arm: cmsis: Convert _ScbDivByZeroFaultEnable to use direct CMSIS register access
Jira: ZEP-1568 Change-Id: I0118f2d44d2b6fb4eac41b0c66b20c5a85e35795 Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
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2 changed files with 1 additions and 16 deletions
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@ -379,7 +379,7 @@ void _FaultInit(void)
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{
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{
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#if defined(CONFIG_ARMV6_M)
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#if defined(CONFIG_ARMV6_M)
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#elif defined(CONFIG_ARMV7_M)
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#elif defined(CONFIG_ARMV7_M)
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_ScbDivByZeroFaultEnable();
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SCB->CCR |= SCB_CCR_DIV_0_TRP_Msk;
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#else
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#else
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#error Unknown ARM architecture
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#error Unknown ARM architecture
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#endif /* CONFIG_ARMV6_M */
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#endif /* CONFIG_ARMV6_M */
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@ -46,21 +46,6 @@ extern "C" {
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#if defined(CONFIG_ARMV6_M)
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#if defined(CONFIG_ARMV6_M)
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#elif defined(CONFIG_ARMV7_M)
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#elif defined(CONFIG_ARMV7_M)
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/**
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*
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* @brief Enable faulting on division by zero
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*
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* This routine enables the divide by zero fault.
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* By default, the CPU ignores the error.
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*
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* @return N/A
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*/
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static inline void _ScbDivByZeroFaultEnable(void)
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{
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__scs.scb.ccr.bit.div_0_trp = 1;
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}
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/**
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/**
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*
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*
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* @brief Find out if a hard fault is caused by a bus error on vector read
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* @brief Find out if a hard fault is caused by a bus error on vector read
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