arm: cmsis: Convert _ScbDivByZeroFaultEnable to use direct CMSIS register access

Jira: ZEP-1568

Change-Id: I0118f2d44d2b6fb4eac41b0c66b20c5a85e35795
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This commit is contained in:
Kumar Gala 2017-01-27 20:40:05 -06:00 committed by Maureen Helm
commit 1a146174cb
2 changed files with 1 additions and 16 deletions

View file

@ -379,7 +379,7 @@ void _FaultInit(void)
{ {
#if defined(CONFIG_ARMV6_M) #if defined(CONFIG_ARMV6_M)
#elif defined(CONFIG_ARMV7_M) #elif defined(CONFIG_ARMV7_M)
_ScbDivByZeroFaultEnable(); SCB->CCR |= SCB_CCR_DIV_0_TRP_Msk;
#else #else
#error Unknown ARM architecture #error Unknown ARM architecture
#endif /* CONFIG_ARMV6_M */ #endif /* CONFIG_ARMV6_M */

View file

@ -46,21 +46,6 @@ extern "C" {
#if defined(CONFIG_ARMV6_M) #if defined(CONFIG_ARMV6_M)
#elif defined(CONFIG_ARMV7_M) #elif defined(CONFIG_ARMV7_M)
/**
*
* @brief Enable faulting on division by zero
*
* This routine enables the divide by zero fault.
* By default, the CPU ignores the error.
*
* @return N/A
*/
static inline void _ScbDivByZeroFaultEnable(void)
{
__scs.scb.ccr.bit.div_0_trp = 1;
}
/** /**
* *
* @brief Find out if a hard fault is caused by a bus error on vector read * @brief Find out if a hard fault is caused by a bus error on vector read