From 1a146174cb340bf69f052fe8c91518dd610e7458 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Fri, 27 Jan 2017 20:40:05 -0600 Subject: [PATCH] arm: cmsis: Convert _ScbDivByZeroFaultEnable to use direct CMSIS register access Jira: ZEP-1568 Change-Id: I0118f2d44d2b6fb4eac41b0c66b20c5a85e35795 Signed-off-by: Kumar Gala --- arch/arm/core/fault.c | 2 +- include/arch/arm/cortex_m/scb.h | 15 --------------- 2 files changed, 1 insertion(+), 16 deletions(-) diff --git a/arch/arm/core/fault.c b/arch/arm/core/fault.c index 6f1069bfc33..347b9b48446 100644 --- a/arch/arm/core/fault.c +++ b/arch/arm/core/fault.c @@ -379,7 +379,7 @@ void _FaultInit(void) { #if defined(CONFIG_ARMV6_M) #elif defined(CONFIG_ARMV7_M) - _ScbDivByZeroFaultEnable(); + SCB->CCR |= SCB_CCR_DIV_0_TRP_Msk; #else #error Unknown ARM architecture #endif /* CONFIG_ARMV6_M */ diff --git a/include/arch/arm/cortex_m/scb.h b/include/arch/arm/cortex_m/scb.h index 123c3e25e26..7394897c57e 100644 --- a/include/arch/arm/cortex_m/scb.h +++ b/include/arch/arm/cortex_m/scb.h @@ -46,21 +46,6 @@ extern "C" { #if defined(CONFIG_ARMV6_M) #elif defined(CONFIG_ARMV7_M) -/** - * - * @brief Enable faulting on division by zero - * - * This routine enables the divide by zero fault. - * By default, the CPU ignores the error. - * - * @return N/A - */ - -static inline void _ScbDivByZeroFaultEnable(void) -{ - __scs.scb.ccr.bit.div_0_trp = 1; -} - /** * * @brief Find out if a hard fault is caused by a bus error on vector read