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riscv32: riscv-privilege: Microsemi Mi-V support

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This commit adds support for Microsemi Mi-V RISC-V softcore CPU
running on the M2GL025 IGLOO2 FPGA development board.

signed-off-by: Karol Gugala <kgugala@antmicro.com>
This commit is contained in:
Karol Gugala 2018-06-10 19:02:14 +02:00 • committed by Anas Nashif
commit 1765d75ff4
19 changed files with 733 additions and 2 deletions
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42
drivers/serial/Kconfig.miv Normal file
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# Kconfig.miv - Mi-V UART configuration option
#
# Copyright (c) 2018 Antmicro <www.antmicro.com>
#
menuconfig UART_MIV
bool "Mi-V serial driver"
depends on SOC_RISCV32_MIV
default n
select SERIAL_HAS_DRIVER
help
This option enables the Mi-V serial driver.
menuconfig UART_MIV_PORT_0
bool "Enable Mi-V Port 0"
default n
depends on UART_MIV
help
This tells the driver to configure the UART port at boot, depending on
the additional configuration options below.
config UART_MIV_PORT_0_NAME
string "Port 0 Device Name"
default "uart0"
depends on UART_MIV_PORT_0
help
This is the device name for UART, and is included in the device
struct.
config UART_MIV_PORT_0_BAUD_RATE
int "Port 0 Baud Rate"
default 0
depends on UART_MIV_PORT_0
help
The baud rate for UART port to be set to at boot.
config UART_MIV_PORT_0_IRQ_PRIORITY
int "Port 0 Interrupt Priority"
default 1
depends on UART_MIV_PORT_0
help
Port 0 Interrupt Priority