riscv32: riscv-privilege: integrate common code
This commit moves code from fe310 platform into RISC-V privilege common folder. This way the code can be reused by other platforms in future. signed-off-by: Karol Gugala <kgugala@antmicro.com>
This commit is contained in:
parent
5417f29def
commit
23a5b5d171
15 changed files with 102 additions and 62 deletions
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@ -1,5 +1,6 @@
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/*
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* Copyright (c) 2016 Jean-Paul Etienne <fractalclone@gmail.com>
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* Contributors: 2018 Antmicro <www.antmicro.com>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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@ -7,7 +8,7 @@
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#include <kernel_structs.h>
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/* exports */
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GTEXT(__start)
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GTEXT(__initialize)
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GTEXT(__reset)
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/* imports */
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@ -16,11 +17,11 @@ GTEXT(_PrepC)
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#if CONFIG_INCLUDE_RESET_VECTOR
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SECTION_FUNC(reset, __reset)
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/*
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* jump to __start
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* use call opcode in case __start is far away.
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* jump to __initialize
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* use call opcode in case __initialize is far away.
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* This will be dependent on linker.ld configuration.
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*/
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call __start
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call __initialize
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#endif /* CONFIG_INCLUDE_RESET_VECTOR */
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/* use ABI name of registers for the sake of simplicity */
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@ -29,7 +30,7 @@ SECTION_FUNC(reset, __reset)
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* Remainder of asm-land initialization code before we can jump into
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* the C domain
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*/
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SECTION_FUNC(TEXT, __start)
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SECTION_FUNC(TEXT, __initialize)
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#ifdef CONFIG_INIT_STACKS
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/* Pre-populate all bytes in _interrupt_stack with 0xAA */
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la t0, _interrupt_stack
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@ -1,11 +1,15 @@
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/*
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* Copyright (c) 2016 Jean-Paul Etienne <fractalclone@gmail.com>
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* Contributors: 2018 Antmicro <www.antmicro.com>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <toolchain.h>
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/* exports */
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GTEXT(__start)
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/* imports */
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GTEXT(__reset)
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GTEXT(__irq_wrapper)
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@ -35,7 +39,7 @@ GTEXT(__irq_wrapper)
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* ECALL Instruction 0x00000088
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* Invalid Memory Access 0x0000008C
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*/
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SECTION_FUNC(vectors, vinit)
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SECTION_FUNC(vectors, __start)
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.option norvc;
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/* nop addr 0x00000000 - 0x00000058 */
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@ -1,6 +1,11 @@
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zephyr_include_directories(.)
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zephyr_sources(
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idle.c
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soc_irq.S
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soc_common_irq.c
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)
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if(NOT(CONFIG_SOC_SERIES_RISCV32_QEMU))
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zephyr_sources(vector.S)
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endif()
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@ -1,5 +1,6 @@
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/*
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* Copyright (c) 2017 Jean-Paul Etienne <fractalclone@gmail.com>
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* Contributors: 2018 Antmicro <www.antmicro.com>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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@ -10,7 +11,7 @@
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#include <logging/kernel_event_logger.h>
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static ALWAYS_INLINE void fe310_idle(unsigned int key)
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static ALWAYS_INLINE void riscv_idle(unsigned int key)
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{
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#ifdef CONFIG_KERNEL_EVENT_LOGGER_SLEEP
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_sys_k_event_logger_enter_sleep();
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@ -34,7 +35,7 @@ static ALWAYS_INLINE void fe310_idle(unsigned int key)
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*/
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void k_cpu_idle(void)
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{
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fe310_idle(SOC_MSTATUS_IEN);
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riscv_idle(SOC_MSTATUS_IEN);
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}
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/**
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@ -56,5 +57,5 @@ void k_cpu_idle(void)
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*/
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void k_cpu_atomic_idle(unsigned int key)
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{
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fe310_idle(key);
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riscv_idle(key);
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}
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@ -1,16 +1,20 @@
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/*
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* Copyright (c) 2017 Jean-Paul Etienne <fractalclone@gmail.com>
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* Contributors: 2018 Antmicro <www.antmicro.com>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <toolchain.h>
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/* imports */
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/* exports */
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GTEXT(__start)
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/* imports */
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GTEXT(__initialize)
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GTEXT(__irq_wrapper)
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SECTION_FUNC(vectors, vinit)
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SECTION_FUNC(vectors, __start)
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.option norvc;
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/*
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la t0, __irq_wrapper
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csrw mtvec, t0
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/* Jump to __start */
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tail __start
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/* Jump to __initialize */
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tail __initialize
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@ -1,4 +1 @@
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zephyr_sources(
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vector.S
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fe310_idle.c
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)
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zephyr_sources()
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@ -1,11 +1,15 @@
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/*
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* Copyright (c) 2016 Jean-Paul Etienne <fractalclone@gmail.com>
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* Contributors: 2018 Antmicro <www.antmicro.com>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <toolchain.h>
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/* exports */
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GTEXT(__start)
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/* imports */
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GTEXT(__reset)
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GTEXT(__irq_wrapper)
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@ -19,7 +23,7 @@ GTEXT(__irq_wrapper)
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*
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* Call __irq_wrapper to handle all interrupts/exceptions/faults
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*/
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SECTION_FUNC(vectors, vinit)
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SECTION_FUNC(vectors, __start)
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.option norvc;
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/*
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@ -11,7 +11,7 @@ CONFIG_UART_FE310_PORT_0_BAUD_RATE=115200
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CONFIG_UART_FE310_PORT_0_NAME="uart0"
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CONFIG_UART_CONSOLE=y
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CONFIG_UART_CONSOLE_ON_DEV_NAME="uart0"
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CONFIG_PLIC_FE310=y
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CONFIG_PLIC=y
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CONFIG_PINMUX=y
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CONFIG_PINMUX_FE310=y
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CONFIG_RISCV_MACHINE_TIMER=y
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@ -4,7 +4,7 @@ zephyr_sources_ifdef(CONFIG_LOAPIC loapic_intr.c system_apic.c)
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zephyr_sources_ifdef(CONFIG_LOAPIC_SPURIOUS_VECTOR loapic_spurious.c)
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zephyr_sources_ifdef(CONFIG_MVIC mvic.c)
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zephyr_sources_ifdef(CONFIG_PIC_DISABLE i8259.c)
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zephyr_sources_ifdef(CONFIG_PLIC_FE310 plic_fe310.c)
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zephyr_sources_ifdef(CONFIG_PLIC plic.c)
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zephyr_sources_ifdef(CONFIG_SHARED_IRQ shared_irq.c)
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zephyr_sources_ifdef(CONFIG_SOC_FAMILY_STM32 exti_stm32.c)
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zephyr_sources_ifdef(CONFIG_CAVS_ICTL cavs_ictl.c)
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@ -116,14 +116,14 @@ config ARCV2_INTERRUPT_UNIT
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building a processor, you can configure the processor to include an
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interrupt unit. The ARCv2 interrupt unit is highly programmable.
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config PLIC_FE310
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bool "SiFive Freedom E310 Platform Level Interrupt Controller (PLIC)"
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config PLIC
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bool "Platform Level Interrupt Controller (PLIC)"
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default y
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depends on SOC_RISCV32_FE310 && !QEMU_TARGET
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depends on SOC_FAMILY_RISCV_PRIVILEGE && !QEMU_TARGET
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select RISCV_HAS_PLIC
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help
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SiFive Freedom E310 Platform Level Interrupt Controller provides support
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for external interrupt lines defined by the FE310 SOC;
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Platform Level Interrupt Controller provides support
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for external interrupt lines defined by the RISC-V SoC;
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config DW_ICTL
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bool "Designware Interrupt Controller"
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/*
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* Copyright (c) 2017 Jean-Paul Etienne <fractalclone@gmail.com>
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* Contributors: 2018 Antmicro <www.antmicro.com>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @brief Platform Level Interrupt Controller (PLIC) driver
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* for the SiFive Freedom E310 processor
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* for the RISC-V processors
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*/
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#include <kernel.h>
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#include <arch/cpu.h>
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#include <init.h>
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#include <soc.h>
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#include "plic.h"
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#include <sw_isr_table.h>
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#define PLIC_FE310_IRQS (CONFIG_NUM_IRQS - RISCV_MAX_GENERIC_IRQ)
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#define PLIC_FE310_EN_SIZE ((PLIC_FE310_IRQS >> 5) + 1)
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struct plic_fe310_regs_t {
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struct plic_regs_t {
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u32_t threshold_prio;
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u32_t claim_complete;
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};
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void riscv_plic_irq_enable(u32_t irq)
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{
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u32_t key;
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u32_t fe310_irq = irq - RISCV_MAX_GENERIC_IRQ;
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u32_t plic_irq = irq - RISCV_MAX_GENERIC_IRQ;
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volatile u32_t *en =
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(volatile u32_t *)FE310_PLIC_IRQ_EN_BASE_ADDR;
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(volatile u32_t *)PLIC_IRQ_EN_BASE_ADDR;
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key = irq_lock();
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en += (fe310_irq >> 5);
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*en |= (1 << (fe310_irq & 31));
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en += (plic_irq >> 5);
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*en |= (1 << (plic_irq & 31));
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irq_unlock(key);
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}
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void riscv_plic_irq_disable(u32_t irq)
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{
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u32_t key;
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u32_t fe310_irq = irq - RISCV_MAX_GENERIC_IRQ;
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u32_t plic_irq = irq - RISCV_MAX_GENERIC_IRQ;
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volatile u32_t *en =
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(volatile u32_t *)FE310_PLIC_IRQ_EN_BASE_ADDR;
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(volatile u32_t *)PLIC_IRQ_EN_BASE_ADDR;
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key = irq_lock();
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en += (fe310_irq >> 5);
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*en &= ~(1 << (fe310_irq & 31));
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en += (plic_irq >> 5);
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*en &= ~(1 << (plic_irq & 31));
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irq_unlock(key);
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}
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int riscv_plic_irq_is_enabled(u32_t irq)
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{
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volatile u32_t *en =
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(volatile u32_t *)FE310_PLIC_IRQ_EN_BASE_ADDR;
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u32_t fe310_irq = irq - RISCV_MAX_GENERIC_IRQ;
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(volatile u32_t *)PLIC_IRQ_EN_BASE_ADDR;
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u32_t plic_irq = irq - RISCV_MAX_GENERIC_IRQ;
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en += (fe310_irq >> 5);
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return !!(*en & (1 << (fe310_irq & 31)));
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en += (plic_irq >> 5);
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return !!(*en & (1 << (plic_irq & 31)));
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}
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/**
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@ -110,14 +109,14 @@ int riscv_plic_irq_is_enabled(u32_t irq)
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void riscv_plic_set_priority(u32_t irq, u32_t priority)
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{
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volatile u32_t *prio =
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(volatile u32_t *)FE310_PLIC_PRIO_BASE_ADDR;
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(volatile u32_t *)PLIC_PRIO_BASE_ADDR;
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/* Can set priority only for PLIC-specific interrupt line */
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if (irq <= RISCV_MAX_GENERIC_IRQ)
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return;
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if (priority > FE310_PLIC_MAX_PRIORITY)
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priority = FE310_PLIC_MAX_PRIORITY;
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if (priority > PLIC_MAX_PRIORITY)
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priority = PLIC_MAX_PRIORITY;
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prio += (irq - RISCV_MAX_GENERIC_IRQ);
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*prio = priority;
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@ -138,10 +137,10 @@ int riscv_plic_get_irq(void)
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return save_irq;
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}
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static void plic_fe310_irq_handler(void *arg)
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static void plic_irq_handler(void *arg)
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{
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volatile struct plic_fe310_regs_t *regs =
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(volatile struct plic_fe310_regs_t *)FE310_PLIC_REG_BASE_ADDR;
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volatile struct plic_regs_t *regs =
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(volatile struct plic_regs_t *)PLIC_REG_BASE_ADDR;
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u32_t irq;
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struct _isr_table_entry *ite;
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@ -161,7 +160,7 @@ static void plic_fe310_irq_handler(void *arg)
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* If the IRQ is out of range, call _irq_spurious.
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* A call to _irq_spurious will not return.
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*/
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if (irq == 0 || irq >= PLIC_FE310_IRQS)
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if (irq == 0 || irq >= PLIC_IRQS)
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_irq_spurious(NULL);
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irq += RISCV_MAX_GENERIC_IRQ;
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@ -179,29 +178,29 @@ static void plic_fe310_irq_handler(void *arg)
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/**
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*
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* @brief Initialize the SiFive FE310 Platform Level Interrupt Controller
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* @brief Initialize the Platform Level Interrupt Controller
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* @return N/A
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*/
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static int plic_fe310_init(struct device *dev)
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static int plic_init(struct device *dev)
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{
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ARG_UNUSED(dev);
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volatile u32_t *en =
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(volatile u32_t *)FE310_PLIC_IRQ_EN_BASE_ADDR;
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(volatile u32_t *)PLIC_IRQ_EN_BASE_ADDR;
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volatile u32_t *prio =
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(volatile u32_t *)FE310_PLIC_PRIO_BASE_ADDR;
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volatile struct plic_fe310_regs_t *regs =
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(volatile struct plic_fe310_regs_t *)FE310_PLIC_REG_BASE_ADDR;
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(volatile u32_t *)PLIC_PRIO_BASE_ADDR;
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volatile struct plic_regs_t *regs =
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(volatile struct plic_regs_t *)PLIC_REG_BASE_ADDR;
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int i;
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/* Ensure that all interrupts are disabled initially */
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for (i = 0; i < PLIC_FE310_EN_SIZE; i++) {
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for (i = 0; i < PLIC_EN_SIZE; i++) {
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*en = 0;
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en++;
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}
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/* Set priority of each interrupt line to 0 initially */
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for (i = 0; i < PLIC_FE310_IRQS; i++) {
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for (i = 0; i < PLIC_IRQS; i++) {
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*prio = 0;
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prio++;
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}
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@ -212,7 +211,7 @@ static int plic_fe310_init(struct device *dev)
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/* Setup IRQ handler for PLIC driver */
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IRQ_CONNECT(RISCV_MACHINE_EXT_IRQ,
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0,
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plic_fe310_irq_handler,
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plic_irq_handler,
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NULL,
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0);
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@ -222,4 +221,4 @@ static int plic_fe310_init(struct device *dev)
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return 0;
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}
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SYS_INIT(plic_fe310_init, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);
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SYS_INIT(plic_init, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);
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23
drivers/interrupt_controller/plic.h
Normal file
23
drivers/interrupt_controller/plic.h
Normal file
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@ -0,0 +1,23 @@
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/*
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* Copyright (c) 2018 Antmicro <www.antmicro.com>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef __PLIC_H_
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#define __PLIC_H_
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#include <soc.h>
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#define PLIC_IRQS (CONFIG_NUM_IRQS - RISCV_MAX_GENERIC_IRQ)
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#define PLIC_EN_SIZE ((PLIC_IRQS >> 5) + 1)
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/* FE310 definitons for the PLIC */
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#if defined(CONFIG_SOC_SERIES_RISCV32_FE310)
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#define PLIC_REG_BASE_ADDR FE310_PLIC_REG_BASE_ADDR
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#define PLIC_IRQ_EN_BASE_ADDR FE310_PLIC_IRQ_EN_BASE_ADDR
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#define PLIC_PRIO_BASE_ADDR FE310_PLIC_PRIO_BASE_ADDR
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#define PLIC_MAX_PRIORITY FE310_PLIC_MAX_PRIORITY
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#endif
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#endif
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@ -1,5 +1,6 @@
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/*
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* Copyright (c) 2016 Jean-Paul Etienne <fractalclone@gmail.com>
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* Contributors: 2018 Antmicro <www.antmicro.com>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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@ -128,8 +129,8 @@ extern u32_t _timer_cycle_get_32(void);
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#include <arch/riscv32/pulpino/asm_inline.h>
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#elif defined(CONFIG_SOC_RISCV32_QEMU)
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#include <arch/riscv32/riscv32-qemu/asm_inline.h>
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#elif defined(CONFIG_SOC_RISCV32_FE310)
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#include <arch/riscv32/fe310/asm_inline.h>
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#elif defined(CONFIG_SOC_FAMILY_RISCV_PRIVILEGE)
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#include <arch/riscv32/riscv-privilege/asm_inline.h>
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#endif
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#ifdef __cplusplus
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@ -1,5 +1,6 @@
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/*
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* Copyright (c) 2017 Jean-Paul Etienne <fractalclone@gmail.com>
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* Contributors: 2018 Antmicro <www.antmicro.com>
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*
|
||||
* SPDX-License-Identifier: Apache-2.0
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*/
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@ -13,7 +14,7 @@
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*/
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|
||||
#if defined(__GNUC__)
|
||||
#include <arch/riscv32/fe310/asm_inline_gcc.h>
|
||||
#include <arch/riscv32/riscv-privilege/asm_inline_gcc.h>
|
||||
#else
|
||||
#error "Supports only GNU C compiler"
|
||||
#endif
|
Loading…
Add table
Add a link
Reference in a new issue