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riscv32: riscv-privilege: integrate common code

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This commit moves code from fe310 platform into RISC-V privilege common
folder. This way the code can be reused by other platforms in future.

signed-off-by: Karol Gugala <kgugala@antmicro.com>
This commit is contained in:
Karol Gugala 2018-06-10 19:02:14 +02:00 • committed by Anas Nashif
commit 23a5b5d171
15 changed files with 102 additions and 62 deletions
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11
arch/riscv32/core/reset.S
View file

@ -1,5 +1,6 @@
/*
* Copyright (c) 2016 Jean-Paul Etienne <fractalclone@gmail.com>
* Contributors: 2018 Antmicro <www.antmicro.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -7,7 +8,7 @@
#include <kernel_structs.h>
/* exports */
GTEXT(__start)
GTEXT(__initialize)
GTEXT(__reset)
/* imports */
@ -16,11 +17,11 @@ GTEXT(_PrepC)
#if CONFIG_INCLUDE_RESET_VECTOR
SECTION_FUNC(reset, __reset)
/*
* jump to __start
* use call opcode in case __start is far away.
* jump to __initialize
* use call opcode in case __initialize is far away.
* This will be dependent on linker.ld configuration.
*/
call __start
call __initialize
#endif /* CONFIG_INCLUDE_RESET_VECTOR */
/* use ABI name of registers for the sake of simplicity */
@ -29,7 +30,7 @@ SECTION_FUNC(reset, __reset)
* Remainder of asm-land initialization code before we can jump into
* the C domain
*/
SECTION_FUNC(TEXT, __start)
SECTION_FUNC(TEXT, __initialize)
#ifdef CONFIG_INIT_STACKS
/* Pre-populate all bytes in _interrupt_stack with 0xAA */
la t0, _interrupt_stack

6
arch/riscv32/soc/pulpino/vector.S
View file

@ -1,11 +1,15 @@
/*
* Copyright (c) 2016 Jean-Paul Etienne <fractalclone@gmail.com>
* Contributors: 2018 Antmicro <www.antmicro.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <toolchain.h>
/* exports */
GTEXT(__start)
/* imports */
GTEXT(__reset)
GTEXT(__irq_wrapper)
@ -35,7 +39,7 @@ GTEXT(__irq_wrapper)
* ECALL Instruction 0x00000088
* Invalid Memory Access 0x0000008C
*/
SECTION_FUNC(vectors, vinit)
SECTION_FUNC(vectors, __start)
.option norvc;
/* nop addr 0x00000000 - 0x00000058 */

5
arch/riscv32/soc/riscv-privilege/common/CMakeLists.txt
View file

@ -1,6 +1,11 @@
zephyr_include_directories(.)
zephyr_sources(
idle.c
soc_irq.S
soc_common_irq.c
)
if(NOT(CONFIG_SOC_SERIES_RISCV32_QEMU))
zephyr_sources(vector.S)
endif()

7
arch/riscv32/soc/riscv-privilege/fe310/fe310_idle.c → arch/riscv32/soc/riscv-privilege/common/idle.c
View file

@ -1,5 +1,6 @@
/*
* Copyright (c) 2017 Jean-Paul Etienne <fractalclone@gmail.com>
* Contributors: 2018 Antmicro <www.antmicro.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -10,7 +11,7 @@
#include <logging/kernel_event_logger.h>
static ALWAYS_INLINE void fe310_idle(unsigned int key)
static ALWAYS_INLINE void riscv_idle(unsigned int key)
{
#ifdef CONFIG_KERNEL_EVENT_LOGGER_SLEEP
_sys_k_event_logger_enter_sleep();
@ -34,7 +35,7 @@ static ALWAYS_INLINE void fe310_idle(unsigned int key)
*/
void k_cpu_idle(void)
{
fe310_idle(SOC_MSTATUS_IEN);
riscv_idle(SOC_MSTATUS_IEN);
}
/**
@ -56,5 +57,5 @@ void k_cpu_idle(void)
*/
void k_cpu_atomic_idle(unsigned int key)
{
fe310_idle(key);
riscv_idle(key);
}

12
arch/riscv32/soc/riscv-privilege/fe310/vector.S → arch/riscv32/soc/riscv-privilege/common/vector.S
View file

@ -1,16 +1,20 @@
/*
* Copyright (c) 2017 Jean-Paul Etienne <fractalclone@gmail.com>
* Contributors: 2018 Antmicro <www.antmicro.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <toolchain.h>
/* imports */
/* exports */
GTEXT(__start)
/* imports */
GTEXT(__initialize)
GTEXT(__irq_wrapper)
SECTION_FUNC(vectors, vinit)
SECTION_FUNC(vectors, __start)
.option norvc;
/*
@ -20,5 +24,5 @@ SECTION_FUNC(vectors, vinit)
la t0, __irq_wrapper
csrw mtvec, t0
/* Jump to __start */
tail __start
/* Jump to __initialize */
tail __initialize

5
arch/riscv32/soc/riscv-privilege/fe310/CMakeLists.txt
View file

@ -1,4 +1 @@
zephyr_sources(
vector.S
fe310_idle.c
)
zephyr_sources()

6
arch/riscv32/soc/riscv-privilege/riscv32-qemu/vector.S
View file

@ -1,11 +1,15 @@
/*
* Copyright (c) 2016 Jean-Paul Etienne <fractalclone@gmail.com>
* Contributors: 2018 Antmicro <www.antmicro.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <toolchain.h>
/* exports */
GTEXT(__start)
/* imports */
GTEXT(__reset)
GTEXT(__irq_wrapper)
@ -19,7 +23,7 @@ GTEXT(__irq_wrapper)
*
* Call __irq_wrapper to handle all interrupts/exceptions/faults
*/
SECTION_FUNC(vectors, vinit)
SECTION_FUNC(vectors, __start)
.option norvc;
/*

2
boards/riscv32/hifive1/hifive1_defconfig
View file

@ -11,7 +11,7 @@ CONFIG_UART_FE310_PORT_0_BAUD_RATE=115200
CONFIG_UART_FE310_PORT_0_NAME="uart0"
CONFIG_UART_CONSOLE=y
CONFIG_UART_CONSOLE_ON_DEV_NAME="uart0"
CONFIG_PLIC_FE310=y
CONFIG_PLIC=y
CONFIG_PINMUX=y
CONFIG_PINMUX_FE310=y
CONFIG_RISCV_MACHINE_TIMER=y

2
drivers/interrupt_controller/CMakeLists.txt
View file

@ -4,7 +4,7 @@ zephyr_sources_ifdef(CONFIG_LOAPIC loapic_intr.c system_apic.c)
zephyr_sources_ifdef(CONFIG_LOAPIC_SPURIOUS_VECTOR loapic_spurious.c)
zephyr_sources_ifdef(CONFIG_MVIC mvic.c)
zephyr_sources_ifdef(CONFIG_PIC_DISABLE i8259.c)
zephyr_sources_ifdef(CONFIG_PLIC_FE310 plic_fe310.c)
zephyr_sources_ifdef(CONFIG_PLIC plic.c)
zephyr_sources_ifdef(CONFIG_SHARED_IRQ shared_irq.c)
zephyr_sources_ifdef(CONFIG_SOC_FAMILY_STM32 exti_stm32.c)
zephyr_sources_ifdef(CONFIG_CAVS_ICTL cavs_ictl.c)

10
drivers/interrupt_controller/Kconfig
View file

@ -116,14 +116,14 @@ config ARCV2_INTERRUPT_UNIT
building a processor, you can configure the processor to include an
interrupt unit. The ARCv2 interrupt unit is highly programmable.
config PLIC_FE310
bool "SiFive Freedom E310 Platform Level Interrupt Controller (PLIC)"
config PLIC
bool "Platform Level Interrupt Controller (PLIC)"
default y
depends on SOC_RISCV32_FE310 && !QEMU_TARGET
depends on SOC_FAMILY_RISCV_PRIVILEGE && !QEMU_TARGET
select RISCV_HAS_PLIC
help
SiFive Freedom E310 Platform Level Interrupt Controller provides support
for external interrupt lines defined by the FE310 SOC;
Platform Level Interrupt Controller provides support
for external interrupt lines defined by the RISC-V SoC;
config DW_ICTL
bool "Designware Interrupt Controller"

67
drivers/interrupt_controller/plic_fe310.c → drivers/interrupt_controller/plic.c
View file

@ -1,24 +1,23 @@
/*
* Copyright (c) 2017 Jean-Paul Etienne <fractalclone@gmail.com>
* Contributors: 2018 Antmicro <www.antmicro.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @brief Platform Level Interrupt Controller (PLIC) driver
* for the SiFive Freedom E310 processor
* for the RISC-V processors
*/
#include <kernel.h>
#include <arch/cpu.h>
#include <init.h>
#include <soc.h>
#include "plic.h"
#include <sw_isr_table.h>
#define PLIC_FE310_IRQS (CONFIG_NUM_IRQS - RISCV_MAX_GENERIC_IRQ)
#define PLIC_FE310_EN_SIZE ((PLIC_FE310_IRQS >> 5) + 1)
struct plic_fe310_regs_t {
struct plic_regs_t {
u32_t threshold_prio;
u32_t claim_complete;
};
@ -41,13 +40,13 @@ static int save_irq;
void riscv_plic_irq_enable(u32_t irq)
{
u32_t key;
u32_t fe310_irq = irq - RISCV_MAX_GENERIC_IRQ;
u32_t plic_irq = irq - RISCV_MAX_GENERIC_IRQ;
volatile u32_t *en =
(volatile u32_t *)FE310_PLIC_IRQ_EN_BASE_ADDR;
(volatile u32_t *)PLIC_IRQ_EN_BASE_ADDR;
key = irq_lock();
en += (fe310_irq >> 5);
*en |= (1 << (fe310_irq & 31));
en += (plic_irq >> 5);
*en |= (1 << (plic_irq & 31));
irq_unlock(key);
}
@ -67,13 +66,13 @@ void riscv_plic_irq_enable(u32_t irq)
void riscv_plic_irq_disable(u32_t irq)
{
u32_t key;
u32_t fe310_irq = irq - RISCV_MAX_GENERIC_IRQ;
u32_t plic_irq = irq - RISCV_MAX_GENERIC_IRQ;
volatile u32_t *en =
(volatile u32_t *)FE310_PLIC_IRQ_EN_BASE_ADDR;
(volatile u32_t *)PLIC_IRQ_EN_BASE_ADDR;
key = irq_lock();
en += (fe310_irq >> 5);
*en &= ~(1 << (fe310_irq & 31));
en += (plic_irq >> 5);
*en &= ~(1 << (plic_irq & 31));
irq_unlock(key);
}
@ -89,11 +88,11 @@ void riscv_plic_irq_disable(u32_t irq)
int riscv_plic_irq_is_enabled(u32_t irq)
{
volatile u32_t *en =
(volatile u32_t *)FE310_PLIC_IRQ_EN_BASE_ADDR;
u32_t fe310_irq = irq - RISCV_MAX_GENERIC_IRQ;
(volatile u32_t *)PLIC_IRQ_EN_BASE_ADDR;
u32_t plic_irq = irq - RISCV_MAX_GENERIC_IRQ;
en += (fe310_irq >> 5);
return !!(*en & (1 << (fe310_irq & 31)));
en += (plic_irq >> 5);
return !!(*en & (1 << (plic_irq & 31)));
}
/**
@ -110,14 +109,14 @@ int riscv_plic_irq_is_enabled(u32_t irq)
void riscv_plic_set_priority(u32_t irq, u32_t priority)
{
volatile u32_t *prio =
(volatile u32_t *)FE310_PLIC_PRIO_BASE_ADDR;
(volatile u32_t *)PLIC_PRIO_BASE_ADDR;
/* Can set priority only for PLIC-specific interrupt line */
if (irq <= RISCV_MAX_GENERIC_IRQ)
return;
if (priority > FE310_PLIC_MAX_PRIORITY)
priority = FE310_PLIC_MAX_PRIORITY;
if (priority > PLIC_MAX_PRIORITY)
priority = PLIC_MAX_PRIORITY;
prio += (irq - RISCV_MAX_GENERIC_IRQ);
*prio = priority;
@ -138,10 +137,10 @@ int riscv_plic_get_irq(void)
return save_irq;
}
static void plic_fe310_irq_handler(void *arg)
static void plic_irq_handler(void *arg)
{
volatile struct plic_fe310_regs_t *regs =
(volatile struct plic_fe310_regs_t *)FE310_PLIC_REG_BASE_ADDR;
volatile struct plic_regs_t *regs =
(volatile struct plic_regs_t *)PLIC_REG_BASE_ADDR;
u32_t irq;
struct _isr_table_entry *ite;
@ -161,7 +160,7 @@ static void plic_fe310_irq_handler(void *arg)
* If the IRQ is out of range, call _irq_spurious.
* A call to _irq_spurious will not return.
*/
if (irq == 0 || irq >= PLIC_FE310_IRQS)
if (irq == 0 || irq >= PLIC_IRQS)
_irq_spurious(NULL);
irq += RISCV_MAX_GENERIC_IRQ;
@ -179,29 +178,29 @@ static void plic_fe310_irq_handler(void *arg)
/**
*
* @brief Initialize the SiFive FE310 Platform Level Interrupt Controller
* @brief Initialize the Platform Level Interrupt Controller
* @return N/A
*/
static int plic_fe310_init(struct device *dev)
static int plic_init(struct device *dev)
{
ARG_UNUSED(dev);
volatile u32_t *en =
(volatile u32_t *)FE310_PLIC_IRQ_EN_BASE_ADDR;
(volatile u32_t *)PLIC_IRQ_EN_BASE_ADDR;
volatile u32_t *prio =
(volatile u32_t *)FE310_PLIC_PRIO_BASE_ADDR;
volatile struct plic_fe310_regs_t *regs =
(volatile struct plic_fe310_regs_t *)FE310_PLIC_REG_BASE_ADDR;
(volatile u32_t *)PLIC_PRIO_BASE_ADDR;
volatile struct plic_regs_t *regs =
(volatile struct plic_regs_t *)PLIC_REG_BASE_ADDR;
int i;
/* Ensure that all interrupts are disabled initially */
for (i = 0; i < PLIC_FE310_EN_SIZE; i++) {
for (i = 0; i < PLIC_EN_SIZE; i++) {
*en = 0;
en++;
}
/* Set priority of each interrupt line to 0 initially */
for (i = 0; i < PLIC_FE310_IRQS; i++) {
for (i = 0; i < PLIC_IRQS; i++) {
*prio = 0;
prio++;
}
@ -212,7 +211,7 @@ static int plic_fe310_init(struct device *dev)
/* Setup IRQ handler for PLIC driver */
IRQ_CONNECT(RISCV_MACHINE_EXT_IRQ,
0,
plic_fe310_irq_handler,
plic_irq_handler,
NULL,
0);
@ -222,4 +221,4 @@ static int plic_fe310_init(struct device *dev)
return 0;
}
SYS_INIT(plic_fe310_init, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);
SYS_INIT(plic_init, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);

23
drivers/interrupt_controller/plic.h Normal file
View file

@ -0,0 +1,23 @@
/*
* Copyright (c) 2018 Antmicro <www.antmicro.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef __PLIC_H_
#define __PLIC_H_
#include <soc.h>
#define PLIC_IRQS (CONFIG_NUM_IRQS - RISCV_MAX_GENERIC_IRQ)
#define PLIC_EN_SIZE ((PLIC_IRQS >> 5) + 1)
/* FE310 definitons for the PLIC */
#if defined(CONFIG_SOC_SERIES_RISCV32_FE310)
#define PLIC_REG_BASE_ADDR FE310_PLIC_REG_BASE_ADDR
#define PLIC_IRQ_EN_BASE_ADDR FE310_PLIC_IRQ_EN_BASE_ADDR
#define PLIC_PRIO_BASE_ADDR FE310_PLIC_PRIO_BASE_ADDR
#define PLIC_MAX_PRIORITY FE310_PLIC_MAX_PRIORITY
#endif
#endif

5
include/arch/riscv32/arch.h
View file

@ -1,5 +1,6 @@
/*
* Copyright (c) 2016 Jean-Paul Etienne <fractalclone@gmail.com>
* Contributors: 2018 Antmicro <www.antmicro.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -128,8 +129,8 @@ extern u32_t _timer_cycle_get_32(void);
#include <arch/riscv32/pulpino/asm_inline.h>
#elif defined(CONFIG_SOC_RISCV32_QEMU)
#include <arch/riscv32/riscv32-qemu/asm_inline.h>
#elif defined(CONFIG_SOC_RISCV32_FE310)
#include <arch/riscv32/fe310/asm_inline.h>
#elif defined(CONFIG_SOC_FAMILY_RISCV_PRIVILEGE)
#include <arch/riscv32/riscv-privilege/asm_inline.h>
#endif
#ifdef __cplusplus

3
include/arch/riscv32/fe310/asm_inline.h → include/arch/riscv32/riscv-privilege/asm_inline.h
View file

@ -1,5 +1,6 @@
/*
* Copyright (c) 2017 Jean-Paul Etienne <fractalclone@gmail.com>
* Contributors: 2018 Antmicro <www.antmicro.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -13,7 +14,7 @@
*/
#if defined(__GNUC__)
#include <arch/riscv32/fe310/asm_inline_gcc.h>
#include <arch/riscv32/riscv-privilege/asm_inline_gcc.h>
#else
#error "Supports only GNU C compiler"
#endif

0
include/arch/riscv32/fe310/asm_inline_gcc.h → include/arch/riscv32/riscv-privilege/asm_inline_gcc.h
View file