soc: polarfire: split into cpu clusters

Split Polarfire SoC into CPU clusters as they have different
capabilities.

Signed-off-by: Andrzej Drabarek <adrabarek@antmicro.com>

boards/beagle/beaglev_fire/Kconfig

@@ -1,7 +0,0 @@
-# Copyright (c) 2023 Microchip Technology Inc
-# SPDX-License-Identifier: Apache-2.0
-
-config BOARD_BEAGLEV_FIRE
-	select 64BIT
-	select SCHED_IPI_SUPPORTED
-	select CPU_HAS_FPU_DOUBLE_PRECISION

boards/beagle/beaglev_fire/Kconfig.beaglev_fire

@@ -2,4 +2,6 @@
 # SPDX-License-Identifier: Apache-2.0
 
 config BOARD_BEAGLEV_FIRE
-	select SOC_POLARFIRE
+	select SOC_POLARFIRE_U54 if BOARD_BEAGLEV_FIRE_POLARFIRE_U54 || \
+				       BOARD_BEAGLEV_FIRE_POLARFIRE_U54_SMP
+	select SOC_POLARFIRE_E51 if BOARD_BEAGLEV_FIRE_POLARFIRE_E51

boards/beagle/beaglev_fire/beaglev_fire_common.dtsi

@@ -10,22 +10,10 @@
 #include <mem.h>
 
 / {
-	model = "BeagleV-Fire";
+	model = "beagle,beaglev-fire";
 	compatible = "beagle,beaglev-fire", "microchip,mpfs";
 	aliases {
 	};
-
-	chosen {
-		zephyr,console = &uart0;
-		zephyr,shell-uart = &uart0;
-		zephyr,sram = &sram1;
-	};
-};
-
-&uart0 {
-	status = "okay";
-	current-speed = <115200>;
-	clock-frequency = <150000000>;
 };
 
 &gpio2 {

boards/beagle/beaglev_fire/beaglev_fire_defconfig

@@ -10,4 +10,3 @@ CONFIG_UART_CONSOLE=y
 CONFIG_XIP=n
 CONFIG_INIT_STACKS=y
 CONFIG_SYS_CLOCK_TICKS_PER_SEC=1000
-CONFIG_FPU=n

boards/beagle/beaglev_fire/beaglev_fire_polarfire_e51.dts

@@ -0,0 +1,36 @@
+/dts-v1/;
+#include "beaglev_fire_common.dtsi"
+
+/ {
+	compatible = "beagle,beaglev-fire", "microchip,mpfs";
+
+	cpus {
+		cpu@1 {
+			status = "disabled";
+		};
+
+		cpu@2 {
+			status = "disabled";
+		};
+
+		cpu@3 {
+			status = "disabled";
+		};
+
+		cpu@4 {
+			status = "disabled";
+		};
+	};
+
+	chosen {
+		zephyr,console = &uart0;
+		zephyr,shell-uart = &uart0;
+		zephyr,sram = &sram1;
+	};
+};
+
+&uart0 {
+	status = "okay";
+	current-speed = <115200>;
+	clock-frequency = <150000000>;
+};

boards/beagle/beaglev_fire/beaglev_fire_polarfire_e51.yaml

@@ -1,4 +1,4 @@
-identifier: beaglev_fire
+identifier: beaglev_fire/polarfire/e51
 name: Beagleboard BeagleV-Fire
 type: mcu
 arch: riscv

boards/beagle/beaglev_fire/beaglev_fire_polarfire_e51_defconfig

@@ -0,0 +1,12 @@
+# Copyright (c) 2023 Microchip Technology Inc
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_MPFS_HAL=n
+CONFIG_BASE64=y
+CONFIG_INCLUDE_RESET_VECTOR=y
+CONFIG_CONSOLE=y
+CONFIG_SERIAL=y
+CONFIG_UART_CONSOLE=y
+CONFIG_XIP=n
+CONFIG_INIT_STACKS=y
+CONFIG_SYS_CLOCK_TICKS_PER_SEC=1000

boards/beagle/beaglev_fire/beaglev_fire_polarfire_u54.dts

@@ -0,0 +1,25 @@
+/dts-v1/;
+#include "beaglev_fire_common.dtsi"
+
+/ {
+	model = "beagle,beaglev-fire";
+	compatible = "beagle,beaglev-fire", "microchip,mpfs";
+
+	chosen {
+		zephyr,console = &uart1;
+		zephyr,shell-uart = &uart1;
+		zephyr,sram = &sram1;
+	};
+
+	cpus {
+		cpu@0 {
+			status = "disabled";
+		};
+	};
+};
+
+&uart1 {
+	status = "okay";
+	current-speed = <115200>;
+	clock-frequency = <150000000>;
+};

boards/beagle/beaglev_fire/beaglev_fire_polarfire_u54.yaml

@@ -0,0 +1,12 @@
+identifier: beaglev_fire/polarfire/u54
+name: Beagleboard BeagleV-Fire
+type: mcu
+arch: riscv
+toolchain:
+  - zephyr
+ram: 3840
+testing:
+  ignore_tags:
+    - net
+    - bluetooth
+vendor: beagle

boards/beagle/beaglev_fire/beaglev_fire_polarfire_u54_defconfig

@@ -0,0 +1,13 @@
+# Copyright (c) 2023 Microchip Technology Inc
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_MPFS_HAL=n
+CONFIG_BASE64=y
+CONFIG_INCLUDE_RESET_VECTOR=y
+CONFIG_CONSOLE=y
+CONFIG_SERIAL=y
+CONFIG_UART_CONSOLE=y
+CONFIG_XIP=n
+CONFIG_INIT_STACKS=y
+CONFIG_SYS_CLOCK_TICKS_PER_SEC=1000
+CONFIG_RV_BOOT_HART=1

boards/beagle/beaglev_fire/beaglev_fire_polarfire_u54_smp.dts

@@ -0,0 +1,19 @@
+/dts-v1/;
+#include "beaglev_fire_polarfire_u54.dts"
+
+/ {
+	model = "beagle,beaglev-fire";
+	compatible = "beagle,beaglev-fire", "microchip,mpfs";
+
+	chosen {
+		zephyr,console = &uart1;
+		zephyr,shell-uart = &uart1;
+		zephyr,sram = &sram1;
+	};
+};
+
+&uart1 {
+	status = "okay";
+	current-speed = <115200>;
+	clock-frequency = <150000000>;
+};

boards/beagle/beaglev_fire/beaglev_fire_polarfire_u54_smp.yaml

@@ -0,0 +1,12 @@
+identifier: beaglev_fire/polarfire/u54/smp
+name: Beagleboard BeagleV-Fire
+type: mcu
+arch: riscv
+toolchain:
+  - zephyr
+ram: 3840
+testing:
+  ignore_tags:
+    - net
+    - bluetooth
+vendor: beagle

boards/beagle/beaglev_fire/beaglev_fire_polarfire_u54_smp_defconfig

@@ -1,3 +1,6 @@
+# Copyright (c) 2023 Microchip Technology Inc
+# SPDX-License-Identifier: Apache-2.0
+
 CONFIG_MPFS_HAL=n
 CONFIG_BASE64=y
 CONFIG_INCLUDE_RESET_VECTOR=y
@@ -7,8 +10,5 @@ CONFIG_UART_CONSOLE=y
 CONFIG_XIP=n
 CONFIG_INIT_STACKS=y
 CONFIG_SYS_CLOCK_TICKS_PER_SEC=1000
-CONFIG_GPIO=y
-CONFIG_I2C=y
-CONFIG_SMP=y
 CONFIG_RV_BOOT_HART=1
-CONFIG_MP_MAX_NUM_CPUS=4
+CONFIG_SMP=y

boards/beagle/beaglev_fire/board.yml

@@ -3,3 +3,6 @@ board:
   vendor: beagle
   socs:
   - name: polarfire
+    variants:
+    - name: smp
+      cpucluster: u54

boards/microchip/mpfs_icicle/Kconfig

@@ -1,7 +0,0 @@
-# Copyright (c) 2021-2022 Microchip Technology Inc
-# SPDX-License-Identifier: Apache-2.0
-
-config BOARD_MPFS_ICICLE
-	select 64BIT
-	select SCHED_IPI_SUPPORTED
-	select CPU_HAS_FPU_DOUBLE_PRECISION

boards/microchip/mpfs_icicle/Kconfig.mpfs_icicle

@@ -2,4 +2,6 @@
 # SPDX-License-Identifier: Apache-2.0
 
 config BOARD_MPFS_ICICLE
-	select SOC_POLARFIRE
+	select SOC_POLARFIRE_U54 if BOARD_MPFS_ICICLE_POLARFIRE_U54 || \
+				       BOARD_MPFS_ICICLE_POLARFIRE_U54_SMP
+	select SOC_POLARFIRE_E51 if BOARD_MPFS_ICICLE_POLARFIRE_E51

boards/microchip/mpfs_icicle/board.cmake

@@ -1,4 +0,0 @@
-# SPDX-License-Identifier: Apache-2.0
-
-set(SUPPORTED_EMU_PLATFORMS renode)
-set(RENODE_SCRIPT ${CMAKE_CURRENT_LIST_DIR}/support/mpfs250t.resc)

boards/microchip/mpfs_icicle/board.yml

@@ -4,4 +4,5 @@ board:
   socs:
   - name: polarfire
     variants:
-    - name: 'smp'
+    - name: smp
+      cpucluster: u54

boards/microchip/mpfs_icicle/mpfs_icicle_common.dtsi

@@ -10,7 +10,7 @@
 #include <mem.h>
 
 / {
-	model = "Microchip PolarFire-SoC Icicle Kit";
+	model = "microchip,mpfs-icicle-kit";
 	compatible = "microchip,mpfs-icicle-kit", "microchip,mpfs";
 	aliases {
 		led0 = &led0;
@@ -19,12 +19,6 @@
 		i2c1 = &i2c1;
 	};
 
-	chosen {
-		zephyr,console = &uart0;
-		zephyr,shell-uart = &uart0;
-		zephyr,sram = &sram1;
-	};
-
 	leds {
 		compatible = "gpio-leds";
 

boards/microchip/mpfs_icicle/mpfs_icicle_polarfire_e51.dts

@@ -0,0 +1,31 @@
+/dts-v1/;
+#include "mpfs_icicle_common.dtsi"
+
+/ {
+	compatible = "microchip,mpfs-icicle-kit", "microchip,mpfs";
+
+	cpus {
+		cpu@1 {
+			status = "disabled";
+		};
+
+		cpu@2 {
+			status = "disabled";
+		};
+
+		cpu@3 {
+			status = "disabled";
+		};
+
+		cpu@4 {
+			status = "disabled";
+		};
+	};
+
+	chosen {
+		zephyr,console = &uart0;
+		zephyr,shell-uart = &uart0;
+		zephyr,sram = &sram1;
+	};
+
+};

boards/microchip/mpfs_icicle/mpfs_icicle_polarfire_e51.yaml

@@ -1,5 +1,5 @@
-identifier: mpfs_icicle
+identifier: mpfs_icicle/polarfire/e51
-name: Microchip PolarFire ICICLE kit
+name: Microchip PolarFire SoC Icicle Kit
 type: mcu
 arch: riscv
 toolchain:

boards/microchip/mpfs_icicle/mpfs_icicle_polarfire_e51_defconfig

@@ -0,0 +1,15 @@
+# Copyright (c) 2020-2021 Microchip Technology Inc
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_MPFS_HAL=n
+CONFIG_BASE64=y
+CONFIG_INCLUDE_RESET_VECTOR=y
+CONFIG_CONSOLE=y
+CONFIG_SERIAL=y
+CONFIG_UART_CONSOLE=y
+CONFIG_XIP=n
+CONFIG_INIT_STACKS=y
+CONFIG_SYS_CLOCK_TICKS_PER_SEC=1000
+# GPIO driver options
+CONFIG_GPIO=y
+CONFIG_I2C=y

boards/microchip/mpfs_icicle/mpfs_icicle_polarfire_u54.dts

@@ -0,0 +1,24 @@
+/dts-v1/;
+#include "mpfs_icicle_common.dtsi"
+
+/ {
+	compatible = "microchip,mpfs-icicle-kit", "microchip,mpfs";
+
+	cpus {
+		cpu@0 {
+			status = "disabled";
+		};
+	};
+
+	chosen {
+		zephyr,console = &uart1;
+		zephyr,shell-uart = &uart1;
+		zephyr,sram = &sram1;
+	};
+};
+
+&uart1 {
+	status = "okay";
+	current-speed = <115200>;
+	clock-frequency = <150000000>;
+};

boards/microchip/mpfs_icicle/mpfs_icicle_polarfire_u54.yaml

@@ -1,5 +1,5 @@
-identifier: mpfs_icicle/polarfire/smp
+identifier: mpfs_icicle/polarfire/u54
-name: Microchip PolarFire ICICLE kit (SMP)
+name: Microchip PolarFire SoC Icicle Kit
 type: mcu
 arch: riscv
 toolchain:

boards/microchip/mpfs_icicle/mpfs_icicle_polarfire_u54_defconfig

@@ -0,0 +1,16 @@
+# Copyright (c) 2020-2021 Microchip Technology Inc
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_MPFS_HAL=n
+CONFIG_BASE64=y
+CONFIG_INCLUDE_RESET_VECTOR=y
+CONFIG_CONSOLE=y
+CONFIG_SERIAL=y
+CONFIG_UART_CONSOLE=y
+CONFIG_XIP=n
+CONFIG_INIT_STACKS=y
+CONFIG_SYS_CLOCK_TICKS_PER_SEC=1000
+CONFIG_RV_BOOT_HART=1
+# GPIO driver options
+CONFIG_GPIO=y
+CONFIG_I2C=y

boards/microchip/mpfs_icicle/mpfs_icicle_polarfire_u54_smp.dts

@@ -0,0 +1,18 @@
+/dts-v1/;
+#include "mpfs_icicle_polarfire_u54.dts"
+
+/ {
+	compatible = "microchip,mpfs-icicle-kit", "microchip,mpfs";
+
+	chosen {
+		zephyr,console = &uart1;
+		zephyr,shell-uart = &uart1;
+		zephyr,sram = &sram1;
+	};
+};
+
+&uart1 {
+	status = "okay";
+	current-speed = <115200>;
+	clock-frequency = <150000000>;
+};

boards/microchip/mpfs_icicle/mpfs_icicle_polarfire_u54_smp.yaml

@@ -0,0 +1,13 @@
+identifier: mpfs_icicle/polarfire/u54/smp
+name: Microchip PolarFire SoC Icicle Kit
+type: mcu
+arch: riscv
+toolchain:
+  - zephyr
+ram: 3840
+testing:
+  ignore_tags:
+    - net
+    - bluetooth
+    - flash
+vendor: microchip

boards/microchip/mpfs_icicle/mpfs_icicle_polarfire_u54_smp_defconfig

@@ -0,0 +1,17 @@
+# Copyright (c) 2020-2021 Microchip Technology Inc
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_MPFS_HAL=n
+CONFIG_BASE64=y
+CONFIG_INCLUDE_RESET_VECTOR=y
+CONFIG_CONSOLE=y
+CONFIG_SERIAL=y
+CONFIG_UART_CONSOLE=y
+CONFIG_XIP=n
+CONFIG_INIT_STACKS=y
+CONFIG_SYS_CLOCK_TICKS_PER_SEC=1000
+# GPIO driver options
+CONFIG_GPIO=y
+CONFIG_I2C=y
+CONFIG_RV_BOOT_HART=1
+CONFIG_SMP=y

boards/microchip/mpfs_icicle/mpfs_icicle_smp.dts

@@ -1,94 +0,0 @@
-/*
- * Copyright (c) 2020-2021 Microchip Technology Inc
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-/dts-v1/;
-#include <microchip/mpfs.dtsi>
-#include <zephyr/dt-bindings/input/input-event-codes.h>
-#include <mem.h>
-
-/ {
-	model = "Microchip PolarFire-SoC Icicle Kit";
-	compatible = "microchip,mpfs-icicle-kit", "microchip,mpfs";
-
-	cpus {
-		cpu@0 {
-			status = "disabled";
-		};
-	};
-
-	aliases {
-		led0 = &led0;
-		sw0 = &sw0;
-		i2c0 = &i2c0;
-		i2c1 = &i2c1;
-	};
-
-	chosen {
-		zephyr,console = &uart1;
-		zephyr,shell-uart = &uart1;
-		zephyr,sram = &sram1;
-	};
-
-	leds {
-		compatible = "gpio-leds";
-
-		led0: led0 {
-			gpios = <&gpio2 16 GPIO_ACTIVE_LOW>;
-			label = "LED_0";
-		};
-	};
-
-	keys {
-		compatible = "gpio-keys";
-		sw0: sw0 {
-			gpios = <&gpio2 30 GPIO_ACTIVE_LOW>;
-			label = "SW_0";
-			zephyr,code = <INPUT_KEY_0>;
-		};
-	};
-};
-
-&uart1 {
-	status = "okay";
-	current-speed = <115200>;
-	clock-frequency = <150000000>;
-};
-
-&qspi0 {
-	status = "okay";
-	qspi_flash: spi-nor-flash@0 {
-		compatible = "jedec,spi-nor";
-		reg = <0>;
-		spi-max-frequency = <5000000>;
-		size = <DT_SIZE_M(256)>;
-		jedec-id = [20 ba 19];
-	};
-};
-
-&spi1 {
-	status = "okay";
-};
-
-&syscontroller_qspi {
-	status = "okay";
-	sys_ctrl_flash: spi-nor-flash@0 {
-		compatible = "jedec,spi-nor";
-		reg = <0>;
-		spi-max-frequency = <5000000>;
-	};
-};
-
-&gpio2 {
-	status = "okay";
-};
-
-&i2c0 {
-	status = "okay";
-};
-
-&i2c1 {
-	status = "okay";
-};

boards/microchip/mpfs_icicle/support/mpfs250t.resc

@@ -1,17 +0,0 @@
-:name: MPFS-ICICLE-KIT
-:description: This script is prepared to run Zephyr on a PolarFire SoC Icicle Kit RISC-V board.
-
-$name?="MPFS-ICICLE-KIT"
-
-using sysbus
-mach create $name
-machine LoadPlatformDescription @platforms/boards/mpfs-icicle-kit.repl
-
-showAnalyzer mmuart0
-e51 PerformanceInMips 80
-
-macro reset
-"""
-    sysbus LoadELF $elf
-"""
-runMacro $reset

soc/microchip/miv/polarfire/Kconfig

@@ -9,12 +9,21 @@ config SOC_SERIES_POLARFIRE
 	select RISCV_HAS_PLIC
 
 config SOC_POLARFIRE
+	select 64BIT
+	select SCHED_IPI_SUPPORTED
 	select ATOMIC_OPERATIONS_BUILTIN
 	select RISCV_GP
 	select USE_SWITCH_SUPPORTED
 	select USE_SWITCH
+
+config SOC_POLARFIRE_U54
 	select CPU_HAS_FPU
-	select SCHED_IPI_SUPPORTED
+	select CPU_HAS_FPU_DOUBLE_PRECISION
+	select RISCV_ISA_RV64I
+	select RISCV_ISA_EXT_G
+	select RISCV_ISA_EXT_C
+
+config SOC_POLARFIRE_E51
 	select RISCV_ISA_RV64I
 	select RISCV_ISA_EXT_M
 	select RISCV_ISA_EXT_A

soc/microchip/miv/polarfire/Kconfig.defconfig

@@ -3,6 +3,8 @@
 
 if SOC_SERIES_POLARFIRE
 
+rsource "Kconfig.defconfig.polarfire*"
+
 # MPFS should be configured so that the mtimer clock is 1MHz independent of the CPU clock...
 
 config SYS_CLOCK_HW_CYCLES_PER_SEC

soc/microchip/miv/polarfire/Kconfig.defconfig.polarfire_u54

@@ -0,0 +1,9 @@
+# Copyright (c) 2024 Antmicro
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_POLARFIRE_U54
+
+config MP_MAX_NUM_CPUS
+	default 4
+
+endif

soc/microchip/miv/polarfire/Kconfig.soc

@@ -15,6 +15,14 @@ config SOC_POLARFIRE
 	help
 	  Microchip MPFS system implementation
 
+config SOC_POLARFIRE_U54
+	bool
+	select SOC_POLARFIRE
+
+config SOC_POLARFIRE_E51
+	bool
+	select SOC_POLARFIRE
+
 config SOC_SERIES
 	default "polarfire" if SOC_SERIES_POLARFIRE
 

soc/microchip/miv/soc.yml

@@ -7,3 +7,6 @@ family:
   - name: polarfire
     socs:
     - name: polarfire
+      cpuclusters:
+      - name: e51
+      - name: u54

tests/subsys/mgmt/mcumgr/fs_mgmt_hash_supported/testcase.yaml

@@ -19,8 +19,9 @@ common:
     - nucleo_h755zi_q/stm32h755xx/m4
     - stm32h747i_disco/stm32h747xx/m4
     - lpcxpresso55s69/lpc55s69/cpu1
-    - mpfs_icicle
+    - mpfs_icicle/polarfire/u54
-    - mpfs_icicle/polarfire/smp
+    - mpfs_icicle/polarfire/u54/smp
+    - mpfs_icicle/polarfire/e51
     - apollo4p_evb
     - stm32h745i_disco/stm32h745xx/m4
     - cyw920829m2evk_02