diff --git a/boards/beagle/beaglev_fire/Kconfig b/boards/beagle/beaglev_fire/Kconfig deleted file mode 100644 index a0ce11033e7..00000000000 --- a/boards/beagle/beaglev_fire/Kconfig +++ /dev/null @@ -1,7 +0,0 @@ -# Copyright (c) 2023 Microchip Technology Inc -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_BEAGLEV_FIRE - select 64BIT - select SCHED_IPI_SUPPORTED - select CPU_HAS_FPU_DOUBLE_PRECISION diff --git a/boards/beagle/beaglev_fire/Kconfig.beaglev_fire b/boards/beagle/beaglev_fire/Kconfig.beaglev_fire index b4bf8b4b2d3..118bee296d0 100644 --- a/boards/beagle/beaglev_fire/Kconfig.beaglev_fire +++ b/boards/beagle/beaglev_fire/Kconfig.beaglev_fire @@ -2,4 +2,6 @@ # SPDX-License-Identifier: Apache-2.0 config BOARD_BEAGLEV_FIRE - select SOC_POLARFIRE + select SOC_POLARFIRE_U54 if BOARD_BEAGLEV_FIRE_POLARFIRE_U54 || \ + BOARD_BEAGLEV_FIRE_POLARFIRE_U54_SMP + select SOC_POLARFIRE_E51 if BOARD_BEAGLEV_FIRE_POLARFIRE_E51 diff --git a/boards/beagle/beaglev_fire/beaglev_fire.dts b/boards/beagle/beaglev_fire/beaglev_fire_common.dtsi similarity index 60% rename from boards/beagle/beaglev_fire/beaglev_fire.dts rename to boards/beagle/beaglev_fire/beaglev_fire_common.dtsi index df956f5c8f2..24b1958a9d9 100644 --- a/boards/beagle/beaglev_fire/beaglev_fire.dts +++ b/boards/beagle/beaglev_fire/beaglev_fire_common.dtsi @@ -10,22 +10,10 @@ #include / { - model = "BeagleV-Fire"; + model = "beagle,beaglev-fire"; compatible = "beagle,beaglev-fire", "microchip,mpfs"; aliases { }; - - chosen { - zephyr,console = &uart0; - zephyr,shell-uart = &uart0; - zephyr,sram = &sram1; - }; -}; - -&uart0 { - status = "okay"; - current-speed = <115200>; - clock-frequency = <150000000>; }; &gpio2 { diff --git a/boards/beagle/beaglev_fire/beaglev_fire_defconfig b/boards/beagle/beaglev_fire/beaglev_fire_defconfig index deb1db784f8..ded4a47c214 100644 --- a/boards/beagle/beaglev_fire/beaglev_fire_defconfig +++ b/boards/beagle/beaglev_fire/beaglev_fire_defconfig @@ -10,4 +10,3 @@ CONFIG_UART_CONSOLE=y CONFIG_XIP=n CONFIG_INIT_STACKS=y CONFIG_SYS_CLOCK_TICKS_PER_SEC=1000 -CONFIG_FPU=n diff --git a/boards/beagle/beaglev_fire/beaglev_fire_polarfire_e51.dts b/boards/beagle/beaglev_fire/beaglev_fire_polarfire_e51.dts new file mode 100644 index 00000000000..5a8537124d4 --- /dev/null +++ b/boards/beagle/beaglev_fire/beaglev_fire_polarfire_e51.dts @@ -0,0 +1,36 @@ +/dts-v1/; +#include "beaglev_fire_common.dtsi" + +/ { + compatible = "beagle,beaglev-fire", "microchip,mpfs"; + + cpus { + cpu@1 { + status = "disabled"; + }; + + cpu@2 { + status = "disabled"; + }; + + cpu@3 { + status = "disabled"; + }; + + cpu@4 { + status = "disabled"; + }; + }; + + chosen { + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + zephyr,sram = &sram1; + }; +}; + +&uart0 { + status = "okay"; + current-speed = <115200>; + clock-frequency = <150000000>; +}; diff --git a/boards/beagle/beaglev_fire/beaglev_fire.yaml b/boards/beagle/beaglev_fire/beaglev_fire_polarfire_e51.yaml similarity index 79% rename from boards/beagle/beaglev_fire/beaglev_fire.yaml rename to boards/beagle/beaglev_fire/beaglev_fire_polarfire_e51.yaml index 79c65d30e0f..bc5ee3de628 100644 --- a/boards/beagle/beaglev_fire/beaglev_fire.yaml +++ b/boards/beagle/beaglev_fire/beaglev_fire_polarfire_e51.yaml @@ -1,4 +1,4 @@ -identifier: beaglev_fire +identifier: beaglev_fire/polarfire/e51 name: Beagleboard BeagleV-Fire type: mcu arch: riscv diff --git a/boards/beagle/beaglev_fire/beaglev_fire_polarfire_e51_defconfig b/boards/beagle/beaglev_fire/beaglev_fire_polarfire_e51_defconfig new file mode 100644 index 00000000000..ded4a47c214 --- /dev/null +++ b/boards/beagle/beaglev_fire/beaglev_fire_polarfire_e51_defconfig @@ -0,0 +1,12 @@ +# Copyright (c) 2023 Microchip Technology Inc +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_MPFS_HAL=n +CONFIG_BASE64=y +CONFIG_INCLUDE_RESET_VECTOR=y +CONFIG_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y +CONFIG_XIP=n +CONFIG_INIT_STACKS=y +CONFIG_SYS_CLOCK_TICKS_PER_SEC=1000 diff --git a/boards/beagle/beaglev_fire/beaglev_fire_polarfire_u54.dts b/boards/beagle/beaglev_fire/beaglev_fire_polarfire_u54.dts new file mode 100644 index 00000000000..7c4fba300fd --- /dev/null +++ b/boards/beagle/beaglev_fire/beaglev_fire_polarfire_u54.dts @@ -0,0 +1,25 @@ +/dts-v1/; +#include "beaglev_fire_common.dtsi" + +/ { + model = "beagle,beaglev-fire"; + compatible = "beagle,beaglev-fire", "microchip,mpfs"; + + chosen { + zephyr,console = &uart1; + zephyr,shell-uart = &uart1; + zephyr,sram = &sram1; + }; + + cpus { + cpu@0 { + status = "disabled"; + }; + }; +}; + +&uart1 { + status = "okay"; + current-speed = <115200>; + clock-frequency = <150000000>; +}; diff --git a/boards/beagle/beaglev_fire/beaglev_fire_polarfire_u54.yaml b/boards/beagle/beaglev_fire/beaglev_fire_polarfire_u54.yaml new file mode 100644 index 00000000000..9204225a766 --- /dev/null +++ b/boards/beagle/beaglev_fire/beaglev_fire_polarfire_u54.yaml @@ -0,0 +1,12 @@ +identifier: beaglev_fire/polarfire/u54 +name: Beagleboard BeagleV-Fire +type: mcu +arch: riscv +toolchain: + - zephyr +ram: 3840 +testing: + ignore_tags: + - net + - bluetooth +vendor: beagle diff --git a/boards/beagle/beaglev_fire/beaglev_fire_polarfire_u54_defconfig b/boards/beagle/beaglev_fire/beaglev_fire_polarfire_u54_defconfig new file mode 100644 index 00000000000..ef99af479d4 --- /dev/null +++ b/boards/beagle/beaglev_fire/beaglev_fire_polarfire_u54_defconfig @@ -0,0 +1,13 @@ +# Copyright (c) 2023 Microchip Technology Inc +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_MPFS_HAL=n +CONFIG_BASE64=y +CONFIG_INCLUDE_RESET_VECTOR=y +CONFIG_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y +CONFIG_XIP=n +CONFIG_INIT_STACKS=y +CONFIG_SYS_CLOCK_TICKS_PER_SEC=1000 +CONFIG_RV_BOOT_HART=1 diff --git a/boards/beagle/beaglev_fire/beaglev_fire_polarfire_u54_smp.dts b/boards/beagle/beaglev_fire/beaglev_fire_polarfire_u54_smp.dts new file mode 100644 index 00000000000..cf9ed20aa3e --- /dev/null +++ b/boards/beagle/beaglev_fire/beaglev_fire_polarfire_u54_smp.dts @@ -0,0 +1,19 @@ +/dts-v1/; +#include "beaglev_fire_polarfire_u54.dts" + +/ { + model = "beagle,beaglev-fire"; + compatible = "beagle,beaglev-fire", "microchip,mpfs"; + + chosen { + zephyr,console = &uart1; + zephyr,shell-uart = &uart1; + zephyr,sram = &sram1; + }; +}; + +&uart1 { + status = "okay"; + current-speed = <115200>; + clock-frequency = <150000000>; +}; diff --git a/boards/beagle/beaglev_fire/beaglev_fire_polarfire_u54_smp.yaml b/boards/beagle/beaglev_fire/beaglev_fire_polarfire_u54_smp.yaml new file mode 100644 index 00000000000..e8f31601438 --- /dev/null +++ b/boards/beagle/beaglev_fire/beaglev_fire_polarfire_u54_smp.yaml @@ -0,0 +1,12 @@ +identifier: beaglev_fire/polarfire/u54/smp +name: Beagleboard BeagleV-Fire +type: mcu +arch: riscv +toolchain: + - zephyr +ram: 3840 +testing: + ignore_tags: + - net + - bluetooth +vendor: beagle diff --git a/boards/microchip/mpfs_icicle/mpfs_icicle_smp_defconfig b/boards/beagle/beaglev_fire/beaglev_fire_polarfire_u54_smp_defconfig similarity index 72% rename from boards/microchip/mpfs_icicle/mpfs_icicle_smp_defconfig rename to boards/beagle/beaglev_fire/beaglev_fire_polarfire_u54_smp_defconfig index 529171d1c46..e1e30df8b16 100644 --- a/boards/microchip/mpfs_icicle/mpfs_icicle_smp_defconfig +++ b/boards/beagle/beaglev_fire/beaglev_fire_polarfire_u54_smp_defconfig @@ -1,3 +1,6 @@ +# Copyright (c) 2023 Microchip Technology Inc +# SPDX-License-Identifier: Apache-2.0 + CONFIG_MPFS_HAL=n CONFIG_BASE64=y CONFIG_INCLUDE_RESET_VECTOR=y @@ -7,8 +10,5 @@ CONFIG_UART_CONSOLE=y CONFIG_XIP=n CONFIG_INIT_STACKS=y CONFIG_SYS_CLOCK_TICKS_PER_SEC=1000 -CONFIG_GPIO=y -CONFIG_I2C=y -CONFIG_SMP=y CONFIG_RV_BOOT_HART=1 -CONFIG_MP_MAX_NUM_CPUS=4 +CONFIG_SMP=y diff --git a/boards/beagle/beaglev_fire/board.yml b/boards/beagle/beaglev_fire/board.yml index 89447e4b4ce..60520301134 100644 --- a/boards/beagle/beaglev_fire/board.yml +++ b/boards/beagle/beaglev_fire/board.yml @@ -3,3 +3,6 @@ board: vendor: beagle socs: - name: polarfire + variants: + - name: smp + cpucluster: u54 diff --git a/boards/microchip/mpfs_icicle/Kconfig b/boards/microchip/mpfs_icicle/Kconfig deleted file mode 100644 index bbacc84d304..00000000000 --- a/boards/microchip/mpfs_icicle/Kconfig +++ /dev/null @@ -1,7 +0,0 @@ -# Copyright (c) 2021-2022 Microchip Technology Inc -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_MPFS_ICICLE - select 64BIT - select SCHED_IPI_SUPPORTED - select CPU_HAS_FPU_DOUBLE_PRECISION diff --git a/boards/microchip/mpfs_icicle/Kconfig.mpfs_icicle b/boards/microchip/mpfs_icicle/Kconfig.mpfs_icicle index cc744a4f940..2efd9446c73 100644 --- a/boards/microchip/mpfs_icicle/Kconfig.mpfs_icicle +++ b/boards/microchip/mpfs_icicle/Kconfig.mpfs_icicle @@ -2,4 +2,6 @@ # SPDX-License-Identifier: Apache-2.0 config BOARD_MPFS_ICICLE - select SOC_POLARFIRE + select SOC_POLARFIRE_U54 if BOARD_MPFS_ICICLE_POLARFIRE_U54 || \ + BOARD_MPFS_ICICLE_POLARFIRE_U54_SMP + select SOC_POLARFIRE_E51 if BOARD_MPFS_ICICLE_POLARFIRE_E51 diff --git a/boards/microchip/mpfs_icicle/board.cmake b/boards/microchip/mpfs_icicle/board.cmake deleted file mode 100644 index 0fed4848fa9..00000000000 --- a/boards/microchip/mpfs_icicle/board.cmake +++ /dev/null @@ -1,4 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -set(SUPPORTED_EMU_PLATFORMS renode) -set(RENODE_SCRIPT ${CMAKE_CURRENT_LIST_DIR}/support/mpfs250t.resc) diff --git a/boards/microchip/mpfs_icicle/board.yml b/boards/microchip/mpfs_icicle/board.yml index f97e2409c14..b9799c5830e 100644 --- a/boards/microchip/mpfs_icicle/board.yml +++ b/boards/microchip/mpfs_icicle/board.yml @@ -4,4 +4,5 @@ board: socs: - name: polarfire variants: - - name: 'smp' + - name: smp + cpucluster: u54 diff --git a/boards/microchip/mpfs_icicle/mpfs_icicle.dts b/boards/microchip/mpfs_icicle/mpfs_icicle_common.dtsi similarity index 89% rename from boards/microchip/mpfs_icicle/mpfs_icicle.dts rename to boards/microchip/mpfs_icicle/mpfs_icicle_common.dtsi index 902180c0a14..0f615ccb861 100644 --- a/boards/microchip/mpfs_icicle/mpfs_icicle.dts +++ b/boards/microchip/mpfs_icicle/mpfs_icicle_common.dtsi @@ -10,7 +10,7 @@ #include / { - model = "Microchip PolarFire-SoC Icicle Kit"; + model = "microchip,mpfs-icicle-kit"; compatible = "microchip,mpfs-icicle-kit", "microchip,mpfs"; aliases { led0 = &led0; @@ -19,12 +19,6 @@ i2c1 = &i2c1; }; - chosen { - zephyr,console = &uart0; - zephyr,shell-uart = &uart0; - zephyr,sram = &sram1; - }; - leds { compatible = "gpio-leds"; diff --git a/boards/microchip/mpfs_icicle/mpfs_icicle_polarfire_e51.dts b/boards/microchip/mpfs_icicle/mpfs_icicle_polarfire_e51.dts new file mode 100644 index 00000000000..63287f678aa --- /dev/null +++ b/boards/microchip/mpfs_icicle/mpfs_icicle_polarfire_e51.dts @@ -0,0 +1,31 @@ +/dts-v1/; +#include "mpfs_icicle_common.dtsi" + +/ { + compatible = "microchip,mpfs-icicle-kit", "microchip,mpfs"; + + cpus { + cpu@1 { + status = "disabled"; + }; + + cpu@2 { + status = "disabled"; + }; + + cpu@3 { + status = "disabled"; + }; + + cpu@4 { + status = "disabled"; + }; + }; + + chosen { + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + zephyr,sram = &sram1; + }; + +}; diff --git a/boards/microchip/mpfs_icicle/mpfs_icicle.yaml b/boards/microchip/mpfs_icicle/mpfs_icicle_polarfire_e51.yaml similarity index 62% rename from boards/microchip/mpfs_icicle/mpfs_icicle.yaml rename to boards/microchip/mpfs_icicle/mpfs_icicle_polarfire_e51.yaml index f4fe86c5cd7..3518a70f8d8 100644 --- a/boards/microchip/mpfs_icicle/mpfs_icicle.yaml +++ b/boards/microchip/mpfs_icicle/mpfs_icicle_polarfire_e51.yaml @@ -1,5 +1,5 @@ -identifier: mpfs_icicle -name: Microchip PolarFire ICICLE kit +identifier: mpfs_icicle/polarfire/e51 +name: Microchip PolarFire SoC Icicle Kit type: mcu arch: riscv toolchain: diff --git a/boards/microchip/mpfs_icicle/mpfs_icicle_polarfire_e51_defconfig b/boards/microchip/mpfs_icicle/mpfs_icicle_polarfire_e51_defconfig new file mode 100644 index 00000000000..bfc0590663a --- /dev/null +++ b/boards/microchip/mpfs_icicle/mpfs_icicle_polarfire_e51_defconfig @@ -0,0 +1,15 @@ +# Copyright (c) 2020-2021 Microchip Technology Inc +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_MPFS_HAL=n +CONFIG_BASE64=y +CONFIG_INCLUDE_RESET_VECTOR=y +CONFIG_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y +CONFIG_XIP=n +CONFIG_INIT_STACKS=y +CONFIG_SYS_CLOCK_TICKS_PER_SEC=1000 +# GPIO driver options +CONFIG_GPIO=y +CONFIG_I2C=y diff --git a/boards/microchip/mpfs_icicle/mpfs_icicle_polarfire_u54.dts b/boards/microchip/mpfs_icicle/mpfs_icicle_polarfire_u54.dts new file mode 100644 index 00000000000..e1652c96e3e --- /dev/null +++ b/boards/microchip/mpfs_icicle/mpfs_icicle_polarfire_u54.dts @@ -0,0 +1,24 @@ +/dts-v1/; +#include "mpfs_icicle_common.dtsi" + +/ { + compatible = "microchip,mpfs-icicle-kit", "microchip,mpfs"; + + cpus { + cpu@0 { + status = "disabled"; + }; + }; + + chosen { + zephyr,console = &uart1; + zephyr,shell-uart = &uart1; + zephyr,sram = &sram1; + }; +}; + +&uart1 { + status = "okay"; + current-speed = <115200>; + clock-frequency = <150000000>; +}; diff --git a/boards/microchip/mpfs_icicle/mpfs_icicle_smp.yaml b/boards/microchip/mpfs_icicle/mpfs_icicle_polarfire_u54.yaml similarity index 62% rename from boards/microchip/mpfs_icicle/mpfs_icicle_smp.yaml rename to boards/microchip/mpfs_icicle/mpfs_icicle_polarfire_u54.yaml index 14437607bf8..9599b13e1c5 100644 --- a/boards/microchip/mpfs_icicle/mpfs_icicle_smp.yaml +++ b/boards/microchip/mpfs_icicle/mpfs_icicle_polarfire_u54.yaml @@ -1,5 +1,5 @@ -identifier: mpfs_icicle/polarfire/smp -name: Microchip PolarFire ICICLE kit (SMP) +identifier: mpfs_icicle/polarfire/u54 +name: Microchip PolarFire SoC Icicle Kit type: mcu arch: riscv toolchain: diff --git a/boards/microchip/mpfs_icicle/mpfs_icicle_polarfire_u54_defconfig b/boards/microchip/mpfs_icicle/mpfs_icicle_polarfire_u54_defconfig new file mode 100644 index 00000000000..c40256dbf73 --- /dev/null +++ b/boards/microchip/mpfs_icicle/mpfs_icicle_polarfire_u54_defconfig @@ -0,0 +1,16 @@ +# Copyright (c) 2020-2021 Microchip Technology Inc +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_MPFS_HAL=n +CONFIG_BASE64=y +CONFIG_INCLUDE_RESET_VECTOR=y +CONFIG_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y +CONFIG_XIP=n +CONFIG_INIT_STACKS=y +CONFIG_SYS_CLOCK_TICKS_PER_SEC=1000 +CONFIG_RV_BOOT_HART=1 +# GPIO driver options +CONFIG_GPIO=y +CONFIG_I2C=y diff --git a/boards/microchip/mpfs_icicle/mpfs_icicle_polarfire_u54_smp.dts b/boards/microchip/mpfs_icicle/mpfs_icicle_polarfire_u54_smp.dts new file mode 100644 index 00000000000..11af6fb7622 --- /dev/null +++ b/boards/microchip/mpfs_icicle/mpfs_icicle_polarfire_u54_smp.dts @@ -0,0 +1,18 @@ +/dts-v1/; +#include "mpfs_icicle_polarfire_u54.dts" + +/ { + compatible = "microchip,mpfs-icicle-kit", "microchip,mpfs"; + + chosen { + zephyr,console = &uart1; + zephyr,shell-uart = &uart1; + zephyr,sram = &sram1; + }; +}; + +&uart1 { + status = "okay"; + current-speed = <115200>; + clock-frequency = <150000000>; +}; diff --git a/boards/microchip/mpfs_icicle/mpfs_icicle_polarfire_u54_smp.yaml b/boards/microchip/mpfs_icicle/mpfs_icicle_polarfire_u54_smp.yaml new file mode 100644 index 00000000000..6118303c246 --- /dev/null +++ b/boards/microchip/mpfs_icicle/mpfs_icicle_polarfire_u54_smp.yaml @@ -0,0 +1,13 @@ +identifier: mpfs_icicle/polarfire/u54/smp +name: Microchip PolarFire SoC Icicle Kit +type: mcu +arch: riscv +toolchain: + - zephyr +ram: 3840 +testing: + ignore_tags: + - net + - bluetooth + - flash +vendor: microchip diff --git a/boards/microchip/mpfs_icicle/mpfs_icicle_polarfire_u54_smp_defconfig b/boards/microchip/mpfs_icicle/mpfs_icicle_polarfire_u54_smp_defconfig new file mode 100644 index 00000000000..e12c515e69a --- /dev/null +++ b/boards/microchip/mpfs_icicle/mpfs_icicle_polarfire_u54_smp_defconfig @@ -0,0 +1,17 @@ +# Copyright (c) 2020-2021 Microchip Technology Inc +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_MPFS_HAL=n +CONFIG_BASE64=y +CONFIG_INCLUDE_RESET_VECTOR=y +CONFIG_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y +CONFIG_XIP=n +CONFIG_INIT_STACKS=y +CONFIG_SYS_CLOCK_TICKS_PER_SEC=1000 +# GPIO driver options +CONFIG_GPIO=y +CONFIG_I2C=y +CONFIG_RV_BOOT_HART=1 +CONFIG_SMP=y diff --git a/boards/microchip/mpfs_icicle/mpfs_icicle_smp.dts b/boards/microchip/mpfs_icicle/mpfs_icicle_smp.dts deleted file mode 100644 index 6d122ed5d97..00000000000 --- a/boards/microchip/mpfs_icicle/mpfs_icicle_smp.dts +++ /dev/null @@ -1,94 +0,0 @@ -/* - * Copyright (c) 2020-2021 Microchip Technology Inc - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/dts-v1/; -#include -#include -#include - -/ { - model = "Microchip PolarFire-SoC Icicle Kit"; - compatible = "microchip,mpfs-icicle-kit", "microchip,mpfs"; - - cpus { - cpu@0 { - status = "disabled"; - }; - }; - - aliases { - led0 = &led0; - sw0 = &sw0; - i2c0 = &i2c0; - i2c1 = &i2c1; - }; - - chosen { - zephyr,console = &uart1; - zephyr,shell-uart = &uart1; - zephyr,sram = &sram1; - }; - - leds { - compatible = "gpio-leds"; - - led0: led0 { - gpios = <&gpio2 16 GPIO_ACTIVE_LOW>; - label = "LED_0"; - }; - }; - - keys { - compatible = "gpio-keys"; - sw0: sw0 { - gpios = <&gpio2 30 GPIO_ACTIVE_LOW>; - label = "SW_0"; - zephyr,code = ; - }; - }; -}; - -&uart1 { - status = "okay"; - current-speed = <115200>; - clock-frequency = <150000000>; -}; - -&qspi0 { - status = "okay"; - qspi_flash: spi-nor-flash@0 { - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <5000000>; - size = ; - jedec-id = [20 ba 19]; - }; -}; - -&spi1 { - status = "okay"; -}; - -&syscontroller_qspi { - status = "okay"; - sys_ctrl_flash: spi-nor-flash@0 { - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <5000000>; - }; -}; - -&gpio2 { - status = "okay"; -}; - -&i2c0 { - status = "okay"; -}; - -&i2c1 { - status = "okay"; -}; diff --git a/boards/microchip/mpfs_icicle/support/mpfs250t.resc b/boards/microchip/mpfs_icicle/support/mpfs250t.resc deleted file mode 100644 index 29005c8f198..00000000000 --- a/boards/microchip/mpfs_icicle/support/mpfs250t.resc +++ /dev/null @@ -1,17 +0,0 @@ -:name: MPFS-ICICLE-KIT -:description: This script is prepared to run Zephyr on a PolarFire SoC Icicle Kit RISC-V board. - -$name?="MPFS-ICICLE-KIT" - -using sysbus -mach create $name -machine LoadPlatformDescription @platforms/boards/mpfs-icicle-kit.repl - -showAnalyzer mmuart0 -e51 PerformanceInMips 80 - -macro reset -""" - sysbus LoadELF $elf -""" -runMacro $reset diff --git a/soc/microchip/miv/polarfire/Kconfig b/soc/microchip/miv/polarfire/Kconfig index b57d0ee92fb..c096759507d 100644 --- a/soc/microchip/miv/polarfire/Kconfig +++ b/soc/microchip/miv/polarfire/Kconfig @@ -9,12 +9,21 @@ config SOC_SERIES_POLARFIRE select RISCV_HAS_PLIC config SOC_POLARFIRE + select 64BIT + select SCHED_IPI_SUPPORTED select ATOMIC_OPERATIONS_BUILTIN select RISCV_GP select USE_SWITCH_SUPPORTED select USE_SWITCH + +config SOC_POLARFIRE_U54 select CPU_HAS_FPU - select SCHED_IPI_SUPPORTED + select CPU_HAS_FPU_DOUBLE_PRECISION + select RISCV_ISA_RV64I + select RISCV_ISA_EXT_G + select RISCV_ISA_EXT_C + +config SOC_POLARFIRE_E51 select RISCV_ISA_RV64I select RISCV_ISA_EXT_M select RISCV_ISA_EXT_A diff --git a/soc/microchip/miv/polarfire/Kconfig.defconfig b/soc/microchip/miv/polarfire/Kconfig.defconfig index 113a3bd6acb..a694c9a50b2 100644 --- a/soc/microchip/miv/polarfire/Kconfig.defconfig +++ b/soc/microchip/miv/polarfire/Kconfig.defconfig @@ -3,6 +3,8 @@ if SOC_SERIES_POLARFIRE +rsource "Kconfig.defconfig.polarfire*" + # MPFS should be configured so that the mtimer clock is 1MHz independent of the CPU clock... config SYS_CLOCK_HW_CYCLES_PER_SEC diff --git a/soc/microchip/miv/polarfire/Kconfig.defconfig.polarfire_u54 b/soc/microchip/miv/polarfire/Kconfig.defconfig.polarfire_u54 new file mode 100644 index 00000000000..a3f5df02f50 --- /dev/null +++ b/soc/microchip/miv/polarfire/Kconfig.defconfig.polarfire_u54 @@ -0,0 +1,9 @@ +# Copyright (c) 2024 Antmicro +# SPDX-License-Identifier: Apache-2.0 + +if SOC_POLARFIRE_U54 + +config MP_MAX_NUM_CPUS + default 4 + +endif diff --git a/soc/microchip/miv/polarfire/Kconfig.soc b/soc/microchip/miv/polarfire/Kconfig.soc index ce44e8b8ada..75380b16861 100644 --- a/soc/microchip/miv/polarfire/Kconfig.soc +++ b/soc/microchip/miv/polarfire/Kconfig.soc @@ -15,6 +15,14 @@ config SOC_POLARFIRE help Microchip MPFS system implementation +config SOC_POLARFIRE_U54 + bool + select SOC_POLARFIRE + +config SOC_POLARFIRE_E51 + bool + select SOC_POLARFIRE + config SOC_SERIES default "polarfire" if SOC_SERIES_POLARFIRE diff --git a/soc/microchip/miv/soc.yml b/soc/microchip/miv/soc.yml index 11f30cffc32..04488e8a8fb 100644 --- a/soc/microchip/miv/soc.yml +++ b/soc/microchip/miv/soc.yml @@ -7,3 +7,6 @@ family: - name: polarfire socs: - name: polarfire + cpuclusters: + - name: e51 + - name: u54 diff --git a/tests/subsys/mgmt/mcumgr/fs_mgmt_hash_supported/testcase.yaml b/tests/subsys/mgmt/mcumgr/fs_mgmt_hash_supported/testcase.yaml index aaaf8a2f3c3..37bd14e53bd 100644 --- a/tests/subsys/mgmt/mcumgr/fs_mgmt_hash_supported/testcase.yaml +++ b/tests/subsys/mgmt/mcumgr/fs_mgmt_hash_supported/testcase.yaml @@ -19,8 +19,9 @@ common: - nucleo_h755zi_q/stm32h755xx/m4 - stm32h747i_disco/stm32h747xx/m4 - lpcxpresso55s69/lpc55s69/cpu1 - - mpfs_icicle - - mpfs_icicle/polarfire/smp + - mpfs_icicle/polarfire/u54 + - mpfs_icicle/polarfire/u54/smp + - mpfs_icicle/polarfire/e51 - apollo4p_evb - stm32h745i_disco/stm32h745xx/m4 - cyw920829m2evk_02