soc: polarfire: split into cpu clusters

Split Polarfire SoC into CPU clusters as they have different
capabilities.

Signed-off-by: Andrzej Drabarek <adrabarek@antmicro.com>

soc/microchip/miv/polarfire/Kconfig

@@ -9,12 +9,21 @@ config SOC_SERIES_POLARFIRE
 	select RISCV_HAS_PLIC
 
 config SOC_POLARFIRE
+	select 64BIT
+	select SCHED_IPI_SUPPORTED
 	select ATOMIC_OPERATIONS_BUILTIN
 	select RISCV_GP
 	select USE_SWITCH_SUPPORTED
 	select USE_SWITCH
+
+config SOC_POLARFIRE_U54
 	select CPU_HAS_FPU
-	select SCHED_IPI_SUPPORTED
+	select CPU_HAS_FPU_DOUBLE_PRECISION
+	select RISCV_ISA_RV64I
+	select RISCV_ISA_EXT_G
+	select RISCV_ISA_EXT_C
+
+config SOC_POLARFIRE_E51
 	select RISCV_ISA_RV64I
 	select RISCV_ISA_EXT_M
 	select RISCV_ISA_EXT_A

soc/microchip/miv/polarfire/Kconfig.defconfig

@@ -3,6 +3,8 @@
 
 if SOC_SERIES_POLARFIRE
 
+rsource "Kconfig.defconfig.polarfire*"
+
 # MPFS should be configured so that the mtimer clock is 1MHz independent of the CPU clock...
 
 config SYS_CLOCK_HW_CYCLES_PER_SEC

soc/microchip/miv/polarfire/Kconfig.defconfig.polarfire_u54

@@ -0,0 +1,9 @@
+# Copyright (c) 2024 Antmicro
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_POLARFIRE_U54
+
+config MP_MAX_NUM_CPUS
+	default 4
+
+endif

soc/microchip/miv/polarfire/Kconfig.soc

@@ -15,6 +15,14 @@ config SOC_POLARFIRE
 	help
 	  Microchip MPFS system implementation
 
+config SOC_POLARFIRE_U54
+	bool
+	select SOC_POLARFIRE
+
+config SOC_POLARFIRE_E51
+	bool
+	select SOC_POLARFIRE
+
 config SOC_SERIES
 	default "polarfire" if SOC_SERIES_POLARFIRE
 

soc/microchip/miv/soc.yml

@@ -7,3 +7,6 @@ family:
   - name: polarfire
     socs:
     - name: polarfire
+      cpuclusters:
+      - name: e51
+      - name: u54