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arch/arm: Use TPIDRURO on cortex-a too

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V7-A also supports TPIDRURO, so go ahead and use that for TLS, enabling
thread local storage for the other ARM architectures.

Add __aeabi_read_tp function in case code was compiled to use that.

Signed-off-by: Keith Packard <keithp@keithp.com>
This commit is contained in:
Keith Packard 2021-12-20 14:56:39 -08:00 • committed by Stephanos Ioannidis
commit 1638d4851e
4 changed files with 18 additions and 2 deletions
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2
arch/Kconfig
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@ -33,7 +33,7 @@ config ARM
# FIXME: current state of the code for all ARM requires this, but # FIXME: current state of the code for all ARM requires this, but
# is really only necessary for Cortex-M with ARM MPU! # is really only necessary for Cortex-M with ARM MPU!
select GEN_PRIV_STACKS select GEN_PRIV_STACKS
select ARCH_HAS_THREAD_LOCAL_STORAGE if CPU_AARCH32_CORTEX_R || CPU_CORTEX_M select ARCH_HAS_THREAD_LOCAL_STORAGE if CPU_AARCH32_CORTEX_R || CPU_CORTEX_M || CPU_AARCH32_CORTEX_A
help help
ARM architecture ARM architecture

1
arch/arm/core/aarch32/cortex_a_r/CMakeLists.txt
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@ -16,3 +16,4 @@ zephyr_library_sources(
zephyr_library_sources_ifdef(CONFIG_USERSPACE thread.c) zephyr_library_sources_ifdef(CONFIG_USERSPACE thread.c)
zephyr_library_sources_ifdef(CONFIG_SEMIHOST semihost.c) zephyr_library_sources_ifdef(CONFIG_SEMIHOST semihost.c)
zephyr_library_sources_ifdef(CONFIG_THREAD_LOCAL_STORAGE __aeabi_read_tp.S)

15
arch/arm/core/aarch32/cortex_a_r/__aeabi_read_tp.S Normal file
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@ -0,0 +1,15 @@
/*
* Copyright (c) 2020 Intel Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <toolchain.h>
_ASM_FILE_PROLOGUE
GTEXT(__aeabi_read_tp)
SECTION_FUNC(text, __aeabi_read_tp)
mrc 15, 0, r0, c13, c0, 3
bx lr

2
arch/arm/core/aarch32/swap_helper.S
View file

@ -186,7 +186,7 @@ out_fp_endif:
adds r4, r2, r4 adds r4, r2, r4
ldr r0, [r4] ldr r0, [r4]
#if defined(CONFIG_CPU_AARCH32_CORTEX_R) #if defined(CONFIG_CPU_AARCH32_CORTEX_R) || defined(CONFIG_CPU_AARCH32_CORTEX_A)
/* Store TLS pointer in the "Process ID" register. /* Store TLS pointer in the "Process ID" register.
* This register is used as a base pointer to all * This register is used as a base pointer to all
* thread variables with offsets added by toolchain. * thread variables with offsets added by toolchain.