From 1638d4851e44b6c61325d14b92506750c707f924 Mon Sep 17 00:00:00 2001 From: Keith Packard Date: Mon, 20 Dec 2021 14:56:39 -0800 Subject: [PATCH] arch/arm: Use TPIDRURO on cortex-a too V7-A also supports TPIDRURO, so go ahead and use that for TLS, enabling thread local storage for the other ARM architectures. Add __aeabi_read_tp function in case code was compiled to use that. Signed-off-by: Keith Packard --- arch/Kconfig | 2 +- arch/arm/core/aarch32/cortex_a_r/CMakeLists.txt | 1 + .../arm/core/aarch32/cortex_a_r/__aeabi_read_tp.S | 15 +++++++++++++++ arch/arm/core/aarch32/swap_helper.S | 2 +- 4 files changed, 18 insertions(+), 2 deletions(-) create mode 100644 arch/arm/core/aarch32/cortex_a_r/__aeabi_read_tp.S diff --git a/arch/Kconfig b/arch/Kconfig index cb3564c2933..7f0e0e74b35 100644 --- a/arch/Kconfig +++ b/arch/Kconfig @@ -33,7 +33,7 @@ config ARM # FIXME: current state of the code for all ARM requires this, but # is really only necessary for Cortex-M with ARM MPU! select GEN_PRIV_STACKS - select ARCH_HAS_THREAD_LOCAL_STORAGE if CPU_AARCH32_CORTEX_R || CPU_CORTEX_M + select ARCH_HAS_THREAD_LOCAL_STORAGE if CPU_AARCH32_CORTEX_R || CPU_CORTEX_M || CPU_AARCH32_CORTEX_A help ARM architecture diff --git a/arch/arm/core/aarch32/cortex_a_r/CMakeLists.txt b/arch/arm/core/aarch32/cortex_a_r/CMakeLists.txt index bb95c33782c..d3337a6753a 100644 --- a/arch/arm/core/aarch32/cortex_a_r/CMakeLists.txt +++ b/arch/arm/core/aarch32/cortex_a_r/CMakeLists.txt @@ -16,3 +16,4 @@ zephyr_library_sources( zephyr_library_sources_ifdef(CONFIG_USERSPACE thread.c) zephyr_library_sources_ifdef(CONFIG_SEMIHOST semihost.c) +zephyr_library_sources_ifdef(CONFIG_THREAD_LOCAL_STORAGE __aeabi_read_tp.S) diff --git a/arch/arm/core/aarch32/cortex_a_r/__aeabi_read_tp.S b/arch/arm/core/aarch32/cortex_a_r/__aeabi_read_tp.S new file mode 100644 index 00000000000..181fae3d7ea --- /dev/null +++ b/arch/arm/core/aarch32/cortex_a_r/__aeabi_read_tp.S @@ -0,0 +1,15 @@ +/* + * Copyright (c) 2020 Intel Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +_ASM_FILE_PROLOGUE + +GTEXT(__aeabi_read_tp) + +SECTION_FUNC(text, __aeabi_read_tp) + mrc 15, 0, r0, c13, c0, 3 + bx lr diff --git a/arch/arm/core/aarch32/swap_helper.S b/arch/arm/core/aarch32/swap_helper.S index 90452186e46..2f9518af265 100644 --- a/arch/arm/core/aarch32/swap_helper.S +++ b/arch/arm/core/aarch32/swap_helper.S @@ -186,7 +186,7 @@ out_fp_endif: adds r4, r2, r4 ldr r0, [r4] -#if defined(CONFIG_CPU_AARCH32_CORTEX_R) +#if defined(CONFIG_CPU_AARCH32_CORTEX_R) || defined(CONFIG_CPU_AARCH32_CORTEX_A) /* Store TLS pointer in the "Process ID" register. * This register is used as a base pointer to all * thread variables with offsets added by toolchain.