soc: riscv32: Move rv32m1 flash memory definitions to dts
Moves the flash memory definitions from Kconfig to device tree for the rv32m1 ri5cy and zero-riscy cores. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
This commit is contained in:
parent
cf1be5a3c5
commit
15baad9419
7 changed files with 75 additions and 15 deletions
|
@ -14,6 +14,7 @@
|
||||||
|
|
||||||
chosen {
|
chosen {
|
||||||
zephyr,sram = &m4_dtcm;
|
zephyr,sram = &m4_dtcm;
|
||||||
|
zephyr,flash = &ri5cy_code_partition;
|
||||||
zephyr,console = &uart0;
|
zephyr,console = &uart0;
|
||||||
zephyr,uart-pipe = &uart0;
|
zephyr,uart-pipe = &uart0;
|
||||||
};
|
};
|
||||||
|
|
|
@ -14,6 +14,7 @@
|
||||||
|
|
||||||
chosen {
|
chosen {
|
||||||
zephyr,sram = &m0_tcm;
|
zephyr,sram = &m0_tcm;
|
||||||
|
zephyr,flash = &zero_riscy_code_partition;
|
||||||
zephyr,console = &uart0;
|
zephyr,console = &uart0;
|
||||||
zephyr,uart-pipe = &uart0;
|
zephyr,uart-pipe = &uart0;
|
||||||
};
|
};
|
||||||
|
|
|
@ -280,5 +280,30 @@
|
||||||
#size-cells = <0>;
|
#size-cells = <0>;
|
||||||
status = "disabled";
|
status = "disabled";
|
||||||
};
|
};
|
||||||
|
|
||||||
|
flash-controller@40023000 {
|
||||||
|
compatible = "nxp,kinetis-ftfe";
|
||||||
|
label = "FLASH_CTRL";
|
||||||
|
reg = <0x40023000 0x18>;
|
||||||
|
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <1>;
|
||||||
|
|
||||||
|
m4_flash: flash@0 {
|
||||||
|
compatible = "soc-nv-flash";
|
||||||
|
label = "M4_FLASH";
|
||||||
|
reg = <0 0x100000>;
|
||||||
|
erase-block-size = <4096>;
|
||||||
|
write-block-size = <8>;
|
||||||
|
};
|
||||||
|
|
||||||
|
m0_flash: flash@1000000 {
|
||||||
|
compatible = "soc-nv-flash";
|
||||||
|
label = "M0_FLASH";
|
||||||
|
reg = <0x01000000 0x40000>;
|
||||||
|
erase-block-size = <4096>;
|
||||||
|
write-block-size = <8>;
|
||||||
|
};
|
||||||
|
};
|
||||||
};
|
};
|
||||||
};
|
};
|
||||||
|
|
|
@ -16,6 +16,29 @@
|
||||||
};
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
|
&m4_flash {
|
||||||
|
partitions {
|
||||||
|
compatible = "fixed-partitions";
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <1>;
|
||||||
|
|
||||||
|
/* This configuration assumes the Arm cores are disabled, as
|
||||||
|
* these base addresses contain the Arm core vector tables if
|
||||||
|
* they are used.
|
||||||
|
*/
|
||||||
|
|
||||||
|
ri5cy_code_partition: partition@0 {
|
||||||
|
label = "ri5cy-code";
|
||||||
|
reg = <0x00000000 0x000fff00>;
|
||||||
|
};
|
||||||
|
|
||||||
|
ri5cy_vector_partition: partition@fff00 {
|
||||||
|
label = "ri5cy-vector";
|
||||||
|
reg = <0x000fff00 0x100>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* INTMUX channels below are somewhat arbitrary.
|
* INTMUX channels below are somewhat arbitrary.
|
||||||
*
|
*
|
||||||
|
|
|
@ -16,6 +16,29 @@
|
||||||
};
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
|
&m0_flash {
|
||||||
|
partitions {
|
||||||
|
compatible = "fixed-partitions";
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <1>;
|
||||||
|
|
||||||
|
/* This configuration assumes the Arm cores are disabled, as
|
||||||
|
* these base addresses contain the Arm core vector tables if
|
||||||
|
* they are used.
|
||||||
|
*/
|
||||||
|
|
||||||
|
zero_riscy_code_partition: partition@1000000 {
|
||||||
|
label = "zero-riscy-code";
|
||||||
|
reg = <0x01000000 0x0003ff00>;
|
||||||
|
};
|
||||||
|
|
||||||
|
zero_riscy_vector_partition: partition@3ff00 {
|
||||||
|
label = "zero-riscy-vector";
|
||||||
|
reg = <0x0003ff00 0x100>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* INTMUX channels below are somewhat arbitrary.
|
* INTMUX channels below are somewhat arbitrary.
|
||||||
*
|
*
|
||||||
|
|
|
@ -49,19 +49,6 @@ config RISCV_SOC_INTERRUPT_INIT
|
||||||
config WDOG_INIT
|
config WDOG_INIT
|
||||||
def_bool y
|
def_bool y
|
||||||
|
|
||||||
# Built-in flash allocated to each chip. This configuration
|
|
||||||
# assumes the Arm cores are disabled, as these base addresses
|
|
||||||
# contain the Arm core vector tables if they are used.
|
|
||||||
config RISCV32_RV32M1_ROM_BASE_ADDR
|
|
||||||
hex
|
|
||||||
default 0x00000000 if SOC_OPENISA_RV32M1_RI5CY
|
|
||||||
default 0x01000000 if SOC_OPENISA_RV32M1_ZERO_RISCY
|
|
||||||
|
|
||||||
config RISCV32_RV32M1_ROM_SIZE
|
|
||||||
hex
|
|
||||||
default 0x000FFF00 if SOC_OPENISA_RV32M1_RI5CY
|
|
||||||
default 0x0003FF00 if SOC_OPENISA_RV32M1_ZERO_RISCY
|
|
||||||
|
|
||||||
# The event unit looks for vector tables at the end of each core's
|
# The event unit looks for vector tables at the end of each core's
|
||||||
# flash space. These vector tables are not relocatable.
|
# flash space. These vector tables are not relocatable.
|
||||||
config RISCV32_RV32M1_VECTOR_BASE_ADDR
|
config RISCV32_RV32M1_VECTOR_BASE_ADDR
|
||||||
|
|
|
@ -29,8 +29,8 @@
|
||||||
#define ROMABLE_REGION ROM
|
#define ROMABLE_REGION ROM
|
||||||
#define RAMABLE_REGION RAM
|
#define RAMABLE_REGION RAM
|
||||||
|
|
||||||
#define ROM_BASE CONFIG_RISCV32_RV32M1_ROM_BASE_ADDR
|
#define ROM_BASE DT_FLASH_BASE_ADDRESS
|
||||||
#define ROM_SIZE CONFIG_RISCV32_RV32M1_ROM_SIZE
|
#define ROM_SIZE KB(DT_FLASH_SIZE)
|
||||||
#define RAM_BASE DT_SRAM_BASE_ADDRESS
|
#define RAM_BASE DT_SRAM_BASE_ADDRESS
|
||||||
#define RAM_SIZE KB(DT_SRAM_SIZE)
|
#define RAM_SIZE KB(DT_SRAM_SIZE)
|
||||||
#define VECTOR_BASE CONFIG_RISCV32_RV32M1_VECTOR_BASE_ADDR
|
#define VECTOR_BASE CONFIG_RISCV32_RV32M1_VECTOR_BASE_ADDR
|
||||||
|
|
Loading…
Add table
Add a link
Reference in a new issue