From 15baad94197c2cdfbbc3ec9de255a50e9b01f1ad Mon Sep 17 00:00:00 2001 From: Maureen Helm Date: Mon, 6 May 2019 13:50:52 -0500 Subject: [PATCH] soc: riscv32: Move rv32m1 flash memory definitions to dts Moves the flash memory definitions from Kconfig to device tree for the rv32m1 ri5cy and zero-riscy cores. Signed-off-by: Maureen Helm --- .../riscv32/rv32m1_vega/rv32m1_vega_ri5cy.dts | 1 + .../rv32m1_vega/rv32m1_vega_zero_riscy.dts | 1 + dts/riscv32/rv32m1.dtsi | 25 +++++++++++++++++++ dts/riscv32/rv32m1_ri5cy.dtsi | 23 +++++++++++++++++ dts/riscv32/rv32m1_zero_riscy.dtsi | 23 +++++++++++++++++ soc/riscv32/openisa_rv32m1/Kconfig.defconfig | 13 ---------- soc/riscv32/openisa_rv32m1/linker.ld | 4 +-- 7 files changed, 75 insertions(+), 15 deletions(-) diff --git a/boards/riscv32/rv32m1_vega/rv32m1_vega_ri5cy.dts b/boards/riscv32/rv32m1_vega/rv32m1_vega_ri5cy.dts index 7fca5c83808..8cbae1c209e 100644 --- a/boards/riscv32/rv32m1_vega/rv32m1_vega_ri5cy.dts +++ b/boards/riscv32/rv32m1_vega/rv32m1_vega_ri5cy.dts @@ -14,6 +14,7 @@ chosen { zephyr,sram = &m4_dtcm; + zephyr,flash = &ri5cy_code_partition; zephyr,console = &uart0; zephyr,uart-pipe = &uart0; }; diff --git a/boards/riscv32/rv32m1_vega/rv32m1_vega_zero_riscy.dts b/boards/riscv32/rv32m1_vega/rv32m1_vega_zero_riscy.dts index bcc6296ed7b..5059a00d56d 100644 --- a/boards/riscv32/rv32m1_vega/rv32m1_vega_zero_riscy.dts +++ b/boards/riscv32/rv32m1_vega/rv32m1_vega_zero_riscy.dts @@ -14,6 +14,7 @@ chosen { zephyr,sram = &m0_tcm; + zephyr,flash = &zero_riscy_code_partition; zephyr,console = &uart0; zephyr,uart-pipe = &uart0; }; diff --git a/dts/riscv32/rv32m1.dtsi b/dts/riscv32/rv32m1.dtsi index db65a2abbfc..eb7afa6086d 100644 --- a/dts/riscv32/rv32m1.dtsi +++ b/dts/riscv32/rv32m1.dtsi @@ -280,5 +280,30 @@ #size-cells = <0>; status = "disabled"; }; + + flash-controller@40023000 { + compatible = "nxp,kinetis-ftfe"; + label = "FLASH_CTRL"; + reg = <0x40023000 0x18>; + + #address-cells = <1>; + #size-cells = <1>; + + m4_flash: flash@0 { + compatible = "soc-nv-flash"; + label = "M4_FLASH"; + reg = <0 0x100000>; + erase-block-size = <4096>; + write-block-size = <8>; + }; + + m0_flash: flash@1000000 { + compatible = "soc-nv-flash"; + label = "M0_FLASH"; + reg = <0x01000000 0x40000>; + erase-block-size = <4096>; + write-block-size = <8>; + }; + }; }; }; diff --git a/dts/riscv32/rv32m1_ri5cy.dtsi b/dts/riscv32/rv32m1_ri5cy.dtsi index 26ae978e75b..54eb4e56c21 100644 --- a/dts/riscv32/rv32m1_ri5cy.dtsi +++ b/dts/riscv32/rv32m1_ri5cy.dtsi @@ -16,6 +16,29 @@ }; }; +&m4_flash { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + /* This configuration assumes the Arm cores are disabled, as + * these base addresses contain the Arm core vector tables if + * they are used. + */ + + ri5cy_code_partition: partition@0 { + label = "ri5cy-code"; + reg = <0x00000000 0x000fff00>; + }; + + ri5cy_vector_partition: partition@fff00 { + label = "ri5cy-vector"; + reg = <0x000fff00 0x100>; + }; + }; +}; + /* * INTMUX channels below are somewhat arbitrary. * diff --git a/dts/riscv32/rv32m1_zero_riscy.dtsi b/dts/riscv32/rv32m1_zero_riscy.dtsi index d5d6372dcf4..d734201056f 100644 --- a/dts/riscv32/rv32m1_zero_riscy.dtsi +++ b/dts/riscv32/rv32m1_zero_riscy.dtsi @@ -16,6 +16,29 @@ }; }; +&m0_flash { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + /* This configuration assumes the Arm cores are disabled, as + * these base addresses contain the Arm core vector tables if + * they are used. + */ + + zero_riscy_code_partition: partition@1000000 { + label = "zero-riscy-code"; + reg = <0x01000000 0x0003ff00>; + }; + + zero_riscy_vector_partition: partition@3ff00 { + label = "zero-riscy-vector"; + reg = <0x0003ff00 0x100>; + }; + }; +}; + /* * INTMUX channels below are somewhat arbitrary. * diff --git a/soc/riscv32/openisa_rv32m1/Kconfig.defconfig b/soc/riscv32/openisa_rv32m1/Kconfig.defconfig index 90fc4532636..758e99813f5 100644 --- a/soc/riscv32/openisa_rv32m1/Kconfig.defconfig +++ b/soc/riscv32/openisa_rv32m1/Kconfig.defconfig @@ -49,19 +49,6 @@ config RISCV_SOC_INTERRUPT_INIT config WDOG_INIT def_bool y -# Built-in flash allocated to each chip. This configuration -# assumes the Arm cores are disabled, as these base addresses -# contain the Arm core vector tables if they are used. -config RISCV32_RV32M1_ROM_BASE_ADDR - hex - default 0x00000000 if SOC_OPENISA_RV32M1_RI5CY - default 0x01000000 if SOC_OPENISA_RV32M1_ZERO_RISCY - -config RISCV32_RV32M1_ROM_SIZE - hex - default 0x000FFF00 if SOC_OPENISA_RV32M1_RI5CY - default 0x0003FF00 if SOC_OPENISA_RV32M1_ZERO_RISCY - # The event unit looks for vector tables at the end of each core's # flash space. These vector tables are not relocatable. config RISCV32_RV32M1_VECTOR_BASE_ADDR diff --git a/soc/riscv32/openisa_rv32m1/linker.ld b/soc/riscv32/openisa_rv32m1/linker.ld index 204ac1051f8..4c725e3dc6a 100644 --- a/soc/riscv32/openisa_rv32m1/linker.ld +++ b/soc/riscv32/openisa_rv32m1/linker.ld @@ -29,8 +29,8 @@ #define ROMABLE_REGION ROM #define RAMABLE_REGION RAM -#define ROM_BASE CONFIG_RISCV32_RV32M1_ROM_BASE_ADDR -#define ROM_SIZE CONFIG_RISCV32_RV32M1_ROM_SIZE +#define ROM_BASE DT_FLASH_BASE_ADDRESS +#define ROM_SIZE KB(DT_FLASH_SIZE) #define RAM_BASE DT_SRAM_BASE_ADDRESS #define RAM_SIZE KB(DT_SRAM_SIZE) #define VECTOR_BASE CONFIG_RISCV32_RV32M1_VECTOR_BASE_ADDR