soc/riscv: add the QEMU "RISC-V VirtIO board"
The QEMU RISC-V VirtIO board is capable: - 8 x CPU - 256 MiB RAM - PMP - PCI - ISA string: RVnnIMAFDCSU - mul/div - FPU with double precision - MMU - Compressed instructions Devicetree was extracted from QEMU as described in virt.dtsi. The same .dtsi SOC description is used for 32-bit and 64-bit. Signed-off-by: Martin Åberg <martin.aberg@gaisler.com>
This commit is contained in:
Martin Åberg
Anas Nashif
parent
d2e9568543
commit
152d3e46ad
8 changed files with 276 additions and 0 deletions
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@ -330,6 +330,7 @@
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/dts/arm/silabs/efm32pg12b* @chrta
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/dts/arm/silabs/efm32pg1b* @rdmeneze
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/dts/arm/silabs/efr32mg21* @l-alfred
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/dts/riscv/ @kgugala @pgielda @nategraff-sifive
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/dts/riscv/it8xxx2.dtsi @ite
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/dts/riscv/microsemi-miv.dtsi @galak
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/dts/riscv/rv32m1* @MaureenHelm
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198
dts/riscv/virt.dtsi
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198
dts/riscv/virt.dtsi
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@ -0,0 +1,198 @@
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/*
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* Copyright (c) 2020 Cobham Gaisler AB
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/*
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* This file is based on:
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* qemu-system-riscv32 -machine virt,dumpdtb=virt.dtb -smp 8 -m 256
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* dtc virt.dtb > virt.dtsi
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*/
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/dts-v1/;
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/ {
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#address-cells = < 0x01 >;
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#size-cells = < 0x01 >;
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compatible = "riscv-virtio";
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model = "riscv-virtio,qemu";
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flash@20000000 {
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bank-width = < 0x04 >;
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reg = < 0x20000000 0x2000000 0x22000000 0x2000000 >;
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compatible = "cfi-flash";
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};
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uart0: uart@10000000 {
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interrupts = < 0x0a 1 >;
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interrupt-parent = < &plic >;
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clock-frequency = < 0x384000 >;
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reg = < 0x10000000 0x100 >;
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compatible = "ns16550";
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reg-shift = < 0 >;
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label = "UART_0";
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};
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cpus {
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#address-cells = < 0x01 >;
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#size-cells = < 0x00 >;
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timebase-frequency = < 10000000 >;
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cpu@0 {
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device_type = "cpu";
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reg = < 0x00 >;
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status = "okay";
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compatible = "riscv";
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hlic0: interrupt-controller {
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#interrupt-cells = < 0x01 >;
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interrupt-controller;
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compatible = "riscv,cpu-intc";
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};
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};
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cpu@1 {
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device_type = "cpu";
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reg = < 0x01 >;
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status = "okay";
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compatible = "riscv";
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hlic1: interrupt-controller {
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#interrupt-cells = < 0x01 >;
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interrupt-controller;
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compatible = "riscv,cpu-intc";
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};
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};
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cpu@2 {
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device_type = "cpu";
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reg = < 0x02 >;
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status = "okay";
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compatible = "riscv";
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hlic2: interrupt-controller {
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#interrupt-cells = < 0x01 >;
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interrupt-controller;
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compatible = "riscv,cpu-intc";
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};
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};
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cpu@3 {
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device_type = "cpu";
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reg = < 0x03 >;
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status = "okay";
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compatible = "riscv";
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hlic3: interrupt-controller {
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#interrupt-cells = < 0x01 >;
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interrupt-controller;
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compatible = "riscv,cpu-intc";
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};
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};
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cpu@4 {
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device_type = "cpu";
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reg = < 0x04 >;
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status = "okay";
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compatible = "riscv";
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hlic4: interrupt-controller {
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#interrupt-cells = < 0x01 >;
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interrupt-controller;
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compatible = "riscv,cpu-intc";
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};
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};
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cpu@5 {
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device_type = "cpu";
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reg = < 0x05 >;
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status = "okay";
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compatible = "riscv";
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hlic5: interrupt-controller {
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#interrupt-cells = < 0x01 >;
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interrupt-controller;
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compatible = "riscv,cpu-intc";
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};
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};
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cpu@6 {
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device_type = "cpu";
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reg = < 0x06 >;
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status = "okay";
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compatible = "riscv";
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hlic6: interrupt-controller {
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#interrupt-cells = < 0x01 >;
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interrupt-controller;
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compatible = "riscv,cpu-intc";
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};
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};
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cpu@7 {
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device_type = "cpu";
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reg = < 0x07 >;
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status = "okay";
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compatible = "riscv";
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hlic7: interrupt-controller {
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#interrupt-cells = < 0x01 >;
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interrupt-controller;
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compatible = "riscv,cpu-intc";
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};
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};
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};
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ram0: memory@80000000 {
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device_type = "memory";
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reg = < 0x80000000 0x10000000 >;
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};
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soc {
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#address-cells = < 0x01 >;
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#size-cells = < 0x01 >;
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compatible = "simple-bus";
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ranges;
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plic: interrupt-controller@c000000 {
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riscv,max-priority = <7>;
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riscv,ndev = < 0x35 >;
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reg = <0x0c000000 0x00002000
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0x0c002000 0x001fe000
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0x0c200000 0x03e00000>;
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reg-names = "prio", "irq_en", "reg";
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interrupts-extended = <
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&hlic0 0x0b &hlic0 0x09
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&hlic1 0x0b &hlic1 0x09
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&hlic2 0x0b &hlic2 0x09
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&hlic3 0x0b &hlic3 0x09
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&hlic4 0x0b &hlic4 0x09
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&hlic5 0x0b &hlic5 0x09
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&hlic6 0x0b &hlic6 0x09
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&hlic7 0x0b &hlic7 0x09
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>;
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interrupt-controller;
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compatible = "sifive,plic-1.0.0";
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#interrupt-cells = < 0x02 >;
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#address-cells = < 0x00 >;
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};
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clint@2000000 {
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interrupts-extended = <
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&hlic0 0x03 &hlic0 0x07
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&hlic1 0x03 &hlic1 0x07
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&hlic2 0x03 &hlic2 0x07
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&hlic3 0x03 &hlic3 0x07
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&hlic4 0x03 &hlic4 0x07
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&hlic5 0x03 &hlic5 0x07
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&hlic6 0x03 &hlic6 0x07
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&hlic7 0x03 &hlic7 0x07
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>;
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reg = < 0x2000000 0x10000 >;
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compatible = "riscv,clint0";
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#interrupt-cells = <1>;
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interrupt-controller;
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};
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};
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};
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3
soc/riscv/riscv-privilege/virt/CMakeLists.txt
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3
soc/riscv/riscv-privilege/virt/CMakeLists.txt
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# SPDX-License-Identifier: Apache-2.0
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zephyr_sources()
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33
soc/riscv/riscv-privilege/virt/Kconfig.defconfig.series
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33
soc/riscv/riscv-privilege/virt/Kconfig.defconfig.series
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# Copyright (c) 2020 Cobham Gaisler AB
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# SPDX-License-Identifier: Apache-2.0
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if SOC_SERIES_RISCV_VIRT
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config SOC_SERIES
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default "virt"
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config SYS_CLOCK_HW_CYCLES_PER_SEC
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default 10000000
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config RISCV_SOC_INTERRUPT_INIT
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default y
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config RISCV_HAS_CPU_IDLE
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default y
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config RISCV_HAS_PLIC
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default y
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config 2ND_LVL_ISR_TBL_OFFSET
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default 12
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config 2ND_LVL_INTR_00_OFFSET
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default 11
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config MAX_IRQ_PER_AGGREGATOR
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default 52
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config NUM_IRQS
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default 64
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endif
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7
soc/riscv/riscv-privilege/virt/Kconfig.series
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7
soc/riscv/riscv-privilege/virt/Kconfig.series
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# Copyright (c) 2020 Cobham Gaisler AB
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# SPDX-License-Identifier: Apache-2.0
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config SOC_SERIES_RISCV_VIRT
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bool "QEMU RISC-V VirtIO Board"
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select RISCV
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select SOC_FAMILY_RISCV_PRIVILEGE
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12
soc/riscv/riscv-privilege/virt/Kconfig.soc
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12
soc/riscv/riscv-privilege/virt/Kconfig.soc
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# Copyright (c) 2020 Cobham Gaisler AB
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# SPDX-License-Identifier: Apache-2.0
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choice
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prompt "QEMU RISC-V VirtIO Board"
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depends on SOC_SERIES_RISCV_VIRT
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config SOC_RISCV_VIRT
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bool "QEMU RISC-V VirtIO Board"
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select ATOMIC_OPERATIONS_BUILTIN
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endchoice
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6
soc/riscv/riscv-privilege/virt/linker.ld
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6
soc/riscv/riscv-privilege/virt/linker.ld
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@ -0,0 +1,6 @@
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/*
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* Copyright (c) 2020 Cobham Gaisler AB
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <arch/riscv/common/linker.ld>
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16
soc/riscv/riscv-privilege/virt/soc.h
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16
soc/riscv/riscv-privilege/virt/soc.h
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/*
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* Copyright (c) 2020 Cobham Gaisler AB
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef __RISCV_VIRT_SOC_H_
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#define __RISCV_VIRT_SOC_H_
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#include <soc_common.h>
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#include <devicetree.h>
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#define RISCV_MTIME_BASE 0x0200BFF8
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#define RISCV_MTIMECMP_BASE 0x02004000
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#endif
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