diff --git a/CODEOWNERS b/CODEOWNERS index fcdc946d1b0..10b3cadd643 100644 --- a/CODEOWNERS +++ b/CODEOWNERS @@ -330,6 +330,7 @@ /dts/arm/silabs/efm32pg12b* @chrta /dts/arm/silabs/efm32pg1b* @rdmeneze /dts/arm/silabs/efr32mg21* @l-alfred +/dts/riscv/ @kgugala @pgielda @nategraff-sifive /dts/riscv/it8xxx2.dtsi @ite /dts/riscv/microsemi-miv.dtsi @galak /dts/riscv/rv32m1* @MaureenHelm diff --git a/dts/riscv/virt.dtsi b/dts/riscv/virt.dtsi new file mode 100644 index 00000000000..82c30b11d45 --- /dev/null +++ b/dts/riscv/virt.dtsi @@ -0,0 +1,198 @@ +/* + * Copyright (c) 2020 Cobham Gaisler AB + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/* + * This file is based on: + * qemu-system-riscv32 -machine virt,dumpdtb=virt.dtb -smp 8 -m 256 + * dtc virt.dtb > virt.dtsi + */ + +/dts-v1/; + +/ { + #address-cells = < 0x01 >; + #size-cells = < 0x01 >; + compatible = "riscv-virtio"; + model = "riscv-virtio,qemu"; + + flash@20000000 { + bank-width = < 0x04 >; + reg = < 0x20000000 0x2000000 0x22000000 0x2000000 >; + compatible = "cfi-flash"; + }; + + uart0: uart@10000000 { + interrupts = < 0x0a 1 >; + interrupt-parent = < &plic >; + clock-frequency = < 0x384000 >; + reg = < 0x10000000 0x100 >; + compatible = "ns16550"; + reg-shift = < 0 >; + label = "UART_0"; + }; + + cpus { + #address-cells = < 0x01 >; + #size-cells = < 0x00 >; + timebase-frequency = < 10000000 >; + + cpu@0 { + device_type = "cpu"; + reg = < 0x00 >; + status = "okay"; + compatible = "riscv"; + + hlic0: interrupt-controller { + #interrupt-cells = < 0x01 >; + interrupt-controller; + compatible = "riscv,cpu-intc"; + }; + }; + + cpu@1 { + device_type = "cpu"; + reg = < 0x01 >; + status = "okay"; + compatible = "riscv"; + + hlic1: interrupt-controller { + #interrupt-cells = < 0x01 >; + interrupt-controller; + compatible = "riscv,cpu-intc"; + }; + }; + + cpu@2 { + device_type = "cpu"; + reg = < 0x02 >; + status = "okay"; + compatible = "riscv"; + + hlic2: interrupt-controller { + #interrupt-cells = < 0x01 >; + interrupt-controller; + compatible = "riscv,cpu-intc"; + }; + }; + + cpu@3 { + device_type = "cpu"; + reg = < 0x03 >; + status = "okay"; + compatible = "riscv"; + + hlic3: interrupt-controller { + #interrupt-cells = < 0x01 >; + interrupt-controller; + compatible = "riscv,cpu-intc"; + }; + }; + + cpu@4 { + device_type = "cpu"; + reg = < 0x04 >; + status = "okay"; + compatible = "riscv"; + + hlic4: interrupt-controller { + #interrupt-cells = < 0x01 >; + interrupt-controller; + compatible = "riscv,cpu-intc"; + }; + }; + + cpu@5 { + device_type = "cpu"; + reg = < 0x05 >; + status = "okay"; + compatible = "riscv"; + + hlic5: interrupt-controller { + #interrupt-cells = < 0x01 >; + interrupt-controller; + compatible = "riscv,cpu-intc"; + }; + }; + + cpu@6 { + device_type = "cpu"; + reg = < 0x06 >; + status = "okay"; + compatible = "riscv"; + + hlic6: interrupt-controller { + #interrupt-cells = < 0x01 >; + interrupt-controller; + compatible = "riscv,cpu-intc"; + }; + }; + + cpu@7 { + device_type = "cpu"; + reg = < 0x07 >; + status = "okay"; + compatible = "riscv"; + + hlic7: interrupt-controller { + #interrupt-cells = < 0x01 >; + interrupt-controller; + compatible = "riscv,cpu-intc"; + }; + }; + }; + + ram0: memory@80000000 { + device_type = "memory"; + reg = < 0x80000000 0x10000000 >; + }; + + soc { + #address-cells = < 0x01 >; + #size-cells = < 0x01 >; + compatible = "simple-bus"; + ranges; + + plic: interrupt-controller@c000000 { + riscv,max-priority = <7>; + riscv,ndev = < 0x35 >; + reg = <0x0c000000 0x00002000 + 0x0c002000 0x001fe000 + 0x0c200000 0x03e00000>; + reg-names = "prio", "irq_en", "reg"; + interrupts-extended = < + &hlic0 0x0b &hlic0 0x09 + &hlic1 0x0b &hlic1 0x09 + &hlic2 0x0b &hlic2 0x09 + &hlic3 0x0b &hlic3 0x09 + &hlic4 0x0b &hlic4 0x09 + &hlic5 0x0b &hlic5 0x09 + &hlic6 0x0b &hlic6 0x09 + &hlic7 0x0b &hlic7 0x09 + >; + interrupt-controller; + compatible = "sifive,plic-1.0.0"; + #interrupt-cells = < 0x02 >; + #address-cells = < 0x00 >; + }; + + clint@2000000 { + interrupts-extended = < + &hlic0 0x03 &hlic0 0x07 + &hlic1 0x03 &hlic1 0x07 + &hlic2 0x03 &hlic2 0x07 + &hlic3 0x03 &hlic3 0x07 + &hlic4 0x03 &hlic4 0x07 + &hlic5 0x03 &hlic5 0x07 + &hlic6 0x03 &hlic6 0x07 + &hlic7 0x03 &hlic7 0x07 + >; + reg = < 0x2000000 0x10000 >; + compatible = "riscv,clint0"; + #interrupt-cells = <1>; + interrupt-controller; + }; + }; +}; diff --git a/soc/riscv/riscv-privilege/virt/CMakeLists.txt b/soc/riscv/riscv-privilege/virt/CMakeLists.txt new file mode 100644 index 00000000000..55fc3999fd7 --- /dev/null +++ b/soc/riscv/riscv-privilege/virt/CMakeLists.txt @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: Apache-2.0 + +zephyr_sources() diff --git a/soc/riscv/riscv-privilege/virt/Kconfig.defconfig.series b/soc/riscv/riscv-privilege/virt/Kconfig.defconfig.series new file mode 100644 index 00000000000..23ec0ef7ff5 --- /dev/null +++ b/soc/riscv/riscv-privilege/virt/Kconfig.defconfig.series @@ -0,0 +1,33 @@ +# Copyright (c) 2020 Cobham Gaisler AB +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_RISCV_VIRT + +config SOC_SERIES + default "virt" + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default 10000000 + +config RISCV_SOC_INTERRUPT_INIT + default y + +config RISCV_HAS_CPU_IDLE + default y + +config RISCV_HAS_PLIC + default y + +config 2ND_LVL_ISR_TBL_OFFSET + default 12 + +config 2ND_LVL_INTR_00_OFFSET + default 11 + +config MAX_IRQ_PER_AGGREGATOR + default 52 + +config NUM_IRQS + default 64 + +endif diff --git a/soc/riscv/riscv-privilege/virt/Kconfig.series b/soc/riscv/riscv-privilege/virt/Kconfig.series new file mode 100644 index 00000000000..4f105a26641 --- /dev/null +++ b/soc/riscv/riscv-privilege/virt/Kconfig.series @@ -0,0 +1,7 @@ +# Copyright (c) 2020 Cobham Gaisler AB +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_RISCV_VIRT + bool "QEMU RISC-V VirtIO Board" + select RISCV + select SOC_FAMILY_RISCV_PRIVILEGE diff --git a/soc/riscv/riscv-privilege/virt/Kconfig.soc b/soc/riscv/riscv-privilege/virt/Kconfig.soc new file mode 100644 index 00000000000..e263adce234 --- /dev/null +++ b/soc/riscv/riscv-privilege/virt/Kconfig.soc @@ -0,0 +1,12 @@ +# Copyright (c) 2020 Cobham Gaisler AB +# SPDX-License-Identifier: Apache-2.0 + +choice + prompt "QEMU RISC-V VirtIO Board" + depends on SOC_SERIES_RISCV_VIRT + +config SOC_RISCV_VIRT + bool "QEMU RISC-V VirtIO Board" + select ATOMIC_OPERATIONS_BUILTIN + +endchoice diff --git a/soc/riscv/riscv-privilege/virt/linker.ld b/soc/riscv/riscv-privilege/virt/linker.ld new file mode 100644 index 00000000000..b2f084ea859 --- /dev/null +++ b/soc/riscv/riscv-privilege/virt/linker.ld @@ -0,0 +1,6 @@ +/* + * Copyright (c) 2020 Cobham Gaisler AB + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include diff --git a/soc/riscv/riscv-privilege/virt/soc.h b/soc/riscv/riscv-privilege/virt/soc.h new file mode 100644 index 00000000000..bbec9314c51 --- /dev/null +++ b/soc/riscv/riscv-privilege/virt/soc.h @@ -0,0 +1,16 @@ +/* + * Copyright (c) 2020 Cobham Gaisler AB + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef __RISCV_VIRT_SOC_H_ +#define __RISCV_VIRT_SOC_H_ + +#include +#include + +#define RISCV_MTIME_BASE 0x0200BFF8 +#define RISCV_MTIMECMP_BASE 0x02004000 + +#endif