From 11d4f8e5e5adec6202a942796ba214d117f9f947 Mon Sep 17 00:00:00 2001 From: Luca Burelli Date: Thu, 30 Nov 2023 14:32:05 +0100 Subject: [PATCH] soc: stm32: unify cache conditionals for F7 and H7 targets The instruction cache in the STM32F7 and H7 was enabled regardless of the value assigned via Kconfig to the CONFIG_ICACHE parameter. This commit adds the missing conditional checks; note that this does not affect the compiled behavior unless CONFIG_ICACHE is explicitly disabled by the user. Remove a redundant low-level check on DCache being already enabled, since it is also performed inside the SCB_EnableDCache function. Signed-off-by: Luca Burelli --- soc/arm/st_stm32/stm32f7/soc.c | 8 ++++---- soc/arm/st_stm32/stm32h7/soc_m7.c | 8 ++++---- 2 files changed, 8 insertions(+), 8 deletions(-) diff --git a/soc/arm/st_stm32/stm32f7/soc.c b/soc/arm/st_stm32/stm32f7/soc.c index b06a894197a..19941c9cee0 100644 --- a/soc/arm/st_stm32/stm32f7/soc.c +++ b/soc/arm/st_stm32/stm32f7/soc.c @@ -30,12 +30,12 @@ static int st_stm32f7_init(void) /* Enable ART Flash cache accelerator */ LL_FLASH_EnableART(); - SCB_EnableICache(); + if (IS_ENABLED(CONFIG_ICACHE)) { + SCB_EnableICache(); + } if (IS_ENABLED(CONFIG_DCACHE)) { - if (!(SCB->CCR & SCB_CCR_DC_Msk)) { - SCB_EnableDCache(); - } + SCB_EnableDCache(); } /* Update CMSIS SystemCoreClock variable (HCLK) */ diff --git a/soc/arm/st_stm32/stm32h7/soc_m7.c b/soc/arm/st_stm32/stm32h7/soc_m7.c index 8e72b3ee390..7ee62921c41 100644 --- a/soc/arm/st_stm32/stm32h7/soc_m7.c +++ b/soc/arm/st_stm32/stm32h7/soc_m7.c @@ -54,12 +54,12 @@ static int stm32h7_m4_wakeup(void) */ static int stm32h7_init(void) { - SCB_EnableICache(); + if (IS_ENABLED(CONFIG_ICACHE)) { + SCB_EnableICache(); + } if (IS_ENABLED(CONFIG_DCACHE)) { - if (!(SCB->CCR & SCB_CCR_DC_Msk)) { - SCB_EnableDCache(); - } + SCB_EnableDCache(); } /* Update CMSIS SystemCoreClock variable (HCLK) */