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riscv: Align _isr_wrapper to 64 bytes for CLIC

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The CLIC requires that mtvec.base is aligned to 64 bytes.
_isr_wrapper is used as mtvec.base, so align it to 64 bytes.

Signed-off-by: Piotr Wojnarowski <pwojnarowski@antmicro.com>
This commit is contained in:
Piotr Wojnarowski 2024-05-22 22:04:55 +02:00 • committed by Henrik Brix Andersen
commit 0f3fe4daab
2 changed files with 2 additions and 1 deletions
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1
arch/riscv/Kconfig
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@ -369,6 +369,7 @@ config ARCH_IRQ_VECTOR_TABLE_ALIGN
config RISCV_TRAP_HANDLER_ALIGNMENT config RISCV_TRAP_HANDLER_ALIGNMENT
int "Alignment of RISC-V trap handler in bytes" int "Alignment of RISC-V trap handler in bytes"
default 64 if RISCV_HAS_CLIC
default 4 default 4
help help
This value configures the alignment of RISC-V trap handling This value configures the alignment of RISC-V trap handling

2
soc/common/riscv-privileged/vector.S
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@ -33,7 +33,7 @@ SECTION_FUNC(vectors, __start)
* *
* CLIC vectored mode uses mtvec exclusively for exception handling and * CLIC vectored mode uses mtvec exclusively for exception handling and
* mtvec.base must be aligned to 64 bytes (this is done using * mtvec.base must be aligned to 64 bytes (this is done using
* CONFIG_ARCH_SW_ISR_TABLE_ALIGN) * CONFIG_RISCV_TRAP_HANDLER_ALIGNMENT)
*/ */
la t0, _isr_wrapper la t0, _isr_wrapper
addi t0, t0, 0x03 /* Enable CLIC vectored mode by setting LSB */ addi t0, t0, 0x03 /* Enable CLIC vectored mode by setting LSB */