diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index 0993189b99c..00121adc714 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -369,6 +369,7 @@ config ARCH_IRQ_VECTOR_TABLE_ALIGN
 
 config RISCV_TRAP_HANDLER_ALIGNMENT
 	int "Alignment of RISC-V trap handler in bytes"
+	default 64 if RISCV_HAS_CLIC
 	default 4
 	help
 	  This value configures the alignment of RISC-V trap handling
diff --git a/soc/common/riscv-privileged/vector.S b/soc/common/riscv-privileged/vector.S
index 4822fa55333..5d7f84eab58 100644
--- a/soc/common/riscv-privileged/vector.S
+++ b/soc/common/riscv-privileged/vector.S
@@ -33,7 +33,7 @@ SECTION_FUNC(vectors, __start)
 	 *
 	 * CLIC vectored mode uses mtvec exclusively for exception handling and
 	 * mtvec.base must be aligned to 64 bytes (this is done using
-	 * CONFIG_ARCH_SW_ISR_TABLE_ALIGN)
+	 * CONFIG_RISCV_TRAP_HANDLER_ALIGNMENT)
 	 */
 	la t0, _isr_wrapper
 	addi t0, t0, 0x03 /* Enable CLIC vectored mode by setting LSB */