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riscv: Use IRQ vector table for vectored mode

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For vectored interrupts use the generated IRQ vector table instead of
relying on a custom-generated table.

Signed-off-by: Carlo Caione <ccaione@baylibre.com>
This commit is contained in:
Carlo Caione 2022-06-27 10:51:28 +02:00 • committed by Carles Cufí
commit 0e788b89a6
4 changed files with 17 additions and 16 deletions
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1
arch/Kconfig
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@ -421,6 +421,7 @@ config ARCH_IRQ_VECTOR_TABLE_ALIGN
choice IRQ_VECTOR_TABLE_TYPE choice IRQ_VECTOR_TABLE_TYPE
prompt "IRQ vector table type" prompt "IRQ vector table type"
depends on GEN_IRQ_VECTOR_TABLE depends on GEN_IRQ_VECTOR_TABLE
default IRQ_VECTOR_TABLE_JUMP_BY_CODE if RISCV
default IRQ_VECTOR_TABLE_JUMP_BY_ADDRESS default IRQ_VECTOR_TABLE_JUMP_BY_ADDRESS
config IRQ_VECTOR_TABLE_JUMP_BY_ADDRESS config IRQ_VECTOR_TABLE_JUMP_BY_ADDRESS

6
arch/riscv/Kconfig
View file

@ -199,6 +199,12 @@ config CMSIS_THREAD_MAX_STACK_SIZE
config CMSIS_V2_THREAD_MAX_STACK_SIZE config CMSIS_V2_THREAD_MAX_STACK_SIZE
default 1024 if 64BIT default 1024 if 64BIT
config ARCH_IRQ_VECTOR_TABLE_ALIGN
default 256
config GEN_IRQ_VECTOR_TABLE
select RISCV_MTVEC_VECTORED_MODE if SOC_FAMILY_RISCV_PRIVILEGE
rsource "Kconfig.isa" rsource "Kconfig.isa"
rsource "Kconfig.core" rsource "Kconfig.core"

4
include/zephyr/arch/riscv/arch.h
View file

@ -169,6 +169,10 @@
extern "C" { extern "C" {
#endif #endif
#ifdef CONFIG_IRQ_VECTOR_TABLE_JUMP_BY_CODE
#define ARCH_IRQ_VECTOR_JUMP_CODE(v) "j " STRINGIFY(v)
#endif
/* Kernel macros for memory attribution /* Kernel macros for memory attribution
* (access permissions and cache-ability). * (access permissions and cache-ability).
* *

22
soc/riscv/riscv-privilege/common/vector.S
View file

@ -28,15 +28,15 @@ SECTION_FUNC(vectors, __start)
#if defined(CONFIG_RISCV_MTVEC_VECTORED_MODE) #if defined(CONFIG_RISCV_MTVEC_VECTORED_MODE)
/* /*
* Set mtvec (Machine Trap-Vector Base-Address Register) * Set mtvec (Machine Trap-Vector Base-Address Register)
* to __ivt (interrupt vector table). Add 1 to base * to _irq_vector_table (interrupt vector table). Add 1 to base
* address of __ivt to indicate that vectored mode * address of _irq_vector_table to indicate that vectored mode
* is used (LSB = 0x1). CPU will mask the LSB out of * is used (LSB = 0x1). CPU will mask the LSB out of
* the address so that base address of __ivt is used. * the address so that base address of _irq_vector_table is used.
* *
* NOTE: __ivt is 256-byte aligned. Incorrect alignment * NOTE: _irq_vector_table is 256-byte aligned. Incorrect alignment
* of __ivt breaks this code. * of _irq_vector_table breaks this code.
*/ */
la t0, __ivt /* Load address of interrupt vector table */ la t0, _irq_vector_table /* Load address of interrupt vector table */
addi t0, t0, 1 /* Enable vectored mode by setting LSB */ addi t0, t0, 1 /* Enable vectored mode by setting LSB */
/* MTVEC_DIRECT_MODE */ /* MTVEC_DIRECT_MODE */
@ -52,13 +52,3 @@ SECTION_FUNC(vectors, __start)
/* Jump to __reset */ /* Jump to __reset */
tail __reset tail __reset
#if defined(CONFIG_RISCV_MTVEC_VECTORED_MODE)
SECTION_FUNC(reset, __ivt)
.option push
.option norvc
.balign 0x100 /* must be 256 byte aligned per specification */
.rept (CONFIG_NUM_IRQS)
j _isr_wrapper
.endr
#endif