From 0e788b89a6e4c7a1660aaf5a5dd9a8affbdf34c7 Mon Sep 17 00:00:00 2001 From: Carlo Caione Date: Mon, 27 Jun 2022 10:51:28 +0200 Subject: [PATCH] riscv: Use IRQ vector table for vectored mode For vectored interrupts use the generated IRQ vector table instead of relying on a custom-generated table. Signed-off-by: Carlo Caione --- arch/Kconfig | 1 + arch/riscv/Kconfig | 6 ++++++ include/zephyr/arch/riscv/arch.h | 4 ++++ soc/riscv/riscv-privilege/common/vector.S | 22 ++++++---------------- 4 files changed, 17 insertions(+), 16 deletions(-) diff --git a/arch/Kconfig b/arch/Kconfig index 91388ade3f3..fb054c2a8e7 100644 --- a/arch/Kconfig +++ b/arch/Kconfig @@ -421,6 +421,7 @@ config ARCH_IRQ_VECTOR_TABLE_ALIGN choice IRQ_VECTOR_TABLE_TYPE prompt "IRQ vector table type" depends on GEN_IRQ_VECTOR_TABLE + default IRQ_VECTOR_TABLE_JUMP_BY_CODE if RISCV default IRQ_VECTOR_TABLE_JUMP_BY_ADDRESS config IRQ_VECTOR_TABLE_JUMP_BY_ADDRESS diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index b8030cbd6fe..2ba0858c7ec 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -199,6 +199,12 @@ config CMSIS_THREAD_MAX_STACK_SIZE config CMSIS_V2_THREAD_MAX_STACK_SIZE default 1024 if 64BIT +config ARCH_IRQ_VECTOR_TABLE_ALIGN + default 256 + +config GEN_IRQ_VECTOR_TABLE + select RISCV_MTVEC_VECTORED_MODE if SOC_FAMILY_RISCV_PRIVILEGE + rsource "Kconfig.isa" rsource "Kconfig.core" diff --git a/include/zephyr/arch/riscv/arch.h b/include/zephyr/arch/riscv/arch.h index f9aee50a6a7..c6e930da2e6 100644 --- a/include/zephyr/arch/riscv/arch.h +++ b/include/zephyr/arch/riscv/arch.h @@ -169,6 +169,10 @@ extern "C" { #endif +#ifdef CONFIG_IRQ_VECTOR_TABLE_JUMP_BY_CODE +#define ARCH_IRQ_VECTOR_JUMP_CODE(v) "j " STRINGIFY(v) +#endif + /* Kernel macros for memory attribution * (access permissions and cache-ability). * diff --git a/soc/riscv/riscv-privilege/common/vector.S b/soc/riscv/riscv-privilege/common/vector.S index a47cd81ce3e..712e550969a 100644 --- a/soc/riscv/riscv-privilege/common/vector.S +++ b/soc/riscv/riscv-privilege/common/vector.S @@ -28,15 +28,15 @@ SECTION_FUNC(vectors, __start) #if defined(CONFIG_RISCV_MTVEC_VECTORED_MODE) /* * Set mtvec (Machine Trap-Vector Base-Address Register) - * to __ivt (interrupt vector table). Add 1 to base - * address of __ivt to indicate that vectored mode + * to _irq_vector_table (interrupt vector table). Add 1 to base + * address of _irq_vector_table to indicate that vectored mode * is used (LSB = 0x1). CPU will mask the LSB out of - * the address so that base address of __ivt is used. + * the address so that base address of _irq_vector_table is used. * - * NOTE: __ivt is 256-byte aligned. Incorrect alignment - * of __ivt breaks this code. + * NOTE: _irq_vector_table is 256-byte aligned. Incorrect alignment + * of _irq_vector_table breaks this code. */ - la t0, __ivt /* Load address of interrupt vector table */ + la t0, _irq_vector_table /* Load address of interrupt vector table */ addi t0, t0, 1 /* Enable vectored mode by setting LSB */ /* MTVEC_DIRECT_MODE */ @@ -52,13 +52,3 @@ SECTION_FUNC(vectors, __start) /* Jump to __reset */ tail __reset - -#if defined(CONFIG_RISCV_MTVEC_VECTORED_MODE) -SECTION_FUNC(reset, __ivt) - .option push - .option norvc - .balign 0x100 /* must be 256 byte aligned per specification */ - .rept (CONFIG_NUM_IRQS) - j _isr_wrapper - .endr -#endif