michaelh/zephyr
1
0
Fork 0
Code Releases Activity

boards: mimxrt1170_evk: Enable ethernet for RT1170 evk

Browse source 
Enables ethernet for RT1170 EVK. Tested using samples/net/telnet.

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
This commit is contained in:
Daniel DeGrasse 2022-01-10 15:29:53 -06:00 • committed by Anas Nashif
commit 0d33a3427e
5 changed files with 78 additions and 37 deletions
Download patch file Download diff file Expand all files Collapse all files

7
boards/arm/mimxrt1170_evk/Kconfig.defconfig
View file

@ -42,4 +42,11 @@ endchoice
endif #FLASH endif #FLASH
if NETWORKING
config NET_L2_ETHERNET
default y if CPU_CORTEX_M7 # No cache memory support is required for driver
endif # NETWORKING
endif # BOARD_MIMXRT1170_EVK_CM7 || BOARD_MIMXRT1170_EVK_CM4 endif # BOARD_MIMXRT1170_EVK_CM7 || BOARD_MIMXRT1170_EVK_CM4

56
boards/arm/mimxrt1170_evk/doc/index.rst
View file

@ -117,6 +117,8 @@ features:
+-----------+------------+-------------------------------------+ +-----------+------------+-------------------------------------+
| WATCHDOG | on-chip | watchdog | | WATCHDOG | on-chip | watchdog |
+-----------+------------+-------------------------------------+ +-----------+------------+-------------------------------------+
| ENET | on-chip | ethernet |
+-----------+------------+-------------------------------------+
The default configuration can be found in the defconfig file: The default configuration can be found in the defconfig file:
``boards/arm/mimxrt1170_evk/mimxrt1170_evk_cm7_defconfig`` ``boards/arm/mimxrt1170_evk/mimxrt1170_evk_cm7_defconfig``
@ -128,39 +130,59 @@ Connections and I/Os
The MIMXRT1170 SoC has six pairs of pinmux/gpio controllers. The MIMXRT1170 SoC has six pairs of pinmux/gpio controllers.
+---------------+-----------------+---------------------------+ +-----------------+-----------------+---------------------------+
| Name | Function | Usage | | Name | Function | Usage |
+===============+=================+===========================+ +-----------------+-----------------+---------------------------+
| WAKEUP | GPIO | SW7 | | WAKEUP | GPIO | SW7 |
+---------------+-----------------+---------------------------+ +-----------------+-----------------+---------------------------+
| GPIO_AD_04 | GPIO | LED | | GPIO_AD_04 | GPIO | LED |
+---------------+-----------------+---------------------------+ +-----------------+-----------------+---------------------------+
| GPIO_AD_24 | LPUART1_TX | UART Console | | GPIO_AD_24 | LPUART1_TX | UART Console |
+---------------+-----------------+---------------------------+ +-----------------+-----------------+---------------------------+
| GPIO_AD_25 | LPUART1_RX | UART Console | | GPIO_AD_25 | LPUART1_RX | UART Console |
+---------------+-----------------+---------------------------+ +-----------------+-----------------+---------------------------+
| GPIO_LPSR_00 | CAN3_TX | flexcan | | GPIO_LPSR_00 | CAN3_TX | flexcan |
+---------------+-----------------+---------------------------+ +-----------------+-----------------+---------------------------+
| GPIO_LPSR_01 | CAN3_RX | flexcan | | GPIO_LPSR_01 | CAN3_RX | flexcan |
+---------------+-----------------+---------------------------+ +-----------------+-----------------+---------------------------+
| GPIO_AD_29 | SPI1_CS0 | spi | | GPIO_AD_29 | SPI1_CS0 | spi |
+---------------+-----------------+---------------------------+ +-----------------+-----------------+---------------------------+
| GPIO_AD_28 | SPI1_CLK | spi | | GPIO_AD_28 | SPI1_CLK | spi |
+---------------+-----------------+---------------------------+ +-----------------+-----------------+---------------------------+
| GPIO_AD_30 | SPI1_SDO | spi | | GPIO_AD_30 | SPI1_SDO | spi |
+---------------+-----------------+---------------------------+ +-----------------+-----------------+---------------------------+
| GPIO_AD_31 | SPI1_SDI | spi | | GPIO_AD_31 | SPI1_SDI | spi |
+---------------+-----------------+---------------------------+ +-----------------+-----------------+---------------------------+
| GPIO_AD_08 | LPI2C1_SCL | i2c | | GPIO_AD_08 | LPI2C1_SCL | i2c |
+---------------+-----------------+---------------------------+ +-----------------+-----------------+---------------------------+
| GPIO_AD_09 | LPI2C1_SDA | i2c | | GPIO_AD_09 | LPI2C1_SDA | i2c |
+---------------+-----------------+---------------------------+ +-----------------+-----------------+---------------------------+
| GPIO_LPSR_05 | LPI2C5_SCL | i2c | | GPIO_LPSR_05 | LPI2C5_SCL | i2c |
+---------------+-----------------+---------------------------+ +-----------------+-----------------+---------------------------+
| GPIO_LPSR_04 | LPI2C5_SDA | i2c | | GPIO_LPSR_04 | LPI2C5_SDA | i2c |
+---------------+-----------------+---------------------------+ +-----------------+-----------------+---------------------------+
| GPIO_AD_04 | FLEXPWM1_PWM2 | pwm | | GPIO_AD_04 | FLEXPWM1_PWM2 | pwm |
+---------------+-----------------+---------------------------+ +-----------------+-----------------+---------------------------+
| GPIO_AD_32 | ENET_MDC | Ethernet |
+-----------------+-----------------+---------------------------+
| GPIO_AD_33 | ENET_MDIO | Ethernet |
+-----------------+-----------------+---------------------------+
| GPIO_DISP_B2_02 | ENET_TX_DATA00 | Ethernet |
+-----------------+-----------------+---------------------------+
| GPIO_DISP_B2_03 | ENET_TX_DATA01 | Ethernet |
+-----------------+-----------------+---------------------------+
| GPIO_DISP_B2_04 | ENET_TX_EN | Ethernet |
+-----------------+-----------------+---------------------------+
| GPIO_DISP_B2_05 | ENET_REF_CLK | Ethernet |
+-----------------+-----------------+---------------------------+
| GPIO_DISP_B2_06 | ENET_RX_DATA00 | Ethernet |
+-----------------+-----------------+---------------------------+
| GPIO_DISP_B2_07 | ENET_RX_DATA01 | Ethernet |
+-----------------+-----------------+---------------------------+
| GPIO_DISP_B2_08 | ENET_RX_EN | Ethernet |
+-----------------+-----------------+---------------------------+
| GPIO_DISP_B2_09 | ENET_RX_ER | Ethernet |
+-----------------+-----------------+---------------------------+
System Clock System Clock

7
boards/arm/mimxrt1170_evk/mimxrt1170_evk_cm7.dts
View file

@ -121,3 +121,10 @@
&wdog1 { &wdog1 {
status = "okay"; status = "okay";
}; };
&enet {
status = "okay";
ptp {
status = "okay";
};
};

1
boards/arm/mimxrt1170_evk/mimxrt1170_evk_cm7.yaml
View file

@ -24,3 +24,4 @@ supported:
- pwm - pwm
- dma - dma
- watchdog - watchdog
- netif:eth

12
boards/arm/mimxrt1170_evk/pinmux.c
View file

@ -108,12 +108,13 @@ static int mimxrt1170_evk_init(const struct device *dev)
#endif #endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(enet), okay) && CONFIG_NET_L2_ETHERNET #if DT_NODE_HAS_STATUS(DT_NODELABEL(enet), okay) && CONFIG_NET_L2_ETHERNET
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_12_GPIO9_IO11, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_32_ENET_MDC, 0U); IOMUXC_SetPinMux(IOMUXC_GPIO_AD_32_ENET_MDC, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_33_ENET_MDIO, 0U); IOMUXC_SetPinMux(IOMUXC_GPIO_AD_33_ENET_MDIO, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_DISP_B2_02_ENET_TX_DATA00, 0U); IOMUXC_SetPinMux(IOMUXC_GPIO_DISP_B2_02_ENET_TX_DATA00, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_DISP_B2_03_ENET_TX_DATA01, 0U); IOMUXC_SetPinMux(IOMUXC_GPIO_DISP_B2_03_ENET_TX_DATA01, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_DISP_B2_04_ENET_TX_EN, 0U); IOMUXC_SetPinMux(IOMUXC_GPIO_DISP_B2_04_ENET_TX_EN, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_DISP_B2_05_ENET_REF_CLK1, 1U); IOMUXC_SetPinMux(IOMUXC_GPIO_DISP_B2_05_ENET_REF_CLK, 1U);
IOMUXC_SetPinMux(IOMUXC_GPIO_DISP_B2_06_ENET_RX_DATA00, 1U); IOMUXC_SetPinMux(IOMUXC_GPIO_DISP_B2_06_ENET_RX_DATA00, 1U);
IOMUXC_SetPinMux(IOMUXC_GPIO_DISP_B2_07_ENET_RX_DATA01, 1U); IOMUXC_SetPinMux(IOMUXC_GPIO_DISP_B2_07_ENET_RX_DATA01, 1U);
IOMUXC_SetPinMux(IOMUXC_GPIO_DISP_B2_08_ENET_RX_EN, 0U); IOMUXC_SetPinMux(IOMUXC_GPIO_DISP_B2_08_ENET_RX_EN, 0U);
@ -126,7 +127,7 @@ static int mimxrt1170_evk_init(const struct device *dev)
IOMUXC_SetPinConfig(IOMUXC_GPIO_DISP_B2_02_ENET_TX_DATA00, 0x02U); IOMUXC_SetPinConfig(IOMUXC_GPIO_DISP_B2_02_ENET_TX_DATA00, 0x02U);
IOMUXC_SetPinConfig(IOMUXC_GPIO_DISP_B2_03_ENET_TX_DATA01, 0x02U); IOMUXC_SetPinConfig(IOMUXC_GPIO_DISP_B2_03_ENET_TX_DATA01, 0x02U);
IOMUXC_SetPinConfig(IOMUXC_GPIO_DISP_B2_04_ENET_TX_EN, 0x02U); IOMUXC_SetPinConfig(IOMUXC_GPIO_DISP_B2_04_ENET_TX_EN, 0x02U);
IOMUXC_SetPinConfig(IOMUXC_GPIO_DISP_B2_05_ENET_REF_CLK1, 0x02U); IOMUXC_SetPinConfig(IOMUXC_GPIO_DISP_B2_05_ENET_REF_CLK, 0x03U);
IOMUXC_SetPinConfig(IOMUXC_GPIO_DISP_B2_06_ENET_RX_DATA00, 0x06U); IOMUXC_SetPinConfig(IOMUXC_GPIO_DISP_B2_06_ENET_RX_DATA00, 0x06U);
IOMUXC_SetPinConfig(IOMUXC_GPIO_DISP_B2_07_ENET_RX_DATA01, 0x06U); IOMUXC_SetPinConfig(IOMUXC_GPIO_DISP_B2_07_ENET_RX_DATA01, 0x06U);
IOMUXC_SetPinConfig(IOMUXC_GPIO_DISP_B2_08_ENET_RX_EN, 0x06U); IOMUXC_SetPinConfig(IOMUXC_GPIO_DISP_B2_08_ENET_RX_EN, 0x06U);
@ -138,8 +139,11 @@ static int mimxrt1170_evk_init(const struct device *dev)
GPIO_PinInit(GPIO12, 12, &enet_gpio_config); GPIO_PinInit(GPIO12, 12, &enet_gpio_config);
/* pull up the ENET_INT before RESET. */ /* pull up the ENET_INT before RESET. */
GPIO_WritePinOutput(GPIO1, 11, 1); GPIO_WritePinOutput(GPIO9, 11, 1);
GPIO_WritePinOutput(GPIO1, 12, 0); GPIO_WritePinOutput(GPIO12, 12, 0);
/* 50M ENET_REF_CLOCK output to PHY and ENET module. */
IOMUXC_GPR->GPR4 |= 0x3;
#endif #endif