michaelh/zephyr
1
0
Fork 0
Code Releases Activity

drivers: pwm: minor formatting enhancements

Browse source 
Some formatting tweaks to improve the outcome of clang-format.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
This commit is contained in:
Gerard Marull-Paretas 2022-06-17 16:15:11 +02:00 • committed by Carles Cufí
commit 0aea96dbca
18 changed files with 31 additions and 17 deletions
Download patch file Download diff file Expand all files Collapse all files

1
drivers/pwm/pwm_gd32.c
View file

@ -16,6 +16,7 @@
#include <gd32_timer.h>
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(pwm_gd32, CONFIG_PWM_LOG_LEVEL);
/** PWM data. */

2
drivers/pwm/pwm_gecko.c
View file

@ -74,7 +74,7 @@ static int pwm_gecko_get_cycles_per_sec(const struct device *dev,
static const struct pwm_driver_api pwm_gecko_driver_api = {
.set_cycles = pwm_gecko_set_cycles,
.get_cycles_per_sec = pwm_gecko_get_cycles_per_sec
.get_cycles_per_sec = pwm_gecko_get_cycles_per_sec,
};
static int pwm_gecko_init(const struct device *dev)

1
drivers/pwm/pwm_imx.c
View file

@ -11,6 +11,7 @@
#include <zephyr/drivers/pinctrl.h>
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(pwm_imx, CONFIG_PWM_LOG_LEVEL);
#define PWM_PWMSR_FIFOAV_4WORDS 0x4

1
drivers/pwm/pwm_ite_it8xxx2.c
View file

@ -17,6 +17,7 @@
#include <stdlib.h>
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(pwm_ite_it8xxx2, CONFIG_PWM_LOG_LEVEL);
#define PWM_CTRX_MIN 100

4
drivers/pwm/pwm_mchp_xec.c
View file

@ -84,7 +84,7 @@ static const uint32_t max_freq_high_on_div[NUM_DIV_ELEMS] = {
3692307,
3428571,
3200000,
3000000
3000000,
};
static const uint32_t max_freq_low_on_div[NUM_DIV_ELEMS] = {
@ -103,7 +103,7 @@ static const uint32_t max_freq_low_on_div[NUM_DIV_ELEMS] = {
7692,
7142,
6666,
6250
6250,
};
static uint32_t xec_compute_frequency(uint32_t clk, uint32_t on, uint32_t off)

1
drivers/pwm/pwm_mcux.c
View file

@ -14,6 +14,7 @@
#include <zephyr/drivers/pinctrl.h>
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(pwm_mcux, CONFIG_PWM_LOG_LEVEL);
#define CHANNEL_COUNT 2

1
drivers/pwm/pwm_mcux_ftm.c
View file

@ -16,6 +16,7 @@
#include <zephyr/drivers/pinctrl.h>
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(pwm_mcux_ftm, CONFIG_PWM_LOG_LEVEL);
#define MAX_CHANNELS ARRAY_SIZE(FTM0->CONTROLS)

1
drivers/pwm/pwm_mcux_pwt.c
View file

@ -15,6 +15,7 @@
#include <zephyr/drivers/pinctrl.h>
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(pwm_mcux_pwt, CONFIG_PWM_LOG_LEVEL);
/* Number of PWT input ports */

1
drivers/pwm/pwm_mcux_sctimer.c
View file

@ -16,6 +16,7 @@
#endif
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(pwm_mcux_sctimer, CONFIG_PWM_LOG_LEVEL);
#define CHANNEL_COUNT FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS

1
drivers/pwm/pwm_mcux_tpm.c
View file

@ -19,6 +19,7 @@
#include <zephyr/drivers/pinctrl.h>
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(pwm_mcux_tpm, CONFIG_PWM_LOG_LEVEL);
#define MAX_CHANNELS ARRAY_SIZE(TPM0->CONTROLS)

1
drivers/pwm/pwm_npcx.c
View file

@ -14,6 +14,7 @@
#include <soc.h>
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(pwm_npcx, LOG_LEVEL_ERR);
/* 16-bit period cycles/prescaler in NPCX PWM modules */

23
drivers/pwm/pwm_nrf5_sw.c
View file

@ -15,6 +15,7 @@
#include <nrf_peripherals.h>
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(pwm_nrf5_sw, CONFIG_PWM_LOG_LEVEL);
#define GENERATOR_NODE DT_INST_PHANDLE(0, generator)
@ -232,31 +233,31 @@ static int pwm_nrf5_sw_set_cycles(const struct device *dev, uint32_t channel,
/* setup PPI */
if (USE_RTC) {
NRF_PPI->CH[ppi_chs[0]].EEP =
(uint32_t) &(rtc->EVENTS_COMPARE[1 + channel]);
(uint32_t) &rtc->EVENTS_COMPARE[1 + channel];
NRF_PPI->CH[ppi_chs[0]].TEP =
(uint32_t) &(NRF_GPIOTE->TASKS_OUT[gpiote_ch]);
(uint32_t) &NRF_GPIOTE->TASKS_OUT[gpiote_ch];
NRF_PPI->CH[ppi_chs[1]].EEP =
(uint32_t) &(rtc->EVENTS_COMPARE[0]);
(uint32_t) &rtc->EVENTS_COMPARE[0];
NRF_PPI->CH[ppi_chs[1]].TEP =
(uint32_t) &(NRF_GPIOTE->TASKS_OUT[gpiote_ch]);
(uint32_t) &NRF_GPIOTE->TASKS_OUT[gpiote_ch];
#if defined(PPI_FEATURE_FORKS_PRESENT)
NRF_PPI->FORK[ppi_chs[1]].TEP =
(uint32_t) &(rtc->TASKS_CLEAR);
(uint32_t) &rtc->TASKS_CLEAR;
#else
NRF_PPI->CH[ppi_chs[2]].EEP =
(uint32_t) &(rtc->EVENTS_COMPARE[0]);
(uint32_t) &rtc->EVENTS_COMPARE[0];
NRF_PPI->CH[ppi_chs[2]].TEP =
(uint32_t) &(rtc->TASKS_CLEAR);
(uint32_t) &rtc->TASKS_CLEAR;
#endif
} else {
NRF_PPI->CH[ppi_chs[0]].EEP =
(uint32_t) &(timer->EVENTS_COMPARE[1 + channel]);
(uint32_t) &timer->EVENTS_COMPARE[1 + channel];
NRF_PPI->CH[ppi_chs[0]].TEP =
(uint32_t) &(NRF_GPIOTE->TASKS_OUT[gpiote_ch]);
(uint32_t) &NRF_GPIOTE->TASKS_OUT[gpiote_ch];
NRF_PPI->CH[ppi_chs[1]].EEP =
(uint32_t) &(timer->EVENTS_COMPARE[0]);
(uint32_t) &timer->EVENTS_COMPARE[0];
NRF_PPI->CH[ppi_chs[1]].TEP =
(uint32_t) &(NRF_GPIOTE->TASKS_OUT[gpiote_ch]);
(uint32_t) &NRF_GPIOTE->TASKS_OUT[gpiote_ch];
}
NRF_PPI->CHENSET = ppi_mask;

1
drivers/pwm/pwm_nrfx.c
View file

@ -12,6 +12,7 @@
#include <stdbool.h>
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(pwm_nrfx, CONFIG_PWM_LOG_LEVEL);
#define PWM_NRFX_CH_POLARITY_MASK BIT(15)

1
drivers/pwm/pwm_rv32m1_tpm.c
View file

@ -20,6 +20,7 @@
#endif
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(pwm_rv32m1_tpm, CONFIG_PWM_LOG_LEVEL);
#define MAX_CHANNELS ARRAY_SIZE(TPM0->CONTROLS)

1
drivers/pwm/pwm_sam.c
View file

@ -13,6 +13,7 @@
#include <soc.h>
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(pwm_sam, CONFIG_PWM_LOG_LEVEL);
struct sam_pwm_config {

5
drivers/pwm/pwm_sifive.c
View file

@ -7,15 +7,14 @@
#define DT_DRV_COMPAT sifive_pwm0
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(pwm_sifive, CONFIG_PWM_LOG_LEVEL);
#include <zephyr/sys/sys_io.h>
#include <zephyr/device.h>
#include <zephyr/drivers/pinctrl.h>
#include <zephyr/drivers/pwm.h>
#include <soc.h>
LOG_MODULE_REGISTER(pwm_sifive, CONFIG_PWM_LOG_LEVEL);
/* Macros */
#define PWM_REG(z_config, _offset) ((mem_addr_t) ((z_config)->base + _offset))

1
drivers/pwm/pwm_stm32.c
View file

@ -22,6 +22,7 @@
#include <zephyr/dt-bindings/pwm/stm32_pwm.h>
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(pwm_stm32, CONFIG_PWM_LOG_LEVEL);
/* L0 series MCUs only have 16-bit timers and don't have below macro defined */

1
drivers/pwm/pwm_xlnx_axi_timer.c
View file

@ -10,6 +10,7 @@
#include <zephyr/drivers/pwm.h>
#include <zephyr/sys/sys_io.h>
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(xlnx_axi_timer_pwm, CONFIG_PWM_LOG_LEVEL);
/* AXI Timer v2.0 registers offsets (See Xilinx PG079 for details) */