boards: stm32_min_dev: convert to dt based clock config
Convert the stm32_min_dev boards to the new device tree based config setup. Signed-off-by: Fabio Baltieri <fabio.baltieri@gmail.com>
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525a235fb3
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3 changed files with 21 additions and 32 deletions
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@ -33,6 +33,25 @@
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};
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};
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};
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};
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&clk_hse {
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clock-frequency = <DT_FREQ_M(8)>;
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status = "okay";
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};
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&pll {
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mul = <9>;
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clocks = <&clk_hse>;
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status = "okay";
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};
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&rcc {
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clocks = <&pll>;
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clock-frequency = <DT_FREQ_M(72)>;
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ahb-prescaler = <1>;
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apb1-prescaler = <2>;
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apb2-prescaler = <1>;
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};
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&usart1 {
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&usart1 {
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pinctrl-0 = <&usart1_tx_pa9 &usart1_rx_pa10>;
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pinctrl-0 = <&usart1_tx_pa9 &usart1_rx_pa10>;
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current-speed = <115200>;
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current-speed = <115200>;
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@ -8,9 +8,6 @@
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CONFIG_SOC_SERIES_STM32F1X=y
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CONFIG_SOC_SERIES_STM32F1X=y
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CONFIG_SOC_STM32F103X8=y
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CONFIG_SOC_STM32F103X8=y
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# 72MHz system clock
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CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=72000000
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# Enable MPU
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# Enable MPU
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CONFIG_ARM_MPU=y
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CONFIG_ARM_MPU=y
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@ -30,17 +27,5 @@ CONFIG_PINMUX=y
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# enable GPIO
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# enable GPIO
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CONFIG_GPIO=y
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CONFIG_GPIO=y
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# clock configuration
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# enable clock control
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CONFIG_CLOCK_CONTROL=y
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CONFIG_CLOCK_CONTROL=y
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CONFIG_CLOCK_STM32_HSE_CLOCK=8000000
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CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL=y
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# use HSE as PLL input
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CONFIG_CLOCK_STM32_PLL_SRC_HSE=y
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# produce 72MHz clock at PLL output
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CONFIG_CLOCK_STM32_PLL_MULTIPLIER=9
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CONFIG_CLOCK_STM32_AHB_PRESCALER=1
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# APB1 clock must not exceed 36MHz limit
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CONFIG_CLOCK_STM32_APB1_PRESCALER=2
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CONFIG_CLOCK_STM32_APB2_PRESCALER=1
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@ -3,9 +3,6 @@
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CONFIG_SOC_SERIES_STM32F1X=y
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CONFIG_SOC_SERIES_STM32F1X=y
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CONFIG_SOC_STM32F103X8=y
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CONFIG_SOC_STM32F103X8=y
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# 72MHz system clock
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CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=72000000
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# Enable MPU
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# Enable MPU
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CONFIG_ARM_MPU=y
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CONFIG_ARM_MPU=y
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@ -25,17 +22,5 @@ CONFIG_PINMUX=y
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# enable GPIO
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# enable GPIO
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CONFIG_GPIO=y
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CONFIG_GPIO=y
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# clock configuration
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# enable clock control
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CONFIG_CLOCK_CONTROL=y
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CONFIG_CLOCK_CONTROL=y
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CONFIG_CLOCK_STM32_HSE_CLOCK=8000000
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CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL=y
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# use HSE as PLL input
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CONFIG_CLOCK_STM32_PLL_SRC_HSE=y
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# produce 72MHz clock at PLL output
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CONFIG_CLOCK_STM32_PLL_MULTIPLIER=9
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CONFIG_CLOCK_STM32_AHB_PRESCALER=1
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# APB1 clock must not exceed 36MHz limit
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CONFIG_CLOCK_STM32_APB1_PRESCALER=2
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CONFIG_CLOCK_STM32_APB2_PRESCALER=1
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