drivers/pinmux: stm32f1: Rework pinmux remap information encoding
Aim of this change is to remove the need for the pinmux driver on stm32f1 series to access the base address of the pinmux owner device. This is achieved by a modification in the device tree pin definition. Instead of providing a generic information on type of the remap (such as NO_REMAP, PARTIAL_REMAP, FULL_REMAP), the remap field encodes all the information required to perform the remap register configuration: -Address of the targeted remap register in AFIO peripheral -Position of the remap configuration in the remap register -Mask used for the remap configuration encoding -Value of the expected remap configuration. All the possible remap configurations are encoded and predefined in a new stm32f1-afio.h dt-bindings include. To match this new configuration, all stm32f1 -pinctrl.dtsi should be regenerated to use these new remap definitions. Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
This commit is contained in:
Erwan Gouriou
Anas Nashif
parent
c35ed25a63
commit
097cb02e59
4 changed files with 239 additions and 263 deletions
212
include/dt-bindings/pinctrl/stm32f1-afio.h
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212
include/dt-bindings/pinctrl/stm32f1-afio.h
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/*
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* Copyright (c) 2021 Linaro Limited
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_STM32_AFIO_H_
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#define ZEPHYR_STM32_AFIO_H_
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/**
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* @brief STM32F1 Remap configuration bit field.
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*
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* - reg (0/1) [ 0 : 0 ]
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* - shift (0..31) [ 1 : 5 ]
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* - mask (0x1, 0x3) [ 6 : 7 ]
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* - val (0..3) [ 8 : 9 ]
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*
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* @param reg AFIO_MAPRx register (MAPR, MAPR2).
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* @param shift Position within AFIO_MAPRx.
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* @param mask Mask for the AFIO_MAPRx field.
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* @param val Remap value (0, 1, 2 or 3).
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*/
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#define STM32_REMAP_REG_MASK 0x1U
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#define STM32_REMAP_REG_SHIFT 0U
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#define STM32_REMAP_SHIFT_MASK 0x1FU
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#define STM32_REMAP_SHIFT_SHIFT 1U
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#define STM32_REMAP_MASK_MASK 0x3U
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#define STM32_REMAP_MASK_SHIFT 6U
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#define STM32_REMAP_VAL_MASK 0x3U
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#define STM32_REMAP_VAL_SHIFT 8U
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#define STM32_REMAP(val, mask, shift, reg) \
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((((reg) & STM32_REMAP_REG_MASK) << STM32_REMAP_REG_SHIFT) | \
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(((shift) & STM32_REMAP_SHIFT_MASK) << STM32_REMAP_SHIFT_SHIFT) | \
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(((mask) & STM32_REMAP_MASK_MASK) << STM32_REMAP_MASK_SHIFT) | \
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(((val) & STM32_REMAP_VAL_MASK) << STM32_REMAP_VAL_SHIFT))
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/* Accessors for remap value */
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/**
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* Obtain register field from remap configuration.
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*
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* @param remap Remap bit field value.
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*/
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#define STM32_REMAP_REG_GET(remap) \
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(((remap) >> STM32_REMAP_REG_SHIFT) & STM32_REMAP_REG_MASK)
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/**
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* Obtain position field from remap configuration.
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*
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* @param remap Remap bit field value.
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*/
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#define STM32_REMAP_SHIFT_GET(remap) \
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(((remap) >> STM32_REMAP_SHIFT_SHIFT) & STM32_REMAP_SHIFT_MASK)
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/**
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* Obtain mask field from remap configuration.
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*
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* @param remap Remap bit field value.
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*/
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#define STM32_REMAP_MASK_GET(remap) \
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(((remap) >> STM32_REMAP_MASK_SHIFT) & STM32_REMAP_MASK_MASK)
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/**
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* Obtain value field from remap configuration.
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*
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* @param remap Remap bit field value.
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*/
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#define STM32_REMAP_VAL_GET(remap) \
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(((remap) >> STM32_REMAP_VAL_SHIFT) & STM32_REMAP_VAL_MASK)
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/* Remap values definitions, according to RM0008.pdf */
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#define STM32_AFIO_MAPR 0U
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#define STM32_AFIO_MAPR2 1U
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/** Device not remappable **/
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#define NO_REMAP 0
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/** SPI1 (no remap) */
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#define SPI1_REMAP0 STM32_REMAP(0U, 0x1U, 0U, STM32_AFIO_MAPR)
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/** SPI1 (remap) */
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#define SPI1_REMAP1 STM32_REMAP(1U, 0x1U, 0U, STM32_AFIO_MAPR)
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/** I2C1 (no remap) */
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#define I2C1_REMAP0 STM32_REMAP(0U, 0x1U, 1U, STM32_AFIO_MAPR)
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/** I2C1 (remap) */
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#define I2C1_REMAP1 STM32_REMAP(1U, 0x1U, 1U, STM32_AFIO_MAPR)
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/** USART1 (no remap) */
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#define USART1_REMAP0 STM32_REMAP(0U, 0x1U, 2U, STM32_AFIO_MAPR)
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/** USART1 (remap) */
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#define USART1_REMAP1 STM32_REMAP(1U, 0x1U, 2U, STM32_AFIO_MAPR)
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/** USART2 (no remap) */
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#define USART2_REMAP0 STM32_REMAP(0U, 0x1U, 3U, STM32_AFIO_MAPR)
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/** USART2 (remap) */
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#define USART2_REMAP1 STM32_REMAP(1U, 0x1U, 3U, STM32_AFIO_MAPR)
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/** USART3 (no remap) */
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#define USART3_REMAP0 STM32_REMAP(0U, 0x3U, 4U, STM32_AFIO_MAPR)
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/** USART3 (partial remap) */
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#define USART3_REMAP1 STM32_REMAP(1U, 0x3U, 4U, STM32_AFIO_MAPR)
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/** USART3 (full remap) */
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#define USART3_REMAP2 STM32_REMAP(3U, 0x3U, 4U, STM32_AFIO_MAPR)
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/** TIM1 (no remap) */
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#define TIM1_REMAP0 STM32_REMAP(0U, 0x3U, 6U, STM32_AFIO_MAPR)
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/** TIM1 (partial remap) */
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#define TIM1_REMAP1 STM32_REMAP(1U, 0x3U, 6U, STM32_AFIO_MAPR)
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/** TIM1 (full remap) */
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#define TIM1_REMAP2 STM32_REMAP(3U, 0x3U, 6U, STM32_AFIO_MAPR)
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/** TIM2 (no remap) */
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#define TIM2_REMAP0 STM32_REMAP(0U, 0x3U, 8U, STM32_AFIO_MAPR)
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/** TIM2 (partial remap 1) */
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#define TIM2_REMAP1 STM32_REMAP(1U, 0x3U, 8U, STM32_AFIO_MAPR)
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/** TIM2 (partial remap 2) */
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#define TIM2_REMAP2 STM32_REMAP(2U, 0x3U, 8U, STM32_AFIO_MAPR)
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/** TIM2 (full remap) */
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#define TIM2_REMAP3 STM32_REMAP(3U, 0x3U, 8U, STM32_AFIO_MAPR)
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/** TIM3 (no remap) */
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#define TIM3_REMAP0 STM32_REMAP(0U, 0x3U, 10U, STM32_AFIO_MAPR)
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/** TIM3 (partial remap 1) */
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#define TIM3_REMAP1 STM32_REMAP(1U, 0x3U, 10U, STM32_AFIO_MAPR)
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/** TIM3 (partial remap 2) */
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#define TIM3_REMAP2 STM32_REMAP(2U, 0x3U, 10U, STM32_AFIO_MAPR)
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/** TIM3 (full remap) */
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#define TIM3_REMAP3 STM32_REMAP(3U, 0x3U, 10U, STM32_AFIO_MAPR)
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/** TIM4 (no remap) */
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#define TIM4_REMAP0 STM32_REMAP(0U, 0x1U, 12U, STM32_AFIO_MAPR)
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/** TIM4 (remap) */
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#define TIM4_REMAP1 STM32_REMAP(1U, 0x1U, 12U, STM32_AFIO_MAPR)
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/** CAN (no remap) */
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#define CAN_REMAP0 STM32_REMAP(0U, 0x3U, 13U, STM32_AFIO_MAPR)
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/** CAN (partial remap) */
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#define CAN_REMAP1 STM32_REMAP(2U, 0x3U, 13U, STM32_AFIO_MAPR)
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/** CAN (full remap) */
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#define CAN_REMAP2 STM32_REMAP(3U, 0x3U, 13U, STM32_AFIO_MAPR)
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/** CAN1 alias */
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#define CAN1_REMAP0 CAN_REMAP0
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#define CAN1_REMAP1 CAN_REMAP1
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#define CAN1_REMAP2 CAN_REMAP2
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/** ETH (no remap) */
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#define ETH_REMAP0 STM32_REMAP(0U, 0x1U, 20U, STM32_AFIO_MAPR)
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/** ETH (remap) */
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#define ETH_REMAP1 STM32_REMAP(1U, 0x1U, 20U, STM32_AFIO_MAPR)
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/** CAN2 (no remap) */
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#define CAN2_REMAP0 STM32_REMAP(0U, 0x1U, 21U, STM32_AFIO_MAPR)
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/** CAN2 (remap) */
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#define CAN2_REMAP1 STM32_REMAP(1U, 0x1U, 21U, STM32_AFIO_MAPR)
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/** SPI3 (no remap) */
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#define SPI3_REMAP0 STM32_REMAP(0U, 0x1U, 27U, STM32_AFIO_MAPR)
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/** SPI3 (remap) */
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#define SPI3_REMAP1 STM32_REMAP(1U, 0x1U, 27U, STM32_AFIO_MAPR)
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/** I2S3 (SPI3) (no remap) */
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#define I2S3_REMAP0 SPI3_REMAP0
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/** I2S3 (SPI3) (remap) */
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#define I2S3_REMAP1 SPI3_REMAP1
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/** TIM9 (no remap) */
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#define TIM9_REMAP0 STM32_REMAP(0U, 0x1U, 5U, STM32_AFIO_MAPR2)
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/** TIM9 (remap) */
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#define TIM9_REMAP1 STM32_REMAP(1U, 0x1U, 5U, STM32_AFIO_MAPR2)
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/** TIM10 (no remap) */
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#define TIM10_REMAP0 STM32_REMAP(0U, 0x1U, 6U, STM32_AFIO_MAPR2)
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/** TIM10 (remap) */
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#define TIM10_REMAP1 STM32_REMAP(1U, 0x1U, 6U, STM32_AFIO_MAPR2)
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/** TIM11 (no remap) */
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#define TIM11_REMAP0 STM32_REMAP(0U, 0x1U, 7U, STM32_AFIO_MAPR2)
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/** TIM11 (remap) */
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#define TIM11_REMAP1 STM32_REMAP(1U, 0x1U, 7U, STM32_AFIO_MAPR2)
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/** TIM13 (no remap) */
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#define TIM13_REMAP0 STM32_REMAP(0U, 0x1U, 8U, STM32_AFIO_MAPR2)
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/** TIM13 (remap) */
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#define TIM13_REMAP1 STM32_REMAP(1U, 0x1U, 8U, STM32_AFIO_MAPR2)
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/** TIM14 (no remap) */
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#define TIM14_REMAP0 STM32_REMAP(0U, 0x1U, 9U, STM32_AFIO_MAPR2)
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/** TIM14 (remap) */
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#define TIM14_REMAP1 STM32_REMAP(1U, 0x1U, 9U, STM32_AFIO_MAPR2)
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/** TIM15 (no remap) */
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#define TIM15_REMAP0 STM32_REMAP(0U, 0x1U, 0U, STM32_AFIO_MAPR2)
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/** TIM15 (remap) */
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#define TIM15_REMAP1 STM32_REMAP(1U, 0x1U, 0U, STM32_AFIO_MAPR2)
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/** TIM16 (no remap) */
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#define TIM16_REMAP0 STM32_REMAP(0U, 0x1U, 1U, STM32_AFIO_MAPR2)
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/** TIM16 (remap) */
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#define TIM16_REMAP1 STM32_REMAP(1U, 0x1U, 1U, STM32_AFIO_MAPR2)
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/** TIM17 (no remap) */
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#define TIM17_REMAP0 STM32_REMAP(0U, 0x1U, 2U, STM32_AFIO_MAPR2)
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/** TIM17 (remap) */
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#define TIM17_REMAP1 STM32_REMAP(1U, 0x1U, 2U, STM32_AFIO_MAPR2)
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#endif /* ZEPHYR_STM32_AFIO_H_ */
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@ -8,6 +8,7 @@
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#define ZEPHYR_STM32_PINCTRLF1_H_
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#include <dt-bindings/pinctrl/stm32-pinctrl-common.h>
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#include <dt-bindings/pinctrl/stm32f1-afio.h>
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/* Adapted from Linux: include/dt-bindings/pinctrl/stm32-pinfunc.h */
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@ -24,7 +25,7 @@
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* - mode [ 0 : 1 ]
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* - line [ 2 : 5 ]
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* - port [ 6 : 9 ]
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* - remap [ 10 : 12 ]
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* - remap [ 10 : 19 ]
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*
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* @param port Port ('A'..'K')
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* @param line Pin (0..15)
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@ -39,7 +40,7 @@
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#define STM32_PORT_SHIFT 6U
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#define STM32_PORT_MASK 0xFU
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#define STM32_REMAP_SHIFT 10U
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#define STM32_REMAP_MASK 0x1FU
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#define STM32_REMAP_MASK 0x3FFU
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#define STM32F1_PINMUX(port, line, mode, remap) \
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(((((port) - 'A') & STM32_PORT_MASK) << STM32_PORT_SHIFT) | \
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@ -55,16 +56,6 @@
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#define GPIO_IN 0x1 /* Input */
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#define ANALOG 0x2 /* Analog */
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/**
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* @brief Pin remapping configurations
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*/
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#define NO_REMAP 0x0 /* No remapping */
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#define REMAP_1 0x1 /* Partial remapping 1 */
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#define REMAP_2 0x2 /* Partial remapping 2 */
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#define REMAP_3 0x3 /* Partial remapping 3 */
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#define REMAP_FULL 0x4 /* Full remapping */
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/**
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* @brief PIN configuration bitfield
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*
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