diff --git a/drivers/pinmux/pinmux_stm32.c b/drivers/pinmux/pinmux_stm32.c
index d004a542808..a77f59ff3ae 100644
--- a/drivers/pinmux/pinmux_stm32.c
+++ b/drivers/pinmux/pinmux_stm32.c
@@ -143,7 +143,7 @@ int stm32_dt_pinctrl_configure(const struct soc_gpio_pinctrl *pinctrl,
 	}
 
 #if DT_HAS_COMPAT_STATUS_OKAY(st_stm32f1_pinctrl)
-	if (stm32_dt_pinctrl_remap(pinctrl, list_size, base)) {
+	if (stm32_dt_pinctrl_remap(pinctrl, list_size)) {
 		/* Wrong remap config. Exit */
 		return -EINVAL;
 	}
@@ -199,37 +199,6 @@ int stm32_dt_pinctrl_configure(const struct soc_gpio_pinctrl *pinctrl,
 }
 
 #if DT_HAS_COMPAT_STATUS_OKAY(st_stm32f1_pinctrl)
-/* Z_AFIO_REMAP is keeping the value of AFIO_MAPR_SWJ_CFG_x */
-#if defined(CONFIG_GPIO_STM32_SWJ_ENABLE)
-/* reset state */
-#define Z_AFIO_REMAP AFIO_MAPR_SWJ_CFG_RESET
-#elif defined(CONFIG_GPIO_STM32_SWJ_NONJTRST)
-/* released PB4 */
-#define Z_AFIO_REMAP AFIO_MAPR_SWJ_CFG_NOJNTRST
-#elif defined(CONFIG_GPIO_STM32_SWJ_NOJTAG)
-/* released PB4 PB3 PA15 */
-#define Z_AFIO_REMAP AFIO_MAPR_SWJ_CFG_JTAGDISABLE
-#elif defined(CONFIG_GPIO_STM32_SWJ_DISABLE)
-/* released PB4 PB3 PA13 PA14 PA15 */
-#define Z_AFIO_REMAP AFIO_MAPR_SWJ_CFG_DISABLE
-#endif
-
-/* enable remap : modify MAPR and keep the AFIO_MAPR_SWJ_CFG_x */
-#define enable_remap(REMAP_PIN) MODIFY_REG(AFIO->MAPR,\
-					   (REMAP_PIN | AFIO_MAPR_SWJ_CFG), \
-					   (REMAP_PIN | Z_AFIO_REMAP))
-
-/* enable partial remap : modify MAPR and keep the AFIO_MAPR_SWJ_CFG_x */
-#define enable_partial_remap(REMAP_PIN, PARTIAL_REMAP) \
-				MODIFY_REG(AFIO->MAPR, \
-					   (REMAP_PIN | AFIO_MAPR_SWJ_CFG), \
-					   (PARTIAL_REMAP | Z_AFIO_REMAP))
-
-/* disable remap : modify MAPR and keep the AFIO_MAPR_SWJ_CFG_x */
-#define disable_remap(REMAP_PIN) MODIFY_REG(AFIO->MAPR,\
-					    (REMAP_PIN | AFIO_MAPR_SWJ_CFG), \
-					    Z_AFIO_REMAP)
-
 /**
  * @brief Helper function to check and apply provided pinctrl remap
  *        configuration
@@ -239,17 +208,24 @@ int stm32_dt_pinctrl_configure(const struct soc_gpio_pinctrl *pinctrl,
  *
  * @param *pinctrl pointer to soc_gpio_pinctrl list
  * @param list_size list size
- * @param base device base register value
  *
  * @return 0 on success, -EINVAL otherwise
  */
 int stm32_dt_pinctrl_remap(const struct soc_gpio_pinctrl *pinctrl,
-			   size_t list_size, uint32_t base)
+			   size_t list_size)
 {
-	uint8_t remap;
+	uint8_t pos;
+	uint32_t reg_val;
+	volatile uint32_t *reg;
+	uint16_t remap;
 
 	remap = (uint8_t)STM32_DT_PINMUX_REMAP(pinctrl[0].pinmux);
 
+	/* not remappable */
+	if (remap == NO_REMAP) {
+		return 0;
+	}
+
 	for (size_t i = 1U; i < list_size; i++) {
 		if (STM32_DT_PINMUX_REMAP(pinctrl[i].pinmux) != remap) {
 			return -EINVAL;
@@ -260,222 +236,20 @@ int stm32_dt_pinctrl_remap(const struct soc_gpio_pinctrl *pinctrl,
 	/* Apply remapping before proceeding with pin configuration */
 	LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_AFIO);
 
-	switch (base) {
-#if DT_NODE_HAS_STATUS(DT_NODELABEL(can1), okay)
-	case DT_REG_ADDR(DT_NODELABEL(can1)):
-		if (remap == REMAP_1) {
-			/* PB8/PB9 (CAN_REMAP = 0b10) */
-			enable_partial_remap(AFIO_MAPR_CAN_REMAP,
-				AFIO_MAPR_CAN_REMAP_REMAP2);
-		} else if (remap == REMAP_2) {
-			/* PD0/PD1  (CAN_REMAP = 0b11) */
-			enable_partial_remap(AFIO_MAPR_CAN_REMAP,
-				AFIO_MAPR_CAN_REMAP_REMAP3);
-		} else {
-			/* NO_REMAP: PA11/PA12 (CAN_REMAP = 0b00) */
-			enable_partial_remap(AFIO_MAPR_CAN_REMAP,
-				AFIO_MAPR_CAN_REMAP_REMAP1);
-		}
-		break;
-#endif
-#if DT_NODE_HAS_STATUS(DT_NODELABEL(can2), okay)
-	case DT_REG_ADDR(DT_NODELABEL(can2)):
-		if (remap == REMAP_1) {
-			/* PB5/PB6 */
-			enable_remap(AFIO_MAPR_CAN2_REMAP);
-		} else {
-			/* PB12/PB13 */
-			disable_remap(AFIO_MAPR_CAN2_REMAP);
-		}
-		break;
-#endif
-#if DT_NODE_HAS_STATUS(DT_NODELABEL(i2c1), okay)
-	case DT_REG_ADDR(DT_NODELABEL(i2c1)):
-		if (remap == REMAP_1) {
-			enable_remap(AFIO_MAPR_I2C1_REMAP);
-		} else {
-			disable_remap(AFIO_MAPR_I2C1_REMAP);
-		}
-		break;
-#endif
-#if DT_NODE_HAS_STATUS(DT_NODELABEL(timers1), okay)
-	case DT_REG_ADDR(DT_NODELABEL(timers1)):
-		if (remap == REMAP_1) {
-			enable_partial_remap(AFIO_MAPR_TIM1_REMAP,
-				AFIO_MAPR_TIM1_REMAP_PARTIALREMAP);
-		} else if (remap == REMAP_2) {
-			enable_partial_remap(AFIO_MAPR_TIM1_REMAP,
-				AFIO_MAPR_TIM1_REMAP_FULLREMAP);
-		} else {
-			enable_partial_remap(AFIO_MAPR_TIM1_REMAP,
-				AFIO_MAPR_TIM1_REMAP_NOREMAP);
-		}
-		break;
-#endif
-#if DT_NODE_HAS_STATUS(DT_NODELABEL(timers2), okay)
-	case DT_REG_ADDR(DT_NODELABEL(timers2)):
-		if (remap == REMAP_1) {
-			enable_partial_remap(AFIO_MAPR_TIM2_REMAP,
-				AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1);
-		} else if (remap == REMAP_2) {
-			enable_partial_remap(AFIO_MAPR_TIM2_REMAP,
-				AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2);
-		} else if (remap == REMAP_FULL) {
-			enable_partial_remap(AFIO_MAPR_TIM2_REMAP,
-				AFIO_MAPR_TIM2_REMAP_FULLREMAP);
-		} else {
-			enable_partial_remap(AFIO_MAPR_TIM2_REMAP,
-				AFIO_MAPR_TIM2_REMAP_NOREMAP);
-		}
-		break;
-#endif
-#if DT_NODE_HAS_STATUS(DT_NODELABEL(timers3), okay)
-	case DT_REG_ADDR(DT_NODELABEL(timers3)):
-		if (remap == REMAP_1) {
-			enable_partial_remap(AFIO_MAPR_TIM3_REMAP,
-				AFIO_MAPR_TIM3_REMAP_PARTIALREMAP);
-		} else if (remap == REMAP_2) {
-			enable_partial_remap(AFIO_MAPR_TIM3_REMAP,
-				AFIO_MAPR_TIM3_REMAP_FULLREMAP);
-		} else {
-			enable_partial_remap(AFIO_MAPR_TIM3_REMAP,
-				AFIO_MAPR_TIM3_REMAP_NOREMAP);
-		}
-		break;
-#endif
-#if DT_NODE_HAS_STATUS(DT_NODELABEL(timers4), okay)
-	case DT_REG_ADDR(DT_NODELABEL(timers4)):
-		if (remap == REMAP_1) {
-			enable_remap(AFIO_MAPR_TIM4_REMAP);
-		} else {
-			disable_remap(AFIO_MAPR_TIM4_REMAP);
-		}
-		break;
-#endif
-#if DT_NODE_HAS_STATUS(DT_NODELABEL(timers9), okay)
-	case DT_REG_ADDR(DT_NODELABEL(timers9)):
-		if (remap == REMAP_1) {
-			LL_GPIO_AF_EnableRemap_TIM9();
-		} else {
-			LL_GPIO_AF_DisableRemap_TIM9();
-		}
-		break;
-#endif
-#if DT_NODE_HAS_STATUS(DT_NODELABEL(timers10), okay)
-	case DT_REG_ADDR(DT_NODELABEL(timers10)):
-		if (remap == REMAP_1) {
-			LL_GPIO_AF_EnableRemap_TIM10();
-		} else {
-			LL_GPIO_AF_DisableRemap_TIM10();
-		}
-		break;
-#endif
-#if DT_NODE_HAS_STATUS(DT_NODELABEL(timers11), okay)
-	case DT_REG_ADDR(DT_NODELABEL(timers11)):
-		if (remap == REMAP_1) {
-			LL_GPIO_AF_EnableRemap_TIM11();
-		} else {
-			LL_GPIO_AF_DisableRemap_TIM11();
-		}
-		break;
-#endif
-#if DT_NODE_HAS_STATUS(DT_NODELABEL(timers12), okay)
-	case DT_REG_ADDR(DT_NODELABEL(timers12)):
-		if (remap == REMAP_1) {
-			LL_GPIO_AF_EnableRemap_TIM12();
-		} else {
-			LL_GPIO_AF_DisableRemap_TIM12();
-		}
-		break;
-#endif
-#if DT_NODE_HAS_STATUS(DT_NODELABEL(timers13), okay)
-	case DT_REG_ADDR(DT_NODELABEL(timers13)):
-		if (remap == REMAP_1) {
-			LL_GPIO_AF_EnableRemap_TIM13();
-		} else {
-			LL_GPIO_AF_DisableRemap_TIM13();
-		}
-		break;
-#endif
-#if DT_NODE_HAS_STATUS(DT_NODELABEL(timers14), okay)
-	case DT_REG_ADDR(DT_NODELABEL(timers14)):
-		if (remap == REMAP_1) {
-			LL_GPIO_AF_EnableRemap_TIM14();
-		} else {
-			LL_GPIO_AF_DisableRemap_TIM14();
-		}
-		break;
-#endif
-#if DT_NODE_HAS_STATUS(DT_NODELABEL(timers15), okay)
-	case DT_REG_ADDR(DT_NODELABEL(timers15)):
-		if (remap == REMAP_1) {
-			LL_GPIO_AF_EnableRemap_TIM15();
-		} else {
-			LL_GPIO_AF_DisableRemap_TIM15();
-		}
-		break;
-#endif
-#if DT_NODE_HAS_STATUS(DT_NODELABEL(timers16), okay)
-	case DT_REG_ADDR(DT_NODELABEL(timers16)):
-		if (remap == REMAP_1) {
-			LL_GPIO_AF_EnableRemap_TIM16();
-		} else {
-			LL_GPIO_AF_DisableRemap_TIM16();
-		}
-		break;
-#endif
-#if DT_NODE_HAS_STATUS(DT_NODELABEL(timers17), okay)
-	case DT_REG_ADDR(DT_NODELABEL(timers17)):
-		if (remap == REMAP_1) {
-			LL_GPIO_AF_EnableRemap_TIM17();
-		} else {
-			LL_GPIO_AF_DisableRemap_TIM17();
-		}
-		break;
-#endif
-#if DT_NODE_HAS_STATUS(DT_NODELABEL(usart1), okay)
-	case DT_REG_ADDR(DT_NODELABEL(usart1)):
-		if (remap == REMAP_1) {
-			enable_remap(AFIO_MAPR_USART1_REMAP);
-		} else {
-			disable_remap(AFIO_MAPR_USART1_REMAP);
-		}
-		break;
-#endif
-#if DT_NODE_HAS_STATUS(DT_NODELABEL(usart2), okay)
-	case DT_REG_ADDR(DT_NODELABEL(usart2)):
-		if (remap == REMAP_1) {
-			enable_remap(AFIO_MAPR_USART2_REMAP);
-		} else {
-			disable_remap(AFIO_MAPR_USART2_REMAP);
-		}
-		break;
-#endif
-#if DT_NODE_HAS_STATUS(DT_NODELABEL(usart3), okay)
-	case DT_REG_ADDR(DT_NODELABEL(usart3)):
-		if (remap == REMAP_2) {
-			enable_partial_remap(AFIO_MAPR_USART3_REMAP,
-				AFIO_MAPR_USART3_REMAP_FULLREMAP);
-		} else if (remap == REMAP_1) {
-			enable_partial_remap(AFIO_MAPR_USART3_REMAP,
-				AFIO_MAPR_USART3_REMAP_PARTIALREMAP);
-		} else {
-			enable_partial_remap(AFIO_MAPR_USART3_REMAP,
-				AFIO_MAPR_USART3_REMAP_NOREMAP);
-		}
-		break;
-#endif
-#if DT_NODE_HAS_STATUS(DT_NODELABEL(spi1), okay)
-	case DT_REG_ADDR(DT_NODELABEL(spi1)):
-		if (remap == REMAP_1) {
-			enable_remap(AFIO_MAPR_SPI1_REMAP);
-		} else {
-			disable_remap(AFIO_MAPR_SPI1_REMAP);
-		}
-		break;
-#endif
+	if (STM32_REMAP_REG_GET(remap) == 0U) {
+		reg = &AFIO->MAPR;
+	} else {
+		reg = &AFIO->MAPR2;
 	}
 
+	pos = STM32_REMAP_SHIFT_GET(remap);
+
+	reg_val = *reg;
+	reg_val &= ~(STM32_REMAP_MASK_GET(remap) << pos);
+	reg_val |= STM32_REMAP_VAL_GET(remap) << pos;
+	*reg = reg_val;
+
 	return 0;
 }
+
 #endif /* DT_HAS_COMPAT_STATUS_OKAY(st_stm32f1_pinctrl) */
diff --git a/drivers/pinmux/pinmux_stm32.h b/drivers/pinmux/pinmux_stm32.h
index 6606b83cb85..acfceaeb8c6 100644
--- a/drivers/pinmux/pinmux_stm32.h
+++ b/drivers/pinmux/pinmux_stm32.h
@@ -99,12 +99,11 @@ int stm32_dt_pinctrl_configure(const struct soc_gpio_pinctrl *pinctrl,
  *
  * @param *pinctrl pointer to soc_gpio_pinctrl list
  * @param list_size list size
- * @param base device base register value
  *
  * @return 0 value on success, -EINVAL otherwise
  */
 int stm32_dt_pinctrl_remap(const struct soc_gpio_pinctrl *pinctrl,
-			   size_t list_size, uint32_t base);
+			   size_t list_size);
 #endif /* DT_HAS_COMPAT_STATUS_OKAY(st_stm32f1_pinctrl) */
 
 #ifdef __cplusplus
diff --git a/include/dt-bindings/pinctrl/stm32f1-afio.h b/include/dt-bindings/pinctrl/stm32f1-afio.h
new file mode 100644
index 00000000000..b9bc2928cfc
--- /dev/null
+++ b/include/dt-bindings/pinctrl/stm32f1-afio.h
@@ -0,0 +1,212 @@
+/*
+ * Copyright (c) 2021 Linaro Limited
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_STM32_AFIO_H_
+#define ZEPHYR_STM32_AFIO_H_
+
+/**
+ * @brief STM32F1 Remap configuration bit field.
+ *
+ * - reg   (0/1)      [ 0 : 0 ]
+ * - shift (0..31)    [ 1 : 5 ]
+ * - mask  (0x1, 0x3) [ 6 : 7 ]
+ * - val   (0..3)     [ 8 : 9 ]
+ *
+ * @param reg AFIO_MAPRx register (MAPR, MAPR2).
+ * @param shift Position within AFIO_MAPRx.
+ * @param mask Mask for the AFIO_MAPRx field.
+ * @param val Remap value (0, 1, 2 or 3).
+ */
+
+#define STM32_REMAP_REG_MASK    0x1U
+#define STM32_REMAP_REG_SHIFT   0U
+#define STM32_REMAP_SHIFT_MASK  0x1FU
+#define STM32_REMAP_SHIFT_SHIFT 1U
+#define STM32_REMAP_MASK_MASK   0x3U
+#define STM32_REMAP_MASK_SHIFT  6U
+#define STM32_REMAP_VAL_MASK    0x3U
+#define STM32_REMAP_VAL_SHIFT   8U
+
+#define STM32_REMAP(val, mask, shift, reg)				       \
+	((((reg) & STM32_REMAP_REG_MASK) << STM32_REMAP_REG_SHIFT) |	       \
+	 (((shift) & STM32_REMAP_SHIFT_MASK) << STM32_REMAP_SHIFT_SHIFT) |     \
+	 (((mask) & STM32_REMAP_MASK_MASK) << STM32_REMAP_MASK_SHIFT) |	       \
+	 (((val) & STM32_REMAP_VAL_MASK) << STM32_REMAP_VAL_SHIFT))
+
+
+/* Accessors for remap value */
+
+/**
+ * Obtain register field from remap configuration.
+ *
+ * @param remap Remap bit field value.
+ */
+#define STM32_REMAP_REG_GET(remap) \
+	(((remap) >> STM32_REMAP_REG_SHIFT) & STM32_REMAP_REG_MASK)
+
+/**
+ * Obtain position field from remap configuration.
+ *
+ * @param remap Remap bit field value.
+ */
+#define STM32_REMAP_SHIFT_GET(remap) \
+	(((remap) >> STM32_REMAP_SHIFT_SHIFT) & STM32_REMAP_SHIFT_MASK)
+
+/**
+ * Obtain mask field from remap configuration.
+ *
+ * @param remap Remap bit field value.
+ */
+#define STM32_REMAP_MASK_GET(remap) \
+	(((remap) >> STM32_REMAP_MASK_SHIFT) & STM32_REMAP_MASK_MASK)
+
+/**
+ * Obtain value field from remap configuration.
+ *
+ * @param remap Remap bit field value.
+ */
+#define STM32_REMAP_VAL_GET(remap) \
+	(((remap) >> STM32_REMAP_VAL_SHIFT) & STM32_REMAP_VAL_MASK)
+
+
+/* Remap values definitions, according to RM0008.pdf */
+
+#define STM32_AFIO_MAPR		0U
+#define STM32_AFIO_MAPR2	1U
+
+/** Device not remappable **/
+#define NO_REMAP		0
+
+/** SPI1 (no remap) */
+#define SPI1_REMAP0		STM32_REMAP(0U, 0x1U, 0U, STM32_AFIO_MAPR)
+/** SPI1 (remap) */
+#define SPI1_REMAP1		STM32_REMAP(1U, 0x1U, 0U, STM32_AFIO_MAPR)
+
+/** I2C1 (no remap) */
+#define I2C1_REMAP0		STM32_REMAP(0U, 0x1U, 1U, STM32_AFIO_MAPR)
+/** I2C1 (remap) */
+#define I2C1_REMAP1		STM32_REMAP(1U, 0x1U, 1U, STM32_AFIO_MAPR)
+
+/** USART1 (no remap) */
+#define USART1_REMAP0		STM32_REMAP(0U, 0x1U, 2U, STM32_AFIO_MAPR)
+/** USART1 (remap) */
+#define USART1_REMAP1		STM32_REMAP(1U, 0x1U, 2U, STM32_AFIO_MAPR)
+
+/** USART2 (no remap) */
+#define USART2_REMAP0		STM32_REMAP(0U, 0x1U, 3U, STM32_AFIO_MAPR)
+/** USART2 (remap) */
+#define USART2_REMAP1		STM32_REMAP(1U, 0x1U, 3U, STM32_AFIO_MAPR)
+
+/** USART3 (no remap) */
+#define USART3_REMAP0		STM32_REMAP(0U, 0x3U, 4U, STM32_AFIO_MAPR)
+/** USART3 (partial remap) */
+#define USART3_REMAP1		STM32_REMAP(1U, 0x3U, 4U, STM32_AFIO_MAPR)
+/** USART3 (full remap) */
+#define USART3_REMAP2		STM32_REMAP(3U, 0x3U, 4U, STM32_AFIO_MAPR)
+
+/** TIM1 (no remap) */
+#define TIM1_REMAP0		STM32_REMAP(0U, 0x3U, 6U, STM32_AFIO_MAPR)
+/** TIM1 (partial remap) */
+#define TIM1_REMAP1		STM32_REMAP(1U, 0x3U, 6U, STM32_AFIO_MAPR)
+/** TIM1 (full remap) */
+#define TIM1_REMAP2		STM32_REMAP(3U, 0x3U, 6U, STM32_AFIO_MAPR)
+
+/** TIM2 (no remap) */
+#define TIM2_REMAP0		STM32_REMAP(0U, 0x3U, 8U, STM32_AFIO_MAPR)
+/** TIM2 (partial remap 1) */
+#define TIM2_REMAP1		STM32_REMAP(1U, 0x3U, 8U, STM32_AFIO_MAPR)
+/** TIM2 (partial remap 2) */
+#define TIM2_REMAP2		STM32_REMAP(2U, 0x3U, 8U, STM32_AFIO_MAPR)
+/** TIM2 (full remap) */
+#define TIM2_REMAP3		STM32_REMAP(3U, 0x3U, 8U, STM32_AFIO_MAPR)
+
+/** TIM3 (no remap) */
+#define TIM3_REMAP0		STM32_REMAP(0U, 0x3U, 10U, STM32_AFIO_MAPR)
+/** TIM3 (partial remap 1) */
+#define TIM3_REMAP1		STM32_REMAP(1U, 0x3U, 10U, STM32_AFIO_MAPR)
+/** TIM3 (partial remap 2) */
+#define TIM3_REMAP2		STM32_REMAP(2U, 0x3U, 10U, STM32_AFIO_MAPR)
+/** TIM3 (full remap) */
+#define TIM3_REMAP3		STM32_REMAP(3U, 0x3U, 10U, STM32_AFIO_MAPR)
+
+/** TIM4 (no remap) */
+#define TIM4_REMAP0		STM32_REMAP(0U, 0x1U, 12U, STM32_AFIO_MAPR)
+/** TIM4 (remap) */
+#define TIM4_REMAP1		STM32_REMAP(1U, 0x1U, 12U, STM32_AFIO_MAPR)
+
+/** CAN (no remap) */
+#define CAN_REMAP0		STM32_REMAP(0U, 0x3U, 13U, STM32_AFIO_MAPR)
+/** CAN (partial remap) */
+#define CAN_REMAP1		STM32_REMAP(2U, 0x3U, 13U, STM32_AFIO_MAPR)
+/** CAN (full remap) */
+#define CAN_REMAP2		STM32_REMAP(3U, 0x3U, 13U, STM32_AFIO_MAPR)
+
+/** CAN1 alias */
+#define CAN1_REMAP0		CAN_REMAP0
+#define CAN1_REMAP1		CAN_REMAP1
+#define CAN1_REMAP2		CAN_REMAP2
+
+/** ETH (no remap) */
+#define ETH_REMAP0		STM32_REMAP(0U, 0x1U, 20U, STM32_AFIO_MAPR)
+/** ETH (remap) */
+#define ETH_REMAP1		STM32_REMAP(1U, 0x1U, 20U, STM32_AFIO_MAPR)
+
+/** CAN2 (no remap) */
+#define CAN2_REMAP0		STM32_REMAP(0U, 0x1U, 21U, STM32_AFIO_MAPR)
+/** CAN2 (remap) */
+#define CAN2_REMAP1		STM32_REMAP(1U, 0x1U, 21U, STM32_AFIO_MAPR)
+
+/** SPI3 (no remap) */
+#define SPI3_REMAP0		STM32_REMAP(0U, 0x1U, 27U, STM32_AFIO_MAPR)
+/** SPI3 (remap) */
+#define SPI3_REMAP1		STM32_REMAP(1U, 0x1U, 27U, STM32_AFIO_MAPR)
+
+/** I2S3 (SPI3) (no remap) */
+#define I2S3_REMAP0		SPI3_REMAP0
+/** I2S3 (SPI3) (remap) */
+#define I2S3_REMAP1		SPI3_REMAP1
+
+/** TIM9 (no remap) */
+#define TIM9_REMAP0		STM32_REMAP(0U, 0x1U, 5U, STM32_AFIO_MAPR2)
+/** TIM9 (remap) */
+#define TIM9_REMAP1		STM32_REMAP(1U, 0x1U, 5U, STM32_AFIO_MAPR2)
+
+/** TIM10 (no remap) */
+#define TIM10_REMAP0		STM32_REMAP(0U, 0x1U, 6U, STM32_AFIO_MAPR2)
+/** TIM10 (remap) */
+#define TIM10_REMAP1		STM32_REMAP(1U, 0x1U, 6U, STM32_AFIO_MAPR2)
+
+/** TIM11 (no remap) */
+#define TIM11_REMAP0		STM32_REMAP(0U, 0x1U, 7U, STM32_AFIO_MAPR2)
+/** TIM11 (remap) */
+#define TIM11_REMAP1		STM32_REMAP(1U, 0x1U, 7U, STM32_AFIO_MAPR2)
+
+/** TIM13 (no remap) */
+#define TIM13_REMAP0		STM32_REMAP(0U, 0x1U, 8U, STM32_AFIO_MAPR2)
+/** TIM13 (remap) */
+#define TIM13_REMAP1		STM32_REMAP(1U, 0x1U, 8U, STM32_AFIO_MAPR2)
+
+/** TIM14 (no remap) */
+#define TIM14_REMAP0		STM32_REMAP(0U, 0x1U, 9U, STM32_AFIO_MAPR2)
+/** TIM14 (remap) */
+#define TIM14_REMAP1		STM32_REMAP(1U, 0x1U, 9U, STM32_AFIO_MAPR2)
+
+/** TIM15 (no remap) */
+#define TIM15_REMAP0		STM32_REMAP(0U, 0x1U, 0U, STM32_AFIO_MAPR2)
+/** TIM15 (remap) */
+#define TIM15_REMAP1		STM32_REMAP(1U, 0x1U, 0U, STM32_AFIO_MAPR2)
+
+/** TIM16 (no remap) */
+#define TIM16_REMAP0		STM32_REMAP(0U, 0x1U, 1U, STM32_AFIO_MAPR2)
+/** TIM16 (remap) */
+#define TIM16_REMAP1		STM32_REMAP(1U, 0x1U, 1U, STM32_AFIO_MAPR2)
+
+/** TIM17 (no remap) */
+#define TIM17_REMAP0		STM32_REMAP(0U, 0x1U, 2U, STM32_AFIO_MAPR2)
+/** TIM17 (remap) */
+#define TIM17_REMAP1		STM32_REMAP(1U, 0x1U, 2U, STM32_AFIO_MAPR2)
+
+#endif	/* ZEPHYR_STM32_AFIO_H_ */
diff --git a/include/dt-bindings/pinctrl/stm32f1-pinctrl.h b/include/dt-bindings/pinctrl/stm32f1-pinctrl.h
index d68d9b85df6..1ba6484906b 100644
--- a/include/dt-bindings/pinctrl/stm32f1-pinctrl.h
+++ b/include/dt-bindings/pinctrl/stm32f1-pinctrl.h
@@ -8,6 +8,7 @@
 #define ZEPHYR_STM32_PINCTRLF1_H_
 
 #include <dt-bindings/pinctrl/stm32-pinctrl-common.h>
+#include <dt-bindings/pinctrl/stm32f1-afio.h>
 
 /* Adapted from Linux: include/dt-bindings/pinctrl/stm32-pinfunc.h */
 
@@ -24,7 +25,7 @@
  * - mode  [ 0 : 1 ]
  * - line  [ 2 : 5 ]
  * - port  [ 6 : 9 ]
- * - remap [ 10 : 12 ]
+ * - remap [ 10 : 19 ]
  *
  * @param port Port ('A'..'K')
  * @param line Pin (0..15)
@@ -39,7 +40,7 @@
 #define STM32_PORT_SHIFT  6U
 #define STM32_PORT_MASK   0xFU
 #define STM32_REMAP_SHIFT 10U
-#define STM32_REMAP_MASK  0x1FU
+#define STM32_REMAP_MASK  0x3FFU
 
 #define STM32F1_PINMUX(port, line, mode, remap)				       \
 		(((((port) - 'A') & STM32_PORT_MASK) << STM32_PORT_SHIFT) |    \
@@ -55,16 +56,6 @@
 #define GPIO_IN		0x1  /* Input */
 #define ANALOG		0x2  /* Analog */
 
-/**
- * @brief Pin remapping configurations
- */
-
-#define NO_REMAP	0x0  /* No remapping */
-#define REMAP_1		0x1  /* Partial remapping 1 */
-#define REMAP_2		0x2  /* Partial remapping 2 */
-#define REMAP_3		0x3  /* Partial remapping 3 */
-#define REMAP_FULL	0x4  /* Full remapping */
-
 /**
  * @brief PIN configuration bitfield
  *