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intel_adsp: cleanup ace_v1x-regs.h more and prep for removal

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File still not being removed due to out-of-tree usage. We will drop it
once the external code has stopped referencing it.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
This commit is contained in:
Anas Nashif 2022-10-02 14:46:51 -04:00
commit 0869e62539
10 changed files with 71 additions and 71 deletions
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1
drivers/counter/counter_ace_v1x_art.c
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@ -8,7 +8,6 @@
#include <zephyr/devicetree.h>
#include <zephyr/drivers/counter.h>
#include <soc.h>
#include <ace_v1x-regs.h>
#include <counter/counter_ace_v1x_art_regs.h>
static struct k_spinlock lock;

1
drivers/counter/counter_ace_v1x_rtc.c
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@ -8,7 +8,6 @@
#include <zephyr/devicetree.h>
#include <zephyr/drivers/counter.h>
#include <soc.h>
#include <ace_v1x-regs.h>
#include <counter/counter_ace_v1x_rtc_regs.h>
static int counter_ace_v1x_rtc_get_value(const struct device *dev,

1
drivers/mm/mm_drv_intel_adsp_mtl_tlb.c
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@ -34,7 +34,6 @@
#include <soc.h>
#include <adsp_memory.h>
#include <ace_v1x-regs.h>
#include "mm_drv_common.h"

4
drivers/timer/intel_adsp_timer.c
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@ -15,10 +15,6 @@
#define DT_DRV_COMPAT intel_adsp_timer
#ifdef CONFIG_SOC_SERIES_INTEL_ACE
#include <ace_v1x-regs.h>
#endif
/**
* @file
* @brief Intel Audio DSP Wall Clock Timer driver

65
soc/xtensa/intel_adsp/ace/include/intel_ace15_mtpm/ace_v1x-regs.h
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@ -6,66 +6,11 @@
#include <stdint.h>
#include <xtensa/config/core-isa.h>
#include <adsp_power.h>
#include <adsp_boot.h>
#include <adsp_memory.h>
#include <adsp_interrupt.h>
/* L2 Local Memory Management */
/* These registers are for the L2 memory control and status. */
#define DFL2MM_REG 0x71d00
struct mtl_l2mm {
uint32_t l2mcap;
uint32_t l2mpat;
uint32_t l2mecap;
uint32_t l2mecs;
uint32_t l2hsbpmptr;
uint32_t l2usbpmptr;
uint32_t l2usbmrpptr;
uint32_t l2ucmrpptr;
uint32_t l2ucmrpdptr;
};
#define MTL_L2MM ((volatile struct mtl_l2mm *)DFL2MM_REG)
/* DfL2MCAP */
struct mtl_l2mcap {
uint32_t l2hss : 8;
uint32_t l2uss : 4;
uint32_t l2hsbs : 4;
uint32_t l2hs2s : 8;
uint32_t l2usbs : 5;
uint32_t l2se : 1;
uint32_t el2se : 1;
uint32_t rsvd32 : 1;
};
#define MTL_L2MCAP ((volatile struct mtl_l2mcap *)DFL2MM_REG)
static inline uint32_t mtl_hpsram_get_bank_count(void)
{
return MTL_L2MCAP->l2hss;
}
static inline uint32_t mtl_lpsram_get_bank_count(void)
{
return MTL_L2MCAP->l2uss;
}
struct mtl_hpsram_regs {
/** @brief power gating control */
uint8_t HSxPGCTL;
/** @brief retention mode control */
uint8_t HSxRMCTL;
uint8_t reserved[2];
/** @brief power gating status */
uint8_t HSxPGISTS;
uint8_t reserved1[3];
};
/* These registers are for the L2 HP SRAM bank power management control and status.*/
#define L2HSBPM_REG 0x17A800
#define L2HSBPM_REG_SIZE 0x0008
#define HPSRAM_REGS(block_idx) ((volatile struct mtl_hpsram_regs *const) \
(L2HSBPM_REG + L2HSBPM_REG_SIZE * (block_idx)))
/* FIXME: This file is to be removed after all users have been adapted */
#endif /* ZEPHYR_SOC_INTEL_ADSP_ACE_v1x_REGS_H_ */

63
soc/xtensa/intel_adsp/ace/include/intel_ace15_mtpm/adsp_memory.h
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@ -57,4 +57,67 @@
/* The number of set associative cache way supported on L1 Instruction Cache */
#define ADSP_CxL1CCAP_ICMWC ((ADSP_CxL1CCAP_REG >> 20) & 7)
#ifndef _LINKER
/* L2 Local Memory Management */
/* These registers are for the L2 memory control and status. */
#define DFL2MM_REG 0x71d00
struct mtl_l2mm {
uint32_t l2mcap;
uint32_t l2mpat;
uint32_t l2mecap;
uint32_t l2mecs;
uint32_t l2hsbpmptr;
uint32_t l2usbpmptr;
uint32_t l2usbmrpptr;
uint32_t l2ucmrpptr;
uint32_t l2ucmrpdptr;
};
#define MTL_L2MM ((volatile struct mtl_l2mm *)DFL2MM_REG)
/* DfL2MCAP */
struct mtl_l2mcap {
uint32_t l2hss : 8;
uint32_t l2uss : 4;
uint32_t l2hsbs : 4;
uint32_t l2hs2s : 8;
uint32_t l2usbs : 5;
uint32_t l2se : 1;
uint32_t el2se : 1;
uint32_t rsvd32 : 1;
};
#define MTL_L2MCAP ((volatile struct mtl_l2mcap *)DFL2MM_REG)
static inline uint32_t mtl_hpsram_get_bank_count(void)
{
return MTL_L2MCAP->l2hss;
}
static inline uint32_t mtl_lpsram_get_bank_count(void)
{
return MTL_L2MCAP->l2uss;
}
struct mtl_hpsram_regs {
/** @brief power gating control */
uint8_t HSxPGCTL;
/** @brief retention mode control */
uint8_t HSxRMCTL;
uint8_t reserved[2];
/** @brief power gating status */
uint8_t HSxPGISTS;
uint8_t reserved1[3];
};
#endif
/* These registers are for the L2 HP SRAM bank power management control and status.*/
#define L2HSBPM_REG 0x17A800
#define L2HSBPM_REG_SIZE 0x0008
#define HPSRAM_REGS(block_idx) ((volatile struct mtl_hpsram_regs *const) \
(L2HSBPM_REG + L2HSBPM_REG_SIZE * (block_idx)))
#endif /* ZEPHYR_SOC_INTEL_ADSP_MEMORY_H_ */

1
soc/xtensa/intel_adsp/ace/power.c
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@ -9,6 +9,7 @@
#include <xtensa/corebits.h>
#include <adsp_boot.h>
#include <adsp_power.h>
#define LPSRAM_MAGIC_VALUE 0x13579BDF
#define LPSCTL_BATTR_MASK GENMASK(16, 12)

2
soc/xtensa/intel_adsp/ace/sram.c
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@ -12,8 +12,6 @@
#include <adsp_memory.h>
#include <cpu_init.h>
#include "manifest.h"
#include <ace_v1x-regs.h>
#define DELAY_COUNT 256

2
soc/xtensa/intel_adsp/common/include/soc.h
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@ -11,6 +11,8 @@
#include <zephyr/arch/xtensa/cache.h>
#include <zephyr/linker/sections.h>
#include <adsp_interrupt.h>
#define SSP_MN_DIV_SIZE (8)
#define SSP_MN_DIV_BASE(x) \

2
soc/xtensa/intel_adsp/common/ipc.c
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@ -157,8 +157,6 @@ bool intel_adsp_ipc_send_message_sync(const struct device *dev,
#if DT_NODE_EXISTS(INTEL_ADSP_IPC_HOST_DTNODE)
#if defined(CONFIG_SOC_SERIES_INTEL_ACE)
#include <ace_v1x-regs.h>
static inline void ace_ipc_intc_unmask(void)
{
for (int i = 0; i < CONFIG_MP_NUM_CPUS; i++) {