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drivers/mm: Get some bit configurations from DTS instead of SoC version

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Migrate information to DTS and get it from there on the code. Note that
for CAVS 15, the information is not migrated as there's no DTS entry for
it. It can be brought back (in the DTS) if TLB support is enabled for
it.

Signed-off-by: Ederson de Souza <ederson.desouza@intel.com>
This commit is contained in:
Ederson de Souza 2022-07-28 14:40:39 -07:00 • committed by Anas Nashif
commit 03a947850d
6 changed files with 23 additions and 9 deletions
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7
drivers/mm/mm_drv_intel_adsp_mtl_tlb.c
View file

@ -46,11 +46,12 @@ DEVICE_MMIO_TOPLEVEL_STATIC(tlb_regs, DT_DRV_INST(0));
* Number of significant bits in the page index (defines the size of
* the table)
*/
#define TLB_PADDR_SIZE DT_INST_PROP(0, paddr_size)
#define TLB_EXEC_BIT BIT(DT_INST_PROP(0, exec_bit_idx))
#define TLB_WRITE_BIT BIT(DT_INST_PROP(0, write_bit_idx))
#if defined(CONFIG_SOC_SERIES_INTEL_ACE1X)
# include <ace_v1x-regs.h>
# define TLB_PADDR_SIZE 12
# define TLB_EXEC_BIT BIT(14)
# define TLB_WRITE_BIT BIT(15)
#endif
#define TLB_ENTRY_NUM (1 << TLB_PADDR_SIZE)

7
drivers/mm/mm_drv_intel_adsp_tlb.c
View file

@ -45,12 +45,7 @@ DEVICE_MMIO_TOPLEVEL_STATIC(tlb_regs, DT_DRV_INST(0));
* Number of significant bits in the page index (defines the size of
* the table)
*/
#if defined(CONFIG_SOC_INTEL_CAVS_V15)
# define TLB_PADDR_SIZE 9
#else
# define TLB_PADDR_SIZE 11
#endif
#define TLB_PADDR_SIZE DT_INST_PROP(0, paddr_size)
#define TLB_PADDR_MASK ((1 << TLB_PADDR_SIZE) - 1)
#define TLB_ENABLE_BIT BIT(TLB_PADDR_SIZE)