From 03a947850d06075d939cdb2136ee6d7439bfd930 Mon Sep 17 00:00:00 2001 From: Ederson de Souza Date: Thu, 28 Jul 2022 14:40:39 -0700 Subject: [PATCH] drivers/mm: Get some bit configurations from DTS instead of SoC version Migrate information to DTS and get it from there on the code. Note that for CAVS 15, the information is not migrated as there's no DTS entry for it. It can be brought back (in the DTS) if TLB support is enabled for it. Signed-off-by: Ederson de Souza --- drivers/mm/mm_drv_intel_adsp_mtl_tlb.c | 7 ++++--- drivers/mm/mm_drv_intel_adsp_tlb.c | 7 +------ dts/bindings/mm/intel,adsp-tlb.yaml | 13 +++++++++++++ dts/xtensa/intel/intel_adsp_ace15_mtpm.dtsi | 3 +++ dts/xtensa/intel/intel_cavs25.dtsi | 1 + dts/xtensa/intel/intel_cavs25_tgph.dtsi | 1 + 6 files changed, 23 insertions(+), 9 deletions(-) diff --git a/drivers/mm/mm_drv_intel_adsp_mtl_tlb.c b/drivers/mm/mm_drv_intel_adsp_mtl_tlb.c index 3b24cecd48a..c9b8bb570d6 100644 --- a/drivers/mm/mm_drv_intel_adsp_mtl_tlb.c +++ b/drivers/mm/mm_drv_intel_adsp_mtl_tlb.c @@ -46,11 +46,12 @@ DEVICE_MMIO_TOPLEVEL_STATIC(tlb_regs, DT_DRV_INST(0)); * Number of significant bits in the page index (defines the size of * the table) */ +#define TLB_PADDR_SIZE DT_INST_PROP(0, paddr_size) +#define TLB_EXEC_BIT BIT(DT_INST_PROP(0, exec_bit_idx)) +#define TLB_WRITE_BIT BIT(DT_INST_PROP(0, write_bit_idx)) + #if defined(CONFIG_SOC_SERIES_INTEL_ACE1X) # include -# define TLB_PADDR_SIZE 12 -# define TLB_EXEC_BIT BIT(14) -# define TLB_WRITE_BIT BIT(15) #endif #define TLB_ENTRY_NUM (1 << TLB_PADDR_SIZE) diff --git a/drivers/mm/mm_drv_intel_adsp_tlb.c b/drivers/mm/mm_drv_intel_adsp_tlb.c index 51adc829b57..01cec6d8c3f 100644 --- a/drivers/mm/mm_drv_intel_adsp_tlb.c +++ b/drivers/mm/mm_drv_intel_adsp_tlb.c @@ -45,12 +45,7 @@ DEVICE_MMIO_TOPLEVEL_STATIC(tlb_regs, DT_DRV_INST(0)); * Number of significant bits in the page index (defines the size of * the table) */ -#if defined(CONFIG_SOC_INTEL_CAVS_V15) -# define TLB_PADDR_SIZE 9 -#else -# define TLB_PADDR_SIZE 11 -#endif - +#define TLB_PADDR_SIZE DT_INST_PROP(0, paddr_size) #define TLB_PADDR_MASK ((1 << TLB_PADDR_SIZE) - 1) #define TLB_ENABLE_BIT BIT(TLB_PADDR_SIZE) diff --git a/dts/bindings/mm/intel,adsp-tlb.yaml b/dts/bindings/mm/intel,adsp-tlb.yaml index 9a2bd4bdda5..56e473c6c82 100644 --- a/dts/bindings/mm/intel,adsp-tlb.yaml +++ b/dts/bindings/mm/intel,adsp-tlb.yaml @@ -11,3 +11,16 @@ include: mm_drv.yaml properties: reg: required: true + + paddr-size: + type: int + description: Number of significant bits in the page index. + required: true + + exec-bit-idx: + type: int + description: Index of the execute permission bit. + + write-bit-idx: + type: int + description: Index of the write permission bit. diff --git a/dts/xtensa/intel/intel_adsp_ace15_mtpm.dtsi b/dts/xtensa/intel/intel_adsp_ace15_mtpm.dtsi index 97592a743d8..a1a46d9010f 100644 --- a/dts/xtensa/intel/intel_adsp_ace15_mtpm.dtsi +++ b/dts/xtensa/intel/intel_adsp_ace15_mtpm.dtsi @@ -165,6 +165,9 @@ tlb: tlb@17e000 { compatible = "intel,adsp-mtl-tlb"; reg = <0x17e000 0x1000>; + paddr-size = <12>; + exec-bit-idx = <14>; + write-bit-idx= <15>; }; lpgpdma0: dma@7c000 { diff --git a/dts/xtensa/intel/intel_cavs25.dtsi b/dts/xtensa/intel/intel_cavs25.dtsi index 55d94b16788..4e33d76028c 100644 --- a/dts/xtensa/intel/intel_cavs25.dtsi +++ b/dts/xtensa/intel/intel_cavs25.dtsi @@ -160,6 +160,7 @@ tlb: tlb@3000 { compatible = "intel,adsp-tlb"; reg = <0x3000 0x1000>; + paddr-size = <11>; }; ssp0: ssp@77000 { diff --git a/dts/xtensa/intel/intel_cavs25_tgph.dtsi b/dts/xtensa/intel/intel_cavs25_tgph.dtsi index 1d5d13cf67c..50d8a52525f 100644 --- a/dts/xtensa/intel/intel_cavs25_tgph.dtsi +++ b/dts/xtensa/intel/intel_cavs25_tgph.dtsi @@ -106,6 +106,7 @@ tlb: tlb@3000 { compatible = "intel,adsp-tlb"; reg = <0x3000 0x1000>; + paddr-size = <11>; }; }; };