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ext: mcux: Update to MCUXpresso SDK 2.5.0

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Updates the MCUXpresso SDK to version 2.5.0 for applicable SoCs.
Wireless (KW*) and legacy (KL25) SoCs were not included in this
MCUXpresso SDK release and are therefore not updated here.

New in this release is SoC-level and board-level support for external
xip flash in the i.MX RT family.

For RT1050, we are now using the MCUXpresso SDK for the EVKB version of
the board, which correponds to an upgrade from A0 to A1 silicon.
However, we don't yet have Kconfigs in place to support A1 silicon part
numbers, and therefore add a simple cmake hack to convert A0 part
numbers to A1 part numbers.

The SDK flash driver interface also changed slightly in this release,
and thus the zephyr flash shim driver is updated accordingly.

Origin: MCUXpresso SDK
License: BSD 3-Clause
URL: mcux.nxp.com
Purpose: Provide device header files and bare metal peripheral drivers
for Kinetis, LPC, and i.MX SoCs.
Maintained-by: External

Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
This commit is contained in:
Maureen Helm 2018-12-19 15:22:00 -06:00 • committed by Anas Nashif
commit 011a88c744
302 changed files with 140274 additions and 23636 deletions
Download patch file Download diff file Expand all files Collapse all files

14
drivers/flash/soc_flash_mcux.c
View file

@ -22,6 +22,7 @@ struct flash_priv {
* HACK: flash write protection is managed in software.
*/
struct k_sem write_lock;
u32_t pflash_block_base;
};
/*
@ -44,7 +45,7 @@ static int flash_mcux_erase(struct device *dev, off_t offset, size_t len)
return -EACCES;
}
addr = offset + priv->config.PFlashBlockBase;
addr = offset + priv->pflash_block_base;
key = irq_lock();
rc = FLASH_Erase(&priv->config, addr, len, kFLASH_ApiEraseKey);
@ -66,7 +67,7 @@ static int flash_mcux_read(struct device *dev, off_t offset,
* hidden below the API: until the API export these ranges, we can not
* do any generic validation
*/
addr = offset + priv->config.PFlashBlockBase;
addr = offset + priv->pflash_block_base;
memcpy(data, (void *) addr, len);
@ -85,10 +86,10 @@ static int flash_mcux_write(struct device *dev, off_t offset,
return -EACCES;
}
addr = offset + priv->config.PFlashBlockBase;
addr = offset + priv->pflash_block_base;
key = irq_lock();
rc = FLASH_Program(&priv->config, addr, (uint32_t *) data, len);
rc = FLASH_Program(&priv->config, addr, (uint8_t *) data, len);
irq_unlock(key);
k_sem_give(&priv->write_lock);
@ -141,12 +142,17 @@ static const struct flash_driver_api flash_mcux_api = {
static int flash_mcux_init(struct device *dev)
{
struct flash_priv *priv = dev->driver_data;
uint32_t pflash_block_base;
status_t rc;
k_sem_init(&priv->write_lock, 0, 1);
rc = FLASH_Init(&priv->config);
FLASH_GetProperty(&priv->config, kFLASH_PropertyPflash0BlockBaseAddr,
&pflash_block_base);
priv->pflash_block_base = (u32_t) pflash_block_base;
return (rc == kStatus_Success) ? 0 : -EIO;
}

2
ext/hal/nxp/mcux/CMakeLists.txt
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@ -7,6 +7,8 @@ if("${MCUX_DEVICE}" STREQUAL "LPC54114")
elseif("${MCUX_DEVICE}" STREQUAL "LPC54114_M0")
set(MCUX_CPU CPU_${CONFIG_SOC_PART_NUMBER}_cm0plus)
set(MCUX_DEVICE LPC54114)
elseif("${MCUX_DEVICE}" STREQUAL "MIMXRT1052")
string(REGEX REPLACE "(.*)A$" "CPU_\\1B" MCUX_CPU ${CONFIG_SOC_PART_NUMBER})
else()
set(MCUX_CPU CPU_${CONFIG_SOC_PART_NUMBER})
endif()

12
ext/hal/nxp/mcux/README
View file

@ -15,12 +15,12 @@ Status:
SoC Version (Release Date) Tag
----------------------------------------------------------------------------
LPC54114 KSDK 2.2.1
MIMXRT1051 KSDK 2.3.0
MIMXRT1052 KSDK 2.3.0
MIMXRT1061 KSDK 2.4.0 (2018-09-04) REL_SDK_2.4.0_RT1060_RFP
MIMXRT1062 KSDK 2.4.0 (2018-09-04) REL_SDK_2.4.0_RT1060_RFP
MK64F12 KSDK 2.2.0
LPC54114 SDK 2.5.0 (2018-12-17) REL_2.5.0_REL9_RFP_RC3_7_1
MIMXRT1051 SDK 2.5.0 (2018-12-17) REL_2.5.0_REL9_RFP_RC3_7_1
MIMXRT1052 SDK 2.5.0 (2018-12-17) REL_2.5.0_REL9_RFP_RC3_7_1
MIMXRT1061 SDK 2.5.0 (2018-12-17) REL_2.5.0_REL9_RFP_RC3_7_1
MIMXRT1062 SDK 2.5.0 (2018-12-17) REL_2.5.0_REL9_RFP_RC3_7_1
MK64F12 SDK 2.5.0 (2018-12-17) REL_2.5.0_REL9_RFP_RC3_7_1
MKL25Z4 KSDK 2.2.0 (2017-06-29) REL6.GA.RC4.6_ISSDK1.6GAFIX.GEN
MKW21Z4 KSDK 2.2.0 (2018-01-19) release_conn_ksdk_2.2_kw41z_1.0.4_stage_final
MKW22D5 KSDK 2.2.0 (2017-03-21) REL_SDK_REL6_2.0.0_GA_RC4_6

55
ext/hal/nxp/mcux/boards/evkbimxrt1050/evkbimxrt1050_flexspi_nor_config.c Normal file
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@ -0,0 +1,55 @@
/*
* Copyright 2017 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include "evkbimxrt1050_flexspi_nor_config.h"
/* Component ID definition, used by tools. */
#ifndef FSL_COMPONENT_ID
#define FSL_COMPONENT_ID "platform.drivers.xip_board"
#endif
/*******************************************************************************
* Code
******************************************************************************/
#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1)
#if defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__)
__attribute__((section(".boot_hdr.conf")))
#elif defined(__ICCARM__)
#pragma location = ".boot_hdr.conf"
#endif
const flexspi_nor_config_t hyperflash_config = {
.memConfig =
{
.tag = FLEXSPI_CFG_BLK_TAG,
.version = FLEXSPI_CFG_BLK_VERSION,
.readSampleClkSrc = kFlexSPIReadSampleClk_ExternalInputFromDqsPad,
.csHoldTime = 3u,
.csSetupTime = 3u,
.columnAddressWidth = 3u,
// Enable DDR mode, Wordaddassable, Safe configuration, Differential clock
.controllerMiscOption =
(1u << kFlexSpiMiscOffset_DdrModeEnable) | (1u << kFlexSpiMiscOffset_WordAddressableEnable) |
(1u << kFlexSpiMiscOffset_SafeConfigFreqEnable) | (1u << kFlexSpiMiscOffset_DiffClkEnable),
.sflashPadType = kSerialFlash_8Pads,
.serialClkFreq = kFlexSpiSerialClk_133MHz,
.sflashA1Size = 64u * 1024u * 1024u,
.dataValidTime = {16u, 16u},
.lookupTable =
{
// Read LUTs
FLEXSPI_LUT_SEQ(CMD_DDR, FLEXSPI_8PAD, 0xA0, RADDR_DDR, FLEXSPI_8PAD, 0x18),
FLEXSPI_LUT_SEQ(CADDR_DDR, FLEXSPI_8PAD, 0x10, DUMMY_DDR, FLEXSPI_8PAD, 0x06),
FLEXSPI_LUT_SEQ(READ_DDR, FLEXSPI_8PAD, 0x04, STOP, FLEXSPI_1PAD, 0x0),
},
},
.pageSize = 512u,
.sectorSize = 256u * 1024u,
.blockSize = 256u * 1024u,
.isUniformBlockSize = true,
};
#endif /* XIP_BOOT_HEADER_ENABLE */

269
ext/hal/nxp/mcux/boards/evkbimxrt1050/evkbimxrt1050_flexspi_nor_config.h Normal file
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@ -0,0 +1,269 @@
/*
* Copyright (c) 2016, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef __EVKBIMXRT1050_FLEXSPI_NOR_CONFIG__
#define __EVKBIMXRT1050_FLEXSPI_NOR_CONFIG__
#include <stdint.h>
#include <stdbool.h>
#include "fsl_common.h"
/*! @name Driver version */
/*@{*/
/*! @brief XIP_BOARD driver version 2.0.0. */
#define FSL_XIP_BOARD_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
/*@}*/
/* FLEXSPI memory config block related defintions */
#define FLEXSPI_CFG_BLK_TAG (0x42464346UL) // ascii "FCFB" Big Endian
#define FLEXSPI_CFG_BLK_VERSION (0x56010400UL) // V1.4.0
#define FLEXSPI_CFG_BLK_SIZE (512)
/* FLEXSPI Feature related definitions */
#define FLEXSPI_FEATURE_HAS_PARALLEL_MODE 1
/* Lookup table related defintions */
#define CMD_INDEX_READ 0
#define CMD_INDEX_READSTATUS 1
#define CMD_INDEX_WRITEENABLE 2
#define CMD_INDEX_WRITE 4
#define CMD_LUT_SEQ_IDX_READ 0
#define CMD_LUT_SEQ_IDX_READSTATUS 1
#define CMD_LUT_SEQ_IDX_WRITEENABLE 3
#define CMD_LUT_SEQ_IDX_WRITE 9
#define CMD_SDR 0x01
#define CMD_DDR 0x21
#define RADDR_SDR 0x02
#define RADDR_DDR 0x22
#define CADDR_SDR 0x03
#define CADDR_DDR 0x23
#define MODE1_SDR 0x04
#define MODE1_DDR 0x24
#define MODE2_SDR 0x05
#define MODE2_DDR 0x25
#define MODE4_SDR 0x06
#define MODE4_DDR 0x26
#define MODE8_SDR 0x07
#define MODE8_DDR 0x27
#define WRITE_SDR 0x08
#define WRITE_DDR 0x28
#define READ_SDR 0x09
#define READ_DDR 0x29
#define LEARN_SDR 0x0A
#define LEARN_DDR 0x2A
#define DATSZ_SDR 0x0B
#define DATSZ_DDR 0x2B
#define DUMMY_SDR 0x0C
#define DUMMY_DDR 0x2C
#define DUMMY_RWDS_SDR 0x0D
#define DUMMY_RWDS_DDR 0x2D
#define JMP_ON_CS 0x1F
#define STOP 0
#define FLEXSPI_1PAD 0
#define FLEXSPI_2PAD 1
#define FLEXSPI_4PAD 2
#define FLEXSPI_8PAD 3
#define FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) \
(FLEXSPI_LUT_OPERAND0(op0) | FLEXSPI_LUT_NUM_PADS0(pad0) | FLEXSPI_LUT_OPCODE0(cmd0) | FLEXSPI_LUT_OPERAND1(op1) | \
FLEXSPI_LUT_NUM_PADS1(pad1) | FLEXSPI_LUT_OPCODE1(cmd1))
//!@brief Definitions for FlexSPI Serial Clock Frequency
typedef enum _FlexSpiSerialClockFreq
{
kFlexSpiSerialClk_30MHz = 1,
kFlexSpiSerialClk_50MHz = 2,
kFlexSpiSerialClk_60MHz = 3,
kFlexSpiSerialClk_75MHz = 4,
kFlexSpiSerialClk_80MHz = 5,
kFlexSpiSerialClk_100MHz = 6,
kFlexSpiSerialClk_133MHz = 7,
kFlexSpiSerialClk_166MHz = 8,
kFlexSpiSerialClk_200MHz = 9,
} flexspi_serial_clk_freq_t;
//!@brief FlexSPI clock configuration type
enum
{
kFlexSpiClk_SDR, //!< Clock configure for SDR mode
kFlexSpiClk_DDR, //!< Clock configurat for DDR mode
};
//!@brief FlexSPI Read Sample Clock Source definition
typedef enum _FlashReadSampleClkSource
{
kFlexSPIReadSampleClk_LoopbackInternally = 0,
kFlexSPIReadSampleClk_LoopbackFromDqsPad = 1,
kFlexSPIReadSampleClk_LoopbackFromSckPad = 2,
kFlexSPIReadSampleClk_ExternalInputFromDqsPad = 3,
} flexspi_read_sample_clk_t;
//!@brief Misc feature bit definitions
enum
{
kFlexSpiMiscOffset_DiffClkEnable = 0, //!< Bit for Differential clock enable
kFlexSpiMiscOffset_Ck2Enable = 1, //!< Bit for CK2 enable
kFlexSpiMiscOffset_ParallelEnable = 2, //!< Bit for Parallel mode enable
kFlexSpiMiscOffset_WordAddressableEnable = 3, //!< Bit for Word Addressable enable
kFlexSpiMiscOffset_SafeConfigFreqEnable = 4, //!< Bit for Safe Configuration Frequency enable
kFlexSpiMiscOffset_PadSettingOverrideEnable = 5, //!< Bit for Pad setting override enable
kFlexSpiMiscOffset_DdrModeEnable = 6, //!< Bit for DDR clock confiuration indication.
};
//!@brief Flash Type Definition
enum
{
kFlexSpiDeviceType_SerialNOR = 1, //!< Flash devices are Serial NOR
kFlexSpiDeviceType_SerialNAND = 2, //!< Flash devices are Serial NAND
kFlexSpiDeviceType_SerialRAM = 3, //!< Flash devices are Serial RAM/HyperFLASH
kFlexSpiDeviceType_MCP_NOR_NAND = 0x12, //!< Flash device is MCP device, A1 is Serial NOR, A2 is Serial NAND
kFlexSpiDeviceType_MCP_NOR_RAM = 0x13, //!< Flash deivce is MCP device, A1 is Serial NOR, A2 is Serial RAMs
};
//!@brief Flash Pad Definitions
enum
{
kSerialFlash_1Pad = 1,
kSerialFlash_2Pads = 2,
kSerialFlash_4Pads = 4,
kSerialFlash_8Pads = 8,
};
//!@brief FlexSPI LUT Sequence structure
typedef struct _lut_sequence
{
uint8_t seqNum; //!< Sequence Number, valid number: 1-16
uint8_t seqId; //!< Sequence Index, valid number: 0-15
uint16_t reserved;
} flexspi_lut_seq_t;
//!@brief Flash Configuration Command Type
enum
{
kDeviceConfigCmdType_Generic, //!< Generic command, for example: configure dummy cycles, drive strength, etc
kDeviceConfigCmdType_QuadEnable, //!< Quad Enable command
kDeviceConfigCmdType_Spi2Xpi, //!< Switch from SPI to DPI/QPI/OPI mode
kDeviceConfigCmdType_Xpi2Spi, //!< Switch from DPI/QPI/OPI to SPI mode
kDeviceConfigCmdType_Spi2NoCmd, //!< Switch to 0-4-4/0-8-8 mode
kDeviceConfigCmdType_Reset, //!< Reset device command
};
//!@brief FlexSPI Memory Configuration Block
typedef struct _FlexSPIConfig
{
uint32_t tag; //!< [0x000-0x003] Tag, fixed value 0x42464346UL
uint32_t version; //!< [0x004-0x007] Version,[31:24] -'V', [23:16] - Major, [15:8] - Minor, [7:0] - bugfix
uint32_t reserved0; //!< [0x008-0x00b] Reserved for future use
uint8_t readSampleClkSrc; //!< [0x00c-0x00c] Read Sample Clock Source, valid value: 0/1/3
uint8_t csHoldTime; //!< [0x00d-0x00d] CS hold time, default value: 3
uint8_t csSetupTime; //!< [0x00e-0x00e] CS setup time, default value: 3
uint8_t columnAddressWidth; //!< [0x00f-0x00f] Column Address with, for HyperBus protocol, it is fixed to 3, For
//! Serial NAND, need to refer to datasheet
uint8_t deviceModeCfgEnable; //!< [0x010-0x010] Device Mode Configure enable flag, 1 - Enable, 0 - Disable
uint8_t deviceModeType; //!< [0x011-0x011] Specify the configuration command type:Quad Enable, DPI/QPI/OPI switch,
//! Generic configuration, etc.
uint16_t waitTimeCfgCommands; //!< [0x012-0x013] Wait time for all configuration commands, unit: 100us, Used for
//! DPI/QPI/OPI switch or reset command
flexspi_lut_seq_t deviceModeSeq; //!< [0x014-0x017] Device mode sequence info, [7:0] - LUT sequence id, [15:8] - LUt
//! sequence number, [31:16] Reserved
uint32_t deviceModeArg; //!< [0x018-0x01b] Argument/Parameter for device configuration
uint8_t configCmdEnable; //!< [0x01c-0x01c] Configure command Enable Flag, 1 - Enable, 0 - Disable
uint8_t configModeType[3]; //!< [0x01d-0x01f] Configure Mode Type, similar as deviceModeTpe
flexspi_lut_seq_t
configCmdSeqs[3]; //!< [0x020-0x02b] Sequence info for Device Configuration command, similar as deviceModeSeq
uint32_t reserved1; //!< [0x02c-0x02f] Reserved for future use
uint32_t configCmdArgs[3]; //!< [0x030-0x03b] Arguments/Parameters for device Configuration commands
uint32_t reserved2; //!< [0x03c-0x03f] Reserved for future use
uint32_t controllerMiscOption; //!< [0x040-0x043] Controller Misc Options, see Misc feature bit definitions for more
//! details
uint8_t deviceType; //!< [0x044-0x044] Device Type: See Flash Type Definition for more details
uint8_t sflashPadType; //!< [0x045-0x045] Serial Flash Pad Type: 1 - Single, 2 - Dual, 4 - Quad, 8 - Octal
uint8_t serialClkFreq; //!< [0x046-0x046] Serial Flash Frequencey, device specific definitions, See System Boot
//! Chapter for more details
uint8_t lutCustomSeqEnable; //!< [0x047-0x047] LUT customization Enable, it is required if the program/erase cannot
//! be done using 1 LUT sequence, currently, only applicable to HyperFLASH
uint32_t reserved3[2]; //!< [0x048-0x04f] Reserved for future use
uint32_t sflashA1Size; //!< [0x050-0x053] Size of Flash connected to A1
uint32_t sflashA2Size; //!< [0x054-0x057] Size of Flash connected to A2
uint32_t sflashB1Size; //!< [0x058-0x05b] Size of Flash connected to B1
uint32_t sflashB2Size; //!< [0x05c-0x05f] Size of Flash connected to B2
uint32_t csPadSettingOverride; //!< [0x060-0x063] CS pad setting override value
uint32_t sclkPadSettingOverride; //!< [0x064-0x067] SCK pad setting override value
uint32_t dataPadSettingOverride; //!< [0x068-0x06b] data pad setting override value
uint32_t dqsPadSettingOverride; //!< [0x06c-0x06f] DQS pad setting override value
uint32_t timeoutInMs; //!< [0x070-0x073] Timeout threshold for read status command
uint32_t commandInterval; //!< [0x074-0x077] CS deselect interval between two commands
uint16_t dataValidTime[2]; //!< [0x078-0x07b] CLK edge to data valid time for PORT A and PORT B, in terms of 0.1ns
uint16_t busyOffset; //!< [0x07c-0x07d] Busy offset, valid value: 0-31
uint16_t busyBitPolarity; //!< [0x07e-0x07f] Busy flag polarity, 0 - busy flag is 1 when flash device is busy, 1 -
//! busy flag is 0 when flash device is busy
uint32_t lookupTable[64]; //!< [0x080-0x17f] Lookup table holds Flash command sequences
flexspi_lut_seq_t lutCustomSeq[12]; //!< [0x180-0x1af] Customizable LUT Sequences
uint32_t reserved4[4]; //!< [0x1b0-0x1bf] Reserved for future use
} flexspi_mem_config_t;
/* */
#define NOR_CMD_INDEX_READ CMD_INDEX_READ //!< 0
#define NOR_CMD_INDEX_READSTATUS CMD_INDEX_READSTATUS //!< 1
#define NOR_CMD_INDEX_WRITEENABLE CMD_INDEX_WRITEENABLE //!< 2
#define NOR_CMD_INDEX_ERASESECTOR 3 //!< 3
#define NOR_CMD_INDEX_PAGEPROGRAM CMD_INDEX_WRITE //!< 4
#define NOR_CMD_INDEX_CHIPERASE 5 //!< 5
#define NOR_CMD_INDEX_DUMMY 6 //!< 6
#define NOR_CMD_INDEX_ERASEBLOCK 7 //!< 7
#define NOR_CMD_LUT_SEQ_IDX_READ CMD_LUT_SEQ_IDX_READ //!< 0 READ LUT sequence id in lookupTable stored in config block
#define NOR_CMD_LUT_SEQ_IDX_READSTATUS \
CMD_LUT_SEQ_IDX_READSTATUS //!< 1 Read Status LUT sequence id in lookupTable stored in config block
#define NOR_CMD_LUT_SEQ_IDX_READSTATUS_XPI \
2 //!< 2 Read status DPI/QPI/OPI sequence id in lookupTable stored in config block
#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE \
CMD_LUT_SEQ_IDX_WRITEENABLE //!< 3 Write Enable sequence id in lookupTable stored in config block
#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE_XPI \
4 //!< 4 Write Enable DPI/QPI/OPI sequence id in lookupTable stored in config block
#define NOR_CMD_LUT_SEQ_IDX_ERASESECTOR 5 //!< 5 Erase Sector sequence id in lookupTable stored in config block
#define NOR_CMD_LUT_SEQ_IDX_ERASEBLOCK 8 //!< 8 Erase Block sequence id in lookupTable stored in config block
#define NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM \
CMD_LUT_SEQ_IDX_WRITE //!< 9 Program sequence id in lookupTable stored in config block
#define NOR_CMD_LUT_SEQ_IDX_CHIPERASE 11 //!< 11 Chip Erase sequence in lookupTable id stored in config block
#define NOR_CMD_LUT_SEQ_IDX_READ_SFDP 13 //!< 13 Read SFDP sequence in lookupTable id stored in config block
#define NOR_CMD_LUT_SEQ_IDX_RESTORE_NOCMD \
14 //!< 14 Restore 0-4-4/0-8-8 mode sequence id in lookupTable stored in config block
#define NOR_CMD_LUT_SEQ_IDX_EXIT_NOCMD \
15 //!< 15 Exit 0-4-4/0-8-8 mode sequence id in lookupTable stored in config blobk
/*
* Serial NOR configuration block
*/
typedef struct _flexspi_nor_config
{
flexspi_mem_config_t memConfig; //!< Common memory configuration info via FlexSPI
uint32_t pageSize; //!< Page size of Serial NOR
uint32_t sectorSize; //!< Sector size of Serial NOR
uint8_t ipcmdSerialClkFreq; //!< Clock frequency for IP command
uint8_t isUniformBlockSize; //!< Sector/Block size is the same
uint8_t reserved0[2]; //!< Reserved for future use
uint8_t serialNorType; //!< Serial NOR Flash type: 0/1/2/3
uint8_t needExitNoCmdMode; //!< Need to exit NoCmd mode before other IP command
uint8_t halfClkForNonReadCmd; //!< Half the Serial Clock for non-read command: true/false
uint8_t needRestoreNoCmdMode; //!< Need to Restore NoCmd mode after IP commmand execution
uint32_t blockSize; //!< Block size
uint32_t reserve2[11]; //!< Reserved for future use
} flexspi_nor_config_t;
#ifdef __cplusplus
extern "C" {
#endif
#ifdef __cplusplus
}
#endif
#endif /* __EVKBIMXRT1050_FLEXSPI_NOR_CONFIG__ */

1105
ext/hal/nxp/mcux/boards/evkbimxrt1050/evkbimxrt1050_sdram_ini_dcd.c Normal file
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27
ext/hal/nxp/mcux/boards/evkbimxrt1050/evkbimxrt1050_sdram_ini_dcd.h Normal file
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@ -0,0 +1,27 @@
/*
* Copyright 2017 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef __EVKBIMXRT1050_DCD_SDRAM_INIT__
#define __EVKBIMXRT1050_DCD_SDRAM_INIT__
#include <stdint.h>
/*! @name Driver version */
/*@{*/
/*! @brief XIP_BOARD driver version 2.0.0. */
#define FSL_XIP_BOARD_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
/*@}*/
/*************************************
* DCD Data
*************************************/
#define DCD_TAG_HEADER (0xD2)
#define DCD_TAG_HEADER_SHIFT (24)
#define DCD_VERSION (0x40)
#define DCD_ARRAY_SIZE 1
#endif /* __EVKBIMXRT1050_DCD_SDRAM_INIT__ */

49
ext/hal/nxp/mcux/boards/evkmimxrt1060/evkmimxrt1060_flexspi_nor_config.c Normal file
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@ -0,0 +1,49 @@
/*
* Copyright 2018 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include "evkmimxrt1060_flexspi_nor_config.h"
/* Component ID definition, used by tools. */
#ifndef FSL_COMPONENT_ID
#define FSL_COMPONENT_ID "platform.drivers.xip_board"
#endif
/*******************************************************************************
* Code
******************************************************************************/
#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1)
#if defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__)
__attribute__((section(".boot_hdr.conf")))
#elif defined(__ICCARM__)
#pragma location = ".boot_hdr.conf"
#endif
const flexspi_nor_config_t qspiflash_config = {
.memConfig =
{
.tag = FLEXSPI_CFG_BLK_TAG,
.version = FLEXSPI_CFG_BLK_VERSION,
.readSampleClkSrc = kFlexSPIReadSampleClk_LoopbackFromDqsPad,
.csHoldTime = 3u,
.csSetupTime = 3u,
// Enable DDR mode, Wordaddassable, Safe configuration, Differential clock
.sflashPadType = kSerialFlash_4Pads,
.serialClkFreq = kFlexSpiSerialClk_100MHz,
.sflashA1Size = 8u * 1024u * 1024u,
.lookupTable =
{
// Read LUTs
FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB, RADDR_SDR, FLEXSPI_4PAD, 0x18),
FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 0x06, READ_SDR, FLEXSPI_4PAD, 0x04),
},
},
.pageSize = 256u,
.sectorSize = 4u * 1024u,
.blockSize = 256u * 1024u,
.isUniformBlockSize = false,
};
#endif /* XIP_BOOT_HEADER_ENABLE */

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/*
* Copyright 2018 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef __EVKMIMXRT1060_FLEXSPI_NOR_CONFIG__
#define __EVKMIMXRT1060_FLEXSPI_NOR_CONFIG__
#include <stdint.h>
#include <stdbool.h>
#include "fsl_common.h"
/*! @name Driver version */
/*@{*/
/*! @brief XIP_BOARD driver version 2.0.0. */
#define FSL_XIP_BOARD_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
/*@}*/
/* FLEXSPI memory config block related defintions */
#define FLEXSPI_CFG_BLK_TAG (0x42464346UL) // ascii "FCFB" Big Endian
#define FLEXSPI_CFG_BLK_VERSION (0x56010400UL) // V1.4.0
#define FLEXSPI_CFG_BLK_SIZE (512)
/* FLEXSPI Feature related definitions */
#define FLEXSPI_FEATURE_HAS_PARALLEL_MODE 1
/* Lookup table related defintions */
#define CMD_INDEX_READ 0
#define CMD_INDEX_READSTATUS 1
#define CMD_INDEX_WRITEENABLE 2
#define CMD_INDEX_WRITE 4
#define CMD_LUT_SEQ_IDX_READ 0
#define CMD_LUT_SEQ_IDX_READSTATUS 1
#define CMD_LUT_SEQ_IDX_WRITEENABLE 3
#define CMD_LUT_SEQ_IDX_WRITE 9
#define CMD_SDR 0x01
#define CMD_DDR 0x21
#define RADDR_SDR 0x02
#define RADDR_DDR 0x22
#define CADDR_SDR 0x03
#define CADDR_DDR 0x23
#define MODE1_SDR 0x04
#define MODE1_DDR 0x24
#define MODE2_SDR 0x05
#define MODE2_DDR 0x25
#define MODE4_SDR 0x06
#define MODE4_DDR 0x26
#define MODE8_SDR 0x07
#define MODE8_DDR 0x27
#define WRITE_SDR 0x08
#define WRITE_DDR 0x28
#define READ_SDR 0x09
#define READ_DDR 0x29
#define LEARN_SDR 0x0A
#define LEARN_DDR 0x2A
#define DATSZ_SDR 0x0B
#define DATSZ_DDR 0x2B
#define DUMMY_SDR 0x0C
#define DUMMY_DDR 0x2C
#define DUMMY_RWDS_SDR 0x0D
#define DUMMY_RWDS_DDR 0x2D
#define JMP_ON_CS 0x1F
#define STOP 0
#define FLEXSPI_1PAD 0
#define FLEXSPI_2PAD 1
#define FLEXSPI_4PAD 2
#define FLEXSPI_8PAD 3
#define FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) \
(FLEXSPI_LUT_OPERAND0(op0) | FLEXSPI_LUT_NUM_PADS0(pad0) | FLEXSPI_LUT_OPCODE0(cmd0) | FLEXSPI_LUT_OPERAND1(op1) | \
FLEXSPI_LUT_NUM_PADS1(pad1) | FLEXSPI_LUT_OPCODE1(cmd1))
//!@brief Definitions for FlexSPI Serial Clock Frequency
typedef enum _FlexSpiSerialClockFreq
{
kFlexSpiSerialClk_30MHz = 1,
kFlexSpiSerialClk_50MHz = 2,
kFlexSpiSerialClk_60MHz = 3,
kFlexSpiSerialClk_75MHz = 4,
kFlexSpiSerialClk_80MHz = 5,
kFlexSpiSerialClk_100MHz = 6,
kFlexSpiSerialClk_120MHz = 7,
kFlexSpiSerialClk_133MHz = 8,
kFlexSpiSerialClk_166MHz = 9,
} flexspi_serial_clk_freq_t;
//!@brief FlexSPI clock configuration type
enum
{
kFlexSpiClk_SDR, //!< Clock configure for SDR mode
kFlexSpiClk_DDR, //!< Clock configurat for DDR mode
};
//!@brief FlexSPI Read Sample Clock Source definition
typedef enum _FlashReadSampleClkSource
{
kFlexSPIReadSampleClk_LoopbackInternally = 0,
kFlexSPIReadSampleClk_LoopbackFromDqsPad = 1,
kFlexSPIReadSampleClk_LoopbackFromSckPad = 2,
kFlexSPIReadSampleClk_ExternalInputFromDqsPad = 3,
} flexspi_read_sample_clk_t;
//!@brief Misc feature bit definitions
enum
{
kFlexSpiMiscOffset_DiffClkEnable = 0, //!< Bit for Differential clock enable
kFlexSpiMiscOffset_Ck2Enable = 1, //!< Bit for CK2 enable
kFlexSpiMiscOffset_ParallelEnable = 2, //!< Bit for Parallel mode enable
kFlexSpiMiscOffset_WordAddressableEnable = 3, //!< Bit for Word Addressable enable
kFlexSpiMiscOffset_SafeConfigFreqEnable = 4, //!< Bit for Safe Configuration Frequency enable
kFlexSpiMiscOffset_PadSettingOverrideEnable = 5, //!< Bit for Pad setting override enable
kFlexSpiMiscOffset_DdrModeEnable = 6, //!< Bit for DDR clock confiuration indication.
};
//!@brief Flash Type Definition
enum
{
kFlexSpiDeviceType_SerialNOR = 1, //!< Flash devices are Serial NOR
kFlexSpiDeviceType_SerialNAND = 2, //!< Flash devices are Serial NAND
kFlexSpiDeviceType_SerialRAM = 3, //!< Flash devices are Serial RAM/HyperFLASH
kFlexSpiDeviceType_MCP_NOR_NAND = 0x12, //!< Flash device is MCP device, A1 is Serial NOR, A2 is Serial NAND
kFlexSpiDeviceType_MCP_NOR_RAM = 0x13, //!< Flash deivce is MCP device, A1 is Serial NOR, A2 is Serial RAMs
};
//!@brief Flash Pad Definitions
enum
{
kSerialFlash_1Pad = 1,
kSerialFlash_2Pads = 2,
kSerialFlash_4Pads = 4,
kSerialFlash_8Pads = 8,
};
//!@brief FlexSPI LUT Sequence structure
typedef struct _lut_sequence
{
uint8_t seqNum; //!< Sequence Number, valid number: 1-16
uint8_t seqId; //!< Sequence Index, valid number: 0-15
uint16_t reserved;
} flexspi_lut_seq_t;
//!@brief Flash Configuration Command Type
enum
{
kDeviceConfigCmdType_Generic, //!< Generic command, for example: configure dummy cycles, drive strength, etc
kDeviceConfigCmdType_QuadEnable, //!< Quad Enable command
kDeviceConfigCmdType_Spi2Xpi, //!< Switch from SPI to DPI/QPI/OPI mode
kDeviceConfigCmdType_Xpi2Spi, //!< Switch from DPI/QPI/OPI to SPI mode
kDeviceConfigCmdType_Spi2NoCmd, //!< Switch to 0-4-4/0-8-8 mode
kDeviceConfigCmdType_Reset, //!< Reset device command
};
//!@brief FlexSPI Memory Configuration Block
typedef struct _FlexSPIConfig
{
uint32_t tag; //!< [0x000-0x003] Tag, fixed value 0x42464346UL
uint32_t version; //!< [0x004-0x007] Version,[31:24] -'V', [23:16] - Major, [15:8] - Minor, [7:0] - bugfix
uint32_t reserved0; //!< [0x008-0x00b] Reserved for future use
uint8_t readSampleClkSrc; //!< [0x00c-0x00c] Read Sample Clock Source, valid value: 0/1/3
uint8_t csHoldTime; //!< [0x00d-0x00d] CS hold time, default value: 3
uint8_t csSetupTime; //!< [0x00e-0x00e] CS setup time, default value: 3
uint8_t columnAddressWidth; //!< [0x00f-0x00f] Column Address with, for HyperBus protocol, it is fixed to 3, For
//! Serial NAND, need to refer to datasheet
uint8_t deviceModeCfgEnable; //!< [0x010-0x010] Device Mode Configure enable flag, 1 - Enable, 0 - Disable
uint8_t deviceModeType; //!< [0x011-0x011] Specify the configuration command type:Quad Enable, DPI/QPI/OPI switch,
//! Generic configuration, etc.
uint16_t waitTimeCfgCommands; //!< [0x012-0x013] Wait time for all configuration commands, unit: 100us, Used for
//! DPI/QPI/OPI switch or reset command
flexspi_lut_seq_t deviceModeSeq; //!< [0x014-0x017] Device mode sequence info, [7:0] - LUT sequence id, [15:8] - LUt
//! sequence number, [31:16] Reserved
uint32_t deviceModeArg; //!< [0x018-0x01b] Argument/Parameter for device configuration
uint8_t configCmdEnable; //!< [0x01c-0x01c] Configure command Enable Flag, 1 - Enable, 0 - Disable
uint8_t configModeType[3]; //!< [0x01d-0x01f] Configure Mode Type, similar as deviceModeTpe
flexspi_lut_seq_t
configCmdSeqs[3]; //!< [0x020-0x02b] Sequence info for Device Configuration command, similar as deviceModeSeq
uint32_t reserved1; //!< [0x02c-0x02f] Reserved for future use
uint32_t configCmdArgs[3]; //!< [0x030-0x03b] Arguments/Parameters for device Configuration commands
uint32_t reserved2; //!< [0x03c-0x03f] Reserved for future use
uint32_t controllerMiscOption; //!< [0x040-0x043] Controller Misc Options, see Misc feature bit definitions for more
//! details
uint8_t deviceType; //!< [0x044-0x044] Device Type: See Flash Type Definition for more details
uint8_t sflashPadType; //!< [0x045-0x045] Serial Flash Pad Type: 1 - Single, 2 - Dual, 4 - Quad, 8 - Octal
uint8_t serialClkFreq; //!< [0x046-0x046] Serial Flash Frequencey, device specific definitions, See System Boot
//! Chapter for more details
uint8_t lutCustomSeqEnable; //!< [0x047-0x047] LUT customization Enable, it is required if the program/erase cannot
//! be done using 1 LUT sequence, currently, only applicable to HyperFLASH
uint32_t reserved3[2]; //!< [0x048-0x04f] Reserved for future use
uint32_t sflashA1Size; //!< [0x050-0x053] Size of Flash connected to A1
uint32_t sflashA2Size; //!< [0x054-0x057] Size of Flash connected to A2
uint32_t sflashB1Size; //!< [0x058-0x05b] Size of Flash connected to B1
uint32_t sflashB2Size; //!< [0x05c-0x05f] Size of Flash connected to B2
uint32_t csPadSettingOverride; //!< [0x060-0x063] CS pad setting override value
uint32_t sclkPadSettingOverride; //!< [0x064-0x067] SCK pad setting override value
uint32_t dataPadSettingOverride; //!< [0x068-0x06b] data pad setting override value
uint32_t dqsPadSettingOverride; //!< [0x06c-0x06f] DQS pad setting override value
uint32_t timeoutInMs; //!< [0x070-0x073] Timeout threshold for read status command
uint32_t commandInterval; //!< [0x074-0x077] CS deselect interval between two commands
uint16_t dataValidTime[2]; //!< [0x078-0x07b] CLK edge to data valid time for PORT A and PORT B, in terms of 0.1ns
uint16_t busyOffset; //!< [0x07c-0x07d] Busy offset, valid value: 0-31
uint16_t busyBitPolarity; //!< [0x07e-0x07f] Busy flag polarity, 0 - busy flag is 1 when flash device is busy, 1 -
//! busy flag is 0 when flash device is busy
uint32_t lookupTable[64]; //!< [0x080-0x17f] Lookup table holds Flash command sequences
flexspi_lut_seq_t lutCustomSeq[12]; //!< [0x180-0x1af] Customizable LUT Sequences
uint32_t reserved4[4]; //!< [0x1b0-0x1bf] Reserved for future use
} flexspi_mem_config_t;
/* */
#define NOR_CMD_INDEX_READ CMD_INDEX_READ //!< 0
#define NOR_CMD_INDEX_READSTATUS CMD_INDEX_READSTATUS //!< 1
#define NOR_CMD_INDEX_WRITEENABLE CMD_INDEX_WRITEENABLE //!< 2
#define NOR_CMD_INDEX_ERASESECTOR 3 //!< 3
#define NOR_CMD_INDEX_PAGEPROGRAM CMD_INDEX_WRITE //!< 4
#define NOR_CMD_INDEX_CHIPERASE 5 //!< 5
#define NOR_CMD_INDEX_DUMMY 6 //!< 6
#define NOR_CMD_INDEX_ERASEBLOCK 7 //!< 7
#define NOR_CMD_LUT_SEQ_IDX_READ CMD_LUT_SEQ_IDX_READ //!< 0 READ LUT sequence id in lookupTable stored in config block
#define NOR_CMD_LUT_SEQ_IDX_READSTATUS \
CMD_LUT_SEQ_IDX_READSTATUS //!< 1 Read Status LUT sequence id in lookupTable stored in config block
#define NOR_CMD_LUT_SEQ_IDX_READSTATUS_XPI \
2 //!< 2 Read status DPI/QPI/OPI sequence id in lookupTable stored in config block
#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE \
CMD_LUT_SEQ_IDX_WRITEENABLE //!< 3 Write Enable sequence id in lookupTable stored in config block
#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE_XPI \
4 //!< 4 Write Enable DPI/QPI/OPI sequence id in lookupTable stored in config block
#define NOR_CMD_LUT_SEQ_IDX_ERASESECTOR 5 //!< 5 Erase Sector sequence id in lookupTable stored in config block
#define NOR_CMD_LUT_SEQ_IDX_ERASEBLOCK 8 //!< 8 Erase Block sequence id in lookupTable stored in config block
#define NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM \
CMD_LUT_SEQ_IDX_WRITE //!< 9 Program sequence id in lookupTable stored in config block
#define NOR_CMD_LUT_SEQ_IDX_CHIPERASE 11 //!< 11 Chip Erase sequence in lookupTable id stored in config block
#define NOR_CMD_LUT_SEQ_IDX_READ_SFDP 13 //!< 13 Read SFDP sequence in lookupTable id stored in config block
#define NOR_CMD_LUT_SEQ_IDX_RESTORE_NOCMD \
14 //!< 14 Restore 0-4-4/0-8-8 mode sequence id in lookupTable stored in config block
#define NOR_CMD_LUT_SEQ_IDX_EXIT_NOCMD \
15 //!< 15 Exit 0-4-4/0-8-8 mode sequence id in lookupTable stored in config blobk
/*
* Serial NOR configuration block
*/
typedef struct _flexspi_nor_config
{
flexspi_mem_config_t memConfig; //!< Common memory configuration info via FlexSPI
uint32_t pageSize; //!< Page size of Serial NOR
uint32_t sectorSize; //!< Sector size of Serial NOR
uint8_t ipcmdSerialClkFreq; //!< Clock frequency for IP command
uint8_t isUniformBlockSize; //!< Sector/Block size is the same
uint8_t reserved0[2]; //!< Reserved for future use
uint8_t serialNorType; //!< Serial NOR Flash type: 0/1/2/3
uint8_t needExitNoCmdMode; //!< Need to exit NoCmd mode before other IP command
uint8_t halfClkForNonReadCmd; //!< Half the Serial Clock for non-read command: true/false
uint8_t needRestoreNoCmdMode; //!< Need to Restore NoCmd mode after IP commmand execution
uint32_t blockSize; //!< Block size
uint32_t reserve2[11]; //!< Reserved for future use
} flexspi_nor_config_t;
#ifdef __cplusplus
extern "C" {
#endif
#ifdef __cplusplus
}
#endif
#endif /* __EVKMIMXRT1060_FLEXSPI_NOR_CONFIG__ */

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/*
* Copyright 2018 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef __EVKMIMXRT1060_DCD_SDRAM_INIT__
#define __EVKMIMXRT1060_DCD_SDRAM_INIT__
#include <stdint.h>
/*! @name Driver version */
/*@{*/
/*! @brief XIP_BOARD driver version 2.0.0. */
#define FSL_XIP_BOARD_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
/*@}*/
/*************************************
* DCD Data
*************************************/
#define DCD_TAG_HEADER (0xD2)
#define DCD_TAG_HEADER_SHIFT (24)
#define DCD_VERSION (0x40)
#define DCD_ARRAY_SIZE 1
#endif /* __EVKMIMXRT1060_DCD_SDRAM_INIT__ */

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/*
** ###################################################################
** Version: rev. 1.0, 2016-05-09
** Build: b161227
** Build: b180806
**
** Abstract:
** Chip specific module features.
**
** Copyright (c) 2016 Freescale Semiconductor, Inc.
** Copyright 2016 - 2017 NXP
** Redistribution and use in source and binary forms, with or without modification,
** are permitted provided that the following conditions are met:
** Copyright 2016 Freescale Semiconductor, Inc.
** Copyright 2016-2018 NXP
**
** o Redistributions of source code must retain the above copyright notice, this list
** of conditions and the following disclaimer.
**
** o Redistributions in binary form must reproduce the above copyright notice, this
** list of conditions and the following disclaimer in the documentation and/or
** other materials provided with the distribution.
**
** o Neither the name of the copyright holder nor the names of its
** contributors may be used to endorse or promote products derived from this
** software without specific prior written permission.
**
** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
** SPDX-License-Identifier: BSD-3-Clause
**
** http: www.nxp.com
** mail: support@nxp.com
@ -54,6 +32,8 @@
#define FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT (1)
/* @brief CRC availability on the SoC. */
#define FSL_FEATURE_SOC_CRC_COUNT (1)
/* @brief CTIMER availability on the SoC. */
#define FSL_FEATURE_SOC_CTIMER_COUNT (5)
/* @brief DMA availability on the SoC. */
#define FSL_FEATURE_SOC_DMA_COUNT (1)
/* @brief DMIC availability on the SoC. */
@ -88,8 +68,6 @@
#define FSL_FEATURE_SOC_SPIFI_COUNT (1)
/* @brief SYSCON availability on the SoC. */
#define FSL_FEATURE_SOC_SYSCON_COUNT (1)
/* @brief CTIMER availability on the SoC. */
#define FSL_FEATURE_SOC_CTIMER_COUNT (5)
/* @brief USART availability on the SoC. */
#define FSL_FEATURE_SOC_USART_COUNT (8)
/* @brief USB availability on the SoC. */
@ -99,16 +77,118 @@
/* @brief WWDT availability on the SoC. */
#define FSL_FEATURE_SOC_WWDT_COUNT (1)
/* ADC module features */
/* @brief Do not has input select (register INSEL). */
#define FSL_FEATURE_ADC_HAS_NO_INSEL (0)
/* @brief Has ASYNMODE bitfile in CTRL reigster. */
#define FSL_FEATURE_ADC_HAS_CTRL_ASYNMODE (1)
/* @brief Has ASYNMODE bitfile in CTRL reigster. */
#define FSL_FEATURE_ADC_HAS_CTRL_RESOL (1)
/* @brief Has ASYNMODE bitfile in CTRL reigster. */
#define FSL_FEATURE_ADC_HAS_CTRL_BYPASSCAL (1)
/* @brief Has ASYNMODE bitfile in CTRL reigster. */
#define FSL_FEATURE_ADC_HAS_CTRL_TSAMP (1)
/* @brief Has ASYNMODE bitfile in CTRL reigster. */
#define FSL_FEATURE_ADC_HAS_CTRL_LPWRMODE (0)
/* @brief Has ASYNMODE bitfile in CTRL reigster. */
#define FSL_FEATURE_ADC_HAS_CTRL_CALMODE (0)
/* @brief Has startup register. */
#define FSL_FEATURE_ADC_HAS_STARTUP_REG (1)
/* @brief Has ADTrim register */
#define FSL_FEATURE_ADC_HAS_TRIM_REG (0)
/* @brief Has Calibration register. */
#define FSL_FEATURE_ADC_HAS_CALIB_REG (1)
/* DMA module features */
/* @brief Number of channels */
#define FSL_FEATURE_DMA_NUMBER_OF_CHANNELS (20)
/* FLEXCOMM module features */
/* @brief FLEXCOMM0 USART INDEX 0 */
#define FSL_FEATURE_FLEXCOMM0_USART_INDEX (0)
/* @brief FLEXCOMM0 SPI INDEX 0 */
#define FSL_FEATURE_FLEXCOMM0_SPI_INDEX (0)
/* @brief FLEXCOMM0 I2C INDEX 0 */
#define FSL_FEATURE_FLEXCOMM0_I2C_INDEX (0)
/* @brief FLEXCOMM1 USART INDEX 1 */
#define FSL_FEATURE_FLEXCOMM1_USART_INDEX (1)
/* @brief FLEXCOMM1 SPI INDEX 1 */
#define FSL_FEATURE_FLEXCOMM1_SPI_INDEX (1)
/* @brief FLEXCOMM1 I2C INDEX 1 */
#define FSL_FEATURE_FLEXCOMM1_I2C_INDEX (1)
/* @brief FLEXCOMM2 USART INDEX 2 */
#define FSL_FEATURE_FLEXCOMM2_USART_INDEX (2)
/* @brief FLEXCOMM2 SPI INDEX 2 */
#define FSL_FEATURE_FLEXCOMM2_SPI_INDEX (2)
/* @brief FLEXCOMM2 I2C INDEX 2 */
#define FSL_FEATURE_FLEXCOMM2_I2C_INDEX (2)
/* @brief FLEXCOMM3 USART INDEX 3 */
#define FSL_FEATURE_FLEXCOMM3_USART_INDEX (3)
/* @brief FLEXCOMM3 SPI INDEX 3 */
#define FSL_FEATURE_FLEXCOMM3_SPI_INDEX (3)
/* @brief FLEXCOMM3 I2C INDEX 3 */
#define FSL_FEATURE_FLEXCOMM3_I2C_INDEX (3)
/* @brief FLEXCOMM4 USART INDEX 4 */
#define FSL_FEATURE_FLEXCOMM4_USART_INDEX (4)
/* @brief FLEXCOMM4 SPI INDEX 4 */
#define FSL_FEATURE_FLEXCOMM4_SPI_INDEX (4)
/* @brief FLEXCOMM4 I2C INDEX 4 */
#define FSL_FEATURE_FLEXCOMM4_I2C_INDEX (4)
/* @brief FLEXCOMM5 USART INDEX 5 */
#define FSL_FEATURE_FLEXCOMM5_USART_INDEX (5)
/* @brief FLEXCOMM5 SPI INDEX 5 */
#define FSL_FEATURE_FLEXCOMM5_SPI_INDEX (5)
/* @brief FLEXCOMM5 I2C INDEX 5 */
#define FSL_FEATURE_FLEXCOMM5_I2C_INDEX (5)
/* @brief FLEXCOMM6 USART INDEX 6 */
#define FSL_FEATURE_FLEXCOMM6_USART_INDEX (6)
/* @brief FLEXCOMM6 SPI INDEX 6 */
#define FSL_FEATURE_FLEXCOMM6_SPI_INDEX (6)
/* @brief FLEXCOMM6 I2C INDEX 6 */
#define FSL_FEATURE_FLEXCOMM6_I2C_INDEX (6)
/* @brief FLEXCOMM7 I2S INDEX 0 */
#define FSL_FEATURE_FLEXCOMM6_I2S_INDEX (0)
/* @brief FLEXCOMM7 USART INDEX 7 */
#define FSL_FEATURE_FLEXCOMM7_USART_INDEX (7)
/* @brief FLEXCOMM7 SPI INDEX 7 */
#define FSL_FEATURE_FLEXCOMM7_SPI_INDEX (7)
/* @brief FLEXCOMM7 I2C INDEX 7 */
#define FSL_FEATURE_FLEXCOMM7_I2C_INDEX (7)
/* @brief FLEXCOMM7 I2S INDEX 1 */
#define FSL_FEATURE_FLEXCOMM7_I2S_INDEX (1)
/* MAILBOX module features */
/* @brief Mailbox side for current core */
#define FSL_FEATURE_MAILBOX_SIDE_B (1)
/* @brief Mailbox has no reset control */
#define FSL_FEATURE_MAILBOX_HAS_NO_RESET (1)
/* MRT module features */
/* @brief number of channels. */
#define FSL_FEATURE_MRT_NUMBER_OF_CHANNELS (4)
/* interrupt module features */
/* @brief Lowest interrupt request number. */
#define FSL_FEATURE_INTERRUPT_IRQ_MIN (-14)
/* @brief Highest interrupt request number. */
#define FSL_FEATURE_INTERRUPT_IRQ_MAX (105)
/* PINT module features */
/* @brief Number of connected outputs */
#define FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS (4)
/* RTC module features */
/* @brief RTC has no reset control */
#define FSL_FEATURE_RTC_HAS_NO_RESET (1)
/* SCT module features */
/* @brief Number of events */
@ -117,6 +197,8 @@
#define FSL_FEATURE_SCT_NUMBER_OF_STATES (10)
/* @brief Number of match capture */
#define FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE (10)
/* @brief Number of outputs */
#define FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS (8)
/* SYSCON module features */
@ -128,6 +210,24 @@
#define FSL_FEATURE_SYSCON_FLASH_SECTOR_SIZE_BYTES (32768)
/* @brief Flash size in bytes */
#define FSL_FEATURE_SYSCON_FLASH_SIZE_BYTES (262144)
/* @brief IAP has Flash read & write function */
#define FSL_FEATURE_IAP_HAS_FLASH_FUNCTION (1)
/* @brief IAP has read Flash signature function */
#define FSL_FEATURE_IAP_HAS_FLASH_SIGNATURE_READ (1)
/* @brief IAP has read extended Flash signature function */
#define FSL_FEATURE_IAP_HAS_FLASH_EXTENDED_SIGNATURE_READ (0)
/* SysTick module features */
/* @brief Systick has external reference clock. */
#define FSL_FEATURE_SYSTICK_HAS_EXT_REF (0)
/* @brief Systick external reference clock is core clock divided by this value. */
#define FSL_FEATURE_SYSTICK_EXT_REF_CORE_DIV (0)
/* USB module features */
/* @brief Number of the endpoint in USB FS */
#define FSL_FEATURE_USB_EP_NUM (5)
#endif /* _LPC54114_cm0plus_FEATURES_H_ */

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ext/hal/nxp/mcux/devices/LPC54114/LPC54114_cm4_features.h
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@ -1,37 +1,15 @@
/*
** ###################################################################
** Version: rev. 1.0, 2016-05-09
** Build: b161227
** Build: b180806
**
** Abstract:
** Chip specific module features.
**
** Copyright (c) 2016 Freescale Semiconductor, Inc.
** Copyright 2016 - 2017 NXP
** Redistribution and use in source and binary forms, with or without modification,
** are permitted provided that the following conditions are met:
** Copyright 2016 Freescale Semiconductor, Inc.
** Copyright 2016-2018 NXP
**
** o Redistributions of source code must retain the above copyright notice, this list
** of conditions and the following disclaimer.
**
** o Redistributions in binary form must reproduce the above copyright notice, this
** list of conditions and the following disclaimer in the documentation and/or
** other materials provided with the distribution.
**
** o Neither the name of the copyright holder nor the names of its
** contributors may be used to endorse or promote products derived from this
** software without specific prior written permission.
**
** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
** SPDX-License-Identifier: BSD-3-Clause
**
** http: www.nxp.com
** mail: support@nxp.com
@ -54,6 +32,8 @@
#define FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT (1)
/* @brief CRC availability on the SoC. */
#define FSL_FEATURE_SOC_CRC_COUNT (1)
/* @brief CTIMER availability on the SoC. */
#define FSL_FEATURE_SOC_CTIMER_COUNT (5)
/* @brief DMA availability on the SoC. */
#define FSL_FEATURE_SOC_DMA_COUNT (1)
/* @brief DMIC availability on the SoC. */
@ -88,8 +68,6 @@
#define FSL_FEATURE_SOC_SPIFI_COUNT (1)
/* @brief SYSCON availability on the SoC. */
#define FSL_FEATURE_SOC_SYSCON_COUNT (1)
/* @brief CTIMER availability on the SoC. */
#define FSL_FEATURE_SOC_CTIMER_COUNT (5)
/* @brief USART availability on the SoC. */
#define FSL_FEATURE_SOC_USART_COUNT (8)
/* @brief USB availability on the SoC. */
@ -99,16 +77,118 @@
/* @brief WWDT availability on the SoC. */
#define FSL_FEATURE_SOC_WWDT_COUNT (1)
/* ADC module features */
/* @brief Do not has input select (register INSEL). */
#define FSL_FEATURE_ADC_HAS_NO_INSEL (0)
/* @brief Has ASYNMODE bitfile in CTRL reigster. */
#define FSL_FEATURE_ADC_HAS_CTRL_ASYNMODE (1)
/* @brief Has ASYNMODE bitfile in CTRL reigster. */
#define FSL_FEATURE_ADC_HAS_CTRL_RESOL (1)
/* @brief Has ASYNMODE bitfile in CTRL reigster. */
#define FSL_FEATURE_ADC_HAS_CTRL_BYPASSCAL (1)
/* @brief Has ASYNMODE bitfile in CTRL reigster. */
#define FSL_FEATURE_ADC_HAS_CTRL_TSAMP (1)
/* @brief Has ASYNMODE bitfile in CTRL reigster. */
#define FSL_FEATURE_ADC_HAS_CTRL_LPWRMODE (0)
/* @brief Has ASYNMODE bitfile in CTRL reigster. */
#define FSL_FEATURE_ADC_HAS_CTRL_CALMODE (0)
/* @brief Has startup register. */
#define FSL_FEATURE_ADC_HAS_STARTUP_REG (1)
/* @brief Has ADTrim register */
#define FSL_FEATURE_ADC_HAS_TRIM_REG (0)
/* @brief Has Calibration register. */
#define FSL_FEATURE_ADC_HAS_CALIB_REG (1)
/* DMA module features */
/* @brief Number of channels */
#define FSL_FEATURE_DMA_NUMBER_OF_CHANNELS (20)
/* FLEXCOMM module features */
/* @brief FLEXCOMM0 USART INDEX 0 */
#define FSL_FEATURE_FLEXCOMM0_USART_INDEX (0)
/* @brief FLEXCOMM0 SPI INDEX 0 */
#define FSL_FEATURE_FLEXCOMM0_SPI_INDEX (0)
/* @brief FLEXCOMM0 I2C INDEX 0 */
#define FSL_FEATURE_FLEXCOMM0_I2C_INDEX (0)
/* @brief FLEXCOMM1 USART INDEX 1 */
#define FSL_FEATURE_FLEXCOMM1_USART_INDEX (1)
/* @brief FLEXCOMM1 SPI INDEX 1 */
#define FSL_FEATURE_FLEXCOMM1_SPI_INDEX (1)
/* @brief FLEXCOMM1 I2C INDEX 1 */
#define FSL_FEATURE_FLEXCOMM1_I2C_INDEX (1)
/* @brief FLEXCOMM2 USART INDEX 2 */
#define FSL_FEATURE_FLEXCOMM2_USART_INDEX (2)
/* @brief FLEXCOMM2 SPI INDEX 2 */
#define FSL_FEATURE_FLEXCOMM2_SPI_INDEX (2)
/* @brief FLEXCOMM2 I2C INDEX 2 */
#define FSL_FEATURE_FLEXCOMM2_I2C_INDEX (2)
/* @brief FLEXCOMM3 USART INDEX 3 */
#define FSL_FEATURE_FLEXCOMM3_USART_INDEX (3)
/* @brief FLEXCOMM3 SPI INDEX 3 */
#define FSL_FEATURE_FLEXCOMM3_SPI_INDEX (3)
/* @brief FLEXCOMM3 I2C INDEX 3 */
#define FSL_FEATURE_FLEXCOMM3_I2C_INDEX (3)
/* @brief FLEXCOMM4 USART INDEX 4 */
#define FSL_FEATURE_FLEXCOMM4_USART_INDEX (4)
/* @brief FLEXCOMM4 SPI INDEX 4 */
#define FSL_FEATURE_FLEXCOMM4_SPI_INDEX (4)
/* @brief FLEXCOMM4 I2C INDEX 4 */
#define FSL_FEATURE_FLEXCOMM4_I2C_INDEX (4)
/* @brief FLEXCOMM5 USART INDEX 5 */
#define FSL_FEATURE_FLEXCOMM5_USART_INDEX (5)
/* @brief FLEXCOMM5 SPI INDEX 5 */
#define FSL_FEATURE_FLEXCOMM5_SPI_INDEX (5)
/* @brief FLEXCOMM5 I2C INDEX 5 */
#define FSL_FEATURE_FLEXCOMM5_I2C_INDEX (5)
/* @brief FLEXCOMM6 USART INDEX 6 */
#define FSL_FEATURE_FLEXCOMM6_USART_INDEX (6)
/* @brief FLEXCOMM6 SPI INDEX 6 */
#define FSL_FEATURE_FLEXCOMM6_SPI_INDEX (6)
/* @brief FLEXCOMM6 I2C INDEX 6 */
#define FSL_FEATURE_FLEXCOMM6_I2C_INDEX (6)
/* @brief FLEXCOMM7 I2S INDEX 0 */
#define FSL_FEATURE_FLEXCOMM6_I2S_INDEX (0)
/* @brief FLEXCOMM7 USART INDEX 7 */
#define FSL_FEATURE_FLEXCOMM7_USART_INDEX (7)
/* @brief FLEXCOMM7 SPI INDEX 7 */
#define FSL_FEATURE_FLEXCOMM7_SPI_INDEX (7)
/* @brief FLEXCOMM7 I2C INDEX 7 */
#define FSL_FEATURE_FLEXCOMM7_I2C_INDEX (7)
/* @brief FLEXCOMM7 I2S INDEX 1 */
#define FSL_FEATURE_FLEXCOMM7_I2S_INDEX (1)
/* MAILBOX module features */
/* @brief Mailbox side for current core */
#define FSL_FEATURE_MAILBOX_SIDE_A (1)
/* @brief Mailbox has no reset control */
#define FSL_FEATURE_MAILBOX_HAS_NO_RESET (1)
/* MRT module features */
/* @brief number of channels. */
#define FSL_FEATURE_MRT_NUMBER_OF_CHANNELS (4)
/* interrupt module features */
/* @brief Lowest interrupt request number. */
#define FSL_FEATURE_INTERRUPT_IRQ_MIN (-14)
/* @brief Highest interrupt request number. */
#define FSL_FEATURE_INTERRUPT_IRQ_MAX (105)
/* PINT module features */
/* @brief Number of connected outputs */
#define FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS (8)
/* RTC module features */
/* @brief RTC has no reset control */
#define FSL_FEATURE_RTC_HAS_NO_RESET (1)
/* SCT module features */
/* @brief Number of events */
@ -117,6 +197,8 @@
#define FSL_FEATURE_SCT_NUMBER_OF_STATES (10)
/* @brief Number of match capture */
#define FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE (10)
/* @brief Number of outputs */
#define FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS (8)
/* SYSCON module features */
@ -128,6 +210,24 @@
#define FSL_FEATURE_SYSCON_FLASH_SECTOR_SIZE_BYTES (32768)
/* @brief Flash size in bytes */
#define FSL_FEATURE_SYSCON_FLASH_SIZE_BYTES (262144)
/* @brief IAP has Flash read & write function */
#define FSL_FEATURE_IAP_HAS_FLASH_FUNCTION (1)
/* @brief IAP has read Flash signature function */
#define FSL_FEATURE_IAP_HAS_FLASH_SIGNATURE_READ (1)
/* @brief IAP has read extended Flash signature function */
#define FSL_FEATURE_IAP_HAS_FLASH_EXTENDED_SIGNATURE_READ (0)
/* SysTick module features */
/* @brief Systick has external reference clock. */
#define FSL_FEATURE_SYSTICK_HAS_EXT_REF (0)
/* @brief Systick external reference clock is core clock divided by this value. */
#define FSL_FEATURE_SYSTICK_EXT_REF_CORE_DIV (0)
/* USB module features */
/* @brief Number of the endpoint in USB FS */
#define FSL_FEATURE_USB_EP_NUM (5)
#endif /* _LPC54114_cm4_FEATURES_H_ */

545
ext/hal/nxp/mcux/devices/LPC54114/fsl_clock.c
View file

@ -1,32 +1,10 @@
/*
* Copyright (c) 2016, Freescale Semiconductor, Inc.
* Copyright (c) 2016 - 2017 , NXP
* Copyright (c) 2016 - 2018 , NXP
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* SPDX-License-Identifier: BSD-3-Clause
*/
#include "fsl_common.h"
@ -35,6 +13,10 @@
/*******************************************************************************
* Definitions
******************************************************************************/
/* Component ID definition, used by tools. */
#ifndef FSL_COMPONENT_ID
#define FSL_COMPONENT_ID "platform.drivers.clock"
#endif
#define NVALMAX (0x100U)
#define PVALMAX (0x20U)
#define MVALMAX (0x8000U)
@ -86,12 +68,13 @@
computation on each call to retrive the PLL rate. */
static uint32_t s_Pll_Freq;
uint32_t g_I2S_Mclk_Freq = 0U;
/* I2S mclk. */
static uint32_t s_I2S_Mclk_Freq = 0U;
/** External clock rate on the CLKIN pin in Hz. If not used,
set this to 0. Otherwise, set it to the exact rate in Hz this pin is
being driven at. */
const uint32_t g_Ext_Clk_Freq = 0U;
static const uint32_t s_Ext_Clk_Freq = 0U;
/*******************************************************************************
* Variables
@ -134,39 +117,104 @@ static const uint8_t wdtFreqLookup[32] = {0, 8, 12, 15, 18, 20, 24, 26, 28, 30
* Code
******************************************************************************/
/**
* brief Configure the clock selection muxes.
* param connection : Clock to be configured.
* return Nothing
*/
void CLOCK_AttachClk(clock_attach_id_t connection)
{
bool final_descriptor = false;
uint8_t mux;
uint8_t pos;
uint8_t sel;
uint16_t item;
uint32_t i;
volatile uint32_t *pClkSel;
pClkSel = &(SYSCON->MAINCLKSELA);
for (i = 0U; (i <= 2U) && (!final_descriptor); i++)
if (connection != kNONE_to_NONE)
{
connection = (clock_attach_id_t)(connection >> (i * 12U)); /* pick up next descriptor */
mux = (uint8_t)connection;
if (connection)
for (i = 0U; i < 2U; i++)
{
pos = ((connection & 0xf00U) >> 8U) - 1U;
if (mux == CM_ASYNCAPB)
if (connection == 0U)
{
ASYNC_SYSCON->ASYNCAPBCLKSELA = pos;
break;
}
else
item = (uint16_t)GET_ID_ITEM(connection);
if (item)
{
pClkSel[mux] = pos;
mux = GET_ID_ITEM_MUX(item);
sel = GET_ID_ITEM_SEL(item);
if (mux == CM_ASYNCAPB)
{
ASYNC_SYSCON->ASYNCAPBCLKSELA = sel;
}
else
{
pClkSel[mux] = sel;
}
}
}
else
{
final_descriptor = true;
connection = GET_ID_NEXT_ITEM(connection); /* pick up next descriptor */
}
}
}
/* Return the actual clock attach id */
/**
* brief Get the actual clock attach id.
* This fuction uses the offset in input attach id, then it reads the actual source value in
* the register and combine the offset to obtain an actual attach id.
* param attachId : Clock attach id to get.
* return Clock source value.
*/
clock_attach_id_t CLOCK_GetClockAttachId(clock_attach_id_t attachId)
{
uint8_t mux;
uint8_t actualSel;
uint32_t i;
uint32_t actualAttachId = 0U;
uint32_t selector = GET_ID_SELECTOR(attachId);
volatile uint32_t *pClkSel;
pClkSel = &(SYSCON->MAINCLKSELA);
if (attachId == kNONE_to_NONE)
{
return kNONE_to_NONE;
}
for (i = 0U; i < 2U; i++)
{
mux = GET_ID_ITEM_MUX(attachId);
if (attachId)
{
if (mux == CM_ASYNCAPB)
{
actualSel = ASYNC_SYSCON->ASYNCAPBCLKSELA;
}
else
{
actualSel = pClkSel[mux];
}
/* Consider the combination of two registers */
actualAttachId |= CLK_ATTACH_ID(mux, actualSel, i);
}
attachId = GET_ID_NEXT_ITEM(attachId); /*!< pick up next descriptor */
}
actualAttachId |= selector;
return (clock_attach_id_t)actualAttachId;
}
/**
* brief Setup peripheral clock dividers.
* param div_name : Clock divider name
* param divided_by_value: Value to be divided
* param reset : Whether to reset the divider counter.
* return Nothing
*/
void CLOCK_SetClkDiv(clock_div_name_t div_name, uint32_t divided_by_value, bool reset)
{
volatile uint32_t *pClkDiv;
@ -187,6 +235,13 @@ void CLOCK_SetClkDiv(clock_div_name_t div_name, uint32_t divided_by_value, bool
}
/* Set FRO Clocking */
/**
* brief Initialize the Core clock to given frequency (12, 48 or 96 MHz).
* Turns on FRO and uses default CCO, if freq is 12000000, then high speed output is off, else high speed output is
* enabled.
* param iFreq : Desired frequency (must be one of CLK_FRO_12MHZ or CLK_FRO_48MHZ or CLK_FRO_96MHZ)
* return returns success or fail status.
*/
status_t CLOCK_SetupFROClocking(uint32_t iFreq)
{
uint32_t usb_adj;
@ -221,15 +276,24 @@ status_t CLOCK_SetupFROClocking(uint32_t iFreq)
return 0U;
}
/*! brief Return Frequency of FRO 12MHz
* return Frequency of FRO 12MHz
*/
uint32_t CLOCK_GetFro12MFreq(void)
{
return (SYSCON->PDRUNCFG[0] & SYSCON_PDRUNCFG_PDEN_FRO_MASK) ? 0U : 12000000U;
}
/*! brief Return Frequency of External Clock
* return Frequency of External Clock. If no external clock is used returns 0.
*/
uint32_t CLOCK_GetExtClkFreq(void)
{
return (g_Ext_Clk_Freq);
return (s_Ext_Clk_Freq);
}
/*! brief Return Frequency of Watchdog Oscillator
* return Frequency of Watchdog Oscillator
*/
uint32_t CLOCK_GetWdtOscFreq(void)
{
uint8_t freq_sel, div_sel;
@ -246,42 +310,97 @@ uint32_t CLOCK_GetWdtOscFreq(void)
}
}
/* Get HF FRO Clk */
/*! brief Return Frequency of High-Freq output of FRO
* return Frequency of High-Freq output of FRO
*/
uint32_t CLOCK_GetFroHfFreq(void)
{
return (SYSCON->PDRUNCFG[0] & SYSCON_PDRUNCFG_PDEN_FRO_MASK) ?
0 :
!(SYSCON->FROCTRL & SYSCON_FROCTRL_HSPDCLK_MASK) ? 0 : (SYSCON->FROCTRL & SYSCON_FROCTRL_SEL_MASK) ?
96000000U :
48000000U;
if ((SYSCON->PDRUNCFG[0] & SYSCON_PDRUNCFG_PDEN_FRO_MASK) || !(SYSCON->FROCTRL & SYSCON_FROCTRL_HSPDCLK_MASK))
{
return 0U;
}
if (SYSCON->FROCTRL & SYSCON_FROCTRL_SEL_MASK)
{
return 96000000U;
}
else
{
return 48000000U;
}
}
/*! brief Return Frequency of PLL
* return Frequency of PLL
*/
uint32_t CLOCK_GetPllOutFreq(void)
{
return s_Pll_Freq;
}
/*! brief Return Frequency of 32kHz osc
* return Frequency of 32kHz osc
*/
uint32_t CLOCK_GetOsc32KFreq(void)
{
return CLK_RTC_32K_CLK; /* Needs to be corrected to check that RTC Clock is enabled */
}
/*! brief Return Frequency of Core System
* return Frequency of Core System
*/
uint32_t CLOCK_GetCoreSysClkFreq(void)
{
return ((SYSCON->MAINCLKSELB == 0U) && (SYSCON->MAINCLKSELA == 0U)) ?
CLOCK_GetFro12MFreq() :
((SYSCON->MAINCLKSELB == 0U) && (SYSCON->MAINCLKSELA == 1U)) ?
CLOCK_GetExtClkFreq() :
((SYSCON->MAINCLKSELB == 0U) && (SYSCON->MAINCLKSELA == 2U)) ?
CLOCK_GetWdtOscFreq() :
((SYSCON->MAINCLKSELB == 0U) && (SYSCON->MAINCLKSELA == 3U)) ?
CLOCK_GetFroHfFreq() :
(SYSCON->MAINCLKSELB == 2U) ? CLOCK_GetPllOutFreq() :
(SYSCON->MAINCLKSELB == 3U) ? CLOCK_GetOsc32KFreq() : 0U;
uint32_t freq = 0U;
switch (SYSCON->MAINCLKSELB)
{
case 0U:
if (SYSCON->MAINCLKSELA == 0U)
{
freq = CLOCK_GetFro12MFreq();
}
else if (SYSCON->MAINCLKSELA == 1U)
{
freq = CLOCK_GetExtClkFreq();
}
else if (SYSCON->MAINCLKSELA == 2U)
{
freq = CLOCK_GetWdtOscFreq();
}
else if (SYSCON->MAINCLKSELA == 3U)
{
freq = CLOCK_GetFroHfFreq();
}
else
{
}
break;
case 2U:
freq = CLOCK_GetPllOutFreq();
break;
case 3U:
freq = CLOCK_GetOsc32KFreq();
break;
default:
break;
}
return freq;
}
/*! brief Return Frequency of I2S MCLK Clock
* return Frequency of I2S MCLK Clock
*/
uint32_t CLOCK_GetI2SMClkFreq(void)
{
return g_I2S_Mclk_Freq;
return s_I2S_Mclk_Freq;
}
/*! brief Return Frequency of Asynchronous APB Clock
* return Frequency of Asynchronous APB Clock Clock
*/
uint32_t CLOCK_GetAsyncApbClkFreq(void)
{
async_clock_src_t clkSrc;
@ -305,26 +424,109 @@ uint32_t CLOCK_GetAsyncApbClkFreq(void)
return clkRate;
}
/* Get FLEXCOMM Clk */
/*! brief Return Frequency of Flexcomm functional Clock
* return Frequency of Flexcomm functional Clock
*/
uint32_t CLOCK_GetFlexCommClkFreq(uint32_t id)
{
return (SYSCON->FXCOMCLKSEL[id] == 0U) ? CLOCK_GetFro12MFreq() : (SYSCON->FXCOMCLKSEL[id] == 1U) ?
CLOCK_GetFroHfFreq() :
(SYSCON->FXCOMCLKSEL[id] == 2U) ?
CLOCK_GetPllOutFreq() :
(SYSCON->FXCOMCLKSEL[id] == 3U) ?
CLOCK_GetI2SMClkFreq() :
(SYSCON->FXCOMCLKSEL[id] == 4U) ? CLOCK_GetFreq(kCLOCK_Frg) : 0U;
uint32_t freq = 0U;
switch (SYSCON->FXCOMCLKSEL[id])
{
case 0U:
freq = CLOCK_GetFro12MFreq();
break;
case 1U:
freq = CLOCK_GetFroHfFreq();
break;
case 2U:
freq = CLOCK_GetPllOutFreq();
break;
case 3U:
freq = CLOCK_GetI2SMClkFreq();
break;
case 4U:
freq = CLOCK_GetFrgClkFreq();
break;
default:
break;
}
return freq;
}
/* Get FRG Clk */
/*! brief Return Input frequency for the Fractional baud rate generator
* return Input Frequency for FRG
*/
uint32_t CLOCK_GetFRGInputClock(void)
{
return (SYSCON->FRGCLKSEL == 0U) ? CLOCK_GetCoreSysClkFreq() : (SYSCON->FRGCLKSEL == 1U) ?
CLOCK_GetPllOutFreq() :
(SYSCON->FRGCLKSEL == 2U) ? CLOCK_GetFro12MFreq() : (SYSCON->FRGCLKSEL == 3U) ?
CLOCK_GetFroHfFreq() :
0U;
uint32_t freq = 0U;
switch (SYSCON->FRGCLKSEL)
{
case 0U:
freq = CLOCK_GetCoreSysClkFreq();
break;
case 1U:
freq = CLOCK_GetPllOutFreq();
break;
case 2U:
freq = CLOCK_GetFro12MFreq();
break;
case 3U:
freq = CLOCK_GetFroHfFreq();
break;
default:
break;
}
return freq;
}
/* Get DMIC Clk */
/*! brief Return Input frequency for the DMIC
* return Input Frequency for DMIC
*/
uint32_t CLOCK_GetDmicClkFreq(void)
{
uint32_t freq = 0U;
switch (SYSCON->DMICCLKSEL)
{
case 0U:
freq = CLOCK_GetFro12MFreq();
break;
case 1U:
freq = CLOCK_GetFroHfFreq();
break;
case 2U:
freq = CLOCK_GetPllOutFreq();
break;
case 3U:
freq = CLOCK_GetI2SMClkFreq();
break;
case 4U:
freq = CLOCK_GetCoreSysClkFreq();
break;
case 5U:
freq = CLOCK_GetWdtOscFreq();
break;
default:
break;
}
return freq / ((SYSCON->DMICCLKDIV & 0xffU) + 1U);
;
}
/*! brief Set output of the Fractional baud rate generator
* param freq : Desired output frequency
* return Error Code 0 - fail 1 - success
*/
uint32_t CLOCK_SetFRGClock(uint32_t freq)
{
uint32_t input = CLOCK_GetFRGInputClock();
@ -343,6 +545,53 @@ uint32_t CLOCK_SetFRGClock(uint32_t freq)
}
}
/* Get FRG Clk */
/*! brief Return Input frequency for the FRG
* return Input Frequency for FRG
*/
uint32_t CLOCK_GetFrgClkFreq(void)
{
uint32_t freq = 0U;
if ((SYSCON->FRGCTRL & SYSCON_FRGCTRL_DIV_MASK) == SYSCON_FRGCTRL_DIV_MASK)
{
freq = ((uint64_t)CLOCK_GetFRGInputClock() * (SYSCON_FRGCTRL_DIV_MASK + 1)) /
((SYSCON_FRGCTRL_DIV_MASK + 1) +
((SYSCON->FRGCTRL & SYSCON_FRGCTRL_MULT_MASK) >> SYSCON_FRGCTRL_MULT_SHIFT));
}
else
{
freq = 0U;
}
return freq;
}
/*! brief Return Frequency of USB
* return Frequency of USB
*/
uint32_t CLOCK_GetUsbClkFreq(void)
{
uint32_t freq = 0U;
if (SYSCON->USBCLKSEL == 0U)
{
freq = CLOCK_GetFroHfFreq();
}
else if (SYSCON->USBCLKSEL == 1)
{
freq = CLOCK_GetPllOutFreq();
}
else
{
}
return freq / ((SYSCON->USBCLKDIV & 0xffU) + 1U);
}
/*! brief Return Frequency of selected clock
* return Frequency of selected clock
*/
uint32_t CLOCK_GetFreq(clock_name_t clockName)
{
uint32_t freq;
@ -364,31 +613,16 @@ uint32_t CLOCK_GetFreq(clock_name_t clockName)
freq = CLOCK_GetPllOutFreq();
break;
case kCLOCK_UsbClk:
freq = (SYSCON->USBCLKSEL == 0U) ? CLOCK_GetFroHfFreq() : (SYSCON->USBCLKSEL == 1) ? CLOCK_GetPllOutFreq() :
0U;
freq = freq / ((SYSCON->USBCLKDIV & 0xffU) + 1U);
freq = CLOCK_GetUsbClkFreq();
break;
case kClock_WdtOsc:
case kCLOCK_WdtOsc:
freq = CLOCK_GetWdtOscFreq();
break;
case kCLOCK_Frg:
freq = ((SYSCON->FRGCTRL & SYSCON_FRGCTRL_DIV_MASK) == SYSCON_FRGCTRL_DIV_MASK) ?
((uint64_t)CLOCK_GetFRGInputClock() * (SYSCON_FRGCTRL_DIV_MASK + 1)) /
((SYSCON_FRGCTRL_DIV_MASK + 1) +
((SYSCON->FRGCTRL & SYSCON_FRGCTRL_MULT_MASK) >> SYSCON_FRGCTRL_MULT_SHIFT)) :
0;
freq = CLOCK_GetFrgClkFreq();
break;
case kCLOCK_Dmic:
freq = (SYSCON->DMICCLKSEL == 0U) ? CLOCK_GetFro12MFreq() : (SYSCON->DMICCLKSEL == 1U) ?
CLOCK_GetFroHfFreq() :
(SYSCON->DMICCLKSEL == 2U) ?
CLOCK_GetPllOutFreq() :
(SYSCON->DMICCLKSEL == 3U) ?
CLOCK_GetI2SMClkFreq() :
(SYSCON->DMICCLKSEL == 4U) ?
CLOCK_GetCoreSysClkFreq() :
(SYSCON->DMICCLKSEL == 5U) ? CLOCK_GetWdtOscFreq() : 0U;
freq = freq / ((SYSCON->DMICCLKDIV & 0xffU) + 1U);
freq = CLOCK_GetDmicClkFreq();
break;
case kCLOCK_AsyncApbClk:
@ -432,6 +666,11 @@ uint32_t CLOCK_GetFreq(clock_name_t clockName)
}
/* Set the FLASH wait states for the passed frequency */
/**
* brief Set the flash wait states for the input freuqency.
* param iFreq : Input frequency
* return Nothing
*/
void CLOCK_SetFLASHAccessCyclesForFreq(uint32_t iFreq)
{
if (iFreq <= 12000000U)
@ -789,8 +1028,13 @@ static uint32_t FindGreatestCommonDivisor(uint32_t m, uint32_t n)
return m;
}
/* Set PLL output based on desired output rate */
static pll_error_t CLOCK_GetPllConfig(
/*
* Set PLL output based on desired output rate.
* In this function, the it calculates the PLL setting for output frequency from input clock
* frequency. The calculation would cost a few time. So it is not recommaned to use it frequently.
* the "pllctrl", "pllndec", "pllpdec", "pllmdec" would updated in this function.
*/
static pll_error_t CLOCK_GetPllConfigInternal(
uint32_t finHz, uint32_t foutHz, pll_setup_t *pSetup, bool useFeedbackDiv2, bool useSS)
{
uint32_t nDivOutHz, fccoHz, multFccoDiv;
@ -960,6 +1204,69 @@ static pll_error_t CLOCK_GetPllConfig(
return kStatus_PLL_Success;
}
#if (defined(CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT) && CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT)
/* Alloct the static buffer for cache. */
static pll_setup_t s_PllSetupCacheStruct[CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT];
static uint32_t s_FinHzCache[CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT] = {0};
static uint32_t s_FoutHzCache[CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT] = {0};
static bool s_UseFeedbackDiv2Cache[CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT] = {false};
static bool s_UseSSCache[CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT] = {false};
static uint32_t s_PllSetupCacheIdx = 0U;
#endif /* CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT */
/*
* Calculate the PLL setting values from input clock freq to output freq.
*/
static pll_error_t CLOCK_GetPllConfig(
uint32_t finHz, uint32_t foutHz, pll_setup_t *pSetup, bool useFeedbackDiv2, bool useSS)
{
pll_error_t retErr;
#if (defined(CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT) && CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT)
uint32_t i;
for (i = 0U; i < CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT; i++)
{
if ((finHz == s_FinHzCache[i]) && (foutHz == s_FoutHzCache[i]) &&
(useFeedbackDiv2 == s_UseFeedbackDiv2Cache[i]) && (useSS == s_UseSSCache[i]))
{
/* Hit the target in cache buffer. */
pSetup->syspllctrl = s_PllSetupCacheStruct[i].syspllctrl;
pSetup->syspllndec = s_PllSetupCacheStruct[i].syspllndec;
pSetup->syspllpdec = s_PllSetupCacheStruct[i].syspllpdec;
pSetup->syspllssctrl[0] = s_PllSetupCacheStruct[i].syspllssctrl[0];
pSetup->syspllssctrl[1] = s_PllSetupCacheStruct[i].syspllssctrl[1];
retErr = kStatus_PLL_Success;
break;
}
}
if (i < CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT)
{
return retErr;
}
#endif /* CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT */
retErr = CLOCK_GetPllConfigInternal(finHz, foutHz, pSetup, useFeedbackDiv2, useSS);
#if (defined(CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT) && CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT)
/* Cache the most recent calulation result into buffer. */
s_FinHzCache[s_PllSetupCacheIdx] = finHz;
s_FoutHzCache[s_PllSetupCacheIdx] = foutHz;
s_UseFeedbackDiv2Cache[s_PllSetupCacheIdx] = useFeedbackDiv2;
s_UseSSCache[s_PllSetupCacheIdx] = useSS;
s_PllSetupCacheStruct[s_PllSetupCacheIdx].syspllctrl = pSetup->syspllctrl;
s_PllSetupCacheStruct[s_PllSetupCacheIdx].syspllndec = pSetup->syspllndec;
s_PllSetupCacheStruct[s_PllSetupCacheIdx].syspllpdec = pSetup->syspllpdec;
s_PllSetupCacheStruct[s_PllSetupCacheIdx].syspllssctrl[0] = pSetup->syspllssctrl[0];
s_PllSetupCacheStruct[s_PllSetupCacheIdx].syspllssctrl[1] = pSetup->syspllssctrl[1];
/* Update the index for next available buffer. */
s_PllSetupCacheIdx = (s_PllSetupCacheIdx + 1U) % CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT;
#endif /* CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT */
return retErr;
}
/* Update local PLL rate variable */
static void CLOCK_GetSystemPLLOutFromSetupUpdate(pll_setup_t *pSetup)
{
@ -967,6 +1274,9 @@ static void CLOCK_GetSystemPLLOutFromSetupUpdate(pll_setup_t *pSetup)
}
/* Return System PLL input clock rate */
/*! brief Return System PLL input clock rate
* return System PLL input clock rate
*/
uint32_t CLOCK_GetSystemPLLInClockRate(void)
{
uint32_t clkRate = 0U;
@ -998,6 +1308,10 @@ uint32_t CLOCK_GetSystemPLLInClockRate(void)
}
/* Return System PLL output clock rate from setup structure */
/*! brief Return System PLL output clock rate from setup structure
* param pSetup : Pointer to a PLL setup structure
* return System PLL output clock rate calculated from the setup structure
*/
uint32_t CLOCK_GetSystemPLLOutFromSetup(pll_setup_t *pSetup)
{
uint32_t prediv, postdiv, mMult, inPllRate;
@ -1074,12 +1388,23 @@ uint32_t CLOCK_GetSystemPLLOutFromSetup(pll_setup_t *pSetup)
}
/* Set the current PLL Rate */
/*! brief Store the current PLL rate
* param rate: Current rate of the PLL
* return Nothing
**/
void CLOCK_SetStoredPLLClockRate(uint32_t rate)
{
s_Pll_Freq = rate;
}
/* Return System PLL output clock rate */
/*! brief Return System PLL output clock rate
* param recompute : Forces a PLL rate recomputation if true
* return System PLL output clock rate
* note The PLL rate is cached in the driver in a variable as
* the rate computation function can take some time to perform. It
* is recommended to use 'false' with the 'recompute' parameter.
*/
uint32_t CLOCK_GetSystemPLLOutClockRate(bool recompute)
{
pll_setup_t Setup;
@ -1102,6 +1427,13 @@ uint32_t CLOCK_GetSystemPLLOutClockRate(bool recompute)
}
/* Set PLL output based on the passed PLL setup data */
/*! brief Set PLL output based on the passed PLL setup data
* param pControl : Pointer to populated PLL control structure to generate setup with
* param pSetup : Pointer to PLL setup structure to be filled
* return PLL_ERROR_SUCCESS on success, or PLL setup error code
* note Actual frequency for setup may vary from the desired frequency based on the
* accuracy of input clocks, rounding, non-fractional PLL mode, etc.
*/
pll_error_t CLOCK_SetupPLLData(pll_config_t *pControl, pll_setup_t *pSetup)
{
uint32_t inRate;
@ -1145,6 +1477,16 @@ pll_error_t CLOCK_SetupPLLData(pll_config_t *pControl, pll_setup_t *pSetup)
}
/* Set PLL output from PLL setup structure */
/*! brief Set PLL output from PLL setup structure (precise frequency)
* param pSetup : Pointer to populated PLL setup structure
* param flagcfg : Flag configuration for PLL config structure
* return PLL_ERROR_SUCCESS on success, or PLL setup error code
* note This function will power off the PLL, setup the PLL with the
* new setup data, and then optionally powerup the PLL, wait for PLL lock,
* and adjust system voltages to the new PLL rate. The function will not
* alter any source clocks (ie, main systen clock) that may use the PLL,
* so these should be setup prior to and after exiting the function.
*/
pll_error_t CLOCK_SetupSystemPLLPrec(pll_setup_t *pSetup, uint32_t flagcfg)
{
/* Power off PLL during setup changes */
@ -1212,6 +1554,16 @@ pll_error_t CLOCK_SetupSystemPLLPrec(pll_setup_t *pSetup, uint32_t flagcfg)
}
/* Setup PLL Frequency from pre-calculated value */
/**
* brief Set PLL output from PLL setup structure (precise frequency)
* param pSetup : Pointer to populated PLL setup structure
* return kStatus_PLL_Success on success, or PLL setup error code
* note This function will power off the PLL, setup the PLL with the
* new setup data, and then optionally powerup the PLL, wait for PLL lock,
* and adjust system voltages to the new PLL rate. The function will not
* alter any source clocks (ie, main systen clock) that may use the PLL,
* so these should be setup prior to and after exiting the function.
*/
pll_error_t CLOCK_SetPLLFreq(const pll_setup_t *pSetup)
{
/* Power off PLL during setup changes */
@ -1271,6 +1623,17 @@ pll_error_t CLOCK_SetPLLFreq(const pll_setup_t *pSetup)
}
/* Set System PLL clock based on the input frequency and multiplier */
/*! brief Set PLL output based on the multiplier and input frequency
* param multiply_by : multiplier
* param input_freq : Clock input frequency of the PLL
* return Nothing
* note Unlike the Chip_Clock_SetupSystemPLLPrec() function, this
* function does not disable or enable PLL power, wait for PLL lock,
* or adjust system voltages. These must be done in the application.
* The function will not alter any source clocks (ie, main systen clock)
* that may use the PLL, so these should be setup prior to and after
* exiting the function.
*/
void CLOCK_SetupSystemPLLMult(uint32_t multiply_by, uint32_t input_freq)
{
uint32_t cco_freq = input_freq * multiply_by;

111
ext/hal/nxp/mcux/devices/LPC54114/fsl_clock.h
View file

@ -1,32 +1,10 @@
/*
* Copyright (c) 2016, Freescale Semiconductor, Inc.
* Copyright (c) 2016 - 2017 , NXP
* Copyright (c) 2016 - 2018 , NXP
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name ofcopyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _FSL_CLOCK_H_
@ -45,6 +23,24 @@
/*******************************************************************************
* Definitions
*****************************************************************************/
/*! @name Driver version */
/*@{*/
/*! @brief CLOCK driver version 2.0.5. */
#define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 0, 5))
/*@}*/
/*!
* @brief User-defined the size of cache for CLOCK_PllGetConfig() function.
*
* Once define this MACRO to be non-zero value, CLOCK_PllGetConfig() function
* would cache the recent calulation and accelerate the execution to get the
* right settings.
*/
#ifndef CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT
#define CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT 2U
#endif
/*! @brief Clock ip name array for FLEXCOMM. */
#define FLEXCOMM_CLOCKS \
{ \
@ -255,10 +251,10 @@ typedef enum _clock_name
kCLOCK_ExtClk, /*!< External Clock */
kCLOCK_PllOut, /*!< PLL Output */
kCLOCK_UsbClk, /*!< USB input */
kClock_WdtOsc, /*!< Watchdog Oscillator */
kCLOCK_WdtOsc, /*!< Watchdog Oscillator */
kCLOCK_Frg, /*!< Frg Clock */
kCLOCK_Dmic, /*!< Digital Mic clock */
kCLOCK_AsyncApbClk, /*!< Async APB clock */
kCLOCK_AsyncApbClk, /*!< Async APB clock */
kCLOCK_FlexI2S, /*!< FlexI2S clock */
kCLOCK_Flexcomm0, /*!< Flexcomm0Clock */
kCLOCK_Flexcomm1, /*!< Flexcomm1Clock */
@ -280,18 +276,22 @@ typedef enum _async_clock_src
} async_clock_src_t;
/*! @brief Clock Mux Switches
* The encoding is as follows each connection identified is 64bits wide
* The encoding is as follows each connection identified is 32bits wide while 24bits are valuable
* starting from LSB upwards
*
* [4 bits for choice, where 1 is A, 2 is B, 3 is C and 4 is D, 0 means end of descriptor] [8 bits mux ID]*
* [4 bits for choice, 0 means invalid choice] [8 bits mux ID]*
*
*/
#define MUX_A(m, choice) (((m) << 0) | ((choice + 1) << 8))
#define MUX_B(m, choice) (((m) << 12) | ((choice + 1) << 20))
#define MUX_C(m, choice) (((m) << 24) | ((choice + 1) << 32))
#define MUX_D(m, choice) (((m) << 36) | ((choice + 1) << 44))
#define MUX_E(m, choice) (((m) << 48) | ((choice + 1) << 56))
#define CLK_ATTACH_ID(mux, sel, pos) (((mux << 0U) | ((sel + 1) & 0xFU) << 8U) << (pos * 12U))
#define MUX_A(mux, sel) CLK_ATTACH_ID(mux, sel, 0U)
#define MUX_B(mux, sel, selector) (CLK_ATTACH_ID(mux, sel, 1U) | (selector << 24U))
#define GET_ID_ITEM(connection) ((connection)&0xFFFU)
#define GET_ID_NEXT_ITEM(connection) ((connection) >> 12U)
#define GET_ID_ITEM_MUX(connection) ((connection)&0xFFU)
#define GET_ID_ITEM_SEL(connection) ((((connection)&0xF00U) >> 8U) - 1U)
#define GET_ID_SELECTOR(connection) ((connection)&0xF000000U)
#define CM_MAINCLKSELA 0
#define CM_MAINCLKSELB 1
@ -327,12 +327,12 @@ typedef enum _async_clock_src
typedef enum _clock_attach_id
{
kFRO12M_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 0) | MUX_B(CM_MAINCLKSELB, 0),
kEXT_CLK_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 1) | MUX_B(CM_MAINCLKSELB, 0),
kWDT_OSC_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 2) | MUX_B(CM_MAINCLKSELB, 0),
kFRO_HF_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 3) | MUX_B(CM_MAINCLKSELB, 0),
kSYS_PLL_to_MAIN_CLK = MUX_A(CM_MAINCLKSELB, 2),
kOSC32K_to_MAIN_CLK = MUX_A(CM_MAINCLKSELB, 3),
kFRO12M_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 0) | MUX_B(CM_MAINCLKSELB, 0, 0),
kEXT_CLK_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 1) | MUX_B(CM_MAINCLKSELB, 0, 0),
kWDT_OSC_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 2) | MUX_B(CM_MAINCLKSELB, 0, 0),
kFRO_HF_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 3) | MUX_B(CM_MAINCLKSELB, 0, 0),
kSYS_PLL_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 0) | MUX_B(CM_MAINCLKSELB, 2, 0),
kOSC32K_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 0) | MUX_B(CM_MAINCLKSELB, 3, 0),
kFRO12M_to_SYS_PLL = MUX_A(CM_SYSPLLCLKSEL, 0),
kEXT_CLK_to_SYS_PLL = MUX_A(CM_SYSPLLCLKSEL, 1),
@ -417,6 +417,7 @@ typedef enum _clock_attach_id
kFRO_HF_to_MCLK = MUX_A(CM_FXI2S0MCLKCLKSEL, 0),
kSYS_PLL_to_MCLK = MUX_A(CM_FXI2S0MCLKCLKSEL, 1),
kMAIN_CLK_to_MCLK = MUX_A(CM_FXI2S0MCLKCLKSEL, 2),
kNONE_to_MCLK = MUX_A(CM_FXI2S0MCLKCLKSEL, 7),
kFRO12M_to_DMIC = MUX_A(CM_DMICCLKSEL, 0),
@ -440,7 +441,7 @@ typedef enum _clock_attach_id
kFRO12M_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 5),
kOSC32K_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 6),
kNONE_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 7),
kNONE_to_NONE = 0x80000000U,
kNONE_to_NONE = (int)0x80000000U,
} clock_attach_id_t;
/* Clock dividers */
@ -535,6 +536,14 @@ status_t CLOCK_SetupFROClocking(uint32_t iFreq);
* @return Nothing
*/
void CLOCK_AttachClk(clock_attach_id_t connection);
/**
* @brief Get the actual clock attach id.
* This fuction uses the offset in input attach id, then it reads the actual source value in
* the register and combine the offset to obtain an actual attach id.
* @param attachId : Clock attach id to get.
* @return Clock source value.
*/
clock_attach_id_t CLOCK_GetClockAttachId(clock_attach_id_t attachId);
/**
* @brief Setup peripheral clock dividers.
* @param div_name : Clock divider name
@ -559,6 +568,16 @@ uint32_t CLOCK_GetFreq(clock_name_t clockName);
*/
uint32_t CLOCK_GetFRGInputClock(void);
/*! @brief Return Input frequency for the DMIC
* @return Input Frequency for DMIC
*/
uint32_t CLOCK_GetDmicClkFreq(void);
/*! @brief Return Input frequency for the FRG
* @return Input Frequency for FRG
*/
uint32_t CLOCK_GetFrgClkFreq(void);
/*! @brief Set output of the Fractional baud rate generator
* @param freq : Desired output frequency
* @return Error Code 0 - fail 1 - success
@ -581,6 +600,10 @@ uint32_t CLOCK_GetWdtOscFreq(void);
* @return Frequency of High-Freq output of FRO
*/
uint32_t CLOCK_GetFroHfFreq(void);
/*! @brief Return Frequency of USB
* @return Frequency of USB
*/
uint32_t CLOCK_GetUsbClkFreq(void);
/*! @brief Return Frequency of PLL
* @return Frequency of PLL
*/
@ -674,10 +697,12 @@ void CLOCK_SetStoredPLLClockRate(uint32_t rate);
#define PLL_CONFIGFLAG_FORCENOFRACT \
(1 << 2) /*!< Force non-fractional output mode, PLL output will not use the fractional, automatic bandwidth, or SS \
\ \ \
\ \ \ \ \
\ \ \ \ \ \ \
\ \ \ \ \
\ \ \ \ \ \ \
\ \ \ \ \ \ \ \ \
hardware */
\ \ \ \ \ \ \ \ \ \ \
\ \ \ \ \ \ \ \ \ \ \ \ \
hardware */
/*! @brief PLL Spread Spectrum (SS) Programmable modulation frequency
* See (MF) field in the SYSPLLSSCTRL1 register in the UM.

28
ext/hal/nxp/mcux/devices/LPC54114/fsl_device_registers.h
View file

@ -1,30 +1,8 @@
/*
* Copyright (c) 2014 - 2016, Freescale Semiconductor, Inc.
* Copyright 2016 - 2017 NXP
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* Copyright 2014-2016 Freescale Semiconductor, Inc.
* Copyright 2016-2018 NXP
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* SPDX-License-Identifier: BSD-3-Clause
*
*/

39
ext/hal/nxp/mcux/devices/LPC54114/system_LPC54114_cm0plus.c
View file

@ -10,39 +10,17 @@
**
** Reference manual: LPC5411x User manual Rev. 1.1 25 May 2016
** Version: rev. 1.0, 2016-04-29
** Build: b161227
** Build: b180802
**
** Abstract:
** Provides a system configuration function and a global variable that
** contains the system frequency. It configures the device and initializes
** the oscillator (PLL) that is part of the microcontroller device.
**
** Copyright (c) 2016 Freescale Semiconductor, Inc.
** Copyright 2016 - 2017 NXP
** Redistribution and use in source and binary forms, with or without modification,
** are permitted provided that the following conditions are met:
** Copyright 2016 Freescale Semiconductor, Inc.
** Copyright 2016-2018 NXP
**
** o Redistributions of source code must retain the above copyright notice, this list
** of conditions and the following disclaimer.
**
** o Redistributions in binary form must reproduce the above copyright notice, this
** list of conditions and the following disclaimer in the documentation and/or
** other materials provided with the distribution.
**
** o Neither the name of the copyright holder nor the names of its
** contributors may be used to endorse or promote products derived from this
** software without specific prior written permission.
**
** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
** SPDX-License-Identifier: BSD-3-Clause
**
** http: www.nxp.com
** mail: support@nxp.com
@ -263,6 +241,7 @@ static uint32_t findPllMMult(uint32_t ctrlReg, uint32_t mDecReg)
void SystemInit(void)
{
SCB->VTOR = (uint32_t)&__Vectors;
SystemInitHook();
}
/* ----------------------------------------------------------------------------
@ -350,3 +329,11 @@ void SystemCoreClockUpdate(void)
}
SystemCoreClock = clkRate / ((SYSCON->AHBCLKDIV & 0xFF) + 1);
}
/* ----------------------------------------------------------------------------
-- SystemInitHook()
---------------------------------------------------------------------------- */
__attribute__ ((weak)) void SystemInitHook (void) {
/* Void implementation of the weak function. */
}

42
ext/hal/nxp/mcux/devices/LPC54114/system_LPC54114_cm0plus.h
View file

@ -10,39 +10,17 @@
**
** Reference manual: LPC5411x User manual Rev. 1.1 25 May 2016
** Version: rev. 1.0, 2016-04-29
** Build: b161227
** Build: b180802
**
** Abstract:
** Provides a system configuration function and a global variable that
** contains the system frequency. It configures the device and initializes
** the oscillator (PLL) that is part of the microcontroller device.
**
** Copyright (c) 2016 Freescale Semiconductor, Inc.
** Copyright 2016 - 2017 NXP
** Redistribution and use in source and binary forms, with or without modification,
** are permitted provided that the following conditions are met:
** Copyright 2016 Freescale Semiconductor, Inc.
** Copyright 2016-2018 NXP
**
** o Redistributions of source code must retain the above copyright notice, this list
** of conditions and the following disclaimer.
**
** o Redistributions in binary form must reproduce the above copyright notice, this
** list of conditions and the following disclaimer in the documentation and/or
** other materials provided with the distribution.
**
** o Neither the name of the copyright holder nor the names of its
** contributors may be used to endorse or promote products derived from this
** software without specific prior written permission.
**
** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
** SPDX-License-Identifier: BSD-3-Clause
**
** http: www.nxp.com
** mail: support@nxp.com
@ -112,6 +90,18 @@ void SystemInit (void);
*/
void SystemCoreClockUpdate (void);
/**
* @brief SystemInit function hook.
*
* This weak function allows to call specific initialization code during the
* SystemInit() execution.This can be used when an application specific code needs
* to be called as close to the reset entry as possible (for example the Multicore
* Manager MCMGR_EarlyInit() function call).
* NOTE: No global r/w variables can be used in this hook function because the
* initialization of these variables happens after this function.
*/
void SystemInitHook (void);
#ifdef __cplusplus
}
#endif

40
ext/hal/nxp/mcux/devices/LPC54114/system_LPC54114_cm4.c
View file

@ -10,39 +10,17 @@
**
** Reference manual: LPC5411x User manual Rev. 1.1 25 May 2016
** Version: rev. 1.0, 2016-04-29
** Build: b161227
** Build: b180802
**
** Abstract:
** Provides a system configuration function and a global variable that
** contains the system frequency. It configures the device and initializes
** the oscillator (PLL) that is part of the microcontroller device.
**
** Copyright (c) 2016 Freescale Semiconductor, Inc.
** Copyright 2016 - 2017 NXP
** Redistribution and use in source and binary forms, with or without modification,
** are permitted provided that the following conditions are met:
** Copyright 2016 Freescale Semiconductor, Inc.
** Copyright 2016-2018 NXP
**
** o Redistributions of source code must retain the above copyright notice, this list
** of conditions and the following disclaimer.
**
** o Redistributions in binary form must reproduce the above copyright notice, this
** list of conditions and the following disclaimer in the documentation and/or
** other materials provided with the distribution.
**
** o Neither the name of the copyright holder nor the names of its
** contributors may be used to endorse or promote products derived from this
** software without specific prior written permission.
**
** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
** SPDX-License-Identifier: BSD-3-Clause
**
** http: www.nxp.com
** mail: support@nxp.com
@ -270,6 +248,8 @@ void SystemInit(void)
#if !defined(DONT_ENABLE_DISABLED_RAMBANKS)
SYSCON->AHBCLKCTRLSET[0] = SYSCON_AHBCLKCTRL_SRAM2_MASK;
#endif
SystemInitHook();
}
/* ----------------------------------------------------------------------------
@ -357,3 +337,11 @@ void SystemCoreClockUpdate(void)
}
SystemCoreClock = clkRate / ((SYSCON->AHBCLKDIV & 0xFF) + 1);
}
/* ----------------------------------------------------------------------------
-- SystemInitHook()
---------------------------------------------------------------------------- */
__attribute__ ((weak)) void SystemInitHook (void) {
/* Void implementation of the weak function. */
}

42
ext/hal/nxp/mcux/devices/LPC54114/system_LPC54114_cm4.h
View file

@ -10,39 +10,17 @@
**
** Reference manual: LPC5411x User manual Rev. 1.1 25 May 2016
** Version: rev. 1.0, 2016-04-29
** Build: b161227
** Build: b180802
**
** Abstract:
** Provides a system configuration function and a global variable that
** contains the system frequency. It configures the device and initializes
** the oscillator (PLL) that is part of the microcontroller device.
**
** Copyright (c) 2016 Freescale Semiconductor, Inc.
** Copyright 2016 - 2017 NXP
** Redistribution and use in source and binary forms, with or without modification,
** are permitted provided that the following conditions are met:
** Copyright 2016 Freescale Semiconductor, Inc.
** Copyright 2016-2018 NXP
**
** o Redistributions of source code must retain the above copyright notice, this list
** of conditions and the following disclaimer.
**
** o Redistributions in binary form must reproduce the above copyright notice, this
** list of conditions and the following disclaimer in the documentation and/or
** other materials provided with the distribution.
**
** o Neither the name of the copyright holder nor the names of its
** contributors may be used to endorse or promote products derived from this
** software without specific prior written permission.
**
** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
** SPDX-License-Identifier: BSD-3-Clause
**
** http: www.nxp.com
** mail: support@nxp.com
@ -112,6 +90,18 @@ void SystemInit (void);
*/
void SystemCoreClockUpdate (void);
/**
* @brief SystemInit function hook.
*
* This weak function allows to call specific initialization code during the
* SystemInit() execution.This can be used when an application specific code needs
* to be called as close to the reset entry as possible (for example the Multicore
* Manager MCMGR_EarlyInit() function call).
* NOTE: No global r/w variables can be used in this hook function because the
* initialization of these variables happens after this function.
*/
void SystemInitHook (void);
#ifdef __cplusplus
}
#endif

14829
ext/hal/nxp/mcux/devices/MIMXRT1051/MIMXRT1051.h
View file

File diff suppressed because it is too large Load diff

6686
ext/hal/nxp/mcux/devices/MIMXRT1051/MIMXRT1051.xml
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File diff suppressed because it is too large Load diff

544
ext/hal/nxp/mcux/devices/MIMXRT1051/MIMXRT1051_features.h
View file

@ -1,37 +1,16 @@
/*
** ###################################################################
** Version: rev. 0.1, 2017-01-10
** Build: b171017
** Version: rev. 1.1, 2018-11-16
** Build: b181120
**
** Abstract:
** Chip specific module features.
**
** Copyright 2016 Freescale Semiconductor, Inc.
** Copyright 2016-2017 NXP
** Redistribution and use in source and binary forms, with or without modification,
** are permitted provided that the following conditions are met:
** Copyright 2016-2018 NXP
** All rights reserved.
**
** 1. Redistributions of source code must retain the above copyright notice, this list
** of conditions and the following disclaimer.
**
** 2. Redistributions in binary form must reproduce the above copyright notice, this
** list of conditions and the following disclaimer in the documentation and/or
** other materials provided with the distribution.
**
** 3. Neither the name of the copyright holder nor the names of its
** contributors may be used to endorse or promote products derived from this
** software without specific prior written permission.
**
** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
** SPDX-License-Identifier: BSD-3-Clause
**
** http: www.nxp.com
** mail: support@nxp.com
@ -39,6 +18,12 @@
** Revisions:
** - rev. 0.1 (2017-01-10)
** Initial version.
** - rev. 1.0 (2018-09-21)
** Update interrupt vector table and dma request source.
** Update register BEE_ADDR_OFFSET1's bitfield name to ADDR_OFFSET1.
** Split GPIO_COMBINED_IRQS to GPIO_COMBINED_LOW_IRQS and GPIO_COMBINED_HIGH_IRQS.
** - rev. 1.1 (2018-11-16)
** Update feature files to align with IMXRT1050RM Rev.1.
**
** ###################################################################
*/
@ -48,532 +33,104 @@
/* SOC module features */
/* @brief ACMP availability on the SoC. */
#define FSL_FEATURE_SOC_ACMP_COUNT (0)
/* @brief ADC availability on the SoC. */
#define FSL_FEATURE_SOC_ADC_COUNT (2)
/* @brief ADC12 availability on the SoC. */
#define FSL_FEATURE_SOC_ADC12_COUNT (0)
/* @brief ADC16 availability on the SoC. */
#define FSL_FEATURE_SOC_ADC16_COUNT (0)
/* @brief ADC_5HC availability on the SoC. */
#define FSL_FEATURE_SOC_ADC_5HC_COUNT (0)
/* @brief AES availability on the SoC. */
#define FSL_FEATURE_SOC_AES_COUNT (0)
/* @brief AFE availability on the SoC. */
#define FSL_FEATURE_SOC_AFE_COUNT (0)
/* @brief AGC availability on the SoC. */
#define FSL_FEATURE_SOC_AGC_COUNT (0)
/* @brief AIPS availability on the SoC. */
#define FSL_FEATURE_SOC_AIPS_COUNT (0)
/* @brief AIPSTZ availability on the SoC. */
#define FSL_FEATURE_SOC_AIPSTZ_COUNT (4)
/* @brief ANATOP availability on the SoC. */
#define FSL_FEATURE_SOC_ANATOP_COUNT (0)
/* @brief AOI availability on the SoC. */
#define FSL_FEATURE_SOC_AOI_COUNT (2)
/* @brief APBH availability on the SoC. */
#define FSL_FEATURE_SOC_APBH_COUNT (0)
/* @brief ASMC availability on the SoC. */
#define FSL_FEATURE_SOC_ASMC_COUNT (0)
/* @brief ASRC availability on the SoC. */
#define FSL_FEATURE_SOC_ASRC_COUNT (0)
/* @brief ASYNC_SYSCON availability on the SoC. */
#define FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT (0)
/* @brief ATX availability on the SoC. */
#define FSL_FEATURE_SOC_ATX_COUNT (0)
/* @brief AXBS availability on the SoC. */
#define FSL_FEATURE_SOC_AXBS_COUNT (0)
/* @brief BCH availability on the SoC. */
#define FSL_FEATURE_SOC_BCH_COUNT (0)
/* @brief BLEDP availability on the SoC. */
#define FSL_FEATURE_SOC_BLEDP_COUNT (0)
/* @brief BOD availability on the SoC. */
#define FSL_FEATURE_SOC_BOD_COUNT (0)
/* @brief CAAM availability on the SoC. */
#define FSL_FEATURE_SOC_CAAM_COUNT (0)
/* @brief CADC availability on the SoC. */
#define FSL_FEATURE_SOC_CADC_COUNT (0)
/* @brief CALIB availability on the SoC. */
#define FSL_FEATURE_SOC_CALIB_COUNT (0)
/* @brief CAN availability on the SoC. */
#define FSL_FEATURE_SOC_CAN_COUNT (0)
/* @brief CAU availability on the SoC. */
#define FSL_FEATURE_SOC_CAU_COUNT (0)
/* @brief CAU3 availability on the SoC. */
#define FSL_FEATURE_SOC_CAU3_COUNT (0)
/* @brief CCM availability on the SoC. */
#define FSL_FEATURE_SOC_CCM_COUNT (1)
/* @brief CCM_ANALOG availability on the SoC. */
#define FSL_FEATURE_SOC_CCM_ANALOG_COUNT (1)
/* @brief CHRG availability on the SoC. */
#define FSL_FEATURE_SOC_CHRG_COUNT (0)
/* @brief CLKCTL0 availability on the SoC. */
#define FSL_FEATURE_SOC_CLKCTL0_COUNT (0)
/* @brief CLKCTL1 availability on the SoC. */
#define FSL_FEATURE_SOC_CLKCTL1_COUNT (0)
/* @brief CMP availability on the SoC. */
#define FSL_FEATURE_SOC_CMP_COUNT (4)
/* @brief CMT availability on the SoC. */
#define FSL_FEATURE_SOC_CMT_COUNT (0)
/* @brief CNC availability on the SoC. */
#define FSL_FEATURE_SOC_CNC_COUNT (0)
/* @brief COP availability on the SoC. */
#define FSL_FEATURE_SOC_COP_COUNT (0)
/* @brief CRC availability on the SoC. */
#define FSL_FEATURE_SOC_CRC_COUNT (0)
/* @brief CS availability on the SoC. */
#define FSL_FEATURE_SOC_CS_COUNT (0)
/* @brief CSI availability on the SoC. */
#define FSL_FEATURE_SOC_CSI_COUNT (0)
/* @brief CT32B availability on the SoC. */
#define FSL_FEATURE_SOC_CT32B_COUNT (0)
/* @brief CTI availability on the SoC. */
#define FSL_FEATURE_SOC_CTI_COUNT (0)
/* @brief CTIMER availability on the SoC. */
#define FSL_FEATURE_SOC_CTIMER_COUNT (0)
/* @brief DAC availability on the SoC. */
#define FSL_FEATURE_SOC_DAC_COUNT (0)
/* @brief DAC32 availability on the SoC. */
#define FSL_FEATURE_SOC_DAC32_COUNT (0)
/* @brief DCDC availability on the SoC. */
#define FSL_FEATURE_SOC_DCDC_COUNT (1)
/* @brief DCP availability on the SoC. */
#define FSL_FEATURE_SOC_DCP_COUNT (1)
/* @brief DDR availability on the SoC. */
#define FSL_FEATURE_SOC_DDR_COUNT (0)
/* @brief DDRC availability on the SoC. */
#define FSL_FEATURE_SOC_DDRC_COUNT (0)
/* @brief DDRC_MP availability on the SoC. */
#define FSL_FEATURE_SOC_DDRC_MP_COUNT (0)
/* @brief DDR_PHY availability on the SoC. */
#define FSL_FEATURE_SOC_DDR_PHY_COUNT (0)
/* @brief DMA availability on the SoC. */
#define FSL_FEATURE_SOC_DMA_COUNT (0)
/* @brief DMAMUX availability on the SoC. */
#define FSL_FEATURE_SOC_DMAMUX_COUNT (1)
/* @brief DMIC availability on the SoC. */
#define FSL_FEATURE_SOC_DMIC_COUNT (0)
/* @brief DRY availability on the SoC. */
#define FSL_FEATURE_SOC_DRY_COUNT (0)
/* @brief DSPI availability on the SoC. */
#define FSL_FEATURE_SOC_DSPI_COUNT (0)
/* @brief ECSPI availability on the SoC. */
#define FSL_FEATURE_SOC_ECSPI_COUNT (0)
/* @brief EDMA availability on the SoC. */
#define FSL_FEATURE_SOC_EDMA_COUNT (1)
/* @brief EEPROM availability on the SoC. */
#define FSL_FEATURE_SOC_EEPROM_COUNT (0)
/* @brief EIM availability on the SoC. */
#define FSL_FEATURE_SOC_EIM_COUNT (0)
/* @brief EMC availability on the SoC. */
#define FSL_FEATURE_SOC_EMC_COUNT (0)
/* @brief EMVSIM availability on the SoC. */
#define FSL_FEATURE_SOC_EMVSIM_COUNT (0)
/* @brief ENC availability on the SoC. */
#define FSL_FEATURE_SOC_ENC_COUNT (4)
/* @brief ENET availability on the SoC. */
#define FSL_FEATURE_SOC_ENET_COUNT (1)
/* @brief EPDC availability on the SoC. */
#define FSL_FEATURE_SOC_EPDC_COUNT (0)
/* @brief EPIT availability on the SoC. */
#define FSL_FEATURE_SOC_EPIT_COUNT (0)
/* @brief ESAI availability on the SoC. */
#define FSL_FEATURE_SOC_ESAI_COUNT (0)
/* @brief EWM availability on the SoC. */
#define FSL_FEATURE_SOC_EWM_COUNT (1)
/* @brief FB availability on the SoC. */
#define FSL_FEATURE_SOC_FB_COUNT (0)
/* @brief FGPIO availability on the SoC. */
#define FSL_FEATURE_SOC_FGPIO_COUNT (0)
/* @brief FLASH availability on the SoC. */
#define FSL_FEATURE_SOC_FLASH_COUNT (0)
/* @brief FLEXCAN availability on the SoC. */
#define FSL_FEATURE_SOC_FLEXCAN_COUNT (2)
/* @brief FLEXCOMM availability on the SoC. */
#define FSL_FEATURE_SOC_FLEXCOMM_COUNT (0)
/* @brief FLEXIO availability on the SoC. */
#define FSL_FEATURE_SOC_FLEXIO_COUNT (2)
/* @brief FLEXRAM availability on the SoC. */
#define FSL_FEATURE_SOC_FLEXRAM_COUNT (1)
/* @brief FLEXSPI availability on the SoC. */
#define FSL_FEATURE_SOC_FLEXSPI_COUNT (1)
/* @brief FMC availability on the SoC. */
#define FSL_FEATURE_SOC_FMC_COUNT (0)
/* @brief FREQME availability on the SoC. */
#define FSL_FEATURE_SOC_FREQME_COUNT (0)
/* @brief FSKDT availability on the SoC. */
#define FSL_FEATURE_SOC_FSKDT_COUNT (0)
/* @brief FSP availability on the SoC. */
#define FSL_FEATURE_SOC_FSP_COUNT (0)
/* @brief FTFA availability on the SoC. */
#define FSL_FEATURE_SOC_FTFA_COUNT (0)
/* @brief FTFE availability on the SoC. */
#define FSL_FEATURE_SOC_FTFE_COUNT (0)
/* @brief FTFL availability on the SoC. */
#define FSL_FEATURE_SOC_FTFL_COUNT (0)
/* @brief FTM availability on the SoC. */
#define FSL_FEATURE_SOC_FTM_COUNT (0)
/* @brief FTMRA availability on the SoC. */
#define FSL_FEATURE_SOC_FTMRA_COUNT (0)
/* @brief FTMRE availability on the SoC. */
#define FSL_FEATURE_SOC_FTMRE_COUNT (0)
/* @brief FTMRH availability on the SoC. */
#define FSL_FEATURE_SOC_FTMRH_COUNT (0)
/* @brief GINT availability on the SoC. */
#define FSL_FEATURE_SOC_GINT_COUNT (0)
/* @brief GPC availability on the SoC. */
#define FSL_FEATURE_SOC_GPC_COUNT (1)
/* @brief GPC_PGC availability on the SoC. */
#define FSL_FEATURE_SOC_GPC_PGC_COUNT (0)
/* @brief GPIO availability on the SoC. */
#define FSL_FEATURE_SOC_GPIO_COUNT (0)
/* @brief GPMI availability on the SoC. */
#define FSL_FEATURE_SOC_GPMI_COUNT (0)
/* @brief GPT availability on the SoC. */
#define FSL_FEATURE_SOC_GPT_COUNT (2)
/* @brief HASH availability on the SoC. */
#define FSL_FEATURE_SOC_HASH_COUNT (0)
/* @brief HSADC availability on the SoC. */
#define FSL_FEATURE_SOC_HSADC_COUNT (0)
/* @brief I2C availability on the SoC. */
#define FSL_FEATURE_SOC_I2C_COUNT (0)
/* @brief I2S availability on the SoC. */
#define FSL_FEATURE_SOC_I2S_COUNT (3)
/* @brief ICS availability on the SoC. */
#define FSL_FEATURE_SOC_ICS_COUNT (0)
/* @brief IEE availability on the SoC. */
#define FSL_FEATURE_SOC_IEE_COUNT (0)
/* @brief IEER availability on the SoC. */
#define FSL_FEATURE_SOC_IEER_COUNT (0)
/* @brief IGPIO availability on the SoC. */
#define FSL_FEATURE_SOC_IGPIO_COUNT (5)
/* @brief II2C availability on the SoC. */
#define FSL_FEATURE_SOC_II2C_COUNT (0)
/* @brief INPUTMUX availability on the SoC. */
#define FSL_FEATURE_SOC_INPUTMUX_COUNT (0)
/* @brief INTMUX availability on the SoC. */
#define FSL_FEATURE_SOC_INTMUX_COUNT (0)
/* @brief IOCON availability on the SoC. */
#define FSL_FEATURE_SOC_IOCON_COUNT (0)
/* @brief IOMUXC availability on the SoC. */
#define FSL_FEATURE_SOC_IOMUXC_COUNT (1)
/* @brief IOMUXC_GPR availability on the SoC. */
#define FSL_FEATURE_SOC_IOMUXC_GPR_COUNT (1)
/* @brief IOMUXC_LPSR availability on the SoC. */
#define FSL_FEATURE_SOC_IOMUXC_LPSR_COUNT (0)
/* @brief IOMUXC_LPSR_GPR availability on the SoC. */
#define FSL_FEATURE_SOC_IOMUXC_LPSR_GPR_COUNT (0)
/* @brief IOMUXC_SNVS availability on the SoC. */
#define FSL_FEATURE_SOC_IOMUXC_SNVS_COUNT (1)
/* @brief IOPCTL availability on the SoC. */
#define FSL_FEATURE_SOC_IOPCTL_COUNT (0)
/* @brief IPWM availability on the SoC. */
#define FSL_FEATURE_SOC_IPWM_COUNT (0)
/* @brief IRQ availability on the SoC. */
#define FSL_FEATURE_SOC_IRQ_COUNT (0)
/* @brief IUART availability on the SoC. */
#define FSL_FEATURE_SOC_IUART_COUNT (0)
/* @brief KBI availability on the SoC. */
#define FSL_FEATURE_SOC_KBI_COUNT (0)
/* @brief KPP availability on the SoC. */
#define FSL_FEATURE_SOC_KPP_COUNT (1)
/* @brief L2CACHEC availability on the SoC. */
#define FSL_FEATURE_SOC_L2CACHEC_COUNT (0)
/* @brief LCD availability on the SoC. */
#define FSL_FEATURE_SOC_LCD_COUNT (0)
/* @brief LCDC availability on the SoC. */
#define FSL_FEATURE_SOC_LCDC_COUNT (0)
/* @brief LCDIF availability on the SoC. */
#define FSL_FEATURE_SOC_LCDIF_COUNT (0)
/* @brief LDO availability on the SoC. */
#define FSL_FEATURE_SOC_LDO_COUNT (0)
/* @brief LLWU availability on the SoC. */
#define FSL_FEATURE_SOC_LLWU_COUNT (0)
/* @brief LMEM availability on the SoC. */
#define FSL_FEATURE_SOC_LMEM_COUNT (0)
/* @brief LPADC availability on the SoC. */
#define FSL_FEATURE_SOC_LPADC_COUNT (0)
/* @brief LPCMP availability on the SoC. */
#define FSL_FEATURE_SOC_LPCMP_COUNT (0)
/* @brief LPDAC availability on the SoC. */
#define FSL_FEATURE_SOC_LPDAC_COUNT (0)
/* @brief LPI2C availability on the SoC. */
#define FSL_FEATURE_SOC_LPI2C_COUNT (4)
/* @brief LPIT availability on the SoC. */
#define FSL_FEATURE_SOC_LPIT_COUNT (0)
/* @brief LPSCI availability on the SoC. */
#define FSL_FEATURE_SOC_LPSCI_COUNT (0)
/* @brief LPSPI availability on the SoC. */
#define FSL_FEATURE_SOC_LPSPI_COUNT (4)
/* @brief LPTMR availability on the SoC. */
#define FSL_FEATURE_SOC_LPTMR_COUNT (0)
/* @brief LPTPM availability on the SoC. */
#define FSL_FEATURE_SOC_LPTPM_COUNT (0)
/* @brief LPUART availability on the SoC. */
#define FSL_FEATURE_SOC_LPUART_COUNT (8)
/* @brief LTC availability on the SoC. */
#define FSL_FEATURE_SOC_LTC_COUNT (0)
/* @brief MAILBOX availability on the SoC. */
#define FSL_FEATURE_SOC_MAILBOX_COUNT (0)
/* @brief MC availability on the SoC. */
#define FSL_FEATURE_SOC_MC_COUNT (0)
/* @brief MCG availability on the SoC. */
#define FSL_FEATURE_SOC_MCG_COUNT (0)
/* @brief MCGLITE availability on the SoC. */
#define FSL_FEATURE_SOC_MCGLITE_COUNT (0)
/* @brief MCM availability on the SoC. */
#define FSL_FEATURE_SOC_MCM_COUNT (0)
/* @brief MIPI_CSI2 availability on the SoC. */
#define FSL_FEATURE_SOC_MIPI_CSI2_COUNT (0)
/* @brief MIPI_CSI2RX availability on the SoC. */
#define FSL_FEATURE_SOC_MIPI_CSI2RX_COUNT (0)
/* @brief MIPI_DSI availability on the SoC. */
#define FSL_FEATURE_SOC_MIPI_DSI_COUNT (0)
/* @brief MIPI_DSI_HOST availability on the SoC. */
#define FSL_FEATURE_SOC_MIPI_DSI_HOST_COUNT (0)
/* @brief MMAU availability on the SoC. */
#define FSL_FEATURE_SOC_MMAU_COUNT (0)
/* @brief MMCAU availability on the SoC. */
#define FSL_FEATURE_SOC_MMCAU_COUNT (0)
/* @brief MMDC availability on the SoC. */
#define FSL_FEATURE_SOC_MMDC_COUNT (0)
/* @brief MMDVSQ availability on the SoC. */
#define FSL_FEATURE_SOC_MMDVSQ_COUNT (0)
/* @brief MPU availability on the SoC. */
#define FSL_FEATURE_SOC_MPU_COUNT (0)
/* @brief MRT availability on the SoC. */
#define FSL_FEATURE_SOC_MRT_COUNT (0)
/* @brief MSCAN availability on the SoC. */
#define FSL_FEATURE_SOC_MSCAN_COUNT (0)
/* @brief MSCM availability on the SoC. */
#define FSL_FEATURE_SOC_MSCM_COUNT (0)
/* @brief MTB availability on the SoC. */
#define FSL_FEATURE_SOC_MTB_COUNT (0)
/* @brief MTBDWT availability on the SoC. */
#define FSL_FEATURE_SOC_MTBDWT_COUNT (0)
/* @brief MU availability on the SoC. */
#define FSL_FEATURE_SOC_MU_COUNT (0)
/* @brief NFC availability on the SoC. */
#define FSL_FEATURE_SOC_NFC_COUNT (0)
/* @brief OCOTP availability on the SoC. */
#define FSL_FEATURE_SOC_OCOTP_COUNT (1)
/* @brief OPAMP availability on the SoC. */
#define FSL_FEATURE_SOC_OPAMP_COUNT (0)
/* @brief OTPC availability on the SoC. */
#define FSL_FEATURE_SOC_OTPC_COUNT (0)
/* @brief OSC availability on the SoC. */
#define FSL_FEATURE_SOC_OSC_COUNT (0)
/* @brief OSC32 availability on the SoC. */
#define FSL_FEATURE_SOC_OSC32_COUNT (0)
/* @brief OTFAD availability on the SoC. */
#define FSL_FEATURE_SOC_OTFAD_COUNT (0)
/* @brief PCC availability on the SoC. */
#define FSL_FEATURE_SOC_PCC_COUNT (0)
/* @brief PCIE_PHY_CMN availability on the SoC. */
#define FSL_FEATURE_SOC_PCIE_PHY_CMN_COUNT (0)
/* @brief PCIE_PHY_TRSV availability on the SoC. */
#define FSL_FEATURE_SOC_PCIE_PHY_TRSV_COUNT (0)
/* @brief PDB availability on the SoC. */
#define FSL_FEATURE_SOC_PDB_COUNT (0)
/* @brief PGA availability on the SoC. */
#define FSL_FEATURE_SOC_PGA_COUNT (0)
/* @brief PIMCTL availability on the SoC. */
#define FSL_FEATURE_SOC_PIMCTL_COUNT (0)
/* @brief PINT availability on the SoC. */
#define FSL_FEATURE_SOC_PINT_COUNT (0)
/* @brief PIT availability on the SoC. */
#define FSL_FEATURE_SOC_PIT_COUNT (1)
/* @brief PMC availability on the SoC. */
#define FSL_FEATURE_SOC_PMC_COUNT (0)
/* @brief PMU availability on the SoC. */
#define FSL_FEATURE_SOC_PMU_COUNT (1)
/* @brief POWERQUAD availability on the SoC. */
#define FSL_FEATURE_SOC_POWERQUAD_COUNT (0)
/* @brief PORT availability on the SoC. */
#define FSL_FEATURE_SOC_PORT_COUNT (0)
/* @brief PROP availability on the SoC. */
#define FSL_FEATURE_SOC_PROP_COUNT (0)
/* @brief PWM availability on the SoC. */
#define FSL_FEATURE_SOC_PWM_COUNT (4)
/* @brief PWT availability on the SoC. */
#define FSL_FEATURE_SOC_PWT_COUNT (0)
/* @brief PXP availability on the SoC. */
#define FSL_FEATURE_SOC_PXP_COUNT (0)
/* @brief QDDKEY availability on the SoC. */
#define FSL_FEATURE_SOC_QDDKEY_COUNT (0)
/* @brief QDEC availability on the SoC. */
#define FSL_FEATURE_SOC_QDEC_COUNT (0)
/* @brief QuadSPI availability on the SoC. */
#define FSL_FEATURE_SOC_QuadSPI_COUNT (0)
/* @brief RCM availability on the SoC. */
#define FSL_FEATURE_SOC_RCM_COUNT (0)
/* @brief RDC availability on the SoC. */
#define FSL_FEATURE_SOC_RDC_COUNT (0)
/* @brief RDC_SEMAPHORE availability on the SoC. */
#define FSL_FEATURE_SOC_RDC_SEMAPHORE_COUNT (0)
/* @brief RFSYS availability on the SoC. */
#define FSL_FEATURE_SOC_RFSYS_COUNT (0)
/* @brief RFVBAT availability on the SoC. */
#define FSL_FEATURE_SOC_RFVBAT_COUNT (0)
/* @brief RIT availability on the SoC. */
#define FSL_FEATURE_SOC_RIT_COUNT (0)
/* @brief RNG availability on the SoC. */
#define FSL_FEATURE_SOC_RNG_COUNT (0)
/* @brief RNGB availability on the SoC. */
#define FSL_FEATURE_SOC_RNGB_COUNT (0)
/* @brief ROM availability on the SoC. */
#define FSL_FEATURE_SOC_ROM_COUNT (0)
/* @brief ROMC availability on the SoC. */
#define FSL_FEATURE_SOC_ROMC_COUNT (1)
/* @brief RSIM availability on the SoC. */
#define FSL_FEATURE_SOC_RSIM_COUNT (0)
/* @brief RSTCTL0 availability on the SoC. */
#define FSL_FEATURE_SOC_RSTCTL0_COUNT (0)
/* @brief RSTCTL1 availability on the SoC. */
#define FSL_FEATURE_SOC_RSTCTL1_COUNT (0)
/* @brief RTC availability on the SoC. */
#define FSL_FEATURE_SOC_RTC_COUNT (0)
/* @brief SCG availability on the SoC. */
#define FSL_FEATURE_SOC_SCG_COUNT (0)
/* @brief SCI availability on the SoC. */
#define FSL_FEATURE_SOC_SCI_COUNT (0)
/* @brief SCT availability on the SoC. */
#define FSL_FEATURE_SOC_SCT_COUNT (0)
/* @brief SDHC availability on the SoC. */
#define FSL_FEATURE_SOC_SDHC_COUNT (0)
/* @brief SDIF availability on the SoC. */
#define FSL_FEATURE_SOC_SDIF_COUNT (0)
/* @brief SDIO availability on the SoC. */
#define FSL_FEATURE_SOC_SDIO_COUNT (0)
/* @brief SDMA availability on the SoC. */
#define FSL_FEATURE_SOC_SDMA_COUNT (0)
/* @brief SDMAARM availability on the SoC. */
#define FSL_FEATURE_SOC_SDMAARM_COUNT (0)
/* @brief SDMABP availability on the SoC. */
#define FSL_FEATURE_SOC_SDMABP_COUNT (0)
/* @brief SDMACORE availability on the SoC. */
#define FSL_FEATURE_SOC_SDMACORE_COUNT (0)
/* @brief SDMCORE availability on the SoC. */
#define FSL_FEATURE_SOC_SDMCORE_COUNT (0)
/* @brief SDRAM availability on the SoC. */
#define FSL_FEATURE_SOC_SDRAM_COUNT (0)
/* @brief SEMA4 availability on the SoC. */
#define FSL_FEATURE_SOC_SEMA4_COUNT (0)
/* @brief SEMA42 availability on the SoC. */
#define FSL_FEATURE_SOC_SEMA42_COUNT (0)
/* @brief SEMC availability on the SoC. */
#define FSL_FEATURE_SOC_SEMC_COUNT (1)
/* @brief SHA availability on the SoC. */
#define FSL_FEATURE_SOC_SHA_COUNT (0)
/* @brief SIM availability on the SoC. */
#define FSL_FEATURE_SOC_SIM_COUNT (0)
/* @brief SJC availability on the SoC. */
#define FSL_FEATURE_SOC_SJC_COUNT (0)
/* @brief SLCD availability on the SoC. */
#define FSL_FEATURE_SOC_SLCD_COUNT (0)
/* @brief SMARTCARD availability on the SoC. */
#define FSL_FEATURE_SOC_SMARTCARD_COUNT (0)
/* @brief SMC availability on the SoC. */
#define FSL_FEATURE_SOC_SMC_COUNT (0)
/* @brief SNVS availability on the SoC. */
#define FSL_FEATURE_SOC_SNVS_COUNT (1)
/* @brief SPBA availability on the SoC. */
#define FSL_FEATURE_SOC_SPBA_COUNT (0)
/* @brief SPDIF availability on the SoC. */
#define FSL_FEATURE_SOC_SPDIF_COUNT (1)
/* @brief SPI availability on the SoC. */
#define FSL_FEATURE_SOC_SPI_COUNT (0)
/* @brief SPIFI availability on the SoC. */
#define FSL_FEATURE_SOC_SPIFI_COUNT (0)
/* @brief SPM availability on the SoC. */
#define FSL_FEATURE_SOC_SPM_COUNT (0)
/* @brief SRC availability on the SoC. */
#define FSL_FEATURE_SOC_SRC_COUNT (1)
/* @brief SYSCON availability on the SoC. */
#define FSL_FEATURE_SOC_SYSCON_COUNT (0)
/* @brief SYSCTL0 availability on the SoC. */
#define FSL_FEATURE_SOC_SYSCTL0_COUNT (0)
/* @brief SYSCTL1 availability on the SoC. */
#define FSL_FEATURE_SOC_SYSCTL1_COUNT (0)
/* @brief TEMPMON availability on the SoC. */
#define FSL_FEATURE_SOC_TEMPMON_COUNT (1)
/* @brief TMR availability on the SoC. */
#define FSL_FEATURE_SOC_TMR_COUNT (4)
/* @brief TPM availability on the SoC. */
#define FSL_FEATURE_SOC_TPM_COUNT (0)
/* @brief TRGMUX availability on the SoC. */
#define FSL_FEATURE_SOC_TRGMUX_COUNT (0)
/* @brief TRIAMP availability on the SoC. */
#define FSL_FEATURE_SOC_TRIAMP_COUNT (0)
/* @brief TRNG availability on the SoC. */
#define FSL_FEATURE_SOC_TRNG_COUNT (1)
/* @brief TSC availability on the SoC. */
#define FSL_FEATURE_SOC_TSC_COUNT (1)
/* @brief TSI availability on the SoC. */
#define FSL_FEATURE_SOC_TSI_COUNT (0)
/* @brief TSTMR availability on the SoC. */
#define FSL_FEATURE_SOC_TSTMR_COUNT (0)
/* @brief UART availability on the SoC. */
#define FSL_FEATURE_SOC_UART_COUNT (0)
/* @brief USART availability on the SoC. */
#define FSL_FEATURE_SOC_USART_COUNT (0)
/* @brief USB availability on the SoC. */
#define FSL_FEATURE_SOC_USB_COUNT (0)
/* @brief USBHS availability on the SoC. */
#define FSL_FEATURE_SOC_USBHS_COUNT (2)
/* @brief USBDCD availability on the SoC. */
#define FSL_FEATURE_SOC_USBDCD_COUNT (0)
/* @brief USBFSH availability on the SoC. */
#define FSL_FEATURE_SOC_USBFSH_COUNT (0)
/* @brief USBHSD availability on the SoC. */
#define FSL_FEATURE_SOC_USBHSD_COUNT (0)
/* @brief USBHSDCD availability on the SoC. */
#define FSL_FEATURE_SOC_USBHSDCD_COUNT (0)
/* @brief USBHSH availability on the SoC. */
#define FSL_FEATURE_SOC_USBHSH_COUNT (0)
/* @brief USBNC availability on the SoC. */
#define FSL_FEATURE_SOC_USBNC_COUNT (2)
/* @brief USBPHY availability on the SoC. */
#define FSL_FEATURE_SOC_USBPHY_COUNT (2)
/* @brief USB_HSIC availability on the SoC. */
#define FSL_FEATURE_SOC_USB_HSIC_COUNT (0)
/* @brief USB_OTG availability on the SoC. */
#define FSL_FEATURE_SOC_USB_OTG_COUNT (0)
/* @brief USBVREG availability on the SoC. */
#define FSL_FEATURE_SOC_USBVREG_COUNT (0)
/* @brief USDHC availability on the SoC. */
#define FSL_FEATURE_SOC_USDHC_COUNT (2)
/* @brief UTICK availability on the SoC. */
#define FSL_FEATURE_SOC_UTICK_COUNT (0)
/* @brief VIU availability on the SoC. */
#define FSL_FEATURE_SOC_VIU_COUNT (0)
/* @brief VREF availability on the SoC. */
#define FSL_FEATURE_SOC_VREF_COUNT (0)
/* @brief VFIFO availability on the SoC. */
#define FSL_FEATURE_SOC_VFIFO_COUNT (0)
/* @brief WDOG availability on the SoC. */
#define FSL_FEATURE_SOC_WDOG_COUNT (2)
/* @brief WKPU availability on the SoC. */
#define FSL_FEATURE_SOC_WKPU_COUNT (0)
/* @brief WWDT availability on the SoC. */
#define FSL_FEATURE_SOC_WWDT_COUNT (0)
/* @brief XBAR availability on the SoC. */
#define FSL_FEATURE_SOC_XBAR_COUNT (0)
/* @brief XBARA availability on the SoC. */
#define FSL_FEATURE_SOC_XBARA_COUNT (1)
/* @brief XBARB availability on the SoC. */
#define FSL_FEATURE_SOC_XBARB_COUNT (2)
/* @brief XCVR availability on the SoC. */
#define FSL_FEATURE_SOC_XCVR_COUNT (0)
/* @brief XRDC availability on the SoC. */
#define FSL_FEATURE_SOC_XRDC_COUNT (0)
/* @brief XTALOSC availability on the SoC. */
#define FSL_FEATURE_SOC_XTALOSC_COUNT (0)
/* @brief XTALOSC24M availability on the SoC. */
#define FSL_FEATURE_SOC_XTALOSC24M_COUNT (1)
/* @brief ZLL availability on the SoC. */
#define FSL_FEATURE_SOC_ZLL_COUNT (0)
/* ADC module features */
@ -582,6 +139,11 @@
/* @brief Remove ALT Clock selection feature. */
#define FSL_FEATURE_ADC_SUPPORT_ALTCLK_REMOVE (1)
/* ADC_ETC module features */
/* @brief Has DMA model control(bit field CTRL[DMA_MODE_SEL]). */
#define FSL_FEATURE_ADC_ETC_HAS_CTRL_DMA_MODE_SEL (1)
/* AOI module features */
/* @brief Maximum value of input mux. */
@ -595,20 +157,34 @@
#define FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(x) (64)
/* @brief Has doze mode support (register bit field MCR[DOZE]). */
#define FSL_FEATURE_FLEXCAN_HAS_DOZE_MODE_SUPPORT (0)
/* @brief Insatnce has doze mode support (register bit field MCR[DOZE]). */
#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_DOZE_MODE_SUPPORTn(x) (0)
/* @brief Has a glitch filter on the receive pin (register bit field MCR[WAKSRC]). */
#define FSL_FEATURE_FLEXCAN_HAS_GLITCH_FILTER (1)
/* @brief Has extended interrupt mask and flag register (register IMASK2, IFLAG2). */
#define FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER (1)
/* @brief Has extended bit timing register (register CBT). */
#define FSL_FEATURE_FLEXCAN_HAS_EXTENDED_TIMING_REGISTER (0)
/* @brief Instance has extended bit timing register (register CBT). */
#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_EXTENDED_TIMING_REGISTERn(x) (0)
/* @brief Has a receive FIFO DMA feature (register bit field MCR[DMA]). */
#define FSL_FEATURE_FLEXCAN_HAS_RX_FIFO_DMA (0)
/* @brief Instance has a receive FIFO DMA feature (register bit field MCR[DMA]). */
#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_RX_FIFO_DMAn(x) (0)
/* @brief Remove CAN Engine Clock Source Selection from unsupported part. */
#define FSL_FEATURE_FLEXCAN_SUPPORT_ENGINE_CLK_SEL_REMOVE (1)
/* @brief Instance remove CAN Engine Clock Source Selection from unsupported part. */
#define FSL_FEATURE_FLEXCAN_INSTANCE_SUPPORT_ENGINE_CLK_SEL_REMOVEn(x) (1)
/* @brief Is affected by errata with ID 5641 (Module does not transmit a message that is enabled to be transmitted at a specific moment during the arbitration process). */
#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641 (0)
/* @brief Is affected by errata with ID 5829 (FlexCAN: FlexCAN does not transmit a message that is enabled to be transmitted in a specific moment during the arbitration process). */
#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_5829 (1)
/* @brief Is affected by errata with ID 6032 (FlexCAN: A frame with wrong ID or payload is transmitted into the CAN bus when the Message Buffer under transmission is either aborted or deactivated while the CAN bus is in the Bus Idle state). */
#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_6032 (1)
/* @brief Is affected by errata with ID 9595 (FlexCAN: Corrupt frame possible if the Freeze Mode or the Low-Power Mode are entered during a Bus-Off state). */
#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_9595 (1)
/* @brief Has CAN with Flexible Data rate (CAN FD) protocol. */
#define FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE (0)
/* @brief CAN instance support Flexible Data rate (CAN FD) protocol. */
#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_FLEXIBLE_DATA_RATEn(x) (0)
/* @brief Has extra MB interrupt or common one. */
#define FSL_FEATURE_FLEXCAN_HAS_EXTRA_MB_INT (1)
@ -666,10 +242,40 @@
/* @brief Has Additional 1588 Timer Channel Interrupt. */
#define FSL_FEATURE_ENET_HAS_ADD_1588_TIMER_CHN_INT (0)
/* EWM module features */
/* @brief Has clock select (register CLKCTRL). */
#define FSL_FEATURE_EWM_HAS_CLOCK_SELECT (1)
/* @brief Has clock prescaler (register CLKPRESCALER). */
#define FSL_FEATURE_EWM_HAS_PRESCALER (1)
/* FLEXIO module features */
/* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */
#define FSL_FEATURE_FLEXIO_HAS_SHIFTER_STATUS (1)
/* @brief Has Pin Data Input Register (FLEXIO_PIN) */
#define FSL_FEATURE_FLEXIO_HAS_PIN_STATUS (1)
/* @brief Has Shifter Buffer N Nibble Byte Swapped Register (FLEXIO_SHIFTBUFNBSn) */
#define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_BYTE_SWAP (1)
/* @brief Has Shifter Buffer N Half Word Swapped Register (FLEXIO_SHIFTBUFHWSn) */
#define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_HALF_WORD_SWAP (1)
/* @brief Has Shifter Buffer N Nibble Swapped Register (FLEXIO_SHIFTBUFNISn) */
#define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_SWAP (1)
/* @brief Supports Shifter State Mode (FLEXIO_SHIFTCTLn[SMOD]) */
#define FSL_FEATURE_FLEXIO_HAS_STATE_MODE (1)
/* @brief Supports Shifter Logic Mode (FLEXIO_SHIFTCTLn[SMOD]) */
#define FSL_FEATURE_FLEXIO_HAS_LOGIC_MODE (1)
/* @brief Supports paralle width (FLEXIO_SHIFTCFGn[PWIDTH]) */
#define FSL_FEATURE_FLEXIO_HAS_PARALLEL_WIDTH (1)
/* @brief Reset value of the FLEXIO_VERID register */
#define FSL_FEATURE_FLEXIO_VERID_RESET_VALUE (0x1010001)
/* @brief Reset value of the FLEXIO_PARAM register */
#define FSL_FEATURE_FLEXIO_PARAM_RESET_VALUE (0x2200404)
/* FLEXRAM module features */
/* @brief Bank size */
#define FSL_FEATURE_FLEXRAM_INTERNAL_RAM_BANK_SIZE (32 * 1024)
#define FSL_FEATURE_FLEXRAM_INTERNAL_RAM_BANK_SIZE (32768)
/* @brief Total Bank numbers */
#define FSL_FEATURE_FLEXRAM_INTERNAL_RAM_TOTAL_BANK_NUMBERS (16)
@ -697,6 +303,15 @@
/* @brief Supports IRQ 0-31. */
#define FSL_FEATURE_GPC_HAS_IRQ_0_31 (1)
/* IGPIO module features */
/* @brief Has data register set DR_SET. */
#define FSL_FEATURE_IGPIO_HAS_DR_SET (1)
/* @brief Has data register clear DR_CLEAR. */
#define FSL_FEATURE_IGPIO_HAS_DR_CLEAR (1)
/* @brief Has data register toggle DR_TOGGLE. */
#define FSL_FEATURE_IGPIO_HAS_DR_TOGGLE (1)
/* LPI2C module features */
/* @brief Has separate DMA RX and TX requests. */
@ -787,7 +402,7 @@
/* @brief Lowest interrupt request number. */
#define FSL_FEATURE_INTERRUPT_IRQ_MIN (-14)
/* @brief Highest interrupt request number. */
#define FSL_FEATURE_INTERRUPT_IRQ_MAX (159)
#define FSL_FEATURE_INTERRUPT_IRQ_MAX (151)
/* OCOTP module features */
@ -865,8 +480,19 @@
#define FSL_FEATURE_SAI_INT_SOURCE_NUM (2)
/* @brief Has register of MCR. */
#define FSL_FEATURE_SAI_HAS_MCR (0)
/* @brief Has bit field MICS of the MCR register. */
#define FSL_FEATURE_SAI_HAS_NO_MCR_MICS (1)
/* @brief Has register of MDR */
#define FSL_FEATURE_SAI_HAS_MDR (0)
/* @brief Has support the BCLK bypass mode when BCLK = MCLK. */
#define FSL_FEATURE_SAI_HAS_BCLK_BYPASS (0)
/* SEMC module features */
/* @brief Has WDH time in NOR controller (register bit field NORCR2[WDH]). */
#define FSL_FEATURE_SEMC_HAS_NOR_WDH_TIME (1)
/* @brief Has WDS time in NOR controller (register bit field NORCR2[WDS]).) */
#define FSL_FEATURE_SEMC_HAS_NOR_WDS_TIME (1)
/* SNVS module features */
@ -892,7 +518,7 @@
/* @brief There is CORE0_RST bit in SCR register. */
#define FSL_FEATURE_SRC_HAS_SCR_CORE0_RST (1)
/* @brief There is LOCKUP_RST bit in SCR register. */
#define FSL_FEATURE_SRC_HAS_SCR_LOCKUP_RST (1)
#define FSL_FEATURE_SRC_HAS_SCR_LOCKUP_RST (0)
/* @brief There is SWRC bit in SCR register. */
#define FSL_FEATURE_SRC_HAS_SCR_SWRC (0)
/* @brief There is EIM_RST bit in SCR register. */

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@ -1,30 +1,9 @@
/*
* Copyright 2014-2016 Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* Copyright 2016-2018 NXP
* All rights reserved.
*
* 1. Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* SPDX-License-Identifier: BSD-3-Clause
*
*/
@ -36,7 +15,7 @@
*
* The CPU macro should be declared in the project or makefile.
*/
#if (defined(CPU_MIMXRT1051CVL5A) || defined(CPU_MIMXRT1051DVL6A))
#if (defined(CPU_MIMXRT1051CVJ5B) || defined(CPU_MIMXRT1051CVL5B) || defined(CPU_MIMXRT1051DVL6B))
#define MIMXRT1051_SERIES

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ext/hal/nxp/mcux/devices/MIMXRT1051/system_MIMXRT1051.c
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@ -1,17 +1,18 @@
/*
** ###################################################################
** Processors: MIMXRT1051CVL5A
** MIMXRT1051DVL6A
** Processors: MIMXRT1051CVJ5B
** MIMXRT1051CVL5B
** MIMXRT1051DVL6B
**
** Compilers: Keil ARM C/C++ Compiler
** Freescale C/C++ for Embedded ARM
** Compilers: Freescale C/C++ for Embedded ARM
** GNU C Compiler
** IAR ANSI C/C++ Compiler for ARM
** Keil ARM C/C++ Compiler
** MCUXpresso Compiler
**
** Reference manual: IMXRT1050RM Rev.C, 08/2017
** Version: rev. 0.1, 2017-01-10
** Build: b170927
** Reference manual: IMXRT1050RM Rev.2.1, 12/2018
** Version: rev. 1.2, 2018-11-27
** Build: b181205
**
** Abstract:
** Provides a system configuration function and a global variable that
@ -19,31 +20,10 @@
** the oscillator (PLL) that is part of the microcontroller device.
**
** Copyright 2016 Freescale Semiconductor, Inc.
** Copyright 2016-2017 NXP
** Redistribution and use in source and binary forms, with or without modification,
** are permitted provided that the following conditions are met:
** Copyright 2016-2018 NXP
** All rights reserved.
**
** 1. Redistributions of source code must retain the above copyright notice, this list
** of conditions and the following disclaimer.
**
** 2. Redistributions in binary form must reproduce the above copyright notice, this
** list of conditions and the following disclaimer in the documentation and/or
** other materials provided with the distribution.
**
** 3. Neither the name of the copyright holder nor the names of its
** contributors may be used to endorse or promote products derived from this
** software without specific prior written permission.
**
** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
** SPDX-License-Identifier: BSD-3-Clause
**
** http: www.nxp.com
** mail: support@nxp.com
@ -51,14 +31,22 @@
** Revisions:
** - rev. 0.1 (2017-01-10)
** Initial version.
** - rev. 1.0 (2018-09-21)
** Update interrupt vector table and dma request source.
** Update register BEE_ADDR_OFFSET1's bitfield name to ADDR_OFFSET1.
** Split GPIO_COMBINED_IRQS to GPIO_COMBINED_LOW_IRQS and GPIO_COMBINED_HIGH_IRQS.
** - rev. 1.1 (2018-11-16)
** Update header files to align with IMXRT1050RM Rev.1.
** - rev. 1.2 (2018-11-27)
** Update header files to align with IMXRT1050RM Rev.2.1.
**
** ###################################################################
*/
/*!
* @file MIMXRT1051
* @version 0.1
* @date 2017-01-10
* @version 1.2
* @date 2018-11-27
* @brief Device specific configuration file for MIMXRT1051 (implementation file)
*
* Provides a system configuration function and a global variable that contains
@ -86,6 +74,15 @@ void SystemInit (void) {
SCB->CPACR |= ((3UL << 10*2) | (3UL << 11*2)); /* set CP10, CP11 Full Access */
#endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */
#if defined(__MCUXPRESSO)
extern uint32_t g_pfnVectors[]; // Vector table defined in startup code
SCB->VTOR = (uint32_t)g_pfnVectors;
#endif
/* Disable Watchdog Power Down Counter */
WDOG1->WMCR &= ~WDOG_WMCR_PDE_MASK;
WDOG2->WMCR &= ~WDOG_WMCR_PDE_MASK;
/* Watchdog disable */
#if (DISABLE_WDOG)
@ -110,12 +107,17 @@ void SystemInit (void) {
/* Enable instruction and data caches */
#if defined(__ICACHE_PRESENT) && __ICACHE_PRESENT
SCB_EnableICache();
if (SCB_CCR_IC_Msk != (SCB_CCR_IC_Msk & SCB->CCR)) {
SCB_EnableICache();
}
#endif
#if defined(__DCACHE_PRESENT) && __DCACHE_PRESENT
SCB_EnableDCache();
if (SCB_CCR_DC_Msk != (SCB_CCR_DC_Msk & SCB->CCR)) {
SCB_EnableDCache();
}
#endif
SystemInitHook();
}
/* ----------------------------------------------------------------------------
@ -135,15 +137,26 @@ void SystemCoreClockUpdate (void) {
{
/* Pll3_sw_clk ---> Periph_clk2_clk ---> Periph_clk */
case CCM_CBCMR_PERIPH_CLK2_SEL(0U):
freq = (24000000UL * ((CCM_ANALOG->PLL_USB1 & CCM_ANALOG_PLL_USB1_DIV_SELECT_MASK) ? 22U : 20U));
if(CCM_ANALOG->PLL_USB1 & CCM_ANALOG_PLL_USB1_BYPASS_MASK)
{
freq = (((CCM_ANALOG->PLL_USB1 & CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_MASK) >> CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_SHIFT) == 0U) ?
CPU_XTAL_CLK_HZ : CPU_CLK1_HZ;
}
else
{
freq = (CPU_XTAL_CLK_HZ * ((CCM_ANALOG->PLL_USB1 & CCM_ANALOG_PLL_USB1_DIV_SELECT_MASK) ? 22U : 20U));
}
break;
/* Osc_clk ---> Periph_clk2_clk ---> Periph_clk */
case CCM_CBCMR_PERIPH_CLK2_SEL(1U):
freq = 24000000UL;
freq = CPU_XTAL_CLK_HZ;
break;
case CCM_CBCMR_PERIPH_CLK2_SEL(2U):
freq = (((CCM_ANALOG->PLL_SYS & CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_MASK) >> CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_SHIFT) == 0U) ?
CPU_XTAL_CLK_HZ : CPU_CLK1_HZ;
case CCM_CBCMR_PERIPH_CLK2_SEL(3U):
default:
freq = 0U;
@ -155,11 +168,29 @@ void SystemCoreClockUpdate (void) {
/* Pre_Periph_clk ---> Periph_clk */
else
{
PLL1MainClock = ((24000000UL * ((CCM_ANALOG->PLL_ARM & CCM_ANALOG_PLL_ARM_DIV_SELECT_MASK) >>
CCM_ANALOG_PLL_ARM_DIV_SELECT_SHIFT)) >> 1U);
/* check if pll is bypassed */
if(CCM_ANALOG->PLL_ARM & CCM_ANALOG_PLL_ARM_BYPASS_MASK)
{
PLL1MainClock = (((CCM_ANALOG->PLL_ARM & CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_MASK) >> CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_SHIFT) == 0U) ?
CPU_XTAL_CLK_HZ : CPU_CLK1_HZ;
}
else
{
PLL1MainClock = ((CPU_XTAL_CLK_HZ * ((CCM_ANALOG->PLL_ARM & CCM_ANALOG_PLL_ARM_DIV_SELECT_MASK) >>
CCM_ANALOG_PLL_ARM_DIV_SELECT_SHIFT)) >> 1U);
}
PLL2MainClock = (24000000UL * ((CCM_ANALOG->PLL_SYS & CCM_ANALOG_PLL_SYS_DIV_SELECT_MASK) ? 22U : 20U));
PLL2MainClock += ((uint64_t)24000000UL * ((uint64_t)(CCM_ANALOG->PLL_SYS_NUM))) / ((uint64_t)(CCM_ANALOG->PLL_SYS_DENOM));
/* check if pll is bypassed */
if(CCM_ANALOG->PLL_SYS & CCM_ANALOG_PLL_SYS_BYPASS_MASK)
{
PLL2MainClock = (((CCM_ANALOG->PLL_SYS & CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_MASK) >> CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_SHIFT) == 0U) ?
CPU_XTAL_CLK_HZ : CPU_CLK1_HZ;
}
else
{
PLL2MainClock = (CPU_XTAL_CLK_HZ * ((CCM_ANALOG->PLL_SYS & CCM_ANALOG_PLL_SYS_DIV_SELECT_MASK) ? 22U : 20U));
}
PLL2MainClock += ((uint64_t)CPU_XTAL_CLK_HZ * ((uint64_t)(CCM_ANALOG->PLL_SYS_NUM))) / ((uint64_t)(CCM_ANALOG->PLL_SYS_DENOM));
switch (CCM->CBCMR & CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK)
@ -193,3 +224,11 @@ void SystemCoreClockUpdate (void) {
SystemCoreClock = (freq / (((CCM->CBCDR & CCM_CBCDR_AHB_PODF_MASK) >> CCM_CBCDR_AHB_PODF_SHIFT) + 1U));
}
/* ----------------------------------------------------------------------------
-- SystemInitHook()
---------------------------------------------------------------------------- */
__attribute__ ((weak)) void SystemInitHook (void) {
/* Void implementation of the weak function. */
}

69
ext/hal/nxp/mcux/devices/MIMXRT1051/system_MIMXRT1051.h
View file

@ -1,17 +1,18 @@
/*
** ###################################################################
** Processors: MIMXRT1051CVL5A
** MIMXRT1051DVL6A
** Processors: MIMXRT1051CVJ5B
** MIMXRT1051CVL5B
** MIMXRT1051DVL6B
**
** Compilers: Keil ARM C/C++ Compiler
** Freescale C/C++ for Embedded ARM
** Compilers: Freescale C/C++ for Embedded ARM
** GNU C Compiler
** IAR ANSI C/C++ Compiler for ARM
** Keil ARM C/C++ Compiler
** MCUXpresso Compiler
**
** Reference manual: IMXRT1050RM Rev.C, 08/2017
** Version: rev. 0.1, 2017-01-10
** Build: b170927
** Reference manual: IMXRT1050RM Rev.2.1, 12/2018
** Version: rev. 1.2, 2018-11-27
** Build: b181205
**
** Abstract:
** Provides a system configuration function and a global variable that
@ -19,31 +20,10 @@
** the oscillator (PLL) that is part of the microcontroller device.
**
** Copyright 2016 Freescale Semiconductor, Inc.
** Copyright 2016-2017 NXP
** Redistribution and use in source and binary forms, with or without modification,
** are permitted provided that the following conditions are met:
** Copyright 2016-2018 NXP
** All rights reserved.
**
** 1. Redistributions of source code must retain the above copyright notice, this list
** of conditions and the following disclaimer.
**
** 2. Redistributions in binary form must reproduce the above copyright notice, this
** list of conditions and the following disclaimer in the documentation and/or
** other materials provided with the distribution.
**
** 3. Neither the name of the copyright holder nor the names of its
** contributors may be used to endorse or promote products derived from this
** software without specific prior written permission.
**
** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
** SPDX-License-Identifier: BSD-3-Clause
**
** http: www.nxp.com
** mail: support@nxp.com
@ -51,14 +31,22 @@
** Revisions:
** - rev. 0.1 (2017-01-10)
** Initial version.
** - rev. 1.0 (2018-09-21)
** Update interrupt vector table and dma request source.
** Update register BEE_ADDR_OFFSET1's bitfield name to ADDR_OFFSET1.
** Split GPIO_COMBINED_IRQS to GPIO_COMBINED_LOW_IRQS and GPIO_COMBINED_HIGH_IRQS.
** - rev. 1.1 (2018-11-16)
** Update header files to align with IMXRT1050RM Rev.1.
** - rev. 1.2 (2018-11-27)
** Update header files to align with IMXRT1050RM Rev.2.1.
**
** ###################################################################
*/
/*!
* @file MIMXRT1051
* @version 0.1
* @date 2017-01-10
* @version 1.2
* @date 2018-11-27
* @brief Device specific configuration file for MIMXRT1051 (header file)
*
* Provides a system configuration function and a global variable that contains
@ -84,6 +72,9 @@ extern "C" {
#define CPU_XTAL_CLK_HZ 24000000UL /* Value of the external crystal or oscillator clock frequency in Hz */
#define CPU_CLK1_HZ 0UL /* Value of the CLK1 (select the CLK1_N/CLK1_P as source) frequency in Hz */
/* If CLOCK1_P,CLOCK1_N is choose as the pll bypass clock source, please implement the CLKPN_FREQ define, otherwise 0 will be returned. */
#define DEFAULT_SYSTEM_CLOCK 528000000UL /* Default System clock value */
@ -116,6 +107,18 @@ void SystemInit (void);
*/
void SystemCoreClockUpdate (void);
/**
* @brief SystemInit function hook.
*
* This weak function allows to call specific initialization code during the
* SystemInit() execution.This can be used when an application specific code needs
* to be called as close to the reset entry as possible (for example the Multicore
* Manager MCMGR_EarlyInit() function call).
* NOTE: No global r/w variables can be used in this hook function because the
* initialization of these variables happens after this function.
*/
void SystemInitHook (void);
#ifdef __cplusplus
}
#endif

16081
ext/hal/nxp/mcux/devices/MIMXRT1052/MIMXRT1052.h
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6931
ext/hal/nxp/mcux/devices/MIMXRT1052/MIMXRT1052.xml
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File diff suppressed because it is too large Load diff

538
ext/hal/nxp/mcux/devices/MIMXRT1052/MIMXRT1052_features.h
View file

@ -1,37 +1,16 @@
/*
** ###################################################################
** Version: rev. 0.1, 2017-01-10
** Build: b171017
** Version: rev. 1.1, 2018-11-16
** Build: b181120
**
** Abstract:
** Chip specific module features.
**
** Copyright 2016 Freescale Semiconductor, Inc.
** Copyright 2016-2017 NXP
** Redistribution and use in source and binary forms, with or without modification,
** are permitted provided that the following conditions are met:
** Copyright 2016-2018 NXP
** All rights reserved.
**
** 1. Redistributions of source code must retain the above copyright notice, this list
** of conditions and the following disclaimer.
**
** 2. Redistributions in binary form must reproduce the above copyright notice, this
** list of conditions and the following disclaimer in the documentation and/or
** other materials provided with the distribution.
**
** 3. Neither the name of the copyright holder nor the names of its
** contributors may be used to endorse or promote products derived from this
** software without specific prior written permission.
**
** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
** SPDX-License-Identifier: BSD-3-Clause
**
** http: www.nxp.com
** mail: support@nxp.com
@ -39,6 +18,12 @@
** Revisions:
** - rev. 0.1 (2017-01-10)
** Initial version.
** - rev. 1.0 (2018-09-21)
** Update interrupt vector table and dma request source.
** Update register BEE_ADDR_OFFSET1's bitfield name to ADDR_OFFSET1.
** Split GPIO_COMBINED_IRQS to GPIO_COMBINED_LOW_IRQS and GPIO_COMBINED_HIGH_IRQS.
** - rev. 1.1 (2018-11-16)
** Update feature files to align with IMXRT1050RM Rev.1.
**
** ###################################################################
*/
@ -48,532 +33,110 @@
/* SOC module features */
/* @brief ACMP availability on the SoC. */
#define FSL_FEATURE_SOC_ACMP_COUNT (0)
/* @brief ADC availability on the SoC. */
#define FSL_FEATURE_SOC_ADC_COUNT (2)
/* @brief ADC12 availability on the SoC. */
#define FSL_FEATURE_SOC_ADC12_COUNT (0)
/* @brief ADC16 availability on the SoC. */
#define FSL_FEATURE_SOC_ADC16_COUNT (0)
/* @brief ADC_5HC availability on the SoC. */
#define FSL_FEATURE_SOC_ADC_5HC_COUNT (0)
/* @brief AES availability on the SoC. */
#define FSL_FEATURE_SOC_AES_COUNT (0)
/* @brief AFE availability on the SoC. */
#define FSL_FEATURE_SOC_AFE_COUNT (0)
/* @brief AGC availability on the SoC. */
#define FSL_FEATURE_SOC_AGC_COUNT (0)
/* @brief AIPS availability on the SoC. */
#define FSL_FEATURE_SOC_AIPS_COUNT (0)
/* @brief AIPSTZ availability on the SoC. */
#define FSL_FEATURE_SOC_AIPSTZ_COUNT (4)
/* @brief ANATOP availability on the SoC. */
#define FSL_FEATURE_SOC_ANATOP_COUNT (0)
/* @brief AOI availability on the SoC. */
#define FSL_FEATURE_SOC_AOI_COUNT (2)
/* @brief APBH availability on the SoC. */
#define FSL_FEATURE_SOC_APBH_COUNT (0)
/* @brief ASMC availability on the SoC. */
#define FSL_FEATURE_SOC_ASMC_COUNT (0)
/* @brief ASRC availability on the SoC. */
#define FSL_FEATURE_SOC_ASRC_COUNT (0)
/* @brief ASYNC_SYSCON availability on the SoC. */
#define FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT (0)
/* @brief ATX availability on the SoC. */
#define FSL_FEATURE_SOC_ATX_COUNT (0)
/* @brief AXBS availability on the SoC. */
#define FSL_FEATURE_SOC_AXBS_COUNT (0)
/* @brief BCH availability on the SoC. */
#define FSL_FEATURE_SOC_BCH_COUNT (0)
/* @brief BLEDP availability on the SoC. */
#define FSL_FEATURE_SOC_BLEDP_COUNT (0)
/* @brief BOD availability on the SoC. */
#define FSL_FEATURE_SOC_BOD_COUNT (0)
/* @brief CAAM availability on the SoC. */
#define FSL_FEATURE_SOC_CAAM_COUNT (0)
/* @brief CADC availability on the SoC. */
#define FSL_FEATURE_SOC_CADC_COUNT (0)
/* @brief CALIB availability on the SoC. */
#define FSL_FEATURE_SOC_CALIB_COUNT (0)
/* @brief CAN availability on the SoC. */
#define FSL_FEATURE_SOC_CAN_COUNT (0)
/* @brief CAU availability on the SoC. */
#define FSL_FEATURE_SOC_CAU_COUNT (0)
/* @brief CAU3 availability on the SoC. */
#define FSL_FEATURE_SOC_CAU3_COUNT (0)
/* @brief CCM availability on the SoC. */
#define FSL_FEATURE_SOC_CCM_COUNT (1)
/* @brief CCM_ANALOG availability on the SoC. */
#define FSL_FEATURE_SOC_CCM_ANALOG_COUNT (1)
/* @brief CHRG availability on the SoC. */
#define FSL_FEATURE_SOC_CHRG_COUNT (0)
/* @brief CLKCTL0 availability on the SoC. */
#define FSL_FEATURE_SOC_CLKCTL0_COUNT (0)
/* @brief CLKCTL1 availability on the SoC. */
#define FSL_FEATURE_SOC_CLKCTL1_COUNT (0)
/* @brief CMP availability on the SoC. */
#define FSL_FEATURE_SOC_CMP_COUNT (4)
/* @brief CMT availability on the SoC. */
#define FSL_FEATURE_SOC_CMT_COUNT (0)
/* @brief CNC availability on the SoC. */
#define FSL_FEATURE_SOC_CNC_COUNT (0)
/* @brief COP availability on the SoC. */
#define FSL_FEATURE_SOC_COP_COUNT (0)
/* @brief CRC availability on the SoC. */
#define FSL_FEATURE_SOC_CRC_COUNT (0)
/* @brief CS availability on the SoC. */
#define FSL_FEATURE_SOC_CS_COUNT (0)
/* @brief CSI availability on the SoC. */
#define FSL_FEATURE_SOC_CSI_COUNT (1)
/* @brief CT32B availability on the SoC. */
#define FSL_FEATURE_SOC_CT32B_COUNT (0)
/* @brief CTI availability on the SoC. */
#define FSL_FEATURE_SOC_CTI_COUNT (0)
/* @brief CTIMER availability on the SoC. */
#define FSL_FEATURE_SOC_CTIMER_COUNT (0)
/* @brief DAC availability on the SoC. */
#define FSL_FEATURE_SOC_DAC_COUNT (0)
/* @brief DAC32 availability on the SoC. */
#define FSL_FEATURE_SOC_DAC32_COUNT (0)
/* @brief DCDC availability on the SoC. */
#define FSL_FEATURE_SOC_DCDC_COUNT (1)
/* @brief DCP availability on the SoC. */
#define FSL_FEATURE_SOC_DCP_COUNT (1)
/* @brief DDR availability on the SoC. */
#define FSL_FEATURE_SOC_DDR_COUNT (0)
/* @brief DDRC availability on the SoC. */
#define FSL_FEATURE_SOC_DDRC_COUNT (0)
/* @brief DDRC_MP availability on the SoC. */
#define FSL_FEATURE_SOC_DDRC_MP_COUNT (0)
/* @brief DDR_PHY availability on the SoC. */
#define FSL_FEATURE_SOC_DDR_PHY_COUNT (0)
/* @brief DMA availability on the SoC. */
#define FSL_FEATURE_SOC_DMA_COUNT (0)
/* @brief DMAMUX availability on the SoC. */
#define FSL_FEATURE_SOC_DMAMUX_COUNT (1)
/* @brief DMIC availability on the SoC. */
#define FSL_FEATURE_SOC_DMIC_COUNT (0)
/* @brief DRY availability on the SoC. */
#define FSL_FEATURE_SOC_DRY_COUNT (0)
/* @brief DSPI availability on the SoC. */
#define FSL_FEATURE_SOC_DSPI_COUNT (0)
/* @brief ECSPI availability on the SoC. */
#define FSL_FEATURE_SOC_ECSPI_COUNT (0)
/* @brief EDMA availability on the SoC. */
#define FSL_FEATURE_SOC_EDMA_COUNT (1)
/* @brief EEPROM availability on the SoC. */
#define FSL_FEATURE_SOC_EEPROM_COUNT (0)
/* @brief EIM availability on the SoC. */
#define FSL_FEATURE_SOC_EIM_COUNT (0)
/* @brief EMC availability on the SoC. */
#define FSL_FEATURE_SOC_EMC_COUNT (0)
/* @brief EMVSIM availability on the SoC. */
#define FSL_FEATURE_SOC_EMVSIM_COUNT (0)
/* @brief ENC availability on the SoC. */
#define FSL_FEATURE_SOC_ENC_COUNT (4)
/* @brief ENET availability on the SoC. */
#define FSL_FEATURE_SOC_ENET_COUNT (1)
/* @brief EPDC availability on the SoC. */
#define FSL_FEATURE_SOC_EPDC_COUNT (0)
/* @brief EPIT availability on the SoC. */
#define FSL_FEATURE_SOC_EPIT_COUNT (0)
/* @brief ESAI availability on the SoC. */
#define FSL_FEATURE_SOC_ESAI_COUNT (0)
/* @brief EWM availability on the SoC. */
#define FSL_FEATURE_SOC_EWM_COUNT (1)
/* @brief FB availability on the SoC. */
#define FSL_FEATURE_SOC_FB_COUNT (0)
/* @brief FGPIO availability on the SoC. */
#define FSL_FEATURE_SOC_FGPIO_COUNT (0)
/* @brief FLASH availability on the SoC. */
#define FSL_FEATURE_SOC_FLASH_COUNT (0)
/* @brief FLEXCAN availability on the SoC. */
#define FSL_FEATURE_SOC_FLEXCAN_COUNT (2)
/* @brief FLEXCOMM availability on the SoC. */
#define FSL_FEATURE_SOC_FLEXCOMM_COUNT (0)
/* @brief FLEXIO availability on the SoC. */
#define FSL_FEATURE_SOC_FLEXIO_COUNT (2)
/* @brief FLEXRAM availability on the SoC. */
#define FSL_FEATURE_SOC_FLEXRAM_COUNT (1)
/* @brief FLEXSPI availability on the SoC. */
#define FSL_FEATURE_SOC_FLEXSPI_COUNT (1)
/* @brief FMC availability on the SoC. */
#define FSL_FEATURE_SOC_FMC_COUNT (0)
/* @brief FREQME availability on the SoC. */
#define FSL_FEATURE_SOC_FREQME_COUNT (0)
/* @brief FSKDT availability on the SoC. */
#define FSL_FEATURE_SOC_FSKDT_COUNT (0)
/* @brief FSP availability on the SoC. */
#define FSL_FEATURE_SOC_FSP_COUNT (0)
/* @brief FTFA availability on the SoC. */
#define FSL_FEATURE_SOC_FTFA_COUNT (0)
/* @brief FTFE availability on the SoC. */
#define FSL_FEATURE_SOC_FTFE_COUNT (0)
/* @brief FTFL availability on the SoC. */
#define FSL_FEATURE_SOC_FTFL_COUNT (0)
/* @brief FTM availability on the SoC. */
#define FSL_FEATURE_SOC_FTM_COUNT (0)
/* @brief FTMRA availability on the SoC. */
#define FSL_FEATURE_SOC_FTMRA_COUNT (0)
/* @brief FTMRE availability on the SoC. */
#define FSL_FEATURE_SOC_FTMRE_COUNT (0)
/* @brief FTMRH availability on the SoC. */
#define FSL_FEATURE_SOC_FTMRH_COUNT (0)
/* @brief GINT availability on the SoC. */
#define FSL_FEATURE_SOC_GINT_COUNT (0)
/* @brief GPC availability on the SoC. */
#define FSL_FEATURE_SOC_GPC_COUNT (1)
/* @brief GPC_PGC availability on the SoC. */
#define FSL_FEATURE_SOC_GPC_PGC_COUNT (0)
/* @brief GPIO availability on the SoC. */
#define FSL_FEATURE_SOC_GPIO_COUNT (0)
/* @brief GPMI availability on the SoC. */
#define FSL_FEATURE_SOC_GPMI_COUNT (0)
/* @brief GPT availability on the SoC. */
#define FSL_FEATURE_SOC_GPT_COUNT (2)
/* @brief HASH availability on the SoC. */
#define FSL_FEATURE_SOC_HASH_COUNT (0)
/* @brief HSADC availability on the SoC. */
#define FSL_FEATURE_SOC_HSADC_COUNT (0)
/* @brief I2C availability on the SoC. */
#define FSL_FEATURE_SOC_I2C_COUNT (0)
/* @brief I2S availability on the SoC. */
#define FSL_FEATURE_SOC_I2S_COUNT (3)
/* @brief ICS availability on the SoC. */
#define FSL_FEATURE_SOC_ICS_COUNT (0)
/* @brief IEE availability on the SoC. */
#define FSL_FEATURE_SOC_IEE_COUNT (0)
/* @brief IEER availability on the SoC. */
#define FSL_FEATURE_SOC_IEER_COUNT (0)
/* @brief IGPIO availability on the SoC. */
#define FSL_FEATURE_SOC_IGPIO_COUNT (5)
/* @brief II2C availability on the SoC. */
#define FSL_FEATURE_SOC_II2C_COUNT (0)
/* @brief INPUTMUX availability on the SoC. */
#define FSL_FEATURE_SOC_INPUTMUX_COUNT (0)
/* @brief INTMUX availability on the SoC. */
#define FSL_FEATURE_SOC_INTMUX_COUNT (0)
/* @brief IOCON availability on the SoC. */
#define FSL_FEATURE_SOC_IOCON_COUNT (0)
/* @brief IOMUXC availability on the SoC. */
#define FSL_FEATURE_SOC_IOMUXC_COUNT (1)
/* @brief IOMUXC_GPR availability on the SoC. */
#define FSL_FEATURE_SOC_IOMUXC_GPR_COUNT (1)
/* @brief IOMUXC_LPSR availability on the SoC. */
#define FSL_FEATURE_SOC_IOMUXC_LPSR_COUNT (0)
/* @brief IOMUXC_LPSR_GPR availability on the SoC. */
#define FSL_FEATURE_SOC_IOMUXC_LPSR_GPR_COUNT (0)
/* @brief IOMUXC_SNVS availability on the SoC. */
#define FSL_FEATURE_SOC_IOMUXC_SNVS_COUNT (1)
/* @brief IOPCTL availability on the SoC. */
#define FSL_FEATURE_SOC_IOPCTL_COUNT (0)
/* @brief IPWM availability on the SoC. */
#define FSL_FEATURE_SOC_IPWM_COUNT (0)
/* @brief IRQ availability on the SoC. */
#define FSL_FEATURE_SOC_IRQ_COUNT (0)
/* @brief IUART availability on the SoC. */
#define FSL_FEATURE_SOC_IUART_COUNT (0)
/* @brief KBI availability on the SoC. */
#define FSL_FEATURE_SOC_KBI_COUNT (0)
/* @brief KPP availability on the SoC. */
#define FSL_FEATURE_SOC_KPP_COUNT (1)
/* @brief L2CACHEC availability on the SoC. */
#define FSL_FEATURE_SOC_L2CACHEC_COUNT (0)
/* @brief LCD availability on the SoC. */
#define FSL_FEATURE_SOC_LCD_COUNT (0)
/* @brief LCDC availability on the SoC. */
#define FSL_FEATURE_SOC_LCDC_COUNT (0)
/* @brief LCDIF availability on the SoC. */
#define FSL_FEATURE_SOC_LCDIF_COUNT (1)
/* @brief LDO availability on the SoC. */
#define FSL_FEATURE_SOC_LDO_COUNT (0)
/* @brief LLWU availability on the SoC. */
#define FSL_FEATURE_SOC_LLWU_COUNT (0)
/* @brief LMEM availability on the SoC. */
#define FSL_FEATURE_SOC_LMEM_COUNT (0)
/* @brief LPADC availability on the SoC. */
#define FSL_FEATURE_SOC_LPADC_COUNT (0)
/* @brief LPCMP availability on the SoC. */
#define FSL_FEATURE_SOC_LPCMP_COUNT (0)
/* @brief LPDAC availability on the SoC. */
#define FSL_FEATURE_SOC_LPDAC_COUNT (0)
/* @brief LPI2C availability on the SoC. */
#define FSL_FEATURE_SOC_LPI2C_COUNT (4)
/* @brief LPIT availability on the SoC. */
#define FSL_FEATURE_SOC_LPIT_COUNT (0)
/* @brief LPSCI availability on the SoC. */
#define FSL_FEATURE_SOC_LPSCI_COUNT (0)
/* @brief LPSPI availability on the SoC. */
#define FSL_FEATURE_SOC_LPSPI_COUNT (4)
/* @brief LPTMR availability on the SoC. */
#define FSL_FEATURE_SOC_LPTMR_COUNT (0)
/* @brief LPTPM availability on the SoC. */
#define FSL_FEATURE_SOC_LPTPM_COUNT (0)
/* @brief LPUART availability on the SoC. */
#define FSL_FEATURE_SOC_LPUART_COUNT (8)
/* @brief LTC availability on the SoC. */
#define FSL_FEATURE_SOC_LTC_COUNT (0)
/* @brief MAILBOX availability on the SoC. */
#define FSL_FEATURE_SOC_MAILBOX_COUNT (0)
/* @brief MC availability on the SoC. */
#define FSL_FEATURE_SOC_MC_COUNT (0)
/* @brief MCG availability on the SoC. */
#define FSL_FEATURE_SOC_MCG_COUNT (0)
/* @brief MCGLITE availability on the SoC. */
#define FSL_FEATURE_SOC_MCGLITE_COUNT (0)
/* @brief MCM availability on the SoC. */
#define FSL_FEATURE_SOC_MCM_COUNT (0)
/* @brief MIPI_CSI2 availability on the SoC. */
#define FSL_FEATURE_SOC_MIPI_CSI2_COUNT (0)
/* @brief MIPI_CSI2RX availability on the SoC. */
#define FSL_FEATURE_SOC_MIPI_CSI2RX_COUNT (0)
/* @brief MIPI_DSI availability on the SoC. */
#define FSL_FEATURE_SOC_MIPI_DSI_COUNT (0)
/* @brief MIPI_DSI_HOST availability on the SoC. */
#define FSL_FEATURE_SOC_MIPI_DSI_HOST_COUNT (0)
/* @brief MMAU availability on the SoC. */
#define FSL_FEATURE_SOC_MMAU_COUNT (0)
/* @brief MMCAU availability on the SoC. */
#define FSL_FEATURE_SOC_MMCAU_COUNT (0)
/* @brief MMDC availability on the SoC. */
#define FSL_FEATURE_SOC_MMDC_COUNT (0)
/* @brief MMDVSQ availability on the SoC. */
#define FSL_FEATURE_SOC_MMDVSQ_COUNT (0)
/* @brief MPU availability on the SoC. */
#define FSL_FEATURE_SOC_MPU_COUNT (0)
/* @brief MRT availability on the SoC. */
#define FSL_FEATURE_SOC_MRT_COUNT (0)
/* @brief MSCAN availability on the SoC. */
#define FSL_FEATURE_SOC_MSCAN_COUNT (0)
/* @brief MSCM availability on the SoC. */
#define FSL_FEATURE_SOC_MSCM_COUNT (0)
/* @brief MTB availability on the SoC. */
#define FSL_FEATURE_SOC_MTB_COUNT (0)
/* @brief MTBDWT availability on the SoC. */
#define FSL_FEATURE_SOC_MTBDWT_COUNT (0)
/* @brief MU availability on the SoC. */
#define FSL_FEATURE_SOC_MU_COUNT (0)
/* @brief NFC availability on the SoC. */
#define FSL_FEATURE_SOC_NFC_COUNT (0)
/* @brief OCOTP availability on the SoC. */
#define FSL_FEATURE_SOC_OCOTP_COUNT (1)
/* @brief OPAMP availability on the SoC. */
#define FSL_FEATURE_SOC_OPAMP_COUNT (0)
/* @brief OTPC availability on the SoC. */
#define FSL_FEATURE_SOC_OTPC_COUNT (0)
/* @brief OSC availability on the SoC. */
#define FSL_FEATURE_SOC_OSC_COUNT (0)
/* @brief OSC32 availability on the SoC. */
#define FSL_FEATURE_SOC_OSC32_COUNT (0)
/* @brief OTFAD availability on the SoC. */
#define FSL_FEATURE_SOC_OTFAD_COUNT (0)
/* @brief PCC availability on the SoC. */
#define FSL_FEATURE_SOC_PCC_COUNT (0)
/* @brief PCIE_PHY_CMN availability on the SoC. */
#define FSL_FEATURE_SOC_PCIE_PHY_CMN_COUNT (0)
/* @brief PCIE_PHY_TRSV availability on the SoC. */
#define FSL_FEATURE_SOC_PCIE_PHY_TRSV_COUNT (0)
/* @brief PDB availability on the SoC. */
#define FSL_FEATURE_SOC_PDB_COUNT (0)
/* @brief PGA availability on the SoC. */
#define FSL_FEATURE_SOC_PGA_COUNT (0)
/* @brief PIMCTL availability on the SoC. */
#define FSL_FEATURE_SOC_PIMCTL_COUNT (0)
/* @brief PINT availability on the SoC. */
#define FSL_FEATURE_SOC_PINT_COUNT (0)
/* @brief PIT availability on the SoC. */
#define FSL_FEATURE_SOC_PIT_COUNT (1)
/* @brief PMC availability on the SoC. */
#define FSL_FEATURE_SOC_PMC_COUNT (0)
/* @brief PMU availability on the SoC. */
#define FSL_FEATURE_SOC_PMU_COUNT (1)
/* @brief POWERQUAD availability on the SoC. */
#define FSL_FEATURE_SOC_POWERQUAD_COUNT (0)
/* @brief PORT availability on the SoC. */
#define FSL_FEATURE_SOC_PORT_COUNT (0)
/* @brief PROP availability on the SoC. */
#define FSL_FEATURE_SOC_PROP_COUNT (0)
/* @brief PWM availability on the SoC. */
#define FSL_FEATURE_SOC_PWM_COUNT (4)
/* @brief PWT availability on the SoC. */
#define FSL_FEATURE_SOC_PWT_COUNT (0)
/* @brief PXP availability on the SoC. */
#define FSL_FEATURE_SOC_PXP_COUNT (1)
/* @brief QDDKEY availability on the SoC. */
#define FSL_FEATURE_SOC_QDDKEY_COUNT (0)
/* @brief QDEC availability on the SoC. */
#define FSL_FEATURE_SOC_QDEC_COUNT (0)
/* @brief QuadSPI availability on the SoC. */
#define FSL_FEATURE_SOC_QuadSPI_COUNT (0)
/* @brief RCM availability on the SoC. */
#define FSL_FEATURE_SOC_RCM_COUNT (0)
/* @brief RDC availability on the SoC. */
#define FSL_FEATURE_SOC_RDC_COUNT (0)
/* @brief RDC_SEMAPHORE availability on the SoC. */
#define FSL_FEATURE_SOC_RDC_SEMAPHORE_COUNT (0)
/* @brief RFSYS availability on the SoC. */
#define FSL_FEATURE_SOC_RFSYS_COUNT (0)
/* @brief RFVBAT availability on the SoC. */
#define FSL_FEATURE_SOC_RFVBAT_COUNT (0)
/* @brief RIT availability on the SoC. */
#define FSL_FEATURE_SOC_RIT_COUNT (0)
/* @brief RNG availability on the SoC. */
#define FSL_FEATURE_SOC_RNG_COUNT (0)
/* @brief RNGB availability on the SoC. */
#define FSL_FEATURE_SOC_RNGB_COUNT (0)
/* @brief ROM availability on the SoC. */
#define FSL_FEATURE_SOC_ROM_COUNT (0)
/* @brief ROMC availability on the SoC. */
#define FSL_FEATURE_SOC_ROMC_COUNT (1)
/* @brief RSIM availability on the SoC. */
#define FSL_FEATURE_SOC_RSIM_COUNT (0)
/* @brief RSTCTL0 availability on the SoC. */
#define FSL_FEATURE_SOC_RSTCTL0_COUNT (0)
/* @brief RSTCTL1 availability on the SoC. */
#define FSL_FEATURE_SOC_RSTCTL1_COUNT (0)
/* @brief RTC availability on the SoC. */
#define FSL_FEATURE_SOC_RTC_COUNT (0)
/* @brief SCG availability on the SoC. */
#define FSL_FEATURE_SOC_SCG_COUNT (0)
/* @brief SCI availability on the SoC. */
#define FSL_FEATURE_SOC_SCI_COUNT (0)
/* @brief SCT availability on the SoC. */
#define FSL_FEATURE_SOC_SCT_COUNT (0)
/* @brief SDHC availability on the SoC. */
#define FSL_FEATURE_SOC_SDHC_COUNT (0)
/* @brief SDIF availability on the SoC. */
#define FSL_FEATURE_SOC_SDIF_COUNT (0)
/* @brief SDIO availability on the SoC. */
#define FSL_FEATURE_SOC_SDIO_COUNT (0)
/* @brief SDMA availability on the SoC. */
#define FSL_FEATURE_SOC_SDMA_COUNT (0)
/* @brief SDMAARM availability on the SoC. */
#define FSL_FEATURE_SOC_SDMAARM_COUNT (0)
/* @brief SDMABP availability on the SoC. */
#define FSL_FEATURE_SOC_SDMABP_COUNT (0)
/* @brief SDMACORE availability on the SoC. */
#define FSL_FEATURE_SOC_SDMACORE_COUNT (0)
/* @brief SDMCORE availability on the SoC. */
#define FSL_FEATURE_SOC_SDMCORE_COUNT (0)
/* @brief SDRAM availability on the SoC. */
#define FSL_FEATURE_SOC_SDRAM_COUNT (0)
/* @brief SEMA4 availability on the SoC. */
#define FSL_FEATURE_SOC_SEMA4_COUNT (0)
/* @brief SEMA42 availability on the SoC. */
#define FSL_FEATURE_SOC_SEMA42_COUNT (0)
/* @brief SEMC availability on the SoC. */
#define FSL_FEATURE_SOC_SEMC_COUNT (1)
/* @brief SHA availability on the SoC. */
#define FSL_FEATURE_SOC_SHA_COUNT (0)
/* @brief SIM availability on the SoC. */
#define FSL_FEATURE_SOC_SIM_COUNT (0)
/* @brief SJC availability on the SoC. */
#define FSL_FEATURE_SOC_SJC_COUNT (0)
/* @brief SLCD availability on the SoC. */
#define FSL_FEATURE_SOC_SLCD_COUNT (0)
/* @brief SMARTCARD availability on the SoC. */
#define FSL_FEATURE_SOC_SMARTCARD_COUNT (0)
/* @brief SMC availability on the SoC. */
#define FSL_FEATURE_SOC_SMC_COUNT (0)
/* @brief SNVS availability on the SoC. */
#define FSL_FEATURE_SOC_SNVS_COUNT (1)
/* @brief SPBA availability on the SoC. */
#define FSL_FEATURE_SOC_SPBA_COUNT (0)
/* @brief SPDIF availability on the SoC. */
#define FSL_FEATURE_SOC_SPDIF_COUNT (1)
/* @brief SPI availability on the SoC. */
#define FSL_FEATURE_SOC_SPI_COUNT (0)
/* @brief SPIFI availability on the SoC. */
#define FSL_FEATURE_SOC_SPIFI_COUNT (0)
/* @brief SPM availability on the SoC. */
#define FSL_FEATURE_SOC_SPM_COUNT (0)
/* @brief SRC availability on the SoC. */
#define FSL_FEATURE_SOC_SRC_COUNT (1)
/* @brief SYSCON availability on the SoC. */
#define FSL_FEATURE_SOC_SYSCON_COUNT (0)
/* @brief SYSCTL0 availability on the SoC. */
#define FSL_FEATURE_SOC_SYSCTL0_COUNT (0)
/* @brief SYSCTL1 availability on the SoC. */
#define FSL_FEATURE_SOC_SYSCTL1_COUNT (0)
/* @brief TEMPMON availability on the SoC. */
#define FSL_FEATURE_SOC_TEMPMON_COUNT (1)
/* @brief TMR availability on the SoC. */
#define FSL_FEATURE_SOC_TMR_COUNT (4)
/* @brief TPM availability on the SoC. */
#define FSL_FEATURE_SOC_TPM_COUNT (0)
/* @brief TRGMUX availability on the SoC. */
#define FSL_FEATURE_SOC_TRGMUX_COUNT (0)
/* @brief TRIAMP availability on the SoC. */
#define FSL_FEATURE_SOC_TRIAMP_COUNT (0)
/* @brief TRNG availability on the SoC. */
#define FSL_FEATURE_SOC_TRNG_COUNT (1)
/* @brief TSC availability on the SoC. */
#define FSL_FEATURE_SOC_TSC_COUNT (1)
/* @brief TSI availability on the SoC. */
#define FSL_FEATURE_SOC_TSI_COUNT (0)
/* @brief TSTMR availability on the SoC. */
#define FSL_FEATURE_SOC_TSTMR_COUNT (0)
/* @brief UART availability on the SoC. */
#define FSL_FEATURE_SOC_UART_COUNT (0)
/* @brief USART availability on the SoC. */
#define FSL_FEATURE_SOC_USART_COUNT (0)
/* @brief USB availability on the SoC. */
#define FSL_FEATURE_SOC_USB_COUNT (0)
/* @brief USBHS availability on the SoC. */
#define FSL_FEATURE_SOC_USBHS_COUNT (2)
/* @brief USBDCD availability on the SoC. */
#define FSL_FEATURE_SOC_USBDCD_COUNT (0)
/* @brief USBFSH availability on the SoC. */
#define FSL_FEATURE_SOC_USBFSH_COUNT (0)
/* @brief USBHSD availability on the SoC. */
#define FSL_FEATURE_SOC_USBHSD_COUNT (0)
/* @brief USBHSDCD availability on the SoC. */
#define FSL_FEATURE_SOC_USBHSDCD_COUNT (0)
/* @brief USBHSH availability on the SoC. */
#define FSL_FEATURE_SOC_USBHSH_COUNT (0)
/* @brief USBNC availability on the SoC. */
#define FSL_FEATURE_SOC_USBNC_COUNT (2)
/* @brief USBPHY availability on the SoC. */
#define FSL_FEATURE_SOC_USBPHY_COUNT (2)
/* @brief USB_HSIC availability on the SoC. */
#define FSL_FEATURE_SOC_USB_HSIC_COUNT (0)
/* @brief USB_OTG availability on the SoC. */
#define FSL_FEATURE_SOC_USB_OTG_COUNT (0)
/* @brief USBVREG availability on the SoC. */
#define FSL_FEATURE_SOC_USBVREG_COUNT (0)
/* @brief USDHC availability on the SoC. */
#define FSL_FEATURE_SOC_USDHC_COUNT (2)
/* @brief UTICK availability on the SoC. */
#define FSL_FEATURE_SOC_UTICK_COUNT (0)
/* @brief VIU availability on the SoC. */
#define FSL_FEATURE_SOC_VIU_COUNT (0)
/* @brief VREF availability on the SoC. */
#define FSL_FEATURE_SOC_VREF_COUNT (0)
/* @brief VFIFO availability on the SoC. */
#define FSL_FEATURE_SOC_VFIFO_COUNT (0)
/* @brief WDOG availability on the SoC. */
#define FSL_FEATURE_SOC_WDOG_COUNT (2)
/* @brief WKPU availability on the SoC. */
#define FSL_FEATURE_SOC_WKPU_COUNT (0)
/* @brief WWDT availability on the SoC. */
#define FSL_FEATURE_SOC_WWDT_COUNT (0)
/* @brief XBAR availability on the SoC. */
#define FSL_FEATURE_SOC_XBAR_COUNT (0)
/* @brief XBARA availability on the SoC. */
#define FSL_FEATURE_SOC_XBARA_COUNT (1)
/* @brief XBARB availability on the SoC. */
#define FSL_FEATURE_SOC_XBARB_COUNT (2)
/* @brief XCVR availability on the SoC. */
#define FSL_FEATURE_SOC_XCVR_COUNT (0)
/* @brief XRDC availability on the SoC. */
#define FSL_FEATURE_SOC_XRDC_COUNT (0)
/* @brief XTALOSC availability on the SoC. */
#define FSL_FEATURE_SOC_XTALOSC_COUNT (0)
/* @brief XTALOSC24M availability on the SoC. */
#define FSL_FEATURE_SOC_XTALOSC24M_COUNT (1)
/* @brief ZLL availability on the SoC. */
#define FSL_FEATURE_SOC_ZLL_COUNT (0)
/* ADC module features */
@ -582,6 +145,11 @@
/* @brief Remove ALT Clock selection feature. */
#define FSL_FEATURE_ADC_SUPPORT_ALTCLK_REMOVE (1)
/* ADC_ETC module features */
/* @brief Has DMA model control(bit field CTRL[DMA_MODE_SEL]). */
#define FSL_FEATURE_ADC_ETC_HAS_CTRL_DMA_MODE_SEL (1)
/* AOI module features */
/* @brief Maximum value of input mux. */
@ -595,20 +163,34 @@
#define FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(x) (64)
/* @brief Has doze mode support (register bit field MCR[DOZE]). */
#define FSL_FEATURE_FLEXCAN_HAS_DOZE_MODE_SUPPORT (0)
/* @brief Insatnce has doze mode support (register bit field MCR[DOZE]). */
#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_DOZE_MODE_SUPPORTn(x) (0)
/* @brief Has a glitch filter on the receive pin (register bit field MCR[WAKSRC]). */
#define FSL_FEATURE_FLEXCAN_HAS_GLITCH_FILTER (1)
/* @brief Has extended interrupt mask and flag register (register IMASK2, IFLAG2). */
#define FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER (1)
/* @brief Has extended bit timing register (register CBT). */
#define FSL_FEATURE_FLEXCAN_HAS_EXTENDED_TIMING_REGISTER (0)
/* @brief Instance has extended bit timing register (register CBT). */
#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_EXTENDED_TIMING_REGISTERn(x) (0)
/* @brief Has a receive FIFO DMA feature (register bit field MCR[DMA]). */
#define FSL_FEATURE_FLEXCAN_HAS_RX_FIFO_DMA (0)
/* @brief Instance has a receive FIFO DMA feature (register bit field MCR[DMA]). */
#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_RX_FIFO_DMAn(x) (0)
/* @brief Remove CAN Engine Clock Source Selection from unsupported part. */
#define FSL_FEATURE_FLEXCAN_SUPPORT_ENGINE_CLK_SEL_REMOVE (1)
/* @brief Instance remove CAN Engine Clock Source Selection from unsupported part. */
#define FSL_FEATURE_FLEXCAN_INSTANCE_SUPPORT_ENGINE_CLK_SEL_REMOVEn(x) (1)
/* @brief Is affected by errata with ID 5641 (Module does not transmit a message that is enabled to be transmitted at a specific moment during the arbitration process). */
#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641 (0)
/* @brief Is affected by errata with ID 5829 (FlexCAN: FlexCAN does not transmit a message that is enabled to be transmitted in a specific moment during the arbitration process). */
#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_5829 (1)
/* @brief Is affected by errata with ID 6032 (FlexCAN: A frame with wrong ID or payload is transmitted into the CAN bus when the Message Buffer under transmission is either aborted or deactivated while the CAN bus is in the Bus Idle state). */
#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_6032 (1)
/* @brief Is affected by errata with ID 9595 (FlexCAN: Corrupt frame possible if the Freeze Mode or the Low-Power Mode are entered during a Bus-Off state). */
#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_9595 (1)
/* @brief Has CAN with Flexible Data rate (CAN FD) protocol. */
#define FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE (0)
/* @brief CAN instance support Flexible Data rate (CAN FD) protocol. */
#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_FLEXIBLE_DATA_RATEn(x) (0)
/* @brief Has extra MB interrupt or common one. */
#define FSL_FEATURE_FLEXCAN_HAS_EXTRA_MB_INT (1)
@ -666,10 +248,40 @@
/* @brief Has Additional 1588 Timer Channel Interrupt. */
#define FSL_FEATURE_ENET_HAS_ADD_1588_TIMER_CHN_INT (0)
/* EWM module features */
/* @brief Has clock select (register CLKCTRL). */
#define FSL_FEATURE_EWM_HAS_CLOCK_SELECT (1)
/* @brief Has clock prescaler (register CLKPRESCALER). */
#define FSL_FEATURE_EWM_HAS_PRESCALER (1)
/* FLEXIO module features */
/* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */
#define FSL_FEATURE_FLEXIO_HAS_SHIFTER_STATUS (1)
/* @brief Has Pin Data Input Register (FLEXIO_PIN) */
#define FSL_FEATURE_FLEXIO_HAS_PIN_STATUS (1)
/* @brief Has Shifter Buffer N Nibble Byte Swapped Register (FLEXIO_SHIFTBUFNBSn) */
#define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_BYTE_SWAP (1)
/* @brief Has Shifter Buffer N Half Word Swapped Register (FLEXIO_SHIFTBUFHWSn) */
#define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_HALF_WORD_SWAP (1)
/* @brief Has Shifter Buffer N Nibble Swapped Register (FLEXIO_SHIFTBUFNISn) */
#define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_SWAP (1)
/* @brief Supports Shifter State Mode (FLEXIO_SHIFTCTLn[SMOD]) */
#define FSL_FEATURE_FLEXIO_HAS_STATE_MODE (1)
/* @brief Supports Shifter Logic Mode (FLEXIO_SHIFTCTLn[SMOD]) */
#define FSL_FEATURE_FLEXIO_HAS_LOGIC_MODE (1)
/* @brief Supports paralle width (FLEXIO_SHIFTCFGn[PWIDTH]) */
#define FSL_FEATURE_FLEXIO_HAS_PARALLEL_WIDTH (1)
/* @brief Reset value of the FLEXIO_VERID register */
#define FSL_FEATURE_FLEXIO_VERID_RESET_VALUE (0x1010001)
/* @brief Reset value of the FLEXIO_PARAM register */
#define FSL_FEATURE_FLEXIO_PARAM_RESET_VALUE (0x2200404)
/* FLEXRAM module features */
/* @brief Bank size */
#define FSL_FEATURE_FLEXRAM_INTERNAL_RAM_BANK_SIZE (32 * 1024)
#define FSL_FEATURE_FLEXRAM_INTERNAL_RAM_BANK_SIZE (32768)
/* @brief Total Bank numbers */
#define FSL_FEATURE_FLEXRAM_INTERNAL_RAM_TOTAL_BANK_NUMBERS (16)
@ -697,6 +309,15 @@
/* @brief Supports IRQ 0-31. */
#define FSL_FEATURE_GPC_HAS_IRQ_0_31 (1)
/* IGPIO module features */
/* @brief Has data register set DR_SET. */
#define FSL_FEATURE_IGPIO_HAS_DR_SET (1)
/* @brief Has data register clear DR_CLEAR. */
#define FSL_FEATURE_IGPIO_HAS_DR_CLEAR (1)
/* @brief Has data register toggle DR_TOGGLE. */
#define FSL_FEATURE_IGPIO_HAS_DR_TOGGLE (1)
/* LCDIF module features */
/* @brief LCDIF does not support alpha support. */
@ -796,7 +417,7 @@
/* @brief Lowest interrupt request number. */
#define FSL_FEATURE_INTERRUPT_IRQ_MIN (-14)
/* @brief Highest interrupt request number. */
#define FSL_FEATURE_INTERRUPT_IRQ_MAX (159)
#define FSL_FEATURE_INTERRUPT_IRQ_MAX (151)
/* OCOTP module features */
@ -885,8 +506,19 @@
#define FSL_FEATURE_SAI_INT_SOURCE_NUM (2)
/* @brief Has register of MCR. */
#define FSL_FEATURE_SAI_HAS_MCR (0)
/* @brief Has bit field MICS of the MCR register. */
#define FSL_FEATURE_SAI_HAS_NO_MCR_MICS (1)
/* @brief Has register of MDR */
#define FSL_FEATURE_SAI_HAS_MDR (0)
/* @brief Has support the BCLK bypass mode when BCLK = MCLK. */
#define FSL_FEATURE_SAI_HAS_BCLK_BYPASS (0)
/* SEMC module features */
/* @brief Has WDH time in NOR controller (register bit field NORCR2[WDH]). */
#define FSL_FEATURE_SEMC_HAS_NOR_WDH_TIME (1)
/* @brief Has WDS time in NOR controller (register bit field NORCR2[WDS]).) */
#define FSL_FEATURE_SEMC_HAS_NOR_WDS_TIME (1)
/* SNVS module features */
@ -912,7 +544,7 @@
/* @brief There is CORE0_RST bit in SCR register. */
#define FSL_FEATURE_SRC_HAS_SCR_CORE0_RST (1)
/* @brief There is LOCKUP_RST bit in SCR register. */
#define FSL_FEATURE_SRC_HAS_SCR_LOCKUP_RST (1)
#define FSL_FEATURE_SRC_HAS_SCR_LOCKUP_RST (0)
/* @brief There is SWRC bit in SCR register. */
#define FSL_FEATURE_SRC_HAS_SCR_SWRC (0)
/* @brief There is EIM_RST bit in SCR register. */

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ext/hal/nxp/mcux/devices/MIMXRT1052/fsl_clock.c
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ext/hal/nxp/mcux/devices/MIMXRT1052/fsl_clock.h
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ext/hal/nxp/mcux/devices/MIMXRT1052/fsl_device_registers.h
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@ -1,30 +1,9 @@
/*
* Copyright 2014-2016 Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* Copyright 2016-2018 NXP
* All rights reserved.
*
* 1. Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* SPDX-License-Identifier: BSD-3-Clause
*
*/
@ -36,7 +15,8 @@
*
* The CPU macro should be declared in the project or makefile.
*/
#if (defined(CPU_MIMXRT1052CVL5A) || defined(CPU_MIMXRT1052DVL6A))
#if (defined(CPU_MIMXRT1052CVJ5B) || defined(CPU_MIMXRT1052CVL5B) || defined(CPU_MIMXRT1052DVJ6B) || \
defined(CPU_MIMXRT1052DVL6B))
#define MIMXRT1052_SERIES

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ext/hal/nxp/mcux/devices/MIMXRT1052/fsl_iomuxc.h
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@ -1,31 +1,9 @@
/*
* Copyright (c) 2016, Freescale Semiconductor, Inc.
* Copyright 2016 Freescale Semiconductor, Inc.
* Copyright 2016-2018 NXP
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _FSL_IOMUXC_H_
@ -43,6 +21,10 @@
/*******************************************************************************
* Definitions
******************************************************************************/
/* Component ID definition, used by tools. */
#ifndef FSL_COMPONENT_ID
#define FSL_COMPONENT_ID "platform.drivers.iomuxc"
#endif
/*! @name Driver version */
/*@{*/
@ -54,7 +36,7 @@
/*@{*/
/*! @brief The pin function ID is a tuple of <muxRegister muxMode inputRegister inputDaisy configRegister> */
#define IOMUXC_SNVS_WAKEUP_GPIO5_IO00 0x400A8000U, 0x5U, 0, 0, 0x400A8018U
#define IOMUXC_SNVS_WAKEUP_NMI_GLUE_NMI 0x400A8000U, 0x7U, 0, 0, 0x400A8018U
#define IOMUXC_SNVS_WAKEUP_NMI_GLUE_NMI 0x400A8000U, 0x7U, 0x401F8568U, 0x1U, 0x400A8018U
#define IOMUXC_SNVS_PMIC_ON_REQ_SNVS_LP_PMIC_ON_REQ 0x400A8004U, 0x0U, 0, 0, 0x400A801CU
#define IOMUXC_SNVS_PMIC_ON_REQ_GPIO5_IO01 0x400A8004U, 0x5U, 0, 0, 0x400A801CU
@ -74,7 +56,6 @@
#define IOMUXC_GPIO_EMC_00_XBAR1_XBAR_IN02 0x401F8014U, 0x3U, 0x401F860CU, 0x0U, 0x401F8204U
#define IOMUXC_GPIO_EMC_00_FLEXIO1_FLEXIO00 0x401F8014U, 0x4U, 0, 0, 0x401F8204U
#define IOMUXC_GPIO_EMC_00_GPIO4_IO00 0x401F8014U, 0x5U, 0, 0, 0x401F8204U
#define IOMUXC_GPIO_EMC_00_JTAG_DONE 0x401F8014U, 0x7U, 0, 0, 0x401F8204U
#define IOMUXC_GPIO_EMC_01_SEMC_DATA01 0x401F8018U, 0x0U, 0, 0, 0x401F8208U
#define IOMUXC_GPIO_EMC_01_FLEXPWM4_PWMB00 0x401F8018U, 0x1U, 0, 0, 0x401F8208U
@ -82,7 +63,6 @@
#define IOMUXC_GPIO_EMC_01_XBAR1_IN03 0x401F8018U, 0x3U, 0x401F8610U, 0x0U, 0x401F8208U
#define IOMUXC_GPIO_EMC_01_FLEXIO1_FLEXIO01 0x401F8018U, 0x4U, 0, 0, 0x401F8208U
#define IOMUXC_GPIO_EMC_01_GPIO4_IO01 0x401F8018U, 0x5U, 0, 0, 0x401F8208U
#define IOMUXC_GPIO_EMC_01_JTAG_DE_B 0x401F8018U, 0x7U, 0, 0, 0x401F8208U
#define IOMUXC_GPIO_EMC_02_SEMC_DATA02 0x401F801CU, 0x0U, 0, 0, 0x401F820CU
#define IOMUXC_GPIO_EMC_02_FLEXPWM4_PWMA01 0x401F801CU, 0x1U, 0x401F8498U, 0x0U, 0x401F820CU
@ -90,7 +70,6 @@
#define IOMUXC_GPIO_EMC_02_XBAR1_INOUT04 0x401F801CU, 0x3U, 0x401F8614U, 0x0U, 0x401F820CU
#define IOMUXC_GPIO_EMC_02_FLEXIO1_FLEXIO02 0x401F801CU, 0x4U, 0, 0, 0x401F820CU
#define IOMUXC_GPIO_EMC_02_GPIO4_IO02 0x401F801CU, 0x5U, 0, 0, 0x401F820CU
#define IOMUXC_GPIO_EMC_02_JTAG_FAIL 0x401F801CU, 0x7U, 0, 0, 0x401F820CU
#define IOMUXC_GPIO_EMC_03_SEMC_DATA03 0x401F8020U, 0x0U, 0, 0, 0x401F8210U
#define IOMUXC_GPIO_EMC_03_FLEXPWM4_PWMB01 0x401F8020U, 0x1U, 0, 0, 0x401F8210U
@ -98,7 +77,6 @@
#define IOMUXC_GPIO_EMC_03_XBAR1_INOUT05 0x401F8020U, 0x3U, 0x401F8618U, 0x0U, 0x401F8210U
#define IOMUXC_GPIO_EMC_03_FLEXIO1_FLEXIO03 0x401F8020U, 0x4U, 0, 0, 0x401F8210U
#define IOMUXC_GPIO_EMC_03_GPIO4_IO03 0x401F8020U, 0x5U, 0, 0, 0x401F8210U
#define IOMUXC_GPIO_EMC_03_JTAG_ACTIVE 0x401F8020U, 0x7U, 0, 0, 0x401F8210U
#define IOMUXC_GPIO_EMC_04_SEMC_DATA04 0x401F8024U, 0x0U, 0, 0, 0x401F8214U
#define IOMUXC_GPIO_EMC_04_FLEXPWM4_PWMA02 0x401F8024U, 0x1U, 0x401F849CU, 0x0U, 0x401F8214U
@ -490,6 +468,7 @@
#define IOMUXC_GPIO_AD_B0_12_FLEXPWM1_PWMX02 0x401F80ECU, 0x4U, 0, 0, 0x401F82DCU
#define IOMUXC_GPIO_AD_B0_12_GPIO1_IO12 0x401F80ECU, 0x5U, 0, 0, 0x401F82DCU
#define IOMUXC_GPIO_AD_B0_12_ENET_1588_EVENT1_OUT 0x401F80ECU, 0x6U, 0, 0, 0x401F82DCU
#define IOMUXC_GPIO_AD_B0_12_NMI_GLUE_NMI 0x401F80ECU, 0x7U, 0x401F8568U, 0x0U, 0x401F82DCU
#define IOMUXC_GPIO_AD_B0_13_LPI2C4_SDA 0x401F80F0U, 0x0U, 0x401F84E8U, 0x1U, 0x401F82E0U
#define IOMUXC_GPIO_AD_B0_13_GPT1_CLK 0x401F80F0U, 0x1U, 0, 0, 0x401F82E0U
@ -696,6 +675,7 @@
#define IOMUXC_GPIO_B0_04_LCD_DATA00 0x401F814CU, 0x0U, 0, 0, 0x401F833CU
#define IOMUXC_GPIO_B0_04_QTIMER2_TIMER1 0x401F814CU, 0x1U, 0x401F8570U, 0x1U, 0x401F833CU
#define IOMUXC_GPIO_B0_04_LPI2C2_SCL 0x401F814CU, 0x2U, 0x401F84D4U, 0x1U, 0x401F833CU
#define IOMUXC_GPIO_B0_04_ARM_CM7_TRACE00 0x401F814CU, 0x3U, 0, 0, 0x401F833CU
#define IOMUXC_GPIO_B0_04_FLEXIO2_FLEXIO04 0x401F814CU, 0x4U, 0, 0, 0x401F833CU
#define IOMUXC_GPIO_B0_04_GPIO2_IO04 0x401F814CU, 0x5U, 0, 0, 0x401F833CU
#define IOMUXC_GPIO_B0_04_SRC_BOOT_CFG00 0x401F814CU, 0x6U, 0, 0, 0x401F833CU
@ -703,6 +683,7 @@
#define IOMUXC_GPIO_B0_05_LCD_DATA01 0x401F8150U, 0x0U, 0, 0, 0x401F8340U
#define IOMUXC_GPIO_B0_05_QTIMER2_TIMER2 0x401F8150U, 0x1U, 0x401F8574U, 0x1U, 0x401F8340U
#define IOMUXC_GPIO_B0_05_LPI2C2_SDA 0x401F8150U, 0x2U, 0x401F84D8U, 0x1U, 0x401F8340U
#define IOMUXC_GPIO_B0_05_ARM_CM7_TRACE01 0x401F8150U, 0x3U, 0, 0, 0x401F8340U
#define IOMUXC_GPIO_B0_05_FLEXIO2_FLEXIO05 0x401F8150U, 0x4U, 0, 0, 0x401F8340U
#define IOMUXC_GPIO_B0_05_GPIO2_IO05 0x401F8150U, 0x5U, 0, 0, 0x401F8340U
#define IOMUXC_GPIO_B0_05_SRC_BOOT_CFG01 0x401F8150U, 0x6U, 0, 0, 0x401F8340U
@ -710,6 +691,7 @@
#define IOMUXC_GPIO_B0_06_LCD_DATA02 0x401F8154U, 0x0U, 0, 0, 0x401F8344U
#define IOMUXC_GPIO_B0_06_QTIMER3_TIMER0 0x401F8154U, 0x1U, 0x401F857CU, 0x2U, 0x401F8344U
#define IOMUXC_GPIO_B0_06_FLEXPWM2_PWMA00 0x401F8154U, 0x2U, 0x401F8478U, 0x1U, 0x401F8344U
#define IOMUXC_GPIO_B0_06_ARM_CM7_TRACE02 0x401F8154U, 0x3U, 0, 0, 0x401F8344U
#define IOMUXC_GPIO_B0_06_FLEXIO2_FLEXIO06 0x401F8154U, 0x4U, 0, 0, 0x401F8344U
#define IOMUXC_GPIO_B0_06_GPIO2_IO06 0x401F8154U, 0x5U, 0, 0, 0x401F8344U
#define IOMUXC_GPIO_B0_06_SRC_BOOT_CFG02 0x401F8154U, 0x6U, 0, 0, 0x401F8344U
@ -717,6 +699,7 @@
#define IOMUXC_GPIO_B0_07_LCD_DATA03 0x401F8158U, 0x0U, 0, 0, 0x401F8348U
#define IOMUXC_GPIO_B0_07_QTIMER3_TIMER1 0x401F8158U, 0x1U, 0x401F8580U, 0x2U, 0x401F8348U
#define IOMUXC_GPIO_B0_07_FLEXPWM2_PWMB00 0x401F8158U, 0x2U, 0x401F8488U, 0x1U, 0x401F8348U
#define IOMUXC_GPIO_B0_07_ARM_CM7_TRACE03 0x401F8158U, 0x3U, 0, 0, 0x401F8348U
#define IOMUXC_GPIO_B0_07_FLEXIO2_FLEXIO07 0x401F8158U, 0x4U, 0, 0, 0x401F8348U
#define IOMUXC_GPIO_B0_07_GPIO2_IO07 0x401F8158U, 0x5U, 0, 0, 0x401F8348U
#define IOMUXC_GPIO_B0_07_SRC_BOOT_CFG03 0x401F8158U, 0x6U, 0, 0, 0x401F8348U
@ -755,6 +738,7 @@
#define IOMUXC_GPIO_B0_12_LCD_DATA08 0x401F816CU, 0x0U, 0, 0, 0x401F835CU
#define IOMUXC_GPIO_B0_12_XBAR1_INOUT10 0x401F816CU, 0x1U, 0, 0, 0x401F835CU
#define IOMUXC_GPIO_B0_12_ARM_CM7_TRACE_CLK 0x401F816CU, 0x2U, 0, 0, 0x401F835CU
#define IOMUXC_GPIO_B0_12_SAI1_TX_DATA01 0x401F816CU, 0x3U, 0x401F85A0U, 0x1U, 0x401F835CU
#define IOMUXC_GPIO_B0_12_FLEXIO2_FLEXIO12 0x401F816CU, 0x4U, 0, 0, 0x401F835CU
#define IOMUXC_GPIO_B0_12_GPIO2_IO12 0x401F816CU, 0x5U, 0, 0, 0x401F835CU
@ -762,6 +746,7 @@
#define IOMUXC_GPIO_B0_13_LCD_DATA09 0x401F8170U, 0x0U, 0, 0, 0x401F8360U
#define IOMUXC_GPIO_B0_13_XBAR1_INOUT11 0x401F8170U, 0x1U, 0, 0, 0x401F8360U
#define IOMUXC_GPIO_B0_13_ARM_CM7_TRACE_SWO 0x401F8170U, 0x2U, 0, 0, 0x401F8360U
#define IOMUXC_GPIO_B0_13_SAI1_MCLK 0x401F8170U, 0x3U, 0x401F858CU, 0x2U, 0x401F8360U
#define IOMUXC_GPIO_B0_13_FLEXIO2_FLEXIO13 0x401F8170U, 0x4U, 0, 0, 0x401F8360U
#define IOMUXC_GPIO_B0_13_GPIO2_IO13 0x401F8170U, 0x5U, 0, 0, 0x401F8360U
@ -821,7 +806,6 @@
#define IOMUXC_GPIO_B1_04_ENET_RX_DATA00 0x401F818CU, 0x3U, 0x401F8434U, 0x1U, 0x401F837CU
#define IOMUXC_GPIO_B1_04_FLEXIO2_FLEXIO20 0x401F818CU, 0x4U, 0, 0, 0x401F837CU
#define IOMUXC_GPIO_B1_04_GPIO2_IO20 0x401F818CU, 0x5U, 0, 0, 0x401F837CU
#define IOMUXC_GPIO_B1_04_CSU_CSU_ALARM_AUT02 0x401F818CU, 0x6U, 0, 0, 0x401F837CU
#define IOMUXC_GPIO_B1_05_LCD_DATA17 0x401F8190U, 0x0U, 0, 0, 0x401F8380U
#define IOMUXC_GPIO_B1_05_LPSPI4_SDI 0x401F8190U, 0x1U, 0x401F8524U, 0x1U, 0x401F8380U
@ -829,7 +813,6 @@
#define IOMUXC_GPIO_B1_05_ENET_RX_DATA01 0x401F8190U, 0x3U, 0x401F8438U, 0x1U, 0x401F8380U
#define IOMUXC_GPIO_B1_05_FLEXIO2_FLEXIO21 0x401F8190U, 0x4U, 0, 0, 0x401F8380U
#define IOMUXC_GPIO_B1_05_GPIO2_IO21 0x401F8190U, 0x5U, 0, 0, 0x401F8380U
#define IOMUXC_GPIO_B1_05_CSU_CSU_ALARM_AUT01 0x401F8190U, 0x6U, 0, 0, 0x401F8380U
#define IOMUXC_GPIO_B1_06_LCD_DATA18 0x401F8194U, 0x0U, 0, 0, 0x401F8384U
#define IOMUXC_GPIO_B1_06_LPSPI4_SDO 0x401F8194U, 0x1U, 0x401F8528U, 0x1U, 0x401F8384U
@ -837,7 +820,6 @@
#define IOMUXC_GPIO_B1_06_ENET_RX_EN 0x401F8194U, 0x3U, 0x401F843CU, 0x1U, 0x401F8384U
#define IOMUXC_GPIO_B1_06_FLEXIO2_FLEXIO22 0x401F8194U, 0x4U, 0, 0, 0x401F8384U
#define IOMUXC_GPIO_B1_06_GPIO2_IO22 0x401F8194U, 0x5U, 0, 0, 0x401F8384U
#define IOMUXC_GPIO_B1_06_CSU_CSU_ALARM_AUT00 0x401F8194U, 0x6U, 0, 0, 0x401F8384U
#define IOMUXC_GPIO_B1_07_LCD_DATA19 0x401F8198U, 0x0U, 0, 0, 0x401F8388U
#define IOMUXC_GPIO_B1_07_LPSPI4_SCK 0x401F8198U, 0x1U, 0x401F8520U, 0x1U, 0x401F8388U
@ -845,7 +827,6 @@
#define IOMUXC_GPIO_B1_07_ENET_TX_DATA00 0x401F8198U, 0x3U, 0, 0, 0x401F8388U
#define IOMUXC_GPIO_B1_07_FLEXIO2_FLEXIO23 0x401F8198U, 0x4U, 0, 0, 0x401F8388U
#define IOMUXC_GPIO_B1_07_GPIO2_IO23 0x401F8198U, 0x5U, 0, 0, 0x401F8388U
#define IOMUXC_GPIO_B1_07_CSU_CSU_INT_DEB 0x401F8198U, 0x6U, 0, 0, 0x401F8388U
#define IOMUXC_GPIO_B1_08_LCD_DATA20 0x401F819CU, 0x0U, 0, 0, 0x401F838CU
#define IOMUXC_GPIO_B1_08_QTIMER1_TIMER3 0x401F819CU, 0x1U, 0, 0, 0x401F838CU
@ -969,7 +950,6 @@
#define IOMUXC_GPIO_SD_B1_01_SAI1_TX_DATA02 0x401F81D8U, 0x3U, 0x401F859CU, 0x0U, 0x401F83C8U
#define IOMUXC_GPIO_SD_B1_01_LPUART4_RX 0x401F81D8U, 0x4U, 0x401F8540U, 0x0U, 0x401F83C8U
#define IOMUXC_GPIO_SD_B1_01_GPIO3_IO01 0x401F81D8U, 0x5U, 0, 0, 0x401F83C8U
#define IOMUXC_GPIO_SD_B1_01_CCM_DI0_EXT_CLK 0x401F81D8U, 0x6U, 0, 0, 0x401F83C8U
#define IOMUXC_GPIO_SD_B1_02_USDHC2_DATA1 0x401F81DCU, 0x0U, 0x401F85ECU, 0x0U, 0x401F83CCU
#define IOMUXC_GPIO_SD_B1_02_FLEXSPIB_DATA01 0x401F81DCU, 0x1U, 0x401F84BCU, 0x0U, 0x401F83CCU
@ -1015,7 +995,6 @@
#define IOMUXC_GPIO_SD_B1_07_SAI1_TX_DATA00 0x401F81F0U, 0x3U, 0, 0, 0x401F83E0U
#define IOMUXC_GPIO_SD_B1_07_LPSPI2_SCK 0x401F81F0U, 0x4U, 0x401F8500U, 0x0U, 0x401F83E0U
#define IOMUXC_GPIO_SD_B1_07_GPIO3_IO07 0x401F81F0U, 0x5U, 0, 0, 0x401F83E0U
#define IOMUXC_GPIO_SD_B1_07_CCM_REF_EN_B 0x401F81F0U, 0x6U, 0, 0, 0x401F83E0U
#define IOMUXC_GPIO_SD_B1_08_USDHC2_DATA4 0x401F81F4U, 0x0U, 0x401F85F8U, 0x0U, 0x401F83E4U
#define IOMUXC_GPIO_SD_B1_08_FLEXSPIA_DATA00 0x401F81F4U, 0x1U, 0x401F84A8U, 0x0U, 0x401F83E4U
@ -1038,7 +1017,6 @@
#define IOMUXC_GPIO_SD_B1_10_LPI2C2_SDA 0x401F81FCU, 0x3U, 0x401F84D8U, 0x0U, 0x401F83ECU
#define IOMUXC_GPIO_SD_B1_10_LPSPI2_PCS2 0x401F81FCU, 0x4U, 0, 0, 0x401F83ECU
#define IOMUXC_GPIO_SD_B1_10_GPIO3_IO10 0x401F81FCU, 0x5U, 0, 0, 0x401F83ECU
#define IOMUXC_GPIO_SD_B1_10_SRC_SYSTEM_RESET 0x401F81FCU, 0x6U, 0, 0, 0x401F83ECU
#define IOMUXC_GPIO_SD_B1_11_USDHC2_DATA7 0x401F8200U, 0x0U, 0x401F8604U, 0x0U, 0x401F83F0U
#define IOMUXC_GPIO_SD_B1_11_FLEXSPIA_DATA03 0x401F8200U, 0x1U, 0x401F84B4U, 0x0U, 0x401F83F0U
@ -1046,7 +1024,6 @@
#define IOMUXC_GPIO_SD_B1_11_LPI2C2_SCL 0x401F8200U, 0x3U, 0x401F84D4U, 0x0U, 0x401F83F0U
#define IOMUXC_GPIO_SD_B1_11_LPSPI2_PCS3 0x401F8200U, 0x4U, 0, 0, 0x401F83F0U
#define IOMUXC_GPIO_SD_B1_11_GPIO3_IO11 0x401F8200U, 0x5U, 0, 0, 0x401F83F0U
#define IOMUXC_GPIO_SD_B1_11_SRC_EARLY_RESET 0x401F8200U, 0x6U, 0, 0, 0x401F83F0U
#define IOMUXC_GPR_SAIMCLK_LOWBITMASK (0x7U)
#define IOMUXC_GPR_SAIMCLK_HIGHBITMASK (0x3U)
@ -1062,16 +1039,16 @@ typedef enum _iomuxc_gpr_mode
kIOMUXC_GPR_SAI3MClkOutputDir = IOMUXC_GPR_GPR1_SAI3_MCLK_DIR_MASK,
kIOMUXC_GPR_ExcMonitorSlavErrResponse = IOMUXC_GPR_GPR1_EXC_MON_MASK,
kIOMUXC_GPR_ENETIpgClkOn = IOMUXC_GPR_GPR1_ENET_IPG_CLK_S_EN_MASK,
kIOMUXC_GPR_AHBClockEnable = IOMUXC_GPR_GPR1_CM7_FORCE_HCLK_EN_MASK,
} iomuxc_gpr_mode_t;
kIOMUXC_GPR_AHBClockEnable = (int)IOMUXC_GPR_GPR1_CM7_FORCE_HCLK_EN_MASK,
} iomuxc_gpr_mode_t;
typedef enum _iomuxc_gpr_saimclk
{
kIOMUXC_GPR_SAI1MClk1Sel = IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL_SHIFT,
kIOMUXC_GPR_SAI1MClk2Sel = IOMUXC_GPR_GPR1_SAI1_MCLK2_SEL_SHIFT,
kIOMUXC_GPR_SAI1MClk3Sel = IOMUXC_GPR_GPR1_SAI1_MCLK3_SEL_SHIFT,
kIOMUXC_GPR_SAI2MClk3Sel = IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL_SHIFT,
kIOMUXC_GPR_SAI3MClk3Sel = IOMUXC_GPR_GPR1_SAI3_MCLK3_SEL_SHIFT,
kIOMUXC_GPR_SAI1MClk3Sel = IOMUXC_GPR_GPR1_SAI1_MCLK3_SEL_SHIFT,
kIOMUXC_GPR_SAI2MClk3Sel = IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL_SHIFT,
kIOMUXC_GPR_SAI3MClk3Sel = IOMUXC_GPR_GPR1_SAI3_MCLK3_SEL_SHIFT,
} iomuxc_gpr_saimclk_t;
typedef enum _iomuxc_mqs_pwm_oversample_rate
@ -1164,11 +1141,13 @@ static inline void IOMUXC_SetPinConfig(uint32_t muxRegister,
*/
static inline void IOMUXC_EnableMode(IOMUXC_GPR_Type *base, uint32_t mode, bool enable)
{
uint32_t gpr = base->GPR1 & 0xFFF;
mode &= ~(IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL_MASK | IOMUXC_GPR_GPR1_SAI1_MCLK2_SEL_MASK |
IOMUXC_GPR_GPR1_SAI1_MCLK3_SEL_MASK | IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL_MASK |
IOMUXC_GPR_GPR1_SAI3_MCLK3_SEL_MASK);
if (enable)
{
base->GPR1 = mode | gpr;
base->GPR1 |= mode;
}
else
{
@ -1190,17 +1169,17 @@ static inline void IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR_Type *base, iomuxc_gp
if (mclk > kIOMUXC_GPR_SAI1MClk2Sel)
{
gpr = base->GPR1 & ~(IOMUXC_GPR_SAIMCLK_HIGHBITMASK << mclk);
base->GPR1 = ((clkSrc & IOMUXC_GPR_SAIMCLK_HIGHBITMASK) << mclk) | gpr;
base->GPR1 = ((clkSrc & IOMUXC_GPR_SAIMCLK_HIGHBITMASK) << mclk) | gpr;
}
else
{
gpr = base->GPR1 & ~(IOMUXC_GPR_SAIMCLK_LOWBITMASK << mclk);
base->GPR1 = ((clkSrc & IOMUXC_GPR_SAIMCLK_LOWBITMASK) << mclk) | gpr;
base->GPR1 = ((clkSrc & IOMUXC_GPR_SAIMCLK_LOWBITMASK) << mclk) | gpr;
}
}
/*!
* @brief Enters or exit MQS software reset.
* @brief Enters or exit MQS software reset.
*
* @param base The IOMUXC GPR base address.
* @param enable Enter or exit MQS software reset.
@ -1209,17 +1188,16 @@ static inline void IOMUXC_MQSEnterSoftwareReset(IOMUXC_GPR_Type *base, bool enab
{
if (enable)
{
base->GPR2 |= IOMUXC_GPR_GPR2_MQS_SW_RST_MASK;
base->GPR2 |= IOMUXC_GPR_GPR2_MQS_SW_RST_MASK;
}
else
{
base->GPR2 &= ~IOMUXC_GPR_GPR2_MQS_SW_RST_MASK;
base->GPR2 &= ~IOMUXC_GPR_GPR2_MQS_SW_RST_MASK;
}
}
/*!
* @brief Enables or disables MQS.
* @brief Enables or disables MQS.
*
* @param base The IOMUXC GPR base address.
* @param enable Enable or disable the MQS.
@ -1228,16 +1206,16 @@ static inline void IOMUXC_MQSEnable(IOMUXC_GPR_Type *base, bool enable)
{
if (enable)
{
base->GPR2 |= IOMUXC_GPR_GPR2_MQS_EN_MASK;
base->GPR2 |= IOMUXC_GPR_GPR2_MQS_EN_MASK;
}
else
{
base->GPR2 &= ~IOMUXC_GPR_GPR2_MQS_EN_MASK;
base->GPR2 &= ~IOMUXC_GPR_GPR2_MQS_EN_MASK;
}
}
/*!
* @brief Configure MQS PWM oversampling rate compared with mclk and divider ratio control for mclk from hmclk.
* @brief Configure MQS PWM oversampling rate compared with mclk and divider ratio control for mclk from hmclk.
*
* @param base The IOMUXC GPR base address.
* @param rate The MQS PWM oversampling rate, refer to "iomuxc_mqs_pwm_oversample_rate_t".
@ -1247,7 +1225,7 @@ static inline void IOMUXC_MQSEnable(IOMUXC_GPR_Type *base, bool enable)
static inline void IOMUXC_MQSConfig(IOMUXC_GPR_Type *base, iomuxc_mqs_pwm_oversample_rate_t rate, uint8_t divider)
{
uint32_t gpr = base->GPR2 & ~(IOMUXC_GPR_GPR2_MQS_OVERSAMPLE_MASK | IOMUXC_GPR_GPR2_MQS_CLK_DIV_MASK);
base->GPR2 = gpr | IOMUXC_GPR_GPR2_MQS_OVERSAMPLE(rate) | IOMUXC_GPR_GPR2_MQS_CLK_DIV(divider);
}
@ -1260,4 +1238,3 @@ static inline void IOMUXC_MQSConfig(IOMUXC_GPR_Type *base, iomuxc_mqs_pwm_oversa
/*! @}*/
#endif /* _FSL_IOMUXC_H_ */

122
ext/hal/nxp/mcux/devices/MIMXRT1052/system_MIMXRT1052.c
View file

@ -1,17 +1,19 @@
/*
** ###################################################################
** Processors: MIMXRT1052CVL5A
** MIMXRT1052DVL6A
** Processors: MIMXRT1052CVJ5B
** MIMXRT1052CVL5B
** MIMXRT1052DVJ6B
** MIMXRT1052DVL6B
**
** Compilers: Keil ARM C/C++ Compiler
** Freescale C/C++ for Embedded ARM
** Compilers: Freescale C/C++ for Embedded ARM
** GNU C Compiler
** IAR ANSI C/C++ Compiler for ARM
** Keil ARM C/C++ Compiler
** MCUXpresso Compiler
**
** Reference manual: IMXRT1050RM Rev.C, 08/2017
** Version: rev. 0.1, 2017-01-10
** Build: b170927
** Reference manual: IMXRT1050RM Rev.2.1, 12/2018
** Version: rev. 1.2, 2018-11-27
** Build: b181205
**
** Abstract:
** Provides a system configuration function and a global variable that
@ -19,31 +21,10 @@
** the oscillator (PLL) that is part of the microcontroller device.
**
** Copyright 2016 Freescale Semiconductor, Inc.
** Copyright 2016-2017 NXP
** Redistribution and use in source and binary forms, with or without modification,
** are permitted provided that the following conditions are met:
** Copyright 2016-2018 NXP
** All rights reserved.
**
** 1. Redistributions of source code must retain the above copyright notice, this list
** of conditions and the following disclaimer.
**
** 2. Redistributions in binary form must reproduce the above copyright notice, this
** list of conditions and the following disclaimer in the documentation and/or
** other materials provided with the distribution.
**
** 3. Neither the name of the copyright holder nor the names of its
** contributors may be used to endorse or promote products derived from this
** software without specific prior written permission.
**
** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
** SPDX-License-Identifier: BSD-3-Clause
**
** http: www.nxp.com
** mail: support@nxp.com
@ -51,14 +32,22 @@
** Revisions:
** - rev. 0.1 (2017-01-10)
** Initial version.
** - rev. 1.0 (2018-09-21)
** Update interrupt vector table and dma request source.
** Update register BEE_ADDR_OFFSET1's bitfield name to ADDR_OFFSET1.
** Split GPIO_COMBINED_IRQS to GPIO_COMBINED_LOW_IRQS and GPIO_COMBINED_HIGH_IRQS.
** - rev. 1.1 (2018-11-16)
** Update header files to align with IMXRT1050RM Rev.1.
** - rev. 1.2 (2018-11-27)
** Update header files to align with IMXRT1050RM Rev.2.1.
**
** ###################################################################
*/
/*!
* @file MIMXRT1052
* @version 0.1
* @date 2017-01-10
* @version 1.2
* @date 2018-11-27
* @brief Device specific configuration file for MIMXRT1052 (implementation file)
*
* Provides a system configuration function and a global variable that contains
@ -86,6 +75,15 @@ void SystemInit (void) {
SCB->CPACR |= ((3UL << 10*2) | (3UL << 11*2)); /* set CP10, CP11 Full Access */
#endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */
#if defined(__MCUXPRESSO)
extern uint32_t g_pfnVectors[]; // Vector table defined in startup code
SCB->VTOR = (uint32_t)g_pfnVectors;
#endif
/* Disable Watchdog Power Down Counter */
WDOG1->WMCR &= ~WDOG_WMCR_PDE_MASK;
WDOG2->WMCR &= ~WDOG_WMCR_PDE_MASK;
/* Watchdog disable */
#if (DISABLE_WDOG)
@ -110,12 +108,17 @@ void SystemInit (void) {
/* Enable instruction and data caches */
#if defined(__ICACHE_PRESENT) && __ICACHE_PRESENT
SCB_EnableICache();
if (SCB_CCR_IC_Msk != (SCB_CCR_IC_Msk & SCB->CCR)) {
SCB_EnableICache();
}
#endif
#if defined(__DCACHE_PRESENT) && __DCACHE_PRESENT
SCB_EnableDCache();
if (SCB_CCR_DC_Msk != (SCB_CCR_DC_Msk & SCB->CCR)) {
SCB_EnableDCache();
}
#endif
SystemInitHook();
}
/* ----------------------------------------------------------------------------
@ -135,15 +138,26 @@ void SystemCoreClockUpdate (void) {
{
/* Pll3_sw_clk ---> Periph_clk2_clk ---> Periph_clk */
case CCM_CBCMR_PERIPH_CLK2_SEL(0U):
freq = (24000000UL * ((CCM_ANALOG->PLL_USB1 & CCM_ANALOG_PLL_USB1_DIV_SELECT_MASK) ? 22U : 20U));
if(CCM_ANALOG->PLL_USB1 & CCM_ANALOG_PLL_USB1_BYPASS_MASK)
{
freq = (((CCM_ANALOG->PLL_USB1 & CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_MASK) >> CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_SHIFT) == 0U) ?
CPU_XTAL_CLK_HZ : CPU_CLK1_HZ;
}
else
{
freq = (CPU_XTAL_CLK_HZ * ((CCM_ANALOG->PLL_USB1 & CCM_ANALOG_PLL_USB1_DIV_SELECT_MASK) ? 22U : 20U));
}
break;
/* Osc_clk ---> Periph_clk2_clk ---> Periph_clk */
case CCM_CBCMR_PERIPH_CLK2_SEL(1U):
freq = 24000000UL;
freq = CPU_XTAL_CLK_HZ;
break;
case CCM_CBCMR_PERIPH_CLK2_SEL(2U):
freq = (((CCM_ANALOG->PLL_SYS & CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_MASK) >> CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_SHIFT) == 0U) ?
CPU_XTAL_CLK_HZ : CPU_CLK1_HZ;
case CCM_CBCMR_PERIPH_CLK2_SEL(3U):
default:
freq = 0U;
@ -155,11 +169,29 @@ void SystemCoreClockUpdate (void) {
/* Pre_Periph_clk ---> Periph_clk */
else
{
PLL1MainClock = ((24000000UL * ((CCM_ANALOG->PLL_ARM & CCM_ANALOG_PLL_ARM_DIV_SELECT_MASK) >>
CCM_ANALOG_PLL_ARM_DIV_SELECT_SHIFT)) >> 1U);
/* check if pll is bypassed */
if(CCM_ANALOG->PLL_ARM & CCM_ANALOG_PLL_ARM_BYPASS_MASK)
{
PLL1MainClock = (((CCM_ANALOG->PLL_ARM & CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_MASK) >> CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_SHIFT) == 0U) ?
CPU_XTAL_CLK_HZ : CPU_CLK1_HZ;
}
else
{
PLL1MainClock = ((CPU_XTAL_CLK_HZ * ((CCM_ANALOG->PLL_ARM & CCM_ANALOG_PLL_ARM_DIV_SELECT_MASK) >>
CCM_ANALOG_PLL_ARM_DIV_SELECT_SHIFT)) >> 1U);
}
PLL2MainClock = (24000000UL * ((CCM_ANALOG->PLL_SYS & CCM_ANALOG_PLL_SYS_DIV_SELECT_MASK) ? 22U : 20U));
PLL2MainClock += ((uint64_t)24000000UL * ((uint64_t)(CCM_ANALOG->PLL_SYS_NUM))) / ((uint64_t)(CCM_ANALOG->PLL_SYS_DENOM));
/* check if pll is bypassed */
if(CCM_ANALOG->PLL_SYS & CCM_ANALOG_PLL_SYS_BYPASS_MASK)
{
PLL2MainClock = (((CCM_ANALOG->PLL_SYS & CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_MASK) >> CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_SHIFT) == 0U) ?
CPU_XTAL_CLK_HZ : CPU_CLK1_HZ;
}
else
{
PLL2MainClock = (CPU_XTAL_CLK_HZ * ((CCM_ANALOG->PLL_SYS & CCM_ANALOG_PLL_SYS_DIV_SELECT_MASK) ? 22U : 20U));
}
PLL2MainClock += ((uint64_t)CPU_XTAL_CLK_HZ * ((uint64_t)(CCM_ANALOG->PLL_SYS_NUM))) / ((uint64_t)(CCM_ANALOG->PLL_SYS_DENOM));
switch (CCM->CBCMR & CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK)
@ -193,3 +225,11 @@ void SystemCoreClockUpdate (void) {
SystemCoreClock = (freq / (((CCM->CBCDR & CCM_CBCDR_AHB_PODF_MASK) >> CCM_CBCDR_AHB_PODF_SHIFT) + 1U));
}
/* ----------------------------------------------------------------------------
-- SystemInitHook()
---------------------------------------------------------------------------- */
__attribute__ ((weak)) void SystemInitHook (void) {
/* Void implementation of the weak function. */
}

70
ext/hal/nxp/mcux/devices/MIMXRT1052/system_MIMXRT1052.h
View file

@ -1,17 +1,19 @@
/*
** ###################################################################
** Processors: MIMXRT1052CVL5A
** MIMXRT1052DVL6A
** Processors: MIMXRT1052CVJ5B
** MIMXRT1052CVL5B
** MIMXRT1052DVJ6B
** MIMXRT1052DVL6B
**
** Compilers: Keil ARM C/C++ Compiler
** Freescale C/C++ for Embedded ARM
** Compilers: Freescale C/C++ for Embedded ARM
** GNU C Compiler
** IAR ANSI C/C++ Compiler for ARM
** Keil ARM C/C++ Compiler
** MCUXpresso Compiler
**
** Reference manual: IMXRT1050RM Rev.C, 08/2017
** Version: rev. 0.1, 2017-01-10
** Build: b170927
** Reference manual: IMXRT1050RM Rev.2.1, 12/2018
** Version: rev. 1.2, 2018-11-27
** Build: b181205
**
** Abstract:
** Provides a system configuration function and a global variable that
@ -19,31 +21,10 @@
** the oscillator (PLL) that is part of the microcontroller device.
**
** Copyright 2016 Freescale Semiconductor, Inc.
** Copyright 2016-2017 NXP
** Redistribution and use in source and binary forms, with or without modification,
** are permitted provided that the following conditions are met:
** Copyright 2016-2018 NXP
** All rights reserved.
**
** 1. Redistributions of source code must retain the above copyright notice, this list
** of conditions and the following disclaimer.
**
** 2. Redistributions in binary form must reproduce the above copyright notice, this
** list of conditions and the following disclaimer in the documentation and/or
** other materials provided with the distribution.
**
** 3. Neither the name of the copyright holder nor the names of its
** contributors may be used to endorse or promote products derived from this
** software without specific prior written permission.
**
** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
** SPDX-License-Identifier: BSD-3-Clause
**
** http: www.nxp.com
** mail: support@nxp.com
@ -51,14 +32,22 @@
** Revisions:
** - rev. 0.1 (2017-01-10)
** Initial version.
** - rev. 1.0 (2018-09-21)
** Update interrupt vector table and dma request source.
** Update register BEE_ADDR_OFFSET1's bitfield name to ADDR_OFFSET1.
** Split GPIO_COMBINED_IRQS to GPIO_COMBINED_LOW_IRQS and GPIO_COMBINED_HIGH_IRQS.
** - rev. 1.1 (2018-11-16)
** Update header files to align with IMXRT1050RM Rev.1.
** - rev. 1.2 (2018-11-27)
** Update header files to align with IMXRT1050RM Rev.2.1.
**
** ###################################################################
*/
/*!
* @file MIMXRT1052
* @version 0.1
* @date 2017-01-10
* @version 1.2
* @date 2018-11-27
* @brief Device specific configuration file for MIMXRT1052 (header file)
*
* Provides a system configuration function and a global variable that contains
@ -84,6 +73,9 @@ extern "C" {
#define CPU_XTAL_CLK_HZ 24000000UL /* Value of the external crystal or oscillator clock frequency in Hz */
#define CPU_CLK1_HZ 0UL /* Value of the CLK1 (select the CLK1_N/CLK1_P as source) frequency in Hz */
/* If CLOCK1_P,CLOCK1_N is choose as the pll bypass clock source, please implement the CLKPN_FREQ define, otherwise 0 will be returned. */
#define DEFAULT_SYSTEM_CLOCK 528000000UL /* Default System clock value */
@ -116,6 +108,18 @@ void SystemInit (void);
*/
void SystemCoreClockUpdate (void);
/**
* @brief SystemInit function hook.
*
* This weak function allows to call specific initialization code during the
* SystemInit() execution.This can be used when an application specific code needs
* to be called as close to the reset entry as possible (for example the Multicore
* Manager MCMGR_EarlyInit() function call).
* NOTE: No global r/w variables can be used in this hook function because the
* initialization of these variables happens after this function.
*/
void SystemInitHook (void);
#ifdef __cplusplus
}
#endif

853
ext/hal/nxp/mcux/devices/MIMXRT1061/MIMXRT1061.h
View file

File diff suppressed because it is too large Load diff

445
ext/hal/nxp/mcux/devices/MIMXRT1061/MIMXRT1061.xml
View file

@ -6,6 +6,7 @@
<description>MIMXRT1061DVL6A</description>
<licenseText>
Copyright 2016-2018 NXP
All rights reserved.
SPDX-License-Identifier: BSD-3-Clause
</licenseText>
@ -8097,13 +8098,6 @@ SPDX-License-Identifier: BSD-3-Clause
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CM7_INIT_VTOR</name>
<description>Vector table offset register out of reset</description>
<bitOffset>7</bitOffset>
<bitWidth>25</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
@ -8729,145 +8723,6 @@ SPDX-License-Identifier: BSD-3-Clause
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>Reserved</name>
<description>Reserved</description>
<bitOffset>3</bitOffset>
<bitWidth>29</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>OCRAM_MAGIC_ADDR</name>
<description>OCRAM Magic Address Register</description>
<addressOffset>0x4</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>OCRAM_WR_RD_SEL</name>
<description>OCRAM Write Read Select</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>OCRAM_WR_RD_SEL_0</name>
<description>When OCRAM read access hits magic address, it will generate interrupt.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>OCRAM_WR_RD_SEL_1</name>
<description>When OCRAM write access hits magic address, it will generate interrupt.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>OCRAM_MAGIC_ADDR</name>
<description>OCRAM Magic Address</description>
<bitOffset>1</bitOffset>
<bitWidth>16</bitWidth>
<access>read-write</access>
</field>
<field>
<name>Reserved</name>
<description>Reserved</description>
<bitOffset>17</bitOffset>
<bitWidth>15</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>DTCM_MAGIC_ADDR</name>
<description>DTCM Magic Address Register</description>
<addressOffset>0x8</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>DTCM_WR_RD_SEL</name>
<description>DTCM Write Read Select</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>DTCM_WR_RD_SEL_0</name>
<description>When DTCM read access hits magic address, it will generate interrupt.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>DTCM_WR_RD_SEL_1</name>
<description>When DTCM write access hits magic address, it will generate interrupt.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DTCM_MAGIC_ADDR</name>
<description>DTCM Magic Address</description>
<bitOffset>1</bitOffset>
<bitWidth>16</bitWidth>
<access>read-write</access>
</field>
<field>
<name>Reserved</name>
<description>Reserved</description>
<bitOffset>17</bitOffset>
<bitWidth>15</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>ITCM_MAGIC_ADDR</name>
<description>ITCM Magic Address Register</description>
<addressOffset>0xC</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>ITCM_WR_RD_SEL</name>
<description>ITCM Write Read Select</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>ITCM_WR_RD_SEL_0</name>
<description>When ITCM read access hits magic address, it will generate interrupt.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ITCM_WR_RD_SEL_1</name>
<description>When ITCM write access hits magic address, it will generate interrupt.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ITCM_MAGIC_ADDR</name>
<description>ITCM Magic Address</description>
<bitOffset>1</bitOffset>
<bitWidth>16</bitWidth>
<access>read-write</access>
</field>
<field>
<name>Reserved</name>
<description>Reserved</description>
<bitOffset>17</bitOffset>
<bitWidth>15</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
@ -8879,66 +8734,6 @@ SPDX-License-Identifier: BSD-3-Clause
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>ITCM_MAM_STATUS</name>
<description>ITCM Magic Address Match Status</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<modifiedWriteValues>oneToClear</modifiedWriteValues>
<enumeratedValues>
<enumeratedValue>
<name>ITCM_MAM_STATUS_0</name>
<description>ITCM did not access magic address.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ITCM_MAM_STATUS_1</name>
<description>ITCM accessed magic address.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DTCM_MAM_STATUS</name>
<description>DTCM Magic Address Match Status</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<modifiedWriteValues>oneToClear</modifiedWriteValues>
<enumeratedValues>
<enumeratedValue>
<name>DTCM_MAM_STATUS_0</name>
<description>DTCM did not access magic address.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>DTCM_MAM_STATUS_1</name>
<description>DTCM accessed magic address.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>OCRAM_MAM_STATUS</name>
<description>OCRAM Magic Address Match Status</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<modifiedWriteValues>oneToClear</modifiedWriteValues>
<enumeratedValues>
<enumeratedValue>
<name>OCRAM_MAM_STATUS_0</name>
<description>OCRAM did not access magic address.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>OCRAM_MAM_STATUS_1</name>
<description>OCRAM accessed magic address.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ITCM_ERR_STATUS</name>
<description>ITCM Access Error Status</description>
@ -8999,13 +8794,6 @@ SPDX-License-Identifier: BSD-3-Clause
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>Reserved</name>
<description>Reserved</description>
<bitOffset>6</bitOffset>
<bitWidth>26</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
@ -9017,63 +8805,6 @@ SPDX-License-Identifier: BSD-3-Clause
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>ITCM_MAM_STAT_EN</name>
<description>ITCM Magic Address Match Status Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>ITCM_MAM_STAT_EN_0</name>
<description>Masked</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ITCM_MAM_STAT_EN_1</name>
<description>Enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DTCM_MAM_STAT_EN</name>
<description>DTCM Magic Address Match Status Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>DTCM_MAM_STAT_EN_0</name>
<description>Masked</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>DTCM_MAM_STAT_EN_1</name>
<description>Enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>OCRAM_MAM_STAT_EN</name>
<description>OCRAM Magic Address Match Status Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>OCRAM_MAM_STAT_EN_0</name>
<description>Masked</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>OCRAM_MAM_STAT_EN_1</name>
<description>Enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ITCM_ERR_STAT_EN</name>
<description>ITCM Access Error Status Enable</description>
@ -9131,13 +8862,6 @@ SPDX-License-Identifier: BSD-3-Clause
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>Reserved</name>
<description>Reserved</description>
<bitOffset>6</bitOffset>
<bitWidth>26</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
@ -9149,63 +8873,6 @@ SPDX-License-Identifier: BSD-3-Clause
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>ITCM_MAM_SIG_EN</name>
<description>ITCM Magic Address Match Interrupt Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>ITCM_MAM_SIG_EN_0</name>
<description>Masked</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ITCM_MAM_SIG_EN_1</name>
<description>Enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DTCM_MAM_SIG_EN</name>
<description>DTCM Magic Address Match Interrupt Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>DTCM_MAM_SIG_EN_0</name>
<description>Masked</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>DTCM_MAM_SIG_EN_1</name>
<description>Enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>OCRAM_MAM_SIG_EN</name>
<description>OCRAM Magic Address Match Interrupt Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>OCRAM_MAM_SIG_EN_0</name>
<description>Masked</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>OCRAM_MAM_SIG_EN_1</name>
<description>Enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ITCM_ERR_SIG_EN</name>
<description>ITCM Access Error Interrupt Enable</description>
@ -9263,13 +8930,6 @@ SPDX-License-Identifier: BSD-3-Clause
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>Reserved</name>
<description>Reserved</description>
<bitOffset>6</bitOffset>
<bitWidth>26</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
</registers>
@ -78935,6 +78595,94 @@ SPDX-License-Identifier: BSD-3-Clause
</field>
</fields>
</register>
<register>
<name>DBG1</name>
<description>Debug 1 register</description>
<addressOffset>0x58</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x10000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CFSM</name>
<description>CAN Finite State Machine</description>
<bitOffset>0</bitOffset>
<bitWidth>6</bitWidth>
<access>read-only</access>
</field>
<field>
<name>CBN</name>
<description>CAN Bit Number</description>
<bitOffset>24</bitOffset>
<bitWidth>5</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>DBG2</name>
<description>Debug 2 register</description>
<addressOffset>0x5C</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>RMP</name>
<description>Rx Matching Pointer</description>
<bitOffset>0</bitOffset>
<bitWidth>7</bitWidth>
<access>read-only</access>
</field>
<field>
<name>MPP</name>
<description>Matching Process in Progress</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>MPP_0</name>
<description>No matching process ongoing.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>MPP_1</name>
<description>Matching process is in progress.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TAP</name>
<description>Tx Arbitration Pointer</description>
<bitOffset>8</bitOffset>
<bitWidth>7</bitWidth>
<access>read-only</access>
</field>
<field>
<name>APP</name>
<description>Arbitration Process in Progress</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>APP_0</name>
<description>No matching process ongoing.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>APP_1</name>
<description>Matching process is in progress.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<dim>64</dim>
<dimIncrement>0x4</dimIncrement>
@ -140288,13 +140036,6 @@ SPDX-License-Identifier: BSD-3-Clause
<bitWidth>2</bitWidth>
<access>read-only</access>
</field>
<field>
<name>SRK</name>
<description>SRK</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>ROM_PATCH</name>
<description>ROM_PATCH</description>
@ -140592,7 +140333,7 @@ SPDX-License-Identifier: BSD-3-Clause
</register>
<register>
<name>ANA0</name>
<description>Value of OTP Bank1 Word5 (Analog Info.)</description>
<description>Value of OTP Bank1 Word5 (Memory Related Info.)</description>
<addressOffset>0x4D0</addressOffset>
<size>32</size>
<access>read-write</access>
@ -140610,7 +140351,7 @@ SPDX-License-Identifier: BSD-3-Clause
</register>
<register>
<name>ANA1</name>
<description>Value of OTP Bank1 Word6 (Analog Info.)</description>
<description>Value of OTP Bank1 Word6 (General Purpose Customer Defined Info.)</description>
<addressOffset>0x4E0</addressOffset>
<size>32</size>
<access>read-write</access>
@ -140628,7 +140369,7 @@ SPDX-License-Identifier: BSD-3-Clause
</register>
<register>
<name>ANA2</name>
<description>Value of OTP Bank1 Word7 (Analog Info.)</description>
<description>Value of OTP Bank1 Word7 (General Purpose Customer Defined Info.)</description>
<addressOffset>0x4F0</addressOffset>
<size>32</size>
<access>read-write</access>
@ -141006,7 +140747,7 @@ SPDX-License-Identifier: BSD-3-Clause
</register>
<register>
<name>MAC2</name>
<description>Value of OTP Bank4 Word4 (MAC Address)</description>
<description>Value of OTP Bank4 Word4 (MAC2 Address)</description>
<addressOffset>0x640</addressOffset>
<size>32</size>
<access>read-write</access>

17
ext/hal/nxp/mcux/devices/MIMXRT1061/MIMXRT1061_features.h
View file

@ -1,13 +1,14 @@
/*
** ###################################################################
** Version: rev. 0.1, 2017-01-10
** Build: b180806
** Version: rev. 1.0, 2018-11-16
** Build: b181120
**
** Abstract:
** Chip specific module features.
**
** Copyright 2016 Freescale Semiconductor, Inc.
** Copyright 2016-2018 NXP
** All rights reserved.
**
** SPDX-License-Identifier: BSD-3-Clause
**
@ -17,6 +18,8 @@
** Revisions:
** - rev. 0.1 (2017-01-10)
** Initial version.
** - rev. 1.0 (2018-11-16)
** Update feature files to align with IMXRT1060RM Rev.0.
**
** ###################################################################
*/
@ -67,7 +70,7 @@
/* @brief I2S availability on the SoC. */
#define FSL_FEATURE_SOC_I2S_COUNT (3)
/* @brief IGPIO availability on the SoC. */
#define FSL_FEATURE_SOC_IGPIO_COUNT (10)
#define FSL_FEATURE_SOC_IGPIO_COUNT (9)
/* @brief IOMUXC availability on the SoC. */
#define FSL_FEATURE_SOC_IOMUXC_COUNT (1)
/* @brief IOMUXC_GPR availability on the SoC. */
@ -180,6 +183,12 @@
((x) == CAN3 ? (0) : (-1))))
/* @brief Is affected by errata with ID 5641 (Module does not transmit a message that is enabled to be transmitted at a specific moment during the arbitration process). */
#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641 (0)
/* @brief Is affected by errata with ID 5829 (FlexCAN: FlexCAN does not transmit a message that is enabled to be transmitted in a specific moment during the arbitration process). */
#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_5829 (1)
/* @brief Is affected by errata with ID 6032 (FlexCAN: A frame with wrong ID or payload is transmitted into the CAN bus when the Message Buffer under transmission is either aborted or deactivated while the CAN bus is in the Bus Idle state). */
#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_6032 (1)
/* @brief Is affected by errata with ID 9595 (FlexCAN: Corrupt frame possible if the Freeze Mode or the Low-Power Mode are entered during a Bus-Off state). */
#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_9595 (1)
/* @brief Has CAN with Flexible Data rate (CAN FD) protocol. */
#define FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE (1)
/* @brief CAN instance support Flexible Data rate (CAN FD) protocol. */
@ -277,7 +286,7 @@
/* FLEXRAM module features */
/* @brief Bank size */
#define FSL_FEATURE_FLEXRAM_INTERNAL_RAM_BANK_SIZE (32 * 1024)
#define FSL_FEATURE_FLEXRAM_INTERNAL_RAM_BANK_SIZE (32768)
/* @brief Total Bank numbers */
#define FSL_FEATURE_FLEXRAM_INTERNAL_RAM_TOTAL_BANK_NUMBERS (16)

37
ext/hal/nxp/mcux/devices/MIMXRT1061/fsl_clock.c
View file

@ -14,20 +14,21 @@
/*******************************************************************************
* Definitions
******************************************************************************/
/* To make full use of CM7 hardware FPU, use double instead of uint64_t in clock driver to
/* To make full use of CM7 hardware FPU, use double instead of uint64_t in clock driver to
achieve better performance, it is depend on the IDE Floating point settings, if double precision is selected
in IDE, clock_64b_t will switch to double type automatically. only support IAR and MDK here */
#if __FPU_USED
#if ((defined(__ICCARM__)) || (defined(__GNUC__)))
#if (__ARMVFP__ >= __ARMFPV5__) && (__ARM_FP == 0xE) /*0xe implies support for half, single and double precision operations*/
#if (__ARMVFP__ >= __ARMFPV5__) && \
(__ARM_FP == 0xE) /*0xe implies support for half, single and double precision operations*/
typedef double clock_64b_t;
#else
typedef uint64_t clock_64b_t;
#endif
#elif defined(__CC_ARM)
#elif defined(__CC_ARM) || defined(__ARMCC_VERSION)
#if defined __TARGET_FPU_FPV5_D16
typedef double clock_64b_t;
@ -447,7 +448,7 @@ bool CLOCK_EnableUsbhs0PhyPllClock(clock_usb_phy_src_t src, uint32_t freq)
const clock_usb_pll_config_t g_ccmConfigUsbPll = {.loopDivider = 0U};
if (CCM_ANALOG->PLL_USB1 & CCM_ANALOG_PLL_USB1_ENABLE_MASK)
{
CCM_ANALOG->PLL_USB1 |= CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK;
CCM_ANALOG->PLL_USB1 |= CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK;
}
else
{
@ -468,7 +469,7 @@ bool CLOCK_EnableUsbhs0PhyPllClock(clock_usb_phy_src_t src, uint32_t freq)
*/
void CLOCK_DisableUsbhs0PhyPllClock(void)
{
CCM_ANALOG->PLL_USB1 &= ~CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK;
CCM_ANALOG->PLL_USB1 &= ~CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK;
USBPHY1->CTRL |= USBPHY_CTRL_CLKGATE_MASK; /* Set to 1U to gate clocks */
}
@ -522,6 +523,15 @@ void CLOCK_InitSysPll(const clock_sys_pll_config_t *config)
(CCM_ANALOG->PLL_SYS & (~(CCM_ANALOG_PLL_SYS_DIV_SELECT_MASK | CCM_ANALOG_PLL_SYS_POWERDOWN_MASK))) |
CCM_ANALOG_PLL_SYS_ENABLE_MASK | CCM_ANALOG_PLL_SYS_DIV_SELECT(config->loopDivider);
/* Initialize the fractional mode */
CCM_ANALOG->PLL_SYS_NUM = CCM_ANALOG_PLL_SYS_NUM_A(config->numerator);
CCM_ANALOG->PLL_SYS_DENOM = CCM_ANALOG_PLL_SYS_DENOM_B(config->denominator);
/* Initialize the spread spectrum mode */
CCM_ANALOG->PLL_SYS_SS = CCM_ANALOG_PLL_SYS_SS_STEP(config->ss_step) |
CCM_ANALOG_PLL_SYS_SS_ENABLE(config->ss_enable) |
CCM_ANALOG_PLL_SYS_SS_STOP(config->ss_stop);
while ((CCM_ANALOG->PLL_SYS & CCM_ANALOG_PLL_SYS_LOCK_MASK) == 0)
{
}
@ -809,7 +819,8 @@ void CLOCK_InitEnetPll(const clock_enet_pll_config_t *config)
CCM_ANALOG->PLL_ENET =
(CCM_ANALOG->PLL_ENET & (~(CCM_ANALOG_PLL_ENET_DIV_SELECT_MASK | CCM_ANALOG_PLL_ENET_ENET2_DIV_SELECT_MASK |
CCM_ANALOG_PLL_ENET_POWERDOWN_MASK))) | enet_pll;
CCM_ANALOG_PLL_ENET_POWERDOWN_MASK))) |
enet_pll;
/* Wait for stable */
while ((CCM_ANALOG->PLL_ENET & CCM_ANALOG_PLL_ENET_LOCK_MASK) == 0)
@ -875,8 +886,8 @@ uint32_t CLOCK_GetPllFreq(clock_pll_t pll)
break;
case kCLOCK_PllSys:
/* PLL output frequency = Fref * (DIV_SELECT + NUM/DENOM). */
freqTmp =
((clock_64b_t)freq * ((clock_64b_t)(CCM_ANALOG->PLL_SYS_NUM))) / ((clock_64b_t)(CCM_ANALOG->PLL_SYS_DENOM));
freqTmp = ((clock_64b_t)freq * ((clock_64b_t)(CCM_ANALOG->PLL_SYS_NUM))) /
((clock_64b_t)(CCM_ANALOG->PLL_SYS_DENOM));
if (CCM_ANALOG->PLL_SYS & CCM_ANALOG_PLL_SYS_DIV_SELECT_MASK)
{
@ -899,8 +910,8 @@ uint32_t CLOCK_GetPllFreq(clock_pll_t pll)
divSelect =
(CCM_ANALOG->PLL_AUDIO & CCM_ANALOG_PLL_AUDIO_DIV_SELECT_MASK) >> CCM_ANALOG_PLL_AUDIO_DIV_SELECT_SHIFT;
freqTmp =
((clock_64b_t)freq * ((clock_64b_t)(CCM_ANALOG->PLL_AUDIO_NUM))) / ((clock_64b_t)(CCM_ANALOG->PLL_AUDIO_DENOM));
freqTmp = ((clock_64b_t)freq * ((clock_64b_t)(CCM_ANALOG->PLL_AUDIO_NUM))) /
((clock_64b_t)(CCM_ANALOG->PLL_AUDIO_DENOM));
freq = freq * divSelect + (uint32_t)freqTmp;
@ -954,8 +965,8 @@ uint32_t CLOCK_GetPllFreq(clock_pll_t pll)
divSelect =
(CCM_ANALOG->PLL_VIDEO & CCM_ANALOG_PLL_VIDEO_DIV_SELECT_MASK) >> CCM_ANALOG_PLL_VIDEO_DIV_SELECT_SHIFT;
freqTmp =
((clock_64b_t)freq * ((clock_64b_t)(CCM_ANALOG->PLL_VIDEO_NUM))) / ((clock_64b_t)(CCM_ANALOG->PLL_VIDEO_DENOM));
freqTmp = ((clock_64b_t)freq * ((clock_64b_t)(CCM_ANALOG->PLL_VIDEO_NUM))) /
((clock_64b_t)(CCM_ANALOG->PLL_VIDEO_DENOM));
freq = freq * divSelect + (uint32_t)freqTmp;
@ -1212,6 +1223,6 @@ bool CLOCK_EnableUsbhs1PhyPllClock(clock_usb_phy_src_t src, uint32_t freq)
*/
void CLOCK_DisableUsbhs1PhyPllClock(void)
{
CCM_ANALOG->PLL_USB2 &= ~CCM_ANALOG_PLL_USB2_EN_USB_CLKS_MASK;
CCM_ANALOG->PLL_USB2 &= ~CCM_ANALOG_PLL_USB2_EN_USB_CLKS_MASK;
USBPHY2->CTRL |= USBPHY_CTRL_CLKGATE_MASK; /* Set to 1U to gate clocks */
}

58
ext/hal/nxp/mcux/devices/MIMXRT1061/fsl_clock.h
View file

@ -39,8 +39,8 @@
/*! @name Driver version */
/*@{*/
/*! @brief CLOCK driver version 2.1.5. */
#define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 1, 5))
/*! @brief CLOCK driver version 2.1.6. */
#define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 1, 6))
/* analog pll definition */
#define CCM_ANALOG_PLL_BYPASS_SHIFT (16U)
@ -156,8 +156,8 @@ extern volatile uint32_t g_rtcXtalFreq;
}
/*! @brief Clock ip name array for ENET. */
#define ENET_CLOCKS \
{ \
#define ENET_CLOCKS \
{ \
kCLOCK_Enet, kCLOCK_IpInvalid, kCLOCK_Enet2 \
}
@ -168,20 +168,20 @@ extern volatile uint32_t g_rtcXtalFreq;
}
/*! @brief Clock ip name array for FLEXCAN. */
#define FLEXCAN_CLOCKS \
{ \
#define FLEXCAN_CLOCKS \
{ \
kCLOCK_IpInvalid, kCLOCK_Can1, kCLOCK_Can2, kCLOCK_Can3 \
}
/*! @brief Clock ip name array for FLEXCAN Peripheral clock. */
#define FLEXCAN_PERIPH_CLOCKS \
{ \
#define FLEXCAN_PERIPH_CLOCKS \
{ \
kCLOCK_IpInvalid, kCLOCK_Can1S, kCLOCK_Can2S, kCLOCK_Can3S \
}
/*! @brief Clock ip name array for FLEXIO. */
#define FLEXIO_CLOCKS \
{ \
#define FLEXIO_CLOCKS \
{ \
kCLOCK_IpInvalid, kCLOCK_Flexio1, kCLOCK_Flexio2, kCLOCK_Flexio3 \
}
@ -192,8 +192,8 @@ extern volatile uint32_t g_rtcXtalFreq;
}
/*! @brief Clock ip name array for FLEXSPI. */
#define FLEXSPI_CLOCKS \
{ \
#define FLEXSPI_CLOCKS \
{ \
kCLOCK_FlexSpi, kCLOCK_IpInvalid, kCLOCK_FlexSpi2 \
}
@ -533,14 +533,14 @@ typedef enum _clock_ip_name
kCLOCK_Timer3 = (6U << 8U) | CCM_CCGR6_CG15_SHIFT, /*!< CCGR6, CG15 */
/* CCM CCGR7 */
kCLOCK_Enet2 = (7U << 8U) | CCM_CCGR7_CG0_SHIFT, /*!< CCGR7, CG0 */
kCLOCK_FlexSpi2 = (7U << 8U) | CCM_CCGR7_CG1_SHIFT, /*!< CCGR7, CG1 */
kCLOCK_Axbs_l = (7U << 8U) | CCM_CCGR7_CG2_SHIFT, /*!< CCGR7, CG2 */
kCLOCK_Can3 = (7U << 8U) | CCM_CCGR7_CG3_SHIFT, /*!< CCGR7, CG3 */
kCLOCK_Can3S = (7U << 8U) | CCM_CCGR7_CG4_SHIFT, /*!< CCGR7, CG4 */
kCLOCK_Aips_lite = (7U << 8U) | CCM_CCGR7_CG5_SHIFT,/*!< CCGR7, CG5 */
kCLOCK_Flexio3 = (7U << 8U) | CCM_CCGR7_CG6_SHIFT, /*!< CCGR7, CG6 */
kCLOCK_Enet2 = (7U << 8U) | CCM_CCGR7_CG0_SHIFT, /*!< CCGR7, CG0 */
kCLOCK_FlexSpi2 = (7U << 8U) | CCM_CCGR7_CG1_SHIFT, /*!< CCGR7, CG1 */
kCLOCK_Axbs_l = (7U << 8U) | CCM_CCGR7_CG2_SHIFT, /*!< CCGR7, CG2 */
kCLOCK_Can3 = (7U << 8U) | CCM_CCGR7_CG3_SHIFT, /*!< CCGR7, CG3 */
kCLOCK_Can3S = (7U << 8U) | CCM_CCGR7_CG4_SHIFT, /*!< CCGR7, CG4 */
kCLOCK_Aips_lite = (7U << 8U) | CCM_CCGR7_CG5_SHIFT, /*!< CCGR7, CG5 */
kCLOCK_Flexio3 = (7U << 8U) | CCM_CCGR7_CG6_SHIFT, /*!< CCGR7, CG6 */
} clock_ip_name_t;
/*! @brief OSC 24M sorce select */
@ -603,9 +603,9 @@ typedef enum _clock_mux
CCM_CBCMR_PERIPH_CLK2_SEL_MASK,
CCM_NO_BUSY_WAIT), /*!< periph clock2 mux name */
kCLOCK_Flexspi2Mux = CCM_TUPLE(CBCMR,
CCM_CBCMR_FLEXSPI2_CLK_SEL_SHIFT,
CCM_CBCMR_FLEXSPI2_CLK_SEL_MASK,
CCM_NO_BUSY_WAIT), /*!< flexspi2 mux name */
CCM_CBCMR_FLEXSPI2_CLK_SEL_SHIFT,
CCM_CBCMR_FLEXSPI2_CLK_SEL_MASK,
CCM_NO_BUSY_WAIT), /*!< flexspi2 mux name */
kCLOCK_LpspiMux = CCM_TUPLE(
CBCMR, CCM_CBCMR_LPSPI_CLK_SEL_SHIFT, CCM_CBCMR_LPSPI_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), /*!< lpspi mux name */
@ -813,7 +813,9 @@ typedef struct _clock_sys_pll_config
uint32_t numerator; /*!< 30 bit numerator of fractional loop divider.*/
uint32_t denominator; /*!< 30 bit denominator of fractional loop divider */
uint8_t src; /*!< Pll clock source, reference _clock_pll_clk_src */
uint16_t ss_stop; /*!< Stop value to get frequency change. */
uint8_t ss_enable; /*!< Enable spread spectrum modulation */
uint16_t ss_step; /*!< Step value to get frequency change step. */
} clock_sys_pll_config_t;
/*! @brief PLL configuration for AUDIO and VIDEO */
@ -841,20 +843,19 @@ typedef struct _clock_video_pll_config
typedef struct _clock_enet_pll_config
{
bool enableClkOutput; /*!< Power on and enable PLL clock output for ENET0 (ref_enetpll0). */
bool enableClkOutput1; /*!< Power on and enable PLL clock output for ENET1 (ref_enetpll1). */
bool enableClkOutput25M; /*!< Power on and enable PLL clock output for ENET2 (ref_enetpll2). */
uint8_t loopDivider; /*!< Controls the frequency of the ENET0 reference clock.
b00 25MHz
b01 50MHz
b10 100MHz (not 50% duty cycle)
b11 125MHz */
uint8_t loopDivider1; /*!< Controls the frequency of the ENET1 reference clock.
uint8_t src; /*!< Pll clock source, reference _clock_pll_clk_src */
bool enableClkOutput1; /*!< Power on and enable PLL clock output for ENET1 (ref_enetpll1). */
uint8_t loopDivider1; /*!< Controls the frequency of the ENET1 reference clock.
b00 25MHz
b01 50MHz
b10 100MHz (not 50% duty cycle)
b11 125MHz */
uint8_t src; /*!< Pll clock source, reference _clock_pll_clk_src */
} clock_enet_pll_config_t;
/*! @brief PLL name */
@ -1157,7 +1158,6 @@ void CLOCK_InitRcOsc24M(void);
void CLOCK_DeinitRcOsc24M(void);
/* @} */
/*! @brief Enable USB HS clock.
*
* This function only enables the access to USB HS prepheral, upper layer

6
ext/hal/nxp/mcux/devices/MIMXRT1061/fsl_iomuxc.h
View file

@ -27,8 +27,8 @@
/*! @name Driver version */
/*@{*/
/*! @brief IOMUXC driver version 2.0.0. */
#define FSL_IOMUXC_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
/*! @brief IOMUXC driver version 2.0.1. */
#define FSL_IOMUXC_DRIVER_VERSION (MAKE_VERSION(2, 0, 1))
/*@}*/
/*! @name Pin function ID */
@ -1206,8 +1206,10 @@ typedef enum _iomuxc_gpr_mode
{
kIOMUXC_GPR_GlobalInterruptRequest = IOMUXC_GPR_GPR1_GINT_MASK,
kIOMUXC_GPR_ENET1RefClkMode = IOMUXC_GPR_GPR1_ENET1_CLK_SEL_MASK,
kIOMUXC_GPR_ENET2RefClkMode = IOMUXC_GPR_GPR1_ENET2_CLK_SEL_MASK,
kIOMUXC_GPR_USBExposureMode = IOMUXC_GPR_GPR1_USB_EXP_MODE_MASK,
kIOMUXC_GPR_ENET1TxClkOutputDir = IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK,
kIOMUXC_GPR_ENET2TxClkOutputDir = IOMUXC_GPR_GPR1_ENET2_TX_CLK_DIR_MASK,
kIOMUXC_GPR_SAI1MClkOutputDir = IOMUXC_GPR_GPR1_SAI1_MCLK_DIR_MASK,
kIOMUXC_GPR_SAI2MClkOutputDir = IOMUXC_GPR_GPR1_SAI2_MCLK_DIR_MASK,
kIOMUXC_GPR_SAI3MClkOutputDir = IOMUXC_GPR_GPR1_SAI3_MCLK_DIR_MASK,

853
ext/hal/nxp/mcux/devices/MIMXRT1062/MIMXRT1062.h
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File diff suppressed because it is too large Load diff

445
ext/hal/nxp/mcux/devices/MIMXRT1062/MIMXRT1062.xml
View file

@ -6,6 +6,7 @@
<description>MIMXRT1062DVL6A</description>
<licenseText>
Copyright 2016-2018 NXP
All rights reserved.
SPDX-License-Identifier: BSD-3-Clause
</licenseText>
@ -8097,13 +8098,6 @@ SPDX-License-Identifier: BSD-3-Clause
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CM7_INIT_VTOR</name>
<description>Vector table offset register out of reset</description>
<bitOffset>7</bitOffset>
<bitWidth>25</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
@ -8729,145 +8723,6 @@ SPDX-License-Identifier: BSD-3-Clause
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>Reserved</name>
<description>Reserved</description>
<bitOffset>3</bitOffset>
<bitWidth>29</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>OCRAM_MAGIC_ADDR</name>
<description>OCRAM Magic Address Register</description>
<addressOffset>0x4</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>OCRAM_WR_RD_SEL</name>
<description>OCRAM Write Read Select</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>OCRAM_WR_RD_SEL_0</name>
<description>When OCRAM read access hits magic address, it will generate interrupt.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>OCRAM_WR_RD_SEL_1</name>
<description>When OCRAM write access hits magic address, it will generate interrupt.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>OCRAM_MAGIC_ADDR</name>
<description>OCRAM Magic Address</description>
<bitOffset>1</bitOffset>
<bitWidth>16</bitWidth>
<access>read-write</access>
</field>
<field>
<name>Reserved</name>
<description>Reserved</description>
<bitOffset>17</bitOffset>
<bitWidth>15</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>DTCM_MAGIC_ADDR</name>
<description>DTCM Magic Address Register</description>
<addressOffset>0x8</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>DTCM_WR_RD_SEL</name>
<description>DTCM Write Read Select</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>DTCM_WR_RD_SEL_0</name>
<description>When DTCM read access hits magic address, it will generate interrupt.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>DTCM_WR_RD_SEL_1</name>
<description>When DTCM write access hits magic address, it will generate interrupt.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DTCM_MAGIC_ADDR</name>
<description>DTCM Magic Address</description>
<bitOffset>1</bitOffset>
<bitWidth>16</bitWidth>
<access>read-write</access>
</field>
<field>
<name>Reserved</name>
<description>Reserved</description>
<bitOffset>17</bitOffset>
<bitWidth>15</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>ITCM_MAGIC_ADDR</name>
<description>ITCM Magic Address Register</description>
<addressOffset>0xC</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>ITCM_WR_RD_SEL</name>
<description>ITCM Write Read Select</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>ITCM_WR_RD_SEL_0</name>
<description>When ITCM read access hits magic address, it will generate interrupt.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ITCM_WR_RD_SEL_1</name>
<description>When ITCM write access hits magic address, it will generate interrupt.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ITCM_MAGIC_ADDR</name>
<description>ITCM Magic Address</description>
<bitOffset>1</bitOffset>
<bitWidth>16</bitWidth>
<access>read-write</access>
</field>
<field>
<name>Reserved</name>
<description>Reserved</description>
<bitOffset>17</bitOffset>
<bitWidth>15</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
@ -8879,66 +8734,6 @@ SPDX-License-Identifier: BSD-3-Clause
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>ITCM_MAM_STATUS</name>
<description>ITCM Magic Address Match Status</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<modifiedWriteValues>oneToClear</modifiedWriteValues>
<enumeratedValues>
<enumeratedValue>
<name>ITCM_MAM_STATUS_0</name>
<description>ITCM did not access magic address.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ITCM_MAM_STATUS_1</name>
<description>ITCM accessed magic address.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DTCM_MAM_STATUS</name>
<description>DTCM Magic Address Match Status</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<modifiedWriteValues>oneToClear</modifiedWriteValues>
<enumeratedValues>
<enumeratedValue>
<name>DTCM_MAM_STATUS_0</name>
<description>DTCM did not access magic address.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>DTCM_MAM_STATUS_1</name>
<description>DTCM accessed magic address.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>OCRAM_MAM_STATUS</name>
<description>OCRAM Magic Address Match Status</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<modifiedWriteValues>oneToClear</modifiedWriteValues>
<enumeratedValues>
<enumeratedValue>
<name>OCRAM_MAM_STATUS_0</name>
<description>OCRAM did not access magic address.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>OCRAM_MAM_STATUS_1</name>
<description>OCRAM accessed magic address.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ITCM_ERR_STATUS</name>
<description>ITCM Access Error Status</description>
@ -8999,13 +8794,6 @@ SPDX-License-Identifier: BSD-3-Clause
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>Reserved</name>
<description>Reserved</description>
<bitOffset>6</bitOffset>
<bitWidth>26</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
@ -9017,63 +8805,6 @@ SPDX-License-Identifier: BSD-3-Clause
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>ITCM_MAM_STAT_EN</name>
<description>ITCM Magic Address Match Status Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>ITCM_MAM_STAT_EN_0</name>
<description>Masked</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ITCM_MAM_STAT_EN_1</name>
<description>Enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DTCM_MAM_STAT_EN</name>
<description>DTCM Magic Address Match Status Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>DTCM_MAM_STAT_EN_0</name>
<description>Masked</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>DTCM_MAM_STAT_EN_1</name>
<description>Enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>OCRAM_MAM_STAT_EN</name>
<description>OCRAM Magic Address Match Status Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>OCRAM_MAM_STAT_EN_0</name>
<description>Masked</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>OCRAM_MAM_STAT_EN_1</name>
<description>Enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ITCM_ERR_STAT_EN</name>
<description>ITCM Access Error Status Enable</description>
@ -9131,13 +8862,6 @@ SPDX-License-Identifier: BSD-3-Clause
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>Reserved</name>
<description>Reserved</description>
<bitOffset>6</bitOffset>
<bitWidth>26</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
@ -9149,63 +8873,6 @@ SPDX-License-Identifier: BSD-3-Clause
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>ITCM_MAM_SIG_EN</name>
<description>ITCM Magic Address Match Interrupt Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>ITCM_MAM_SIG_EN_0</name>
<description>Masked</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ITCM_MAM_SIG_EN_1</name>
<description>Enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DTCM_MAM_SIG_EN</name>
<description>DTCM Magic Address Match Interrupt Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>DTCM_MAM_SIG_EN_0</name>
<description>Masked</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>DTCM_MAM_SIG_EN_1</name>
<description>Enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>OCRAM_MAM_SIG_EN</name>
<description>OCRAM Magic Address Match Interrupt Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>OCRAM_MAM_SIG_EN_0</name>
<description>Masked</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>OCRAM_MAM_SIG_EN_1</name>
<description>Enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ITCM_ERR_SIG_EN</name>
<description>ITCM Access Error Interrupt Enable</description>
@ -9263,13 +8930,6 @@ SPDX-License-Identifier: BSD-3-Clause
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>Reserved</name>
<description>Reserved</description>
<bitOffset>6</bitOffset>
<bitWidth>26</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
</registers>
@ -78935,6 +78595,94 @@ SPDX-License-Identifier: BSD-3-Clause
</field>
</fields>
</register>
<register>
<name>DBG1</name>
<description>Debug 1 register</description>
<addressOffset>0x58</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x10000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CFSM</name>
<description>CAN Finite State Machine</description>
<bitOffset>0</bitOffset>
<bitWidth>6</bitWidth>
<access>read-only</access>
</field>
<field>
<name>CBN</name>
<description>CAN Bit Number</description>
<bitOffset>24</bitOffset>
<bitWidth>5</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>DBG2</name>
<description>Debug 2 register</description>
<addressOffset>0x5C</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>RMP</name>
<description>Rx Matching Pointer</description>
<bitOffset>0</bitOffset>
<bitWidth>7</bitWidth>
<access>read-only</access>
</field>
<field>
<name>MPP</name>
<description>Matching Process in Progress</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>MPP_0</name>
<description>No matching process ongoing.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>MPP_1</name>
<description>Matching process is in progress.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TAP</name>
<description>Tx Arbitration Pointer</description>
<bitOffset>8</bitOffset>
<bitWidth>7</bitWidth>
<access>read-only</access>
</field>
<field>
<name>APP</name>
<description>Arbitration Process in Progress</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>APP_0</name>
<description>No matching process ongoing.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>APP_1</name>
<description>Matching process is in progress.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<dim>64</dim>
<dimIncrement>0x4</dimIncrement>
@ -140288,13 +140036,6 @@ SPDX-License-Identifier: BSD-3-Clause
<bitWidth>2</bitWidth>
<access>read-only</access>
</field>
<field>
<name>SRK</name>
<description>SRK</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>ROM_PATCH</name>
<description>ROM_PATCH</description>
@ -140592,7 +140333,7 @@ SPDX-License-Identifier: BSD-3-Clause
</register>
<register>
<name>ANA0</name>
<description>Value of OTP Bank1 Word5 (Analog Info.)</description>
<description>Value of OTP Bank1 Word5 (Memory Related Info.)</description>
<addressOffset>0x4D0</addressOffset>
<size>32</size>
<access>read-write</access>
@ -140610,7 +140351,7 @@ SPDX-License-Identifier: BSD-3-Clause
</register>
<register>
<name>ANA1</name>
<description>Value of OTP Bank1 Word6 (Analog Info.)</description>
<description>Value of OTP Bank1 Word6 (General Purpose Customer Defined Info.)</description>
<addressOffset>0x4E0</addressOffset>
<size>32</size>
<access>read-write</access>
@ -140628,7 +140369,7 @@ SPDX-License-Identifier: BSD-3-Clause
</register>
<register>
<name>ANA2</name>
<description>Value of OTP Bank1 Word7 (Analog Info.)</description>
<description>Value of OTP Bank1 Word7 (General Purpose Customer Defined Info.)</description>
<addressOffset>0x4F0</addressOffset>
<size>32</size>
<access>read-write</access>
@ -141006,7 +140747,7 @@ SPDX-License-Identifier: BSD-3-Clause
</register>
<register>
<name>MAC2</name>
<description>Value of OTP Bank4 Word4 (MAC Address)</description>
<description>Value of OTP Bank4 Word4 (MAC2 Address)</description>
<addressOffset>0x640</addressOffset>
<size>32</size>
<access>read-write</access>

17
ext/hal/nxp/mcux/devices/MIMXRT1062/MIMXRT1062_features.h
View file

@ -1,13 +1,14 @@
/*
** ###################################################################
** Version: rev. 0.1, 2017-01-10
** Build: b180806
** Version: rev. 1.0, 2018-11-16
** Build: b181120
**
** Abstract:
** Chip specific module features.
**
** Copyright 2016 Freescale Semiconductor, Inc.
** Copyright 2016-2018 NXP
** All rights reserved.
**
** SPDX-License-Identifier: BSD-3-Clause
**
@ -17,6 +18,8 @@
** Revisions:
** - rev. 0.1 (2017-01-10)
** Initial version.
** - rev. 1.0 (2018-11-16)
** Update feature files to align with IMXRT1060RM Rev.0.
**
** ###################################################################
*/
@ -69,7 +72,7 @@
/* @brief I2S availability on the SoC. */
#define FSL_FEATURE_SOC_I2S_COUNT (3)
/* @brief IGPIO availability on the SoC. */
#define FSL_FEATURE_SOC_IGPIO_COUNT (10)
#define FSL_FEATURE_SOC_IGPIO_COUNT (9)
/* @brief IOMUXC availability on the SoC. */
#define FSL_FEATURE_SOC_IOMUXC_COUNT (1)
/* @brief IOMUXC_GPR availability on the SoC. */
@ -186,6 +189,12 @@
((x) == CAN3 ? (0) : (-1))))
/* @brief Is affected by errata with ID 5641 (Module does not transmit a message that is enabled to be transmitted at a specific moment during the arbitration process). */
#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641 (0)
/* @brief Is affected by errata with ID 5829 (FlexCAN: FlexCAN does not transmit a message that is enabled to be transmitted in a specific moment during the arbitration process). */
#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_5829 (1)
/* @brief Is affected by errata with ID 6032 (FlexCAN: A frame with wrong ID or payload is transmitted into the CAN bus when the Message Buffer under transmission is either aborted or deactivated while the CAN bus is in the Bus Idle state). */
#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_6032 (1)
/* @brief Is affected by errata with ID 9595 (FlexCAN: Corrupt frame possible if the Freeze Mode or the Low-Power Mode are entered during a Bus-Off state). */
#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_9595 (1)
/* @brief Has CAN with Flexible Data rate (CAN FD) protocol. */
#define FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE (1)
/* @brief CAN instance support Flexible Data rate (CAN FD) protocol. */
@ -283,7 +292,7 @@
/* FLEXRAM module features */
/* @brief Bank size */
#define FSL_FEATURE_FLEXRAM_INTERNAL_RAM_BANK_SIZE (32 * 1024)
#define FSL_FEATURE_FLEXRAM_INTERNAL_RAM_BANK_SIZE (32768)
/* @brief Total Bank numbers */
#define FSL_FEATURE_FLEXRAM_INTERNAL_RAM_TOTAL_BANK_NUMBERS (16)

37
ext/hal/nxp/mcux/devices/MIMXRT1062/fsl_clock.c
View file

@ -14,20 +14,21 @@
/*******************************************************************************
* Definitions
******************************************************************************/
/* To make full use of CM7 hardware FPU, use double instead of uint64_t in clock driver to
/* To make full use of CM7 hardware FPU, use double instead of uint64_t in clock driver to
achieve better performance, it is depend on the IDE Floating point settings, if double precision is selected
in IDE, clock_64b_t will switch to double type automatically. only support IAR and MDK here */
#if __FPU_USED
#if ((defined(__ICCARM__)) || (defined(__GNUC__)))
#if (__ARMVFP__ >= __ARMFPV5__) && (__ARM_FP == 0xE) /*0xe implies support for half, single and double precision operations*/
#if (__ARMVFP__ >= __ARMFPV5__) && \
(__ARM_FP == 0xE) /*0xe implies support for half, single and double precision operations*/
typedef double clock_64b_t;
#else
typedef uint64_t clock_64b_t;
#endif
#elif defined(__CC_ARM)
#elif defined(__CC_ARM) || defined(__ARMCC_VERSION)
#if defined __TARGET_FPU_FPV5_D16
typedef double clock_64b_t;
@ -447,7 +448,7 @@ bool CLOCK_EnableUsbhs0PhyPllClock(clock_usb_phy_src_t src, uint32_t freq)
const clock_usb_pll_config_t g_ccmConfigUsbPll = {.loopDivider = 0U};
if (CCM_ANALOG->PLL_USB1 & CCM_ANALOG_PLL_USB1_ENABLE_MASK)
{
CCM_ANALOG->PLL_USB1 |= CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK;
CCM_ANALOG->PLL_USB1 |= CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK;
}
else
{
@ -468,7 +469,7 @@ bool CLOCK_EnableUsbhs0PhyPllClock(clock_usb_phy_src_t src, uint32_t freq)
*/
void CLOCK_DisableUsbhs0PhyPllClock(void)
{
CCM_ANALOG->PLL_USB1 &= ~CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK;
CCM_ANALOG->PLL_USB1 &= ~CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK;
USBPHY1->CTRL |= USBPHY_CTRL_CLKGATE_MASK; /* Set to 1U to gate clocks */
}
@ -522,6 +523,15 @@ void CLOCK_InitSysPll(const clock_sys_pll_config_t *config)
(CCM_ANALOG->PLL_SYS & (~(CCM_ANALOG_PLL_SYS_DIV_SELECT_MASK | CCM_ANALOG_PLL_SYS_POWERDOWN_MASK))) |
CCM_ANALOG_PLL_SYS_ENABLE_MASK | CCM_ANALOG_PLL_SYS_DIV_SELECT(config->loopDivider);
/* Initialize the fractional mode */
CCM_ANALOG->PLL_SYS_NUM = CCM_ANALOG_PLL_SYS_NUM_A(config->numerator);
CCM_ANALOG->PLL_SYS_DENOM = CCM_ANALOG_PLL_SYS_DENOM_B(config->denominator);
/* Initialize the spread spectrum mode */
CCM_ANALOG->PLL_SYS_SS = CCM_ANALOG_PLL_SYS_SS_STEP(config->ss_step) |
CCM_ANALOG_PLL_SYS_SS_ENABLE(config->ss_enable) |
CCM_ANALOG_PLL_SYS_SS_STOP(config->ss_stop);
while ((CCM_ANALOG->PLL_SYS & CCM_ANALOG_PLL_SYS_LOCK_MASK) == 0)
{
}
@ -809,7 +819,8 @@ void CLOCK_InitEnetPll(const clock_enet_pll_config_t *config)
CCM_ANALOG->PLL_ENET =
(CCM_ANALOG->PLL_ENET & (~(CCM_ANALOG_PLL_ENET_DIV_SELECT_MASK | CCM_ANALOG_PLL_ENET_ENET2_DIV_SELECT_MASK |
CCM_ANALOG_PLL_ENET_POWERDOWN_MASK))) | enet_pll;
CCM_ANALOG_PLL_ENET_POWERDOWN_MASK))) |
enet_pll;
/* Wait for stable */
while ((CCM_ANALOG->PLL_ENET & CCM_ANALOG_PLL_ENET_LOCK_MASK) == 0)
@ -875,8 +886,8 @@ uint32_t CLOCK_GetPllFreq(clock_pll_t pll)
break;
case kCLOCK_PllSys:
/* PLL output frequency = Fref * (DIV_SELECT + NUM/DENOM). */
freqTmp =
((clock_64b_t)freq * ((clock_64b_t)(CCM_ANALOG->PLL_SYS_NUM))) / ((clock_64b_t)(CCM_ANALOG->PLL_SYS_DENOM));
freqTmp = ((clock_64b_t)freq * ((clock_64b_t)(CCM_ANALOG->PLL_SYS_NUM))) /
((clock_64b_t)(CCM_ANALOG->PLL_SYS_DENOM));
if (CCM_ANALOG->PLL_SYS & CCM_ANALOG_PLL_SYS_DIV_SELECT_MASK)
{
@ -899,8 +910,8 @@ uint32_t CLOCK_GetPllFreq(clock_pll_t pll)
divSelect =
(CCM_ANALOG->PLL_AUDIO & CCM_ANALOG_PLL_AUDIO_DIV_SELECT_MASK) >> CCM_ANALOG_PLL_AUDIO_DIV_SELECT_SHIFT;
freqTmp =
((clock_64b_t)freq * ((clock_64b_t)(CCM_ANALOG->PLL_AUDIO_NUM))) / ((clock_64b_t)(CCM_ANALOG->PLL_AUDIO_DENOM));
freqTmp = ((clock_64b_t)freq * ((clock_64b_t)(CCM_ANALOG->PLL_AUDIO_NUM))) /
((clock_64b_t)(CCM_ANALOG->PLL_AUDIO_DENOM));
freq = freq * divSelect + (uint32_t)freqTmp;
@ -954,8 +965,8 @@ uint32_t CLOCK_GetPllFreq(clock_pll_t pll)
divSelect =
(CCM_ANALOG->PLL_VIDEO & CCM_ANALOG_PLL_VIDEO_DIV_SELECT_MASK) >> CCM_ANALOG_PLL_VIDEO_DIV_SELECT_SHIFT;
freqTmp =
((clock_64b_t)freq * ((clock_64b_t)(CCM_ANALOG->PLL_VIDEO_NUM))) / ((clock_64b_t)(CCM_ANALOG->PLL_VIDEO_DENOM));
freqTmp = ((clock_64b_t)freq * ((clock_64b_t)(CCM_ANALOG->PLL_VIDEO_NUM))) /
((clock_64b_t)(CCM_ANALOG->PLL_VIDEO_DENOM));
freq = freq * divSelect + (uint32_t)freqTmp;
@ -1212,6 +1223,6 @@ bool CLOCK_EnableUsbhs1PhyPllClock(clock_usb_phy_src_t src, uint32_t freq)
*/
void CLOCK_DisableUsbhs1PhyPllClock(void)
{
CCM_ANALOG->PLL_USB2 &= ~CCM_ANALOG_PLL_USB2_EN_USB_CLKS_MASK;
CCM_ANALOG->PLL_USB2 &= ~CCM_ANALOG_PLL_USB2_EN_USB_CLKS_MASK;
USBPHY2->CTRL |= USBPHY_CTRL_CLKGATE_MASK; /* Set to 1U to gate clocks */
}

18
ext/hal/nxp/mcux/devices/MIMXRT1062/fsl_clock.h
View file

@ -39,8 +39,8 @@
/*! @name Driver version */
/*@{*/
/*! @brief CLOCK driver version 2.1.5. */
#define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 1, 5))
/*! @brief CLOCK driver version 2.1.6. */
#define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 1, 6))
/* analog pll definition */
#define CCM_ANALOG_PLL_BYPASS_SHIFT (16U)
@ -48,9 +48,9 @@
#define CCM_ANALOG_PLL_BYPASS_CLK_SRC_SHIFT (14U)
/*@}*/
#define CCM_TUPLE(reg, shift, mask, busyShift) \
((((uint32_t)(&((CCM_Type *)0U)->reg)) & 0xFFU) | ((shift) << 8U) | ((((mask) >> (shift)) & 0x1FFFU) << 13U) | \
((busyShift) << 26U))
#define CCM_TUPLE(reg, shift, mask, busyShift) \
(int)((((uint32_t)(&((CCM_Type *)0U)->reg)) & 0xFFU) | ((shift) << 8U) | \
((((mask) >> (shift)) & 0x1FFFU) << 13U) | ((busyShift) << 26U))
#define CCM_TUPLE_REG(base, tuple) (*((volatile uint32_t *)(((uint32_t)(base)) + ((tuple)&0xFFU))))
#define CCM_TUPLE_SHIFT(tuple) (((tuple) >> 8U) & 0x1FU)
#define CCM_TUPLE_MASK(tuple) ((uint32_t)((((tuple) >> 13U) & 0x1FFFU) << ((((tuple) >> 8U) & 0x1FU))))
@ -769,8 +769,8 @@ typedef enum _clock_div
/*! @brief USB clock source definition. */
typedef enum _clock_usb_src
{
kCLOCK_Usb480M = 0, /*!< Use 480M. */
kCLOCK_UsbSrcUnused = 0xFFFFFFFFU, /*!< Used when the function does not
kCLOCK_Usb480M = 0, /*!< Use 480M. */
kCLOCK_UsbSrcUnused = (int)0xFFFFFFFFU, /*!< Used when the function does not
care the clock source. */
} clock_usb_src_t;
@ -813,7 +813,9 @@ typedef struct _clock_sys_pll_config
uint32_t numerator; /*!< 30 bit numerator of fractional loop divider.*/
uint32_t denominator; /*!< 30 bit denominator of fractional loop divider */
uint8_t src; /*!< Pll clock source, reference _clock_pll_clk_src */
uint16_t ss_stop; /*!< Stop value to get frequency change. */
uint8_t ss_enable; /*!< Enable spread spectrum modulation */
uint16_t ss_step; /*!< Step value to get frequency change step. */
} clock_sys_pll_config_t;
/*! @brief PLL configuration for AUDIO and VIDEO */

48
ext/hal/nxp/mcux/devices/MIMXRT1062/fsl_iomuxc.h
View file

@ -1,7 +1,7 @@
/*
* Copyright 2016 Freescale Semiconductor, Inc.
* Copyright 2016-2018 NXP
*
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -27,8 +27,8 @@
/*! @name Driver version */
/*@{*/
/*! @brief IOMUXC driver version 2.0.0. */
#define FSL_IOMUXC_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
/*! @brief IOMUXC driver version 2.0.1. */
#define FSL_IOMUXC_DRIVER_VERSION (MAKE_VERSION(2, 0, 1))
/*@}*/
/*! @name Pin function ID */
@ -1206,23 +1206,25 @@ typedef enum _iomuxc_gpr_mode
{
kIOMUXC_GPR_GlobalInterruptRequest = IOMUXC_GPR_GPR1_GINT_MASK,
kIOMUXC_GPR_ENET1RefClkMode = IOMUXC_GPR_GPR1_ENET1_CLK_SEL_MASK,
kIOMUXC_GPR_ENET2RefClkMode = IOMUXC_GPR_GPR1_ENET2_CLK_SEL_MASK,
kIOMUXC_GPR_USBExposureMode = IOMUXC_GPR_GPR1_USB_EXP_MODE_MASK,
kIOMUXC_GPR_ENET1TxClkOutputDir = IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK,
kIOMUXC_GPR_ENET2TxClkOutputDir = IOMUXC_GPR_GPR1_ENET2_TX_CLK_DIR_MASK,
kIOMUXC_GPR_SAI1MClkOutputDir = IOMUXC_GPR_GPR1_SAI1_MCLK_DIR_MASK,
kIOMUXC_GPR_SAI2MClkOutputDir = IOMUXC_GPR_GPR1_SAI2_MCLK_DIR_MASK,
kIOMUXC_GPR_SAI3MClkOutputDir = IOMUXC_GPR_GPR1_SAI3_MCLK_DIR_MASK,
kIOMUXC_GPR_ExcMonitorSlavErrResponse = IOMUXC_GPR_GPR1_EXC_MON_MASK,
kIOMUXC_GPR_ENETIpgClkOn = IOMUXC_GPR_GPR1_ENET_IPG_CLK_S_EN_MASK,
kIOMUXC_GPR_AHBClockEnable = IOMUXC_GPR_GPR1_CM7_FORCE_HCLK_EN_MASK,
} iomuxc_gpr_mode_t;
kIOMUXC_GPR_AHBClockEnable = (int)IOMUXC_GPR_GPR1_CM7_FORCE_HCLK_EN_MASK,
} iomuxc_gpr_mode_t;
typedef enum _iomuxc_gpr_saimclk
{
kIOMUXC_GPR_SAI1MClk1Sel = IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL_SHIFT,
kIOMUXC_GPR_SAI1MClk2Sel = IOMUXC_GPR_GPR1_SAI1_MCLK2_SEL_SHIFT,
kIOMUXC_GPR_SAI1MClk3Sel = IOMUXC_GPR_GPR1_SAI1_MCLK3_SEL_SHIFT,
kIOMUXC_GPR_SAI2MClk3Sel = IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL_SHIFT,
kIOMUXC_GPR_SAI3MClk3Sel = IOMUXC_GPR_GPR1_SAI3_MCLK3_SEL_SHIFT,
kIOMUXC_GPR_SAI1MClk3Sel = IOMUXC_GPR_GPR1_SAI1_MCLK3_SEL_SHIFT,
kIOMUXC_GPR_SAI2MClk3Sel = IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL_SHIFT,
kIOMUXC_GPR_SAI3MClk3Sel = IOMUXC_GPR_GPR1_SAI3_MCLK3_SEL_SHIFT,
} iomuxc_gpr_saimclk_t;
typedef enum _iomuxc_mqs_pwm_oversample_rate
@ -1315,11 +1317,9 @@ static inline void IOMUXC_SetPinConfig(uint32_t muxRegister,
*/
static inline void IOMUXC_EnableMode(IOMUXC_GPR_Type *base, uint32_t mode, bool enable)
{
mode &= ~(IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL_MASK
| IOMUXC_GPR_GPR1_SAI1_MCLK2_SEL_MASK
| IOMUXC_GPR_GPR1_SAI1_MCLK3_SEL_MASK
| IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL_MASK
| IOMUXC_GPR_GPR1_SAI3_MCLK3_SEL_MASK);
mode &= ~(IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL_MASK | IOMUXC_GPR_GPR1_SAI1_MCLK2_SEL_MASK |
IOMUXC_GPR_GPR1_SAI1_MCLK3_SEL_MASK | IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL_MASK |
IOMUXC_GPR_GPR1_SAI3_MCLK3_SEL_MASK);
if (enable)
{
@ -1345,17 +1345,17 @@ static inline void IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR_Type *base, iomuxc_gp
if (mclk > kIOMUXC_GPR_SAI1MClk2Sel)
{
gpr = base->GPR1 & ~(IOMUXC_GPR_SAIMCLK_HIGHBITMASK << mclk);
base->GPR1 = ((clkSrc & IOMUXC_GPR_SAIMCLK_HIGHBITMASK) << mclk) | gpr;
base->GPR1 = ((clkSrc & IOMUXC_GPR_SAIMCLK_HIGHBITMASK) << mclk) | gpr;
}
else
{
gpr = base->GPR1 & ~(IOMUXC_GPR_SAIMCLK_LOWBITMASK << mclk);
base->GPR1 = ((clkSrc & IOMUXC_GPR_SAIMCLK_LOWBITMASK) << mclk) | gpr;
base->GPR1 = ((clkSrc & IOMUXC_GPR_SAIMCLK_LOWBITMASK) << mclk) | gpr;
}
}
/*!
* @brief Enters or exit MQS software reset.
* @brief Enters or exit MQS software reset.
*
* @param base The IOMUXC GPR base address.
* @param enable Enter or exit MQS software reset.
@ -1364,17 +1364,16 @@ static inline void IOMUXC_MQSEnterSoftwareReset(IOMUXC_GPR_Type *base, bool enab
{
if (enable)
{
base->GPR2 |= IOMUXC_GPR_GPR2_MQS_SW_RST_MASK;
base->GPR2 |= IOMUXC_GPR_GPR2_MQS_SW_RST_MASK;
}
else
{
base->GPR2 &= ~IOMUXC_GPR_GPR2_MQS_SW_RST_MASK;
base->GPR2 &= ~IOMUXC_GPR_GPR2_MQS_SW_RST_MASK;
}
}
/*!
* @brief Enables or disables MQS.
* @brief Enables or disables MQS.
*
* @param base The IOMUXC GPR base address.
* @param enable Enable or disable the MQS.
@ -1383,16 +1382,16 @@ static inline void IOMUXC_MQSEnable(IOMUXC_GPR_Type *base, bool enable)
{
if (enable)
{
base->GPR2 |= IOMUXC_GPR_GPR2_MQS_EN_MASK;
base->GPR2 |= IOMUXC_GPR_GPR2_MQS_EN_MASK;
}
else
{
base->GPR2 &= ~IOMUXC_GPR_GPR2_MQS_EN_MASK;
base->GPR2 &= ~IOMUXC_GPR_GPR2_MQS_EN_MASK;
}
}
/*!
* @brief Configure MQS PWM oversampling rate compared with mclk and divider ratio control for mclk from hmclk.
* @brief Configure MQS PWM oversampling rate compared with mclk and divider ratio control for mclk from hmclk.
*
* @param base The IOMUXC GPR base address.
* @param rate The MQS PWM oversampling rate, refer to "iomuxc_mqs_pwm_oversample_rate_t".
@ -1402,7 +1401,7 @@ static inline void IOMUXC_MQSEnable(IOMUXC_GPR_Type *base, bool enable)
static inline void IOMUXC_MQSConfig(IOMUXC_GPR_Type *base, iomuxc_mqs_pwm_oversample_rate_t rate, uint8_t divider)
{
uint32_t gpr = base->GPR2 & ~(IOMUXC_GPR_GPR2_MQS_OVERSAMPLE_MASK | IOMUXC_GPR_GPR2_MQS_CLK_DIV_MASK);
base->GPR2 = gpr | IOMUXC_GPR_GPR2_MQS_OVERSAMPLE(rate) | IOMUXC_GPR_GPR2_MQS_CLK_DIV(divider);
}
@ -1415,4 +1414,3 @@ static inline void IOMUXC_MQSConfig(IOMUXC_GPR_Type *base, iomuxc_mqs_pwm_oversa
/*! @}*/
#endif /* _FSL_IOMUXC_H_ */

9718
ext/hal/nxp/mcux/devices/MK64F12/MK64F12.h
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File diff suppressed because it is too large Load diff

30876
ext/hal/nxp/mcux/devices/MK64F12/MK64F12.xml
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File diff suppressed because it is too large Load diff

434
ext/hal/nxp/mcux/devices/MK64F12/MK64F12_features.h
View file

@ -1,37 +1,15 @@
/*
** ###################################################################
** Version: rev. 2.15, 2016-03-21
** Build: b170228
** Build: b180801
**
** Abstract:
** Chip specific module features.
**
** Copyright 2016 Freescale Semiconductor, Inc.
** Copyright 2016-2017 NXP
** Redistribution and use in source and binary forms, with or without modification,
** are permitted provided that the following conditions are met:
** Copyright 2016-2018 NXP
**
** o Redistributions of source code must retain the above copyright notice, this list
** of conditions and the following disclaimer.
**
** o Redistributions in binary form must reproduce the above copyright notice, this
** list of conditions and the following disclaimer in the documentation and/or
** other materials provided with the distribution.
**
** o Neither the name of the copyright holder nor the names of its
** contributors may be used to endorse or promote products derived from this
** software without specific prior written permission.
**
** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
** SPDX-License-Identifier: BSD-3-Clause
**
** http: www.nxp.com
** mail: support@nxp.com
@ -95,24 +73,12 @@
#if defined(CPU_MK64FN1M0CAJ12) || defined(CPU_MK64FN1M0VDC12) || defined(CPU_MK64FN1M0VLQ12) || defined(CPU_MK64FN1M0VMD12) || \
defined(CPU_MK64FX512VDC12) || defined(CPU_MK64FX512VLQ12) || defined(CPU_MK64FX512VMD12)
/* @brief ACMP availability on the SoC. */
#define FSL_FEATURE_SOC_ACMP_COUNT (0)
/* @brief ADC16 availability on the SoC. */
#define FSL_FEATURE_SOC_ADC16_COUNT (2)
/* @brief ADC12 availability on the SoC. */
#define FSL_FEATURE_SOC_ADC12_COUNT (0)
/* @brief AFE availability on the SoC. */
#define FSL_FEATURE_SOC_AFE_COUNT (0)
/* @brief AIPS availability on the SoC. */
#define FSL_FEATURE_SOC_AIPS_COUNT (2)
/* @brief AOI availability on the SoC. */
#define FSL_FEATURE_SOC_AOI_COUNT (0)
/* @brief AXBS availability on the SoC. */
#define FSL_FEATURE_SOC_AXBS_COUNT (1)
/* @brief ASMC availability on the SoC. */
#define FSL_FEATURE_SOC_ASMC_COUNT (0)
/* @brief CADC availability on the SoC. */
#define FSL_FEATURE_SOC_CADC_COUNT (0)
/* @brief FLEXCAN availability on the SoC. */
#define FSL_FEATURE_SOC_FLEXCAN_COUNT (1)
/* @brief MMCAU availability on the SoC. */
@ -121,154 +87,54 @@
#define FSL_FEATURE_SOC_CMP_COUNT (3)
/* @brief CMT availability on the SoC. */
#define FSL_FEATURE_SOC_CMT_COUNT (1)
/* @brief CNC availability on the SoC. */
#define FSL_FEATURE_SOC_CNC_COUNT (0)
/* @brief CRC availability on the SoC. */
#define FSL_FEATURE_SOC_CRC_COUNT (1)
/* @brief DAC availability on the SoC. */
#define FSL_FEATURE_SOC_DAC_COUNT (2)
/* @brief DAC32 availability on the SoC. */
#define FSL_FEATURE_SOC_DAC32_COUNT (0)
/* @brief DCDC availability on the SoC. */
#define FSL_FEATURE_SOC_DCDC_COUNT (0)
/* @brief DDR availability on the SoC. */
#define FSL_FEATURE_SOC_DDR_COUNT (0)
/* @brief DMA availability on the SoC. */
#define FSL_FEATURE_SOC_DMA_COUNT (0)
/* @brief EDMA availability on the SoC. */
#define FSL_FEATURE_SOC_EDMA_COUNT (1)
/* @brief DMAMUX availability on the SoC. */
#define FSL_FEATURE_SOC_DMAMUX_COUNT (1)
/* @brief DRY availability on the SoC. */
#define FSL_FEATURE_SOC_DRY_COUNT (0)
/* @brief DSPI availability on the SoC. */
#define FSL_FEATURE_SOC_DSPI_COUNT (3)
/* @brief EMVSIM availability on the SoC. */
#define FSL_FEATURE_SOC_EMVSIM_COUNT (0)
/* @brief ENC availability on the SoC. */
#define FSL_FEATURE_SOC_ENC_COUNT (0)
/* @brief ENET availability on the SoC. */
#define FSL_FEATURE_SOC_ENET_COUNT (1)
/* @brief EWM availability on the SoC. */
#define FSL_FEATURE_SOC_EWM_COUNT (1)
/* @brief FB availability on the SoC. */
#define FSL_FEATURE_SOC_FB_COUNT (1)
/* @brief FGPIO availability on the SoC. */
#define FSL_FEATURE_SOC_FGPIO_COUNT (0)
/* @brief FLEXIO availability on the SoC. */
#define FSL_FEATURE_SOC_FLEXIO_COUNT (0)
/* @brief FMC availability on the SoC. */
#define FSL_FEATURE_SOC_FMC_COUNT (1)
/* @brief FSKDT availability on the SoC. */
#define FSL_FEATURE_SOC_FSKDT_COUNT (0)
/* @brief FTFA availability on the SoC. */
#define FSL_FEATURE_SOC_FTFA_COUNT (0)
/* @brief FTFE availability on the SoC. */
#define FSL_FEATURE_SOC_FTFE_COUNT (1)
/* @brief FTFL availability on the SoC. */
#define FSL_FEATURE_SOC_FTFL_COUNT (0)
/* @brief FTM availability on the SoC. */
#define FSL_FEATURE_SOC_FTM_COUNT (4)
/* @brief FTMRA availability on the SoC. */
#define FSL_FEATURE_SOC_FTMRA_COUNT (0)
/* @brief FTMRE availability on the SoC. */
#define FSL_FEATURE_SOC_FTMRE_COUNT (0)
/* @brief FTMRH availability on the SoC. */
#define FSL_FEATURE_SOC_FTMRH_COUNT (0)
/* @brief GPIO availability on the SoC. */
#define FSL_FEATURE_SOC_GPIO_COUNT (5)
/* @brief HSADC availability on the SoC. */
#define FSL_FEATURE_SOC_HSADC_COUNT (0)
/* @brief I2C availability on the SoC. */
#define FSL_FEATURE_SOC_I2C_COUNT (3)
/* @brief I2S availability on the SoC. */
#define FSL_FEATURE_SOC_I2S_COUNT (1)
/* @brief ICS availability on the SoC. */
#define FSL_FEATURE_SOC_ICS_COUNT (0)
/* @brief INTMUX availability on the SoC. */
#define FSL_FEATURE_SOC_INTMUX_COUNT (0)
/* @brief IRQ availability on the SoC. */
#define FSL_FEATURE_SOC_IRQ_COUNT (0)
/* @brief KBI availability on the SoC. */
#define FSL_FEATURE_SOC_KBI_COUNT (0)
/* @brief SLCD availability on the SoC. */
#define FSL_FEATURE_SOC_SLCD_COUNT (0)
/* @brief LCDC availability on the SoC. */
#define FSL_FEATURE_SOC_LCDC_COUNT (0)
/* @brief LDO availability on the SoC. */
#define FSL_FEATURE_SOC_LDO_COUNT (0)
/* @brief LLWU availability on the SoC. */
#define FSL_FEATURE_SOC_LLWU_COUNT (1)
/* @brief LMEM availability on the SoC. */
#define FSL_FEATURE_SOC_LMEM_COUNT (0)
/* @brief LPI2C availability on the SoC. */
#define FSL_FEATURE_SOC_LPI2C_COUNT (0)
/* @brief LPIT availability on the SoC. */
#define FSL_FEATURE_SOC_LPIT_COUNT (0)
/* @brief LPSCI availability on the SoC. */
#define FSL_FEATURE_SOC_LPSCI_COUNT (0)
/* @brief LPSPI availability on the SoC. */
#define FSL_FEATURE_SOC_LPSPI_COUNT (0)
/* @brief LPTMR availability on the SoC. */
#define FSL_FEATURE_SOC_LPTMR_COUNT (1)
/* @brief LPTPM availability on the SoC. */
#define FSL_FEATURE_SOC_LPTPM_COUNT (0)
/* @brief LPUART availability on the SoC. */
#define FSL_FEATURE_SOC_LPUART_COUNT (0)
/* @brief LTC availability on the SoC. */
#define FSL_FEATURE_SOC_LTC_COUNT (0)
/* @brief MC availability on the SoC. */
#define FSL_FEATURE_SOC_MC_COUNT (0)
/* @brief MCG availability on the SoC. */
#define FSL_FEATURE_SOC_MCG_COUNT (1)
/* @brief MCGLITE availability on the SoC. */
#define FSL_FEATURE_SOC_MCGLITE_COUNT (0)
/* @brief MCM availability on the SoC. */
#define FSL_FEATURE_SOC_MCM_COUNT (1)
/* @brief MMAU availability on the SoC. */
#define FSL_FEATURE_SOC_MMAU_COUNT (0)
/* @brief MMDVSQ availability on the SoC. */
#define FSL_FEATURE_SOC_MMDVSQ_COUNT (0)
/* @brief SYSMPU availability on the SoC. */
#define FSL_FEATURE_SOC_SYSMPU_COUNT (1)
/* @brief MSCAN availability on the SoC. */
#define FSL_FEATURE_SOC_MSCAN_COUNT (0)
/* @brief MSCM availability on the SoC. */
#define FSL_FEATURE_SOC_MSCM_COUNT (0)
/* @brief MTB availability on the SoC. */
#define FSL_FEATURE_SOC_MTB_COUNT (0)
/* @brief MTBDWT availability on the SoC. */
#define FSL_FEATURE_SOC_MTBDWT_COUNT (0)
/* @brief MU availability on the SoC. */
#define FSL_FEATURE_SOC_MU_COUNT (0)
/* @brief NFC availability on the SoC. */
#define FSL_FEATURE_SOC_NFC_COUNT (0)
/* @brief OPAMP availability on the SoC. */
#define FSL_FEATURE_SOC_OPAMP_COUNT (0)
/* @brief OSC availability on the SoC. */
#define FSL_FEATURE_SOC_OSC_COUNT (1)
/* @brief OSC32 availability on the SoC. */
#define FSL_FEATURE_SOC_OSC32_COUNT (0)
/* @brief OTFAD availability on the SoC. */
#define FSL_FEATURE_SOC_OTFAD_COUNT (0)
/* @brief PDB availability on the SoC. */
#define FSL_FEATURE_SOC_PDB_COUNT (1)
/* @brief PCC availability on the SoC. */
#define FSL_FEATURE_SOC_PCC_COUNT (0)
/* @brief PGA availability on the SoC. */
#define FSL_FEATURE_SOC_PGA_COUNT (0)
/* @brief PIT availability on the SoC. */
#define FSL_FEATURE_SOC_PIT_COUNT (1)
/* @brief PMC availability on the SoC. */
#define FSL_FEATURE_SOC_PMC_COUNT (1)
/* @brief PORT availability on the SoC. */
#define FSL_FEATURE_SOC_PORT_COUNT (5)
/* @brief PWM availability on the SoC. */
#define FSL_FEATURE_SOC_PWM_COUNT (0)
/* @brief PWT availability on the SoC. */
#define FSL_FEATURE_SOC_PWT_COUNT (0)
/* @brief QuadSPI availability on the SoC. */
#define FSL_FEATURE_SOC_QuadSPI_COUNT (0)
/* @brief RCM availability on the SoC. */
#define FSL_FEATURE_SOC_RCM_COUNT (1)
/* @brief RFSYS availability on the SoC. */
@ -277,91 +143,31 @@
#define FSL_FEATURE_SOC_RFVBAT_COUNT (1)
/* @brief RNG availability on the SoC. */
#define FSL_FEATURE_SOC_RNG_COUNT (1)
/* @brief RNGB availability on the SoC. */
#define FSL_FEATURE_SOC_RNGB_COUNT (0)
/* @brief ROM availability on the SoC. */
#define FSL_FEATURE_SOC_ROM_COUNT (0)
/* @brief RSIM availability on the SoC. */
#define FSL_FEATURE_SOC_RSIM_COUNT (0)
/* @brief RTC availability on the SoC. */
#define FSL_FEATURE_SOC_RTC_COUNT (1)
/* @brief SCG availability on the SoC. */
#define FSL_FEATURE_SOC_SCG_COUNT (0)
/* @brief SCI availability on the SoC. */
#define FSL_FEATURE_SOC_SCI_COUNT (0)
/* @brief SDHC availability on the SoC. */
#define FSL_FEATURE_SOC_SDHC_COUNT (1)
/* @brief SDRAM availability on the SoC. */
#define FSL_FEATURE_SOC_SDRAM_COUNT (0)
/* @brief SEMA42 availability on the SoC. */
#define FSL_FEATURE_SOC_SEMA42_COUNT (0)
/* @brief SIM availability on the SoC. */
#define FSL_FEATURE_SOC_SIM_COUNT (1)
/* @brief SMC availability on the SoC. */
#define FSL_FEATURE_SOC_SMC_COUNT (1)
/* @brief SPI availability on the SoC. */
#define FSL_FEATURE_SOC_SPI_COUNT (0)
/* @brief TMR availability on the SoC. */
#define FSL_FEATURE_SOC_TMR_COUNT (0)
/* @brief TPM availability on the SoC. */
#define FSL_FEATURE_SOC_TPM_COUNT (0)
/* @brief TRGMUX availability on the SoC. */
#define FSL_FEATURE_SOC_TRGMUX_COUNT (0)
/* @brief TRIAMP availability on the SoC. */
#define FSL_FEATURE_SOC_TRIAMP_COUNT (0)
/* @brief TRNG availability on the SoC. */
#define FSL_FEATURE_SOC_TRNG_COUNT (0)
/* @brief TSI availability on the SoC. */
#define FSL_FEATURE_SOC_TSI_COUNT (0)
/* @brief TSTMR availability on the SoC. */
#define FSL_FEATURE_SOC_TSTMR_COUNT (0)
/* @brief UART availability on the SoC. */
#define FSL_FEATURE_SOC_UART_COUNT (6)
/* @brief USB availability on the SoC. */
#define FSL_FEATURE_SOC_USB_COUNT (1)
/* @brief USBDCD availability on the SoC. */
#define FSL_FEATURE_SOC_USBDCD_COUNT (1)
/* @brief USBHS availability on the SoC. */
#define FSL_FEATURE_SOC_USBHS_COUNT (0)
/* @brief USBHSDCD availability on the SoC. */
#define FSL_FEATURE_SOC_USBHSDCD_COUNT (0)
/* @brief USBPHY availability on the SoC. */
#define FSL_FEATURE_SOC_USBPHY_COUNT (0)
/* @brief VREF availability on the SoC. */
#define FSL_FEATURE_SOC_VREF_COUNT (1)
/* @brief WDOG availability on the SoC. */
#define FSL_FEATURE_SOC_WDOG_COUNT (1)
/* @brief XBAR availability on the SoC. */
#define FSL_FEATURE_SOC_XBAR_COUNT (0)
/* @brief XBARA availability on the SoC. */
#define FSL_FEATURE_SOC_XBARA_COUNT (0)
/* @brief XBARB availability on the SoC. */
#define FSL_FEATURE_SOC_XBARB_COUNT (0)
/* @brief XCVR availability on the SoC. */
#define FSL_FEATURE_SOC_XCVR_COUNT (0)
/* @brief XRDC availability on the SoC. */
#define FSL_FEATURE_SOC_XRDC_COUNT (0)
/* @brief ZLL availability on the SoC. */
#define FSL_FEATURE_SOC_ZLL_COUNT (0)
#elif defined(CPU_MK64FN1M0VLL12) || defined(CPU_MK64FX512VLL12)
/* @brief ACMP availability on the SoC. */
#define FSL_FEATURE_SOC_ACMP_COUNT (0)
/* @brief ADC16 availability on the SoC. */
#define FSL_FEATURE_SOC_ADC16_COUNT (2)
/* @brief ADC12 availability on the SoC. */
#define FSL_FEATURE_SOC_ADC12_COUNT (0)
/* @brief AFE availability on the SoC. */
#define FSL_FEATURE_SOC_AFE_COUNT (0)
/* @brief AIPS availability on the SoC. */
#define FSL_FEATURE_SOC_AIPS_COUNT (2)
/* @brief AOI availability on the SoC. */
#define FSL_FEATURE_SOC_AOI_COUNT (0)
/* @brief AXBS availability on the SoC. */
#define FSL_FEATURE_SOC_AXBS_COUNT (1)
/* @brief ASMC availability on the SoC. */
#define FSL_FEATURE_SOC_ASMC_COUNT (0)
/* @brief CADC availability on the SoC. */
#define FSL_FEATURE_SOC_CADC_COUNT (0)
/* @brief FLEXCAN availability on the SoC. */
#define FSL_FEATURE_SOC_FLEXCAN_COUNT (1)
/* @brief MMCAU availability on the SoC. */
@ -370,154 +176,54 @@
#define FSL_FEATURE_SOC_CMP_COUNT (3)
/* @brief CMT availability on the SoC. */
#define FSL_FEATURE_SOC_CMT_COUNT (1)
/* @brief CNC availability on the SoC. */
#define FSL_FEATURE_SOC_CNC_COUNT (0)
/* @brief CRC availability on the SoC. */
#define FSL_FEATURE_SOC_CRC_COUNT (1)
/* @brief DAC availability on the SoC. */
#define FSL_FEATURE_SOC_DAC_COUNT (1)
/* @brief DAC32 availability on the SoC. */
#define FSL_FEATURE_SOC_DAC32_COUNT (0)
/* @brief DCDC availability on the SoC. */
#define FSL_FEATURE_SOC_DCDC_COUNT (0)
/* @brief DDR availability on the SoC. */
#define FSL_FEATURE_SOC_DDR_COUNT (0)
/* @brief DMA availability on the SoC. */
#define FSL_FEATURE_SOC_DMA_COUNT (0)
/* @brief EDMA availability on the SoC. */
#define FSL_FEATURE_SOC_EDMA_COUNT (1)
/* @brief DMAMUX availability on the SoC. */
#define FSL_FEATURE_SOC_DMAMUX_COUNT (1)
/* @brief DRY availability on the SoC. */
#define FSL_FEATURE_SOC_DRY_COUNT (0)
/* @brief DSPI availability on the SoC. */
#define FSL_FEATURE_SOC_DSPI_COUNT (3)
/* @brief EMVSIM availability on the SoC. */
#define FSL_FEATURE_SOC_EMVSIM_COUNT (0)
/* @brief ENC availability on the SoC. */
#define FSL_FEATURE_SOC_ENC_COUNT (0)
/* @brief ENET availability on the SoC. */
#define FSL_FEATURE_SOC_ENET_COUNT (1)
/* @brief EWM availability on the SoC. */
#define FSL_FEATURE_SOC_EWM_COUNT (1)
/* @brief FB availability on the SoC. */
#define FSL_FEATURE_SOC_FB_COUNT (1)
/* @brief FGPIO availability on the SoC. */
#define FSL_FEATURE_SOC_FGPIO_COUNT (0)
/* @brief FLEXIO availability on the SoC. */
#define FSL_FEATURE_SOC_FLEXIO_COUNT (0)
/* @brief FMC availability on the SoC. */
#define FSL_FEATURE_SOC_FMC_COUNT (1)
/* @brief FSKDT availability on the SoC. */
#define FSL_FEATURE_SOC_FSKDT_COUNT (0)
/* @brief FTFA availability on the SoC. */
#define FSL_FEATURE_SOC_FTFA_COUNT (0)
/* @brief FTFE availability on the SoC. */
#define FSL_FEATURE_SOC_FTFE_COUNT (1)
/* @brief FTFL availability on the SoC. */
#define FSL_FEATURE_SOC_FTFL_COUNT (0)
/* @brief FTM availability on the SoC. */
#define FSL_FEATURE_SOC_FTM_COUNT (4)
/* @brief FTMRA availability on the SoC. */
#define FSL_FEATURE_SOC_FTMRA_COUNT (0)
/* @brief FTMRE availability on the SoC. */
#define FSL_FEATURE_SOC_FTMRE_COUNT (0)
/* @brief FTMRH availability on the SoC. */
#define FSL_FEATURE_SOC_FTMRH_COUNT (0)
/* @brief GPIO availability on the SoC. */
#define FSL_FEATURE_SOC_GPIO_COUNT (5)
/* @brief HSADC availability on the SoC. */
#define FSL_FEATURE_SOC_HSADC_COUNT (0)
/* @brief I2C availability on the SoC. */
#define FSL_FEATURE_SOC_I2C_COUNT (3)
/* @brief I2S availability on the SoC. */
#define FSL_FEATURE_SOC_I2S_COUNT (1)
/* @brief ICS availability on the SoC. */
#define FSL_FEATURE_SOC_ICS_COUNT (0)
/* @brief INTMUX availability on the SoC. */
#define FSL_FEATURE_SOC_INTMUX_COUNT (0)
/* @brief IRQ availability on the SoC. */
#define FSL_FEATURE_SOC_IRQ_COUNT (0)
/* @brief KBI availability on the SoC. */
#define FSL_FEATURE_SOC_KBI_COUNT (0)
/* @brief SLCD availability on the SoC. */
#define FSL_FEATURE_SOC_SLCD_COUNT (0)
/* @brief LCDC availability on the SoC. */
#define FSL_FEATURE_SOC_LCDC_COUNT (0)
/* @brief LDO availability on the SoC. */
#define FSL_FEATURE_SOC_LDO_COUNT (0)
/* @brief LLWU availability on the SoC. */
#define FSL_FEATURE_SOC_LLWU_COUNT (1)
/* @brief LMEM availability on the SoC. */
#define FSL_FEATURE_SOC_LMEM_COUNT (0)
/* @brief LPI2C availability on the SoC. */
#define FSL_FEATURE_SOC_LPI2C_COUNT (0)
/* @brief LPIT availability on the SoC. */
#define FSL_FEATURE_SOC_LPIT_COUNT (0)
/* @brief LPSCI availability on the SoC. */
#define FSL_FEATURE_SOC_LPSCI_COUNT (0)
/* @brief LPSPI availability on the SoC. */
#define FSL_FEATURE_SOC_LPSPI_COUNT (0)
/* @brief LPTMR availability on the SoC. */
#define FSL_FEATURE_SOC_LPTMR_COUNT (1)
/* @brief LPTPM availability on the SoC. */
#define FSL_FEATURE_SOC_LPTPM_COUNT (0)
/* @brief LPUART availability on the SoC. */
#define FSL_FEATURE_SOC_LPUART_COUNT (0)
/* @brief LTC availability on the SoC. */
#define FSL_FEATURE_SOC_LTC_COUNT (0)
/* @brief MC availability on the SoC. */
#define FSL_FEATURE_SOC_MC_COUNT (0)
/* @brief MCG availability on the SoC. */
#define FSL_FEATURE_SOC_MCG_COUNT (1)
/* @brief MCGLITE availability on the SoC. */
#define FSL_FEATURE_SOC_MCGLITE_COUNT (0)
/* @brief MCM availability on the SoC. */
#define FSL_FEATURE_SOC_MCM_COUNT (1)
/* @brief MMAU availability on the SoC. */
#define FSL_FEATURE_SOC_MMAU_COUNT (0)
/* @brief MMDVSQ availability on the SoC. */
#define FSL_FEATURE_SOC_MMDVSQ_COUNT (0)
/* @brief SYSMPU availability on the SoC. */
#define FSL_FEATURE_SOC_SYSMPU_COUNT (1)
/* @brief MSCAN availability on the SoC. */
#define FSL_FEATURE_SOC_MSCAN_COUNT (0)
/* @brief MSCM availability on the SoC. */
#define FSL_FEATURE_SOC_MSCM_COUNT (0)
/* @brief MTB availability on the SoC. */
#define FSL_FEATURE_SOC_MTB_COUNT (0)
/* @brief MTBDWT availability on the SoC. */
#define FSL_FEATURE_SOC_MTBDWT_COUNT (0)
/* @brief MU availability on the SoC. */
#define FSL_FEATURE_SOC_MU_COUNT (0)
/* @brief NFC availability on the SoC. */
#define FSL_FEATURE_SOC_NFC_COUNT (0)
/* @brief OPAMP availability on the SoC. */
#define FSL_FEATURE_SOC_OPAMP_COUNT (0)
/* @brief OSC availability on the SoC. */
#define FSL_FEATURE_SOC_OSC_COUNT (1)
/* @brief OSC32 availability on the SoC. */
#define FSL_FEATURE_SOC_OSC32_COUNT (0)
/* @brief OTFAD availability on the SoC. */
#define FSL_FEATURE_SOC_OTFAD_COUNT (0)
/* @brief PDB availability on the SoC. */
#define FSL_FEATURE_SOC_PDB_COUNT (1)
/* @brief PCC availability on the SoC. */
#define FSL_FEATURE_SOC_PCC_COUNT (0)
/* @brief PGA availability on the SoC. */
#define FSL_FEATURE_SOC_PGA_COUNT (0)
/* @brief PIT availability on the SoC. */
#define FSL_FEATURE_SOC_PIT_COUNT (1)
/* @brief PMC availability on the SoC. */
#define FSL_FEATURE_SOC_PMC_COUNT (1)
/* @brief PORT availability on the SoC. */
#define FSL_FEATURE_SOC_PORT_COUNT (5)
/* @brief PWM availability on the SoC. */
#define FSL_FEATURE_SOC_PWM_COUNT (0)
/* @brief PWT availability on the SoC. */
#define FSL_FEATURE_SOC_PWT_COUNT (0)
/* @brief QuadSPI availability on the SoC. */
#define FSL_FEATURE_SOC_QuadSPI_COUNT (0)
/* @brief RCM availability on the SoC. */
#define FSL_FEATURE_SOC_RCM_COUNT (1)
/* @brief RFSYS availability on the SoC. */
@ -526,72 +232,24 @@
#define FSL_FEATURE_SOC_RFVBAT_COUNT (1)
/* @brief RNG availability on the SoC. */
#define FSL_FEATURE_SOC_RNG_COUNT (1)
/* @brief RNGB availability on the SoC. */
#define FSL_FEATURE_SOC_RNGB_COUNT (0)
/* @brief ROM availability on the SoC. */
#define FSL_FEATURE_SOC_ROM_COUNT (0)
/* @brief RSIM availability on the SoC. */
#define FSL_FEATURE_SOC_RSIM_COUNT (0)
/* @brief RTC availability on the SoC. */
#define FSL_FEATURE_SOC_RTC_COUNT (1)
/* @brief SCG availability on the SoC. */
#define FSL_FEATURE_SOC_SCG_COUNT (0)
/* @brief SCI availability on the SoC. */
#define FSL_FEATURE_SOC_SCI_COUNT (0)
/* @brief SDHC availability on the SoC. */
#define FSL_FEATURE_SOC_SDHC_COUNT (1)
/* @brief SDRAM availability on the SoC. */
#define FSL_FEATURE_SOC_SDRAM_COUNT (0)
/* @brief SEMA42 availability on the SoC. */
#define FSL_FEATURE_SOC_SEMA42_COUNT (0)
/* @brief SIM availability on the SoC. */
#define FSL_FEATURE_SOC_SIM_COUNT (1)
/* @brief SMC availability on the SoC. */
#define FSL_FEATURE_SOC_SMC_COUNT (1)
/* @brief SPI availability on the SoC. */
#define FSL_FEATURE_SOC_SPI_COUNT (0)
/* @brief TMR availability on the SoC. */
#define FSL_FEATURE_SOC_TMR_COUNT (0)
/* @brief TPM availability on the SoC. */
#define FSL_FEATURE_SOC_TPM_COUNT (0)
/* @brief TRGMUX availability on the SoC. */
#define FSL_FEATURE_SOC_TRGMUX_COUNT (0)
/* @brief TRIAMP availability on the SoC. */
#define FSL_FEATURE_SOC_TRIAMP_COUNT (0)
/* @brief TRNG availability on the SoC. */
#define FSL_FEATURE_SOC_TRNG_COUNT (0)
/* @brief TSI availability on the SoC. */
#define FSL_FEATURE_SOC_TSI_COUNT (0)
/* @brief TSTMR availability on the SoC. */
#define FSL_FEATURE_SOC_TSTMR_COUNT (0)
/* @brief UART availability on the SoC. */
#define FSL_FEATURE_SOC_UART_COUNT (5)
/* @brief USB availability on the SoC. */
#define FSL_FEATURE_SOC_USB_COUNT (1)
/* @brief USBDCD availability on the SoC. */
#define FSL_FEATURE_SOC_USBDCD_COUNT (1)
/* @brief USBHS availability on the SoC. */
#define FSL_FEATURE_SOC_USBHS_COUNT (0)
/* @brief USBHSDCD availability on the SoC. */
#define FSL_FEATURE_SOC_USBHSDCD_COUNT (0)
/* @brief USBPHY availability on the SoC. */
#define FSL_FEATURE_SOC_USBPHY_COUNT (0)
/* @brief VREF availability on the SoC. */
#define FSL_FEATURE_SOC_VREF_COUNT (1)
/* @brief WDOG availability on the SoC. */
#define FSL_FEATURE_SOC_WDOG_COUNT (1)
/* @brief XBAR availability on the SoC. */
#define FSL_FEATURE_SOC_XBAR_COUNT (0)
/* @brief XBARA availability on the SoC. */
#define FSL_FEATURE_SOC_XBARA_COUNT (0)
/* @brief XBARB availability on the SoC. */
#define FSL_FEATURE_SOC_XBARB_COUNT (0)
/* @brief XCVR availability on the SoC. */
#define FSL_FEATURE_SOC_XCVR_COUNT (0)
/* @brief XRDC availability on the SoC. */
#define FSL_FEATURE_SOC_XRDC_COUNT (0)
/* @brief ZLL availability on the SoC. */
#define FSL_FEATURE_SOC_ZLL_COUNT (0)
#endif
/* ADC16 module features */
@ -631,14 +289,18 @@
#define FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(x) (16)
/* @brief Has doze mode support (register bit field MCR[DOZE]). */
#define FSL_FEATURE_FLEXCAN_HAS_DOZE_MODE_SUPPORT (0)
/* @brief Insatnce has doze mode support (register bit field MCR[DOZE]). */
#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_DOZE_MODE_SUPPORTn(x) (0)
/* @brief Has a glitch filter on the receive pin (register bit field MCR[WAKSRC]). */
#define FSL_FEATURE_FLEXCAN_HAS_GLITCH_FILTER (1)
/* @brief Has extended interrupt mask and flag register (register IMASK2, IFLAG2). */
#define FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER (0)
/* @brief Has extended bit timing register (register CBT). */
#define FSL_FEATURE_FLEXCAN_HAS_EXTENDED_TIMING_REGISTER (0)
/* @brief Instance has extended bit timing register (register CBT). */
#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_EXTENDED_TIMING_REGISTERn(x) (0)
/* @brief Has a receive FIFO DMA feature (register bit field MCR[DMA]). */
#define FSL_FEATURE_FLEXCAN_HAS_RX_FIFO_DMA (0)
/* @brief Instance has a receive FIFO DMA feature (register bit field MCR[DMA]). */
#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_RX_FIFO_DMAn(x) (0)
/* @brief Has separate message buffer 0 interrupt flag (register bit field IFLAG1[BUF0I]). */
#define FSL_FEATURE_FLEXCAN_HAS_SEPARATE_BUFFER_0_FLAG (1)
/* @brief Has bitfield name BUF31TO0M. */
@ -761,6 +423,8 @@
#define FSL_FEATURE_FLASH_HAS_MSCM_FLASH_CACHE_CONTROLS (0)
/* @brief Has prefetch speculation control in flash, such as kv5x. */
#define FSL_FEATURE_FLASH_PREFETCH_SPECULATION_CONTROL_IN_FLASH (0)
/* @brief P-Flash flash size coding rule version, value 0 for K1 and K2, value 1 for K3. */
#define FSL_FEATURE_FLASH_SIZE_ENCODING_RULE_VERSION (0)
/* @brief P-Flash start address. */
#define FSL_FEATURE_FLASH_PFLASH_START_ADDRESS (0x00000000)
/* @brief P-Flash block count. */
@ -948,6 +612,8 @@
#define FSL_FEATURE_FLASH_HAS_MSCM_FLASH_CACHE_CONTROLS (0)
/* @brief Has prefetch speculation control in flash, such as kv5x. */
#define FSL_FEATURE_FLASH_PREFETCH_SPECULATION_CONTROL_IN_FLASH (0)
/* @brief P-Flash flash size coding rule version, value 0 for K1 and K2, value 1 for K3. */
#define FSL_FEATURE_FLASH_SIZE_ENCODING_RULE_VERSION (0)
/* @brief P-Flash start address. */
#define FSL_FEATURE_FLASH_PFLASH_START_ADDRESS (0x00000000)
/* @brief P-Flash block count. */
@ -1133,6 +799,14 @@
#define FSL_FEATURE_FTM_HAS_RELOAD_INTERRUPT (0)
/* @brief Has reload initialization trigger. */
#define FSL_FEATURE_FTM_HAS_RELOAD_INITIALIZATION_TRIGGER (0)
/* @brief Has DMA support, bitfield CnSC[DMA]. */
#define FSL_FEATURE_FTM_HAS_DMA_SUPPORT (1)
/* @brief If channel 6 is used to generate channel trigger, bitfield EXTTRIG[CH6TRIG]. */
#define FSL_FEATURE_FTM_HAS_CHANNEL6_TRIGGER (0)
/* @brief If channel 7 is used to generate channel trigger, bitfield EXTTRIG[CH7TRIG]. */
#define FSL_FEATURE_FTM_HAS_CHANNEL7_TRIGGER (0)
/* @brief Has no QDCTRL. */
#define FSL_FEATURE_FTM_HAS_NO_QDCTRL (0)
/* GPIO module features */
@ -1549,6 +1223,8 @@
#define FSL_FEATURE_PIT_HAS_CHAIN_MODE (1)
/* @brief Has shared interrupt handler (has not individual interrupt handler for each channel). */
#define FSL_FEATURE_PIT_HAS_SHARED_IRQ_HANDLER (0)
/* @brief Has timer enable control. */
#define FSL_FEATURE_PIT_HAS_MDIS (1)
/* PMC module features */
@ -1669,6 +1345,28 @@
#define FSL_FEATURE_RTC_HAS_TSIC (0)
/* @brief Has OSC capacitor setting RTC_CR[SC2P ~ SC16P] */
#define FSL_FEATURE_RTC_HAS_OSC_SCXP (1)
/* @brief Has Tamper Interrupt Register (register TIR). */
#define FSL_FEATURE_RTC_HAS_TIR (0)
/* @brief Has Tamper Pin Interrupt Enable (bitfield TIR[TPIE]). */
#define FSL_FEATURE_RTC_HAS_TIR_TPIE (0)
/* @brief Has Security Interrupt Enable (bitfield TIR[SIE]). */
#define FSL_FEATURE_RTC_HAS_TIR_SIE (0)
/* @brief Has Loss of Clock Interrupt Enable (bitfield TIR[LCIE]). */
#define FSL_FEATURE_RTC_HAS_TIR_LCIE (0)
/* @brief Has Tamper Interrupt Detect Flag (bitfield SR[TIDF]). */
#define FSL_FEATURE_RTC_HAS_SR_TIDF (0)
/* @brief Has Tamper Detect Register (register TDR). */
#define FSL_FEATURE_RTC_HAS_TDR (0)
/* @brief Has Tamper Pin Flag (bitfield TDR[TPF]). */
#define FSL_FEATURE_RTC_HAS_TDR_TPF (0)
/* @brief Has Security Tamper Flag (bitfield TDR[STF]). */
#define FSL_FEATURE_RTC_HAS_TDR_STF (0)
/* @brief Has Loss of Clock Tamper Flag (bitfield TDR[LCTF]). */
#define FSL_FEATURE_RTC_HAS_TDR_LCTF (0)
/* @brief Has Tamper Time Seconds Register (register TTSR). */
#define FSL_FEATURE_RTC_HAS_TTSR (0)
/* @brief Has Pin Configuration Register (register PCR). */
#define FSL_FEATURE_RTC_HAS_PCR (0)
#elif defined(CPU_MK64FN1M0VMD12) || defined(CPU_MK64FX512VMD12)
/* @brief Has wakeup pin. */
#define FSL_FEATURE_RTC_HAS_WAKEUP_PIN (1)
@ -1690,6 +1388,28 @@
#define FSL_FEATURE_RTC_HAS_TSIC (0)
/* @brief Has OSC capacitor setting RTC_CR[SC2P ~ SC16P] */
#define FSL_FEATURE_RTC_HAS_OSC_SCXP (1)
/* @brief Has Tamper Interrupt Register (register TIR). */
#define FSL_FEATURE_RTC_HAS_TIR (0)
/* @brief Has Tamper Pin Interrupt Enable (bitfield TIR[TPIE]). */
#define FSL_FEATURE_RTC_HAS_TIR_TPIE (0)
/* @brief Has Security Interrupt Enable (bitfield TIR[SIE]). */
#define FSL_FEATURE_RTC_HAS_TIR_SIE (0)
/* @brief Has Loss of Clock Interrupt Enable (bitfield TIR[LCIE]). */
#define FSL_FEATURE_RTC_HAS_TIR_LCIE (0)
/* @brief Has Tamper Interrupt Detect Flag (bitfield SR[TIDF]). */
#define FSL_FEATURE_RTC_HAS_SR_TIDF (0)
/* @brief Has Tamper Detect Register (register TDR). */
#define FSL_FEATURE_RTC_HAS_TDR (0)
/* @brief Has Tamper Pin Flag (bitfield TDR[TPF]). */
#define FSL_FEATURE_RTC_HAS_TDR_TPF (0)
/* @brief Has Security Tamper Flag (bitfield TDR[STF]). */
#define FSL_FEATURE_RTC_HAS_TDR_STF (0)
/* @brief Has Loss of Clock Tamper Flag (bitfield TDR[LCTF]). */
#define FSL_FEATURE_RTC_HAS_TDR_LCTF (0)
/* @brief Has Tamper Time Seconds Register (register TTSR). */
#define FSL_FEATURE_RTC_HAS_TTSR (0)
/* @brief Has Pin Configuration Register (register PCR). */
#define FSL_FEATURE_RTC_HAS_PCR (0)
#endif /* defined(CPU_MK64FN1M0CAJ12) || defined(CPU_MK64FN1M0VDC12) || defined(CPU_MK64FN1M0VLL12) || defined(CPU_MK64FN1M0VLQ12) || \
defined(CPU_MK64FX512VDC12) || defined(CPU_MK64FX512VLL12) || defined(CPU_MK64FX512VLQ12) */
@ -1975,6 +1695,8 @@
#define FSL_FEATURE_SMC_HAS_SUB_STOP_MODE (1)
/* @brief Has stop submode 0(VLLS0). */
#define FSL_FEATURE_SMC_HAS_STOP_SUBMODE0 (1)
/* @brief Has stop submode 1(VLLS1). */
#define FSL_FEATURE_SMC_HAS_STOP_SUBMODE1 (1)
/* @brief Has stop submode 2(VLLS2). */
#define FSL_FEATURE_SMC_HAS_STOP_SUBMODE2 (1)
/* @brief Has SMC_PARAM. */
@ -1992,15 +1714,17 @@
/* @brief Receive/transmit FIFO size in number of items. */
#define FSL_FEATURE_DSPI_FIFO_SIZEn(x) \
((x) == DSPI0 ? (4) : \
((x) == DSPI1 ? (1) : \
((x) == DSPI2 ? (1) : (-1))))
((x) == SPI0 ? (4) : \
((x) == SPI1 ? (1) : \
((x) == SPI2 ? (1) : (-1))))
/* @brief Maximum transfer data width in bits. */
#define FSL_FEATURE_DSPI_MAX_DATA_WIDTH (16)
/* @brief Maximum number of chip select pins. (Reflects the width of register bit field PUSHR[PCS].) */
#define FSL_FEATURE_DSPI_MAX_CHIP_SELECT_COUNT (6)
/* @brief Number of chip select pins. */
#define FSL_FEATURE_DSPI_CHIP_SELECT_COUNT (6)
/* @brief Number of CTAR registers. */
#define FSL_FEATURE_DSPI_CTAR_COUNT (2)
/* @brief Has chip select strobe capability on the PCS5 pin. */
#define FSL_FEATURE_DSPI_HAS_CHIP_SELECT_STROBE (1)
/* @brief Has separated TXDATA and CMD FIFOs (register SREX). */
@ -2009,9 +1733,9 @@
#define FSL_FEATURE_DSPI_16BIT_TRANSFERS (1)
/* @brief Has separate DMA RX and TX requests. */
#define FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(x) \
((x) == DSPI0 ? (1) : \
((x) == DSPI1 ? (0) : \
((x) == DSPI2 ? (0) : (-1))))
((x) == SPI0 ? (1) : \
((x) == SPI1 ? (0) : \
((x) == SPI2 ? (0) : (-1))))
/* SYSMPU module features */
@ -2189,6 +1913,10 @@
#define FSL_FEATURE_USB_KHCI_IRC48M_MODULE_CLOCK_ENABLED (1)
/* @brief Number of endpoints supported */
#define FSL_FEATURE_USB_ENDPT_COUNT (16)
/* @brief Has STALL_IL/OL_DIS registers */
#define FSL_FEATURE_USB_KHCI_HAS_STALL_LOW (0)
/* @brief Has STALL_IH/OH_DIS registers */
#define FSL_FEATURE_USB_KHCI_HAS_STALL_HIGH (0)
/* VREF module features */

540
ext/hal/nxp/mcux/devices/MK64F12/fsl_clock.c
View file

@ -3,30 +3,8 @@
* Copyright (c) 2016 - 2017 , NXP
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* SPDX-License-Identifier: BSD-3-Clause
*/
#include "fsl_clock.h"
@ -34,6 +12,10 @@
/*******************************************************************************
* Definitions
******************************************************************************/
/* Component ID definition, used by tools. */
#ifndef FSL_COMPONENT_ID
#define FSL_COMPONENT_ID "platform.drivers.clock"
#endif
/* Macro definition remap workaround. */
#if (defined(MCG_C2_EREFS_MASK) && !(defined(MCG_C2_EREFS0_MASK)))
@ -119,9 +101,9 @@ static uint32_t s_slowIrcFreq = 32768U;
static uint32_t s_fastIrcFreq = 4000000U;
/* External XTAL0 (OSC0) clock frequency. */
uint32_t g_xtal0Freq;
volatile uint32_t g_xtal0Freq;
/* External XTAL32K clock frequency. */
uint32_t g_xtal32Freq;
volatile uint32_t g_xtal32Freq;
/*******************************************************************************
* Prototypes
@ -190,10 +172,6 @@ static uint32_t CLOCK_GetPll0RefFreq(void);
*/
static uint8_t CLOCK_GetOscRangeFromFreq(uint32_t freq);
/*******************************************************************************
* Code
******************************************************************************/
#ifndef MCG_USER_CONFIG_FLL_STABLE_DELAY_EN
/*!
* @brief Delay function to wait FLL stable.
@ -201,7 +179,15 @@ static uint8_t CLOCK_GetOscRangeFromFreq(uint32_t freq);
* Delay function to wait FLL stable in FEI mode or FEE mode, should wait at least
* 1ms. Every time changes FLL setting, should wait this time for FLL stable.
*/
void CLOCK_FllStableDelay(void)
static void CLOCK_FllStableDelay(void);
#endif
/*******************************************************************************
* Code
******************************************************************************/
#ifndef MCG_USER_CONFIG_FLL_STABLE_DELAY_EN
static void CLOCK_FllStableDelay(void)
{
/*
Should wait at least 1ms. Because in these modes, the core clock is 100MHz
@ -216,7 +202,7 @@ void CLOCK_FllStableDelay(void)
#else /* With MCG_USER_CONFIG_FLL_STABLE_DELAY_EN defined. */
/* Once user defines the MCG_USER_CONFIG_FLL_STABLE_DELAY_EN to use their own delay function, he has to
* create his own CLOCK_FllStableDelay() function in application code. Since the clock functions in this
* file would call the CLOCK_FllStableDelay() regardness how it is defined.
* file would call the CLOCK_FllStableDelay() regardless how it is defined.
*/
extern void CLOCK_FllStableDelay(void);
#endif /* MCG_USER_CONFIG_FLL_STABLE_DELAY_EN */
@ -356,6 +342,11 @@ static uint8_t CLOCK_GetOscRangeFromFreq(uint32_t freq)
return range;
}
/*!
* brief Get the OSC0 external reference clock frequency (OSC0ERCLK).
*
* return Clock frequency in Hz.
*/
uint32_t CLOCK_GetOsc0ErClkFreq(void)
{
if (OSC0->CR & OSC_CR_ERCLKEN_MASK)
@ -370,6 +361,11 @@ uint32_t CLOCK_GetOsc0ErClkFreq(void)
}
}
/*!
* brief Get the external reference 32K clock frequency (ERCLK32K).
*
* return Clock frequency in Hz.
*/
uint32_t CLOCK_GetEr32kClkFreq(void)
{
uint32_t freq;
@ -394,6 +390,11 @@ uint32_t CLOCK_GetEr32kClkFreq(void)
return freq;
}
/*!
* brief Get the output clock frequency selected by SIM[PLLFLLSEL].
*
* return Clock frequency in Hz.
*/
uint32_t CLOCK_GetPllFllSelClkFreq(void)
{
uint32_t freq;
@ -417,31 +418,66 @@ uint32_t CLOCK_GetPllFllSelClkFreq(void)
return freq;
}
/*!
* brief Get the platform clock frequency.
*
* return Clock frequency in Hz.
*/
uint32_t CLOCK_GetPlatClkFreq(void)
{
return CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV1_VAL + 1);
}
/*!
* brief Get the flash clock frequency.
*
* return Clock frequency in Hz.
*/
uint32_t CLOCK_GetFlashClkFreq(void)
{
return CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV4_VAL + 1);
}
/*!
* brief Get the flexbus clock frequency.
*
* return Clock frequency in Hz.
*/
uint32_t CLOCK_GetFlexBusClkFreq(void)
{
return CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV3_VAL + 1);
}
/*!
* brief Get the bus clock frequency.
*
* return Clock frequency in Hz.
*/
uint32_t CLOCK_GetBusClkFreq(void)
{
return CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV2_VAL + 1);
}
/*!
* brief Get the core clock or system clock frequency.
*
* return Clock frequency in Hz.
*/
uint32_t CLOCK_GetCoreSysClkFreq(void)
{
return CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV1_VAL + 1);
}
/*!
* brief Gets the clock frequency for a specific clock name.
*
* This function checks the current clock configurations and then calculates
* the clock frequency for a specific clock name defined in clock_name_t.
* The MCG must be properly configured before using this function.
*
* param clockName Clock names defined in clock_name_t
* return Clock frequency value in Hertz
*/
uint32_t CLOCK_GetFreq(clock_name_t clockName)
{
uint32_t freq;
@ -496,6 +532,13 @@ uint32_t CLOCK_GetFreq(clock_name_t clockName)
return freq;
}
/*!
* brief Set the clock configure in SIM module.
*
* This function sets system layer clock settings in SIM module.
*
* param config Pointer to the configure structure.
*/
void CLOCK_SetSimConfig(sim_clock_config_t const *config)
{
SIM->CLKDIV1 = config->clkdiv1;
@ -503,6 +546,13 @@ void CLOCK_SetSimConfig(sim_clock_config_t const *config)
CLOCK_SetEr32kClock(config->er32kSrc);
}
/*! brief Enable USB FS clock.
*
* param src USB FS clock source.
* param freq The frequency specified by src.
* retval true The clock is set successfully.
* retval false The clock source is invalid to get proper USB FS clock.
*/
bool CLOCK_EnableUsbfs0Clock(clock_usb_src_t src, uint32_t freq)
{
bool ret = true;
@ -547,6 +597,14 @@ bool CLOCK_EnableUsbfs0Clock(clock_usb_src_t src, uint32_t freq)
return ret;
}
/*!
* brief Gets the MCG output clock (MCGOUTCLK) frequency.
*
* This function gets the MCG output clock frequency in Hz based on the current MCG
* register value.
*
* return The frequency of MCGOUTCLK.
*/
uint32_t CLOCK_GetOutClkFreq(void)
{
uint32_t mcgoutclk;
@ -573,6 +631,15 @@ uint32_t CLOCK_GetOutClkFreq(void)
return mcgoutclk;
}
/*!
* brief Gets the MCG FLL clock (MCGFLLCLK) frequency.
*
* This function gets the MCG FLL clock frequency in Hz based on the current MCG
* register value. The FLL is enabled in FEI/FBI/FEE/FBE mode and
* disabled in low power state in other modes.
*
* return The frequency of MCGFLLCLK.
*/
uint32_t CLOCK_GetFllFreq(void)
{
static const uint16_t fllFactorTable[4][2] = {{640, 732}, {1280, 1464}, {1920, 2197}, {2560, 2929}};
@ -599,6 +666,14 @@ uint32_t CLOCK_GetFllFreq(void)
return freq * fllFactorTable[drs][dmx32];
}
/*!
* brief Gets the MCG internal reference clock (MCGIRCLK) frequency.
*
* This function gets the MCG internal reference clock frequency in Hz based
* on the current MCG register value.
*
* return The frequency of MCGIRCLK.
*/
uint32_t CLOCK_GetInternalRefClkFreq(void)
{
/* If MCGIRCLK is gated. */
@ -610,6 +685,14 @@ uint32_t CLOCK_GetInternalRefClkFreq(void)
return CLOCK_GetInternalRefClkSelectFreq();
}
/*!
* brief Gets the MCG fixed frequency clock (MCGFFCLK) frequency.
*
* This function gets the MCG fixed frequency clock frequency in Hz based
* on the current MCG register value.
*
* return The frequency of MCGFFCLK.
*/
uint32_t CLOCK_GetFixedFreqClkFreq(void)
{
uint32_t freq = CLOCK_GetFllRefClkFreq();
@ -625,6 +708,14 @@ uint32_t CLOCK_GetFixedFreqClkFreq(void)
}
}
/*!
* brief Gets the MCG PLL0 clock (MCGPLL0CLK) frequency.
*
* This function gets the MCG PLL0 clock frequency in Hz based on the current MCG
* register value.
*
* return The frequency of MCGPLL0CLK.
*/
uint32_t CLOCK_GetPll0Freq(void)
{
uint32_t mcgpll0clk;
@ -649,6 +740,18 @@ uint32_t CLOCK_GetPll0Freq(void)
return mcgpll0clk;
}
/*!
* brief Selects the MCG external reference clock.
*
* Selects the MCG external reference clock source, changes the MCG_C7[OSCSEL],
* and waits for the clock source to be stable. Because the external reference
* clock should not be changed in FEE/FBE/BLPE/PBE/PEE modes, do not call this function in these modes.
*
* param oscsel MCG external reference clock source, MCG_C7[OSCSEL].
* retval kStatus_MCG_SourceUsed Because the external reference clock is used as a clock source,
* the configuration should not be changed. Otherwise, a glitch occurs.
* retval kStatus_Success External reference clock set successfully.
*/
status_t CLOCK_SetExternalRefClkConfig(mcg_oscsel_t oscsel)
{
bool needDelay;
@ -686,6 +789,22 @@ status_t CLOCK_SetExternalRefClkConfig(mcg_oscsel_t oscsel)
return kStatus_Success;
}
/*!
* brief Configures the Internal Reference clock (MCGIRCLK).
*
* This function sets the \c MCGIRCLK base on parameters. It also selects the IRC
* source. If the fast IRC is used, this function sets the fast IRC divider.
* This function also sets whether the \c MCGIRCLK is enabled in stop mode.
* Calling this function in FBI/PBI/BLPI modes may change the system clock. As a result,
* using the function in these modes it is not allowed.
*
* param enableMode MCGIRCLK enable mode, OR'ed value of ref _mcg_irclk_enable_mode.
* param ircs MCGIRCLK clock source, choose fast or slow.
* param fcrdiv Fast IRC divider setting (\c FCRDIV).
* retval kStatus_MCG_SourceUsed Because the internal reference clock is used as a clock source,
* the configuration should not be changed. Otherwise, a glitch occurs.
* retval kStatus_Success MCGIRCLK configuration finished successfully.
*/
status_t CLOCK_SetInternalRefClkConfig(uint8_t enableMode, mcg_irc_mode_t ircs, uint8_t fcrdiv)
{
uint32_t mcgOutClkState = MCG_S_CLKST_VAL;
@ -734,6 +853,21 @@ status_t CLOCK_SetInternalRefClkConfig(uint8_t enableMode, mcg_irc_mode_t ircs,
return kStatus_Success;
}
/*!
* brief Calculates the PLL divider setting for a desired output frequency.
*
* This function calculates the correct reference clock divider (\c PRDIV) and
* VCO divider (\c VDIV) to generate a desired PLL output frequency. It returns the
* closest frequency match with the corresponding \c PRDIV/VDIV
* returned from parameters. If a desired frequency is not valid, this function
* returns 0.
*
* param refFreq PLL reference clock frequency.
* param desireFreq Desired PLL output frequency.
* param prdiv PRDIV value to generate desired PLL frequency.
* param vdiv VDIV value to generate desired PLL frequency.
* return Closest frequency match that the PLL was able generate.
*/
uint32_t CLOCK_CalcPllDiv(uint32_t refFreq, uint32_t desireFreq, uint8_t *prdiv, uint8_t *vdiv)
{
uint8_t ret_prdiv; /* PRDIV to return. */
@ -742,7 +876,7 @@ uint32_t CLOCK_CalcPllDiv(uint32_t refFreq, uint32_t desireFreq, uint8_t *prdiv,
uint8_t prdiv_max; /* Max PRDIV value to make reference clock in allowed range. */
uint8_t prdiv_cur; /* PRDIV value for iteration. */
uint8_t vdiv_cur; /* VDIV value for iteration. */
uint32_t ret_freq = 0U; /* PLL output fequency to return. */
uint32_t ret_freq = 0U; /* PLL output frequency to return. */
uint32_t diff = 0xFFFFFFFFU; /* Difference between desireFreq and return frequency. */
uint32_t ref_div; /* Reference frequency after PRDIV. */
@ -831,6 +965,17 @@ uint32_t CLOCK_CalcPllDiv(uint32_t refFreq, uint32_t desireFreq, uint8_t *prdiv,
}
}
/*!
* brief Enables the PLL0 in FLL mode.
*
* This function sets us the PLL0 in FLL mode and reconfigures
* the PLL0. Ensure that the PLL reference
* clock is enabled before calling this function and that the PLL0 is not used as a clock source.
* The function CLOCK_CalcPllDiv gets the correct PLL
* divider values.
*
* param config Pointer to the configuration structure.
*/
void CLOCK_EnablePll0(mcg_pll_config_t const *config)
{
assert(config);
@ -851,6 +996,13 @@ void CLOCK_EnablePll0(mcg_pll_config_t const *config)
}
}
/*!
* brief Sets the OSC0 clock monitor mode.
*
* This function sets the OSC0 clock monitor mode. See ref mcg_monitor_mode_t for details.
*
* param mode Monitor mode to set.
*/
void CLOCK_SetOsc0MonitorMode(mcg_monitor_mode_t mode)
{
/* Clear the previous flag, MCG_SC[LOCS0]. */
@ -874,6 +1026,13 @@ void CLOCK_SetOsc0MonitorMode(mcg_monitor_mode_t mode)
}
}
/*!
* brief Sets the RTC OSC clock monitor mode.
*
* This function sets the RTC OSC clock monitor mode. See ref mcg_monitor_mode_t for details.
*
* param mode Monitor mode to set.
*/
void CLOCK_SetRtcOscMonitorMode(mcg_monitor_mode_t mode)
{
uint8_t mcg_c8 = MCG->C8;
@ -891,6 +1050,13 @@ void CLOCK_SetRtcOscMonitorMode(mcg_monitor_mode_t mode)
MCG->C8 = mcg_c8;
}
/*!
* brief Sets the PLL0 clock monitor mode.
*
* This function sets the PLL0 clock monitor mode. See ref mcg_monitor_mode_t for details.
*
* param mode Monitor mode to set.
*/
void CLOCK_SetPll0MonitorMode(mcg_monitor_mode_t mode)
{
uint8_t mcg_c8;
@ -921,6 +1087,32 @@ void CLOCK_SetPll0MonitorMode(mcg_monitor_mode_t mode)
}
}
/*!
* brief Gets the MCG status flags.
*
* This function gets the MCG clock status flags. All status flags are
* returned as a logical OR of the enumeration ref _mcg_status_flags_t. To
* check a specific flag, compare the return value with the flag.
*
* Example:
* code
// To check the clock lost lock status of OSC0 and PLL0.
uint32_t mcgFlags;
mcgFlags = CLOCK_GetStatusFlags();
if (mcgFlags & kMCG_Osc0LostFlag)
{
// OSC0 clock lock lost. Do something.
}
if (mcgFlags & kMCG_Pll0LostFlag)
{
// PLL0 clock lock lost. Do something.
}
endcode
*
* return Logical OR value of the ref _mcg_status_flags_t.
*/
uint32_t CLOCK_GetStatusFlags(void)
{
uint32_t ret = 0U;
@ -949,6 +1141,22 @@ uint32_t CLOCK_GetStatusFlags(void)
return ret;
}
/*!
* brief Clears the MCG status flags.
*
* This function clears the MCG clock lock lost status. The parameter is a logical
* OR value of the flags to clear. See ref _mcg_status_flags_t.
*
* Example:
* code
// To clear the clock lost lock status flags of OSC0 and PLL0.
CLOCK_ClearStatusFlags(kMCG_Osc0LostFlag | kMCG_Pll0LostFlag);
endcode
*
* param mask The status flags to clear. This is a logical OR of members of the
* enumeration ref _mcg_status_flags_t.
*/
void CLOCK_ClearStatusFlags(uint32_t mask)
{
uint8_t reg;
@ -968,6 +1176,13 @@ void CLOCK_ClearStatusFlags(uint32_t mask)
}
}
/*!
* brief Initializes the OSC0.
*
* This function initializes the OSC0 according to the board configuration.
*
* param config Pointer to the OSC0 configuration structure.
*/
void CLOCK_InitOsc0(osc_config_t const *config)
{
uint8_t range = CLOCK_GetOscRangeFromFreq(config->freq);
@ -986,12 +1201,35 @@ void CLOCK_InitOsc0(osc_config_t const *config)
}
}
/*!
* brief Deinitializes the OSC0.
*
* This function deinitializes the OSC0.
*/
void CLOCK_DeinitOsc0(void)
{
OSC0->CR = 0U;
MCG->C2 &= ~OSC_MODE_MASK;
}
/*!
* brief Auto trims the internal reference clock.
*
* This function trims the internal reference clock by using the external clock. If
* successful, it returns the kStatus_Success and the frequency after
* trimming is received in the parameter p actualFreq. If an error occurs,
* the error code is returned.
*
* param extFreq External clock frequency, which should be a bus clock.
* param desireFreq Frequency to trim to.
* param actualFreq Actual frequency after trimming.
* param atms Trim fast or slow internal reference clock.
* retval kStatus_Success ATM success.
* retval kStatus_MCG_AtmBusClockInvalid The bus clock is not in allowed range for the ATM.
* retval kStatus_MCG_AtmDesiredFreqInvalid MCGIRCLK could not be trimmed to the desired frequency.
* retval kStatus_MCG_AtmIrcUsed Could not trim because MCGIRCLK is used as a bus clock source.
* retval kStatus_MCG_AtmHardwareFail Hardware fails while trimming.
*/
status_t CLOCK_TrimInternalRefClk(uint32_t extFreq, uint32_t desireFreq, uint32_t *actualFreq, mcg_atm_select_t atms)
{
uint32_t multi; /* extFreq / desireFreq */
@ -1068,6 +1306,13 @@ status_t CLOCK_TrimInternalRefClk(uint32_t extFreq, uint32_t desireFreq, uint32_
return kStatus_Success;
}
/*!
* brief Gets the current MCG mode.
*
* This function checks the MCG registers and determines the current MCG mode.
*
* return Current MCG mode or error code; See ref mcg_mode_t.
*/
mcg_mode_t CLOCK_GetMode(void)
{
mcg_mode_t mode = kMCG_ModeError;
@ -1168,6 +1413,21 @@ mcg_mode_t CLOCK_GetMode(void)
return mode;
}
/*!
* brief Sets the MCG to FEI mode.
*
* This function sets the MCG to FEI mode. If setting to FEI mode fails
* from the current mode, this function returns an error.
*
* param dmx32 DMX32 in FEI mode.
* param drs The DCO range selection.
* param fllStableDelay Delay function to ensure that the FLL is stable. Passing
* NULL does not cause a delay.
* retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
* retval kStatus_Success Switched to the target mode successfully.
* note If p dmx32 is set to kMCG_Dmx32Fine, the slow IRC must not be trimmed
* to a frequency above 32768 Hz.
*/
status_t CLOCK_SetFeiMode(mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void))
{
uint8_t mcg_c4;
@ -1228,6 +1488,21 @@ status_t CLOCK_SetFeiMode(mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDela
return kStatus_Success;
}
/*!
* brief Sets the MCG to FEE mode.
*
* This function sets the MCG to FEE mode. If setting to FEE mode fails
* from the current mode, this function returns an error.
*
* param frdiv FLL reference clock divider setting, FRDIV.
* param dmx32 DMX32 in FEE mode.
* param drs The DCO range selection.
* param fllStableDelay Delay function to make sure FLL is stable. Passing
* NULL does not cause a delay.
*
* retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
* retval kStatus_Success Switched to the target mode successfully.
*/
status_t CLOCK_SetFeeMode(uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void))
{
uint8_t mcg_c4;
@ -1306,6 +1581,22 @@ status_t CLOCK_SetFeeMode(uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void
return kStatus_Success;
}
/*!
* brief Sets the MCG to FBI mode.
*
* This function sets the MCG to FBI mode. If setting to FBI mode fails
* from the current mode, this function returns an error.
*
* param dmx32 DMX32 in FBI mode.
* param drs The DCO range selection.
* param fllStableDelay Delay function to make sure FLL is stable. If the FLL
* is not used in FBI mode, this parameter can be NULL. Passing
* NULL does not cause a delay.
* retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
* retval kStatus_Success Switched to the target mode successfully.
* note If p dmx32 is set to kMCG_Dmx32Fine, the slow IRC must not be trimmed
* to frequency above 32768 Hz.
*/
status_t CLOCK_SetFbiMode(mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void))
{
uint8_t mcg_c4;
@ -1370,6 +1661,21 @@ status_t CLOCK_SetFbiMode(mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDela
return kStatus_Success;
}
/*!
* brief Sets the MCG to FBE mode.
*
* This function sets the MCG to FBE mode. If setting to FBE mode fails
* from the current mode, this function returns an error.
*
* param frdiv FLL reference clock divider setting, FRDIV.
* param dmx32 DMX32 in FBE mode.
* param drs The DCO range selection.
* param fllStableDelay Delay function to make sure FLL is stable. If the FLL
* is not used in FBE mode, this parameter can be NULL. Passing NULL
* does not cause a delay.
* retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
* retval kStatus_Success Switched to the target mode successfully.
*/
status_t CLOCK_SetFbeMode(uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void))
{
uint8_t mcg_c4;
@ -1453,6 +1759,15 @@ status_t CLOCK_SetFbeMode(uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void
return kStatus_Success;
}
/*!
* brief Sets the MCG to BLPI mode.
*
* This function sets the MCG to BLPI mode. If setting to BLPI mode fails
* from the current mode, this function returns an error.
*
* retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
* retval kStatus_Success Switched to the target mode successfully.
*/
status_t CLOCK_SetBlpiMode(void)
{
#if (defined(MCG_CONFIG_CHECK_PARAM) && MCG_CONFIG_CHECK_PARAM)
@ -1468,6 +1783,15 @@ status_t CLOCK_SetBlpiMode(void)
return kStatus_Success;
}
/*!
* brief Sets the MCG to BLPE mode.
*
* This function sets the MCG to BLPE mode. If setting to BLPE mode fails
* from the current mode, this function returns an error.
*
* retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
* retval kStatus_Success Switched to the target mode successfully.
*/
status_t CLOCK_SetBlpeMode(void)
{
#if (defined(MCG_CONFIG_CHECK_PARAM) && MCG_CONFIG_CHECK_PARAM)
@ -1483,6 +1807,25 @@ status_t CLOCK_SetBlpeMode(void)
return kStatus_Success;
}
/*!
* brief Sets the MCG to PBE mode.
*
* This function sets the MCG to PBE mode. If setting to PBE mode fails
* from the current mode, this function returns an error.
*
* param pllcs The PLL selection, PLLCS.
* param config Pointer to the PLL configuration.
* retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
* retval kStatus_Success Switched to the target mode successfully.
*
* note
* 1. The parameter \c pllcs selects the PLL. For platforms with
* only one PLL, the parameter pllcs is kept for interface compatibility.
* 2. The parameter \c config is the PLL configuration structure. On some
* platforms, it is possible to choose the external PLL directly, which renders the
* configuration structure not necessary. In this case, pass in NULL.
* For example: CLOCK_SetPbeMode(kMCG_OscselOsc, kMCG_PllClkSelExtPll, NULL);
*/
status_t CLOCK_SetPbeMode(mcg_pll_clk_select_t pllcs, mcg_pll_config_t const *config)
{
assert(config);
@ -1524,6 +1867,18 @@ status_t CLOCK_SetPbeMode(mcg_pll_clk_select_t pllcs, mcg_pll_config_t const *co
return kStatus_Success;
}
/*!
* brief Sets the MCG to PEE mode.
*
* This function sets the MCG to PEE mode.
*
* retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
* retval kStatus_Success Switched to the target mode successfully.
*
* note This function only changes the CLKS to use the PLL/FLL output. If the
* PRDIV/VDIV are different than in the PBE mode, set them up
* in PBE mode and wait. When the clock is stable, switch to PEE mode.
*/
status_t CLOCK_SetPeeMode(void)
{
#if (defined(MCG_CONFIG_CHECK_PARAM) && MCG_CONFIG_CHECK_PARAM)
@ -1545,6 +1900,22 @@ status_t CLOCK_SetPeeMode(void)
return kStatus_Success;
}
/*!
* brief Switches the MCG to FBE mode from the external mode.
*
* This function switches the MCG from external modes (PEE/PBE/BLPE/FEE) to the FBE mode quickly.
* The external clock is used as the system clock source and PLL is disabled. However,
* the FLL settings are not configured. This is a lite function with a small code size, which is useful
* during the mode switch. For example, to switch from PEE mode to FEI mode:
*
* code
* CLOCK_ExternalModeToFbeModeQuick();
* CLOCK_SetFeiMode(...);
* endcode
*
* retval kStatus_Success Switched successfully.
* retval kStatus_MCG_ModeInvalid If the current mode is not an external mode, do not call this function.
*/
status_t CLOCK_ExternalModeToFbeModeQuick(void)
{
#if (defined(MCG_CONFIG_CHECK_PARAM) && MCG_CONFIG_CHECK_PARAM)
@ -1571,6 +1942,22 @@ status_t CLOCK_ExternalModeToFbeModeQuick(void)
return kStatus_Success;
}
/*!
* brief Switches the MCG to FBI mode from internal modes.
*
* This function switches the MCG from internal modes (PEI/PBI/BLPI/FEI) to the FBI mode quickly.
* The MCGIRCLK is used as the system clock source and PLL is disabled. However,
* FLL settings are not configured. This is a lite function with a small code size, which is useful
* during the mode switch. For example, to switch from PEI mode to FEE mode:
*
* code
* CLOCK_InternalModeToFbiModeQuick();
* CLOCK_SetFeeMode(...);
* endcode
*
* retval kStatus_Success Switched successfully.
* retval kStatus_MCG_ModeInvalid If the current mode is not an internal mode, do not call this function.
*/
status_t CLOCK_InternalModeToFbiModeQuick(void)
{
#if (defined(MCG_CONFIG_CHECK_PARAM) && MCG_CONFIG_CHECK_PARAM)
@ -1591,11 +1978,41 @@ status_t CLOCK_InternalModeToFbiModeQuick(void)
return kStatus_Success;
}
/*!
* brief Sets the MCG to FEI mode during system boot up.
*
* This function sets the MCG to FEI mode from the reset mode. It can also be used to
* set up MCG during system boot up.
*
* param dmx32 DMX32 in FEI mode.
* param drs The DCO range selection.
* param fllStableDelay Delay function to ensure that the FLL is stable.
*
* retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
* retval kStatus_Success Switched to the target mode successfully.
* note If p dmx32 is set to kMCG_Dmx32Fine, the slow IRC must not be trimmed
* to frequency above 32768 Hz.
*/
status_t CLOCK_BootToFeiMode(mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void))
{
return CLOCK_SetFeiMode(dmx32, drs, fllStableDelay);
}
/*!
* brief Sets the MCG to FEE mode during system bootup.
*
* This function sets MCG to FEE mode from the reset mode. It can also be used to
* set up the MCG during system boot up.
*
* param oscsel OSC clock select, OSCSEL.
* param frdiv FLL reference clock divider setting, FRDIV.
* param dmx32 DMX32 in FEE mode.
* param drs The DCO range selection.
* param fllStableDelay Delay function to ensure that the FLL is stable.
*
* retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
* retval kStatus_Success Switched to the target mode successfully.
*/
status_t CLOCK_BootToFeeMode(
mcg_oscsel_t oscsel, uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void))
{
@ -1604,6 +2021,19 @@ status_t CLOCK_BootToFeeMode(
return CLOCK_SetFeeMode(frdiv, dmx32, drs, fllStableDelay);
}
/*!
* brief Sets the MCG to BLPI mode during system boot up.
*
* This function sets the MCG to BLPI mode from the reset mode. It can also be used to
* set up the MCG during system boot up.
*
* param fcrdiv Fast IRC divider, FCRDIV.
* param ircs The internal reference clock to select, IRCS.
* param ircEnableMode The MCGIRCLK enable mode, OR'ed value of ref _mcg_irclk_enable_mode.
*
* retval kStatus_MCG_SourceUsed Could not change MCGIRCLK setting.
* retval kStatus_Success Switched to the target mode successfully.
*/
status_t CLOCK_BootToBlpiMode(uint8_t fcrdiv, mcg_irc_mode_t ircs, uint8_t ircEnableMode)
{
/* If reset mode is FEI mode, set MCGIRCLK and always success. */
@ -1621,6 +2051,17 @@ status_t CLOCK_BootToBlpiMode(uint8_t fcrdiv, mcg_irc_mode_t ircs, uint8_t ircEn
return kStatus_Success;
}
/*!
* brief Sets the MCG to BLPE mode during system boot up.
*
* This function sets the MCG to BLPE mode from the reset mode. It can also be used to
* set up the MCG during system boot up.
*
* param oscsel OSC clock select, MCG_C7[OSCSEL].
*
* retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
* retval kStatus_Success Switched to the target mode successfully.
*/
status_t CLOCK_BootToBlpeMode(mcg_oscsel_t oscsel)
{
CLOCK_SetExternalRefClkConfig(oscsel);
@ -1653,6 +2094,19 @@ status_t CLOCK_BootToBlpeMode(mcg_oscsel_t oscsel)
return kStatus_Success;
}
/*!
* brief Sets the MCG to PEE mode during system boot up.
*
* This function sets the MCG to PEE mode from reset mode. It can also be used to
* set up the MCG during system boot up.
*
* param oscsel OSC clock select, MCG_C7[OSCSEL].
* param pllcs The PLL selection, PLLCS.
* param config Pointer to the PLL configuration.
*
* retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
* retval kStatus_Success Switched to the target mode successfully.
*/
status_t CLOCK_BootToPeeMode(mcg_oscsel_t oscsel, mcg_pll_clk_select_t pllcs, mcg_pll_config_t const *config)
{
assert(config);
@ -1699,6 +2153,20 @@ static const mcg_mode_t mcgModeMatrix[8][8] = {
/* FEI FBI BLPI FEE FBE BLPE PBE PEE */
};
/*!
* brief Sets the MCG to a target mode.
*
* This function sets MCG to a target mode defined by the configuration
* structure. If switching to the target mode fails, this function
* chooses the correct path.
*
* param config Pointer to the target MCG mode configuration structure.
* return Return kStatus_Success if switched successfully; Otherwise, it returns an error code #_mcg_status.
*
* note If the external clock is used in the target mode, ensure that it is
* enabled. For example, if the OSC0 is used, set up OSC0 correctly before calling this
* function.
*/
status_t CLOCK_SetMcgConfig(const mcg_config_t *config)
{
mcg_mode_t next_mode;
@ -1710,10 +2178,10 @@ status_t CLOCK_SetMcgConfig(const mcg_config_t *config)
if (MCG_C7_OSCSEL_VAL != config->oscsel)
{
/* If external clock is in use, change to FEI first. */
if (!(MCG->S & MCG_S_IRCST_MASK))
if (kMCG_FllSrcExternal == MCG_S_IREFST_VAL)
{
CLOCK_ExternalModeToFbeModeQuick();
CLOCK_SetFeiMode(config->dmx32, config->drs, (void (*)(void))0);
CLOCK_SetFeiMode(config->dmx32, config->drs, NULL);
}
CLOCK_SetExternalRefClkConfig(config->oscsel);
@ -1747,10 +2215,10 @@ status_t CLOCK_SetMcgConfig(const mcg_config_t *config)
status = CLOCK_SetFeeMode(config->frdiv, config->dmx32, config->drs, CLOCK_FllStableDelay);
break;
case kMCG_ModeFBI:
status = CLOCK_SetFbiMode(config->dmx32, config->drs, (void (*)(void))0);
status = CLOCK_SetFbiMode(config->dmx32, config->drs, NULL);
break;
case kMCG_ModeFBE:
status = CLOCK_SetFbeMode(config->frdiv, config->dmx32, config->drs, (void (*)(void))0);
status = CLOCK_SetFbeMode(config->frdiv, config->dmx32, config->drs, NULL);
break;
case kMCG_ModeBLPI:
status = CLOCK_SetBlpiMode();

46
ext/hal/nxp/mcux/devices/MK64F12/fsl_clock.h
View file

@ -3,30 +3,8 @@
* Copyright (c) 2016 - 2017 , NXP
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _FSL_CLOCK_H_
@ -65,7 +43,7 @@
*
* When set to 0, peripheral drivers will enable clock in initialize function
* and disable clock in de-initialize function. When set to 1, peripheral
* driver will not control the clock, application could contol the clock out of
* driver will not control the clock, application could control the clock out of
* the driver.
*
* @note All drivers share this feature switcher. If it is set to 1, application
@ -99,7 +77,7 @@
* OSC0 using the CLOCK_InitOsc0. All other cores need to call the CLOCK_SetXtal0Freq
* to get a valid clock frequency.
*/
extern uint32_t g_xtal0Freq;
extern volatile uint32_t g_xtal0Freq;
/*! @brief External XTAL32/EXTAL32/RTC_CLKIN clock frequency.
*
@ -110,7 +88,7 @@ extern uint32_t g_xtal0Freq;
* the clock. All other cores need to call the CLOCK_SetXtal32Freq
* to get a valid clock frequency.
*/
extern uint32_t g_xtal32Freq;
extern volatile uint32_t g_xtal32Freq;
/*! @brief IRC48M clock frequency in Hz. */
#define MCG_INTERNAL_IRC_48M 48000000U
@ -1005,8 +983,8 @@ static inline void CLOCK_SetLowPowerEnable(bool enable)
* @param enableMode MCGIRCLK enable mode, OR'ed value of @ref _mcg_irclk_enable_mode.
* @param ircs MCGIRCLK clock source, choose fast or slow.
* @param fcrdiv Fast IRC divider setting (\c FCRDIV).
* @retval kStatus_MCG_SourceUsed Because the internall reference clock is used as a clock source,
* the confuration should not be changed. Otherwise, a glitch occurs.
* @retval kStatus_MCG_SourceUsed Because the internal reference clock is used as a clock source,
* the configuration should not be changed. Otherwise, a glitch occurs.
* @retval kStatus_Success MCGIRCLK configuration finished successfully.
*/
status_t CLOCK_SetInternalRefClkConfig(uint8_t enableMode, mcg_irc_mode_t ircs, uint8_t fcrdiv);
@ -1020,7 +998,7 @@ status_t CLOCK_SetInternalRefClkConfig(uint8_t enableMode, mcg_irc_mode_t ircs,
*
* @param oscsel MCG external reference clock source, MCG_C7[OSCSEL].
* @retval kStatus_MCG_SourceUsed Because the external reference clock is used as a clock source,
* the confuration should not be changed. Otherwise, a glitch occurs.
* the configuration should not be changed. Otherwise, a glitch occurs.
* @retval kStatus_Success External reference clock set successfully.
*/
status_t CLOCK_SetExternalRefClkConfig(mcg_oscsel_t oscsel);
@ -1431,7 +1409,7 @@ status_t CLOCK_SetPeeMode(void);
* @brief Switches the MCG to FBE mode from the external mode.
*
* This function switches the MCG from external modes (PEE/PBE/BLPE/FEE) to the FBE mode quickly.
* The external clock is used as the system clock souce and PLL is disabled. However,
* The external clock is used as the system clock source and PLL is disabled. However,
* the FLL settings are not configured. This is a lite function with a small code size, which is useful
* during the mode switch. For example, to switch from PEE mode to FEI mode:
*
@ -1449,7 +1427,7 @@ status_t CLOCK_ExternalModeToFbeModeQuick(void);
* @brief Switches the MCG to FBI mode from internal modes.
*
* This function switches the MCG from internal modes (PEI/PBI/BLPI/FEI) to the FBI mode quickly.
* The MCGIRCLK is used as the system clock souce and PLL is disabled. However,
* The MCGIRCLK is used as the system clock source and PLL is disabled. However,
* FLL settings are not configured. This is a lite function with a small code size, which is useful
* during the mode switch. For example, to switch from PEI mode to FEE mode:
*
@ -1502,7 +1480,7 @@ status_t CLOCK_BootToFeeMode(
* @brief Sets the MCG to BLPI mode during system boot up.
*
* This function sets the MCG to BLPI mode from the reset mode. It can also be used to
* set up the MCG during sytem boot up.
* set up the MCG during system boot up.
*
* @param fcrdiv Fast IRC divider, FCRDIV.
* @param ircs The internal reference clock to select, IRCS.
@ -1514,10 +1492,10 @@ status_t CLOCK_BootToFeeMode(
status_t CLOCK_BootToBlpiMode(uint8_t fcrdiv, mcg_irc_mode_t ircs, uint8_t ircEnableMode);
/*!
* @brief Sets the MCG to BLPE mode during sytem boot up.
* @brief Sets the MCG to BLPE mode during system boot up.
*
* This function sets the MCG to BLPE mode from the reset mode. It can also be used to
* set up the MCG during sytem boot up.
* set up the MCG during system boot up.
*
* @param oscsel OSC clock select, MCG_C7[OSCSEL].
*

28
ext/hal/nxp/mcux/devices/MK64F12/fsl_device_registers.h
View file

@ -1,31 +1,9 @@
/*
* Copyright (c) 2014 - 2016, Freescale Semiconductor, Inc.
* All rights reserved.
* Copyright 2014-2016 Freescale Semiconductor, Inc.
* Copyright 2016-2018 NXP
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* SPDX-License-Identifier: BSD-3-Clause
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __FSL_DEVICE_REGISTERS_H__

39
ext/hal/nxp/mcux/devices/MK64F12/system_MK64F12.c
View file

@ -18,39 +18,17 @@
**
** Reference manual: K64P144M120SF5RM, Rev.2, January 2014
** Version: rev. 2.9, 2016-03-21
** Build: b170112
** Build: b180801
**
** Abstract:
** Provides a system configuration function and a global variable that
** contains the system frequency. It configures the device and initializes
** the oscillator (PLL) that is part of the microcontroller device.
**
** Copyright (c) 2016 Freescale Semiconductor, Inc.
** Copyright 2016 - 2017 NXP
** Redistribution and use in source and binary forms, with or without modification,
** are permitted provided that the following conditions are met:
** Copyright 2016 Freescale Semiconductor, Inc.
** Copyright 2016-2018 NXP
**
** o Redistributions of source code must retain the above copyright notice, this list
** of conditions and the following disclaimer.
**
** o Redistributions in binary form must reproduce the above copyright notice, this
** list of conditions and the following disclaimer in the documentation and/or
** other materials provided with the distribution.
**
** o Neither the name of the copyright holder nor the names of its
** contributors may be used to endorse or promote products derived from this
** software without specific prior written permission.
**
** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
** SPDX-License-Identifier: BSD-3-Clause
**
** http: www.nxp.com
** mail: support@nxp.com
@ -138,6 +116,7 @@ void SystemInit (void) {
0x0100U;
#endif /* (DISABLE_WDOG) */
SystemInitHook();
}
/* ----------------------------------------------------------------------------
@ -249,3 +228,11 @@ void SystemCoreClockUpdate (void) {
} /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U)) */
SystemCoreClock = (MCGOUTClock / (0x01U + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT)));
}
/* ----------------------------------------------------------------------------
-- SystemInitHook()
---------------------------------------------------------------------------- */
__attribute__ ((weak)) void SystemInitHook (void) {
/* Void implementation of the weak function. */
}

42
ext/hal/nxp/mcux/devices/MK64F12/system_MK64F12.h
View file

@ -18,39 +18,17 @@
**
** Reference manual: K64P144M120SF5RM, Rev.2, January 2014
** Version: rev. 2.9, 2016-03-21
** Build: b170112
** Build: b180801
**
** Abstract:
** Provides a system configuration function and a global variable that
** contains the system frequency. It configures the device and initializes
** the oscillator (PLL) that is part of the microcontroller device.
**
** Copyright (c) 2016 Freescale Semiconductor, Inc.
** Copyright 2016 - 2017 NXP
** Redistribution and use in source and binary forms, with or without modification,
** are permitted provided that the following conditions are met:
** Copyright 2016 Freescale Semiconductor, Inc.
** Copyright 2016-2018 NXP
**
** o Redistributions of source code must retain the above copyright notice, this list
** of conditions and the following disclaimer.
**
** o Redistributions in binary form must reproduce the above copyright notice, this
** list of conditions and the following disclaimer in the documentation and/or
** other materials provided with the distribution.
**
** o Neither the name of the copyright holder nor the names of its
** contributors may be used to endorse or promote products derived from this
** software without specific prior written permission.
**
** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
** SPDX-License-Identifier: BSD-3-Clause
**
** http: www.nxp.com
** mail: support@nxp.com
@ -167,6 +145,18 @@ void SystemInit (void);
*/
void SystemCoreClockUpdate (void);
/**
* @brief SystemInit function hook.
*
* This weak function allows to call specific initialization code during the
* SystemInit() execution.This can be used when an application specific code needs
* to be called as close to the reset entry as possible (for example the Multicore
* Manager MCMGR_EarlyInit() function call).
* NOTE: No global r/w variables can be used in this hook function because the
* initialization of these variables happens after this function.
*/
void SystemInitHook (void);
#ifdef __cplusplus
}
#endif

109
ext/hal/nxp/mcux/drivers/imx/fsl_adc.c
View file

@ -55,6 +55,12 @@ static uint32_t ADC_GetInstance(ADC_Type *base)
return instance;
}
/*!
* brief Initialize the ADC module.
*
* param base ADC peripheral base address.
* param config Pointer to "adc_config_t" structure.
*/
void ADC_Init(ADC_Type *base, const adc_config_t *config)
{
assert(NULL != config);
@ -100,6 +106,11 @@ void ADC_Init(ADC_Type *base, const adc_config_t *config)
base->GC = tmp32;
}
/*!
* brief De-initializes the ADC module.
*
* param base ADC peripheral base address.
*/
void ADC_Deinit(ADC_Type *base)
{
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
@ -108,10 +119,33 @@ void ADC_Deinit(ADC_Type *base)
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
}
/*!
* brief Gets an available pre-defined settings for the converter's configuration.
*
* This function initializes the converter configuration structure with available settings. The default values are:
* code
* config->enableAsynchronousClockOutput = true;
* config->enableOverWrite = false;
* config->enableContinuousConversion = false;
* config->enableHighSpeed = false;
* config->enableLowPower = false;
* config->enableLongSample = false;
* config->referenceVoltageSource = kADC_ReferenceVoltageSourceAlt0;
* config->samplePeriodMode = kADC_SamplePeriod2or12Clocks;
* config->clockSource = kADC_ClockSourceAD;
* config->clockDriver = kADC_ClockDriver1;
* config->resolution = kADC_Resolution12Bit;
* endcode
* param base ADC peripheral base address.
* param config Pointer to the configuration structure.
*/
void ADC_GetDefaultConfig(adc_config_t *config)
{
assert(NULL != config);
/* Initializes the configure structure to zero. */
memset(config, 0, sizeof(*config));
config->enableAsynchronousClockOutput = true;
config->enableOverWrite = false;
config->enableContinuousConversion = false;
@ -125,6 +159,33 @@ void ADC_GetDefaultConfig(adc_config_t *config)
config->resolution = kADC_Resolution12Bit;
}
/*!
* brief Configures the conversion channel.
*
* This operation triggers the conversion when in software trigger mode. When in hardware trigger mode, this API
* configures the channel while the external trigger source helps to trigger the conversion.
*
* Note that the "Channel Group" has a detailed description.
* To allow sequential conversions of the ADC to be triggered by internal peripherals, the ADC has more than one
* group of status and control registers, one for each conversion. The channel group parameter indicates which group of
* registers are used, for example channel group 0 is for Group A registers and channel group 1 is for Group B
* registers. The
* channel groups are used in a "ping-pong" approach to control the ADC operation. At any point, only one of
* the channel groups is actively controlling ADC conversions. The channel group 0 is used for both software and
* hardware
* trigger modes. Channel groups 1 and greater indicate potentially multiple channel group registers for
* use only in hardware trigger mode. See the chip configuration information in the appropriate MCU reference manual
* about the
* number of SC1n registers (channel groups) specific to this device. None of the channel groups 1 or greater are used
* for software trigger operation. Therefore, writing to these channel groups does not initiate a new conversion.
* Updating the channel group 0 while a different channel group is actively controlling a conversion is allowed and
* vice versa. Writing any of the channel group registers while that specific channel group is actively controlling a
* conversion aborts the current conversion.
*
* param base ADC peripheral base address.
* param channelGroup Channel group index.
* param config Pointer to the "adc_channel_config_t" structure for the conversion channel.
*/
void ADC_SetChannelConfig(ADC_Type *base, uint32_t channelGroup, const adc_channel_config_t *config)
{
assert(NULL != config);
@ -147,6 +208,19 @@ void ADC_SetChannelConfig(ADC_Type *base, uint32_t channelGroup, const adc_chann
* 3. Check the status of CALF bit in ADC_GS and the CAL bit in ADC_GC.
* 4. When CAL bit becomes '0' then check the CALF status and COCO[0] bit status.
*/
/*!
* brief Automates the hardware calibration.
*
* This auto calibration helps to adjust the plus/minus side gain automatically.
* Execute the calibration before using the converter. Note that the software trigger should be used
* during calibration.
*
* param base ADC peripheral base address.
*
* return Execution status.
* retval kStatus_Success Calibration is done successfully.
* retval kStatus_Fail Calibration has failed.
*/
status_t ADC_DoAutoCalibration(ADC_Type *base)
{
status_t status = kStatus_Success;
@ -201,6 +275,12 @@ status_t ADC_DoAutoCalibration(ADC_Type *base)
return status;
}
/*!
* brief Set user defined offset.
*
* param base ADC peripheral base address.
* param config Pointer to "adc_offest_config_t" structure.
*/
void ADC_SetOffsetConfig(ADC_Type *base, const adc_offest_config_t *config)
{
assert(NULL != config);
@ -215,6 +295,19 @@ void ADC_SetOffsetConfig(ADC_Type *base, const adc_offest_config_t *config)
base->OFS = tmp32;
}
/*!
* brief Configures the hardware compare mode.
*
* The hardware compare mode provides a way to process the conversion result automatically by using hardware. Only the
* result
* in the compare range is available. To compare the range, see "adc_hardware_compare_mode_t" or the appopriate
* reference
* manual for more information.
*
* param base ADC peripheral base address.
* param Pointer to "adc_hardware_compare_config_t" structure.
*
*/
void ADC_SetHardwareCompareConfig(ADC_Type *base, const adc_hardware_compare_config_t *config)
{
uint32_t tmp32;
@ -252,6 +345,16 @@ void ADC_SetHardwareCompareConfig(ADC_Type *base, const adc_hardware_compare_con
base->CV = tmp32;
}
/*!
* brief Configures the hardware average mode.
*
* The hardware average mode provides a way to process the conversion result automatically by using hardware. The
* multiple
* conversion results are accumulated and averaged internally making them easier to read.
*
* param base ADC peripheral base address.
* param mode Setting the hardware average mode. See "adc_hardware_average_mode_t".
*/
void ADC_SetHardwareAverageConfig(ADC_Type *base, adc_hardware_average_mode_t mode)
{
uint32_t tmp32;
@ -269,6 +372,12 @@ void ADC_SetHardwareAverageConfig(ADC_Type *base, adc_hardware_average_mode_t mo
}
}
/*!
* brief Clears the converter's status falgs.
*
* param base ADC peripheral base address.
* param mask Mask value for the cleared flags. See "adc_status_flags_t".
*/
void ADC_ClearStatusFlags(ADC_Type *base, uint32_t mask)
{
uint32_t tmp32 = 0;

71
ext/hal/nxp/mcux/drivers/imx/fsl_adc_etc.c
View file

@ -55,6 +55,12 @@ static uint32_t ADC_ETC_GetInstance(ADC_ETC_Type *base)
}
#endif /* ADC_ETC_CLOCKS */
/*!
* brief Initialize the ADC_ETC module.
*
* param base ADC_ETC peripheral base address.
* param config Pointer to "adc_etc_config_t" structure.
*/
void ADC_ETC_Init(ADC_ETC_Type *base, const adc_etc_config_t *config)
{
assert(NULL != config);
@ -94,6 +100,11 @@ void ADC_ETC_Init(ADC_ETC_Type *base, const adc_etc_config_t *config)
base->CTRL = tmp32;
}
/*!
* brief De-Initialize the ADC_ETC module.
*
* param base ADC_ETC peripheral base address.
*/
void ADC_ETC_Deinit(ADC_ETC_Type *base)
{
/* Do software reset to clear all logical. */
@ -107,8 +118,26 @@ void ADC_ETC_Deinit(ADC_ETC_Type *base)
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
}
/*!
* brief Gets an available pre-defined settings for the ADC_ETC's configuration.
* This function initializes the ADC_ETC's configuration structure with available settings. The default values are:
* code
* config->enableTSCBypass = true;
* config->enableTSC0Trigger = false;
* config->enableTSC1Trigger = false;
* config->TSC0triggerPriority = 0U;
* config->TSC1triggerPriority = 0U;
* config->clockPreDivider = 0U;
* config->XBARtriggerMask = 0U;
* endCode
*
* param config Pointer to "adc_etc_config_t" structure.
*/
void ADC_ETC_GetDefaultConfig(adc_etc_config_t *config)
{
/* Initializes the configure structure to zero. */
memset(config, 0, sizeof(*config));
config->enableTSCBypass = true;
config->enableTSC0Trigger = false;
config->enableTSC1Trigger = false;
@ -121,6 +150,13 @@ void ADC_ETC_GetDefaultConfig(adc_etc_config_t *config)
config->XBARtriggerMask = 0U;
}
/*!
* brief Set the external XBAR trigger configuration.
*
* param base ADC_ETC peripheral base address.
* param triggerGroup Trigger group index.
* param config Pointer to "adc_etc_trigger_config_t" structure.
*/
void ADC_ETC_SetTriggerConfig(ADC_ETC_Type *base, uint32_t triggerGroup, const adc_etc_trigger_config_t *config)
{
assert(triggerGroup < ADC_ETC_TRIGn_CTRL_COUNT);
@ -147,6 +183,16 @@ void ADC_ETC_SetTriggerConfig(ADC_ETC_Type *base, uint32_t triggerGroup, const a
base->TRIG[triggerGroup].TRIGn_COUNTER = tmp32;
}
/*!
* brief Set the external XBAR trigger chain configuration.
* For example, if triggerGroup is set to 0U and chainGroup is set to 1U, which means Trigger0 source's chain1 would be
* configurated.
*
* param base ADC_ETC peripheral base address.
* param triggerGroup Trigger group index. Available number is 0~7.
* param chainGroup Trigger chain group index. Available number is 0~7.
* param config Pointer to "adc_etc_trigger_chain_config_t" structure.
*/
void ADC_ETC_SetTriggerChainConfig(ADC_ETC_Type *base,
uint32_t triggerGroup,
uint32_t chainGroup,
@ -237,6 +283,14 @@ void ADC_ETC_SetTriggerChainConfig(ADC_ETC_Type *base,
}
}
/*!
* brief Gets the interrupt status flags of external XBAR and TSC triggers.
*
* param base ADC_ETC peripheral base address.
* param sourceIndex trigger source index.
*
* return Status flags mask of trigger. Refer to "_adc_etc_status_flag_mask".
*/
uint32_t ADC_ETC_GetInterruptStatusFlags(ADC_ETC_Type *base, adc_etc_external_trigger_source_t sourceIndex)
{
uint32_t tmp32 = 0U;
@ -264,6 +318,13 @@ uint32_t ADC_ETC_GetInterruptStatusFlags(ADC_ETC_Type *base, adc_etc_external_tr
return tmp32;
}
/*!
* brief Clears the ADC_ETC's interrupt status falgs.
*
* param base ADC_ETC peripheral base address.
* param sourceIndex trigger source index.
* param mask Status flags mask of trigger. Refer to "_adc_etc_status_flag_mask".
*/
void ADC_ETC_ClearInterruptStatusFlags(ADC_ETC_Type *base, adc_etc_external_trigger_source_t sourceIndex, uint32_t mask)
{
if (0U != (mask & kADC_ETC_Done0StatusFlagMask)) /* Write 1 to clear DONE0 status flags. */
@ -284,6 +345,16 @@ void ADC_ETC_ClearInterruptStatusFlags(ADC_ETC_Type *base, adc_etc_external_trig
}
}
/*!
* brief Get ADC conversion result from external XBAR sources.
* For example, if triggerGroup is set to 0U and chainGroup is set to 1U, which means the API would
* return Trigger0 source's chain1 conversion result.
*
* param base ADC_ETC peripheral base address.
* param triggerGroup Trigger group index. Available number is 0~7.
* param chainGroup Trigger chain group index. Available number is 0~7.
* return ADC conversion result value.
*/
uint32_t ADC_ETC_GetADCConversionValue(ADC_ETC_Type *base, uint32_t triggerGroup, uint32_t chainGroup)
{
assert(triggerGroup < ADC_ETC_TRIGn_RESULT_1_0_COUNT);

19
ext/hal/nxp/mcux/drivers/imx/fsl_aipstz.c
View file

@ -2,7 +2,7 @@
* Copyright (c) 2015, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
* All rights reserved.
*
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -17,10 +17,16 @@
#define FSL_COMPONENT_ID "platform.drivers.aipstz"
#endif
/*******************************************************************************
* Prototypes
******************************************************************************/
/*!
* brief Configure the privilege level for master.
*
* param base AIPSTZ peripheral base pointer
* param master Masters for AIPSTZ.
* param privilegeConfig Configuration is ORed from aipstz_master_privilege_level_t.
*/
void AIPSTZ_SetMasterPriviledgeLevel(AIPSTZ_Type *base, aipstz_master_t master, uint32_t privilegeConfig)
{
uint32_t mask = ((uint32_t)master >> 8) - 1;
@ -28,6 +34,13 @@ void AIPSTZ_SetMasterPriviledgeLevel(AIPSTZ_Type *base, aipstz_master_t master,
base->MPR = (base->MPR & (~(mask << shift))) | (privilegeConfig << shift);
}
/*!
* brief Configure the access for peripheral.
*
* param base AIPSTZ peripheral base pointer
* param master Peripheral for AIPSTZ.
* param accessControl Configuration is ORed from aipstz_peripheral_access_control_t.
*/
void AIPSTZ_SetPeripheralAccessControl(AIPSTZ_Type *base, aipstz_peripheral_t peripheral, uint32_t accessControl)
{
volatile uint32_t *reg = (uint32_t *)((uint32_t)base + ((uint32_t)peripheral >> 16));
@ -36,5 +49,3 @@ void AIPSTZ_SetPeripheralAccessControl(AIPSTZ_Type *base, aipstz_peripheral_t pe
*reg = (*reg & (~(mask << shift))) | ((accessControl & mask) << shift);
}

78
ext/hal/nxp/mcux/drivers/imx/fsl_aoi.c
View file

@ -2,7 +2,7 @@
* Copyright (c) 2015, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
* All rights reserved.
*
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include "fsl_aoi.h"
@ -12,7 +12,6 @@
#define FSL_COMPONENT_ID "platform.drivers.aoi"
#endif
/*******************************************************************************
* Variables
******************************************************************************/
@ -23,9 +22,9 @@ static AOI_Type *const s_aoiBases[] = AOI_BASE_PTRS;
/*! @brief Pointers to aoi clocks for each instance. */
static const clock_ip_name_t s_aoiClocks[] = AOI_CLOCKS;
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
/*******************************************************************************
* Prototypes
******************************************************************************/
/*******************************************************************************
* Prototypes
******************************************************************************/
/*!
* @brief Get instance number for AOI module.
*
@ -56,6 +55,13 @@ static uint32_t AOI_GetInstance(AOI_Type *base)
return instance;
}
/*!
* brief Initializes an AOI instance for operation.
*
* This function un-gates the AOI clock.
*
* param base AOI peripheral address.
*/
void AOI_Init(AOI_Type *base)
{
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
@ -64,6 +70,13 @@ void AOI_Init(AOI_Type *base)
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
}
/*!
* brief Deinitializes an AOI instance for operation.
*
* This function shutdowns AOI module.
*
* param base AOI peripheral address.
*/
void AOI_Deinit(AOI_Type *base)
{
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
@ -72,6 +85,22 @@ void AOI_Deinit(AOI_Type *base)
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
}
/*!
* brief Gets the Boolean evaluation associated.
*
* This function returns the Boolean evaluation associated.
*
* Example:
code
aoi_event_config_t demoEventLogicStruct;
AOI_GetEventLogicConfig(AOI, kAOI_Event0, &demoEventLogicStruct);
endcode
*
* param base AOI peripheral address.
* param event Index of the event which will be set of type aoi_event_t.
* param config Selected input configuration .
*/
void AOI_GetEventLogicConfig(AOI_Type *base, aoi_event_t event, aoi_event_config_t *config)
{
assert(event < FSL_FEATURE_AOI_EVENT_COUNT);
@ -106,6 +135,45 @@ void AOI_GetEventLogicConfig(AOI_Type *base, aoi_event_t event, aoi_event_config
config->PT3DC = (aoi_input_config_t)((value & AOI_BFCRT23_PT3_DC_MASK) >> AOI_BFCRT23_PT3_DC_SHIFT);
}
/*!
* brief Configures an AOI event.
*
* This function configures an AOI event according
* to the aoiEventConfig structure. This function configures all inputs (A, B, C, and D)
* of all product terms (0, 1, 2, and 3) of a desired event.
*
* Example:
code
aoi_event_config_t demoEventLogicStruct;
demoEventLogicStruct.PT0AC = kAOI_InvInputSignal;
demoEventLogicStruct.PT0BC = kAOI_InputSignal;
demoEventLogicStruct.PT0CC = kAOI_LogicOne;
demoEventLogicStruct.PT0DC = kAOI_LogicOne;
demoEventLogicStruct.PT1AC = kAOI_LogicZero;
demoEventLogicStruct.PT1BC = kAOI_LogicOne;
demoEventLogicStruct.PT1CC = kAOI_LogicOne;
demoEventLogicStruct.PT1DC = kAOI_LogicOne;
demoEventLogicStruct.PT2AC = kAOI_LogicZero;
demoEventLogicStruct.PT2BC = kAOI_LogicOne;
demoEventLogicStruct.PT2CC = kAOI_LogicOne;
demoEventLogicStruct.PT2DC = kAOI_LogicOne;
demoEventLogicStruct.PT3AC = kAOI_LogicZero;
demoEventLogicStruct.PT3BC = kAOI_LogicOne;
demoEventLogicStruct.PT3CC = kAOI_LogicOne;
demoEventLogicStruct.PT3DC = kAOI_LogicOne;
AOI_SetEventLogicConfig(AOI, kAOI_Event0, demoEventLogicStruct);
endcode
*
* param base AOI peripheral address.
* param event Event which will be configured of type aoi_event_t.
* param eventConfig Pointer to type aoi_event_config_t structure. The user is responsible for
* filling out the members of this structure and passing the pointer to this function.
*/
void AOI_SetEventLogicConfig(AOI_Type *base, aoi_event_t event, const aoi_event_config_t *eventConfig)
{
assert(eventConfig != NULL);

100
ext/hal/nxp/mcux/drivers/imx/fsl_bee.c
View file

@ -2,7 +2,7 @@
* Copyright 2017 NXP
* All rights reserved.
*
*
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -17,7 +17,6 @@
#define FSL_COMPONENT_ID "platform.drivers.bee"
#endif
/*******************************************************************************
* Variables
******************************************************************************/
@ -40,6 +39,13 @@ static void aligned_memcpy(void *dst, const void *src, size_t size)
}
}
/*!
* brief Resets BEE module to factory default values.
*
* This function performs hardware reset of BEE module. Attributes and keys from software for both regions are cleared.
*
* param base BEE peripheral address.
*/
void BEE_Init(BEE_Type *base)
{
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
@ -49,6 +55,14 @@ void BEE_Init(BEE_Type *base)
base->CTRL = BEE_CTRL_CTRL_SFTRST_N_MASK | BEE_CTRL_CTRL_CLK_EN_MASK;
}
/*!
* brief Resets BEE module, clears keys for both regions and disables clock to the BEE.
*
* This function performs hardware reset of BEE module and disables clocks. Attributes and keys from software for both
* regions are cleared.
*
* param base BEE peripheral address.
*/
void BEE_Deinit(BEE_Type *base)
{
base->CTRL &=
@ -59,10 +73,32 @@ void BEE_Deinit(BEE_Type *base)
#endif
}
/*!
* brief Loads default values to the BEE region configuration structure.
*
* Loads default values to the BEE region configuration structure. The default values are as follows:
* code
* config->region0Mode = kBEE_AesCtrMode;
* config->region1Mode = kBEE_AesCtrMode;
* config->region0AddrOffset = 0U;
* config->region1AddrOffset = 0U;
* config->region0SecLevel = kBEE_SecurityLevel3;
* config->region1SecLevel = kBEE_SecurityLevel3;
* config->region1Bot = 0U;
* config->region1Top = 0U;
* config->accessPermission = kBEE_AccessProtDisabled;
* config->endianSwapEn = kBEE_EndianSwapEnabled;
* endcode
*
* param config Configuration structure for BEE peripheral.
*/
void BEE_GetDefaultConfig(bee_region_config_t *config)
{
assert(config);
/* Initializes the configure structure to zero. */
memset(config, 0, sizeof(*config));
config->region0Mode = kBEE_AesCtrMode;
config->region1Mode = kBEE_AesCtrMode;
config->region0AddrOffset = 0U;
@ -75,6 +111,14 @@ void BEE_GetDefaultConfig(bee_region_config_t *config)
config->endianSwapEn = kBEE_EndianSwapEnabled;
}
/*!
* brief Sets BEE configuration.
*
* This function sets BEE peripheral and BEE region settings accorging to given configuration structure.
*
* param base BEE peripheral address.
* param config Configuration structure for BEE.
*/
void BEE_SetConfig(BEE_Type *base, const bee_region_config_t *config)
{
uint32_t beeCtrlVal;
@ -96,8 +140,8 @@ void BEE_SetConfig(BEE_Type *base, const bee_region_config_t *config)
beeCtrlVal = base->CTRL & 0xFFFF0037;
/* Set variable according to configuration */
beeCtrlVal |= BEE_CTRL_AC_PROT_EN(config->accessPermission) | BEE_CTRL_LITTLE_ENDIAN(config->endianSwapEn) |\
BEE_CTRL_SECURITY_LEVEL_R0(config->region0SecLevel) | BEE_CTRL_CTRL_AES_MODE_R0(config->region0Mode) |\
beeCtrlVal |= BEE_CTRL_AC_PROT_EN(config->accessPermission) | BEE_CTRL_LITTLE_ENDIAN(config->endianSwapEn) |
BEE_CTRL_SECURITY_LEVEL_R0(config->region0SecLevel) | BEE_CTRL_CTRL_AES_MODE_R0(config->region0Mode) |
BEE_CTRL_SECURITY_LEVEL_R1(config->region1SecLevel) | BEE_CTRL_CTRL_AES_MODE_R1(config->region1Mode);
/* Load values to registers */
@ -114,8 +158,21 @@ void BEE_SetConfig(BEE_Type *base, const bee_region_config_t *config)
}
}
status_t BEE_SetRegionKey(
BEE_Type *base, bee_region_t region, const uint8_t *key, size_t keySize)
/*!
* brief Loads the AES key for selected region into BEE key registers.
*
* This function loads given AES key to BEE register for the given region.
* The key must be 32-bit aligned and stored in little-endian format.
*
* Please note, that eFuse BEE_KEYx_SEL must be set accordingly to be able to load and use key loaded in BEE registers.
* Otherwise, key cannot loaded and BEE will use key from OTPMK or SW_GP2.
*
* param base BEE peripheral address.
* param region Selection of the BEE region to be configured.
* param key AES key (in little-endian format).
* param keySize Size of AES key.
*/
status_t BEE_SetRegionKey(BEE_Type *base, bee_region_t region, const uint8_t *key, size_t keySize)
{
bool redisable = false;
@ -174,8 +231,18 @@ status_t BEE_SetRegionKey(
return kStatus_Success;
}
status_t BEE_SetRegionNonce(
BEE_Type *base, bee_region_t region, const uint8_t *nonce, size_t nonceSize)
/*!
* brief Loads the nonce for selected region into BEE nonce registers.
*
* This function loads given nonce(only AES CTR mode) to BEE register for the given region.
* The nonce must be 32-bit aligned and stored in little-endian format.
*
* param base BEE peripheral address.
* param region Selection of the BEE region to be configured.
* param nonce AES nonce (in little-endian format).
* param nonceSize Size of AES nonce.
*/
status_t BEE_SetRegionNonce(BEE_Type *base, bee_region_t region, const uint8_t *nonce, size_t nonceSize)
{
/* Nonce must be 32-bit aligned */
if (((uintptr_t)nonce & 0x3u) || (nonceSize != 16))
@ -207,11 +274,28 @@ status_t BEE_SetRegionNonce(
return kStatus_Success;
}
/*!
* brief Gets the BEE status flags.
*
* This function returns status of BEE peripheral.
*
* param base BEE peripheral address.
*
* return The status flags. This is the logical OR of members of the
* enumeration ::bee_status_flags_t
*/
uint32_t BEE_GetStatusFlags(BEE_Type *base)
{
return base->STATUS;
}
/*!
* brief Clears the BEE status flags.
*
* param base BEE peripheral base address.
* param mask The status flags to clear. This is a logical OR of members of the
* enumeration ::bee_status_flags_t
*/
void BEE_ClearStatusFlags(BEE_Type *base, uint32_t mask)
{
/* w1c */

221
ext/hal/nxp/mcux/drivers/imx/fsl_cache.c
View file

@ -2,7 +2,7 @@
* Copyright (c) 2016, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
* All rights reserved.
*
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -24,10 +24,10 @@
#define L2CACHE_SMALLWAYS_NUM 8U
#define L2CACHE_1KBCOVERTOB 1024U
#define L2CACHE_SAMLLWAYS_SIZE 16U
#define L2CACHE_LOCKDOWN_REGNUM 8 /*!< Lock down register numbers.*/
/*******************************************************************************
* Prototypes
******************************************************************************/
#define L2CACHE_LOCKDOWN_REGNUM 8 /*!< Lock down register numbers.*/
/*******************************************************************************
* Prototypes
******************************************************************************/
/*!
* @brief Set for all ways and waiting for the operation finished.
* This is provided for all the background operations.
@ -166,10 +166,15 @@ static void L2CACHE_GetWayNumSize(uint32_t *num_ways, uint32_t *size_way)
*size_way = (1 << (size - 1)) * L2CACHE_SAMLLWAYS_SIZE * L2CACHE_1KBCOVERTOB;
}
/*!
* brief Initializes the level 2 cache controller module.
*
* param config Pointer to configuration structure. See "l2cache_config_t".
*/
void L2CACHE_Init(l2cache_config_t *config)
{
assert (config);
assert(config);
uint16_t waysNum = 0xFFU; /* Default use the 8-way mask. */
uint8_t count;
uint32_t auxReg = 0;
@ -180,7 +185,7 @@ void L2CACHE_Init(l2cache_config_t *config)
if (L2CACHEC->REG1_CONTROL & L2CACHEC_REG1_CONTROL_CE_MASK)
{
L2CACHE_Disable();
}
}
/* Unlock all entries. */
if (L2CACHEC->REG1_AUX_CONTROL & L2CACHEC_REG1_AUX_CONTROL_ASSOCIATIVITY_MASK)
@ -188,20 +193,18 @@ void L2CACHE_Init(l2cache_config_t *config)
waysNum = 0xFFFFU;
}
for (count = 0; count < L2CACHE_LOCKDOWN_REGNUM; count ++)
for (count = 0; count < L2CACHE_LOCKDOWN_REGNUM; count++)
{
L2CACHE_LockdownByWayEnable(count, waysNum, false);
L2CACHE_LockdownByWayEnable(count, waysNum, false);
}
/* Set the ways and way-size etc. */
auxReg = L2CACHEC_REG1_AUX_CONTROL_ASSOCIATIVITY(config->wayNum) |
L2CACHEC_REG1_AUX_CONTROL_WAYSIZE(config->waySize) |
L2CACHEC_REG1_AUX_CONTROL_CRP(config->repacePolicy) |
L2CACHEC_REG1_AUX_CONTROL_IPE(config->istrPrefetchEnable) |
L2CACHEC_REG1_AUX_CONTROL_DPE(config->dataPrefetchEnable) |
L2CACHEC_REG1_AUX_CONTROL_NLE(config->nsLockdownEnable) |
L2CACHEC_REG1_AUX_CONTROL_FWA(config->writeAlloc) |
L2CACHEC_REG1_AUX_CONTROL_HPSDRE(config->writeAlloc);
L2CACHEC_REG1_AUX_CONTROL_WAYSIZE(config->waySize) | L2CACHEC_REG1_AUX_CONTROL_CRP(config->repacePolicy) |
L2CACHEC_REG1_AUX_CONTROL_IPE(config->istrPrefetchEnable) |
L2CACHEC_REG1_AUX_CONTROL_DPE(config->dataPrefetchEnable) |
L2CACHEC_REG1_AUX_CONTROL_NLE(config->nsLockdownEnable) |
L2CACHEC_REG1_AUX_CONTROL_FWA(config->writeAlloc) | L2CACHEC_REG1_AUX_CONTROL_HPSDRE(config->writeAlloc);
L2CACHEC->REG1_AUX_CONTROL = auxReg;
/* Set the tag/data ram latency. */
@ -209,23 +212,44 @@ void L2CACHE_Init(l2cache_config_t *config)
{
uint32_t data = 0;
/* Tag latency. */
data = L2CACHEC_REG1_TAG_RAM_CONTROL_SL(config->lateConfig->tagSetupLate)|
L2CACHEC_REG1_TAG_RAM_CONTROL_SL(config->lateConfig->tagSetupLate)|
L2CACHEC_REG1_TAG_RAM_CONTROL_RAL(config->lateConfig->tagReadLate)|
L2CACHEC_REG1_TAG_RAM_CONTROL_WAL(config->lateConfig->dataWriteLate);
data = L2CACHEC_REG1_TAG_RAM_CONTROL_SL(config->lateConfig->tagSetupLate) |
L2CACHEC_REG1_TAG_RAM_CONTROL_SL(config->lateConfig->tagSetupLate) |
L2CACHEC_REG1_TAG_RAM_CONTROL_RAL(config->lateConfig->tagReadLate) |
L2CACHEC_REG1_TAG_RAM_CONTROL_WAL(config->lateConfig->dataWriteLate);
L2CACHEC->REG1_TAG_RAM_CONTROL = data;
/* Data latency. */
data = L2CACHEC_REG1_DATA_RAM_CONTROL_SL(config->lateConfig->dataSetupLate)|
L2CACHEC_REG1_DATA_RAM_CONTROL_SL(config->lateConfig->dataSetupLate)|
L2CACHEC_REG1_DATA_RAM_CONTROL_RAL(config->lateConfig->dataReadLate)|
L2CACHEC_REG1_DATA_RAM_CONTROL_WAL(config->lateConfig->dataWriteLate);
data = L2CACHEC_REG1_DATA_RAM_CONTROL_SL(config->lateConfig->dataSetupLate) |
L2CACHEC_REG1_DATA_RAM_CONTROL_SL(config->lateConfig->dataSetupLate) |
L2CACHEC_REG1_DATA_RAM_CONTROL_RAL(config->lateConfig->dataReadLate) |
L2CACHEC_REG1_DATA_RAM_CONTROL_WAL(config->lateConfig->dataWriteLate);
L2CACHEC->REG1_DATA_RAM_CONTROL = data;
}
}
/*!
* brief Gets an available default settings for the cache controller.
*
* This function initializes the cache controller configuration structure with default settings.
* The default values are:
* code
* config->waysNum = kL2CACHE_8ways;
* config->waySize = kL2CACHE_32KbSize;
* config->repacePolicy = kL2CACHE_Roundrobin;
* config->lateConfig = NULL;
* config->istrPrefetchEnable = false;
* config->dataPrefetchEnable = false;
* config->nsLockdownEnable = false;
* config->writeAlloc = kL2CACHE_UseAwcache;
* endcode
* param config Pointer to the configuration structure.
*/
void L2CACHE_GetDefaultConfig(l2cache_config_t *config)
{
assert(config);
/* Initializes the configure structure to zero. */
memset(config, 0, sizeof(*config));
uint32_t number = (L2CACHEC->REG1_AUX_CONTROL & L2CACHEC_REG1_AUX_CONTROL_ASSOCIATIVITY_MASK) >>
L2CACHEC_REG1_AUX_CONTROL_ASSOCIATIVITY_SHIFT;
uint32_t size = (L2CACHEC->REG1_AUX_CONTROL & L2CACHEC_REG1_AUX_CONTROL_WAYSIZE_MASK) >>
@ -239,9 +263,15 @@ void L2CACHE_GetDefaultConfig(l2cache_config_t *config)
config->istrPrefetchEnable = false;
config->dataPrefetchEnable = false;
config->nsLockdownEnable = false;
config->writeAlloc = kL2CACHE_UseAwcache;
config->writeAlloc = kL2CACHE_UseAwcache;
}
/*!
* brief Enables the level 2 cache controller.
* This function enables the cache controller. Must be written using a secure access.
* If write with a Non-secure access will cause a DECERR response.
*
*/
void L2CACHE_Enable(void)
{
/* Invalidate first. */
@ -250,6 +280,12 @@ void L2CACHE_Enable(void)
L2CACHEC->REG1_CONTROL = L2CACHEC_REG1_CONTROL_CE_MASK;
}
/*!
* brief Disables the level 2 cache controller.
* This function disables the cache controller. Must be written using a secure access.
* If write with a Non-secure access will cause a DECERR response.
*
*/
void L2CACHE_Disable(void)
{
/* First CleanInvalidate all enties in the cache. */
@ -260,6 +296,11 @@ void L2CACHE_Disable(void)
__DSB();
}
/*!
* brief Invalidates the Level 2 cache.
* This function invalidates all entries in cache.
*
*/
void L2CACHE_Invalidate(void)
{
/* Invalidate all entries in cache. */
@ -268,6 +309,11 @@ void L2CACHE_Invalidate(void)
L2CACHEC->REG7_CACHE_SYNC = 0;
}
/*!
* brief Cleans the level 2 cache controller.
* This function cleans all entries in the level 2 cache controller.
*
*/
void L2CACHE_Clean(void)
{
/* Clean all entries of the cache. */
@ -276,6 +322,11 @@ void L2CACHE_Clean(void)
L2CACHEC->REG7_CACHE_SYNC = 0;
}
/*!
* brief Cleans and invalidates the level 2 cache controller.
* This function cleans and invalidates all entries in the level 2 cache controller.
*
*/
void L2CACHE_CleanInvalidate(void)
{
/* Clean all entries of the cache. */
@ -284,6 +335,17 @@ void L2CACHE_CleanInvalidate(void)
L2CACHEC->REG7_CACHE_SYNC = 0;
}
/*!
* brief Invalidates the Level 2 cache lines in the range of two physical addresses.
* This function invalidates all cache lines between two physical addresses.
*
* param address The start address of the memory to be invalidated.
* param size_byte The memory size.
* note The start address and size_byte should be 32-byte(FSL_FEATURE_L2CACHE_LINESIZE_BYTE) aligned.
* The startAddr here will be forced to align to L2 line size if startAddr
* is not aligned. For the size_byte, application should make sure the
* alignment or make sure the right operation order if the size_byte is not aligned.
*/
void L2CACHE_InvalidateByRange(uint32_t address, uint32_t size_byte)
{
uint32_t endAddr = address + size_byte;
@ -300,6 +362,17 @@ void L2CACHE_InvalidateByRange(uint32_t address, uint32_t size_byte)
L2CACHEC->REG7_CACHE_SYNC = 0;
}
/*!
* brief Cleans the Level 2 cache lines in the range of two physical addresses.
* This function cleans all cache lines between two physical addresses.
*
* param address The start address of the memory to be cleaned.
* param size_byte The memory size.
* note The start address and size_byte should be 32-byte(FSL_FEATURE_L2CACHE_LINESIZE_BYTE) aligned.
* The startAddr here will be forced to align to L2 line size if startAddr
* is not aligned. For the size_byte, application should make sure the
* alignment or make sure the right operation order if the size_byte is not aligned.
*/
void L2CACHE_CleanByRange(uint32_t address, uint32_t size_byte)
{
uint32_t num_ways = 0;
@ -327,6 +400,17 @@ void L2CACHE_CleanByRange(uint32_t address, uint32_t size_byte)
L2CACHEC->REG7_CACHE_SYNC = 0;
}
/*!
* brief Cleans and invalidates the Level 2 cache lines in the range of two physical addresses.
* This function cleans and invalidates all cache lines between two physical addresses.
*
* param address The start address of the memory to be cleaned and invalidated.
* param size_byte The memory size.
* note The start address and size_byte should be 32-byte(FSL_FEATURE_L2CACHE_LINESIZE_BYTE) aligned.
* The startAddr here will be forced to align to L2 line size if startAddr
* is not aligned. For the size_byte, application should make sure the
* alignment or make sure the right operation order if the size_byte is not aligned.
*/
void L2CACHE_CleanInvalidateByRange(uint32_t address, uint32_t size_byte)
{
uint32_t num_ways = 0;
@ -354,6 +438,23 @@ void L2CACHE_CleanInvalidateByRange(uint32_t address, uint32_t size_byte)
L2CACHEC->REG7_CACHE_SYNC = 0;
}
/*!
* brief Enables or disables to lock down the data and instruction by way.
* This function locks down the cached instruction/data by way and prevent the adresses from
* being allocated and prevent dara from being evicted out of the level 2 cache.
* But the normal cache maintenance operations that invalidate, clean or clean
* and validate cache contents affect the locked-down cache lines as normal.
*
* param masterId The master id, range from 0 ~ 7.
* param mask The ways to be enabled or disabled to lockdown.
* each bit in value is related to each way of the cache. for example:
* value: bit 0 ------ way 0.
* value: bit 1 ------ way 1.
* --------------------------
* value: bit 15 ------ way 15.
* Note: please make sure the value setting is align with your supported ways.
* param enable True enable the lockdown, false to disable the lockdown.
*/
void L2CACHE_LockdownByWayEnable(uint32_t masterId, uint32_t mask, bool enable)
{
uint8_t num_ways = (L2CACHEC->REG1_AUX_CONTROL & L2CACHEC_REG1_AUX_CONTROL_ASSOCIATIVITY_MASK) >>
@ -381,12 +482,22 @@ void L2CACHE_LockdownByWayEnable(uint32_t masterId, uint32_t mask, bool enable)
L2CACHEC->LOCKDOWN[masterId].REG9_I_LOCKDOWN = istrReg & ~mask;
}
}
#endif /* FSL_FEATURE_SOC_L2CACHEC_COUNT */
#endif /* FSL_FEATURE_SOC_L2CACHEC_COUNT */
/*!
* brief Invalidate cortex-m7 L1 instruction cache by range.
*
* param address The start address of the memory to be invalidated.
* param size_byte The memory size.
* note The start address and size_byte should be 32-byte(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE) aligned.
* The startAddr here will be forced to align to L1 I-cache line size if
* startAddr is not aligned. For the size_byte, application should make sure the
* alignment or make sure the right operation order if the size_byte is not aligned.
*/
void L1CACHE_InvalidateICacheByRange(uint32_t address, uint32_t size_byte)
{
#if (__DCACHE_PRESENT == 1U)
uint32_t addr = address & (uint32_t)~(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE - 1);
uint32_t addr = address & (uint32_t) ~(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE - 1);
int32_t size = size_byte + address - addr;
uint32_t linesize = 32U;
@ -399,9 +510,21 @@ void L1CACHE_InvalidateICacheByRange(uint32_t address, uint32_t size_byte)
}
__DSB();
__ISB();
#endif
#endif
}
/*!
* brief Invalidates all instruction caches by range.
*
* Both cortex-m7 L1 cache line and L2 PL310 cache line length is 32-byte.
*
* param address The physical address.
* param size_byte size of the memory to be invalidated.
* note address and size should be aligned to cache line size
* 32-Byte due to the cache operation unit is one cache line. The startAddr here will be forced
* to align to the cache line size if startAddr is not aligned. For the size_byte, application should
* make sure the alignment or make sure the right operation order if the size_byte is not aligned.
*/
void ICACHE_InvalidateByRange(uint32_t address, uint32_t size_byte)
{
#if defined(FSL_FEATURE_SOC_L2CACHEC_COUNT) && FSL_FEATURE_SOC_L2CACHEC_COUNT
@ -410,9 +533,21 @@ void ICACHE_InvalidateByRange(uint32_t address, uint32_t size_byte)
#endif /* !FSL_SDK_DISBLE_L2CACHE_PRESENT */
#endif /* FSL_FEATURE_SOC_L2CACHEC_COUNT */
L1CACHE_InvalidateICacheByRange(address, size_byte);
L1CACHE_InvalidateICacheByRange(address, size_byte);
}
/*!
* brief Invalidates all data caches by range.
*
* Both cortex-m7 L1 cache line and L2 PL310 cache line length is 32-byte.
*
* param address The physical address.
* param size_byte size of the memory to be invalidated.
* note address and size should be aligned to cache line size
* 32-Byte due to the cache operation unit is one cache line. The startAddr here will be forced
* to align to the cache line size if startAddr is not aligned. For the size_byte, application should
* make sure the alignment or make sure the right operation order if the size_byte is not aligned.
*/
void DCACHE_InvalidateByRange(uint32_t address, uint32_t size_byte)
{
#if defined(FSL_FEATURE_SOC_L2CACHEC_COUNT) && FSL_FEATURE_SOC_L2CACHEC_COUNT
@ -423,6 +558,18 @@ void DCACHE_InvalidateByRange(uint32_t address, uint32_t size_byte)
L1CACHE_InvalidateDCacheByRange(address, size_byte);
}
/*!
* brief Cleans all data caches by range.
*
* Both cortex-m7 L1 cache line and L2 PL310 cache line length is 32-byte.
*
* param address The physical address.
* param size_byte size of the memory to be cleaned.
* note address and size should be aligned to cache line size
* 32-Byte due to the cache operation unit is one cache line. The startAddr here will be forced
* to align to the cache line size if startAddr is not aligned. For the size_byte, application should
* make sure the alignment or make sure the right operation order if the size_byte is not aligned.
*/
void DCACHE_CleanByRange(uint32_t address, uint32_t size_byte)
{
L1CACHE_CleanDCacheByRange(address, size_byte);
@ -433,6 +580,18 @@ void DCACHE_CleanByRange(uint32_t address, uint32_t size_byte)
#endif /* FSL_FEATURE_SOC_L2CACHEC_COUNT */
}
/*!
* brief Cleans and Invalidates all data caches by range.
*
* Both cortex-m7 L1 cache line and L2 PL310 cache line length is 32-byte.
*
* param address The physical address.
* param size_byte size of the memory to be cleaned and invalidated.
* note address and size should be aligned to cache line size
* 32-Byte due to the cache operation unit is one cache line. The startAddr here will be forced
* to align to the cache line size if startAddr is not aligned. For the size_byte, application should
* make sure the alignment or make sure the right operation order if the size_byte is not aligned.
*/
void DCACHE_CleanInvalidateByRange(uint32_t address, uint32_t size_byte)
{
L1CACHE_CleanInvalidateDCacheByRange(address, size_byte);

106
ext/hal/nxp/mcux/drivers/imx/fsl_cmp.c
View file

@ -2,7 +2,7 @@
* Copyright (c) 2015, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
* All rights reserved.
*
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -13,7 +13,6 @@
#define FSL_COMPONENT_ID "platform.drivers.cmp"
#endif
/*******************************************************************************
* Prototypes
******************************************************************************/
@ -55,6 +54,19 @@ static uint32_t CMP_GetInstance(CMP_Type *base)
return instance;
}
/*!
* brief Initializes the CMP.
*
* This function initializes the CMP module. The operations included are as follows.
* - Enabling the clock for CMP module.
* - Configuring the comparator.
* - Enabling the CMP module.
* Note that for some devices, multiple CMP instances share the same clock gate. In this case, to enable the clock for
* any instance enables all CMPs. See the appropriate MCU reference manual for the clock assignment of the CMP.
*
* param base CMP peripheral base address.
* param config Pointer to the configuration structure.
*/
void CMP_Init(CMP_Type *base, const cmp_config_t *config)
{
assert(NULL != config);
@ -106,6 +118,19 @@ void CMP_Init(CMP_Type *base, const cmp_config_t *config)
CMP_Enable(base, config->enableCmp); /* Enable the CMP module after configured or not. */
}
/*!
* brief De-initializes the CMP module.
*
* This function de-initializes the CMP module. The operations included are as follows.
* - Disabling the CMP module.
* - Disabling the clock for CMP module.
*
* This function disables the clock for the CMP.
* Note that for some devices, multiple CMP instances share the same clock gate. In this case, before disabling the
* clock for the CMP, ensure that all the CMP instances are not used.
*
* param base CMP peripheral base address.
*/
void CMP_Deinit(CMP_Type *base)
{
/* Disable the CMP module. */
@ -117,10 +142,28 @@ void CMP_Deinit(CMP_Type *base)
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
}
/*!
* brief Initializes the CMP user configuration structure.
*
* This function initializes the user configuration structure to these default values.
* code
* config->enableCmp = true;
* config->hysteresisMode = kCMP_HysteresisLevel0;
* config->enableHighSpeed = false;
* config->enableInvertOutput = false;
* config->useUnfilteredOutput = false;
* config->enablePinOut = false;
* config->enableTriggerMode = false;
* endcode
* param config Pointer to the configuration structure.
*/
void CMP_GetDefaultConfig(cmp_config_t *config)
{
assert(NULL != config);
/* Initializes the configure structure to zero. */
memset(config, 0, sizeof(*config));
config->enableCmp = true; /* Enable the CMP module after initialization. */
config->hysteresisMode = kCMP_HysteresisLevel0;
config->enableHighSpeed = false;
@ -132,6 +175,17 @@ void CMP_GetDefaultConfig(cmp_config_t *config)
#endif /* FSL_FEATURE_CMP_HAS_TRIGGER_MODE */
}
/*!
* brief Sets the input channels for the comparator.
*
* This function sets the input channels for the comparator.
* Note that two input channels cannot be set the same way in the application. When the user selects the same input
* from the analog mux to the positive and negative port, the comparator is disabled automatically.
*
* param base CMP peripheral base address.
* param positiveChannel Positive side input channel number. Available range is 0-7.
* param negativeChannel Negative side input channel number. Available range is 0-7.
*/
void CMP_SetInputChannels(CMP_Type *base, uint8_t positiveChannel, uint8_t negativeChannel)
{
uint8_t tmp8 = base->MUXCR;
@ -142,6 +196,17 @@ void CMP_SetInputChannels(CMP_Type *base, uint8_t positiveChannel, uint8_t negat
}
#if defined(FSL_FEATURE_CMP_HAS_DMA) && FSL_FEATURE_CMP_HAS_DMA
/*!
* brief Enables/disables the DMA request for rising/falling events.
*
* This function enables/disables the DMA request for rising/falling events. Either event triggers the generation of
* the DMA request from CMP if the DMA feature is enabled. Both events are ignored for generating the DMA request from
* the CMP
* if the DMA is disabled.
*
* param base CMP peripheral base address.
* param enable Enables or disables the feature.
*/
void CMP_EnableDMA(CMP_Type *base, bool enable)
{
uint8_t tmp8 = base->SCR & ~(CMP_SCR_CFR_MASK | CMP_SCR_CFF_MASK); /* To avoid change the w1c bits. */
@ -158,6 +223,12 @@ void CMP_EnableDMA(CMP_Type *base, bool enable)
}
#endif /* FSL_FEATURE_CMP_HAS_DMA */
/*!
* brief Configures the filter.
*
* param base CMP peripheral base address.
* param config Pointer to the configuration structure.
*/
void CMP_SetFilterConfig(CMP_Type *base, const cmp_filter_config_t *config)
{
assert(NULL != config);
@ -183,6 +254,12 @@ void CMP_SetFilterConfig(CMP_Type *base, const cmp_filter_config_t *config)
base->FPR = CMP_FPR_FILT_PER(config->filterPeriod);
}
/*!
* brief Configures the internal DAC.
*
* param base CMP peripheral base address.
* param config Pointer to the configuration structure. "NULL" disables the feature.
*/
void CMP_SetDACConfig(CMP_Type *base, const cmp_dac_config_t *config)
{
uint8_t tmp8 = 0U;
@ -204,6 +281,12 @@ void CMP_SetDACConfig(CMP_Type *base, const cmp_dac_config_t *config)
base->DACCR = tmp8;
}
/*!
* brief Enables the interrupts.
*
* param base CMP peripheral base address.
* param mask Mask value for interrupts. See "_cmp_interrupt_enable".
*/
void CMP_EnableInterrupts(CMP_Type *base, uint32_t mask)
{
uint8_t tmp8 = base->SCR & ~(CMP_SCR_CFR_MASK | CMP_SCR_CFF_MASK); /* To avoid change the w1c bits. */
@ -219,6 +302,12 @@ void CMP_EnableInterrupts(CMP_Type *base, uint32_t mask)
base->SCR = tmp8;
}
/*!
* brief Disables the interrupts.
*
* param base CMP peripheral base address.
* param mask Mask value for interrupts. See "_cmp_interrupt_enable".
*/
void CMP_DisableInterrupts(CMP_Type *base, uint32_t mask)
{
uint8_t tmp8 = base->SCR & ~(CMP_SCR_CFR_MASK | CMP_SCR_CFF_MASK); /* To avoid change the w1c bits. */
@ -234,6 +323,13 @@ void CMP_DisableInterrupts(CMP_Type *base, uint32_t mask)
base->SCR = tmp8;
}
/*!
* brief Gets the status flags.
*
* param base CMP peripheral base address.
*
* return Mask value for the asserted flags. See "_cmp_status_flags".
*/
uint32_t CMP_GetStatusFlags(CMP_Type *base)
{
uint32_t ret32 = 0U;
@ -253,6 +349,12 @@ uint32_t CMP_GetStatusFlags(CMP_Type *base)
return ret32;
}
/*!
* brief Clears the status flags.
*
* param base CMP peripheral base address.
* param mask Mask value for the flags. See "_cmp_status_flags".
*/
void CMP_ClearStatusFlags(CMP_Type *base, uint32_t mask)
{
uint8_t tmp8 = base->SCR & ~(CMP_SCR_CFR_MASK | CMP_SCR_CFF_MASK); /* To avoid change the w1c bits. */

55
ext/hal/nxp/mcux/drivers/imx/fsl_common.c
View file

@ -1,6 +1,6 @@
/*
* Copyright (c) 2015-2016, Freescale Semiconductor, Inc.
* Copyright 2016 NXP
* Copyright 2016-2018 NXP
* All rights reserved.
*
*
@ -26,7 +26,7 @@ typedef struct _mem_align_control_block
uint32_t InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler)
{
/* Addresses for VECTOR_TABLE and VECTOR_RAM come from the linker file */
#if defined(__CC_ARM)
#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
extern uint32_t Image$$VECTOR_ROM$$Base[];
extern uint32_t Image$$VECTOR_RAM$$Base[];
extern uint32_t Image$$RW_m_data$$Base[];
@ -43,7 +43,7 @@ uint32_t InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler)
extern uint32_t __VECTOR_RAM[];
extern uint32_t __RAM_VECTOR_TABLE_SIZE_BYTES[];
uint32_t __RAM_VECTOR_TABLE_SIZE = (uint32_t)(__RAM_VECTOR_TABLE_SIZE_BYTES);
#endif /* defined(__CC_ARM) */
#endif /* defined(__CC_ARM) || defined(__ARMCC_VERSION) */
uint32_t n;
uint32_t ret;
uint32_t irqMaskValue;
@ -77,30 +77,22 @@ uint32_t InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler)
#endif /* ENABLE_RAM_VECTOR_TABLE. */
#endif /* __GIC_PRIO_BITS. */
#ifndef QN908XC_SERIES
#if (defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0))
#if !(defined(FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS) && FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS)
void EnableDeepSleepIRQ(IRQn_Type interrupt)
{
uint32_t intNumber = (uint32_t)interrupt;
#if (defined(FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS) && (FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS == 1))
{
SYSCON->STARTERP1 = 1u << intNumber;
}
#else
{
uint32_t index = 0;
uint32_t index = 0;
while (intNumber >= 32u)
{
index++;
intNumber -= 32u;
}
SYSCON->STARTERSET[index] = 1u << intNumber;
while (intNumber >= 32u)
{
index++;
intNumber -= 32u;
}
#endif /* FSL_FEATURE_STARTER_DISCONTINUOUS */
SYSCON->STARTERSET[index] = 1u << intNumber;
EnableIRQ(interrupt); /* also enable interrupt at NVIC */
}
@ -109,28 +101,19 @@ void DisableDeepSleepIRQ(IRQn_Type interrupt)
uint32_t intNumber = (uint32_t)interrupt;
DisableIRQ(interrupt); /* also disable interrupt at NVIC */
#if (defined(FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS) && (FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS == 1))
{
SYSCON->STARTERP1 &= ~(1u << intNumber);
}
#else
{
uint32_t index = 0;
uint32_t index = 0;
while (intNumber >= 32u)
{
index++;
intNumber -= 32u;
}
SYSCON->STARTERCLR[index] = 1u << intNumber;
while (intNumber >= 32u)
{
index++;
intNumber -= 32u;
}
#endif /* FSL_FEATURE_STARTER_DISCONTINUOUS */
SYSCON->STARTERCLR[index] = 1u << intNumber;
}
#endif /* FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS */
#endif /* FSL_FEATURE_SOC_SYSCON_COUNT */
#endif /* QN908XC_SERIES */
void *SDK_Malloc(size_t size, size_t alignbytes)
{
mem_align_cb_t *p_cb = NULL;

70
ext/hal/nxp/mcux/drivers/imx/fsl_common.h
View file

@ -38,8 +38,8 @@
/*! @name Driver version */
/*@{*/
/*! @brief common driver version 2.0.0. */
#define FSL_COMMON_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
/*! @brief common driver version 2.0.1. */
#define FSL_COMMON_DRIVER_VERSION (MAKE_VERSION(2, 0, 1))
/*@}*/
/* Debug console type definition. */
@ -121,11 +121,34 @@ enum _status_groups
kStatusGroup_ICS = 74, /*!< Group number for ICS status codes. */
kStatusGroup_SPDIF = 75, /*!< Group number for SPDIF status codes. */
kStatusGroup_LPC_MINISPI = 76, /*!< Group number for LPC_MINISPI status codes. */
kStatusGroup_HASHCRYPT = 77, /*!< Group number for Hashcrypt status codes */
kStatusGroup_LPC_SPI_SSP = 78, /*!< Group number for LPC_SPI_SSP status codes. */
kStatusGroup_LPC_I2C_1 = 97, /*!< Group number for LPC_I2C_1 status codes. */
kStatusGroup_NOTIFIER = 98, /*!< Group number for NOTIFIER status codes. */
kStatusGroup_DebugConsole = 99, /*!< Group number for debug console status codes. */
kStatusGroup_SEMC = 100, /*!< Group number for SEMC status codes. */
kStatusGroup_ApplicationRangeStart = 101, /*!< Starting number for application groups. */
kStatusGroup_IAP = 102, /*!< Group number for IAP status codes */
kStatusGroup_HAL_GPIO = 121, /*!< Group number for HAL GPIO status codes. */
kStatusGroup_HAL_UART = 122, /*!< Group number for HAL UART status codes. */
kStatusGroup_HAL_TIMER = 123, /*!< Group number for HAL TIMER status codes. */
kStatusGroup_HAL_SPI = 124, /*!< Group number for HAL SPI status codes. */
kStatusGroup_HAL_I2C = 125, /*!< Group number for HAL I2C status codes. */
kStatusGroup_HAL_FLASH = 126, /*!< Group number for HAL FLASH status codes. */
kStatusGroup_HAL_PWM = 127, /*!< Group number for HAL PWM status codes. */
kStatusGroup_HAL_RNG = 128, /*!< Group number for HAL RNG status codes. */
kStatusGroup_TIMERMANAGER = 135, /*!< Group number for TiMER MANAGER status codes. */
kStatusGroup_SERIALMANAGER = 136, /*!< Group number for SERIAL MANAGER status codes. */
kStatusGroup_LED = 137, /*!< Group number for LED status codes. */
kStatusGroup_BUTTON = 138, /*!< Group number for BUTTON status codes. */
kStatusGroup_EXTERN_EEPROM = 139, /*!< Group number for EXTERN EEPROM status codes. */
kStatusGroup_SHELL = 140, /*!< Group number for SHELL status codes. */
kStatusGroup_MEM_MANAGER = 141, /*!< Group number for MEM MANAGER status codes. */
kStatusGroup_LIST = 142, /*!< Group number for List status codes. */
kStatusGroup_OSA = 143, /*!< Group number for OSA status codes. */
kStatusGroup_COMMON_TASK = 144, /*!< Group number for Common task status codes. */
kStatusGroup_MSG = 145, /*!< Group number for messaging status codes. */
};
/*! @brief Generic status return codes. */
@ -224,16 +247,16 @@ _Pragma("diag_suppress=Pm120")
#if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE)
#define SDK_L2CACHE_ALIGN(var) SDK_PRAGMA(data_alignment = FSL_FEATURE_L2CACHE_LINESIZE_BYTE) var
#endif
#elif defined(__ARMCC_VERSION)
#elif defined(__CC_ARM) || defined(__ARMCC_VERSION)
/*! Macro to define a variable with alignbytes alignment */
#define SDK_ALIGN(var, alignbytes) __align(alignbytes) var
#define SDK_ALIGN(var, alignbytes) __attribute__((aligned(alignbytes))) var
/*! Macro to define a variable with L1 d-cache line size alignment */
#if defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE)
#define SDK_L1DCACHE_ALIGN(var) __align(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) var
#define SDK_L1DCACHE_ALIGN(var) __attribute__((aligned(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE))) var
#endif
/*! Macro to define a variable with L2 cache line size alignment */
#if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE)
#define SDK_L2CACHE_ALIGN(var) __align(FSL_FEATURE_L2CACHE_LINESIZE_BYTE) var
#define SDK_L2CACHE_ALIGN(var) __attribute__((aligned(FSL_FEATURE_L2CACHE_LINESIZE_BYTE))) var
#endif
#elif defined(__GNUC__)
/*! Macro to define a variable with alignbytes alignment */
@ -270,7 +293,7 @@ _Pragma("diag_suppress=Pm120")
*/
/* @{ */
#if (defined(__ICCARM__))
#if defined(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE)
#if ((!(defined(FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION) && FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION)) && defined(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE))
#define AT_NONCACHEABLE_SECTION(var) var @"NonCacheable"
#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var @"NonCacheable"
#define AT_NONCACHEABLE_SECTION_INIT(var) var @"NonCacheable.init"
@ -281,25 +304,25 @@ _Pragma("diag_suppress=Pm120")
#define AT_NONCACHEABLE_SECTION_INIT(var) var
#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var
#endif
#elif(defined(__ARMCC_VERSION))
#if defined(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE)
#elif(defined(__CC_ARM) || defined(__ARMCC_VERSION))
#if ((!(defined(FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION) && FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION)) && defined(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE))
#define AT_NONCACHEABLE_SECTION(var) __attribute__((section("NonCacheable"), zero_init)) var
#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) \
__attribute__((section("NonCacheable"), zero_init)) __align(alignbytes) var
__attribute__((section("NonCacheable"), zero_init)) __attribute__((aligned(alignbytes))) var
#define AT_NONCACHEABLE_SECTION_INIT(var) __attribute__((section("NonCacheable.init"))) var
#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) \
__attribute__((section("NonCacheable.init"))) __align(alignbytes) var
__attribute__((section("NonCacheable.init"))) __attribute__((aligned(alignbytes))) var
#else
#define AT_NONCACHEABLE_SECTION(var) var
#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) __align(alignbytes) var
#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) __attribute__((aligned(alignbytes))) var
#define AT_NONCACHEABLE_SECTION_INIT(var) var
#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) __align(alignbytes) var
#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) __attribute__((aligned(alignbytes))) var
#endif
#elif(defined(__GNUC__))
/* For GCC, when the non-cacheable section is required, please define "__STARTUP_INITIALIZE_NONCACHEDATA"
* in your projects to make sure the non-cacheable section variables will be initialized in system startup.
*/
#if defined(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE)
#if ((!(defined(FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION) && FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION)) && defined(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE))
#define AT_NONCACHEABLE_SECTION_INIT(var) __attribute__((section("NonCacheable.init"))) var
#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) \
__attribute__((section("NonCacheable.init"))) var __attribute__((aligned(alignbytes)))
@ -327,7 +350,7 @@ _Pragma("diag_suppress=Pm120")
#if (defined(__ICCARM__))
#define AT_QUICKACCESS_SECTION_CODE(func) func @"CodeQuickAccess"
#define AT_QUICKACCESS_SECTION_DATA(func) func @"DataQuickAccess"
#elif(defined(__ARMCC_VERSION))
#elif(defined(__CC_ARM) || defined(__ARMCC_VERSION))
#define AT_QUICKACCESS_SECTION_CODE(func) __attribute__((section("CodeQuickAccess"))) func
#define AT_QUICKACCESS_SECTION_DATA(func) __attribute__((section("DataQuickAccess"))) func
#elif(defined(__GNUC__))
@ -340,7 +363,7 @@ _Pragma("diag_suppress=Pm120")
#if (defined(__ICCARM__))
#define AT_QUICKACCESS_SECTION_CODE(func) func
#define AT_QUICKACCESS_SECTION_DATA(func) func
#elif(defined(__ARMCC_VERSION))
#elif(defined(__CC_ARM) || defined(__ARMCC_VERSION))
#define AT_QUICKACCESS_SECTION_CODE(func) func
#define AT_QUICKACCESS_SECTION_DATA(func) func
#elif(defined(__GNUC__))
@ -352,6 +375,17 @@ _Pragma("diag_suppress=Pm120")
#endif /* __FSL_SDK_DRIVER_QUICK_ACCESS_ENABLE */
/* @} */
/*! @name Ram Function */
#if (defined(__ICCARM__))
#define RAMFUNCTION_SECTION_CODE(func) func @"RamFunction"
#elif(defined(__CC_ARM) || defined(__ARMCC_VERSION))
#define RAMFUNCTION_SECTION_CODE(func) __attribute__((section("RamFunction"))) func
#elif(defined(__GNUC__))
#define RAMFUNCTION_SECTION_CODE(func) __attribute__((section("RamFunction"))) func
#else
#error Toolchain not supported.
#endif /* defined(__ICCARM__) */
/* @} */
/*******************************************************************************
* API
******************************************************************************/
@ -463,7 +497,7 @@ _Pragma("diag_suppress=Pm120")
}
/*!
* @brief Enaable the global IRQ
* @brief Enable the global IRQ
*
* Set the primask register with the provided primask value but not just enable the primask. The idea is for the
* convenience of integration of RTOS. some RTOS get its own management mechanism of primask. User is required to
@ -491,7 +525,7 @@ _Pragma("diag_suppress=Pm120")
*/
uint32_t InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler);
#endif /* ENABLE_RAM_VECTOR_TABLE. */
#if (defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0))
/*!
* @brief Enable specific interrupt for wake-up from deep-sleep mode.

642
ext/hal/nxp/mcux/drivers/imx/fsl_csi.c
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2017, NXP Semiconductors, Inc.
* Copyright (c) 2017-2018, NXP Semiconductors, Inc.
* All rights reserved.
*
*
@ -7,6 +7,9 @@
*/
#include "fsl_csi.h"
#if CSI_DRIVER_FRAG_MODE
#include "fsl_cache.h"
#endif
/*******************************************************************************
* Definitions
@ -20,9 +23,13 @@
/* Two frame buffer loaded to CSI register at most. */
#define CSI_MAX_ACTIVE_FRAME_NUM 2
/* CSI driver only support RGB565 and YUV422 in fragment mode, 2 bytes per pixel. */
#define CSI_FRAG_INPUT_BYTES_PER_PIXEL 2
/*******************************************************************************
* Prototypes
******************************************************************************/
/*!
* @brief Get the instance from the base address
*
@ -32,6 +39,7 @@
*/
static uint32_t CSI_GetInstance(CSI_Type *base);
#if !CSI_DRIVER_FRAG_MODE
/*!
* @brief Get the delta value of two index in queue.
*
@ -78,6 +86,12 @@ static void CSI_TransferLoadBufferToDevice(CSI_Type *base, csi_handle_t *handle)
/* Typedef for interrupt handler. */
typedef void (*csi_isr_t)(CSI_Type *base, csi_handle_t *handle);
#else
/* Typedef for interrupt handler to work in fragment mode. */
typedef void (*csi_isr_t)(CSI_Type *base, csi_frag_handle_t *handle);
#endif /* CSI_DRIVER_FRAG_MODE */
/*******************************************************************************
* Variables
******************************************************************************/
@ -90,7 +104,11 @@ static const clock_ip_name_t s_csiClocks[] = CSI_CLOCKS;
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
/* Array for the CSI driver handle. */
#if !CSI_DRIVER_FRAG_MODE
static csi_handle_t *s_csiHandle[ARRAY_SIZE(s_csiBases)];
#else
static csi_frag_handle_t *s_csiHandle[ARRAY_SIZE(s_csiBases)];
#endif
/* Array of CSI IRQ number. */
static const IRQn_Type s_csiIRQ[] = CSI_IRQS;
@ -119,6 +137,7 @@ static uint32_t CSI_GetInstance(CSI_Type *base)
return instance;
}
#if !CSI_DRIVER_FRAG_MODE
static uint32_t CSI_TransferGetQueueDelta(uint32_t startIdx, uint32_t endIdx)
{
if (endIdx >= startIdx)
@ -168,7 +187,19 @@ static void CSI_TransferLoadBufferToDevice(CSI_Type *base, csi_handle_t *handle)
/* There are two CSI buffers, so could use XOR to get the next index. */
handle->nextBufferIdx ^= 1U;
}
#endif /* CSI_DRIVER_FRAG_MODE */
/*!
* brief Initialize the CSI.
*
* This function enables the CSI peripheral clock, and resets the CSI registers.
*
* param base CSI peripheral base address.
* param config Pointer to the configuration structure.
*
* retval kStatus_Success Initialize successfully.
* retval kStatus_InvalidArgument Initialize failed because of invalid argument.
*/
status_t CSI_Init(CSI_Type *base, const csi_config_t *config)
{
assert(config);
@ -261,6 +292,13 @@ status_t CSI_Init(CSI_Type *base, const csi_config_t *config)
return kStatus_Success;
}
/*!
* brief De-initialize the CSI.
*
* This function disables the CSI peripheral clock.
*
* param base CSI peripheral base address.
*/
void CSI_Deinit(CSI_Type *base)
{
/* Disable transfer first. */
@ -271,6 +309,13 @@ void CSI_Deinit(CSI_Type *base)
#endif
}
/*!
* brief Reset the CSI.
*
* This function resets the CSI peripheral registers to default status.
*
* param base CSI peripheral base address.
*/
void CSI_Reset(CSI_Type *base)
{
uint32_t csisr;
@ -310,10 +355,31 @@ void CSI_Reset(CSI_Type *base)
base->CSIIMAG_PARA = 0U;
}
/*!
* brief Get the default configuration for to initialize the CSI.
*
* The default configuration value is:
*
* code
config->width = 320U;
config->height = 240U;
config->polarityFlags = kCSI_HsyncActiveHigh | kCSI_DataLatchOnRisingEdge;
config->bytesPerPixel = 2U;
config->linePitch_Bytes = 320U * 2U;
config->workMode = kCSI_GatedClockMode;
config->dataBus = kCSI_DataBus8Bit;
config->useExtVsync = true;
endcode
*
* param config Pointer to the CSI configuration.
*/
void CSI_GetDefaultConfig(csi_config_t *config)
{
assert(config);
/* Initializes the configure structure to zero. */
memset(config, 0, sizeof(*config));
config->width = 320U;
config->height = 240U;
config->polarityFlags = kCSI_HsyncActiveHigh | kCSI_DataLatchOnRisingEdge;
@ -324,6 +390,13 @@ void CSI_GetDefaultConfig(csi_config_t *config)
config->useExtVsync = true;
}
/*!
* brief Set the RX frame buffer address.
*
* param base CSI peripheral base address.
* param index Buffer index.
* param addr Frame buffer address to set.
*/
void CSI_SetRxBufferAddr(CSI_Type *base, uint8_t index, uint32_t addr)
{
if (index)
@ -336,6 +409,14 @@ void CSI_SetRxBufferAddr(CSI_Type *base, uint8_t index, uint32_t addr)
}
}
/*!
* brief Clear the CSI FIFO.
*
* This function clears the CSI FIFO.
*
* param base CSI peripheral base address.
* param fifo The FIFO to clear.
*/
void CSI_ClearFifo(CSI_Type *base, csi_fifo_t fifo)
{
uint32_t cr1;
@ -366,6 +447,19 @@ void CSI_ClearFifo(CSI_Type *base, csi_fifo_t fifo)
base->CSICR1 = cr1;
}
/*!
* brief Reflash the CSI FIFO DMA.
*
* This function reflashes the CSI FIFO DMA.
*
* For RXFIFO, there are two frame buffers. When the CSI module started, it saves
* the frames to frame buffer 0 then frame buffer 1, the two buffers will be
* written by turns. After reflash DMA using this function, the CSI is reset to
* save frame to buffer 0.
*
* param base CSI peripheral base address.
* param fifo The FIFO DMA to reflash.
*/
void CSI_ReflashFifoDma(CSI_Type *base, csi_fifo_t fifo)
{
uint32_t cr3 = 0U;
@ -388,6 +482,13 @@ void CSI_ReflashFifoDma(CSI_Type *base, csi_fifo_t fifo)
}
}
/*!
* brief Enable or disable the CSI FIFO DMA request.
*
* param base CSI peripheral base address.
* param fifo The FIFO DMA reques to enable or disable.
* param enable True to enable, false to disable.
*/
void CSI_EnableFifoDmaRequest(CSI_Type *base, csi_fifo_t fifo, bool enable)
{
uint32_t cr3 = 0U;
@ -412,6 +513,12 @@ void CSI_EnableFifoDmaRequest(CSI_Type *base, csi_fifo_t fifo, bool enable)
}
}
/*!
* brief Enables CSI interrupt requests.
*
* param base CSI peripheral base address.
* param mask The interrupts to enable, pass in as OR'ed value of ref _csi_interrupt_enable.
*/
void CSI_EnableInterrupts(CSI_Type *base, uint32_t mask)
{
base->CSICR1 |= (mask & CSI_CSICR1_INT_EN_MASK);
@ -419,6 +526,12 @@ void CSI_EnableInterrupts(CSI_Type *base, uint32_t mask)
base->CSICR18 |= ((mask & CSI_CSICR18_INT_EN_MASK) >> 6U);
}
/*!
* brief Disable CSI interrupt requests.
*
* param base CSI peripheral base address.
* param mask The interrupts to disable, pass in as OR'ed value of ref _csi_interrupt_enable.
*/
void CSI_DisableInterrupts(CSI_Type *base, uint32_t mask)
{
base->CSICR1 &= ~(mask & CSI_CSICR1_INT_EN_MASK);
@ -426,6 +539,20 @@ void CSI_DisableInterrupts(CSI_Type *base, uint32_t mask)
base->CSICR18 &= ~((mask & CSI_CSICR18_INT_EN_MASK) >> 6U);
}
#if !CSI_DRIVER_FRAG_MODE
/*!
* brief Initializes the CSI handle.
*
* This function initializes CSI handle, it should be called before any other
* CSI transactional functions.
*
* param base CSI peripheral base address.
* param handle Pointer to the handle structure.
* param callback Callback function for CSI transfer.
* param userData Callback function parameter.
*
* retval kStatus_Success Handle created successfully.
*/
status_t CSI_TransferCreateHandle(CSI_Type *base,
csi_handle_t *handle,
csi_transfer_callback_t callback,
@ -454,6 +581,20 @@ status_t CSI_TransferCreateHandle(CSI_Type *base,
return kStatus_Success;
}
/*!
* brief Start the transfer using transactional functions.
*
* When the empty frame buffers have been submit to CSI driver using function
* ref CSI_TransferSubmitEmptyBuffer, user could call this function to start
* the transfer. The incoming frame will be saved to the empty frame buffer,
* and user could be optionally notified through callback function.
*
* param base CSI peripheral base address.
* param handle Pointer to the handle structure.
*
* retval kStatus_Success Started successfully.
* retval kStatus_CSI_NoEmptyBuffer Could not start because no empty frame buffer in queue.
*/
status_t CSI_TransferStart(CSI_Type *base, csi_handle_t *handle)
{
assert(handle);
@ -495,6 +636,18 @@ status_t CSI_TransferStart(CSI_Type *base, csi_handle_t *handle)
return kStatus_Success;
}
/*!
* brief Stop the transfer using transactional functions.
*
* The driver does not clean the full frame buffers in queue. In other words, after
* calling this function, user still could get the full frame buffers in queue
* using function ref CSI_TransferGetFullBuffer.
*
* param base CSI peripheral base address.
* param handle Pointer to the handle structure.
*
* retval kStatus_Success Stoped successfully.
*/
status_t CSI_TransferStop(CSI_Type *base, csi_handle_t *handle)
{
assert(handle);
@ -512,6 +665,20 @@ status_t CSI_TransferStop(CSI_Type *base, csi_handle_t *handle)
return kStatus_Success;
}
/*!
* brief Submit empty frame buffer to queue.
*
* This function could be called before ref CSI_TransferStart or after ref
* CSI_TransferStart. If there is no room in queue to store the empty frame
* buffer, this function returns error.
*
* param base CSI peripheral base address.
* param handle Pointer to the handle structure.
* param frameBuffer Empty frame buffer to submit.
*
* retval kStatus_Success Started successfully.
* retval kStatus_CSI_QueueFull Could not submit because there is no room in queue.
*/
status_t CSI_TransferSubmitEmptyBuffer(CSI_Type *base, csi_handle_t *handle, uint32_t frameBuffer)
{
uint32_t csicr1;
@ -554,6 +721,21 @@ status_t CSI_TransferSubmitEmptyBuffer(CSI_Type *base, csi_handle_t *handle, uin
return kStatus_Success;
}
/*!
* brief Get one full frame buffer from queue.
*
* After the transfer started using function ref CSI_TransferStart, the incoming
* frames will be saved to the empty frame buffers in queue. This function gets
* the full-filled frame buffer from the queue. If there is no full frame buffer
* in queue, this function returns error.
*
* param base CSI peripheral base address.
* param handle Pointer to the handle structure.
* param frameBuffer Full frame buffer.
*
* retval kStatus_Success Started successfully.
* retval kStatus_CSI_NoFullBuffer There is no full frame buffer in queue.
*/
status_t CSI_TransferGetFullBuffer(CSI_Type *base, csi_handle_t *handle, uint32_t *frameBuffer)
{
uint32_t csicr1;
@ -578,6 +760,15 @@ status_t CSI_TransferGetFullBuffer(CSI_Type *base, csi_handle_t *handle, uint32_
return kStatus_Success;
}
/*!
* brief CSI IRQ handle function.
*
* This function handles the CSI IRQ request to work with CSI driver transactional
* APIs.
*
* param base CSI peripheral base address.
* param handle CSI handle pointer.
*/
void CSI_TransferHandleIRQ(CSI_Type *base, csi_handle_t *handle)
{
uint32_t queueDrvWriteIdx;
@ -647,6 +838,455 @@ void CSI_TransferHandleIRQ(CSI_Type *base, csi_handle_t *handle)
}
}
#else /* CSI_DRIVER_FRAG_MODE */
#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
__asm void CSI_ExtractYFromYUYV(void *datBase, const void *dmaBase, size_t count)
{
/* clang-format off */
push {r4-r7, lr}
10
LDMIA R1!, {r3-r6}
bfi r7, r3, #0, #8 /* Y0 */
bfi ip, r5, #0, #8 /* Y4 */
lsr r3, r3, #16
lsr r5, r5, #16
bfi r7, r3, #8, #8 /* Y1 */
bfi ip, r5, #8, #8 /* Y5 */
bfi r7, r4, #16, #8 /* Y2 */
bfi ip, r6, #16, #8 /* Y6 */
lsr r4, r4, #16
lsr r6, r6, #16
bfi r7, r4, #24, #8 /* Y3 */
bfi ip, r6, #24, #8 /* Y7 */
STMIA r0!, {r7, ip}
subs r2, #8
bne %b10
pop {r4-r7, pc}
/* clang-format on */
}
__asm void CSI_ExtractYFromUYVY(void *datBase, const void *dmaBase, size_t count)
{
/* clang-format off */
push {r4-r7, lr}
10
LDMIA R1!, {r3-r6}
lsr r3, r3, #8
lsr r5, r5, #8
bfi r7, r3, #0, #8 /* Y0 */
bfi ip, r5, #0, #8 /* Y4 */
lsr r3, r3, #16
lsr r5, r5, #16
bfi r7, r3, #8, #8 /* Y1 */
bfi ip, r5, #8, #8 /* Y5 */
lsr r4, r4, #8
lsr r6, r6, #8
bfi r7, r4, #16, #8 /* Y2 */
bfi ip, r6, #16, #8 /* Y6 */
lsr r4, r4, #16
lsr r6, r6, #16
bfi r7, r4, #24, #8 /* Y3 */
bfi ip, r6, #24, #8 /* Y7 */
STMIA r0!, {r7, ip}
subs r2, #8
bne %b10
pop {r4-r7, pc}
/* clang-format on */
}
#elif(defined(__GNUC__) || defined(__ICCARM__))
#if defined(__ICCARM__)
#pragma diag_suppress = Pe940
#endif
__attribute__((naked)) void CSI_ExtractYFromYUYV(void *datBase, const void *dmaBase, size_t count)
{
/* clang-format off */
__asm volatile(
" push {r1-r7, r12, lr} \n"
"loop0: \n"
" ldmia r1!, {r3-r6} \n"
" bfi r7, r3, #0, #8 \n" /* Y0 */
" bfi r12, r5, #0, #8 \n" /* Y4 */
" lsr r3, r3, #16 \n"
" lsr r5, r5, #16 \n"
" bfi r7, r3, #8, #8 \n" /* Y1 */
" bfi r12, r5, #8, #8 \n" /* Y5 */
" bfi r7, r4, #16, #8 \n" /* Y2 */
" bfi r12, r6, #16, #8 \n" /* Y6 */
" lsr r4, r4, #16 \n"
" lsr r6, r6, #16 \n"
" bfi r7, r4, #24, #8 \n" /* Y3 */
" bfi r12, r6, #24, #8 \n" /* Y7 */
" stmia r0!, {r7, r12} \n"
" subs r2, #8 \n"
" bne loop0 \n"
" pop {r1-r7, r12, pc} \n");
/* clang-format on */
}
__attribute__((naked)) void CSI_ExtractYFromUYVY(void *datBase, const void *dmaBase, size_t count)
{
/* clang-format off */
__asm volatile(
" push {r1-r7, r12, lr} \n"
"loop1: \n"
" ldmia r1!, {r3-r6} \n"
" lsr r3, r3, #8 \n"
" lsr r5, r5, #8 \n"
" bfi r7, r3, #0, #8 \n" /* Y0 */
" bfi r12, r5, #0, #8 \n" /* Y4 */
" lsr r3, r3, #16 \n"
" lsr r5, r5, #16 \n"
" bfi r7, r3, #8, #8 \n" /* Y1 */
" bfi r12, r5, #8, #8 \n" /* Y5 */
" lsr r4, r4, #8 \n"
" lsr r6, r6, #8 \n"
" bfi r7, r4, #16, #8 \n" /* Y2 */
" bfi r12, r6, #16, #8 \n" /* Y6 */
" lsr r4, r4, #16 \n"
" lsr r6, r6, #16 \n"
" bfi r7, r4, #24, #8 \n" /* Y3 */
" bfi r12, r6, #24, #8 \n" /* Y7 */
" stmia r0!, {r7, r12} \n"
" subs r2, #8 \n"
" bne loop1 \n"
" pop {r1-r7, r12, pc} \n");
/* clang-format on */
}
#if defined(__ICCARM__)
#pragma diag_default = Pe940
#endif
#else
#error Toolchain not supported.
#endif
static void CSI_MemCopy(void *pDest, const void *pSrc, size_t cnt)
{
memcpy(pDest, pSrc, cnt);
}
/*!
* brief Initialize the CSI to work in fragment mode.
*
* This function enables the CSI peripheral clock, and resets the CSI registers.
*
* param base CSI peripheral base address.
*/
void CSI_FragModeInit(CSI_Type *base)
{
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
uint32_t instance = CSI_GetInstance(base);
CLOCK_EnableClock(s_csiClocks[instance]);
#endif
CSI_Reset(base);
}
/*!
* brief De-initialize the CSI.
*
* This function disables the CSI peripheral clock.
*
* param base CSI peripheral base address.
*/
void CSI_FragModeDeinit(CSI_Type *base)
{
CSI_Deinit(base);
}
/*!
* brief Create handle for CSI work in fragment mode.
*
* param base CSI peripheral base address.
* param handle Pointer to the transactional handle.
* param config Pointer to the configuration structure.
* param callback Callback function for CSI transfer.
* param userData Callback function parameter.
*
* retval kStatus_Success Initialize successfully.
* retval kStatus_InvalidArgument Initialize failed because of invalid argument.
*/
status_t CSI_FragModeCreateHandle(CSI_Type *base,
csi_frag_handle_t *handle,
const csi_frag_config_t *config,
csi_frag_transfer_callback_t callback,
void *userData)
{
assert(config);
uint32_t reg;
uint32_t instance;
uint32_t imgWidth_Bytes;
imgWidth_Bytes = config->width * CSI_FRAG_INPUT_BYTES_PER_PIXEL;
/* The image buffer line width should be multiple of 8-bytes. */
if ((imgWidth_Bytes & 0x07) != 0)
{
return kStatus_InvalidArgument;
}
/* Camera frame height must be dividable by DMA buffer line. */
if (config->height % config->dmaBufferLine != 0)
{
return kStatus_InvalidArgument;
}
memset(handle, 0, sizeof(*handle));
handle->callback = callback;
handle->userData = userData;
handle->height = config->height;
handle->width = config->width;
handle->maxLinePerFrag = config->dmaBufferLine;
handle->dmaBytePerLine = config->width * CSI_FRAG_INPUT_BYTES_PER_PIXEL;
handle->isDmaBufferCachable = config->isDmaBufferCachable;
/* Get instance from peripheral base address. */
instance = CSI_GetInstance(base);
/* Save the handle in global variables to support the double weak mechanism. */
s_csiHandle[instance] = handle;
s_csiIsr = CSI_FragModeTransferHandleIRQ;
EnableIRQ(s_csiIRQ[instance]);
/* Configure CSICR1. CSICR1 has been reset to the default value, so could write it directly. */
reg = ((uint32_t)config->workMode) | config->polarityFlags | CSI_CSICR1_FCC_MASK;
if (config->useExtVsync)
{
reg |= CSI_CSICR1_EXT_VSYNC_MASK;
}
base->CSICR1 = reg;
/* No stride. */
base->CSIFBUF_PARA = 0;
/* Enable auto ECC. */
base->CSICR3 |= CSI_CSICR3_ECC_AUTO_EN_MASK;
/*
* For better performance.
* The DMA burst size could be set to 16 * 8 byte, 8 * 8 byte, or 4 * 8 byte,
* choose the best burst size based on bytes per line.
*/
if (!(imgWidth_Bytes % (8 * 16)))
{
base->CSICR2 = CSI_CSICR2_DMA_BURST_TYPE_RFF(3U);
base->CSICR3 = (CSI->CSICR3 & ~CSI_CSICR3_RxFF_LEVEL_MASK) | ((2U << CSI_CSICR3_RxFF_LEVEL_SHIFT));
}
else if (!(imgWidth_Bytes % (8 * 8)))
{
base->CSICR2 = CSI_CSICR2_DMA_BURST_TYPE_RFF(2U);
base->CSICR3 = (CSI->CSICR3 & ~CSI_CSICR3_RxFF_LEVEL_MASK) | ((1U << CSI_CSICR3_RxFF_LEVEL_SHIFT));
}
else
{
base->CSICR2 = CSI_CSICR2_DMA_BURST_TYPE_RFF(1U);
base->CSICR3 = (CSI->CSICR3 & ~CSI_CSICR3_RxFF_LEVEL_MASK) | ((0U << CSI_CSICR3_RxFF_LEVEL_SHIFT));
}
base->CSIDMASA_FB1 = config->dmaBufferAddr0;
base->CSIDMASA_FB2 = config->dmaBufferAddr1;
if (handle->isDmaBufferCachable)
{
DCACHE_CleanInvalidateByRange(config->dmaBufferAddr0,
config->dmaBufferLine * config->width * CSI_FRAG_INPUT_BYTES_PER_PIXEL);
DCACHE_CleanInvalidateByRange(config->dmaBufferAddr1,
config->dmaBufferLine * config->width * CSI_FRAG_INPUT_BYTES_PER_PIXEL);
}
return kStatus_Success;
}
/*!
* brief Start to capture a image.
*
* param base CSI peripheral base address.
* param handle Pointer to the transactional handle.
* param config Pointer to the capture configuration.
*
* retval kStatus_Success Initialize successfully.
* retval kStatus_InvalidArgument Initialize failed because of invalid argument.
*/
status_t CSI_FragModeTransferCaptureImage(CSI_Type *base,
csi_frag_handle_t *handle,
const csi_frag_capture_config_t *config)
{
assert(config);
uint16_t windowWidth;
/*
* If no special window setting, capture full frame.
* If capture window, then capture 1 one each fragment.
*/
if (config->window != NULL)
{
handle->windowULX = config->window->windowULX;
handle->windowULY = config->window->windowULY;
handle->windowLRX = config->window->windowLRX;
handle->windowLRY = config->window->windowLRY;
handle->linePerFrag = 1;
}
else
{
handle->windowULX = 0;
handle->windowULY = 0;
handle->windowLRX = handle->width - 1;
handle->windowLRY = handle->height - 1;
handle->linePerFrag = handle->maxLinePerFrag;
}
windowWidth = handle->windowLRX - handle->windowULX + 1;
if (config->outputGrayScale)
{
/* When output format is gray, the window width must be multiple value of 8. */
if (windowWidth % 8 != 0)
{
return kStatus_InvalidArgument;
}
handle->datBytePerLine = windowWidth;
if (handle->inputFormat == kCSI_FragInputYUYV)
{
handle->copyFunc = CSI_ExtractYFromYUYV;
}
else
{
handle->copyFunc = CSI_ExtractYFromUYVY;
}
}
else
{
handle->datBytePerLine = windowWidth * CSI_FRAG_INPUT_BYTES_PER_PIXEL;
handle->copyFunc = CSI_MemCopy;
}
handle->dmaCurLine = 0;
handle->outputBuffer = (uint32_t)config->buffer;
handle->datCurWriteAddr = (uint32_t)config->buffer;
/* Image parameter. */
base->CSIIMAG_PARA =
((uint32_t)(handle->width * CSI_FRAG_INPUT_BYTES_PER_PIXEL) << CSI_CSIIMAG_PARA_IMAGE_WIDTH_SHIFT) |
((uint32_t)(handle->linePerFrag) << CSI_CSIIMAG_PARA_IMAGE_HEIGHT_SHIFT);
/*
* Write to memory from first completed frame.
* DMA base addr switch at dma transfer done.
*/
base->CSICR18 = (base->CSICR18 & ~CSI_CSICR18_MASK_OPTION_MASK) | CSI_CSICR18_MASK_OPTION(0);
CSI_EnableInterrupts(base, kCSI_StartOfFrameInterruptEnable | kCSI_RxBuffer1DmaDoneInterruptEnable |
kCSI_RxBuffer0DmaDoneInterruptEnable);
return kStatus_Success;
}
/*!
* brief Abort image capture.
*
* Abort image capture initialized by ref CSI_FragModeTransferCaptureImage.
*
* param base CSI peripheral base address.
* param handle Pointer to the transactional handle.
*/
void CSI_FragModeTransferAbortCaptureImage(CSI_Type *base, csi_frag_handle_t *handle)
{
CSI_Stop(base);
CSI_DisableInterrupts(base, kCSI_StartOfFrameInterruptEnable | kCSI_RxBuffer1DmaDoneInterruptEnable |
kCSI_RxBuffer0DmaDoneInterruptEnable);
}
/*!
* brief CSI IRQ handle function.
*
* This function handles the CSI IRQ request to work with CSI driver fragment mode
* APIs.
*
* param base CSI peripheral base address.
* param handle CSI handle pointer.
*/
void CSI_FragModeTransferHandleIRQ(CSI_Type *base, csi_frag_handle_t *handle)
{
uint32_t csisr = base->CSISR;
uint32_t dmaBufAddr;
uint16_t line;
/* Clear the error flags. */
base->CSISR = csisr;
/* Start of frame, clear the FIFO and start receiving. */
if (csisr & kCSI_StartOfFrameFlag)
{
/* Reflash the DMA and enable RX DMA request. */
base->CSICR3 |= (CSI_CSICR3_DMA_REFLASH_RFF_MASK | CSI_CSICR3_DMA_REQ_EN_RFF_MASK);
CSI_Start(base);
handle->dmaCurLine = 0;
handle->datCurWriteAddr = handle->outputBuffer;
}
else if ((csisr & (CSI_CSISR_DMA_TSF_DONE_FB2_MASK | CSI_CSISR_DMA_TSF_DONE_FB1_MASK)) != 0)
{
if ((csisr & CSI_CSISR_DMA_TSF_DONE_FB1_MASK) == CSI_CSISR_DMA_TSF_DONE_FB1_MASK)
{
dmaBufAddr = base->CSIDMASA_FB1;
}
else
{
dmaBufAddr = base->CSIDMASA_FB2;
}
if (handle->isDmaBufferCachable)
{
DCACHE_InvalidateByRange(dmaBufAddr, handle->dmaBytePerLine * handle->linePerFrag);
}
/* Copy from DMA buffer to user data buffer. */
dmaBufAddr += (handle->windowULX * CSI_FRAG_INPUT_BYTES_PER_PIXEL);
for (line = 0; line < handle->linePerFrag; line++)
{
if (handle->dmaCurLine + line > handle->windowLRY)
{
/* out of window range */
break;
}
else if (handle->dmaCurLine + line >= handle->windowULY)
{
handle->copyFunc((void *)(handle->datCurWriteAddr), (void const *)dmaBufAddr, handle->datBytePerLine);
handle->datCurWriteAddr += handle->datBytePerLine;
dmaBufAddr += handle->dmaBytePerLine;
}
else
{
}
}
handle->dmaCurLine += handle->linePerFrag;
if (handle->dmaCurLine >= handle->height)
{
CSI_Stop(base);
CSI_DisableInterrupts(base, kCSI_StartOfFrameInterruptEnable | kCSI_RxBuffer1DmaDoneInterruptEnable |
kCSI_RxBuffer0DmaDoneInterruptEnable);
/* Image captured. Stop the CSI. */
if (handle->callback)
{
handle->callback(base, handle, kStatus_CSI_FrameDone, handle->userData);
}
}
}
else
{
}
}
#endif /* CSI_DRIVER_FRAG_MODE */
#if defined(CSI)
void CSI_DriverIRQHandler(void)
{

191
ext/hal/nxp/mcux/drivers/imx/fsl_csi.h
View file

@ -1,8 +1,8 @@
/*
* Copyright (c) 2017, NXP Semiconductors, Inc.
* Copyright (c) 2017-2018, NXP Semiconductors, Inc.
* All rights reserved.
*
*
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -22,7 +22,7 @@
/*! @name Driver version */
/*@{*/
#define FSL_CSI_DRIVER_VERSION (MAKE_VERSION(2, 0, 1))
#define FSL_CSI_DRIVER_VERSION (MAKE_VERSION(2, 0, 2))
/*@}*/
/*! @brief Size of the frame buffer queue used in CSI transactional function. */
@ -30,6 +30,11 @@
#define CSI_DRIVER_QUEUE_SIZE 4U
#endif
/*! @brief Enable fragment capture function or not. */
#ifndef CSI_DRIVER_FRAG_MODE
#define CSI_DRIVER_FRAG_MODE 0U
#endif
/*
* There is one empty room in queue, used to distinguish whether the queue
* is full or empty. When header equals tail, the queue is empty; when header
@ -100,8 +105,8 @@ enum _csi_polarity_flags
kCSI_HsyncActiveHigh = CSI_CSICR1_HSYNC_POL_MASK, /*!< HSYNC is active high. */
kCSI_DataLatchOnRisingEdge = CSI_CSICR1_REDGE_MASK, /*!< Pixel data latched at rising edge of pixel clock. */
kCSI_DataLatchOnFallingEdge = 0U, /*!< Pixel data latched at falling edge of pixel clock. */
kCSI_VsyncActiveHigh = 0U, /*!< VSYNC is active high. */
kCSI_VsyncActiveLow = CSI_CSICR1_SOF_POL_MASK, /*!< VSYNC is active low. */
kCSI_VsyncActiveHigh = 0U, /*!< VSYNC is active high. */
kCSI_VsyncActiveLow = CSI_CSICR1_SOF_POL_MASK, /*!< VSYNC is active low. */
};
/*! @brief Configuration to initialize the CSI module. */
@ -232,6 +237,99 @@ struct _csi_handle
void *userData; /*!< CSI callback function parameter.*/
};
#if CSI_DRIVER_FRAG_MODE
/*! @brief Input pixel format when CSI works in fragment mode. */
typedef enum _csi_frag_input_pixel_format
{
kCSI_FragInputRGB565 = 0, /*!< Input pixel format is RGB565. */
kCSI_FragInputYUYV, /*!< Input pixel format is YUV422 (Y-U-Y-V). */
kCSI_FragInputUYVY, /*!< Input pixel format is YUV422 (U-Y-V-Y). */
} csi_frag_input_pixel_format_t;
/*! @brief Configuration for CSI module to work in fragment mode. */
typedef struct _csi_frag_config
{
uint16_t width; /*!< Pixels of the input frame. */
uint16_t height; /*!< Lines of the input frame. */
uint32_t polarityFlags; /*!< Timing signal polarity flags, OR'ed value of @ref _csi_polarity_flags. */
csi_work_mode_t workMode; /*!< CSI work mode. */
csi_data_bus_t dataBus; /*!< Data bus width. */
bool useExtVsync; /*!< In CCIR656 progressive mode, set true to use external VSYNC signal, set false
to use internal VSYNC signal decoded from SOF. */
csi_frag_input_pixel_format_t inputFormat; /*!< Input pixel format. */
uint32_t dmaBufferAddr0; /*!< Buffer 0 used for CSI DMA, must be double word aligned. */
uint32_t dmaBufferAddr1; /*!< Buffer 1 used for CSI DMA, must be double word aligned. */
uint16_t dmaBufferLine; /*!< Lines of each DMA buffer. The size of DMA buffer 0 and
buffer 1 must be the same. Camera frame height must be
dividable by this value. */
bool isDmaBufferCachable; /*!< Is DMA buffer cachable or not. */
} csi_frag_config_t;
/* Forward declaration of the handle typedef. */
typedef struct _csi_frag_handle csi_frag_handle_t;
/*!
* @brief CSI fragment transfer callback function.
*
* When a new frame is received and saved to the frame buffer queue, the callback
* is called and the pass the status @ref kStatus_CSI_FrameDone to upper layer.
*/
typedef void (*csi_frag_transfer_callback_t)(CSI_Type *base,
csi_frag_handle_t *handle,
status_t status,
void *userData);
/*!
* @brief Function to copy data from CSI DMA buffer to user buffer.
*/
typedef void (*csi_frag_copy_func_t)(void *pDest, const void *pSrc, size_t cnt);
/*! @brief Handle for CSI module to work in fragment mode. */
struct _csi_frag_handle
{
uint16_t width; /*!< Pixels of the input frame. */
uint16_t height; /*!< Lines of the input frame. */
uint16_t maxLinePerFrag; /*!< Max line saved per fragment. */
uint16_t linePerFrag; /*!< Actual line saved per fragment. */
uint16_t dmaBytePerLine; /*!< How many bytes DMA transfered each line. */
uint16_t datBytePerLine; /*!< How many bytes copied to user buffer each line. */
uint16_t dmaCurLine; /*!< Current line index in whole frame. */
uint16_t windowULX; /*!< X of windows upper left corner. */
uint16_t windowULY; /*!< Y of windows upper left corner. */
uint16_t windowLRX; /*!< X of windows lower right corner. */
uint16_t windowLRY; /*!< Y of windows lower right corner. */
uint32_t outputBuffer; /*!< Address of buffer to save the captured image. */
uint32_t datCurWriteAddr; /*!< Current write address to the user buffer. */
csi_frag_input_pixel_format_t inputFormat; /*!< Input pixel format. */
csi_frag_transfer_callback_t callback; /*!< Callback function. */
void *userData; /*!< CSI callback function parameter.*/
csi_frag_copy_func_t copyFunc; /*!< Function to copy data from CSI DMA buffer to user buffer. */
bool isDmaBufferCachable; /*!< Is DMA buffer cachable or not. */
};
/*! @brief Handle for CSI module to work in fragment mode. */
typedef struct _csi_frag_window
{
uint16_t windowULX; /*!< X of windows upper left corner. */
uint16_t windowULY; /*!< Y of windows upper left corner. */
uint16_t windowLRX; /*!< X of windows lower right corner. */
uint16_t windowLRY; /*!< Y of windows lower right corner. */
} csi_frag_window_t;
/*! @brief Handle for CSI module to work in fragment mode. */
typedef struct _csi_frag_capture_config
{
bool outputGrayScale; /*!< Output gray scale image or not, could only enable when input format is YUV. */
uint32_t buffer; /*!< Buffer to save the captured image. */
csi_frag_window_t *window; /*!< Capture window. Capture full frame if set this to NULL. When output format is gray,
the window width must be multiple value of 8. */
} csi_frag_capture_config_t;
#endif /* CSI_DRIVER_FRAG_MODE */
/*******************************************************************************
* API
******************************************************************************/
@ -429,6 +527,7 @@ static inline void CSI_ClearStatusFlags(CSI_Type *base, uint32_t statusMask)
}
/* @} */
#if !CSI_DRIVER_FRAG_MODE
/*!
* @name Transactional
* @{
@ -527,6 +626,88 @@ status_t CSI_TransferGetFullBuffer(CSI_Type *base, csi_handle_t *handle, uint32_
void CSI_TransferHandleIRQ(CSI_Type *base, csi_handle_t *handle);
/* @} */
#else
/*!
* @name Fragment mode
* @{
*/
/*!
* @brief Initialize the CSI to work in fragment mode.
*
* This function enables the CSI peripheral clock, and resets the CSI registers.
*
* @param base CSI peripheral base address.
*/
void CSI_FragModeInit(CSI_Type *base);
/*!
* @brief De-initialize the CSI.
*
* This function disables the CSI peripheral clock.
*
* @param base CSI peripheral base address.
*/
void CSI_FragModeDeinit(CSI_Type *base);
/*!
* @brief Create handle for CSI work in fragment mode.
*
* @param base CSI peripheral base address.
* @param handle Pointer to the transactional handle.
* @param config Pointer to the configuration structure.
* @param callback Callback function for CSI transfer.
* @param userData Callback function parameter.
*
* @retval kStatus_Success Initialize successfully.
* @retval kStatus_InvalidArgument Initialize failed because of invalid argument.
*/
status_t CSI_FragModeCreateHandle(CSI_Type *base,
csi_frag_handle_t *handle,
const csi_frag_config_t *config,
csi_frag_transfer_callback_t callback,
void *userData);
/*!
* @brief Start to capture a image.
*
* @param base CSI peripheral base address.
* @param handle Pointer to the transactional handle.
* @param config Pointer to the capture configuration.
*
* @retval kStatus_Success Initialize successfully.
* @retval kStatus_InvalidArgument Initialize failed because of invalid argument.
*/
status_t CSI_FragModeTransferCaptureImage(CSI_Type *base,
csi_frag_handle_t *handle,
const csi_frag_capture_config_t *config);
/*!
* @brief Abort image capture.
*
* Abort image capture initialized by @ref CSI_FragModeTransferCaptureImage.
*
* @param base CSI peripheral base address.
* @param handle Pointer to the transactional handle.
*/
void CSI_FragModeTransferAbortCaptureImage(CSI_Type *base, csi_frag_handle_t *handle);
/*!
* @brief CSI IRQ handle function.
*
* This function handles the CSI IRQ request to work with CSI driver fragment mode
* APIs.
*
* @param base CSI peripheral base address.
* @param handle CSI handle pointer.
*/
void CSI_FragModeTransferHandleIRQ(CSI_Type *base, csi_frag_handle_t *handle);
/* @} */
#endif /* CSI_DRIVER_FRAG_MODE */
#if defined(__cplusplus)
}
#endif

151
ext/hal/nxp/mcux/drivers/imx/fsl_dcdc.c
View file

@ -2,7 +2,7 @@
* Copyright (c) 2017, NXP
* All rights reserved.
*
*
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -13,7 +13,6 @@
#define FSL_COMPONENT_ID "platform.drivers.dcdc_1"
#endif
/*******************************************************************************
* Prototypes
******************************************************************************/
@ -56,6 +55,11 @@ static uint32_t DCDC_GetInstance(DCDC_Type *base)
return instance;
}
/*!
* brief Enable the access to DCDC registers.
*
* param base DCDC peripheral base address.
*/
void DCDC_Init(DCDC_Type *base)
{
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
@ -64,6 +68,11 @@ void DCDC_Init(DCDC_Type *base)
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
}
/*!
* brief Disable the access to DCDC registers.
*
* param base DCDC peripheral base address.
*/
void DCDC_Deinit(DCDC_Type *base)
{
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
@ -72,6 +81,12 @@ void DCDC_Deinit(DCDC_Type *base)
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
}
/*!
* brief Configure the DCDC clock source.
*
* param base DCDC peripheral base address.
* param clockSource Clock source for DCDC. See to "dcdc_clock_source_t".
*/
void DCDC_SetClockSource(DCDC_Type *base, dcdc_clock_source_t clockSource)
{
uint32_t tmp32;
@ -99,10 +114,31 @@ void DCDC_SetClockSource(DCDC_Type *base, dcdc_clock_source_t clockSource)
base->REG0 = tmp32;
}
/*!
* brief Get the default setting for detection configuration.
*
* The default configuration are set according to responding registers' setting when powered on.
* They are:
* code
* config->enableXtalokDetection = false;
* config->powerDownOverVoltageDetection = true;
* config->powerDownLowVlotageDetection = false;
* config->powerDownOverCurrentDetection = true;
* config->powerDownPeakCurrentDetection = true;
* config->powerDownZeroCrossDetection = true;
* config->OverCurrentThreshold = kDCDC_OverCurrentThresholdAlt0;
* config->PeakCurrentThreshold = kDCDC_PeakCurrentThresholdAlt0;
* endcode
*
* param config Pointer to configuration structure. See to "dcdc_detection_config_t"
*/
void DCDC_GetDefaultDetectionConfig(dcdc_detection_config_t *config)
{
assert(NULL != config);
/* Initializes the configure structure to zero. */
memset(config, 0, sizeof(*config));
config->enableXtalokDetection = false;
config->powerDownOverVoltageDetection = true;
config->powerDownLowVlotageDetection = false;
@ -113,6 +149,12 @@ void DCDC_GetDefaultDetectionConfig(dcdc_detection_config_t *config)
config->PeakCurrentThreshold = kDCDC_PeakCurrentThresholdAlt0;
}
/*!
* breif Configure the DCDC detection.
*
* param base DCDC peripheral base address.
* param config Pointer to configuration structure. See to "dcdc_detection_config_t"
*/
void DCDC_SetDetectionConfig(DCDC_Type *base, const dcdc_detection_config_t *config)
{
assert(NULL != config);
@ -153,16 +195,39 @@ void DCDC_SetDetectionConfig(DCDC_Type *base, const dcdc_detection_config_t *con
base->REG0 = tmp32;
}
/*!
* brief Get the default setting for low power configuration.
*
* The default configuration are set according to responding registers' setting when powered on.
* They are:
* code
* config->enableOverloadDetection = true;
* config->enableAdjustHystereticValue = false;
* config->countChargingTimePeriod = kDCDC_CountChargingTimePeriod8Cycle;
* config->countChargingTimeThreshold = kDCDC_CountChargingTimeThreshold32;
* endcode
*
* param config Pointer to configuration structure. See to "dcdc_low_power_config_t"
*/
void DCDC_GetDefaultLowPowerConfig(dcdc_low_power_config_t *config)
{
assert(NULL != config);
/* Initializes the configure structure to zero. */
memset(config, 0, sizeof(*config));
config->enableOverloadDetection = true;
config->enableAdjustHystereticValue = false;
config->countChargingTimePeriod = kDCDC_CountChargingTimePeriod8Cycle;
config->countChargingTimeThreshold = kDCDC_CountChargingTimeThreshold32;
}
/*!
* brief Configure the DCDC low power.
*
* param base DCDC peripheral base address.
* param config Pointer to configuration structure. See to "dcdc_low_power_config_t".
*/
void DCDC_SetLowPowerConfig(DCDC_Type *base, const dcdc_low_power_config_t *config)
{
assert(NULL != config);
@ -185,6 +250,12 @@ void DCDC_SetLowPowerConfig(DCDC_Type *base, const dcdc_low_power_config_t *conf
base->REG0 = tmp32;
}
/*!
* brief Get DCDC status flags.
*
* param base peripheral base address.
* return Mask of asserted status flags. See to "_dcdc_status_flags_t".
*/
uint32_t DCDC_GetstatusFlags(DCDC_Type *base)
{
uint32_t tmp32 = 0U;
@ -197,6 +268,12 @@ uint32_t DCDC_GetstatusFlags(DCDC_Type *base)
return tmp32;
}
/*!
* brief Reset current alert signal. Alert signal is generate by peak current detection.
*
* param base DCDC peripheral base address.
* param enable Switcher to reset signal. True means reset signal. False means don't reset signal.
*/
void DCDC_ResetCurrentAlertSignal(DCDC_Type *base, bool enable)
{
if (enable)
@ -209,10 +286,31 @@ void DCDC_ResetCurrentAlertSignal(DCDC_Type *base, bool enable)
}
}
/*!
* brief Get the default setting for loop control configuration.
*
* The default configuration are set according to responding registers' setting when powered on.
* They are:
* code
* config->enableCommonHysteresis = false;
* config->enableCommonThresholdDetection = false;
* config->enableInvertHysteresisSign = false;
* config->enableRCThresholdDetection = false;
* config->enableRCScaleCircuit = 0U;
* config->complementFeedForwardStep = 0U;
* config->controlParameterMagnitude = 2U;
* config->integralProportionalRatio = 2U;
* endcode
*
* param config Pointer to configuration structure. See to "dcdc_loop_control_config_t"
*/
void DCDC_GetDefaultLoopControlConfig(dcdc_loop_control_config_t *config)
{
assert(NULL != config);
/* Initializes the configure structure to zero. */
memset(config, 0, sizeof(*config));
config->enableCommonHysteresis = false;
config->enableCommonThresholdDetection = false;
config->enableInvertHysteresisSign = false;
@ -223,6 +321,12 @@ void DCDC_GetDefaultLoopControlConfig(dcdc_loop_control_config_t *config)
config->integralProportionalRatio = 2U;
}
/*!
* brief Configure the DCDC loop control.
*
* param base DCDC peripheral base address.
* param config Pointer to configuration structure. See to "dcdc_loop_control_config_t".
*/
void DCDC_SetLoopControlConfig(DCDC_Type *base, const dcdc_loop_control_config_t *config)
{
assert(NULL != config);
@ -261,6 +365,12 @@ void DCDC_SetLoopControlConfig(DCDC_Type *base, const dcdc_loop_control_config_t
base->REG2 = tmp32;
}
/*!
* brief Configure for the min power.
*
* param base DCDC peripheral base address.
* param config Pointer to configuration structure. See to "dcdc_min_power_config_t".
*/
void DCDC_SetMinPowerConfig(DCDC_Type *base, const dcdc_min_power_config_t *config)
{
assert(NULL != config);
@ -275,6 +385,18 @@ void DCDC_SetMinPowerConfig(DCDC_Type *base, const dcdc_min_power_config_t *conf
base->REG3 = tmp32;
}
/*!
* brief Adjust the target voltage of VDD_SOC in run mode and low power mode.
*
* This function is to adjust the target voltage of DCDC output. Change them and finally wait until the output is
* stabled.
* Set the target value of run mode the same as low power mode before entering power save mode, because DCDC will switch
* back to run mode if it detects the current loading is larger than about 50 mA(typical value).
*
* param base DCDC peripheral base address.
* param VDDRun Target value in run mode. 25 mV each step from 0x00 to 0x1F. 00 is for 0.8V, 0x1F is for 1.575V.
* param VDDStandby Target value in low power mode. 25 mV each step from 0x00 to 0x4. 00 is for 0.9V, 0x4 is for 1.0V.
*/
void DCDC_AdjustTargetVoltage(DCDC_Type *base, uint32_t VDDRun, uint32_t VDDStandby)
{
uint32_t tmp32;
@ -295,6 +417,12 @@ void DCDC_AdjustTargetVoltage(DCDC_Type *base, uint32_t VDDRun, uint32_t VDDStan
}
}
/*!
* brief Configure the DCDC internal regulator.
*
* param base DCDC peripheral base address.
* param config Pointer to configuration structure. See to "dcdc_internal_regulator_config_t".
*/
void DCDC_SetInternalRegulatorConfig(DCDC_Type *base, const dcdc_internal_regulator_config_t *config)
{
assert(NULL != config);
@ -311,6 +439,16 @@ void DCDC_SetInternalRegulatorConfig(DCDC_Type *base, const dcdc_internal_regula
base->REG1 = tmp32;
}
/*!
* brief Boot DCDC into DCM(discontinous conduction mode).
*
* pwd_zcd=0x0;
* pwd_cmp_offset=0x0;
* dcdc_loopctrl_en_rcscale=0x3 or 0x5;
* DCM_set_ctrl=1'b1;
*
* param base DCDC peripheral base address.
*/
void DCDC_BootIntoDCM(DCDC_Type *base)
{
base->REG0 &= ~(DCDC_REG0_PWD_ZCD_MASK | DCDC_REG0_PWD_CMP_OFFSET_MASK);
@ -318,6 +456,15 @@ void DCDC_BootIntoDCM(DCDC_Type *base)
DCDC_REG2_DCM_SET_CTRL_MASK;
}
/*!
* brief Boot DCDC into CCM(continous conduction mode).
*
* pwd_zcd=0x1;
* pwd_cmp_offset=0x0;
* dcdc_loopctrl_en_rcscale=0x3;
*
* param base DCDC peripheral base address.
*/
void DCDC_BootIntoCCM(DCDC_Type *base)
{
base->REG0 = (~DCDC_REG0_PWD_CMP_OFFSET_MASK & base->REG0) | DCDC_REG0_PWD_ZCD_MASK;

239
ext/hal/nxp/mcux/drivers/imx/fsl_dcp.c
View file

@ -2,7 +2,7 @@
* Copyright 2017 NXP
* All rights reserved.
*
*
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -17,7 +17,6 @@
#define FSL_COMPONENT_ID "platform.drivers.dcp"
#endif
/*! Compile time sizeof() check */
#define BUILD_ASSURE(condition, msg) extern int msg[1 - 2 * (!(condition))] __attribute__((unused))
@ -260,6 +259,24 @@ static status_t dcp_schedule_work(DCP_Type *base, dcp_handle_t *handle, dcp_work
return status;
}
/*!
* brief Set AES key to dcp_handle_t struct and optionally to DCP.
*
* Sets the AES key for encryption/decryption with the dcp_handle_t structure.
* The dcp_handle_t input argument specifies keySlot.
* If the keySlot is kDCP_OtpKey, the function will check the OTP_KEY_READY bit and will return it's ready to use
* status.
* For other keySlot selections, the function will copy and hold the key in dcp_handle_t struct.
* If the keySlot is one of the four DCP SRAM-based keys (one of kDCP_KeySlot0, kDCP_KeySlot1, kDCP_KeySlot2,
* kDCP_KeySlot3),
* this function will also load the supplied key to the specified keySlot in DCP.
*
* param base DCP peripheral base address.
* param handle Handle used for the request.
* param key 0-mod-4 aligned pointer to AES key.
* param keySize AES key size in bytes. Shall equal 16.
* return status from set key operation
*/
status_t DCP_AES_SetKey(DCP_Type *base, dcp_handle_t *handle, const uint8_t *key, size_t keySize)
{
status_t status = kStatus_Fail;
@ -310,6 +327,19 @@ status_t DCP_AES_SetKey(DCP_Type *base, dcp_handle_t *handle, const uint8_t *key
return status;
}
/*!
* brief Encrypts AES on one or multiple 128-bit block(s).
*
* Encrypts AES.
* The source plaintext and destination ciphertext can overlap in system memory.
*
* param base DCP peripheral base address
* param handle Handle used for this request.
* param plaintext Input plain text to encrypt
* param[out] ciphertext Output cipher text
* param size Size of input and output data in bytes. Must be multiple of 16 bytes.
* return Status from encrypt operation
*/
status_t DCP_AES_EncryptEcb(
DCP_Type *base, dcp_handle_t *handle, const uint8_t *plaintext, uint8_t *ciphertext, size_t size)
{
@ -329,6 +359,20 @@ status_t DCP_AES_EncryptEcb(
return DCP_WaitForChannelComplete(base, handle);
}
/*!
* brief Encrypts AES using the ECB block mode.
*
* Puts AES ECB encrypt work packet to DCP channel.
*
* param base DCP peripheral base address
* param handle Handle used for this request.
* param[out] dcpPacket Memory for the DCP work packet.
* param plaintext Input plain text to encrypt.
* param[out] ciphertext Output cipher text
* param size Size of input and output data in bytes. Must be multiple of 16 bytes.
* return kStatus_Success The work packet has been scheduled at DCP channel.
* return kStatus_DCP_Again The DCP channel is busy processing previous request.
*/
status_t DCP_AES_EncryptEcbNonBlocking(DCP_Type *base,
dcp_handle_t *handle,
dcp_work_packet_t *dcpPacket,
@ -342,7 +386,8 @@ status_t DCP_AES_EncryptEcbNonBlocking(DCP_Type *base,
return kStatus_InvalidArgument;
}
dcpPacket->control0 = 0x122u | (handle->swapConfig & 0xFC0000u); /* CIPHER_ENCRYPT | ENABLE_CIPHER | DECR_SEMAPHORE */
dcpPacket->control0 =
0x122u | (handle->swapConfig & 0xFC0000u); /* CIPHER_ENCRYPT | ENABLE_CIPHER | DECR_SEMAPHORE */
dcpPacket->sourceBufferAddress = (uint32_t)plaintext;
dcpPacket->destinationBufferAddress = (uint32_t)ciphertext;
dcpPacket->bufferSize = (uint32_t)size;
@ -371,6 +416,19 @@ status_t DCP_AES_EncryptEcbNonBlocking(DCP_Type *base,
return dcp_schedule_work(base, handle, dcpPacket);
}
/*!
* brief Decrypts AES on one or multiple 128-bit block(s).
*
* Decrypts AES.
* The source ciphertext and destination plaintext can overlap in system memory.
*
* param base DCP peripheral base address
* param handle Handle used for this request.
* param ciphertext Input plain text to encrypt
* param[out] plaintext Output cipher text
* param size Size of input and output data in bytes. Must be multiple of 16 bytes.
* return Status from decrypt operation
*/
status_t DCP_AES_DecryptEcb(
DCP_Type *base, dcp_handle_t *handle, const uint8_t *ciphertext, uint8_t *plaintext, size_t size)
{
@ -390,6 +448,20 @@ status_t DCP_AES_DecryptEcb(
return DCP_WaitForChannelComplete(base, handle);
}
/*!
* brief Decrypts AES using ECB block mode.
*
* Puts AES ECB decrypt dcpPacket to DCP input job ring.
*
* param base DCP peripheral base address
* param handle Handle used for this request.
* param[out] dcpPacket Memory for the DCP work packet.
* param ciphertext Input cipher text to decrypt
* param[out] plaintext Output plain text
* param size Size of input and output data in bytes. Must be multiple of 16 bytes.
* return kStatus_Success The work packet has been scheduled at DCP channel.
* return kStatus_DCP_Again The DCP channel is busy processing previous request.
*/
status_t DCP_AES_DecryptEcbNonBlocking(DCP_Type *base,
dcp_handle_t *handle,
dcp_work_packet_t *dcpPacket,
@ -432,6 +504,20 @@ status_t DCP_AES_DecryptEcbNonBlocking(DCP_Type *base,
return dcp_schedule_work(base, handle, dcpPacket);
}
/*!
* brief Encrypts AES using CBC block mode.
*
* Encrypts AES using CBC block mode.
* The source plaintext and destination ciphertext can overlap in system memory.
*
* param base DCP peripheral base address
* param handle Handle used for this request.
* param plaintext Input plain text to encrypt
* param[out] ciphertext Output cipher text
* param size Size of input and output data in bytes. Must be multiple of 16 bytes.
* param iv Input initial vector to combine with the first input block.
* return Status from encrypt operation
*/
status_t DCP_AES_EncryptCbc(DCP_Type *base,
dcp_handle_t *handle,
const uint8_t *plaintext,
@ -455,6 +541,21 @@ status_t DCP_AES_EncryptCbc(DCP_Type *base,
return DCP_WaitForChannelComplete(base, handle);
}
/*!
* brief Encrypts AES using CBC block mode.
*
* Puts AES CBC encrypt dcpPacket to DCP input job ring.
*
* param base DCP peripheral base address
* param handle Handle used for this request. Specifies jobRing.
* param[out] dcpPacket Memory for the DCP work packet.
* param plaintext Input plain text to encrypt
* param[out] ciphertext Output cipher text
* param size Size of input and output data in bytes. Must be multiple of 16 bytes.
* param iv Input initial vector to combine with the first input block.
* return kStatus_Success The work packet has been scheduled at DCP channel.
* return kStatus_DCP_Again The DCP channel is busy processing previous request.
*/
status_t DCP_AES_EncryptCbcNonBlocking(DCP_Type *base,
dcp_handle_t *handle,
dcp_work_packet_t *dcpPacket,
@ -469,8 +570,9 @@ status_t DCP_AES_EncryptCbcNonBlocking(DCP_Type *base,
return kStatus_InvalidArgument;
}
dcpPacket->control0 = 0x322u | (handle->swapConfig & 0xFC0000u); /* CIPHER_INIT | CIPHER_ENCRYPT | ENABLE_CIPHER | DECR_SEMAPHORE */
dcpPacket->control1 = 0x10u; /* CBC */
dcpPacket->control0 =
0x322u | (handle->swapConfig & 0xFC0000u); /* CIPHER_INIT | CIPHER_ENCRYPT | ENABLE_CIPHER | DECR_SEMAPHORE */
dcpPacket->control1 = 0x10u; /* CBC */
dcpPacket->sourceBufferAddress = (uint32_t)plaintext;
dcpPacket->destinationBufferAddress = (uint32_t)ciphertext;
dcpPacket->bufferSize = (uint32_t)size;
@ -504,6 +606,20 @@ status_t DCP_AES_EncryptCbcNonBlocking(DCP_Type *base,
return dcp_schedule_work(base, handle, dcpPacket);
}
/*!
* brief Decrypts AES using CBC block mode.
*
* Decrypts AES using CBC block mode.
* The source ciphertext and destination plaintext can overlap in system memory.
*
* param base DCP peripheral base address
* param handle Handle used for this request.
* param ciphertext Input cipher text to decrypt
* param[out] plaintext Output plain text
* param size Size of input and output data in bytes. Must be multiple of 16 bytes.
* param iv Input initial vector to combine with the first input block.
* return Status from decrypt operation
*/
status_t DCP_AES_DecryptCbc(DCP_Type *base,
dcp_handle_t *handle,
const uint8_t *ciphertext,
@ -527,6 +643,21 @@ status_t DCP_AES_DecryptCbc(DCP_Type *base,
return DCP_WaitForChannelComplete(base, handle);
}
/*!
* brief Decrypts AES using CBC block mode.
*
* Puts AES CBC decrypt dcpPacket to DCP input job ring.
*
* param base DCP peripheral base address
* param handle Handle used for this request. Specifies jobRing.
* param[out] dcpPacket Memory for the DCP work packet.
* param ciphertext Input cipher text to decrypt
* param[out] plaintext Output plain text
* param size Size of input and output data in bytes. Must be multiple of 16 bytes.
* param iv Input initial vector to combine with the first input block.
* return kStatus_Success The work packet has been scheduled at DCP channel.
* return kStatus_DCP_Again The DCP channel is busy processing previous request.
*/
status_t DCP_AES_DecryptCbcNonBlocking(DCP_Type *base,
dcp_handle_t *handle,
dcp_work_packet_t *dcpPacket,
@ -542,7 +673,7 @@ status_t DCP_AES_DecryptCbcNonBlocking(DCP_Type *base,
}
dcpPacket->control0 = 0x222u | (handle->swapConfig & 0xFC0000u); /* CIPHER_INIT | ENABLE_CIPHER | DECR_SEMAPHORE */
dcpPacket->control1 = 0x10u; /* CBC */
dcpPacket->control1 = 0x10u; /* CBC */
dcpPacket->sourceBufferAddress = (uint32_t)ciphertext;
dcpPacket->destinationBufferAddress = (uint32_t)plaintext;
dcpPacket->bufferSize = (uint32_t)size;
@ -576,12 +707,29 @@ status_t DCP_AES_DecryptCbcNonBlocking(DCP_Type *base,
return dcp_schedule_work(base, handle, dcpPacket);
}
/*!
* brief Gets the default configuration structure.
*
* This function initializes the DCP configuration structure to a default value. The default
* values are as follows.
* dcpConfig->gatherResidualWrites = true;
* dcpConfig->enableContextCaching = true;
* dcpConfig->enableContextSwitching = true;
* dcpConfig->enableChannnel = kDCP_chEnableAll;
* dcpConfig->enableChannelInterrupt = kDCP_chIntDisable;
*
* param[out] config Pointer to configuration structure.
*/
void DCP_GetDefaultConfig(dcp_config_t *config)
{
/* ENABLE_CONTEXT_CACHING is disabled by default as the DCP Hash driver uses
* dcp_hash_save_running_hash() and dcp_hash_restore_running_hash() to support
* Hash context switch (different messages interleaved) on the same channel.
*/
/* Initializes the configure structure to zero. */
memset(config, 0, sizeof(*config));
dcp_config_t userConfig = {
true, false, true, kDCP_chEnableAll, kDCP_chIntDisable,
};
@ -589,6 +737,14 @@ void DCP_GetDefaultConfig(dcp_config_t *config)
*config = userConfig;
}
/*!
* brief Enables clock to and enables DCP
*
* Enable DCP clock and configure DCP.
*
* param base DCP base address
* param config Pointer to configuration structure.
*/
void DCP_Init(DCP_Type *base, const dcp_config_t *config)
{
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
@ -613,6 +769,13 @@ void DCP_Init(DCP_Type *base, const dcp_config_t *config)
base->CONTEXT = (uint32_t)&s_dcpContextSwitchingBuffer;
}
/*!
* brief Disable DCP clock
*
* Reset DCP and Disable DCP clock.
*
* param base DCP base address
*/
void DCP_Deinit(DCP_Type *base)
{
base->CTRL = 0xF0800000u; /* reset value */
@ -623,6 +786,16 @@ void DCP_Deinit(DCP_Type *base)
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
}
/*!
* brief Poll and wait on DCP channel.
*
* Polls the specified DCP channel until current it completes activity.
*
* param base DCP peripheral base address.
* param handle Specifies DCP channel.
* return kStatus_Success When data processing completes without error.
* return kStatus_Fail When error occurs.
*/
status_t DCP_WaitForChannelComplete(DCP_Type *base, dcp_handle_t *handle)
{
/* wait if our channel is still active */
@ -728,7 +901,8 @@ static status_t dcp_hash_engine_init(DCP_Type *base, dcp_hash_ctx_internal_t *ct
static status_t dcp_hash_update_non_blocking(
DCP_Type *base, dcp_hash_ctx_internal_t *ctxInternal, dcp_work_packet_t *dcpPacket, const uint8_t *msg, size_t size)
{
dcpPacket->control0 = ctxInternal->ctrl0 | (ctxInternal->handle->swapConfig & 0xFC0000u) | kDCP_CONTROL0_ENABLE_HASH | kDCP_CONTROL0_DECR_SEMAPHOR;
dcpPacket->control0 = ctxInternal->ctrl0 | (ctxInternal->handle->swapConfig & 0xFC0000u) |
kDCP_CONTROL0_ENABLE_HASH | kDCP_CONTROL0_DECR_SEMAPHOR;
if (ctxInternal->algo == kDCP_Sha256)
{
dcpPacket->control1 = kDCP_CONTROL1_HASH_SELECT_SHA256;
@ -906,6 +1080,17 @@ static void dcp_hash_restore_running_hash(dcp_hash_ctx_internal_t *ctxInternal)
}
}
/*!
* brief Initialize HASH context
*
* This function initializes the HASH.
*
* param base DCP peripheral base address
* param handle Specifies the DCP channel used for hashing.
* param[out] ctx Output hash context
* param algo Underlaying algorithm to use for hash computation.
* return Status of initialization
*/
status_t DCP_HASH_Init(DCP_Type *base, dcp_handle_t *handle, dcp_hash_ctx_t *ctx, dcp_hash_algo_t algo)
{
status_t status;
@ -935,6 +1120,21 @@ status_t DCP_HASH_Init(DCP_Type *base, dcp_handle_t *handle, dcp_hash_ctx_t *ctx
return status;
}
/*!
* brief Add data to current HASH
*
* Add data to current HASH. This can be called repeatedly with an arbitrary amount of data to be
* hashed. The functions blocks. If it returns kStatus_Success, the running hash
* has been updated (DCP has processed the input data), so the memory at ref input pointer
* can be released back to system. The DCP context buffer is updated with the running hash
* and with all necessary information to support possible context switch.
*
* param base DCP peripheral base address
* param[in,out] ctx HASH context
* param input Input data
* param inputSize Size of input data in bytes
* return Status of the hash update operation
*/
status_t DCP_HASH_Update(DCP_Type *base, dcp_hash_ctx_t *ctx, const uint8_t *input, size_t inputSize)
{
bool isUpdateState;
@ -988,6 +1188,17 @@ status_t DCP_HASH_Update(DCP_Type *base, dcp_hash_ctx_t *ctx, const uint8_t *inp
return status;
}
/*!
* brief Finalize hashing
*
* Outputs the final hash (computed by DCP_HASH_Update()) and erases the context.
*
* param[in,out] ctx Input hash context
* param[out] output Output hash data
* param[in,out] outputSize Optional parameter (can be passed as NULL). On function entry, it specifies the size of
* output[] buffer. On function return, it stores the number of updated output bytes.
* return Status of the hash finish operation
*/
status_t DCP_HASH_Finish(DCP_Type *base, dcp_hash_ctx_t *ctx, uint8_t *output, size_t *outputSize)
{
size_t algOutSize = 0;
@ -1074,6 +1285,20 @@ status_t DCP_HASH_Finish(DCP_Type *base, dcp_hash_ctx_t *ctx, uint8_t *output, s
return status;
}
/*!
* brief Create HASH on given data
*
* Perform the full SHA or CRC32 in one function call. The function is blocking.
*
* param base DCP peripheral base address
* param handle Handle used for the request.
* param algo Underlaying algorithm to use for hash computation.
* param input Input data
* param inputSize Size of input data in bytes
* param[out] output Output hash data
* param[out] outputSize Output parameter storing the size of the output hash in bytes
* return Status of the one call hash operation.
*/
status_t DCP_HASH(DCP_Type *base,
dcp_handle_t *handle,
dcp_hash_algo_t algo,

9
ext/hal/nxp/mcux/drivers/imx/fsl_dcp.h
View file

@ -27,15 +27,18 @@ enum _dcp_status
*/
/*! @name Driver version */
/*@{*/
/*! @brief DCP driver version. Version 2.0.0.
/*! @brief DCP driver version. Version 2.1.0.
*
* Current version: 2.0.0
* Current version: 2.1.0
*
* Change log:
* - Version 2.1.0
* - Add byte/word swap feature for key, input and output data
*
* - Version 2.0.0
* - Initial version
*/
#define FSL_DCP_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
#define FSL_DCP_DRIVER_VERSION (MAKE_VERSION(2, 1, 0))
/*@}*/
/*! @brief DCP channel enable.

18
ext/hal/nxp/mcux/drivers/imx/fsl_dmamux.c
View file

@ -2,7 +2,7 @@
* Copyright (c) 2015, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
* All rights reserved.
*
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -17,7 +17,6 @@
#define FSL_COMPONENT_ID "platform.drivers.dmamux"
#endif
/*******************************************************************************
* Prototypes
******************************************************************************/
@ -62,6 +61,14 @@ static uint32_t DMAMUX_GetInstance(DMAMUX_Type *base)
return instance;
}
/*!
* brief Initializes the DMAMUX peripheral.
*
* This function ungates the DMAMUX clock.
*
* param base DMAMUX peripheral base address.
*
*/
void DMAMUX_Init(DMAMUX_Type *base)
{
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
@ -69,6 +76,13 @@ void DMAMUX_Init(DMAMUX_Type *base)
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
}
/*!
* brief Deinitializes the DMAMUX peripheral.
*
* This function gates the DMAMUX clock.
*
* param base DMAMUX peripheral base address.
*/
void DMAMUX_Deinit(DMAMUX_Type *base)
{
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)

391
ext/hal/nxp/mcux/drivers/imx/fsl_edma.c
View file

@ -1,6 +1,6 @@
/*
* Copyright (c) 2015, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
* Copyright 2016-2018 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
@ -70,6 +70,13 @@ static uint32_t EDMA_GetInstance(DMA_Type *base)
return instance;
}
/*!
* brief Push content of TCD structure into hardware TCD register.
*
* param base EDMA peripheral base address.
* param channel EDMA channel number.
* param tcd Point to TCD structure.
*/
void EDMA_InstallTCD(DMA_Type *base, uint32_t channel, edma_tcd_t *tcd)
{
assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL);
@ -92,6 +99,16 @@ void EDMA_InstallTCD(DMA_Type *base, uint32_t channel, edma_tcd_t *tcd)
base->TCD[channel].BITER_ELINKNO = tcd->BITER;
}
/*!
* brief Initializes the eDMA peripheral.
*
* This function ungates the eDMA clock and configures the eDMA peripheral according
* to the configuration structure.
*
* param base eDMA peripheral base address.
* param config A pointer to the configuration structure, see "edma_config_t".
* note This function enables the minor loop map feature.
*/
void EDMA_Init(DMA_Type *base, const edma_config_t *config)
{
assert(config != NULL);
@ -102,6 +119,11 @@ void EDMA_Init(DMA_Type *base, const edma_config_t *config)
/* Ungate EDMA peripheral clock */
CLOCK_EnableClock(s_edmaClockName[EDMA_GetInstance(base)]);
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
/* clear all the enabled request, status to make sure EDMA status is in normal condition */
base->ERQ = 0U;
base->INT = 0xFFFFFFFFU;
base->ERR = 0xFFFFFFFFU;
/* Configure EDMA peripheral according to the configuration structure. */
tmpreg = base->CR;
tmpreg &= ~(DMA_CR_ERCA_MASK | DMA_CR_HOE_MASK | DMA_CR_CLM_MASK | DMA_CR_EDBG_MASK);
@ -110,6 +132,13 @@ void EDMA_Init(DMA_Type *base, const edma_config_t *config)
base->CR = tmpreg;
}
/*!
* brief Deinitializes the eDMA peripheral.
*
* This function gates the eDMA clock.
*
* param base eDMA peripheral base address.
*/
void EDMA_Deinit(DMA_Type *base)
{
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
@ -118,16 +147,44 @@ void EDMA_Deinit(DMA_Type *base)
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
}
/*!
* brief Gets the eDMA default configuration structure.
*
* This function sets the configuration structure to default values.
* The default configuration is set to the following values.
* code
* config.enableContinuousLinkMode = false;
* config.enableHaltOnError = true;
* config.enableRoundRobinArbitration = false;
* config.enableDebugMode = false;
* endcode
*
* param config A pointer to the eDMA configuration structure.
*/
void EDMA_GetDefaultConfig(edma_config_t *config)
{
assert(config != NULL);
/* Initializes the configure structure to zero. */
memset(config, 0, sizeof(*config));
config->enableRoundRobinArbitration = false;
config->enableHaltOnError = true;
config->enableContinuousLinkMode = false;
config->enableDebugMode = false;
}
/*!
* brief Sets all TCD registers to default values.
*
* This function sets TCD registers for this channel to default values.
*
* param base eDMA peripheral base address.
* param channel eDMA channel number.
* note This function must not be called while the channel transfer is ongoing
* or it causes unpredictable results.
* note This function enables the auto stop request feature.
*/
void EDMA_ResetChannel(DMA_Type *base, uint32_t channel)
{
assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL);
@ -135,6 +192,31 @@ void EDMA_ResetChannel(DMA_Type *base, uint32_t channel)
EDMA_TcdReset((edma_tcd_t *)&base->TCD[channel]);
}
/*!
* brief Configures the eDMA transfer attribute.
*
* This function configures the transfer attribute, including source address, destination address,
* transfer size, address offset, and so on. It also configures the scatter gather feature if the
* user supplies the TCD address.
* Example:
* code
* edma_transfer_t config;
* edma_tcd_t tcd;
* config.srcAddr = ..;
* config.destAddr = ..;
* ...
* EDMA_SetTransferConfig(DMA0, channel, &config, &stcd);
* endcode
*
* param base eDMA peripheral base address.
* param channel eDMA channel number.
* param config Pointer to eDMA transfer configuration structure.
* param nextTcd Point to TCD structure. It can be NULL if users
* do not want to enable scatter/gather feature.
* note If nextTcd is not NULL, it means scatter gather feature is enabled
* and DREQ bit is cleared in the previous transfer configuration, which
* is set in the eDMA_ResetChannel.
*/
void EDMA_SetTransferConfig(DMA_Type *base, uint32_t channel, const edma_transfer_config_t *config, edma_tcd_t *nextTcd)
{
assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL);
@ -144,6 +226,16 @@ void EDMA_SetTransferConfig(DMA_Type *base, uint32_t channel, const edma_transfe
EDMA_TcdSetTransferConfig((edma_tcd_t *)&base->TCD[channel], config, nextTcd);
}
/*!
* brief Configures the eDMA minor offset feature.
*
* The minor offset means that the signed-extended value is added to the source address or destination
* address after each minor loop.
*
* param base eDMA peripheral base address.
* param channel eDMA channel number.
* param config A pointer to the minor offset configuration structure.
*/
void EDMA_SetMinorOffsetConfig(DMA_Type *base, uint32_t channel, const edma_minor_offset_config_t *config)
{
assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL);
@ -159,6 +251,22 @@ void EDMA_SetMinorOffsetConfig(DMA_Type *base, uint32_t channel, const edma_mino
base->TCD[channel].NBYTES_MLOFFYES = tmpreg;
}
/*!
* brief Sets the channel link for the eDMA transfer.
*
* This function configures either the minor link or the major link mode. The minor link means that the channel link is
* triggered every time CITER decreases by 1. The major link means that the channel link is triggered when the CITER is
* exhausted.
*
* param base eDMA peripheral base address.
* param channel eDMA channel number.
* param type A channel link type, which can be one of the following:
* arg kEDMA_LinkNone
* arg kEDMA_MinorLink
* arg kEDMA_MajorLink
* param linkedChannel The linked channel number.
* note Users should ensure that DONE flag is cleared before calling this interface, or the configuration is invalid.
*/
void EDMA_SetChannelLink(DMA_Type *base, uint32_t channel, edma_channel_link_type_t type, uint32_t linkedChannel)
{
assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL);
@ -167,6 +275,20 @@ void EDMA_SetChannelLink(DMA_Type *base, uint32_t channel, edma_channel_link_typ
EDMA_TcdSetChannelLink((edma_tcd_t *)&base->TCD[channel], type, linkedChannel);
}
/*!
* brief Sets the bandwidth for the eDMA transfer.
*
* Because the eDMA processes the minor loop, it continuously generates read/write sequences
* until the minor count is exhausted. The bandwidth forces the eDMA to stall after the completion of
* each read/write access to control the bus request bandwidth seen by the crossbar switch.
*
* param base eDMA peripheral base address.
* param channel eDMA channel number.
* param bandWidth A bandwidth setting, which can be one of the following:
* arg kEDMABandwidthStallNone
* arg kEDMABandwidthStall4Cycle
* arg kEDMABandwidthStall8Cycle
*/
void EDMA_SetBandWidth(DMA_Type *base, uint32_t channel, edma_bandwidth_t bandWidth)
{
assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL);
@ -174,6 +296,18 @@ void EDMA_SetBandWidth(DMA_Type *base, uint32_t channel, edma_bandwidth_t bandWi
base->TCD[channel].CSR = (base->TCD[channel].CSR & (~DMA_CSR_BWC_MASK)) | DMA_CSR_BWC(bandWidth);
}
/*!
* brief Sets the source modulo and the destination modulo for the eDMA transfer.
*
* This function defines a specific address range specified to be the value after (SADDR + SOFF)/(DADDR + DOFF)
* calculation is performed or the original register value. It provides the ability to implement a circular data
* queue easily.
*
* param base eDMA peripheral base address.
* param channel eDMA channel number.
* param srcModulo A source modulo value.
* param destModulo A destination modulo value.
*/
void EDMA_SetModulo(DMA_Type *base, uint32_t channel, edma_modulo_t srcModulo, edma_modulo_t destModulo)
{
assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL);
@ -184,6 +318,14 @@ void EDMA_SetModulo(DMA_Type *base, uint32_t channel, edma_modulo_t srcModulo, e
base->TCD[channel].ATTR = tmpreg | DMA_ATTR_DMOD(destModulo) | DMA_ATTR_SMOD(srcModulo);
}
/*!
* brief Enables the interrupt source for the eDMA transfer.
*
* param base eDMA peripheral base address.
* param channel eDMA channel number.
* param mask The mask of interrupt source to be set. Users need to use
* the defined edma_interrupt_enable_t type.
*/
void EDMA_EnableChannelInterrupts(DMA_Type *base, uint32_t channel, uint32_t mask)
{
assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL);
@ -207,6 +349,14 @@ void EDMA_EnableChannelInterrupts(DMA_Type *base, uint32_t channel, uint32_t mas
}
}
/*!
* brief Disables the interrupt source for the eDMA transfer.
*
* param base eDMA peripheral base address.
* param channel eDMA channel number.
* param mask The mask of the interrupt source to be set. Use
* the defined edma_interrupt_enable_t type.
*/
void EDMA_DisableChannelInterrupts(DMA_Type *base, uint32_t channel, uint32_t mask)
{
assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL);
@ -230,6 +380,14 @@ void EDMA_DisableChannelInterrupts(DMA_Type *base, uint32_t channel, uint32_t ma
}
}
/*!
* brief Sets all fields to default values for the TCD structure.
*
* This function sets all fields for this TCD structure to default value.
*
* param tcd Pointer to the TCD structure.
* note This function enables the auto stop request feature.
*/
void EDMA_TcdReset(edma_tcd_t *tcd)
{
assert(tcd != NULL);
@ -250,6 +408,33 @@ void EDMA_TcdReset(edma_tcd_t *tcd)
tcd->BITER = 0U;
}
/*!
* brief Configures the eDMA TCD transfer attribute.
*
* The TCD is a transfer control descriptor. The content of the TCD is the same as the hardware TCD registers.
* The STCD is used in the scatter-gather mode.
* This function configures the TCD transfer attribute, including source address, destination address,
* transfer size, address offset, and so on. It also configures the scatter gather feature if the
* user supplies the next TCD address.
* Example:
* code
* edma_transfer_t config = {
* ...
* }
* edma_tcd_t tcd __aligned(32);
* edma_tcd_t nextTcd __aligned(32);
* EDMA_TcdSetTransferConfig(&tcd, &config, &nextTcd);
* endcode
*
* param tcd Pointer to the TCD structure.
* param config Pointer to eDMA transfer configuration structure.
* param nextTcd Pointer to the next TCD structure. It can be NULL if users
* do not want to enable scatter/gather feature.
* note TCD address should be 32 bytes aligned or it causes an eDMA error.
* note If the nextTcd is not NULL, the scatter gather feature is enabled
* and DREQ bit is cleared in the previous transfer configuration, which
* is set in the EDMA_TcdReset.
*/
void EDMA_TcdSetTransferConfig(edma_tcd_t *tcd, const edma_transfer_config_t *config, edma_tcd_t *nextTcd)
{
assert(tcd != NULL);
@ -290,6 +475,15 @@ void EDMA_TcdSetTransferConfig(edma_tcd_t *tcd, const edma_transfer_config_t *co
}
}
/*!
* brief Configures the eDMA TCD minor offset feature.
*
* A minor offset is a signed-extended value added to the source address or a destination
* address after each minor loop.
*
* param tcd A point to the TCD structure.
* param config A pointer to the minor offset configuration structure.
*/
void EDMA_TcdSetMinorOffsetConfig(edma_tcd_t *tcd, const edma_minor_offset_config_t *config)
{
assert(tcd != NULL);
@ -305,6 +499,21 @@ void EDMA_TcdSetMinorOffsetConfig(edma_tcd_t *tcd, const edma_minor_offset_confi
tcd->NBYTES = tmpreg;
}
/*!
* brief Sets the channel link for the eDMA TCD.
*
* This function configures either a minor link or a major link. The minor link means the channel link is
* triggered every time CITER decreases by 1. The major link means that the channel link is triggered when the CITER is
* exhausted.
*
* note Users should ensure that DONE flag is cleared before calling this interface, or the configuration is invalid.
* param tcd Point to the TCD structure.
* param type Channel link type, it can be one of:
* arg kEDMA_LinkNone
* arg kEDMA_MinorLink
* arg kEDMA_MajorLink
* param linkedChannel The linked channel number.
*/
void EDMA_TcdSetChannelLink(edma_tcd_t *tcd, edma_channel_link_type_t type, uint32_t linkedChannel)
{
assert(tcd != NULL);
@ -344,6 +553,17 @@ void EDMA_TcdSetChannelLink(edma_tcd_t *tcd, edma_channel_link_type_t type, uint
}
}
/*!
* brief Sets the source modulo and the destination modulo for the eDMA TCD.
*
* This function defines a specific address range specified to be the value after (SADDR + SOFF)/(DADDR + DOFF)
* calculation is performed or the original register value. It provides the ability to implement a circular data
* queue easily.
*
* param tcd A pointer to the TCD structure.
* param srcModulo A source modulo value.
* param destModulo A destination modulo value.
*/
void EDMA_TcdSetModulo(edma_tcd_t *tcd, edma_modulo_t srcModulo, edma_modulo_t destModulo)
{
assert(tcd != NULL);
@ -355,6 +575,13 @@ void EDMA_TcdSetModulo(edma_tcd_t *tcd, edma_modulo_t srcModulo, edma_modulo_t d
tcd->ATTR = tmpreg | DMA_ATTR_DMOD(destModulo) | DMA_ATTR_SMOD(srcModulo);
}
/*!
* brief Enables the interrupt source for the eDMA TCD.
*
* param tcd Point to the TCD structure.
* param mask The mask of interrupt source to be set. Users need to use
* the defined edma_interrupt_enable_t type.
*/
void EDMA_TcdEnableInterrupts(edma_tcd_t *tcd, uint32_t mask)
{
assert(tcd != NULL);
@ -372,6 +599,13 @@ void EDMA_TcdEnableInterrupts(edma_tcd_t *tcd, uint32_t mask)
}
}
/*!
* brief Disables the interrupt source for the eDMA TCD.
*
* param tcd Point to the TCD structure.
* param mask The mask of interrupt source to be set. Users need to use
* the defined edma_interrupt_enable_t type.
*/
void EDMA_TcdDisableInterrupts(edma_tcd_t *tcd, uint32_t mask)
{
assert(tcd != NULL);
@ -389,6 +623,27 @@ void EDMA_TcdDisableInterrupts(edma_tcd_t *tcd, uint32_t mask)
}
}
/*!
* brief Gets the remaining major loop count from the eDMA current channel TCD.
*
* This function checks the TCD (Task Control Descriptor) status for a specified
* eDMA channel and returns the number of major loop count that has not finished.
*
* param base eDMA peripheral base address.
* param channel eDMA channel number.
* return Major loop count which has not been transferred yet for the current TCD.
* note 1. This function can only be used to get unfinished major loop count of transfer without
* the next TCD, or it might be inaccuracy.
* 2. The unfinished/remaining transfer bytes cannot be obtained directly from registers while
* the channel is running.
* Because to calculate the remaining bytes, the initial NBYTES configured in DMA_TCDn_NBYTES_MLNO
* register is needed while the eDMA IP does not support getting it while a channel is active.
* In another word, the NBYTES value reading is always the actual (decrementing) NBYTES value the dma_engine
* is working with while a channel is running.
* Consequently, to get the remaining transfer bytes, a software-saved initial value of NBYTES (for example
* copied before enabling the channel) is needed. The formula to calculate it is shown below:
* RemainingBytes = RemainingMajorLoopCount * NBYTES(initially configured)
*/
uint32_t EDMA_GetRemainingMajorLoopCount(DMA_Type *base, uint32_t channel)
{
assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL);
@ -417,6 +672,14 @@ uint32_t EDMA_GetRemainingMajorLoopCount(DMA_Type *base, uint32_t channel)
return remainingCount;
}
/*!
* brief Gets the eDMA channel status flags.
*
* param base eDMA peripheral base address.
* param channel eDMA channel number.
* return The mask of channel status flags. Users need to use the
* _edma_channel_status_flags type to decode the return variables.
*/
uint32_t EDMA_GetChannelStatusFlags(DMA_Type *base, uint32_t channel)
{
assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL);
@ -433,6 +696,14 @@ uint32_t EDMA_GetChannelStatusFlags(DMA_Type *base, uint32_t channel)
return retval;
}
/*!
* brief Clears the eDMA channel status flags.
*
* param base eDMA peripheral base address.
* param channel eDMA channel number.
* param mask The mask of channel status to be cleared. Users need to use
* the defined _edma_channel_status_flags type.
*/
void EDMA_ClearChannelStatusFlags(DMA_Type *base, uint32_t channel, uint32_t mask)
{
assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL);
@ -471,6 +742,17 @@ static uint8_t Get_StartInstance(void)
return StartInstanceNum;
}
/*!
* brief Creates the eDMA handle.
*
* This function is called if using the transactional API for eDMA. This function
* initializes the internal state of the eDMA handle.
*
* param handle eDMA handle pointer. The eDMA handle stores callback function and
* parameters.
* param base eDMA peripheral base address.
* param channel eDMA channel number.
*/
void EDMA_CreateHandle(edma_handle_t *handle, DMA_Type *base, uint32_t channel)
{
assert(handle != NULL);
@ -514,6 +796,18 @@ void EDMA_CreateHandle(edma_handle_t *handle, DMA_Type *base, uint32_t channel)
tcdRegs->BITER = 0;
}
/*!
* brief Installs the TCDs memory pool into the eDMA handle.
*
* This function is called after the EDMA_CreateHandle to use scatter/gather feature. This function shall only be used
* while users need to use scatter gather mode. Scatter gather mode enables EDMA to load a new transfer control block
* (tcd) in hardware, and automatically reconfigure that DMA channel for a new transfer.
* Users need to prepare tcd memory and also configure tcds using interface EDMA_SubmitTransfer.
*
* param handle eDMA handle pointer.
* param tcdPool A memory pool to store TCDs. It must be 32 bytes aligned.
* param tcdSize The number of TCD slots.
*/
void EDMA_InstallTCDMemory(edma_handle_t *handle, edma_tcd_t *tcdPool, uint32_t tcdSize)
{
assert(handle != NULL);
@ -528,6 +822,16 @@ void EDMA_InstallTCDMemory(edma_handle_t *handle, edma_tcd_t *tcdPool, uint32_t
handle->tcdPool = tcdPool;
}
/*!
* brief Installs a callback function for the eDMA transfer.
*
* This callback is called in the eDMA IRQ handler. Use the callback to do something after
* the current major loop transfer completes. This function will be called every time one tcd finished transfer.
*
* param handle eDMA handle pointer.
* param callback eDMA callback function pointer.
* param userData A parameter for the callback function.
*/
void EDMA_SetCallback(edma_handle_t *handle, edma_callback callback, void *userData)
{
assert(handle != NULL);
@ -536,6 +840,23 @@ void EDMA_SetCallback(edma_handle_t *handle, edma_callback callback, void *userD
handle->userData = userData;
}
/*!
* brief Prepares the eDMA transfer structure.
*
* This function prepares the transfer configuration structure according to the user input.
*
* param config The user configuration structure of type edma_transfer_t.
* param srcAddr eDMA transfer source address.
* param srcWidth eDMA transfer source address width(bytes).
* param destAddr eDMA transfer destination address.
* param destWidth eDMA transfer destination address width(bytes).
* param bytesEachRequest eDMA transfer bytes per channel request.
* param transferBytes eDMA transfer bytes to be transferred.
* param type eDMA transfer type.
* note The data address and the data width must be consistent. For example, if the SRC
* is 4 bytes, the source address must be 4 bytes aligned, or it results in
* source address error (SAE).
*/
void EDMA_PrepareTransfer(edma_transfer_config_t *config,
void *srcAddr,
uint32_t srcWidth,
@ -552,6 +873,9 @@ void EDMA_PrepareTransfer(edma_transfer_config_t *config,
assert((destWidth == 1U) || (destWidth == 2U) || (destWidth == 4U) || (destWidth == 16U) || (destWidth == 32U));
assert(transferBytes % bytesEachRequest == 0);
/* Initializes the configure structure to zero. */
memset(config, 0, sizeof(*config));
config->destAddr = (uint32_t)destAddr;
config->srcAddr = (uint32_t)srcAddr;
config->minorLoopBytes = bytesEachRequest;
@ -615,6 +939,19 @@ void EDMA_PrepareTransfer(edma_transfer_config_t *config,
}
}
/*!
* brief Submits the eDMA transfer request.
*
* This function submits the eDMA transfer request according to the transfer configuration structure.
* In scatter gather mode, call this function will add a configured tcd to the circular list of tcd pool.
* The tcd pools is setup by call function EDMA_InstallTCDMemory before.
*
* param handle eDMA handle pointer.
* param config Pointer to eDMA transfer configuration structure.
* retval kStatus_EDMA_Success It means submit transfer request succeed.
* retval kStatus_EDMA_QueueFull It means TCD queue is full. Submit transfer request is not allowed.
* retval kStatus_EDMA_Busy It means the given channel is busy, need to submit request later.
*/
status_t EDMA_SubmitTransfer(edma_handle_t *handle, const edma_transfer_config_t *config)
{
assert(handle != NULL);
@ -754,6 +1091,14 @@ status_t EDMA_SubmitTransfer(edma_handle_t *handle, const edma_transfer_config_t
}
}
/*!
* brief eDMA starts transfer.
*
* This function enables the channel request. Users can call this function after submitting the transfer request
* or before submitting the transfer request.
*
* param handle eDMA handle pointer.
*/
void EDMA_StartTransfer(edma_handle_t *handle)
{
assert(handle != NULL);
@ -791,6 +1136,14 @@ void EDMA_StartTransfer(edma_handle_t *handle)
}
}
/*!
* brief eDMA stops transfer.
*
* This function disables the channel request to pause the transfer. Users can call EDMA_StartTransfer()
* again to resume the transfer.
*
* param handle eDMA handle pointer.
*/
void EDMA_StopTransfer(edma_handle_t *handle)
{
assert(handle != NULL);
@ -799,6 +1152,14 @@ void EDMA_StopTransfer(edma_handle_t *handle)
handle->base->CERQ = DMA_CERQ_CERQ(handle->channel);
}
/*!
* brief eDMA aborts transfer.
*
* This function disables the channel request and clear transfer status bits.
* Users can submit another transfer after calling this API.
*
* param handle DMA handle pointer.
*/
void EDMA_AbortTransfer(edma_handle_t *handle)
{
handle->base->CERQ = DMA_CERQ_CERQ(handle->channel);
@ -820,6 +1181,34 @@ void EDMA_AbortTransfer(edma_handle_t *handle)
}
}
/*!
* brief eDMA IRQ handler for the current major loop transfer completion.
*
* This function clears the channel major interrupt flag and calls
* the callback function if it is not NULL.
*
* Note:
* For the case using TCD queue, when the major iteration count is exhausted, additional operations are performed.
* These include the final address adjustments and reloading of the BITER field into the CITER.
* Assertion of an optional interrupt request also occurs at this time, as does a possible fetch of a new TCD from
* memory using the scatter/gather address pointer included in the descriptor (if scatter/gather is enabled).
*
* For instance, when the time interrupt of TCD[0] happens, the TCD[1] has already been loaded into the eDMA engine.
* As sga and sga_index are calculated based on the DLAST_SGA bitfield lies in the TCD_CSR register, the sga_index
* in this case should be 2 (DLAST_SGA of TCD[1] stores the address of TCD[2]). Thus, the "tcdUsed" updated should be
* (tcdUsed - 2U) which indicates the number of TCDs can be loaded in the memory pool (because TCD[0] and TCD[1] have
* been loaded into the eDMA engine at this point already.).
*
* For the last two continuous ISRs in a scatter/gather process, they both load the last TCD (The last ISR does not
* load a new TCD) from the memory pool to the eDMA engine when major loop completes.
* Therefore, ensure that the header and tcdUsed updated are identical for them.
* tcdUsed are both 0 in this case as no TCD to be loaded.
*
* See the "eDMA basic data flow" in the eDMA Functional description section of the Reference Manual for
* further details.
*
* param handle eDMA handle pointer.
*/
void EDMA_HandleIRQ(edma_handle_t *handle)
{
assert(handle != NULL);

6
ext/hal/nxp/mcux/drivers/imx/fsl_edma.h
View file

@ -1,6 +1,6 @@
/*
* Copyright (c) 2015, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
* Copyright 2016-2018 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
@ -23,7 +23,7 @@
/*! @name Driver version */
/*@{*/
/*! @brief eDMA driver version */
#define FSL_EDMA_DRIVER_VERSION (MAKE_VERSION(2, 1, 3)) /*!< Version 2.1.3. */
#define FSL_EDMA_DRIVER_VERSION (MAKE_VERSION(2, 1, 4)) /*!< Version 2.1.4. */
/*@}*/
/*! @brief Compute the offset unit from DCHPRI3 */
@ -121,7 +121,7 @@ enum _edma_error_status_flags
#if defined(FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT) && FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT > 1
kEDMA_GroupPriorityErrorFlag = DMA_ES_GPE_MASK, /*!< Group priority is not unique. */
#endif
kEDMA_ValidFlag = DMA_ES_VLD_MASK, /*!< No error occurred, this bit is 0. Otherwise, it is 1. */
kEDMA_ValidFlag = (int)DMA_ES_VLD_MASK, /*!< No error occurred, this bit is 0. Otherwise, it is 1. */
};
/*! @brief eDMA interrupt source */

81
ext/hal/nxp/mcux/drivers/imx/fsl_elcdif.c
View file

@ -2,7 +2,7 @@
* Copyright (c) 2017, NXP Semiconductors, Inc.
* All rights reserved.
*
*
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -13,7 +13,6 @@
#define FSL_COMPONENT_ID "platform.drivers.elcdif"
#endif
/*******************************************************************************
* Prototypes
******************************************************************************/
@ -91,6 +90,15 @@ static uint32_t ELCDIF_GetInstance(LCDIF_Type *base)
return instance;
}
/*!
* brief Initializes the eLCDIF to work in RGB mode (DOTCLK mode).
*
* This function ungates the eLCDIF clock and configures the eLCDIF peripheral according
* to the configuration structure.
*
* param base eLCDIF peripheral base address.
* param config Pointer to the configuration structure.
*/
void ELCDIF_RgbModeInit(LCDIF_Type *base, const elcdif_rgb_mode_config_t *config)
{
assert(config);
@ -138,10 +146,38 @@ void ELCDIF_RgbModeInit(LCDIF_Type *base, const elcdif_rgb_mode_config_t *config
base->NEXT_BUF = config->bufferAddr;
}
/*!
* brief Gets the eLCDIF default configuration structure for RGB (DOTCLK) mode.
*
* This function sets the configuration structure to default values.
* The default configuration is set to the following values.
* code
config->panelWidth = 480U;
config->panelHeight = 272U;
config->hsw = 41;
config->hfp = 4;
config->hbp = 8;
config->vsw = 10;
config->vfp = 4;
config->vbp = 2;
config->polarityFlags = kELCDIF_VsyncActiveLow |
kELCDIF_HsyncActiveLow |
kELCDIF_DataEnableActiveLow |
kELCDIF_DriveDataOnFallingClkEdge;
config->bufferAddr = 0U;
config->pixelFormat = kELCDIF_PixelFormatRGB888;
config->dataBus = kELCDIF_DataBus24Bit;
code
*
* param config Pointer to the eLCDIF configuration structure.
*/
void ELCDIF_RgbModeGetDefaultConfig(elcdif_rgb_mode_config_t *config)
{
assert(config);
/* Initializes the configure structure to zero. */
memset(config, 0, sizeof(*config));
config->panelWidth = 480U;
config->panelHeight = 272U;
config->hsw = 41;
@ -157,6 +193,11 @@ void ELCDIF_RgbModeGetDefaultConfig(elcdif_rgb_mode_config_t *config)
config->dataBus = kELCDIF_DataBus24Bit;
}
/*!
* brief Deinitializes the eLCDIF peripheral.
*
* param base eLCDIF peripheral base address.
*/
void ELCDIF_Deinit(LCDIF_Type *base)
{
ELCDIF_Reset(base);
@ -171,6 +212,11 @@ void ELCDIF_Deinit(LCDIF_Type *base)
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
}
/*!
* brief Stop display in RGB (DOTCLK) mode and wait until finished.
*
* param base eLCDIF peripheral base address.
*/
void ELCDIF_RgbModeStop(LCDIF_Type *base)
{
base->CTRL_CLR = LCDIF_CTRL_DOTCLK_MODE_MASK;
@ -181,6 +227,11 @@ void ELCDIF_RgbModeStop(LCDIF_Type *base)
}
}
/*!
* brief Reset the eLCDIF peripheral.
*
* param base eLCDIF peripheral base address.
*/
void ELCDIF_Reset(LCDIF_Type *base)
{
volatile uint32_t i = 0x100;
@ -211,6 +262,12 @@ void ELCDIF_Reset(LCDIF_Type *base)
}
#if !(defined(FSL_FEATURE_LCDIF_HAS_NO_AS) && FSL_FEATURE_LCDIF_HAS_NO_AS)
/*!
* brief Set the configuration for alpha surface buffer.
*
* param base eLCDIF peripheral base address.
* param config Pointer to the configuration structure.
*/
void ELCDIF_SetAlphaSurfaceBufferConfig(LCDIF_Type *base, const elcdif_as_buffer_config_t *config)
{
assert(config);
@ -220,6 +277,12 @@ void ELCDIF_SetAlphaSurfaceBufferConfig(LCDIF_Type *base, const elcdif_as_buffer
base->AS_NEXT_BUF = config->bufferAddr;
}
/*!
* brief Set the alpha surface blending configuration.
*
* param base eLCDIF peripheral base address.
* param config Pointer to the configuration structure.
*/
void ELCDIF_SetAlphaSurfaceBlendConfig(LCDIF_Type *base, const elcdif_as_blend_config_t *config)
{
assert(config);
@ -241,6 +304,20 @@ void ELCDIF_SetAlphaSurfaceBlendConfig(LCDIF_Type *base, const elcdif_as_blend_c
#endif /* FSL_FEATURE_LCDIF_HAS_NO_AS */
#if (defined(FSL_FEATURE_LCDIF_HAS_LUT) && FSL_FEATURE_LCDIF_HAS_LUT)
/*!
* brief Load the LUT value.
*
* This function loads the LUT value to the specific LUT memory, user can
* specify the start entry index.
*
* param base eLCDIF peripheral base address.
* param lut Which LUT to load.
* param startIndex The start index of the LUT entry to update.
* param lutData The LUT data to load.
* param count Count of p lutData.
* retval kStatus_Success Initialization success.
* retval kStatus_InvalidArgument Wrong argument.
*/
status_t ELCDIF_UpdateLut(
LCDIF_Type *base, elcdif_lut_t lut, uint16_t startIndex, const uint32_t *lutData, uint16_t count)
{

129
ext/hal/nxp/mcux/drivers/imx/fsl_enc.c
View file

@ -2,7 +2,7 @@
* Copyright (c) 2015, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
* All rights reserved.
*
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -62,6 +62,17 @@ static uint32_t ENC_GetInstance(ENC_Type *base)
return instance;
}
/*!
* brief Initialization for the ENC module.
*
* This function is to make the initialization for the ENC module. It should be called firstly before any operation to
* the ENC with the operations like:
* - Enable the clock for ENC module.
* - Configure the ENC's working attributes.
*
* param base ENC peripheral base address.
* param config Pointer to configuration structure. See to "enc_config_t".
*/
void ENC_Init(ENC_Type *base, const enc_config_t *config)
{
assert(NULL != config);
@ -151,6 +162,15 @@ void ENC_Init(ENC_Type *base, const enc_config_t *config)
base->LINIT = (uint16_t)(config->positionInitialValue); /* Lower 16 bits. */
}
/*!
* brief De-initialization for the ENC module.
*
* This function is to make the de-initialization for the ENC module. It could be called when ENC is no longer used with
* the operations like:
* - Disable the clock for ENC module.
*
* param base ENC peripheral base address.
*/
void ENC_Deinit(ENC_Type *base)
{
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
@ -159,10 +179,37 @@ void ENC_Deinit(ENC_Type *base)
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
}
/*!
* brief Get an available pre-defined settings for ENC's configuration.
*
* This function initializes the ENC configuration structure with an available settings, the default value are:
* code
* config->enableReverseDirection = false;
* config->decoderWorkMode = kENC_DecoderWorkAsNormalMode;
* config->HOMETriggerMode = kENC_HOMETriggerDisabled;
* config->INDEXTriggerMode = kENC_INDEXTriggerDisabled;
* config->enableTRIGGERClearPositionCounter = false;
* config->enableTRIGGERClearHoldPositionCounter = false;
* config->enableWatchdog = false;
* config->watchdogTimeoutValue = 0U;
* config->filterCount = 0U;
* config->filterSamplePeriod = 0U;
* config->positionMatchMode = kENC_POSMATCHOnPositionCounterEqualToComapreValue;
* config->positionCompareValue = 0xFFFFFFFFU;
* config->revolutionCountCondition = kENC_RevolutionCountOnINDEXPulse;
* config->enableModuloCountMode = false;
* config->positionModulusValue = 0U;
* config->positionInitialValue = 0U;
* endcode
* param config Pointer to a variable of configuration structure. See to "enc_config_t".
*/
void ENC_GetDefaultConfig(enc_config_t *config)
{
assert(NULL != config);
/* Initializes the configure structure to zero. */
memset(config, 0, sizeof(*config));
config->enableReverseDirection = false;
config->decoderWorkMode = kENC_DecoderWorkAsNormalMode;
config->HOMETriggerMode = kENC_HOMETriggerDisabled;
@ -181,6 +228,14 @@ void ENC_GetDefaultConfig(enc_config_t *config)
config->positionInitialValue = 0U;
}
/*!
* brief Load the initial position value to position counter.
*
* This function is to transfer the initial position value (UINIT and LINIT) contents to position counter (UPOS and
* LPOS), so that to provide the consistent operation the position counter registers.
*
* param base ENC peripheral base address.
*/
void ENC_DoSoftwareLoadInitialPositionValue(ENC_Type *base)
{
uint16_t tmp16 = base->CTRL & (uint16_t)(~ENC_CTRL_W1C_FLAGS);
@ -189,6 +244,16 @@ void ENC_DoSoftwareLoadInitialPositionValue(ENC_Type *base)
base->CTRL = tmp16;
}
/*!
* brief Enable and configure the self test function.
*
* This function is to enable and configuration the self test function. It controls and sets the frequency of a
* quadrature signal generator. It provides a quadrature test signal to the inputs of the quadrature decoder module.
* It is a factory test feature; however, it may be useful to customers' software development and testing.
*
* param base ENC peripheral base address.
* param config Pointer to configuration structure. See to "enc_self_test_config_t". Pass "NULL" to disable.
*/
void ENC_SetSelfTestConfig(ENC_Type *base, const enc_self_test_config_t *config)
{
uint16_t tmp16 = 0U;
@ -207,6 +272,12 @@ void ENC_SetSelfTestConfig(ENC_Type *base, const enc_self_test_config_t *config)
base->TST = tmp16;
}
/*!
* brief Enable watchdog for ENC module.
*
* param base ENC peripheral base address
* param enable Enables or disables the watchdog
*/
void ENC_EnableWatchdog(ENC_Type *base, bool enable)
{
uint16_t tmp16 = base->CTRL & (uint16_t)(~(ENC_CTRL_W1C_FLAGS | ENC_CTRL_WDE_MASK));
@ -218,6 +289,13 @@ void ENC_EnableWatchdog(ENC_Type *base, bool enable)
base->CTRL = tmp16;
}
/*!
* brief Get the status flags.
*
* param base ENC peripheral base address.
*
* return Mask value of status flags. For available mask, see to "_enc_status_flags".
*/
uint32_t ENC_GetStatusFlags(ENC_Type *base)
{
uint32_t ret32 = 0U;
@ -261,6 +339,12 @@ uint32_t ENC_GetStatusFlags(ENC_Type *base)
return ret32;
}
/*!
* brief Clear the status flags.
*
* param base ENC peripheral base address.
* param mask Mask value of status flags to be cleared. For available mask, see to "_enc_status_flags".
*/
void ENC_ClearStatusFlags(ENC_Type *base, uint32_t mask)
{
uint32_t tmp16 = 0U;
@ -307,6 +391,12 @@ void ENC_ClearStatusFlags(ENC_Type *base, uint32_t mask)
}
}
/*!
* brief Enable the interrupts.
*
* param base ENC peripheral base address.
* param mask Mask value of interrupts to be enabled. For available mask, see to "_enc_interrupt_enable".
*/
void ENC_EnableInterrupts(ENC_Type *base, uint32_t mask)
{
uint32_t tmp16 = 0U;
@ -352,6 +442,12 @@ void ENC_EnableInterrupts(ENC_Type *base, uint32_t mask)
}
}
/*!
* brief Disable the interrupts.
*
* param base ENC peripheral base address.
* param mask Mask value of interrupts to be disabled. For available mask, see to "_enc_interrupt_enable".
*/
void ENC_DisableInterrupts(ENC_Type *base, uint32_t mask)
{
uint16_t tmp16 = 0U;
@ -397,6 +493,13 @@ void ENC_DisableInterrupts(ENC_Type *base, uint32_t mask)
}
}
/*!
* brief Get the enabled interrupts' flags.
*
* param base ENC peripheral base address.
*
* return Mask value of enabled interrupts.
*/
uint32_t ENC_GetEnabledInterrupts(ENC_Type *base)
{
uint32_t ret32 = 0U;
@ -434,12 +537,25 @@ uint32_t ENC_GetEnabledInterrupts(ENC_Type *base)
return ret32;
}
/*!
* brief Set initial position value for ENC module.
*
* param base ENC peripheral base address
* param value Positive initial value
*/
void ENC_SetInitialPositionValue(ENC_Type *base, uint32_t value)
{
base->UINIT = (uint16_t)(value >> 16U); /* Set upper 16 bits. */
base->LINIT = (uint16_t)(value); /* Set lower 16 bits. */
}
/*!
* brief Get the current position counter's value.
*
* param base ENC peripheral base address.
*
* return Current position counter's value.
*/
uint32_t ENC_GetPositionValue(ENC_Type *base)
{
uint32_t ret32;
@ -451,6 +567,17 @@ uint32_t ENC_GetPositionValue(ENC_Type *base)
return ret32;
}
/*!
* brief Get the hold position counter's value.
*
* When any of the counter registers is read, the contents of each counter register is written to the corresponding hold
* register. Taking a snapshot of the counters' values provides a consistent view of a system position and a velocity to
* be attained.
*
* param base ENC peripheral base address.
*
* return Hold position counter's value.
*/
uint32_t ENC_GetHoldPositionValue(ENC_Type *base)
{
uint32_t ret32;

667
ext/hal/nxp/mcux/drivers/imx/fsl_enet.c
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62
ext/hal/nxp/mcux/drivers/imx/fsl_ewm.c
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@ -2,7 +2,7 @@
* Copyright (c) 2015, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
* All rights reserved.
*
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -13,11 +13,29 @@
#define FSL_COMPONENT_ID "platform.drivers.ewm"
#endif
/*******************************************************************************
* Code
******************************************************************************/
/*!
* brief Initializes the EWM peripheral.
*
* This function is used to initialize the EWM. After calling, the EWM
* runs immediately according to the configuration.
* Note that, except for the interrupt enable control bit, other control bits and registers are write once after a
* CPU reset. Modifying them more than once generates a bus transfer error.
*
* This is an example.
* code
* ewm_config_t config;
* EWM_GetDefaultConfig(&config);
* config.compareHighValue = 0xAAU;
* EWM_Init(ewm_base,&config);
* endcode
*
* param base EWM peripheral base address
* param config The configuration of the EWM
*/
void EWM_Init(EWM_Type *base, const ewm_config_t *config)
{
assert(config);
@ -25,7 +43,7 @@ void EWM_Init(EWM_Type *base, const ewm_config_t *config)
uint32_t value = 0U;
#if !((defined(FSL_FEATURE_SOC_PCC_COUNT) && FSL_FEATURE_SOC_PCC_COUNT) && \
(defined(FSL_FEATURE_PCC_SUPPORT_EWM_CLOCK_REMOVE) && FSL_FEATURE_PCC_SUPPORT_EWM_CLOCK_REMOVE))
(defined(FSL_FEATURE_PCC_SUPPORT_EWM_CLOCK_REMOVE) && FSL_FEATURE_PCC_SUPPORT_EWM_CLOCK_REMOVE))
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
CLOCK_EnableClock(kCLOCK_Ewm0);
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
@ -45,21 +63,50 @@ void EWM_Init(EWM_Type *base, const ewm_config_t *config)
base->CTRL = value;
}
/*!
* brief Deinitializes the EWM peripheral.
*
* This function is used to shut down the EWM.
*
* param base EWM peripheral base address
*/
void EWM_Deinit(EWM_Type *base)
{
EWM_DisableInterrupts(base, kEWM_InterruptEnable);
#if !((defined(FSL_FEATURE_SOC_PCC_COUNT) && FSL_FEATURE_SOC_PCC_COUNT) && \
(defined(FSL_FEATURE_PCC_SUPPORT_EWM_CLOCK_REMOVE) && FSL_FEATURE_PCC_SUPPORT_EWM_CLOCK_REMOVE))
(defined(FSL_FEATURE_PCC_SUPPORT_EWM_CLOCK_REMOVE) && FSL_FEATURE_PCC_SUPPORT_EWM_CLOCK_REMOVE))
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
CLOCK_DisableClock(kCLOCK_Ewm0);
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
#endif /* FSL_FEATURE_PCC_SUPPORT_EWM_CLOCK_REMOVE */
}
/*!
* brief Initializes the EWM configuration structure.
*
* This function initializes the EWM configuration structure to default values. The default
* values are as follows.
* code
* ewmConfig->enableEwm = true;
* ewmConfig->enableEwmInput = false;
* ewmConfig->setInputAssertLogic = false;
* ewmConfig->enableInterrupt = false;
* ewmConfig->ewm_lpo_clock_source_t = kEWM_LpoClockSource0;
* ewmConfig->prescaler = 0;
* ewmConfig->compareLowValue = 0;
* ewmConfig->compareHighValue = 0xFEU;
* endcode
*
* param config Pointer to the EWM configuration structure.
* see ewm_config_t
*/
void EWM_GetDefaultConfig(ewm_config_t *config)
{
assert(config);
/* Initializes the configure structure to zero. */
memset(config, 0, sizeof(*config));
config->enableEwm = true;
config->enableEwmInput = false;
config->setInputAssertLogic = false;
@ -74,6 +121,13 @@ void EWM_GetDefaultConfig(ewm_config_t *config)
config->compareHighValue = 0xFEU;
}
/*!
* brief Services the EWM.
*
* This function resets the EWM counter to zero.
*
* param base EWM peripheral base address
*/
void EWM_Refresh(EWM_Type *base)
{
uint32_t primaskValue = 0U;

757
ext/hal/nxp/mcux/drivers/imx/fsl_flexcan.c
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79
ext/hal/nxp/mcux/drivers/imx/fsl_flexcan.h
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@ -21,10 +21,15 @@
/*! @name Driver version */
/*@{*/
/*! @brief FlexCAN driver version 2.2.3. */
#define FSL_FLEXCAN_DRIVER_VERSION (MAKE_VERSION(2, 2, 3))
/*! @brief FlexCAN driver version 2.3.0. */
#define FSL_FLEXCAN_DRIVER_VERSION (MAKE_VERSION(2, 3, 2))
/*@}*/
#ifndef FLEXCAN_WAIT_TIMEOUT
/* Define to 1000 means keep waiting 1000 times until the flag is assert/deassert. */
#define FLEXCAN_WAIT_TIMEOUT (1000U)
#endif
/*! @brief FlexCAN Frame ID helper macro. */
#define FLEXCAN_ID_STD(id) \
(((uint32_t)(((uint32_t)(id)) << CAN_ID_STD_SHIFT)) & CAN_ID_STD_MASK) /*!< Standard Frame ID helper macro. */
@ -99,10 +104,9 @@
#define FLEXCAN_RX_FIFO_STD_FILTER_TYPE_C_MID_LOW(id) \
FLEXCAN_RX_FIFO_STD_MASK_TYPE_C_MID_LOW( \
id) /*!< Standard Rx FIFO Filter helper macro Type C mid-lower part helper macro. */
#define FLEXCAN_RX_FIFO_STD_FILTER_TYPE_C_LOW(id) \
FLEXCAN_RX_FIFO_STD_MASK_TYPE_C_LOW( \
id) /*!< Standard Rx FIFO Filter helper macro Type C lower part helper macro. \ \ \ \ \ \
*/
#define FLEXCAN_RX_FIFO_STD_FILTER_TYPE_C_LOW(id) \
FLEXCAN_RX_FIFO_STD_MASK_TYPE_C_LOW( \
id) /*!< Standard Rx FIFO Filter helper macro Type C lower part helper macro. */
#define FLEXCAN_RX_FIFO_EXT_FILTER_TYPE_A(id, rtr, ide) \
FLEXCAN_RX_FIFO_EXT_MASK_TYPE_A(id, rtr, ide) /*!< Extend Rx FIFO Filter helper macro Type A helper macro. */
#define FLEXCAN_RX_FIFO_EXT_FILTER_TYPE_B_HIGH(id, rtr, ide) \
@ -111,10 +115,9 @@
#define FLEXCAN_RX_FIFO_EXT_FILTER_TYPE_B_LOW(id, rtr, ide) \
FLEXCAN_RX_FIFO_EXT_MASK_TYPE_B_LOW( \
id, rtr, ide) /*!< Extend Rx FIFO Filter helper macro Type B lower part helper macro. */
#define FLEXCAN_RX_FIFO_EXT_FILTER_TYPE_C_HIGH(id) \
FLEXCAN_RX_FIFO_EXT_MASK_TYPE_C_HIGH( \
id) /*!< Extend Rx FIFO Filter helper macro Type C upper part helper macro. \ \ \ \ \ \
*/
#define FLEXCAN_RX_FIFO_EXT_FILTER_TYPE_C_HIGH(id) \
FLEXCAN_RX_FIFO_EXT_MASK_TYPE_C_HIGH( \
id) /*!< Extend Rx FIFO Filter helper macro Type C upper part helper macro. */
#define FLEXCAN_RX_FIFO_EXT_FILTER_TYPE_C_MID_HIGH(id) \
FLEXCAN_RX_FIFO_EXT_MASK_TYPE_C_MID_HIGH( \
id) /*!< Extend Rx FIFO Filter helper macro Type C mid-upper part helper macro. */
@ -139,7 +142,8 @@ enum _flexcan_status
kStatus_FLEXCAN_RxFifoOverflow = MAKE_STATUS(kStatusGroup_FLEXCAN, 8), /*!< Rx Message FIFO is overflowed. */
kStatus_FLEXCAN_RxFifoWarning = MAKE_STATUS(kStatusGroup_FLEXCAN, 9), /*!< Rx Message FIFO is almost overflowed. */
kStatus_FLEXCAN_ErrorStatus = MAKE_STATUS(kStatusGroup_FLEXCAN, 10), /*!< FlexCAN Module Error and Status. */
kStatus_FLEXCAN_UnHandled = MAKE_STATUS(kStatusGroup_FLEXCAN, 11), /*!< UnHadled Interrupt asserted. */
kStatus_FLEXCAN_WakeUp = MAKE_STATUS(kStatusGroup_FLEXCAN, 11), /*!< FlexCAN is waken up from STOP mode. */
kStatus_FLEXCAN_UnHandled = MAKE_STATUS(kStatusGroup_FLEXCAN, 12), /*!< UnHadled Interrupt asserted. */
};
/*! @brief FlexCAN frame format. */
@ -163,6 +167,13 @@ typedef enum _flexcan_clock_source
kFLEXCAN_ClkSrcPeri = 0x1U, /*!< FlexCAN Protocol Engine clock from Peripheral Clock. */
} flexcan_clock_source_t;
/*! @brief FlexCAN wake up source. */
typedef enum _flexcan_wake_up_source
{
kFLEXCAN_WakeupSrcUnfiltered = 0x0U, /*!< FlexCAN uses unfiltered Rx input to detect edge. */
kFLEXCAN_WakeupSrcFiltered = 0x1U, /*!< FlexCAN uses filtered Rx input to detect edge. */
} flexcan_wake_up_source_t;
/*! @brief FlexCAN Rx Fifo Filter type. */
typedef enum _flexcan_rx_fifo_filter_type
{
@ -241,13 +252,13 @@ enum _flexcan_flags
kFLEXCAN_BusOffIntFlag = CAN_ESR1_BOFFINT_MASK, /*!< Bus Off Interrupt Flag. */
kFLEXCAN_ErrorIntFlag = CAN_ESR1_ERRINT_MASK, /*!< Error Interrupt Flag. */
kFLEXCAN_WakeUpIntFlag = CAN_ESR1_WAKINT_MASK, /*!< Wake-Up Interrupt Flag. */
kFLEXCAN_ErrorFlag = /*!< All FlexCAN Error Status. */
kFLEXCAN_ErrorFlag = (int)( /*!< All FlexCAN Error Status. */
#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE)
CAN_ESR1_STFERR_FAST_MASK | CAN_ESR1_FRMERR_FAST_MASK | CAN_ESR1_CRCERR_FAST_MASK | CAN_ESR1_BIT0ERR_FAST_MASK |
CAN_ESR1_BIT1ERR_FAST_MASK | CAN_ESR1_ERROVR_MASK |
CAN_ESR1_STFERR_FAST_MASK | CAN_ESR1_FRMERR_FAST_MASK | CAN_ESR1_CRCERR_FAST_MASK |
CAN_ESR1_BIT0ERR_FAST_MASK | CAN_ESR1_BIT1ERR_FAST_MASK | CAN_ESR1_ERROVR_MASK |
#endif
CAN_ESR1_BIT1ERR_MASK | CAN_ESR1_BIT0ERR_MASK | CAN_ESR1_ACKERR_MASK | CAN_ESR1_CRCERR_MASK | CAN_ESR1_FRMERR_MASK |
CAN_ESR1_STFERR_MASK,
CAN_ESR1_BIT1ERR_MASK | CAN_ESR1_BIT0ERR_MASK | CAN_ESR1_ACKERR_MASK |
CAN_ESR1_CRCERR_MASK | CAN_ESR1_FRMERR_MASK | CAN_ESR1_STFERR_MASK),
};
/*!
@ -260,12 +271,12 @@ enum _flexcan_flags
enum _flexcan_error_flags
{
#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE)
kFLEXCAN_FDStuffingError = CAN_ESR1_STFERR_FAST_MASK, /*!< Stuffing Error. */
kFLEXCAN_FDFormError = CAN_ESR1_FRMERR_FAST_MASK, /*!< Form Error. */
kFLEXCAN_FDCrcError = CAN_ESR1_CRCERR_FAST_MASK, /*!< Cyclic Redundancy Check Error. */
kFLEXCAN_FDBit0Error = CAN_ESR1_BIT0ERR_FAST_MASK, /*!< Unable to send dominant bit. */
kFLEXCAN_FDBit1Error = CAN_ESR1_BIT1ERR_FAST_MASK, /*!< Unable to send recessive bit. */
kFLEXCAN_OverrunError = CAN_ESR1_ERROVR_MASK, /*!< Error Overrun Status. */
kFLEXCAN_FDStuffingError = CAN_ESR1_STFERR_FAST_MASK, /*!< Stuffing Error. */
kFLEXCAN_FDFormError = CAN_ESR1_FRMERR_FAST_MASK, /*!< Form Error. */
kFLEXCAN_FDCrcError = CAN_ESR1_CRCERR_FAST_MASK, /*!< Cyclic Redundancy Check Error. */
kFLEXCAN_FDBit0Error = CAN_ESR1_BIT0ERR_FAST_MASK, /*!< Unable to send dominant bit. */
kFLEXCAN_FDBit1Error = (int)CAN_ESR1_BIT1ERR_FAST_MASK, /*!< Unable to send recessive bit. */
kFLEXCAN_OverrunError = CAN_ESR1_ERROVR_MASK, /*!< Error Overrun Status. */
#endif
kFLEXCAN_StuffingError = CAN_ESR1_STFERR_MASK, /*!< Stuffing Error. */
kFLEXCAN_FormError = CAN_ESR1_FRMERR_MASK, /*!< Form Error. */
@ -343,11 +354,11 @@ typedef struct _flexcan_fd_frame
uint32_t format : 1; /*!< CAN Frame Identifier(STD or EXT format). */
uint32_t srr : 1; /*!< Substitute Remote request. */
uint32_t : 1;
uint32_t code : 4; /*!< Message Buffer Code. */
uint32_t code : 4; /*!< Message Buffer Code. */
uint32_t : 1;
uint32_t esi : 1; /*!< Error State Indicator. */
uint32_t brs : 1; /*!< Bit Rate Switch. */
uint32_t edl : 1; /*!< Extended Data Length. */
uint32_t esi : 1; /*!< Error State Indicator. */
uint32_t brs : 1; /*!< Bit Rate Switch. */
uint32_t edl : 1; /*!< Extended Data Length. */
};
struct
{
@ -401,12 +412,13 @@ typedef struct _flexcan_config
#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE)
uint32_t baudRateFD; /*!< FlexCAN FD baud rate in bps. */
#endif
flexcan_clock_source_t clkSrc; /*!< Clock source for FlexCAN Protocol Engine. */
uint8_t maxMbNum; /*!< The maximum number of Message Buffers used by user. */
bool enableLoopBack; /*!< Enable or Disable Loop Back Self Test Mode. */
bool enableTimerSync; /*!< Enable or Disable Timer Synchronization. */
bool enableSelfWakeup; /*!< Enable or Disable Self Wakeup Mode. */
bool enableIndividMask; /*!< Enable or Disable Rx Individual Mask. */
flexcan_clock_source_t clkSrc; /*!< Clock source for FlexCAN Protocol Engine. */
flexcan_wake_up_source_t wakeupSrc; /*!< Wake up source selection. */
uint8_t maxMbNum; /*!< The maximum number of Message Buffers used by user. */
bool enableLoopBack; /*!< Enable or Disable Loop Back Self Test Mode. */
bool enableTimerSync; /*!< Enable or Disable Timer Synchronization. */
bool enableSelfWakeup; /*!< Enable or Disable Self Wakeup Mode. */
bool enableIndividMask; /*!< Enable or Disable Rx Individual Mask. */
#if (defined(FSL_FEATURE_FLEXCAN_HAS_DOZE_MODE_SUPPORT) && FSL_FEATURE_FLEXCAN_HAS_DOZE_MODE_SUPPORT)
bool enableDoze; /*!< Enable or Disable Doze Mode. */
#endif
@ -559,7 +571,8 @@ void FLEXCAN_Init(CAN_Type *base, const flexcan_config_t *config, uint32_t sourc
* @param dataSize FlexCAN FD frame payload size.
* @param brs If bitrate switch is enabled in FD mode.
*/
void FLEXCAN_FDInit(CAN_Type *base, const flexcan_config_t *config, uint32_t sourceClock_Hz, flexcan_mb_size_t dataSize, bool brs);
void FLEXCAN_FDInit(
CAN_Type *base, const flexcan_config_t *config, uint32_t sourceClock_Hz, flexcan_mb_size_t dataSize, bool brs);
#endif
/*!

132
ext/hal/nxp/mcux/drivers/imx/fsl_flexio.c
View file

@ -2,7 +2,7 @@
* Copyright (c) 2015, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
* All rights reserved.
*
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -17,7 +17,6 @@
#define FSL_COMPONENT_ID "platform.drivers.flexio"
#endif
/*< @brief user configurable flexio handle count. */
#define FLEXIO_HANDLE_COUNT 2
@ -45,6 +44,11 @@ static flexio_isr_t s_flexioIsr[FLEXIO_HANDLE_COUNT];
* Codes
******************************************************************************/
/*!
* brief Get instance number for FLEXIO module.
*
* param base FLEXIO peripheral base address.
*/
uint32_t FLEXIO_GetInstance(FLEXIO_Type *base)
{
uint32_t instance;
@ -63,6 +67,24 @@ uint32_t FLEXIO_GetInstance(FLEXIO_Type *base)
return instance;
}
/*!
* brief Configures the FlexIO with a FlexIO configuration. The configuration structure
* can be filled by the user or be set with default values by FLEXIO_GetDefaultConfig().
*
* Example
code
flexio_config_t config = {
.enableFlexio = true,
.enableInDoze = false,
.enableInDebug = true,
.enableFastAccess = false
};
FLEXIO_Configure(base, &config);
endcode
*
* param base FlexIO peripheral base address
* param userConfig pointer to flexio_config_t structure
*/
void FLEXIO_Init(FLEXIO_Type *base, const flexio_config_t *userConfig)
{
uint32_t ctrlReg = 0;
@ -85,6 +107,13 @@ void FLEXIO_Init(FLEXIO_Type *base, const flexio_config_t *userConfig)
base->CTRL = ctrlReg;
}
/*!
* brief Gates the FlexIO clock. Call this API to stop the FlexIO clock.
*
* note After calling this API, call the FLEXO_Init to use the FlexIO module.
*
* param base FlexIO peripheral base address
*/
void FLEXIO_Deinit(FLEXIO_Type *base)
{
FLEXIO_Enable(base, false);
@ -93,16 +122,36 @@ void FLEXIO_Deinit(FLEXIO_Type *base)
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
}
/*!
* brief Gets the default configuration to configure the FlexIO module. The configuration
* can used directly to call the FLEXIO_Configure().
*
* Example:
code
flexio_config_t config;
FLEXIO_GetDefaultConfig(&config);
endcode
*
* param userConfig pointer to flexio_config_t structure
*/
void FLEXIO_GetDefaultConfig(flexio_config_t *userConfig)
{
assert(userConfig);
/* Initializes the configure structure to zero. */
memset(userConfig, 0, sizeof(*userConfig));
userConfig->enableFlexio = true;
userConfig->enableInDoze = false;
userConfig->enableInDebug = true;
userConfig->enableFastAccess = false;
}
/*!
* brief Resets the FlexIO module.
*
* param base FlexIO peripheral base address
*/
void FLEXIO_Reset(FLEXIO_Type *base)
{
/*do software reset, software reset operation affect all other FLEXIO registers except CTRL*/
@ -110,6 +159,14 @@ void FLEXIO_Reset(FLEXIO_Type *base)
base->CTRL = 0;
}
/*!
* brief Gets the shifter buffer address for the DMA transfer usage.
*
* param base FlexIO peripheral base address
* param type Shifter type of flexio_shifter_buffer_type_t
* param index Shifter index
* return Corresponding shifter buffer index
*/
uint32_t FLEXIO_GetShifterBufferAddress(FLEXIO_Type *base, flexio_shifter_buffer_type_t type, uint8_t index)
{
assert(index < FLEXIO_SHIFTBUF_COUNT);
@ -158,6 +215,31 @@ uint32_t FLEXIO_GetShifterBufferAddress(FLEXIO_Type *base, flexio_shifter_buffer
return address;
}
/*!
* brief Configures the shifter with the shifter configuration. The configuration structure
* covers both the SHIFTCTL and SHIFTCFG registers. To configure the shifter to the proper
* mode, select which timer controls the shifter to shift, whether to generate start bit/stop
* bit, and the polarity of start bit and stop bit.
*
* Example
code
flexio_shifter_config_t config = {
.timerSelect = 0,
.timerPolarity = kFLEXIO_ShifterTimerPolarityOnPositive,
.pinConfig = kFLEXIO_PinConfigOpenDrainOrBidirection,
.pinPolarity = kFLEXIO_PinActiveLow,
.shifterMode = kFLEXIO_ShifterModeTransmit,
.inputSource = kFLEXIO_ShifterInputFromPin,
.shifterStop = kFLEXIO_ShifterStopBitHigh,
.shifterStart = kFLEXIO_ShifterStartBitLow
};
FLEXIO_SetShifterConfig(base, &config);
endcode
*
* param base FlexIO peripheral base address
* param index Shifter index
* param shifterConfig Pointer to flexio_shifter_config_t structure
*/
void FLEXIO_SetShifterConfig(FLEXIO_Type *base, uint8_t index, const flexio_shifter_config_t *shifterConfig)
{
base->SHIFTCFG[index] = FLEXIO_SHIFTCFG_INSRC(shifterConfig->inputSource)
@ -173,6 +255,36 @@ void FLEXIO_SetShifterConfig(FLEXIO_Type *base, uint8_t index, const flexio_shif
FLEXIO_SHIFTCTL_PINPOL(shifterConfig->pinPolarity) | FLEXIO_SHIFTCTL_SMOD(shifterConfig->shifterMode);
}
/*!
* brief Configures the timer with the timer configuration. The configuration structure
* covers both the TIMCTL and TIMCFG registers. To configure the timer to the proper
* mode, select trigger source for timer and the timer pin output and the timing for timer.
*
* Example
code
flexio_timer_config_t config = {
.triggerSelect = FLEXIO_TIMER_TRIGGER_SEL_SHIFTnSTAT(0),
.triggerPolarity = kFLEXIO_TimerTriggerPolarityActiveLow,
.triggerSource = kFLEXIO_TimerTriggerSourceInternal,
.pinConfig = kFLEXIO_PinConfigOpenDrainOrBidirection,
.pinSelect = 0,
.pinPolarity = kFLEXIO_PinActiveHigh,
.timerMode = kFLEXIO_TimerModeDual8BitBaudBit,
.timerOutput = kFLEXIO_TimerOutputZeroNotAffectedByReset,
.timerDecrement = kFLEXIO_TimerDecSrcOnFlexIOClockShiftTimerOutput,
.timerReset = kFLEXIO_TimerResetOnTimerPinEqualToTimerOutput,
.timerDisable = kFLEXIO_TimerDisableOnTimerCompare,
.timerEnable = kFLEXIO_TimerEnableOnTriggerHigh,
.timerStop = kFLEXIO_TimerStopBitEnableOnTimerDisable,
.timerStart = kFLEXIO_TimerStartBitEnabled
};
FLEXIO_SetTimerConfig(base, &config);
endcode
*
* param base FlexIO peripheral base address
* param index Timer index
* param timerConfig Pointer to the flexio_timer_config_t structure
*/
void FLEXIO_SetTimerConfig(FLEXIO_Type *base, uint8_t index, const flexio_timer_config_t *timerConfig)
{
base->TIMCFG[index] =
@ -190,6 +302,15 @@ void FLEXIO_SetTimerConfig(FLEXIO_Type *base, uint8_t index, const flexio_timer_
FLEXIO_TIMCTL_PINPOL(timerConfig->pinPolarity) | FLEXIO_TIMCTL_TIMOD(timerConfig->timerMode);
}
/*!
* brief Registers the handle and the interrupt handler for the FlexIO-simulated peripheral.
*
* param base Pointer to the FlexIO simulated peripheral type.
* param handle Pointer to the handler for FlexIO simulated peripheral.
* param isr FlexIO simulated peripheral interrupt handler.
* retval kStatus_Success Successfully create the handle.
* retval kStatus_OutOfRange The FlexIO type/handle/ISR table out of range.
*/
status_t FLEXIO_RegisterHandleIRQ(void *base, void *handle, flexio_isr_t isr)
{
assert(base);
@ -221,6 +342,13 @@ status_t FLEXIO_RegisterHandleIRQ(void *base, void *handle, flexio_isr_t isr)
}
}
/*!
* brief Unregisters the handle and the interrupt handler for the FlexIO-simulated peripheral.
*
* param base Pointer to the FlexIO simulated peripheral type.
* retval kStatus_Success Successfully create the handle.
* retval kStatus_OutOfRange The FlexIO type/handle/ISR table out of range.
*/
status_t FLEXIO_UnregisterHandleIRQ(void *base)
{
assert(base);

4
ext/hal/nxp/mcux/drivers/imx/fsl_flexio.h
View file

@ -151,8 +151,8 @@ typedef enum _flexio_timer_start_bit_condition
/*! @brief Define type of timer polarity for shifter control. */
typedef enum _flexio_shifter_timer_polarity
{
kFLEXIO_ShifterTimerPolarityOnPositive = 0x0U, /* Shift on positive edge of shift clock. */
kFLEXIO_ShifterTimerPolarityOnNegitive = 0x1U, /* Shift on negative edge of shift clock. */
kFLEXIO_ShifterTimerPolarityOnPositive = 0x0U, /*!< Shift on positive edge of shift clock. */
kFLEXIO_ShifterTimerPolarityOnNegitive = 0x1U, /*!< Shift on negative edge of shift clock. */
} flexio_shifter_timer_polarity_t;
/*! @brief Define type of shifter working mode.*/

211
ext/hal/nxp/mcux/drivers/imx/fsl_flexio_i2c_master.c
View file

@ -353,6 +353,34 @@ static void FLEXIO_I2C_MasterTransferComplete(FLEXIO_I2C_Type *base,
}
}
/*!
* brief Ungates the FlexIO clock, resets the FlexIO module, and configures the FlexIO I2C
* hardware configuration.
*
* Example
code
FLEXIO_I2C_Type base = {
.flexioBase = FLEXIO,
.SDAPinIndex = 0,
.SCLPinIndex = 1,
.shifterIndex = {0,1},
.timerIndex = {0,1}
};
flexio_i2c_master_config_t config = {
.enableInDoze = false,
.enableInDebug = true,
.enableFastAccess = false,
.baudRate_Bps = 100000
};
FLEXIO_I2C_MasterInit(base, &config, srcClock_Hz);
endcode
*
* param base Pointer to FLEXIO_I2C_Type structure.
* param masterConfig Pointer to flexio_i2c_master_config_t structure.
* param srcClock_Hz FlexIO source clock in Hz.
* retval kStatus_Success Initialization successful
* retval kStatus_InvalidArgument The source clock exceed upper range limitation
*/
status_t FLEXIO_I2C_MasterInit(FLEXIO_I2C_Type *base, flexio_i2c_master_config_t *masterConfig, uint32_t srcClock_Hz)
{
assert(base && masterConfig);
@ -463,6 +491,12 @@ status_t FLEXIO_I2C_MasterInit(FLEXIO_I2C_Type *base, flexio_i2c_master_config_t
return result;
}
/*!
* brief De-initializes the FlexIO I2C master peripheral. Calling this API Resets the FlexIO I2C master
* shifer and timer config, module can't work unless the FLEXIO_I2C_MasterInit is called.
*
* param base pointer to FLEXIO_I2C_Type structure.
*/
void FLEXIO_I2C_MasterDeinit(FLEXIO_I2C_Type *base)
{
base->flexioBase->SHIFTCFG[base->shifterIndex[0]] = 0;
@ -483,10 +517,24 @@ void FLEXIO_I2C_MasterDeinit(FLEXIO_I2C_Type *base)
base->flexioBase->TIMSTAT = (1U << base->timerIndex[1]);
}
/*!
* brief Gets the default configuration to configure the FlexIO module. The configuration
* can be used directly for calling the FLEXIO_I2C_MasterInit().
*
* Example:
code
flexio_i2c_master_config_t config;
FLEXIO_I2C_MasterGetDefaultConfig(&config);
endcode
* param masterConfig Pointer to flexio_i2c_master_config_t structure.
*/
void FLEXIO_I2C_MasterGetDefaultConfig(flexio_i2c_master_config_t *masterConfig)
{
assert(masterConfig);
/* Initializes the configure structure to zero. */
memset(masterConfig, 0, sizeof(*masterConfig));
masterConfig->enableMaster = true;
masterConfig->enableInDoze = false;
masterConfig->enableInDebug = true;
@ -496,6 +544,13 @@ void FLEXIO_I2C_MasterGetDefaultConfig(flexio_i2c_master_config_t *masterConfig)
masterConfig->baudRate_Bps = 100000U;
}
/*!
* brief Gets the FlexIO I2C master status flags.
*
* param base Pointer to FLEXIO_I2C_Type structure
* return Status flag, use status flag to AND #_flexio_i2c_master_status_flags can get the related status.
*/
uint32_t FLEXIO_I2C_MasterGetStatusFlags(FLEXIO_I2C_Type *base)
{
uint32_t status = 0;
@ -512,6 +567,16 @@ uint32_t FLEXIO_I2C_MasterGetStatusFlags(FLEXIO_I2C_Type *base)
return status;
}
/*!
* brief Clears the FlexIO I2C master status flags.
*
* param base Pointer to FLEXIO_I2C_Type structure.
* param mask Status flag.
* The parameter can be any combination of the following values:
* arg kFLEXIO_I2C_RxFullFlag
* arg kFLEXIO_I2C_ReceiveNakFlag
*/
void FLEXIO_I2C_MasterClearStatusFlags(FLEXIO_I2C_Type *base, uint32_t mask)
{
if (mask & kFLEXIO_I2C_TxEmptyFlag)
@ -530,6 +595,14 @@ void FLEXIO_I2C_MasterClearStatusFlags(FLEXIO_I2C_Type *base, uint32_t mask)
}
}
/*!
* brief Enables the FlexIO i2c master interrupt requests.
*
* param base Pointer to FLEXIO_I2C_Type structure.
* param mask Interrupt source.
* Currently only one interrupt request source:
* arg kFLEXIO_I2C_TransferCompleteInterruptEnable
*/
void FLEXIO_I2C_MasterEnableInterrupts(FLEXIO_I2C_Type *base, uint32_t mask)
{
if (mask & kFLEXIO_I2C_TxEmptyInterruptEnable)
@ -542,6 +615,12 @@ void FLEXIO_I2C_MasterEnableInterrupts(FLEXIO_I2C_Type *base, uint32_t mask)
}
}
/*!
* brief Disables the FlexIO I2C master interrupt requests.
*
* param base Pointer to FLEXIO_I2C_Type structure.
* param mask Interrupt source.
*/
void FLEXIO_I2C_MasterDisableInterrupts(FLEXIO_I2C_Type *base, uint32_t mask)
{
if (mask & kFLEXIO_I2C_TxEmptyInterruptEnable)
@ -554,6 +633,13 @@ void FLEXIO_I2C_MasterDisableInterrupts(FLEXIO_I2C_Type *base, uint32_t mask)
}
}
/*!
* brief Sets the FlexIO I2C master transfer baudrate.
*
* param base Pointer to FLEXIO_I2C_Type structure
* param baudRate_Bps the baud rate value in HZ
* param srcClock_Hz source clock in HZ
*/
void FLEXIO_I2C_MasterSetBaudRate(FLEXIO_I2C_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz)
{
uint16_t timerDiv = 0;
@ -571,6 +657,17 @@ void FLEXIO_I2C_MasterSetBaudRate(FLEXIO_I2C_Type *base, uint32_t baudRate_Bps,
flexioBase->TIMCMP[base->timerIndex[0]] = timerCmp;
}
/*!
* brief Sets the number of bytes to be transferred from a start signal to a stop signal.
*
* note Call this API before a transfer begins because the timer generates a number of clocks according
* to the number of bytes that need to be transferred.
*
* param base Pointer to FLEXIO_I2C_Type structure.
* param count Number of bytes need to be transferred from a start signal to a re-start/stop signal
* retval kStatus_Success Successfully configured the count.
* retval kStatus_InvalidArgument Input argument is invalid.
*/
status_t FLEXIO_I2C_MasterSetTransferCount(FLEXIO_I2C_Type *base, uint8_t count)
{
if (count > 14U)
@ -594,6 +691,21 @@ status_t FLEXIO_I2C_MasterSetTransferCount(FLEXIO_I2C_Type *base, uint8_t count)
return kStatus_Success;
}
/*!
* brief Sends START + 7-bit address to the bus.
*
* note This API should be called when the transfer configuration is ready to send a START signal
* and 7-bit address to the bus. This is a non-blocking API, which returns directly after the address
* is put into the data register but the address transfer is not finished on the bus. Ensure that
* the kFLEXIO_I2C_RxFullFlag status is asserted before calling this API.
* param base Pointer to FLEXIO_I2C_Type structure.
* param address 7-bit address.
* param direction transfer direction.
* This parameter is one of the values in flexio_i2c_direction_t:
* arg kFLEXIO_I2C_Write: Transmit
* arg kFLEXIO_I2C_Read: Receive
*/
void FLEXIO_I2C_MasterStart(FLEXIO_I2C_Type *base, uint8_t address, flexio_i2c_direction_t direction)
{
uint32_t data;
@ -603,12 +715,22 @@ void FLEXIO_I2C_MasterStart(FLEXIO_I2C_Type *base, uint8_t address, flexio_i2c_d
FLEXIO_I2C_MasterWriteByte(base, data);
}
/*!
* brief Sends the repeated start signal on the bus.
*
* param base Pointer to FLEXIO_I2C_Type structure.
*/
void FLEXIO_I2C_MasterRepeatedStart(FLEXIO_I2C_Type *base)
{
/* Prepare for RESTART condition, no stop.*/
FLEXIO_I2C_MasterWriteByte(base, 0xFFFFFFFFU);
}
/*!
* brief Sends the stop signal on the bus.
*
* param base Pointer to FLEXIO_I2C_Type structure.
*/
void FLEXIO_I2C_MasterStop(FLEXIO_I2C_Type *base)
{
/* Prepare normal stop. */
@ -616,6 +738,11 @@ void FLEXIO_I2C_MasterStop(FLEXIO_I2C_Type *base)
FLEXIO_I2C_MasterWriteByte(base, 0x0U);
}
/*!
* brief Sends the stop signal when transfer is still on-going.
*
* param base Pointer to FLEXIO_I2C_Type structure.
*/
void FLEXIO_I2C_MasterAbortStop(FLEXIO_I2C_Type *base)
{
uint32_t tmpConfig;
@ -627,6 +754,12 @@ void FLEXIO_I2C_MasterAbortStop(FLEXIO_I2C_Type *base)
base->flexioBase->TIMCFG[base->timerIndex[0]] = tmpConfig;
}
/*!
* brief Configures the sent ACK/NAK for the following byte.
*
* param base Pointer to FLEXIO_I2C_Type structure.
* param enable True to configure send ACK, false configure to send NAK.
*/
void FLEXIO_I2C_MasterEnableAck(FLEXIO_I2C_Type *base, bool enable)
{
uint32_t tmpConfig = 0;
@ -644,6 +777,17 @@ void FLEXIO_I2C_MasterEnableAck(FLEXIO_I2C_Type *base, bool enable)
base->flexioBase->SHIFTCFG[base->shifterIndex[0]] = tmpConfig;
}
/*!
* brief Sends a buffer of data in bytes.
*
* note This function blocks via polling until all bytes have been sent.
*
* param base Pointer to FLEXIO_I2C_Type structure.
* param txBuff The data bytes to send.
* param txSize The number of data bytes to send.
* retval kStatus_Success Successfully write data.
* retval kStatus_FLEXIO_I2C_Nak Receive NAK during writing data.
*/
status_t FLEXIO_I2C_MasterWriteBlocking(FLEXIO_I2C_Type *base, const uint8_t *txBuff, uint8_t txSize)
{
assert(txBuff);
@ -669,6 +813,15 @@ status_t FLEXIO_I2C_MasterWriteBlocking(FLEXIO_I2C_Type *base, const uint8_t *tx
return kStatus_Success;
}
/*!
* brief Receives a buffer of bytes.
*
* note This function blocks via polling until all bytes have been received.
*
* param base Pointer to FLEXIO_I2C_Type structure.
* param rxBuff The buffer to store the received bytes.
* param rxSize The number of data bytes to be received.
*/
void FLEXIO_I2C_MasterReadBlocking(FLEXIO_I2C_Type *base, uint8_t *rxBuff, uint8_t rxSize)
{
assert(rxBuff);
@ -685,6 +838,16 @@ void FLEXIO_I2C_MasterReadBlocking(FLEXIO_I2C_Type *base, uint8_t *rxBuff, uint8
}
}
/*!
* brief Performs a master polling transfer on the I2C bus.
*
* note The API does not return until the transfer succeeds or fails due
* to receiving NAK.
*
* param base pointer to FLEXIO_I2C_Type structure.
* param xfer pointer to flexio_i2c_master_transfer_t structure.
* return status of status_t.
*/
status_t FLEXIO_I2C_MasterTransferBlocking(FLEXIO_I2C_Type *base, flexio_i2c_master_transfer_t *xfer)
{
assert(xfer);
@ -714,6 +877,16 @@ status_t FLEXIO_I2C_MasterTransferBlocking(FLEXIO_I2C_Type *base, flexio_i2c_mas
return result;
}
/*!
* brief Initializes the I2C handle which is used in transactional functions.
*
* param base Pointer to FLEXIO_I2C_Type structure.
* param handle Pointer to flexio_i2c_master_handle_t structure to store the transfer state.
* param callback Pointer to user callback function.
* param userData User param passed to the callback function.
* retval kStatus_Success Successfully create the handle.
* retval kStatus_OutOfRange The FlexIO type/handle/isr table out of range.
*/
status_t FLEXIO_I2C_MasterTransferCreateHandle(FLEXIO_I2C_Type *base,
flexio_i2c_master_handle_t *handle,
flexio_i2c_master_transfer_callback_t callback,
@ -737,6 +910,20 @@ status_t FLEXIO_I2C_MasterTransferCreateHandle(FLEXIO_I2C_Type *base,
return FLEXIO_RegisterHandleIRQ(base, handle, FLEXIO_I2C_MasterTransferHandleIRQ);
}
/*!
* brief Performs a master interrupt non-blocking transfer on the I2C bus.
*
* note The API returns immediately after the transfer initiates.
* Call FLEXIO_I2C_MasterGetTransferCount to poll the transfer status to check whether
* the transfer is finished. If the return status is not kStatus_FLEXIO_I2C_Busy, the transfer
* is finished.
*
* param base Pointer to FLEXIO_I2C_Type structure
* param handle Pointer to flexio_i2c_master_handle_t structure which stores the transfer state
* param xfer pointer to flexio_i2c_master_transfer_t structure
* retval kStatus_Success Successfully start a transfer.
* retval kStatus_FLEXIO_I2C_Busy FlexIO I2C is not idle, is running another transfer.
*/
status_t FLEXIO_I2C_MasterTransferNonBlocking(FLEXIO_I2C_Type *base,
flexio_i2c_master_handle_t *handle,
flexio_i2c_master_transfer_t *xfer)
@ -760,6 +947,15 @@ status_t FLEXIO_I2C_MasterTransferNonBlocking(FLEXIO_I2C_Type *base,
}
}
/*!
* brief Aborts an interrupt non-blocking transfer early.
*
* note This API can be called at any time when an interrupt non-blocking transfer initiates
* to abort the transfer early.
*
* param base Pointer to FLEXIO_I2C_Type structure
* param handle Pointer to flexio_i2c_master_handle_t structure which stores the transfer state
*/
void FLEXIO_I2C_MasterTransferAbort(FLEXIO_I2C_Type *base, flexio_i2c_master_handle_t *handle)
{
assert(handle);
@ -771,6 +967,15 @@ void FLEXIO_I2C_MasterTransferAbort(FLEXIO_I2C_Type *base, flexio_i2c_master_han
handle->state = kFLEXIO_I2C_Idle;
}
/*!
* brief Gets the master transfer status during a interrupt non-blocking transfer.
*
* param base Pointer to FLEXIO_I2C_Type structure.
* param handle Pointer to flexio_i2c_master_handle_t structure which stores the transfer state.
* param count Number of bytes transferred so far by the non-blocking transaction.
* retval kStatus_InvalidArgument count is Invalid.
* retval kStatus_Success Successfully return the count.
*/
status_t FLEXIO_I2C_MasterTransferGetCount(FLEXIO_I2C_Type *base, flexio_i2c_master_handle_t *handle, size_t *count)
{
if (!count)
@ -783,6 +988,12 @@ status_t FLEXIO_I2C_MasterTransferGetCount(FLEXIO_I2C_Type *base, flexio_i2c_mas
return kStatus_Success;
}
/*!
* brief Master interrupt handler.
*
* param i2cType Pointer to FLEXIO_I2C_Type structure
* param i2cHandle Pointer to flexio_i2c_master_transfer_t structure
*/
void FLEXIO_I2C_MasterTransferHandleIRQ(void *i2cType, void *i2cHandle)
{
FLEXIO_I2C_Type *base = (FLEXIO_I2C_Type *)i2cType;

228
ext/hal/nxp/mcux/drivers/imx/fsl_flexio_i2s.c
View file

@ -1,8 +1,8 @@
/*
* Copyright (c) 2015, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
* Copyright 2016-2018 NXP
* All rights reserved.
*
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -13,7 +13,6 @@
#define FSL_COMPONENT_ID "platform.drivers.flexio_i2s"
#endif
/*******************************************************************************
* Definitations
******************************************************************************/
@ -75,7 +74,7 @@ static void FLEXIO_I2S_WriteNonBlocking(FLEXIO_I2S_Type *base, uint8_t bitWidth,
data |= (temp << (8U * j));
txData++;
}
base->flexioBase->SHIFTBUFBIS[base->txShifterIndex] = (data << (32U - bitWidth));
base->flexioBase->SHIFTBUFBIS[base->txShifterIndex] = data << (32U - bitWidth);
data = 0;
}
}
@ -89,7 +88,7 @@ static void FLEXIO_I2S_ReadNonBlocking(FLEXIO_I2S_Type *base, uint8_t bitWidth,
for (i = 0; i < size / bytesPerWord; i++)
{
data = (base->flexioBase->SHIFTBUFBIS[base->rxShifterIndex] >> (32U - bitWidth));
data = (base->flexioBase->SHIFTBUFBIS[base->rxShifterIndex]);
for (j = 0; j < bytesPerWord; j++)
{
*rxData = (data >> (8U * j)) & 0xFF;
@ -98,6 +97,20 @@ static void FLEXIO_I2S_ReadNonBlocking(FLEXIO_I2S_Type *base, uint8_t bitWidth,
}
}
/*!
* brief Initializes the FlexIO I2S.
*
* This API configures FlexIO pins and shifter to I2S and configures the FlexIO I2S with a configuration structure.
* The configuration structure can be filled by the user, or be set with default values by
* FLEXIO_I2S_GetDefaultConfig().
*
* note This API should be called at the beginning of the application to use
* the FlexIO I2S driver. Otherwise, any access to the FlexIO I2S module can cause hard fault
* because the clock is not enabled.
*
* param base FlexIO I2S base pointer
* param config FlexIO I2S configure structure.
*/
void FLEXIO_I2S_Init(FLEXIO_I2S_Type *base, const flexio_i2s_config_t *config)
{
assert(base && config);
@ -110,6 +123,9 @@ void FLEXIO_I2S_Init(FLEXIO_I2S_Type *base, const flexio_i2s_config_t *config)
CLOCK_EnableClock(s_flexioClocks[FLEXIO_I2S_GetInstance(base)]);
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
/* reset Flexio */
FLEXIO_Reset(base->flexioBase);
/* Set shifter for I2S Tx data */
shifterConfig.timerSelect = base->bclkTimerIndex;
shifterConfig.pinSelect = base->txPinIndex;
@ -228,8 +244,20 @@ void FLEXIO_I2S_Init(FLEXIO_I2S_Type *base, const flexio_i2s_config_t *config)
}
}
/*!
* brief Sets the FlexIO I2S configuration structure to default values.
*
* The purpose of this API is to get the configuration structure initialized for use in FLEXIO_I2S_Init().
* Users may use the initialized structure unchanged in FLEXIO_I2S_Init() or modify
* some fields of the structure before calling FLEXIO_I2S_Init().
*
* param config pointer to master configuration structure
*/
void FLEXIO_I2S_GetDefaultConfig(flexio_i2s_config_t *config)
{
/* Initializes the configure structure to zero. */
memset(config, 0, sizeof(*config));
config->masterSlave = kFLEXIO_I2S_Master;
config->enableI2S = true;
config->txPinPolarity = kFLEXIO_PinActiveHigh;
@ -240,6 +268,14 @@ void FLEXIO_I2S_GetDefaultConfig(flexio_i2s_config_t *config)
config->rxTimerPolarity = kFLEXIO_ShifterTimerPolarityOnNegitive;
}
/*!
* brief De-initializes the FlexIO I2S.
*
* Calling this API resets the FlexIO I2S shifter and timer config. After calling this API,
* call the FLEXO_I2S_Init to use the FlexIO I2S module.
*
* param base FlexIO I2S base pointer
*/
void FLEXIO_I2S_Deinit(FLEXIO_I2S_Type *base)
{
base->flexioBase->SHIFTCFG[base->txShifterIndex] = 0;
@ -254,6 +290,14 @@ void FLEXIO_I2S_Deinit(FLEXIO_I2S_Type *base)
base->flexioBase->TIMCTL[base->bclkTimerIndex] = 0;
}
/*!
* brief Enables the FlexIO I2S interrupt.
*
* This function enables the FlexIO UART interrupt.
*
* param base Pointer to FLEXIO_I2S_Type structure
* param mask interrupt source
*/
void FLEXIO_I2S_EnableInterrupts(FLEXIO_I2S_Type *base, uint32_t mask)
{
if (mask & kFLEXIO_I2S_TxDataRegEmptyInterruptEnable)
@ -266,6 +310,12 @@ void FLEXIO_I2S_EnableInterrupts(FLEXIO_I2S_Type *base, uint32_t mask)
}
}
/*!
* brief Gets the FlexIO I2S status flags.
*
* param base Pointer to FLEXIO_I2S_Type structure
* return Status flag, which are ORed by the enumerators in the _flexio_i2s_status_flags.
*/
uint32_t FLEXIO_I2S_GetStatusFlags(FLEXIO_I2S_Type *base)
{
uint32_t status = 0;
@ -276,6 +326,14 @@ uint32_t FLEXIO_I2S_GetStatusFlags(FLEXIO_I2S_Type *base)
return status;
}
/*!
* brief Disables the FlexIO I2S interrupt.
*
* This function enables the FlexIO UART interrupt.
*
* param base pointer to FLEXIO_I2S_Type structure
* param mask interrupt source
*/
void FLEXIO_I2S_DisableInterrupts(FLEXIO_I2S_Type *base, uint32_t mask)
{
if (mask & kFLEXIO_I2S_TxDataRegEmptyInterruptEnable)
@ -288,9 +346,19 @@ void FLEXIO_I2S_DisableInterrupts(FLEXIO_I2S_Type *base, uint32_t mask)
}
}
/*!
* brief Configures the FlexIO I2S audio format in master mode.
*
* Audio format can be changed in run-time of FlexIO I2S. This function configures the sample rate and audio data
* format to be transferred.
*
* param base Pointer to FLEXIO_I2S_Type structure
* param format Pointer to FlexIO I2S audio data format structure.
* param srcClock_Hz I2S master clock source frequency in Hz.
*/
void FLEXIO_I2S_MasterSetFormat(FLEXIO_I2S_Type *base, flexio_i2s_format_t *format, uint32_t srcClock_Hz)
{
uint32_t timDiv = srcClock_Hz / (format->sampleRate_Hz * 32U * 2U);
uint32_t timDiv = srcClock_Hz / (format->sampleRate_Hz * format->bitWidth * 2U);
uint32_t bclkDiv = 0;
/* Shall keep bclk and fs div an integer */
@ -299,22 +367,41 @@ void FLEXIO_I2S_MasterSetFormat(FLEXIO_I2S_Type *base, flexio_i2s_format_t *form
timDiv += 1U;
}
/* Set Frame sync timer cmp */
base->flexioBase->TIMCMP[base->fsTimerIndex] = FLEXIO_TIMCMP_CMP(32U * timDiv - 1U);
base->flexioBase->TIMCMP[base->fsTimerIndex] = FLEXIO_TIMCMP_CMP(format->bitWidth * timDiv - 1U);
/* Set bit clock timer cmp */
bclkDiv = ((timDiv / 2U - 1U) | (63U << 8U));
bclkDiv = ((timDiv / 2U - 1U) | ((format->bitWidth * 2U - 1U) << 8U));
base->flexioBase->TIMCMP[base->bclkTimerIndex] = FLEXIO_TIMCMP_CMP(bclkDiv);
}
/*!
* brief Configures the FlexIO I2S audio format in slave mode.
*
* Audio format can be changed in run-time of FlexIO I2S. This function configures the sample rate and audio data
* format to be transferred.
*
* param base Pointer to FLEXIO_I2S_Type structure
* param format Pointer to FlexIO I2S audio data format structure.
*/
void FLEXIO_I2S_SlaveSetFormat(FLEXIO_I2S_Type *base, flexio_i2s_format_t *format)
{
/* Set Frame sync timer cmp */
base->flexioBase->TIMCMP[base->fsTimerIndex] = FLEXIO_TIMCMP_CMP(32U * 4U - 3U);
base->flexioBase->TIMCMP[base->fsTimerIndex] = FLEXIO_TIMCMP_CMP(format->bitWidth * 4U - 3U);
/* Set bit clock timer cmp */
base->flexioBase->TIMCMP[base->bclkTimerIndex] = FLEXIO_TIMCMP_CMP(32U * 2U - 1U);
base->flexioBase->TIMCMP[base->bclkTimerIndex] = FLEXIO_TIMCMP_CMP(format->bitWidth * 2U - 1U);
}
/*!
* brief Sends data using a blocking method.
*
* note This function blocks via polling until data is ready to be sent.
*
* param base FlexIO I2S base pointer.
* param bitWidth How many bits in a audio word, usually 8/16/24/32 bits.
* param txData Pointer to the data to be written.
* param size Bytes to be written.
*/
void FLEXIO_I2S_WriteBlocking(FLEXIO_I2S_Type *base, uint8_t bitWidth, uint8_t *txData, size_t size)
{
uint32_t i = 0;
@ -337,6 +424,16 @@ void FLEXIO_I2S_WriteBlocking(FLEXIO_I2S_Type *base, uint8_t bitWidth, uint8_t *
}
}
/*!
* brief Receives a piece of data using a blocking method.
*
* note This function blocks via polling until data is ready to be sent.
*
* param base FlexIO I2S base pointer
* param bitWidth How many bits in a audio word, usually 8/16/24/32 bits.
* param rxData Pointer to the data to be read.
* param size Bytes to be read.
*/
void FLEXIO_I2S_ReadBlocking(FLEXIO_I2S_Type *base, uint8_t bitWidth, uint8_t *rxData, size_t size)
{
uint32_t i = 0;
@ -354,6 +451,18 @@ void FLEXIO_I2S_ReadBlocking(FLEXIO_I2S_Type *base, uint8_t bitWidth, uint8_t *r
}
}
/*!
* brief Initializes the FlexIO I2S handle.
*
* This function initializes the FlexIO I2S handle which can be used for other
* FlexIO I2S transactional APIs. Call this API once to get the
* initialized handle.
*
* param base Pointer to FLEXIO_I2S_Type structure
* param handle Pointer to flexio_i2s_handle_t structure to store the transfer state.
* param callback FlexIO I2S callback function, which is called while finished a block.
* param userData User parameter for the FlexIO I2S callback.
*/
void FLEXIO_I2S_TransferTxCreateHandle(FLEXIO_I2S_Type *base,
flexio_i2s_handle_t *handle,
flexio_i2s_callback_t callback,
@ -380,6 +489,18 @@ void FLEXIO_I2S_TransferTxCreateHandle(FLEXIO_I2S_Type *base,
EnableIRQ(flexio_irqs[FLEXIO_I2S_GetInstance(base)]);
}
/*!
* brief Initializes the FlexIO I2S receive handle.
*
* This function initializes the FlexIO I2S handle which can be used for other
* FlexIO I2S transactional APIs. Call this API once to get the
* initialized handle.
*
* param base Pointer to FLEXIO_I2S_Type structure.
* param handle Pointer to flexio_i2s_handle_t structure to store the transfer state.
* param callback FlexIO I2S callback function, which is called while finished a block.
* param userData User parameter for the FlexIO I2S callback.
*/
void FLEXIO_I2S_TransferRxCreateHandle(FLEXIO_I2S_Type *base,
flexio_i2s_handle_t *handle,
flexio_i2s_callback_t callback,
@ -406,6 +527,17 @@ void FLEXIO_I2S_TransferRxCreateHandle(FLEXIO_I2S_Type *base,
EnableIRQ(flexio_irqs[FLEXIO_I2S_GetInstance(base)]);
}
/*!
* brief Configures the FlexIO I2S audio format.
*
* Audio format can be changed at run-time of FlexIO I2S. This function configures the sample rate and audio data
* format to be transferred.
*
* param base Pointer to FLEXIO_I2S_Type structure.
* param handle FlexIO I2S handle pointer.
* param format Pointer to audio data format structure.
* param srcClock_Hz FlexIO I2S bit clock source frequency in Hz. This parameter should be 0 while in slave mode.
*/
void FLEXIO_I2S_TransferSetFormat(FLEXIO_I2S_Type *base,
flexio_i2s_handle_t *handle,
flexio_i2s_format_t *format,
@ -428,6 +560,20 @@ void FLEXIO_I2S_TransferSetFormat(FLEXIO_I2S_Type *base,
}
}
/*!
* brief Performs an interrupt non-blocking send transfer on FlexIO I2S.
*
* note The API returns immediately after transfer initiates.
* Call FLEXIO_I2S_GetRemainingBytes to poll the transfer status and check whether
* the transfer is finished. If the return status is 0, the transfer is finished.
*
* param base Pointer to FLEXIO_I2S_Type structure.
* param handle Pointer to flexio_i2s_handle_t structure which stores the transfer state
* param xfer Pointer to flexio_i2s_transfer_t structure
* retval kStatus_Success Successfully start the data transmission.
* retval kStatus_FLEXIO_I2S_TxBusy Previous transmission still not finished, data not all written to TX register yet.
* retval kStatus_InvalidArgument The input parameter is invalid.
*/
status_t FLEXIO_I2S_TransferSendNonBlocking(FLEXIO_I2S_Type *base,
flexio_i2s_handle_t *handle,
flexio_i2s_transfer_t *xfer)
@ -461,6 +607,20 @@ status_t FLEXIO_I2S_TransferSendNonBlocking(FLEXIO_I2S_Type *base,
return kStatus_Success;
}
/*!
* brief Performs an interrupt non-blocking receive transfer on FlexIO I2S.
*
* note The API returns immediately after transfer initiates.
* Call FLEXIO_I2S_GetRemainingBytes to poll the transfer status to check whether
* the transfer is finished. If the return status is 0, the transfer is finished.
*
* param base Pointer to FLEXIO_I2S_Type structure.
* param handle Pointer to flexio_i2s_handle_t structure which stores the transfer state
* param xfer Pointer to flexio_i2s_transfer_t structure
* retval kStatus_Success Successfully start the data receive.
* retval kStatus_FLEXIO_I2S_RxBusy Previous receive still not finished.
* retval kStatus_InvalidArgument The input parameter is invalid.
*/
status_t FLEXIO_I2S_TransferReceiveNonBlocking(FLEXIO_I2S_Type *base,
flexio_i2s_handle_t *handle,
flexio_i2s_transfer_t *xfer)
@ -496,6 +656,15 @@ status_t FLEXIO_I2S_TransferReceiveNonBlocking(FLEXIO_I2S_Type *base,
return kStatus_Success;
}
/*!
* brief Aborts the current send.
*
* note This API can be called at any time when interrupt non-blocking transfer initiates
* to abort the transfer in a early time.
*
* param base Pointer to FLEXIO_I2S_Type structure.
* param handle Pointer to flexio_i2s_handle_t structure which stores the transfer state
*/
void FLEXIO_I2S_TransferAbortSend(FLEXIO_I2S_Type *base, flexio_i2s_handle_t *handle)
{
assert(handle);
@ -510,6 +679,15 @@ void FLEXIO_I2S_TransferAbortSend(FLEXIO_I2S_Type *base, flexio_i2s_handle_t *ha
handle->queueUser = 0;
}
/*!
* brief Aborts the current receive.
*
* note This API can be called at any time when interrupt non-blocking transfer initiates
* to abort the transfer in a early time.
*
* param base Pointer to FLEXIO_I2S_Type structure.
* param handle Pointer to flexio_i2s_handle_t structure which stores the transfer state
*/
void FLEXIO_I2S_TransferAbortReceive(FLEXIO_I2S_Type *base, flexio_i2s_handle_t *handle)
{
assert(handle);
@ -524,6 +702,15 @@ void FLEXIO_I2S_TransferAbortReceive(FLEXIO_I2S_Type *base, flexio_i2s_handle_t
handle->queueUser = 0;
}
/*!
* brief Gets the remaining bytes to be sent.
*
* param base Pointer to FLEXIO_I2S_Type structure.
* param handle Pointer to flexio_i2s_handle_t structure which stores the transfer state
* param count Bytes sent.
* retval kStatus_Success Succeed get the transfer count.
* retval kStatus_NoTransferInProgress There is not a non-blocking transaction currently in progress.
*/
status_t FLEXIO_I2S_TransferGetSendCount(FLEXIO_I2S_Type *base, flexio_i2s_handle_t *handle, size_t *count)
{
assert(handle);
@ -542,6 +729,15 @@ status_t FLEXIO_I2S_TransferGetSendCount(FLEXIO_I2S_Type *base, flexio_i2s_handl
return status;
}
/*!
* brief Gets the remaining bytes to be received.
*
* param base Pointer to FLEXIO_I2S_Type structure.
* param handle Pointer to flexio_i2s_handle_t structure which stores the transfer state
* return count Bytes received.
* retval kStatus_Success Succeed get the transfer count.
* retval kStatus_NoTransferInProgress There is not a non-blocking transaction currently in progress.
*/
status_t FLEXIO_I2S_TransferGetReceiveCount(FLEXIO_I2S_Type *base, flexio_i2s_handle_t *handle, size_t *count)
{
assert(handle);
@ -560,6 +756,12 @@ status_t FLEXIO_I2S_TransferGetReceiveCount(FLEXIO_I2S_Type *base, flexio_i2s_ha
return status;
}
/*!
* brief Tx interrupt handler.
*
* param i2sBase Pointer to FLEXIO_I2S_Type structure.
* param i2sHandle Pointer to flexio_i2s_handle_t structure
*/
void FLEXIO_I2S_TransferTxHandleIRQ(void *i2sBase, void *i2sHandle)
{
assert(i2sHandle);
@ -603,6 +805,12 @@ void FLEXIO_I2S_TransferTxHandleIRQ(void *i2sBase, void *i2sHandle)
}
}
/*!
* brief Rx interrupt handler.
*
* param i2sBase Pointer to FLEXIO_I2S_Type structure.
* param i2sHandle Pointer to flexio_i2s_handle_t structure.
*/
void FLEXIO_I2S_TransferRxHandleIRQ(void *i2sBase, void *i2sHandle)
{
assert(i2sHandle);

8
ext/hal/nxp/mcux/drivers/imx/fsl_flexio_i2s.h
View file

@ -1,8 +1,8 @@
/*
* Copyright (c) 2015, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
* Copyright 2016-2018 NXP
* All rights reserved.
*
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _FSL_FLEXIO_I2S_H_
@ -22,8 +22,8 @@
/*! @name Driver version */
/*@{*/
/*! @brief FlexIO I2S driver version 2.1.4. */
#define FSL_FLEXIO_I2S_DRIVER_VERSION (MAKE_VERSION(2, 1, 4))
/*! @brief FlexIO I2S driver version 2.1.6. */
#define FSL_FLEXIO_I2S_DRIVER_VERSION (MAKE_VERSION(2, 1, 6))
/*@}*/
/*! @brief FlexIO I2S transfer status */

103
ext/hal/nxp/mcux/drivers/imx/fsl_flexio_i2s_edma.c
View file

@ -1,8 +1,8 @@
/*
* Copyright (c) 2015, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
* Copyright 2016-2018 NXP
* All rights reserved.
*
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -13,7 +13,6 @@
#define FSL_COMPONENT_ID "platform.drivers.flexio_i2s_edma"
#endif
/*******************************************************************************
* Definitations
******************************************************************************/
@ -102,6 +101,19 @@ static void FLEXIO_I2S_RxEDMACallback(edma_handle_t *handle, void *userData, boo
}
}
/*!
* brief Initializes the FlexIO I2S eDMA handle.
*
* This function initializes the FlexIO I2S master DMA handle which can be used for other FlexIO I2S master
* transactional APIs.
* Usually, for a specified FlexIO I2S instance, call this API once to get the initialized handle.
*
* param base FlexIO I2S peripheral base address.
* param handle FlexIO I2S eDMA handle pointer.
* param callback FlexIO I2S eDMA callback function called while finished a block.
* param userData User parameter for callback.
* param dmaHandle eDMA handle for FlexIO I2S. This handle is a static value allocated by users.
*/
void FLEXIO_I2S_TransferTxCreateHandleEDMA(FLEXIO_I2S_Type *base,
flexio_i2s_edma_handle_t *handle,
flexio_i2s_edma_callback_t callback,
@ -131,6 +143,19 @@ void FLEXIO_I2S_TransferTxCreateHandleEDMA(FLEXIO_I2S_Type *base,
EDMA_SetCallback(dmaHandle, FLEXIO_I2S_TxEDMACallback, &s_edmaPrivateHandle[0]);
}
/*!
* brief Initializes the FlexIO I2S Rx eDMA handle.
*
* This function initializes the FlexIO I2S slave DMA handle which can be used for other FlexIO I2S master transactional
* APIs.
* Usually, for a specified FlexIO I2S instance, call this API once to get the initialized handle.
*
* param base FlexIO I2S peripheral base address.
* param handle FlexIO I2S eDMA handle pointer.
* param callback FlexIO I2S eDMA callback function called while finished a block.
* param userData User parameter for callback.
* param dmaHandle eDMA handle for FlexIO I2S. This handle is a static value allocated by users.
*/
void FLEXIO_I2S_TransferRxCreateHandleEDMA(FLEXIO_I2S_Type *base,
flexio_i2s_edma_handle_t *handle,
flexio_i2s_edma_callback_t callback,
@ -160,6 +185,19 @@ void FLEXIO_I2S_TransferRxCreateHandleEDMA(FLEXIO_I2S_Type *base,
EDMA_SetCallback(dmaHandle, FLEXIO_I2S_RxEDMACallback, &s_edmaPrivateHandle[1]);
}
/*!
* brief Configures the FlexIO I2S Tx audio format.
*
* Audio format can be changed in run-time of FlexIO I2S. This function configures the sample rate and audio data
* format to be transferred. This function also sets the eDMA parameter according to format.
*
* param base FlexIO I2S peripheral base address.
* param handle FlexIO I2S eDMA handle pointer
* param format Pointer to FlexIO I2S audio data format structure.
* param srcClock_Hz FlexIO I2S clock source frequency in Hz, it should be 0 while in slave mode.
* retval kStatus_Success Audio format set successfully.
* retval kStatus_InvalidArgument The input arguments is invalid.
*/
void FLEXIO_I2S_TransferSetFormatEDMA(FLEXIO_I2S_Type *base,
flexio_i2s_edma_handle_t *handle,
flexio_i2s_format_t *format,
@ -182,6 +220,19 @@ void FLEXIO_I2S_TransferSetFormatEDMA(FLEXIO_I2S_Type *base,
handle->bytesPerFrame = format->bitWidth / 8U;
}
/*!
* brief Performs a non-blocking FlexIO I2S transfer using DMA.
*
* note This interface returned immediately after transfer initiates. Users should call
* FLEXIO_I2S_GetTransferStatus to poll the transfer status and check whether the FlexIO I2S transfer is finished.
*
* param base FlexIO I2S peripheral base address.
* param handle FlexIO I2S DMA handle pointer.
* param xfer Pointer to DMA transfer structure.
* retval kStatus_Success Start a FlexIO I2S eDMA send successfully.
* retval kStatus_InvalidArgument The input arguments is invalid.
* retval kStatus_TxBusy FlexIO I2S is busy sending data.
*/
status_t FLEXIO_I2S_TransferSendEDMA(FLEXIO_I2S_Type *base,
flexio_i2s_edma_handle_t *handle,
flexio_i2s_transfer_t *xfer)
@ -232,6 +283,20 @@ status_t FLEXIO_I2S_TransferSendEDMA(FLEXIO_I2S_Type *base,
return kStatus_Success;
}
/*!
* brief Performs a non-blocking FlexIO I2S receive using eDMA.
*
* note This interface returned immediately after transfer initiates. Users should call
* FLEXIO_I2S_GetReceiveRemainingBytes to poll the transfer status and check whether the FlexIO I2S transfer is
* finished.
*
* param base FlexIO I2S peripheral base address.
* param handle FlexIO I2S DMA handle pointer.
* param xfer Pointer to DMA transfer structure.
* retval kStatus_Success Start a FlexIO I2S eDMA receive successfully.
* retval kStatus_InvalidArgument The input arguments is invalid.
* retval kStatus_RxBusy FlexIO I2S is busy receiving data.
*/
status_t FLEXIO_I2S_TransferReceiveEDMA(FLEXIO_I2S_Type *base,
flexio_i2s_edma_handle_t *handle,
flexio_i2s_transfer_t *xfer)
@ -239,7 +304,7 @@ status_t FLEXIO_I2S_TransferReceiveEDMA(FLEXIO_I2S_Type *base,
assert(handle && xfer);
edma_transfer_config_t config = {0};
uint32_t srcAddr = FLEXIO_I2S_RxGetDataRegisterAddress(base) + (4U - handle->bytesPerFrame);
uint32_t srcAddr = FLEXIO_I2S_RxGetDataRegisterAddress(base);
/* Check if input parameter invalid */
if ((xfer->data == NULL) || (xfer->dataSize == 0U))
@ -282,6 +347,12 @@ status_t FLEXIO_I2S_TransferReceiveEDMA(FLEXIO_I2S_Type *base,
return kStatus_Success;
}
/*!
* brief Aborts a FlexIO I2S transfer using eDMA.
*
* param base FlexIO I2S peripheral base address.
* param handle FlexIO I2S DMA handle pointer.
*/
void FLEXIO_I2S_TransferAbortSendEDMA(FLEXIO_I2S_Type *base, flexio_i2s_edma_handle_t *handle)
{
assert(handle);
@ -296,6 +367,12 @@ void FLEXIO_I2S_TransferAbortSendEDMA(FLEXIO_I2S_Type *base, flexio_i2s_edma_han
handle->state = kFLEXIO_I2S_Idle;
}
/*!
* brief Aborts a FlexIO I2S receive using eDMA.
*
* param base FlexIO I2S peripheral base address.
* param handle FlexIO I2S DMA handle pointer.
*/
void FLEXIO_I2S_TransferAbortReceiveEDMA(FLEXIO_I2S_Type *base, flexio_i2s_edma_handle_t *handle)
{
assert(handle);
@ -310,6 +387,15 @@ void FLEXIO_I2S_TransferAbortReceiveEDMA(FLEXIO_I2S_Type *base, flexio_i2s_edma_
handle->state = kFLEXIO_I2S_Idle;
}
/*!
* brief Gets the remaining bytes to be sent.
*
* param base FlexIO I2S peripheral base address.
* param handle FlexIO I2S DMA handle pointer.
* param count Bytes sent.
* retval kStatus_Success Succeed get the transfer count.
* retval kStatus_NoTransferInProgress There is not a non-blocking transaction currently in progress.
*/
status_t FLEXIO_I2S_TransferGetSendCountEDMA(FLEXIO_I2S_Type *base, flexio_i2s_edma_handle_t *handle, size_t *count)
{
assert(handle);
@ -330,6 +416,15 @@ status_t FLEXIO_I2S_TransferGetSendCountEDMA(FLEXIO_I2S_Type *base, flexio_i2s_e
return status;
}
/*!
* brief Get the remaining bytes to be received.
*
* param base FlexIO I2S peripheral base address.
* param handle FlexIO I2S DMA handle pointer.
* param count Bytes received.
* retval kStatus_Success Succeed get the transfer count.
* retval kStatus_NoTransferInProgress There is not a non-blocking transaction currently in progress.
*/
status_t FLEXIO_I2S_TransferGetReceiveCountEDMA(FLEXIO_I2S_Type *base, flexio_i2s_edma_handle_t *handle, size_t *count)
{
assert(handle);

8
ext/hal/nxp/mcux/drivers/imx/fsl_flexio_i2s_edma.h
View file

@ -1,8 +1,8 @@
/*
* Copyright (c) 2015, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
* Copyright 2016-2018 NXP
* All rights reserved.
*
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _FSL_FLEXIO_I2S_EDMA_H_
@ -22,8 +22,8 @@
/*! @name Driver version */
/*@{*/
/*! @brief FlexIO I2S EDMA driver version 2.1.4. */
#define FSL_FLEXIO_I2S_EDMA_DRIVER_VERSION (MAKE_VERSION(2, 1, 4))
/*! @brief FlexIO I2S EDMA driver version 2.1.5. */
#define FSL_FLEXIO_I2S_EDMA_DRIVER_VERSION (MAKE_VERSION(2, 1, 5))
/*@}*/
typedef struct _flexio_i2s_edma_handle flexio_i2s_edma_handle_t;

264
ext/hal/nxp/mcux/drivers/imx/fsl_flexio_spi.c
View file

@ -2,7 +2,7 @@
* Copyright (c) 2015, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
* All rights reserved.
*
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -17,7 +17,6 @@
#define FSL_COMPONENT_ID "platform.drivers.flexio_spi"
#endif
/*! @brief FLEXIO SPI transfer state, which is used for SPI transactiaonl APIs' internal state. */
enum _flexio_spi_transfer_states
{
@ -137,6 +136,42 @@ static void FLEXIO_SPI_TransferReceiveTransaction(FLEXIO_SPI_Type *base, flexio_
handle->rxRemainingBytes -= handle->bytePerFrame;
}
/*!
* brief Ungates the FlexIO clock, resets the FlexIO module, configures the FlexIO SPI master hardware,
* and configures the FlexIO SPI with FlexIO SPI master configuration. The
* configuration structure can be filled by the user, or be set with default values
* by the FLEXIO_SPI_MasterGetDefaultConfig().
*
* note FlexIO SPI master only support CPOL = 0, which means clock inactive low.
*
* Example
code
FLEXIO_SPI_Type spiDev = {
.flexioBase = FLEXIO,
.SDOPinIndex = 0,
.SDIPinIndex = 1,
.SCKPinIndex = 2,
.CSnPinIndex = 3,
.shifterIndex = {0,1},
.timerIndex = {0,1}
};
flexio_spi_master_config_t config = {
.enableMaster = true,
.enableInDoze = false,
.enableInDebug = true,
.enableFastAccess = false,
.baudRate_Bps = 500000,
.phase = kFLEXIO_SPI_ClockPhaseFirstEdge,
.direction = kFLEXIO_SPI_MsbFirst,
.dataMode = kFLEXIO_SPI_8BitMode
};
FLEXIO_SPI_MasterInit(&spiDev, &config, srcClock_Hz);
endcode
*
* param base Pointer to the FLEXIO_SPI_Type structure.
* param masterConfig Pointer to the flexio_spi_master_config_t structure.
* param srcClock_Hz FlexIO source clock in Hz.
*/
void FLEXIO_SPI_MasterInit(FLEXIO_SPI_Type *base, flexio_spi_master_config_t *masterConfig, uint32_t srcClock_Hz)
{
assert(base);
@ -259,6 +294,11 @@ void FLEXIO_SPI_MasterInit(FLEXIO_SPI_Type *base, flexio_spi_master_config_t *ma
FLEXIO_SetTimerConfig(base->flexioBase, base->timerIndex[1], &timerConfig);
}
/*!
* brief Resets the FlexIO SPI timer and shifter config.
*
* param base Pointer to the FLEXIO_SPI_Type.
*/
void FLEXIO_SPI_MasterDeinit(FLEXIO_SPI_Type *base)
{
base->flexioBase->SHIFTCFG[base->shifterIndex[0]] = 0;
@ -273,10 +313,23 @@ void FLEXIO_SPI_MasterDeinit(FLEXIO_SPI_Type *base)
base->flexioBase->TIMCTL[base->timerIndex[1]] = 0;
}
/*!
* brief Gets the default configuration to configure the FlexIO SPI master. The configuration
* can be used directly by calling the FLEXIO_SPI_MasterConfigure().
* Example:
code
flexio_spi_master_config_t masterConfig;
FLEXIO_SPI_MasterGetDefaultConfig(&masterConfig);
endcode
* param masterConfig Pointer to the flexio_spi_master_config_t structure.
*/
void FLEXIO_SPI_MasterGetDefaultConfig(flexio_spi_master_config_t *masterConfig)
{
assert(masterConfig);
/* Initializes the configure structure to zero. */
memset(masterConfig, 0, sizeof(*masterConfig));
masterConfig->enableMaster = true;
masterConfig->enableInDoze = false;
masterConfig->enableInDebug = true;
@ -289,6 +342,39 @@ void FLEXIO_SPI_MasterGetDefaultConfig(flexio_spi_master_config_t *masterConfig)
masterConfig->dataMode = kFLEXIO_SPI_8BitMode;
}
/*!
* brief Ungates the FlexIO clock, resets the FlexIO module, configures the FlexIO SPI slave hardware
* configuration, and configures the FlexIO SPI with FlexIO SPI slave configuration. The
* configuration structure can be filled by the user, or be set with default values
* by the FLEXIO_SPI_SlaveGetDefaultConfig().
*
* note Only one timer is needed in the FlexIO SPI slave. As a result, the second timer index is ignored.
* FlexIO SPI slave only support CPOL = 0, which means clock inactive low.
* Example
code
FLEXIO_SPI_Type spiDev = {
.flexioBase = FLEXIO,
.SDOPinIndex = 0,
.SDIPinIndex = 1,
.SCKPinIndex = 2,
.CSnPinIndex = 3,
.shifterIndex = {0,1},
.timerIndex = {0}
};
flexio_spi_slave_config_t config = {
.enableSlave = true,
.enableInDoze = false,
.enableInDebug = true,
.enableFastAccess = false,
.phase = kFLEXIO_SPI_ClockPhaseFirstEdge,
.direction = kFLEXIO_SPI_MsbFirst,
.dataMode = kFLEXIO_SPI_8BitMode
};
FLEXIO_SPI_SlaveInit(&spiDev, &config);
endcode
* param base Pointer to the FLEXIO_SPI_Type structure.
* param slaveConfig Pointer to the flexio_spi_slave_config_t structure.
*/
void FLEXIO_SPI_SlaveInit(FLEXIO_SPI_Type *base, flexio_spi_slave_config_t *slaveConfig)
{
assert(base && slaveConfig);
@ -391,15 +477,33 @@ void FLEXIO_SPI_SlaveInit(FLEXIO_SPI_Type *base, flexio_spi_slave_config_t *slav
FLEXIO_SetTimerConfig(base->flexioBase, base->timerIndex[0], &timerConfig);
}
/*!
* brief Gates the FlexIO clock.
*
* param base Pointer to the FLEXIO_SPI_Type.
*/
void FLEXIO_SPI_SlaveDeinit(FLEXIO_SPI_Type *base)
{
FLEXIO_SPI_MasterDeinit(base);
}
/*!
* brief Gets the default configuration to configure the FlexIO SPI slave. The configuration
* can be used directly for calling the FLEXIO_SPI_SlaveConfigure().
* Example:
code
flexio_spi_slave_config_t slaveConfig;
FLEXIO_SPI_SlaveGetDefaultConfig(&slaveConfig);
endcode
* param slaveConfig Pointer to the flexio_spi_slave_config_t structure.
*/
void FLEXIO_SPI_SlaveGetDefaultConfig(flexio_spi_slave_config_t *slaveConfig)
{
assert(slaveConfig);
/* Initializes the configure structure to zero. */
memset(slaveConfig, 0, sizeof(*slaveConfig));
slaveConfig->enableSlave = true;
slaveConfig->enableInDoze = false;
slaveConfig->enableInDebug = true;
@ -410,6 +514,16 @@ void FLEXIO_SPI_SlaveGetDefaultConfig(flexio_spi_slave_config_t *slaveConfig)
slaveConfig->dataMode = kFLEXIO_SPI_8BitMode;
}
/*!
* brief Enables the FlexIO SPI interrupt.
*
* This function enables the FlexIO SPI interrupt.
*
* param base Pointer to the FLEXIO_SPI_Type structure.
* param mask interrupt source. The parameter can be any combination of the following values:
* arg kFLEXIO_SPI_RxFullInterruptEnable
* arg kFLEXIO_SPI_TxEmptyInterruptEnable
*/
void FLEXIO_SPI_EnableInterrupts(FLEXIO_SPI_Type *base, uint32_t mask)
{
if (mask & kFLEXIO_SPI_TxEmptyInterruptEnable)
@ -422,6 +536,16 @@ void FLEXIO_SPI_EnableInterrupts(FLEXIO_SPI_Type *base, uint32_t mask)
}
}
/*!
* brief Disables the FlexIO SPI interrupt.
*
* This function disables the FlexIO SPI interrupt.
*
* param base Pointer to the FLEXIO_SPI_Type structure.
* param mask interrupt source The parameter can be any combination of the following values:
* arg kFLEXIO_SPI_RxFullInterruptEnable
* arg kFLEXIO_SPI_TxEmptyInterruptEnable
*/
void FLEXIO_SPI_DisableInterrupts(FLEXIO_SPI_Type *base, uint32_t mask)
{
if (mask & kFLEXIO_SPI_TxEmptyInterruptEnable)
@ -434,6 +558,14 @@ void FLEXIO_SPI_DisableInterrupts(FLEXIO_SPI_Type *base, uint32_t mask)
}
}
/*!
* brief Enables/disables the FlexIO SPI transmit DMA. This function enables/disables the FlexIO SPI Tx DMA,
* which means that asserting the kFLEXIO_SPI_TxEmptyFlag does/doesn't trigger the DMA request.
*
* param base Pointer to the FLEXIO_SPI_Type structure.
* param mask SPI DMA source.
* param enable True means enable DMA, false means disable DMA.
*/
void FLEXIO_SPI_EnableDMA(FLEXIO_SPI_Type *base, uint32_t mask, bool enable)
{
if (mask & kFLEXIO_SPI_TxDmaEnable)
@ -447,6 +579,15 @@ void FLEXIO_SPI_EnableDMA(FLEXIO_SPI_Type *base, uint32_t mask, bool enable)
}
}
/*!
* brief Gets FlexIO SPI status flags.
*
* param base Pointer to the FLEXIO_SPI_Type structure.
* return status flag; Use the status flag to AND the following flag mask and get the status.
* arg kFLEXIO_SPI_TxEmptyFlag
* arg kFLEXIO_SPI_RxEmptyFlag
*/
uint32_t FLEXIO_SPI_GetStatusFlags(FLEXIO_SPI_Type *base)
{
uint32_t shifterStatus = FLEXIO_GetShifterStatusFlags(base->flexioBase);
@ -458,6 +599,16 @@ uint32_t FLEXIO_SPI_GetStatusFlags(FLEXIO_SPI_Type *base)
return status;
}
/*!
* brief Clears FlexIO SPI status flags.
*
* param base Pointer to the FLEXIO_SPI_Type structure.
* param mask status flag
* The parameter can be any combination of the following values:
* arg kFLEXIO_SPI_TxEmptyFlag
* arg kFLEXIO_SPI_RxEmptyFlag
*/
void FLEXIO_SPI_ClearStatusFlags(FLEXIO_SPI_Type *base, uint32_t mask)
{
if (mask & kFLEXIO_SPI_TxBufferEmptyFlag)
@ -470,6 +621,13 @@ void FLEXIO_SPI_ClearStatusFlags(FLEXIO_SPI_Type *base, uint32_t mask)
}
}
/*!
* brief Sets baud rate for the FlexIO SPI transfer, which is only used for the master.
*
* param base Pointer to the FLEXIO_SPI_Type structure.
* param baudRate_Bps Baud Rate needed in Hz.
* param srcClockHz SPI source clock frequency in Hz.
*/
void FLEXIO_SPI_MasterSetBaudRate(FLEXIO_SPI_Type *base, uint32_t baudRate_Bps, uint32_t srcClockHz)
{
uint16_t timerDiv = 0;
@ -487,6 +645,16 @@ void FLEXIO_SPI_MasterSetBaudRate(FLEXIO_SPI_Type *base, uint32_t baudRate_Bps,
flexioBase->TIMCMP[base->timerIndex[0]] = timerCmp;
}
/*!
* brief Sends a buffer of data bytes.
*
* note This function blocks using the polling method until all bytes have been sent.
*
* param base Pointer to the FLEXIO_SPI_Type structure.
* param direction Shift direction of MSB first or LSB first.
* param buffer The data bytes to send.
* param size The number of data bytes to send.
*/
void FLEXIO_SPI_WriteBlocking(FLEXIO_SPI_Type *base,
flexio_spi_shift_direction_t direction,
const uint8_t *buffer,
@ -505,6 +673,17 @@ void FLEXIO_SPI_WriteBlocking(FLEXIO_SPI_Type *base,
}
}
/*!
* brief Receives a buffer of bytes.
*
* note This function blocks using the polling method until all bytes have been received.
*
* param base Pointer to the FLEXIO_SPI_Type structure.
* param direction Shift direction of MSB first or LSB first.
* param buffer The buffer to store the received bytes.
* param size The number of data bytes to be received.
* param direction Shift direction of MSB first or LSB first.
*/
void FLEXIO_SPI_ReadBlocking(FLEXIO_SPI_Type *base,
flexio_spi_shift_direction_t direction,
uint8_t *buffer,
@ -523,6 +702,14 @@ void FLEXIO_SPI_ReadBlocking(FLEXIO_SPI_Type *base,
}
}
/*!
* brief Receives a buffer of bytes.
*
* note This function blocks via polling until all bytes have been received.
*
* param base pointer to FLEXIO_SPI_Type structure
* param xfer FlexIO SPI transfer structure, see #flexio_spi_transfer_t.
*/
void FLEXIO_SPI_MasterTransferBlocking(FLEXIO_SPI_Type *base, flexio_spi_transfer_t *xfer)
{
flexio_spi_shift_direction_t direction;
@ -638,6 +825,16 @@ void FLEXIO_SPI_MasterTransferBlocking(FLEXIO_SPI_Type *base, flexio_spi_transfe
}
}
/*!
* brief Initializes the FlexIO SPI Master handle, which is used in transactional functions.
*
* param base Pointer to the FLEXIO_SPI_Type structure.
* param handle Pointer to the flexio_spi_master_handle_t structure to store the transfer state.
* param callback The callback function.
* param userData The parameter of the callback function.
* retval kStatus_Success Successfully create the handle.
* retval kStatus_OutOfRange The FlexIO type/handle/ISR table out of range.
*/
status_t FLEXIO_SPI_MasterTransferCreateHandle(FLEXIO_SPI_Type *base,
flexio_spi_master_handle_t *handle,
flexio_spi_master_transfer_callback_t callback,
@ -661,6 +858,19 @@ status_t FLEXIO_SPI_MasterTransferCreateHandle(FLEXIO_SPI_Type *base,
return FLEXIO_RegisterHandleIRQ(base, handle, FLEXIO_SPI_MasterTransferHandleIRQ);
}
/*!
* brief Master transfer data using IRQ.
*
* This function sends data using IRQ. This is a non-blocking function, which returns
* right away. When all data is sent out/received, the callback function is called.
*
* param base Pointer to the FLEXIO_SPI_Type structure.
* param handle Pointer to the flexio_spi_master_handle_t structure to store the transfer state.
* param xfer FlexIO SPI transfer structure. See #flexio_spi_transfer_t.
* retval kStatus_Success Successfully start a transfer.
* retval kStatus_InvalidArgument Input argument is invalid.
* retval kStatus_FLEXIO_SPI_Busy SPI is not idle, is running another transfer.
*/
status_t FLEXIO_SPI_MasterTransferNonBlocking(FLEXIO_SPI_Type *base,
flexio_spi_master_handle_t *handle,
flexio_spi_transfer_t *xfer)
@ -769,6 +979,15 @@ status_t FLEXIO_SPI_MasterTransferNonBlocking(FLEXIO_SPI_Type *base,
return kStatus_Success;
}
/*!
* brief Gets the data transfer status which used IRQ.
*
* param base Pointer to the FLEXIO_SPI_Type structure.
* param handle Pointer to the flexio_spi_master_handle_t structure to store the transfer state.
* param count Number of bytes transferred so far by the non-blocking transaction.
* retval kStatus_InvalidArgument count is Invalid.
* retval kStatus_Success Successfully return the count.
*/
status_t FLEXIO_SPI_MasterTransferGetCount(FLEXIO_SPI_Type *base, flexio_spi_master_handle_t *handle, size_t *count)
{
assert(handle);
@ -791,6 +1010,12 @@ status_t FLEXIO_SPI_MasterTransferGetCount(FLEXIO_SPI_Type *base, flexio_spi_mas
return kStatus_Success;
}
/*!
* brief Aborts the master data transfer, which used IRQ.
*
* param base Pointer to the FLEXIO_SPI_Type structure.
* param handle Pointer to the flexio_spi_master_handle_t structure to store the transfer state.
*/
void FLEXIO_SPI_MasterTransferAbort(FLEXIO_SPI_Type *base, flexio_spi_master_handle_t *handle)
{
assert(handle);
@ -806,6 +1031,12 @@ void FLEXIO_SPI_MasterTransferAbort(FLEXIO_SPI_Type *base, flexio_spi_master_han
handle->txRemainingBytes = 0;
}
/*!
* brief FlexIO SPI master IRQ handler function.
*
* param spiType Pointer to the FLEXIO_SPI_Type structure.
* param spiHandle Pointer to the flexio_spi_master_handle_t structure to store the transfer state.
*/
void FLEXIO_SPI_MasterTransferHandleIRQ(void *spiType, void *spiHandle)
{
assert(spiHandle);
@ -845,6 +1076,16 @@ void FLEXIO_SPI_MasterTransferHandleIRQ(void *spiType, void *spiHandle)
}
}
/*!
* brief Initializes the FlexIO SPI Slave handle, which is used in transactional functions.
*
* param base Pointer to the FLEXIO_SPI_Type structure.
* param handle Pointer to the flexio_spi_slave_handle_t structure to store the transfer state.
* param callback The callback function.
* param userData The parameter of the callback function.
* retval kStatus_Success Successfully create the handle.
* retval kStatus_OutOfRange The FlexIO type/handle/ISR table out of range.
*/
status_t FLEXIO_SPI_SlaveTransferCreateHandle(FLEXIO_SPI_Type *base,
flexio_spi_slave_handle_t *handle,
flexio_spi_slave_transfer_callback_t callback,
@ -868,6 +1109,19 @@ status_t FLEXIO_SPI_SlaveTransferCreateHandle(FLEXIO_SPI_Type *base,
return FLEXIO_RegisterHandleIRQ(base, handle, FLEXIO_SPI_SlaveTransferHandleIRQ);
}
/*!
* brief Slave transfer data using IRQ.
*
* This function sends data using IRQ. This is a non-blocking function, which returns
* right away. When all data is sent out/received, the callback function is called.
* param handle Pointer to the flexio_spi_slave_handle_t structure to store the transfer state.
*
* param base Pointer to the FLEXIO_SPI_Type structure.
* param xfer FlexIO SPI transfer structure. See #flexio_spi_transfer_t.
* retval kStatus_Success Successfully start a transfer.
* retval kStatus_InvalidArgument Input argument is invalid.
* retval kStatus_FLEXIO_SPI_Busy SPI is not idle; it is running another transfer.
*/
status_t FLEXIO_SPI_SlaveTransferNonBlocking(FLEXIO_SPI_Type *base,
flexio_spi_slave_handle_t *handle,
flexio_spi_transfer_t *xfer)
@ -939,6 +1193,12 @@ status_t FLEXIO_SPI_SlaveTransferNonBlocking(FLEXIO_SPI_Type *base,
return kStatus_Success;
}
/*!
* brief FlexIO SPI slave IRQ handler function.
*
* param spiType Pointer to the FLEXIO_SPI_Type structure.
* param spiHandle Pointer to the flexio_spi_slave_handle_t structure to store the transfer state.
*/
void FLEXIO_SPI_SlaveTransferHandleIRQ(void *spiType, void *spiHandle)
{
assert(spiHandle);

64
ext/hal/nxp/mcux/drivers/imx/fsl_flexio_spi_edma.c
View file

@ -2,7 +2,7 @@
* Copyright (c) 2015, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
* All rights reserved.
*
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -126,8 +126,8 @@ static void FLEXIO_SPI_EDMAConfig(FLEXIO_SPI_Type *base,
flexio_spi_master_edma_handle_t *handle,
flexio_spi_transfer_t *xfer)
{
edma_transfer_config_t xferConfig;
flexio_spi_shift_direction_t direction;
edma_transfer_config_t xferConfig = {0};
flexio_spi_shift_direction_t direction = kFLEXIO_SPI_MsbFirst;
uint8_t bytesPerFrame;
/* Configure the values in handle. */
@ -231,6 +231,23 @@ static void FLEXIO_SPI_EDMAConfig(FLEXIO_SPI_Type *base,
}
}
/*!
* brief Initializes the FlexIO SPI master eDMA handle.
*
* This function initializes the FlexIO SPI master eDMA handle which can be used for other FlexIO SPI master
* transactional
* APIs.
* For a specified FlexIO SPI instance, call this API once to get the initialized handle.
*
* param base Pointer to FLEXIO_SPI_Type structure.
* param handle Pointer to flexio_spi_master_edma_handle_t structure to store the transfer state.
* param callback SPI callback, NULL means no callback.
* param userData callback function parameter.
* param txHandle User requested eDMA handle for FlexIO SPI RX eDMA transfer.
* param rxHandle User requested eDMA handle for FlexIO SPI TX eDMA transfer.
* retval kStatus_Success Successfully create the handle.
* retval kStatus_OutOfRange The FlexIO SPI eDMA type/handle table out of range.
*/
status_t FLEXIO_SPI_MasterTransferCreateHandleEDMA(FLEXIO_SPI_Type *base,
flexio_spi_master_edma_handle_t *handle,
flexio_spi_master_edma_transfer_callback_t callback,
@ -283,6 +300,20 @@ status_t FLEXIO_SPI_MasterTransferCreateHandleEDMA(FLEXIO_SPI_Type *base,
return kStatus_Success;
}
/*!
* brief Performs a non-blocking FlexIO SPI transfer using eDMA.
*
* note This interface returns immediately after transfer initiates. Call
* FLEXIO_SPI_MasterGetTransferCountEDMA to poll the transfer status and check
* whether the FlexIO SPI transfer is finished.
*
* param base Pointer to FLEXIO_SPI_Type structure.
* param handle Pointer to flexio_spi_master_edma_handle_t structure to store the transfer state.
* param xfer Pointer to FlexIO SPI transfer structure.
* retval kStatus_Success Successfully start a transfer.
* retval kStatus_InvalidArgument Input argument is invalid.
* retval kStatus_FLEXIO_SPI_Busy FlexIO SPI is not idle, is running another transfer.
*/
status_t FLEXIO_SPI_MasterTransferEDMA(FLEXIO_SPI_Type *base,
flexio_spi_master_edma_handle_t *handle,
flexio_spi_transfer_t *xfer)
@ -330,6 +361,13 @@ status_t FLEXIO_SPI_MasterTransferEDMA(FLEXIO_SPI_Type *base,
return kStatus_Success;
}
/*!
* brief Gets the remaining bytes for FlexIO SPI eDMA transfer.
*
* param base Pointer to FLEXIO_SPI_Type structure.
* param handle FlexIO SPI eDMA handle pointer.
* param count Number of bytes transferred so far by the non-blocking transaction.
*/
status_t FLEXIO_SPI_MasterTransferGetCountEDMA(FLEXIO_SPI_Type *base,
flexio_spi_master_edma_handle_t *handle,
size_t *count)
@ -357,6 +395,12 @@ status_t FLEXIO_SPI_MasterTransferGetCountEDMA(FLEXIO_SPI_Type *base,
return kStatus_Success;
}
/*!
* brief Aborts a FlexIO SPI transfer using eDMA.
*
* param base Pointer to FLEXIO_SPI_Type structure.
* param handle FlexIO SPI eDMA handle pointer.
*/
void FLEXIO_SPI_MasterTransferAbortEDMA(FLEXIO_SPI_Type *base, flexio_spi_master_edma_handle_t *handle)
{
assert(handle);
@ -373,6 +417,20 @@ void FLEXIO_SPI_MasterTransferAbortEDMA(FLEXIO_SPI_Type *base, flexio_spi_master
handle->rxInProgress = false;
}
/*!
* brief Performs a non-blocking FlexIO SPI transfer using eDMA.
*
* note This interface returns immediately after transfer initiates. Call
* FLEXIO_SPI_SlaveGetTransferCountEDMA to poll the transfer status and
* check whether the FlexIO SPI transfer is finished.
*
* param base Pointer to FLEXIO_SPI_Type structure.
* param handle Pointer to flexio_spi_slave_edma_handle_t structure to store the transfer state.
* param xfer Pointer to FlexIO SPI transfer structure.
* retval kStatus_Success Successfully start a transfer.
* retval kStatus_InvalidArgument Input argument is invalid.
* retval kStatus_FLEXIO_SPI_Busy FlexIO SPI is not idle, is running another transfer.
*/
status_t FLEXIO_SPI_SlaveTransferEDMA(FLEXIO_SPI_Type *base,
flexio_spi_slave_edma_handle_t *handle,
flexio_spi_transfer_t *xfer)

251
ext/hal/nxp/mcux/drivers/imx/fsl_flexio_uart.c
View file

@ -1,8 +1,8 @@
/*
* Copyright (c) 2015-2016, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
* Copyright 2016-2018 NXP
* All rights reserved.
*
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -17,7 +17,6 @@
#define FSL_COMPONENT_ID "platform.drivers.flexio_uart"
#endif
/*<! @brief uart transfer state. */
enum _flexio_uart_transfer_states
{
@ -89,6 +88,37 @@ static bool FLEXIO_UART_TransferIsRxRingBufferFull(flexio_uart_handle_t *handle)
return full;
}
/*!
* brief Ungates the FlexIO clock, resets the FlexIO module, configures FlexIO UART
* hardware, and configures the FlexIO UART with FlexIO UART configuration.
* The configuration structure can be filled by the user or be set with
* default values by FLEXIO_UART_GetDefaultConfig().
*
* Example
code
FLEXIO_UART_Type base = {
.flexioBase = FLEXIO,
.TxPinIndex = 0,
.RxPinIndex = 1,
.shifterIndex = {0,1},
.timerIndex = {0,1}
};
flexio_uart_config_t config = {
.enableInDoze = false,
.enableInDebug = true,
.enableFastAccess = false,
.baudRate_Bps = 115200U,
.bitCountPerChar = 8
};
FLEXIO_UART_Init(base, &config, srcClock_Hz);
endcode
*
* param base Pointer to the FLEXIO_UART_Type structure.
* param userConfig Pointer to the flexio_uart_config_t structure.
* param srcClock_Hz FlexIO source clock in Hz.
* retval kStatus_Success Configuration success
* retval kStatus_InvalidArgument Buadrate configuration out of range
*/
status_t FLEXIO_UART_Init(FLEXIO_UART_Type *base, const flexio_uart_config_t *userConfig, uint32_t srcClock_Hz)
{
assert(base && userConfig);
@ -202,6 +232,13 @@ status_t FLEXIO_UART_Init(FLEXIO_UART_Type *base, const flexio_uart_config_t *us
return result;
}
/*!
* brief Resets the FlexIO UART shifter and timer config.
*
* note After calling this API, call the FLEXO_UART_Init to use the FlexIO UART module.
*
* param base Pointer to FLEXIO_UART_Type structure
*/
void FLEXIO_UART_Deinit(FLEXIO_UART_Type *base)
{
base->flexioBase->SHIFTCFG[base->shifterIndex[0]] = 0;
@ -222,10 +259,23 @@ void FLEXIO_UART_Deinit(FLEXIO_UART_Type *base)
base->flexioBase->TIMSTAT = (1U << base->timerIndex[1]);
}
/*!
* brief Gets the default configuration to configure the FlexIO UART. The configuration
* can be used directly for calling the FLEXIO_UART_Init().
* Example:
code
flexio_uart_config_t config;
FLEXIO_UART_GetDefaultConfig(&userConfig);
endcode
* param userConfig Pointer to the flexio_uart_config_t structure.
*/
void FLEXIO_UART_GetDefaultConfig(flexio_uart_config_t *userConfig)
{
assert(userConfig);
/* Initializes the configure structure to zero. */
memset(userConfig, 0, sizeof(*userConfig));
userConfig->enableUart = true;
userConfig->enableInDoze = false;
userConfig->enableInDebug = true;
@ -236,6 +286,14 @@ void FLEXIO_UART_GetDefaultConfig(flexio_uart_config_t *userConfig)
userConfig->bitCountPerChar = kFLEXIO_UART_8BitsPerChar;
}
/*!
* brief Enables the FlexIO UART interrupt.
*
* This function enables the FlexIO UART interrupt.
*
* param base Pointer to the FLEXIO_UART_Type structure.
* param mask Interrupt source.
*/
void FLEXIO_UART_EnableInterrupts(FLEXIO_UART_Type *base, uint32_t mask)
{
if (mask & kFLEXIO_UART_TxDataRegEmptyInterruptEnable)
@ -248,6 +306,14 @@ void FLEXIO_UART_EnableInterrupts(FLEXIO_UART_Type *base, uint32_t mask)
}
}
/*!
* brief Disables the FlexIO UART interrupt.
*
* This function disables the FlexIO UART interrupt.
*
* param base Pointer to the FLEXIO_UART_Type structure.
* param mask Interrupt source.
*/
void FLEXIO_UART_DisableInterrupts(FLEXIO_UART_Type *base, uint32_t mask)
{
if (mask & kFLEXIO_UART_TxDataRegEmptyInterruptEnable)
@ -260,6 +326,13 @@ void FLEXIO_UART_DisableInterrupts(FLEXIO_UART_Type *base, uint32_t mask)
}
}
/*!
* brief Gets the FlexIO UART status flags.
*
* param base Pointer to the FLEXIO_UART_Type structure.
* return FlexIO UART status flags.
*/
uint32_t FLEXIO_UART_GetStatusFlags(FLEXIO_UART_Type *base)
{
uint32_t status = 0;
@ -274,6 +347,17 @@ uint32_t FLEXIO_UART_GetStatusFlags(FLEXIO_UART_Type *base)
return status;
}
/*!
* brief Gets the FlexIO UART status flags.
*
* param base Pointer to the FLEXIO_UART_Type structure.
* param mask Status flag.
* The parameter can be any combination of the following values:
* arg kFLEXIO_UART_TxDataRegEmptyFlag
* arg kFLEXIO_UART_RxEmptyFlag
* arg kFLEXIO_UART_RxOverRunFlag
*/
void FLEXIO_UART_ClearStatusFlags(FLEXIO_UART_Type *base, uint32_t mask)
{
if (mask & kFLEXIO_UART_TxDataRegEmptyFlag)
@ -290,6 +374,15 @@ void FLEXIO_UART_ClearStatusFlags(FLEXIO_UART_Type *base, uint32_t mask)
}
}
/*!
* brief Sends a buffer of data bytes.
*
* note This function blocks using the polling method until all bytes have been sent.
*
* param base Pointer to the FLEXIO_UART_Type structure.
* param txData The data bytes to send.
* param txSize The number of data bytes to send.
*/
void FLEXIO_UART_WriteBlocking(FLEXIO_UART_Type *base, const uint8_t *txData, size_t txSize)
{
assert(txData);
@ -306,6 +399,15 @@ void FLEXIO_UART_WriteBlocking(FLEXIO_UART_Type *base, const uint8_t *txData, si
}
}
/*!
* brief Receives a buffer of bytes.
*
* note This function blocks using the polling method until all bytes have been received.
*
* param base Pointer to the FLEXIO_UART_Type structure.
* param rxData The buffer to store the received bytes.
* param rxSize The number of data bytes to be received.
*/
void FLEXIO_UART_ReadBlocking(FLEXIO_UART_Type *base, uint8_t *rxData, size_t rxSize)
{
assert(rxData);
@ -322,6 +424,26 @@ void FLEXIO_UART_ReadBlocking(FLEXIO_UART_Type *base, uint8_t *rxData, size_t rx
}
}
/*!
* brief Initializes the UART handle.
*
* This function initializes the FlexIO UART handle, which can be used for other FlexIO
* UART transactional APIs. Call this API once to get the
* initialized handle.
*
* The UART driver supports the "background" receiving, which means that users can set up
* a RX ring buffer optionally. Data received is stored into the ring buffer even when
* the user doesn't call the FLEXIO_UART_TransferReceiveNonBlocking() API. If there is already data
* received in the ring buffer, users can get the received data from the ring buffer
* directly. The ring buffer is disabled if passing NULL as p ringBuffer.
*
* param base to FLEXIO_UART_Type structure.
* param handle Pointer to the flexio_uart_handle_t structure to store the transfer state.
* param callback The callback function.
* param userData The parameter of the callback function.
* retval kStatus_Success Successfully create the handle.
* retval kStatus_OutOfRange The FlexIO type/handle/ISR table out of range.
*/
status_t FLEXIO_UART_TransferCreateHandle(FLEXIO_UART_Type *base,
flexio_uart_handle_t *handle,
flexio_uart_transfer_callback_t callback,
@ -349,6 +471,23 @@ status_t FLEXIO_UART_TransferCreateHandle(FLEXIO_UART_Type *base,
return FLEXIO_RegisterHandleIRQ(base, handle, FLEXIO_UART_TransferHandleIRQ);
}
/*!
* brief Sets up the RX ring buffer.
*
* This function sets up the RX ring buffer to a specific UART handle.
*
* When the RX ring buffer is used, data received is stored into the ring buffer even when
* the user doesn't call the UART_ReceiveNonBlocking() API. If there is already data received
* in the ring buffer, users can get the received data from the ring buffer directly.
*
* note When using the RX ring buffer, one byte is reserved for internal use. In other
* words, if p ringBufferSize is 32, only 31 bytes are used for saving data.
*
* param base Pointer to the FLEXIO_UART_Type structure.
* param handle Pointer to the flexio_uart_handle_t structure to store the transfer state.
* param ringBuffer Start address of ring buffer for background receiving. Pass NULL to disable the ring buffer.
* param ringBufferSize Size of the ring buffer.
*/
void FLEXIO_UART_TransferStartRingBuffer(FLEXIO_UART_Type *base,
flexio_uart_handle_t *handle,
uint8_t *ringBuffer,
@ -369,6 +508,14 @@ void FLEXIO_UART_TransferStartRingBuffer(FLEXIO_UART_Type *base,
}
}
/*!
* brief Aborts the background transfer and uninstalls the ring buffer.
*
* This function aborts the background transfer and uninstalls the ring buffer.
*
* param base Pointer to the FLEXIO_UART_Type structure.
* param handle Pointer to the flexio_uart_handle_t structure to store the transfer state.
*/
void FLEXIO_UART_TransferStopRingBuffer(FLEXIO_UART_Type *base, flexio_uart_handle_t *handle)
{
assert(handle);
@ -384,6 +531,23 @@ void FLEXIO_UART_TransferStopRingBuffer(FLEXIO_UART_Type *base, flexio_uart_hand
handle->rxRingBufferTail = 0U;
}
/*!
* brief Transmits a buffer of data using the interrupt method.
*
* This function sends data using an interrupt method. This is a non-blocking function,
* which returns directly without waiting for all data to be written to the TX register. When
* all data is written to the TX register in ISR, the FlexIO UART driver calls the callback
* function and passes the ref kStatus_FLEXIO_UART_TxIdle as status parameter.
*
* note The kStatus_FLEXIO_UART_TxIdle is passed to the upper layer when all data is written
* to the TX register. However, it does not ensure that all data is sent out.
*
* param base Pointer to the FLEXIO_UART_Type structure.
* param handle Pointer to the flexio_uart_handle_t structure to store the transfer state.
* param xfer FlexIO UART transfer structure. See #flexio_uart_transfer_t.
* retval kStatus_Success Successfully starts the data transmission.
* retval kStatus_UART_TxBusy Previous transmission still not finished, data not written to the TX register.
*/
status_t FLEXIO_UART_TransferSendNonBlocking(FLEXIO_UART_Type *base,
flexio_uart_handle_t *handle,
flexio_uart_transfer_t *xfer)
@ -417,6 +581,15 @@ status_t FLEXIO_UART_TransferSendNonBlocking(FLEXIO_UART_Type *base,
return status;
}
/*!
* brief Aborts the interrupt-driven data transmit.
*
* This function aborts the interrupt-driven data sending. Get the remainBytes to find out
* how many bytes are still not sent out.
*
* param base Pointer to the FLEXIO_UART_Type structure.
* param handle Pointer to the flexio_uart_handle_t structure to store the transfer state.
*/
void FLEXIO_UART_TransferAbortSend(FLEXIO_UART_Type *base, flexio_uart_handle_t *handle)
{
/* Disable the transmitter and disable the interrupt. */
@ -426,6 +599,17 @@ void FLEXIO_UART_TransferAbortSend(FLEXIO_UART_Type *base, flexio_uart_handle_t
handle->txState = kFLEXIO_UART_TxIdle;
}
/*!
* brief Gets the number of bytes sent.
*
* This function gets the number of bytes sent driven by interrupt.
*
* param base Pointer to the FLEXIO_UART_Type structure.
* param handle Pointer to the flexio_uart_handle_t structure to store the transfer state.
* param count Number of bytes sent so far by the non-blocking transaction.
* retval kStatus_NoTransferInProgress transfer has finished or no transfer in progress.
* retval kStatus_Success Successfully return the count.
*/
status_t FLEXIO_UART_TransferGetSendCount(FLEXIO_UART_Type *base, flexio_uart_handle_t *handle, size_t *count)
{
assert(handle);
@ -441,6 +625,31 @@ status_t FLEXIO_UART_TransferGetSendCount(FLEXIO_UART_Type *base, flexio_uart_ha
return kStatus_Success;
}
/*!
* brief Receives a buffer of data using the interrupt method.
*
* This function receives data using the interrupt method. This is a non-blocking function,
* which returns without waiting for all data to be received.
* If the RX ring buffer is used and not empty, the data in ring buffer is copied and
* the parameter p receivedBytes shows how many bytes are copied from the ring buffer.
* After copying, if the data in ring buffer is not enough to read, the receive
* request is saved by the UART driver. When new data arrives, the receive request
* is serviced first. When all data is received, the UART driver notifies the upper layer
* through a callback function and passes the status parameter ref kStatus_UART_RxIdle.
* For example, if the upper layer needs 10 bytes but there are only 5 bytes in the ring buffer,
* the 5 bytes are copied to xfer->data. This function returns with the
* parameter p receivedBytes set to 5. For the last 5 bytes, newly arrived data is
* saved from the xfer->data[5]. When 5 bytes are received, the UART driver notifies upper layer.
* If the RX ring buffer is not enabled, this function enables the RX and RX interrupt
* to receive data to xfer->data. When all data is received, the upper layer is notified.
*
* param base Pointer to the FLEXIO_UART_Type structure.
* param handle Pointer to the flexio_uart_handle_t structure to store the transfer state.
* param xfer UART transfer structure. See #flexio_uart_transfer_t.
* param receivedBytes Bytes received from the ring buffer directly.
* retval kStatus_Success Successfully queue the transfer into the transmit queue.
* retval kStatus_FLEXIO_UART_RxBusy Previous receive request is not finished.
*/
status_t FLEXIO_UART_TransferReceiveNonBlocking(FLEXIO_UART_Type *base,
flexio_uart_handle_t *handle,
flexio_uart_transfer_t *xfer,
@ -524,6 +733,15 @@ status_t FLEXIO_UART_TransferReceiveNonBlocking(FLEXIO_UART_Type *base,
/* Enable FLEXIO_UART RX IRQ if previously enabled. */
FLEXIO_UART_EnableInterrupts(base, kFLEXIO_UART_RxDataRegFullInterruptEnable);
/* Call user callback since all data are received. */
if (0 == bytesToReceive)
{
if (handle->callback)
{
handle->callback(base, handle, kStatus_FLEXIO_UART_RxIdle, handle->userData);
}
}
}
/* Ring buffer not used. */
else
@ -549,6 +767,14 @@ status_t FLEXIO_UART_TransferReceiveNonBlocking(FLEXIO_UART_Type *base,
return status;
}
/*!
* brief Aborts the receive data which was using IRQ.
*
* This function aborts the receive data which was using IRQ.
*
* param base Pointer to the FLEXIO_UART_Type structure.
* param handle Pointer to the flexio_uart_handle_t structure to store the transfer state.
*/
void FLEXIO_UART_TransferAbortReceive(FLEXIO_UART_Type *base, flexio_uart_handle_t *handle)
{
/* Only abort the receive to handle->rxData, the RX ring buffer is still working. */
@ -562,6 +788,17 @@ void FLEXIO_UART_TransferAbortReceive(FLEXIO_UART_Type *base, flexio_uart_handle
handle->rxState = kFLEXIO_UART_RxIdle;
}
/*!
* brief Gets the number of bytes received.
*
* This function gets the number of bytes received driven by interrupt.
*
* param base Pointer to the FLEXIO_UART_Type structure.
* param handle Pointer to the flexio_uart_handle_t structure to store the transfer state.
* param count Number of bytes received so far by the non-blocking transaction.
* retval kStatus_NoTransferInProgress transfer has finished or no transfer in progress.
* retval kStatus_Success Successfully return the count.
*/
status_t FLEXIO_UART_TransferGetReceiveCount(FLEXIO_UART_Type *base, flexio_uart_handle_t *handle, size_t *count)
{
assert(handle);
@ -577,6 +814,14 @@ status_t FLEXIO_UART_TransferGetReceiveCount(FLEXIO_UART_Type *base, flexio_uart
return kStatus_Success;
}
/*!
* brief FlexIO UART IRQ handler function.
*
* This function processes the FlexIO UART transmit and receives the IRQ request.
*
* param uartType Pointer to the FLEXIO_UART_Type structure.
* param uartHandle Pointer to the flexio_uart_handle_t structure to store the transfer state.
*/
void FLEXIO_UART_TransferHandleIRQ(void *uartType, void *uartHandle)
{
uint8_t count = 1;

8
ext/hal/nxp/mcux/drivers/imx/fsl_flexio_uart.h
View file

@ -1,8 +1,8 @@
/*
* Copyright (c) 2015-2016, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
* Copyright 2016-2018 NXP
* All rights reserved.
*
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -23,8 +23,8 @@
/*! @name Driver version */
/*@{*/
/*! @brief FlexIO UART driver version 2.1.4. */
#define FSL_FLEXIO_UART_DRIVER_VERSION (MAKE_VERSION(2, 1, 4))
/*! @brief FlexIO UART driver version 2.1.5. */
#define FSL_FLEXIO_UART_DRIVER_VERSION (MAKE_VERSION(2, 1, 5))
/*@}*/
/*! @brief Error codes for the UART driver. */

77
ext/hal/nxp/mcux/drivers/imx/fsl_flexio_uart_edma.c
View file

@ -2,7 +2,7 @@
* Copyright (c) 2015, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
* All rights reserved.
*
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -17,7 +17,6 @@
#define FSL_COMPONENT_ID "platform.drivers.flexio_uart_edma"
#endif
/*<! Structure definition for uart_edma_private_handle_t. The structure is private. */
typedef struct _flexio_uart_edma_private_handle
{
@ -125,6 +124,18 @@ static void FLEXIO_UART_TransferReceiveEDMACallback(edma_handle_t *handle,
}
}
/*!
* brief Initializes the UART handle which is used in transactional functions.
*
* param base Pointer to FLEXIO_UART_Type.
* param handle Pointer to flexio_uart_edma_handle_t structure.
* param callback The callback function.
* param userData The parameter of the callback function.
* param rxEdmaHandle User requested DMA handle for RX DMA transfer.
* param txEdmaHandle User requested DMA handle for TX DMA transfer.
* retval kStatus_Success Successfully create the handle.
* retval kStatus_OutOfRange The FlexIO SPI eDMA type/handle table out of range.
*/
status_t FLEXIO_UART_TransferCreateHandleEDMA(FLEXIO_UART_Type *base,
flexio_uart_edma_handle_t *handle,
flexio_uart_edma_transfer_callback_t callback,
@ -178,6 +189,18 @@ status_t FLEXIO_UART_TransferCreateHandleEDMA(FLEXIO_UART_Type *base,
return kStatus_Success;
}
/*!
* brief Sends data using eDMA.
*
* This function sends data using eDMA. This is a non-blocking function, which returns
* right away. When all data is sent out, the send callback function is called.
*
* param base Pointer to FLEXIO_UART_Type
* param handle UART handle pointer.
* param xfer UART eDMA transfer structure, see #flexio_uart_transfer_t.
* retval kStatus_Success if succeed, others failed.
* retval kStatus_FLEXIO_UART_TxBusy Previous transfer on going.
*/
status_t FLEXIO_UART_TransferSendEDMA(FLEXIO_UART_Type *base,
flexio_uart_edma_handle_t *handle,
flexio_uart_transfer_t *xfer)
@ -224,6 +247,18 @@ status_t FLEXIO_UART_TransferSendEDMA(FLEXIO_UART_Type *base,
return status;
}
/*!
* brief Receives data using eDMA.
*
* This function receives data using eDMA. This is a non-blocking function, which returns
* right away. When all data is received, the receive callback function is called.
*
* param base Pointer to FLEXIO_UART_Type
* param handle Pointer to flexio_uart_edma_handle_t structure
* param xfer UART eDMA transfer structure, see #flexio_uart_transfer_t.
* retval kStatus_Success if succeed, others failed.
* retval kStatus_UART_RxBusy Previous transfer on going.
*/
status_t FLEXIO_UART_TransferReceiveEDMA(FLEXIO_UART_Type *base,
flexio_uart_edma_handle_t *handle,
flexio_uart_transfer_t *xfer)
@ -269,6 +304,14 @@ status_t FLEXIO_UART_TransferReceiveEDMA(FLEXIO_UART_Type *base,
return status;
}
/*!
* brief Aborts the sent data which using eDMA.
*
* This function aborts sent data which using eDMA.
*
* param base Pointer to FLEXIO_UART_Type
* param handle Pointer to flexio_uart_edma_handle_t structure
*/
void FLEXIO_UART_TransferAbortSendEDMA(FLEXIO_UART_Type *base, flexio_uart_edma_handle_t *handle)
{
assert(handle->txEdmaHandle);
@ -282,6 +325,14 @@ void FLEXIO_UART_TransferAbortSendEDMA(FLEXIO_UART_Type *base, flexio_uart_edma_
handle->txState = kFLEXIO_UART_TxIdle;
}
/*!
* brief Aborts the receive data which using eDMA.
*
* This function aborts the receive data which using eDMA.
*
* param base Pointer to FLEXIO_UART_Type
* param handle Pointer to flexio_uart_edma_handle_t structure
*/
void FLEXIO_UART_TransferAbortReceiveEDMA(FLEXIO_UART_Type *base, flexio_uart_edma_handle_t *handle)
{
assert(handle->rxEdmaHandle);
@ -295,6 +346,17 @@ void FLEXIO_UART_TransferAbortReceiveEDMA(FLEXIO_UART_Type *base, flexio_uart_ed
handle->rxState = kFLEXIO_UART_RxIdle;
}
/*!
* brief Gets the number of bytes received.
*
* This function gets the number of bytes received.
*
* param base Pointer to FLEXIO_UART_Type
* param handle Pointer to flexio_uart_edma_handle_t structure
* param count Number of bytes received so far by the non-blocking transaction.
* retval kStatus_NoTransferInProgress transfer has finished or no transfer in progress.
* retval kStatus_Success Successfully return the count.
*/
status_t FLEXIO_UART_TransferGetReceiveCountEDMA(FLEXIO_UART_Type *base,
flexio_uart_edma_handle_t *handle,
size_t *count)
@ -315,6 +377,17 @@ status_t FLEXIO_UART_TransferGetReceiveCountEDMA(FLEXIO_UART_Type *base,
return kStatus_Success;
}
/*!
* brief Gets the number of bytes sent out.
*
* This function gets the number of bytes sent out.
*
* param base Pointer to FLEXIO_UART_Type
* param handle Pointer to flexio_uart_edma_handle_t structure
* param count Number of bytes sent so far by the non-blocking transaction.
* retval kStatus_NoTransferInProgress transfer has finished or no transfer in progress.
* retval kStatus_Success Successfully return the count.
*/
status_t FLEXIO_UART_TransferGetSendCountEDMA(FLEXIO_UART_Type *base, flexio_uart_edma_handle_t *handle, size_t *count)
{
assert(handle);

83
ext/hal/nxp/mcux/drivers/imx/fsl_flexram.c
View file

@ -2,7 +2,7 @@
* Copyright 2017 NXP
* All rights reserved.
*
*
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -37,15 +37,6 @@ static uint32_t FLEXRAM_GetInstance(FLEXRAM_Type *base);
*/
static uint8_t FLEXRAM_MapTcmSizeToRegister(uint8_t tcmBankNum);
/*!
* @brief FLEXRAM configure TCM size
* This function is used to set the TCM to the actual size.When access to the TCM memory boundary ,hardfault will
* raised by core.
* @param itcmBankNum itcm bank number to allocate
* @param dtcmBankNum dtcm bank number to allocate
*/
static status_t FLEXRAM_SetTCMSize(uint8_t itcmBankNum, uint8_t dtcmBankNum);
/*******************************************************************************
* Variables
******************************************************************************/
@ -78,6 +69,11 @@ static uint32_t FLEXRAM_GetInstance(FLEXRAM_Type *base)
return instance;
}
/*!
* brief FLEXRAM module initialization function.
*
* param base FLEXRAM base address.
*/
void FLEXRAM_Init(FLEXRAM_Type *base)
{
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
@ -93,6 +89,10 @@ void FLEXRAM_Init(FLEXRAM_Type *base)
base->INT_SIG_EN = 0U;
}
/*!
* brief Deinitializes the FLEXRAM.
*
*/
void FLEXRAN_Deinit(FLEXRAM_Type *base)
{
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
@ -104,38 +104,40 @@ void FLEXRAN_Deinit(FLEXRAM_Type *base)
static uint8_t FLEXRAM_MapTcmSizeToRegister(uint8_t tcmBankNum)
{
uint8_t tcmSizeConfig = 0U;
uint32_t totalTcmSize = 0U;
switch (tcmBankNum * FSL_FEATURE_FLEXRAM_INTERNAL_RAM_BANK_SIZE)
/* if bank number is a odd value, use a new bank number which bigger than target */
do
{
case kFLEXRAM_TCMSize32KB:
tcmSizeConfig = 6U;
if ((tcmBankNum & (tcmBankNum - 1U)) == 0U)
{
break;
}
} while (++tcmBankNum < FSL_FEATURE_FLEXRAM_INTERNAL_RAM_TOTAL_BANK_NUMBERS);
case kFLEXRAM_TCMSize64KB:
tcmSizeConfig = 7U;
break;
case kFLEXRAM_TCMSize128KB:
tcmSizeConfig = 8U;
break;
case kFLEXRAM_TCMSize256KB:
tcmSizeConfig = 9U;
break;
case kFLEXRAM_TCMSize512KB:
tcmSizeConfig = 10U;
break;
default:
totalTcmSize = tcmBankNum * (FSL_FEATURE_FLEXRAM_INTERNAL_RAM_BANK_SIZE >> 10U);
/* get bit '1' position */
while (totalTcmSize)
{
if ((totalTcmSize & 1U) == 0U)
{
tcmSizeConfig++;
}
else
{
break;
}
totalTcmSize >>= 1U;
}
return tcmSizeConfig;
return tcmSizeConfig + 1U;
}
static status_t FLEXRAM_SetTCMSize(uint8_t itcmBankNum, uint8_t dtcmBankNum)
void FLEXRAM_SetTCMSize(uint8_t itcmBankNum, uint8_t dtcmBankNum)
{
assert(itcmBankNum <= FSL_FEATURE_FLEXRAM_INTERNAL_RAM_TOTAL_BANK_NUMBERS);
assert(dtcmBankNum <= FSL_FEATURE_FLEXRAM_INTERNAL_RAM_TOTAL_BANK_NUMBERS);
/* dtcm configuration */
if (dtcmBankNum != 0U)
{
@ -147,6 +149,7 @@ static status_t FLEXRAM_SetTCMSize(uint8_t itcmBankNum, uint8_t dtcmBankNum)
{
IOMUXC_GPR->GPR16 &= ~IOMUXC_GPR_GPR16_INIT_DTCM_EN_MASK;
}
/* itcm configuration */
if (itcmBankNum != 0U)
{
@ -158,21 +161,27 @@ static status_t FLEXRAM_SetTCMSize(uint8_t itcmBankNum, uint8_t dtcmBankNum)
{
IOMUXC_GPR->GPR16 &= ~IOMUXC_GPR_GPR16_INIT_ITCM_EN_MASK;
}
return kStatus_Success;
}
/*!
* brief FLEXRAM allocate on-chip ram for OCRAM,ITCM,DTCM
* This function is independent of FLEXRAM_Init, it can be called directly if ram re-allocate
* is needed.
* param config allocate configuration.
* retval kStatus_InvalidArgument the argument is invalid
* kStatus_Success allocate success
*/
status_t FLEXRAM_AllocateRam(flexram_allocate_ram_t *config)
{
assert(config != NULL);
uint8_t dtcmBankNum = config->dtcmBankNum;
uint8_t itcmBankNum = config->itcmBankNum;
uint8_t ocramBankNum = config->ocramBankNum;
uint32_t bankCfg = 0U, i = 0U;
/* check the arguments */
if ((FSL_FEATURE_FLEXRAM_INTERNAL_RAM_TOTAL_BANK_NUMBERS < (dtcmBankNum + itcmBankNum + ocramBankNum)) ||
((dtcmBankNum != 0U) && ((dtcmBankNum & (dtcmBankNum - 1u)) != 0U)) ||
((itcmBankNum != 0U) && ((itcmBankNum & (itcmBankNum - 1u)) != 0U)))
if (FSL_FEATURE_FLEXRAM_INTERNAL_RAM_TOTAL_BANK_NUMBERS < (dtcmBankNum + itcmBankNum + ocramBankNum))
{
return kStatus_InvalidArgument;
}

79
ext/hal/nxp/mcux/drivers/imx/fsl_flexram.h
View file

@ -2,7 +2,7 @@
* Copyright 2017 NXP
* All rights reserved.
*
*
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -22,8 +22,8 @@
/*! @name Driver version */
/*@{*/
/*! @brief Driver version 2.0.2. */
#define FSL_FLEXRAM_DRIVER_VERSION (MAKE_VERSION(2U, 0U, 2U))
/*! @brief Driver version 2.0.4. */
#define FSL_FLEXRAM_DRIVER_VERSION (MAKE_VERSION(2U, 0U, 4U))
/*@}*/
/*! @brief flexram write read sel */
@ -36,14 +36,12 @@ enum _flexram_wr_rd_sel
/*! @brief Interrupt status flag mask */
enum _flexram_interrupt_status
{
kFLEXRAM_OCRAMAccessError = FLEXRAM_INT_STATUS_OCRAM_ERR_STATUS_MASK, /*!< ocram access unallocated address */
kFLEXRAM_DTCMAccessError = FLEXRAM_INT_STATUS_DTCM_ERR_STATUS_MASK, /*!< dtcm access unallocated address */
kFLEXRAM_ITCMAccessError = FLEXRAM_INT_STATUS_ITCM_ERR_STATUS_MASK, /*!< itcm access unallocated address */
kFLEXRAM_OCRAMMagicAddrMatch = FLEXRAM_INT_STATUS_OCRAM_MAM_STATUS_MASK, /*!< ocram maigc address match */
kFLEXRAM_DTCMMagicAddrMatch = FLEXRAM_INT_STATUS_DTCM_MAM_STATUS_MASK, /*!< dtcm maigc address match */
kFLEXRAM_ITCMMagicAddrMatch = FLEXRAM_INT_STATUS_ITCM_MAM_STATUS_MASK, /*!< itcm maigc address match */
kFLEXRAM_OCRAMAccessError = FLEXRAM_INT_STATUS_OCRAM_ERR_STATUS_MASK, /*!< ocram access unallocated address */
kFLEXRAM_DTCMAccessError = FLEXRAM_INT_STATUS_DTCM_ERR_STATUS_MASK, /*!< dtcm access unallocated address */
kFLEXRAM_ITCMAccessError = FLEXRAM_INT_STATUS_ITCM_ERR_STATUS_MASK, /*!< itcm access unallocated address */
kFLEXRAM_InterruptStatusAll = 0x3FU, /*!< all the interrupt status mask */
kFLEXRAM_InterruptStatusAll = FLEXRAM_INT_STATUS_OCRAM_ERR_STATUS_MASK | FLEXRAM_INT_STATUS_DTCM_ERR_STATUS_MASK |
FLEXRAM_INT_STATUS_ITCM_ERR_STATUS_MASK, /*!< all the interrupt status mask */
};
/*! @brief FLEXRAM TCM access mode
@ -92,6 +90,15 @@ typedef struct _flexram_allocate_ram
const uint8_t dtcmBankNum; /*!< dtcm bank number to allocate, the number should be power of 2 */
const uint8_t itcmBankNum; /*!< itcm bank number to allocate, the number should be power of 2 */
} flexram_allocate_ram_t;
/*******************************************************************************
* APIs
******************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif
/*!
* @name Initialization and deinitialization
* @{
@ -236,42 +243,6 @@ static inline void FLEXRAM_EnableForceRamClockOn(FLEXRAM_Type *base, bool enable
}
}
/*!
* @brief FLEXRAM OCRAM magic addr configuration
* When read/write access hit magic address, it will generate interrupt
* @param magicAddr magic address.
* @param rwsel read write select, 0 read access , 1 write access
*/
static inline void FLEXRAM_SetOCRAMMagicAddr(FLEXRAM_Type *base, uint16_t magicAddr, uint32_t rwSel)
{
base->OCRAM_MAGIC_ADDR =
FLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_WR_RD_SEL(rwSel) | FLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_MAGIC_ADDR(magicAddr >> 3U);
}
/*!
* @brief FLEXRAM DTCM magic addr configuration
* When read/write access hit magic address, it will generate interrupt
* @param magicAddr magic address.
* @param rwsel read write select, 0 read access , 1 write access
*/
static inline void FLEXRAM_SetDTCMMagicAddr(FLEXRAM_Type *base, uint16_t magicAddr, uint32_t rwSel)
{
base->DTCM_MAGIC_ADDR =
FLEXRAM_DTCM_MAGIC_ADDR_DTCM_WR_RD_SEL(rwSel) | FLEXRAM_DTCM_MAGIC_ADDR_DTCM_MAGIC_ADDR(magicAddr >> 3U);
}
/*!
* @brief FLEXRAM ITCM magic addr configuration
* When read/write access hit magic address, it will generate interrupt
* @param magicAddr magic address.
* @param rwsel read write select, 0 read access , 1 write access
*/
static inline void FLEXRAM_SetITCMMagicAddr(FLEXRAM_Type *base, uint16_t magicAddr, uint32_t rwSel)
{
base->ITCM_MAGIC_ADDR =
FLEXRAM_ITCM_MAGIC_ADDR_ITCM_WR_RD_SEL(rwSel) | FLEXRAM_ITCM_MAGIC_ADDR_ITCM_MAGIC_ADDR(magicAddr >> 3U);
}
/*!
* @brief FLEXRAM allocate on-chip ram for OCRAM,ITCM,DTCM
* This function is independent of FLEXRAM_Init, it can be called directly if ram re-allocate
@ -292,6 +263,22 @@ static inline void FLEXRAM_SetAllocateRamSrc(flexram_bank_allocate_src_t src)
IOMUXC_GPR->GPR16 |= IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL(src);
}
/*!
* @brief FLEXRAM configure TCM size
* This function is used to set the TCM to the target size. If a odd bank number is used,
* a new banknumber will be used which is bigger than target value, application can set tcm
* size to the biggest bank number always, then boundary access error can be captured by flexram only.
* When access to the TCM memory boundary ,hardfault will raised by core.
* @param itcmBankNum itcm bank number to allocate
* @param dtcmBankNum dtcm bank number to allocate
*
*/
void FLEXRAM_SetTCMSize(uint8_t itcmBankNum, uint8_t dtcmBankNum);
#if defined(__cplusplus)
}
#endif
/*! @}*/
#endif

148
ext/hal/nxp/mcux/drivers/imx/fsl_flexspi.c
View file

@ -2,7 +2,7 @@
* Copyright (c) 2016, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
* All rights reserved.
*
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -13,7 +13,6 @@
#define FSL_COMPONENT_ID "platform.drivers.flexspi"
#endif
/*******************************************************************************
* Definitations
******************************************************************************/
@ -80,12 +79,6 @@ status_t FLEXSPI_CheckAndClearError(FLEXSPI_Type *base, uint32_t status);
/*******************************************************************************
* Variables
******************************************************************************/
#if defined(FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ) && FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ
/*! @brief Pointers to flexspi handles for each instance. */
static void *s_flexspiHandle[FSL_FEATURE_SOC_FLEXSPI_COUNT];
#endif
/*! @brief Pointers to flexspi bases for each instance. */
static FLEXSPI_Type *const s_flexspiBases[] = FLEXSPI_BASE_PTRS;
@ -97,6 +90,11 @@ static const IRQn_Type s_flexspiIrqs[] = FLEXSPI_IRQS;
static const clock_ip_name_t s_flexspiClock[] = FLEXSPI_CLOCKS;
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
#if defined(FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ) && FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ
/*! @brief Pointers to flexspi handles for each instance. */
static void *s_flexspiHandle[ARRAY_SIZE(s_flexspiBases)];
#endif
/*******************************************************************************
* Code
******************************************************************************/
@ -106,7 +104,7 @@ uint32_t FLEXSPI_GetInstance(FLEXSPI_Type *base)
uint32_t instance;
/* Find the instance index from base address mappings. */
for (instance = 0; instance < FSL_FEATURE_SOC_FLEXSPI_COUNT; instance++)
for (instance = 0; instance < ARRAY_SIZE(s_flexspiBases); instance++)
{
if (s_flexspiBases[instance] == base)
{
@ -114,7 +112,7 @@ uint32_t FLEXSPI_GetInstance(FLEXSPI_Type *base)
}
}
assert(instance < FSL_FEATURE_SOC_FLEXSPI_COUNT);
assert(instance < ARRAY_SIZE(s_flexspiBases));
return instance;
}
@ -210,6 +208,15 @@ status_t FLEXSPI_CheckAndClearError(FLEXSPI_Type *base, uint32_t status)
return result;
}
/*!
* brief Initializes the FLEXSPI module and internal state.
*
* This function enables the clock for FLEXSPI and also configures the FLEXSPI with the
* input configure parameters. Users should call this function before any FLEXSPI operations.
*
* param base FLEXSPI peripheral base address.
* param config FLEXSPI configure structure.
*/
void FLEXSPI_Init(FLEXSPI_Type *base, const flexspi_config_t *config)
{
uint32_t configValue = 0;
@ -281,10 +288,24 @@ void FLEXSPI_Init(FLEXSPI_Type *base, const flexspi_config_t *config)
base->IPRXFCR |= FLEXSPI_IPRXFCR_RXWMRK(config->rxWatermark / 8 - 1);
base->IPTXFCR &= ~FLEXSPI_IPTXFCR_TXWMRK_MASK;
base->IPTXFCR |= FLEXSPI_IPTXFCR_TXWMRK(config->txWatermark / 8 - 1);
/* Reset flash size on all ports */
for (i = 0; i < kFLEXSPI_PortCount; i++)
{
base->FLSHCR0[i] = 0;
}
}
/*!
* brief Gets default settings for FLEXSPI.
*
* param config FLEXSPI configuration structure.
*/
void FLEXSPI_GetDefaultConfig(flexspi_config_t *config)
{
/* Initializes the configure structure to zero. */
memset(config, 0, sizeof(*config));
config->rxSampleClock = kFLEXSPI_ReadSampleClkLoopbackInternally;
config->enableSckFreeRunning = false;
config->enableCombination = false;
@ -313,12 +334,29 @@ void FLEXSPI_GetDefaultConfig(flexspi_config_t *config)
config->ahbConfig.enableAHBCachable = false;
}
/*!
* brief Deinitializes the FLEXSPI module.
*
* Clears the FLEXSPI state and FLEXSPI module registers.
* param base FLEXSPI peripheral base address.
*/
void FLEXSPI_Deinit(FLEXSPI_Type *base)
{
/* Reset peripheral. */
FLEXSPI_SoftwareReset(base);
}
/*!
* brief Configures the connected device parameter.
*
* This function configures the connected device relevant parameters, such as the size, command, and so on.
* The flash configuration value cannot have a default value. The user needs to configure it according to the
* connected device.
*
* param base FLEXSPI peripheral base address.
* param config Flash configuration parameters.
* param port FLEXSPI Operation port.
*/
void FLEXSPI_SetFlashConfig(FLEXSPI_Type *base, flexspi_device_config_t *config, flexspi_port_t port)
{
uint32_t configValue = 0;
@ -330,7 +368,6 @@ void FLEXSPI_SetFlashConfig(FLEXSPI_Type *base, flexspi_device_config_t *config,
}
/* Configure flash size. */
base->FLSHCR0[index] = 0;
base->FLSHCR0[port] = config->flashSize;
/* Configure flash parameters. */
@ -390,6 +427,15 @@ void FLEXSPI_SetFlashConfig(FLEXSPI_Type *base, flexspi_device_config_t *config,
base->MCR0 &= ~FLEXSPI_MCR0_MDIS_MASK;
}
/*! brief Updates the LUT table.
*
* param base FLEXSPI peripheral base address.
* param index From which index start to update. It could be any index of the LUT table, which
* also allows user to update command content inside a command. Each command consists of up to
* 8 instructions and occupy 4*32-bit memory.
* param cmd Command sequence array.
* param count Number of sequences.
*/
void FLEXSPI_UpdateLUT(FLEXSPI_Type *base, uint32_t index, const uint32_t *cmd, uint32_t count)
{
assert(index < 64U);
@ -407,7 +453,7 @@ void FLEXSPI_UpdateLUT(FLEXSPI_Type *base, uint32_t index, const uint32_t *cmd,
base->LUTCR = 0x02;
lutBase = &base->LUT[index];
for (i = index; i < count; i++)
for (i = 0; i < count; i++)
{
*lutBase++ = *cmd++;
}
@ -417,6 +463,17 @@ void FLEXSPI_UpdateLUT(FLEXSPI_Type *base, uint32_t index, const uint32_t *cmd,
base->LUTCR = 0x01;
}
/*!
* brief Sends a buffer of data bytes using blocking method.
* note This function blocks via polling until all bytes have been sent.
* param base FLEXSPI peripheral base address
* param buffer The data bytes to send
* param size The number of data bytes to send
* retval kStatus_Success write success without error
* retval kStatus_FLEXSPI_SequenceExecutionTimeout sequence execution timeout
* retval kStatus_FLEXSPI_IpCommandSequenceError IP command sequencen error detected
* retval kStatus_FLEXSPI_IpCommandGrantTimeout IP command grant timeout detected
*/
status_t FLEXSPI_WriteBlocking(FLEXSPI_Type *base, uint32_t *buffer, size_t size)
{
uint8_t txWatermark = ((base->IPTXFCR & FLEXSPI_IPTXFCR_TXWMRK_MASK) >> FLEXSPI_IPTXFCR_TXWMRK_SHIFT) + 1;
@ -465,6 +522,17 @@ status_t FLEXSPI_WriteBlocking(FLEXSPI_Type *base, uint32_t *buffer, size_t size
return result;
}
/*!
* brief Receives a buffer of data bytes using a blocking method.
* note This function blocks via polling until all bytes have been sent.
* param base FLEXSPI peripheral base address
* param buffer The data bytes to send
* param size The number of data bytes to receive
* retval kStatus_Success read success without error
* retval kStatus_FLEXSPI_SequenceExecutionTimeout sequence execution timeout
* retval kStatus_FLEXSPI_IpCommandSequenceError IP command sequencen error detected
* retval kStatus_FLEXSPI_IpCommandGrantTimeout IP command grant timeout detected
*/
status_t FLEXSPI_ReadBlocking(FLEXSPI_Type *base, uint32_t *buffer, size_t size)
{
uint8_t rxWatermark = ((base->IPRXFCR & FLEXSPI_IPRXFCR_RXWMRK_MASK) >> FLEXSPI_IPRXFCR_RXWMRK_SHIFT) + 1;
@ -535,6 +603,15 @@ status_t FLEXSPI_ReadBlocking(FLEXSPI_Type *base, uint32_t *buffer, size_t size)
return result;
}
/*!
* brief Execute command to transfer a buffer data bytes using a blocking method.
* param base FLEXSPI peripheral base address
* param xfer pointer to the transfer structure.
* retval kStatus_Success command transfer success without error
* retval kStatus_FLEXSPI_SequenceExecutionTimeout sequence execution timeout
* retval kStatus_FLEXSPI_IpCommandSequenceError IP command sequencen error detected
* retval kStatus_FLEXSPI_IpCommandGrantTimeout IP command grant timeout detected
*/
status_t FLEXSPI_TransferBlocking(FLEXSPI_Type *base, flexspi_transfer_t *xfer)
{
uint32_t configValue = 0;
@ -592,6 +669,14 @@ status_t FLEXSPI_TransferBlocking(FLEXSPI_Type *base, flexspi_transfer_t *xfer)
return result;
}
/*!
* brief Initializes the FLEXSPI handle which is used in transactional functions.
*
* param base FLEXSPI peripheral base address.
* param handle pointer to flexspi_handle_t structure to store the transfer state.
* param callback pointer to user callback function.
* param userData user parameter passed to the callback function.
*/
void FLEXSPI_TransferCreateHandle(FLEXSPI_Type *base,
flexspi_handle_t *handle,
flexspi_transfer_callback_t callback,
@ -617,6 +702,21 @@ void FLEXSPI_TransferCreateHandle(FLEXSPI_Type *base,
EnableIRQ(s_flexspiIrqs[instance]);
}
/*!
* brief Performs a interrupt non-blocking transfer on the FLEXSPI bus.
*
* note Calling the API returns immediately after transfer initiates. The user needs
* to call FLEXSPI_GetTransferCount to poll the transfer status to check whether
* the transfer is finished. If the return status is not kStatus_FLEXSPI_Busy, the transfer
* is finished. For FLEXSPI_Read, the dataSize should be multiple of rx watermark levle, or
* FLEXSPI could not read data properly.
*
* param base FLEXSPI peripheral base address.
* param handle pointer to flexspi_handle_t structure which stores the transfer state.
* param xfer pointer to flexspi_transfer_t structure.
* retval kStatus_Success Successfully start the data transmission.
* retval kStatus_FLEXSPI_Busy Previous transmission still not finished.
*/
status_t FLEXSPI_TransferNonBlocking(FLEXSPI_Type *base, flexspi_handle_t *handle, flexspi_transfer_t *xfer)
{
uint32_t configValue = 0;
@ -683,6 +783,15 @@ status_t FLEXSPI_TransferNonBlocking(FLEXSPI_Type *base, flexspi_handle_t *handl
return result;
}
/*!
* brief Gets the master transfer status during a interrupt non-blocking transfer.
*
* param base FLEXSPI peripheral base address.
* param handle pointer to flexspi_handle_t structure which stores the transfer state.
* param count Number of bytes transferred so far by the non-blocking transaction.
* retval kStatus_InvalidArgument count is Invalid.
* retval kStatus_Success Successfully return the count.
*/
status_t FLEXSPI_TransferGetCount(FLEXSPI_Type *base, flexspi_handle_t *handle, size_t *count)
{
assert(handle);
@ -701,6 +810,15 @@ status_t FLEXSPI_TransferGetCount(FLEXSPI_Type *base, flexspi_handle_t *handle,
return result;
}
/*!
* brief Aborts an interrupt non-blocking transfer early.
*
* note This API can be called at any time when an interrupt non-blocking transfer initiates
* to abort the transfer early.
*
* param base FLEXSPI peripheral base address.
* param handle pointer to flexspi_handle_t structure which stores the transfer state
*/
void FLEXSPI_TransferAbort(FLEXSPI_Type *base, flexspi_handle_t *handle)
{
assert(handle);
@ -709,6 +827,12 @@ void FLEXSPI_TransferAbort(FLEXSPI_Type *base, flexspi_handle_t *handle)
handle->state = kFLEXSPI_Idle;
}
/*!
* brief Master interrupt handler.
*
* param base FLEXSPI peripheral base address.
* param handle pointer to flexspi_handle_t structure.
*/
void FLEXSPI_TransferHandleIRQ(FLEXSPI_Type *base, flexspi_handle_t *handle)
{
uint8_t status;

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