From 011a88c7441bf9bfec5bcc0727105bfdb76f2dd9 Mon Sep 17 00:00:00 2001 From: Maureen Helm Date: Wed, 19 Dec 2018 15:22:00 -0600 Subject: [PATCH] ext: mcux: Update to MCUXpresso SDK 2.5.0 Updates the MCUXpresso SDK to version 2.5.0 for applicable SoCs. Wireless (KW*) and legacy (KL25) SoCs were not included in this MCUXpresso SDK release and are therefore not updated here. New in this release is SoC-level and board-level support for external xip flash in the i.MX RT family. For RT1050, we are now using the MCUXpresso SDK for the EVKB version of the board, which correponds to an upgrade from A0 to A1 silicon. However, we don't yet have Kconfigs in place to support A1 silicon part numbers, and therefore add a simple cmake hack to convert A0 part numbers to A1 part numbers. The SDK flash driver interface also changed slightly in this release, and thus the zephyr flash shim driver is updated accordingly. Origin: MCUXpresso SDK License: BSD 3-Clause URL: mcux.nxp.com Purpose: Provide device header files and bare metal peripheral drivers for Kinetis, LPC, and i.MX SoCs. Maintained-by: External Signed-off-by: Maureen Helm --- drivers/flash/soc_flash_mcux.c | 14 +- ext/hal/nxp/mcux/CMakeLists.txt | 2 + ext/hal/nxp/mcux/README | 12 +- .../evkbimxrt1050_flexspi_nor_config.c | 55 + .../evkbimxrt1050_flexspi_nor_config.h | 269 + .../evkbimxrt1050_sdram_ini_dcd.c | 1105 + .../evkbimxrt1050_sdram_ini_dcd.h | 27 + .../evkmimxrt1060_flexspi_nor_config.c | 49 + .../evkmimxrt1060_flexspi_nor_config.h | 268 + .../evkmimxrt1060_sdram_ini_dcd.c | 1105 + .../evkmimxrt1060_sdram_ini_dcd.h | 27 + .../mcux/devices/LPC54114/LPC54114_cm0plus.h | 826 +- .../devices/LPC54114/LPC54114_cm0plus.xml | 9125 ++++- .../LPC54114/LPC54114_cm0plus_features.h | 156 +- .../nxp/mcux/devices/LPC54114/LPC54114_cm4.h | 826 +- .../mcux/devices/LPC54114/LPC54114_cm4.xml | 9141 ++++- .../devices/LPC54114/LPC54114_cm4_features.h | 156 +- ext/hal/nxp/mcux/devices/LPC54114/fsl_clock.c | 545 +- ext/hal/nxp/mcux/devices/LPC54114/fsl_clock.h | 111 +- .../devices/LPC54114/fsl_device_registers.h | 28 +- .../LPC54114/system_LPC54114_cm0plus.c | 39 +- .../LPC54114/system_LPC54114_cm0plus.h | 42 +- .../devices/LPC54114/system_LPC54114_cm4.c | 40 +- .../devices/LPC54114/system_LPC54114_cm4.h | 42 +- .../nxp/mcux/devices/MIMXRT1051/MIMXRT1051.h | 14829 +++++++- .../mcux/devices/MIMXRT1051/MIMXRT1051.xml | 6686 +++- .../devices/MIMXRT1051/MIMXRT1051_features.h | 544 +- .../nxp/mcux/devices/MIMXRT1051/fsl_clock.c | 1207 + .../nxp/mcux/devices/MIMXRT1051/fsl_clock.h | 1471 + .../devices/MIMXRT1051/fsl_device_registers.h | 29 +- .../nxp/mcux/devices/MIMXRT1051/fsl_iomuxc.h | 1244 + .../devices/MIMXRT1051/system_MIMXRT1051.c | 121 +- .../devices/MIMXRT1051/system_MIMXRT1051.h | 69 +- .../nxp/mcux/devices/MIMXRT1052/MIMXRT1052.h | 16081 +++++++- .../mcux/devices/MIMXRT1052/MIMXRT1052.xml | 6931 +++- .../devices/MIMXRT1052/MIMXRT1052_features.h | 538 +- .../nxp/mcux/devices/MIMXRT1052/fsl_clock.c | 729 +- .../nxp/mcux/devices/MIMXRT1052/fsl_clock.h | 1335 +- .../devices/MIMXRT1052/fsl_device_registers.h | 30 +- .../nxp/mcux/devices/MIMXRT1052/fsl_iomuxc.h | 91 +- .../devices/MIMXRT1052/system_MIMXRT1052.c | 122 +- .../devices/MIMXRT1052/system_MIMXRT1052.h | 70 +- .../nxp/mcux/devices/MIMXRT1061/MIMXRT1061.h | 853 +- .../mcux/devices/MIMXRT1061/MIMXRT1061.xml | 445 +- .../devices/MIMXRT1061/MIMXRT1061_features.h | 17 +- .../nxp/mcux/devices/MIMXRT1061/fsl_clock.c | 37 +- .../nxp/mcux/devices/MIMXRT1061/fsl_clock.h | 58 +- .../nxp/mcux/devices/MIMXRT1061/fsl_iomuxc.h | 6 +- .../nxp/mcux/devices/MIMXRT1062/MIMXRT1062.h | 853 +- .../mcux/devices/MIMXRT1062/MIMXRT1062.xml | 445 +- .../devices/MIMXRT1062/MIMXRT1062_features.h | 17 +- .../nxp/mcux/devices/MIMXRT1062/fsl_clock.c | 37 +- .../nxp/mcux/devices/MIMXRT1062/fsl_clock.h | 18 +- .../nxp/mcux/devices/MIMXRT1062/fsl_iomuxc.h | 48 +- ext/hal/nxp/mcux/devices/MK64F12/MK64F12.h | 9718 ++++- ext/hal/nxp/mcux/devices/MK64F12/MK64F12.xml | 30876 +++++++++++++++- .../mcux/devices/MK64F12/MK64F12_features.h | 434 +- ext/hal/nxp/mcux/devices/MK64F12/fsl_clock.c | 540 +- ext/hal/nxp/mcux/devices/MK64F12/fsl_clock.h | 46 +- .../devices/MK64F12/fsl_device_registers.h | 28 +- .../nxp/mcux/devices/MK64F12/system_MK64F12.c | 39 +- .../nxp/mcux/devices/MK64F12/system_MK64F12.h | 42 +- ext/hal/nxp/mcux/drivers/imx/fsl_adc.c | 109 + ext/hal/nxp/mcux/drivers/imx/fsl_adc_etc.c | 71 + ext/hal/nxp/mcux/drivers/imx/fsl_aipstz.c | 19 +- ext/hal/nxp/mcux/drivers/imx/fsl_aoi.c | 78 +- ext/hal/nxp/mcux/drivers/imx/fsl_bee.c | 100 +- ext/hal/nxp/mcux/drivers/imx/fsl_cache.c | 221 +- ext/hal/nxp/mcux/drivers/imx/fsl_cmp.c | 106 +- ext/hal/nxp/mcux/drivers/imx/fsl_common.c | 55 +- ext/hal/nxp/mcux/drivers/imx/fsl_common.h | 70 +- ext/hal/nxp/mcux/drivers/imx/fsl_csi.c | 642 +- ext/hal/nxp/mcux/drivers/imx/fsl_csi.h | 191 +- ext/hal/nxp/mcux/drivers/imx/fsl_dcdc.c | 151 +- ext/hal/nxp/mcux/drivers/imx/fsl_dcp.c | 239 +- ext/hal/nxp/mcux/drivers/imx/fsl_dcp.h | 9 +- ext/hal/nxp/mcux/drivers/imx/fsl_dmamux.c | 18 +- ext/hal/nxp/mcux/drivers/imx/fsl_edma.c | 391 +- ext/hal/nxp/mcux/drivers/imx/fsl_edma.h | 6 +- ext/hal/nxp/mcux/drivers/imx/fsl_elcdif.c | 81 +- ext/hal/nxp/mcux/drivers/imx/fsl_enc.c | 129 +- ext/hal/nxp/mcux/drivers/imx/fsl_enet.c | 667 +- ext/hal/nxp/mcux/drivers/imx/fsl_ewm.c | 62 +- ext/hal/nxp/mcux/drivers/imx/fsl_flexcan.c | 757 +- ext/hal/nxp/mcux/drivers/imx/fsl_flexcan.h | 79 +- ext/hal/nxp/mcux/drivers/imx/fsl_flexio.c | 132 +- ext/hal/nxp/mcux/drivers/imx/fsl_flexio.h | 4 +- .../mcux/drivers/imx/fsl_flexio_i2c_master.c | 211 + ext/hal/nxp/mcux/drivers/imx/fsl_flexio_i2s.c | 228 +- ext/hal/nxp/mcux/drivers/imx/fsl_flexio_i2s.h | 8 +- .../mcux/drivers/imx/fsl_flexio_i2s_edma.c | 103 +- .../mcux/drivers/imx/fsl_flexio_i2s_edma.h | 8 +- ext/hal/nxp/mcux/drivers/imx/fsl_flexio_spi.c | 264 +- .../mcux/drivers/imx/fsl_flexio_spi_edma.c | 64 +- .../nxp/mcux/drivers/imx/fsl_flexio_uart.c | 251 +- .../nxp/mcux/drivers/imx/fsl_flexio_uart.h | 8 +- .../mcux/drivers/imx/fsl_flexio_uart_edma.c | 77 +- ext/hal/nxp/mcux/drivers/imx/fsl_flexram.c | 83 +- ext/hal/nxp/mcux/drivers/imx/fsl_flexram.h | 79 +- ext/hal/nxp/mcux/drivers/imx/fsl_flexspi.c | 148 +- ext/hal/nxp/mcux/drivers/imx/fsl_flexspi.h | 13 +- .../mcux/drivers/imx/fsl_flexspi_nor_boot.c | 51 + .../mcux/drivers/imx/fsl_flexspi_nor_boot.h | 111 + ext/hal/nxp/mcux/drivers/imx/fsl_gpc.c | 22 +- ext/hal/nxp/mcux/drivers/imx/fsl_gpio.c | 27 +- ext/hal/nxp/mcux/drivers/imx/fsl_gpt.c | 33 +- ext/hal/nxp/mcux/drivers/imx/fsl_kpp.c | 38 +- ext/hal/nxp/mcux/drivers/imx/fsl_lpi2c.c | 340 +- ext/hal/nxp/mcux/drivers/imx/fsl_lpi2c.h | 8 +- ext/hal/nxp/mcux/drivers/imx/fsl_lpi2c_edma.c | 50 + ext/hal/nxp/mcux/drivers/imx/fsl_lpspi.c | 279 +- ext/hal/nxp/mcux/drivers/imx/fsl_lpspi.h | 48 +- ext/hal/nxp/mcux/drivers/imx/fsl_lpspi_edma.c | 109 + ext/hal/nxp/mcux/drivers/imx/fsl_lpuart.c | 348 +- ext/hal/nxp/mcux/drivers/imx/fsl_lpuart.h | 11 +- .../nxp/mcux/drivers/imx/fsl_lpuart_edma.c | 76 + .../nxp/mcux/drivers/imx/fsl_lpuart_edma.h | 6 +- ext/hal/nxp/mcux/drivers/imx/fsl_pit.c | 26 + ext/hal/nxp/mcux/drivers/imx/fsl_pmu.c | 6 +- ext/hal/nxp/mcux/drivers/imx/fsl_pmu.h | 7 + ext/hal/nxp/mcux/drivers/imx/fsl_pwm.c | 150 +- ext/hal/nxp/mcux/drivers/imx/fsl_pxp.c | 188 +- ext/hal/nxp/mcux/drivers/imx/fsl_pxp.h | 24 +- ext/hal/nxp/mcux/drivers/imx/fsl_qtmr.c | 163 +- ext/hal/nxp/mcux/drivers/imx/fsl_rtwdog.c | 87 +- ext/hal/nxp/mcux/drivers/imx/fsl_rtwdog.h | 23 +- ext/hal/nxp/mcux/drivers/imx/fsl_sai.c | 759 +- ext/hal/nxp/mcux/drivers/imx/fsl_sai.h | 110 +- ext/hal/nxp/mcux/drivers/imx/fsl_sai_edma.c | 136 + ext/hal/nxp/mcux/drivers/imx/fsl_sai_edma.h | 2 +- ext/hal/nxp/mcux/drivers/imx/fsl_semc.c | 128 +- ext/hal/nxp/mcux/drivers/imx/fsl_semc.h | 8 +- ext/hal/nxp/mcux/drivers/imx/fsl_snvs_hp.c | 97 +- ext/hal/nxp/mcux/drivers/imx/fsl_snvs_hp.h | 70 +- ext/hal/nxp/mcux/drivers/imx/fsl_snvs_lp.c | 138 +- ext/hal/nxp/mcux/drivers/imx/fsl_snvs_lp.h | 2 +- ext/hal/nxp/mcux/drivers/imx/fsl_spdif.c | 183 +- ext/hal/nxp/mcux/drivers/imx/fsl_spdif_edma.c | 84 + ext/hal/nxp/mcux/drivers/imx/fsl_src.c | 9 +- ext/hal/nxp/mcux/drivers/imx/fsl_tempmon.c | 39 + ext/hal/nxp/mcux/drivers/imx/fsl_trng.c | 69 +- ext/hal/nxp/mcux/drivers/imx/fsl_trng.h | 11 +- ext/hal/nxp/mcux/drivers/imx/fsl_tsc.c | 60 + ext/hal/nxp/mcux/drivers/imx/fsl_usdhc.c | 254 +- ext/hal/nxp/mcux/drivers/imx/fsl_usdhc.h | 41 +- ext/hal/nxp/mcux/drivers/imx/fsl_wdog.c | 97 +- ext/hal/nxp/mcux/drivers/imx/fsl_wdog.h | 38 +- ext/hal/nxp/mcux/drivers/imx/fsl_xbara.c | 79 +- ext/hal/nxp/mcux/drivers/imx/fsl_xbarb.c | 28 +- .../nxp/mcux/drivers/kinetis/CMakeLists.txt | 2 +- ext/hal/nxp/mcux/drivers/kinetis/fsl_adc16.c | 161 +- ext/hal/nxp/mcux/drivers/kinetis/fsl_adc16.h | 28 +- ext/hal/nxp/mcux/drivers/kinetis/fsl_cmp.c | 134 +- ext/hal/nxp/mcux/drivers/kinetis/fsl_cmp.h | 28 +- ext/hal/nxp/mcux/drivers/kinetis/fsl_cmt.c | 112 +- ext/hal/nxp/mcux/drivers/kinetis/fsl_cmt.h | 28 +- ext/hal/nxp/mcux/drivers/kinetis/fsl_common.c | 57 +- ext/hal/nxp/mcux/drivers/kinetis/fsl_common.h | 189 +- ext/hal/nxp/mcux/drivers/kinetis/fsl_crc.c | 88 +- ext/hal/nxp/mcux/drivers/kinetis/fsl_crc.h | 28 +- ext/hal/nxp/mcux/drivers/kinetis/fsl_dac.c | 129 +- ext/hal/nxp/mcux/drivers/kinetis/fsl_dac.h | 28 +- ext/hal/nxp/mcux/drivers/kinetis/fsl_dmamux.c | 46 +- ext/hal/nxp/mcux/drivers/kinetis/fsl_dmamux.h | 28 +- ext/hal/nxp/mcux/drivers/kinetis/fsl_dspi.c | 623 +- ext/hal/nxp/mcux/drivers/kinetis/fsl_dspi.h | 132 +- .../nxp/mcux/drivers/kinetis/fsl_dspi_edma.c | 384 +- .../nxp/mcux/drivers/kinetis/fsl_dspi_edma.h | 47 +- ext/hal/nxp/mcux/drivers/kinetis/fsl_edma.c | 824 +- ext/hal/nxp/mcux/drivers/kinetis/fsl_edma.h | 69 +- ext/hal/nxp/mcux/drivers/kinetis/fsl_enet.c | 847 +- ext/hal/nxp/mcux/drivers/kinetis/fsl_enet.h | 75 +- ext/hal/nxp/mcux/drivers/kinetis/fsl_ewm.c | 90 +- ext/hal/nxp/mcux/drivers/kinetis/fsl_ewm.h | 28 +- ext/hal/nxp/mcux/drivers/kinetis/fsl_flash.c | 3432 -- ext/hal/nxp/mcux/drivers/kinetis/fsl_flash.h | 1373 +- .../nxp/mcux/drivers/kinetis/fsl_flexbus.c | 121 +- .../nxp/mcux/drivers/kinetis/fsl_flexbus.h | 33 +- .../nxp/mcux/drivers/kinetis/fsl_flexcan.c | 1428 +- .../nxp/mcux/drivers/kinetis/fsl_flexcan.h | 214 +- .../mcux/drivers/kinetis/fsl_ftfx_adapter.h | 397 + .../nxp/mcux/drivers/kinetis/fsl_ftfx_cache.c | 539 + .../nxp/mcux/drivers/kinetis/fsl_ftfx_cache.h | 116 + .../drivers/kinetis/fsl_ftfx_controller.c | 1376 + .../drivers/kinetis/fsl_ftfx_controller.h | 812 + .../mcux/drivers/kinetis/fsl_ftfx_features.h | 89 + .../nxp/mcux/drivers/kinetis/fsl_ftfx_flash.c | 1176 + .../nxp/mcux/drivers/kinetis/fsl_ftfx_flash.h | 611 + .../mcux/drivers/kinetis/fsl_ftfx_flexnvm.c | 410 + .../mcux/drivers/kinetis/fsl_ftfx_flexnvm.h | 564 + .../mcux/drivers/kinetis/fsl_ftfx_utilities.h | 66 + ext/hal/nxp/mcux/drivers/kinetis/fsl_ftm.c | 356 +- ext/hal/nxp/mcux/drivers/kinetis/fsl_ftm.h | 108 +- ext/hal/nxp/mcux/drivers/kinetis/fsl_gpio.c | 210 +- ext/hal/nxp/mcux/drivers/kinetis/fsl_gpio.h | 174 +- ext/hal/nxp/mcux/drivers/kinetis/fsl_i2c.c | 705 +- ext/hal/nxp/mcux/drivers/kinetis/fsl_i2c.h | 61 +- .../nxp/mcux/drivers/kinetis/fsl_i2c_edma.c | 77 +- .../nxp/mcux/drivers/kinetis/fsl_i2c_edma.h | 35 +- ext/hal/nxp/mcux/drivers/kinetis/fsl_llwu.c | 140 +- ext/hal/nxp/mcux/drivers/kinetis/fsl_llwu.h | 75 +- ext/hal/nxp/mcux/drivers/kinetis/fsl_lptmr.c | 75 +- ext/hal/nxp/mcux/drivers/kinetis/fsl_lptmr.h | 48 +- ext/hal/nxp/mcux/drivers/kinetis/fsl_pdb.c | 72 +- ext/hal/nxp/mcux/drivers/kinetis/fsl_pdb.h | 120 +- ext/hal/nxp/mcux/drivers/kinetis/fsl_pit.c | 66 +- ext/hal/nxp/mcux/drivers/kinetis/fsl_pit.h | 32 +- ext/hal/nxp/mcux/drivers/kinetis/fsl_pmc.c | 75 +- ext/hal/nxp/mcux/drivers/kinetis/fsl_pmc.h | 28 +- ext/hal/nxp/mcux/drivers/kinetis/fsl_port.h | 107 +- ext/hal/nxp/mcux/drivers/kinetis/fsl_rcm.c | 48 +- ext/hal/nxp/mcux/drivers/kinetis/fsl_rcm.h | 29 +- ext/hal/nxp/mcux/drivers/kinetis/fsl_rnga.c | 83 +- ext/hal/nxp/mcux/drivers/kinetis/fsl_rnga.h | 28 +- ext/hal/nxp/mcux/drivers/kinetis/fsl_rtc.c | 457 +- ext/hal/nxp/mcux/drivers/kinetis/fsl_rtc.h | 155 +- ext/hal/nxp/mcux/drivers/kinetis/fsl_sai.c | 1322 +- ext/hal/nxp/mcux/drivers/kinetis/fsl_sai.h | 265 +- .../nxp/mcux/drivers/kinetis/fsl_sai_edma.c | 195 +- .../nxp/mcux/drivers/kinetis/fsl_sai_edma.h | 57 +- ext/hal/nxp/mcux/drivers/kinetis/fsl_sdhc.c | 297 +- ext/hal/nxp/mcux/drivers/kinetis/fsl_sdhc.h | 92 +- ext/hal/nxp/mcux/drivers/kinetis/fsl_sim.c | 66 +- ext/hal/nxp/mcux/drivers/kinetis/fsl_sim.h | 84 +- ext/hal/nxp/mcux/drivers/kinetis/fsl_smc.c | 232 +- ext/hal/nxp/mcux/drivers/kinetis/fsl_smc.h | 45 +- ext/hal/nxp/mcux/drivers/kinetis/fsl_sysmpu.c | 167 +- ext/hal/nxp/mcux/drivers/kinetis/fsl_sysmpu.h | 36 +- ext/hal/nxp/mcux/drivers/kinetis/fsl_uart.c | 565 +- ext/hal/nxp/mcux/drivers/kinetis/fsl_uart.h | 85 +- .../nxp/mcux/drivers/kinetis/fsl_uart_edma.c | 118 +- .../nxp/mcux/drivers/kinetis/fsl_uart_edma.h | 33 +- ext/hal/nxp/mcux/drivers/kinetis/fsl_vref.c | 132 +- ext/hal/nxp/mcux/drivers/kinetis/fsl_vref.h | 28 +- ext/hal/nxp/mcux/drivers/kinetis/fsl_wdog.c | 135 +- ext/hal/nxp/mcux/drivers/kinetis/fsl_wdog.h | 28 +- ext/hal/nxp/mcux/drivers/lpc/CMakeLists.txt | 1 + ext/hal/nxp/mcux/drivers/lpc/fsl_adc.c | 189 +- ext/hal/nxp/mcux/drivers/lpc/fsl_adc.h | 118 +- ext/hal/nxp/mcux/drivers/lpc/fsl_common.c | 57 +- ext/hal/nxp/mcux/drivers/lpc/fsl_common.h | 189 +- ext/hal/nxp/mcux/drivers/lpc/fsl_crc.c | 84 +- ext/hal/nxp/mcux/drivers/lpc/fsl_crc.h | 28 +- ext/hal/nxp/mcux/drivers/lpc/fsl_ctimer.c | 254 +- ext/hal/nxp/mcux/drivers/lpc/fsl_ctimer.h | 150 +- ext/hal/nxp/mcux/drivers/lpc/fsl_dma.c | 400 +- ext/hal/nxp/mcux/drivers/lpc/fsl_dma.h | 259 +- ext/hal/nxp/mcux/drivers/lpc/fsl_dmic.c | 161 +- ext/hal/nxp/mcux/drivers/lpc/fsl_dmic.h | 44 +- ext/hal/nxp/mcux/drivers/lpc/fsl_dmic_dma.c | 85 +- ext/hal/nxp/mcux/drivers/lpc/fsl_dmic_dma.h | 37 +- ext/hal/nxp/mcux/drivers/lpc/fsl_flashiap.c | 155 +- ext/hal/nxp/mcux/drivers/lpc/fsl_flashiap.h | 40 +- ext/hal/nxp/mcux/drivers/lpc/fsl_flexcomm.c | 151 +- ext/hal/nxp/mcux/drivers/lpc/fsl_flexcomm.h | 34 +- ext/hal/nxp/mcux/drivers/lpc/fsl_fmeas.c | 39 +- ext/hal/nxp/mcux/drivers/lpc/fsl_fmeas.h | 28 +- ext/hal/nxp/mcux/drivers/lpc/fsl_fro_calib.h | 39 + ext/hal/nxp/mcux/drivers/lpc/fsl_gint.c | 173 +- ext/hal/nxp/mcux/drivers/lpc/fsl_gint.h | 28 +- ext/hal/nxp/mcux/drivers/lpc/fsl_gpio.c | 87 +- ext/hal/nxp/mcux/drivers/lpc/fsl_gpio.h | 69 +- ext/hal/nxp/mcux/drivers/lpc/fsl_i2c.c | 519 +- ext/hal/nxp/mcux/drivers/lpc/fsl_i2c.h | 89 +- ext/hal/nxp/mcux/drivers/lpc/fsl_i2c_dma.c | 79 +- ext/hal/nxp/mcux/drivers/lpc/fsl_i2c_dma.h | 34 +- ext/hal/nxp/mcux/drivers/lpc/fsl_i2s.c | 304 +- ext/hal/nxp/mcux/drivers/lpc/fsl_i2s.h | 58 +- ext/hal/nxp/mcux/drivers/lpc/fsl_i2s_dma.c | 117 +- ext/hal/nxp/mcux/drivers/lpc/fsl_i2s_dma.h | 41 +- ext/hal/nxp/mcux/drivers/lpc/fsl_iap.c | 458 + ext/hal/nxp/mcux/drivers/lpc/fsl_iap.h | 386 + ext/hal/nxp/mcux/drivers/lpc/fsl_inputmux.c | 103 +- ext/hal/nxp/mcux/drivers/lpc/fsl_inputmux.h | 43 +- .../drivers/lpc/fsl_inputmux_connections.h | 28 +- ext/hal/nxp/mcux/drivers/lpc/fsl_iocon.h | 192 +- ext/hal/nxp/mcux/drivers/lpc/fsl_mailbox.h | 78 +- ext/hal/nxp/mcux/drivers/lpc/fsl_mrt.c | 80 +- ext/hal/nxp/mcux/drivers/lpc/fsl_mrt.h | 48 +- ext/hal/nxp/mcux/drivers/lpc/fsl_pint.c | 339 +- ext/hal/nxp/mcux/drivers/lpc/fsl_pint.h | 52 +- ext/hal/nxp/mcux/drivers/lpc/fsl_power.c | 28 +- ext/hal/nxp/mcux/drivers/lpc/fsl_power.h | 59 +- ext/hal/nxp/mcux/drivers/lpc/fsl_reset.c | 105 +- ext/hal/nxp/mcux/drivers/lpc/fsl_reset.h | 49 +- ext/hal/nxp/mcux/drivers/lpc/fsl_rtc.c | 81 +- ext/hal/nxp/mcux/drivers/lpc/fsl_rtc.h | 28 +- ext/hal/nxp/mcux/drivers/lpc/fsl_sctimer.c | 221 +- ext/hal/nxp/mcux/drivers/lpc/fsl_sctimer.h | 42 +- ext/hal/nxp/mcux/drivers/lpc/fsl_spi.c | 393 +- ext/hal/nxp/mcux/drivers/lpc/fsl_spi.h | 176 +- ext/hal/nxp/mcux/drivers/lpc/fsl_spi_dma.c | 338 +- ext/hal/nxp/mcux/drivers/lpc/fsl_spi_dma.h | 47 +- ext/hal/nxp/mcux/drivers/lpc/fsl_usart.c | 268 +- ext/hal/nxp/mcux/drivers/lpc/fsl_usart.h | 73 +- ext/hal/nxp/mcux/drivers/lpc/fsl_usart_dma.c | 102 +- ext/hal/nxp/mcux/drivers/lpc/fsl_usart_dma.h | 34 +- ext/hal/nxp/mcux/drivers/lpc/fsl_utick.c | 110 +- ext/hal/nxp/mcux/drivers/lpc/fsl_utick.h | 30 +- ext/hal/nxp/mcux/drivers/lpc/fsl_wwdt.c | 130 +- ext/hal/nxp/mcux/drivers/lpc/fsl_wwdt.h | 32 +- soc/arm/nxp_lpc/lpc54xxx/soc.c | 10 +- 302 files changed, 140274 insertions(+), 23636 deletions(-) create mode 100644 ext/hal/nxp/mcux/boards/evkbimxrt1050/evkbimxrt1050_flexspi_nor_config.c create mode 100644 ext/hal/nxp/mcux/boards/evkbimxrt1050/evkbimxrt1050_flexspi_nor_config.h create mode 100644 ext/hal/nxp/mcux/boards/evkbimxrt1050/evkbimxrt1050_sdram_ini_dcd.c create mode 100644 ext/hal/nxp/mcux/boards/evkbimxrt1050/evkbimxrt1050_sdram_ini_dcd.h create mode 100644 ext/hal/nxp/mcux/boards/evkmimxrt1060/evkmimxrt1060_flexspi_nor_config.c create mode 100644 ext/hal/nxp/mcux/boards/evkmimxrt1060/evkmimxrt1060_flexspi_nor_config.h create mode 100644 ext/hal/nxp/mcux/boards/evkmimxrt1060/evkmimxrt1060_sdram_ini_dcd.c create mode 100644 ext/hal/nxp/mcux/boards/evkmimxrt1060/evkmimxrt1060_sdram_ini_dcd.h create mode 100644 ext/hal/nxp/mcux/devices/MIMXRT1051/fsl_clock.c create mode 100644 ext/hal/nxp/mcux/devices/MIMXRT1051/fsl_clock.h create mode 100644 ext/hal/nxp/mcux/devices/MIMXRT1051/fsl_iomuxc.h create mode 100644 ext/hal/nxp/mcux/drivers/imx/fsl_flexspi_nor_boot.c create mode 100644 ext/hal/nxp/mcux/drivers/imx/fsl_flexspi_nor_boot.h delete mode 100644 ext/hal/nxp/mcux/drivers/kinetis/fsl_flash.c create mode 100644 ext/hal/nxp/mcux/drivers/kinetis/fsl_ftfx_adapter.h create mode 100644 ext/hal/nxp/mcux/drivers/kinetis/fsl_ftfx_cache.c create mode 100644 ext/hal/nxp/mcux/drivers/kinetis/fsl_ftfx_cache.h create mode 100644 ext/hal/nxp/mcux/drivers/kinetis/fsl_ftfx_controller.c create mode 100644 ext/hal/nxp/mcux/drivers/kinetis/fsl_ftfx_controller.h create mode 100644 ext/hal/nxp/mcux/drivers/kinetis/fsl_ftfx_features.h create mode 100644 ext/hal/nxp/mcux/drivers/kinetis/fsl_ftfx_flash.c create mode 100644 ext/hal/nxp/mcux/drivers/kinetis/fsl_ftfx_flash.h create mode 100644 ext/hal/nxp/mcux/drivers/kinetis/fsl_ftfx_flexnvm.c create mode 100644 ext/hal/nxp/mcux/drivers/kinetis/fsl_ftfx_flexnvm.h create mode 100644 ext/hal/nxp/mcux/drivers/kinetis/fsl_ftfx_utilities.h mode change 100644 => 100755 ext/hal/nxp/mcux/drivers/kinetis/fsl_sim.c mode change 100644 => 100755 ext/hal/nxp/mcux/drivers/kinetis/fsl_sim.h create mode 100644 ext/hal/nxp/mcux/drivers/lpc/fsl_fro_calib.h create mode 100644 ext/hal/nxp/mcux/drivers/lpc/fsl_iap.c create mode 100644 ext/hal/nxp/mcux/drivers/lpc/fsl_iap.h diff --git a/drivers/flash/soc_flash_mcux.c b/drivers/flash/soc_flash_mcux.c index d9a2a6d33a2..8845c761a5c 100644 --- a/drivers/flash/soc_flash_mcux.c +++ b/drivers/flash/soc_flash_mcux.c @@ -22,6 +22,7 @@ struct flash_priv { * HACK: flash write protection is managed in software. */ struct k_sem write_lock; + u32_t pflash_block_base; }; /* @@ -44,7 +45,7 @@ static int flash_mcux_erase(struct device *dev, off_t offset, size_t len) return -EACCES; } - addr = offset + priv->config.PFlashBlockBase; + addr = offset + priv->pflash_block_base; key = irq_lock(); rc = FLASH_Erase(&priv->config, addr, len, kFLASH_ApiEraseKey); @@ -66,7 +67,7 @@ static int flash_mcux_read(struct device *dev, off_t offset, * hidden below the API: until the API export these ranges, we can not * do any generic validation */ - addr = offset + priv->config.PFlashBlockBase; + addr = offset + priv->pflash_block_base; memcpy(data, (void *) addr, len); @@ -85,10 +86,10 @@ static int flash_mcux_write(struct device *dev, off_t offset, return -EACCES; } - addr = offset + priv->config.PFlashBlockBase; + addr = offset + priv->pflash_block_base; key = irq_lock(); - rc = FLASH_Program(&priv->config, addr, (uint32_t *) data, len); + rc = FLASH_Program(&priv->config, addr, (uint8_t *) data, len); irq_unlock(key); k_sem_give(&priv->write_lock); @@ -141,12 +142,17 @@ static const struct flash_driver_api flash_mcux_api = { static int flash_mcux_init(struct device *dev) { struct flash_priv *priv = dev->driver_data; + uint32_t pflash_block_base; status_t rc; k_sem_init(&priv->write_lock, 0, 1); rc = FLASH_Init(&priv->config); + FLASH_GetProperty(&priv->config, kFLASH_PropertyPflash0BlockBaseAddr, + &pflash_block_base); + priv->pflash_block_base = (u32_t) pflash_block_base; + return (rc == kStatus_Success) ? 0 : -EIO; } diff --git a/ext/hal/nxp/mcux/CMakeLists.txt b/ext/hal/nxp/mcux/CMakeLists.txt index 19d969112a6..bb939900446 100644 --- a/ext/hal/nxp/mcux/CMakeLists.txt +++ b/ext/hal/nxp/mcux/CMakeLists.txt @@ -7,6 +7,8 @@ if("${MCUX_DEVICE}" STREQUAL "LPC54114") elseif("${MCUX_DEVICE}" STREQUAL "LPC54114_M0") set(MCUX_CPU CPU_${CONFIG_SOC_PART_NUMBER}_cm0plus) set(MCUX_DEVICE LPC54114) +elseif("${MCUX_DEVICE}" STREQUAL "MIMXRT1052") + string(REGEX REPLACE "(.*)A$" "CPU_\\1B" MCUX_CPU ${CONFIG_SOC_PART_NUMBER}) else() set(MCUX_CPU CPU_${CONFIG_SOC_PART_NUMBER}) endif() diff --git a/ext/hal/nxp/mcux/README b/ext/hal/nxp/mcux/README index 0fd2eade568..ea8c3b540ee 100644 --- a/ext/hal/nxp/mcux/README +++ b/ext/hal/nxp/mcux/README @@ -15,12 +15,12 @@ Status: SoC Version (Release Date) Tag ---------------------------------------------------------------------------- - LPC54114 KSDK 2.2.1 - MIMXRT1051 KSDK 2.3.0 - MIMXRT1052 KSDK 2.3.0 - MIMXRT1061 KSDK 2.4.0 (2018-09-04) REL_SDK_2.4.0_RT1060_RFP - MIMXRT1062 KSDK 2.4.0 (2018-09-04) REL_SDK_2.4.0_RT1060_RFP - MK64F12 KSDK 2.2.0 + LPC54114 SDK 2.5.0 (2018-12-17) REL_2.5.0_REL9_RFP_RC3_7_1 + MIMXRT1051 SDK 2.5.0 (2018-12-17) REL_2.5.0_REL9_RFP_RC3_7_1 + MIMXRT1052 SDK 2.5.0 (2018-12-17) REL_2.5.0_REL9_RFP_RC3_7_1 + MIMXRT1061 SDK 2.5.0 (2018-12-17) REL_2.5.0_REL9_RFP_RC3_7_1 + MIMXRT1062 SDK 2.5.0 (2018-12-17) REL_2.5.0_REL9_RFP_RC3_7_1 + MK64F12 SDK 2.5.0 (2018-12-17) REL_2.5.0_REL9_RFP_RC3_7_1 MKL25Z4 KSDK 2.2.0 (2017-06-29) REL6.GA.RC4.6_ISSDK1.6GAFIX.GEN MKW21Z4 KSDK 2.2.0 (2018-01-19) release_conn_ksdk_2.2_kw41z_1.0.4_stage_final MKW22D5 KSDK 2.2.0 (2017-03-21) REL_SDK_REL6_2.0.0_GA_RC4_6 diff --git a/ext/hal/nxp/mcux/boards/evkbimxrt1050/evkbimxrt1050_flexspi_nor_config.c b/ext/hal/nxp/mcux/boards/evkbimxrt1050/evkbimxrt1050_flexspi_nor_config.c new file mode 100644 index 00000000000..3486c84963e --- /dev/null +++ b/ext/hal/nxp/mcux/boards/evkbimxrt1050/evkbimxrt1050_flexspi_nor_config.c @@ -0,0 +1,55 @@ +/* + * Copyright 2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "evkbimxrt1050_flexspi_nor_config.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.xip_board" +#endif + +/******************************************************************************* + * Code + ******************************************************************************/ +#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1) +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__) +__attribute__((section(".boot_hdr.conf"))) +#elif defined(__ICCARM__) +#pragma location = ".boot_hdr.conf" +#endif + +const flexspi_nor_config_t hyperflash_config = { + .memConfig = + { + .tag = FLEXSPI_CFG_BLK_TAG, + .version = FLEXSPI_CFG_BLK_VERSION, + .readSampleClkSrc = kFlexSPIReadSampleClk_ExternalInputFromDqsPad, + .csHoldTime = 3u, + .csSetupTime = 3u, + .columnAddressWidth = 3u, + // Enable DDR mode, Wordaddassable, Safe configuration, Differential clock + .controllerMiscOption = + (1u << kFlexSpiMiscOffset_DdrModeEnable) | (1u << kFlexSpiMiscOffset_WordAddressableEnable) | + (1u << kFlexSpiMiscOffset_SafeConfigFreqEnable) | (1u << kFlexSpiMiscOffset_DiffClkEnable), + .sflashPadType = kSerialFlash_8Pads, + .serialClkFreq = kFlexSpiSerialClk_133MHz, + .sflashA1Size = 64u * 1024u * 1024u, + .dataValidTime = {16u, 16u}, + .lookupTable = + { + // Read LUTs + FLEXSPI_LUT_SEQ(CMD_DDR, FLEXSPI_8PAD, 0xA0, RADDR_DDR, FLEXSPI_8PAD, 0x18), + FLEXSPI_LUT_SEQ(CADDR_DDR, FLEXSPI_8PAD, 0x10, DUMMY_DDR, FLEXSPI_8PAD, 0x06), + FLEXSPI_LUT_SEQ(READ_DDR, FLEXSPI_8PAD, 0x04, STOP, FLEXSPI_1PAD, 0x0), + }, + }, + .pageSize = 512u, + .sectorSize = 256u * 1024u, + .blockSize = 256u * 1024u, + .isUniformBlockSize = true, +}; +#endif /* XIP_BOOT_HEADER_ENABLE */ diff --git a/ext/hal/nxp/mcux/boards/evkbimxrt1050/evkbimxrt1050_flexspi_nor_config.h b/ext/hal/nxp/mcux/boards/evkbimxrt1050/evkbimxrt1050_flexspi_nor_config.h new file mode 100644 index 00000000000..7b422d01b91 --- /dev/null +++ b/ext/hal/nxp/mcux/boards/evkbimxrt1050/evkbimxrt1050_flexspi_nor_config.h @@ -0,0 +1,269 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __EVKBIMXRT1050_FLEXSPI_NOR_CONFIG__ +#define __EVKBIMXRT1050_FLEXSPI_NOR_CONFIG__ + +#include +#include +#include "fsl_common.h" + +/*! @name Driver version */ +/*@{*/ +/*! @brief XIP_BOARD driver version 2.0.0. */ +#define FSL_XIP_BOARD_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) +/*@}*/ + +/* FLEXSPI memory config block related defintions */ +#define FLEXSPI_CFG_BLK_TAG (0x42464346UL) // ascii "FCFB" Big Endian +#define FLEXSPI_CFG_BLK_VERSION (0x56010400UL) // V1.4.0 +#define FLEXSPI_CFG_BLK_SIZE (512) + +/* FLEXSPI Feature related definitions */ +#define FLEXSPI_FEATURE_HAS_PARALLEL_MODE 1 + +/* Lookup table related defintions */ +#define CMD_INDEX_READ 0 +#define CMD_INDEX_READSTATUS 1 +#define CMD_INDEX_WRITEENABLE 2 +#define CMD_INDEX_WRITE 4 + +#define CMD_LUT_SEQ_IDX_READ 0 +#define CMD_LUT_SEQ_IDX_READSTATUS 1 +#define CMD_LUT_SEQ_IDX_WRITEENABLE 3 +#define CMD_LUT_SEQ_IDX_WRITE 9 + +#define CMD_SDR 0x01 +#define CMD_DDR 0x21 +#define RADDR_SDR 0x02 +#define RADDR_DDR 0x22 +#define CADDR_SDR 0x03 +#define CADDR_DDR 0x23 +#define MODE1_SDR 0x04 +#define MODE1_DDR 0x24 +#define MODE2_SDR 0x05 +#define MODE2_DDR 0x25 +#define MODE4_SDR 0x06 +#define MODE4_DDR 0x26 +#define MODE8_SDR 0x07 +#define MODE8_DDR 0x27 +#define WRITE_SDR 0x08 +#define WRITE_DDR 0x28 +#define READ_SDR 0x09 +#define READ_DDR 0x29 +#define LEARN_SDR 0x0A +#define LEARN_DDR 0x2A +#define DATSZ_SDR 0x0B +#define DATSZ_DDR 0x2B +#define DUMMY_SDR 0x0C +#define DUMMY_DDR 0x2C +#define DUMMY_RWDS_SDR 0x0D +#define DUMMY_RWDS_DDR 0x2D +#define JMP_ON_CS 0x1F +#define STOP 0 + +#define FLEXSPI_1PAD 0 +#define FLEXSPI_2PAD 1 +#define FLEXSPI_4PAD 2 +#define FLEXSPI_8PAD 3 + +#define FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) \ + (FLEXSPI_LUT_OPERAND0(op0) | FLEXSPI_LUT_NUM_PADS0(pad0) | FLEXSPI_LUT_OPCODE0(cmd0) | FLEXSPI_LUT_OPERAND1(op1) | \ + FLEXSPI_LUT_NUM_PADS1(pad1) | FLEXSPI_LUT_OPCODE1(cmd1)) + +//!@brief Definitions for FlexSPI Serial Clock Frequency +typedef enum _FlexSpiSerialClockFreq +{ + kFlexSpiSerialClk_30MHz = 1, + kFlexSpiSerialClk_50MHz = 2, + kFlexSpiSerialClk_60MHz = 3, + kFlexSpiSerialClk_75MHz = 4, + kFlexSpiSerialClk_80MHz = 5, + kFlexSpiSerialClk_100MHz = 6, + kFlexSpiSerialClk_133MHz = 7, + kFlexSpiSerialClk_166MHz = 8, + kFlexSpiSerialClk_200MHz = 9, +} flexspi_serial_clk_freq_t; + +//!@brief FlexSPI clock configuration type +enum +{ + kFlexSpiClk_SDR, //!< Clock configure for SDR mode + kFlexSpiClk_DDR, //!< Clock configurat for DDR mode +}; + +//!@brief FlexSPI Read Sample Clock Source definition +typedef enum _FlashReadSampleClkSource +{ + kFlexSPIReadSampleClk_LoopbackInternally = 0, + kFlexSPIReadSampleClk_LoopbackFromDqsPad = 1, + kFlexSPIReadSampleClk_LoopbackFromSckPad = 2, + kFlexSPIReadSampleClk_ExternalInputFromDqsPad = 3, +} flexspi_read_sample_clk_t; + +//!@brief Misc feature bit definitions +enum +{ + kFlexSpiMiscOffset_DiffClkEnable = 0, //!< Bit for Differential clock enable + kFlexSpiMiscOffset_Ck2Enable = 1, //!< Bit for CK2 enable + kFlexSpiMiscOffset_ParallelEnable = 2, //!< Bit for Parallel mode enable + kFlexSpiMiscOffset_WordAddressableEnable = 3, //!< Bit for Word Addressable enable + kFlexSpiMiscOffset_SafeConfigFreqEnable = 4, //!< Bit for Safe Configuration Frequency enable + kFlexSpiMiscOffset_PadSettingOverrideEnable = 5, //!< Bit for Pad setting override enable + kFlexSpiMiscOffset_DdrModeEnable = 6, //!< Bit for DDR clock confiuration indication. +}; + +//!@brief Flash Type Definition +enum +{ + kFlexSpiDeviceType_SerialNOR = 1, //!< Flash devices are Serial NOR + kFlexSpiDeviceType_SerialNAND = 2, //!< Flash devices are Serial NAND + kFlexSpiDeviceType_SerialRAM = 3, //!< Flash devices are Serial RAM/HyperFLASH + kFlexSpiDeviceType_MCP_NOR_NAND = 0x12, //!< Flash device is MCP device, A1 is Serial NOR, A2 is Serial NAND + kFlexSpiDeviceType_MCP_NOR_RAM = 0x13, //!< Flash deivce is MCP device, A1 is Serial NOR, A2 is Serial RAMs +}; + +//!@brief Flash Pad Definitions +enum +{ + kSerialFlash_1Pad = 1, + kSerialFlash_2Pads = 2, + kSerialFlash_4Pads = 4, + kSerialFlash_8Pads = 8, +}; + +//!@brief FlexSPI LUT Sequence structure +typedef struct _lut_sequence +{ + uint8_t seqNum; //!< Sequence Number, valid number: 1-16 + uint8_t seqId; //!< Sequence Index, valid number: 0-15 + uint16_t reserved; +} flexspi_lut_seq_t; + +//!@brief Flash Configuration Command Type +enum +{ + kDeviceConfigCmdType_Generic, //!< Generic command, for example: configure dummy cycles, drive strength, etc + kDeviceConfigCmdType_QuadEnable, //!< Quad Enable command + kDeviceConfigCmdType_Spi2Xpi, //!< Switch from SPI to DPI/QPI/OPI mode + kDeviceConfigCmdType_Xpi2Spi, //!< Switch from DPI/QPI/OPI to SPI mode + kDeviceConfigCmdType_Spi2NoCmd, //!< Switch to 0-4-4/0-8-8 mode + kDeviceConfigCmdType_Reset, //!< Reset device command +}; + +//!@brief FlexSPI Memory Configuration Block +typedef struct _FlexSPIConfig +{ + uint32_t tag; //!< [0x000-0x003] Tag, fixed value 0x42464346UL + uint32_t version; //!< [0x004-0x007] Version,[31:24] -'V', [23:16] - Major, [15:8] - Minor, [7:0] - bugfix + uint32_t reserved0; //!< [0x008-0x00b] Reserved for future use + uint8_t readSampleClkSrc; //!< [0x00c-0x00c] Read Sample Clock Source, valid value: 0/1/3 + uint8_t csHoldTime; //!< [0x00d-0x00d] CS hold time, default value: 3 + uint8_t csSetupTime; //!< [0x00e-0x00e] CS setup time, default value: 3 + uint8_t columnAddressWidth; //!< [0x00f-0x00f] Column Address with, for HyperBus protocol, it is fixed to 3, For + //! Serial NAND, need to refer to datasheet + uint8_t deviceModeCfgEnable; //!< [0x010-0x010] Device Mode Configure enable flag, 1 - Enable, 0 - Disable + uint8_t deviceModeType; //!< [0x011-0x011] Specify the configuration command type:Quad Enable, DPI/QPI/OPI switch, + //! Generic configuration, etc. + uint16_t waitTimeCfgCommands; //!< [0x012-0x013] Wait time for all configuration commands, unit: 100us, Used for + //! DPI/QPI/OPI switch or reset command + flexspi_lut_seq_t deviceModeSeq; //!< [0x014-0x017] Device mode sequence info, [7:0] - LUT sequence id, [15:8] - LUt + //! sequence number, [31:16] Reserved + uint32_t deviceModeArg; //!< [0x018-0x01b] Argument/Parameter for device configuration + uint8_t configCmdEnable; //!< [0x01c-0x01c] Configure command Enable Flag, 1 - Enable, 0 - Disable + uint8_t configModeType[3]; //!< [0x01d-0x01f] Configure Mode Type, similar as deviceModeTpe + flexspi_lut_seq_t + configCmdSeqs[3]; //!< [0x020-0x02b] Sequence info for Device Configuration command, similar as deviceModeSeq + uint32_t reserved1; //!< [0x02c-0x02f] Reserved for future use + uint32_t configCmdArgs[3]; //!< [0x030-0x03b] Arguments/Parameters for device Configuration commands + uint32_t reserved2; //!< [0x03c-0x03f] Reserved for future use + uint32_t controllerMiscOption; //!< [0x040-0x043] Controller Misc Options, see Misc feature bit definitions for more + //! details + uint8_t deviceType; //!< [0x044-0x044] Device Type: See Flash Type Definition for more details + uint8_t sflashPadType; //!< [0x045-0x045] Serial Flash Pad Type: 1 - Single, 2 - Dual, 4 - Quad, 8 - Octal + uint8_t serialClkFreq; //!< [0x046-0x046] Serial Flash Frequencey, device specific definitions, See System Boot + //! Chapter for more details + uint8_t lutCustomSeqEnable; //!< [0x047-0x047] LUT customization Enable, it is required if the program/erase cannot + //! be done using 1 LUT sequence, currently, only applicable to HyperFLASH + uint32_t reserved3[2]; //!< [0x048-0x04f] Reserved for future use + uint32_t sflashA1Size; //!< [0x050-0x053] Size of Flash connected to A1 + uint32_t sflashA2Size; //!< [0x054-0x057] Size of Flash connected to A2 + uint32_t sflashB1Size; //!< [0x058-0x05b] Size of Flash connected to B1 + uint32_t sflashB2Size; //!< [0x05c-0x05f] Size of Flash connected to B2 + uint32_t csPadSettingOverride; //!< [0x060-0x063] CS pad setting override value + uint32_t sclkPadSettingOverride; //!< [0x064-0x067] SCK pad setting override value + uint32_t dataPadSettingOverride; //!< [0x068-0x06b] data pad setting override value + uint32_t dqsPadSettingOverride; //!< [0x06c-0x06f] DQS pad setting override value + uint32_t timeoutInMs; //!< [0x070-0x073] Timeout threshold for read status command + uint32_t commandInterval; //!< [0x074-0x077] CS deselect interval between two commands + uint16_t dataValidTime[2]; //!< [0x078-0x07b] CLK edge to data valid time for PORT A and PORT B, in terms of 0.1ns + uint16_t busyOffset; //!< [0x07c-0x07d] Busy offset, valid value: 0-31 + uint16_t busyBitPolarity; //!< [0x07e-0x07f] Busy flag polarity, 0 - busy flag is 1 when flash device is busy, 1 - + //! busy flag is 0 when flash device is busy + uint32_t lookupTable[64]; //!< [0x080-0x17f] Lookup table holds Flash command sequences + flexspi_lut_seq_t lutCustomSeq[12]; //!< [0x180-0x1af] Customizable LUT Sequences + uint32_t reserved4[4]; //!< [0x1b0-0x1bf] Reserved for future use +} flexspi_mem_config_t; + +/* */ +#define NOR_CMD_INDEX_READ CMD_INDEX_READ //!< 0 +#define NOR_CMD_INDEX_READSTATUS CMD_INDEX_READSTATUS //!< 1 +#define NOR_CMD_INDEX_WRITEENABLE CMD_INDEX_WRITEENABLE //!< 2 +#define NOR_CMD_INDEX_ERASESECTOR 3 //!< 3 +#define NOR_CMD_INDEX_PAGEPROGRAM CMD_INDEX_WRITE //!< 4 +#define NOR_CMD_INDEX_CHIPERASE 5 //!< 5 +#define NOR_CMD_INDEX_DUMMY 6 //!< 6 +#define NOR_CMD_INDEX_ERASEBLOCK 7 //!< 7 + +#define NOR_CMD_LUT_SEQ_IDX_READ CMD_LUT_SEQ_IDX_READ //!< 0 READ LUT sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_READSTATUS \ + CMD_LUT_SEQ_IDX_READSTATUS //!< 1 Read Status LUT sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_READSTATUS_XPI \ + 2 //!< 2 Read status DPI/QPI/OPI sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE \ + CMD_LUT_SEQ_IDX_WRITEENABLE //!< 3 Write Enable sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE_XPI \ + 4 //!< 4 Write Enable DPI/QPI/OPI sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_ERASESECTOR 5 //!< 5 Erase Sector sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_ERASEBLOCK 8 //!< 8 Erase Block sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM \ + CMD_LUT_SEQ_IDX_WRITE //!< 9 Program sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_CHIPERASE 11 //!< 11 Chip Erase sequence in lookupTable id stored in config block +#define NOR_CMD_LUT_SEQ_IDX_READ_SFDP 13 //!< 13 Read SFDP sequence in lookupTable id stored in config block +#define NOR_CMD_LUT_SEQ_IDX_RESTORE_NOCMD \ + 14 //!< 14 Restore 0-4-4/0-8-8 mode sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_EXIT_NOCMD \ + 15 //!< 15 Exit 0-4-4/0-8-8 mode sequence id in lookupTable stored in config blobk + +/* + * Serial NOR configuration block + */ +typedef struct _flexspi_nor_config +{ + flexspi_mem_config_t memConfig; //!< Common memory configuration info via FlexSPI + uint32_t pageSize; //!< Page size of Serial NOR + uint32_t sectorSize; //!< Sector size of Serial NOR + uint8_t ipcmdSerialClkFreq; //!< Clock frequency for IP command + uint8_t isUniformBlockSize; //!< Sector/Block size is the same + uint8_t reserved0[2]; //!< Reserved for future use + uint8_t serialNorType; //!< Serial NOR Flash type: 0/1/2/3 + uint8_t needExitNoCmdMode; //!< Need to exit NoCmd mode before other IP command + uint8_t halfClkForNonReadCmd; //!< Half the Serial Clock for non-read command: true/false + uint8_t needRestoreNoCmdMode; //!< Need to Restore NoCmd mode after IP commmand execution + uint32_t blockSize; //!< Block size + uint32_t reserve2[11]; //!< Reserved for future use +} flexspi_nor_config_t; + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef __cplusplus +} +#endif +#endif /* __EVKBIMXRT1050_FLEXSPI_NOR_CONFIG__ */ diff --git a/ext/hal/nxp/mcux/boards/evkbimxrt1050/evkbimxrt1050_sdram_ini_dcd.c b/ext/hal/nxp/mcux/boards/evkbimxrt1050/evkbimxrt1050_sdram_ini_dcd.c new file mode 100644 index 00000000000..c42cc0a1c2d --- /dev/null +++ b/ext/hal/nxp/mcux/boards/evkbimxrt1050/evkbimxrt1050_sdram_ini_dcd.c @@ -0,0 +1,1105 @@ +/* + * Copyright 2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "evkbimxrt1050_sdram_ini_dcd.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.xip_board" +#endif + +#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1) +#if defined(XIP_BOOT_HEADER_DCD_ENABLE) && (XIP_BOOT_HEADER_DCD_ENABLE == 1) +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__) +__attribute__((section(".boot_hdr.dcd_data"))) +#elif defined(__ICCARM__) +#pragma location = ".boot_hdr.dcd_data" +#endif +/************************************* + * DCD Data + *************************************/ +const uint8_t dcd_data[] = { + /*0000*/ DCD_TAG_HEADER, + 0x04, + 0x30, + 0x41, + 0xCC, + 0x03, + 0xAC, + 0x04, + 0x40, + 0x0F, + 0xC0, + 0x68, + 0xFF, + 0xFF, + 0xFF, + 0xFF, + /*0010*/ 0x40, + 0x0F, + 0xC0, + 0x6C, + 0xFF, + 0xFF, + 0xFF, + 0xFF, + 0x40, + 0x0F, + 0xC0, + 0x70, + 0xFF, + 0xFF, + 0xFF, + 0xFF, + /*0020*/ 0x40, + 0x0F, + 0xC0, + 0x74, + 0xFF, + 0xFF, + 0xFF, + 0xFF, + 0x40, + 0x0F, + 0xC0, + 0x78, + 0xFF, + 0xFF, + 0xFF, + 0xFF, + /*0030*/ 0x40, + 0x0F, + 0xC0, + 0x7C, + 0xFF, + 0xFF, + 0xFF, + 0xFF, + 0x40, + 0x0F, + 0xC0, + 0x80, + 0xFF, + 0xFF, + 0xFF, + 0xFF, + /*0040*/ 0x40, + 0x0D, + 0x80, + 0x30, + 0x00, + 0x00, + 0x20, + 0x01, + 0x40, + 0x0D, + 0x81, + 0x00, + 0x00, + 0x1D, + 0x00, + 0x00, + /*0050*/ 0x40, + 0x0F, + 0xC0, + 0x14, + 0x00, + 0x01, + 0x0D, + 0x40, + 0x40, + 0x1F, + 0x80, + 0x14, + 0x00, + 0x00, + 0x00, + 0x00, + /*0060*/ 0x40, + 0x1F, + 0x80, + 0x18, + 0x00, + 0x00, + 0x00, + 0x00, + 0x40, + 0x1F, + 0x80, + 0x1C, + 0x00, + 0x00, + 0x00, + 0x00, + /*0070*/ 0x40, + 0x1F, + 0x80, + 0x20, + 0x00, + 0x00, + 0x00, + 0x00, + 0x40, + 0x1F, + 0x80, + 0x24, + 0x00, + 0x00, + 0x00, + 0x00, + /*0080*/ 0x40, + 0x1F, + 0x80, + 0x28, + 0x00, + 0x00, + 0x00, + 0x00, + 0x40, + 0x1F, + 0x80, + 0x2C, + 0x00, + 0x00, + 0x00, + 0x00, + /*0090*/ 0x40, + 0x1F, + 0x80, + 0x30, + 0x00, + 0x00, + 0x00, + 0x00, + 0x40, + 0x1F, + 0x80, + 0x34, + 0x00, + 0x00, + 0x00, + 0x00, + /*00a0*/ 0x40, + 0x1F, + 0x80, + 0x38, + 0x00, + 0x00, + 0x00, + 0x00, + 0x40, + 0x1F, + 0x80, + 0x3C, + 0x00, + 0x00, + 0x00, + 0x00, + /*00b0*/ 0x40, + 0x1F, + 0x80, + 0x40, + 0x00, + 0x00, + 0x00, + 0x00, + 0x40, + 0x1F, + 0x80, + 0x44, + 0x00, + 0x00, + 0x00, + 0x00, + /*00c0*/ 0x40, + 0x1F, + 0x80, + 0x48, + 0x00, + 0x00, + 0x00, + 0x00, + 0x40, + 0x1F, + 0x80, + 0x4C, + 0x00, + 0x00, + 0x00, + 0x00, + /*00d0*/ 0x40, + 0x1F, + 0x80, + 0x50, + 0x00, + 0x00, + 0x00, + 0x00, + 0x40, + 0x1F, + 0x80, + 0x54, + 0x00, + 0x00, + 0x00, + 0x00, + /*00e0*/ 0x40, + 0x1F, + 0x80, + 0x58, + 0x00, + 0x00, + 0x00, + 0x00, + 0x40, + 0x1F, + 0x80, + 0x5C, + 0x00, + 0x00, + 0x00, + 0x00, + /*00f0*/ 0x40, + 0x1F, + 0x80, + 0x60, + 0x00, + 0x00, + 0x00, + 0x00, + 0x40, + 0x1F, + 0x80, + 0x64, + 0x00, + 0x00, + 0x00, + 0x00, + /*0100*/ 0x40, + 0x1F, + 0x80, + 0x68, + 0x00, + 0x00, + 0x00, + 0x00, + 0x40, + 0x1F, + 0x80, + 0x6C, + 0x00, + 0x00, + 0x00, + 0x00, + /*0110*/ 0x40, + 0x1F, + 0x80, + 0x70, + 0x00, + 0x00, + 0x00, + 0x00, + 0x40, + 0x1F, + 0x80, + 0x74, + 0x00, + 0x00, + 0x00, + 0x00, + /*0120*/ 0x40, + 0x1F, + 0x80, + 0x78, + 0x00, + 0x00, + 0x00, + 0x00, + 0x40, + 0x1F, + 0x80, + 0x7C, + 0x00, + 0x00, + 0x00, + 0x00, + /*0130*/ 0x40, + 0x1F, + 0x80, + 0x80, + 0x00, + 0x00, + 0x00, + 0x00, + 0x40, + 0x1F, + 0x80, + 0x84, + 0x00, + 0x00, + 0x00, + 0x00, + /*0140*/ 0x40, + 0x1F, + 0x80, + 0x88, + 0x00, + 0x00, + 0x00, + 0x00, + 0x40, + 0x1F, + 0x80, + 0x8C, + 0x00, + 0x00, + 0x00, + 0x00, + /*0150*/ 0x40, + 0x1F, + 0x80, + 0x90, + 0x00, + 0x00, + 0x00, + 0x00, + 0x40, + 0x1F, + 0x80, + 0x94, + 0x00, + 0x00, + 0x00, + 0x00, + /*0160*/ 0x40, + 0x1F, + 0x80, + 0x98, + 0x00, + 0x00, + 0x00, + 0x00, + 0x40, + 0x1F, + 0x80, + 0x9C, + 0x00, + 0x00, + 0x00, + 0x00, + /*0170*/ 0x40, + 0x1F, + 0x80, + 0xA0, + 0x00, + 0x00, + 0x00, + 0x00, + 0x40, + 0x1F, + 0x80, + 0xA4, + 0x00, + 0x00, + 0x00, + 0x00, + /*0180*/ 0x40, + 0x1F, + 0x80, + 0xA8, + 0x00, + 0x00, + 0x00, + 0x00, + 0x40, + 0x1F, + 0x80, + 0xAC, + 0x00, + 0x00, + 0x00, + 0x00, + /*0190*/ 0x40, + 0x1F, + 0x80, + 0xB0, + 0x00, + 0x00, + 0x00, + 0x10, + 0x40, + 0x1F, + 0x80, + 0xB4, + 0x00, + 0x00, + 0x00, + 0x00, + /*01a0*/ 0x40, + 0x1F, + 0x80, + 0xB8, + 0x00, + 0x00, + 0x00, + 0x00, + 0x40, + 0x1F, + 0x82, + 0x04, + 0x00, + 0x01, + 0x10, + 0xF9, + /*01b0*/ 0x40, + 0x1F, + 0x82, + 0x08, + 0x00, + 0x01, + 0x10, + 0xF9, + 0x40, + 0x1F, + 0x82, + 0x0C, + 0x00, + 0x01, + 0x10, + 0xF9, + /*01c0*/ 0x40, + 0x1F, + 0x82, + 0x10, + 0x00, + 0x01, + 0x10, + 0xF9, + 0x40, + 0x1F, + 0x82, + 0x14, + 0x00, + 0x01, + 0x10, + 0xF9, + /*01d0*/ 0x40, + 0x1F, + 0x82, + 0x18, + 0x00, + 0x01, + 0x10, + 0xF9, + 0x40, + 0x1F, + 0x82, + 0x1C, + 0x00, + 0x01, + 0x10, + 0xF9, + /*01e0*/ 0x40, + 0x1F, + 0x82, + 0x20, + 0x00, + 0x01, + 0x10, + 0xF9, + 0x40, + 0x1F, + 0x82, + 0x24, + 0x00, + 0x01, + 0x10, + 0xF9, + /*01f0*/ 0x40, + 0x1F, + 0x82, + 0x28, + 0x00, + 0x01, + 0x10, + 0xF9, + 0x40, + 0x1F, + 0x82, + 0x2C, + 0x00, + 0x01, + 0x10, + 0xF9, + /*0200*/ 0x40, + 0x1F, + 0x82, + 0x30, + 0x00, + 0x01, + 0x10, + 0xF9, + 0x40, + 0x1F, + 0x82, + 0x34, + 0x00, + 0x01, + 0x10, + 0xF9, + /*0210*/ 0x40, + 0x1F, + 0x82, + 0x38, + 0x00, + 0x01, + 0x10, + 0xF9, + 0x40, + 0x1F, + 0x82, + 0x3C, + 0x00, + 0x01, + 0x10, + 0xF9, + /*0220*/ 0x40, + 0x1F, + 0x82, + 0x40, + 0x00, + 0x01, + 0x10, + 0xF9, + 0x40, + 0x1F, + 0x82, + 0x44, + 0x00, + 0x01, + 0x10, + 0xF9, + /*0230*/ 0x40, + 0x1F, + 0x82, + 0x48, + 0x00, + 0x01, + 0x10, + 0xF9, + 0x40, + 0x1F, + 0x82, + 0x4C, + 0x00, + 0x01, + 0x10, + 0xF9, + /*0240*/ 0x40, + 0x1F, + 0x82, + 0x50, + 0x00, + 0x01, + 0x10, + 0xF9, + 0x40, + 0x1F, + 0x82, + 0x54, + 0x00, + 0x01, + 0x10, + 0xF9, + /*0250*/ 0x40, + 0x1F, + 0x82, + 0x58, + 0x00, + 0x01, + 0x10, + 0xF9, + 0x40, + 0x1F, + 0x82, + 0x5C, + 0x00, + 0x01, + 0x10, + 0xF9, + /*0260*/ 0x40, + 0x1F, + 0x82, + 0x60, + 0x00, + 0x01, + 0x10, + 0xF9, + 0x40, + 0x1F, + 0x82, + 0x64, + 0x00, + 0x01, + 0x10, + 0xF9, + /*0270*/ 0x40, + 0x1F, + 0x82, + 0x68, + 0x00, + 0x01, + 0x10, + 0xF9, + 0x40, + 0x1F, + 0x82, + 0x6C, + 0x00, + 0x01, + 0x10, + 0xF9, + /*0280*/ 0x40, + 0x1F, + 0x82, + 0x70, + 0x00, + 0x01, + 0x10, + 0xF9, + 0x40, + 0x1F, + 0x82, + 0x74, + 0x00, + 0x01, + 0x10, + 0xF9, + /*0290*/ 0x40, + 0x1F, + 0x82, + 0x78, + 0x00, + 0x01, + 0x10, + 0xF9, + 0x40, + 0x1F, + 0x82, + 0x7C, + 0x00, + 0x01, + 0x10, + 0xF9, + /*02a0*/ 0x40, + 0x1F, + 0x82, + 0x80, + 0x00, + 0x01, + 0x10, + 0xF9, + 0x40, + 0x1F, + 0x82, + 0x84, + 0x00, + 0x01, + 0x10, + 0xF9, + /*02b0*/ 0x40, + 0x1F, + 0x82, + 0x88, + 0x00, + 0x01, + 0x10, + 0xF9, + 0x40, + 0x1F, + 0x82, + 0x8C, + 0x00, + 0x01, + 0x10, + 0xF9, + /*02c0*/ 0x40, + 0x1F, + 0x82, + 0x90, + 0x00, + 0x01, + 0x10, + 0xF9, + 0x40, + 0x1F, + 0x82, + 0x94, + 0x00, + 0x01, + 0x10, + 0xF9, + /*02d0*/ 0x40, + 0x1F, + 0x82, + 0x98, + 0x00, + 0x01, + 0x10, + 0xF9, + 0x40, + 0x1F, + 0x82, + 0x9C, + 0x00, + 0x01, + 0x10, + 0xF9, + /*02e0*/ 0x40, + 0x1F, + 0x82, + 0xA0, + 0x00, + 0x01, + 0x10, + 0xF9, + 0x40, + 0x1F, + 0x82, + 0xA4, + 0x00, + 0x01, + 0x10, + 0xF9, + /*02f0*/ 0x40, + 0x1F, + 0x82, + 0xA8, + 0x00, + 0x01, + 0x10, + 0xF9, + 0x40, + 0x2F, + 0x00, + 0x00, + 0x10, + 0x00, + 0x00, + 0x04, + /*0300*/ 0x40, + 0x2F, + 0x00, + 0x08, + 0x00, + 0x03, + 0x05, + 0x24, + 0x40, + 0x2F, + 0x00, + 0x0C, + 0x06, + 0x03, + 0x05, + 0x24, + /*0310*/ 0x40, + 0x2F, + 0x00, + 0x10, + 0x80, + 0x00, + 0x00, + 0x1B, + 0x40, + 0x2F, + 0x00, + 0x14, + 0x82, + 0x00, + 0x00, + 0x1B, + /*0320*/ 0x40, + 0x2F, + 0x00, + 0x18, + 0x84, + 0x00, + 0x00, + 0x1B, + 0x40, + 0x2F, + 0x00, + 0x1C, + 0x86, + 0x00, + 0x00, + 0x1B, + /*0330*/ 0x40, + 0x2F, + 0x00, + 0x20, + 0x90, + 0x00, + 0x00, + 0x21, + 0x40, + 0x2F, + 0x00, + 0x24, + 0xA0, + 0x00, + 0x00, + 0x19, + /*0340*/ 0x40, + 0x2F, + 0x00, + 0x28, + 0xA8, + 0x00, + 0x00, + 0x17, + 0x40, + 0x2F, + 0x00, + 0x2C, + 0xA9, + 0x00, + 0x00, + 0x1B, + /*0350*/ 0x40, + 0x2F, + 0x00, + 0x30, + 0x00, + 0x00, + 0x00, + 0x21, + 0x40, + 0x2F, + 0x00, + 0x04, + 0x00, + 0x00, + 0x79, + 0xA8, + /*0360*/ 0x40, + 0x2F, + 0x00, + 0x40, + 0x00, + 0x00, + 0x0F, + 0x31, + 0x40, + 0x2F, + 0x00, + 0x44, + 0x00, + 0x65, + 0x29, + 0x22, + /*0370*/ 0x40, + 0x2F, + 0x00, + 0x48, + 0x00, + 0x01, + 0x09, + 0x20, + 0x40, + 0x2F, + 0x00, + 0x4C, + 0x50, + 0x21, + 0x0A, + 0x08, + /*0380*/ 0x40, + 0x2F, + 0x00, + 0x80, + 0x00, + 0x00, + 0x00, + 0x21, + 0x40, + 0x2F, + 0x00, + 0x84, + 0x00, + 0x88, + 0x88, + 0x88, + /*0390*/ 0x40, + 0x2F, + 0x00, + 0x94, + 0x00, + 0x00, + 0x00, + 0x02, + 0x40, + 0x2F, + 0x00, + 0x98, + 0x00, + 0x00, + 0x00, + 0x00, + /*03a0*/ 0x40, + 0x2F, + 0x00, + 0x90, + 0x80, + 0x00, + 0x00, + 0x00, + 0x40, + 0x2F, + 0x00, + 0x9C, + 0xA5, + 0x5A, + 0x00, + 0x0F, + /*03b0*/ 0xCF, + 0x00, + 0x0C, + 0x1C, + 0x40, + 0x2F, + 0x00, + 0x3C, + 0x00, + 0x00, + 0x00, + 0x01, + 0xCC, + 0x00, + 0x14, + 0x04, + /*03c0*/ 0x40, + 0x2F, + 0x00, + 0x90, + 0x80, + 0x00, + 0x00, + 0x00, + 0x40, + 0x2F, + 0x00, + 0x9C, + 0xA5, + 0x5A, + 0x00, + 0x0C, + /*03d0*/ 0xCF, + 0x00, + 0x0C, + 0x1C, + 0x40, + 0x2F, + 0x00, + 0x3C, + 0x00, + 0x00, + 0x00, + 0x01, + 0xCC, + 0x00, + 0x14, + 0x04, + /*03e0*/ 0x40, + 0x2F, + 0x00, + 0x90, + 0x80, + 0x00, + 0x00, + 0x00, + 0x40, + 0x2F, + 0x00, + 0x9C, + 0xA5, + 0x5A, + 0x00, + 0x0C, + /*03f0*/ 0xCF, + 0x00, + 0x0C, + 0x1C, + 0x40, + 0x2F, + 0x00, + 0x3C, + 0x00, + 0x00, + 0x00, + 0x01, + 0xCC, + 0x00, + 0x1C, + 0x04, + /*0400*/ 0x40, + 0x2F, + 0x00, + 0xA0, + 0x00, + 0x00, + 0x00, + 0x33, + 0x40, + 0x2F, + 0x00, + 0x90, + 0x80, + 0x00, + 0x00, + 0x00, + /*0410*/ 0x40, + 0x2F, + 0x00, + 0x9C, + 0xA5, + 0x5A, + 0x00, + 0x0A, + 0xCF, + 0x00, + 0x0C, + 0x1C, + 0x40, + 0x2F, + 0x00, + 0x3C, + /*0420*/ 0x00, + 0x00, + 0x00, + 0x01, + 0xCC, + 0x00, + 0x0C, + 0x04, + 0x40, + 0x2F, + 0x00, + 0x4C, + 0x50, + 0x21, + 0x0A, + 0x09, +}; +#else +/************************************* + * DCD Data + *************************************/ +const uint8_t dcd_data[] = {0x00}; +#endif /* XIP_BOOT_HEADER_DCD_ENABLE */ +#endif /* XIP_BOOT_HEADER_ENABLE */ diff --git a/ext/hal/nxp/mcux/boards/evkbimxrt1050/evkbimxrt1050_sdram_ini_dcd.h b/ext/hal/nxp/mcux/boards/evkbimxrt1050/evkbimxrt1050_sdram_ini_dcd.h new file mode 100644 index 00000000000..fe7d17144b8 --- /dev/null +++ b/ext/hal/nxp/mcux/boards/evkbimxrt1050/evkbimxrt1050_sdram_ini_dcd.h @@ -0,0 +1,27 @@ +/* + * Copyright 2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __EVKBIMXRT1050_DCD_SDRAM_INIT__ +#define __EVKBIMXRT1050_DCD_SDRAM_INIT__ + +#include + +/*! @name Driver version */ +/*@{*/ +/*! @brief XIP_BOARD driver version 2.0.0. */ +#define FSL_XIP_BOARD_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) +/*@}*/ + +/************************************* + * DCD Data + *************************************/ +#define DCD_TAG_HEADER (0xD2) +#define DCD_TAG_HEADER_SHIFT (24) +#define DCD_VERSION (0x40) +#define DCD_ARRAY_SIZE 1 + +#endif /* __EVKBIMXRT1050_DCD_SDRAM_INIT__ */ diff --git a/ext/hal/nxp/mcux/boards/evkmimxrt1060/evkmimxrt1060_flexspi_nor_config.c b/ext/hal/nxp/mcux/boards/evkmimxrt1060/evkmimxrt1060_flexspi_nor_config.c new file mode 100644 index 00000000000..316fea1e4c8 --- /dev/null +++ b/ext/hal/nxp/mcux/boards/evkmimxrt1060/evkmimxrt1060_flexspi_nor_config.c @@ -0,0 +1,49 @@ +/* + * Copyright 2018 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "evkmimxrt1060_flexspi_nor_config.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.xip_board" +#endif + +/******************************************************************************* + * Code + ******************************************************************************/ +#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1) +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__) +__attribute__((section(".boot_hdr.conf"))) +#elif defined(__ICCARM__) +#pragma location = ".boot_hdr.conf" +#endif + +const flexspi_nor_config_t qspiflash_config = { + .memConfig = + { + .tag = FLEXSPI_CFG_BLK_TAG, + .version = FLEXSPI_CFG_BLK_VERSION, + .readSampleClkSrc = kFlexSPIReadSampleClk_LoopbackFromDqsPad, + .csHoldTime = 3u, + .csSetupTime = 3u, + // Enable DDR mode, Wordaddassable, Safe configuration, Differential clock + .sflashPadType = kSerialFlash_4Pads, + .serialClkFreq = kFlexSpiSerialClk_100MHz, + .sflashA1Size = 8u * 1024u * 1024u, + .lookupTable = + { + // Read LUTs + FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB, RADDR_SDR, FLEXSPI_4PAD, 0x18), + FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 0x06, READ_SDR, FLEXSPI_4PAD, 0x04), + }, + }, + .pageSize = 256u, + .sectorSize = 4u * 1024u, + .blockSize = 256u * 1024u, + .isUniformBlockSize = false, +}; +#endif /* XIP_BOOT_HEADER_ENABLE */ diff --git a/ext/hal/nxp/mcux/boards/evkmimxrt1060/evkmimxrt1060_flexspi_nor_config.h b/ext/hal/nxp/mcux/boards/evkmimxrt1060/evkmimxrt1060_flexspi_nor_config.h new file mode 100644 index 00000000000..452eb3dfb0c --- /dev/null +++ b/ext/hal/nxp/mcux/boards/evkmimxrt1060/evkmimxrt1060_flexspi_nor_config.h @@ -0,0 +1,268 @@ +/* + * Copyright 2018 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __EVKMIMXRT1060_FLEXSPI_NOR_CONFIG__ +#define __EVKMIMXRT1060_FLEXSPI_NOR_CONFIG__ + +#include +#include +#include "fsl_common.h" + +/*! @name Driver version */ +/*@{*/ +/*! @brief XIP_BOARD driver version 2.0.0. */ +#define FSL_XIP_BOARD_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) +/*@}*/ + +/* FLEXSPI memory config block related defintions */ +#define FLEXSPI_CFG_BLK_TAG (0x42464346UL) // ascii "FCFB" Big Endian +#define FLEXSPI_CFG_BLK_VERSION (0x56010400UL) // V1.4.0 +#define FLEXSPI_CFG_BLK_SIZE (512) + +/* FLEXSPI Feature related definitions */ +#define FLEXSPI_FEATURE_HAS_PARALLEL_MODE 1 + +/* Lookup table related defintions */ +#define CMD_INDEX_READ 0 +#define CMD_INDEX_READSTATUS 1 +#define CMD_INDEX_WRITEENABLE 2 +#define CMD_INDEX_WRITE 4 + +#define CMD_LUT_SEQ_IDX_READ 0 +#define CMD_LUT_SEQ_IDX_READSTATUS 1 +#define CMD_LUT_SEQ_IDX_WRITEENABLE 3 +#define CMD_LUT_SEQ_IDX_WRITE 9 + +#define CMD_SDR 0x01 +#define CMD_DDR 0x21 +#define RADDR_SDR 0x02 +#define RADDR_DDR 0x22 +#define CADDR_SDR 0x03 +#define CADDR_DDR 0x23 +#define MODE1_SDR 0x04 +#define MODE1_DDR 0x24 +#define MODE2_SDR 0x05 +#define MODE2_DDR 0x25 +#define MODE4_SDR 0x06 +#define MODE4_DDR 0x26 +#define MODE8_SDR 0x07 +#define MODE8_DDR 0x27 +#define WRITE_SDR 0x08 +#define WRITE_DDR 0x28 +#define READ_SDR 0x09 +#define READ_DDR 0x29 +#define LEARN_SDR 0x0A +#define LEARN_DDR 0x2A +#define DATSZ_SDR 0x0B +#define DATSZ_DDR 0x2B +#define DUMMY_SDR 0x0C +#define DUMMY_DDR 0x2C +#define DUMMY_RWDS_SDR 0x0D +#define DUMMY_RWDS_DDR 0x2D +#define JMP_ON_CS 0x1F +#define STOP 0 + +#define FLEXSPI_1PAD 0 +#define FLEXSPI_2PAD 1 +#define FLEXSPI_4PAD 2 +#define FLEXSPI_8PAD 3 + +#define FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) \ + (FLEXSPI_LUT_OPERAND0(op0) | FLEXSPI_LUT_NUM_PADS0(pad0) | FLEXSPI_LUT_OPCODE0(cmd0) | FLEXSPI_LUT_OPERAND1(op1) | \ + FLEXSPI_LUT_NUM_PADS1(pad1) | FLEXSPI_LUT_OPCODE1(cmd1)) + +//!@brief Definitions for FlexSPI Serial Clock Frequency +typedef enum _FlexSpiSerialClockFreq +{ + kFlexSpiSerialClk_30MHz = 1, + kFlexSpiSerialClk_50MHz = 2, + kFlexSpiSerialClk_60MHz = 3, + kFlexSpiSerialClk_75MHz = 4, + kFlexSpiSerialClk_80MHz = 5, + kFlexSpiSerialClk_100MHz = 6, + kFlexSpiSerialClk_120MHz = 7, + kFlexSpiSerialClk_133MHz = 8, + kFlexSpiSerialClk_166MHz = 9, +} flexspi_serial_clk_freq_t; + +//!@brief FlexSPI clock configuration type +enum +{ + kFlexSpiClk_SDR, //!< Clock configure for SDR mode + kFlexSpiClk_DDR, //!< Clock configurat for DDR mode +}; + +//!@brief FlexSPI Read Sample Clock Source definition +typedef enum _FlashReadSampleClkSource +{ + kFlexSPIReadSampleClk_LoopbackInternally = 0, + kFlexSPIReadSampleClk_LoopbackFromDqsPad = 1, + kFlexSPIReadSampleClk_LoopbackFromSckPad = 2, + kFlexSPIReadSampleClk_ExternalInputFromDqsPad = 3, +} flexspi_read_sample_clk_t; + +//!@brief Misc feature bit definitions +enum +{ + kFlexSpiMiscOffset_DiffClkEnable = 0, //!< Bit for Differential clock enable + kFlexSpiMiscOffset_Ck2Enable = 1, //!< Bit for CK2 enable + kFlexSpiMiscOffset_ParallelEnable = 2, //!< Bit for Parallel mode enable + kFlexSpiMiscOffset_WordAddressableEnable = 3, //!< Bit for Word Addressable enable + kFlexSpiMiscOffset_SafeConfigFreqEnable = 4, //!< Bit for Safe Configuration Frequency enable + kFlexSpiMiscOffset_PadSettingOverrideEnable = 5, //!< Bit for Pad setting override enable + kFlexSpiMiscOffset_DdrModeEnable = 6, //!< Bit for DDR clock confiuration indication. +}; + +//!@brief Flash Type Definition +enum +{ + kFlexSpiDeviceType_SerialNOR = 1, //!< Flash devices are Serial NOR + kFlexSpiDeviceType_SerialNAND = 2, //!< Flash devices are Serial NAND + kFlexSpiDeviceType_SerialRAM = 3, //!< Flash devices are Serial RAM/HyperFLASH + kFlexSpiDeviceType_MCP_NOR_NAND = 0x12, //!< Flash device is MCP device, A1 is Serial NOR, A2 is Serial NAND + kFlexSpiDeviceType_MCP_NOR_RAM = 0x13, //!< Flash deivce is MCP device, A1 is Serial NOR, A2 is Serial RAMs +}; + +//!@brief Flash Pad Definitions +enum +{ + kSerialFlash_1Pad = 1, + kSerialFlash_2Pads = 2, + kSerialFlash_4Pads = 4, + kSerialFlash_8Pads = 8, +}; + +//!@brief FlexSPI LUT Sequence structure +typedef struct _lut_sequence +{ + uint8_t seqNum; //!< Sequence Number, valid number: 1-16 + uint8_t seqId; //!< Sequence Index, valid number: 0-15 + uint16_t reserved; +} flexspi_lut_seq_t; + +//!@brief Flash Configuration Command Type +enum +{ + kDeviceConfigCmdType_Generic, //!< Generic command, for example: configure dummy cycles, drive strength, etc + kDeviceConfigCmdType_QuadEnable, //!< Quad Enable command + kDeviceConfigCmdType_Spi2Xpi, //!< Switch from SPI to DPI/QPI/OPI mode + kDeviceConfigCmdType_Xpi2Spi, //!< Switch from DPI/QPI/OPI to SPI mode + kDeviceConfigCmdType_Spi2NoCmd, //!< Switch to 0-4-4/0-8-8 mode + kDeviceConfigCmdType_Reset, //!< Reset device command +}; + +//!@brief FlexSPI Memory Configuration Block +typedef struct _FlexSPIConfig +{ + uint32_t tag; //!< [0x000-0x003] Tag, fixed value 0x42464346UL + uint32_t version; //!< [0x004-0x007] Version,[31:24] -'V', [23:16] - Major, [15:8] - Minor, [7:0] - bugfix + uint32_t reserved0; //!< [0x008-0x00b] Reserved for future use + uint8_t readSampleClkSrc; //!< [0x00c-0x00c] Read Sample Clock Source, valid value: 0/1/3 + uint8_t csHoldTime; //!< [0x00d-0x00d] CS hold time, default value: 3 + uint8_t csSetupTime; //!< [0x00e-0x00e] CS setup time, default value: 3 + uint8_t columnAddressWidth; //!< [0x00f-0x00f] Column Address with, for HyperBus protocol, it is fixed to 3, For + //! Serial NAND, need to refer to datasheet + uint8_t deviceModeCfgEnable; //!< [0x010-0x010] Device Mode Configure enable flag, 1 - Enable, 0 - Disable + uint8_t deviceModeType; //!< [0x011-0x011] Specify the configuration command type:Quad Enable, DPI/QPI/OPI switch, + //! Generic configuration, etc. + uint16_t waitTimeCfgCommands; //!< [0x012-0x013] Wait time for all configuration commands, unit: 100us, Used for + //! DPI/QPI/OPI switch or reset command + flexspi_lut_seq_t deviceModeSeq; //!< [0x014-0x017] Device mode sequence info, [7:0] - LUT sequence id, [15:8] - LUt + //! sequence number, [31:16] Reserved + uint32_t deviceModeArg; //!< [0x018-0x01b] Argument/Parameter for device configuration + uint8_t configCmdEnable; //!< [0x01c-0x01c] Configure command Enable Flag, 1 - Enable, 0 - Disable + uint8_t configModeType[3]; //!< [0x01d-0x01f] Configure Mode Type, similar as deviceModeTpe + flexspi_lut_seq_t + configCmdSeqs[3]; //!< [0x020-0x02b] Sequence info for Device Configuration command, similar as deviceModeSeq + uint32_t reserved1; //!< [0x02c-0x02f] Reserved for future use + uint32_t configCmdArgs[3]; //!< [0x030-0x03b] Arguments/Parameters for device Configuration commands + uint32_t reserved2; //!< [0x03c-0x03f] Reserved for future use + uint32_t controllerMiscOption; //!< [0x040-0x043] Controller Misc Options, see Misc feature bit definitions for more + //! details + uint8_t deviceType; //!< [0x044-0x044] Device Type: See Flash Type Definition for more details + uint8_t sflashPadType; //!< [0x045-0x045] Serial Flash Pad Type: 1 - Single, 2 - Dual, 4 - Quad, 8 - Octal + uint8_t serialClkFreq; //!< [0x046-0x046] Serial Flash Frequencey, device specific definitions, See System Boot + //! Chapter for more details + uint8_t lutCustomSeqEnable; //!< [0x047-0x047] LUT customization Enable, it is required if the program/erase cannot + //! be done using 1 LUT sequence, currently, only applicable to HyperFLASH + uint32_t reserved3[2]; //!< [0x048-0x04f] Reserved for future use + uint32_t sflashA1Size; //!< [0x050-0x053] Size of Flash connected to A1 + uint32_t sflashA2Size; //!< [0x054-0x057] Size of Flash connected to A2 + uint32_t sflashB1Size; //!< [0x058-0x05b] Size of Flash connected to B1 + uint32_t sflashB2Size; //!< [0x05c-0x05f] Size of Flash connected to B2 + uint32_t csPadSettingOverride; //!< [0x060-0x063] CS pad setting override value + uint32_t sclkPadSettingOverride; //!< [0x064-0x067] SCK pad setting override value + uint32_t dataPadSettingOverride; //!< [0x068-0x06b] data pad setting override value + uint32_t dqsPadSettingOverride; //!< [0x06c-0x06f] DQS pad setting override value + uint32_t timeoutInMs; //!< [0x070-0x073] Timeout threshold for read status command + uint32_t commandInterval; //!< [0x074-0x077] CS deselect interval between two commands + uint16_t dataValidTime[2]; //!< [0x078-0x07b] CLK edge to data valid time for PORT A and PORT B, in terms of 0.1ns + uint16_t busyOffset; //!< [0x07c-0x07d] Busy offset, valid value: 0-31 + uint16_t busyBitPolarity; //!< [0x07e-0x07f] Busy flag polarity, 0 - busy flag is 1 when flash device is busy, 1 - + //! busy flag is 0 when flash device is busy + uint32_t lookupTable[64]; //!< [0x080-0x17f] Lookup table holds Flash command sequences + flexspi_lut_seq_t lutCustomSeq[12]; //!< [0x180-0x1af] Customizable LUT Sequences + uint32_t reserved4[4]; //!< [0x1b0-0x1bf] Reserved for future use +} flexspi_mem_config_t; + +/* */ +#define NOR_CMD_INDEX_READ CMD_INDEX_READ //!< 0 +#define NOR_CMD_INDEX_READSTATUS CMD_INDEX_READSTATUS //!< 1 +#define NOR_CMD_INDEX_WRITEENABLE CMD_INDEX_WRITEENABLE //!< 2 +#define NOR_CMD_INDEX_ERASESECTOR 3 //!< 3 +#define NOR_CMD_INDEX_PAGEPROGRAM CMD_INDEX_WRITE //!< 4 +#define NOR_CMD_INDEX_CHIPERASE 5 //!< 5 +#define NOR_CMD_INDEX_DUMMY 6 //!< 6 +#define NOR_CMD_INDEX_ERASEBLOCK 7 //!< 7 + +#define NOR_CMD_LUT_SEQ_IDX_READ CMD_LUT_SEQ_IDX_READ //!< 0 READ LUT sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_READSTATUS \ + CMD_LUT_SEQ_IDX_READSTATUS //!< 1 Read Status LUT sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_READSTATUS_XPI \ + 2 //!< 2 Read status DPI/QPI/OPI sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE \ + CMD_LUT_SEQ_IDX_WRITEENABLE //!< 3 Write Enable sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE_XPI \ + 4 //!< 4 Write Enable DPI/QPI/OPI sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_ERASESECTOR 5 //!< 5 Erase Sector sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_ERASEBLOCK 8 //!< 8 Erase Block sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM \ + CMD_LUT_SEQ_IDX_WRITE //!< 9 Program sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_CHIPERASE 11 //!< 11 Chip Erase sequence in lookupTable id stored in config block +#define NOR_CMD_LUT_SEQ_IDX_READ_SFDP 13 //!< 13 Read SFDP sequence in lookupTable id stored in config block +#define NOR_CMD_LUT_SEQ_IDX_RESTORE_NOCMD \ + 14 //!< 14 Restore 0-4-4/0-8-8 mode sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_EXIT_NOCMD \ + 15 //!< 15 Exit 0-4-4/0-8-8 mode sequence id in lookupTable stored in config blobk + +/* + * Serial NOR configuration block + */ +typedef struct _flexspi_nor_config +{ + flexspi_mem_config_t memConfig; //!< Common memory configuration info via FlexSPI + uint32_t pageSize; //!< Page size of Serial NOR + uint32_t sectorSize; //!< Sector size of Serial NOR + uint8_t ipcmdSerialClkFreq; //!< Clock frequency for IP command + uint8_t isUniformBlockSize; //!< Sector/Block size is the same + uint8_t reserved0[2]; //!< Reserved for future use + uint8_t serialNorType; //!< Serial NOR Flash type: 0/1/2/3 + uint8_t needExitNoCmdMode; //!< Need to exit NoCmd mode before other IP command + uint8_t halfClkForNonReadCmd; //!< Half the Serial Clock for non-read command: true/false + uint8_t needRestoreNoCmdMode; //!< Need to Restore NoCmd mode after IP commmand execution + uint32_t blockSize; //!< Block size + uint32_t reserve2[11]; //!< Reserved for future use +} flexspi_nor_config_t; + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef __cplusplus +} +#endif +#endif /* __EVKMIMXRT1060_FLEXSPI_NOR_CONFIG__ */ diff --git a/ext/hal/nxp/mcux/boards/evkmimxrt1060/evkmimxrt1060_sdram_ini_dcd.c b/ext/hal/nxp/mcux/boards/evkmimxrt1060/evkmimxrt1060_sdram_ini_dcd.c new file mode 100644 index 00000000000..d8aae7d9ae0 --- /dev/null +++ b/ext/hal/nxp/mcux/boards/evkmimxrt1060/evkmimxrt1060_sdram_ini_dcd.c @@ -0,0 +1,1105 @@ +/* + * Copyright 2018 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "evkmimxrt1060_sdram_ini_dcd.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.xip_board" +#endif + +#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1) +#if defined(XIP_BOOT_HEADER_DCD_ENABLE) && (XIP_BOOT_HEADER_DCD_ENABLE == 1) +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__) +__attribute__((section(".boot_hdr.dcd_data"))) +#elif defined(__ICCARM__) +#pragma location = ".boot_hdr.dcd_data" +#endif +/************************************* + * DCD Data + *************************************/ +const uint8_t dcd_data[] = { + /*0000*/ DCD_TAG_HEADER, + 0x04, + 0x30, + 0x41, + 0xCC, + 0x03, + 0xAC, + 0x04, + 0x40, + 0x0F, + 0xC0, + 0x68, + 0xFF, + 0xFF, + 0xFF, + 0xFF, + /*0010*/ 0x40, + 0x0F, + 0xC0, + 0x6C, + 0xFF, + 0xFF, + 0xFF, + 0xFF, + 0x40, + 0x0F, + 0xC0, + 0x70, + 0xFF, + 0xFF, + 0xFF, + 0xFF, + /*0020*/ 0x40, + 0x0F, + 0xC0, + 0x74, + 0xFF, + 0xFF, + 0xFF, + 0xFF, + 0x40, + 0x0F, + 0xC0, + 0x78, + 0xFF, + 0xFF, + 0xFF, + 0xFF, + /*0030*/ 0x40, + 0x0F, + 0xC0, + 0x7C, + 0xFF, + 0xFF, + 0xFF, + 0xFF, + 0x40, + 0x0F, + 0xC0, + 0x80, + 0xFF, + 0xFF, + 0xFF, + 0xFF, + /*0040*/ 0x40, + 0x0D, + 0x80, + 0x30, + 0x00, + 0x00, + 0x20, + 0x01, + 0x40, + 0x0D, + 0x81, + 0x00, + 0x00, + 0x1D, + 0x00, + 0x00, + /*0050*/ 0x40, + 0x0F, + 0xC0, + 0x14, + 0x00, + 0x01, + 0x0D, + 0x40, + 0x40, + 0x1F, + 0x80, + 0x14, + 0x00, + 0x00, + 0x00, + 0x00, + /*0060*/ 0x40, + 0x1F, + 0x80, + 0x18, + 0x00, + 0x00, + 0x00, + 0x00, + 0x40, + 0x1F, + 0x80, + 0x1C, + 0x00, + 0x00, + 0x00, + 0x00, + /*0070*/ 0x40, + 0x1F, + 0x80, + 0x20, + 0x00, + 0x00, + 0x00, + 0x00, + 0x40, + 0x1F, + 0x80, + 0x24, + 0x00, + 0x00, + 0x00, + 0x00, + /*0080*/ 0x40, + 0x1F, + 0x80, + 0x28, + 0x00, + 0x00, + 0x00, + 0x00, + 0x40, + 0x1F, + 0x80, + 0x2C, + 0x00, + 0x00, + 0x00, + 0x00, + /*0090*/ 0x40, + 0x1F, + 0x80, + 0x30, + 0x00, + 0x00, + 0x00, + 0x00, + 0x40, + 0x1F, + 0x80, + 0x34, + 0x00, + 0x00, + 0x00, + 0x00, + /*00a0*/ 0x40, + 0x1F, + 0x80, + 0x38, + 0x00, + 0x00, + 0x00, + 0x00, + 0x40, + 0x1F, + 0x80, + 0x3C, + 0x00, + 0x00, + 0x00, + 0x00, + /*00b0*/ 0x40, + 0x1F, + 0x80, + 0x40, + 0x00, + 0x00, + 0x00, + 0x00, + 0x40, + 0x1F, + 0x80, + 0x44, + 0x00, + 0x00, + 0x00, + 0x00, + /*00c0*/ 0x40, + 0x1F, + 0x80, + 0x48, + 0x00, + 0x00, + 0x00, + 0x00, + 0x40, + 0x1F, + 0x80, + 0x4C, + 0x00, + 0x00, + 0x00, + 0x00, + /*00d0*/ 0x40, + 0x1F, + 0x80, + 0x50, + 0x00, + 0x00, + 0x00, + 0x00, + 0x40, + 0x1F, + 0x80, + 0x54, + 0x00, + 0x00, + 0x00, + 0x00, + /*00e0*/ 0x40, + 0x1F, + 0x80, + 0x58, + 0x00, + 0x00, + 0x00, + 0x00, + 0x40, + 0x1F, + 0x80, + 0x5C, + 0x00, + 0x00, + 0x00, + 0x00, + /*00f0*/ 0x40, + 0x1F, + 0x80, + 0x60, + 0x00, + 0x00, + 0x00, + 0x00, + 0x40, + 0x1F, + 0x80, + 0x64, + 0x00, + 0x00, + 0x00, + 0x00, + /*0100*/ 0x40, + 0x1F, + 0x80, + 0x68, + 0x00, + 0x00, + 0x00, + 0x00, + 0x40, + 0x1F, + 0x80, + 0x6C, + 0x00, + 0x00, + 0x00, + 0x00, + /*0110*/ 0x40, + 0x1F, + 0x80, + 0x70, + 0x00, + 0x00, + 0x00, + 0x00, + 0x40, + 0x1F, + 0x80, + 0x74, + 0x00, + 0x00, + 0x00, + 0x00, + /*0120*/ 0x40, + 0x1F, + 0x80, + 0x78, + 0x00, + 0x00, + 0x00, + 0x00, + 0x40, + 0x1F, + 0x80, + 0x7C, + 0x00, + 0x00, + 0x00, + 0x00, + /*0130*/ 0x40, + 0x1F, + 0x80, + 0x80, + 0x00, + 0x00, + 0x00, + 0x00, + 0x40, + 0x1F, + 0x80, + 0x84, + 0x00, + 0x00, + 0x00, + 0x00, + /*0140*/ 0x40, + 0x1F, + 0x80, + 0x88, + 0x00, + 0x00, + 0x00, + 0x00, + 0x40, + 0x1F, + 0x80, + 0x8C, + 0x00, + 0x00, + 0x00, + 0x00, + /*0150*/ 0x40, + 0x1F, + 0x80, + 0x90, + 0x00, + 0x00, + 0x00, + 0x00, + 0x40, + 0x1F, + 0x80, + 0x94, + 0x00, + 0x00, + 0x00, + 0x00, + /*0160*/ 0x40, + 0x1F, + 0x80, + 0x98, + 0x00, + 0x00, + 0x00, + 0x00, + 0x40, + 0x1F, + 0x80, + 0x9C, + 0x00, + 0x00, + 0x00, + 0x00, + /*0170*/ 0x40, + 0x1F, + 0x80, + 0xA0, + 0x00, + 0x00, + 0x00, + 0x00, + 0x40, + 0x1F, + 0x80, + 0xA4, + 0x00, + 0x00, + 0x00, + 0x00, + /*0180*/ 0x40, + 0x1F, + 0x80, + 0xA8, + 0x00, + 0x00, + 0x00, + 0x00, + 0x40, + 0x1F, + 0x80, + 0xAC, + 0x00, + 0x00, + 0x00, + 0x00, + /*0190*/ 0x40, + 0x1F, + 0x80, + 0xB0, + 0x00, + 0x00, + 0x00, + 0x10, + 0x40, + 0x1F, + 0x80, + 0xB4, + 0x00, + 0x00, + 0x00, + 0x00, + /*01a0*/ 0x40, + 0x1F, + 0x80, + 0xB8, + 0x00, + 0x00, + 0x00, + 0x00, + 0x40, + 0x1F, + 0x82, + 0x04, + 0x00, + 0x01, + 0x10, + 0xF9, + /*01b0*/ 0x40, + 0x1F, + 0x82, + 0x08, + 0x00, + 0x01, + 0x10, + 0xF9, + 0x40, + 0x1F, + 0x82, + 0x0C, + 0x00, + 0x01, + 0x10, + 0xF9, + /*01c0*/ 0x40, + 0x1F, + 0x82, + 0x10, + 0x00, + 0x01, + 0x10, + 0xF9, + 0x40, + 0x1F, + 0x82, + 0x14, + 0x00, + 0x01, + 0x10, + 0xF9, + /*01d0*/ 0x40, + 0x1F, + 0x82, + 0x18, + 0x00, + 0x01, + 0x10, + 0xF9, + 0x40, + 0x1F, + 0x82, + 0x1C, + 0x00, + 0x01, + 0x10, + 0xF9, + /*01e0*/ 0x40, + 0x1F, + 0x82, + 0x20, + 0x00, + 0x01, + 0x10, + 0xF9, + 0x40, + 0x1F, + 0x82, + 0x24, + 0x00, + 0x01, + 0x10, + 0xF9, + /*01f0*/ 0x40, + 0x1F, + 0x82, + 0x28, + 0x00, + 0x01, + 0x10, + 0xF9, + 0x40, + 0x1F, + 0x82, + 0x2C, + 0x00, + 0x01, + 0x10, + 0xF9, + /*0200*/ 0x40, + 0x1F, + 0x82, + 0x30, + 0x00, + 0x01, + 0x10, + 0xF9, + 0x40, + 0x1F, + 0x82, + 0x34, + 0x00, + 0x01, + 0x10, + 0xF9, + /*0210*/ 0x40, + 0x1F, + 0x82, + 0x38, + 0x00, + 0x01, + 0x10, + 0xF9, + 0x40, + 0x1F, + 0x82, + 0x3C, + 0x00, + 0x01, + 0x10, + 0xF9, + /*0220*/ 0x40, + 0x1F, + 0x82, + 0x40, + 0x00, + 0x01, + 0x10, + 0xF9, + 0x40, + 0x1F, + 0x82, + 0x44, + 0x00, + 0x01, + 0x10, + 0xF9, + /*0230*/ 0x40, + 0x1F, + 0x82, + 0x48, + 0x00, + 0x01, + 0x10, + 0xF9, + 0x40, + 0x1F, + 0x82, + 0x4C, + 0x00, + 0x01, + 0x10, + 0xF9, + /*0240*/ 0x40, + 0x1F, + 0x82, + 0x50, + 0x00, + 0x01, + 0x10, + 0xF9, + 0x40, + 0x1F, + 0x82, + 0x54, + 0x00, + 0x01, + 0x10, + 0xF9, + /*0250*/ 0x40, + 0x1F, + 0x82, + 0x58, + 0x00, + 0x01, + 0x10, + 0xF9, + 0x40, + 0x1F, + 0x82, + 0x5C, + 0x00, + 0x01, + 0x10, + 0xF9, + /*0260*/ 0x40, + 0x1F, + 0x82, + 0x60, + 0x00, + 0x01, + 0x10, + 0xF9, + 0x40, + 0x1F, + 0x82, + 0x64, + 0x00, + 0x01, + 0x10, + 0xF9, + /*0270*/ 0x40, + 0x1F, + 0x82, + 0x68, + 0x00, + 0x01, + 0x10, + 0xF9, + 0x40, + 0x1F, + 0x82, + 0x6C, + 0x00, + 0x01, + 0x10, + 0xF9, + /*0280*/ 0x40, + 0x1F, + 0x82, + 0x70, + 0x00, + 0x01, + 0x10, + 0xF9, + 0x40, + 0x1F, + 0x82, + 0x74, + 0x00, + 0x01, + 0x10, + 0xF9, + /*0290*/ 0x40, + 0x1F, + 0x82, + 0x78, + 0x00, + 0x01, + 0x10, + 0xF9, + 0x40, + 0x1F, + 0x82, + 0x7C, + 0x00, + 0x01, + 0x10, + 0xF9, + /*02a0*/ 0x40, + 0x1F, + 0x82, + 0x80, + 0x00, + 0x01, + 0x10, + 0xF9, + 0x40, + 0x1F, + 0x82, + 0x84, + 0x00, + 0x01, + 0x10, + 0xF9, + /*02b0*/ 0x40, + 0x1F, + 0x82, + 0x88, + 0x00, + 0x01, + 0x10, + 0xF9, + 0x40, + 0x1F, + 0x82, + 0x8C, + 0x00, + 0x01, + 0x10, + 0xF9, + /*02c0*/ 0x40, + 0x1F, + 0x82, + 0x90, + 0x00, + 0x01, + 0x10, + 0xF9, + 0x40, + 0x1F, + 0x82, + 0x94, + 0x00, + 0x01, + 0x10, + 0xF9, + /*02d0*/ 0x40, + 0x1F, + 0x82, + 0x98, + 0x00, + 0x01, + 0x10, + 0xF9, + 0x40, + 0x1F, + 0x82, + 0x9C, + 0x00, + 0x01, + 0x10, + 0xF9, + /*02e0*/ 0x40, + 0x1F, + 0x82, + 0xA0, + 0x00, + 0x01, + 0x10, + 0xF9, + 0x40, + 0x1F, + 0x82, + 0xA4, + 0x00, + 0x01, + 0x10, + 0xF9, + /*02f0*/ 0x40, + 0x1F, + 0x82, + 0xA8, + 0x00, + 0x01, + 0x10, + 0xF9, + 0x40, + 0x2F, + 0x00, + 0x00, + 0x10, + 0x00, + 0x00, + 0x04, + /*0300*/ 0x40, + 0x2F, + 0x00, + 0x08, + 0x00, + 0x03, + 0x05, + 0x24, + 0x40, + 0x2F, + 0x00, + 0x0C, + 0x06, + 0x03, + 0x05, + 0x24, + /*0310*/ 0x40, + 0x2F, + 0x00, + 0x10, + 0x80, + 0x00, + 0x00, + 0x1B, + 0x40, + 0x2F, + 0x00, + 0x14, + 0x82, + 0x00, + 0x00, + 0x1B, + /*0320*/ 0x40, + 0x2F, + 0x00, + 0x18, + 0x84, + 0x00, + 0x00, + 0x1B, + 0x40, + 0x2F, + 0x00, + 0x1C, + 0x86, + 0x00, + 0x00, + 0x1B, + /*0330*/ 0x40, + 0x2F, + 0x00, + 0x20, + 0x90, + 0x00, + 0x00, + 0x21, + 0x40, + 0x2F, + 0x00, + 0x24, + 0xA0, + 0x00, + 0x00, + 0x19, + /*0340*/ 0x40, + 0x2F, + 0x00, + 0x28, + 0xA8, + 0x00, + 0x00, + 0x17, + 0x40, + 0x2F, + 0x00, + 0x2C, + 0xA9, + 0x00, + 0x00, + 0x1B, + /*0350*/ 0x40, + 0x2F, + 0x00, + 0x30, + 0x00, + 0x00, + 0x00, + 0x21, + 0x40, + 0x2F, + 0x00, + 0x04, + 0x00, + 0x00, + 0x79, + 0xA8, + /*0360*/ 0x40, + 0x2F, + 0x00, + 0x40, + 0x00, + 0x00, + 0x0F, + 0x31, + 0x40, + 0x2F, + 0x00, + 0x44, + 0x00, + 0x65, + 0x29, + 0x22, + /*0370*/ 0x40, + 0x2F, + 0x00, + 0x48, + 0x00, + 0x01, + 0x09, + 0x20, + 0x40, + 0x2F, + 0x00, + 0x4C, + 0x50, + 0x21, + 0x0A, + 0x08, + /*0380*/ 0x40, + 0x2F, + 0x00, + 0x80, + 0x00, + 0x00, + 0x00, + 0x21, + 0x40, + 0x2F, + 0x00, + 0x84, + 0x00, + 0x88, + 0x88, + 0x88, + /*0390*/ 0x40, + 0x2F, + 0x00, + 0x94, + 0x00, + 0x00, + 0x00, + 0x02, + 0x40, + 0x2F, + 0x00, + 0x98, + 0x00, + 0x00, + 0x00, + 0x00, + /*03a0*/ 0x40, + 0x2F, + 0x00, + 0x90, + 0x80, + 0x00, + 0x00, + 0x00, + 0x40, + 0x2F, + 0x00, + 0x9C, + 0xA5, + 0x5A, + 0x00, + 0x0F, + /*03b0*/ 0xCF, + 0x00, + 0x0C, + 0x1C, + 0x40, + 0x2F, + 0x00, + 0x3C, + 0x00, + 0x00, + 0x00, + 0x01, + 0xCC, + 0x00, + 0x14, + 0x04, + /*03c0*/ 0x40, + 0x2F, + 0x00, + 0x90, + 0x80, + 0x00, + 0x00, + 0x00, + 0x40, + 0x2F, + 0x00, + 0x9C, + 0xA5, + 0x5A, + 0x00, + 0x0C, + /*03d0*/ 0xCF, + 0x00, + 0x0C, + 0x1C, + 0x40, + 0x2F, + 0x00, + 0x3C, + 0x00, + 0x00, + 0x00, + 0x01, + 0xCC, + 0x00, + 0x14, + 0x04, + /*03e0*/ 0x40, + 0x2F, + 0x00, + 0x90, + 0x80, + 0x00, + 0x00, + 0x00, + 0x40, + 0x2F, + 0x00, + 0x9C, + 0xA5, + 0x5A, + 0x00, + 0x0C, + /*03f0*/ 0xCF, + 0x00, + 0x0C, + 0x1C, + 0x40, + 0x2F, + 0x00, + 0x3C, + 0x00, + 0x00, + 0x00, + 0x01, + 0xCC, + 0x00, + 0x1C, + 0x04, + /*0400*/ 0x40, + 0x2F, + 0x00, + 0xA0, + 0x00, + 0x00, + 0x00, + 0x33, + 0x40, + 0x2F, + 0x00, + 0x90, + 0x80, + 0x00, + 0x00, + 0x00, + /*0410*/ 0x40, + 0x2F, + 0x00, + 0x9C, + 0xA5, + 0x5A, + 0x00, + 0x0A, + 0xCF, + 0x00, + 0x0C, + 0x1C, + 0x40, + 0x2F, + 0x00, + 0x3C, + /*0420*/ 0x00, + 0x00, + 0x00, + 0x01, + 0xCC, + 0x00, + 0x0C, + 0x04, + 0x40, + 0x2F, + 0x00, + 0x4C, + 0x50, + 0x21, + 0x0A, + 0x09, +}; +#else +/************************************* + * DCD Data + *************************************/ +const uint8_t dcd_data[] = {0x00}; +#endif /* XIP_BOOT_HEADER_DCD_ENABLE */ +#endif /* XIP_BOOT_HEADER_ENABLE */ diff --git a/ext/hal/nxp/mcux/boards/evkmimxrt1060/evkmimxrt1060_sdram_ini_dcd.h b/ext/hal/nxp/mcux/boards/evkmimxrt1060/evkmimxrt1060_sdram_ini_dcd.h new file mode 100644 index 00000000000..ecf41c11850 --- /dev/null +++ b/ext/hal/nxp/mcux/boards/evkmimxrt1060/evkmimxrt1060_sdram_ini_dcd.h @@ -0,0 +1,27 @@ +/* + * Copyright 2018 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __EVKMIMXRT1060_DCD_SDRAM_INIT__ +#define __EVKMIMXRT1060_DCD_SDRAM_INIT__ + +#include + +/*! @name Driver version */ +/*@{*/ +/*! @brief XIP_BOARD driver version 2.0.0. */ +#define FSL_XIP_BOARD_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) +/*@}*/ + +/************************************* + * DCD Data + *************************************/ +#define DCD_TAG_HEADER (0xD2) +#define DCD_TAG_HEADER_SHIFT (24) +#define DCD_VERSION (0x40) +#define DCD_ARRAY_SIZE 1 + +#endif /* __EVKMIMXRT1060_DCD_SDRAM_INIT__ */ diff --git a/ext/hal/nxp/mcux/devices/LPC54114/LPC54114_cm0plus.h b/ext/hal/nxp/mcux/devices/LPC54114/LPC54114_cm0plus.h index df59c71bf57..b717fdfc274 100644 --- a/ext/hal/nxp/mcux/devices/LPC54114/LPC54114_cm0plus.h +++ b/ext/hal/nxp/mcux/devices/LPC54114/LPC54114_cm0plus.h @@ -10,37 +10,15 @@ ** ** Reference manual: LPC5411x User manual Rev. 1.1 25 May 2016 ** Version: rev. 1.0, 2016-04-29 -** Build: b161227 +** Build: b180802 ** ** Abstract: ** CMSIS Peripheral Access Layer for LPC54114_cm0plus ** -** Copyright (c) 1997 - 2016 Freescale Semiconductor, Inc. -** Copyright 2016 - 2017 NXP -** Redistribution and use in source and binary forms, with or without modification, -** are permitted provided that the following conditions are met: +** Copyright 1997-2016 Freescale Semiconductor, Inc. +** Copyright 2016-2018 NXP ** -** o Redistributions of source code must retain the above copyright notice, this list -** of conditions and the following disclaimer. -** -** o Redistributions in binary form must reproduce the above copyright notice, this -** list of conditions and the following disclaimer in the documentation and/or -** other materials provided with the distribution. -** -** o Neither the name of the copyright holder nor the names of its -** contributors may be used to endorse or promote products derived from this -** software without specific prior written permission. -** -** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** SPDX-License-Identifier: BSD-3-Clause ** ** http: www.nxp.com ** mail: support@nxp.com @@ -167,6 +145,48 @@ typedef enum IRQn { */ /** Mapping Information */ +/*! + * @addtogroup dma_request + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! + * @brief Structure for the DMA hardware request + * + * Defines the structure for the DMA hardware request collections. The user can configure the + * hardware request to trigger the DMA transfer accordingly. The index + * of the hardware request varies according to the to SoC. + */ +typedef enum _dma_request_source +{ + kDmaRequestFlexcomm0Rx = 0U, /**< Flexcomm Interface 0 RX/I2C Slave */ + kDmaRequestFlexcomm0Tx = 1U, /**< Flexcomm Interface 0 TX/I2C Master */ + kDmaRequestFlexcomm1Rx = 2U, /**< Flexcomm Interface 1 RX/I2C Slave */ + kDmaRequestFlexcomm1Tx = 3U, /**< Flexcomm Interface 1 TX/I2C Master */ + kDmaRequestFlexcomm2Rx = 4U, /**< Flexcomm Interface 2 RX/I2C Slave */ + kDmaRequestFlexcomm2Tx = 5U, /**< Flexcomm Interface 2 TX/I2C Master */ + kDmaRequestFlexcomm3Rx = 6U, /**< Flexcomm Interface 3 RX/I2C Slave */ + kDmaRequestFlexcomm3Tx = 7U, /**< Flexcomm Interface 3 TX/I2C Master */ + kDmaRequestFlexcomm4Rx = 8U, /**< Flexcomm Interface 4 RX/I2C Slave */ + kDmaRequestFlexcomm4Tx = 9U, /**< Flexcomm Interface 4 TX/I2C Master */ + kDmaRequestFlexcomm5Rx = 10U, /**< Flexcomm Interface 5 RX/I2C Slave */ + kDmaRequestFlexcomm5Tx = 11U, /**< Flexcomm Interface 5 TX/I2C Master */ + kDmaRequestFlexcomm6Rx = 12U, /**< Flexcomm Interface 6 RX/I2C Slave */ + kDmaRequestFlexcomm6Tx = 13U, /**< Flexcomm Interface 6 TX/I2C Master */ + kDmaRequestFlexcomm7Rx = 14U, /**< Flexcomm Interface 7 RX/I2C Slave */ + kDmaRequestFlexcomm7Tx = 15U, /**< Flexcomm Interface 7 TX/I2C Master */ + kDmaRequestDMIC0 = 16U, /**< Digital microphone interface 0 */ + kDmaRequestDMIC1 = 17U, /**< Digital microphone interface 1 */ + kDmaRequestNoDMARequest18 = 18U, /**< No DMA request 18 */ + kDmaRequestNoDMARequest19 = 19U, /**< No DMA request 19 */ +} dma_request_source_t; + +/* @} */ + /*! * @} @@ -188,8 +208,12 @@ typedef enum IRQn { */ #if defined(__ARMCC_VERSION) - #pragma push - #pragma anon_unions + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #else + #pragma push + #pragma anon_unions + #endif #elif defined(__GNUC__) /* anonymous unions are enabled by default */ #elif defined(__IAR_SYSTEMS_ICC__) @@ -236,6 +260,7 @@ typedef struct { */ /*! @name CTRL - ADC Control register. Contains the clock divide value, resolution selection, sampling time selection, and mode controls. */ +/*! @{ */ #define ADC_CTRL_CLKDIV_MASK (0xFFU) #define ADC_CTRL_CLKDIV_SHIFT (0U) #define ADC_CTRL_CLKDIV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_CLKDIV_SHIFT)) & ADC_CTRL_CLKDIV_MASK) @@ -251,13 +276,17 @@ typedef struct { #define ADC_CTRL_TSAMP_MASK (0x7000U) #define ADC_CTRL_TSAMP_SHIFT (12U) #define ADC_CTRL_TSAMP(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_TSAMP_SHIFT)) & ADC_CTRL_TSAMP_MASK) +/*! @} */ /*! @name INSEL - Input Select. Allows selection of the temperature sensor as an alternate input to ADC channel 0. */ +/*! @{ */ #define ADC_INSEL_SEL_MASK (0x3U) #define ADC_INSEL_SEL_SHIFT (0U) #define ADC_INSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_INSEL_SEL_SHIFT)) & ADC_INSEL_SEL_MASK) +/*! @} */ /*! @name SEQ_CTRL - ADC Conversion Sequence-n control register: Controls triggering and channel selection for conversion sequence-n. Also specifies interrupt mode for sequence-n. */ +/*! @{ */ #define ADC_SEQ_CTRL_CHANNELS_MASK (0xFFFU) #define ADC_SEQ_CTRL_CHANNELS_SHIFT (0U) #define ADC_SEQ_CTRL_CHANNELS(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_CHANNELS_SHIFT)) & ADC_SEQ_CTRL_CHANNELS_MASK) @@ -288,11 +317,13 @@ typedef struct { #define ADC_SEQ_CTRL_SEQ_ENA_MASK (0x80000000U) #define ADC_SEQ_CTRL_SEQ_ENA_SHIFT (31U) #define ADC_SEQ_CTRL_SEQ_ENA(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_SEQ_ENA_SHIFT)) & ADC_SEQ_CTRL_SEQ_ENA_MASK) +/*! @} */ /* The count of ADC_SEQ_CTRL */ #define ADC_SEQ_CTRL_COUNT (2U) /*! @name SEQ_GDAT - ADC Sequence-n Global Data register. This register contains the result of the most recent ADC conversion performed under sequence-n. */ +/*! @{ */ #define ADC_SEQ_GDAT_RESULT_MASK (0xFFF0U) #define ADC_SEQ_GDAT_RESULT_SHIFT (4U) #define ADC_SEQ_GDAT_RESULT(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_RESULT_SHIFT)) & ADC_SEQ_GDAT_RESULT_MASK) @@ -311,11 +342,13 @@ typedef struct { #define ADC_SEQ_GDAT_DATAVALID_MASK (0x80000000U) #define ADC_SEQ_GDAT_DATAVALID_SHIFT (31U) #define ADC_SEQ_GDAT_DATAVALID(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_DATAVALID_SHIFT)) & ADC_SEQ_GDAT_DATAVALID_MASK) +/*! @} */ /* The count of ADC_SEQ_GDAT */ #define ADC_SEQ_GDAT_COUNT (2U) /*! @name DAT - ADC Channel 0 Data register. This register contains the result of the most recent conversion completed on channel 0. */ +/*! @{ */ #define ADC_DAT_RESULT_MASK (0xFFF0U) #define ADC_DAT_RESULT_SHIFT (4U) #define ADC_DAT_RESULT(x) (((uint32_t)(((uint32_t)(x)) << ADC_DAT_RESULT_SHIFT)) & ADC_DAT_RESULT_MASK) @@ -334,31 +367,41 @@ typedef struct { #define ADC_DAT_DATAVALID_MASK (0x80000000U) #define ADC_DAT_DATAVALID_SHIFT (31U) #define ADC_DAT_DATAVALID(x) (((uint32_t)(((uint32_t)(x)) << ADC_DAT_DATAVALID_SHIFT)) & ADC_DAT_DATAVALID_MASK) +/*! @} */ /* The count of ADC_DAT */ #define ADC_DAT_COUNT (12U) /*! @name THR0_LOW - ADC Low Compare Threshold register 0: Contains the lower threshold level for automatic threshold comparison for any channels linked to threshold pair 0. */ +/*! @{ */ #define ADC_THR0_LOW_THRLOW_MASK (0xFFF0U) #define ADC_THR0_LOW_THRLOW_SHIFT (4U) #define ADC_THR0_LOW_THRLOW(x) (((uint32_t)(((uint32_t)(x)) << ADC_THR0_LOW_THRLOW_SHIFT)) & ADC_THR0_LOW_THRLOW_MASK) +/*! @} */ /*! @name THR1_LOW - ADC Low Compare Threshold register 1: Contains the lower threshold level for automatic threshold comparison for any channels linked to threshold pair 1. */ +/*! @{ */ #define ADC_THR1_LOW_THRLOW_MASK (0xFFF0U) #define ADC_THR1_LOW_THRLOW_SHIFT (4U) #define ADC_THR1_LOW_THRLOW(x) (((uint32_t)(((uint32_t)(x)) << ADC_THR1_LOW_THRLOW_SHIFT)) & ADC_THR1_LOW_THRLOW_MASK) +/*! @} */ /*! @name THR0_HIGH - ADC High Compare Threshold register 0: Contains the upper threshold level for automatic threshold comparison for any channels linked to threshold pair 0. */ +/*! @{ */ #define ADC_THR0_HIGH_THRHIGH_MASK (0xFFF0U) #define ADC_THR0_HIGH_THRHIGH_SHIFT (4U) #define ADC_THR0_HIGH_THRHIGH(x) (((uint32_t)(((uint32_t)(x)) << ADC_THR0_HIGH_THRHIGH_SHIFT)) & ADC_THR0_HIGH_THRHIGH_MASK) +/*! @} */ /*! @name THR1_HIGH - ADC High Compare Threshold register 1: Contains the upper threshold level for automatic threshold comparison for any channels linked to threshold pair 1. */ +/*! @{ */ #define ADC_THR1_HIGH_THRHIGH_MASK (0xFFF0U) #define ADC_THR1_HIGH_THRHIGH_SHIFT (4U) #define ADC_THR1_HIGH_THRHIGH(x) (((uint32_t)(((uint32_t)(x)) << ADC_THR1_HIGH_THRHIGH_SHIFT)) & ADC_THR1_HIGH_THRHIGH_MASK) +/*! @} */ /*! @name CHAN_THRSEL - ADC Channel-Threshold Select register. Specifies which set of threshold compare registers are to be used for each channel */ +/*! @{ */ #define ADC_CHAN_THRSEL_CH0_THRSEL_MASK (0x1U) #define ADC_CHAN_THRSEL_CH0_THRSEL_SHIFT (0U) #define ADC_CHAN_THRSEL_CH0_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH0_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH0_THRSEL_MASK) @@ -395,8 +438,10 @@ typedef struct { #define ADC_CHAN_THRSEL_CH11_THRSEL_MASK (0x800U) #define ADC_CHAN_THRSEL_CH11_THRSEL_SHIFT (11U) #define ADC_CHAN_THRSEL_CH11_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH11_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH11_THRSEL_MASK) +/*! @} */ /*! @name INTEN - ADC Interrupt Enable register. This register contains enable bits that enable the sequence-A, sequence-B, threshold compare and data overrun interrupts to be generated. */ +/*! @{ */ #define ADC_INTEN_SEQA_INTEN_MASK (0x1U) #define ADC_INTEN_SEQA_INTEN_SHIFT (0U) #define ADC_INTEN_SEQA_INTEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_SEQA_INTEN_SHIFT)) & ADC_INTEN_SEQA_INTEN_MASK) @@ -442,8 +487,10 @@ typedef struct { #define ADC_INTEN_ADCMPINTEN11_MASK (0x6000000U) #define ADC_INTEN_ADCMPINTEN11_SHIFT (25U) #define ADC_INTEN_ADCMPINTEN11(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN11_SHIFT)) & ADC_INTEN_ADCMPINTEN11_MASK) +/*! @} */ /*! @name FLAGS - ADC Flags register. Contains the four interrupt/DMA trigger flags and the individual component overrun and threshold-compare flags. (The overrun bits replicate information stored in the result registers). */ +/*! @{ */ #define ADC_FLAGS_THCMP0_MASK (0x1U) #define ADC_FLAGS_THCMP0_SHIFT (0U) #define ADC_FLAGS_THCMP0(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP0_SHIFT)) & ADC_FLAGS_THCMP0_MASK) @@ -534,16 +581,20 @@ typedef struct { #define ADC_FLAGS_OVR_INT_MASK (0x80000000U) #define ADC_FLAGS_OVR_INT_SHIFT (31U) #define ADC_FLAGS_OVR_INT(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVR_INT_SHIFT)) & ADC_FLAGS_OVR_INT_MASK) +/*! @} */ /*! @name STARTUP - ADC Startup register. */ +/*! @{ */ #define ADC_STARTUP_ADC_ENA_MASK (0x1U) #define ADC_STARTUP_ADC_ENA_SHIFT (0U) #define ADC_STARTUP_ADC_ENA(x) (((uint32_t)(((uint32_t)(x)) << ADC_STARTUP_ADC_ENA_SHIFT)) & ADC_STARTUP_ADC_ENA_MASK) #define ADC_STARTUP_ADC_INIT_MASK (0x2U) #define ADC_STARTUP_ADC_INIT_SHIFT (1U) #define ADC_STARTUP_ADC_INIT(x) (((uint32_t)(((uint32_t)(x)) << ADC_STARTUP_ADC_INIT_SHIFT)) & ADC_STARTUP_ADC_INIT_MASK) +/*! @} */ /*! @name CALIB - ADC Calibration register. */ +/*! @{ */ #define ADC_CALIB_CALIB_MASK (0x1U) #define ADC_CALIB_CALIB_SHIFT (0U) #define ADC_CALIB_CALIB(x) (((uint32_t)(((uint32_t)(x)) << ADC_CALIB_CALIB_SHIFT)) & ADC_CALIB_CALIB_MASK) @@ -553,6 +604,7 @@ typedef struct { #define ADC_CALIB_CALVALUE_MASK (0x1FCU) #define ADC_CALIB_CALVALUE_SHIFT (2U) #define ADC_CALIB_CALVALUE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CALIB_CALVALUE_SHIFT)) & ADC_CALIB_CALVALUE_MASK) +/*! @} */ /*! @@ -610,45 +662,59 @@ typedef struct { */ /*! @name ASYNCPRESETCTRL - Async peripheral reset control */ +/*! @{ */ #define ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER3_MASK (0x2000U) #define ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER3_SHIFT (13U) #define ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER3(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER3_SHIFT)) & ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER3_MASK) #define ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER4_MASK (0x4000U) #define ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER4_SHIFT (14U) #define ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER4(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER4_SHIFT)) & ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER4_MASK) +/*! @} */ /*! @name ASYNCPRESETCTRLSET - Set bits in ASYNCPRESETCTRL */ +/*! @{ */ #define ASYNC_SYSCON_ASYNCPRESETCTRLSET_ARST_SET_MASK (0xFFFFFFFFU) #define ASYNC_SYSCON_ASYNCPRESETCTRLSET_ARST_SET_SHIFT (0U) #define ASYNC_SYSCON_ASYNCPRESETCTRLSET_ARST_SET(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCPRESETCTRLSET_ARST_SET_SHIFT)) & ASYNC_SYSCON_ASYNCPRESETCTRLSET_ARST_SET_MASK) +/*! @} */ /*! @name ASYNCPRESETCTRLCLR - Clear bits in ASYNCPRESETCTRL */ +/*! @{ */ #define ASYNC_SYSCON_ASYNCPRESETCTRLCLR_ARST_CLR_MASK (0xFFFFFFFFU) #define ASYNC_SYSCON_ASYNCPRESETCTRLCLR_ARST_CLR_SHIFT (0U) #define ASYNC_SYSCON_ASYNCPRESETCTRLCLR_ARST_CLR(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCPRESETCTRLCLR_ARST_CLR_SHIFT)) & ASYNC_SYSCON_ASYNCPRESETCTRLCLR_ARST_CLR_MASK) +/*! @} */ /*! @name ASYNCAPBCLKCTRL - Async peripheral clock control */ +/*! @{ */ #define ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER3_MASK (0x2000U) #define ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER3_SHIFT (13U) #define ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER3(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER3_SHIFT)) & ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER3_MASK) #define ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER4_MASK (0x4000U) #define ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER4_SHIFT (14U) #define ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER4(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER4_SHIFT)) & ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER4_MASK) +/*! @} */ /*! @name ASYNCAPBCLKCTRLSET - Set bits in ASYNCAPBCLKCTRL */ +/*! @{ */ #define ASYNC_SYSCON_ASYNCAPBCLKCTRLSET_ACLK_SET_MASK (0xFFFFFFFFU) #define ASYNC_SYSCON_ASYNCAPBCLKCTRLSET_ACLK_SET_SHIFT (0U) #define ASYNC_SYSCON_ASYNCAPBCLKCTRLSET_ACLK_SET(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCAPBCLKCTRLSET_ACLK_SET_SHIFT)) & ASYNC_SYSCON_ASYNCAPBCLKCTRLSET_ACLK_SET_MASK) +/*! @} */ /*! @name ASYNCAPBCLKCTRLCLR - Clear bits in ASYNCAPBCLKCTRL */ +/*! @{ */ #define ASYNC_SYSCON_ASYNCAPBCLKCTRLCLR_ACLK_CLR_MASK (0xFFFFFFFFU) #define ASYNC_SYSCON_ASYNCAPBCLKCTRLCLR_ACLK_CLR_SHIFT (0U) #define ASYNC_SYSCON_ASYNCAPBCLKCTRLCLR_ACLK_CLR(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCAPBCLKCTRLCLR_ACLK_CLR_SHIFT)) & ASYNC_SYSCON_ASYNCAPBCLKCTRLCLR_ACLK_CLR_MASK) +/*! @} */ /*! @name ASYNCAPBCLKSELA - Async APB clock source select A */ +/*! @{ */ #define ASYNC_SYSCON_ASYNCAPBCLKSELA_SEL_MASK (0x3U) #define ASYNC_SYSCON_ASYNCAPBCLKSELA_SEL_SHIFT (0U) #define ASYNC_SYSCON_ASYNCAPBCLKSELA_SEL(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCAPBCLKSELA_SEL_SHIFT)) & ASYNC_SYSCON_ASYNCAPBCLKSELA_SEL_MASK) +/*! @} */ /*! @@ -700,6 +766,7 @@ typedef struct { */ /*! @name MODE - CRC mode register */ +/*! @{ */ #define CRC_MODE_CRC_POLY_MASK (0x3U) #define CRC_MODE_CRC_POLY_SHIFT (0U) #define CRC_MODE_CRC_POLY(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_CRC_POLY_SHIFT)) & CRC_MODE_CRC_POLY_MASK) @@ -715,21 +782,28 @@ typedef struct { #define CRC_MODE_CMPL_SUM_MASK (0x20U) #define CRC_MODE_CMPL_SUM_SHIFT (5U) #define CRC_MODE_CMPL_SUM(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_CMPL_SUM_SHIFT)) & CRC_MODE_CMPL_SUM_MASK) +/*! @} */ /*! @name SEED - CRC seed register */ +/*! @{ */ #define CRC_SEED_CRC_SEED_MASK (0xFFFFFFFFU) #define CRC_SEED_CRC_SEED_SHIFT (0U) #define CRC_SEED_CRC_SEED(x) (((uint32_t)(((uint32_t)(x)) << CRC_SEED_CRC_SEED_SHIFT)) & CRC_SEED_CRC_SEED_MASK) +/*! @} */ /*! @name SUM - CRC checksum register */ +/*! @{ */ #define CRC_SUM_CRC_SUM_MASK (0xFFFFFFFFU) #define CRC_SUM_CRC_SUM_SHIFT (0U) #define CRC_SUM_CRC_SUM(x) (((uint32_t)(((uint32_t)(x)) << CRC_SUM_CRC_SUM_SHIFT)) & CRC_SUM_CRC_SUM_MASK) +/*! @} */ /*! @name WR_DATA - CRC data register */ +/*! @{ */ #define CRC_WR_DATA_CRC_WR_DATA_MASK (0xFFFFFFFFU) #define CRC_WR_DATA_CRC_WR_DATA_SHIFT (0U) #define CRC_WR_DATA_CRC_WR_DATA(x) (((uint32_t)(((uint32_t)(x)) << CRC_WR_DATA_CRC_WR_DATA_SHIFT)) & CRC_WR_DATA_CRC_WR_DATA_MASK) +/*! @} */ /*! @@ -788,6 +862,7 @@ typedef struct { */ /*! @name IR - Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. */ +/*! @{ */ #define CTIMER_IR_MR0INT_MASK (0x1U) #define CTIMER_IR_MR0INT_SHIFT (0U) #define CTIMER_IR_MR0INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR0INT_SHIFT)) & CTIMER_IR_MR0INT_MASK) @@ -812,31 +887,41 @@ typedef struct { #define CTIMER_IR_CR3INT_MASK (0x80U) #define CTIMER_IR_CR3INT_SHIFT (7U) #define CTIMER_IR_CR3INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR3INT_SHIFT)) & CTIMER_IR_CR3INT_MASK) +/*! @} */ /*! @name TCR - Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. */ +/*! @{ */ #define CTIMER_TCR_CEN_MASK (0x1U) #define CTIMER_TCR_CEN_SHIFT (0U) #define CTIMER_TCR_CEN(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_TCR_CEN_SHIFT)) & CTIMER_TCR_CEN_MASK) #define CTIMER_TCR_CRST_MASK (0x2U) #define CTIMER_TCR_CRST_SHIFT (1U) #define CTIMER_TCR_CRST(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_TCR_CRST_SHIFT)) & CTIMER_TCR_CRST_MASK) +/*! @} */ /*! @name TC - Timer Counter. The 32 bit TC is incremented every PR+1 cycles of the APB bus clock. The TC is controlled through the TCR. */ +/*! @{ */ #define CTIMER_TC_TCVAL_MASK (0xFFFFFFFFU) #define CTIMER_TC_TCVAL_SHIFT (0U) #define CTIMER_TC_TCVAL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_TC_TCVAL_SHIFT)) & CTIMER_TC_TCVAL_MASK) +/*! @} */ /*! @name PR - Prescale Register. When the Prescale Counter (PC) is equal to this value, the next clock increments the TC and clears the PC. */ +/*! @{ */ #define CTIMER_PR_PRVAL_MASK (0xFFFFFFFFU) #define CTIMER_PR_PRVAL_SHIFT (0U) #define CTIMER_PR_PRVAL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PR_PRVAL_SHIFT)) & CTIMER_PR_PRVAL_MASK) +/*! @} */ /*! @name PC - Prescale Counter. The 32 bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface. */ +/*! @{ */ #define CTIMER_PC_PCVAL_MASK (0xFFFFFFFFU) #define CTIMER_PC_PCVAL_SHIFT (0U) #define CTIMER_PC_PCVAL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PC_PCVAL_SHIFT)) & CTIMER_PC_PCVAL_MASK) +/*! @} */ /*! @name MCR - Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs. */ +/*! @{ */ #define CTIMER_MCR_MR0I_MASK (0x1U) #define CTIMER_MCR_MR0I_SHIFT (0U) #define CTIMER_MCR_MR0I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0I_SHIFT)) & CTIMER_MCR_MR0I_MASK) @@ -873,16 +958,20 @@ typedef struct { #define CTIMER_MCR_MR3S_MASK (0x800U) #define CTIMER_MCR_MR3S_SHIFT (11U) #define CTIMER_MCR_MR3S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3S_SHIFT)) & CTIMER_MCR_MR3S_MASK) +/*! @} */ /*! @name MR - Match Register . MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. */ +/*! @{ */ #define CTIMER_MR_MATCH_MASK (0xFFFFFFFFU) #define CTIMER_MR_MATCH_SHIFT (0U) #define CTIMER_MR_MATCH(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MR_MATCH_SHIFT)) & CTIMER_MR_MATCH_MASK) +/*! @} */ /* The count of CTIMER_MR */ #define CTIMER_MR_COUNT (4U) /*! @name CCR - Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. */ +/*! @{ */ #define CTIMER_CCR_CAP0RE_MASK (0x1U) #define CTIMER_CCR_CAP0RE_SHIFT (0U) #define CTIMER_CCR_CAP0RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0RE_SHIFT)) & CTIMER_CCR_CAP0RE_MASK) @@ -919,16 +1008,20 @@ typedef struct { #define CTIMER_CCR_CAP3I_MASK (0x800U) #define CTIMER_CCR_CAP3I_SHIFT (11U) #define CTIMER_CCR_CAP3I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3I_SHIFT)) & CTIMER_CCR_CAP3I_MASK) +/*! @} */ /*! @name CR - Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input. */ +/*! @{ */ #define CTIMER_CR_CAP_MASK (0xFFFFFFFFU) #define CTIMER_CR_CAP_SHIFT (0U) #define CTIMER_CR_CAP(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CR_CAP_SHIFT)) & CTIMER_CR_CAP_MASK) +/*! @} */ /* The count of CTIMER_CR */ #define CTIMER_CR_COUNT (4U) /*! @name EMR - External Match Register. The EMR controls the match function and the external match pins. */ +/*! @{ */ #define CTIMER_EMR_EM0_MASK (0x1U) #define CTIMER_EMR_EM0_SHIFT (0U) #define CTIMER_EMR_EM0(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM0_SHIFT)) & CTIMER_EMR_EM0_MASK) @@ -953,8 +1046,10 @@ typedef struct { #define CTIMER_EMR_EMC3_MASK (0xC00U) #define CTIMER_EMR_EMC3_SHIFT (10U) #define CTIMER_EMR_EMC3(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC3_SHIFT)) & CTIMER_EMR_EMC3_MASK) +/*! @} */ /*! @name CTCR - Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. */ +/*! @{ */ #define CTIMER_CTCR_CTMODE_MASK (0x3U) #define CTIMER_CTCR_CTMODE_SHIFT (0U) #define CTIMER_CTCR_CTMODE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_CTMODE_SHIFT)) & CTIMER_CTCR_CTMODE_MASK) @@ -967,8 +1062,10 @@ typedef struct { #define CTIMER_CTCR_SELCC_MASK (0xE0U) #define CTIMER_CTCR_SELCC_SHIFT (5U) #define CTIMER_CTCR_SELCC(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_SELCC_SHIFT)) & CTIMER_CTCR_SELCC_MASK) +/*! @} */ /*! @name PWMC - PWM Control Register. The PWMCON enables PWM mode for the external match pins. */ +/*! @{ */ #define CTIMER_PWMC_PWMEN0_MASK (0x1U) #define CTIMER_PWMC_PWMEN0_SHIFT (0U) #define CTIMER_PWMC_PWMEN0(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN0_SHIFT)) & CTIMER_PWMC_PWMEN0_MASK) @@ -981,6 +1078,7 @@ typedef struct { #define CTIMER_PWMC_PWMEN3_MASK (0x8U) #define CTIMER_PWMC_PWMEN3_SHIFT (3U) #define CTIMER_PWMC_PWMEN3(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN3_SHIFT)) & CTIMER_PWMC_PWMEN3_MASK) +/*! @} */ /*! @@ -1080,120 +1178,151 @@ typedef struct { */ /*! @name CTRL - DMA control. */ +/*! @{ */ #define DMA_CTRL_ENABLE_MASK (0x1U) #define DMA_CTRL_ENABLE_SHIFT (0U) #define DMA_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CTRL_ENABLE_SHIFT)) & DMA_CTRL_ENABLE_MASK) +/*! @} */ /*! @name INTSTAT - Interrupt status. */ +/*! @{ */ #define DMA_INTSTAT_ACTIVEINT_MASK (0x2U) #define DMA_INTSTAT_ACTIVEINT_SHIFT (1U) #define DMA_INTSTAT_ACTIVEINT(x) (((uint32_t)(((uint32_t)(x)) << DMA_INTSTAT_ACTIVEINT_SHIFT)) & DMA_INTSTAT_ACTIVEINT_MASK) #define DMA_INTSTAT_ACTIVEERRINT_MASK (0x4U) #define DMA_INTSTAT_ACTIVEERRINT_SHIFT (2U) #define DMA_INTSTAT_ACTIVEERRINT(x) (((uint32_t)(((uint32_t)(x)) << DMA_INTSTAT_ACTIVEERRINT_SHIFT)) & DMA_INTSTAT_ACTIVEERRINT_MASK) +/*! @} */ /*! @name SRAMBASE - SRAM address of the channel configuration table. */ +/*! @{ */ #define DMA_SRAMBASE_OFFSET_MASK (0xFFFFFE00U) #define DMA_SRAMBASE_OFFSET_SHIFT (9U) #define DMA_SRAMBASE_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << DMA_SRAMBASE_OFFSET_SHIFT)) & DMA_SRAMBASE_OFFSET_MASK) +/*! @} */ /*! @name COMMON_ENABLESET - Channel Enable read and Set for all DMA channels. */ +/*! @{ */ #define DMA_COMMON_ENABLESET_ENA_MASK (0xFFFFFFFFU) #define DMA_COMMON_ENABLESET_ENA_SHIFT (0U) #define DMA_COMMON_ENABLESET_ENA(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENA_SHIFT)) & DMA_COMMON_ENABLESET_ENA_MASK) +/*! @} */ /* The count of DMA_COMMON_ENABLESET */ #define DMA_COMMON_ENABLESET_COUNT (1U) /*! @name COMMON_ENABLECLR - Channel Enable Clear for all DMA channels. */ +/*! @{ */ #define DMA_COMMON_ENABLECLR_CLR_MASK (0xFFFFFFFFU) #define DMA_COMMON_ENABLECLR_CLR_SHIFT (0U) #define DMA_COMMON_ENABLECLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR_SHIFT)) & DMA_COMMON_ENABLECLR_CLR_MASK) +/*! @} */ /* The count of DMA_COMMON_ENABLECLR */ #define DMA_COMMON_ENABLECLR_COUNT (1U) /*! @name COMMON_ACTIVE - Channel Active status for all DMA channels. */ +/*! @{ */ #define DMA_COMMON_ACTIVE_ACT_MASK (0xFFFFFFFFU) #define DMA_COMMON_ACTIVE_ACT_SHIFT (0U) #define DMA_COMMON_ACTIVE_ACT(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACT_SHIFT)) & DMA_COMMON_ACTIVE_ACT_MASK) +/*! @} */ /* The count of DMA_COMMON_ACTIVE */ #define DMA_COMMON_ACTIVE_COUNT (1U) /*! @name COMMON_BUSY - Channel Busy status for all DMA channels. */ +/*! @{ */ #define DMA_COMMON_BUSY_BSY_MASK (0xFFFFFFFFU) #define DMA_COMMON_BUSY_BSY_SHIFT (0U) #define DMA_COMMON_BUSY_BSY(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BSY_SHIFT)) & DMA_COMMON_BUSY_BSY_MASK) +/*! @} */ /* The count of DMA_COMMON_BUSY */ #define DMA_COMMON_BUSY_COUNT (1U) /*! @name COMMON_ERRINT - Error Interrupt status for all DMA channels. */ +/*! @{ */ #define DMA_COMMON_ERRINT_ERR_MASK (0xFFFFFFFFU) #define DMA_COMMON_ERRINT_ERR_SHIFT (0U) #define DMA_COMMON_ERRINT_ERR(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR_SHIFT)) & DMA_COMMON_ERRINT_ERR_MASK) +/*! @} */ /* The count of DMA_COMMON_ERRINT */ #define DMA_COMMON_ERRINT_COUNT (1U) /*! @name COMMON_INTENSET - Interrupt Enable read and Set for all DMA channels. */ +/*! @{ */ #define DMA_COMMON_INTENSET_INTEN_MASK (0xFFFFFFFFU) #define DMA_COMMON_INTENSET_INTEN_SHIFT (0U) #define DMA_COMMON_INTENSET_INTEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN_SHIFT)) & DMA_COMMON_INTENSET_INTEN_MASK) +/*! @} */ /* The count of DMA_COMMON_INTENSET */ #define DMA_COMMON_INTENSET_COUNT (1U) /*! @name COMMON_INTENCLR - Interrupt Enable Clear for all DMA channels. */ +/*! @{ */ #define DMA_COMMON_INTENCLR_CLR_MASK (0xFFFFFFFFU) #define DMA_COMMON_INTENCLR_CLR_SHIFT (0U) #define DMA_COMMON_INTENCLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR_SHIFT)) & DMA_COMMON_INTENCLR_CLR_MASK) +/*! @} */ /* The count of DMA_COMMON_INTENCLR */ #define DMA_COMMON_INTENCLR_COUNT (1U) /*! @name COMMON_INTA - Interrupt A status for all DMA channels. */ +/*! @{ */ #define DMA_COMMON_INTA_IA_MASK (0xFFFFFFFFU) #define DMA_COMMON_INTA_IA_SHIFT (0U) #define DMA_COMMON_INTA_IA(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_IA_SHIFT)) & DMA_COMMON_INTA_IA_MASK) +/*! @} */ /* The count of DMA_COMMON_INTA */ #define DMA_COMMON_INTA_COUNT (1U) /*! @name COMMON_INTB - Interrupt B status for all DMA channels. */ +/*! @{ */ #define DMA_COMMON_INTB_IB_MASK (0xFFFFFFFFU) #define DMA_COMMON_INTB_IB_SHIFT (0U) #define DMA_COMMON_INTB_IB(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_IB_SHIFT)) & DMA_COMMON_INTB_IB_MASK) +/*! @} */ /* The count of DMA_COMMON_INTB */ #define DMA_COMMON_INTB_COUNT (1U) /*! @name COMMON_SETVALID - Set ValidPending control bits for all DMA channels. */ +/*! @{ */ #define DMA_COMMON_SETVALID_SV_MASK (0xFFFFFFFFU) #define DMA_COMMON_SETVALID_SV_SHIFT (0U) #define DMA_COMMON_SETVALID_SV(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SV_SHIFT)) & DMA_COMMON_SETVALID_SV_MASK) +/*! @} */ /* The count of DMA_COMMON_SETVALID */ #define DMA_COMMON_SETVALID_COUNT (1U) /*! @name COMMON_SETTRIG - Set Trigger control bits for all DMA channels. */ +/*! @{ */ #define DMA_COMMON_SETTRIG_TRIG_MASK (0xFFFFFFFFU) #define DMA_COMMON_SETTRIG_TRIG_SHIFT (0U) #define DMA_COMMON_SETTRIG_TRIG(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_TRIG_SHIFT)) & DMA_COMMON_SETTRIG_TRIG_MASK) +/*! @} */ /* The count of DMA_COMMON_SETTRIG */ #define DMA_COMMON_SETTRIG_COUNT (1U) /*! @name COMMON_ABORT - Channel Abort control for all DMA channels. */ +/*! @{ */ #define DMA_COMMON_ABORT_ABORTCTRL_MASK (0xFFFFFFFFU) #define DMA_COMMON_ABORT_ABORTCTRL_SHIFT (0U) #define DMA_COMMON_ABORT_ABORTCTRL(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORTCTRL_SHIFT)) & DMA_COMMON_ABORT_ABORTCTRL_MASK) +/*! @} */ /* The count of DMA_COMMON_ABORT */ #define DMA_COMMON_ABORT_COUNT (1U) /*! @name CHANNEL_CFG - Configuration register for DMA channel . */ +/*! @{ */ #define DMA_CHANNEL_CFG_PERIPHREQEN_MASK (0x1U) #define DMA_CHANNEL_CFG_PERIPHREQEN_SHIFT (0U) #define DMA_CHANNEL_CFG_PERIPHREQEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_PERIPHREQEN_SHIFT)) & DMA_CHANNEL_CFG_PERIPHREQEN_MASK) @@ -1221,22 +1350,26 @@ typedef struct { #define DMA_CHANNEL_CFG_CHPRIORITY_MASK (0x70000U) #define DMA_CHANNEL_CFG_CHPRIORITY_SHIFT (16U) #define DMA_CHANNEL_CFG_CHPRIORITY(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_CHPRIORITY_SHIFT)) & DMA_CHANNEL_CFG_CHPRIORITY_MASK) +/*! @} */ /* The count of DMA_CHANNEL_CFG */ #define DMA_CHANNEL_CFG_COUNT (20U) /*! @name CHANNEL_CTLSTAT - Control and status register for DMA channel . */ +/*! @{ */ #define DMA_CHANNEL_CTLSTAT_VALIDPENDING_MASK (0x1U) #define DMA_CHANNEL_CTLSTAT_VALIDPENDING_SHIFT (0U) #define DMA_CHANNEL_CTLSTAT_VALIDPENDING(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CTLSTAT_VALIDPENDING_SHIFT)) & DMA_CHANNEL_CTLSTAT_VALIDPENDING_MASK) #define DMA_CHANNEL_CTLSTAT_TRIG_MASK (0x4U) #define DMA_CHANNEL_CTLSTAT_TRIG_SHIFT (2U) #define DMA_CHANNEL_CTLSTAT_TRIG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CTLSTAT_TRIG_SHIFT)) & DMA_CHANNEL_CTLSTAT_TRIG_MASK) +/*! @} */ /* The count of DMA_CHANNEL_CTLSTAT */ #define DMA_CHANNEL_CTLSTAT_COUNT (20U) /*! @name CHANNEL_XFERCFG - Transfer configuration register for DMA channel . */ +/*! @{ */ #define DMA_CHANNEL_XFERCFG_CFGVALID_MASK (0x1U) #define DMA_CHANNEL_XFERCFG_CFGVALID_SHIFT (0U) #define DMA_CHANNEL_XFERCFG_CFGVALID(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_CFGVALID_SHIFT)) & DMA_CHANNEL_XFERCFG_CFGVALID_MASK) @@ -1267,6 +1400,7 @@ typedef struct { #define DMA_CHANNEL_XFERCFG_XFERCOUNT_MASK (0x3FF0000U) #define DMA_CHANNEL_XFERCFG_XFERCOUNT_SHIFT (16U) #define DMA_CHANNEL_XFERCFG_XFERCOUNT(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_XFERCOUNT_SHIFT)) & DMA_CHANNEL_XFERCFG_XFERCOUNT_MASK) +/*! @} */ /* The count of DMA_CHANNEL_XFERCFG */ #define DMA_CHANNEL_XFERCFG_COUNT (20U) @@ -1346,46 +1480,57 @@ typedef struct { */ /*! @name CHANNEL_OSR - Oversample Rate register 0 */ +/*! @{ */ #define DMIC_CHANNEL_OSR_OSR_MASK (0xFFU) #define DMIC_CHANNEL_OSR_OSR_SHIFT (0U) #define DMIC_CHANNEL_OSR_OSR(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_OSR_OSR_SHIFT)) & DMIC_CHANNEL_OSR_OSR_MASK) +/*! @} */ /* The count of DMIC_CHANNEL_OSR */ #define DMIC_CHANNEL_OSR_COUNT (2U) /*! @name CHANNEL_DIVHFCLK - DMIC Clock Register 0 */ +/*! @{ */ #define DMIC_CHANNEL_DIVHFCLK_PDMDIV_MASK (0xFU) #define DMIC_CHANNEL_DIVHFCLK_PDMDIV_SHIFT (0U) #define DMIC_CHANNEL_DIVHFCLK_PDMDIV(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_DIVHFCLK_PDMDIV_SHIFT)) & DMIC_CHANNEL_DIVHFCLK_PDMDIV_MASK) +/*! @} */ /* The count of DMIC_CHANNEL_DIVHFCLK */ #define DMIC_CHANNEL_DIVHFCLK_COUNT (2U) /*! @name CHANNEL_PREAC2FSCOEF - Pre-Emphasis Filter Coefficient for 2 FS register */ +/*! @{ */ #define DMIC_CHANNEL_PREAC2FSCOEF_COMP_MASK (0x3U) #define DMIC_CHANNEL_PREAC2FSCOEF_COMP_SHIFT (0U) #define DMIC_CHANNEL_PREAC2FSCOEF_COMP(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_PREAC2FSCOEF_COMP_SHIFT)) & DMIC_CHANNEL_PREAC2FSCOEF_COMP_MASK) +/*! @} */ /* The count of DMIC_CHANNEL_PREAC2FSCOEF */ #define DMIC_CHANNEL_PREAC2FSCOEF_COUNT (2U) /*! @name CHANNEL_PREAC4FSCOEF - Pre-Emphasis Filter Coefficient for 4 FS register */ +/*! @{ */ #define DMIC_CHANNEL_PREAC4FSCOEF_COMP_MASK (0x3U) #define DMIC_CHANNEL_PREAC4FSCOEF_COMP_SHIFT (0U) #define DMIC_CHANNEL_PREAC4FSCOEF_COMP(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_PREAC4FSCOEF_COMP_SHIFT)) & DMIC_CHANNEL_PREAC4FSCOEF_COMP_MASK) +/*! @} */ /* The count of DMIC_CHANNEL_PREAC4FSCOEF */ #define DMIC_CHANNEL_PREAC4FSCOEF_COUNT (2U) /*! @name CHANNEL_GAINSHIFT - Decimator Gain Shift register */ +/*! @{ */ #define DMIC_CHANNEL_GAINSHIFT_GAIN_MASK (0x3FU) #define DMIC_CHANNEL_GAINSHIFT_GAIN_SHIFT (0U) #define DMIC_CHANNEL_GAINSHIFT_GAIN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_GAINSHIFT_GAIN_SHIFT)) & DMIC_CHANNEL_GAINSHIFT_GAIN_MASK) +/*! @} */ /* The count of DMIC_CHANNEL_GAINSHIFT */ #define DMIC_CHANNEL_GAINSHIFT_COUNT (2U) /*! @name CHANNEL_FIFO_CTRL - FIFO Control register 0 */ +/*! @{ */ #define DMIC_CHANNEL_FIFO_CTRL_ENABLE_MASK (0x1U) #define DMIC_CHANNEL_FIFO_CTRL_ENABLE_SHIFT (0U) #define DMIC_CHANNEL_FIFO_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_CTRL_ENABLE_SHIFT)) & DMIC_CHANNEL_FIFO_CTRL_ENABLE_MASK) @@ -1401,11 +1546,13 @@ typedef struct { #define DMIC_CHANNEL_FIFO_CTRL_TRIGLVL_MASK (0x1F0000U) #define DMIC_CHANNEL_FIFO_CTRL_TRIGLVL_SHIFT (16U) #define DMIC_CHANNEL_FIFO_CTRL_TRIGLVL(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_CTRL_TRIGLVL_SHIFT)) & DMIC_CHANNEL_FIFO_CTRL_TRIGLVL_MASK) +/*! @} */ /* The count of DMIC_CHANNEL_FIFO_CTRL */ #define DMIC_CHANNEL_FIFO_CTRL_COUNT (2U) /*! @name CHANNEL_FIFO_STATUS - FIFO Status register 0 */ +/*! @{ */ #define DMIC_CHANNEL_FIFO_STATUS_INT_MASK (0x1U) #define DMIC_CHANNEL_FIFO_STATUS_INT_SHIFT (0U) #define DMIC_CHANNEL_FIFO_STATUS_INT(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_STATUS_INT_SHIFT)) & DMIC_CHANNEL_FIFO_STATUS_INT_MASK) @@ -1415,30 +1562,36 @@ typedef struct { #define DMIC_CHANNEL_FIFO_STATUS_UNDERRUN_MASK (0x4U) #define DMIC_CHANNEL_FIFO_STATUS_UNDERRUN_SHIFT (2U) #define DMIC_CHANNEL_FIFO_STATUS_UNDERRUN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_STATUS_UNDERRUN_SHIFT)) & DMIC_CHANNEL_FIFO_STATUS_UNDERRUN_MASK) +/*! @} */ /* The count of DMIC_CHANNEL_FIFO_STATUS */ #define DMIC_CHANNEL_FIFO_STATUS_COUNT (2U) /*! @name CHANNEL_FIFO_DATA - FIFO Data Register 0 */ +/*! @{ */ #define DMIC_CHANNEL_FIFO_DATA_DATA_MASK (0xFFFFFFU) #define DMIC_CHANNEL_FIFO_DATA_DATA_SHIFT (0U) #define DMIC_CHANNEL_FIFO_DATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_DATA_DATA_SHIFT)) & DMIC_CHANNEL_FIFO_DATA_DATA_MASK) +/*! @} */ /* The count of DMIC_CHANNEL_FIFO_DATA */ #define DMIC_CHANNEL_FIFO_DATA_COUNT (2U) /*! @name CHANNEL_PHY_CTRL - PDM Source Configuration register 0 */ +/*! @{ */ #define DMIC_CHANNEL_PHY_CTRL_PHY_FALL_MASK (0x1U) #define DMIC_CHANNEL_PHY_CTRL_PHY_FALL_SHIFT (0U) #define DMIC_CHANNEL_PHY_CTRL_PHY_FALL(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_PHY_CTRL_PHY_FALL_SHIFT)) & DMIC_CHANNEL_PHY_CTRL_PHY_FALL_MASK) #define DMIC_CHANNEL_PHY_CTRL_PHY_HALF_MASK (0x2U) #define DMIC_CHANNEL_PHY_CTRL_PHY_HALF_SHIFT (1U) #define DMIC_CHANNEL_PHY_CTRL_PHY_HALF(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_PHY_CTRL_PHY_HALF_SHIFT)) & DMIC_CHANNEL_PHY_CTRL_PHY_HALF_MASK) +/*! @} */ /* The count of DMIC_CHANNEL_PHY_CTRL */ #define DMIC_CHANNEL_PHY_CTRL_COUNT (2U) /*! @name CHANNEL_DC_CTRL - DC Control register 0 */ +/*! @{ */ #define DMIC_CHANNEL_DC_CTRL_DCPOLE_MASK (0x3U) #define DMIC_CHANNEL_DC_CTRL_DCPOLE_SHIFT (0U) #define DMIC_CHANNEL_DC_CTRL_DCPOLE(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_DC_CTRL_DCPOLE_SHIFT)) & DMIC_CHANNEL_DC_CTRL_DCPOLE_MASK) @@ -1448,19 +1601,23 @@ typedef struct { #define DMIC_CHANNEL_DC_CTRL_SATURATEAT16BIT_MASK (0x100U) #define DMIC_CHANNEL_DC_CTRL_SATURATEAT16BIT_SHIFT (8U) #define DMIC_CHANNEL_DC_CTRL_SATURATEAT16BIT(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_DC_CTRL_SATURATEAT16BIT_SHIFT)) & DMIC_CHANNEL_DC_CTRL_SATURATEAT16BIT_MASK) +/*! @} */ /* The count of DMIC_CHANNEL_DC_CTRL */ #define DMIC_CHANNEL_DC_CTRL_COUNT (2U) /*! @name CHANEN - Channel Enable register */ +/*! @{ */ #define DMIC_CHANEN_EN_CH0_MASK (0x1U) #define DMIC_CHANEN_EN_CH0_SHIFT (0U) #define DMIC_CHANEN_EN_CH0(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANEN_EN_CH0_SHIFT)) & DMIC_CHANEN_EN_CH0_MASK) #define DMIC_CHANEN_EN_CH1_MASK (0x2U) #define DMIC_CHANEN_EN_CH1_SHIFT (1U) #define DMIC_CHANEN_EN_CH1(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANEN_EN_CH1_SHIFT)) & DMIC_CHANEN_EN_CH1_MASK) +/*! @} */ /*! @name IOCFG - I/O Configuration register */ +/*! @{ */ #define DMIC_IOCFG_CLK_BYPASS0_MASK (0x1U) #define DMIC_IOCFG_CLK_BYPASS0_SHIFT (0U) #define DMIC_IOCFG_CLK_BYPASS0(x) (((uint32_t)(((uint32_t)(x)) << DMIC_IOCFG_CLK_BYPASS0_SHIFT)) & DMIC_IOCFG_CLK_BYPASS0_MASK) @@ -1470,51 +1627,70 @@ typedef struct { #define DMIC_IOCFG_STEREO_DATA0_MASK (0x4U) #define DMIC_IOCFG_STEREO_DATA0_SHIFT (2U) #define DMIC_IOCFG_STEREO_DATA0(x) (((uint32_t)(((uint32_t)(x)) << DMIC_IOCFG_STEREO_DATA0_SHIFT)) & DMIC_IOCFG_STEREO_DATA0_MASK) +/*! @} */ /*! @name USE2FS - Use 2FS register */ +/*! @{ */ #define DMIC_USE2FS_USE2FS_MASK (0x1U) #define DMIC_USE2FS_USE2FS_SHIFT (0U) #define DMIC_USE2FS_USE2FS(x) (((uint32_t)(((uint32_t)(x)) << DMIC_USE2FS_USE2FS_SHIFT)) & DMIC_USE2FS_USE2FS_MASK) +/*! @} */ /*! @name HWVADGAIN - HWVAD input gain register */ +/*! @{ */ #define DMIC_HWVADGAIN_INPUTGAIN_MASK (0xFU) #define DMIC_HWVADGAIN_INPUTGAIN_SHIFT (0U) #define DMIC_HWVADGAIN_INPUTGAIN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADGAIN_INPUTGAIN_SHIFT)) & DMIC_HWVADGAIN_INPUTGAIN_MASK) +/*! @} */ /*! @name HWVADHPFS - HWVAD filter control register */ +/*! @{ */ #define DMIC_HWVADHPFS_HPFS_MASK (0x3U) #define DMIC_HWVADHPFS_HPFS_SHIFT (0U) #define DMIC_HWVADHPFS_HPFS(x) (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADHPFS_HPFS_SHIFT)) & DMIC_HWVADHPFS_HPFS_MASK) +/*! @} */ /*! @name HWVADST10 - HWVAD control register */ +/*! @{ */ #define DMIC_HWVADST10_ST10_MASK (0x1U) #define DMIC_HWVADST10_ST10_SHIFT (0U) #define DMIC_HWVADST10_ST10(x) (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADST10_ST10_SHIFT)) & DMIC_HWVADST10_ST10_MASK) +/*! @} */ /*! @name HWVADRSTT - HWVAD filter reset register */ +/*! @{ */ #define DMIC_HWVADRSTT_RSTT_MASK (0x1U) #define DMIC_HWVADRSTT_RSTT_SHIFT (0U) #define DMIC_HWVADRSTT_RSTT(x) (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADRSTT_RSTT_SHIFT)) & DMIC_HWVADRSTT_RSTT_MASK) +/*! @} */ /*! @name HWVADTHGN - HWVAD noise estimator gain register */ +/*! @{ */ #define DMIC_HWVADTHGN_THGN_MASK (0xFU) #define DMIC_HWVADTHGN_THGN_SHIFT (0U) #define DMIC_HWVADTHGN_THGN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADTHGN_THGN_SHIFT)) & DMIC_HWVADTHGN_THGN_MASK) +/*! @} */ /*! @name HWVADTHGS - HWVAD signal estimator gain register */ +/*! @{ */ #define DMIC_HWVADTHGS_THGS_MASK (0xFU) #define DMIC_HWVADTHGS_THGS_SHIFT (0U) #define DMIC_HWVADTHGS_THGS(x) (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADTHGS_THGS_SHIFT)) & DMIC_HWVADTHGS_THGS_MASK) +/*! @} */ /*! @name HWVADLOWZ - HWVAD noise envelope estimator register */ +/*! @{ */ #define DMIC_HWVADLOWZ_LOWZ_MASK (0xFFFFU) #define DMIC_HWVADLOWZ_LOWZ_SHIFT (0U) #define DMIC_HWVADLOWZ_LOWZ(x) (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADLOWZ_LOWZ_SHIFT)) & DMIC_HWVADLOWZ_LOWZ_MASK) +/*! @} */ /*! @name ID - Module Identification register */ +/*! @{ */ #define DMIC_ID_ID_MASK (0xFFFFFFFFU) #define DMIC_ID_ID_SHIFT (0U) #define DMIC_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << DMIC_ID_ID_SHIFT)) & DMIC_ID_ID_MASK) +/*! @} */ /*! @@ -1566,6 +1742,7 @@ typedef struct { */ /*! @name PSELID - Peripheral Select and Flexcomm ID register. */ +/*! @{ */ #define FLEXCOMM_PSELID_PERSEL_MASK (0x7U) #define FLEXCOMM_PSELID_PERSEL_SHIFT (0U) #define FLEXCOMM_PSELID_PERSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_PERSEL_SHIFT)) & FLEXCOMM_PSELID_PERSEL_MASK) @@ -1587,8 +1764,10 @@ typedef struct { #define FLEXCOMM_PSELID_ID_MASK (0xFFFFF000U) #define FLEXCOMM_PSELID_ID_SHIFT (12U) #define FLEXCOMM_PSELID_ID(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_ID_SHIFT)) & FLEXCOMM_PSELID_ID_MASK) +/*! @} */ /*! @name PID - Peripheral identification register. */ +/*! @{ */ #define FLEXCOMM_PID_Minor_Rev_MASK (0xF00U) #define FLEXCOMM_PID_Minor_Rev_SHIFT (8U) #define FLEXCOMM_PID_Minor_Rev(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PID_Minor_Rev_SHIFT)) & FLEXCOMM_PID_Minor_Rev_MASK) @@ -1598,6 +1777,7 @@ typedef struct { #define FLEXCOMM_PID_ID_MASK (0xFFFF0000U) #define FLEXCOMM_PID_ID_SHIFT (16U) #define FLEXCOMM_PID_ID(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PID_ID_SHIFT)) & FLEXCOMM_PID_ID_MASK) +/*! @} */ /*! @@ -1678,6 +1858,7 @@ typedef struct { */ /*! @name CTRL - GPIO grouped interrupt control register */ +/*! @{ */ #define GINT_CTRL_INT_MASK (0x1U) #define GINT_CTRL_INT_SHIFT (0U) #define GINT_CTRL_INT(x) (((uint32_t)(((uint32_t)(x)) << GINT_CTRL_INT_SHIFT)) & GINT_CTRL_INT_MASK) @@ -1687,19 +1868,24 @@ typedef struct { #define GINT_CTRL_TRIG_MASK (0x4U) #define GINT_CTRL_TRIG_SHIFT (2U) #define GINT_CTRL_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GINT_CTRL_TRIG_SHIFT)) & GINT_CTRL_TRIG_MASK) +/*! @} */ /*! @name PORT_POL - GPIO grouped interrupt port 0 polarity register */ +/*! @{ */ #define GINT_PORT_POL_POL_MASK (0xFFFFFFFFU) #define GINT_PORT_POL_POL_SHIFT (0U) #define GINT_PORT_POL_POL(x) (((uint32_t)(((uint32_t)(x)) << GINT_PORT_POL_POL_SHIFT)) & GINT_PORT_POL_POL_MASK) +/*! @} */ /* The count of GINT_PORT_POL */ #define GINT_PORT_POL_COUNT (2U) /*! @name PORT_ENA - GPIO grouped interrupt port 0 enable register */ +/*! @{ */ #define GINT_PORT_ENA_ENA_MASK (0xFFFFFFFFU) #define GINT_PORT_ENA_ENA_SHIFT (0U) #define GINT_PORT_ENA_ENA(x) (((uint32_t)(((uint32_t)(x)) << GINT_PORT_ENA_ENA_SHIFT)) & GINT_PORT_ENA_ENA_MASK) +/*! @} */ /* The count of GINT_PORT_ENA */ #define GINT_PORT_ENA_COUNT (2U) @@ -1777,9 +1963,11 @@ typedef struct { */ /*! @name B - Byte pin registers for all port 0 and 1 GPIO pins */ +/*! @{ */ #define GPIO_B_PBYTE_MASK (0x1U) #define GPIO_B_PBYTE_SHIFT (0U) #define GPIO_B_PBYTE(x) (((uint8_t)(((uint8_t)(x)) << GPIO_B_PBYTE_SHIFT)) & GPIO_B_PBYTE_MASK) +/*! @} */ /* The count of GPIO_B */ #define GPIO_B_COUNT (2U) @@ -1788,9 +1976,11 @@ typedef struct { #define GPIO_B_COUNT2 (32U) /*! @name W - Word pin registers for all port 0 and 1 GPIO pins */ +/*! @{ */ #define GPIO_W_PWORD_MASK (0xFFFFFFFFU) #define GPIO_W_PWORD_SHIFT (0U) #define GPIO_W_PWORD(x) (((uint32_t)(((uint32_t)(x)) << GPIO_W_PWORD_SHIFT)) & GPIO_W_PWORD_MASK) +/*! @} */ /* The count of GPIO_W */ #define GPIO_W_COUNT (2U) @@ -1799,81 +1989,101 @@ typedef struct { #define GPIO_W_COUNT2 (32U) /*! @name DIR - Direction registers */ +/*! @{ */ #define GPIO_DIR_DIRP_MASK (0xFFFFFFFFU) #define GPIO_DIR_DIRP_SHIFT (0U) #define GPIO_DIR_DIRP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP_SHIFT)) & GPIO_DIR_DIRP_MASK) +/*! @} */ /* The count of GPIO_DIR */ #define GPIO_DIR_COUNT (2U) /*! @name MASK - Mask register */ +/*! @{ */ #define GPIO_MASK_MASKP_MASK (0xFFFFFFFFU) #define GPIO_MASK_MASKP_SHIFT (0U) #define GPIO_MASK_MASKP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP_SHIFT)) & GPIO_MASK_MASKP_MASK) +/*! @} */ /* The count of GPIO_MASK */ #define GPIO_MASK_COUNT (2U) /*! @name PIN - Port pin register */ +/*! @{ */ #define GPIO_PIN_PORT_MASK (0xFFFFFFFFU) #define GPIO_PIN_PORT_SHIFT (0U) #define GPIO_PIN_PORT(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT_SHIFT)) & GPIO_PIN_PORT_MASK) +/*! @} */ /* The count of GPIO_PIN */ #define GPIO_PIN_COUNT (2U) /*! @name MPIN - Masked port register */ +/*! @{ */ #define GPIO_MPIN_MPORTP_MASK (0xFFFFFFFFU) #define GPIO_MPIN_MPORTP_SHIFT (0U) #define GPIO_MPIN_MPORTP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP_SHIFT)) & GPIO_MPIN_MPORTP_MASK) +/*! @} */ /* The count of GPIO_MPIN */ #define GPIO_MPIN_COUNT (2U) /*! @name SET - Write: Set register for port Read: output bits for port */ +/*! @{ */ #define GPIO_SET_SETP_MASK (0xFFFFFFFFU) #define GPIO_SET_SETP_SHIFT (0U) #define GPIO_SET_SETP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_SET_SETP_SHIFT)) & GPIO_SET_SETP_MASK) +/*! @} */ /* The count of GPIO_SET */ #define GPIO_SET_COUNT (2U) /*! @name CLR - Clear port */ +/*! @{ */ #define GPIO_CLR_CLRP_MASK (0xFFFFFFFFU) #define GPIO_CLR_CLRP_SHIFT (0U) #define GPIO_CLR_CLRP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP_SHIFT)) & GPIO_CLR_CLRP_MASK) +/*! @} */ /* The count of GPIO_CLR */ #define GPIO_CLR_COUNT (2U) /*! @name NOT - Toggle port */ +/*! @{ */ #define GPIO_NOT_NOTP_MASK (0xFFFFFFFFU) #define GPIO_NOT_NOTP_SHIFT (0U) #define GPIO_NOT_NOTP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP_SHIFT)) & GPIO_NOT_NOTP_MASK) +/*! @} */ /* The count of GPIO_NOT */ #define GPIO_NOT_COUNT (2U) /*! @name DIRSET - Set pin direction bits for port */ +/*! @{ */ #define GPIO_DIRSET_DIRSETP_MASK (0x1FFFFFFFU) #define GPIO_DIRSET_DIRSETP_SHIFT (0U) #define GPIO_DIRSET_DIRSETP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP_SHIFT)) & GPIO_DIRSET_DIRSETP_MASK) +/*! @} */ /* The count of GPIO_DIRSET */ #define GPIO_DIRSET_COUNT (2U) /*! @name DIRCLR - Clear pin direction bits for port */ +/*! @{ */ #define GPIO_DIRCLR_DIRCLRP_MASK (0x1FFFFFFFU) #define GPIO_DIRCLR_DIRCLRP_SHIFT (0U) #define GPIO_DIRCLR_DIRCLRP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP_SHIFT)) & GPIO_DIRCLR_DIRCLRP_MASK) +/*! @} */ /* The count of GPIO_DIRCLR */ #define GPIO_DIRCLR_COUNT (2U) /*! @name DIRNOT - Toggle pin direction bits for port */ +/*! @{ */ #define GPIO_DIRNOT_DIRNOTP_MASK (0x1FFFFFFFU) #define GPIO_DIRNOT_DIRNOTP_SHIFT (0U) #define GPIO_DIRNOT_DIRNOTP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRNOT_DIRNOTP_SHIFT)) & GPIO_DIRNOT_DIRNOTP_MASK) +/*! @} */ /* The count of GPIO_DIRNOT */ #define GPIO_DIRNOT_COUNT (2U) @@ -1941,6 +2151,7 @@ typedef struct { */ /*! @name CFG - Configuration for shared functions. */ +/*! @{ */ #define I2C_CFG_MSTEN_MASK (0x1U) #define I2C_CFG_MSTEN_SHIFT (0U) #define I2C_CFG_MSTEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_MSTEN_SHIFT)) & I2C_CFG_MSTEN_MASK) @@ -1959,8 +2170,10 @@ typedef struct { #define I2C_CFG_HSCAPABLE_MASK (0x20U) #define I2C_CFG_HSCAPABLE_SHIFT (5U) #define I2C_CFG_HSCAPABLE(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_HSCAPABLE_SHIFT)) & I2C_CFG_HSCAPABLE_MASK) +/*! @} */ /*! @name STAT - Status register for Master, Slave, and Monitor functions. */ +/*! @{ */ #define I2C_STAT_MSTPENDING_MASK (0x1U) #define I2C_STAT_MSTPENDING_SHIFT (0U) #define I2C_STAT_MSTPENDING(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTPENDING_SHIFT)) & I2C_STAT_MSTPENDING_MASK) @@ -2009,8 +2222,10 @@ typedef struct { #define I2C_STAT_SCLTIMEOUT_MASK (0x2000000U) #define I2C_STAT_SCLTIMEOUT_SHIFT (25U) #define I2C_STAT_SCLTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SCLTIMEOUT_SHIFT)) & I2C_STAT_SCLTIMEOUT_MASK) +/*! @} */ /*! @name INTENSET - Interrupt Enable Set and read register. */ +/*! @{ */ #define I2C_INTENSET_MSTPENDINGEN_MASK (0x1U) #define I2C_INTENSET_MSTPENDINGEN_SHIFT (0U) #define I2C_INTENSET_MSTPENDINGEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MSTPENDINGEN_SHIFT)) & I2C_INTENSET_MSTPENDINGEN_MASK) @@ -2044,8 +2259,10 @@ typedef struct { #define I2C_INTENSET_SCLTIMEOUTEN_MASK (0x2000000U) #define I2C_INTENSET_SCLTIMEOUTEN_SHIFT (25U) #define I2C_INTENSET_SCLTIMEOUTEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SCLTIMEOUTEN_SHIFT)) & I2C_INTENSET_SCLTIMEOUTEN_MASK) +/*! @} */ /*! @name INTENCLR - Interrupt Enable Clear register. */ +/*! @{ */ #define I2C_INTENCLR_MSTPENDINGCLR_MASK (0x1U) #define I2C_INTENCLR_MSTPENDINGCLR_SHIFT (0U) #define I2C_INTENCLR_MSTPENDINGCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MSTPENDINGCLR_SHIFT)) & I2C_INTENCLR_MSTPENDINGCLR_MASK) @@ -2079,21 +2296,27 @@ typedef struct { #define I2C_INTENCLR_SCLTIMEOUTCLR_MASK (0x2000000U) #define I2C_INTENCLR_SCLTIMEOUTCLR_SHIFT (25U) #define I2C_INTENCLR_SCLTIMEOUTCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SCLTIMEOUTCLR_SHIFT)) & I2C_INTENCLR_SCLTIMEOUTCLR_MASK) +/*! @} */ /*! @name TIMEOUT - Time-out value register. */ +/*! @{ */ #define I2C_TIMEOUT_TOMIN_MASK (0xFU) #define I2C_TIMEOUT_TOMIN_SHIFT (0U) #define I2C_TIMEOUT_TOMIN(x) (((uint32_t)(((uint32_t)(x)) << I2C_TIMEOUT_TOMIN_SHIFT)) & I2C_TIMEOUT_TOMIN_MASK) #define I2C_TIMEOUT_TO_MASK (0xFFF0U) #define I2C_TIMEOUT_TO_SHIFT (4U) #define I2C_TIMEOUT_TO(x) (((uint32_t)(((uint32_t)(x)) << I2C_TIMEOUT_TO_SHIFT)) & I2C_TIMEOUT_TO_MASK) +/*! @} */ /*! @name CLKDIV - Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register, and controls some timing of the Slave function. */ +/*! @{ */ #define I2C_CLKDIV_DIVVAL_MASK (0xFFFFU) #define I2C_CLKDIV_DIVVAL_SHIFT (0U) #define I2C_CLKDIV_DIVVAL(x) (((uint32_t)(((uint32_t)(x)) << I2C_CLKDIV_DIVVAL_SHIFT)) & I2C_CLKDIV_DIVVAL_MASK) +/*! @} */ /*! @name INTSTAT - Interrupt Status register for Master, Slave, and Monitor functions. */ +/*! @{ */ #define I2C_INTSTAT_MSTPENDING_MASK (0x1U) #define I2C_INTSTAT_MSTPENDING_SHIFT (0U) #define I2C_INTSTAT_MSTPENDING(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MSTPENDING_SHIFT)) & I2C_INTSTAT_MSTPENDING_MASK) @@ -2127,8 +2350,10 @@ typedef struct { #define I2C_INTSTAT_SCLTIMEOUT_MASK (0x2000000U) #define I2C_INTSTAT_SCLTIMEOUT_SHIFT (25U) #define I2C_INTSTAT_SCLTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SCLTIMEOUT_SHIFT)) & I2C_INTSTAT_SCLTIMEOUT_MASK) +/*! @} */ /*! @name MSTCTL - Master control register. */ +/*! @{ */ #define I2C_MSTCTL_MSTCONTINUE_MASK (0x1U) #define I2C_MSTCTL_MSTCONTINUE_SHIFT (0U) #define I2C_MSTCTL_MSTCONTINUE(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTCONTINUE_SHIFT)) & I2C_MSTCTL_MSTCONTINUE_MASK) @@ -2141,21 +2366,27 @@ typedef struct { #define I2C_MSTCTL_MSTDMA_MASK (0x8U) #define I2C_MSTCTL_MSTDMA_SHIFT (3U) #define I2C_MSTCTL_MSTDMA(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTDMA_SHIFT)) & I2C_MSTCTL_MSTDMA_MASK) +/*! @} */ /*! @name MSTTIME - Master timing configuration. */ +/*! @{ */ #define I2C_MSTTIME_MSTSCLLOW_MASK (0x7U) #define I2C_MSTTIME_MSTSCLLOW_SHIFT (0U) #define I2C_MSTTIME_MSTSCLLOW(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTTIME_MSTSCLLOW_SHIFT)) & I2C_MSTTIME_MSTSCLLOW_MASK) #define I2C_MSTTIME_MSTSCLHIGH_MASK (0x70U) #define I2C_MSTTIME_MSTSCLHIGH_SHIFT (4U) #define I2C_MSTTIME_MSTSCLHIGH(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTTIME_MSTSCLHIGH_SHIFT)) & I2C_MSTTIME_MSTSCLHIGH_MASK) +/*! @} */ /*! @name MSTDAT - Combined Master receiver and transmitter data register. */ +/*! @{ */ #define I2C_MSTDAT_DATA_MASK (0xFFU) #define I2C_MSTDAT_DATA_SHIFT (0U) #define I2C_MSTDAT_DATA(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTDAT_DATA_SHIFT)) & I2C_MSTDAT_DATA_MASK) +/*! @} */ /*! @name SLVCTL - Slave control register. */ +/*! @{ */ #define I2C_SLVCTL_SLVCONTINUE_MASK (0x1U) #define I2C_SLVCTL_SLVCONTINUE_SHIFT (0U) #define I2C_SLVCTL_SLVCONTINUE(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_SLVCONTINUE_SHIFT)) & I2C_SLVCTL_SLVCONTINUE_MASK) @@ -2171,13 +2402,17 @@ typedef struct { #define I2C_SLVCTL_AUTOMATCHREAD_MASK (0x200U) #define I2C_SLVCTL_AUTOMATCHREAD_SHIFT (9U) #define I2C_SLVCTL_AUTOMATCHREAD(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_AUTOMATCHREAD_SHIFT)) & I2C_SLVCTL_AUTOMATCHREAD_MASK) +/*! @} */ /*! @name SLVDAT - Combined Slave receiver and transmitter data register. */ +/*! @{ */ #define I2C_SLVDAT_DATA_MASK (0xFFU) #define I2C_SLVDAT_DATA_SHIFT (0U) #define I2C_SLVDAT_DATA(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVDAT_DATA_SHIFT)) & I2C_SLVDAT_DATA_MASK) +/*! @} */ /*! @name SLVADR - Slave address register. */ +/*! @{ */ #define I2C_SLVADR_SADISABLE_MASK (0x1U) #define I2C_SLVADR_SADISABLE_SHIFT (0U) #define I2C_SLVADR_SADISABLE(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVADR_SADISABLE_SHIFT)) & I2C_SLVADR_SADISABLE_MASK) @@ -2187,19 +2422,23 @@ typedef struct { #define I2C_SLVADR_AUTONACK_MASK (0x8000U) #define I2C_SLVADR_AUTONACK_SHIFT (15U) #define I2C_SLVADR_AUTONACK(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVADR_AUTONACK_SHIFT)) & I2C_SLVADR_AUTONACK_MASK) +/*! @} */ /* The count of I2C_SLVADR */ #define I2C_SLVADR_COUNT (4U) /*! @name SLVQUAL0 - Slave Qualification for address 0. */ +/*! @{ */ #define I2C_SLVQUAL0_QUALMODE0_MASK (0x1U) #define I2C_SLVQUAL0_QUALMODE0_SHIFT (0U) #define I2C_SLVQUAL0_QUALMODE0(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVQUAL0_QUALMODE0_SHIFT)) & I2C_SLVQUAL0_QUALMODE0_MASK) #define I2C_SLVQUAL0_SLVQUAL0_MASK (0xFEU) #define I2C_SLVQUAL0_SLVQUAL0_SHIFT (1U) #define I2C_SLVQUAL0_SLVQUAL0(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVQUAL0_SLVQUAL0_SHIFT)) & I2C_SLVQUAL0_SLVQUAL0_MASK) +/*! @} */ /*! @name MONRXDAT - Monitor receiver data register. */ +/*! @{ */ #define I2C_MONRXDAT_MONRXDAT_MASK (0xFFU) #define I2C_MONRXDAT_MONRXDAT_SHIFT (0U) #define I2C_MONRXDAT_MONRXDAT(x) (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONRXDAT_SHIFT)) & I2C_MONRXDAT_MONRXDAT_MASK) @@ -2212,6 +2451,7 @@ typedef struct { #define I2C_MONRXDAT_MONNACK_MASK (0x400U) #define I2C_MONRXDAT_MONNACK_SHIFT (10U) #define I2C_MONRXDAT_MONNACK(x) (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONNACK_SHIFT)) & I2C_MONRXDAT_MONNACK_MASK) +/*! @} */ /*! @@ -2310,6 +2550,7 @@ typedef struct { */ /*! @name CFG1 - Configuration register 1 for the primary channel pair. */ +/*! @{ */ #define I2S_CFG1_MAINENABLE_MASK (0x1U) #define I2S_CFG1_MAINENABLE_SHIFT (0U) #define I2S_CFG1_MAINENABLE(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_MAINENABLE_SHIFT)) & I2S_CFG1_MAINENABLE_MASK) @@ -2346,16 +2587,20 @@ typedef struct { #define I2S_CFG1_DATALEN_MASK (0x1F0000U) #define I2S_CFG1_DATALEN_SHIFT (16U) #define I2S_CFG1_DATALEN(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_DATALEN_SHIFT)) & I2S_CFG1_DATALEN_MASK) +/*! @} */ /*! @name CFG2 - Configuration register 2 for the primary channel pair. */ +/*! @{ */ #define I2S_CFG2_FRAMELEN_MASK (0x1FFU) #define I2S_CFG2_FRAMELEN_SHIFT (0U) #define I2S_CFG2_FRAMELEN(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG2_FRAMELEN_SHIFT)) & I2S_CFG2_FRAMELEN_MASK) #define I2S_CFG2_POSITION_MASK (0x1FF0000U) #define I2S_CFG2_POSITION_SHIFT (16U) #define I2S_CFG2_POSITION(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG2_POSITION_SHIFT)) & I2S_CFG2_POSITION_MASK) +/*! @} */ /*! @name STAT - Status register for the primary channel pair. */ +/*! @{ */ #define I2S_STAT_BUSY_MASK (0x1U) #define I2S_STAT_BUSY_SHIFT (0U) #define I2S_STAT_BUSY(x) (((uint32_t)(((uint32_t)(x)) << I2S_STAT_BUSY_SHIFT)) & I2S_STAT_BUSY_MASK) @@ -2368,13 +2613,17 @@ typedef struct { #define I2S_STAT_DATAPAUSED_MASK (0x8U) #define I2S_STAT_DATAPAUSED_SHIFT (3U) #define I2S_STAT_DATAPAUSED(x) (((uint32_t)(((uint32_t)(x)) << I2S_STAT_DATAPAUSED_SHIFT)) & I2S_STAT_DATAPAUSED_MASK) +/*! @} */ /*! @name DIV - Clock divider, used by all channel pairs. */ +/*! @{ */ #define I2S_DIV_DIV_MASK (0xFFFU) #define I2S_DIV_DIV_SHIFT (0U) #define I2S_DIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << I2S_DIV_DIV_SHIFT)) & I2S_DIV_DIV_MASK) +/*! @} */ /*! @name FIFOCFG - FIFO configuration and enable register. */ +/*! @{ */ #define I2S_FIFOCFG_ENABLETX_MASK (0x1U) #define I2S_FIFOCFG_ENABLETX_SHIFT (0U) #define I2S_FIFOCFG_ENABLETX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_ENABLETX_SHIFT)) & I2S_FIFOCFG_ENABLETX_MASK) @@ -2411,8 +2660,10 @@ typedef struct { #define I2S_FIFOCFG_POPDBG_MASK (0x40000U) #define I2S_FIFOCFG_POPDBG_SHIFT (18U) #define I2S_FIFOCFG_POPDBG(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_POPDBG_SHIFT)) & I2S_FIFOCFG_POPDBG_MASK) +/*! @} */ /*! @name FIFOSTAT - FIFO status register. */ +/*! @{ */ #define I2S_FIFOSTAT_TXERR_MASK (0x1U) #define I2S_FIFOSTAT_TXERR_SHIFT (0U) #define I2S_FIFOSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_TXERR_SHIFT)) & I2S_FIFOSTAT_TXERR_MASK) @@ -2440,8 +2691,10 @@ typedef struct { #define I2S_FIFOSTAT_RXLVL_MASK (0x1F0000U) #define I2S_FIFOSTAT_RXLVL_SHIFT (16U) #define I2S_FIFOSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_RXLVL_SHIFT)) & I2S_FIFOSTAT_RXLVL_MASK) +/*! @} */ /*! @name FIFOTRIG - FIFO trigger settings for interrupt and DMA request. */ +/*! @{ */ #define I2S_FIFOTRIG_TXLVLENA_MASK (0x1U) #define I2S_FIFOTRIG_TXLVLENA_SHIFT (0U) #define I2S_FIFOTRIG_TXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOTRIG_TXLVLENA_SHIFT)) & I2S_FIFOTRIG_TXLVLENA_MASK) @@ -2454,8 +2707,10 @@ typedef struct { #define I2S_FIFOTRIG_RXLVL_MASK (0xF0000U) #define I2S_FIFOTRIG_RXLVL_SHIFT (16U) #define I2S_FIFOTRIG_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOTRIG_RXLVL_SHIFT)) & I2S_FIFOTRIG_RXLVL_MASK) +/*! @} */ /*! @name FIFOINTENSET - FIFO interrupt enable set (enable) and read register. */ +/*! @{ */ #define I2S_FIFOINTENSET_TXERR_MASK (0x1U) #define I2S_FIFOINTENSET_TXERR_SHIFT (0U) #define I2S_FIFOINTENSET_TXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENSET_TXERR_SHIFT)) & I2S_FIFOINTENSET_TXERR_MASK) @@ -2468,8 +2723,10 @@ typedef struct { #define I2S_FIFOINTENSET_RXLVL_MASK (0x8U) #define I2S_FIFOINTENSET_RXLVL_SHIFT (3U) #define I2S_FIFOINTENSET_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENSET_RXLVL_SHIFT)) & I2S_FIFOINTENSET_RXLVL_MASK) +/*! @} */ /*! @name FIFOINTENCLR - FIFO interrupt enable clear (disable) and read register. */ +/*! @{ */ #define I2S_FIFOINTENCLR_TXERR_MASK (0x1U) #define I2S_FIFOINTENCLR_TXERR_SHIFT (0U) #define I2S_FIFOINTENCLR_TXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENCLR_TXERR_SHIFT)) & I2S_FIFOINTENCLR_TXERR_MASK) @@ -2482,8 +2739,10 @@ typedef struct { #define I2S_FIFOINTENCLR_RXLVL_MASK (0x8U) #define I2S_FIFOINTENCLR_RXLVL_SHIFT (3U) #define I2S_FIFOINTENCLR_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENCLR_RXLVL_SHIFT)) & I2S_FIFOINTENCLR_RXLVL_MASK) +/*! @} */ /*! @name FIFOINTSTAT - FIFO interrupt status register. */ +/*! @{ */ #define I2S_FIFOINTSTAT_TXERR_MASK (0x1U) #define I2S_FIFOINTSTAT_TXERR_SHIFT (0U) #define I2S_FIFOINTSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_TXERR_SHIFT)) & I2S_FIFOINTSTAT_TXERR_MASK) @@ -2499,36 +2758,49 @@ typedef struct { #define I2S_FIFOINTSTAT_PERINT_MASK (0x10U) #define I2S_FIFOINTSTAT_PERINT_SHIFT (4U) #define I2S_FIFOINTSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_PERINT_SHIFT)) & I2S_FIFOINTSTAT_PERINT_MASK) +/*! @} */ /*! @name FIFOWR - FIFO write data. */ +/*! @{ */ #define I2S_FIFOWR_TXDATA_MASK (0xFFFFFFFFU) #define I2S_FIFOWR_TXDATA_SHIFT (0U) #define I2S_FIFOWR_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOWR_TXDATA_SHIFT)) & I2S_FIFOWR_TXDATA_MASK) +/*! @} */ /*! @name FIFOWR48H - FIFO write data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA. */ +/*! @{ */ #define I2S_FIFOWR48H_TXDATA_MASK (0xFFFFFFU) #define I2S_FIFOWR48H_TXDATA_SHIFT (0U) #define I2S_FIFOWR48H_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOWR48H_TXDATA_SHIFT)) & I2S_FIFOWR48H_TXDATA_MASK) +/*! @} */ /*! @name FIFORD - FIFO read data. */ +/*! @{ */ #define I2S_FIFORD_RXDATA_MASK (0xFFFFFFFFU) #define I2S_FIFORD_RXDATA_SHIFT (0U) #define I2S_FIFORD_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFORD_RXDATA_SHIFT)) & I2S_FIFORD_RXDATA_MASK) +/*! @} */ /*! @name FIFORD48H - FIFO read data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA. */ +/*! @{ */ #define I2S_FIFORD48H_RXDATA_MASK (0xFFFFFFU) #define I2S_FIFORD48H_RXDATA_SHIFT (0U) #define I2S_FIFORD48H_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFORD48H_RXDATA_SHIFT)) & I2S_FIFORD48H_RXDATA_MASK) +/*! @} */ /*! @name FIFORDNOPOP - FIFO data read with no FIFO pop. */ +/*! @{ */ #define I2S_FIFORDNOPOP_RXDATA_MASK (0xFFFFFFFFU) #define I2S_FIFORDNOPOP_RXDATA_SHIFT (0U) #define I2S_FIFORDNOPOP_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFORDNOPOP_RXDATA_SHIFT)) & I2S_FIFORDNOPOP_RXDATA_MASK) +/*! @} */ /*! @name FIFORD48HNOPOP - FIFO data read for upper data bits with no FIFO pop. May only be used if the I2S is configured for 2x 24-bit data and not using DMA. */ +/*! @{ */ #define I2S_FIFORD48HNOPOP_RXDATA_MASK (0xFFFFFFU) #define I2S_FIFORD48HNOPOP_RXDATA_SHIFT (0U) #define I2S_FIFORD48HNOPOP_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFORD48HNOPOP_RXDATA_SHIFT)) & I2S_FIFORD48HNOPOP_RXDATA_MASK) +/*! @} */ /*! @@ -2588,38 +2860,48 @@ typedef struct { */ /*! @name PINTSEL - Pin interrupt select register */ +/*! @{ */ #define INPUTMUX_PINTSEL_INTPIN_MASK (0xFFU) #define INPUTMUX_PINTSEL_INTPIN_SHIFT (0U) #define INPUTMUX_PINTSEL_INTPIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_PINTSEL_INTPIN_SHIFT)) & INPUTMUX_PINTSEL_INTPIN_MASK) +/*! @} */ /* The count of INPUTMUX_PINTSEL */ #define INPUTMUX_PINTSEL_COUNT (8U) /*! @name DMA_ITRIG_INMUX - Trigger select register for DMA channel */ +/*! @{ */ #define INPUTMUX_DMA_ITRIG_INMUX_INP_MASK (0x1FU) #define INPUTMUX_DMA_ITRIG_INMUX_INP_SHIFT (0U) #define INPUTMUX_DMA_ITRIG_INMUX_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA_ITRIG_INMUX_INP_SHIFT)) & INPUTMUX_DMA_ITRIG_INMUX_INP_MASK) +/*! @} */ /* The count of INPUTMUX_DMA_ITRIG_INMUX */ #define INPUTMUX_DMA_ITRIG_INMUX_COUNT (22U) /*! @name DMA_OTRIG_INMUX - DMA output trigger selection to become DMA trigger */ +/*! @{ */ #define INPUTMUX_DMA_OTRIG_INMUX_INP_MASK (0x1FU) #define INPUTMUX_DMA_OTRIG_INMUX_INP_SHIFT (0U) #define INPUTMUX_DMA_OTRIG_INMUX_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA_OTRIG_INMUX_INP_SHIFT)) & INPUTMUX_DMA_OTRIG_INMUX_INP_MASK) +/*! @} */ /* The count of INPUTMUX_DMA_OTRIG_INMUX */ #define INPUTMUX_DMA_OTRIG_INMUX_COUNT (4U) /*! @name FREQMEAS_REF - Selection for frequency measurement reference clock */ +/*! @{ */ #define INPUTMUX_FREQMEAS_REF_CLKIN_MASK (0x1FU) #define INPUTMUX_FREQMEAS_REF_CLKIN_SHIFT (0U) #define INPUTMUX_FREQMEAS_REF_CLKIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FREQMEAS_REF_CLKIN_SHIFT)) & INPUTMUX_FREQMEAS_REF_CLKIN_MASK) +/*! @} */ /*! @name FREQMEAS_TARGET - Selection for frequency measurement target clock */ +/*! @{ */ #define INPUTMUX_FREQMEAS_TARGET_CLKIN_MASK (0x1FU) #define INPUTMUX_FREQMEAS_TARGET_CLKIN_SHIFT (0U) #define INPUTMUX_FREQMEAS_TARGET_CLKIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FREQMEAS_TARGET_CLKIN_SHIFT)) & INPUTMUX_FREQMEAS_TARGET_CLKIN_MASK) +/*! @} */ /*! @@ -2666,6 +2948,7 @@ typedef struct { */ /*! @name PIO - Digital I/O control for port 0 pins PIO0_0..Digital I/O control for port 1 pins PIO1_31 */ +/*! @{ */ #define IOCON_PIO_FUNC_MASK (0x7U) #define IOCON_PIO_FUNC_SHIFT (0U) #define IOCON_PIO_FUNC(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_FUNC_SHIFT)) & IOCON_PIO_FUNC_MASK) @@ -2690,12 +2973,13 @@ typedef struct { #define IOCON_PIO_SLEW_MASK (0x200U) #define IOCON_PIO_SLEW_SHIFT (9U) #define IOCON_PIO_SLEW(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_SLEW_SHIFT)) & IOCON_PIO_SLEW_MASK) -#define IOCON_PIO_OD_MASK (0x400U) -#define IOCON_PIO_OD_SHIFT (10U) -#define IOCON_PIO_OD(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_OD_SHIFT)) & IOCON_PIO_OD_MASK) #define IOCON_PIO_I2CFILTER_MASK (0x400U) #define IOCON_PIO_I2CFILTER_SHIFT (10U) #define IOCON_PIO_I2CFILTER(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_I2CFILTER_SHIFT)) & IOCON_PIO_I2CFILTER_MASK) +#define IOCON_PIO_OD_MASK (0x400U) +#define IOCON_PIO_OD_SHIFT (10U) +#define IOCON_PIO_OD(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_OD_SHIFT)) & IOCON_PIO_OD_MASK) +/*! @} */ /* The count of IOCON_PIO */ #define IOCON_PIO_COUNT (2U) @@ -2755,33 +3039,41 @@ typedef struct { */ /*! @name MBOXIRQ_IRQ - Interrupt request register for the Cortex-M0+ CPU. */ +/*! @{ */ #define MAILBOX_MBOXIRQ_IRQ_INTREQ_MASK (0xFFFFFFFFU) #define MAILBOX_MBOXIRQ_IRQ_INTREQ_SHIFT (0U) #define MAILBOX_MBOXIRQ_IRQ_INTREQ(x) (((uint32_t)(((uint32_t)(x)) << MAILBOX_MBOXIRQ_IRQ_INTREQ_SHIFT)) & MAILBOX_MBOXIRQ_IRQ_INTREQ_MASK) +/*! @} */ /* The count of MAILBOX_MBOXIRQ_IRQ */ #define MAILBOX_MBOXIRQ_IRQ_COUNT (2U) /*! @name MBOXIRQ_IRQSET - Set bits in IRQ0 */ +/*! @{ */ #define MAILBOX_MBOXIRQ_IRQSET_INTREQSET_MASK (0xFFFFFFFFU) #define MAILBOX_MBOXIRQ_IRQSET_INTREQSET_SHIFT (0U) #define MAILBOX_MBOXIRQ_IRQSET_INTREQSET(x) (((uint32_t)(((uint32_t)(x)) << MAILBOX_MBOXIRQ_IRQSET_INTREQSET_SHIFT)) & MAILBOX_MBOXIRQ_IRQSET_INTREQSET_MASK) +/*! @} */ /* The count of MAILBOX_MBOXIRQ_IRQSET */ #define MAILBOX_MBOXIRQ_IRQSET_COUNT (2U) /*! @name MBOXIRQ_IRQCLR - Clear bits in IRQ0 */ +/*! @{ */ #define MAILBOX_MBOXIRQ_IRQCLR_INTREQCLR_MASK (0xFFFFFFFFU) #define MAILBOX_MBOXIRQ_IRQCLR_INTREQCLR_SHIFT (0U) #define MAILBOX_MBOXIRQ_IRQCLR_INTREQCLR(x) (((uint32_t)(((uint32_t)(x)) << MAILBOX_MBOXIRQ_IRQCLR_INTREQCLR_SHIFT)) & MAILBOX_MBOXIRQ_IRQCLR_INTREQCLR_MASK) +/*! @} */ /* The count of MAILBOX_MBOXIRQ_IRQCLR */ #define MAILBOX_MBOXIRQ_IRQCLR_COUNT (2U) /*! @name MUTEX - Mutual exclusion register[1] */ +/*! @{ */ #define MAILBOX_MUTEX_EX_MASK (0x1U) #define MAILBOX_MUTEX_EX_SHIFT (0U) #define MAILBOX_MUTEX_EX(x) (((uint32_t)(((uint32_t)(x)) << MAILBOX_MUTEX_EX_SHIFT)) & MAILBOX_MUTEX_EX_MASK) +/*! @} */ /*! @@ -2839,36 +3131,43 @@ typedef struct { */ /*! @name CHANNEL_INTVAL - MRT Time interval value register. This value is loaded into the TIMER register. */ +/*! @{ */ #define MRT_CHANNEL_INTVAL_IVALUE_MASK (0xFFFFFFU) #define MRT_CHANNEL_INTVAL_IVALUE_SHIFT (0U) #define MRT_CHANNEL_INTVAL_IVALUE(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_INTVAL_IVALUE_SHIFT)) & MRT_CHANNEL_INTVAL_IVALUE_MASK) #define MRT_CHANNEL_INTVAL_LOAD_MASK (0x80000000U) #define MRT_CHANNEL_INTVAL_LOAD_SHIFT (31U) #define MRT_CHANNEL_INTVAL_LOAD(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_INTVAL_LOAD_SHIFT)) & MRT_CHANNEL_INTVAL_LOAD_MASK) +/*! @} */ /* The count of MRT_CHANNEL_INTVAL */ #define MRT_CHANNEL_INTVAL_COUNT (4U) /*! @name CHANNEL_TIMER - MRT Timer register. This register reads the value of the down-counter. */ +/*! @{ */ #define MRT_CHANNEL_TIMER_VALUE_MASK (0xFFFFFFU) #define MRT_CHANNEL_TIMER_VALUE_SHIFT (0U) #define MRT_CHANNEL_TIMER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_TIMER_VALUE_SHIFT)) & MRT_CHANNEL_TIMER_VALUE_MASK) +/*! @} */ /* The count of MRT_CHANNEL_TIMER */ #define MRT_CHANNEL_TIMER_COUNT (4U) /*! @name CHANNEL_CTRL - MRT Control register. This register controls the MRT modes. */ +/*! @{ */ #define MRT_CHANNEL_CTRL_INTEN_MASK (0x1U) #define MRT_CHANNEL_CTRL_INTEN_SHIFT (0U) #define MRT_CHANNEL_CTRL_INTEN(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_CTRL_INTEN_SHIFT)) & MRT_CHANNEL_CTRL_INTEN_MASK) #define MRT_CHANNEL_CTRL_MODE_MASK (0x6U) #define MRT_CHANNEL_CTRL_MODE_SHIFT (1U) #define MRT_CHANNEL_CTRL_MODE(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_CTRL_MODE_SHIFT)) & MRT_CHANNEL_CTRL_MODE_MASK) +/*! @} */ /* The count of MRT_CHANNEL_CTRL */ #define MRT_CHANNEL_CTRL_COUNT (4U) /*! @name CHANNEL_STAT - MRT Status register. */ +/*! @{ */ #define MRT_CHANNEL_STAT_INTFLAG_MASK (0x1U) #define MRT_CHANNEL_STAT_INTFLAG_SHIFT (0U) #define MRT_CHANNEL_STAT_INTFLAG(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_STAT_INTFLAG_SHIFT)) & MRT_CHANNEL_STAT_INTFLAG_MASK) @@ -2878,11 +3177,13 @@ typedef struct { #define MRT_CHANNEL_STAT_INUSE_MASK (0x4U) #define MRT_CHANNEL_STAT_INUSE_SHIFT (2U) #define MRT_CHANNEL_STAT_INUSE(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_STAT_INUSE_SHIFT)) & MRT_CHANNEL_STAT_INUSE_MASK) +/*! @} */ /* The count of MRT_CHANNEL_STAT */ #define MRT_CHANNEL_STAT_COUNT (4U) /*! @name MODCFG - Module Configuration register. This register provides information about this particular MRT instance, and allows choosing an overall mode for the idle channel feature. */ +/*! @{ */ #define MRT_MODCFG_NOC_MASK (0xFU) #define MRT_MODCFG_NOC_SHIFT (0U) #define MRT_MODCFG_NOC(x) (((uint32_t)(((uint32_t)(x)) << MRT_MODCFG_NOC_SHIFT)) & MRT_MODCFG_NOC_MASK) @@ -2892,13 +3193,17 @@ typedef struct { #define MRT_MODCFG_MULTITASK_MASK (0x80000000U) #define MRT_MODCFG_MULTITASK_SHIFT (31U) #define MRT_MODCFG_MULTITASK(x) (((uint32_t)(((uint32_t)(x)) << MRT_MODCFG_MULTITASK_SHIFT)) & MRT_MODCFG_MULTITASK_MASK) +/*! @} */ /*! @name IDLE_CH - Idle channel register. This register returns the number of the first idle channel. */ +/*! @{ */ #define MRT_IDLE_CH_CHAN_MASK (0xF0U) #define MRT_IDLE_CH_CHAN_SHIFT (4U) #define MRT_IDLE_CH_CHAN(x) (((uint32_t)(((uint32_t)(x)) << MRT_IDLE_CH_CHAN_SHIFT)) & MRT_IDLE_CH_CHAN_MASK) +/*! @} */ /*! @name IRQ_FLAG - Global interrupt flag register */ +/*! @{ */ #define MRT_IRQ_FLAG_GFLAG0_MASK (0x1U) #define MRT_IRQ_FLAG_GFLAG0_SHIFT (0U) #define MRT_IRQ_FLAG_GFLAG0(x) (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG0_SHIFT)) & MRT_IRQ_FLAG_GFLAG0_MASK) @@ -2911,6 +3216,7 @@ typedef struct { #define MRT_IRQ_FLAG_GFLAG3_MASK (0x8U) #define MRT_IRQ_FLAG_GFLAG3_SHIFT (3U) #define MRT_IRQ_FLAG_GFLAG3(x) (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG3_SHIFT)) & MRT_IRQ_FLAG_GFLAG3_MASK) +/*! @} */ /*! @@ -2971,56 +3277,77 @@ typedef struct { */ /*! @name ISEL - Pin Interrupt Mode register */ +/*! @{ */ #define PINT_ISEL_PMODE_MASK (0xFFU) #define PINT_ISEL_PMODE_SHIFT (0U) #define PINT_ISEL_PMODE(x) (((uint32_t)(((uint32_t)(x)) << PINT_ISEL_PMODE_SHIFT)) & PINT_ISEL_PMODE_MASK) +/*! @} */ /*! @name IENR - Pin interrupt level or rising edge interrupt enable register */ +/*! @{ */ #define PINT_IENR_ENRL_MASK (0xFFU) #define PINT_IENR_ENRL_SHIFT (0U) #define PINT_IENR_ENRL(x) (((uint32_t)(((uint32_t)(x)) << PINT_IENR_ENRL_SHIFT)) & PINT_IENR_ENRL_MASK) +/*! @} */ /*! @name SIENR - Pin interrupt level or rising edge interrupt set register */ +/*! @{ */ #define PINT_SIENR_SETENRL_MASK (0xFFU) #define PINT_SIENR_SETENRL_SHIFT (0U) #define PINT_SIENR_SETENRL(x) (((uint32_t)(((uint32_t)(x)) << PINT_SIENR_SETENRL_SHIFT)) & PINT_SIENR_SETENRL_MASK) +/*! @} */ /*! @name CIENR - Pin interrupt level (rising edge interrupt) clear register */ +/*! @{ */ #define PINT_CIENR_CENRL_MASK (0xFFU) #define PINT_CIENR_CENRL_SHIFT (0U) #define PINT_CIENR_CENRL(x) (((uint32_t)(((uint32_t)(x)) << PINT_CIENR_CENRL_SHIFT)) & PINT_CIENR_CENRL_MASK) +/*! @} */ /*! @name IENF - Pin interrupt active level or falling edge interrupt enable register */ +/*! @{ */ #define PINT_IENF_ENAF_MASK (0xFFU) #define PINT_IENF_ENAF_SHIFT (0U) #define PINT_IENF_ENAF(x) (((uint32_t)(((uint32_t)(x)) << PINT_IENF_ENAF_SHIFT)) & PINT_IENF_ENAF_MASK) +/*! @} */ /*! @name SIENF - Pin interrupt active level or falling edge interrupt set register */ +/*! @{ */ #define PINT_SIENF_SETENAF_MASK (0xFFU) #define PINT_SIENF_SETENAF_SHIFT (0U) #define PINT_SIENF_SETENAF(x) (((uint32_t)(((uint32_t)(x)) << PINT_SIENF_SETENAF_SHIFT)) & PINT_SIENF_SETENAF_MASK) +/*! @} */ /*! @name CIENF - Pin interrupt active level or falling edge interrupt clear register */ +/*! @{ */ #define PINT_CIENF_CENAF_MASK (0xFFU) #define PINT_CIENF_CENAF_SHIFT (0U) #define PINT_CIENF_CENAF(x) (((uint32_t)(((uint32_t)(x)) << PINT_CIENF_CENAF_SHIFT)) & PINT_CIENF_CENAF_MASK) +/*! @} */ /*! @name RISE - Pin interrupt rising edge register */ +/*! @{ */ #define PINT_RISE_RDET_MASK (0xFFU) #define PINT_RISE_RDET_SHIFT (0U) #define PINT_RISE_RDET(x) (((uint32_t)(((uint32_t)(x)) << PINT_RISE_RDET_SHIFT)) & PINT_RISE_RDET_MASK) +/*! @} */ /*! @name FALL - Pin interrupt falling edge register */ +/*! @{ */ #define PINT_FALL_FDET_MASK (0xFFU) #define PINT_FALL_FDET_SHIFT (0U) #define PINT_FALL_FDET(x) (((uint32_t)(((uint32_t)(x)) << PINT_FALL_FDET_SHIFT)) & PINT_FALL_FDET_MASK) +/*! @} */ /*! @name IST - Pin interrupt status register */ +/*! @{ */ #define PINT_IST_PSTAT_MASK (0xFFU) #define PINT_IST_PSTAT_SHIFT (0U) #define PINT_IST_PSTAT(x) (((uint32_t)(((uint32_t)(x)) << PINT_IST_PSTAT_SHIFT)) & PINT_IST_PSTAT_MASK) +/*! @} */ /*! @name PMCTRL - Pattern match interrupt control register */ +/*! @{ */ #define PINT_PMCTRL_SEL_PMATCH_MASK (0x1U) #define PINT_PMCTRL_SEL_PMATCH_SHIFT (0U) #define PINT_PMCTRL_SEL_PMATCH(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCTRL_SEL_PMATCH_SHIFT)) & PINT_PMCTRL_SEL_PMATCH_MASK) @@ -3030,8 +3357,10 @@ typedef struct { #define PINT_PMCTRL_PMAT_MASK (0xFF000000U) #define PINT_PMCTRL_PMAT_SHIFT (24U) #define PINT_PMCTRL_PMAT(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCTRL_PMAT_SHIFT)) & PINT_PMCTRL_PMAT_MASK) +/*! @} */ /*! @name PMSRC - Pattern match interrupt bit-slice source register */ +/*! @{ */ #define PINT_PMSRC_SRC0_MASK (0x700U) #define PINT_PMSRC_SRC0_SHIFT (8U) #define PINT_PMSRC_SRC0(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC0_SHIFT)) & PINT_PMSRC_SRC0_MASK) @@ -3056,8 +3385,10 @@ typedef struct { #define PINT_PMSRC_SRC7_MASK (0xE0000000U) #define PINT_PMSRC_SRC7_SHIFT (29U) #define PINT_PMSRC_SRC7(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC7_SHIFT)) & PINT_PMSRC_SRC7_MASK) +/*! @} */ /*! @name PMCFG - Pattern match interrupt bit slice configuration register */ +/*! @{ */ #define PINT_PMCFG_PROD_ENDPTS0_MASK (0x1U) #define PINT_PMCFG_PROD_ENDPTS0_SHIFT (0U) #define PINT_PMCFG_PROD_ENDPTS0(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS0_SHIFT)) & PINT_PMCFG_PROD_ENDPTS0_MASK) @@ -3103,6 +3434,7 @@ typedef struct { #define PINT_PMCFG_CFG7_MASK (0xE0000000U) #define PINT_PMCFG_CFG7_SHIFT (29U) #define PINT_PMCFG_CFG7(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG7_SHIFT)) & PINT_PMCFG_CFG7_MASK) +/*! @} */ /*! @@ -3154,6 +3486,7 @@ typedef struct { */ /*! @name CTRL - RTC control register */ +/*! @{ */ #define RTC_CTRL_SWRESET_MASK (0x1U) #define RTC_CTRL_SWRESET_SHIFT (0U) #define RTC_CTRL_SWRESET(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_SWRESET_SHIFT)) & RTC_CTRL_SWRESET_MASK) @@ -3181,21 +3514,28 @@ typedef struct { #define RTC_CTRL_RTC_OSC_BYPASS_MASK (0x200U) #define RTC_CTRL_RTC_OSC_BYPASS_SHIFT (9U) #define RTC_CTRL_RTC_OSC_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_RTC_OSC_BYPASS_SHIFT)) & RTC_CTRL_RTC_OSC_BYPASS_MASK) +/*! @} */ /*! @name MATCH - RTC match register */ +/*! @{ */ #define RTC_MATCH_MATVAL_MASK (0xFFFFFFFFU) #define RTC_MATCH_MATVAL_SHIFT (0U) #define RTC_MATCH_MATVAL(x) (((uint32_t)(((uint32_t)(x)) << RTC_MATCH_MATVAL_SHIFT)) & RTC_MATCH_MATVAL_MASK) +/*! @} */ /*! @name COUNT - RTC counter register */ +/*! @{ */ #define RTC_COUNT_VAL_MASK (0xFFFFFFFFU) #define RTC_COUNT_VAL_SHIFT (0U) #define RTC_COUNT_VAL(x) (((uint32_t)(((uint32_t)(x)) << RTC_COUNT_VAL_SHIFT)) & RTC_COUNT_VAL_MASK) +/*! @} */ /*! @name WAKE - High-resolution/wake-up timer control register */ +/*! @{ */ #define RTC_WAKE_VAL_MASK (0xFFFFU) #define RTC_WAKE_VAL_SHIFT (0U) #define RTC_WAKE_VAL(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAKE_VAL_SHIFT)) & RTC_WAKE_VAL_MASK) +/*! @} */ /*! @@ -3272,7 +3612,7 @@ typedef struct { __IO uint32_t CLR; /**< SCT output 0 clear register, array offset: 0x504, array step: 0x8 */ } OUT[8]; uint8_t RESERVED_5[700]; - __IO uint32_t MODULECONTENT; /**< Reserved, offset: 0x7FC */ + uint32_t MODULECONTENT; /**< Reserved, offset: 0x7FC */ } SCT_Type; /* ---------------------------------------------------------------------------- @@ -3285,6 +3625,7 @@ typedef struct { */ /*! @name CONFIG - SCT configuration register */ +/*! @{ */ #define SCT_CONFIG_UNIFY_MASK (0x1U) #define SCT_CONFIG_UNIFY_SHIFT (0U) #define SCT_CONFIG_UNIFY(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_UNIFY_SHIFT)) & SCT_CONFIG_UNIFY_MASK) @@ -3309,8 +3650,10 @@ typedef struct { #define SCT_CONFIG_AUTOLIMIT_H_MASK (0x40000U) #define SCT_CONFIG_AUTOLIMIT_H_SHIFT (18U) #define SCT_CONFIG_AUTOLIMIT_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_AUTOLIMIT_H_SHIFT)) & SCT_CONFIG_AUTOLIMIT_H_MASK) +/*! @} */ /*! @name CTRL - SCT control register */ +/*! @{ */ #define SCT_CTRL_DOWN_L_MASK (0x1U) #define SCT_CTRL_DOWN_L_SHIFT (0U) #define SCT_CTRL_DOWN_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_DOWN_L_SHIFT)) & SCT_CTRL_DOWN_L_MASK) @@ -3347,56 +3690,70 @@ typedef struct { #define SCT_CTRL_PRE_H_MASK (0x1FE00000U) #define SCT_CTRL_PRE_H_SHIFT (21U) #define SCT_CTRL_PRE_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_PRE_H_SHIFT)) & SCT_CTRL_PRE_H_MASK) +/*! @} */ /*! @name LIMIT - SCT limit event select register */ +/*! @{ */ #define SCT_LIMIT_LIMMSK_L_MASK (0xFFFFU) #define SCT_LIMIT_LIMMSK_L_SHIFT (0U) #define SCT_LIMIT_LIMMSK_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_LIMIT_LIMMSK_L_SHIFT)) & SCT_LIMIT_LIMMSK_L_MASK) #define SCT_LIMIT_LIMMSK_H_MASK (0xFFFF0000U) #define SCT_LIMIT_LIMMSK_H_SHIFT (16U) #define SCT_LIMIT_LIMMSK_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_LIMIT_LIMMSK_H_SHIFT)) & SCT_LIMIT_LIMMSK_H_MASK) +/*! @} */ /*! @name HALT - SCT halt event select register */ +/*! @{ */ #define SCT_HALT_HALTMSK_L_MASK (0xFFFFU) #define SCT_HALT_HALTMSK_L_SHIFT (0U) #define SCT_HALT_HALTMSK_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_HALT_HALTMSK_L_SHIFT)) & SCT_HALT_HALTMSK_L_MASK) #define SCT_HALT_HALTMSK_H_MASK (0xFFFF0000U) #define SCT_HALT_HALTMSK_H_SHIFT (16U) #define SCT_HALT_HALTMSK_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_HALT_HALTMSK_H_SHIFT)) & SCT_HALT_HALTMSK_H_MASK) +/*! @} */ /*! @name STOP - SCT stop event select register */ +/*! @{ */ #define SCT_STOP_STOPMSK_L_MASK (0xFFFFU) #define SCT_STOP_STOPMSK_L_SHIFT (0U) #define SCT_STOP_STOPMSK_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_STOP_STOPMSK_L_SHIFT)) & SCT_STOP_STOPMSK_L_MASK) #define SCT_STOP_STOPMSK_H_MASK (0xFFFF0000U) #define SCT_STOP_STOPMSK_H_SHIFT (16U) #define SCT_STOP_STOPMSK_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_STOP_STOPMSK_H_SHIFT)) & SCT_STOP_STOPMSK_H_MASK) +/*! @} */ /*! @name START - SCT start event select register */ +/*! @{ */ #define SCT_START_STARTMSK_L_MASK (0xFFFFU) #define SCT_START_STARTMSK_L_SHIFT (0U) #define SCT_START_STARTMSK_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_START_STARTMSK_L_SHIFT)) & SCT_START_STARTMSK_L_MASK) #define SCT_START_STARTMSK_H_MASK (0xFFFF0000U) #define SCT_START_STARTMSK_H_SHIFT (16U) #define SCT_START_STARTMSK_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_START_STARTMSK_H_SHIFT)) & SCT_START_STARTMSK_H_MASK) +/*! @} */ /*! @name COUNT - SCT counter register */ +/*! @{ */ #define SCT_COUNT_CTR_L_MASK (0xFFFFU) #define SCT_COUNT_CTR_L_SHIFT (0U) #define SCT_COUNT_CTR_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_COUNT_CTR_L_SHIFT)) & SCT_COUNT_CTR_L_MASK) #define SCT_COUNT_CTR_H_MASK (0xFFFF0000U) #define SCT_COUNT_CTR_H_SHIFT (16U) #define SCT_COUNT_CTR_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_COUNT_CTR_H_SHIFT)) & SCT_COUNT_CTR_H_MASK) +/*! @} */ /*! @name STATE - SCT state register */ +/*! @{ */ #define SCT_STATE_STATE_L_MASK (0x1FU) #define SCT_STATE_STATE_L_SHIFT (0U) #define SCT_STATE_STATE_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_STATE_STATE_L_SHIFT)) & SCT_STATE_STATE_L_MASK) #define SCT_STATE_STATE_H_MASK (0x1F0000U) #define SCT_STATE_STATE_H_SHIFT (16U) #define SCT_STATE_STATE_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_STATE_STATE_H_SHIFT)) & SCT_STATE_STATE_H_MASK) +/*! @} */ /*! @name INPUT - SCT input register */ +/*! @{ */ #define SCT_INPUT_AIN0_MASK (0x1U) #define SCT_INPUT_AIN0_SHIFT (0U) #define SCT_INPUT_AIN0(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN0_SHIFT)) & SCT_INPUT_AIN0_MASK) @@ -3493,21 +3850,27 @@ typedef struct { #define SCT_INPUT_SIN15_MASK (0x80000000U) #define SCT_INPUT_SIN15_SHIFT (31U) #define SCT_INPUT_SIN15(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN15_SHIFT)) & SCT_INPUT_SIN15_MASK) +/*! @} */ /*! @name REGMODE - SCT match/capture mode register */ +/*! @{ */ #define SCT_REGMODE_REGMOD_L_MASK (0xFFFFU) #define SCT_REGMODE_REGMOD_L_SHIFT (0U) #define SCT_REGMODE_REGMOD_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_L_SHIFT)) & SCT_REGMODE_REGMOD_L_MASK) #define SCT_REGMODE_REGMOD_H_MASK (0xFFFF0000U) #define SCT_REGMODE_REGMOD_H_SHIFT (16U) #define SCT_REGMODE_REGMOD_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_H_SHIFT)) & SCT_REGMODE_REGMOD_H_MASK) +/*! @} */ /*! @name OUTPUT - SCT output register */ +/*! @{ */ #define SCT_OUTPUT_OUT_MASK (0xFFFFU) #define SCT_OUTPUT_OUT_SHIFT (0U) #define SCT_OUTPUT_OUT(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUT_OUT_SHIFT)) & SCT_OUTPUT_OUT_MASK) +/*! @} */ /*! @name OUTPUTDIRCTRL - SCT output counter direction control register */ +/*! @{ */ #define SCT_OUTPUTDIRCTRL_SETCLR0_MASK (0x3U) #define SCT_OUTPUTDIRCTRL_SETCLR0_SHIFT (0U) #define SCT_OUTPUTDIRCTRL_SETCLR0(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR0_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR0_MASK) @@ -3556,8 +3919,10 @@ typedef struct { #define SCT_OUTPUTDIRCTRL_SETCLR15_MASK (0xC0000000U) #define SCT_OUTPUTDIRCTRL_SETCLR15_SHIFT (30U) #define SCT_OUTPUTDIRCTRL_SETCLR15(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR15_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR15_MASK) +/*! @} */ /*! @name RES - SCT conflict resolution register */ +/*! @{ */ #define SCT_RES_O0RES_MASK (0x3U) #define SCT_RES_O0RES_SHIFT (0U) #define SCT_RES_O0RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O0RES_SHIFT)) & SCT_RES_O0RES_MASK) @@ -3606,8 +3971,10 @@ typedef struct { #define SCT_RES_O15RES_MASK (0xC0000000U) #define SCT_RES_O15RES_SHIFT (30U) #define SCT_RES_O15RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O15RES_SHIFT)) & SCT_RES_O15RES_MASK) +/*! @} */ /*! @name DMA0REQUEST - SCT DMA request 0 register */ +/*! @{ */ #define SCT_DMA0REQUEST_DEV_0_MASK (0xFFFFU) #define SCT_DMA0REQUEST_DEV_0_SHIFT (0U) #define SCT_DMA0REQUEST_DEV_0(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMA0REQUEST_DEV_0_SHIFT)) & SCT_DMA0REQUEST_DEV_0_MASK) @@ -3617,8 +3984,10 @@ typedef struct { #define SCT_DMA0REQUEST_DRQ0_MASK (0x80000000U) #define SCT_DMA0REQUEST_DRQ0_SHIFT (31U) #define SCT_DMA0REQUEST_DRQ0(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMA0REQUEST_DRQ0_SHIFT)) & SCT_DMA0REQUEST_DRQ0_MASK) +/*! @} */ /*! @name DMA1REQUEST - SCT DMA request 1 register */ +/*! @{ */ #define SCT_DMA1REQUEST_DEV_1_MASK (0xFFFFU) #define SCT_DMA1REQUEST_DEV_1_SHIFT (0U) #define SCT_DMA1REQUEST_DEV_1(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMA1REQUEST_DEV_1_SHIFT)) & SCT_DMA1REQUEST_DEV_1_MASK) @@ -3628,23 +3997,31 @@ typedef struct { #define SCT_DMA1REQUEST_DRQ1_MASK (0x80000000U) #define SCT_DMA1REQUEST_DRQ1_SHIFT (31U) #define SCT_DMA1REQUEST_DRQ1(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMA1REQUEST_DRQ1_SHIFT)) & SCT_DMA1REQUEST_DRQ1_MASK) +/*! @} */ /*! @name EVEN - SCT event interrupt enable register */ +/*! @{ */ #define SCT_EVEN_IEN_MASK (0xFFFFU) #define SCT_EVEN_IEN_SHIFT (0U) #define SCT_EVEN_IEN(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVEN_IEN_SHIFT)) & SCT_EVEN_IEN_MASK) +/*! @} */ /*! @name EVFLAG - SCT event flag register */ +/*! @{ */ #define SCT_EVFLAG_FLAG_MASK (0xFFFFU) #define SCT_EVFLAG_FLAG_SHIFT (0U) #define SCT_EVFLAG_FLAG(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVFLAG_FLAG_SHIFT)) & SCT_EVFLAG_FLAG_MASK) +/*! @} */ /*! @name CONEN - SCT conflict interrupt enable register */ +/*! @{ */ #define SCT_CONEN_NCEN_MASK (0xFFFFU) #define SCT_CONEN_NCEN_SHIFT (0U) #define SCT_CONEN_NCEN(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONEN_NCEN_SHIFT)) & SCT_CONEN_NCEN_MASK) +/*! @} */ /*! @name CONFLAG - SCT conflict flag register */ +/*! @{ */ #define SCT_CONFLAG_NCFLAG_MASK (0xFFFFU) #define SCT_CONFLAG_NCFLAG_SHIFT (0U) #define SCT_CONFLAG_NCFLAG(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_NCFLAG_SHIFT)) & SCT_CONFLAG_NCFLAG_MASK) @@ -3654,60 +4031,72 @@ typedef struct { #define SCT_CONFLAG_BUSERRH_MASK (0x80000000U) #define SCT_CONFLAG_BUSERRH_SHIFT (31U) #define SCT_CONFLAG_BUSERRH(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_BUSERRH_SHIFT)) & SCT_CONFLAG_BUSERRH_MASK) +/*! @} */ /*! @name SCTCAP - SCT capture register of capture channel */ +/*! @{ */ #define SCT_SCTCAP_CAPn_L_MASK (0xFFFFU) #define SCT_SCTCAP_CAPn_L_SHIFT (0U) #define SCT_SCTCAP_CAPn_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_SCTCAP_CAPn_L_SHIFT)) & SCT_SCTCAP_CAPn_L_MASK) #define SCT_SCTCAP_CAPn_H_MASK (0xFFFF0000U) #define SCT_SCTCAP_CAPn_H_SHIFT (16U) #define SCT_SCTCAP_CAPn_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_SCTCAP_CAPn_H_SHIFT)) & SCT_SCTCAP_CAPn_H_MASK) +/*! @} */ /* The count of SCT_SCTCAP */ #define SCT_SCTCAP_COUNT (10U) /*! @name SCTMATCH - SCT match value register of match channels */ +/*! @{ */ #define SCT_SCTMATCH_MATCHn_L_MASK (0xFFFFU) #define SCT_SCTMATCH_MATCHn_L_SHIFT (0U) #define SCT_SCTMATCH_MATCHn_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_SCTMATCH_MATCHn_L_SHIFT)) & SCT_SCTMATCH_MATCHn_L_MASK) #define SCT_SCTMATCH_MATCHn_H_MASK (0xFFFF0000U) #define SCT_SCTMATCH_MATCHn_H_SHIFT (16U) #define SCT_SCTMATCH_MATCHn_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_SCTMATCH_MATCHn_H_SHIFT)) & SCT_SCTMATCH_MATCHn_H_MASK) +/*! @} */ /* The count of SCT_SCTMATCH */ #define SCT_SCTMATCH_COUNT (10U) /*! @name SCTCAPCTRL - SCT capture control register */ +/*! @{ */ #define SCT_SCTCAPCTRL_CAPCONn_L_MASK (0xFFFFU) #define SCT_SCTCAPCTRL_CAPCONn_L_SHIFT (0U) #define SCT_SCTCAPCTRL_CAPCONn_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_SCTCAPCTRL_CAPCONn_L_SHIFT)) & SCT_SCTCAPCTRL_CAPCONn_L_MASK) #define SCT_SCTCAPCTRL_CAPCONn_H_MASK (0xFFFF0000U) #define SCT_SCTCAPCTRL_CAPCONn_H_SHIFT (16U) #define SCT_SCTCAPCTRL_CAPCONn_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_SCTCAPCTRL_CAPCONn_H_SHIFT)) & SCT_SCTCAPCTRL_CAPCONn_H_MASK) +/*! @} */ /* The count of SCT_SCTCAPCTRL */ #define SCT_SCTCAPCTRL_COUNT (10U) /*! @name SCTMATCHREL - SCT match reload value register */ +/*! @{ */ #define SCT_SCTMATCHREL_RELOADn_L_MASK (0xFFFFU) #define SCT_SCTMATCHREL_RELOADn_L_SHIFT (0U) #define SCT_SCTMATCHREL_RELOADn_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_SCTMATCHREL_RELOADn_L_SHIFT)) & SCT_SCTMATCHREL_RELOADn_L_MASK) #define SCT_SCTMATCHREL_RELOADn_H_MASK (0xFFFF0000U) #define SCT_SCTMATCHREL_RELOADn_H_SHIFT (16U) #define SCT_SCTMATCHREL_RELOADn_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_SCTMATCHREL_RELOADn_H_SHIFT)) & SCT_SCTMATCHREL_RELOADn_H_MASK) +/*! @} */ /* The count of SCT_SCTMATCHREL */ #define SCT_SCTMATCHREL_COUNT (10U) /*! @name EVENT_STATE - SCT event state register 0 */ +/*! @{ */ #define SCT_EVENT_STATE_STATEMSKn_MASK (0xFFFFU) #define SCT_EVENT_STATE_STATEMSKn_SHIFT (0U) #define SCT_EVENT_STATE_STATEMSKn(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_STATE_STATEMSKn_SHIFT)) & SCT_EVENT_STATE_STATEMSKn_MASK) +/*! @} */ /* The count of SCT_EVENT_STATE */ #define SCT_EVENT_STATE_COUNT (10U) /*! @name EVENT_CTRL - SCT event control register 0 */ +/*! @{ */ #define SCT_EVENT_CTRL_MATCHSEL_MASK (0xFU) #define SCT_EVENT_CTRL_MATCHSEL_SHIFT (0U) #define SCT_EVENT_CTRL_MATCHSEL(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_MATCHSEL_SHIFT)) & SCT_EVENT_CTRL_MATCHSEL_MASK) @@ -3738,22 +4127,27 @@ typedef struct { #define SCT_EVENT_CTRL_DIRECTION_MASK (0x600000U) #define SCT_EVENT_CTRL_DIRECTION_SHIFT (21U) #define SCT_EVENT_CTRL_DIRECTION(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_DIRECTION_SHIFT)) & SCT_EVENT_CTRL_DIRECTION_MASK) +/*! @} */ /* The count of SCT_EVENT_CTRL */ #define SCT_EVENT_CTRL_COUNT (10U) /*! @name OUT_SET - SCT output 0 set register */ +/*! @{ */ #define SCT_OUT_SET_SET_MASK (0xFFFFU) #define SCT_OUT_SET_SET_SHIFT (0U) #define SCT_OUT_SET_SET(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUT_SET_SET_SHIFT)) & SCT_OUT_SET_SET_MASK) +/*! @} */ /* The count of SCT_OUT_SET */ #define SCT_OUT_SET_COUNT (8U) /*! @name OUT_CLR - SCT output 0 clear register */ +/*! @{ */ #define SCT_OUT_CLR_CLR_MASK (0xFFFFU) #define SCT_OUT_CLR_CLR_SHIFT (0U) #define SCT_OUT_CLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUT_CLR_CLR_SHIFT)) & SCT_OUT_CLR_CLR_MASK) +/*! @} */ /* The count of SCT_OUT_CLR */ #define SCT_OUT_CLR_COUNT (8U) @@ -3827,6 +4221,7 @@ typedef struct { */ /*! @name CFG - SPI Configuration register */ +/*! @{ */ #define SPI_CFG_ENABLE_MASK (0x1U) #define SPI_CFG_ENABLE_SHIFT (0U) #define SPI_CFG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_ENABLE_SHIFT)) & SPI_CFG_ENABLE_MASK) @@ -3857,8 +4252,10 @@ typedef struct { #define SPI_CFG_SPOL3_MASK (0x800U) #define SPI_CFG_SPOL3_SHIFT (11U) #define SPI_CFG_SPOL3(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL3_SHIFT)) & SPI_CFG_SPOL3_MASK) +/*! @} */ /*! @name DLY - SPI Delay register */ +/*! @{ */ #define SPI_DLY_PRE_DELAY_MASK (0xFU) #define SPI_DLY_PRE_DELAY_SHIFT (0U) #define SPI_DLY_PRE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SPI_DLY_PRE_DELAY_SHIFT)) & SPI_DLY_PRE_DELAY_MASK) @@ -3871,8 +4268,10 @@ typedef struct { #define SPI_DLY_TRANSFER_DELAY_MASK (0xF000U) #define SPI_DLY_TRANSFER_DELAY_SHIFT (12U) #define SPI_DLY_TRANSFER_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SPI_DLY_TRANSFER_DELAY_SHIFT)) & SPI_DLY_TRANSFER_DELAY_MASK) +/*! @} */ /*! @name STAT - SPI Status. Some status flags can be cleared by writing a 1 to that bit position. */ +/*! @{ */ #define SPI_STAT_SSA_MASK (0x10U) #define SPI_STAT_SSA_SHIFT (4U) #define SPI_STAT_SSA(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_SSA_SHIFT)) & SPI_STAT_SSA_MASK) @@ -3888,8 +4287,10 @@ typedef struct { #define SPI_STAT_MSTIDLE_MASK (0x100U) #define SPI_STAT_MSTIDLE_SHIFT (8U) #define SPI_STAT_MSTIDLE(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_MSTIDLE_SHIFT)) & SPI_STAT_MSTIDLE_MASK) +/*! @} */ /*! @name INTENSET - SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set. */ +/*! @{ */ #define SPI_INTENSET_SSAEN_MASK (0x10U) #define SPI_INTENSET_SSAEN_SHIFT (4U) #define SPI_INTENSET_SSAEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENSET_SSAEN_SHIFT)) & SPI_INTENSET_SSAEN_MASK) @@ -3899,8 +4300,10 @@ typedef struct { #define SPI_INTENSET_MSTIDLEEN_MASK (0x100U) #define SPI_INTENSET_MSTIDLEEN_SHIFT (8U) #define SPI_INTENSET_MSTIDLEEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENSET_MSTIDLEEN_SHIFT)) & SPI_INTENSET_MSTIDLEEN_MASK) +/*! @} */ /*! @name INTENCLR - SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared. */ +/*! @{ */ #define SPI_INTENCLR_SSAEN_MASK (0x10U) #define SPI_INTENCLR_SSAEN_SHIFT (4U) #define SPI_INTENCLR_SSAEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENCLR_SSAEN_SHIFT)) & SPI_INTENCLR_SSAEN_MASK) @@ -3910,13 +4313,17 @@ typedef struct { #define SPI_INTENCLR_MSTIDLE_MASK (0x100U) #define SPI_INTENCLR_MSTIDLE_SHIFT (8U) #define SPI_INTENCLR_MSTIDLE(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENCLR_MSTIDLE_SHIFT)) & SPI_INTENCLR_MSTIDLE_MASK) +/*! @} */ /*! @name DIV - SPI clock Divider */ +/*! @{ */ #define SPI_DIV_DIVVAL_MASK (0xFFFFU) #define SPI_DIV_DIVVAL_SHIFT (0U) #define SPI_DIV_DIVVAL(x) (((uint32_t)(((uint32_t)(x)) << SPI_DIV_DIVVAL_SHIFT)) & SPI_DIV_DIVVAL_MASK) +/*! @} */ /*! @name INTSTAT - SPI Interrupt Status */ +/*! @{ */ #define SPI_INTSTAT_SSA_MASK (0x10U) #define SPI_INTSTAT_SSA_SHIFT (4U) #define SPI_INTSTAT_SSA(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTSTAT_SSA_SHIFT)) & SPI_INTSTAT_SSA_MASK) @@ -3926,8 +4333,10 @@ typedef struct { #define SPI_INTSTAT_MSTIDLE_MASK (0x100U) #define SPI_INTSTAT_MSTIDLE_SHIFT (8U) #define SPI_INTSTAT_MSTIDLE(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTSTAT_MSTIDLE_SHIFT)) & SPI_INTSTAT_MSTIDLE_MASK) +/*! @} */ /*! @name FIFOCFG - FIFO configuration and enable register. */ +/*! @{ */ #define SPI_FIFOCFG_ENABLETX_MASK (0x1U) #define SPI_FIFOCFG_ENABLETX_SHIFT (0U) #define SPI_FIFOCFG_ENABLETX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_ENABLETX_SHIFT)) & SPI_FIFOCFG_ENABLETX_MASK) @@ -3955,8 +4364,10 @@ typedef struct { #define SPI_FIFOCFG_EMPTYRX_MASK (0x20000U) #define SPI_FIFOCFG_EMPTYRX_SHIFT (17U) #define SPI_FIFOCFG_EMPTYRX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_EMPTYRX_SHIFT)) & SPI_FIFOCFG_EMPTYRX_MASK) +/*! @} */ /*! @name FIFOSTAT - FIFO status register. */ +/*! @{ */ #define SPI_FIFOSTAT_TXERR_MASK (0x1U) #define SPI_FIFOSTAT_TXERR_SHIFT (0U) #define SPI_FIFOSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_TXERR_SHIFT)) & SPI_FIFOSTAT_TXERR_MASK) @@ -3984,8 +4395,10 @@ typedef struct { #define SPI_FIFOSTAT_RXLVL_MASK (0x1F0000U) #define SPI_FIFOSTAT_RXLVL_SHIFT (16U) #define SPI_FIFOSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_RXLVL_SHIFT)) & SPI_FIFOSTAT_RXLVL_MASK) +/*! @} */ /*! @name FIFOTRIG - FIFO trigger settings for interrupt and DMA request. */ +/*! @{ */ #define SPI_FIFOTRIG_TXLVLENA_MASK (0x1U) #define SPI_FIFOTRIG_TXLVLENA_SHIFT (0U) #define SPI_FIFOTRIG_TXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOTRIG_TXLVLENA_SHIFT)) & SPI_FIFOTRIG_TXLVLENA_MASK) @@ -3998,8 +4411,10 @@ typedef struct { #define SPI_FIFOTRIG_RXLVL_MASK (0xF0000U) #define SPI_FIFOTRIG_RXLVL_SHIFT (16U) #define SPI_FIFOTRIG_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOTRIG_RXLVL_SHIFT)) & SPI_FIFOTRIG_RXLVL_MASK) +/*! @} */ /*! @name FIFOINTENSET - FIFO interrupt enable set (enable) and read register. */ +/*! @{ */ #define SPI_FIFOINTENSET_TXERR_MASK (0x1U) #define SPI_FIFOINTENSET_TXERR_SHIFT (0U) #define SPI_FIFOINTENSET_TXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENSET_TXERR_SHIFT)) & SPI_FIFOINTENSET_TXERR_MASK) @@ -4012,8 +4427,10 @@ typedef struct { #define SPI_FIFOINTENSET_RXLVL_MASK (0x8U) #define SPI_FIFOINTENSET_RXLVL_SHIFT (3U) #define SPI_FIFOINTENSET_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENSET_RXLVL_SHIFT)) & SPI_FIFOINTENSET_RXLVL_MASK) +/*! @} */ /*! @name FIFOINTENCLR - FIFO interrupt enable clear (disable) and read register. */ +/*! @{ */ #define SPI_FIFOINTENCLR_TXERR_MASK (0x1U) #define SPI_FIFOINTENCLR_TXERR_SHIFT (0U) #define SPI_FIFOINTENCLR_TXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENCLR_TXERR_SHIFT)) & SPI_FIFOINTENCLR_TXERR_MASK) @@ -4026,8 +4443,10 @@ typedef struct { #define SPI_FIFOINTENCLR_RXLVL_MASK (0x8U) #define SPI_FIFOINTENCLR_RXLVL_SHIFT (3U) #define SPI_FIFOINTENCLR_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENCLR_RXLVL_SHIFT)) & SPI_FIFOINTENCLR_RXLVL_MASK) +/*! @} */ /*! @name FIFOINTSTAT - FIFO interrupt status register. */ +/*! @{ */ #define SPI_FIFOINTSTAT_TXERR_MASK (0x1U) #define SPI_FIFOINTSTAT_TXERR_SHIFT (0U) #define SPI_FIFOINTSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_TXERR_SHIFT)) & SPI_FIFOINTSTAT_TXERR_MASK) @@ -4043,8 +4462,10 @@ typedef struct { #define SPI_FIFOINTSTAT_PERINT_MASK (0x10U) #define SPI_FIFOINTSTAT_PERINT_SHIFT (4U) #define SPI_FIFOINTSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_PERINT_SHIFT)) & SPI_FIFOINTSTAT_PERINT_MASK) +/*! @} */ /*! @name FIFOWR - FIFO write data. */ +/*! @{ */ #define SPI_FIFOWR_TXDATA_MASK (0xFFFFU) #define SPI_FIFOWR_TXDATA_SHIFT (0U) #define SPI_FIFOWR_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXDATA_SHIFT)) & SPI_FIFOWR_TXDATA_MASK) @@ -4072,8 +4493,10 @@ typedef struct { #define SPI_FIFOWR_LEN_MASK (0xF000000U) #define SPI_FIFOWR_LEN_SHIFT (24U) #define SPI_FIFOWR_LEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_LEN_SHIFT)) & SPI_FIFOWR_LEN_MASK) +/*! @} */ /*! @name FIFORD - FIFO read data. */ +/*! @{ */ #define SPI_FIFORD_RXDATA_MASK (0xFFFFU) #define SPI_FIFORD_RXDATA_SHIFT (0U) #define SPI_FIFORD_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXDATA_SHIFT)) & SPI_FIFORD_RXDATA_MASK) @@ -4092,8 +4515,10 @@ typedef struct { #define SPI_FIFORD_SOT_MASK (0x100000U) #define SPI_FIFORD_SOT_SHIFT (20U) #define SPI_FIFORD_SOT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_SOT_SHIFT)) & SPI_FIFORD_SOT_MASK) +/*! @} */ /*! @name FIFORDNOPOP - FIFO data read with no FIFO pop. */ +/*! @{ */ #define SPI_FIFORDNOPOP_RXDATA_MASK (0xFFFFU) #define SPI_FIFORDNOPOP_RXDATA_SHIFT (0U) #define SPI_FIFORDNOPOP_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXDATA_SHIFT)) & SPI_FIFORDNOPOP_RXDATA_MASK) @@ -4112,6 +4537,7 @@ typedef struct { #define SPI_FIFORDNOPOP_SOT_MASK (0x100000U) #define SPI_FIFORDNOPOP_SOT_SHIFT (20U) #define SPI_FIFORDNOPOP_SOT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_SOT_SHIFT)) & SPI_FIFORDNOPOP_SOT_MASK) +/*! @} */ /*! @@ -4195,6 +4621,7 @@ typedef struct { */ /*! @name CTRL - SPIFI control register */ +/*! @{ */ #define SPIFI_CTRL_TIMEOUT_MASK (0xFFFFU) #define SPIFI_CTRL_TIMEOUT_SHIFT (0U) #define SPIFI_CTRL_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CTRL_TIMEOUT_SHIFT)) & SPIFI_CTRL_TIMEOUT_MASK) @@ -4225,8 +4652,10 @@ typedef struct { #define SPIFI_CTRL_DMAEN_MASK (0x80000000U) #define SPIFI_CTRL_DMAEN_SHIFT (31U) #define SPIFI_CTRL_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CTRL_DMAEN_SHIFT)) & SPIFI_CTRL_DMAEN_MASK) +/*! @} */ /*! @name CMD - SPIFI command register */ +/*! @{ */ #define SPIFI_CMD_DATALEN_MASK (0x3FFFU) #define SPIFI_CMD_DATALEN_SHIFT (0U) #define SPIFI_CMD_DATALEN(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CMD_DATALEN_SHIFT)) & SPIFI_CMD_DATALEN_MASK) @@ -4248,28 +4677,38 @@ typedef struct { #define SPIFI_CMD_OPCODE_MASK (0xFF000000U) #define SPIFI_CMD_OPCODE_SHIFT (24U) #define SPIFI_CMD_OPCODE(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CMD_OPCODE_SHIFT)) & SPIFI_CMD_OPCODE_MASK) +/*! @} */ /*! @name ADDR - SPIFI address register */ +/*! @{ */ #define SPIFI_ADDR_ADDRESS_MASK (0xFFFFFFFFU) #define SPIFI_ADDR_ADDRESS_SHIFT (0U) #define SPIFI_ADDR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_ADDR_ADDRESS_SHIFT)) & SPIFI_ADDR_ADDRESS_MASK) +/*! @} */ /*! @name IDATA - SPIFI intermediate data register */ +/*! @{ */ #define SPIFI_IDATA_IDATA_MASK (0xFFFFFFFFU) #define SPIFI_IDATA_IDATA_SHIFT (0U) #define SPIFI_IDATA_IDATA(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_IDATA_IDATA_SHIFT)) & SPIFI_IDATA_IDATA_MASK) +/*! @} */ /*! @name CLIMIT - SPIFI limit register */ +/*! @{ */ #define SPIFI_CLIMIT_CLIMIT_MASK (0xFFFFFFFFU) #define SPIFI_CLIMIT_CLIMIT_SHIFT (0U) #define SPIFI_CLIMIT_CLIMIT(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CLIMIT_CLIMIT_SHIFT)) & SPIFI_CLIMIT_CLIMIT_MASK) +/*! @} */ /*! @name DATA - SPIFI data register */ +/*! @{ */ #define SPIFI_DATA_DATA_MASK (0xFFFFFFFFU) #define SPIFI_DATA_DATA_SHIFT (0U) #define SPIFI_DATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_DATA_DATA_SHIFT)) & SPIFI_DATA_DATA_MASK) +/*! @} */ /*! @name MCMD - SPIFI memory command register */ +/*! @{ */ #define SPIFI_MCMD_POLL_MASK (0x4000U) #define SPIFI_MCMD_POLL_SHIFT (14U) #define SPIFI_MCMD_POLL(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_MCMD_POLL_SHIFT)) & SPIFI_MCMD_POLL_MASK) @@ -4288,8 +4727,10 @@ typedef struct { #define SPIFI_MCMD_OPCODE_MASK (0xFF000000U) #define SPIFI_MCMD_OPCODE_SHIFT (24U) #define SPIFI_MCMD_OPCODE(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_MCMD_OPCODE_SHIFT)) & SPIFI_MCMD_OPCODE_MASK) +/*! @} */ /*! @name STAT - SPIFI status register */ +/*! @{ */ #define SPIFI_STAT_MCINIT_MASK (0x1U) #define SPIFI_STAT_MCINIT_SHIFT (0U) #define SPIFI_STAT_MCINIT(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_STAT_MCINIT_SHIFT)) & SPIFI_STAT_MCINIT_MASK) @@ -4305,6 +4746,7 @@ typedef struct { #define SPIFI_STAT_VERSION_MASK (0xFF000000U) #define SPIFI_STAT_VERSION_SHIFT (24U) #define SPIFI_STAT_VERSION(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_STAT_VERSION_SHIFT)) & SPIFI_STAT_VERSION_MASK) +/*! @} */ /*! @@ -4338,7 +4780,7 @@ typedef struct { /** SYSCON - Register Layout Typedef */ typedef struct { - __IO uint32_t SYSMEMREMAP; /**< System Remap register, offset: 0x0 */ + uint32_t SYSMEMREMAP; /**< System Remap register, offset: 0x0 */ uint8_t RESERVED_0[12]; __IO uint32_t AHBMATPRIO; /**< AHB multilayer matrix priority control, offset: 0x10 */ uint8_t RESERVED_1[44]; @@ -4434,7 +4876,7 @@ typedef struct { uint8_t RESERVED_37[184]; __IO uint32_t HWWAKE; /**< Configures special cases of hardware wake-up, offset: 0x780 */ uint8_t RESERVED_38[124]; - __IO uint32_t CPCTRL; /**< CPU Control for multiple processors, offset: 0x800 */ + __IO uint32_t CPUCTRL; /**< CPU Control for multiple processors, offset: 0x800 */ __IO uint32_t CPBOOT; /**< Coprocessor Boot Address, offset: 0x804 */ __IO uint32_t CPSTACK; /**< Coprocessor Stack Address, offset: 0x808 */ __I uint32_t CPSTAT; /**< Coprocessor Status, offset: 0x80C */ @@ -4458,6 +4900,7 @@ typedef struct { */ /*! @name AHBMATPRIO - AHB multilayer matrix priority control */ +/*! @{ */ #define SYSCON_AHBMATPRIO_PRI_ICODE_MASK (0x3U) #define SYSCON_AHBMATPRIO_PRI_ICODE_SHIFT (0U) #define SYSCON_AHBMATPRIO_PRI_ICODE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_ICODE_SHIFT)) & SYSCON_AHBMATPRIO_PRI_ICODE_MASK) @@ -4476,8 +4919,10 @@ typedef struct { #define SYSCON_AHBMATPRIO_PRI_DMA_MASK (0xC00U) #define SYSCON_AHBMATPRIO_PRI_DMA_SHIFT (10U) #define SYSCON_AHBMATPRIO_PRI_DMA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_DMA_SHIFT)) & SYSCON_AHBMATPRIO_PRI_DMA_MASK) +/*! @} */ /*! @name SYSTCKCAL - System tick counter calibration */ +/*! @{ */ #define SYSCON_SYSTCKCAL_CAL_MASK (0xFFFFFFU) #define SYSCON_SYSTCKCAL_CAL_SHIFT (0U) #define SYSCON_SYSTCKCAL_CAL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTCKCAL_CAL_SHIFT)) & SYSCON_SYSTCKCAL_CAL_MASK) @@ -4487,8 +4932,10 @@ typedef struct { #define SYSCON_SYSTCKCAL_NOREF_MASK (0x2000000U) #define SYSCON_SYSTCKCAL_NOREF_SHIFT (25U) #define SYSCON_SYSTCKCAL_NOREF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTCKCAL_NOREF_SHIFT)) & SYSCON_SYSTCKCAL_NOREF_MASK) +/*! @} */ /*! @name NMISRC - NMI Source Select */ +/*! @{ */ #define SYSCON_NMISRC_IRQM4_MASK (0x3FU) #define SYSCON_NMISRC_IRQM4_SHIFT (0U) #define SYSCON_NMISRC_IRQM4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_NMISRC_IRQM4_SHIFT)) & SYSCON_NMISRC_IRQM4_MASK) @@ -4501,29 +4948,37 @@ typedef struct { #define SYSCON_NMISRC_NMIENM4_MASK (0x80000000U) #define SYSCON_NMISRC_NMIENM4_SHIFT (31U) #define SYSCON_NMISRC_NMIENM4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_NMISRC_NMIENM4_SHIFT)) & SYSCON_NMISRC_NMIENM4_MASK) +/*! @} */ /*! @name ASYNCAPBCTRL - Asynchronous APB Control */ +/*! @{ */ #define SYSCON_ASYNCAPBCTRL_ENABLE_MASK (0x1U) #define SYSCON_ASYNCAPBCTRL_ENABLE_SHIFT (0U) #define SYSCON_ASYNCAPBCTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ASYNCAPBCTRL_ENABLE_SHIFT)) & SYSCON_ASYNCAPBCTRL_ENABLE_MASK) +/*! @} */ /*! @name PIOPORCAP - POR captured value of port n */ +/*! @{ */ #define SYSCON_PIOPORCAP_PIOPORCAP_MASK (0xFFFFFFFFU) #define SYSCON_PIOPORCAP_PIOPORCAP_SHIFT (0U) #define SYSCON_PIOPORCAP_PIOPORCAP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PIOPORCAP_PIOPORCAP_SHIFT)) & SYSCON_PIOPORCAP_PIOPORCAP_MASK) +/*! @} */ /* The count of SYSCON_PIOPORCAP */ #define SYSCON_PIOPORCAP_COUNT (2U) /*! @name PIORESCAP - Reset captured value of port n */ +/*! @{ */ #define SYSCON_PIORESCAP_PIORESCAP_MASK (0xFFFFFFFFU) #define SYSCON_PIORESCAP_PIORESCAP_SHIFT (0U) #define SYSCON_PIORESCAP_PIORESCAP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PIORESCAP_PIORESCAP_SHIFT)) & SYSCON_PIORESCAP_PIORESCAP_MASK) +/*! @} */ /* The count of SYSCON_PIORESCAP */ #define SYSCON_PIORESCAP_COUNT (2U) /*! @name PRESETCTRL - Peripheral reset control n */ +/*! @{ */ #define SYSCON_PRESETCTRL_MRT0_RST_MASK (0x1U) #define SYSCON_PRESETCTRL_MRT0_RST_SHIFT (0U) #define SYSCON_PRESETCTRL_MRT0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_MRT0_RST_SHIFT)) & SYSCON_PRESETCTRL_MRT0_RST_MASK) @@ -4539,12 +4994,12 @@ typedef struct { #define SYSCON_PRESETCTRL_UTICK0_RST_MASK (0x400U) #define SYSCON_PRESETCTRL_UTICK0_RST_SHIFT (10U) #define SYSCON_PRESETCTRL_UTICK0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_UTICK0_RST_SHIFT)) & SYSCON_PRESETCTRL_UTICK0_RST_MASK) -#define SYSCON_PRESETCTRL_MUX_RST_MASK (0x800U) -#define SYSCON_PRESETCTRL_MUX_RST_SHIFT (11U) -#define SYSCON_PRESETCTRL_MUX_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_MUX_RST_SHIFT)) & SYSCON_PRESETCTRL_MUX_RST_MASK) #define SYSCON_PRESETCTRL_FC0_RST_MASK (0x800U) #define SYSCON_PRESETCTRL_FC0_RST_SHIFT (11U) #define SYSCON_PRESETCTRL_FC0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FC0_RST_SHIFT)) & SYSCON_PRESETCTRL_FC0_RST_MASK) +#define SYSCON_PRESETCTRL_MUX_RST_MASK (0x800U) +#define SYSCON_PRESETCTRL_MUX_RST_SHIFT (11U) +#define SYSCON_PRESETCTRL_MUX_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_MUX_RST_SHIFT)) & SYSCON_PRESETCTRL_MUX_RST_MASK) #define SYSCON_PRESETCTRL_FC1_RST_MASK (0x1000U) #define SYSCON_PRESETCTRL_FC1_RST_SHIFT (12U) #define SYSCON_PRESETCTRL_FC1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FC1_RST_SHIFT)) & SYSCON_PRESETCTRL_FC1_RST_MASK) @@ -4578,12 +5033,12 @@ typedef struct { #define SYSCON_PRESETCTRL_PINT_RST_MASK (0x40000U) #define SYSCON_PRESETCTRL_PINT_RST_SHIFT (18U) #define SYSCON_PRESETCTRL_PINT_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_PINT_RST_SHIFT)) & SYSCON_PRESETCTRL_PINT_RST_MASK) -#define SYSCON_PRESETCTRL_GINT_RST_MASK (0x80000U) -#define SYSCON_PRESETCTRL_GINT_RST_SHIFT (19U) -#define SYSCON_PRESETCTRL_GINT_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_GINT_RST_SHIFT)) & SYSCON_PRESETCTRL_GINT_RST_MASK) #define SYSCON_PRESETCTRL_DMIC0_RST_MASK (0x80000U) #define SYSCON_PRESETCTRL_DMIC0_RST_SHIFT (19U) #define SYSCON_PRESETCTRL_DMIC0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_DMIC0_RST_SHIFT)) & SYSCON_PRESETCTRL_DMIC0_RST_MASK) +#define SYSCON_PRESETCTRL_GINT_RST_MASK (0x80000U) +#define SYSCON_PRESETCTRL_GINT_RST_SHIFT (19U) +#define SYSCON_PRESETCTRL_GINT_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_GINT_RST_SHIFT)) & SYSCON_PRESETCTRL_GINT_RST_MASK) #define SYSCON_PRESETCTRL_DMA0_RST_MASK (0x100000U) #define SYSCON_PRESETCTRL_DMA0_RST_SHIFT (20U) #define SYSCON_PRESETCTRL_DMA0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_DMA0_RST_SHIFT)) & SYSCON_PRESETCTRL_DMA0_RST_MASK) @@ -4602,33 +5057,39 @@ typedef struct { #define SYSCON_PRESETCTRL_CTIMER0_RST_MASK (0x4000000U) #define SYSCON_PRESETCTRL_CTIMER0_RST_SHIFT (26U) #define SYSCON_PRESETCTRL_CTIMER0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_CTIMER0_RST_SHIFT)) & SYSCON_PRESETCTRL_CTIMER0_RST_MASK) -#define SYSCON_PRESETCTRL_CTIMER1_RST_MASK (0x8000000U) -#define SYSCON_PRESETCTRL_CTIMER1_RST_SHIFT (27U) -#define SYSCON_PRESETCTRL_CTIMER1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_CTIMER1_RST_SHIFT)) & SYSCON_PRESETCTRL_CTIMER1_RST_MASK) #define SYSCON_PRESETCTRL_ADC0_RST_MASK (0x8000000U) #define SYSCON_PRESETCTRL_ADC0_RST_SHIFT (27U) #define SYSCON_PRESETCTRL_ADC0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_ADC0_RST_SHIFT)) & SYSCON_PRESETCTRL_ADC0_RST_MASK) +#define SYSCON_PRESETCTRL_CTIMER1_RST_MASK (0x8000000U) +#define SYSCON_PRESETCTRL_CTIMER1_RST_SHIFT (27U) +#define SYSCON_PRESETCTRL_CTIMER1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_CTIMER1_RST_SHIFT)) & SYSCON_PRESETCTRL_CTIMER1_RST_MASK) +/*! @} */ /* The count of SYSCON_PRESETCTRL */ #define SYSCON_PRESETCTRL_COUNT (2U) /*! @name PRESETCTRLSET - Set bits in PRESETCTRLn */ +/*! @{ */ #define SYSCON_PRESETCTRLSET_RST_SET_MASK (0xFFFFFFFFU) #define SYSCON_PRESETCTRLSET_RST_SET_SHIFT (0U) #define SYSCON_PRESETCTRLSET_RST_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRLSET_RST_SET_SHIFT)) & SYSCON_PRESETCTRLSET_RST_SET_MASK) +/*! @} */ /* The count of SYSCON_PRESETCTRLSET */ #define SYSCON_PRESETCTRLSET_COUNT (2U) /*! @name PRESETCTRLCLR - Clear bits in PRESETCTRLn */ +/*! @{ */ #define SYSCON_PRESETCTRLCLR_RST_CLR_MASK (0xFFFFFFFFU) #define SYSCON_PRESETCTRLCLR_RST_CLR_SHIFT (0U) #define SYSCON_PRESETCTRLCLR_RST_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRLCLR_RST_CLR_SHIFT)) & SYSCON_PRESETCTRLCLR_RST_CLR_MASK) +/*! @} */ /* The count of SYSCON_PRESETCTRLCLR */ #define SYSCON_PRESETCTRLCLR_COUNT (2U) /*! @name SYSRSTSTAT - System reset status register */ +/*! @{ */ #define SYSCON_SYSRSTSTAT_POR_MASK (0x1U) #define SYSCON_SYSRSTSTAT_POR_SHIFT (0U) #define SYSCON_SYSRSTSTAT_POR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSRSTSTAT_POR_SHIFT)) & SYSCON_SYSRSTSTAT_POR_MASK) @@ -4644,8 +5105,10 @@ typedef struct { #define SYSCON_SYSRSTSTAT_SYSRST_MASK (0x10U) #define SYSCON_SYSRSTSTAT_SYSRST_SHIFT (4U) #define SYSCON_SYSRSTSTAT_SYSRST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSRSTSTAT_SYSRST_SHIFT)) & SYSCON_SYSRSTSTAT_SYSRST_MASK) +/*! @} */ /*! @name AHBCLKCTRL - AHB Clock control n */ +/*! @{ */ #define SYSCON_AHBCLKCTRL_MRT0_MASK (0x1U) #define SYSCON_AHBCLKCTRL_MRT0_SHIFT (0U) #define SYSCON_AHBCLKCTRL_MRT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_MRT0_SHIFT)) & SYSCON_AHBCLKCTRL_MRT0_MASK) @@ -4679,18 +5142,18 @@ typedef struct { #define SYSCON_AHBCLKCTRL_FLEXCOMM1_MASK (0x1000U) #define SYSCON_AHBCLKCTRL_FLEXCOMM1_SHIFT (12U) #define SYSCON_AHBCLKCTRL_FLEXCOMM1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLEXCOMM1_SHIFT)) & SYSCON_AHBCLKCTRL_FLEXCOMM1_MASK) -#define SYSCON_AHBCLKCTRL_IOCON_MASK (0x2000U) -#define SYSCON_AHBCLKCTRL_IOCON_SHIFT (13U) -#define SYSCON_AHBCLKCTRL_IOCON(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_IOCON_SHIFT)) & SYSCON_AHBCLKCTRL_IOCON_MASK) #define SYSCON_AHBCLKCTRL_FLEXCOMM2_MASK (0x2000U) #define SYSCON_AHBCLKCTRL_FLEXCOMM2_SHIFT (13U) #define SYSCON_AHBCLKCTRL_FLEXCOMM2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLEXCOMM2_SHIFT)) & SYSCON_AHBCLKCTRL_FLEXCOMM2_MASK) -#define SYSCON_AHBCLKCTRL_GPIO0_MASK (0x4000U) -#define SYSCON_AHBCLKCTRL_GPIO0_SHIFT (14U) -#define SYSCON_AHBCLKCTRL_GPIO0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_GPIO0_SHIFT)) & SYSCON_AHBCLKCTRL_GPIO0_MASK) +#define SYSCON_AHBCLKCTRL_IOCON_MASK (0x2000U) +#define SYSCON_AHBCLKCTRL_IOCON_SHIFT (13U) +#define SYSCON_AHBCLKCTRL_IOCON(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_IOCON_SHIFT)) & SYSCON_AHBCLKCTRL_IOCON_MASK) #define SYSCON_AHBCLKCTRL_FLEXCOMM3_MASK (0x4000U) #define SYSCON_AHBCLKCTRL_FLEXCOMM3_SHIFT (14U) #define SYSCON_AHBCLKCTRL_FLEXCOMM3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLEXCOMM3_SHIFT)) & SYSCON_AHBCLKCTRL_FLEXCOMM3_MASK) +#define SYSCON_AHBCLKCTRL_GPIO0_MASK (0x4000U) +#define SYSCON_AHBCLKCTRL_GPIO0_SHIFT (14U) +#define SYSCON_AHBCLKCTRL_GPIO0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_GPIO0_SHIFT)) & SYSCON_AHBCLKCTRL_GPIO0_MASK) #define SYSCON_AHBCLKCTRL_FLEXCOMM4_MASK (0x8000U) #define SYSCON_AHBCLKCTRL_FLEXCOMM4_SHIFT (15U) #define SYSCON_AHBCLKCTRL_FLEXCOMM4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLEXCOMM4_SHIFT)) & SYSCON_AHBCLKCTRL_FLEXCOMM4_MASK) @@ -4709,12 +5172,12 @@ typedef struct { #define SYSCON_AHBCLKCTRL_PINT_MASK (0x40000U) #define SYSCON_AHBCLKCTRL_PINT_SHIFT (18U) #define SYSCON_AHBCLKCTRL_PINT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_PINT_SHIFT)) & SYSCON_AHBCLKCTRL_PINT_MASK) -#define SYSCON_AHBCLKCTRL_GINT_MASK (0x80000U) -#define SYSCON_AHBCLKCTRL_GINT_SHIFT (19U) -#define SYSCON_AHBCLKCTRL_GINT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_GINT_SHIFT)) & SYSCON_AHBCLKCTRL_GINT_MASK) #define SYSCON_AHBCLKCTRL_DMIC0_MASK (0x80000U) #define SYSCON_AHBCLKCTRL_DMIC0_SHIFT (19U) #define SYSCON_AHBCLKCTRL_DMIC0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_DMIC0_SHIFT)) & SYSCON_AHBCLKCTRL_DMIC0_MASK) +#define SYSCON_AHBCLKCTRL_GINT_MASK (0x80000U) +#define SYSCON_AHBCLKCTRL_GINT_SHIFT (19U) +#define SYSCON_AHBCLKCTRL_GINT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_GINT_SHIFT)) & SYSCON_AHBCLKCTRL_GINT_MASK) #define SYSCON_AHBCLKCTRL_DMA0_MASK (0x100000U) #define SYSCON_AHBCLKCTRL_DMA0_SHIFT (20U) #define SYSCON_AHBCLKCTRL_DMA0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_DMA0_SHIFT)) & SYSCON_AHBCLKCTRL_DMA0_MASK) @@ -4739,91 +5202,119 @@ typedef struct { #define SYSCON_AHBCLKCTRL_MAILBOX_MASK (0x4000000U) #define SYSCON_AHBCLKCTRL_MAILBOX_SHIFT (26U) #define SYSCON_AHBCLKCTRL_MAILBOX(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_MAILBOX_SHIFT)) & SYSCON_AHBCLKCTRL_MAILBOX_MASK) -#define SYSCON_AHBCLKCTRL_CTIMER1_MASK (0x8000000U) -#define SYSCON_AHBCLKCTRL_CTIMER1_SHIFT (27U) -#define SYSCON_AHBCLKCTRL_CTIMER1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_CTIMER1_SHIFT)) & SYSCON_AHBCLKCTRL_CTIMER1_MASK) #define SYSCON_AHBCLKCTRL_ADC0_MASK (0x8000000U) #define SYSCON_AHBCLKCTRL_ADC0_SHIFT (27U) #define SYSCON_AHBCLKCTRL_ADC0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_ADC0_SHIFT)) & SYSCON_AHBCLKCTRL_ADC0_MASK) +#define SYSCON_AHBCLKCTRL_CTIMER1_MASK (0x8000000U) +#define SYSCON_AHBCLKCTRL_CTIMER1_SHIFT (27U) +#define SYSCON_AHBCLKCTRL_CTIMER1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_CTIMER1_SHIFT)) & SYSCON_AHBCLKCTRL_CTIMER1_MASK) +/*! @} */ /* The count of SYSCON_AHBCLKCTRL */ #define SYSCON_AHBCLKCTRL_COUNT (2U) /*! @name AHBCLKCTRLSET - Set bits in AHBCLKCTRLn */ +/*! @{ */ #define SYSCON_AHBCLKCTRLSET_CLK_SET_MASK (0xFFFFFFFFU) #define SYSCON_AHBCLKCTRLSET_CLK_SET_SHIFT (0U) #define SYSCON_AHBCLKCTRLSET_CLK_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRLSET_CLK_SET_SHIFT)) & SYSCON_AHBCLKCTRLSET_CLK_SET_MASK) +/*! @} */ /* The count of SYSCON_AHBCLKCTRLSET */ #define SYSCON_AHBCLKCTRLSET_COUNT (2U) /*! @name AHBCLKCTRLCLR - Clear bits in AHBCLKCTRLn */ +/*! @{ */ #define SYSCON_AHBCLKCTRLCLR_CLK_CLR_MASK (0xFFFFFFFFU) #define SYSCON_AHBCLKCTRLCLR_CLK_CLR_SHIFT (0U) #define SYSCON_AHBCLKCTRLCLR_CLK_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRLCLR_CLK_CLR_SHIFT)) & SYSCON_AHBCLKCTRLCLR_CLK_CLR_MASK) +/*! @} */ /* The count of SYSCON_AHBCLKCTRLCLR */ #define SYSCON_AHBCLKCTRLCLR_COUNT (2U) /*! @name MAINCLKSELA - Main clock source select A */ +/*! @{ */ #define SYSCON_MAINCLKSELA_SEL_MASK (0x3U) #define SYSCON_MAINCLKSELA_SEL_SHIFT (0U) #define SYSCON_MAINCLKSELA_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MAINCLKSELA_SEL_SHIFT)) & SYSCON_MAINCLKSELA_SEL_MASK) +/*! @} */ /*! @name MAINCLKSELB - Main clock source select B */ +/*! @{ */ #define SYSCON_MAINCLKSELB_SEL_MASK (0x3U) #define SYSCON_MAINCLKSELB_SEL_SHIFT (0U) #define SYSCON_MAINCLKSELB_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MAINCLKSELB_SEL_SHIFT)) & SYSCON_MAINCLKSELB_SEL_MASK) +/*! @} */ /*! @name CLKOUTSELA - CLKOUT clock source select A */ +/*! @{ */ #define SYSCON_CLKOUTSELA_SEL_MASK (0x7U) #define SYSCON_CLKOUTSELA_SEL_SHIFT (0U) #define SYSCON_CLKOUTSELA_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTSELA_SEL_SHIFT)) & SYSCON_CLKOUTSELA_SEL_MASK) +/*! @} */ /*! @name SYSPLLCLKSEL - PLL clock source select */ +/*! @{ */ #define SYSCON_SYSPLLCLKSEL_SEL_MASK (0x7U) #define SYSCON_SYSPLLCLKSEL_SEL_SHIFT (0U) #define SYSCON_SYSPLLCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLCLKSEL_SEL_SHIFT)) & SYSCON_SYSPLLCLKSEL_SEL_MASK) +/*! @} */ /*! @name SPIFICLKSEL - SPIFI clock source select */ +/*! @{ */ #define SYSCON_SPIFICLKSEL_SEL_MASK (0x7U) #define SYSCON_SPIFICLKSEL_SEL_SHIFT (0U) #define SYSCON_SPIFICLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SPIFICLKSEL_SEL_SHIFT)) & SYSCON_SPIFICLKSEL_SEL_MASK) +/*! @} */ /*! @name ADCCLKSEL - ADC clock source select */ +/*! @{ */ #define SYSCON_ADCCLKSEL_SEL_MASK (0x7U) #define SYSCON_ADCCLKSEL_SEL_SHIFT (0U) #define SYSCON_ADCCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADCCLKSEL_SEL_SHIFT)) & SYSCON_ADCCLKSEL_SEL_MASK) +/*! @} */ /*! @name USBCLKSEL - USB clock source select */ +/*! @{ */ #define SYSCON_USBCLKSEL_SEL_MASK (0x7U) #define SYSCON_USBCLKSEL_SEL_SHIFT (0U) #define SYSCON_USBCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USBCLKSEL_SEL_SHIFT)) & SYSCON_USBCLKSEL_SEL_MASK) +/*! @} */ /*! @name FXCOMCLKSEL - Flexcomm 0 clock source select */ +/*! @{ */ #define SYSCON_FXCOMCLKSEL_SEL_MASK (0x7U) #define SYSCON_FXCOMCLKSEL_SEL_SHIFT (0U) #define SYSCON_FXCOMCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FXCOMCLKSEL_SEL_SHIFT)) & SYSCON_FXCOMCLKSEL_SEL_MASK) +/*! @} */ /* The count of SYSCON_FXCOMCLKSEL */ #define SYSCON_FXCOMCLKSEL_COUNT (8U) /*! @name MCLKCLKSEL - MCLK clock source select */ +/*! @{ */ #define SYSCON_MCLKCLKSEL_SEL_MASK (0x7U) #define SYSCON_MCLKCLKSEL_SEL_SHIFT (0U) #define SYSCON_MCLKCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKCLKSEL_SEL_SHIFT)) & SYSCON_MCLKCLKSEL_SEL_MASK) +/*! @} */ /*! @name FRGCLKSEL - Fractional Rate Generator clock source select */ +/*! @{ */ #define SYSCON_FRGCLKSEL_SEL_MASK (0x7U) #define SYSCON_FRGCLKSEL_SEL_SHIFT (0U) #define SYSCON_FRGCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FRGCLKSEL_SEL_SHIFT)) & SYSCON_FRGCLKSEL_SEL_MASK) +/*! @} */ /*! @name DMICCLKSEL - Digital microphone (D-Mic) subsystem clock select */ +/*! @{ */ #define SYSCON_DMICCLKSEL_SEL_MASK (0x7U) #define SYSCON_DMICCLKSEL_SEL_SHIFT (0U) #define SYSCON_DMICCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DMICCLKSEL_SEL_SHIFT)) & SYSCON_DMICCLKSEL_SEL_MASK) +/*! @} */ /*! @name SYSTICKCLKDIV - SYSTICK clock divider */ +/*! @{ */ #define SYSCON_SYSTICKCLKDIV_DIV_MASK (0xFFU) #define SYSCON_SYSTICKCLKDIV_DIV_SHIFT (0U) #define SYSCON_SYSTICKCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV_DIV_SHIFT)) & SYSCON_SYSTICKCLKDIV_DIV_MASK) @@ -4833,8 +5324,10 @@ typedef struct { #define SYSCON_SYSTICKCLKDIV_HALT_MASK (0x40000000U) #define SYSCON_SYSTICKCLKDIV_HALT_SHIFT (30U) #define SYSCON_SYSTICKCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV_HALT_SHIFT)) & SYSCON_SYSTICKCLKDIV_HALT_MASK) +/*! @} */ /*! @name TRACECLKDIV - Trace clock divider */ +/*! @{ */ #define SYSCON_TRACECLKDIV_DIV_MASK (0xFFU) #define SYSCON_TRACECLKDIV_DIV_SHIFT (0U) #define SYSCON_TRACECLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_TRACECLKDIV_DIV_SHIFT)) & SYSCON_TRACECLKDIV_DIV_MASK) @@ -4844,8 +5337,10 @@ typedef struct { #define SYSCON_TRACECLKDIV_HALT_MASK (0x40000000U) #define SYSCON_TRACECLKDIV_HALT_SHIFT (30U) #define SYSCON_TRACECLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_TRACECLKDIV_HALT_SHIFT)) & SYSCON_TRACECLKDIV_HALT_MASK) +/*! @} */ /*! @name AHBCLKDIV - AHB clock divider */ +/*! @{ */ #define SYSCON_AHBCLKDIV_DIV_MASK (0xFFU) #define SYSCON_AHBCLKDIV_DIV_SHIFT (0U) #define SYSCON_AHBCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKDIV_DIV_SHIFT)) & SYSCON_AHBCLKDIV_DIV_MASK) @@ -4855,8 +5350,10 @@ typedef struct { #define SYSCON_AHBCLKDIV_HALT_MASK (0x40000000U) #define SYSCON_AHBCLKDIV_HALT_SHIFT (30U) #define SYSCON_AHBCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKDIV_HALT_SHIFT)) & SYSCON_AHBCLKDIV_HALT_MASK) +/*! @} */ /*! @name CLKOUTDIV - CLKOUT clock divider */ +/*! @{ */ #define SYSCON_CLKOUTDIV_DIV_MASK (0xFFU) #define SYSCON_CLKOUTDIV_DIV_SHIFT (0U) #define SYSCON_CLKOUTDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTDIV_DIV_SHIFT)) & SYSCON_CLKOUTDIV_DIV_MASK) @@ -4866,8 +5363,10 @@ typedef struct { #define SYSCON_CLKOUTDIV_HALT_MASK (0x40000000U) #define SYSCON_CLKOUTDIV_HALT_SHIFT (30U) #define SYSCON_CLKOUTDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTDIV_HALT_SHIFT)) & SYSCON_CLKOUTDIV_HALT_MASK) +/*! @} */ /*! @name SPIFICLKDIV - SPIFI clock divider */ +/*! @{ */ #define SYSCON_SPIFICLKDIV_DIV_MASK (0xFFU) #define SYSCON_SPIFICLKDIV_DIV_SHIFT (0U) #define SYSCON_SPIFICLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SPIFICLKDIV_DIV_SHIFT)) & SYSCON_SPIFICLKDIV_DIV_MASK) @@ -4877,8 +5376,10 @@ typedef struct { #define SYSCON_SPIFICLKDIV_HALT_MASK (0x40000000U) #define SYSCON_SPIFICLKDIV_HALT_SHIFT (30U) #define SYSCON_SPIFICLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SPIFICLKDIV_HALT_SHIFT)) & SYSCON_SPIFICLKDIV_HALT_MASK) +/*! @} */ /*! @name ADCCLKDIV - ADC clock divider */ +/*! @{ */ #define SYSCON_ADCCLKDIV_DIV_MASK (0xFFU) #define SYSCON_ADCCLKDIV_DIV_SHIFT (0U) #define SYSCON_ADCCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADCCLKDIV_DIV_SHIFT)) & SYSCON_ADCCLKDIV_DIV_MASK) @@ -4888,8 +5389,10 @@ typedef struct { #define SYSCON_ADCCLKDIV_HALT_MASK (0x40000000U) #define SYSCON_ADCCLKDIV_HALT_SHIFT (30U) #define SYSCON_ADCCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADCCLKDIV_HALT_SHIFT)) & SYSCON_ADCCLKDIV_HALT_MASK) +/*! @} */ /*! @name USBCLKDIV - USB clock divider */ +/*! @{ */ #define SYSCON_USBCLKDIV_DIV_MASK (0xFFU) #define SYSCON_USBCLKDIV_DIV_SHIFT (0U) #define SYSCON_USBCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USBCLKDIV_DIV_SHIFT)) & SYSCON_USBCLKDIV_DIV_MASK) @@ -4899,16 +5402,20 @@ typedef struct { #define SYSCON_USBCLKDIV_HALT_MASK (0x40000000U) #define SYSCON_USBCLKDIV_HALT_SHIFT (30U) #define SYSCON_USBCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USBCLKDIV_HALT_SHIFT)) & SYSCON_USBCLKDIV_HALT_MASK) +/*! @} */ /*! @name FRGCTRL - Fractional rate divider */ +/*! @{ */ #define SYSCON_FRGCTRL_DIV_MASK (0xFFU) #define SYSCON_FRGCTRL_DIV_SHIFT (0U) #define SYSCON_FRGCTRL_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FRGCTRL_DIV_SHIFT)) & SYSCON_FRGCTRL_DIV_MASK) #define SYSCON_FRGCTRL_MULT_MASK (0xFF00U) #define SYSCON_FRGCTRL_MULT_SHIFT (8U) #define SYSCON_FRGCTRL_MULT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FRGCTRL_MULT_SHIFT)) & SYSCON_FRGCTRL_MULT_MASK) +/*! @} */ /*! @name DMICCLKDIV - DMIC clock divider */ +/*! @{ */ #define SYSCON_DMICCLKDIV_DIV_MASK (0xFFU) #define SYSCON_DMICCLKDIV_DIV_SHIFT (0U) #define SYSCON_DMICCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DMICCLKDIV_DIV_SHIFT)) & SYSCON_DMICCLKDIV_DIV_MASK) @@ -4918,8 +5425,10 @@ typedef struct { #define SYSCON_DMICCLKDIV_HALT_MASK (0x40000000U) #define SYSCON_DMICCLKDIV_HALT_SHIFT (30U) #define SYSCON_DMICCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DMICCLKDIV_HALT_SHIFT)) & SYSCON_DMICCLKDIV_HALT_MASK) +/*! @} */ /*! @name MCLKDIV - I2S MCLK clock divider */ +/*! @{ */ #define SYSCON_MCLKDIV_DIV_MASK (0xFFU) #define SYSCON_MCLKDIV_DIV_SHIFT (0U) #define SYSCON_MCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKDIV_DIV_SHIFT)) & SYSCON_MCLKDIV_DIV_MASK) @@ -4929,8 +5438,10 @@ typedef struct { #define SYSCON_MCLKDIV_HALT_MASK (0x40000000U) #define SYSCON_MCLKDIV_HALT_SHIFT (30U) #define SYSCON_MCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKDIV_HALT_SHIFT)) & SYSCON_MCLKDIV_HALT_MASK) +/*! @} */ /*! @name FLASHCFG - Flash wait states configuration */ +/*! @{ */ #define SYSCON_FLASHCFG_FETCHCFG_MASK (0x3U) #define SYSCON_FLASHCFG_FETCHCFG_SHIFT (0U) #define SYSCON_FLASHCFG_FETCHCFG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLASHCFG_FETCHCFG_SHIFT)) & SYSCON_FLASHCFG_FETCHCFG_MASK) @@ -4949,31 +5460,41 @@ typedef struct { #define SYSCON_FLASHCFG_FLASHTIM_MASK (0xF000U) #define SYSCON_FLASHCFG_FLASHTIM_SHIFT (12U) #define SYSCON_FLASHCFG_FLASHTIM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLASHCFG_FLASHTIM_SHIFT)) & SYSCON_FLASHCFG_FLASHTIM_MASK) +/*! @} */ /*! @name USBCLKCTRL - USB clock control */ +/*! @{ */ #define SYSCON_USBCLKCTRL_POL_CLK_MASK (0x2U) #define SYSCON_USBCLKCTRL_POL_CLK_SHIFT (1U) #define SYSCON_USBCLKCTRL_POL_CLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USBCLKCTRL_POL_CLK_SHIFT)) & SYSCON_USBCLKCTRL_POL_CLK_MASK) +/*! @} */ /*! @name USBCLKSTAT - USB clock status */ +/*! @{ */ #define SYSCON_USBCLKSTAT_NEED_CLKST_MASK (0x1U) #define SYSCON_USBCLKSTAT_NEED_CLKST_SHIFT (0U) #define SYSCON_USBCLKSTAT_NEED_CLKST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USBCLKSTAT_NEED_CLKST_SHIFT)) & SYSCON_USBCLKSTAT_NEED_CLKST_MASK) +/*! @} */ /*! @name FREQMECTRL - Frequency measure register */ +/*! @{ */ #define SYSCON_FREQMECTRL_CAPVAL_MASK (0x3FFFU) #define SYSCON_FREQMECTRL_CAPVAL_SHIFT (0U) #define SYSCON_FREQMECTRL_CAPVAL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FREQMECTRL_CAPVAL_SHIFT)) & SYSCON_FREQMECTRL_CAPVAL_MASK) #define SYSCON_FREQMECTRL_PROG_MASK (0x80000000U) #define SYSCON_FREQMECTRL_PROG_SHIFT (31U) #define SYSCON_FREQMECTRL_PROG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FREQMECTRL_PROG_SHIFT)) & SYSCON_FREQMECTRL_PROG_MASK) +/*! @} */ /*! @name MCLKIO - MCLK input/output control */ +/*! @{ */ #define SYSCON_MCLKIO_DIR_MASK (0x1U) #define SYSCON_MCLKIO_DIR_SHIFT (0U) #define SYSCON_MCLKIO_DIR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKIO_DIR_SHIFT)) & SYSCON_MCLKIO_DIR_MASK) +/*! @} */ /*! @name FROCTRL - FRO oscillator control */ +/*! @{ */ #define SYSCON_FROCTRL_TRIM_MASK (0x3FFFU) #define SYSCON_FROCTRL_TRIM_SHIFT (0U) #define SYSCON_FROCTRL_TRIM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROCTRL_TRIM_SHIFT)) & SYSCON_FROCTRL_TRIM_MASK) @@ -4995,21 +5516,27 @@ typedef struct { #define SYSCON_FROCTRL_WRTRIM_MASK (0x80000000U) #define SYSCON_FROCTRL_WRTRIM_SHIFT (31U) #define SYSCON_FROCTRL_WRTRIM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROCTRL_WRTRIM_SHIFT)) & SYSCON_FROCTRL_WRTRIM_MASK) +/*! @} */ /*! @name WDTOSCCTRL - Watchdog oscillator control */ +/*! @{ */ #define SYSCON_WDTOSCCTRL_DIVSEL_MASK (0x1FU) #define SYSCON_WDTOSCCTRL_DIVSEL_SHIFT (0U) #define SYSCON_WDTOSCCTRL_DIVSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_WDTOSCCTRL_DIVSEL_SHIFT)) & SYSCON_WDTOSCCTRL_DIVSEL_MASK) #define SYSCON_WDTOSCCTRL_FREQSEL_MASK (0x3E0U) #define SYSCON_WDTOSCCTRL_FREQSEL_SHIFT (5U) #define SYSCON_WDTOSCCTRL_FREQSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_WDTOSCCTRL_FREQSEL_SHIFT)) & SYSCON_WDTOSCCTRL_FREQSEL_MASK) +/*! @} */ /*! @name RTCOSCCTRL - RTC oscillator 32 kHz output control */ +/*! @{ */ #define SYSCON_RTCOSCCTRL_EN_MASK (0x1U) #define SYSCON_RTCOSCCTRL_EN_SHIFT (0U) #define SYSCON_RTCOSCCTRL_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_RTCOSCCTRL_EN_SHIFT)) & SYSCON_RTCOSCCTRL_EN_MASK) +/*! @} */ /*! @name SYSPLLCTRL - PLL control */ +/*! @{ */ #define SYSCON_SYSPLLCTRL_SELR_MASK (0xFU) #define SYSCON_SYSPLLCTRL_SELR_SHIFT (0U) #define SYSCON_SYSPLLCTRL_SELR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLCTRL_SELR_SHIFT)) & SYSCON_SYSPLLCTRL_SELR_MASK) @@ -5037,29 +5564,37 @@ typedef struct { #define SYSCON_SYSPLLCTRL_DIRECTO_MASK (0x100000U) #define SYSCON_SYSPLLCTRL_DIRECTO_SHIFT (20U) #define SYSCON_SYSPLLCTRL_DIRECTO(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLCTRL_DIRECTO_SHIFT)) & SYSCON_SYSPLLCTRL_DIRECTO_MASK) +/*! @} */ /*! @name SYSPLLSTAT - PLL status */ +/*! @{ */ #define SYSCON_SYSPLLSTAT_LOCK_MASK (0x1U) #define SYSCON_SYSPLLSTAT_LOCK_SHIFT (0U) #define SYSCON_SYSPLLSTAT_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLSTAT_LOCK_SHIFT)) & SYSCON_SYSPLLSTAT_LOCK_MASK) +/*! @} */ /*! @name SYSPLLNDEC - PLL N decoder */ +/*! @{ */ #define SYSCON_SYSPLLNDEC_NDEC_MASK (0x3FFU) #define SYSCON_SYSPLLNDEC_NDEC_SHIFT (0U) #define SYSCON_SYSPLLNDEC_NDEC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLNDEC_NDEC_SHIFT)) & SYSCON_SYSPLLNDEC_NDEC_MASK) #define SYSCON_SYSPLLNDEC_NREQ_MASK (0x400U) #define SYSCON_SYSPLLNDEC_NREQ_SHIFT (10U) #define SYSCON_SYSPLLNDEC_NREQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLNDEC_NREQ_SHIFT)) & SYSCON_SYSPLLNDEC_NREQ_MASK) +/*! @} */ /*! @name SYSPLLPDEC - PLL P decoder */ +/*! @{ */ #define SYSCON_SYSPLLPDEC_PDEC_MASK (0x7FU) #define SYSCON_SYSPLLPDEC_PDEC_SHIFT (0U) #define SYSCON_SYSPLLPDEC_PDEC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLPDEC_PDEC_SHIFT)) & SYSCON_SYSPLLPDEC_PDEC_MASK) #define SYSCON_SYSPLLPDEC_PREQ_MASK (0x80U) #define SYSCON_SYSPLLPDEC_PREQ_SHIFT (7U) #define SYSCON_SYSPLLPDEC_PREQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLPDEC_PREQ_SHIFT)) & SYSCON_SYSPLLPDEC_PREQ_MASK) +/*! @} */ /*! @name SYSPLLSSCTRL0 - PLL spread spectrum control 0 */ +/*! @{ */ #define SYSCON_SYSPLLSSCTRL0_MDEC_MASK (0x1FFFFU) #define SYSCON_SYSPLLSSCTRL0_MDEC_SHIFT (0U) #define SYSCON_SYSPLLSSCTRL0_MDEC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLSSCTRL0_MDEC_SHIFT)) & SYSCON_SYSPLLSSCTRL0_MDEC_MASK) @@ -5069,8 +5604,10 @@ typedef struct { #define SYSCON_SYSPLLSSCTRL0_SEL_EXT_MASK (0x40000U) #define SYSCON_SYSPLLSSCTRL0_SEL_EXT_SHIFT (18U) #define SYSCON_SYSPLLSSCTRL0_SEL_EXT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLSSCTRL0_SEL_EXT_SHIFT)) & SYSCON_SYSPLLSSCTRL0_SEL_EXT_MASK) +/*! @} */ /*! @name SYSPLLSSCTRL1 - PLL spread spectrum control 1 */ +/*! @{ */ #define SYSCON_SYSPLLSSCTRL1_MD_MASK (0x7FFFFU) #define SYSCON_SYSPLLSSCTRL1_MD_SHIFT (0U) #define SYSCON_SYSPLLSSCTRL1_MD(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLSSCTRL1_MD_SHIFT)) & SYSCON_SYSPLLSSCTRL1_MD_MASK) @@ -5092,16 +5629,20 @@ typedef struct { #define SYSCON_SYSPLLSSCTRL1_DITHER_MASK (0x20000000U) #define SYSCON_SYSPLLSSCTRL1_DITHER_SHIFT (29U) #define SYSCON_SYSPLLSSCTRL1_DITHER(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLSSCTRL1_DITHER_SHIFT)) & SYSCON_SYSPLLSSCTRL1_DITHER_MASK) +/*! @} */ /*! @name PDSLEEPCFG - Sleep configuration register n */ +/*! @{ */ #define SYSCON_PDSLEEPCFG_PD_SLEEP_MASK (0xFFFFFFFFU) #define SYSCON_PDSLEEPCFG_PD_SLEEP_SHIFT (0U) #define SYSCON_PDSLEEPCFG_PD_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PD_SLEEP_SHIFT)) & SYSCON_PDSLEEPCFG_PD_SLEEP_MASK) +/*! @} */ /* The count of SYSCON_PDSLEEPCFG */ #define SYSCON_PDSLEEPCFG_COUNT (2U) /*! @name PDRUNCFG - Power configuration register n */ +/*! @{ */ #define SYSCON_PDRUNCFG_PDEN_FRO_MASK (0x10U) #define SYSCON_PDRUNCFG_PDEN_FRO_SHIFT (4U) #define SYSCON_PDRUNCFG_PDEN_FRO(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_FRO_SHIFT)) & SYSCON_PDRUNCFG_PDEN_FRO_MASK) @@ -5168,39 +5709,45 @@ typedef struct { #define SYSCON_PDRUNCFG_SEL_ALT_FLASH_IBG_MASK (0x20000000U) #define SYSCON_PDRUNCFG_SEL_ALT_FLASH_IBG_SHIFT (29U) #define SYSCON_PDRUNCFG_SEL_ALT_FLASH_IBG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_SEL_ALT_FLASH_IBG_SHIFT)) & SYSCON_PDRUNCFG_SEL_ALT_FLASH_IBG_MASK) +/*! @} */ /* The count of SYSCON_PDRUNCFG */ #define SYSCON_PDRUNCFG_COUNT (2U) /*! @name PDRUNCFGSET - Set bits in PDRUNCFGn */ +/*! @{ */ #define SYSCON_PDRUNCFGSET_PD_SET_MASK (0xFFFFFFFFU) #define SYSCON_PDRUNCFGSET_PD_SET_SHIFT (0U) #define SYSCON_PDRUNCFGSET_PD_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PD_SET_SHIFT)) & SYSCON_PDRUNCFGSET_PD_SET_MASK) +/*! @} */ /* The count of SYSCON_PDRUNCFGSET */ #define SYSCON_PDRUNCFGSET_COUNT (2U) /*! @name PDRUNCFGCLR - Clear bits in PDRUNCFGn */ +/*! @{ */ #define SYSCON_PDRUNCFGCLR_PD_CLR_MASK (0xFFFFFFFFU) #define SYSCON_PDRUNCFGCLR_PD_CLR_SHIFT (0U) #define SYSCON_PDRUNCFGCLR_PD_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PD_CLR_SHIFT)) & SYSCON_PDRUNCFGCLR_PD_CLR_MASK) +/*! @} */ /* The count of SYSCON_PDRUNCFGCLR */ #define SYSCON_PDRUNCFGCLR_COUNT (2U) /*! @name STARTERP - Start logic n wake-up enable register */ -#define SYSCON_STARTERP_WDT_BOD_MASK (0x1U) -#define SYSCON_STARTERP_WDT_BOD_SHIFT (0U) -#define SYSCON_STARTERP_WDT_BOD(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_WDT_BOD_SHIFT)) & SYSCON_STARTERP_WDT_BOD_MASK) +/*! @{ */ #define SYSCON_STARTERP_PINT4_MASK (0x1U) #define SYSCON_STARTERP_PINT4_SHIFT (0U) #define SYSCON_STARTERP_PINT4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_PINT4_SHIFT)) & SYSCON_STARTERP_PINT4_MASK) -#define SYSCON_STARTERP_PINT5_MASK (0x2U) -#define SYSCON_STARTERP_PINT5_SHIFT (1U) -#define SYSCON_STARTERP_PINT5(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_PINT5_SHIFT)) & SYSCON_STARTERP_PINT5_MASK) +#define SYSCON_STARTERP_WDT_BOD_MASK (0x1U) +#define SYSCON_STARTERP_WDT_BOD_SHIFT (0U) +#define SYSCON_STARTERP_WDT_BOD(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_WDT_BOD_SHIFT)) & SYSCON_STARTERP_WDT_BOD_MASK) #define SYSCON_STARTERP_DMA0_MASK (0x2U) #define SYSCON_STARTERP_DMA0_SHIFT (1U) #define SYSCON_STARTERP_DMA0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_DMA0_SHIFT)) & SYSCON_STARTERP_DMA0_MASK) +#define SYSCON_STARTERP_PINT5_MASK (0x2U) +#define SYSCON_STARTERP_PINT5_SHIFT (1U) +#define SYSCON_STARTERP_PINT5(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_PINT5_SHIFT)) & SYSCON_STARTERP_PINT5_MASK) #define SYSCON_STARTERP_GINT0_MASK (0x4U) #define SYSCON_STARTERP_GINT0_SHIFT (2U) #define SYSCON_STARTERP_GINT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_GINT0_SHIFT)) & SYSCON_STARTERP_GINT0_MASK) @@ -5219,12 +5766,12 @@ typedef struct { #define SYSCON_STARTERP_PIN_INT0_MASK (0x10U) #define SYSCON_STARTERP_PIN_INT0_SHIFT (4U) #define SYSCON_STARTERP_PIN_INT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_PIN_INT0_SHIFT)) & SYSCON_STARTERP_PIN_INT0_MASK) -#define SYSCON_STARTERP_PIN_INT1_MASK (0x20U) -#define SYSCON_STARTERP_PIN_INT1_SHIFT (5U) -#define SYSCON_STARTERP_PIN_INT1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_PIN_INT1_SHIFT)) & SYSCON_STARTERP_PIN_INT1_MASK) #define SYSCON_STARTERP_CTIMER4_MASK (0x20U) #define SYSCON_STARTERP_CTIMER4_SHIFT (5U) #define SYSCON_STARTERP_CTIMER4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_CTIMER4_SHIFT)) & SYSCON_STARTERP_CTIMER4_MASK) +#define SYSCON_STARTERP_PIN_INT1_MASK (0x20U) +#define SYSCON_STARTERP_PIN_INT1_SHIFT (5U) +#define SYSCON_STARTERP_PIN_INT1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_PIN_INT1_SHIFT)) & SYSCON_STARTERP_PIN_INT1_MASK) #define SYSCON_STARTERP_PIN_INT2_MASK (0x40U) #define SYSCON_STARTERP_PIN_INT2_SHIFT (6U) #define SYSCON_STARTERP_PIN_INT2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_PIN_INT2_SHIFT)) & SYSCON_STARTERP_PIN_INT2_MASK) @@ -5297,27 +5844,33 @@ typedef struct { #define SYSCON_STARTERP_MAILBOX_MASK (0x80000000U) #define SYSCON_STARTERP_MAILBOX_SHIFT (31U) #define SYSCON_STARTERP_MAILBOX(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_MAILBOX_SHIFT)) & SYSCON_STARTERP_MAILBOX_MASK) +/*! @} */ /* The count of SYSCON_STARTERP */ #define SYSCON_STARTERP_COUNT (2U) /*! @name STARTERSET - Set bits in STARTERn */ +/*! @{ */ #define SYSCON_STARTERSET_START_SET_MASK (0xFFFFFFFFU) #define SYSCON_STARTERSET_START_SET_SHIFT (0U) #define SYSCON_STARTERSET_START_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_START_SET_SHIFT)) & SYSCON_STARTERSET_START_SET_MASK) +/*! @} */ /* The count of SYSCON_STARTERSET */ #define SYSCON_STARTERSET_COUNT (2U) /*! @name STARTERCLR - Clear bits in STARTERn */ +/*! @{ */ #define SYSCON_STARTERCLR_START_CLR_MASK (0xFFFFFFFFU) #define SYSCON_STARTERCLR_START_CLR_SHIFT (0U) #define SYSCON_STARTERCLR_START_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_START_CLR_SHIFT)) & SYSCON_STARTERCLR_START_CLR_MASK) +/*! @} */ /* The count of SYSCON_STARTERCLR */ #define SYSCON_STARTERCLR_COUNT (2U) /*! @name HWWAKE - Configures special cases of hardware wake-up */ +/*! @{ */ #define SYSCON_HWWAKE_FORCEWAKE_MASK (0x1U) #define SYSCON_HWWAKE_FORCEWAKE_SHIFT (0U) #define SYSCON_HWWAKE_FORCEWAKE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_HWWAKE_FORCEWAKE_SHIFT)) & SYSCON_HWWAKE_FORCEWAKE_MASK) @@ -5330,38 +5883,46 @@ typedef struct { #define SYSCON_HWWAKE_WAKEDMA_MASK (0x8U) #define SYSCON_HWWAKE_WAKEDMA_SHIFT (3U) #define SYSCON_HWWAKE_WAKEDMA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_HWWAKE_WAKEDMA_SHIFT)) & SYSCON_HWWAKE_WAKEDMA_MASK) +/*! @} */ -/*! @name CPCTRL - CPU Control for multiple processors */ -#define SYSCON_CPCTRL_MASTERCPU_MASK (0x1U) -#define SYSCON_CPCTRL_MASTERCPU_SHIFT (0U) -#define SYSCON_CPCTRL_MASTERCPU(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPCTRL_MASTERCPU_SHIFT)) & SYSCON_CPCTRL_MASTERCPU_MASK) -#define SYSCON_CPCTRL_CM4CLKEN_MASK (0x4U) -#define SYSCON_CPCTRL_CM4CLKEN_SHIFT (2U) -#define SYSCON_CPCTRL_CM4CLKEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPCTRL_CM4CLKEN_SHIFT)) & SYSCON_CPCTRL_CM4CLKEN_MASK) -#define SYSCON_CPCTRL_CM0CLKEN_MASK (0x8U) -#define SYSCON_CPCTRL_CM0CLKEN_SHIFT (3U) -#define SYSCON_CPCTRL_CM0CLKEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPCTRL_CM0CLKEN_SHIFT)) & SYSCON_CPCTRL_CM0CLKEN_MASK) -#define SYSCON_CPCTRL_CM4RSTEN_MASK (0x10U) -#define SYSCON_CPCTRL_CM4RSTEN_SHIFT (4U) -#define SYSCON_CPCTRL_CM4RSTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPCTRL_CM4RSTEN_SHIFT)) & SYSCON_CPCTRL_CM4RSTEN_MASK) -#define SYSCON_CPCTRL_CM0RSTEN_MASK (0x20U) -#define SYSCON_CPCTRL_CM0RSTEN_SHIFT (5U) -#define SYSCON_CPCTRL_CM0RSTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPCTRL_CM0RSTEN_SHIFT)) & SYSCON_CPCTRL_CM0RSTEN_MASK) -#define SYSCON_CPCTRL_POWERCPU_MASK (0x40U) -#define SYSCON_CPCTRL_POWERCPU_SHIFT (6U) -#define SYSCON_CPCTRL_POWERCPU(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPCTRL_POWERCPU_SHIFT)) & SYSCON_CPCTRL_POWERCPU_MASK) +/*! @name CPUCTRL - CPU Control for multiple processors */ +/*! @{ */ +#define SYSCON_CPUCTRL_MASTERCPU_MASK (0x1U) +#define SYSCON_CPUCTRL_MASTERCPU_SHIFT (0U) +#define SYSCON_CPUCTRL_MASTERCPU(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPUCTRL_MASTERCPU_SHIFT)) & SYSCON_CPUCTRL_MASTERCPU_MASK) +#define SYSCON_CPUCTRL_CM4CLKEN_MASK (0x4U) +#define SYSCON_CPUCTRL_CM4CLKEN_SHIFT (2U) +#define SYSCON_CPUCTRL_CM4CLKEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPUCTRL_CM4CLKEN_SHIFT)) & SYSCON_CPUCTRL_CM4CLKEN_MASK) +#define SYSCON_CPUCTRL_CM0CLKEN_MASK (0x8U) +#define SYSCON_CPUCTRL_CM0CLKEN_SHIFT (3U) +#define SYSCON_CPUCTRL_CM0CLKEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPUCTRL_CM0CLKEN_SHIFT)) & SYSCON_CPUCTRL_CM0CLKEN_MASK) +#define SYSCON_CPUCTRL_CM4RSTEN_MASK (0x10U) +#define SYSCON_CPUCTRL_CM4RSTEN_SHIFT (4U) +#define SYSCON_CPUCTRL_CM4RSTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPUCTRL_CM4RSTEN_SHIFT)) & SYSCON_CPUCTRL_CM4RSTEN_MASK) +#define SYSCON_CPUCTRL_CM0RSTEN_MASK (0x20U) +#define SYSCON_CPUCTRL_CM0RSTEN_SHIFT (5U) +#define SYSCON_CPUCTRL_CM0RSTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPUCTRL_CM0RSTEN_SHIFT)) & SYSCON_CPUCTRL_CM0RSTEN_MASK) +#define SYSCON_CPUCTRL_POWERCPU_MASK (0x40U) +#define SYSCON_CPUCTRL_POWERCPU_SHIFT (6U) +#define SYSCON_CPUCTRL_POWERCPU(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPUCTRL_POWERCPU_SHIFT)) & SYSCON_CPUCTRL_POWERCPU_MASK) +/*! @} */ /*! @name CPBOOT - Coprocessor Boot Address */ +/*! @{ */ #define SYSCON_CPBOOT_BOOTADDR_MASK (0xFFFFFFFFU) #define SYSCON_CPBOOT_BOOTADDR_SHIFT (0U) #define SYSCON_CPBOOT_BOOTADDR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPBOOT_BOOTADDR_SHIFT)) & SYSCON_CPBOOT_BOOTADDR_MASK) +/*! @} */ /*! @name CPSTACK - Coprocessor Stack Address */ +/*! @{ */ #define SYSCON_CPSTACK_STACKADDR_MASK (0xFFFFFFFFU) #define SYSCON_CPSTACK_STACKADDR_SHIFT (0U) #define SYSCON_CPSTACK_STACKADDR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPSTACK_STACKADDR_SHIFT)) & SYSCON_CPSTACK_STACKADDR_MASK) +/*! @} */ /*! @name CPSTAT - Coprocessor Status */ +/*! @{ */ #define SYSCON_CPSTAT_CM4SLEEPING_MASK (0x1U) #define SYSCON_CPSTAT_CM4SLEEPING_SHIFT (0U) #define SYSCON_CPSTAT_CM4SLEEPING(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPSTAT_CM4SLEEPING_SHIFT)) & SYSCON_CPSTAT_CM4SLEEPING_MASK) @@ -5374,8 +5935,10 @@ typedef struct { #define SYSCON_CPSTAT_CM0LOCKUP_MASK (0x8U) #define SYSCON_CPSTAT_CM0LOCKUP_SHIFT (3U) #define SYSCON_CPSTAT_CM0LOCKUP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPSTAT_CM0LOCKUP_SHIFT)) & SYSCON_CPSTAT_CM0LOCKUP_MASK) +/*! @} */ /*! @name AUTOCGOR - Auto Clock-Gate Override Register */ +/*! @{ */ #define SYSCON_AUTOCGOR_RAM0X_MASK (0x2U) #define SYSCON_AUTOCGOR_RAM0X_SHIFT (1U) #define SYSCON_AUTOCGOR_RAM0X(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCGOR_RAM0X_SHIFT)) & SYSCON_AUTOCGOR_RAM0X_MASK) @@ -5385,23 +5948,31 @@ typedef struct { #define SYSCON_AUTOCGOR_RAM2_MASK (0x8U) #define SYSCON_AUTOCGOR_RAM2_SHIFT (3U) #define SYSCON_AUTOCGOR_RAM2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCGOR_RAM2_SHIFT)) & SYSCON_AUTOCGOR_RAM2_MASK) +/*! @} */ /*! @name JTAGIDCODE - JTAG ID code register */ +/*! @{ */ #define SYSCON_JTAGIDCODE_JTAGID_MASK (0xFFFFFFFFU) #define SYSCON_JTAGIDCODE_JTAGID_SHIFT (0U) #define SYSCON_JTAGIDCODE_JTAGID(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_JTAGIDCODE_JTAGID_SHIFT)) & SYSCON_JTAGIDCODE_JTAGID_MASK) +/*! @} */ /*! @name DEVICE_ID0 - Part ID register */ +/*! @{ */ #define SYSCON_DEVICE_ID0_PARTID_MASK (0xFFFFFFFFU) #define SYSCON_DEVICE_ID0_PARTID_SHIFT (0U) #define SYSCON_DEVICE_ID0_PARTID(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEVICE_ID0_PARTID_SHIFT)) & SYSCON_DEVICE_ID0_PARTID_MASK) +/*! @} */ /*! @name DEVICE_ID1 - Boot ROM and die revision register */ +/*! @{ */ #define SYSCON_DEVICE_ID1_REVID_MASK (0xFFFFFFFFU) #define SYSCON_DEVICE_ID1_REVID_SHIFT (0U) #define SYSCON_DEVICE_ID1_REVID(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEVICE_ID1_REVID_SHIFT)) & SYSCON_DEVICE_ID1_REVID_MASK) +/*! @} */ /*! @name BODCTRL - Brown-Out Detect control */ +/*! @{ */ #define SYSCON_BODCTRL_BODRSTLEV_MASK (0x3U) #define SYSCON_BODCTRL_BODRSTLEV_SHIFT (0U) #define SYSCON_BODCTRL_BODRSTLEV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_BODCTRL_BODRSTLEV_SHIFT)) & SYSCON_BODCTRL_BODRSTLEV_MASK) @@ -5420,6 +5991,7 @@ typedef struct { #define SYSCON_BODCTRL_BODINTSTAT_MASK (0x80U) #define SYSCON_BODCTRL_BODINTSTAT_SHIFT (7U) #define SYSCON_BODCTRL_BODINTSTAT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_BODCTRL_BODINTSTAT_SHIFT)) & SYSCON_BODCTRL_BODINTSTAT_MASK) +/*! @} */ /*! @@ -5489,6 +6061,7 @@ typedef struct { */ /*! @name CFG - USART Configuration register. Basic USART configuration settings that typically are not changed during operation. */ +/*! @{ */ #define USART_CFG_ENABLE_MASK (0x1U) #define USART_CFG_ENABLE_SHIFT (0U) #define USART_CFG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_ENABLE_SHIFT)) & USART_CFG_ENABLE_MASK) @@ -5543,8 +6116,10 @@ typedef struct { #define USART_CFG_TXPOL_MASK (0x800000U) #define USART_CFG_TXPOL_SHIFT (23U) #define USART_CFG_TXPOL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_TXPOL_SHIFT)) & USART_CFG_TXPOL_MASK) +/*! @} */ /*! @name CTL - USART Control register. USART control settings that are more likely to change during operation. */ +/*! @{ */ #define USART_CTL_TXBRKEN_MASK (0x2U) #define USART_CTL_TXBRKEN_SHIFT (1U) #define USART_CTL_TXBRKEN(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_TXBRKEN_SHIFT)) & USART_CTL_TXBRKEN_MASK) @@ -5563,8 +6138,10 @@ typedef struct { #define USART_CTL_AUTOBAUD_MASK (0x10000U) #define USART_CTL_AUTOBAUD_SHIFT (16U) #define USART_CTL_AUTOBAUD(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_AUTOBAUD_SHIFT)) & USART_CTL_AUTOBAUD_MASK) +/*! @} */ /*! @name STAT - USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them. */ +/*! @{ */ #define USART_STAT_RXIDLE_MASK (0x2U) #define USART_STAT_RXIDLE_SHIFT (1U) #define USART_STAT_RXIDLE(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_RXIDLE_SHIFT)) & USART_STAT_RXIDLE_MASK) @@ -5601,8 +6178,10 @@ typedef struct { #define USART_STAT_ABERR_MASK (0x10000U) #define USART_STAT_ABERR_SHIFT (16U) #define USART_STAT_ABERR(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_ABERR_SHIFT)) & USART_STAT_ABERR_MASK) +/*! @} */ /*! @name INTENSET - Interrupt Enable read and Set register for USART (not FIFO) status. Contains individual interrupt enable bits for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set. */ +/*! @{ */ #define USART_INTENSET_TXIDLEEN_MASK (0x8U) #define USART_INTENSET_TXIDLEEN_SHIFT (3U) #define USART_INTENSET_TXIDLEEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_TXIDLEEN_SHIFT)) & USART_INTENSET_TXIDLEEN_MASK) @@ -5630,8 +6209,10 @@ typedef struct { #define USART_INTENSET_ABERREN_MASK (0x10000U) #define USART_INTENSET_ABERREN_SHIFT (16U) #define USART_INTENSET_ABERREN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_ABERREN_SHIFT)) & USART_INTENSET_ABERREN_MASK) +/*! @} */ /*! @name INTENCLR - Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared. */ +/*! @{ */ #define USART_INTENCLR_TXIDLECLR_MASK (0x8U) #define USART_INTENCLR_TXIDLECLR_SHIFT (3U) #define USART_INTENCLR_TXIDLECLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_TXIDLECLR_SHIFT)) & USART_INTENCLR_TXIDLECLR_MASK) @@ -5659,13 +6240,17 @@ typedef struct { #define USART_INTENCLR_ABERRCLR_MASK (0x10000U) #define USART_INTENCLR_ABERRCLR_SHIFT (16U) #define USART_INTENCLR_ABERRCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_ABERRCLR_SHIFT)) & USART_INTENCLR_ABERRCLR_MASK) +/*! @} */ /*! @name BRG - Baud Rate Generator register. 16-bit integer baud rate divisor value. */ +/*! @{ */ #define USART_BRG_BRGVAL_MASK (0xFFFFU) #define USART_BRG_BRGVAL_SHIFT (0U) #define USART_BRG_BRGVAL(x) (((uint32_t)(((uint32_t)(x)) << USART_BRG_BRGVAL_SHIFT)) & USART_BRG_BRGVAL_MASK) +/*! @} */ /*! @name INTSTAT - Interrupt status register. Reflects interrupts that are currently enabled. */ +/*! @{ */ #define USART_INTSTAT_TXIDLE_MASK (0x8U) #define USART_INTSTAT_TXIDLE_SHIFT (3U) #define USART_INTSTAT_TXIDLE(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_TXIDLE_SHIFT)) & USART_INTSTAT_TXIDLE_MASK) @@ -5693,18 +6278,24 @@ typedef struct { #define USART_INTSTAT_ABERRINT_MASK (0x10000U) #define USART_INTSTAT_ABERRINT_SHIFT (16U) #define USART_INTSTAT_ABERRINT(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_ABERRINT_SHIFT)) & USART_INTSTAT_ABERRINT_MASK) +/*! @} */ /*! @name OSR - Oversample selection register for asynchronous communication. */ +/*! @{ */ #define USART_OSR_OSRVAL_MASK (0xFU) #define USART_OSR_OSRVAL_SHIFT (0U) #define USART_OSR_OSRVAL(x) (((uint32_t)(((uint32_t)(x)) << USART_OSR_OSRVAL_SHIFT)) & USART_OSR_OSRVAL_MASK) +/*! @} */ /*! @name ADDR - Address register for automatic address matching. */ +/*! @{ */ #define USART_ADDR_ADDRESS_MASK (0xFFU) #define USART_ADDR_ADDRESS_SHIFT (0U) #define USART_ADDR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << USART_ADDR_ADDRESS_SHIFT)) & USART_ADDR_ADDRESS_MASK) +/*! @} */ /*! @name FIFOCFG - FIFO configuration and enable register. */ +/*! @{ */ #define USART_FIFOCFG_ENABLETX_MASK (0x1U) #define USART_FIFOCFG_ENABLETX_SHIFT (0U) #define USART_FIFOCFG_ENABLETX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_ENABLETX_SHIFT)) & USART_FIFOCFG_ENABLETX_MASK) @@ -5732,8 +6323,10 @@ typedef struct { #define USART_FIFOCFG_EMPTYRX_MASK (0x20000U) #define USART_FIFOCFG_EMPTYRX_SHIFT (17U) #define USART_FIFOCFG_EMPTYRX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_EMPTYRX_SHIFT)) & USART_FIFOCFG_EMPTYRX_MASK) +/*! @} */ /*! @name FIFOSTAT - FIFO status register. */ +/*! @{ */ #define USART_FIFOSTAT_TXERR_MASK (0x1U) #define USART_FIFOSTAT_TXERR_SHIFT (0U) #define USART_FIFOSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_TXERR_SHIFT)) & USART_FIFOSTAT_TXERR_MASK) @@ -5761,8 +6354,10 @@ typedef struct { #define USART_FIFOSTAT_RXLVL_MASK (0x1F0000U) #define USART_FIFOSTAT_RXLVL_SHIFT (16U) #define USART_FIFOSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_RXLVL_SHIFT)) & USART_FIFOSTAT_RXLVL_MASK) +/*! @} */ /*! @name FIFOTRIG - FIFO trigger settings for interrupt and DMA request. */ +/*! @{ */ #define USART_FIFOTRIG_TXLVLENA_MASK (0x1U) #define USART_FIFOTRIG_TXLVLENA_SHIFT (0U) #define USART_FIFOTRIG_TXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOTRIG_TXLVLENA_SHIFT)) & USART_FIFOTRIG_TXLVLENA_MASK) @@ -5775,8 +6370,10 @@ typedef struct { #define USART_FIFOTRIG_RXLVL_MASK (0xF0000U) #define USART_FIFOTRIG_RXLVL_SHIFT (16U) #define USART_FIFOTRIG_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOTRIG_RXLVL_SHIFT)) & USART_FIFOTRIG_RXLVL_MASK) +/*! @} */ /*! @name FIFOINTENSET - FIFO interrupt enable set (enable) and read register. */ +/*! @{ */ #define USART_FIFOINTENSET_TXERR_MASK (0x1U) #define USART_FIFOINTENSET_TXERR_SHIFT (0U) #define USART_FIFOINTENSET_TXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENSET_TXERR_SHIFT)) & USART_FIFOINTENSET_TXERR_MASK) @@ -5789,8 +6386,10 @@ typedef struct { #define USART_FIFOINTENSET_RXLVL_MASK (0x8U) #define USART_FIFOINTENSET_RXLVL_SHIFT (3U) #define USART_FIFOINTENSET_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENSET_RXLVL_SHIFT)) & USART_FIFOINTENSET_RXLVL_MASK) +/*! @} */ /*! @name FIFOINTENCLR - FIFO interrupt enable clear (disable) and read register. */ +/*! @{ */ #define USART_FIFOINTENCLR_TXERR_MASK (0x1U) #define USART_FIFOINTENCLR_TXERR_SHIFT (0U) #define USART_FIFOINTENCLR_TXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENCLR_TXERR_SHIFT)) & USART_FIFOINTENCLR_TXERR_MASK) @@ -5803,8 +6402,10 @@ typedef struct { #define USART_FIFOINTENCLR_RXLVL_MASK (0x8U) #define USART_FIFOINTENCLR_RXLVL_SHIFT (3U) #define USART_FIFOINTENCLR_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENCLR_RXLVL_SHIFT)) & USART_FIFOINTENCLR_RXLVL_MASK) +/*! @} */ /*! @name FIFOINTSTAT - FIFO interrupt status register. */ +/*! @{ */ #define USART_FIFOINTSTAT_TXERR_MASK (0x1U) #define USART_FIFOINTSTAT_TXERR_SHIFT (0U) #define USART_FIFOINTSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_TXERR_SHIFT)) & USART_FIFOINTSTAT_TXERR_MASK) @@ -5820,13 +6421,17 @@ typedef struct { #define USART_FIFOINTSTAT_PERINT_MASK (0x10U) #define USART_FIFOINTSTAT_PERINT_SHIFT (4U) #define USART_FIFOINTSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_PERINT_SHIFT)) & USART_FIFOINTSTAT_PERINT_MASK) +/*! @} */ /*! @name FIFOWR - FIFO write data. */ +/*! @{ */ #define USART_FIFOWR_TXDATA_MASK (0x1FFU) #define USART_FIFOWR_TXDATA_SHIFT (0U) #define USART_FIFOWR_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOWR_TXDATA_SHIFT)) & USART_FIFOWR_TXDATA_MASK) +/*! @} */ /*! @name FIFORD - FIFO read data. */ +/*! @{ */ #define USART_FIFORD_RXDATA_MASK (0x1FFU) #define USART_FIFORD_RXDATA_SHIFT (0U) #define USART_FIFORD_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORD_RXDATA_SHIFT)) & USART_FIFORD_RXDATA_MASK) @@ -5839,8 +6444,10 @@ typedef struct { #define USART_FIFORD_RXNOISE_MASK (0x8000U) #define USART_FIFORD_RXNOISE_SHIFT (15U) #define USART_FIFORD_RXNOISE(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORD_RXNOISE_SHIFT)) & USART_FIFORD_RXNOISE_MASK) +/*! @} */ /*! @name FIFORDNOPOP - FIFO data read with no FIFO pop. */ +/*! @{ */ #define USART_FIFORDNOPOP_RXDATA_MASK (0x1FFU) #define USART_FIFORDNOPOP_RXDATA_SHIFT (0U) #define USART_FIFORDNOPOP_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORDNOPOP_RXDATA_SHIFT)) & USART_FIFORDNOPOP_RXDATA_MASK) @@ -5853,6 +6460,7 @@ typedef struct { #define USART_FIFORDNOPOP_RXNOISE_MASK (0x8000U) #define USART_FIFORDNOPOP_RXNOISE_SHIFT (15U) #define USART_FIFORDNOPOP_RXNOISE(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORDNOPOP_RXNOISE_SHIFT)) & USART_FIFORDNOPOP_RXNOISE_MASK) +/*! @} */ /*! @@ -5941,6 +6549,7 @@ typedef struct { */ /*! @name DEVCMDSTAT - USB Device Command/Status register */ +/*! @{ */ #define USB_DEVCMDSTAT_DEV_ADDR_MASK (0x7FU) #define USB_DEVCMDSTAT_DEV_ADDR_SHIFT (0U) #define USB_DEVCMDSTAT_DEV_ADDR(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DEV_ADDR_SHIFT)) & USB_DEVCMDSTAT_DEV_ADDR_MASK) @@ -5992,26 +6601,34 @@ typedef struct { #define USB_DEVCMDSTAT_VBUSDEBOUNCED_MASK (0x10000000U) #define USB_DEVCMDSTAT_VBUSDEBOUNCED_SHIFT (28U) #define USB_DEVCMDSTAT_VBUSDEBOUNCED(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_VBUSDEBOUNCED_SHIFT)) & USB_DEVCMDSTAT_VBUSDEBOUNCED_MASK) +/*! @} */ /*! @name INFO - USB Info register */ +/*! @{ */ #define USB_INFO_FRAME_NR_MASK (0x7FFU) #define USB_INFO_FRAME_NR_SHIFT (0U) #define USB_INFO_FRAME_NR(x) (((uint32_t)(((uint32_t)(x)) << USB_INFO_FRAME_NR_SHIFT)) & USB_INFO_FRAME_NR_MASK) #define USB_INFO_ERR_CODE_MASK (0x7800U) #define USB_INFO_ERR_CODE_SHIFT (11U) #define USB_INFO_ERR_CODE(x) (((uint32_t)(((uint32_t)(x)) << USB_INFO_ERR_CODE_SHIFT)) & USB_INFO_ERR_CODE_MASK) +/*! @} */ /*! @name EPLISTSTART - USB EP Command/Status List start address */ +/*! @{ */ #define USB_EPLISTSTART_EP_LIST_MASK (0xFFFFFF00U) #define USB_EPLISTSTART_EP_LIST_SHIFT (8U) #define USB_EPLISTSTART_EP_LIST(x) (((uint32_t)(((uint32_t)(x)) << USB_EPLISTSTART_EP_LIST_SHIFT)) & USB_EPLISTSTART_EP_LIST_MASK) +/*! @} */ /*! @name DATABUFSTART - USB Data buffer start address */ +/*! @{ */ #define USB_DATABUFSTART_DA_BUF_MASK (0xFFC00000U) #define USB_DATABUFSTART_DA_BUF_SHIFT (22U) #define USB_DATABUFSTART_DA_BUF(x) (((uint32_t)(((uint32_t)(x)) << USB_DATABUFSTART_DA_BUF_SHIFT)) & USB_DATABUFSTART_DA_BUF_MASK) +/*! @} */ /*! @name LPM - USB Link Power Management register */ +/*! @{ */ #define USB_LPM_HIRD_HW_MASK (0xFU) #define USB_LPM_HIRD_HW_SHIFT (0U) #define USB_LPM_HIRD_HW(x) (((uint32_t)(((uint32_t)(x)) << USB_LPM_HIRD_HW_SHIFT)) & USB_LPM_HIRD_HW_MASK) @@ -6021,23 +6638,31 @@ typedef struct { #define USB_LPM_DATA_PENDING_MASK (0x100U) #define USB_LPM_DATA_PENDING_SHIFT (8U) #define USB_LPM_DATA_PENDING(x) (((uint32_t)(((uint32_t)(x)) << USB_LPM_DATA_PENDING_SHIFT)) & USB_LPM_DATA_PENDING_MASK) +/*! @} */ /*! @name EPSKIP - USB Endpoint skip */ +/*! @{ */ #define USB_EPSKIP_SKIP_MASK (0x3FFFFFFFU) #define USB_EPSKIP_SKIP_SHIFT (0U) #define USB_EPSKIP_SKIP(x) (((uint32_t)(((uint32_t)(x)) << USB_EPSKIP_SKIP_SHIFT)) & USB_EPSKIP_SKIP_MASK) +/*! @} */ /*! @name EPINUSE - USB Endpoint Buffer in use */ +/*! @{ */ #define USB_EPINUSE_BUF_MASK (0x3FCU) #define USB_EPINUSE_BUF_SHIFT (2U) #define USB_EPINUSE_BUF(x) (((uint32_t)(((uint32_t)(x)) << USB_EPINUSE_BUF_SHIFT)) & USB_EPINUSE_BUF_MASK) +/*! @} */ /*! @name EPBUFCFG - USB Endpoint Buffer Configuration register */ +/*! @{ */ #define USB_EPBUFCFG_BUF_SB_MASK (0x3FCU) #define USB_EPBUFCFG_BUF_SB_SHIFT (2U) #define USB_EPBUFCFG_BUF_SB(x) (((uint32_t)(((uint32_t)(x)) << USB_EPBUFCFG_BUF_SB_SHIFT)) & USB_EPBUFCFG_BUF_SB_MASK) +/*! @} */ /*! @name INTSTAT - USB interrupt status register */ +/*! @{ */ #define USB_INTSTAT_EP0OUT_MASK (0x1U) #define USB_INTSTAT_EP0OUT_SHIFT (0U) #define USB_INTSTAT_EP0OUT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP0OUT_SHIFT)) & USB_INTSTAT_EP0OUT_MASK) @@ -6074,8 +6699,10 @@ typedef struct { #define USB_INTSTAT_DEV_INT_MASK (0x80000000U) #define USB_INTSTAT_DEV_INT_SHIFT (31U) #define USB_INTSTAT_DEV_INT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_DEV_INT_SHIFT)) & USB_INTSTAT_DEV_INT_MASK) +/*! @} */ /*! @name INTEN - USB interrupt enable register */ +/*! @{ */ #define USB_INTEN_EP_INT_EN_MASK (0x3FFU) #define USB_INTEN_EP_INT_EN_SHIFT (0U) #define USB_INTEN_EP_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTEN_EP_INT_EN_SHIFT)) & USB_INTEN_EP_INT_EN_MASK) @@ -6085,8 +6712,10 @@ typedef struct { #define USB_INTEN_DEV_INT_EN_MASK (0x80000000U) #define USB_INTEN_DEV_INT_EN_SHIFT (31U) #define USB_INTEN_DEV_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTEN_DEV_INT_EN_SHIFT)) & USB_INTEN_DEV_INT_EN_MASK) +/*! @} */ /*! @name INTSETSTAT - USB set interrupt status register */ +/*! @{ */ #define USB_INTSETSTAT_EP_SET_INT_MASK (0x3FFU) #define USB_INTSETSTAT_EP_SET_INT_SHIFT (0U) #define USB_INTSETSTAT_EP_SET_INT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSETSTAT_EP_SET_INT_SHIFT)) & USB_INTSETSTAT_EP_SET_INT_MASK) @@ -6096,11 +6725,14 @@ typedef struct { #define USB_INTSETSTAT_DEV_SET_INT_MASK (0x80000000U) #define USB_INTSETSTAT_DEV_SET_INT_SHIFT (31U) #define USB_INTSETSTAT_DEV_SET_INT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSETSTAT_DEV_SET_INT_SHIFT)) & USB_INTSETSTAT_DEV_SET_INT_MASK) +/*! @} */ /*! @name EPTOGGLE - USB Endpoint toggle register */ +/*! @{ */ #define USB_EPTOGGLE_TOGGLE_MASK (0x3FFU) #define USB_EPTOGGLE_TOGGLE_SHIFT (0U) #define USB_EPTOGGLE_TOGGLE(x) (((uint32_t)(((uint32_t)(x)) << USB_EPTOGGLE_TOGGLE_SHIFT)) & USB_EPTOGGLE_TOGGLE_MASK) +/*! @} */ /*! @@ -6154,22 +6786,27 @@ typedef struct { */ /*! @name CTRL - Control register. */ +/*! @{ */ #define UTICK_CTRL_DELAYVAL_MASK (0x7FFFFFFFU) #define UTICK_CTRL_DELAYVAL_SHIFT (0U) #define UTICK_CTRL_DELAYVAL(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CTRL_DELAYVAL_SHIFT)) & UTICK_CTRL_DELAYVAL_MASK) #define UTICK_CTRL_REPEAT_MASK (0x80000000U) #define UTICK_CTRL_REPEAT_SHIFT (31U) #define UTICK_CTRL_REPEAT(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CTRL_REPEAT_SHIFT)) & UTICK_CTRL_REPEAT_MASK) +/*! @} */ /*! @name STAT - Status register. */ +/*! @{ */ #define UTICK_STAT_INTR_MASK (0x1U) #define UTICK_STAT_INTR_SHIFT (0U) #define UTICK_STAT_INTR(x) (((uint32_t)(((uint32_t)(x)) << UTICK_STAT_INTR_SHIFT)) & UTICK_STAT_INTR_MASK) #define UTICK_STAT_ACTIVE_MASK (0x2U) #define UTICK_STAT_ACTIVE_SHIFT (1U) #define UTICK_STAT_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << UTICK_STAT_ACTIVE_SHIFT)) & UTICK_STAT_ACTIVE_MASK) +/*! @} */ /*! @name CFG - Capture configuration register. */ +/*! @{ */ #define UTICK_CFG_CAPEN0_MASK (0x1U) #define UTICK_CFG_CAPEN0_SHIFT (0U) #define UTICK_CFG_CAPEN0(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN0_SHIFT)) & UTICK_CFG_CAPEN0_MASK) @@ -6194,8 +6831,10 @@ typedef struct { #define UTICK_CFG_CAPPOL3_MASK (0x800U) #define UTICK_CFG_CAPPOL3_SHIFT (11U) #define UTICK_CFG_CAPPOL3(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL3_SHIFT)) & UTICK_CFG_CAPPOL3_MASK) +/*! @} */ /*! @name CAPCLR - Capture clear register. */ +/*! @{ */ #define UTICK_CAPCLR_CAPCLR0_MASK (0x1U) #define UTICK_CAPCLR_CAPCLR0_SHIFT (0U) #define UTICK_CAPCLR_CAPCLR0(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR0_SHIFT)) & UTICK_CAPCLR_CAPCLR0_MASK) @@ -6208,14 +6847,17 @@ typedef struct { #define UTICK_CAPCLR_CAPCLR3_MASK (0x8U) #define UTICK_CAPCLR_CAPCLR3_SHIFT (3U) #define UTICK_CAPCLR_CAPCLR3(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR3_SHIFT)) & UTICK_CAPCLR_CAPCLR3_MASK) +/*! @} */ /*! @name CAP - Capture register . */ +/*! @{ */ #define UTICK_CAP_CAP_VALUE_MASK (0x7FFFFFFFU) #define UTICK_CAP_CAP_VALUE_SHIFT (0U) #define UTICK_CAP_CAP_VALUE(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAP_CAP_VALUE_SHIFT)) & UTICK_CAP_CAP_VALUE_MASK) #define UTICK_CAP_VALID_MASK (0x80000000U) #define UTICK_CAP_VALID_SHIFT (31U) #define UTICK_CAP_VALID(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAP_VALID_SHIFT)) & UTICK_CAP_VALID_MASK) +/*! @} */ /* The count of UTICK_CAP */ #define UTICK_CAP_COUNT (4U) @@ -6273,6 +6915,7 @@ typedef struct { */ /*! @name MOD - Watchdog mode register. This register contains the basic mode and status of the Watchdog Timer. */ +/*! @{ */ #define WWDT_MOD_WDEN_MASK (0x1U) #define WWDT_MOD_WDEN_SHIFT (0U) #define WWDT_MOD_WDEN(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDEN_SHIFT)) & WWDT_MOD_WDEN_MASK) @@ -6291,31 +6934,42 @@ typedef struct { #define WWDT_MOD_LOCK_MASK (0x20U) #define WWDT_MOD_LOCK_SHIFT (5U) #define WWDT_MOD_LOCK(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_LOCK_SHIFT)) & WWDT_MOD_LOCK_MASK) +/*! @} */ /*! @name TC - Watchdog timer constant register. This 24-bit register determines the time-out value. */ +/*! @{ */ #define WWDT_TC_COUNT_MASK (0xFFFFFFU) #define WWDT_TC_COUNT_SHIFT (0U) #define WWDT_TC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_TC_COUNT_SHIFT)) & WWDT_TC_COUNT_MASK) +/*! @} */ /*! @name FEED - Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in TC. */ +/*! @{ */ #define WWDT_FEED_FEED_MASK (0xFFU) #define WWDT_FEED_FEED_SHIFT (0U) #define WWDT_FEED_FEED(x) (((uint32_t)(((uint32_t)(x)) << WWDT_FEED_FEED_SHIFT)) & WWDT_FEED_FEED_MASK) +/*! @} */ /*! @name TV - Watchdog timer value register. This 24-bit register reads out the current value of the Watchdog timer. */ +/*! @{ */ #define WWDT_TV_COUNT_MASK (0xFFFFFFU) #define WWDT_TV_COUNT_SHIFT (0U) #define WWDT_TV_COUNT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_TV_COUNT_SHIFT)) & WWDT_TV_COUNT_MASK) +/*! @} */ /*! @name WARNINT - Watchdog Warning Interrupt compare value. */ +/*! @{ */ #define WWDT_WARNINT_WARNINT_MASK (0x3FFU) #define WWDT_WARNINT_WARNINT_SHIFT (0U) #define WWDT_WARNINT_WARNINT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_WARNINT_WARNINT_SHIFT)) & WWDT_WARNINT_WARNINT_MASK) +/*! @} */ /*! @name WINDOW - Watchdog Window compare value. */ +/*! @{ */ #define WWDT_WINDOW_WINDOW_MASK (0xFFFFFFU) #define WWDT_WINDOW_WINDOW_SHIFT (0U) #define WWDT_WINDOW_WINDOW(x) (((uint32_t)(((uint32_t)(x)) << WWDT_WINDOW_WINDOW_SHIFT)) & WWDT_WINDOW_WINDOW_MASK) +/*! @} */ /*! @@ -6345,7 +6999,11 @@ typedef struct { */ #if defined(__ARMCC_VERSION) - #pragma pop + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop + #else + #pragma pop + #endif #elif defined(__GNUC__) /* leave anonymous unions enabled */ #elif defined(__IAR_SYSTEMS_ICC__) diff --git a/ext/hal/nxp/mcux/devices/LPC54114/LPC54114_cm0plus.xml b/ext/hal/nxp/mcux/devices/LPC54114/LPC54114_cm0plus.xml index 8cdfdd8e7d3..c7c55984bf4 100644 --- a/ext/hal/nxp/mcux/devices/LPC54114/LPC54114_cm0plus.xml +++ b/ext/hal/nxp/mcux/devices/LPC54114/LPC54114_cm0plus.xml @@ -1,9 +1,35 @@ - + nxp.com LPC54114_cm0plus 1.0 - LPC54114J256BD64, LPC54114J256UK49, LPC54113J256BD64, LPC54113J256UK49, LPC54113J128BD64 + LPC54114J256BD64,LPC54114J256UK49 + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +1. Redistributions of source code must retain the above copyright notice, this list + of conditions and the following disclaimer. + +2. Redistributions in binary form must reproduce the above copyright notice, this + list of conditions and the following disclaimer in the documentation and/or + other materials provided with the distribution. + +3. Neither the name of the copyright holder nor the names of its + contributors may be used to endorse or promote products derived from this + software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + CM0PLUS r0p0 @@ -56,35 +82,35 @@ PRI_DCODE Cortex M4 D-Code bus priority. - 0x2 + 2 2 read-write PRI_SYS Cortex M4 System bus priority. - 0x4 + 4 2 read-write PRI_M0 Cortex-M0+ bus priority. Present on selected devices. - 0x6 + 6 2 read-write PRI_USB USB interface priority. - 0x8 + 8 2 read-write PRI_DMA DMA controller priority. - 0xA + 10 2 read-write @@ -109,14 +135,14 @@ SKEW Initial value for the Systick timer. - 0x18 + 24 1 read-write NOREF Initial value for the Systick timer. - 0x19 + 25 1 read-write @@ -141,21 +167,21 @@ IRQM0 The IRQ number of the interrupt that acts as the Non-Maskable Interrupt (NMI) for the Cortex-M0+, if enabled by NMIENM0. Present on selected devices. - 0x8 + 8 6 read-write NMIENM0 Write a 1 to this bit to enable the Non-Maskable Interrupt (NMI) source selected by IRQM0. Present on selected devices. - 0x1E + 30 1 read-write NMIENM4 Write a 1 to this bit to enable the Non-Maskable Interrupt (NMI) source selected by IRQM4. - 0x1F + 31 1 read-write @@ -243,84 +269,84 @@ FLASH_RST Flash controller reset control. 0 = Clear reset to this function. 1 = Assert reset to this function. - 0x7 + 7 1 read-write FMC_RST Flash accelerator reset control. Note that the FMC must not be reset while executing from flash, and must be reconfigured after reset. 0 = Clear reset to this function. 1 = Assert reset to this function. - 0x8 + 8 1 read-write MUX_RST Input mux reset control. 0 = Clear reset to this function. 1 = Assert reset to this function. - 0xB + 11 1 read-write IOCON_RST IOCON reset control. 0 = Clear reset to this function. 1 = Assert reset to this function. - 0xD + 13 1 read-write GPIO0_RST GPIO0 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function. - 0xE + 14 1 read-write GPIO1_RST GPIO1 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function. - 0xF + 15 1 read-write PINT_RST Pin interrupt (PINT) reset control. 0 = Clear reset to this function. 1 = Assert reset to this function. - 0x12 + 18 1 read-write GINT_RST Grouped interrupt (GINT) reset control. 0 = Clear reset to this function. 1 = Assert reset to this function. - 0x13 + 19 1 read-write DMA0_RST DMA0 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function. - 0x14 + 20 1 read-write CRC_RST CRC generator reset control. 0 = Clear reset to this function. 1 = Assert reset to this function. - 0x15 + 21 1 read-write WWDT_RST Watchdog timer reset control. 0 = Clear reset to this function. 1 = Assert reset to this function. - 0x16 + 22 1 read-write ADC0_RST ADC0 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function. - 0x1B + 27 1 read-write @@ -345,105 +371,105 @@ SCT0_RST State configurable timer 0 (SCT0) reset control. 0 = Clear reset to this function. 1 = Assert reset to this function. - 0x2 + 2 1 read-write UTICK0_RST Micro-tick Timer reset control. 0 = Clear reset to this function. 1 = Assert reset to this function. - 0xA + 10 1 read-write FC0_RST Flexcomm 0 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function. - 0xB + 11 1 read-write FC1_RST Flexcomm 1 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function. - 0xC + 12 1 read-write FC2_RST Flexcomm 2 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function. - 0xD + 13 1 read-write FC3_RST Flexcomm 3 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function. - 0xE + 14 1 read-write FC4_RST Flexcomm 4 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function. - 0xF + 15 1 read-write FC5_RST Flexcomm 5 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function. - 0x10 + 16 1 read-write FC6_RST Flexcomm 6 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function. - 0x11 + 17 1 read-write FC7_RST Flexcomm 7 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function. - 0x12 + 18 1 read-write DMIC0_RST Digital microphone interface reset control. 0 = Clear reset to this function. 1 = Assert reset to this function. - 0x13 + 19 1 read-write CTIMER2_RST CTIMER2 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function - 0x16 + 22 1 read-write USB0_RST USB0 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function. - 0x19 + 25 1 read-write CTIMER0_RST CTIMER0 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function. - 0x1A + 26 1 read-write CTIMER1_RST CTIMER1 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function. - 0x1B + 27 1 read-write @@ -520,7 +546,7 @@ EXTRST Status of the external RESET pin. External reset status - 0x1 + 1 1 read-write @@ -539,7 +565,7 @@ WDT Status of the Watchdog reset - 0x2 + 2 1 read-write @@ -558,7 +584,7 @@ BOD Status of the Brown-out detect reset - 0x3 + 3 1 read-write @@ -577,7 +603,7 @@ SYSRST Status of the software system reset - 0x4 + 4 1 read-write @@ -607,119 +633,119 @@ ROM Enables the clock for the Boot ROM. 0 = Disable; 1 = Enable. - 0x1 + 1 1 read-write SRAM1 Enables the clock for SRAM1. 0 = Disable; 1 = Enable. - 0x3 + 3 1 read-write SRAM2 Enables the clock for SRAM2. 0 = Disable; 1 = Enable. - 0x4 + 4 1 read-write FLASH Enables the clock for the flash controller. 0 = Disable; 1 = Enable. This clock is needed for flash programming, not for flash read. - 0x7 + 7 1 read-write FMC Enables the clock for the Flash accelerator. 0 = Disable; 1 = Enable. This clock is needed if the flash is being read. - 0x8 + 8 1 read-write INPUTMUX Enables the clock for the input muxes. 0 = Disable; 1 = Enable. - 0xB + 11 1 read-write IOCON Enables the clock for the IOCON block. 0 = Disable; 1 = Enable. - 0xD + 13 1 read-write GPIO0 Enables the clock for the GPIO0 port registers. 0 = Disable; 1 = Enable. - 0xE + 14 1 read-write GPIO1 Enables the clock for the GPIO1 port registers. 0 = Disable; 1 = Enable. - 0xF + 15 1 read-write PINT Enables the clock for the pin interrupt block.0 = Disable; 1 = Enable. - 0x12 + 18 1 read-write GINT Enables the clock for the grouped pin interrupt block. 0 = Disable; 1 = Enable. - 0x13 + 19 1 read-write DMA0 Enables the clock for the DMA0 controller. 0 = Disable; 1 = Enable. - 0x14 + 20 1 read-write CRC Enables the clock for the CRC engine. 0 = Disable; 1 = Enable. - 0x15 + 21 1 read-write WWDT Enables the clock for the Watchdog Timer. 0 = Disable; 1 = Enable. - 0x16 + 22 1 read-write RTC Enables the bus clock for the RTC. 0 = Disable; 1 = Enable. - 0x17 + 23 1 read-write MAILBOX Enables the clock for the Mailbox. 0 = Disable; 1 = Enable. Present on selected devices - 0x1A + 26 1 read-write ADC0 Enables the clock for the ADC0 register interface. 0 = Disable; 1 = Enable. - 0x1B + 27 1 read-write @@ -744,105 +770,105 @@ SCT0 Enables the clock for SCT0. 0 = Disable; 1 = Enable. - 0x2 + 2 1 read-write UTICK0 Enables the clock for the Micro-tick Timer. 0 = Disable; 1 = Enable. - 0xA + 10 1 read-write FLEXCOMM0 Enables the clock for Flexcomm 0. 0 = Disable; 1 = Enable. - 0xB + 11 1 read-write FLEXCOMM1 Enables the clock for Flexcomm 1. 0 = Disable; 1 = Enable. - 0xC + 12 1 read-write FLEXCOMM2 Enables the clock for Flexcomm 2. 0 = Disable; 1 = Enable. - 0xD + 13 1 read-write FLEXCOMM3 Enables the clock for Flexcomm 3. 0 = Disable; 1 = Enable. - 0xE + 14 1 read-write FLEXCOMM4 Enables the clock for Flexcomm 4. 0 = Disable; 1 = Enable. - 0xF + 15 1 read-write FLEXCOMM5 Enables the clock for Flexcomm 5. 0 = Disable; 1 = Enable. - 0x10 + 16 1 read-write FLEXCOMM6 Enables the clock for Flexcomm 6. 0 = Disable; 1 = Enable. - 0x11 + 17 1 read-write FLEXCOMM7 Enables the clock for Flexcomm 7. 0 = Disable; 1 = Enable. - 0x12 + 18 1 read-write DMIC0 Enables the clock for the digital microphone interface. 0 = Disable; 1 = Enable. - 0x13 + 19 1 read-write CTIMER2 Enables the clock for CTIMER 2. 0 = Disable; 1 = Enable. - 0x16 + 22 1 read-write USB0 Enables the clock for the USB0 interface. 0 = Disable; 1 = Enable. - 0x19 + 25 1 read-write CTIMER0 Enables the clock for timer CTIMER0. 0 = Disable; 1 = Enable. - 0x1A + 26 1 read-write CTIMER1 Enables the clock for timer CTIMER1. 0 = Disable; 1 = Enable. - 0x1B + 27 1 read-write @@ -1399,14 +1425,14 @@ RESET Resets the divider counter. Can be used to make sure a new divider value is used right away rather than completing the previous count. - 0x1D + 29 1 read-write HALT Halts the divider counter. The intent is to allow the divider clock source to be changed without the risk of a glitch at the output. - 0x1E + 30 1 read-write @@ -1418,7 +1444,7 @@ 0x304 32 read-write - 0 + 0x40000000 0x600000FF @@ -1431,14 +1457,14 @@ RESET Resets the divider counter. Can be used to make sure a new divider value is used right away rather than completing the previous count. - 0x1D + 29 1 read-write HALT Halts the divider counter. The intent is to allow the divider clock source to be changed without the risk of a glitch at the output. - 0x1E + 30 1 read-write @@ -1463,14 +1489,14 @@ RESET Resets the divider counter. Can be used to make sure a new divider value is used right away rather than completing the previous count. - 0x1D + 29 1 read-write HALT Halts the divider counter. The intent is to allow the divider clock source to be changed without the risk of a glitch at the output. - 0x1E + 30 1 read-write @@ -1495,14 +1521,14 @@ RESET Resets the divider counter. Can be used to make sure a new divider value is used right away rather than completing the previous count. - 0x1D + 29 1 read-write HALT Halts the divider counter. The intent is to allow the divider clock source to be changed without the risk of a glitch at the output. - 0x1E + 30 1 read-write @@ -1527,14 +1553,14 @@ RESET Resets the divider counter. Can be used to make sure a new divider value is used right away rather than completing the previous count. - 0x1D + 29 1 read-write HALT Halts the divider counter. The intent is to allow the divider clock source to be changed without the risk of a glitch at the output. - 0x1E + 30 1 read-write @@ -1559,14 +1585,14 @@ RESET Resets the divider counter. Can be used to make sure a new divider value is used right away rather than completing the previous count. - 0x1D + 29 1 read-write HALT Halts the divider counter. The intent is to allow the divider clock source to be changed without the risk of a glitch at the output. - 0x1E + 30 1 read-write @@ -1591,14 +1617,14 @@ RESET Resets the divider counter. Can be used to make sure a new divider value is used right away rather than completing the previous count. - 0x1D + 29 1 read-write HALT Halts the divider counter. The intent is to allow the divider clock source to be changed without the risk of a glitch at the output. - 0x1E + 30 1 read-write @@ -1623,7 +1649,7 @@ MULT Numerator of the fractional divider. MULT is equal to the programmed value. - 0x8 + 8 8 read-write @@ -1648,14 +1674,14 @@ RESET Resets the divider counter. Can be used to make sure a new divider value is used right away rather than completing the previous count. - 0x1D + 29 1 read-write HALT Halts the divider counter. The intent is to allow the divider clock source to be changed without the risk of a glitch at the output. - 0x1E + 30 1 read-write @@ -1680,14 +1706,14 @@ RESET Resets the divider counter. Can be used to make sure a new divider value is used right away rather than completing the previous count. - 0x1D + 29 1 read-write HALT Halts the divider counter. The intent is to allow the divider clock source to be changed without the risk of a glitch at the output. - 0x1E + 30 1 read-write @@ -1729,7 +1755,7 @@ DATACFG Data read configuration. This field determines how flash accelerator buffers are used for data accesses. - 0x2 + 2 2 read-write @@ -1753,7 +1779,7 @@ ACCEL Acceleration enable. - 0x4 + 4 1 read-write @@ -1772,7 +1798,7 @@ PREFEN Prefetch enable. - 0x5 + 5 1 read-write @@ -1791,7 +1817,7 @@ PREFOVR Prefetch override. This bit only applies when PREFEN = 1 and a buffered instruction is completing for which the next flash line is not already buffered or being prefetched. - 0x6 + 6 1 read-write @@ -1810,7 +1836,7 @@ FLASHTIM Flash memory access time. The number of system clocks used for flash accesses is equal to FLASHTIM +1. - 0xC + 12 4 read-write @@ -1855,7 +1881,7 @@ POL_CLK USB_NEED_CLK polarity for triggering the USB wake-up interrupt - 0x1 + 1 1 read-write @@ -1922,7 +1948,7 @@ PROG Set this bit to one to initiate a frequency measurement cycle. Hardware clears this bit when the measurement cycle has completed and there is valid capture data in the CAPVAL field (bits 13:0). - 0x1F + 31 1 read-write @@ -1977,7 +2003,7 @@ SEL Select the fro_hf output frequency. This bit can only be changed by software when the WRTRIM bit = 1. Note that the factory trim values are for the 96 MHz FRO only. - 0xE + 14 1 read-write @@ -1996,14 +2022,14 @@ FREQTRIM Frequency trim. Boot code configures this to a device-specific factory trim value for the 96 MHz FRO. If USBCLKADJ = 1, this field is read-only and provides the value resulting from USB rate adjustment. See the USBMODCFG flag regarding reading this field. Application code may adjust this field when USBCLKADJ = 0. A single step of FREQTRIM is roughly equivalent to 0.1% of the selected FRO frequency. - 0x10 + 16 8 read-write USBCLKADJ USB clock adjust mode. - 0x18 + 24 1 read-write @@ -2022,14 +2048,14 @@ USBMODCHG USB Mode value Change flag. When 1, indicates that the USB trim is currently being updated (or is still starting up) and software should wait to read FREQTRIM. Update occurs at most once per millisecond. - 0x19 + 25 1 read-write HSPDCLK High speed clock disable. Allows disabling the highs-speed FRO output if it is not needed. - 0x1E + 30 1 read-write @@ -2048,7 +2074,7 @@ WRTRIM Write Trim value. Must be written to 1 to modify the SEL or TRIM fields, during the same write. This bit always reads as 0. - 0x1F + 31 1 read-write @@ -2060,7 +2086,7 @@ 0x508 32 read-write - 0 + 0xA0 0x3FF @@ -2073,7 +2099,7 @@ FREQSEL Frequency select. Selects the frequency of the oscillator. 0x00 = invalid setting when watchdog oscillator is running 0x01 = 0.4 MHz 0x02 = 0.6 MHz 0x03 = 0.75 MHz 0x04 = 0.9 MHz 0x05 = 1.0 MHz 0x06 = 1.2 MHz 0x07 = 1.3 MHz 0x08 = 1.4 MHz 0x09 = 1.5 MHz 0x0A = 1.6 MHz 0x0B = 1.7 MHz 0x0C = 1.8 MHz 0x0D = 1.9 MHz 0x0E = 2.0 MHz 0x0F = 2.05 MHz 0x10 = 2.1 MHz 0x11 = 2.2 MHz 0x12 = 2.25 MHz 0x13 = 2.3 MHz 0x14 = 2.4 MHz 0x15 = 2.45 MHz 0x16 = 2.5 MHz 0x17 = 2.6 MHz 0x18 = 2.65 MHz 0x19 = 2.7 MHz 0x1A = 2.8 MHz 0x1B = 2.85 MHz 0x1C = 2.9 MHz 0x1D = 2.95 MHz 0x1E = 3.0 MHz 0x1F = 3.05 MHz - 0x5 + 5 5 read-write @@ -2128,21 +2154,21 @@ SELI Bandwidth select I value. - 0x4 + 4 6 read-write SELP Bandwidth select P value - 0xA + 10 5 read-write BYPASS PLL bypass control. - 0xF + 15 1 read-write @@ -2153,7 +2179,7 @@ ENABLED - Bypass enabled. PLL input clock is sent to the PLL post-dividers (default). + Bypass enabled. PLL input clock is sent directly to the PLL output (default). 0x1 @@ -2161,7 +2187,7 @@ BYPASSCCODIV2 Bypass feedback clock divide by 2. - 0x10 + 16 1 read-write @@ -2180,7 +2206,7 @@ UPLIMOFF Disable upper frequency limiter. - 0x11 + 17 1 read-write @@ -2199,7 +2225,7 @@ BANDSEL PLL filter control. Set this bit to one when the spread spectrum controller is disabled or at low frequencies. For spread spectrum mode: SEL_EXT = 0, BANDSEL = 0, and UPLIMOFF = 1. - 0x12 + 18 1 read-write @@ -2218,7 +2244,7 @@ DIRECTI PLL0 direct input enable - 0x13 + 19 1 read-write @@ -2237,7 +2263,7 @@ DIRECTO PLL0 direct output enable. - 0x14 + 20 1 read-write @@ -2292,7 +2318,7 @@ NREQ NDEC reload request. When a 1 is written to this bit, the NDEC value is loaded into the PLL. Must be cleared by software for any subsequent load, or the PLL can be powered down and back up via the PDEN_SYS_PLL bit in the PDRUNCFG register if the NDEC value is changed. - 0xA + 10 1 read-write @@ -2317,7 +2343,7 @@ PREQ PDEC reload request. When a 1 is written to this bit, the PDEC value is loaded into the PLL. Must be cleared by software for any subsequent load, or the PLL can be powered down and back up via the PDEN_SYS_PLL bit in the PDRUNCFG register if the PDEC value is changed. - 0x7 + 7 1 read-write @@ -2342,14 +2368,14 @@ MREQ MDEC reload request. When a 1 is written to this bit, the MDEC value is loaded into the PLL. Must be cleared by software for any subsequent load, or the PLL can be powered down and back up via the PDEN_SYS_PLL bit in the PDRUNCFG register if the MDEC value is changed. - 0x11 + 17 1 read-write SEL_EXT Select spread spectrum mode. Selects the source of the feedback divider value. For normal mode, this must be the value from the MDEC field in this register. For spread spectrum mode: SEL_EXT = 0, BANDSEL = 0, and UPLIMOFF = 1. - 0x12 + 18 1 read-write @@ -2374,35 +2400,35 @@ MDREQ MD reload request. When a 1 is written to this bit, the MD value is loaded into the PLL. This bit is cleared when the load is complete - 0x13 + 19 1 read-write MF Programmable modulation frequency fm = Fref/Nss with Fref = Fin/N 0b000 => Nss = 512 (fm _ 3.9 - 7.8 kHz) 0b001 => Nss _ 384 (fm _ 5.2 - 10.4 kHz) 0b010 => Nss = 256 (fm _ 7.8 - 15.6 kHz) 0b011 => Nss = 128 (fm _ 15.6 - 31.3 kHz) 0b100 => Nss = 64 (fm _ 32.3 - 64.5 kHz) 0b101 => Nss = 32 (fm _ 62.5- 125 kHz) 0b110 => Nss _ 24 (fm _ 83.3- 166.6 kHz) 0b111 => Nss = 16 (fm _ 125- 250 kHz) - 0x14 + 20 3 read-write MR Programmable frequency modulation depth. 0 = no spread. _fmodpk-pk = Fref x k/Fcco = k/MDdec 0b000 -> k = 0 (no spread spectrum) 0b001 => k _ 1 0b010 => k _ 1.5 0b011 => k _ 2 0b100 => k _ 3 0b101 => k _ 4 0b110 => k _ 6 0b111 => k _ 8 - 0x17 + 23 3 read-write MC Modulation waveform control. 0 = no compensation. Compensation for low pass filtering of the PLL to get a triangular modulation at the output of the PLL, giving a flat frequency spectrum. 0b00 => no compensation 0b10 => recommended setting 0b11 => max. compensation - 0x1A + 26 2 read-write PD Spread spectrum power-down. - 0x1C + 28 1 read-write @@ -2421,7 +2447,7 @@ DITHER Select modulation frequency. - 0x1D + 29 1 read-write @@ -2471,140 +2497,140 @@ PDEN_FRO FRO oscillator. 0 = Powered; 1 = Powered down. - 0x4 + 4 1 read-write PD_FLASH Part of flash power control. - 0x5 + 5 1 read-write PDEN_TS Temp sensor. 0 = Powered; 1 = Powered down. - 0x6 + 6 1 read-write PDEN_BOD_RST Brown-out Detect reset. 0 = Powered; 1 = Powered down. - 0x7 + 7 1 read-write PDEN_BOD_INTR Brown-out Detect interrupt. 0 = Powered; 1 = Powered down. - 0x8 + 8 1 read-write PDEN_ADC0 ADC0. 0 = Powered; 1 = Powered down. - 0xA + 10 1 read-write PD_VDDFLASH Part of flash power control. - 0xB + 11 1 read-write LP_VDDFLASH Part of flash power control. - 0xC + 12 1 read-write PDEN_SRAM0 SRAM0. 0 = Powered; 1 = Powered down. - 0xD + 13 1 read-write PDEN_SRAM1 SRAM1. 0 = Powered; 1 = Powered down. - 0xE + 14 1 read-write PDEN_SRAM2 SRAM2. 0 = Powered; 1 = Powered down. - 0xF + 15 1 read-write PDEN_SRAMX SRAMX. 0 = Powered; 1 = Powered down. - 0x10 + 16 1 read-write PDEN_ROM ROM. 0 = Powered; 1 = Powered down. - 0x11 + 17 1 read-write PD_VDDHV_ENA Part of flash power control. - 0x12 + 18 1 read-write PDEN_VDDA Vdda to the ADC, must be enabled for the ADC to work. Also see bit 23. 0 = Powered; 1 = Powered down. - 0x13 + 19 1 read-write PDEN_WDT_OSC Watchdog oscillator. 0 = Powered; 1 = Powered down. - 0x14 + 20 1 read-write PDEN_USB_PHY USB pin interface. 0 = Powered; 1 = Powered down. - 0x15 + 21 1 read-write PDEN_SYS_PLL PLL0. 0 = Powered; 1 = Powered down. - 0x16 + 22 1 read-write PDEN_VREFP Vrefp to the ADC, must be enabled for the ADC to work. Also see bit 19. 0 = Powered; 1 = Powered down. - 0x17 + 23 1 read-write PD_FLASH_BG Part of flash power control. - 0x19 + 25 1 read-write @@ -2622,14 +2648,14 @@ PD_ALT_FLASH_IBG Part of flash power control. - 0x1C + 28 1 read-write SEL_ALT_FLASH_IBG Part of flash power control. - 0x1D + 29 1 read-write @@ -2694,203 +2720,203 @@ DMA0 DMA0 wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. Typically used in sleep mode only since the peripheral clock must be running for it to function. - 0x1 + 1 1 read-write GINT0 Group interrupt 0 wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. - 0x2 + 2 1 read-write GINT1 Group interrupt 1 wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. - 0x3 + 3 1 read-write PIN_INT0 GPIO pin interrupt 0 wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. Not for pattern match. - 0x4 + 4 1 read-write PIN_INT1 GPIO pin interrupt 1 wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. Not for pattern match. - 0x5 + 5 1 read-write PIN_INT2 GPIO pin interrupt 2 wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. Not for pattern match. - 0x6 + 6 1 read-write PIN_INT3 GPIO pin interrupt 3 wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. Not for pattern match. - 0x7 + 7 1 read-write UTICK0 Micro-tick Timer wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. - 0x8 + 8 1 read-write MRT0 Multi-Rate Timer wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. Typically used in sleep mode only since the peripheral clock must be running for it to function. - 0x9 + 9 1 read-write CTIMER0 Standard counter/timer CTIMER0 wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled.Typically used in sleep mode only since the peripheral clock must be running for it to function. - 0xA + 10 1 read-write CTIMER1 Standard counter/timer CTIMER1 wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled.Typically used in sleep mode only since the peripheral clock must be running for it to function. - 0xB + 11 1 read-write SCT0 SCT0 wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled.Typically used in sleep mode only since the peripheral clock must be running for it to function. - 0xC + 12 1 read-write CTIMER3 Standard counter/timer CTIMER3 wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled.Typically used in sleep mode only since the peripheral clock must be running for it to function. - 0xD + 13 1 read-write FLEXCOMM0 Flexcomm0 peripheral interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. - 0xE + 14 1 read-write FLEXCOMM1 Flexcomm1 peripheral interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. - 0xF + 15 1 read-write FLEXCOMM2 Flexcomm2 peripheral interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. - 0x10 + 16 1 read-write FLEXCOMM3 Flexcomm3 peripheral interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. - 0x11 + 17 1 read-write FLEXCOMM4 Flexcomm4 peripheral interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. - 0x12 + 18 1 read-write FLEXCOMM5 Flexcomm5 peripheral interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. - 0x13 + 19 1 read-write FLEXCOMM6 Flexcomm6 peripheral interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. - 0x14 + 20 1 read-write FLEXCOMM7 Flexcomm7 peripheral interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. - 0x15 + 21 1 read-write ADC0_SEQA ADC0 sequence A interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled.Typically used in sleep mode only since the peripheral clock must be running for it to function. - 0x16 + 22 1 read-write ADC0_SEQB ADC0 sequence B interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled.Typically used in sleep mode only since the peripheral clock must be running for it to function. - 0x17 + 23 1 read-write ADC0_THCMP ADC0 threshold and error interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled.Typically used in sleep mode only since the peripheral clock must be running for it to function. - 0x18 + 24 1 read-write DMIC0 Digital microphone interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. - 0x19 + 25 1 read-write USB0_NEEDCLK USB0 activity interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. - 0x1B + 27 1 read-write USB0 USB0 function interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. - 0x1C + 28 1 read-write RTC RTC interrupt alarm and wake-up timer. 0 = Wake-up disabled. 1 = Wake-up enabled. - 0x1D + 29 1 read-write MAILBOX Mailbox interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled.At least one CPU must be running in order for a mailbox interrupt to occur. Present on selected devices. - 0x1F + 31 1 read-write @@ -2915,35 +2941,35 @@ PINT5 GPIO pin interrupt 5 wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. Not for pattern match. - 0x1 + 1 1 read-write PINT6 GPIO pin interrupt 6 wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. Not for pattern match. - 0x2 + 2 1 read-write PINT7 GPIO pin interrupt 7 wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. Not for pattern match. - 0x3 + 3 1 read-write CTIMER2 Standard counter/timer CTIMER2 wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled.Typically used in sleep mode only since the peripheral clock must be running for it to function. - 0x4 + 4 1 read-write CTIMER4 Standard counter/timer CTIMER4 wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled.Typically used in sleep mode only since the peripheral clock must be running for it to function. - 0x5 + 5 1 read-write @@ -3008,21 +3034,21 @@ FCWAKE Wake for Flexcomms. When 1, any Flexcomm FIFO reaching the level specified by its own TXLVL will cause peripheral clocking to wake up temporarily while the related status is asserted. - 0x1 + 1 1 read-write WAKEDMIC Wake for Digital Microphone. When 1, the digital microphone input FIFO reaching the level specified by TRIGLVL of either channel will cause peripheral clocking to wake up temporarily while the related status is asserted. - 0x2 + 2 1 read-write WAKEDMA Wake for DMA. When 1, DMA being busy will cause peripheral clocking to remain running until DMA completes. This is generally used in conjunction with bit 1 and/or 2 in order to prevent peripheral clocking from being shut down as soon as the cause of wake-up is cleared, but before DMA has completed its related activity. - 0x3 + 3 1 read-write @@ -3059,7 +3085,7 @@ CM4CLKEN Cortex-M4 clock enable - 0x2 + 2 1 read-write @@ -3078,7 +3104,7 @@ CM0CLKEN Cortex-M0+ clock enable - 0x3 + 3 1 read-write @@ -3097,7 +3123,7 @@ CM4RSTEN Cortex-M4 reset. - 0x4 + 4 1 read-write @@ -3116,7 +3142,7 @@ CM0RSTEN Cortex-M0+ reset. - 0x5 + 5 1 read-write @@ -3135,7 +3161,7 @@ POWERCPU Identifies the owner of reduced power mode control: which CPU can cause the device to enter Deep Sleep, Power-down, and Deep Power-down modes. - 0x6 + 6 1 read-write @@ -3208,21 +3234,21 @@ CM0SLEEPING When 1, the Cortex-M0+ CPU is sleeping - 0x1 + 1 1 read-only CM4LOCKUP When 1, the Cortex-M4 CPU is in lockup - 0x2 + 2 1 read-only CM0LOCKUP When 1, the Cortex-M0+ CPU is in lockup. - 0x3 + 3 1 read-only @@ -3240,21 +3266,21 @@ RAM0X When 1, automatic clock gating for RAMX and RAM0 are turned off. - 0x1 + 1 1 read-write RAM1 When 1, automatic clock gating for RAM1 is turned off. - 0x2 + 2 1 read-write RAM2 When 1, automatic clock gating for RAM2 is turned off. - 0x3 + 3 1 read-write @@ -3355,7 +3381,7 @@ BODRSTENA BOD reset enable - 0x2 + 2 1 read-write @@ -3374,7 +3400,7 @@ BODINTLEV BOD interrupt level - 0x3 + 3 2 read-write @@ -3403,7 +3429,7 @@ BODINTENA BOD interrupt enable - 0x5 + 5 1 read-write @@ -3422,14 +3448,14 @@ BODRSTSTAT BOD reset status. When 1, a BOD reset has occurred. Cleared by writing 1 to this bit. - 0x6 + 6 1 read-write BODINTSTAT BOD interrupt status. When 1, a BOD interrupt has occurred. Cleared by writing 1 to this bit. - 0x7 + 7 1 read-write @@ -3509,7 +3535,7 @@ MODE Selects function mode (on-chip pull-up/pull-down resistor control). - 0x3 + 3 2 read-write @@ -3538,7 +3564,7 @@ INVERT Input polarity. - 0x6 + 6 1 read-write @@ -3557,7 +3583,7 @@ DIGIMODE Select Analog/Digital mode. - 0x7 + 7 1 read-write @@ -3576,7 +3602,7 @@ FILTEROFF Controls input glitch filter. - 0x8 + 8 1 read-write @@ -3595,7 +3621,7 @@ SLEW Driver slew rate. - 0x9 + 9 1 read-write @@ -3614,7 +3640,7 @@ OD Controls open-drain mode. - 0xA + 10 1 read-write @@ -3693,7 +3719,7 @@ MODE Selects function mode (on-chip pull-up/pull-down resistor control). - 0x3 + 3 2 read-write @@ -3722,7 +3748,7 @@ INVERT Input polarity. - 0x6 + 6 1 read-write @@ -3741,7 +3767,7 @@ DIGIMODE Select Analog/Digital mode. - 0x7 + 7 1 read-write @@ -3760,7 +3786,7 @@ FILTEROFF Controls input glitch filter. - 0x8 + 8 1 read-write @@ -3779,7 +3805,7 @@ SLEW Driver slew rate. - 0x9 + 9 1 read-write @@ -3798,7 +3824,7 @@ OD Controls open-drain mode. - 0xA + 10 1 read-write @@ -3877,7 +3903,7 @@ MODE Selects function mode (on-chip pull-up/pull-down resistor control). - 0x3 + 3 2 read-write @@ -3906,7 +3932,7 @@ INVERT Input polarity. - 0x6 + 6 1 read-write @@ -3925,7 +3951,7 @@ DIGIMODE Select Analog/Digital mode. - 0x7 + 7 1 read-write @@ -3944,7 +3970,7 @@ FILTEROFF Controls input glitch filter. - 0x8 + 8 1 read-write @@ -3963,7 +3989,7 @@ SLEW Driver slew rate. - 0x9 + 9 1 read-write @@ -3982,7 +4008,7 @@ OD Controls open-drain mode. - 0xA + 10 1 read-write @@ -4061,7 +4087,7 @@ MODE Selects function mode (on-chip pull-up/pull-down resistor control). - 0x3 + 3 2 read-write @@ -4090,7 +4116,7 @@ INVERT Input polarity. - 0x6 + 6 1 read-write @@ -4109,7 +4135,7 @@ DIGIMODE Select Analog/Digital mode. - 0x7 + 7 1 read-write @@ -4128,7 +4154,7 @@ FILTEROFF Controls input glitch filter. - 0x8 + 8 1 read-write @@ -4147,7 +4173,7 @@ SLEW Driver slew rate. - 0x9 + 9 1 read-write @@ -4166,7 +4192,7 @@ OD Controls open-drain mode. - 0xA + 10 1 read-write @@ -4245,7 +4271,7 @@ MODE Selects function mode (on-chip pull-up/pull-down resistor control). - 0x3 + 3 2 read-write @@ -4274,7 +4300,7 @@ INVERT Input polarity. - 0x6 + 6 1 read-write @@ -4293,7 +4319,7 @@ DIGIMODE Select Analog/Digital mode. - 0x7 + 7 1 read-write @@ -4312,7 +4338,7 @@ FILTEROFF Controls input glitch filter. - 0x8 + 8 1 read-write @@ -4331,7 +4357,7 @@ SLEW Driver slew rate. - 0x9 + 9 1 read-write @@ -4350,7 +4376,7 @@ OD Controls open-drain mode. - 0xA + 10 1 read-write @@ -4429,7 +4455,7 @@ MODE Selects function mode (on-chip pull-up/pull-down resistor control). - 0x3 + 3 2 read-write @@ -4458,7 +4484,7 @@ INVERT Input polarity. - 0x6 + 6 1 read-write @@ -4477,7 +4503,7 @@ DIGIMODE Select Analog/Digital mode. - 0x7 + 7 1 read-write @@ -4496,7 +4522,7 @@ FILTEROFF Controls input glitch filter. - 0x8 + 8 1 read-write @@ -4515,7 +4541,7 @@ SLEW Driver slew rate. - 0x9 + 9 1 read-write @@ -4534,7 +4560,7 @@ OD Controls open-drain mode. - 0xA + 10 1 read-write @@ -4613,7 +4639,7 @@ MODE Selects function mode (on-chip pull-up/pull-down resistor control). - 0x3 + 3 2 read-write @@ -4642,7 +4668,7 @@ INVERT Input polarity. - 0x6 + 6 1 read-write @@ -4661,7 +4687,7 @@ DIGIMODE Select Analog/Digital mode. - 0x7 + 7 1 read-write @@ -4680,7 +4706,7 @@ FILTEROFF Controls input glitch filter. - 0x8 + 8 1 read-write @@ -4699,7 +4725,7 @@ SLEW Driver slew rate. - 0x9 + 9 1 read-write @@ -4718,7 +4744,7 @@ OD Controls open-drain mode. - 0xA + 10 1 read-write @@ -4797,7 +4823,7 @@ MODE Selects function mode (on-chip pull-up/pull-down resistor control). - 0x3 + 3 2 read-write @@ -4826,7 +4852,7 @@ INVERT Input polarity. - 0x6 + 6 1 read-write @@ -4845,7 +4871,7 @@ DIGIMODE Select Analog/Digital mode. - 0x7 + 7 1 read-write @@ -4864,7 +4890,7 @@ FILTEROFF Controls input glitch filter. - 0x8 + 8 1 read-write @@ -4883,7 +4909,7 @@ SLEW Driver slew rate. - 0x9 + 9 1 read-write @@ -4902,7 +4928,7 @@ OD Controls open-drain mode. - 0xA + 10 1 read-write @@ -4981,7 +5007,7 @@ MODE Selects function mode (on-chip pull-up/pull-down resistor control). - 0x3 + 3 2 read-write @@ -5010,7 +5036,7 @@ INVERT Input polarity. - 0x6 + 6 1 read-write @@ -5029,7 +5055,7 @@ DIGIMODE Select Analog/Digital mode. - 0x7 + 7 1 read-write @@ -5048,7 +5074,7 @@ FILTEROFF Controls input glitch filter. - 0x8 + 8 1 read-write @@ -5067,7 +5093,7 @@ SLEW Driver slew rate. - 0x9 + 9 1 read-write @@ -5086,7 +5112,7 @@ OD Controls open-drain mode. - 0xA + 10 1 read-write @@ -5165,7 +5191,7 @@ MODE Selects function mode (on-chip pull-up/pull-down resistor control). - 0x3 + 3 2 read-write @@ -5194,7 +5220,7 @@ INVERT Input polarity. - 0x6 + 6 1 read-write @@ -5213,7 +5239,7 @@ DIGIMODE Select Analog/Digital mode. - 0x7 + 7 1 read-write @@ -5232,7 +5258,7 @@ FILTEROFF Controls input glitch filter. - 0x8 + 8 1 read-write @@ -5251,7 +5277,7 @@ SLEW Driver slew rate. - 0x9 + 9 1 read-write @@ -5270,7 +5296,7 @@ OD Controls open-drain mode. - 0xA + 10 1 read-write @@ -5349,7 +5375,7 @@ MODE Selects function mode (on-chip pull-up/pull-down resistor control). - 0x3 + 3 2 read-write @@ -5378,7 +5404,7 @@ INVERT Input polarity. - 0x6 + 6 1 read-write @@ -5397,7 +5423,7 @@ DIGIMODE Select Analog/Digital mode. - 0x7 + 7 1 read-write @@ -5416,7 +5442,7 @@ FILTEROFF Controls input glitch filter. - 0x8 + 8 1 read-write @@ -5435,7 +5461,7 @@ SLEW Driver slew rate. - 0x9 + 9 1 read-write @@ -5454,7 +5480,7 @@ OD Controls open-drain mode. - 0xA + 10 1 read-write @@ -5533,7 +5559,7 @@ MODE Selects function mode (on-chip pull-up/pull-down resistor control). - 0x3 + 3 2 read-write @@ -5562,7 +5588,7 @@ INVERT Input polarity. - 0x6 + 6 1 read-write @@ -5581,7 +5607,7 @@ DIGIMODE Select Analog/Digital mode. - 0x7 + 7 1 read-write @@ -5600,7 +5626,7 @@ FILTEROFF Controls input glitch filter. - 0x8 + 8 1 read-write @@ -5619,7 +5645,7 @@ SLEW Driver slew rate. - 0x9 + 9 1 read-write @@ -5638,7 +5664,7 @@ OD Controls open-drain mode. - 0xA + 10 1 read-write @@ -5717,7 +5743,7 @@ MODE Selects function mode (on-chip pull-up/pull-down resistor control). - 0x3 + 3 2 read-write @@ -5746,7 +5772,7 @@ INVERT Input polarity. - 0x6 + 6 1 read-write @@ -5765,7 +5791,7 @@ DIGIMODE Select Analog/Digital mode. - 0x7 + 7 1 read-write @@ -5784,7 +5810,7 @@ FILTEROFF Controls input glitch filter. - 0x8 + 8 1 read-write @@ -5803,7 +5829,7 @@ SLEW Driver slew rate. - 0x9 + 9 1 read-write @@ -5822,7 +5848,7 @@ OD Controls open-drain mode. - 0xA + 10 1 read-write @@ -5901,7 +5927,7 @@ MODE Selects function mode (on-chip pull-up/pull-down resistor control). - 0x3 + 3 2 read-write @@ -5930,7 +5956,7 @@ INVERT Input polarity. - 0x6 + 6 1 read-write @@ -5949,7 +5975,7 @@ DIGIMODE Select Analog/Digital mode. - 0x7 + 7 1 read-write @@ -5968,7 +5994,7 @@ FILTEROFF Controls input glitch filter. - 0x8 + 8 1 read-write @@ -5987,7 +6013,7 @@ SLEW Driver slew rate. - 0x9 + 9 1 read-write @@ -6006,7 +6032,7 @@ OD Controls open-drain mode. - 0xA + 10 1 read-write @@ -6085,7 +6111,7 @@ MODE Selects function mode (on-chip pull-up/pull-down resistor control). - 0x3 + 3 2 read-write @@ -6114,7 +6140,7 @@ INVERT Input polarity. - 0x6 + 6 1 read-write @@ -6133,7 +6159,7 @@ DIGIMODE Select Analog/Digital mode. - 0x7 + 7 1 read-write @@ -6152,7 +6178,7 @@ FILTEROFF Controls input glitch filter. - 0x8 + 8 1 read-write @@ -6171,7 +6197,7 @@ SLEW Driver slew rate. - 0x9 + 9 1 read-write @@ -6190,7 +6216,7 @@ OD Controls open-drain mode. - 0xA + 10 1 read-write @@ -6269,7 +6295,7 @@ MODE Selects function mode (on-chip pull-up/pull-down resistor control). - 0x3 + 3 2 read-write @@ -6298,7 +6324,7 @@ INVERT Input polarity. - 0x6 + 6 1 read-write @@ -6317,7 +6343,7 @@ DIGIMODE Select Analog/Digital mode. - 0x7 + 7 1 read-write @@ -6336,7 +6362,7 @@ FILTEROFF Controls input glitch filter. - 0x8 + 8 1 read-write @@ -6355,7 +6381,7 @@ SLEW Driver slew rate. - 0x9 + 9 1 read-write @@ -6374,7 +6400,7 @@ OD Controls open-drain mode. - 0xA + 10 1 read-write @@ -6453,7 +6479,7 @@ MODE Selects function mode (on-chip pull-up/pull-down resistor control). - 0x3 + 3 2 read-write @@ -6482,7 +6508,7 @@ INVERT Input polarity. - 0x6 + 6 1 read-write @@ -6501,7 +6527,7 @@ DIGIMODE Select Analog/Digital mode. - 0x7 + 7 1 read-write @@ -6520,7 +6546,7 @@ FILTEROFF Controls input glitch filter. - 0x8 + 8 1 read-write @@ -6539,7 +6565,7 @@ SLEW Driver slew rate. - 0x9 + 9 1 read-write @@ -6558,7 +6584,7 @@ OD Controls open-drain mode. - 0xA + 10 1 read-write @@ -6637,7 +6663,7 @@ MODE Selects function mode (on-chip pull-up/pull-down resistor control). - 0x3 + 3 2 read-write @@ -6666,7 +6692,7 @@ INVERT Input polarity. - 0x6 + 6 1 read-write @@ -6685,7 +6711,7 @@ DIGIMODE Select Analog/Digital mode. - 0x7 + 7 1 read-write @@ -6704,7 +6730,7 @@ FILTEROFF Controls input glitch filter. - 0x8 + 8 1 read-write @@ -6723,7 +6749,7 @@ SLEW Driver slew rate. - 0x9 + 9 1 read-write @@ -6742,7 +6768,7 @@ OD Controls open-drain mode. - 0xA + 10 1 read-write @@ -6821,7 +6847,7 @@ MODE Selects function mode (on-chip pull-up/pull-down resistor control). - 0x3 + 3 2 read-write @@ -6850,7 +6876,7 @@ INVERT Input polarity. - 0x6 + 6 1 read-write @@ -6869,7 +6895,7 @@ DIGIMODE Select Analog/Digital mode. - 0x7 + 7 1 read-write @@ -6888,7 +6914,7 @@ FILTEROFF Controls input glitch filter. - 0x8 + 8 1 read-write @@ -6907,7 +6933,7 @@ SLEW Driver slew rate. - 0x9 + 9 1 read-write @@ -6926,7 +6952,7 @@ OD Controls open-drain mode. - 0xA + 10 1 read-write @@ -7005,7 +7031,7 @@ MODE Selects function mode (on-chip pull-up/pull-down resistor control). - 0x3 + 3 2 read-write @@ -7034,7 +7060,7 @@ INVERT Input polarity. - 0x6 + 6 1 read-write @@ -7053,7 +7079,7 @@ DIGIMODE Select Analog/Digital mode. - 0x7 + 7 1 read-write @@ -7072,7 +7098,7 @@ FILTEROFF Controls input glitch filter. - 0x8 + 8 1 read-write @@ -7091,7 +7117,7 @@ SLEW Driver slew rate. - 0x9 + 9 1 read-write @@ -7110,7 +7136,7 @@ OD Controls open-drain mode. - 0xA + 10 1 read-write @@ -7189,7 +7215,7 @@ MODE Selects function mode (on-chip pull-up/pull-down resistor control). - 0x3 + 3 2 read-write @@ -7218,7 +7244,7 @@ INVERT Input polarity. - 0x6 + 6 1 read-write @@ -7237,7 +7263,7 @@ DIGIMODE Select Analog/Digital mode. - 0x7 + 7 1 read-write @@ -7256,7 +7282,7 @@ FILTEROFF Controls input glitch filter. - 0x8 + 8 1 read-write @@ -7275,7 +7301,7 @@ SLEW Driver slew rate. - 0x9 + 9 1 read-write @@ -7294,7 +7320,7 @@ OD Controls open-drain mode. - 0xA + 10 1 read-write @@ -7373,7 +7399,7 @@ MODE Selects function mode (on-chip pull-up/pull-down resistor control). - 0x3 + 3 2 read-write @@ -7402,7 +7428,7 @@ INVERT Input polarity. - 0x6 + 6 1 read-write @@ -7421,7 +7447,7 @@ DIGIMODE Select Analog/Digital mode. - 0x7 + 7 1 read-write @@ -7440,7 +7466,7 @@ FILTEROFF Controls input glitch filter. - 0x8 + 8 1 read-write @@ -7459,7 +7485,7 @@ SLEW Driver slew rate. - 0x9 + 9 1 read-write @@ -7478,7 +7504,7 @@ OD Controls open-drain mode. - 0xA + 10 1 read-write @@ -7557,7 +7583,7 @@ MODE Selects function mode (on-chip pull-up/pull-down resistor control). - 0x3 + 3 2 read-write @@ -7586,7 +7612,7 @@ INVERT Input polarity. - 0x6 + 6 1 read-write @@ -7605,7 +7631,7 @@ DIGIMODE Select Analog/Digital mode. - 0x7 + 7 1 read-write @@ -7624,7 +7650,7 @@ FILTEROFF Controls input glitch filter. - 0x8 + 8 1 read-write @@ -7643,7 +7669,7 @@ SLEW Driver slew rate. - 0x9 + 9 1 read-write @@ -7662,7 +7688,7 @@ OD Controls open-drain mode. - 0xA + 10 1 read-write @@ -7741,7 +7767,7 @@ I2CSLEW Controls slew rate of I2C pad. - 0x5 + 5 1 read-write @@ -7760,7 +7786,7 @@ INVERT Input polarity. - 0x6 + 6 1 read-write @@ -7779,7 +7805,7 @@ DIGIMODE Select Analog/Digital mode. - 0x7 + 7 1 read-write @@ -7798,7 +7824,7 @@ FILTEROFF Controls input glitch filter. - 0x8 + 8 1 read-write @@ -7817,7 +7843,7 @@ I2CDRIVE Controls the current sink capability of the pin. - 0x9 + 9 1 read-write @@ -7836,7 +7862,7 @@ I2CFILTER Configures I2C features for standard mode, fast mode, and Fast Mode Plus operation. - 0xA + 10 1 read-write @@ -7915,7 +7941,7 @@ I2CSLEW Controls slew rate of I2C pad. - 0x5 + 5 1 read-write @@ -7934,7 +7960,7 @@ INVERT Input polarity. - 0x6 + 6 1 read-write @@ -7953,7 +7979,7 @@ DIGIMODE Select Analog/Digital mode. - 0x7 + 7 1 read-write @@ -7972,7 +7998,7 @@ FILTEROFF Controls input glitch filter. - 0x8 + 8 1 read-write @@ -7991,7 +8017,7 @@ I2CDRIVE Controls the current sink capability of the pin. - 0x9 + 9 1 read-write @@ -8010,7 +8036,7 @@ I2CFILTER Configures I2C features for standard mode, fast mode, and Fast Mode Plus operation. - 0xA + 10 1 read-write @@ -8089,7 +8115,7 @@ I2CSLEW Controls slew rate of I2C pad. - 0x5 + 5 1 read-write @@ -8108,7 +8134,7 @@ INVERT Input polarity. - 0x6 + 6 1 read-write @@ -8127,7 +8153,7 @@ DIGIMODE Select Analog/Digital mode. - 0x7 + 7 1 read-write @@ -8146,7 +8172,7 @@ FILTEROFF Controls input glitch filter. - 0x8 + 8 1 read-write @@ -8165,7 +8191,7 @@ I2CDRIVE Controls the current sink capability of the pin. - 0x9 + 9 1 read-write @@ -8184,7 +8210,7 @@ I2CFILTER Configures I2C features for standard mode, fast mode, and Fast Mode Plus operation. - 0xA + 10 1 read-write @@ -8263,7 +8289,7 @@ I2CSLEW Controls slew rate of I2C pad. - 0x5 + 5 1 read-write @@ -8282,7 +8308,7 @@ INVERT Input polarity. - 0x6 + 6 1 read-write @@ -8301,7 +8327,7 @@ DIGIMODE Select Analog/Digital mode. - 0x7 + 7 1 read-write @@ -8320,7 +8346,7 @@ FILTEROFF Controls input glitch filter. - 0x8 + 8 1 read-write @@ -8339,7 +8365,7 @@ I2CDRIVE Controls the current sink capability of the pin. - 0x9 + 9 1 read-write @@ -8358,7 +8384,7 @@ I2CFILTER Configures I2C features for standard mode, fast mode, and Fast Mode Plus operation. - 0xA + 10 1 read-write @@ -8437,7 +8463,7 @@ MODE Selects function mode (on-chip pull-up/pull-down resistor control). - 0x3 + 3 2 read-write @@ -8466,7 +8492,7 @@ INVERT Input polarity. - 0x6 + 6 1 read-write @@ -8485,7 +8511,7 @@ DIGIMODE Select Analog/Digital mode. - 0x7 + 7 1 read-write @@ -8504,7 +8530,7 @@ FILTEROFF Controls input glitch filter. - 0x8 + 8 1 read-write @@ -8523,7 +8549,7 @@ SLEW Driver slew rate. - 0x9 + 9 1 read-write @@ -8542,7 +8568,7 @@ OD Controls open-drain mode. - 0xA + 10 1 read-write @@ -8621,7 +8647,7 @@ MODE Selects function mode (on-chip pull-up/pull-down resistor control). - 0x3 + 3 2 read-write @@ -8650,7 +8676,7 @@ INVERT Input polarity. - 0x6 + 6 1 read-write @@ -8669,7 +8695,7 @@ DIGIMODE Select Analog/Digital mode. - 0x7 + 7 1 read-write @@ -8688,7 +8714,7 @@ FILTEROFF Controls input glitch filter. - 0x8 + 8 1 read-write @@ -8707,7 +8733,7 @@ SLEW Driver slew rate. - 0x9 + 9 1 read-write @@ -8726,7 +8752,7 @@ OD Controls open-drain mode. - 0xA + 10 1 read-write @@ -8805,7 +8831,7 @@ MODE Selects function mode (on-chip pull-up/pull-down resistor control). - 0x3 + 3 2 read-write @@ -8834,7 +8860,7 @@ INVERT Input polarity. - 0x6 + 6 1 read-write @@ -8853,7 +8879,7 @@ DIGIMODE Select Analog/Digital mode. - 0x7 + 7 1 read-write @@ -8872,7 +8898,7 @@ FILTEROFF Controls input glitch filter. - 0x8 + 8 1 read-write @@ -8891,7 +8917,7 @@ OD Controls open-drain mode. - 0xA + 10 1 read-write @@ -8970,7 +8996,7 @@ MODE Selects function mode (on-chip pull-up/pull-down resistor control). - 0x3 + 3 2 read-write @@ -8999,7 +9025,7 @@ INVERT Input polarity. - 0x6 + 6 1 read-write @@ -9018,7 +9044,7 @@ DIGIMODE Select Analog/Digital mode. - 0x7 + 7 1 read-write @@ -9037,7 +9063,7 @@ FILTEROFF Controls input glitch filter. - 0x8 + 8 1 read-write @@ -9056,7 +9082,7 @@ OD Controls open-drain mode. - 0xA + 10 1 read-write @@ -9135,7 +9161,7 @@ MODE Selects function mode (on-chip pull-up/pull-down resistor control). - 0x3 + 3 2 read-write @@ -9164,7 +9190,7 @@ INVERT Input polarity. - 0x6 + 6 1 read-write @@ -9183,7 +9209,7 @@ DIGIMODE Select Analog/Digital mode. - 0x7 + 7 1 read-write @@ -9202,7 +9228,7 @@ FILTEROFF Controls input glitch filter. - 0x8 + 8 1 read-write @@ -9221,7 +9247,7 @@ OD Controls open-drain mode. - 0xA + 10 1 read-write @@ -9300,7 +9326,7 @@ MODE Selects function mode (on-chip pull-up/pull-down resistor control). - 0x3 + 3 2 read-write @@ -9329,7 +9355,7 @@ INVERT Input polarity. - 0x6 + 6 1 read-write @@ -9348,7 +9374,7 @@ DIGIMODE Select Analog/Digital mode. - 0x7 + 7 1 read-write @@ -9367,7 +9393,7 @@ FILTEROFF Controls input glitch filter. - 0x8 + 8 1 read-write @@ -9386,7 +9412,7 @@ OD Controls open-drain mode. - 0xA + 10 1 read-write @@ -9465,7 +9491,7 @@ MODE Selects function mode (on-chip pull-up/pull-down resistor control). - 0x3 + 3 2 read-write @@ -9494,7 +9520,7 @@ INVERT Input polarity. - 0x6 + 6 1 read-write @@ -9513,7 +9539,7 @@ DIGIMODE Select Analog/Digital mode. - 0x7 + 7 1 read-write @@ -9532,7 +9558,7 @@ FILTEROFF Controls input glitch filter. - 0x8 + 8 1 read-write @@ -9551,7 +9577,7 @@ OD Controls open-drain mode. - 0xA + 10 1 read-write @@ -9630,7 +9656,7 @@ MODE Selects function mode (on-chip pull-up/pull-down resistor control). - 0x3 + 3 2 read-write @@ -9659,7 +9685,7 @@ INVERT Input polarity. - 0x6 + 6 1 read-write @@ -9678,7 +9704,7 @@ DIGIMODE Select Analog/Digital mode. - 0x7 + 7 1 read-write @@ -9697,7 +9723,7 @@ FILTEROFF Controls input glitch filter. - 0x8 + 8 1 read-write @@ -9716,7 +9742,7 @@ OD Controls open-drain mode. - 0xA + 10 1 read-write @@ -9795,7 +9821,7 @@ MODE Selects function mode (on-chip pull-up/pull-down resistor control). - 0x3 + 3 2 read-write @@ -9824,7 +9850,7 @@ INVERT Input polarity. - 0x6 + 6 1 read-write @@ -9843,7 +9869,7 @@ DIGIMODE Select Analog/Digital mode. - 0x7 + 7 1 read-write @@ -9862,7 +9888,7 @@ FILTEROFF Controls input glitch filter. - 0x8 + 8 1 read-write @@ -9881,7 +9907,7 @@ OD Controls open-drain mode. - 0xA + 10 1 read-write @@ -9960,7 +9986,7 @@ MODE Selects function mode (on-chip pull-up/pull-down resistor control). - 0x3 + 3 2 read-write @@ -9989,7 +10015,7 @@ INVERT Input polarity. - 0x6 + 6 1 read-write @@ -10008,7 +10034,7 @@ DIGIMODE Select Analog/Digital mode. - 0x7 + 7 1 read-write @@ -10027,7 +10053,7 @@ FILTEROFF Controls input glitch filter. - 0x8 + 8 1 read-write @@ -10046,7 +10072,7 @@ OD Controls open-drain mode. - 0xA + 10 1 read-write @@ -10125,7 +10151,7 @@ MODE Selects function mode (on-chip pull-up/pull-down resistor control). - 0x3 + 3 2 read-write @@ -10154,7 +10180,7 @@ INVERT Input polarity. - 0x6 + 6 1 read-write @@ -10173,7 +10199,7 @@ DIGIMODE Select Analog/Digital mode. - 0x7 + 7 1 read-write @@ -10192,7 +10218,7 @@ FILTEROFF Controls input glitch filter. - 0x8 + 8 1 read-write @@ -10211,7 +10237,7 @@ OD Controls open-drain mode. - 0xA + 10 1 read-write @@ -10290,7 +10316,7 @@ MODE Selects function mode (on-chip pull-up/pull-down resistor control). - 0x3 + 3 2 read-write @@ -10319,7 +10345,7 @@ INVERT Input polarity. - 0x6 + 6 1 read-write @@ -10338,7 +10364,7 @@ DIGIMODE Select Analog/Digital mode. - 0x7 + 7 1 read-write @@ -10357,7 +10383,7 @@ FILTEROFF Controls input glitch filter. - 0x8 + 8 1 read-write @@ -10376,7 +10402,7 @@ OD Controls open-drain mode. - 0xA + 10 1 read-write @@ -10455,7 +10481,7 @@ MODE Selects function mode (on-chip pull-up/pull-down resistor control). - 0x3 + 3 2 read-write @@ -10484,7 +10510,7 @@ INVERT Input polarity. - 0x6 + 6 1 read-write @@ -10503,7 +10529,7 @@ DIGIMODE Select Analog/Digital mode. - 0x7 + 7 1 read-write @@ -10522,7 +10548,7 @@ FILTEROFF Controls input glitch filter. - 0x8 + 8 1 read-write @@ -10541,7 +10567,7 @@ OD Controls open-drain mode. - 0xA + 10 1 read-write @@ -10620,7 +10646,7 @@ MODE Selects function mode (on-chip pull-up/pull-down resistor control). - 0x3 + 3 2 read-write @@ -10649,7 +10675,7 @@ INVERT Input polarity. - 0x6 + 6 1 read-write @@ -10668,7 +10694,7 @@ DIGIMODE Select Analog/Digital mode. - 0x7 + 7 1 read-write @@ -10687,7 +10713,7 @@ FILTEROFF Controls input glitch filter. - 0x8 + 8 1 read-write @@ -10706,7 +10732,7 @@ OD Controls open-drain mode. - 0xA + 10 1 read-write @@ -10785,7 +10811,7 @@ MODE Selects function mode (on-chip pull-up/pull-down resistor control). - 0x3 + 3 2 read-write @@ -10814,7 +10840,7 @@ INVERT Input polarity. - 0x6 + 6 1 read-write @@ -10833,7 +10859,7 @@ DIGIMODE Select Analog/Digital mode. - 0x7 + 7 1 read-write @@ -10852,7 +10878,7 @@ FILTEROFF Controls input glitch filter. - 0x8 + 8 1 read-write @@ -10871,7 +10897,7 @@ SLEW Driver slew rate. - 0x9 + 9 1 read-write @@ -10890,7 +10916,7 @@ OD Controls open-drain mode. - 0xA + 10 1 read-write @@ -10969,7 +10995,7 @@ MODE Selects function mode (on-chip pull-up/pull-down resistor control). - 0x3 + 3 2 read-write @@ -10998,7 +11024,7 @@ INVERT Input polarity. - 0x6 + 6 1 read-write @@ -11017,7 +11043,7 @@ DIGIMODE Select Analog/Digital mode. - 0x7 + 7 1 read-write @@ -11036,7 +11062,7 @@ FILTEROFF Controls input glitch filter. - 0x8 + 8 1 read-write @@ -11055,7 +11081,7 @@ SLEW Driver slew rate. - 0x9 + 9 1 read-write @@ -11074,7 +11100,7 @@ OD Controls open-drain mode. - 0xA + 10 1 read-write @@ -11153,7 +11179,7 @@ MODE Selects function mode (on-chip pull-up/pull-down resistor control). - 0x3 + 3 2 read-write @@ -11182,7 +11208,7 @@ INVERT Input polarity. - 0x6 + 6 1 read-write @@ -11201,7 +11227,7 @@ DIGIMODE Select Analog/Digital mode. - 0x7 + 7 1 read-write @@ -11220,7 +11246,7 @@ FILTEROFF Controls input glitch filter. - 0x8 + 8 1 read-write @@ -11239,7 +11265,7 @@ SLEW Driver slew rate. - 0x9 + 9 1 read-write @@ -11258,7 +11284,7 @@ OD Controls open-drain mode. - 0xA + 10 1 read-write @@ -11337,7 +11363,7 @@ MODE Selects function mode (on-chip pull-up/pull-down resistor control). - 0x3 + 3 2 read-write @@ -11366,7 +11392,7 @@ INVERT Input polarity. - 0x6 + 6 1 read-write @@ -11385,7 +11411,7 @@ DIGIMODE Select Analog/Digital mode. - 0x7 + 7 1 read-write @@ -11404,7 +11430,7 @@ FILTEROFF Controls input glitch filter. - 0x8 + 8 1 read-write @@ -11423,7 +11449,7 @@ SLEW Driver slew rate. - 0x9 + 9 1 read-write @@ -11442,7 +11468,7 @@ OD Controls open-drain mode. - 0xA + 10 1 read-write @@ -11521,7 +11547,7 @@ MODE Selects function mode (on-chip pull-up/pull-down resistor control). - 0x3 + 3 2 read-write @@ -11550,7 +11576,7 @@ INVERT Input polarity. - 0x6 + 6 1 read-write @@ -11569,7 +11595,7 @@ DIGIMODE Select Analog/Digital mode. - 0x7 + 7 1 read-write @@ -11588,7 +11614,7 @@ FILTEROFF Controls input glitch filter. - 0x8 + 8 1 read-write @@ -11607,7 +11633,7 @@ SLEW Driver slew rate. - 0x9 + 9 1 read-write @@ -11626,7 +11652,7 @@ OD Controls open-drain mode. - 0xA + 10 1 read-write @@ -11705,7 +11731,7 @@ MODE Selects function mode (on-chip pull-up/pull-down resistor control). - 0x3 + 3 2 read-write @@ -11734,7 +11760,7 @@ INVERT Input polarity. - 0x6 + 6 1 read-write @@ -11753,7 +11779,7 @@ DIGIMODE Select Analog/Digital mode. - 0x7 + 7 1 read-write @@ -11772,7 +11798,7 @@ FILTEROFF Controls input glitch filter. - 0x8 + 8 1 read-write @@ -11791,7 +11817,7 @@ SLEW Driver slew rate. - 0x9 + 9 1 read-write @@ -11810,7 +11836,7 @@ OD Controls open-drain mode. - 0xA + 10 1 read-write @@ -11889,7 +11915,7 @@ MODE Selects function mode (on-chip pull-up/pull-down resistor control). - 0x3 + 3 2 read-write @@ -11918,7 +11944,7 @@ INVERT Input polarity. - 0x6 + 6 1 read-write @@ -11937,7 +11963,7 @@ DIGIMODE Select Analog/Digital mode. - 0x7 + 7 1 read-write @@ -11956,7 +11982,7 @@ FILTEROFF Controls input glitch filter. - 0x8 + 8 1 read-write @@ -11975,7 +12001,7 @@ SLEW Driver slew rate. - 0x9 + 9 1 read-write @@ -11994,7 +12020,7 @@ OD Controls open-drain mode. - 0xA + 10 1 read-write @@ -12073,7 +12099,7 @@ MODE Selects function mode (on-chip pull-up/pull-down resistor control). - 0x3 + 3 2 read-write @@ -12102,7 +12128,7 @@ INVERT Input polarity. - 0x6 + 6 1 read-write @@ -12121,7 +12147,7 @@ DIGIMODE Select Analog/Digital mode. - 0x7 + 7 1 read-write @@ -12140,7 +12166,7 @@ FILTEROFF Controls input glitch filter. - 0x8 + 8 1 read-write @@ -12159,7 +12185,7 @@ SLEW Driver slew rate. - 0x9 + 9 1 read-write @@ -12178,7 +12204,7 @@ OD Controls open-drain mode. - 0xA + 10 1 read-write @@ -12257,7 +12283,7 @@ MODE Selects function mode (on-chip pull-up/pull-down resistor control). - 0x3 + 3 2 read-write @@ -12286,7 +12312,7 @@ INVERT Input polarity. - 0x6 + 6 1 read-write @@ -12305,7 +12331,7 @@ DIGIMODE Select Analog/Digital mode. - 0x7 + 7 1 read-write @@ -12324,7 +12350,7 @@ FILTEROFF Controls input glitch filter. - 0x8 + 8 1 read-write @@ -12343,7 +12369,7 @@ SLEW Driver slew rate. - 0x9 + 9 1 read-write @@ -12362,7 +12388,7 @@ OD Controls open-drain mode. - 0xA + 10 1 read-write @@ -12441,7 +12467,7 @@ MODE Selects function mode (on-chip pull-up/pull-down resistor control). - 0x3 + 3 2 read-write @@ -12470,7 +12496,7 @@ INVERT Input polarity. - 0x6 + 6 1 read-write @@ -12489,7 +12515,7 @@ DIGIMODE Select Analog/Digital mode. - 0x7 + 7 1 read-write @@ -12508,7 +12534,7 @@ FILTEROFF Controls input glitch filter. - 0x8 + 8 1 read-write @@ -12527,7 +12553,7 @@ SLEW Driver slew rate. - 0x9 + 9 1 read-write @@ -12546,7 +12572,7 @@ OD Controls open-drain mode. - 0xA + 10 1 read-write @@ -12625,7 +12651,7 @@ MODE Selects function mode (on-chip pull-up/pull-down resistor control). - 0x3 + 3 2 read-write @@ -12654,7 +12680,7 @@ INVERT Input polarity. - 0x6 + 6 1 read-write @@ -12673,7 +12699,7 @@ DIGIMODE Select Analog/Digital mode. - 0x7 + 7 1 read-write @@ -12692,7 +12718,7 @@ FILTEROFF Controls input glitch filter. - 0x8 + 8 1 read-write @@ -12711,7 +12737,7 @@ SLEW Driver slew rate. - 0x9 + 9 1 read-write @@ -12730,7 +12756,7 @@ OD Controls open-drain mode. - 0xA + 10 1 read-write @@ -12809,7 +12835,7 @@ MODE Selects function mode (on-chip pull-up/pull-down resistor control). - 0x3 + 3 2 read-write @@ -12838,7 +12864,7 @@ INVERT Input polarity. - 0x6 + 6 1 read-write @@ -12857,7 +12883,7 @@ DIGIMODE Select Analog/Digital mode. - 0x7 + 7 1 read-write @@ -12876,7 +12902,7 @@ FILTEROFF Controls input glitch filter. - 0x8 + 8 1 read-write @@ -12895,7 +12921,7 @@ SLEW Driver slew rate. - 0x9 + 9 1 read-write @@ -12914,7 +12940,7 @@ OD Controls open-drain mode. - 0xA + 10 1 read-write @@ -12993,7 +13019,7 @@ MODE Selects function mode (on-chip pull-up/pull-down resistor control). - 0x3 + 3 2 read-write @@ -13022,7 +13048,7 @@ INVERT Input polarity. - 0x6 + 6 1 read-write @@ -13041,7 +13067,7 @@ DIGIMODE Select Analog/Digital mode. - 0x7 + 7 1 read-write @@ -13060,7 +13086,7 @@ FILTEROFF Controls input glitch filter. - 0x8 + 8 1 read-write @@ -13079,7 +13105,7 @@ SLEW Driver slew rate. - 0x9 + 9 1 read-write @@ -13098,7 +13124,7 @@ OD Controls open-drain mode. - 0xA + 10 1 read-write @@ -13177,7 +13203,7 @@ MODE Selects function mode (on-chip pull-up/pull-down resistor control). - 0x3 + 3 2 read-write @@ -13206,7 +13232,7 @@ INVERT Input polarity. - 0x6 + 6 1 read-write @@ -13225,7 +13251,7 @@ DIGIMODE Select Analog/Digital mode. - 0x7 + 7 1 read-write @@ -13244,7 +13270,7 @@ FILTEROFF Controls input glitch filter. - 0x8 + 8 1 read-write @@ -13263,7 +13289,7 @@ SLEW Driver slew rate. - 0x9 + 9 1 read-write @@ -13282,7 +13308,7 @@ OD Controls open-drain mode. - 0xA + 10 1 read-write @@ -13361,7 +13387,7 @@ MODE Selects function mode (on-chip pull-up/pull-down resistor control). - 0x3 + 3 2 read-write @@ -13390,7 +13416,7 @@ INVERT Input polarity. - 0x6 + 6 1 read-write @@ -13409,7 +13435,7 @@ DIGIMODE Select Analog/Digital mode. - 0x7 + 7 1 read-write @@ -13428,7 +13454,7 @@ FILTEROFF Controls input glitch filter. - 0x8 + 8 1 read-write @@ -13447,7 +13473,7 @@ SLEW Driver slew rate. - 0x9 + 9 1 read-write @@ -13466,7 +13492,7 @@ OD Controls open-drain mode. - 0xA + 10 1 read-write @@ -13545,7 +13571,7 @@ MODE Selects function mode (on-chip pull-up/pull-down resistor control). - 0x3 + 3 2 read-write @@ -13574,7 +13600,7 @@ INVERT Input polarity. - 0x6 + 6 1 read-write @@ -13593,7 +13619,7 @@ DIGIMODE Select Analog/Digital mode. - 0x7 + 7 1 read-write @@ -13612,7 +13638,7 @@ FILTEROFF Controls input glitch filter. - 0x8 + 8 1 read-write @@ -13631,7 +13657,7 @@ SLEW Driver slew rate. - 0x9 + 9 1 read-write @@ -13650,7 +13676,7 @@ OD Controls open-drain mode. - 0xA + 10 1 read-write @@ -13729,7 +13755,7 @@ MODE Selects function mode (on-chip pull-up/pull-down resistor control). - 0x3 + 3 2 read-write @@ -13758,7 +13784,7 @@ INVERT Input polarity. - 0x6 + 6 1 read-write @@ -13777,7 +13803,7 @@ DIGIMODE Select Analog/Digital mode. - 0x7 + 7 1 read-write @@ -13796,7 +13822,7 @@ FILTEROFF Controls input glitch filter. - 0x8 + 8 1 read-write @@ -13815,7 +13841,7 @@ SLEW Driver slew rate. - 0x9 + 9 1 read-write @@ -13834,7 +13860,7 @@ OD Controls open-drain mode. - 0xA + 10 1 read-write @@ -13913,7 +13939,7 @@ MODE Selects function mode (on-chip pull-up/pull-down resistor control). - 0x3 + 3 2 read-write @@ -13942,7 +13968,7 @@ INVERT Input polarity. - 0x6 + 6 1 read-write @@ -13961,7 +13987,7 @@ DIGIMODE Select Analog/Digital mode. - 0x7 + 7 1 read-write @@ -13980,7 +14006,7 @@ FILTEROFF Controls input glitch filter. - 0x8 + 8 1 read-write @@ -13999,7 +14025,7 @@ SLEW Driver slew rate. - 0x9 + 9 1 read-write @@ -14018,7 +14044,7 @@ OD Controls open-drain mode. - 0xA + 10 1 read-write @@ -14097,7 +14123,7 @@ MODE Selects function mode (on-chip pull-up/pull-down resistor control). - 0x3 + 3 2 read-write @@ -14126,7 +14152,7 @@ INVERT Input polarity. - 0x6 + 6 1 read-write @@ -14145,7 +14171,7 @@ DIGIMODE Select Analog/Digital mode. - 0x7 + 7 1 read-write @@ -14164,7 +14190,7 @@ FILTEROFF Controls input glitch filter. - 0x8 + 8 1 read-write @@ -14183,7 +14209,7 @@ SLEW Driver slew rate. - 0x9 + 9 1 read-write @@ -14202,7 +14228,7 @@ OD Controls open-drain mode. - 0xA + 10 1 read-write @@ -14281,7 +14307,7 @@ MODE Selects function mode (on-chip pull-up/pull-down resistor control). - 0x3 + 3 2 read-write @@ -14310,7 +14336,7 @@ INVERT Input polarity. - 0x6 + 6 1 read-write @@ -14329,7 +14355,7 @@ DIGIMODE Select Analog/Digital mode. - 0x7 + 7 1 read-write @@ -14348,7 +14374,7 @@ FILTEROFF Controls input glitch filter. - 0x8 + 8 1 read-write @@ -14367,7 +14393,7 @@ SLEW Driver slew rate. - 0x9 + 9 1 read-write @@ -14386,7 +14412,7 @@ OD Controls open-drain mode. - 0xA + 10 1 read-write @@ -14465,7 +14491,7 @@ MODE Selects function mode (on-chip pull-up/pull-down resistor control). - 0x3 + 3 2 read-write @@ -14494,7 +14520,7 @@ INVERT Input polarity. - 0x6 + 6 1 read-write @@ -14513,7 +14539,7 @@ DIGIMODE Select Analog/Digital mode. - 0x7 + 7 1 read-write @@ -14532,7 +14558,7 @@ FILTEROFF Controls input glitch filter. - 0x8 + 8 1 read-write @@ -14551,7 +14577,7 @@ SLEW Driver slew rate. - 0x9 + 9 1 read-write @@ -14570,7 +14596,7 @@ OD Controls open-drain mode. - 0xA + 10 1 read-write @@ -14649,7 +14675,7 @@ MODE Selects function mode (on-chip pull-up/pull-down resistor control). - 0x3 + 3 2 read-write @@ -14678,7 +14704,7 @@ INVERT Input polarity. - 0x6 + 6 1 read-write @@ -14697,7 +14723,7 @@ DIGIMODE Select Analog/Digital mode. - 0x7 + 7 1 read-write @@ -14716,7 +14742,7 @@ FILTEROFF Controls input glitch filter. - 0x8 + 8 1 read-write @@ -14735,7 +14761,7 @@ SLEW Driver slew rate. - 0x9 + 9 1 read-write @@ -14754,7 +14780,7 @@ OD Controls open-drain mode. - 0xA + 10 1 read-write @@ -14833,7 +14859,7 @@ MODE Selects function mode (on-chip pull-up/pull-down resistor control). - 0x3 + 3 2 read-write @@ -14862,7 +14888,7 @@ INVERT Input polarity. - 0x6 + 6 1 read-write @@ -14881,7 +14907,7 @@ DIGIMODE Select Analog/Digital mode. - 0x7 + 7 1 read-write @@ -14900,7 +14926,7 @@ FILTEROFF Controls input glitch filter. - 0x8 + 8 1 read-write @@ -14919,7 +14945,7 @@ SLEW Driver slew rate. - 0x9 + 9 1 read-write @@ -14938,7 +14964,7 @@ OD Controls open-drain mode. - 0xA + 10 1 read-write @@ -14962,8 +14988,8 @@ GINT0 LPC5411x Group GPIO input interrupt (GINT0/1) GINT - 0x40002000 GINT + 0x40002000 0 0x48 @@ -15005,7 +15031,7 @@ COMB Combine enabled inputs for group interrupt - 0x1 + 1 1 read-write @@ -15024,7 +15050,7 @@ TRIG Group interrupt trigger - 0x2 + 2 1 read-write @@ -15337,7 +15363,7 @@ ENA_RXEV Enables the RXEV output to the CPU and/or to a GPIO output when the specified boolean expression evaluates to true. - 0x1 + 1 1 read-write @@ -15356,7 +15382,7 @@ PMAT This field displays the current state of pattern matches. A 1 in any bit of this field indicates that the corresponding product term is matched by the current state of the appropriate inputs. - 0x18 + 24 8 read-write @@ -15374,7 +15400,7 @@ SRC0 Selects the input source for bit slice 0 - 0x8 + 8 3 read-write @@ -15423,7 +15449,7 @@ SRC1 Selects the input source for bit slice 1 - 0xB + 11 3 read-write @@ -15472,7 +15498,7 @@ SRC2 Selects the input source for bit slice 2 - 0xE + 14 3 read-write @@ -15521,7 +15547,7 @@ SRC3 Selects the input source for bit slice 3 - 0x11 + 17 3 read-write @@ -15570,7 +15596,7 @@ SRC4 Selects the input source for bit slice 4 - 0x14 + 20 3 read-write @@ -15619,7 +15645,7 @@ SRC5 Selects the input source for bit slice 5 - 0x17 + 23 3 read-write @@ -15668,7 +15694,7 @@ SRC6 Selects the input source for bit slice 6 - 0x1A + 26 3 read-write @@ -15717,7 +15743,7 @@ SRC7 Selects the input source for bit slice 7 - 0x1D + 29 3 read-write @@ -15796,7 +15822,7 @@ PROD_ENDPTS1 Determines whether slice 1 is an endpoint. - 0x1 + 1 1 read-write @@ -15815,7 +15841,7 @@ PROD_ENDPTS2 Determines whether slice 2 is an endpoint. - 0x2 + 2 1 read-write @@ -15834,7 +15860,7 @@ PROD_ENDPTS3 Determines whether slice 3 is an endpoint. - 0x3 + 3 1 read-write @@ -15853,7 +15879,7 @@ PROD_ENDPTS4 Determines whether slice 4 is an endpoint. - 0x4 + 4 1 read-write @@ -15872,7 +15898,7 @@ PROD_ENDPTS5 Determines whether slice 5 is an endpoint. - 0x5 + 5 1 read-write @@ -15891,7 +15917,7 @@ PROD_ENDPTS6 Determines whether slice 6 is an endpoint. - 0x6 + 6 1 read-write @@ -15910,7 +15936,7 @@ CFG0 Specifies the match contribution condition for bit slice 0. - 0x8 + 8 3 read-write @@ -15959,7 +15985,7 @@ CFG1 Specifies the match contribution condition for bit slice 1. - 0xB + 11 3 read-write @@ -16008,7 +16034,7 @@ CFG2 Specifies the match contribution condition for bit slice 2. - 0xE + 14 3 read-write @@ -16057,7 +16083,7 @@ CFG3 Specifies the match contribution condition for bit slice 3. - 0x11 + 17 3 read-write @@ -16106,7 +16132,7 @@ CFG4 Specifies the match contribution condition for bit slice 4. - 0x14 + 20 3 read-write @@ -16155,7 +16181,7 @@ CFG5 Specifies the match contribution condition for bit slice 5. - 0x17 + 23 3 read-write @@ -16204,7 +16230,7 @@ CFG6 Specifies the match contribution condition for bit slice 6. - 0x1A + 26 3 read-write @@ -16253,7 +16279,7 @@ CFG7 Specifies the match contribution condition for bit slice 7. - 0x1D + 29 3 read-write @@ -16416,8 +16442,8 @@ CTIMER0 LPC5411x Standard counter/timers (CTIMER0 to 4) CTIMER - 0x40008000 CTIMER + 0x40008000 0 0x78 @@ -16447,49 +16473,49 @@ MR1INT Interrupt flag for match channel 1. - 0x1 + 1 1 read-write MR2INT Interrupt flag for match channel 2. - 0x2 + 2 1 read-write MR3INT Interrupt flag for match channel 3. - 0x3 + 3 1 read-write CR0INT Interrupt flag for capture channel 0 event. - 0x4 + 4 1 read-write CR1INT Interrupt flag for capture channel 1 event. - 0x5 + 5 1 read-write CR2INT Interrupt flag for capture channel 2 event. - 0x6 + 6 1 read-write CR3INT Interrupt flag for capture channel 3 event. - 0x7 + 7 1 read-write @@ -16526,7 +16552,7 @@ CRST Counter reset. - 0x1 + 1 1 read-write @@ -16617,77 +16643,77 @@ MR0R Reset on MR0: the TC will be reset if MR0 matches it. 0 = disabled. 1 = enabled. - 0x1 + 1 1 read-write MR0S Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC. 0 = disabled. 1 = enabled. - 0x2 + 2 1 read-write MR1I Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC. 0 = disabled. 1 = enabled. 0 = disabled. 1 = enabled. - 0x3 + 3 1 read-write MR1R Reset on MR1: the TC will be reset if MR1 matches it. 0 = disabled. 1 = enabled. - 0x4 + 4 1 read-write MR1S Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC. 0 = disabled. 1 = enabled. - 0x5 + 5 1 read-write MR2I Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC. 0 = disabled. 1 = enabled. - 0x6 + 6 1 read-write MR2R Reset on MR2: the TC will be reset if MR2 matches it. 0 = disabled. 1 = enabled. - 0x7 + 7 1 read-write MR2S Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC. 0 = disabled. 1 = enabled. - 0x8 + 8 1 read-write MR3I Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC. 0 = disabled. 1 = enabled. - 0x9 + 9 1 read-write MR3R Reset on MR3: the TC will be reset if MR3 matches it. 0 = disabled. 1 = enabled. - 0xA + 10 1 read-write MR3S Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC. 0 = disabled. 1 = enabled. - 0xB + 11 1 read-write @@ -16732,77 +16758,77 @@ CAP0FE Falling edge of capture channel 0: a sequence of 1 then 0 causes CR0 to be loaded with the contents of TC. 0 = disabled. 1 = enabled. - 0x1 + 1 1 read-write CAP0I Generate interrupt on channel 0 capture event: a CR0 load generates an interrupt. - 0x2 + 2 1 read-write CAP1RE Rising edge of capture channel 1: a sequence of 0 then 1 causes CR1 to be loaded with the contents of TC. 0 = disabled. 1 = enabled. - 0x3 + 3 1 read-write CAP1FE Falling edge of capture channel 1: a sequence of 1 then 0 causes CR1 to be loaded with the contents of TC. 0 = disabled. 1 = enabled. - 0x4 + 4 1 read-write CAP1I Generate interrupt on channel 1 capture event: a CR1 load generates an interrupt. - 0x5 + 5 1 read-write CAP2RE Rising edge of capture channel 2: a sequence of 0 then 1 causes CR2 to be loaded with the contents of TC. 0 = disabled. 1 = enabled. - 0x6 + 6 1 read-write CAP2FE Falling edge of capture channel 2: a sequence of 1 then 0 causes CR2 to be loaded with the contents of TC. 0 = disabled. 1 = enabled. - 0x7 + 7 1 read-write CAP2I Generate interrupt on channel 2 capture event: a CR2 load generates an interrupt. - 0x8 + 8 1 read-write CAP3RE Rising edge of capture channel 3: a sequence of 0 then 1 causes CR3 to be loaded with the contents of TC. 0 = disabled. 1 = enabled. - 0x9 + 9 1 read-write CAP3FE Falling edge of capture channel 3: a sequence of 1 then 0 causes CR3 to be loaded with the contents of TC. 0 = disabled. 1 = enabled. - 0xA + 10 1 read-write CAP3I Generate interrupt on channel 3 capture event: a CR3 load generates an interrupt. - 0xB + 11 1 read-write @@ -16847,28 +16873,28 @@ EM1 External Match 1. This bit reflects the state of output MAT1, whether or not this output is connected to a pin. When a match occurs between the TC and MR1, this bit can either toggle, go LOW, go HIGH, or do nothing, as selected by EMR[7:6]. This bit is driven to the MAT pins if the match function is selected via IOCON. 0 = LOW. 1 = HIGH. - 0x1 + 1 1 read-write EM2 External Match 2. This bit reflects the state of output MAT2, whether or not this output is connected to a pin. When a match occurs between the TC and MR2, this bit can either toggle, go LOW, go HIGH, or do nothing, as selected by EMR[9:8]. This bit is driven to the MAT pins if the match function is selected via IOCON. 0 = LOW. 1 = HIGH. - 0x2 + 2 1 read-write EM3 External Match 3. This bit reflects the state of output MAT3, whether or not this output is connected to a pin. When a match occurs between the TC and MR3, this bit can either toggle, go LOW, go HIGH, or do nothing, as selected by MR[11:10]. This bit is driven to the MAT pins if the match function is selected via IOCON. 0 = LOW. 1 = HIGH. - 0x3 + 3 1 read-write EMC0 External Match Control 0. Determines the functionality of External Match 0. - 0x4 + 4 2 read-write @@ -16897,7 +16923,7 @@ EMC1 External Match Control 1. Determines the functionality of External Match 1. - 0x6 + 6 2 read-write @@ -16926,7 +16952,7 @@ EMC2 External Match Control 2. Determines the functionality of External Match 2. - 0x8 + 8 2 read-write @@ -16955,7 +16981,7 @@ EMC3 External Match Control 3. Determines the functionality of External Match 3. - 0xA + 10 2 read-write @@ -17024,7 +17050,7 @@ CINSEL Count Input Select When bits 1:0 in this register are not 00, these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input in the CTCR, the 3 bits for that input in the Capture Control Register (CCR) must be programmed as 000. However, capture and/or interrupt can be selected for the other 3 CAPn inputs in the same timer. - 0x2 + 2 2 read-write @@ -17053,14 +17079,14 @@ ENCC Setting this bit to 1 enables clearing of the timer and the prescaler when the capture-edge event specified in bits 7:5 occurs. - 0x4 + 4 1 read-write SELCC Edge select. When bit 4 is 1, these bits select which capture input edge will cause the timer and prescaler to be cleared. These bits have no effect when bit 4 is low. Values 0x2 to 0x3 and 0x6 to 0x7 are reserved. - 0x5 + 5 3 read-write @@ -17129,7 +17155,7 @@ PWMEN1 PWM mode enable for channel1. - 0x1 + 1 1 read-write @@ -17148,7 +17174,7 @@ PWMEN2 PWM mode enable for channel2. - 0x2 + 2 1 read-write @@ -17167,7 +17193,7 @@ PWMEN3 PWM mode enable for channel3. Note: It is recommended to use match channel 3 to set the PWM cycle. - 0x3 + 3 1 read-write @@ -17202,6 +17228,43 @@ 11 + + CTIMER2 + LPC5411x Standard counter/timers (CTIMER0 to 4) + CTIMER + 0x40028000 + + 0 + 0x78 + registers + + + + CTIMER3 + LPC5411x Standard counter/timers (CTIMER0 to 4) + CTIMER + 0x40048000 + + 0 + 0x78 + registers + + + CTIMER3 + 13 + + + + CTIMER4 + LPC5411x Standard counter/timers (CTIMER0 to 4) + CTIMER + 0x40049000 + + 0 + 0x78 + registers + + WWDT LPC5411x Windowed Watchdog Timer (WWDT) @@ -17248,7 +17311,7 @@ WDRESET Watchdog reset enable bit. Once this bit has been written with a 1 it cannot be re-written with a 0. - 0x1 + 1 1 read-write @@ -17267,21 +17330,21 @@ WDTOF Watchdog time-out flag. Set when the watchdog timer times out, by a feed error, or by events associated with WDPROTECT. Cleared by software writing a 0 to this bit position. Causes a chip reset if WDRESET = 1. - 0x2 + 2 1 read-write WDINT Warning interrupt flag. Set when the timer is at or below the value in WDWARNINT. Cleared by software writing a 1 to this bit position. Note that this bit cannot be cleared while the WARNINT value is equal to the value of the TV register. This can occur if the value of WARNINT is 0 and the WDRESET bit is 0 when TV decrements to 0. - 0x3 + 3 1 read-write WDPROTECT Watchdog update mode. This bit can be set once by software and is only cleared by a reset. - 0x4 + 4 1 read-write @@ -17300,7 +17363,7 @@ LOCK Once this bit is set to one and a watchdog feed is performed, disabling or powering down the watchdog oscillator is prevented by hardware. This bit can be set once by software and is only cleared by any reset. - 0x5 + 5 1 read-write @@ -17438,7 +17501,7 @@ LOAD Determines how the timer interval value IVALUE -1 is loaded into the TIMERn register. This bit is write-only. Reading this bit always returns 0. - 0x1F + 31 1 read-write @@ -17505,7 +17568,7 @@ MODE Selects timer mode. - 0x1 + 1 2 read-write @@ -17559,7 +17622,7 @@ RUN Indicates the state of TIMERn. This bit is read-only. - 0x1 + 1 1 read-write @@ -17578,7 +17641,7 @@ INUSE Channel In Use flag. Operating details depend on the MULTITASK bit in the MODCFG register, and affects the use of IDLE_CH. See Idle channel register for details of the two operating modes. - 0x2 + 2 1 read-write @@ -17616,14 +17679,14 @@ NOB Identifies the number of timer bits in this MRT. (24 bits wide on this device.) - 0x4 + 4 5 read-write MULTITASK Selects the operating mode for the INUSE flags and the IDLE_CH register. - 0x1F + 31 1 read-write @@ -17653,7 +17716,7 @@ CHAN Idle channel. Reading the CHAN bits, returns the lowest idle timer channel. The number is positioned such that it can be used as an offset from the MRT base address in order to access the registers for the allocated channel. If all timer channels are running, CHAN = 0xF. See text above for more details. - 0x4 + 4 4 read-only @@ -17690,21 +17753,21 @@ GFLAG1 Monitors the interrupt flag of TIMER1. See description of channel 0. - 0x1 + 1 1 read-write GFLAG2 Monitors the interrupt flag of TIMER2. See description of channel 0. - 0x2 + 2 1 read-write GFLAG3 Monitors the interrupt flag of TIMER3. See description of channel 0. - 0x3 + 3 1 read-write @@ -17746,7 +17809,7 @@ REPEAT Repeat delay. 0 = One-time delay. 1 = Delay repeats continuously. - 0x1F + 31 1 read-write @@ -17771,7 +17834,7 @@ ACTIVE Active flag. 0 = The Micro-Tick Timer is stopped. 1 = The Micro-Tick Timer is currently active. - 0x1 + 1 1 read-write @@ -17796,49 +17859,49 @@ CAPEN1 Enable Capture 1. 1 = Enabled, 0 = Disabled. - 0x1 + 1 1 read-write CAPEN2 Enable Capture 2. 1 = Enabled, 0 = Disabled. - 0x2 + 2 1 read-write CAPEN3 Enable Capture 3. 1 = Enabled, 0 = Disabled. - 0x3 + 3 1 read-write CAPPOL0 Capture Polarity 0. 0 = Positive edge capture, 1 = Negative edge capture. - 0x8 + 8 1 read-write CAPPOL1 Capture Polarity 1. 0 = Positive edge capture, 1 = Negative edge capture. - 0x9 + 9 1 read-write CAPPOL2 Capture Polarity 2. 0 = Positive edge capture, 1 = Negative edge capture. - 0xA + 10 1 read-write CAPPOL3 Capture Polarity 3. 0 = Positive edge capture, 1 = Negative edge capture. - 0xB + 11 1 read-write @@ -17863,21 +17926,21 @@ CAPCLR1 Clear capture 1. Writing 1 to this bit clears the CAP1 register value. - 0x1 + 1 1 write-only CAPCLR2 Clear capture 2. Writing 1 to this bit clears the CAP2 register value. - 0x2 + 2 1 write-only CAPCLR3 Clear capture 3. Writing 1 to this bit clears the CAP3 register value. - 0x3 + 3 1 write-only @@ -17904,7 +17967,7 @@ VALID Capture Valid. When 1, a value has been captured based on a transition of the related UTICK_CAPn pin. Cleared by writing to the related bit in the CAPCLR register. - 0x1F + 31 1 read-only @@ -17912,17 +17975,6 @@ - - CTIMER2 - LPC5411x Standard counter/timers (CTIMER0 to 4) - CTIMER - 0x40028000 - - 0 - 0x78 - registers - - RTC LPC5411x Real-Time Clock (RTC) @@ -17969,7 +18021,7 @@ ALARM1HZ RTC 1 Hz timer alarm flag status. - 0x2 + 2 1 read-write @@ -17988,7 +18040,7 @@ WAKE1KHZ RTC 1 kHz timer wake-up flag status. - 0x3 + 3 1 read-write @@ -18007,7 +18059,7 @@ ALARMDPD_EN RTC 1 Hz timer alarm enable for Deep power-down. - 0x4 + 4 1 read-write @@ -18026,7 +18078,7 @@ WAKEDPD_EN RTC 1 kHz timer wake-up enable for Deep power-down. - 0x5 + 5 1 read-write @@ -18045,7 +18097,7 @@ RTC1KHZ_EN RTC 1 kHz clock enable. This bit can be set to 0 to conserve power if the 1 kHz timer is not used. This bit has no effect when the RTC is disabled (bit 7 of this register is 0). - 0x6 + 6 1 read-write @@ -18064,7 +18116,7 @@ RTC_EN RTC enable. - 0x7 + 7 1 read-write @@ -18083,7 +18135,7 @@ RTC_OSC_PD RTC oscillator power-down control. - 0x8 + 8 1 read-write @@ -18102,7 +18154,7 @@ RTC_OSC_BYPASS RTC oscillator bypass control. - 0x9 + 9 1 read-write @@ -18199,14 +18251,14 @@ CTIMER3 Standard counter/timer CTIMER3 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function. - 0xD + 13 1 read-write CTIMER4 Standard counter/timer CTIMER4 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function. - 0xE + 14 1 read-write @@ -18260,14 +18312,14 @@ CTIMER3 Controls the clock for CTIMER3. 0 = Disable; 1 = Enable. - 0xD + 13 1 read-write CTIMER4 Controls the clock for CTIMER4. 0 = Disable; 1 = Enable. - 0xE + 14 1 read-write @@ -18341,32 +18393,6 @@ - - CTIMER3 - LPC5411x Standard counter/timers (CTIMER0 to 4) - CTIMER - 0x40048000 - - 0 - 0x78 - registers - - - CTIMER3 - 13 - - - - CTIMER4 - LPC5411x Standard counter/timers (CTIMER0 to 4) - CTIMER - 0x40049000 - - 0 - 0x78 - registers - - SPIFI0 LPC5411x SPI Flash Interface (SPIFI) @@ -18397,28 +18423,28 @@ CSHIGH This field controls the minimum CS high time, expressed as a number of serial clock periods minus one. - 0x10 + 16 4 read-write D_PRFTCH_DIS This bit allows conditioning of memory mode prefetches based on the AHB HPROT (instruction/data) access information. A 1 in this register means that the SPIFI will not attempt a speculative prefetch when it encounters data accesses. - 0x15 + 21 1 read-write INTEN If this bit is 1 when a command ends, the SPIFI will assert its interrupt request output. See INTRQ in the status register for further details. - 0x16 + 22 1 read-write MODE3 SPI Mode 3 select. - 0x17 + 23 1 read-write @@ -18437,7 +18463,7 @@ PRFTCH_DIS Cache prefetching enable. The SPIFI includes an internal cache. A 1 in this bit disables prefetching of cache lines. - 0x1B + 27 1 read-write @@ -18456,7 +18482,7 @@ DUAL Select dual protocol. - 0x1C + 28 1 read-write @@ -18475,7 +18501,7 @@ RFCLK Select active clock edge for input data. - 0x1D + 29 1 read-write @@ -18494,7 +18520,7 @@ FBCLK Feedback clock select. - 0x1E + 30 1 read-write @@ -18513,7 +18539,7 @@ DMAEN A 1 in this bit enables the DMA Request output from the SPIFI. Set this bit only when a DMA channel is used to transfer data in peripheral mode. Do not set this bit when a DMA channel is used for memory-to-memory transfers from the SPIFI memory area. DMAEN should only be used in Command mode. - 0x1F + 31 1 read-write @@ -18538,14 +18564,14 @@ POLL This bit should be written as 1 only with an opcode that a) contains an input data field, and b) causes the serial flash device to return byte status repetitively (e.g., a Read Status command). When this bit is 1, the SPIFI hardware continues to read bytes until the test specified by the DATALEN field is met. The hardware tests the bit in each status byte selected by DATALEN bits 2:0, until a bit is found that is equal to DATALEN bit 3. When the test succeeds, the SPIFI captures the byte that meets this test so that it can be read from the Data Register, and terminates the command by raising CS. The end-of-command interrupt can be enabled to inform software when this occurs - 0xE + 14 1 read-write DOUT If the DATALEN field is not zero, this bit controls the direction of the data: - 0xF + 15 1 read-write @@ -18564,14 +18590,14 @@ INTLEN This field controls how many intermediate bytes precede the data. (Each such byte may require 8 or 2 SCK cycles, depending on whether the intermediate field is in serial, 2-bit, or 4-bit format.) Intermediate bytes are output by the SPIFI, and include post-address control information, dummy and delay bytes. See the description of the Intermediate Data register for the contents of such bytes. - 0x10 + 16 3 read-write FIELDFORM This field controls how the fields of the command are sent. - 0x13 + 19 2 read-write @@ -18600,7 +18626,7 @@ FRAMEFORM This field controls the opcode and address fields. - 0x15 + 21 3 read-write @@ -18644,7 +18670,7 @@ OPCODE The opcode of the command (not used for some FRAMEFORM values). - 0x18 + 24 8 read-write @@ -18734,28 +18760,28 @@ POLL This bit should be written as 0. - 0xE + 14 1 read-write DOUT This bit should be written as 0. - 0xF + 15 1 read-write INTLEN This field controls how many intermediate bytes precede the data. (Each such byte may require 8 or 2 SCK cycles, depending on whether the intermediate field is in serial, 2-bit, or 4-bit format.) Intermediate bytes are output by the SPIFI, and include post-address control information, dummy and delay bytes. See the description of the Intermediate Data register for the contents of such bytes. - 0x10 + 16 3 read-write FIELDFORM This field controls how the fields of the command are sent. - 0x13 + 19 2 read-write @@ -18784,7 +18810,7 @@ FRAMEFORM This field controls the opcode and address fields. - 0x15 + 21 3 read-write @@ -18828,7 +18854,7 @@ OPCODE The opcode of the command (not used for some FRAMEFORM values). - 0x18 + 24 8 read-write @@ -18853,28 +18879,28 @@ CMD This bit is 1 when the Command register is written. It is cleared by a hardware reset, a write to the RESET bit in this register, or the deassertion of CS which indicates that the command has completed communication with the SPI Flash. - 0x1 + 1 1 read-write RESET Write a 1 to this bit to abort a current command or memory mode. This bit is cleared when the hardware is ready for a new command to be written to the Command register. - 0x4 + 4 1 read-write INTRQ This bit reflects the SPIFI interrupt request. Write a 1 to this bit to clear it. This bit is set when a CMD was previously 1 and has been cleared due to the deassertion of CS. - 0x5 + 5 1 read-write VERSION - - 0x18 + 24 8 read-write @@ -18939,7 +18965,7 @@ ACTIVEINT Summarizes whether any enabled interrupts (other than error interrupts) are pending. - 0x1 + 1 1 read-only @@ -18958,7 +18984,7 @@ ACTIVEERRINT Summarizes whether any error interrupts are pending. - 0x2 + 2 1 read-only @@ -18988,7 +19014,7 @@ OFFSET Address bits 31:9 of the beginning of the DMA descriptor table. For 18 channels, the table must begin on a 512 byte boundary. - 0x9 + 9 23 read-write @@ -19247,7 +19273,7 @@ HWTRIGEN Hardware Triggering Enable for this channel. - 0x1 + 1 1 read-write @@ -19266,7 +19292,7 @@ TRIGPOL Trigger Polarity. Selects the polarity of a hardware trigger for this channel. - 0x4 + 4 1 read-write @@ -19285,7 +19311,7 @@ TRIGTYPE Trigger Type. Selects hardware trigger as edge triggered or level triggered. - 0x5 + 5 1 read-write @@ -19304,7 +19330,7 @@ TRIGBURST Trigger Burst. Selects whether hardware triggers cause a single or burst transfer. - 0x6 + 6 1 read-write @@ -19323,14 +19349,14 @@ BURSTPOWER Burst Power is used in two ways. It always selects the address wrap size when SRCBURSTWRAP and/or DSTBURSTWRAP modes are selected (see descriptions elsewhere in this register). When the TRIGBURST field elsewhere in this register = 1, Burst Power selects how many transfers are performed for each DMA trigger. This can be used, for example, with peripherals that contain a FIFO that can initiate a DMA operation when the FIFO reaches a certain level. 0000: Burst size = 1 (20). 0001: Burst size = 2 (21). 0010: Burst size = 4 (22). 1010: Burst size = 1024 (210). This corresponds to the maximum supported transfer count. others: not supported. The total transfer length as defined in the XFERCOUNT bits in the XFERCFG register must be an even multiple of the burst size. - 0x8 + 8 4 read-write SRCBURSTWRAP Source Burst Wrap. When enabled, the source data address for the DMA is 'wrapped', meaning that the source address range for each burst will be the same. As an example, this could be used to read several sequential registers from a peripheral for each DMA burst, reading the same registers again for each burst. - 0xE + 14 1 read-write @@ -19349,7 +19375,7 @@ DSTBURSTWRAP Destination Burst Wrap. When enabled, the destination data address for the DMA is 'wrapped', meaning that the destination address range for each burst will be the same. As an example, this could be used to write several sequential registers to a peripheral for each DMA burst, writing the same registers again for each burst. - 0xF + 15 1 read-write @@ -19368,7 +19394,7 @@ CHPRIORITY Priority of this channel when multiple DMA requests are pending. Eight priority levels are supported: 0x0 = highest priority. 0x7 = lowest priority. - 0x10 + 16 3 read-write @@ -19405,7 +19431,7 @@ TRIG Trigger flag. Indicates that the trigger for this channel is currently set. This bit is cleared at the end of an entire transfer or upon reload when CLRTRIG = 1. - 0x2 + 2 1 read-only @@ -19454,7 +19480,7 @@ RELOAD Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted. Reloading allows ping-pong and linked transfers. - 0x1 + 1 1 read-write @@ -19473,7 +19499,7 @@ SWTRIG Software Trigger. - 0x2 + 2 1 read-write @@ -19492,7 +19518,7 @@ CLRTRIG Clear Trigger. - 0x3 + 3 1 read-write @@ -19511,7 +19537,7 @@ SETINTA Set Interrupt flag A for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed. - 0x4 + 4 1 read-write @@ -19530,7 +19556,7 @@ SETINTB Set Interrupt flag B for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed. - 0x5 + 5 1 read-write @@ -19549,7 +19575,7 @@ WIDTH Transfer width used for this DMA channel. - 0x8 + 8 2 read-write @@ -19573,7 +19599,7 @@ SRCINC Determines whether the source address is incremented for each DMA transfer. - 0xC + 12 2 read-write @@ -19602,7 +19628,7 @@ DSTINC Determines whether the destination address is incremented for each DMA transfer. - 0xE + 14 2 read-write @@ -19631,7 +19657,7 @@ XFERCOUNT Total number of transfers to be performed, minus 1 encoded. The number of bytes transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller uses this bit field during transfer to count down. Hence, it cannot be used by software to read back the size of the transfer, for instance, in an interrupt handler. 0x0 = a total of 1 transfer will be performed. 0x1 = a total of 2 transfers will be performed. 0x3FF = a total of 1,024 transfers will be performed. - 0x10 + 16 10 read-write @@ -19678,21 +19704,21 @@ DEV_EN USB device enable. If this bit is set, the HW will start responding on packets for function address DEV_ADDR. - 0x7 + 7 1 read-write SETUP SETUP token received. If a SETUP token is received and acknowledged by the device, this bit is set. As long as this bit is set all received IN and OUT tokens will be NAKed by HW. SW must clear this bit by writing a one. If this bit is zero, HW will handle the tokens to the CTRL EP0 as indicated by the CTRL EP0 IN and OUT data information programmed by SW. - 0x8 + 8 1 read-write FORCE_NEEDCLK Forces the NEEDCLK output to always be on: - 0x9 + 9 1 read-write @@ -19711,7 +19737,7 @@ LPM_SUP LPM Supported: - 0xB + 11 1 read-write @@ -19730,7 +19756,7 @@ INTONNAK_AO Interrupt on NAK for interrupt and bulk OUT EP - 0xC + 12 1 read-write @@ -19749,7 +19775,7 @@ INTONNAK_AI Interrupt on NAK for interrupt and bulk IN EP - 0xD + 13 1 read-write @@ -19768,7 +19794,7 @@ INTONNAK_CO Interrupt on NAK for control OUT EP - 0xE + 14 1 read-write @@ -19787,7 +19813,7 @@ INTONNAK_CI Interrupt on NAK for control IN EP - 0xF + 15 1 read-write @@ -19806,56 +19832,56 @@ DCON Device status - connect. The connect bit must be set by SW to indicate that the device must signal a connect. The pull-up resistor on USB_DP will be enabled when this bit is set and the VBUSDEBOUNCED bit is one. - 0x10 + 16 1 read-write DSUS Device status - suspend. The suspend bit indicates the current suspend state. It is set to 1 when the device hasn't seen any activity on its upstream port for more than 3 milliseconds. It is reset to 0 on any activity. When the device is suspended (Suspend bit DSUS = 1) and the software writes a 0 to it, the device will generate a remote wake-up. This will only happen when the device is connected (Connect bit = 1). When the device is not connected or not suspended, a writing a 0 has no effect. Writing a 1 never has an effect. - 0x11 + 17 1 read-write LPM_SUS Device status - LPM Suspend. This bit represents the current LPM suspend state. It is set to 1 by HW when the device has acknowledged the LPM request from the USB host and the Token Retry Time of 10 ms has elapsed. When the device is in the LPM suspended state (LPM suspend bit = 1) and the software writes a zero to this bit, the device will generate a remote walk-up. Software can only write a zero to this bit when the LPM_REWP bit is set to 1. HW resets this bit when it receives a host initiated resume. HW only updates the LPM_SUS bit when the LPM_SUPP bit is equal to one. - 0x13 + 19 1 read-write LPM_REWP LPM Remote Wake-up Enabled by USB host. HW sets this bit to one when the bRemoteWake bit in the LPM extended token is set to 1. HW will reset this bit to 0 when it receives the host initiated LPM resume, when a remote wake-up is sent by the device or when a USB bus reset is received. Software can use this bit to check if the remote wake-up feature is enabled by the host for the LPM transaction. - 0x14 + 20 1 read-only DCON_C Device status - connect change. The Connect Change bit is set when the device's pull-up resistor is disconnected because VBus disappeared. The bit is reset by writing a one to it. - 0x18 + 24 1 read-write DSUS_C Device status - suspend change. The suspend change bit is set to 1 when the suspend bit toggles. The suspend bit can toggle because: - The device goes in the suspended state - The device is disconnected - The device receives resume signaling on its upstream port. The bit is reset by writing a one to it. - 0x19 + 25 1 read-write DRES_C Device status - reset change. This bit is set when the device received a bus reset. On a bus reset the device will automatically go to the default state (unconfigured and responding to address 0). The bit is reset by writing a one to it. - 0x1A + 26 1 read-write VBUSDEBOUNCED This bit indicates if Vbus is detected or not. The bit raises immediately when Vbus becomes high. It drops to zero if Vbus is low for at least 3 ms. If this bit is high and the DCon bit is set, the HW will enable the pull-up resistor to signal a connect. - 0x1C + 28 1 read-only @@ -19880,7 +19906,7 @@ ERR_CODE The error code which last occurred: - 0xB + 11 4 read-write @@ -19980,7 +20006,7 @@ EP_LIST Start address of the USB EP Command/Status List. - 0x8 + 8 24 read-write @@ -19998,7 +20024,7 @@ DA_BUF Start address of the buffer pointer page where all endpoint data buffers are located. - 0x16 + 22 10 read-write @@ -20023,14 +20049,14 @@ HIRD_SW Host Initiated Resume Duration - SW. This is the time duration required by the USB device system to come out of LPM initiated suspend after receiving the host initiated LPM resume. - 0x4 + 4 4 read-write DATA_PENDING As long as this bit is set to one and LPM supported bit is set to one, HW will return a NYET handshake on every LPM token it receives. If LPM supported bit is set to one and this bit is zero, HW will return an ACK handshake on every LPM token it receives. If SW has still data pending and LPM is supported, it must set this bit to 1. - 0x8 + 8 1 read-write @@ -20066,7 +20092,7 @@ BUF Buffer in use: This register has one bit per physical endpoint. 0: HW is accessing buffer 0. 1: HW is accessing buffer 1. - 0x2 + 2 8 read-write @@ -20084,7 +20110,7 @@ BUF_SB Buffer usage: This register has one bit per physical endpoint. 0: Single-buffer. 1: Double-buffer. If the bit is set to single-buffer (0), it will not toggle the corresponding EPINUSE bit when it clears the active bit. If the bit is set to double-buffer (1), HW will toggle the EPINUSE bit when it clears the Active bit for the buffer. - 0x2 + 2 8 read-write @@ -20109,77 +20135,77 @@ EP0IN Interrupt status register bit for the Control EP0 IN direction. This bit will be set if NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_CI is set, this bit will also be set when a NAK is transmitted for the Control EP0 IN direction. Software can clear this bit by writing a one to it. - 0x1 + 1 1 read-write EP1OUT Interrupt status register bit for the EP1 OUT direction. This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_AO is set, this bit will also be set when a NAK is transmitted for the EP1 OUT direction. Software can clear this bit by writing a one to it. - 0x2 + 2 1 read-write EP1IN Interrupt status register bit for the EP1 IN direction. This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_AI is set, this bit will also be set when a NAK is transmitted for the EP1 IN direction. Software can clear this bit by writing a one to it. - 0x3 + 3 1 read-write EP2OUT Interrupt status register bit for the EP2 OUT direction. This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_AO is set, this bit will also be set when a NAK is transmitted for the EP2 OUT direction. Software can clear this bit by writing a one to it. - 0x4 + 4 1 read-write EP2IN Interrupt status register bit for the EP2 IN direction. This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_AI is set, this bit will also be set when a NAK is transmitted for the EP2 IN direction. Software can clear this bit by writing a one to it. - 0x5 + 5 1 read-write EP3OUT Interrupt status register bit for the EP3 OUT direction. This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_AO is set, this bit will also be set when a NAK is transmitted for the EP3 OUT direction. Software can clear this bit by writing a one to it. - 0x6 + 6 1 read-write EP3IN Interrupt status register bit for the EP3 IN direction. This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_AI is set, this bit will also be set when a NAK is transmitted for the EP3 IN direction. Software can clear this bit by writing a one to it. - 0x7 + 7 1 read-write EP4OUT Interrupt status register bit for the EP4 OUT direction. This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_AO is set, this bit will also be set when a NAK is transmitted for the EP4 OUT direction. Software can clear this bit by writing a one to it. - 0x8 + 8 1 read-write EP4IN Interrupt status register bit for the EP4 IN direction. This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_AI is set, this bit will also be set when a NAK is transmitted for the EP4 IN direction. Software can clear this bit by writing a one to it. - 0x9 + 9 1 read-write FRAME_INT Frame interrupt. This bit is set to one every millisecond when the VbusDebounced bit and the DCON bit are set. This bit can be used by software when handling isochronous endpoints. Software can clear this bit by writing a one to it. - 0x1E + 30 1 read-write DEV_INT Device status interrupt. This bit is set by HW when one of the bits in the Device Status Change register are set. Software can clear this bit by writing a one to it. - 0x1F + 31 1 read-write @@ -20204,14 +20230,14 @@ FRAME_INT_EN If this bit is set and the corresponding USB interrupt status bit is set, a HW interrupt is generated on the interrupt line indicated by the corresponding USB interrupt routing bit. - 0x1E + 30 1 read-write DEV_INT_EN If this bit is set and the corresponding USB interrupt status bit is set, a HW interrupt is generated on the interrupt line indicated by the corresponding USB interrupt routing bit. - 0x1F + 31 1 read-write @@ -20236,14 +20262,14 @@ FRAME_SET_INT If software writes a one to one of these bits, the corresponding USB interrupt status bit is set. When this register is read, the same value as the USB interrupt status register is returned. - 0x1E + 30 1 read-write DEV_SET_INT If software writes a one to one of these bits, the corresponding USB interrupt status bit is set. When this register is read, the same value as the USB interrupt status register is returned. - 0x1F + 31 1 read-write @@ -20315,7 +20341,7 @@ CLKMODE SCT clock mode - 0x1 + 1 2 read-write @@ -20344,7 +20370,7 @@ CKSEL SCT clock select. The specific functionality of the designated input/edge is dependent on the CLKMODE bit selection in this register. - 0x3 + 3 4 read-write @@ -20393,35 +20419,35 @@ NORELAOD_L A 1 in this bit prevents the lower match registers from being reloaded from their respective reload registers. Setting this bit eliminates the need to write to the reload registers MATCHREL if the match values are fixed. Software can write to set or clear this bit at any time. This bit applies to both the higher and lower registers when the UNIFY bit is set. - 0x7 + 7 1 read-write NORELOAD_H A 1 in this bit prevents the higher match registers from being reloaded from their respective reload registers. Setting this bit eliminates the need to write to the reload registers MATCHREL if the match values are fixed. Software can write to set or clear this bit at any time. This bit is not used when the UNIFY bit is set. - 0x8 + 8 1 read-write INSYNC Synchronization for input N (bit 9 = input 0, bit 10 = input 1,, bit 12 = input 3); all other bits are reserved. A 1 in one of these bits subjects the corresponding input to synchronization to the SCT clock, before it is used to create an event. If an input is known to already be synchronous to the SCT clock, this bit may be set to 0 for faster input response. (Note: The SCT clock is the system clock for CKMODEs 0-2. It is the selected, asynchronous SCT input clock for CKMODE3). Note that the INSYNC field only affects inputs used for event generation. It does not apply to the clock input specified in the CKSEL field. - 0x9 + 9 4 read-write AUTOLIMIT_L A one in this bit causes a match on match register 0 to be treated as a de-facto LIMIT condition without the need to define an associated event. As with any LIMIT event, this automatic limit causes the counter to be cleared to zero in unidirectional mode or to change the direction of count in bi-directional mode. Software can write to set or clear this bit at any time. This bit applies to both the higher and lower registers when the UNIFY bit is set. - 0x11 + 17 1 read-write AUTOLIMIT_H A one in this bit will cause a match on match register 0 to be treated as a de-facto LIMIT condition without the need to define an associated event. As with any LIMIT event, this automatic limit causes the counter to be cleared to zero in unidirectional mode or to change the direction of count in bi-directional mode. Software can write to set or clear this bit at any time. This bit is not used when the UNIFY bit is set. - 0x12 + 18 1 read-write @@ -20446,28 +20472,28 @@ STOP_L When this bit is 1 and HALT is 0, the L or unified counter does not run, but I/O events related to the counter can occur. If a designated start event occurs, this bit is cleared and counting resumes. - 0x1 + 1 1 read-write HALT_L When this bit is 1, the L or unified counter does not run and no events can occur. A reset sets this bit. When the HALT_L bit is one, the STOP_L bit is cleared. It is possible to remove the halt condition while keeping the SCT in the stop condition (not running) with a single write to this register to simultaneously clear the HALT bit and set the STOP bit. Once set, only software can clear this bit to restore counter operation. This bit is set on reset. - 0x2 + 2 1 read-write CLRCTR_L Writing a 1 to this bit clears the L or unified counter. This bit always reads as 0. - 0x3 + 3 1 read-write BIDIR_L L or unified counter direction select - 0x4 + 4 1 read-write @@ -20486,42 +20512,42 @@ PRE_L Specifies the factor by which the SCT clock is prescaled to produce the L or unified counter clock. The counter clock is clocked at the rate of the SCT clock divided by PRE_L+1. Clear the counter (by writing a 1 to the CLRCTR bit) whenever changing the PRE value. - 0x5 + 5 8 read-write DOWN_H This bit is 1 when the H counter is counting down. Hardware sets this bit when the counter is counting, a counter limit condition occurs, and BIDIR is 1. Hardware clears this bit when the counter is counting down and a limit condition occurs or when the counter reaches 0. - 0x10 + 16 1 read-write STOP_H When this bit is 1 and HALT is 0, the H counter does not, run but I/O events related to the counter can occur. If such an event matches the mask in the Start register, this bit is cleared and counting resumes. - 0x11 + 17 1 read-write HALT_H When this bit is 1, the H counter does not run and no events can occur. A reset sets this bit. When the HALT_H bit is one, the STOP_H bit is cleared. It is possible to remove the halt condition while keeping the SCT in the stop condition (not running) with a single write to this register to simultaneously clear the HALT bit and set the STOP bit. Once set, this bit can only be cleared by software to restore counter operation. This bit is set on reset. - 0x12 + 18 1 read-write CLRCTR_H Writing a 1 to this bit clears the H counter. This bit always reads as 0. - 0x13 + 19 1 read-write BIDIR_H Direction select - 0x14 + 20 1 read-write @@ -20540,7 +20566,7 @@ PRE_H Specifies the factor by which the SCT clock is prescaled to produce the H counter clock. The counter clock is clocked at the rate of the SCT clock divided by PRELH+1. Clear the counter (by writing a 1 to the CLRCTR bit) whenever changing the PRE value. - 0x15 + 21 8 read-write @@ -20565,7 +20591,7 @@ LIMMSK_H If bit n is one, event n is used as a counter limit for the H counter (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of events in this SCT. - 0x10 + 16 16 read-write @@ -20590,7 +20616,7 @@ HALTMSK_H If bit n is one, event n sets the HALT_H bit in the CTRL register (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of events in this SCT. - 0x10 + 16 16 read-write @@ -20615,7 +20641,7 @@ STOPMSK_H If bit n is one, event n sets the STOP_H bit in the CTRL register (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of events in this SCT. - 0x10 + 16 16 read-write @@ -20640,7 +20666,7 @@ STARTMSK_H If bit n is one, event n clears the STOP_H bit in the CTRL register (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of events in this SCT. - 0x10 + 16 16 read-write @@ -20665,7 +20691,7 @@ CTR_H When UNIFY = 0, read or write the 16-bit H counter value. When UNIFY = 1, read or write the upper 16 bits of the 32-bit unified counter. - 0x10 + 16 16 read-write @@ -20690,7 +20716,7 @@ STATE_H State variable. - 0x10 + 16 5 read-write @@ -20715,217 +20741,217 @@ AIN1 Input 1 state. Input 1 state on the last SCT clock edge. - 0x1 + 1 1 read-only AIN2 Input 2 state. Input 2 state on the last SCT clock edge. - 0x2 + 2 1 read-only AIN3 Input 3 state. Input 3 state on the last SCT clock edge. - 0x3 + 3 1 read-only AIN4 Input 4 state. Input 4 state on the last SCT clock edge. - 0x4 + 4 1 read-only AIN5 Input 5 state. Input 5 state on the last SCT clock edge. - 0x5 + 5 1 read-only AIN6 Input 6 state. Input 6 state on the last SCT clock edge. - 0x6 + 6 1 read-only AIN7 Input 7 state. Input 7 state on the last SCT clock edge. - 0x7 + 7 1 read-only AIN8 Input 8 state. Input 8 state on the last SCT clock edge. - 0x8 + 8 1 read-only AIN9 Input 9 state. Input 9 state on the last SCT clock edge. - 0x9 + 9 1 read-only AIN10 Input 10 state. Input 10 state on the last SCT clock edge. - 0xA + 10 1 read-only AIN11 Input 11 state. Input 11 state on the last SCT clock edge. - 0xB + 11 1 read-only AIN12 Input 12 state. Input 12 state on the last SCT clock edge. - 0xC + 12 1 read-only AIN13 Input 13 state. Input 13 state on the last SCT clock edge. - 0xD + 13 1 read-only AIN14 Input 14 state. Input 14 state on the last SCT clock edge. - 0xE + 14 1 read-only AIN15 Input 15 state. Input 15 state on the last SCT clock edge. - 0xF + 15 1 read-only SIN0 Input 0 state. Input 0 state following the synchronization specified by INSYNC. - 0x10 + 16 1 read-only SIN1 Input 1 state. Input 1 state following the synchronization specified by INSYNC. - 0x11 + 17 1 read-only SIN2 Input 2 state. Input 2 state following the synchronization specified by INSYNC. - 0x12 + 18 1 read-only SIN3 Input 3 state. Input 3 state following the synchronization specified by INSYNC. - 0x13 + 19 1 read-only SIN4 Input 4 state. Input 4 state following the synchronization specified by INSYNC. - 0x14 + 20 1 read-only SIN5 Input 5 state. Input 5 state following the synchronization specified by INSYNC. - 0x15 + 21 1 read-only SIN6 Input 6 state. Input 6 state following the synchronization specified by INSYNC. - 0x16 + 22 1 read-only SIN7 Input 7 state. Input 7 state following the synchronization specified by INSYNC. - 0x17 + 23 1 read-only SIN8 Input 8 state. Input 8 state following the synchronization specified by INSYNC. - 0x18 + 24 1 read-only SIN9 Input 9 state. Input 9 state following the synchronization specified by INSYNC. - 0x19 + 25 1 read-only SIN10 Input 10 state. Input 10 state following the synchronization specified by INSYNC. - 0x1A + 26 1 read-only SIN11 Input 11 state. Input 11 state following the synchronization specified by INSYNC. - 0x1B + 27 1 read-only SIN12 Input 12 state. Input 12 state following the synchronization specified by INSYNC. - 0x1C + 28 1 read-only SIN13 Input 13 state. Input 13 state following the synchronization specified by INSYNC. - 0x1D + 29 1 read-only SIN14 Input 14 state. Input 14 state following the synchronization specified by INSYNC. - 0x1E + 30 1 read-only SIN15 Input 15 state. Input 15 state following the synchronization specified by INSYNC. - 0x1F + 31 1 read-only @@ -20950,7 +20976,7 @@ REGMOD_H Each bit controls one match/capture register (register 0 = bit 16, register 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT. 0 = register operates as match registers. 1 = register operates as capture registers. - 0x10 + 16 16 read-write @@ -21010,7 +21036,7 @@ SETCLR1 Set/clear operation on output 1. Value 0x3 is reserved. Do not program this value. - 0x2 + 2 2 read-write @@ -21034,7 +21060,7 @@ SETCLR2 Set/clear operation on output 2. Value 0x3 is reserved. Do not program this value. - 0x4 + 4 2 read-write @@ -21058,7 +21084,7 @@ SETCLR3 Set/clear operation on output 3. Value 0x3 is reserved. Do not program this value. - 0x6 + 6 2 read-write @@ -21082,7 +21108,7 @@ SETCLR4 Set/clear operation on output 4. Value 0x3 is reserved. Do not program this value. - 0x8 + 8 2 read-write @@ -21106,7 +21132,7 @@ SETCLR5 Set/clear operation on output 5. Value 0x3 is reserved. Do not program this value. - 0xA + 10 2 read-write @@ -21130,7 +21156,7 @@ SETCLR6 Set/clear operation on output 6. Value 0x3 is reserved. Do not program this value. - 0xC + 12 2 read-write @@ -21154,7 +21180,7 @@ SETCLR7 Set/clear operation on output 7. Value 0x3 is reserved. Do not program this value. - 0xE + 14 2 read-write @@ -21178,7 +21204,7 @@ SETCLR8 Set/clear operation on output 8. Value 0x3 is reserved. Do not program this value. - 0x10 + 16 2 read-write @@ -21202,7 +21228,7 @@ SETCLR9 Set/clear operation on output 9. Value 0x3 is reserved. Do not program this value. - 0x12 + 18 2 read-write @@ -21226,7 +21252,7 @@ SETCLR10 Set/clear operation on output 10. Value 0x3 is reserved. Do not program this value. - 0x14 + 20 2 read-write @@ -21250,7 +21276,7 @@ SETCLR11 Set/clear operation on output 11. Value 0x3 is reserved. Do not program this value. - 0x16 + 22 2 read-write @@ -21274,7 +21300,7 @@ SETCLR12 Set/clear operation on output 12. Value 0x3 is reserved. Do not program this value. - 0x18 + 24 2 read-write @@ -21298,7 +21324,7 @@ SETCLR13 Set/clear operation on output 13. Value 0x3 is reserved. Do not program this value. - 0x1A + 26 2 read-write @@ -21322,7 +21348,7 @@ SETCLR14 Set/clear operation on output 14. Value 0x3 is reserved. Do not program this value. - 0x1C + 28 2 read-write @@ -21346,7 +21372,7 @@ SETCLR15 Set/clear operation on output 15. Value 0x3 is reserved. Do not program this value. - 0x1E + 30 2 read-write @@ -21410,7 +21436,7 @@ O1RES Effect of simultaneous set and clear on output 1. - 0x2 + 2 2 read-write @@ -21439,7 +21465,7 @@ O2RES Effect of simultaneous set and clear on output 2. - 0x4 + 4 2 read-write @@ -21468,7 +21494,7 @@ O3RES Effect of simultaneous set and clear on output 3. - 0x6 + 6 2 read-write @@ -21497,7 +21523,7 @@ O4RES Effect of simultaneous set and clear on output 4. - 0x8 + 8 2 read-write @@ -21526,7 +21552,7 @@ O5RES Effect of simultaneous set and clear on output 5. - 0xA + 10 2 read-write @@ -21555,7 +21581,7 @@ O6RES Effect of simultaneous set and clear on output 6. - 0xC + 12 2 read-write @@ -21584,7 +21610,7 @@ O7RES Effect of simultaneous set and clear on output 7. - 0xE + 14 2 read-write @@ -21613,7 +21639,7 @@ O8RES Effect of simultaneous set and clear on output 8. - 0x10 + 16 2 read-write @@ -21642,7 +21668,7 @@ O9RES Effect of simultaneous set and clear on output 9. - 0x12 + 18 2 read-write @@ -21671,7 +21697,7 @@ O10RES Effect of simultaneous set and clear on output 10. - 0x14 + 20 2 read-write @@ -21700,7 +21726,7 @@ O11RES Effect of simultaneous set and clear on output 11. - 0x16 + 22 2 read-write @@ -21729,7 +21755,7 @@ O12RES Effect of simultaneous set and clear on output 12. - 0x18 + 24 2 read-write @@ -21758,7 +21784,7 @@ O13RES Effect of simultaneous set and clear on output 13. - 0x1A + 26 2 read-write @@ -21787,7 +21813,7 @@ O14RES Effect of simultaneous set and clear on output 14. - 0x1C + 28 2 read-write @@ -21816,7 +21842,7 @@ O15RES Effect of simultaneous set and clear on output 15. - 0x1E + 30 2 read-write @@ -21863,14 +21889,14 @@ DRL0 A 1 in this bit triggers DMA request 0 when it loads the MATCH_L/Unified registers from the RELOAD_L/Unified registers. - 0x1E + 30 1 read-write DRQ0 This read-only bit indicates the state of DMA Request 0. Note that if the related DMA channel is enabled and properly set up, it is unlikely that software will see this flag, it will be cleared rapidly by the DMA service. The flag remaining set could point to an issue with DMA setup. - 0x1F + 31 1 read-write @@ -21895,14 +21921,14 @@ DRL1 A 1 in this bit triggers DMA request 1 when it loads the Match L/Unified registers from the Reload L/Unified registers. - 0x1E + 30 1 read-write DRQ1 This read-only bit indicates the state of DMA Request 1. Note that if the related DMA channel is enabled and properly set up, it is unlikely that software will see this flag, it will be cleared rapidly by the DMA service. The flag remaining set could point to an issue with DMA setup. - 0x1F + 31 1 read-write @@ -21981,14 +22007,14 @@ BUSERRL The most recent bus error from this SCT involved writing CTR L/Unified, STATE L/Unified, MATCH L/Unified, or the Output register when the L/U counter was not halted. A word write to certain L and H registers can be half successful and half unsuccessful. - 0x1E + 30 1 read-write BUSERRH The most recent bus error from this SCT involved writing CTR H, STATE H, MATCH H, or the Output register when the H counter was not halted. - 0x1F + 31 1 read-write @@ -22016,7 +22042,7 @@ CAPn_H When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured. - 0x10 + 16 16 read-write @@ -22044,7 +22070,7 @@ MATCHn_H When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter. - 0x10 + 16 16 read-write @@ -22072,7 +22098,7 @@ CAPCONn_H If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT. - 0x10 + 16 16 read-write @@ -22100,7 +22126,7 @@ RELOADn_H When UNIFY = 0, specifies the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn register. - 0x10 + 16 16 read-write @@ -22149,7 +22175,7 @@ HEVENT Select L/H counter. Do not set this bit if UNIFY = 1. - 0x4 + 4 1 read-write @@ -22168,7 +22194,7 @@ OUTSEL Input/output select - 0x5 + 5 1 read-write @@ -22187,14 +22213,14 @@ IOSEL Selects the input or output signal number associated with this event (if any). Do not select an input in this register if CKMODE is 1x. In this case the clock input is an implicit ingredient of every event. - 0x6 + 6 4 read-write IOCOND Selects the I/O condition for event n. (The detection of edges on outputs lag the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT clock period . - 0xA + 10 2 read-write @@ -22223,7 +22249,7 @@ COMBMODE Selects how the specified match and I/O condition are used and combined. - 0xC + 12 2 read-write @@ -22252,7 +22278,7 @@ STATELD This bit controls how the STATEV value modifies the state selected by HEVENT when this event is the highest-numbered event occurring for that state. - 0xE + 14 1 read-write @@ -22271,21 +22297,21 @@ STATEV This value is loaded into or added to the state selected by HEVENT, depending on STATELD, when this event is the highest-numbered event occurring for that state. If STATELD and STATEV are both zero, there is no change to the STATE value. - 0xF + 15 5 read-write MATCHMEM If this bit is one and the COMBMODE field specifies a match component to the triggering of this event, then a match is considered to be active whenever the counter value is GREATER THAN OR EQUAL TO the value specified in the match register when counting up, LESS THEN OR EQUAL TO the match value when counting down. If this bit is zero, a match is only be active during the cycle when the counter is equal to the match value. - 0x14 + 20 1 read-write DIRECTION Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved. - 0x15 + 21 2 read-write @@ -22367,8 +22393,8 @@ FLEXCOMM0 LPC5411x Flexcomm serial communication FLEXCOMM - 0x40086000 FLEXCOMM + 0x40086000 0 0x1000 @@ -22430,7 +22456,7 @@ LOCK Lock the peripheral select. This field is writable by software. - 0x3 + 3 1 read-write @@ -22449,7 +22475,7 @@ USARTPRESENT USART present indicator. This field is Read-only. - 0x4 + 4 1 read-only @@ -22468,7 +22494,7 @@ SPIPRESENT SPI present indicator. This field is Read-only. - 0x5 + 5 1 read-only @@ -22487,7 +22513,7 @@ I2CPRESENT I2C present indicator. This field is Read-only. - 0x6 + 6 1 read-only @@ -22506,7 +22532,7 @@ I2SPRESENT I 2S present indicator. This field is Read-only. - 0x7 + 7 1 read-only @@ -22525,7 +22551,7 @@ ID Flexcomm ID. - 0xC + 12 20 read-only @@ -22543,21 +22569,21 @@ Minor_Rev Minor revision of module implementation. - 0x8 + 8 4 read-only Major_Rev Major revision of module implementation. - 0xC + 12 4 read-only ID Module identifier for the selected function. - 0x10 + 16 16 read-only @@ -22565,13 +22591,118 @@ + + FLEXCOMM1 + LPC5411x Flexcomm serial communication + FLEXCOMM + 0x40087000 + + 0 + 0x1000 + registers + + + FLEXCOMM1 + 15 + + + + FLEXCOMM2 + LPC5411x Flexcomm serial communication + FLEXCOMM + 0x40088000 + + 0 + 0x1000 + registers + + + FLEXCOMM2 + 16 + + + + FLEXCOMM3 + LPC5411x Flexcomm serial communication + FLEXCOMM + 0x40089000 + + 0 + 0x1000 + registers + + + FLEXCOMM3 + 17 + + + + FLEXCOMM4 + LPC5411x Flexcomm serial communication + FLEXCOMM + 0x4008A000 + + 0 + 0x1000 + registers + + + FLEXCOMM4 + 18 + + + + FLEXCOMM5 + LPC5411x Flexcomm serial communication + FLEXCOMM + 0x40096000 + + 0 + 0x1000 + registers + + + FLEXCOMM5 + 19 + + + + FLEXCOMM6 + LPC5411x Flexcomm serial communication + FLEXCOMM + 0x40097000 + + 0 + 0x1000 + registers + + + FLEXCOMM6 + 20 + + + + FLEXCOMM7 + LPC5411x Flexcomm serial communication + FLEXCOMM + 0x40098000 + + 0 + 0x1000 + registers + + + FLEXCOMM7 + 21 + + I2C0 - FLEXCOMM0 LPC5411x I2C-bus interfaces + FLEXCOMM0 I2C - 0x40086000 I2C + 0x40086000 0 0x884 @@ -22613,7 +22744,7 @@ SLVEN Slave Enable. When disabled, configurations settings for the Slave function are not changed, but the Slave function is internally reset. - 0x1 + 1 1 read-write @@ -22632,7 +22763,7 @@ MONEN Monitor Enable. When disabled, configurations settings for the Monitor function are not changed, but the Monitor function is internally reset. - 0x2 + 2 1 read-write @@ -22651,7 +22782,7 @@ TIMEOUTEN I2C bus Time-out Enable. When disabled, the time-out function is internally reset. - 0x3 + 3 1 read-write @@ -22670,7 +22801,7 @@ MONCLKSTR Monitor function Clock Stretching. - 0x4 + 4 1 read-write @@ -22689,7 +22820,7 @@ HSCAPABLE High-speed mode Capable enable. Since High Speed mode alters the way I2C pins drive and filter, as well as the timing for certain I2C signalling, enabling High-speed mode applies to all functions: Master, Slave, and Monitor. - 0x5 + 5 1 read-write @@ -22738,7 +22869,7 @@ MSTSTATE Master State code. The master state code reflects the master state when the MSTPENDING bit is set, that is the master is pending or in the idle state. Each value of this field indicates a specific required service for the Master function. All other values are reserved. See Table 400 for details of state values and appropriate responses. - 0x1 + 1 3 read-only @@ -22772,7 +22903,7 @@ MSTARBLOSS Master Arbitration Loss flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE. - 0x4 + 4 1 read-write @@ -22791,7 +22922,7 @@ MSTSTSTPERR Master Start/Stop Error flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE. - 0x6 + 6 1 read-write @@ -22810,7 +22941,7 @@ SLVPENDING Slave Pending. Indicates that the Slave function is waiting to continue communication on the I2C-bus and needs software service. This flag will cause an interrupt when set if enabled via INTENSET. The SLVPENDING flag is not set when the DMA is handling an event (if the SLVDMA bit in the SLVCTL register is set). The SLVPENDING flag is read-only and is automatically cleared when a 1 is written to the SLVCONTINUE bit in the SLVCTL register. The point in time when SlvPending is set depends on whether the I2C interface is in HSCAPABLE mode. See Section 25.7.2.2.2. When the I2C interface is configured to be HSCAPABLE, HS master codes are detected automatically. Due to the requirements of the HS I2C specification, slave addresses must also be detected automatically, since the address must be acknowledged before the clock can be stretched. - 0x8 + 8 1 read-only @@ -22829,7 +22960,7 @@ SLVSTATE Slave State code. Each value of this field indicates a specific required service for the Slave function. All other values are reserved. See Table 401 for state values and actions. note that the occurrence of some states and how they are handled are affected by DMA mode and Automatic Operation modes. - 0x9 + 9 2 read-only @@ -22853,7 +22984,7 @@ SLVNOTSTR Slave Not Stretching. Indicates when the slave function is stretching the I2C clock. This is needed in order to gracefully invoke Deep Sleep or Power-down modes during slave operation. This read-only flag reflects the slave function status in real time. - 0xB + 11 1 read-only @@ -22872,7 +23003,7 @@ SLVIDX Slave address match Index. This field is valid when the I2C slave function has been selected by receiving an address that matches one of the slave addresses defined by any enabled slave address registers, and provides an identification of the address that was matched. It is possible that more than one address could be matched, but only one match can be reported here. - 0xC + 12 2 read-only @@ -22901,7 +23032,7 @@ SLVSEL Slave selected flag. SLVSEL is set after an address match when software tells the Slave function to acknowledge the address, or when the address has been automatically acknowledged. It is cleared when another address cycle presents an address that does not match an enabled address on the Slave function, when slave software decides to NACK a matched address, when there is a Stop detected on the bus, when the master NACKs slave data, and in some combinations of Automatic Operation. SLVSEL is not cleared if software NACKs data. - 0xE + 14 1 read-only @@ -22920,7 +23051,7 @@ SLVDESEL Slave Deselected flag. This flag will cause an interrupt when set if enabled via INTENSET. This flag can be cleared by writing a 1 to this bit. - 0xF + 15 1 read-write @@ -22939,7 +23070,7 @@ MONRDY Monitor Ready. This flag is cleared when the MONRXDAT register is read. - 0x10 + 16 1 read-only @@ -22958,7 +23089,7 @@ MONOV Monitor Overflow flag. - 0x11 + 17 1 read-write @@ -22977,7 +23108,7 @@ MONACTIVE Monitor Active flag. Indicates when the Monitor function considers the I 2C bus to be active. Active is defined here as when some Master is on the bus: a bus Start has occurred more recently than a bus Stop. - 0x12 + 18 1 read-only @@ -22996,7 +23127,7 @@ MONIDLE Monitor Idle flag. This flag is set when the Monitor function sees the I2C bus change from active to inactive. This can be used by software to decide when to process data accumulated by the Monitor function. This flag will cause an interrupt when set if enabled via the INTENSET register. The flag can be cleared by writing a 1 to this bit. - 0x13 + 19 1 read-write @@ -23015,7 +23146,7 @@ EVENTTIMEOUT Event Time-out Interrupt flag. Indicates when the time between events has been longer than the time specified by the TIMEOUT register. Events include Start, Stop, and clock edges. The flag is cleared by writing a 1 to this bit. No time-out is created when the I2C-bus is idle. - 0x18 + 24 1 read-write @@ -23034,7 +23165,7 @@ SCLTIMEOUT SCL Time-out Interrupt flag. Indicates when SCL has remained low longer than the time specific by the TIMEOUT register. The flag is cleared by writing a 1 to this bit. - 0x19 + 25 1 read-write @@ -23083,7 +23214,7 @@ MSTARBLOSSEN Master Arbitration Loss interrupt Enable. - 0x4 + 4 1 read-write @@ -23102,7 +23233,7 @@ MSTSTSTPERREN Master Start/Stop Error interrupt Enable. - 0x6 + 6 1 read-write @@ -23121,7 +23252,7 @@ SLVPENDINGEN Slave Pending interrupt Enable. - 0x8 + 8 1 read-write @@ -23140,7 +23271,7 @@ SLVNOTSTREN Slave Not Stretching interrupt Enable. - 0xB + 11 1 read-write @@ -23159,7 +23290,7 @@ SLVDESELEN Slave Deselect interrupt Enable. - 0xF + 15 1 read-write @@ -23178,7 +23309,7 @@ MONRDYEN Monitor data Ready interrupt Enable. - 0x10 + 16 1 read-write @@ -23197,7 +23328,7 @@ MONOVEN Monitor Overrun interrupt Enable. - 0x11 + 17 1 read-write @@ -23216,7 +23347,7 @@ MONIDLEEN Monitor Idle interrupt Enable. - 0x13 + 19 1 read-write @@ -23235,7 +23366,7 @@ EVENTTIMEOUTEN Event time-out interrupt Enable. - 0x18 + 24 1 read-write @@ -23254,7 +23385,7 @@ SCLTIMEOUTEN SCL time-out interrupt Enable. - 0x19 + 25 1 read-write @@ -23291,70 +23422,70 @@ MSTARBLOSSCLR Master Arbitration Loss interrupt clear. - 0x4 + 4 1 write-only MSTSTSTPERRCLR Master Start/Stop Error interrupt clear. - 0x6 + 6 1 write-only SLVPENDINGCLR Slave Pending interrupt clear. - 0x8 + 8 1 write-only SLVNOTSTRCLR Slave Not Stretching interrupt clear. - 0xB + 11 1 write-only SLVDESELCLR Slave Deselect interrupt clear. - 0xF + 15 1 write-only MONRDYCLR Monitor data Ready interrupt clear. - 0x10 + 16 1 write-only MONOVCLR Monitor Overrun interrupt clear. - 0x11 + 17 1 write-only MONIDLECLR Monitor Idle interrupt clear. - 0x13 + 19 1 write-only EVENTTIMEOUTCLR Event time-out interrupt clear. - 0x18 + 24 1 write-only SCLTIMEOUTCLR SCL time-out interrupt clear. - 0x19 + 25 1 write-only @@ -23379,7 +23510,7 @@ TO Time-out time value. Specifies the time-out interval value in increments of 16 I 2C function clocks, as defined by the CLKDIV register. To change this value while I2C is in operation, disable all time-outs, write a new value to TIMEOUT, then re-enable time-outs. 0x000 = A time-out will occur after 16 counts of the I2C function clock. 0x001 = A time-out will occur after 32 counts of the I2C function clock. 0xFFF = A time-out will occur after 65,536 counts of the I2C function clock. - 0x4 + 4 12 read-write @@ -23422,70 +23553,70 @@ MSTARBLOSS Master Arbitration Loss flag. - 0x4 + 4 1 read-only MSTSTSTPERR Master Start/Stop Error flag. - 0x6 + 6 1 read-only SLVPENDING Slave Pending. - 0x8 + 8 1 read-only SLVNOTSTR Slave Not Stretching status. - 0xB + 11 1 read-only SLVDESEL Slave Deselected flag. - 0xF + 15 1 read-only MONRDY Monitor Ready. - 0x10 + 16 1 read-only MONOV Monitor Overflow flag. - 0x11 + 17 1 read-only MONIDLE Monitor Idle flag. - 0x13 + 19 1 read-only EVENTTIMEOUT Event time-out Interrupt flag. - 0x18 + 24 1 read-only SCLTIMEOUT SCL time-out Interrupt flag. - 0x19 + 25 1 read-only @@ -23522,7 +23653,7 @@ MSTSTART Master Start control. This bit is write-only. - 0x1 + 1 1 read-write @@ -23541,7 +23672,7 @@ MSTSTOP Master Stop control. This bit is write-only. - 0x2 + 2 1 read-write @@ -23560,7 +23691,7 @@ MSTDMA Master DMA enable. Data operations of the I2C can be performed with DMA. Protocol type operations such as Start, address, Stop, and address match must always be done with software, typically via an interrupt. Address acknowledgement must also be done by software except when the I2C is configured to be HSCAPABLE (and address acknowledgement is handled entirely by hardware) or when Automatic Operation is enabled. When a DMA data transfer is complete, MSTDMA must be cleared prior to beginning the next operation, typically a Start or Stop.This bit is read/write. - 0x3 + 3 1 read-write @@ -23639,7 +23770,7 @@ MSTSCLHIGH Master SCL High time. Specifies the minimum high time that will be asserted by this master on SCL. Other masters in a multi-master system could shorten this time. This corresponds to the parameter tHIGH in the I2C bus specification. I2C bus specification parameters tSU;STO and tHD;STA have the same values and are also controlled by MSTSCLHIGH. - 0x4 + 4 3 read-write @@ -23736,7 +23867,7 @@ SLVNACK Slave NACK. - 0x1 + 1 1 read-write @@ -23755,7 +23886,7 @@ SLVDMA Slave DMA enable. - 0x3 + 3 1 read-write @@ -23774,7 +23905,7 @@ AUTOACK Automatic Acknowledge.When this bit is set, it will cause an I2C header which matches SLVADR0 and the direction set by AUTOMATCHREAD to be ACKed immediately; this is used with DMA to allow processing of the data without intervention. If this bit is clear and a header matches SLVADR0, the behavior is controlled by AUTONACK in the SLVADR0 register: allowing NACK or interrupt. - 0x8 + 8 1 read-write @@ -23793,7 +23924,7 @@ AUTOMATCHREAD When AUTOACK is set, this bit controls whether it matches a read or write request on the next header with an address matching SLVADR0. Since DMA needs to be configured to match the transfer direction, the direction needs to be specified. This bit allows a direction to be chosen for the next operation. - 0x9 + 9 1 read-write @@ -23862,14 +23993,14 @@ SLVADR Slave Address. Seven bit slave address that is compared to received addresses if enabled. - 0x1 + 1 7 read-write AUTONACK Automatic NACK operation. Used in conjunction with AUTOACK and AUTOMATCHREAD, allows software to ignore I2C traffic while handling previous I2C data or other operations. - 0xF + 15 1 read-write @@ -23918,7 +24049,7 @@ SLVQUAL0 Slave address Qualifier for address 0. A value of 0 causes the address in SLVADR0 to be used as-is, assuming that it is enabled. If QUALMODE0 = 0, any bit in this field which is set to 1 will cause an automatic match of the corresponding bit of the received address when it is compared to the SLVADR0 register. If QUALMODE0 = 1, an address range is matched for address 0. This range extends from the value defined by SLVADR0 to the address defined by SLVQUAL0 (address matches when SLVADR0[7:1] <= received address <= SLVQUAL0[7:1]). - 0x1 + 1 7 read-write @@ -23943,7 +24074,7 @@ MONSTART Monitor Received Start. - 0x8 + 8 1 read-only @@ -23962,7 +24093,7 @@ MONRESTART Monitor Received Repeated Start. - 0x9 + 9 1 read-only @@ -23981,7 +24112,7 @@ MONNACK Monitor Received NACK. - 0xA + 10 1 read-only @@ -24001,13 +24132,125 @@ + + I2C1 + LPC5411x I2C-bus interfaces + FLEXCOMM1 + I2C + 0x40087000 + + 0 + 0x884 + registers + + + FLEXCOMM1 + 15 + + + + I2C2 + LPC5411x I2C-bus interfaces + FLEXCOMM2 + I2C + 0x40088000 + + 0 + 0x884 + registers + + + FLEXCOMM2 + 16 + + + + I2C3 + LPC5411x I2C-bus interfaces + FLEXCOMM3 + I2C + 0x40089000 + + 0 + 0x884 + registers + + + FLEXCOMM3 + 17 + + + + I2C4 + LPC5411x I2C-bus interfaces + FLEXCOMM4 + I2C + 0x4008A000 + + 0 + 0x884 + registers + + + FLEXCOMM4 + 18 + + + + I2C5 + LPC5411x I2C-bus interfaces + FLEXCOMM5 + I2C + 0x40096000 + + 0 + 0x884 + registers + + + FLEXCOMM5 + 19 + + + + I2C6 + LPC5411x I2C-bus interfaces + FLEXCOMM6 + I2C + 0x40097000 + + 0 + 0x884 + registers + + + FLEXCOMM6 + 20 + + + + I2C7 + LPC5411x I2C-bus interfaces + FLEXCOMM7 + I2C + 0x40098000 + + 0 + 0x884 + registers + + + FLEXCOMM7 + 21 + + SPI0 - FLEXCOMM0 LPC5411x Serial Peripheral Interfaces (SPI) + FLEXCOMM0 SPI - 0x40086000 SPI + 0x40086000 0 0xE44 @@ -24049,7 +24292,7 @@ MASTER Master mode select. - 0x2 + 2 1 read-write @@ -24068,7 +24311,7 @@ LSBF LSB First mode enable. - 0x3 + 3 1 read-write @@ -24087,7 +24330,7 @@ CPHA Clock Phase select. - 0x4 + 4 1 read-write @@ -24106,7 +24349,7 @@ CPOL Clock Polarity select. - 0x5 + 5 1 read-write @@ -24125,7 +24368,7 @@ LOOP Loopback mode enable. Loopback mode applies only to Master mode, and connects transmit and receive data connected together to allow simple software testing. - 0x7 + 7 1 read-write @@ -24144,7 +24387,7 @@ SPOL0 SSEL0 Polarity select. - 0x8 + 8 1 read-write @@ -24163,7 +24406,7 @@ SPOL1 SSEL1 Polarity select. - 0x9 + 9 1 read-write @@ -24182,7 +24425,7 @@ SPOL2 SSEL2 Polarity select. - 0xA + 10 1 read-write @@ -24201,7 +24444,7 @@ SPOL3 SSEL3 Polarity select. - 0xB + 11 1 read-write @@ -24238,21 +24481,21 @@ POST_DELAY Controls the amount of time between the end of a data transfer and SSEL deassertion. 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are inserted. - 0x4 + 4 4 read-write FRAME_DELAY If the EOF flag is set, controls the minimum amount of time between the current frame and the next frame (or SSEL deassertion if EOT). 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are inserted. - 0x8 + 8 4 read-write TRANSFER_DELAY Controls the minimum amount of time that the SSEL is deasserted between transfers. 0x0 = The minimum time that SSEL is deasserted is 1 SPI clock time. (Zero added time.) 0x1 = The minimum time that SSEL is deasserted is 2 SPI clock times. 0x2 = The minimum time that SSEL is deasserted is 3 SPI clock times. 0xF = The minimum time that SSEL is deasserted is 16 SPI clock times. - 0xC + 12 4 read-write @@ -24270,35 +24513,35 @@ SSA Slave Select Assert. This flag is set whenever any slave select transitions from deasserted to asserted, in both master and slave modes. This allows determining when the SPI transmit/receive functions become busy, and allows waking up the device from reduced power modes when a slave mode access begins. This flag is cleared by software. - 0x4 + 4 1 write-only SSD Slave Select Deassert. This flag is set whenever any asserted slave selects transition to deasserted, in both master and slave modes. This allows determining when the SPI transmit/receive functions become idle. This flag is cleared by software. - 0x5 + 5 1 write-only STALLED Stalled status flag. This indicates whether the SPI is currently in a stall condition. - 0x6 + 6 1 read-only ENDTRANSFER End Transfer control bit. Software can set this bit to force an end to the current transfer when the transmitter finishes any activity already in progress, as if the EOT flag had been set prior to the last transmission. This capability is included to support cases where it is not known when transmit data is written that it will be the end of a transfer. The bit is cleared when the transmitter becomes idle as the transfer comes to an end. Forcing an end of transfer in this manner causes any specified FRAME_DELAY and TRANSFER_DELAY to be inserted. - 0x7 + 7 1 read-write MSTIDLE Master idle status flag. This bit is 1 whenever the SPI master function is fully idle. This means that the transmit holding register is empty and the transmitter is not in the process of sending data. - 0x8 + 8 1 read-only @@ -24316,7 +24559,7 @@ SSAEN Slave select assert interrupt enable. Determines whether an interrupt occurs when the Slave Select is asserted. - 0x4 + 4 1 read-write @@ -24335,7 +24578,7 @@ SSDEN Slave select deassert interrupt enable. Determines whether an interrupt occurs when the Slave Select is deasserted. - 0x5 + 5 1 read-write @@ -24354,7 +24597,7 @@ MSTIDLEEN Master idle interrupt enable. - 0x8 + 8 1 read-write @@ -24384,21 +24627,21 @@ SSAEN Writing 1 clears the corresponding bit in the INTENSET register. - 0x4 + 4 1 write-only SSDEN Writing 1 clears the corresponding bit in the INTENSET register. - 0x5 + 5 1 write-only MSTIDLE Writing 1 clears the corresponding bit in the INTENSET register. - 0x8 + 8 1 write-only @@ -24434,21 +24677,21 @@ SSA Slave Select Assert. - 0x4 + 4 1 read-only SSD Slave Select Deassert. - 0x5 + 5 1 read-only MSTIDLE Master Idle status flag. - 0x8 + 8 1 read-only @@ -24485,7 +24728,7 @@ ENABLERX Enable the receive FIFO. - 0x1 + 1 1 read-write @@ -24504,14 +24747,14 @@ SIZE FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1, 0x2, 0x3 = not applicable to USART. - 0x4 + 4 2 read-only DMATX DMA configuration for transmit. - 0xC + 12 1 read-write @@ -24530,7 +24773,7 @@ DMARX DMA configuration for receive. - 0xD + 13 1 read-write @@ -24549,7 +24792,7 @@ WAKETX Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down, as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware Wake-up control register. - 0xE + 14 1 read-write @@ -24568,7 +24811,7 @@ WAKERX Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down, as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware Wake-up control register. - 0xF + 15 1 read-write @@ -24587,14 +24830,14 @@ EMPTYTX Empty command for the transmit FIFO. When a 1 is written to this bit, the TX FIFO is emptied. - 0x10 + 16 1 read-write EMPTYRX Empty command for the receive FIFO. When a 1 is written to this bit, the RX FIFO is emptied. - 0x11 + 17 1 read-write @@ -24619,56 +24862,56 @@ RXERR RX FIFO error. Will be set if a receive FIFO overflow occurs, caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit. - 0x1 + 1 1 read-write PERINT Peripheral interrupt. When 1, this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register. - 0x3 + 3 1 read-only TXEMPTY Transmit FIFO empty. When 1, the transmit FIFO is empty. The peripheral may still be processing the last piece of data. - 0x4 + 4 1 read-only TXNOTFULL Transmit FIFO not full. When 1, the transmit FIFO is not full, so more data can be written. When 0, the transmit FIFO is full and another write would cause it to overflow. - 0x5 + 5 1 read-only RXNOTEMPTY Receive FIFO not empty. When 1, the receive FIFO is not empty, so data can be read. When 0, the receive FIFO is empty. - 0x6 + 6 1 read-only RXFULL Receive FIFO full. When 1, the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow. - 0x7 + 7 1 read-only TXLVL Transmit FIFO current level. A 0 means the TX FIFO is currently empty, and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full, the TXEMPTY and TXNOTFULL flags will be 0. - 0x8 + 8 5 read-only RXLVL Receive FIFO current level. A 0 means the RX FIFO is currently empty, and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full, the RXFULL and RXNOTEMPTY flags will be 1. - 0x10 + 16 5 read-only @@ -24705,7 +24948,7 @@ RXLVLENA Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET, or a DMA trigger if DMARX in FIFOCFG is set. - 0x1 + 1 1 read-write @@ -24724,14 +24967,14 @@ TXLVL Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so, the FIFO level can wake up the device just enough to perform DMA, then return to the reduced power mode. See Hardware Wake-up control register. 0 = trigger when the TX FIFO becomes empty. 1 = trigger when the TX FIFO level decreases to one entry. 15 = trigger when the TX FIFO level decreases to 15 entries (is no longer full). - 0x8 + 8 4 read-write RXLVL Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so, the FIFO level can wake up the device just enough to perform DMA, then return to the reduced power mode. See Hardware Wake-up control register. 0 = trigger when the RX FIFO has received one entry (is no longer empty). 1 = trigger when the RX FIFO has received two entries. 15 = trigger when the RX FIFO has received 16 entries (has become full). - 0x10 + 16 4 read-write @@ -24768,7 +25011,7 @@ RXERR Determines whether an interrupt occurs when a receive error occurs, based on the RXERR flag in the FIFOSTAT register. - 0x1 + 1 1 read-write @@ -24787,7 +25030,7 @@ TXLVL Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register. - 0x2 + 2 1 read-write @@ -24806,7 +25049,7 @@ RXLVL Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register. - 0x3 + 3 1 read-write @@ -24843,21 +25086,21 @@ RXERR Writing one clears the corresponding bits in the FIFOINTENSET register. - 0x1 + 1 1 read-write TXLVL Writing one clears the corresponding bits in the FIFOINTENSET register. - 0x2 + 2 1 read-write RXLVL Writing one clears the corresponding bits in the FIFOINTENSET register. - 0x3 + 3 1 read-write @@ -24882,28 +25125,28 @@ RXERR RX FIFO error. - 0x1 + 1 1 read-only TXLVL Transmit FIFO level interrupt. - 0x2 + 2 1 read-only RXLVL Receive FIFO level interrupt. - 0x3 + 3 1 read-only PERINT Peripheral interrupt. - 0x4 + 4 1 read-only @@ -24928,7 +25171,7 @@ TXSSEL0_N Transmit slave select. This field asserts SSEL0 in master mode. The output on the pin is active LOW by default. - 0x10 + 16 1 write-only @@ -24947,7 +25190,7 @@ TXSSEL1_N Transmit slave select. This field asserts SSEL1 in master mode. The output on the pin is active LOW by default. - 0x11 + 17 1 write-only @@ -24966,7 +25209,7 @@ TXSSEL2_N Transmit slave select. This field asserts SSEL2 in master mode. The output on the pin is active LOW by default. - 0x12 + 18 1 write-only @@ -24985,7 +25228,7 @@ TXSSEL3_N Transmit slave select. This field asserts SSEL3 in master mode. The output on the pin is active LOW by default. - 0x13 + 19 1 write-only @@ -25004,7 +25247,7 @@ EOT End of transfer. The asserted SSEL will be deasserted at the end of a transfer and remain so far at least the time specified by the Transfer_delay value in the DLY register. - 0x14 + 20 1 write-only @@ -25023,7 +25266,7 @@ EOF End of frame. Between frames, a delay may be inserted, as defined by the Frame_delay value in the DLY register. The end of a frame may not be particularly meaningful if the Frame_delay value = 0. This control can be used as part of the support for frame lengths greater than 16 bits. - 0x15 + 21 1 write-only @@ -25042,7 +25285,7 @@ RXIGNORE Receive Ignore. This allows data to be transmitted using the SPI without the need to read unneeded data from the receiver. Setting this bit simplifies the transmit process and can be used with the DMA. - 0x16 + 22 1 write-only @@ -25061,7 +25304,7 @@ LEN Data Length. Specifies the data length from 4 to 16 bits. Note that transfer lengths greater than 16 bits are supported by implementing multiple sequential transmits. 0x0-2 = Reserved. 0x3 = Data transfer is 4 bits in length. 0x4 = Data transfer is 5 bits in length. 0xF = Data transfer is 16 bits in length. - 0x18 + 24 4 write-only @@ -25086,35 +25329,35 @@ RXSSEL0_N Slave Select for receive. This field allows the state of the SSEL0 pin to be saved along with received data. The value will reflect the SSEL0 pin for both master and slave operation. A zero indicates that a slave select is active. The actual polarity of each slave select pin is configured by the related SPOL bit in CFG. - 0x10 + 16 1 read-only RXSSEL1_N Slave Select for receive. This field allows the state of the SSEL1 pin to be saved along with received data. The value will reflect the SSEL1 pin for both master and slave operation. A zero indicates that a slave select is active. The actual polarity of each slave select pin is configured by the related SPOL bit in CFG. - 0x11 + 17 1 read-only RXSSEL2_N Slave Select for receive. This field allows the state of the SSEL2 pin to be saved along with received data. The value will reflect the SSEL2 pin for both master and slave operation. A zero indicates that a slave select is active. The actual polarity of each slave select pin is configured by the related SPOL bit in CFG. - 0x12 + 18 1 read-only RXSSEL3_N Slave Select for receive. This field allows the state of the SSEL3 pin to be saved along with received data. The value will reflect the SSEL3 pin for both master and slave operation. A zero indicates that a slave select is active. The actual polarity of each slave select pin is configured by the related SPOL bit in CFG. - 0x13 + 19 1 read-only SOT Start of Transfer flag. This flag will be 1 if this is the first data after the SSELs went from deasserted to asserted (i.e., any previous transfer has ended). This information can be used to identify the first piece of data in cases where the transfer length is greater than 16 bits. - 0x14 + 20 1 read-only @@ -25139,35 +25382,35 @@ RXSSEL0_N Slave Select for receive. - 0x10 + 16 1 read-only RXSSEL1_N Slave Select for receive. - 0x11 + 17 1 read-only RXSSEL2_N Slave Select for receive. - 0x12 + 18 1 read-only RXSSEL3_N Slave Select for receive. - 0x13 + 19 1 read-only SOT Start of transfer flag. - 0x14 + 20 1 read-only @@ -25175,13 +25418,125 @@ + + SPI1 + LPC5411x Serial Peripheral Interfaces (SPI) + FLEXCOMM1 + SPI + 0x40087000 + + 0 + 0xE44 + registers + + + FLEXCOMM1 + 15 + + + + SPI2 + LPC5411x Serial Peripheral Interfaces (SPI) + FLEXCOMM2 + SPI + 0x40088000 + + 0 + 0xE44 + registers + + + FLEXCOMM2 + 16 + + + + SPI3 + LPC5411x Serial Peripheral Interfaces (SPI) + FLEXCOMM3 + SPI + 0x40089000 + + 0 + 0xE44 + registers + + + FLEXCOMM3 + 17 + + + + SPI4 + LPC5411x Serial Peripheral Interfaces (SPI) + FLEXCOMM4 + SPI + 0x4008A000 + + 0 + 0xE44 + registers + + + FLEXCOMM4 + 18 + + + + SPI5 + LPC5411x Serial Peripheral Interfaces (SPI) + FLEXCOMM5 + SPI + 0x40096000 + + 0 + 0xE44 + registers + + + FLEXCOMM5 + 19 + + + + SPI6 + LPC5411x Serial Peripheral Interfaces (SPI) + FLEXCOMM6 + SPI + 0x40097000 + + 0 + 0xE44 + registers + + + FLEXCOMM6 + 20 + + + + SPI7 + LPC5411x Serial Peripheral Interfaces (SPI) + FLEXCOMM7 + SPI + 0x40098000 + + 0 + 0xE44 + registers + + + FLEXCOMM7 + 21 + + USART0 - FLEXCOMM0 LPC5411x USARTs + FLEXCOMM0 USART - 0x40086000 USART + 0x40086000 0 0xE44 @@ -25223,7 +25578,7 @@ DATALEN Selects the data size for the USART. - 0x2 + 2 2 read-write @@ -25247,7 +25602,7 @@ PARITYSEL Selects what type of parity is used by the USART. - 0x4 + 4 2 read-write @@ -25271,7 +25626,7 @@ STOPLEN Number of stop bits appended to transmitted data. Only a single stop bit is required for received data. - 0x6 + 6 1 read-write @@ -25290,7 +25645,7 @@ MODE32K Selects standard or 32 kHz clocking mode. - 0x7 + 7 1 read-write @@ -25309,7 +25664,7 @@ LINMODE LIN break mode enable. - 0x8 + 8 1 read-write @@ -25328,7 +25683,7 @@ CTSEN CTS Enable. Determines whether CTS is used for flow control. CTS can be from the input pin, or from the USART's own RTS if loopback mode is enabled. - 0x9 + 9 1 read-write @@ -25347,7 +25702,7 @@ SYNCEN Selects synchronous or asynchronous operation. - 0xB + 11 1 read-write @@ -25366,7 +25721,7 @@ CLKPOL Selects the clock polarity and sampling edge of received data in synchronous mode. - 0xC + 12 1 read-write @@ -25385,7 +25740,7 @@ SYNCMST Synchronous mode Master select. - 0xE + 14 1 read-write @@ -25404,7 +25759,7 @@ LOOP Selects data loopback mode. - 0xF + 15 1 read-write @@ -25423,7 +25778,7 @@ IOMODE I/O output mode. - 0x10 + 16 1 read-write @@ -25442,7 +25797,7 @@ OETA Output Enable Turnaround time enable for RS-485 operation. - 0x12 + 18 1 read-write @@ -25461,7 +25816,7 @@ AUTOADDR Automatic Address matching enable. - 0x13 + 19 1 read-write @@ -25480,7 +25835,7 @@ OESEL Output Enable Select. - 0x14 + 20 1 read-write @@ -25499,7 +25854,7 @@ OEPOL Output Enable Polarity. - 0x15 + 21 1 read-write @@ -25518,7 +25873,7 @@ RXPOL Receive data polarity. - 0x16 + 22 1 read-write @@ -25537,7 +25892,7 @@ TXPOL Transmit data polarity. - 0x17 + 23 1 read-write @@ -25567,7 +25922,7 @@ TXBRKEN Break Enable. - 0x1 + 1 1 read-write @@ -25586,7 +25941,7 @@ ADDRDET Enable address detect mode. - 0x2 + 2 1 read-write @@ -25605,7 +25960,7 @@ TXDIS Transmit Disable. - 0x6 + 6 1 read-write @@ -25624,7 +25979,7 @@ CC Continuous Clock generation. By default, SCLK is only output while data is being transmitted in synchronous mode. - 0x8 + 8 1 read-write @@ -25643,7 +25998,7 @@ CLRCCONRX Clear Continuous Clock. - 0x9 + 9 1 read-write @@ -25662,7 +26017,7 @@ AUTOBAUD Autobaud enable. - 0x10 + 16 1 read-write @@ -25692,84 +26047,84 @@ RXIDLE Receiver Idle. When 0, indicates that the receiver is currently in the process of receiving data. When 1, indicates that the receiver is not currently in the process of receiving data. - 0x1 + 1 1 read-only TXIDLE Transmitter Idle. When 0, indicates that the transmitter is currently in the process of sending data.When 1, indicate that the transmitter is not currently in the process of sending data. - 0x3 + 3 1 read-only CTS This bit reflects the current state of the CTS signal, regardless of the setting of the CTSEN bit in the CFG register. This will be the value of the CTS input pin unless loopback mode is enabled. - 0x4 + 4 1 read-only DELTACTS This bit is set when a change in the state is detected for the CTS flag above. This bit is cleared by software. - 0x5 + 5 1 write-only TXDISSTAT Transmitter Disabled Status flag. When 1, this bit indicates that the USART transmitter is fully idle after being disabled via the TXDIS bit in the CFG register (TXDIS = 1). - 0x6 + 6 1 read-only RXBRK Received Break. This bit reflects the current state of the receiver break detection logic. It is set when the Un_RXD pin remains low for 16 bit times. Note that FRAMERRINT will also be set when this condition occurs because the stop bit(s) for the character would be missing. RXBRK is cleared when the Un_RXD pin goes high. - 0xA + 10 1 read-only DELTARXBRK This bit is set when a change in the state of receiver break detection occurs. Cleared by software. - 0xB + 11 1 write-only START This bit is set when a start is detected on the receiver input. Its purpose is primarily to allow wake-up from Deep-sleep or Power-down mode immediately when a start is detected. Cleared by software. - 0xC + 12 1 write-only FRAMERRINT Framing Error interrupt flag. This flag is set when a character is received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source. - 0xD + 13 1 write-only PARITYERRINT Parity Error interrupt flag. This flag is set when a parity error is detected in a received character. - 0xE + 14 1 write-only RXNOISEINT Received Noise interrupt flag. Three samples of received data are taken in order to determine the value of each received data bit, except in synchronous mode. This acts as a noise filter if one sample disagrees. This flag is set when a received data bit contains one disagreeing sample. This could indicate line noise, a baud rate or character format mismatch, or loss of synchronization during data reception. - 0xF + 15 1 write-only ABERR Auto baud Error. An auto baud error can occur if the BRG counts to its limit before the end of the start bit that is being measured, essentially an auto baud time-out. - 0x10 + 16 1 write-only @@ -25787,63 +26142,63 @@ TXIDLEEN When 1, enables an interrupt when the transmitter becomes idle (TXIDLE = 1). - 0x3 + 3 1 read-write DELTACTSEN When 1, enables an interrupt when there is a change in the state of the CTS input. - 0x5 + 5 1 read-write TXDISEN When 1, enables an interrupt when the transmitter is fully disabled as indicated by the TXDISINT flag in STAT. See description of the TXDISINT bit for details. - 0x6 + 6 1 read-write DELTARXBRKEN When 1, enables an interrupt when a change of state has occurred in the detection of a received break condition (break condition asserted or deasserted). - 0xB + 11 1 read-write STARTEN When 1, enables an interrupt when a received start bit has been detected. - 0xC + 12 1 read-write FRAMERREN When 1, enables an interrupt when a framing error has been detected. - 0xD + 13 1 read-write PARITYERREN When 1, enables an interrupt when a parity error has been detected. - 0xE + 14 1 read-write RXNOISEEN When 1, enables an interrupt when noise is detected. See description of the RXNOISEINT bit in Table 354. - 0xF + 15 1 read-write ABERREN When 1, enables an interrupt when an auto baud error occurs. - 0x10 + 16 1 read-write @@ -25861,63 +26216,63 @@ TXIDLECLR Writing 1 clears the corresponding bit in the INTENSET register. - 0x3 + 3 1 write-only DELTACTSCLR Writing 1 clears the corresponding bit in the INTENSET register. - 0x5 + 5 1 write-only TXDISCLR Writing 1 clears the corresponding bit in the INTENSET register. - 0x6 + 6 1 write-only DELTARXBRKCLR Writing 1 clears the corresponding bit in the INTENSET register. - 0xB + 11 1 write-only STARTCLR Writing 1 clears the corresponding bit in the INTENSET register. - 0xC + 12 1 write-only FRAMERRCLR Writing 1 clears the corresponding bit in the INTENSET register. - 0xD + 13 1 write-only PARITYERRCLR Writing 1 clears the corresponding bit in the INTENSET register. - 0xE + 14 1 write-only RXNOISECLR Writing 1 clears the corresponding bit in the INTENSET register. - 0xF + 15 1 write-only ABERRCLR Writing 1 clears the corresponding bit in the INTENSET register. - 0x10 + 16 1 write-only @@ -25953,63 +26308,63 @@ TXIDLE Transmitter Idle status. - 0x3 + 3 1 read-only DELTACTS This bit is set when a change in the state of the CTS input is detected. - 0x5 + 5 1 read-only TXDISINT Transmitter Disabled Interrupt flag. - 0x6 + 6 1 read-only DELTARXBRK This bit is set when a change in the state of receiver break detection occurs. - 0xB + 11 1 read-only START This bit is set when a start is detected on the receiver input. - 0xC + 12 1 read-only FRAMERRINT Framing Error interrupt flag. - 0xD + 13 1 read-only PARITYERRINT Parity Error interrupt flag. - 0xE + 14 1 read-only RXNOISEINT Received Noise interrupt flag. - 0xF + 15 1 read-only ABERRINT Auto baud Error Interrupt flag. - 0x10 + 16 1 read-only @@ -26082,7 +26437,7 @@ ENABLERX Enable the receive FIFO. - 0x1 + 1 1 read-write @@ -26101,14 +26456,14 @@ SIZE FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1, 0x2, 0x3 = not applicable to USART. - 0x4 + 4 2 read-only DMATX DMA configuration for transmit. - 0xC + 12 1 read-write @@ -26127,7 +26482,7 @@ DMARX DMA configuration for receive. - 0xD + 13 1 read-write @@ -26146,7 +26501,7 @@ WAKETX Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down, as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware Wake-up control register. - 0xE + 14 1 read-write @@ -26165,7 +26520,7 @@ WAKERX Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down, as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware Wake-up control register. - 0xF + 15 1 read-write @@ -26184,14 +26539,14 @@ EMPTYTX Empty command for the transmit FIFO. When a 1 is written to this bit, the TX FIFO is emptied. - 0x10 + 16 1 read-write EMPTYRX Empty command for the receive FIFO. When a 1 is written to this bit, the RX FIFO is emptied. - 0x11 + 17 1 read-write @@ -26216,56 +26571,56 @@ RXERR RX FIFO error. Will be set if a receive FIFO overflow occurs, caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit. - 0x1 + 1 1 read-write PERINT Peripheral interrupt. When 1, this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register. - 0x3 + 3 1 read-only TXEMPTY Transmit FIFO empty. When 1, the transmit FIFO is empty. The peripheral may still be processing the last piece of data. - 0x4 + 4 1 read-only TXNOTFULL Transmit FIFO not full. When 1, the transmit FIFO is not full, so more data can be written. When 0, the transmit FIFO is full and another write would cause it to overflow. - 0x5 + 5 1 read-only RXNOTEMPTY Receive FIFO not empty. When 1, the receive FIFO is not empty, so data can be read. When 0, the receive FIFO is empty. - 0x6 + 6 1 read-only RXFULL Receive FIFO full. When 1, the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow. - 0x7 + 7 1 read-only TXLVL Transmit FIFO current level. A 0 means the TX FIFO is currently empty, and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full, the TXEMPTY and TXNOTFULL flags will be 0. - 0x8 + 8 5 read-only RXLVL Receive FIFO current level. A 0 means the RX FIFO is currently empty, and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full, the RXFULL and RXNOTEMPTY flags will be 1. - 0x10 + 16 5 read-only @@ -26302,7 +26657,7 @@ RXLVLENA Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET, or a DMA trigger if DMARX in FIFOCFG is set. - 0x1 + 1 1 read-write @@ -26321,14 +26676,14 @@ TXLVL Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so, the FIFO level can wake up the device just enough to perform DMA, then return to the reduced power mode. See Hardware Wake-up control register. 0 = trigger when the TX FIFO becomes empty. 1 = trigger when the TX FIFO level decreases to one entry. 15 = trigger when the TX FIFO level decreases to 15 entries (is no longer full). - 0x8 + 8 4 read-write RXLVL Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so, the FIFO level can wake up the device just enough to perform DMA, then return to the reduced power mode. See Hardware Wake-up control register. 0 = trigger when the RX FIFO has received one entry (is no longer empty). 1 = trigger when the RX FIFO has received two entries. 15 = trigger when the RX FIFO has received 16 entries (has become full). - 0x10 + 16 4 read-write @@ -26365,7 +26720,7 @@ RXERR Determines whether an interrupt occurs when a receive error occurs, based on the RXERR flag in the FIFOSTAT register. - 0x1 + 1 1 read-write @@ -26384,7 +26739,7 @@ TXLVL Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register. - 0x2 + 2 1 read-write @@ -26403,7 +26758,7 @@ RXLVL Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register. - 0x3 + 3 1 read-write @@ -26440,21 +26795,21 @@ RXERR Writing one clears the corresponding bits in the FIFOINTENSET register. - 0x1 + 1 1 read-write TXLVL Writing one clears the corresponding bits in the FIFOINTENSET register. - 0x2 + 2 1 read-write RXLVL Writing one clears the corresponding bits in the FIFOINTENSET register. - 0x3 + 3 1 read-write @@ -26479,28 +26834,28 @@ RXERR RX FIFO error. - 0x1 + 1 1 read-only TXLVL Transmit FIFO level interrupt. - 0x2 + 2 1 read-only RXLVL Receive FIFO level interrupt. - 0x3 + 3 1 read-only PERINT Peripheral interrupt. - 0x4 + 4 1 read-only @@ -26543,21 +26898,21 @@ FRAMERR Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO, and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source. - 0xD + 13 1 read-only PARITYERR Parity Error status flag. This bit reflects the status for the data it is read along with from the FIFO. This bit will be set when a parity error is detected in a received character. - 0xE + 14 1 read-only RXNOISE Received Noise flag. See description of the RxNoiseInt bit in Table 354. - 0xF + 15 1 read-only @@ -26582,21 +26937,21 @@ FRAMERR Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO, and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source. - 0xD + 13 1 read-only PARITYERR Parity Error status flag. This bit reflects the status for the data it is read along with from the FIFO. This bit will be set when a parity error is detected in a received character. - 0xE + 14 1 read-only RXNOISE Received Noise flag. See description of the RxNoiseInt bit in Table 354. - 0xF + 15 1 read-only @@ -26604,57 +26959,10 @@ - - FLEXCOMM1 - LPC5411x Flexcomm serial communication - FLEXCOMM - 0x40087000 - - 0 - 0x1000 - registers - - - FLEXCOMM1 - 15 - - - - I2C1 - FLEXCOMM1 - LPC5411x I2C-bus interfaces - I2C - 0x40087000 - - 0 - 0x884 - registers - - - FLEXCOMM1 - 15 - - - - SPI1 - FLEXCOMM1 - LPC5411x Serial Peripheral Interfaces (SPI) - SPI - 0x40087000 - - 0 - 0xE44 - registers - - - FLEXCOMM1 - 15 - - USART1 - FLEXCOMM1 LPC5411x USARTs + FLEXCOMM1 USART 0x40087000 @@ -26667,57 +26975,10 @@ 15 - - FLEXCOMM2 - LPC5411x Flexcomm serial communication - FLEXCOMM - 0x40088000 - - 0 - 0x1000 - registers - - - FLEXCOMM2 - 16 - - - - I2C2 - FLEXCOMM2 - LPC5411x I2C-bus interfaces - I2C - 0x40088000 - - 0 - 0x884 - registers - - - FLEXCOMM2 - 16 - - - - SPI2 - FLEXCOMM2 - LPC5411x Serial Peripheral Interfaces (SPI) - SPI - 0x40088000 - - 0 - 0xE44 - registers - - - FLEXCOMM2 - 16 - - USART2 - FLEXCOMM2 LPC5411x USARTs + FLEXCOMM2 USART 0x40088000 @@ -26730,57 +26991,10 @@ 16 - - FLEXCOMM3 - LPC5411x Flexcomm serial communication - FLEXCOMM - 0x40089000 - - 0 - 0x1000 - registers - - - FLEXCOMM3 - 17 - - - - I2C3 - FLEXCOMM3 - LPC5411x I2C-bus interfaces - I2C - 0x40089000 - - 0 - 0x884 - registers - - - FLEXCOMM3 - 17 - - - - SPI3 - FLEXCOMM3 - LPC5411x Serial Peripheral Interfaces (SPI) - SPI - 0x40089000 - - 0 - 0xE44 - registers - - - FLEXCOMM3 - 17 - - USART3 - FLEXCOMM3 LPC5411x USARTs + FLEXCOMM3 USART 0x40089000 @@ -26793,57 +27007,10 @@ 17 - - FLEXCOMM4 - LPC5411x Flexcomm serial communication - FLEXCOMM - 0x4008A000 - - 0 - 0x1000 - registers - - - FLEXCOMM4 - 18 - - - - I2C4 - FLEXCOMM4 - LPC5411x I2C-bus interfaces - I2C - 0x4008A000 - - 0 - 0x884 - registers - - - FLEXCOMM4 - 18 - - - - SPI4 - FLEXCOMM4 - LPC5411x Serial Peripheral Interfaces (SPI) - SPI - 0x4008A000 - - 0 - 0xE44 - registers - - - FLEXCOMM4 - 18 - - USART4 - FLEXCOMM4 LPC5411x USARTs + FLEXCOMM4 USART 0x4008A000 @@ -26856,6 +27023,54 @@ 18 + + USART5 + LPC5411x USARTs + FLEXCOMM5 + USART + 0x40096000 + + 0 + 0xE44 + registers + + + FLEXCOMM5 + 19 + + + + USART6 + LPC5411x USARTs + FLEXCOMM6 + USART + 0x40097000 + + 0 + 0xE44 + registers + + + FLEXCOMM6 + 20 + + + + USART7 + LPC5411x USARTs + FLEXCOMM7 + USART + 0x40098000 + + 0 + 0xE44 + registers + + + FLEXCOMM7 + 21 + + MAILBOX LPC5411x Mailbox @@ -27351,7 +27566,7 @@ RESETN FIFO reset. - 0x1 + 1 1 read-write @@ -27370,7 +27585,7 @@ INTEN Interrupt enable. - 0x2 + 2 1 read-write @@ -27389,7 +27604,7 @@ DMAEN DMA enable - 0x3 + 3 1 read-write @@ -27408,7 +27623,7 @@ TRIGLVL FIFO trigger level. Selects the data trigger level for interrupt or DMA operation. If enabled to do so, the FIFO level can wake up the device just enough to perform DMA, then return to the reduced power mode See Section 4.5.66 'Hardware Wake-up control register'. 0 = trigger when the FIFO has received one entry (is no longer empty). 1 = trigger when the FIFO has received two entries. 15 = trigger when the FIFO has received 16 entries (has become full). - 0x10 + 16 5 read-write @@ -27433,14 +27648,14 @@ OVERRUN Overrun flag. Indicates that a FIFO overflow has occurred at some point. Writing a one to this bit clears the flag. This flag does not cause an interrupt. - 0x1 + 1 1 read-write UNDERRUN Underrun flag. Indicates that a FIFO underflow has occurred at some point. Writing a one to this bit clears the flag. - 0x2 + 2 1 read-write @@ -27495,7 +27710,7 @@ PHY_HALF Half rate sampling - 0x1 + 1 1 read-write @@ -27554,14 +27769,14 @@ DCGAIN Fine gain adjustment in the form of a number of bits to downshift. - 0x4 + 4 4 read-write SATURATEAT16BIT Selects 16-bit saturation. - 0x8 + 8 1 read-write @@ -27599,7 +27814,7 @@ EN_CH1 Enable channel 1. When 1, PDM channel 1 is enabled. - 0x1 + 1 1 read-write @@ -27624,14 +27839,14 @@ CLK_BYPASS1 Bypass CLK1. When 1, PDM_DATA1 becomes the clock for PDM channel 1. This provides for the possibility of an external codec taking over the PDM bus. - 0x1 + 1 1 read-write STEREO_DATA0 Stereo PDM select. When 1, PDM_DATA0 is routed to both PDM channels in a configuration that supports a single stereo digital microphone. - 0x2 + 2 1 read-write @@ -27872,28 +28087,28 @@ BIT_RVS_WR Data bit order: 1 = Bit order reverse for CRC_WR_DATA (per byte) 0 = No bit order reverse for CRC_WR_DATA (per byte) - 0x2 + 2 1 read-write CMPL_WR Data complement: 1 = 1's complement for CRC_WR_DATA 0 = No 1's complement for CRC_WR_DATA - 0x3 + 3 1 read-write BIT_RVS_SUM CRC sum bit order: 1 = Bit order reverse for CRC_SUM 0 = No bit order reverse for CRC_SUM - 0x4 + 4 1 read-write CMPL_SUM CRC sum complement: 1 = 1's complement for CRC_SUM 0 = No 1's complement for CRC_SUM - 0x5 + 5 1 read-write @@ -27957,107 +28172,13 @@ - - FLEXCOMM5 - LPC5411x Flexcomm serial communication - FLEXCOMM - 0x40096000 - - 0 - 0x1000 - registers - - - FLEXCOMM5 - 19 - - - - I2C5 - FLEXCOMM5 - LPC5411x I2C-bus interfaces - I2C - 0x40096000 - - 0 - 0x884 - registers - - - FLEXCOMM5 - 19 - - - - SPI5 - FLEXCOMM5 - LPC5411x Serial Peripheral Interfaces (SPI) - SPI - 0x40096000 - - 0 - 0xE44 - registers - - - FLEXCOMM5 - 19 - - - - USART5 - FLEXCOMM5 - LPC5411x USARTs - USART - 0x40096000 - - 0 - 0xE44 - registers - - - FLEXCOMM5 - 19 - - - - FLEXCOMM6 - LPC5411x Flexcomm serial communication - FLEXCOMM - 0x40097000 - - 0 - 0x1000 - registers - - - FLEXCOMM6 - 20 - - - - I2C6 - FLEXCOMM6 - LPC5411x I2C-bus interfaces - I2C - 0x40097000 - - 0 - 0x884 - registers - - - FLEXCOMM6 - 20 - - I2S0 - FLEXCOMM6 LPC5411x I2S interface + FLEXCOMM6 I2S - 0x40097000 I2S + 0x40097000 0 0xE48 @@ -28099,7 +28220,7 @@ DATAPAUSE Data flow Pause. Allows pausing data flow between the I2S serializer/deserializer and the FIFO. This could be done in order to change streams, or while restarting after a data underflow or overflow. When paused, FIFO operations can be done without corrupting data that is in the process of being sent or received. Once a data pause has been requested, the interface may need to complete sending data that was in progress before interrupting the flow of data. Software must check that the pause is actually in effect before taking action. This is done by monitoring the DATAPAUSED flag in the STAT register. When DATAPAUSE is cleared, data transfer will resume at the beginning of the next frame. - 0x1 + 1 1 read-write @@ -28118,7 +28239,7 @@ PAIRCOUNT Provides the number of I2S channel pairs in this Flexcomm This is a read-only field whose value may be different in other Flexcomms. 00 = there is 1 I2S channel pair in this Flexcomm. 01 = there are 2 I2S channel pairs in this Flexcomm. 10 = there are 3 I2S channel pairs in this Flexcomm. 11 = there are 4 I2S channel pairs in this Flexcomm. - 0x2 + 2 2 read-write @@ -28147,7 +28268,7 @@ MSTSLVCFG Master / slave configuration selection, determining how SCK and WS are used by all channel pairs in this Flexcomm. - 0x4 + 4 2 read-write @@ -28176,7 +28297,7 @@ MODE Selects the basic I2S operating mode. Other configurations modify this to obtain all supported cases. See Formats and modes for examples. - 0x6 + 6 2 read-write @@ -28205,7 +28326,7 @@ RIGHTLOW Right channel data is in the Low portion of FIFO data. Essentially, this swaps left and right channel data as it is transferred to or from the FIFO. This bit is not used if the data width is greater than 24 bits or if PDMDATA = 1. Note that if the ONECHANNEL field (bit 10 of this register) = 1, the one channel to be used is the nominally the left channel. POSITION can still place that data in the frame where right channel data is normally located. if all enabled channel pairs have ONECHANNEL = 1, then RIGHTLOW = 1 is not allowed. - 0x8 + 8 1 read-write @@ -28224,7 +28345,7 @@ LEFTJUST Left Justify data. - 0x9 + 9 1 read-write @@ -28243,7 +28364,7 @@ ONECHANNEL Single channel mode. Applies to both transmit and receive. This configuration bit applies only to the first I2S channel pair. Other channel pairs may select this mode independently in their separate CFG1 registers. - 0xA + 10 1 read-write @@ -28262,7 +28383,7 @@ PDMDATA PDM Data selection. This bit controls the data source for I2S transmit, and cannot be set in Rx mode. This bit only has an effect if the device the Flexcomm resides in includes a D-Mic subsystem. For the LPC5411x, this bit applies only to Flexcomm 7. - 0xB + 11 1 read-write @@ -28281,7 +28402,7 @@ SCK_POL SCK polarity. - 0xC + 12 1 read-write @@ -28300,7 +28421,7 @@ WS_POL WS polarity. - 0xD + 13 1 read-write @@ -28319,7 +28440,7 @@ DATALEN Data Length, minus 1 encoded, defines the number of data bits to be transmitted or received for all I2S channel pairs in this Flexcomm. Note that data is only driven to or received from SDA for the number of bits defined by DATALEN. DATALEN is also used in these ways by the I2S: Determines the size of data transfers between the FIFO and the I2S serializer/deserializer. See FIFO buffer configurations and usage In mode 1, 2, and 3, determines the location of right data following left data in the frame. In mode 3 (where WS has a one data slot long pulse at the beginning of each data frame) determines the duration of the WS pulse. Values: 0x00 to 0x02 = not supported 0x03 = data is 4 bits in length 0x04 = data is 5 bits in length 0x1F = data is 32 bits in length - 0x10 + 16 5 read-write @@ -28344,7 +28465,7 @@ POSITION Data Position. Defines the location within the frame of the data for this channel pair. POSITION + DATALEN must be less than FRAMELEN. See Frame format. When MODE = 0, POSITION defines the location of data in both the left phase and right phase, starting one clock after the WS edge. In other modes, POSITION defines the location of data within the entire frame. ONECHANNEL = 1 while MODE = 0 is a special case, see the description of ONECHANNEL. The combination of DATALEN and the POSITION fields of all channel pairs must be made such that the channels do not overlap within the frame. 0x000 = data begins at bit position 0 (the first bit position) within the frame or WS phase. 0x001 = data begins at bit position 1 within the frame or WS phase. 0x002 = data begins at bit position 2 within the frame or WS phase. - 0x10 + 16 9 read-write @@ -28381,7 +28502,7 @@ SLVFRMERR Slave Frame Error flag. This applies when at least one channel pair is operating as a slave. An error indicates that the incoming WS signal did not transition as expected due to a mismatch between FRAMELEN and the actual incoming I2S stream. - 0x1 + 1 1 write-only @@ -28400,7 +28521,7 @@ LR Left/Right indication. This flag is considered to be a debugging aid and is not expected to be used by an I2S driver. Valid when one channel pair is busy. Indicates left or right data being processed for the currently busy channel pair. - 0x2 + 2 1 read-only @@ -28419,7 +28540,7 @@ DATAPAUSED Data Paused status flag. Applies to all I2S channels - 0x3 + 3 1 read-only @@ -28486,7 +28607,7 @@ ENABLERX Enable the receive FIFO. - 0x1 + 1 1 read-write @@ -28505,7 +28626,7 @@ TXI2SSE0 Transmit I2S empty 0. Determines the value sent by the I2S in transmit mode if the TX FIFO becomes empty. This value is sent repeatedly until the I2S is paused, the error is cleared, new data is provided, and the I2S is un-paused. - 0x2 + 2 1 read-write @@ -28524,7 +28645,7 @@ PACK48 Packing format for 48-bit data. This relates to how data is entered into or taken from the FIFO by software or DMA. - 0x3 + 3 1 read-write @@ -28543,14 +28664,14 @@ SIZE FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1, 0x2, 0x3 = not applicable to USART. - 0x4 + 4 2 read-only DMATX DMA configuration for transmit. - 0xC + 12 1 read-write @@ -28569,7 +28690,7 @@ DMARX DMA configuration for receive. - 0xD + 13 1 read-write @@ -28588,7 +28709,7 @@ WAKETX Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down, as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware Wake-up control register. - 0xE + 14 1 read-write @@ -28607,7 +28728,7 @@ WAKERX Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down, as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware Wake-up control register. - 0xF + 15 1 read-write @@ -28626,21 +28747,21 @@ EMPTYTX Empty command for the transmit FIFO. When a 1 is written to this bit, the TX FIFO is emptied. - 0x10 + 16 1 read-write EMPTYRX Empty command for the receive FIFO. When a 1 is written to this bit, the RX FIFO is emptied. - 0x11 + 17 1 read-write POPDBG Pop FIFO for debug reads. - 0x12 + 18 1 read-write @@ -28677,56 +28798,56 @@ RXERR RX FIFO error. Will be set if a receive FIFO overflow occurs, caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit. - 0x1 + 1 1 read-write PERINT Peripheral interrupt. When 1, this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register. - 0x3 + 3 1 read-only TXEMPTY Transmit FIFO empty. When 1, the transmit FIFO is empty. The peripheral may still be processing the last piece of data. - 0x4 + 4 1 read-only TXNOTFULL Transmit FIFO not full. When 1, the transmit FIFO is not full, so more data can be written. When 0, the transmit FIFO is full and another write would cause it to overflow. - 0x5 + 5 1 read-only RXNOTEMPTY Receive FIFO not empty. When 1, the receive FIFO is not empty, so data can be read. When 0, the receive FIFO is empty. - 0x6 + 6 1 read-only RXFULL Receive FIFO full. When 1, the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow. - 0x7 + 7 1 read-only TXLVL Transmit FIFO current level. A 0 means the TX FIFO is currently empty, and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full, the TXEMPTY and TXNOTFULL flags will be 0. - 0x8 + 8 5 read-only RXLVL Receive FIFO current level. A 0 means the RX FIFO is currently empty, and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full, the RXFULL and RXNOTEMPTY flags will be 1. - 0x10 + 16 5 read-only @@ -28763,7 +28884,7 @@ RXLVLENA Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET, or a DMA trigger if DMARX in FIFOCFG is set. - 0x1 + 1 1 read-write @@ -28782,14 +28903,14 @@ TXLVL Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so, the FIFO level can wake up the device just enough to perform DMA, then return to the reduced power mode. See Hardware Wake-up control register. 0 = trigger when the TX FIFO becomes empty. 1 = trigger when the TX FIFO level decreases to one entry. 15 = trigger when the TX FIFO level decreases to 15 entries (is no longer full). - 0x8 + 8 4 read-write RXLVL Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so, the FIFO level can wake up the device just enough to perform DMA, then return to the reduced power mode. See Hardware Wake-up control register. 0 = trigger when the RX FIFO has received one entry (is no longer empty). 1 = trigger when the RX FIFO has received two entries. 15 = trigger when the RX FIFO has received 16 entries (has become full). - 0x10 + 16 4 read-write @@ -28826,7 +28947,7 @@ RXERR Determines whether an interrupt occurs when a receive error occurs, based on the RXERR flag in the FIFOSTAT register. - 0x1 + 1 1 read-write @@ -28845,7 +28966,7 @@ TXLVL Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register. - 0x2 + 2 1 read-write @@ -28864,7 +28985,7 @@ RXLVL Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register. - 0x3 + 3 1 read-write @@ -28901,21 +29022,21 @@ RXERR Writing one clears the corresponding bits in the FIFOINTENSET register. - 0x1 + 1 1 read-write TXLVL Writing one clears the corresponding bits in the FIFOINTENSET register. - 0x2 + 2 1 read-write RXLVL Writing one clears the corresponding bits in the FIFOINTENSET register. - 0x3 + 3 1 read-write @@ -28940,28 +29061,28 @@ RXERR RX FIFO error. - 0x1 + 1 1 read-only TXLVL Transmit FIFO level interrupt. - 0x2 + 2 1 read-only RXLVL Receive FIFO level interrupt. - 0x3 + 3 1 read-only PERINT Peripheral interrupt. - 0x4 + 4 1 read-only @@ -29077,73 +29198,10 @@ - - SPI6 - FLEXCOMM6 - LPC5411x Serial Peripheral Interfaces (SPI) - SPI - 0x40097000 - - 0 - 0xE44 - registers - - - FLEXCOMM6 - 20 - - - - USART6 - FLEXCOMM6 - LPC5411x USARTs - USART - 0x40097000 - - 0 - 0xE44 - registers - - - FLEXCOMM6 - 20 - - - - FLEXCOMM7 - LPC5411x Flexcomm serial communication - FLEXCOMM - 0x40098000 - - 0 - 0x1000 - registers - - - FLEXCOMM7 - 21 - - - - I2C7 - FLEXCOMM7 - LPC5411x I2C-bus interfaces - I2C - 0x40098000 - - 0 - 0x884 - registers - - - FLEXCOMM7 - 21 - - I2S1 - FLEXCOMM7 LPC5411x I2S interface + FLEXCOMM7 I2S 0x40098000 @@ -29156,38 +29214,6 @@ 21 - - SPI7 - FLEXCOMM7 - LPC5411x Serial Peripheral Interfaces (SPI) - SPI - 0x40098000 - - 0 - 0xE44 - registers - - - FLEXCOMM7 - 21 - - - - USART7 - FLEXCOMM7 - LPC5411x USARTs - USART - 0x40098000 - - 0 - 0xE44 - registers - - - FLEXCOMM7 - 21 - - ADC0 LPC5411x 12-bit ADC controller (ADC) @@ -29230,7 +29256,7 @@ ASYNMODE Select clock mode. - 0x8 + 8 1 read-write @@ -29249,7 +29275,7 @@ RESOL The number of bits of ADC resolution. Accuracy can be reduced to achieve higher conversion rates. A single conversion (including one conversion in a burst or sequence) requires the selected number of bits of resolution plus 3 ADC clocks. This field must only be altered when the ADC is fully idle. Changing it during any kind of ADC operation may have unpredictable results. ADC clock frequencies for various resolutions must not exceed: - 5x the system clock rate for 12-bit resolution - 4.3x the system clock rate for 10-bit resolution - 3.6x the system clock for 8-bit resolution - 3x the bus clock rate for 6-bit resolution - 0x9 + 9 2 read-write @@ -29278,7 +29304,7 @@ BYPASSCAL Bypass Calibration. This bit may be set to avoid the need to calibrate if offset error is not a concern in the application. - 0xB + 11 1 read-write @@ -29297,7 +29323,7 @@ TSAMP Sample Time. The default sampling period (TSAMP = '000') at the start of each conversion is 2.5 ADC clock periods. Depending on a variety of factors, including operating conditions and the output impedance of the analog source, longer sampling times may be required. See Section 28.7.10. The TSAMP field specifies the number of additional ADC clock cycles, from zero to seven, by which the sample period will be extended. The total conversion time will increase by the same number of clocks. 000 - The sample period will be the default 2.5 ADC clocks. A complete conversion with 12-bits of accuracy will require 15 clocks. 001- The sample period will be extended by one ADC clock to a total of 3.5 clock periods. A complete 12-bit conversion will require 16 clocks. 010 - The sample period will be extended by two clocks to 4.5 ADC clock cycles. A complete 12-bit conversion will require 17 ADC clocks. 111 - The sample period will be extended by seven clocks to 9.5 ADC clock cycles. A complete 12-bit conversion will require 22 ADC clocks. - 0xC + 12 3 read-write @@ -29355,14 +29381,14 @@ TRIGGER Selects which of the available hardware trigger sources will cause this conversion sequence to be initiated. Program the trigger input number in this field. See Table 476. In order to avoid generating a spurious trigger, it is recommended writing to this field only when SEQA_ENA (bit 31) is low. It is safe to change this field and set bit 31 in the same write. - 0xC + 12 6 read-write TRIGPOL Select the polarity of the selected input trigger for this conversion sequence. In order to avoid generating a spurious trigger, it is recommended writing to this field only when SEQA_ENA (bit 31) is low. It is safe to change this field and set bit 31 in the same write. - 0x12 + 18 1 read-write @@ -29381,7 +29407,7 @@ SYNCBYPASS Setting this bit allows the hardware trigger input to bypass synchronization flip-flop stages and therefore shorten the time between the trigger input signal and the start of a conversion. There are slightly different criteria for whether or not this bit can be set depending on the clock operating mode: Synchronous mode (the ASYNMODE in the CTRL register = 0): Synchronization may be bypassed (this bit may be set) if the selected trigger source is already synchronous with the main system clock (eg. coming from an on-chip, system-clock-based timer). Whether this bit is set or not, a trigger pulse must be maintained for at least one system clock period. Asynchronous mode (the ASYNMODE in the CTRL register = 1): Synchronization may be bypassed (this bit may be set) if it is certain that the duration of a trigger input pulse will be at least one cycle of the ADC clock (regardless of whether the trigger comes from and on-chip or off-chip source). If this bit is NOT set, the trigger pulse must at least be maintained for one system clock period. - 0x13 + 19 1 read-write @@ -29400,28 +29426,28 @@ START Writing a 1 to this field will launch one pass through this conversion sequence. The behavior will be identical to a sequence triggered by a hardware trigger. Do not write 1 to this bit if the BURST bit is set. This bit is only set to a 1 momentarily when written to launch a conversion sequence. It will consequently always read back as a zero. - 0x1A + 26 1 read-write BURST Writing a 1 to this bit will cause this conversion sequence to be continuously cycled through. Other sequence A triggers will be ignored while this bit is set. Repeated conversions can be halted by clearing this bit. The sequence currently in progress will be completed before conversions are terminated. Note that a new sequence could begin just before BURST is cleared. - 0x1B + 27 1 read-write SINGLESTEP When this bit is set, a hardware trigger or a write to the START bit will launch a single conversion on the next channel in the sequence instead of the default response of launching an entire sequence of conversions. Once all of the channels comprising a sequence have been converted, a subsequent trigger will repeat the sequence beginning with the first enabled channel. Interrupt generation will still occur either after each individual conversion or at the end of the entire sequence, depending on the state of the MODE bit. - 0x1C + 28 1 read-write LOWPRIO Set priority for sequence A. - 0x1D + 29 1 read-write @@ -29440,7 +29466,7 @@ MODE Indicates whether the primary method for retrieving conversion results for this sequence will be accomplished via reading the global data register (SEQA_GDAT) at the end of each conversion, or the individual channel result registers at the end of the entire sequence. Impacts when conversion-complete interrupt/DMA trigger for sequence-A will be generated and which overrun conditions contribute to an overrun interrupt as described below. - 0x1E + 30 1 read-write @@ -29459,7 +29485,7 @@ SEQ_ENA Sequence Enable. In order to avoid spuriously triggering the sequence, care should be taken to only set the SEQn_ENA bit when the selected trigger input is in its INACTIVE state (as defined by the TRIGPOL bit). If this condition is not met, the sequence will be triggered immediately upon being enabled. In order to avoid spuriously triggering the sequence, care should be taken to only set the SEQn_ENA bit when the selected trigger input is in its INACTIVE state (as defined by the TRIGPOL bit). If this condition is not met, the sequence will be triggered immediately upon being enabled. - 0x1F + 31 1 read-write @@ -29492,42 +29518,42 @@ RESULT This field contains the 12-bit ADC conversion result from the most recent conversion performed under conversion sequence associated with this register. The result is a binary fraction representing the voltage on the currently-selected input channel as it falls within the range of VREFP to VREFN. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VREFN, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP. DATAVALID = 1 indicates that this result has not yet been read. - 0x4 + 4 12 read-only THCMPRANGE Indicates whether the result of the last conversion performed was above, below or within the range established by the designated threshold comparison registers (THRn_LOW and THRn_HIGH). - 0x10 + 16 2 read-only THCMPCROSS Indicates whether the result of the last conversion performed represented a crossing of the threshold level established by the designated LOW threshold comparison register (THRn_LOW) and, if so, in what direction the crossing occurred. - 0x12 + 18 2 read-only CHN These bits contain the channel from which the RESULT bits were converted (e.g. 0000 identifies channel 0, 0001 channel 1, etc.). - 0x1A + 26 4 read-only OVERRUN This bit is set if a new conversion result is loaded into the RESULT field before a previous result has been read - i.e. while the DATAVALID bit is set. This bit is cleared, along with the DATAVALID bit, whenever this register is read. This bit will contribute to an overrun interrupt/DMA trigger if the MODE bit (in SEQAA_CTRL) for the corresponding sequence is set to '0' (and if the overrun interrupt is enabled). - 0x1E + 30 1 read-only DATAVALID This bit is set to '1' at the end of each conversion when a new result is loaded into the RESULT field. It is cleared whenever this register is read. This bit will cause a conversion-complete interrupt for the corresponding sequence if the MODE bit (in SEQA_CTRL) for that sequence is set to 0 (and if the interrupt is enabled). - 0x1F + 31 1 read-only @@ -29547,42 +29573,42 @@ RESULT This field contains the 12-bit ADC conversion result from the last conversion performed on this channel. This will be a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to VREFN. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VREFN, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP. - 0x4 + 4 12 read-only THCMPRANGE Threshold Range Comparison result. 0x0 = In Range: The last completed conversion was greater than or equal to the value programmed into the designated LOW threshold register (THRn_LOW) but less than or equal to the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x1 = Below Range: The last completed conversion on was less than the value programmed into the designated LOW threshold register (THRn_LOW). 0x2 = Above Range: The last completed conversion was greater than the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x3 = Reserved. - 0x10 + 16 2 read-only THCMPCROSS Threshold Crossing Comparison result. 0x0 = No threshold Crossing detected: The most recent completed conversion on this channel had the same relationship (above or below) to the threshold value established by the designated LOW threshold register (THRn_LOW) as did the previous conversion on this channel. 0x1 = Reserved. 0x2 = Downward Threshold Crossing Detected. Indicates that a threshold crossing in the downward direction has occurred - i.e. the previous sample on this channel was above the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is below that threshold. 0x3 = Upward Threshold Crossing Detected. Indicates that a threshold crossing in the upward direction has occurred - i.e. the previous sample on this channel was below the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is above that threshold. - 0x12 + 18 2 read-only CHANNEL This field is hard-coded to contain the channel number that this particular register relates to (i.e. this field will contain 0b0000 for the DAT0 register, 0b0001 for the DAT1 register, etc) - 0x1A + 26 4 read-only OVERRUN This bit will be set to a 1 if a new conversion on this channel completes and overwrites the previous contents of the RESULT field before it has been read - i.e. while the DONE bit is set. This bit is cleared, along with the DONE bit, whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. This bit (in any of the 12 registers) will cause an overrun interrupt/DMA trigger to be asserted if the overrun interrupt is enabled. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled. - 0x1E + 30 1 read-only DATAVALID This bit is set to 1 when an ADC conversion on this channel completes. This bit is cleared whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled. - 0x1F + 31 1 read-only @@ -29600,7 +29626,7 @@ THRLOW Low threshold value against which ADC results will be compared - 0x4 + 4 12 read-write @@ -29618,7 +29644,7 @@ THRLOW Low threshold value against which ADC results will be compared - 0x4 + 4 12 read-write @@ -29636,7 +29662,7 @@ THRHIGH High threshold value against which ADC results will be compared - 0x4 + 4 12 read-write @@ -29654,7 +29680,7 @@ THRHIGH High threshold value against which ADC results will be compared - 0x4 + 4 12 read-write @@ -29691,77 +29717,77 @@ CH1_THRSEL Threshold select for channel 1. See description for channel 0. - 0x1 + 1 1 read-write CH2_THRSEL Threshold select for channel 2. See description for channel 0. - 0x2 + 2 1 read-write CH3_THRSEL Threshold select for channel 3. See description for channel 0. - 0x3 + 3 1 read-write CH4_THRSEL Threshold select for channel 4. See description for channel 0. - 0x4 + 4 1 read-write CH5_THRSEL Threshold select for channel 5. See description for channel 0. - 0x5 + 5 1 read-write CH6_THRSEL Threshold select for channel 6. See description for channel 0. - 0x6 + 6 1 read-write CH7_THRSEL Threshold select for channel 7. See description for channel 0. - 0x7 + 7 1 read-write CH8_THRSEL Threshold select for channel 8. See description for channel 0. - 0x8 + 8 1 read-write CH9_THRSEL Threshold select for channel 9. See description for channel 0. - 0x9 + 9 1 read-write CH10_THRSEL Threshold select for channel 10. See description for channel 0. - 0xA + 10 1 read-write CH11_THRSEL Threshold select for channel 11. See description for channel 0. - 0xB + 11 1 read-write @@ -29798,7 +29824,7 @@ SEQB_INTEN Sequence B interrupt enable. - 0x1 + 1 1 read-write @@ -29817,7 +29843,7 @@ OVR_INTEN Overrun interrupt enable. - 0x2 + 2 1 read-write @@ -29836,7 +29862,7 @@ ADCMPINTEN0 Threshold comparison interrupt enable for channel 0. - 0x3 + 3 2 read-write @@ -29860,77 +29886,77 @@ ADCMPINTEN1 Channel 1 threshold comparison interrupt enable. See description for channel 0. - 0x5 + 5 2 read-write ADCMPINTEN2 Channel 2 threshold comparison interrupt enable. See description for channel 0. - 0x7 + 7 2 read-write ADCMPINTEN3 Channel 3 threshold comparison interrupt enable. See description for channel 0. - 0x9 + 9 2 read-write ADCMPINTEN4 Channel 4 threshold comparison interrupt enable. See description for channel 0. - 0xB + 11 2 read-write ADCMPINTEN5 Channel 5 threshold comparison interrupt enable. See description for channel 0. - 0xD + 13 2 read-write ADCMPINTEN6 Channel 6 threshold comparison interrupt enable. See description for channel 0. - 0xF + 15 2 read-write ADCMPINTEN7 Channel 7 threshold comparison interrupt enable. See description for channel 0. - 0x11 + 17 2 read-write ADCMPINTEN8 Channel 8 threshold comparison interrupt enable. See description for channel 0. - 0x13 + 19 2 read-write ADCMPINTEN9 Channel 9 threshold comparison interrupt enable. See description for channel 0. - 0x15 + 21 2 read-write ADCMPINTEN10 Channel 10 threshold comparison interrupt enable. See description for channel 0. - 0x17 + 23 2 read-write ADCMPINTEN11 Channel 21 threshold comparison interrupt enable. See description for channel 0. - 0x19 + 25 2 read-write @@ -29955,203 +29981,203 @@ THCMP1 Threshold comparison event on Channel 1. See description for channel 0. - 0x1 + 1 1 read-write THCMP2 Threshold comparison event on Channel 2. See description for channel 0. - 0x2 + 2 1 read-write THCMP3 Threshold comparison event on Channel 3. See description for channel 0. - 0x3 + 3 1 read-write THCMP4 Threshold comparison event on Channel 4. See description for channel 0. - 0x4 + 4 1 read-write THCMP5 Threshold comparison event on Channel 5. See description for channel 0. - 0x5 + 5 1 read-write THCMP6 Threshold comparison event on Channel 6. See description for channel 0. - 0x6 + 6 1 read-write THCMP7 Threshold comparison event on Channel 7. See description for channel 0. - 0x7 + 7 1 read-write THCMP8 Threshold comparison event on Channel 8. See description for channel 0. - 0x8 + 8 1 read-write THCMP9 Threshold comparison event on Channel 9. See description for channel 0. - 0x9 + 9 1 read-write THCMP10 Threshold comparison event on Channel 10. See description for channel 0. - 0xA + 10 1 read-write THCMP11 Threshold comparison event on Channel 11. See description for channel 0. - 0xB + 11 1 read-write OVERRUN0 Mirrors the OVERRRUN status flag from the result register for ADC channel 0 - 0xC + 12 1 read-only OVERRUN1 Mirrors the OVERRRUN status flag from the result register for ADC channel 1 - 0xD + 13 1 read-only OVERRUN2 Mirrors the OVERRRUN status flag from the result register for ADC channel 2 - 0xE + 14 1 read-only OVERRUN3 Mirrors the OVERRRUN status flag from the result register for ADC channel 3 - 0xF + 15 1 read-only OVERRUN4 Mirrors the OVERRRUN status flag from the result register for ADC channel 4 - 0x10 + 16 1 read-only OVERRUN5 Mirrors the OVERRRUN status flag from the result register for ADC channel 5 - 0x11 + 17 1 read-only OVERRUN6 Mirrors the OVERRRUN status flag from the result register for ADC channel 6 - 0x12 + 18 1 read-only OVERRUN7 Mirrors the OVERRRUN status flag from the result register for ADC channel 7 - 0x13 + 19 1 read-only OVERRUN8 Mirrors the OVERRRUN status flag from the result register for ADC channel 8 - 0x14 + 20 1 read-only OVERRUN9 Mirrors the OVERRRUN status flag from the result register for ADC channel 9 - 0x15 + 21 1 read-only OVERRUN10 Mirrors the OVERRRUN status flag from the result register for ADC channel 10 - 0x16 + 22 1 read-only OVERRUN11 Mirrors the OVERRRUN status flag from the result register for ADC channel 11 - 0x17 + 23 1 read-only SEQA_OVR Mirrors the global OVERRUN status flag in the SEQA_GDAT register - 0x18 + 24 1 read-only SEQB_OVR Mirrors the global OVERRUN status flag in the SEQB_GDAT register - 0x19 + 25 1 read-only SEQA_INT Sequence A interrupt/DMA trigger. If the MODE bit in the SEQA_CTRL register is 0, this flag will mirror the DATAVALID bit in the sequence A global data register (SEQA_GDAT), which is set at the end of every ADC conversion performed as part of sequence A. It will be cleared automatically when the SEQA_GDAT register is read. If the MODE bit in the SEQA_CTRL register is 1, this flag will be set upon completion of an entire A sequence. In this case it must be cleared by writing a 1 to this SEQA_INT bit. This interrupt must be enabled in the INTEN register. - 0x1C + 28 1 read-only SEQB_INT Sequence A interrupt/DMA trigger. If the MODE bit in the SEQB_CTRL register is 0, this flag will mirror the DATAVALID bit in the sequence A global data register (SEQB_GDAT), which is set at the end of every ADC conversion performed as part of sequence B. It will be cleared automatically when the SEQB_GDAT register is read. If the MODE bit in the SEQB_CTRL register is 1, this flag will be set upon completion of an entire B sequence. In this case it must be cleared by writing a 1 to this SEQB_INT bit. This interrupt must be enabled in the INTEN register. - 0x1D + 29 1 read-only THCMP_INT Threshold Comparison Interrupt. This bit will be set if any of the THCMP flags in the lower bits of this register are set to 1 (due to an enabled out-of-range or threshold-crossing event on any channel). Each type of threshold comparison interrupt on each channel must be individually enabled in the INTEN register to cause this interrupt. This bit will be cleared when all of the individual threshold flags are cleared via writing 1s to those bits. - 0x1E + 30 1 read-only OVR_INT Overrun Interrupt flag. Any overrun bit in any of the individual channel data registers will cause this interrupt. In addition, if the MODE bit in either of the SEQn_CTRL registers is 0 then the OVERRUN bit in the corresponding SEQn_GDAT register will also cause this interrupt. This interrupt must be enabled in the INTEN register. This bit will be cleared when all of the individual overrun bits have been cleared via reading the corresponding data registers. - 0x1F + 31 1 read-only @@ -30176,7 +30202,7 @@ ADC_INIT ADC Initialization. After enabling the ADC (setting the ADC_ENA bit), the API routine will EITHER set this bit or the CALIB bit in the CALIB register, depending on whether or not calibration is required. Setting this bit will launch the 'dummy' conversion cycle that is required if a calibration is not performed. It will also reload the stored calibration value from a previous calibration unless the BYPASSCAL bit is set. This bit should only be set AFTER the ADC_ENA bit is set and after the CALIREQD bit is tested to determine whether a calibration or an ADC dummy conversion cycle is required. It should not be set during the same write that sets the ADC_ENA bit. This bit can only be set to a '1' by software. It is cleared automatically when the 'dummy' conversion cycle completes. - 0x1 + 1 1 read-write @@ -30201,14 +30227,14 @@ CALREQD Calibration required. This read-only bit indicates if calibration is required when enabling the ADC. CALREQD will be '1' if no calibration has been run since the chip was powered-up and if the BYPASSCAL bit in the CTRL register is low. Software will test this bit to determine whether to initiate a calibration cycle or whether to set the ADC_INIT bit (in the STARTUP register) to launch the ADC initialization process which includes a 'dummy' conversion cycle. Note: A 'dummy' conversion cycle requires approximately 6 ADC clocks as opposed to 81 clocks required for calibration. - 0x1 + 1 1 read-write CALVALUE Calibration Value. This read-only field displays the calibration value established during last calibration cycle. This value is not typically of any use to the user. - 0x2 + 2 7 read-write @@ -30216,5 +30242,5710 @@ + + ITM + Instrumentation Trace Macrocell Registers + ITM + ITM_ + 0xE0000000 + + 0 + 0x1000 + registers + + + + STIM0_READ + Stimulus Port Register 0 (for reading) + STIM0_READ_STIM0_WRITE + 0 + 32 + read-write + 0 + 0xFFFFFFFE + + + FIFOREADY + no description available + 0 + 1 + read-write + + + + + STIM0_WRITE + Stimulus Port Register 0 (for writing) + STIM0_READ_STIM0_WRITE + 0 + 32 + read-write + 0 + 0 + + + STIMULUS + Data write to the stimulus port FIFO, for forwarding as a software event packet. + 0 + 32 + read-write + + + + + STIM1_READ + Stimulus Port Register 1 (for reading) + STIM1_READ_STIM1_WRITE + 0x4 + 32 + read-write + 0 + 0xFFFFFFFE + + + FIFOREADY + no description available + 0 + 1 + read-write + + + + + STIM1_WRITE + Stimulus Port Register 1 (for writing) + STIM1_READ_STIM1_WRITE + 0x4 + 32 + read-write + 0 + 0 + + + STIMULUS + Data write to the stimulus port FIFO, for forwarding as a software event packet. + 0 + 32 + read-write + + + + + STIM2_READ + Stimulus Port Register 2 (for reading) + STIM2_READ_STIM2_WRITE + 0x8 + 32 + read-write + 0 + 0xFFFFFFFE + + + FIFOREADY + no description available + 0 + 1 + read-write + + + + + STIM2_WRITE + Stimulus Port Register 2 (for writing) + STIM2_READ_STIM2_WRITE + 0x8 + 32 + read-write + 0 + 0 + + + STIMULUS + Data write to the stimulus port FIFO, for forwarding as a software event packet. + 0 + 32 + read-write + + + + + STIM3_READ + Stimulus Port Register 3 (for reading) + STIM3_READ_STIM3_WRITE + 0xC + 32 + read-write + 0 + 0xFFFFFFFE + + + FIFOREADY + no description available + 0 + 1 + read-write + + + + + STIM3_WRITE + Stimulus Port Register 3 (for writing) + STIM3_READ_STIM3_WRITE + 0xC + 32 + read-write + 0 + 0 + + + STIMULUS + Data write to the stimulus port FIFO, for forwarding as a software event packet. + 0 + 32 + read-write + + + + + STIM4_READ + Stimulus Port Register 4 (for reading) + STIM4_READ_STIM4_WRITE + 0x10 + 32 + read-write + 0 + 0xFFFFFFFE + + + FIFOREADY + no description available + 0 + 1 + read-write + + + + + STIM4_WRITE + Stimulus Port Register 4 (for writing) + STIM4_READ_STIM4_WRITE + 0x10 + 32 + read-write + 0 + 0 + + + STIMULUS + Data write to the stimulus port FIFO, for forwarding as a software event packet. + 0 + 32 + read-write + + + + + STIM5_READ + Stimulus Port Register 5 (for reading) + STIM5_READ_STIM5_WRITE + 0x14 + 32 + read-write + 0 + 0xFFFFFFFE + + + FIFOREADY + no description available + 0 + 1 + read-write + + + + + STIM5_WRITE + Stimulus Port Register 5 (for writing) + STIM5_READ_STIM5_WRITE + 0x14 + 32 + read-write + 0 + 0 + + + STIMULUS + Data write to the stimulus port FIFO, for forwarding as a software event packet. + 0 + 32 + read-write + + + + + STIM6_READ + Stimulus Port Register 6 (for reading) + STIM6_READ_STIM6_WRITE + 0x18 + 32 + read-write + 0 + 0xFFFFFFFE + + + FIFOREADY + no description available + 0 + 1 + read-write + + + + + STIM6_WRITE + Stimulus Port Register 6 (for writing) + STIM6_READ_STIM6_WRITE + 0x18 + 32 + read-write + 0 + 0 + + + STIMULUS + Data write to the stimulus port FIFO, for forwarding as a software event packet. + 0 + 32 + read-write + + + + + STIM7_READ + Stimulus Port Register 7 (for reading) + STIM7_READ_STIM7_WRITE + 0x1C + 32 + read-write + 0 + 0xFFFFFFFE + + + FIFOREADY + no description available + 0 + 1 + read-write + + + + + STIM7_WRITE + Stimulus Port Register 7 (for writing) + STIM7_READ_STIM7_WRITE + 0x1C + 32 + read-write + 0 + 0 + + + STIMULUS + Data write to the stimulus port FIFO, for forwarding as a software event packet. + 0 + 32 + read-write + + + + + STIM8_READ + Stimulus Port Register 8 (for reading) + STIM8_READ_STIM8_WRITE + 0x20 + 32 + read-write + 0 + 0xFFFFFFFE + + + FIFOREADY + no description available + 0 + 1 + read-write + + + + + STIM8_WRITE + Stimulus Port Register 8 (for writing) + STIM8_READ_STIM8_WRITE + 0x20 + 32 + read-write + 0 + 0 + + + STIMULUS + Data write to the stimulus port FIFO, for forwarding as a software event packet. + 0 + 32 + read-write + + + + + STIM9_READ + Stimulus Port Register 9 (for reading) + STIM9_READ_STIM9_WRITE + 0x24 + 32 + read-write + 0 + 0xFFFFFFFE + + + FIFOREADY + no description available + 0 + 1 + read-write + + + + + STIM9_WRITE + Stimulus Port Register 9 (for writing) + STIM9_READ_STIM9_WRITE + 0x24 + 32 + read-write + 0 + 0 + + + STIMULUS + Data write to the stimulus port FIFO, for forwarding as a software event packet. + 0 + 32 + read-write + + + + + STIM10_READ + Stimulus Port Register 10 (for reading) + STIM10_READ_STIM10_WRITE + 0x28 + 32 + read-write + 0 + 0xFFFFFFFE + + + FIFOREADY + no description available + 0 + 1 + read-write + + + + + STIM10_WRITE + Stimulus Port Register 10 (for writing) + STIM10_READ_STIM10_WRITE + 0x28 + 32 + read-write + 0 + 0 + + + STIMULUS + Data write to the stimulus port FIFO, for forwarding as a software event packet. + 0 + 32 + read-write + + + + + STIM11_READ + Stimulus Port Register 11 (for reading) + STIM11_READ_STIM11_WRITE + 0x2C + 32 + read-write + 0 + 0xFFFFFFFE + + + FIFOREADY + no description available + 0 + 1 + read-write + + + + + STIM11_WRITE + Stimulus Port Register 11 (for writing) + STIM11_READ_STIM11_WRITE + 0x2C + 32 + read-write + 0 + 0 + + + STIMULUS + Data write to the stimulus port FIFO, for forwarding as a software event packet. + 0 + 32 + read-write + + + + + STIM12_READ + Stimulus Port Register 12 (for reading) + STIM12_READ_STIM12_WRITE + 0x30 + 32 + read-write + 0 + 0xFFFFFFFE + + + FIFOREADY + no description available + 0 + 1 + read-write + + + + + STIM12_WRITE + Stimulus Port Register 12 (for writing) + STIM12_READ_STIM12_WRITE + 0x30 + 32 + read-write + 0 + 0 + + + STIMULUS + Data write to the stimulus port FIFO, for forwarding as a software event packet. + 0 + 32 + read-write + + + + + STIM13_READ + Stimulus Port Register 13 (for reading) + STIM13_READ_STIM13_WRITE + 0x34 + 32 + read-write + 0 + 0xFFFFFFFE + + + FIFOREADY + no description available + 0 + 1 + read-write + + + + + STIM13_WRITE + Stimulus Port Register 13 (for writing) + STIM13_READ_STIM13_WRITE + 0x34 + 32 + read-write + 0 + 0 + + + STIMULUS + Data write to the stimulus port FIFO, for forwarding as a software event packet. + 0 + 32 + read-write + + + + + STIM14_READ + Stimulus Port Register 14 (for reading) + STIM14_READ_STIM14_WRITE + 0x38 + 32 + read-write + 0 + 0xFFFFFFFE + + + FIFOREADY + no description available + 0 + 1 + read-write + + + + + STIM14_WRITE + Stimulus Port Register 14 (for writing) + STIM14_READ_STIM14_WRITE + 0x38 + 32 + read-write + 0 + 0 + + + STIMULUS + Data write to the stimulus port FIFO, for forwarding as a software event packet. + 0 + 32 + read-write + + + + + STIM15_READ + Stimulus Port Register 15 (for reading) + STIM15_READ_STIM15_WRITE + 0x3C + 32 + read-write + 0 + 0xFFFFFFFE + + + FIFOREADY + no description available + 0 + 1 + read-write + + + + + STIM15_WRITE + Stimulus Port Register 15 (for writing) + STIM15_READ_STIM15_WRITE + 0x3C + 32 + read-write + 0 + 0 + + + STIMULUS + Data write to the stimulus port FIFO, for forwarding as a software event packet. + 0 + 32 + read-write + + + + + STIM16_READ + Stimulus Port Register 16 (for reading) + STIM16_READ_STIM16_WRITE + 0x40 + 32 + read-write + 0 + 0xFFFFFFFE + + + FIFOREADY + no description available + 0 + 1 + read-write + + + + + STIM16_WRITE + Stimulus Port Register 16 (for writing) + STIM16_READ_STIM16_WRITE + 0x40 + 32 + read-write + 0 + 0 + + + STIMULUS + Data write to the stimulus port FIFO, for forwarding as a software event packet. + 0 + 32 + read-write + + + + + STIM17_READ + Stimulus Port Register 17 (for reading) + STIM17_READ_STIM17_WRITE + 0x44 + 32 + read-write + 0 + 0xFFFFFFFE + + + FIFOREADY + no description available + 0 + 1 + read-write + + + + + STIM17_WRITE + Stimulus Port Register 17 (for writing) + STIM17_READ_STIM17_WRITE + 0x44 + 32 + read-write + 0 + 0 + + + STIMULUS + Data write to the stimulus port FIFO, for forwarding as a software event packet. + 0 + 32 + read-write + + + + + STIM18_READ + Stimulus Port Register 18 (for reading) + STIM18_READ_STIM18_WRITE + 0x48 + 32 + read-write + 0 + 0xFFFFFFFE + + + FIFOREADY + no description available + 0 + 1 + read-write + + + + + STIM18_WRITE + Stimulus Port Register 18 (for writing) + STIM18_READ_STIM18_WRITE + 0x48 + 32 + read-write + 0 + 0 + + + STIMULUS + Data write to the stimulus port FIFO, for forwarding as a software event packet. + 0 + 32 + read-write + + + + + STIM19_READ + Stimulus Port Register 19 (for reading) + STIM19_READ_STIM19_WRITE + 0x4C + 32 + read-write + 0 + 0xFFFFFFFE + + + FIFOREADY + no description available + 0 + 1 + read-write + + + + + STIM19_WRITE + Stimulus Port Register 19 (for writing) + STIM19_READ_STIM19_WRITE + 0x4C + 32 + read-write + 0 + 0 + + + STIMULUS + Data write to the stimulus port FIFO, for forwarding as a software event packet. + 0 + 32 + read-write + + + + + STIM20_READ + Stimulus Port Register 20 (for reading) + STIM20_READ_STIM20_WRITE + 0x50 + 32 + read-write + 0 + 0xFFFFFFFE + + + FIFOREADY + no description available + 0 + 1 + read-write + + + + + STIM20_WRITE + Stimulus Port Register 20 (for writing) + STIM20_READ_STIM20_WRITE + 0x50 + 32 + read-write + 0 + 0 + + + STIMULUS + Data write to the stimulus port FIFO, for forwarding as a software event packet. + 0 + 32 + read-write + + + + + STIM21_READ + Stimulus Port Register 21 (for reading) + STIM21_READ_STIM21_WRITE + 0x54 + 32 + read-write + 0 + 0xFFFFFFFE + + + FIFOREADY + no description available + 0 + 1 + read-write + + + + + STIM21_WRITE + Stimulus Port Register 21 (for writing) + STIM21_READ_STIM21_WRITE + 0x54 + 32 + read-write + 0 + 0 + + + STIMULUS + Data write to the stimulus port FIFO, for forwarding as a software event packet. + 0 + 32 + read-write + + + + + STIM22_READ + Stimulus Port Register 22 (for reading) + STIM22_READ_STIM22_WRITE + 0x58 + 32 + read-write + 0 + 0xFFFFFFFE + + + FIFOREADY + no description available + 0 + 1 + read-write + + + + + STIM22_WRITE + Stimulus Port Register 22 (for writing) + STIM22_READ_STIM22_WRITE + 0x58 + 32 + read-write + 0 + 0 + + + STIMULUS + Data write to the stimulus port FIFO, for forwarding as a software event packet. + 0 + 32 + read-write + + + + + STIM23_READ + Stimulus Port Register 23 (for reading) + STIM23_READ_STIM23_WRITE + 0x5C + 32 + read-write + 0 + 0xFFFFFFFE + + + FIFOREADY + no description available + 0 + 1 + read-write + + + + + STIM23_WRITE + Stimulus Port Register 23 (for writing) + STIM23_READ_STIM23_WRITE + 0x5C + 32 + read-write + 0 + 0 + + + STIMULUS + Data write to the stimulus port FIFO, for forwarding as a software event packet. + 0 + 32 + read-write + + + + + STIM24_READ + Stimulus Port Register 24 (for reading) + STIM24_READ_STIM24_WRITE + 0x60 + 32 + read-write + 0 + 0xFFFFFFFE + + + FIFOREADY + no description available + 0 + 1 + read-write + + + + + STIM24_WRITE + Stimulus Port Register 24 (for writing) + STIM24_READ_STIM24_WRITE + 0x60 + 32 + read-write + 0 + 0 + + + STIMULUS + Data write to the stimulus port FIFO, for forwarding as a software event packet. + 0 + 32 + read-write + + + + + STIM25_READ + Stimulus Port Register 25 (for reading) + STIM25_READ_STIM25_WRITE + 0x64 + 32 + read-write + 0 + 0xFFFFFFFE + + + FIFOREADY + no description available + 0 + 1 + read-write + + + + + STIM25_WRITE + Stimulus Port Register 25 (for writing) + STIM25_READ_STIM25_WRITE + 0x64 + 32 + read-write + 0 + 0 + + + STIMULUS + Data write to the stimulus port FIFO, for forwarding as a software event packet. + 0 + 32 + read-write + + + + + STIM26_READ + Stimulus Port Register 26 (for reading) + STIM26_READ_STIM26_WRITE + 0x68 + 32 + read-write + 0 + 0xFFFFFFFE + + + FIFOREADY + no description available + 0 + 1 + read-write + + + + + STIM26_WRITE + Stimulus Port Register 26 (for writing) + STIM26_READ_STIM26_WRITE + 0x68 + 32 + read-write + 0 + 0 + + + STIMULUS + Data write to the stimulus port FIFO, for forwarding as a software event packet. + 0 + 32 + read-write + + + + + STIM27_READ + Stimulus Port Register 27 (for reading) + STIM27_READ_STIM27_WRITE + 0x6C + 32 + read-write + 0 + 0xFFFFFFFE + + + FIFOREADY + no description available + 0 + 1 + read-write + + + + + STIM27_WRITE + Stimulus Port Register 27 (for writing) + STIM27_READ_STIM27_WRITE + 0x6C + 32 + read-write + 0 + 0 + + + STIMULUS + Data write to the stimulus port FIFO, for forwarding as a software event packet. + 0 + 32 + read-write + + + + + STIM28_READ + Stimulus Port Register 28 (for reading) + STIM28_READ_STIM28_WRITE + 0x70 + 32 + read-write + 0 + 0xFFFFFFFE + + + FIFOREADY + no description available + 0 + 1 + read-write + + + + + STIM28_WRITE + Stimulus Port Register 28 (for writing) + STIM28_READ_STIM28_WRITE + 0x70 + 32 + read-write + 0 + 0 + + + STIMULUS + Data write to the stimulus port FIFO, for forwarding as a software event packet. + 0 + 32 + read-write + + + + + STIM29_READ + Stimulus Port Register 29 (for reading) + STIM29_READ_STIM29_WRITE + 0x74 + 32 + read-write + 0 + 0xFFFFFFFE + + + FIFOREADY + no description available + 0 + 1 + read-write + + + + + STIM29_WRITE + Stimulus Port Register 29 (for writing) + STIM29_READ_STIM29_WRITE + 0x74 + 32 + read-write + 0 + 0 + + + STIMULUS + Data write to the stimulus port FIFO, for forwarding as a software event packet. + 0 + 32 + read-write + + + + + STIM30_READ + Stimulus Port Register 30 (for reading) + STIM30_READ_STIM30_WRITE + 0x78 + 32 + read-write + 0 + 0xFFFFFFFE + + + FIFOREADY + no description available + 0 + 1 + read-write + + + + + STIM30_WRITE + Stimulus Port Register 30 (for writing) + STIM30_READ_STIM30_WRITE + 0x78 + 32 + read-write + 0 + 0 + + + STIMULUS + Data write to the stimulus port FIFO, for forwarding as a software event packet. + 0 + 32 + read-write + + + + + STIM31_READ + Stimulus Port Register 31 (for reading) + STIM31_READ_STIM31_WRITE + 0x7C + 32 + read-write + 0 + 0xFFFFFFFE + + + FIFOREADY + no description available + 0 + 1 + read-write + + + + + STIM31_WRITE + Stimulus Port Register 31 (for writing) + STIM31_READ_STIM31_WRITE + 0x7C + 32 + read-write + 0 + 0 + + + STIMULUS + Data write to the stimulus port FIFO, for forwarding as a software event packet. + 0 + 32 + read-write + + + + + TER + Trace Enable Register + 0xE00 + 32 + read-write + 0 + 0xFFFFFFFF + + + STIMENA + For bit STIMENA[n], in register ITM_TERx: 0 = Stimulus port (32x + n) disabled 1 = Stimulus port (32x + n) enabled + 0 + 32 + read-write + + + + + TPR + Trace Privilege Register + 0xE40 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRIVMASK + Bit mask to enable tracing on ITM stimulus ports: Bit [0] = stimulus port [7:0] Bit [1] = stimulus port [15:8] Bit [2] = stimulus port [23:16] Bit [3] = stimulus port [31:24] + 0 + 4 + read-write + + + + + TCR + Trace Control Register + 0xE80 + 32 + read-write + 0 + 0xFFFFFFFF + + + ITMENA + no description available + 0 + 1 + read-write + + + ITMENA_0 + Disabled. + 0 + + + ITMENA_1 + Enabled. + 0x1 + + + + + TSENA + no description available + 1 + 1 + read-write + + + TSENA_0 + Disabled. + 0 + + + TSENA_1 + Enabled. + 0x1 + + + + + SYNCENA + no description available + 2 + 1 + read-write + + + SYNCENA_0 + Disabled. + 0 + + + SYNCENA_1 + Enabled. + 0x1 + + + + + TXENA + no description available + 3 + 1 + read-write + + + TXENA_0 + Disabled. + 0 + + + TXENA_1 + Enabled. + 0x1 + + + + + SWOENA + no description available + 4 + 1 + read-write + + + SWOENA_0 + Timestamp counter uses the processor system clock. + 0 + + + SWOENA_1 + Timestamp counter uses asynchronous clock from the TPIU interface. + 0x1 + + + + + TSPrescale + Local timestamp prescaler, used with the trace packet reference clock. + 8 + 2 + read-write + + + TSPrescale_0 + No prescaling. + 0 + + + TSPrescale_1 + Divide by 4. + 0x1 + + + TSPrescale_2 + Divide by 16. + 0x2 + + + TSPrescale_3 + Divide by 64. + 0x3 + + + + + GTSFREQ + Global timestamp frequency. Defines how often the ITM generates a global timestamp, based on the global timestamp clock frequency, or disables generation of global timestamps. + 10 + 2 + read-write + + + GTSFREQ_0 + Disable generation of global timestamps. + 0 + + + GTSFREQ_1 + Generate timestamp request whenever the ITM detects a change in global timestamp counter bits [47:7]. This is approximately every 128 cycles. + 0x1 + + + GTSFREQ_2 + Generate timestamp request whenever the ITM detects a change in global timestamp counter bits [47:13]. This is approximately every 8192 cycles. + 0x2 + + + GTSFREQ_3 + Generate a timestamp after every packet, if the output FIFO is empty. + 0x3 + + + + + TraceBusID + Identifier for multi-source trace stream formatting. If multi-source trace is in use, the debugger must write a non-zero value to this field. + 16 + 7 + read-write + + + BUSY + Indicates whether the ITM is currently processing events: 0: ITM is not processing any events. 1: ITM events present and being drained. + 23 + 1 + read-only + + + BUSY_0 + ITM is not processing any events. + 0 + + + BUSY_1 + ITM events present and beeing drained. + 0x1 + + + + + + + LAR + Lock Access Register + 0xFB0 + 32 + read-write + 0 + 0 + + + WriteAccessCode + Write Access Code. A write of 0xC5ACCE55 enables further write access to this device. An invalid write will have the affect of removing write access. + 0 + 32 + read-write + + + + + LSR + Lock Status Register + 0xFB4 + 32 + read-only + 0x1 + 0xFFFFFFFD + + + IMP + Lock mechanism is implemented. This bit always reads 1. + 0 + 1 + read-only + + + STATUS + Lock Status. This bit is HIGH when the device is locked, and LOW when unlocked. + 1 + 1 + read-only + + + s8BIT + Access Lock Register size. This bit reads 0 to indicate a 32-bit register is present. + 2 + 1 + read-only + + + + + PID4 + Peripheral Identification Register 4. + 0xFD0 + 32 + read-only + 0x4 + 0xFFFFFFFF + + + JEP106 + JEP106 continuation code. + 0 + 4 + read-only + + + c4KB + 4KB Count + 4 + 4 + read-only + + + + + PID5 + Peripheral Identification Register 5. + 0xFD4 + 32 + read-only + 0 + 0xFFFFFFFF + + + PID6 + Peripheral Identification Register 6. + 0xFD8 + 32 + read-only + 0 + 0xFFFFFFFF + + + PID7 + Peripheral Identification Register 7. + 0xFDC + 32 + read-only + 0 + 0xFFFFFFFF + + + PID0 + Peripheral Identification Register 0. + 0xFE0 + 32 + read-only + 0x2 + 0xFFFFFFFF + + + PartNumber + Part Number [7:0] + 0 + 8 + read-only + + + + + PID1 + Peripheral Identification Register 1. + 0xFE4 + 32 + read-only + 0xB0 + 0xFFFFFFFF + + + PartNumber + Part Number [11:8] + 0 + 4 + read-only + + + JEP106_identity_code + JEP106 identity code [3:0] + 4 + 4 + read-only + + + + + PID2 + Peripheral Identification Register 2. + 0xFE8 + 32 + read-only + 0x3B + 0xFFFFFFFF + + + JEP106_identity_code + JEP106 identity code [6:4] + 0 + 3 + read-only + + + Revision + Revision + 4 + 4 + read-only + + + + + PID3 + Peripheral Identification Register 3. + 0xFEC + 32 + read-only + 0 + 0xFFFFFFFF + + + CustomerModified + Customer Modified. + 0 + 4 + read-only + + + RevAnd + RevAnd + 4 + 4 + read-only + + + + + CID0 + Component Identification Register 0. + 0xFF0 + 32 + read-only + 0xD + 0xFFFFFFFF + + + Preamble + Preamble + 0 + 8 + read-only + + + + + CID1 + Component Identification Register 1. + 0xFF4 + 32 + read-only + 0xE0 + 0xFFFFFFFF + + + Preamble + Preamble + 0 + 4 + read-only + + + ComponentClass + Component class + 4 + 4 + read-only + + + ComponentClass_1 + ROM table. + 0x1 + + + ComponentClass_9 + CoreSight component. + 0x9 + + + ComponentClass_15 + PrimeCell of system component with no standardized register layout, for backward compatibility. + 0xF + + + + + + + CID2 + Component Identification Register 2. + 0xFF8 + 32 + read-only + 0x5 + 0xFFFFFFFF + + + Preamble + Preamble + 0 + 8 + read-only + + + + + CID3 + Component Identification Register 3. + 0xFFC + 32 + read-only + 0xB1 + 0xFFFFFFFF + + + Preamble + Preamble + 0 + 8 + read-only + + + + + + + SystemControl + System Control Block + SCB + SCB_ + 0xE000E000 + + 0 + 0xD40 + registers + + + + ACTLR + Auxiliary Control Register, + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DISMCYCINT + Disables interruption of multi-cycle instructions. + 0 + 1 + read-write + + + DISDEFWBUF + Disables write buffer use during default memory map accesses. + 1 + 1 + read-write + + + DISFOLD + Disables folding of IT instructions. + 2 + 1 + read-write + + + + + CPUID + CPUID Base Register + 0xD00 + 32 + read-only + 0x410FC240 + 0xFFFFFFFF + + + REVISION + Indicates patch release: 0x0 = Patch 0 + 0 + 4 + read-only + + + PARTNO + Indicates part number + 4 + 12 + read-only + + + VARIANT + Indicates processor revision: 0x2 = Revision 2 + 20 + 4 + read-only + + + IMPLEMENTER + Implementer code + 24 + 8 + read-only + + + + + ICSR + Interrupt Control and State Register + 0xD04 + 32 + read-write + 0 + 0xFFFFFFFF + + + VECTACTIVE + Active exception number + 0 + 9 + read-only + + + RETTOBASE + no description available + 11 + 1 + read-only + + + RETTOBASE_0 + there are preempted active exceptions to execute + 0 + + + RETTOBASE_1 + there are no active exceptions, or the currently-executing exception is the only active exception + 0x1 + + + + + VECTPENDING + Exception number of the highest priority pending enabled exception + 12 + 6 + read-only + + + ISRPENDING + no description available + 22 + 1 + read-only + + + ISRPREEMPT + no description available + 23 + 1 + read-only + + + ISRPREEMPT_0 + Will not service + 0 + + + ISRPREEMPT_1 + Will service a pending exception + 0x1 + + + + + PENDSTCLR + no description available + 25 + 1 + write-only + + + PENDSTCLR_0 + no effect + 0 + + + PENDSTCLR_1 + removes the pending state from the SysTick exception + 0x1 + + + + + PENDSTSET + no description available + 26 + 1 + read-write + + + PENDSTSET_0 + write: no effect; read: SysTick exception is not pending + 0 + + + PENDSTSET_1 + write: changes SysTick exception state to pending; read: SysTick exception is pending + 0x1 + + + + + PENDSVCLR + no description available + 27 + 1 + write-only + + + PENDSVCLR_0 + no effect + 0 + + + PENDSVCLR_1 + removes the pending state from the PendSV exception + 0x1 + + + + + PENDSVSET + no description available + 28 + 1 + read-write + + + PENDSVSET_0 + write: no effect; read: PendSV exception is not pending + 0 + + + PENDSVSET_1 + write: changes PendSV exception state to pending; read: PendSV exception is pending + 0x1 + + + + + NMIPENDSET + no description available + 31 + 1 + read-write + + + NMIPENDSET_0 + write: no effect; read: NMI exception is not pending + 0 + + + NMIPENDSET_1 + write: changes NMI exception state to pending; read: NMI exception is pending + 0x1 + + + + + + + VTOR + Vector Table Offset Register + 0xD08 + 32 + read-write + 0 + 0xFFFFFFFF + + + TBLOFF + Vector table base offset + 7 + 25 + read-write + + + + + AIRCR + Application Interrupt and Reset Control Register + 0xD0C + 32 + read-write + 0xFA050000 + 0xFFFFFFFF + + + VECTRESET + no description available + 0 + 1 + write-only + + + VECTCLRACTIVE + no description available + 1 + 1 + write-only + + + SYSRESETREQ + no description available + 2 + 1 + write-only + + + SYSRESETREQ_0 + no system reset request + 0 + + + SYSRESETREQ_1 + asserts a signal to the outer system that requests a reset + 0x1 + + + + + PRIGROUP + Interrupt priority grouping field. This field determines the split of group priority from subpriority. + 8 + 3 + read-write + + + ENDIANNESS + no description available + 15 + 1 + read-only + + + ENDIANNESS_0 + Little-endian + 0 + + + ENDIANNESS_1 + Big-endian + 0x1 + + + + + VECTKEY + Register key + 16 + 16 + read-write + + + + + SCR + System Control Register + 0xD10 + 32 + read-write + 0 + 0xFFFFFFFF + + + SLEEPONEXIT + no description available + 1 + 1 + read-write + + + SLEEPONEXIT_0 + o not sleep when returning to Thread mode + 0 + + + SLEEPONEXIT_1 + enter sleep, or deep sleep, on return from an ISR + 0x1 + + + + + SLEEPDEEP + no description available + 2 + 1 + read-write + + + SLEEPDEEP_0 + sleep + 0 + + + SLEEPDEEP_1 + deep sleep + 0x1 + + + + + SEVONPEND + no description available + 4 + 1 + read-write + + + SEVONPEND_0 + only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded + 0 + + + SEVONPEND_1 + enabled events and all interrupts, including disabled interrupts, can wakeup the processor + 0x1 + + + + + + + CCR + Configuration and Control Register + 0xD14 + 32 + read-write + 0 + 0xFFFFFFFF + + + NONBASETHRDENA + no description available + 0 + 1 + read-write + + + NONBASETHRDENA_0 + processor can enter Thread mode only when no exception is active + 0 + + + NONBASETHRDENA_1 + processor can enter Thread mode from any level under the control of an EXC_RETURN value + 0x1 + + + + + USERSETMPEND + Enables unprivileged software access to the STIR + 1 + 1 + read-write + + + USERSETMPEND_0 + disable + 0 + + + USERSETMPEND_1 + enable + 0x1 + + + + + UNALIGN_TRP + Enables unaligned access traps + 3 + 1 + read-write + + + UNALIGN_TRP_0 + do not trap unaligned halfword and word accesses + 0 + + + UNALIGN_TRP_1 + trap unaligned halfword and word accesses + 0x1 + + + + + DIV_0_TRP + Enables faulting or halting when the processor executes an SDIV or UDIV instruction with a divisor of 0 + 4 + 1 + read-write + + + DIV_0_TRP_0 + do not trap divide by 0 + 0 + + + DIV_0_TRP_1 + trap divide by 0 + 0x1 + + + + + BFHFNMIGN + Enables handlers with priority -1 or -2 to ignore data BusFaults caused by load and store instructions. + 8 + 1 + read-write + + + BFHFNMIGN_0 + data bus faults caused by load and store instructions cause a lock-up + 0 + + + BFHFNMIGN_1 + handlers running at priority -1 and -2 ignore data bus faults caused by load and store instructions + 0x1 + + + + + STKALIGN + Indicates stack alignment on exception entry + 9 + 1 + read-write + + + STKALIGN_0 + 4-byte aligned + 0 + + + STKALIGN_1 + 8-byte aligned + 0x1 + + + + + + + SHPR1 + System Handler Priority Register 1 + 0xD18 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRI_4 + Priority of system handler 4, MemManage + 0 + 8 + read-write + + + PRI_5 + Priority of system handler 5, BusFault + 8 + 8 + read-write + + + PRI_6 + Priority of system handler 6, UsageFault + 16 + 8 + read-write + + + + + SHPR2 + System Handler Priority Register 2 + 0xD1C + 32 + read-write + 0 + 0xFFFFFFFF + + + PRI_11 + Priority of system handler 11, SVCall + 24 + 8 + read-write + + + + + SHPR3 + System Handler Priority Register 3 + 0xD20 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRI_14 + Priority of system handler 14, PendSV + 16 + 8 + read-write + + + PRI_15 + Priority of system handler 15, SysTick exception + 24 + 8 + read-write + + + + + SHCSR + System Handler Control and State Register + 0xD24 + 32 + read-write + 0 + 0xFFFFFFFF + + + MEMFAULTACT + no description available + 0 + 1 + read-write + + + MEMFAULTACT_0 + exception is not active + 0 + + + MEMFAULTACT_1 + exception is active + 0x1 + + + + + BUSFAULTACT + no description available + 1 + 1 + read-write + + + BUSFAULTACT_0 + exception is not active + 0 + + + BUSFAULTACT_1 + exception is active + 0x1 + + + + + USGFAULTACT + no description available + 3 + 1 + read-write + + + USGFAULTACT_0 + exception is not active + 0 + + + USGFAULTACT_1 + exception is active + 0x1 + + + + + SVCALLACT + no description available + 7 + 1 + read-write + + + SVCALLACT_0 + exception is not active + 0 + + + SVCALLACT_1 + exception is active + 0x1 + + + + + MONITORACT + no description available + 8 + 1 + read-write + + + MONITORACT_0 + exception is not active + 0 + + + MONITORACT_1 + exception is active + 0x1 + + + + + PENDSVACT + no description available + 10 + 1 + read-write + + + PENDSVACT_0 + exception is not active + 0 + + + PENDSVACT_1 + exception is active + 0x1 + + + + + SYSTICKACT + no description available + 11 + 1 + read-write + + + SYSTICKACT_0 + exception is not active + 0 + + + SYSTICKACT_1 + exception is active + 0x1 + + + + + USGFAULTPENDED + no description available + 12 + 1 + read-write + + + USGFAULTPENDED_0 + exception is not pending + 0 + + + USGFAULTPENDED_1 + exception is pending + 0x1 + + + + + MEMFAULTPENDED + no description available + 13 + 1 + read-write + + + MEMFAULTPENDED_0 + exception is not pending + 0 + + + MEMFAULTPENDED_1 + exception is pending + 0x1 + + + + + BUSFAULTPENDED + no description available + 14 + 1 + read-write + + + BUSFAULTPENDED_0 + exception is not pending + 0 + + + BUSFAULTPENDED_1 + exception is pending + 0x1 + + + + + SVCALLPENDED + no description available + 15 + 1 + read-write + + + SVCALLPENDED_0 + exception is not pending + 0 + + + SVCALLPENDED_1 + exception is pending + 0x1 + + + + + MEMFAULTENA + no description available + 16 + 1 + read-write + + + MEMFAULTENA_0 + disable the exception + 0 + + + MEMFAULTENA_1 + enable the exception + 0x1 + + + + + BUSFAULTENA + no description available + 17 + 1 + read-write + + + BUSFAULTENA_0 + disable the exception + 0 + + + BUSFAULTENA_1 + enable the exception + 0x1 + + + + + USGFAULTENA + no description available + 18 + 1 + read-write + + + USGFAULTENA_0 + disable the exception + 0 + + + USGFAULTENA_1 + enable the exception + 0x1 + + + + + + + CFSR + Configurable Fault Status Registers + 0xD28 + 32 + read-write + 0 + 0xFFFFFFFF + + + IACCVIOL + no description available + 0 + 1 + read-write + + + IACCVIOL_0 + no instruction access violation fault + 0 + + + IACCVIOL_1 + the processor attempted an instruction fetch from a location that does not permit execution + 0x1 + + + + + DACCVIOL + no description available + 1 + 1 + read-write + + + DACCVIOL_0 + no data access violation fault + 0 + + + DACCVIOL_1 + the processor attempted a load or store at a location that does not permit the operation + 0x1 + + + + + MUNSTKERR + no description available + 3 + 1 + read-write + + + MUNSTKERR_0 + no unstacking fault + 0 + + + MUNSTKERR_1 + unstack for an exception return has caused one or more access violations + 0x1 + + + + + MSTKERR + no description available + 4 + 1 + read-write + + + MSTKERR_0 + no stacking fault + 0 + + + MSTKERR_1 + stacking for an exception entry has caused one or more access violations + 0x1 + + + + + MLSPERR + no description available + 5 + 1 + read-write + + + MLSPERR_0 + No MemManage fault occurred during floating-point lazy state preservation + 0 + + + MLSPERR_1 + A MemManage fault occurred during floating-point lazy state preservation + 0x1 + + + + + MMARVALID + no description available + 7 + 1 + read-write + + + MMARVALID_0 + value in MMAR is not a valid fault address + 0 + + + MMARVALID_1 + MMAR holds a valid fault address + 0x1 + + + + + IBUSERR + no description available + 8 + 1 + read-write + + + IBUSERR_0 + no instruction bus error + 0 + + + IBUSERR_1 + instruction bus error + 0x1 + + + + + PRECISERR + no description available + 9 + 1 + read-write + + + PRECISERR_0 + no precise data bus error + 0 + + + PRECISERR_1 + a data bus error has occurred, and the PC value stacked for the exception return points to the instruction that caused the fault + 0x1 + + + + + IMPRECISERR + no description available + 10 + 1 + read-write + + + IMPRECISERR_0 + no imprecise data bus error + 0 + + + IMPRECISERR_1 + a data bus error has occurred, but the return address in the stack frame is not related to the instruction that caused the error + 0x1 + + + + + UNSTKERR + no description available + 11 + 1 + read-write + + + UNSTKERR_0 + no unstacking fault + 0 + + + UNSTKERR_1 + unstack for an exception return has caused one or more BusFaults + 0x1 + + + + + STKERR + no description available + 12 + 1 + read-write + + + STKERR_0 + no stacking fault + 0 + + + STKERR_1 + stacking for an exception entry has caused one or more BusFaults + 0x1 + + + + + LSPERR + no description available + 13 + 1 + read-write + + + LSPERR_0 + No bus fault occurred during floating-point lazy state preservation + 0 + + + LSPERR_1 + A bus fault occurred during floating-point lazy state preservation + 0x1 + + + + + BFARVALID + no description available + 15 + 1 + read-write + + + BFARVALID_0 + value in BFAR is not a valid fault address + 0 + + + BFARVALID_1 + BFAR holds a valid fault address + 0x1 + + + + + UNDEFINSTR + no description available + 16 + 1 + read-write + + + UNDEFINSTR_0 + no undefined instruction UsageFault + 0 + + + UNDEFINSTR_1 + the processor has attempted to execute an undefined instruction + 0x1 + + + + + INVSTATE + no description available + 17 + 1 + read-write + + + INVSTATE_0 + no invalid state UsageFault + 0 + + + INVSTATE_1 + the processor has attempted to execute an instruction that makes illegal use of the EPSR + 0x1 + + + + + INVPC + no description available + 18 + 1 + read-write + + + INVPC_0 + no invalid PC load UsageFault + 0 + + + INVPC_1 + the processor has attempted an illegal load of EXC_RETURN to the PC + 0x1 + + + + + NOCP + no description available + 19 + 1 + read-write + + + NOCP_0 + no UsageFault caused by attempting to access a coprocessor + 0 + + + NOCP_1 + the processor has attempted to access a coprocessor + 0x1 + + + + + UNALIGNED + no description available + 24 + 1 + read-write + + + UNALIGNED_0 + no unaligned access fault, or unaligned access trapping not enabled + 0 + + + UNALIGNED_1 + the processor has made an unaligned memory access + 0x1 + + + + + DIVBYZERO + no description available + 25 + 1 + read-write + + + DIVBYZERO_0 + no divide by zero fault, or divide by zero trapping not enabled + 0 + + + DIVBYZERO_1 + the processor has executed an SDIV or UDIV instruction with a divisor of 0 + 0x1 + + + + + + + HFSR + HardFault Status register + 0xD2C + 32 + read-write + 0 + 0xFFFFFFFF + + + VECTTBL + no description available + 1 + 1 + read-write + + + VECTTBL_0 + no BusFault on vector table read + 0 + + + VECTTBL_1 + BusFault on vector table read + 0x1 + + + + + FORCED + no description available + 30 + 1 + read-write + + + FORCED_0 + no forced HardFault + 0 + + + FORCED_1 + forced HardFault + 0x1 + + + + + DEBUGEVT + no description available + 31 + 1 + read-write + + + + + DFSR + Debug Fault Status Register + 0xD30 + 32 + read-write + 0 + 0xFFFFFFFF + + + HALTED + no description available + 0 + 1 + read-write + + + HALTED_0 + No active halt request debug event + 0 + + + HALTED_1 + Halt request debug event active + 0x1 + + + + + BKPT + no description available + 1 + 1 + read-write + + + BKPT_0 + No current breakpoint debug event + 0 + + + BKPT_1 + At least one current breakpoint debug event + 0x1 + + + + + DWTTRAP + no description available + 2 + 1 + read-write + + + DWTTRAP_0 + No current debug events generated by the DWT + 0 + + + DWTTRAP_1 + At least one current debug event generated by the DWT + 0x1 + + + + + VCATCH + no description available + 3 + 1 + read-write + + + VCATCH_0 + No Vector catch triggered + 0 + + + VCATCH_1 + Vector catch triggered + 0x1 + + + + + EXTERNAL + no description available + 4 + 1 + read-write + + + EXTERNAL_0 + No EDBGRQ debug event + 0 + + + EXTERNAL_1 + EDBGRQ debug event + 0x1 + + + + + + + MMFAR + MemManage Address Register + 0xD34 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADDRESS + Address of MemManage fault location + 0 + 32 + read-write + + + + + BFAR + BusFault Address Register + 0xD38 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADDRESS + Address of the BusFault location + 0 + 32 + read-write + + + + + AFSR + Auxiliary Fault Status Register + 0xD3C + 32 + read-write + 0 + 0xFFFFFFFF + + + AUXFAULT + Latched version of the AUXFAULT inputs + 0 + 32 + read-write + + + + + + + SysTick + System timer + SysTick + SYST_ + 0xE000E010 + + 0 + 0x10 + registers + + + + CSR + SysTick Control and Status Register + 0 + 32 + read-write + 0x4 + 0xFFFFFFFF + + + ENABLE + no description available + 0 + 1 + read-write + + + ENABLE_0 + counter disabled + 0 + + + ENABLE_1 + counter enabled + 0x1 + + + + + TICKINT + no description available + 1 + 1 + read-write + + + TICKINT_0 + counting down to 0 does not assert the SysTick exception request + 0 + + + TICKINT_1 + counting down to 0 asserts the SysTick exception request + 0x1 + + + + + CLKSOURCE + no description available + 2 + 1 + read-write + + + CLKSOURCE_0 + external clock + 0 + + + CLKSOURCE_1 + processor clock + 0x1 + + + + + COUNTFLAG + no description available + 16 + 1 + read-write + + + + + RVR + SysTick Reload Value Register + 0x4 + 32 + read-write + 0 + 0xFFFFFFFF + + + RELOAD + Value to load into the SysTick Current Value Register when the counter reaches 0 + 0 + 24 + read-write + + + + + CVR + SysTick Current Value Register + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + CURRENT + Current value at the time the register is accessed + 0 + 24 + read-write + + + + + CALIB + SysTick Calibration Value Register + 0xC + 32 + read-only + 0x80000000 + 0xFFFFFFFF + + + TENMS + Reload value to use for 10ms timing + 0 + 24 + read-only + + + SKEW + no description available + 30 + 1 + read-only + + + SKEW_0 + 10ms calibration value is exact + 0 + + + SKEW_1 + 10ms calibration value is inexact, because of the clock frequency + 0x1 + + + + + NOREF + no description available + 31 + 1 + read-only + + + NOREF_0 + The reference clock is provided + 0 + + + NOREF_1 + The reference clock is not provided + 0x1 + + + + + + + + + NVIC + Nested Vectored Interrupt Controller + NVIC + 0xE000E100 + + 0 + 0xE04 + registers + + + + NVICISER0 + Interrupt Set Enable Register n + 0 + 32 + read-write + 0 + 0xFFFFFFFF + + + SETENA + Interrupt set enable bits + 0 + 32 + read-write + + + + + NVICISER1 + Interrupt Set Enable Register n + 0x4 + 32 + read-write + 0 + 0xFFFFFFFF + + + SETENA + Interrupt set enable bits + 0 + 32 + read-write + + + + + NVICISER2 + Interrupt Set Enable Register n + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + SETENA + Interrupt set enable bits + 0 + 32 + read-write + + + + + NVICISER3 + Interrupt Set Enable Register n + 0xC + 32 + read-write + 0 + 0xFFFFFFFF + + + SETENA + Interrupt set enable bits + 0 + 32 + read-write + + + + + NVICICER0 + Interrupt Clear Enable Register n + 0x80 + 32 + read-write + 0 + 0xFFFFFFFF + + + CLRENA + Interrupt clear-enable bits + 0 + 32 + read-write + + + + + NVICICER1 + Interrupt Clear Enable Register n + 0x84 + 32 + read-write + 0 + 0xFFFFFFFF + + + CLRENA + Interrupt clear-enable bits + 0 + 32 + read-write + + + + + NVICICER2 + Interrupt Clear Enable Register n + 0x88 + 32 + read-write + 0 + 0xFFFFFFFF + + + CLRENA + Interrupt clear-enable bits + 0 + 32 + read-write + + + + + NVICICER3 + Interrupt Clear Enable Register n + 0x8C + 32 + read-write + 0 + 0xFFFFFFFF + + + CLRENA + Interrupt clear-enable bits + 0 + 32 + read-write + + + + + NVICISPR0 + Interrupt Set Pending Register n + 0x100 + 32 + read-write + 0 + 0xFFFFFFFF + + + SETPEND + Interrupt set-pending bits + 0 + 32 + read-write + + + + + NVICISPR1 + Interrupt Set Pending Register n + 0x104 + 32 + read-write + 0 + 0xFFFFFFFF + + + SETPEND + Interrupt set-pending bits + 0 + 32 + read-write + + + + + NVICISPR2 + Interrupt Set Pending Register n + 0x108 + 32 + read-write + 0 + 0xFFFFFFFF + + + SETPEND + Interrupt set-pending bits + 0 + 32 + read-write + + + + + NVICISPR3 + Interrupt Set Pending Register n + 0x10C + 32 + read-write + 0 + 0xFFFFFFFF + + + SETPEND + Interrupt set-pending bits + 0 + 32 + read-write + + + + + NVICICPR0 + Interrupt Clear Pending Register n + 0x180 + 32 + read-write + 0 + 0xFFFFFFFF + + + CLRPEND + Interrupt clear-pending bits + 0 + 32 + read-write + + + + + NVICICPR1 + Interrupt Clear Pending Register n + 0x184 + 32 + read-write + 0 + 0xFFFFFFFF + + + CLRPEND + Interrupt clear-pending bits + 0 + 32 + read-write + + + + + NVICICPR2 + Interrupt Clear Pending Register n + 0x188 + 32 + read-write + 0 + 0xFFFFFFFF + + + CLRPEND + Interrupt clear-pending bits + 0 + 32 + read-write + + + + + NVICICPR3 + Interrupt Clear Pending Register n + 0x18C + 32 + read-write + 0 + 0xFFFFFFFF + + + CLRPEND + Interrupt clear-pending bits + 0 + 32 + read-write + + + + + NVICIABR0 + Interrupt Active bit Register n + 0x200 + 32 + read-write + 0 + 0xFFFFFFFF + + + ACTIVE + Interrupt active flags + 0 + 32 + read-write + + + + + NVICIABR1 + Interrupt Active bit Register n + 0x204 + 32 + read-write + 0 + 0xFFFFFFFF + + + ACTIVE + Interrupt active flags + 0 + 32 + read-write + + + + + NVICIABR2 + Interrupt Active bit Register n + 0x208 + 32 + read-write + 0 + 0xFFFFFFFF + + + ACTIVE + Interrupt active flags + 0 + 32 + read-write + + + + + NVICIABR3 + Interrupt Active bit Register n + 0x20C + 32 + read-write + 0 + 0xFFFFFFFF + + + ACTIVE + Interrupt active flags + 0 + 32 + read-write + + + + + NVICIP0 + Interrupt Priority Register n + 0x300 + 8 + read-write + 0 + 0xFF + + + PRI0 + Priority of interrupt 0 + 0 + 8 + read-write + + + + + NVICIP1 + Interrupt Priority Register n + 0x301 + 8 + read-write + 0 + 0xFF + + + PRI1 + Priority of interrupt 1 + 0 + 8 + read-write + + + + + NVICIP2 + Interrupt Priority Register n + 0x302 + 8 + read-write + 0 + 0xFF + + + PRI2 + Priority of interrupt 2 + 0 + 8 + read-write + + + + + NVICIP3 + Interrupt Priority Register n + 0x303 + 8 + read-write + 0 + 0xFF + + + PRI3 + Priority of interrupt 3 + 0 + 8 + read-write + + + + + NVICIP4 + Interrupt Priority Register n + 0x304 + 8 + read-write + 0 + 0xFF + + + PRI4 + Priority of interrupt 4 + 0 + 8 + read-write + + + + + NVICIP5 + Interrupt Priority Register n + 0x305 + 8 + read-write + 0 + 0xFF + + + PRI5 + Priority of interrupt 5 + 0 + 8 + read-write + + + + + NVICIP6 + Interrupt Priority Register n + 0x306 + 8 + read-write + 0 + 0xFF + + + PRI6 + Priority of interrupt 6 + 0 + 8 + read-write + + + + + NVICIP7 + Interrupt Priority Register n + 0x307 + 8 + read-write + 0 + 0xFF + + + PRI7 + Priority of interrupt 7 + 0 + 8 + read-write + + + + + NVICIP8 + Interrupt Priority Register n + 0x308 + 8 + read-write + 0 + 0xFF + + + PRI8 + Priority of interrupt 8 + 0 + 8 + read-write + + + + + NVICIP9 + Interrupt Priority Register n + 0x309 + 8 + read-write + 0 + 0xFF + + + PRI9 + Priority of interrupt 9 + 0 + 8 + read-write + + + + + NVICIP10 + Interrupt Priority Register n + 0x30A + 8 + read-write + 0 + 0xFF + + + PRI10 + Priority of interrupt 10 + 0 + 8 + read-write + + + + + NVICIP11 + Interrupt Priority Register n + 0x30B + 8 + read-write + 0 + 0xFF + + + PRI11 + Priority of interrupt 11 + 0 + 8 + read-write + + + + + NVICIP12 + Interrupt Priority Register n + 0x30C + 8 + read-write + 0 + 0xFF + + + PRI12 + Priority of interrupt 12 + 0 + 8 + read-write + + + + + NVICIP13 + Interrupt Priority Register n + 0x30D + 8 + read-write + 0 + 0xFF + + + PRI13 + Priority of interrupt 13 + 0 + 8 + read-write + + + + + NVICIP14 + Interrupt Priority Register n + 0x30E + 8 + read-write + 0 + 0xFF + + + PRI14 + Priority of interrupt 14 + 0 + 8 + read-write + + + + + NVICIP15 + Interrupt Priority Register n + 0x30F + 8 + read-write + 0 + 0xFF + + + PRI15 + Priority of interrupt 15 + 0 + 8 + read-write + + + + + NVICIP16 + Interrupt Priority Register n + 0x310 + 8 + read-write + 0 + 0xFF + + + PRI16 + Priority of interrupt 16 + 0 + 8 + read-write + + + + + NVICIP17 + Interrupt Priority Register n + 0x311 + 8 + read-write + 0 + 0xFF + + + PRI17 + Priority of interrupt 17 + 0 + 8 + read-write + + + + + NVICIP18 + Interrupt Priority Register n + 0x312 + 8 + read-write + 0 + 0xFF + + + PRI18 + Priority of interrupt 18 + 0 + 8 + read-write + + + + + NVICIP19 + Interrupt Priority Register n + 0x313 + 8 + read-write + 0 + 0xFF + + + PRI19 + Priority of interrupt 19 + 0 + 8 + read-write + + + + + NVICIP20 + Interrupt Priority Register n + 0x314 + 8 + read-write + 0 + 0xFF + + + PRI20 + Priority of interrupt 20 + 0 + 8 + read-write + + + + + NVICIP21 + Interrupt Priority Register n + 0x315 + 8 + read-write + 0 + 0xFF + + + PRI21 + Priority of interrupt 21 + 0 + 8 + read-write + + + + + NVICIP22 + Interrupt Priority Register n + 0x316 + 8 + read-write + 0 + 0xFF + + + PRI22 + Priority of interrupt 22 + 0 + 8 + read-write + + + + + NVICIP23 + Interrupt Priority Register n + 0x317 + 8 + read-write + 0 + 0xFF + + + PRI23 + Priority of interrupt 23 + 0 + 8 + read-write + + + + + NVICIP24 + Interrupt Priority Register n + 0x318 + 8 + read-write + 0 + 0xFF + + + PRI24 + Priority of interrupt 24 + 0 + 8 + read-write + + + + + NVICIP25 + Interrupt Priority Register n + 0x319 + 8 + read-write + 0 + 0xFF + + + PRI25 + Priority of interrupt 25 + 0 + 8 + read-write + + + + + NVICIP26 + Interrupt Priority Register n + 0x31A + 8 + read-write + 0 + 0xFF + + + PRI26 + Priority of interrupt 26 + 0 + 8 + read-write + + + + + NVICIP27 + Interrupt Priority Register n + 0x31B + 8 + read-write + 0 + 0xFF + + + PRI27 + Priority of interrupt 27 + 0 + 8 + read-write + + + + + NVICIP28 + Interrupt Priority Register n + 0x31C + 8 + read-write + 0 + 0xFF + + + PRI28 + Priority of interrupt 28 + 0 + 8 + read-write + + + + + NVICIP29 + Interrupt Priority Register n + 0x31D + 8 + read-write + 0 + 0xFF + + + PRI29 + Priority of interrupt 29 + 0 + 8 + read-write + + + + + NVICIP30 + Interrupt Priority Register n + 0x31E + 8 + read-write + 0 + 0xFF + + + PRI30 + Priority of interrupt 30 + 0 + 8 + read-write + + + + + NVICIP31 + Interrupt Priority Register n + 0x31F + 8 + read-write + 0 + 0xFF + + + PRI31 + Priority of interrupt 31 + 0 + 8 + read-write + + + + + NVICIP32 + Interrupt Priority Register n + 0x320 + 8 + read-write + 0 + 0xFF + + + PRI32 + Priority of interrupt 32 + 0 + 8 + read-write + + + + + NVICIP33 + Interrupt Priority Register n + 0x321 + 8 + read-write + 0 + 0xFF + + + PRI33 + Priority of interrupt 33 + 0 + 8 + read-write + + + + + NVICIP34 + Interrupt Priority Register n + 0x322 + 8 + read-write + 0 + 0xFF + + + PRI34 + Priority of interrupt 34 + 0 + 8 + read-write + + + + + NVICIP35 + Interrupt Priority Register n + 0x323 + 8 + read-write + 0 + 0xFF + + + PRI35 + Priority of interrupt 35 + 0 + 8 + read-write + + + + + NVICIP36 + Interrupt Priority Register n + 0x324 + 8 + read-write + 0 + 0xFF + + + PRI36 + Priority of interrupt 36 + 0 + 8 + read-write + + + + + NVICIP37 + Interrupt Priority Register n + 0x325 + 8 + read-write + 0 + 0xFF + + + PRI37 + Priority of interrupt 37 + 0 + 8 + read-write + + + + + NVICIP38 + Interrupt Priority Register n + 0x326 + 8 + read-write + 0 + 0xFF + + + PRI38 + Priority of interrupt 38 + 0 + 8 + read-write + + + + + NVICIP39 + Interrupt Priority Register n + 0x327 + 8 + read-write + 0 + 0xFF + + + PRI39 + Priority of interrupt 39 + 0 + 8 + read-write + + + + + NVICIP40 + Interrupt Priority Register n + 0x328 + 8 + read-write + 0 + 0xFF + + + PRI40 + Priority of interrupt 40 + 0 + 8 + read-write + + + + + NVICIP41 + Interrupt Priority Register n + 0x329 + 8 + read-write + 0 + 0xFF + + + PRI41 + Priority of interrupt 41 + 0 + 8 + read-write + + + + + NVICIP42 + Interrupt Priority Register n + 0x32A + 8 + read-write + 0 + 0xFF + + + PRI42 + Priority of interrupt 42 + 0 + 8 + read-write + + + + + NVICIP43 + Interrupt Priority Register n + 0x32B + 8 + read-write + 0 + 0xFF + + + PRI43 + Priority of interrupt 43 + 0 + 8 + read-write + + + + + NVICIP44 + Interrupt Priority Register n + 0x32C + 8 + read-write + 0 + 0xFF + + + PRI44 + Priority of interrupt 44 + 0 + 8 + read-write + + + + + NVICIP45 + Interrupt Priority Register n + 0x32D + 8 + read-write + 0 + 0xFF + + + PRI45 + Priority of interrupt 45 + 0 + 8 + read-write + + + + + NVICIP46 + Interrupt Priority Register n + 0x32E + 8 + read-write + 0 + 0xFF + + + PRI46 + Priority of interrupt 46 + 0 + 8 + read-write + + + + + NVICIP47 + Interrupt Priority Register n + 0x32F + 8 + read-write + 0 + 0xFF + + + PRI47 + Priority of interrupt 47 + 0 + 8 + read-write + + + + + NVICIP48 + Interrupt Priority Register n + 0x330 + 8 + read-write + 0 + 0xFF + + + PRI48 + Priority of interrupt 48 + 0 + 8 + read-write + + + + + NVICIP49 + Interrupt Priority Register n + 0x331 + 8 + read-write + 0 + 0xFF + + + PRI49 + Priority of interrupt 49 + 0 + 8 + read-write + + + + + NVICIP50 + Interrupt Priority Register n + 0x332 + 8 + read-write + 0 + 0xFF + + + PRI50 + Priority of interrupt 50 + 0 + 8 + read-write + + + + + NVICIP51 + Interrupt Priority Register n + 0x333 + 8 + read-write + 0 + 0xFF + + + PRI51 + Priority of interrupt 51 + 0 + 8 + read-write + + + + + NVICIP52 + Interrupt Priority Register n + 0x334 + 8 + read-write + 0 + 0xFF + + + PRI52 + Priority of interrupt 52 + 0 + 8 + read-write + + + + + NVICIP53 + Interrupt Priority Register n + 0x335 + 8 + read-write + 0 + 0xFF + + + PRI53 + Priority of interrupt 53 + 0 + 8 + read-write + + + + + NVICIP54 + Interrupt Priority Register n + 0x336 + 8 + read-write + 0 + 0xFF + + + PRI54 + Priority of interrupt 54 + 0 + 8 + read-write + + + + + NVICIP55 + Interrupt Priority Register n + 0x337 + 8 + read-write + 0 + 0xFF + + + PRI55 + Priority of interrupt 55 + 0 + 8 + read-write + + + + + NVICIP56 + Interrupt Priority Register n + 0x338 + 8 + read-write + 0 + 0xFF + + + PRI56 + Priority of interrupt 56 + 0 + 8 + read-write + + + + + NVICIP57 + Interrupt Priority Register n + 0x339 + 8 + read-write + 0 + 0xFF + + + PRI57 + Priority of interrupt 57 + 0 + 8 + read-write + + + + + NVICIP58 + Interrupt Priority Register n + 0x33A + 8 + read-write + 0 + 0xFF + + + PRI58 + Priority of interrupt 58 + 0 + 8 + read-write + + + + + NVICIP59 + Interrupt Priority Register n + 0x33B + 8 + read-write + 0 + 0xFF + + + PRI59 + Priority of interrupt 59 + 0 + 8 + read-write + + + + + NVICIP60 + Interrupt Priority Register n + 0x33C + 8 + read-write + 0 + 0xFF + + + PRI60 + Priority of interrupt 60 + 0 + 8 + read-write + + + + + NVICIP61 + Interrupt Priority Register n + 0x33D + 8 + read-write + 0 + 0xFF + + + PRI61 + Priority of interrupt 61 + 0 + 8 + read-write + + + + + NVICIP62 + Interrupt Priority Register n + 0x33E + 8 + read-write + 0 + 0xFF + + + PRI62 + Priority of interrupt 62 + 0 + 8 + read-write + + + + + NVICIP63 + Interrupt Priority Register n + 0x33F + 8 + read-write + 0 + 0xFF + + + PRI63 + Priority of interrupt 63 + 0 + 8 + read-write + + + + + NVICIP64 + Interrupt Priority Register n + 0x340 + 8 + read-write + 0 + 0xFF + + + PRI64 + Priority of interrupt 64 + 0 + 8 + read-write + + + + + NVICIP65 + Interrupt Priority Register n + 0x341 + 8 + read-write + 0 + 0xFF + + + PRI65 + Priority of interrupt 65 + 0 + 8 + read-write + + + + + NVICIP66 + Interrupt Priority Register n + 0x342 + 8 + read-write + 0 + 0xFF + + + PRI66 + Priority of interrupt 66 + 0 + 8 + read-write + + + + + NVICIP67 + Interrupt Priority Register n + 0x343 + 8 + read-write + 0 + 0xFF + + + PRI67 + Priority of interrupt 67 + 0 + 8 + read-write + + + + + NVICIP68 + Interrupt Priority Register n + 0x344 + 8 + read-write + 0 + 0xFF + + + PRI68 + Priority of interrupt 68 + 0 + 8 + read-write + + + + + NVICIP69 + Interrupt Priority Register n + 0x345 + 8 + read-write + 0 + 0xFF + + + PRI69 + Priority of interrupt 69 + 0 + 8 + read-write + + + + + NVICIP70 + Interrupt Priority Register n + 0x346 + 8 + read-write + 0 + 0xFF + + + PRI70 + Priority of interrupt 70 + 0 + 8 + read-write + + + + + NVICIP71 + Interrupt Priority Register n + 0x347 + 8 + read-write + 0 + 0xFF + + + PRI71 + Priority of interrupt 71 + 0 + 8 + read-write + + + + + NVICIP72 + Interrupt Priority Register n + 0x348 + 8 + read-write + 0 + 0xFF + + + PRI72 + Priority of interrupt 72 + 0 + 8 + read-write + + + + + NVICIP73 + Interrupt Priority Register n + 0x349 + 8 + read-write + 0 + 0xFF + + + PRI73 + Priority of interrupt 73 + 0 + 8 + read-write + + + + + NVICIP74 + Interrupt Priority Register n + 0x34A + 8 + read-write + 0 + 0xFF + + + PRI74 + Priority of interrupt 74 + 0 + 8 + read-write + + + + + NVICIP75 + Interrupt Priority Register n + 0x34B + 8 + read-write + 0 + 0xFF + + + PRI75 + Priority of interrupt 75 + 0 + 8 + read-write + + + + + NVICIP76 + Interrupt Priority Register n + 0x34C + 8 + read-write + 0 + 0xFF + + + PRI76 + Priority of interrupt 76 + 0 + 8 + read-write + + + + + NVICIP77 + Interrupt Priority Register n + 0x34D + 8 + read-write + 0 + 0xFF + + + PRI77 + Priority of interrupt 77 + 0 + 8 + read-write + + + + + NVICIP78 + Interrupt Priority Register n + 0x34E + 8 + read-write + 0 + 0xFF + + + PRI78 + Priority of interrupt 78 + 0 + 8 + read-write + + + + + NVICIP79 + Interrupt Priority Register n + 0x34F + 8 + read-write + 0 + 0xFF + + + PRI79 + Priority of interrupt 79 + 0 + 8 + read-write + + + + + NVICIP80 + Interrupt Priority Register n + 0x350 + 8 + read-write + 0 + 0xFF + + + PRI80 + Priority of interrupt 80 + 0 + 8 + read-write + + + + + NVICIP81 + Interrupt Priority Register n + 0x351 + 8 + read-write + 0 + 0xFF + + + PRI81 + Priority of interrupt 81 + 0 + 8 + read-write + + + + + NVICIP82 + Interrupt Priority Register n + 0x352 + 8 + read-write + 0 + 0xFF + + + PRI82 + Priority of interrupt 82 + 0 + 8 + read-write + + + + + NVICIP83 + Interrupt Priority Register n + 0x353 + 8 + read-write + 0 + 0xFF + + + PRI83 + Priority of interrupt 83 + 0 + 8 + read-write + + + + + NVICIP84 + Interrupt Priority Register n + 0x354 + 8 + read-write + 0 + 0xFF + + + PRI84 + Priority of interrupt 84 + 0 + 8 + read-write + + + + + NVICIP85 + Interrupt Priority Register n + 0x355 + 8 + read-write + 0 + 0xFF + + + PRI85 + Priority of interrupt 85 + 0 + 8 + read-write + + + + + NVICIP86 + Interrupt Priority Register n + 0x356 + 8 + read-write + 0 + 0xFF + + + PRI86 + Priority of interrupt 86 + 0 + 8 + read-write + + + + + NVICIP87 + Interrupt Priority Register n + 0x357 + 8 + read-write + 0 + 0xFF + + + PRI87 + Priority of interrupt 87 + 0 + 8 + read-write + + + + + NVICIP88 + Interrupt Priority Register n + 0x358 + 8 + read-write + 0 + 0xFF + + + PRI88 + Priority of interrupt 88 + 0 + 8 + read-write + + + + + NVICIP89 + Interrupt Priority Register n + 0x359 + 8 + read-write + 0 + 0xFF + + + PRI89 + Priority of interrupt 89 + 0 + 8 + read-write + + + + + NVICIP90 + Interrupt Priority Register n + 0x35A + 8 + read-write + 0 + 0xFF + + + PRI90 + Priority of interrupt 90 + 0 + 8 + read-write + + + + + NVICIP91 + Interrupt Priority Register n + 0x35B + 8 + read-write + 0 + 0xFF + + + PRI91 + Priority of interrupt 91 + 0 + 8 + read-write + + + + + NVICIP92 + Interrupt Priority Register n + 0x35C + 8 + read-write + 0 + 0xFF + + + PRI92 + Priority of interrupt 92 + 0 + 8 + read-write + + + + + NVICIP93 + Interrupt Priority Register n + 0x35D + 8 + read-write + 0 + 0xFF + + + PRI93 + Priority of interrupt 93 + 0 + 8 + read-write + + + + + NVICIP94 + Interrupt Priority Register n + 0x35E + 8 + read-write + 0 + 0xFF + + + PRI94 + Priority of interrupt 94 + 0 + 8 + read-write + + + + + NVICIP95 + Interrupt Priority Register n + 0x35F + 8 + read-write + 0 + 0xFF + + + PRI95 + Priority of interrupt 95 + 0 + 8 + read-write + + + + + NVICIP96 + Interrupt Priority Register n + 0x360 + 8 + read-write + 0 + 0xFF + + + PRI96 + Priority of interrupt 96 + 0 + 8 + read-write + + + + + NVICIP97 + Interrupt Priority Register n + 0x361 + 8 + read-write + 0 + 0xFF + + + PRI97 + Priority of interrupt 97 + 0 + 8 + read-write + + + + + NVICIP98 + Interrupt Priority Register n + 0x362 + 8 + read-write + 0 + 0xFF + + + PRI98 + Priority of interrupt 98 + 0 + 8 + read-write + + + + + NVICIP99 + Interrupt Priority Register n + 0x363 + 8 + read-write + 0 + 0xFF + + + PRI99 + Priority of interrupt 99 + 0 + 8 + read-write + + + + + NVICIP100 + Interrupt Priority Register n + 0x364 + 8 + read-write + 0 + 0xFF + + + PRI100 + Priority of interrupt 100 + 0 + 8 + read-write + + + + + NVICIP101 + Interrupt Priority Register n + 0x365 + 8 + read-write + 0 + 0xFF + + + PRI101 + Priority of interrupt 101 + 0 + 8 + read-write + + + + + NVICIP102 + Interrupt Priority Register n + 0x366 + 8 + read-write + 0 + 0xFF + + + PRI102 + Priority of interrupt 102 + 0 + 8 + read-write + + + + + NVICIP103 + Interrupt Priority Register n + 0x367 + 8 + read-write + 0 + 0xFF + + + PRI103 + Priority of interrupt 103 + 0 + 8 + read-write + + + + + NVICIP104 + Interrupt Priority Register n + 0x368 + 8 + read-write + 0 + 0xFF + + + PRI104 + Priority of interrupt 104 + 0 + 8 + read-write + + + + + NVICIP105 + Interrupt Priority Register n + 0x369 + 8 + read-write + 0 + 0xFF + + + PRI105 + Priority of interrupt 105 + 0 + 8 + read-write + + + + + NVICSTIR + Software Trigger Interrupt Register + 0xE00 + 32 + read-write + 0 + 0xFFFFFFFF + + + INTID + Interrupt ID of the interrupt to trigger, in the range 0-239. For example, a value of 0x03 specifies interrupt IRQ3. + 0 + 9 + read-write + + + + + \ No newline at end of file diff --git a/ext/hal/nxp/mcux/devices/LPC54114/LPC54114_cm0plus_features.h b/ext/hal/nxp/mcux/devices/LPC54114/LPC54114_cm0plus_features.h index 2905516ac47..4beeb79a2b9 100644 --- a/ext/hal/nxp/mcux/devices/LPC54114/LPC54114_cm0plus_features.h +++ b/ext/hal/nxp/mcux/devices/LPC54114/LPC54114_cm0plus_features.h @@ -1,37 +1,15 @@ /* ** ################################################################### ** Version: rev. 1.0, 2016-05-09 -** Build: b161227 +** Build: b180806 ** ** Abstract: ** Chip specific module features. ** -** Copyright (c) 2016 Freescale Semiconductor, Inc. -** Copyright 2016 - 2017 NXP -** Redistribution and use in source and binary forms, with or without modification, -** are permitted provided that the following conditions are met: +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2018 NXP ** -** o Redistributions of source code must retain the above copyright notice, this list -** of conditions and the following disclaimer. -** -** o Redistributions in binary form must reproduce the above copyright notice, this -** list of conditions and the following disclaimer in the documentation and/or -** other materials provided with the distribution. -** -** o Neither the name of the copyright holder nor the names of its -** contributors may be used to endorse or promote products derived from this -** software without specific prior written permission. -** -** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** SPDX-License-Identifier: BSD-3-Clause ** ** http: www.nxp.com ** mail: support@nxp.com @@ -54,6 +32,8 @@ #define FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT (1) /* @brief CRC availability on the SoC. */ #define FSL_FEATURE_SOC_CRC_COUNT (1) +/* @brief CTIMER availability on the SoC. */ +#define FSL_FEATURE_SOC_CTIMER_COUNT (5) /* @brief DMA availability on the SoC. */ #define FSL_FEATURE_SOC_DMA_COUNT (1) /* @brief DMIC availability on the SoC. */ @@ -88,8 +68,6 @@ #define FSL_FEATURE_SOC_SPIFI_COUNT (1) /* @brief SYSCON availability on the SoC. */ #define FSL_FEATURE_SOC_SYSCON_COUNT (1) -/* @brief CTIMER availability on the SoC. */ -#define FSL_FEATURE_SOC_CTIMER_COUNT (5) /* @brief USART availability on the SoC. */ #define FSL_FEATURE_SOC_USART_COUNT (8) /* @brief USB availability on the SoC. */ @@ -99,16 +77,118 @@ /* @brief WWDT availability on the SoC. */ #define FSL_FEATURE_SOC_WWDT_COUNT (1) +/* ADC module features */ + +/* @brief Do not has input select (register INSEL). */ +#define FSL_FEATURE_ADC_HAS_NO_INSEL (0) +/* @brief Has ASYNMODE bitfile in CTRL reigster. */ +#define FSL_FEATURE_ADC_HAS_CTRL_ASYNMODE (1) +/* @brief Has ASYNMODE bitfile in CTRL reigster. */ +#define FSL_FEATURE_ADC_HAS_CTRL_RESOL (1) +/* @brief Has ASYNMODE bitfile in CTRL reigster. */ +#define FSL_FEATURE_ADC_HAS_CTRL_BYPASSCAL (1) +/* @brief Has ASYNMODE bitfile in CTRL reigster. */ +#define FSL_FEATURE_ADC_HAS_CTRL_TSAMP (1) +/* @brief Has ASYNMODE bitfile in CTRL reigster. */ +#define FSL_FEATURE_ADC_HAS_CTRL_LPWRMODE (0) +/* @brief Has ASYNMODE bitfile in CTRL reigster. */ +#define FSL_FEATURE_ADC_HAS_CTRL_CALMODE (0) +/* @brief Has startup register. */ +#define FSL_FEATURE_ADC_HAS_STARTUP_REG (1) +/* @brief Has ADTrim register */ +#define FSL_FEATURE_ADC_HAS_TRIM_REG (0) +/* @brief Has Calibration register. */ +#define FSL_FEATURE_ADC_HAS_CALIB_REG (1) + /* DMA module features */ /* @brief Number of channels */ #define FSL_FEATURE_DMA_NUMBER_OF_CHANNELS (20) +/* FLEXCOMM module features */ + +/* @brief FLEXCOMM0 USART INDEX 0 */ +#define FSL_FEATURE_FLEXCOMM0_USART_INDEX (0) +/* @brief FLEXCOMM0 SPI INDEX 0 */ +#define FSL_FEATURE_FLEXCOMM0_SPI_INDEX (0) +/* @brief FLEXCOMM0 I2C INDEX 0 */ +#define FSL_FEATURE_FLEXCOMM0_I2C_INDEX (0) +/* @brief FLEXCOMM1 USART INDEX 1 */ +#define FSL_FEATURE_FLEXCOMM1_USART_INDEX (1) +/* @brief FLEXCOMM1 SPI INDEX 1 */ +#define FSL_FEATURE_FLEXCOMM1_SPI_INDEX (1) +/* @brief FLEXCOMM1 I2C INDEX 1 */ +#define FSL_FEATURE_FLEXCOMM1_I2C_INDEX (1) +/* @brief FLEXCOMM2 USART INDEX 2 */ +#define FSL_FEATURE_FLEXCOMM2_USART_INDEX (2) +/* @brief FLEXCOMM2 SPI INDEX 2 */ +#define FSL_FEATURE_FLEXCOMM2_SPI_INDEX (2) +/* @brief FLEXCOMM2 I2C INDEX 2 */ +#define FSL_FEATURE_FLEXCOMM2_I2C_INDEX (2) +/* @brief FLEXCOMM3 USART INDEX 3 */ +#define FSL_FEATURE_FLEXCOMM3_USART_INDEX (3) +/* @brief FLEXCOMM3 SPI INDEX 3 */ +#define FSL_FEATURE_FLEXCOMM3_SPI_INDEX (3) +/* @brief FLEXCOMM3 I2C INDEX 3 */ +#define FSL_FEATURE_FLEXCOMM3_I2C_INDEX (3) +/* @brief FLEXCOMM4 USART INDEX 4 */ +#define FSL_FEATURE_FLEXCOMM4_USART_INDEX (4) +/* @brief FLEXCOMM4 SPI INDEX 4 */ +#define FSL_FEATURE_FLEXCOMM4_SPI_INDEX (4) +/* @brief FLEXCOMM4 I2C INDEX 4 */ +#define FSL_FEATURE_FLEXCOMM4_I2C_INDEX (4) +/* @brief FLEXCOMM5 USART INDEX 5 */ +#define FSL_FEATURE_FLEXCOMM5_USART_INDEX (5) +/* @brief FLEXCOMM5 SPI INDEX 5 */ +#define FSL_FEATURE_FLEXCOMM5_SPI_INDEX (5) +/* @brief FLEXCOMM5 I2C INDEX 5 */ +#define FSL_FEATURE_FLEXCOMM5_I2C_INDEX (5) +/* @brief FLEXCOMM6 USART INDEX 6 */ +#define FSL_FEATURE_FLEXCOMM6_USART_INDEX (6) +/* @brief FLEXCOMM6 SPI INDEX 6 */ +#define FSL_FEATURE_FLEXCOMM6_SPI_INDEX (6) +/* @brief FLEXCOMM6 I2C INDEX 6 */ +#define FSL_FEATURE_FLEXCOMM6_I2C_INDEX (6) +/* @brief FLEXCOMM7 I2S INDEX 0 */ +#define FSL_FEATURE_FLEXCOMM6_I2S_INDEX (0) +/* @brief FLEXCOMM7 USART INDEX 7 */ +#define FSL_FEATURE_FLEXCOMM7_USART_INDEX (7) +/* @brief FLEXCOMM7 SPI INDEX 7 */ +#define FSL_FEATURE_FLEXCOMM7_SPI_INDEX (7) +/* @brief FLEXCOMM7 I2C INDEX 7 */ +#define FSL_FEATURE_FLEXCOMM7_I2C_INDEX (7) +/* @brief FLEXCOMM7 I2S INDEX 1 */ +#define FSL_FEATURE_FLEXCOMM7_I2S_INDEX (1) + +/* MAILBOX module features */ + +/* @brief Mailbox side for current core */ +#define FSL_FEATURE_MAILBOX_SIDE_B (1) +/* @brief Mailbox has no reset control */ +#define FSL_FEATURE_MAILBOX_HAS_NO_RESET (1) + +/* MRT module features */ + +/* @brief number of channels. */ +#define FSL_FEATURE_MRT_NUMBER_OF_CHANNELS (4) + +/* interrupt module features */ + +/* @brief Lowest interrupt request number. */ +#define FSL_FEATURE_INTERRUPT_IRQ_MIN (-14) +/* @brief Highest interrupt request number. */ +#define FSL_FEATURE_INTERRUPT_IRQ_MAX (105) + /* PINT module features */ /* @brief Number of connected outputs */ #define FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS (4) +/* RTC module features */ + +/* @brief RTC has no reset control */ +#define FSL_FEATURE_RTC_HAS_NO_RESET (1) + /* SCT module features */ /* @brief Number of events */ @@ -117,6 +197,8 @@ #define FSL_FEATURE_SCT_NUMBER_OF_STATES (10) /* @brief Number of match capture */ #define FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE (10) +/* @brief Number of outputs */ +#define FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS (8) /* SYSCON module features */ @@ -128,6 +210,24 @@ #define FSL_FEATURE_SYSCON_FLASH_SECTOR_SIZE_BYTES (32768) /* @brief Flash size in bytes */ #define FSL_FEATURE_SYSCON_FLASH_SIZE_BYTES (262144) +/* @brief IAP has Flash read & write function */ +#define FSL_FEATURE_IAP_HAS_FLASH_FUNCTION (1) +/* @brief IAP has read Flash signature function */ +#define FSL_FEATURE_IAP_HAS_FLASH_SIGNATURE_READ (1) +/* @brief IAP has read extended Flash signature function */ +#define FSL_FEATURE_IAP_HAS_FLASH_EXTENDED_SIGNATURE_READ (0) + +/* SysTick module features */ + +/* @brief Systick has external reference clock. */ +#define FSL_FEATURE_SYSTICK_HAS_EXT_REF (0) +/* @brief Systick external reference clock is core clock divided by this value. */ +#define FSL_FEATURE_SYSTICK_EXT_REF_CORE_DIV (0) + +/* USB module features */ + +/* @brief Number of the endpoint in USB FS */ +#define FSL_FEATURE_USB_EP_NUM (5) #endif /* _LPC54114_cm0plus_FEATURES_H_ */ diff --git a/ext/hal/nxp/mcux/devices/LPC54114/LPC54114_cm4.h b/ext/hal/nxp/mcux/devices/LPC54114/LPC54114_cm4.h index 45bfce6a1f7..1b85b03ec89 100644 --- a/ext/hal/nxp/mcux/devices/LPC54114/LPC54114_cm4.h +++ b/ext/hal/nxp/mcux/devices/LPC54114/LPC54114_cm4.h @@ -10,37 +10,15 @@ ** ** Reference manual: LPC5411x User manual Rev. 1.1 25 May 2016 ** Version: rev. 1.0, 2016-04-29 -** Build: b161227 +** Build: b180802 ** ** Abstract: ** CMSIS Peripheral Access Layer for LPC54114_cm4 ** -** Copyright (c) 1997 - 2016 Freescale Semiconductor, Inc. -** Copyright 2016 - 2017 NXP -** Redistribution and use in source and binary forms, with or without modification, -** are permitted provided that the following conditions are met: +** Copyright 1997-2016 Freescale Semiconductor, Inc. +** Copyright 2016-2018 NXP ** -** o Redistributions of source code must retain the above copyright notice, this list -** of conditions and the following disclaimer. -** -** o Redistributions in binary form must reproduce the above copyright notice, this -** list of conditions and the following disclaimer in the documentation and/or -** other materials provided with the distribution. -** -** o Neither the name of the copyright holder nor the names of its -** contributors may be used to endorse or promote products derived from this -** software without specific prior written permission. -** -** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** SPDX-License-Identifier: BSD-3-Clause ** ** http: www.nxp.com ** mail: support@nxp.com @@ -178,6 +156,48 @@ typedef enum IRQn { */ /** Mapping Information */ +/*! + * @addtogroup dma_request + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! + * @brief Structure for the DMA hardware request + * + * Defines the structure for the DMA hardware request collections. The user can configure the + * hardware request to trigger the DMA transfer accordingly. The index + * of the hardware request varies according to the to SoC. + */ +typedef enum _dma_request_source +{ + kDmaRequestFlexcomm0Rx = 0U, /**< Flexcomm Interface 0 RX/I2C Slave */ + kDmaRequestFlexcomm0Tx = 1U, /**< Flexcomm Interface 0 TX/I2C Master */ + kDmaRequestFlexcomm1Rx = 2U, /**< Flexcomm Interface 1 RX/I2C Slave */ + kDmaRequestFlexcomm1Tx = 3U, /**< Flexcomm Interface 1 TX/I2C Master */ + kDmaRequestFlexcomm2Rx = 4U, /**< Flexcomm Interface 2 RX/I2C Slave */ + kDmaRequestFlexcomm2Tx = 5U, /**< Flexcomm Interface 2 TX/I2C Master */ + kDmaRequestFlexcomm3Rx = 6U, /**< Flexcomm Interface 3 RX/I2C Slave */ + kDmaRequestFlexcomm3Tx = 7U, /**< Flexcomm Interface 3 TX/I2C Master */ + kDmaRequestFlexcomm4Rx = 8U, /**< Flexcomm Interface 4 RX/I2C Slave */ + kDmaRequestFlexcomm4Tx = 9U, /**< Flexcomm Interface 4 TX/I2C Master */ + kDmaRequestFlexcomm5Rx = 10U, /**< Flexcomm Interface 5 RX/I2C Slave */ + kDmaRequestFlexcomm5Tx = 11U, /**< Flexcomm Interface 5 TX/I2C Master */ + kDmaRequestFlexcomm6Rx = 12U, /**< Flexcomm Interface 6 RX/I2C Slave */ + kDmaRequestFlexcomm6Tx = 13U, /**< Flexcomm Interface 6 TX/I2C Master */ + kDmaRequestFlexcomm7Rx = 14U, /**< Flexcomm Interface 7 RX/I2C Slave */ + kDmaRequestFlexcomm7Tx = 15U, /**< Flexcomm Interface 7 TX/I2C Master */ + kDmaRequestDMIC0 = 16U, /**< Digital microphone interface 0 */ + kDmaRequestDMIC1 = 17U, /**< Digital microphone interface 1 */ + kDmaRequestNoDMARequest18 = 18U, /**< No DMA request 18 */ + kDmaRequestNoDMARequest19 = 19U, /**< No DMA request 19 */ +} dma_request_source_t; + +/* @} */ + /*! * @} @@ -199,8 +219,12 @@ typedef enum IRQn { */ #if defined(__ARMCC_VERSION) - #pragma push - #pragma anon_unions + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #else + #pragma push + #pragma anon_unions + #endif #elif defined(__GNUC__) /* anonymous unions are enabled by default */ #elif defined(__IAR_SYSTEMS_ICC__) @@ -247,6 +271,7 @@ typedef struct { */ /*! @name CTRL - ADC Control register. Contains the clock divide value, resolution selection, sampling time selection, and mode controls. */ +/*! @{ */ #define ADC_CTRL_CLKDIV_MASK (0xFFU) #define ADC_CTRL_CLKDIV_SHIFT (0U) #define ADC_CTRL_CLKDIV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_CLKDIV_SHIFT)) & ADC_CTRL_CLKDIV_MASK) @@ -262,13 +287,17 @@ typedef struct { #define ADC_CTRL_TSAMP_MASK (0x7000U) #define ADC_CTRL_TSAMP_SHIFT (12U) #define ADC_CTRL_TSAMP(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_TSAMP_SHIFT)) & ADC_CTRL_TSAMP_MASK) +/*! @} */ /*! @name INSEL - Input Select. Allows selection of the temperature sensor as an alternate input to ADC channel 0. */ +/*! @{ */ #define ADC_INSEL_SEL_MASK (0x3U) #define ADC_INSEL_SEL_SHIFT (0U) #define ADC_INSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_INSEL_SEL_SHIFT)) & ADC_INSEL_SEL_MASK) +/*! @} */ /*! @name SEQ_CTRL - ADC Conversion Sequence-n control register: Controls triggering and channel selection for conversion sequence-n. Also specifies interrupt mode for sequence-n. */ +/*! @{ */ #define ADC_SEQ_CTRL_CHANNELS_MASK (0xFFFU) #define ADC_SEQ_CTRL_CHANNELS_SHIFT (0U) #define ADC_SEQ_CTRL_CHANNELS(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_CHANNELS_SHIFT)) & ADC_SEQ_CTRL_CHANNELS_MASK) @@ -299,11 +328,13 @@ typedef struct { #define ADC_SEQ_CTRL_SEQ_ENA_MASK (0x80000000U) #define ADC_SEQ_CTRL_SEQ_ENA_SHIFT (31U) #define ADC_SEQ_CTRL_SEQ_ENA(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_SEQ_ENA_SHIFT)) & ADC_SEQ_CTRL_SEQ_ENA_MASK) +/*! @} */ /* The count of ADC_SEQ_CTRL */ #define ADC_SEQ_CTRL_COUNT (2U) /*! @name SEQ_GDAT - ADC Sequence-n Global Data register. This register contains the result of the most recent ADC conversion performed under sequence-n. */ +/*! @{ */ #define ADC_SEQ_GDAT_RESULT_MASK (0xFFF0U) #define ADC_SEQ_GDAT_RESULT_SHIFT (4U) #define ADC_SEQ_GDAT_RESULT(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_RESULT_SHIFT)) & ADC_SEQ_GDAT_RESULT_MASK) @@ -322,11 +353,13 @@ typedef struct { #define ADC_SEQ_GDAT_DATAVALID_MASK (0x80000000U) #define ADC_SEQ_GDAT_DATAVALID_SHIFT (31U) #define ADC_SEQ_GDAT_DATAVALID(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_DATAVALID_SHIFT)) & ADC_SEQ_GDAT_DATAVALID_MASK) +/*! @} */ /* The count of ADC_SEQ_GDAT */ #define ADC_SEQ_GDAT_COUNT (2U) /*! @name DAT - ADC Channel 0 Data register. This register contains the result of the most recent conversion completed on channel 0. */ +/*! @{ */ #define ADC_DAT_RESULT_MASK (0xFFF0U) #define ADC_DAT_RESULT_SHIFT (4U) #define ADC_DAT_RESULT(x) (((uint32_t)(((uint32_t)(x)) << ADC_DAT_RESULT_SHIFT)) & ADC_DAT_RESULT_MASK) @@ -345,31 +378,41 @@ typedef struct { #define ADC_DAT_DATAVALID_MASK (0x80000000U) #define ADC_DAT_DATAVALID_SHIFT (31U) #define ADC_DAT_DATAVALID(x) (((uint32_t)(((uint32_t)(x)) << ADC_DAT_DATAVALID_SHIFT)) & ADC_DAT_DATAVALID_MASK) +/*! @} */ /* The count of ADC_DAT */ #define ADC_DAT_COUNT (12U) /*! @name THR0_LOW - ADC Low Compare Threshold register 0: Contains the lower threshold level for automatic threshold comparison for any channels linked to threshold pair 0. */ +/*! @{ */ #define ADC_THR0_LOW_THRLOW_MASK (0xFFF0U) #define ADC_THR0_LOW_THRLOW_SHIFT (4U) #define ADC_THR0_LOW_THRLOW(x) (((uint32_t)(((uint32_t)(x)) << ADC_THR0_LOW_THRLOW_SHIFT)) & ADC_THR0_LOW_THRLOW_MASK) +/*! @} */ /*! @name THR1_LOW - ADC Low Compare Threshold register 1: Contains the lower threshold level for automatic threshold comparison for any channels linked to threshold pair 1. */ +/*! @{ */ #define ADC_THR1_LOW_THRLOW_MASK (0xFFF0U) #define ADC_THR1_LOW_THRLOW_SHIFT (4U) #define ADC_THR1_LOW_THRLOW(x) (((uint32_t)(((uint32_t)(x)) << ADC_THR1_LOW_THRLOW_SHIFT)) & ADC_THR1_LOW_THRLOW_MASK) +/*! @} */ /*! @name THR0_HIGH - ADC High Compare Threshold register 0: Contains the upper threshold level for automatic threshold comparison for any channels linked to threshold pair 0. */ +/*! @{ */ #define ADC_THR0_HIGH_THRHIGH_MASK (0xFFF0U) #define ADC_THR0_HIGH_THRHIGH_SHIFT (4U) #define ADC_THR0_HIGH_THRHIGH(x) (((uint32_t)(((uint32_t)(x)) << ADC_THR0_HIGH_THRHIGH_SHIFT)) & ADC_THR0_HIGH_THRHIGH_MASK) +/*! @} */ /*! @name THR1_HIGH - ADC High Compare Threshold register 1: Contains the upper threshold level for automatic threshold comparison for any channels linked to threshold pair 1. */ +/*! @{ */ #define ADC_THR1_HIGH_THRHIGH_MASK (0xFFF0U) #define ADC_THR1_HIGH_THRHIGH_SHIFT (4U) #define ADC_THR1_HIGH_THRHIGH(x) (((uint32_t)(((uint32_t)(x)) << ADC_THR1_HIGH_THRHIGH_SHIFT)) & ADC_THR1_HIGH_THRHIGH_MASK) +/*! @} */ /*! @name CHAN_THRSEL - ADC Channel-Threshold Select register. Specifies which set of threshold compare registers are to be used for each channel */ +/*! @{ */ #define ADC_CHAN_THRSEL_CH0_THRSEL_MASK (0x1U) #define ADC_CHAN_THRSEL_CH0_THRSEL_SHIFT (0U) #define ADC_CHAN_THRSEL_CH0_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH0_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH0_THRSEL_MASK) @@ -406,8 +449,10 @@ typedef struct { #define ADC_CHAN_THRSEL_CH11_THRSEL_MASK (0x800U) #define ADC_CHAN_THRSEL_CH11_THRSEL_SHIFT (11U) #define ADC_CHAN_THRSEL_CH11_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH11_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH11_THRSEL_MASK) +/*! @} */ /*! @name INTEN - ADC Interrupt Enable register. This register contains enable bits that enable the sequence-A, sequence-B, threshold compare and data overrun interrupts to be generated. */ +/*! @{ */ #define ADC_INTEN_SEQA_INTEN_MASK (0x1U) #define ADC_INTEN_SEQA_INTEN_SHIFT (0U) #define ADC_INTEN_SEQA_INTEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_SEQA_INTEN_SHIFT)) & ADC_INTEN_SEQA_INTEN_MASK) @@ -453,8 +498,10 @@ typedef struct { #define ADC_INTEN_ADCMPINTEN11_MASK (0x6000000U) #define ADC_INTEN_ADCMPINTEN11_SHIFT (25U) #define ADC_INTEN_ADCMPINTEN11(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN11_SHIFT)) & ADC_INTEN_ADCMPINTEN11_MASK) +/*! @} */ /*! @name FLAGS - ADC Flags register. Contains the four interrupt/DMA trigger flags and the individual component overrun and threshold-compare flags. (The overrun bits replicate information stored in the result registers). */ +/*! @{ */ #define ADC_FLAGS_THCMP0_MASK (0x1U) #define ADC_FLAGS_THCMP0_SHIFT (0U) #define ADC_FLAGS_THCMP0(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP0_SHIFT)) & ADC_FLAGS_THCMP0_MASK) @@ -545,16 +592,20 @@ typedef struct { #define ADC_FLAGS_OVR_INT_MASK (0x80000000U) #define ADC_FLAGS_OVR_INT_SHIFT (31U) #define ADC_FLAGS_OVR_INT(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVR_INT_SHIFT)) & ADC_FLAGS_OVR_INT_MASK) +/*! @} */ /*! @name STARTUP - ADC Startup register. */ +/*! @{ */ #define ADC_STARTUP_ADC_ENA_MASK (0x1U) #define ADC_STARTUP_ADC_ENA_SHIFT (0U) #define ADC_STARTUP_ADC_ENA(x) (((uint32_t)(((uint32_t)(x)) << ADC_STARTUP_ADC_ENA_SHIFT)) & ADC_STARTUP_ADC_ENA_MASK) #define ADC_STARTUP_ADC_INIT_MASK (0x2U) #define ADC_STARTUP_ADC_INIT_SHIFT (1U) #define ADC_STARTUP_ADC_INIT(x) (((uint32_t)(((uint32_t)(x)) << ADC_STARTUP_ADC_INIT_SHIFT)) & ADC_STARTUP_ADC_INIT_MASK) +/*! @} */ /*! @name CALIB - ADC Calibration register. */ +/*! @{ */ #define ADC_CALIB_CALIB_MASK (0x1U) #define ADC_CALIB_CALIB_SHIFT (0U) #define ADC_CALIB_CALIB(x) (((uint32_t)(((uint32_t)(x)) << ADC_CALIB_CALIB_SHIFT)) & ADC_CALIB_CALIB_MASK) @@ -564,6 +615,7 @@ typedef struct { #define ADC_CALIB_CALVALUE_MASK (0x1FCU) #define ADC_CALIB_CALVALUE_SHIFT (2U) #define ADC_CALIB_CALVALUE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CALIB_CALVALUE_SHIFT)) & ADC_CALIB_CALVALUE_MASK) +/*! @} */ /*! @@ -621,45 +673,59 @@ typedef struct { */ /*! @name ASYNCPRESETCTRL - Async peripheral reset control */ +/*! @{ */ #define ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER3_MASK (0x2000U) #define ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER3_SHIFT (13U) #define ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER3(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER3_SHIFT)) & ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER3_MASK) #define ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER4_MASK (0x4000U) #define ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER4_SHIFT (14U) #define ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER4(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER4_SHIFT)) & ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER4_MASK) +/*! @} */ /*! @name ASYNCPRESETCTRLSET - Set bits in ASYNCPRESETCTRL */ +/*! @{ */ #define ASYNC_SYSCON_ASYNCPRESETCTRLSET_ARST_SET_MASK (0xFFFFFFFFU) #define ASYNC_SYSCON_ASYNCPRESETCTRLSET_ARST_SET_SHIFT (0U) #define ASYNC_SYSCON_ASYNCPRESETCTRLSET_ARST_SET(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCPRESETCTRLSET_ARST_SET_SHIFT)) & ASYNC_SYSCON_ASYNCPRESETCTRLSET_ARST_SET_MASK) +/*! @} */ /*! @name ASYNCPRESETCTRLCLR - Clear bits in ASYNCPRESETCTRL */ +/*! @{ */ #define ASYNC_SYSCON_ASYNCPRESETCTRLCLR_ARST_CLR_MASK (0xFFFFFFFFU) #define ASYNC_SYSCON_ASYNCPRESETCTRLCLR_ARST_CLR_SHIFT (0U) #define ASYNC_SYSCON_ASYNCPRESETCTRLCLR_ARST_CLR(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCPRESETCTRLCLR_ARST_CLR_SHIFT)) & ASYNC_SYSCON_ASYNCPRESETCTRLCLR_ARST_CLR_MASK) +/*! @} */ /*! @name ASYNCAPBCLKCTRL - Async peripheral clock control */ +/*! @{ */ #define ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER3_MASK (0x2000U) #define ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER3_SHIFT (13U) #define ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER3(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER3_SHIFT)) & ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER3_MASK) #define ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER4_MASK (0x4000U) #define ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER4_SHIFT (14U) #define ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER4(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER4_SHIFT)) & ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER4_MASK) +/*! @} */ /*! @name ASYNCAPBCLKCTRLSET - Set bits in ASYNCAPBCLKCTRL */ +/*! @{ */ #define ASYNC_SYSCON_ASYNCAPBCLKCTRLSET_ACLK_SET_MASK (0xFFFFFFFFU) #define ASYNC_SYSCON_ASYNCAPBCLKCTRLSET_ACLK_SET_SHIFT (0U) #define ASYNC_SYSCON_ASYNCAPBCLKCTRLSET_ACLK_SET(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCAPBCLKCTRLSET_ACLK_SET_SHIFT)) & ASYNC_SYSCON_ASYNCAPBCLKCTRLSET_ACLK_SET_MASK) +/*! @} */ /*! @name ASYNCAPBCLKCTRLCLR - Clear bits in ASYNCAPBCLKCTRL */ +/*! @{ */ #define ASYNC_SYSCON_ASYNCAPBCLKCTRLCLR_ACLK_CLR_MASK (0xFFFFFFFFU) #define ASYNC_SYSCON_ASYNCAPBCLKCTRLCLR_ACLK_CLR_SHIFT (0U) #define ASYNC_SYSCON_ASYNCAPBCLKCTRLCLR_ACLK_CLR(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCAPBCLKCTRLCLR_ACLK_CLR_SHIFT)) & ASYNC_SYSCON_ASYNCAPBCLKCTRLCLR_ACLK_CLR_MASK) +/*! @} */ /*! @name ASYNCAPBCLKSELA - Async APB clock source select A */ +/*! @{ */ #define ASYNC_SYSCON_ASYNCAPBCLKSELA_SEL_MASK (0x3U) #define ASYNC_SYSCON_ASYNCAPBCLKSELA_SEL_SHIFT (0U) #define ASYNC_SYSCON_ASYNCAPBCLKSELA_SEL(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCAPBCLKSELA_SEL_SHIFT)) & ASYNC_SYSCON_ASYNCAPBCLKSELA_SEL_MASK) +/*! @} */ /*! @@ -711,6 +777,7 @@ typedef struct { */ /*! @name MODE - CRC mode register */ +/*! @{ */ #define CRC_MODE_CRC_POLY_MASK (0x3U) #define CRC_MODE_CRC_POLY_SHIFT (0U) #define CRC_MODE_CRC_POLY(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_CRC_POLY_SHIFT)) & CRC_MODE_CRC_POLY_MASK) @@ -726,21 +793,28 @@ typedef struct { #define CRC_MODE_CMPL_SUM_MASK (0x20U) #define CRC_MODE_CMPL_SUM_SHIFT (5U) #define CRC_MODE_CMPL_SUM(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_CMPL_SUM_SHIFT)) & CRC_MODE_CMPL_SUM_MASK) +/*! @} */ /*! @name SEED - CRC seed register */ +/*! @{ */ #define CRC_SEED_CRC_SEED_MASK (0xFFFFFFFFU) #define CRC_SEED_CRC_SEED_SHIFT (0U) #define CRC_SEED_CRC_SEED(x) (((uint32_t)(((uint32_t)(x)) << CRC_SEED_CRC_SEED_SHIFT)) & CRC_SEED_CRC_SEED_MASK) +/*! @} */ /*! @name SUM - CRC checksum register */ +/*! @{ */ #define CRC_SUM_CRC_SUM_MASK (0xFFFFFFFFU) #define CRC_SUM_CRC_SUM_SHIFT (0U) #define CRC_SUM_CRC_SUM(x) (((uint32_t)(((uint32_t)(x)) << CRC_SUM_CRC_SUM_SHIFT)) & CRC_SUM_CRC_SUM_MASK) +/*! @} */ /*! @name WR_DATA - CRC data register */ +/*! @{ */ #define CRC_WR_DATA_CRC_WR_DATA_MASK (0xFFFFFFFFU) #define CRC_WR_DATA_CRC_WR_DATA_SHIFT (0U) #define CRC_WR_DATA_CRC_WR_DATA(x) (((uint32_t)(((uint32_t)(x)) << CRC_WR_DATA_CRC_WR_DATA_SHIFT)) & CRC_WR_DATA_CRC_WR_DATA_MASK) +/*! @} */ /*! @@ -799,6 +873,7 @@ typedef struct { */ /*! @name IR - Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. */ +/*! @{ */ #define CTIMER_IR_MR0INT_MASK (0x1U) #define CTIMER_IR_MR0INT_SHIFT (0U) #define CTIMER_IR_MR0INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR0INT_SHIFT)) & CTIMER_IR_MR0INT_MASK) @@ -823,31 +898,41 @@ typedef struct { #define CTIMER_IR_CR3INT_MASK (0x80U) #define CTIMER_IR_CR3INT_SHIFT (7U) #define CTIMER_IR_CR3INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR3INT_SHIFT)) & CTIMER_IR_CR3INT_MASK) +/*! @} */ /*! @name TCR - Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. */ +/*! @{ */ #define CTIMER_TCR_CEN_MASK (0x1U) #define CTIMER_TCR_CEN_SHIFT (0U) #define CTIMER_TCR_CEN(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_TCR_CEN_SHIFT)) & CTIMER_TCR_CEN_MASK) #define CTIMER_TCR_CRST_MASK (0x2U) #define CTIMER_TCR_CRST_SHIFT (1U) #define CTIMER_TCR_CRST(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_TCR_CRST_SHIFT)) & CTIMER_TCR_CRST_MASK) +/*! @} */ /*! @name TC - Timer Counter. The 32 bit TC is incremented every PR+1 cycles of the APB bus clock. The TC is controlled through the TCR. */ +/*! @{ */ #define CTIMER_TC_TCVAL_MASK (0xFFFFFFFFU) #define CTIMER_TC_TCVAL_SHIFT (0U) #define CTIMER_TC_TCVAL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_TC_TCVAL_SHIFT)) & CTIMER_TC_TCVAL_MASK) +/*! @} */ /*! @name PR - Prescale Register. When the Prescale Counter (PC) is equal to this value, the next clock increments the TC and clears the PC. */ +/*! @{ */ #define CTIMER_PR_PRVAL_MASK (0xFFFFFFFFU) #define CTIMER_PR_PRVAL_SHIFT (0U) #define CTIMER_PR_PRVAL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PR_PRVAL_SHIFT)) & CTIMER_PR_PRVAL_MASK) +/*! @} */ /*! @name PC - Prescale Counter. The 32 bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface. */ +/*! @{ */ #define CTIMER_PC_PCVAL_MASK (0xFFFFFFFFU) #define CTIMER_PC_PCVAL_SHIFT (0U) #define CTIMER_PC_PCVAL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PC_PCVAL_SHIFT)) & CTIMER_PC_PCVAL_MASK) +/*! @} */ /*! @name MCR - Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs. */ +/*! @{ */ #define CTIMER_MCR_MR0I_MASK (0x1U) #define CTIMER_MCR_MR0I_SHIFT (0U) #define CTIMER_MCR_MR0I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0I_SHIFT)) & CTIMER_MCR_MR0I_MASK) @@ -884,16 +969,20 @@ typedef struct { #define CTIMER_MCR_MR3S_MASK (0x800U) #define CTIMER_MCR_MR3S_SHIFT (11U) #define CTIMER_MCR_MR3S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3S_SHIFT)) & CTIMER_MCR_MR3S_MASK) +/*! @} */ /*! @name MR - Match Register . MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. */ +/*! @{ */ #define CTIMER_MR_MATCH_MASK (0xFFFFFFFFU) #define CTIMER_MR_MATCH_SHIFT (0U) #define CTIMER_MR_MATCH(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MR_MATCH_SHIFT)) & CTIMER_MR_MATCH_MASK) +/*! @} */ /* The count of CTIMER_MR */ #define CTIMER_MR_COUNT (4U) /*! @name CCR - Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. */ +/*! @{ */ #define CTIMER_CCR_CAP0RE_MASK (0x1U) #define CTIMER_CCR_CAP0RE_SHIFT (0U) #define CTIMER_CCR_CAP0RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0RE_SHIFT)) & CTIMER_CCR_CAP0RE_MASK) @@ -930,16 +1019,20 @@ typedef struct { #define CTIMER_CCR_CAP3I_MASK (0x800U) #define CTIMER_CCR_CAP3I_SHIFT (11U) #define CTIMER_CCR_CAP3I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3I_SHIFT)) & CTIMER_CCR_CAP3I_MASK) +/*! @} */ /*! @name CR - Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input. */ +/*! @{ */ #define CTIMER_CR_CAP_MASK (0xFFFFFFFFU) #define CTIMER_CR_CAP_SHIFT (0U) #define CTIMER_CR_CAP(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CR_CAP_SHIFT)) & CTIMER_CR_CAP_MASK) +/*! @} */ /* The count of CTIMER_CR */ #define CTIMER_CR_COUNT (4U) /*! @name EMR - External Match Register. The EMR controls the match function and the external match pins. */ +/*! @{ */ #define CTIMER_EMR_EM0_MASK (0x1U) #define CTIMER_EMR_EM0_SHIFT (0U) #define CTIMER_EMR_EM0(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM0_SHIFT)) & CTIMER_EMR_EM0_MASK) @@ -964,8 +1057,10 @@ typedef struct { #define CTIMER_EMR_EMC3_MASK (0xC00U) #define CTIMER_EMR_EMC3_SHIFT (10U) #define CTIMER_EMR_EMC3(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC3_SHIFT)) & CTIMER_EMR_EMC3_MASK) +/*! @} */ /*! @name CTCR - Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. */ +/*! @{ */ #define CTIMER_CTCR_CTMODE_MASK (0x3U) #define CTIMER_CTCR_CTMODE_SHIFT (0U) #define CTIMER_CTCR_CTMODE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_CTMODE_SHIFT)) & CTIMER_CTCR_CTMODE_MASK) @@ -978,8 +1073,10 @@ typedef struct { #define CTIMER_CTCR_SELCC_MASK (0xE0U) #define CTIMER_CTCR_SELCC_SHIFT (5U) #define CTIMER_CTCR_SELCC(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_SELCC_SHIFT)) & CTIMER_CTCR_SELCC_MASK) +/*! @} */ /*! @name PWMC - PWM Control Register. The PWMCON enables PWM mode for the external match pins. */ +/*! @{ */ #define CTIMER_PWMC_PWMEN0_MASK (0x1U) #define CTIMER_PWMC_PWMEN0_SHIFT (0U) #define CTIMER_PWMC_PWMEN0(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN0_SHIFT)) & CTIMER_PWMC_PWMEN0_MASK) @@ -992,6 +1089,7 @@ typedef struct { #define CTIMER_PWMC_PWMEN3_MASK (0x8U) #define CTIMER_PWMC_PWMEN3_SHIFT (3U) #define CTIMER_PWMC_PWMEN3(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN3_SHIFT)) & CTIMER_PWMC_PWMEN3_MASK) +/*! @} */ /*! @@ -1091,120 +1189,151 @@ typedef struct { */ /*! @name CTRL - DMA control. */ +/*! @{ */ #define DMA_CTRL_ENABLE_MASK (0x1U) #define DMA_CTRL_ENABLE_SHIFT (0U) #define DMA_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CTRL_ENABLE_SHIFT)) & DMA_CTRL_ENABLE_MASK) +/*! @} */ /*! @name INTSTAT - Interrupt status. */ +/*! @{ */ #define DMA_INTSTAT_ACTIVEINT_MASK (0x2U) #define DMA_INTSTAT_ACTIVEINT_SHIFT (1U) #define DMA_INTSTAT_ACTIVEINT(x) (((uint32_t)(((uint32_t)(x)) << DMA_INTSTAT_ACTIVEINT_SHIFT)) & DMA_INTSTAT_ACTIVEINT_MASK) #define DMA_INTSTAT_ACTIVEERRINT_MASK (0x4U) #define DMA_INTSTAT_ACTIVEERRINT_SHIFT (2U) #define DMA_INTSTAT_ACTIVEERRINT(x) (((uint32_t)(((uint32_t)(x)) << DMA_INTSTAT_ACTIVEERRINT_SHIFT)) & DMA_INTSTAT_ACTIVEERRINT_MASK) +/*! @} */ /*! @name SRAMBASE - SRAM address of the channel configuration table. */ +/*! @{ */ #define DMA_SRAMBASE_OFFSET_MASK (0xFFFFFE00U) #define DMA_SRAMBASE_OFFSET_SHIFT (9U) #define DMA_SRAMBASE_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << DMA_SRAMBASE_OFFSET_SHIFT)) & DMA_SRAMBASE_OFFSET_MASK) +/*! @} */ /*! @name COMMON_ENABLESET - Channel Enable read and Set for all DMA channels. */ +/*! @{ */ #define DMA_COMMON_ENABLESET_ENA_MASK (0xFFFFFFFFU) #define DMA_COMMON_ENABLESET_ENA_SHIFT (0U) #define DMA_COMMON_ENABLESET_ENA(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENA_SHIFT)) & DMA_COMMON_ENABLESET_ENA_MASK) +/*! @} */ /* The count of DMA_COMMON_ENABLESET */ #define DMA_COMMON_ENABLESET_COUNT (1U) /*! @name COMMON_ENABLECLR - Channel Enable Clear for all DMA channels. */ +/*! @{ */ #define DMA_COMMON_ENABLECLR_CLR_MASK (0xFFFFFFFFU) #define DMA_COMMON_ENABLECLR_CLR_SHIFT (0U) #define DMA_COMMON_ENABLECLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR_SHIFT)) & DMA_COMMON_ENABLECLR_CLR_MASK) +/*! @} */ /* The count of DMA_COMMON_ENABLECLR */ #define DMA_COMMON_ENABLECLR_COUNT (1U) /*! @name COMMON_ACTIVE - Channel Active status for all DMA channels. */ +/*! @{ */ #define DMA_COMMON_ACTIVE_ACT_MASK (0xFFFFFFFFU) #define DMA_COMMON_ACTIVE_ACT_SHIFT (0U) #define DMA_COMMON_ACTIVE_ACT(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACT_SHIFT)) & DMA_COMMON_ACTIVE_ACT_MASK) +/*! @} */ /* The count of DMA_COMMON_ACTIVE */ #define DMA_COMMON_ACTIVE_COUNT (1U) /*! @name COMMON_BUSY - Channel Busy status for all DMA channels. */ +/*! @{ */ #define DMA_COMMON_BUSY_BSY_MASK (0xFFFFFFFFU) #define DMA_COMMON_BUSY_BSY_SHIFT (0U) #define DMA_COMMON_BUSY_BSY(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BSY_SHIFT)) & DMA_COMMON_BUSY_BSY_MASK) +/*! @} */ /* The count of DMA_COMMON_BUSY */ #define DMA_COMMON_BUSY_COUNT (1U) /*! @name COMMON_ERRINT - Error Interrupt status for all DMA channels. */ +/*! @{ */ #define DMA_COMMON_ERRINT_ERR_MASK (0xFFFFFFFFU) #define DMA_COMMON_ERRINT_ERR_SHIFT (0U) #define DMA_COMMON_ERRINT_ERR(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR_SHIFT)) & DMA_COMMON_ERRINT_ERR_MASK) +/*! @} */ /* The count of DMA_COMMON_ERRINT */ #define DMA_COMMON_ERRINT_COUNT (1U) /*! @name COMMON_INTENSET - Interrupt Enable read and Set for all DMA channels. */ +/*! @{ */ #define DMA_COMMON_INTENSET_INTEN_MASK (0xFFFFFFFFU) #define DMA_COMMON_INTENSET_INTEN_SHIFT (0U) #define DMA_COMMON_INTENSET_INTEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN_SHIFT)) & DMA_COMMON_INTENSET_INTEN_MASK) +/*! @} */ /* The count of DMA_COMMON_INTENSET */ #define DMA_COMMON_INTENSET_COUNT (1U) /*! @name COMMON_INTENCLR - Interrupt Enable Clear for all DMA channels. */ +/*! @{ */ #define DMA_COMMON_INTENCLR_CLR_MASK (0xFFFFFFFFU) #define DMA_COMMON_INTENCLR_CLR_SHIFT (0U) #define DMA_COMMON_INTENCLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR_SHIFT)) & DMA_COMMON_INTENCLR_CLR_MASK) +/*! @} */ /* The count of DMA_COMMON_INTENCLR */ #define DMA_COMMON_INTENCLR_COUNT (1U) /*! @name COMMON_INTA - Interrupt A status for all DMA channels. */ +/*! @{ */ #define DMA_COMMON_INTA_IA_MASK (0xFFFFFFFFU) #define DMA_COMMON_INTA_IA_SHIFT (0U) #define DMA_COMMON_INTA_IA(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_IA_SHIFT)) & DMA_COMMON_INTA_IA_MASK) +/*! @} */ /* The count of DMA_COMMON_INTA */ #define DMA_COMMON_INTA_COUNT (1U) /*! @name COMMON_INTB - Interrupt B status for all DMA channels. */ +/*! @{ */ #define DMA_COMMON_INTB_IB_MASK (0xFFFFFFFFU) #define DMA_COMMON_INTB_IB_SHIFT (0U) #define DMA_COMMON_INTB_IB(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_IB_SHIFT)) & DMA_COMMON_INTB_IB_MASK) +/*! @} */ /* The count of DMA_COMMON_INTB */ #define DMA_COMMON_INTB_COUNT (1U) /*! @name COMMON_SETVALID - Set ValidPending control bits for all DMA channels. */ +/*! @{ */ #define DMA_COMMON_SETVALID_SV_MASK (0xFFFFFFFFU) #define DMA_COMMON_SETVALID_SV_SHIFT (0U) #define DMA_COMMON_SETVALID_SV(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SV_SHIFT)) & DMA_COMMON_SETVALID_SV_MASK) +/*! @} */ /* The count of DMA_COMMON_SETVALID */ #define DMA_COMMON_SETVALID_COUNT (1U) /*! @name COMMON_SETTRIG - Set Trigger control bits for all DMA channels. */ +/*! @{ */ #define DMA_COMMON_SETTRIG_TRIG_MASK (0xFFFFFFFFU) #define DMA_COMMON_SETTRIG_TRIG_SHIFT (0U) #define DMA_COMMON_SETTRIG_TRIG(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_TRIG_SHIFT)) & DMA_COMMON_SETTRIG_TRIG_MASK) +/*! @} */ /* The count of DMA_COMMON_SETTRIG */ #define DMA_COMMON_SETTRIG_COUNT (1U) /*! @name COMMON_ABORT - Channel Abort control for all DMA channels. */ +/*! @{ */ #define DMA_COMMON_ABORT_ABORTCTRL_MASK (0xFFFFFFFFU) #define DMA_COMMON_ABORT_ABORTCTRL_SHIFT (0U) #define DMA_COMMON_ABORT_ABORTCTRL(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORTCTRL_SHIFT)) & DMA_COMMON_ABORT_ABORTCTRL_MASK) +/*! @} */ /* The count of DMA_COMMON_ABORT */ #define DMA_COMMON_ABORT_COUNT (1U) /*! @name CHANNEL_CFG - Configuration register for DMA channel . */ +/*! @{ */ #define DMA_CHANNEL_CFG_PERIPHREQEN_MASK (0x1U) #define DMA_CHANNEL_CFG_PERIPHREQEN_SHIFT (0U) #define DMA_CHANNEL_CFG_PERIPHREQEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_PERIPHREQEN_SHIFT)) & DMA_CHANNEL_CFG_PERIPHREQEN_MASK) @@ -1232,22 +1361,26 @@ typedef struct { #define DMA_CHANNEL_CFG_CHPRIORITY_MASK (0x70000U) #define DMA_CHANNEL_CFG_CHPRIORITY_SHIFT (16U) #define DMA_CHANNEL_CFG_CHPRIORITY(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_CHPRIORITY_SHIFT)) & DMA_CHANNEL_CFG_CHPRIORITY_MASK) +/*! @} */ /* The count of DMA_CHANNEL_CFG */ #define DMA_CHANNEL_CFG_COUNT (20U) /*! @name CHANNEL_CTLSTAT - Control and status register for DMA channel . */ +/*! @{ */ #define DMA_CHANNEL_CTLSTAT_VALIDPENDING_MASK (0x1U) #define DMA_CHANNEL_CTLSTAT_VALIDPENDING_SHIFT (0U) #define DMA_CHANNEL_CTLSTAT_VALIDPENDING(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CTLSTAT_VALIDPENDING_SHIFT)) & DMA_CHANNEL_CTLSTAT_VALIDPENDING_MASK) #define DMA_CHANNEL_CTLSTAT_TRIG_MASK (0x4U) #define DMA_CHANNEL_CTLSTAT_TRIG_SHIFT (2U) #define DMA_CHANNEL_CTLSTAT_TRIG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CTLSTAT_TRIG_SHIFT)) & DMA_CHANNEL_CTLSTAT_TRIG_MASK) +/*! @} */ /* The count of DMA_CHANNEL_CTLSTAT */ #define DMA_CHANNEL_CTLSTAT_COUNT (20U) /*! @name CHANNEL_XFERCFG - Transfer configuration register for DMA channel . */ +/*! @{ */ #define DMA_CHANNEL_XFERCFG_CFGVALID_MASK (0x1U) #define DMA_CHANNEL_XFERCFG_CFGVALID_SHIFT (0U) #define DMA_CHANNEL_XFERCFG_CFGVALID(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_CFGVALID_SHIFT)) & DMA_CHANNEL_XFERCFG_CFGVALID_MASK) @@ -1278,6 +1411,7 @@ typedef struct { #define DMA_CHANNEL_XFERCFG_XFERCOUNT_MASK (0x3FF0000U) #define DMA_CHANNEL_XFERCFG_XFERCOUNT_SHIFT (16U) #define DMA_CHANNEL_XFERCFG_XFERCOUNT(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_XFERCOUNT_SHIFT)) & DMA_CHANNEL_XFERCFG_XFERCOUNT_MASK) +/*! @} */ /* The count of DMA_CHANNEL_XFERCFG */ #define DMA_CHANNEL_XFERCFG_COUNT (20U) @@ -1357,46 +1491,57 @@ typedef struct { */ /*! @name CHANNEL_OSR - Oversample Rate register 0 */ +/*! @{ */ #define DMIC_CHANNEL_OSR_OSR_MASK (0xFFU) #define DMIC_CHANNEL_OSR_OSR_SHIFT (0U) #define DMIC_CHANNEL_OSR_OSR(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_OSR_OSR_SHIFT)) & DMIC_CHANNEL_OSR_OSR_MASK) +/*! @} */ /* The count of DMIC_CHANNEL_OSR */ #define DMIC_CHANNEL_OSR_COUNT (2U) /*! @name CHANNEL_DIVHFCLK - DMIC Clock Register 0 */ +/*! @{ */ #define DMIC_CHANNEL_DIVHFCLK_PDMDIV_MASK (0xFU) #define DMIC_CHANNEL_DIVHFCLK_PDMDIV_SHIFT (0U) #define DMIC_CHANNEL_DIVHFCLK_PDMDIV(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_DIVHFCLK_PDMDIV_SHIFT)) & DMIC_CHANNEL_DIVHFCLK_PDMDIV_MASK) +/*! @} */ /* The count of DMIC_CHANNEL_DIVHFCLK */ #define DMIC_CHANNEL_DIVHFCLK_COUNT (2U) /*! @name CHANNEL_PREAC2FSCOEF - Pre-Emphasis Filter Coefficient for 2 FS register */ +/*! @{ */ #define DMIC_CHANNEL_PREAC2FSCOEF_COMP_MASK (0x3U) #define DMIC_CHANNEL_PREAC2FSCOEF_COMP_SHIFT (0U) #define DMIC_CHANNEL_PREAC2FSCOEF_COMP(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_PREAC2FSCOEF_COMP_SHIFT)) & DMIC_CHANNEL_PREAC2FSCOEF_COMP_MASK) +/*! @} */ /* The count of DMIC_CHANNEL_PREAC2FSCOEF */ #define DMIC_CHANNEL_PREAC2FSCOEF_COUNT (2U) /*! @name CHANNEL_PREAC4FSCOEF - Pre-Emphasis Filter Coefficient for 4 FS register */ +/*! @{ */ #define DMIC_CHANNEL_PREAC4FSCOEF_COMP_MASK (0x3U) #define DMIC_CHANNEL_PREAC4FSCOEF_COMP_SHIFT (0U) #define DMIC_CHANNEL_PREAC4FSCOEF_COMP(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_PREAC4FSCOEF_COMP_SHIFT)) & DMIC_CHANNEL_PREAC4FSCOEF_COMP_MASK) +/*! @} */ /* The count of DMIC_CHANNEL_PREAC4FSCOEF */ #define DMIC_CHANNEL_PREAC4FSCOEF_COUNT (2U) /*! @name CHANNEL_GAINSHIFT - Decimator Gain Shift register */ +/*! @{ */ #define DMIC_CHANNEL_GAINSHIFT_GAIN_MASK (0x3FU) #define DMIC_CHANNEL_GAINSHIFT_GAIN_SHIFT (0U) #define DMIC_CHANNEL_GAINSHIFT_GAIN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_GAINSHIFT_GAIN_SHIFT)) & DMIC_CHANNEL_GAINSHIFT_GAIN_MASK) +/*! @} */ /* The count of DMIC_CHANNEL_GAINSHIFT */ #define DMIC_CHANNEL_GAINSHIFT_COUNT (2U) /*! @name CHANNEL_FIFO_CTRL - FIFO Control register 0 */ +/*! @{ */ #define DMIC_CHANNEL_FIFO_CTRL_ENABLE_MASK (0x1U) #define DMIC_CHANNEL_FIFO_CTRL_ENABLE_SHIFT (0U) #define DMIC_CHANNEL_FIFO_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_CTRL_ENABLE_SHIFT)) & DMIC_CHANNEL_FIFO_CTRL_ENABLE_MASK) @@ -1412,11 +1557,13 @@ typedef struct { #define DMIC_CHANNEL_FIFO_CTRL_TRIGLVL_MASK (0x1F0000U) #define DMIC_CHANNEL_FIFO_CTRL_TRIGLVL_SHIFT (16U) #define DMIC_CHANNEL_FIFO_CTRL_TRIGLVL(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_CTRL_TRIGLVL_SHIFT)) & DMIC_CHANNEL_FIFO_CTRL_TRIGLVL_MASK) +/*! @} */ /* The count of DMIC_CHANNEL_FIFO_CTRL */ #define DMIC_CHANNEL_FIFO_CTRL_COUNT (2U) /*! @name CHANNEL_FIFO_STATUS - FIFO Status register 0 */ +/*! @{ */ #define DMIC_CHANNEL_FIFO_STATUS_INT_MASK (0x1U) #define DMIC_CHANNEL_FIFO_STATUS_INT_SHIFT (0U) #define DMIC_CHANNEL_FIFO_STATUS_INT(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_STATUS_INT_SHIFT)) & DMIC_CHANNEL_FIFO_STATUS_INT_MASK) @@ -1426,30 +1573,36 @@ typedef struct { #define DMIC_CHANNEL_FIFO_STATUS_UNDERRUN_MASK (0x4U) #define DMIC_CHANNEL_FIFO_STATUS_UNDERRUN_SHIFT (2U) #define DMIC_CHANNEL_FIFO_STATUS_UNDERRUN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_STATUS_UNDERRUN_SHIFT)) & DMIC_CHANNEL_FIFO_STATUS_UNDERRUN_MASK) +/*! @} */ /* The count of DMIC_CHANNEL_FIFO_STATUS */ #define DMIC_CHANNEL_FIFO_STATUS_COUNT (2U) /*! @name CHANNEL_FIFO_DATA - FIFO Data Register 0 */ +/*! @{ */ #define DMIC_CHANNEL_FIFO_DATA_DATA_MASK (0xFFFFFFU) #define DMIC_CHANNEL_FIFO_DATA_DATA_SHIFT (0U) #define DMIC_CHANNEL_FIFO_DATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_DATA_DATA_SHIFT)) & DMIC_CHANNEL_FIFO_DATA_DATA_MASK) +/*! @} */ /* The count of DMIC_CHANNEL_FIFO_DATA */ #define DMIC_CHANNEL_FIFO_DATA_COUNT (2U) /*! @name CHANNEL_PHY_CTRL - PDM Source Configuration register 0 */ +/*! @{ */ #define DMIC_CHANNEL_PHY_CTRL_PHY_FALL_MASK (0x1U) #define DMIC_CHANNEL_PHY_CTRL_PHY_FALL_SHIFT (0U) #define DMIC_CHANNEL_PHY_CTRL_PHY_FALL(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_PHY_CTRL_PHY_FALL_SHIFT)) & DMIC_CHANNEL_PHY_CTRL_PHY_FALL_MASK) #define DMIC_CHANNEL_PHY_CTRL_PHY_HALF_MASK (0x2U) #define DMIC_CHANNEL_PHY_CTRL_PHY_HALF_SHIFT (1U) #define DMIC_CHANNEL_PHY_CTRL_PHY_HALF(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_PHY_CTRL_PHY_HALF_SHIFT)) & DMIC_CHANNEL_PHY_CTRL_PHY_HALF_MASK) +/*! @} */ /* The count of DMIC_CHANNEL_PHY_CTRL */ #define DMIC_CHANNEL_PHY_CTRL_COUNT (2U) /*! @name CHANNEL_DC_CTRL - DC Control register 0 */ +/*! @{ */ #define DMIC_CHANNEL_DC_CTRL_DCPOLE_MASK (0x3U) #define DMIC_CHANNEL_DC_CTRL_DCPOLE_SHIFT (0U) #define DMIC_CHANNEL_DC_CTRL_DCPOLE(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_DC_CTRL_DCPOLE_SHIFT)) & DMIC_CHANNEL_DC_CTRL_DCPOLE_MASK) @@ -1459,19 +1612,23 @@ typedef struct { #define DMIC_CHANNEL_DC_CTRL_SATURATEAT16BIT_MASK (0x100U) #define DMIC_CHANNEL_DC_CTRL_SATURATEAT16BIT_SHIFT (8U) #define DMIC_CHANNEL_DC_CTRL_SATURATEAT16BIT(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_DC_CTRL_SATURATEAT16BIT_SHIFT)) & DMIC_CHANNEL_DC_CTRL_SATURATEAT16BIT_MASK) +/*! @} */ /* The count of DMIC_CHANNEL_DC_CTRL */ #define DMIC_CHANNEL_DC_CTRL_COUNT (2U) /*! @name CHANEN - Channel Enable register */ +/*! @{ */ #define DMIC_CHANEN_EN_CH0_MASK (0x1U) #define DMIC_CHANEN_EN_CH0_SHIFT (0U) #define DMIC_CHANEN_EN_CH0(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANEN_EN_CH0_SHIFT)) & DMIC_CHANEN_EN_CH0_MASK) #define DMIC_CHANEN_EN_CH1_MASK (0x2U) #define DMIC_CHANEN_EN_CH1_SHIFT (1U) #define DMIC_CHANEN_EN_CH1(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANEN_EN_CH1_SHIFT)) & DMIC_CHANEN_EN_CH1_MASK) +/*! @} */ /*! @name IOCFG - I/O Configuration register */ +/*! @{ */ #define DMIC_IOCFG_CLK_BYPASS0_MASK (0x1U) #define DMIC_IOCFG_CLK_BYPASS0_SHIFT (0U) #define DMIC_IOCFG_CLK_BYPASS0(x) (((uint32_t)(((uint32_t)(x)) << DMIC_IOCFG_CLK_BYPASS0_SHIFT)) & DMIC_IOCFG_CLK_BYPASS0_MASK) @@ -1481,51 +1638,70 @@ typedef struct { #define DMIC_IOCFG_STEREO_DATA0_MASK (0x4U) #define DMIC_IOCFG_STEREO_DATA0_SHIFT (2U) #define DMIC_IOCFG_STEREO_DATA0(x) (((uint32_t)(((uint32_t)(x)) << DMIC_IOCFG_STEREO_DATA0_SHIFT)) & DMIC_IOCFG_STEREO_DATA0_MASK) +/*! @} */ /*! @name USE2FS - Use 2FS register */ +/*! @{ */ #define DMIC_USE2FS_USE2FS_MASK (0x1U) #define DMIC_USE2FS_USE2FS_SHIFT (0U) #define DMIC_USE2FS_USE2FS(x) (((uint32_t)(((uint32_t)(x)) << DMIC_USE2FS_USE2FS_SHIFT)) & DMIC_USE2FS_USE2FS_MASK) +/*! @} */ /*! @name HWVADGAIN - HWVAD input gain register */ +/*! @{ */ #define DMIC_HWVADGAIN_INPUTGAIN_MASK (0xFU) #define DMIC_HWVADGAIN_INPUTGAIN_SHIFT (0U) #define DMIC_HWVADGAIN_INPUTGAIN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADGAIN_INPUTGAIN_SHIFT)) & DMIC_HWVADGAIN_INPUTGAIN_MASK) +/*! @} */ /*! @name HWVADHPFS - HWVAD filter control register */ +/*! @{ */ #define DMIC_HWVADHPFS_HPFS_MASK (0x3U) #define DMIC_HWVADHPFS_HPFS_SHIFT (0U) #define DMIC_HWVADHPFS_HPFS(x) (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADHPFS_HPFS_SHIFT)) & DMIC_HWVADHPFS_HPFS_MASK) +/*! @} */ /*! @name HWVADST10 - HWVAD control register */ +/*! @{ */ #define DMIC_HWVADST10_ST10_MASK (0x1U) #define DMIC_HWVADST10_ST10_SHIFT (0U) #define DMIC_HWVADST10_ST10(x) (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADST10_ST10_SHIFT)) & DMIC_HWVADST10_ST10_MASK) +/*! @} */ /*! @name HWVADRSTT - HWVAD filter reset register */ +/*! @{ */ #define DMIC_HWVADRSTT_RSTT_MASK (0x1U) #define DMIC_HWVADRSTT_RSTT_SHIFT (0U) #define DMIC_HWVADRSTT_RSTT(x) (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADRSTT_RSTT_SHIFT)) & DMIC_HWVADRSTT_RSTT_MASK) +/*! @} */ /*! @name HWVADTHGN - HWVAD noise estimator gain register */ +/*! @{ */ #define DMIC_HWVADTHGN_THGN_MASK (0xFU) #define DMIC_HWVADTHGN_THGN_SHIFT (0U) #define DMIC_HWVADTHGN_THGN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADTHGN_THGN_SHIFT)) & DMIC_HWVADTHGN_THGN_MASK) +/*! @} */ /*! @name HWVADTHGS - HWVAD signal estimator gain register */ +/*! @{ */ #define DMIC_HWVADTHGS_THGS_MASK (0xFU) #define DMIC_HWVADTHGS_THGS_SHIFT (0U) #define DMIC_HWVADTHGS_THGS(x) (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADTHGS_THGS_SHIFT)) & DMIC_HWVADTHGS_THGS_MASK) +/*! @} */ /*! @name HWVADLOWZ - HWVAD noise envelope estimator register */ +/*! @{ */ #define DMIC_HWVADLOWZ_LOWZ_MASK (0xFFFFU) #define DMIC_HWVADLOWZ_LOWZ_SHIFT (0U) #define DMIC_HWVADLOWZ_LOWZ(x) (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADLOWZ_LOWZ_SHIFT)) & DMIC_HWVADLOWZ_LOWZ_MASK) +/*! @} */ /*! @name ID - Module Identification register */ +/*! @{ */ #define DMIC_ID_ID_MASK (0xFFFFFFFFU) #define DMIC_ID_ID_SHIFT (0U) #define DMIC_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << DMIC_ID_ID_SHIFT)) & DMIC_ID_ID_MASK) +/*! @} */ /*! @@ -1577,6 +1753,7 @@ typedef struct { */ /*! @name PSELID - Peripheral Select and Flexcomm ID register. */ +/*! @{ */ #define FLEXCOMM_PSELID_PERSEL_MASK (0x7U) #define FLEXCOMM_PSELID_PERSEL_SHIFT (0U) #define FLEXCOMM_PSELID_PERSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_PERSEL_SHIFT)) & FLEXCOMM_PSELID_PERSEL_MASK) @@ -1598,8 +1775,10 @@ typedef struct { #define FLEXCOMM_PSELID_ID_MASK (0xFFFFF000U) #define FLEXCOMM_PSELID_ID_SHIFT (12U) #define FLEXCOMM_PSELID_ID(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_ID_SHIFT)) & FLEXCOMM_PSELID_ID_MASK) +/*! @} */ /*! @name PID - Peripheral identification register. */ +/*! @{ */ #define FLEXCOMM_PID_Minor_Rev_MASK (0xF00U) #define FLEXCOMM_PID_Minor_Rev_SHIFT (8U) #define FLEXCOMM_PID_Minor_Rev(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PID_Minor_Rev_SHIFT)) & FLEXCOMM_PID_Minor_Rev_MASK) @@ -1609,6 +1788,7 @@ typedef struct { #define FLEXCOMM_PID_ID_MASK (0xFFFF0000U) #define FLEXCOMM_PID_ID_SHIFT (16U) #define FLEXCOMM_PID_ID(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PID_ID_SHIFT)) & FLEXCOMM_PID_ID_MASK) +/*! @} */ /*! @@ -1689,6 +1869,7 @@ typedef struct { */ /*! @name CTRL - GPIO grouped interrupt control register */ +/*! @{ */ #define GINT_CTRL_INT_MASK (0x1U) #define GINT_CTRL_INT_SHIFT (0U) #define GINT_CTRL_INT(x) (((uint32_t)(((uint32_t)(x)) << GINT_CTRL_INT_SHIFT)) & GINT_CTRL_INT_MASK) @@ -1698,19 +1879,24 @@ typedef struct { #define GINT_CTRL_TRIG_MASK (0x4U) #define GINT_CTRL_TRIG_SHIFT (2U) #define GINT_CTRL_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GINT_CTRL_TRIG_SHIFT)) & GINT_CTRL_TRIG_MASK) +/*! @} */ /*! @name PORT_POL - GPIO grouped interrupt port 0 polarity register */ +/*! @{ */ #define GINT_PORT_POL_POL_MASK (0xFFFFFFFFU) #define GINT_PORT_POL_POL_SHIFT (0U) #define GINT_PORT_POL_POL(x) (((uint32_t)(((uint32_t)(x)) << GINT_PORT_POL_POL_SHIFT)) & GINT_PORT_POL_POL_MASK) +/*! @} */ /* The count of GINT_PORT_POL */ #define GINT_PORT_POL_COUNT (2U) /*! @name PORT_ENA - GPIO grouped interrupt port 0 enable register */ +/*! @{ */ #define GINT_PORT_ENA_ENA_MASK (0xFFFFFFFFU) #define GINT_PORT_ENA_ENA_SHIFT (0U) #define GINT_PORT_ENA_ENA(x) (((uint32_t)(((uint32_t)(x)) << GINT_PORT_ENA_ENA_SHIFT)) & GINT_PORT_ENA_ENA_MASK) +/*! @} */ /* The count of GINT_PORT_ENA */ #define GINT_PORT_ENA_COUNT (2U) @@ -1788,9 +1974,11 @@ typedef struct { */ /*! @name B - Byte pin registers for all port 0 and 1 GPIO pins */ +/*! @{ */ #define GPIO_B_PBYTE_MASK (0x1U) #define GPIO_B_PBYTE_SHIFT (0U) #define GPIO_B_PBYTE(x) (((uint8_t)(((uint8_t)(x)) << GPIO_B_PBYTE_SHIFT)) & GPIO_B_PBYTE_MASK) +/*! @} */ /* The count of GPIO_B */ #define GPIO_B_COUNT (2U) @@ -1799,9 +1987,11 @@ typedef struct { #define GPIO_B_COUNT2 (32U) /*! @name W - Word pin registers for all port 0 and 1 GPIO pins */ +/*! @{ */ #define GPIO_W_PWORD_MASK (0xFFFFFFFFU) #define GPIO_W_PWORD_SHIFT (0U) #define GPIO_W_PWORD(x) (((uint32_t)(((uint32_t)(x)) << GPIO_W_PWORD_SHIFT)) & GPIO_W_PWORD_MASK) +/*! @} */ /* The count of GPIO_W */ #define GPIO_W_COUNT (2U) @@ -1810,81 +2000,101 @@ typedef struct { #define GPIO_W_COUNT2 (32U) /*! @name DIR - Direction registers */ +/*! @{ */ #define GPIO_DIR_DIRP_MASK (0xFFFFFFFFU) #define GPIO_DIR_DIRP_SHIFT (0U) #define GPIO_DIR_DIRP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP_SHIFT)) & GPIO_DIR_DIRP_MASK) +/*! @} */ /* The count of GPIO_DIR */ #define GPIO_DIR_COUNT (2U) /*! @name MASK - Mask register */ +/*! @{ */ #define GPIO_MASK_MASKP_MASK (0xFFFFFFFFU) #define GPIO_MASK_MASKP_SHIFT (0U) #define GPIO_MASK_MASKP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP_SHIFT)) & GPIO_MASK_MASKP_MASK) +/*! @} */ /* The count of GPIO_MASK */ #define GPIO_MASK_COUNT (2U) /*! @name PIN - Port pin register */ +/*! @{ */ #define GPIO_PIN_PORT_MASK (0xFFFFFFFFU) #define GPIO_PIN_PORT_SHIFT (0U) #define GPIO_PIN_PORT(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT_SHIFT)) & GPIO_PIN_PORT_MASK) +/*! @} */ /* The count of GPIO_PIN */ #define GPIO_PIN_COUNT (2U) /*! @name MPIN - Masked port register */ +/*! @{ */ #define GPIO_MPIN_MPORTP_MASK (0xFFFFFFFFU) #define GPIO_MPIN_MPORTP_SHIFT (0U) #define GPIO_MPIN_MPORTP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP_SHIFT)) & GPIO_MPIN_MPORTP_MASK) +/*! @} */ /* The count of GPIO_MPIN */ #define GPIO_MPIN_COUNT (2U) /*! @name SET - Write: Set register for port Read: output bits for port */ +/*! @{ */ #define GPIO_SET_SETP_MASK (0xFFFFFFFFU) #define GPIO_SET_SETP_SHIFT (0U) #define GPIO_SET_SETP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_SET_SETP_SHIFT)) & GPIO_SET_SETP_MASK) +/*! @} */ /* The count of GPIO_SET */ #define GPIO_SET_COUNT (2U) /*! @name CLR - Clear port */ +/*! @{ */ #define GPIO_CLR_CLRP_MASK (0xFFFFFFFFU) #define GPIO_CLR_CLRP_SHIFT (0U) #define GPIO_CLR_CLRP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP_SHIFT)) & GPIO_CLR_CLRP_MASK) +/*! @} */ /* The count of GPIO_CLR */ #define GPIO_CLR_COUNT (2U) /*! @name NOT - Toggle port */ +/*! @{ */ #define GPIO_NOT_NOTP_MASK (0xFFFFFFFFU) #define GPIO_NOT_NOTP_SHIFT (0U) #define GPIO_NOT_NOTP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP_SHIFT)) & GPIO_NOT_NOTP_MASK) +/*! @} */ /* The count of GPIO_NOT */ #define GPIO_NOT_COUNT (2U) /*! @name DIRSET - Set pin direction bits for port */ +/*! @{ */ #define GPIO_DIRSET_DIRSETP_MASK (0x1FFFFFFFU) #define GPIO_DIRSET_DIRSETP_SHIFT (0U) #define GPIO_DIRSET_DIRSETP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP_SHIFT)) & GPIO_DIRSET_DIRSETP_MASK) +/*! @} */ /* The count of GPIO_DIRSET */ #define GPIO_DIRSET_COUNT (2U) /*! @name DIRCLR - Clear pin direction bits for port */ +/*! @{ */ #define GPIO_DIRCLR_DIRCLRP_MASK (0x1FFFFFFFU) #define GPIO_DIRCLR_DIRCLRP_SHIFT (0U) #define GPIO_DIRCLR_DIRCLRP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP_SHIFT)) & GPIO_DIRCLR_DIRCLRP_MASK) +/*! @} */ /* The count of GPIO_DIRCLR */ #define GPIO_DIRCLR_COUNT (2U) /*! @name DIRNOT - Toggle pin direction bits for port */ +/*! @{ */ #define GPIO_DIRNOT_DIRNOTP_MASK (0x1FFFFFFFU) #define GPIO_DIRNOT_DIRNOTP_SHIFT (0U) #define GPIO_DIRNOT_DIRNOTP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRNOT_DIRNOTP_SHIFT)) & GPIO_DIRNOT_DIRNOTP_MASK) +/*! @} */ /* The count of GPIO_DIRNOT */ #define GPIO_DIRNOT_COUNT (2U) @@ -1952,6 +2162,7 @@ typedef struct { */ /*! @name CFG - Configuration for shared functions. */ +/*! @{ */ #define I2C_CFG_MSTEN_MASK (0x1U) #define I2C_CFG_MSTEN_SHIFT (0U) #define I2C_CFG_MSTEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_MSTEN_SHIFT)) & I2C_CFG_MSTEN_MASK) @@ -1970,8 +2181,10 @@ typedef struct { #define I2C_CFG_HSCAPABLE_MASK (0x20U) #define I2C_CFG_HSCAPABLE_SHIFT (5U) #define I2C_CFG_HSCAPABLE(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_HSCAPABLE_SHIFT)) & I2C_CFG_HSCAPABLE_MASK) +/*! @} */ /*! @name STAT - Status register for Master, Slave, and Monitor functions. */ +/*! @{ */ #define I2C_STAT_MSTPENDING_MASK (0x1U) #define I2C_STAT_MSTPENDING_SHIFT (0U) #define I2C_STAT_MSTPENDING(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTPENDING_SHIFT)) & I2C_STAT_MSTPENDING_MASK) @@ -2020,8 +2233,10 @@ typedef struct { #define I2C_STAT_SCLTIMEOUT_MASK (0x2000000U) #define I2C_STAT_SCLTIMEOUT_SHIFT (25U) #define I2C_STAT_SCLTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SCLTIMEOUT_SHIFT)) & I2C_STAT_SCLTIMEOUT_MASK) +/*! @} */ /*! @name INTENSET - Interrupt Enable Set and read register. */ +/*! @{ */ #define I2C_INTENSET_MSTPENDINGEN_MASK (0x1U) #define I2C_INTENSET_MSTPENDINGEN_SHIFT (0U) #define I2C_INTENSET_MSTPENDINGEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MSTPENDINGEN_SHIFT)) & I2C_INTENSET_MSTPENDINGEN_MASK) @@ -2055,8 +2270,10 @@ typedef struct { #define I2C_INTENSET_SCLTIMEOUTEN_MASK (0x2000000U) #define I2C_INTENSET_SCLTIMEOUTEN_SHIFT (25U) #define I2C_INTENSET_SCLTIMEOUTEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SCLTIMEOUTEN_SHIFT)) & I2C_INTENSET_SCLTIMEOUTEN_MASK) +/*! @} */ /*! @name INTENCLR - Interrupt Enable Clear register. */ +/*! @{ */ #define I2C_INTENCLR_MSTPENDINGCLR_MASK (0x1U) #define I2C_INTENCLR_MSTPENDINGCLR_SHIFT (0U) #define I2C_INTENCLR_MSTPENDINGCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MSTPENDINGCLR_SHIFT)) & I2C_INTENCLR_MSTPENDINGCLR_MASK) @@ -2090,21 +2307,27 @@ typedef struct { #define I2C_INTENCLR_SCLTIMEOUTCLR_MASK (0x2000000U) #define I2C_INTENCLR_SCLTIMEOUTCLR_SHIFT (25U) #define I2C_INTENCLR_SCLTIMEOUTCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SCLTIMEOUTCLR_SHIFT)) & I2C_INTENCLR_SCLTIMEOUTCLR_MASK) +/*! @} */ /*! @name TIMEOUT - Time-out value register. */ +/*! @{ */ #define I2C_TIMEOUT_TOMIN_MASK (0xFU) #define I2C_TIMEOUT_TOMIN_SHIFT (0U) #define I2C_TIMEOUT_TOMIN(x) (((uint32_t)(((uint32_t)(x)) << I2C_TIMEOUT_TOMIN_SHIFT)) & I2C_TIMEOUT_TOMIN_MASK) #define I2C_TIMEOUT_TO_MASK (0xFFF0U) #define I2C_TIMEOUT_TO_SHIFT (4U) #define I2C_TIMEOUT_TO(x) (((uint32_t)(((uint32_t)(x)) << I2C_TIMEOUT_TO_SHIFT)) & I2C_TIMEOUT_TO_MASK) +/*! @} */ /*! @name CLKDIV - Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register, and controls some timing of the Slave function. */ +/*! @{ */ #define I2C_CLKDIV_DIVVAL_MASK (0xFFFFU) #define I2C_CLKDIV_DIVVAL_SHIFT (0U) #define I2C_CLKDIV_DIVVAL(x) (((uint32_t)(((uint32_t)(x)) << I2C_CLKDIV_DIVVAL_SHIFT)) & I2C_CLKDIV_DIVVAL_MASK) +/*! @} */ /*! @name INTSTAT - Interrupt Status register for Master, Slave, and Monitor functions. */ +/*! @{ */ #define I2C_INTSTAT_MSTPENDING_MASK (0x1U) #define I2C_INTSTAT_MSTPENDING_SHIFT (0U) #define I2C_INTSTAT_MSTPENDING(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MSTPENDING_SHIFT)) & I2C_INTSTAT_MSTPENDING_MASK) @@ -2138,8 +2361,10 @@ typedef struct { #define I2C_INTSTAT_SCLTIMEOUT_MASK (0x2000000U) #define I2C_INTSTAT_SCLTIMEOUT_SHIFT (25U) #define I2C_INTSTAT_SCLTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SCLTIMEOUT_SHIFT)) & I2C_INTSTAT_SCLTIMEOUT_MASK) +/*! @} */ /*! @name MSTCTL - Master control register. */ +/*! @{ */ #define I2C_MSTCTL_MSTCONTINUE_MASK (0x1U) #define I2C_MSTCTL_MSTCONTINUE_SHIFT (0U) #define I2C_MSTCTL_MSTCONTINUE(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTCONTINUE_SHIFT)) & I2C_MSTCTL_MSTCONTINUE_MASK) @@ -2152,21 +2377,27 @@ typedef struct { #define I2C_MSTCTL_MSTDMA_MASK (0x8U) #define I2C_MSTCTL_MSTDMA_SHIFT (3U) #define I2C_MSTCTL_MSTDMA(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTDMA_SHIFT)) & I2C_MSTCTL_MSTDMA_MASK) +/*! @} */ /*! @name MSTTIME - Master timing configuration. */ +/*! @{ */ #define I2C_MSTTIME_MSTSCLLOW_MASK (0x7U) #define I2C_MSTTIME_MSTSCLLOW_SHIFT (0U) #define I2C_MSTTIME_MSTSCLLOW(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTTIME_MSTSCLLOW_SHIFT)) & I2C_MSTTIME_MSTSCLLOW_MASK) #define I2C_MSTTIME_MSTSCLHIGH_MASK (0x70U) #define I2C_MSTTIME_MSTSCLHIGH_SHIFT (4U) #define I2C_MSTTIME_MSTSCLHIGH(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTTIME_MSTSCLHIGH_SHIFT)) & I2C_MSTTIME_MSTSCLHIGH_MASK) +/*! @} */ /*! @name MSTDAT - Combined Master receiver and transmitter data register. */ +/*! @{ */ #define I2C_MSTDAT_DATA_MASK (0xFFU) #define I2C_MSTDAT_DATA_SHIFT (0U) #define I2C_MSTDAT_DATA(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTDAT_DATA_SHIFT)) & I2C_MSTDAT_DATA_MASK) +/*! @} */ /*! @name SLVCTL - Slave control register. */ +/*! @{ */ #define I2C_SLVCTL_SLVCONTINUE_MASK (0x1U) #define I2C_SLVCTL_SLVCONTINUE_SHIFT (0U) #define I2C_SLVCTL_SLVCONTINUE(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_SLVCONTINUE_SHIFT)) & I2C_SLVCTL_SLVCONTINUE_MASK) @@ -2182,13 +2413,17 @@ typedef struct { #define I2C_SLVCTL_AUTOMATCHREAD_MASK (0x200U) #define I2C_SLVCTL_AUTOMATCHREAD_SHIFT (9U) #define I2C_SLVCTL_AUTOMATCHREAD(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_AUTOMATCHREAD_SHIFT)) & I2C_SLVCTL_AUTOMATCHREAD_MASK) +/*! @} */ /*! @name SLVDAT - Combined Slave receiver and transmitter data register. */ +/*! @{ */ #define I2C_SLVDAT_DATA_MASK (0xFFU) #define I2C_SLVDAT_DATA_SHIFT (0U) #define I2C_SLVDAT_DATA(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVDAT_DATA_SHIFT)) & I2C_SLVDAT_DATA_MASK) +/*! @} */ /*! @name SLVADR - Slave address register. */ +/*! @{ */ #define I2C_SLVADR_SADISABLE_MASK (0x1U) #define I2C_SLVADR_SADISABLE_SHIFT (0U) #define I2C_SLVADR_SADISABLE(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVADR_SADISABLE_SHIFT)) & I2C_SLVADR_SADISABLE_MASK) @@ -2198,19 +2433,23 @@ typedef struct { #define I2C_SLVADR_AUTONACK_MASK (0x8000U) #define I2C_SLVADR_AUTONACK_SHIFT (15U) #define I2C_SLVADR_AUTONACK(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVADR_AUTONACK_SHIFT)) & I2C_SLVADR_AUTONACK_MASK) +/*! @} */ /* The count of I2C_SLVADR */ #define I2C_SLVADR_COUNT (4U) /*! @name SLVQUAL0 - Slave Qualification for address 0. */ +/*! @{ */ #define I2C_SLVQUAL0_QUALMODE0_MASK (0x1U) #define I2C_SLVQUAL0_QUALMODE0_SHIFT (0U) #define I2C_SLVQUAL0_QUALMODE0(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVQUAL0_QUALMODE0_SHIFT)) & I2C_SLVQUAL0_QUALMODE0_MASK) #define I2C_SLVQUAL0_SLVQUAL0_MASK (0xFEU) #define I2C_SLVQUAL0_SLVQUAL0_SHIFT (1U) #define I2C_SLVQUAL0_SLVQUAL0(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVQUAL0_SLVQUAL0_SHIFT)) & I2C_SLVQUAL0_SLVQUAL0_MASK) +/*! @} */ /*! @name MONRXDAT - Monitor receiver data register. */ +/*! @{ */ #define I2C_MONRXDAT_MONRXDAT_MASK (0xFFU) #define I2C_MONRXDAT_MONRXDAT_SHIFT (0U) #define I2C_MONRXDAT_MONRXDAT(x) (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONRXDAT_SHIFT)) & I2C_MONRXDAT_MONRXDAT_MASK) @@ -2223,6 +2462,7 @@ typedef struct { #define I2C_MONRXDAT_MONNACK_MASK (0x400U) #define I2C_MONRXDAT_MONNACK_SHIFT (10U) #define I2C_MONRXDAT_MONNACK(x) (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONNACK_SHIFT)) & I2C_MONRXDAT_MONNACK_MASK) +/*! @} */ /*! @@ -2321,6 +2561,7 @@ typedef struct { */ /*! @name CFG1 - Configuration register 1 for the primary channel pair. */ +/*! @{ */ #define I2S_CFG1_MAINENABLE_MASK (0x1U) #define I2S_CFG1_MAINENABLE_SHIFT (0U) #define I2S_CFG1_MAINENABLE(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_MAINENABLE_SHIFT)) & I2S_CFG1_MAINENABLE_MASK) @@ -2357,16 +2598,20 @@ typedef struct { #define I2S_CFG1_DATALEN_MASK (0x1F0000U) #define I2S_CFG1_DATALEN_SHIFT (16U) #define I2S_CFG1_DATALEN(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_DATALEN_SHIFT)) & I2S_CFG1_DATALEN_MASK) +/*! @} */ /*! @name CFG2 - Configuration register 2 for the primary channel pair. */ +/*! @{ */ #define I2S_CFG2_FRAMELEN_MASK (0x1FFU) #define I2S_CFG2_FRAMELEN_SHIFT (0U) #define I2S_CFG2_FRAMELEN(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG2_FRAMELEN_SHIFT)) & I2S_CFG2_FRAMELEN_MASK) #define I2S_CFG2_POSITION_MASK (0x1FF0000U) #define I2S_CFG2_POSITION_SHIFT (16U) #define I2S_CFG2_POSITION(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG2_POSITION_SHIFT)) & I2S_CFG2_POSITION_MASK) +/*! @} */ /*! @name STAT - Status register for the primary channel pair. */ +/*! @{ */ #define I2S_STAT_BUSY_MASK (0x1U) #define I2S_STAT_BUSY_SHIFT (0U) #define I2S_STAT_BUSY(x) (((uint32_t)(((uint32_t)(x)) << I2S_STAT_BUSY_SHIFT)) & I2S_STAT_BUSY_MASK) @@ -2379,13 +2624,17 @@ typedef struct { #define I2S_STAT_DATAPAUSED_MASK (0x8U) #define I2S_STAT_DATAPAUSED_SHIFT (3U) #define I2S_STAT_DATAPAUSED(x) (((uint32_t)(((uint32_t)(x)) << I2S_STAT_DATAPAUSED_SHIFT)) & I2S_STAT_DATAPAUSED_MASK) +/*! @} */ /*! @name DIV - Clock divider, used by all channel pairs. */ +/*! @{ */ #define I2S_DIV_DIV_MASK (0xFFFU) #define I2S_DIV_DIV_SHIFT (0U) #define I2S_DIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << I2S_DIV_DIV_SHIFT)) & I2S_DIV_DIV_MASK) +/*! @} */ /*! @name FIFOCFG - FIFO configuration and enable register. */ +/*! @{ */ #define I2S_FIFOCFG_ENABLETX_MASK (0x1U) #define I2S_FIFOCFG_ENABLETX_SHIFT (0U) #define I2S_FIFOCFG_ENABLETX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_ENABLETX_SHIFT)) & I2S_FIFOCFG_ENABLETX_MASK) @@ -2422,8 +2671,10 @@ typedef struct { #define I2S_FIFOCFG_POPDBG_MASK (0x40000U) #define I2S_FIFOCFG_POPDBG_SHIFT (18U) #define I2S_FIFOCFG_POPDBG(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_POPDBG_SHIFT)) & I2S_FIFOCFG_POPDBG_MASK) +/*! @} */ /*! @name FIFOSTAT - FIFO status register. */ +/*! @{ */ #define I2S_FIFOSTAT_TXERR_MASK (0x1U) #define I2S_FIFOSTAT_TXERR_SHIFT (0U) #define I2S_FIFOSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_TXERR_SHIFT)) & I2S_FIFOSTAT_TXERR_MASK) @@ -2451,8 +2702,10 @@ typedef struct { #define I2S_FIFOSTAT_RXLVL_MASK (0x1F0000U) #define I2S_FIFOSTAT_RXLVL_SHIFT (16U) #define I2S_FIFOSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_RXLVL_SHIFT)) & I2S_FIFOSTAT_RXLVL_MASK) +/*! @} */ /*! @name FIFOTRIG - FIFO trigger settings for interrupt and DMA request. */ +/*! @{ */ #define I2S_FIFOTRIG_TXLVLENA_MASK (0x1U) #define I2S_FIFOTRIG_TXLVLENA_SHIFT (0U) #define I2S_FIFOTRIG_TXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOTRIG_TXLVLENA_SHIFT)) & I2S_FIFOTRIG_TXLVLENA_MASK) @@ -2465,8 +2718,10 @@ typedef struct { #define I2S_FIFOTRIG_RXLVL_MASK (0xF0000U) #define I2S_FIFOTRIG_RXLVL_SHIFT (16U) #define I2S_FIFOTRIG_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOTRIG_RXLVL_SHIFT)) & I2S_FIFOTRIG_RXLVL_MASK) +/*! @} */ /*! @name FIFOINTENSET - FIFO interrupt enable set (enable) and read register. */ +/*! @{ */ #define I2S_FIFOINTENSET_TXERR_MASK (0x1U) #define I2S_FIFOINTENSET_TXERR_SHIFT (0U) #define I2S_FIFOINTENSET_TXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENSET_TXERR_SHIFT)) & I2S_FIFOINTENSET_TXERR_MASK) @@ -2479,8 +2734,10 @@ typedef struct { #define I2S_FIFOINTENSET_RXLVL_MASK (0x8U) #define I2S_FIFOINTENSET_RXLVL_SHIFT (3U) #define I2S_FIFOINTENSET_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENSET_RXLVL_SHIFT)) & I2S_FIFOINTENSET_RXLVL_MASK) +/*! @} */ /*! @name FIFOINTENCLR - FIFO interrupt enable clear (disable) and read register. */ +/*! @{ */ #define I2S_FIFOINTENCLR_TXERR_MASK (0x1U) #define I2S_FIFOINTENCLR_TXERR_SHIFT (0U) #define I2S_FIFOINTENCLR_TXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENCLR_TXERR_SHIFT)) & I2S_FIFOINTENCLR_TXERR_MASK) @@ -2493,8 +2750,10 @@ typedef struct { #define I2S_FIFOINTENCLR_RXLVL_MASK (0x8U) #define I2S_FIFOINTENCLR_RXLVL_SHIFT (3U) #define I2S_FIFOINTENCLR_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENCLR_RXLVL_SHIFT)) & I2S_FIFOINTENCLR_RXLVL_MASK) +/*! @} */ /*! @name FIFOINTSTAT - FIFO interrupt status register. */ +/*! @{ */ #define I2S_FIFOINTSTAT_TXERR_MASK (0x1U) #define I2S_FIFOINTSTAT_TXERR_SHIFT (0U) #define I2S_FIFOINTSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_TXERR_SHIFT)) & I2S_FIFOINTSTAT_TXERR_MASK) @@ -2510,36 +2769,49 @@ typedef struct { #define I2S_FIFOINTSTAT_PERINT_MASK (0x10U) #define I2S_FIFOINTSTAT_PERINT_SHIFT (4U) #define I2S_FIFOINTSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_PERINT_SHIFT)) & I2S_FIFOINTSTAT_PERINT_MASK) +/*! @} */ /*! @name FIFOWR - FIFO write data. */ +/*! @{ */ #define I2S_FIFOWR_TXDATA_MASK (0xFFFFFFFFU) #define I2S_FIFOWR_TXDATA_SHIFT (0U) #define I2S_FIFOWR_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOWR_TXDATA_SHIFT)) & I2S_FIFOWR_TXDATA_MASK) +/*! @} */ /*! @name FIFOWR48H - FIFO write data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA. */ +/*! @{ */ #define I2S_FIFOWR48H_TXDATA_MASK (0xFFFFFFU) #define I2S_FIFOWR48H_TXDATA_SHIFT (0U) #define I2S_FIFOWR48H_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOWR48H_TXDATA_SHIFT)) & I2S_FIFOWR48H_TXDATA_MASK) +/*! @} */ /*! @name FIFORD - FIFO read data. */ +/*! @{ */ #define I2S_FIFORD_RXDATA_MASK (0xFFFFFFFFU) #define I2S_FIFORD_RXDATA_SHIFT (0U) #define I2S_FIFORD_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFORD_RXDATA_SHIFT)) & I2S_FIFORD_RXDATA_MASK) +/*! @} */ /*! @name FIFORD48H - FIFO read data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA. */ +/*! @{ */ #define I2S_FIFORD48H_RXDATA_MASK (0xFFFFFFU) #define I2S_FIFORD48H_RXDATA_SHIFT (0U) #define I2S_FIFORD48H_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFORD48H_RXDATA_SHIFT)) & I2S_FIFORD48H_RXDATA_MASK) +/*! @} */ /*! @name FIFORDNOPOP - FIFO data read with no FIFO pop. */ +/*! @{ */ #define I2S_FIFORDNOPOP_RXDATA_MASK (0xFFFFFFFFU) #define I2S_FIFORDNOPOP_RXDATA_SHIFT (0U) #define I2S_FIFORDNOPOP_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFORDNOPOP_RXDATA_SHIFT)) & I2S_FIFORDNOPOP_RXDATA_MASK) +/*! @} */ /*! @name FIFORD48HNOPOP - FIFO data read for upper data bits with no FIFO pop. May only be used if the I2S is configured for 2x 24-bit data and not using DMA. */ +/*! @{ */ #define I2S_FIFORD48HNOPOP_RXDATA_MASK (0xFFFFFFU) #define I2S_FIFORD48HNOPOP_RXDATA_SHIFT (0U) #define I2S_FIFORD48HNOPOP_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFORD48HNOPOP_RXDATA_SHIFT)) & I2S_FIFORD48HNOPOP_RXDATA_MASK) +/*! @} */ /*! @@ -2599,38 +2871,48 @@ typedef struct { */ /*! @name PINTSEL - Pin interrupt select register */ +/*! @{ */ #define INPUTMUX_PINTSEL_INTPIN_MASK (0xFFU) #define INPUTMUX_PINTSEL_INTPIN_SHIFT (0U) #define INPUTMUX_PINTSEL_INTPIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_PINTSEL_INTPIN_SHIFT)) & INPUTMUX_PINTSEL_INTPIN_MASK) +/*! @} */ /* The count of INPUTMUX_PINTSEL */ #define INPUTMUX_PINTSEL_COUNT (8U) /*! @name DMA_ITRIG_INMUX - Trigger select register for DMA channel */ +/*! @{ */ #define INPUTMUX_DMA_ITRIG_INMUX_INP_MASK (0x1FU) #define INPUTMUX_DMA_ITRIG_INMUX_INP_SHIFT (0U) #define INPUTMUX_DMA_ITRIG_INMUX_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA_ITRIG_INMUX_INP_SHIFT)) & INPUTMUX_DMA_ITRIG_INMUX_INP_MASK) +/*! @} */ /* The count of INPUTMUX_DMA_ITRIG_INMUX */ #define INPUTMUX_DMA_ITRIG_INMUX_COUNT (22U) /*! @name DMA_OTRIG_INMUX - DMA output trigger selection to become DMA trigger */ +/*! @{ */ #define INPUTMUX_DMA_OTRIG_INMUX_INP_MASK (0x1FU) #define INPUTMUX_DMA_OTRIG_INMUX_INP_SHIFT (0U) #define INPUTMUX_DMA_OTRIG_INMUX_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA_OTRIG_INMUX_INP_SHIFT)) & INPUTMUX_DMA_OTRIG_INMUX_INP_MASK) +/*! @} */ /* The count of INPUTMUX_DMA_OTRIG_INMUX */ #define INPUTMUX_DMA_OTRIG_INMUX_COUNT (4U) /*! @name FREQMEAS_REF - Selection for frequency measurement reference clock */ +/*! @{ */ #define INPUTMUX_FREQMEAS_REF_CLKIN_MASK (0x1FU) #define INPUTMUX_FREQMEAS_REF_CLKIN_SHIFT (0U) #define INPUTMUX_FREQMEAS_REF_CLKIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FREQMEAS_REF_CLKIN_SHIFT)) & INPUTMUX_FREQMEAS_REF_CLKIN_MASK) +/*! @} */ /*! @name FREQMEAS_TARGET - Selection for frequency measurement target clock */ +/*! @{ */ #define INPUTMUX_FREQMEAS_TARGET_CLKIN_MASK (0x1FU) #define INPUTMUX_FREQMEAS_TARGET_CLKIN_SHIFT (0U) #define INPUTMUX_FREQMEAS_TARGET_CLKIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FREQMEAS_TARGET_CLKIN_SHIFT)) & INPUTMUX_FREQMEAS_TARGET_CLKIN_MASK) +/*! @} */ /*! @@ -2677,6 +2959,7 @@ typedef struct { */ /*! @name PIO - Digital I/O control for port 0 pins PIO0_0..Digital I/O control for port 1 pins PIO1_31 */ +/*! @{ */ #define IOCON_PIO_FUNC_MASK (0x7U) #define IOCON_PIO_FUNC_SHIFT (0U) #define IOCON_PIO_FUNC(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_FUNC_SHIFT)) & IOCON_PIO_FUNC_MASK) @@ -2701,12 +2984,13 @@ typedef struct { #define IOCON_PIO_SLEW_MASK (0x200U) #define IOCON_PIO_SLEW_SHIFT (9U) #define IOCON_PIO_SLEW(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_SLEW_SHIFT)) & IOCON_PIO_SLEW_MASK) -#define IOCON_PIO_OD_MASK (0x400U) -#define IOCON_PIO_OD_SHIFT (10U) -#define IOCON_PIO_OD(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_OD_SHIFT)) & IOCON_PIO_OD_MASK) #define IOCON_PIO_I2CFILTER_MASK (0x400U) #define IOCON_PIO_I2CFILTER_SHIFT (10U) #define IOCON_PIO_I2CFILTER(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_I2CFILTER_SHIFT)) & IOCON_PIO_I2CFILTER_MASK) +#define IOCON_PIO_OD_MASK (0x400U) +#define IOCON_PIO_OD_SHIFT (10U) +#define IOCON_PIO_OD(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_OD_SHIFT)) & IOCON_PIO_OD_MASK) +/*! @} */ /* The count of IOCON_PIO */ #define IOCON_PIO_COUNT (2U) @@ -2766,33 +3050,41 @@ typedef struct { */ /*! @name MBOXIRQ_IRQ - Interrupt request register for the Cortex-M0+ CPU. */ +/*! @{ */ #define MAILBOX_MBOXIRQ_IRQ_INTREQ_MASK (0xFFFFFFFFU) #define MAILBOX_MBOXIRQ_IRQ_INTREQ_SHIFT (0U) #define MAILBOX_MBOXIRQ_IRQ_INTREQ(x) (((uint32_t)(((uint32_t)(x)) << MAILBOX_MBOXIRQ_IRQ_INTREQ_SHIFT)) & MAILBOX_MBOXIRQ_IRQ_INTREQ_MASK) +/*! @} */ /* The count of MAILBOX_MBOXIRQ_IRQ */ #define MAILBOX_MBOXIRQ_IRQ_COUNT (2U) /*! @name MBOXIRQ_IRQSET - Set bits in IRQ0 */ +/*! @{ */ #define MAILBOX_MBOXIRQ_IRQSET_INTREQSET_MASK (0xFFFFFFFFU) #define MAILBOX_MBOXIRQ_IRQSET_INTREQSET_SHIFT (0U) #define MAILBOX_MBOXIRQ_IRQSET_INTREQSET(x) (((uint32_t)(((uint32_t)(x)) << MAILBOX_MBOXIRQ_IRQSET_INTREQSET_SHIFT)) & MAILBOX_MBOXIRQ_IRQSET_INTREQSET_MASK) +/*! @} */ /* The count of MAILBOX_MBOXIRQ_IRQSET */ #define MAILBOX_MBOXIRQ_IRQSET_COUNT (2U) /*! @name MBOXIRQ_IRQCLR - Clear bits in IRQ0 */ +/*! @{ */ #define MAILBOX_MBOXIRQ_IRQCLR_INTREQCLR_MASK (0xFFFFFFFFU) #define MAILBOX_MBOXIRQ_IRQCLR_INTREQCLR_SHIFT (0U) #define MAILBOX_MBOXIRQ_IRQCLR_INTREQCLR(x) (((uint32_t)(((uint32_t)(x)) << MAILBOX_MBOXIRQ_IRQCLR_INTREQCLR_SHIFT)) & MAILBOX_MBOXIRQ_IRQCLR_INTREQCLR_MASK) +/*! @} */ /* The count of MAILBOX_MBOXIRQ_IRQCLR */ #define MAILBOX_MBOXIRQ_IRQCLR_COUNT (2U) /*! @name MUTEX - Mutual exclusion register[1] */ +/*! @{ */ #define MAILBOX_MUTEX_EX_MASK (0x1U) #define MAILBOX_MUTEX_EX_SHIFT (0U) #define MAILBOX_MUTEX_EX(x) (((uint32_t)(((uint32_t)(x)) << MAILBOX_MUTEX_EX_SHIFT)) & MAILBOX_MUTEX_EX_MASK) +/*! @} */ /*! @@ -2850,36 +3142,43 @@ typedef struct { */ /*! @name CHANNEL_INTVAL - MRT Time interval value register. This value is loaded into the TIMER register. */ +/*! @{ */ #define MRT_CHANNEL_INTVAL_IVALUE_MASK (0xFFFFFFU) #define MRT_CHANNEL_INTVAL_IVALUE_SHIFT (0U) #define MRT_CHANNEL_INTVAL_IVALUE(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_INTVAL_IVALUE_SHIFT)) & MRT_CHANNEL_INTVAL_IVALUE_MASK) #define MRT_CHANNEL_INTVAL_LOAD_MASK (0x80000000U) #define MRT_CHANNEL_INTVAL_LOAD_SHIFT (31U) #define MRT_CHANNEL_INTVAL_LOAD(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_INTVAL_LOAD_SHIFT)) & MRT_CHANNEL_INTVAL_LOAD_MASK) +/*! @} */ /* The count of MRT_CHANNEL_INTVAL */ #define MRT_CHANNEL_INTVAL_COUNT (4U) /*! @name CHANNEL_TIMER - MRT Timer register. This register reads the value of the down-counter. */ +/*! @{ */ #define MRT_CHANNEL_TIMER_VALUE_MASK (0xFFFFFFU) #define MRT_CHANNEL_TIMER_VALUE_SHIFT (0U) #define MRT_CHANNEL_TIMER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_TIMER_VALUE_SHIFT)) & MRT_CHANNEL_TIMER_VALUE_MASK) +/*! @} */ /* The count of MRT_CHANNEL_TIMER */ #define MRT_CHANNEL_TIMER_COUNT (4U) /*! @name CHANNEL_CTRL - MRT Control register. This register controls the MRT modes. */ +/*! @{ */ #define MRT_CHANNEL_CTRL_INTEN_MASK (0x1U) #define MRT_CHANNEL_CTRL_INTEN_SHIFT (0U) #define MRT_CHANNEL_CTRL_INTEN(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_CTRL_INTEN_SHIFT)) & MRT_CHANNEL_CTRL_INTEN_MASK) #define MRT_CHANNEL_CTRL_MODE_MASK (0x6U) #define MRT_CHANNEL_CTRL_MODE_SHIFT (1U) #define MRT_CHANNEL_CTRL_MODE(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_CTRL_MODE_SHIFT)) & MRT_CHANNEL_CTRL_MODE_MASK) +/*! @} */ /* The count of MRT_CHANNEL_CTRL */ #define MRT_CHANNEL_CTRL_COUNT (4U) /*! @name CHANNEL_STAT - MRT Status register. */ +/*! @{ */ #define MRT_CHANNEL_STAT_INTFLAG_MASK (0x1U) #define MRT_CHANNEL_STAT_INTFLAG_SHIFT (0U) #define MRT_CHANNEL_STAT_INTFLAG(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_STAT_INTFLAG_SHIFT)) & MRT_CHANNEL_STAT_INTFLAG_MASK) @@ -2889,11 +3188,13 @@ typedef struct { #define MRT_CHANNEL_STAT_INUSE_MASK (0x4U) #define MRT_CHANNEL_STAT_INUSE_SHIFT (2U) #define MRT_CHANNEL_STAT_INUSE(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_STAT_INUSE_SHIFT)) & MRT_CHANNEL_STAT_INUSE_MASK) +/*! @} */ /* The count of MRT_CHANNEL_STAT */ #define MRT_CHANNEL_STAT_COUNT (4U) /*! @name MODCFG - Module Configuration register. This register provides information about this particular MRT instance, and allows choosing an overall mode for the idle channel feature. */ +/*! @{ */ #define MRT_MODCFG_NOC_MASK (0xFU) #define MRT_MODCFG_NOC_SHIFT (0U) #define MRT_MODCFG_NOC(x) (((uint32_t)(((uint32_t)(x)) << MRT_MODCFG_NOC_SHIFT)) & MRT_MODCFG_NOC_MASK) @@ -2903,13 +3204,17 @@ typedef struct { #define MRT_MODCFG_MULTITASK_MASK (0x80000000U) #define MRT_MODCFG_MULTITASK_SHIFT (31U) #define MRT_MODCFG_MULTITASK(x) (((uint32_t)(((uint32_t)(x)) << MRT_MODCFG_MULTITASK_SHIFT)) & MRT_MODCFG_MULTITASK_MASK) +/*! @} */ /*! @name IDLE_CH - Idle channel register. This register returns the number of the first idle channel. */ +/*! @{ */ #define MRT_IDLE_CH_CHAN_MASK (0xF0U) #define MRT_IDLE_CH_CHAN_SHIFT (4U) #define MRT_IDLE_CH_CHAN(x) (((uint32_t)(((uint32_t)(x)) << MRT_IDLE_CH_CHAN_SHIFT)) & MRT_IDLE_CH_CHAN_MASK) +/*! @} */ /*! @name IRQ_FLAG - Global interrupt flag register */ +/*! @{ */ #define MRT_IRQ_FLAG_GFLAG0_MASK (0x1U) #define MRT_IRQ_FLAG_GFLAG0_SHIFT (0U) #define MRT_IRQ_FLAG_GFLAG0(x) (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG0_SHIFT)) & MRT_IRQ_FLAG_GFLAG0_MASK) @@ -2922,6 +3227,7 @@ typedef struct { #define MRT_IRQ_FLAG_GFLAG3_MASK (0x8U) #define MRT_IRQ_FLAG_GFLAG3_SHIFT (3U) #define MRT_IRQ_FLAG_GFLAG3(x) (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG3_SHIFT)) & MRT_IRQ_FLAG_GFLAG3_MASK) +/*! @} */ /*! @@ -2982,56 +3288,77 @@ typedef struct { */ /*! @name ISEL - Pin Interrupt Mode register */ +/*! @{ */ #define PINT_ISEL_PMODE_MASK (0xFFU) #define PINT_ISEL_PMODE_SHIFT (0U) #define PINT_ISEL_PMODE(x) (((uint32_t)(((uint32_t)(x)) << PINT_ISEL_PMODE_SHIFT)) & PINT_ISEL_PMODE_MASK) +/*! @} */ /*! @name IENR - Pin interrupt level or rising edge interrupt enable register */ +/*! @{ */ #define PINT_IENR_ENRL_MASK (0xFFU) #define PINT_IENR_ENRL_SHIFT (0U) #define PINT_IENR_ENRL(x) (((uint32_t)(((uint32_t)(x)) << PINT_IENR_ENRL_SHIFT)) & PINT_IENR_ENRL_MASK) +/*! @} */ /*! @name SIENR - Pin interrupt level or rising edge interrupt set register */ +/*! @{ */ #define PINT_SIENR_SETENRL_MASK (0xFFU) #define PINT_SIENR_SETENRL_SHIFT (0U) #define PINT_SIENR_SETENRL(x) (((uint32_t)(((uint32_t)(x)) << PINT_SIENR_SETENRL_SHIFT)) & PINT_SIENR_SETENRL_MASK) +/*! @} */ /*! @name CIENR - Pin interrupt level (rising edge interrupt) clear register */ +/*! @{ */ #define PINT_CIENR_CENRL_MASK (0xFFU) #define PINT_CIENR_CENRL_SHIFT (0U) #define PINT_CIENR_CENRL(x) (((uint32_t)(((uint32_t)(x)) << PINT_CIENR_CENRL_SHIFT)) & PINT_CIENR_CENRL_MASK) +/*! @} */ /*! @name IENF - Pin interrupt active level or falling edge interrupt enable register */ +/*! @{ */ #define PINT_IENF_ENAF_MASK (0xFFU) #define PINT_IENF_ENAF_SHIFT (0U) #define PINT_IENF_ENAF(x) (((uint32_t)(((uint32_t)(x)) << PINT_IENF_ENAF_SHIFT)) & PINT_IENF_ENAF_MASK) +/*! @} */ /*! @name SIENF - Pin interrupt active level or falling edge interrupt set register */ +/*! @{ */ #define PINT_SIENF_SETENAF_MASK (0xFFU) #define PINT_SIENF_SETENAF_SHIFT (0U) #define PINT_SIENF_SETENAF(x) (((uint32_t)(((uint32_t)(x)) << PINT_SIENF_SETENAF_SHIFT)) & PINT_SIENF_SETENAF_MASK) +/*! @} */ /*! @name CIENF - Pin interrupt active level or falling edge interrupt clear register */ +/*! @{ */ #define PINT_CIENF_CENAF_MASK (0xFFU) #define PINT_CIENF_CENAF_SHIFT (0U) #define PINT_CIENF_CENAF(x) (((uint32_t)(((uint32_t)(x)) << PINT_CIENF_CENAF_SHIFT)) & PINT_CIENF_CENAF_MASK) +/*! @} */ /*! @name RISE - Pin interrupt rising edge register */ +/*! @{ */ #define PINT_RISE_RDET_MASK (0xFFU) #define PINT_RISE_RDET_SHIFT (0U) #define PINT_RISE_RDET(x) (((uint32_t)(((uint32_t)(x)) << PINT_RISE_RDET_SHIFT)) & PINT_RISE_RDET_MASK) +/*! @} */ /*! @name FALL - Pin interrupt falling edge register */ +/*! @{ */ #define PINT_FALL_FDET_MASK (0xFFU) #define PINT_FALL_FDET_SHIFT (0U) #define PINT_FALL_FDET(x) (((uint32_t)(((uint32_t)(x)) << PINT_FALL_FDET_SHIFT)) & PINT_FALL_FDET_MASK) +/*! @} */ /*! @name IST - Pin interrupt status register */ +/*! @{ */ #define PINT_IST_PSTAT_MASK (0xFFU) #define PINT_IST_PSTAT_SHIFT (0U) #define PINT_IST_PSTAT(x) (((uint32_t)(((uint32_t)(x)) << PINT_IST_PSTAT_SHIFT)) & PINT_IST_PSTAT_MASK) +/*! @} */ /*! @name PMCTRL - Pattern match interrupt control register */ +/*! @{ */ #define PINT_PMCTRL_SEL_PMATCH_MASK (0x1U) #define PINT_PMCTRL_SEL_PMATCH_SHIFT (0U) #define PINT_PMCTRL_SEL_PMATCH(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCTRL_SEL_PMATCH_SHIFT)) & PINT_PMCTRL_SEL_PMATCH_MASK) @@ -3041,8 +3368,10 @@ typedef struct { #define PINT_PMCTRL_PMAT_MASK (0xFF000000U) #define PINT_PMCTRL_PMAT_SHIFT (24U) #define PINT_PMCTRL_PMAT(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCTRL_PMAT_SHIFT)) & PINT_PMCTRL_PMAT_MASK) +/*! @} */ /*! @name PMSRC - Pattern match interrupt bit-slice source register */ +/*! @{ */ #define PINT_PMSRC_SRC0_MASK (0x700U) #define PINT_PMSRC_SRC0_SHIFT (8U) #define PINT_PMSRC_SRC0(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC0_SHIFT)) & PINT_PMSRC_SRC0_MASK) @@ -3067,8 +3396,10 @@ typedef struct { #define PINT_PMSRC_SRC7_MASK (0xE0000000U) #define PINT_PMSRC_SRC7_SHIFT (29U) #define PINT_PMSRC_SRC7(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC7_SHIFT)) & PINT_PMSRC_SRC7_MASK) +/*! @} */ /*! @name PMCFG - Pattern match interrupt bit slice configuration register */ +/*! @{ */ #define PINT_PMCFG_PROD_ENDPTS0_MASK (0x1U) #define PINT_PMCFG_PROD_ENDPTS0_SHIFT (0U) #define PINT_PMCFG_PROD_ENDPTS0(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS0_SHIFT)) & PINT_PMCFG_PROD_ENDPTS0_MASK) @@ -3114,6 +3445,7 @@ typedef struct { #define PINT_PMCFG_CFG7_MASK (0xE0000000U) #define PINT_PMCFG_CFG7_SHIFT (29U) #define PINT_PMCFG_CFG7(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG7_SHIFT)) & PINT_PMCFG_CFG7_MASK) +/*! @} */ /*! @@ -3165,6 +3497,7 @@ typedef struct { */ /*! @name CTRL - RTC control register */ +/*! @{ */ #define RTC_CTRL_SWRESET_MASK (0x1U) #define RTC_CTRL_SWRESET_SHIFT (0U) #define RTC_CTRL_SWRESET(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_SWRESET_SHIFT)) & RTC_CTRL_SWRESET_MASK) @@ -3192,21 +3525,28 @@ typedef struct { #define RTC_CTRL_RTC_OSC_BYPASS_MASK (0x200U) #define RTC_CTRL_RTC_OSC_BYPASS_SHIFT (9U) #define RTC_CTRL_RTC_OSC_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_RTC_OSC_BYPASS_SHIFT)) & RTC_CTRL_RTC_OSC_BYPASS_MASK) +/*! @} */ /*! @name MATCH - RTC match register */ +/*! @{ */ #define RTC_MATCH_MATVAL_MASK (0xFFFFFFFFU) #define RTC_MATCH_MATVAL_SHIFT (0U) #define RTC_MATCH_MATVAL(x) (((uint32_t)(((uint32_t)(x)) << RTC_MATCH_MATVAL_SHIFT)) & RTC_MATCH_MATVAL_MASK) +/*! @} */ /*! @name COUNT - RTC counter register */ +/*! @{ */ #define RTC_COUNT_VAL_MASK (0xFFFFFFFFU) #define RTC_COUNT_VAL_SHIFT (0U) #define RTC_COUNT_VAL(x) (((uint32_t)(((uint32_t)(x)) << RTC_COUNT_VAL_SHIFT)) & RTC_COUNT_VAL_MASK) +/*! @} */ /*! @name WAKE - High-resolution/wake-up timer control register */ +/*! @{ */ #define RTC_WAKE_VAL_MASK (0xFFFFU) #define RTC_WAKE_VAL_SHIFT (0U) #define RTC_WAKE_VAL(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAKE_VAL_SHIFT)) & RTC_WAKE_VAL_MASK) +/*! @} */ /*! @@ -3283,7 +3623,7 @@ typedef struct { __IO uint32_t CLR; /**< SCT output 0 clear register, array offset: 0x504, array step: 0x8 */ } OUT[8]; uint8_t RESERVED_5[700]; - __IO uint32_t MODULECONTENT; /**< Reserved, offset: 0x7FC */ + uint32_t MODULECONTENT; /**< Reserved, offset: 0x7FC */ } SCT_Type; /* ---------------------------------------------------------------------------- @@ -3296,6 +3636,7 @@ typedef struct { */ /*! @name CONFIG - SCT configuration register */ +/*! @{ */ #define SCT_CONFIG_UNIFY_MASK (0x1U) #define SCT_CONFIG_UNIFY_SHIFT (0U) #define SCT_CONFIG_UNIFY(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_UNIFY_SHIFT)) & SCT_CONFIG_UNIFY_MASK) @@ -3320,8 +3661,10 @@ typedef struct { #define SCT_CONFIG_AUTOLIMIT_H_MASK (0x40000U) #define SCT_CONFIG_AUTOLIMIT_H_SHIFT (18U) #define SCT_CONFIG_AUTOLIMIT_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_AUTOLIMIT_H_SHIFT)) & SCT_CONFIG_AUTOLIMIT_H_MASK) +/*! @} */ /*! @name CTRL - SCT control register */ +/*! @{ */ #define SCT_CTRL_DOWN_L_MASK (0x1U) #define SCT_CTRL_DOWN_L_SHIFT (0U) #define SCT_CTRL_DOWN_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_DOWN_L_SHIFT)) & SCT_CTRL_DOWN_L_MASK) @@ -3358,56 +3701,70 @@ typedef struct { #define SCT_CTRL_PRE_H_MASK (0x1FE00000U) #define SCT_CTRL_PRE_H_SHIFT (21U) #define SCT_CTRL_PRE_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_PRE_H_SHIFT)) & SCT_CTRL_PRE_H_MASK) +/*! @} */ /*! @name LIMIT - SCT limit event select register */ +/*! @{ */ #define SCT_LIMIT_LIMMSK_L_MASK (0xFFFFU) #define SCT_LIMIT_LIMMSK_L_SHIFT (0U) #define SCT_LIMIT_LIMMSK_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_LIMIT_LIMMSK_L_SHIFT)) & SCT_LIMIT_LIMMSK_L_MASK) #define SCT_LIMIT_LIMMSK_H_MASK (0xFFFF0000U) #define SCT_LIMIT_LIMMSK_H_SHIFT (16U) #define SCT_LIMIT_LIMMSK_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_LIMIT_LIMMSK_H_SHIFT)) & SCT_LIMIT_LIMMSK_H_MASK) +/*! @} */ /*! @name HALT - SCT halt event select register */ +/*! @{ */ #define SCT_HALT_HALTMSK_L_MASK (0xFFFFU) #define SCT_HALT_HALTMSK_L_SHIFT (0U) #define SCT_HALT_HALTMSK_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_HALT_HALTMSK_L_SHIFT)) & SCT_HALT_HALTMSK_L_MASK) #define SCT_HALT_HALTMSK_H_MASK (0xFFFF0000U) #define SCT_HALT_HALTMSK_H_SHIFT (16U) #define SCT_HALT_HALTMSK_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_HALT_HALTMSK_H_SHIFT)) & SCT_HALT_HALTMSK_H_MASK) +/*! @} */ /*! @name STOP - SCT stop event select register */ +/*! @{ */ #define SCT_STOP_STOPMSK_L_MASK (0xFFFFU) #define SCT_STOP_STOPMSK_L_SHIFT (0U) #define SCT_STOP_STOPMSK_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_STOP_STOPMSK_L_SHIFT)) & SCT_STOP_STOPMSK_L_MASK) #define SCT_STOP_STOPMSK_H_MASK (0xFFFF0000U) #define SCT_STOP_STOPMSK_H_SHIFT (16U) #define SCT_STOP_STOPMSK_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_STOP_STOPMSK_H_SHIFT)) & SCT_STOP_STOPMSK_H_MASK) +/*! @} */ /*! @name START - SCT start event select register */ +/*! @{ */ #define SCT_START_STARTMSK_L_MASK (0xFFFFU) #define SCT_START_STARTMSK_L_SHIFT (0U) #define SCT_START_STARTMSK_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_START_STARTMSK_L_SHIFT)) & SCT_START_STARTMSK_L_MASK) #define SCT_START_STARTMSK_H_MASK (0xFFFF0000U) #define SCT_START_STARTMSK_H_SHIFT (16U) #define SCT_START_STARTMSK_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_START_STARTMSK_H_SHIFT)) & SCT_START_STARTMSK_H_MASK) +/*! @} */ /*! @name COUNT - SCT counter register */ +/*! @{ */ #define SCT_COUNT_CTR_L_MASK (0xFFFFU) #define SCT_COUNT_CTR_L_SHIFT (0U) #define SCT_COUNT_CTR_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_COUNT_CTR_L_SHIFT)) & SCT_COUNT_CTR_L_MASK) #define SCT_COUNT_CTR_H_MASK (0xFFFF0000U) #define SCT_COUNT_CTR_H_SHIFT (16U) #define SCT_COUNT_CTR_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_COUNT_CTR_H_SHIFT)) & SCT_COUNT_CTR_H_MASK) +/*! @} */ /*! @name STATE - SCT state register */ +/*! @{ */ #define SCT_STATE_STATE_L_MASK (0x1FU) #define SCT_STATE_STATE_L_SHIFT (0U) #define SCT_STATE_STATE_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_STATE_STATE_L_SHIFT)) & SCT_STATE_STATE_L_MASK) #define SCT_STATE_STATE_H_MASK (0x1F0000U) #define SCT_STATE_STATE_H_SHIFT (16U) #define SCT_STATE_STATE_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_STATE_STATE_H_SHIFT)) & SCT_STATE_STATE_H_MASK) +/*! @} */ /*! @name INPUT - SCT input register */ +/*! @{ */ #define SCT_INPUT_AIN0_MASK (0x1U) #define SCT_INPUT_AIN0_SHIFT (0U) #define SCT_INPUT_AIN0(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN0_SHIFT)) & SCT_INPUT_AIN0_MASK) @@ -3504,21 +3861,27 @@ typedef struct { #define SCT_INPUT_SIN15_MASK (0x80000000U) #define SCT_INPUT_SIN15_SHIFT (31U) #define SCT_INPUT_SIN15(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN15_SHIFT)) & SCT_INPUT_SIN15_MASK) +/*! @} */ /*! @name REGMODE - SCT match/capture mode register */ +/*! @{ */ #define SCT_REGMODE_REGMOD_L_MASK (0xFFFFU) #define SCT_REGMODE_REGMOD_L_SHIFT (0U) #define SCT_REGMODE_REGMOD_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_L_SHIFT)) & SCT_REGMODE_REGMOD_L_MASK) #define SCT_REGMODE_REGMOD_H_MASK (0xFFFF0000U) #define SCT_REGMODE_REGMOD_H_SHIFT (16U) #define SCT_REGMODE_REGMOD_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_H_SHIFT)) & SCT_REGMODE_REGMOD_H_MASK) +/*! @} */ /*! @name OUTPUT - SCT output register */ +/*! @{ */ #define SCT_OUTPUT_OUT_MASK (0xFFFFU) #define SCT_OUTPUT_OUT_SHIFT (0U) #define SCT_OUTPUT_OUT(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUT_OUT_SHIFT)) & SCT_OUTPUT_OUT_MASK) +/*! @} */ /*! @name OUTPUTDIRCTRL - SCT output counter direction control register */ +/*! @{ */ #define SCT_OUTPUTDIRCTRL_SETCLR0_MASK (0x3U) #define SCT_OUTPUTDIRCTRL_SETCLR0_SHIFT (0U) #define SCT_OUTPUTDIRCTRL_SETCLR0(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR0_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR0_MASK) @@ -3567,8 +3930,10 @@ typedef struct { #define SCT_OUTPUTDIRCTRL_SETCLR15_MASK (0xC0000000U) #define SCT_OUTPUTDIRCTRL_SETCLR15_SHIFT (30U) #define SCT_OUTPUTDIRCTRL_SETCLR15(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR15_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR15_MASK) +/*! @} */ /*! @name RES - SCT conflict resolution register */ +/*! @{ */ #define SCT_RES_O0RES_MASK (0x3U) #define SCT_RES_O0RES_SHIFT (0U) #define SCT_RES_O0RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O0RES_SHIFT)) & SCT_RES_O0RES_MASK) @@ -3617,8 +3982,10 @@ typedef struct { #define SCT_RES_O15RES_MASK (0xC0000000U) #define SCT_RES_O15RES_SHIFT (30U) #define SCT_RES_O15RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O15RES_SHIFT)) & SCT_RES_O15RES_MASK) +/*! @} */ /*! @name DMA0REQUEST - SCT DMA request 0 register */ +/*! @{ */ #define SCT_DMA0REQUEST_DEV_0_MASK (0xFFFFU) #define SCT_DMA0REQUEST_DEV_0_SHIFT (0U) #define SCT_DMA0REQUEST_DEV_0(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMA0REQUEST_DEV_0_SHIFT)) & SCT_DMA0REQUEST_DEV_0_MASK) @@ -3628,8 +3995,10 @@ typedef struct { #define SCT_DMA0REQUEST_DRQ0_MASK (0x80000000U) #define SCT_DMA0REQUEST_DRQ0_SHIFT (31U) #define SCT_DMA0REQUEST_DRQ0(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMA0REQUEST_DRQ0_SHIFT)) & SCT_DMA0REQUEST_DRQ0_MASK) +/*! @} */ /*! @name DMA1REQUEST - SCT DMA request 1 register */ +/*! @{ */ #define SCT_DMA1REQUEST_DEV_1_MASK (0xFFFFU) #define SCT_DMA1REQUEST_DEV_1_SHIFT (0U) #define SCT_DMA1REQUEST_DEV_1(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMA1REQUEST_DEV_1_SHIFT)) & SCT_DMA1REQUEST_DEV_1_MASK) @@ -3639,23 +4008,31 @@ typedef struct { #define SCT_DMA1REQUEST_DRQ1_MASK (0x80000000U) #define SCT_DMA1REQUEST_DRQ1_SHIFT (31U) #define SCT_DMA1REQUEST_DRQ1(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMA1REQUEST_DRQ1_SHIFT)) & SCT_DMA1REQUEST_DRQ1_MASK) +/*! @} */ /*! @name EVEN - SCT event interrupt enable register */ +/*! @{ */ #define SCT_EVEN_IEN_MASK (0xFFFFU) #define SCT_EVEN_IEN_SHIFT (0U) #define SCT_EVEN_IEN(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVEN_IEN_SHIFT)) & SCT_EVEN_IEN_MASK) +/*! @} */ /*! @name EVFLAG - SCT event flag register */ +/*! @{ */ #define SCT_EVFLAG_FLAG_MASK (0xFFFFU) #define SCT_EVFLAG_FLAG_SHIFT (0U) #define SCT_EVFLAG_FLAG(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVFLAG_FLAG_SHIFT)) & SCT_EVFLAG_FLAG_MASK) +/*! @} */ /*! @name CONEN - SCT conflict interrupt enable register */ +/*! @{ */ #define SCT_CONEN_NCEN_MASK (0xFFFFU) #define SCT_CONEN_NCEN_SHIFT (0U) #define SCT_CONEN_NCEN(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONEN_NCEN_SHIFT)) & SCT_CONEN_NCEN_MASK) +/*! @} */ /*! @name CONFLAG - SCT conflict flag register */ +/*! @{ */ #define SCT_CONFLAG_NCFLAG_MASK (0xFFFFU) #define SCT_CONFLAG_NCFLAG_SHIFT (0U) #define SCT_CONFLAG_NCFLAG(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_NCFLAG_SHIFT)) & SCT_CONFLAG_NCFLAG_MASK) @@ -3665,60 +4042,72 @@ typedef struct { #define SCT_CONFLAG_BUSERRH_MASK (0x80000000U) #define SCT_CONFLAG_BUSERRH_SHIFT (31U) #define SCT_CONFLAG_BUSERRH(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_BUSERRH_SHIFT)) & SCT_CONFLAG_BUSERRH_MASK) +/*! @} */ /*! @name SCTCAP - SCT capture register of capture channel */ +/*! @{ */ #define SCT_SCTCAP_CAPn_L_MASK (0xFFFFU) #define SCT_SCTCAP_CAPn_L_SHIFT (0U) #define SCT_SCTCAP_CAPn_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_SCTCAP_CAPn_L_SHIFT)) & SCT_SCTCAP_CAPn_L_MASK) #define SCT_SCTCAP_CAPn_H_MASK (0xFFFF0000U) #define SCT_SCTCAP_CAPn_H_SHIFT (16U) #define SCT_SCTCAP_CAPn_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_SCTCAP_CAPn_H_SHIFT)) & SCT_SCTCAP_CAPn_H_MASK) +/*! @} */ /* The count of SCT_SCTCAP */ #define SCT_SCTCAP_COUNT (10U) /*! @name SCTMATCH - SCT match value register of match channels */ +/*! @{ */ #define SCT_SCTMATCH_MATCHn_L_MASK (0xFFFFU) #define SCT_SCTMATCH_MATCHn_L_SHIFT (0U) #define SCT_SCTMATCH_MATCHn_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_SCTMATCH_MATCHn_L_SHIFT)) & SCT_SCTMATCH_MATCHn_L_MASK) #define SCT_SCTMATCH_MATCHn_H_MASK (0xFFFF0000U) #define SCT_SCTMATCH_MATCHn_H_SHIFT (16U) #define SCT_SCTMATCH_MATCHn_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_SCTMATCH_MATCHn_H_SHIFT)) & SCT_SCTMATCH_MATCHn_H_MASK) +/*! @} */ /* The count of SCT_SCTMATCH */ #define SCT_SCTMATCH_COUNT (10U) /*! @name SCTCAPCTRL - SCT capture control register */ +/*! @{ */ #define SCT_SCTCAPCTRL_CAPCONn_L_MASK (0xFFFFU) #define SCT_SCTCAPCTRL_CAPCONn_L_SHIFT (0U) #define SCT_SCTCAPCTRL_CAPCONn_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_SCTCAPCTRL_CAPCONn_L_SHIFT)) & SCT_SCTCAPCTRL_CAPCONn_L_MASK) #define SCT_SCTCAPCTRL_CAPCONn_H_MASK (0xFFFF0000U) #define SCT_SCTCAPCTRL_CAPCONn_H_SHIFT (16U) #define SCT_SCTCAPCTRL_CAPCONn_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_SCTCAPCTRL_CAPCONn_H_SHIFT)) & SCT_SCTCAPCTRL_CAPCONn_H_MASK) +/*! @} */ /* The count of SCT_SCTCAPCTRL */ #define SCT_SCTCAPCTRL_COUNT (10U) /*! @name SCTMATCHREL - SCT match reload value register */ +/*! @{ */ #define SCT_SCTMATCHREL_RELOADn_L_MASK (0xFFFFU) #define SCT_SCTMATCHREL_RELOADn_L_SHIFT (0U) #define SCT_SCTMATCHREL_RELOADn_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_SCTMATCHREL_RELOADn_L_SHIFT)) & SCT_SCTMATCHREL_RELOADn_L_MASK) #define SCT_SCTMATCHREL_RELOADn_H_MASK (0xFFFF0000U) #define SCT_SCTMATCHREL_RELOADn_H_SHIFT (16U) #define SCT_SCTMATCHREL_RELOADn_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_SCTMATCHREL_RELOADn_H_SHIFT)) & SCT_SCTMATCHREL_RELOADn_H_MASK) +/*! @} */ /* The count of SCT_SCTMATCHREL */ #define SCT_SCTMATCHREL_COUNT (10U) /*! @name EVENT_STATE - SCT event state register 0 */ +/*! @{ */ #define SCT_EVENT_STATE_STATEMSKn_MASK (0xFFFFU) #define SCT_EVENT_STATE_STATEMSKn_SHIFT (0U) #define SCT_EVENT_STATE_STATEMSKn(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_STATE_STATEMSKn_SHIFT)) & SCT_EVENT_STATE_STATEMSKn_MASK) +/*! @} */ /* The count of SCT_EVENT_STATE */ #define SCT_EVENT_STATE_COUNT (10U) /*! @name EVENT_CTRL - SCT event control register 0 */ +/*! @{ */ #define SCT_EVENT_CTRL_MATCHSEL_MASK (0xFU) #define SCT_EVENT_CTRL_MATCHSEL_SHIFT (0U) #define SCT_EVENT_CTRL_MATCHSEL(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_MATCHSEL_SHIFT)) & SCT_EVENT_CTRL_MATCHSEL_MASK) @@ -3749,22 +4138,27 @@ typedef struct { #define SCT_EVENT_CTRL_DIRECTION_MASK (0x600000U) #define SCT_EVENT_CTRL_DIRECTION_SHIFT (21U) #define SCT_EVENT_CTRL_DIRECTION(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_DIRECTION_SHIFT)) & SCT_EVENT_CTRL_DIRECTION_MASK) +/*! @} */ /* The count of SCT_EVENT_CTRL */ #define SCT_EVENT_CTRL_COUNT (10U) /*! @name OUT_SET - SCT output 0 set register */ +/*! @{ */ #define SCT_OUT_SET_SET_MASK (0xFFFFU) #define SCT_OUT_SET_SET_SHIFT (0U) #define SCT_OUT_SET_SET(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUT_SET_SET_SHIFT)) & SCT_OUT_SET_SET_MASK) +/*! @} */ /* The count of SCT_OUT_SET */ #define SCT_OUT_SET_COUNT (8U) /*! @name OUT_CLR - SCT output 0 clear register */ +/*! @{ */ #define SCT_OUT_CLR_CLR_MASK (0xFFFFU) #define SCT_OUT_CLR_CLR_SHIFT (0U) #define SCT_OUT_CLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUT_CLR_CLR_SHIFT)) & SCT_OUT_CLR_CLR_MASK) +/*! @} */ /* The count of SCT_OUT_CLR */ #define SCT_OUT_CLR_COUNT (8U) @@ -3838,6 +4232,7 @@ typedef struct { */ /*! @name CFG - SPI Configuration register */ +/*! @{ */ #define SPI_CFG_ENABLE_MASK (0x1U) #define SPI_CFG_ENABLE_SHIFT (0U) #define SPI_CFG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_ENABLE_SHIFT)) & SPI_CFG_ENABLE_MASK) @@ -3868,8 +4263,10 @@ typedef struct { #define SPI_CFG_SPOL3_MASK (0x800U) #define SPI_CFG_SPOL3_SHIFT (11U) #define SPI_CFG_SPOL3(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL3_SHIFT)) & SPI_CFG_SPOL3_MASK) +/*! @} */ /*! @name DLY - SPI Delay register */ +/*! @{ */ #define SPI_DLY_PRE_DELAY_MASK (0xFU) #define SPI_DLY_PRE_DELAY_SHIFT (0U) #define SPI_DLY_PRE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SPI_DLY_PRE_DELAY_SHIFT)) & SPI_DLY_PRE_DELAY_MASK) @@ -3882,8 +4279,10 @@ typedef struct { #define SPI_DLY_TRANSFER_DELAY_MASK (0xF000U) #define SPI_DLY_TRANSFER_DELAY_SHIFT (12U) #define SPI_DLY_TRANSFER_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SPI_DLY_TRANSFER_DELAY_SHIFT)) & SPI_DLY_TRANSFER_DELAY_MASK) +/*! @} */ /*! @name STAT - SPI Status. Some status flags can be cleared by writing a 1 to that bit position. */ +/*! @{ */ #define SPI_STAT_SSA_MASK (0x10U) #define SPI_STAT_SSA_SHIFT (4U) #define SPI_STAT_SSA(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_SSA_SHIFT)) & SPI_STAT_SSA_MASK) @@ -3899,8 +4298,10 @@ typedef struct { #define SPI_STAT_MSTIDLE_MASK (0x100U) #define SPI_STAT_MSTIDLE_SHIFT (8U) #define SPI_STAT_MSTIDLE(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_MSTIDLE_SHIFT)) & SPI_STAT_MSTIDLE_MASK) +/*! @} */ /*! @name INTENSET - SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set. */ +/*! @{ */ #define SPI_INTENSET_SSAEN_MASK (0x10U) #define SPI_INTENSET_SSAEN_SHIFT (4U) #define SPI_INTENSET_SSAEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENSET_SSAEN_SHIFT)) & SPI_INTENSET_SSAEN_MASK) @@ -3910,8 +4311,10 @@ typedef struct { #define SPI_INTENSET_MSTIDLEEN_MASK (0x100U) #define SPI_INTENSET_MSTIDLEEN_SHIFT (8U) #define SPI_INTENSET_MSTIDLEEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENSET_MSTIDLEEN_SHIFT)) & SPI_INTENSET_MSTIDLEEN_MASK) +/*! @} */ /*! @name INTENCLR - SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared. */ +/*! @{ */ #define SPI_INTENCLR_SSAEN_MASK (0x10U) #define SPI_INTENCLR_SSAEN_SHIFT (4U) #define SPI_INTENCLR_SSAEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENCLR_SSAEN_SHIFT)) & SPI_INTENCLR_SSAEN_MASK) @@ -3921,13 +4324,17 @@ typedef struct { #define SPI_INTENCLR_MSTIDLE_MASK (0x100U) #define SPI_INTENCLR_MSTIDLE_SHIFT (8U) #define SPI_INTENCLR_MSTIDLE(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENCLR_MSTIDLE_SHIFT)) & SPI_INTENCLR_MSTIDLE_MASK) +/*! @} */ /*! @name DIV - SPI clock Divider */ +/*! @{ */ #define SPI_DIV_DIVVAL_MASK (0xFFFFU) #define SPI_DIV_DIVVAL_SHIFT (0U) #define SPI_DIV_DIVVAL(x) (((uint32_t)(((uint32_t)(x)) << SPI_DIV_DIVVAL_SHIFT)) & SPI_DIV_DIVVAL_MASK) +/*! @} */ /*! @name INTSTAT - SPI Interrupt Status */ +/*! @{ */ #define SPI_INTSTAT_SSA_MASK (0x10U) #define SPI_INTSTAT_SSA_SHIFT (4U) #define SPI_INTSTAT_SSA(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTSTAT_SSA_SHIFT)) & SPI_INTSTAT_SSA_MASK) @@ -3937,8 +4344,10 @@ typedef struct { #define SPI_INTSTAT_MSTIDLE_MASK (0x100U) #define SPI_INTSTAT_MSTIDLE_SHIFT (8U) #define SPI_INTSTAT_MSTIDLE(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTSTAT_MSTIDLE_SHIFT)) & SPI_INTSTAT_MSTIDLE_MASK) +/*! @} */ /*! @name FIFOCFG - FIFO configuration and enable register. */ +/*! @{ */ #define SPI_FIFOCFG_ENABLETX_MASK (0x1U) #define SPI_FIFOCFG_ENABLETX_SHIFT (0U) #define SPI_FIFOCFG_ENABLETX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_ENABLETX_SHIFT)) & SPI_FIFOCFG_ENABLETX_MASK) @@ -3966,8 +4375,10 @@ typedef struct { #define SPI_FIFOCFG_EMPTYRX_MASK (0x20000U) #define SPI_FIFOCFG_EMPTYRX_SHIFT (17U) #define SPI_FIFOCFG_EMPTYRX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_EMPTYRX_SHIFT)) & SPI_FIFOCFG_EMPTYRX_MASK) +/*! @} */ /*! @name FIFOSTAT - FIFO status register. */ +/*! @{ */ #define SPI_FIFOSTAT_TXERR_MASK (0x1U) #define SPI_FIFOSTAT_TXERR_SHIFT (0U) #define SPI_FIFOSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_TXERR_SHIFT)) & SPI_FIFOSTAT_TXERR_MASK) @@ -3995,8 +4406,10 @@ typedef struct { #define SPI_FIFOSTAT_RXLVL_MASK (0x1F0000U) #define SPI_FIFOSTAT_RXLVL_SHIFT (16U) #define SPI_FIFOSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_RXLVL_SHIFT)) & SPI_FIFOSTAT_RXLVL_MASK) +/*! @} */ /*! @name FIFOTRIG - FIFO trigger settings for interrupt and DMA request. */ +/*! @{ */ #define SPI_FIFOTRIG_TXLVLENA_MASK (0x1U) #define SPI_FIFOTRIG_TXLVLENA_SHIFT (0U) #define SPI_FIFOTRIG_TXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOTRIG_TXLVLENA_SHIFT)) & SPI_FIFOTRIG_TXLVLENA_MASK) @@ -4009,8 +4422,10 @@ typedef struct { #define SPI_FIFOTRIG_RXLVL_MASK (0xF0000U) #define SPI_FIFOTRIG_RXLVL_SHIFT (16U) #define SPI_FIFOTRIG_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOTRIG_RXLVL_SHIFT)) & SPI_FIFOTRIG_RXLVL_MASK) +/*! @} */ /*! @name FIFOINTENSET - FIFO interrupt enable set (enable) and read register. */ +/*! @{ */ #define SPI_FIFOINTENSET_TXERR_MASK (0x1U) #define SPI_FIFOINTENSET_TXERR_SHIFT (0U) #define SPI_FIFOINTENSET_TXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENSET_TXERR_SHIFT)) & SPI_FIFOINTENSET_TXERR_MASK) @@ -4023,8 +4438,10 @@ typedef struct { #define SPI_FIFOINTENSET_RXLVL_MASK (0x8U) #define SPI_FIFOINTENSET_RXLVL_SHIFT (3U) #define SPI_FIFOINTENSET_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENSET_RXLVL_SHIFT)) & SPI_FIFOINTENSET_RXLVL_MASK) +/*! @} */ /*! @name FIFOINTENCLR - FIFO interrupt enable clear (disable) and read register. */ +/*! @{ */ #define SPI_FIFOINTENCLR_TXERR_MASK (0x1U) #define SPI_FIFOINTENCLR_TXERR_SHIFT (0U) #define SPI_FIFOINTENCLR_TXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENCLR_TXERR_SHIFT)) & SPI_FIFOINTENCLR_TXERR_MASK) @@ -4037,8 +4454,10 @@ typedef struct { #define SPI_FIFOINTENCLR_RXLVL_MASK (0x8U) #define SPI_FIFOINTENCLR_RXLVL_SHIFT (3U) #define SPI_FIFOINTENCLR_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENCLR_RXLVL_SHIFT)) & SPI_FIFOINTENCLR_RXLVL_MASK) +/*! @} */ /*! @name FIFOINTSTAT - FIFO interrupt status register. */ +/*! @{ */ #define SPI_FIFOINTSTAT_TXERR_MASK (0x1U) #define SPI_FIFOINTSTAT_TXERR_SHIFT (0U) #define SPI_FIFOINTSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_TXERR_SHIFT)) & SPI_FIFOINTSTAT_TXERR_MASK) @@ -4054,8 +4473,10 @@ typedef struct { #define SPI_FIFOINTSTAT_PERINT_MASK (0x10U) #define SPI_FIFOINTSTAT_PERINT_SHIFT (4U) #define SPI_FIFOINTSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_PERINT_SHIFT)) & SPI_FIFOINTSTAT_PERINT_MASK) +/*! @} */ /*! @name FIFOWR - FIFO write data. */ +/*! @{ */ #define SPI_FIFOWR_TXDATA_MASK (0xFFFFU) #define SPI_FIFOWR_TXDATA_SHIFT (0U) #define SPI_FIFOWR_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXDATA_SHIFT)) & SPI_FIFOWR_TXDATA_MASK) @@ -4083,8 +4504,10 @@ typedef struct { #define SPI_FIFOWR_LEN_MASK (0xF000000U) #define SPI_FIFOWR_LEN_SHIFT (24U) #define SPI_FIFOWR_LEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_LEN_SHIFT)) & SPI_FIFOWR_LEN_MASK) +/*! @} */ /*! @name FIFORD - FIFO read data. */ +/*! @{ */ #define SPI_FIFORD_RXDATA_MASK (0xFFFFU) #define SPI_FIFORD_RXDATA_SHIFT (0U) #define SPI_FIFORD_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXDATA_SHIFT)) & SPI_FIFORD_RXDATA_MASK) @@ -4103,8 +4526,10 @@ typedef struct { #define SPI_FIFORD_SOT_MASK (0x100000U) #define SPI_FIFORD_SOT_SHIFT (20U) #define SPI_FIFORD_SOT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_SOT_SHIFT)) & SPI_FIFORD_SOT_MASK) +/*! @} */ /*! @name FIFORDNOPOP - FIFO data read with no FIFO pop. */ +/*! @{ */ #define SPI_FIFORDNOPOP_RXDATA_MASK (0xFFFFU) #define SPI_FIFORDNOPOP_RXDATA_SHIFT (0U) #define SPI_FIFORDNOPOP_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXDATA_SHIFT)) & SPI_FIFORDNOPOP_RXDATA_MASK) @@ -4123,6 +4548,7 @@ typedef struct { #define SPI_FIFORDNOPOP_SOT_MASK (0x100000U) #define SPI_FIFORDNOPOP_SOT_SHIFT (20U) #define SPI_FIFORDNOPOP_SOT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_SOT_SHIFT)) & SPI_FIFORDNOPOP_SOT_MASK) +/*! @} */ /*! @@ -4206,6 +4632,7 @@ typedef struct { */ /*! @name CTRL - SPIFI control register */ +/*! @{ */ #define SPIFI_CTRL_TIMEOUT_MASK (0xFFFFU) #define SPIFI_CTRL_TIMEOUT_SHIFT (0U) #define SPIFI_CTRL_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CTRL_TIMEOUT_SHIFT)) & SPIFI_CTRL_TIMEOUT_MASK) @@ -4236,8 +4663,10 @@ typedef struct { #define SPIFI_CTRL_DMAEN_MASK (0x80000000U) #define SPIFI_CTRL_DMAEN_SHIFT (31U) #define SPIFI_CTRL_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CTRL_DMAEN_SHIFT)) & SPIFI_CTRL_DMAEN_MASK) +/*! @} */ /*! @name CMD - SPIFI command register */ +/*! @{ */ #define SPIFI_CMD_DATALEN_MASK (0x3FFFU) #define SPIFI_CMD_DATALEN_SHIFT (0U) #define SPIFI_CMD_DATALEN(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CMD_DATALEN_SHIFT)) & SPIFI_CMD_DATALEN_MASK) @@ -4259,28 +4688,38 @@ typedef struct { #define SPIFI_CMD_OPCODE_MASK (0xFF000000U) #define SPIFI_CMD_OPCODE_SHIFT (24U) #define SPIFI_CMD_OPCODE(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CMD_OPCODE_SHIFT)) & SPIFI_CMD_OPCODE_MASK) +/*! @} */ /*! @name ADDR - SPIFI address register */ +/*! @{ */ #define SPIFI_ADDR_ADDRESS_MASK (0xFFFFFFFFU) #define SPIFI_ADDR_ADDRESS_SHIFT (0U) #define SPIFI_ADDR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_ADDR_ADDRESS_SHIFT)) & SPIFI_ADDR_ADDRESS_MASK) +/*! @} */ /*! @name IDATA - SPIFI intermediate data register */ +/*! @{ */ #define SPIFI_IDATA_IDATA_MASK (0xFFFFFFFFU) #define SPIFI_IDATA_IDATA_SHIFT (0U) #define SPIFI_IDATA_IDATA(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_IDATA_IDATA_SHIFT)) & SPIFI_IDATA_IDATA_MASK) +/*! @} */ /*! @name CLIMIT - SPIFI limit register */ +/*! @{ */ #define SPIFI_CLIMIT_CLIMIT_MASK (0xFFFFFFFFU) #define SPIFI_CLIMIT_CLIMIT_SHIFT (0U) #define SPIFI_CLIMIT_CLIMIT(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CLIMIT_CLIMIT_SHIFT)) & SPIFI_CLIMIT_CLIMIT_MASK) +/*! @} */ /*! @name DATA - SPIFI data register */ +/*! @{ */ #define SPIFI_DATA_DATA_MASK (0xFFFFFFFFU) #define SPIFI_DATA_DATA_SHIFT (0U) #define SPIFI_DATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_DATA_DATA_SHIFT)) & SPIFI_DATA_DATA_MASK) +/*! @} */ /*! @name MCMD - SPIFI memory command register */ +/*! @{ */ #define SPIFI_MCMD_POLL_MASK (0x4000U) #define SPIFI_MCMD_POLL_SHIFT (14U) #define SPIFI_MCMD_POLL(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_MCMD_POLL_SHIFT)) & SPIFI_MCMD_POLL_MASK) @@ -4299,8 +4738,10 @@ typedef struct { #define SPIFI_MCMD_OPCODE_MASK (0xFF000000U) #define SPIFI_MCMD_OPCODE_SHIFT (24U) #define SPIFI_MCMD_OPCODE(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_MCMD_OPCODE_SHIFT)) & SPIFI_MCMD_OPCODE_MASK) +/*! @} */ /*! @name STAT - SPIFI status register */ +/*! @{ */ #define SPIFI_STAT_MCINIT_MASK (0x1U) #define SPIFI_STAT_MCINIT_SHIFT (0U) #define SPIFI_STAT_MCINIT(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_STAT_MCINIT_SHIFT)) & SPIFI_STAT_MCINIT_MASK) @@ -4316,6 +4757,7 @@ typedef struct { #define SPIFI_STAT_VERSION_MASK (0xFF000000U) #define SPIFI_STAT_VERSION_SHIFT (24U) #define SPIFI_STAT_VERSION(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_STAT_VERSION_SHIFT)) & SPIFI_STAT_VERSION_MASK) +/*! @} */ /*! @@ -4351,7 +4793,7 @@ typedef struct { /** SYSCON - Register Layout Typedef */ typedef struct { - __IO uint32_t SYSMEMREMAP; /**< System Remap register, offset: 0x0 */ + uint32_t SYSMEMREMAP; /**< System Remap register, offset: 0x0 */ uint8_t RESERVED_0[12]; __IO uint32_t AHBMATPRIO; /**< AHB multilayer matrix priority control, offset: 0x10 */ uint8_t RESERVED_1[44]; @@ -4447,7 +4889,7 @@ typedef struct { uint8_t RESERVED_37[184]; __IO uint32_t HWWAKE; /**< Configures special cases of hardware wake-up, offset: 0x780 */ uint8_t RESERVED_38[124]; - __IO uint32_t CPCTRL; /**< CPU Control for multiple processors, offset: 0x800 */ + __IO uint32_t CPUCTRL; /**< CPU Control for multiple processors, offset: 0x800 */ __IO uint32_t CPBOOT; /**< Coprocessor Boot Address, offset: 0x804 */ __IO uint32_t CPSTACK; /**< Coprocessor Stack Address, offset: 0x808 */ __I uint32_t CPSTAT; /**< Coprocessor Status, offset: 0x80C */ @@ -4471,6 +4913,7 @@ typedef struct { */ /*! @name AHBMATPRIO - AHB multilayer matrix priority control */ +/*! @{ */ #define SYSCON_AHBMATPRIO_PRI_ICODE_MASK (0x3U) #define SYSCON_AHBMATPRIO_PRI_ICODE_SHIFT (0U) #define SYSCON_AHBMATPRIO_PRI_ICODE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_ICODE_SHIFT)) & SYSCON_AHBMATPRIO_PRI_ICODE_MASK) @@ -4489,8 +4932,10 @@ typedef struct { #define SYSCON_AHBMATPRIO_PRI_DMA_MASK (0xC00U) #define SYSCON_AHBMATPRIO_PRI_DMA_SHIFT (10U) #define SYSCON_AHBMATPRIO_PRI_DMA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_DMA_SHIFT)) & SYSCON_AHBMATPRIO_PRI_DMA_MASK) +/*! @} */ /*! @name SYSTCKCAL - System tick counter calibration */ +/*! @{ */ #define SYSCON_SYSTCKCAL_CAL_MASK (0xFFFFFFU) #define SYSCON_SYSTCKCAL_CAL_SHIFT (0U) #define SYSCON_SYSTCKCAL_CAL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTCKCAL_CAL_SHIFT)) & SYSCON_SYSTCKCAL_CAL_MASK) @@ -4500,8 +4945,10 @@ typedef struct { #define SYSCON_SYSTCKCAL_NOREF_MASK (0x2000000U) #define SYSCON_SYSTCKCAL_NOREF_SHIFT (25U) #define SYSCON_SYSTCKCAL_NOREF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTCKCAL_NOREF_SHIFT)) & SYSCON_SYSTCKCAL_NOREF_MASK) +/*! @} */ /*! @name NMISRC - NMI Source Select */ +/*! @{ */ #define SYSCON_NMISRC_IRQM4_MASK (0x3FU) #define SYSCON_NMISRC_IRQM4_SHIFT (0U) #define SYSCON_NMISRC_IRQM4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_NMISRC_IRQM4_SHIFT)) & SYSCON_NMISRC_IRQM4_MASK) @@ -4514,29 +4961,37 @@ typedef struct { #define SYSCON_NMISRC_NMIENM4_MASK (0x80000000U) #define SYSCON_NMISRC_NMIENM4_SHIFT (31U) #define SYSCON_NMISRC_NMIENM4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_NMISRC_NMIENM4_SHIFT)) & SYSCON_NMISRC_NMIENM4_MASK) +/*! @} */ /*! @name ASYNCAPBCTRL - Asynchronous APB Control */ +/*! @{ */ #define SYSCON_ASYNCAPBCTRL_ENABLE_MASK (0x1U) #define SYSCON_ASYNCAPBCTRL_ENABLE_SHIFT (0U) #define SYSCON_ASYNCAPBCTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ASYNCAPBCTRL_ENABLE_SHIFT)) & SYSCON_ASYNCAPBCTRL_ENABLE_MASK) +/*! @} */ /*! @name PIOPORCAP - POR captured value of port n */ +/*! @{ */ #define SYSCON_PIOPORCAP_PIOPORCAP_MASK (0xFFFFFFFFU) #define SYSCON_PIOPORCAP_PIOPORCAP_SHIFT (0U) #define SYSCON_PIOPORCAP_PIOPORCAP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PIOPORCAP_PIOPORCAP_SHIFT)) & SYSCON_PIOPORCAP_PIOPORCAP_MASK) +/*! @} */ /* The count of SYSCON_PIOPORCAP */ #define SYSCON_PIOPORCAP_COUNT (2U) /*! @name PIORESCAP - Reset captured value of port n */ +/*! @{ */ #define SYSCON_PIORESCAP_PIORESCAP_MASK (0xFFFFFFFFU) #define SYSCON_PIORESCAP_PIORESCAP_SHIFT (0U) #define SYSCON_PIORESCAP_PIORESCAP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PIORESCAP_PIORESCAP_SHIFT)) & SYSCON_PIORESCAP_PIORESCAP_MASK) +/*! @} */ /* The count of SYSCON_PIORESCAP */ #define SYSCON_PIORESCAP_COUNT (2U) /*! @name PRESETCTRL - Peripheral reset control n */ +/*! @{ */ #define SYSCON_PRESETCTRL_MRT0_RST_MASK (0x1U) #define SYSCON_PRESETCTRL_MRT0_RST_SHIFT (0U) #define SYSCON_PRESETCTRL_MRT0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_MRT0_RST_SHIFT)) & SYSCON_PRESETCTRL_MRT0_RST_MASK) @@ -4552,12 +5007,12 @@ typedef struct { #define SYSCON_PRESETCTRL_UTICK0_RST_MASK (0x400U) #define SYSCON_PRESETCTRL_UTICK0_RST_SHIFT (10U) #define SYSCON_PRESETCTRL_UTICK0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_UTICK0_RST_SHIFT)) & SYSCON_PRESETCTRL_UTICK0_RST_MASK) -#define SYSCON_PRESETCTRL_MUX_RST_MASK (0x800U) -#define SYSCON_PRESETCTRL_MUX_RST_SHIFT (11U) -#define SYSCON_PRESETCTRL_MUX_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_MUX_RST_SHIFT)) & SYSCON_PRESETCTRL_MUX_RST_MASK) #define SYSCON_PRESETCTRL_FC0_RST_MASK (0x800U) #define SYSCON_PRESETCTRL_FC0_RST_SHIFT (11U) #define SYSCON_PRESETCTRL_FC0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FC0_RST_SHIFT)) & SYSCON_PRESETCTRL_FC0_RST_MASK) +#define SYSCON_PRESETCTRL_MUX_RST_MASK (0x800U) +#define SYSCON_PRESETCTRL_MUX_RST_SHIFT (11U) +#define SYSCON_PRESETCTRL_MUX_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_MUX_RST_SHIFT)) & SYSCON_PRESETCTRL_MUX_RST_MASK) #define SYSCON_PRESETCTRL_FC1_RST_MASK (0x1000U) #define SYSCON_PRESETCTRL_FC1_RST_SHIFT (12U) #define SYSCON_PRESETCTRL_FC1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FC1_RST_SHIFT)) & SYSCON_PRESETCTRL_FC1_RST_MASK) @@ -4591,12 +5046,12 @@ typedef struct { #define SYSCON_PRESETCTRL_PINT_RST_MASK (0x40000U) #define SYSCON_PRESETCTRL_PINT_RST_SHIFT (18U) #define SYSCON_PRESETCTRL_PINT_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_PINT_RST_SHIFT)) & SYSCON_PRESETCTRL_PINT_RST_MASK) -#define SYSCON_PRESETCTRL_GINT_RST_MASK (0x80000U) -#define SYSCON_PRESETCTRL_GINT_RST_SHIFT (19U) -#define SYSCON_PRESETCTRL_GINT_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_GINT_RST_SHIFT)) & SYSCON_PRESETCTRL_GINT_RST_MASK) #define SYSCON_PRESETCTRL_DMIC0_RST_MASK (0x80000U) #define SYSCON_PRESETCTRL_DMIC0_RST_SHIFT (19U) #define SYSCON_PRESETCTRL_DMIC0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_DMIC0_RST_SHIFT)) & SYSCON_PRESETCTRL_DMIC0_RST_MASK) +#define SYSCON_PRESETCTRL_GINT_RST_MASK (0x80000U) +#define SYSCON_PRESETCTRL_GINT_RST_SHIFT (19U) +#define SYSCON_PRESETCTRL_GINT_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_GINT_RST_SHIFT)) & SYSCON_PRESETCTRL_GINT_RST_MASK) #define SYSCON_PRESETCTRL_DMA0_RST_MASK (0x100000U) #define SYSCON_PRESETCTRL_DMA0_RST_SHIFT (20U) #define SYSCON_PRESETCTRL_DMA0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_DMA0_RST_SHIFT)) & SYSCON_PRESETCTRL_DMA0_RST_MASK) @@ -4615,33 +5070,39 @@ typedef struct { #define SYSCON_PRESETCTRL_CTIMER0_RST_MASK (0x4000000U) #define SYSCON_PRESETCTRL_CTIMER0_RST_SHIFT (26U) #define SYSCON_PRESETCTRL_CTIMER0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_CTIMER0_RST_SHIFT)) & SYSCON_PRESETCTRL_CTIMER0_RST_MASK) -#define SYSCON_PRESETCTRL_CTIMER1_RST_MASK (0x8000000U) -#define SYSCON_PRESETCTRL_CTIMER1_RST_SHIFT (27U) -#define SYSCON_PRESETCTRL_CTIMER1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_CTIMER1_RST_SHIFT)) & SYSCON_PRESETCTRL_CTIMER1_RST_MASK) #define SYSCON_PRESETCTRL_ADC0_RST_MASK (0x8000000U) #define SYSCON_PRESETCTRL_ADC0_RST_SHIFT (27U) #define SYSCON_PRESETCTRL_ADC0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_ADC0_RST_SHIFT)) & SYSCON_PRESETCTRL_ADC0_RST_MASK) +#define SYSCON_PRESETCTRL_CTIMER1_RST_MASK (0x8000000U) +#define SYSCON_PRESETCTRL_CTIMER1_RST_SHIFT (27U) +#define SYSCON_PRESETCTRL_CTIMER1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_CTIMER1_RST_SHIFT)) & SYSCON_PRESETCTRL_CTIMER1_RST_MASK) +/*! @} */ /* The count of SYSCON_PRESETCTRL */ #define SYSCON_PRESETCTRL_COUNT (2U) /*! @name PRESETCTRLSET - Set bits in PRESETCTRLn */ +/*! @{ */ #define SYSCON_PRESETCTRLSET_RST_SET_MASK (0xFFFFFFFFU) #define SYSCON_PRESETCTRLSET_RST_SET_SHIFT (0U) #define SYSCON_PRESETCTRLSET_RST_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRLSET_RST_SET_SHIFT)) & SYSCON_PRESETCTRLSET_RST_SET_MASK) +/*! @} */ /* The count of SYSCON_PRESETCTRLSET */ #define SYSCON_PRESETCTRLSET_COUNT (2U) /*! @name PRESETCTRLCLR - Clear bits in PRESETCTRLn */ +/*! @{ */ #define SYSCON_PRESETCTRLCLR_RST_CLR_MASK (0xFFFFFFFFU) #define SYSCON_PRESETCTRLCLR_RST_CLR_SHIFT (0U) #define SYSCON_PRESETCTRLCLR_RST_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRLCLR_RST_CLR_SHIFT)) & SYSCON_PRESETCTRLCLR_RST_CLR_MASK) +/*! @} */ /* The count of SYSCON_PRESETCTRLCLR */ #define SYSCON_PRESETCTRLCLR_COUNT (2U) /*! @name SYSRSTSTAT - System reset status register */ +/*! @{ */ #define SYSCON_SYSRSTSTAT_POR_MASK (0x1U) #define SYSCON_SYSRSTSTAT_POR_SHIFT (0U) #define SYSCON_SYSRSTSTAT_POR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSRSTSTAT_POR_SHIFT)) & SYSCON_SYSRSTSTAT_POR_MASK) @@ -4657,8 +5118,10 @@ typedef struct { #define SYSCON_SYSRSTSTAT_SYSRST_MASK (0x10U) #define SYSCON_SYSRSTSTAT_SYSRST_SHIFT (4U) #define SYSCON_SYSRSTSTAT_SYSRST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSRSTSTAT_SYSRST_SHIFT)) & SYSCON_SYSRSTSTAT_SYSRST_MASK) +/*! @} */ /*! @name AHBCLKCTRL - AHB Clock control n */ +/*! @{ */ #define SYSCON_AHBCLKCTRL_MRT0_MASK (0x1U) #define SYSCON_AHBCLKCTRL_MRT0_SHIFT (0U) #define SYSCON_AHBCLKCTRL_MRT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_MRT0_SHIFT)) & SYSCON_AHBCLKCTRL_MRT0_MASK) @@ -4692,18 +5155,18 @@ typedef struct { #define SYSCON_AHBCLKCTRL_FLEXCOMM1_MASK (0x1000U) #define SYSCON_AHBCLKCTRL_FLEXCOMM1_SHIFT (12U) #define SYSCON_AHBCLKCTRL_FLEXCOMM1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLEXCOMM1_SHIFT)) & SYSCON_AHBCLKCTRL_FLEXCOMM1_MASK) -#define SYSCON_AHBCLKCTRL_IOCON_MASK (0x2000U) -#define SYSCON_AHBCLKCTRL_IOCON_SHIFT (13U) -#define SYSCON_AHBCLKCTRL_IOCON(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_IOCON_SHIFT)) & SYSCON_AHBCLKCTRL_IOCON_MASK) #define SYSCON_AHBCLKCTRL_FLEXCOMM2_MASK (0x2000U) #define SYSCON_AHBCLKCTRL_FLEXCOMM2_SHIFT (13U) #define SYSCON_AHBCLKCTRL_FLEXCOMM2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLEXCOMM2_SHIFT)) & SYSCON_AHBCLKCTRL_FLEXCOMM2_MASK) -#define SYSCON_AHBCLKCTRL_GPIO0_MASK (0x4000U) -#define SYSCON_AHBCLKCTRL_GPIO0_SHIFT (14U) -#define SYSCON_AHBCLKCTRL_GPIO0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_GPIO0_SHIFT)) & SYSCON_AHBCLKCTRL_GPIO0_MASK) +#define SYSCON_AHBCLKCTRL_IOCON_MASK (0x2000U) +#define SYSCON_AHBCLKCTRL_IOCON_SHIFT (13U) +#define SYSCON_AHBCLKCTRL_IOCON(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_IOCON_SHIFT)) & SYSCON_AHBCLKCTRL_IOCON_MASK) #define SYSCON_AHBCLKCTRL_FLEXCOMM3_MASK (0x4000U) #define SYSCON_AHBCLKCTRL_FLEXCOMM3_SHIFT (14U) #define SYSCON_AHBCLKCTRL_FLEXCOMM3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLEXCOMM3_SHIFT)) & SYSCON_AHBCLKCTRL_FLEXCOMM3_MASK) +#define SYSCON_AHBCLKCTRL_GPIO0_MASK (0x4000U) +#define SYSCON_AHBCLKCTRL_GPIO0_SHIFT (14U) +#define SYSCON_AHBCLKCTRL_GPIO0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_GPIO0_SHIFT)) & SYSCON_AHBCLKCTRL_GPIO0_MASK) #define SYSCON_AHBCLKCTRL_FLEXCOMM4_MASK (0x8000U) #define SYSCON_AHBCLKCTRL_FLEXCOMM4_SHIFT (15U) #define SYSCON_AHBCLKCTRL_FLEXCOMM4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLEXCOMM4_SHIFT)) & SYSCON_AHBCLKCTRL_FLEXCOMM4_MASK) @@ -4722,12 +5185,12 @@ typedef struct { #define SYSCON_AHBCLKCTRL_PINT_MASK (0x40000U) #define SYSCON_AHBCLKCTRL_PINT_SHIFT (18U) #define SYSCON_AHBCLKCTRL_PINT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_PINT_SHIFT)) & SYSCON_AHBCLKCTRL_PINT_MASK) -#define SYSCON_AHBCLKCTRL_GINT_MASK (0x80000U) -#define SYSCON_AHBCLKCTRL_GINT_SHIFT (19U) -#define SYSCON_AHBCLKCTRL_GINT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_GINT_SHIFT)) & SYSCON_AHBCLKCTRL_GINT_MASK) #define SYSCON_AHBCLKCTRL_DMIC0_MASK (0x80000U) #define SYSCON_AHBCLKCTRL_DMIC0_SHIFT (19U) #define SYSCON_AHBCLKCTRL_DMIC0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_DMIC0_SHIFT)) & SYSCON_AHBCLKCTRL_DMIC0_MASK) +#define SYSCON_AHBCLKCTRL_GINT_MASK (0x80000U) +#define SYSCON_AHBCLKCTRL_GINT_SHIFT (19U) +#define SYSCON_AHBCLKCTRL_GINT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_GINT_SHIFT)) & SYSCON_AHBCLKCTRL_GINT_MASK) #define SYSCON_AHBCLKCTRL_DMA0_MASK (0x100000U) #define SYSCON_AHBCLKCTRL_DMA0_SHIFT (20U) #define SYSCON_AHBCLKCTRL_DMA0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_DMA0_SHIFT)) & SYSCON_AHBCLKCTRL_DMA0_MASK) @@ -4752,91 +5215,119 @@ typedef struct { #define SYSCON_AHBCLKCTRL_MAILBOX_MASK (0x4000000U) #define SYSCON_AHBCLKCTRL_MAILBOX_SHIFT (26U) #define SYSCON_AHBCLKCTRL_MAILBOX(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_MAILBOX_SHIFT)) & SYSCON_AHBCLKCTRL_MAILBOX_MASK) -#define SYSCON_AHBCLKCTRL_CTIMER1_MASK (0x8000000U) -#define SYSCON_AHBCLKCTRL_CTIMER1_SHIFT (27U) -#define SYSCON_AHBCLKCTRL_CTIMER1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_CTIMER1_SHIFT)) & SYSCON_AHBCLKCTRL_CTIMER1_MASK) #define SYSCON_AHBCLKCTRL_ADC0_MASK (0x8000000U) #define SYSCON_AHBCLKCTRL_ADC0_SHIFT (27U) #define SYSCON_AHBCLKCTRL_ADC0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_ADC0_SHIFT)) & SYSCON_AHBCLKCTRL_ADC0_MASK) +#define SYSCON_AHBCLKCTRL_CTIMER1_MASK (0x8000000U) +#define SYSCON_AHBCLKCTRL_CTIMER1_SHIFT (27U) +#define SYSCON_AHBCLKCTRL_CTIMER1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_CTIMER1_SHIFT)) & SYSCON_AHBCLKCTRL_CTIMER1_MASK) +/*! @} */ /* The count of SYSCON_AHBCLKCTRL */ #define SYSCON_AHBCLKCTRL_COUNT (2U) /*! @name AHBCLKCTRLSET - Set bits in AHBCLKCTRLn */ +/*! @{ */ #define SYSCON_AHBCLKCTRLSET_CLK_SET_MASK (0xFFFFFFFFU) #define SYSCON_AHBCLKCTRLSET_CLK_SET_SHIFT (0U) #define SYSCON_AHBCLKCTRLSET_CLK_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRLSET_CLK_SET_SHIFT)) & SYSCON_AHBCLKCTRLSET_CLK_SET_MASK) +/*! @} */ /* The count of SYSCON_AHBCLKCTRLSET */ #define SYSCON_AHBCLKCTRLSET_COUNT (2U) /*! @name AHBCLKCTRLCLR - Clear bits in AHBCLKCTRLn */ +/*! @{ */ #define SYSCON_AHBCLKCTRLCLR_CLK_CLR_MASK (0xFFFFFFFFU) #define SYSCON_AHBCLKCTRLCLR_CLK_CLR_SHIFT (0U) #define SYSCON_AHBCLKCTRLCLR_CLK_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRLCLR_CLK_CLR_SHIFT)) & SYSCON_AHBCLKCTRLCLR_CLK_CLR_MASK) +/*! @} */ /* The count of SYSCON_AHBCLKCTRLCLR */ #define SYSCON_AHBCLKCTRLCLR_COUNT (2U) /*! @name MAINCLKSELA - Main clock source select A */ +/*! @{ */ #define SYSCON_MAINCLKSELA_SEL_MASK (0x3U) #define SYSCON_MAINCLKSELA_SEL_SHIFT (0U) #define SYSCON_MAINCLKSELA_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MAINCLKSELA_SEL_SHIFT)) & SYSCON_MAINCLKSELA_SEL_MASK) +/*! @} */ /*! @name MAINCLKSELB - Main clock source select B */ +/*! @{ */ #define SYSCON_MAINCLKSELB_SEL_MASK (0x3U) #define SYSCON_MAINCLKSELB_SEL_SHIFT (0U) #define SYSCON_MAINCLKSELB_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MAINCLKSELB_SEL_SHIFT)) & SYSCON_MAINCLKSELB_SEL_MASK) +/*! @} */ /*! @name CLKOUTSELA - CLKOUT clock source select A */ +/*! @{ */ #define SYSCON_CLKOUTSELA_SEL_MASK (0x7U) #define SYSCON_CLKOUTSELA_SEL_SHIFT (0U) #define SYSCON_CLKOUTSELA_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTSELA_SEL_SHIFT)) & SYSCON_CLKOUTSELA_SEL_MASK) +/*! @} */ /*! @name SYSPLLCLKSEL - PLL clock source select */ +/*! @{ */ #define SYSCON_SYSPLLCLKSEL_SEL_MASK (0x7U) #define SYSCON_SYSPLLCLKSEL_SEL_SHIFT (0U) #define SYSCON_SYSPLLCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLCLKSEL_SEL_SHIFT)) & SYSCON_SYSPLLCLKSEL_SEL_MASK) +/*! @} */ /*! @name SPIFICLKSEL - SPIFI clock source select */ +/*! @{ */ #define SYSCON_SPIFICLKSEL_SEL_MASK (0x7U) #define SYSCON_SPIFICLKSEL_SEL_SHIFT (0U) #define SYSCON_SPIFICLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SPIFICLKSEL_SEL_SHIFT)) & SYSCON_SPIFICLKSEL_SEL_MASK) +/*! @} */ /*! @name ADCCLKSEL - ADC clock source select */ +/*! @{ */ #define SYSCON_ADCCLKSEL_SEL_MASK (0x7U) #define SYSCON_ADCCLKSEL_SEL_SHIFT (0U) #define SYSCON_ADCCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADCCLKSEL_SEL_SHIFT)) & SYSCON_ADCCLKSEL_SEL_MASK) +/*! @} */ /*! @name USBCLKSEL - USB clock source select */ +/*! @{ */ #define SYSCON_USBCLKSEL_SEL_MASK (0x7U) #define SYSCON_USBCLKSEL_SEL_SHIFT (0U) #define SYSCON_USBCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USBCLKSEL_SEL_SHIFT)) & SYSCON_USBCLKSEL_SEL_MASK) +/*! @} */ /*! @name FXCOMCLKSEL - Flexcomm 0 clock source select */ +/*! @{ */ #define SYSCON_FXCOMCLKSEL_SEL_MASK (0x7U) #define SYSCON_FXCOMCLKSEL_SEL_SHIFT (0U) #define SYSCON_FXCOMCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FXCOMCLKSEL_SEL_SHIFT)) & SYSCON_FXCOMCLKSEL_SEL_MASK) +/*! @} */ /* The count of SYSCON_FXCOMCLKSEL */ #define SYSCON_FXCOMCLKSEL_COUNT (8U) /*! @name MCLKCLKSEL - MCLK clock source select */ +/*! @{ */ #define SYSCON_MCLKCLKSEL_SEL_MASK (0x7U) #define SYSCON_MCLKCLKSEL_SEL_SHIFT (0U) #define SYSCON_MCLKCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKCLKSEL_SEL_SHIFT)) & SYSCON_MCLKCLKSEL_SEL_MASK) +/*! @} */ /*! @name FRGCLKSEL - Fractional Rate Generator clock source select */ +/*! @{ */ #define SYSCON_FRGCLKSEL_SEL_MASK (0x7U) #define SYSCON_FRGCLKSEL_SEL_SHIFT (0U) #define SYSCON_FRGCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FRGCLKSEL_SEL_SHIFT)) & SYSCON_FRGCLKSEL_SEL_MASK) +/*! @} */ /*! @name DMICCLKSEL - Digital microphone (D-Mic) subsystem clock select */ +/*! @{ */ #define SYSCON_DMICCLKSEL_SEL_MASK (0x7U) #define SYSCON_DMICCLKSEL_SEL_SHIFT (0U) #define SYSCON_DMICCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DMICCLKSEL_SEL_SHIFT)) & SYSCON_DMICCLKSEL_SEL_MASK) +/*! @} */ /*! @name SYSTICKCLKDIV - SYSTICK clock divider */ +/*! @{ */ #define SYSCON_SYSTICKCLKDIV_DIV_MASK (0xFFU) #define SYSCON_SYSTICKCLKDIV_DIV_SHIFT (0U) #define SYSCON_SYSTICKCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV_DIV_SHIFT)) & SYSCON_SYSTICKCLKDIV_DIV_MASK) @@ -4846,8 +5337,10 @@ typedef struct { #define SYSCON_SYSTICKCLKDIV_HALT_MASK (0x40000000U) #define SYSCON_SYSTICKCLKDIV_HALT_SHIFT (30U) #define SYSCON_SYSTICKCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV_HALT_SHIFT)) & SYSCON_SYSTICKCLKDIV_HALT_MASK) +/*! @} */ /*! @name TRACECLKDIV - Trace clock divider */ +/*! @{ */ #define SYSCON_TRACECLKDIV_DIV_MASK (0xFFU) #define SYSCON_TRACECLKDIV_DIV_SHIFT (0U) #define SYSCON_TRACECLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_TRACECLKDIV_DIV_SHIFT)) & SYSCON_TRACECLKDIV_DIV_MASK) @@ -4857,8 +5350,10 @@ typedef struct { #define SYSCON_TRACECLKDIV_HALT_MASK (0x40000000U) #define SYSCON_TRACECLKDIV_HALT_SHIFT (30U) #define SYSCON_TRACECLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_TRACECLKDIV_HALT_SHIFT)) & SYSCON_TRACECLKDIV_HALT_MASK) +/*! @} */ /*! @name AHBCLKDIV - AHB clock divider */ +/*! @{ */ #define SYSCON_AHBCLKDIV_DIV_MASK (0xFFU) #define SYSCON_AHBCLKDIV_DIV_SHIFT (0U) #define SYSCON_AHBCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKDIV_DIV_SHIFT)) & SYSCON_AHBCLKDIV_DIV_MASK) @@ -4868,8 +5363,10 @@ typedef struct { #define SYSCON_AHBCLKDIV_HALT_MASK (0x40000000U) #define SYSCON_AHBCLKDIV_HALT_SHIFT (30U) #define SYSCON_AHBCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKDIV_HALT_SHIFT)) & SYSCON_AHBCLKDIV_HALT_MASK) +/*! @} */ /*! @name CLKOUTDIV - CLKOUT clock divider */ +/*! @{ */ #define SYSCON_CLKOUTDIV_DIV_MASK (0xFFU) #define SYSCON_CLKOUTDIV_DIV_SHIFT (0U) #define SYSCON_CLKOUTDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTDIV_DIV_SHIFT)) & SYSCON_CLKOUTDIV_DIV_MASK) @@ -4879,8 +5376,10 @@ typedef struct { #define SYSCON_CLKOUTDIV_HALT_MASK (0x40000000U) #define SYSCON_CLKOUTDIV_HALT_SHIFT (30U) #define SYSCON_CLKOUTDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTDIV_HALT_SHIFT)) & SYSCON_CLKOUTDIV_HALT_MASK) +/*! @} */ /*! @name SPIFICLKDIV - SPIFI clock divider */ +/*! @{ */ #define SYSCON_SPIFICLKDIV_DIV_MASK (0xFFU) #define SYSCON_SPIFICLKDIV_DIV_SHIFT (0U) #define SYSCON_SPIFICLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SPIFICLKDIV_DIV_SHIFT)) & SYSCON_SPIFICLKDIV_DIV_MASK) @@ -4890,8 +5389,10 @@ typedef struct { #define SYSCON_SPIFICLKDIV_HALT_MASK (0x40000000U) #define SYSCON_SPIFICLKDIV_HALT_SHIFT (30U) #define SYSCON_SPIFICLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SPIFICLKDIV_HALT_SHIFT)) & SYSCON_SPIFICLKDIV_HALT_MASK) +/*! @} */ /*! @name ADCCLKDIV - ADC clock divider */ +/*! @{ */ #define SYSCON_ADCCLKDIV_DIV_MASK (0xFFU) #define SYSCON_ADCCLKDIV_DIV_SHIFT (0U) #define SYSCON_ADCCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADCCLKDIV_DIV_SHIFT)) & SYSCON_ADCCLKDIV_DIV_MASK) @@ -4901,8 +5402,10 @@ typedef struct { #define SYSCON_ADCCLKDIV_HALT_MASK (0x40000000U) #define SYSCON_ADCCLKDIV_HALT_SHIFT (30U) #define SYSCON_ADCCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADCCLKDIV_HALT_SHIFT)) & SYSCON_ADCCLKDIV_HALT_MASK) +/*! @} */ /*! @name USBCLKDIV - USB clock divider */ +/*! @{ */ #define SYSCON_USBCLKDIV_DIV_MASK (0xFFU) #define SYSCON_USBCLKDIV_DIV_SHIFT (0U) #define SYSCON_USBCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USBCLKDIV_DIV_SHIFT)) & SYSCON_USBCLKDIV_DIV_MASK) @@ -4912,16 +5415,20 @@ typedef struct { #define SYSCON_USBCLKDIV_HALT_MASK (0x40000000U) #define SYSCON_USBCLKDIV_HALT_SHIFT (30U) #define SYSCON_USBCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USBCLKDIV_HALT_SHIFT)) & SYSCON_USBCLKDIV_HALT_MASK) +/*! @} */ /*! @name FRGCTRL - Fractional rate divider */ +/*! @{ */ #define SYSCON_FRGCTRL_DIV_MASK (0xFFU) #define SYSCON_FRGCTRL_DIV_SHIFT (0U) #define SYSCON_FRGCTRL_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FRGCTRL_DIV_SHIFT)) & SYSCON_FRGCTRL_DIV_MASK) #define SYSCON_FRGCTRL_MULT_MASK (0xFF00U) #define SYSCON_FRGCTRL_MULT_SHIFT (8U) #define SYSCON_FRGCTRL_MULT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FRGCTRL_MULT_SHIFT)) & SYSCON_FRGCTRL_MULT_MASK) +/*! @} */ /*! @name DMICCLKDIV - DMIC clock divider */ +/*! @{ */ #define SYSCON_DMICCLKDIV_DIV_MASK (0xFFU) #define SYSCON_DMICCLKDIV_DIV_SHIFT (0U) #define SYSCON_DMICCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DMICCLKDIV_DIV_SHIFT)) & SYSCON_DMICCLKDIV_DIV_MASK) @@ -4931,8 +5438,10 @@ typedef struct { #define SYSCON_DMICCLKDIV_HALT_MASK (0x40000000U) #define SYSCON_DMICCLKDIV_HALT_SHIFT (30U) #define SYSCON_DMICCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DMICCLKDIV_HALT_SHIFT)) & SYSCON_DMICCLKDIV_HALT_MASK) +/*! @} */ /*! @name MCLKDIV - I2S MCLK clock divider */ +/*! @{ */ #define SYSCON_MCLKDIV_DIV_MASK (0xFFU) #define SYSCON_MCLKDIV_DIV_SHIFT (0U) #define SYSCON_MCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKDIV_DIV_SHIFT)) & SYSCON_MCLKDIV_DIV_MASK) @@ -4942,8 +5451,10 @@ typedef struct { #define SYSCON_MCLKDIV_HALT_MASK (0x40000000U) #define SYSCON_MCLKDIV_HALT_SHIFT (30U) #define SYSCON_MCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKDIV_HALT_SHIFT)) & SYSCON_MCLKDIV_HALT_MASK) +/*! @} */ /*! @name FLASHCFG - Flash wait states configuration */ +/*! @{ */ #define SYSCON_FLASHCFG_FETCHCFG_MASK (0x3U) #define SYSCON_FLASHCFG_FETCHCFG_SHIFT (0U) #define SYSCON_FLASHCFG_FETCHCFG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLASHCFG_FETCHCFG_SHIFT)) & SYSCON_FLASHCFG_FETCHCFG_MASK) @@ -4962,31 +5473,41 @@ typedef struct { #define SYSCON_FLASHCFG_FLASHTIM_MASK (0xF000U) #define SYSCON_FLASHCFG_FLASHTIM_SHIFT (12U) #define SYSCON_FLASHCFG_FLASHTIM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLASHCFG_FLASHTIM_SHIFT)) & SYSCON_FLASHCFG_FLASHTIM_MASK) +/*! @} */ /*! @name USBCLKCTRL - USB clock control */ +/*! @{ */ #define SYSCON_USBCLKCTRL_POL_CLK_MASK (0x2U) #define SYSCON_USBCLKCTRL_POL_CLK_SHIFT (1U) #define SYSCON_USBCLKCTRL_POL_CLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USBCLKCTRL_POL_CLK_SHIFT)) & SYSCON_USBCLKCTRL_POL_CLK_MASK) +/*! @} */ /*! @name USBCLKSTAT - USB clock status */ +/*! @{ */ #define SYSCON_USBCLKSTAT_NEED_CLKST_MASK (0x1U) #define SYSCON_USBCLKSTAT_NEED_CLKST_SHIFT (0U) #define SYSCON_USBCLKSTAT_NEED_CLKST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USBCLKSTAT_NEED_CLKST_SHIFT)) & SYSCON_USBCLKSTAT_NEED_CLKST_MASK) +/*! @} */ /*! @name FREQMECTRL - Frequency measure register */ +/*! @{ */ #define SYSCON_FREQMECTRL_CAPVAL_MASK (0x3FFFU) #define SYSCON_FREQMECTRL_CAPVAL_SHIFT (0U) #define SYSCON_FREQMECTRL_CAPVAL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FREQMECTRL_CAPVAL_SHIFT)) & SYSCON_FREQMECTRL_CAPVAL_MASK) #define SYSCON_FREQMECTRL_PROG_MASK (0x80000000U) #define SYSCON_FREQMECTRL_PROG_SHIFT (31U) #define SYSCON_FREQMECTRL_PROG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FREQMECTRL_PROG_SHIFT)) & SYSCON_FREQMECTRL_PROG_MASK) +/*! @} */ /*! @name MCLKIO - MCLK input/output control */ +/*! @{ */ #define SYSCON_MCLKIO_DIR_MASK (0x1U) #define SYSCON_MCLKIO_DIR_SHIFT (0U) #define SYSCON_MCLKIO_DIR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKIO_DIR_SHIFT)) & SYSCON_MCLKIO_DIR_MASK) +/*! @} */ /*! @name FROCTRL - FRO oscillator control */ +/*! @{ */ #define SYSCON_FROCTRL_TRIM_MASK (0x3FFFU) #define SYSCON_FROCTRL_TRIM_SHIFT (0U) #define SYSCON_FROCTRL_TRIM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROCTRL_TRIM_SHIFT)) & SYSCON_FROCTRL_TRIM_MASK) @@ -5008,21 +5529,27 @@ typedef struct { #define SYSCON_FROCTRL_WRTRIM_MASK (0x80000000U) #define SYSCON_FROCTRL_WRTRIM_SHIFT (31U) #define SYSCON_FROCTRL_WRTRIM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROCTRL_WRTRIM_SHIFT)) & SYSCON_FROCTRL_WRTRIM_MASK) +/*! @} */ /*! @name WDTOSCCTRL - Watchdog oscillator control */ +/*! @{ */ #define SYSCON_WDTOSCCTRL_DIVSEL_MASK (0x1FU) #define SYSCON_WDTOSCCTRL_DIVSEL_SHIFT (0U) #define SYSCON_WDTOSCCTRL_DIVSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_WDTOSCCTRL_DIVSEL_SHIFT)) & SYSCON_WDTOSCCTRL_DIVSEL_MASK) #define SYSCON_WDTOSCCTRL_FREQSEL_MASK (0x3E0U) #define SYSCON_WDTOSCCTRL_FREQSEL_SHIFT (5U) #define SYSCON_WDTOSCCTRL_FREQSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_WDTOSCCTRL_FREQSEL_SHIFT)) & SYSCON_WDTOSCCTRL_FREQSEL_MASK) +/*! @} */ /*! @name RTCOSCCTRL - RTC oscillator 32 kHz output control */ +/*! @{ */ #define SYSCON_RTCOSCCTRL_EN_MASK (0x1U) #define SYSCON_RTCOSCCTRL_EN_SHIFT (0U) #define SYSCON_RTCOSCCTRL_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_RTCOSCCTRL_EN_SHIFT)) & SYSCON_RTCOSCCTRL_EN_MASK) +/*! @} */ /*! @name SYSPLLCTRL - PLL control */ +/*! @{ */ #define SYSCON_SYSPLLCTRL_SELR_MASK (0xFU) #define SYSCON_SYSPLLCTRL_SELR_SHIFT (0U) #define SYSCON_SYSPLLCTRL_SELR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLCTRL_SELR_SHIFT)) & SYSCON_SYSPLLCTRL_SELR_MASK) @@ -5050,29 +5577,37 @@ typedef struct { #define SYSCON_SYSPLLCTRL_DIRECTO_MASK (0x100000U) #define SYSCON_SYSPLLCTRL_DIRECTO_SHIFT (20U) #define SYSCON_SYSPLLCTRL_DIRECTO(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLCTRL_DIRECTO_SHIFT)) & SYSCON_SYSPLLCTRL_DIRECTO_MASK) +/*! @} */ /*! @name SYSPLLSTAT - PLL status */ +/*! @{ */ #define SYSCON_SYSPLLSTAT_LOCK_MASK (0x1U) #define SYSCON_SYSPLLSTAT_LOCK_SHIFT (0U) #define SYSCON_SYSPLLSTAT_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLSTAT_LOCK_SHIFT)) & SYSCON_SYSPLLSTAT_LOCK_MASK) +/*! @} */ /*! @name SYSPLLNDEC - PLL N decoder */ +/*! @{ */ #define SYSCON_SYSPLLNDEC_NDEC_MASK (0x3FFU) #define SYSCON_SYSPLLNDEC_NDEC_SHIFT (0U) #define SYSCON_SYSPLLNDEC_NDEC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLNDEC_NDEC_SHIFT)) & SYSCON_SYSPLLNDEC_NDEC_MASK) #define SYSCON_SYSPLLNDEC_NREQ_MASK (0x400U) #define SYSCON_SYSPLLNDEC_NREQ_SHIFT (10U) #define SYSCON_SYSPLLNDEC_NREQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLNDEC_NREQ_SHIFT)) & SYSCON_SYSPLLNDEC_NREQ_MASK) +/*! @} */ /*! @name SYSPLLPDEC - PLL P decoder */ +/*! @{ */ #define SYSCON_SYSPLLPDEC_PDEC_MASK (0x7FU) #define SYSCON_SYSPLLPDEC_PDEC_SHIFT (0U) #define SYSCON_SYSPLLPDEC_PDEC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLPDEC_PDEC_SHIFT)) & SYSCON_SYSPLLPDEC_PDEC_MASK) #define SYSCON_SYSPLLPDEC_PREQ_MASK (0x80U) #define SYSCON_SYSPLLPDEC_PREQ_SHIFT (7U) #define SYSCON_SYSPLLPDEC_PREQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLPDEC_PREQ_SHIFT)) & SYSCON_SYSPLLPDEC_PREQ_MASK) +/*! @} */ /*! @name SYSPLLSSCTRL0 - PLL spread spectrum control 0 */ +/*! @{ */ #define SYSCON_SYSPLLSSCTRL0_MDEC_MASK (0x1FFFFU) #define SYSCON_SYSPLLSSCTRL0_MDEC_SHIFT (0U) #define SYSCON_SYSPLLSSCTRL0_MDEC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLSSCTRL0_MDEC_SHIFT)) & SYSCON_SYSPLLSSCTRL0_MDEC_MASK) @@ -5082,8 +5617,10 @@ typedef struct { #define SYSCON_SYSPLLSSCTRL0_SEL_EXT_MASK (0x40000U) #define SYSCON_SYSPLLSSCTRL0_SEL_EXT_SHIFT (18U) #define SYSCON_SYSPLLSSCTRL0_SEL_EXT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLSSCTRL0_SEL_EXT_SHIFT)) & SYSCON_SYSPLLSSCTRL0_SEL_EXT_MASK) +/*! @} */ /*! @name SYSPLLSSCTRL1 - PLL spread spectrum control 1 */ +/*! @{ */ #define SYSCON_SYSPLLSSCTRL1_MD_MASK (0x7FFFFU) #define SYSCON_SYSPLLSSCTRL1_MD_SHIFT (0U) #define SYSCON_SYSPLLSSCTRL1_MD(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLSSCTRL1_MD_SHIFT)) & SYSCON_SYSPLLSSCTRL1_MD_MASK) @@ -5105,16 +5642,20 @@ typedef struct { #define SYSCON_SYSPLLSSCTRL1_DITHER_MASK (0x20000000U) #define SYSCON_SYSPLLSSCTRL1_DITHER_SHIFT (29U) #define SYSCON_SYSPLLSSCTRL1_DITHER(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLSSCTRL1_DITHER_SHIFT)) & SYSCON_SYSPLLSSCTRL1_DITHER_MASK) +/*! @} */ /*! @name PDSLEEPCFG - Sleep configuration register n */ +/*! @{ */ #define SYSCON_PDSLEEPCFG_PD_SLEEP_MASK (0xFFFFFFFFU) #define SYSCON_PDSLEEPCFG_PD_SLEEP_SHIFT (0U) #define SYSCON_PDSLEEPCFG_PD_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PD_SLEEP_SHIFT)) & SYSCON_PDSLEEPCFG_PD_SLEEP_MASK) +/*! @} */ /* The count of SYSCON_PDSLEEPCFG */ #define SYSCON_PDSLEEPCFG_COUNT (2U) /*! @name PDRUNCFG - Power configuration register n */ +/*! @{ */ #define SYSCON_PDRUNCFG_PDEN_FRO_MASK (0x10U) #define SYSCON_PDRUNCFG_PDEN_FRO_SHIFT (4U) #define SYSCON_PDRUNCFG_PDEN_FRO(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_FRO_SHIFT)) & SYSCON_PDRUNCFG_PDEN_FRO_MASK) @@ -5181,39 +5722,45 @@ typedef struct { #define SYSCON_PDRUNCFG_SEL_ALT_FLASH_IBG_MASK (0x20000000U) #define SYSCON_PDRUNCFG_SEL_ALT_FLASH_IBG_SHIFT (29U) #define SYSCON_PDRUNCFG_SEL_ALT_FLASH_IBG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_SEL_ALT_FLASH_IBG_SHIFT)) & SYSCON_PDRUNCFG_SEL_ALT_FLASH_IBG_MASK) +/*! @} */ /* The count of SYSCON_PDRUNCFG */ #define SYSCON_PDRUNCFG_COUNT (2U) /*! @name PDRUNCFGSET - Set bits in PDRUNCFGn */ +/*! @{ */ #define SYSCON_PDRUNCFGSET_PD_SET_MASK (0xFFFFFFFFU) #define SYSCON_PDRUNCFGSET_PD_SET_SHIFT (0U) #define SYSCON_PDRUNCFGSET_PD_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PD_SET_SHIFT)) & SYSCON_PDRUNCFGSET_PD_SET_MASK) +/*! @} */ /* The count of SYSCON_PDRUNCFGSET */ #define SYSCON_PDRUNCFGSET_COUNT (2U) /*! @name PDRUNCFGCLR - Clear bits in PDRUNCFGn */ +/*! @{ */ #define SYSCON_PDRUNCFGCLR_PD_CLR_MASK (0xFFFFFFFFU) #define SYSCON_PDRUNCFGCLR_PD_CLR_SHIFT (0U) #define SYSCON_PDRUNCFGCLR_PD_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PD_CLR_SHIFT)) & SYSCON_PDRUNCFGCLR_PD_CLR_MASK) +/*! @} */ /* The count of SYSCON_PDRUNCFGCLR */ #define SYSCON_PDRUNCFGCLR_COUNT (2U) /*! @name STARTERP - Start logic n wake-up enable register */ -#define SYSCON_STARTERP_WDT_BOD_MASK (0x1U) -#define SYSCON_STARTERP_WDT_BOD_SHIFT (0U) -#define SYSCON_STARTERP_WDT_BOD(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_WDT_BOD_SHIFT)) & SYSCON_STARTERP_WDT_BOD_MASK) +/*! @{ */ #define SYSCON_STARTERP_PINT4_MASK (0x1U) #define SYSCON_STARTERP_PINT4_SHIFT (0U) #define SYSCON_STARTERP_PINT4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_PINT4_SHIFT)) & SYSCON_STARTERP_PINT4_MASK) -#define SYSCON_STARTERP_PINT5_MASK (0x2U) -#define SYSCON_STARTERP_PINT5_SHIFT (1U) -#define SYSCON_STARTERP_PINT5(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_PINT5_SHIFT)) & SYSCON_STARTERP_PINT5_MASK) +#define SYSCON_STARTERP_WDT_BOD_MASK (0x1U) +#define SYSCON_STARTERP_WDT_BOD_SHIFT (0U) +#define SYSCON_STARTERP_WDT_BOD(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_WDT_BOD_SHIFT)) & SYSCON_STARTERP_WDT_BOD_MASK) #define SYSCON_STARTERP_DMA0_MASK (0x2U) #define SYSCON_STARTERP_DMA0_SHIFT (1U) #define SYSCON_STARTERP_DMA0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_DMA0_SHIFT)) & SYSCON_STARTERP_DMA0_MASK) +#define SYSCON_STARTERP_PINT5_MASK (0x2U) +#define SYSCON_STARTERP_PINT5_SHIFT (1U) +#define SYSCON_STARTERP_PINT5(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_PINT5_SHIFT)) & SYSCON_STARTERP_PINT5_MASK) #define SYSCON_STARTERP_GINT0_MASK (0x4U) #define SYSCON_STARTERP_GINT0_SHIFT (2U) #define SYSCON_STARTERP_GINT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_GINT0_SHIFT)) & SYSCON_STARTERP_GINT0_MASK) @@ -5232,12 +5779,12 @@ typedef struct { #define SYSCON_STARTERP_PIN_INT0_MASK (0x10U) #define SYSCON_STARTERP_PIN_INT0_SHIFT (4U) #define SYSCON_STARTERP_PIN_INT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_PIN_INT0_SHIFT)) & SYSCON_STARTERP_PIN_INT0_MASK) -#define SYSCON_STARTERP_PIN_INT1_MASK (0x20U) -#define SYSCON_STARTERP_PIN_INT1_SHIFT (5U) -#define SYSCON_STARTERP_PIN_INT1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_PIN_INT1_SHIFT)) & SYSCON_STARTERP_PIN_INT1_MASK) #define SYSCON_STARTERP_CTIMER4_MASK (0x20U) #define SYSCON_STARTERP_CTIMER4_SHIFT (5U) #define SYSCON_STARTERP_CTIMER4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_CTIMER4_SHIFT)) & SYSCON_STARTERP_CTIMER4_MASK) +#define SYSCON_STARTERP_PIN_INT1_MASK (0x20U) +#define SYSCON_STARTERP_PIN_INT1_SHIFT (5U) +#define SYSCON_STARTERP_PIN_INT1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_PIN_INT1_SHIFT)) & SYSCON_STARTERP_PIN_INT1_MASK) #define SYSCON_STARTERP_PIN_INT2_MASK (0x40U) #define SYSCON_STARTERP_PIN_INT2_SHIFT (6U) #define SYSCON_STARTERP_PIN_INT2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_PIN_INT2_SHIFT)) & SYSCON_STARTERP_PIN_INT2_MASK) @@ -5310,27 +5857,33 @@ typedef struct { #define SYSCON_STARTERP_MAILBOX_MASK (0x80000000U) #define SYSCON_STARTERP_MAILBOX_SHIFT (31U) #define SYSCON_STARTERP_MAILBOX(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_MAILBOX_SHIFT)) & SYSCON_STARTERP_MAILBOX_MASK) +/*! @} */ /* The count of SYSCON_STARTERP */ #define SYSCON_STARTERP_COUNT (2U) /*! @name STARTERSET - Set bits in STARTERn */ +/*! @{ */ #define SYSCON_STARTERSET_START_SET_MASK (0xFFFFFFFFU) #define SYSCON_STARTERSET_START_SET_SHIFT (0U) #define SYSCON_STARTERSET_START_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_START_SET_SHIFT)) & SYSCON_STARTERSET_START_SET_MASK) +/*! @} */ /* The count of SYSCON_STARTERSET */ #define SYSCON_STARTERSET_COUNT (2U) /*! @name STARTERCLR - Clear bits in STARTERn */ +/*! @{ */ #define SYSCON_STARTERCLR_START_CLR_MASK (0xFFFFFFFFU) #define SYSCON_STARTERCLR_START_CLR_SHIFT (0U) #define SYSCON_STARTERCLR_START_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_START_CLR_SHIFT)) & SYSCON_STARTERCLR_START_CLR_MASK) +/*! @} */ /* The count of SYSCON_STARTERCLR */ #define SYSCON_STARTERCLR_COUNT (2U) /*! @name HWWAKE - Configures special cases of hardware wake-up */ +/*! @{ */ #define SYSCON_HWWAKE_FORCEWAKE_MASK (0x1U) #define SYSCON_HWWAKE_FORCEWAKE_SHIFT (0U) #define SYSCON_HWWAKE_FORCEWAKE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_HWWAKE_FORCEWAKE_SHIFT)) & SYSCON_HWWAKE_FORCEWAKE_MASK) @@ -5343,38 +5896,46 @@ typedef struct { #define SYSCON_HWWAKE_WAKEDMA_MASK (0x8U) #define SYSCON_HWWAKE_WAKEDMA_SHIFT (3U) #define SYSCON_HWWAKE_WAKEDMA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_HWWAKE_WAKEDMA_SHIFT)) & SYSCON_HWWAKE_WAKEDMA_MASK) +/*! @} */ -/*! @name CPCTRL - CPU Control for multiple processors */ -#define SYSCON_CPCTRL_MASTERCPU_MASK (0x1U) -#define SYSCON_CPCTRL_MASTERCPU_SHIFT (0U) -#define SYSCON_CPCTRL_MASTERCPU(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPCTRL_MASTERCPU_SHIFT)) & SYSCON_CPCTRL_MASTERCPU_MASK) -#define SYSCON_CPCTRL_CM4CLKEN_MASK (0x4U) -#define SYSCON_CPCTRL_CM4CLKEN_SHIFT (2U) -#define SYSCON_CPCTRL_CM4CLKEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPCTRL_CM4CLKEN_SHIFT)) & SYSCON_CPCTRL_CM4CLKEN_MASK) -#define SYSCON_CPCTRL_CM0CLKEN_MASK (0x8U) -#define SYSCON_CPCTRL_CM0CLKEN_SHIFT (3U) -#define SYSCON_CPCTRL_CM0CLKEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPCTRL_CM0CLKEN_SHIFT)) & SYSCON_CPCTRL_CM0CLKEN_MASK) -#define SYSCON_CPCTRL_CM4RSTEN_MASK (0x10U) -#define SYSCON_CPCTRL_CM4RSTEN_SHIFT (4U) -#define SYSCON_CPCTRL_CM4RSTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPCTRL_CM4RSTEN_SHIFT)) & SYSCON_CPCTRL_CM4RSTEN_MASK) -#define SYSCON_CPCTRL_CM0RSTEN_MASK (0x20U) -#define SYSCON_CPCTRL_CM0RSTEN_SHIFT (5U) -#define SYSCON_CPCTRL_CM0RSTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPCTRL_CM0RSTEN_SHIFT)) & SYSCON_CPCTRL_CM0RSTEN_MASK) -#define SYSCON_CPCTRL_POWERCPU_MASK (0x40U) -#define SYSCON_CPCTRL_POWERCPU_SHIFT (6U) -#define SYSCON_CPCTRL_POWERCPU(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPCTRL_POWERCPU_SHIFT)) & SYSCON_CPCTRL_POWERCPU_MASK) +/*! @name CPUCTRL - CPU Control for multiple processors */ +/*! @{ */ +#define SYSCON_CPUCTRL_MASTERCPU_MASK (0x1U) +#define SYSCON_CPUCTRL_MASTERCPU_SHIFT (0U) +#define SYSCON_CPUCTRL_MASTERCPU(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPUCTRL_MASTERCPU_SHIFT)) & SYSCON_CPUCTRL_MASTERCPU_MASK) +#define SYSCON_CPUCTRL_CM4CLKEN_MASK (0x4U) +#define SYSCON_CPUCTRL_CM4CLKEN_SHIFT (2U) +#define SYSCON_CPUCTRL_CM4CLKEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPUCTRL_CM4CLKEN_SHIFT)) & SYSCON_CPUCTRL_CM4CLKEN_MASK) +#define SYSCON_CPUCTRL_CM0CLKEN_MASK (0x8U) +#define SYSCON_CPUCTRL_CM0CLKEN_SHIFT (3U) +#define SYSCON_CPUCTRL_CM0CLKEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPUCTRL_CM0CLKEN_SHIFT)) & SYSCON_CPUCTRL_CM0CLKEN_MASK) +#define SYSCON_CPUCTRL_CM4RSTEN_MASK (0x10U) +#define SYSCON_CPUCTRL_CM4RSTEN_SHIFT (4U) +#define SYSCON_CPUCTRL_CM4RSTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPUCTRL_CM4RSTEN_SHIFT)) & SYSCON_CPUCTRL_CM4RSTEN_MASK) +#define SYSCON_CPUCTRL_CM0RSTEN_MASK (0x20U) +#define SYSCON_CPUCTRL_CM0RSTEN_SHIFT (5U) +#define SYSCON_CPUCTRL_CM0RSTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPUCTRL_CM0RSTEN_SHIFT)) & SYSCON_CPUCTRL_CM0RSTEN_MASK) +#define SYSCON_CPUCTRL_POWERCPU_MASK (0x40U) +#define SYSCON_CPUCTRL_POWERCPU_SHIFT (6U) +#define SYSCON_CPUCTRL_POWERCPU(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPUCTRL_POWERCPU_SHIFT)) & SYSCON_CPUCTRL_POWERCPU_MASK) +/*! @} */ /*! @name CPBOOT - Coprocessor Boot Address */ +/*! @{ */ #define SYSCON_CPBOOT_BOOTADDR_MASK (0xFFFFFFFFU) #define SYSCON_CPBOOT_BOOTADDR_SHIFT (0U) #define SYSCON_CPBOOT_BOOTADDR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPBOOT_BOOTADDR_SHIFT)) & SYSCON_CPBOOT_BOOTADDR_MASK) +/*! @} */ /*! @name CPSTACK - Coprocessor Stack Address */ +/*! @{ */ #define SYSCON_CPSTACK_STACKADDR_MASK (0xFFFFFFFFU) #define SYSCON_CPSTACK_STACKADDR_SHIFT (0U) #define SYSCON_CPSTACK_STACKADDR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPSTACK_STACKADDR_SHIFT)) & SYSCON_CPSTACK_STACKADDR_MASK) +/*! @} */ /*! @name CPSTAT - Coprocessor Status */ +/*! @{ */ #define SYSCON_CPSTAT_CM4SLEEPING_MASK (0x1U) #define SYSCON_CPSTAT_CM4SLEEPING_SHIFT (0U) #define SYSCON_CPSTAT_CM4SLEEPING(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPSTAT_CM4SLEEPING_SHIFT)) & SYSCON_CPSTAT_CM4SLEEPING_MASK) @@ -5387,8 +5948,10 @@ typedef struct { #define SYSCON_CPSTAT_CM0LOCKUP_MASK (0x8U) #define SYSCON_CPSTAT_CM0LOCKUP_SHIFT (3U) #define SYSCON_CPSTAT_CM0LOCKUP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPSTAT_CM0LOCKUP_SHIFT)) & SYSCON_CPSTAT_CM0LOCKUP_MASK) +/*! @} */ /*! @name AUTOCGOR - Auto Clock-Gate Override Register */ +/*! @{ */ #define SYSCON_AUTOCGOR_RAM0X_MASK (0x2U) #define SYSCON_AUTOCGOR_RAM0X_SHIFT (1U) #define SYSCON_AUTOCGOR_RAM0X(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCGOR_RAM0X_SHIFT)) & SYSCON_AUTOCGOR_RAM0X_MASK) @@ -5398,23 +5961,31 @@ typedef struct { #define SYSCON_AUTOCGOR_RAM2_MASK (0x8U) #define SYSCON_AUTOCGOR_RAM2_SHIFT (3U) #define SYSCON_AUTOCGOR_RAM2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCGOR_RAM2_SHIFT)) & SYSCON_AUTOCGOR_RAM2_MASK) +/*! @} */ /*! @name JTAGIDCODE - JTAG ID code register */ +/*! @{ */ #define SYSCON_JTAGIDCODE_JTAGID_MASK (0xFFFFFFFFU) #define SYSCON_JTAGIDCODE_JTAGID_SHIFT (0U) #define SYSCON_JTAGIDCODE_JTAGID(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_JTAGIDCODE_JTAGID_SHIFT)) & SYSCON_JTAGIDCODE_JTAGID_MASK) +/*! @} */ /*! @name DEVICE_ID0 - Part ID register */ +/*! @{ */ #define SYSCON_DEVICE_ID0_PARTID_MASK (0xFFFFFFFFU) #define SYSCON_DEVICE_ID0_PARTID_SHIFT (0U) #define SYSCON_DEVICE_ID0_PARTID(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEVICE_ID0_PARTID_SHIFT)) & SYSCON_DEVICE_ID0_PARTID_MASK) +/*! @} */ /*! @name DEVICE_ID1 - Boot ROM and die revision register */ +/*! @{ */ #define SYSCON_DEVICE_ID1_REVID_MASK (0xFFFFFFFFU) #define SYSCON_DEVICE_ID1_REVID_SHIFT (0U) #define SYSCON_DEVICE_ID1_REVID(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEVICE_ID1_REVID_SHIFT)) & SYSCON_DEVICE_ID1_REVID_MASK) +/*! @} */ /*! @name BODCTRL - Brown-Out Detect control */ +/*! @{ */ #define SYSCON_BODCTRL_BODRSTLEV_MASK (0x3U) #define SYSCON_BODCTRL_BODRSTLEV_SHIFT (0U) #define SYSCON_BODCTRL_BODRSTLEV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_BODCTRL_BODRSTLEV_SHIFT)) & SYSCON_BODCTRL_BODRSTLEV_MASK) @@ -5433,6 +6004,7 @@ typedef struct { #define SYSCON_BODCTRL_BODINTSTAT_MASK (0x80U) #define SYSCON_BODCTRL_BODINTSTAT_SHIFT (7U) #define SYSCON_BODCTRL_BODINTSTAT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_BODCTRL_BODINTSTAT_SHIFT)) & SYSCON_BODCTRL_BODINTSTAT_MASK) +/*! @} */ /*! @@ -5502,6 +6074,7 @@ typedef struct { */ /*! @name CFG - USART Configuration register. Basic USART configuration settings that typically are not changed during operation. */ +/*! @{ */ #define USART_CFG_ENABLE_MASK (0x1U) #define USART_CFG_ENABLE_SHIFT (0U) #define USART_CFG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_ENABLE_SHIFT)) & USART_CFG_ENABLE_MASK) @@ -5556,8 +6129,10 @@ typedef struct { #define USART_CFG_TXPOL_MASK (0x800000U) #define USART_CFG_TXPOL_SHIFT (23U) #define USART_CFG_TXPOL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_TXPOL_SHIFT)) & USART_CFG_TXPOL_MASK) +/*! @} */ /*! @name CTL - USART Control register. USART control settings that are more likely to change during operation. */ +/*! @{ */ #define USART_CTL_TXBRKEN_MASK (0x2U) #define USART_CTL_TXBRKEN_SHIFT (1U) #define USART_CTL_TXBRKEN(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_TXBRKEN_SHIFT)) & USART_CTL_TXBRKEN_MASK) @@ -5576,8 +6151,10 @@ typedef struct { #define USART_CTL_AUTOBAUD_MASK (0x10000U) #define USART_CTL_AUTOBAUD_SHIFT (16U) #define USART_CTL_AUTOBAUD(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_AUTOBAUD_SHIFT)) & USART_CTL_AUTOBAUD_MASK) +/*! @} */ /*! @name STAT - USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them. */ +/*! @{ */ #define USART_STAT_RXIDLE_MASK (0x2U) #define USART_STAT_RXIDLE_SHIFT (1U) #define USART_STAT_RXIDLE(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_RXIDLE_SHIFT)) & USART_STAT_RXIDLE_MASK) @@ -5614,8 +6191,10 @@ typedef struct { #define USART_STAT_ABERR_MASK (0x10000U) #define USART_STAT_ABERR_SHIFT (16U) #define USART_STAT_ABERR(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_ABERR_SHIFT)) & USART_STAT_ABERR_MASK) +/*! @} */ /*! @name INTENSET - Interrupt Enable read and Set register for USART (not FIFO) status. Contains individual interrupt enable bits for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set. */ +/*! @{ */ #define USART_INTENSET_TXIDLEEN_MASK (0x8U) #define USART_INTENSET_TXIDLEEN_SHIFT (3U) #define USART_INTENSET_TXIDLEEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_TXIDLEEN_SHIFT)) & USART_INTENSET_TXIDLEEN_MASK) @@ -5643,8 +6222,10 @@ typedef struct { #define USART_INTENSET_ABERREN_MASK (0x10000U) #define USART_INTENSET_ABERREN_SHIFT (16U) #define USART_INTENSET_ABERREN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_ABERREN_SHIFT)) & USART_INTENSET_ABERREN_MASK) +/*! @} */ /*! @name INTENCLR - Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared. */ +/*! @{ */ #define USART_INTENCLR_TXIDLECLR_MASK (0x8U) #define USART_INTENCLR_TXIDLECLR_SHIFT (3U) #define USART_INTENCLR_TXIDLECLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_TXIDLECLR_SHIFT)) & USART_INTENCLR_TXIDLECLR_MASK) @@ -5672,13 +6253,17 @@ typedef struct { #define USART_INTENCLR_ABERRCLR_MASK (0x10000U) #define USART_INTENCLR_ABERRCLR_SHIFT (16U) #define USART_INTENCLR_ABERRCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_ABERRCLR_SHIFT)) & USART_INTENCLR_ABERRCLR_MASK) +/*! @} */ /*! @name BRG - Baud Rate Generator register. 16-bit integer baud rate divisor value. */ +/*! @{ */ #define USART_BRG_BRGVAL_MASK (0xFFFFU) #define USART_BRG_BRGVAL_SHIFT (0U) #define USART_BRG_BRGVAL(x) (((uint32_t)(((uint32_t)(x)) << USART_BRG_BRGVAL_SHIFT)) & USART_BRG_BRGVAL_MASK) +/*! @} */ /*! @name INTSTAT - Interrupt status register. Reflects interrupts that are currently enabled. */ +/*! @{ */ #define USART_INTSTAT_TXIDLE_MASK (0x8U) #define USART_INTSTAT_TXIDLE_SHIFT (3U) #define USART_INTSTAT_TXIDLE(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_TXIDLE_SHIFT)) & USART_INTSTAT_TXIDLE_MASK) @@ -5706,18 +6291,24 @@ typedef struct { #define USART_INTSTAT_ABERRINT_MASK (0x10000U) #define USART_INTSTAT_ABERRINT_SHIFT (16U) #define USART_INTSTAT_ABERRINT(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_ABERRINT_SHIFT)) & USART_INTSTAT_ABERRINT_MASK) +/*! @} */ /*! @name OSR - Oversample selection register for asynchronous communication. */ +/*! @{ */ #define USART_OSR_OSRVAL_MASK (0xFU) #define USART_OSR_OSRVAL_SHIFT (0U) #define USART_OSR_OSRVAL(x) (((uint32_t)(((uint32_t)(x)) << USART_OSR_OSRVAL_SHIFT)) & USART_OSR_OSRVAL_MASK) +/*! @} */ /*! @name ADDR - Address register for automatic address matching. */ +/*! @{ */ #define USART_ADDR_ADDRESS_MASK (0xFFU) #define USART_ADDR_ADDRESS_SHIFT (0U) #define USART_ADDR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << USART_ADDR_ADDRESS_SHIFT)) & USART_ADDR_ADDRESS_MASK) +/*! @} */ /*! @name FIFOCFG - FIFO configuration and enable register. */ +/*! @{ */ #define USART_FIFOCFG_ENABLETX_MASK (0x1U) #define USART_FIFOCFG_ENABLETX_SHIFT (0U) #define USART_FIFOCFG_ENABLETX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_ENABLETX_SHIFT)) & USART_FIFOCFG_ENABLETX_MASK) @@ -5745,8 +6336,10 @@ typedef struct { #define USART_FIFOCFG_EMPTYRX_MASK (0x20000U) #define USART_FIFOCFG_EMPTYRX_SHIFT (17U) #define USART_FIFOCFG_EMPTYRX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_EMPTYRX_SHIFT)) & USART_FIFOCFG_EMPTYRX_MASK) +/*! @} */ /*! @name FIFOSTAT - FIFO status register. */ +/*! @{ */ #define USART_FIFOSTAT_TXERR_MASK (0x1U) #define USART_FIFOSTAT_TXERR_SHIFT (0U) #define USART_FIFOSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_TXERR_SHIFT)) & USART_FIFOSTAT_TXERR_MASK) @@ -5774,8 +6367,10 @@ typedef struct { #define USART_FIFOSTAT_RXLVL_MASK (0x1F0000U) #define USART_FIFOSTAT_RXLVL_SHIFT (16U) #define USART_FIFOSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_RXLVL_SHIFT)) & USART_FIFOSTAT_RXLVL_MASK) +/*! @} */ /*! @name FIFOTRIG - FIFO trigger settings for interrupt and DMA request. */ +/*! @{ */ #define USART_FIFOTRIG_TXLVLENA_MASK (0x1U) #define USART_FIFOTRIG_TXLVLENA_SHIFT (0U) #define USART_FIFOTRIG_TXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOTRIG_TXLVLENA_SHIFT)) & USART_FIFOTRIG_TXLVLENA_MASK) @@ -5788,8 +6383,10 @@ typedef struct { #define USART_FIFOTRIG_RXLVL_MASK (0xF0000U) #define USART_FIFOTRIG_RXLVL_SHIFT (16U) #define USART_FIFOTRIG_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOTRIG_RXLVL_SHIFT)) & USART_FIFOTRIG_RXLVL_MASK) +/*! @} */ /*! @name FIFOINTENSET - FIFO interrupt enable set (enable) and read register. */ +/*! @{ */ #define USART_FIFOINTENSET_TXERR_MASK (0x1U) #define USART_FIFOINTENSET_TXERR_SHIFT (0U) #define USART_FIFOINTENSET_TXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENSET_TXERR_SHIFT)) & USART_FIFOINTENSET_TXERR_MASK) @@ -5802,8 +6399,10 @@ typedef struct { #define USART_FIFOINTENSET_RXLVL_MASK (0x8U) #define USART_FIFOINTENSET_RXLVL_SHIFT (3U) #define USART_FIFOINTENSET_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENSET_RXLVL_SHIFT)) & USART_FIFOINTENSET_RXLVL_MASK) +/*! @} */ /*! @name FIFOINTENCLR - FIFO interrupt enable clear (disable) and read register. */ +/*! @{ */ #define USART_FIFOINTENCLR_TXERR_MASK (0x1U) #define USART_FIFOINTENCLR_TXERR_SHIFT (0U) #define USART_FIFOINTENCLR_TXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENCLR_TXERR_SHIFT)) & USART_FIFOINTENCLR_TXERR_MASK) @@ -5816,8 +6415,10 @@ typedef struct { #define USART_FIFOINTENCLR_RXLVL_MASK (0x8U) #define USART_FIFOINTENCLR_RXLVL_SHIFT (3U) #define USART_FIFOINTENCLR_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENCLR_RXLVL_SHIFT)) & USART_FIFOINTENCLR_RXLVL_MASK) +/*! @} */ /*! @name FIFOINTSTAT - FIFO interrupt status register. */ +/*! @{ */ #define USART_FIFOINTSTAT_TXERR_MASK (0x1U) #define USART_FIFOINTSTAT_TXERR_SHIFT (0U) #define USART_FIFOINTSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_TXERR_SHIFT)) & USART_FIFOINTSTAT_TXERR_MASK) @@ -5833,13 +6434,17 @@ typedef struct { #define USART_FIFOINTSTAT_PERINT_MASK (0x10U) #define USART_FIFOINTSTAT_PERINT_SHIFT (4U) #define USART_FIFOINTSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_PERINT_SHIFT)) & USART_FIFOINTSTAT_PERINT_MASK) +/*! @} */ /*! @name FIFOWR - FIFO write data. */ +/*! @{ */ #define USART_FIFOWR_TXDATA_MASK (0x1FFU) #define USART_FIFOWR_TXDATA_SHIFT (0U) #define USART_FIFOWR_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOWR_TXDATA_SHIFT)) & USART_FIFOWR_TXDATA_MASK) +/*! @} */ /*! @name FIFORD - FIFO read data. */ +/*! @{ */ #define USART_FIFORD_RXDATA_MASK (0x1FFU) #define USART_FIFORD_RXDATA_SHIFT (0U) #define USART_FIFORD_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORD_RXDATA_SHIFT)) & USART_FIFORD_RXDATA_MASK) @@ -5852,8 +6457,10 @@ typedef struct { #define USART_FIFORD_RXNOISE_MASK (0x8000U) #define USART_FIFORD_RXNOISE_SHIFT (15U) #define USART_FIFORD_RXNOISE(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORD_RXNOISE_SHIFT)) & USART_FIFORD_RXNOISE_MASK) +/*! @} */ /*! @name FIFORDNOPOP - FIFO data read with no FIFO pop. */ +/*! @{ */ #define USART_FIFORDNOPOP_RXDATA_MASK (0x1FFU) #define USART_FIFORDNOPOP_RXDATA_SHIFT (0U) #define USART_FIFORDNOPOP_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORDNOPOP_RXDATA_SHIFT)) & USART_FIFORDNOPOP_RXDATA_MASK) @@ -5866,6 +6473,7 @@ typedef struct { #define USART_FIFORDNOPOP_RXNOISE_MASK (0x8000U) #define USART_FIFORDNOPOP_RXNOISE_SHIFT (15U) #define USART_FIFORDNOPOP_RXNOISE(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORDNOPOP_RXNOISE_SHIFT)) & USART_FIFORDNOPOP_RXNOISE_MASK) +/*! @} */ /*! @@ -5954,6 +6562,7 @@ typedef struct { */ /*! @name DEVCMDSTAT - USB Device Command/Status register */ +/*! @{ */ #define USB_DEVCMDSTAT_DEV_ADDR_MASK (0x7FU) #define USB_DEVCMDSTAT_DEV_ADDR_SHIFT (0U) #define USB_DEVCMDSTAT_DEV_ADDR(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DEV_ADDR_SHIFT)) & USB_DEVCMDSTAT_DEV_ADDR_MASK) @@ -6005,26 +6614,34 @@ typedef struct { #define USB_DEVCMDSTAT_VBUSDEBOUNCED_MASK (0x10000000U) #define USB_DEVCMDSTAT_VBUSDEBOUNCED_SHIFT (28U) #define USB_DEVCMDSTAT_VBUSDEBOUNCED(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_VBUSDEBOUNCED_SHIFT)) & USB_DEVCMDSTAT_VBUSDEBOUNCED_MASK) +/*! @} */ /*! @name INFO - USB Info register */ +/*! @{ */ #define USB_INFO_FRAME_NR_MASK (0x7FFU) #define USB_INFO_FRAME_NR_SHIFT (0U) #define USB_INFO_FRAME_NR(x) (((uint32_t)(((uint32_t)(x)) << USB_INFO_FRAME_NR_SHIFT)) & USB_INFO_FRAME_NR_MASK) #define USB_INFO_ERR_CODE_MASK (0x7800U) #define USB_INFO_ERR_CODE_SHIFT (11U) #define USB_INFO_ERR_CODE(x) (((uint32_t)(((uint32_t)(x)) << USB_INFO_ERR_CODE_SHIFT)) & USB_INFO_ERR_CODE_MASK) +/*! @} */ /*! @name EPLISTSTART - USB EP Command/Status List start address */ +/*! @{ */ #define USB_EPLISTSTART_EP_LIST_MASK (0xFFFFFF00U) #define USB_EPLISTSTART_EP_LIST_SHIFT (8U) #define USB_EPLISTSTART_EP_LIST(x) (((uint32_t)(((uint32_t)(x)) << USB_EPLISTSTART_EP_LIST_SHIFT)) & USB_EPLISTSTART_EP_LIST_MASK) +/*! @} */ /*! @name DATABUFSTART - USB Data buffer start address */ +/*! @{ */ #define USB_DATABUFSTART_DA_BUF_MASK (0xFFC00000U) #define USB_DATABUFSTART_DA_BUF_SHIFT (22U) #define USB_DATABUFSTART_DA_BUF(x) (((uint32_t)(((uint32_t)(x)) << USB_DATABUFSTART_DA_BUF_SHIFT)) & USB_DATABUFSTART_DA_BUF_MASK) +/*! @} */ /*! @name LPM - USB Link Power Management register */ +/*! @{ */ #define USB_LPM_HIRD_HW_MASK (0xFU) #define USB_LPM_HIRD_HW_SHIFT (0U) #define USB_LPM_HIRD_HW(x) (((uint32_t)(((uint32_t)(x)) << USB_LPM_HIRD_HW_SHIFT)) & USB_LPM_HIRD_HW_MASK) @@ -6034,23 +6651,31 @@ typedef struct { #define USB_LPM_DATA_PENDING_MASK (0x100U) #define USB_LPM_DATA_PENDING_SHIFT (8U) #define USB_LPM_DATA_PENDING(x) (((uint32_t)(((uint32_t)(x)) << USB_LPM_DATA_PENDING_SHIFT)) & USB_LPM_DATA_PENDING_MASK) +/*! @} */ /*! @name EPSKIP - USB Endpoint skip */ +/*! @{ */ #define USB_EPSKIP_SKIP_MASK (0x3FFFFFFFU) #define USB_EPSKIP_SKIP_SHIFT (0U) #define USB_EPSKIP_SKIP(x) (((uint32_t)(((uint32_t)(x)) << USB_EPSKIP_SKIP_SHIFT)) & USB_EPSKIP_SKIP_MASK) +/*! @} */ /*! @name EPINUSE - USB Endpoint Buffer in use */ +/*! @{ */ #define USB_EPINUSE_BUF_MASK (0x3FCU) #define USB_EPINUSE_BUF_SHIFT (2U) #define USB_EPINUSE_BUF(x) (((uint32_t)(((uint32_t)(x)) << USB_EPINUSE_BUF_SHIFT)) & USB_EPINUSE_BUF_MASK) +/*! @} */ /*! @name EPBUFCFG - USB Endpoint Buffer Configuration register */ +/*! @{ */ #define USB_EPBUFCFG_BUF_SB_MASK (0x3FCU) #define USB_EPBUFCFG_BUF_SB_SHIFT (2U) #define USB_EPBUFCFG_BUF_SB(x) (((uint32_t)(((uint32_t)(x)) << USB_EPBUFCFG_BUF_SB_SHIFT)) & USB_EPBUFCFG_BUF_SB_MASK) +/*! @} */ /*! @name INTSTAT - USB interrupt status register */ +/*! @{ */ #define USB_INTSTAT_EP0OUT_MASK (0x1U) #define USB_INTSTAT_EP0OUT_SHIFT (0U) #define USB_INTSTAT_EP0OUT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP0OUT_SHIFT)) & USB_INTSTAT_EP0OUT_MASK) @@ -6087,8 +6712,10 @@ typedef struct { #define USB_INTSTAT_DEV_INT_MASK (0x80000000U) #define USB_INTSTAT_DEV_INT_SHIFT (31U) #define USB_INTSTAT_DEV_INT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_DEV_INT_SHIFT)) & USB_INTSTAT_DEV_INT_MASK) +/*! @} */ /*! @name INTEN - USB interrupt enable register */ +/*! @{ */ #define USB_INTEN_EP_INT_EN_MASK (0x3FFU) #define USB_INTEN_EP_INT_EN_SHIFT (0U) #define USB_INTEN_EP_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTEN_EP_INT_EN_SHIFT)) & USB_INTEN_EP_INT_EN_MASK) @@ -6098,8 +6725,10 @@ typedef struct { #define USB_INTEN_DEV_INT_EN_MASK (0x80000000U) #define USB_INTEN_DEV_INT_EN_SHIFT (31U) #define USB_INTEN_DEV_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTEN_DEV_INT_EN_SHIFT)) & USB_INTEN_DEV_INT_EN_MASK) +/*! @} */ /*! @name INTSETSTAT - USB set interrupt status register */ +/*! @{ */ #define USB_INTSETSTAT_EP_SET_INT_MASK (0x3FFU) #define USB_INTSETSTAT_EP_SET_INT_SHIFT (0U) #define USB_INTSETSTAT_EP_SET_INT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSETSTAT_EP_SET_INT_SHIFT)) & USB_INTSETSTAT_EP_SET_INT_MASK) @@ -6109,11 +6738,14 @@ typedef struct { #define USB_INTSETSTAT_DEV_SET_INT_MASK (0x80000000U) #define USB_INTSETSTAT_DEV_SET_INT_SHIFT (31U) #define USB_INTSETSTAT_DEV_SET_INT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSETSTAT_DEV_SET_INT_SHIFT)) & USB_INTSETSTAT_DEV_SET_INT_MASK) +/*! @} */ /*! @name EPTOGGLE - USB Endpoint toggle register */ +/*! @{ */ #define USB_EPTOGGLE_TOGGLE_MASK (0x3FFU) #define USB_EPTOGGLE_TOGGLE_SHIFT (0U) #define USB_EPTOGGLE_TOGGLE(x) (((uint32_t)(((uint32_t)(x)) << USB_EPTOGGLE_TOGGLE_SHIFT)) & USB_EPTOGGLE_TOGGLE_MASK) +/*! @} */ /*! @@ -6167,22 +6799,27 @@ typedef struct { */ /*! @name CTRL - Control register. */ +/*! @{ */ #define UTICK_CTRL_DELAYVAL_MASK (0x7FFFFFFFU) #define UTICK_CTRL_DELAYVAL_SHIFT (0U) #define UTICK_CTRL_DELAYVAL(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CTRL_DELAYVAL_SHIFT)) & UTICK_CTRL_DELAYVAL_MASK) #define UTICK_CTRL_REPEAT_MASK (0x80000000U) #define UTICK_CTRL_REPEAT_SHIFT (31U) #define UTICK_CTRL_REPEAT(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CTRL_REPEAT_SHIFT)) & UTICK_CTRL_REPEAT_MASK) +/*! @} */ /*! @name STAT - Status register. */ +/*! @{ */ #define UTICK_STAT_INTR_MASK (0x1U) #define UTICK_STAT_INTR_SHIFT (0U) #define UTICK_STAT_INTR(x) (((uint32_t)(((uint32_t)(x)) << UTICK_STAT_INTR_SHIFT)) & UTICK_STAT_INTR_MASK) #define UTICK_STAT_ACTIVE_MASK (0x2U) #define UTICK_STAT_ACTIVE_SHIFT (1U) #define UTICK_STAT_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << UTICK_STAT_ACTIVE_SHIFT)) & UTICK_STAT_ACTIVE_MASK) +/*! @} */ /*! @name CFG - Capture configuration register. */ +/*! @{ */ #define UTICK_CFG_CAPEN0_MASK (0x1U) #define UTICK_CFG_CAPEN0_SHIFT (0U) #define UTICK_CFG_CAPEN0(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN0_SHIFT)) & UTICK_CFG_CAPEN0_MASK) @@ -6207,8 +6844,10 @@ typedef struct { #define UTICK_CFG_CAPPOL3_MASK (0x800U) #define UTICK_CFG_CAPPOL3_SHIFT (11U) #define UTICK_CFG_CAPPOL3(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL3_SHIFT)) & UTICK_CFG_CAPPOL3_MASK) +/*! @} */ /*! @name CAPCLR - Capture clear register. */ +/*! @{ */ #define UTICK_CAPCLR_CAPCLR0_MASK (0x1U) #define UTICK_CAPCLR_CAPCLR0_SHIFT (0U) #define UTICK_CAPCLR_CAPCLR0(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR0_SHIFT)) & UTICK_CAPCLR_CAPCLR0_MASK) @@ -6221,14 +6860,17 @@ typedef struct { #define UTICK_CAPCLR_CAPCLR3_MASK (0x8U) #define UTICK_CAPCLR_CAPCLR3_SHIFT (3U) #define UTICK_CAPCLR_CAPCLR3(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR3_SHIFT)) & UTICK_CAPCLR_CAPCLR3_MASK) +/*! @} */ /*! @name CAP - Capture register . */ +/*! @{ */ #define UTICK_CAP_CAP_VALUE_MASK (0x7FFFFFFFU) #define UTICK_CAP_CAP_VALUE_SHIFT (0U) #define UTICK_CAP_CAP_VALUE(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAP_CAP_VALUE_SHIFT)) & UTICK_CAP_CAP_VALUE_MASK) #define UTICK_CAP_VALID_MASK (0x80000000U) #define UTICK_CAP_VALID_SHIFT (31U) #define UTICK_CAP_VALID(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAP_VALID_SHIFT)) & UTICK_CAP_VALID_MASK) +/*! @} */ /* The count of UTICK_CAP */ #define UTICK_CAP_COUNT (4U) @@ -6286,6 +6928,7 @@ typedef struct { */ /*! @name MOD - Watchdog mode register. This register contains the basic mode and status of the Watchdog Timer. */ +/*! @{ */ #define WWDT_MOD_WDEN_MASK (0x1U) #define WWDT_MOD_WDEN_SHIFT (0U) #define WWDT_MOD_WDEN(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDEN_SHIFT)) & WWDT_MOD_WDEN_MASK) @@ -6304,31 +6947,42 @@ typedef struct { #define WWDT_MOD_LOCK_MASK (0x20U) #define WWDT_MOD_LOCK_SHIFT (5U) #define WWDT_MOD_LOCK(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_LOCK_SHIFT)) & WWDT_MOD_LOCK_MASK) +/*! @} */ /*! @name TC - Watchdog timer constant register. This 24-bit register determines the time-out value. */ +/*! @{ */ #define WWDT_TC_COUNT_MASK (0xFFFFFFU) #define WWDT_TC_COUNT_SHIFT (0U) #define WWDT_TC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_TC_COUNT_SHIFT)) & WWDT_TC_COUNT_MASK) +/*! @} */ /*! @name FEED - Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in TC. */ +/*! @{ */ #define WWDT_FEED_FEED_MASK (0xFFU) #define WWDT_FEED_FEED_SHIFT (0U) #define WWDT_FEED_FEED(x) (((uint32_t)(((uint32_t)(x)) << WWDT_FEED_FEED_SHIFT)) & WWDT_FEED_FEED_MASK) +/*! @} */ /*! @name TV - Watchdog timer value register. This 24-bit register reads out the current value of the Watchdog timer. */ +/*! @{ */ #define WWDT_TV_COUNT_MASK (0xFFFFFFU) #define WWDT_TV_COUNT_SHIFT (0U) #define WWDT_TV_COUNT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_TV_COUNT_SHIFT)) & WWDT_TV_COUNT_MASK) +/*! @} */ /*! @name WARNINT - Watchdog Warning Interrupt compare value. */ +/*! @{ */ #define WWDT_WARNINT_WARNINT_MASK (0x3FFU) #define WWDT_WARNINT_WARNINT_SHIFT (0U) #define WWDT_WARNINT_WARNINT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_WARNINT_WARNINT_SHIFT)) & WWDT_WARNINT_WARNINT_MASK) +/*! @} */ /*! @name WINDOW - Watchdog Window compare value. */ +/*! @{ */ #define WWDT_WINDOW_WINDOW_MASK (0xFFFFFFU) #define WWDT_WINDOW_WINDOW_SHIFT (0U) #define WWDT_WINDOW_WINDOW(x) (((uint32_t)(((uint32_t)(x)) << WWDT_WINDOW_WINDOW_SHIFT)) & WWDT_WINDOW_WINDOW_MASK) +/*! @} */ /*! @@ -6358,7 +7012,11 @@ typedef struct { */ #if defined(__ARMCC_VERSION) - #pragma pop + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop + #else + #pragma pop + #endif #elif defined(__GNUC__) /* leave anonymous unions enabled */ #elif defined(__IAR_SYSTEMS_ICC__) diff --git a/ext/hal/nxp/mcux/devices/LPC54114/LPC54114_cm4.xml b/ext/hal/nxp/mcux/devices/LPC54114/LPC54114_cm4.xml index 294447f0756..8d7f397bfef 100644 --- a/ext/hal/nxp/mcux/devices/LPC54114/LPC54114_cm4.xml +++ b/ext/hal/nxp/mcux/devices/LPC54114/LPC54114_cm4.xml @@ -1,9 +1,35 @@ - + nxp.com LPC54114_cm4 1.0 - LPC54114J256BD64, LPC54114J256UK49, LPC54113J256BD64, LPC54113J256UK49, LPC54113J128BD64 + LPC54114J256BD64,LPC54114J256UK49 + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +1. Redistributions of source code must retain the above copyright notice, this list + of conditions and the following disclaimer. + +2. Redistributions in binary form must reproduce the above copyright notice, this + list of conditions and the following disclaimer in the documentation and/or + other materials provided with the distribution. + +3. Neither the name of the copyright holder nor the names of its + contributors may be used to endorse or promote products derived from this + software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + CM4 r0p1 @@ -56,35 +82,35 @@ PRI_DCODE Cortex M4 D-Code bus priority. - 0x2 + 2 2 read-write PRI_SYS Cortex M4 System bus priority. - 0x4 + 4 2 read-write PRI_M0 Cortex-M0+ bus priority. Present on selected devices. - 0x6 + 6 2 read-write PRI_USB USB interface priority. - 0x8 + 8 2 read-write PRI_DMA DMA controller priority. - 0xA + 10 2 read-write @@ -109,14 +135,14 @@ SKEW Initial value for the Systick timer. - 0x18 + 24 1 read-write NOREF Initial value for the Systick timer. - 0x19 + 25 1 read-write @@ -141,21 +167,21 @@ IRQM0 The IRQ number of the interrupt that acts as the Non-Maskable Interrupt (NMI) for the Cortex-M0+, if enabled by NMIENM0. Present on selected devices. - 0x8 + 8 6 read-write NMIENM0 Write a 1 to this bit to enable the Non-Maskable Interrupt (NMI) source selected by IRQM0. Present on selected devices. - 0x1E + 30 1 read-write NMIENM4 Write a 1 to this bit to enable the Non-Maskable Interrupt (NMI) source selected by IRQM4. - 0x1F + 31 1 read-write @@ -243,84 +269,84 @@ FLASH_RST Flash controller reset control. 0 = Clear reset to this function. 1 = Assert reset to this function. - 0x7 + 7 1 read-write FMC_RST Flash accelerator reset control. Note that the FMC must not be reset while executing from flash, and must be reconfigured after reset. 0 = Clear reset to this function. 1 = Assert reset to this function. - 0x8 + 8 1 read-write MUX_RST Input mux reset control. 0 = Clear reset to this function. 1 = Assert reset to this function. - 0xB + 11 1 read-write IOCON_RST IOCON reset control. 0 = Clear reset to this function. 1 = Assert reset to this function. - 0xD + 13 1 read-write GPIO0_RST GPIO0 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function. - 0xE + 14 1 read-write GPIO1_RST GPIO1 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function. - 0xF + 15 1 read-write PINT_RST Pin interrupt (PINT) reset control. 0 = Clear reset to this function. 1 = Assert reset to this function. - 0x12 + 18 1 read-write GINT_RST Grouped interrupt (GINT) reset control. 0 = Clear reset to this function. 1 = Assert reset to this function. - 0x13 + 19 1 read-write DMA0_RST DMA0 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function. - 0x14 + 20 1 read-write CRC_RST CRC generator reset control. 0 = Clear reset to this function. 1 = Assert reset to this function. - 0x15 + 21 1 read-write WWDT_RST Watchdog timer reset control. 0 = Clear reset to this function. 1 = Assert reset to this function. - 0x16 + 22 1 read-write ADC0_RST ADC0 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function. - 0x1B + 27 1 read-write @@ -345,105 +371,105 @@ SCT0_RST State configurable timer 0 (SCT0) reset control. 0 = Clear reset to this function. 1 = Assert reset to this function. - 0x2 + 2 1 read-write UTICK0_RST Micro-tick Timer reset control. 0 = Clear reset to this function. 1 = Assert reset to this function. - 0xA + 10 1 read-write FC0_RST Flexcomm 0 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function. - 0xB + 11 1 read-write FC1_RST Flexcomm 1 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function. - 0xC + 12 1 read-write FC2_RST Flexcomm 2 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function. - 0xD + 13 1 read-write FC3_RST Flexcomm 3 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function. - 0xE + 14 1 read-write FC4_RST Flexcomm 4 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function. - 0xF + 15 1 read-write FC5_RST Flexcomm 5 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function. - 0x10 + 16 1 read-write FC6_RST Flexcomm 6 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function. - 0x11 + 17 1 read-write FC7_RST Flexcomm 7 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function. - 0x12 + 18 1 read-write DMIC0_RST Digital microphone interface reset control. 0 = Clear reset to this function. 1 = Assert reset to this function. - 0x13 + 19 1 read-write CTIMER2_RST CTIMER2 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function - 0x16 + 22 1 read-write USB0_RST USB0 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function. - 0x19 + 25 1 read-write CTIMER0_RST CTIMER0 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function. - 0x1A + 26 1 read-write CTIMER1_RST CTIMER1 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function. - 0x1B + 27 1 read-write @@ -520,7 +546,7 @@ EXTRST Status of the external RESET pin. External reset status - 0x1 + 1 1 read-write @@ -539,7 +565,7 @@ WDT Status of the Watchdog reset - 0x2 + 2 1 read-write @@ -558,7 +584,7 @@ BOD Status of the Brown-out detect reset - 0x3 + 3 1 read-write @@ -577,7 +603,7 @@ SYSRST Status of the software system reset - 0x4 + 4 1 read-write @@ -607,119 +633,119 @@ ROM Enables the clock for the Boot ROM. 0 = Disable; 1 = Enable. - 0x1 + 1 1 read-write SRAM1 Enables the clock for SRAM1. 0 = Disable; 1 = Enable. - 0x3 + 3 1 read-write SRAM2 Enables the clock for SRAM2. 0 = Disable; 1 = Enable. - 0x4 + 4 1 read-write FLASH Enables the clock for the flash controller. 0 = Disable; 1 = Enable. This clock is needed for flash programming, not for flash read. - 0x7 + 7 1 read-write FMC Enables the clock for the Flash accelerator. 0 = Disable; 1 = Enable. This clock is needed if the flash is being read. - 0x8 + 8 1 read-write INPUTMUX Enables the clock for the input muxes. 0 = Disable; 1 = Enable. - 0xB + 11 1 read-write IOCON Enables the clock for the IOCON block. 0 = Disable; 1 = Enable. - 0xD + 13 1 read-write GPIO0 Enables the clock for the GPIO0 port registers. 0 = Disable; 1 = Enable. - 0xE + 14 1 read-write GPIO1 Enables the clock for the GPIO1 port registers. 0 = Disable; 1 = Enable. - 0xF + 15 1 read-write PINT Enables the clock for the pin interrupt block.0 = Disable; 1 = Enable. - 0x12 + 18 1 read-write GINT Enables the clock for the grouped pin interrupt block. 0 = Disable; 1 = Enable. - 0x13 + 19 1 read-write DMA0 Enables the clock for the DMA0 controller. 0 = Disable; 1 = Enable. - 0x14 + 20 1 read-write CRC Enables the clock for the CRC engine. 0 = Disable; 1 = Enable. - 0x15 + 21 1 read-write WWDT Enables the clock for the Watchdog Timer. 0 = Disable; 1 = Enable. - 0x16 + 22 1 read-write RTC Enables the bus clock for the RTC. 0 = Disable; 1 = Enable. - 0x17 + 23 1 read-write MAILBOX Enables the clock for the Mailbox. 0 = Disable; 1 = Enable. Present on selected devices - 0x1A + 26 1 read-write ADC0 Enables the clock for the ADC0 register interface. 0 = Disable; 1 = Enable. - 0x1B + 27 1 read-write @@ -744,105 +770,105 @@ SCT0 Enables the clock for SCT0. 0 = Disable; 1 = Enable. - 0x2 + 2 1 read-write UTICK0 Enables the clock for the Micro-tick Timer. 0 = Disable; 1 = Enable. - 0xA + 10 1 read-write FLEXCOMM0 Enables the clock for Flexcomm 0. 0 = Disable; 1 = Enable. - 0xB + 11 1 read-write FLEXCOMM1 Enables the clock for Flexcomm 1. 0 = Disable; 1 = Enable. - 0xC + 12 1 read-write FLEXCOMM2 Enables the clock for Flexcomm 2. 0 = Disable; 1 = Enable. - 0xD + 13 1 read-write FLEXCOMM3 Enables the clock for Flexcomm 3. 0 = Disable; 1 = Enable. - 0xE + 14 1 read-write FLEXCOMM4 Enables the clock for Flexcomm 4. 0 = Disable; 1 = Enable. - 0xF + 15 1 read-write FLEXCOMM5 Enables the clock for Flexcomm 5. 0 = Disable; 1 = Enable. - 0x10 + 16 1 read-write FLEXCOMM6 Enables the clock for Flexcomm 6. 0 = Disable; 1 = Enable. - 0x11 + 17 1 read-write FLEXCOMM7 Enables the clock for Flexcomm 7. 0 = Disable; 1 = Enable. - 0x12 + 18 1 read-write DMIC0 Enables the clock for the digital microphone interface. 0 = Disable; 1 = Enable. - 0x13 + 19 1 read-write CTIMER2 Enables the clock for CTIMER 2. 0 = Disable; 1 = Enable. - 0x16 + 22 1 read-write USB0 Enables the clock for the USB0 interface. 0 = Disable; 1 = Enable. - 0x19 + 25 1 read-write CTIMER0 Enables the clock for timer CTIMER0. 0 = Disable; 1 = Enable. - 0x1A + 26 1 read-write CTIMER1 Enables the clock for timer CTIMER1. 0 = Disable; 1 = Enable. - 0x1B + 27 1 read-write @@ -1399,14 +1425,14 @@ RESET Resets the divider counter. Can be used to make sure a new divider value is used right away rather than completing the previous count. - 0x1D + 29 1 read-write HALT Halts the divider counter. The intent is to allow the divider clock source to be changed without the risk of a glitch at the output. - 0x1E + 30 1 read-write @@ -1418,7 +1444,7 @@ 0x304 32 read-write - 0 + 0x40000000 0x600000FF @@ -1431,14 +1457,14 @@ RESET Resets the divider counter. Can be used to make sure a new divider value is used right away rather than completing the previous count. - 0x1D + 29 1 read-write HALT Halts the divider counter. The intent is to allow the divider clock source to be changed without the risk of a glitch at the output. - 0x1E + 30 1 read-write @@ -1463,14 +1489,14 @@ RESET Resets the divider counter. Can be used to make sure a new divider value is used right away rather than completing the previous count. - 0x1D + 29 1 read-write HALT Halts the divider counter. The intent is to allow the divider clock source to be changed without the risk of a glitch at the output. - 0x1E + 30 1 read-write @@ -1495,14 +1521,14 @@ RESET Resets the divider counter. Can be used to make sure a new divider value is used right away rather than completing the previous count. - 0x1D + 29 1 read-write HALT Halts the divider counter. The intent is to allow the divider clock source to be changed without the risk of a glitch at the output. - 0x1E + 30 1 read-write @@ -1527,14 +1553,14 @@ RESET Resets the divider counter. Can be used to make sure a new divider value is used right away rather than completing the previous count. - 0x1D + 29 1 read-write HALT Halts the divider counter. The intent is to allow the divider clock source to be changed without the risk of a glitch at the output. - 0x1E + 30 1 read-write @@ -1559,14 +1585,14 @@ RESET Resets the divider counter. Can be used to make sure a new divider value is used right away rather than completing the previous count. - 0x1D + 29 1 read-write HALT Halts the divider counter. The intent is to allow the divider clock source to be changed without the risk of a glitch at the output. - 0x1E + 30 1 read-write @@ -1591,14 +1617,14 @@ RESET Resets the divider counter. Can be used to make sure a new divider value is used right away rather than completing the previous count. - 0x1D + 29 1 read-write HALT Halts the divider counter. The intent is to allow the divider clock source to be changed without the risk of a glitch at the output. - 0x1E + 30 1 read-write @@ -1623,7 +1649,7 @@ MULT Numerator of the fractional divider. MULT is equal to the programmed value. - 0x8 + 8 8 read-write @@ -1648,14 +1674,14 @@ RESET Resets the divider counter. Can be used to make sure a new divider value is used right away rather than completing the previous count. - 0x1D + 29 1 read-write HALT Halts the divider counter. The intent is to allow the divider clock source to be changed without the risk of a glitch at the output. - 0x1E + 30 1 read-write @@ -1680,14 +1706,14 @@ RESET Resets the divider counter. Can be used to make sure a new divider value is used right away rather than completing the previous count. - 0x1D + 29 1 read-write HALT Halts the divider counter. The intent is to allow the divider clock source to be changed without the risk of a glitch at the output. - 0x1E + 30 1 read-write @@ -1729,7 +1755,7 @@ DATACFG Data read configuration. This field determines how flash accelerator buffers are used for data accesses. - 0x2 + 2 2 read-write @@ -1753,7 +1779,7 @@ ACCEL Acceleration enable. - 0x4 + 4 1 read-write @@ -1772,7 +1798,7 @@ PREFEN Prefetch enable. - 0x5 + 5 1 read-write @@ -1791,7 +1817,7 @@ PREFOVR Prefetch override. This bit only applies when PREFEN = 1 and a buffered instruction is completing for which the next flash line is not already buffered or being prefetched. - 0x6 + 6 1 read-write @@ -1810,7 +1836,7 @@ FLASHTIM Flash memory access time. The number of system clocks used for flash accesses is equal to FLASHTIM +1. - 0xC + 12 4 read-write @@ -1855,7 +1881,7 @@ POL_CLK USB_NEED_CLK polarity for triggering the USB wake-up interrupt - 0x1 + 1 1 read-write @@ -1922,7 +1948,7 @@ PROG Set this bit to one to initiate a frequency measurement cycle. Hardware clears this bit when the measurement cycle has completed and there is valid capture data in the CAPVAL field (bits 13:0). - 0x1F + 31 1 read-write @@ -1977,7 +2003,7 @@ SEL Select the fro_hf output frequency. This bit can only be changed by software when the WRTRIM bit = 1. Note that the factory trim values are for the 96 MHz FRO only. - 0xE + 14 1 read-write @@ -1996,14 +2022,14 @@ FREQTRIM Frequency trim. Boot code configures this to a device-specific factory trim value for the 96 MHz FRO. If USBCLKADJ = 1, this field is read-only and provides the value resulting from USB rate adjustment. See the USBMODCFG flag regarding reading this field. Application code may adjust this field when USBCLKADJ = 0. A single step of FREQTRIM is roughly equivalent to 0.1% of the selected FRO frequency. - 0x10 + 16 8 read-write USBCLKADJ USB clock adjust mode. - 0x18 + 24 1 read-write @@ -2022,14 +2048,14 @@ USBMODCHG USB Mode value Change flag. When 1, indicates that the USB trim is currently being updated (or is still starting up) and software should wait to read FREQTRIM. Update occurs at most once per millisecond. - 0x19 + 25 1 read-write HSPDCLK High speed clock disable. Allows disabling the highs-speed FRO output if it is not needed. - 0x1E + 30 1 read-write @@ -2048,7 +2074,7 @@ WRTRIM Write Trim value. Must be written to 1 to modify the SEL or TRIM fields, during the same write. This bit always reads as 0. - 0x1F + 31 1 read-write @@ -2060,7 +2086,7 @@ 0x508 32 read-write - 0 + 0xA0 0x3FF @@ -2073,7 +2099,7 @@ FREQSEL Frequency select. Selects the frequency of the oscillator. 0x00 = invalid setting when watchdog oscillator is running 0x01 = 0.4 MHz 0x02 = 0.6 MHz 0x03 = 0.75 MHz 0x04 = 0.9 MHz 0x05 = 1.0 MHz 0x06 = 1.2 MHz 0x07 = 1.3 MHz 0x08 = 1.4 MHz 0x09 = 1.5 MHz 0x0A = 1.6 MHz 0x0B = 1.7 MHz 0x0C = 1.8 MHz 0x0D = 1.9 MHz 0x0E = 2.0 MHz 0x0F = 2.05 MHz 0x10 = 2.1 MHz 0x11 = 2.2 MHz 0x12 = 2.25 MHz 0x13 = 2.3 MHz 0x14 = 2.4 MHz 0x15 = 2.45 MHz 0x16 = 2.5 MHz 0x17 = 2.6 MHz 0x18 = 2.65 MHz 0x19 = 2.7 MHz 0x1A = 2.8 MHz 0x1B = 2.85 MHz 0x1C = 2.9 MHz 0x1D = 2.95 MHz 0x1E = 3.0 MHz 0x1F = 3.05 MHz - 0x5 + 5 5 read-write @@ -2128,21 +2154,21 @@ SELI Bandwidth select I value. - 0x4 + 4 6 read-write SELP Bandwidth select P value - 0xA + 10 5 read-write BYPASS PLL bypass control. - 0xF + 15 1 read-write @@ -2153,7 +2179,7 @@ ENABLED - Bypass enabled. PLL input clock is sent to the PLL post-dividers (default). + Bypass enabled. PLL input clock is sent directly to the PLL output (default). 0x1 @@ -2161,7 +2187,7 @@ BYPASSCCODIV2 Bypass feedback clock divide by 2. - 0x10 + 16 1 read-write @@ -2180,7 +2206,7 @@ UPLIMOFF Disable upper frequency limiter. - 0x11 + 17 1 read-write @@ -2199,7 +2225,7 @@ BANDSEL PLL filter control. Set this bit to one when the spread spectrum controller is disabled or at low frequencies. For spread spectrum mode: SEL_EXT = 0, BANDSEL = 0, and UPLIMOFF = 1. - 0x12 + 18 1 read-write @@ -2218,7 +2244,7 @@ DIRECTI PLL0 direct input enable - 0x13 + 19 1 read-write @@ -2237,7 +2263,7 @@ DIRECTO PLL0 direct output enable. - 0x14 + 20 1 read-write @@ -2292,7 +2318,7 @@ NREQ NDEC reload request. When a 1 is written to this bit, the NDEC value is loaded into the PLL. Must be cleared by software for any subsequent load, or the PLL can be powered down and back up via the PDEN_SYS_PLL bit in the PDRUNCFG register if the NDEC value is changed. - 0xA + 10 1 read-write @@ -2317,7 +2343,7 @@ PREQ PDEC reload request. When a 1 is written to this bit, the PDEC value is loaded into the PLL. Must be cleared by software for any subsequent load, or the PLL can be powered down and back up via the PDEN_SYS_PLL bit in the PDRUNCFG register if the PDEC value is changed. - 0x7 + 7 1 read-write @@ -2342,14 +2368,14 @@ MREQ MDEC reload request. When a 1 is written to this bit, the MDEC value is loaded into the PLL. Must be cleared by software for any subsequent load, or the PLL can be powered down and back up via the PDEN_SYS_PLL bit in the PDRUNCFG register if the MDEC value is changed. - 0x11 + 17 1 read-write SEL_EXT Select spread spectrum mode. Selects the source of the feedback divider value. For normal mode, this must be the value from the MDEC field in this register. For spread spectrum mode: SEL_EXT = 0, BANDSEL = 0, and UPLIMOFF = 1. - 0x12 + 18 1 read-write @@ -2374,35 +2400,35 @@ MDREQ MD reload request. When a 1 is written to this bit, the MD value is loaded into the PLL. This bit is cleared when the load is complete - 0x13 + 19 1 read-write MF Programmable modulation frequency fm = Fref/Nss with Fref = Fin/N 0b000 => Nss = 512 (fm _ 3.9 - 7.8 kHz) 0b001 => Nss _ 384 (fm _ 5.2 - 10.4 kHz) 0b010 => Nss = 256 (fm _ 7.8 - 15.6 kHz) 0b011 => Nss = 128 (fm _ 15.6 - 31.3 kHz) 0b100 => Nss = 64 (fm _ 32.3 - 64.5 kHz) 0b101 => Nss = 32 (fm _ 62.5- 125 kHz) 0b110 => Nss _ 24 (fm _ 83.3- 166.6 kHz) 0b111 => Nss = 16 (fm _ 125- 250 kHz) - 0x14 + 20 3 read-write MR Programmable frequency modulation depth. 0 = no spread. _fmodpk-pk = Fref x k/Fcco = k/MDdec 0b000 -> k = 0 (no spread spectrum) 0b001 => k _ 1 0b010 => k _ 1.5 0b011 => k _ 2 0b100 => k _ 3 0b101 => k _ 4 0b110 => k _ 6 0b111 => k _ 8 - 0x17 + 23 3 read-write MC Modulation waveform control. 0 = no compensation. Compensation for low pass filtering of the PLL to get a triangular modulation at the output of the PLL, giving a flat frequency spectrum. 0b00 => no compensation 0b10 => recommended setting 0b11 => max. compensation - 0x1A + 26 2 read-write PD Spread spectrum power-down. - 0x1C + 28 1 read-write @@ -2421,7 +2447,7 @@ DITHER Select modulation frequency. - 0x1D + 29 1 read-write @@ -2471,140 +2497,140 @@ PDEN_FRO FRO oscillator. 0 = Powered; 1 = Powered down. - 0x4 + 4 1 read-write PD_FLASH Part of flash power control. - 0x5 + 5 1 read-write PDEN_TS Temp sensor. 0 = Powered; 1 = Powered down. - 0x6 + 6 1 read-write PDEN_BOD_RST Brown-out Detect reset. 0 = Powered; 1 = Powered down. - 0x7 + 7 1 read-write PDEN_BOD_INTR Brown-out Detect interrupt. 0 = Powered; 1 = Powered down. - 0x8 + 8 1 read-write PDEN_ADC0 ADC0. 0 = Powered; 1 = Powered down. - 0xA + 10 1 read-write PD_VDDFLASH Part of flash power control. - 0xB + 11 1 read-write LP_VDDFLASH Part of flash power control. - 0xC + 12 1 read-write PDEN_SRAM0 SRAM0. 0 = Powered; 1 = Powered down. - 0xD + 13 1 read-write PDEN_SRAM1 SRAM1. 0 = Powered; 1 = Powered down. - 0xE + 14 1 read-write PDEN_SRAM2 SRAM2. 0 = Powered; 1 = Powered down. - 0xF + 15 1 read-write PDEN_SRAMX SRAMX. 0 = Powered; 1 = Powered down. - 0x10 + 16 1 read-write PDEN_ROM ROM. 0 = Powered; 1 = Powered down. - 0x11 + 17 1 read-write PD_VDDHV_ENA Part of flash power control. - 0x12 + 18 1 read-write PDEN_VDDA Vdda to the ADC, must be enabled for the ADC to work. Also see bit 23. 0 = Powered; 1 = Powered down. - 0x13 + 19 1 read-write PDEN_WDT_OSC Watchdog oscillator. 0 = Powered; 1 = Powered down. - 0x14 + 20 1 read-write PDEN_USB_PHY USB pin interface. 0 = Powered; 1 = Powered down. - 0x15 + 21 1 read-write PDEN_SYS_PLL PLL0. 0 = Powered; 1 = Powered down. - 0x16 + 22 1 read-write PDEN_VREFP Vrefp to the ADC, must be enabled for the ADC to work. Also see bit 19. 0 = Powered; 1 = Powered down. - 0x17 + 23 1 read-write PD_FLASH_BG Part of flash power control. - 0x19 + 25 1 read-write @@ -2622,14 +2648,14 @@ PD_ALT_FLASH_IBG Part of flash power control. - 0x1C + 28 1 read-write SEL_ALT_FLASH_IBG Part of flash power control. - 0x1D + 29 1 read-write @@ -2694,203 +2720,203 @@ DMA0 DMA0 wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. Typically used in sleep mode only since the peripheral clock must be running for it to function. - 0x1 + 1 1 read-write GINT0 Group interrupt 0 wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. - 0x2 + 2 1 read-write GINT1 Group interrupt 1 wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. - 0x3 + 3 1 read-write PIN_INT0 GPIO pin interrupt 0 wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. Not for pattern match. - 0x4 + 4 1 read-write PIN_INT1 GPIO pin interrupt 1 wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. Not for pattern match. - 0x5 + 5 1 read-write PIN_INT2 GPIO pin interrupt 2 wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. Not for pattern match. - 0x6 + 6 1 read-write PIN_INT3 GPIO pin interrupt 3 wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. Not for pattern match. - 0x7 + 7 1 read-write UTICK0 Micro-tick Timer wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. - 0x8 + 8 1 read-write MRT0 Multi-Rate Timer wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. Typically used in sleep mode only since the peripheral clock must be running for it to function. - 0x9 + 9 1 read-write CTIMER0 Standard counter/timer CTIMER0 wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled.Typically used in sleep mode only since the peripheral clock must be running for it to function. - 0xA + 10 1 read-write CTIMER1 Standard counter/timer CTIMER1 wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled.Typically used in sleep mode only since the peripheral clock must be running for it to function. - 0xB + 11 1 read-write SCT0 SCT0 wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled.Typically used in sleep mode only since the peripheral clock must be running for it to function. - 0xC + 12 1 read-write CTIMER3 Standard counter/timer CTIMER3 wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled.Typically used in sleep mode only since the peripheral clock must be running for it to function. - 0xD + 13 1 read-write FLEXCOMM0 Flexcomm0 peripheral interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. - 0xE + 14 1 read-write FLEXCOMM1 Flexcomm1 peripheral interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. - 0xF + 15 1 read-write FLEXCOMM2 Flexcomm2 peripheral interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. - 0x10 + 16 1 read-write FLEXCOMM3 Flexcomm3 peripheral interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. - 0x11 + 17 1 read-write FLEXCOMM4 Flexcomm4 peripheral interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. - 0x12 + 18 1 read-write FLEXCOMM5 Flexcomm5 peripheral interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. - 0x13 + 19 1 read-write FLEXCOMM6 Flexcomm6 peripheral interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. - 0x14 + 20 1 read-write FLEXCOMM7 Flexcomm7 peripheral interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. - 0x15 + 21 1 read-write ADC0_SEQA ADC0 sequence A interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled.Typically used in sleep mode only since the peripheral clock must be running for it to function. - 0x16 + 22 1 read-write ADC0_SEQB ADC0 sequence B interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled.Typically used in sleep mode only since the peripheral clock must be running for it to function. - 0x17 + 23 1 read-write ADC0_THCMP ADC0 threshold and error interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled.Typically used in sleep mode only since the peripheral clock must be running for it to function. - 0x18 + 24 1 read-write DMIC0 Digital microphone interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. - 0x19 + 25 1 read-write USB0_NEEDCLK USB0 activity interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. - 0x1B + 27 1 read-write USB0 USB0 function interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. - 0x1C + 28 1 read-write RTC RTC interrupt alarm and wake-up timer. 0 = Wake-up disabled. 1 = Wake-up enabled. - 0x1D + 29 1 read-write MAILBOX Mailbox interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled.At least one CPU must be running in order for a mailbox interrupt to occur. Present on selected devices. - 0x1F + 31 1 read-write @@ -2915,35 +2941,35 @@ PINT5 GPIO pin interrupt 5 wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. Not for pattern match. - 0x1 + 1 1 read-write PINT6 GPIO pin interrupt 6 wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. Not for pattern match. - 0x2 + 2 1 read-write PINT7 GPIO pin interrupt 7 wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. Not for pattern match. - 0x3 + 3 1 read-write CTIMER2 Standard counter/timer CTIMER2 wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled.Typically used in sleep mode only since the peripheral clock must be running for it to function. - 0x4 + 4 1 read-write CTIMER4 Standard counter/timer CTIMER4 wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled.Typically used in sleep mode only since the peripheral clock must be running for it to function. - 0x5 + 5 1 read-write @@ -3008,21 +3034,21 @@ FCWAKE Wake for Flexcomms. When 1, any Flexcomm FIFO reaching the level specified by its own TXLVL will cause peripheral clocking to wake up temporarily while the related status is asserted. - 0x1 + 1 1 read-write WAKEDMIC Wake for Digital Microphone. When 1, the digital microphone input FIFO reaching the level specified by TRIGLVL of either channel will cause peripheral clocking to wake up temporarily while the related status is asserted. - 0x2 + 2 1 read-write WAKEDMA Wake for DMA. When 1, DMA being busy will cause peripheral clocking to remain running until DMA completes. This is generally used in conjunction with bit 1 and/or 2 in order to prevent peripheral clocking from being shut down as soon as the cause of wake-up is cleared, but before DMA has completed its related activity. - 0x3 + 3 1 read-write @@ -3059,7 +3085,7 @@ CM4CLKEN Cortex-M4 clock enable - 0x2 + 2 1 read-write @@ -3078,7 +3104,7 @@ CM0CLKEN Cortex-M0+ clock enable - 0x3 + 3 1 read-write @@ -3097,7 +3123,7 @@ CM4RSTEN Cortex-M4 reset. - 0x4 + 4 1 read-write @@ -3116,7 +3142,7 @@ CM0RSTEN Cortex-M0+ reset. - 0x5 + 5 1 read-write @@ -3135,7 +3161,7 @@ POWERCPU Identifies the owner of reduced power mode control: which CPU can cause the device to enter Deep Sleep, Power-down, and Deep Power-down modes. - 0x6 + 6 1 read-write @@ -3208,21 +3234,21 @@ CM0SLEEPING When 1, the Cortex-M0+ CPU is sleeping - 0x1 + 1 1 read-only CM4LOCKUP When 1, the Cortex-M4 CPU is in lockup - 0x2 + 2 1 read-only CM0LOCKUP When 1, the Cortex-M0+ CPU is in lockup. - 0x3 + 3 1 read-only @@ -3240,21 +3266,21 @@ RAM0X When 1, automatic clock gating for RAMX and RAM0 are turned off. - 0x1 + 1 1 read-write RAM1 When 1, automatic clock gating for RAM1 is turned off. - 0x2 + 2 1 read-write RAM2 When 1, automatic clock gating for RAM2 is turned off. - 0x3 + 3 1 read-write @@ -3355,7 +3381,7 @@ BODRSTENA BOD reset enable - 0x2 + 2 1 read-write @@ -3374,7 +3400,7 @@ BODINTLEV BOD interrupt level - 0x3 + 3 2 read-write @@ -3403,7 +3429,7 @@ BODINTENA BOD interrupt enable - 0x5 + 5 1 read-write @@ -3422,14 +3448,14 @@ BODRSTSTAT BOD reset status. When 1, a BOD reset has occurred. Cleared by writing 1 to this bit. - 0x6 + 6 1 read-write BODINTSTAT BOD interrupt status. When 1, a BOD interrupt has occurred. Cleared by writing 1 to this bit. - 0x7 + 7 1 read-write @@ -3509,7 +3535,7 @@ MODE Selects function mode (on-chip pull-up/pull-down resistor control). - 0x3 + 3 2 read-write @@ -3538,7 +3564,7 @@ INVERT Input polarity. - 0x6 + 6 1 read-write @@ -3557,7 +3583,7 @@ DIGIMODE Select Analog/Digital mode. - 0x7 + 7 1 read-write @@ -3576,7 +3602,7 @@ FILTEROFF Controls input glitch filter. - 0x8 + 8 1 read-write @@ -3595,7 +3621,7 @@ SLEW Driver slew rate. - 0x9 + 9 1 read-write @@ -3614,7 +3640,7 @@ OD Controls open-drain mode. - 0xA + 10 1 read-write @@ -3693,7 +3719,7 @@ MODE Selects function mode (on-chip pull-up/pull-down resistor control). - 0x3 + 3 2 read-write @@ -3722,7 +3748,7 @@ INVERT Input polarity. - 0x6 + 6 1 read-write @@ -3741,7 +3767,7 @@ DIGIMODE Select Analog/Digital mode. - 0x7 + 7 1 read-write @@ -3760,7 +3786,7 @@ FILTEROFF Controls input glitch filter. - 0x8 + 8 1 read-write @@ -3779,7 +3805,7 @@ SLEW Driver slew rate. - 0x9 + 9 1 read-write @@ -3798,7 +3824,7 @@ OD Controls open-drain mode. - 0xA + 10 1 read-write @@ -3877,7 +3903,7 @@ MODE Selects function mode (on-chip pull-up/pull-down resistor control). - 0x3 + 3 2 read-write @@ -3906,7 +3932,7 @@ INVERT Input polarity. - 0x6 + 6 1 read-write @@ -3925,7 +3951,7 @@ DIGIMODE Select Analog/Digital mode. - 0x7 + 7 1 read-write @@ -3944,7 +3970,7 @@ FILTEROFF Controls input glitch filter. - 0x8 + 8 1 read-write @@ -3963,7 +3989,7 @@ SLEW Driver slew rate. - 0x9 + 9 1 read-write @@ -3982,7 +4008,7 @@ OD Controls open-drain mode. - 0xA + 10 1 read-write @@ -4061,7 +4087,7 @@ MODE Selects function mode (on-chip pull-up/pull-down resistor control). - 0x3 + 3 2 read-write @@ -4090,7 +4116,7 @@ INVERT Input polarity. - 0x6 + 6 1 read-write @@ -4109,7 +4135,7 @@ DIGIMODE Select Analog/Digital mode. - 0x7 + 7 1 read-write @@ -4128,7 +4154,7 @@ FILTEROFF Controls input glitch filter. - 0x8 + 8 1 read-write @@ -4147,7 +4173,7 @@ SLEW Driver slew rate. - 0x9 + 9 1 read-write @@ -4166,7 +4192,7 @@ OD Controls open-drain mode. - 0xA + 10 1 read-write @@ -4245,7 +4271,7 @@ MODE Selects function mode (on-chip pull-up/pull-down resistor control). - 0x3 + 3 2 read-write @@ -4274,7 +4300,7 @@ INVERT Input polarity. - 0x6 + 6 1 read-write @@ -4293,7 +4319,7 @@ DIGIMODE Select Analog/Digital mode. - 0x7 + 7 1 read-write @@ -4312,7 +4338,7 @@ FILTEROFF Controls input glitch filter. - 0x8 + 8 1 read-write @@ -4331,7 +4357,7 @@ SLEW Driver slew rate. - 0x9 + 9 1 read-write @@ -4350,7 +4376,7 @@ OD Controls open-drain mode. - 0xA + 10 1 read-write @@ -4429,7 +4455,7 @@ MODE Selects function mode (on-chip pull-up/pull-down resistor control). - 0x3 + 3 2 read-write @@ -4458,7 +4484,7 @@ INVERT Input polarity. - 0x6 + 6 1 read-write @@ -4477,7 +4503,7 @@ DIGIMODE Select Analog/Digital mode. - 0x7 + 7 1 read-write @@ -4496,7 +4522,7 @@ FILTEROFF Controls input glitch filter. - 0x8 + 8 1 read-write @@ -4515,7 +4541,7 @@ SLEW Driver slew rate. - 0x9 + 9 1 read-write @@ -4534,7 +4560,7 @@ OD Controls open-drain mode. - 0xA + 10 1 read-write @@ -4613,7 +4639,7 @@ MODE Selects function mode (on-chip pull-up/pull-down resistor control). - 0x3 + 3 2 read-write @@ -4642,7 +4668,7 @@ INVERT Input polarity. - 0x6 + 6 1 read-write @@ -4661,7 +4687,7 @@ DIGIMODE Select Analog/Digital mode. - 0x7 + 7 1 read-write @@ -4680,7 +4706,7 @@ FILTEROFF Controls input glitch filter. - 0x8 + 8 1 read-write @@ -4699,7 +4725,7 @@ SLEW Driver slew rate. - 0x9 + 9 1 read-write @@ -4718,7 +4744,7 @@ OD Controls open-drain mode. - 0xA + 10 1 read-write @@ -4797,7 +4823,7 @@ MODE Selects function mode (on-chip pull-up/pull-down resistor control). - 0x3 + 3 2 read-write @@ -4826,7 +4852,7 @@ INVERT Input polarity. - 0x6 + 6 1 read-write @@ -4845,7 +4871,7 @@ DIGIMODE Select Analog/Digital mode. - 0x7 + 7 1 read-write @@ -4864,7 +4890,7 @@ FILTEROFF Controls input glitch filter. - 0x8 + 8 1 read-write @@ -4883,7 +4909,7 @@ SLEW Driver slew rate. - 0x9 + 9 1 read-write @@ -4902,7 +4928,7 @@ OD Controls open-drain mode. - 0xA + 10 1 read-write @@ -4981,7 +5007,7 @@ MODE Selects function mode (on-chip pull-up/pull-down resistor control). - 0x3 + 3 2 read-write @@ -5010,7 +5036,7 @@ INVERT Input polarity. - 0x6 + 6 1 read-write @@ -5029,7 +5055,7 @@ DIGIMODE Select Analog/Digital mode. - 0x7 + 7 1 read-write @@ -5048,7 +5074,7 @@ FILTEROFF Controls input glitch filter. - 0x8 + 8 1 read-write @@ -5067,7 +5093,7 @@ SLEW Driver slew rate. - 0x9 + 9 1 read-write @@ -5086,7 +5112,7 @@ OD Controls open-drain mode. - 0xA + 10 1 read-write @@ -5165,7 +5191,7 @@ MODE Selects function mode (on-chip pull-up/pull-down resistor control). - 0x3 + 3 2 read-write @@ -5194,7 +5220,7 @@ INVERT Input polarity. - 0x6 + 6 1 read-write @@ -5213,7 +5239,7 @@ DIGIMODE Select Analog/Digital mode. - 0x7 + 7 1 read-write @@ -5232,7 +5258,7 @@ FILTEROFF Controls input glitch filter. - 0x8 + 8 1 read-write @@ -5251,7 +5277,7 @@ SLEW Driver slew rate. - 0x9 + 9 1 read-write @@ -5270,7 +5296,7 @@ OD Controls open-drain mode. - 0xA + 10 1 read-write @@ -5349,7 +5375,7 @@ MODE Selects function mode (on-chip pull-up/pull-down resistor control). - 0x3 + 3 2 read-write @@ -5378,7 +5404,7 @@ INVERT Input polarity. - 0x6 + 6 1 read-write @@ -5397,7 +5423,7 @@ DIGIMODE Select Analog/Digital mode. - 0x7 + 7 1 read-write @@ -5416,7 +5442,7 @@ FILTEROFF Controls input glitch filter. - 0x8 + 8 1 read-write @@ -5435,7 +5461,7 @@ SLEW Driver slew rate. - 0x9 + 9 1 read-write @@ -5454,7 +5480,7 @@ OD Controls open-drain mode. - 0xA + 10 1 read-write @@ -5533,7 +5559,7 @@ MODE Selects function mode (on-chip pull-up/pull-down resistor control). - 0x3 + 3 2 read-write @@ -5562,7 +5588,7 @@ INVERT Input polarity. - 0x6 + 6 1 read-write @@ -5581,7 +5607,7 @@ DIGIMODE Select Analog/Digital mode. - 0x7 + 7 1 read-write @@ -5600,7 +5626,7 @@ FILTEROFF Controls input glitch filter. - 0x8 + 8 1 read-write @@ -5619,7 +5645,7 @@ SLEW Driver slew rate. - 0x9 + 9 1 read-write @@ -5638,7 +5664,7 @@ OD Controls open-drain mode. - 0xA + 10 1 read-write @@ -5717,7 +5743,7 @@ MODE Selects function mode (on-chip pull-up/pull-down resistor control). - 0x3 + 3 2 read-write @@ -5746,7 +5772,7 @@ INVERT Input polarity. - 0x6 + 6 1 read-write @@ -5765,7 +5791,7 @@ DIGIMODE Select Analog/Digital mode. - 0x7 + 7 1 read-write @@ -5784,7 +5810,7 @@ FILTEROFF Controls input glitch filter. - 0x8 + 8 1 read-write @@ -5803,7 +5829,7 @@ SLEW Driver slew rate. - 0x9 + 9 1 read-write @@ -5822,7 +5848,7 @@ OD Controls open-drain mode. - 0xA + 10 1 read-write @@ -5901,7 +5927,7 @@ MODE Selects function mode (on-chip pull-up/pull-down resistor control). - 0x3 + 3 2 read-write @@ -5930,7 +5956,7 @@ INVERT Input polarity. - 0x6 + 6 1 read-write @@ -5949,7 +5975,7 @@ DIGIMODE Select Analog/Digital mode. - 0x7 + 7 1 read-write @@ -5968,7 +5994,7 @@ FILTEROFF Controls input glitch filter. - 0x8 + 8 1 read-write @@ -5987,7 +6013,7 @@ SLEW Driver slew rate. - 0x9 + 9 1 read-write @@ -6006,7 +6032,7 @@ OD Controls open-drain mode. - 0xA + 10 1 read-write @@ -6085,7 +6111,7 @@ MODE Selects function mode (on-chip pull-up/pull-down resistor control). - 0x3 + 3 2 read-write @@ -6114,7 +6140,7 @@ INVERT Input polarity. - 0x6 + 6 1 read-write @@ -6133,7 +6159,7 @@ DIGIMODE Select Analog/Digital mode. - 0x7 + 7 1 read-write @@ -6152,7 +6178,7 @@ FILTEROFF Controls input glitch filter. - 0x8 + 8 1 read-write @@ -6171,7 +6197,7 @@ SLEW Driver slew rate. - 0x9 + 9 1 read-write @@ -6190,7 +6216,7 @@ OD Controls open-drain mode. - 0xA + 10 1 read-write @@ -6269,7 +6295,7 @@ MODE Selects function mode (on-chip pull-up/pull-down resistor control). - 0x3 + 3 2 read-write @@ -6298,7 +6324,7 @@ INVERT Input polarity. - 0x6 + 6 1 read-write @@ -6317,7 +6343,7 @@ DIGIMODE Select Analog/Digital mode. - 0x7 + 7 1 read-write @@ -6336,7 +6362,7 @@ FILTEROFF Controls input glitch filter. - 0x8 + 8 1 read-write @@ -6355,7 +6381,7 @@ SLEW Driver slew rate. - 0x9 + 9 1 read-write @@ -6374,7 +6400,7 @@ OD Controls open-drain mode. - 0xA + 10 1 read-write @@ -6453,7 +6479,7 @@ MODE Selects function mode (on-chip pull-up/pull-down resistor control). - 0x3 + 3 2 read-write @@ -6482,7 +6508,7 @@ INVERT Input polarity. - 0x6 + 6 1 read-write @@ -6501,7 +6527,7 @@ DIGIMODE Select Analog/Digital mode. - 0x7 + 7 1 read-write @@ -6520,7 +6546,7 @@ FILTEROFF Controls input glitch filter. - 0x8 + 8 1 read-write @@ -6539,7 +6565,7 @@ SLEW Driver slew rate. - 0x9 + 9 1 read-write @@ -6558,7 +6584,7 @@ OD Controls open-drain mode. - 0xA + 10 1 read-write @@ -6637,7 +6663,7 @@ MODE Selects function mode (on-chip pull-up/pull-down resistor control). - 0x3 + 3 2 read-write @@ -6666,7 +6692,7 @@ INVERT Input polarity. - 0x6 + 6 1 read-write @@ -6685,7 +6711,7 @@ DIGIMODE Select Analog/Digital mode. - 0x7 + 7 1 read-write @@ -6704,7 +6730,7 @@ FILTEROFF Controls input glitch filter. - 0x8 + 8 1 read-write @@ -6723,7 +6749,7 @@ SLEW Driver slew rate. - 0x9 + 9 1 read-write @@ -6742,7 +6768,7 @@ OD Controls open-drain mode. - 0xA + 10 1 read-write @@ -6821,7 +6847,7 @@ MODE Selects function mode (on-chip pull-up/pull-down resistor control). - 0x3 + 3 2 read-write @@ -6850,7 +6876,7 @@ INVERT Input polarity. - 0x6 + 6 1 read-write @@ -6869,7 +6895,7 @@ DIGIMODE Select Analog/Digital mode. - 0x7 + 7 1 read-write @@ -6888,7 +6914,7 @@ FILTEROFF Controls input glitch filter. - 0x8 + 8 1 read-write @@ -6907,7 +6933,7 @@ SLEW Driver slew rate. - 0x9 + 9 1 read-write @@ -6926,7 +6952,7 @@ OD Controls open-drain mode. - 0xA + 10 1 read-write @@ -7005,7 +7031,7 @@ MODE Selects function mode (on-chip pull-up/pull-down resistor control). - 0x3 + 3 2 read-write @@ -7034,7 +7060,7 @@ INVERT Input polarity. - 0x6 + 6 1 read-write @@ -7053,7 +7079,7 @@ DIGIMODE Select Analog/Digital mode. - 0x7 + 7 1 read-write @@ -7072,7 +7098,7 @@ FILTEROFF Controls input glitch filter. - 0x8 + 8 1 read-write @@ -7091,7 +7117,7 @@ SLEW Driver slew rate. - 0x9 + 9 1 read-write @@ -7110,7 +7136,7 @@ OD Controls open-drain mode. - 0xA + 10 1 read-write @@ -7189,7 +7215,7 @@ MODE Selects function mode (on-chip pull-up/pull-down resistor control). - 0x3 + 3 2 read-write @@ -7218,7 +7244,7 @@ INVERT Input polarity. - 0x6 + 6 1 read-write @@ -7237,7 +7263,7 @@ DIGIMODE Select Analog/Digital mode. - 0x7 + 7 1 read-write @@ -7256,7 +7282,7 @@ FILTEROFF Controls input glitch filter. - 0x8 + 8 1 read-write @@ -7275,7 +7301,7 @@ SLEW Driver slew rate. - 0x9 + 9 1 read-write @@ -7294,7 +7320,7 @@ OD Controls open-drain mode. - 0xA + 10 1 read-write @@ -7373,7 +7399,7 @@ MODE Selects function mode (on-chip pull-up/pull-down resistor control). - 0x3 + 3 2 read-write @@ -7402,7 +7428,7 @@ INVERT Input polarity. - 0x6 + 6 1 read-write @@ -7421,7 +7447,7 @@ DIGIMODE Select Analog/Digital mode. - 0x7 + 7 1 read-write @@ -7440,7 +7466,7 @@ FILTEROFF Controls input glitch filter. - 0x8 + 8 1 read-write @@ -7459,7 +7485,7 @@ SLEW Driver slew rate. - 0x9 + 9 1 read-write @@ -7478,7 +7504,7 @@ OD Controls open-drain mode. - 0xA + 10 1 read-write @@ -7557,7 +7583,7 @@ MODE Selects function mode (on-chip pull-up/pull-down resistor control). - 0x3 + 3 2 read-write @@ -7586,7 +7612,7 @@ INVERT Input polarity. - 0x6 + 6 1 read-write @@ -7605,7 +7631,7 @@ DIGIMODE Select Analog/Digital mode. - 0x7 + 7 1 read-write @@ -7624,7 +7650,7 @@ FILTEROFF Controls input glitch filter. - 0x8 + 8 1 read-write @@ -7643,7 +7669,7 @@ SLEW Driver slew rate. - 0x9 + 9 1 read-write @@ -7662,7 +7688,7 @@ OD Controls open-drain mode. - 0xA + 10 1 read-write @@ -7741,7 +7767,7 @@ I2CSLEW Controls slew rate of I2C pad. - 0x5 + 5 1 read-write @@ -7760,7 +7786,7 @@ INVERT Input polarity. - 0x6 + 6 1 read-write @@ -7779,7 +7805,7 @@ DIGIMODE Select Analog/Digital mode. - 0x7 + 7 1 read-write @@ -7798,7 +7824,7 @@ FILTEROFF Controls input glitch filter. - 0x8 + 8 1 read-write @@ -7817,7 +7843,7 @@ I2CDRIVE Controls the current sink capability of the pin. - 0x9 + 9 1 read-write @@ -7836,7 +7862,7 @@ I2CFILTER Configures I2C features for standard mode, fast mode, and Fast Mode Plus operation. - 0xA + 10 1 read-write @@ -7915,7 +7941,7 @@ I2CSLEW Controls slew rate of I2C pad. - 0x5 + 5 1 read-write @@ -7934,7 +7960,7 @@ INVERT Input polarity. - 0x6 + 6 1 read-write @@ -7953,7 +7979,7 @@ DIGIMODE Select Analog/Digital mode. - 0x7 + 7 1 read-write @@ -7972,7 +7998,7 @@ FILTEROFF Controls input glitch filter. - 0x8 + 8 1 read-write @@ -7991,7 +8017,7 @@ I2CDRIVE Controls the current sink capability of the pin. - 0x9 + 9 1 read-write @@ -8010,7 +8036,7 @@ I2CFILTER Configures I2C features for standard mode, fast mode, and Fast Mode Plus operation. - 0xA + 10 1 read-write @@ -8089,7 +8115,7 @@ I2CSLEW Controls slew rate of I2C pad. - 0x5 + 5 1 read-write @@ -8108,7 +8134,7 @@ INVERT Input polarity. - 0x6 + 6 1 read-write @@ -8127,7 +8153,7 @@ DIGIMODE Select Analog/Digital mode. - 0x7 + 7 1 read-write @@ -8146,7 +8172,7 @@ FILTEROFF Controls input glitch filter. - 0x8 + 8 1 read-write @@ -8165,7 +8191,7 @@ I2CDRIVE Controls the current sink capability of the pin. - 0x9 + 9 1 read-write @@ -8184,7 +8210,7 @@ I2CFILTER Configures I2C features for standard mode, fast mode, and Fast Mode Plus operation. - 0xA + 10 1 read-write @@ -8263,7 +8289,7 @@ I2CSLEW Controls slew rate of I2C pad. - 0x5 + 5 1 read-write @@ -8282,7 +8308,7 @@ INVERT Input polarity. - 0x6 + 6 1 read-write @@ -8301,7 +8327,7 @@ DIGIMODE Select Analog/Digital mode. - 0x7 + 7 1 read-write @@ -8320,7 +8346,7 @@ FILTEROFF Controls input glitch filter. - 0x8 + 8 1 read-write @@ -8339,7 +8365,7 @@ I2CDRIVE Controls the current sink capability of the pin. - 0x9 + 9 1 read-write @@ -8358,7 +8384,7 @@ I2CFILTER Configures I2C features for standard mode, fast mode, and Fast Mode Plus operation. - 0xA + 10 1 read-write @@ -8437,7 +8463,7 @@ MODE Selects function mode (on-chip pull-up/pull-down resistor control). - 0x3 + 3 2 read-write @@ -8466,7 +8492,7 @@ INVERT Input polarity. - 0x6 + 6 1 read-write @@ -8485,7 +8511,7 @@ DIGIMODE Select Analog/Digital mode. - 0x7 + 7 1 read-write @@ -8504,7 +8530,7 @@ FILTEROFF Controls input glitch filter. - 0x8 + 8 1 read-write @@ -8523,7 +8549,7 @@ SLEW Driver slew rate. - 0x9 + 9 1 read-write @@ -8542,7 +8568,7 @@ OD Controls open-drain mode. - 0xA + 10 1 read-write @@ -8621,7 +8647,7 @@ MODE Selects function mode (on-chip pull-up/pull-down resistor control). - 0x3 + 3 2 read-write @@ -8650,7 +8676,7 @@ INVERT Input polarity. - 0x6 + 6 1 read-write @@ -8669,7 +8695,7 @@ DIGIMODE Select Analog/Digital mode. - 0x7 + 7 1 read-write @@ -8688,7 +8714,7 @@ FILTEROFF Controls input glitch filter. - 0x8 + 8 1 read-write @@ -8707,7 +8733,7 @@ SLEW Driver slew rate. - 0x9 + 9 1 read-write @@ -8726,7 +8752,7 @@ OD Controls open-drain mode. - 0xA + 10 1 read-write @@ -8805,7 +8831,7 @@ MODE Selects function mode (on-chip pull-up/pull-down resistor control). - 0x3 + 3 2 read-write @@ -8834,7 +8860,7 @@ INVERT Input polarity. - 0x6 + 6 1 read-write @@ -8853,7 +8879,7 @@ DIGIMODE Select Analog/Digital mode. - 0x7 + 7 1 read-write @@ -8872,7 +8898,7 @@ FILTEROFF Controls input glitch filter. - 0x8 + 8 1 read-write @@ -8891,7 +8917,7 @@ OD Controls open-drain mode. - 0xA + 10 1 read-write @@ -8970,7 +8996,7 @@ MODE Selects function mode (on-chip pull-up/pull-down resistor control). - 0x3 + 3 2 read-write @@ -8999,7 +9025,7 @@ INVERT Input polarity. - 0x6 + 6 1 read-write @@ -9018,7 +9044,7 @@ DIGIMODE Select Analog/Digital mode. - 0x7 + 7 1 read-write @@ -9037,7 +9063,7 @@ FILTEROFF Controls input glitch filter. - 0x8 + 8 1 read-write @@ -9056,7 +9082,7 @@ OD Controls open-drain mode. - 0xA + 10 1 read-write @@ -9135,7 +9161,7 @@ MODE Selects function mode (on-chip pull-up/pull-down resistor control). - 0x3 + 3 2 read-write @@ -9164,7 +9190,7 @@ INVERT Input polarity. - 0x6 + 6 1 read-write @@ -9183,7 +9209,7 @@ DIGIMODE Select Analog/Digital mode. - 0x7 + 7 1 read-write @@ -9202,7 +9228,7 @@ FILTEROFF Controls input glitch filter. - 0x8 + 8 1 read-write @@ -9221,7 +9247,7 @@ OD Controls open-drain mode. - 0xA + 10 1 read-write @@ -9300,7 +9326,7 @@ MODE Selects function mode (on-chip pull-up/pull-down resistor control). - 0x3 + 3 2 read-write @@ -9329,7 +9355,7 @@ INVERT Input polarity. - 0x6 + 6 1 read-write @@ -9348,7 +9374,7 @@ DIGIMODE Select Analog/Digital mode. - 0x7 + 7 1 read-write @@ -9367,7 +9393,7 @@ FILTEROFF Controls input glitch filter. - 0x8 + 8 1 read-write @@ -9386,7 +9412,7 @@ OD Controls open-drain mode. - 0xA + 10 1 read-write @@ -9465,7 +9491,7 @@ MODE Selects function mode (on-chip pull-up/pull-down resistor control). - 0x3 + 3 2 read-write @@ -9494,7 +9520,7 @@ INVERT Input polarity. - 0x6 + 6 1 read-write @@ -9513,7 +9539,7 @@ DIGIMODE Select Analog/Digital mode. - 0x7 + 7 1 read-write @@ -9532,7 +9558,7 @@ FILTEROFF Controls input glitch filter. - 0x8 + 8 1 read-write @@ -9551,7 +9577,7 @@ OD Controls open-drain mode. - 0xA + 10 1 read-write @@ -9630,7 +9656,7 @@ MODE Selects function mode (on-chip pull-up/pull-down resistor control). - 0x3 + 3 2 read-write @@ -9659,7 +9685,7 @@ INVERT Input polarity. - 0x6 + 6 1 read-write @@ -9678,7 +9704,7 @@ DIGIMODE Select Analog/Digital mode. - 0x7 + 7 1 read-write @@ -9697,7 +9723,7 @@ FILTEROFF Controls input glitch filter. - 0x8 + 8 1 read-write @@ -9716,7 +9742,7 @@ OD Controls open-drain mode. - 0xA + 10 1 read-write @@ -9795,7 +9821,7 @@ MODE Selects function mode (on-chip pull-up/pull-down resistor control). - 0x3 + 3 2 read-write @@ -9824,7 +9850,7 @@ INVERT Input polarity. - 0x6 + 6 1 read-write @@ -9843,7 +9869,7 @@ DIGIMODE Select Analog/Digital mode. - 0x7 + 7 1 read-write @@ -9862,7 +9888,7 @@ FILTEROFF Controls input glitch filter. - 0x8 + 8 1 read-write @@ -9881,7 +9907,7 @@ OD Controls open-drain mode. - 0xA + 10 1 read-write @@ -9960,7 +9986,7 @@ MODE Selects function mode (on-chip pull-up/pull-down resistor control). - 0x3 + 3 2 read-write @@ -9989,7 +10015,7 @@ INVERT Input polarity. - 0x6 + 6 1 read-write @@ -10008,7 +10034,7 @@ DIGIMODE Select Analog/Digital mode. - 0x7 + 7 1 read-write @@ -10027,7 +10053,7 @@ FILTEROFF Controls input glitch filter. - 0x8 + 8 1 read-write @@ -10046,7 +10072,7 @@ OD Controls open-drain mode. - 0xA + 10 1 read-write @@ -10125,7 +10151,7 @@ MODE Selects function mode (on-chip pull-up/pull-down resistor control). - 0x3 + 3 2 read-write @@ -10154,7 +10180,7 @@ INVERT Input polarity. - 0x6 + 6 1 read-write @@ -10173,7 +10199,7 @@ DIGIMODE Select Analog/Digital mode. - 0x7 + 7 1 read-write @@ -10192,7 +10218,7 @@ FILTEROFF Controls input glitch filter. - 0x8 + 8 1 read-write @@ -10211,7 +10237,7 @@ OD Controls open-drain mode. - 0xA + 10 1 read-write @@ -10290,7 +10316,7 @@ MODE Selects function mode (on-chip pull-up/pull-down resistor control). - 0x3 + 3 2 read-write @@ -10319,7 +10345,7 @@ INVERT Input polarity. - 0x6 + 6 1 read-write @@ -10338,7 +10364,7 @@ DIGIMODE Select Analog/Digital mode. - 0x7 + 7 1 read-write @@ -10357,7 +10383,7 @@ FILTEROFF Controls input glitch filter. - 0x8 + 8 1 read-write @@ -10376,7 +10402,7 @@ OD Controls open-drain mode. - 0xA + 10 1 read-write @@ -10455,7 +10481,7 @@ MODE Selects function mode (on-chip pull-up/pull-down resistor control). - 0x3 + 3 2 read-write @@ -10484,7 +10510,7 @@ INVERT Input polarity. - 0x6 + 6 1 read-write @@ -10503,7 +10529,7 @@ DIGIMODE Select Analog/Digital mode. - 0x7 + 7 1 read-write @@ -10522,7 +10548,7 @@ FILTEROFF Controls input glitch filter. - 0x8 + 8 1 read-write @@ -10541,7 +10567,7 @@ OD Controls open-drain mode. - 0xA + 10 1 read-write @@ -10620,7 +10646,7 @@ MODE Selects function mode (on-chip pull-up/pull-down resistor control). - 0x3 + 3 2 read-write @@ -10649,7 +10675,7 @@ INVERT Input polarity. - 0x6 + 6 1 read-write @@ -10668,7 +10694,7 @@ DIGIMODE Select Analog/Digital mode. - 0x7 + 7 1 read-write @@ -10687,7 +10713,7 @@ FILTEROFF Controls input glitch filter. - 0x8 + 8 1 read-write @@ -10706,7 +10732,7 @@ OD Controls open-drain mode. - 0xA + 10 1 read-write @@ -10785,7 +10811,7 @@ MODE Selects function mode (on-chip pull-up/pull-down resistor control). - 0x3 + 3 2 read-write @@ -10814,7 +10840,7 @@ INVERT Input polarity. - 0x6 + 6 1 read-write @@ -10833,7 +10859,7 @@ DIGIMODE Select Analog/Digital mode. - 0x7 + 7 1 read-write @@ -10852,7 +10878,7 @@ FILTEROFF Controls input glitch filter. - 0x8 + 8 1 read-write @@ -10871,7 +10897,7 @@ SLEW Driver slew rate. - 0x9 + 9 1 read-write @@ -10890,7 +10916,7 @@ OD Controls open-drain mode. - 0xA + 10 1 read-write @@ -10969,7 +10995,7 @@ MODE Selects function mode (on-chip pull-up/pull-down resistor control). - 0x3 + 3 2 read-write @@ -10998,7 +11024,7 @@ INVERT Input polarity. - 0x6 + 6 1 read-write @@ -11017,7 +11043,7 @@ DIGIMODE Select Analog/Digital mode. - 0x7 + 7 1 read-write @@ -11036,7 +11062,7 @@ FILTEROFF Controls input glitch filter. - 0x8 + 8 1 read-write @@ -11055,7 +11081,7 @@ SLEW Driver slew rate. - 0x9 + 9 1 read-write @@ -11074,7 +11100,7 @@ OD Controls open-drain mode. - 0xA + 10 1 read-write @@ -11153,7 +11179,7 @@ MODE Selects function mode (on-chip pull-up/pull-down resistor control). - 0x3 + 3 2 read-write @@ -11182,7 +11208,7 @@ INVERT Input polarity. - 0x6 + 6 1 read-write @@ -11201,7 +11227,7 @@ DIGIMODE Select Analog/Digital mode. - 0x7 + 7 1 read-write @@ -11220,7 +11246,7 @@ FILTEROFF Controls input glitch filter. - 0x8 + 8 1 read-write @@ -11239,7 +11265,7 @@ SLEW Driver slew rate. - 0x9 + 9 1 read-write @@ -11258,7 +11284,7 @@ OD Controls open-drain mode. - 0xA + 10 1 read-write @@ -11337,7 +11363,7 @@ MODE Selects function mode (on-chip pull-up/pull-down resistor control). - 0x3 + 3 2 read-write @@ -11366,7 +11392,7 @@ INVERT Input polarity. - 0x6 + 6 1 read-write @@ -11385,7 +11411,7 @@ DIGIMODE Select Analog/Digital mode. - 0x7 + 7 1 read-write @@ -11404,7 +11430,7 @@ FILTEROFF Controls input glitch filter. - 0x8 + 8 1 read-write @@ -11423,7 +11449,7 @@ SLEW Driver slew rate. - 0x9 + 9 1 read-write @@ -11442,7 +11468,7 @@ OD Controls open-drain mode. - 0xA + 10 1 read-write @@ -11521,7 +11547,7 @@ MODE Selects function mode (on-chip pull-up/pull-down resistor control). - 0x3 + 3 2 read-write @@ -11550,7 +11576,7 @@ INVERT Input polarity. - 0x6 + 6 1 read-write @@ -11569,7 +11595,7 @@ DIGIMODE Select Analog/Digital mode. - 0x7 + 7 1 read-write @@ -11588,7 +11614,7 @@ FILTEROFF Controls input glitch filter. - 0x8 + 8 1 read-write @@ -11607,7 +11633,7 @@ SLEW Driver slew rate. - 0x9 + 9 1 read-write @@ -11626,7 +11652,7 @@ OD Controls open-drain mode. - 0xA + 10 1 read-write @@ -11705,7 +11731,7 @@ MODE Selects function mode (on-chip pull-up/pull-down resistor control). - 0x3 + 3 2 read-write @@ -11734,7 +11760,7 @@ INVERT Input polarity. - 0x6 + 6 1 read-write @@ -11753,7 +11779,7 @@ DIGIMODE Select Analog/Digital mode. - 0x7 + 7 1 read-write @@ -11772,7 +11798,7 @@ FILTEROFF Controls input glitch filter. - 0x8 + 8 1 read-write @@ -11791,7 +11817,7 @@ SLEW Driver slew rate. - 0x9 + 9 1 read-write @@ -11810,7 +11836,7 @@ OD Controls open-drain mode. - 0xA + 10 1 read-write @@ -11889,7 +11915,7 @@ MODE Selects function mode (on-chip pull-up/pull-down resistor control). - 0x3 + 3 2 read-write @@ -11918,7 +11944,7 @@ INVERT Input polarity. - 0x6 + 6 1 read-write @@ -11937,7 +11963,7 @@ DIGIMODE Select Analog/Digital mode. - 0x7 + 7 1 read-write @@ -11956,7 +11982,7 @@ FILTEROFF Controls input glitch filter. - 0x8 + 8 1 read-write @@ -11975,7 +12001,7 @@ SLEW Driver slew rate. - 0x9 + 9 1 read-write @@ -11994,7 +12020,7 @@ OD Controls open-drain mode. - 0xA + 10 1 read-write @@ -12073,7 +12099,7 @@ MODE Selects function mode (on-chip pull-up/pull-down resistor control). - 0x3 + 3 2 read-write @@ -12102,7 +12128,7 @@ INVERT Input polarity. - 0x6 + 6 1 read-write @@ -12121,7 +12147,7 @@ DIGIMODE Select Analog/Digital mode. - 0x7 + 7 1 read-write @@ -12140,7 +12166,7 @@ FILTEROFF Controls input glitch filter. - 0x8 + 8 1 read-write @@ -12159,7 +12185,7 @@ SLEW Driver slew rate. - 0x9 + 9 1 read-write @@ -12178,7 +12204,7 @@ OD Controls open-drain mode. - 0xA + 10 1 read-write @@ -12257,7 +12283,7 @@ MODE Selects function mode (on-chip pull-up/pull-down resistor control). - 0x3 + 3 2 read-write @@ -12286,7 +12312,7 @@ INVERT Input polarity. - 0x6 + 6 1 read-write @@ -12305,7 +12331,7 @@ DIGIMODE Select Analog/Digital mode. - 0x7 + 7 1 read-write @@ -12324,7 +12350,7 @@ FILTEROFF Controls input glitch filter. - 0x8 + 8 1 read-write @@ -12343,7 +12369,7 @@ SLEW Driver slew rate. - 0x9 + 9 1 read-write @@ -12362,7 +12388,7 @@ OD Controls open-drain mode. - 0xA + 10 1 read-write @@ -12441,7 +12467,7 @@ MODE Selects function mode (on-chip pull-up/pull-down resistor control). - 0x3 + 3 2 read-write @@ -12470,7 +12496,7 @@ INVERT Input polarity. - 0x6 + 6 1 read-write @@ -12489,7 +12515,7 @@ DIGIMODE Select Analog/Digital mode. - 0x7 + 7 1 read-write @@ -12508,7 +12534,7 @@ FILTEROFF Controls input glitch filter. - 0x8 + 8 1 read-write @@ -12527,7 +12553,7 @@ SLEW Driver slew rate. - 0x9 + 9 1 read-write @@ -12546,7 +12572,7 @@ OD Controls open-drain mode. - 0xA + 10 1 read-write @@ -12625,7 +12651,7 @@ MODE Selects function mode (on-chip pull-up/pull-down resistor control). - 0x3 + 3 2 read-write @@ -12654,7 +12680,7 @@ INVERT Input polarity. - 0x6 + 6 1 read-write @@ -12673,7 +12699,7 @@ DIGIMODE Select Analog/Digital mode. - 0x7 + 7 1 read-write @@ -12692,7 +12718,7 @@ FILTEROFF Controls input glitch filter. - 0x8 + 8 1 read-write @@ -12711,7 +12737,7 @@ SLEW Driver slew rate. - 0x9 + 9 1 read-write @@ -12730,7 +12756,7 @@ OD Controls open-drain mode. - 0xA + 10 1 read-write @@ -12809,7 +12835,7 @@ MODE Selects function mode (on-chip pull-up/pull-down resistor control). - 0x3 + 3 2 read-write @@ -12838,7 +12864,7 @@ INVERT Input polarity. - 0x6 + 6 1 read-write @@ -12857,7 +12883,7 @@ DIGIMODE Select Analog/Digital mode. - 0x7 + 7 1 read-write @@ -12876,7 +12902,7 @@ FILTEROFF Controls input glitch filter. - 0x8 + 8 1 read-write @@ -12895,7 +12921,7 @@ SLEW Driver slew rate. - 0x9 + 9 1 read-write @@ -12914,7 +12940,7 @@ OD Controls open-drain mode. - 0xA + 10 1 read-write @@ -12993,7 +13019,7 @@ MODE Selects function mode (on-chip pull-up/pull-down resistor control). - 0x3 + 3 2 read-write @@ -13022,7 +13048,7 @@ INVERT Input polarity. - 0x6 + 6 1 read-write @@ -13041,7 +13067,7 @@ DIGIMODE Select Analog/Digital mode. - 0x7 + 7 1 read-write @@ -13060,7 +13086,7 @@ FILTEROFF Controls input glitch filter. - 0x8 + 8 1 read-write @@ -13079,7 +13105,7 @@ SLEW Driver slew rate. - 0x9 + 9 1 read-write @@ -13098,7 +13124,7 @@ OD Controls open-drain mode. - 0xA + 10 1 read-write @@ -13177,7 +13203,7 @@ MODE Selects function mode (on-chip pull-up/pull-down resistor control). - 0x3 + 3 2 read-write @@ -13206,7 +13232,7 @@ INVERT Input polarity. - 0x6 + 6 1 read-write @@ -13225,7 +13251,7 @@ DIGIMODE Select Analog/Digital mode. - 0x7 + 7 1 read-write @@ -13244,7 +13270,7 @@ FILTEROFF Controls input glitch filter. - 0x8 + 8 1 read-write @@ -13263,7 +13289,7 @@ SLEW Driver slew rate. - 0x9 + 9 1 read-write @@ -13282,7 +13308,7 @@ OD Controls open-drain mode. - 0xA + 10 1 read-write @@ -13361,7 +13387,7 @@ MODE Selects function mode (on-chip pull-up/pull-down resistor control). - 0x3 + 3 2 read-write @@ -13390,7 +13416,7 @@ INVERT Input polarity. - 0x6 + 6 1 read-write @@ -13409,7 +13435,7 @@ DIGIMODE Select Analog/Digital mode. - 0x7 + 7 1 read-write @@ -13428,7 +13454,7 @@ FILTEROFF Controls input glitch filter. - 0x8 + 8 1 read-write @@ -13447,7 +13473,7 @@ SLEW Driver slew rate. - 0x9 + 9 1 read-write @@ -13466,7 +13492,7 @@ OD Controls open-drain mode. - 0xA + 10 1 read-write @@ -13545,7 +13571,7 @@ MODE Selects function mode (on-chip pull-up/pull-down resistor control). - 0x3 + 3 2 read-write @@ -13574,7 +13600,7 @@ INVERT Input polarity. - 0x6 + 6 1 read-write @@ -13593,7 +13619,7 @@ DIGIMODE Select Analog/Digital mode. - 0x7 + 7 1 read-write @@ -13612,7 +13638,7 @@ FILTEROFF Controls input glitch filter. - 0x8 + 8 1 read-write @@ -13631,7 +13657,7 @@ SLEW Driver slew rate. - 0x9 + 9 1 read-write @@ -13650,7 +13676,7 @@ OD Controls open-drain mode. - 0xA + 10 1 read-write @@ -13729,7 +13755,7 @@ MODE Selects function mode (on-chip pull-up/pull-down resistor control). - 0x3 + 3 2 read-write @@ -13758,7 +13784,7 @@ INVERT Input polarity. - 0x6 + 6 1 read-write @@ -13777,7 +13803,7 @@ DIGIMODE Select Analog/Digital mode. - 0x7 + 7 1 read-write @@ -13796,7 +13822,7 @@ FILTEROFF Controls input glitch filter. - 0x8 + 8 1 read-write @@ -13815,7 +13841,7 @@ SLEW Driver slew rate. - 0x9 + 9 1 read-write @@ -13834,7 +13860,7 @@ OD Controls open-drain mode. - 0xA + 10 1 read-write @@ -13913,7 +13939,7 @@ MODE Selects function mode (on-chip pull-up/pull-down resistor control). - 0x3 + 3 2 read-write @@ -13942,7 +13968,7 @@ INVERT Input polarity. - 0x6 + 6 1 read-write @@ -13961,7 +13987,7 @@ DIGIMODE Select Analog/Digital mode. - 0x7 + 7 1 read-write @@ -13980,7 +14006,7 @@ FILTEROFF Controls input glitch filter. - 0x8 + 8 1 read-write @@ -13999,7 +14025,7 @@ SLEW Driver slew rate. - 0x9 + 9 1 read-write @@ -14018,7 +14044,7 @@ OD Controls open-drain mode. - 0xA + 10 1 read-write @@ -14097,7 +14123,7 @@ MODE Selects function mode (on-chip pull-up/pull-down resistor control). - 0x3 + 3 2 read-write @@ -14126,7 +14152,7 @@ INVERT Input polarity. - 0x6 + 6 1 read-write @@ -14145,7 +14171,7 @@ DIGIMODE Select Analog/Digital mode. - 0x7 + 7 1 read-write @@ -14164,7 +14190,7 @@ FILTEROFF Controls input glitch filter. - 0x8 + 8 1 read-write @@ -14183,7 +14209,7 @@ SLEW Driver slew rate. - 0x9 + 9 1 read-write @@ -14202,7 +14228,7 @@ OD Controls open-drain mode. - 0xA + 10 1 read-write @@ -14281,7 +14307,7 @@ MODE Selects function mode (on-chip pull-up/pull-down resistor control). - 0x3 + 3 2 read-write @@ -14310,7 +14336,7 @@ INVERT Input polarity. - 0x6 + 6 1 read-write @@ -14329,7 +14355,7 @@ DIGIMODE Select Analog/Digital mode. - 0x7 + 7 1 read-write @@ -14348,7 +14374,7 @@ FILTEROFF Controls input glitch filter. - 0x8 + 8 1 read-write @@ -14367,7 +14393,7 @@ SLEW Driver slew rate. - 0x9 + 9 1 read-write @@ -14386,7 +14412,7 @@ OD Controls open-drain mode. - 0xA + 10 1 read-write @@ -14465,7 +14491,7 @@ MODE Selects function mode (on-chip pull-up/pull-down resistor control). - 0x3 + 3 2 read-write @@ -14494,7 +14520,7 @@ INVERT Input polarity. - 0x6 + 6 1 read-write @@ -14513,7 +14539,7 @@ DIGIMODE Select Analog/Digital mode. - 0x7 + 7 1 read-write @@ -14532,7 +14558,7 @@ FILTEROFF Controls input glitch filter. - 0x8 + 8 1 read-write @@ -14551,7 +14577,7 @@ SLEW Driver slew rate. - 0x9 + 9 1 read-write @@ -14570,7 +14596,7 @@ OD Controls open-drain mode. - 0xA + 10 1 read-write @@ -14649,7 +14675,7 @@ MODE Selects function mode (on-chip pull-up/pull-down resistor control). - 0x3 + 3 2 read-write @@ -14678,7 +14704,7 @@ INVERT Input polarity. - 0x6 + 6 1 read-write @@ -14697,7 +14723,7 @@ DIGIMODE Select Analog/Digital mode. - 0x7 + 7 1 read-write @@ -14716,7 +14742,7 @@ FILTEROFF Controls input glitch filter. - 0x8 + 8 1 read-write @@ -14735,7 +14761,7 @@ SLEW Driver slew rate. - 0x9 + 9 1 read-write @@ -14754,7 +14780,7 @@ OD Controls open-drain mode. - 0xA + 10 1 read-write @@ -14833,7 +14859,7 @@ MODE Selects function mode (on-chip pull-up/pull-down resistor control). - 0x3 + 3 2 read-write @@ -14862,7 +14888,7 @@ INVERT Input polarity. - 0x6 + 6 1 read-write @@ -14881,7 +14907,7 @@ DIGIMODE Select Analog/Digital mode. - 0x7 + 7 1 read-write @@ -14900,7 +14926,7 @@ FILTEROFF Controls input glitch filter. - 0x8 + 8 1 read-write @@ -14919,7 +14945,7 @@ SLEW Driver slew rate. - 0x9 + 9 1 read-write @@ -14938,7 +14964,7 @@ OD Controls open-drain mode. - 0xA + 10 1 read-write @@ -14962,8 +14988,8 @@ GINT0 LPC5411x Group GPIO input interrupt (GINT0/1) GINT - 0x40002000 GINT + 0x40002000 0 0x48 @@ -15005,7 +15031,7 @@ COMB Combine enabled inputs for group interrupt - 0x1 + 1 1 read-write @@ -15024,7 +15050,7 @@ TRIG Group interrupt trigger - 0x2 + 2 1 read-write @@ -15353,7 +15379,7 @@ ENA_RXEV Enables the RXEV output to the CPU and/or to a GPIO output when the specified boolean expression evaluates to true. - 0x1 + 1 1 read-write @@ -15372,7 +15398,7 @@ PMAT This field displays the current state of pattern matches. A 1 in any bit of this field indicates that the corresponding product term is matched by the current state of the appropriate inputs. - 0x18 + 24 8 read-write @@ -15390,7 +15416,7 @@ SRC0 Selects the input source for bit slice 0 - 0x8 + 8 3 read-write @@ -15439,7 +15465,7 @@ SRC1 Selects the input source for bit slice 1 - 0xB + 11 3 read-write @@ -15488,7 +15514,7 @@ SRC2 Selects the input source for bit slice 2 - 0xE + 14 3 read-write @@ -15537,7 +15563,7 @@ SRC3 Selects the input source for bit slice 3 - 0x11 + 17 3 read-write @@ -15586,7 +15612,7 @@ SRC4 Selects the input source for bit slice 4 - 0x14 + 20 3 read-write @@ -15635,7 +15661,7 @@ SRC5 Selects the input source for bit slice 5 - 0x17 + 23 3 read-write @@ -15684,7 +15710,7 @@ SRC6 Selects the input source for bit slice 6 - 0x1A + 26 3 read-write @@ -15733,7 +15759,7 @@ SRC7 Selects the input source for bit slice 7 - 0x1D + 29 3 read-write @@ -15812,7 +15838,7 @@ PROD_ENDPTS1 Determines whether slice 1 is an endpoint. - 0x1 + 1 1 read-write @@ -15831,7 +15857,7 @@ PROD_ENDPTS2 Determines whether slice 2 is an endpoint. - 0x2 + 2 1 read-write @@ -15850,7 +15876,7 @@ PROD_ENDPTS3 Determines whether slice 3 is an endpoint. - 0x3 + 3 1 read-write @@ -15869,7 +15895,7 @@ PROD_ENDPTS4 Determines whether slice 4 is an endpoint. - 0x4 + 4 1 read-write @@ -15888,7 +15914,7 @@ PROD_ENDPTS5 Determines whether slice 5 is an endpoint. - 0x5 + 5 1 read-write @@ -15907,7 +15933,7 @@ PROD_ENDPTS6 Determines whether slice 6 is an endpoint. - 0x6 + 6 1 read-write @@ -15926,7 +15952,7 @@ CFG0 Specifies the match contribution condition for bit slice 0. - 0x8 + 8 3 read-write @@ -15975,7 +16001,7 @@ CFG1 Specifies the match contribution condition for bit slice 1. - 0xB + 11 3 read-write @@ -16024,7 +16050,7 @@ CFG2 Specifies the match contribution condition for bit slice 2. - 0xE + 14 3 read-write @@ -16073,7 +16099,7 @@ CFG3 Specifies the match contribution condition for bit slice 3. - 0x11 + 17 3 read-write @@ -16122,7 +16148,7 @@ CFG4 Specifies the match contribution condition for bit slice 4. - 0x14 + 20 3 read-write @@ -16171,7 +16197,7 @@ CFG5 Specifies the match contribution condition for bit slice 5. - 0x17 + 23 3 read-write @@ -16220,7 +16246,7 @@ CFG6 Specifies the match contribution condition for bit slice 6. - 0x1A + 26 3 read-write @@ -16269,7 +16295,7 @@ CFG7 Specifies the match contribution condition for bit slice 7. - 0x1D + 29 3 read-write @@ -16432,8 +16458,8 @@ CTIMER0 LPC5411x Standard counter/timers (CTIMER0 to 4) CTIMER - 0x40008000 CTIMER + 0x40008000 0 0x78 @@ -16463,49 +16489,49 @@ MR1INT Interrupt flag for match channel 1. - 0x1 + 1 1 read-write MR2INT Interrupt flag for match channel 2. - 0x2 + 2 1 read-write MR3INT Interrupt flag for match channel 3. - 0x3 + 3 1 read-write CR0INT Interrupt flag for capture channel 0 event. - 0x4 + 4 1 read-write CR1INT Interrupt flag for capture channel 1 event. - 0x5 + 5 1 read-write CR2INT Interrupt flag for capture channel 2 event. - 0x6 + 6 1 read-write CR3INT Interrupt flag for capture channel 3 event. - 0x7 + 7 1 read-write @@ -16542,7 +16568,7 @@ CRST Counter reset. - 0x1 + 1 1 read-write @@ -16633,77 +16659,77 @@ MR0R Reset on MR0: the TC will be reset if MR0 matches it. 0 = disabled. 1 = enabled. - 0x1 + 1 1 read-write MR0S Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC. 0 = disabled. 1 = enabled. - 0x2 + 2 1 read-write MR1I Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC. 0 = disabled. 1 = enabled. 0 = disabled. 1 = enabled. - 0x3 + 3 1 read-write MR1R Reset on MR1: the TC will be reset if MR1 matches it. 0 = disabled. 1 = enabled. - 0x4 + 4 1 read-write MR1S Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC. 0 = disabled. 1 = enabled. - 0x5 + 5 1 read-write MR2I Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC. 0 = disabled. 1 = enabled. - 0x6 + 6 1 read-write MR2R Reset on MR2: the TC will be reset if MR2 matches it. 0 = disabled. 1 = enabled. - 0x7 + 7 1 read-write MR2S Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC. 0 = disabled. 1 = enabled. - 0x8 + 8 1 read-write MR3I Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC. 0 = disabled. 1 = enabled. - 0x9 + 9 1 read-write MR3R Reset on MR3: the TC will be reset if MR3 matches it. 0 = disabled. 1 = enabled. - 0xA + 10 1 read-write MR3S Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC. 0 = disabled. 1 = enabled. - 0xB + 11 1 read-write @@ -16748,77 +16774,77 @@ CAP0FE Falling edge of capture channel 0: a sequence of 1 then 0 causes CR0 to be loaded with the contents of TC. 0 = disabled. 1 = enabled. - 0x1 + 1 1 read-write CAP0I Generate interrupt on channel 0 capture event: a CR0 load generates an interrupt. - 0x2 + 2 1 read-write CAP1RE Rising edge of capture channel 1: a sequence of 0 then 1 causes CR1 to be loaded with the contents of TC. 0 = disabled. 1 = enabled. - 0x3 + 3 1 read-write CAP1FE Falling edge of capture channel 1: a sequence of 1 then 0 causes CR1 to be loaded with the contents of TC. 0 = disabled. 1 = enabled. - 0x4 + 4 1 read-write CAP1I Generate interrupt on channel 1 capture event: a CR1 load generates an interrupt. - 0x5 + 5 1 read-write CAP2RE Rising edge of capture channel 2: a sequence of 0 then 1 causes CR2 to be loaded with the contents of TC. 0 = disabled. 1 = enabled. - 0x6 + 6 1 read-write CAP2FE Falling edge of capture channel 2: a sequence of 1 then 0 causes CR2 to be loaded with the contents of TC. 0 = disabled. 1 = enabled. - 0x7 + 7 1 read-write CAP2I Generate interrupt on channel 2 capture event: a CR2 load generates an interrupt. - 0x8 + 8 1 read-write CAP3RE Rising edge of capture channel 3: a sequence of 0 then 1 causes CR3 to be loaded with the contents of TC. 0 = disabled. 1 = enabled. - 0x9 + 9 1 read-write CAP3FE Falling edge of capture channel 3: a sequence of 1 then 0 causes CR3 to be loaded with the contents of TC. 0 = disabled. 1 = enabled. - 0xA + 10 1 read-write CAP3I Generate interrupt on channel 3 capture event: a CR3 load generates an interrupt. - 0xB + 11 1 read-write @@ -16863,28 +16889,28 @@ EM1 External Match 1. This bit reflects the state of output MAT1, whether or not this output is connected to a pin. When a match occurs between the TC and MR1, this bit can either toggle, go LOW, go HIGH, or do nothing, as selected by EMR[7:6]. This bit is driven to the MAT pins if the match function is selected via IOCON. 0 = LOW. 1 = HIGH. - 0x1 + 1 1 read-write EM2 External Match 2. This bit reflects the state of output MAT2, whether or not this output is connected to a pin. When a match occurs between the TC and MR2, this bit can either toggle, go LOW, go HIGH, or do nothing, as selected by EMR[9:8]. This bit is driven to the MAT pins if the match function is selected via IOCON. 0 = LOW. 1 = HIGH. - 0x2 + 2 1 read-write EM3 External Match 3. This bit reflects the state of output MAT3, whether or not this output is connected to a pin. When a match occurs between the TC and MR3, this bit can either toggle, go LOW, go HIGH, or do nothing, as selected by MR[11:10]. This bit is driven to the MAT pins if the match function is selected via IOCON. 0 = LOW. 1 = HIGH. - 0x3 + 3 1 read-write EMC0 External Match Control 0. Determines the functionality of External Match 0. - 0x4 + 4 2 read-write @@ -16913,7 +16939,7 @@ EMC1 External Match Control 1. Determines the functionality of External Match 1. - 0x6 + 6 2 read-write @@ -16942,7 +16968,7 @@ EMC2 External Match Control 2. Determines the functionality of External Match 2. - 0x8 + 8 2 read-write @@ -16971,7 +16997,7 @@ EMC3 External Match Control 3. Determines the functionality of External Match 3. - 0xA + 10 2 read-write @@ -17040,7 +17066,7 @@ CINSEL Count Input Select When bits 1:0 in this register are not 00, these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input in the CTCR, the 3 bits for that input in the Capture Control Register (CCR) must be programmed as 000. However, capture and/or interrupt can be selected for the other 3 CAPn inputs in the same timer. - 0x2 + 2 2 read-write @@ -17069,14 +17095,14 @@ ENCC Setting this bit to 1 enables clearing of the timer and the prescaler when the capture-edge event specified in bits 7:5 occurs. - 0x4 + 4 1 read-write SELCC Edge select. When bit 4 is 1, these bits select which capture input edge will cause the timer and prescaler to be cleared. These bits have no effect when bit 4 is low. Values 0x2 to 0x3 and 0x6 to 0x7 are reserved. - 0x5 + 5 3 read-write @@ -17145,7 +17171,7 @@ PWMEN1 PWM mode enable for channel1. - 0x1 + 1 1 read-write @@ -17164,7 +17190,7 @@ PWMEN2 PWM mode enable for channel2. - 0x2 + 2 1 read-write @@ -17183,7 +17209,7 @@ PWMEN3 PWM mode enable for channel3. Note: It is recommended to use match channel 3 to set the PWM cycle. - 0x3 + 3 1 read-write @@ -17218,6 +17244,51 @@ 11 + + CTIMER2 + LPC5411x Standard counter/timers (CTIMER0 to 4) + CTIMER + 0x40028000 + + 0 + 0x78 + registers + + + CTIMER2 + 36 + + + + CTIMER3 + LPC5411x Standard counter/timers (CTIMER0 to 4) + CTIMER + 0x40048000 + + 0 + 0x78 + registers + + + CTIMER3 + 13 + + + + CTIMER4 + LPC5411x Standard counter/timers (CTIMER0 to 4) + CTIMER + 0x40049000 + + 0 + 0x78 + registers + + + CTIMER4 + 37 + + WWDT LPC5411x Windowed Watchdog Timer (WWDT) @@ -17264,7 +17335,7 @@ WDRESET Watchdog reset enable bit. Once this bit has been written with a 1 it cannot be re-written with a 0. - 0x1 + 1 1 read-write @@ -17283,21 +17354,21 @@ WDTOF Watchdog time-out flag. Set when the watchdog timer times out, by a feed error, or by events associated with WDPROTECT. Cleared by software writing a 0 to this bit position. Causes a chip reset if WDRESET = 1. - 0x2 + 2 1 read-write WDINT Warning interrupt flag. Set when the timer is at or below the value in WDWARNINT. Cleared by software writing a 1 to this bit position. Note that this bit cannot be cleared while the WARNINT value is equal to the value of the TV register. This can occur if the value of WARNINT is 0 and the WDRESET bit is 0 when TV decrements to 0. - 0x3 + 3 1 read-write WDPROTECT Watchdog update mode. This bit can be set once by software and is only cleared by a reset. - 0x4 + 4 1 read-write @@ -17316,7 +17387,7 @@ LOCK Once this bit is set to one and a watchdog feed is performed, disabling or powering down the watchdog oscillator is prevented by hardware. This bit can be set once by software and is only cleared by any reset. - 0x5 + 5 1 read-write @@ -17454,7 +17525,7 @@ LOAD Determines how the timer interval value IVALUE -1 is loaded into the TIMERn register. This bit is write-only. Reading this bit always returns 0. - 0x1F + 31 1 read-write @@ -17521,7 +17592,7 @@ MODE Selects timer mode. - 0x1 + 1 2 read-write @@ -17575,7 +17646,7 @@ RUN Indicates the state of TIMERn. This bit is read-only. - 0x1 + 1 1 read-write @@ -17594,7 +17665,7 @@ INUSE Channel In Use flag. Operating details depend on the MULTITASK bit in the MODCFG register, and affects the use of IDLE_CH. See Idle channel register for details of the two operating modes. - 0x2 + 2 1 read-write @@ -17632,14 +17703,14 @@ NOB Identifies the number of timer bits in this MRT. (24 bits wide on this device.) - 0x4 + 4 5 read-write MULTITASK Selects the operating mode for the INUSE flags and the IDLE_CH register. - 0x1F + 31 1 read-write @@ -17669,7 +17740,7 @@ CHAN Idle channel. Reading the CHAN bits, returns the lowest idle timer channel. The number is positioned such that it can be used as an offset from the MRT base address in order to access the registers for the allocated channel. If all timer channels are running, CHAN = 0xF. See text above for more details. - 0x4 + 4 4 read-only @@ -17706,21 +17777,21 @@ GFLAG1 Monitors the interrupt flag of TIMER1. See description of channel 0. - 0x1 + 1 1 read-write GFLAG2 Monitors the interrupt flag of TIMER2. See description of channel 0. - 0x2 + 2 1 read-write GFLAG3 Monitors the interrupt flag of TIMER3. See description of channel 0. - 0x3 + 3 1 read-write @@ -17762,7 +17833,7 @@ REPEAT Repeat delay. 0 = One-time delay. 1 = Delay repeats continuously. - 0x1F + 31 1 read-write @@ -17787,7 +17858,7 @@ ACTIVE Active flag. 0 = The Micro-Tick Timer is stopped. 1 = The Micro-Tick Timer is currently active. - 0x1 + 1 1 read-write @@ -17812,49 +17883,49 @@ CAPEN1 Enable Capture 1. 1 = Enabled, 0 = Disabled. - 0x1 + 1 1 read-write CAPEN2 Enable Capture 2. 1 = Enabled, 0 = Disabled. - 0x2 + 2 1 read-write CAPEN3 Enable Capture 3. 1 = Enabled, 0 = Disabled. - 0x3 + 3 1 read-write CAPPOL0 Capture Polarity 0. 0 = Positive edge capture, 1 = Negative edge capture. - 0x8 + 8 1 read-write CAPPOL1 Capture Polarity 1. 0 = Positive edge capture, 1 = Negative edge capture. - 0x9 + 9 1 read-write CAPPOL2 Capture Polarity 2. 0 = Positive edge capture, 1 = Negative edge capture. - 0xA + 10 1 read-write CAPPOL3 Capture Polarity 3. 0 = Positive edge capture, 1 = Negative edge capture. - 0xB + 11 1 read-write @@ -17879,21 +17950,21 @@ CAPCLR1 Clear capture 1. Writing 1 to this bit clears the CAP1 register value. - 0x1 + 1 1 write-only CAPCLR2 Clear capture 2. Writing 1 to this bit clears the CAP2 register value. - 0x2 + 2 1 write-only CAPCLR3 Clear capture 3. Writing 1 to this bit clears the CAP3 register value. - 0x3 + 3 1 write-only @@ -17920,7 +17991,7 @@ VALID Capture Valid. When 1, a value has been captured based on a transition of the related UTICK_CAPn pin. Cleared by writing to the related bit in the CAPCLR register. - 0x1F + 31 1 read-only @@ -17928,21 +17999,6 @@ - - CTIMER2 - LPC5411x Standard counter/timers (CTIMER0 to 4) - CTIMER - 0x40028000 - - 0 - 0x78 - registers - - - CTIMER2 - 36 - - RTC LPC5411x Real-Time Clock (RTC) @@ -17989,7 +18045,7 @@ ALARM1HZ RTC 1 Hz timer alarm flag status. - 0x2 + 2 1 read-write @@ -18008,7 +18064,7 @@ WAKE1KHZ RTC 1 kHz timer wake-up flag status. - 0x3 + 3 1 read-write @@ -18027,7 +18083,7 @@ ALARMDPD_EN RTC 1 Hz timer alarm enable for Deep power-down. - 0x4 + 4 1 read-write @@ -18046,7 +18102,7 @@ WAKEDPD_EN RTC 1 kHz timer wake-up enable for Deep power-down. - 0x5 + 5 1 read-write @@ -18065,7 +18121,7 @@ RTC1KHZ_EN RTC 1 kHz clock enable. This bit can be set to 0 to conserve power if the 1 kHz timer is not used. This bit has no effect when the RTC is disabled (bit 7 of this register is 0). - 0x6 + 6 1 read-write @@ -18084,7 +18140,7 @@ RTC_EN RTC enable. - 0x7 + 7 1 read-write @@ -18103,7 +18159,7 @@ RTC_OSC_PD RTC oscillator power-down control. - 0x8 + 8 1 read-write @@ -18122,7 +18178,7 @@ RTC_OSC_BYPASS RTC oscillator bypass control. - 0x9 + 9 1 read-write @@ -18219,14 +18275,14 @@ CTIMER3 Standard counter/timer CTIMER3 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function. - 0xD + 13 1 read-write CTIMER4 Standard counter/timer CTIMER4 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function. - 0xE + 14 1 read-write @@ -18280,14 +18336,14 @@ CTIMER3 Controls the clock for CTIMER3. 0 = Disable; 1 = Enable. - 0xD + 13 1 read-write CTIMER4 Controls the clock for CTIMER4. 0 = Disable; 1 = Enable. - 0xE + 14 1 read-write @@ -18361,36 +18417,6 @@ - - CTIMER3 - LPC5411x Standard counter/timers (CTIMER0 to 4) - CTIMER - 0x40048000 - - 0 - 0x78 - registers - - - CTIMER3 - 13 - - - - CTIMER4 - LPC5411x Standard counter/timers (CTIMER0 to 4) - CTIMER - 0x40049000 - - 0 - 0x78 - registers - - - CTIMER4 - 37 - - SPIFI0 LPC5411x SPI Flash Interface (SPIFI) @@ -18425,28 +18451,28 @@ CSHIGH This field controls the minimum CS high time, expressed as a number of serial clock periods minus one. - 0x10 + 16 4 read-write D_PRFTCH_DIS This bit allows conditioning of memory mode prefetches based on the AHB HPROT (instruction/data) access information. A 1 in this register means that the SPIFI will not attempt a speculative prefetch when it encounters data accesses. - 0x15 + 21 1 read-write INTEN If this bit is 1 when a command ends, the SPIFI will assert its interrupt request output. See INTRQ in the status register for further details. - 0x16 + 22 1 read-write MODE3 SPI Mode 3 select. - 0x17 + 23 1 read-write @@ -18465,7 +18491,7 @@ PRFTCH_DIS Cache prefetching enable. The SPIFI includes an internal cache. A 1 in this bit disables prefetching of cache lines. - 0x1B + 27 1 read-write @@ -18484,7 +18510,7 @@ DUAL Select dual protocol. - 0x1C + 28 1 read-write @@ -18503,7 +18529,7 @@ RFCLK Select active clock edge for input data. - 0x1D + 29 1 read-write @@ -18522,7 +18548,7 @@ FBCLK Feedback clock select. - 0x1E + 30 1 read-write @@ -18541,7 +18567,7 @@ DMAEN A 1 in this bit enables the DMA Request output from the SPIFI. Set this bit only when a DMA channel is used to transfer data in peripheral mode. Do not set this bit when a DMA channel is used for memory-to-memory transfers from the SPIFI memory area. DMAEN should only be used in Command mode. - 0x1F + 31 1 read-write @@ -18566,14 +18592,14 @@ POLL This bit should be written as 1 only with an opcode that a) contains an input data field, and b) causes the serial flash device to return byte status repetitively (e.g., a Read Status command). When this bit is 1, the SPIFI hardware continues to read bytes until the test specified by the DATALEN field is met. The hardware tests the bit in each status byte selected by DATALEN bits 2:0, until a bit is found that is equal to DATALEN bit 3. When the test succeeds, the SPIFI captures the byte that meets this test so that it can be read from the Data Register, and terminates the command by raising CS. The end-of-command interrupt can be enabled to inform software when this occurs - 0xE + 14 1 read-write DOUT If the DATALEN field is not zero, this bit controls the direction of the data: - 0xF + 15 1 read-write @@ -18592,14 +18618,14 @@ INTLEN This field controls how many intermediate bytes precede the data. (Each such byte may require 8 or 2 SCK cycles, depending on whether the intermediate field is in serial, 2-bit, or 4-bit format.) Intermediate bytes are output by the SPIFI, and include post-address control information, dummy and delay bytes. See the description of the Intermediate Data register for the contents of such bytes. - 0x10 + 16 3 read-write FIELDFORM This field controls how the fields of the command are sent. - 0x13 + 19 2 read-write @@ -18628,7 +18654,7 @@ FRAMEFORM This field controls the opcode and address fields. - 0x15 + 21 3 read-write @@ -18672,7 +18698,7 @@ OPCODE The opcode of the command (not used for some FRAMEFORM values). - 0x18 + 24 8 read-write @@ -18762,28 +18788,28 @@ POLL This bit should be written as 0. - 0xE + 14 1 read-write DOUT This bit should be written as 0. - 0xF + 15 1 read-write INTLEN This field controls how many intermediate bytes precede the data. (Each such byte may require 8 or 2 SCK cycles, depending on whether the intermediate field is in serial, 2-bit, or 4-bit format.) Intermediate bytes are output by the SPIFI, and include post-address control information, dummy and delay bytes. See the description of the Intermediate Data register for the contents of such bytes. - 0x10 + 16 3 read-write FIELDFORM This field controls how the fields of the command are sent. - 0x13 + 19 2 read-write @@ -18812,7 +18838,7 @@ FRAMEFORM This field controls the opcode and address fields. - 0x15 + 21 3 read-write @@ -18856,7 +18882,7 @@ OPCODE The opcode of the command (not used for some FRAMEFORM values). - 0x18 + 24 8 read-write @@ -18881,28 +18907,28 @@ CMD This bit is 1 when the Command register is written. It is cleared by a hardware reset, a write to the RESET bit in this register, or the deassertion of CS which indicates that the command has completed communication with the SPI Flash. - 0x1 + 1 1 read-write RESET Write a 1 to this bit to abort a current command or memory mode. This bit is cleared when the hardware is ready for a new command to be written to the Command register. - 0x4 + 4 1 read-write INTRQ This bit reflects the SPIFI interrupt request. Write a 1 to this bit to clear it. This bit is set when a CMD was previously 1 and has been cleared due to the deassertion of CS. - 0x5 + 5 1 read-write VERSION - - 0x18 + 24 8 read-write @@ -18967,7 +18993,7 @@ ACTIVEINT Summarizes whether any enabled interrupts (other than error interrupts) are pending. - 0x1 + 1 1 read-only @@ -18986,7 +19012,7 @@ ACTIVEERRINT Summarizes whether any error interrupts are pending. - 0x2 + 2 1 read-only @@ -19016,7 +19042,7 @@ OFFSET Address bits 31:9 of the beginning of the DMA descriptor table. For 18 channels, the table must begin on a 512 byte boundary. - 0x9 + 9 23 read-write @@ -19275,7 +19301,7 @@ HWTRIGEN Hardware Triggering Enable for this channel. - 0x1 + 1 1 read-write @@ -19294,7 +19320,7 @@ TRIGPOL Trigger Polarity. Selects the polarity of a hardware trigger for this channel. - 0x4 + 4 1 read-write @@ -19313,7 +19339,7 @@ TRIGTYPE Trigger Type. Selects hardware trigger as edge triggered or level triggered. - 0x5 + 5 1 read-write @@ -19332,7 +19358,7 @@ TRIGBURST Trigger Burst. Selects whether hardware triggers cause a single or burst transfer. - 0x6 + 6 1 read-write @@ -19351,14 +19377,14 @@ BURSTPOWER Burst Power is used in two ways. It always selects the address wrap size when SRCBURSTWRAP and/or DSTBURSTWRAP modes are selected (see descriptions elsewhere in this register). When the TRIGBURST field elsewhere in this register = 1, Burst Power selects how many transfers are performed for each DMA trigger. This can be used, for example, with peripherals that contain a FIFO that can initiate a DMA operation when the FIFO reaches a certain level. 0000: Burst size = 1 (20). 0001: Burst size = 2 (21). 0010: Burst size = 4 (22). 1010: Burst size = 1024 (210). This corresponds to the maximum supported transfer count. others: not supported. The total transfer length as defined in the XFERCOUNT bits in the XFERCFG register must be an even multiple of the burst size. - 0x8 + 8 4 read-write SRCBURSTWRAP Source Burst Wrap. When enabled, the source data address for the DMA is 'wrapped', meaning that the source address range for each burst will be the same. As an example, this could be used to read several sequential registers from a peripheral for each DMA burst, reading the same registers again for each burst. - 0xE + 14 1 read-write @@ -19377,7 +19403,7 @@ DSTBURSTWRAP Destination Burst Wrap. When enabled, the destination data address for the DMA is 'wrapped', meaning that the destination address range for each burst will be the same. As an example, this could be used to write several sequential registers to a peripheral for each DMA burst, writing the same registers again for each burst. - 0xF + 15 1 read-write @@ -19396,7 +19422,7 @@ CHPRIORITY Priority of this channel when multiple DMA requests are pending. Eight priority levels are supported: 0x0 = highest priority. 0x7 = lowest priority. - 0x10 + 16 3 read-write @@ -19433,7 +19459,7 @@ TRIG Trigger flag. Indicates that the trigger for this channel is currently set. This bit is cleared at the end of an entire transfer or upon reload when CLRTRIG = 1. - 0x2 + 2 1 read-only @@ -19482,7 +19508,7 @@ RELOAD Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted. Reloading allows ping-pong and linked transfers. - 0x1 + 1 1 read-write @@ -19501,7 +19527,7 @@ SWTRIG Software Trigger. - 0x2 + 2 1 read-write @@ -19520,7 +19546,7 @@ CLRTRIG Clear Trigger. - 0x3 + 3 1 read-write @@ -19539,7 +19565,7 @@ SETINTA Set Interrupt flag A for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed. - 0x4 + 4 1 read-write @@ -19558,7 +19584,7 @@ SETINTB Set Interrupt flag B for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed. - 0x5 + 5 1 read-write @@ -19577,7 +19603,7 @@ WIDTH Transfer width used for this DMA channel. - 0x8 + 8 2 read-write @@ -19601,7 +19627,7 @@ SRCINC Determines whether the source address is incremented for each DMA transfer. - 0xC + 12 2 read-write @@ -19630,7 +19656,7 @@ DSTINC Determines whether the destination address is incremented for each DMA transfer. - 0xE + 14 2 read-write @@ -19659,7 +19685,7 @@ XFERCOUNT Total number of transfers to be performed, minus 1 encoded. The number of bytes transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller uses this bit field during transfer to count down. Hence, it cannot be used by software to read back the size of the transfer, for instance, in an interrupt handler. 0x0 = a total of 1 transfer will be performed. 0x1 = a total of 2 transfers will be performed. 0x3FF = a total of 1,024 transfers will be performed. - 0x10 + 16 10 read-write @@ -19706,21 +19732,21 @@ DEV_EN USB device enable. If this bit is set, the HW will start responding on packets for function address DEV_ADDR. - 0x7 + 7 1 read-write SETUP SETUP token received. If a SETUP token is received and acknowledged by the device, this bit is set. As long as this bit is set all received IN and OUT tokens will be NAKed by HW. SW must clear this bit by writing a one. If this bit is zero, HW will handle the tokens to the CTRL EP0 as indicated by the CTRL EP0 IN and OUT data information programmed by SW. - 0x8 + 8 1 read-write FORCE_NEEDCLK Forces the NEEDCLK output to always be on: - 0x9 + 9 1 read-write @@ -19739,7 +19765,7 @@ LPM_SUP LPM Supported: - 0xB + 11 1 read-write @@ -19758,7 +19784,7 @@ INTONNAK_AO Interrupt on NAK for interrupt and bulk OUT EP - 0xC + 12 1 read-write @@ -19777,7 +19803,7 @@ INTONNAK_AI Interrupt on NAK for interrupt and bulk IN EP - 0xD + 13 1 read-write @@ -19796,7 +19822,7 @@ INTONNAK_CO Interrupt on NAK for control OUT EP - 0xE + 14 1 read-write @@ -19815,7 +19841,7 @@ INTONNAK_CI Interrupt on NAK for control IN EP - 0xF + 15 1 read-write @@ -19834,56 +19860,56 @@ DCON Device status - connect. The connect bit must be set by SW to indicate that the device must signal a connect. The pull-up resistor on USB_DP will be enabled when this bit is set and the VBUSDEBOUNCED bit is one. - 0x10 + 16 1 read-write DSUS Device status - suspend. The suspend bit indicates the current suspend state. It is set to 1 when the device hasn't seen any activity on its upstream port for more than 3 milliseconds. It is reset to 0 on any activity. When the device is suspended (Suspend bit DSUS = 1) and the software writes a 0 to it, the device will generate a remote wake-up. This will only happen when the device is connected (Connect bit = 1). When the device is not connected or not suspended, a writing a 0 has no effect. Writing a 1 never has an effect. - 0x11 + 17 1 read-write LPM_SUS Device status - LPM Suspend. This bit represents the current LPM suspend state. It is set to 1 by HW when the device has acknowledged the LPM request from the USB host and the Token Retry Time of 10 ms has elapsed. When the device is in the LPM suspended state (LPM suspend bit = 1) and the software writes a zero to this bit, the device will generate a remote walk-up. Software can only write a zero to this bit when the LPM_REWP bit is set to 1. HW resets this bit when it receives a host initiated resume. HW only updates the LPM_SUS bit when the LPM_SUPP bit is equal to one. - 0x13 + 19 1 read-write LPM_REWP LPM Remote Wake-up Enabled by USB host. HW sets this bit to one when the bRemoteWake bit in the LPM extended token is set to 1. HW will reset this bit to 0 when it receives the host initiated LPM resume, when a remote wake-up is sent by the device or when a USB bus reset is received. Software can use this bit to check if the remote wake-up feature is enabled by the host for the LPM transaction. - 0x14 + 20 1 read-only DCON_C Device status - connect change. The Connect Change bit is set when the device's pull-up resistor is disconnected because VBus disappeared. The bit is reset by writing a one to it. - 0x18 + 24 1 read-write DSUS_C Device status - suspend change. The suspend change bit is set to 1 when the suspend bit toggles. The suspend bit can toggle because: - The device goes in the suspended state - The device is disconnected - The device receives resume signaling on its upstream port. The bit is reset by writing a one to it. - 0x19 + 25 1 read-write DRES_C Device status - reset change. This bit is set when the device received a bus reset. On a bus reset the device will automatically go to the default state (unconfigured and responding to address 0). The bit is reset by writing a one to it. - 0x1A + 26 1 read-write VBUSDEBOUNCED This bit indicates if Vbus is detected or not. The bit raises immediately when Vbus becomes high. It drops to zero if Vbus is low for at least 3 ms. If this bit is high and the DCon bit is set, the HW will enable the pull-up resistor to signal a connect. - 0x1C + 28 1 read-only @@ -19908,7 +19934,7 @@ ERR_CODE The error code which last occurred: - 0xB + 11 4 read-write @@ -20008,7 +20034,7 @@ EP_LIST Start address of the USB EP Command/Status List. - 0x8 + 8 24 read-write @@ -20026,7 +20052,7 @@ DA_BUF Start address of the buffer pointer page where all endpoint data buffers are located. - 0x16 + 22 10 read-write @@ -20051,14 +20077,14 @@ HIRD_SW Host Initiated Resume Duration - SW. This is the time duration required by the USB device system to come out of LPM initiated suspend after receiving the host initiated LPM resume. - 0x4 + 4 4 read-write DATA_PENDING As long as this bit is set to one and LPM supported bit is set to one, HW will return a NYET handshake on every LPM token it receives. If LPM supported bit is set to one and this bit is zero, HW will return an ACK handshake on every LPM token it receives. If SW has still data pending and LPM is supported, it must set this bit to 1. - 0x8 + 8 1 read-write @@ -20094,7 +20120,7 @@ BUF Buffer in use: This register has one bit per physical endpoint. 0: HW is accessing buffer 0. 1: HW is accessing buffer 1. - 0x2 + 2 8 read-write @@ -20112,7 +20138,7 @@ BUF_SB Buffer usage: This register has one bit per physical endpoint. 0: Single-buffer. 1: Double-buffer. If the bit is set to single-buffer (0), it will not toggle the corresponding EPINUSE bit when it clears the active bit. If the bit is set to double-buffer (1), HW will toggle the EPINUSE bit when it clears the Active bit for the buffer. - 0x2 + 2 8 read-write @@ -20137,77 +20163,77 @@ EP0IN Interrupt status register bit for the Control EP0 IN direction. This bit will be set if NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_CI is set, this bit will also be set when a NAK is transmitted for the Control EP0 IN direction. Software can clear this bit by writing a one to it. - 0x1 + 1 1 read-write EP1OUT Interrupt status register bit for the EP1 OUT direction. This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_AO is set, this bit will also be set when a NAK is transmitted for the EP1 OUT direction. Software can clear this bit by writing a one to it. - 0x2 + 2 1 read-write EP1IN Interrupt status register bit for the EP1 IN direction. This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_AI is set, this bit will also be set when a NAK is transmitted for the EP1 IN direction. Software can clear this bit by writing a one to it. - 0x3 + 3 1 read-write EP2OUT Interrupt status register bit for the EP2 OUT direction. This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_AO is set, this bit will also be set when a NAK is transmitted for the EP2 OUT direction. Software can clear this bit by writing a one to it. - 0x4 + 4 1 read-write EP2IN Interrupt status register bit for the EP2 IN direction. This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_AI is set, this bit will also be set when a NAK is transmitted for the EP2 IN direction. Software can clear this bit by writing a one to it. - 0x5 + 5 1 read-write EP3OUT Interrupt status register bit for the EP3 OUT direction. This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_AO is set, this bit will also be set when a NAK is transmitted for the EP3 OUT direction. Software can clear this bit by writing a one to it. - 0x6 + 6 1 read-write EP3IN Interrupt status register bit for the EP3 IN direction. This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_AI is set, this bit will also be set when a NAK is transmitted for the EP3 IN direction. Software can clear this bit by writing a one to it. - 0x7 + 7 1 read-write EP4OUT Interrupt status register bit for the EP4 OUT direction. This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_AO is set, this bit will also be set when a NAK is transmitted for the EP4 OUT direction. Software can clear this bit by writing a one to it. - 0x8 + 8 1 read-write EP4IN Interrupt status register bit for the EP4 IN direction. This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_AI is set, this bit will also be set when a NAK is transmitted for the EP4 IN direction. Software can clear this bit by writing a one to it. - 0x9 + 9 1 read-write FRAME_INT Frame interrupt. This bit is set to one every millisecond when the VbusDebounced bit and the DCON bit are set. This bit can be used by software when handling isochronous endpoints. Software can clear this bit by writing a one to it. - 0x1E + 30 1 read-write DEV_INT Device status interrupt. This bit is set by HW when one of the bits in the Device Status Change register are set. Software can clear this bit by writing a one to it. - 0x1F + 31 1 read-write @@ -20232,14 +20258,14 @@ FRAME_INT_EN If this bit is set and the corresponding USB interrupt status bit is set, a HW interrupt is generated on the interrupt line indicated by the corresponding USB interrupt routing bit. - 0x1E + 30 1 read-write DEV_INT_EN If this bit is set and the corresponding USB interrupt status bit is set, a HW interrupt is generated on the interrupt line indicated by the corresponding USB interrupt routing bit. - 0x1F + 31 1 read-write @@ -20264,14 +20290,14 @@ FRAME_SET_INT If software writes a one to one of these bits, the corresponding USB interrupt status bit is set. When this register is read, the same value as the USB interrupt status register is returned. - 0x1E + 30 1 read-write DEV_SET_INT If software writes a one to one of these bits, the corresponding USB interrupt status bit is set. When this register is read, the same value as the USB interrupt status register is returned. - 0x1F + 31 1 read-write @@ -20343,7 +20369,7 @@ CLKMODE SCT clock mode - 0x1 + 1 2 read-write @@ -20372,7 +20398,7 @@ CKSEL SCT clock select. The specific functionality of the designated input/edge is dependent on the CLKMODE bit selection in this register. - 0x3 + 3 4 read-write @@ -20421,35 +20447,35 @@ NORELAOD_L A 1 in this bit prevents the lower match registers from being reloaded from their respective reload registers. Setting this bit eliminates the need to write to the reload registers MATCHREL if the match values are fixed. Software can write to set or clear this bit at any time. This bit applies to both the higher and lower registers when the UNIFY bit is set. - 0x7 + 7 1 read-write NORELOAD_H A 1 in this bit prevents the higher match registers from being reloaded from their respective reload registers. Setting this bit eliminates the need to write to the reload registers MATCHREL if the match values are fixed. Software can write to set or clear this bit at any time. This bit is not used when the UNIFY bit is set. - 0x8 + 8 1 read-write INSYNC Synchronization for input N (bit 9 = input 0, bit 10 = input 1,, bit 12 = input 3); all other bits are reserved. A 1 in one of these bits subjects the corresponding input to synchronization to the SCT clock, before it is used to create an event. If an input is known to already be synchronous to the SCT clock, this bit may be set to 0 for faster input response. (Note: The SCT clock is the system clock for CKMODEs 0-2. It is the selected, asynchronous SCT input clock for CKMODE3). Note that the INSYNC field only affects inputs used for event generation. It does not apply to the clock input specified in the CKSEL field. - 0x9 + 9 4 read-write AUTOLIMIT_L A one in this bit causes a match on match register 0 to be treated as a de-facto LIMIT condition without the need to define an associated event. As with any LIMIT event, this automatic limit causes the counter to be cleared to zero in unidirectional mode or to change the direction of count in bi-directional mode. Software can write to set or clear this bit at any time. This bit applies to both the higher and lower registers when the UNIFY bit is set. - 0x11 + 17 1 read-write AUTOLIMIT_H A one in this bit will cause a match on match register 0 to be treated as a de-facto LIMIT condition without the need to define an associated event. As with any LIMIT event, this automatic limit causes the counter to be cleared to zero in unidirectional mode or to change the direction of count in bi-directional mode. Software can write to set or clear this bit at any time. This bit is not used when the UNIFY bit is set. - 0x12 + 18 1 read-write @@ -20474,28 +20500,28 @@ STOP_L When this bit is 1 and HALT is 0, the L or unified counter does not run, but I/O events related to the counter can occur. If a designated start event occurs, this bit is cleared and counting resumes. - 0x1 + 1 1 read-write HALT_L When this bit is 1, the L or unified counter does not run and no events can occur. A reset sets this bit. When the HALT_L bit is one, the STOP_L bit is cleared. It is possible to remove the halt condition while keeping the SCT in the stop condition (not running) with a single write to this register to simultaneously clear the HALT bit and set the STOP bit. Once set, only software can clear this bit to restore counter operation. This bit is set on reset. - 0x2 + 2 1 read-write CLRCTR_L Writing a 1 to this bit clears the L or unified counter. This bit always reads as 0. - 0x3 + 3 1 read-write BIDIR_L L or unified counter direction select - 0x4 + 4 1 read-write @@ -20514,42 +20540,42 @@ PRE_L Specifies the factor by which the SCT clock is prescaled to produce the L or unified counter clock. The counter clock is clocked at the rate of the SCT clock divided by PRE_L+1. Clear the counter (by writing a 1 to the CLRCTR bit) whenever changing the PRE value. - 0x5 + 5 8 read-write DOWN_H This bit is 1 when the H counter is counting down. Hardware sets this bit when the counter is counting, a counter limit condition occurs, and BIDIR is 1. Hardware clears this bit when the counter is counting down and a limit condition occurs or when the counter reaches 0. - 0x10 + 16 1 read-write STOP_H When this bit is 1 and HALT is 0, the H counter does not, run but I/O events related to the counter can occur. If such an event matches the mask in the Start register, this bit is cleared and counting resumes. - 0x11 + 17 1 read-write HALT_H When this bit is 1, the H counter does not run and no events can occur. A reset sets this bit. When the HALT_H bit is one, the STOP_H bit is cleared. It is possible to remove the halt condition while keeping the SCT in the stop condition (not running) with a single write to this register to simultaneously clear the HALT bit and set the STOP bit. Once set, this bit can only be cleared by software to restore counter operation. This bit is set on reset. - 0x12 + 18 1 read-write CLRCTR_H Writing a 1 to this bit clears the H counter. This bit always reads as 0. - 0x13 + 19 1 read-write BIDIR_H Direction select - 0x14 + 20 1 read-write @@ -20568,7 +20594,7 @@ PRE_H Specifies the factor by which the SCT clock is prescaled to produce the H counter clock. The counter clock is clocked at the rate of the SCT clock divided by PRELH+1. Clear the counter (by writing a 1 to the CLRCTR bit) whenever changing the PRE value. - 0x15 + 21 8 read-write @@ -20593,7 +20619,7 @@ LIMMSK_H If bit n is one, event n is used as a counter limit for the H counter (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of events in this SCT. - 0x10 + 16 16 read-write @@ -20618,7 +20644,7 @@ HALTMSK_H If bit n is one, event n sets the HALT_H bit in the CTRL register (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of events in this SCT. - 0x10 + 16 16 read-write @@ -20643,7 +20669,7 @@ STOPMSK_H If bit n is one, event n sets the STOP_H bit in the CTRL register (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of events in this SCT. - 0x10 + 16 16 read-write @@ -20668,7 +20694,7 @@ STARTMSK_H If bit n is one, event n clears the STOP_H bit in the CTRL register (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of events in this SCT. - 0x10 + 16 16 read-write @@ -20693,7 +20719,7 @@ CTR_H When UNIFY = 0, read or write the 16-bit H counter value. When UNIFY = 1, read or write the upper 16 bits of the 32-bit unified counter. - 0x10 + 16 16 read-write @@ -20718,7 +20744,7 @@ STATE_H State variable. - 0x10 + 16 5 read-write @@ -20743,217 +20769,217 @@ AIN1 Input 1 state. Input 1 state on the last SCT clock edge. - 0x1 + 1 1 read-only AIN2 Input 2 state. Input 2 state on the last SCT clock edge. - 0x2 + 2 1 read-only AIN3 Input 3 state. Input 3 state on the last SCT clock edge. - 0x3 + 3 1 read-only AIN4 Input 4 state. Input 4 state on the last SCT clock edge. - 0x4 + 4 1 read-only AIN5 Input 5 state. Input 5 state on the last SCT clock edge. - 0x5 + 5 1 read-only AIN6 Input 6 state. Input 6 state on the last SCT clock edge. - 0x6 + 6 1 read-only AIN7 Input 7 state. Input 7 state on the last SCT clock edge. - 0x7 + 7 1 read-only AIN8 Input 8 state. Input 8 state on the last SCT clock edge. - 0x8 + 8 1 read-only AIN9 Input 9 state. Input 9 state on the last SCT clock edge. - 0x9 + 9 1 read-only AIN10 Input 10 state. Input 10 state on the last SCT clock edge. - 0xA + 10 1 read-only AIN11 Input 11 state. Input 11 state on the last SCT clock edge. - 0xB + 11 1 read-only AIN12 Input 12 state. Input 12 state on the last SCT clock edge. - 0xC + 12 1 read-only AIN13 Input 13 state. Input 13 state on the last SCT clock edge. - 0xD + 13 1 read-only AIN14 Input 14 state. Input 14 state on the last SCT clock edge. - 0xE + 14 1 read-only AIN15 Input 15 state. Input 15 state on the last SCT clock edge. - 0xF + 15 1 read-only SIN0 Input 0 state. Input 0 state following the synchronization specified by INSYNC. - 0x10 + 16 1 read-only SIN1 Input 1 state. Input 1 state following the synchronization specified by INSYNC. - 0x11 + 17 1 read-only SIN2 Input 2 state. Input 2 state following the synchronization specified by INSYNC. - 0x12 + 18 1 read-only SIN3 Input 3 state. Input 3 state following the synchronization specified by INSYNC. - 0x13 + 19 1 read-only SIN4 Input 4 state. Input 4 state following the synchronization specified by INSYNC. - 0x14 + 20 1 read-only SIN5 Input 5 state. Input 5 state following the synchronization specified by INSYNC. - 0x15 + 21 1 read-only SIN6 Input 6 state. Input 6 state following the synchronization specified by INSYNC. - 0x16 + 22 1 read-only SIN7 Input 7 state. Input 7 state following the synchronization specified by INSYNC. - 0x17 + 23 1 read-only SIN8 Input 8 state. Input 8 state following the synchronization specified by INSYNC. - 0x18 + 24 1 read-only SIN9 Input 9 state. Input 9 state following the synchronization specified by INSYNC. - 0x19 + 25 1 read-only SIN10 Input 10 state. Input 10 state following the synchronization specified by INSYNC. - 0x1A + 26 1 read-only SIN11 Input 11 state. Input 11 state following the synchronization specified by INSYNC. - 0x1B + 27 1 read-only SIN12 Input 12 state. Input 12 state following the synchronization specified by INSYNC. - 0x1C + 28 1 read-only SIN13 Input 13 state. Input 13 state following the synchronization specified by INSYNC. - 0x1D + 29 1 read-only SIN14 Input 14 state. Input 14 state following the synchronization specified by INSYNC. - 0x1E + 30 1 read-only SIN15 Input 15 state. Input 15 state following the synchronization specified by INSYNC. - 0x1F + 31 1 read-only @@ -20978,7 +21004,7 @@ REGMOD_H Each bit controls one match/capture register (register 0 = bit 16, register 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT. 0 = register operates as match registers. 1 = register operates as capture registers. - 0x10 + 16 16 read-write @@ -21038,7 +21064,7 @@ SETCLR1 Set/clear operation on output 1. Value 0x3 is reserved. Do not program this value. - 0x2 + 2 2 read-write @@ -21062,7 +21088,7 @@ SETCLR2 Set/clear operation on output 2. Value 0x3 is reserved. Do not program this value. - 0x4 + 4 2 read-write @@ -21086,7 +21112,7 @@ SETCLR3 Set/clear operation on output 3. Value 0x3 is reserved. Do not program this value. - 0x6 + 6 2 read-write @@ -21110,7 +21136,7 @@ SETCLR4 Set/clear operation on output 4. Value 0x3 is reserved. Do not program this value. - 0x8 + 8 2 read-write @@ -21134,7 +21160,7 @@ SETCLR5 Set/clear operation on output 5. Value 0x3 is reserved. Do not program this value. - 0xA + 10 2 read-write @@ -21158,7 +21184,7 @@ SETCLR6 Set/clear operation on output 6. Value 0x3 is reserved. Do not program this value. - 0xC + 12 2 read-write @@ -21182,7 +21208,7 @@ SETCLR7 Set/clear operation on output 7. Value 0x3 is reserved. Do not program this value. - 0xE + 14 2 read-write @@ -21206,7 +21232,7 @@ SETCLR8 Set/clear operation on output 8. Value 0x3 is reserved. Do not program this value. - 0x10 + 16 2 read-write @@ -21230,7 +21256,7 @@ SETCLR9 Set/clear operation on output 9. Value 0x3 is reserved. Do not program this value. - 0x12 + 18 2 read-write @@ -21254,7 +21280,7 @@ SETCLR10 Set/clear operation on output 10. Value 0x3 is reserved. Do not program this value. - 0x14 + 20 2 read-write @@ -21278,7 +21304,7 @@ SETCLR11 Set/clear operation on output 11. Value 0x3 is reserved. Do not program this value. - 0x16 + 22 2 read-write @@ -21302,7 +21328,7 @@ SETCLR12 Set/clear operation on output 12. Value 0x3 is reserved. Do not program this value. - 0x18 + 24 2 read-write @@ -21326,7 +21352,7 @@ SETCLR13 Set/clear operation on output 13. Value 0x3 is reserved. Do not program this value. - 0x1A + 26 2 read-write @@ -21350,7 +21376,7 @@ SETCLR14 Set/clear operation on output 14. Value 0x3 is reserved. Do not program this value. - 0x1C + 28 2 read-write @@ -21374,7 +21400,7 @@ SETCLR15 Set/clear operation on output 15. Value 0x3 is reserved. Do not program this value. - 0x1E + 30 2 read-write @@ -21438,7 +21464,7 @@ O1RES Effect of simultaneous set and clear on output 1. - 0x2 + 2 2 read-write @@ -21467,7 +21493,7 @@ O2RES Effect of simultaneous set and clear on output 2. - 0x4 + 4 2 read-write @@ -21496,7 +21522,7 @@ O3RES Effect of simultaneous set and clear on output 3. - 0x6 + 6 2 read-write @@ -21525,7 +21551,7 @@ O4RES Effect of simultaneous set and clear on output 4. - 0x8 + 8 2 read-write @@ -21554,7 +21580,7 @@ O5RES Effect of simultaneous set and clear on output 5. - 0xA + 10 2 read-write @@ -21583,7 +21609,7 @@ O6RES Effect of simultaneous set and clear on output 6. - 0xC + 12 2 read-write @@ -21612,7 +21638,7 @@ O7RES Effect of simultaneous set and clear on output 7. - 0xE + 14 2 read-write @@ -21641,7 +21667,7 @@ O8RES Effect of simultaneous set and clear on output 8. - 0x10 + 16 2 read-write @@ -21670,7 +21696,7 @@ O9RES Effect of simultaneous set and clear on output 9. - 0x12 + 18 2 read-write @@ -21699,7 +21725,7 @@ O10RES Effect of simultaneous set and clear on output 10. - 0x14 + 20 2 read-write @@ -21728,7 +21754,7 @@ O11RES Effect of simultaneous set and clear on output 11. - 0x16 + 22 2 read-write @@ -21757,7 +21783,7 @@ O12RES Effect of simultaneous set and clear on output 12. - 0x18 + 24 2 read-write @@ -21786,7 +21812,7 @@ O13RES Effect of simultaneous set and clear on output 13. - 0x1A + 26 2 read-write @@ -21815,7 +21841,7 @@ O14RES Effect of simultaneous set and clear on output 14. - 0x1C + 28 2 read-write @@ -21844,7 +21870,7 @@ O15RES Effect of simultaneous set and clear on output 15. - 0x1E + 30 2 read-write @@ -21891,14 +21917,14 @@ DRL0 A 1 in this bit triggers DMA request 0 when it loads the MATCH_L/Unified registers from the RELOAD_L/Unified registers. - 0x1E + 30 1 read-write DRQ0 This read-only bit indicates the state of DMA Request 0. Note that if the related DMA channel is enabled and properly set up, it is unlikely that software will see this flag, it will be cleared rapidly by the DMA service. The flag remaining set could point to an issue with DMA setup. - 0x1F + 31 1 read-write @@ -21923,14 +21949,14 @@ DRL1 A 1 in this bit triggers DMA request 1 when it loads the Match L/Unified registers from the Reload L/Unified registers. - 0x1E + 30 1 read-write DRQ1 This read-only bit indicates the state of DMA Request 1. Note that if the related DMA channel is enabled and properly set up, it is unlikely that software will see this flag, it will be cleared rapidly by the DMA service. The flag remaining set could point to an issue with DMA setup. - 0x1F + 31 1 read-write @@ -22009,14 +22035,14 @@ BUSERRL The most recent bus error from this SCT involved writing CTR L/Unified, STATE L/Unified, MATCH L/Unified, or the Output register when the L/U counter was not halted. A word write to certain L and H registers can be half successful and half unsuccessful. - 0x1E + 30 1 read-write BUSERRH The most recent bus error from this SCT involved writing CTR H, STATE H, MATCH H, or the Output register when the H counter was not halted. - 0x1F + 31 1 read-write @@ -22044,7 +22070,7 @@ CAPn_H When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured. - 0x10 + 16 16 read-write @@ -22072,7 +22098,7 @@ MATCHn_H When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter. - 0x10 + 16 16 read-write @@ -22100,7 +22126,7 @@ CAPCONn_H If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT. - 0x10 + 16 16 read-write @@ -22128,7 +22154,7 @@ RELOADn_H When UNIFY = 0, specifies the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn register. - 0x10 + 16 16 read-write @@ -22177,7 +22203,7 @@ HEVENT Select L/H counter. Do not set this bit if UNIFY = 1. - 0x4 + 4 1 read-write @@ -22196,7 +22222,7 @@ OUTSEL Input/output select - 0x5 + 5 1 read-write @@ -22215,14 +22241,14 @@ IOSEL Selects the input or output signal number associated with this event (if any). Do not select an input in this register if CKMODE is 1x. In this case the clock input is an implicit ingredient of every event. - 0x6 + 6 4 read-write IOCOND Selects the I/O condition for event n. (The detection of edges on outputs lag the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT clock period . - 0xA + 10 2 read-write @@ -22251,7 +22277,7 @@ COMBMODE Selects how the specified match and I/O condition are used and combined. - 0xC + 12 2 read-write @@ -22280,7 +22306,7 @@ STATELD This bit controls how the STATEV value modifies the state selected by HEVENT when this event is the highest-numbered event occurring for that state. - 0xE + 14 1 read-write @@ -22299,21 +22325,21 @@ STATEV This value is loaded into or added to the state selected by HEVENT, depending on STATELD, when this event is the highest-numbered event occurring for that state. If STATELD and STATEV are both zero, there is no change to the STATE value. - 0xF + 15 5 read-write MATCHMEM If this bit is one and the COMBMODE field specifies a match component to the triggering of this event, then a match is considered to be active whenever the counter value is GREATER THAN OR EQUAL TO the value specified in the match register when counting up, LESS THEN OR EQUAL TO the match value when counting down. If this bit is zero, a match is only be active during the cycle when the counter is equal to the match value. - 0x14 + 20 1 read-write DIRECTION Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved. - 0x15 + 21 2 read-write @@ -22395,8 +22421,8 @@ FLEXCOMM0 LPC5411x Flexcomm serial communication FLEXCOMM - 0x40086000 FLEXCOMM + 0x40086000 0 0x1000 @@ -22458,7 +22484,7 @@ LOCK Lock the peripheral select. This field is writable by software. - 0x3 + 3 1 read-write @@ -22477,7 +22503,7 @@ USARTPRESENT USART present indicator. This field is Read-only. - 0x4 + 4 1 read-only @@ -22496,7 +22522,7 @@ SPIPRESENT SPI present indicator. This field is Read-only. - 0x5 + 5 1 read-only @@ -22515,7 +22541,7 @@ I2CPRESENT I2C present indicator. This field is Read-only. - 0x6 + 6 1 read-only @@ -22534,7 +22560,7 @@ I2SPRESENT I 2S present indicator. This field is Read-only. - 0x7 + 7 1 read-only @@ -22553,7 +22579,7 @@ ID Flexcomm ID. - 0xC + 12 20 read-only @@ -22571,21 +22597,21 @@ Minor_Rev Minor revision of module implementation. - 0x8 + 8 4 read-only Major_Rev Major revision of module implementation. - 0xC + 12 4 read-only ID Module identifier for the selected function. - 0x10 + 16 16 read-only @@ -22593,13 +22619,118 @@ + + FLEXCOMM1 + LPC5411x Flexcomm serial communication + FLEXCOMM + 0x40087000 + + 0 + 0x1000 + registers + + + FLEXCOMM1 + 15 + + + + FLEXCOMM2 + LPC5411x Flexcomm serial communication + FLEXCOMM + 0x40088000 + + 0 + 0x1000 + registers + + + FLEXCOMM2 + 16 + + + + FLEXCOMM3 + LPC5411x Flexcomm serial communication + FLEXCOMM + 0x40089000 + + 0 + 0x1000 + registers + + + FLEXCOMM3 + 17 + + + + FLEXCOMM4 + LPC5411x Flexcomm serial communication + FLEXCOMM + 0x4008A000 + + 0 + 0x1000 + registers + + + FLEXCOMM4 + 18 + + + + FLEXCOMM5 + LPC5411x Flexcomm serial communication + FLEXCOMM + 0x40096000 + + 0 + 0x1000 + registers + + + FLEXCOMM5 + 19 + + + + FLEXCOMM6 + LPC5411x Flexcomm serial communication + FLEXCOMM + 0x40097000 + + 0 + 0x1000 + registers + + + FLEXCOMM6 + 20 + + + + FLEXCOMM7 + LPC5411x Flexcomm serial communication + FLEXCOMM + 0x40098000 + + 0 + 0x1000 + registers + + + FLEXCOMM7 + 21 + + I2C0 - FLEXCOMM0 LPC5411x I2C-bus interfaces + FLEXCOMM0 I2C - 0x40086000 I2C + 0x40086000 0 0x884 @@ -22641,7 +22772,7 @@ SLVEN Slave Enable. When disabled, configurations settings for the Slave function are not changed, but the Slave function is internally reset. - 0x1 + 1 1 read-write @@ -22660,7 +22791,7 @@ MONEN Monitor Enable. When disabled, configurations settings for the Monitor function are not changed, but the Monitor function is internally reset. - 0x2 + 2 1 read-write @@ -22679,7 +22810,7 @@ TIMEOUTEN I2C bus Time-out Enable. When disabled, the time-out function is internally reset. - 0x3 + 3 1 read-write @@ -22698,7 +22829,7 @@ MONCLKSTR Monitor function Clock Stretching. - 0x4 + 4 1 read-write @@ -22717,7 +22848,7 @@ HSCAPABLE High-speed mode Capable enable. Since High Speed mode alters the way I2C pins drive and filter, as well as the timing for certain I2C signalling, enabling High-speed mode applies to all functions: Master, Slave, and Monitor. - 0x5 + 5 1 read-write @@ -22766,7 +22897,7 @@ MSTSTATE Master State code. The master state code reflects the master state when the MSTPENDING bit is set, that is the master is pending or in the idle state. Each value of this field indicates a specific required service for the Master function. All other values are reserved. See Table 400 for details of state values and appropriate responses. - 0x1 + 1 3 read-only @@ -22800,7 +22931,7 @@ MSTARBLOSS Master Arbitration Loss flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE. - 0x4 + 4 1 read-write @@ -22819,7 +22950,7 @@ MSTSTSTPERR Master Start/Stop Error flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE. - 0x6 + 6 1 read-write @@ -22838,7 +22969,7 @@ SLVPENDING Slave Pending. Indicates that the Slave function is waiting to continue communication on the I2C-bus and needs software service. This flag will cause an interrupt when set if enabled via INTENSET. The SLVPENDING flag is not set when the DMA is handling an event (if the SLVDMA bit in the SLVCTL register is set). The SLVPENDING flag is read-only and is automatically cleared when a 1 is written to the SLVCONTINUE bit in the SLVCTL register. The point in time when SlvPending is set depends on whether the I2C interface is in HSCAPABLE mode. See Section 25.7.2.2.2. When the I2C interface is configured to be HSCAPABLE, HS master codes are detected automatically. Due to the requirements of the HS I2C specification, slave addresses must also be detected automatically, since the address must be acknowledged before the clock can be stretched. - 0x8 + 8 1 read-only @@ -22857,7 +22988,7 @@ SLVSTATE Slave State code. Each value of this field indicates a specific required service for the Slave function. All other values are reserved. See Table 401 for state values and actions. note that the occurrence of some states and how they are handled are affected by DMA mode and Automatic Operation modes. - 0x9 + 9 2 read-only @@ -22881,7 +23012,7 @@ SLVNOTSTR Slave Not Stretching. Indicates when the slave function is stretching the I2C clock. This is needed in order to gracefully invoke Deep Sleep or Power-down modes during slave operation. This read-only flag reflects the slave function status in real time. - 0xB + 11 1 read-only @@ -22900,7 +23031,7 @@ SLVIDX Slave address match Index. This field is valid when the I2C slave function has been selected by receiving an address that matches one of the slave addresses defined by any enabled slave address registers, and provides an identification of the address that was matched. It is possible that more than one address could be matched, but only one match can be reported here. - 0xC + 12 2 read-only @@ -22929,7 +23060,7 @@ SLVSEL Slave selected flag. SLVSEL is set after an address match when software tells the Slave function to acknowledge the address, or when the address has been automatically acknowledged. It is cleared when another address cycle presents an address that does not match an enabled address on the Slave function, when slave software decides to NACK a matched address, when there is a Stop detected on the bus, when the master NACKs slave data, and in some combinations of Automatic Operation. SLVSEL is not cleared if software NACKs data. - 0xE + 14 1 read-only @@ -22948,7 +23079,7 @@ SLVDESEL Slave Deselected flag. This flag will cause an interrupt when set if enabled via INTENSET. This flag can be cleared by writing a 1 to this bit. - 0xF + 15 1 read-write @@ -22967,7 +23098,7 @@ MONRDY Monitor Ready. This flag is cleared when the MONRXDAT register is read. - 0x10 + 16 1 read-only @@ -22986,7 +23117,7 @@ MONOV Monitor Overflow flag. - 0x11 + 17 1 read-write @@ -23005,7 +23136,7 @@ MONACTIVE Monitor Active flag. Indicates when the Monitor function considers the I 2C bus to be active. Active is defined here as when some Master is on the bus: a bus Start has occurred more recently than a bus Stop. - 0x12 + 18 1 read-only @@ -23024,7 +23155,7 @@ MONIDLE Monitor Idle flag. This flag is set when the Monitor function sees the I2C bus change from active to inactive. This can be used by software to decide when to process data accumulated by the Monitor function. This flag will cause an interrupt when set if enabled via the INTENSET register. The flag can be cleared by writing a 1 to this bit. - 0x13 + 19 1 read-write @@ -23043,7 +23174,7 @@ EVENTTIMEOUT Event Time-out Interrupt flag. Indicates when the time between events has been longer than the time specified by the TIMEOUT register. Events include Start, Stop, and clock edges. The flag is cleared by writing a 1 to this bit. No time-out is created when the I2C-bus is idle. - 0x18 + 24 1 read-write @@ -23062,7 +23193,7 @@ SCLTIMEOUT SCL Time-out Interrupt flag. Indicates when SCL has remained low longer than the time specific by the TIMEOUT register. The flag is cleared by writing a 1 to this bit. - 0x19 + 25 1 read-write @@ -23111,7 +23242,7 @@ MSTARBLOSSEN Master Arbitration Loss interrupt Enable. - 0x4 + 4 1 read-write @@ -23130,7 +23261,7 @@ MSTSTSTPERREN Master Start/Stop Error interrupt Enable. - 0x6 + 6 1 read-write @@ -23149,7 +23280,7 @@ SLVPENDINGEN Slave Pending interrupt Enable. - 0x8 + 8 1 read-write @@ -23168,7 +23299,7 @@ SLVNOTSTREN Slave Not Stretching interrupt Enable. - 0xB + 11 1 read-write @@ -23187,7 +23318,7 @@ SLVDESELEN Slave Deselect interrupt Enable. - 0xF + 15 1 read-write @@ -23206,7 +23337,7 @@ MONRDYEN Monitor data Ready interrupt Enable. - 0x10 + 16 1 read-write @@ -23225,7 +23356,7 @@ MONOVEN Monitor Overrun interrupt Enable. - 0x11 + 17 1 read-write @@ -23244,7 +23375,7 @@ MONIDLEEN Monitor Idle interrupt Enable. - 0x13 + 19 1 read-write @@ -23263,7 +23394,7 @@ EVENTTIMEOUTEN Event time-out interrupt Enable. - 0x18 + 24 1 read-write @@ -23282,7 +23413,7 @@ SCLTIMEOUTEN SCL time-out interrupt Enable. - 0x19 + 25 1 read-write @@ -23319,70 +23450,70 @@ MSTARBLOSSCLR Master Arbitration Loss interrupt clear. - 0x4 + 4 1 write-only MSTSTSTPERRCLR Master Start/Stop Error interrupt clear. - 0x6 + 6 1 write-only SLVPENDINGCLR Slave Pending interrupt clear. - 0x8 + 8 1 write-only SLVNOTSTRCLR Slave Not Stretching interrupt clear. - 0xB + 11 1 write-only SLVDESELCLR Slave Deselect interrupt clear. - 0xF + 15 1 write-only MONRDYCLR Monitor data Ready interrupt clear. - 0x10 + 16 1 write-only MONOVCLR Monitor Overrun interrupt clear. - 0x11 + 17 1 write-only MONIDLECLR Monitor Idle interrupt clear. - 0x13 + 19 1 write-only EVENTTIMEOUTCLR Event time-out interrupt clear. - 0x18 + 24 1 write-only SCLTIMEOUTCLR SCL time-out interrupt clear. - 0x19 + 25 1 write-only @@ -23407,7 +23538,7 @@ TO Time-out time value. Specifies the time-out interval value in increments of 16 I 2C function clocks, as defined by the CLKDIV register. To change this value while I2C is in operation, disable all time-outs, write a new value to TIMEOUT, then re-enable time-outs. 0x000 = A time-out will occur after 16 counts of the I2C function clock. 0x001 = A time-out will occur after 32 counts of the I2C function clock. 0xFFF = A time-out will occur after 65,536 counts of the I2C function clock. - 0x4 + 4 12 read-write @@ -23450,70 +23581,70 @@ MSTARBLOSS Master Arbitration Loss flag. - 0x4 + 4 1 read-only MSTSTSTPERR Master Start/Stop Error flag. - 0x6 + 6 1 read-only SLVPENDING Slave Pending. - 0x8 + 8 1 read-only SLVNOTSTR Slave Not Stretching status. - 0xB + 11 1 read-only SLVDESEL Slave Deselected flag. - 0xF + 15 1 read-only MONRDY Monitor Ready. - 0x10 + 16 1 read-only MONOV Monitor Overflow flag. - 0x11 + 17 1 read-only MONIDLE Monitor Idle flag. - 0x13 + 19 1 read-only EVENTTIMEOUT Event time-out Interrupt flag. - 0x18 + 24 1 read-only SCLTIMEOUT SCL time-out Interrupt flag. - 0x19 + 25 1 read-only @@ -23550,7 +23681,7 @@ MSTSTART Master Start control. This bit is write-only. - 0x1 + 1 1 read-write @@ -23569,7 +23700,7 @@ MSTSTOP Master Stop control. This bit is write-only. - 0x2 + 2 1 read-write @@ -23588,7 +23719,7 @@ MSTDMA Master DMA enable. Data operations of the I2C can be performed with DMA. Protocol type operations such as Start, address, Stop, and address match must always be done with software, typically via an interrupt. Address acknowledgement must also be done by software except when the I2C is configured to be HSCAPABLE (and address acknowledgement is handled entirely by hardware) or when Automatic Operation is enabled. When a DMA data transfer is complete, MSTDMA must be cleared prior to beginning the next operation, typically a Start or Stop.This bit is read/write. - 0x3 + 3 1 read-write @@ -23667,7 +23798,7 @@ MSTSCLHIGH Master SCL High time. Specifies the minimum high time that will be asserted by this master on SCL. Other masters in a multi-master system could shorten this time. This corresponds to the parameter tHIGH in the I2C bus specification. I2C bus specification parameters tSU;STO and tHD;STA have the same values and are also controlled by MSTSCLHIGH. - 0x4 + 4 3 read-write @@ -23764,7 +23895,7 @@ SLVNACK Slave NACK. - 0x1 + 1 1 read-write @@ -23783,7 +23914,7 @@ SLVDMA Slave DMA enable. - 0x3 + 3 1 read-write @@ -23802,7 +23933,7 @@ AUTOACK Automatic Acknowledge.When this bit is set, it will cause an I2C header which matches SLVADR0 and the direction set by AUTOMATCHREAD to be ACKed immediately; this is used with DMA to allow processing of the data without intervention. If this bit is clear and a header matches SLVADR0, the behavior is controlled by AUTONACK in the SLVADR0 register: allowing NACK or interrupt. - 0x8 + 8 1 read-write @@ -23821,7 +23952,7 @@ AUTOMATCHREAD When AUTOACK is set, this bit controls whether it matches a read or write request on the next header with an address matching SLVADR0. Since DMA needs to be configured to match the transfer direction, the direction needs to be specified. This bit allows a direction to be chosen for the next operation. - 0x9 + 9 1 read-write @@ -23890,14 +24021,14 @@ SLVADR Slave Address. Seven bit slave address that is compared to received addresses if enabled. - 0x1 + 1 7 read-write AUTONACK Automatic NACK operation. Used in conjunction with AUTOACK and AUTOMATCHREAD, allows software to ignore I2C traffic while handling previous I2C data or other operations. - 0xF + 15 1 read-write @@ -23946,7 +24077,7 @@ SLVQUAL0 Slave address Qualifier for address 0. A value of 0 causes the address in SLVADR0 to be used as-is, assuming that it is enabled. If QUALMODE0 = 0, any bit in this field which is set to 1 will cause an automatic match of the corresponding bit of the received address when it is compared to the SLVADR0 register. If QUALMODE0 = 1, an address range is matched for address 0. This range extends from the value defined by SLVADR0 to the address defined by SLVQUAL0 (address matches when SLVADR0[7:1] <= received address <= SLVQUAL0[7:1]). - 0x1 + 1 7 read-write @@ -23971,7 +24102,7 @@ MONSTART Monitor Received Start. - 0x8 + 8 1 read-only @@ -23990,7 +24121,7 @@ MONRESTART Monitor Received Repeated Start. - 0x9 + 9 1 read-only @@ -24009,7 +24140,7 @@ MONNACK Monitor Received NACK. - 0xA + 10 1 read-only @@ -24029,13 +24160,125 @@ + + I2C1 + LPC5411x I2C-bus interfaces + FLEXCOMM1 + I2C + 0x40087000 + + 0 + 0x884 + registers + + + FLEXCOMM1 + 15 + + + + I2C2 + LPC5411x I2C-bus interfaces + FLEXCOMM2 + I2C + 0x40088000 + + 0 + 0x884 + registers + + + FLEXCOMM2 + 16 + + + + I2C3 + LPC5411x I2C-bus interfaces + FLEXCOMM3 + I2C + 0x40089000 + + 0 + 0x884 + registers + + + FLEXCOMM3 + 17 + + + + I2C4 + LPC5411x I2C-bus interfaces + FLEXCOMM4 + I2C + 0x4008A000 + + 0 + 0x884 + registers + + + FLEXCOMM4 + 18 + + + + I2C5 + LPC5411x I2C-bus interfaces + FLEXCOMM5 + I2C + 0x40096000 + + 0 + 0x884 + registers + + + FLEXCOMM5 + 19 + + + + I2C6 + LPC5411x I2C-bus interfaces + FLEXCOMM6 + I2C + 0x40097000 + + 0 + 0x884 + registers + + + FLEXCOMM6 + 20 + + + + I2C7 + LPC5411x I2C-bus interfaces + FLEXCOMM7 + I2C + 0x40098000 + + 0 + 0x884 + registers + + + FLEXCOMM7 + 21 + + SPI0 - FLEXCOMM0 LPC5411x Serial Peripheral Interfaces (SPI) + FLEXCOMM0 SPI - 0x40086000 SPI + 0x40086000 0 0xE44 @@ -24077,7 +24320,7 @@ MASTER Master mode select. - 0x2 + 2 1 read-write @@ -24096,7 +24339,7 @@ LSBF LSB First mode enable. - 0x3 + 3 1 read-write @@ -24115,7 +24358,7 @@ CPHA Clock Phase select. - 0x4 + 4 1 read-write @@ -24134,7 +24377,7 @@ CPOL Clock Polarity select. - 0x5 + 5 1 read-write @@ -24153,7 +24396,7 @@ LOOP Loopback mode enable. Loopback mode applies only to Master mode, and connects transmit and receive data connected together to allow simple software testing. - 0x7 + 7 1 read-write @@ -24172,7 +24415,7 @@ SPOL0 SSEL0 Polarity select. - 0x8 + 8 1 read-write @@ -24191,7 +24434,7 @@ SPOL1 SSEL1 Polarity select. - 0x9 + 9 1 read-write @@ -24210,7 +24453,7 @@ SPOL2 SSEL2 Polarity select. - 0xA + 10 1 read-write @@ -24229,7 +24472,7 @@ SPOL3 SSEL3 Polarity select. - 0xB + 11 1 read-write @@ -24266,21 +24509,21 @@ POST_DELAY Controls the amount of time between the end of a data transfer and SSEL deassertion. 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are inserted. - 0x4 + 4 4 read-write FRAME_DELAY If the EOF flag is set, controls the minimum amount of time between the current frame and the next frame (or SSEL deassertion if EOT). 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are inserted. - 0x8 + 8 4 read-write TRANSFER_DELAY Controls the minimum amount of time that the SSEL is deasserted between transfers. 0x0 = The minimum time that SSEL is deasserted is 1 SPI clock time. (Zero added time.) 0x1 = The minimum time that SSEL is deasserted is 2 SPI clock times. 0x2 = The minimum time that SSEL is deasserted is 3 SPI clock times. 0xF = The minimum time that SSEL is deasserted is 16 SPI clock times. - 0xC + 12 4 read-write @@ -24298,35 +24541,35 @@ SSA Slave Select Assert. This flag is set whenever any slave select transitions from deasserted to asserted, in both master and slave modes. This allows determining when the SPI transmit/receive functions become busy, and allows waking up the device from reduced power modes when a slave mode access begins. This flag is cleared by software. - 0x4 + 4 1 write-only SSD Slave Select Deassert. This flag is set whenever any asserted slave selects transition to deasserted, in both master and slave modes. This allows determining when the SPI transmit/receive functions become idle. This flag is cleared by software. - 0x5 + 5 1 write-only STALLED Stalled status flag. This indicates whether the SPI is currently in a stall condition. - 0x6 + 6 1 read-only ENDTRANSFER End Transfer control bit. Software can set this bit to force an end to the current transfer when the transmitter finishes any activity already in progress, as if the EOT flag had been set prior to the last transmission. This capability is included to support cases where it is not known when transmit data is written that it will be the end of a transfer. The bit is cleared when the transmitter becomes idle as the transfer comes to an end. Forcing an end of transfer in this manner causes any specified FRAME_DELAY and TRANSFER_DELAY to be inserted. - 0x7 + 7 1 read-write MSTIDLE Master idle status flag. This bit is 1 whenever the SPI master function is fully idle. This means that the transmit holding register is empty and the transmitter is not in the process of sending data. - 0x8 + 8 1 read-only @@ -24344,7 +24587,7 @@ SSAEN Slave select assert interrupt enable. Determines whether an interrupt occurs when the Slave Select is asserted. - 0x4 + 4 1 read-write @@ -24363,7 +24606,7 @@ SSDEN Slave select deassert interrupt enable. Determines whether an interrupt occurs when the Slave Select is deasserted. - 0x5 + 5 1 read-write @@ -24382,7 +24625,7 @@ MSTIDLEEN Master idle interrupt enable. - 0x8 + 8 1 read-write @@ -24412,21 +24655,21 @@ SSAEN Writing 1 clears the corresponding bit in the INTENSET register. - 0x4 + 4 1 write-only SSDEN Writing 1 clears the corresponding bit in the INTENSET register. - 0x5 + 5 1 write-only MSTIDLE Writing 1 clears the corresponding bit in the INTENSET register. - 0x8 + 8 1 write-only @@ -24462,21 +24705,21 @@ SSA Slave Select Assert. - 0x4 + 4 1 read-only SSD Slave Select Deassert. - 0x5 + 5 1 read-only MSTIDLE Master Idle status flag. - 0x8 + 8 1 read-only @@ -24513,7 +24756,7 @@ ENABLERX Enable the receive FIFO. - 0x1 + 1 1 read-write @@ -24532,14 +24775,14 @@ SIZE FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1, 0x2, 0x3 = not applicable to USART. - 0x4 + 4 2 read-only DMATX DMA configuration for transmit. - 0xC + 12 1 read-write @@ -24558,7 +24801,7 @@ DMARX DMA configuration for receive. - 0xD + 13 1 read-write @@ -24577,7 +24820,7 @@ WAKETX Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down, as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware Wake-up control register. - 0xE + 14 1 read-write @@ -24596,7 +24839,7 @@ WAKERX Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down, as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware Wake-up control register. - 0xF + 15 1 read-write @@ -24615,14 +24858,14 @@ EMPTYTX Empty command for the transmit FIFO. When a 1 is written to this bit, the TX FIFO is emptied. - 0x10 + 16 1 read-write EMPTYRX Empty command for the receive FIFO. When a 1 is written to this bit, the RX FIFO is emptied. - 0x11 + 17 1 read-write @@ -24647,56 +24890,56 @@ RXERR RX FIFO error. Will be set if a receive FIFO overflow occurs, caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit. - 0x1 + 1 1 read-write PERINT Peripheral interrupt. When 1, this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register. - 0x3 + 3 1 read-only TXEMPTY Transmit FIFO empty. When 1, the transmit FIFO is empty. The peripheral may still be processing the last piece of data. - 0x4 + 4 1 read-only TXNOTFULL Transmit FIFO not full. When 1, the transmit FIFO is not full, so more data can be written. When 0, the transmit FIFO is full and another write would cause it to overflow. - 0x5 + 5 1 read-only RXNOTEMPTY Receive FIFO not empty. When 1, the receive FIFO is not empty, so data can be read. When 0, the receive FIFO is empty. - 0x6 + 6 1 read-only RXFULL Receive FIFO full. When 1, the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow. - 0x7 + 7 1 read-only TXLVL Transmit FIFO current level. A 0 means the TX FIFO is currently empty, and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full, the TXEMPTY and TXNOTFULL flags will be 0. - 0x8 + 8 5 read-only RXLVL Receive FIFO current level. A 0 means the RX FIFO is currently empty, and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full, the RXFULL and RXNOTEMPTY flags will be 1. - 0x10 + 16 5 read-only @@ -24733,7 +24976,7 @@ RXLVLENA Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET, or a DMA trigger if DMARX in FIFOCFG is set. - 0x1 + 1 1 read-write @@ -24752,14 +24995,14 @@ TXLVL Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so, the FIFO level can wake up the device just enough to perform DMA, then return to the reduced power mode. See Hardware Wake-up control register. 0 = trigger when the TX FIFO becomes empty. 1 = trigger when the TX FIFO level decreases to one entry. 15 = trigger when the TX FIFO level decreases to 15 entries (is no longer full). - 0x8 + 8 4 read-write RXLVL Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so, the FIFO level can wake up the device just enough to perform DMA, then return to the reduced power mode. See Hardware Wake-up control register. 0 = trigger when the RX FIFO has received one entry (is no longer empty). 1 = trigger when the RX FIFO has received two entries. 15 = trigger when the RX FIFO has received 16 entries (has become full). - 0x10 + 16 4 read-write @@ -24796,7 +25039,7 @@ RXERR Determines whether an interrupt occurs when a receive error occurs, based on the RXERR flag in the FIFOSTAT register. - 0x1 + 1 1 read-write @@ -24815,7 +25058,7 @@ TXLVL Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register. - 0x2 + 2 1 read-write @@ -24834,7 +25077,7 @@ RXLVL Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register. - 0x3 + 3 1 read-write @@ -24871,21 +25114,21 @@ RXERR Writing one clears the corresponding bits in the FIFOINTENSET register. - 0x1 + 1 1 read-write TXLVL Writing one clears the corresponding bits in the FIFOINTENSET register. - 0x2 + 2 1 read-write RXLVL Writing one clears the corresponding bits in the FIFOINTENSET register. - 0x3 + 3 1 read-write @@ -24910,28 +25153,28 @@ RXERR RX FIFO error. - 0x1 + 1 1 read-only TXLVL Transmit FIFO level interrupt. - 0x2 + 2 1 read-only RXLVL Receive FIFO level interrupt. - 0x3 + 3 1 read-only PERINT Peripheral interrupt. - 0x4 + 4 1 read-only @@ -24956,7 +25199,7 @@ TXSSEL0_N Transmit slave select. This field asserts SSEL0 in master mode. The output on the pin is active LOW by default. - 0x10 + 16 1 write-only @@ -24975,7 +25218,7 @@ TXSSEL1_N Transmit slave select. This field asserts SSEL1 in master mode. The output on the pin is active LOW by default. - 0x11 + 17 1 write-only @@ -24994,7 +25237,7 @@ TXSSEL2_N Transmit slave select. This field asserts SSEL2 in master mode. The output on the pin is active LOW by default. - 0x12 + 18 1 write-only @@ -25013,7 +25256,7 @@ TXSSEL3_N Transmit slave select. This field asserts SSEL3 in master mode. The output on the pin is active LOW by default. - 0x13 + 19 1 write-only @@ -25032,7 +25275,7 @@ EOT End of transfer. The asserted SSEL will be deasserted at the end of a transfer and remain so far at least the time specified by the Transfer_delay value in the DLY register. - 0x14 + 20 1 write-only @@ -25051,7 +25294,7 @@ EOF End of frame. Between frames, a delay may be inserted, as defined by the Frame_delay value in the DLY register. The end of a frame may not be particularly meaningful if the Frame_delay value = 0. This control can be used as part of the support for frame lengths greater than 16 bits. - 0x15 + 21 1 write-only @@ -25070,7 +25313,7 @@ RXIGNORE Receive Ignore. This allows data to be transmitted using the SPI without the need to read unneeded data from the receiver. Setting this bit simplifies the transmit process and can be used with the DMA. - 0x16 + 22 1 write-only @@ -25089,7 +25332,7 @@ LEN Data Length. Specifies the data length from 4 to 16 bits. Note that transfer lengths greater than 16 bits are supported by implementing multiple sequential transmits. 0x0-2 = Reserved. 0x3 = Data transfer is 4 bits in length. 0x4 = Data transfer is 5 bits in length. 0xF = Data transfer is 16 bits in length. - 0x18 + 24 4 write-only @@ -25114,35 +25357,35 @@ RXSSEL0_N Slave Select for receive. This field allows the state of the SSEL0 pin to be saved along with received data. The value will reflect the SSEL0 pin for both master and slave operation. A zero indicates that a slave select is active. The actual polarity of each slave select pin is configured by the related SPOL bit in CFG. - 0x10 + 16 1 read-only RXSSEL1_N Slave Select for receive. This field allows the state of the SSEL1 pin to be saved along with received data. The value will reflect the SSEL1 pin for both master and slave operation. A zero indicates that a slave select is active. The actual polarity of each slave select pin is configured by the related SPOL bit in CFG. - 0x11 + 17 1 read-only RXSSEL2_N Slave Select for receive. This field allows the state of the SSEL2 pin to be saved along with received data. The value will reflect the SSEL2 pin for both master and slave operation. A zero indicates that a slave select is active. The actual polarity of each slave select pin is configured by the related SPOL bit in CFG. - 0x12 + 18 1 read-only RXSSEL3_N Slave Select for receive. This field allows the state of the SSEL3 pin to be saved along with received data. The value will reflect the SSEL3 pin for both master and slave operation. A zero indicates that a slave select is active. The actual polarity of each slave select pin is configured by the related SPOL bit in CFG. - 0x13 + 19 1 read-only SOT Start of Transfer flag. This flag will be 1 if this is the first data after the SSELs went from deasserted to asserted (i.e., any previous transfer has ended). This information can be used to identify the first piece of data in cases where the transfer length is greater than 16 bits. - 0x14 + 20 1 read-only @@ -25167,35 +25410,35 @@ RXSSEL0_N Slave Select for receive. - 0x10 + 16 1 read-only RXSSEL1_N Slave Select for receive. - 0x11 + 17 1 read-only RXSSEL2_N Slave Select for receive. - 0x12 + 18 1 read-only RXSSEL3_N Slave Select for receive. - 0x13 + 19 1 read-only SOT Start of transfer flag. - 0x14 + 20 1 read-only @@ -25203,13 +25446,125 @@ + + SPI1 + LPC5411x Serial Peripheral Interfaces (SPI) + FLEXCOMM1 + SPI + 0x40087000 + + 0 + 0xE44 + registers + + + FLEXCOMM1 + 15 + + + + SPI2 + LPC5411x Serial Peripheral Interfaces (SPI) + FLEXCOMM2 + SPI + 0x40088000 + + 0 + 0xE44 + registers + + + FLEXCOMM2 + 16 + + + + SPI3 + LPC5411x Serial Peripheral Interfaces (SPI) + FLEXCOMM3 + SPI + 0x40089000 + + 0 + 0xE44 + registers + + + FLEXCOMM3 + 17 + + + + SPI4 + LPC5411x Serial Peripheral Interfaces (SPI) + FLEXCOMM4 + SPI + 0x4008A000 + + 0 + 0xE44 + registers + + + FLEXCOMM4 + 18 + + + + SPI5 + LPC5411x Serial Peripheral Interfaces (SPI) + FLEXCOMM5 + SPI + 0x40096000 + + 0 + 0xE44 + registers + + + FLEXCOMM5 + 19 + + + + SPI6 + LPC5411x Serial Peripheral Interfaces (SPI) + FLEXCOMM6 + SPI + 0x40097000 + + 0 + 0xE44 + registers + + + FLEXCOMM6 + 20 + + + + SPI7 + LPC5411x Serial Peripheral Interfaces (SPI) + FLEXCOMM7 + SPI + 0x40098000 + + 0 + 0xE44 + registers + + + FLEXCOMM7 + 21 + + USART0 - FLEXCOMM0 LPC5411x USARTs + FLEXCOMM0 USART - 0x40086000 USART + 0x40086000 0 0xE44 @@ -25251,7 +25606,7 @@ DATALEN Selects the data size for the USART. - 0x2 + 2 2 read-write @@ -25275,7 +25630,7 @@ PARITYSEL Selects what type of parity is used by the USART. - 0x4 + 4 2 read-write @@ -25299,7 +25654,7 @@ STOPLEN Number of stop bits appended to transmitted data. Only a single stop bit is required for received data. - 0x6 + 6 1 read-write @@ -25318,7 +25673,7 @@ MODE32K Selects standard or 32 kHz clocking mode. - 0x7 + 7 1 read-write @@ -25337,7 +25692,7 @@ LINMODE LIN break mode enable. - 0x8 + 8 1 read-write @@ -25356,7 +25711,7 @@ CTSEN CTS Enable. Determines whether CTS is used for flow control. CTS can be from the input pin, or from the USART's own RTS if loopback mode is enabled. - 0x9 + 9 1 read-write @@ -25375,7 +25730,7 @@ SYNCEN Selects synchronous or asynchronous operation. - 0xB + 11 1 read-write @@ -25394,7 +25749,7 @@ CLKPOL Selects the clock polarity and sampling edge of received data in synchronous mode. - 0xC + 12 1 read-write @@ -25413,7 +25768,7 @@ SYNCMST Synchronous mode Master select. - 0xE + 14 1 read-write @@ -25432,7 +25787,7 @@ LOOP Selects data loopback mode. - 0xF + 15 1 read-write @@ -25451,7 +25806,7 @@ IOMODE I/O output mode. - 0x10 + 16 1 read-write @@ -25470,7 +25825,7 @@ OETA Output Enable Turnaround time enable for RS-485 operation. - 0x12 + 18 1 read-write @@ -25489,7 +25844,7 @@ AUTOADDR Automatic Address matching enable. - 0x13 + 19 1 read-write @@ -25508,7 +25863,7 @@ OESEL Output Enable Select. - 0x14 + 20 1 read-write @@ -25527,7 +25882,7 @@ OEPOL Output Enable Polarity. - 0x15 + 21 1 read-write @@ -25546,7 +25901,7 @@ RXPOL Receive data polarity. - 0x16 + 22 1 read-write @@ -25565,7 +25920,7 @@ TXPOL Transmit data polarity. - 0x17 + 23 1 read-write @@ -25595,7 +25950,7 @@ TXBRKEN Break Enable. - 0x1 + 1 1 read-write @@ -25614,7 +25969,7 @@ ADDRDET Enable address detect mode. - 0x2 + 2 1 read-write @@ -25633,7 +25988,7 @@ TXDIS Transmit Disable. - 0x6 + 6 1 read-write @@ -25652,7 +26007,7 @@ CC Continuous Clock generation. By default, SCLK is only output while data is being transmitted in synchronous mode. - 0x8 + 8 1 read-write @@ -25671,7 +26026,7 @@ CLRCCONRX Clear Continuous Clock. - 0x9 + 9 1 read-write @@ -25690,7 +26045,7 @@ AUTOBAUD Autobaud enable. - 0x10 + 16 1 read-write @@ -25720,84 +26075,84 @@ RXIDLE Receiver Idle. When 0, indicates that the receiver is currently in the process of receiving data. When 1, indicates that the receiver is not currently in the process of receiving data. - 0x1 + 1 1 read-only TXIDLE Transmitter Idle. When 0, indicates that the transmitter is currently in the process of sending data.When 1, indicate that the transmitter is not currently in the process of sending data. - 0x3 + 3 1 read-only CTS This bit reflects the current state of the CTS signal, regardless of the setting of the CTSEN bit in the CFG register. This will be the value of the CTS input pin unless loopback mode is enabled. - 0x4 + 4 1 read-only DELTACTS This bit is set when a change in the state is detected for the CTS flag above. This bit is cleared by software. - 0x5 + 5 1 write-only TXDISSTAT Transmitter Disabled Status flag. When 1, this bit indicates that the USART transmitter is fully idle after being disabled via the TXDIS bit in the CFG register (TXDIS = 1). - 0x6 + 6 1 read-only RXBRK Received Break. This bit reflects the current state of the receiver break detection logic. It is set when the Un_RXD pin remains low for 16 bit times. Note that FRAMERRINT will also be set when this condition occurs because the stop bit(s) for the character would be missing. RXBRK is cleared when the Un_RXD pin goes high. - 0xA + 10 1 read-only DELTARXBRK This bit is set when a change in the state of receiver break detection occurs. Cleared by software. - 0xB + 11 1 write-only START This bit is set when a start is detected on the receiver input. Its purpose is primarily to allow wake-up from Deep-sleep or Power-down mode immediately when a start is detected. Cleared by software. - 0xC + 12 1 write-only FRAMERRINT Framing Error interrupt flag. This flag is set when a character is received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source. - 0xD + 13 1 write-only PARITYERRINT Parity Error interrupt flag. This flag is set when a parity error is detected in a received character. - 0xE + 14 1 write-only RXNOISEINT Received Noise interrupt flag. Three samples of received data are taken in order to determine the value of each received data bit, except in synchronous mode. This acts as a noise filter if one sample disagrees. This flag is set when a received data bit contains one disagreeing sample. This could indicate line noise, a baud rate or character format mismatch, or loss of synchronization during data reception. - 0xF + 15 1 write-only ABERR Auto baud Error. An auto baud error can occur if the BRG counts to its limit before the end of the start bit that is being measured, essentially an auto baud time-out. - 0x10 + 16 1 write-only @@ -25815,63 +26170,63 @@ TXIDLEEN When 1, enables an interrupt when the transmitter becomes idle (TXIDLE = 1). - 0x3 + 3 1 read-write DELTACTSEN When 1, enables an interrupt when there is a change in the state of the CTS input. - 0x5 + 5 1 read-write TXDISEN When 1, enables an interrupt when the transmitter is fully disabled as indicated by the TXDISINT flag in STAT. See description of the TXDISINT bit for details. - 0x6 + 6 1 read-write DELTARXBRKEN When 1, enables an interrupt when a change of state has occurred in the detection of a received break condition (break condition asserted or deasserted). - 0xB + 11 1 read-write STARTEN When 1, enables an interrupt when a received start bit has been detected. - 0xC + 12 1 read-write FRAMERREN When 1, enables an interrupt when a framing error has been detected. - 0xD + 13 1 read-write PARITYERREN When 1, enables an interrupt when a parity error has been detected. - 0xE + 14 1 read-write RXNOISEEN When 1, enables an interrupt when noise is detected. See description of the RXNOISEINT bit in Table 354. - 0xF + 15 1 read-write ABERREN When 1, enables an interrupt when an auto baud error occurs. - 0x10 + 16 1 read-write @@ -25889,63 +26244,63 @@ TXIDLECLR Writing 1 clears the corresponding bit in the INTENSET register. - 0x3 + 3 1 write-only DELTACTSCLR Writing 1 clears the corresponding bit in the INTENSET register. - 0x5 + 5 1 write-only TXDISCLR Writing 1 clears the corresponding bit in the INTENSET register. - 0x6 + 6 1 write-only DELTARXBRKCLR Writing 1 clears the corresponding bit in the INTENSET register. - 0xB + 11 1 write-only STARTCLR Writing 1 clears the corresponding bit in the INTENSET register. - 0xC + 12 1 write-only FRAMERRCLR Writing 1 clears the corresponding bit in the INTENSET register. - 0xD + 13 1 write-only PARITYERRCLR Writing 1 clears the corresponding bit in the INTENSET register. - 0xE + 14 1 write-only RXNOISECLR Writing 1 clears the corresponding bit in the INTENSET register. - 0xF + 15 1 write-only ABERRCLR Writing 1 clears the corresponding bit in the INTENSET register. - 0x10 + 16 1 write-only @@ -25981,63 +26336,63 @@ TXIDLE Transmitter Idle status. - 0x3 + 3 1 read-only DELTACTS This bit is set when a change in the state of the CTS input is detected. - 0x5 + 5 1 read-only TXDISINT Transmitter Disabled Interrupt flag. - 0x6 + 6 1 read-only DELTARXBRK This bit is set when a change in the state of receiver break detection occurs. - 0xB + 11 1 read-only START This bit is set when a start is detected on the receiver input. - 0xC + 12 1 read-only FRAMERRINT Framing Error interrupt flag. - 0xD + 13 1 read-only PARITYERRINT Parity Error interrupt flag. - 0xE + 14 1 read-only RXNOISEINT Received Noise interrupt flag. - 0xF + 15 1 read-only ABERRINT Auto baud Error Interrupt flag. - 0x10 + 16 1 read-only @@ -26110,7 +26465,7 @@ ENABLERX Enable the receive FIFO. - 0x1 + 1 1 read-write @@ -26129,14 +26484,14 @@ SIZE FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1, 0x2, 0x3 = not applicable to USART. - 0x4 + 4 2 read-only DMATX DMA configuration for transmit. - 0xC + 12 1 read-write @@ -26155,7 +26510,7 @@ DMARX DMA configuration for receive. - 0xD + 13 1 read-write @@ -26174,7 +26529,7 @@ WAKETX Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down, as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware Wake-up control register. - 0xE + 14 1 read-write @@ -26193,7 +26548,7 @@ WAKERX Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down, as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware Wake-up control register. - 0xF + 15 1 read-write @@ -26212,14 +26567,14 @@ EMPTYTX Empty command for the transmit FIFO. When a 1 is written to this bit, the TX FIFO is emptied. - 0x10 + 16 1 read-write EMPTYRX Empty command for the receive FIFO. When a 1 is written to this bit, the RX FIFO is emptied. - 0x11 + 17 1 read-write @@ -26244,56 +26599,56 @@ RXERR RX FIFO error. Will be set if a receive FIFO overflow occurs, caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit. - 0x1 + 1 1 read-write PERINT Peripheral interrupt. When 1, this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register. - 0x3 + 3 1 read-only TXEMPTY Transmit FIFO empty. When 1, the transmit FIFO is empty. The peripheral may still be processing the last piece of data. - 0x4 + 4 1 read-only TXNOTFULL Transmit FIFO not full. When 1, the transmit FIFO is not full, so more data can be written. When 0, the transmit FIFO is full and another write would cause it to overflow. - 0x5 + 5 1 read-only RXNOTEMPTY Receive FIFO not empty. When 1, the receive FIFO is not empty, so data can be read. When 0, the receive FIFO is empty. - 0x6 + 6 1 read-only RXFULL Receive FIFO full. When 1, the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow. - 0x7 + 7 1 read-only TXLVL Transmit FIFO current level. A 0 means the TX FIFO is currently empty, and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full, the TXEMPTY and TXNOTFULL flags will be 0. - 0x8 + 8 5 read-only RXLVL Receive FIFO current level. A 0 means the RX FIFO is currently empty, and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full, the RXFULL and RXNOTEMPTY flags will be 1. - 0x10 + 16 5 read-only @@ -26330,7 +26685,7 @@ RXLVLENA Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET, or a DMA trigger if DMARX in FIFOCFG is set. - 0x1 + 1 1 read-write @@ -26349,14 +26704,14 @@ TXLVL Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so, the FIFO level can wake up the device just enough to perform DMA, then return to the reduced power mode. See Hardware Wake-up control register. 0 = trigger when the TX FIFO becomes empty. 1 = trigger when the TX FIFO level decreases to one entry. 15 = trigger when the TX FIFO level decreases to 15 entries (is no longer full). - 0x8 + 8 4 read-write RXLVL Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so, the FIFO level can wake up the device just enough to perform DMA, then return to the reduced power mode. See Hardware Wake-up control register. 0 = trigger when the RX FIFO has received one entry (is no longer empty). 1 = trigger when the RX FIFO has received two entries. 15 = trigger when the RX FIFO has received 16 entries (has become full). - 0x10 + 16 4 read-write @@ -26393,7 +26748,7 @@ RXERR Determines whether an interrupt occurs when a receive error occurs, based on the RXERR flag in the FIFOSTAT register. - 0x1 + 1 1 read-write @@ -26412,7 +26767,7 @@ TXLVL Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register. - 0x2 + 2 1 read-write @@ -26431,7 +26786,7 @@ RXLVL Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register. - 0x3 + 3 1 read-write @@ -26468,21 +26823,21 @@ RXERR Writing one clears the corresponding bits in the FIFOINTENSET register. - 0x1 + 1 1 read-write TXLVL Writing one clears the corresponding bits in the FIFOINTENSET register. - 0x2 + 2 1 read-write RXLVL Writing one clears the corresponding bits in the FIFOINTENSET register. - 0x3 + 3 1 read-write @@ -26507,28 +26862,28 @@ RXERR RX FIFO error. - 0x1 + 1 1 read-only TXLVL Transmit FIFO level interrupt. - 0x2 + 2 1 read-only RXLVL Receive FIFO level interrupt. - 0x3 + 3 1 read-only PERINT Peripheral interrupt. - 0x4 + 4 1 read-only @@ -26571,21 +26926,21 @@ FRAMERR Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO, and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source. - 0xD + 13 1 read-only PARITYERR Parity Error status flag. This bit reflects the status for the data it is read along with from the FIFO. This bit will be set when a parity error is detected in a received character. - 0xE + 14 1 read-only RXNOISE Received Noise flag. See description of the RxNoiseInt bit in Table 354. - 0xF + 15 1 read-only @@ -26610,21 +26965,21 @@ FRAMERR Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO, and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source. - 0xD + 13 1 read-only PARITYERR Parity Error status flag. This bit reflects the status for the data it is read along with from the FIFO. This bit will be set when a parity error is detected in a received character. - 0xE + 14 1 read-only RXNOISE Received Noise flag. See description of the RxNoiseInt bit in Table 354. - 0xF + 15 1 read-only @@ -26632,57 +26987,10 @@ - - FLEXCOMM1 - LPC5411x Flexcomm serial communication - FLEXCOMM - 0x40087000 - - 0 - 0x1000 - registers - - - FLEXCOMM1 - 15 - - - - I2C1 - FLEXCOMM1 - LPC5411x I2C-bus interfaces - I2C - 0x40087000 - - 0 - 0x884 - registers - - - FLEXCOMM1 - 15 - - - - SPI1 - FLEXCOMM1 - LPC5411x Serial Peripheral Interfaces (SPI) - SPI - 0x40087000 - - 0 - 0xE44 - registers - - - FLEXCOMM1 - 15 - - USART1 - FLEXCOMM1 LPC5411x USARTs + FLEXCOMM1 USART 0x40087000 @@ -26695,57 +27003,10 @@ 15 - - FLEXCOMM2 - LPC5411x Flexcomm serial communication - FLEXCOMM - 0x40088000 - - 0 - 0x1000 - registers - - - FLEXCOMM2 - 16 - - - - I2C2 - FLEXCOMM2 - LPC5411x I2C-bus interfaces - I2C - 0x40088000 - - 0 - 0x884 - registers - - - FLEXCOMM2 - 16 - - - - SPI2 - FLEXCOMM2 - LPC5411x Serial Peripheral Interfaces (SPI) - SPI - 0x40088000 - - 0 - 0xE44 - registers - - - FLEXCOMM2 - 16 - - USART2 - FLEXCOMM2 LPC5411x USARTs + FLEXCOMM2 USART 0x40088000 @@ -26758,57 +27019,10 @@ 16 - - FLEXCOMM3 - LPC5411x Flexcomm serial communication - FLEXCOMM - 0x40089000 - - 0 - 0x1000 - registers - - - FLEXCOMM3 - 17 - - - - I2C3 - FLEXCOMM3 - LPC5411x I2C-bus interfaces - I2C - 0x40089000 - - 0 - 0x884 - registers - - - FLEXCOMM3 - 17 - - - - SPI3 - FLEXCOMM3 - LPC5411x Serial Peripheral Interfaces (SPI) - SPI - 0x40089000 - - 0 - 0xE44 - registers - - - FLEXCOMM3 - 17 - - USART3 - FLEXCOMM3 LPC5411x USARTs + FLEXCOMM3 USART 0x40089000 @@ -26821,57 +27035,10 @@ 17 - - FLEXCOMM4 - LPC5411x Flexcomm serial communication - FLEXCOMM - 0x4008A000 - - 0 - 0x1000 - registers - - - FLEXCOMM4 - 18 - - - - I2C4 - FLEXCOMM4 - LPC5411x I2C-bus interfaces - I2C - 0x4008A000 - - 0 - 0x884 - registers - - - FLEXCOMM4 - 18 - - - - SPI4 - FLEXCOMM4 - LPC5411x Serial Peripheral Interfaces (SPI) - SPI - 0x4008A000 - - 0 - 0xE44 - registers - - - FLEXCOMM4 - 18 - - USART4 - FLEXCOMM4 LPC5411x USARTs + FLEXCOMM4 USART 0x4008A000 @@ -26884,6 +27051,54 @@ 18 + + USART5 + LPC5411x USARTs + FLEXCOMM5 + USART + 0x40096000 + + 0 + 0xE44 + registers + + + FLEXCOMM5 + 19 + + + + USART6 + LPC5411x USARTs + FLEXCOMM6 + USART + 0x40097000 + + 0 + 0xE44 + registers + + + FLEXCOMM6 + 20 + + + + USART7 + LPC5411x USARTs + FLEXCOMM7 + USART + 0x40098000 + + 0 + 0xE44 + registers + + + FLEXCOMM7 + 21 + + MAILBOX LPC5411x Mailbox @@ -27379,7 +27594,7 @@ RESETN FIFO reset. - 0x1 + 1 1 read-write @@ -27398,7 +27613,7 @@ INTEN Interrupt enable. - 0x2 + 2 1 read-write @@ -27417,7 +27632,7 @@ DMAEN DMA enable - 0x3 + 3 1 read-write @@ -27436,7 +27651,7 @@ TRIGLVL FIFO trigger level. Selects the data trigger level for interrupt or DMA operation. If enabled to do so, the FIFO level can wake up the device just enough to perform DMA, then return to the reduced power mode See Section 4.5.66 'Hardware Wake-up control register'. 0 = trigger when the FIFO has received one entry (is no longer empty). 1 = trigger when the FIFO has received two entries. 15 = trigger when the FIFO has received 16 entries (has become full). - 0x10 + 16 5 read-write @@ -27461,14 +27676,14 @@ OVERRUN Overrun flag. Indicates that a FIFO overflow has occurred at some point. Writing a one to this bit clears the flag. This flag does not cause an interrupt. - 0x1 + 1 1 read-write UNDERRUN Underrun flag. Indicates that a FIFO underflow has occurred at some point. Writing a one to this bit clears the flag. - 0x2 + 2 1 read-write @@ -27523,7 +27738,7 @@ PHY_HALF Half rate sampling - 0x1 + 1 1 read-write @@ -27582,14 +27797,14 @@ DCGAIN Fine gain adjustment in the form of a number of bits to downshift. - 0x4 + 4 4 read-write SATURATEAT16BIT Selects 16-bit saturation. - 0x8 + 8 1 read-write @@ -27627,7 +27842,7 @@ EN_CH1 Enable channel 1. When 1, PDM channel 1 is enabled. - 0x1 + 1 1 read-write @@ -27652,14 +27867,14 @@ CLK_BYPASS1 Bypass CLK1. When 1, PDM_DATA1 becomes the clock for PDM channel 1. This provides for the possibility of an external codec taking over the PDM bus. - 0x1 + 1 1 read-write STEREO_DATA0 Stereo PDM select. When 1, PDM_DATA0 is routed to both PDM channels in a configuration that supports a single stereo digital microphone. - 0x2 + 2 1 read-write @@ -27900,28 +28115,28 @@ BIT_RVS_WR Data bit order: 1 = Bit order reverse for CRC_WR_DATA (per byte) 0 = No bit order reverse for CRC_WR_DATA (per byte) - 0x2 + 2 1 read-write CMPL_WR Data complement: 1 = 1's complement for CRC_WR_DATA 0 = No 1's complement for CRC_WR_DATA - 0x3 + 3 1 read-write BIT_RVS_SUM CRC sum bit order: 1 = Bit order reverse for CRC_SUM 0 = No bit order reverse for CRC_SUM - 0x4 + 4 1 read-write CMPL_SUM CRC sum complement: 1 = 1's complement for CRC_SUM 0 = No 1's complement for CRC_SUM - 0x5 + 5 1 read-write @@ -27985,107 +28200,13 @@ - - FLEXCOMM5 - LPC5411x Flexcomm serial communication - FLEXCOMM - 0x40096000 - - 0 - 0x1000 - registers - - - FLEXCOMM5 - 19 - - - - I2C5 - FLEXCOMM5 - LPC5411x I2C-bus interfaces - I2C - 0x40096000 - - 0 - 0x884 - registers - - - FLEXCOMM5 - 19 - - - - SPI5 - FLEXCOMM5 - LPC5411x Serial Peripheral Interfaces (SPI) - SPI - 0x40096000 - - 0 - 0xE44 - registers - - - FLEXCOMM5 - 19 - - - - USART5 - FLEXCOMM5 - LPC5411x USARTs - USART - 0x40096000 - - 0 - 0xE44 - registers - - - FLEXCOMM5 - 19 - - - - FLEXCOMM6 - LPC5411x Flexcomm serial communication - FLEXCOMM - 0x40097000 - - 0 - 0x1000 - registers - - - FLEXCOMM6 - 20 - - - - I2C6 - FLEXCOMM6 - LPC5411x I2C-bus interfaces - I2C - 0x40097000 - - 0 - 0x884 - registers - - - FLEXCOMM6 - 20 - - I2S0 - FLEXCOMM6 LPC5411x I2S interface + FLEXCOMM6 I2S - 0x40097000 I2S + 0x40097000 0 0xE48 @@ -28127,7 +28248,7 @@ DATAPAUSE Data flow Pause. Allows pausing data flow between the I2S serializer/deserializer and the FIFO. This could be done in order to change streams, or while restarting after a data underflow or overflow. When paused, FIFO operations can be done without corrupting data that is in the process of being sent or received. Once a data pause has been requested, the interface may need to complete sending data that was in progress before interrupting the flow of data. Software must check that the pause is actually in effect before taking action. This is done by monitoring the DATAPAUSED flag in the STAT register. When DATAPAUSE is cleared, data transfer will resume at the beginning of the next frame. - 0x1 + 1 1 read-write @@ -28146,7 +28267,7 @@ PAIRCOUNT Provides the number of I2S channel pairs in this Flexcomm This is a read-only field whose value may be different in other Flexcomms. 00 = there is 1 I2S channel pair in this Flexcomm. 01 = there are 2 I2S channel pairs in this Flexcomm. 10 = there are 3 I2S channel pairs in this Flexcomm. 11 = there are 4 I2S channel pairs in this Flexcomm. - 0x2 + 2 2 read-write @@ -28175,7 +28296,7 @@ MSTSLVCFG Master / slave configuration selection, determining how SCK and WS are used by all channel pairs in this Flexcomm. - 0x4 + 4 2 read-write @@ -28204,7 +28325,7 @@ MODE Selects the basic I2S operating mode. Other configurations modify this to obtain all supported cases. See Formats and modes for examples. - 0x6 + 6 2 read-write @@ -28233,7 +28354,7 @@ RIGHTLOW Right channel data is in the Low portion of FIFO data. Essentially, this swaps left and right channel data as it is transferred to or from the FIFO. This bit is not used if the data width is greater than 24 bits or if PDMDATA = 1. Note that if the ONECHANNEL field (bit 10 of this register) = 1, the one channel to be used is the nominally the left channel. POSITION can still place that data in the frame where right channel data is normally located. if all enabled channel pairs have ONECHANNEL = 1, then RIGHTLOW = 1 is not allowed. - 0x8 + 8 1 read-write @@ -28252,7 +28373,7 @@ LEFTJUST Left Justify data. - 0x9 + 9 1 read-write @@ -28271,7 +28392,7 @@ ONECHANNEL Single channel mode. Applies to both transmit and receive. This configuration bit applies only to the first I2S channel pair. Other channel pairs may select this mode independently in their separate CFG1 registers. - 0xA + 10 1 read-write @@ -28290,7 +28411,7 @@ PDMDATA PDM Data selection. This bit controls the data source for I2S transmit, and cannot be set in Rx mode. This bit only has an effect if the device the Flexcomm resides in includes a D-Mic subsystem. For the LPC5411x, this bit applies only to Flexcomm 7. - 0xB + 11 1 read-write @@ -28309,7 +28430,7 @@ SCK_POL SCK polarity. - 0xC + 12 1 read-write @@ -28328,7 +28449,7 @@ WS_POL WS polarity. - 0xD + 13 1 read-write @@ -28347,7 +28468,7 @@ DATALEN Data Length, minus 1 encoded, defines the number of data bits to be transmitted or received for all I2S channel pairs in this Flexcomm. Note that data is only driven to or received from SDA for the number of bits defined by DATALEN. DATALEN is also used in these ways by the I2S: Determines the size of data transfers between the FIFO and the I2S serializer/deserializer. See FIFO buffer configurations and usage In mode 1, 2, and 3, determines the location of right data following left data in the frame. In mode 3 (where WS has a one data slot long pulse at the beginning of each data frame) determines the duration of the WS pulse. Values: 0x00 to 0x02 = not supported 0x03 = data is 4 bits in length 0x04 = data is 5 bits in length 0x1F = data is 32 bits in length - 0x10 + 16 5 read-write @@ -28372,7 +28493,7 @@ POSITION Data Position. Defines the location within the frame of the data for this channel pair. POSITION + DATALEN must be less than FRAMELEN. See Frame format. When MODE = 0, POSITION defines the location of data in both the left phase and right phase, starting one clock after the WS edge. In other modes, POSITION defines the location of data within the entire frame. ONECHANNEL = 1 while MODE = 0 is a special case, see the description of ONECHANNEL. The combination of DATALEN and the POSITION fields of all channel pairs must be made such that the channels do not overlap within the frame. 0x000 = data begins at bit position 0 (the first bit position) within the frame or WS phase. 0x001 = data begins at bit position 1 within the frame or WS phase. 0x002 = data begins at bit position 2 within the frame or WS phase. - 0x10 + 16 9 read-write @@ -28409,7 +28530,7 @@ SLVFRMERR Slave Frame Error flag. This applies when at least one channel pair is operating as a slave. An error indicates that the incoming WS signal did not transition as expected due to a mismatch between FRAMELEN and the actual incoming I2S stream. - 0x1 + 1 1 write-only @@ -28428,7 +28549,7 @@ LR Left/Right indication. This flag is considered to be a debugging aid and is not expected to be used by an I2S driver. Valid when one channel pair is busy. Indicates left or right data being processed for the currently busy channel pair. - 0x2 + 2 1 read-only @@ -28447,7 +28568,7 @@ DATAPAUSED Data Paused status flag. Applies to all I2S channels - 0x3 + 3 1 read-only @@ -28514,7 +28635,7 @@ ENABLERX Enable the receive FIFO. - 0x1 + 1 1 read-write @@ -28533,7 +28654,7 @@ TXI2SSE0 Transmit I2S empty 0. Determines the value sent by the I2S in transmit mode if the TX FIFO becomes empty. This value is sent repeatedly until the I2S is paused, the error is cleared, new data is provided, and the I2S is un-paused. - 0x2 + 2 1 read-write @@ -28552,7 +28673,7 @@ PACK48 Packing format for 48-bit data. This relates to how data is entered into or taken from the FIFO by software or DMA. - 0x3 + 3 1 read-write @@ -28571,14 +28692,14 @@ SIZE FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1, 0x2, 0x3 = not applicable to USART. - 0x4 + 4 2 read-only DMATX DMA configuration for transmit. - 0xC + 12 1 read-write @@ -28597,7 +28718,7 @@ DMARX DMA configuration for receive. - 0xD + 13 1 read-write @@ -28616,7 +28737,7 @@ WAKETX Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down, as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware Wake-up control register. - 0xE + 14 1 read-write @@ -28635,7 +28756,7 @@ WAKERX Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down, as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware Wake-up control register. - 0xF + 15 1 read-write @@ -28654,21 +28775,21 @@ EMPTYTX Empty command for the transmit FIFO. When a 1 is written to this bit, the TX FIFO is emptied. - 0x10 + 16 1 read-write EMPTYRX Empty command for the receive FIFO. When a 1 is written to this bit, the RX FIFO is emptied. - 0x11 + 17 1 read-write POPDBG Pop FIFO for debug reads. - 0x12 + 18 1 read-write @@ -28705,56 +28826,56 @@ RXERR RX FIFO error. Will be set if a receive FIFO overflow occurs, caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit. - 0x1 + 1 1 read-write PERINT Peripheral interrupt. When 1, this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register. - 0x3 + 3 1 read-only TXEMPTY Transmit FIFO empty. When 1, the transmit FIFO is empty. The peripheral may still be processing the last piece of data. - 0x4 + 4 1 read-only TXNOTFULL Transmit FIFO not full. When 1, the transmit FIFO is not full, so more data can be written. When 0, the transmit FIFO is full and another write would cause it to overflow. - 0x5 + 5 1 read-only RXNOTEMPTY Receive FIFO not empty. When 1, the receive FIFO is not empty, so data can be read. When 0, the receive FIFO is empty. - 0x6 + 6 1 read-only RXFULL Receive FIFO full. When 1, the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow. - 0x7 + 7 1 read-only TXLVL Transmit FIFO current level. A 0 means the TX FIFO is currently empty, and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full, the TXEMPTY and TXNOTFULL flags will be 0. - 0x8 + 8 5 read-only RXLVL Receive FIFO current level. A 0 means the RX FIFO is currently empty, and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full, the RXFULL and RXNOTEMPTY flags will be 1. - 0x10 + 16 5 read-only @@ -28791,7 +28912,7 @@ RXLVLENA Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET, or a DMA trigger if DMARX in FIFOCFG is set. - 0x1 + 1 1 read-write @@ -28810,14 +28931,14 @@ TXLVL Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so, the FIFO level can wake up the device just enough to perform DMA, then return to the reduced power mode. See Hardware Wake-up control register. 0 = trigger when the TX FIFO becomes empty. 1 = trigger when the TX FIFO level decreases to one entry. 15 = trigger when the TX FIFO level decreases to 15 entries (is no longer full). - 0x8 + 8 4 read-write RXLVL Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so, the FIFO level can wake up the device just enough to perform DMA, then return to the reduced power mode. See Hardware Wake-up control register. 0 = trigger when the RX FIFO has received one entry (is no longer empty). 1 = trigger when the RX FIFO has received two entries. 15 = trigger when the RX FIFO has received 16 entries (has become full). - 0x10 + 16 4 read-write @@ -28854,7 +28975,7 @@ RXERR Determines whether an interrupt occurs when a receive error occurs, based on the RXERR flag in the FIFOSTAT register. - 0x1 + 1 1 read-write @@ -28873,7 +28994,7 @@ TXLVL Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register. - 0x2 + 2 1 read-write @@ -28892,7 +29013,7 @@ RXLVL Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register. - 0x3 + 3 1 read-write @@ -28929,21 +29050,21 @@ RXERR Writing one clears the corresponding bits in the FIFOINTENSET register. - 0x1 + 1 1 read-write TXLVL Writing one clears the corresponding bits in the FIFOINTENSET register. - 0x2 + 2 1 read-write RXLVL Writing one clears the corresponding bits in the FIFOINTENSET register. - 0x3 + 3 1 read-write @@ -28968,28 +29089,28 @@ RXERR RX FIFO error. - 0x1 + 1 1 read-only TXLVL Transmit FIFO level interrupt. - 0x2 + 2 1 read-only RXLVL Receive FIFO level interrupt. - 0x3 + 3 1 read-only PERINT Peripheral interrupt. - 0x4 + 4 1 read-only @@ -29105,73 +29226,10 @@ - - SPI6 - FLEXCOMM6 - LPC5411x Serial Peripheral Interfaces (SPI) - SPI - 0x40097000 - - 0 - 0xE44 - registers - - - FLEXCOMM6 - 20 - - - - USART6 - FLEXCOMM6 - LPC5411x USARTs - USART - 0x40097000 - - 0 - 0xE44 - registers - - - FLEXCOMM6 - 20 - - - - FLEXCOMM7 - LPC5411x Flexcomm serial communication - FLEXCOMM - 0x40098000 - - 0 - 0x1000 - registers - - - FLEXCOMM7 - 21 - - - - I2C7 - FLEXCOMM7 - LPC5411x I2C-bus interfaces - I2C - 0x40098000 - - 0 - 0x884 - registers - - - FLEXCOMM7 - 21 - - I2S1 - FLEXCOMM7 LPC5411x I2S interface + FLEXCOMM7 I2S 0x40098000 @@ -29184,38 +29242,6 @@ 21 - - SPI7 - FLEXCOMM7 - LPC5411x Serial Peripheral Interfaces (SPI) - SPI - 0x40098000 - - 0 - 0xE44 - registers - - - FLEXCOMM7 - 21 - - - - USART7 - FLEXCOMM7 - LPC5411x USARTs - USART - 0x40098000 - - 0 - 0xE44 - registers - - - FLEXCOMM7 - 21 - - ADC0 LPC5411x 12-bit ADC controller (ADC) @@ -29258,7 +29284,7 @@ ASYNMODE Select clock mode. - 0x8 + 8 1 read-write @@ -29277,7 +29303,7 @@ RESOL The number of bits of ADC resolution. Accuracy can be reduced to achieve higher conversion rates. A single conversion (including one conversion in a burst or sequence) requires the selected number of bits of resolution plus 3 ADC clocks. This field must only be altered when the ADC is fully idle. Changing it during any kind of ADC operation may have unpredictable results. ADC clock frequencies for various resolutions must not exceed: - 5x the system clock rate for 12-bit resolution - 4.3x the system clock rate for 10-bit resolution - 3.6x the system clock for 8-bit resolution - 3x the bus clock rate for 6-bit resolution - 0x9 + 9 2 read-write @@ -29306,7 +29332,7 @@ BYPASSCAL Bypass Calibration. This bit may be set to avoid the need to calibrate if offset error is not a concern in the application. - 0xB + 11 1 read-write @@ -29325,7 +29351,7 @@ TSAMP Sample Time. The default sampling period (TSAMP = '000') at the start of each conversion is 2.5 ADC clock periods. Depending on a variety of factors, including operating conditions and the output impedance of the analog source, longer sampling times may be required. See Section 28.7.10. The TSAMP field specifies the number of additional ADC clock cycles, from zero to seven, by which the sample period will be extended. The total conversion time will increase by the same number of clocks. 000 - The sample period will be the default 2.5 ADC clocks. A complete conversion with 12-bits of accuracy will require 15 clocks. 001- The sample period will be extended by one ADC clock to a total of 3.5 clock periods. A complete 12-bit conversion will require 16 clocks. 010 - The sample period will be extended by two clocks to 4.5 ADC clock cycles. A complete 12-bit conversion will require 17 ADC clocks. 111 - The sample period will be extended by seven clocks to 9.5 ADC clock cycles. A complete 12-bit conversion will require 22 ADC clocks. - 0xC + 12 3 read-write @@ -29383,14 +29409,14 @@ TRIGGER Selects which of the available hardware trigger sources will cause this conversion sequence to be initiated. Program the trigger input number in this field. See Table 476. In order to avoid generating a spurious trigger, it is recommended writing to this field only when SEQA_ENA (bit 31) is low. It is safe to change this field and set bit 31 in the same write. - 0xC + 12 6 read-write TRIGPOL Select the polarity of the selected input trigger for this conversion sequence. In order to avoid generating a spurious trigger, it is recommended writing to this field only when SEQA_ENA (bit 31) is low. It is safe to change this field and set bit 31 in the same write. - 0x12 + 18 1 read-write @@ -29409,7 +29435,7 @@ SYNCBYPASS Setting this bit allows the hardware trigger input to bypass synchronization flip-flop stages and therefore shorten the time between the trigger input signal and the start of a conversion. There are slightly different criteria for whether or not this bit can be set depending on the clock operating mode: Synchronous mode (the ASYNMODE in the CTRL register = 0): Synchronization may be bypassed (this bit may be set) if the selected trigger source is already synchronous with the main system clock (eg. coming from an on-chip, system-clock-based timer). Whether this bit is set or not, a trigger pulse must be maintained for at least one system clock period. Asynchronous mode (the ASYNMODE in the CTRL register = 1): Synchronization may be bypassed (this bit may be set) if it is certain that the duration of a trigger input pulse will be at least one cycle of the ADC clock (regardless of whether the trigger comes from and on-chip or off-chip source). If this bit is NOT set, the trigger pulse must at least be maintained for one system clock period. - 0x13 + 19 1 read-write @@ -29428,28 +29454,28 @@ START Writing a 1 to this field will launch one pass through this conversion sequence. The behavior will be identical to a sequence triggered by a hardware trigger. Do not write 1 to this bit if the BURST bit is set. This bit is only set to a 1 momentarily when written to launch a conversion sequence. It will consequently always read back as a zero. - 0x1A + 26 1 read-write BURST Writing a 1 to this bit will cause this conversion sequence to be continuously cycled through. Other sequence A triggers will be ignored while this bit is set. Repeated conversions can be halted by clearing this bit. The sequence currently in progress will be completed before conversions are terminated. Note that a new sequence could begin just before BURST is cleared. - 0x1B + 27 1 read-write SINGLESTEP When this bit is set, a hardware trigger or a write to the START bit will launch a single conversion on the next channel in the sequence instead of the default response of launching an entire sequence of conversions. Once all of the channels comprising a sequence have been converted, a subsequent trigger will repeat the sequence beginning with the first enabled channel. Interrupt generation will still occur either after each individual conversion or at the end of the entire sequence, depending on the state of the MODE bit. - 0x1C + 28 1 read-write LOWPRIO Set priority for sequence A. - 0x1D + 29 1 read-write @@ -29468,7 +29494,7 @@ MODE Indicates whether the primary method for retrieving conversion results for this sequence will be accomplished via reading the global data register (SEQA_GDAT) at the end of each conversion, or the individual channel result registers at the end of the entire sequence. Impacts when conversion-complete interrupt/DMA trigger for sequence-A will be generated and which overrun conditions contribute to an overrun interrupt as described below. - 0x1E + 30 1 read-write @@ -29487,7 +29513,7 @@ SEQ_ENA Sequence Enable. In order to avoid spuriously triggering the sequence, care should be taken to only set the SEQn_ENA bit when the selected trigger input is in its INACTIVE state (as defined by the TRIGPOL bit). If this condition is not met, the sequence will be triggered immediately upon being enabled. In order to avoid spuriously triggering the sequence, care should be taken to only set the SEQn_ENA bit when the selected trigger input is in its INACTIVE state (as defined by the TRIGPOL bit). If this condition is not met, the sequence will be triggered immediately upon being enabled. - 0x1F + 31 1 read-write @@ -29520,42 +29546,42 @@ RESULT This field contains the 12-bit ADC conversion result from the most recent conversion performed under conversion sequence associated with this register. The result is a binary fraction representing the voltage on the currently-selected input channel as it falls within the range of VREFP to VREFN. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VREFN, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP. DATAVALID = 1 indicates that this result has not yet been read. - 0x4 + 4 12 read-only THCMPRANGE Indicates whether the result of the last conversion performed was above, below or within the range established by the designated threshold comparison registers (THRn_LOW and THRn_HIGH). - 0x10 + 16 2 read-only THCMPCROSS Indicates whether the result of the last conversion performed represented a crossing of the threshold level established by the designated LOW threshold comparison register (THRn_LOW) and, if so, in what direction the crossing occurred. - 0x12 + 18 2 read-only CHN These bits contain the channel from which the RESULT bits were converted (e.g. 0000 identifies channel 0, 0001 channel 1, etc.). - 0x1A + 26 4 read-only OVERRUN This bit is set if a new conversion result is loaded into the RESULT field before a previous result has been read - i.e. while the DATAVALID bit is set. This bit is cleared, along with the DATAVALID bit, whenever this register is read. This bit will contribute to an overrun interrupt/DMA trigger if the MODE bit (in SEQAA_CTRL) for the corresponding sequence is set to '0' (and if the overrun interrupt is enabled). - 0x1E + 30 1 read-only DATAVALID This bit is set to '1' at the end of each conversion when a new result is loaded into the RESULT field. It is cleared whenever this register is read. This bit will cause a conversion-complete interrupt for the corresponding sequence if the MODE bit (in SEQA_CTRL) for that sequence is set to 0 (and if the interrupt is enabled). - 0x1F + 31 1 read-only @@ -29575,42 +29601,42 @@ RESULT This field contains the 12-bit ADC conversion result from the last conversion performed on this channel. This will be a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to VREFN. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VREFN, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP. - 0x4 + 4 12 read-only THCMPRANGE Threshold Range Comparison result. 0x0 = In Range: The last completed conversion was greater than or equal to the value programmed into the designated LOW threshold register (THRn_LOW) but less than or equal to the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x1 = Below Range: The last completed conversion on was less than the value programmed into the designated LOW threshold register (THRn_LOW). 0x2 = Above Range: The last completed conversion was greater than the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x3 = Reserved. - 0x10 + 16 2 read-only THCMPCROSS Threshold Crossing Comparison result. 0x0 = No threshold Crossing detected: The most recent completed conversion on this channel had the same relationship (above or below) to the threshold value established by the designated LOW threshold register (THRn_LOW) as did the previous conversion on this channel. 0x1 = Reserved. 0x2 = Downward Threshold Crossing Detected. Indicates that a threshold crossing in the downward direction has occurred - i.e. the previous sample on this channel was above the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is below that threshold. 0x3 = Upward Threshold Crossing Detected. Indicates that a threshold crossing in the upward direction has occurred - i.e. the previous sample on this channel was below the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is above that threshold. - 0x12 + 18 2 read-only CHANNEL This field is hard-coded to contain the channel number that this particular register relates to (i.e. this field will contain 0b0000 for the DAT0 register, 0b0001 for the DAT1 register, etc) - 0x1A + 26 4 read-only OVERRUN This bit will be set to a 1 if a new conversion on this channel completes and overwrites the previous contents of the RESULT field before it has been read - i.e. while the DONE bit is set. This bit is cleared, along with the DONE bit, whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. This bit (in any of the 12 registers) will cause an overrun interrupt/DMA trigger to be asserted if the overrun interrupt is enabled. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled. - 0x1E + 30 1 read-only DATAVALID This bit is set to 1 when an ADC conversion on this channel completes. This bit is cleared whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled. - 0x1F + 31 1 read-only @@ -29628,7 +29654,7 @@ THRLOW Low threshold value against which ADC results will be compared - 0x4 + 4 12 read-write @@ -29646,7 +29672,7 @@ THRLOW Low threshold value against which ADC results will be compared - 0x4 + 4 12 read-write @@ -29664,7 +29690,7 @@ THRHIGH High threshold value against which ADC results will be compared - 0x4 + 4 12 read-write @@ -29682,7 +29708,7 @@ THRHIGH High threshold value against which ADC results will be compared - 0x4 + 4 12 read-write @@ -29719,77 +29745,77 @@ CH1_THRSEL Threshold select for channel 1. See description for channel 0. - 0x1 + 1 1 read-write CH2_THRSEL Threshold select for channel 2. See description for channel 0. - 0x2 + 2 1 read-write CH3_THRSEL Threshold select for channel 3. See description for channel 0. - 0x3 + 3 1 read-write CH4_THRSEL Threshold select for channel 4. See description for channel 0. - 0x4 + 4 1 read-write CH5_THRSEL Threshold select for channel 5. See description for channel 0. - 0x5 + 5 1 read-write CH6_THRSEL Threshold select for channel 6. See description for channel 0. - 0x6 + 6 1 read-write CH7_THRSEL Threshold select for channel 7. See description for channel 0. - 0x7 + 7 1 read-write CH8_THRSEL Threshold select for channel 8. See description for channel 0. - 0x8 + 8 1 read-write CH9_THRSEL Threshold select for channel 9. See description for channel 0. - 0x9 + 9 1 read-write CH10_THRSEL Threshold select for channel 10. See description for channel 0. - 0xA + 10 1 read-write CH11_THRSEL Threshold select for channel 11. See description for channel 0. - 0xB + 11 1 read-write @@ -29826,7 +29852,7 @@ SEQB_INTEN Sequence B interrupt enable. - 0x1 + 1 1 read-write @@ -29845,7 +29871,7 @@ OVR_INTEN Overrun interrupt enable. - 0x2 + 2 1 read-write @@ -29864,7 +29890,7 @@ ADCMPINTEN0 Threshold comparison interrupt enable for channel 0. - 0x3 + 3 2 read-write @@ -29888,77 +29914,77 @@ ADCMPINTEN1 Channel 1 threshold comparison interrupt enable. See description for channel 0. - 0x5 + 5 2 read-write ADCMPINTEN2 Channel 2 threshold comparison interrupt enable. See description for channel 0. - 0x7 + 7 2 read-write ADCMPINTEN3 Channel 3 threshold comparison interrupt enable. See description for channel 0. - 0x9 + 9 2 read-write ADCMPINTEN4 Channel 4 threshold comparison interrupt enable. See description for channel 0. - 0xB + 11 2 read-write ADCMPINTEN5 Channel 5 threshold comparison interrupt enable. See description for channel 0. - 0xD + 13 2 read-write ADCMPINTEN6 Channel 6 threshold comparison interrupt enable. See description for channel 0. - 0xF + 15 2 read-write ADCMPINTEN7 Channel 7 threshold comparison interrupt enable. See description for channel 0. - 0x11 + 17 2 read-write ADCMPINTEN8 Channel 8 threshold comparison interrupt enable. See description for channel 0. - 0x13 + 19 2 read-write ADCMPINTEN9 Channel 9 threshold comparison interrupt enable. See description for channel 0. - 0x15 + 21 2 read-write ADCMPINTEN10 Channel 10 threshold comparison interrupt enable. See description for channel 0. - 0x17 + 23 2 read-write ADCMPINTEN11 Channel 21 threshold comparison interrupt enable. See description for channel 0. - 0x19 + 25 2 read-write @@ -29983,203 +30009,203 @@ THCMP1 Threshold comparison event on Channel 1. See description for channel 0. - 0x1 + 1 1 read-write THCMP2 Threshold comparison event on Channel 2. See description for channel 0. - 0x2 + 2 1 read-write THCMP3 Threshold comparison event on Channel 3. See description for channel 0. - 0x3 + 3 1 read-write THCMP4 Threshold comparison event on Channel 4. See description for channel 0. - 0x4 + 4 1 read-write THCMP5 Threshold comparison event on Channel 5. See description for channel 0. - 0x5 + 5 1 read-write THCMP6 Threshold comparison event on Channel 6. See description for channel 0. - 0x6 + 6 1 read-write THCMP7 Threshold comparison event on Channel 7. See description for channel 0. - 0x7 + 7 1 read-write THCMP8 Threshold comparison event on Channel 8. See description for channel 0. - 0x8 + 8 1 read-write THCMP9 Threshold comparison event on Channel 9. See description for channel 0. - 0x9 + 9 1 read-write THCMP10 Threshold comparison event on Channel 10. See description for channel 0. - 0xA + 10 1 read-write THCMP11 Threshold comparison event on Channel 11. See description for channel 0. - 0xB + 11 1 read-write OVERRUN0 Mirrors the OVERRRUN status flag from the result register for ADC channel 0 - 0xC + 12 1 read-only OVERRUN1 Mirrors the OVERRRUN status flag from the result register for ADC channel 1 - 0xD + 13 1 read-only OVERRUN2 Mirrors the OVERRRUN status flag from the result register for ADC channel 2 - 0xE + 14 1 read-only OVERRUN3 Mirrors the OVERRRUN status flag from the result register for ADC channel 3 - 0xF + 15 1 read-only OVERRUN4 Mirrors the OVERRRUN status flag from the result register for ADC channel 4 - 0x10 + 16 1 read-only OVERRUN5 Mirrors the OVERRRUN status flag from the result register for ADC channel 5 - 0x11 + 17 1 read-only OVERRUN6 Mirrors the OVERRRUN status flag from the result register for ADC channel 6 - 0x12 + 18 1 read-only OVERRUN7 Mirrors the OVERRRUN status flag from the result register for ADC channel 7 - 0x13 + 19 1 read-only OVERRUN8 Mirrors the OVERRRUN status flag from the result register for ADC channel 8 - 0x14 + 20 1 read-only OVERRUN9 Mirrors the OVERRRUN status flag from the result register for ADC channel 9 - 0x15 + 21 1 read-only OVERRUN10 Mirrors the OVERRRUN status flag from the result register for ADC channel 10 - 0x16 + 22 1 read-only OVERRUN11 Mirrors the OVERRRUN status flag from the result register for ADC channel 11 - 0x17 + 23 1 read-only SEQA_OVR Mirrors the global OVERRUN status flag in the SEQA_GDAT register - 0x18 + 24 1 read-only SEQB_OVR Mirrors the global OVERRUN status flag in the SEQB_GDAT register - 0x19 + 25 1 read-only SEQA_INT Sequence A interrupt/DMA trigger. If the MODE bit in the SEQA_CTRL register is 0, this flag will mirror the DATAVALID bit in the sequence A global data register (SEQA_GDAT), which is set at the end of every ADC conversion performed as part of sequence A. It will be cleared automatically when the SEQA_GDAT register is read. If the MODE bit in the SEQA_CTRL register is 1, this flag will be set upon completion of an entire A sequence. In this case it must be cleared by writing a 1 to this SEQA_INT bit. This interrupt must be enabled in the INTEN register. - 0x1C + 28 1 read-only SEQB_INT Sequence A interrupt/DMA trigger. If the MODE bit in the SEQB_CTRL register is 0, this flag will mirror the DATAVALID bit in the sequence A global data register (SEQB_GDAT), which is set at the end of every ADC conversion performed as part of sequence B. It will be cleared automatically when the SEQB_GDAT register is read. If the MODE bit in the SEQB_CTRL register is 1, this flag will be set upon completion of an entire B sequence. In this case it must be cleared by writing a 1 to this SEQB_INT bit. This interrupt must be enabled in the INTEN register. - 0x1D + 29 1 read-only THCMP_INT Threshold Comparison Interrupt. This bit will be set if any of the THCMP flags in the lower bits of this register are set to 1 (due to an enabled out-of-range or threshold-crossing event on any channel). Each type of threshold comparison interrupt on each channel must be individually enabled in the INTEN register to cause this interrupt. This bit will be cleared when all of the individual threshold flags are cleared via writing 1s to those bits. - 0x1E + 30 1 read-only OVR_INT Overrun Interrupt flag. Any overrun bit in any of the individual channel data registers will cause this interrupt. In addition, if the MODE bit in either of the SEQn_CTRL registers is 0 then the OVERRUN bit in the corresponding SEQn_GDAT register will also cause this interrupt. This interrupt must be enabled in the INTEN register. This bit will be cleared when all of the individual overrun bits have been cleared via reading the corresponding data registers. - 0x1F + 31 1 read-only @@ -30204,7 +30230,7 @@ ADC_INIT ADC Initialization. After enabling the ADC (setting the ADC_ENA bit), the API routine will EITHER set this bit or the CALIB bit in the CALIB register, depending on whether or not calibration is required. Setting this bit will launch the 'dummy' conversion cycle that is required if a calibration is not performed. It will also reload the stored calibration value from a previous calibration unless the BYPASSCAL bit is set. This bit should only be set AFTER the ADC_ENA bit is set and after the CALIREQD bit is tested to determine whether a calibration or an ADC dummy conversion cycle is required. It should not be set during the same write that sets the ADC_ENA bit. This bit can only be set to a '1' by software. It is cleared automatically when the 'dummy' conversion cycle completes. - 0x1 + 1 1 read-write @@ -30229,14 +30255,14 @@ CALREQD Calibration required. This read-only bit indicates if calibration is required when enabling the ADC. CALREQD will be '1' if no calibration has been run since the chip was powered-up and if the BYPASSCAL bit in the CTRL register is low. Software will test this bit to determine whether to initiate a calibration cycle or whether to set the ADC_INIT bit (in the STARTUP register) to launch the ADC initialization process which includes a 'dummy' conversion cycle. Note: A 'dummy' conversion cycle requires approximately 6 ADC clocks as opposed to 81 clocks required for calibration. - 0x1 + 1 1 read-write CALVALUE Calibration Value. This read-only field displays the calibration value established during last calibration cycle. This value is not typically of any use to the user. - 0x2 + 2 7 read-write @@ -30244,5 +30270,5710 @@ + + ITM + Instrumentation Trace Macrocell Registers + ITM + ITM_ + 0xE0000000 + + 0 + 0x1000 + registers + + + + STIM0_READ + Stimulus Port Register 0 (for reading) + STIM0_READ_STIM0_WRITE + 0 + 32 + read-write + 0 + 0xFFFFFFFE + + + FIFOREADY + no description available + 0 + 1 + read-write + + + + + STIM0_WRITE + Stimulus Port Register 0 (for writing) + STIM0_READ_STIM0_WRITE + 0 + 32 + read-write + 0 + 0 + + + STIMULUS + Data write to the stimulus port FIFO, for forwarding as a software event packet. + 0 + 32 + read-write + + + + + STIM1_READ + Stimulus Port Register 1 (for reading) + STIM1_READ_STIM1_WRITE + 0x4 + 32 + read-write + 0 + 0xFFFFFFFE + + + FIFOREADY + no description available + 0 + 1 + read-write + + + + + STIM1_WRITE + Stimulus Port Register 1 (for writing) + STIM1_READ_STIM1_WRITE + 0x4 + 32 + read-write + 0 + 0 + + + STIMULUS + Data write to the stimulus port FIFO, for forwarding as a software event packet. + 0 + 32 + read-write + + + + + STIM2_READ + Stimulus Port Register 2 (for reading) + STIM2_READ_STIM2_WRITE + 0x8 + 32 + read-write + 0 + 0xFFFFFFFE + + + FIFOREADY + no description available + 0 + 1 + read-write + + + + + STIM2_WRITE + Stimulus Port Register 2 (for writing) + STIM2_READ_STIM2_WRITE + 0x8 + 32 + read-write + 0 + 0 + + + STIMULUS + Data write to the stimulus port FIFO, for forwarding as a software event packet. + 0 + 32 + read-write + + + + + STIM3_READ + Stimulus Port Register 3 (for reading) + STIM3_READ_STIM3_WRITE + 0xC + 32 + read-write + 0 + 0xFFFFFFFE + + + FIFOREADY + no description available + 0 + 1 + read-write + + + + + STIM3_WRITE + Stimulus Port Register 3 (for writing) + STIM3_READ_STIM3_WRITE + 0xC + 32 + read-write + 0 + 0 + + + STIMULUS + Data write to the stimulus port FIFO, for forwarding as a software event packet. + 0 + 32 + read-write + + + + + STIM4_READ + Stimulus Port Register 4 (for reading) + STIM4_READ_STIM4_WRITE + 0x10 + 32 + read-write + 0 + 0xFFFFFFFE + + + FIFOREADY + no description available + 0 + 1 + read-write + + + + + STIM4_WRITE + Stimulus Port Register 4 (for writing) + STIM4_READ_STIM4_WRITE + 0x10 + 32 + read-write + 0 + 0 + + + STIMULUS + Data write to the stimulus port FIFO, for forwarding as a software event packet. + 0 + 32 + read-write + + + + + STIM5_READ + Stimulus Port Register 5 (for reading) + STIM5_READ_STIM5_WRITE + 0x14 + 32 + read-write + 0 + 0xFFFFFFFE + + + FIFOREADY + no description available + 0 + 1 + read-write + + + + + STIM5_WRITE + Stimulus Port Register 5 (for writing) + STIM5_READ_STIM5_WRITE + 0x14 + 32 + read-write + 0 + 0 + + + STIMULUS + Data write to the stimulus port FIFO, for forwarding as a software event packet. + 0 + 32 + read-write + + + + + STIM6_READ + Stimulus Port Register 6 (for reading) + STIM6_READ_STIM6_WRITE + 0x18 + 32 + read-write + 0 + 0xFFFFFFFE + + + FIFOREADY + no description available + 0 + 1 + read-write + + + + + STIM6_WRITE + Stimulus Port Register 6 (for writing) + STIM6_READ_STIM6_WRITE + 0x18 + 32 + read-write + 0 + 0 + + + STIMULUS + Data write to the stimulus port FIFO, for forwarding as a software event packet. + 0 + 32 + read-write + + + + + STIM7_READ + Stimulus Port Register 7 (for reading) + STIM7_READ_STIM7_WRITE + 0x1C + 32 + read-write + 0 + 0xFFFFFFFE + + + FIFOREADY + no description available + 0 + 1 + read-write + + + + + STIM7_WRITE + Stimulus Port Register 7 (for writing) + STIM7_READ_STIM7_WRITE + 0x1C + 32 + read-write + 0 + 0 + + + STIMULUS + Data write to the stimulus port FIFO, for forwarding as a software event packet. + 0 + 32 + read-write + + + + + STIM8_READ + Stimulus Port Register 8 (for reading) + STIM8_READ_STIM8_WRITE + 0x20 + 32 + read-write + 0 + 0xFFFFFFFE + + + FIFOREADY + no description available + 0 + 1 + read-write + + + + + STIM8_WRITE + Stimulus Port Register 8 (for writing) + STIM8_READ_STIM8_WRITE + 0x20 + 32 + read-write + 0 + 0 + + + STIMULUS + Data write to the stimulus port FIFO, for forwarding as a software event packet. + 0 + 32 + read-write + + + + + STIM9_READ + Stimulus Port Register 9 (for reading) + STIM9_READ_STIM9_WRITE + 0x24 + 32 + read-write + 0 + 0xFFFFFFFE + + + FIFOREADY + no description available + 0 + 1 + read-write + + + + + STIM9_WRITE + Stimulus Port Register 9 (for writing) + STIM9_READ_STIM9_WRITE + 0x24 + 32 + read-write + 0 + 0 + + + STIMULUS + Data write to the stimulus port FIFO, for forwarding as a software event packet. + 0 + 32 + read-write + + + + + STIM10_READ + Stimulus Port Register 10 (for reading) + STIM10_READ_STIM10_WRITE + 0x28 + 32 + read-write + 0 + 0xFFFFFFFE + + + FIFOREADY + no description available + 0 + 1 + read-write + + + + + STIM10_WRITE + Stimulus Port Register 10 (for writing) + STIM10_READ_STIM10_WRITE + 0x28 + 32 + read-write + 0 + 0 + + + STIMULUS + Data write to the stimulus port FIFO, for forwarding as a software event packet. + 0 + 32 + read-write + + + + + STIM11_READ + Stimulus Port Register 11 (for reading) + STIM11_READ_STIM11_WRITE + 0x2C + 32 + read-write + 0 + 0xFFFFFFFE + + + FIFOREADY + no description available + 0 + 1 + read-write + + + + + STIM11_WRITE + Stimulus Port Register 11 (for writing) + STIM11_READ_STIM11_WRITE + 0x2C + 32 + read-write + 0 + 0 + + + STIMULUS + Data write to the stimulus port FIFO, for forwarding as a software event packet. + 0 + 32 + read-write + + + + + STIM12_READ + Stimulus Port Register 12 (for reading) + STIM12_READ_STIM12_WRITE + 0x30 + 32 + read-write + 0 + 0xFFFFFFFE + + + FIFOREADY + no description available + 0 + 1 + read-write + + + + + STIM12_WRITE + Stimulus Port Register 12 (for writing) + STIM12_READ_STIM12_WRITE + 0x30 + 32 + read-write + 0 + 0 + + + STIMULUS + Data write to the stimulus port FIFO, for forwarding as a software event packet. + 0 + 32 + read-write + + + + + STIM13_READ + Stimulus Port Register 13 (for reading) + STIM13_READ_STIM13_WRITE + 0x34 + 32 + read-write + 0 + 0xFFFFFFFE + + + FIFOREADY + no description available + 0 + 1 + read-write + + + + + STIM13_WRITE + Stimulus Port Register 13 (for writing) + STIM13_READ_STIM13_WRITE + 0x34 + 32 + read-write + 0 + 0 + + + STIMULUS + Data write to the stimulus port FIFO, for forwarding as a software event packet. + 0 + 32 + read-write + + + + + STIM14_READ + Stimulus Port Register 14 (for reading) + STIM14_READ_STIM14_WRITE + 0x38 + 32 + read-write + 0 + 0xFFFFFFFE + + + FIFOREADY + no description available + 0 + 1 + read-write + + + + + STIM14_WRITE + Stimulus Port Register 14 (for writing) + STIM14_READ_STIM14_WRITE + 0x38 + 32 + read-write + 0 + 0 + + + STIMULUS + Data write to the stimulus port FIFO, for forwarding as a software event packet. + 0 + 32 + read-write + + + + + STIM15_READ + Stimulus Port Register 15 (for reading) + STIM15_READ_STIM15_WRITE + 0x3C + 32 + read-write + 0 + 0xFFFFFFFE + + + FIFOREADY + no description available + 0 + 1 + read-write + + + + + STIM15_WRITE + Stimulus Port Register 15 (for writing) + STIM15_READ_STIM15_WRITE + 0x3C + 32 + read-write + 0 + 0 + + + STIMULUS + Data write to the stimulus port FIFO, for forwarding as a software event packet. + 0 + 32 + read-write + + + + + STIM16_READ + Stimulus Port Register 16 (for reading) + STIM16_READ_STIM16_WRITE + 0x40 + 32 + read-write + 0 + 0xFFFFFFFE + + + FIFOREADY + no description available + 0 + 1 + read-write + + + + + STIM16_WRITE + Stimulus Port Register 16 (for writing) + STIM16_READ_STIM16_WRITE + 0x40 + 32 + read-write + 0 + 0 + + + STIMULUS + Data write to the stimulus port FIFO, for forwarding as a software event packet. + 0 + 32 + read-write + + + + + STIM17_READ + Stimulus Port Register 17 (for reading) + STIM17_READ_STIM17_WRITE + 0x44 + 32 + read-write + 0 + 0xFFFFFFFE + + + FIFOREADY + no description available + 0 + 1 + read-write + + + + + STIM17_WRITE + Stimulus Port Register 17 (for writing) + STIM17_READ_STIM17_WRITE + 0x44 + 32 + read-write + 0 + 0 + + + STIMULUS + Data write to the stimulus port FIFO, for forwarding as a software event packet. + 0 + 32 + read-write + + + + + STIM18_READ + Stimulus Port Register 18 (for reading) + STIM18_READ_STIM18_WRITE + 0x48 + 32 + read-write + 0 + 0xFFFFFFFE + + + FIFOREADY + no description available + 0 + 1 + read-write + + + + + STIM18_WRITE + Stimulus Port Register 18 (for writing) + STIM18_READ_STIM18_WRITE + 0x48 + 32 + read-write + 0 + 0 + + + STIMULUS + Data write to the stimulus port FIFO, for forwarding as a software event packet. + 0 + 32 + read-write + + + + + STIM19_READ + Stimulus Port Register 19 (for reading) + STIM19_READ_STIM19_WRITE + 0x4C + 32 + read-write + 0 + 0xFFFFFFFE + + + FIFOREADY + no description available + 0 + 1 + read-write + + + + + STIM19_WRITE + Stimulus Port Register 19 (for writing) + STIM19_READ_STIM19_WRITE + 0x4C + 32 + read-write + 0 + 0 + + + STIMULUS + Data write to the stimulus port FIFO, for forwarding as a software event packet. + 0 + 32 + read-write + + + + + STIM20_READ + Stimulus Port Register 20 (for reading) + STIM20_READ_STIM20_WRITE + 0x50 + 32 + read-write + 0 + 0xFFFFFFFE + + + FIFOREADY + no description available + 0 + 1 + read-write + + + + + STIM20_WRITE + Stimulus Port Register 20 (for writing) + STIM20_READ_STIM20_WRITE + 0x50 + 32 + read-write + 0 + 0 + + + STIMULUS + Data write to the stimulus port FIFO, for forwarding as a software event packet. + 0 + 32 + read-write + + + + + STIM21_READ + Stimulus Port Register 21 (for reading) + STIM21_READ_STIM21_WRITE + 0x54 + 32 + read-write + 0 + 0xFFFFFFFE + + + FIFOREADY + no description available + 0 + 1 + read-write + + + + + STIM21_WRITE + Stimulus Port Register 21 (for writing) + STIM21_READ_STIM21_WRITE + 0x54 + 32 + read-write + 0 + 0 + + + STIMULUS + Data write to the stimulus port FIFO, for forwarding as a software event packet. + 0 + 32 + read-write + + + + + STIM22_READ + Stimulus Port Register 22 (for reading) + STIM22_READ_STIM22_WRITE + 0x58 + 32 + read-write + 0 + 0xFFFFFFFE + + + FIFOREADY + no description available + 0 + 1 + read-write + + + + + STIM22_WRITE + Stimulus Port Register 22 (for writing) + STIM22_READ_STIM22_WRITE + 0x58 + 32 + read-write + 0 + 0 + + + STIMULUS + Data write to the stimulus port FIFO, for forwarding as a software event packet. + 0 + 32 + read-write + + + + + STIM23_READ + Stimulus Port Register 23 (for reading) + STIM23_READ_STIM23_WRITE + 0x5C + 32 + read-write + 0 + 0xFFFFFFFE + + + FIFOREADY + no description available + 0 + 1 + read-write + + + + + STIM23_WRITE + Stimulus Port Register 23 (for writing) + STIM23_READ_STIM23_WRITE + 0x5C + 32 + read-write + 0 + 0 + + + STIMULUS + Data write to the stimulus port FIFO, for forwarding as a software event packet. + 0 + 32 + read-write + + + + + STIM24_READ + Stimulus Port Register 24 (for reading) + STIM24_READ_STIM24_WRITE + 0x60 + 32 + read-write + 0 + 0xFFFFFFFE + + + FIFOREADY + no description available + 0 + 1 + read-write + + + + + STIM24_WRITE + Stimulus Port Register 24 (for writing) + STIM24_READ_STIM24_WRITE + 0x60 + 32 + read-write + 0 + 0 + + + STIMULUS + Data write to the stimulus port FIFO, for forwarding as a software event packet. + 0 + 32 + read-write + + + + + STIM25_READ + Stimulus Port Register 25 (for reading) + STIM25_READ_STIM25_WRITE + 0x64 + 32 + read-write + 0 + 0xFFFFFFFE + + + FIFOREADY + no description available + 0 + 1 + read-write + + + + + STIM25_WRITE + Stimulus Port Register 25 (for writing) + STIM25_READ_STIM25_WRITE + 0x64 + 32 + read-write + 0 + 0 + + + STIMULUS + Data write to the stimulus port FIFO, for forwarding as a software event packet. + 0 + 32 + read-write + + + + + STIM26_READ + Stimulus Port Register 26 (for reading) + STIM26_READ_STIM26_WRITE + 0x68 + 32 + read-write + 0 + 0xFFFFFFFE + + + FIFOREADY + no description available + 0 + 1 + read-write + + + + + STIM26_WRITE + Stimulus Port Register 26 (for writing) + STIM26_READ_STIM26_WRITE + 0x68 + 32 + read-write + 0 + 0 + + + STIMULUS + Data write to the stimulus port FIFO, for forwarding as a software event packet. + 0 + 32 + read-write + + + + + STIM27_READ + Stimulus Port Register 27 (for reading) + STIM27_READ_STIM27_WRITE + 0x6C + 32 + read-write + 0 + 0xFFFFFFFE + + + FIFOREADY + no description available + 0 + 1 + read-write + + + + + STIM27_WRITE + Stimulus Port Register 27 (for writing) + STIM27_READ_STIM27_WRITE + 0x6C + 32 + read-write + 0 + 0 + + + STIMULUS + Data write to the stimulus port FIFO, for forwarding as a software event packet. + 0 + 32 + read-write + + + + + STIM28_READ + Stimulus Port Register 28 (for reading) + STIM28_READ_STIM28_WRITE + 0x70 + 32 + read-write + 0 + 0xFFFFFFFE + + + FIFOREADY + no description available + 0 + 1 + read-write + + + + + STIM28_WRITE + Stimulus Port Register 28 (for writing) + STIM28_READ_STIM28_WRITE + 0x70 + 32 + read-write + 0 + 0 + + + STIMULUS + Data write to the stimulus port FIFO, for forwarding as a software event packet. + 0 + 32 + read-write + + + + + STIM29_READ + Stimulus Port Register 29 (for reading) + STIM29_READ_STIM29_WRITE + 0x74 + 32 + read-write + 0 + 0xFFFFFFFE + + + FIFOREADY + no description available + 0 + 1 + read-write + + + + + STIM29_WRITE + Stimulus Port Register 29 (for writing) + STIM29_READ_STIM29_WRITE + 0x74 + 32 + read-write + 0 + 0 + + + STIMULUS + Data write to the stimulus port FIFO, for forwarding as a software event packet. + 0 + 32 + read-write + + + + + STIM30_READ + Stimulus Port Register 30 (for reading) + STIM30_READ_STIM30_WRITE + 0x78 + 32 + read-write + 0 + 0xFFFFFFFE + + + FIFOREADY + no description available + 0 + 1 + read-write + + + + + STIM30_WRITE + Stimulus Port Register 30 (for writing) + STIM30_READ_STIM30_WRITE + 0x78 + 32 + read-write + 0 + 0 + + + STIMULUS + Data write to the stimulus port FIFO, for forwarding as a software event packet. + 0 + 32 + read-write + + + + + STIM31_READ + Stimulus Port Register 31 (for reading) + STIM31_READ_STIM31_WRITE + 0x7C + 32 + read-write + 0 + 0xFFFFFFFE + + + FIFOREADY + no description available + 0 + 1 + read-write + + + + + STIM31_WRITE + Stimulus Port Register 31 (for writing) + STIM31_READ_STIM31_WRITE + 0x7C + 32 + read-write + 0 + 0 + + + STIMULUS + Data write to the stimulus port FIFO, for forwarding as a software event packet. + 0 + 32 + read-write + + + + + TER + Trace Enable Register + 0xE00 + 32 + read-write + 0 + 0xFFFFFFFF + + + STIMENA + For bit STIMENA[n], in register ITM_TERx: 0 = Stimulus port (32x + n) disabled 1 = Stimulus port (32x + n) enabled + 0 + 32 + read-write + + + + + TPR + Trace Privilege Register + 0xE40 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRIVMASK + Bit mask to enable tracing on ITM stimulus ports: Bit [0] = stimulus port [7:0] Bit [1] = stimulus port [15:8] Bit [2] = stimulus port [23:16] Bit [3] = stimulus port [31:24] + 0 + 4 + read-write + + + + + TCR + Trace Control Register + 0xE80 + 32 + read-write + 0 + 0xFFFFFFFF + + + ITMENA + no description available + 0 + 1 + read-write + + + ITMENA_0 + Disabled. + 0 + + + ITMENA_1 + Enabled. + 0x1 + + + + + TSENA + no description available + 1 + 1 + read-write + + + TSENA_0 + Disabled. + 0 + + + TSENA_1 + Enabled. + 0x1 + + + + + SYNCENA + no description available + 2 + 1 + read-write + + + SYNCENA_0 + Disabled. + 0 + + + SYNCENA_1 + Enabled. + 0x1 + + + + + TXENA + no description available + 3 + 1 + read-write + + + TXENA_0 + Disabled. + 0 + + + TXENA_1 + Enabled. + 0x1 + + + + + SWOENA + no description available + 4 + 1 + read-write + + + SWOENA_0 + Timestamp counter uses the processor system clock. + 0 + + + SWOENA_1 + Timestamp counter uses asynchronous clock from the TPIU interface. + 0x1 + + + + + TSPrescale + Local timestamp prescaler, used with the trace packet reference clock. + 8 + 2 + read-write + + + TSPrescale_0 + No prescaling. + 0 + + + TSPrescale_1 + Divide by 4. + 0x1 + + + TSPrescale_2 + Divide by 16. + 0x2 + + + TSPrescale_3 + Divide by 64. + 0x3 + + + + + GTSFREQ + Global timestamp frequency. Defines how often the ITM generates a global timestamp, based on the global timestamp clock frequency, or disables generation of global timestamps. + 10 + 2 + read-write + + + GTSFREQ_0 + Disable generation of global timestamps. + 0 + + + GTSFREQ_1 + Generate timestamp request whenever the ITM detects a change in global timestamp counter bits [47:7]. This is approximately every 128 cycles. + 0x1 + + + GTSFREQ_2 + Generate timestamp request whenever the ITM detects a change in global timestamp counter bits [47:13]. This is approximately every 8192 cycles. + 0x2 + + + GTSFREQ_3 + Generate a timestamp after every packet, if the output FIFO is empty. + 0x3 + + + + + TraceBusID + Identifier for multi-source trace stream formatting. If multi-source trace is in use, the debugger must write a non-zero value to this field. + 16 + 7 + read-write + + + BUSY + Indicates whether the ITM is currently processing events: 0: ITM is not processing any events. 1: ITM events present and being drained. + 23 + 1 + read-only + + + BUSY_0 + ITM is not processing any events. + 0 + + + BUSY_1 + ITM events present and beeing drained. + 0x1 + + + + + + + LAR + Lock Access Register + 0xFB0 + 32 + read-write + 0 + 0 + + + WriteAccessCode + Write Access Code. A write of 0xC5ACCE55 enables further write access to this device. An invalid write will have the affect of removing write access. + 0 + 32 + read-write + + + + + LSR + Lock Status Register + 0xFB4 + 32 + read-only + 0x1 + 0xFFFFFFFD + + + IMP + Lock mechanism is implemented. This bit always reads 1. + 0 + 1 + read-only + + + STATUS + Lock Status. This bit is HIGH when the device is locked, and LOW when unlocked. + 1 + 1 + read-only + + + s8BIT + Access Lock Register size. This bit reads 0 to indicate a 32-bit register is present. + 2 + 1 + read-only + + + + + PID4 + Peripheral Identification Register 4. + 0xFD0 + 32 + read-only + 0x4 + 0xFFFFFFFF + + + JEP106 + JEP106 continuation code. + 0 + 4 + read-only + + + c4KB + 4KB Count + 4 + 4 + read-only + + + + + PID5 + Peripheral Identification Register 5. + 0xFD4 + 32 + read-only + 0 + 0xFFFFFFFF + + + PID6 + Peripheral Identification Register 6. + 0xFD8 + 32 + read-only + 0 + 0xFFFFFFFF + + + PID7 + Peripheral Identification Register 7. + 0xFDC + 32 + read-only + 0 + 0xFFFFFFFF + + + PID0 + Peripheral Identification Register 0. + 0xFE0 + 32 + read-only + 0x2 + 0xFFFFFFFF + + + PartNumber + Part Number [7:0] + 0 + 8 + read-only + + + + + PID1 + Peripheral Identification Register 1. + 0xFE4 + 32 + read-only + 0xB0 + 0xFFFFFFFF + + + PartNumber + Part Number [11:8] + 0 + 4 + read-only + + + JEP106_identity_code + JEP106 identity code [3:0] + 4 + 4 + read-only + + + + + PID2 + Peripheral Identification Register 2. + 0xFE8 + 32 + read-only + 0x3B + 0xFFFFFFFF + + + JEP106_identity_code + JEP106 identity code [6:4] + 0 + 3 + read-only + + + Revision + Revision + 4 + 4 + read-only + + + + + PID3 + Peripheral Identification Register 3. + 0xFEC + 32 + read-only + 0 + 0xFFFFFFFF + + + CustomerModified + Customer Modified. + 0 + 4 + read-only + + + RevAnd + RevAnd + 4 + 4 + read-only + + + + + CID0 + Component Identification Register 0. + 0xFF0 + 32 + read-only + 0xD + 0xFFFFFFFF + + + Preamble + Preamble + 0 + 8 + read-only + + + + + CID1 + Component Identification Register 1. + 0xFF4 + 32 + read-only + 0xE0 + 0xFFFFFFFF + + + Preamble + Preamble + 0 + 4 + read-only + + + ComponentClass + Component class + 4 + 4 + read-only + + + ComponentClass_1 + ROM table. + 0x1 + + + ComponentClass_9 + CoreSight component. + 0x9 + + + ComponentClass_15 + PrimeCell of system component with no standardized register layout, for backward compatibility. + 0xF + + + + + + + CID2 + Component Identification Register 2. + 0xFF8 + 32 + read-only + 0x5 + 0xFFFFFFFF + + + Preamble + Preamble + 0 + 8 + read-only + + + + + CID3 + Component Identification Register 3. + 0xFFC + 32 + read-only + 0xB1 + 0xFFFFFFFF + + + Preamble + Preamble + 0 + 8 + read-only + + + + + + + SystemControl + System Control Block + SCB + SCB_ + 0xE000E000 + + 0 + 0xD40 + registers + + + + ACTLR + Auxiliary Control Register, + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DISMCYCINT + Disables interruption of multi-cycle instructions. + 0 + 1 + read-write + + + DISDEFWBUF + Disables write buffer use during default memory map accesses. + 1 + 1 + read-write + + + DISFOLD + Disables folding of IT instructions. + 2 + 1 + read-write + + + + + CPUID + CPUID Base Register + 0xD00 + 32 + read-only + 0x410FC240 + 0xFFFFFFFF + + + REVISION + Indicates patch release: 0x0 = Patch 0 + 0 + 4 + read-only + + + PARTNO + Indicates part number + 4 + 12 + read-only + + + VARIANT + Indicates processor revision: 0x2 = Revision 2 + 20 + 4 + read-only + + + IMPLEMENTER + Implementer code + 24 + 8 + read-only + + + + + ICSR + Interrupt Control and State Register + 0xD04 + 32 + read-write + 0 + 0xFFFFFFFF + + + VECTACTIVE + Active exception number + 0 + 9 + read-only + + + RETTOBASE + no description available + 11 + 1 + read-only + + + RETTOBASE_0 + there are preempted active exceptions to execute + 0 + + + RETTOBASE_1 + there are no active exceptions, or the currently-executing exception is the only active exception + 0x1 + + + + + VECTPENDING + Exception number of the highest priority pending enabled exception + 12 + 6 + read-only + + + ISRPENDING + no description available + 22 + 1 + read-only + + + ISRPREEMPT + no description available + 23 + 1 + read-only + + + ISRPREEMPT_0 + Will not service + 0 + + + ISRPREEMPT_1 + Will service a pending exception + 0x1 + + + + + PENDSTCLR + no description available + 25 + 1 + write-only + + + PENDSTCLR_0 + no effect + 0 + + + PENDSTCLR_1 + removes the pending state from the SysTick exception + 0x1 + + + + + PENDSTSET + no description available + 26 + 1 + read-write + + + PENDSTSET_0 + write: no effect; read: SysTick exception is not pending + 0 + + + PENDSTSET_1 + write: changes SysTick exception state to pending; read: SysTick exception is pending + 0x1 + + + + + PENDSVCLR + no description available + 27 + 1 + write-only + + + PENDSVCLR_0 + no effect + 0 + + + PENDSVCLR_1 + removes the pending state from the PendSV exception + 0x1 + + + + + PENDSVSET + no description available + 28 + 1 + read-write + + + PENDSVSET_0 + write: no effect; read: PendSV exception is not pending + 0 + + + PENDSVSET_1 + write: changes PendSV exception state to pending; read: PendSV exception is pending + 0x1 + + + + + NMIPENDSET + no description available + 31 + 1 + read-write + + + NMIPENDSET_0 + write: no effect; read: NMI exception is not pending + 0 + + + NMIPENDSET_1 + write: changes NMI exception state to pending; read: NMI exception is pending + 0x1 + + + + + + + VTOR + Vector Table Offset Register + 0xD08 + 32 + read-write + 0 + 0xFFFFFFFF + + + TBLOFF + Vector table base offset + 7 + 25 + read-write + + + + + AIRCR + Application Interrupt and Reset Control Register + 0xD0C + 32 + read-write + 0xFA050000 + 0xFFFFFFFF + + + VECTRESET + no description available + 0 + 1 + write-only + + + VECTCLRACTIVE + no description available + 1 + 1 + write-only + + + SYSRESETREQ + no description available + 2 + 1 + write-only + + + SYSRESETREQ_0 + no system reset request + 0 + + + SYSRESETREQ_1 + asserts a signal to the outer system that requests a reset + 0x1 + + + + + PRIGROUP + Interrupt priority grouping field. This field determines the split of group priority from subpriority. + 8 + 3 + read-write + + + ENDIANNESS + no description available + 15 + 1 + read-only + + + ENDIANNESS_0 + Little-endian + 0 + + + ENDIANNESS_1 + Big-endian + 0x1 + + + + + VECTKEY + Register key + 16 + 16 + read-write + + + + + SCR + System Control Register + 0xD10 + 32 + read-write + 0 + 0xFFFFFFFF + + + SLEEPONEXIT + no description available + 1 + 1 + read-write + + + SLEEPONEXIT_0 + o not sleep when returning to Thread mode + 0 + + + SLEEPONEXIT_1 + enter sleep, or deep sleep, on return from an ISR + 0x1 + + + + + SLEEPDEEP + no description available + 2 + 1 + read-write + + + SLEEPDEEP_0 + sleep + 0 + + + SLEEPDEEP_1 + deep sleep + 0x1 + + + + + SEVONPEND + no description available + 4 + 1 + read-write + + + SEVONPEND_0 + only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded + 0 + + + SEVONPEND_1 + enabled events and all interrupts, including disabled interrupts, can wakeup the processor + 0x1 + + + + + + + CCR + Configuration and Control Register + 0xD14 + 32 + read-write + 0 + 0xFFFFFFFF + + + NONBASETHRDENA + no description available + 0 + 1 + read-write + + + NONBASETHRDENA_0 + processor can enter Thread mode only when no exception is active + 0 + + + NONBASETHRDENA_1 + processor can enter Thread mode from any level under the control of an EXC_RETURN value + 0x1 + + + + + USERSETMPEND + Enables unprivileged software access to the STIR + 1 + 1 + read-write + + + USERSETMPEND_0 + disable + 0 + + + USERSETMPEND_1 + enable + 0x1 + + + + + UNALIGN_TRP + Enables unaligned access traps + 3 + 1 + read-write + + + UNALIGN_TRP_0 + do not trap unaligned halfword and word accesses + 0 + + + UNALIGN_TRP_1 + trap unaligned halfword and word accesses + 0x1 + + + + + DIV_0_TRP + Enables faulting or halting when the processor executes an SDIV or UDIV instruction with a divisor of 0 + 4 + 1 + read-write + + + DIV_0_TRP_0 + do not trap divide by 0 + 0 + + + DIV_0_TRP_1 + trap divide by 0 + 0x1 + + + + + BFHFNMIGN + Enables handlers with priority -1 or -2 to ignore data BusFaults caused by load and store instructions. + 8 + 1 + read-write + + + BFHFNMIGN_0 + data bus faults caused by load and store instructions cause a lock-up + 0 + + + BFHFNMIGN_1 + handlers running at priority -1 and -2 ignore data bus faults caused by load and store instructions + 0x1 + + + + + STKALIGN + Indicates stack alignment on exception entry + 9 + 1 + read-write + + + STKALIGN_0 + 4-byte aligned + 0 + + + STKALIGN_1 + 8-byte aligned + 0x1 + + + + + + + SHPR1 + System Handler Priority Register 1 + 0xD18 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRI_4 + Priority of system handler 4, MemManage + 0 + 8 + read-write + + + PRI_5 + Priority of system handler 5, BusFault + 8 + 8 + read-write + + + PRI_6 + Priority of system handler 6, UsageFault + 16 + 8 + read-write + + + + + SHPR2 + System Handler Priority Register 2 + 0xD1C + 32 + read-write + 0 + 0xFFFFFFFF + + + PRI_11 + Priority of system handler 11, SVCall + 24 + 8 + read-write + + + + + SHPR3 + System Handler Priority Register 3 + 0xD20 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRI_14 + Priority of system handler 14, PendSV + 16 + 8 + read-write + + + PRI_15 + Priority of system handler 15, SysTick exception + 24 + 8 + read-write + + + + + SHCSR + System Handler Control and State Register + 0xD24 + 32 + read-write + 0 + 0xFFFFFFFF + + + MEMFAULTACT + no description available + 0 + 1 + read-write + + + MEMFAULTACT_0 + exception is not active + 0 + + + MEMFAULTACT_1 + exception is active + 0x1 + + + + + BUSFAULTACT + no description available + 1 + 1 + read-write + + + BUSFAULTACT_0 + exception is not active + 0 + + + BUSFAULTACT_1 + exception is active + 0x1 + + + + + USGFAULTACT + no description available + 3 + 1 + read-write + + + USGFAULTACT_0 + exception is not active + 0 + + + USGFAULTACT_1 + exception is active + 0x1 + + + + + SVCALLACT + no description available + 7 + 1 + read-write + + + SVCALLACT_0 + exception is not active + 0 + + + SVCALLACT_1 + exception is active + 0x1 + + + + + MONITORACT + no description available + 8 + 1 + read-write + + + MONITORACT_0 + exception is not active + 0 + + + MONITORACT_1 + exception is active + 0x1 + + + + + PENDSVACT + no description available + 10 + 1 + read-write + + + PENDSVACT_0 + exception is not active + 0 + + + PENDSVACT_1 + exception is active + 0x1 + + + + + SYSTICKACT + no description available + 11 + 1 + read-write + + + SYSTICKACT_0 + exception is not active + 0 + + + SYSTICKACT_1 + exception is active + 0x1 + + + + + USGFAULTPENDED + no description available + 12 + 1 + read-write + + + USGFAULTPENDED_0 + exception is not pending + 0 + + + USGFAULTPENDED_1 + exception is pending + 0x1 + + + + + MEMFAULTPENDED + no description available + 13 + 1 + read-write + + + MEMFAULTPENDED_0 + exception is not pending + 0 + + + MEMFAULTPENDED_1 + exception is pending + 0x1 + + + + + BUSFAULTPENDED + no description available + 14 + 1 + read-write + + + BUSFAULTPENDED_0 + exception is not pending + 0 + + + BUSFAULTPENDED_1 + exception is pending + 0x1 + + + + + SVCALLPENDED + no description available + 15 + 1 + read-write + + + SVCALLPENDED_0 + exception is not pending + 0 + + + SVCALLPENDED_1 + exception is pending + 0x1 + + + + + MEMFAULTENA + no description available + 16 + 1 + read-write + + + MEMFAULTENA_0 + disable the exception + 0 + + + MEMFAULTENA_1 + enable the exception + 0x1 + + + + + BUSFAULTENA + no description available + 17 + 1 + read-write + + + BUSFAULTENA_0 + disable the exception + 0 + + + BUSFAULTENA_1 + enable the exception + 0x1 + + + + + USGFAULTENA + no description available + 18 + 1 + read-write + + + USGFAULTENA_0 + disable the exception + 0 + + + USGFAULTENA_1 + enable the exception + 0x1 + + + + + + + CFSR + Configurable Fault Status Registers + 0xD28 + 32 + read-write + 0 + 0xFFFFFFFF + + + IACCVIOL + no description available + 0 + 1 + read-write + + + IACCVIOL_0 + no instruction access violation fault + 0 + + + IACCVIOL_1 + the processor attempted an instruction fetch from a location that does not permit execution + 0x1 + + + + + DACCVIOL + no description available + 1 + 1 + read-write + + + DACCVIOL_0 + no data access violation fault + 0 + + + DACCVIOL_1 + the processor attempted a load or store at a location that does not permit the operation + 0x1 + + + + + MUNSTKERR + no description available + 3 + 1 + read-write + + + MUNSTKERR_0 + no unstacking fault + 0 + + + MUNSTKERR_1 + unstack for an exception return has caused one or more access violations + 0x1 + + + + + MSTKERR + no description available + 4 + 1 + read-write + + + MSTKERR_0 + no stacking fault + 0 + + + MSTKERR_1 + stacking for an exception entry has caused one or more access violations + 0x1 + + + + + MLSPERR + no description available + 5 + 1 + read-write + + + MLSPERR_0 + No MemManage fault occurred during floating-point lazy state preservation + 0 + + + MLSPERR_1 + A MemManage fault occurred during floating-point lazy state preservation + 0x1 + + + + + MMARVALID + no description available + 7 + 1 + read-write + + + MMARVALID_0 + value in MMAR is not a valid fault address + 0 + + + MMARVALID_1 + MMAR holds a valid fault address + 0x1 + + + + + IBUSERR + no description available + 8 + 1 + read-write + + + IBUSERR_0 + no instruction bus error + 0 + + + IBUSERR_1 + instruction bus error + 0x1 + + + + + PRECISERR + no description available + 9 + 1 + read-write + + + PRECISERR_0 + no precise data bus error + 0 + + + PRECISERR_1 + a data bus error has occurred, and the PC value stacked for the exception return points to the instruction that caused the fault + 0x1 + + + + + IMPRECISERR + no description available + 10 + 1 + read-write + + + IMPRECISERR_0 + no imprecise data bus error + 0 + + + IMPRECISERR_1 + a data bus error has occurred, but the return address in the stack frame is not related to the instruction that caused the error + 0x1 + + + + + UNSTKERR + no description available + 11 + 1 + read-write + + + UNSTKERR_0 + no unstacking fault + 0 + + + UNSTKERR_1 + unstack for an exception return has caused one or more BusFaults + 0x1 + + + + + STKERR + no description available + 12 + 1 + read-write + + + STKERR_0 + no stacking fault + 0 + + + STKERR_1 + stacking for an exception entry has caused one or more BusFaults + 0x1 + + + + + LSPERR + no description available + 13 + 1 + read-write + + + LSPERR_0 + No bus fault occurred during floating-point lazy state preservation + 0 + + + LSPERR_1 + A bus fault occurred during floating-point lazy state preservation + 0x1 + + + + + BFARVALID + no description available + 15 + 1 + read-write + + + BFARVALID_0 + value in BFAR is not a valid fault address + 0 + + + BFARVALID_1 + BFAR holds a valid fault address + 0x1 + + + + + UNDEFINSTR + no description available + 16 + 1 + read-write + + + UNDEFINSTR_0 + no undefined instruction UsageFault + 0 + + + UNDEFINSTR_1 + the processor has attempted to execute an undefined instruction + 0x1 + + + + + INVSTATE + no description available + 17 + 1 + read-write + + + INVSTATE_0 + no invalid state UsageFault + 0 + + + INVSTATE_1 + the processor has attempted to execute an instruction that makes illegal use of the EPSR + 0x1 + + + + + INVPC + no description available + 18 + 1 + read-write + + + INVPC_0 + no invalid PC load UsageFault + 0 + + + INVPC_1 + the processor has attempted an illegal load of EXC_RETURN to the PC + 0x1 + + + + + NOCP + no description available + 19 + 1 + read-write + + + NOCP_0 + no UsageFault caused by attempting to access a coprocessor + 0 + + + NOCP_1 + the processor has attempted to access a coprocessor + 0x1 + + + + + UNALIGNED + no description available + 24 + 1 + read-write + + + UNALIGNED_0 + no unaligned access fault, or unaligned access trapping not enabled + 0 + + + UNALIGNED_1 + the processor has made an unaligned memory access + 0x1 + + + + + DIVBYZERO + no description available + 25 + 1 + read-write + + + DIVBYZERO_0 + no divide by zero fault, or divide by zero trapping not enabled + 0 + + + DIVBYZERO_1 + the processor has executed an SDIV or UDIV instruction with a divisor of 0 + 0x1 + + + + + + + HFSR + HardFault Status register + 0xD2C + 32 + read-write + 0 + 0xFFFFFFFF + + + VECTTBL + no description available + 1 + 1 + read-write + + + VECTTBL_0 + no BusFault on vector table read + 0 + + + VECTTBL_1 + BusFault on vector table read + 0x1 + + + + + FORCED + no description available + 30 + 1 + read-write + + + FORCED_0 + no forced HardFault + 0 + + + FORCED_1 + forced HardFault + 0x1 + + + + + DEBUGEVT + no description available + 31 + 1 + read-write + + + + + DFSR + Debug Fault Status Register + 0xD30 + 32 + read-write + 0 + 0xFFFFFFFF + + + HALTED + no description available + 0 + 1 + read-write + + + HALTED_0 + No active halt request debug event + 0 + + + HALTED_1 + Halt request debug event active + 0x1 + + + + + BKPT + no description available + 1 + 1 + read-write + + + BKPT_0 + No current breakpoint debug event + 0 + + + BKPT_1 + At least one current breakpoint debug event + 0x1 + + + + + DWTTRAP + no description available + 2 + 1 + read-write + + + DWTTRAP_0 + No current debug events generated by the DWT + 0 + + + DWTTRAP_1 + At least one current debug event generated by the DWT + 0x1 + + + + + VCATCH + no description available + 3 + 1 + read-write + + + VCATCH_0 + No Vector catch triggered + 0 + + + VCATCH_1 + Vector catch triggered + 0x1 + + + + + EXTERNAL + no description available + 4 + 1 + read-write + + + EXTERNAL_0 + No EDBGRQ debug event + 0 + + + EXTERNAL_1 + EDBGRQ debug event + 0x1 + + + + + + + MMFAR + MemManage Address Register + 0xD34 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADDRESS + Address of MemManage fault location + 0 + 32 + read-write + + + + + BFAR + BusFault Address Register + 0xD38 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADDRESS + Address of the BusFault location + 0 + 32 + read-write + + + + + AFSR + Auxiliary Fault Status Register + 0xD3C + 32 + read-write + 0 + 0xFFFFFFFF + + + AUXFAULT + Latched version of the AUXFAULT inputs + 0 + 32 + read-write + + + + + + + SysTick + System timer + SysTick + SYST_ + 0xE000E010 + + 0 + 0x10 + registers + + + + CSR + SysTick Control and Status Register + 0 + 32 + read-write + 0x4 + 0xFFFFFFFF + + + ENABLE + no description available + 0 + 1 + read-write + + + ENABLE_0 + counter disabled + 0 + + + ENABLE_1 + counter enabled + 0x1 + + + + + TICKINT + no description available + 1 + 1 + read-write + + + TICKINT_0 + counting down to 0 does not assert the SysTick exception request + 0 + + + TICKINT_1 + counting down to 0 asserts the SysTick exception request + 0x1 + + + + + CLKSOURCE + no description available + 2 + 1 + read-write + + + CLKSOURCE_0 + external clock + 0 + + + CLKSOURCE_1 + processor clock + 0x1 + + + + + COUNTFLAG + no description available + 16 + 1 + read-write + + + + + RVR + SysTick Reload Value Register + 0x4 + 32 + read-write + 0 + 0xFFFFFFFF + + + RELOAD + Value to load into the SysTick Current Value Register when the counter reaches 0 + 0 + 24 + read-write + + + + + CVR + SysTick Current Value Register + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + CURRENT + Current value at the time the register is accessed + 0 + 24 + read-write + + + + + CALIB + SysTick Calibration Value Register + 0xC + 32 + read-only + 0x80000000 + 0xFFFFFFFF + + + TENMS + Reload value to use for 10ms timing + 0 + 24 + read-only + + + SKEW + no description available + 30 + 1 + read-only + + + SKEW_0 + 10ms calibration value is exact + 0 + + + SKEW_1 + 10ms calibration value is inexact, because of the clock frequency + 0x1 + + + + + NOREF + no description available + 31 + 1 + read-only + + + NOREF_0 + The reference clock is provided + 0 + + + NOREF_1 + The reference clock is not provided + 0x1 + + + + + + + + + NVIC + Nested Vectored Interrupt Controller + NVIC + 0xE000E100 + + 0 + 0xE04 + registers + + + + NVICISER0 + Interrupt Set Enable Register n + 0 + 32 + read-write + 0 + 0xFFFFFFFF + + + SETENA + Interrupt set enable bits + 0 + 32 + read-write + + + + + NVICISER1 + Interrupt Set Enable Register n + 0x4 + 32 + read-write + 0 + 0xFFFFFFFF + + + SETENA + Interrupt set enable bits + 0 + 32 + read-write + + + + + NVICISER2 + Interrupt Set Enable Register n + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + SETENA + Interrupt set enable bits + 0 + 32 + read-write + + + + + NVICISER3 + Interrupt Set Enable Register n + 0xC + 32 + read-write + 0 + 0xFFFFFFFF + + + SETENA + Interrupt set enable bits + 0 + 32 + read-write + + + + + NVICICER0 + Interrupt Clear Enable Register n + 0x80 + 32 + read-write + 0 + 0xFFFFFFFF + + + CLRENA + Interrupt clear-enable bits + 0 + 32 + read-write + + + + + NVICICER1 + Interrupt Clear Enable Register n + 0x84 + 32 + read-write + 0 + 0xFFFFFFFF + + + CLRENA + Interrupt clear-enable bits + 0 + 32 + read-write + + + + + NVICICER2 + Interrupt Clear Enable Register n + 0x88 + 32 + read-write + 0 + 0xFFFFFFFF + + + CLRENA + Interrupt clear-enable bits + 0 + 32 + read-write + + + + + NVICICER3 + Interrupt Clear Enable Register n + 0x8C + 32 + read-write + 0 + 0xFFFFFFFF + + + CLRENA + Interrupt clear-enable bits + 0 + 32 + read-write + + + + + NVICISPR0 + Interrupt Set Pending Register n + 0x100 + 32 + read-write + 0 + 0xFFFFFFFF + + + SETPEND + Interrupt set-pending bits + 0 + 32 + read-write + + + + + NVICISPR1 + Interrupt Set Pending Register n + 0x104 + 32 + read-write + 0 + 0xFFFFFFFF + + + SETPEND + Interrupt set-pending bits + 0 + 32 + read-write + + + + + NVICISPR2 + Interrupt Set Pending Register n + 0x108 + 32 + read-write + 0 + 0xFFFFFFFF + + + SETPEND + Interrupt set-pending bits + 0 + 32 + read-write + + + + + NVICISPR3 + Interrupt Set Pending Register n + 0x10C + 32 + read-write + 0 + 0xFFFFFFFF + + + SETPEND + Interrupt set-pending bits + 0 + 32 + read-write + + + + + NVICICPR0 + Interrupt Clear Pending Register n + 0x180 + 32 + read-write + 0 + 0xFFFFFFFF + + + CLRPEND + Interrupt clear-pending bits + 0 + 32 + read-write + + + + + NVICICPR1 + Interrupt Clear Pending Register n + 0x184 + 32 + read-write + 0 + 0xFFFFFFFF + + + CLRPEND + Interrupt clear-pending bits + 0 + 32 + read-write + + + + + NVICICPR2 + Interrupt Clear Pending Register n + 0x188 + 32 + read-write + 0 + 0xFFFFFFFF + + + CLRPEND + Interrupt clear-pending bits + 0 + 32 + read-write + + + + + NVICICPR3 + Interrupt Clear Pending Register n + 0x18C + 32 + read-write + 0 + 0xFFFFFFFF + + + CLRPEND + Interrupt clear-pending bits + 0 + 32 + read-write + + + + + NVICIABR0 + Interrupt Active bit Register n + 0x200 + 32 + read-write + 0 + 0xFFFFFFFF + + + ACTIVE + Interrupt active flags + 0 + 32 + read-write + + + + + NVICIABR1 + Interrupt Active bit Register n + 0x204 + 32 + read-write + 0 + 0xFFFFFFFF + + + ACTIVE + Interrupt active flags + 0 + 32 + read-write + + + + + NVICIABR2 + Interrupt Active bit Register n + 0x208 + 32 + read-write + 0 + 0xFFFFFFFF + + + ACTIVE + Interrupt active flags + 0 + 32 + read-write + + + + + NVICIABR3 + Interrupt Active bit Register n + 0x20C + 32 + read-write + 0 + 0xFFFFFFFF + + + ACTIVE + Interrupt active flags + 0 + 32 + read-write + + + + + NVICIP0 + Interrupt Priority Register n + 0x300 + 8 + read-write + 0 + 0xFF + + + PRI0 + Priority of interrupt 0 + 0 + 8 + read-write + + + + + NVICIP1 + Interrupt Priority Register n + 0x301 + 8 + read-write + 0 + 0xFF + + + PRI1 + Priority of interrupt 1 + 0 + 8 + read-write + + + + + NVICIP2 + Interrupt Priority Register n + 0x302 + 8 + read-write + 0 + 0xFF + + + PRI2 + Priority of interrupt 2 + 0 + 8 + read-write + + + + + NVICIP3 + Interrupt Priority Register n + 0x303 + 8 + read-write + 0 + 0xFF + + + PRI3 + Priority of interrupt 3 + 0 + 8 + read-write + + + + + NVICIP4 + Interrupt Priority Register n + 0x304 + 8 + read-write + 0 + 0xFF + + + PRI4 + Priority of interrupt 4 + 0 + 8 + read-write + + + + + NVICIP5 + Interrupt Priority Register n + 0x305 + 8 + read-write + 0 + 0xFF + + + PRI5 + Priority of interrupt 5 + 0 + 8 + read-write + + + + + NVICIP6 + Interrupt Priority Register n + 0x306 + 8 + read-write + 0 + 0xFF + + + PRI6 + Priority of interrupt 6 + 0 + 8 + read-write + + + + + NVICIP7 + Interrupt Priority Register n + 0x307 + 8 + read-write + 0 + 0xFF + + + PRI7 + Priority of interrupt 7 + 0 + 8 + read-write + + + + + NVICIP8 + Interrupt Priority Register n + 0x308 + 8 + read-write + 0 + 0xFF + + + PRI8 + Priority of interrupt 8 + 0 + 8 + read-write + + + + + NVICIP9 + Interrupt Priority Register n + 0x309 + 8 + read-write + 0 + 0xFF + + + PRI9 + Priority of interrupt 9 + 0 + 8 + read-write + + + + + NVICIP10 + Interrupt Priority Register n + 0x30A + 8 + read-write + 0 + 0xFF + + + PRI10 + Priority of interrupt 10 + 0 + 8 + read-write + + + + + NVICIP11 + Interrupt Priority Register n + 0x30B + 8 + read-write + 0 + 0xFF + + + PRI11 + Priority of interrupt 11 + 0 + 8 + read-write + + + + + NVICIP12 + Interrupt Priority Register n + 0x30C + 8 + read-write + 0 + 0xFF + + + PRI12 + Priority of interrupt 12 + 0 + 8 + read-write + + + + + NVICIP13 + Interrupt Priority Register n + 0x30D + 8 + read-write + 0 + 0xFF + + + PRI13 + Priority of interrupt 13 + 0 + 8 + read-write + + + + + NVICIP14 + Interrupt Priority Register n + 0x30E + 8 + read-write + 0 + 0xFF + + + PRI14 + Priority of interrupt 14 + 0 + 8 + read-write + + + + + NVICIP15 + Interrupt Priority Register n + 0x30F + 8 + read-write + 0 + 0xFF + + + PRI15 + Priority of interrupt 15 + 0 + 8 + read-write + + + + + NVICIP16 + Interrupt Priority Register n + 0x310 + 8 + read-write + 0 + 0xFF + + + PRI16 + Priority of interrupt 16 + 0 + 8 + read-write + + + + + NVICIP17 + Interrupt Priority Register n + 0x311 + 8 + read-write + 0 + 0xFF + + + PRI17 + Priority of interrupt 17 + 0 + 8 + read-write + + + + + NVICIP18 + Interrupt Priority Register n + 0x312 + 8 + read-write + 0 + 0xFF + + + PRI18 + Priority of interrupt 18 + 0 + 8 + read-write + + + + + NVICIP19 + Interrupt Priority Register n + 0x313 + 8 + read-write + 0 + 0xFF + + + PRI19 + Priority of interrupt 19 + 0 + 8 + read-write + + + + + NVICIP20 + Interrupt Priority Register n + 0x314 + 8 + read-write + 0 + 0xFF + + + PRI20 + Priority of interrupt 20 + 0 + 8 + read-write + + + + + NVICIP21 + Interrupt Priority Register n + 0x315 + 8 + read-write + 0 + 0xFF + + + PRI21 + Priority of interrupt 21 + 0 + 8 + read-write + + + + + NVICIP22 + Interrupt Priority Register n + 0x316 + 8 + read-write + 0 + 0xFF + + + PRI22 + Priority of interrupt 22 + 0 + 8 + read-write + + + + + NVICIP23 + Interrupt Priority Register n + 0x317 + 8 + read-write + 0 + 0xFF + + + PRI23 + Priority of interrupt 23 + 0 + 8 + read-write + + + + + NVICIP24 + Interrupt Priority Register n + 0x318 + 8 + read-write + 0 + 0xFF + + + PRI24 + Priority of interrupt 24 + 0 + 8 + read-write + + + + + NVICIP25 + Interrupt Priority Register n + 0x319 + 8 + read-write + 0 + 0xFF + + + PRI25 + Priority of interrupt 25 + 0 + 8 + read-write + + + + + NVICIP26 + Interrupt Priority Register n + 0x31A + 8 + read-write + 0 + 0xFF + + + PRI26 + Priority of interrupt 26 + 0 + 8 + read-write + + + + + NVICIP27 + Interrupt Priority Register n + 0x31B + 8 + read-write + 0 + 0xFF + + + PRI27 + Priority of interrupt 27 + 0 + 8 + read-write + + + + + NVICIP28 + Interrupt Priority Register n + 0x31C + 8 + read-write + 0 + 0xFF + + + PRI28 + Priority of interrupt 28 + 0 + 8 + read-write + + + + + NVICIP29 + Interrupt Priority Register n + 0x31D + 8 + read-write + 0 + 0xFF + + + PRI29 + Priority of interrupt 29 + 0 + 8 + read-write + + + + + NVICIP30 + Interrupt Priority Register n + 0x31E + 8 + read-write + 0 + 0xFF + + + PRI30 + Priority of interrupt 30 + 0 + 8 + read-write + + + + + NVICIP31 + Interrupt Priority Register n + 0x31F + 8 + read-write + 0 + 0xFF + + + PRI31 + Priority of interrupt 31 + 0 + 8 + read-write + + + + + NVICIP32 + Interrupt Priority Register n + 0x320 + 8 + read-write + 0 + 0xFF + + + PRI32 + Priority of interrupt 32 + 0 + 8 + read-write + + + + + NVICIP33 + Interrupt Priority Register n + 0x321 + 8 + read-write + 0 + 0xFF + + + PRI33 + Priority of interrupt 33 + 0 + 8 + read-write + + + + + NVICIP34 + Interrupt Priority Register n + 0x322 + 8 + read-write + 0 + 0xFF + + + PRI34 + Priority of interrupt 34 + 0 + 8 + read-write + + + + + NVICIP35 + Interrupt Priority Register n + 0x323 + 8 + read-write + 0 + 0xFF + + + PRI35 + Priority of interrupt 35 + 0 + 8 + read-write + + + + + NVICIP36 + Interrupt Priority Register n + 0x324 + 8 + read-write + 0 + 0xFF + + + PRI36 + Priority of interrupt 36 + 0 + 8 + read-write + + + + + NVICIP37 + Interrupt Priority Register n + 0x325 + 8 + read-write + 0 + 0xFF + + + PRI37 + Priority of interrupt 37 + 0 + 8 + read-write + + + + + NVICIP38 + Interrupt Priority Register n + 0x326 + 8 + read-write + 0 + 0xFF + + + PRI38 + Priority of interrupt 38 + 0 + 8 + read-write + + + + + NVICIP39 + Interrupt Priority Register n + 0x327 + 8 + read-write + 0 + 0xFF + + + PRI39 + Priority of interrupt 39 + 0 + 8 + read-write + + + + + NVICIP40 + Interrupt Priority Register n + 0x328 + 8 + read-write + 0 + 0xFF + + + PRI40 + Priority of interrupt 40 + 0 + 8 + read-write + + + + + NVICIP41 + Interrupt Priority Register n + 0x329 + 8 + read-write + 0 + 0xFF + + + PRI41 + Priority of interrupt 41 + 0 + 8 + read-write + + + + + NVICIP42 + Interrupt Priority Register n + 0x32A + 8 + read-write + 0 + 0xFF + + + PRI42 + Priority of interrupt 42 + 0 + 8 + read-write + + + + + NVICIP43 + Interrupt Priority Register n + 0x32B + 8 + read-write + 0 + 0xFF + + + PRI43 + Priority of interrupt 43 + 0 + 8 + read-write + + + + + NVICIP44 + Interrupt Priority Register n + 0x32C + 8 + read-write + 0 + 0xFF + + + PRI44 + Priority of interrupt 44 + 0 + 8 + read-write + + + + + NVICIP45 + Interrupt Priority Register n + 0x32D + 8 + read-write + 0 + 0xFF + + + PRI45 + Priority of interrupt 45 + 0 + 8 + read-write + + + + + NVICIP46 + Interrupt Priority Register n + 0x32E + 8 + read-write + 0 + 0xFF + + + PRI46 + Priority of interrupt 46 + 0 + 8 + read-write + + + + + NVICIP47 + Interrupt Priority Register n + 0x32F + 8 + read-write + 0 + 0xFF + + + PRI47 + Priority of interrupt 47 + 0 + 8 + read-write + + + + + NVICIP48 + Interrupt Priority Register n + 0x330 + 8 + read-write + 0 + 0xFF + + + PRI48 + Priority of interrupt 48 + 0 + 8 + read-write + + + + + NVICIP49 + Interrupt Priority Register n + 0x331 + 8 + read-write + 0 + 0xFF + + + PRI49 + Priority of interrupt 49 + 0 + 8 + read-write + + + + + NVICIP50 + Interrupt Priority Register n + 0x332 + 8 + read-write + 0 + 0xFF + + + PRI50 + Priority of interrupt 50 + 0 + 8 + read-write + + + + + NVICIP51 + Interrupt Priority Register n + 0x333 + 8 + read-write + 0 + 0xFF + + + PRI51 + Priority of interrupt 51 + 0 + 8 + read-write + + + + + NVICIP52 + Interrupt Priority Register n + 0x334 + 8 + read-write + 0 + 0xFF + + + PRI52 + Priority of interrupt 52 + 0 + 8 + read-write + + + + + NVICIP53 + Interrupt Priority Register n + 0x335 + 8 + read-write + 0 + 0xFF + + + PRI53 + Priority of interrupt 53 + 0 + 8 + read-write + + + + + NVICIP54 + Interrupt Priority Register n + 0x336 + 8 + read-write + 0 + 0xFF + + + PRI54 + Priority of interrupt 54 + 0 + 8 + read-write + + + + + NVICIP55 + Interrupt Priority Register n + 0x337 + 8 + read-write + 0 + 0xFF + + + PRI55 + Priority of interrupt 55 + 0 + 8 + read-write + + + + + NVICIP56 + Interrupt Priority Register n + 0x338 + 8 + read-write + 0 + 0xFF + + + PRI56 + Priority of interrupt 56 + 0 + 8 + read-write + + + + + NVICIP57 + Interrupt Priority Register n + 0x339 + 8 + read-write + 0 + 0xFF + + + PRI57 + Priority of interrupt 57 + 0 + 8 + read-write + + + + + NVICIP58 + Interrupt Priority Register n + 0x33A + 8 + read-write + 0 + 0xFF + + + PRI58 + Priority of interrupt 58 + 0 + 8 + read-write + + + + + NVICIP59 + Interrupt Priority Register n + 0x33B + 8 + read-write + 0 + 0xFF + + + PRI59 + Priority of interrupt 59 + 0 + 8 + read-write + + + + + NVICIP60 + Interrupt Priority Register n + 0x33C + 8 + read-write + 0 + 0xFF + + + PRI60 + Priority of interrupt 60 + 0 + 8 + read-write + + + + + NVICIP61 + Interrupt Priority Register n + 0x33D + 8 + read-write + 0 + 0xFF + + + PRI61 + Priority of interrupt 61 + 0 + 8 + read-write + + + + + NVICIP62 + Interrupt Priority Register n + 0x33E + 8 + read-write + 0 + 0xFF + + + PRI62 + Priority of interrupt 62 + 0 + 8 + read-write + + + + + NVICIP63 + Interrupt Priority Register n + 0x33F + 8 + read-write + 0 + 0xFF + + + PRI63 + Priority of interrupt 63 + 0 + 8 + read-write + + + + + NVICIP64 + Interrupt Priority Register n + 0x340 + 8 + read-write + 0 + 0xFF + + + PRI64 + Priority of interrupt 64 + 0 + 8 + read-write + + + + + NVICIP65 + Interrupt Priority Register n + 0x341 + 8 + read-write + 0 + 0xFF + + + PRI65 + Priority of interrupt 65 + 0 + 8 + read-write + + + + + NVICIP66 + Interrupt Priority Register n + 0x342 + 8 + read-write + 0 + 0xFF + + + PRI66 + Priority of interrupt 66 + 0 + 8 + read-write + + + + + NVICIP67 + Interrupt Priority Register n + 0x343 + 8 + read-write + 0 + 0xFF + + + PRI67 + Priority of interrupt 67 + 0 + 8 + read-write + + + + + NVICIP68 + Interrupt Priority Register n + 0x344 + 8 + read-write + 0 + 0xFF + + + PRI68 + Priority of interrupt 68 + 0 + 8 + read-write + + + + + NVICIP69 + Interrupt Priority Register n + 0x345 + 8 + read-write + 0 + 0xFF + + + PRI69 + Priority of interrupt 69 + 0 + 8 + read-write + + + + + NVICIP70 + Interrupt Priority Register n + 0x346 + 8 + read-write + 0 + 0xFF + + + PRI70 + Priority of interrupt 70 + 0 + 8 + read-write + + + + + NVICIP71 + Interrupt Priority Register n + 0x347 + 8 + read-write + 0 + 0xFF + + + PRI71 + Priority of interrupt 71 + 0 + 8 + read-write + + + + + NVICIP72 + Interrupt Priority Register n + 0x348 + 8 + read-write + 0 + 0xFF + + + PRI72 + Priority of interrupt 72 + 0 + 8 + read-write + + + + + NVICIP73 + Interrupt Priority Register n + 0x349 + 8 + read-write + 0 + 0xFF + + + PRI73 + Priority of interrupt 73 + 0 + 8 + read-write + + + + + NVICIP74 + Interrupt Priority Register n + 0x34A + 8 + read-write + 0 + 0xFF + + + PRI74 + Priority of interrupt 74 + 0 + 8 + read-write + + + + + NVICIP75 + Interrupt Priority Register n + 0x34B + 8 + read-write + 0 + 0xFF + + + PRI75 + Priority of interrupt 75 + 0 + 8 + read-write + + + + + NVICIP76 + Interrupt Priority Register n + 0x34C + 8 + read-write + 0 + 0xFF + + + PRI76 + Priority of interrupt 76 + 0 + 8 + read-write + + + + + NVICIP77 + Interrupt Priority Register n + 0x34D + 8 + read-write + 0 + 0xFF + + + PRI77 + Priority of interrupt 77 + 0 + 8 + read-write + + + + + NVICIP78 + Interrupt Priority Register n + 0x34E + 8 + read-write + 0 + 0xFF + + + PRI78 + Priority of interrupt 78 + 0 + 8 + read-write + + + + + NVICIP79 + Interrupt Priority Register n + 0x34F + 8 + read-write + 0 + 0xFF + + + PRI79 + Priority of interrupt 79 + 0 + 8 + read-write + + + + + NVICIP80 + Interrupt Priority Register n + 0x350 + 8 + read-write + 0 + 0xFF + + + PRI80 + Priority of interrupt 80 + 0 + 8 + read-write + + + + + NVICIP81 + Interrupt Priority Register n + 0x351 + 8 + read-write + 0 + 0xFF + + + PRI81 + Priority of interrupt 81 + 0 + 8 + read-write + + + + + NVICIP82 + Interrupt Priority Register n + 0x352 + 8 + read-write + 0 + 0xFF + + + PRI82 + Priority of interrupt 82 + 0 + 8 + read-write + + + + + NVICIP83 + Interrupt Priority Register n + 0x353 + 8 + read-write + 0 + 0xFF + + + PRI83 + Priority of interrupt 83 + 0 + 8 + read-write + + + + + NVICIP84 + Interrupt Priority Register n + 0x354 + 8 + read-write + 0 + 0xFF + + + PRI84 + Priority of interrupt 84 + 0 + 8 + read-write + + + + + NVICIP85 + Interrupt Priority Register n + 0x355 + 8 + read-write + 0 + 0xFF + + + PRI85 + Priority of interrupt 85 + 0 + 8 + read-write + + + + + NVICIP86 + Interrupt Priority Register n + 0x356 + 8 + read-write + 0 + 0xFF + + + PRI86 + Priority of interrupt 86 + 0 + 8 + read-write + + + + + NVICIP87 + Interrupt Priority Register n + 0x357 + 8 + read-write + 0 + 0xFF + + + PRI87 + Priority of interrupt 87 + 0 + 8 + read-write + + + + + NVICIP88 + Interrupt Priority Register n + 0x358 + 8 + read-write + 0 + 0xFF + + + PRI88 + Priority of interrupt 88 + 0 + 8 + read-write + + + + + NVICIP89 + Interrupt Priority Register n + 0x359 + 8 + read-write + 0 + 0xFF + + + PRI89 + Priority of interrupt 89 + 0 + 8 + read-write + + + + + NVICIP90 + Interrupt Priority Register n + 0x35A + 8 + read-write + 0 + 0xFF + + + PRI90 + Priority of interrupt 90 + 0 + 8 + read-write + + + + + NVICIP91 + Interrupt Priority Register n + 0x35B + 8 + read-write + 0 + 0xFF + + + PRI91 + Priority of interrupt 91 + 0 + 8 + read-write + + + + + NVICIP92 + Interrupt Priority Register n + 0x35C + 8 + read-write + 0 + 0xFF + + + PRI92 + Priority of interrupt 92 + 0 + 8 + read-write + + + + + NVICIP93 + Interrupt Priority Register n + 0x35D + 8 + read-write + 0 + 0xFF + + + PRI93 + Priority of interrupt 93 + 0 + 8 + read-write + + + + + NVICIP94 + Interrupt Priority Register n + 0x35E + 8 + read-write + 0 + 0xFF + + + PRI94 + Priority of interrupt 94 + 0 + 8 + read-write + + + + + NVICIP95 + Interrupt Priority Register n + 0x35F + 8 + read-write + 0 + 0xFF + + + PRI95 + Priority of interrupt 95 + 0 + 8 + read-write + + + + + NVICIP96 + Interrupt Priority Register n + 0x360 + 8 + read-write + 0 + 0xFF + + + PRI96 + Priority of interrupt 96 + 0 + 8 + read-write + + + + + NVICIP97 + Interrupt Priority Register n + 0x361 + 8 + read-write + 0 + 0xFF + + + PRI97 + Priority of interrupt 97 + 0 + 8 + read-write + + + + + NVICIP98 + Interrupt Priority Register n + 0x362 + 8 + read-write + 0 + 0xFF + + + PRI98 + Priority of interrupt 98 + 0 + 8 + read-write + + + + + NVICIP99 + Interrupt Priority Register n + 0x363 + 8 + read-write + 0 + 0xFF + + + PRI99 + Priority of interrupt 99 + 0 + 8 + read-write + + + + + NVICIP100 + Interrupt Priority Register n + 0x364 + 8 + read-write + 0 + 0xFF + + + PRI100 + Priority of interrupt 100 + 0 + 8 + read-write + + + + + NVICIP101 + Interrupt Priority Register n + 0x365 + 8 + read-write + 0 + 0xFF + + + PRI101 + Priority of interrupt 101 + 0 + 8 + read-write + + + + + NVICIP102 + Interrupt Priority Register n + 0x366 + 8 + read-write + 0 + 0xFF + + + PRI102 + Priority of interrupt 102 + 0 + 8 + read-write + + + + + NVICIP103 + Interrupt Priority Register n + 0x367 + 8 + read-write + 0 + 0xFF + + + PRI103 + Priority of interrupt 103 + 0 + 8 + read-write + + + + + NVICIP104 + Interrupt Priority Register n + 0x368 + 8 + read-write + 0 + 0xFF + + + PRI104 + Priority of interrupt 104 + 0 + 8 + read-write + + + + + NVICIP105 + Interrupt Priority Register n + 0x369 + 8 + read-write + 0 + 0xFF + + + PRI105 + Priority of interrupt 105 + 0 + 8 + read-write + + + + + NVICSTIR + Software Trigger Interrupt Register + 0xE00 + 32 + read-write + 0 + 0xFFFFFFFF + + + INTID + Interrupt ID of the interrupt to trigger, in the range 0-239. For example, a value of 0x03 specifies interrupt IRQ3. + 0 + 9 + read-write + + + + + \ No newline at end of file diff --git a/ext/hal/nxp/mcux/devices/LPC54114/LPC54114_cm4_features.h b/ext/hal/nxp/mcux/devices/LPC54114/LPC54114_cm4_features.h index fd3dae5f95e..4dc17f59c2b 100644 --- a/ext/hal/nxp/mcux/devices/LPC54114/LPC54114_cm4_features.h +++ b/ext/hal/nxp/mcux/devices/LPC54114/LPC54114_cm4_features.h @@ -1,37 +1,15 @@ /* ** ################################################################### ** Version: rev. 1.0, 2016-05-09 -** Build: b161227 +** Build: b180806 ** ** Abstract: ** Chip specific module features. ** -** Copyright (c) 2016 Freescale Semiconductor, Inc. -** Copyright 2016 - 2017 NXP -** Redistribution and use in source and binary forms, with or without modification, -** are permitted provided that the following conditions are met: +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2018 NXP ** -** o Redistributions of source code must retain the above copyright notice, this list -** of conditions and the following disclaimer. -** -** o Redistributions in binary form must reproduce the above copyright notice, this -** list of conditions and the following disclaimer in the documentation and/or -** other materials provided with the distribution. -** -** o Neither the name of the copyright holder nor the names of its -** contributors may be used to endorse or promote products derived from this -** software without specific prior written permission. -** -** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** SPDX-License-Identifier: BSD-3-Clause ** ** http: www.nxp.com ** mail: support@nxp.com @@ -54,6 +32,8 @@ #define FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT (1) /* @brief CRC availability on the SoC. */ #define FSL_FEATURE_SOC_CRC_COUNT (1) +/* @brief CTIMER availability on the SoC. */ +#define FSL_FEATURE_SOC_CTIMER_COUNT (5) /* @brief DMA availability on the SoC. */ #define FSL_FEATURE_SOC_DMA_COUNT (1) /* @brief DMIC availability on the SoC. */ @@ -88,8 +68,6 @@ #define FSL_FEATURE_SOC_SPIFI_COUNT (1) /* @brief SYSCON availability on the SoC. */ #define FSL_FEATURE_SOC_SYSCON_COUNT (1) -/* @brief CTIMER availability on the SoC. */ -#define FSL_FEATURE_SOC_CTIMER_COUNT (5) /* @brief USART availability on the SoC. */ #define FSL_FEATURE_SOC_USART_COUNT (8) /* @brief USB availability on the SoC. */ @@ -99,16 +77,118 @@ /* @brief WWDT availability on the SoC. */ #define FSL_FEATURE_SOC_WWDT_COUNT (1) +/* ADC module features */ + +/* @brief Do not has input select (register INSEL). */ +#define FSL_FEATURE_ADC_HAS_NO_INSEL (0) +/* @brief Has ASYNMODE bitfile in CTRL reigster. */ +#define FSL_FEATURE_ADC_HAS_CTRL_ASYNMODE (1) +/* @brief Has ASYNMODE bitfile in CTRL reigster. */ +#define FSL_FEATURE_ADC_HAS_CTRL_RESOL (1) +/* @brief Has ASYNMODE bitfile in CTRL reigster. */ +#define FSL_FEATURE_ADC_HAS_CTRL_BYPASSCAL (1) +/* @brief Has ASYNMODE bitfile in CTRL reigster. */ +#define FSL_FEATURE_ADC_HAS_CTRL_TSAMP (1) +/* @brief Has ASYNMODE bitfile in CTRL reigster. */ +#define FSL_FEATURE_ADC_HAS_CTRL_LPWRMODE (0) +/* @brief Has ASYNMODE bitfile in CTRL reigster. */ +#define FSL_FEATURE_ADC_HAS_CTRL_CALMODE (0) +/* @brief Has startup register. */ +#define FSL_FEATURE_ADC_HAS_STARTUP_REG (1) +/* @brief Has ADTrim register */ +#define FSL_FEATURE_ADC_HAS_TRIM_REG (0) +/* @brief Has Calibration register. */ +#define FSL_FEATURE_ADC_HAS_CALIB_REG (1) + /* DMA module features */ /* @brief Number of channels */ #define FSL_FEATURE_DMA_NUMBER_OF_CHANNELS (20) +/* FLEXCOMM module features */ + +/* @brief FLEXCOMM0 USART INDEX 0 */ +#define FSL_FEATURE_FLEXCOMM0_USART_INDEX (0) +/* @brief FLEXCOMM0 SPI INDEX 0 */ +#define FSL_FEATURE_FLEXCOMM0_SPI_INDEX (0) +/* @brief FLEXCOMM0 I2C INDEX 0 */ +#define FSL_FEATURE_FLEXCOMM0_I2C_INDEX (0) +/* @brief FLEXCOMM1 USART INDEX 1 */ +#define FSL_FEATURE_FLEXCOMM1_USART_INDEX (1) +/* @brief FLEXCOMM1 SPI INDEX 1 */ +#define FSL_FEATURE_FLEXCOMM1_SPI_INDEX (1) +/* @brief FLEXCOMM1 I2C INDEX 1 */ +#define FSL_FEATURE_FLEXCOMM1_I2C_INDEX (1) +/* @brief FLEXCOMM2 USART INDEX 2 */ +#define FSL_FEATURE_FLEXCOMM2_USART_INDEX (2) +/* @brief FLEXCOMM2 SPI INDEX 2 */ +#define FSL_FEATURE_FLEXCOMM2_SPI_INDEX (2) +/* @brief FLEXCOMM2 I2C INDEX 2 */ +#define FSL_FEATURE_FLEXCOMM2_I2C_INDEX (2) +/* @brief FLEXCOMM3 USART INDEX 3 */ +#define FSL_FEATURE_FLEXCOMM3_USART_INDEX (3) +/* @brief FLEXCOMM3 SPI INDEX 3 */ +#define FSL_FEATURE_FLEXCOMM3_SPI_INDEX (3) +/* @brief FLEXCOMM3 I2C INDEX 3 */ +#define FSL_FEATURE_FLEXCOMM3_I2C_INDEX (3) +/* @brief FLEXCOMM4 USART INDEX 4 */ +#define FSL_FEATURE_FLEXCOMM4_USART_INDEX (4) +/* @brief FLEXCOMM4 SPI INDEX 4 */ +#define FSL_FEATURE_FLEXCOMM4_SPI_INDEX (4) +/* @brief FLEXCOMM4 I2C INDEX 4 */ +#define FSL_FEATURE_FLEXCOMM4_I2C_INDEX (4) +/* @brief FLEXCOMM5 USART INDEX 5 */ +#define FSL_FEATURE_FLEXCOMM5_USART_INDEX (5) +/* @brief FLEXCOMM5 SPI INDEX 5 */ +#define FSL_FEATURE_FLEXCOMM5_SPI_INDEX (5) +/* @brief FLEXCOMM5 I2C INDEX 5 */ +#define FSL_FEATURE_FLEXCOMM5_I2C_INDEX (5) +/* @brief FLEXCOMM6 USART INDEX 6 */ +#define FSL_FEATURE_FLEXCOMM6_USART_INDEX (6) +/* @brief FLEXCOMM6 SPI INDEX 6 */ +#define FSL_FEATURE_FLEXCOMM6_SPI_INDEX (6) +/* @brief FLEXCOMM6 I2C INDEX 6 */ +#define FSL_FEATURE_FLEXCOMM6_I2C_INDEX (6) +/* @brief FLEXCOMM7 I2S INDEX 0 */ +#define FSL_FEATURE_FLEXCOMM6_I2S_INDEX (0) +/* @brief FLEXCOMM7 USART INDEX 7 */ +#define FSL_FEATURE_FLEXCOMM7_USART_INDEX (7) +/* @brief FLEXCOMM7 SPI INDEX 7 */ +#define FSL_FEATURE_FLEXCOMM7_SPI_INDEX (7) +/* @brief FLEXCOMM7 I2C INDEX 7 */ +#define FSL_FEATURE_FLEXCOMM7_I2C_INDEX (7) +/* @brief FLEXCOMM7 I2S INDEX 1 */ +#define FSL_FEATURE_FLEXCOMM7_I2S_INDEX (1) + +/* MAILBOX module features */ + +/* @brief Mailbox side for current core */ +#define FSL_FEATURE_MAILBOX_SIDE_A (1) +/* @brief Mailbox has no reset control */ +#define FSL_FEATURE_MAILBOX_HAS_NO_RESET (1) + +/* MRT module features */ + +/* @brief number of channels. */ +#define FSL_FEATURE_MRT_NUMBER_OF_CHANNELS (4) + +/* interrupt module features */ + +/* @brief Lowest interrupt request number. */ +#define FSL_FEATURE_INTERRUPT_IRQ_MIN (-14) +/* @brief Highest interrupt request number. */ +#define FSL_FEATURE_INTERRUPT_IRQ_MAX (105) + /* PINT module features */ /* @brief Number of connected outputs */ #define FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS (8) +/* RTC module features */ + +/* @brief RTC has no reset control */ +#define FSL_FEATURE_RTC_HAS_NO_RESET (1) + /* SCT module features */ /* @brief Number of events */ @@ -117,6 +197,8 @@ #define FSL_FEATURE_SCT_NUMBER_OF_STATES (10) /* @brief Number of match capture */ #define FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE (10) +/* @brief Number of outputs */ +#define FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS (8) /* SYSCON module features */ @@ -128,6 +210,24 @@ #define FSL_FEATURE_SYSCON_FLASH_SECTOR_SIZE_BYTES (32768) /* @brief Flash size in bytes */ #define FSL_FEATURE_SYSCON_FLASH_SIZE_BYTES (262144) +/* @brief IAP has Flash read & write function */ +#define FSL_FEATURE_IAP_HAS_FLASH_FUNCTION (1) +/* @brief IAP has read Flash signature function */ +#define FSL_FEATURE_IAP_HAS_FLASH_SIGNATURE_READ (1) +/* @brief IAP has read extended Flash signature function */ +#define FSL_FEATURE_IAP_HAS_FLASH_EXTENDED_SIGNATURE_READ (0) + +/* SysTick module features */ + +/* @brief Systick has external reference clock. */ +#define FSL_FEATURE_SYSTICK_HAS_EXT_REF (0) +/* @brief Systick external reference clock is core clock divided by this value. */ +#define FSL_FEATURE_SYSTICK_EXT_REF_CORE_DIV (0) + +/* USB module features */ + +/* @brief Number of the endpoint in USB FS */ +#define FSL_FEATURE_USB_EP_NUM (5) #endif /* _LPC54114_cm4_FEATURES_H_ */ diff --git a/ext/hal/nxp/mcux/devices/LPC54114/fsl_clock.c b/ext/hal/nxp/mcux/devices/LPC54114/fsl_clock.c index 78d3ffe2299..82af60147bb 100644 --- a/ext/hal/nxp/mcux/devices/LPC54114/fsl_clock.c +++ b/ext/hal/nxp/mcux/devices/LPC54114/fsl_clock.c @@ -1,32 +1,10 @@ /* * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright (c) 2016 - 2017 , NXP + * Copyright (c) 2016 - 2018 , NXP * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * SPDX-License-Identifier: BSD-3-Clause */ #include "fsl_common.h" @@ -35,6 +13,10 @@ /******************************************************************************* * Definitions ******************************************************************************/ +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.clock" +#endif #define NVALMAX (0x100U) #define PVALMAX (0x20U) #define MVALMAX (0x8000U) @@ -86,12 +68,13 @@ computation on each call to retrive the PLL rate. */ static uint32_t s_Pll_Freq; -uint32_t g_I2S_Mclk_Freq = 0U; +/* I2S mclk. */ +static uint32_t s_I2S_Mclk_Freq = 0U; /** External clock rate on the CLKIN pin in Hz. If not used, set this to 0. Otherwise, set it to the exact rate in Hz this pin is being driven at. */ -const uint32_t g_Ext_Clk_Freq = 0U; +static const uint32_t s_Ext_Clk_Freq = 0U; /******************************************************************************* * Variables @@ -134,39 +117,104 @@ static const uint8_t wdtFreqLookup[32] = {0, 8, 12, 15, 18, 20, 24, 26, 28, 30 * Code ******************************************************************************/ +/** + * brief Configure the clock selection muxes. + * param connection : Clock to be configured. + * return Nothing + */ void CLOCK_AttachClk(clock_attach_id_t connection) { - bool final_descriptor = false; uint8_t mux; - uint8_t pos; + uint8_t sel; + uint16_t item; uint32_t i; volatile uint32_t *pClkSel; pClkSel = &(SYSCON->MAINCLKSELA); - for (i = 0U; (i <= 2U) && (!final_descriptor); i++) + if (connection != kNONE_to_NONE) { - connection = (clock_attach_id_t)(connection >> (i * 12U)); /* pick up next descriptor */ - mux = (uint8_t)connection; - if (connection) + for (i = 0U; i < 2U; i++) { - pos = ((connection & 0xf00U) >> 8U) - 1U; - if (mux == CM_ASYNCAPB) + if (connection == 0U) { - ASYNC_SYSCON->ASYNCAPBCLKSELA = pos; + break; } - else + item = (uint16_t)GET_ID_ITEM(connection); + if (item) { - pClkSel[mux] = pos; + mux = GET_ID_ITEM_MUX(item); + sel = GET_ID_ITEM_SEL(item); + if (mux == CM_ASYNCAPB) + { + ASYNC_SYSCON->ASYNCAPBCLKSELA = sel; + } + else + { + pClkSel[mux] = sel; + } } - } - else - { - final_descriptor = true; + connection = GET_ID_NEXT_ITEM(connection); /* pick up next descriptor */ } } } +/* Return the actual clock attach id */ +/** + * brief Get the actual clock attach id. + * This fuction uses the offset in input attach id, then it reads the actual source value in + * the register and combine the offset to obtain an actual attach id. + * param attachId : Clock attach id to get. + * return Clock source value. + */ +clock_attach_id_t CLOCK_GetClockAttachId(clock_attach_id_t attachId) +{ + uint8_t mux; + uint8_t actualSel; + uint32_t i; + uint32_t actualAttachId = 0U; + uint32_t selector = GET_ID_SELECTOR(attachId); + volatile uint32_t *pClkSel; + + pClkSel = &(SYSCON->MAINCLKSELA); + + if (attachId == kNONE_to_NONE) + { + return kNONE_to_NONE; + } + + for (i = 0U; i < 2U; i++) + { + mux = GET_ID_ITEM_MUX(attachId); + if (attachId) + { + if (mux == CM_ASYNCAPB) + { + actualSel = ASYNC_SYSCON->ASYNCAPBCLKSELA; + } + else + { + actualSel = pClkSel[mux]; + } + + /* Consider the combination of two registers */ + actualAttachId |= CLK_ATTACH_ID(mux, actualSel, i); + } + attachId = GET_ID_NEXT_ITEM(attachId); /*!< pick up next descriptor */ + } + + actualAttachId |= selector; + + return (clock_attach_id_t)actualAttachId; +} + +/** + * brief Setup peripheral clock dividers. + * param div_name : Clock divider name + * param divided_by_value: Value to be divided + * param reset : Whether to reset the divider counter. + * return Nothing + */ void CLOCK_SetClkDiv(clock_div_name_t div_name, uint32_t divided_by_value, bool reset) { volatile uint32_t *pClkDiv; @@ -187,6 +235,13 @@ void CLOCK_SetClkDiv(clock_div_name_t div_name, uint32_t divided_by_value, bool } /* Set FRO Clocking */ +/** + * brief Initialize the Core clock to given frequency (12, 48 or 96 MHz). + * Turns on FRO and uses default CCO, if freq is 12000000, then high speed output is off, else high speed output is + * enabled. + * param iFreq : Desired frequency (must be one of CLK_FRO_12MHZ or CLK_FRO_48MHZ or CLK_FRO_96MHZ) + * return returns success or fail status. + */ status_t CLOCK_SetupFROClocking(uint32_t iFreq) { uint32_t usb_adj; @@ -221,15 +276,24 @@ status_t CLOCK_SetupFROClocking(uint32_t iFreq) return 0U; } +/*! brief Return Frequency of FRO 12MHz + * return Frequency of FRO 12MHz + */ uint32_t CLOCK_GetFro12MFreq(void) { return (SYSCON->PDRUNCFG[0] & SYSCON_PDRUNCFG_PDEN_FRO_MASK) ? 0U : 12000000U; } +/*! brief Return Frequency of External Clock + * return Frequency of External Clock. If no external clock is used returns 0. + */ uint32_t CLOCK_GetExtClkFreq(void) { - return (g_Ext_Clk_Freq); + return (s_Ext_Clk_Freq); } +/*! brief Return Frequency of Watchdog Oscillator + * return Frequency of Watchdog Oscillator + */ uint32_t CLOCK_GetWdtOscFreq(void) { uint8_t freq_sel, div_sel; @@ -246,42 +310,97 @@ uint32_t CLOCK_GetWdtOscFreq(void) } } +/* Get HF FRO Clk */ +/*! brief Return Frequency of High-Freq output of FRO + * return Frequency of High-Freq output of FRO + */ uint32_t CLOCK_GetFroHfFreq(void) { - return (SYSCON->PDRUNCFG[0] & SYSCON_PDRUNCFG_PDEN_FRO_MASK) ? - 0 : - !(SYSCON->FROCTRL & SYSCON_FROCTRL_HSPDCLK_MASK) ? 0 : (SYSCON->FROCTRL & SYSCON_FROCTRL_SEL_MASK) ? - 96000000U : - 48000000U; + if ((SYSCON->PDRUNCFG[0] & SYSCON_PDRUNCFG_PDEN_FRO_MASK) || !(SYSCON->FROCTRL & SYSCON_FROCTRL_HSPDCLK_MASK)) + { + return 0U; + } + + if (SYSCON->FROCTRL & SYSCON_FROCTRL_SEL_MASK) + { + return 96000000U; + } + else + { + return 48000000U; + } } +/*! brief Return Frequency of PLL + * return Frequency of PLL + */ uint32_t CLOCK_GetPllOutFreq(void) { return s_Pll_Freq; } +/*! brief Return Frequency of 32kHz osc + * return Frequency of 32kHz osc + */ uint32_t CLOCK_GetOsc32KFreq(void) { return CLK_RTC_32K_CLK; /* Needs to be corrected to check that RTC Clock is enabled */ } +/*! brief Return Frequency of Core System + * return Frequency of Core System + */ uint32_t CLOCK_GetCoreSysClkFreq(void) { - return ((SYSCON->MAINCLKSELB == 0U) && (SYSCON->MAINCLKSELA == 0U)) ? - CLOCK_GetFro12MFreq() : - ((SYSCON->MAINCLKSELB == 0U) && (SYSCON->MAINCLKSELA == 1U)) ? - CLOCK_GetExtClkFreq() : - ((SYSCON->MAINCLKSELB == 0U) && (SYSCON->MAINCLKSELA == 2U)) ? - CLOCK_GetWdtOscFreq() : - ((SYSCON->MAINCLKSELB == 0U) && (SYSCON->MAINCLKSELA == 3U)) ? - CLOCK_GetFroHfFreq() : - (SYSCON->MAINCLKSELB == 2U) ? CLOCK_GetPllOutFreq() : - (SYSCON->MAINCLKSELB == 3U) ? CLOCK_GetOsc32KFreq() : 0U; + uint32_t freq = 0U; + + switch (SYSCON->MAINCLKSELB) + { + case 0U: + if (SYSCON->MAINCLKSELA == 0U) + { + freq = CLOCK_GetFro12MFreq(); + } + else if (SYSCON->MAINCLKSELA == 1U) + { + freq = CLOCK_GetExtClkFreq(); + } + else if (SYSCON->MAINCLKSELA == 2U) + { + freq = CLOCK_GetWdtOscFreq(); + } + else if (SYSCON->MAINCLKSELA == 3U) + { + freq = CLOCK_GetFroHfFreq(); + } + else + { + } + break; + case 2U: + freq = CLOCK_GetPllOutFreq(); + break; + + case 3U: + freq = CLOCK_GetOsc32KFreq(); + break; + + default: + break; + } + + return freq; } +/*! brief Return Frequency of I2S MCLK Clock + * return Frequency of I2S MCLK Clock + */ uint32_t CLOCK_GetI2SMClkFreq(void) { - return g_I2S_Mclk_Freq; + return s_I2S_Mclk_Freq; } +/*! brief Return Frequency of Asynchronous APB Clock + * return Frequency of Asynchronous APB Clock Clock + */ uint32_t CLOCK_GetAsyncApbClkFreq(void) { async_clock_src_t clkSrc; @@ -305,26 +424,109 @@ uint32_t CLOCK_GetAsyncApbClkFreq(void) return clkRate; } +/* Get FLEXCOMM Clk */ +/*! brief Return Frequency of Flexcomm functional Clock + * return Frequency of Flexcomm functional Clock + */ uint32_t CLOCK_GetFlexCommClkFreq(uint32_t id) { - return (SYSCON->FXCOMCLKSEL[id] == 0U) ? CLOCK_GetFro12MFreq() : (SYSCON->FXCOMCLKSEL[id] == 1U) ? - CLOCK_GetFroHfFreq() : - (SYSCON->FXCOMCLKSEL[id] == 2U) ? - CLOCK_GetPllOutFreq() : - (SYSCON->FXCOMCLKSEL[id] == 3U) ? - CLOCK_GetI2SMClkFreq() : - (SYSCON->FXCOMCLKSEL[id] == 4U) ? CLOCK_GetFreq(kCLOCK_Frg) : 0U; + uint32_t freq = 0U; + + switch (SYSCON->FXCOMCLKSEL[id]) + { + case 0U: + freq = CLOCK_GetFro12MFreq(); + break; + case 1U: + freq = CLOCK_GetFroHfFreq(); + break; + case 2U: + freq = CLOCK_GetPllOutFreq(); + break; + case 3U: + freq = CLOCK_GetI2SMClkFreq(); + break; + case 4U: + freq = CLOCK_GetFrgClkFreq(); + break; + + default: + break; + } + + return freq; } +/* Get FRG Clk */ +/*! brief Return Input frequency for the Fractional baud rate generator + * return Input Frequency for FRG + */ uint32_t CLOCK_GetFRGInputClock(void) { - return (SYSCON->FRGCLKSEL == 0U) ? CLOCK_GetCoreSysClkFreq() : (SYSCON->FRGCLKSEL == 1U) ? - CLOCK_GetPllOutFreq() : - (SYSCON->FRGCLKSEL == 2U) ? CLOCK_GetFro12MFreq() : (SYSCON->FRGCLKSEL == 3U) ? - CLOCK_GetFroHfFreq() : - 0U; + uint32_t freq = 0U; + + switch (SYSCON->FRGCLKSEL) + { + case 0U: + freq = CLOCK_GetCoreSysClkFreq(); + break; + case 1U: + freq = CLOCK_GetPllOutFreq(); + break; + case 2U: + freq = CLOCK_GetFro12MFreq(); + break; + case 3U: + freq = CLOCK_GetFroHfFreq(); + break; + + default: + break; + } + + return freq; } +/* Get DMIC Clk */ +/*! brief Return Input frequency for the DMIC + * return Input Frequency for DMIC + */ +uint32_t CLOCK_GetDmicClkFreq(void) +{ + uint32_t freq = 0U; + + switch (SYSCON->DMICCLKSEL) + { + case 0U: + freq = CLOCK_GetFro12MFreq(); + break; + case 1U: + freq = CLOCK_GetFroHfFreq(); + break; + case 2U: + freq = CLOCK_GetPllOutFreq(); + break; + case 3U: + freq = CLOCK_GetI2SMClkFreq(); + break; + case 4U: + freq = CLOCK_GetCoreSysClkFreq(); + break; + case 5U: + freq = CLOCK_GetWdtOscFreq(); + break; + default: + break; + } + + return freq / ((SYSCON->DMICCLKDIV & 0xffU) + 1U); + ; +} + +/*! brief Set output of the Fractional baud rate generator + * param freq : Desired output frequency + * return Error Code 0 - fail 1 - success + */ uint32_t CLOCK_SetFRGClock(uint32_t freq) { uint32_t input = CLOCK_GetFRGInputClock(); @@ -343,6 +545,53 @@ uint32_t CLOCK_SetFRGClock(uint32_t freq) } } +/* Get FRG Clk */ +/*! brief Return Input frequency for the FRG + * return Input Frequency for FRG + */ +uint32_t CLOCK_GetFrgClkFreq(void) +{ + uint32_t freq = 0U; + + if ((SYSCON->FRGCTRL & SYSCON_FRGCTRL_DIV_MASK) == SYSCON_FRGCTRL_DIV_MASK) + { + freq = ((uint64_t)CLOCK_GetFRGInputClock() * (SYSCON_FRGCTRL_DIV_MASK + 1)) / + ((SYSCON_FRGCTRL_DIV_MASK + 1) + + ((SYSCON->FRGCTRL & SYSCON_FRGCTRL_MULT_MASK) >> SYSCON_FRGCTRL_MULT_SHIFT)); + } + else + { + freq = 0U; + } + + return freq; +} + +/*! brief Return Frequency of USB + * return Frequency of USB + */ +uint32_t CLOCK_GetUsbClkFreq(void) +{ + uint32_t freq = 0U; + + if (SYSCON->USBCLKSEL == 0U) + { + freq = CLOCK_GetFroHfFreq(); + } + else if (SYSCON->USBCLKSEL == 1) + { + freq = CLOCK_GetPllOutFreq(); + } + else + { + } + + return freq / ((SYSCON->USBCLKDIV & 0xffU) + 1U); +} + +/*! brief Return Frequency of selected clock + * return Frequency of selected clock + */ uint32_t CLOCK_GetFreq(clock_name_t clockName) { uint32_t freq; @@ -364,31 +613,16 @@ uint32_t CLOCK_GetFreq(clock_name_t clockName) freq = CLOCK_GetPllOutFreq(); break; case kCLOCK_UsbClk: - freq = (SYSCON->USBCLKSEL == 0U) ? CLOCK_GetFroHfFreq() : (SYSCON->USBCLKSEL == 1) ? CLOCK_GetPllOutFreq() : - 0U; - freq = freq / ((SYSCON->USBCLKDIV & 0xffU) + 1U); + freq = CLOCK_GetUsbClkFreq(); break; - case kClock_WdtOsc: + case kCLOCK_WdtOsc: freq = CLOCK_GetWdtOscFreq(); break; case kCLOCK_Frg: - freq = ((SYSCON->FRGCTRL & SYSCON_FRGCTRL_DIV_MASK) == SYSCON_FRGCTRL_DIV_MASK) ? - ((uint64_t)CLOCK_GetFRGInputClock() * (SYSCON_FRGCTRL_DIV_MASK + 1)) / - ((SYSCON_FRGCTRL_DIV_MASK + 1) + - ((SYSCON->FRGCTRL & SYSCON_FRGCTRL_MULT_MASK) >> SYSCON_FRGCTRL_MULT_SHIFT)) : - 0; + freq = CLOCK_GetFrgClkFreq(); break; case kCLOCK_Dmic: - freq = (SYSCON->DMICCLKSEL == 0U) ? CLOCK_GetFro12MFreq() : (SYSCON->DMICCLKSEL == 1U) ? - CLOCK_GetFroHfFreq() : - (SYSCON->DMICCLKSEL == 2U) ? - CLOCK_GetPllOutFreq() : - (SYSCON->DMICCLKSEL == 3U) ? - CLOCK_GetI2SMClkFreq() : - (SYSCON->DMICCLKSEL == 4U) ? - CLOCK_GetCoreSysClkFreq() : - (SYSCON->DMICCLKSEL == 5U) ? CLOCK_GetWdtOscFreq() : 0U; - freq = freq / ((SYSCON->DMICCLKDIV & 0xffU) + 1U); + freq = CLOCK_GetDmicClkFreq(); break; case kCLOCK_AsyncApbClk: @@ -432,6 +666,11 @@ uint32_t CLOCK_GetFreq(clock_name_t clockName) } /* Set the FLASH wait states for the passed frequency */ +/** + * brief Set the flash wait states for the input freuqency. + * param iFreq : Input frequency + * return Nothing + */ void CLOCK_SetFLASHAccessCyclesForFreq(uint32_t iFreq) { if (iFreq <= 12000000U) @@ -789,8 +1028,13 @@ static uint32_t FindGreatestCommonDivisor(uint32_t m, uint32_t n) return m; } -/* Set PLL output based on desired output rate */ -static pll_error_t CLOCK_GetPllConfig( +/* + * Set PLL output based on desired output rate. + * In this function, the it calculates the PLL setting for output frequency from input clock + * frequency. The calculation would cost a few time. So it is not recommaned to use it frequently. + * the "pllctrl", "pllndec", "pllpdec", "pllmdec" would updated in this function. + */ +static pll_error_t CLOCK_GetPllConfigInternal( uint32_t finHz, uint32_t foutHz, pll_setup_t *pSetup, bool useFeedbackDiv2, bool useSS) { uint32_t nDivOutHz, fccoHz, multFccoDiv; @@ -960,6 +1204,69 @@ static pll_error_t CLOCK_GetPllConfig( return kStatus_PLL_Success; } +#if (defined(CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT) && CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT) +/* Alloct the static buffer for cache. */ +static pll_setup_t s_PllSetupCacheStruct[CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT]; +static uint32_t s_FinHzCache[CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT] = {0}; +static uint32_t s_FoutHzCache[CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT] = {0}; +static bool s_UseFeedbackDiv2Cache[CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT] = {false}; +static bool s_UseSSCache[CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT] = {false}; +static uint32_t s_PllSetupCacheIdx = 0U; +#endif /* CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT */ + +/* + * Calculate the PLL setting values from input clock freq to output freq. + */ +static pll_error_t CLOCK_GetPllConfig( + uint32_t finHz, uint32_t foutHz, pll_setup_t *pSetup, bool useFeedbackDiv2, bool useSS) +{ + pll_error_t retErr; +#if (defined(CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT) && CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT) + uint32_t i; + + for (i = 0U; i < CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT; i++) + { + if ((finHz == s_FinHzCache[i]) && (foutHz == s_FoutHzCache[i]) && + (useFeedbackDiv2 == s_UseFeedbackDiv2Cache[i]) && (useSS == s_UseSSCache[i])) + { + /* Hit the target in cache buffer. */ + pSetup->syspllctrl = s_PllSetupCacheStruct[i].syspllctrl; + pSetup->syspllndec = s_PllSetupCacheStruct[i].syspllndec; + pSetup->syspllpdec = s_PllSetupCacheStruct[i].syspllpdec; + pSetup->syspllssctrl[0] = s_PllSetupCacheStruct[i].syspllssctrl[0]; + pSetup->syspllssctrl[1] = s_PllSetupCacheStruct[i].syspllssctrl[1]; + retErr = kStatus_PLL_Success; + break; + } + } + + if (i < CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT) + { + return retErr; + } +#endif /* CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT */ + + retErr = CLOCK_GetPllConfigInternal(finHz, foutHz, pSetup, useFeedbackDiv2, useSS); + +#if (defined(CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT) && CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT) + /* Cache the most recent calulation result into buffer. */ + s_FinHzCache[s_PllSetupCacheIdx] = finHz; + s_FoutHzCache[s_PllSetupCacheIdx] = foutHz; + s_UseFeedbackDiv2Cache[s_PllSetupCacheIdx] = useFeedbackDiv2; + s_UseSSCache[s_PllSetupCacheIdx] = useSS; + + s_PllSetupCacheStruct[s_PllSetupCacheIdx].syspllctrl = pSetup->syspllctrl; + s_PllSetupCacheStruct[s_PllSetupCacheIdx].syspllndec = pSetup->syspllndec; + s_PllSetupCacheStruct[s_PllSetupCacheIdx].syspllpdec = pSetup->syspllpdec; + s_PllSetupCacheStruct[s_PllSetupCacheIdx].syspllssctrl[0] = pSetup->syspllssctrl[0]; + s_PllSetupCacheStruct[s_PllSetupCacheIdx].syspllssctrl[1] = pSetup->syspllssctrl[1]; + /* Update the index for next available buffer. */ + s_PllSetupCacheIdx = (s_PllSetupCacheIdx + 1U) % CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT; +#endif /* CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT */ + + return retErr; +} + /* Update local PLL rate variable */ static void CLOCK_GetSystemPLLOutFromSetupUpdate(pll_setup_t *pSetup) { @@ -967,6 +1274,9 @@ static void CLOCK_GetSystemPLLOutFromSetupUpdate(pll_setup_t *pSetup) } /* Return System PLL input clock rate */ +/*! brief Return System PLL input clock rate + * return System PLL input clock rate + */ uint32_t CLOCK_GetSystemPLLInClockRate(void) { uint32_t clkRate = 0U; @@ -998,6 +1308,10 @@ uint32_t CLOCK_GetSystemPLLInClockRate(void) } /* Return System PLL output clock rate from setup structure */ +/*! brief Return System PLL output clock rate from setup structure + * param pSetup : Pointer to a PLL setup structure + * return System PLL output clock rate calculated from the setup structure + */ uint32_t CLOCK_GetSystemPLLOutFromSetup(pll_setup_t *pSetup) { uint32_t prediv, postdiv, mMult, inPllRate; @@ -1074,12 +1388,23 @@ uint32_t CLOCK_GetSystemPLLOutFromSetup(pll_setup_t *pSetup) } /* Set the current PLL Rate */ +/*! brief Store the current PLL rate + * param rate: Current rate of the PLL + * return Nothing + **/ void CLOCK_SetStoredPLLClockRate(uint32_t rate) { s_Pll_Freq = rate; } /* Return System PLL output clock rate */ +/*! brief Return System PLL output clock rate + * param recompute : Forces a PLL rate recomputation if true + * return System PLL output clock rate + * note The PLL rate is cached in the driver in a variable as + * the rate computation function can take some time to perform. It + * is recommended to use 'false' with the 'recompute' parameter. + */ uint32_t CLOCK_GetSystemPLLOutClockRate(bool recompute) { pll_setup_t Setup; @@ -1102,6 +1427,13 @@ uint32_t CLOCK_GetSystemPLLOutClockRate(bool recompute) } /* Set PLL output based on the passed PLL setup data */ +/*! brief Set PLL output based on the passed PLL setup data + * param pControl : Pointer to populated PLL control structure to generate setup with + * param pSetup : Pointer to PLL setup structure to be filled + * return PLL_ERROR_SUCCESS on success, or PLL setup error code + * note Actual frequency for setup may vary from the desired frequency based on the + * accuracy of input clocks, rounding, non-fractional PLL mode, etc. + */ pll_error_t CLOCK_SetupPLLData(pll_config_t *pControl, pll_setup_t *pSetup) { uint32_t inRate; @@ -1145,6 +1477,16 @@ pll_error_t CLOCK_SetupPLLData(pll_config_t *pControl, pll_setup_t *pSetup) } /* Set PLL output from PLL setup structure */ +/*! brief Set PLL output from PLL setup structure (precise frequency) + * param pSetup : Pointer to populated PLL setup structure +* param flagcfg : Flag configuration for PLL config structure + * return PLL_ERROR_SUCCESS on success, or PLL setup error code + * note This function will power off the PLL, setup the PLL with the + * new setup data, and then optionally powerup the PLL, wait for PLL lock, + * and adjust system voltages to the new PLL rate. The function will not + * alter any source clocks (ie, main systen clock) that may use the PLL, + * so these should be setup prior to and after exiting the function. + */ pll_error_t CLOCK_SetupSystemPLLPrec(pll_setup_t *pSetup, uint32_t flagcfg) { /* Power off PLL during setup changes */ @@ -1212,6 +1554,16 @@ pll_error_t CLOCK_SetupSystemPLLPrec(pll_setup_t *pSetup, uint32_t flagcfg) } /* Setup PLL Frequency from pre-calculated value */ +/** + * brief Set PLL output from PLL setup structure (precise frequency) + * param pSetup : Pointer to populated PLL setup structure + * return kStatus_PLL_Success on success, or PLL setup error code + * note This function will power off the PLL, setup the PLL with the + * new setup data, and then optionally powerup the PLL, wait for PLL lock, + * and adjust system voltages to the new PLL rate. The function will not + * alter any source clocks (ie, main systen clock) that may use the PLL, + * so these should be setup prior to and after exiting the function. + */ pll_error_t CLOCK_SetPLLFreq(const pll_setup_t *pSetup) { /* Power off PLL during setup changes */ @@ -1271,6 +1623,17 @@ pll_error_t CLOCK_SetPLLFreq(const pll_setup_t *pSetup) } /* Set System PLL clock based on the input frequency and multiplier */ +/*! brief Set PLL output based on the multiplier and input frequency + * param multiply_by : multiplier + * param input_freq : Clock input frequency of the PLL + * return Nothing + * note Unlike the Chip_Clock_SetupSystemPLLPrec() function, this + * function does not disable or enable PLL power, wait for PLL lock, + * or adjust system voltages. These must be done in the application. + * The function will not alter any source clocks (ie, main systen clock) + * that may use the PLL, so these should be setup prior to and after + * exiting the function. + */ void CLOCK_SetupSystemPLLMult(uint32_t multiply_by, uint32_t input_freq) { uint32_t cco_freq = input_freq * multiply_by; diff --git a/ext/hal/nxp/mcux/devices/LPC54114/fsl_clock.h b/ext/hal/nxp/mcux/devices/LPC54114/fsl_clock.h index 918085881b5..b6010f52b48 100644 --- a/ext/hal/nxp/mcux/devices/LPC54114/fsl_clock.h +++ b/ext/hal/nxp/mcux/devices/LPC54114/fsl_clock.h @@ -1,32 +1,10 @@ /* * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright (c) 2016 - 2017 , NXP + * Copyright (c) 2016 - 2018 , NXP * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name ofcopyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * SPDX-License-Identifier: BSD-3-Clause */ #ifndef _FSL_CLOCK_H_ @@ -45,6 +23,24 @@ /******************************************************************************* * Definitions *****************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief CLOCK driver version 2.0.5. */ +#define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 0, 5)) +/*@}*/ + +/*! + * @brief User-defined the size of cache for CLOCK_PllGetConfig() function. + * + * Once define this MACRO to be non-zero value, CLOCK_PllGetConfig() function + * would cache the recent calulation and accelerate the execution to get the + * right settings. + */ +#ifndef CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT +#define CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT 2U +#endif + /*! @brief Clock ip name array for FLEXCOMM. */ #define FLEXCOMM_CLOCKS \ { \ @@ -255,10 +251,10 @@ typedef enum _clock_name kCLOCK_ExtClk, /*!< External Clock */ kCLOCK_PllOut, /*!< PLL Output */ kCLOCK_UsbClk, /*!< USB input */ - kClock_WdtOsc, /*!< Watchdog Oscillator */ + kCLOCK_WdtOsc, /*!< Watchdog Oscillator */ kCLOCK_Frg, /*!< Frg Clock */ kCLOCK_Dmic, /*!< Digital Mic clock */ - kCLOCK_AsyncApbClk, /*!< Async APB clock */ + kCLOCK_AsyncApbClk, /*!< Async APB clock */ kCLOCK_FlexI2S, /*!< FlexI2S clock */ kCLOCK_Flexcomm0, /*!< Flexcomm0Clock */ kCLOCK_Flexcomm1, /*!< Flexcomm1Clock */ @@ -280,18 +276,22 @@ typedef enum _async_clock_src } async_clock_src_t; /*! @brief Clock Mux Switches -* The encoding is as follows each connection identified is 64bits wide +* The encoding is as follows each connection identified is 32bits wide while 24bits are valuable * starting from LSB upwards * -* [4 bits for choice, where 1 is A, 2 is B, 3 is C and 4 is D, 0 means end of descriptor] [8 bits mux ID]* +* [4 bits for choice, 0 means invalid choice] [8 bits mux ID]* * */ -#define MUX_A(m, choice) (((m) << 0) | ((choice + 1) << 8)) -#define MUX_B(m, choice) (((m) << 12) | ((choice + 1) << 20)) -#define MUX_C(m, choice) (((m) << 24) | ((choice + 1) << 32)) -#define MUX_D(m, choice) (((m) << 36) | ((choice + 1) << 44)) -#define MUX_E(m, choice) (((m) << 48) | ((choice + 1) << 56)) +#define CLK_ATTACH_ID(mux, sel, pos) (((mux << 0U) | ((sel + 1) & 0xFU) << 8U) << (pos * 12U)) +#define MUX_A(mux, sel) CLK_ATTACH_ID(mux, sel, 0U) +#define MUX_B(mux, sel, selector) (CLK_ATTACH_ID(mux, sel, 1U) | (selector << 24U)) + +#define GET_ID_ITEM(connection) ((connection)&0xFFFU) +#define GET_ID_NEXT_ITEM(connection) ((connection) >> 12U) +#define GET_ID_ITEM_MUX(connection) ((connection)&0xFFU) +#define GET_ID_ITEM_SEL(connection) ((((connection)&0xF00U) >> 8U) - 1U) +#define GET_ID_SELECTOR(connection) ((connection)&0xF000000U) #define CM_MAINCLKSELA 0 #define CM_MAINCLKSELB 1 @@ -327,12 +327,12 @@ typedef enum _async_clock_src typedef enum _clock_attach_id { - kFRO12M_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 0) | MUX_B(CM_MAINCLKSELB, 0), - kEXT_CLK_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 1) | MUX_B(CM_MAINCLKSELB, 0), - kWDT_OSC_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 2) | MUX_B(CM_MAINCLKSELB, 0), - kFRO_HF_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 3) | MUX_B(CM_MAINCLKSELB, 0), - kSYS_PLL_to_MAIN_CLK = MUX_A(CM_MAINCLKSELB, 2), - kOSC32K_to_MAIN_CLK = MUX_A(CM_MAINCLKSELB, 3), + kFRO12M_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 0) | MUX_B(CM_MAINCLKSELB, 0, 0), + kEXT_CLK_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 1) | MUX_B(CM_MAINCLKSELB, 0, 0), + kWDT_OSC_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 2) | MUX_B(CM_MAINCLKSELB, 0, 0), + kFRO_HF_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 3) | MUX_B(CM_MAINCLKSELB, 0, 0), + kSYS_PLL_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 0) | MUX_B(CM_MAINCLKSELB, 2, 0), + kOSC32K_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 0) | MUX_B(CM_MAINCLKSELB, 3, 0), kFRO12M_to_SYS_PLL = MUX_A(CM_SYSPLLCLKSEL, 0), kEXT_CLK_to_SYS_PLL = MUX_A(CM_SYSPLLCLKSEL, 1), @@ -417,6 +417,7 @@ typedef enum _clock_attach_id kFRO_HF_to_MCLK = MUX_A(CM_FXI2S0MCLKCLKSEL, 0), kSYS_PLL_to_MCLK = MUX_A(CM_FXI2S0MCLKCLKSEL, 1), + kMAIN_CLK_to_MCLK = MUX_A(CM_FXI2S0MCLKCLKSEL, 2), kNONE_to_MCLK = MUX_A(CM_FXI2S0MCLKCLKSEL, 7), kFRO12M_to_DMIC = MUX_A(CM_DMICCLKSEL, 0), @@ -440,7 +441,7 @@ typedef enum _clock_attach_id kFRO12M_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 5), kOSC32K_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 6), kNONE_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 7), - kNONE_to_NONE = 0x80000000U, + kNONE_to_NONE = (int)0x80000000U, } clock_attach_id_t; /* Clock dividers */ @@ -535,6 +536,14 @@ status_t CLOCK_SetupFROClocking(uint32_t iFreq); * @return Nothing */ void CLOCK_AttachClk(clock_attach_id_t connection); +/** + * @brief Get the actual clock attach id. + * This fuction uses the offset in input attach id, then it reads the actual source value in + * the register and combine the offset to obtain an actual attach id. + * @param attachId : Clock attach id to get. + * @return Clock source value. + */ +clock_attach_id_t CLOCK_GetClockAttachId(clock_attach_id_t attachId); /** * @brief Setup peripheral clock dividers. * @param div_name : Clock divider name @@ -559,6 +568,16 @@ uint32_t CLOCK_GetFreq(clock_name_t clockName); */ uint32_t CLOCK_GetFRGInputClock(void); +/*! @brief Return Input frequency for the DMIC + * @return Input Frequency for DMIC + */ +uint32_t CLOCK_GetDmicClkFreq(void); + +/*! @brief Return Input frequency for the FRG + * @return Input Frequency for FRG + */ +uint32_t CLOCK_GetFrgClkFreq(void); + /*! @brief Set output of the Fractional baud rate generator * @param freq : Desired output frequency * @return Error Code 0 - fail 1 - success @@ -581,6 +600,10 @@ uint32_t CLOCK_GetWdtOscFreq(void); * @return Frequency of High-Freq output of FRO */ uint32_t CLOCK_GetFroHfFreq(void); +/*! @brief Return Frequency of USB + * @return Frequency of USB + */ +uint32_t CLOCK_GetUsbClkFreq(void); /*! @brief Return Frequency of PLL * @return Frequency of PLL */ @@ -674,10 +697,12 @@ void CLOCK_SetStoredPLLClockRate(uint32_t rate); #define PLL_CONFIGFLAG_FORCENOFRACT \ (1 << 2) /*!< Force non-fractional output mode, PLL output will not use the fractional, automatic bandwidth, or SS \ \ \ \ - \ \ \ \ \ - \ \ \ \ \ \ \ + \ \ \ \ \ + \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ - hardware */ + \ \ \ \ \ \ \ \ \ \ \ + \ \ \ \ \ \ \ \ \ \ \ \ \ + hardware */ /*! @brief PLL Spread Spectrum (SS) Programmable modulation frequency * See (MF) field in the SYSPLLSSCTRL1 register in the UM. diff --git a/ext/hal/nxp/mcux/devices/LPC54114/fsl_device_registers.h b/ext/hal/nxp/mcux/devices/LPC54114/fsl_device_registers.h index 3670b4b941f..15d028b5fb7 100644 --- a/ext/hal/nxp/mcux/devices/LPC54114/fsl_device_registers.h +++ b/ext/hal/nxp/mcux/devices/LPC54114/fsl_device_registers.h @@ -1,30 +1,8 @@ /* - * Copyright (c) 2014 - 2016, Freescale Semiconductor, Inc. - * Copyright 2016 - 2017 NXP - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * Copyright 2014-2016 Freescale Semiconductor, Inc. + * Copyright 2016-2018 NXP * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * SPDX-License-Identifier: BSD-3-Clause * */ diff --git a/ext/hal/nxp/mcux/devices/LPC54114/system_LPC54114_cm0plus.c b/ext/hal/nxp/mcux/devices/LPC54114/system_LPC54114_cm0plus.c index d71293b58a7..9fc70088caa 100644 --- a/ext/hal/nxp/mcux/devices/LPC54114/system_LPC54114_cm0plus.c +++ b/ext/hal/nxp/mcux/devices/LPC54114/system_LPC54114_cm0plus.c @@ -10,39 +10,17 @@ ** ** Reference manual: LPC5411x User manual Rev. 1.1 25 May 2016 ** Version: rev. 1.0, 2016-04-29 -** Build: b161227 +** Build: b180802 ** ** Abstract: ** Provides a system configuration function and a global variable that ** contains the system frequency. It configures the device and initializes ** the oscillator (PLL) that is part of the microcontroller device. ** -** Copyright (c) 2016 Freescale Semiconductor, Inc. -** Copyright 2016 - 2017 NXP -** Redistribution and use in source and binary forms, with or without modification, -** are permitted provided that the following conditions are met: +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2018 NXP ** -** o Redistributions of source code must retain the above copyright notice, this list -** of conditions and the following disclaimer. -** -** o Redistributions in binary form must reproduce the above copyright notice, this -** list of conditions and the following disclaimer in the documentation and/or -** other materials provided with the distribution. -** -** o Neither the name of the copyright holder nor the names of its -** contributors may be used to endorse or promote products derived from this -** software without specific prior written permission. -** -** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** SPDX-License-Identifier: BSD-3-Clause ** ** http: www.nxp.com ** mail: support@nxp.com @@ -263,6 +241,7 @@ static uint32_t findPllMMult(uint32_t ctrlReg, uint32_t mDecReg) void SystemInit(void) { SCB->VTOR = (uint32_t)&__Vectors; + SystemInitHook(); } /* ---------------------------------------------------------------------------- @@ -350,3 +329,11 @@ void SystemCoreClockUpdate(void) } SystemCoreClock = clkRate / ((SYSCON->AHBCLKDIV & 0xFF) + 1); } + +/* ---------------------------------------------------------------------------- + -- SystemInitHook() + ---------------------------------------------------------------------------- */ + +__attribute__ ((weak)) void SystemInitHook (void) { + /* Void implementation of the weak function. */ +} diff --git a/ext/hal/nxp/mcux/devices/LPC54114/system_LPC54114_cm0plus.h b/ext/hal/nxp/mcux/devices/LPC54114/system_LPC54114_cm0plus.h index b8fc8d8d869..6eaacd58397 100644 --- a/ext/hal/nxp/mcux/devices/LPC54114/system_LPC54114_cm0plus.h +++ b/ext/hal/nxp/mcux/devices/LPC54114/system_LPC54114_cm0plus.h @@ -10,39 +10,17 @@ ** ** Reference manual: LPC5411x User manual Rev. 1.1 25 May 2016 ** Version: rev. 1.0, 2016-04-29 -** Build: b161227 +** Build: b180802 ** ** Abstract: ** Provides a system configuration function and a global variable that ** contains the system frequency. It configures the device and initializes ** the oscillator (PLL) that is part of the microcontroller device. ** -** Copyright (c) 2016 Freescale Semiconductor, Inc. -** Copyright 2016 - 2017 NXP -** Redistribution and use in source and binary forms, with or without modification, -** are permitted provided that the following conditions are met: +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2018 NXP ** -** o Redistributions of source code must retain the above copyright notice, this list -** of conditions and the following disclaimer. -** -** o Redistributions in binary form must reproduce the above copyright notice, this -** list of conditions and the following disclaimer in the documentation and/or -** other materials provided with the distribution. -** -** o Neither the name of the copyright holder nor the names of its -** contributors may be used to endorse or promote products derived from this -** software without specific prior written permission. -** -** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** SPDX-License-Identifier: BSD-3-Clause ** ** http: www.nxp.com ** mail: support@nxp.com @@ -112,6 +90,18 @@ void SystemInit (void); */ void SystemCoreClockUpdate (void); +/** + * @brief SystemInit function hook. + * + * This weak function allows to call specific initialization code during the + * SystemInit() execution.This can be used when an application specific code needs + * to be called as close to the reset entry as possible (for example the Multicore + * Manager MCMGR_EarlyInit() function call). + * NOTE: No global r/w variables can be used in this hook function because the + * initialization of these variables happens after this function. + */ +void SystemInitHook (void); + #ifdef __cplusplus } #endif diff --git a/ext/hal/nxp/mcux/devices/LPC54114/system_LPC54114_cm4.c b/ext/hal/nxp/mcux/devices/LPC54114/system_LPC54114_cm4.c index 650f89e1e4c..795c64fce6d 100644 --- a/ext/hal/nxp/mcux/devices/LPC54114/system_LPC54114_cm4.c +++ b/ext/hal/nxp/mcux/devices/LPC54114/system_LPC54114_cm4.c @@ -10,39 +10,17 @@ ** ** Reference manual: LPC5411x User manual Rev. 1.1 25 May 2016 ** Version: rev. 1.0, 2016-04-29 -** Build: b161227 +** Build: b180802 ** ** Abstract: ** Provides a system configuration function and a global variable that ** contains the system frequency. It configures the device and initializes ** the oscillator (PLL) that is part of the microcontroller device. ** -** Copyright (c) 2016 Freescale Semiconductor, Inc. -** Copyright 2016 - 2017 NXP -** Redistribution and use in source and binary forms, with or without modification, -** are permitted provided that the following conditions are met: +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2018 NXP ** -** o Redistributions of source code must retain the above copyright notice, this list -** of conditions and the following disclaimer. -** -** o Redistributions in binary form must reproduce the above copyright notice, this -** list of conditions and the following disclaimer in the documentation and/or -** other materials provided with the distribution. -** -** o Neither the name of the copyright holder nor the names of its -** contributors may be used to endorse or promote products derived from this -** software without specific prior written permission. -** -** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** SPDX-License-Identifier: BSD-3-Clause ** ** http: www.nxp.com ** mail: support@nxp.com @@ -270,6 +248,8 @@ void SystemInit(void) #if !defined(DONT_ENABLE_DISABLED_RAMBANKS) SYSCON->AHBCLKCTRLSET[0] = SYSCON_AHBCLKCTRL_SRAM2_MASK; #endif + + SystemInitHook(); } /* ---------------------------------------------------------------------------- @@ -357,3 +337,11 @@ void SystemCoreClockUpdate(void) } SystemCoreClock = clkRate / ((SYSCON->AHBCLKDIV & 0xFF) + 1); } + +/* ---------------------------------------------------------------------------- + -- SystemInitHook() + ---------------------------------------------------------------------------- */ + +__attribute__ ((weak)) void SystemInitHook (void) { + /* Void implementation of the weak function. */ +} diff --git a/ext/hal/nxp/mcux/devices/LPC54114/system_LPC54114_cm4.h b/ext/hal/nxp/mcux/devices/LPC54114/system_LPC54114_cm4.h index d59c9f71253..1113260167b 100644 --- a/ext/hal/nxp/mcux/devices/LPC54114/system_LPC54114_cm4.h +++ b/ext/hal/nxp/mcux/devices/LPC54114/system_LPC54114_cm4.h @@ -10,39 +10,17 @@ ** ** Reference manual: LPC5411x User manual Rev. 1.1 25 May 2016 ** Version: rev. 1.0, 2016-04-29 -** Build: b161227 +** Build: b180802 ** ** Abstract: ** Provides a system configuration function and a global variable that ** contains the system frequency. It configures the device and initializes ** the oscillator (PLL) that is part of the microcontroller device. ** -** Copyright (c) 2016 Freescale Semiconductor, Inc. -** Copyright 2016 - 2017 NXP -** Redistribution and use in source and binary forms, with or without modification, -** are permitted provided that the following conditions are met: +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2018 NXP ** -** o Redistributions of source code must retain the above copyright notice, this list -** of conditions and the following disclaimer. -** -** o Redistributions in binary form must reproduce the above copyright notice, this -** list of conditions and the following disclaimer in the documentation and/or -** other materials provided with the distribution. -** -** o Neither the name of the copyright holder nor the names of its -** contributors may be used to endorse or promote products derived from this -** software without specific prior written permission. -** -** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** SPDX-License-Identifier: BSD-3-Clause ** ** http: www.nxp.com ** mail: support@nxp.com @@ -112,6 +90,18 @@ void SystemInit (void); */ void SystemCoreClockUpdate (void); +/** + * @brief SystemInit function hook. + * + * This weak function allows to call specific initialization code during the + * SystemInit() execution.This can be used when an application specific code needs + * to be called as close to the reset entry as possible (for example the Multicore + * Manager MCMGR_EarlyInit() function call). + * NOTE: No global r/w variables can be used in this hook function because the + * initialization of these variables happens after this function. + */ +void SystemInitHook (void); + #ifdef __cplusplus } #endif diff --git a/ext/hal/nxp/mcux/devices/MIMXRT1051/MIMXRT1051.h b/ext/hal/nxp/mcux/devices/MIMXRT1051/MIMXRT1051.h index e08c20cf73d..a861f377689 100644 --- a/ext/hal/nxp/mcux/devices/MIMXRT1051/MIMXRT1051.h +++ b/ext/hal/nxp/mcux/devices/MIMXRT1051/MIMXRT1051.h @@ -1,47 +1,27 @@ /* ** ################################################################### -** Processors: MIMXRT1051CVL5A -** MIMXRT1051DVL6A +** Processors: MIMXRT1051CVJ5B +** MIMXRT1051CVL5B +** MIMXRT1051DVL6B ** -** Compilers: Keil ARM C/C++ Compiler -** Freescale C/C++ for Embedded ARM +** Compilers: Freescale C/C++ for Embedded ARM ** GNU C Compiler ** IAR ANSI C/C++ Compiler for ARM +** Keil ARM C/C++ Compiler ** MCUXpresso Compiler ** -** Reference manual: IMXRT1050RM Rev.C, 08/2017 -** Version: rev. 0.1, 2017-01-10 -** Build: b171011 +** Reference manual: IMXRT1050RM Rev.2.1, 12/2018 +** Version: rev. 1.2, 2018-11-27 +** Build: b181205 ** ** Abstract: ** CMSIS Peripheral Access Layer for MIMXRT1051 ** ** Copyright 1997-2016 Freescale Semiconductor, Inc. -** Copyright 2016-2017 NXP -** Redistribution and use in source and binary forms, with or without modification, -** are permitted provided that the following conditions are met: +** Copyright 2016-2018 NXP +** All rights reserved. ** -** 1. Redistributions of source code must retain the above copyright notice, this list -** of conditions and the following disclaimer. -** -** 2. Redistributions in binary form must reproduce the above copyright notice, this -** list of conditions and the following disclaimer in the documentation and/or -** other materials provided with the distribution. -** -** 3. Neither the name of the copyright holder nor the names of its -** contributors may be used to endorse or promote products derived from this -** software without specific prior written permission. -** -** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** SPDX-License-Identifier: BSD-3-Clause ** ** http: www.nxp.com ** mail: support@nxp.com @@ -49,14 +29,22 @@ ** Revisions: ** - rev. 0.1 (2017-01-10) ** Initial version. +** - rev. 1.0 (2018-09-21) +** Update interrupt vector table and dma request source. +** Update register BEE_ADDR_OFFSET1's bitfield name to ADDR_OFFSET1. +** Split GPIO_COMBINED_IRQS to GPIO_COMBINED_LOW_IRQS and GPIO_COMBINED_HIGH_IRQS. +** - rev. 1.1 (2018-11-16) +** Update header files to align with IMXRT1050RM Rev.1. +** - rev. 1.2 (2018-11-27) +** Update header files to align with IMXRT1050RM Rev.2.1. ** ** ################################################################### */ /*! * @file MIMXRT1051.h - * @version 0.1 - * @date 2017-01-10 + * @version 1.2 + * @date 2018-11-27 * @brief CMSIS Peripheral Access Layer for MIMXRT1051 * * CMSIS Peripheral Access Layer for MIMXRT1051 @@ -67,9 +55,9 @@ /** Memory map major version (memory maps with equal major version number are * compatible) */ -#define MCU_MEM_MAP_VERSION 0x0000U +#define MCU_MEM_MAP_VERSION 0x0100U /** Memory map minor version */ -#define MCU_MEM_MAP_VERSION_MINOR 0x0001U +#define MCU_MEM_MAP_VERSION_MINOR 0x0002U /* ---------------------------------------------------------------------------- @@ -82,7 +70,7 @@ */ /** Interrupt Number Definitions */ -#define NUMBER_OF_INT_VECTORS 176 /**< Number of interrupts in the Vector table */ +#define NUMBER_OF_INT_VECTORS 168 /**< Number of interrupts in the Vector table */ typedef enum IRQn { /* Auxiliary constants */ @@ -161,10 +149,10 @@ typedef enum IRQn { SAI3_RX_IRQn = 58, /**< SAI3 interrupt */ SAI3_TX_IRQn = 59, /**< SAI3 interrupt */ SPDIF_IRQn = 60, /**< SPDIF interrupt */ - ANATOP_EVENT0_IRQn = 61, /**< ANATOP interrupt */ - ANATOP_EVENT1_IRQn = 62, /**< ANATOP interrupt */ - ANATOP_TAMP_LOW_HIGH_IRQn = 63, /**< ANATOP interrupt */ - ANATOP_TEMP_PANIC_IRQn = 64, /**< ANATOP interrupt */ + PMU_EVENT_IRQn = 61, /**< Brown-out event interrupt */ + Reserved78_IRQn = 62, /**< Reserved interrupt */ + TEMP_LOW_HIGH_IRQn = 63, /**< TempSensor low/high interrupt */ + TEMP_PANIC_IRQn = 64, /**< TempSensor panic interrupt */ USB_PHY1_IRQn = 65, /**< USBPHY (UTMI0), Interrupt */ USB_PHY2_IRQn = 66, /**< USBPHY (UTMI0), Interrupt */ ADC1_IRQn = 67, /**< ADC1 interrupt */ @@ -251,15 +239,7 @@ typedef enum IRQn { PWM4_1_IRQn = 148, /**< PWM4 capture 1, compare 1, or reload 0 interrupt */ PWM4_2_IRQn = 149, /**< PWM4 capture 2, compare 2, or reload 0 interrupt */ PWM4_3_IRQn = 150, /**< PWM4 capture 3, compare 3, or reload 0 interrupt */ - PWM4_FAULT_IRQn = 151, /**< PWM4 fault or reload error interrupt */ - Reserved168_IRQn = 152, /**< Reserved interrupt */ - Reserved169_IRQn = 153, /**< Reserved interrupt */ - Reserved170_IRQn = 154, /**< Reserved interrupt */ - Reserved171_IRQn = 155, /**< Reserved interrupt */ - Reserved172_IRQn = 156, /**< Reserved interrupt */ - Reserved173_IRQn = 157, /**< Reserved interrupt */ - SJC_ARM_DEBUG_IRQn = 158, /**< SJC ARM debug interrupt */ - NMI_WAKEUP_IRQn = 159 /**< NMI wake up */ + PWM4_FAULT_IRQn = 151 /**< PWM4 fault or reload error interrupt */ } IRQn_Type; /*! @@ -304,21 +284,24 @@ typedef enum IRQn { /** Mapping Information */ /*! * @addtogroup edma_request - * @{ */ + * @{ + */ /******************************************************************************* * Definitions -*******************************************************************************/ + ******************************************************************************/ /*! - * @brief Enumeration for the DMA0 hardware request + * @brief Structure for the DMA hardware request * - * Defines the enumeration for the DMA0 hardware request collections. + * Defines the structure for the DMA hardware request collections. The user can configure the + * hardware request into DMAMUX to trigger the DMA transfer accordingly. The index + * of the hardware request varies according to the to SoC. */ typedef enum _dma_request_source { - kDmaRequestMuxFlexIO1Request0Request1 = 0|0x100U, /**< FlexIO1 */ - kDmaRequestMuxFlexIO2Request0Request1 = 1|0x100U, /**< FlexIO2 */ + kDmaRequestMuxFlexIO1Request0Request1 = 0|0x100U, /**< FlexIO1 Request0 and Request1 */ + kDmaRequestMuxFlexIO2Request0Request1 = 1|0x100U, /**< FlexIO2 Request0 and Request1 */ kDmaRequestMuxLPUART1Tx = 2|0x100U, /**< LPUART1 Transmit */ kDmaRequestMuxLPUART1Rx = 3|0x100U, /**< LPUART1 Receive */ kDmaRequestMuxLPUART3Tx = 4|0x100U, /**< LPUART3 Transmit */ @@ -333,14 +316,14 @@ typedef enum _dma_request_source kDmaRequestMuxLPSPI3Tx = 16|0x100U, /**< LPSPI3 Transmit */ kDmaRequestMuxLPI2C1 = 17|0x100U, /**< LPI2C1 */ kDmaRequestMuxLPI2C3 = 18|0x100U, /**< LPI2C3 */ - kDmaRequestMuxSai1Rx = 19|0x100U, /**< Sai1 Receive */ - kDmaRequestMuxSai1Tx = 20|0x100U, /**< Sai1 Transmit */ - kDmaRequestMuxSai2Rx = 21|0x100U, /**< Sai2 Receive */ - kDmaRequestMuxSai2Tx = 22|0x100U, /**< Sai2 Transmit */ + kDmaRequestMuxSai1Rx = 19|0x100U, /**< SAI1 Receive */ + kDmaRequestMuxSai1Tx = 20|0x100U, /**< SAI1 Transmit */ + kDmaRequestMuxSai2Rx = 21|0x100U, /**< SAI2 Receive */ + kDmaRequestMuxSai2Tx = 22|0x100U, /**< SAI2 Transmit */ kDmaRequestMuxADC_ETC = 23|0x100U, /**< ADC_ETC */ kDmaRequestMuxADC1 = 24|0x100U, /**< ADC1 */ kDmaRequestMuxACMP1 = 25|0x100U, /**< ACMP1 */ - kDmaRequestMuxACMP2 = 26|0x100U, /**< ACMP2 */ + kDmaRequestMuxACMP3 = 26|0x100U, /**< ACMP3 */ kDmaRequestMuxFlexSPIRx = 28|0x100U, /**< FlexSPI Receive */ kDmaRequestMuxFlexSPITx = 29|0x100U, /**< FlexSPI Transmit */ kDmaRequestMuxXBAR1Request0 = 30|0x100U, /**< XBAR1 Request 0 */ @@ -361,20 +344,20 @@ typedef enum _dma_request_source kDmaRequestMuxFlexPWM3ValueSub1 = 45|0x100U, /**< FlexPWM3 Value sub-module1 */ kDmaRequestMuxFlexPWM3ValueSub2 = 46|0x100U, /**< FlexPWM3 Value sub-module2 */ kDmaRequestMuxFlexPWM3ValueSub3 = 47|0x100U, /**< FlexPWM3 Value sub-module3 */ - kDmaRequestMuxQTIMER1CaptTimer0 = 48|0x100U, /**< QTIMER1 Capture timer 0 */ - kDmaRequestMuxQTIMER1CaptTimer1 = 49|0x100U, /**< QTIMER1 Capture timer 1 */ - kDmaRequestMuxQTIMER1CaptTimer2 = 50|0x100U, /**< QTIMER1 Capture timer 2 */ - kDmaRequestMuxQTIMER1CaptTimer3 = 51|0x100U, /**< QTIMER1 Capture timer 3 */ - kDmaRequestMuxQTIMER1Cmpld1Timer0Cmpld2Timer1 = 52|0x100U, /**< QTIMER1 cmpld1 in timer 0 or cmpld2 in timer 1 */ - kDmaRequestMuxQTIMER1Cmpld1Timer1Cmpld2Timer0 = 53|0x100U, /**< QTIMER1 cmpld1 in timer 1 or cmpld2 in timer 0 */ - kDmaRequestMuxQTIMER1Cmpld1Timer2Cmpld2Timer3 = 54|0x100U, /**< QTIMER1 cmpld1 in timer 2 or cmpld2 in timer 3 */ - kDmaRequestMuxQTIMER1Cmpld1Timer3Cmpld2Timer2 = 55|0x100U, /**< QTIMER1 cmpld1 in timer 3 or cmpld2 in timer 2 */ - kDmaRequestMuxQTIMER3CaptTimer0Cmpld1Timer0Cmpld2Timer1 = 56|0x100U, /**< QTIMER3 capture timer 0, cmpld1 in timer 0 or cmpld2 in timer 1 */ - kDmaRequestMuxQTIMER3CaptTimer1Cmpld1Timer0Cmpld2Timer1 = 57|0x100U, /**< QTIMER3 capture timer 1, cmpld1 in timer 0 or cmpld2 in timer 1 */ - kDmaRequestMuxQTIMER3CaptTimer2Cmpld1Timer0Cmpld2Timer1 = 58|0x100U, /**< QTIMER3 capture timer 2, cmpld1 in timer 0 or cmpld2 in timer 1 */ - kDmaRequestMuxQTIMER3CaptTimer3Cmpld1Timer0Cmpld2Timer1 = 59|0x100U, /**< QTIMER3 capture timer 3, cmpld1 in timer 0 or cmpld2 in timer 1 */ - kDmaRequestMuxFlexIO1Request2Request3 = 64|0x100U, /**< FlexIO1 */ - kDmaRequestMuxFlexIO2Request2Request3 = 65|0x100U, /**< FlexIO2 */ + kDmaRequestMuxQTIMER1CaptTimer0 = 48|0x100U, /**< TMR1 Capture timer 0 */ + kDmaRequestMuxQTIMER1CaptTimer1 = 49|0x100U, /**< TMR1 Capture timer 1 */ + kDmaRequestMuxQTIMER1CaptTimer2 = 50|0x100U, /**< TMR1 Capture timer 2 */ + kDmaRequestMuxQTIMER1CaptTimer3 = 51|0x100U, /**< TMR1 Capture timer 3 */ + kDmaRequestMuxQTIMER1Cmpld1Timer0Cmpld2Timer1 = 52|0x100U, /**< TMR1 cmpld1 in timer 0 or cmpld2 in timer 1 */ + kDmaRequestMuxQTIMER1Cmpld1Timer1Cmpld2Timer0 = 53|0x100U, /**< TMR1 cmpld1 in timer 1 or cmpld2 in timer 0 */ + kDmaRequestMuxQTIMER1Cmpld1Timer2Cmpld2Timer3 = 54|0x100U, /**< TMR1 cmpld1 in timer 2 or cmpld2 in timer 3 */ + kDmaRequestMuxQTIMER1Cmpld1Timer3Cmpld2Timer2 = 55|0x100U, /**< TMR1 cmpld1 in timer 3 or cmpld2 in timer 2 */ + kDmaRequestMuxQTIMER3CaptTimer0Cmpld1Timer0Cmpld2Timer1 = 56|0x100U, /**< TMR3 capture timer 0, cmpld1 in timer 0 or cmpld2 in timer 1 */ + kDmaRequestMuxQTIMER3CaptTimer1Cmpld1Timer1Cmpld2Timer0 = 57|0x100U, /**< TMR3 capture timer 1, cmpld1 in timer 1 or cmpld2 in timer 0 */ + kDmaRequestMuxQTIMER3CaptTimer2Cmpld1Timer2Cmpld2Timer3 = 58|0x100U, /**< TMR3 capture timer 2, cmpld1 in timer 2 or cmpld2 in timer 3 */ + kDmaRequestMuxQTIMER3CaptTimer3Cmpld1Timer3Cmpld2Timer2 = 59|0x100U, /**< TMR3 capture timer 3, cmpld1 in timer 3 or cmpld2 in timer 2 */ + kDmaRequestMuxFlexIO1Request2Request3 = 64|0x100U, /**< FlexIO1 Request2 and Request3 */ + kDmaRequestMuxFlexIO2Request2Request3 = 65|0x100U, /**< FlexIO2 Request2 and Request3 */ kDmaRequestMuxLPUART2Tx = 66|0x100U, /**< LPUART2 Transmit */ kDmaRequestMuxLPUART2Rx = 67|0x100U, /**< LPUART2 Receive */ kDmaRequestMuxLPUART4Tx = 68|0x100U, /**< LPUART4 Transmit */ @@ -389,15 +372,15 @@ typedef enum _dma_request_source kDmaRequestMuxLPSPI4Tx = 80|0x100U, /**< LPSPI4 Transmit */ kDmaRequestMuxLPI2C2 = 81|0x100U, /**< LPI2C2 */ kDmaRequestMuxLPI2C4 = 82|0x100U, /**< LPI2C4 */ - kDmaRequestMuxSai3Rx = 83|0x100U, /**< Sai3 Receive */ - kDmaRequestMuxSai3Tx = 84|0x100U, /**< Sai3 Transmit */ - kDmaRequestMuxSpdifRx = 85|0x100U, /**< Spdif Receive */ - kDmaRequestMuxSpdifTx = 86|0x100U, /**< Spdif Transmit */ + kDmaRequestMuxSai3Rx = 83|0x100U, /**< SAI3 Receive */ + kDmaRequestMuxSai3Tx = 84|0x100U, /**< SAI3 Transmit */ + kDmaRequestMuxSpdifRx = 85|0x100U, /**< SPDIF Receive */ + kDmaRequestMuxSpdifTx = 86|0x100U, /**< SPDIF Transmit */ kDmaRequestMuxADC2 = 88|0x100U, /**< ADC2 */ - kDmaRequestMuxACMP3 = 89|0x100U, /**< ACMP3 */ + kDmaRequestMuxACMP2 = 89|0x100U, /**< ACMP2 */ kDmaRequestMuxACMP4 = 90|0x100U, /**< ACMP4 */ - kDmaRequestMuxEnetTimer0 = 92|0x100U, /**< Enet Timer0 */ - kDmaRequestMuxEnetTimer1 = 93|0x100U, /**< Enet Timer1 */ + kDmaRequestMuxEnetTimer0 = 92|0x100U, /**< ENET Timer0 */ + kDmaRequestMuxEnetTimer1 = 93|0x100U, /**< ENET Timer1 */ kDmaRequestMuxXBAR1Request2 = 94|0x100U, /**< XBAR1 Request 2 */ kDmaRequestMuxXBAR1Request3 = 95|0x100U, /**< XBAR1 Request 3 */ kDmaRequestMuxFlexPWM2CaptureSub0 = 96|0x100U, /**< FlexPWM2 Capture sub-module0 */ @@ -416,20 +399,22 @@ typedef enum _dma_request_source kDmaRequestMuxFlexPWM4ValueSub1 = 109|0x100U, /**< FlexPWM4 Value sub-module1 */ kDmaRequestMuxFlexPWM4ValueSub2 = 110|0x100U, /**< FlexPWM4 Value sub-module2 */ kDmaRequestMuxFlexPWM4ValueSub3 = 111|0x100U, /**< FlexPWM4 Value sub-module3 */ - kDmaRequestMuxQTIMER2CaptTimer0 = 112|0x100U, /**< QTIMER2 Capture timer 0 */ - kDmaRequestMuxQTIMER2CaptTimer1 = 113|0x100U, /**< QTIMER2 Capture timer 1 */ - kDmaRequestMuxQTIMER2CaptTimer2 = 114|0x100U, /**< QTIMER2 Capture timer 2 */ - kDmaRequestMuxQTIMER2CaptTimer3 = 115|0x100U, /**< QTIMER2 Capture timer 3 */ - kDmaRequestMuxQTIMER2Cmpld1Timer0Cmpld2Timer1 = 116|0x100U, /**< QTIMER2 cmpld1 in timer 0 or cmpld2 in timer 1 */ - kDmaRequestMuxQTIMER2Cmpld1Timer1Cmpld2Timer0 = 117|0x100U, /**< QTIMER2 cmpld1 in timer 1 or cmpld2 in timer 0 */ - kDmaRequestMuxQTIMER2Cmpld1Timer2Cmpld2Timer3 = 118|0x100U, /**< QTIMER2 cmpld1 in timer 2 or cmpld2 in timer 3 */ - kDmaRequestMuxQTIMER2Cmpld1Timer3Cmpld2Timer2 = 119|0x100U, /**< QTIMER2 cmpld1 in timer 3 or cmpld2 in timer 2 */ - kDmaRequestMuxQTIMER4CaptTimer0Cmpld1Timer0Cmpld2Timer1 = 120|0x100U, /**< QTIMER4 capture timer 0, cmpld1 in timer 0 or cmpld2 in timer 1 */ - kDmaRequestMuxQTIMER4CaptTimer1Cmpld1Timer0Cmpld2Timer1 = 121|0x100U, /**< QTIMER4 capture timer 1, cmpld1 in timer 0 or cmpld2 in timer 1 */ - kDmaRequestMuxQTIMER4CaptTimer2Cmpld1Timer0Cmpld2Timer1 = 122|0x100U, /**< QTIMER4 capture timer 2, cmpld1 in timer 0 or cmpld2 in timer 1 */ - kDmaRequestMuxQTIMER4CaptTimer3Cmpld1Timer0Cmpld2Timer1 = 123|0x100U, /**< QTIMER4 capture timer 3, cmpld1 in timer 0 or cmpld2 in timer 1 */ + kDmaRequestMuxQTIMER2CaptTimer0 = 112|0x100U, /**< TMR2 Capture timer 0 */ + kDmaRequestMuxQTIMER2CaptTimer1 = 113|0x100U, /**< TMR2 Capture timer 1 */ + kDmaRequestMuxQTIMER2CaptTimer2 = 114|0x100U, /**< TMR2 Capture timer 2 */ + kDmaRequestMuxQTIMER2CaptTimer3 = 115|0x100U, /**< TMR2 Capture timer 3 */ + kDmaRequestMuxQTIMER2Cmpld1Timer0Cmpld2Timer1 = 116|0x100U, /**< TMR2 cmpld1 in timer 0 or cmpld2 in timer 1 */ + kDmaRequestMuxQTIMER2Cmpld1Timer1Cmpld2Timer0 = 117|0x100U, /**< TMR2 cmpld1 in timer 1 or cmpld2 in timer 0 */ + kDmaRequestMuxQTIMER2Cmpld1Timer2Cmpld2Timer3 = 118|0x100U, /**< TMR2 cmpld1 in timer 2 or cmpld2 in timer 3 */ + kDmaRequestMuxQTIMER2Cmpld1Timer3Cmpld2Timer2 = 119|0x100U, /**< TMR2 cmpld1 in timer 3 or cmpld2 in timer 2 */ + kDmaRequestMuxQTIMER4CaptTimer0Cmpld1Timer0Cmpld2Timer1 = 120|0x100U, /**< TMR4 capture timer 0, cmpld1 in timer 0 or cmpld2 in timer 1 */ + kDmaRequestMuxQTIMER4CaptTimer1Cmpld1Timer1Cmpld2Timer0 = 121|0x100U, /**< TMR4 capture timer 1, cmpld1 in timer 1 or cmpld2 in timer 0 */ + kDmaRequestMuxQTIMER4CaptTimer2Cmpld1Timer2Cmpld2Timer3 = 122|0x100U, /**< TMR4 capture timer 2, cmpld1 in timer 2 or cmpld2 in timer 3 */ + kDmaRequestMuxQTIMER4CaptTimer3Cmpld1Timer3Cmpld2Timer2 = 123|0x100U, /**< TMR4 capture timer 3, cmpld1 in timer 3 or cmpld2 in timer 2 */ } dma_request_source_t; +/* @} */ + /*! * @addtogroup iomuxc_pads * @{ */ @@ -571,6 +556,8 @@ typedef enum _iomuxc_sw_mux_ctl_pad kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_11 = 123U, /**< IOMUXC SW_MUX_CTL_PAD index */ } iomuxc_sw_mux_ctl_pad_t; +/* @} */ + /*! * @addtogroup iomuxc_pads * @{ */ @@ -712,6 +699,8 @@ typedef enum _iomuxc_sw_pad_ctl_pad kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_11 = 123U, /**< IOMUXC SW_PAD_CTL_PAD index */ } iomuxc_sw_pad_ctl_pad_t; +/* @} */ + /*! * @brief Enumeration for the IOMUXC select input * @@ -875,8 +864,6 @@ typedef enum _iomuxc_select_input kIOMUXC_XBAR1_IN21_SELECT_INPUT = 153U, /**< IOMUXC select input index */ } iomuxc_select_input_t; -/* @} */ - typedef enum _xbar_input_signal { kXBARA1_InputLogicLow = 0|0x100U, /**< LOGIC_LOW output assigned to XBARA1_IN0 input. */ @@ -1273,8 +1260,12 @@ typedef enum _xbar_output_signal */ #if defined(__ARMCC_VERSION) - #pragma push - #pragma anon_unions + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #else + #pragma push + #pragma anon_unions + #endif #elif defined(__CWCC__) #pragma push #pragma cpp_extensions on @@ -1318,121 +1309,251 @@ typedef struct { */ /*! @name HC - Control register for hardware triggers */ +/*! @{ */ #define ADC_HC_ADCH_MASK (0x1FU) #define ADC_HC_ADCH_SHIFT (0U) +/*! ADCH - Input Channel Select + * 0b10000..External channel selection from ADC_ETC + * 0b11000..Reserved. + * 0b11001..VREFSH = internal channel, for ADC self-test, hard connected to VRH internally + * 0b11010..Reserved. + * 0b11011..Reserved. + * 0b11111..Conversion Disabled. Hardware Triggers will not initiate any conversion. + */ #define ADC_HC_ADCH(x) (((uint32_t)(((uint32_t)(x)) << ADC_HC_ADCH_SHIFT)) & ADC_HC_ADCH_MASK) #define ADC_HC_AIEN_MASK (0x80U) #define ADC_HC_AIEN_SHIFT (7U) +/*! AIEN - Conversion Complete Interrupt Enable/Disable Control + * 0b1..Conversion complete interrupt enabled + * 0b0..Conversion complete interrupt disabled + */ #define ADC_HC_AIEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_HC_AIEN_SHIFT)) & ADC_HC_AIEN_MASK) +/*! @} */ /* The count of ADC_HC */ #define ADC_HC_COUNT (8U) /*! @name HS - Status register for HW triggers */ +/*! @{ */ #define ADC_HS_COCO0_MASK (0x1U) #define ADC_HS_COCO0_SHIFT (0U) #define ADC_HS_COCO0(x) (((uint32_t)(((uint32_t)(x)) << ADC_HS_COCO0_SHIFT)) & ADC_HS_COCO0_MASK) +/*! @} */ /*! @name R - Data result register for HW triggers */ +/*! @{ */ #define ADC_R_CDATA_MASK (0xFFFU) #define ADC_R_CDATA_SHIFT (0U) #define ADC_R_CDATA(x) (((uint32_t)(((uint32_t)(x)) << ADC_R_CDATA_SHIFT)) & ADC_R_CDATA_MASK) +/*! @} */ /* The count of ADC_R */ #define ADC_R_COUNT (8U) /*! @name CFG - Configuration register */ +/*! @{ */ #define ADC_CFG_ADICLK_MASK (0x3U) #define ADC_CFG_ADICLK_SHIFT (0U) +/*! ADICLK - Input Clock Select + * 0b00..IPG clock + * 0b01..IPG clock divided by 2 + * 0b10..Reserved + * 0b11..Asynchronous clock (ADACK) + */ #define ADC_CFG_ADICLK(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADICLK_SHIFT)) & ADC_CFG_ADICLK_MASK) #define ADC_CFG_MODE_MASK (0xCU) #define ADC_CFG_MODE_SHIFT (2U) +/*! MODE - Conversion Mode Selection + * 0b00..8-bit conversion + * 0b01..10-bit conversion + * 0b10..12-bit conversion + * 0b11..Reserved + */ #define ADC_CFG_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_MODE_SHIFT)) & ADC_CFG_MODE_MASK) #define ADC_CFG_ADLSMP_MASK (0x10U) #define ADC_CFG_ADLSMP_SHIFT (4U) +/*! ADLSMP - Long Sample Time Configuration + * 0b0..Short sample mode. + * 0b1..Long sample mode. + */ #define ADC_CFG_ADLSMP(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADLSMP_SHIFT)) & ADC_CFG_ADLSMP_MASK) #define ADC_CFG_ADIV_MASK (0x60U) #define ADC_CFG_ADIV_SHIFT (5U) +/*! ADIV - Clock Divide Select + * 0b00..Input clock + * 0b01..Input clock / 2 + * 0b10..Input clock / 4 + * 0b11..Input clock / 8 + */ #define ADC_CFG_ADIV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADIV_SHIFT)) & ADC_CFG_ADIV_MASK) #define ADC_CFG_ADLPC_MASK (0x80U) #define ADC_CFG_ADLPC_SHIFT (7U) +/*! ADLPC - Low-Power Configuration + * 0b0..ADC hard block not in low power mode. + * 0b1..ADC hard block in low power mode. + */ #define ADC_CFG_ADLPC(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADLPC_SHIFT)) & ADC_CFG_ADLPC_MASK) #define ADC_CFG_ADSTS_MASK (0x300U) #define ADC_CFG_ADSTS_SHIFT (8U) +/*! ADSTS + * 0b00..Sample period (ADC clocks) = 2 if ADLSMP=0b Sample period (ADC clocks) = 12 if ADLSMP=1b + * 0b01..Sample period (ADC clocks) = 4 if ADLSMP=0b Sample period (ADC clocks) = 16 if ADLSMP=1b + * 0b10..Sample period (ADC clocks) = 6 if ADLSMP=0b Sample period (ADC clocks) = 20 if ADLSMP=1b + * 0b11..Sample period (ADC clocks) = 8 if ADLSMP=0b Sample period (ADC clocks) = 24 if ADLSMP=1b + */ #define ADC_CFG_ADSTS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADSTS_SHIFT)) & ADC_CFG_ADSTS_MASK) #define ADC_CFG_ADHSC_MASK (0x400U) #define ADC_CFG_ADHSC_SHIFT (10U) +/*! ADHSC - High Speed Configuration + * 0b0..Normal conversion selected. + * 0b1..High speed conversion selected. + */ #define ADC_CFG_ADHSC(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADHSC_SHIFT)) & ADC_CFG_ADHSC_MASK) #define ADC_CFG_REFSEL_MASK (0x1800U) #define ADC_CFG_REFSEL_SHIFT (11U) +/*! REFSEL - Voltage Reference Selection + * 0b00..Selects VREFH/VREFL as reference voltage. + * 0b01..Reserved + * 0b10..Reserved + * 0b11..Reserved + */ #define ADC_CFG_REFSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_REFSEL_SHIFT)) & ADC_CFG_REFSEL_MASK) #define ADC_CFG_ADTRG_MASK (0x2000U) #define ADC_CFG_ADTRG_SHIFT (13U) +/*! ADTRG - Conversion Trigger Select + * 0b0..Software trigger selected + * 0b1..Hardware trigger selected + */ #define ADC_CFG_ADTRG(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADTRG_SHIFT)) & ADC_CFG_ADTRG_MASK) #define ADC_CFG_AVGS_MASK (0xC000U) #define ADC_CFG_AVGS_SHIFT (14U) +/*! AVGS - Hardware Average select + * 0b00..4 samples averaged + * 0b01..8 samples averaged + * 0b10..16 samples averaged + * 0b11..32 samples averaged + */ #define ADC_CFG_AVGS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_AVGS_SHIFT)) & ADC_CFG_AVGS_MASK) #define ADC_CFG_OVWREN_MASK (0x10000U) #define ADC_CFG_OVWREN_SHIFT (16U) +/*! OVWREN - Data Overwrite Enable + * 0b1..Enable the overwriting. + * 0b0..Disable the overwriting. Existing Data in Data result register will not be overwritten by subsequent converted data. + */ #define ADC_CFG_OVWREN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_OVWREN_SHIFT)) & ADC_CFG_OVWREN_MASK) +/*! @} */ /*! @name GC - General control register */ +/*! @{ */ #define ADC_GC_ADACKEN_MASK (0x1U) #define ADC_GC_ADACKEN_SHIFT (0U) +/*! ADACKEN - Asynchronous clock output enable + * 0b0..Asynchronous clock output disabled; Asynchronous clock only enabled if selected by ADICLK and a conversion is active. + * 0b1..Asynchronous clock and clock output enabled regardless of the state of the ADC + */ #define ADC_GC_ADACKEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_ADACKEN_SHIFT)) & ADC_GC_ADACKEN_MASK) #define ADC_GC_DMAEN_MASK (0x2U) #define ADC_GC_DMAEN_SHIFT (1U) +/*! DMAEN - DMA Enable + * 0b0..DMA disabled (default) + * 0b1..DMA enabled + */ #define ADC_GC_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_DMAEN_SHIFT)) & ADC_GC_DMAEN_MASK) #define ADC_GC_ACREN_MASK (0x4U) #define ADC_GC_ACREN_SHIFT (2U) +/*! ACREN - Compare Function Range Enable + * 0b0..Range function disabled. Only the compare value 1 of ADC_CV register (CV1) is compared. + * 0b1..Range function enabled. Both compare values of ADC_CV registers (CV1 and CV2) are compared. + */ #define ADC_GC_ACREN(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_ACREN_SHIFT)) & ADC_GC_ACREN_MASK) #define ADC_GC_ACFGT_MASK (0x8U) #define ADC_GC_ACFGT_SHIFT (3U) +/*! ACFGT - Compare Function Greater Than Enable + * 0b0..Configures "Less Than Threshold, Outside Range Not Inclusive and Inside Range Not Inclusive" functionality based on the values placed in the ADC_CV register. + * 0b1..Configures "Greater Than Or Equal To Threshold, Outside Range Inclusive and Inside Range Inclusive" functionality based on the values placed in the ADC_CV registers. + */ #define ADC_GC_ACFGT(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_ACFGT_SHIFT)) & ADC_GC_ACFGT_MASK) #define ADC_GC_ACFE_MASK (0x10U) #define ADC_GC_ACFE_SHIFT (4U) +/*! ACFE - Compare Function Enable + * 0b0..Compare function disabled + * 0b1..Compare function enabled + */ #define ADC_GC_ACFE(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_ACFE_SHIFT)) & ADC_GC_ACFE_MASK) #define ADC_GC_AVGE_MASK (0x20U) #define ADC_GC_AVGE_SHIFT (5U) +/*! AVGE - Hardware average enable + * 0b0..Hardware average function disabled + * 0b1..Hardware average function enabled + */ #define ADC_GC_AVGE(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_AVGE_SHIFT)) & ADC_GC_AVGE_MASK) #define ADC_GC_ADCO_MASK (0x40U) #define ADC_GC_ADCO_SHIFT (6U) +/*! ADCO - Continuous Conversion Enable + * 0b0..One conversion or one set of conversions if the hardware average function is enabled (AVGE=1) after initiating a conversion. + * 0b1..Continuous conversions or sets of conversions if the hardware average function is enabled (AVGE=1) after initiating a conversion. + */ #define ADC_GC_ADCO(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_ADCO_SHIFT)) & ADC_GC_ADCO_MASK) #define ADC_GC_CAL_MASK (0x80U) #define ADC_GC_CAL_SHIFT (7U) #define ADC_GC_CAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_CAL_SHIFT)) & ADC_GC_CAL_MASK) +/*! @} */ /*! @name GS - General status register */ +/*! @{ */ #define ADC_GS_ADACT_MASK (0x1U) #define ADC_GS_ADACT_SHIFT (0U) +/*! ADACT - Conversion Active + * 0b0..Conversion not in progress. + * 0b1..Conversion in progress. + */ #define ADC_GS_ADACT(x) (((uint32_t)(((uint32_t)(x)) << ADC_GS_ADACT_SHIFT)) & ADC_GS_ADACT_MASK) #define ADC_GS_CALF_MASK (0x2U) #define ADC_GS_CALF_SHIFT (1U) +/*! CALF - Calibration Failed Flag + * 0b0..Calibration completed normally. + * 0b1..Calibration failed. ADC accuracy specifications are not guaranteed. + */ #define ADC_GS_CALF(x) (((uint32_t)(((uint32_t)(x)) << ADC_GS_CALF_SHIFT)) & ADC_GS_CALF_MASK) #define ADC_GS_AWKST_MASK (0x4U) #define ADC_GS_AWKST_SHIFT (2U) +/*! AWKST - Asynchronous wakeup interrupt status + * 0b1..Asynchronous wake up interrupt occurred in stop mode. + * 0b0..No asynchronous interrupt. + */ #define ADC_GS_AWKST(x) (((uint32_t)(((uint32_t)(x)) << ADC_GS_AWKST_SHIFT)) & ADC_GS_AWKST_MASK) +/*! @} */ /*! @name CV - Compare value register */ +/*! @{ */ #define ADC_CV_CV1_MASK (0xFFFU) #define ADC_CV_CV1_SHIFT (0U) #define ADC_CV_CV1(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV_CV1_SHIFT)) & ADC_CV_CV1_MASK) #define ADC_CV_CV2_MASK (0xFFF0000U) #define ADC_CV_CV2_SHIFT (16U) #define ADC_CV_CV2(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV_CV2_SHIFT)) & ADC_CV_CV2_MASK) +/*! @} */ /*! @name OFS - Offset correction value register */ +/*! @{ */ #define ADC_OFS_OFS_MASK (0xFFFU) #define ADC_OFS_OFS_SHIFT (0U) #define ADC_OFS_OFS(x) (((uint32_t)(((uint32_t)(x)) << ADC_OFS_OFS_SHIFT)) & ADC_OFS_OFS_MASK) #define ADC_OFS_SIGN_MASK (0x1000U) #define ADC_OFS_SIGN_SHIFT (12U) +/*! SIGN - Sign bit + * 0b0..The offset value is added with the raw result + * 0b1..The offset value is subtracted from the raw converted value + */ #define ADC_OFS_SIGN(x) (((uint32_t)(((uint32_t)(x)) << ADC_OFS_SIGN_SHIFT)) & ADC_OFS_SIGN_MASK) +/*! @} */ /*! @name CAL - Calibration value register */ +/*! @{ */ #define ADC_CAL_CAL_CODE_MASK (0xFU) #define ADC_CAL_CAL_CODE_SHIFT (0U) #define ADC_CAL_CAL_CODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_CAL_CODE_SHIFT)) & ADC_CAL_CAL_CODE_MASK) +/*! @} */ /*! @@ -1477,16 +1598,8 @@ typedef struct { __IO uint32_t DONE2_ERR_IRQ; /**< ETC DONE_2 and DONE_ERR IRQ State Register, offset: 0x8 */ __IO uint32_t DMA_CTRL; /**< ETC DMA control Register, offset: 0xC */ struct { /* offset: 0x10, array step: 0x28 */ - __IO uint32_t TRIGn_CTRL; /**< - ETC_TRIG0 Control Register - .. - ETC_TRIG7 Control Register - , array offset: 0x10, array step: 0x28 */ - __IO uint32_t TRIGn_COUNTER; /**< - ETC_TRIG0 Counter Register - .. - ETC_TRIG7 Counter Register - , array offset: 0x14, array step: 0x28 */ + __IO uint32_t TRIGn_CTRL; /**< ETC_TRIG0 Control Register..ETC_TRIG7 Control Register, array offset: 0x10, array step: 0x28 */ + __IO uint32_t TRIGn_COUNTER; /**< ETC_TRIG0 Counter Register..ETC_TRIG7 Counter Register, array offset: 0x14, array step: 0x28 */ __IO uint32_t TRIGn_CHAIN_1_0; /**< ETC_TRIG Chain 0/1 Register, array offset: 0x18, array step: 0x28 */ __IO uint32_t TRIGn_CHAIN_3_2; /**< ETC_TRIG Chain 2/3 Register, array offset: 0x1C, array step: 0x28 */ __IO uint32_t TRIGn_CHAIN_5_4; /**< ETC_TRIG Chain 4/5 Register, array offset: 0x20, array step: 0x28 */ @@ -1508,6 +1621,7 @@ typedef struct { */ /*! @name CTRL - ADC_ETC Global Control Register */ +/*! @{ */ #define ADC_ETC_CTRL_TRIG_ENABLE_MASK (0xFFU) #define ADC_ETC_CTRL_TRIG_ENABLE_SHIFT (0U) #define ADC_ETC_CTRL_TRIG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_TRIG_ENABLE_SHIFT)) & ADC_ETC_CTRL_TRIG_ENABLE_MASK) @@ -1526,14 +1640,19 @@ typedef struct { #define ADC_ETC_CTRL_PRE_DIVIDER_MASK (0xFF0000U) #define ADC_ETC_CTRL_PRE_DIVIDER_SHIFT (16U) #define ADC_ETC_CTRL_PRE_DIVIDER(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_PRE_DIVIDER_SHIFT)) & ADC_ETC_CTRL_PRE_DIVIDER_MASK) +#define ADC_ETC_CTRL_DMA_MODE_SEL_MASK (0x20000000U) +#define ADC_ETC_CTRL_DMA_MODE_SEL_SHIFT (29U) +#define ADC_ETC_CTRL_DMA_MODE_SEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_DMA_MODE_SEL_SHIFT)) & ADC_ETC_CTRL_DMA_MODE_SEL_MASK) #define ADC_ETC_CTRL_TSC_BYPASS_MASK (0x40000000U) #define ADC_ETC_CTRL_TSC_BYPASS_SHIFT (30U) #define ADC_ETC_CTRL_TSC_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_TSC_BYPASS_SHIFT)) & ADC_ETC_CTRL_TSC_BYPASS_MASK) #define ADC_ETC_CTRL_SOFTRST_MASK (0x80000000U) #define ADC_ETC_CTRL_SOFTRST_SHIFT (31U) #define ADC_ETC_CTRL_SOFTRST(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_SOFTRST_SHIFT)) & ADC_ETC_CTRL_SOFTRST_MASK) +/*! @} */ /*! @name DONE0_1_IRQ - ETC DONE0 and DONE1 IRQ State Register */ +/*! @{ */ #define ADC_ETC_DONE0_1_IRQ_TRIG0_DONE0_MASK (0x1U) #define ADC_ETC_DONE0_1_IRQ_TRIG0_DONE0_SHIFT (0U) #define ADC_ETC_DONE0_1_IRQ_TRIG0_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG0_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG0_DONE0_MASK) @@ -1582,8 +1701,10 @@ typedef struct { #define ADC_ETC_DONE0_1_IRQ_TRIG7_DONE1_MASK (0x800000U) #define ADC_ETC_DONE0_1_IRQ_TRIG7_DONE1_SHIFT (23U) #define ADC_ETC_DONE0_1_IRQ_TRIG7_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG7_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG7_DONE1_MASK) +/*! @} */ /*! @name DONE2_ERR_IRQ - ETC DONE_2 and DONE_ERR IRQ State Register */ +/*! @{ */ #define ADC_ETC_DONE2_ERR_IRQ_TRIG0_DONE2_MASK (0x1U) #define ADC_ETC_DONE2_ERR_IRQ_TRIG0_DONE2_SHIFT (0U) #define ADC_ETC_DONE2_ERR_IRQ_TRIG0_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG0_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG0_DONE2_MASK) @@ -1632,8 +1753,10 @@ typedef struct { #define ADC_ETC_DONE2_ERR_IRQ_TRIG7_ERR_MASK (0x800000U) #define ADC_ETC_DONE2_ERR_IRQ_TRIG7_ERR_SHIFT (23U) #define ADC_ETC_DONE2_ERR_IRQ_TRIG7_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG7_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG7_ERR_MASK) +/*! @} */ /*! @name DMA_CTRL - ETC DMA control Register */ +/*! @{ */ #define ADC_ETC_DMA_CTRL_TRIG0_ENABLE_MASK (0x1U) #define ADC_ETC_DMA_CTRL_TRIG0_ENABLE_SHIFT (0U) #define ADC_ETC_DMA_CTRL_TRIG0_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG0_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG0_ENABLE_MASK) @@ -1682,12 +1805,10 @@ typedef struct { #define ADC_ETC_DMA_CTRL_TRIG7_REQ_MASK (0x800000U) #define ADC_ETC_DMA_CTRL_TRIG7_REQ_SHIFT (23U) #define ADC_ETC_DMA_CTRL_TRIG7_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG7_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG7_REQ_MASK) +/*! @} */ -/*! @name TRIGn_CTRL - - ETC_TRIG0 Control Register - .. - ETC_TRIG7 Control Register - */ +/*! @name TRIGn_CTRL - ETC_TRIG0 Control Register..ETC_TRIG7 Control Register */ +/*! @{ */ #define ADC_ETC_TRIGn_CTRL_SW_TRIG_MASK (0x1U) #define ADC_ETC_TRIGn_CTRL_SW_TRIG_SHIFT (0U) #define ADC_ETC_TRIGn_CTRL_SW_TRIG(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CTRL_SW_TRIG_SHIFT)) & ADC_ETC_TRIGn_CTRL_SW_TRIG_MASK) @@ -1703,26 +1824,26 @@ typedef struct { #define ADC_ETC_TRIGn_CTRL_SYNC_MODE_MASK (0x10000U) #define ADC_ETC_TRIGn_CTRL_SYNC_MODE_SHIFT (16U) #define ADC_ETC_TRIGn_CTRL_SYNC_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CTRL_SYNC_MODE_SHIFT)) & ADC_ETC_TRIGn_CTRL_SYNC_MODE_MASK) +/*! @} */ /* The count of ADC_ETC_TRIGn_CTRL */ #define ADC_ETC_TRIGn_CTRL_COUNT (8U) -/*! @name TRIGn_COUNTER - - ETC_TRIG0 Counter Register - .. - ETC_TRIG7 Counter Register - */ +/*! @name TRIGn_COUNTER - ETC_TRIG0 Counter Register..ETC_TRIG7 Counter Register */ +/*! @{ */ #define ADC_ETC_TRIGn_COUNTER_INIT_DELAY_MASK (0xFFFFU) #define ADC_ETC_TRIGn_COUNTER_INIT_DELAY_SHIFT (0U) #define ADC_ETC_TRIGn_COUNTER_INIT_DELAY(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_COUNTER_INIT_DELAY_SHIFT)) & ADC_ETC_TRIGn_COUNTER_INIT_DELAY_MASK) #define ADC_ETC_TRIGn_COUNTER_SAMPLE_INTERVAL_MASK (0xFFFF0000U) #define ADC_ETC_TRIGn_COUNTER_SAMPLE_INTERVAL_SHIFT (16U) #define ADC_ETC_TRIGn_COUNTER_SAMPLE_INTERVAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_COUNTER_SAMPLE_INTERVAL_SHIFT)) & ADC_ETC_TRIGn_COUNTER_SAMPLE_INTERVAL_MASK) +/*! @} */ /* The count of ADC_ETC_TRIGn_COUNTER */ #define ADC_ETC_TRIGn_COUNTER_COUNT (8U) /*! @name TRIGn_CHAIN_1_0 - ETC_TRIG Chain 0/1 Register */ +/*! @{ */ #define ADC_ETC_TRIGn_CHAIN_1_0_CSEL0_MASK (0xFU) #define ADC_ETC_TRIGn_CHAIN_1_0_CSEL0_SHIFT (0U) #define ADC_ETC_TRIGn_CHAIN_1_0_CSEL0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_CSEL0_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_CSEL0_MASK) @@ -1747,11 +1868,13 @@ typedef struct { #define ADC_ETC_TRIGn_CHAIN_1_0_IE1_MASK (0x60000000U) #define ADC_ETC_TRIGn_CHAIN_1_0_IE1_SHIFT (29U) #define ADC_ETC_TRIGn_CHAIN_1_0_IE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_IE1_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_IE1_MASK) +/*! @} */ /* The count of ADC_ETC_TRIGn_CHAIN_1_0 */ #define ADC_ETC_TRIGn_CHAIN_1_0_COUNT (8U) /*! @name TRIGn_CHAIN_3_2 - ETC_TRIG Chain 2/3 Register */ +/*! @{ */ #define ADC_ETC_TRIGn_CHAIN_3_2_CSEL2_MASK (0xFU) #define ADC_ETC_TRIGn_CHAIN_3_2_CSEL2_SHIFT (0U) #define ADC_ETC_TRIGn_CHAIN_3_2_CSEL2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_CSEL2_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_CSEL2_MASK) @@ -1776,11 +1899,13 @@ typedef struct { #define ADC_ETC_TRIGn_CHAIN_3_2_IE3_MASK (0x60000000U) #define ADC_ETC_TRIGn_CHAIN_3_2_IE3_SHIFT (29U) #define ADC_ETC_TRIGn_CHAIN_3_2_IE3(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_IE3_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_IE3_MASK) +/*! @} */ /* The count of ADC_ETC_TRIGn_CHAIN_3_2 */ #define ADC_ETC_TRIGn_CHAIN_3_2_COUNT (8U) /*! @name TRIGn_CHAIN_5_4 - ETC_TRIG Chain 4/5 Register */ +/*! @{ */ #define ADC_ETC_TRIGn_CHAIN_5_4_CSEL4_MASK (0xFU) #define ADC_ETC_TRIGn_CHAIN_5_4_CSEL4_SHIFT (0U) #define ADC_ETC_TRIGn_CHAIN_5_4_CSEL4(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_CSEL4_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_CSEL4_MASK) @@ -1805,11 +1930,13 @@ typedef struct { #define ADC_ETC_TRIGn_CHAIN_5_4_IE5_MASK (0x60000000U) #define ADC_ETC_TRIGn_CHAIN_5_4_IE5_SHIFT (29U) #define ADC_ETC_TRIGn_CHAIN_5_4_IE5(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_IE5_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_IE5_MASK) +/*! @} */ /* The count of ADC_ETC_TRIGn_CHAIN_5_4 */ #define ADC_ETC_TRIGn_CHAIN_5_4_COUNT (8U) /*! @name TRIGn_CHAIN_7_6 - ETC_TRIG Chain 6/7 Register */ +/*! @{ */ #define ADC_ETC_TRIGn_CHAIN_7_6_CSEL6_MASK (0xFU) #define ADC_ETC_TRIGn_CHAIN_7_6_CSEL6_SHIFT (0U) #define ADC_ETC_TRIGn_CHAIN_7_6_CSEL6(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_CSEL6_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_CSEL6_MASK) @@ -1834,50 +1961,59 @@ typedef struct { #define ADC_ETC_TRIGn_CHAIN_7_6_IE7_MASK (0x60000000U) #define ADC_ETC_TRIGn_CHAIN_7_6_IE7_SHIFT (29U) #define ADC_ETC_TRIGn_CHAIN_7_6_IE7(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_IE7_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_IE7_MASK) +/*! @} */ /* The count of ADC_ETC_TRIGn_CHAIN_7_6 */ #define ADC_ETC_TRIGn_CHAIN_7_6_COUNT (8U) /*! @name TRIGn_RESULT_1_0 - ETC_TRIG Result Data 1/0 Register */ +/*! @{ */ #define ADC_ETC_TRIGn_RESULT_1_0_DATA0_MASK (0xFFFU) #define ADC_ETC_TRIGn_RESULT_1_0_DATA0_SHIFT (0U) #define ADC_ETC_TRIGn_RESULT_1_0_DATA0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_1_0_DATA0_SHIFT)) & ADC_ETC_TRIGn_RESULT_1_0_DATA0_MASK) #define ADC_ETC_TRIGn_RESULT_1_0_DATA1_MASK (0xFFF0000U) #define ADC_ETC_TRIGn_RESULT_1_0_DATA1_SHIFT (16U) #define ADC_ETC_TRIGn_RESULT_1_0_DATA1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_1_0_DATA1_SHIFT)) & ADC_ETC_TRIGn_RESULT_1_0_DATA1_MASK) +/*! @} */ /* The count of ADC_ETC_TRIGn_RESULT_1_0 */ #define ADC_ETC_TRIGn_RESULT_1_0_COUNT (8U) /*! @name TRIGn_RESULT_3_2 - ETC_TRIG Result Data 3/2 Register */ +/*! @{ */ #define ADC_ETC_TRIGn_RESULT_3_2_DATA2_MASK (0xFFFU) #define ADC_ETC_TRIGn_RESULT_3_2_DATA2_SHIFT (0U) #define ADC_ETC_TRIGn_RESULT_3_2_DATA2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_3_2_DATA2_SHIFT)) & ADC_ETC_TRIGn_RESULT_3_2_DATA2_MASK) #define ADC_ETC_TRIGn_RESULT_3_2_DATA3_MASK (0xFFF0000U) #define ADC_ETC_TRIGn_RESULT_3_2_DATA3_SHIFT (16U) #define ADC_ETC_TRIGn_RESULT_3_2_DATA3(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_3_2_DATA3_SHIFT)) & ADC_ETC_TRIGn_RESULT_3_2_DATA3_MASK) +/*! @} */ /* The count of ADC_ETC_TRIGn_RESULT_3_2 */ #define ADC_ETC_TRIGn_RESULT_3_2_COUNT (8U) /*! @name TRIGn_RESULT_5_4 - ETC_TRIG Result Data 5/4 Register */ +/*! @{ */ #define ADC_ETC_TRIGn_RESULT_5_4_DATA4_MASK (0xFFFU) #define ADC_ETC_TRIGn_RESULT_5_4_DATA4_SHIFT (0U) #define ADC_ETC_TRIGn_RESULT_5_4_DATA4(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_5_4_DATA4_SHIFT)) & ADC_ETC_TRIGn_RESULT_5_4_DATA4_MASK) #define ADC_ETC_TRIGn_RESULT_5_4_DATA5_MASK (0xFFF0000U) #define ADC_ETC_TRIGn_RESULT_5_4_DATA5_SHIFT (16U) #define ADC_ETC_TRIGn_RESULT_5_4_DATA5(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_5_4_DATA5_SHIFT)) & ADC_ETC_TRIGn_RESULT_5_4_DATA5_MASK) +/*! @} */ /* The count of ADC_ETC_TRIGn_RESULT_5_4 */ #define ADC_ETC_TRIGn_RESULT_5_4_COUNT (8U) /*! @name TRIGn_RESULT_7_6 - ETC_TRIG Result Data 7/6 Register */ +/*! @{ */ #define ADC_ETC_TRIGn_RESULT_7_6_DATA6_MASK (0xFFFU) #define ADC_ETC_TRIGn_RESULT_7_6_DATA6_SHIFT (0U) #define ADC_ETC_TRIGn_RESULT_7_6_DATA6(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_7_6_DATA6_SHIFT)) & ADC_ETC_TRIGn_RESULT_7_6_DATA6_MASK) #define ADC_ETC_TRIGn_RESULT_7_6_DATA7_MASK (0xFFF0000U) #define ADC_ETC_TRIGn_RESULT_7_6_DATA7_SHIFT (16U) #define ADC_ETC_TRIGn_RESULT_7_6_DATA7(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_7_6_DATA7_SHIFT)) & ADC_ETC_TRIGn_RESULT_7_6_DATA7_MASK) +/*! @} */ /* The count of ADC_ETC_TRIGn_RESULT_7_6 */ #define ADC_ETC_TRIGn_RESULT_7_6_COUNT (8U) @@ -1936,133 +2072,496 @@ typedef struct { */ /*! @name MPR - Master Priviledge Registers */ +/*! @{ */ #define AIPSTZ_MPR_MPROT5_MASK (0xF00U) #define AIPSTZ_MPR_MPROT5_SHIFT (8U) +/*! MPROT5 + * 0bxxx0..Accesses from this master are forced to user-mode (ips_supervisor_access is forced to zero) regardless of the hprot[1] access attribute. + * 0bxxx1..Accesses from this master are not forced to user-mode. The hprot[1] access attribute is used directly to determine ips_supervisor_access. + * 0bxx0x..This master is not trusted for write accesses. + * 0bxx1x..This master is trusted for write accesses. + * 0bx0xx..This master is not trusted for read accesses. + * 0bx1xx..This master is trusted for read accesses. + * 0b1xxx..Write accesses from this master are allowed to be buffered + */ #define AIPSTZ_MPR_MPROT5(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT5_SHIFT)) & AIPSTZ_MPR_MPROT5_MASK) #define AIPSTZ_MPR_MPROT3_MASK (0xF0000U) #define AIPSTZ_MPR_MPROT3_SHIFT (16U) +/*! MPROT3 + * 0bxxx0..Accesses from this master are forced to user-mode (ips_supervisor_access is forced to zero) regardless of the hprot[1] access attribute. + * 0bxxx1..Accesses from this master are not forced to user-mode. The hprot[1] access attribute is used directly to determine ips_supervisor_access. + * 0bxx0x..This master is not trusted for write accesses. + * 0bxx1x..This master is trusted for write accesses. + * 0bx0xx..This master is not trusted for read accesses. + * 0bx1xx..This master is trusted for read accesses. + * 0b1xxx..Write accesses from this master are allowed to be buffered + */ #define AIPSTZ_MPR_MPROT3(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT3_SHIFT)) & AIPSTZ_MPR_MPROT3_MASK) #define AIPSTZ_MPR_MPROT2_MASK (0xF00000U) #define AIPSTZ_MPR_MPROT2_SHIFT (20U) +/*! MPROT2 + * 0bxxx0..Accesses from this master are forced to user-mode (ips_supervisor_access is forced to zero) regardless of the hprot[1] access attribute. + * 0bxxx1..Accesses from this master are not forced to user-mode. The hprot[1] access attribute is used directly to determine ips_supervisor_access. + * 0bxx0x..This master is not trusted for write accesses. + * 0bxx1x..This master is trusted for write accesses. + * 0bx0xx..This master is not trusted for read accesses. + * 0bx1xx..This master is trusted for read accesses. + * 0b1xxx..Write accesses from this master are allowed to be buffered + */ #define AIPSTZ_MPR_MPROT2(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT2_SHIFT)) & AIPSTZ_MPR_MPROT2_MASK) #define AIPSTZ_MPR_MPROT1_MASK (0xF000000U) #define AIPSTZ_MPR_MPROT1_SHIFT (24U) +/*! MPROT1 + * 0bxxx0..Accesses from this master are forced to user-mode (ips_supervisor_access is forced to zero) regardless of the hprot[1] access attribute. + * 0bxxx1..Accesses from this master are not forced to user-mode. The hprot[1] access attribute is used directly to determine ips_supervisor_access. + * 0bxx0x..This master is not trusted for write accesses. + * 0bxx1x..This master is trusted for write accesses. + * 0bx0xx..This master is not trusted for read accesses. + * 0bx1xx..This master is trusted for read accesses. + * 0b1xxx..Write accesses from this master are allowed to be buffered + */ #define AIPSTZ_MPR_MPROT1(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT1_SHIFT)) & AIPSTZ_MPR_MPROT1_MASK) #define AIPSTZ_MPR_MPROT0_MASK (0xF0000000U) #define AIPSTZ_MPR_MPROT0_SHIFT (28U) +/*! MPROT0 + * 0bxxx0..Accesses from this master are forced to user-mode (ips_supervisor_access is forced to zero) regardless of the hprot[1] access attribute. + * 0bxxx1..Accesses from this master are not forced to user-mode. The hprot[1] access attribute is used directly to determine ips_supervisor_access. + * 0bxx0x..This master is not trusted for write accesses. + * 0bxx1x..This master is trusted for write accesses. + * 0bx0xx..This master is not trusted for read accesses. + * 0bx1xx..This master is trusted for read accesses. + * 0b1xxx..Write accesses from this master are allowed to be buffered + */ #define AIPSTZ_MPR_MPROT0(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT0_SHIFT)) & AIPSTZ_MPR_MPROT0_MASK) +/*! @} */ /*! @name OPACR - Off-Platform Peripheral Access Control Registers */ +/*! @{ */ #define AIPSTZ_OPACR_OPAC7_MASK (0xFU) #define AIPSTZ_OPACR_OPAC7_SHIFT (0U) +/*! OPAC7 + * 0bxxx0..Accesses from an untrusted master are allowed. + * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bxx0x..This peripheral allows write accesses. + * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. + * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must be set. If not, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. + */ #define AIPSTZ_OPACR_OPAC7(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC7_SHIFT)) & AIPSTZ_OPACR_OPAC7_MASK) #define AIPSTZ_OPACR_OPAC6_MASK (0xF0U) #define AIPSTZ_OPACR_OPAC6_SHIFT (4U) +/*! OPAC6 + * 0bxxx0..Accesses from an untrusted master are allowed. + * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bxx0x..This peripheral allows write accesses. + * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. + * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must be set. If not, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. + */ #define AIPSTZ_OPACR_OPAC6(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC6_SHIFT)) & AIPSTZ_OPACR_OPAC6_MASK) #define AIPSTZ_OPACR_OPAC5_MASK (0xF00U) #define AIPSTZ_OPACR_OPAC5_SHIFT (8U) +/*! OPAC5 + * 0bxxx0..Accesses from an untrusted master are allowed. + * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bxx0x..This peripheral allows write accesses. + * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. + * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must be set. If not, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. + */ #define AIPSTZ_OPACR_OPAC5(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC5_SHIFT)) & AIPSTZ_OPACR_OPAC5_MASK) #define AIPSTZ_OPACR_OPAC4_MASK (0xF000U) #define AIPSTZ_OPACR_OPAC4_SHIFT (12U) +/*! OPAC4 + * 0bxxx0..Accesses from an untrusted master are allowed. + * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bxx0x..This peripheral allows write accesses. + * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. + * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must be set. If not, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. + */ #define AIPSTZ_OPACR_OPAC4(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC4_SHIFT)) & AIPSTZ_OPACR_OPAC4_MASK) #define AIPSTZ_OPACR_OPAC3_MASK (0xF0000U) #define AIPSTZ_OPACR_OPAC3_SHIFT (16U) +/*! OPAC3 + * 0bxxx0..Accesses from an untrusted master are allowed. + * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bxx0x..This peripheral allows write accesses. + * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. + * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must be set. If not, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. + */ #define AIPSTZ_OPACR_OPAC3(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC3_SHIFT)) & AIPSTZ_OPACR_OPAC3_MASK) #define AIPSTZ_OPACR_OPAC2_MASK (0xF00000U) #define AIPSTZ_OPACR_OPAC2_SHIFT (20U) +/*! OPAC2 + * 0bxxx0..Accesses from an untrusted master are allowed. + * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bxx0x..This peripheral allows write accesses. + * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. + * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must be set. If not, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. + */ #define AIPSTZ_OPACR_OPAC2(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC2_SHIFT)) & AIPSTZ_OPACR_OPAC2_MASK) #define AIPSTZ_OPACR_OPAC1_MASK (0xF000000U) #define AIPSTZ_OPACR_OPAC1_SHIFT (24U) +/*! OPAC1 + * 0bxxx0..Accesses from an untrusted master are allowed. + * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bxx0x..This peripheral allows write accesses. + * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. + * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must be set. If not, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. + */ #define AIPSTZ_OPACR_OPAC1(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC1_SHIFT)) & AIPSTZ_OPACR_OPAC1_MASK) #define AIPSTZ_OPACR_OPAC0_MASK (0xF0000000U) #define AIPSTZ_OPACR_OPAC0_SHIFT (28U) +/*! OPAC0 + * 0bxxx0..Accesses from an untrusted master are allowed. + * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bxx0x..This peripheral allows write accesses. + * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. + * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must be set. If not, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. + */ #define AIPSTZ_OPACR_OPAC0(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC0_SHIFT)) & AIPSTZ_OPACR_OPAC0_MASK) +/*! @} */ /*! @name OPACR1 - Off-Platform Peripheral Access Control Registers */ +/*! @{ */ #define AIPSTZ_OPACR1_OPAC15_MASK (0xFU) #define AIPSTZ_OPACR1_OPAC15_SHIFT (0U) +/*! OPAC15 + * 0bxxx0..Accesses from an untrusted master are allowed. + * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bxx0x..This peripheral allows write accesses. + * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. + * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must be set. If not, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. + */ #define AIPSTZ_OPACR1_OPAC15(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC15_SHIFT)) & AIPSTZ_OPACR1_OPAC15_MASK) #define AIPSTZ_OPACR1_OPAC14_MASK (0xF0U) #define AIPSTZ_OPACR1_OPAC14_SHIFT (4U) +/*! OPAC14 + * 0bxxx0..Accesses from an untrusted master are allowed. + * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bxx0x..This peripheral allows write accesses. + * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. + * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must be set. If not, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. + */ #define AIPSTZ_OPACR1_OPAC14(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC14_SHIFT)) & AIPSTZ_OPACR1_OPAC14_MASK) #define AIPSTZ_OPACR1_OPAC13_MASK (0xF00U) #define AIPSTZ_OPACR1_OPAC13_SHIFT (8U) +/*! OPAC13 + * 0bxxx0..Accesses from an untrusted master are allowed. + * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bxx0x..This peripheral allows write accesses. + * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. + * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must be set. If not, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. + */ #define AIPSTZ_OPACR1_OPAC13(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC13_SHIFT)) & AIPSTZ_OPACR1_OPAC13_MASK) #define AIPSTZ_OPACR1_OPAC12_MASK (0xF000U) #define AIPSTZ_OPACR1_OPAC12_SHIFT (12U) +/*! OPAC12 + * 0bxxx0..Accesses from an untrusted master are allowed. + * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bxx0x..This peripheral allows write accesses. + * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. + * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must be set. If not, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. + */ #define AIPSTZ_OPACR1_OPAC12(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC12_SHIFT)) & AIPSTZ_OPACR1_OPAC12_MASK) #define AIPSTZ_OPACR1_OPAC11_MASK (0xF0000U) #define AIPSTZ_OPACR1_OPAC11_SHIFT (16U) +/*! OPAC11 + * 0bxxx0..Accesses from an untrusted master are allowed. + * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bxx0x..This peripheral allows write accesses. + * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. + * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must be set. If not, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. + */ #define AIPSTZ_OPACR1_OPAC11(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC11_SHIFT)) & AIPSTZ_OPACR1_OPAC11_MASK) #define AIPSTZ_OPACR1_OPAC10_MASK (0xF00000U) #define AIPSTZ_OPACR1_OPAC10_SHIFT (20U) +/*! OPAC10 + * 0bxxx0..Accesses from an untrusted master are allowed. + * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bxx0x..This peripheral allows write accesses. + * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. + * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must be set. If not, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. + */ #define AIPSTZ_OPACR1_OPAC10(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC10_SHIFT)) & AIPSTZ_OPACR1_OPAC10_MASK) #define AIPSTZ_OPACR1_OPAC9_MASK (0xF000000U) #define AIPSTZ_OPACR1_OPAC9_SHIFT (24U) +/*! OPAC9 + * 0bxxx0..Accesses from an untrusted master are allowed. + * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bxx0x..This peripheral allows write accesses. + * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. + * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must be set. If not, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. + */ #define AIPSTZ_OPACR1_OPAC9(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC9_SHIFT)) & AIPSTZ_OPACR1_OPAC9_MASK) #define AIPSTZ_OPACR1_OPAC8_MASK (0xF0000000U) #define AIPSTZ_OPACR1_OPAC8_SHIFT (28U) +/*! OPAC8 + * 0bxxx0..Accesses from an untrusted master are allowed. + * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bxx0x..This peripheral allows write accesses. + * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. + * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must be set. If not, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. + */ #define AIPSTZ_OPACR1_OPAC8(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC8_SHIFT)) & AIPSTZ_OPACR1_OPAC8_MASK) +/*! @} */ /*! @name OPACR2 - Off-Platform Peripheral Access Control Registers */ +/*! @{ */ #define AIPSTZ_OPACR2_OPAC23_MASK (0xFU) #define AIPSTZ_OPACR2_OPAC23_SHIFT (0U) +/*! OPAC23 + * 0bxxx0..Accesses from an untrusted master are allowed. + * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bxx0x..This peripheral allows write accesses. + * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. + * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must be set. If not, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. + */ #define AIPSTZ_OPACR2_OPAC23(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC23_SHIFT)) & AIPSTZ_OPACR2_OPAC23_MASK) #define AIPSTZ_OPACR2_OPAC22_MASK (0xF0U) #define AIPSTZ_OPACR2_OPAC22_SHIFT (4U) +/*! OPAC22 + * 0bxxx0..Accesses from an untrusted master are allowed. + * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bxx0x..This peripheral allows write accesses. + * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. + * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must be set. If not, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. + */ #define AIPSTZ_OPACR2_OPAC22(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC22_SHIFT)) & AIPSTZ_OPACR2_OPAC22_MASK) #define AIPSTZ_OPACR2_OPAC21_MASK (0xF00U) #define AIPSTZ_OPACR2_OPAC21_SHIFT (8U) +/*! OPAC21 + * 0bxxx0..Accesses from an untrusted master are allowed. + * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bxx0x..This peripheral allows write accesses. + * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. + * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must be set. If not, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. + */ #define AIPSTZ_OPACR2_OPAC21(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC21_SHIFT)) & AIPSTZ_OPACR2_OPAC21_MASK) #define AIPSTZ_OPACR2_OPAC20_MASK (0xF000U) #define AIPSTZ_OPACR2_OPAC20_SHIFT (12U) +/*! OPAC20 + * 0bxxx0..Accesses from an untrusted master are allowed. + * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bxx0x..This peripheral allows write accesses. + * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. + * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must be set. If not, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. + */ #define AIPSTZ_OPACR2_OPAC20(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC20_SHIFT)) & AIPSTZ_OPACR2_OPAC20_MASK) #define AIPSTZ_OPACR2_OPAC19_MASK (0xF0000U) #define AIPSTZ_OPACR2_OPAC19_SHIFT (16U) +/*! OPAC19 + * 0bxxx0..Accesses from an untrusted master are allowed. + * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bxx0x..This peripheral allows write accesses. + * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. + * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must be set. If not, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. + */ #define AIPSTZ_OPACR2_OPAC19(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC19_SHIFT)) & AIPSTZ_OPACR2_OPAC19_MASK) #define AIPSTZ_OPACR2_OPAC18_MASK (0xF00000U) #define AIPSTZ_OPACR2_OPAC18_SHIFT (20U) +/*! OPAC18 + * 0bxxx0..Accesses from an untrusted master are allowed. + * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bxx0x..This peripheral allows write accesses. + * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. + * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must be set. If not, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. + */ #define AIPSTZ_OPACR2_OPAC18(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC18_SHIFT)) & AIPSTZ_OPACR2_OPAC18_MASK) #define AIPSTZ_OPACR2_OPAC17_MASK (0xF000000U) #define AIPSTZ_OPACR2_OPAC17_SHIFT (24U) +/*! OPAC17 + * 0bxxx0..Accesses from an untrusted master are allowed. + * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bxx0x..This peripheral allows write accesses. + * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. + * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must be set. If not, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. + */ #define AIPSTZ_OPACR2_OPAC17(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC17_SHIFT)) & AIPSTZ_OPACR2_OPAC17_MASK) #define AIPSTZ_OPACR2_OPAC16_MASK (0xF0000000U) #define AIPSTZ_OPACR2_OPAC16_SHIFT (28U) +/*! OPAC16 + * 0bxxx0..Accesses from an untrusted master are allowed. + * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bxx0x..This peripheral allows write accesses. + * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. + * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must be set. If not, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. + */ #define AIPSTZ_OPACR2_OPAC16(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC16_SHIFT)) & AIPSTZ_OPACR2_OPAC16_MASK) +/*! @} */ /*! @name OPACR3 - Off-Platform Peripheral Access Control Registers */ +/*! @{ */ #define AIPSTZ_OPACR3_OPAC31_MASK (0xFU) #define AIPSTZ_OPACR3_OPAC31_SHIFT (0U) +/*! OPAC31 + * 0bxxx0..Accesses from an untrusted master are allowed. + * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bxx0x..This peripheral allows write accesses. + * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. + * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must be set. If not, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. + */ #define AIPSTZ_OPACR3_OPAC31(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC31_SHIFT)) & AIPSTZ_OPACR3_OPAC31_MASK) #define AIPSTZ_OPACR3_OPAC30_MASK (0xF0U) #define AIPSTZ_OPACR3_OPAC30_SHIFT (4U) +/*! OPAC30 + * 0bxxx0..Accesses from an untrusted master are allowed. + * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bxx0x..This peripheral allows write accesses. + * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. + * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must be set. If not, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. + */ #define AIPSTZ_OPACR3_OPAC30(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC30_SHIFT)) & AIPSTZ_OPACR3_OPAC30_MASK) #define AIPSTZ_OPACR3_OPAC29_MASK (0xF00U) #define AIPSTZ_OPACR3_OPAC29_SHIFT (8U) +/*! OPAC29 + * 0bxxx0..Accesses from an untrusted master are allowed. + * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bxx0x..This peripheral allows write accesses. + * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. + * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must be set. If not, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. + */ #define AIPSTZ_OPACR3_OPAC29(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC29_SHIFT)) & AIPSTZ_OPACR3_OPAC29_MASK) #define AIPSTZ_OPACR3_OPAC28_MASK (0xF000U) #define AIPSTZ_OPACR3_OPAC28_SHIFT (12U) +/*! OPAC28 + * 0bxxx0..Accesses from an untrusted master are allowed. + * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bxx0x..This peripheral allows write accesses. + * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. + * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must be set. If not, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. + */ #define AIPSTZ_OPACR3_OPAC28(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC28_SHIFT)) & AIPSTZ_OPACR3_OPAC28_MASK) #define AIPSTZ_OPACR3_OPAC27_MASK (0xF0000U) #define AIPSTZ_OPACR3_OPAC27_SHIFT (16U) +/*! OPAC27 + * 0bxxx0..Accesses from an untrusted master are allowed. + * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bxx0x..This peripheral allows write accesses. + * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. + * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must be set. If not, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. + */ #define AIPSTZ_OPACR3_OPAC27(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC27_SHIFT)) & AIPSTZ_OPACR3_OPAC27_MASK) #define AIPSTZ_OPACR3_OPAC26_MASK (0xF00000U) #define AIPSTZ_OPACR3_OPAC26_SHIFT (20U) +/*! OPAC26 + * 0bxxx0..Accesses from an untrusted master are allowed. + * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bxx0x..This peripheral allows write accesses. + * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. + * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must be set. If not, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. + */ #define AIPSTZ_OPACR3_OPAC26(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC26_SHIFT)) & AIPSTZ_OPACR3_OPAC26_MASK) #define AIPSTZ_OPACR3_OPAC25_MASK (0xF000000U) #define AIPSTZ_OPACR3_OPAC25_SHIFT (24U) +/*! OPAC25 + * 0bxxx0..Accesses from an untrusted master are allowed. + * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bxx0x..This peripheral allows write accesses. + * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. + * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must be set. If not, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. + */ #define AIPSTZ_OPACR3_OPAC25(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC25_SHIFT)) & AIPSTZ_OPACR3_OPAC25_MASK) #define AIPSTZ_OPACR3_OPAC24_MASK (0xF0000000U) #define AIPSTZ_OPACR3_OPAC24_SHIFT (28U) +/*! OPAC24 + * 0bxxx0..Accesses from an untrusted master are allowed. + * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bxx0x..This peripheral allows write accesses. + * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. + * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must be set. If not, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. + */ #define AIPSTZ_OPACR3_OPAC24(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC24_SHIFT)) & AIPSTZ_OPACR3_OPAC24_MASK) +/*! @} */ /*! @name OPACR4 - Off-Platform Peripheral Access Control Registers */ +/*! @{ */ #define AIPSTZ_OPACR4_OPAC33_MASK (0xF000000U) #define AIPSTZ_OPACR4_OPAC33_SHIFT (24U) +/*! OPAC33 + * 0bxxx0..Accesses from an untrusted master are allowed. + * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bxx0x..This peripheral allows write accesses. + * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. + * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must be set. If not, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. + */ #define AIPSTZ_OPACR4_OPAC33(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR4_OPAC33_SHIFT)) & AIPSTZ_OPACR4_OPAC33_MASK) #define AIPSTZ_OPACR4_OPAC32_MASK (0xF0000000U) #define AIPSTZ_OPACR4_OPAC32_SHIFT (28U) +/*! OPAC32 + * 0bxxx0..Accesses from an untrusted master are allowed. + * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bxx0x..This peripheral allows write accesses. + * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. + * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must be set. If not, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. + */ #define AIPSTZ_OPACR4_OPAC32(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR4_OPAC32_SHIFT)) & AIPSTZ_OPACR4_OPAC32_MASK) +/*! @} */ /*! @@ -2124,59 +2623,159 @@ typedef struct { */ /*! @name BFCRT01 - Boolean Function Term 0 and 1 Configuration Register for EVENTn */ +/*! @{ */ #define AOI_BFCRT01_PT1_DC_MASK (0x3U) #define AOI_BFCRT01_PT1_DC_SHIFT (0U) +/*! PT1_DC - Product term 1, D input configuration + * 0b00..Force the D input in this product term to a logical zero + * 0b01..Pass the D input in this product term + * 0b10..Complement the D input in this product term + * 0b11..Force the D input in this product term to a logical one + */ #define AOI_BFCRT01_PT1_DC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT1_DC_SHIFT)) & AOI_BFCRT01_PT1_DC_MASK) #define AOI_BFCRT01_PT1_CC_MASK (0xCU) #define AOI_BFCRT01_PT1_CC_SHIFT (2U) +/*! PT1_CC - Product term 1, C input configuration + * 0b00..Force the C input in this product term to a logical zero + * 0b01..Pass the C input in this product term + * 0b10..Complement the C input in this product term + * 0b11..Force the C input in this product term to a logical one + */ #define AOI_BFCRT01_PT1_CC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT1_CC_SHIFT)) & AOI_BFCRT01_PT1_CC_MASK) #define AOI_BFCRT01_PT1_BC_MASK (0x30U) #define AOI_BFCRT01_PT1_BC_SHIFT (4U) +/*! PT1_BC - Product term 1, B input configuration + * 0b00..Force the B input in this product term to a logical zero + * 0b01..Pass the B input in this product term + * 0b10..Complement the B input in this product term + * 0b11..Force the B input in this product term to a logical one + */ #define AOI_BFCRT01_PT1_BC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT1_BC_SHIFT)) & AOI_BFCRT01_PT1_BC_MASK) #define AOI_BFCRT01_PT1_AC_MASK (0xC0U) #define AOI_BFCRT01_PT1_AC_SHIFT (6U) +/*! PT1_AC - Product term 1, A input configuration + * 0b00..Force the A input in this product term to a logical zero + * 0b01..Pass the A input in this product term + * 0b10..Complement the A input in this product term + * 0b11..Force the A input in this product term to a logical one + */ #define AOI_BFCRT01_PT1_AC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT1_AC_SHIFT)) & AOI_BFCRT01_PT1_AC_MASK) #define AOI_BFCRT01_PT0_DC_MASK (0x300U) #define AOI_BFCRT01_PT0_DC_SHIFT (8U) +/*! PT0_DC - Product term 0, D input configuration + * 0b00..Force the D input in this product term to a logical zero + * 0b01..Pass the D input in this product term + * 0b10..Complement the D input in this product term + * 0b11..Force the D input in this product term to a logical one + */ #define AOI_BFCRT01_PT0_DC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT0_DC_SHIFT)) & AOI_BFCRT01_PT0_DC_MASK) #define AOI_BFCRT01_PT0_CC_MASK (0xC00U) #define AOI_BFCRT01_PT0_CC_SHIFT (10U) +/*! PT0_CC - Product term 0, C input configuration + * 0b00..Force the C input in this product term to a logical zero + * 0b01..Pass the C input in this product term + * 0b10..Complement the C input in this product term + * 0b11..Force the C input in this product term to a logical one + */ #define AOI_BFCRT01_PT0_CC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT0_CC_SHIFT)) & AOI_BFCRT01_PT0_CC_MASK) #define AOI_BFCRT01_PT0_BC_MASK (0x3000U) #define AOI_BFCRT01_PT0_BC_SHIFT (12U) +/*! PT0_BC - Product term 0, B input configuration + * 0b00..Force the B input in this product term to a logical zero + * 0b01..Pass the B input in this product term + * 0b10..Complement the B input in this product term + * 0b11..Force the B input in this product term to a logical one + */ #define AOI_BFCRT01_PT0_BC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT0_BC_SHIFT)) & AOI_BFCRT01_PT0_BC_MASK) #define AOI_BFCRT01_PT0_AC_MASK (0xC000U) #define AOI_BFCRT01_PT0_AC_SHIFT (14U) +/*! PT0_AC - Product term 0, A input configuration + * 0b00..Force the A input in this product term to a logical zero + * 0b01..Pass the A input in this product term + * 0b10..Complement the A input in this product term + * 0b11..Force the A input in this product term to a logical one + */ #define AOI_BFCRT01_PT0_AC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT0_AC_SHIFT)) & AOI_BFCRT01_PT0_AC_MASK) +/*! @} */ /* The count of AOI_BFCRT01 */ #define AOI_BFCRT01_COUNT (4U) /*! @name BFCRT23 - Boolean Function Term 2 and 3 Configuration Register for EVENTn */ +/*! @{ */ #define AOI_BFCRT23_PT3_DC_MASK (0x3U) #define AOI_BFCRT23_PT3_DC_SHIFT (0U) +/*! PT3_DC - Product term 3, D input configuration + * 0b00..Force the D input in this product term to a logical zero + * 0b01..Pass the D input in this product term + * 0b10..Complement the D input in this product term + * 0b11..Force the D input in this product term to a logical one + */ #define AOI_BFCRT23_PT3_DC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT3_DC_SHIFT)) & AOI_BFCRT23_PT3_DC_MASK) #define AOI_BFCRT23_PT3_CC_MASK (0xCU) #define AOI_BFCRT23_PT3_CC_SHIFT (2U) +/*! PT3_CC - Product term 3, C input configuration + * 0b00..Force the C input in this product term to a logical zero + * 0b01..Pass the C input in this product term + * 0b10..Complement the C input in this product term + * 0b11..Force the C input in this product term to a logical one + */ #define AOI_BFCRT23_PT3_CC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT3_CC_SHIFT)) & AOI_BFCRT23_PT3_CC_MASK) #define AOI_BFCRT23_PT3_BC_MASK (0x30U) #define AOI_BFCRT23_PT3_BC_SHIFT (4U) +/*! PT3_BC - Product term 3, B input configuration + * 0b00..Force the B input in this product term to a logical zero + * 0b01..Pass the B input in this product term + * 0b10..Complement the B input in this product term + * 0b11..Force the B input in this product term to a logical one + */ #define AOI_BFCRT23_PT3_BC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT3_BC_SHIFT)) & AOI_BFCRT23_PT3_BC_MASK) #define AOI_BFCRT23_PT3_AC_MASK (0xC0U) #define AOI_BFCRT23_PT3_AC_SHIFT (6U) +/*! PT3_AC - Product term 3, A input configuration + * 0b00..Force the A input in this product term to a logical zero + * 0b01..Pass the A input in this product term + * 0b10..Complement the A input in this product term + * 0b11..Force the A input in this product term to a logical one + */ #define AOI_BFCRT23_PT3_AC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT3_AC_SHIFT)) & AOI_BFCRT23_PT3_AC_MASK) #define AOI_BFCRT23_PT2_DC_MASK (0x300U) #define AOI_BFCRT23_PT2_DC_SHIFT (8U) +/*! PT2_DC - Product term 2, D input configuration + * 0b00..Force the D input in this product term to a logical zero + * 0b01..Pass the D input in this product term + * 0b10..Complement the D input in this product term + * 0b11..Force the D input in this product term to a logical one + */ #define AOI_BFCRT23_PT2_DC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT2_DC_SHIFT)) & AOI_BFCRT23_PT2_DC_MASK) #define AOI_BFCRT23_PT2_CC_MASK (0xC00U) #define AOI_BFCRT23_PT2_CC_SHIFT (10U) +/*! PT2_CC - Product term 2, C input configuration + * 0b00..Force the C input in this product term to a logical zero + * 0b01..Pass the C input in this product term + * 0b10..Complement the C input in this product term + * 0b11..Force the C input in this product term to a logical one + */ #define AOI_BFCRT23_PT2_CC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT2_CC_SHIFT)) & AOI_BFCRT23_PT2_CC_MASK) #define AOI_BFCRT23_PT2_BC_MASK (0x3000U) #define AOI_BFCRT23_PT2_BC_SHIFT (12U) +/*! PT2_BC - Product term 2, B input configuration + * 0b00..Force the B input in this product term to a logical zero + * 0b01..Pass the B input in this product term + * 0b10..Complement the B input in this product term + * 0b11..Force the B input in this product term to a logical one + */ #define AOI_BFCRT23_PT2_BC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT2_BC_SHIFT)) & AOI_BFCRT23_PT2_BC_MASK) #define AOI_BFCRT23_PT2_AC_MASK (0xC000U) #define AOI_BFCRT23_PT2_AC_SHIFT (14U) +/*! PT2_AC - Product term 2, A input configuration + * 0b00..Force the A input in this product term to a logical zero + * 0b01..Pass the A input in this product term + * 0b10..Complement the A input in this product term + * 0b11..Force the A input in this product term to a logical one + */ #define AOI_BFCRT23_PT2_AC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT2_AC_SHIFT)) & AOI_BFCRT23_PT2_AC_MASK) +/*! @} */ /* The count of AOI_BFCRT23 */ #define AOI_BFCRT23_COUNT (4U) @@ -2247,8 +2846,13 @@ typedef struct { */ /*! @name CTRL - BEE Control Register */ +/*! @{ */ #define BEE_CTRL_BEE_ENABLE_MASK (0x1U) #define BEE_CTRL_BEE_ENABLE_SHIFT (0U) +/*! BEE_ENABLE + * 0b0..Disable BEE + * 0b1..Enable BEE + */ #define BEE_CTRL_BEE_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_BEE_ENABLE_SHIFT)) & BEE_CTRL_BEE_ENABLE_MASK) #define BEE_CTRL_CTRL_CLK_EN_MASK (0x2U) #define BEE_CTRL_CTRL_CLK_EN_SHIFT (1U) @@ -2261,24 +2865,40 @@ typedef struct { #define BEE_CTRL_KEY_VALID(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_KEY_VALID_SHIFT)) & BEE_CTRL_KEY_VALID_MASK) #define BEE_CTRL_KEY_REGION_SEL_MASK (0x20U) #define BEE_CTRL_KEY_REGION_SEL_SHIFT (5U) +/*! KEY_REGION_SEL + * 0b0..Load AES key for region0 + * 0b1..Load AES key for region1 + */ #define BEE_CTRL_KEY_REGION_SEL(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_KEY_REGION_SEL_SHIFT)) & BEE_CTRL_KEY_REGION_SEL_MASK) #define BEE_CTRL_AC_PROT_EN_MASK (0x40U) #define BEE_CTRL_AC_PROT_EN_SHIFT (6U) #define BEE_CTRL_AC_PROT_EN(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_AC_PROT_EN_SHIFT)) & BEE_CTRL_AC_PROT_EN_MASK) #define BEE_CTRL_LITTLE_ENDIAN_MASK (0x80U) #define BEE_CTRL_LITTLE_ENDIAN_SHIFT (7U) +/*! LITTLE_ENDIAN + * 0b0..The input and output data of the AES core is swapped as below: {B15,B14,B13,B12,B11,B10,B9,B8, B7,B6,B5,B4,B3,B2,B1,B0} swap to {B0,B1,B2,B3,B4,B5,B6,B7, B8,B9,B10,B11,B12,B13,B14,B15}, where B0~B15 refers to Byte0 to Byte15. + * 0b1..The input and output data of AES core is not swapped. + */ #define BEE_CTRL_LITTLE_ENDIAN(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_LITTLE_ENDIAN_SHIFT)) & BEE_CTRL_LITTLE_ENDIAN_MASK) #define BEE_CTRL_SECURITY_LEVEL_R0_MASK (0x300U) #define BEE_CTRL_SECURITY_LEVEL_R0_SHIFT (8U) #define BEE_CTRL_SECURITY_LEVEL_R0(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_SECURITY_LEVEL_R0_SHIFT)) & BEE_CTRL_SECURITY_LEVEL_R0_MASK) #define BEE_CTRL_CTRL_AES_MODE_R0_MASK (0x400U) #define BEE_CTRL_CTRL_AES_MODE_R0_SHIFT (10U) +/*! CTRL_AES_MODE_R0 + * 0b0..ECB + * 0b1..CTR + */ #define BEE_CTRL_CTRL_AES_MODE_R0(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_AES_MODE_R0_SHIFT)) & BEE_CTRL_CTRL_AES_MODE_R0_MASK) #define BEE_CTRL_SECURITY_LEVEL_R1_MASK (0x3000U) #define BEE_CTRL_SECURITY_LEVEL_R1_SHIFT (12U) #define BEE_CTRL_SECURITY_LEVEL_R1(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_SECURITY_LEVEL_R1_SHIFT)) & BEE_CTRL_SECURITY_LEVEL_R1_MASK) #define BEE_CTRL_CTRL_AES_MODE_R1_MASK (0x4000U) #define BEE_CTRL_CTRL_AES_MODE_R1_SHIFT (14U) +/*! CTRL_AES_MODE_R1 + * 0b0..ECB + * 0b1..CTR + */ #define BEE_CTRL_CTRL_AES_MODE_R1(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_AES_MODE_R1_SHIFT)) & BEE_CTRL_CTRL_AES_MODE_R1_MASK) #define BEE_CTRL_BEE_ENABLE_LOCK_MASK (0x10000U) #define BEE_CTRL_BEE_ENABLE_LOCK_SHIFT (16U) @@ -2322,100 +2942,135 @@ typedef struct { #define BEE_CTRL_REGION1_KEY_LOCK_MASK (0x80000000U) #define BEE_CTRL_REGION1_KEY_LOCK_SHIFT (31U) #define BEE_CTRL_REGION1_KEY_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_REGION1_KEY_LOCK_SHIFT)) & BEE_CTRL_REGION1_KEY_LOCK_MASK) +/*! @} */ /*! @name ADDR_OFFSET0 - */ +/*! @{ */ #define BEE_ADDR_OFFSET0_ADDR_OFFSET0_MASK (0xFFFFU) #define BEE_ADDR_OFFSET0_ADDR_OFFSET0_SHIFT (0U) #define BEE_ADDR_OFFSET0_ADDR_OFFSET0(x) (((uint32_t)(((uint32_t)(x)) << BEE_ADDR_OFFSET0_ADDR_OFFSET0_SHIFT)) & BEE_ADDR_OFFSET0_ADDR_OFFSET0_MASK) #define BEE_ADDR_OFFSET0_ADDR_OFFSET0_LOCK_MASK (0xFFFF0000U) #define BEE_ADDR_OFFSET0_ADDR_OFFSET0_LOCK_SHIFT (16U) #define BEE_ADDR_OFFSET0_ADDR_OFFSET0_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_ADDR_OFFSET0_ADDR_OFFSET0_LOCK_SHIFT)) & BEE_ADDR_OFFSET0_ADDR_OFFSET0_LOCK_MASK) +/*! @} */ /*! @name ADDR_OFFSET1 - */ -#define BEE_ADDR_OFFSET1_ADDR_OFFSET0_MASK (0xFFFFU) -#define BEE_ADDR_OFFSET1_ADDR_OFFSET0_SHIFT (0U) -#define BEE_ADDR_OFFSET1_ADDR_OFFSET0(x) (((uint32_t)(((uint32_t)(x)) << BEE_ADDR_OFFSET1_ADDR_OFFSET0_SHIFT)) & BEE_ADDR_OFFSET1_ADDR_OFFSET0_MASK) -#define BEE_ADDR_OFFSET1_ADDR_OFFSET0_LOCK_MASK (0xFFFF0000U) -#define BEE_ADDR_OFFSET1_ADDR_OFFSET0_LOCK_SHIFT (16U) -#define BEE_ADDR_OFFSET1_ADDR_OFFSET0_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_ADDR_OFFSET1_ADDR_OFFSET0_LOCK_SHIFT)) & BEE_ADDR_OFFSET1_ADDR_OFFSET0_LOCK_MASK) +/*! @{ */ +#define BEE_ADDR_OFFSET1_ADDR_OFFSET1_MASK (0xFFFFU) +#define BEE_ADDR_OFFSET1_ADDR_OFFSET1_SHIFT (0U) +#define BEE_ADDR_OFFSET1_ADDR_OFFSET1(x) (((uint32_t)(((uint32_t)(x)) << BEE_ADDR_OFFSET1_ADDR_OFFSET1_SHIFT)) & BEE_ADDR_OFFSET1_ADDR_OFFSET1_MASK) +#define BEE_ADDR_OFFSET1_ADDR_OFFSET1_LOCK_MASK (0xFFFF0000U) +#define BEE_ADDR_OFFSET1_ADDR_OFFSET1_LOCK_SHIFT (16U) +#define BEE_ADDR_OFFSET1_ADDR_OFFSET1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_ADDR_OFFSET1_ADDR_OFFSET1_LOCK_SHIFT)) & BEE_ADDR_OFFSET1_ADDR_OFFSET1_LOCK_MASK) +/*! @} */ /*! @name AES_KEY0_W0 - */ +/*! @{ */ #define BEE_AES_KEY0_W0_KEY0_MASK (0xFFFFFFFFU) #define BEE_AES_KEY0_W0_KEY0_SHIFT (0U) #define BEE_AES_KEY0_W0_KEY0(x) (((uint32_t)(((uint32_t)(x)) << BEE_AES_KEY0_W0_KEY0_SHIFT)) & BEE_AES_KEY0_W0_KEY0_MASK) +/*! @} */ /*! @name AES_KEY0_W1 - */ +/*! @{ */ #define BEE_AES_KEY0_W1_KEY1_MASK (0xFFFFFFFFU) #define BEE_AES_KEY0_W1_KEY1_SHIFT (0U) #define BEE_AES_KEY0_W1_KEY1(x) (((uint32_t)(((uint32_t)(x)) << BEE_AES_KEY0_W1_KEY1_SHIFT)) & BEE_AES_KEY0_W1_KEY1_MASK) +/*! @} */ /*! @name AES_KEY0_W2 - */ +/*! @{ */ #define BEE_AES_KEY0_W2_KEY2_MASK (0xFFFFFFFFU) #define BEE_AES_KEY0_W2_KEY2_SHIFT (0U) #define BEE_AES_KEY0_W2_KEY2(x) (((uint32_t)(((uint32_t)(x)) << BEE_AES_KEY0_W2_KEY2_SHIFT)) & BEE_AES_KEY0_W2_KEY2_MASK) +/*! @} */ /*! @name AES_KEY0_W3 - */ +/*! @{ */ #define BEE_AES_KEY0_W3_KEY3_MASK (0xFFFFFFFFU) #define BEE_AES_KEY0_W3_KEY3_SHIFT (0U) #define BEE_AES_KEY0_W3_KEY3(x) (((uint32_t)(((uint32_t)(x)) << BEE_AES_KEY0_W3_KEY3_SHIFT)) & BEE_AES_KEY0_W3_KEY3_MASK) +/*! @} */ /*! @name STATUS - */ +/*! @{ */ #define BEE_STATUS_IRQ_VEC_MASK (0xFFU) #define BEE_STATUS_IRQ_VEC_SHIFT (0U) #define BEE_STATUS_IRQ_VEC(x) (((uint32_t)(((uint32_t)(x)) << BEE_STATUS_IRQ_VEC_SHIFT)) & BEE_STATUS_IRQ_VEC_MASK) #define BEE_STATUS_BEE_IDLE_MASK (0x100U) #define BEE_STATUS_BEE_IDLE_SHIFT (8U) #define BEE_STATUS_BEE_IDLE(x) (((uint32_t)(((uint32_t)(x)) << BEE_STATUS_BEE_IDLE_SHIFT)) & BEE_STATUS_BEE_IDLE_MASK) +/*! @} */ /*! @name CTR_NONCE0_W0 - */ +/*! @{ */ #define BEE_CTR_NONCE0_W0_NONCE00_MASK (0xFFFFFFFFU) #define BEE_CTR_NONCE0_W0_NONCE00_SHIFT (0U) #define BEE_CTR_NONCE0_W0_NONCE00(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE0_W0_NONCE00_SHIFT)) & BEE_CTR_NONCE0_W0_NONCE00_MASK) +/*! @} */ /*! @name CTR_NONCE0_W1 - */ +/*! @{ */ #define BEE_CTR_NONCE0_W1_NONCE01_MASK (0xFFFFFFFFU) #define BEE_CTR_NONCE0_W1_NONCE01_SHIFT (0U) #define BEE_CTR_NONCE0_W1_NONCE01(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE0_W1_NONCE01_SHIFT)) & BEE_CTR_NONCE0_W1_NONCE01_MASK) +/*! @} */ /*! @name CTR_NONCE0_W2 - */ +/*! @{ */ #define BEE_CTR_NONCE0_W2_NONCE02_MASK (0xFFFFFFFFU) #define BEE_CTR_NONCE0_W2_NONCE02_SHIFT (0U) #define BEE_CTR_NONCE0_W2_NONCE02(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE0_W2_NONCE02_SHIFT)) & BEE_CTR_NONCE0_W2_NONCE02_MASK) +/*! @} */ /*! @name CTR_NONCE0_W3 - */ +/*! @{ */ #define BEE_CTR_NONCE0_W3_NONCE03_MASK (0xFFFFFFFFU) #define BEE_CTR_NONCE0_W3_NONCE03_SHIFT (0U) #define BEE_CTR_NONCE0_W3_NONCE03(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE0_W3_NONCE03_SHIFT)) & BEE_CTR_NONCE0_W3_NONCE03_MASK) +/*! @} */ /*! @name CTR_NONCE1_W0 - */ +/*! @{ */ #define BEE_CTR_NONCE1_W0_NONCE10_MASK (0xFFFFFFFFU) #define BEE_CTR_NONCE1_W0_NONCE10_SHIFT (0U) #define BEE_CTR_NONCE1_W0_NONCE10(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE1_W0_NONCE10_SHIFT)) & BEE_CTR_NONCE1_W0_NONCE10_MASK) +/*! @} */ /*! @name CTR_NONCE1_W1 - */ +/*! @{ */ #define BEE_CTR_NONCE1_W1_NONCE11_MASK (0xFFFFFFFFU) #define BEE_CTR_NONCE1_W1_NONCE11_SHIFT (0U) #define BEE_CTR_NONCE1_W1_NONCE11(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE1_W1_NONCE11_SHIFT)) & BEE_CTR_NONCE1_W1_NONCE11_MASK) +/*! @} */ /*! @name CTR_NONCE1_W2 - */ +/*! @{ */ #define BEE_CTR_NONCE1_W2_NONCE12_MASK (0xFFFFFFFFU) #define BEE_CTR_NONCE1_W2_NONCE12_SHIFT (0U) #define BEE_CTR_NONCE1_W2_NONCE12(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE1_W2_NONCE12_SHIFT)) & BEE_CTR_NONCE1_W2_NONCE12_MASK) +/*! @} */ /*! @name CTR_NONCE1_W3 - */ +/*! @{ */ #define BEE_CTR_NONCE1_W3_NONCE13_MASK (0xFFFFFFFFU) #define BEE_CTR_NONCE1_W3_NONCE13_SHIFT (0U) #define BEE_CTR_NONCE1_W3_NONCE13(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE1_W3_NONCE13_SHIFT)) & BEE_CTR_NONCE1_W3_NONCE13_MASK) +/*! @} */ /*! @name REGION1_TOP - */ +/*! @{ */ #define BEE_REGION1_TOP_REGION1_TOP_MASK (0xFFFFFFFFU) #define BEE_REGION1_TOP_REGION1_TOP_SHIFT (0U) #define BEE_REGION1_TOP_REGION1_TOP(x) (((uint32_t)(((uint32_t)(x)) << BEE_REGION1_TOP_REGION1_TOP_SHIFT)) & BEE_REGION1_TOP_REGION1_TOP_MASK) +/*! @} */ /*! @name REGION1_BOT - */ +/*! @{ */ #define BEE_REGION1_BOT_REGION1_BOT_MASK (0xFFFFFFFFU) #define BEE_REGION1_BOT_REGION1_BOT_SHIFT (0U) #define BEE_REGION1_BOT_REGION1_BOT(x) (((uint32_t)(((uint32_t)(x)) << BEE_REGION1_BOT_REGION1_BOT_SHIFT)) & BEE_REGION1_BOT_REGION1_BOT_MASK) +/*! @} */ /*! @@ -2468,16 +3123,19 @@ typedef struct { __I uint32_t CRCR; /**< CRC Register, offset: 0x44 */ __IO uint32_t RXFGMASK; /**< Rx FIFO Global Mask Register, offset: 0x48 */ __I uint32_t RXFIR; /**< Rx FIFO Information Register, offset: 0x4C */ - uint8_t RESERVED_2[48]; + uint8_t RESERVED_2[8]; + __I uint32_t DBG1; /**< Debug 1 register, offset: 0x58 */ + __I uint32_t DBG2; /**< Debug 2 register, offset: 0x5C */ + uint8_t RESERVED_3[32]; struct { /* offset: 0x80, array step: 0x10 */ __IO uint32_t CS; /**< Message Buffer 0 CS Register..Message Buffer 63 CS Register, array offset: 0x80, array step: 0x10 */ __IO uint32_t ID; /**< Message Buffer 0 ID Register..Message Buffer 63 ID Register, array offset: 0x84, array step: 0x10 */ __IO uint32_t WORD0; /**< Message Buffer 0 WORD0 Register..Message Buffer 63 WORD0 Register, array offset: 0x88, array step: 0x10 */ __IO uint32_t WORD1; /**< Message Buffer 0 WORD1 Register..Message Buffer 63 WORD1 Register, array offset: 0x8C, array step: 0x10 */ } MB[64]; - uint8_t RESERVED_3[1024]; + uint8_t RESERVED_4[1024]; __IO uint32_t RXIMR[64]; /**< Rx Individual Mask Registers, array offset: 0x880, array step: 0x4 */ - uint8_t RESERVED_4[96]; + uint8_t RESERVED_5[96]; __IO uint32_t GFWR; /**< Glitch Filter Width Registers, offset: 0x9E0 */ } CAN_Type; @@ -2491,97 +3149,214 @@ typedef struct { */ /*! @name MCR - Module Configuration Register */ +/*! @{ */ #define CAN_MCR_MAXMB_MASK (0x7FU) #define CAN_MCR_MAXMB_SHIFT (0U) #define CAN_MCR_MAXMB(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_MAXMB_SHIFT)) & CAN_MCR_MAXMB_MASK) #define CAN_MCR_IDAM_MASK (0x300U) #define CAN_MCR_IDAM_SHIFT (8U) +/*! IDAM + * 0b00..Format A One full ID (standard or extended) per ID filter Table element. + * 0b01..Format B Two full standard IDs or two partial 14-bit extended IDs per ID filter Table element. + * 0b10..Format C Four partial 8-bit IDs (standard or extended) per ID filter Table element. + * 0b11..Format D All frames rejected. + */ #define CAN_MCR_IDAM(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_IDAM_SHIFT)) & CAN_MCR_IDAM_MASK) #define CAN_MCR_AEN_MASK (0x1000U) #define CAN_MCR_AEN_SHIFT (12U) +/*! AEN + * 0b1..Abort enabled + * 0b0..Abort disabled + */ #define CAN_MCR_AEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_AEN_SHIFT)) & CAN_MCR_AEN_MASK) #define CAN_MCR_LPRIOEN_MASK (0x2000U) #define CAN_MCR_LPRIOEN_SHIFT (13U) +/*! LPRIOEN + * 0b1..Local Priority enabled + * 0b0..Local Priority disabled + */ #define CAN_MCR_LPRIOEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_LPRIOEN_SHIFT)) & CAN_MCR_LPRIOEN_MASK) #define CAN_MCR_IRMQ_MASK (0x10000U) #define CAN_MCR_IRMQ_SHIFT (16U) +/*! IRMQ + * 0b1..Individual Rx masking and queue feature are enabled. + * 0b0..Individual Rx masking and queue feature are disabled.For backward compatibility, the reading of C/S word locks the MB even if it is EMPTY. + */ #define CAN_MCR_IRMQ(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_IRMQ_SHIFT)) & CAN_MCR_IRMQ_MASK) #define CAN_MCR_SRXDIS_MASK (0x20000U) #define CAN_MCR_SRXDIS_SHIFT (17U) +/*! SRXDIS + * 0b1..Self reception disabled + * 0b0..Self reception enabled + */ #define CAN_MCR_SRXDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SRXDIS_SHIFT)) & CAN_MCR_SRXDIS_MASK) #define CAN_MCR_WAKSRC_MASK (0x80000U) #define CAN_MCR_WAKSRC_SHIFT (19U) +/*! WAKSRC + * 0b1..FLEXCAN uses the filtered FLEXCAN_RX input to detect recessive to dominant edges on the CAN bus + * 0b0..FLEXCAN uses the unfiltered FLEXCAN_RX input to detect recessive to dominant edges on the CAN bus. + */ #define CAN_MCR_WAKSRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WAKSRC_SHIFT)) & CAN_MCR_WAKSRC_MASK) #define CAN_MCR_LPMACK_MASK (0x100000U) #define CAN_MCR_LPMACK_SHIFT (20U) +/*! LPMACK + * 0b1..FLEXCAN is either in Disable Mode, or Stop mode + * 0b0..FLEXCAN not in any of the low power modes + */ #define CAN_MCR_LPMACK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_LPMACK_SHIFT)) & CAN_MCR_LPMACK_MASK) #define CAN_MCR_WRNEN_MASK (0x200000U) #define CAN_MCR_WRNEN_SHIFT (21U) +/*! WRNEN + * 0b1..TWRN_INT and RWRN_INT bits are set when the respective error counter transition from <96 to >= 96. + * 0b0..TWRN_INT and RWRN_INT bits are zero, independent of the values in the error counters. + */ #define CAN_MCR_WRNEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WRNEN_SHIFT)) & CAN_MCR_WRNEN_MASK) #define CAN_MCR_SLFWAK_MASK (0x400000U) #define CAN_MCR_SLFWAK_SHIFT (22U) +/*! SLFWAK + * 0b1..FLEXCAN Self Wake Up feature is enabled + * 0b0..FLEXCAN Self Wake Up feature is disabled + */ #define CAN_MCR_SLFWAK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SLFWAK_SHIFT)) & CAN_MCR_SLFWAK_MASK) #define CAN_MCR_SUPV_MASK (0x800000U) #define CAN_MCR_SUPV_SHIFT (23U) +/*! SUPV + * 0b1..FlexCAN is in Supervisor Mode. Affected registers allow only Supervisor access. Unrestricted access behaves as though the access was done to an unimplemented register location + * 0b0..FlexCAN is in User Mode. Affected registers allow both Supervisor and Unrestricted accesses + */ #define CAN_MCR_SUPV(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SUPV_SHIFT)) & CAN_MCR_SUPV_MASK) #define CAN_MCR_FRZACK_MASK (0x1000000U) #define CAN_MCR_FRZACK_SHIFT (24U) +/*! FRZACK + * 0b1..FLEXCAN in Freeze Mode, prescaler stopped + * 0b0..FLEXCAN not in Freeze Mode, prescaler running + */ #define CAN_MCR_FRZACK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FRZACK_SHIFT)) & CAN_MCR_FRZACK_MASK) #define CAN_MCR_SOFTRST_MASK (0x2000000U) #define CAN_MCR_SOFTRST_SHIFT (25U) +/*! SOFTRST + * 0b1..Reset the registers + * 0b0..No reset request + */ #define CAN_MCR_SOFTRST(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SOFTRST_SHIFT)) & CAN_MCR_SOFTRST_MASK) #define CAN_MCR_WAKMSK_MASK (0x4000000U) #define CAN_MCR_WAKMSK_SHIFT (26U) +/*! WAKMSK + * 0b1..Wake Up Interrupt is enabled + * 0b0..Wake Up Interrupt is disabled + */ #define CAN_MCR_WAKMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WAKMSK_SHIFT)) & CAN_MCR_WAKMSK_MASK) #define CAN_MCR_NOTRDY_MASK (0x8000000U) #define CAN_MCR_NOTRDY_SHIFT (27U) +/*! NOTRDY + * 0b1..FLEXCAN module is either in Disable Mode, Stop Mode or Freeze Mode + * 0b0..FLEXCAN module is either in Normal Mode, Listen-Only Mode or Loop-Back Mode + */ #define CAN_MCR_NOTRDY(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_NOTRDY_SHIFT)) & CAN_MCR_NOTRDY_MASK) #define CAN_MCR_HALT_MASK (0x10000000U) #define CAN_MCR_HALT_SHIFT (28U) +/*! HALT + * 0b1..Enters Freeze Mode if the FRZ bit is asserted. + * 0b0..No Freeze Mode request. + */ #define CAN_MCR_HALT(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_HALT_SHIFT)) & CAN_MCR_HALT_MASK) #define CAN_MCR_RFEN_MASK (0x20000000U) #define CAN_MCR_RFEN_SHIFT (29U) +/*! RFEN + * 0b1..FIFO enabled + * 0b0..FIFO not enabled + */ #define CAN_MCR_RFEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_RFEN_SHIFT)) & CAN_MCR_RFEN_MASK) #define CAN_MCR_FRZ_MASK (0x40000000U) #define CAN_MCR_FRZ_SHIFT (30U) +/*! FRZ + * 0b1..Enabled to enter Freeze Mode + * 0b0..Not enabled to enter Freeze Mode + */ #define CAN_MCR_FRZ(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FRZ_SHIFT)) & CAN_MCR_FRZ_MASK) #define CAN_MCR_MDIS_MASK (0x80000000U) #define CAN_MCR_MDIS_SHIFT (31U) +/*! MDIS + * 0b1..Disable the FLEXCAN module + * 0b0..Enable the FLEXCAN module + */ #define CAN_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_MDIS_SHIFT)) & CAN_MCR_MDIS_MASK) +/*! @} */ /*! @name CTRL1 - Control 1 Register */ +/*! @{ */ #define CAN_CTRL1_PROPSEG_MASK (0x7U) #define CAN_CTRL1_PROPSEG_SHIFT (0U) #define CAN_CTRL1_PROPSEG(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PROPSEG_SHIFT)) & CAN_CTRL1_PROPSEG_MASK) #define CAN_CTRL1_LOM_MASK (0x8U) #define CAN_CTRL1_LOM_SHIFT (3U) +/*! LOM + * 0b1..FLEXCAN module operates in Listen Only Mode + * 0b0..Listen Only Mode is deactivated + */ #define CAN_CTRL1_LOM(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LOM_SHIFT)) & CAN_CTRL1_LOM_MASK) #define CAN_CTRL1_LBUF_MASK (0x10U) #define CAN_CTRL1_LBUF_SHIFT (4U) +/*! LBUF + * 0b1..Lowest number buffer is transmitted first + * 0b0..Buffer with highest priority is transmitted first + */ #define CAN_CTRL1_LBUF(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LBUF_SHIFT)) & CAN_CTRL1_LBUF_MASK) #define CAN_CTRL1_TSYN_MASK (0x20U) #define CAN_CTRL1_TSYN_SHIFT (5U) +/*! TSYN + * 0b1..Timer Sync feature enabled + * 0b0..Timer Sync feature disabled + */ #define CAN_CTRL1_TSYN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_TSYN_SHIFT)) & CAN_CTRL1_TSYN_MASK) #define CAN_CTRL1_BOFFREC_MASK (0x40U) #define CAN_CTRL1_BOFFREC_SHIFT (6U) +/*! BOFFREC + * 0b1..Automatic recovering from Bus Off state disabled + * 0b0..Automatic recovering from Bus Off state enabled, according to CAN Spec 2.0 part B + */ #define CAN_CTRL1_BOFFREC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_BOFFREC_SHIFT)) & CAN_CTRL1_BOFFREC_MASK) #define CAN_CTRL1_SMP_MASK (0x80U) #define CAN_CTRL1_SMP_SHIFT (7U) +/*! SMP + * 0b1..Three samples are used to determine the value of the received bit: the regular one (sample point) and 2 preceding samples, a majority rule is used + * 0b0..Just one sample is used to determine the bit value + */ #define CAN_CTRL1_SMP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_SMP_SHIFT)) & CAN_CTRL1_SMP_MASK) #define CAN_CTRL1_RWRNMSK_MASK (0x400U) #define CAN_CTRL1_RWRNMSK_SHIFT (10U) +/*! RWRNMSK + * 0b1..Rx Warning Interrupt enabled + * 0b0..Rx Warning Interrupt disabled + */ #define CAN_CTRL1_RWRNMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_RWRNMSK_SHIFT)) & CAN_CTRL1_RWRNMSK_MASK) #define CAN_CTRL1_TWRNMSK_MASK (0x800U) #define CAN_CTRL1_TWRNMSK_SHIFT (11U) +/*! TWRNMSK + * 0b1..Tx Warning Interrupt enabled + * 0b0..Tx Warning Interrupt disabled + */ #define CAN_CTRL1_TWRNMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_TWRNMSK_SHIFT)) & CAN_CTRL1_TWRNMSK_MASK) #define CAN_CTRL1_LPB_MASK (0x1000U) #define CAN_CTRL1_LPB_SHIFT (12U) +/*! LPB + * 0b1..Loop Back enabled + * 0b0..Loop Back disabled + */ #define CAN_CTRL1_LPB(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LPB_SHIFT)) & CAN_CTRL1_LPB_MASK) #define CAN_CTRL1_ERRMSK_MASK (0x4000U) #define CAN_CTRL1_ERRMSK_SHIFT (14U) +/*! ERRMSK + * 0b1..Error interrupt enabled + * 0b0..Error interrupt disabled + */ #define CAN_CTRL1_ERRMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_ERRMSK_SHIFT)) & CAN_CTRL1_ERRMSK_MASK) #define CAN_CTRL1_BOFFMSK_MASK (0x8000U) #define CAN_CTRL1_BOFFMSK_SHIFT (15U) +/*! BOFFMSK + * 0b1..Bus Off interrupt enabled + * 0b0..Bus Off interrupt disabled + */ #define CAN_CTRL1_BOFFMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_BOFFMSK_SHIFT)) & CAN_CTRL1_BOFFMSK_MASK) #define CAN_CTRL1_PSEG2_MASK (0x70000U) #define CAN_CTRL1_PSEG2_SHIFT (16U) @@ -2595,132 +3370,283 @@ typedef struct { #define CAN_CTRL1_PRESDIV_MASK (0xFF000000U) #define CAN_CTRL1_PRESDIV_SHIFT (24U) #define CAN_CTRL1_PRESDIV(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PRESDIV_SHIFT)) & CAN_CTRL1_PRESDIV_MASK) +/*! @} */ /*! @name TIMER - Free Running Timer Register */ +/*! @{ */ #define CAN_TIMER_TIMER_MASK (0xFFFFU) #define CAN_TIMER_TIMER_SHIFT (0U) #define CAN_TIMER_TIMER(x) (((uint32_t)(((uint32_t)(x)) << CAN_TIMER_TIMER_SHIFT)) & CAN_TIMER_TIMER_MASK) +/*! @} */ /*! @name RXMGMASK - Rx Mailboxes Global Mask Register */ +/*! @{ */ #define CAN_RXMGMASK_MG_MASK (0xFFFFFFFFU) #define CAN_RXMGMASK_MG_SHIFT (0U) +/*! MG + * 0b00000000000000000000000000000001..The corresponding bit in the filter is checked against the one received + * 0b00000000000000000000000000000000..the corresponding bit in the filter is "don't care" + */ #define CAN_RXMGMASK_MG(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXMGMASK_MG_SHIFT)) & CAN_RXMGMASK_MG_MASK) +/*! @} */ /*! @name RX14MASK - Rx Buffer 14 Mask Register */ +/*! @{ */ #define CAN_RX14MASK_RX14M_MASK (0xFFFFFFFFU) #define CAN_RX14MASK_RX14M_SHIFT (0U) +/*! RX14M + * 0b00000000000000000000000000000001..The corresponding bit in the filter is checked + * 0b00000000000000000000000000000000..the corresponding bit in the filter is "don't care" + */ #define CAN_RX14MASK_RX14M(x) (((uint32_t)(((uint32_t)(x)) << CAN_RX14MASK_RX14M_SHIFT)) & CAN_RX14MASK_RX14M_MASK) +/*! @} */ /*! @name RX15MASK - Rx Buffer 15 Mask Register */ +/*! @{ */ #define CAN_RX15MASK_RX15M_MASK (0xFFFFFFFFU) #define CAN_RX15MASK_RX15M_SHIFT (0U) +/*! RX15M + * 0b00000000000000000000000000000001..The corresponding bit in the filter is checked + * 0b00000000000000000000000000000000..the corresponding bit in the filter is "don't care" + */ #define CAN_RX15MASK_RX15M(x) (((uint32_t)(((uint32_t)(x)) << CAN_RX15MASK_RX15M_SHIFT)) & CAN_RX15MASK_RX15M_MASK) +/*! @} */ /*! @name ECR - Error Counter Register */ +/*! @{ */ #define CAN_ECR_TX_ERR_COUNTER_MASK (0xFFU) #define CAN_ECR_TX_ERR_COUNTER_SHIFT (0U) #define CAN_ECR_TX_ERR_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_TX_ERR_COUNTER_SHIFT)) & CAN_ECR_TX_ERR_COUNTER_MASK) #define CAN_ECR_RX_ERR_COUNTER_MASK (0xFF00U) #define CAN_ECR_RX_ERR_COUNTER_SHIFT (8U) #define CAN_ECR_RX_ERR_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_RX_ERR_COUNTER_SHIFT)) & CAN_ECR_RX_ERR_COUNTER_MASK) +/*! @} */ /*! @name ESR1 - Error and Status 1 Register */ +/*! @{ */ #define CAN_ESR1_WAKINT_MASK (0x1U) #define CAN_ESR1_WAKINT_SHIFT (0U) +/*! WAKINT + * 0b1..Indicates a recessive to dominant transition received on the CAN bus when the FLEXCAN module is in Stop Mode + * 0b0..No such occurrence + */ #define CAN_ESR1_WAKINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_WAKINT_SHIFT)) & CAN_ESR1_WAKINT_MASK) #define CAN_ESR1_ERRINT_MASK (0x2U) #define CAN_ESR1_ERRINT_SHIFT (1U) +/*! ERRINT + * 0b1..Indicates setting of any Error Bit in the Error and Status Register + * 0b0..No such occurrence + */ #define CAN_ESR1_ERRINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ERRINT_SHIFT)) & CAN_ESR1_ERRINT_MASK) #define CAN_ESR1_BOFFINT_MASK (0x4U) #define CAN_ESR1_BOFFINT_SHIFT (2U) +/*! BOFFINT + * 0b1..FLEXCAN module entered 'Bus Off' state + * 0b0..No such occurrence + */ #define CAN_ESR1_BOFFINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BOFFINT_SHIFT)) & CAN_ESR1_BOFFINT_MASK) #define CAN_ESR1_RX_MASK (0x8U) #define CAN_ESR1_RX_SHIFT (3U) +/*! RX + * 0b1..FLEXCAN is transmitting a message + * 0b0..FLEXCAN is receiving a message + */ #define CAN_ESR1_RX(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RX_SHIFT)) & CAN_ESR1_RX_MASK) #define CAN_ESR1_FLTCONF_MASK (0x30U) #define CAN_ESR1_FLTCONF_SHIFT (4U) +/*! FLTCONF + * 0b00..Error Active + * 0b01..Error Passive + * 0b1x..Bus off + */ #define CAN_ESR1_FLTCONF(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FLTCONF_SHIFT)) & CAN_ESR1_FLTCONF_MASK) #define CAN_ESR1_TX_MASK (0x40U) #define CAN_ESR1_TX_SHIFT (6U) +/*! TX + * 0b1..FLEXCAN is transmitting a message + * 0b0..FLEXCAN is receiving a message + */ #define CAN_ESR1_TX(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TX_SHIFT)) & CAN_ESR1_TX_MASK) #define CAN_ESR1_IDLE_MASK (0x80U) #define CAN_ESR1_IDLE_SHIFT (7U) +/*! IDLE + * 0b1..CAN bus is now IDLE + * 0b0..No such occurrence + */ #define CAN_ESR1_IDLE(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_IDLE_SHIFT)) & CAN_ESR1_IDLE_MASK) #define CAN_ESR1_RXWRN_MASK (0x100U) #define CAN_ESR1_RXWRN_SHIFT (8U) +/*! RXWRN + * 0b1..Rx_Err_Counter >= 96 + * 0b0..No such occurrence + */ #define CAN_ESR1_RXWRN(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RXWRN_SHIFT)) & CAN_ESR1_RXWRN_MASK) #define CAN_ESR1_TXWRN_MASK (0x200U) #define CAN_ESR1_TXWRN_SHIFT (9U) +/*! TXWRN + * 0b1..TX_Err_Counter >= 96 + * 0b0..No such occurrence + */ #define CAN_ESR1_TXWRN(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TXWRN_SHIFT)) & CAN_ESR1_TXWRN_MASK) #define CAN_ESR1_STFERR_MASK (0x400U) #define CAN_ESR1_STFERR_SHIFT (10U) +/*! STFERR + * 0b1..A Stuffing Error occurred since last read of this register. + * 0b0..No such occurrence. + */ #define CAN_ESR1_STFERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_STFERR_SHIFT)) & CAN_ESR1_STFERR_MASK) #define CAN_ESR1_FRMERR_MASK (0x800U) #define CAN_ESR1_FRMERR_SHIFT (11U) +/*! FRMERR + * 0b1..A Form Error occurred since last read of this register + * 0b0..No such occurrence + */ #define CAN_ESR1_FRMERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FRMERR_SHIFT)) & CAN_ESR1_FRMERR_MASK) #define CAN_ESR1_CRCERR_MASK (0x1000U) #define CAN_ESR1_CRCERR_SHIFT (12U) +/*! CRCERR + * 0b1..A CRC error occurred since last read of this register. + * 0b0..No such occurrence + */ #define CAN_ESR1_CRCERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_CRCERR_SHIFT)) & CAN_ESR1_CRCERR_MASK) #define CAN_ESR1_ACKERR_MASK (0x2000U) #define CAN_ESR1_ACKERR_SHIFT (13U) +/*! ACKERR + * 0b1..An ACK error occurred since last read of this register + * 0b0..No such occurrence + */ #define CAN_ESR1_ACKERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ACKERR_SHIFT)) & CAN_ESR1_ACKERR_MASK) #define CAN_ESR1_BIT0ERR_MASK (0x4000U) #define CAN_ESR1_BIT0ERR_SHIFT (14U) +/*! BIT0ERR + * 0b1..At least one bit sent as dominant is received as recessive + * 0b0..No such occurrence + */ #define CAN_ESR1_BIT0ERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT0ERR_SHIFT)) & CAN_ESR1_BIT0ERR_MASK) #define CAN_ESR1_BIT1ERR_MASK (0x8000U) #define CAN_ESR1_BIT1ERR_SHIFT (15U) +/*! BIT1ERR + * 0b1..At least one bit sent as recessive is received as dominant + * 0b0..No such occurrence + */ #define CAN_ESR1_BIT1ERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT1ERR_SHIFT)) & CAN_ESR1_BIT1ERR_MASK) #define CAN_ESR1_RWRNINT_MASK (0x10000U) #define CAN_ESR1_RWRNINT_SHIFT (16U) +/*! RWRNINT + * 0b1..The Rx error counter transition from < 96 to >= 96 + * 0b0..No such occurrence + */ #define CAN_ESR1_RWRNINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RWRNINT_SHIFT)) & CAN_ESR1_RWRNINT_MASK) #define CAN_ESR1_TWRNINT_MASK (0x20000U) #define CAN_ESR1_TWRNINT_SHIFT (17U) +/*! TWRNINT + * 0b1..The Tx error counter transition from < 96 to >= 96 + * 0b0..No such occurrence + */ #define CAN_ESR1_TWRNINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TWRNINT_SHIFT)) & CAN_ESR1_TWRNINT_MASK) #define CAN_ESR1_SYNCH_MASK (0x40000U) #define CAN_ESR1_SYNCH_SHIFT (18U) +/*! SYNCH + * 0b1..FlexCAN is synchronized to the CAN bus + * 0b0..FlexCAN is not synchronized to the CAN bus + */ #define CAN_ESR1_SYNCH(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_SYNCH_SHIFT)) & CAN_ESR1_SYNCH_MASK) +/*! @} */ /*! @name IMASK2 - Interrupt Masks 2 Register */ +/*! @{ */ #define CAN_IMASK2_BUFHM_MASK (0xFFFFFFFFU) #define CAN_IMASK2_BUFHM_SHIFT (0U) +/*! BUFHM + * 0b00000000000000000000000000000001..The corresponding buffer Interrupt is enabled + * 0b00000000000000000000000000000000..The corresponding buffer Interrupt is disabled + */ #define CAN_IMASK2_BUFHM(x) (((uint32_t)(((uint32_t)(x)) << CAN_IMASK2_BUFHM_SHIFT)) & CAN_IMASK2_BUFHM_MASK) +/*! @} */ /*! @name IMASK1 - Interrupt Masks 1 Register */ +/*! @{ */ #define CAN_IMASK1_BUFLM_MASK (0xFFFFFFFFU) #define CAN_IMASK1_BUFLM_SHIFT (0U) +/*! BUFLM + * 0b00000000000000000000000000000001..The corresponding buffer Interrupt is enabled + * 0b00000000000000000000000000000000..The corresponding buffer Interrupt is disabled + */ #define CAN_IMASK1_BUFLM(x) (((uint32_t)(((uint32_t)(x)) << CAN_IMASK1_BUFLM_SHIFT)) & CAN_IMASK1_BUFLM_MASK) +/*! @} */ /*! @name IFLAG2 - Interrupt Flags 2 Register */ +/*! @{ */ #define CAN_IFLAG2_BUFHI_MASK (0xFFFFFFFFU) #define CAN_IFLAG2_BUFHI_SHIFT (0U) +/*! BUFHI + * 0b00000000000000000000000000000001..The corresponding buffer has successfully completed transmission or reception + * 0b00000000000000000000000000000000..No such occurrence + */ #define CAN_IFLAG2_BUFHI(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG2_BUFHI_SHIFT)) & CAN_IFLAG2_BUFHI_MASK) +/*! @} */ /*! @name IFLAG1 - Interrupt Flags 1 Register */ +/*! @{ */ #define CAN_IFLAG1_BUF4TO0I_MASK (0x1FU) #define CAN_IFLAG1_BUF4TO0I_SHIFT (0U) +/*! BUF4TO0I + * 0b00001..Corresponding MB completed transmission/reception + * 0b00000..No such occurrence + */ #define CAN_IFLAG1_BUF4TO0I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF4TO0I_SHIFT)) & CAN_IFLAG1_BUF4TO0I_MASK) #define CAN_IFLAG1_BUF5I_MASK (0x20U) #define CAN_IFLAG1_BUF5I_SHIFT (5U) +/*! BUF5I + * 0b1..MB5 completed transmission/reception or frames available in the FIFO + * 0b0..No such occurrence + */ #define CAN_IFLAG1_BUF5I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF5I_SHIFT)) & CAN_IFLAG1_BUF5I_MASK) #define CAN_IFLAG1_BUF6I_MASK (0x40U) #define CAN_IFLAG1_BUF6I_SHIFT (6U) +/*! BUF6I + * 0b1..MB6 completed transmission/reception or FIFO almost full + * 0b0..No such occurrence + */ #define CAN_IFLAG1_BUF6I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF6I_SHIFT)) & CAN_IFLAG1_BUF6I_MASK) #define CAN_IFLAG1_BUF7I_MASK (0x80U) #define CAN_IFLAG1_BUF7I_SHIFT (7U) +/*! BUF7I + * 0b1..MB7 completed transmission/reception or FIFO overflow + * 0b0..No such occurrence + */ #define CAN_IFLAG1_BUF7I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF7I_SHIFT)) & CAN_IFLAG1_BUF7I_MASK) #define CAN_IFLAG1_BUF31TO8I_MASK (0xFFFFFF00U) #define CAN_IFLAG1_BUF31TO8I_SHIFT (8U) +/*! BUF31TO8I + * 0b000000000000000000000001..The corresponding MB has successfully completed transmission or reception + * 0b000000000000000000000000..No such occurrence + */ #define CAN_IFLAG1_BUF31TO8I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF31TO8I_SHIFT)) & CAN_IFLAG1_BUF31TO8I_MASK) +/*! @} */ /*! @name CTRL2 - Control 2 Register */ +/*! @{ */ #define CAN_CTRL2_EACEN_MASK (0x10000U) #define CAN_CTRL2_EACEN_SHIFT (16U) +/*! EACEN + * 0b1..Enables the comparison of both Rx Mailbox filter's IDE and RTR bit with their corresponding bits within the incoming frame. Mask bits do apply. + * 0b0..Rx Mailbox filter's IDE bit is always compared and RTR is never compared despite mask bits. + */ #define CAN_CTRL2_EACEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_EACEN_SHIFT)) & CAN_CTRL2_EACEN_MASK) #define CAN_CTRL2_RRS_MASK (0x20000U) #define CAN_CTRL2_RRS_SHIFT (17U) +/*! RRS + * 0b1..Remote Request Frame is stored + * 0b0..Remote Response Frame is generated + */ #define CAN_CTRL2_RRS(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_RRS_SHIFT)) & CAN_CTRL2_RRS_MASK) #define CAN_CTRL2_MRP_MASK (0x40000U) #define CAN_CTRL2_MRP_SHIFT (18U) +/*! MRP + * 0b1..Matching starts from Mailboxes and continues on Rx FIFO + * 0b0..Matching starts from Rx FIFO and continues on Mailboxes + */ #define CAN_CTRL2_MRP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_MRP_SHIFT)) & CAN_CTRL2_MRP_MASK) #define CAN_CTRL2_TASD_MASK (0xF80000U) #define CAN_CTRL2_TASD_SHIFT (19U) @@ -2730,38 +3656,98 @@ typedef struct { #define CAN_CTRL2_RFFN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_RFFN_SHIFT)) & CAN_CTRL2_RFFN_MASK) #define CAN_CTRL2_WRMFRZ_MASK (0x10000000U) #define CAN_CTRL2_WRMFRZ_SHIFT (28U) +/*! WRMFRZ + * 0b1..Enable unrestricted write access to FlexCAN memory + * 0b0..Keep the write access restricted in some regions of FlexCAN memory + */ #define CAN_CTRL2_WRMFRZ(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_WRMFRZ_SHIFT)) & CAN_CTRL2_WRMFRZ_MASK) +/*! @} */ /*! @name ESR2 - Error and Status 2 Register */ +/*! @{ */ #define CAN_ESR2_IMB_MASK (0x2000U) #define CAN_ESR2_IMB_SHIFT (13U) +/*! IMB + * 0b1..If ESR2[VPS] is asserted, there is at least one inactive Mailbox. LPTM content is the number of the first one. + * 0b0..If ESR2[VPS] is asserted, the ESR2[LPTM] is not an inactive Mailbox. + */ #define CAN_ESR2_IMB(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_IMB_SHIFT)) & CAN_ESR2_IMB_MASK) #define CAN_ESR2_VPS_MASK (0x4000U) #define CAN_ESR2_VPS_SHIFT (14U) +/*! VPS + * 0b1..Contents of IMB and LPTM are valid + * 0b0..Contents of IMB and LPTM are invalid + */ #define CAN_ESR2_VPS(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_VPS_SHIFT)) & CAN_ESR2_VPS_MASK) #define CAN_ESR2_LPTM_MASK (0x7F0000U) #define CAN_ESR2_LPTM_SHIFT (16U) #define CAN_ESR2_LPTM(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_LPTM_SHIFT)) & CAN_ESR2_LPTM_MASK) +/*! @} */ /*! @name CRCR - CRC Register */ +/*! @{ */ #define CAN_CRCR_TXCRC_MASK (0x7FFFU) #define CAN_CRCR_TXCRC_SHIFT (0U) #define CAN_CRCR_TXCRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CRCR_TXCRC_SHIFT)) & CAN_CRCR_TXCRC_MASK) #define CAN_CRCR_MBCRC_MASK (0x7F0000U) #define CAN_CRCR_MBCRC_SHIFT (16U) #define CAN_CRCR_MBCRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CRCR_MBCRC_SHIFT)) & CAN_CRCR_MBCRC_MASK) +/*! @} */ /*! @name RXFGMASK - Rx FIFO Global Mask Register */ +/*! @{ */ #define CAN_RXFGMASK_FGM_MASK (0xFFFFFFFFU) #define CAN_RXFGMASK_FGM_SHIFT (0U) +/*! FGM + * 0b00000000000000000000000000000001..The corresponding bit in the filter is checked + * 0b00000000000000000000000000000000..The corresponding bit in the filter is "don't care" + */ #define CAN_RXFGMASK_FGM(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXFGMASK_FGM_SHIFT)) & CAN_RXFGMASK_FGM_MASK) +/*! @} */ /*! @name RXFIR - Rx FIFO Information Register */ +/*! @{ */ #define CAN_RXFIR_IDHIT_MASK (0x1FFU) #define CAN_RXFIR_IDHIT_SHIFT (0U) #define CAN_RXFIR_IDHIT(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXFIR_IDHIT_SHIFT)) & CAN_RXFIR_IDHIT_MASK) +/*! @} */ + +/*! @name DBG1 - Debug 1 register */ +/*! @{ */ +#define CAN_DBG1_CFSM_MASK (0x3FU) +#define CAN_DBG1_CFSM_SHIFT (0U) +#define CAN_DBG1_CFSM(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBG1_CFSM_SHIFT)) & CAN_DBG1_CFSM_MASK) +#define CAN_DBG1_CBN_MASK (0x1F000000U) +#define CAN_DBG1_CBN_SHIFT (24U) +#define CAN_DBG1_CBN(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBG1_CBN_SHIFT)) & CAN_DBG1_CBN_MASK) +/*! @} */ + +/*! @name DBG2 - Debug 2 register */ +/*! @{ */ +#define CAN_DBG2_RMP_MASK (0x7FU) +#define CAN_DBG2_RMP_SHIFT (0U) +#define CAN_DBG2_RMP(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBG2_RMP_SHIFT)) & CAN_DBG2_RMP_MASK) +#define CAN_DBG2_MPP_MASK (0x80U) +#define CAN_DBG2_MPP_SHIFT (7U) +/*! MPP - Matching Process in Progress + * 0b0..No matching process ongoing. + * 0b1..Matching process is in progress. + */ +#define CAN_DBG2_MPP(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBG2_MPP_SHIFT)) & CAN_DBG2_MPP_MASK) +#define CAN_DBG2_TAP_MASK (0x7F00U) +#define CAN_DBG2_TAP_SHIFT (8U) +#define CAN_DBG2_TAP(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBG2_TAP_SHIFT)) & CAN_DBG2_TAP_MASK) +#define CAN_DBG2_APP_MASK (0x8000U) +#define CAN_DBG2_APP_SHIFT (15U) +/*! APP - Arbitration Process in Progress + * 0b0..No matching process ongoing. + * 0b1..Matching process is in progress. + */ +#define CAN_DBG2_APP(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBG2_APP_SHIFT)) & CAN_DBG2_APP_MASK) +/*! @} */ /*! @name CS - Message Buffer 0 CS Register..Message Buffer 63 CS Register */ +/*! @{ */ #define CAN_CS_TIME_STAMP_MASK (0xFFFFU) #define CAN_CS_TIME_STAMP_SHIFT (0U) #define CAN_CS_TIME_STAMP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_TIME_STAMP_SHIFT)) & CAN_CS_TIME_STAMP_MASK) @@ -2780,11 +3766,13 @@ typedef struct { #define CAN_CS_CODE_MASK (0xF000000U) #define CAN_CS_CODE_SHIFT (24U) #define CAN_CS_CODE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_CODE_SHIFT)) & CAN_CS_CODE_MASK) +/*! @} */ /* The count of CAN_CS */ #define CAN_CS_COUNT (64U) /*! @name ID - Message Buffer 0 ID Register..Message Buffer 63 ID Register */ +/*! @{ */ #define CAN_ID_EXT_MASK (0x3FFFFU) #define CAN_ID_EXT_SHIFT (0U) #define CAN_ID_EXT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_EXT_SHIFT)) & CAN_ID_EXT_MASK) @@ -2794,11 +3782,13 @@ typedef struct { #define CAN_ID_PRIO_MASK (0xE0000000U) #define CAN_ID_PRIO_SHIFT (29U) #define CAN_ID_PRIO(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_PRIO_SHIFT)) & CAN_ID_PRIO_MASK) +/*! @} */ /* The count of CAN_ID */ #define CAN_ID_COUNT (64U) /*! @name WORD0 - Message Buffer 0 WORD0 Register..Message Buffer 63 WORD0 Register */ +/*! @{ */ #define CAN_WORD0_DATA_BYTE_3_MASK (0xFFU) #define CAN_WORD0_DATA_BYTE_3_SHIFT (0U) #define CAN_WORD0_DATA_BYTE_3(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_3_SHIFT)) & CAN_WORD0_DATA_BYTE_3_MASK) @@ -2811,11 +3801,13 @@ typedef struct { #define CAN_WORD0_DATA_BYTE_0_MASK (0xFF000000U) #define CAN_WORD0_DATA_BYTE_0_SHIFT (24U) #define CAN_WORD0_DATA_BYTE_0(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_0_SHIFT)) & CAN_WORD0_DATA_BYTE_0_MASK) +/*! @} */ /* The count of CAN_WORD0 */ #define CAN_WORD0_COUNT (64U) /*! @name WORD1 - Message Buffer 0 WORD1 Register..Message Buffer 63 WORD1 Register */ +/*! @{ */ #define CAN_WORD1_DATA_BYTE_7_MASK (0xFFU) #define CAN_WORD1_DATA_BYTE_7_SHIFT (0U) #define CAN_WORD1_DATA_BYTE_7(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_7_SHIFT)) & CAN_WORD1_DATA_BYTE_7_MASK) @@ -2828,22 +3820,31 @@ typedef struct { #define CAN_WORD1_DATA_BYTE_4_MASK (0xFF000000U) #define CAN_WORD1_DATA_BYTE_4_SHIFT (24U) #define CAN_WORD1_DATA_BYTE_4(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_4_SHIFT)) & CAN_WORD1_DATA_BYTE_4_MASK) +/*! @} */ /* The count of CAN_WORD1 */ #define CAN_WORD1_COUNT (64U) /*! @name RXIMR - Rx Individual Mask Registers */ +/*! @{ */ #define CAN_RXIMR_MI_MASK (0xFFFFFFFFU) #define CAN_RXIMR_MI_SHIFT (0U) +/*! MI + * 0b00000000000000000000000000000001..The corresponding bit in the filter is checked + * 0b00000000000000000000000000000000..the corresponding bit in the filter is "don't care" + */ #define CAN_RXIMR_MI(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXIMR_MI_SHIFT)) & CAN_RXIMR_MI_MASK) +/*! @} */ /* The count of CAN_RXIMR */ #define CAN_RXIMR_COUNT (64U) /*! @name GFWR - Glitch Filter Width Registers */ +/*! @{ */ #define CAN_GFWR_GFWR_MASK (0xFFU) #define CAN_GFWR_GFWR_SHIFT (0U) #define CAN_GFWR_GFWR(x) (((uint32_t)(((uint32_t)(x)) << CAN_GFWR_GFWR_SHIFT)) & CAN_GFWR_GFWR_MASK) +/*! @} */ /*! @@ -2941,251 +3942,709 @@ typedef struct { */ /*! @name CCR - CCM Control Register */ +/*! @{ */ #define CCM_CCR_OSCNT_MASK (0xFFU) #define CCM_CCR_OSCNT_SHIFT (0U) +/*! OSCNT + * 0b00000000..count 1 ckil + * 0b11111111..count 256 ckil's + */ #define CCM_CCR_OSCNT(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCR_OSCNT_SHIFT)) & CCM_CCR_OSCNT_MASK) #define CCM_CCR_COSC_EN_MASK (0x1000U) #define CCM_CCR_COSC_EN_SHIFT (12U) +/*! COSC_EN + * 0b0..disable on chip oscillator + * 0b1..enable on chip oscillator + */ #define CCM_CCR_COSC_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCR_COSC_EN_SHIFT)) & CCM_CCR_COSC_EN_MASK) #define CCM_CCR_REG_BYPASS_COUNT_MASK (0x7E00000U) #define CCM_CCR_REG_BYPASS_COUNT_SHIFT (21U) +/*! REG_BYPASS_COUNT + * 0b000000..no delay + * 0b000001..1 CKIL clock period delay + * 0b111111..63 CKIL clock periods delay + */ #define CCM_CCR_REG_BYPASS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCR_REG_BYPASS_COUNT_SHIFT)) & CCM_CCR_REG_BYPASS_COUNT_MASK) #define CCM_CCR_RBC_EN_MASK (0x8000000U) #define CCM_CCR_RBC_EN_SHIFT (27U) +/*! RBC_EN + * 0b1..REG_BYPASS_COUNTER enabled. + * 0b0..REG_BYPASS_COUNTER disabled + */ #define CCM_CCR_RBC_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCR_RBC_EN_SHIFT)) & CCM_CCR_RBC_EN_MASK) +/*! @} */ /*! @name CSR - CCM Status Register */ +/*! @{ */ #define CCM_CSR_REF_EN_B_MASK (0x1U) #define CCM_CSR_REF_EN_B_SHIFT (0U) +/*! REF_EN_B + * 0b0..value of CCM_REF_EN_B is '0' + * 0b1..value of CCM_REF_EN_B is '1' + */ #define CCM_CSR_REF_EN_B(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSR_REF_EN_B_SHIFT)) & CCM_CSR_REF_EN_B_MASK) #define CCM_CSR_CAMP2_READY_MASK (0x8U) #define CCM_CSR_CAMP2_READY_SHIFT (3U) +/*! CAMP2_READY + * 0b0..CAMP2 is not ready. + * 0b1..CAMP2 is ready. + */ #define CCM_CSR_CAMP2_READY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSR_CAMP2_READY_SHIFT)) & CCM_CSR_CAMP2_READY_MASK) #define CCM_CSR_COSC_READY_MASK (0x20U) #define CCM_CSR_COSC_READY_SHIFT (5U) +/*! COSC_READY + * 0b0..on board oscillator is not ready. + * 0b1..on board oscillator is ready. + */ #define CCM_CSR_COSC_READY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSR_COSC_READY_SHIFT)) & CCM_CSR_COSC_READY_MASK) +/*! @} */ /*! @name CCSR - CCM Clock Switcher Register */ +/*! @{ */ #define CCM_CCSR_PLL3_SW_CLK_SEL_MASK (0x1U) #define CCM_CCSR_PLL3_SW_CLK_SEL_SHIFT (0U) +/*! PLL3_SW_CLK_SEL + * 0b0..pll3_main_clk + * 0b1..pll3 bypass clock + */ #define CCM_CCSR_PLL3_SW_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCSR_PLL3_SW_CLK_SEL_SHIFT)) & CCM_CCSR_PLL3_SW_CLK_SEL_MASK) +/*! @} */ /*! @name CACRR - CCM Arm Clock Root Register */ +/*! @{ */ #define CCM_CACRR_ARM_PODF_MASK (0x7U) #define CCM_CACRR_ARM_PODF_SHIFT (0U) +/*! ARM_PODF + * 0b000..divide by 1 + * 0b001..divide by 2 + * 0b010..divide by 3 + * 0b011..divide by 4 + * 0b100..divide by 5 + * 0b101..divide by 6 + * 0b110..divide by 7 + * 0b111..divide by 8 + */ #define CCM_CACRR_ARM_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CACRR_ARM_PODF_SHIFT)) & CCM_CACRR_ARM_PODF_MASK) +/*! @} */ /*! @name CBCDR - CCM Bus Clock Divider Register */ +/*! @{ */ #define CCM_CBCDR_SEMC_CLK_SEL_MASK (0x40U) #define CCM_CBCDR_SEMC_CLK_SEL_SHIFT (6U) +/*! SEMC_CLK_SEL + * 0b0..Periph_clk output will be used as SEMC clock root + * 0b1..SEMC alternative clock will be used as SEMC clock root + */ #define CCM_CBCDR_SEMC_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_SEMC_CLK_SEL_SHIFT)) & CCM_CBCDR_SEMC_CLK_SEL_MASK) #define CCM_CBCDR_SEMC_ALT_CLK_SEL_MASK (0x80U) #define CCM_CBCDR_SEMC_ALT_CLK_SEL_SHIFT (7U) +/*! SEMC_ALT_CLK_SEL + * 0b0..PLL2 PFD2 will be selected as alternative clock for SEMC root clock + * 0b1..PLL3 PFD1 will be selected as alternative clock for SEMC root clock + */ #define CCM_CBCDR_SEMC_ALT_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_SEMC_ALT_CLK_SEL_SHIFT)) & CCM_CBCDR_SEMC_ALT_CLK_SEL_MASK) #define CCM_CBCDR_IPG_PODF_MASK (0x300U) #define CCM_CBCDR_IPG_PODF_SHIFT (8U) +/*! IPG_PODF + * 0b00..divide by 1 + * 0b01..divide by 2 + * 0b10..divide by 3 + * 0b11..divide by 4 + */ #define CCM_CBCDR_IPG_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_IPG_PODF_SHIFT)) & CCM_CBCDR_IPG_PODF_MASK) #define CCM_CBCDR_AHB_PODF_MASK (0x1C00U) #define CCM_CBCDR_AHB_PODF_SHIFT (10U) +/*! AHB_PODF + * 0b000..divide by 1 + * 0b001..divide by 2 + * 0b010..divide by 3 + * 0b011..divide by 4 + * 0b100..divide by 5 + * 0b101..divide by 6 + * 0b110..divide by 7 + * 0b111..divide by 8 + */ #define CCM_CBCDR_AHB_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_AHB_PODF_SHIFT)) & CCM_CBCDR_AHB_PODF_MASK) #define CCM_CBCDR_SEMC_PODF_MASK (0x70000U) #define CCM_CBCDR_SEMC_PODF_SHIFT (16U) +/*! SEMC_PODF + * 0b000..divide by 1 + * 0b001..divide by 2 + * 0b010..divide by 3 + * 0b011..divide by 4 + * 0b100..divide by 5 + * 0b101..divide by 6 + * 0b110..divide by 7 + * 0b111..divide by 8 + */ #define CCM_CBCDR_SEMC_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_SEMC_PODF_SHIFT)) & CCM_CBCDR_SEMC_PODF_MASK) #define CCM_CBCDR_PERIPH_CLK_SEL_MASK (0x2000000U) #define CCM_CBCDR_PERIPH_CLK_SEL_SHIFT (25U) +/*! PERIPH_CLK_SEL + * 0b0..derive clock from pre_periph_clk_sel + * 0b1..derive clock from periph_clk2_clk_divided + */ #define CCM_CBCDR_PERIPH_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_PERIPH_CLK_SEL_SHIFT)) & CCM_CBCDR_PERIPH_CLK_SEL_MASK) #define CCM_CBCDR_PERIPH_CLK2_PODF_MASK (0x38000000U) #define CCM_CBCDR_PERIPH_CLK2_PODF_SHIFT (27U) +/*! PERIPH_CLK2_PODF + * 0b000..divide by 1 + * 0b001..divide by 2 + * 0b010..divide by 3 + * 0b011..divide by 4 + * 0b100..divide by 5 + * 0b101..divide by 6 + * 0b110..divide by 7 + * 0b111..divide by 8 + */ #define CCM_CBCDR_PERIPH_CLK2_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_PERIPH_CLK2_PODF_SHIFT)) & CCM_CBCDR_PERIPH_CLK2_PODF_MASK) +/*! @} */ /*! @name CBCMR - CCM Bus Clock Multiplexer Register */ +/*! @{ */ #define CCM_CBCMR_LPSPI_CLK_SEL_MASK (0x30U) #define CCM_CBCMR_LPSPI_CLK_SEL_SHIFT (4U) +/*! LPSPI_CLK_SEL + * 0b00..derive clock from PLL3 PFD1 clk + * 0b01..derive clock from PLL3 PFD0 + * 0b10..derive clock from PLL2 + * 0b11..derive clock from PLL2 PFD2 + */ #define CCM_CBCMR_LPSPI_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_LPSPI_CLK_SEL_SHIFT)) & CCM_CBCMR_LPSPI_CLK_SEL_MASK) #define CCM_CBCMR_PERIPH_CLK2_SEL_MASK (0x3000U) #define CCM_CBCMR_PERIPH_CLK2_SEL_SHIFT (12U) +/*! PERIPH_CLK2_SEL + * 0b00..derive clock from pll3_sw_clk + * 0b01..derive clock from osc_clk (pll1_ref_clk) + * 0b10..derive clock from pll2_bypass_clk + * 0b11..reserved + */ #define CCM_CBCMR_PERIPH_CLK2_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_PERIPH_CLK2_SEL_SHIFT)) & CCM_CBCMR_PERIPH_CLK2_SEL_MASK) #define CCM_CBCMR_TRACE_CLK_SEL_MASK (0xC000U) #define CCM_CBCMR_TRACE_CLK_SEL_SHIFT (14U) +/*! TRACE_CLK_SEL + * 0b00..derive clock from PLL2 + * 0b01..derive clock from PLL2 PFD2 + * 0b10..derive clock from PLL2 PFD0 + * 0b11..derive clock from PLL2 PFD1 + */ #define CCM_CBCMR_TRACE_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_TRACE_CLK_SEL_SHIFT)) & CCM_CBCMR_TRACE_CLK_SEL_MASK) #define CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK (0xC0000U) #define CCM_CBCMR_PRE_PERIPH_CLK_SEL_SHIFT (18U) +/*! PRE_PERIPH_CLK_SEL + * 0b00..derive clock from PLL2 + * 0b01..derive clock from PLL2 PFD2 + * 0b10..derive clock from PLL2 PFD0 + * 0b11..derive clock from divided PLL1 + */ #define CCM_CBCMR_PRE_PERIPH_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_PRE_PERIPH_CLK_SEL_SHIFT)) & CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK) #define CCM_CBCMR_LCDIF_PODF_MASK (0x3800000U) #define CCM_CBCMR_LCDIF_PODF_SHIFT (23U) +/*! LCDIF_PODF + * 0b000..divide by 1 + * 0b001..divide by 2 + * 0b010..divide by 3 + * 0b011..divide by 4 + * 0b100..divide by 5 + * 0b101..divide by 6 + * 0b110..divide by 7 + * 0b111..divide by 8 + */ #define CCM_CBCMR_LCDIF_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_LCDIF_PODF_SHIFT)) & CCM_CBCMR_LCDIF_PODF_MASK) #define CCM_CBCMR_LPSPI_PODF_MASK (0x1C000000U) #define CCM_CBCMR_LPSPI_PODF_SHIFT (26U) +/*! LPSPI_PODF + * 0b000..divide by 1 + * 0b001..divide by 2 + * 0b010..divide by 3 + * 0b011..divide by 4 + * 0b100..divide by 5 + * 0b101..divide by 6 + * 0b110..divide by 7 + * 0b111..divide by 8 + */ #define CCM_CBCMR_LPSPI_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_LPSPI_PODF_SHIFT)) & CCM_CBCMR_LPSPI_PODF_MASK) +/*! @} */ /*! @name CSCMR1 - CCM Serial Clock Multiplexer Register 1 */ +/*! @{ */ #define CCM_CSCMR1_PERCLK_PODF_MASK (0x3FU) #define CCM_CSCMR1_PERCLK_PODF_SHIFT (0U) +/*! PERCLK_PODF + * 0b000000..divide by 1 + * 0b000001..divide by 2 + * 0b000010..divide by 3 + * 0b000011..divide by 4 + * 0b000100..divide by 5 + * 0b000101..divide by 6 + * 0b000110..divide by 7 + * 0b111111..divide by 64 + */ #define CCM_CSCMR1_PERCLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_PERCLK_PODF_SHIFT)) & CCM_CSCMR1_PERCLK_PODF_MASK) #define CCM_CSCMR1_PERCLK_CLK_SEL_MASK (0x40U) #define CCM_CSCMR1_PERCLK_CLK_SEL_SHIFT (6U) +/*! PERCLK_CLK_SEL + * 0b0..derive clock from ipg clk root + * 0b1..derive clock from osc_clk + */ #define CCM_CSCMR1_PERCLK_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_PERCLK_CLK_SEL_SHIFT)) & CCM_CSCMR1_PERCLK_CLK_SEL_MASK) #define CCM_CSCMR1_SAI1_CLK_SEL_MASK (0xC00U) #define CCM_CSCMR1_SAI1_CLK_SEL_SHIFT (10U) +/*! SAI1_CLK_SEL + * 0b00..derive clock from PLL3 PFD2 + * 0b01..derive clock from PLL5 + * 0b10..derive clock from PLL4 + * 0b11..Reserved + */ #define CCM_CSCMR1_SAI1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_SAI1_CLK_SEL_SHIFT)) & CCM_CSCMR1_SAI1_CLK_SEL_MASK) #define CCM_CSCMR1_SAI2_CLK_SEL_MASK (0x3000U) #define CCM_CSCMR1_SAI2_CLK_SEL_SHIFT (12U) +/*! SAI2_CLK_SEL + * 0b00..derive clock from PLL3 PFD2 + * 0b01..derive clock from PLL5 + * 0b10..derive clock from PLL4 + * 0b11..Reserved + */ #define CCM_CSCMR1_SAI2_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_SAI2_CLK_SEL_SHIFT)) & CCM_CSCMR1_SAI2_CLK_SEL_MASK) #define CCM_CSCMR1_SAI3_CLK_SEL_MASK (0xC000U) #define CCM_CSCMR1_SAI3_CLK_SEL_SHIFT (14U) +/*! SAI3_CLK_SEL + * 0b00..derive clock from PLL3 PFD2 + * 0b01..derive clock from PLL5 + * 0b10..derive clock from PLL4 + * 0b11..Reserved + */ #define CCM_CSCMR1_SAI3_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_SAI3_CLK_SEL_SHIFT)) & CCM_CSCMR1_SAI3_CLK_SEL_MASK) #define CCM_CSCMR1_USDHC1_CLK_SEL_MASK (0x10000U) #define CCM_CSCMR1_USDHC1_CLK_SEL_SHIFT (16U) +/*! USDHC1_CLK_SEL + * 0b0..derive clock from PLL2 PFD2 + * 0b1..derive clock from PLL2 PFD0 + */ #define CCM_CSCMR1_USDHC1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_USDHC1_CLK_SEL_SHIFT)) & CCM_CSCMR1_USDHC1_CLK_SEL_MASK) #define CCM_CSCMR1_USDHC2_CLK_SEL_MASK (0x20000U) #define CCM_CSCMR1_USDHC2_CLK_SEL_SHIFT (17U) +/*! USDHC2_CLK_SEL + * 0b0..derive clock from PLL2 PFD2 + * 0b1..derive clock from PLL2 PFD0 + */ #define CCM_CSCMR1_USDHC2_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_USDHC2_CLK_SEL_SHIFT)) & CCM_CSCMR1_USDHC2_CLK_SEL_MASK) #define CCM_CSCMR1_FLEXSPI_PODF_MASK (0x3800000U) #define CCM_CSCMR1_FLEXSPI_PODF_SHIFT (23U) +/*! FLEXSPI_PODF + * 0b000..divide by 1 + * 0b001..divide by 2 + * 0b010..divide by 3 + * 0b011..divide by 4 + * 0b100..divide by 5 + * 0b101..divide by 6 + * 0b110..divide by 7 + * 0b111..divide by 8 + */ #define CCM_CSCMR1_FLEXSPI_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_FLEXSPI_PODF_SHIFT)) & CCM_CSCMR1_FLEXSPI_PODF_MASK) #define CCM_CSCMR1_FLEXSPI_CLK_SEL_MASK (0x60000000U) #define CCM_CSCMR1_FLEXSPI_CLK_SEL_SHIFT (29U) +/*! FLEXSPI_CLK_SEL + * 0b00..derive clock from semc_clk_root_pre + * 0b01..derive clock from pll3_sw_clk + * 0b10..derive clock from PLL2 PFD2 + * 0b11..derive clock from PLL3 PFD0 + */ #define CCM_CSCMR1_FLEXSPI_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_FLEXSPI_CLK_SEL_SHIFT)) & CCM_CSCMR1_FLEXSPI_CLK_SEL_MASK) +/*! @} */ /*! @name CSCMR2 - CCM Serial Clock Multiplexer Register 2 */ +/*! @{ */ #define CCM_CSCMR2_CAN_CLK_PODF_MASK (0xFCU) #define CCM_CSCMR2_CAN_CLK_PODF_SHIFT (2U) +/*! CAN_CLK_PODF + * 0b000000..divide by 1 + * 0b000111..divide by 8 + * 0b111111..divide by 2^6 + */ #define CCM_CSCMR2_CAN_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR2_CAN_CLK_PODF_SHIFT)) & CCM_CSCMR2_CAN_CLK_PODF_MASK) #define CCM_CSCMR2_CAN_CLK_SEL_MASK (0x300U) #define CCM_CSCMR2_CAN_CLK_SEL_SHIFT (8U) +/*! CAN_CLK_SEL + * 0b00..derive clock from pll3_sw_clk divided clock (60M) + * 0b01..derive clock from osc_clk (24M) + * 0b10..derive clock from pll3_sw_clk divided clock (80M) + * 0b11..Disable FlexCAN clock + */ #define CCM_CSCMR2_CAN_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR2_CAN_CLK_SEL_SHIFT)) & CCM_CSCMR2_CAN_CLK_SEL_MASK) #define CCM_CSCMR2_FLEXIO2_CLK_SEL_MASK (0x180000U) #define CCM_CSCMR2_FLEXIO2_CLK_SEL_SHIFT (19U) +/*! FLEXIO2_CLK_SEL + * 0b00..derive clock from PLL4 divided clock + * 0b01..derive clock from PLL3 PFD2 clock + * 0b10..derive clock from PLL5 clock + * 0b11..derive clock from pll3_sw_clk + */ #define CCM_CSCMR2_FLEXIO2_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR2_FLEXIO2_CLK_SEL_SHIFT)) & CCM_CSCMR2_FLEXIO2_CLK_SEL_MASK) +/*! @} */ /*! @name CSCDR1 - CCM Serial Clock Divider Register 1 */ +/*! @{ */ #define CCM_CSCDR1_UART_CLK_PODF_MASK (0x3FU) #define CCM_CSCDR1_UART_CLK_PODF_SHIFT (0U) +/*! UART_CLK_PODF + * 0b000000..divide by 1 + * 0b111111..divide by 2^6 + */ #define CCM_CSCDR1_UART_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR1_UART_CLK_PODF_SHIFT)) & CCM_CSCDR1_UART_CLK_PODF_MASK) #define CCM_CSCDR1_UART_CLK_SEL_MASK (0x40U) #define CCM_CSCDR1_UART_CLK_SEL_SHIFT (6U) +/*! UART_CLK_SEL + * 0b0..derive clock from pll3_80m + * 0b1..derive clock from osc_clk + */ #define CCM_CSCDR1_UART_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR1_UART_CLK_SEL_SHIFT)) & CCM_CSCDR1_UART_CLK_SEL_MASK) #define CCM_CSCDR1_USDHC1_PODF_MASK (0x3800U) #define CCM_CSCDR1_USDHC1_PODF_SHIFT (11U) +/*! USDHC1_PODF + * 0b000..divide by 1 + * 0b001..divide by 2 + * 0b010..divide by 3 + * 0b011..divide by 4 + * 0b100..divide by 5 + * 0b101..divide by 6 + * 0b110..divide by 7 + * 0b111..divide by 8 + */ #define CCM_CSCDR1_USDHC1_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR1_USDHC1_PODF_SHIFT)) & CCM_CSCDR1_USDHC1_PODF_MASK) #define CCM_CSCDR1_USDHC2_PODF_MASK (0x70000U) #define CCM_CSCDR1_USDHC2_PODF_SHIFT (16U) +/*! USDHC2_PODF + * 0b000..divide by 1 + * 0b001..divide by 2 + * 0b010..divide by 3 + * 0b011..divide by 4 + * 0b100..divide by 5 + * 0b101..divide by 6 + * 0b110..divide by 7 + * 0b111..divide by 8 + */ #define CCM_CSCDR1_USDHC2_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR1_USDHC2_PODF_SHIFT)) & CCM_CSCDR1_USDHC2_PODF_MASK) -#define CCM_CSCDR1_TRACE_PODF_MASK (0xE000000U) +#define CCM_CSCDR1_TRACE_PODF_MASK (0x6000000U) #define CCM_CSCDR1_TRACE_PODF_SHIFT (25U) +/*! TRACE_PODF + * 0b00..divide by 1 + * 0b01..divide by 2 + * 0b10..divide by 3 + * 0b11..divide by 4 + */ #define CCM_CSCDR1_TRACE_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR1_TRACE_PODF_SHIFT)) & CCM_CSCDR1_TRACE_PODF_MASK) +/*! @} */ /*! @name CS1CDR - CCM Clock Divider Register */ +/*! @{ */ #define CCM_CS1CDR_SAI1_CLK_PODF_MASK (0x3FU) #define CCM_CS1CDR_SAI1_CLK_PODF_SHIFT (0U) +/*! SAI1_CLK_PODF + * 0b000000..divide by 1 + * 0b111111..divide by 2^6 + */ #define CCM_CS1CDR_SAI1_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_SAI1_CLK_PODF_SHIFT)) & CCM_CS1CDR_SAI1_CLK_PODF_MASK) #define CCM_CS1CDR_SAI1_CLK_PRED_MASK (0x1C0U) #define CCM_CS1CDR_SAI1_CLK_PRED_SHIFT (6U) +/*! SAI1_CLK_PRED + * 0b000..divide by 1 + * 0b001..divide by 2 + * 0b010..divide by 3 + * 0b011..divide by 4 + * 0b100..divide by 5 + * 0b101..divide by 6 + * 0b110..divide by 7 + * 0b111..divide by 8 + */ #define CCM_CS1CDR_SAI1_CLK_PRED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_SAI1_CLK_PRED_SHIFT)) & CCM_CS1CDR_SAI1_CLK_PRED_MASK) #define CCM_CS1CDR_FLEXIO2_CLK_PRED_MASK (0xE00U) #define CCM_CS1CDR_FLEXIO2_CLK_PRED_SHIFT (9U) +/*! FLEXIO2_CLK_PRED + * 0b000..divide by 1 + * 0b001..divide by 2 + * 0b010..divide by 3 + * 0b011..divide by 4 + * 0b100..divide by 5 + * 0b101..divide by 6 + * 0b110..divide by 7 + * 0b111..divide by 8 + */ #define CCM_CS1CDR_FLEXIO2_CLK_PRED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_FLEXIO2_CLK_PRED_SHIFT)) & CCM_CS1CDR_FLEXIO2_CLK_PRED_MASK) #define CCM_CS1CDR_SAI3_CLK_PODF_MASK (0x3F0000U) #define CCM_CS1CDR_SAI3_CLK_PODF_SHIFT (16U) +/*! SAI3_CLK_PODF + * 0b000000..divide by 1 + * 0b111111..divide by 2^6 + */ #define CCM_CS1CDR_SAI3_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_SAI3_CLK_PODF_SHIFT)) & CCM_CS1CDR_SAI3_CLK_PODF_MASK) #define CCM_CS1CDR_SAI3_CLK_PRED_MASK (0x1C00000U) #define CCM_CS1CDR_SAI3_CLK_PRED_SHIFT (22U) +/*! SAI3_CLK_PRED + * 0b000..divide by 1 + * 0b001..divide by 2 + * 0b010..divide by 3 + * 0b011..divide by 4 + * 0b100..divide by 5 + * 0b101..divide by 6 + * 0b110..divide by 7 + * 0b111..divide by 8 + */ #define CCM_CS1CDR_SAI3_CLK_PRED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_SAI3_CLK_PRED_SHIFT)) & CCM_CS1CDR_SAI3_CLK_PRED_MASK) #define CCM_CS1CDR_FLEXIO2_CLK_PODF_MASK (0xE000000U) #define CCM_CS1CDR_FLEXIO2_CLK_PODF_SHIFT (25U) +/*! FLEXIO2_CLK_PODF + * 0b000..divide by 1 + * 0b001..divide by 2 + * 0b010..divide by 3 + * 0b011..divide by 4 + * 0b100..divide by 5 + * 0b101..divide by 6 + * 0b110..divide by 7 + * 0b111..divide by 8 + */ #define CCM_CS1CDR_FLEXIO2_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_FLEXIO2_CLK_PODF_SHIFT)) & CCM_CS1CDR_FLEXIO2_CLK_PODF_MASK) +/*! @} */ /*! @name CS2CDR - CCM Clock Divider Register */ +/*! @{ */ #define CCM_CS2CDR_SAI2_CLK_PODF_MASK (0x3FU) #define CCM_CS2CDR_SAI2_CLK_PODF_SHIFT (0U) +/*! SAI2_CLK_PODF + * 0b000000..divide by 1 + * 0b111111..divide by 2^6 + */ #define CCM_CS2CDR_SAI2_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS2CDR_SAI2_CLK_PODF_SHIFT)) & CCM_CS2CDR_SAI2_CLK_PODF_MASK) #define CCM_CS2CDR_SAI2_CLK_PRED_MASK (0x1C0U) #define CCM_CS2CDR_SAI2_CLK_PRED_SHIFT (6U) +/*! SAI2_CLK_PRED + * 0b000..divide by 1 + * 0b001..divide by 2 + * 0b010..divide by 3 + * 0b011..divide by 4 + * 0b100..divide by 5 + * 0b101..divide by 6 + * 0b110..divide by 7 + * 0b111..divide by 8 + */ #define CCM_CS2CDR_SAI2_CLK_PRED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS2CDR_SAI2_CLK_PRED_SHIFT)) & CCM_CS2CDR_SAI2_CLK_PRED_MASK) +/*! @} */ /*! @name CDCDR - CCM D1 Clock Divider Register */ +/*! @{ */ #define CCM_CDCDR_FLEXIO1_CLK_SEL_MASK (0x180U) #define CCM_CDCDR_FLEXIO1_CLK_SEL_SHIFT (7U) +/*! FLEXIO1_CLK_SEL + * 0b00..derive clock from PLL4 + * 0b01..derive clock from PLL3 PFD2 + * 0b10..derive clock from PLL5 + * 0b11..derive clock from pll3_sw_clk + */ #define CCM_CDCDR_FLEXIO1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDCDR_FLEXIO1_CLK_SEL_SHIFT)) & CCM_CDCDR_FLEXIO1_CLK_SEL_MASK) #define CCM_CDCDR_FLEXIO1_CLK_PODF_MASK (0xE00U) #define CCM_CDCDR_FLEXIO1_CLK_PODF_SHIFT (9U) +/*! FLEXIO1_CLK_PODF + * 0b000..divide by 1 + * 0b111..divide by 8 + */ #define CCM_CDCDR_FLEXIO1_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDCDR_FLEXIO1_CLK_PODF_SHIFT)) & CCM_CDCDR_FLEXIO1_CLK_PODF_MASK) #define CCM_CDCDR_FLEXIO1_CLK_PRED_MASK (0x7000U) #define CCM_CDCDR_FLEXIO1_CLK_PRED_SHIFT (12U) +/*! FLEXIO1_CLK_PRED + * 0b000..divide by 1 (do not use with high input frequencies) + * 0b001..divide by 2 + * 0b010..divide by 3 + * 0b111..divide by 8 + */ #define CCM_CDCDR_FLEXIO1_CLK_PRED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDCDR_FLEXIO1_CLK_PRED_SHIFT)) & CCM_CDCDR_FLEXIO1_CLK_PRED_MASK) #define CCM_CDCDR_SPDIF0_CLK_SEL_MASK (0x300000U) #define CCM_CDCDR_SPDIF0_CLK_SEL_SHIFT (20U) +/*! SPDIF0_CLK_SEL + * 0b00..derive clock from PLL4 + * 0b01..derive clock from PLL3 PFD2 + * 0b10..derive clock from PLL5 + * 0b11..derive clock from pll3_sw_clk + */ #define CCM_CDCDR_SPDIF0_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDCDR_SPDIF0_CLK_SEL_SHIFT)) & CCM_CDCDR_SPDIF0_CLK_SEL_MASK) #define CCM_CDCDR_SPDIF0_CLK_PODF_MASK (0x1C00000U) #define CCM_CDCDR_SPDIF0_CLK_PODF_SHIFT (22U) +/*! SPDIF0_CLK_PODF + * 0b000..divide by 1 + * 0b111..divide by 8 + */ #define CCM_CDCDR_SPDIF0_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDCDR_SPDIF0_CLK_PODF_SHIFT)) & CCM_CDCDR_SPDIF0_CLK_PODF_MASK) #define CCM_CDCDR_SPDIF0_CLK_PRED_MASK (0xE000000U) #define CCM_CDCDR_SPDIF0_CLK_PRED_SHIFT (25U) +/*! SPDIF0_CLK_PRED + * 0b000..divide by 1 (do not use with high input frequencies) + * 0b001..divide by 2 + * 0b010..divide by 3 + * 0b111..divide by 8 + */ #define CCM_CDCDR_SPDIF0_CLK_PRED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDCDR_SPDIF0_CLK_PRED_SHIFT)) & CCM_CDCDR_SPDIF0_CLK_PRED_MASK) +/*! @} */ /*! @name CSCDR2 - CCM Serial Clock Divider Register 2 */ -#define CCM_CSCDR2_LCDIF_CLK_SEL_MASK (0xE00U) -#define CCM_CSCDR2_LCDIF_CLK_SEL_SHIFT (9U) -#define CCM_CSCDR2_LCDIF_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR2_LCDIF_CLK_SEL_SHIFT)) & CCM_CSCDR2_LCDIF_CLK_SEL_MASK) +/*! @{ */ #define CCM_CSCDR2_LCDIF_PRED_MASK (0x7000U) #define CCM_CSCDR2_LCDIF_PRED_SHIFT (12U) +/*! LCDIF_PRED + * 0b000..divide by 1 + * 0b001..divide by 2 + * 0b010..divide by 3 + * 0b011..divide by 4 + * 0b100..divide by 5 + * 0b101..divide by 6 + * 0b110..divide by 7 + * 0b111..divide by 8 + */ #define CCM_CSCDR2_LCDIF_PRED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR2_LCDIF_PRED_SHIFT)) & CCM_CSCDR2_LCDIF_PRED_MASK) #define CCM_CSCDR2_LCDIF_PRE_CLK_SEL_MASK (0x38000U) #define CCM_CSCDR2_LCDIF_PRE_CLK_SEL_SHIFT (15U) +/*! LCDIF_PRE_CLK_SEL + * 0b000..derive clock from PLL2 + * 0b001..derive clock from PLL3 PFD3 + * 0b010..derive clock from PLL5 + * 0b011..derive clock from PLL2 PFD0 + * 0b100..derive clock from PLL2 PFD1 + * 0b101..derive clock from PLL3 PFD1 + */ #define CCM_CSCDR2_LCDIF_PRE_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR2_LCDIF_PRE_CLK_SEL_SHIFT)) & CCM_CSCDR2_LCDIF_PRE_CLK_SEL_MASK) #define CCM_CSCDR2_LPI2C_CLK_SEL_MASK (0x40000U) #define CCM_CSCDR2_LPI2C_CLK_SEL_SHIFT (18U) +/*! LPI2C_CLK_SEL + * 0b0..derive clock from pll3_60m + * 0b1..derive clock from osc_clk + */ #define CCM_CSCDR2_LPI2C_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR2_LPI2C_CLK_SEL_SHIFT)) & CCM_CSCDR2_LPI2C_CLK_SEL_MASK) #define CCM_CSCDR2_LPI2C_CLK_PODF_MASK (0x1F80000U) #define CCM_CSCDR2_LPI2C_CLK_PODF_SHIFT (19U) +/*! LPI2C_CLK_PODF + * 0b000000..divide by 1 + * 0b111111..divide by 2^6 + */ #define CCM_CSCDR2_LPI2C_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR2_LPI2C_CLK_PODF_SHIFT)) & CCM_CSCDR2_LPI2C_CLK_PODF_MASK) +/*! @} */ /*! @name CSCDR3 - CCM Serial Clock Divider Register 3 */ +/*! @{ */ #define CCM_CSCDR3_CSI_CLK_SEL_MASK (0x600U) #define CCM_CSCDR3_CSI_CLK_SEL_SHIFT (9U) +/*! CSI_CLK_SEL + * 0b00..derive clock from osc_clk (24M) + * 0b01..derive clock from PLL2 PFD2 + * 0b10..derive clock from pll3_120M + * 0b11..derive clock from PLL3 PFD1 + */ #define CCM_CSCDR3_CSI_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR3_CSI_CLK_SEL_SHIFT)) & CCM_CSCDR3_CSI_CLK_SEL_MASK) #define CCM_CSCDR3_CSI_PODF_MASK (0x3800U) #define CCM_CSCDR3_CSI_PODF_SHIFT (11U) +/*! CSI_PODF + * 0b000..divide by 1 + * 0b001..divide by 2 + * 0b010..divide by 3 + * 0b011..divide by 4 + * 0b100..divide by 5 + * 0b101..divide by 6 + * 0b110..divide by 7 + * 0b111..divide by 8 + */ #define CCM_CSCDR3_CSI_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR3_CSI_PODF_SHIFT)) & CCM_CSCDR3_CSI_PODF_MASK) +/*! @} */ /*! @name CDHIPR - CCM Divider Handshake In-Process Register */ +/*! @{ */ #define CCM_CDHIPR_SEMC_PODF_BUSY_MASK (0x1U) #define CCM_CDHIPR_SEMC_PODF_BUSY_SHIFT (0U) +/*! SEMC_PODF_BUSY + * 0b0..divider is not busy and its value represents the actual division. + * 0b1..divider is busy with handshake process with module. The value read in the divider represents the previous value of the division factor, and after the handshake the written value of the semc_podf will be applied. + */ #define CCM_CDHIPR_SEMC_PODF_BUSY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDHIPR_SEMC_PODF_BUSY_SHIFT)) & CCM_CDHIPR_SEMC_PODF_BUSY_MASK) #define CCM_CDHIPR_AHB_PODF_BUSY_MASK (0x2U) #define CCM_CDHIPR_AHB_PODF_BUSY_SHIFT (1U) +/*! AHB_PODF_BUSY + * 0b0..divider is not busy and its value represents the actual division. + * 0b1..divider is busy with handshake process with module. The value read in the divider represents the previous value of the division factor, and after the handshake the written value of the ahb_podf will be applied. + */ #define CCM_CDHIPR_AHB_PODF_BUSY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDHIPR_AHB_PODF_BUSY_SHIFT)) & CCM_CDHIPR_AHB_PODF_BUSY_MASK) #define CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY_MASK (0x8U) #define CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY_SHIFT (3U) +/*! PERIPH2_CLK_SEL_BUSY + * 0b0..mux is not busy and its value represents the actual division. + * 0b1..mux is busy with handshake process with module. The value read in the periph2_clk_sel represents the previous value of select, and after the handshake periph2_clk_sel value will be applied. + */ #define CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY_SHIFT)) & CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY_MASK) #define CCM_CDHIPR_PERIPH_CLK_SEL_BUSY_MASK (0x20U) #define CCM_CDHIPR_PERIPH_CLK_SEL_BUSY_SHIFT (5U) +/*! PERIPH_CLK_SEL_BUSY + * 0b0..mux is not busy and its value represents the actual division. + * 0b1..mux is busy with handshake process with module. The value read in the periph_clk_sel represents the previous value of select, and after the handshake periph_clk_sel value will be applied. + */ #define CCM_CDHIPR_PERIPH_CLK_SEL_BUSY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDHIPR_PERIPH_CLK_SEL_BUSY_SHIFT)) & CCM_CDHIPR_PERIPH_CLK_SEL_BUSY_MASK) #define CCM_CDHIPR_ARM_PODF_BUSY_MASK (0x10000U) #define CCM_CDHIPR_ARM_PODF_BUSY_SHIFT (16U) +/*! ARM_PODF_BUSY + * 0b0..divider is not busy and its value represents the actual division. + * 0b1..divider is busy with handshake process with module. The value read in the divider represents the previous value of the division factor, and after the handshake the written value of the arm_podf will be applied. + */ #define CCM_CDHIPR_ARM_PODF_BUSY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDHIPR_ARM_PODF_BUSY_SHIFT)) & CCM_CDHIPR_ARM_PODF_BUSY_MASK) +/*! @} */ /*! @name CLPCR - CCM Low Power Control Register */ +/*! @{ */ #define CCM_CLPCR_LPM_MASK (0x3U) #define CCM_CLPCR_LPM_SHIFT (0U) +/*! LPM + * 0b00..Remain in run mode + * 0b01..Transfer to wait mode + * 0b10..Transfer to stop mode + * 0b11..Reserved + */ #define CCM_CLPCR_LPM(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_LPM_SHIFT)) & CCM_CLPCR_LPM_MASK) #define CCM_CLPCR_ARM_CLK_DIS_ON_LPM_MASK (0x20U) #define CCM_CLPCR_ARM_CLK_DIS_ON_LPM_SHIFT (5U) +/*! ARM_CLK_DIS_ON_LPM + * 0b0..ARM clock enabled on wait mode. + * 0b1..ARM clock disabled on wait mode. . + */ #define CCM_CLPCR_ARM_CLK_DIS_ON_LPM(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_ARM_CLK_DIS_ON_LPM_SHIFT)) & CCM_CLPCR_ARM_CLK_DIS_ON_LPM_MASK) #define CCM_CLPCR_SBYOS_MASK (0x40U) #define CCM_CLPCR_SBYOS_SHIFT (6U) +/*! SBYOS + * 0b0..On-chip oscillator will not be powered down, after next entrance to STOP mode. (CCM_REF_EN_B will remain asserted - '0' and cosc_pwrdown will remain de asserted - '0') + * 0b1..On-chip oscillator will be powered down, after next entrance to STOP mode. (CCM_REF_EN_B will be deasserted - '1' and cosc_pwrdown will be asserted - '1'). When returning from STOP mode, external oscillator will be enabled again, on-chip oscillator will return to oscillator mode, and after oscnt count, CCM will continue with the exit from the STOP mode process. + */ #define CCM_CLPCR_SBYOS(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_SBYOS_SHIFT)) & CCM_CLPCR_SBYOS_MASK) #define CCM_CLPCR_DIS_REF_OSC_MASK (0x80U) #define CCM_CLPCR_DIS_REF_OSC_SHIFT (7U) +/*! DIS_REF_OSC + * 0b0..external high frequency oscillator will be enabled, i.e. CCM_REF_EN_B = '0'. + * 0b1..external high frequency oscillator will be disabled, i.e. CCM_REF_EN_B = '1' + */ #define CCM_CLPCR_DIS_REF_OSC(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_DIS_REF_OSC_SHIFT)) & CCM_CLPCR_DIS_REF_OSC_MASK) #define CCM_CLPCR_VSTBY_MASK (0x100U) #define CCM_CLPCR_VSTBY_SHIFT (8U) +/*! VSTBY + * 0b0..Voltage will not be changed to standby voltage after next entrance to STOP mode. ( PMIC_STBY_REQ will remain negated - '0') + * 0b1..Voltage will be requested to change to standby voltage after next entrance to stop mode. ( PMIC_STBY_REQ will be asserted - '1'). + */ #define CCM_CLPCR_VSTBY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_VSTBY_SHIFT)) & CCM_CLPCR_VSTBY_MASK) #define CCM_CLPCR_STBY_COUNT_MASK (0x600U) #define CCM_CLPCR_STBY_COUNT_SHIFT (9U) +/*! STBY_COUNT + * 0b00..CCM will wait (1*pmic_delay_scaler)+1 ckil clock cycles + * 0b01..CCM will wait (3*pmic_delay_scaler)+1 ckil clock cycles + * 0b10..CCM will wait (7*pmic_delay_scaler)+1 ckil clock cycles + * 0b11..CCM will wait (15*pmic_delay_scaler)+1 ckil clock cycles + */ #define CCM_CLPCR_STBY_COUNT(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_STBY_COUNT_SHIFT)) & CCM_CLPCR_STBY_COUNT_MASK) #define CCM_CLPCR_COSC_PWRDOWN_MASK (0x800U) #define CCM_CLPCR_COSC_PWRDOWN_SHIFT (11U) +/*! COSC_PWRDOWN + * 0b0..On chip oscillator will not be powered down, i.e. cosc_pwrdown = '0'. + * 0b1..On chip oscillator will be powered down, i.e. cosc_pwrdown = '1'. + */ #define CCM_CLPCR_COSC_PWRDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_COSC_PWRDOWN_SHIFT)) & CCM_CLPCR_COSC_PWRDOWN_MASK) #define CCM_CLPCR_BYPASS_LPM_HS1_MASK (0x80000U) #define CCM_CLPCR_BYPASS_LPM_HS1_SHIFT (19U) @@ -3195,101 +4654,261 @@ typedef struct { #define CCM_CLPCR_BYPASS_LPM_HS0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_BYPASS_LPM_HS0_SHIFT)) & CCM_CLPCR_BYPASS_LPM_HS0_MASK) #define CCM_CLPCR_MASK_CORE0_WFI_MASK (0x400000U) #define CCM_CLPCR_MASK_CORE0_WFI_SHIFT (22U) +/*! MASK_CORE0_WFI + * 0b0..WFI of core0 is not masked + * 0b1..WFI of core0 is masked + */ #define CCM_CLPCR_MASK_CORE0_WFI(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_MASK_CORE0_WFI_SHIFT)) & CCM_CLPCR_MASK_CORE0_WFI_MASK) #define CCM_CLPCR_MASK_SCU_IDLE_MASK (0x4000000U) #define CCM_CLPCR_MASK_SCU_IDLE_SHIFT (26U) +/*! MASK_SCU_IDLE + * 0b1..SCU IDLE is masked + * 0b0..SCU IDLE is not masked + */ #define CCM_CLPCR_MASK_SCU_IDLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_MASK_SCU_IDLE_SHIFT)) & CCM_CLPCR_MASK_SCU_IDLE_MASK) #define CCM_CLPCR_MASK_L2CC_IDLE_MASK (0x8000000U) #define CCM_CLPCR_MASK_L2CC_IDLE_SHIFT (27U) +/*! MASK_L2CC_IDLE + * 0b1..L2CC IDLE is masked + * 0b0..L2CC IDLE is not masked + */ #define CCM_CLPCR_MASK_L2CC_IDLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_MASK_L2CC_IDLE_SHIFT)) & CCM_CLPCR_MASK_L2CC_IDLE_MASK) +/*! @} */ /*! @name CISR - CCM Interrupt Status Register */ +/*! @{ */ #define CCM_CISR_LRF_PLL_MASK (0x1U) #define CCM_CISR_LRF_PLL_SHIFT (0U) +/*! LRF_PLL + * 0b0..interrupt is not generated due to lock ready of all enabled and not bypaseed PLLs + * 0b1..interrupt generated due to lock ready of all enabled and not bypaseed PLLs + */ #define CCM_CISR_LRF_PLL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_LRF_PLL_SHIFT)) & CCM_CISR_LRF_PLL_MASK) #define CCM_CISR_COSC_READY_MASK (0x40U) #define CCM_CISR_COSC_READY_SHIFT (6U) +/*! COSC_READY + * 0b0..interrupt is not generated due to on board oscillator ready + * 0b1..interrupt generated due to on board oscillator ready + */ #define CCM_CISR_COSC_READY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_COSC_READY_SHIFT)) & CCM_CISR_COSC_READY_MASK) #define CCM_CISR_SEMC_PODF_LOADED_MASK (0x20000U) #define CCM_CISR_SEMC_PODF_LOADED_SHIFT (17U) +/*! SEMC_PODF_LOADED + * 0b0..interrupt is not generated due to frequency change of semc_podf + * 0b1..interrupt generated due to frequency change of semc_podf + */ #define CCM_CISR_SEMC_PODF_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_SEMC_PODF_LOADED_SHIFT)) & CCM_CISR_SEMC_PODF_LOADED_MASK) #define CCM_CISR_PERIPH2_CLK_SEL_LOADED_MASK (0x80000U) #define CCM_CISR_PERIPH2_CLK_SEL_LOADED_SHIFT (19U) +/*! PERIPH2_CLK_SEL_LOADED + * 0b0..interrupt is not generated due to frequency change of periph2_clk_sel + * 0b1..interrupt generated due to frequency change of periph2_clk_sel + */ #define CCM_CISR_PERIPH2_CLK_SEL_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_PERIPH2_CLK_SEL_LOADED_SHIFT)) & CCM_CISR_PERIPH2_CLK_SEL_LOADED_MASK) #define CCM_CISR_AHB_PODF_LOADED_MASK (0x100000U) #define CCM_CISR_AHB_PODF_LOADED_SHIFT (20U) +/*! AHB_PODF_LOADED + * 0b0..interrupt is not generated due to frequency change of ahb_podf + * 0b1..interrupt generated due to frequency change of ahb_podf + */ #define CCM_CISR_AHB_PODF_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_AHB_PODF_LOADED_SHIFT)) & CCM_CISR_AHB_PODF_LOADED_MASK) #define CCM_CISR_PERIPH_CLK_SEL_LOADED_MASK (0x400000U) #define CCM_CISR_PERIPH_CLK_SEL_LOADED_SHIFT (22U) +/*! PERIPH_CLK_SEL_LOADED + * 0b0..interrupt is not generated due to update of periph_clk_sel. + * 0b1..interrupt generated due to update of periph_clk_sel. + */ #define CCM_CISR_PERIPH_CLK_SEL_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_PERIPH_CLK_SEL_LOADED_SHIFT)) & CCM_CISR_PERIPH_CLK_SEL_LOADED_MASK) #define CCM_CISR_ARM_PODF_LOADED_MASK (0x4000000U) #define CCM_CISR_ARM_PODF_LOADED_SHIFT (26U) +/*! ARM_PODF_LOADED + * 0b0..interrupt is not generated due to frequency change of arm_podf + * 0b1..interrupt generated due to frequency change of arm_podf + */ #define CCM_CISR_ARM_PODF_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_ARM_PODF_LOADED_SHIFT)) & CCM_CISR_ARM_PODF_LOADED_MASK) +/*! @} */ /*! @name CIMR - CCM Interrupt Mask Register */ +/*! @{ */ #define CCM_CIMR_MASK_LRF_PLL_MASK (0x1U) #define CCM_CIMR_MASK_LRF_PLL_SHIFT (0U) +/*! MASK_LRF_PLL + * 0b0..don't mask interrupt due to lrf of PLLs - interrupt will be created + * 0b1..mask interrupt due to lrf of PLLs + */ #define CCM_CIMR_MASK_LRF_PLL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_MASK_LRF_PLL_SHIFT)) & CCM_CIMR_MASK_LRF_PLL_MASK) #define CCM_CIMR_MASK_COSC_READY_MASK (0x40U) #define CCM_CIMR_MASK_COSC_READY_SHIFT (6U) +/*! MASK_COSC_READY + * 0b0..don't mask interrupt due to on board oscillator ready - interrupt will be created + * 0b1..mask interrupt due to on board oscillator ready + */ #define CCM_CIMR_MASK_COSC_READY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_MASK_COSC_READY_SHIFT)) & CCM_CIMR_MASK_COSC_READY_MASK) #define CCM_CIMR_MASK_SEMC_PODF_LOADED_MASK (0x20000U) #define CCM_CIMR_MASK_SEMC_PODF_LOADED_SHIFT (17U) +/*! MASK_SEMC_PODF_LOADED + * 0b0..don't mask interrupt due to frequency change of semc_podf - interrupt will be created + * 0b1..mask interrupt due to frequency change of semc_podf + */ #define CCM_CIMR_MASK_SEMC_PODF_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_MASK_SEMC_PODF_LOADED_SHIFT)) & CCM_CIMR_MASK_SEMC_PODF_LOADED_MASK) #define CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED_MASK (0x80000U) #define CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED_SHIFT (19U) +/*! MASK_PERIPH2_CLK_SEL_LOADED + * 0b0..don't mask interrupt due to update of periph2_clk_sel - interrupt will be created + * 0b1..mask interrupt due to update of periph2_clk_sel + */ #define CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED_SHIFT)) & CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED_MASK) #define CCM_CIMR_MASK_AHB_PODF_LOADED_MASK (0x100000U) #define CCM_CIMR_MASK_AHB_PODF_LOADED_SHIFT (20U) +/*! MASK_AHB_PODF_LOADED + * 0b0..don't mask interrupt due to frequency change of ahb_podf - interrupt will be created + * 0b1..mask interrupt due to frequency change of ahb_podf + */ #define CCM_CIMR_MASK_AHB_PODF_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_MASK_AHB_PODF_LOADED_SHIFT)) & CCM_CIMR_MASK_AHB_PODF_LOADED_MASK) #define CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED_MASK (0x400000U) #define CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED_SHIFT (22U) +/*! MASK_PERIPH_CLK_SEL_LOADED + * 0b0..don't mask interrupt due to update of periph_clk_sel - interrupt will be created + * 0b1..mask interrupt due to update of periph_clk_sel + */ #define CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED_SHIFT)) & CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED_MASK) #define CCM_CIMR_ARM_PODF_LOADED_MASK (0x4000000U) #define CCM_CIMR_ARM_PODF_LOADED_SHIFT (26U) +/*! ARM_PODF_LOADED + * 0b0..don't mask interrupt due to frequency change of arm_podf - interrupt will be created + * 0b1..mask interrupt due to frequency change of arm_podf + */ #define CCM_CIMR_ARM_PODF_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_ARM_PODF_LOADED_SHIFT)) & CCM_CIMR_ARM_PODF_LOADED_MASK) +/*! @} */ /*! @name CCOSR - CCM Clock Output Source Register */ +/*! @{ */ #define CCM_CCOSR_CLKO1_SEL_MASK (0xFU) #define CCM_CCOSR_CLKO1_SEL_SHIFT (0U) +/*! CLKO1_SEL + * 0b0000..USB1 PLL clock (divided by 2) + * 0b0001..SYS PLL clock (divided by 2) + * 0b0011..VIDEO PLL clock (divided by 2) + * 0b0101..semc_clk_root + * 0b0110..Reserved + * 0b1010..lcdif_pix_clk_root + * 0b1011..ahb_clk_root + * 0b1100..ipg_clk_root + * 0b1101..perclk_root + * 0b1110..ckil_sync_clk_root + * 0b1111..pll4_main_clk + */ #define CCM_CCOSR_CLKO1_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLKO1_SEL_SHIFT)) & CCM_CCOSR_CLKO1_SEL_MASK) #define CCM_CCOSR_CLKO1_DIV_MASK (0x70U) #define CCM_CCOSR_CLKO1_DIV_SHIFT (4U) +/*! CLKO1_DIV + * 0b000..divide by 1 + * 0b001..divide by 2 + * 0b010..divide by 3 + * 0b011..divide by 4 + * 0b100..divide by 5 + * 0b101..divide by 6 + * 0b110..divide by 7 + * 0b111..divide by 8 + */ #define CCM_CCOSR_CLKO1_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLKO1_DIV_SHIFT)) & CCM_CCOSR_CLKO1_DIV_MASK) #define CCM_CCOSR_CLKO1_EN_MASK (0x80U) #define CCM_CCOSR_CLKO1_EN_SHIFT (7U) +/*! CLKO1_EN + * 0b0..CCM_CLKO1 disabled. + * 0b1..CCM_CLKO1 enabled. + */ #define CCM_CCOSR_CLKO1_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLKO1_EN_SHIFT)) & CCM_CCOSR_CLKO1_EN_MASK) #define CCM_CCOSR_CLK_OUT_SEL_MASK (0x100U) #define CCM_CCOSR_CLK_OUT_SEL_SHIFT (8U) +/*! CLK_OUT_SEL + * 0b0..CCM_CLKO1 output drives CCM_CLKO1 clock + * 0b1..CCM_CLKO1 output drives CCM_CLKO2 clock + */ #define CCM_CCOSR_CLK_OUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLK_OUT_SEL_SHIFT)) & CCM_CCOSR_CLK_OUT_SEL_MASK) #define CCM_CCOSR_CLKO2_SEL_MASK (0x1F0000U) #define CCM_CCOSR_CLKO2_SEL_SHIFT (16U) +/*! CLKO2_SEL + * 0b00011..usdhc1_clk_root + * 0b00101..wrck_clk_root + * 0b00110..lpi2c_clk_root + * 0b01011..csi_clk_root + * 0b01110..osc_clk + * 0b10001..usdhc2_clk_root + * 0b10010..sai1_clk_root + * 0b10011..sai2_clk_root + * 0b10100..sai3_clk_root + * 0b10111..can_clk_root + * 0b11011..flexspi_clk_root + * 0b11100..uart_clk_root + * 0b11101..spdif0_clk_root + * 0b11111..Reserved + */ #define CCM_CCOSR_CLKO2_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLKO2_SEL_SHIFT)) & CCM_CCOSR_CLKO2_SEL_MASK) #define CCM_CCOSR_CLKO2_DIV_MASK (0xE00000U) #define CCM_CCOSR_CLKO2_DIV_SHIFT (21U) +/*! CLKO2_DIV + * 0b000..divide by 1 + * 0b001..divide by 2 + * 0b010..divide by 3 + * 0b011..divide by 4 + * 0b100..divide by 5 + * 0b101..divide by 6 + * 0b110..divide by 7 + * 0b111..divide by 8 + */ #define CCM_CCOSR_CLKO2_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLKO2_DIV_SHIFT)) & CCM_CCOSR_CLKO2_DIV_MASK) #define CCM_CCOSR_CLKO2_EN_MASK (0x1000000U) #define CCM_CCOSR_CLKO2_EN_SHIFT (24U) +/*! CLKO2_EN + * 0b0..CCM_CLKO2 disabled. + * 0b1..CCM_CLKO2 enabled. + */ #define CCM_CCOSR_CLKO2_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLKO2_EN_SHIFT)) & CCM_CCOSR_CLKO2_EN_MASK) +/*! @} */ /*! @name CGPR - CCM General Purpose Register */ +/*! @{ */ #define CCM_CGPR_PMIC_DELAY_SCALER_MASK (0x1U) #define CCM_CGPR_PMIC_DELAY_SCALER_SHIFT (0U) +/*! PMIC_DELAY_SCALER + * 0b0..clock is not divided + * 0b1..clock is divided /8 + */ #define CCM_CGPR_PMIC_DELAY_SCALER(x) (((uint32_t)(((uint32_t)(x)) << CCM_CGPR_PMIC_DELAY_SCALER_SHIFT)) & CCM_CGPR_PMIC_DELAY_SCALER_MASK) #define CCM_CGPR_EFUSE_PROG_SUPPLY_GATE_MASK (0x10U) #define CCM_CGPR_EFUSE_PROG_SUPPLY_GATE_SHIFT (4U) +/*! EFUSE_PROG_SUPPLY_GATE + * 0b0..fuse programing supply voltage is gated off to the efuse module + * 0b1..allow fuse programing. + */ #define CCM_CGPR_EFUSE_PROG_SUPPLY_GATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CGPR_EFUSE_PROG_SUPPLY_GATE_SHIFT)) & CCM_CGPR_EFUSE_PROG_SUPPLY_GATE_MASK) #define CCM_CGPR_SYS_MEM_DS_CTRL_MASK (0xC000U) #define CCM_CGPR_SYS_MEM_DS_CTRL_SHIFT (14U) +/*! SYS_MEM_DS_CTRL + * 0b00..Disable memory DS mode always + * 0b01..Enable memory (outside ARM platform) DS mode when system STOP and PLL are disabled + * 0b1x..enable memory (outside ARM platform) DS mode when system is in STOP mode + */ #define CCM_CGPR_SYS_MEM_DS_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CGPR_SYS_MEM_DS_CTRL_SHIFT)) & CCM_CGPR_SYS_MEM_DS_CTRL_MASK) #define CCM_CGPR_FPL_MASK (0x10000U) #define CCM_CGPR_FPL_SHIFT (16U) +/*! FPL - Fast PLL enable. + * 0b0..Engage PLL enable default way. + * 0b1..Engage PLL enable 3 CKIL clocks earlier at exiting low power mode (STOP). Should be used only if 24MHz OSC was active in low power mode. + */ #define CCM_CGPR_FPL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CGPR_FPL_SHIFT)) & CCM_CGPR_FPL_MASK) #define CCM_CGPR_INT_MEM_CLK_LPM_MASK (0x20000U) #define CCM_CGPR_INT_MEM_CLK_LPM_SHIFT (17U) +/*! INT_MEM_CLK_LPM + * 0b0..Disable the clock to the ARM platform memories when entering Low Power Mode + * 0b1..Keep the clocks to the ARM platform memories enabled only if an interrupt is pending when entering Low Power Modes (WAIT and STOP without power gating) + */ #define CCM_CGPR_INT_MEM_CLK_LPM(x) (((uint32_t)(((uint32_t)(x)) << CCM_CGPR_INT_MEM_CLK_LPM_SHIFT)) & CCM_CGPR_INT_MEM_CLK_LPM_MASK) +/*! @} */ /*! @name CCGR0 - CCM Clock Gating Register 0 */ +/*! @{ */ #define CCM_CCGR0_CG0_MASK (0x3U) #define CCM_CCGR0_CG0_SHIFT (0U) #define CCM_CCGR0_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG0_SHIFT)) & CCM_CCGR0_CG0_MASK) @@ -3338,8 +4957,10 @@ typedef struct { #define CCM_CCGR0_CG15_MASK (0xC0000000U) #define CCM_CCGR0_CG15_SHIFT (30U) #define CCM_CCGR0_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG15_SHIFT)) & CCM_CCGR0_CG15_MASK) +/*! @} */ /*! @name CCGR1 - CCM Clock Gating Register 1 */ +/*! @{ */ #define CCM_CCGR1_CG0_MASK (0x3U) #define CCM_CCGR1_CG0_SHIFT (0U) #define CCM_CCGR1_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG0_SHIFT)) & CCM_CCGR1_CG0_MASK) @@ -3388,8 +5009,10 @@ typedef struct { #define CCM_CCGR1_CG15_MASK (0xC0000000U) #define CCM_CCGR1_CG15_SHIFT (30U) #define CCM_CCGR1_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG15_SHIFT)) & CCM_CCGR1_CG15_MASK) +/*! @} */ /*! @name CCGR2 - CCM Clock Gating Register 2 */ +/*! @{ */ #define CCM_CCGR2_CG0_MASK (0x3U) #define CCM_CCGR2_CG0_SHIFT (0U) #define CCM_CCGR2_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG0_SHIFT)) & CCM_CCGR2_CG0_MASK) @@ -3438,8 +5061,10 @@ typedef struct { #define CCM_CCGR2_CG15_MASK (0xC0000000U) #define CCM_CCGR2_CG15_SHIFT (30U) #define CCM_CCGR2_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG15_SHIFT)) & CCM_CCGR2_CG15_MASK) +/*! @} */ /*! @name CCGR3 - CCM Clock Gating Register 3 */ +/*! @{ */ #define CCM_CCGR3_CG0_MASK (0x3U) #define CCM_CCGR3_CG0_SHIFT (0U) #define CCM_CCGR3_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG0_SHIFT)) & CCM_CCGR3_CG0_MASK) @@ -3488,8 +5113,10 @@ typedef struct { #define CCM_CCGR3_CG15_MASK (0xC0000000U) #define CCM_CCGR3_CG15_SHIFT (30U) #define CCM_CCGR3_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG15_SHIFT)) & CCM_CCGR3_CG15_MASK) +/*! @} */ /*! @name CCGR4 - CCM Clock Gating Register 4 */ +/*! @{ */ #define CCM_CCGR4_CG0_MASK (0x3U) #define CCM_CCGR4_CG0_SHIFT (0U) #define CCM_CCGR4_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG0_SHIFT)) & CCM_CCGR4_CG0_MASK) @@ -3538,8 +5165,10 @@ typedef struct { #define CCM_CCGR4_CG15_MASK (0xC0000000U) #define CCM_CCGR4_CG15_SHIFT (30U) #define CCM_CCGR4_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG15_SHIFT)) & CCM_CCGR4_CG15_MASK) +/*! @} */ /*! @name CCGR5 - CCM Clock Gating Register 5 */ +/*! @{ */ #define CCM_CCGR5_CG0_MASK (0x3U) #define CCM_CCGR5_CG0_SHIFT (0U) #define CCM_CCGR5_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG0_SHIFT)) & CCM_CCGR5_CG0_MASK) @@ -3588,8 +5217,10 @@ typedef struct { #define CCM_CCGR5_CG15_MASK (0xC0000000U) #define CCM_CCGR5_CG15_SHIFT (30U) #define CCM_CCGR5_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG15_SHIFT)) & CCM_CCGR5_CG15_MASK) +/*! @} */ /*! @name CCGR6 - CCM Clock Gating Register 6 */ +/*! @{ */ #define CCM_CCGR6_CG0_MASK (0x3U) #define CCM_CCGR6_CG0_SHIFT (0U) #define CCM_CCGR6_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG0_SHIFT)) & CCM_CCGR6_CG0_MASK) @@ -3638,26 +5269,53 @@ typedef struct { #define CCM_CCGR6_CG15_MASK (0xC0000000U) #define CCM_CCGR6_CG15_SHIFT (30U) #define CCM_CCGR6_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG15_SHIFT)) & CCM_CCGR6_CG15_MASK) +/*! @} */ /*! @name CMEOR - CCM Module Enable Overide Register */ +/*! @{ */ #define CCM_CMEOR_MOD_EN_OV_GPT_MASK (0x20U) #define CCM_CMEOR_MOD_EN_OV_GPT_SHIFT (5U) +/*! MOD_EN_OV_GPT + * 0b0..don't override module enable signal + * 0b1..override module enable signal + */ #define CCM_CMEOR_MOD_EN_OV_GPT(x) (((uint32_t)(((uint32_t)(x)) << CCM_CMEOR_MOD_EN_OV_GPT_SHIFT)) & CCM_CMEOR_MOD_EN_OV_GPT_MASK) #define CCM_CMEOR_MOD_EN_OV_PIT_MASK (0x40U) #define CCM_CMEOR_MOD_EN_OV_PIT_SHIFT (6U) +/*! MOD_EN_OV_PIT + * 0b0..don't override module enable signal + * 0b1..override module enable signal + */ #define CCM_CMEOR_MOD_EN_OV_PIT(x) (((uint32_t)(((uint32_t)(x)) << CCM_CMEOR_MOD_EN_OV_PIT_SHIFT)) & CCM_CMEOR_MOD_EN_OV_PIT_MASK) #define CCM_CMEOR_MOD_EN_USDHC_MASK (0x80U) #define CCM_CMEOR_MOD_EN_USDHC_SHIFT (7U) +/*! MOD_EN_USDHC + * 0b0..don't override module enable signal + * 0b1..override module enable signal + */ #define CCM_CMEOR_MOD_EN_USDHC(x) (((uint32_t)(((uint32_t)(x)) << CCM_CMEOR_MOD_EN_USDHC_SHIFT)) & CCM_CMEOR_MOD_EN_USDHC_MASK) #define CCM_CMEOR_MOD_EN_OV_TRNG_MASK (0x200U) #define CCM_CMEOR_MOD_EN_OV_TRNG_SHIFT (9U) +/*! MOD_EN_OV_TRNG + * 0b0..don't override module enable signal + * 0b1..override module enable signal + */ #define CCM_CMEOR_MOD_EN_OV_TRNG(x) (((uint32_t)(((uint32_t)(x)) << CCM_CMEOR_MOD_EN_OV_TRNG_SHIFT)) & CCM_CMEOR_MOD_EN_OV_TRNG_MASK) #define CCM_CMEOR_MOD_EN_OV_CAN2_CPI_MASK (0x10000000U) #define CCM_CMEOR_MOD_EN_OV_CAN2_CPI_SHIFT (28U) +/*! MOD_EN_OV_CAN2_CPI + * 0b0..don't override module enable signal + * 0b1..override module enable signal + */ #define CCM_CMEOR_MOD_EN_OV_CAN2_CPI(x) (((uint32_t)(((uint32_t)(x)) << CCM_CMEOR_MOD_EN_OV_CAN2_CPI_SHIFT)) & CCM_CMEOR_MOD_EN_OV_CAN2_CPI_MASK) #define CCM_CMEOR_MOD_EN_OV_CAN1_CPI_MASK (0x40000000U) #define CCM_CMEOR_MOD_EN_OV_CAN1_CPI_SHIFT (30U) +/*! MOD_EN_OV_CAN1_CPI + * 0b0..don't overide module enable signal + * 0b1..overide module enable signal + */ #define CCM_CMEOR_MOD_EN_OV_CAN1_CPI(x) (((uint32_t)(((uint32_t)(x)) << CCM_CMEOR_MOD_EN_OV_CAN1_CPI_SHIFT)) & CCM_CMEOR_MOD_EN_OV_CAN1_CPI_MASK) +/*! @} */ /*! @@ -3768,6 +5426,7 @@ typedef struct { */ /*! @name PLL_ARM - Analog ARM PLL control Register */ +/*! @{ */ #define CCM_ANALOG_PLL_ARM_DIV_SELECT_MASK (0x7FU) #define CCM_ANALOG_PLL_ARM_DIV_SELECT_SHIFT (0U) #define CCM_ANALOG_PLL_ARM_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ARM_DIV_SELECT_MASK) @@ -3779,6 +5438,12 @@ typedef struct { #define CCM_ANALOG_PLL_ARM_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_ENABLE_SHIFT)) & CCM_ANALOG_PLL_ARM_ENABLE_MASK) #define CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_MASK (0xC000U) #define CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_SHIFT (14U) +/*! BYPASS_CLK_SRC + * 0b00..Select the 24MHz oscillator as source. + * 0b01..Select the CLK1_N / CLK1_P as source. + * 0b10..Reserved1 + * 0b11..Reserved2 + */ #define CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_MASK) #define CCM_ANALOG_PLL_ARM_BYPASS_MASK (0x10000U) #define CCM_ANALOG_PLL_ARM_BYPASS_SHIFT (16U) @@ -3789,8 +5454,10 @@ typedef struct { #define CCM_ANALOG_PLL_ARM_LOCK_MASK (0x80000000U) #define CCM_ANALOG_PLL_ARM_LOCK_SHIFT (31U) #define CCM_ANALOG_PLL_ARM_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_LOCK_SHIFT)) & CCM_ANALOG_PLL_ARM_LOCK_MASK) +/*! @} */ /*! @name PLL_ARM_SET - Analog ARM PLL control Register */ +/*! @{ */ #define CCM_ANALOG_PLL_ARM_SET_DIV_SELECT_MASK (0x7FU) #define CCM_ANALOG_PLL_ARM_SET_DIV_SELECT_SHIFT (0U) #define CCM_ANALOG_PLL_ARM_SET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_SET_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ARM_SET_DIV_SELECT_MASK) @@ -3802,6 +5469,12 @@ typedef struct { #define CCM_ANALOG_PLL_ARM_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_SET_ENABLE_SHIFT)) & CCM_ANALOG_PLL_ARM_SET_ENABLE_MASK) #define CCM_ANALOG_PLL_ARM_SET_BYPASS_CLK_SRC_MASK (0xC000U) #define CCM_ANALOG_PLL_ARM_SET_BYPASS_CLK_SRC_SHIFT (14U) +/*! BYPASS_CLK_SRC + * 0b00..Select the 24MHz oscillator as source. + * 0b01..Select the CLK1_N / CLK1_P as source. + * 0b10..Reserved1 + * 0b11..Reserved2 + */ #define CCM_ANALOG_PLL_ARM_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_SET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ARM_SET_BYPASS_CLK_SRC_MASK) #define CCM_ANALOG_PLL_ARM_SET_BYPASS_MASK (0x10000U) #define CCM_ANALOG_PLL_ARM_SET_BYPASS_SHIFT (16U) @@ -3812,8 +5485,10 @@ typedef struct { #define CCM_ANALOG_PLL_ARM_SET_LOCK_MASK (0x80000000U) #define CCM_ANALOG_PLL_ARM_SET_LOCK_SHIFT (31U) #define CCM_ANALOG_PLL_ARM_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_SET_LOCK_SHIFT)) & CCM_ANALOG_PLL_ARM_SET_LOCK_MASK) +/*! @} */ /*! @name PLL_ARM_CLR - Analog ARM PLL control Register */ +/*! @{ */ #define CCM_ANALOG_PLL_ARM_CLR_DIV_SELECT_MASK (0x7FU) #define CCM_ANALOG_PLL_ARM_CLR_DIV_SELECT_SHIFT (0U) #define CCM_ANALOG_PLL_ARM_CLR_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_CLR_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ARM_CLR_DIV_SELECT_MASK) @@ -3825,6 +5500,12 @@ typedef struct { #define CCM_ANALOG_PLL_ARM_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_CLR_ENABLE_SHIFT)) & CCM_ANALOG_PLL_ARM_CLR_ENABLE_MASK) #define CCM_ANALOG_PLL_ARM_CLR_BYPASS_CLK_SRC_MASK (0xC000U) #define CCM_ANALOG_PLL_ARM_CLR_BYPASS_CLK_SRC_SHIFT (14U) +/*! BYPASS_CLK_SRC + * 0b00..Select the 24MHz oscillator as source. + * 0b01..Select the CLK1_N / CLK1_P as source. + * 0b10..Reserved1 + * 0b11..Reserved2 + */ #define CCM_ANALOG_PLL_ARM_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_CLR_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ARM_CLR_BYPASS_CLK_SRC_MASK) #define CCM_ANALOG_PLL_ARM_CLR_BYPASS_MASK (0x10000U) #define CCM_ANALOG_PLL_ARM_CLR_BYPASS_SHIFT (16U) @@ -3835,8 +5516,10 @@ typedef struct { #define CCM_ANALOG_PLL_ARM_CLR_LOCK_MASK (0x80000000U) #define CCM_ANALOG_PLL_ARM_CLR_LOCK_SHIFT (31U) #define CCM_ANALOG_PLL_ARM_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_CLR_LOCK_SHIFT)) & CCM_ANALOG_PLL_ARM_CLR_LOCK_MASK) +/*! @} */ /*! @name PLL_ARM_TOG - Analog ARM PLL control Register */ +/*! @{ */ #define CCM_ANALOG_PLL_ARM_TOG_DIV_SELECT_MASK (0x7FU) #define CCM_ANALOG_PLL_ARM_TOG_DIV_SELECT_SHIFT (0U) #define CCM_ANALOG_PLL_ARM_TOG_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_TOG_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ARM_TOG_DIV_SELECT_MASK) @@ -3848,6 +5531,12 @@ typedef struct { #define CCM_ANALOG_PLL_ARM_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_TOG_ENABLE_SHIFT)) & CCM_ANALOG_PLL_ARM_TOG_ENABLE_MASK) #define CCM_ANALOG_PLL_ARM_TOG_BYPASS_CLK_SRC_MASK (0xC000U) #define CCM_ANALOG_PLL_ARM_TOG_BYPASS_CLK_SRC_SHIFT (14U) +/*! BYPASS_CLK_SRC + * 0b00..Select the 24MHz oscillator as source. + * 0b01..Select the CLK1_N / CLK1_P as source. + * 0b10..Reserved1 + * 0b11..Reserved2 + */ #define CCM_ANALOG_PLL_ARM_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_TOG_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ARM_TOG_BYPASS_CLK_SRC_MASK) #define CCM_ANALOG_PLL_ARM_TOG_BYPASS_MASK (0x10000U) #define CCM_ANALOG_PLL_ARM_TOG_BYPASS_SHIFT (16U) @@ -3858,13 +5547,19 @@ typedef struct { #define CCM_ANALOG_PLL_ARM_TOG_LOCK_MASK (0x80000000U) #define CCM_ANALOG_PLL_ARM_TOG_LOCK_SHIFT (31U) #define CCM_ANALOG_PLL_ARM_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_TOG_LOCK_SHIFT)) & CCM_ANALOG_PLL_ARM_TOG_LOCK_MASK) +/*! @} */ /*! @name PLL_USB1 - Analog USB1 480MHz PLL Control Register */ -#define CCM_ANALOG_PLL_USB1_DIV_SELECT_MASK (0x3U) -#define CCM_ANALOG_PLL_USB1_DIV_SELECT_SHIFT (0U) +/*! @{ */ +#define CCM_ANALOG_PLL_USB1_DIV_SELECT_MASK (0x2U) +#define CCM_ANALOG_PLL_USB1_DIV_SELECT_SHIFT (1U) #define CCM_ANALOG_PLL_USB1_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB1_DIV_SELECT_MASK) #define CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK (0x40U) #define CCM_ANALOG_PLL_USB1_EN_USB_CLKS_SHIFT (6U) +/*! EN_USB_CLKS + * 0b0..PLL outputs for USBPHYn off. + * 0b1..PLL outputs for USBPHYn on. + */ #define CCM_ANALOG_PLL_USB1_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_EN_USB_CLKS_SHIFT)) & CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK) #define CCM_ANALOG_PLL_USB1_POWER_MASK (0x1000U) #define CCM_ANALOG_PLL_USB1_POWER_SHIFT (12U) @@ -3874,6 +5569,10 @@ typedef struct { #define CCM_ANALOG_PLL_USB1_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB1_ENABLE_MASK) #define CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_MASK (0xC000U) #define CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_SHIFT (14U) +/*! BYPASS_CLK_SRC + * 0b00..Select the 24MHz oscillator as source. + * 0b01..Select the CLK1_N / CLK1_P as source. + */ #define CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_MASK) #define CCM_ANALOG_PLL_USB1_BYPASS_MASK (0x10000U) #define CCM_ANALOG_PLL_USB1_BYPASS_SHIFT (16U) @@ -3881,13 +5580,19 @@ typedef struct { #define CCM_ANALOG_PLL_USB1_LOCK_MASK (0x80000000U) #define CCM_ANALOG_PLL_USB1_LOCK_SHIFT (31U) #define CCM_ANALOG_PLL_USB1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB1_LOCK_MASK) +/*! @} */ /*! @name PLL_USB1_SET - Analog USB1 480MHz PLL Control Register */ -#define CCM_ANALOG_PLL_USB1_SET_DIV_SELECT_MASK (0x3U) -#define CCM_ANALOG_PLL_USB1_SET_DIV_SELECT_SHIFT (0U) +/*! @{ */ +#define CCM_ANALOG_PLL_USB1_SET_DIV_SELECT_MASK (0x2U) +#define CCM_ANALOG_PLL_USB1_SET_DIV_SELECT_SHIFT (1U) #define CCM_ANALOG_PLL_USB1_SET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_DIV_SELECT_MASK) #define CCM_ANALOG_PLL_USB1_SET_EN_USB_CLKS_MASK (0x40U) #define CCM_ANALOG_PLL_USB1_SET_EN_USB_CLKS_SHIFT (6U) +/*! EN_USB_CLKS + * 0b0..PLL outputs for USBPHYn off. + * 0b1..PLL outputs for USBPHYn on. + */ #define CCM_ANALOG_PLL_USB1_SET_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_EN_USB_CLKS_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_EN_USB_CLKS_MASK) #define CCM_ANALOG_PLL_USB1_SET_POWER_MASK (0x1000U) #define CCM_ANALOG_PLL_USB1_SET_POWER_SHIFT (12U) @@ -3897,6 +5602,10 @@ typedef struct { #define CCM_ANALOG_PLL_USB1_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_ENABLE_MASK) #define CCM_ANALOG_PLL_USB1_SET_BYPASS_CLK_SRC_MASK (0xC000U) #define CCM_ANALOG_PLL_USB1_SET_BYPASS_CLK_SRC_SHIFT (14U) +/*! BYPASS_CLK_SRC + * 0b00..Select the 24MHz oscillator as source. + * 0b01..Select the CLK1_N / CLK1_P as source. + */ #define CCM_ANALOG_PLL_USB1_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_BYPASS_CLK_SRC_MASK) #define CCM_ANALOG_PLL_USB1_SET_BYPASS_MASK (0x10000U) #define CCM_ANALOG_PLL_USB1_SET_BYPASS_SHIFT (16U) @@ -3904,13 +5613,19 @@ typedef struct { #define CCM_ANALOG_PLL_USB1_SET_LOCK_MASK (0x80000000U) #define CCM_ANALOG_PLL_USB1_SET_LOCK_SHIFT (31U) #define CCM_ANALOG_PLL_USB1_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_LOCK_MASK) +/*! @} */ /*! @name PLL_USB1_CLR - Analog USB1 480MHz PLL Control Register */ -#define CCM_ANALOG_PLL_USB1_CLR_DIV_SELECT_MASK (0x3U) -#define CCM_ANALOG_PLL_USB1_CLR_DIV_SELECT_SHIFT (0U) +/*! @{ */ +#define CCM_ANALOG_PLL_USB1_CLR_DIV_SELECT_MASK (0x2U) +#define CCM_ANALOG_PLL_USB1_CLR_DIV_SELECT_SHIFT (1U) #define CCM_ANALOG_PLL_USB1_CLR_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_DIV_SELECT_MASK) #define CCM_ANALOG_PLL_USB1_CLR_EN_USB_CLKS_MASK (0x40U) #define CCM_ANALOG_PLL_USB1_CLR_EN_USB_CLKS_SHIFT (6U) +/*! EN_USB_CLKS + * 0b0..PLL outputs for USBPHYn off. + * 0b1..PLL outputs for USBPHYn on. + */ #define CCM_ANALOG_PLL_USB1_CLR_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_EN_USB_CLKS_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_EN_USB_CLKS_MASK) #define CCM_ANALOG_PLL_USB1_CLR_POWER_MASK (0x1000U) #define CCM_ANALOG_PLL_USB1_CLR_POWER_SHIFT (12U) @@ -3920,6 +5635,10 @@ typedef struct { #define CCM_ANALOG_PLL_USB1_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_ENABLE_MASK) #define CCM_ANALOG_PLL_USB1_CLR_BYPASS_CLK_SRC_MASK (0xC000U) #define CCM_ANALOG_PLL_USB1_CLR_BYPASS_CLK_SRC_SHIFT (14U) +/*! BYPASS_CLK_SRC + * 0b00..Select the 24MHz oscillator as source. + * 0b01..Select the CLK1_N / CLK1_P as source. + */ #define CCM_ANALOG_PLL_USB1_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_BYPASS_CLK_SRC_MASK) #define CCM_ANALOG_PLL_USB1_CLR_BYPASS_MASK (0x10000U) #define CCM_ANALOG_PLL_USB1_CLR_BYPASS_SHIFT (16U) @@ -3927,13 +5646,19 @@ typedef struct { #define CCM_ANALOG_PLL_USB1_CLR_LOCK_MASK (0x80000000U) #define CCM_ANALOG_PLL_USB1_CLR_LOCK_SHIFT (31U) #define CCM_ANALOG_PLL_USB1_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_LOCK_MASK) +/*! @} */ /*! @name PLL_USB1_TOG - Analog USB1 480MHz PLL Control Register */ -#define CCM_ANALOG_PLL_USB1_TOG_DIV_SELECT_MASK (0x3U) -#define CCM_ANALOG_PLL_USB1_TOG_DIV_SELECT_SHIFT (0U) +/*! @{ */ +#define CCM_ANALOG_PLL_USB1_TOG_DIV_SELECT_MASK (0x2U) +#define CCM_ANALOG_PLL_USB1_TOG_DIV_SELECT_SHIFT (1U) #define CCM_ANALOG_PLL_USB1_TOG_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_DIV_SELECT_MASK) #define CCM_ANALOG_PLL_USB1_TOG_EN_USB_CLKS_MASK (0x40U) #define CCM_ANALOG_PLL_USB1_TOG_EN_USB_CLKS_SHIFT (6U) +/*! EN_USB_CLKS + * 0b0..PLL outputs for USBPHYn off. + * 0b1..PLL outputs for USBPHYn on. + */ #define CCM_ANALOG_PLL_USB1_TOG_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_EN_USB_CLKS_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_EN_USB_CLKS_MASK) #define CCM_ANALOG_PLL_USB1_TOG_POWER_MASK (0x1000U) #define CCM_ANALOG_PLL_USB1_TOG_POWER_SHIFT (12U) @@ -3943,6 +5668,10 @@ typedef struct { #define CCM_ANALOG_PLL_USB1_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_ENABLE_MASK) #define CCM_ANALOG_PLL_USB1_TOG_BYPASS_CLK_SRC_MASK (0xC000U) #define CCM_ANALOG_PLL_USB1_TOG_BYPASS_CLK_SRC_SHIFT (14U) +/*! BYPASS_CLK_SRC + * 0b00..Select the 24MHz oscillator as source. + * 0b01..Select the CLK1_N / CLK1_P as source. + */ #define CCM_ANALOG_PLL_USB1_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_BYPASS_CLK_SRC_MASK) #define CCM_ANALOG_PLL_USB1_TOG_BYPASS_MASK (0x10000U) #define CCM_ANALOG_PLL_USB1_TOG_BYPASS_SHIFT (16U) @@ -3950,10 +5679,12 @@ typedef struct { #define CCM_ANALOG_PLL_USB1_TOG_LOCK_MASK (0x80000000U) #define CCM_ANALOG_PLL_USB1_TOG_LOCK_SHIFT (31U) #define CCM_ANALOG_PLL_USB1_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_LOCK_MASK) +/*! @} */ /*! @name PLL_USB2 - Analog USB2 480MHz PLL Control Register */ -#define CCM_ANALOG_PLL_USB2_DIV_SELECT_MASK (0x3U) -#define CCM_ANALOG_PLL_USB2_DIV_SELECT_SHIFT (0U) +/*! @{ */ +#define CCM_ANALOG_PLL_USB2_DIV_SELECT_MASK (0x2U) +#define CCM_ANALOG_PLL_USB2_DIV_SELECT_SHIFT (1U) #define CCM_ANALOG_PLL_USB2_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB2_DIV_SELECT_MASK) #define CCM_ANALOG_PLL_USB2_EN_USB_CLKS_MASK (0x40U) #define CCM_ANALOG_PLL_USB2_EN_USB_CLKS_SHIFT (6U) @@ -3966,6 +5697,12 @@ typedef struct { #define CCM_ANALOG_PLL_USB2_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB2_ENABLE_MASK) #define CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC_MASK (0xC000U) #define CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC_SHIFT (14U) +/*! BYPASS_CLK_SRC + * 0b00..Select the 24MHz oscillator as source. + * 0b01..Select the CLK1_N / CLK1_P as source. + * 0b10..Reserved1 + * 0b11..Reserved2 + */ #define CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC_MASK) #define CCM_ANALOG_PLL_USB2_BYPASS_MASK (0x10000U) #define CCM_ANALOG_PLL_USB2_BYPASS_SHIFT (16U) @@ -3973,10 +5710,12 @@ typedef struct { #define CCM_ANALOG_PLL_USB2_LOCK_MASK (0x80000000U) #define CCM_ANALOG_PLL_USB2_LOCK_SHIFT (31U) #define CCM_ANALOG_PLL_USB2_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB2_LOCK_MASK) +/*! @} */ /*! @name PLL_USB2_SET - Analog USB2 480MHz PLL Control Register */ -#define CCM_ANALOG_PLL_USB2_SET_DIV_SELECT_MASK (0x3U) -#define CCM_ANALOG_PLL_USB2_SET_DIV_SELECT_SHIFT (0U) +/*! @{ */ +#define CCM_ANALOG_PLL_USB2_SET_DIV_SELECT_MASK (0x2U) +#define CCM_ANALOG_PLL_USB2_SET_DIV_SELECT_SHIFT (1U) #define CCM_ANALOG_PLL_USB2_SET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_SET_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB2_SET_DIV_SELECT_MASK) #define CCM_ANALOG_PLL_USB2_SET_EN_USB_CLKS_MASK (0x40U) #define CCM_ANALOG_PLL_USB2_SET_EN_USB_CLKS_SHIFT (6U) @@ -3989,6 +5728,12 @@ typedef struct { #define CCM_ANALOG_PLL_USB2_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_SET_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB2_SET_ENABLE_MASK) #define CCM_ANALOG_PLL_USB2_SET_BYPASS_CLK_SRC_MASK (0xC000U) #define CCM_ANALOG_PLL_USB2_SET_BYPASS_CLK_SRC_SHIFT (14U) +/*! BYPASS_CLK_SRC + * 0b00..Select the 24MHz oscillator as source. + * 0b01..Select the CLK1_N / CLK1_P as source. + * 0b10..Reserved1 + * 0b11..Reserved2 + */ #define CCM_ANALOG_PLL_USB2_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_SET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB2_SET_BYPASS_CLK_SRC_MASK) #define CCM_ANALOG_PLL_USB2_SET_BYPASS_MASK (0x10000U) #define CCM_ANALOG_PLL_USB2_SET_BYPASS_SHIFT (16U) @@ -3996,10 +5741,12 @@ typedef struct { #define CCM_ANALOG_PLL_USB2_SET_LOCK_MASK (0x80000000U) #define CCM_ANALOG_PLL_USB2_SET_LOCK_SHIFT (31U) #define CCM_ANALOG_PLL_USB2_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_SET_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB2_SET_LOCK_MASK) +/*! @} */ /*! @name PLL_USB2_CLR - Analog USB2 480MHz PLL Control Register */ -#define CCM_ANALOG_PLL_USB2_CLR_DIV_SELECT_MASK (0x3U) -#define CCM_ANALOG_PLL_USB2_CLR_DIV_SELECT_SHIFT (0U) +/*! @{ */ +#define CCM_ANALOG_PLL_USB2_CLR_DIV_SELECT_MASK (0x2U) +#define CCM_ANALOG_PLL_USB2_CLR_DIV_SELECT_SHIFT (1U) #define CCM_ANALOG_PLL_USB2_CLR_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_CLR_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB2_CLR_DIV_SELECT_MASK) #define CCM_ANALOG_PLL_USB2_CLR_EN_USB_CLKS_MASK (0x40U) #define CCM_ANALOG_PLL_USB2_CLR_EN_USB_CLKS_SHIFT (6U) @@ -4012,6 +5759,12 @@ typedef struct { #define CCM_ANALOG_PLL_USB2_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_CLR_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB2_CLR_ENABLE_MASK) #define CCM_ANALOG_PLL_USB2_CLR_BYPASS_CLK_SRC_MASK (0xC000U) #define CCM_ANALOG_PLL_USB2_CLR_BYPASS_CLK_SRC_SHIFT (14U) +/*! BYPASS_CLK_SRC + * 0b00..Select the 24MHz oscillator as source. + * 0b01..Select the CLK1_N / CLK1_P as source. + * 0b10..Reserved1 + * 0b11..Reserved2 + */ #define CCM_ANALOG_PLL_USB2_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_CLR_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB2_CLR_BYPASS_CLK_SRC_MASK) #define CCM_ANALOG_PLL_USB2_CLR_BYPASS_MASK (0x10000U) #define CCM_ANALOG_PLL_USB2_CLR_BYPASS_SHIFT (16U) @@ -4019,10 +5772,12 @@ typedef struct { #define CCM_ANALOG_PLL_USB2_CLR_LOCK_MASK (0x80000000U) #define CCM_ANALOG_PLL_USB2_CLR_LOCK_SHIFT (31U) #define CCM_ANALOG_PLL_USB2_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_CLR_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB2_CLR_LOCK_MASK) +/*! @} */ /*! @name PLL_USB2_TOG - Analog USB2 480MHz PLL Control Register */ -#define CCM_ANALOG_PLL_USB2_TOG_DIV_SELECT_MASK (0x3U) -#define CCM_ANALOG_PLL_USB2_TOG_DIV_SELECT_SHIFT (0U) +/*! @{ */ +#define CCM_ANALOG_PLL_USB2_TOG_DIV_SELECT_MASK (0x2U) +#define CCM_ANALOG_PLL_USB2_TOG_DIV_SELECT_SHIFT (1U) #define CCM_ANALOG_PLL_USB2_TOG_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_TOG_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB2_TOG_DIV_SELECT_MASK) #define CCM_ANALOG_PLL_USB2_TOG_EN_USB_CLKS_MASK (0x40U) #define CCM_ANALOG_PLL_USB2_TOG_EN_USB_CLKS_SHIFT (6U) @@ -4035,6 +5790,12 @@ typedef struct { #define CCM_ANALOG_PLL_USB2_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_TOG_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB2_TOG_ENABLE_MASK) #define CCM_ANALOG_PLL_USB2_TOG_BYPASS_CLK_SRC_MASK (0xC000U) #define CCM_ANALOG_PLL_USB2_TOG_BYPASS_CLK_SRC_SHIFT (14U) +/*! BYPASS_CLK_SRC + * 0b00..Select the 24MHz oscillator as source. + * 0b01..Select the CLK1_N / CLK1_P as source. + * 0b10..Reserved1 + * 0b11..Reserved2 + */ #define CCM_ANALOG_PLL_USB2_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_TOG_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB2_TOG_BYPASS_CLK_SRC_MASK) #define CCM_ANALOG_PLL_USB2_TOG_BYPASS_MASK (0x10000U) #define CCM_ANALOG_PLL_USB2_TOG_BYPASS_SHIFT (16U) @@ -4042,8 +5803,10 @@ typedef struct { #define CCM_ANALOG_PLL_USB2_TOG_LOCK_MASK (0x80000000U) #define CCM_ANALOG_PLL_USB2_TOG_LOCK_SHIFT (31U) #define CCM_ANALOG_PLL_USB2_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_TOG_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB2_TOG_LOCK_MASK) +/*! @} */ /*! @name PLL_SYS - Analog System PLL Control Register */ +/*! @{ */ #define CCM_ANALOG_PLL_SYS_DIV_SELECT_MASK (0x1U) #define CCM_ANALOG_PLL_SYS_DIV_SELECT_SHIFT (0U) #define CCM_ANALOG_PLL_SYS_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_SYS_DIV_SELECT_MASK) @@ -4055,6 +5818,10 @@ typedef struct { #define CCM_ANALOG_PLL_SYS_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_ENABLE_SHIFT)) & CCM_ANALOG_PLL_SYS_ENABLE_MASK) #define CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_MASK (0xC000U) #define CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_SHIFT (14U) +/*! BYPASS_CLK_SRC + * 0b00..Select the 24MHz oscillator as source. + * 0b01..Select the CLK1_N / CLK1_P as source. + */ #define CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_MASK) #define CCM_ANALOG_PLL_SYS_BYPASS_MASK (0x10000U) #define CCM_ANALOG_PLL_SYS_BYPASS_SHIFT (16U) @@ -4065,8 +5832,10 @@ typedef struct { #define CCM_ANALOG_PLL_SYS_LOCK_MASK (0x80000000U) #define CCM_ANALOG_PLL_SYS_LOCK_SHIFT (31U) #define CCM_ANALOG_PLL_SYS_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_LOCK_SHIFT)) & CCM_ANALOG_PLL_SYS_LOCK_MASK) +/*! @} */ /*! @name PLL_SYS_SET - Analog System PLL Control Register */ +/*! @{ */ #define CCM_ANALOG_PLL_SYS_SET_DIV_SELECT_MASK (0x1U) #define CCM_ANALOG_PLL_SYS_SET_DIV_SELECT_SHIFT (0U) #define CCM_ANALOG_PLL_SYS_SET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SET_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_SYS_SET_DIV_SELECT_MASK) @@ -4078,6 +5847,10 @@ typedef struct { #define CCM_ANALOG_PLL_SYS_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SET_ENABLE_SHIFT)) & CCM_ANALOG_PLL_SYS_SET_ENABLE_MASK) #define CCM_ANALOG_PLL_SYS_SET_BYPASS_CLK_SRC_MASK (0xC000U) #define CCM_ANALOG_PLL_SYS_SET_BYPASS_CLK_SRC_SHIFT (14U) +/*! BYPASS_CLK_SRC + * 0b00..Select the 24MHz oscillator as source. + * 0b01..Select the CLK1_N / CLK1_P as source. + */ #define CCM_ANALOG_PLL_SYS_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_SYS_SET_BYPASS_CLK_SRC_MASK) #define CCM_ANALOG_PLL_SYS_SET_BYPASS_MASK (0x10000U) #define CCM_ANALOG_PLL_SYS_SET_BYPASS_SHIFT (16U) @@ -4088,8 +5861,10 @@ typedef struct { #define CCM_ANALOG_PLL_SYS_SET_LOCK_MASK (0x80000000U) #define CCM_ANALOG_PLL_SYS_SET_LOCK_SHIFT (31U) #define CCM_ANALOG_PLL_SYS_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SET_LOCK_SHIFT)) & CCM_ANALOG_PLL_SYS_SET_LOCK_MASK) +/*! @} */ /*! @name PLL_SYS_CLR - Analog System PLL Control Register */ +/*! @{ */ #define CCM_ANALOG_PLL_SYS_CLR_DIV_SELECT_MASK (0x1U) #define CCM_ANALOG_PLL_SYS_CLR_DIV_SELECT_SHIFT (0U) #define CCM_ANALOG_PLL_SYS_CLR_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_CLR_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_SYS_CLR_DIV_SELECT_MASK) @@ -4101,6 +5876,10 @@ typedef struct { #define CCM_ANALOG_PLL_SYS_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_CLR_ENABLE_SHIFT)) & CCM_ANALOG_PLL_SYS_CLR_ENABLE_MASK) #define CCM_ANALOG_PLL_SYS_CLR_BYPASS_CLK_SRC_MASK (0xC000U) #define CCM_ANALOG_PLL_SYS_CLR_BYPASS_CLK_SRC_SHIFT (14U) +/*! BYPASS_CLK_SRC + * 0b00..Select the 24MHz oscillator as source. + * 0b01..Select the CLK1_N / CLK1_P as source. + */ #define CCM_ANALOG_PLL_SYS_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_CLR_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_SYS_CLR_BYPASS_CLK_SRC_MASK) #define CCM_ANALOG_PLL_SYS_CLR_BYPASS_MASK (0x10000U) #define CCM_ANALOG_PLL_SYS_CLR_BYPASS_SHIFT (16U) @@ -4111,8 +5890,10 @@ typedef struct { #define CCM_ANALOG_PLL_SYS_CLR_LOCK_MASK (0x80000000U) #define CCM_ANALOG_PLL_SYS_CLR_LOCK_SHIFT (31U) #define CCM_ANALOG_PLL_SYS_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_CLR_LOCK_SHIFT)) & CCM_ANALOG_PLL_SYS_CLR_LOCK_MASK) +/*! @} */ /*! @name PLL_SYS_TOG - Analog System PLL Control Register */ +/*! @{ */ #define CCM_ANALOG_PLL_SYS_TOG_DIV_SELECT_MASK (0x1U) #define CCM_ANALOG_PLL_SYS_TOG_DIV_SELECT_SHIFT (0U) #define CCM_ANALOG_PLL_SYS_TOG_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_TOG_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_SYS_TOG_DIV_SELECT_MASK) @@ -4124,6 +5905,10 @@ typedef struct { #define CCM_ANALOG_PLL_SYS_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_TOG_ENABLE_SHIFT)) & CCM_ANALOG_PLL_SYS_TOG_ENABLE_MASK) #define CCM_ANALOG_PLL_SYS_TOG_BYPASS_CLK_SRC_MASK (0xC000U) #define CCM_ANALOG_PLL_SYS_TOG_BYPASS_CLK_SRC_SHIFT (14U) +/*! BYPASS_CLK_SRC + * 0b00..Select the 24MHz oscillator as source. + * 0b01..Select the CLK1_N / CLK1_P as source. + */ #define CCM_ANALOG_PLL_SYS_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_TOG_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_SYS_TOG_BYPASS_CLK_SRC_MASK) #define CCM_ANALOG_PLL_SYS_TOG_BYPASS_MASK (0x10000U) #define CCM_ANALOG_PLL_SYS_TOG_BYPASS_SHIFT (16U) @@ -4134,29 +5919,41 @@ typedef struct { #define CCM_ANALOG_PLL_SYS_TOG_LOCK_MASK (0x80000000U) #define CCM_ANALOG_PLL_SYS_TOG_LOCK_SHIFT (31U) #define CCM_ANALOG_PLL_SYS_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_TOG_LOCK_SHIFT)) & CCM_ANALOG_PLL_SYS_TOG_LOCK_MASK) +/*! @} */ /*! @name PLL_SYS_SS - 528MHz System PLL Spread Spectrum Register */ +/*! @{ */ #define CCM_ANALOG_PLL_SYS_SS_STEP_MASK (0x7FFFU) #define CCM_ANALOG_PLL_SYS_SS_STEP_SHIFT (0U) #define CCM_ANALOG_PLL_SYS_SS_STEP(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SS_STEP_SHIFT)) & CCM_ANALOG_PLL_SYS_SS_STEP_MASK) #define CCM_ANALOG_PLL_SYS_SS_ENABLE_MASK (0x8000U) #define CCM_ANALOG_PLL_SYS_SS_ENABLE_SHIFT (15U) +/*! ENABLE - Enable bit + * 0b0..Spread spectrum modulation disabled + * 0b1..Soread spectrum modulation enabled + */ #define CCM_ANALOG_PLL_SYS_SS_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SS_ENABLE_SHIFT)) & CCM_ANALOG_PLL_SYS_SS_ENABLE_MASK) #define CCM_ANALOG_PLL_SYS_SS_STOP_MASK (0xFFFF0000U) #define CCM_ANALOG_PLL_SYS_SS_STOP_SHIFT (16U) #define CCM_ANALOG_PLL_SYS_SS_STOP(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SS_STOP_SHIFT)) & CCM_ANALOG_PLL_SYS_SS_STOP_MASK) +/*! @} */ /*! @name PLL_SYS_NUM - Numerator of 528MHz System PLL Fractional Loop Divider Register */ +/*! @{ */ #define CCM_ANALOG_PLL_SYS_NUM_A_MASK (0x3FFFFFFFU) #define CCM_ANALOG_PLL_SYS_NUM_A_SHIFT (0U) #define CCM_ANALOG_PLL_SYS_NUM_A(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_NUM_A_SHIFT)) & CCM_ANALOG_PLL_SYS_NUM_A_MASK) +/*! @} */ /*! @name PLL_SYS_DENOM - Denominator of 528MHz System PLL Fractional Loop Divider Register */ +/*! @{ */ #define CCM_ANALOG_PLL_SYS_DENOM_B_MASK (0x3FFFFFFFU) #define CCM_ANALOG_PLL_SYS_DENOM_B_SHIFT (0U) #define CCM_ANALOG_PLL_SYS_DENOM_B(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_DENOM_B_SHIFT)) & CCM_ANALOG_PLL_SYS_DENOM_B_MASK) +/*! @} */ /*! @name PLL_AUDIO - Analog Audio PLL control Register */ +/*! @{ */ #define CCM_ANALOG_PLL_AUDIO_DIV_SELECT_MASK (0x7FU) #define CCM_ANALOG_PLL_AUDIO_DIV_SELECT_SHIFT (0U) #define CCM_ANALOG_PLL_AUDIO_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_DIV_SELECT_MASK) @@ -4168,6 +5965,12 @@ typedef struct { #define CCM_ANALOG_PLL_AUDIO_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_ENABLE_SHIFT)) & CCM_ANALOG_PLL_AUDIO_ENABLE_MASK) #define CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_MASK (0xC000U) #define CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_SHIFT (14U) +/*! BYPASS_CLK_SRC + * 0b00..Select the 24MHz oscillator as source. + * 0b01..Select the CLK1_N / CLK1_P as source. + * 0b10..Reserved1 + * 0b11..Reserved2 + */ #define CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_MASK) #define CCM_ANALOG_PLL_AUDIO_BYPASS_MASK (0x10000U) #define CCM_ANALOG_PLL_AUDIO_BYPASS_SHIFT (16U) @@ -4177,12 +5980,20 @@ typedef struct { #define CCM_ANALOG_PLL_AUDIO_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_AUDIO_PFD_OFFSET_EN_MASK) #define CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_MASK (0x180000U) #define CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_SHIFT (19U) +/*! POST_DIV_SELECT + * 0b00..Divide by 4. + * 0b01..Divide by 2. + * 0b10..Divide by 1. + * 0b11..Reserved + */ #define CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_MASK) #define CCM_ANALOG_PLL_AUDIO_LOCK_MASK (0x80000000U) #define CCM_ANALOG_PLL_AUDIO_LOCK_SHIFT (31U) #define CCM_ANALOG_PLL_AUDIO_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_LOCK_SHIFT)) & CCM_ANALOG_PLL_AUDIO_LOCK_MASK) +/*! @} */ /*! @name PLL_AUDIO_SET - Analog Audio PLL control Register */ +/*! @{ */ #define CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT_MASK (0x7FU) #define CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT_SHIFT (0U) #define CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT_MASK) @@ -4194,6 +6005,12 @@ typedef struct { #define CCM_ANALOG_PLL_AUDIO_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_ENABLE_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_ENABLE_MASK) #define CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC_MASK (0xC000U) #define CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC_SHIFT (14U) +/*! BYPASS_CLK_SRC + * 0b00..Select the 24MHz oscillator as source. + * 0b01..Select the CLK1_N / CLK1_P as source. + * 0b10..Reserved1 + * 0b11..Reserved2 + */ #define CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC_MASK) #define CCM_ANALOG_PLL_AUDIO_SET_BYPASS_MASK (0x10000U) #define CCM_ANALOG_PLL_AUDIO_SET_BYPASS_SHIFT (16U) @@ -4203,12 +6020,20 @@ typedef struct { #define CCM_ANALOG_PLL_AUDIO_SET_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_PFD_OFFSET_EN_MASK) #define CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SELECT_MASK (0x180000U) #define CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SELECT_SHIFT (19U) +/*! POST_DIV_SELECT + * 0b00..Divide by 4. + * 0b01..Divide by 2. + * 0b10..Divide by 1. + * 0b11..Reserved + */ #define CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SELECT_MASK) #define CCM_ANALOG_PLL_AUDIO_SET_LOCK_MASK (0x80000000U) #define CCM_ANALOG_PLL_AUDIO_SET_LOCK_SHIFT (31U) #define CCM_ANALOG_PLL_AUDIO_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_LOCK_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_LOCK_MASK) +/*! @} */ /*! @name PLL_AUDIO_CLR - Analog Audio PLL control Register */ +/*! @{ */ #define CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT_MASK (0x7FU) #define CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT_SHIFT (0U) #define CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT_MASK) @@ -4220,6 +6045,12 @@ typedef struct { #define CCM_ANALOG_PLL_AUDIO_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_ENABLE_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_ENABLE_MASK) #define CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC_MASK (0xC000U) #define CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC_SHIFT (14U) +/*! BYPASS_CLK_SRC + * 0b00..Select the 24MHz oscillator as source. + * 0b01..Select the CLK1_N / CLK1_P as source. + * 0b10..Reserved1 + * 0b11..Reserved2 + */ #define CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC_MASK) #define CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_MASK (0x10000U) #define CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_SHIFT (16U) @@ -4229,12 +6060,20 @@ typedef struct { #define CCM_ANALOG_PLL_AUDIO_CLR_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_PFD_OFFSET_EN_MASK) #define CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SELECT_MASK (0x180000U) #define CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SELECT_SHIFT (19U) +/*! POST_DIV_SELECT + * 0b00..Divide by 4. + * 0b01..Divide by 2. + * 0b10..Divide by 1. + * 0b11..Reserved + */ #define CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SELECT_MASK) #define CCM_ANALOG_PLL_AUDIO_CLR_LOCK_MASK (0x80000000U) #define CCM_ANALOG_PLL_AUDIO_CLR_LOCK_SHIFT (31U) #define CCM_ANALOG_PLL_AUDIO_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_LOCK_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_LOCK_MASK) +/*! @} */ /*! @name PLL_AUDIO_TOG - Analog Audio PLL control Register */ +/*! @{ */ #define CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT_MASK (0x7FU) #define CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT_SHIFT (0U) #define CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT_MASK) @@ -4246,6 +6085,12 @@ typedef struct { #define CCM_ANALOG_PLL_AUDIO_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_ENABLE_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_ENABLE_MASK) #define CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC_MASK (0xC000U) #define CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC_SHIFT (14U) +/*! BYPASS_CLK_SRC + * 0b00..Select the 24MHz oscillator as source. + * 0b01..Select the CLK1_N / CLK1_P as source. + * 0b10..Reserved1 + * 0b11..Reserved2 + */ #define CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC_MASK) #define CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_MASK (0x10000U) #define CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_SHIFT (16U) @@ -4255,22 +6100,34 @@ typedef struct { #define CCM_ANALOG_PLL_AUDIO_TOG_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_PFD_OFFSET_EN_MASK) #define CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SELECT_MASK (0x180000U) #define CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SELECT_SHIFT (19U) +/*! POST_DIV_SELECT + * 0b00..Divide by 4. + * 0b01..Divide by 2. + * 0b10..Divide by 1. + * 0b11..Reserved + */ #define CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SELECT_MASK) #define CCM_ANALOG_PLL_AUDIO_TOG_LOCK_MASK (0x80000000U) #define CCM_ANALOG_PLL_AUDIO_TOG_LOCK_SHIFT (31U) #define CCM_ANALOG_PLL_AUDIO_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_LOCK_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_LOCK_MASK) +/*! @} */ /*! @name PLL_AUDIO_NUM - Numerator of Audio PLL Fractional Loop Divider Register */ +/*! @{ */ #define CCM_ANALOG_PLL_AUDIO_NUM_A_MASK (0x3FFFFFFFU) #define CCM_ANALOG_PLL_AUDIO_NUM_A_SHIFT (0U) #define CCM_ANALOG_PLL_AUDIO_NUM_A(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_NUM_A_SHIFT)) & CCM_ANALOG_PLL_AUDIO_NUM_A_MASK) +/*! @} */ /*! @name PLL_AUDIO_DENOM - Denominator of Audio PLL Fractional Loop Divider Register */ +/*! @{ */ #define CCM_ANALOG_PLL_AUDIO_DENOM_B_MASK (0x3FFFFFFFU) #define CCM_ANALOG_PLL_AUDIO_DENOM_B_SHIFT (0U) #define CCM_ANALOG_PLL_AUDIO_DENOM_B(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_DENOM_B_SHIFT)) & CCM_ANALOG_PLL_AUDIO_DENOM_B_MASK) +/*! @} */ /*! @name PLL_VIDEO - Analog Video PLL control Register */ +/*! @{ */ #define CCM_ANALOG_PLL_VIDEO_DIV_SELECT_MASK (0x7FU) #define CCM_ANALOG_PLL_VIDEO_DIV_SELECT_SHIFT (0U) #define CCM_ANALOG_PLL_VIDEO_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_VIDEO_DIV_SELECT_MASK) @@ -4282,6 +6139,12 @@ typedef struct { #define CCM_ANALOG_PLL_VIDEO_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_ENABLE_SHIFT)) & CCM_ANALOG_PLL_VIDEO_ENABLE_MASK) #define CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_MASK (0xC000U) #define CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_SHIFT (14U) +/*! BYPASS_CLK_SRC + * 0b00..Select the 24MHz oscillator as source. + * 0b01..Select the CLK1_N / CLK1_P as source. + * 0b10..Reserved1 + * 0b11..Reserved2 + */ #define CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_MASK) #define CCM_ANALOG_PLL_VIDEO_BYPASS_MASK (0x10000U) #define CCM_ANALOG_PLL_VIDEO_BYPASS_SHIFT (16U) @@ -4291,12 +6154,20 @@ typedef struct { #define CCM_ANALOG_PLL_VIDEO_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_VIDEO_PFD_OFFSET_EN_MASK) #define CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT_MASK (0x180000U) #define CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT_SHIFT (19U) +/*! POST_DIV_SELECT + * 0b00..Divide by 4. + * 0b01..Divide by 2. + * 0b10..Divide by 1. + * 0b11..Reserved + */ #define CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT_MASK) #define CCM_ANALOG_PLL_VIDEO_LOCK_MASK (0x80000000U) #define CCM_ANALOG_PLL_VIDEO_LOCK_SHIFT (31U) #define CCM_ANALOG_PLL_VIDEO_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_LOCK_SHIFT)) & CCM_ANALOG_PLL_VIDEO_LOCK_MASK) +/*! @} */ /*! @name PLL_VIDEO_SET - Analog Video PLL control Register */ +/*! @{ */ #define CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT_MASK (0x7FU) #define CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT_SHIFT (0U) #define CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT_MASK) @@ -4308,6 +6179,12 @@ typedef struct { #define CCM_ANALOG_PLL_VIDEO_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_SET_ENABLE_SHIFT)) & CCM_ANALOG_PLL_VIDEO_SET_ENABLE_MASK) #define CCM_ANALOG_PLL_VIDEO_SET_BYPASS_CLK_SRC_MASK (0xC000U) #define CCM_ANALOG_PLL_VIDEO_SET_BYPASS_CLK_SRC_SHIFT (14U) +/*! BYPASS_CLK_SRC + * 0b00..Select the 24MHz oscillator as source. + * 0b01..Select the CLK1_N / CLK1_P as source. + * 0b10..Reserved1 + * 0b11..Reserved2 + */ #define CCM_ANALOG_PLL_VIDEO_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_SET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_VIDEO_SET_BYPASS_CLK_SRC_MASK) #define CCM_ANALOG_PLL_VIDEO_SET_BYPASS_MASK (0x10000U) #define CCM_ANALOG_PLL_VIDEO_SET_BYPASS_SHIFT (16U) @@ -4317,12 +6194,20 @@ typedef struct { #define CCM_ANALOG_PLL_VIDEO_SET_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_SET_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_VIDEO_SET_PFD_OFFSET_EN_MASK) #define CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SELECT_MASK (0x180000U) #define CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SELECT_SHIFT (19U) +/*! POST_DIV_SELECT + * 0b00..Divide by 4. + * 0b01..Divide by 2. + * 0b10..Divide by 1. + * 0b11..Reserved + */ #define CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SELECT_MASK) #define CCM_ANALOG_PLL_VIDEO_SET_LOCK_MASK (0x80000000U) #define CCM_ANALOG_PLL_VIDEO_SET_LOCK_SHIFT (31U) #define CCM_ANALOG_PLL_VIDEO_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_SET_LOCK_SHIFT)) & CCM_ANALOG_PLL_VIDEO_SET_LOCK_MASK) +/*! @} */ /*! @name PLL_VIDEO_CLR - Analog Video PLL control Register */ +/*! @{ */ #define CCM_ANALOG_PLL_VIDEO_CLR_DIV_SELECT_MASK (0x7FU) #define CCM_ANALOG_PLL_VIDEO_CLR_DIV_SELECT_SHIFT (0U) #define CCM_ANALOG_PLL_VIDEO_CLR_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_CLR_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_VIDEO_CLR_DIV_SELECT_MASK) @@ -4334,6 +6219,12 @@ typedef struct { #define CCM_ANALOG_PLL_VIDEO_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_CLR_ENABLE_SHIFT)) & CCM_ANALOG_PLL_VIDEO_CLR_ENABLE_MASK) #define CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_CLK_SRC_MASK (0xC000U) #define CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_CLK_SRC_SHIFT (14U) +/*! BYPASS_CLK_SRC + * 0b00..Select the 24MHz oscillator as source. + * 0b01..Select the CLK1_N / CLK1_P as source. + * 0b10..Reserved1 + * 0b11..Reserved2 + */ #define CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_CLK_SRC_MASK) #define CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_MASK (0x10000U) #define CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_SHIFT (16U) @@ -4343,12 +6234,20 @@ typedef struct { #define CCM_ANALOG_PLL_VIDEO_CLR_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_CLR_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_VIDEO_CLR_PFD_OFFSET_EN_MASK) #define CCM_ANALOG_PLL_VIDEO_CLR_POST_DIV_SELECT_MASK (0x180000U) #define CCM_ANALOG_PLL_VIDEO_CLR_POST_DIV_SELECT_SHIFT (19U) +/*! POST_DIV_SELECT + * 0b00..Divide by 4. + * 0b01..Divide by 2. + * 0b10..Divide by 1. + * 0b11..Reserved + */ #define CCM_ANALOG_PLL_VIDEO_CLR_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_CLR_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_VIDEO_CLR_POST_DIV_SELECT_MASK) #define CCM_ANALOG_PLL_VIDEO_CLR_LOCK_MASK (0x80000000U) #define CCM_ANALOG_PLL_VIDEO_CLR_LOCK_SHIFT (31U) #define CCM_ANALOG_PLL_VIDEO_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_CLR_LOCK_SHIFT)) & CCM_ANALOG_PLL_VIDEO_CLR_LOCK_MASK) +/*! @} */ /*! @name PLL_VIDEO_TOG - Analog Video PLL control Register */ +/*! @{ */ #define CCM_ANALOG_PLL_VIDEO_TOG_DIV_SELECT_MASK (0x7FU) #define CCM_ANALOG_PLL_VIDEO_TOG_DIV_SELECT_SHIFT (0U) #define CCM_ANALOG_PLL_VIDEO_TOG_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_TOG_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_VIDEO_TOG_DIV_SELECT_MASK) @@ -4360,6 +6259,12 @@ typedef struct { #define CCM_ANALOG_PLL_VIDEO_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_TOG_ENABLE_SHIFT)) & CCM_ANALOG_PLL_VIDEO_TOG_ENABLE_MASK) #define CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_CLK_SRC_MASK (0xC000U) #define CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_CLK_SRC_SHIFT (14U) +/*! BYPASS_CLK_SRC + * 0b00..Select the 24MHz oscillator as source. + * 0b01..Select the CLK1_N / CLK1_P as source. + * 0b10..Reserved1 + * 0b11..Reserved2 + */ #define CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_CLK_SRC_MASK) #define CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_MASK (0x10000U) #define CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_SHIFT (16U) @@ -4369,36 +6274,51 @@ typedef struct { #define CCM_ANALOG_PLL_VIDEO_TOG_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_TOG_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_VIDEO_TOG_PFD_OFFSET_EN_MASK) #define CCM_ANALOG_PLL_VIDEO_TOG_POST_DIV_SELECT_MASK (0x180000U) #define CCM_ANALOG_PLL_VIDEO_TOG_POST_DIV_SELECT_SHIFT (19U) +/*! POST_DIV_SELECT + * 0b00..Divide by 4. + * 0b01..Divide by 2. + * 0b10..Divide by 1. + * 0b11..Reserved + */ #define CCM_ANALOG_PLL_VIDEO_TOG_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_TOG_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_VIDEO_TOG_POST_DIV_SELECT_MASK) #define CCM_ANALOG_PLL_VIDEO_TOG_LOCK_MASK (0x80000000U) #define CCM_ANALOG_PLL_VIDEO_TOG_LOCK_SHIFT (31U) #define CCM_ANALOG_PLL_VIDEO_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_TOG_LOCK_SHIFT)) & CCM_ANALOG_PLL_VIDEO_TOG_LOCK_MASK) +/*! @} */ /*! @name PLL_VIDEO_NUM - Numerator of Video PLL Fractional Loop Divider Register */ +/*! @{ */ #define CCM_ANALOG_PLL_VIDEO_NUM_A_MASK (0x3FFFFFFFU) #define CCM_ANALOG_PLL_VIDEO_NUM_A_SHIFT (0U) #define CCM_ANALOG_PLL_VIDEO_NUM_A(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_NUM_A_SHIFT)) & CCM_ANALOG_PLL_VIDEO_NUM_A_MASK) +/*! @} */ /*! @name PLL_VIDEO_DENOM - Denominator of Video PLL Fractional Loop Divider Register */ +/*! @{ */ #define CCM_ANALOG_PLL_VIDEO_DENOM_B_MASK (0x3FFFFFFFU) #define CCM_ANALOG_PLL_VIDEO_DENOM_B_SHIFT (0U) #define CCM_ANALOG_PLL_VIDEO_DENOM_B(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_DENOM_B_SHIFT)) & CCM_ANALOG_PLL_VIDEO_DENOM_B_MASK) +/*! @} */ /*! @name PLL_ENET - Analog ENET PLL Control Register */ -#define CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT_MASK (0x3U) -#define CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT_SHIFT (0U) -#define CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT_MASK) -#define CCM_ANALOG_PLL_ENET_ENET1_DIV_SELECT_MASK (0xCU) -#define CCM_ANALOG_PLL_ENET_ENET1_DIV_SELECT_SHIFT (2U) -#define CCM_ANALOG_PLL_ENET_ENET1_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_ENET1_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ENET_ENET1_DIV_SELECT_MASK) +/*! @{ */ +#define CCM_ANALOG_PLL_ENET_DIV_SELECT_MASK (0x3U) +#define CCM_ANALOG_PLL_ENET_DIV_SELECT_SHIFT (0U) +#define CCM_ANALOG_PLL_ENET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ENET_DIV_SELECT_MASK) #define CCM_ANALOG_PLL_ENET_POWERDOWN_MASK (0x1000U) #define CCM_ANALOG_PLL_ENET_POWERDOWN_SHIFT (12U) #define CCM_ANALOG_PLL_ENET_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_ENET_POWERDOWN_MASK) -#define CCM_ANALOG_PLL_ENET_ENET1_125M_EN_MASK (0x2000U) -#define CCM_ANALOG_PLL_ENET_ENET1_125M_EN_SHIFT (13U) -#define CCM_ANALOG_PLL_ENET_ENET1_125M_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_ENET1_125M_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_ENET1_125M_EN_MASK) +#define CCM_ANALOG_PLL_ENET_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_ENET_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_ENET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_ENABLE_SHIFT)) & CCM_ANALOG_PLL_ENET_ENABLE_MASK) #define CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_MASK (0xC000U) #define CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_SHIFT (14U) +/*! BYPASS_CLK_SRC + * 0b00..Select the 24MHz oscillator as source. + * 0b01..Select the CLK1_N / CLK1_P as source. + * 0b10..Reserved1 + * 0b11..Reserved2 + */ #define CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_MASK) #define CCM_ANALOG_PLL_ENET_BYPASS_MASK (0x10000U) #define CCM_ANALOG_PLL_ENET_BYPASS_SHIFT (16U) @@ -4406,34 +6326,33 @@ typedef struct { #define CCM_ANALOG_PLL_ENET_PFD_OFFSET_EN_MASK (0x40000U) #define CCM_ANALOG_PLL_ENET_PFD_OFFSET_EN_SHIFT (18U) #define CCM_ANALOG_PLL_ENET_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_PFD_OFFSET_EN_MASK) -#define CCM_ANALOG_PLL_ENET_ENABLE_125M_MASK (0x80000U) -#define CCM_ANALOG_PLL_ENET_ENABLE_125M_SHIFT (19U) -#define CCM_ANALOG_PLL_ENET_ENABLE_125M(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_ENABLE_125M_SHIFT)) & CCM_ANALOG_PLL_ENET_ENABLE_125M_MASK) -#define CCM_ANALOG_PLL_ENET_ENET2_125M_EN_MASK (0x100000U) -#define CCM_ANALOG_PLL_ENET_ENET2_125M_EN_SHIFT (20U) -#define CCM_ANALOG_PLL_ENET_ENET2_125M_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_ENET2_125M_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_ENET2_125M_EN_MASK) #define CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_MASK (0x200000U) #define CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_SHIFT (21U) #define CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_MASK) #define CCM_ANALOG_PLL_ENET_LOCK_MASK (0x80000000U) #define CCM_ANALOG_PLL_ENET_LOCK_SHIFT (31U) #define CCM_ANALOG_PLL_ENET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_LOCK_SHIFT)) & CCM_ANALOG_PLL_ENET_LOCK_MASK) +/*! @} */ /*! @name PLL_ENET_SET - Analog ENET PLL Control Register */ -#define CCM_ANALOG_PLL_ENET_SET_ENET0_DIV_SELECT_MASK (0x3U) -#define CCM_ANALOG_PLL_ENET_SET_ENET0_DIV_SELECT_SHIFT (0U) -#define CCM_ANALOG_PLL_ENET_SET_ENET0_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_ENET0_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_ENET0_DIV_SELECT_MASK) -#define CCM_ANALOG_PLL_ENET_SET_ENET1_DIV_SELECT_MASK (0xCU) -#define CCM_ANALOG_PLL_ENET_SET_ENET1_DIV_SELECT_SHIFT (2U) -#define CCM_ANALOG_PLL_ENET_SET_ENET1_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_ENET1_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_ENET1_DIV_SELECT_MASK) +/*! @{ */ +#define CCM_ANALOG_PLL_ENET_SET_DIV_SELECT_MASK (0x3U) +#define CCM_ANALOG_PLL_ENET_SET_DIV_SELECT_SHIFT (0U) +#define CCM_ANALOG_PLL_ENET_SET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_DIV_SELECT_MASK) #define CCM_ANALOG_PLL_ENET_SET_POWERDOWN_MASK (0x1000U) #define CCM_ANALOG_PLL_ENET_SET_POWERDOWN_SHIFT (12U) #define CCM_ANALOG_PLL_ENET_SET_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_POWERDOWN_MASK) -#define CCM_ANALOG_PLL_ENET_SET_ENET1_125M_EN_MASK (0x2000U) -#define CCM_ANALOG_PLL_ENET_SET_ENET1_125M_EN_SHIFT (13U) -#define CCM_ANALOG_PLL_ENET_SET_ENET1_125M_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_ENET1_125M_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_ENET1_125M_EN_MASK) +#define CCM_ANALOG_PLL_ENET_SET_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_ENET_SET_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_ENET_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_ENABLE_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_ENABLE_MASK) #define CCM_ANALOG_PLL_ENET_SET_BYPASS_CLK_SRC_MASK (0xC000U) #define CCM_ANALOG_PLL_ENET_SET_BYPASS_CLK_SRC_SHIFT (14U) +/*! BYPASS_CLK_SRC + * 0b00..Select the 24MHz oscillator as source. + * 0b01..Select the CLK1_N / CLK1_P as source. + * 0b10..Reserved1 + * 0b11..Reserved2 + */ #define CCM_ANALOG_PLL_ENET_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_BYPASS_CLK_SRC_MASK) #define CCM_ANALOG_PLL_ENET_SET_BYPASS_MASK (0x10000U) #define CCM_ANALOG_PLL_ENET_SET_BYPASS_SHIFT (16U) @@ -4441,34 +6360,33 @@ typedef struct { #define CCM_ANALOG_PLL_ENET_SET_PFD_OFFSET_EN_MASK (0x40000U) #define CCM_ANALOG_PLL_ENET_SET_PFD_OFFSET_EN_SHIFT (18U) #define CCM_ANALOG_PLL_ENET_SET_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_PFD_OFFSET_EN_MASK) -#define CCM_ANALOG_PLL_ENET_SET_ENABLE_125M_MASK (0x80000U) -#define CCM_ANALOG_PLL_ENET_SET_ENABLE_125M_SHIFT (19U) -#define CCM_ANALOG_PLL_ENET_SET_ENABLE_125M(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_ENABLE_125M_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_ENABLE_125M_MASK) -#define CCM_ANALOG_PLL_ENET_SET_ENET2_125M_EN_MASK (0x100000U) -#define CCM_ANALOG_PLL_ENET_SET_ENET2_125M_EN_SHIFT (20U) -#define CCM_ANALOG_PLL_ENET_SET_ENET2_125M_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_ENET2_125M_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_ENET2_125M_EN_MASK) #define CCM_ANALOG_PLL_ENET_SET_ENET_25M_REF_EN_MASK (0x200000U) #define CCM_ANALOG_PLL_ENET_SET_ENET_25M_REF_EN_SHIFT (21U) #define CCM_ANALOG_PLL_ENET_SET_ENET_25M_REF_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_ENET_25M_REF_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_ENET_25M_REF_EN_MASK) #define CCM_ANALOG_PLL_ENET_SET_LOCK_MASK (0x80000000U) #define CCM_ANALOG_PLL_ENET_SET_LOCK_SHIFT (31U) #define CCM_ANALOG_PLL_ENET_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_LOCK_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_LOCK_MASK) +/*! @} */ /*! @name PLL_ENET_CLR - Analog ENET PLL Control Register */ -#define CCM_ANALOG_PLL_ENET_CLR_ENET0_DIV_SELECT_MASK (0x3U) -#define CCM_ANALOG_PLL_ENET_CLR_ENET0_DIV_SELECT_SHIFT (0U) -#define CCM_ANALOG_PLL_ENET_CLR_ENET0_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_ENET0_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_ENET0_DIV_SELECT_MASK) -#define CCM_ANALOG_PLL_ENET_CLR_ENET1_DIV_SELECT_MASK (0xCU) -#define CCM_ANALOG_PLL_ENET_CLR_ENET1_DIV_SELECT_SHIFT (2U) -#define CCM_ANALOG_PLL_ENET_CLR_ENET1_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_ENET1_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_ENET1_DIV_SELECT_MASK) +/*! @{ */ +#define CCM_ANALOG_PLL_ENET_CLR_DIV_SELECT_MASK (0x3U) +#define CCM_ANALOG_PLL_ENET_CLR_DIV_SELECT_SHIFT (0U) +#define CCM_ANALOG_PLL_ENET_CLR_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_DIV_SELECT_MASK) #define CCM_ANALOG_PLL_ENET_CLR_POWERDOWN_MASK (0x1000U) #define CCM_ANALOG_PLL_ENET_CLR_POWERDOWN_SHIFT (12U) #define CCM_ANALOG_PLL_ENET_CLR_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_POWERDOWN_MASK) -#define CCM_ANALOG_PLL_ENET_CLR_ENET1_125M_EN_MASK (0x2000U) -#define CCM_ANALOG_PLL_ENET_CLR_ENET1_125M_EN_SHIFT (13U) -#define CCM_ANALOG_PLL_ENET_CLR_ENET1_125M_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_ENET1_125M_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_ENET1_125M_EN_MASK) +#define CCM_ANALOG_PLL_ENET_CLR_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_ENET_CLR_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_ENET_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_ENABLE_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_ENABLE_MASK) #define CCM_ANALOG_PLL_ENET_CLR_BYPASS_CLK_SRC_MASK (0xC000U) #define CCM_ANALOG_PLL_ENET_CLR_BYPASS_CLK_SRC_SHIFT (14U) +/*! BYPASS_CLK_SRC + * 0b00..Select the 24MHz oscillator as source. + * 0b01..Select the CLK1_N / CLK1_P as source. + * 0b10..Reserved1 + * 0b11..Reserved2 + */ #define CCM_ANALOG_PLL_ENET_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_BYPASS_CLK_SRC_MASK) #define CCM_ANALOG_PLL_ENET_CLR_BYPASS_MASK (0x10000U) #define CCM_ANALOG_PLL_ENET_CLR_BYPASS_SHIFT (16U) @@ -4476,34 +6394,33 @@ typedef struct { #define CCM_ANALOG_PLL_ENET_CLR_PFD_OFFSET_EN_MASK (0x40000U) #define CCM_ANALOG_PLL_ENET_CLR_PFD_OFFSET_EN_SHIFT (18U) #define CCM_ANALOG_PLL_ENET_CLR_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_PFD_OFFSET_EN_MASK) -#define CCM_ANALOG_PLL_ENET_CLR_ENABLE_125M_MASK (0x80000U) -#define CCM_ANALOG_PLL_ENET_CLR_ENABLE_125M_SHIFT (19U) -#define CCM_ANALOG_PLL_ENET_CLR_ENABLE_125M(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_ENABLE_125M_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_ENABLE_125M_MASK) -#define CCM_ANALOG_PLL_ENET_CLR_ENET2_125M_EN_MASK (0x100000U) -#define CCM_ANALOG_PLL_ENET_CLR_ENET2_125M_EN_SHIFT (20U) -#define CCM_ANALOG_PLL_ENET_CLR_ENET2_125M_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_ENET2_125M_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_ENET2_125M_EN_MASK) #define CCM_ANALOG_PLL_ENET_CLR_ENET_25M_REF_EN_MASK (0x200000U) #define CCM_ANALOG_PLL_ENET_CLR_ENET_25M_REF_EN_SHIFT (21U) #define CCM_ANALOG_PLL_ENET_CLR_ENET_25M_REF_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_ENET_25M_REF_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_ENET_25M_REF_EN_MASK) #define CCM_ANALOG_PLL_ENET_CLR_LOCK_MASK (0x80000000U) #define CCM_ANALOG_PLL_ENET_CLR_LOCK_SHIFT (31U) #define CCM_ANALOG_PLL_ENET_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_LOCK_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_LOCK_MASK) +/*! @} */ /*! @name PLL_ENET_TOG - Analog ENET PLL Control Register */ -#define CCM_ANALOG_PLL_ENET_TOG_ENET0_DIV_SELECT_MASK (0x3U) -#define CCM_ANALOG_PLL_ENET_TOG_ENET0_DIV_SELECT_SHIFT (0U) -#define CCM_ANALOG_PLL_ENET_TOG_ENET0_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_ENET0_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_ENET0_DIV_SELECT_MASK) -#define CCM_ANALOG_PLL_ENET_TOG_ENET1_DIV_SELECT_MASK (0xCU) -#define CCM_ANALOG_PLL_ENET_TOG_ENET1_DIV_SELECT_SHIFT (2U) -#define CCM_ANALOG_PLL_ENET_TOG_ENET1_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_ENET1_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_ENET1_DIV_SELECT_MASK) +/*! @{ */ +#define CCM_ANALOG_PLL_ENET_TOG_DIV_SELECT_MASK (0x3U) +#define CCM_ANALOG_PLL_ENET_TOG_DIV_SELECT_SHIFT (0U) +#define CCM_ANALOG_PLL_ENET_TOG_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_DIV_SELECT_MASK) #define CCM_ANALOG_PLL_ENET_TOG_POWERDOWN_MASK (0x1000U) #define CCM_ANALOG_PLL_ENET_TOG_POWERDOWN_SHIFT (12U) #define CCM_ANALOG_PLL_ENET_TOG_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_POWERDOWN_MASK) -#define CCM_ANALOG_PLL_ENET_TOG_ENET1_125M_EN_MASK (0x2000U) -#define CCM_ANALOG_PLL_ENET_TOG_ENET1_125M_EN_SHIFT (13U) -#define CCM_ANALOG_PLL_ENET_TOG_ENET1_125M_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_ENET1_125M_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_ENET1_125M_EN_MASK) +#define CCM_ANALOG_PLL_ENET_TOG_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_ENET_TOG_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_ENET_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_ENABLE_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_ENABLE_MASK) #define CCM_ANALOG_PLL_ENET_TOG_BYPASS_CLK_SRC_MASK (0xC000U) #define CCM_ANALOG_PLL_ENET_TOG_BYPASS_CLK_SRC_SHIFT (14U) +/*! BYPASS_CLK_SRC + * 0b00..Select the 24MHz oscillator as source. + * 0b01..Select the CLK1_N / CLK1_P as source. + * 0b10..Reserved1 + * 0b11..Reserved2 + */ #define CCM_ANALOG_PLL_ENET_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_BYPASS_CLK_SRC_MASK) #define CCM_ANALOG_PLL_ENET_TOG_BYPASS_MASK (0x10000U) #define CCM_ANALOG_PLL_ENET_TOG_BYPASS_SHIFT (16U) @@ -4511,20 +6428,16 @@ typedef struct { #define CCM_ANALOG_PLL_ENET_TOG_PFD_OFFSET_EN_MASK (0x40000U) #define CCM_ANALOG_PLL_ENET_TOG_PFD_OFFSET_EN_SHIFT (18U) #define CCM_ANALOG_PLL_ENET_TOG_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_PFD_OFFSET_EN_MASK) -#define CCM_ANALOG_PLL_ENET_TOG_ENABLE_125M_MASK (0x80000U) -#define CCM_ANALOG_PLL_ENET_TOG_ENABLE_125M_SHIFT (19U) -#define CCM_ANALOG_PLL_ENET_TOG_ENABLE_125M(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_ENABLE_125M_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_ENABLE_125M_MASK) -#define CCM_ANALOG_PLL_ENET_TOG_ENET2_125M_EN_MASK (0x100000U) -#define CCM_ANALOG_PLL_ENET_TOG_ENET2_125M_EN_SHIFT (20U) -#define CCM_ANALOG_PLL_ENET_TOG_ENET2_125M_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_ENET2_125M_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_ENET2_125M_EN_MASK) #define CCM_ANALOG_PLL_ENET_TOG_ENET_25M_REF_EN_MASK (0x200000U) #define CCM_ANALOG_PLL_ENET_TOG_ENET_25M_REF_EN_SHIFT (21U) #define CCM_ANALOG_PLL_ENET_TOG_ENET_25M_REF_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_ENET_25M_REF_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_ENET_25M_REF_EN_MASK) #define CCM_ANALOG_PLL_ENET_TOG_LOCK_MASK (0x80000000U) #define CCM_ANALOG_PLL_ENET_TOG_LOCK_SHIFT (31U) #define CCM_ANALOG_PLL_ENET_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_LOCK_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_LOCK_MASK) +/*! @} */ /*! @name PFD_480 - 480MHz Clock (PLL3) Phase Fractional Divider Control Register */ +/*! @{ */ #define CCM_ANALOG_PFD_480_PFD0_FRAC_MASK (0x3FU) #define CCM_ANALOG_PFD_480_PFD0_FRAC_SHIFT (0U) #define CCM_ANALOG_PFD_480_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_PFD0_FRAC_MASK) @@ -4561,8 +6474,10 @@ typedef struct { #define CCM_ANALOG_PFD_480_PFD3_CLKGATE_MASK (0x80000000U) #define CCM_ANALOG_PFD_480_PFD3_CLKGATE_SHIFT (31U) #define CCM_ANALOG_PFD_480_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_PFD3_CLKGATE_MASK) +/*! @} */ /*! @name PFD_480_SET - 480MHz Clock (PLL3) Phase Fractional Divider Control Register */ +/*! @{ */ #define CCM_ANALOG_PFD_480_SET_PFD0_FRAC_MASK (0x3FU) #define CCM_ANALOG_PFD_480_SET_PFD0_FRAC_SHIFT (0U) #define CCM_ANALOG_PFD_480_SET_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD0_FRAC_MASK) @@ -4599,8 +6514,10 @@ typedef struct { #define CCM_ANALOG_PFD_480_SET_PFD3_CLKGATE_MASK (0x80000000U) #define CCM_ANALOG_PFD_480_SET_PFD3_CLKGATE_SHIFT (31U) #define CCM_ANALOG_PFD_480_SET_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD3_CLKGATE_MASK) +/*! @} */ /*! @name PFD_480_CLR - 480MHz Clock (PLL3) Phase Fractional Divider Control Register */ +/*! @{ */ #define CCM_ANALOG_PFD_480_CLR_PFD0_FRAC_MASK (0x3FU) #define CCM_ANALOG_PFD_480_CLR_PFD0_FRAC_SHIFT (0U) #define CCM_ANALOG_PFD_480_CLR_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD0_FRAC_MASK) @@ -4637,8 +6554,10 @@ typedef struct { #define CCM_ANALOG_PFD_480_CLR_PFD3_CLKGATE_MASK (0x80000000U) #define CCM_ANALOG_PFD_480_CLR_PFD3_CLKGATE_SHIFT (31U) #define CCM_ANALOG_PFD_480_CLR_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD3_CLKGATE_MASK) +/*! @} */ /*! @name PFD_480_TOG - 480MHz Clock (PLL3) Phase Fractional Divider Control Register */ +/*! @{ */ #define CCM_ANALOG_PFD_480_TOG_PFD0_FRAC_MASK (0x3FU) #define CCM_ANALOG_PFD_480_TOG_PFD0_FRAC_SHIFT (0U) #define CCM_ANALOG_PFD_480_TOG_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD0_FRAC_MASK) @@ -4675,8 +6594,10 @@ typedef struct { #define CCM_ANALOG_PFD_480_TOG_PFD3_CLKGATE_MASK (0x80000000U) #define CCM_ANALOG_PFD_480_TOG_PFD3_CLKGATE_SHIFT (31U) #define CCM_ANALOG_PFD_480_TOG_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD3_CLKGATE_MASK) +/*! @} */ /*! @name PFD_528 - 528MHz Clock (PLL2) Phase Fractional Divider Control Register */ +/*! @{ */ #define CCM_ANALOG_PFD_528_PFD0_FRAC_MASK (0x3FU) #define CCM_ANALOG_PFD_528_PFD0_FRAC_SHIFT (0U) #define CCM_ANALOG_PFD_528_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_PFD0_FRAC_MASK) @@ -4713,8 +6634,10 @@ typedef struct { #define CCM_ANALOG_PFD_528_PFD3_CLKGATE_MASK (0x80000000U) #define CCM_ANALOG_PFD_528_PFD3_CLKGATE_SHIFT (31U) #define CCM_ANALOG_PFD_528_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_PFD3_CLKGATE_MASK) +/*! @} */ /*! @name PFD_528_SET - 528MHz Clock (PLL2) Phase Fractional Divider Control Register */ +/*! @{ */ #define CCM_ANALOG_PFD_528_SET_PFD0_FRAC_MASK (0x3FU) #define CCM_ANALOG_PFD_528_SET_PFD0_FRAC_SHIFT (0U) #define CCM_ANALOG_PFD_528_SET_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD0_FRAC_MASK) @@ -4751,8 +6674,10 @@ typedef struct { #define CCM_ANALOG_PFD_528_SET_PFD3_CLKGATE_MASK (0x80000000U) #define CCM_ANALOG_PFD_528_SET_PFD3_CLKGATE_SHIFT (31U) #define CCM_ANALOG_PFD_528_SET_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD3_CLKGATE_MASK) +/*! @} */ /*! @name PFD_528_CLR - 528MHz Clock (PLL2) Phase Fractional Divider Control Register */ +/*! @{ */ #define CCM_ANALOG_PFD_528_CLR_PFD0_FRAC_MASK (0x3FU) #define CCM_ANALOG_PFD_528_CLR_PFD0_FRAC_SHIFT (0U) #define CCM_ANALOG_PFD_528_CLR_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD0_FRAC_MASK) @@ -4789,8 +6714,10 @@ typedef struct { #define CCM_ANALOG_PFD_528_CLR_PFD3_CLKGATE_MASK (0x80000000U) #define CCM_ANALOG_PFD_528_CLR_PFD3_CLKGATE_SHIFT (31U) #define CCM_ANALOG_PFD_528_CLR_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD3_CLKGATE_MASK) +/*! @} */ /*! @name PFD_528_TOG - 528MHz Clock (PLL2) Phase Fractional Divider Control Register */ +/*! @{ */ #define CCM_ANALOG_PFD_528_TOG_PFD0_FRAC_MASK (0x3FU) #define CCM_ANALOG_PFD_528_TOG_PFD0_FRAC_SHIFT (0U) #define CCM_ANALOG_PFD_528_TOG_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD0_FRAC_MASK) @@ -4827,28 +6754,60 @@ typedef struct { #define CCM_ANALOG_PFD_528_TOG_PFD3_CLKGATE_MASK (0x80000000U) #define CCM_ANALOG_PFD_528_TOG_PFD3_CLKGATE_SHIFT (31U) #define CCM_ANALOG_PFD_528_TOG_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD3_CLKGATE_MASK) +/*! @} */ /*! @name MISC0 - Miscellaneous Register 0 */ +/*! @{ */ #define CCM_ANALOG_MISC0_REFTOP_PWD_MASK (0x1U) #define CCM_ANALOG_MISC0_REFTOP_PWD_SHIFT (0U) #define CCM_ANALOG_MISC0_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_REFTOP_PWD_SHIFT)) & CCM_ANALOG_MISC0_REFTOP_PWD_MASK) #define CCM_ANALOG_MISC0_REFTOP_SELFBIASOFF_MASK (0x8U) #define CCM_ANALOG_MISC0_REFTOP_SELFBIASOFF_SHIFT (3U) +/*! REFTOP_SELFBIASOFF + * 0b0..Uses coarse bias currents for startup + * 0b1..Uses bandgap-based bias currents for best performance. + */ #define CCM_ANALOG_MISC0_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_REFTOP_SELFBIASOFF_SHIFT)) & CCM_ANALOG_MISC0_REFTOP_SELFBIASOFF_MASK) #define CCM_ANALOG_MISC0_REFTOP_VBGADJ_MASK (0x70U) #define CCM_ANALOG_MISC0_REFTOP_VBGADJ_SHIFT (4U) +/*! REFTOP_VBGADJ + * 0b000..Nominal VBG + * 0b001..VBG+0.78% + * 0b010..VBG+1.56% + * 0b011..VBG+2.34% + * 0b100..VBG-0.78% + * 0b101..VBG-1.56% + * 0b110..VBG-2.34% + * 0b111..VBG-3.12% + */ #define CCM_ANALOG_MISC0_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_REFTOP_VBGADJ_SHIFT)) & CCM_ANALOG_MISC0_REFTOP_VBGADJ_MASK) #define CCM_ANALOG_MISC0_REFTOP_VBGUP_MASK (0x80U) #define CCM_ANALOG_MISC0_REFTOP_VBGUP_SHIFT (7U) #define CCM_ANALOG_MISC0_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_REFTOP_VBGUP_SHIFT)) & CCM_ANALOG_MISC0_REFTOP_VBGUP_MASK) #define CCM_ANALOG_MISC0_STOP_MODE_CONFIG_MASK (0xC00U) #define CCM_ANALOG_MISC0_STOP_MODE_CONFIG_SHIFT (10U) +/*! STOP_MODE_CONFIG + * 0b00..All analog except rtc powered down on stop mode assertion. XtalOsc=on, RCOsc=off; + * 0b01..Certain analog functions such as certain regulators left up. XtalOsc=on, RCOsc=off; + * 0b10..XtalOsc=off, RCOsc=on, Old BG=on, New BG=off. + * 0b11..XtalOsc=off, RCOsc=on, Old BG=off, New BG=on. + */ #define CCM_ANALOG_MISC0_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_STOP_MODE_CONFIG_SHIFT)) & CCM_ANALOG_MISC0_STOP_MODE_CONFIG_MASK) #define CCM_ANALOG_MISC0_DISCON_HIGH_SNVS_MASK (0x1000U) #define CCM_ANALOG_MISC0_DISCON_HIGH_SNVS_SHIFT (12U) +/*! DISCON_HIGH_SNVS + * 0b0..Turn on the switch + * 0b1..Turn off the switch + */ #define CCM_ANALOG_MISC0_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_DISCON_HIGH_SNVS_SHIFT)) & CCM_ANALOG_MISC0_DISCON_HIGH_SNVS_MASK) #define CCM_ANALOG_MISC0_OSC_I_MASK (0x6000U) #define CCM_ANALOG_MISC0_OSC_I_SHIFT (13U) +/*! OSC_I + * 0b00..Nominal + * 0b01..Decrease current by 12.5% + * 0b10..Decrease current by 25.0% + * 0b11..Decrease current by 37.5% + */ #define CCM_ANALOG_MISC0_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_OSC_I_SHIFT)) & CCM_ANALOG_MISC0_OSC_I_MASK) #define CCM_ANALOG_MISC0_OSC_XTALOK_MASK (0x8000U) #define CCM_ANALOG_MISC0_OSC_XTALOK_SHIFT (15U) @@ -4858,41 +6817,88 @@ typedef struct { #define CCM_ANALOG_MISC0_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_OSC_XTALOK_EN_SHIFT)) & CCM_ANALOG_MISC0_OSC_XTALOK_EN_MASK) #define CCM_ANALOG_MISC0_CLKGATE_CTRL_MASK (0x2000000U) #define CCM_ANALOG_MISC0_CLKGATE_CTRL_SHIFT (25U) +/*! CLKGATE_CTRL + * 0b0..Allow the logic to automatically gate the clock when the XTAL is powered down. + * 0b1..Prevent the logic from ever gating off the clock. + */ #define CCM_ANALOG_MISC0_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLKGATE_CTRL_SHIFT)) & CCM_ANALOG_MISC0_CLKGATE_CTRL_MASK) #define CCM_ANALOG_MISC0_CLKGATE_DELAY_MASK (0x1C000000U) #define CCM_ANALOG_MISC0_CLKGATE_DELAY_SHIFT (26U) +/*! CLKGATE_DELAY + * 0b000..0.5ms + * 0b001..1.0ms + * 0b010..2.0ms + * 0b011..3.0ms + * 0b100..4.0ms + * 0b101..5.0ms + * 0b110..6.0ms + * 0b111..7.0ms + */ #define CCM_ANALOG_MISC0_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLKGATE_DELAY_SHIFT)) & CCM_ANALOG_MISC0_CLKGATE_DELAY_MASK) #define CCM_ANALOG_MISC0_RTC_XTAL_SOURCE_MASK (0x20000000U) #define CCM_ANALOG_MISC0_RTC_XTAL_SOURCE_SHIFT (29U) +/*! RTC_XTAL_SOURCE + * 0b0..Internal ring oscillator + * 0b1..RTC_XTAL + */ #define CCM_ANALOG_MISC0_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_RTC_XTAL_SOURCE_SHIFT)) & CCM_ANALOG_MISC0_RTC_XTAL_SOURCE_MASK) #define CCM_ANALOG_MISC0_XTAL_24M_PWD_MASK (0x40000000U) #define CCM_ANALOG_MISC0_XTAL_24M_PWD_SHIFT (30U) #define CCM_ANALOG_MISC0_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_XTAL_24M_PWD_SHIFT)) & CCM_ANALOG_MISC0_XTAL_24M_PWD_MASK) -#define CCM_ANALOG_MISC0_VID_PLL_PREDIV_MASK (0x80000000U) -#define CCM_ANALOG_MISC0_VID_PLL_PREDIV_SHIFT (31U) -#define CCM_ANALOG_MISC0_VID_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_VID_PLL_PREDIV_SHIFT)) & CCM_ANALOG_MISC0_VID_PLL_PREDIV_MASK) +/*! @} */ /*! @name MISC0_SET - Miscellaneous Register 0 */ +/*! @{ */ #define CCM_ANALOG_MISC0_SET_REFTOP_PWD_MASK (0x1U) #define CCM_ANALOG_MISC0_SET_REFTOP_PWD_SHIFT (0U) #define CCM_ANALOG_MISC0_SET_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_REFTOP_PWD_SHIFT)) & CCM_ANALOG_MISC0_SET_REFTOP_PWD_MASK) #define CCM_ANALOG_MISC0_SET_REFTOP_SELFBIASOFF_MASK (0x8U) #define CCM_ANALOG_MISC0_SET_REFTOP_SELFBIASOFF_SHIFT (3U) +/*! REFTOP_SELFBIASOFF + * 0b0..Uses coarse bias currents for startup + * 0b1..Uses bandgap-based bias currents for best performance. + */ #define CCM_ANALOG_MISC0_SET_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_REFTOP_SELFBIASOFF_SHIFT)) & CCM_ANALOG_MISC0_SET_REFTOP_SELFBIASOFF_MASK) #define CCM_ANALOG_MISC0_SET_REFTOP_VBGADJ_MASK (0x70U) #define CCM_ANALOG_MISC0_SET_REFTOP_VBGADJ_SHIFT (4U) +/*! REFTOP_VBGADJ + * 0b000..Nominal VBG + * 0b001..VBG+0.78% + * 0b010..VBG+1.56% + * 0b011..VBG+2.34% + * 0b100..VBG-0.78% + * 0b101..VBG-1.56% + * 0b110..VBG-2.34% + * 0b111..VBG-3.12% + */ #define CCM_ANALOG_MISC0_SET_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_REFTOP_VBGADJ_SHIFT)) & CCM_ANALOG_MISC0_SET_REFTOP_VBGADJ_MASK) #define CCM_ANALOG_MISC0_SET_REFTOP_VBGUP_MASK (0x80U) #define CCM_ANALOG_MISC0_SET_REFTOP_VBGUP_SHIFT (7U) #define CCM_ANALOG_MISC0_SET_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_REFTOP_VBGUP_SHIFT)) & CCM_ANALOG_MISC0_SET_REFTOP_VBGUP_MASK) #define CCM_ANALOG_MISC0_SET_STOP_MODE_CONFIG_MASK (0xC00U) #define CCM_ANALOG_MISC0_SET_STOP_MODE_CONFIG_SHIFT (10U) +/*! STOP_MODE_CONFIG + * 0b00..All analog except rtc powered down on stop mode assertion. XtalOsc=on, RCOsc=off; + * 0b01..Certain analog functions such as certain regulators left up. XtalOsc=on, RCOsc=off; + * 0b10..XtalOsc=off, RCOsc=on, Old BG=on, New BG=off. + * 0b11..XtalOsc=off, RCOsc=on, Old BG=off, New BG=on. + */ #define CCM_ANALOG_MISC0_SET_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_STOP_MODE_CONFIG_SHIFT)) & CCM_ANALOG_MISC0_SET_STOP_MODE_CONFIG_MASK) #define CCM_ANALOG_MISC0_SET_DISCON_HIGH_SNVS_MASK (0x1000U) #define CCM_ANALOG_MISC0_SET_DISCON_HIGH_SNVS_SHIFT (12U) +/*! DISCON_HIGH_SNVS + * 0b0..Turn on the switch + * 0b1..Turn off the switch + */ #define CCM_ANALOG_MISC0_SET_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_DISCON_HIGH_SNVS_SHIFT)) & CCM_ANALOG_MISC0_SET_DISCON_HIGH_SNVS_MASK) #define CCM_ANALOG_MISC0_SET_OSC_I_MASK (0x6000U) #define CCM_ANALOG_MISC0_SET_OSC_I_SHIFT (13U) +/*! OSC_I + * 0b00..Nominal + * 0b01..Decrease current by 12.5% + * 0b10..Decrease current by 25.0% + * 0b11..Decrease current by 37.5% + */ #define CCM_ANALOG_MISC0_SET_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_OSC_I_SHIFT)) & CCM_ANALOG_MISC0_SET_OSC_I_MASK) #define CCM_ANALOG_MISC0_SET_OSC_XTALOK_MASK (0x8000U) #define CCM_ANALOG_MISC0_SET_OSC_XTALOK_SHIFT (15U) @@ -4902,41 +6908,88 @@ typedef struct { #define CCM_ANALOG_MISC0_SET_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_OSC_XTALOK_EN_SHIFT)) & CCM_ANALOG_MISC0_SET_OSC_XTALOK_EN_MASK) #define CCM_ANALOG_MISC0_SET_CLKGATE_CTRL_MASK (0x2000000U) #define CCM_ANALOG_MISC0_SET_CLKGATE_CTRL_SHIFT (25U) +/*! CLKGATE_CTRL + * 0b0..Allow the logic to automatically gate the clock when the XTAL is powered down. + * 0b1..Prevent the logic from ever gating off the clock. + */ #define CCM_ANALOG_MISC0_SET_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_CLKGATE_CTRL_SHIFT)) & CCM_ANALOG_MISC0_SET_CLKGATE_CTRL_MASK) #define CCM_ANALOG_MISC0_SET_CLKGATE_DELAY_MASK (0x1C000000U) #define CCM_ANALOG_MISC0_SET_CLKGATE_DELAY_SHIFT (26U) +/*! CLKGATE_DELAY + * 0b000..0.5ms + * 0b001..1.0ms + * 0b010..2.0ms + * 0b011..3.0ms + * 0b100..4.0ms + * 0b101..5.0ms + * 0b110..6.0ms + * 0b111..7.0ms + */ #define CCM_ANALOG_MISC0_SET_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_CLKGATE_DELAY_SHIFT)) & CCM_ANALOG_MISC0_SET_CLKGATE_DELAY_MASK) #define CCM_ANALOG_MISC0_SET_RTC_XTAL_SOURCE_MASK (0x20000000U) #define CCM_ANALOG_MISC0_SET_RTC_XTAL_SOURCE_SHIFT (29U) +/*! RTC_XTAL_SOURCE + * 0b0..Internal ring oscillator + * 0b1..RTC_XTAL + */ #define CCM_ANALOG_MISC0_SET_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_RTC_XTAL_SOURCE_SHIFT)) & CCM_ANALOG_MISC0_SET_RTC_XTAL_SOURCE_MASK) #define CCM_ANALOG_MISC0_SET_XTAL_24M_PWD_MASK (0x40000000U) #define CCM_ANALOG_MISC0_SET_XTAL_24M_PWD_SHIFT (30U) #define CCM_ANALOG_MISC0_SET_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_XTAL_24M_PWD_SHIFT)) & CCM_ANALOG_MISC0_SET_XTAL_24M_PWD_MASK) -#define CCM_ANALOG_MISC0_SET_VID_PLL_PREDIV_MASK (0x80000000U) -#define CCM_ANALOG_MISC0_SET_VID_PLL_PREDIV_SHIFT (31U) -#define CCM_ANALOG_MISC0_SET_VID_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_VID_PLL_PREDIV_SHIFT)) & CCM_ANALOG_MISC0_SET_VID_PLL_PREDIV_MASK) +/*! @} */ /*! @name MISC0_CLR - Miscellaneous Register 0 */ +/*! @{ */ #define CCM_ANALOG_MISC0_CLR_REFTOP_PWD_MASK (0x1U) #define CCM_ANALOG_MISC0_CLR_REFTOP_PWD_SHIFT (0U) #define CCM_ANALOG_MISC0_CLR_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_REFTOP_PWD_SHIFT)) & CCM_ANALOG_MISC0_CLR_REFTOP_PWD_MASK) #define CCM_ANALOG_MISC0_CLR_REFTOP_SELFBIASOFF_MASK (0x8U) #define CCM_ANALOG_MISC0_CLR_REFTOP_SELFBIASOFF_SHIFT (3U) +/*! REFTOP_SELFBIASOFF + * 0b0..Uses coarse bias currents for startup + * 0b1..Uses bandgap-based bias currents for best performance. + */ #define CCM_ANALOG_MISC0_CLR_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_REFTOP_SELFBIASOFF_SHIFT)) & CCM_ANALOG_MISC0_CLR_REFTOP_SELFBIASOFF_MASK) #define CCM_ANALOG_MISC0_CLR_REFTOP_VBGADJ_MASK (0x70U) #define CCM_ANALOG_MISC0_CLR_REFTOP_VBGADJ_SHIFT (4U) +/*! REFTOP_VBGADJ + * 0b000..Nominal VBG + * 0b001..VBG+0.78% + * 0b010..VBG+1.56% + * 0b011..VBG+2.34% + * 0b100..VBG-0.78% + * 0b101..VBG-1.56% + * 0b110..VBG-2.34% + * 0b111..VBG-3.12% + */ #define CCM_ANALOG_MISC0_CLR_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_REFTOP_VBGADJ_SHIFT)) & CCM_ANALOG_MISC0_CLR_REFTOP_VBGADJ_MASK) #define CCM_ANALOG_MISC0_CLR_REFTOP_VBGUP_MASK (0x80U) #define CCM_ANALOG_MISC0_CLR_REFTOP_VBGUP_SHIFT (7U) #define CCM_ANALOG_MISC0_CLR_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_REFTOP_VBGUP_SHIFT)) & CCM_ANALOG_MISC0_CLR_REFTOP_VBGUP_MASK) #define CCM_ANALOG_MISC0_CLR_STOP_MODE_CONFIG_MASK (0xC00U) #define CCM_ANALOG_MISC0_CLR_STOP_MODE_CONFIG_SHIFT (10U) +/*! STOP_MODE_CONFIG + * 0b00..All analog except rtc powered down on stop mode assertion. XtalOsc=on, RCOsc=off; + * 0b01..Certain analog functions such as certain regulators left up. XtalOsc=on, RCOsc=off; + * 0b10..XtalOsc=off, RCOsc=on, Old BG=on, New BG=off. + * 0b11..XtalOsc=off, RCOsc=on, Old BG=off, New BG=on. + */ #define CCM_ANALOG_MISC0_CLR_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_STOP_MODE_CONFIG_SHIFT)) & CCM_ANALOG_MISC0_CLR_STOP_MODE_CONFIG_MASK) #define CCM_ANALOG_MISC0_CLR_DISCON_HIGH_SNVS_MASK (0x1000U) #define CCM_ANALOG_MISC0_CLR_DISCON_HIGH_SNVS_SHIFT (12U) +/*! DISCON_HIGH_SNVS + * 0b0..Turn on the switch + * 0b1..Turn off the switch + */ #define CCM_ANALOG_MISC0_CLR_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_DISCON_HIGH_SNVS_SHIFT)) & CCM_ANALOG_MISC0_CLR_DISCON_HIGH_SNVS_MASK) #define CCM_ANALOG_MISC0_CLR_OSC_I_MASK (0x6000U) #define CCM_ANALOG_MISC0_CLR_OSC_I_SHIFT (13U) +/*! OSC_I + * 0b00..Nominal + * 0b01..Decrease current by 12.5% + * 0b10..Decrease current by 25.0% + * 0b11..Decrease current by 37.5% + */ #define CCM_ANALOG_MISC0_CLR_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_OSC_I_SHIFT)) & CCM_ANALOG_MISC0_CLR_OSC_I_MASK) #define CCM_ANALOG_MISC0_CLR_OSC_XTALOK_MASK (0x8000U) #define CCM_ANALOG_MISC0_CLR_OSC_XTALOK_SHIFT (15U) @@ -4946,41 +6999,88 @@ typedef struct { #define CCM_ANALOG_MISC0_CLR_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_OSC_XTALOK_EN_SHIFT)) & CCM_ANALOG_MISC0_CLR_OSC_XTALOK_EN_MASK) #define CCM_ANALOG_MISC0_CLR_CLKGATE_CTRL_MASK (0x2000000U) #define CCM_ANALOG_MISC0_CLR_CLKGATE_CTRL_SHIFT (25U) +/*! CLKGATE_CTRL + * 0b0..Allow the logic to automatically gate the clock when the XTAL is powered down. + * 0b1..Prevent the logic from ever gating off the clock. + */ #define CCM_ANALOG_MISC0_CLR_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_CLKGATE_CTRL_SHIFT)) & CCM_ANALOG_MISC0_CLR_CLKGATE_CTRL_MASK) #define CCM_ANALOG_MISC0_CLR_CLKGATE_DELAY_MASK (0x1C000000U) #define CCM_ANALOG_MISC0_CLR_CLKGATE_DELAY_SHIFT (26U) +/*! CLKGATE_DELAY + * 0b000..0.5ms + * 0b001..1.0ms + * 0b010..2.0ms + * 0b011..3.0ms + * 0b100..4.0ms + * 0b101..5.0ms + * 0b110..6.0ms + * 0b111..7.0ms + */ #define CCM_ANALOG_MISC0_CLR_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_CLKGATE_DELAY_SHIFT)) & CCM_ANALOG_MISC0_CLR_CLKGATE_DELAY_MASK) #define CCM_ANALOG_MISC0_CLR_RTC_XTAL_SOURCE_MASK (0x20000000U) #define CCM_ANALOG_MISC0_CLR_RTC_XTAL_SOURCE_SHIFT (29U) +/*! RTC_XTAL_SOURCE + * 0b0..Internal ring oscillator + * 0b1..RTC_XTAL + */ #define CCM_ANALOG_MISC0_CLR_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_RTC_XTAL_SOURCE_SHIFT)) & CCM_ANALOG_MISC0_CLR_RTC_XTAL_SOURCE_MASK) #define CCM_ANALOG_MISC0_CLR_XTAL_24M_PWD_MASK (0x40000000U) #define CCM_ANALOG_MISC0_CLR_XTAL_24M_PWD_SHIFT (30U) #define CCM_ANALOG_MISC0_CLR_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_XTAL_24M_PWD_SHIFT)) & CCM_ANALOG_MISC0_CLR_XTAL_24M_PWD_MASK) -#define CCM_ANALOG_MISC0_CLR_VID_PLL_PREDIV_MASK (0x80000000U) -#define CCM_ANALOG_MISC0_CLR_VID_PLL_PREDIV_SHIFT (31U) -#define CCM_ANALOG_MISC0_CLR_VID_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_VID_PLL_PREDIV_SHIFT)) & CCM_ANALOG_MISC0_CLR_VID_PLL_PREDIV_MASK) +/*! @} */ /*! @name MISC0_TOG - Miscellaneous Register 0 */ +/*! @{ */ #define CCM_ANALOG_MISC0_TOG_REFTOP_PWD_MASK (0x1U) #define CCM_ANALOG_MISC0_TOG_REFTOP_PWD_SHIFT (0U) #define CCM_ANALOG_MISC0_TOG_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_REFTOP_PWD_SHIFT)) & CCM_ANALOG_MISC0_TOG_REFTOP_PWD_MASK) #define CCM_ANALOG_MISC0_TOG_REFTOP_SELFBIASOFF_MASK (0x8U) #define CCM_ANALOG_MISC0_TOG_REFTOP_SELFBIASOFF_SHIFT (3U) +/*! REFTOP_SELFBIASOFF + * 0b0..Uses coarse bias currents for startup + * 0b1..Uses bandgap-based bias currents for best performance. + */ #define CCM_ANALOG_MISC0_TOG_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_REFTOP_SELFBIASOFF_SHIFT)) & CCM_ANALOG_MISC0_TOG_REFTOP_SELFBIASOFF_MASK) #define CCM_ANALOG_MISC0_TOG_REFTOP_VBGADJ_MASK (0x70U) #define CCM_ANALOG_MISC0_TOG_REFTOP_VBGADJ_SHIFT (4U) +/*! REFTOP_VBGADJ + * 0b000..Nominal VBG + * 0b001..VBG+0.78% + * 0b010..VBG+1.56% + * 0b011..VBG+2.34% + * 0b100..VBG-0.78% + * 0b101..VBG-1.56% + * 0b110..VBG-2.34% + * 0b111..VBG-3.12% + */ #define CCM_ANALOG_MISC0_TOG_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_REFTOP_VBGADJ_SHIFT)) & CCM_ANALOG_MISC0_TOG_REFTOP_VBGADJ_MASK) #define CCM_ANALOG_MISC0_TOG_REFTOP_VBGUP_MASK (0x80U) #define CCM_ANALOG_MISC0_TOG_REFTOP_VBGUP_SHIFT (7U) #define CCM_ANALOG_MISC0_TOG_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_REFTOP_VBGUP_SHIFT)) & CCM_ANALOG_MISC0_TOG_REFTOP_VBGUP_MASK) #define CCM_ANALOG_MISC0_TOG_STOP_MODE_CONFIG_MASK (0xC00U) #define CCM_ANALOG_MISC0_TOG_STOP_MODE_CONFIG_SHIFT (10U) +/*! STOP_MODE_CONFIG + * 0b00..All analog except rtc powered down on stop mode assertion. XtalOsc=on, RCOsc=off; + * 0b01..Certain analog functions such as certain regulators left up. XtalOsc=on, RCOsc=off; + * 0b10..XtalOsc=off, RCOsc=on, Old BG=on, New BG=off. + * 0b11..XtalOsc=off, RCOsc=on, Old BG=off, New BG=on. + */ #define CCM_ANALOG_MISC0_TOG_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_STOP_MODE_CONFIG_SHIFT)) & CCM_ANALOG_MISC0_TOG_STOP_MODE_CONFIG_MASK) #define CCM_ANALOG_MISC0_TOG_DISCON_HIGH_SNVS_MASK (0x1000U) #define CCM_ANALOG_MISC0_TOG_DISCON_HIGH_SNVS_SHIFT (12U) +/*! DISCON_HIGH_SNVS + * 0b0..Turn on the switch + * 0b1..Turn off the switch + */ #define CCM_ANALOG_MISC0_TOG_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_DISCON_HIGH_SNVS_SHIFT)) & CCM_ANALOG_MISC0_TOG_DISCON_HIGH_SNVS_MASK) #define CCM_ANALOG_MISC0_TOG_OSC_I_MASK (0x6000U) #define CCM_ANALOG_MISC0_TOG_OSC_I_SHIFT (13U) +/*! OSC_I + * 0b00..Nominal + * 0b01..Decrease current by 12.5% + * 0b10..Decrease current by 25.0% + * 0b11..Decrease current by 37.5% + */ #define CCM_ANALOG_MISC0_TOG_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_OSC_I_SHIFT)) & CCM_ANALOG_MISC0_TOG_OSC_I_MASK) #define CCM_ANALOG_MISC0_TOG_OSC_XTALOK_MASK (0x8000U) #define CCM_ANALOG_MISC0_TOG_OSC_XTALOK_SHIFT (15U) @@ -4990,23 +7090,58 @@ typedef struct { #define CCM_ANALOG_MISC0_TOG_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_OSC_XTALOK_EN_SHIFT)) & CCM_ANALOG_MISC0_TOG_OSC_XTALOK_EN_MASK) #define CCM_ANALOG_MISC0_TOG_CLKGATE_CTRL_MASK (0x2000000U) #define CCM_ANALOG_MISC0_TOG_CLKGATE_CTRL_SHIFT (25U) +/*! CLKGATE_CTRL + * 0b0..Allow the logic to automatically gate the clock when the XTAL is powered down. + * 0b1..Prevent the logic from ever gating off the clock. + */ #define CCM_ANALOG_MISC0_TOG_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_CLKGATE_CTRL_SHIFT)) & CCM_ANALOG_MISC0_TOG_CLKGATE_CTRL_MASK) #define CCM_ANALOG_MISC0_TOG_CLKGATE_DELAY_MASK (0x1C000000U) #define CCM_ANALOG_MISC0_TOG_CLKGATE_DELAY_SHIFT (26U) +/*! CLKGATE_DELAY + * 0b000..0.5ms + * 0b001..1.0ms + * 0b010..2.0ms + * 0b011..3.0ms + * 0b100..4.0ms + * 0b101..5.0ms + * 0b110..6.0ms + * 0b111..7.0ms + */ #define CCM_ANALOG_MISC0_TOG_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_CLKGATE_DELAY_SHIFT)) & CCM_ANALOG_MISC0_TOG_CLKGATE_DELAY_MASK) #define CCM_ANALOG_MISC0_TOG_RTC_XTAL_SOURCE_MASK (0x20000000U) #define CCM_ANALOG_MISC0_TOG_RTC_XTAL_SOURCE_SHIFT (29U) +/*! RTC_XTAL_SOURCE + * 0b0..Internal ring oscillator + * 0b1..RTC_XTAL + */ #define CCM_ANALOG_MISC0_TOG_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_RTC_XTAL_SOURCE_SHIFT)) & CCM_ANALOG_MISC0_TOG_RTC_XTAL_SOURCE_MASK) #define CCM_ANALOG_MISC0_TOG_XTAL_24M_PWD_MASK (0x40000000U) #define CCM_ANALOG_MISC0_TOG_XTAL_24M_PWD_SHIFT (30U) #define CCM_ANALOG_MISC0_TOG_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_XTAL_24M_PWD_SHIFT)) & CCM_ANALOG_MISC0_TOG_XTAL_24M_PWD_MASK) -#define CCM_ANALOG_MISC0_TOG_VID_PLL_PREDIV_MASK (0x80000000U) -#define CCM_ANALOG_MISC0_TOG_VID_PLL_PREDIV_SHIFT (31U) -#define CCM_ANALOG_MISC0_TOG_VID_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_VID_PLL_PREDIV_SHIFT)) & CCM_ANALOG_MISC0_TOG_VID_PLL_PREDIV_MASK) +/*! @} */ /*! @name MISC1 - Miscellaneous Register 1 */ +/*! @{ */ #define CCM_ANALOG_MISC1_LVDS1_CLK_SEL_MASK (0x1FU) #define CCM_ANALOG_MISC1_LVDS1_CLK_SEL_SHIFT (0U) +/*! LVDS1_CLK_SEL + * 0b00000..Arm PLL + * 0b00001..System PLL + * 0b00010..ref_pfd4_clk == pll2_pfd0_clk + * 0b00011..ref_pfd5_clk == pll2_pfd1_clk + * 0b00100..ref_pfd6_clk == pll2_pfd2_clk + * 0b00101..ref_pfd7_clk == pll2_pfd3_clk + * 0b00110..Audio PLL + * 0b00111..Video PLL + * 0b01001..ethernet ref clock (ENET_PLL) + * 0b01100..USB1 PLL clock + * 0b01101..USB2 PLL clock + * 0b01110..ref_pfd0_clk == pll3_pfd0_clk + * 0b01111..ref_pfd1_clk == pll3_pfd1_clk + * 0b10000..ref_pfd2_clk == pll3_pfd2_clk + * 0b10001..ref_pfd3_clk == pll3_pfd3_clk + * 0b10010..xtal (24M) + */ #define CCM_ANALOG_MISC1_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_LVDS1_CLK_SEL_SHIFT)) & CCM_ANALOG_MISC1_LVDS1_CLK_SEL_MASK) #define CCM_ANALOG_MISC1_LVDSCLK1_OBEN_MASK (0x400U) #define CCM_ANALOG_MISC1_LVDSCLK1_OBEN_SHIFT (10U) @@ -5035,10 +7170,30 @@ typedef struct { #define CCM_ANALOG_MISC1_IRQ_DIG_BO_MASK (0x80000000U) #define CCM_ANALOG_MISC1_IRQ_DIG_BO_SHIFT (31U) #define CCM_ANALOG_MISC1_IRQ_DIG_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_IRQ_DIG_BO_SHIFT)) & CCM_ANALOG_MISC1_IRQ_DIG_BO_MASK) +/*! @} */ /*! @name MISC1_SET - Miscellaneous Register 1 */ +/*! @{ */ #define CCM_ANALOG_MISC1_SET_LVDS1_CLK_SEL_MASK (0x1FU) #define CCM_ANALOG_MISC1_SET_LVDS1_CLK_SEL_SHIFT (0U) +/*! LVDS1_CLK_SEL + * 0b00000..Arm PLL + * 0b00001..System PLL + * 0b00010..ref_pfd4_clk == pll2_pfd0_clk + * 0b00011..ref_pfd5_clk == pll2_pfd1_clk + * 0b00100..ref_pfd6_clk == pll2_pfd2_clk + * 0b00101..ref_pfd7_clk == pll2_pfd3_clk + * 0b00110..Audio PLL + * 0b00111..Video PLL + * 0b01001..ethernet ref clock (ENET_PLL) + * 0b01100..USB1 PLL clock + * 0b01101..USB2 PLL clock + * 0b01110..ref_pfd0_clk == pll3_pfd0_clk + * 0b01111..ref_pfd1_clk == pll3_pfd1_clk + * 0b10000..ref_pfd2_clk == pll3_pfd2_clk + * 0b10001..ref_pfd3_clk == pll3_pfd3_clk + * 0b10010..xtal (24M) + */ #define CCM_ANALOG_MISC1_SET_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_LVDS1_CLK_SEL_SHIFT)) & CCM_ANALOG_MISC1_SET_LVDS1_CLK_SEL_MASK) #define CCM_ANALOG_MISC1_SET_LVDSCLK1_OBEN_MASK (0x400U) #define CCM_ANALOG_MISC1_SET_LVDSCLK1_OBEN_SHIFT (10U) @@ -5067,10 +7222,30 @@ typedef struct { #define CCM_ANALOG_MISC1_SET_IRQ_DIG_BO_MASK (0x80000000U) #define CCM_ANALOG_MISC1_SET_IRQ_DIG_BO_SHIFT (31U) #define CCM_ANALOG_MISC1_SET_IRQ_DIG_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_IRQ_DIG_BO_SHIFT)) & CCM_ANALOG_MISC1_SET_IRQ_DIG_BO_MASK) +/*! @} */ /*! @name MISC1_CLR - Miscellaneous Register 1 */ +/*! @{ */ #define CCM_ANALOG_MISC1_CLR_LVDS1_CLK_SEL_MASK (0x1FU) #define CCM_ANALOG_MISC1_CLR_LVDS1_CLK_SEL_SHIFT (0U) +/*! LVDS1_CLK_SEL + * 0b00000..Arm PLL + * 0b00001..System PLL + * 0b00010..ref_pfd4_clk == pll2_pfd0_clk + * 0b00011..ref_pfd5_clk == pll2_pfd1_clk + * 0b00100..ref_pfd6_clk == pll2_pfd2_clk + * 0b00101..ref_pfd7_clk == pll2_pfd3_clk + * 0b00110..Audio PLL + * 0b00111..Video PLL + * 0b01001..ethernet ref clock (ENET_PLL) + * 0b01100..USB1 PLL clock + * 0b01101..USB2 PLL clock + * 0b01110..ref_pfd0_clk == pll3_pfd0_clk + * 0b01111..ref_pfd1_clk == pll3_pfd1_clk + * 0b10000..ref_pfd2_clk == pll3_pfd2_clk + * 0b10001..ref_pfd3_clk == pll3_pfd3_clk + * 0b10010..xtal (24M) + */ #define CCM_ANALOG_MISC1_CLR_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_LVDS1_CLK_SEL_SHIFT)) & CCM_ANALOG_MISC1_CLR_LVDS1_CLK_SEL_MASK) #define CCM_ANALOG_MISC1_CLR_LVDSCLK1_OBEN_MASK (0x400U) #define CCM_ANALOG_MISC1_CLR_LVDSCLK1_OBEN_SHIFT (10U) @@ -5099,10 +7274,30 @@ typedef struct { #define CCM_ANALOG_MISC1_CLR_IRQ_DIG_BO_MASK (0x80000000U) #define CCM_ANALOG_MISC1_CLR_IRQ_DIG_BO_SHIFT (31U) #define CCM_ANALOG_MISC1_CLR_IRQ_DIG_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_IRQ_DIG_BO_SHIFT)) & CCM_ANALOG_MISC1_CLR_IRQ_DIG_BO_MASK) +/*! @} */ /*! @name MISC1_TOG - Miscellaneous Register 1 */ +/*! @{ */ #define CCM_ANALOG_MISC1_TOG_LVDS1_CLK_SEL_MASK (0x1FU) #define CCM_ANALOG_MISC1_TOG_LVDS1_CLK_SEL_SHIFT (0U) +/*! LVDS1_CLK_SEL + * 0b00000..Arm PLL + * 0b00001..System PLL + * 0b00010..ref_pfd4_clk == pll2_pfd0_clk + * 0b00011..ref_pfd5_clk == pll2_pfd1_clk + * 0b00100..ref_pfd6_clk == pll2_pfd2_clk + * 0b00101..ref_pfd7_clk == pll2_pfd3_clk + * 0b00110..Audio PLL + * 0b00111..Video PLL + * 0b01001..ethernet ref clock (ENET_PLL) + * 0b01100..USB1 PLL clock + * 0b01101..USB2 PLL clock + * 0b01110..ref_pfd0_clk == pll3_pfd0_clk + * 0b01111..ref_pfd1_clk == pll3_pfd1_clk + * 0b10000..ref_pfd2_clk == pll3_pfd2_clk + * 0b10001..ref_pfd3_clk == pll3_pfd3_clk + * 0b10010..xtal (24M) + */ #define CCM_ANALOG_MISC1_TOG_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_LVDS1_CLK_SEL_SHIFT)) & CCM_ANALOG_MISC1_TOG_LVDS1_CLK_SEL_MASK) #define CCM_ANALOG_MISC1_TOG_LVDSCLK1_OBEN_MASK (0x400U) #define CCM_ANALOG_MISC1_TOG_LVDSCLK1_OBEN_SHIFT (10U) @@ -5131,13 +7326,22 @@ typedef struct { #define CCM_ANALOG_MISC1_TOG_IRQ_DIG_BO_MASK (0x80000000U) #define CCM_ANALOG_MISC1_TOG_IRQ_DIG_BO_SHIFT (31U) #define CCM_ANALOG_MISC1_TOG_IRQ_DIG_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_IRQ_DIG_BO_SHIFT)) & CCM_ANALOG_MISC1_TOG_IRQ_DIG_BO_MASK) +/*! @} */ /*! @name MISC2 - Miscellaneous Register 2 */ +/*! @{ */ #define CCM_ANALOG_MISC2_REG0_BO_OFFSET_MASK (0x7U) #define CCM_ANALOG_MISC2_REG0_BO_OFFSET_SHIFT (0U) +/*! REG0_BO_OFFSET + * 0b100..Brownout offset = 0.100V + * 0b111..Brownout offset = 0.175V + */ #define CCM_ANALOG_MISC2_REG0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG0_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_REG0_BO_OFFSET_MASK) #define CCM_ANALOG_MISC2_REG0_BO_STATUS_MASK (0x8U) #define CCM_ANALOG_MISC2_REG0_BO_STATUS_SHIFT (3U) +/*! REG0_BO_STATUS + * 0b1..Brownout, supply is below target minus brownout offset. + */ #define CCM_ANALOG_MISC2_REG0_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG0_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_REG0_BO_STATUS_MASK) #define CCM_ANALOG_MISC2_REG0_ENABLE_BO_MASK (0x20U) #define CCM_ANALOG_MISC2_REG0_ENABLE_BO_SHIFT (5U) @@ -5147,12 +7351,23 @@ typedef struct { #define CCM_ANALOG_MISC2_REG0_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG0_OK_SHIFT)) & CCM_ANALOG_MISC2_REG0_OK_MASK) #define CCM_ANALOG_MISC2_PLL3_disable_MASK (0x80U) #define CCM_ANALOG_MISC2_PLL3_disable_SHIFT (7U) +/*! PLL3_disable + * 0b0..PLL3 is being used by peripherals and is enabled when SoC is not in any low power mode + * 0b1..PLL3 can be disabled when the SoC is not in any low power mode + */ #define CCM_ANALOG_MISC2_PLL3_disable(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_PLL3_disable_SHIFT)) & CCM_ANALOG_MISC2_PLL3_disable_MASK) #define CCM_ANALOG_MISC2_REG1_BO_OFFSET_MASK (0x700U) #define CCM_ANALOG_MISC2_REG1_BO_OFFSET_SHIFT (8U) +/*! REG1_BO_OFFSET + * 0b100..Brownout offset = 0.100V + * 0b111..Brownout offset = 0.175V + */ #define CCM_ANALOG_MISC2_REG1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG1_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_REG1_BO_OFFSET_MASK) #define CCM_ANALOG_MISC2_REG1_BO_STATUS_MASK (0x800U) #define CCM_ANALOG_MISC2_REG1_BO_STATUS_SHIFT (11U) +/*! REG1_BO_STATUS + * 0b1..Brownout, supply is below target minus brownout offset. + */ #define CCM_ANALOG_MISC2_REG1_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG1_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_REG1_BO_STATUS_MASK) #define CCM_ANALOG_MISC2_REG1_ENABLE_BO_MASK (0x2000U) #define CCM_ANALOG_MISC2_REG1_ENABLE_BO_SHIFT (13U) @@ -5162,9 +7377,17 @@ typedef struct { #define CCM_ANALOG_MISC2_REG1_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG1_OK_SHIFT)) & CCM_ANALOG_MISC2_REG1_OK_MASK) #define CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK (0x8000U) #define CCM_ANALOG_MISC2_AUDIO_DIV_LSB_SHIFT (15U) +/*! AUDIO_DIV_LSB + * 0b0..divide by 1 (Default) + * 0b1..divide by 2 + */ #define CCM_ANALOG_MISC2_AUDIO_DIV_LSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_AUDIO_DIV_LSB_SHIFT)) & CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK) #define CCM_ANALOG_MISC2_REG2_BO_OFFSET_MASK (0x70000U) #define CCM_ANALOG_MISC2_REG2_BO_OFFSET_SHIFT (16U) +/*! REG2_BO_OFFSET + * 0b100..Brownout offset = 0.100V + * 0b111..Brownout offset = 0.175V + */ #define CCM_ANALOG_MISC2_REG2_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG2_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_REG2_BO_OFFSET_MASK) #define CCM_ANALOG_MISC2_REG2_BO_STATUS_MASK (0x80000U) #define CCM_ANALOG_MISC2_REG2_BO_STATUS_SHIFT (19U) @@ -5177,26 +7400,63 @@ typedef struct { #define CCM_ANALOG_MISC2_REG2_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG2_OK_SHIFT)) & CCM_ANALOG_MISC2_REG2_OK_MASK) #define CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK (0x800000U) #define CCM_ANALOG_MISC2_AUDIO_DIV_MSB_SHIFT (23U) +/*! AUDIO_DIV_MSB + * 0b0..divide by 1 (Default) + * 0b1..divide by 2 + */ #define CCM_ANALOG_MISC2_AUDIO_DIV_MSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_AUDIO_DIV_MSB_SHIFT)) & CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK) #define CCM_ANALOG_MISC2_REG0_STEP_TIME_MASK (0x3000000U) #define CCM_ANALOG_MISC2_REG0_STEP_TIME_SHIFT (24U) +/*! REG0_STEP_TIME + * 0b00..64 + * 0b01..128 + * 0b10..256 + * 0b11..512 + */ #define CCM_ANALOG_MISC2_REG0_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG0_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_REG0_STEP_TIME_MASK) #define CCM_ANALOG_MISC2_REG1_STEP_TIME_MASK (0xC000000U) #define CCM_ANALOG_MISC2_REG1_STEP_TIME_SHIFT (26U) +/*! REG1_STEP_TIME + * 0b00..64 + * 0b01..128 + * 0b10..256 + * 0b11..512 + */ #define CCM_ANALOG_MISC2_REG1_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG1_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_REG1_STEP_TIME_MASK) #define CCM_ANALOG_MISC2_REG2_STEP_TIME_MASK (0x30000000U) #define CCM_ANALOG_MISC2_REG2_STEP_TIME_SHIFT (28U) +/*! REG2_STEP_TIME + * 0b00..64 + * 0b01..128 + * 0b10..256 + * 0b11..512 + */ #define CCM_ANALOG_MISC2_REG2_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG2_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_REG2_STEP_TIME_MASK) #define CCM_ANALOG_MISC2_VIDEO_DIV_MASK (0xC0000000U) #define CCM_ANALOG_MISC2_VIDEO_DIV_SHIFT (30U) +/*! VIDEO_DIV + * 0b00..divide by 1 (Default) + * 0b01..divide by 2 + * 0b10..divide by 1 + * 0b11..divide by 4 + */ #define CCM_ANALOG_MISC2_VIDEO_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_VIDEO_DIV_SHIFT)) & CCM_ANALOG_MISC2_VIDEO_DIV_MASK) +/*! @} */ /*! @name MISC2_SET - Miscellaneous Register 2 */ +/*! @{ */ #define CCM_ANALOG_MISC2_SET_REG0_BO_OFFSET_MASK (0x7U) #define CCM_ANALOG_MISC2_SET_REG0_BO_OFFSET_SHIFT (0U) +/*! REG0_BO_OFFSET + * 0b100..Brownout offset = 0.100V + * 0b111..Brownout offset = 0.175V + */ #define CCM_ANALOG_MISC2_SET_REG0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG0_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_SET_REG0_BO_OFFSET_MASK) #define CCM_ANALOG_MISC2_SET_REG0_BO_STATUS_MASK (0x8U) #define CCM_ANALOG_MISC2_SET_REG0_BO_STATUS_SHIFT (3U) +/*! REG0_BO_STATUS + * 0b1..Brownout, supply is below target minus brownout offset. + */ #define CCM_ANALOG_MISC2_SET_REG0_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG0_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_SET_REG0_BO_STATUS_MASK) #define CCM_ANALOG_MISC2_SET_REG0_ENABLE_BO_MASK (0x20U) #define CCM_ANALOG_MISC2_SET_REG0_ENABLE_BO_SHIFT (5U) @@ -5206,12 +7466,23 @@ typedef struct { #define CCM_ANALOG_MISC2_SET_REG0_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG0_OK_SHIFT)) & CCM_ANALOG_MISC2_SET_REG0_OK_MASK) #define CCM_ANALOG_MISC2_SET_PLL3_disable_MASK (0x80U) #define CCM_ANALOG_MISC2_SET_PLL3_disable_SHIFT (7U) +/*! PLL3_disable + * 0b0..PLL3 is being used by peripherals and is enabled when SoC is not in any low power mode + * 0b1..PLL3 can be disabled when the SoC is not in any low power mode + */ #define CCM_ANALOG_MISC2_SET_PLL3_disable(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_PLL3_disable_SHIFT)) & CCM_ANALOG_MISC2_SET_PLL3_disable_MASK) #define CCM_ANALOG_MISC2_SET_REG1_BO_OFFSET_MASK (0x700U) #define CCM_ANALOG_MISC2_SET_REG1_BO_OFFSET_SHIFT (8U) +/*! REG1_BO_OFFSET + * 0b100..Brownout offset = 0.100V + * 0b111..Brownout offset = 0.175V + */ #define CCM_ANALOG_MISC2_SET_REG1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG1_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_SET_REG1_BO_OFFSET_MASK) #define CCM_ANALOG_MISC2_SET_REG1_BO_STATUS_MASK (0x800U) #define CCM_ANALOG_MISC2_SET_REG1_BO_STATUS_SHIFT (11U) +/*! REG1_BO_STATUS + * 0b1..Brownout, supply is below target minus brownout offset. + */ #define CCM_ANALOG_MISC2_SET_REG1_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG1_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_SET_REG1_BO_STATUS_MASK) #define CCM_ANALOG_MISC2_SET_REG1_ENABLE_BO_MASK (0x2000U) #define CCM_ANALOG_MISC2_SET_REG1_ENABLE_BO_SHIFT (13U) @@ -5221,9 +7492,17 @@ typedef struct { #define CCM_ANALOG_MISC2_SET_REG1_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG1_OK_SHIFT)) & CCM_ANALOG_MISC2_SET_REG1_OK_MASK) #define CCM_ANALOG_MISC2_SET_AUDIO_DIV_LSB_MASK (0x8000U) #define CCM_ANALOG_MISC2_SET_AUDIO_DIV_LSB_SHIFT (15U) +/*! AUDIO_DIV_LSB + * 0b0..divide by 1 (Default) + * 0b1..divide by 2 + */ #define CCM_ANALOG_MISC2_SET_AUDIO_DIV_LSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_AUDIO_DIV_LSB_SHIFT)) & CCM_ANALOG_MISC2_SET_AUDIO_DIV_LSB_MASK) #define CCM_ANALOG_MISC2_SET_REG2_BO_OFFSET_MASK (0x70000U) #define CCM_ANALOG_MISC2_SET_REG2_BO_OFFSET_SHIFT (16U) +/*! REG2_BO_OFFSET + * 0b100..Brownout offset = 0.100V + * 0b111..Brownout offset = 0.175V + */ #define CCM_ANALOG_MISC2_SET_REG2_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG2_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_SET_REG2_BO_OFFSET_MASK) #define CCM_ANALOG_MISC2_SET_REG2_BO_STATUS_MASK (0x80000U) #define CCM_ANALOG_MISC2_SET_REG2_BO_STATUS_SHIFT (19U) @@ -5236,26 +7515,63 @@ typedef struct { #define CCM_ANALOG_MISC2_SET_REG2_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG2_OK_SHIFT)) & CCM_ANALOG_MISC2_SET_REG2_OK_MASK) #define CCM_ANALOG_MISC2_SET_AUDIO_DIV_MSB_MASK (0x800000U) #define CCM_ANALOG_MISC2_SET_AUDIO_DIV_MSB_SHIFT (23U) +/*! AUDIO_DIV_MSB + * 0b0..divide by 1 (Default) + * 0b1..divide by 2 + */ #define CCM_ANALOG_MISC2_SET_AUDIO_DIV_MSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_AUDIO_DIV_MSB_SHIFT)) & CCM_ANALOG_MISC2_SET_AUDIO_DIV_MSB_MASK) #define CCM_ANALOG_MISC2_SET_REG0_STEP_TIME_MASK (0x3000000U) #define CCM_ANALOG_MISC2_SET_REG0_STEP_TIME_SHIFT (24U) +/*! REG0_STEP_TIME + * 0b00..64 + * 0b01..128 + * 0b10..256 + * 0b11..512 + */ #define CCM_ANALOG_MISC2_SET_REG0_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG0_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_SET_REG0_STEP_TIME_MASK) #define CCM_ANALOG_MISC2_SET_REG1_STEP_TIME_MASK (0xC000000U) #define CCM_ANALOG_MISC2_SET_REG1_STEP_TIME_SHIFT (26U) +/*! REG1_STEP_TIME + * 0b00..64 + * 0b01..128 + * 0b10..256 + * 0b11..512 + */ #define CCM_ANALOG_MISC2_SET_REG1_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG1_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_SET_REG1_STEP_TIME_MASK) #define CCM_ANALOG_MISC2_SET_REG2_STEP_TIME_MASK (0x30000000U) #define CCM_ANALOG_MISC2_SET_REG2_STEP_TIME_SHIFT (28U) +/*! REG2_STEP_TIME + * 0b00..64 + * 0b01..128 + * 0b10..256 + * 0b11..512 + */ #define CCM_ANALOG_MISC2_SET_REG2_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG2_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_SET_REG2_STEP_TIME_MASK) #define CCM_ANALOG_MISC2_SET_VIDEO_DIV_MASK (0xC0000000U) #define CCM_ANALOG_MISC2_SET_VIDEO_DIV_SHIFT (30U) +/*! VIDEO_DIV + * 0b00..divide by 1 (Default) + * 0b01..divide by 2 + * 0b10..divide by 1 + * 0b11..divide by 4 + */ #define CCM_ANALOG_MISC2_SET_VIDEO_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_VIDEO_DIV_SHIFT)) & CCM_ANALOG_MISC2_SET_VIDEO_DIV_MASK) +/*! @} */ /*! @name MISC2_CLR - Miscellaneous Register 2 */ +/*! @{ */ #define CCM_ANALOG_MISC2_CLR_REG0_BO_OFFSET_MASK (0x7U) #define CCM_ANALOG_MISC2_CLR_REG0_BO_OFFSET_SHIFT (0U) +/*! REG0_BO_OFFSET + * 0b100..Brownout offset = 0.100V + * 0b111..Brownout offset = 0.175V + */ #define CCM_ANALOG_MISC2_CLR_REG0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG0_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG0_BO_OFFSET_MASK) #define CCM_ANALOG_MISC2_CLR_REG0_BO_STATUS_MASK (0x8U) #define CCM_ANALOG_MISC2_CLR_REG0_BO_STATUS_SHIFT (3U) +/*! REG0_BO_STATUS + * 0b1..Brownout, supply is below target minus brownout offset. + */ #define CCM_ANALOG_MISC2_CLR_REG0_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG0_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG0_BO_STATUS_MASK) #define CCM_ANALOG_MISC2_CLR_REG0_ENABLE_BO_MASK (0x20U) #define CCM_ANALOG_MISC2_CLR_REG0_ENABLE_BO_SHIFT (5U) @@ -5265,12 +7581,23 @@ typedef struct { #define CCM_ANALOG_MISC2_CLR_REG0_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG0_OK_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG0_OK_MASK) #define CCM_ANALOG_MISC2_CLR_PLL3_disable_MASK (0x80U) #define CCM_ANALOG_MISC2_CLR_PLL3_disable_SHIFT (7U) +/*! PLL3_disable + * 0b0..PLL3 is being used by peripherals and is enabled when SoC is not in any low power mode + * 0b1..PLL3 can be disabled when the SoC is not in any low power mode + */ #define CCM_ANALOG_MISC2_CLR_PLL3_disable(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_PLL3_disable_SHIFT)) & CCM_ANALOG_MISC2_CLR_PLL3_disable_MASK) #define CCM_ANALOG_MISC2_CLR_REG1_BO_OFFSET_MASK (0x700U) #define CCM_ANALOG_MISC2_CLR_REG1_BO_OFFSET_SHIFT (8U) +/*! REG1_BO_OFFSET + * 0b100..Brownout offset = 0.100V + * 0b111..Brownout offset = 0.175V + */ #define CCM_ANALOG_MISC2_CLR_REG1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG1_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG1_BO_OFFSET_MASK) #define CCM_ANALOG_MISC2_CLR_REG1_BO_STATUS_MASK (0x800U) #define CCM_ANALOG_MISC2_CLR_REG1_BO_STATUS_SHIFT (11U) +/*! REG1_BO_STATUS + * 0b1..Brownout, supply is below target minus brownout offset. + */ #define CCM_ANALOG_MISC2_CLR_REG1_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG1_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG1_BO_STATUS_MASK) #define CCM_ANALOG_MISC2_CLR_REG1_ENABLE_BO_MASK (0x2000U) #define CCM_ANALOG_MISC2_CLR_REG1_ENABLE_BO_SHIFT (13U) @@ -5280,9 +7607,17 @@ typedef struct { #define CCM_ANALOG_MISC2_CLR_REG1_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG1_OK_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG1_OK_MASK) #define CCM_ANALOG_MISC2_CLR_AUDIO_DIV_LSB_MASK (0x8000U) #define CCM_ANALOG_MISC2_CLR_AUDIO_DIV_LSB_SHIFT (15U) +/*! AUDIO_DIV_LSB + * 0b0..divide by 1 (Default) + * 0b1..divide by 2 + */ #define CCM_ANALOG_MISC2_CLR_AUDIO_DIV_LSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_AUDIO_DIV_LSB_SHIFT)) & CCM_ANALOG_MISC2_CLR_AUDIO_DIV_LSB_MASK) #define CCM_ANALOG_MISC2_CLR_REG2_BO_OFFSET_MASK (0x70000U) #define CCM_ANALOG_MISC2_CLR_REG2_BO_OFFSET_SHIFT (16U) +/*! REG2_BO_OFFSET + * 0b100..Brownout offset = 0.100V + * 0b111..Brownout offset = 0.175V + */ #define CCM_ANALOG_MISC2_CLR_REG2_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG2_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG2_BO_OFFSET_MASK) #define CCM_ANALOG_MISC2_CLR_REG2_BO_STATUS_MASK (0x80000U) #define CCM_ANALOG_MISC2_CLR_REG2_BO_STATUS_SHIFT (19U) @@ -5295,26 +7630,63 @@ typedef struct { #define CCM_ANALOG_MISC2_CLR_REG2_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG2_OK_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG2_OK_MASK) #define CCM_ANALOG_MISC2_CLR_AUDIO_DIV_MSB_MASK (0x800000U) #define CCM_ANALOG_MISC2_CLR_AUDIO_DIV_MSB_SHIFT (23U) +/*! AUDIO_DIV_MSB + * 0b0..divide by 1 (Default) + * 0b1..divide by 2 + */ #define CCM_ANALOG_MISC2_CLR_AUDIO_DIV_MSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_AUDIO_DIV_MSB_SHIFT)) & CCM_ANALOG_MISC2_CLR_AUDIO_DIV_MSB_MASK) #define CCM_ANALOG_MISC2_CLR_REG0_STEP_TIME_MASK (0x3000000U) #define CCM_ANALOG_MISC2_CLR_REG0_STEP_TIME_SHIFT (24U) +/*! REG0_STEP_TIME + * 0b00..64 + * 0b01..128 + * 0b10..256 + * 0b11..512 + */ #define CCM_ANALOG_MISC2_CLR_REG0_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG0_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG0_STEP_TIME_MASK) #define CCM_ANALOG_MISC2_CLR_REG1_STEP_TIME_MASK (0xC000000U) #define CCM_ANALOG_MISC2_CLR_REG1_STEP_TIME_SHIFT (26U) +/*! REG1_STEP_TIME + * 0b00..64 + * 0b01..128 + * 0b10..256 + * 0b11..512 + */ #define CCM_ANALOG_MISC2_CLR_REG1_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG1_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG1_STEP_TIME_MASK) #define CCM_ANALOG_MISC2_CLR_REG2_STEP_TIME_MASK (0x30000000U) #define CCM_ANALOG_MISC2_CLR_REG2_STEP_TIME_SHIFT (28U) +/*! REG2_STEP_TIME + * 0b00..64 + * 0b01..128 + * 0b10..256 + * 0b11..512 + */ #define CCM_ANALOG_MISC2_CLR_REG2_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG2_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG2_STEP_TIME_MASK) #define CCM_ANALOG_MISC2_CLR_VIDEO_DIV_MASK (0xC0000000U) #define CCM_ANALOG_MISC2_CLR_VIDEO_DIV_SHIFT (30U) +/*! VIDEO_DIV + * 0b00..divide by 1 (Default) + * 0b01..divide by 2 + * 0b10..divide by 1 + * 0b11..divide by 4 + */ #define CCM_ANALOG_MISC2_CLR_VIDEO_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_VIDEO_DIV_SHIFT)) & CCM_ANALOG_MISC2_CLR_VIDEO_DIV_MASK) +/*! @} */ /*! @name MISC2_TOG - Miscellaneous Register 2 */ +/*! @{ */ #define CCM_ANALOG_MISC2_TOG_REG0_BO_OFFSET_MASK (0x7U) #define CCM_ANALOG_MISC2_TOG_REG0_BO_OFFSET_SHIFT (0U) +/*! REG0_BO_OFFSET + * 0b100..Brownout offset = 0.100V + * 0b111..Brownout offset = 0.175V + */ #define CCM_ANALOG_MISC2_TOG_REG0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG0_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG0_BO_OFFSET_MASK) #define CCM_ANALOG_MISC2_TOG_REG0_BO_STATUS_MASK (0x8U) #define CCM_ANALOG_MISC2_TOG_REG0_BO_STATUS_SHIFT (3U) +/*! REG0_BO_STATUS + * 0b1..Brownout, supply is below target minus brownout offset. + */ #define CCM_ANALOG_MISC2_TOG_REG0_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG0_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG0_BO_STATUS_MASK) #define CCM_ANALOG_MISC2_TOG_REG0_ENABLE_BO_MASK (0x20U) #define CCM_ANALOG_MISC2_TOG_REG0_ENABLE_BO_SHIFT (5U) @@ -5324,12 +7696,23 @@ typedef struct { #define CCM_ANALOG_MISC2_TOG_REG0_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG0_OK_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG0_OK_MASK) #define CCM_ANALOG_MISC2_TOG_PLL3_disable_MASK (0x80U) #define CCM_ANALOG_MISC2_TOG_PLL3_disable_SHIFT (7U) +/*! PLL3_disable + * 0b0..PLL3 is being used by peripherals and is enabled when SoC is not in any low power mode + * 0b1..PLL3 can be disabled when the SoC is not in any low power mode + */ #define CCM_ANALOG_MISC2_TOG_PLL3_disable(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_PLL3_disable_SHIFT)) & CCM_ANALOG_MISC2_TOG_PLL3_disable_MASK) #define CCM_ANALOG_MISC2_TOG_REG1_BO_OFFSET_MASK (0x700U) #define CCM_ANALOG_MISC2_TOG_REG1_BO_OFFSET_SHIFT (8U) +/*! REG1_BO_OFFSET + * 0b100..Brownout offset = 0.100V + * 0b111..Brownout offset = 0.175V + */ #define CCM_ANALOG_MISC2_TOG_REG1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG1_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG1_BO_OFFSET_MASK) #define CCM_ANALOG_MISC2_TOG_REG1_BO_STATUS_MASK (0x800U) #define CCM_ANALOG_MISC2_TOG_REG1_BO_STATUS_SHIFT (11U) +/*! REG1_BO_STATUS + * 0b1..Brownout, supply is below target minus brownout offset. + */ #define CCM_ANALOG_MISC2_TOG_REG1_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG1_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG1_BO_STATUS_MASK) #define CCM_ANALOG_MISC2_TOG_REG1_ENABLE_BO_MASK (0x2000U) #define CCM_ANALOG_MISC2_TOG_REG1_ENABLE_BO_SHIFT (13U) @@ -5339,9 +7722,17 @@ typedef struct { #define CCM_ANALOG_MISC2_TOG_REG1_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG1_OK_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG1_OK_MASK) #define CCM_ANALOG_MISC2_TOG_AUDIO_DIV_LSB_MASK (0x8000U) #define CCM_ANALOG_MISC2_TOG_AUDIO_DIV_LSB_SHIFT (15U) +/*! AUDIO_DIV_LSB + * 0b0..divide by 1 (Default) + * 0b1..divide by 2 + */ #define CCM_ANALOG_MISC2_TOG_AUDIO_DIV_LSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_AUDIO_DIV_LSB_SHIFT)) & CCM_ANALOG_MISC2_TOG_AUDIO_DIV_LSB_MASK) #define CCM_ANALOG_MISC2_TOG_REG2_BO_OFFSET_MASK (0x70000U) #define CCM_ANALOG_MISC2_TOG_REG2_BO_OFFSET_SHIFT (16U) +/*! REG2_BO_OFFSET + * 0b100..Brownout offset = 0.100V + * 0b111..Brownout offset = 0.175V + */ #define CCM_ANALOG_MISC2_TOG_REG2_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG2_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG2_BO_OFFSET_MASK) #define CCM_ANALOG_MISC2_TOG_REG2_BO_STATUS_MASK (0x80000U) #define CCM_ANALOG_MISC2_TOG_REG2_BO_STATUS_SHIFT (19U) @@ -5354,19 +7745,48 @@ typedef struct { #define CCM_ANALOG_MISC2_TOG_REG2_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG2_OK_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG2_OK_MASK) #define CCM_ANALOG_MISC2_TOG_AUDIO_DIV_MSB_MASK (0x800000U) #define CCM_ANALOG_MISC2_TOG_AUDIO_DIV_MSB_SHIFT (23U) +/*! AUDIO_DIV_MSB + * 0b0..divide by 1 (Default) + * 0b1..divide by 2 + */ #define CCM_ANALOG_MISC2_TOG_AUDIO_DIV_MSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_AUDIO_DIV_MSB_SHIFT)) & CCM_ANALOG_MISC2_TOG_AUDIO_DIV_MSB_MASK) #define CCM_ANALOG_MISC2_TOG_REG0_STEP_TIME_MASK (0x3000000U) #define CCM_ANALOG_MISC2_TOG_REG0_STEP_TIME_SHIFT (24U) +/*! REG0_STEP_TIME + * 0b00..64 + * 0b01..128 + * 0b10..256 + * 0b11..512 + */ #define CCM_ANALOG_MISC2_TOG_REG0_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG0_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG0_STEP_TIME_MASK) #define CCM_ANALOG_MISC2_TOG_REG1_STEP_TIME_MASK (0xC000000U) #define CCM_ANALOG_MISC2_TOG_REG1_STEP_TIME_SHIFT (26U) +/*! REG1_STEP_TIME + * 0b00..64 + * 0b01..128 + * 0b10..256 + * 0b11..512 + */ #define CCM_ANALOG_MISC2_TOG_REG1_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG1_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG1_STEP_TIME_MASK) #define CCM_ANALOG_MISC2_TOG_REG2_STEP_TIME_MASK (0x30000000U) #define CCM_ANALOG_MISC2_TOG_REG2_STEP_TIME_SHIFT (28U) +/*! REG2_STEP_TIME + * 0b00..64 + * 0b01..128 + * 0b10..256 + * 0b11..512 + */ #define CCM_ANALOG_MISC2_TOG_REG2_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG2_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG2_STEP_TIME_MASK) #define CCM_ANALOG_MISC2_TOG_VIDEO_DIV_MASK (0xC0000000U) #define CCM_ANALOG_MISC2_TOG_VIDEO_DIV_SHIFT (30U) +/*! VIDEO_DIV + * 0b00..divide by 1 (Default) + * 0b01..divide by 2 + * 0b10..divide by 1 + * 0b11..divide by 4 + */ #define CCM_ANALOG_MISC2_TOG_VIDEO_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_VIDEO_DIV_SHIFT)) & CCM_ANALOG_MISC2_TOG_VIDEO_DIV_MASK) +/*! @} */ /*! @@ -5418,79 +7838,183 @@ typedef struct { */ /*! @name CR0 - CMP Control Register 0 */ +/*! @{ */ #define CMP_CR0_HYSTCTR_MASK (0x3U) #define CMP_CR0_HYSTCTR_SHIFT (0U) +/*! HYSTCTR - Comparator hard block hysteresis control + * 0b00..Level 0 + * 0b01..Level 1 + * 0b10..Level 2 + * 0b11..Level 3 + */ #define CMP_CR0_HYSTCTR(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR0_HYSTCTR_SHIFT)) & CMP_CR0_HYSTCTR_MASK) #define CMP_CR0_FILTER_CNT_MASK (0x70U) #define CMP_CR0_FILTER_CNT_SHIFT (4U) +/*! FILTER_CNT - Filter Sample Count + * 0b000..Filter is disabled. If SE = 1, then COUT is a logic 0. This is not a legal state, and is not recommended. If SE = 0, COUT = COUTA. + * 0b001..One sample must agree. The comparator output is simply sampled. + * 0b010..2 consecutive samples must agree. + * 0b011..3 consecutive samples must agree. + * 0b100..4 consecutive samples must agree. + * 0b101..5 consecutive samples must agree. + * 0b110..6 consecutive samples must agree. + * 0b111..7 consecutive samples must agree. + */ #define CMP_CR0_FILTER_CNT(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR0_FILTER_CNT_SHIFT)) & CMP_CR0_FILTER_CNT_MASK) +/*! @} */ /*! @name CR1 - CMP Control Register 1 */ +/*! @{ */ #define CMP_CR1_EN_MASK (0x1U) #define CMP_CR1_EN_SHIFT (0U) +/*! EN - Comparator Module Enable + * 0b0..Analog Comparator is disabled. + * 0b1..Analog Comparator is enabled. + */ #define CMP_CR1_EN(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_EN_SHIFT)) & CMP_CR1_EN_MASK) #define CMP_CR1_OPE_MASK (0x2U) #define CMP_CR1_OPE_SHIFT (1U) +/*! OPE - Comparator Output Pin Enable + * 0b0..CMPO is not available on the associated CMPO output pin. If the comparator does not own the pin, this field has no effect. + * 0b1..CMPO is available on the associated CMPO output pin. The comparator output (CMPO) is driven out on the associated CMPO output pin if the comparator owns the pin. If the comparator does not own the field, this bit has no effect. + */ #define CMP_CR1_OPE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_OPE_SHIFT)) & CMP_CR1_OPE_MASK) #define CMP_CR1_COS_MASK (0x4U) #define CMP_CR1_COS_SHIFT (2U) +/*! COS - Comparator Output Select + * 0b0..Set the filtered comparator output (CMPO) to equal COUT. + * 0b1..Set the unfiltered comparator output (CMPO) to equal COUTA. + */ #define CMP_CR1_COS(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_COS_SHIFT)) & CMP_CR1_COS_MASK) #define CMP_CR1_INV_MASK (0x8U) #define CMP_CR1_INV_SHIFT (3U) +/*! INV - Comparator INVERT + * 0b0..Does not invert the comparator output. + * 0b1..Inverts the comparator output. + */ #define CMP_CR1_INV(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_INV_SHIFT)) & CMP_CR1_INV_MASK) #define CMP_CR1_PMODE_MASK (0x10U) #define CMP_CR1_PMODE_SHIFT (4U) +/*! PMODE - Power Mode Select + * 0b0..Low-Speed (LS) Comparison mode selected. In this mode, CMP has slower output propagation delay and lower current consumption. + * 0b1..High-Speed (HS) Comparison mode selected. In this mode, CMP has faster output propagation delay and higher current consumption. + */ #define CMP_CR1_PMODE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_PMODE_SHIFT)) & CMP_CR1_PMODE_MASK) #define CMP_CR1_WE_MASK (0x40U) #define CMP_CR1_WE_SHIFT (6U) +/*! WE - Windowing Enable + * 0b0..Windowing mode is not selected. + * 0b1..Windowing mode is selected. + */ #define CMP_CR1_WE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_WE_SHIFT)) & CMP_CR1_WE_MASK) #define CMP_CR1_SE_MASK (0x80U) #define CMP_CR1_SE_SHIFT (7U) +/*! SE - Sample Enable + * 0b0..Sampling mode is not selected. + * 0b1..Sampling mode is selected. + */ #define CMP_CR1_SE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_SE_SHIFT)) & CMP_CR1_SE_MASK) +/*! @} */ /*! @name FPR - CMP Filter Period Register */ +/*! @{ */ #define CMP_FPR_FILT_PER_MASK (0xFFU) #define CMP_FPR_FILT_PER_SHIFT (0U) #define CMP_FPR_FILT_PER(x) (((uint8_t)(((uint8_t)(x)) << CMP_FPR_FILT_PER_SHIFT)) & CMP_FPR_FILT_PER_MASK) +/*! @} */ /*! @name SCR - CMP Status and Control Register */ +/*! @{ */ #define CMP_SCR_COUT_MASK (0x1U) #define CMP_SCR_COUT_SHIFT (0U) #define CMP_SCR_COUT(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_COUT_SHIFT)) & CMP_SCR_COUT_MASK) #define CMP_SCR_CFF_MASK (0x2U) #define CMP_SCR_CFF_SHIFT (1U) +/*! CFF - Analog Comparator Flag Falling + * 0b0..Falling-edge on COUT has not been detected. + * 0b1..Falling-edge on COUT has occurred. + */ #define CMP_SCR_CFF(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFF_SHIFT)) & CMP_SCR_CFF_MASK) #define CMP_SCR_CFR_MASK (0x4U) #define CMP_SCR_CFR_SHIFT (2U) +/*! CFR - Analog Comparator Flag Rising + * 0b0..Rising-edge on COUT has not been detected. + * 0b1..Rising-edge on COUT has occurred. + */ #define CMP_SCR_CFR(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFR_SHIFT)) & CMP_SCR_CFR_MASK) #define CMP_SCR_IEF_MASK (0x8U) #define CMP_SCR_IEF_SHIFT (3U) +/*! IEF - Comparator Interrupt Enable Falling + * 0b0..Interrupt is disabled. + * 0b1..Interrupt is enabled. + */ #define CMP_SCR_IEF(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_IEF_SHIFT)) & CMP_SCR_IEF_MASK) #define CMP_SCR_IER_MASK (0x10U) #define CMP_SCR_IER_SHIFT (4U) +/*! IER - Comparator Interrupt Enable Rising + * 0b0..Interrupt is disabled. + * 0b1..Interrupt is enabled. + */ #define CMP_SCR_IER(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_IER_SHIFT)) & CMP_SCR_IER_MASK) #define CMP_SCR_DMAEN_MASK (0x40U) #define CMP_SCR_DMAEN_SHIFT (6U) +/*! DMAEN - DMA Enable Control + * 0b0..DMA is disabled. + * 0b1..DMA is enabled. + */ #define CMP_SCR_DMAEN(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_DMAEN_SHIFT)) & CMP_SCR_DMAEN_MASK) +/*! @} */ /*! @name DACCR - DAC Control Register */ +/*! @{ */ #define CMP_DACCR_VOSEL_MASK (0x3FU) #define CMP_DACCR_VOSEL_SHIFT (0U) #define CMP_DACCR_VOSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_VOSEL_SHIFT)) & CMP_DACCR_VOSEL_MASK) #define CMP_DACCR_VRSEL_MASK (0x40U) #define CMP_DACCR_VRSEL_SHIFT (6U) +/*! VRSEL - Supply Voltage Reference Source Select + * 0b0..Vin1 is selected as resistor ladder network supply reference. + * 0b1..Vin2 is selected as resistor ladder network supply reference. + */ #define CMP_DACCR_VRSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_VRSEL_SHIFT)) & CMP_DACCR_VRSEL_MASK) #define CMP_DACCR_DACEN_MASK (0x80U) #define CMP_DACCR_DACEN_SHIFT (7U) +/*! DACEN - DAC Enable + * 0b0..DAC is disabled. + * 0b1..DAC is enabled. + */ #define CMP_DACCR_DACEN(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_DACEN_SHIFT)) & CMP_DACCR_DACEN_MASK) +/*! @} */ /*! @name MUXCR - MUX Control Register */ +/*! @{ */ #define CMP_MUXCR_MSEL_MASK (0x7U) #define CMP_MUXCR_MSEL_SHIFT (0U) +/*! MSEL - Minus Input Mux Control + * 0b000..IN0 + * 0b001..IN1 + * 0b010..IN2 + * 0b011..IN3 + * 0b100..IN4 + * 0b101..IN5 + * 0b110..IN6 + * 0b111..IN7 + */ #define CMP_MUXCR_MSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_MSEL_SHIFT)) & CMP_MUXCR_MSEL_MASK) #define CMP_MUXCR_PSEL_MASK (0x38U) #define CMP_MUXCR_PSEL_SHIFT (3U) +/*! PSEL - Plus Input Mux Control + * 0b000..IN0 + * 0b001..IN1 + * 0b010..IN2 + * 0b011..IN3 + * 0b100..IN4 + * 0b101..IN5 + * 0b110..IN6 + * 0b111..IN7 + */ #define CMP_MUXCR_PSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_PSEL_SHIFT)) & CMP_MUXCR_PSEL_MASK) +/*! @} */ /*! @@ -5557,249 +8081,569 @@ typedef struct { */ /*! @name CSL - Config security level register */ +/*! @{ */ #define CSU_CSL_SUR_S2_MASK (0x1U) #define CSU_CSL_SUR_S2_SHIFT (0U) +/*! SUR_S2 + * 0b0..The secure user read access is disabled for the second slave. + * 0b1..The secure user read access is enabled for the second slave. + */ #define CSU_CSL_SUR_S2(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SUR_S2_SHIFT)) & CSU_CSL_SUR_S2_MASK) #define CSU_CSL_SSR_S2_MASK (0x2U) #define CSU_CSL_SSR_S2_SHIFT (1U) +/*! SSR_S2 + * 0b0..The secure supervisor read access is disabled for the second slave. + * 0b1..The secure supervisor read access is enabled for the second slave. + */ #define CSU_CSL_SSR_S2(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SSR_S2_SHIFT)) & CSU_CSL_SSR_S2_MASK) #define CSU_CSL_NUR_S2_MASK (0x4U) #define CSU_CSL_NUR_S2_SHIFT (2U) +/*! NUR_S2 + * 0b0..The non-secure user read access is disabled for the second slave. + * 0b1..The non-secure user read access is enabled for the second slave. + */ #define CSU_CSL_NUR_S2(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NUR_S2_SHIFT)) & CSU_CSL_NUR_S2_MASK) #define CSU_CSL_NSR_S2_MASK (0x8U) #define CSU_CSL_NSR_S2_SHIFT (3U) +/*! NSR_S2 + * 0b0..The non-secure supervisor read access is disabled for the second slave. + * 0b1..The non-secure supervisor read access is enabled for the second slave. + */ #define CSU_CSL_NSR_S2(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NSR_S2_SHIFT)) & CSU_CSL_NSR_S2_MASK) #define CSU_CSL_SUW_S2_MASK (0x10U) #define CSU_CSL_SUW_S2_SHIFT (4U) +/*! SUW_S2 + * 0b0..The secure user write access is disabled for the second slave. + * 0b1..The secure user write access is enabled for the second slave. + */ #define CSU_CSL_SUW_S2(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SUW_S2_SHIFT)) & CSU_CSL_SUW_S2_MASK) #define CSU_CSL_SSW_S2_MASK (0x20U) #define CSU_CSL_SSW_S2_SHIFT (5U) +/*! SSW_S2 + * 0b0..The secure supervisor write access is disabled for the second slave. + * 0b1..The secure supervisor write access is enabled for the second slave. + */ #define CSU_CSL_SSW_S2(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SSW_S2_SHIFT)) & CSU_CSL_SSW_S2_MASK) #define CSU_CSL_NUW_S2_MASK (0x40U) #define CSU_CSL_NUW_S2_SHIFT (6U) +/*! NUW_S2 + * 0b0..The non-secure user write access is disabled for the second slave. + * 0b1..The non-secure user write access is enabled for the second slave. + */ #define CSU_CSL_NUW_S2(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NUW_S2_SHIFT)) & CSU_CSL_NUW_S2_MASK) #define CSU_CSL_NSW_S2_MASK (0x80U) #define CSU_CSL_NSW_S2_SHIFT (7U) +/*! NSW_S2 + * 0b0..The non-secure supervisor write access is disabled for the second slave. + * 0b1..The non-secure supervisor write access is enabled for the second slave. + */ #define CSU_CSL_NSW_S2(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NSW_S2_SHIFT)) & CSU_CSL_NSW_S2_MASK) #define CSU_CSL_LOCK_S2_MASK (0x100U) #define CSU_CSL_LOCK_S2_SHIFT (8U) +/*! LOCK_S2 + * 0b0..Not locked. Bits 7-0 can be written by the software. + * 0b1..Bits 7-0 are locked and cannot be written by the software + */ #define CSU_CSL_LOCK_S2(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_LOCK_S2_SHIFT)) & CSU_CSL_LOCK_S2_MASK) #define CSU_CSL_SUR_S1_MASK (0x10000U) #define CSU_CSL_SUR_S1_SHIFT (16U) +/*! SUR_S1 + * 0b0..The secure user read access is disabled for the first slave. + * 0b1..The secure user read access is enabled for the first slave. + */ #define CSU_CSL_SUR_S1(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SUR_S1_SHIFT)) & CSU_CSL_SUR_S1_MASK) #define CSU_CSL_SSR_S1_MASK (0x20000U) #define CSU_CSL_SSR_S1_SHIFT (17U) +/*! SSR_S1 + * 0b0..The secure supervisor read access is disabled for the first slave. + * 0b1..The secure supervisor read access is enabled for the first slave. + */ #define CSU_CSL_SSR_S1(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SSR_S1_SHIFT)) & CSU_CSL_SSR_S1_MASK) #define CSU_CSL_NUR_S1_MASK (0x40000U) #define CSU_CSL_NUR_S1_SHIFT (18U) +/*! NUR_S1 + * 0b0..The non-secure user read access is disabled for the first slave. + * 0b1..The non-secure user read access is enabled for the first slave. + */ #define CSU_CSL_NUR_S1(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NUR_S1_SHIFT)) & CSU_CSL_NUR_S1_MASK) #define CSU_CSL_NSR_S1_MASK (0x80000U) #define CSU_CSL_NSR_S1_SHIFT (19U) +/*! NSR_S1 + * 0b0..The non-secure supervisor read access is disabled for the first slave. + * 0b1..The non-secure supervisor read access is enabled for the first slave. + */ #define CSU_CSL_NSR_S1(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NSR_S1_SHIFT)) & CSU_CSL_NSR_S1_MASK) #define CSU_CSL_SUW_S1_MASK (0x100000U) #define CSU_CSL_SUW_S1_SHIFT (20U) +/*! SUW_S1 + * 0b0..The secure user write access is disabled for the first slave. + * 0b1..The secure user write access is enabled for the first slave. + */ #define CSU_CSL_SUW_S1(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SUW_S1_SHIFT)) & CSU_CSL_SUW_S1_MASK) #define CSU_CSL_SSW_S1_MASK (0x200000U) #define CSU_CSL_SSW_S1_SHIFT (21U) +/*! SSW_S1 + * 0b0..The secure supervisor write access is disabled for the first slave. + * 0b1..The secure supervisor write access is enabled for the first slave. + */ #define CSU_CSL_SSW_S1(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SSW_S1_SHIFT)) & CSU_CSL_SSW_S1_MASK) #define CSU_CSL_NUW_S1_MASK (0x400000U) #define CSU_CSL_NUW_S1_SHIFT (22U) +/*! NUW_S1 + * 0b0..The non-secure user write access is disabled for the first slave. + * 0b1..The non-secure user write access is enabled for the first slave. + */ #define CSU_CSL_NUW_S1(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NUW_S1_SHIFT)) & CSU_CSL_NUW_S1_MASK) #define CSU_CSL_NSW_S1_MASK (0x800000U) #define CSU_CSL_NSW_S1_SHIFT (23U) +/*! NSW_S1 + * 0b0..The non-secure supervisor write access is disabled for the first slave. + * 0b1..The non-secure supervisor write access is enabled for the first slave + */ #define CSU_CSL_NSW_S1(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NSW_S1_SHIFT)) & CSU_CSL_NSW_S1_MASK) #define CSU_CSL_LOCK_S1_MASK (0x1000000U) #define CSU_CSL_LOCK_S1_SHIFT (24U) +/*! LOCK_S1 + * 0b0..Not locked. The bits 16-23 can be written by the software. + * 0b1..The bits 16-23 are locked and can't be written by the software. + */ #define CSU_CSL_LOCK_S1(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_LOCK_S1_SHIFT)) & CSU_CSL_LOCK_S1_MASK) +/*! @} */ /* The count of CSU_CSL */ #define CSU_CSL_COUNT (32U) /*! @name HP0 - HP0 register */ +/*! @{ */ #define CSU_HP0_HP_DMA_MASK (0x4U) #define CSU_HP0_HP_DMA_SHIFT (2U) +/*! HP_DMA + * 0b0..The hprot1 input signal value is routed to the csu_hprot1 output for the corresponding master. + * 0b1..The HP register bit is routed to the csu_hprot1 output for the corresponding master. + */ #define CSU_HP0_HP_DMA(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_DMA_SHIFT)) & CSU_HP0_HP_DMA_MASK) #define CSU_HP0_L_DMA_MASK (0x8U) #define CSU_HP0_L_DMA_SHIFT (3U) +/*! L_DMA + * 0b0..No lock-the adjacent (next lower) bit can be written by the software. + * 0b1..Lock-the adjacent (next lower) bit can't be written by the software. + */ #define CSU_HP0_L_DMA(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_DMA_SHIFT)) & CSU_HP0_L_DMA_MASK) #define CSU_HP0_HP_LCDIF_MASK (0x10U) #define CSU_HP0_HP_LCDIF_SHIFT (4U) +/*! HP_LCDIF + * 0b0..The hprot1 input signal value is routed to the csu_hprot1 output for the corresponding master. + * 0b1..The HP register bit is routed to the csu_hprot1 output for the corresponding master. + */ #define CSU_HP0_HP_LCDIF(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_LCDIF_SHIFT)) & CSU_HP0_HP_LCDIF_MASK) #define CSU_HP0_L_LCDIF_MASK (0x20U) #define CSU_HP0_L_LCDIF_SHIFT (5U) +/*! L_LCDIF + * 0b0..No lock-the adjacent (next lower) bit can be written by the software. + * 0b1..Lock-the adjacent (next lower) bit can't be written by the software. + */ #define CSU_HP0_L_LCDIF(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_LCDIF_SHIFT)) & CSU_HP0_L_LCDIF_MASK) #define CSU_HP0_HP_CSI_MASK (0x40U) #define CSU_HP0_HP_CSI_SHIFT (6U) +/*! HP_CSI + * 0b0..The hprot1 input signal value is routed to the csu_hprot1 output for the corresponding master. + * 0b1..The HP register bit is routed to the csu_hprot1 output for the corresponding master. + */ #define CSU_HP0_HP_CSI(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_CSI_SHIFT)) & CSU_HP0_HP_CSI_MASK) #define CSU_HP0_L_CSI_MASK (0x80U) #define CSU_HP0_L_CSI_SHIFT (7U) +/*! L_CSI + * 0b0..No lock-the adjacent (next lower) bit can be written by the software. + * 0b1..Lock-the adjacent (next lower) bit can't be written by the software. + */ #define CSU_HP0_L_CSI(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_CSI_SHIFT)) & CSU_HP0_L_CSI_MASK) #define CSU_HP0_HP_PXP_MASK (0x100U) #define CSU_HP0_HP_PXP_SHIFT (8U) +/*! HP_PXP + * 0b0..The hprot1 input signal value is routed to the csu_hprot1 output for the corresponding master. + * 0b1..The HP register bit is routed to the csu_hprot1 output for the corresponding master. + */ #define CSU_HP0_HP_PXP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_PXP_SHIFT)) & CSU_HP0_HP_PXP_MASK) #define CSU_HP0_L_PXP_MASK (0x200U) #define CSU_HP0_L_PXP_SHIFT (9U) +/*! L_PXP + * 0b0..No lock-the adjacent (next lower) bit can be written by the software. + * 0b1..Lock-the adjacent (next lower) bit can't be written by the software. + */ #define CSU_HP0_L_PXP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_PXP_SHIFT)) & CSU_HP0_L_PXP_MASK) #define CSU_HP0_HP_DCP_MASK (0x400U) #define CSU_HP0_HP_DCP_SHIFT (10U) +/*! HP_DCP + * 0b0..The hprot1 input signal value is routed to the csu_hprot1 output for the corresponding master. + * 0b1..The HP register bit is routed to the csu_hprot1 output for the corresponding master. + */ #define CSU_HP0_HP_DCP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_DCP_SHIFT)) & CSU_HP0_HP_DCP_MASK) #define CSU_HP0_L_DCP_MASK (0x800U) #define CSU_HP0_L_DCP_SHIFT (11U) +/*! L_DCP + * 0b0..No lock-the adjacent (next lower) bit can be written by the software. + * 0b1..Lock-the adjacent (next lower) bit cannot be written by the software. + */ #define CSU_HP0_L_DCP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_DCP_SHIFT)) & CSU_HP0_L_DCP_MASK) #define CSU_HP0_HP_ENET_MASK (0x4000U) #define CSU_HP0_HP_ENET_SHIFT (14U) +/*! HP_ENET + * 0b0..The hprot1 input signal value is routed to the csu_hprot1 output for the corresponding master. + * 0b1..The HP register bit is routed to the csu_hprot1 output for the corresponding master. + */ #define CSU_HP0_HP_ENET(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_ENET_SHIFT)) & CSU_HP0_HP_ENET_MASK) #define CSU_HP0_L_ENET_MASK (0x8000U) #define CSU_HP0_L_ENET_SHIFT (15U) +/*! L_ENET + * 0b0..No lock-the adjacent (next lower) bit can be written by the software. + * 0b1..Lock-the adjacent (next lower) bit can't be written by the software. + */ #define CSU_HP0_L_ENET(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_ENET_SHIFT)) & CSU_HP0_L_ENET_MASK) #define CSU_HP0_HP_USDHC1_MASK (0x10000U) #define CSU_HP0_HP_USDHC1_SHIFT (16U) +/*! HP_USDHC1 + * 0b0..The hprot1 input signal value is routed to the csu_hprot1 output for the corresponding master. + * 0b1..The HP register bit is routed to the csu_hprot1 output for the corresponding master. + */ #define CSU_HP0_HP_USDHC1(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_USDHC1_SHIFT)) & CSU_HP0_HP_USDHC1_MASK) #define CSU_HP0_L_USDHC1_MASK (0x20000U) #define CSU_HP0_L_USDHC1_SHIFT (17U) +/*! L_USDHC1 + * 0b0..No lock-the adjacent (next lower) bit can be written by the software. + * 0b1..Lock-the adjacent (next lower) bit can't be written by the software. + */ #define CSU_HP0_L_USDHC1(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_USDHC1_SHIFT)) & CSU_HP0_L_USDHC1_MASK) #define CSU_HP0_HP_USDHC2_MASK (0x40000U) #define CSU_HP0_HP_USDHC2_SHIFT (18U) +/*! HP_USDHC2 + * 0b0..The hprot1 input signal value is routed to the csu_hprot1 output for the corresponding master. + * 0b1..The HP register bit is routed to the csu_hprot1 output for the corresponding master. + */ #define CSU_HP0_HP_USDHC2(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_USDHC2_SHIFT)) & CSU_HP0_HP_USDHC2_MASK) #define CSU_HP0_L_USDHC2_MASK (0x80000U) #define CSU_HP0_L_USDHC2_SHIFT (19U) +/*! L_USDHC2 + * 0b0..No lock-the adjacent (next lower) bit can be written by the software. + * 0b1..Lock-the adjacent (next lower) bit can't be written by the software. + */ #define CSU_HP0_L_USDHC2(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_USDHC2_SHIFT)) & CSU_HP0_L_USDHC2_MASK) #define CSU_HP0_HP_TPSMP_MASK (0x100000U) #define CSU_HP0_HP_TPSMP_SHIFT (20U) +/*! HP_TPSMP + * 0b0..The hprot1 input signal value is routed to the csu_hprot1 output for the corresponding master. + * 0b1..The HP register bit is routed to the csu_hprot1 output for the corresponding master. + */ #define CSU_HP0_HP_TPSMP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_TPSMP_SHIFT)) & CSU_HP0_HP_TPSMP_MASK) #define CSU_HP0_L_TPSMP_MASK (0x200000U) #define CSU_HP0_L_TPSMP_SHIFT (21U) +/*! L_TPSMP + * 0b0..No lock-the adjacent (next lower) bit can be written by the software. + * 0b1..Lock-the adjacent (next lower) bit can't be written by the software. + */ #define CSU_HP0_L_TPSMP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_TPSMP_SHIFT)) & CSU_HP0_L_TPSMP_MASK) #define CSU_HP0_HP_USB_MASK (0x400000U) #define CSU_HP0_HP_USB_SHIFT (22U) +/*! HP_USB + * 0b0..The hprot1 input signal value is routed to the csu_hprot1 output for the corresponding master. + * 0b1..The HP register bit is routed to the csu_hprot1 output for the corresponding master. + */ #define CSU_HP0_HP_USB(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_USB_SHIFT)) & CSU_HP0_HP_USB_MASK) #define CSU_HP0_L_USB_MASK (0x800000U) #define CSU_HP0_L_USB_SHIFT (23U) +/*! L_USB + * 0b0..No lock-the adjacent (next lower) bit can be written by the software. + * 0b1..Lock-the adjacent (next lower) bit can't be written by the software. + */ #define CSU_HP0_L_USB(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_USB_SHIFT)) & CSU_HP0_L_USB_MASK) +/*! @} */ /*! @name SA - Secure access register */ +/*! @{ */ #define CSU_SA_NSA_DMA_MASK (0x4U) #define CSU_SA_NSA_DMA_SHIFT (2U) +/*! NSA_DMA - Non-secure access policy indicator bit + * 0b0..Secure access for the corresponding type-1 master + * 0b1..Non-secure access for the corresponding type-1 master + */ #define CSU_SA_NSA_DMA(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_DMA_SHIFT)) & CSU_SA_NSA_DMA_MASK) #define CSU_SA_L_DMA_MASK (0x8U) #define CSU_SA_L_DMA_SHIFT (3U) +/*! L_DMA + * 0b0..No lock-the adjacent (next lower) bit can be written by the software. + * 0b1..Lock-the adjacent (next lower) bit can't be written by the software. + */ #define CSU_SA_L_DMA(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_DMA_SHIFT)) & CSU_SA_L_DMA_MASK) #define CSU_SA_NSA_LCDIF_MASK (0x10U) #define CSU_SA_NSA_LCDIF_SHIFT (4U) +/*! NSA_LCDIF - Non-secure access policy indicator bit + * 0b0..Secure access for the corresponding type-1 master + * 0b1..Non-secure access for the corresponding type-1 master + */ #define CSU_SA_NSA_LCDIF(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_LCDIF_SHIFT)) & CSU_SA_NSA_LCDIF_MASK) #define CSU_SA_L_LCDIF_MASK (0x20U) #define CSU_SA_L_LCDIF_SHIFT (5U) +/*! L_LCDIF + * 0b0..No lock-the adjacent (next lower) bit can be written by the software. + * 0b1..Lock-the adjacent (next lower) bit can't be written by the software. + */ #define CSU_SA_L_LCDIF(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_LCDIF_SHIFT)) & CSU_SA_L_LCDIF_MASK) #define CSU_SA_NSA_CSI_MASK (0x40U) #define CSU_SA_NSA_CSI_SHIFT (6U) +/*! NSA_CSI - Non-secure access policy indicator bit + * 0b0..Secure access for the corresponding type-1 master + * 0b1..Non-secure access for the corresponding type-1 master + */ #define CSU_SA_NSA_CSI(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_CSI_SHIFT)) & CSU_SA_NSA_CSI_MASK) #define CSU_SA_L_CSI_MASK (0x80U) #define CSU_SA_L_CSI_SHIFT (7U) +/*! L_CSI + * 0b0..No lock-the adjacent (next lower) bit can be written by the software. + * 0b1..Lock-the adjacent (next lower) bit can't be written by the software. + */ #define CSU_SA_L_CSI(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_CSI_SHIFT)) & CSU_SA_L_CSI_MASK) #define CSU_SA_NSA_PXP_MASK (0x100U) #define CSU_SA_NSA_PXP_SHIFT (8U) +/*! NSA_PXP - Non-Secure Access Policy indicator bit + * 0b0..Secure access for the corresponding type-1 master + * 0b1..Non-secure access for the corresponding type-1 master + */ #define CSU_SA_NSA_PXP(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_PXP_SHIFT)) & CSU_SA_NSA_PXP_MASK) #define CSU_SA_L_PXP_MASK (0x200U) #define CSU_SA_L_PXP_SHIFT (9U) +/*! L_PXP + * 0b0..No lock-the adjacent (next lower) bit can be written by the software. + * 0b1..Lock-the adjacent (next lower) bit can't be written by the software. + */ #define CSU_SA_L_PXP(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_PXP_SHIFT)) & CSU_SA_L_PXP_MASK) #define CSU_SA_NSA_DCP_MASK (0x400U) #define CSU_SA_NSA_DCP_SHIFT (10U) +/*! NSA_DCP - Non-secure access policy indicator bit + * 0b0..Secure access for the corresponding type-1 master + * 0b1..Non-secure access for the corresponding type-1 master + */ #define CSU_SA_NSA_DCP(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_DCP_SHIFT)) & CSU_SA_NSA_DCP_MASK) #define CSU_SA_L_DCP_MASK (0x800U) #define CSU_SA_L_DCP_SHIFT (11U) +/*! L_DCP + * 0b0..No lock-the adjacent (next lower) bit can be written by the software. + * 0b1..Lock-the adjacent (next lower) bit can't be written by the software. + */ #define CSU_SA_L_DCP(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_DCP_SHIFT)) & CSU_SA_L_DCP_MASK) #define CSU_SA_NSA_ENET_MASK (0x4000U) #define CSU_SA_NSA_ENET_SHIFT (14U) +/*! NSA_ENET - Non-secure access policy indicator bit + * 0b0..Secure access for the corresponding type-1 master + * 0b1..Non-secure access for the corresponding type-1 master + */ #define CSU_SA_NSA_ENET(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_ENET_SHIFT)) & CSU_SA_NSA_ENET_MASK) #define CSU_SA_L_ENET_MASK (0x8000U) #define CSU_SA_L_ENET_SHIFT (15U) +/*! L_ENET + * 0b0..No lock-the adjacent (next lower) bit can be written by the software. + * 0b1..Lock-the adjacent (next lower) bit can't be written by the software. + */ #define CSU_SA_L_ENET(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_ENET_SHIFT)) & CSU_SA_L_ENET_MASK) #define CSU_SA_NSA_USDHC1_MASK (0x10000U) #define CSU_SA_NSA_USDHC1_SHIFT (16U) +/*! NSA_USDHC1 - Non-secure access policy indicator bit + * 0b0..Secure access for the corresponding type-1 master + * 0b1..Non-secure access for the corresponding type-1 master + */ #define CSU_SA_NSA_USDHC1(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_USDHC1_SHIFT)) & CSU_SA_NSA_USDHC1_MASK) #define CSU_SA_L_USDHC1_MASK (0x20000U) #define CSU_SA_L_USDHC1_SHIFT (17U) +/*! L_USDHC1 + * 0b0..No lock-the adjacent (next lower) bit can be written by the software. + * 0b1..Lock-the adjacent (next lower) bit can't be written by the software. + */ #define CSU_SA_L_USDHC1(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_USDHC1_SHIFT)) & CSU_SA_L_USDHC1_MASK) #define CSU_SA_NSA_USDHC2_MASK (0x40000U) #define CSU_SA_NSA_USDHC2_SHIFT (18U) +/*! NSA_USDHC2 - Non-secure access policy indicator bit + * 0b0..Secure access for the corresponding type-1 master + * 0b1..Non-secure access for the corresponding type-1 master + */ #define CSU_SA_NSA_USDHC2(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_USDHC2_SHIFT)) & CSU_SA_NSA_USDHC2_MASK) #define CSU_SA_L_USDHC2_MASK (0x80000U) #define CSU_SA_L_USDHC2_SHIFT (19U) +/*! L_USDHC2 + * 0b0..No lock-the adjacent (next lower) bit can be written by the software. + * 0b1..Lock-the adjacent (next lower) bit can't be written by the software. + */ #define CSU_SA_L_USDHC2(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_USDHC2_SHIFT)) & CSU_SA_L_USDHC2_MASK) #define CSU_SA_NSA_TPSMP_MASK (0x100000U) #define CSU_SA_NSA_TPSMP_SHIFT (20U) +/*! NSA_TPSMP - Non-secure access policy indicator bit + * 0b0..Secure access for the corresponding type-1 master + * 0b1..Non-secure access for the corresponding type-1 master + */ #define CSU_SA_NSA_TPSMP(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_TPSMP_SHIFT)) & CSU_SA_NSA_TPSMP_MASK) #define CSU_SA_L_TPSMP_MASK (0x200000U) #define CSU_SA_L_TPSMP_SHIFT (21U) +/*! L_TPSMP + * 0b0..No lock-the adjacent (next lower) bit can be written by the software. + * 0b1..Lock-the adjacent (next lower) bit can't be written by the software. + */ #define CSU_SA_L_TPSMP(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_TPSMP_SHIFT)) & CSU_SA_L_TPSMP_MASK) #define CSU_SA_NSA_USB_MASK (0x400000U) #define CSU_SA_NSA_USB_SHIFT (22U) +/*! NSA_USB - Non-secure access policy indicator bit + * 0b0..Secure access for the corresponding type-1 master + * 0b1..Non-secure access for the corresponding type-1 master + */ #define CSU_SA_NSA_USB(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_USB_SHIFT)) & CSU_SA_NSA_USB_MASK) #define CSU_SA_L_USB_MASK (0x800000U) #define CSU_SA_L_USB_SHIFT (23U) +/*! L_USB + * 0b0..No lock-the adjacent (next lower) bit can be written by the software. + * 0b1..Lock-the adjacent (next lower) bit can't be written by the software. + */ #define CSU_SA_L_USB(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_USB_SHIFT)) & CSU_SA_L_USB_MASK) +/*! @} */ /*! @name HPCONTROL0 - HPCONTROL0 register */ +/*! @{ */ #define CSU_HPCONTROL0_HPC_DMA_MASK (0x4U) #define CSU_HPCONTROL0_HPC_DMA_SHIFT (2U) +/*! HPC_DMA + * 0b0..User mode for the corresponding master + * 0b1..Supervisor mode for the corresponding master + */ #define CSU_HPCONTROL0_HPC_DMA(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_DMA_SHIFT)) & CSU_HPCONTROL0_HPC_DMA_MASK) #define CSU_HPCONTROL0_L_DMA_MASK (0x8U) #define CSU_HPCONTROL0_L_DMA_SHIFT (3U) +/*! L_DMA + * 0b0..No lock-the adjacent (next lower) bit can be written by the software. + * 0b1..Lock-the adjacent (next lower) bit can't be written by the software. + */ #define CSU_HPCONTROL0_L_DMA(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_DMA_SHIFT)) & CSU_HPCONTROL0_L_DMA_MASK) #define CSU_HPCONTROL0_HPC_LCDIF_MASK (0x10U) #define CSU_HPCONTROL0_HPC_LCDIF_SHIFT (4U) +/*! HPC_LCDIF + * 0b0..User mode for the corresponding master + * 0b1..Supervisor mode for the corresponding master + */ #define CSU_HPCONTROL0_HPC_LCDIF(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_LCDIF_SHIFT)) & CSU_HPCONTROL0_HPC_LCDIF_MASK) #define CSU_HPCONTROL0_L_LCDIF_MASK (0x20U) #define CSU_HPCONTROL0_L_LCDIF_SHIFT (5U) +/*! L_LCDIF + * 0b0..No lock-the adjacent (next lower) bit can be written by the software. + * 0b1..Lock-the adjacent (next lower) bit can't be written by the software. + */ #define CSU_HPCONTROL0_L_LCDIF(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_LCDIF_SHIFT)) & CSU_HPCONTROL0_L_LCDIF_MASK) #define CSU_HPCONTROL0_HPC_CSI_MASK (0x40U) #define CSU_HPCONTROL0_HPC_CSI_SHIFT (6U) +/*! HPC_CSI + * 0b0..User mode for the corresponding master + * 0b1..Supervisor mode for the corresponding master + */ #define CSU_HPCONTROL0_HPC_CSI(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_CSI_SHIFT)) & CSU_HPCONTROL0_HPC_CSI_MASK) #define CSU_HPCONTROL0_L_CSI_MASK (0x80U) #define CSU_HPCONTROL0_L_CSI_SHIFT (7U) +/*! L_CSI + * 0b0..No lock-the adjacent (next lower) bit can be written by the software. + * 0b1..Lock-the adjacent (next lower) bit can't be written by the software. + */ #define CSU_HPCONTROL0_L_CSI(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_CSI_SHIFT)) & CSU_HPCONTROL0_L_CSI_MASK) #define CSU_HPCONTROL0_HPC_PXP_MASK (0x100U) #define CSU_HPCONTROL0_HPC_PXP_SHIFT (8U) +/*! HPC_PXP + * 0b0..User mode for the corresponding master + * 0b1..Supervisor mode for the corresponding master + */ #define CSU_HPCONTROL0_HPC_PXP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_PXP_SHIFT)) & CSU_HPCONTROL0_HPC_PXP_MASK) #define CSU_HPCONTROL0_L_PXP_MASK (0x200U) #define CSU_HPCONTROL0_L_PXP_SHIFT (9U) +/*! L_PXP + * 0b0..No lock-the adjacent (next lower) bit can be written by the software. + * 0b1..Lock-the adjacent (next lower) bit can't be written by the software. + */ #define CSU_HPCONTROL0_L_PXP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_PXP_SHIFT)) & CSU_HPCONTROL0_L_PXP_MASK) #define CSU_HPCONTROL0_HPC_DCP_MASK (0x400U) #define CSU_HPCONTROL0_HPC_DCP_SHIFT (10U) +/*! HPC_DCP + * 0b0..User mode for the corresponding master + * 0b1..Supervisor mode for the corresponding master + */ #define CSU_HPCONTROL0_HPC_DCP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_DCP_SHIFT)) & CSU_HPCONTROL0_HPC_DCP_MASK) #define CSU_HPCONTROL0_L_DCP_MASK (0x800U) #define CSU_HPCONTROL0_L_DCP_SHIFT (11U) +/*! L_DCP + * 0b0..No lock-the adjacent (next lower) bit can be written by the software. + * 0b1..Lock-the adjacent (next lower) bit can't be written by the software. + */ #define CSU_HPCONTROL0_L_DCP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_DCP_SHIFT)) & CSU_HPCONTROL0_L_DCP_MASK) #define CSU_HPCONTROL0_HPC_ENET_MASK (0x4000U) #define CSU_HPCONTROL0_HPC_ENET_SHIFT (14U) +/*! HPC_ENET + * 0b0..User mode for the corresponding master + * 0b1..Supervisor mode for the corresponding master + */ #define CSU_HPCONTROL0_HPC_ENET(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_ENET_SHIFT)) & CSU_HPCONTROL0_HPC_ENET_MASK) #define CSU_HPCONTROL0_L_ENET_MASK (0x8000U) #define CSU_HPCONTROL0_L_ENET_SHIFT (15U) +/*! L_ENET + * 0b0..No lock-the adjacent (next lower) bit can be written by the software. + * 0b1..Lock-the adjacent (next lower) bit can't be written by the software. + */ #define CSU_HPCONTROL0_L_ENET(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_ENET_SHIFT)) & CSU_HPCONTROL0_L_ENET_MASK) #define CSU_HPCONTROL0_HPC_USDHC1_MASK (0x10000U) #define CSU_HPCONTROL0_HPC_USDHC1_SHIFT (16U) +/*! HPC_USDHC1 + * 0b0..User mode for the corresponding master + * 0b1..Supervisor mode for the corresponding master + */ #define CSU_HPCONTROL0_HPC_USDHC1(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_USDHC1_SHIFT)) & CSU_HPCONTROL0_HPC_USDHC1_MASK) #define CSU_HPCONTROL0_L_USDHC1_MASK (0x20000U) #define CSU_HPCONTROL0_L_USDHC1_SHIFT (17U) +/*! L_USDHC1 + * 0b0..No lock-the adjacent (next lower) bit can be written by the software. + * 0b1..Lock-the adjacent (next lower) bit can't be written by the software. + */ #define CSU_HPCONTROL0_L_USDHC1(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_USDHC1_SHIFT)) & CSU_HPCONTROL0_L_USDHC1_MASK) #define CSU_HPCONTROL0_HPC_USDHC2_MASK (0x40000U) #define CSU_HPCONTROL0_HPC_USDHC2_SHIFT (18U) +/*! HPC_USDHC2 + * 0b0..User mode for the corresponding master + * 0b1..Supervisor mode for the corresponding master + */ #define CSU_HPCONTROL0_HPC_USDHC2(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_USDHC2_SHIFT)) & CSU_HPCONTROL0_HPC_USDHC2_MASK) #define CSU_HPCONTROL0_L_USDHC2_MASK (0x80000U) #define CSU_HPCONTROL0_L_USDHC2_SHIFT (19U) +/*! L_USDHC2 + * 0b0..No lock-the adjacent (next lower) bit can be written by the software. + * 0b1..Lock-the adjacent (next lower) bit can't be written by the software. + */ #define CSU_HPCONTROL0_L_USDHC2(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_USDHC2_SHIFT)) & CSU_HPCONTROL0_L_USDHC2_MASK) #define CSU_HPCONTROL0_HPC_TPSMP_MASK (0x100000U) #define CSU_HPCONTROL0_HPC_TPSMP_SHIFT (20U) +/*! HPC_TPSMP + * 0b0..User mode for the corresponding master + * 0b1..Supervisor mode for the corresponding master + */ #define CSU_HPCONTROL0_HPC_TPSMP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_TPSMP_SHIFT)) & CSU_HPCONTROL0_HPC_TPSMP_MASK) #define CSU_HPCONTROL0_L_TPSMP_MASK (0x200000U) #define CSU_HPCONTROL0_L_TPSMP_SHIFT (21U) +/*! L_TPSMP + * 0b0..No lock-the adjacent (next lower) bit can be written by the software. + * 0b1..Lock-the adjacent (next lower) bit can't be written by the software. + */ #define CSU_HPCONTROL0_L_TPSMP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_TPSMP_SHIFT)) & CSU_HPCONTROL0_L_TPSMP_MASK) #define CSU_HPCONTROL0_HPC_USB_MASK (0x400000U) #define CSU_HPCONTROL0_HPC_USB_SHIFT (22U) +/*! HPC_USB + * 0b0..User mode for the corresponding master + * 0b1..Supervisor mode for the corresponding master + */ #define CSU_HPCONTROL0_HPC_USB(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_USB_SHIFT)) & CSU_HPCONTROL0_HPC_USB_MASK) #define CSU_HPCONTROL0_L_USB_MASK (0x800000U) #define CSU_HPCONTROL0_L_USB_SHIFT (23U) +/*! L_USB + * 0b0..No lock-the adjacent (next lower) bit can be written by the software. + * 0b1..Lock-the adjacent (next lower) bit can't be written by the software. + */ #define CSU_HPCONTROL0_L_USB(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_USB_SHIFT)) & CSU_HPCONTROL0_L_USB_MASK) +/*! @} */ /*! @@ -5849,6 +8693,7 @@ typedef struct { */ /*! @name REG0 - DCDC Register 0 */ +/*! @{ */ #define DCDC_REG0_PWD_ZCD_MASK (0x1U) #define DCDC_REG0_PWD_ZCD_SHIFT (0U) #define DCDC_REG0_PWD_ZCD(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_ZCD_SHIFT)) & DCDC_REG0_PWD_ZCD_MASK) @@ -5909,8 +8754,10 @@ typedef struct { #define DCDC_REG0_STS_DC_OK_MASK (0x80000000U) #define DCDC_REG0_STS_DC_OK_SHIFT (31U) #define DCDC_REG0_STS_DC_OK(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_STS_DC_OK_SHIFT)) & DCDC_REG0_STS_DC_OK_MASK) +/*! @} */ /*! @name REG1 - DCDC Register 1 */ +/*! @{ */ #define DCDC_REG1_REG_FBK_SEL_MASK (0x180U) #define DCDC_REG1_REG_FBK_SEL_SHIFT (7U) #define DCDC_REG1_REG_FBK_SEL(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_REG_FBK_SEL_SHIFT)) & DCDC_REG1_REG_FBK_SEL_MASK) @@ -5929,8 +8776,10 @@ typedef struct { #define DCDC_REG1_VBG_TRIM_MASK (0x1F000000U) #define DCDC_REG1_VBG_TRIM_SHIFT (24U) #define DCDC_REG1_VBG_TRIM(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_VBG_TRIM_SHIFT)) & DCDC_REG1_VBG_TRIM_MASK) +/*! @} */ /*! @name REG2 - DCDC Register 2 */ +/*! @{ */ #define DCDC_REG2_LOOPCTRL_DC_C_MASK (0x3U) #define DCDC_REG2_LOOPCTRL_DC_C_SHIFT (0U) #define DCDC_REG2_LOOPCTRL_DC_C(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_LOOPCTRL_DC_C_SHIFT)) & DCDC_REG2_LOOPCTRL_DC_C_MASK) @@ -5955,8 +8804,10 @@ typedef struct { #define DCDC_REG2_DCM_SET_CTRL_MASK (0x10000000U) #define DCDC_REG2_DCM_SET_CTRL_SHIFT (28U) #define DCDC_REG2_DCM_SET_CTRL(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_DCM_SET_CTRL_SHIFT)) & DCDC_REG2_DCM_SET_CTRL_MASK) +/*! @} */ /*! @name REG3 - DCDC Register 3 */ +/*! @{ */ #define DCDC_REG3_TRG_MASK (0x1FU) #define DCDC_REG3_TRG_SHIFT (0U) #define DCDC_REG3_TRG(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_TRG_SHIFT)) & DCDC_REG3_TRG_MASK) @@ -5975,6 +8826,7 @@ typedef struct { #define DCDC_REG3_DISABLE_STEP_MASK (0x40000000U) #define DCDC_REG3_DISABLE_STEP_SHIFT (30U) #define DCDC_REG3_DISABLE_STEP(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_DISABLE_STEP_SHIFT)) & DCDC_REG3_DISABLE_STEP_MASK) +/*! @} */ /*! @@ -6091,8 +8943,15 @@ typedef struct { */ /*! @name CTRL - DCP control register 0 */ +/*! @{ */ #define DCP_CTRL_CHANNEL_INTERRUPT_ENABLE_MASK (0xFFU) #define DCP_CTRL_CHANNEL_INTERRUPT_ENABLE_SHIFT (0U) +/*! CHANNEL_INTERRUPT_ENABLE + * 0b00000001..CH0 + * 0b00000010..CH1 + * 0b00000100..CH2 + * 0b00001000..CH3 + */ #define DCP_CTRL_CHANNEL_INTERRUPT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_CHANNEL_INTERRUPT_ENABLE_SHIFT)) & DCP_CTRL_CHANNEL_INTERRUPT_ENABLE_MASK) #define DCP_CTRL_RSVD_CSC_INTERRUPT_ENABLE_MASK (0x100U) #define DCP_CTRL_RSVD_CSC_INTERRUPT_ENABLE_SHIFT (8U) @@ -6108,9 +8967,17 @@ typedef struct { #define DCP_CTRL_GATHER_RESIDUAL_WRITES(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_GATHER_RESIDUAL_WRITES_SHIFT)) & DCP_CTRL_GATHER_RESIDUAL_WRITES_MASK) #define DCP_CTRL_PRESENT_SHA_MASK (0x10000000U) #define DCP_CTRL_PRESENT_SHA_SHIFT (28U) +/*! PRESENT_SHA + * 0b1..Present + * 0b0..Absent + */ #define DCP_CTRL_PRESENT_SHA(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_PRESENT_SHA_SHIFT)) & DCP_CTRL_PRESENT_SHA_MASK) #define DCP_CTRL_PRESENT_CRYPTO_MASK (0x20000000U) #define DCP_CTRL_PRESENT_CRYPTO_SHIFT (29U) +/*! PRESENT_CRYPTO + * 0b1..Present + * 0b0..Absent + */ #define DCP_CTRL_PRESENT_CRYPTO(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_PRESENT_CRYPTO_SHIFT)) & DCP_CTRL_PRESENT_CRYPTO_MASK) #define DCP_CTRL_CLKGATE_MASK (0x40000000U) #define DCP_CTRL_CLKGATE_SHIFT (30U) @@ -6118,8 +8985,10 @@ typedef struct { #define DCP_CTRL_SFTRST_MASK (0x80000000U) #define DCP_CTRL_SFTRST_SHIFT (31U) #define DCP_CTRL_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_SFTRST_SHIFT)) & DCP_CTRL_SFTRST_MASK) +/*! @} */ /*! @name STAT - DCP status register */ +/*! @{ */ #define DCP_STAT_IRQ_MASK (0xFU) #define DCP_STAT_IRQ_SHIFT (0U) #define DCP_STAT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_IRQ_SHIFT)) & DCP_STAT_IRQ_MASK) @@ -6128,20 +8997,47 @@ typedef struct { #define DCP_STAT_RSVD_IRQ(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_RSVD_IRQ_SHIFT)) & DCP_STAT_RSVD_IRQ_MASK) #define DCP_STAT_READY_CHANNELS_MASK (0xFF0000U) #define DCP_STAT_READY_CHANNELS_SHIFT (16U) +/*! READY_CHANNELS + * 0b00000001..CH0 + * 0b00000010..CH1 + * 0b00000100..CH2 + * 0b00001000..CH3 + */ #define DCP_STAT_READY_CHANNELS(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_READY_CHANNELS_SHIFT)) & DCP_STAT_READY_CHANNELS_MASK) #define DCP_STAT_CUR_CHANNEL_MASK (0xF000000U) #define DCP_STAT_CUR_CHANNEL_SHIFT (24U) +/*! CUR_CHANNEL + * 0b0000..None + * 0b0001..CH0 + * 0b0010..CH1 + * 0b0011..CH2 + * 0b0100..CH3 + */ #define DCP_STAT_CUR_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_CUR_CHANNEL_SHIFT)) & DCP_STAT_CUR_CHANNEL_MASK) #define DCP_STAT_OTP_KEY_READY_MASK (0x10000000U) #define DCP_STAT_OTP_KEY_READY_SHIFT (28U) #define DCP_STAT_OTP_KEY_READY(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_OTP_KEY_READY_SHIFT)) & DCP_STAT_OTP_KEY_READY_MASK) +/*! @} */ /*! @name CHANNELCTRL - DCP channel control register */ +/*! @{ */ #define DCP_CHANNELCTRL_ENABLE_CHANNEL_MASK (0xFFU) #define DCP_CHANNELCTRL_ENABLE_CHANNEL_SHIFT (0U) +/*! ENABLE_CHANNEL + * 0b00000001..CH0 + * 0b00000010..CH1 + * 0b00000100..CH2 + * 0b00001000..CH3 + */ #define DCP_CHANNELCTRL_ENABLE_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_ENABLE_CHANNEL_SHIFT)) & DCP_CHANNELCTRL_ENABLE_CHANNEL_MASK) #define DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL_MASK (0xFF00U) #define DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL_SHIFT (8U) +/*! HIGH_PRIORITY_CHANNEL + * 0b00000001..CH0 + * 0b00000010..CH1 + * 0b00000100..CH2 + * 0b00001000..CH3 + */ #define DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL_SHIFT)) & DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL_MASK) #define DCP_CHANNELCTRL_CH0_IRQ_MERGED_MASK (0x10000U) #define DCP_CHANNELCTRL_CH0_IRQ_MERGED_SHIFT (16U) @@ -6149,8 +9045,10 @@ typedef struct { #define DCP_CHANNELCTRL_RSVD_MASK (0xFFFE0000U) #define DCP_CHANNELCTRL_RSVD_SHIFT (17U) #define DCP_CHANNELCTRL_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_RSVD_SHIFT)) & DCP_CHANNELCTRL_RSVD_MASK) +/*! @} */ /*! @name CAPABILITY0 - DCP capability 0 register */ +/*! @{ */ #define DCP_CAPABILITY0_NUM_KEYS_MASK (0xFFU) #define DCP_CAPABILITY0_NUM_KEYS_SHIFT (0U) #define DCP_CAPABILITY0_NUM_KEYS(x) (((uint32_t)(((uint32_t)(x)) << DCP_CAPABILITY0_NUM_KEYS_SHIFT)) & DCP_CAPABILITY0_NUM_KEYS_MASK) @@ -6166,21 +9064,35 @@ typedef struct { #define DCP_CAPABILITY0_DISABLE_DECRYPT_MASK (0x80000000U) #define DCP_CAPABILITY0_DISABLE_DECRYPT_SHIFT (31U) #define DCP_CAPABILITY0_DISABLE_DECRYPT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CAPABILITY0_DISABLE_DECRYPT_SHIFT)) & DCP_CAPABILITY0_DISABLE_DECRYPT_MASK) +/*! @} */ /*! @name CAPABILITY1 - DCP capability 1 register */ +/*! @{ */ #define DCP_CAPABILITY1_CIPHER_ALGORITHMS_MASK (0xFFFFU) #define DCP_CAPABILITY1_CIPHER_ALGORITHMS_SHIFT (0U) +/*! CIPHER_ALGORITHMS + * 0b0000000000000001..AES128 + */ #define DCP_CAPABILITY1_CIPHER_ALGORITHMS(x) (((uint32_t)(((uint32_t)(x)) << DCP_CAPABILITY1_CIPHER_ALGORITHMS_SHIFT)) & DCP_CAPABILITY1_CIPHER_ALGORITHMS_MASK) #define DCP_CAPABILITY1_HASH_ALGORITHMS_MASK (0xFFFF0000U) #define DCP_CAPABILITY1_HASH_ALGORITHMS_SHIFT (16U) +/*! HASH_ALGORITHMS + * 0b0000000000000001..SHA1 + * 0b0000000000000010..CRC32 + * 0b0000000000000100..SHA256 + */ #define DCP_CAPABILITY1_HASH_ALGORITHMS(x) (((uint32_t)(((uint32_t)(x)) << DCP_CAPABILITY1_HASH_ALGORITHMS_SHIFT)) & DCP_CAPABILITY1_HASH_ALGORITHMS_MASK) +/*! @} */ /*! @name CONTEXT - DCP context buffer pointer */ +/*! @{ */ #define DCP_CONTEXT_ADDR_MASK (0xFFFFFFFFU) #define DCP_CONTEXT_ADDR_SHIFT (0U) #define DCP_CONTEXT_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_CONTEXT_ADDR_SHIFT)) & DCP_CONTEXT_ADDR_MASK) +/*! @} */ /*! @name KEY - DCP key index */ +/*! @{ */ #define DCP_KEY_SUBWORD_MASK (0x3U) #define DCP_KEY_SUBWORD_SHIFT (0U) #define DCP_KEY_SUBWORD(x) (((uint32_t)(((uint32_t)(x)) << DCP_KEY_SUBWORD_SHIFT)) & DCP_KEY_SUBWORD_MASK) @@ -6196,18 +9108,24 @@ typedef struct { #define DCP_KEY_RSVD_MASK (0xFFFFFF00U) #define DCP_KEY_RSVD_SHIFT (8U) #define DCP_KEY_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_KEY_RSVD_SHIFT)) & DCP_KEY_RSVD_MASK) +/*! @} */ /*! @name KEYDATA - DCP key data */ +/*! @{ */ #define DCP_KEYDATA_DATA_MASK (0xFFFFFFFFU) #define DCP_KEYDATA_DATA_SHIFT (0U) #define DCP_KEYDATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << DCP_KEYDATA_DATA_SHIFT)) & DCP_KEYDATA_DATA_MASK) +/*! @} */ /*! @name PACKET0 - DCP work packet 0 status register */ +/*! @{ */ #define DCP_PACKET0_ADDR_MASK (0xFFFFFFFFU) #define DCP_PACKET0_ADDR_SHIFT (0U) #define DCP_PACKET0_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET0_ADDR_SHIFT)) & DCP_PACKET0_ADDR_MASK) +/*! @} */ /*! @name PACKET1 - DCP work packet 1 status register */ +/*! @{ */ #define DCP_PACKET1_INTERRUPT_MASK (0x1U) #define DCP_PACKET1_INTERRUPT_SHIFT (0U) #define DCP_PACKET1_INTERRUPT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_INTERRUPT_SHIFT)) & DCP_PACKET1_INTERRUPT_MASK) @@ -6234,6 +9152,10 @@ typedef struct { #define DCP_PACKET1_ENABLE_BLIT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_ENABLE_BLIT_SHIFT)) & DCP_PACKET1_ENABLE_BLIT_MASK) #define DCP_PACKET1_CIPHER_ENCRYPT_MASK (0x100U) #define DCP_PACKET1_CIPHER_ENCRYPT_SHIFT (8U) +/*! CIPHER_ENCRYPT + * 0b1..ENCRYPT + * 0b0..DECRYPT + */ #define DCP_PACKET1_CIPHER_ENCRYPT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_CIPHER_ENCRYPT_SHIFT)) & DCP_PACKET1_CIPHER_ENCRYPT_MASK) #define DCP_PACKET1_CIPHER_INIT_MASK (0x200U) #define DCP_PACKET1_CIPHER_INIT_SHIFT (9U) @@ -6255,6 +9177,10 @@ typedef struct { #define DCP_PACKET1_CHECK_HASH(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_CHECK_HASH_SHIFT)) & DCP_PACKET1_CHECK_HASH_MASK) #define DCP_PACKET1_HASH_OUTPUT_MASK (0x8000U) #define DCP_PACKET1_HASH_OUTPUT_SHIFT (15U) +/*! HASH_OUTPUT + * 0b0..INPUT + * 0b1..OUTPUT + */ #define DCP_PACKET1_HASH_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_HASH_OUTPUT_SHIFT)) & DCP_PACKET1_HASH_OUTPUT_MASK) #define DCP_PACKET1_CONSTANT_FILL_MASK (0x10000U) #define DCP_PACKET1_CONSTANT_FILL_SHIFT (16U) @@ -6283,19 +9209,41 @@ typedef struct { #define DCP_PACKET1_TAG_MASK (0xFF000000U) #define DCP_PACKET1_TAG_SHIFT (24U) #define DCP_PACKET1_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_TAG_SHIFT)) & DCP_PACKET1_TAG_MASK) +/*! @} */ /*! @name PACKET2 - DCP work packet 2 status register */ +/*! @{ */ #define DCP_PACKET2_CIPHER_SELECT_MASK (0xFU) #define DCP_PACKET2_CIPHER_SELECT_SHIFT (0U) +/*! CIPHER_SELECT + * 0b0000..AES128 + */ #define DCP_PACKET2_CIPHER_SELECT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET2_CIPHER_SELECT_SHIFT)) & DCP_PACKET2_CIPHER_SELECT_MASK) #define DCP_PACKET2_CIPHER_MODE_MASK (0xF0U) #define DCP_PACKET2_CIPHER_MODE_SHIFT (4U) +/*! CIPHER_MODE + * 0b0000..ECB + * 0b0001..CBC + */ #define DCP_PACKET2_CIPHER_MODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET2_CIPHER_MODE_SHIFT)) & DCP_PACKET2_CIPHER_MODE_MASK) #define DCP_PACKET2_KEY_SELECT_MASK (0xFF00U) #define DCP_PACKET2_KEY_SELECT_SHIFT (8U) +/*! KEY_SELECT + * 0b00000000..KEY0 + * 0b00000001..KEY1 + * 0b00000010..KEY2 + * 0b00000011..KEY3 + * 0b11111110..UNIQUE_KEY + * 0b11111111..OTP_KEY + */ #define DCP_PACKET2_KEY_SELECT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET2_KEY_SELECT_SHIFT)) & DCP_PACKET2_KEY_SELECT_MASK) #define DCP_PACKET2_HASH_SELECT_MASK (0xF0000U) #define DCP_PACKET2_HASH_SELECT_SHIFT (16U) +/*! HASH_SELECT + * 0b0000..SHA1 + * 0b0001..CRC32 + * 0b0010..SHA256 + */ #define DCP_PACKET2_HASH_SELECT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET2_HASH_SELECT_SHIFT)) & DCP_PACKET2_HASH_SELECT_MASK) #define DCP_PACKET2_RSVD_MASK (0xF00000U) #define DCP_PACKET2_RSVD_SHIFT (20U) @@ -6303,41 +9251,55 @@ typedef struct { #define DCP_PACKET2_CIPHER_CFG_MASK (0xFF000000U) #define DCP_PACKET2_CIPHER_CFG_SHIFT (24U) #define DCP_PACKET2_CIPHER_CFG(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET2_CIPHER_CFG_SHIFT)) & DCP_PACKET2_CIPHER_CFG_MASK) +/*! @} */ /*! @name PACKET3 - DCP work packet 3 status register */ +/*! @{ */ #define DCP_PACKET3_ADDR_MASK (0xFFFFFFFFU) #define DCP_PACKET3_ADDR_SHIFT (0U) #define DCP_PACKET3_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET3_ADDR_SHIFT)) & DCP_PACKET3_ADDR_MASK) +/*! @} */ /*! @name PACKET4 - DCP work packet 4 status register */ +/*! @{ */ #define DCP_PACKET4_ADDR_MASK (0xFFFFFFFFU) #define DCP_PACKET4_ADDR_SHIFT (0U) #define DCP_PACKET4_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET4_ADDR_SHIFT)) & DCP_PACKET4_ADDR_MASK) +/*! @} */ /*! @name PACKET5 - DCP work packet 5 status register */ +/*! @{ */ #define DCP_PACKET5_COUNT_MASK (0xFFFFFFFFU) #define DCP_PACKET5_COUNT_SHIFT (0U) #define DCP_PACKET5_COUNT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET5_COUNT_SHIFT)) & DCP_PACKET5_COUNT_MASK) +/*! @} */ /*! @name PACKET6 - DCP work packet 6 status register */ +/*! @{ */ #define DCP_PACKET6_ADDR_MASK (0xFFFFFFFFU) #define DCP_PACKET6_ADDR_SHIFT (0U) #define DCP_PACKET6_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET6_ADDR_SHIFT)) & DCP_PACKET6_ADDR_MASK) +/*! @} */ /*! @name CH0CMDPTR - DCP channel 0 command pointer address register */ +/*! @{ */ #define DCP_CH0CMDPTR_ADDR_MASK (0xFFFFFFFFU) #define DCP_CH0CMDPTR_ADDR_SHIFT (0U) #define DCP_CH0CMDPTR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0CMDPTR_ADDR_SHIFT)) & DCP_CH0CMDPTR_ADDR_MASK) +/*! @} */ /*! @name CH0SEMA - DCP channel 0 semaphore register */ +/*! @{ */ #define DCP_CH0SEMA_INCREMENT_MASK (0xFFU) #define DCP_CH0SEMA_INCREMENT_SHIFT (0U) #define DCP_CH0SEMA_INCREMENT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0SEMA_INCREMENT_SHIFT)) & DCP_CH0SEMA_INCREMENT_MASK) #define DCP_CH0SEMA_VALUE_MASK (0xFF0000U) #define DCP_CH0SEMA_VALUE_SHIFT (16U) #define DCP_CH0SEMA_VALUE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0SEMA_VALUE_SHIFT)) & DCP_CH0SEMA_VALUE_MASK) +/*! @} */ /*! @name CH0STAT - DCP channel 0 status register */ +/*! @{ */ #define DCP_CH0STAT_RSVD_COMPLETE_MASK (0x1U) #define DCP_CH0STAT_RSVD_COMPLETE_SHIFT (0U) #define DCP_CH0STAT_RSVD_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_RSVD_COMPLETE_SHIFT)) & DCP_CH0STAT_RSVD_COMPLETE_MASK) @@ -6361,33 +9323,48 @@ typedef struct { #define DCP_CH0STAT_ERROR_PAGEFAULT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_ERROR_PAGEFAULT_SHIFT)) & DCP_CH0STAT_ERROR_PAGEFAULT_MASK) #define DCP_CH0STAT_ERROR_CODE_MASK (0xFF0000U) #define DCP_CH0STAT_ERROR_CODE_SHIFT (16U) +/*! ERROR_CODE + * 0b00000001..Error signalled because the next pointer is 0x00000000 + * 0b00000010..Error signalled because the semaphore is non-zero and neither chain bit is set + * 0b00000011..Error signalled because an error is reported reading/writing the context buffer + * 0b00000100..Error signalled because an error is reported reading/writing the payload + * 0b00000101..Error signalled because the control packet specifies an invalid mode select (for instance, blit + hash) + */ #define DCP_CH0STAT_ERROR_CODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_ERROR_CODE_SHIFT)) & DCP_CH0STAT_ERROR_CODE_MASK) #define DCP_CH0STAT_TAG_MASK (0xFF000000U) #define DCP_CH0STAT_TAG_SHIFT (24U) #define DCP_CH0STAT_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_TAG_SHIFT)) & DCP_CH0STAT_TAG_MASK) +/*! @} */ /*! @name CH0OPTS - DCP channel 0 options register */ +/*! @{ */ #define DCP_CH0OPTS_RECOVERY_TIMER_MASK (0xFFFFU) #define DCP_CH0OPTS_RECOVERY_TIMER_SHIFT (0U) #define DCP_CH0OPTS_RECOVERY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0OPTS_RECOVERY_TIMER_SHIFT)) & DCP_CH0OPTS_RECOVERY_TIMER_MASK) #define DCP_CH0OPTS_RSVD_MASK (0xFFFF0000U) #define DCP_CH0OPTS_RSVD_SHIFT (16U) #define DCP_CH0OPTS_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0OPTS_RSVD_SHIFT)) & DCP_CH0OPTS_RSVD_MASK) +/*! @} */ /*! @name CH1CMDPTR - DCP channel 1 command pointer address register */ +/*! @{ */ #define DCP_CH1CMDPTR_ADDR_MASK (0xFFFFFFFFU) #define DCP_CH1CMDPTR_ADDR_SHIFT (0U) #define DCP_CH1CMDPTR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1CMDPTR_ADDR_SHIFT)) & DCP_CH1CMDPTR_ADDR_MASK) +/*! @} */ /*! @name CH1SEMA - DCP channel 1 semaphore register */ +/*! @{ */ #define DCP_CH1SEMA_INCREMENT_MASK (0xFFU) #define DCP_CH1SEMA_INCREMENT_SHIFT (0U) #define DCP_CH1SEMA_INCREMENT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1SEMA_INCREMENT_SHIFT)) & DCP_CH1SEMA_INCREMENT_MASK) #define DCP_CH1SEMA_VALUE_MASK (0xFF0000U) #define DCP_CH1SEMA_VALUE_SHIFT (16U) #define DCP_CH1SEMA_VALUE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1SEMA_VALUE_SHIFT)) & DCP_CH1SEMA_VALUE_MASK) +/*! @} */ /*! @name CH1STAT - DCP channel 1 status register */ +/*! @{ */ #define DCP_CH1STAT_RSVD_COMPLETE_MASK (0x1U) #define DCP_CH1STAT_RSVD_COMPLETE_SHIFT (0U) #define DCP_CH1STAT_RSVD_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_RSVD_COMPLETE_SHIFT)) & DCP_CH1STAT_RSVD_COMPLETE_MASK) @@ -6411,33 +9388,48 @@ typedef struct { #define DCP_CH1STAT_ERROR_PAGEFAULT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_ERROR_PAGEFAULT_SHIFT)) & DCP_CH1STAT_ERROR_PAGEFAULT_MASK) #define DCP_CH1STAT_ERROR_CODE_MASK (0xFF0000U) #define DCP_CH1STAT_ERROR_CODE_SHIFT (16U) +/*! ERROR_CODE + * 0b00000001..Error is signalled because the next pointer is 0x00000000. + * 0b00000010..Error is signalled because the semaphore is of a non-zero value and neither of the chain bits is set. + * 0b00000011..Error is signalled because an error was reported when reading/writing the context buffer. + * 0b00000100..Error is signalled because an error was reported when reading/writing the payload. + * 0b00000101..Error is signalled because the control packet specifies an invalid mode select (for example, blit + hash). + */ #define DCP_CH1STAT_ERROR_CODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_ERROR_CODE_SHIFT)) & DCP_CH1STAT_ERROR_CODE_MASK) #define DCP_CH1STAT_TAG_MASK (0xFF000000U) #define DCP_CH1STAT_TAG_SHIFT (24U) #define DCP_CH1STAT_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_TAG_SHIFT)) & DCP_CH1STAT_TAG_MASK) +/*! @} */ /*! @name CH1OPTS - DCP channel 1 options register */ +/*! @{ */ #define DCP_CH1OPTS_RECOVERY_TIMER_MASK (0xFFFFU) #define DCP_CH1OPTS_RECOVERY_TIMER_SHIFT (0U) #define DCP_CH1OPTS_RECOVERY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1OPTS_RECOVERY_TIMER_SHIFT)) & DCP_CH1OPTS_RECOVERY_TIMER_MASK) #define DCP_CH1OPTS_RSVD_MASK (0xFFFF0000U) #define DCP_CH1OPTS_RSVD_SHIFT (16U) #define DCP_CH1OPTS_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1OPTS_RSVD_SHIFT)) & DCP_CH1OPTS_RSVD_MASK) +/*! @} */ /*! @name CH2CMDPTR - DCP channel 2 command pointer address register */ +/*! @{ */ #define DCP_CH2CMDPTR_ADDR_MASK (0xFFFFFFFFU) #define DCP_CH2CMDPTR_ADDR_SHIFT (0U) #define DCP_CH2CMDPTR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2CMDPTR_ADDR_SHIFT)) & DCP_CH2CMDPTR_ADDR_MASK) +/*! @} */ /*! @name CH2SEMA - DCP channel 2 semaphore register */ +/*! @{ */ #define DCP_CH2SEMA_INCREMENT_MASK (0xFFU) #define DCP_CH2SEMA_INCREMENT_SHIFT (0U) #define DCP_CH2SEMA_INCREMENT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2SEMA_INCREMENT_SHIFT)) & DCP_CH2SEMA_INCREMENT_MASK) #define DCP_CH2SEMA_VALUE_MASK (0xFF0000U) #define DCP_CH2SEMA_VALUE_SHIFT (16U) #define DCP_CH2SEMA_VALUE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2SEMA_VALUE_SHIFT)) & DCP_CH2SEMA_VALUE_MASK) +/*! @} */ /*! @name CH2STAT - DCP channel 2 status register */ +/*! @{ */ #define DCP_CH2STAT_RSVD_COMPLETE_MASK (0x1U) #define DCP_CH2STAT_RSVD_COMPLETE_SHIFT (0U) #define DCP_CH2STAT_RSVD_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_RSVD_COMPLETE_SHIFT)) & DCP_CH2STAT_RSVD_COMPLETE_MASK) @@ -6461,33 +9453,48 @@ typedef struct { #define DCP_CH2STAT_ERROR_PAGEFAULT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_ERROR_PAGEFAULT_SHIFT)) & DCP_CH2STAT_ERROR_PAGEFAULT_MASK) #define DCP_CH2STAT_ERROR_CODE_MASK (0xFF0000U) #define DCP_CH2STAT_ERROR_CODE_SHIFT (16U) +/*! ERROR_CODE + * 0b00000001..Error is signalled because the next pointer is 0x00000000. + * 0b00000010..Error is signalled because the semaphore is of a non-zero value and neither of the chain bits is set. + * 0b00000011..Error is signalled because an error was reported while reading/writing the context buffer. + * 0b00000100..Error is signalled because an error was reported while reading/writing the payload. + * 0b00000101..Error is signalled because the control packet specifies an invalid mode select (for instance, blit + hash). + */ #define DCP_CH2STAT_ERROR_CODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_ERROR_CODE_SHIFT)) & DCP_CH2STAT_ERROR_CODE_MASK) #define DCP_CH2STAT_TAG_MASK (0xFF000000U) #define DCP_CH2STAT_TAG_SHIFT (24U) #define DCP_CH2STAT_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_TAG_SHIFT)) & DCP_CH2STAT_TAG_MASK) +/*! @} */ /*! @name CH2OPTS - DCP channel 2 options register */ +/*! @{ */ #define DCP_CH2OPTS_RECOVERY_TIMER_MASK (0xFFFFU) #define DCP_CH2OPTS_RECOVERY_TIMER_SHIFT (0U) #define DCP_CH2OPTS_RECOVERY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2OPTS_RECOVERY_TIMER_SHIFT)) & DCP_CH2OPTS_RECOVERY_TIMER_MASK) #define DCP_CH2OPTS_RSVD_MASK (0xFFFF0000U) #define DCP_CH2OPTS_RSVD_SHIFT (16U) #define DCP_CH2OPTS_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2OPTS_RSVD_SHIFT)) & DCP_CH2OPTS_RSVD_MASK) +/*! @} */ /*! @name CH3CMDPTR - DCP channel 3 command pointer address register */ +/*! @{ */ #define DCP_CH3CMDPTR_ADDR_MASK (0xFFFFFFFFU) #define DCP_CH3CMDPTR_ADDR_SHIFT (0U) #define DCP_CH3CMDPTR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3CMDPTR_ADDR_SHIFT)) & DCP_CH3CMDPTR_ADDR_MASK) +/*! @} */ /*! @name CH3SEMA - DCP channel 3 semaphore register */ +/*! @{ */ #define DCP_CH3SEMA_INCREMENT_MASK (0xFFU) #define DCP_CH3SEMA_INCREMENT_SHIFT (0U) #define DCP_CH3SEMA_INCREMENT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3SEMA_INCREMENT_SHIFT)) & DCP_CH3SEMA_INCREMENT_MASK) #define DCP_CH3SEMA_VALUE_MASK (0xFF0000U) #define DCP_CH3SEMA_VALUE_SHIFT (16U) #define DCP_CH3SEMA_VALUE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3SEMA_VALUE_SHIFT)) & DCP_CH3SEMA_VALUE_MASK) +/*! @} */ /*! @name CH3STAT - DCP channel 3 status register */ +/*! @{ */ #define DCP_CH3STAT_RSVD_COMPLETE_MASK (0x1U) #define DCP_CH3STAT_RSVD_COMPLETE_SHIFT (0U) #define DCP_CH3STAT_RSVD_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_RSVD_COMPLETE_SHIFT)) & DCP_CH3STAT_RSVD_COMPLETE_MASK) @@ -6511,33 +9518,55 @@ typedef struct { #define DCP_CH3STAT_ERROR_PAGEFAULT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_ERROR_PAGEFAULT_SHIFT)) & DCP_CH3STAT_ERROR_PAGEFAULT_MASK) #define DCP_CH3STAT_ERROR_CODE_MASK (0xFF0000U) #define DCP_CH3STAT_ERROR_CODE_SHIFT (16U) +/*! ERROR_CODE + * 0b00000001..Error is signalled because the next pointer is 0x00000000. + * 0b00000010..Error is signalled because the semaphore is of a non-zero value and neither of the chain bits is set. + * 0b00000011..Error is signalled because an error was reported while reading/writing the context buffer. + * 0b00000100..Error is signalled because an error was reported while reading/writing the payload. + * 0b00000101..Error is signalled because the control packet specifies an invalid mode select (for example, blit + hash). + */ #define DCP_CH3STAT_ERROR_CODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_ERROR_CODE_SHIFT)) & DCP_CH3STAT_ERROR_CODE_MASK) #define DCP_CH3STAT_TAG_MASK (0xFF000000U) #define DCP_CH3STAT_TAG_SHIFT (24U) #define DCP_CH3STAT_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_TAG_SHIFT)) & DCP_CH3STAT_TAG_MASK) +/*! @} */ /*! @name CH3OPTS - DCP channel 3 options register */ +/*! @{ */ #define DCP_CH3OPTS_RECOVERY_TIMER_MASK (0xFFFFU) #define DCP_CH3OPTS_RECOVERY_TIMER_SHIFT (0U) #define DCP_CH3OPTS_RECOVERY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3OPTS_RECOVERY_TIMER_SHIFT)) & DCP_CH3OPTS_RECOVERY_TIMER_MASK) #define DCP_CH3OPTS_RSVD_MASK (0xFFFF0000U) #define DCP_CH3OPTS_RSVD_SHIFT (16U) #define DCP_CH3OPTS_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3OPTS_RSVD_SHIFT)) & DCP_CH3OPTS_RSVD_MASK) +/*! @} */ /*! @name DBGSELECT - DCP debug select register */ +/*! @{ */ #define DCP_DBGSELECT_INDEX_MASK (0xFFU) #define DCP_DBGSELECT_INDEX_SHIFT (0U) +/*! INDEX + * 0b00000001..CONTROL + * 0b00010000..OTPKEY0 + * 0b00010001..OTPKEY1 + * 0b00010010..OTPKEY2 + * 0b00010011..OTPKEY3 + */ #define DCP_DBGSELECT_INDEX(x) (((uint32_t)(((uint32_t)(x)) << DCP_DBGSELECT_INDEX_SHIFT)) & DCP_DBGSELECT_INDEX_MASK) #define DCP_DBGSELECT_RSVD_MASK (0xFFFFFF00U) #define DCP_DBGSELECT_RSVD_SHIFT (8U) #define DCP_DBGSELECT_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_DBGSELECT_RSVD_SHIFT)) & DCP_DBGSELECT_RSVD_MASK) +/*! @} */ /*! @name DBGDATA - DCP debug data register */ +/*! @{ */ #define DCP_DBGDATA_DATA_MASK (0xFFFFFFFFU) #define DCP_DBGDATA_DATA_SHIFT (0U) #define DCP_DBGDATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << DCP_DBGDATA_DATA_SHIFT)) & DCP_DBGDATA_DATA_MASK) +/*! @} */ /*! @name PAGETABLE - DCP page table register */ +/*! @{ */ #define DCP_PAGETABLE_ENABLE_MASK (0x1U) #define DCP_PAGETABLE_ENABLE_SHIFT (0U) #define DCP_PAGETABLE_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DCP_PAGETABLE_ENABLE_SHIFT)) & DCP_PAGETABLE_ENABLE_MASK) @@ -6547,8 +9576,10 @@ typedef struct { #define DCP_PAGETABLE_BASE_MASK (0xFFFFFFFCU) #define DCP_PAGETABLE_BASE_SHIFT (2U) #define DCP_PAGETABLE_BASE(x) (((uint32_t)(((uint32_t)(x)) << DCP_PAGETABLE_BASE_SHIFT)) & DCP_PAGETABLE_BASE_MASK) +/*! @} */ /*! @name VERSION - DCP version register */ +/*! @{ */ #define DCP_VERSION_STEP_MASK (0xFFFFU) #define DCP_VERSION_STEP_SHIFT (0U) #define DCP_VERSION_STEP(x) (((uint32_t)(((uint32_t)(x)) << DCP_VERSION_STEP_SHIFT)) & DCP_VERSION_STEP_MASK) @@ -6558,6 +9589,7 @@ typedef struct { #define DCP_VERSION_MAJOR_MASK (0xFF000000U) #define DCP_VERSION_MAJOR_SHIFT (24U) #define DCP_VERSION_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << DCP_VERSION_MAJOR_SHIFT)) & DCP_VERSION_MAJOR_MASK) +/*! @} */ /*! @@ -6685,26 +9717,55 @@ typedef struct { */ /*! @name CR - Control Register */ +/*! @{ */ #define DMA_CR_EDBG_MASK (0x2U) #define DMA_CR_EDBG_SHIFT (1U) +/*! EDBG - Enable Debug + * 0b0..When in debug mode, the DMA continues to operate. + * 0b1..When in debug mode, the DMA stalls the start of a new channel. Executing channels are allowed to complete. Channel execution resumes when the system exits debug mode or the EDBG bit is cleared. + */ #define DMA_CR_EDBG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_EDBG_SHIFT)) & DMA_CR_EDBG_MASK) #define DMA_CR_ERCA_MASK (0x4U) #define DMA_CR_ERCA_SHIFT (2U) +/*! ERCA - Enable Round Robin Channel Arbitration + * 0b0..Fixed priority arbitration is used for channel selection within each group. + * 0b1..Round robin arbitration is used for channel selection within each group. + */ #define DMA_CR_ERCA(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ERCA_SHIFT)) & DMA_CR_ERCA_MASK) #define DMA_CR_ERGA_MASK (0x8U) #define DMA_CR_ERGA_SHIFT (3U) +/*! ERGA - Enable Round Robin Group Arbitration + * 0b0..Fixed priority arbitration is used for selection among the groups. + * 0b1..Round robin arbitration is used for selection among the groups. + */ #define DMA_CR_ERGA(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ERGA_SHIFT)) & DMA_CR_ERGA_MASK) #define DMA_CR_HOE_MASK (0x10U) #define DMA_CR_HOE_SHIFT (4U) +/*! HOE - Halt On Error + * 0b0..Normal operation + * 0b1..Any error causes the HALT bit to set. Subsequently, all service requests are ignored until the HALT bit is cleared. + */ #define DMA_CR_HOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_HOE_SHIFT)) & DMA_CR_HOE_MASK) #define DMA_CR_HALT_MASK (0x20U) #define DMA_CR_HALT_SHIFT (5U) +/*! HALT - Halt DMA Operations + * 0b0..Normal operation + * 0b1..Stall the start of any new channels. Executing channels are allowed to complete. Channel execution resumes when this bit is cleared. + */ #define DMA_CR_HALT(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_HALT_SHIFT)) & DMA_CR_HALT_MASK) #define DMA_CR_CLM_MASK (0x40U) #define DMA_CR_CLM_SHIFT (6U) +/*! CLM - Continuous Link Mode + * 0b0..A minor loop channel link made to itself goes through channel arbitration before being activated again. + * 0b1..A minor loop channel link made to itself does not go through channel arbitration before being activated again. Upon minor loop completion, the channel activates again if that channel has a minor loop channel link enabled and the link channel is itself. This effectively applies the minor loop offsets and restarts the next minor loop. + */ #define DMA_CR_CLM(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_CLM_SHIFT)) & DMA_CR_CLM_MASK) #define DMA_CR_EMLM_MASK (0x80U) #define DMA_CR_EMLM_SHIFT (7U) +/*! EMLM - Enable Minor Loop Mapping + * 0b0..Disabled. TCDn.word2 is defined as a 32-bit NBYTES field. + * 0b1..Enabled. TCDn.word2 is redefined to include individual enable fields, an offset field, and the NBYTES field. The individual enable fields allow the minor loop offset to be applied to the source address, the destination address, or both. The NBYTES field is reduced when either offset is enabled. + */ #define DMA_CR_EMLM(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_EMLM_SHIFT)) & DMA_CR_EMLM_MASK) #define DMA_CR_GRP0PRI_MASK (0x100U) #define DMA_CR_GRP0PRI_SHIFT (8U) @@ -6714,732 +9775,1656 @@ typedef struct { #define DMA_CR_GRP1PRI(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_GRP1PRI_SHIFT)) & DMA_CR_GRP1PRI_MASK) #define DMA_CR_ECX_MASK (0x10000U) #define DMA_CR_ECX_SHIFT (16U) +/*! ECX - Error Cancel Transfer + * 0b0..Normal operation + * 0b1..Cancel the remaining data transfer in the same fashion as the CX bit. Stop the executing channel and force the minor loop to finish. The cancel takes effect after the last write of the current read/write sequence. The ECX bit clears itself after the cancel is honored. In addition to cancelling the transfer, ECX treats the cancel as an error condition, thus updating the Error Status register (DMAx_ES) and generating an optional error interrupt. + */ #define DMA_CR_ECX(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ECX_SHIFT)) & DMA_CR_ECX_MASK) #define DMA_CR_CX_MASK (0x20000U) #define DMA_CR_CX_SHIFT (17U) +/*! CX - Cancel Transfer + * 0b0..Normal operation + * 0b1..Cancel the remaining data transfer. Stop the executing channel and force the minor loop to finish. The cancel takes effect after the last write of the current read/write sequence. The CX bit clears itself after the cancel has been honored. This cancel retires the channel normally as if the minor loop was completed. + */ #define DMA_CR_CX(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_CX_SHIFT)) & DMA_CR_CX_MASK) #define DMA_CR_ACTIVE_MASK (0x80000000U) #define DMA_CR_ACTIVE_SHIFT (31U) +/*! ACTIVE - DMA Active Status + * 0b0..eDMA is idle. + * 0b1..eDMA is executing a channel. + */ #define DMA_CR_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ACTIVE_SHIFT)) & DMA_CR_ACTIVE_MASK) +/*! @} */ /*! @name ES - Error Status Register */ +/*! @{ */ #define DMA_ES_DBE_MASK (0x1U) #define DMA_ES_DBE_SHIFT (0U) +/*! DBE - Destination Bus Error + * 0b0..No destination bus error + * 0b1..The last recorded error was a bus error on a destination write + */ #define DMA_ES_DBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DBE_SHIFT)) & DMA_ES_DBE_MASK) #define DMA_ES_SBE_MASK (0x2U) #define DMA_ES_SBE_SHIFT (1U) +/*! SBE - Source Bus Error + * 0b0..No source bus error + * 0b1..The last recorded error was a bus error on a source read + */ #define DMA_ES_SBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SBE_SHIFT)) & DMA_ES_SBE_MASK) #define DMA_ES_SGE_MASK (0x4U) #define DMA_ES_SGE_SHIFT (2U) +/*! SGE - Scatter/Gather Configuration Error + * 0b0..No scatter/gather configuration error + * 0b1..The last recorded error was a configuration error detected in the TCDn_DLASTSGA field. This field is checked at the beginning of a scatter/gather operation after major loop completion if TCDn_CSR[ESG] is enabled. TCDn_DLASTSGA is not on a 32 byte boundary. + */ #define DMA_ES_SGE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SGE_SHIFT)) & DMA_ES_SGE_MASK) #define DMA_ES_NCE_MASK (0x8U) #define DMA_ES_NCE_SHIFT (3U) +/*! NCE - NBYTES/CITER Configuration Error + * 0b0..No NBYTES/CITER configuration error + * 0b1..The last recorded error was a configuration error detected in the TCDn_NBYTES or TCDn_CITER fields. TCDn_NBYTES is not a multiple of TCDn_ATTR[SSIZE] and TCDn_ATTR[DSIZE], or TCDn_CITER[CITER] is equal to zero, or TCDn_CITER[ELINK] is not equal to TCDn_BITER[ELINK] + */ #define DMA_ES_NCE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_NCE_SHIFT)) & DMA_ES_NCE_MASK) #define DMA_ES_DOE_MASK (0x10U) #define DMA_ES_DOE_SHIFT (4U) +/*! DOE - Destination Offset Error + * 0b0..No destination offset configuration error + * 0b1..The last recorded error was a configuration error detected in the TCDn_DOFF field. TCDn_DOFF is inconsistent with TCDn_ATTR[DSIZE]. + */ #define DMA_ES_DOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DOE_SHIFT)) & DMA_ES_DOE_MASK) #define DMA_ES_DAE_MASK (0x20U) #define DMA_ES_DAE_SHIFT (5U) +/*! DAE - Destination Address Error + * 0b0..No destination address configuration error + * 0b1..The last recorded error was a configuration error detected in the TCDn_DADDR field. TCDn_DADDR is inconsistent with TCDn_ATTR[DSIZE]. + */ #define DMA_ES_DAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DAE_SHIFT)) & DMA_ES_DAE_MASK) #define DMA_ES_SOE_MASK (0x40U) #define DMA_ES_SOE_SHIFT (6U) +/*! SOE - Source Offset Error + * 0b0..No source offset configuration error + * 0b1..The last recorded error was a configuration error detected in the TCDn_SOFF field. TCDn_SOFF is inconsistent with TCDn_ATTR[SSIZE]. + */ #define DMA_ES_SOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SOE_SHIFT)) & DMA_ES_SOE_MASK) #define DMA_ES_SAE_MASK (0x80U) #define DMA_ES_SAE_SHIFT (7U) +/*! SAE - Source Address Error + * 0b0..No source address configuration error. + * 0b1..The last recorded error was a configuration error detected in the TCDn_SADDR field. TCDn_SADDR is inconsistent with TCDn_ATTR[SSIZE]. + */ #define DMA_ES_SAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SAE_SHIFT)) & DMA_ES_SAE_MASK) #define DMA_ES_ERRCHN_MASK (0x1F00U) #define DMA_ES_ERRCHN_SHIFT (8U) #define DMA_ES_ERRCHN(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_ERRCHN_SHIFT)) & DMA_ES_ERRCHN_MASK) #define DMA_ES_CPE_MASK (0x4000U) #define DMA_ES_CPE_SHIFT (14U) +/*! CPE - Channel Priority Error + * 0b0..No channel priority error + * 0b1..The last recorded error was a configuration error in the channel priorities within a group. Channel priorities within a group are not unique. + */ #define DMA_ES_CPE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_CPE_SHIFT)) & DMA_ES_CPE_MASK) #define DMA_ES_GPE_MASK (0x8000U) #define DMA_ES_GPE_SHIFT (15U) +/*! GPE - Group Priority Error + * 0b0..No group priority error + * 0b1..The last recorded error was a configuration error among the group priorities. All group priorities are not unique. + */ #define DMA_ES_GPE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_GPE_SHIFT)) & DMA_ES_GPE_MASK) #define DMA_ES_ECX_MASK (0x10000U) #define DMA_ES_ECX_SHIFT (16U) +/*! ECX - Transfer Canceled + * 0b0..No canceled transfers + * 0b1..The last recorded entry was a canceled transfer by the error cancel transfer input + */ #define DMA_ES_ECX(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_ECX_SHIFT)) & DMA_ES_ECX_MASK) #define DMA_ES_VLD_MASK (0x80000000U) #define DMA_ES_VLD_SHIFT (31U) +/*! VLD - VLD + * 0b0..No ERR bits are set. + * 0b1..At least one ERR bit is set indicating a valid error exists that has not been cleared. + */ #define DMA_ES_VLD(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_VLD_SHIFT)) & DMA_ES_VLD_MASK) +/*! @} */ /*! @name ERQ - Enable Request Register */ +/*! @{ */ #define DMA_ERQ_ERQ0_MASK (0x1U) #define DMA_ERQ_ERQ0_SHIFT (0U) +/*! ERQ0 - Enable DMA Request 0 + * 0b0..The DMA request signal for the corresponding channel is disabled + * 0b1..The DMA request signal for the corresponding channel is enabled + */ #define DMA_ERQ_ERQ0(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ0_SHIFT)) & DMA_ERQ_ERQ0_MASK) #define DMA_ERQ_ERQ1_MASK (0x2U) #define DMA_ERQ_ERQ1_SHIFT (1U) +/*! ERQ1 - Enable DMA Request 1 + * 0b0..The DMA request signal for the corresponding channel is disabled + * 0b1..The DMA request signal for the corresponding channel is enabled + */ #define DMA_ERQ_ERQ1(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ1_SHIFT)) & DMA_ERQ_ERQ1_MASK) #define DMA_ERQ_ERQ2_MASK (0x4U) #define DMA_ERQ_ERQ2_SHIFT (2U) +/*! ERQ2 - Enable DMA Request 2 + * 0b0..The DMA request signal for the corresponding channel is disabled + * 0b1..The DMA request signal for the corresponding channel is enabled + */ #define DMA_ERQ_ERQ2(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ2_SHIFT)) & DMA_ERQ_ERQ2_MASK) #define DMA_ERQ_ERQ3_MASK (0x8U) #define DMA_ERQ_ERQ3_SHIFT (3U) +/*! ERQ3 - Enable DMA Request 3 + * 0b0..The DMA request signal for the corresponding channel is disabled + * 0b1..The DMA request signal for the corresponding channel is enabled + */ #define DMA_ERQ_ERQ3(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ3_SHIFT)) & DMA_ERQ_ERQ3_MASK) #define DMA_ERQ_ERQ4_MASK (0x10U) #define DMA_ERQ_ERQ4_SHIFT (4U) +/*! ERQ4 - Enable DMA Request 4 + * 0b0..The DMA request signal for the corresponding channel is disabled + * 0b1..The DMA request signal for the corresponding channel is enabled + */ #define DMA_ERQ_ERQ4(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ4_SHIFT)) & DMA_ERQ_ERQ4_MASK) #define DMA_ERQ_ERQ5_MASK (0x20U) #define DMA_ERQ_ERQ5_SHIFT (5U) +/*! ERQ5 - Enable DMA Request 5 + * 0b0..The DMA request signal for the corresponding channel is disabled + * 0b1..The DMA request signal for the corresponding channel is enabled + */ #define DMA_ERQ_ERQ5(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ5_SHIFT)) & DMA_ERQ_ERQ5_MASK) #define DMA_ERQ_ERQ6_MASK (0x40U) #define DMA_ERQ_ERQ6_SHIFT (6U) +/*! ERQ6 - Enable DMA Request 6 + * 0b0..The DMA request signal for the corresponding channel is disabled + * 0b1..The DMA request signal for the corresponding channel is enabled + */ #define DMA_ERQ_ERQ6(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ6_SHIFT)) & DMA_ERQ_ERQ6_MASK) #define DMA_ERQ_ERQ7_MASK (0x80U) #define DMA_ERQ_ERQ7_SHIFT (7U) +/*! ERQ7 - Enable DMA Request 7 + * 0b0..The DMA request signal for the corresponding channel is disabled + * 0b1..The DMA request signal for the corresponding channel is enabled + */ #define DMA_ERQ_ERQ7(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ7_SHIFT)) & DMA_ERQ_ERQ7_MASK) #define DMA_ERQ_ERQ8_MASK (0x100U) #define DMA_ERQ_ERQ8_SHIFT (8U) +/*! ERQ8 - Enable DMA Request 8 + * 0b0..The DMA request signal for the corresponding channel is disabled + * 0b1..The DMA request signal for the corresponding channel is enabled + */ #define DMA_ERQ_ERQ8(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ8_SHIFT)) & DMA_ERQ_ERQ8_MASK) #define DMA_ERQ_ERQ9_MASK (0x200U) #define DMA_ERQ_ERQ9_SHIFT (9U) +/*! ERQ9 - Enable DMA Request 9 + * 0b0..The DMA request signal for the corresponding channel is disabled + * 0b1..The DMA request signal for the corresponding channel is enabled + */ #define DMA_ERQ_ERQ9(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ9_SHIFT)) & DMA_ERQ_ERQ9_MASK) #define DMA_ERQ_ERQ10_MASK (0x400U) #define DMA_ERQ_ERQ10_SHIFT (10U) +/*! ERQ10 - Enable DMA Request 10 + * 0b0..The DMA request signal for the corresponding channel is disabled + * 0b1..The DMA request signal for the corresponding channel is enabled + */ #define DMA_ERQ_ERQ10(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ10_SHIFT)) & DMA_ERQ_ERQ10_MASK) #define DMA_ERQ_ERQ11_MASK (0x800U) #define DMA_ERQ_ERQ11_SHIFT (11U) +/*! ERQ11 - Enable DMA Request 11 + * 0b0..The DMA request signal for the corresponding channel is disabled + * 0b1..The DMA request signal for the corresponding channel is enabled + */ #define DMA_ERQ_ERQ11(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ11_SHIFT)) & DMA_ERQ_ERQ11_MASK) #define DMA_ERQ_ERQ12_MASK (0x1000U) #define DMA_ERQ_ERQ12_SHIFT (12U) +/*! ERQ12 - Enable DMA Request 12 + * 0b0..The DMA request signal for the corresponding channel is disabled + * 0b1..The DMA request signal for the corresponding channel is enabled + */ #define DMA_ERQ_ERQ12(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ12_SHIFT)) & DMA_ERQ_ERQ12_MASK) #define DMA_ERQ_ERQ13_MASK (0x2000U) #define DMA_ERQ_ERQ13_SHIFT (13U) +/*! ERQ13 - Enable DMA Request 13 + * 0b0..The DMA request signal for the corresponding channel is disabled + * 0b1..The DMA request signal for the corresponding channel is enabled + */ #define DMA_ERQ_ERQ13(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ13_SHIFT)) & DMA_ERQ_ERQ13_MASK) #define DMA_ERQ_ERQ14_MASK (0x4000U) #define DMA_ERQ_ERQ14_SHIFT (14U) +/*! ERQ14 - Enable DMA Request 14 + * 0b0..The DMA request signal for the corresponding channel is disabled + * 0b1..The DMA request signal for the corresponding channel is enabled + */ #define DMA_ERQ_ERQ14(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ14_SHIFT)) & DMA_ERQ_ERQ14_MASK) #define DMA_ERQ_ERQ15_MASK (0x8000U) #define DMA_ERQ_ERQ15_SHIFT (15U) +/*! ERQ15 - Enable DMA Request 15 + * 0b0..The DMA request signal for the corresponding channel is disabled + * 0b1..The DMA request signal for the corresponding channel is enabled + */ #define DMA_ERQ_ERQ15(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ15_SHIFT)) & DMA_ERQ_ERQ15_MASK) #define DMA_ERQ_ERQ16_MASK (0x10000U) #define DMA_ERQ_ERQ16_SHIFT (16U) +/*! ERQ16 - Enable DMA Request 16 + * 0b0..The DMA request signal for the corresponding channel is disabled + * 0b1..The DMA request signal for the corresponding channel is enabled + */ #define DMA_ERQ_ERQ16(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ16_SHIFT)) & DMA_ERQ_ERQ16_MASK) #define DMA_ERQ_ERQ17_MASK (0x20000U) #define DMA_ERQ_ERQ17_SHIFT (17U) +/*! ERQ17 - Enable DMA Request 17 + * 0b0..The DMA request signal for the corresponding channel is disabled + * 0b1..The DMA request signal for the corresponding channel is enabled + */ #define DMA_ERQ_ERQ17(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ17_SHIFT)) & DMA_ERQ_ERQ17_MASK) #define DMA_ERQ_ERQ18_MASK (0x40000U) #define DMA_ERQ_ERQ18_SHIFT (18U) +/*! ERQ18 - Enable DMA Request 18 + * 0b0..The DMA request signal for the corresponding channel is disabled + * 0b1..The DMA request signal for the corresponding channel is enabled + */ #define DMA_ERQ_ERQ18(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ18_SHIFT)) & DMA_ERQ_ERQ18_MASK) #define DMA_ERQ_ERQ19_MASK (0x80000U) #define DMA_ERQ_ERQ19_SHIFT (19U) +/*! ERQ19 - Enable DMA Request 19 + * 0b0..The DMA request signal for the corresponding channel is disabled + * 0b1..The DMA request signal for the corresponding channel is enabled + */ #define DMA_ERQ_ERQ19(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ19_SHIFT)) & DMA_ERQ_ERQ19_MASK) #define DMA_ERQ_ERQ20_MASK (0x100000U) #define DMA_ERQ_ERQ20_SHIFT (20U) +/*! ERQ20 - Enable DMA Request 20 + * 0b0..The DMA request signal for the corresponding channel is disabled + * 0b1..The DMA request signal for the corresponding channel is enabled + */ #define DMA_ERQ_ERQ20(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ20_SHIFT)) & DMA_ERQ_ERQ20_MASK) #define DMA_ERQ_ERQ21_MASK (0x200000U) #define DMA_ERQ_ERQ21_SHIFT (21U) +/*! ERQ21 - Enable DMA Request 21 + * 0b0..The DMA request signal for the corresponding channel is disabled + * 0b1..The DMA request signal for the corresponding channel is enabled + */ #define DMA_ERQ_ERQ21(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ21_SHIFT)) & DMA_ERQ_ERQ21_MASK) #define DMA_ERQ_ERQ22_MASK (0x400000U) #define DMA_ERQ_ERQ22_SHIFT (22U) +/*! ERQ22 - Enable DMA Request 22 + * 0b0..The DMA request signal for the corresponding channel is disabled + * 0b1..The DMA request signal for the corresponding channel is enabled + */ #define DMA_ERQ_ERQ22(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ22_SHIFT)) & DMA_ERQ_ERQ22_MASK) #define DMA_ERQ_ERQ23_MASK (0x800000U) #define DMA_ERQ_ERQ23_SHIFT (23U) +/*! ERQ23 - Enable DMA Request 23 + * 0b0..The DMA request signal for the corresponding channel is disabled + * 0b1..The DMA request signal for the corresponding channel is enabled + */ #define DMA_ERQ_ERQ23(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ23_SHIFT)) & DMA_ERQ_ERQ23_MASK) #define DMA_ERQ_ERQ24_MASK (0x1000000U) #define DMA_ERQ_ERQ24_SHIFT (24U) +/*! ERQ24 - Enable DMA Request 24 + * 0b0..The DMA request signal for the corresponding channel is disabled + * 0b1..The DMA request signal for the corresponding channel is enabled + */ #define DMA_ERQ_ERQ24(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ24_SHIFT)) & DMA_ERQ_ERQ24_MASK) #define DMA_ERQ_ERQ25_MASK (0x2000000U) #define DMA_ERQ_ERQ25_SHIFT (25U) +/*! ERQ25 - Enable DMA Request 25 + * 0b0..The DMA request signal for the corresponding channel is disabled + * 0b1..The DMA request signal for the corresponding channel is enabled + */ #define DMA_ERQ_ERQ25(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ25_SHIFT)) & DMA_ERQ_ERQ25_MASK) #define DMA_ERQ_ERQ26_MASK (0x4000000U) #define DMA_ERQ_ERQ26_SHIFT (26U) +/*! ERQ26 - Enable DMA Request 26 + * 0b0..The DMA request signal for the corresponding channel is disabled + * 0b1..The DMA request signal for the corresponding channel is enabled + */ #define DMA_ERQ_ERQ26(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ26_SHIFT)) & DMA_ERQ_ERQ26_MASK) #define DMA_ERQ_ERQ27_MASK (0x8000000U) #define DMA_ERQ_ERQ27_SHIFT (27U) +/*! ERQ27 - Enable DMA Request 27 + * 0b0..The DMA request signal for the corresponding channel is disabled + * 0b1..The DMA request signal for the corresponding channel is enabled + */ #define DMA_ERQ_ERQ27(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ27_SHIFT)) & DMA_ERQ_ERQ27_MASK) #define DMA_ERQ_ERQ28_MASK (0x10000000U) #define DMA_ERQ_ERQ28_SHIFT (28U) +/*! ERQ28 - Enable DMA Request 28 + * 0b0..The DMA request signal for the corresponding channel is disabled + * 0b1..The DMA request signal for the corresponding channel is enabled + */ #define DMA_ERQ_ERQ28(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ28_SHIFT)) & DMA_ERQ_ERQ28_MASK) #define DMA_ERQ_ERQ29_MASK (0x20000000U) #define DMA_ERQ_ERQ29_SHIFT (29U) +/*! ERQ29 - Enable DMA Request 29 + * 0b0..The DMA request signal for the corresponding channel is disabled + * 0b1..The DMA request signal for the corresponding channel is enabled + */ #define DMA_ERQ_ERQ29(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ29_SHIFT)) & DMA_ERQ_ERQ29_MASK) #define DMA_ERQ_ERQ30_MASK (0x40000000U) #define DMA_ERQ_ERQ30_SHIFT (30U) +/*! ERQ30 - Enable DMA Request 30 + * 0b0..The DMA request signal for the corresponding channel is disabled + * 0b1..The DMA request signal for the corresponding channel is enabled + */ #define DMA_ERQ_ERQ30(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ30_SHIFT)) & DMA_ERQ_ERQ30_MASK) #define DMA_ERQ_ERQ31_MASK (0x80000000U) #define DMA_ERQ_ERQ31_SHIFT (31U) +/*! ERQ31 - Enable DMA Request 31 + * 0b0..The DMA request signal for the corresponding channel is disabled + * 0b1..The DMA request signal for the corresponding channel is enabled + */ #define DMA_ERQ_ERQ31(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ31_SHIFT)) & DMA_ERQ_ERQ31_MASK) +/*! @} */ /*! @name EEI - Enable Error Interrupt Register */ +/*! @{ */ #define DMA_EEI_EEI0_MASK (0x1U) #define DMA_EEI_EEI0_SHIFT (0U) +/*! EEI0 - Enable Error Interrupt 0 + * 0b0..The error signal for corresponding channel does not generate an error interrupt + * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request + */ #define DMA_EEI_EEI0(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI0_SHIFT)) & DMA_EEI_EEI0_MASK) #define DMA_EEI_EEI1_MASK (0x2U) #define DMA_EEI_EEI1_SHIFT (1U) +/*! EEI1 - Enable Error Interrupt 1 + * 0b0..The error signal for corresponding channel does not generate an error interrupt + * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request + */ #define DMA_EEI_EEI1(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI1_SHIFT)) & DMA_EEI_EEI1_MASK) #define DMA_EEI_EEI2_MASK (0x4U) #define DMA_EEI_EEI2_SHIFT (2U) +/*! EEI2 - Enable Error Interrupt 2 + * 0b0..The error signal for corresponding channel does not generate an error interrupt + * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request + */ #define DMA_EEI_EEI2(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI2_SHIFT)) & DMA_EEI_EEI2_MASK) #define DMA_EEI_EEI3_MASK (0x8U) #define DMA_EEI_EEI3_SHIFT (3U) +/*! EEI3 - Enable Error Interrupt 3 + * 0b0..The error signal for corresponding channel does not generate an error interrupt + * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request + */ #define DMA_EEI_EEI3(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI3_SHIFT)) & DMA_EEI_EEI3_MASK) #define DMA_EEI_EEI4_MASK (0x10U) #define DMA_EEI_EEI4_SHIFT (4U) +/*! EEI4 - Enable Error Interrupt 4 + * 0b0..The error signal for corresponding channel does not generate an error interrupt + * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request + */ #define DMA_EEI_EEI4(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI4_SHIFT)) & DMA_EEI_EEI4_MASK) #define DMA_EEI_EEI5_MASK (0x20U) #define DMA_EEI_EEI5_SHIFT (5U) +/*! EEI5 - Enable Error Interrupt 5 + * 0b0..The error signal for corresponding channel does not generate an error interrupt + * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request + */ #define DMA_EEI_EEI5(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI5_SHIFT)) & DMA_EEI_EEI5_MASK) #define DMA_EEI_EEI6_MASK (0x40U) #define DMA_EEI_EEI6_SHIFT (6U) +/*! EEI6 - Enable Error Interrupt 6 + * 0b0..The error signal for corresponding channel does not generate an error interrupt + * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request + */ #define DMA_EEI_EEI6(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI6_SHIFT)) & DMA_EEI_EEI6_MASK) #define DMA_EEI_EEI7_MASK (0x80U) #define DMA_EEI_EEI7_SHIFT (7U) +/*! EEI7 - Enable Error Interrupt 7 + * 0b0..The error signal for corresponding channel does not generate an error interrupt + * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request + */ #define DMA_EEI_EEI7(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI7_SHIFT)) & DMA_EEI_EEI7_MASK) #define DMA_EEI_EEI8_MASK (0x100U) #define DMA_EEI_EEI8_SHIFT (8U) +/*! EEI8 - Enable Error Interrupt 8 + * 0b0..The error signal for corresponding channel does not generate an error interrupt + * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request + */ #define DMA_EEI_EEI8(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI8_SHIFT)) & DMA_EEI_EEI8_MASK) #define DMA_EEI_EEI9_MASK (0x200U) #define DMA_EEI_EEI9_SHIFT (9U) +/*! EEI9 - Enable Error Interrupt 9 + * 0b0..The error signal for corresponding channel does not generate an error interrupt + * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request + */ #define DMA_EEI_EEI9(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI9_SHIFT)) & DMA_EEI_EEI9_MASK) #define DMA_EEI_EEI10_MASK (0x400U) #define DMA_EEI_EEI10_SHIFT (10U) +/*! EEI10 - Enable Error Interrupt 10 + * 0b0..The error signal for corresponding channel does not generate an error interrupt + * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request + */ #define DMA_EEI_EEI10(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI10_SHIFT)) & DMA_EEI_EEI10_MASK) #define DMA_EEI_EEI11_MASK (0x800U) #define DMA_EEI_EEI11_SHIFT (11U) +/*! EEI11 - Enable Error Interrupt 11 + * 0b0..The error signal for corresponding channel does not generate an error interrupt + * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request + */ #define DMA_EEI_EEI11(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI11_SHIFT)) & DMA_EEI_EEI11_MASK) #define DMA_EEI_EEI12_MASK (0x1000U) #define DMA_EEI_EEI12_SHIFT (12U) +/*! EEI12 - Enable Error Interrupt 12 + * 0b0..The error signal for corresponding channel does not generate an error interrupt + * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request + */ #define DMA_EEI_EEI12(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI12_SHIFT)) & DMA_EEI_EEI12_MASK) #define DMA_EEI_EEI13_MASK (0x2000U) #define DMA_EEI_EEI13_SHIFT (13U) +/*! EEI13 - Enable Error Interrupt 13 + * 0b0..The error signal for corresponding channel does not generate an error interrupt + * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request + */ #define DMA_EEI_EEI13(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI13_SHIFT)) & DMA_EEI_EEI13_MASK) #define DMA_EEI_EEI14_MASK (0x4000U) #define DMA_EEI_EEI14_SHIFT (14U) +/*! EEI14 - Enable Error Interrupt 14 + * 0b0..The error signal for corresponding channel does not generate an error interrupt + * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request + */ #define DMA_EEI_EEI14(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI14_SHIFT)) & DMA_EEI_EEI14_MASK) #define DMA_EEI_EEI15_MASK (0x8000U) #define DMA_EEI_EEI15_SHIFT (15U) +/*! EEI15 - Enable Error Interrupt 15 + * 0b0..The error signal for corresponding channel does not generate an error interrupt + * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request + */ #define DMA_EEI_EEI15(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI15_SHIFT)) & DMA_EEI_EEI15_MASK) #define DMA_EEI_EEI16_MASK (0x10000U) #define DMA_EEI_EEI16_SHIFT (16U) +/*! EEI16 - Enable Error Interrupt 16 + * 0b0..The error signal for corresponding channel does not generate an error interrupt + * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request + */ #define DMA_EEI_EEI16(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI16_SHIFT)) & DMA_EEI_EEI16_MASK) #define DMA_EEI_EEI17_MASK (0x20000U) #define DMA_EEI_EEI17_SHIFT (17U) +/*! EEI17 - Enable Error Interrupt 17 + * 0b0..The error signal for corresponding channel does not generate an error interrupt + * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request + */ #define DMA_EEI_EEI17(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI17_SHIFT)) & DMA_EEI_EEI17_MASK) #define DMA_EEI_EEI18_MASK (0x40000U) #define DMA_EEI_EEI18_SHIFT (18U) +/*! EEI18 - Enable Error Interrupt 18 + * 0b0..The error signal for corresponding channel does not generate an error interrupt + * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request + */ #define DMA_EEI_EEI18(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI18_SHIFT)) & DMA_EEI_EEI18_MASK) #define DMA_EEI_EEI19_MASK (0x80000U) #define DMA_EEI_EEI19_SHIFT (19U) +/*! EEI19 - Enable Error Interrupt 19 + * 0b0..The error signal for corresponding channel does not generate an error interrupt + * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request + */ #define DMA_EEI_EEI19(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI19_SHIFT)) & DMA_EEI_EEI19_MASK) #define DMA_EEI_EEI20_MASK (0x100000U) #define DMA_EEI_EEI20_SHIFT (20U) +/*! EEI20 - Enable Error Interrupt 20 + * 0b0..The error signal for corresponding channel does not generate an error interrupt + * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request + */ #define DMA_EEI_EEI20(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI20_SHIFT)) & DMA_EEI_EEI20_MASK) #define DMA_EEI_EEI21_MASK (0x200000U) #define DMA_EEI_EEI21_SHIFT (21U) +/*! EEI21 - Enable Error Interrupt 21 + * 0b0..The error signal for corresponding channel does not generate an error interrupt + * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request + */ #define DMA_EEI_EEI21(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI21_SHIFT)) & DMA_EEI_EEI21_MASK) #define DMA_EEI_EEI22_MASK (0x400000U) #define DMA_EEI_EEI22_SHIFT (22U) +/*! EEI22 - Enable Error Interrupt 22 + * 0b0..The error signal for corresponding channel does not generate an error interrupt + * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request + */ #define DMA_EEI_EEI22(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI22_SHIFT)) & DMA_EEI_EEI22_MASK) #define DMA_EEI_EEI23_MASK (0x800000U) #define DMA_EEI_EEI23_SHIFT (23U) +/*! EEI23 - Enable Error Interrupt 23 + * 0b0..The error signal for corresponding channel does not generate an error interrupt + * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request + */ #define DMA_EEI_EEI23(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI23_SHIFT)) & DMA_EEI_EEI23_MASK) #define DMA_EEI_EEI24_MASK (0x1000000U) #define DMA_EEI_EEI24_SHIFT (24U) +/*! EEI24 - Enable Error Interrupt 24 + * 0b0..The error signal for corresponding channel does not generate an error interrupt + * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request + */ #define DMA_EEI_EEI24(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI24_SHIFT)) & DMA_EEI_EEI24_MASK) #define DMA_EEI_EEI25_MASK (0x2000000U) #define DMA_EEI_EEI25_SHIFT (25U) +/*! EEI25 - Enable Error Interrupt 25 + * 0b0..The error signal for corresponding channel does not generate an error interrupt + * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request + */ #define DMA_EEI_EEI25(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI25_SHIFT)) & DMA_EEI_EEI25_MASK) #define DMA_EEI_EEI26_MASK (0x4000000U) #define DMA_EEI_EEI26_SHIFT (26U) +/*! EEI26 - Enable Error Interrupt 26 + * 0b0..The error signal for corresponding channel does not generate an error interrupt + * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request + */ #define DMA_EEI_EEI26(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI26_SHIFT)) & DMA_EEI_EEI26_MASK) #define DMA_EEI_EEI27_MASK (0x8000000U) #define DMA_EEI_EEI27_SHIFT (27U) +/*! EEI27 - Enable Error Interrupt 27 + * 0b0..The error signal for corresponding channel does not generate an error interrupt + * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request + */ #define DMA_EEI_EEI27(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI27_SHIFT)) & DMA_EEI_EEI27_MASK) #define DMA_EEI_EEI28_MASK (0x10000000U) #define DMA_EEI_EEI28_SHIFT (28U) +/*! EEI28 - Enable Error Interrupt 28 + * 0b0..The error signal for corresponding channel does not generate an error interrupt + * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request + */ #define DMA_EEI_EEI28(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI28_SHIFT)) & DMA_EEI_EEI28_MASK) #define DMA_EEI_EEI29_MASK (0x20000000U) #define DMA_EEI_EEI29_SHIFT (29U) +/*! EEI29 - Enable Error Interrupt 29 + * 0b0..The error signal for corresponding channel does not generate an error interrupt + * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request + */ #define DMA_EEI_EEI29(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI29_SHIFT)) & DMA_EEI_EEI29_MASK) #define DMA_EEI_EEI30_MASK (0x40000000U) #define DMA_EEI_EEI30_SHIFT (30U) +/*! EEI30 - Enable Error Interrupt 30 + * 0b0..The error signal for corresponding channel does not generate an error interrupt + * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request + */ #define DMA_EEI_EEI30(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI30_SHIFT)) & DMA_EEI_EEI30_MASK) #define DMA_EEI_EEI31_MASK (0x80000000U) #define DMA_EEI_EEI31_SHIFT (31U) +/*! EEI31 - Enable Error Interrupt 31 + * 0b0..The error signal for corresponding channel does not generate an error interrupt + * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request + */ #define DMA_EEI_EEI31(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI31_SHIFT)) & DMA_EEI_EEI31_MASK) +/*! @} */ /*! @name CEEI - Clear Enable Error Interrupt Register */ +/*! @{ */ #define DMA_CEEI_CEEI_MASK (0x1FU) #define DMA_CEEI_CEEI_SHIFT (0U) #define DMA_CEEI_CEEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_CEEI_SHIFT)) & DMA_CEEI_CEEI_MASK) #define DMA_CEEI_CAEE_MASK (0x40U) #define DMA_CEEI_CAEE_SHIFT (6U) +/*! CAEE - Clear All Enable Error Interrupts + * 0b0..Clear only the EEI bit specified in the CEEI field + * 0b1..Clear all bits in EEI + */ #define DMA_CEEI_CAEE(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_CAEE_SHIFT)) & DMA_CEEI_CAEE_MASK) #define DMA_CEEI_NOP_MASK (0x80U) #define DMA_CEEI_NOP_SHIFT (7U) +/*! NOP - No Op enable + * 0b0..Normal operation + * 0b1..No operation, ignore the other bits in this register + */ #define DMA_CEEI_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_NOP_SHIFT)) & DMA_CEEI_NOP_MASK) +/*! @} */ /*! @name SEEI - Set Enable Error Interrupt Register */ +/*! @{ */ #define DMA_SEEI_SEEI_MASK (0x1FU) #define DMA_SEEI_SEEI_SHIFT (0U) #define DMA_SEEI_SEEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_SEEI_SHIFT)) & DMA_SEEI_SEEI_MASK) #define DMA_SEEI_SAEE_MASK (0x40U) #define DMA_SEEI_SAEE_SHIFT (6U) +/*! SAEE - Sets All Enable Error Interrupts + * 0b0..Set only the EEI bit specified in the SEEI field. + * 0b1..Sets all bits in EEI + */ #define DMA_SEEI_SAEE(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_SAEE_SHIFT)) & DMA_SEEI_SAEE_MASK) #define DMA_SEEI_NOP_MASK (0x80U) #define DMA_SEEI_NOP_SHIFT (7U) +/*! NOP - No Op enable + * 0b0..Normal operation + * 0b1..No operation, ignore the other bits in this register + */ #define DMA_SEEI_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_NOP_SHIFT)) & DMA_SEEI_NOP_MASK) +/*! @} */ /*! @name CERQ - Clear Enable Request Register */ +/*! @{ */ #define DMA_CERQ_CERQ_MASK (0x1FU) #define DMA_CERQ_CERQ_SHIFT (0U) #define DMA_CERQ_CERQ(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_CERQ_SHIFT)) & DMA_CERQ_CERQ_MASK) #define DMA_CERQ_CAER_MASK (0x40U) #define DMA_CERQ_CAER_SHIFT (6U) +/*! CAER - Clear All Enable Requests + * 0b0..Clear only the ERQ bit specified in the CERQ field + * 0b1..Clear all bits in ERQ + */ #define DMA_CERQ_CAER(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_CAER_SHIFT)) & DMA_CERQ_CAER_MASK) #define DMA_CERQ_NOP_MASK (0x80U) #define DMA_CERQ_NOP_SHIFT (7U) +/*! NOP - No Op enable + * 0b0..Normal operation + * 0b1..No operation, ignore the other bits in this register + */ #define DMA_CERQ_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_NOP_SHIFT)) & DMA_CERQ_NOP_MASK) +/*! @} */ /*! @name SERQ - Set Enable Request Register */ +/*! @{ */ #define DMA_SERQ_SERQ_MASK (0x1FU) #define DMA_SERQ_SERQ_SHIFT (0U) #define DMA_SERQ_SERQ(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_SERQ_SHIFT)) & DMA_SERQ_SERQ_MASK) #define DMA_SERQ_SAER_MASK (0x40U) #define DMA_SERQ_SAER_SHIFT (6U) +/*! SAER - Set All Enable Requests + * 0b0..Set only the ERQ bit specified in the SERQ field + * 0b1..Set all bits in ERQ + */ #define DMA_SERQ_SAER(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_SAER_SHIFT)) & DMA_SERQ_SAER_MASK) #define DMA_SERQ_NOP_MASK (0x80U) #define DMA_SERQ_NOP_SHIFT (7U) +/*! NOP - No Op enable + * 0b0..Normal operation + * 0b1..No operation, ignore the other bits in this register + */ #define DMA_SERQ_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_NOP_SHIFT)) & DMA_SERQ_NOP_MASK) +/*! @} */ /*! @name CDNE - Clear DONE Status Bit Register */ +/*! @{ */ #define DMA_CDNE_CDNE_MASK (0x1FU) #define DMA_CDNE_CDNE_SHIFT (0U) #define DMA_CDNE_CDNE(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_CDNE_SHIFT)) & DMA_CDNE_CDNE_MASK) #define DMA_CDNE_CADN_MASK (0x40U) #define DMA_CDNE_CADN_SHIFT (6U) +/*! CADN - Clears All DONE Bits + * 0b0..Clears only the TCDn_CSR[DONE] bit specified in the CDNE field + * 0b1..Clears all bits in TCDn_CSR[DONE] + */ #define DMA_CDNE_CADN(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_CADN_SHIFT)) & DMA_CDNE_CADN_MASK) #define DMA_CDNE_NOP_MASK (0x80U) #define DMA_CDNE_NOP_SHIFT (7U) +/*! NOP - No Op enable + * 0b0..Normal operation + * 0b1..No operation, ignore the other bits in this register + */ #define DMA_CDNE_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_NOP_SHIFT)) & DMA_CDNE_NOP_MASK) +/*! @} */ /*! @name SSRT - Set START Bit Register */ +/*! @{ */ #define DMA_SSRT_SSRT_MASK (0x1FU) #define DMA_SSRT_SSRT_SHIFT (0U) #define DMA_SSRT_SSRT(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_SSRT_SHIFT)) & DMA_SSRT_SSRT_MASK) #define DMA_SSRT_SAST_MASK (0x40U) #define DMA_SSRT_SAST_SHIFT (6U) +/*! SAST - Set All START Bits (activates all channels) + * 0b0..Set only the TCDn_CSR[START] bit specified in the SSRT field + * 0b1..Set all bits in TCDn_CSR[START] + */ #define DMA_SSRT_SAST(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_SAST_SHIFT)) & DMA_SSRT_SAST_MASK) #define DMA_SSRT_NOP_MASK (0x80U) #define DMA_SSRT_NOP_SHIFT (7U) +/*! NOP - No Op enable + * 0b0..Normal operation + * 0b1..No operation, ignore the other bits in this register + */ #define DMA_SSRT_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_NOP_SHIFT)) & DMA_SSRT_NOP_MASK) +/*! @} */ /*! @name CERR - Clear Error Register */ +/*! @{ */ #define DMA_CERR_CERR_MASK (0x1FU) #define DMA_CERR_CERR_SHIFT (0U) #define DMA_CERR_CERR(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_CERR_SHIFT)) & DMA_CERR_CERR_MASK) #define DMA_CERR_CAEI_MASK (0x40U) #define DMA_CERR_CAEI_SHIFT (6U) +/*! CAEI - Clear All Error Indicators + * 0b0..Clear only the ERR bit specified in the CERR field + * 0b1..Clear all bits in ERR + */ #define DMA_CERR_CAEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_CAEI_SHIFT)) & DMA_CERR_CAEI_MASK) #define DMA_CERR_NOP_MASK (0x80U) #define DMA_CERR_NOP_SHIFT (7U) +/*! NOP - No Op enable + * 0b0..Normal operation + * 0b1..No operation, ignore the other bits in this register + */ #define DMA_CERR_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_NOP_SHIFT)) & DMA_CERR_NOP_MASK) +/*! @} */ /*! @name CINT - Clear Interrupt Request Register */ +/*! @{ */ #define DMA_CINT_CINT_MASK (0x1FU) #define DMA_CINT_CINT_SHIFT (0U) #define DMA_CINT_CINT(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_CINT_SHIFT)) & DMA_CINT_CINT_MASK) #define DMA_CINT_CAIR_MASK (0x40U) #define DMA_CINT_CAIR_SHIFT (6U) +/*! CAIR - Clear All Interrupt Requests + * 0b0..Clear only the INT bit specified in the CINT field + * 0b1..Clear all bits in INT + */ #define DMA_CINT_CAIR(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_CAIR_SHIFT)) & DMA_CINT_CAIR_MASK) #define DMA_CINT_NOP_MASK (0x80U) #define DMA_CINT_NOP_SHIFT (7U) +/*! NOP - No Op enable + * 0b0..Normal operation + * 0b1..No operation, ignore the other bits in this register + */ #define DMA_CINT_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_NOP_SHIFT)) & DMA_CINT_NOP_MASK) +/*! @} */ /*! @name INT - Interrupt Request Register */ +/*! @{ */ #define DMA_INT_INT0_MASK (0x1U) #define DMA_INT_INT0_SHIFT (0U) +/*! INT0 - Interrupt Request 0 + * 0b0..The interrupt request for corresponding channel is cleared + * 0b1..The interrupt request for corresponding channel is active + */ #define DMA_INT_INT0(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT0_SHIFT)) & DMA_INT_INT0_MASK) #define DMA_INT_INT1_MASK (0x2U) #define DMA_INT_INT1_SHIFT (1U) +/*! INT1 - Interrupt Request 1 + * 0b0..The interrupt request for corresponding channel is cleared + * 0b1..The interrupt request for corresponding channel is active + */ #define DMA_INT_INT1(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT1_SHIFT)) & DMA_INT_INT1_MASK) #define DMA_INT_INT2_MASK (0x4U) #define DMA_INT_INT2_SHIFT (2U) +/*! INT2 - Interrupt Request 2 + * 0b0..The interrupt request for corresponding channel is cleared + * 0b1..The interrupt request for corresponding channel is active + */ #define DMA_INT_INT2(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT2_SHIFT)) & DMA_INT_INT2_MASK) #define DMA_INT_INT3_MASK (0x8U) #define DMA_INT_INT3_SHIFT (3U) +/*! INT3 - Interrupt Request 3 + * 0b0..The interrupt request for corresponding channel is cleared + * 0b1..The interrupt request for corresponding channel is active + */ #define DMA_INT_INT3(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT3_SHIFT)) & DMA_INT_INT3_MASK) #define DMA_INT_INT4_MASK (0x10U) #define DMA_INT_INT4_SHIFT (4U) +/*! INT4 - Interrupt Request 4 + * 0b0..The interrupt request for corresponding channel is cleared + * 0b1..The interrupt request for corresponding channel is active + */ #define DMA_INT_INT4(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT4_SHIFT)) & DMA_INT_INT4_MASK) #define DMA_INT_INT5_MASK (0x20U) #define DMA_INT_INT5_SHIFT (5U) +/*! INT5 - Interrupt Request 5 + * 0b0..The interrupt request for corresponding channel is cleared + * 0b1..The interrupt request for corresponding channel is active + */ #define DMA_INT_INT5(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT5_SHIFT)) & DMA_INT_INT5_MASK) #define DMA_INT_INT6_MASK (0x40U) #define DMA_INT_INT6_SHIFT (6U) +/*! INT6 - Interrupt Request 6 + * 0b0..The interrupt request for corresponding channel is cleared + * 0b1..The interrupt request for corresponding channel is active + */ #define DMA_INT_INT6(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT6_SHIFT)) & DMA_INT_INT6_MASK) #define DMA_INT_INT7_MASK (0x80U) #define DMA_INT_INT7_SHIFT (7U) +/*! INT7 - Interrupt Request 7 + * 0b0..The interrupt request for corresponding channel is cleared + * 0b1..The interrupt request for corresponding channel is active + */ #define DMA_INT_INT7(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT7_SHIFT)) & DMA_INT_INT7_MASK) #define DMA_INT_INT8_MASK (0x100U) #define DMA_INT_INT8_SHIFT (8U) +/*! INT8 - Interrupt Request 8 + * 0b0..The interrupt request for corresponding channel is cleared + * 0b1..The interrupt request for corresponding channel is active + */ #define DMA_INT_INT8(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT8_SHIFT)) & DMA_INT_INT8_MASK) #define DMA_INT_INT9_MASK (0x200U) #define DMA_INT_INT9_SHIFT (9U) +/*! INT9 - Interrupt Request 9 + * 0b0..The interrupt request for corresponding channel is cleared + * 0b1..The interrupt request for corresponding channel is active + */ #define DMA_INT_INT9(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT9_SHIFT)) & DMA_INT_INT9_MASK) #define DMA_INT_INT10_MASK (0x400U) #define DMA_INT_INT10_SHIFT (10U) +/*! INT10 - Interrupt Request 10 + * 0b0..The interrupt request for corresponding channel is cleared + * 0b1..The interrupt request for corresponding channel is active + */ #define DMA_INT_INT10(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT10_SHIFT)) & DMA_INT_INT10_MASK) #define DMA_INT_INT11_MASK (0x800U) #define DMA_INT_INT11_SHIFT (11U) +/*! INT11 - Interrupt Request 11 + * 0b0..The interrupt request for corresponding channel is cleared + * 0b1..The interrupt request for corresponding channel is active + */ #define DMA_INT_INT11(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT11_SHIFT)) & DMA_INT_INT11_MASK) #define DMA_INT_INT12_MASK (0x1000U) #define DMA_INT_INT12_SHIFT (12U) +/*! INT12 - Interrupt Request 12 + * 0b0..The interrupt request for corresponding channel is cleared + * 0b1..The interrupt request for corresponding channel is active + */ #define DMA_INT_INT12(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT12_SHIFT)) & DMA_INT_INT12_MASK) #define DMA_INT_INT13_MASK (0x2000U) #define DMA_INT_INT13_SHIFT (13U) +/*! INT13 - Interrupt Request 13 + * 0b0..The interrupt request for corresponding channel is cleared + * 0b1..The interrupt request for corresponding channel is active + */ #define DMA_INT_INT13(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT13_SHIFT)) & DMA_INT_INT13_MASK) #define DMA_INT_INT14_MASK (0x4000U) #define DMA_INT_INT14_SHIFT (14U) +/*! INT14 - Interrupt Request 14 + * 0b0..The interrupt request for corresponding channel is cleared + * 0b1..The interrupt request for corresponding channel is active + */ #define DMA_INT_INT14(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT14_SHIFT)) & DMA_INT_INT14_MASK) #define DMA_INT_INT15_MASK (0x8000U) #define DMA_INT_INT15_SHIFT (15U) +/*! INT15 - Interrupt Request 15 + * 0b0..The interrupt request for corresponding channel is cleared + * 0b1..The interrupt request for corresponding channel is active + */ #define DMA_INT_INT15(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT15_SHIFT)) & DMA_INT_INT15_MASK) #define DMA_INT_INT16_MASK (0x10000U) #define DMA_INT_INT16_SHIFT (16U) +/*! INT16 - Interrupt Request 16 + * 0b0..The interrupt request for corresponding channel is cleared + * 0b1..The interrupt request for corresponding channel is active + */ #define DMA_INT_INT16(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT16_SHIFT)) & DMA_INT_INT16_MASK) #define DMA_INT_INT17_MASK (0x20000U) #define DMA_INT_INT17_SHIFT (17U) +/*! INT17 - Interrupt Request 17 + * 0b0..The interrupt request for corresponding channel is cleared + * 0b1..The interrupt request for corresponding channel is active + */ #define DMA_INT_INT17(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT17_SHIFT)) & DMA_INT_INT17_MASK) #define DMA_INT_INT18_MASK (0x40000U) #define DMA_INT_INT18_SHIFT (18U) +/*! INT18 - Interrupt Request 18 + * 0b0..The interrupt request for corresponding channel is cleared + * 0b1..The interrupt request for corresponding channel is active + */ #define DMA_INT_INT18(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT18_SHIFT)) & DMA_INT_INT18_MASK) #define DMA_INT_INT19_MASK (0x80000U) #define DMA_INT_INT19_SHIFT (19U) +/*! INT19 - Interrupt Request 19 + * 0b0..The interrupt request for corresponding channel is cleared + * 0b1..The interrupt request for corresponding channel is active + */ #define DMA_INT_INT19(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT19_SHIFT)) & DMA_INT_INT19_MASK) #define DMA_INT_INT20_MASK (0x100000U) #define DMA_INT_INT20_SHIFT (20U) +/*! INT20 - Interrupt Request 20 + * 0b0..The interrupt request for corresponding channel is cleared + * 0b1..The interrupt request for corresponding channel is active + */ #define DMA_INT_INT20(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT20_SHIFT)) & DMA_INT_INT20_MASK) #define DMA_INT_INT21_MASK (0x200000U) #define DMA_INT_INT21_SHIFT (21U) +/*! INT21 - Interrupt Request 21 + * 0b0..The interrupt request for corresponding channel is cleared + * 0b1..The interrupt request for corresponding channel is active + */ #define DMA_INT_INT21(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT21_SHIFT)) & DMA_INT_INT21_MASK) #define DMA_INT_INT22_MASK (0x400000U) #define DMA_INT_INT22_SHIFT (22U) +/*! INT22 - Interrupt Request 22 + * 0b0..The interrupt request for corresponding channel is cleared + * 0b1..The interrupt request for corresponding channel is active + */ #define DMA_INT_INT22(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT22_SHIFT)) & DMA_INT_INT22_MASK) #define DMA_INT_INT23_MASK (0x800000U) #define DMA_INT_INT23_SHIFT (23U) +/*! INT23 - Interrupt Request 23 + * 0b0..The interrupt request for corresponding channel is cleared + * 0b1..The interrupt request for corresponding channel is active + */ #define DMA_INT_INT23(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT23_SHIFT)) & DMA_INT_INT23_MASK) #define DMA_INT_INT24_MASK (0x1000000U) #define DMA_INT_INT24_SHIFT (24U) +/*! INT24 - Interrupt Request 24 + * 0b0..The interrupt request for corresponding channel is cleared + * 0b1..The interrupt request for corresponding channel is active + */ #define DMA_INT_INT24(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT24_SHIFT)) & DMA_INT_INT24_MASK) #define DMA_INT_INT25_MASK (0x2000000U) #define DMA_INT_INT25_SHIFT (25U) +/*! INT25 - Interrupt Request 25 + * 0b0..The interrupt request for corresponding channel is cleared + * 0b1..The interrupt request for corresponding channel is active + */ #define DMA_INT_INT25(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT25_SHIFT)) & DMA_INT_INT25_MASK) #define DMA_INT_INT26_MASK (0x4000000U) #define DMA_INT_INT26_SHIFT (26U) +/*! INT26 - Interrupt Request 26 + * 0b0..The interrupt request for corresponding channel is cleared + * 0b1..The interrupt request for corresponding channel is active + */ #define DMA_INT_INT26(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT26_SHIFT)) & DMA_INT_INT26_MASK) #define DMA_INT_INT27_MASK (0x8000000U) #define DMA_INT_INT27_SHIFT (27U) +/*! INT27 - Interrupt Request 27 + * 0b0..The interrupt request for corresponding channel is cleared + * 0b1..The interrupt request for corresponding channel is active + */ #define DMA_INT_INT27(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT27_SHIFT)) & DMA_INT_INT27_MASK) #define DMA_INT_INT28_MASK (0x10000000U) #define DMA_INT_INT28_SHIFT (28U) +/*! INT28 - Interrupt Request 28 + * 0b0..The interrupt request for corresponding channel is cleared + * 0b1..The interrupt request for corresponding channel is active + */ #define DMA_INT_INT28(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT28_SHIFT)) & DMA_INT_INT28_MASK) #define DMA_INT_INT29_MASK (0x20000000U) #define DMA_INT_INT29_SHIFT (29U) +/*! INT29 - Interrupt Request 29 + * 0b0..The interrupt request for corresponding channel is cleared + * 0b1..The interrupt request for corresponding channel is active + */ #define DMA_INT_INT29(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT29_SHIFT)) & DMA_INT_INT29_MASK) #define DMA_INT_INT30_MASK (0x40000000U) #define DMA_INT_INT30_SHIFT (30U) +/*! INT30 - Interrupt Request 30 + * 0b0..The interrupt request for corresponding channel is cleared + * 0b1..The interrupt request for corresponding channel is active + */ #define DMA_INT_INT30(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT30_SHIFT)) & DMA_INT_INT30_MASK) #define DMA_INT_INT31_MASK (0x80000000U) #define DMA_INT_INT31_SHIFT (31U) +/*! INT31 - Interrupt Request 31 + * 0b0..The interrupt request for corresponding channel is cleared + * 0b1..The interrupt request for corresponding channel is active + */ #define DMA_INT_INT31(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT31_SHIFT)) & DMA_INT_INT31_MASK) +/*! @} */ /*! @name ERR - Error Register */ +/*! @{ */ #define DMA_ERR_ERR0_MASK (0x1U) #define DMA_ERR_ERR0_SHIFT (0U) +/*! ERR0 - Error In Channel 0 + * 0b0..An error in this channel has not occurred + * 0b1..An error in this channel has occurred + */ #define DMA_ERR_ERR0(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR0_SHIFT)) & DMA_ERR_ERR0_MASK) #define DMA_ERR_ERR1_MASK (0x2U) #define DMA_ERR_ERR1_SHIFT (1U) +/*! ERR1 - Error In Channel 1 + * 0b0..An error in this channel has not occurred + * 0b1..An error in this channel has occurred + */ #define DMA_ERR_ERR1(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR1_SHIFT)) & DMA_ERR_ERR1_MASK) #define DMA_ERR_ERR2_MASK (0x4U) #define DMA_ERR_ERR2_SHIFT (2U) +/*! ERR2 - Error In Channel 2 + * 0b0..An error in this channel has not occurred + * 0b1..An error in this channel has occurred + */ #define DMA_ERR_ERR2(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR2_SHIFT)) & DMA_ERR_ERR2_MASK) #define DMA_ERR_ERR3_MASK (0x8U) #define DMA_ERR_ERR3_SHIFT (3U) +/*! ERR3 - Error In Channel 3 + * 0b0..An error in this channel has not occurred + * 0b1..An error in this channel has occurred + */ #define DMA_ERR_ERR3(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR3_SHIFT)) & DMA_ERR_ERR3_MASK) #define DMA_ERR_ERR4_MASK (0x10U) #define DMA_ERR_ERR4_SHIFT (4U) +/*! ERR4 - Error In Channel 4 + * 0b0..An error in this channel has not occurred + * 0b1..An error in this channel has occurred + */ #define DMA_ERR_ERR4(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR4_SHIFT)) & DMA_ERR_ERR4_MASK) #define DMA_ERR_ERR5_MASK (0x20U) #define DMA_ERR_ERR5_SHIFT (5U) +/*! ERR5 - Error In Channel 5 + * 0b0..An error in this channel has not occurred + * 0b1..An error in this channel has occurred + */ #define DMA_ERR_ERR5(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR5_SHIFT)) & DMA_ERR_ERR5_MASK) #define DMA_ERR_ERR6_MASK (0x40U) #define DMA_ERR_ERR6_SHIFT (6U) +/*! ERR6 - Error In Channel 6 + * 0b0..An error in this channel has not occurred + * 0b1..An error in this channel has occurred + */ #define DMA_ERR_ERR6(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR6_SHIFT)) & DMA_ERR_ERR6_MASK) #define DMA_ERR_ERR7_MASK (0x80U) #define DMA_ERR_ERR7_SHIFT (7U) +/*! ERR7 - Error In Channel 7 + * 0b0..An error in this channel has not occurred + * 0b1..An error in this channel has occurred + */ #define DMA_ERR_ERR7(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR7_SHIFT)) & DMA_ERR_ERR7_MASK) #define DMA_ERR_ERR8_MASK (0x100U) #define DMA_ERR_ERR8_SHIFT (8U) +/*! ERR8 - Error In Channel 8 + * 0b0..An error in this channel has not occurred + * 0b1..An error in this channel has occurred + */ #define DMA_ERR_ERR8(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR8_SHIFT)) & DMA_ERR_ERR8_MASK) #define DMA_ERR_ERR9_MASK (0x200U) #define DMA_ERR_ERR9_SHIFT (9U) +/*! ERR9 - Error In Channel 9 + * 0b0..An error in this channel has not occurred + * 0b1..An error in this channel has occurred + */ #define DMA_ERR_ERR9(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR9_SHIFT)) & DMA_ERR_ERR9_MASK) #define DMA_ERR_ERR10_MASK (0x400U) #define DMA_ERR_ERR10_SHIFT (10U) +/*! ERR10 - Error In Channel 10 + * 0b0..An error in this channel has not occurred + * 0b1..An error in this channel has occurred + */ #define DMA_ERR_ERR10(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR10_SHIFT)) & DMA_ERR_ERR10_MASK) #define DMA_ERR_ERR11_MASK (0x800U) #define DMA_ERR_ERR11_SHIFT (11U) +/*! ERR11 - Error In Channel 11 + * 0b0..An error in this channel has not occurred + * 0b1..An error in this channel has occurred + */ #define DMA_ERR_ERR11(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR11_SHIFT)) & DMA_ERR_ERR11_MASK) #define DMA_ERR_ERR12_MASK (0x1000U) #define DMA_ERR_ERR12_SHIFT (12U) +/*! ERR12 - Error In Channel 12 + * 0b0..An error in this channel has not occurred + * 0b1..An error in this channel has occurred + */ #define DMA_ERR_ERR12(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR12_SHIFT)) & DMA_ERR_ERR12_MASK) #define DMA_ERR_ERR13_MASK (0x2000U) #define DMA_ERR_ERR13_SHIFT (13U) +/*! ERR13 - Error In Channel 13 + * 0b0..An error in this channel has not occurred + * 0b1..An error in this channel has occurred + */ #define DMA_ERR_ERR13(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR13_SHIFT)) & DMA_ERR_ERR13_MASK) #define DMA_ERR_ERR14_MASK (0x4000U) #define DMA_ERR_ERR14_SHIFT (14U) +/*! ERR14 - Error In Channel 14 + * 0b0..An error in this channel has not occurred + * 0b1..An error in this channel has occurred + */ #define DMA_ERR_ERR14(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR14_SHIFT)) & DMA_ERR_ERR14_MASK) #define DMA_ERR_ERR15_MASK (0x8000U) #define DMA_ERR_ERR15_SHIFT (15U) +/*! ERR15 - Error In Channel 15 + * 0b0..An error in this channel has not occurred + * 0b1..An error in this channel has occurred + */ #define DMA_ERR_ERR15(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR15_SHIFT)) & DMA_ERR_ERR15_MASK) #define DMA_ERR_ERR16_MASK (0x10000U) #define DMA_ERR_ERR16_SHIFT (16U) +/*! ERR16 - Error In Channel 16 + * 0b0..An error in this channel has not occurred + * 0b1..An error in this channel has occurred + */ #define DMA_ERR_ERR16(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR16_SHIFT)) & DMA_ERR_ERR16_MASK) #define DMA_ERR_ERR17_MASK (0x20000U) #define DMA_ERR_ERR17_SHIFT (17U) +/*! ERR17 - Error In Channel 17 + * 0b0..An error in this channel has not occurred + * 0b1..An error in this channel has occurred + */ #define DMA_ERR_ERR17(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR17_SHIFT)) & DMA_ERR_ERR17_MASK) #define DMA_ERR_ERR18_MASK (0x40000U) #define DMA_ERR_ERR18_SHIFT (18U) +/*! ERR18 - Error In Channel 18 + * 0b0..An error in this channel has not occurred + * 0b1..An error in this channel has occurred + */ #define DMA_ERR_ERR18(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR18_SHIFT)) & DMA_ERR_ERR18_MASK) #define DMA_ERR_ERR19_MASK (0x80000U) #define DMA_ERR_ERR19_SHIFT (19U) +/*! ERR19 - Error In Channel 19 + * 0b0..An error in this channel has not occurred + * 0b1..An error in this channel has occurred + */ #define DMA_ERR_ERR19(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR19_SHIFT)) & DMA_ERR_ERR19_MASK) #define DMA_ERR_ERR20_MASK (0x100000U) #define DMA_ERR_ERR20_SHIFT (20U) +/*! ERR20 - Error In Channel 20 + * 0b0..An error in this channel has not occurred + * 0b1..An error in this channel has occurred + */ #define DMA_ERR_ERR20(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR20_SHIFT)) & DMA_ERR_ERR20_MASK) #define DMA_ERR_ERR21_MASK (0x200000U) #define DMA_ERR_ERR21_SHIFT (21U) +/*! ERR21 - Error In Channel 21 + * 0b0..An error in this channel has not occurred + * 0b1..An error in this channel has occurred + */ #define DMA_ERR_ERR21(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR21_SHIFT)) & DMA_ERR_ERR21_MASK) #define DMA_ERR_ERR22_MASK (0x400000U) #define DMA_ERR_ERR22_SHIFT (22U) +/*! ERR22 - Error In Channel 22 + * 0b0..An error in this channel has not occurred + * 0b1..An error in this channel has occurred + */ #define DMA_ERR_ERR22(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR22_SHIFT)) & DMA_ERR_ERR22_MASK) #define DMA_ERR_ERR23_MASK (0x800000U) #define DMA_ERR_ERR23_SHIFT (23U) +/*! ERR23 - Error In Channel 23 + * 0b0..An error in this channel has not occurred + * 0b1..An error in this channel has occurred + */ #define DMA_ERR_ERR23(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR23_SHIFT)) & DMA_ERR_ERR23_MASK) #define DMA_ERR_ERR24_MASK (0x1000000U) #define DMA_ERR_ERR24_SHIFT (24U) +/*! ERR24 - Error In Channel 24 + * 0b0..An error in this channel has not occurred + * 0b1..An error in this channel has occurred + */ #define DMA_ERR_ERR24(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR24_SHIFT)) & DMA_ERR_ERR24_MASK) #define DMA_ERR_ERR25_MASK (0x2000000U) #define DMA_ERR_ERR25_SHIFT (25U) +/*! ERR25 - Error In Channel 25 + * 0b0..An error in this channel has not occurred + * 0b1..An error in this channel has occurred + */ #define DMA_ERR_ERR25(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR25_SHIFT)) & DMA_ERR_ERR25_MASK) #define DMA_ERR_ERR26_MASK (0x4000000U) #define DMA_ERR_ERR26_SHIFT (26U) +/*! ERR26 - Error In Channel 26 + * 0b0..An error in this channel has not occurred + * 0b1..An error in this channel has occurred + */ #define DMA_ERR_ERR26(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR26_SHIFT)) & DMA_ERR_ERR26_MASK) #define DMA_ERR_ERR27_MASK (0x8000000U) #define DMA_ERR_ERR27_SHIFT (27U) +/*! ERR27 - Error In Channel 27 + * 0b0..An error in this channel has not occurred + * 0b1..An error in this channel has occurred + */ #define DMA_ERR_ERR27(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR27_SHIFT)) & DMA_ERR_ERR27_MASK) #define DMA_ERR_ERR28_MASK (0x10000000U) #define DMA_ERR_ERR28_SHIFT (28U) +/*! ERR28 - Error In Channel 28 + * 0b0..An error in this channel has not occurred + * 0b1..An error in this channel has occurred + */ #define DMA_ERR_ERR28(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR28_SHIFT)) & DMA_ERR_ERR28_MASK) #define DMA_ERR_ERR29_MASK (0x20000000U) #define DMA_ERR_ERR29_SHIFT (29U) +/*! ERR29 - Error In Channel 29 + * 0b0..An error in this channel has not occurred + * 0b1..An error in this channel has occurred + */ #define DMA_ERR_ERR29(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR29_SHIFT)) & DMA_ERR_ERR29_MASK) #define DMA_ERR_ERR30_MASK (0x40000000U) #define DMA_ERR_ERR30_SHIFT (30U) +/*! ERR30 - Error In Channel 30 + * 0b0..An error in this channel has not occurred + * 0b1..An error in this channel has occurred + */ #define DMA_ERR_ERR30(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR30_SHIFT)) & DMA_ERR_ERR30_MASK) #define DMA_ERR_ERR31_MASK (0x80000000U) #define DMA_ERR_ERR31_SHIFT (31U) +/*! ERR31 - Error In Channel 31 + * 0b0..An error in this channel has not occurred + * 0b1..An error in this channel has occurred + */ #define DMA_ERR_ERR31(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR31_SHIFT)) & DMA_ERR_ERR31_MASK) +/*! @} */ /*! @name HRS - Hardware Request Status Register */ +/*! @{ */ #define DMA_HRS_HRS0_MASK (0x1U) #define DMA_HRS_HRS0_SHIFT (0U) +/*! HRS0 - Hardware Request Status Channel 0 + * 0b0..A hardware service request for channel 0 is not present + * 0b1..A hardware service request for channel 0 is present + */ #define DMA_HRS_HRS0(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS0_SHIFT)) & DMA_HRS_HRS0_MASK) #define DMA_HRS_HRS1_MASK (0x2U) #define DMA_HRS_HRS1_SHIFT (1U) +/*! HRS1 - Hardware Request Status Channel 1 + * 0b0..A hardware service request for channel 1 is not present + * 0b1..A hardware service request for channel 1 is present + */ #define DMA_HRS_HRS1(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS1_SHIFT)) & DMA_HRS_HRS1_MASK) #define DMA_HRS_HRS2_MASK (0x4U) #define DMA_HRS_HRS2_SHIFT (2U) +/*! HRS2 - Hardware Request Status Channel 2 + * 0b0..A hardware service request for channel 2 is not present + * 0b1..A hardware service request for channel 2 is present + */ #define DMA_HRS_HRS2(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS2_SHIFT)) & DMA_HRS_HRS2_MASK) #define DMA_HRS_HRS3_MASK (0x8U) #define DMA_HRS_HRS3_SHIFT (3U) +/*! HRS3 - Hardware Request Status Channel 3 + * 0b0..A hardware service request for channel 3 is not present + * 0b1..A hardware service request for channel 3 is present + */ #define DMA_HRS_HRS3(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS3_SHIFT)) & DMA_HRS_HRS3_MASK) #define DMA_HRS_HRS4_MASK (0x10U) #define DMA_HRS_HRS4_SHIFT (4U) +/*! HRS4 - Hardware Request Status Channel 4 + * 0b0..A hardware service request for channel 4 is not present + * 0b1..A hardware service request for channel 4 is present + */ #define DMA_HRS_HRS4(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS4_SHIFT)) & DMA_HRS_HRS4_MASK) #define DMA_HRS_HRS5_MASK (0x20U) #define DMA_HRS_HRS5_SHIFT (5U) +/*! HRS5 - Hardware Request Status Channel 5 + * 0b0..A hardware service request for channel 5 is not present + * 0b1..A hardware service request for channel 5 is present + */ #define DMA_HRS_HRS5(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS5_SHIFT)) & DMA_HRS_HRS5_MASK) #define DMA_HRS_HRS6_MASK (0x40U) #define DMA_HRS_HRS6_SHIFT (6U) +/*! HRS6 - Hardware Request Status Channel 6 + * 0b0..A hardware service request for channel 6 is not present + * 0b1..A hardware service request for channel 6 is present + */ #define DMA_HRS_HRS6(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS6_SHIFT)) & DMA_HRS_HRS6_MASK) #define DMA_HRS_HRS7_MASK (0x80U) #define DMA_HRS_HRS7_SHIFT (7U) +/*! HRS7 - Hardware Request Status Channel 7 + * 0b0..A hardware service request for channel 7 is not present + * 0b1..A hardware service request for channel 7 is present + */ #define DMA_HRS_HRS7(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS7_SHIFT)) & DMA_HRS_HRS7_MASK) #define DMA_HRS_HRS8_MASK (0x100U) #define DMA_HRS_HRS8_SHIFT (8U) +/*! HRS8 - Hardware Request Status Channel 8 + * 0b0..A hardware service request for channel 8 is not present + * 0b1..A hardware service request for channel 8 is present + */ #define DMA_HRS_HRS8(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS8_SHIFT)) & DMA_HRS_HRS8_MASK) #define DMA_HRS_HRS9_MASK (0x200U) #define DMA_HRS_HRS9_SHIFT (9U) +/*! HRS9 - Hardware Request Status Channel 9 + * 0b0..A hardware service request for channel 9 is not present + * 0b1..A hardware service request for channel 9 is present + */ #define DMA_HRS_HRS9(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS9_SHIFT)) & DMA_HRS_HRS9_MASK) #define DMA_HRS_HRS10_MASK (0x400U) #define DMA_HRS_HRS10_SHIFT (10U) +/*! HRS10 - Hardware Request Status Channel 10 + * 0b0..A hardware service request for channel 10 is not present + * 0b1..A hardware service request for channel 10 is present + */ #define DMA_HRS_HRS10(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS10_SHIFT)) & DMA_HRS_HRS10_MASK) #define DMA_HRS_HRS11_MASK (0x800U) #define DMA_HRS_HRS11_SHIFT (11U) +/*! HRS11 - Hardware Request Status Channel 11 + * 0b0..A hardware service request for channel 11 is not present + * 0b1..A hardware service request for channel 11 is present + */ #define DMA_HRS_HRS11(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS11_SHIFT)) & DMA_HRS_HRS11_MASK) #define DMA_HRS_HRS12_MASK (0x1000U) #define DMA_HRS_HRS12_SHIFT (12U) +/*! HRS12 - Hardware Request Status Channel 12 + * 0b0..A hardware service request for channel 12 is not present + * 0b1..A hardware service request for channel 12 is present + */ #define DMA_HRS_HRS12(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS12_SHIFT)) & DMA_HRS_HRS12_MASK) #define DMA_HRS_HRS13_MASK (0x2000U) #define DMA_HRS_HRS13_SHIFT (13U) +/*! HRS13 - Hardware Request Status Channel 13 + * 0b0..A hardware service request for channel 13 is not present + * 0b1..A hardware service request for channel 13 is present + */ #define DMA_HRS_HRS13(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS13_SHIFT)) & DMA_HRS_HRS13_MASK) #define DMA_HRS_HRS14_MASK (0x4000U) #define DMA_HRS_HRS14_SHIFT (14U) +/*! HRS14 - Hardware Request Status Channel 14 + * 0b0..A hardware service request for channel 14 is not present + * 0b1..A hardware service request for channel 14 is present + */ #define DMA_HRS_HRS14(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS14_SHIFT)) & DMA_HRS_HRS14_MASK) #define DMA_HRS_HRS15_MASK (0x8000U) #define DMA_HRS_HRS15_SHIFT (15U) +/*! HRS15 - Hardware Request Status Channel 15 + * 0b0..A hardware service request for channel 15 is not present + * 0b1..A hardware service request for channel 15 is present + */ #define DMA_HRS_HRS15(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS15_SHIFT)) & DMA_HRS_HRS15_MASK) #define DMA_HRS_HRS16_MASK (0x10000U) #define DMA_HRS_HRS16_SHIFT (16U) +/*! HRS16 - Hardware Request Status Channel 16 + * 0b0..A hardware service request for channel 16 is not present + * 0b1..A hardware service request for channel 16 is present + */ #define DMA_HRS_HRS16(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS16_SHIFT)) & DMA_HRS_HRS16_MASK) #define DMA_HRS_HRS17_MASK (0x20000U) #define DMA_HRS_HRS17_SHIFT (17U) +/*! HRS17 - Hardware Request Status Channel 17 + * 0b0..A hardware service request for channel 17 is not present + * 0b1..A hardware service request for channel 17 is present + */ #define DMA_HRS_HRS17(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS17_SHIFT)) & DMA_HRS_HRS17_MASK) #define DMA_HRS_HRS18_MASK (0x40000U) #define DMA_HRS_HRS18_SHIFT (18U) +/*! HRS18 - Hardware Request Status Channel 18 + * 0b0..A hardware service request for channel 18 is not present + * 0b1..A hardware service request for channel 18 is present + */ #define DMA_HRS_HRS18(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS18_SHIFT)) & DMA_HRS_HRS18_MASK) #define DMA_HRS_HRS19_MASK (0x80000U) #define DMA_HRS_HRS19_SHIFT (19U) +/*! HRS19 - Hardware Request Status Channel 19 + * 0b0..A hardware service request for channel 19 is not present + * 0b1..A hardware service request for channel 19 is present + */ #define DMA_HRS_HRS19(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS19_SHIFT)) & DMA_HRS_HRS19_MASK) #define DMA_HRS_HRS20_MASK (0x100000U) #define DMA_HRS_HRS20_SHIFT (20U) +/*! HRS20 - Hardware Request Status Channel 20 + * 0b0..A hardware service request for channel 20 is not present + * 0b1..A hardware service request for channel 20 is present + */ #define DMA_HRS_HRS20(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS20_SHIFT)) & DMA_HRS_HRS20_MASK) #define DMA_HRS_HRS21_MASK (0x200000U) #define DMA_HRS_HRS21_SHIFT (21U) +/*! HRS21 - Hardware Request Status Channel 21 + * 0b0..A hardware service request for channel 21 is not present + * 0b1..A hardware service request for channel 21 is present + */ #define DMA_HRS_HRS21(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS21_SHIFT)) & DMA_HRS_HRS21_MASK) #define DMA_HRS_HRS22_MASK (0x400000U) #define DMA_HRS_HRS22_SHIFT (22U) +/*! HRS22 - Hardware Request Status Channel 22 + * 0b0..A hardware service request for channel 22 is not present + * 0b1..A hardware service request for channel 22 is present + */ #define DMA_HRS_HRS22(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS22_SHIFT)) & DMA_HRS_HRS22_MASK) #define DMA_HRS_HRS23_MASK (0x800000U) #define DMA_HRS_HRS23_SHIFT (23U) +/*! HRS23 - Hardware Request Status Channel 23 + * 0b0..A hardware service request for channel 23 is not present + * 0b1..A hardware service request for channel 23 is present + */ #define DMA_HRS_HRS23(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS23_SHIFT)) & DMA_HRS_HRS23_MASK) #define DMA_HRS_HRS24_MASK (0x1000000U) #define DMA_HRS_HRS24_SHIFT (24U) +/*! HRS24 - Hardware Request Status Channel 24 + * 0b0..A hardware service request for channel 24 is not present + * 0b1..A hardware service request for channel 24 is present + */ #define DMA_HRS_HRS24(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS24_SHIFT)) & DMA_HRS_HRS24_MASK) #define DMA_HRS_HRS25_MASK (0x2000000U) #define DMA_HRS_HRS25_SHIFT (25U) +/*! HRS25 - Hardware Request Status Channel 25 + * 0b0..A hardware service request for channel 25 is not present + * 0b1..A hardware service request for channel 25 is present + */ #define DMA_HRS_HRS25(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS25_SHIFT)) & DMA_HRS_HRS25_MASK) #define DMA_HRS_HRS26_MASK (0x4000000U) #define DMA_HRS_HRS26_SHIFT (26U) +/*! HRS26 - Hardware Request Status Channel 26 + * 0b0..A hardware service request for channel 26 is not present + * 0b1..A hardware service request for channel 26 is present + */ #define DMA_HRS_HRS26(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS26_SHIFT)) & DMA_HRS_HRS26_MASK) #define DMA_HRS_HRS27_MASK (0x8000000U) #define DMA_HRS_HRS27_SHIFT (27U) +/*! HRS27 - Hardware Request Status Channel 27 + * 0b0..A hardware service request for channel 27 is not present + * 0b1..A hardware service request for channel 27 is present + */ #define DMA_HRS_HRS27(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS27_SHIFT)) & DMA_HRS_HRS27_MASK) #define DMA_HRS_HRS28_MASK (0x10000000U) #define DMA_HRS_HRS28_SHIFT (28U) +/*! HRS28 - Hardware Request Status Channel 28 + * 0b0..A hardware service request for channel 28 is not present + * 0b1..A hardware service request for channel 28 is present + */ #define DMA_HRS_HRS28(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS28_SHIFT)) & DMA_HRS_HRS28_MASK) #define DMA_HRS_HRS29_MASK (0x20000000U) #define DMA_HRS_HRS29_SHIFT (29U) +/*! HRS29 - Hardware Request Status Channel 29 + * 0b0..A hardware service request for channel 29 is not preset + * 0b1..A hardware service request for channel 29 is present + */ #define DMA_HRS_HRS29(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS29_SHIFT)) & DMA_HRS_HRS29_MASK) #define DMA_HRS_HRS30_MASK (0x40000000U) #define DMA_HRS_HRS30_SHIFT (30U) +/*! HRS30 - Hardware Request Status Channel 30 + * 0b0..A hardware service request for channel 30 is not present + * 0b1..A hardware service request for channel 30 is present + */ #define DMA_HRS_HRS30(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS30_SHIFT)) & DMA_HRS_HRS30_MASK) #define DMA_HRS_HRS31_MASK (0x80000000U) #define DMA_HRS_HRS31_SHIFT (31U) +/*! HRS31 - Hardware Request Status Channel 31 + * 0b0..A hardware service request for channel 31 is not present + * 0b1..A hardware service request for channel 31 is present + */ #define DMA_HRS_HRS31(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS31_SHIFT)) & DMA_HRS_HRS31_MASK) +/*! @} */ /*! @name EARS - Enable Asynchronous Request in Stop Register */ +/*! @{ */ #define DMA_EARS_EDREQ_0_MASK (0x1U) #define DMA_EARS_EDREQ_0_SHIFT (0U) +/*! EDREQ_0 - Enable asynchronous DMA request in stop mode for channel 0. + * 0b0..Disable asynchronous DMA request for channel 0. + * 0b1..Enable asynchronous DMA request for channel 0. + */ #define DMA_EARS_EDREQ_0(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_0_SHIFT)) & DMA_EARS_EDREQ_0_MASK) #define DMA_EARS_EDREQ_1_MASK (0x2U) #define DMA_EARS_EDREQ_1_SHIFT (1U) +/*! EDREQ_1 - Enable asynchronous DMA request in stop mode for channel 1. + * 0b0..Disable asynchronous DMA request for channel 1 + * 0b1..Enable asynchronous DMA request for channel 1. + */ #define DMA_EARS_EDREQ_1(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_1_SHIFT)) & DMA_EARS_EDREQ_1_MASK) #define DMA_EARS_EDREQ_2_MASK (0x4U) #define DMA_EARS_EDREQ_2_SHIFT (2U) +/*! EDREQ_2 - Enable asynchronous DMA request in stop mode for channel 2. + * 0b0..Disable asynchronous DMA request for channel 2. + * 0b1..Enable asynchronous DMA request for channel 2. + */ #define DMA_EARS_EDREQ_2(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_2_SHIFT)) & DMA_EARS_EDREQ_2_MASK) #define DMA_EARS_EDREQ_3_MASK (0x8U) #define DMA_EARS_EDREQ_3_SHIFT (3U) +/*! EDREQ_3 - Enable asynchronous DMA request in stop mode for channel 3. + * 0b0..Disable asynchronous DMA request for channel 3. + * 0b1..Enable asynchronous DMA request for channel 3. + */ #define DMA_EARS_EDREQ_3(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_3_SHIFT)) & DMA_EARS_EDREQ_3_MASK) #define DMA_EARS_EDREQ_4_MASK (0x10U) #define DMA_EARS_EDREQ_4_SHIFT (4U) +/*! EDREQ_4 - Enable asynchronous DMA request in stop mode for channel 4 + * 0b0..Disable asynchronous DMA request for channel 4. + * 0b1..Enable asynchronous DMA request for channel 4. + */ #define DMA_EARS_EDREQ_4(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_4_SHIFT)) & DMA_EARS_EDREQ_4_MASK) #define DMA_EARS_EDREQ_5_MASK (0x20U) #define DMA_EARS_EDREQ_5_SHIFT (5U) +/*! EDREQ_5 - Enable asynchronous DMA request in stop mode for channel 5 + * 0b0..Disable asynchronous DMA request for channel 5. + * 0b1..Enable asynchronous DMA request for channel 5. + */ #define DMA_EARS_EDREQ_5(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_5_SHIFT)) & DMA_EARS_EDREQ_5_MASK) #define DMA_EARS_EDREQ_6_MASK (0x40U) #define DMA_EARS_EDREQ_6_SHIFT (6U) +/*! EDREQ_6 - Enable asynchronous DMA request in stop mode for channel 6 + * 0b0..Disable asynchronous DMA request for channel 6. + * 0b1..Enable asynchronous DMA request for channel 6. + */ #define DMA_EARS_EDREQ_6(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_6_SHIFT)) & DMA_EARS_EDREQ_6_MASK) #define DMA_EARS_EDREQ_7_MASK (0x80U) #define DMA_EARS_EDREQ_7_SHIFT (7U) +/*! EDREQ_7 - Enable asynchronous DMA request in stop mode for channel 7 + * 0b0..Disable asynchronous DMA request for channel 7. + * 0b1..Enable asynchronous DMA request for channel 7. + */ #define DMA_EARS_EDREQ_7(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_7_SHIFT)) & DMA_EARS_EDREQ_7_MASK) #define DMA_EARS_EDREQ_8_MASK (0x100U) #define DMA_EARS_EDREQ_8_SHIFT (8U) +/*! EDREQ_8 - Enable asynchronous DMA request in stop mode for channel 8 + * 0b0..Disable asynchronous DMA request for channel 8. + * 0b1..Enable asynchronous DMA request for channel 8. + */ #define DMA_EARS_EDREQ_8(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_8_SHIFT)) & DMA_EARS_EDREQ_8_MASK) #define DMA_EARS_EDREQ_9_MASK (0x200U) #define DMA_EARS_EDREQ_9_SHIFT (9U) +/*! EDREQ_9 - Enable asynchronous DMA request in stop mode for channel 9 + * 0b0..Disable asynchronous DMA request for channel 9. + * 0b1..Enable asynchronous DMA request for channel 9. + */ #define DMA_EARS_EDREQ_9(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_9_SHIFT)) & DMA_EARS_EDREQ_9_MASK) #define DMA_EARS_EDREQ_10_MASK (0x400U) #define DMA_EARS_EDREQ_10_SHIFT (10U) +/*! EDREQ_10 - Enable asynchronous DMA request in stop mode for channel 10 + * 0b0..Disable asynchronous DMA request for channel 10. + * 0b1..Enable asynchronous DMA request for channel 10. + */ #define DMA_EARS_EDREQ_10(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_10_SHIFT)) & DMA_EARS_EDREQ_10_MASK) #define DMA_EARS_EDREQ_11_MASK (0x800U) #define DMA_EARS_EDREQ_11_SHIFT (11U) +/*! EDREQ_11 - Enable asynchronous DMA request in stop mode for channel 11 + * 0b0..Disable asynchronous DMA request for channel 11. + * 0b1..Enable asynchronous DMA request for channel 11. + */ #define DMA_EARS_EDREQ_11(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_11_SHIFT)) & DMA_EARS_EDREQ_11_MASK) #define DMA_EARS_EDREQ_12_MASK (0x1000U) #define DMA_EARS_EDREQ_12_SHIFT (12U) +/*! EDREQ_12 - Enable asynchronous DMA request in stop mode for channel 12 + * 0b0..Disable asynchronous DMA request for channel 12. + * 0b1..Enable asynchronous DMA request for channel 12. + */ #define DMA_EARS_EDREQ_12(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_12_SHIFT)) & DMA_EARS_EDREQ_12_MASK) #define DMA_EARS_EDREQ_13_MASK (0x2000U) #define DMA_EARS_EDREQ_13_SHIFT (13U) +/*! EDREQ_13 - Enable asynchronous DMA request in stop mode for channel 13 + * 0b0..Disable asynchronous DMA request for channel 13. + * 0b1..Enable asynchronous DMA request for channel 13. + */ #define DMA_EARS_EDREQ_13(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_13_SHIFT)) & DMA_EARS_EDREQ_13_MASK) #define DMA_EARS_EDREQ_14_MASK (0x4000U) #define DMA_EARS_EDREQ_14_SHIFT (14U) +/*! EDREQ_14 - Enable asynchronous DMA request in stop mode for channel 14 + * 0b0..Disable asynchronous DMA request for channel 14. + * 0b1..Enable asynchronous DMA request for channel 14. + */ #define DMA_EARS_EDREQ_14(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_14_SHIFT)) & DMA_EARS_EDREQ_14_MASK) #define DMA_EARS_EDREQ_15_MASK (0x8000U) #define DMA_EARS_EDREQ_15_SHIFT (15U) +/*! EDREQ_15 - Enable asynchronous DMA request in stop mode for channel 15 + * 0b0..Disable asynchronous DMA request for channel 15. + * 0b1..Enable asynchronous DMA request for channel 15. + */ #define DMA_EARS_EDREQ_15(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_15_SHIFT)) & DMA_EARS_EDREQ_15_MASK) #define DMA_EARS_EDREQ_16_MASK (0x10000U) #define DMA_EARS_EDREQ_16_SHIFT (16U) +/*! EDREQ_16 - Enable asynchronous DMA request in stop mode for channel 16 + * 0b0..Disable asynchronous DMA request for channel 16 + * 0b1..Enable asynchronous DMA request for channel 16 + */ #define DMA_EARS_EDREQ_16(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_16_SHIFT)) & DMA_EARS_EDREQ_16_MASK) #define DMA_EARS_EDREQ_17_MASK (0x20000U) #define DMA_EARS_EDREQ_17_SHIFT (17U) +/*! EDREQ_17 - Enable asynchronous DMA request in stop mode for channel 17 + * 0b0..Disable asynchronous DMA request for channel 17 + * 0b1..Enable asynchronous DMA request for channel 17 + */ #define DMA_EARS_EDREQ_17(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_17_SHIFT)) & DMA_EARS_EDREQ_17_MASK) #define DMA_EARS_EDREQ_18_MASK (0x40000U) #define DMA_EARS_EDREQ_18_SHIFT (18U) +/*! EDREQ_18 - Enable asynchronous DMA request in stop mode for channel 18 + * 0b0..Disable asynchronous DMA request for channel 18 + * 0b1..Enable asynchronous DMA request for channel 18 + */ #define DMA_EARS_EDREQ_18(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_18_SHIFT)) & DMA_EARS_EDREQ_18_MASK) #define DMA_EARS_EDREQ_19_MASK (0x80000U) #define DMA_EARS_EDREQ_19_SHIFT (19U) +/*! EDREQ_19 - Enable asynchronous DMA request in stop mode for channel 19 + * 0b0..Disable asynchronous DMA request for channel 19 + * 0b1..Enable asynchronous DMA request for channel 19 + */ #define DMA_EARS_EDREQ_19(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_19_SHIFT)) & DMA_EARS_EDREQ_19_MASK) #define DMA_EARS_EDREQ_20_MASK (0x100000U) #define DMA_EARS_EDREQ_20_SHIFT (20U) +/*! EDREQ_20 - Enable asynchronous DMA request in stop mode for channel 20 + * 0b0..Disable asynchronous DMA request for channel 20 + * 0b1..Enable asynchronous DMA request for channel 20 + */ #define DMA_EARS_EDREQ_20(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_20_SHIFT)) & DMA_EARS_EDREQ_20_MASK) #define DMA_EARS_EDREQ_21_MASK (0x200000U) #define DMA_EARS_EDREQ_21_SHIFT (21U) +/*! EDREQ_21 - Enable asynchronous DMA request in stop mode for channel 21 + * 0b0..Disable asynchronous DMA request for channel 21 + * 0b1..Enable asynchronous DMA request for channel 21 + */ #define DMA_EARS_EDREQ_21(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_21_SHIFT)) & DMA_EARS_EDREQ_21_MASK) #define DMA_EARS_EDREQ_22_MASK (0x400000U) #define DMA_EARS_EDREQ_22_SHIFT (22U) +/*! EDREQ_22 - Enable asynchronous DMA request in stop mode for channel 22 + * 0b0..Disable asynchronous DMA request for channel 22 + * 0b1..Enable asynchronous DMA request for channel 22 + */ #define DMA_EARS_EDREQ_22(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_22_SHIFT)) & DMA_EARS_EDREQ_22_MASK) #define DMA_EARS_EDREQ_23_MASK (0x800000U) #define DMA_EARS_EDREQ_23_SHIFT (23U) +/*! EDREQ_23 - Enable asynchronous DMA request in stop mode for channel 23 + * 0b0..Disable asynchronous DMA request for channel 23 + * 0b1..Enable asynchronous DMA request for channel 23 + */ #define DMA_EARS_EDREQ_23(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_23_SHIFT)) & DMA_EARS_EDREQ_23_MASK) #define DMA_EARS_EDREQ_24_MASK (0x1000000U) #define DMA_EARS_EDREQ_24_SHIFT (24U) +/*! EDREQ_24 - Enable asynchronous DMA request in stop mode for channel 24 + * 0b0..Disable asynchronous DMA request for channel 24 + * 0b1..Enable asynchronous DMA request for channel 24 + */ #define DMA_EARS_EDREQ_24(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_24_SHIFT)) & DMA_EARS_EDREQ_24_MASK) #define DMA_EARS_EDREQ_25_MASK (0x2000000U) #define DMA_EARS_EDREQ_25_SHIFT (25U) +/*! EDREQ_25 - Enable asynchronous DMA request in stop mode for channel 25 + * 0b0..Disable asynchronous DMA request for channel 25 + * 0b1..Enable asynchronous DMA request for channel 25 + */ #define DMA_EARS_EDREQ_25(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_25_SHIFT)) & DMA_EARS_EDREQ_25_MASK) #define DMA_EARS_EDREQ_26_MASK (0x4000000U) #define DMA_EARS_EDREQ_26_SHIFT (26U) +/*! EDREQ_26 - Enable asynchronous DMA request in stop mode for channel 26 + * 0b0..Disable asynchronous DMA request for channel 26 + * 0b1..Enable asynchronous DMA request for channel 26 + */ #define DMA_EARS_EDREQ_26(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_26_SHIFT)) & DMA_EARS_EDREQ_26_MASK) #define DMA_EARS_EDREQ_27_MASK (0x8000000U) #define DMA_EARS_EDREQ_27_SHIFT (27U) +/*! EDREQ_27 - Enable asynchronous DMA request in stop mode for channel 27 + * 0b0..Disable asynchronous DMA request for channel 27 + * 0b1..Enable asynchronous DMA request for channel 27 + */ #define DMA_EARS_EDREQ_27(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_27_SHIFT)) & DMA_EARS_EDREQ_27_MASK) #define DMA_EARS_EDREQ_28_MASK (0x10000000U) #define DMA_EARS_EDREQ_28_SHIFT (28U) +/*! EDREQ_28 - Enable asynchronous DMA request in stop mode for channel 28 + * 0b0..Disable asynchronous DMA request for channel 28 + * 0b1..Enable asynchronous DMA request for channel 28 + */ #define DMA_EARS_EDREQ_28(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_28_SHIFT)) & DMA_EARS_EDREQ_28_MASK) #define DMA_EARS_EDREQ_29_MASK (0x20000000U) #define DMA_EARS_EDREQ_29_SHIFT (29U) +/*! EDREQ_29 - Enable asynchronous DMA request in stop mode for channel 29 + * 0b0..Disable asynchronous DMA request for channel 29 + * 0b1..Enable asynchronous DMA request for channel 29 + */ #define DMA_EARS_EDREQ_29(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_29_SHIFT)) & DMA_EARS_EDREQ_29_MASK) #define DMA_EARS_EDREQ_30_MASK (0x40000000U) #define DMA_EARS_EDREQ_30_SHIFT (30U) +/*! EDREQ_30 - Enable asynchronous DMA request in stop mode for channel 30 + * 0b0..Disable asynchronous DMA request for channel 30 + * 0b1..Enable asynchronous DMA request for channel 30 + */ #define DMA_EARS_EDREQ_30(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_30_SHIFT)) & DMA_EARS_EDREQ_30_MASK) #define DMA_EARS_EDREQ_31_MASK (0x80000000U) #define DMA_EARS_EDREQ_31_SHIFT (31U) +/*! EDREQ_31 - Enable asynchronous DMA request in stop mode for channel 31 + * 0b0..Disable asynchronous DMA request for channel 31 + * 0b1..Enable asynchronous DMA request for channel 31 + */ #define DMA_EARS_EDREQ_31(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_31_SHIFT)) & DMA_EARS_EDREQ_31_MASK) +/*! @} */ /*! @name DCHPRI3 - Channel n Priority Register */ +/*! @{ */ #define DMA_DCHPRI3_CHPRI_MASK (0xFU) #define DMA_DCHPRI3_CHPRI_SHIFT (0U) #define DMA_DCHPRI3_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_CHPRI_SHIFT)) & DMA_DCHPRI3_CHPRI_MASK) @@ -7448,12 +11433,22 @@ typedef struct { #define DMA_DCHPRI3_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_GRPPRI_SHIFT)) & DMA_DCHPRI3_GRPPRI_MASK) #define DMA_DCHPRI3_DPA_MASK (0x40U) #define DMA_DCHPRI3_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability. This field resets to 0. + * 0b0..Channel n can suspend a lower priority channel. + * 0b1..Channel n cannot suspend any channel, regardless of channel priority. + */ #define DMA_DCHPRI3_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_DPA_SHIFT)) & DMA_DCHPRI3_DPA_MASK) #define DMA_DCHPRI3_ECP_MASK (0x80U) #define DMA_DCHPRI3_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption. This field resets to 0. + * 0b0..Channel n cannot be suspended by a higher priority channel's service request. + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. + */ #define DMA_DCHPRI3_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_ECP_SHIFT)) & DMA_DCHPRI3_ECP_MASK) +/*! @} */ /*! @name DCHPRI2 - Channel n Priority Register */ +/*! @{ */ #define DMA_DCHPRI2_CHPRI_MASK (0xFU) #define DMA_DCHPRI2_CHPRI_SHIFT (0U) #define DMA_DCHPRI2_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_CHPRI_SHIFT)) & DMA_DCHPRI2_CHPRI_MASK) @@ -7462,12 +11457,22 @@ typedef struct { #define DMA_DCHPRI2_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_GRPPRI_SHIFT)) & DMA_DCHPRI2_GRPPRI_MASK) #define DMA_DCHPRI2_DPA_MASK (0x40U) #define DMA_DCHPRI2_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability. This field resets to 0. + * 0b0..Channel n can suspend a lower priority channel. + * 0b1..Channel n cannot suspend any channel, regardless of channel priority. + */ #define DMA_DCHPRI2_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_DPA_SHIFT)) & DMA_DCHPRI2_DPA_MASK) #define DMA_DCHPRI2_ECP_MASK (0x80U) #define DMA_DCHPRI2_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption. This field resets to 0. + * 0b0..Channel n cannot be suspended by a higher priority channel's service request. + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. + */ #define DMA_DCHPRI2_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_ECP_SHIFT)) & DMA_DCHPRI2_ECP_MASK) +/*! @} */ /*! @name DCHPRI1 - Channel n Priority Register */ +/*! @{ */ #define DMA_DCHPRI1_CHPRI_MASK (0xFU) #define DMA_DCHPRI1_CHPRI_SHIFT (0U) #define DMA_DCHPRI1_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_CHPRI_SHIFT)) & DMA_DCHPRI1_CHPRI_MASK) @@ -7476,12 +11481,22 @@ typedef struct { #define DMA_DCHPRI1_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_GRPPRI_SHIFT)) & DMA_DCHPRI1_GRPPRI_MASK) #define DMA_DCHPRI1_DPA_MASK (0x40U) #define DMA_DCHPRI1_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability. This field resets to 0. + * 0b0..Channel n can suspend a lower priority channel. + * 0b1..Channel n cannot suspend any channel, regardless of channel priority. + */ #define DMA_DCHPRI1_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_DPA_SHIFT)) & DMA_DCHPRI1_DPA_MASK) #define DMA_DCHPRI1_ECP_MASK (0x80U) #define DMA_DCHPRI1_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption. This field resets to 0. + * 0b0..Channel n cannot be suspended by a higher priority channel's service request. + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. + */ #define DMA_DCHPRI1_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_ECP_SHIFT)) & DMA_DCHPRI1_ECP_MASK) +/*! @} */ /*! @name DCHPRI0 - Channel n Priority Register */ +/*! @{ */ #define DMA_DCHPRI0_CHPRI_MASK (0xFU) #define DMA_DCHPRI0_CHPRI_SHIFT (0U) #define DMA_DCHPRI0_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_CHPRI_SHIFT)) & DMA_DCHPRI0_CHPRI_MASK) @@ -7490,12 +11505,22 @@ typedef struct { #define DMA_DCHPRI0_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_GRPPRI_SHIFT)) & DMA_DCHPRI0_GRPPRI_MASK) #define DMA_DCHPRI0_DPA_MASK (0x40U) #define DMA_DCHPRI0_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability. This field resets to 0. + * 0b0..Channel n can suspend a lower priority channel. + * 0b1..Channel n cannot suspend any channel, regardless of channel priority. + */ #define DMA_DCHPRI0_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_DPA_SHIFT)) & DMA_DCHPRI0_DPA_MASK) #define DMA_DCHPRI0_ECP_MASK (0x80U) #define DMA_DCHPRI0_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption. This field resets to 0. + * 0b0..Channel n cannot be suspended by a higher priority channel's service request. + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. + */ #define DMA_DCHPRI0_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_ECP_SHIFT)) & DMA_DCHPRI0_ECP_MASK) +/*! @} */ /*! @name DCHPRI7 - Channel n Priority Register */ +/*! @{ */ #define DMA_DCHPRI7_CHPRI_MASK (0xFU) #define DMA_DCHPRI7_CHPRI_SHIFT (0U) #define DMA_DCHPRI7_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_CHPRI_SHIFT)) & DMA_DCHPRI7_CHPRI_MASK) @@ -7504,12 +11529,22 @@ typedef struct { #define DMA_DCHPRI7_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_GRPPRI_SHIFT)) & DMA_DCHPRI7_GRPPRI_MASK) #define DMA_DCHPRI7_DPA_MASK (0x40U) #define DMA_DCHPRI7_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability. This field resets to 0. + * 0b0..Channel n can suspend a lower priority channel. + * 0b1..Channel n cannot suspend any channel, regardless of channel priority. + */ #define DMA_DCHPRI7_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_DPA_SHIFT)) & DMA_DCHPRI7_DPA_MASK) #define DMA_DCHPRI7_ECP_MASK (0x80U) #define DMA_DCHPRI7_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption. This field resets to 0. + * 0b0..Channel n cannot be suspended by a higher priority channel's service request. + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. + */ #define DMA_DCHPRI7_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_ECP_SHIFT)) & DMA_DCHPRI7_ECP_MASK) +/*! @} */ /*! @name DCHPRI6 - Channel n Priority Register */ +/*! @{ */ #define DMA_DCHPRI6_CHPRI_MASK (0xFU) #define DMA_DCHPRI6_CHPRI_SHIFT (0U) #define DMA_DCHPRI6_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_CHPRI_SHIFT)) & DMA_DCHPRI6_CHPRI_MASK) @@ -7518,12 +11553,22 @@ typedef struct { #define DMA_DCHPRI6_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_GRPPRI_SHIFT)) & DMA_DCHPRI6_GRPPRI_MASK) #define DMA_DCHPRI6_DPA_MASK (0x40U) #define DMA_DCHPRI6_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability. This field resets to 0. + * 0b0..Channel n can suspend a lower priority channel. + * 0b1..Channel n cannot suspend any channel, regardless of channel priority. + */ #define DMA_DCHPRI6_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_DPA_SHIFT)) & DMA_DCHPRI6_DPA_MASK) #define DMA_DCHPRI6_ECP_MASK (0x80U) #define DMA_DCHPRI6_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption. This field resets to 0. + * 0b0..Channel n cannot be suspended by a higher priority channel's service request. + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. + */ #define DMA_DCHPRI6_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_ECP_SHIFT)) & DMA_DCHPRI6_ECP_MASK) +/*! @} */ /*! @name DCHPRI5 - Channel n Priority Register */ +/*! @{ */ #define DMA_DCHPRI5_CHPRI_MASK (0xFU) #define DMA_DCHPRI5_CHPRI_SHIFT (0U) #define DMA_DCHPRI5_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_CHPRI_SHIFT)) & DMA_DCHPRI5_CHPRI_MASK) @@ -7532,12 +11577,22 @@ typedef struct { #define DMA_DCHPRI5_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_GRPPRI_SHIFT)) & DMA_DCHPRI5_GRPPRI_MASK) #define DMA_DCHPRI5_DPA_MASK (0x40U) #define DMA_DCHPRI5_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability. This field resets to 0. + * 0b0..Channel n can suspend a lower priority channel. + * 0b1..Channel n cannot suspend any channel, regardless of channel priority. + */ #define DMA_DCHPRI5_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_DPA_SHIFT)) & DMA_DCHPRI5_DPA_MASK) #define DMA_DCHPRI5_ECP_MASK (0x80U) #define DMA_DCHPRI5_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption. This field resets to 0. + * 0b0..Channel n cannot be suspended by a higher priority channel's service request. + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. + */ #define DMA_DCHPRI5_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_ECP_SHIFT)) & DMA_DCHPRI5_ECP_MASK) +/*! @} */ /*! @name DCHPRI4 - Channel n Priority Register */ +/*! @{ */ #define DMA_DCHPRI4_CHPRI_MASK (0xFU) #define DMA_DCHPRI4_CHPRI_SHIFT (0U) #define DMA_DCHPRI4_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_CHPRI_SHIFT)) & DMA_DCHPRI4_CHPRI_MASK) @@ -7546,12 +11601,22 @@ typedef struct { #define DMA_DCHPRI4_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_GRPPRI_SHIFT)) & DMA_DCHPRI4_GRPPRI_MASK) #define DMA_DCHPRI4_DPA_MASK (0x40U) #define DMA_DCHPRI4_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability. This field resets to 0. + * 0b0..Channel n can suspend a lower priority channel. + * 0b1..Channel n cannot suspend any channel, regardless of channel priority. + */ #define DMA_DCHPRI4_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_DPA_SHIFT)) & DMA_DCHPRI4_DPA_MASK) #define DMA_DCHPRI4_ECP_MASK (0x80U) #define DMA_DCHPRI4_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption. This field resets to 0. + * 0b0..Channel n cannot be suspended by a higher priority channel's service request. + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. + */ #define DMA_DCHPRI4_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_ECP_SHIFT)) & DMA_DCHPRI4_ECP_MASK) +/*! @} */ /*! @name DCHPRI11 - Channel n Priority Register */ +/*! @{ */ #define DMA_DCHPRI11_CHPRI_MASK (0xFU) #define DMA_DCHPRI11_CHPRI_SHIFT (0U) #define DMA_DCHPRI11_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_CHPRI_SHIFT)) & DMA_DCHPRI11_CHPRI_MASK) @@ -7560,12 +11625,22 @@ typedef struct { #define DMA_DCHPRI11_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_GRPPRI_SHIFT)) & DMA_DCHPRI11_GRPPRI_MASK) #define DMA_DCHPRI11_DPA_MASK (0x40U) #define DMA_DCHPRI11_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability. This field resets to 0. + * 0b0..Channel n can suspend a lower priority channel. + * 0b1..Channel n cannot suspend any channel, regardless of channel priority. + */ #define DMA_DCHPRI11_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_DPA_SHIFT)) & DMA_DCHPRI11_DPA_MASK) #define DMA_DCHPRI11_ECP_MASK (0x80U) #define DMA_DCHPRI11_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption. This field resets to 0. + * 0b0..Channel n cannot be suspended by a higher priority channel's service request. + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. + */ #define DMA_DCHPRI11_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_ECP_SHIFT)) & DMA_DCHPRI11_ECP_MASK) +/*! @} */ /*! @name DCHPRI10 - Channel n Priority Register */ +/*! @{ */ #define DMA_DCHPRI10_CHPRI_MASK (0xFU) #define DMA_DCHPRI10_CHPRI_SHIFT (0U) #define DMA_DCHPRI10_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_CHPRI_SHIFT)) & DMA_DCHPRI10_CHPRI_MASK) @@ -7574,12 +11649,22 @@ typedef struct { #define DMA_DCHPRI10_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_GRPPRI_SHIFT)) & DMA_DCHPRI10_GRPPRI_MASK) #define DMA_DCHPRI10_DPA_MASK (0x40U) #define DMA_DCHPRI10_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability. This field resets to 0. + * 0b0..Channel n can suspend a lower priority channel. + * 0b1..Channel n cannot suspend any channel, regardless of channel priority. + */ #define DMA_DCHPRI10_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_DPA_SHIFT)) & DMA_DCHPRI10_DPA_MASK) #define DMA_DCHPRI10_ECP_MASK (0x80U) #define DMA_DCHPRI10_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption. This field resets to 0. + * 0b0..Channel n cannot be suspended by a higher priority channel's service request. + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. + */ #define DMA_DCHPRI10_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_ECP_SHIFT)) & DMA_DCHPRI10_ECP_MASK) +/*! @} */ /*! @name DCHPRI9 - Channel n Priority Register */ +/*! @{ */ #define DMA_DCHPRI9_CHPRI_MASK (0xFU) #define DMA_DCHPRI9_CHPRI_SHIFT (0U) #define DMA_DCHPRI9_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_CHPRI_SHIFT)) & DMA_DCHPRI9_CHPRI_MASK) @@ -7588,12 +11673,22 @@ typedef struct { #define DMA_DCHPRI9_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_GRPPRI_SHIFT)) & DMA_DCHPRI9_GRPPRI_MASK) #define DMA_DCHPRI9_DPA_MASK (0x40U) #define DMA_DCHPRI9_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability. This field resets to 0. + * 0b0..Channel n can suspend a lower priority channel. + * 0b1..Channel n cannot suspend any channel, regardless of channel priority. + */ #define DMA_DCHPRI9_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_DPA_SHIFT)) & DMA_DCHPRI9_DPA_MASK) #define DMA_DCHPRI9_ECP_MASK (0x80U) #define DMA_DCHPRI9_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption. This field resets to 0. + * 0b0..Channel n cannot be suspended by a higher priority channel's service request. + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. + */ #define DMA_DCHPRI9_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_ECP_SHIFT)) & DMA_DCHPRI9_ECP_MASK) +/*! @} */ /*! @name DCHPRI8 - Channel n Priority Register */ +/*! @{ */ #define DMA_DCHPRI8_CHPRI_MASK (0xFU) #define DMA_DCHPRI8_CHPRI_SHIFT (0U) #define DMA_DCHPRI8_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_CHPRI_SHIFT)) & DMA_DCHPRI8_CHPRI_MASK) @@ -7602,12 +11697,22 @@ typedef struct { #define DMA_DCHPRI8_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_GRPPRI_SHIFT)) & DMA_DCHPRI8_GRPPRI_MASK) #define DMA_DCHPRI8_DPA_MASK (0x40U) #define DMA_DCHPRI8_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability. This field resets to 0. + * 0b0..Channel n can suspend a lower priority channel. + * 0b1..Channel n cannot suspend any channel, regardless of channel priority. + */ #define DMA_DCHPRI8_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_DPA_SHIFT)) & DMA_DCHPRI8_DPA_MASK) #define DMA_DCHPRI8_ECP_MASK (0x80U) #define DMA_DCHPRI8_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption. This field resets to 0. + * 0b0..Channel n cannot be suspended by a higher priority channel's service request. + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. + */ #define DMA_DCHPRI8_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_ECP_SHIFT)) & DMA_DCHPRI8_ECP_MASK) +/*! @} */ /*! @name DCHPRI15 - Channel n Priority Register */ +/*! @{ */ #define DMA_DCHPRI15_CHPRI_MASK (0xFU) #define DMA_DCHPRI15_CHPRI_SHIFT (0U) #define DMA_DCHPRI15_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_CHPRI_SHIFT)) & DMA_DCHPRI15_CHPRI_MASK) @@ -7616,12 +11721,22 @@ typedef struct { #define DMA_DCHPRI15_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_GRPPRI_SHIFT)) & DMA_DCHPRI15_GRPPRI_MASK) #define DMA_DCHPRI15_DPA_MASK (0x40U) #define DMA_DCHPRI15_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability. This field resets to 0. + * 0b0..Channel n can suspend a lower priority channel. + * 0b1..Channel n cannot suspend any channel, regardless of channel priority. + */ #define DMA_DCHPRI15_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_DPA_SHIFT)) & DMA_DCHPRI15_DPA_MASK) #define DMA_DCHPRI15_ECP_MASK (0x80U) #define DMA_DCHPRI15_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption. This field resets to 0. + * 0b0..Channel n cannot be suspended by a higher priority channel's service request. + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. + */ #define DMA_DCHPRI15_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_ECP_SHIFT)) & DMA_DCHPRI15_ECP_MASK) +/*! @} */ /*! @name DCHPRI14 - Channel n Priority Register */ +/*! @{ */ #define DMA_DCHPRI14_CHPRI_MASK (0xFU) #define DMA_DCHPRI14_CHPRI_SHIFT (0U) #define DMA_DCHPRI14_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_CHPRI_SHIFT)) & DMA_DCHPRI14_CHPRI_MASK) @@ -7630,12 +11745,22 @@ typedef struct { #define DMA_DCHPRI14_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_GRPPRI_SHIFT)) & DMA_DCHPRI14_GRPPRI_MASK) #define DMA_DCHPRI14_DPA_MASK (0x40U) #define DMA_DCHPRI14_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability. This field resets to 0. + * 0b0..Channel n can suspend a lower priority channel. + * 0b1..Channel n cannot suspend any channel, regardless of channel priority. + */ #define DMA_DCHPRI14_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_DPA_SHIFT)) & DMA_DCHPRI14_DPA_MASK) #define DMA_DCHPRI14_ECP_MASK (0x80U) #define DMA_DCHPRI14_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption. This field resets to 0. + * 0b0..Channel n cannot be suspended by a higher priority channel's service request. + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. + */ #define DMA_DCHPRI14_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_ECP_SHIFT)) & DMA_DCHPRI14_ECP_MASK) +/*! @} */ /*! @name DCHPRI13 - Channel n Priority Register */ +/*! @{ */ #define DMA_DCHPRI13_CHPRI_MASK (0xFU) #define DMA_DCHPRI13_CHPRI_SHIFT (0U) #define DMA_DCHPRI13_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_CHPRI_SHIFT)) & DMA_DCHPRI13_CHPRI_MASK) @@ -7644,12 +11769,22 @@ typedef struct { #define DMA_DCHPRI13_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_GRPPRI_SHIFT)) & DMA_DCHPRI13_GRPPRI_MASK) #define DMA_DCHPRI13_DPA_MASK (0x40U) #define DMA_DCHPRI13_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability. This field resets to 0. + * 0b0..Channel n can suspend a lower priority channel. + * 0b1..Channel n cannot suspend any channel, regardless of channel priority. + */ #define DMA_DCHPRI13_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_DPA_SHIFT)) & DMA_DCHPRI13_DPA_MASK) #define DMA_DCHPRI13_ECP_MASK (0x80U) #define DMA_DCHPRI13_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption. This field resets to 0. + * 0b0..Channel n cannot be suspended by a higher priority channel's service request. + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. + */ #define DMA_DCHPRI13_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_ECP_SHIFT)) & DMA_DCHPRI13_ECP_MASK) +/*! @} */ /*! @name DCHPRI12 - Channel n Priority Register */ +/*! @{ */ #define DMA_DCHPRI12_CHPRI_MASK (0xFU) #define DMA_DCHPRI12_CHPRI_SHIFT (0U) #define DMA_DCHPRI12_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_CHPRI_SHIFT)) & DMA_DCHPRI12_CHPRI_MASK) @@ -7658,12 +11793,22 @@ typedef struct { #define DMA_DCHPRI12_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_GRPPRI_SHIFT)) & DMA_DCHPRI12_GRPPRI_MASK) #define DMA_DCHPRI12_DPA_MASK (0x40U) #define DMA_DCHPRI12_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability. This field resets to 0. + * 0b0..Channel n can suspend a lower priority channel. + * 0b1..Channel n cannot suspend any channel, regardless of channel priority. + */ #define DMA_DCHPRI12_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_DPA_SHIFT)) & DMA_DCHPRI12_DPA_MASK) #define DMA_DCHPRI12_ECP_MASK (0x80U) #define DMA_DCHPRI12_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption. This field resets to 0. + * 0b0..Channel n cannot be suspended by a higher priority channel's service request. + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. + */ #define DMA_DCHPRI12_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_ECP_SHIFT)) & DMA_DCHPRI12_ECP_MASK) +/*! @} */ /*! @name DCHPRI19 - Channel n Priority Register */ +/*! @{ */ #define DMA_DCHPRI19_CHPRI_MASK (0xFU) #define DMA_DCHPRI19_CHPRI_SHIFT (0U) #define DMA_DCHPRI19_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_CHPRI_SHIFT)) & DMA_DCHPRI19_CHPRI_MASK) @@ -7672,12 +11817,22 @@ typedef struct { #define DMA_DCHPRI19_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_GRPPRI_SHIFT)) & DMA_DCHPRI19_GRPPRI_MASK) #define DMA_DCHPRI19_DPA_MASK (0x40U) #define DMA_DCHPRI19_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability. This field resets to 0. + * 0b0..Channel n can suspend a lower priority channel. + * 0b1..Channel n cannot suspend any channel, regardless of channel priority. + */ #define DMA_DCHPRI19_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_DPA_SHIFT)) & DMA_DCHPRI19_DPA_MASK) #define DMA_DCHPRI19_ECP_MASK (0x80U) #define DMA_DCHPRI19_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption. This field resets to 0. + * 0b0..Channel n cannot be suspended by a higher priority channel's service request. + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. + */ #define DMA_DCHPRI19_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_ECP_SHIFT)) & DMA_DCHPRI19_ECP_MASK) +/*! @} */ /*! @name DCHPRI18 - Channel n Priority Register */ +/*! @{ */ #define DMA_DCHPRI18_CHPRI_MASK (0xFU) #define DMA_DCHPRI18_CHPRI_SHIFT (0U) #define DMA_DCHPRI18_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_CHPRI_SHIFT)) & DMA_DCHPRI18_CHPRI_MASK) @@ -7686,12 +11841,22 @@ typedef struct { #define DMA_DCHPRI18_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_GRPPRI_SHIFT)) & DMA_DCHPRI18_GRPPRI_MASK) #define DMA_DCHPRI18_DPA_MASK (0x40U) #define DMA_DCHPRI18_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability. This field resets to 0. + * 0b0..Channel n can suspend a lower priority channel. + * 0b1..Channel n cannot suspend any channel, regardless of channel priority. + */ #define DMA_DCHPRI18_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_DPA_SHIFT)) & DMA_DCHPRI18_DPA_MASK) #define DMA_DCHPRI18_ECP_MASK (0x80U) #define DMA_DCHPRI18_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption. This field resets to 0. + * 0b0..Channel n cannot be suspended by a higher priority channel's service request. + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. + */ #define DMA_DCHPRI18_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_ECP_SHIFT)) & DMA_DCHPRI18_ECP_MASK) +/*! @} */ /*! @name DCHPRI17 - Channel n Priority Register */ +/*! @{ */ #define DMA_DCHPRI17_CHPRI_MASK (0xFU) #define DMA_DCHPRI17_CHPRI_SHIFT (0U) #define DMA_DCHPRI17_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_CHPRI_SHIFT)) & DMA_DCHPRI17_CHPRI_MASK) @@ -7700,12 +11865,22 @@ typedef struct { #define DMA_DCHPRI17_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_GRPPRI_SHIFT)) & DMA_DCHPRI17_GRPPRI_MASK) #define DMA_DCHPRI17_DPA_MASK (0x40U) #define DMA_DCHPRI17_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability. This field resets to 0. + * 0b0..Channel n can suspend a lower priority channel. + * 0b1..Channel n cannot suspend any channel, regardless of channel priority. + */ #define DMA_DCHPRI17_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_DPA_SHIFT)) & DMA_DCHPRI17_DPA_MASK) #define DMA_DCHPRI17_ECP_MASK (0x80U) #define DMA_DCHPRI17_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption. This field resets to 0. + * 0b0..Channel n cannot be suspended by a higher priority channel's service request. + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. + */ #define DMA_DCHPRI17_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_ECP_SHIFT)) & DMA_DCHPRI17_ECP_MASK) +/*! @} */ /*! @name DCHPRI16 - Channel n Priority Register */ +/*! @{ */ #define DMA_DCHPRI16_CHPRI_MASK (0xFU) #define DMA_DCHPRI16_CHPRI_SHIFT (0U) #define DMA_DCHPRI16_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_CHPRI_SHIFT)) & DMA_DCHPRI16_CHPRI_MASK) @@ -7714,12 +11889,22 @@ typedef struct { #define DMA_DCHPRI16_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_GRPPRI_SHIFT)) & DMA_DCHPRI16_GRPPRI_MASK) #define DMA_DCHPRI16_DPA_MASK (0x40U) #define DMA_DCHPRI16_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability. This field resets to 0. + * 0b0..Channel n can suspend a lower priority channel. + * 0b1..Channel n cannot suspend any channel, regardless of channel priority. + */ #define DMA_DCHPRI16_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_DPA_SHIFT)) & DMA_DCHPRI16_DPA_MASK) #define DMA_DCHPRI16_ECP_MASK (0x80U) #define DMA_DCHPRI16_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption. This field resets to 0. + * 0b0..Channel n cannot be suspended by a higher priority channel's service request. + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. + */ #define DMA_DCHPRI16_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_ECP_SHIFT)) & DMA_DCHPRI16_ECP_MASK) +/*! @} */ /*! @name DCHPRI23 - Channel n Priority Register */ +/*! @{ */ #define DMA_DCHPRI23_CHPRI_MASK (0xFU) #define DMA_DCHPRI23_CHPRI_SHIFT (0U) #define DMA_DCHPRI23_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_CHPRI_SHIFT)) & DMA_DCHPRI23_CHPRI_MASK) @@ -7728,12 +11913,22 @@ typedef struct { #define DMA_DCHPRI23_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_GRPPRI_SHIFT)) & DMA_DCHPRI23_GRPPRI_MASK) #define DMA_DCHPRI23_DPA_MASK (0x40U) #define DMA_DCHPRI23_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability. This field resets to 0. + * 0b0..Channel n can suspend a lower priority channel. + * 0b1..Channel n cannot suspend any channel, regardless of channel priority. + */ #define DMA_DCHPRI23_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_DPA_SHIFT)) & DMA_DCHPRI23_DPA_MASK) #define DMA_DCHPRI23_ECP_MASK (0x80U) #define DMA_DCHPRI23_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption. This field resets to 0. + * 0b0..Channel n cannot be suspended by a higher priority channel's service request. + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. + */ #define DMA_DCHPRI23_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_ECP_SHIFT)) & DMA_DCHPRI23_ECP_MASK) +/*! @} */ /*! @name DCHPRI22 - Channel n Priority Register */ +/*! @{ */ #define DMA_DCHPRI22_CHPRI_MASK (0xFU) #define DMA_DCHPRI22_CHPRI_SHIFT (0U) #define DMA_DCHPRI22_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_CHPRI_SHIFT)) & DMA_DCHPRI22_CHPRI_MASK) @@ -7742,12 +11937,22 @@ typedef struct { #define DMA_DCHPRI22_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_GRPPRI_SHIFT)) & DMA_DCHPRI22_GRPPRI_MASK) #define DMA_DCHPRI22_DPA_MASK (0x40U) #define DMA_DCHPRI22_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability. This field resets to 0. + * 0b0..Channel n can suspend a lower priority channel. + * 0b1..Channel n cannot suspend any channel, regardless of channel priority. + */ #define DMA_DCHPRI22_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_DPA_SHIFT)) & DMA_DCHPRI22_DPA_MASK) #define DMA_DCHPRI22_ECP_MASK (0x80U) #define DMA_DCHPRI22_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption. This field resets to 0. + * 0b0..Channel n cannot be suspended by a higher priority channel's service request. + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. + */ #define DMA_DCHPRI22_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_ECP_SHIFT)) & DMA_DCHPRI22_ECP_MASK) +/*! @} */ /*! @name DCHPRI21 - Channel n Priority Register */ +/*! @{ */ #define DMA_DCHPRI21_CHPRI_MASK (0xFU) #define DMA_DCHPRI21_CHPRI_SHIFT (0U) #define DMA_DCHPRI21_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_CHPRI_SHIFT)) & DMA_DCHPRI21_CHPRI_MASK) @@ -7756,12 +11961,22 @@ typedef struct { #define DMA_DCHPRI21_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_GRPPRI_SHIFT)) & DMA_DCHPRI21_GRPPRI_MASK) #define DMA_DCHPRI21_DPA_MASK (0x40U) #define DMA_DCHPRI21_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability. This field resets to 0. + * 0b0..Channel n can suspend a lower priority channel. + * 0b1..Channel n cannot suspend any channel, regardless of channel priority. + */ #define DMA_DCHPRI21_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_DPA_SHIFT)) & DMA_DCHPRI21_DPA_MASK) #define DMA_DCHPRI21_ECP_MASK (0x80U) #define DMA_DCHPRI21_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption. This field resets to 0. + * 0b0..Channel n cannot be suspended by a higher priority channel's service request. + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. + */ #define DMA_DCHPRI21_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_ECP_SHIFT)) & DMA_DCHPRI21_ECP_MASK) +/*! @} */ /*! @name DCHPRI20 - Channel n Priority Register */ +/*! @{ */ #define DMA_DCHPRI20_CHPRI_MASK (0xFU) #define DMA_DCHPRI20_CHPRI_SHIFT (0U) #define DMA_DCHPRI20_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_CHPRI_SHIFT)) & DMA_DCHPRI20_CHPRI_MASK) @@ -7770,12 +11985,22 @@ typedef struct { #define DMA_DCHPRI20_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_GRPPRI_SHIFT)) & DMA_DCHPRI20_GRPPRI_MASK) #define DMA_DCHPRI20_DPA_MASK (0x40U) #define DMA_DCHPRI20_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability. This field resets to 0. + * 0b0..Channel n can suspend a lower priority channel. + * 0b1..Channel n cannot suspend any channel, regardless of channel priority. + */ #define DMA_DCHPRI20_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_DPA_SHIFT)) & DMA_DCHPRI20_DPA_MASK) #define DMA_DCHPRI20_ECP_MASK (0x80U) #define DMA_DCHPRI20_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption. This field resets to 0. + * 0b0..Channel n cannot be suspended by a higher priority channel's service request. + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. + */ #define DMA_DCHPRI20_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_ECP_SHIFT)) & DMA_DCHPRI20_ECP_MASK) +/*! @} */ /*! @name DCHPRI27 - Channel n Priority Register */ +/*! @{ */ #define DMA_DCHPRI27_CHPRI_MASK (0xFU) #define DMA_DCHPRI27_CHPRI_SHIFT (0U) #define DMA_DCHPRI27_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_CHPRI_SHIFT)) & DMA_DCHPRI27_CHPRI_MASK) @@ -7784,12 +12009,22 @@ typedef struct { #define DMA_DCHPRI27_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_GRPPRI_SHIFT)) & DMA_DCHPRI27_GRPPRI_MASK) #define DMA_DCHPRI27_DPA_MASK (0x40U) #define DMA_DCHPRI27_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability. This field resets to 0. + * 0b0..Channel n can suspend a lower priority channel. + * 0b1..Channel n cannot suspend any channel, regardless of channel priority. + */ #define DMA_DCHPRI27_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_DPA_SHIFT)) & DMA_DCHPRI27_DPA_MASK) #define DMA_DCHPRI27_ECP_MASK (0x80U) #define DMA_DCHPRI27_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption. This field resets to 0. + * 0b0..Channel n cannot be suspended by a higher priority channel's service request. + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. + */ #define DMA_DCHPRI27_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_ECP_SHIFT)) & DMA_DCHPRI27_ECP_MASK) +/*! @} */ /*! @name DCHPRI26 - Channel n Priority Register */ +/*! @{ */ #define DMA_DCHPRI26_CHPRI_MASK (0xFU) #define DMA_DCHPRI26_CHPRI_SHIFT (0U) #define DMA_DCHPRI26_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_CHPRI_SHIFT)) & DMA_DCHPRI26_CHPRI_MASK) @@ -7798,12 +12033,22 @@ typedef struct { #define DMA_DCHPRI26_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_GRPPRI_SHIFT)) & DMA_DCHPRI26_GRPPRI_MASK) #define DMA_DCHPRI26_DPA_MASK (0x40U) #define DMA_DCHPRI26_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability. This field resets to 0. + * 0b0..Channel n can suspend a lower priority channel. + * 0b1..Channel n cannot suspend any channel, regardless of channel priority. + */ #define DMA_DCHPRI26_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_DPA_SHIFT)) & DMA_DCHPRI26_DPA_MASK) #define DMA_DCHPRI26_ECP_MASK (0x80U) #define DMA_DCHPRI26_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption. This field resets to 0. + * 0b0..Channel n cannot be suspended by a higher priority channel's service request. + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. + */ #define DMA_DCHPRI26_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_ECP_SHIFT)) & DMA_DCHPRI26_ECP_MASK) +/*! @} */ /*! @name DCHPRI25 - Channel n Priority Register */ +/*! @{ */ #define DMA_DCHPRI25_CHPRI_MASK (0xFU) #define DMA_DCHPRI25_CHPRI_SHIFT (0U) #define DMA_DCHPRI25_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_CHPRI_SHIFT)) & DMA_DCHPRI25_CHPRI_MASK) @@ -7812,12 +12057,22 @@ typedef struct { #define DMA_DCHPRI25_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_GRPPRI_SHIFT)) & DMA_DCHPRI25_GRPPRI_MASK) #define DMA_DCHPRI25_DPA_MASK (0x40U) #define DMA_DCHPRI25_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability. This field resets to 0. + * 0b0..Channel n can suspend a lower priority channel. + * 0b1..Channel n cannot suspend any channel, regardless of channel priority. + */ #define DMA_DCHPRI25_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_DPA_SHIFT)) & DMA_DCHPRI25_DPA_MASK) #define DMA_DCHPRI25_ECP_MASK (0x80U) #define DMA_DCHPRI25_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption. This field resets to 0. + * 0b0..Channel n cannot be suspended by a higher priority channel's service request. + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. + */ #define DMA_DCHPRI25_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_ECP_SHIFT)) & DMA_DCHPRI25_ECP_MASK) +/*! @} */ /*! @name DCHPRI24 - Channel n Priority Register */ +/*! @{ */ #define DMA_DCHPRI24_CHPRI_MASK (0xFU) #define DMA_DCHPRI24_CHPRI_SHIFT (0U) #define DMA_DCHPRI24_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_CHPRI_SHIFT)) & DMA_DCHPRI24_CHPRI_MASK) @@ -7826,12 +12081,22 @@ typedef struct { #define DMA_DCHPRI24_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_GRPPRI_SHIFT)) & DMA_DCHPRI24_GRPPRI_MASK) #define DMA_DCHPRI24_DPA_MASK (0x40U) #define DMA_DCHPRI24_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability. This field resets to 0. + * 0b0..Channel n can suspend a lower priority channel. + * 0b1..Channel n cannot suspend any channel, regardless of channel priority. + */ #define DMA_DCHPRI24_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_DPA_SHIFT)) & DMA_DCHPRI24_DPA_MASK) #define DMA_DCHPRI24_ECP_MASK (0x80U) #define DMA_DCHPRI24_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption. This field resets to 0. + * 0b0..Channel n cannot be suspended by a higher priority channel's service request. + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. + */ #define DMA_DCHPRI24_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_ECP_SHIFT)) & DMA_DCHPRI24_ECP_MASK) +/*! @} */ /*! @name DCHPRI31 - Channel n Priority Register */ +/*! @{ */ #define DMA_DCHPRI31_CHPRI_MASK (0xFU) #define DMA_DCHPRI31_CHPRI_SHIFT (0U) #define DMA_DCHPRI31_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_CHPRI_SHIFT)) & DMA_DCHPRI31_CHPRI_MASK) @@ -7840,12 +12105,22 @@ typedef struct { #define DMA_DCHPRI31_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_GRPPRI_SHIFT)) & DMA_DCHPRI31_GRPPRI_MASK) #define DMA_DCHPRI31_DPA_MASK (0x40U) #define DMA_DCHPRI31_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability. This field resets to 0. + * 0b0..Channel n can suspend a lower priority channel. + * 0b1..Channel n cannot suspend any channel, regardless of channel priority. + */ #define DMA_DCHPRI31_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_DPA_SHIFT)) & DMA_DCHPRI31_DPA_MASK) #define DMA_DCHPRI31_ECP_MASK (0x80U) #define DMA_DCHPRI31_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption. This field resets to 0. + * 0b0..Channel n cannot be suspended by a higher priority channel's service request. + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. + */ #define DMA_DCHPRI31_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_ECP_SHIFT)) & DMA_DCHPRI31_ECP_MASK) +/*! @} */ /*! @name DCHPRI30 - Channel n Priority Register */ +/*! @{ */ #define DMA_DCHPRI30_CHPRI_MASK (0xFU) #define DMA_DCHPRI30_CHPRI_SHIFT (0U) #define DMA_DCHPRI30_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_CHPRI_SHIFT)) & DMA_DCHPRI30_CHPRI_MASK) @@ -7854,12 +12129,22 @@ typedef struct { #define DMA_DCHPRI30_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_GRPPRI_SHIFT)) & DMA_DCHPRI30_GRPPRI_MASK) #define DMA_DCHPRI30_DPA_MASK (0x40U) #define DMA_DCHPRI30_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability. This field resets to 0. + * 0b0..Channel n can suspend a lower priority channel. + * 0b1..Channel n cannot suspend any channel, regardless of channel priority. + */ #define DMA_DCHPRI30_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_DPA_SHIFT)) & DMA_DCHPRI30_DPA_MASK) #define DMA_DCHPRI30_ECP_MASK (0x80U) #define DMA_DCHPRI30_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption. This field resets to 0. + * 0b0..Channel n cannot be suspended by a higher priority channel's service request. + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. + */ #define DMA_DCHPRI30_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_ECP_SHIFT)) & DMA_DCHPRI30_ECP_MASK) +/*! @} */ /*! @name DCHPRI29 - Channel n Priority Register */ +/*! @{ */ #define DMA_DCHPRI29_CHPRI_MASK (0xFU) #define DMA_DCHPRI29_CHPRI_SHIFT (0U) #define DMA_DCHPRI29_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_CHPRI_SHIFT)) & DMA_DCHPRI29_CHPRI_MASK) @@ -7868,12 +12153,22 @@ typedef struct { #define DMA_DCHPRI29_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_GRPPRI_SHIFT)) & DMA_DCHPRI29_GRPPRI_MASK) #define DMA_DCHPRI29_DPA_MASK (0x40U) #define DMA_DCHPRI29_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability. This field resets to 0. + * 0b0..Channel n can suspend a lower priority channel. + * 0b1..Channel n cannot suspend any channel, regardless of channel priority. + */ #define DMA_DCHPRI29_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_DPA_SHIFT)) & DMA_DCHPRI29_DPA_MASK) #define DMA_DCHPRI29_ECP_MASK (0x80U) #define DMA_DCHPRI29_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption. This field resets to 0. + * 0b0..Channel n cannot be suspended by a higher priority channel's service request. + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. + */ #define DMA_DCHPRI29_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_ECP_SHIFT)) & DMA_DCHPRI29_ECP_MASK) +/*! @} */ /*! @name DCHPRI28 - Channel n Priority Register */ +/*! @{ */ #define DMA_DCHPRI28_CHPRI_MASK (0xFU) #define DMA_DCHPRI28_CHPRI_SHIFT (0U) #define DMA_DCHPRI28_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_CHPRI_SHIFT)) & DMA_DCHPRI28_CHPRI_MASK) @@ -7882,28 +12177,42 @@ typedef struct { #define DMA_DCHPRI28_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_GRPPRI_SHIFT)) & DMA_DCHPRI28_GRPPRI_MASK) #define DMA_DCHPRI28_DPA_MASK (0x40U) #define DMA_DCHPRI28_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability. This field resets to 0. + * 0b0..Channel n can suspend a lower priority channel. + * 0b1..Channel n cannot suspend any channel, regardless of channel priority. + */ #define DMA_DCHPRI28_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_DPA_SHIFT)) & DMA_DCHPRI28_DPA_MASK) #define DMA_DCHPRI28_ECP_MASK (0x80U) #define DMA_DCHPRI28_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption. This field resets to 0. + * 0b0..Channel n cannot be suspended by a higher priority channel's service request. + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. + */ #define DMA_DCHPRI28_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_ECP_SHIFT)) & DMA_DCHPRI28_ECP_MASK) +/*! @} */ /*! @name SADDR - TCD Source Address */ +/*! @{ */ #define DMA_SADDR_SADDR_MASK (0xFFFFFFFFU) #define DMA_SADDR_SADDR_SHIFT (0U) #define DMA_SADDR_SADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_SADDR_SADDR_SHIFT)) & DMA_SADDR_SADDR_MASK) +/*! @} */ /* The count of DMA_SADDR */ #define DMA_SADDR_COUNT (32U) /*! @name SOFF - TCD Signed Source Address Offset */ +/*! @{ */ #define DMA_SOFF_SOFF_MASK (0xFFFFU) #define DMA_SOFF_SOFF_SHIFT (0U) #define DMA_SOFF_SOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_SOFF_SOFF_SHIFT)) & DMA_SOFF_SOFF_MASK) +/*! @} */ /* The count of DMA_SOFF */ #define DMA_SOFF_COUNT (32U) /*! @name ATTR - TCD Transfer Attributes */ +/*! @{ */ #define DMA_ATTR_DSIZE_MASK (0x7U) #define DMA_ATTR_DSIZE_SHIFT (0U) #define DMA_ATTR_DSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_DSIZE_SHIFT)) & DMA_ATTR_DSIZE_MASK) @@ -7912,37 +12221,65 @@ typedef struct { #define DMA_ATTR_DMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_DMOD_SHIFT)) & DMA_ATTR_DMOD_MASK) #define DMA_ATTR_SSIZE_MASK (0x700U) #define DMA_ATTR_SSIZE_SHIFT (8U) +/*! SSIZE - Source data transfer size + * 0b000..8-bit + * 0b001..16-bit + * 0b010..32-bit + * 0b011..64-bit + * 0b100..Reserved + * 0b101..32-byte burst (4 beats of 64 bits) + * 0b110..Reserved + * 0b111..Reserved + */ #define DMA_ATTR_SSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_SSIZE_SHIFT)) & DMA_ATTR_SSIZE_MASK) #define DMA_ATTR_SMOD_MASK (0xF800U) #define DMA_ATTR_SMOD_SHIFT (11U) +/*! SMOD - Source Address Modulo + * 0b00000..Source address modulo feature is disabled + * 0b00001-0b11111..This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + */ #define DMA_ATTR_SMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_SMOD_SHIFT)) & DMA_ATTR_SMOD_MASK) +/*! @} */ /* The count of DMA_ATTR */ #define DMA_ATTR_COUNT (32U) /*! @name NBYTES_MLNO - TCD Minor Byte Count (Minor Loop Mapping Disabled) */ +/*! @{ */ #define DMA_NBYTES_MLNO_NBYTES_MASK (0xFFFFFFFFU) #define DMA_NBYTES_MLNO_NBYTES_SHIFT (0U) #define DMA_NBYTES_MLNO_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLNO_NBYTES_SHIFT)) & DMA_NBYTES_MLNO_NBYTES_MASK) +/*! @} */ /* The count of DMA_NBYTES_MLNO */ #define DMA_NBYTES_MLNO_COUNT (32U) /*! @name NBYTES_MLOFFNO - TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) */ +/*! @{ */ #define DMA_NBYTES_MLOFFNO_NBYTES_MASK (0x3FFFFFFFU) #define DMA_NBYTES_MLOFFNO_NBYTES_SHIFT (0U) #define DMA_NBYTES_MLOFFNO_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_NBYTES_SHIFT)) & DMA_NBYTES_MLOFFNO_NBYTES_MASK) #define DMA_NBYTES_MLOFFNO_DMLOE_MASK (0x40000000U) #define DMA_NBYTES_MLOFFNO_DMLOE_SHIFT (30U) +/*! DMLOE - Destination Minor Loop Offset enable + * 0b0..The minor loop offset is not applied to the DADDR + * 0b1..The minor loop offset is applied to the DADDR + */ #define DMA_NBYTES_MLOFFNO_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_DMLOE_SHIFT)) & DMA_NBYTES_MLOFFNO_DMLOE_MASK) #define DMA_NBYTES_MLOFFNO_SMLOE_MASK (0x80000000U) #define DMA_NBYTES_MLOFFNO_SMLOE_SHIFT (31U) +/*! SMLOE - Source Minor Loop Offset Enable + * 0b0..The minor loop offset is not applied to the SADDR + * 0b1..The minor loop offset is applied to the SADDR + */ #define DMA_NBYTES_MLOFFNO_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_SMLOE_SHIFT)) & DMA_NBYTES_MLOFFNO_SMLOE_MASK) +/*! @} */ /* The count of DMA_NBYTES_MLOFFNO */ #define DMA_NBYTES_MLOFFNO_COUNT (32U) /*! @name NBYTES_MLOFFYES - TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) */ +/*! @{ */ #define DMA_NBYTES_MLOFFYES_NBYTES_MASK (0x3FFU) #define DMA_NBYTES_MLOFFYES_NBYTES_SHIFT (0U) #define DMA_NBYTES_MLOFFYES_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_NBYTES_SHIFT)) & DMA_NBYTES_MLOFFYES_NBYTES_MASK) @@ -7951,50 +12288,72 @@ typedef struct { #define DMA_NBYTES_MLOFFYES_MLOFF(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_MLOFF_SHIFT)) & DMA_NBYTES_MLOFFYES_MLOFF_MASK) #define DMA_NBYTES_MLOFFYES_DMLOE_MASK (0x40000000U) #define DMA_NBYTES_MLOFFYES_DMLOE_SHIFT (30U) +/*! DMLOE - Destination Minor Loop Offset enable + * 0b0..The minor loop offset is not applied to the DADDR + * 0b1..The minor loop offset is applied to the DADDR + */ #define DMA_NBYTES_MLOFFYES_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_DMLOE_SHIFT)) & DMA_NBYTES_MLOFFYES_DMLOE_MASK) #define DMA_NBYTES_MLOFFYES_SMLOE_MASK (0x80000000U) #define DMA_NBYTES_MLOFFYES_SMLOE_SHIFT (31U) +/*! SMLOE - Source Minor Loop Offset Enable + * 0b0..The minor loop offset is not applied to the SADDR + * 0b1..The minor loop offset is applied to the SADDR + */ #define DMA_NBYTES_MLOFFYES_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_SMLOE_SHIFT)) & DMA_NBYTES_MLOFFYES_SMLOE_MASK) +/*! @} */ /* The count of DMA_NBYTES_MLOFFYES */ #define DMA_NBYTES_MLOFFYES_COUNT (32U) /*! @name SLAST - TCD Last Source Address Adjustment */ +/*! @{ */ #define DMA_SLAST_SLAST_MASK (0xFFFFFFFFU) #define DMA_SLAST_SLAST_SHIFT (0U) #define DMA_SLAST_SLAST(x) (((uint32_t)(((uint32_t)(x)) << DMA_SLAST_SLAST_SHIFT)) & DMA_SLAST_SLAST_MASK) +/*! @} */ /* The count of DMA_SLAST */ #define DMA_SLAST_COUNT (32U) /*! @name DADDR - TCD Destination Address */ +/*! @{ */ #define DMA_DADDR_DADDR_MASK (0xFFFFFFFFU) #define DMA_DADDR_DADDR_SHIFT (0U) #define DMA_DADDR_DADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_DADDR_DADDR_SHIFT)) & DMA_DADDR_DADDR_MASK) +/*! @} */ /* The count of DMA_DADDR */ #define DMA_DADDR_COUNT (32U) /*! @name DOFF - TCD Signed Destination Address Offset */ +/*! @{ */ #define DMA_DOFF_DOFF_MASK (0xFFFFU) #define DMA_DOFF_DOFF_SHIFT (0U) #define DMA_DOFF_DOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_DOFF_DOFF_SHIFT)) & DMA_DOFF_DOFF_MASK) +/*! @} */ /* The count of DMA_DOFF */ #define DMA_DOFF_COUNT (32U) /*! @name CITER_ELINKNO - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) */ +/*! @{ */ #define DMA_CITER_ELINKNO_CITER_MASK (0x7FFFU) #define DMA_CITER_ELINKNO_CITER_SHIFT (0U) #define DMA_CITER_ELINKNO_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKNO_CITER_SHIFT)) & DMA_CITER_ELINKNO_CITER_MASK) #define DMA_CITER_ELINKNO_ELINK_MASK (0x8000U) #define DMA_CITER_ELINKNO_ELINK_SHIFT (15U) +/*! ELINK - Enable channel-to-channel linking on minor-loop complete + * 0b0..The channel-to-channel linking is disabled + * 0b1..The channel-to-channel linking is enabled + */ #define DMA_CITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKNO_ELINK_SHIFT)) & DMA_CITER_ELINKNO_ELINK_MASK) +/*! @} */ /* The count of DMA_CITER_ELINKNO */ #define DMA_CITER_ELINKNO_COUNT (32U) /*! @name CITER_ELINKYES - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) */ +/*! @{ */ #define DMA_CITER_ELINKYES_CITER_MASK (0x1FFU) #define DMA_CITER_ELINKYES_CITER_SHIFT (0U) #define DMA_CITER_ELINKYES_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_CITER_SHIFT)) & DMA_CITER_ELINKYES_CITER_MASK) @@ -8003,37 +12362,69 @@ typedef struct { #define DMA_CITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_LINKCH_SHIFT)) & DMA_CITER_ELINKYES_LINKCH_MASK) #define DMA_CITER_ELINKYES_ELINK_MASK (0x8000U) #define DMA_CITER_ELINKYES_ELINK_SHIFT (15U) +/*! ELINK - Enable channel-to-channel linking on minor-loop complete + * 0b0..The channel-to-channel linking is disabled + * 0b1..The channel-to-channel linking is enabled + */ #define DMA_CITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_ELINK_SHIFT)) & DMA_CITER_ELINKYES_ELINK_MASK) +/*! @} */ /* The count of DMA_CITER_ELINKYES */ #define DMA_CITER_ELINKYES_COUNT (32U) /*! @name DLAST_SGA - TCD Last Destination Address Adjustment/Scatter Gather Address */ +/*! @{ */ #define DMA_DLAST_SGA_DLASTSGA_MASK (0xFFFFFFFFU) #define DMA_DLAST_SGA_DLASTSGA_SHIFT (0U) #define DMA_DLAST_SGA_DLASTSGA(x) (((uint32_t)(((uint32_t)(x)) << DMA_DLAST_SGA_DLASTSGA_SHIFT)) & DMA_DLAST_SGA_DLASTSGA_MASK) +/*! @} */ /* The count of DMA_DLAST_SGA */ #define DMA_DLAST_SGA_COUNT (32U) /*! @name CSR - TCD Control and Status */ +/*! @{ */ #define DMA_CSR_START_MASK (0x1U) #define DMA_CSR_START_SHIFT (0U) +/*! START - Channel Start + * 0b0..The channel is not explicitly started. + * 0b1..The channel is explicitly started via a software initiated service request. + */ #define DMA_CSR_START(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_START_SHIFT)) & DMA_CSR_START_MASK) #define DMA_CSR_INTMAJOR_MASK (0x2U) #define DMA_CSR_INTMAJOR_SHIFT (1U) +/*! INTMAJOR - Enable an interrupt when major iteration count completes. + * 0b0..The end-of-major loop interrupt is disabled. + * 0b1..The end-of-major loop interrupt is enabled. + */ #define DMA_CSR_INTMAJOR(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_INTMAJOR_SHIFT)) & DMA_CSR_INTMAJOR_MASK) #define DMA_CSR_INTHALF_MASK (0x4U) #define DMA_CSR_INTHALF_SHIFT (2U) +/*! INTHALF - Enable an interrupt when major counter is half complete. + * 0b0..The half-point interrupt is disabled. + * 0b1..The half-point interrupt is enabled. + */ #define DMA_CSR_INTHALF(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_INTHALF_SHIFT)) & DMA_CSR_INTHALF_MASK) #define DMA_CSR_DREQ_MASK (0x8U) #define DMA_CSR_DREQ_SHIFT (3U) +/*! DREQ - Disable Request + * 0b0..The channel's ERQ bit is not affected. + * 0b1..The channel's ERQ bit is cleared when the major loop is complete. + */ #define DMA_CSR_DREQ(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_DREQ_SHIFT)) & DMA_CSR_DREQ_MASK) #define DMA_CSR_ESG_MASK (0x10U) #define DMA_CSR_ESG_SHIFT (4U) +/*! ESG - Enable Scatter/Gather Processing + * 0b0..The current channel's TCD is normal format. + * 0b1..The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. + */ #define DMA_CSR_ESG(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_ESG_SHIFT)) & DMA_CSR_ESG_MASK) #define DMA_CSR_MAJORELINK_MASK (0x20U) #define DMA_CSR_MAJORELINK_SHIFT (5U) +/*! MAJORELINK - Enable channel-to-channel linking on major loop complete + * 0b0..The channel-to-channel linking is disabled. + * 0b1..The channel-to-channel linking is enabled. + */ #define DMA_CSR_MAJORELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_MAJORELINK_SHIFT)) & DMA_CSR_MAJORELINK_MASK) #define DMA_CSR_ACTIVE_MASK (0x40U) #define DMA_CSR_ACTIVE_SHIFT (6U) @@ -8046,23 +12437,37 @@ typedef struct { #define DMA_CSR_MAJORLINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_MAJORLINKCH_SHIFT)) & DMA_CSR_MAJORLINKCH_MASK) #define DMA_CSR_BWC_MASK (0xC000U) #define DMA_CSR_BWC_SHIFT (14U) +/*! BWC - Bandwidth Control + * 0b00..No eDMA engine stalls. + * 0b01..Reserved + * 0b10..eDMA engine stalls for 4 cycles after each R/W. + * 0b11..eDMA engine stalls for 8 cycles after each R/W. + */ #define DMA_CSR_BWC(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_BWC_SHIFT)) & DMA_CSR_BWC_MASK) +/*! @} */ /* The count of DMA_CSR */ #define DMA_CSR_COUNT (32U) /*! @name BITER_ELINKNO - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) */ +/*! @{ */ #define DMA_BITER_ELINKNO_BITER_MASK (0x7FFFU) #define DMA_BITER_ELINKNO_BITER_SHIFT (0U) #define DMA_BITER_ELINKNO_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKNO_BITER_SHIFT)) & DMA_BITER_ELINKNO_BITER_MASK) #define DMA_BITER_ELINKNO_ELINK_MASK (0x8000U) #define DMA_BITER_ELINKNO_ELINK_SHIFT (15U) +/*! ELINK - Enables channel-to-channel linking on minor loop complete + * 0b0..The channel-to-channel linking is disabled + * 0b1..The channel-to-channel linking is enabled + */ #define DMA_BITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKNO_ELINK_SHIFT)) & DMA_BITER_ELINKNO_ELINK_MASK) +/*! @} */ /* The count of DMA_BITER_ELINKNO */ #define DMA_BITER_ELINKNO_COUNT (32U) /*! @name BITER_ELINKYES - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) */ +/*! @{ */ #define DMA_BITER_ELINKYES_BITER_MASK (0x1FFU) #define DMA_BITER_ELINKYES_BITER_SHIFT (0U) #define DMA_BITER_ELINKYES_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_BITER_SHIFT)) & DMA_BITER_ELINKYES_BITER_MASK) @@ -8071,7 +12476,12 @@ typedef struct { #define DMA_BITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_LINKCH_SHIFT)) & DMA_BITER_ELINKYES_LINKCH_MASK) #define DMA_BITER_ELINKYES_ELINK_MASK (0x8000U) #define DMA_BITER_ELINKYES_ELINK_SHIFT (15U) +/*! ELINK - Enables channel-to-channel linking on minor loop complete + * 0b0..The channel-to-channel linking is disabled + * 0b1..The channel-to-channel linking is enabled + */ #define DMA_BITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_ELINK_SHIFT)) & DMA_BITER_ELINKYES_ELINK_MASK) +/*! @} */ /* The count of DMA_BITER_ELINKYES */ #define DMA_BITER_ELINKYES_COUNT (32U) @@ -8111,11 +12521,7 @@ typedef struct { /** DMAMUX - Register Layout Typedef */ typedef struct { - __IO uint32_t CHCFG[32]; /**< - Channel 0 Configuration Register - .. - Channel 31 Configuration Register - , array offset: 0x0, array step: 0x4 */ + __IO uint32_t CHCFG[32]; /**< Channel 0 Configuration Register..Channel 31 Configuration Register, array offset: 0x0, array step: 0x4 */ } DMAMUX_Type; /* ---------------------------------------------------------------------------- @@ -8127,23 +12533,33 @@ typedef struct { * @{ */ -/*! @name CHCFG - - Channel 0 Configuration Register - .. - Channel 31 Configuration Register - */ +/*! @name CHCFG - Channel 0 Configuration Register..Channel 31 Configuration Register */ +/*! @{ */ #define DMAMUX_CHCFG_SOURCE_MASK (0x7FU) #define DMAMUX_CHCFG_SOURCE_SHIFT (0U) #define DMAMUX_CHCFG_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << DMAMUX_CHCFG_SOURCE_SHIFT)) & DMAMUX_CHCFG_SOURCE_MASK) #define DMAMUX_CHCFG_A_ON_MASK (0x20000000U) #define DMAMUX_CHCFG_A_ON_SHIFT (29U) +/*! A_ON - DMA Channel Always Enable + * 0b0..DMA Channel Always ON function is disabled + * 0b1..DMA Channel Always ON function is enabled + */ #define DMAMUX_CHCFG_A_ON(x) (((uint32_t)(((uint32_t)(x)) << DMAMUX_CHCFG_A_ON_SHIFT)) & DMAMUX_CHCFG_A_ON_MASK) #define DMAMUX_CHCFG_TRIG_MASK (0x40000000U) #define DMAMUX_CHCFG_TRIG_SHIFT (30U) +/*! TRIG - DMA Channel Trigger Enable + * 0b0..Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode) + * 0b1..Triggering is enabled. If triggering is enabled and ENBL is set, the DMA_CH_MUX is in Periodic Trigger mode. + */ #define DMAMUX_CHCFG_TRIG(x) (((uint32_t)(((uint32_t)(x)) << DMAMUX_CHCFG_TRIG_SHIFT)) & DMAMUX_CHCFG_TRIG_MASK) #define DMAMUX_CHCFG_ENBL_MASK (0x80000000U) #define DMAMUX_CHCFG_ENBL_SHIFT (31U) +/*! ENBL - DMA Mux Channel Enable + * 0b0..DMA Mux channel is disabled + * 0b1..DMA Mux channel is enabled + */ #define DMAMUX_CHCFG_ENBL(x) (((uint32_t)(((uint32_t)(x)) << DMAMUX_CHCFG_ENBL_SHIFT)) & DMAMUX_CHCFG_ENBL_MASK) +/*! @} */ /* The count of DMAMUX_CHCFG */ #define DMAMUX_CHCFG_COUNT (32U) @@ -8212,119 +12628,210 @@ typedef struct { */ /*! @name CTRL - Control Register */ +/*! @{ */ #define ENC_CTRL_CMPIE_MASK (0x1U) #define ENC_CTRL_CMPIE_SHIFT (0U) +/*! CMPIE - Compare Interrupt Enable + * 0b0..Compare interrupt is disabled + * 0b1..Compare interrupt is enabled + */ #define ENC_CTRL_CMPIE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_CMPIE_SHIFT)) & ENC_CTRL_CMPIE_MASK) #define ENC_CTRL_CMPIRQ_MASK (0x2U) #define ENC_CTRL_CMPIRQ_SHIFT (1U) +/*! CMPIRQ - Compare Interrupt Request + * 0b0..No match has occurred + * 0b1..COMP match has occurred + */ #define ENC_CTRL_CMPIRQ(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_CMPIRQ_SHIFT)) & ENC_CTRL_CMPIRQ_MASK) #define ENC_CTRL_WDE_MASK (0x4U) #define ENC_CTRL_WDE_SHIFT (2U) +/*! WDE - Watchdog Enable + * 0b0..Watchdog timer is disabled + * 0b1..Watchdog timer is enabled + */ #define ENC_CTRL_WDE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_WDE_SHIFT)) & ENC_CTRL_WDE_MASK) #define ENC_CTRL_DIE_MASK (0x8U) #define ENC_CTRL_DIE_SHIFT (3U) +/*! DIE - Watchdog Timeout Interrupt Enable + * 0b0..Watchdog timer interrupt is disabled + * 0b1..Watchdog timer interrupt is enabled + */ #define ENC_CTRL_DIE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_DIE_SHIFT)) & ENC_CTRL_DIE_MASK) #define ENC_CTRL_DIRQ_MASK (0x10U) #define ENC_CTRL_DIRQ_SHIFT (4U) +/*! DIRQ - Watchdog Timeout Interrupt Request + * 0b0..No interrupt has occurred + * 0b1..Watchdog timeout interrupt has occurred + */ #define ENC_CTRL_DIRQ(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_DIRQ_SHIFT)) & ENC_CTRL_DIRQ_MASK) #define ENC_CTRL_XNE_MASK (0x20U) #define ENC_CTRL_XNE_SHIFT (5U) +/*! XNE - Use Negative Edge of INDEX Pulse + * 0b0..Use positive transition edge of INDEX pulse + * 0b1..Use negative transition edge of INDEX pulse + */ #define ENC_CTRL_XNE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_XNE_SHIFT)) & ENC_CTRL_XNE_MASK) #define ENC_CTRL_XIP_MASK (0x40U) #define ENC_CTRL_XIP_SHIFT (6U) +/*! XIP - INDEX Triggered Initialization of Position Counters UPOS and LPOS + * 0b0..No action + * 0b1..INDEX pulse initializes the position counter + */ #define ENC_CTRL_XIP(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_XIP_SHIFT)) & ENC_CTRL_XIP_MASK) #define ENC_CTRL_XIE_MASK (0x80U) #define ENC_CTRL_XIE_SHIFT (7U) +/*! XIE - INDEX Pulse Interrupt Enable + * 0b0..INDEX pulse interrupt is disabled + * 0b1..INDEX pulse interrupt is enabled + */ #define ENC_CTRL_XIE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_XIE_SHIFT)) & ENC_CTRL_XIE_MASK) #define ENC_CTRL_XIRQ_MASK (0x100U) #define ENC_CTRL_XIRQ_SHIFT (8U) +/*! XIRQ - INDEX Pulse Interrupt Request + * 0b0..No interrupt has occurred + * 0b1..INDEX pulse interrupt has occurred + */ #define ENC_CTRL_XIRQ(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_XIRQ_SHIFT)) & ENC_CTRL_XIRQ_MASK) #define ENC_CTRL_PH1_MASK (0x200U) #define ENC_CTRL_PH1_SHIFT (9U) +/*! PH1 - Enable Signal Phase Count Mode + * 0b0..Use standard quadrature decoder where PHASEA and PHASEB represent a two phase quadrature signal. + * 0b1..Bypass the quadrature decoder. A positive transition of the PHASEA input generates a count signal. The PHASEB input and the REV bit control the counter direction. If CTRL[REV] = 0, PHASEB = 0, then count up If CTRL[REV] = 0, PHASEB = 1, then count down If CTRL[REV] = 1, PHASEB = 0, then count down If CTRL[REV] = 1, PHASEB = 1, then count up + */ #define ENC_CTRL_PH1(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_PH1_SHIFT)) & ENC_CTRL_PH1_MASK) #define ENC_CTRL_REV_MASK (0x400U) #define ENC_CTRL_REV_SHIFT (10U) +/*! REV - Enable Reverse Direction Counting + * 0b0..Count normally + * 0b1..Count in the reverse direction + */ #define ENC_CTRL_REV(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_REV_SHIFT)) & ENC_CTRL_REV_MASK) #define ENC_CTRL_SWIP_MASK (0x800U) #define ENC_CTRL_SWIP_SHIFT (11U) +/*! SWIP - Software Triggered Initialization of Position Counters UPOS and LPOS + * 0b0..No action + * 0b1..Initialize position counter + */ #define ENC_CTRL_SWIP(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_SWIP_SHIFT)) & ENC_CTRL_SWIP_MASK) #define ENC_CTRL_HNE_MASK (0x1000U) #define ENC_CTRL_HNE_SHIFT (12U) +/*! HNE - Use Negative Edge of HOME Input + * 0b0..Use positive going edge-to-trigger initialization of position counters UPOS and LPOS + * 0b1..Use negative going edge-to-trigger initialization of position counters UPOS and LPOS + */ #define ENC_CTRL_HNE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_HNE_SHIFT)) & ENC_CTRL_HNE_MASK) #define ENC_CTRL_HIP_MASK (0x2000U) #define ENC_CTRL_HIP_SHIFT (13U) +/*! HIP - Enable HOME to Initialize Position Counters UPOS and LPOS + * 0b0..No action + * 0b1..HOME signal initializes the position counter + */ #define ENC_CTRL_HIP(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_HIP_SHIFT)) & ENC_CTRL_HIP_MASK) #define ENC_CTRL_HIE_MASK (0x4000U) #define ENC_CTRL_HIE_SHIFT (14U) +/*! HIE - HOME Interrupt Enable + * 0b0..Disable HOME interrupts + * 0b1..Enable HOME interrupts + */ #define ENC_CTRL_HIE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_HIE_SHIFT)) & ENC_CTRL_HIE_MASK) #define ENC_CTRL_HIRQ_MASK (0x8000U) #define ENC_CTRL_HIRQ_SHIFT (15U) +/*! HIRQ - HOME Signal Transition Interrupt Request + * 0b0..No interrupt + * 0b1..HOME signal transition interrupt request + */ #define ENC_CTRL_HIRQ(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_HIRQ_SHIFT)) & ENC_CTRL_HIRQ_MASK) +/*! @} */ /*! @name FILT - Input Filter Register */ +/*! @{ */ #define ENC_FILT_FILT_PER_MASK (0xFFU) #define ENC_FILT_FILT_PER_SHIFT (0U) #define ENC_FILT_FILT_PER(x) (((uint16_t)(((uint16_t)(x)) << ENC_FILT_FILT_PER_SHIFT)) & ENC_FILT_FILT_PER_MASK) #define ENC_FILT_FILT_CNT_MASK (0x700U) #define ENC_FILT_FILT_CNT_SHIFT (8U) #define ENC_FILT_FILT_CNT(x) (((uint16_t)(((uint16_t)(x)) << ENC_FILT_FILT_CNT_SHIFT)) & ENC_FILT_FILT_CNT_MASK) +/*! @} */ /*! @name WTR - Watchdog Timeout Register */ +/*! @{ */ #define ENC_WTR_WDOG_MASK (0xFFFFU) #define ENC_WTR_WDOG_SHIFT (0U) #define ENC_WTR_WDOG(x) (((uint16_t)(((uint16_t)(x)) << ENC_WTR_WDOG_SHIFT)) & ENC_WTR_WDOG_MASK) +/*! @} */ /*! @name POSD - Position Difference Counter Register */ +/*! @{ */ #define ENC_POSD_POSD_MASK (0xFFFFU) #define ENC_POSD_POSD_SHIFT (0U) #define ENC_POSD_POSD(x) (((uint16_t)(((uint16_t)(x)) << ENC_POSD_POSD_SHIFT)) & ENC_POSD_POSD_MASK) +/*! @} */ /*! @name POSDH - Position Difference Hold Register */ +/*! @{ */ #define ENC_POSDH_POSDH_MASK (0xFFFFU) #define ENC_POSDH_POSDH_SHIFT (0U) #define ENC_POSDH_POSDH(x) (((uint16_t)(((uint16_t)(x)) << ENC_POSDH_POSDH_SHIFT)) & ENC_POSDH_POSDH_MASK) +/*! @} */ /*! @name REV - Revolution Counter Register */ +/*! @{ */ #define ENC_REV_REV_MASK (0xFFFFU) #define ENC_REV_REV_SHIFT (0U) #define ENC_REV_REV(x) (((uint16_t)(((uint16_t)(x)) << ENC_REV_REV_SHIFT)) & ENC_REV_REV_MASK) +/*! @} */ /*! @name REVH - Revolution Hold Register */ +/*! @{ */ #define ENC_REVH_REVH_MASK (0xFFFFU) #define ENC_REVH_REVH_SHIFT (0U) #define ENC_REVH_REVH(x) (((uint16_t)(((uint16_t)(x)) << ENC_REVH_REVH_SHIFT)) & ENC_REVH_REVH_MASK) +/*! @} */ /*! @name UPOS - Upper Position Counter Register */ +/*! @{ */ #define ENC_UPOS_POS_MASK (0xFFFFU) #define ENC_UPOS_POS_SHIFT (0U) #define ENC_UPOS_POS(x) (((uint16_t)(((uint16_t)(x)) << ENC_UPOS_POS_SHIFT)) & ENC_UPOS_POS_MASK) +/*! @} */ /*! @name LPOS - Lower Position Counter Register */ +/*! @{ */ #define ENC_LPOS_POS_MASK (0xFFFFU) #define ENC_LPOS_POS_SHIFT (0U) #define ENC_LPOS_POS(x) (((uint16_t)(((uint16_t)(x)) << ENC_LPOS_POS_SHIFT)) & ENC_LPOS_POS_MASK) +/*! @} */ /*! @name UPOSH - Upper Position Hold Register */ +/*! @{ */ #define ENC_UPOSH_POSH_MASK (0xFFFFU) #define ENC_UPOSH_POSH_SHIFT (0U) #define ENC_UPOSH_POSH(x) (((uint16_t)(((uint16_t)(x)) << ENC_UPOSH_POSH_SHIFT)) & ENC_UPOSH_POSH_MASK) +/*! @} */ /*! @name LPOSH - Lower Position Hold Register */ +/*! @{ */ #define ENC_LPOSH_POSH_MASK (0xFFFFU) #define ENC_LPOSH_POSH_SHIFT (0U) #define ENC_LPOSH_POSH(x) (((uint16_t)(((uint16_t)(x)) << ENC_LPOSH_POSH_SHIFT)) & ENC_LPOSH_POSH_MASK) +/*! @} */ /*! @name UINIT - Upper Initialization Register */ +/*! @{ */ #define ENC_UINIT_INIT_MASK (0xFFFFU) #define ENC_UINIT_INIT_SHIFT (0U) #define ENC_UINIT_INIT(x) (((uint16_t)(((uint16_t)(x)) << ENC_UINIT_INIT_SHIFT)) & ENC_UINIT_INIT_MASK) +/*! @} */ /*! @name LINIT - Lower Initialization Register */ +/*! @{ */ #define ENC_LINIT_INIT_MASK (0xFFFFU) #define ENC_LINIT_INIT_SHIFT (0U) #define ENC_LINIT_INIT(x) (((uint16_t)(((uint16_t)(x)) << ENC_LINIT_INIT_SHIFT)) & ENC_LINIT_INIT_MASK) +/*! @} */ /*! @name IMR - Input Monitor Register */ +/*! @{ */ #define ENC_IMR_HOME_MASK (0x1U) #define ENC_IMR_HOME_SHIFT (0U) #define ENC_IMR_HOME(x) (((uint16_t)(((uint16_t)(x)) << ENC_IMR_HOME_SHIFT)) & ENC_IMR_HOME_MASK) @@ -8349,8 +12856,10 @@ typedef struct { #define ENC_IMR_FPHA_MASK (0x80U) #define ENC_IMR_FPHA_SHIFT (7U) #define ENC_IMR_FPHA(x) (((uint16_t)(((uint16_t)(x)) << ENC_IMR_FPHA_SHIFT)) & ENC_IMR_FPHA_MASK) +/*! @} */ /*! @name TST - Test Register */ +/*! @{ */ #define ENC_TST_TEST_COUNT_MASK (0xFFU) #define ENC_TST_TEST_COUNT_SHIFT (0U) #define ENC_TST_TEST_COUNT(x) (((uint16_t)(((uint16_t)(x)) << ENC_TST_TEST_COUNT_SHIFT)) & ENC_TST_TEST_COUNT_MASK) @@ -8359,71 +12868,142 @@ typedef struct { #define ENC_TST_TEST_PERIOD(x) (((uint16_t)(((uint16_t)(x)) << ENC_TST_TEST_PERIOD_SHIFT)) & ENC_TST_TEST_PERIOD_MASK) #define ENC_TST_QDN_MASK (0x2000U) #define ENC_TST_QDN_SHIFT (13U) +/*! QDN - Quadrature Decoder Negative Signal + * 0b0..Leaves quadrature decoder signal in a positive direction + * 0b1..Generates a negative quadrature decoder signal + */ #define ENC_TST_QDN(x) (((uint16_t)(((uint16_t)(x)) << ENC_TST_QDN_SHIFT)) & ENC_TST_QDN_MASK) #define ENC_TST_TCE_MASK (0x4000U) #define ENC_TST_TCE_SHIFT (14U) +/*! TCE - Test Counter Enable + * 0b0..Test count is not enabled + * 0b1..Test count is enabled + */ #define ENC_TST_TCE(x) (((uint16_t)(((uint16_t)(x)) << ENC_TST_TCE_SHIFT)) & ENC_TST_TCE_MASK) #define ENC_TST_TEN_MASK (0x8000U) #define ENC_TST_TEN_SHIFT (15U) +/*! TEN - Test Mode Enable + * 0b0..Test module is not enabled + * 0b1..Test module is enabled + */ #define ENC_TST_TEN(x) (((uint16_t)(((uint16_t)(x)) << ENC_TST_TEN_SHIFT)) & ENC_TST_TEN_MASK) +/*! @} */ /*! @name CTRL2 - Control 2 Register */ +/*! @{ */ #define ENC_CTRL2_UPDHLD_MASK (0x1U) #define ENC_CTRL2_UPDHLD_SHIFT (0U) +/*! UPDHLD - Update Hold Registers + * 0b0..Disable updates of hold registers on rising edge of TRIGGER + * 0b1..Enable updates of hold registers on rising edge of TRIGGER + */ #define ENC_CTRL2_UPDHLD(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_UPDHLD_SHIFT)) & ENC_CTRL2_UPDHLD_MASK) #define ENC_CTRL2_UPDPOS_MASK (0x2U) #define ENC_CTRL2_UPDPOS_SHIFT (1U) +/*! UPDPOS - Update Position Registers + * 0b0..No action for POSD, REV, UPOS and LPOS on rising edge of TRIGGER + * 0b1..Clear POSD, REV, UPOS and LPOS on rising edge of TRIGGER + */ #define ENC_CTRL2_UPDPOS(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_UPDPOS_SHIFT)) & ENC_CTRL2_UPDPOS_MASK) #define ENC_CTRL2_MOD_MASK (0x4U) #define ENC_CTRL2_MOD_SHIFT (2U) +/*! MOD - Enable Modulo Counting + * 0b0..Disable modulo counting + * 0b1..Enable modulo counting + */ #define ENC_CTRL2_MOD(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_MOD_SHIFT)) & ENC_CTRL2_MOD_MASK) #define ENC_CTRL2_DIR_MASK (0x8U) #define ENC_CTRL2_DIR_SHIFT (3U) +/*! DIR - Count Direction Flag + * 0b0..Last count was in the down direction + * 0b1..Last count was in the up direction + */ #define ENC_CTRL2_DIR(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_DIR_SHIFT)) & ENC_CTRL2_DIR_MASK) #define ENC_CTRL2_RUIE_MASK (0x10U) #define ENC_CTRL2_RUIE_SHIFT (4U) +/*! RUIE - Roll-under Interrupt Enable + * 0b0..Roll-under interrupt is disabled + * 0b1..Roll-under interrupt is enabled + */ #define ENC_CTRL2_RUIE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_RUIE_SHIFT)) & ENC_CTRL2_RUIE_MASK) #define ENC_CTRL2_RUIRQ_MASK (0x20U) #define ENC_CTRL2_RUIRQ_SHIFT (5U) +/*! RUIRQ - Roll-under Interrupt Request + * 0b0..No roll-under has occurred + * 0b1..Roll-under has occurred + */ #define ENC_CTRL2_RUIRQ(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_RUIRQ_SHIFT)) & ENC_CTRL2_RUIRQ_MASK) #define ENC_CTRL2_ROIE_MASK (0x40U) #define ENC_CTRL2_ROIE_SHIFT (6U) +/*! ROIE - Roll-over Interrupt Enable + * 0b0..Roll-over interrupt is disabled + * 0b1..Roll-over interrupt is enabled + */ #define ENC_CTRL2_ROIE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_ROIE_SHIFT)) & ENC_CTRL2_ROIE_MASK) #define ENC_CTRL2_ROIRQ_MASK (0x80U) #define ENC_CTRL2_ROIRQ_SHIFT (7U) +/*! ROIRQ - Roll-over Interrupt Request + * 0b0..No roll-over has occurred + * 0b1..Roll-over has occurred + */ #define ENC_CTRL2_ROIRQ(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_ROIRQ_SHIFT)) & ENC_CTRL2_ROIRQ_MASK) #define ENC_CTRL2_REVMOD_MASK (0x100U) #define ENC_CTRL2_REVMOD_SHIFT (8U) +/*! REVMOD - Revolution Counter Modulus Enable + * 0b0..Use INDEX pulse to increment/decrement revolution counter (REV). + * 0b1..Use modulus counting roll-over/under to increment/decrement revolution counter (REV). + */ #define ENC_CTRL2_REVMOD(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_REVMOD_SHIFT)) & ENC_CTRL2_REVMOD_MASK) #define ENC_CTRL2_OUTCTL_MASK (0x200U) #define ENC_CTRL2_OUTCTL_SHIFT (9U) +/*! OUTCTL - Output Control + * 0b0..POSMATCH pulses when a match occurs between the position counters (POS) and the compare value (COMP). + * 0b1..POSMATCH pulses when the UPOS, LPOS, REV, or POSD registers are read. + */ #define ENC_CTRL2_OUTCTL(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_OUTCTL_SHIFT)) & ENC_CTRL2_OUTCTL_MASK) #define ENC_CTRL2_SABIE_MASK (0x400U) #define ENC_CTRL2_SABIE_SHIFT (10U) +/*! SABIE - Simultaneous PHASEA and PHASEB Change Interrupt Enable + * 0b0..Simultaneous PHASEA and PHASEB change interrupt disabled. + * 0b1..Simultaneous PHASEA and PHASEB change interrupt enabled. + */ #define ENC_CTRL2_SABIE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_SABIE_SHIFT)) & ENC_CTRL2_SABIE_MASK) #define ENC_CTRL2_SABIRQ_MASK (0x800U) #define ENC_CTRL2_SABIRQ_SHIFT (11U) +/*! SABIRQ - Simultaneous PHASEA and PHASEB Change Interrupt Request + * 0b0..No simultaneous change of PHASEA and PHASEB has occurred. + * 0b1..A simultaneous change of PHASEA and PHASEB has occurred. + */ #define ENC_CTRL2_SABIRQ(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_SABIRQ_SHIFT)) & ENC_CTRL2_SABIRQ_MASK) +/*! @} */ /*! @name UMOD - Upper Modulus Register */ +/*! @{ */ #define ENC_UMOD_MOD_MASK (0xFFFFU) #define ENC_UMOD_MOD_SHIFT (0U) #define ENC_UMOD_MOD(x) (((uint16_t)(((uint16_t)(x)) << ENC_UMOD_MOD_SHIFT)) & ENC_UMOD_MOD_MASK) +/*! @} */ /*! @name LMOD - Lower Modulus Register */ +/*! @{ */ #define ENC_LMOD_MOD_MASK (0xFFFFU) #define ENC_LMOD_MOD_SHIFT (0U) #define ENC_LMOD_MOD(x) (((uint16_t)(((uint16_t)(x)) << ENC_LMOD_MOD_SHIFT)) & ENC_LMOD_MOD_MASK) +/*! @} */ /*! @name UCOMP - Upper Position Compare Register */ +/*! @{ */ #define ENC_UCOMP_COMP_MASK (0xFFFFU) #define ENC_UCOMP_COMP_SHIFT (0U) #define ENC_UCOMP_COMP(x) (((uint16_t)(((uint16_t)(x)) << ENC_UCOMP_COMP_SHIFT)) & ENC_UCOMP_COMP_MASK) +/*! @} */ /*! @name LCOMP - Lower Position Compare Register */ +/*! @{ */ #define ENC_LCOMP_COMP_MASK (0xFFFFU) #define ENC_LCOMP_COMP_SHIFT (0U) #define ENC_LCOMP_COMP(x) (((uint16_t)(((uint16_t)(x)) << ENC_LCOMP_COMP_SHIFT)) & ENC_LCOMP_COMP_MASK) +/*! @} */ /*! @@ -8605,6 +13185,7 @@ typedef struct { */ /*! @name EIR - Interrupt Event Register */ +/*! @{ */ #define ENET_EIR_TS_TIMER_MASK (0x8000U) #define ENET_EIR_TS_TIMER_SHIFT (15U) #define ENET_EIR_TS_TIMER(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TS_TIMER_SHIFT)) & ENET_EIR_TS_TIMER_MASK) @@ -8653,8 +13234,10 @@ typedef struct { #define ENET_EIR_BABR_MASK (0x40000000U) #define ENET_EIR_BABR_SHIFT (30U) #define ENET_EIR_BABR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_BABR_SHIFT)) & ENET_EIR_BABR_MASK) +/*! @} */ /*! @name EIMR - Interrupt Mask Register */ +/*! @{ */ #define ENET_EIMR_TS_TIMER_MASK (0x8000U) #define ENET_EIMR_TS_TIMER_SHIFT (15U) #define ENET_EIMR_TS_TIMER(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TS_TIMER_SHIFT)) & ENET_EIMR_TS_TIMER_MASK) @@ -8690,54 +13273,106 @@ typedef struct { #define ENET_EIMR_RXF(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXF_SHIFT)) & ENET_EIMR_RXF_MASK) #define ENET_EIMR_TXB_MASK (0x4000000U) #define ENET_EIMR_TXB_SHIFT (26U) +/*! TXB - TXB Interrupt Mask + * 0b0..The corresponding interrupt source is masked. + * 0b1..The corresponding interrupt source is not masked. + */ #define ENET_EIMR_TXB(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXB_SHIFT)) & ENET_EIMR_TXB_MASK) #define ENET_EIMR_TXF_MASK (0x8000000U) #define ENET_EIMR_TXF_SHIFT (27U) +/*! TXF - TXF Interrupt Mask + * 0b0..The corresponding interrupt source is masked. + * 0b1..The corresponding interrupt source is not masked. + */ #define ENET_EIMR_TXF(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXF_SHIFT)) & ENET_EIMR_TXF_MASK) #define ENET_EIMR_GRA_MASK (0x10000000U) #define ENET_EIMR_GRA_SHIFT (28U) +/*! GRA - GRA Interrupt Mask + * 0b0..The corresponding interrupt source is masked. + * 0b1..The corresponding interrupt source is not masked. + */ #define ENET_EIMR_GRA(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_GRA_SHIFT)) & ENET_EIMR_GRA_MASK) #define ENET_EIMR_BABT_MASK (0x20000000U) #define ENET_EIMR_BABT_SHIFT (29U) +/*! BABT - BABT Interrupt Mask + * 0b0..The corresponding interrupt source is masked. + * 0b1..The corresponding interrupt source is not masked. + */ #define ENET_EIMR_BABT(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_BABT_SHIFT)) & ENET_EIMR_BABT_MASK) #define ENET_EIMR_BABR_MASK (0x40000000U) #define ENET_EIMR_BABR_SHIFT (30U) +/*! BABR - BABR Interrupt Mask + * 0b0..The corresponding interrupt source is masked. + * 0b1..The corresponding interrupt source is not masked. + */ #define ENET_EIMR_BABR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_BABR_SHIFT)) & ENET_EIMR_BABR_MASK) +/*! @} */ /*! @name RDAR - Receive Descriptor Active Register */ +/*! @{ */ #define ENET_RDAR_RDAR_MASK (0x1000000U) #define ENET_RDAR_RDAR_SHIFT (24U) #define ENET_RDAR_RDAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_RDAR_RDAR_SHIFT)) & ENET_RDAR_RDAR_MASK) +/*! @} */ /*! @name TDAR - Transmit Descriptor Active Register */ +/*! @{ */ #define ENET_TDAR_TDAR_MASK (0x1000000U) #define ENET_TDAR_TDAR_SHIFT (24U) #define ENET_TDAR_TDAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_TDAR_TDAR_SHIFT)) & ENET_TDAR_TDAR_MASK) +/*! @} */ /*! @name ECR - Ethernet Control Register */ +/*! @{ */ #define ENET_ECR_RESET_MASK (0x1U) #define ENET_ECR_RESET_SHIFT (0U) #define ENET_ECR_RESET(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_RESET_SHIFT)) & ENET_ECR_RESET_MASK) #define ENET_ECR_ETHEREN_MASK (0x2U) #define ENET_ECR_ETHEREN_SHIFT (1U) +/*! ETHEREN - Ethernet Enable + * 0b0..Reception immediately stops and transmission stops after a bad CRC is appended to any currently transmitted frame. + * 0b1..MAC is enabled, and reception and transmission are possible. + */ #define ENET_ECR_ETHEREN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_ETHEREN_SHIFT)) & ENET_ECR_ETHEREN_MASK) #define ENET_ECR_MAGICEN_MASK (0x4U) #define ENET_ECR_MAGICEN_SHIFT (2U) +/*! MAGICEN - Magic Packet Detection Enable + * 0b0..Magic detection logic disabled. + * 0b1..The MAC core detects magic packets and asserts EIR[WAKEUP] when a frame is detected. + */ #define ENET_ECR_MAGICEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_MAGICEN_SHIFT)) & ENET_ECR_MAGICEN_MASK) #define ENET_ECR_SLEEP_MASK (0x8U) #define ENET_ECR_SLEEP_SHIFT (3U) +/*! SLEEP - Sleep Mode Enable + * 0b0..Normal operating mode. + * 0b1..Sleep mode. + */ #define ENET_ECR_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_SLEEP_SHIFT)) & ENET_ECR_SLEEP_MASK) #define ENET_ECR_EN1588_MASK (0x10U) #define ENET_ECR_EN1588_SHIFT (4U) +/*! EN1588 - EN1588 Enable + * 0b0..Legacy FEC buffer descriptors and functions enabled. + * 0b1..Enhanced frame time-stamping functions enabled. + */ #define ENET_ECR_EN1588(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_EN1588_SHIFT)) & ENET_ECR_EN1588_MASK) #define ENET_ECR_DBGEN_MASK (0x40U) #define ENET_ECR_DBGEN_SHIFT (6U) +/*! DBGEN - Debug Enable + * 0b0..MAC continues operation in debug mode. + * 0b1..MAC enters hardware freeze mode when the processor is in debug mode. + */ #define ENET_ECR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_DBGEN_SHIFT)) & ENET_ECR_DBGEN_MASK) #define ENET_ECR_DBSWP_MASK (0x100U) #define ENET_ECR_DBSWP_SHIFT (8U) +/*! DBSWP - Descriptor Byte Swapping Enable + * 0b0..The buffer descriptor bytes are not swapped to support big-endian devices. + * 0b1..The buffer descriptor bytes are swapped to support little-endian devices. + */ #define ENET_ECR_DBSWP(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_DBSWP_SHIFT)) & ENET_ECR_DBSWP_MASK) +/*! @} */ /*! @name MMFR - MII Management Frame Register */ +/*! @{ */ #define ENET_MMFR_DATA_MASK (0xFFFFU) #define ENET_MMFR_DATA_SHIFT (0U) #define ENET_MMFR_DATA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_DATA_SHIFT)) & ENET_MMFR_DATA_MASK) @@ -8756,41 +13391,85 @@ typedef struct { #define ENET_MMFR_ST_MASK (0xC0000000U) #define ENET_MMFR_ST_SHIFT (30U) #define ENET_MMFR_ST(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_ST_SHIFT)) & ENET_MMFR_ST_MASK) +/*! @} */ /*! @name MSCR - MII Speed Control Register */ +/*! @{ */ #define ENET_MSCR_MII_SPEED_MASK (0x7EU) #define ENET_MSCR_MII_SPEED_SHIFT (1U) #define ENET_MSCR_MII_SPEED(x) (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_MII_SPEED_SHIFT)) & ENET_MSCR_MII_SPEED_MASK) #define ENET_MSCR_DIS_PRE_MASK (0x80U) #define ENET_MSCR_DIS_PRE_SHIFT (7U) +/*! DIS_PRE - Disable Preamble + * 0b0..Preamble enabled. + * 0b1..Preamble (32 ones) is not prepended to the MII management frame. + */ #define ENET_MSCR_DIS_PRE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_DIS_PRE_SHIFT)) & ENET_MSCR_DIS_PRE_MASK) #define ENET_MSCR_HOLDTIME_MASK (0x700U) #define ENET_MSCR_HOLDTIME_SHIFT (8U) +/*! HOLDTIME - Hold time On MDIO Output + * 0b000..1 internal module clock cycle + * 0b001..2 internal module clock cycles + * 0b010..3 internal module clock cycles + * 0b111..8 internal module clock cycles + */ #define ENET_MSCR_HOLDTIME(x) (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_HOLDTIME_SHIFT)) & ENET_MSCR_HOLDTIME_MASK) +/*! @} */ /*! @name MIBC - MIB Control Register */ +/*! @{ */ #define ENET_MIBC_MIB_CLEAR_MASK (0x20000000U) #define ENET_MIBC_MIB_CLEAR_SHIFT (29U) +/*! MIB_CLEAR - MIB Clear + * 0b0..See note above. + * 0b1..All statistics counters are reset to 0. + */ #define ENET_MIBC_MIB_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_CLEAR_SHIFT)) & ENET_MIBC_MIB_CLEAR_MASK) #define ENET_MIBC_MIB_IDLE_MASK (0x40000000U) #define ENET_MIBC_MIB_IDLE_SHIFT (30U) +/*! MIB_IDLE - MIB Idle + * 0b0..The MIB block is updating MIB counters. + * 0b1..The MIB block is not currently updating any MIB counters. + */ #define ENET_MIBC_MIB_IDLE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_IDLE_SHIFT)) & ENET_MIBC_MIB_IDLE_MASK) #define ENET_MIBC_MIB_DIS_MASK (0x80000000U) #define ENET_MIBC_MIB_DIS_SHIFT (31U) +/*! MIB_DIS - Disable MIB Logic + * 0b0..MIB logic is enabled. + * 0b1..MIB logic is disabled. The MIB logic halts and does not update any MIB counters. + */ #define ENET_MIBC_MIB_DIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_DIS_SHIFT)) & ENET_MIBC_MIB_DIS_MASK) +/*! @} */ /*! @name RCR - Receive Control Register */ +/*! @{ */ #define ENET_RCR_LOOP_MASK (0x1U) #define ENET_RCR_LOOP_SHIFT (0U) +/*! LOOP - Internal Loopback + * 0b0..Loopback disabled. + * 0b1..Transmitted frames are looped back internal to the device and transmit MII output signals are not asserted. DRT must be cleared. + */ #define ENET_RCR_LOOP(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_LOOP_SHIFT)) & ENET_RCR_LOOP_MASK) #define ENET_RCR_DRT_MASK (0x2U) #define ENET_RCR_DRT_SHIFT (1U) +/*! DRT - Disable Receive On Transmit + * 0b0..Receive path operates independently of transmit (i.e., full-duplex mode). Can also be used to monitor transmit activity in half-duplex mode. + * 0b1..Disable reception of frames while transmitting. (Normally used for half-duplex mode.) + */ #define ENET_RCR_DRT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_DRT_SHIFT)) & ENET_RCR_DRT_MASK) #define ENET_RCR_MII_MODE_MASK (0x4U) #define ENET_RCR_MII_MODE_SHIFT (2U) +/*! MII_MODE - Media Independent Interface Mode + * 0b0..Reserved. + * 0b1..MII or RMII mode, as indicated by the RMII_MODE field. + */ #define ENET_RCR_MII_MODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_MII_MODE_SHIFT)) & ENET_RCR_MII_MODE_MASK) #define ENET_RCR_PROM_MASK (0x8U) #define ENET_RCR_PROM_SHIFT (3U) +/*! PROM - Promiscuous Mode + * 0b0..Disabled. + * 0b1..Enabled. + */ #define ENET_RCR_PROM(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PROM_SHIFT)) & ENET_RCR_PROM_MASK) #define ENET_RCR_BC_REJ_MASK (0x10U) #define ENET_RCR_BC_REJ_SHIFT (4U) @@ -8800,33 +13479,63 @@ typedef struct { #define ENET_RCR_FCE(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_FCE_SHIFT)) & ENET_RCR_FCE_MASK) #define ENET_RCR_RMII_MODE_MASK (0x100U) #define ENET_RCR_RMII_MODE_SHIFT (8U) +/*! RMII_MODE - RMII Mode Enable + * 0b0..MAC configured for MII mode. + * 0b1..MAC configured for RMII operation. + */ #define ENET_RCR_RMII_MODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_RMII_MODE_SHIFT)) & ENET_RCR_RMII_MODE_MASK) #define ENET_RCR_RMII_10T_MASK (0x200U) #define ENET_RCR_RMII_10T_SHIFT (9U) +/*! RMII_10T + * 0b0..100-Mbit/s operation. + * 0b1..10-Mbit/s operation. + */ #define ENET_RCR_RMII_10T(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_RMII_10T_SHIFT)) & ENET_RCR_RMII_10T_MASK) #define ENET_RCR_PADEN_MASK (0x1000U) #define ENET_RCR_PADEN_SHIFT (12U) +/*! PADEN - Enable Frame Padding Remove On Receive + * 0b0..No padding is removed on receive by the MAC. + * 0b1..Padding is removed from received frames. + */ #define ENET_RCR_PADEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PADEN_SHIFT)) & ENET_RCR_PADEN_MASK) #define ENET_RCR_PAUFWD_MASK (0x2000U) #define ENET_RCR_PAUFWD_SHIFT (13U) +/*! PAUFWD - Terminate/Forward Pause Frames + * 0b0..Pause frames are terminated and discarded in the MAC. + * 0b1..Pause frames are forwarded to the user application. + */ #define ENET_RCR_PAUFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PAUFWD_SHIFT)) & ENET_RCR_PAUFWD_MASK) #define ENET_RCR_CRCFWD_MASK (0x4000U) #define ENET_RCR_CRCFWD_SHIFT (14U) +/*! CRCFWD - Terminate/Forward Received CRC + * 0b0..The CRC field of received frames is transmitted to the user application. + * 0b1..The CRC field is stripped from the frame. + */ #define ENET_RCR_CRCFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_CRCFWD_SHIFT)) & ENET_RCR_CRCFWD_MASK) #define ENET_RCR_CFEN_MASK (0x8000U) #define ENET_RCR_CFEN_SHIFT (15U) +/*! CFEN - MAC Control Frame Enable + * 0b0..MAC control frames with any opcode other than 0x0001 (pause frame) are accepted and forwarded to the client interface. + * 0b1..MAC control frames with any opcode other than 0x0001 (pause frame) are silently discarded. + */ #define ENET_RCR_CFEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_CFEN_SHIFT)) & ENET_RCR_CFEN_MASK) #define ENET_RCR_MAX_FL_MASK (0x3FFF0000U) #define ENET_RCR_MAX_FL_SHIFT (16U) #define ENET_RCR_MAX_FL(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_MAX_FL_SHIFT)) & ENET_RCR_MAX_FL_MASK) #define ENET_RCR_NLC_MASK (0x40000000U) #define ENET_RCR_NLC_SHIFT (30U) +/*! NLC - Payload Length Check Disable + * 0b0..The payload length check is disabled. + * 0b1..The core checks the frame's payload length with the frame length/type field. Errors are indicated in the EIR[PLR] field. + */ #define ENET_RCR_NLC(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_NLC_SHIFT)) & ENET_RCR_NLC_MASK) #define ENET_RCR_GRS_MASK (0x80000000U) #define ENET_RCR_GRS_SHIFT (31U) #define ENET_RCR_GRS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_GRS_SHIFT)) & ENET_RCR_GRS_MASK) +/*! @} */ /*! @name TCR - Transmit Control Register */ +/*! @{ */ #define ENET_TCR_GTS_MASK (0x1U) #define ENET_TCR_GTS_SHIFT (0U) #define ENET_TCR_GTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_GTS_SHIFT)) & ENET_TCR_GTS_MASK) @@ -8835,42 +13544,68 @@ typedef struct { #define ENET_TCR_FDEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_FDEN_SHIFT)) & ENET_TCR_FDEN_MASK) #define ENET_TCR_TFC_PAUSE_MASK (0x8U) #define ENET_TCR_TFC_PAUSE_SHIFT (3U) +/*! TFC_PAUSE - Transmit Frame Control Pause + * 0b0..No PAUSE frame transmitted. + * 0b1..The MAC stops transmission of data frames after the current transmission is complete. + */ #define ENET_TCR_TFC_PAUSE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_TFC_PAUSE_SHIFT)) & ENET_TCR_TFC_PAUSE_MASK) #define ENET_TCR_RFC_PAUSE_MASK (0x10U) #define ENET_TCR_RFC_PAUSE_SHIFT (4U) #define ENET_TCR_RFC_PAUSE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_RFC_PAUSE_SHIFT)) & ENET_TCR_RFC_PAUSE_MASK) #define ENET_TCR_ADDSEL_MASK (0xE0U) #define ENET_TCR_ADDSEL_SHIFT (5U) +/*! ADDSEL - Source MAC Address Select On Transmit + * 0b000..Node MAC address programmed on PADDR1/2 registers. + * 0b100..Reserved. + * 0b101..Reserved. + * 0b110..Reserved. + */ #define ENET_TCR_ADDSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_ADDSEL_SHIFT)) & ENET_TCR_ADDSEL_MASK) #define ENET_TCR_ADDINS_MASK (0x100U) #define ENET_TCR_ADDINS_SHIFT (8U) +/*! ADDINS - Set MAC Address On Transmit + * 0b0..The source MAC address is not modified by the MAC. + * 0b1..The MAC overwrites the source MAC address with the programmed MAC address according to ADDSEL. + */ #define ENET_TCR_ADDINS(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_ADDINS_SHIFT)) & ENET_TCR_ADDINS_MASK) #define ENET_TCR_CRCFWD_MASK (0x200U) #define ENET_TCR_CRCFWD_SHIFT (9U) +/*! CRCFWD - Forward Frame From Application With CRC + * 0b0..TxBD[TC] controls whether the frame has a CRC from the application. + * 0b1..The transmitter does not append any CRC to transmitted frames, as it is expecting a frame with CRC from the application. + */ #define ENET_TCR_CRCFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_CRCFWD_SHIFT)) & ENET_TCR_CRCFWD_MASK) +/*! @} */ /*! @name PALR - Physical Address Lower Register */ +/*! @{ */ #define ENET_PALR_PADDR1_MASK (0xFFFFFFFFU) #define ENET_PALR_PADDR1_SHIFT (0U) #define ENET_PALR_PADDR1(x) (((uint32_t)(((uint32_t)(x)) << ENET_PALR_PADDR1_SHIFT)) & ENET_PALR_PADDR1_MASK) +/*! @} */ /*! @name PAUR - Physical Address Upper Register */ +/*! @{ */ #define ENET_PAUR_TYPE_MASK (0xFFFFU) #define ENET_PAUR_TYPE_SHIFT (0U) #define ENET_PAUR_TYPE(x) (((uint32_t)(((uint32_t)(x)) << ENET_PAUR_TYPE_SHIFT)) & ENET_PAUR_TYPE_MASK) #define ENET_PAUR_PADDR2_MASK (0xFFFF0000U) #define ENET_PAUR_PADDR2_SHIFT (16U) #define ENET_PAUR_PADDR2(x) (((uint32_t)(((uint32_t)(x)) << ENET_PAUR_PADDR2_SHIFT)) & ENET_PAUR_PADDR2_MASK) +/*! @} */ /*! @name OPD - Opcode/Pause Duration Register */ +/*! @{ */ #define ENET_OPD_PAUSE_DUR_MASK (0xFFFFU) #define ENET_OPD_PAUSE_DUR_SHIFT (0U) #define ENET_OPD_PAUSE_DUR(x) (((uint32_t)(((uint32_t)(x)) << ENET_OPD_PAUSE_DUR_SHIFT)) & ENET_OPD_PAUSE_DUR_MASK) #define ENET_OPD_OPCODE_MASK (0xFFFF0000U) #define ENET_OPD_OPCODE_SHIFT (16U) #define ENET_OPD_OPCODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_OPD_OPCODE_SHIFT)) & ENET_OPD_OPCODE_MASK) +/*! @} */ /*! @name TXIC - Transmit Interrupt Coalescing Register */ +/*! @{ */ #define ENET_TXIC_ICTT_MASK (0xFFFFU) #define ENET_TXIC_ICTT_SHIFT (0U) #define ENET_TXIC_ICTT(x) (((uint32_t)(((uint32_t)(x)) << ENET_TXIC_ICTT_SHIFT)) & ENET_TXIC_ICTT_MASK) @@ -8879,12 +13614,22 @@ typedef struct { #define ENET_TXIC_ICFT(x) (((uint32_t)(((uint32_t)(x)) << ENET_TXIC_ICFT_SHIFT)) & ENET_TXIC_ICFT_MASK) #define ENET_TXIC_ICCS_MASK (0x40000000U) #define ENET_TXIC_ICCS_SHIFT (30U) +/*! ICCS - Interrupt Coalescing Timer Clock Source Select + * 0b0..Use MII/GMII TX clocks. + * 0b1..Use ENET system clock. + */ #define ENET_TXIC_ICCS(x) (((uint32_t)(((uint32_t)(x)) << ENET_TXIC_ICCS_SHIFT)) & ENET_TXIC_ICCS_MASK) #define ENET_TXIC_ICEN_MASK (0x80000000U) #define ENET_TXIC_ICEN_SHIFT (31U) +/*! ICEN - Interrupt Coalescing Enable + * 0b0..Disable Interrupt coalescing. + * 0b1..Enable Interrupt coalescing. + */ #define ENET_TXIC_ICEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_TXIC_ICEN_SHIFT)) & ENET_TXIC_ICEN_MASK) +/*! @} */ /*! @name RXIC - Receive Interrupt Coalescing Register */ +/*! @{ */ #define ENET_RXIC_ICTT_MASK (0xFFFFU) #define ENET_RXIC_ICTT_SHIFT (0U) #define ENET_RXIC_ICTT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RXIC_ICTT_SHIFT)) & ENET_RXIC_ICTT_MASK) @@ -8893,482 +13638,773 @@ typedef struct { #define ENET_RXIC_ICFT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RXIC_ICFT_SHIFT)) & ENET_RXIC_ICFT_MASK) #define ENET_RXIC_ICCS_MASK (0x40000000U) #define ENET_RXIC_ICCS_SHIFT (30U) +/*! ICCS - Interrupt Coalescing Timer Clock Source Select + * 0b0..Use MII/GMII TX clocks. + * 0b1..Use ENET system clock. + */ #define ENET_RXIC_ICCS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RXIC_ICCS_SHIFT)) & ENET_RXIC_ICCS_MASK) #define ENET_RXIC_ICEN_MASK (0x80000000U) #define ENET_RXIC_ICEN_SHIFT (31U) +/*! ICEN - Interrupt Coalescing Enable + * 0b0..Disable Interrupt coalescing. + * 0b1..Enable Interrupt coalescing. + */ #define ENET_RXIC_ICEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_RXIC_ICEN_SHIFT)) & ENET_RXIC_ICEN_MASK) +/*! @} */ /*! @name IAUR - Descriptor Individual Upper Address Register */ +/*! @{ */ #define ENET_IAUR_IADDR1_MASK (0xFFFFFFFFU) #define ENET_IAUR_IADDR1_SHIFT (0U) #define ENET_IAUR_IADDR1(x) (((uint32_t)(((uint32_t)(x)) << ENET_IAUR_IADDR1_SHIFT)) & ENET_IAUR_IADDR1_MASK) +/*! @} */ /*! @name IALR - Descriptor Individual Lower Address Register */ +/*! @{ */ #define ENET_IALR_IADDR2_MASK (0xFFFFFFFFU) #define ENET_IALR_IADDR2_SHIFT (0U) #define ENET_IALR_IADDR2(x) (((uint32_t)(((uint32_t)(x)) << ENET_IALR_IADDR2_SHIFT)) & ENET_IALR_IADDR2_MASK) +/*! @} */ /*! @name GAUR - Descriptor Group Upper Address Register */ +/*! @{ */ #define ENET_GAUR_GADDR1_MASK (0xFFFFFFFFU) #define ENET_GAUR_GADDR1_SHIFT (0U) #define ENET_GAUR_GADDR1(x) (((uint32_t)(((uint32_t)(x)) << ENET_GAUR_GADDR1_SHIFT)) & ENET_GAUR_GADDR1_MASK) +/*! @} */ /*! @name GALR - Descriptor Group Lower Address Register */ +/*! @{ */ #define ENET_GALR_GADDR2_MASK (0xFFFFFFFFU) #define ENET_GALR_GADDR2_SHIFT (0U) #define ENET_GALR_GADDR2(x) (((uint32_t)(((uint32_t)(x)) << ENET_GALR_GADDR2_SHIFT)) & ENET_GALR_GADDR2_MASK) +/*! @} */ /*! @name TFWR - Transmit FIFO Watermark Register */ +/*! @{ */ #define ENET_TFWR_TFWR_MASK (0x3FU) #define ENET_TFWR_TFWR_SHIFT (0U) +/*! TFWR - Transmit FIFO Write + * 0b000000..64 bytes written. + * 0b000001..64 bytes written. + * 0b000010..128 bytes written. + * 0b000011..192 bytes written. + * 0b011111..1984 bytes written. + */ #define ENET_TFWR_TFWR(x) (((uint32_t)(((uint32_t)(x)) << ENET_TFWR_TFWR_SHIFT)) & ENET_TFWR_TFWR_MASK) #define ENET_TFWR_STRFWD_MASK (0x100U) #define ENET_TFWR_STRFWD_SHIFT (8U) +/*! STRFWD - Store And Forward Enable + * 0b0..Reset. The transmission start threshold is programmed in TFWR[TFWR]. + * 0b1..Enabled. + */ #define ENET_TFWR_STRFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_TFWR_STRFWD_SHIFT)) & ENET_TFWR_STRFWD_MASK) +/*! @} */ /*! @name RDSR - Receive Descriptor Ring Start Register */ +/*! @{ */ #define ENET_RDSR_R_DES_START_MASK (0xFFFFFFF8U) #define ENET_RDSR_R_DES_START_SHIFT (3U) #define ENET_RDSR_R_DES_START(x) (((uint32_t)(((uint32_t)(x)) << ENET_RDSR_R_DES_START_SHIFT)) & ENET_RDSR_R_DES_START_MASK) +/*! @} */ /*! @name TDSR - Transmit Buffer Descriptor Ring Start Register */ +/*! @{ */ #define ENET_TDSR_X_DES_START_MASK (0xFFFFFFF8U) #define ENET_TDSR_X_DES_START_SHIFT (3U) #define ENET_TDSR_X_DES_START(x) (((uint32_t)(((uint32_t)(x)) << ENET_TDSR_X_DES_START_SHIFT)) & ENET_TDSR_X_DES_START_MASK) +/*! @} */ /*! @name MRBR - Maximum Receive Buffer Size Register */ +/*! @{ */ #define ENET_MRBR_R_BUF_SIZE_MASK (0x3FF0U) #define ENET_MRBR_R_BUF_SIZE_SHIFT (4U) #define ENET_MRBR_R_BUF_SIZE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MRBR_R_BUF_SIZE_SHIFT)) & ENET_MRBR_R_BUF_SIZE_MASK) +/*! @} */ /*! @name RSFL - Receive FIFO Section Full Threshold */ +/*! @{ */ #define ENET_RSFL_RX_SECTION_FULL_MASK (0xFFU) #define ENET_RSFL_RX_SECTION_FULL_SHIFT (0U) #define ENET_RSFL_RX_SECTION_FULL(x) (((uint32_t)(((uint32_t)(x)) << ENET_RSFL_RX_SECTION_FULL_SHIFT)) & ENET_RSFL_RX_SECTION_FULL_MASK) +/*! @} */ /*! @name RSEM - Receive FIFO Section Empty Threshold */ +/*! @{ */ #define ENET_RSEM_RX_SECTION_EMPTY_MASK (0xFFU) #define ENET_RSEM_RX_SECTION_EMPTY_SHIFT (0U) #define ENET_RSEM_RX_SECTION_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_RSEM_RX_SECTION_EMPTY_SHIFT)) & ENET_RSEM_RX_SECTION_EMPTY_MASK) #define ENET_RSEM_STAT_SECTION_EMPTY_MASK (0x1F0000U) #define ENET_RSEM_STAT_SECTION_EMPTY_SHIFT (16U) #define ENET_RSEM_STAT_SECTION_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_RSEM_STAT_SECTION_EMPTY_SHIFT)) & ENET_RSEM_STAT_SECTION_EMPTY_MASK) +/*! @} */ /*! @name RAEM - Receive FIFO Almost Empty Threshold */ +/*! @{ */ #define ENET_RAEM_RX_ALMOST_EMPTY_MASK (0xFFU) #define ENET_RAEM_RX_ALMOST_EMPTY_SHIFT (0U) #define ENET_RAEM_RX_ALMOST_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_RAEM_RX_ALMOST_EMPTY_SHIFT)) & ENET_RAEM_RX_ALMOST_EMPTY_MASK) +/*! @} */ /*! @name RAFL - Receive FIFO Almost Full Threshold */ +/*! @{ */ #define ENET_RAFL_RX_ALMOST_FULL_MASK (0xFFU) #define ENET_RAFL_RX_ALMOST_FULL_SHIFT (0U) #define ENET_RAFL_RX_ALMOST_FULL(x) (((uint32_t)(((uint32_t)(x)) << ENET_RAFL_RX_ALMOST_FULL_SHIFT)) & ENET_RAFL_RX_ALMOST_FULL_MASK) +/*! @} */ /*! @name TSEM - Transmit FIFO Section Empty Threshold */ +/*! @{ */ #define ENET_TSEM_TX_SECTION_EMPTY_MASK (0xFFU) #define ENET_TSEM_TX_SECTION_EMPTY_SHIFT (0U) #define ENET_TSEM_TX_SECTION_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_TSEM_TX_SECTION_EMPTY_SHIFT)) & ENET_TSEM_TX_SECTION_EMPTY_MASK) +/*! @} */ /*! @name TAEM - Transmit FIFO Almost Empty Threshold */ +/*! @{ */ #define ENET_TAEM_TX_ALMOST_EMPTY_MASK (0xFFU) #define ENET_TAEM_TX_ALMOST_EMPTY_SHIFT (0U) #define ENET_TAEM_TX_ALMOST_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_TAEM_TX_ALMOST_EMPTY_SHIFT)) & ENET_TAEM_TX_ALMOST_EMPTY_MASK) +/*! @} */ /*! @name TAFL - Transmit FIFO Almost Full Threshold */ +/*! @{ */ #define ENET_TAFL_TX_ALMOST_FULL_MASK (0xFFU) #define ENET_TAFL_TX_ALMOST_FULL_SHIFT (0U) #define ENET_TAFL_TX_ALMOST_FULL(x) (((uint32_t)(((uint32_t)(x)) << ENET_TAFL_TX_ALMOST_FULL_SHIFT)) & ENET_TAFL_TX_ALMOST_FULL_MASK) +/*! @} */ /*! @name TIPG - Transmit Inter-Packet Gap */ +/*! @{ */ #define ENET_TIPG_IPG_MASK (0x1FU) #define ENET_TIPG_IPG_SHIFT (0U) #define ENET_TIPG_IPG(x) (((uint32_t)(((uint32_t)(x)) << ENET_TIPG_IPG_SHIFT)) & ENET_TIPG_IPG_MASK) +/*! @} */ /*! @name FTRL - Frame Truncation Length */ +/*! @{ */ #define ENET_FTRL_TRUNC_FL_MASK (0x3FFFU) #define ENET_FTRL_TRUNC_FL_SHIFT (0U) #define ENET_FTRL_TRUNC_FL(x) (((uint32_t)(((uint32_t)(x)) << ENET_FTRL_TRUNC_FL_SHIFT)) & ENET_FTRL_TRUNC_FL_MASK) +/*! @} */ /*! @name TACC - Transmit Accelerator Function Configuration */ +/*! @{ */ #define ENET_TACC_SHIFT16_MASK (0x1U) #define ENET_TACC_SHIFT16_SHIFT (0U) +/*! SHIFT16 - TX FIFO Shift-16 + * 0b0..Disabled. + * 0b1..Indicates to the transmit data FIFO that the written frames contain two additional octets before the frame data. This means the actual frame begins at bit 16 of the first word written into the FIFO. This function allows putting the frame payload on a 32-bit boundary in memory, as the 14-byte Ethernet header is extended to a 16-byte header. + */ #define ENET_TACC_SHIFT16(x) (((uint32_t)(((uint32_t)(x)) << ENET_TACC_SHIFT16_SHIFT)) & ENET_TACC_SHIFT16_MASK) #define ENET_TACC_IPCHK_MASK (0x8U) #define ENET_TACC_IPCHK_SHIFT (3U) +/*! IPCHK + * 0b0..Checksum is not inserted. + * 0b1..If an IP frame is transmitted, the checksum is inserted automatically. The IP header checksum field must be cleared. If a non-IP frame is transmitted the frame is not modified. + */ #define ENET_TACC_IPCHK(x) (((uint32_t)(((uint32_t)(x)) << ENET_TACC_IPCHK_SHIFT)) & ENET_TACC_IPCHK_MASK) #define ENET_TACC_PROCHK_MASK (0x10U) #define ENET_TACC_PROCHK_SHIFT (4U) +/*! PROCHK + * 0b0..Checksum not inserted. + * 0b1..If an IP frame with a known protocol is transmitted, the checksum is inserted automatically into the frame. The checksum field must be cleared. The other frames are not modified. + */ #define ENET_TACC_PROCHK(x) (((uint32_t)(((uint32_t)(x)) << ENET_TACC_PROCHK_SHIFT)) & ENET_TACC_PROCHK_MASK) +/*! @} */ /*! @name RACC - Receive Accelerator Function Configuration */ +/*! @{ */ #define ENET_RACC_PADREM_MASK (0x1U) #define ENET_RACC_PADREM_SHIFT (0U) +/*! PADREM - Enable Padding Removal For Short IP Frames + * 0b0..Padding not removed. + * 0b1..Any bytes following the IP payload section of the frame are removed from the frame. + */ #define ENET_RACC_PADREM(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_PADREM_SHIFT)) & ENET_RACC_PADREM_MASK) #define ENET_RACC_IPDIS_MASK (0x2U) #define ENET_RACC_IPDIS_SHIFT (1U) +/*! IPDIS - Enable Discard Of Frames With Wrong IPv4 Header Checksum + * 0b0..Frames with wrong IPv4 header checksum are not discarded. + * 0b1..If an IPv4 frame is received with a mismatching header checksum, the frame is discarded. IPv6 has no header checksum and is not affected by this setting. Discarding is only available when the RX FIFO operates in store and forward mode (RSFL cleared). + */ #define ENET_RACC_IPDIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_IPDIS_SHIFT)) & ENET_RACC_IPDIS_MASK) #define ENET_RACC_PRODIS_MASK (0x4U) #define ENET_RACC_PRODIS_SHIFT (2U) +/*! PRODIS - Enable Discard Of Frames With Wrong Protocol Checksum + * 0b0..Frames with wrong checksum are not discarded. + * 0b1..If a TCP/IP, UDP/IP, or ICMP/IP frame is received that has a wrong TCP, UDP, or ICMP checksum, the frame is discarded. Discarding is only available when the RX FIFO operates in store and forward mode (RSFL cleared). + */ #define ENET_RACC_PRODIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_PRODIS_SHIFT)) & ENET_RACC_PRODIS_MASK) #define ENET_RACC_LINEDIS_MASK (0x40U) #define ENET_RACC_LINEDIS_SHIFT (6U) +/*! LINEDIS - Enable Discard Of Frames With MAC Layer Errors + * 0b0..Frames with errors are not discarded. + * 0b1..Any frame received with a CRC, length, or PHY error is automatically discarded and not forwarded to the user application interface. + */ #define ENET_RACC_LINEDIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_LINEDIS_SHIFT)) & ENET_RACC_LINEDIS_MASK) #define ENET_RACC_SHIFT16_MASK (0x80U) #define ENET_RACC_SHIFT16_SHIFT (7U) +/*! SHIFT16 - RX FIFO Shift-16 + * 0b0..Disabled. + * 0b1..Instructs the MAC to write two additional bytes in front of each frame received into the RX FIFO. + */ #define ENET_RACC_SHIFT16(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_SHIFT16_SHIFT)) & ENET_RACC_SHIFT16_MASK) +/*! @} */ /*! @name RMON_T_PACKETS - Tx Packet Count Statistic Register */ +/*! @{ */ #define ENET_RMON_T_PACKETS_TXPKTS_MASK (0xFFFFU) #define ENET_RMON_T_PACKETS_TXPKTS_SHIFT (0U) #define ENET_RMON_T_PACKETS_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_PACKETS_TXPKTS_SHIFT)) & ENET_RMON_T_PACKETS_TXPKTS_MASK) +/*! @} */ /*! @name RMON_T_BC_PKT - Tx Broadcast Packets Statistic Register */ +/*! @{ */ #define ENET_RMON_T_BC_PKT_TXPKTS_MASK (0xFFFFU) #define ENET_RMON_T_BC_PKT_TXPKTS_SHIFT (0U) #define ENET_RMON_T_BC_PKT_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_BC_PKT_TXPKTS_SHIFT)) & ENET_RMON_T_BC_PKT_TXPKTS_MASK) +/*! @} */ /*! @name RMON_T_MC_PKT - Tx Multicast Packets Statistic Register */ +/*! @{ */ #define ENET_RMON_T_MC_PKT_TXPKTS_MASK (0xFFFFU) #define ENET_RMON_T_MC_PKT_TXPKTS_SHIFT (0U) #define ENET_RMON_T_MC_PKT_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_MC_PKT_TXPKTS_SHIFT)) & ENET_RMON_T_MC_PKT_TXPKTS_MASK) +/*! @} */ /*! @name RMON_T_CRC_ALIGN - Tx Packets with CRC/Align Error Statistic Register */ +/*! @{ */ #define ENET_RMON_T_CRC_ALIGN_TXPKTS_MASK (0xFFFFU) #define ENET_RMON_T_CRC_ALIGN_TXPKTS_SHIFT (0U) #define ENET_RMON_T_CRC_ALIGN_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_CRC_ALIGN_TXPKTS_SHIFT)) & ENET_RMON_T_CRC_ALIGN_TXPKTS_MASK) +/*! @} */ /*! @name RMON_T_UNDERSIZE - Tx Packets Less Than Bytes and Good CRC Statistic Register */ +/*! @{ */ #define ENET_RMON_T_UNDERSIZE_TXPKTS_MASK (0xFFFFU) #define ENET_RMON_T_UNDERSIZE_TXPKTS_SHIFT (0U) #define ENET_RMON_T_UNDERSIZE_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_UNDERSIZE_TXPKTS_SHIFT)) & ENET_RMON_T_UNDERSIZE_TXPKTS_MASK) +/*! @} */ /*! @name RMON_T_OVERSIZE - Tx Packets GT MAX_FL bytes and Good CRC Statistic Register */ +/*! @{ */ #define ENET_RMON_T_OVERSIZE_TXPKTS_MASK (0xFFFFU) #define ENET_RMON_T_OVERSIZE_TXPKTS_SHIFT (0U) #define ENET_RMON_T_OVERSIZE_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_OVERSIZE_TXPKTS_SHIFT)) & ENET_RMON_T_OVERSIZE_TXPKTS_MASK) +/*! @} */ /*! @name RMON_T_FRAG - Tx Packets Less Than 64 Bytes and Bad CRC Statistic Register */ +/*! @{ */ #define ENET_RMON_T_FRAG_TXPKTS_MASK (0xFFFFU) #define ENET_RMON_T_FRAG_TXPKTS_SHIFT (0U) #define ENET_RMON_T_FRAG_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_FRAG_TXPKTS_SHIFT)) & ENET_RMON_T_FRAG_TXPKTS_MASK) +/*! @} */ /*! @name RMON_T_JAB - Tx Packets Greater Than MAX_FL bytes and Bad CRC Statistic Register */ +/*! @{ */ #define ENET_RMON_T_JAB_TXPKTS_MASK (0xFFFFU) #define ENET_RMON_T_JAB_TXPKTS_SHIFT (0U) #define ENET_RMON_T_JAB_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_JAB_TXPKTS_SHIFT)) & ENET_RMON_T_JAB_TXPKTS_MASK) +/*! @} */ /*! @name RMON_T_COL - Tx Collision Count Statistic Register */ +/*! @{ */ #define ENET_RMON_T_COL_TXPKTS_MASK (0xFFFFU) #define ENET_RMON_T_COL_TXPKTS_SHIFT (0U) #define ENET_RMON_T_COL_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_COL_TXPKTS_SHIFT)) & ENET_RMON_T_COL_TXPKTS_MASK) +/*! @} */ /*! @name RMON_T_P64 - Tx 64-Byte Packets Statistic Register */ +/*! @{ */ #define ENET_RMON_T_P64_TXPKTS_MASK (0xFFFFU) #define ENET_RMON_T_P64_TXPKTS_SHIFT (0U) #define ENET_RMON_T_P64_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P64_TXPKTS_SHIFT)) & ENET_RMON_T_P64_TXPKTS_MASK) +/*! @} */ /*! @name RMON_T_P65TO127 - Tx 65- to 127-byte Packets Statistic Register */ +/*! @{ */ #define ENET_RMON_T_P65TO127_TXPKTS_MASK (0xFFFFU) #define ENET_RMON_T_P65TO127_TXPKTS_SHIFT (0U) #define ENET_RMON_T_P65TO127_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P65TO127_TXPKTS_SHIFT)) & ENET_RMON_T_P65TO127_TXPKTS_MASK) +/*! @} */ /*! @name RMON_T_P128TO255 - Tx 128- to 255-byte Packets Statistic Register */ +/*! @{ */ #define ENET_RMON_T_P128TO255_TXPKTS_MASK (0xFFFFU) #define ENET_RMON_T_P128TO255_TXPKTS_SHIFT (0U) #define ENET_RMON_T_P128TO255_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P128TO255_TXPKTS_SHIFT)) & ENET_RMON_T_P128TO255_TXPKTS_MASK) +/*! @} */ /*! @name RMON_T_P256TO511 - Tx 256- to 511-byte Packets Statistic Register */ +/*! @{ */ #define ENET_RMON_T_P256TO511_TXPKTS_MASK (0xFFFFU) #define ENET_RMON_T_P256TO511_TXPKTS_SHIFT (0U) #define ENET_RMON_T_P256TO511_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P256TO511_TXPKTS_SHIFT)) & ENET_RMON_T_P256TO511_TXPKTS_MASK) +/*! @} */ /*! @name RMON_T_P512TO1023 - Tx 512- to 1023-byte Packets Statistic Register */ +/*! @{ */ #define ENET_RMON_T_P512TO1023_TXPKTS_MASK (0xFFFFU) #define ENET_RMON_T_P512TO1023_TXPKTS_SHIFT (0U) #define ENET_RMON_T_P512TO1023_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P512TO1023_TXPKTS_SHIFT)) & ENET_RMON_T_P512TO1023_TXPKTS_MASK) +/*! @} */ /*! @name RMON_T_P1024TO2047 - Tx 1024- to 2047-byte Packets Statistic Register */ +/*! @{ */ #define ENET_RMON_T_P1024TO2047_TXPKTS_MASK (0xFFFFU) #define ENET_RMON_T_P1024TO2047_TXPKTS_SHIFT (0U) #define ENET_RMON_T_P1024TO2047_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P1024TO2047_TXPKTS_SHIFT)) & ENET_RMON_T_P1024TO2047_TXPKTS_MASK) +/*! @} */ /*! @name RMON_T_P_GTE2048 - Tx Packets Greater Than 2048 Bytes Statistic Register */ +/*! @{ */ #define ENET_RMON_T_P_GTE2048_TXPKTS_MASK (0xFFFFU) #define ENET_RMON_T_P_GTE2048_TXPKTS_SHIFT (0U) #define ENET_RMON_T_P_GTE2048_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P_GTE2048_TXPKTS_SHIFT)) & ENET_RMON_T_P_GTE2048_TXPKTS_MASK) +/*! @} */ /*! @name RMON_T_OCTETS - Tx Octets Statistic Register */ +/*! @{ */ #define ENET_RMON_T_OCTETS_TXOCTS_MASK (0xFFFFFFFFU) #define ENET_RMON_T_OCTETS_TXOCTS_SHIFT (0U) #define ENET_RMON_T_OCTETS_TXOCTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_OCTETS_TXOCTS_SHIFT)) & ENET_RMON_T_OCTETS_TXOCTS_MASK) +/*! @} */ /*! @name IEEE_T_FRAME_OK - Frames Transmitted OK Statistic Register */ +/*! @{ */ #define ENET_IEEE_T_FRAME_OK_COUNT_MASK (0xFFFFU) #define ENET_IEEE_T_FRAME_OK_COUNT_SHIFT (0U) #define ENET_IEEE_T_FRAME_OK_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_FRAME_OK_COUNT_SHIFT)) & ENET_IEEE_T_FRAME_OK_COUNT_MASK) +/*! @} */ /*! @name IEEE_T_1COL - Frames Transmitted with Single Collision Statistic Register */ +/*! @{ */ #define ENET_IEEE_T_1COL_COUNT_MASK (0xFFFFU) #define ENET_IEEE_T_1COL_COUNT_SHIFT (0U) #define ENET_IEEE_T_1COL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_1COL_COUNT_SHIFT)) & ENET_IEEE_T_1COL_COUNT_MASK) +/*! @} */ /*! @name IEEE_T_MCOL - Frames Transmitted with Multiple Collisions Statistic Register */ +/*! @{ */ #define ENET_IEEE_T_MCOL_COUNT_MASK (0xFFFFU) #define ENET_IEEE_T_MCOL_COUNT_SHIFT (0U) #define ENET_IEEE_T_MCOL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_MCOL_COUNT_SHIFT)) & ENET_IEEE_T_MCOL_COUNT_MASK) +/*! @} */ /*! @name IEEE_T_DEF - Frames Transmitted after Deferral Delay Statistic Register */ +/*! @{ */ #define ENET_IEEE_T_DEF_COUNT_MASK (0xFFFFU) #define ENET_IEEE_T_DEF_COUNT_SHIFT (0U) #define ENET_IEEE_T_DEF_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_DEF_COUNT_SHIFT)) & ENET_IEEE_T_DEF_COUNT_MASK) +/*! @} */ /*! @name IEEE_T_LCOL - Frames Transmitted with Late Collision Statistic Register */ +/*! @{ */ #define ENET_IEEE_T_LCOL_COUNT_MASK (0xFFFFU) #define ENET_IEEE_T_LCOL_COUNT_SHIFT (0U) #define ENET_IEEE_T_LCOL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_LCOL_COUNT_SHIFT)) & ENET_IEEE_T_LCOL_COUNT_MASK) +/*! @} */ /*! @name IEEE_T_EXCOL - Frames Transmitted with Excessive Collisions Statistic Register */ +/*! @{ */ #define ENET_IEEE_T_EXCOL_COUNT_MASK (0xFFFFU) #define ENET_IEEE_T_EXCOL_COUNT_SHIFT (0U) #define ENET_IEEE_T_EXCOL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_EXCOL_COUNT_SHIFT)) & ENET_IEEE_T_EXCOL_COUNT_MASK) +/*! @} */ /*! @name IEEE_T_MACERR - Frames Transmitted with Tx FIFO Underrun Statistic Register */ +/*! @{ */ #define ENET_IEEE_T_MACERR_COUNT_MASK (0xFFFFU) #define ENET_IEEE_T_MACERR_COUNT_SHIFT (0U) #define ENET_IEEE_T_MACERR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_MACERR_COUNT_SHIFT)) & ENET_IEEE_T_MACERR_COUNT_MASK) +/*! @} */ /*! @name IEEE_T_CSERR - Frames Transmitted with Carrier Sense Error Statistic Register */ +/*! @{ */ #define ENET_IEEE_T_CSERR_COUNT_MASK (0xFFFFU) #define ENET_IEEE_T_CSERR_COUNT_SHIFT (0U) #define ENET_IEEE_T_CSERR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_CSERR_COUNT_SHIFT)) & ENET_IEEE_T_CSERR_COUNT_MASK) +/*! @} */ /*! @name IEEE_T_SQE - Reserved Statistic Register */ +/*! @{ */ #define ENET_IEEE_T_SQE_COUNT_MASK (0xFFFFU) #define ENET_IEEE_T_SQE_COUNT_SHIFT (0U) #define ENET_IEEE_T_SQE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_SQE_COUNT_SHIFT)) & ENET_IEEE_T_SQE_COUNT_MASK) +/*! @} */ /*! @name IEEE_T_FDXFC - Flow Control Pause Frames Transmitted Statistic Register */ +/*! @{ */ #define ENET_IEEE_T_FDXFC_COUNT_MASK (0xFFFFU) #define ENET_IEEE_T_FDXFC_COUNT_SHIFT (0U) #define ENET_IEEE_T_FDXFC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_FDXFC_COUNT_SHIFT)) & ENET_IEEE_T_FDXFC_COUNT_MASK) +/*! @} */ /*! @name IEEE_T_OCTETS_OK - Octet Count for Frames Transmitted w/o Error Statistic Register */ +/*! @{ */ #define ENET_IEEE_T_OCTETS_OK_COUNT_MASK (0xFFFFFFFFU) #define ENET_IEEE_T_OCTETS_OK_COUNT_SHIFT (0U) #define ENET_IEEE_T_OCTETS_OK_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_OCTETS_OK_COUNT_SHIFT)) & ENET_IEEE_T_OCTETS_OK_COUNT_MASK) +/*! @} */ /*! @name RMON_R_PACKETS - Rx Packet Count Statistic Register */ +/*! @{ */ #define ENET_RMON_R_PACKETS_COUNT_MASK (0xFFFFU) #define ENET_RMON_R_PACKETS_COUNT_SHIFT (0U) #define ENET_RMON_R_PACKETS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_PACKETS_COUNT_SHIFT)) & ENET_RMON_R_PACKETS_COUNT_MASK) +/*! @} */ /*! @name RMON_R_BC_PKT - Rx Broadcast Packets Statistic Register */ +/*! @{ */ #define ENET_RMON_R_BC_PKT_COUNT_MASK (0xFFFFU) #define ENET_RMON_R_BC_PKT_COUNT_SHIFT (0U) #define ENET_RMON_R_BC_PKT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_BC_PKT_COUNT_SHIFT)) & ENET_RMON_R_BC_PKT_COUNT_MASK) +/*! @} */ /*! @name RMON_R_MC_PKT - Rx Multicast Packets Statistic Register */ +/*! @{ */ #define ENET_RMON_R_MC_PKT_COUNT_MASK (0xFFFFU) #define ENET_RMON_R_MC_PKT_COUNT_SHIFT (0U) #define ENET_RMON_R_MC_PKT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_MC_PKT_COUNT_SHIFT)) & ENET_RMON_R_MC_PKT_COUNT_MASK) +/*! @} */ /*! @name RMON_R_CRC_ALIGN - Rx Packets with CRC/Align Error Statistic Register */ +/*! @{ */ #define ENET_RMON_R_CRC_ALIGN_COUNT_MASK (0xFFFFU) #define ENET_RMON_R_CRC_ALIGN_COUNT_SHIFT (0U) #define ENET_RMON_R_CRC_ALIGN_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_CRC_ALIGN_COUNT_SHIFT)) & ENET_RMON_R_CRC_ALIGN_COUNT_MASK) +/*! @} */ /*! @name RMON_R_UNDERSIZE - Rx Packets with Less Than 64 Bytes and Good CRC Statistic Register */ +/*! @{ */ #define ENET_RMON_R_UNDERSIZE_COUNT_MASK (0xFFFFU) #define ENET_RMON_R_UNDERSIZE_COUNT_SHIFT (0U) #define ENET_RMON_R_UNDERSIZE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_UNDERSIZE_COUNT_SHIFT)) & ENET_RMON_R_UNDERSIZE_COUNT_MASK) +/*! @} */ /*! @name RMON_R_OVERSIZE - Rx Packets Greater Than MAX_FL and Good CRC Statistic Register */ +/*! @{ */ #define ENET_RMON_R_OVERSIZE_COUNT_MASK (0xFFFFU) #define ENET_RMON_R_OVERSIZE_COUNT_SHIFT (0U) #define ENET_RMON_R_OVERSIZE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_OVERSIZE_COUNT_SHIFT)) & ENET_RMON_R_OVERSIZE_COUNT_MASK) +/*! @} */ /*! @name RMON_R_FRAG - Rx Packets Less Than 64 Bytes and Bad CRC Statistic Register */ +/*! @{ */ #define ENET_RMON_R_FRAG_COUNT_MASK (0xFFFFU) #define ENET_RMON_R_FRAG_COUNT_SHIFT (0U) #define ENET_RMON_R_FRAG_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_FRAG_COUNT_SHIFT)) & ENET_RMON_R_FRAG_COUNT_MASK) +/*! @} */ /*! @name RMON_R_JAB - Rx Packets Greater Than MAX_FL Bytes and Bad CRC Statistic Register */ +/*! @{ */ #define ENET_RMON_R_JAB_COUNT_MASK (0xFFFFU) #define ENET_RMON_R_JAB_COUNT_SHIFT (0U) #define ENET_RMON_R_JAB_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_JAB_COUNT_SHIFT)) & ENET_RMON_R_JAB_COUNT_MASK) +/*! @} */ /*! @name RMON_R_P64 - Rx 64-Byte Packets Statistic Register */ +/*! @{ */ #define ENET_RMON_R_P64_COUNT_MASK (0xFFFFU) #define ENET_RMON_R_P64_COUNT_SHIFT (0U) #define ENET_RMON_R_P64_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P64_COUNT_SHIFT)) & ENET_RMON_R_P64_COUNT_MASK) +/*! @} */ /*! @name RMON_R_P65TO127 - Rx 65- to 127-Byte Packets Statistic Register */ +/*! @{ */ #define ENET_RMON_R_P65TO127_COUNT_MASK (0xFFFFU) #define ENET_RMON_R_P65TO127_COUNT_SHIFT (0U) #define ENET_RMON_R_P65TO127_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P65TO127_COUNT_SHIFT)) & ENET_RMON_R_P65TO127_COUNT_MASK) +/*! @} */ /*! @name RMON_R_P128TO255 - Rx 128- to 255-Byte Packets Statistic Register */ +/*! @{ */ #define ENET_RMON_R_P128TO255_COUNT_MASK (0xFFFFU) #define ENET_RMON_R_P128TO255_COUNT_SHIFT (0U) #define ENET_RMON_R_P128TO255_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P128TO255_COUNT_SHIFT)) & ENET_RMON_R_P128TO255_COUNT_MASK) +/*! @} */ /*! @name RMON_R_P256TO511 - Rx 256- to 511-Byte Packets Statistic Register */ +/*! @{ */ #define ENET_RMON_R_P256TO511_COUNT_MASK (0xFFFFU) #define ENET_RMON_R_P256TO511_COUNT_SHIFT (0U) #define ENET_RMON_R_P256TO511_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P256TO511_COUNT_SHIFT)) & ENET_RMON_R_P256TO511_COUNT_MASK) +/*! @} */ /*! @name RMON_R_P512TO1023 - Rx 512- to 1023-Byte Packets Statistic Register */ +/*! @{ */ #define ENET_RMON_R_P512TO1023_COUNT_MASK (0xFFFFU) #define ENET_RMON_R_P512TO1023_COUNT_SHIFT (0U) #define ENET_RMON_R_P512TO1023_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P512TO1023_COUNT_SHIFT)) & ENET_RMON_R_P512TO1023_COUNT_MASK) +/*! @} */ /*! @name RMON_R_P1024TO2047 - Rx 1024- to 2047-Byte Packets Statistic Register */ +/*! @{ */ #define ENET_RMON_R_P1024TO2047_COUNT_MASK (0xFFFFU) #define ENET_RMON_R_P1024TO2047_COUNT_SHIFT (0U) #define ENET_RMON_R_P1024TO2047_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P1024TO2047_COUNT_SHIFT)) & ENET_RMON_R_P1024TO2047_COUNT_MASK) +/*! @} */ /*! @name RMON_R_P_GTE2048 - Rx Packets Greater than 2048 Bytes Statistic Register */ +/*! @{ */ #define ENET_RMON_R_P_GTE2048_COUNT_MASK (0xFFFFU) #define ENET_RMON_R_P_GTE2048_COUNT_SHIFT (0U) #define ENET_RMON_R_P_GTE2048_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P_GTE2048_COUNT_SHIFT)) & ENET_RMON_R_P_GTE2048_COUNT_MASK) +/*! @} */ /*! @name RMON_R_OCTETS - Rx Octets Statistic Register */ +/*! @{ */ #define ENET_RMON_R_OCTETS_COUNT_MASK (0xFFFFFFFFU) #define ENET_RMON_R_OCTETS_COUNT_SHIFT (0U) #define ENET_RMON_R_OCTETS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_OCTETS_COUNT_SHIFT)) & ENET_RMON_R_OCTETS_COUNT_MASK) +/*! @} */ /*! @name IEEE_R_DROP - Frames not Counted Correctly Statistic Register */ +/*! @{ */ #define ENET_IEEE_R_DROP_COUNT_MASK (0xFFFFU) #define ENET_IEEE_R_DROP_COUNT_SHIFT (0U) #define ENET_IEEE_R_DROP_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_DROP_COUNT_SHIFT)) & ENET_IEEE_R_DROP_COUNT_MASK) +/*! @} */ /*! @name IEEE_R_FRAME_OK - Frames Received OK Statistic Register */ +/*! @{ */ #define ENET_IEEE_R_FRAME_OK_COUNT_MASK (0xFFFFU) #define ENET_IEEE_R_FRAME_OK_COUNT_SHIFT (0U) #define ENET_IEEE_R_FRAME_OK_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_FRAME_OK_COUNT_SHIFT)) & ENET_IEEE_R_FRAME_OK_COUNT_MASK) +/*! @} */ /*! @name IEEE_R_CRC - Frames Received with CRC Error Statistic Register */ +/*! @{ */ #define ENET_IEEE_R_CRC_COUNT_MASK (0xFFFFU) #define ENET_IEEE_R_CRC_COUNT_SHIFT (0U) #define ENET_IEEE_R_CRC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_CRC_COUNT_SHIFT)) & ENET_IEEE_R_CRC_COUNT_MASK) +/*! @} */ /*! @name IEEE_R_ALIGN - Frames Received with Alignment Error Statistic Register */ +/*! @{ */ #define ENET_IEEE_R_ALIGN_COUNT_MASK (0xFFFFU) #define ENET_IEEE_R_ALIGN_COUNT_SHIFT (0U) #define ENET_IEEE_R_ALIGN_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_ALIGN_COUNT_SHIFT)) & ENET_IEEE_R_ALIGN_COUNT_MASK) +/*! @} */ /*! @name IEEE_R_MACERR - Receive FIFO Overflow Count Statistic Register */ +/*! @{ */ #define ENET_IEEE_R_MACERR_COUNT_MASK (0xFFFFU) #define ENET_IEEE_R_MACERR_COUNT_SHIFT (0U) #define ENET_IEEE_R_MACERR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_MACERR_COUNT_SHIFT)) & ENET_IEEE_R_MACERR_COUNT_MASK) +/*! @} */ /*! @name IEEE_R_FDXFC - Flow Control Pause Frames Received Statistic Register */ +/*! @{ */ #define ENET_IEEE_R_FDXFC_COUNT_MASK (0xFFFFU) #define ENET_IEEE_R_FDXFC_COUNT_SHIFT (0U) #define ENET_IEEE_R_FDXFC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_FDXFC_COUNT_SHIFT)) & ENET_IEEE_R_FDXFC_COUNT_MASK) +/*! @} */ /*! @name IEEE_R_OCTETS_OK - Octet Count for Frames Received without Error Statistic Register */ +/*! @{ */ #define ENET_IEEE_R_OCTETS_OK_COUNT_MASK (0xFFFFFFFFU) #define ENET_IEEE_R_OCTETS_OK_COUNT_SHIFT (0U) #define ENET_IEEE_R_OCTETS_OK_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_OCTETS_OK_COUNT_SHIFT)) & ENET_IEEE_R_OCTETS_OK_COUNT_MASK) +/*! @} */ /*! @name ATCR - Adjustable Timer Control Register */ +/*! @{ */ #define ENET_ATCR_EN_MASK (0x1U) #define ENET_ATCR_EN_SHIFT (0U) +/*! EN - Enable Timer + * 0b0..The timer stops at the current value. + * 0b1..The timer starts incrementing. + */ #define ENET_ATCR_EN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_EN_SHIFT)) & ENET_ATCR_EN_MASK) #define ENET_ATCR_OFFEN_MASK (0x4U) #define ENET_ATCR_OFFEN_SHIFT (2U) +/*! OFFEN - Enable One-Shot Offset Event + * 0b0..Disable. + * 0b1..The timer can be reset to zero when the given offset time is reached (offset event). The field is cleared when the offset event is reached, so no further event occurs until the field is set again. The timer offset value must be set before setting this field. + */ #define ENET_ATCR_OFFEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_OFFEN_SHIFT)) & ENET_ATCR_OFFEN_MASK) #define ENET_ATCR_OFFRST_MASK (0x8U) #define ENET_ATCR_OFFRST_SHIFT (3U) +/*! OFFRST - Reset Timer On Offset Event + * 0b0..The timer is not affected and no action occurs, besides clearing OFFEN, when the offset is reached. + * 0b1..If OFFEN is set, the timer resets to zero when the offset setting is reached. The offset event does not cause a timer interrupt. + */ #define ENET_ATCR_OFFRST(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_OFFRST_SHIFT)) & ENET_ATCR_OFFRST_MASK) #define ENET_ATCR_PEREN_MASK (0x10U) #define ENET_ATCR_PEREN_SHIFT (4U) +/*! PEREN - Enable Periodical Event + * 0b0..Disable. + * 0b1..A period event interrupt can be generated (EIR[TS_TIMER]) and the event signal output is asserted when the timer wraps around according to the periodic setting ATPER. The timer period value must be set before setting this bit. Not all devices contain the event signal output. See the chip configuration details. + */ #define ENET_ATCR_PEREN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_PEREN_SHIFT)) & ENET_ATCR_PEREN_MASK) #define ENET_ATCR_PINPER_MASK (0x80U) #define ENET_ATCR_PINPER_SHIFT (7U) +/*! PINPER + * 0b0..Disable. + * 0b1..Enable. + */ #define ENET_ATCR_PINPER(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_PINPER_SHIFT)) & ENET_ATCR_PINPER_MASK) #define ENET_ATCR_RESTART_MASK (0x200U) #define ENET_ATCR_RESTART_SHIFT (9U) #define ENET_ATCR_RESTART(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_RESTART_SHIFT)) & ENET_ATCR_RESTART_MASK) #define ENET_ATCR_CAPTURE_MASK (0x800U) #define ENET_ATCR_CAPTURE_SHIFT (11U) +/*! CAPTURE - Capture Timer Value + * 0b0..No effect. + * 0b1..The current time is captured and can be read from the ATVR register. + */ #define ENET_ATCR_CAPTURE(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_CAPTURE_SHIFT)) & ENET_ATCR_CAPTURE_MASK) #define ENET_ATCR_SLAVE_MASK (0x2000U) #define ENET_ATCR_SLAVE_SHIFT (13U) +/*! SLAVE - Enable Timer Slave Mode + * 0b0..The timer is active and all configuration fields in this register are relevant. + * 0b1..The internal timer is disabled and the externally provided timer value is used. All other fields, except CAPTURE, in this register have no effect. CAPTURE can still be used to capture the current timer value. + */ #define ENET_ATCR_SLAVE(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_SLAVE_SHIFT)) & ENET_ATCR_SLAVE_MASK) +/*! @} */ /*! @name ATVR - Timer Value Register */ +/*! @{ */ #define ENET_ATVR_ATIME_MASK (0xFFFFFFFFU) #define ENET_ATVR_ATIME_SHIFT (0U) #define ENET_ATVR_ATIME(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATVR_ATIME_SHIFT)) & ENET_ATVR_ATIME_MASK) +/*! @} */ /*! @name ATOFF - Timer Offset Register */ +/*! @{ */ #define ENET_ATOFF_OFFSET_MASK (0xFFFFFFFFU) #define ENET_ATOFF_OFFSET_SHIFT (0U) #define ENET_ATOFF_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATOFF_OFFSET_SHIFT)) & ENET_ATOFF_OFFSET_MASK) +/*! @} */ /*! @name ATPER - Timer Period Register */ +/*! @{ */ #define ENET_ATPER_PERIOD_MASK (0xFFFFFFFFU) #define ENET_ATPER_PERIOD_SHIFT (0U) #define ENET_ATPER_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATPER_PERIOD_SHIFT)) & ENET_ATPER_PERIOD_MASK) +/*! @} */ /*! @name ATCOR - Timer Correction Register */ +/*! @{ */ #define ENET_ATCOR_COR_MASK (0x7FFFFFFFU) #define ENET_ATCOR_COR_SHIFT (0U) #define ENET_ATCOR_COR(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCOR_COR_SHIFT)) & ENET_ATCOR_COR_MASK) +/*! @} */ /*! @name ATINC - Time-Stamping Clock Period Register */ +/*! @{ */ #define ENET_ATINC_INC_MASK (0x7FU) #define ENET_ATINC_INC_SHIFT (0U) #define ENET_ATINC_INC(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATINC_INC_SHIFT)) & ENET_ATINC_INC_MASK) #define ENET_ATINC_INC_CORR_MASK (0x7F00U) #define ENET_ATINC_INC_CORR_SHIFT (8U) #define ENET_ATINC_INC_CORR(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATINC_INC_CORR_SHIFT)) & ENET_ATINC_INC_CORR_MASK) +/*! @} */ /*! @name ATSTMP - Timestamp of Last Transmitted Frame */ +/*! @{ */ #define ENET_ATSTMP_TIMESTAMP_MASK (0xFFFFFFFFU) #define ENET_ATSTMP_TIMESTAMP_SHIFT (0U) #define ENET_ATSTMP_TIMESTAMP(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATSTMP_TIMESTAMP_SHIFT)) & ENET_ATSTMP_TIMESTAMP_MASK) +/*! @} */ /*! @name TGSR - Timer Global Status Register */ +/*! @{ */ #define ENET_TGSR_TF0_MASK (0x1U) #define ENET_TGSR_TF0_SHIFT (0U) +/*! TF0 - Copy Of Timer Flag For Channel 0 + * 0b0..Timer Flag for Channel 0 is clear + * 0b1..Timer Flag for Channel 0 is set + */ #define ENET_TGSR_TF0(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF0_SHIFT)) & ENET_TGSR_TF0_MASK) #define ENET_TGSR_TF1_MASK (0x2U) #define ENET_TGSR_TF1_SHIFT (1U) +/*! TF1 - Copy Of Timer Flag For Channel 1 + * 0b0..Timer Flag for Channel 1 is clear + * 0b1..Timer Flag for Channel 1 is set + */ #define ENET_TGSR_TF1(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF1_SHIFT)) & ENET_TGSR_TF1_MASK) #define ENET_TGSR_TF2_MASK (0x4U) #define ENET_TGSR_TF2_SHIFT (2U) +/*! TF2 - Copy Of Timer Flag For Channel 2 + * 0b0..Timer Flag for Channel 2 is clear + * 0b1..Timer Flag for Channel 2 is set + */ #define ENET_TGSR_TF2(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF2_SHIFT)) & ENET_TGSR_TF2_MASK) #define ENET_TGSR_TF3_MASK (0x8U) #define ENET_TGSR_TF3_SHIFT (3U) +/*! TF3 - Copy Of Timer Flag For Channel 3 + * 0b0..Timer Flag for Channel 3 is clear + * 0b1..Timer Flag for Channel 3 is set + */ #define ENET_TGSR_TF3(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF3_SHIFT)) & ENET_TGSR_TF3_MASK) +/*! @} */ /*! @name TCSR - Timer Control Status Register */ +/*! @{ */ #define ENET_TCSR_TDRE_MASK (0x1U) #define ENET_TCSR_TDRE_SHIFT (0U) +/*! TDRE - Timer DMA Request Enable + * 0b0..DMA request is disabled + * 0b1..DMA request is enabled + */ #define ENET_TCSR_TDRE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TDRE_SHIFT)) & ENET_TCSR_TDRE_MASK) #define ENET_TCSR_TMODE_MASK (0x3CU) #define ENET_TCSR_TMODE_SHIFT (2U) +/*! TMODE - Timer Mode + * 0b0000..Timer Channel is disabled. + * 0b0001..Timer Channel is configured for Input Capture on rising edge. + * 0b0010..Timer Channel is configured for Input Capture on falling edge. + * 0b0011..Timer Channel is configured for Input Capture on both edges. + * 0b0100..Timer Channel is configured for Output Compare - software only. + * 0b0101..Timer Channel is configured for Output Compare - toggle output on compare. + * 0b0110..Timer Channel is configured for Output Compare - clear output on compare. + * 0b0111..Timer Channel is configured for Output Compare - set output on compare. + * 0b1000..Reserved + * 0b1010..Timer Channel is configured for Output Compare - clear output on compare, set output on overflow. + * 0b10x1..Timer Channel is configured for Output Compare - set output on compare, clear output on overflow. + * 0b110x..Reserved + * 0b1110..Timer Channel is configured for Output Compare - pulse output low on compare for 1 to 32 1588-clock cycles as specified by TPWC. + * 0b1111..Timer Channel is configured for Output Compare - pulse output high on compare for 1 to 32 1588-clock cycles as specified by TPWC. + */ #define ENET_TCSR_TMODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TMODE_SHIFT)) & ENET_TCSR_TMODE_MASK) #define ENET_TCSR_TIE_MASK (0x40U) #define ENET_TCSR_TIE_SHIFT (6U) +/*! TIE - Timer Interrupt Enable + * 0b0..Interrupt is disabled + * 0b1..Interrupt is enabled + */ #define ENET_TCSR_TIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TIE_SHIFT)) & ENET_TCSR_TIE_MASK) #define ENET_TCSR_TF_MASK (0x80U) #define ENET_TCSR_TF_SHIFT (7U) +/*! TF - Timer Flag + * 0b0..Input Capture or Output Compare has not occurred. + * 0b1..Input Capture or Output Compare has occurred. + */ #define ENET_TCSR_TF(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TF_SHIFT)) & ENET_TCSR_TF_MASK) #define ENET_TCSR_TPWC_MASK (0xF800U) #define ENET_TCSR_TPWC_SHIFT (11U) +/*! TPWC - Timer PulseWidth Control + * 0b00000..Pulse width is one 1588-clock cycle. + * 0b00001..Pulse width is two 1588-clock cycles. + * 0b00010..Pulse width is three 1588-clock cycles. + * 0b00011..Pulse width is four 1588-clock cycles. + * 0b11111..Pulse width is 32 1588-clock cycles. + */ #define ENET_TCSR_TPWC(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TPWC_SHIFT)) & ENET_TCSR_TPWC_MASK) +/*! @} */ /* The count of ENET_TCSR */ #define ENET_TCSR_COUNT (4U) /*! @name TCCR - Timer Compare Capture Register */ +/*! @{ */ #define ENET_TCCR_TCC_MASK (0xFFFFFFFFU) #define ENET_TCCR_TCC_SHIFT (0U) #define ENET_TCCR_TCC(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCCR_TCC_SHIFT)) & ENET_TCCR_TCC_MASK) +/*! @} */ /* The count of ENET_TCCR */ #define ENET_TCCR_COUNT (4U) @@ -9431,6 +14467,7 @@ typedef struct { */ /*! @name CTRL - Control Register */ +/*! @{ */ #define EWM_CTRL_EWMEN_MASK (0x1U) #define EWM_CTRL_EWMEN_SHIFT (0U) #define EWM_CTRL_EWMEN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_EWMEN_SHIFT)) & EWM_CTRL_EWMEN_MASK) @@ -9443,31 +14480,42 @@ typedef struct { #define EWM_CTRL_INTEN_MASK (0x8U) #define EWM_CTRL_INTEN_SHIFT (3U) #define EWM_CTRL_INTEN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_INTEN_SHIFT)) & EWM_CTRL_INTEN_MASK) +/*! @} */ /*! @name SERV - Service Register */ +/*! @{ */ #define EWM_SERV_SERVICE_MASK (0xFFU) #define EWM_SERV_SERVICE_SHIFT (0U) #define EWM_SERV_SERVICE(x) (((uint8_t)(((uint8_t)(x)) << EWM_SERV_SERVICE_SHIFT)) & EWM_SERV_SERVICE_MASK) +/*! @} */ /*! @name CMPL - Compare Low Register */ +/*! @{ */ #define EWM_CMPL_COMPAREL_MASK (0xFFU) #define EWM_CMPL_COMPAREL_SHIFT (0U) #define EWM_CMPL_COMPAREL(x) (((uint8_t)(((uint8_t)(x)) << EWM_CMPL_COMPAREL_SHIFT)) & EWM_CMPL_COMPAREL_MASK) +/*! @} */ /*! @name CMPH - Compare High Register */ +/*! @{ */ #define EWM_CMPH_COMPAREH_MASK (0xFFU) #define EWM_CMPH_COMPAREH_SHIFT (0U) #define EWM_CMPH_COMPAREH(x) (((uint8_t)(((uint8_t)(x)) << EWM_CMPH_COMPAREH_SHIFT)) & EWM_CMPH_COMPAREH_MASK) +/*! @} */ /*! @name CLKCTRL - Clock Control Register */ +/*! @{ */ #define EWM_CLKCTRL_CLKSEL_MASK (0x3U) #define EWM_CLKCTRL_CLKSEL_SHIFT (0U) #define EWM_CLKCTRL_CLKSEL(x) (((uint8_t)(((uint8_t)(x)) << EWM_CLKCTRL_CLKSEL_SHIFT)) & EWM_CLKCTRL_CLKSEL_MASK) +/*! @} */ /*! @name CLKPRESCALER - Clock Prescaler Register */ +/*! @{ */ #define EWM_CLKPRESCALER_CLK_DIV_MASK (0xFFU) #define EWM_CLKPRESCALER_CLK_DIV_SHIFT (0U) #define EWM_CLKPRESCALER_CLK_DIV(x) (((uint8_t)(((uint8_t)(x)) << EWM_CLKPRESCALER_CLK_DIV_SHIFT)) & EWM_CLKPRESCALER_CLK_DIV_MASK) +/*! @} */ /*! @@ -9554,8 +14602,13 @@ typedef struct { */ /*! @name VERID - Version ID Register */ +/*! @{ */ #define FLEXIO_VERID_FEATURE_MASK (0xFFFFU) #define FLEXIO_VERID_FEATURE_SHIFT (0U) +/*! FEATURE - Feature Specification Number + * 0b0000000000000000..Standard features implemented. + * 0b0000000000000001..Supports state, logic and parallel modes. + */ #define FLEXIO_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_FEATURE_SHIFT)) & FLEXIO_VERID_FEATURE_MASK) #define FLEXIO_VERID_MINOR_MASK (0xFF0000U) #define FLEXIO_VERID_MINOR_SHIFT (16U) @@ -9563,8 +14616,10 @@ typedef struct { #define FLEXIO_VERID_MAJOR_MASK (0xFF000000U) #define FLEXIO_VERID_MAJOR_SHIFT (24U) #define FLEXIO_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_MAJOR_SHIFT)) & FLEXIO_VERID_MAJOR_MASK) +/*! @} */ /*! @name PARAM - Parameter Register */ +/*! @{ */ #define FLEXIO_PARAM_SHIFTER_MASK (0xFFU) #define FLEXIO_PARAM_SHIFTER_SHIFT (0U) #define FLEXIO_PARAM_SHIFTER(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_SHIFTER_SHIFT)) & FLEXIO_PARAM_SHIFTER_MASK) @@ -9577,221 +14632,402 @@ typedef struct { #define FLEXIO_PARAM_TRIGGER_MASK (0xFF000000U) #define FLEXIO_PARAM_TRIGGER_SHIFT (24U) #define FLEXIO_PARAM_TRIGGER(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_TRIGGER_SHIFT)) & FLEXIO_PARAM_TRIGGER_MASK) +/*! @} */ /*! @name CTRL - FlexIO Control Register */ +/*! @{ */ #define FLEXIO_CTRL_FLEXEN_MASK (0x1U) #define FLEXIO_CTRL_FLEXEN_SHIFT (0U) +/*! FLEXEN - FlexIO Enable + * 0b0..FlexIO module is disabled. + * 0b1..FlexIO module is enabled. + */ #define FLEXIO_CTRL_FLEXEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_FLEXEN_SHIFT)) & FLEXIO_CTRL_FLEXEN_MASK) #define FLEXIO_CTRL_SWRST_MASK (0x2U) #define FLEXIO_CTRL_SWRST_SHIFT (1U) +/*! SWRST - Software Reset + * 0b0..Software reset is disabled + * 0b1..Software reset is enabled, all FlexIO registers except the Control Register are reset. + */ #define FLEXIO_CTRL_SWRST(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_SWRST_SHIFT)) & FLEXIO_CTRL_SWRST_MASK) #define FLEXIO_CTRL_FASTACC_MASK (0x4U) #define FLEXIO_CTRL_FASTACC_SHIFT (2U) +/*! FASTACC - Fast Access + * 0b0..Configures for normal register accesses to FlexIO + * 0b1..Configures for fast register accesses to FlexIO + */ #define FLEXIO_CTRL_FASTACC(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_FASTACC_SHIFT)) & FLEXIO_CTRL_FASTACC_MASK) #define FLEXIO_CTRL_DBGE_MASK (0x40000000U) #define FLEXIO_CTRL_DBGE_SHIFT (30U) +/*! DBGE - Debug Enable + * 0b0..FlexIO is disabled in debug modes. + * 0b1..FlexIO is enabled in debug modes + */ #define FLEXIO_CTRL_DBGE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_DBGE_SHIFT)) & FLEXIO_CTRL_DBGE_MASK) #define FLEXIO_CTRL_DOZEN_MASK (0x80000000U) #define FLEXIO_CTRL_DOZEN_SHIFT (31U) +/*! DOZEN - Doze Enable + * 0b0..FlexIO enabled in Doze modes. + * 0b1..FlexIO disabled in Doze modes. + */ #define FLEXIO_CTRL_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_DOZEN_SHIFT)) & FLEXIO_CTRL_DOZEN_MASK) +/*! @} */ /*! @name PIN - Pin State Register */ +/*! @{ */ #define FLEXIO_PIN_PDI_MASK (0xFFFFFFFFU) #define FLEXIO_PIN_PDI_SHIFT (0U) #define FLEXIO_PIN_PDI(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PIN_PDI_SHIFT)) & FLEXIO_PIN_PDI_MASK) +/*! @} */ /*! @name SHIFTSTAT - Shifter Status Register */ +/*! @{ */ #define FLEXIO_SHIFTSTAT_SSF_MASK (0xFU) #define FLEXIO_SHIFTSTAT_SSF_SHIFT (0U) #define FLEXIO_SHIFTSTAT_SSF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSTAT_SSF_SHIFT)) & FLEXIO_SHIFTSTAT_SSF_MASK) +/*! @} */ /*! @name SHIFTERR - Shifter Error Register */ +/*! @{ */ #define FLEXIO_SHIFTERR_SEF_MASK (0xFU) #define FLEXIO_SHIFTERR_SEF_SHIFT (0U) #define FLEXIO_SHIFTERR_SEF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTERR_SEF_SHIFT)) & FLEXIO_SHIFTERR_SEF_MASK) +/*! @} */ /*! @name TIMSTAT - Timer Status Register */ +/*! @{ */ #define FLEXIO_TIMSTAT_TSF_MASK (0xFU) #define FLEXIO_TIMSTAT_TSF_SHIFT (0U) #define FLEXIO_TIMSTAT_TSF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMSTAT_TSF_SHIFT)) & FLEXIO_TIMSTAT_TSF_MASK) +/*! @} */ /*! @name SHIFTSIEN - Shifter Status Interrupt Enable */ +/*! @{ */ #define FLEXIO_SHIFTSIEN_SSIE_MASK (0xFU) #define FLEXIO_SHIFTSIEN_SSIE_SHIFT (0U) #define FLEXIO_SHIFTSIEN_SSIE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSIEN_SSIE_SHIFT)) & FLEXIO_SHIFTSIEN_SSIE_MASK) +/*! @} */ /*! @name SHIFTEIEN - Shifter Error Interrupt Enable */ +/*! @{ */ #define FLEXIO_SHIFTEIEN_SEIE_MASK (0xFU) #define FLEXIO_SHIFTEIEN_SEIE_SHIFT (0U) #define FLEXIO_SHIFTEIEN_SEIE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTEIEN_SEIE_SHIFT)) & FLEXIO_SHIFTEIEN_SEIE_MASK) +/*! @} */ /*! @name TIMIEN - Timer Interrupt Enable Register */ +/*! @{ */ #define FLEXIO_TIMIEN_TEIE_MASK (0xFU) #define FLEXIO_TIMIEN_TEIE_SHIFT (0U) #define FLEXIO_TIMIEN_TEIE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMIEN_TEIE_SHIFT)) & FLEXIO_TIMIEN_TEIE_MASK) +/*! @} */ /*! @name SHIFTSDEN - Shifter Status DMA Enable */ +/*! @{ */ #define FLEXIO_SHIFTSDEN_SSDE_MASK (0xFU) #define FLEXIO_SHIFTSDEN_SSDE_SHIFT (0U) #define FLEXIO_SHIFTSDEN_SSDE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSDEN_SSDE_SHIFT)) & FLEXIO_SHIFTSDEN_SSDE_MASK) +/*! @} */ /*! @name SHIFTSTATE - Shifter State Register */ +/*! @{ */ #define FLEXIO_SHIFTSTATE_STATE_MASK (0x7U) #define FLEXIO_SHIFTSTATE_STATE_SHIFT (0U) #define FLEXIO_SHIFTSTATE_STATE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSTATE_STATE_SHIFT)) & FLEXIO_SHIFTSTATE_STATE_MASK) +/*! @} */ /*! @name SHIFTCTL - Shifter Control N Register */ +/*! @{ */ #define FLEXIO_SHIFTCTL_SMOD_MASK (0x7U) #define FLEXIO_SHIFTCTL_SMOD_SHIFT (0U) +/*! SMOD - Shifter Mode + * 0b000..Disabled. + * 0b001..Receive mode. Captures the current Shifter content into the SHIFTBUF on expiration of the Timer. + * 0b010..Transmit mode. Load SHIFTBUF contents into the Shifter on expiration of the Timer. + * 0b011..Reserved. + * 0b100..Match Store mode. Shifter data is compared to SHIFTBUF content on expiration of the Timer. + * 0b101..Match Continuous mode. Shifter data is continuously compared to SHIFTBUF contents. + * 0b110..State mode. SHIFTBUF contents are used for storing programmable state attributes. + * 0b111..Logic mode. SHIFTBUF contents are used for implementing programmable logic look up table. + */ #define FLEXIO_SHIFTCTL_SMOD(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_SMOD_SHIFT)) & FLEXIO_SHIFTCTL_SMOD_MASK) #define FLEXIO_SHIFTCTL_PINPOL_MASK (0x80U) #define FLEXIO_SHIFTCTL_PINPOL_SHIFT (7U) +/*! PINPOL - Shifter Pin Polarity + * 0b0..Pin is active high + * 0b1..Pin is active low + */ #define FLEXIO_SHIFTCTL_PINPOL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINPOL_SHIFT)) & FLEXIO_SHIFTCTL_PINPOL_MASK) #define FLEXIO_SHIFTCTL_PINSEL_MASK (0x1F00U) #define FLEXIO_SHIFTCTL_PINSEL_SHIFT (8U) #define FLEXIO_SHIFTCTL_PINSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINSEL_SHIFT)) & FLEXIO_SHIFTCTL_PINSEL_MASK) #define FLEXIO_SHIFTCTL_PINCFG_MASK (0x30000U) #define FLEXIO_SHIFTCTL_PINCFG_SHIFT (16U) +/*! PINCFG - Shifter Pin Configuration + * 0b00..Shifter pin output disabled + * 0b01..Shifter pin open drain or bidirectional output enable + * 0b10..Shifter pin bidirectional output data + * 0b11..Shifter pin output + */ #define FLEXIO_SHIFTCTL_PINCFG(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINCFG_SHIFT)) & FLEXIO_SHIFTCTL_PINCFG_MASK) #define FLEXIO_SHIFTCTL_TIMPOL_MASK (0x800000U) #define FLEXIO_SHIFTCTL_TIMPOL_SHIFT (23U) +/*! TIMPOL - Timer Polarity + * 0b0..Shift on posedge of Shift clock + * 0b1..Shift on negedge of Shift clock + */ #define FLEXIO_SHIFTCTL_TIMPOL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_TIMPOL_SHIFT)) & FLEXIO_SHIFTCTL_TIMPOL_MASK) #define FLEXIO_SHIFTCTL_TIMSEL_MASK (0x3000000U) #define FLEXIO_SHIFTCTL_TIMSEL_SHIFT (24U) #define FLEXIO_SHIFTCTL_TIMSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_TIMSEL_SHIFT)) & FLEXIO_SHIFTCTL_TIMSEL_MASK) +/*! @} */ /* The count of FLEXIO_SHIFTCTL */ #define FLEXIO_SHIFTCTL_COUNT (4U) /*! @name SHIFTCFG - Shifter Configuration N Register */ +/*! @{ */ #define FLEXIO_SHIFTCFG_SSTART_MASK (0x3U) #define FLEXIO_SHIFTCFG_SSTART_SHIFT (0U) +/*! SSTART - Shifter Start bit + * 0b00..Start bit disabled for transmitter/receiver/match store, transmitter loads data on enable + * 0b01..Start bit disabled for transmitter/receiver/match store, transmitter loads data on first shift + * 0b10..Transmitter outputs start bit value 0 before loading data on first shift, receiver/match store sets error flag if start bit is not 0 + * 0b11..Transmitter outputs start bit value 1 before loading data on first shift, receiver/match store sets error flag if start bit is not 1 + */ #define FLEXIO_SHIFTCFG_SSTART(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_SSTART_SHIFT)) & FLEXIO_SHIFTCFG_SSTART_MASK) #define FLEXIO_SHIFTCFG_SSTOP_MASK (0x30U) #define FLEXIO_SHIFTCFG_SSTOP_SHIFT (4U) +/*! SSTOP - Shifter Stop bit + * 0b00..Stop bit disabled for transmitter/receiver/match store + * 0b01..Reserved for transmitter/receiver/match store + * 0b10..Transmitter outputs stop bit value 0 on store, receiver/match store sets error flag if stop bit is not 0 + * 0b11..Transmitter outputs stop bit value 1 on store, receiver/match store sets error flag if stop bit is not 1 + */ #define FLEXIO_SHIFTCFG_SSTOP(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_SSTOP_SHIFT)) & FLEXIO_SHIFTCFG_SSTOP_MASK) #define FLEXIO_SHIFTCFG_INSRC_MASK (0x100U) #define FLEXIO_SHIFTCFG_INSRC_SHIFT (8U) +/*! INSRC - Input Source + * 0b0..Pin + * 0b1..Shifter N+1 Output + */ #define FLEXIO_SHIFTCFG_INSRC(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_INSRC_SHIFT)) & FLEXIO_SHIFTCFG_INSRC_MASK) #define FLEXIO_SHIFTCFG_PWIDTH_MASK (0x1F0000U) #define FLEXIO_SHIFTCFG_PWIDTH_SHIFT (16U) #define FLEXIO_SHIFTCFG_PWIDTH(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_PWIDTH_SHIFT)) & FLEXIO_SHIFTCFG_PWIDTH_MASK) +/*! @} */ /* The count of FLEXIO_SHIFTCFG */ #define FLEXIO_SHIFTCFG_COUNT (4U) /*! @name SHIFTBUF - Shifter Buffer N Register */ +/*! @{ */ #define FLEXIO_SHIFTBUF_SHIFTBUF_MASK (0xFFFFFFFFU) #define FLEXIO_SHIFTBUF_SHIFTBUF_SHIFT (0U) #define FLEXIO_SHIFTBUF_SHIFTBUF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUF_SHIFTBUF_SHIFT)) & FLEXIO_SHIFTBUF_SHIFTBUF_MASK) +/*! @} */ /* The count of FLEXIO_SHIFTBUF */ #define FLEXIO_SHIFTBUF_COUNT (4U) /*! @name SHIFTBUFBIS - Shifter Buffer N Bit Swapped Register */ +/*! @{ */ #define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_MASK (0xFFFFFFFFU) #define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_SHIFT (0U) #define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_SHIFT)) & FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_MASK) +/*! @} */ /* The count of FLEXIO_SHIFTBUFBIS */ #define FLEXIO_SHIFTBUFBIS_COUNT (4U) /*! @name SHIFTBUFBYS - Shifter Buffer N Byte Swapped Register */ +/*! @{ */ #define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_MASK (0xFFFFFFFFU) #define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_SHIFT (0U) #define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_SHIFT)) & FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_MASK) +/*! @} */ /* The count of FLEXIO_SHIFTBUFBYS */ #define FLEXIO_SHIFTBUFBYS_COUNT (4U) /*! @name SHIFTBUFBBS - Shifter Buffer N Bit Byte Swapped Register */ +/*! @{ */ #define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_MASK (0xFFFFFFFFU) #define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_SHIFT (0U) #define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_SHIFT)) & FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_MASK) +/*! @} */ /* The count of FLEXIO_SHIFTBUFBBS */ #define FLEXIO_SHIFTBUFBBS_COUNT (4U) /*! @name TIMCTL - Timer Control N Register */ +/*! @{ */ #define FLEXIO_TIMCTL_TIMOD_MASK (0x3U) #define FLEXIO_TIMCTL_TIMOD_SHIFT (0U) +/*! TIMOD - Timer Mode + * 0b00..Timer Disabled. + * 0b01..Dual 8-bit counters baud mode. + * 0b10..Dual 8-bit counters PWM high mode. + * 0b11..Single 16-bit counter mode. + */ #define FLEXIO_TIMCTL_TIMOD(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TIMOD_SHIFT)) & FLEXIO_TIMCTL_TIMOD_MASK) #define FLEXIO_TIMCTL_PINPOL_MASK (0x80U) #define FLEXIO_TIMCTL_PINPOL_SHIFT (7U) +/*! PINPOL - Timer Pin Polarity + * 0b0..Pin is active high + * 0b1..Pin is active low + */ #define FLEXIO_TIMCTL_PINPOL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINPOL_SHIFT)) & FLEXIO_TIMCTL_PINPOL_MASK) #define FLEXIO_TIMCTL_PINSEL_MASK (0x1F00U) #define FLEXIO_TIMCTL_PINSEL_SHIFT (8U) #define FLEXIO_TIMCTL_PINSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINSEL_SHIFT)) & FLEXIO_TIMCTL_PINSEL_MASK) #define FLEXIO_TIMCTL_PINCFG_MASK (0x30000U) #define FLEXIO_TIMCTL_PINCFG_SHIFT (16U) +/*! PINCFG - Timer Pin Configuration + * 0b00..Timer pin output disabled + * 0b01..Timer pin open drain or bidirectional output enable + * 0b10..Timer pin bidirectional output data + * 0b11..Timer pin output + */ #define FLEXIO_TIMCTL_PINCFG(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINCFG_SHIFT)) & FLEXIO_TIMCTL_PINCFG_MASK) #define FLEXIO_TIMCTL_TRGSRC_MASK (0x400000U) #define FLEXIO_TIMCTL_TRGSRC_SHIFT (22U) +/*! TRGSRC - Trigger Source + * 0b0..External trigger selected + * 0b1..Internal trigger selected + */ #define FLEXIO_TIMCTL_TRGSRC(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGSRC_SHIFT)) & FLEXIO_TIMCTL_TRGSRC_MASK) #define FLEXIO_TIMCTL_TRGPOL_MASK (0x800000U) #define FLEXIO_TIMCTL_TRGPOL_SHIFT (23U) +/*! TRGPOL - Trigger Polarity + * 0b0..Trigger active high + * 0b1..Trigger active low + */ #define FLEXIO_TIMCTL_TRGPOL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGPOL_SHIFT)) & FLEXIO_TIMCTL_TRGPOL_MASK) #define FLEXIO_TIMCTL_TRGSEL_MASK (0x3F000000U) #define FLEXIO_TIMCTL_TRGSEL_SHIFT (24U) #define FLEXIO_TIMCTL_TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGSEL_SHIFT)) & FLEXIO_TIMCTL_TRGSEL_MASK) +/*! @} */ /* The count of FLEXIO_TIMCTL */ #define FLEXIO_TIMCTL_COUNT (4U) /*! @name TIMCFG - Timer Configuration N Register */ +/*! @{ */ #define FLEXIO_TIMCFG_TSTART_MASK (0x2U) #define FLEXIO_TIMCFG_TSTART_SHIFT (1U) +/*! TSTART - Timer Start Bit + * 0b0..Start bit disabled + * 0b1..Start bit enabled + */ #define FLEXIO_TIMCFG_TSTART(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TSTART_SHIFT)) & FLEXIO_TIMCFG_TSTART_MASK) #define FLEXIO_TIMCFG_TSTOP_MASK (0x30U) #define FLEXIO_TIMCFG_TSTOP_SHIFT (4U) +/*! TSTOP - Timer Stop Bit + * 0b00..Stop bit disabled + * 0b01..Stop bit is enabled on timer compare + * 0b10..Stop bit is enabled on timer disable + * 0b11..Stop bit is enabled on timer compare and timer disable + */ #define FLEXIO_TIMCFG_TSTOP(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TSTOP_SHIFT)) & FLEXIO_TIMCFG_TSTOP_MASK) #define FLEXIO_TIMCFG_TIMENA_MASK (0x700U) #define FLEXIO_TIMCFG_TIMENA_SHIFT (8U) +/*! TIMENA - Timer Enable + * 0b000..Timer always enabled + * 0b001..Timer enabled on Timer N-1 enable + * 0b010..Timer enabled on Trigger high + * 0b011..Timer enabled on Trigger high and Pin high + * 0b100..Timer enabled on Pin rising edge + * 0b101..Timer enabled on Pin rising edge and Trigger high + * 0b110..Timer enabled on Trigger rising edge + * 0b111..Timer enabled on Trigger rising or falling edge + */ #define FLEXIO_TIMCFG_TIMENA(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMENA_SHIFT)) & FLEXIO_TIMCFG_TIMENA_MASK) #define FLEXIO_TIMCFG_TIMDIS_MASK (0x7000U) #define FLEXIO_TIMCFG_TIMDIS_SHIFT (12U) +/*! TIMDIS - Timer Disable + * 0b000..Timer never disabled + * 0b001..Timer disabled on Timer N-1 disable + * 0b010..Timer disabled on Timer compare (upper 8-bits match and decrement) + * 0b011..Timer disabled on Timer compare (upper 8-bits match and decrement) and Trigger Low + * 0b100..Timer disabled on Pin rising or falling edge + * 0b101..Timer disabled on Pin rising or falling edge provided Trigger is high + * 0b110..Timer disabled on Trigger falling edge + * 0b111..Reserved + */ #define FLEXIO_TIMCFG_TIMDIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMDIS_SHIFT)) & FLEXIO_TIMCFG_TIMDIS_MASK) #define FLEXIO_TIMCFG_TIMRST_MASK (0x70000U) #define FLEXIO_TIMCFG_TIMRST_SHIFT (16U) +/*! TIMRST - Timer Reset + * 0b000..Timer never reset + * 0b001..Reserved + * 0b010..Timer reset on Timer Pin equal to Timer Output + * 0b011..Timer reset on Timer Trigger equal to Timer Output + * 0b100..Timer reset on Timer Pin rising edge + * 0b101..Reserved + * 0b110..Timer reset on Trigger rising edge + * 0b111..Timer reset on Trigger rising or falling edge + */ #define FLEXIO_TIMCFG_TIMRST(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMRST_SHIFT)) & FLEXIO_TIMCFG_TIMRST_MASK) #define FLEXIO_TIMCFG_TIMDEC_MASK (0x300000U) #define FLEXIO_TIMCFG_TIMDEC_SHIFT (20U) +/*! TIMDEC - Timer Decrement + * 0b00..Decrement counter on FlexIO clock, Shift clock equals Timer output. + * 0b01..Decrement counter on Trigger input (both edges), Shift clock equals Timer output. + * 0b10..Decrement counter on Pin input (both edges), Shift clock equals Pin input. + * 0b11..Decrement counter on Trigger input (both edges), Shift clock equals Trigger input. + */ #define FLEXIO_TIMCFG_TIMDEC(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMDEC_SHIFT)) & FLEXIO_TIMCFG_TIMDEC_MASK) #define FLEXIO_TIMCFG_TIMOUT_MASK (0x3000000U) #define FLEXIO_TIMCFG_TIMOUT_SHIFT (24U) +/*! TIMOUT - Timer Output + * 0b00..Timer output is logic one when enabled and is not affected by timer reset + * 0b01..Timer output is logic zero when enabled and is not affected by timer reset + * 0b10..Timer output is logic one when enabled and on timer reset + * 0b11..Timer output is logic zero when enabled and on timer reset + */ #define FLEXIO_TIMCFG_TIMOUT(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMOUT_SHIFT)) & FLEXIO_TIMCFG_TIMOUT_MASK) +/*! @} */ /* The count of FLEXIO_TIMCFG */ #define FLEXIO_TIMCFG_COUNT (4U) /*! @name TIMCMP - Timer Compare N Register */ +/*! @{ */ #define FLEXIO_TIMCMP_CMP_MASK (0xFFFFU) #define FLEXIO_TIMCMP_CMP_SHIFT (0U) #define FLEXIO_TIMCMP_CMP(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCMP_CMP_SHIFT)) & FLEXIO_TIMCMP_CMP_MASK) +/*! @} */ /* The count of FLEXIO_TIMCMP */ #define FLEXIO_TIMCMP_COUNT (4U) /*! @name SHIFTBUFNBS - Shifter Buffer N Nibble Byte Swapped Register */ +/*! @{ */ #define FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_MASK (0xFFFFFFFFU) #define FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_SHIFT (0U) #define FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_SHIFT)) & FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_MASK) +/*! @} */ /* The count of FLEXIO_SHIFTBUFNBS */ #define FLEXIO_SHIFTBUFNBS_COUNT (4U) /*! @name SHIFTBUFHWS - Shifter Buffer N Half Word Swapped Register */ +/*! @{ */ #define FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_MASK (0xFFFFFFFFU) #define FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_SHIFT (0U) #define FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_SHIFT)) & FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_MASK) +/*! @} */ /* The count of FLEXIO_SHIFTBUFHWS */ #define FLEXIO_SHIFTBUFHWS_COUNT (4U) /*! @name SHIFTBUFNIS - Shifter Buffer N Nibble Swapped Register */ +/*! @{ */ #define FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_MASK (0xFFFFFFFFU) #define FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_SHIFT (0U) #define FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_SHIFT)) & FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_MASK) +/*! @} */ /* The count of FLEXIO_SHIFTBUFNIS */ #define FLEXIO_SHIFTBUFNIS_COUNT (4U) @@ -9835,9 +15071,7 @@ typedef struct { /** FLEXRAM - Register Layout Typedef */ typedef struct { __IO uint32_t TCM_CTRL; /**< TCM CRTL Register, offset: 0x0 */ - __IO uint32_t OCRAM_MAGIC_ADDR; /**< OCRAM Magic Address Register, offset: 0x4 */ - __IO uint32_t DTCM_MAGIC_ADDR; /**< DTCM Magic Address Register, offset: 0x8 */ - __IO uint32_t ITCM_MAGIC_ADDR; /**< ITCM Magic Address Register, offset: 0xC */ + uint8_t RESERVED_0[12]; __IO uint32_t INT_STATUS; /**< Interrupt Status Register, offset: 0x10 */ __IO uint32_t INT_STAT_EN; /**< Interrupt Status Enable Register, offset: 0x14 */ __IO uint32_t INT_SIG_EN; /**< Interrupt Enable Register, offset: 0x18 */ @@ -9853,120 +15087,100 @@ typedef struct { */ /*! @name TCM_CTRL - TCM CRTL Register */ +/*! @{ */ #define FLEXRAM_TCM_CTRL_TCM_WWAIT_EN_MASK (0x1U) #define FLEXRAM_TCM_CTRL_TCM_WWAIT_EN_SHIFT (0U) +/*! TCM_WWAIT_EN - TCM Write Wait Mode Enable + * 0b0..TCM write fast mode: Write RAM accesses are expected to be finished in 1-cycle. + * 0b1..TCM write wait mode: Write RAM accesses are expected to be finished in 2-cycles. + */ #define FLEXRAM_TCM_CTRL_TCM_WWAIT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_TCM_CTRL_TCM_WWAIT_EN_SHIFT)) & FLEXRAM_TCM_CTRL_TCM_WWAIT_EN_MASK) #define FLEXRAM_TCM_CTRL_TCM_RWAIT_EN_MASK (0x2U) #define FLEXRAM_TCM_CTRL_TCM_RWAIT_EN_SHIFT (1U) +/*! TCM_RWAIT_EN - TCM Read Wait Mode Enable + * 0b0..TCM read fast mode: Read RAM accesses are expected to be finished in 1-cycle. + * 0b1..TCM read wait mode: Read RAM accesses are expected to be finished in 2-cycles. + */ #define FLEXRAM_TCM_CTRL_TCM_RWAIT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_TCM_CTRL_TCM_RWAIT_EN_SHIFT)) & FLEXRAM_TCM_CTRL_TCM_RWAIT_EN_MASK) #define FLEXRAM_TCM_CTRL_FORCE_CLK_ON_MASK (0x4U) #define FLEXRAM_TCM_CTRL_FORCE_CLK_ON_SHIFT (2U) #define FLEXRAM_TCM_CTRL_FORCE_CLK_ON(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_TCM_CTRL_FORCE_CLK_ON_SHIFT)) & FLEXRAM_TCM_CTRL_FORCE_CLK_ON_MASK) -#define FLEXRAM_TCM_CTRL_Reserved_MASK (0xFFFFFFF8U) -#define FLEXRAM_TCM_CTRL_Reserved_SHIFT (3U) -#define FLEXRAM_TCM_CTRL_Reserved(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_TCM_CTRL_Reserved_SHIFT)) & FLEXRAM_TCM_CTRL_Reserved_MASK) - -/*! @name OCRAM_MAGIC_ADDR - OCRAM Magic Address Register */ -#define FLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_WR_RD_SEL_MASK (0x1U) -#define FLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_WR_RD_SEL_SHIFT (0U) -#define FLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_WR_RD_SEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_WR_RD_SEL_SHIFT)) & FLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_WR_RD_SEL_MASK) -#define FLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_MAGIC_ADDR_MASK (0x1FFFEU) -#define FLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_MAGIC_ADDR_SHIFT (1U) -#define FLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_MAGIC_ADDR(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_MAGIC_ADDR_SHIFT)) & FLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_MAGIC_ADDR_MASK) -#define FLEXRAM_OCRAM_MAGIC_ADDR_Reserved_MASK (0xFFFE0000U) -#define FLEXRAM_OCRAM_MAGIC_ADDR_Reserved_SHIFT (17U) -#define FLEXRAM_OCRAM_MAGIC_ADDR_Reserved(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_OCRAM_MAGIC_ADDR_Reserved_SHIFT)) & FLEXRAM_OCRAM_MAGIC_ADDR_Reserved_MASK) - -/*! @name DTCM_MAGIC_ADDR - DTCM Magic Address Register */ -#define FLEXRAM_DTCM_MAGIC_ADDR_DTCM_WR_RD_SEL_MASK (0x1U) -#define FLEXRAM_DTCM_MAGIC_ADDR_DTCM_WR_RD_SEL_SHIFT (0U) -#define FLEXRAM_DTCM_MAGIC_ADDR_DTCM_WR_RD_SEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_DTCM_MAGIC_ADDR_DTCM_WR_RD_SEL_SHIFT)) & FLEXRAM_DTCM_MAGIC_ADDR_DTCM_WR_RD_SEL_MASK) -#define FLEXRAM_DTCM_MAGIC_ADDR_DTCM_MAGIC_ADDR_MASK (0x1FFFEU) -#define FLEXRAM_DTCM_MAGIC_ADDR_DTCM_MAGIC_ADDR_SHIFT (1U) -#define FLEXRAM_DTCM_MAGIC_ADDR_DTCM_MAGIC_ADDR(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_DTCM_MAGIC_ADDR_DTCM_MAGIC_ADDR_SHIFT)) & FLEXRAM_DTCM_MAGIC_ADDR_DTCM_MAGIC_ADDR_MASK) -#define FLEXRAM_DTCM_MAGIC_ADDR_Reserved_MASK (0xFFFE0000U) -#define FLEXRAM_DTCM_MAGIC_ADDR_Reserved_SHIFT (17U) -#define FLEXRAM_DTCM_MAGIC_ADDR_Reserved(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_DTCM_MAGIC_ADDR_Reserved_SHIFT)) & FLEXRAM_DTCM_MAGIC_ADDR_Reserved_MASK) - -/*! @name ITCM_MAGIC_ADDR - ITCM Magic Address Register */ -#define FLEXRAM_ITCM_MAGIC_ADDR_ITCM_WR_RD_SEL_MASK (0x1U) -#define FLEXRAM_ITCM_MAGIC_ADDR_ITCM_WR_RD_SEL_SHIFT (0U) -#define FLEXRAM_ITCM_MAGIC_ADDR_ITCM_WR_RD_SEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_ITCM_MAGIC_ADDR_ITCM_WR_RD_SEL_SHIFT)) & FLEXRAM_ITCM_MAGIC_ADDR_ITCM_WR_RD_SEL_MASK) -#define FLEXRAM_ITCM_MAGIC_ADDR_ITCM_MAGIC_ADDR_MASK (0x1FFFEU) -#define FLEXRAM_ITCM_MAGIC_ADDR_ITCM_MAGIC_ADDR_SHIFT (1U) -#define FLEXRAM_ITCM_MAGIC_ADDR_ITCM_MAGIC_ADDR(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_ITCM_MAGIC_ADDR_ITCM_MAGIC_ADDR_SHIFT)) & FLEXRAM_ITCM_MAGIC_ADDR_ITCM_MAGIC_ADDR_MASK) -#define FLEXRAM_ITCM_MAGIC_ADDR_Reserved_MASK (0xFFFE0000U) -#define FLEXRAM_ITCM_MAGIC_ADDR_Reserved_SHIFT (17U) -#define FLEXRAM_ITCM_MAGIC_ADDR_Reserved(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_ITCM_MAGIC_ADDR_Reserved_SHIFT)) & FLEXRAM_ITCM_MAGIC_ADDR_Reserved_MASK) +/*! @} */ /*! @name INT_STATUS - Interrupt Status Register */ -#define FLEXRAM_INT_STATUS_ITCM_MAM_STATUS_MASK (0x1U) -#define FLEXRAM_INT_STATUS_ITCM_MAM_STATUS_SHIFT (0U) -#define FLEXRAM_INT_STATUS_ITCM_MAM_STATUS(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_ITCM_MAM_STATUS_SHIFT)) & FLEXRAM_INT_STATUS_ITCM_MAM_STATUS_MASK) -#define FLEXRAM_INT_STATUS_DTCM_MAM_STATUS_MASK (0x2U) -#define FLEXRAM_INT_STATUS_DTCM_MAM_STATUS_SHIFT (1U) -#define FLEXRAM_INT_STATUS_DTCM_MAM_STATUS(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_DTCM_MAM_STATUS_SHIFT)) & FLEXRAM_INT_STATUS_DTCM_MAM_STATUS_MASK) -#define FLEXRAM_INT_STATUS_OCRAM_MAM_STATUS_MASK (0x4U) -#define FLEXRAM_INT_STATUS_OCRAM_MAM_STATUS_SHIFT (2U) -#define FLEXRAM_INT_STATUS_OCRAM_MAM_STATUS(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_OCRAM_MAM_STATUS_SHIFT)) & FLEXRAM_INT_STATUS_OCRAM_MAM_STATUS_MASK) +/*! @{ */ #define FLEXRAM_INT_STATUS_ITCM_ERR_STATUS_MASK (0x8U) #define FLEXRAM_INT_STATUS_ITCM_ERR_STATUS_SHIFT (3U) +/*! ITCM_ERR_STATUS - ITCM Access Error Status + * 0b0..ITCM access error does not happen + * 0b1..ITCM access error happens. + */ #define FLEXRAM_INT_STATUS_ITCM_ERR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_ITCM_ERR_STATUS_SHIFT)) & FLEXRAM_INT_STATUS_ITCM_ERR_STATUS_MASK) #define FLEXRAM_INT_STATUS_DTCM_ERR_STATUS_MASK (0x10U) #define FLEXRAM_INT_STATUS_DTCM_ERR_STATUS_SHIFT (4U) +/*! DTCM_ERR_STATUS - DTCM Access Error Status + * 0b0..DTCM access error does not happen + * 0b1..DTCM access error happens. + */ #define FLEXRAM_INT_STATUS_DTCM_ERR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_DTCM_ERR_STATUS_SHIFT)) & FLEXRAM_INT_STATUS_DTCM_ERR_STATUS_MASK) #define FLEXRAM_INT_STATUS_OCRAM_ERR_STATUS_MASK (0x20U) #define FLEXRAM_INT_STATUS_OCRAM_ERR_STATUS_SHIFT (5U) +/*! OCRAM_ERR_STATUS - OCRAM Access Error Status + * 0b0..OCRAM access error does not happen + * 0b1..OCRAM access error happens. + */ #define FLEXRAM_INT_STATUS_OCRAM_ERR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_OCRAM_ERR_STATUS_SHIFT)) & FLEXRAM_INT_STATUS_OCRAM_ERR_STATUS_MASK) -#define FLEXRAM_INT_STATUS_Reserved_MASK (0xFFFFFFC0U) -#define FLEXRAM_INT_STATUS_Reserved_SHIFT (6U) -#define FLEXRAM_INT_STATUS_Reserved(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_Reserved_SHIFT)) & FLEXRAM_INT_STATUS_Reserved_MASK) +/*! @} */ /*! @name INT_STAT_EN - Interrupt Status Enable Register */ -#define FLEXRAM_INT_STAT_EN_ITCM_MAM_STAT_EN_MASK (0x1U) -#define FLEXRAM_INT_STAT_EN_ITCM_MAM_STAT_EN_SHIFT (0U) -#define FLEXRAM_INT_STAT_EN_ITCM_MAM_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_ITCM_MAM_STAT_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_ITCM_MAM_STAT_EN_MASK) -#define FLEXRAM_INT_STAT_EN_DTCM_MAM_STAT_EN_MASK (0x2U) -#define FLEXRAM_INT_STAT_EN_DTCM_MAM_STAT_EN_SHIFT (1U) -#define FLEXRAM_INT_STAT_EN_DTCM_MAM_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_DTCM_MAM_STAT_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_DTCM_MAM_STAT_EN_MASK) -#define FLEXRAM_INT_STAT_EN_OCRAM_MAM_STAT_EN_MASK (0x4U) -#define FLEXRAM_INT_STAT_EN_OCRAM_MAM_STAT_EN_SHIFT (2U) -#define FLEXRAM_INT_STAT_EN_OCRAM_MAM_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_OCRAM_MAM_STAT_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_OCRAM_MAM_STAT_EN_MASK) +/*! @{ */ #define FLEXRAM_INT_STAT_EN_ITCM_ERR_STAT_EN_MASK (0x8U) #define FLEXRAM_INT_STAT_EN_ITCM_ERR_STAT_EN_SHIFT (3U) +/*! ITCM_ERR_STAT_EN - ITCM Access Error Status Enable + * 0b0..Masked + * 0b1..Enabled + */ #define FLEXRAM_INT_STAT_EN_ITCM_ERR_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_ITCM_ERR_STAT_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_ITCM_ERR_STAT_EN_MASK) #define FLEXRAM_INT_STAT_EN_DTCM_ERR_STAT_EN_MASK (0x10U) #define FLEXRAM_INT_STAT_EN_DTCM_ERR_STAT_EN_SHIFT (4U) +/*! DTCM_ERR_STAT_EN - DTCM Access Error Status Enable + * 0b0..Masked + * 0b1..Enabled + */ #define FLEXRAM_INT_STAT_EN_DTCM_ERR_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_DTCM_ERR_STAT_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_DTCM_ERR_STAT_EN_MASK) #define FLEXRAM_INT_STAT_EN_OCRAM_ERR_STAT_EN_MASK (0x20U) #define FLEXRAM_INT_STAT_EN_OCRAM_ERR_STAT_EN_SHIFT (5U) +/*! OCRAM_ERR_STAT_EN - OCRAM Access Error Status Enable + * 0b0..Masked + * 0b1..Enabled + */ #define FLEXRAM_INT_STAT_EN_OCRAM_ERR_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_OCRAM_ERR_STAT_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_OCRAM_ERR_STAT_EN_MASK) -#define FLEXRAM_INT_STAT_EN_Reserved_MASK (0xFFFFFFC0U) -#define FLEXRAM_INT_STAT_EN_Reserved_SHIFT (6U) -#define FLEXRAM_INT_STAT_EN_Reserved(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_Reserved_SHIFT)) & FLEXRAM_INT_STAT_EN_Reserved_MASK) +/*! @} */ /*! @name INT_SIG_EN - Interrupt Enable Register */ -#define FLEXRAM_INT_SIG_EN_ITCM_MAM_SIG_EN_MASK (0x1U) -#define FLEXRAM_INT_SIG_EN_ITCM_MAM_SIG_EN_SHIFT (0U) -#define FLEXRAM_INT_SIG_EN_ITCM_MAM_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_ITCM_MAM_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_ITCM_MAM_SIG_EN_MASK) -#define FLEXRAM_INT_SIG_EN_DTCM_MAM_SIG_EN_MASK (0x2U) -#define FLEXRAM_INT_SIG_EN_DTCM_MAM_SIG_EN_SHIFT (1U) -#define FLEXRAM_INT_SIG_EN_DTCM_MAM_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_DTCM_MAM_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_DTCM_MAM_SIG_EN_MASK) -#define FLEXRAM_INT_SIG_EN_OCRAM_MAM_SIG_EN_MASK (0x4U) -#define FLEXRAM_INT_SIG_EN_OCRAM_MAM_SIG_EN_SHIFT (2U) -#define FLEXRAM_INT_SIG_EN_OCRAM_MAM_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_OCRAM_MAM_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_OCRAM_MAM_SIG_EN_MASK) +/*! @{ */ #define FLEXRAM_INT_SIG_EN_ITCM_ERR_SIG_EN_MASK (0x8U) #define FLEXRAM_INT_SIG_EN_ITCM_ERR_SIG_EN_SHIFT (3U) +/*! ITCM_ERR_SIG_EN - ITCM Access Error Interrupt Enable + * 0b0..Masked + * 0b1..Enabled + */ #define FLEXRAM_INT_SIG_EN_ITCM_ERR_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_ITCM_ERR_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_ITCM_ERR_SIG_EN_MASK) #define FLEXRAM_INT_SIG_EN_DTCM_ERR_SIG_EN_MASK (0x10U) #define FLEXRAM_INT_SIG_EN_DTCM_ERR_SIG_EN_SHIFT (4U) +/*! DTCM_ERR_SIG_EN - DTCM Access Error Interrupt Enable + * 0b0..Masked + * 0b1..Enabled + */ #define FLEXRAM_INT_SIG_EN_DTCM_ERR_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_DTCM_ERR_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_DTCM_ERR_SIG_EN_MASK) #define FLEXRAM_INT_SIG_EN_OCRAM_ERR_SIG_EN_MASK (0x20U) #define FLEXRAM_INT_SIG_EN_OCRAM_ERR_SIG_EN_SHIFT (5U) +/*! OCRAM_ERR_SIG_EN - OCRAM Access Error Interrupt Enable + * 0b0..Masked + * 0b1..Enabled + */ #define FLEXRAM_INT_SIG_EN_OCRAM_ERR_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_OCRAM_ERR_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_OCRAM_ERR_SIG_EN_MASK) -#define FLEXRAM_INT_SIG_EN_Reserved_MASK (0xFFFFFFC0U) -#define FLEXRAM_INT_SIG_EN_Reserved_SHIFT (6U) -#define FLEXRAM_INT_SIG_EN_Reserved(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_Reserved_SHIFT)) & FLEXRAM_INT_SIG_EN_Reserved_MASK) +/*! @} */ /*! @@ -10049,6 +15263,7 @@ typedef struct { */ /*! @name MCR0 - Module Control Register 0 */ +/*! @{ */ #define FLEXSPI_MCR0_SWRESET_MASK (0x1U) #define FLEXSPI_MCR0_SWRESET_SHIFT (0U) #define FLEXSPI_MCR0_SWRESET(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_SWRESET_SHIFT)) & FLEXSPI_MCR0_SWRESET_MASK) @@ -10057,24 +15272,54 @@ typedef struct { #define FLEXSPI_MCR0_MDIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_MDIS_SHIFT)) & FLEXSPI_MCR0_MDIS_MASK) #define FLEXSPI_MCR0_RXCLKSRC_MASK (0x30U) #define FLEXSPI_MCR0_RXCLKSRC_SHIFT (4U) +/*! RXCLKSRC - Sample Clock source selection for Flash Reading + * 0b00..Dummy Read strobe generated by FlexSPI Controller and loopback internally. + * 0b01..Dummy Read strobe generated by FlexSPI Controller and loopback from DQS pad. + * 0b10..Reserved + * 0b11..Flash provided Read strobe and input from DQS pad + */ #define FLEXSPI_MCR0_RXCLKSRC(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_RXCLKSRC_SHIFT)) & FLEXSPI_MCR0_RXCLKSRC_MASK) #define FLEXSPI_MCR0_ARDFEN_MASK (0x40U) #define FLEXSPI_MCR0_ARDFEN_SHIFT (6U) +/*! ARDFEN - Enable AHB bus Read Access to IP RX FIFO. + * 0b0..IP RX FIFO should be read by IP Bus. AHB Bus read access to IP RX FIFO memory space will get bus error response. + * 0b1..IP RX FIFO should be read by AHB Bus. IP Bus read access to IP RX FIFO memory space will always return data zero but no bus error response. + */ #define FLEXSPI_MCR0_ARDFEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_ARDFEN_SHIFT)) & FLEXSPI_MCR0_ARDFEN_MASK) #define FLEXSPI_MCR0_ATDFEN_MASK (0x80U) #define FLEXSPI_MCR0_ATDFEN_SHIFT (7U) +/*! ATDFEN - Enable AHB bus Write Access to IP TX FIFO. + * 0b0..IP TX FIFO should be written by IP Bus. AHB Bus write access to IP TX FIFO memory space will get bus error response. + * 0b1..IP TX FIFO should be written by AHB Bus. IP Bus write access to IP TX FIFO memory space will be ignored but no bus error response. + */ #define FLEXSPI_MCR0_ATDFEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_ATDFEN_SHIFT)) & FLEXSPI_MCR0_ATDFEN_MASK) #define FLEXSPI_MCR0_HSEN_MASK (0x800U) #define FLEXSPI_MCR0_HSEN_SHIFT (11U) +/*! HSEN - Half Speed Serial Flash access Enable. + * 0b0..Disable divide by 2 of serial flash clock for half speed commands. + * 0b1..Enable divide by 2 of serial flash clock for half speed commands. + */ #define FLEXSPI_MCR0_HSEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_HSEN_SHIFT)) & FLEXSPI_MCR0_HSEN_MASK) #define FLEXSPI_MCR0_DOZEEN_MASK (0x1000U) #define FLEXSPI_MCR0_DOZEEN_SHIFT (12U) +/*! DOZEEN - Doze mode enable bit + * 0b0..Doze mode support disabled. AHB clock and serial clock will not be gated off when there is doze mode request from system. + * 0b1..Doze mode support enabled. AHB clock and serial clock will be gated off when there is doze mode request from system. + */ #define FLEXSPI_MCR0_DOZEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_DOZEEN_SHIFT)) & FLEXSPI_MCR0_DOZEEN_MASK) #define FLEXSPI_MCR0_COMBINATIONEN_MASK (0x2000U) #define FLEXSPI_MCR0_COMBINATIONEN_SHIFT (13U) +/*! COMBINATIONEN - This bit is to support Flash Octal mode access by combining Port A and B Data pins (SIOA[3:0] and SIOB[3:0]). + * 0b0..Disable. + * 0b1..Enable. + */ #define FLEXSPI_MCR0_COMBINATIONEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_COMBINATIONEN_SHIFT)) & FLEXSPI_MCR0_COMBINATIONEN_MASK) #define FLEXSPI_MCR0_SCKFREERUNEN_MASK (0x4000U) #define FLEXSPI_MCR0_SCKFREERUNEN_SHIFT (14U) +/*! SCKFREERUNEN - This bit is used to force SCK output free-running. For FPGA applications, external device may use SCK clock as reference clock to its internal PLL. If SCK free-running is enabled, data sampling with loopback clock from SCK pad is not supported (MCR0[RXCLKSRC]=2). + * 0b0..Disable. + * 0b1..Enable. + */ #define FLEXSPI_MCR0_SCKFREERUNEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_SCKFREERUNEN_SHIFT)) & FLEXSPI_MCR0_SCKFREERUNEN_MASK) #define FLEXSPI_MCR0_IPGRANTWAIT_MASK (0xFF0000U) #define FLEXSPI_MCR0_IPGRANTWAIT_SHIFT (16U) @@ -10082,50 +15327,86 @@ typedef struct { #define FLEXSPI_MCR0_AHBGRANTWAIT_MASK (0xFF000000U) #define FLEXSPI_MCR0_AHBGRANTWAIT_SHIFT (24U) #define FLEXSPI_MCR0_AHBGRANTWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_AHBGRANTWAIT_SHIFT)) & FLEXSPI_MCR0_AHBGRANTWAIT_MASK) +/*! @} */ /*! @name MCR1 - Module Control Register 1 */ +/*! @{ */ #define FLEXSPI_MCR1_AHBBUSWAIT_MASK (0xFFFFU) #define FLEXSPI_MCR1_AHBBUSWAIT_SHIFT (0U) #define FLEXSPI_MCR1_AHBBUSWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR1_AHBBUSWAIT_SHIFT)) & FLEXSPI_MCR1_AHBBUSWAIT_MASK) #define FLEXSPI_MCR1_SEQWAIT_MASK (0xFFFF0000U) #define FLEXSPI_MCR1_SEQWAIT_SHIFT (16U) #define FLEXSPI_MCR1_SEQWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR1_SEQWAIT_SHIFT)) & FLEXSPI_MCR1_SEQWAIT_MASK) +/*! @} */ /*! @name MCR2 - Module Control Register 2 */ +/*! @{ */ #define FLEXSPI_MCR2_CLRAHBBUFOPT_MASK (0x800U) #define FLEXSPI_MCR2_CLRAHBBUFOPT_SHIFT (11U) +/*! CLRAHBBUFOPT - This bit determines whether AHB RX Buffer and AHB TX Buffer will be cleaned automaticaly when FlexSPI returns STOP mode ACK. Software should set this bit if AHB RX Buffer or AHB TX Buffer will be powered off in STOP mode. Otherwise AHB read access after exiting STOP mode may hit AHB RX Buffer or AHB TX Buffer but their data entries are invalid. + * 0b0..AHB RX/TX Buffer will not be cleaned automatically when FlexSPI return Stop mode ACK. + * 0b1..AHB RX/TX Buffer will be cleaned automatically when FlexSPI return Stop mode ACK. + */ #define FLEXSPI_MCR2_CLRAHBBUFOPT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_CLRAHBBUFOPT_SHIFT)) & FLEXSPI_MCR2_CLRAHBBUFOPT_MASK) #define FLEXSPI_MCR2_CLRLEARNPHASE_MASK (0x4000U) #define FLEXSPI_MCR2_CLRLEARNPHASE_SHIFT (14U) #define FLEXSPI_MCR2_CLRLEARNPHASE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_CLRLEARNPHASE_SHIFT)) & FLEXSPI_MCR2_CLRLEARNPHASE_MASK) #define FLEXSPI_MCR2_SAMEDEVICEEN_MASK (0x8000U) #define FLEXSPI_MCR2_SAMEDEVICEEN_SHIFT (15U) +/*! SAMEDEVICEEN - All external devices are same devices (both in types and size) for A1/A2/B1/B2. + * 0b0..In Individual mode, FLSHA1CRx/FLSHA2CRx/FLSHB1CRx/FLSHB2CRx register setting will be applied to Flash A1/A2/B1/B2 seperately. In Parallel mode, FLSHA1CRx register setting will be applied to Flash A1 and B1, FLSHA2CRx register setting will be applied to Flash A2 and B2. FLSHB1CRx/FLSHB2CRx register settings will be ignored. + * 0b1..FLSHA1CR0/FLSHA1CR1/FLSHA1CR2 register settings will be applied to Flash A1/A2/B1/B2. FLSHA2CRx/FLSHB1CRx/FLSHB2CRx will be ignored. + */ #define FLEXSPI_MCR2_SAMEDEVICEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_SAMEDEVICEEN_SHIFT)) & FLEXSPI_MCR2_SAMEDEVICEEN_MASK) #define FLEXSPI_MCR2_SCKBDIFFOPT_MASK (0x80000U) #define FLEXSPI_MCR2_SCKBDIFFOPT_SHIFT (19U) +/*! SCKBDIFFOPT - SCKB pad can be used as SCKA differential clock output (inverted clock to SCKA). In this case, port B flash access is not available. After change the value of this feild, MCR0[SWRESET] should be set. + * 0b1..SCKB pad is used as port A SCK inverted clock output (Differential clock to SCKA). Port B flash access is not available. + * 0b0..SCKB pad is used as port B SCK clock output. Port B flash access is available. + */ #define FLEXSPI_MCR2_SCKBDIFFOPT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_SCKBDIFFOPT_SHIFT)) & FLEXSPI_MCR2_SCKBDIFFOPT_MASK) #define FLEXSPI_MCR2_RESUMEWAIT_MASK (0xFF000000U) #define FLEXSPI_MCR2_RESUMEWAIT_SHIFT (24U) #define FLEXSPI_MCR2_RESUMEWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_RESUMEWAIT_SHIFT)) & FLEXSPI_MCR2_RESUMEWAIT_MASK) +/*! @} */ /*! @name AHBCR - AHB Bus Control Register */ +/*! @{ */ #define FLEXSPI_AHBCR_APAREN_MASK (0x1U) #define FLEXSPI_AHBCR_APAREN_SHIFT (0U) +/*! APAREN - Parallel mode enabled for AHB triggered Command (both read and write) . + * 0b0..Flash will be accessed in Individual mode. + * 0b1..Flash will be accessed in Parallel mode. + */ #define FLEXSPI_AHBCR_APAREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_APAREN_SHIFT)) & FLEXSPI_AHBCR_APAREN_MASK) #define FLEXSPI_AHBCR_CACHABLEEN_MASK (0x8U) #define FLEXSPI_AHBCR_CACHABLEEN_SHIFT (3U) +/*! CACHABLEEN - Enable AHB bus cachable read access support. + * 0b0..Disabled. When there is AHB bus cachable read access, FlexSPI will not check whether it hit AHB TX Buffer. + * 0b1..Enabled. When there is AHB bus cachable read access, FlexSPI will check whether it hit AHB TX Buffer first. + */ #define FLEXSPI_AHBCR_CACHABLEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_CACHABLEEN_SHIFT)) & FLEXSPI_AHBCR_CACHABLEEN_MASK) #define FLEXSPI_AHBCR_BUFFERABLEEN_MASK (0x10U) #define FLEXSPI_AHBCR_BUFFERABLEEN_SHIFT (4U) +/*! BUFFERABLEEN - Enable AHB bus bufferable write access support. This field affects the last beat of AHB write access, refer for more details about AHB bufferable write. + * 0b0..Disabled. For all AHB write access (no matter bufferable or non-bufferable ), FlexSPI will return AHB Bus ready after all data is transmitted to External device and AHB command finished. + * 0b1..Enabled. For AHB bufferable write access, FlexSPI will return AHB Bus ready when the AHB command is granted by arbitrator and will not wait for AHB command finished. + */ #define FLEXSPI_AHBCR_BUFFERABLEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_BUFFERABLEEN_SHIFT)) & FLEXSPI_AHBCR_BUFFERABLEEN_MASK) #define FLEXSPI_AHBCR_PREFETCHEN_MASK (0x20U) #define FLEXSPI_AHBCR_PREFETCHEN_SHIFT (5U) #define FLEXSPI_AHBCR_PREFETCHEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_PREFETCHEN_SHIFT)) & FLEXSPI_AHBCR_PREFETCHEN_MASK) #define FLEXSPI_AHBCR_READADDROPT_MASK (0x40U) #define FLEXSPI_AHBCR_READADDROPT_SHIFT (6U) +/*! READADDROPT - AHB Read Address option bit. This option bit is intend to remove AHB burst start address alignment limitation. + * 0b0..There is AHB read burst start address alignment limitation when flash is accessed in parallel mode or flash is wordaddressable. + * 0b1..There is no AHB read burst start address alignment limitation. FlexSPI will fetch more datas than AHB burst required to meet the alignment requirement. + */ #define FLEXSPI_AHBCR_READADDROPT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_READADDROPT_SHIFT)) & FLEXSPI_AHBCR_READADDROPT_MASK) +/*! @} */ /*! @name INTEN - Interrupt Enable Register */ +/*! @{ */ #define FLEXSPI_INTEN_IPCMDDONEEN_MASK (0x1U) #define FLEXSPI_INTEN_IPCMDDONEEN_SHIFT (0U) #define FLEXSPI_INTEN_IPCMDDONEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPCMDDONEEN_SHIFT)) & FLEXSPI_INTEN_IPCMDDONEEN_MASK) @@ -10159,8 +15440,10 @@ typedef struct { #define FLEXSPI_INTEN_SEQTIMEOUTEN_MASK (0x800U) #define FLEXSPI_INTEN_SEQTIMEOUTEN_SHIFT (11U) #define FLEXSPI_INTEN_SEQTIMEOUTEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_SEQTIMEOUTEN_SHIFT)) & FLEXSPI_INTEN_SEQTIMEOUTEN_MASK) +/*! @} */ /*! @name INTR - Interrupt Register */ +/*! @{ */ #define FLEXSPI_INTR_IPCMDDONE_MASK (0x1U) #define FLEXSPI_INTR_IPCMDDONE_SHIFT (0U) #define FLEXSPI_INTR_IPCMDDONE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPCMDDONE_SHIFT)) & FLEXSPI_INTR_IPCMDDONE_MASK) @@ -10194,21 +15477,27 @@ typedef struct { #define FLEXSPI_INTR_SEQTIMEOUT_MASK (0x800U) #define FLEXSPI_INTR_SEQTIMEOUT_SHIFT (11U) #define FLEXSPI_INTR_SEQTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_SEQTIMEOUT_SHIFT)) & FLEXSPI_INTR_SEQTIMEOUT_MASK) +/*! @} */ /*! @name LUTKEY - LUT Key Register */ +/*! @{ */ #define FLEXSPI_LUTKEY_KEY_MASK (0xFFFFFFFFU) #define FLEXSPI_LUTKEY_KEY_SHIFT (0U) #define FLEXSPI_LUTKEY_KEY(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUTKEY_KEY_SHIFT)) & FLEXSPI_LUTKEY_KEY_MASK) +/*! @} */ /*! @name LUTCR - LUT Control Register */ +/*! @{ */ #define FLEXSPI_LUTCR_LOCK_MASK (0x1U) #define FLEXSPI_LUTCR_LOCK_SHIFT (0U) #define FLEXSPI_LUTCR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUTCR_LOCK_SHIFT)) & FLEXSPI_LUTCR_LOCK_MASK) #define FLEXSPI_LUTCR_UNLOCK_MASK (0x2U) #define FLEXSPI_LUTCR_UNLOCK_SHIFT (1U) #define FLEXSPI_LUTCR_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUTCR_UNLOCK_SHIFT)) & FLEXSPI_LUTCR_UNLOCK_MASK) +/*! @} */ /*! @name AHBRXBUFCR0 - AHB RX Buffer 0 Control Register 0..AHB RX Buffer 3 Control Register 0 */ +/*! @{ */ #define FLEXSPI_AHBRXBUFCR0_BUFSZ_MASK (0xFFU) #define FLEXSPI_AHBRXBUFCR0_BUFSZ_SHIFT (0U) #define FLEXSPI_AHBRXBUFCR0_BUFSZ(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_BUFSZ_SHIFT)) & FLEXSPI_AHBRXBUFCR0_BUFSZ_MASK) @@ -10218,19 +15507,26 @@ typedef struct { #define FLEXSPI_AHBRXBUFCR0_PRIORITY_MASK (0x3000000U) #define FLEXSPI_AHBRXBUFCR0_PRIORITY_SHIFT (24U) #define FLEXSPI_AHBRXBUFCR0_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_PRIORITY_SHIFT)) & FLEXSPI_AHBRXBUFCR0_PRIORITY_MASK) +#define FLEXSPI_AHBRXBUFCR0_PREFETCHEN_MASK (0x80000000U) +#define FLEXSPI_AHBRXBUFCR0_PREFETCHEN_SHIFT (31U) +#define FLEXSPI_AHBRXBUFCR0_PREFETCHEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_PREFETCHEN_SHIFT)) & FLEXSPI_AHBRXBUFCR0_PREFETCHEN_MASK) +/*! @} */ /* The count of FLEXSPI_AHBRXBUFCR0 */ #define FLEXSPI_AHBRXBUFCR0_COUNT (4U) /*! @name FLSHCR0 - Flash A1 Control Register 0..Flash B2 Control Register 0 */ +/*! @{ */ #define FLEXSPI_FLSHCR0_FLSHSZ_MASK (0x7FFFFFU) #define FLEXSPI_FLSHCR0_FLSHSZ_SHIFT (0U) #define FLEXSPI_FLSHCR0_FLSHSZ(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR0_FLSHSZ_SHIFT)) & FLEXSPI_FLSHCR0_FLSHSZ_MASK) +/*! @} */ /* The count of FLEXSPI_FLSHCR0 */ #define FLEXSPI_FLSHCR0_COUNT (4U) /*! @name FLSHCR1 - Flash A1 Control Register 1..Flash B2 Control Register 1 */ +/*! @{ */ #define FLEXSPI_FLSHCR1_TCSS_MASK (0x1FU) #define FLEXSPI_FLSHCR1_TCSS_SHIFT (0U) #define FLEXSPI_FLSHCR1_TCSS(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_TCSS_SHIFT)) & FLEXSPI_FLSHCR1_TCSS_MASK) @@ -10245,15 +15541,21 @@ typedef struct { #define FLEXSPI_FLSHCR1_CAS(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_CAS_SHIFT)) & FLEXSPI_FLSHCR1_CAS_MASK) #define FLEXSPI_FLSHCR1_CSINTERVALUNIT_MASK (0x8000U) #define FLEXSPI_FLSHCR1_CSINTERVALUNIT_SHIFT (15U) +/*! CSINTERVALUNIT - CS interval unit + * 0b0..The CS interval unit is 1 serial clock cycle + * 0b1..The CS interval unit is 256 serial clock cycle + */ #define FLEXSPI_FLSHCR1_CSINTERVALUNIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_CSINTERVALUNIT_SHIFT)) & FLEXSPI_FLSHCR1_CSINTERVALUNIT_MASK) #define FLEXSPI_FLSHCR1_CSINTERVAL_MASK (0xFFFF0000U) #define FLEXSPI_FLSHCR1_CSINTERVAL_SHIFT (16U) #define FLEXSPI_FLSHCR1_CSINTERVAL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_CSINTERVAL_SHIFT)) & FLEXSPI_FLSHCR1_CSINTERVAL_MASK) +/*! @} */ /* The count of FLEXSPI_FLSHCR1 */ #define FLEXSPI_FLSHCR1_COUNT (4U) /*! @name FLSHCR2 - Flash A1 Control Register 2..Flash B2 Control Register 2 */ +/*! @{ */ #define FLEXSPI_FLSHCR2_ARDSEQID_MASK (0xFU) #define FLEXSPI_FLSHCR2_ARDSEQID_SHIFT (0U) #define FLEXSPI_FLSHCR2_ARDSEQID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_ARDSEQID_SHIFT)) & FLEXSPI_FLSHCR2_ARDSEQID_MASK) @@ -10271,31 +15573,59 @@ typedef struct { #define FLEXSPI_FLSHCR2_AWRWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRWAIT_SHIFT)) & FLEXSPI_FLSHCR2_AWRWAIT_MASK) #define FLEXSPI_FLSHCR2_AWRWAITUNIT_MASK (0x70000000U) #define FLEXSPI_FLSHCR2_AWRWAITUNIT_SHIFT (28U) +/*! AWRWAITUNIT - AWRWAIT unit + * 0b000..The AWRWAIT unit is 2 ahb clock cycle + * 0b001..The AWRWAIT unit is 8 ahb clock cycle + * 0b010..The AWRWAIT unit is 32 ahb clock cycle + * 0b011..The AWRWAIT unit is 128 ahb clock cycle + * 0b100..The AWRWAIT unit is 512 ahb clock cycle + * 0b101..The AWRWAIT unit is 2048 ahb clock cycle + * 0b110..The AWRWAIT unit is 8192 ahb clock cycle + * 0b111..The AWRWAIT unit is 32768 ahb clock cycle + */ #define FLEXSPI_FLSHCR2_AWRWAITUNIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRWAITUNIT_SHIFT)) & FLEXSPI_FLSHCR2_AWRWAITUNIT_MASK) #define FLEXSPI_FLSHCR2_CLRINSTRPTR_MASK (0x80000000U) #define FLEXSPI_FLSHCR2_CLRINSTRPTR_SHIFT (31U) #define FLEXSPI_FLSHCR2_CLRINSTRPTR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_CLRINSTRPTR_SHIFT)) & FLEXSPI_FLSHCR2_CLRINSTRPTR_MASK) +/*! @} */ /* The count of FLEXSPI_FLSHCR2 */ #define FLEXSPI_FLSHCR2_COUNT (4U) /*! @name FLSHCR4 - Flash Control Register 4 */ +/*! @{ */ #define FLEXSPI_FLSHCR4_WMOPT1_MASK (0x1U) #define FLEXSPI_FLSHCR4_WMOPT1_SHIFT (0U) +/*! WMOPT1 - Write mask option bit 1. This option bit could be used to remove AHB write burst start address alignment limitation. + * 0b0..DQS pin will be used as Write Mask when writing to external device. There is no limitation on AHB write burst start address alignment when flash is accessed in individual mode. + * 0b1..DQS pin will not be used as Write Mask when writing to external device. There is limitation on AHB write burst start address alignment when flash is accessed in individual mode. + */ #define FLEXSPI_FLSHCR4_WMOPT1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR4_WMOPT1_SHIFT)) & FLEXSPI_FLSHCR4_WMOPT1_MASK) #define FLEXSPI_FLSHCR4_WMENA_MASK (0x4U) #define FLEXSPI_FLSHCR4_WMENA_SHIFT (2U) +/*! WMENA - Write mask enable bit for flash device on port A. When write mask function is needed for memory device on port A, this bit must be set. + * 0b0..Write mask is disabled, DQS(RWDS) pin will be un-driven when writing to external device. + * 0b1..Write mask is enabled, DQS(RWDS) pin will be driven by FlexSPI as write mask output when writing to external device. + */ #define FLEXSPI_FLSHCR4_WMENA(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR4_WMENA_SHIFT)) & FLEXSPI_FLSHCR4_WMENA_MASK) #define FLEXSPI_FLSHCR4_WMENB_MASK (0x8U) #define FLEXSPI_FLSHCR4_WMENB_SHIFT (3U) +/*! WMENB - Write mask enable bit for flash device on port B. When write mask function is needed for memory device on port B, this bit must be set. + * 0b0..Write mask is disabled, DQS(RWDS) pin will be un-driven when writing to external device. + * 0b1..Write mask is enabled, DQS(RWDS) pin will be driven by FlexSPI as write mask output when writing to external device. + */ #define FLEXSPI_FLSHCR4_WMENB(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR4_WMENB_SHIFT)) & FLEXSPI_FLSHCR4_WMENB_MASK) +/*! @} */ /*! @name IPCR0 - IP Control Register 0 */ +/*! @{ */ #define FLEXSPI_IPCR0_SFAR_MASK (0xFFFFFFFFU) #define FLEXSPI_IPCR0_SFAR_SHIFT (0U) #define FLEXSPI_IPCR0_SFAR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR0_SFAR_SHIFT)) & FLEXSPI_IPCR0_SFAR_MASK) +/*! @} */ /*! @name IPCR1 - IP Control Register 1 */ +/*! @{ */ #define FLEXSPI_IPCR1_IDATSZ_MASK (0xFFFFU) #define FLEXSPI_IPCR1_IDATSZ_SHIFT (0U) #define FLEXSPI_IPCR1_IDATSZ(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_IDATSZ_SHIFT)) & FLEXSPI_IPCR1_IDATSZ_MASK) @@ -10307,36 +15637,56 @@ typedef struct { #define FLEXSPI_IPCR1_ISEQNUM(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_ISEQNUM_SHIFT)) & FLEXSPI_IPCR1_ISEQNUM_MASK) #define FLEXSPI_IPCR1_IPAREN_MASK (0x80000000U) #define FLEXSPI_IPCR1_IPAREN_SHIFT (31U) +/*! IPAREN - Parallel mode Enabled for IP command. + * 0b0..Flash will be accessed in Individual mode. + * 0b1..Flash will be accessed in Parallel mode. + */ #define FLEXSPI_IPCR1_IPAREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_IPAREN_SHIFT)) & FLEXSPI_IPCR1_IPAREN_MASK) +/*! @} */ /*! @name IPCMD - IP Command Register */ +/*! @{ */ #define FLEXSPI_IPCMD_TRG_MASK (0x1U) #define FLEXSPI_IPCMD_TRG_SHIFT (0U) #define FLEXSPI_IPCMD_TRG(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCMD_TRG_SHIFT)) & FLEXSPI_IPCMD_TRG_MASK) +/*! @} */ /*! @name IPRXFCR - IP RX FIFO Control Register */ +/*! @{ */ #define FLEXSPI_IPRXFCR_CLRIPRXF_MASK (0x1U) #define FLEXSPI_IPRXFCR_CLRIPRXF_SHIFT (0U) #define FLEXSPI_IPRXFCR_CLRIPRXF(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFCR_CLRIPRXF_SHIFT)) & FLEXSPI_IPRXFCR_CLRIPRXF_MASK) #define FLEXSPI_IPRXFCR_RXDMAEN_MASK (0x2U) #define FLEXSPI_IPRXFCR_RXDMAEN_SHIFT (1U) +/*! RXDMAEN - IP RX FIFO reading by DMA enabled. + * 0b0..IP RX FIFO would be read by processor. + * 0b1..IP RX FIFO would be read by DMA. + */ #define FLEXSPI_IPRXFCR_RXDMAEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFCR_RXDMAEN_SHIFT)) & FLEXSPI_IPRXFCR_RXDMAEN_MASK) #define FLEXSPI_IPRXFCR_RXWMRK_MASK (0x3CU) #define FLEXSPI_IPRXFCR_RXWMRK_SHIFT (2U) #define FLEXSPI_IPRXFCR_RXWMRK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFCR_RXWMRK_SHIFT)) & FLEXSPI_IPRXFCR_RXWMRK_MASK) +/*! @} */ /*! @name IPTXFCR - IP TX FIFO Control Register */ +/*! @{ */ #define FLEXSPI_IPTXFCR_CLRIPTXF_MASK (0x1U) #define FLEXSPI_IPTXFCR_CLRIPTXF_SHIFT (0U) #define FLEXSPI_IPTXFCR_CLRIPTXF(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFCR_CLRIPTXF_SHIFT)) & FLEXSPI_IPTXFCR_CLRIPTXF_MASK) #define FLEXSPI_IPTXFCR_TXDMAEN_MASK (0x2U) #define FLEXSPI_IPTXFCR_TXDMAEN_SHIFT (1U) +/*! TXDMAEN - IP TX FIFO filling by DMA enabled. + * 0b0..IP TX FIFO would be filled by processor. + * 0b1..IP TX FIFO would be filled by DMA. + */ #define FLEXSPI_IPTXFCR_TXDMAEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFCR_TXDMAEN_SHIFT)) & FLEXSPI_IPTXFCR_TXDMAEN_MASK) #define FLEXSPI_IPTXFCR_TXWMRK_MASK (0x3CU) #define FLEXSPI_IPTXFCR_TXWMRK_SHIFT (2U) #define FLEXSPI_IPTXFCR_TXWMRK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFCR_TXWMRK_SHIFT)) & FLEXSPI_IPTXFCR_TXWMRK_MASK) +/*! @} */ /*! @name DLLCR - DLL Control Register 0 */ +/*! @{ */ #define FLEXSPI_DLLCR_DLLEN_MASK (0x1U) #define FLEXSPI_DLLCR_DLLEN_SHIFT (0U) #define FLEXSPI_DLLCR_DLLEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_DLLEN_SHIFT)) & FLEXSPI_DLLCR_DLLEN_MASK) @@ -10352,11 +15702,13 @@ typedef struct { #define FLEXSPI_DLLCR_OVRDVAL_MASK (0x7E00U) #define FLEXSPI_DLLCR_OVRDVAL_SHIFT (9U) #define FLEXSPI_DLLCR_OVRDVAL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_OVRDVAL_SHIFT)) & FLEXSPI_DLLCR_OVRDVAL_MASK) +/*! @} */ /* The count of FLEXSPI_DLLCR */ #define FLEXSPI_DLLCR_COUNT (2U) /*! @name STS0 - Status Register 0 */ +/*! @{ */ #define FLEXSPI_STS0_SEQIDLE_MASK (0x1U) #define FLEXSPI_STS0_SEQIDLE_SHIFT (0U) #define FLEXSPI_STS0_SEQIDLE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS0_SEQIDLE_SHIFT)) & FLEXSPI_STS0_SEQIDLE_MASK) @@ -10365,23 +15717,51 @@ typedef struct { #define FLEXSPI_STS0_ARBIDLE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS0_ARBIDLE_SHIFT)) & FLEXSPI_STS0_ARBIDLE_MASK) #define FLEXSPI_STS0_ARBCMDSRC_MASK (0xCU) #define FLEXSPI_STS0_ARBCMDSRC_SHIFT (2U) +/*! ARBCMDSRC - This status field indicates the trigger source of current command sequence granted by arbitrator. This field value is meaningless when ARB_CTL is not busy (STS0[ARBIDLE]=0x1). + * 0b00..Triggered by AHB read command (triggered by AHB read). + * 0b01..Triggered by AHB write command (triggered by AHB Write). + * 0b10..Triggered by IP command (triggered by setting register bit IPCMD.TRG). + * 0b11..Triggered by suspended command (resumed). + */ #define FLEXSPI_STS0_ARBCMDSRC(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS0_ARBCMDSRC_SHIFT)) & FLEXSPI_STS0_ARBCMDSRC_MASK) +/*! @} */ /*! @name STS1 - Status Register 1 */ +/*! @{ */ #define FLEXSPI_STS1_AHBCMDERRID_MASK (0xFU) #define FLEXSPI_STS1_AHBCMDERRID_SHIFT (0U) #define FLEXSPI_STS1_AHBCMDERRID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_AHBCMDERRID_SHIFT)) & FLEXSPI_STS1_AHBCMDERRID_MASK) #define FLEXSPI_STS1_AHBCMDERRCODE_MASK (0xF00U) #define FLEXSPI_STS1_AHBCMDERRCODE_SHIFT (8U) +/*! AHBCMDERRCODE - Indicates the Error Code when AHB command Error detected. This field will be cleared when INTR[AHBCMDERR] is write-1-clear(w1c). + * 0b0000..No error. + * 0b0010..AHB Write command with JMP_ON_CS instruction used in the sequence. + * 0b0011..There is unknown instruction opcode in the sequence. + * 0b0100..Instruction DUMMY_SDR/DUMMY_RWDS_SDR used in DDR sequence. + * 0b0101..Instruction DUMMY_DDR/DUMMY_RWDS_DDR used in SDR sequence. + * 0b1110..Sequence execution timeout. + */ #define FLEXSPI_STS1_AHBCMDERRCODE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_AHBCMDERRCODE_SHIFT)) & FLEXSPI_STS1_AHBCMDERRCODE_MASK) #define FLEXSPI_STS1_IPCMDERRID_MASK (0xF0000U) #define FLEXSPI_STS1_IPCMDERRID_SHIFT (16U) #define FLEXSPI_STS1_IPCMDERRID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_IPCMDERRID_SHIFT)) & FLEXSPI_STS1_IPCMDERRID_MASK) #define FLEXSPI_STS1_IPCMDERRCODE_MASK (0xF000000U) #define FLEXSPI_STS1_IPCMDERRCODE_SHIFT (24U) +/*! IPCMDERRCODE - Indicates the Error Code when IP command Error detected. This field will be cleared when INTR[IPCMDERR] is write-1-clear(w1c). + * 0b0000..No error. + * 0b0010..IP command with JMP_ON_CS instruction used in the sequence. + * 0b0011..There is unknown instruction opcode in the sequence. + * 0b0100..Instruction DUMMY_SDR/DUMMY_RWDS_SDR used in DDR sequence. + * 0b0101..Instruction DUMMY_DDR/DUMMY_RWDS_DDR used in SDR sequence. + * 0b0110..Flash access start address exceed the whole flash address range (A1/A2/B1/B2). + * 0b1110..Sequence execution timeout. + * 0b1111..Flash boundary crossed. + */ #define FLEXSPI_STS1_IPCMDERRCODE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_IPCMDERRCODE_SHIFT)) & FLEXSPI_STS1_IPCMDERRCODE_MASK) +/*! @} */ /*! @name STS2 - Status Register 2 */ +/*! @{ */ #define FLEXSPI_STS2_ASLVLOCK_MASK (0x1U) #define FLEXSPI_STS2_ASLVLOCK_SHIFT (0U) #define FLEXSPI_STS2_ASLVLOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_ASLVLOCK_SHIFT)) & FLEXSPI_STS2_ASLVLOCK_MASK) @@ -10406,8 +15786,10 @@ typedef struct { #define FLEXSPI_STS2_BREFSEL_MASK (0x3F000000U) #define FLEXSPI_STS2_BREFSEL_SHIFT (24U) #define FLEXSPI_STS2_BREFSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_BREFSEL_SHIFT)) & FLEXSPI_STS2_BREFSEL_MASK) +/*! @} */ /*! @name AHBSPNDSTS - AHB Suspend Status Register */ +/*! @{ */ #define FLEXSPI_AHBSPNDSTS_ACTIVE_MASK (0x1U) #define FLEXSPI_AHBSPNDSTS_ACTIVE_SHIFT (0U) #define FLEXSPI_AHBSPNDSTS_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBSPNDSTS_ACTIVE_SHIFT)) & FLEXSPI_AHBSPNDSTS_ACTIVE_MASK) @@ -10417,40 +15799,50 @@ typedef struct { #define FLEXSPI_AHBSPNDSTS_DATLFT_MASK (0xFFFF0000U) #define FLEXSPI_AHBSPNDSTS_DATLFT_SHIFT (16U) #define FLEXSPI_AHBSPNDSTS_DATLFT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBSPNDSTS_DATLFT_SHIFT)) & FLEXSPI_AHBSPNDSTS_DATLFT_MASK) +/*! @} */ /*! @name IPRXFSTS - IP RX FIFO Status Register */ +/*! @{ */ #define FLEXSPI_IPRXFSTS_FILL_MASK (0xFFU) #define FLEXSPI_IPRXFSTS_FILL_SHIFT (0U) #define FLEXSPI_IPRXFSTS_FILL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFSTS_FILL_SHIFT)) & FLEXSPI_IPRXFSTS_FILL_MASK) #define FLEXSPI_IPRXFSTS_RDCNTR_MASK (0xFFFF0000U) #define FLEXSPI_IPRXFSTS_RDCNTR_SHIFT (16U) #define FLEXSPI_IPRXFSTS_RDCNTR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFSTS_RDCNTR_SHIFT)) & FLEXSPI_IPRXFSTS_RDCNTR_MASK) +/*! @} */ /*! @name IPTXFSTS - IP TX FIFO Status Register */ +/*! @{ */ #define FLEXSPI_IPTXFSTS_FILL_MASK (0xFFU) #define FLEXSPI_IPTXFSTS_FILL_SHIFT (0U) #define FLEXSPI_IPTXFSTS_FILL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFSTS_FILL_SHIFT)) & FLEXSPI_IPTXFSTS_FILL_MASK) #define FLEXSPI_IPTXFSTS_WRCNTR_MASK (0xFFFF0000U) #define FLEXSPI_IPTXFSTS_WRCNTR_SHIFT (16U) #define FLEXSPI_IPTXFSTS_WRCNTR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFSTS_WRCNTR_SHIFT)) & FLEXSPI_IPTXFSTS_WRCNTR_MASK) +/*! @} */ /*! @name RFDR - IP RX FIFO Data Register 0..IP RX FIFO Data Register 31 */ +/*! @{ */ #define FLEXSPI_RFDR_RXDATA_MASK (0xFFFFFFFFU) #define FLEXSPI_RFDR_RXDATA_SHIFT (0U) #define FLEXSPI_RFDR_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_RFDR_RXDATA_SHIFT)) & FLEXSPI_RFDR_RXDATA_MASK) +/*! @} */ /* The count of FLEXSPI_RFDR */ #define FLEXSPI_RFDR_COUNT (32U) /*! @name TFDR - IP TX FIFO Data Register 0..IP TX FIFO Data Register 31 */ +/*! @{ */ #define FLEXSPI_TFDR_TXDATA_MASK (0xFFFFFFFFU) #define FLEXSPI_TFDR_TXDATA_SHIFT (0U) #define FLEXSPI_TFDR_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_TFDR_TXDATA_SHIFT)) & FLEXSPI_TFDR_TXDATA_MASK) +/*! @} */ /* The count of FLEXSPI_TFDR */ #define FLEXSPI_TFDR_COUNT (32U) /*! @name LUT - LUT 0..LUT 63 */ +/*! @{ */ #define FLEXSPI_LUT_OPERAND0_MASK (0xFFU) #define FLEXSPI_LUT_OPERAND0_SHIFT (0U) #define FLEXSPI_LUT_OPERAND0(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPERAND0_SHIFT)) & FLEXSPI_LUT_OPERAND0_MASK) @@ -10469,6 +15861,7 @@ typedef struct { #define FLEXSPI_LUT_OPCODE1_MASK (0xFC000000U) #define FLEXSPI_LUT_OPCODE1_SHIFT (26U) #define FLEXSPI_LUT_OPCODE1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPCODE1_SHIFT)) & FLEXSPI_LUT_OPCODE1_MASK) +/*! @} */ /* The count of FLEXSPI_LUT */ #define FLEXSPI_LUT_COUNT (64U) @@ -10535,17 +15928,32 @@ typedef struct { */ /*! @name CNTR - GPC Interface control register */ +/*! @{ */ #define GPC_CNTR_MEGA_PDN_REQ_MASK (0x4U) #define GPC_CNTR_MEGA_PDN_REQ_SHIFT (2U) +/*! MEGA_PDN_REQ + * 0b0..No Request + * 0b1..Request power down sequence + */ #define GPC_CNTR_MEGA_PDN_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_CNTR_MEGA_PDN_REQ_SHIFT)) & GPC_CNTR_MEGA_PDN_REQ_MASK) #define GPC_CNTR_MEGA_PUP_REQ_MASK (0x8U) #define GPC_CNTR_MEGA_PUP_REQ_SHIFT (3U) +/*! MEGA_PUP_REQ + * 0b0..No Request + * 0b1..Request power up sequence + */ #define GPC_CNTR_MEGA_PUP_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_CNTR_MEGA_PUP_REQ_SHIFT)) & GPC_CNTR_MEGA_PUP_REQ_MASK) #define GPC_CNTR_PDRAM0_PGE_MASK (0x400000U) #define GPC_CNTR_PDRAM0_PGE_SHIFT (22U) +/*! PDRAM0_PGE + * 0b1..FlexRAM PDRAM0 domain (bank1-7) will be power down once when CPU core is power down. + * 0b0..FlexRAM PDRAM0 domain (bank1-7) will keep power on even if CPU core is power down. + */ #define GPC_CNTR_PDRAM0_PGE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CNTR_PDRAM0_PGE_SHIFT)) & GPC_CNTR_PDRAM0_PGE_MASK) +/*! @} */ /*! @name IMR - IRQ masking register 1..IRQ masking register 4 */ +/*! @{ */ #define GPC_IMR_IMR1_MASK (0xFFFFFFFFU) #define GPC_IMR_IMR1_SHIFT (0U) #define GPC_IMR_IMR1(x) (((uint32_t)(((uint32_t)(x)) << GPC_IMR_IMR1_SHIFT)) & GPC_IMR_IMR1_MASK) @@ -10558,11 +15966,13 @@ typedef struct { #define GPC_IMR_IMR4_MASK (0xFFFFFFFFU) #define GPC_IMR_IMR4_SHIFT (0U) #define GPC_IMR_IMR4(x) (((uint32_t)(((uint32_t)(x)) << GPC_IMR_IMR4_SHIFT)) & GPC_IMR_IMR4_MASK) +/*! @} */ /* The count of GPC_IMR */ #define GPC_IMR_COUNT (4U) /*! @name ISR - IRQ status resister 1..IRQ status resister 4 */ +/*! @{ */ #define GPC_ISR_ISR1_MASK (0xFFFFFFFFU) #define GPC_ISR_ISR1_SHIFT (0U) #define GPC_ISR_ISR1(x) (((uint32_t)(((uint32_t)(x)) << GPC_ISR_ISR1_SHIFT)) & GPC_ISR_ISR1_MASK) @@ -10575,19 +15985,24 @@ typedef struct { #define GPC_ISR_ISR4_MASK (0xFFFFFFFFU) #define GPC_ISR_ISR4_SHIFT (0U) #define GPC_ISR_ISR4(x) (((uint32_t)(((uint32_t)(x)) << GPC_ISR_ISR4_SHIFT)) & GPC_ISR_ISR4_MASK) +/*! @} */ /* The count of GPC_ISR */ #define GPC_ISR_COUNT (4U) /*! @name IMR5 - IRQ masking register 5 */ +/*! @{ */ #define GPC_IMR5_IMR5_MASK (0xFFFFFFFFU) #define GPC_IMR5_IMR5_SHIFT (0U) #define GPC_IMR5_IMR5(x) (((uint32_t)(((uint32_t)(x)) << GPC_IMR5_IMR5_SHIFT)) & GPC_IMR5_IMR5_MASK) +/*! @} */ /*! @name ISR5 - IRQ status resister 5 */ +/*! @{ */ #define GPC_ISR5_ISR4_MASK (0xFFFFFFFFU) #define GPC_ISR5_ISR4_SHIFT (0U) #define GPC_ISR5_ISR4(x) (((uint32_t)(((uint32_t)(x)) << GPC_ISR5_ISR4_SHIFT)) & GPC_ISR5_ISR4_MASK) +/*! @} */ /*! @@ -10631,6 +16046,10 @@ typedef struct { __IO uint32_t IMR; /**< GPIO interrupt mask register, offset: 0x14 */ __IO uint32_t ISR; /**< GPIO interrupt status register, offset: 0x18 */ __IO uint32_t EDGE_SEL; /**< GPIO edge select register, offset: 0x1C */ + uint8_t RESERVED_0[100]; + __O uint32_t DR_SET; /**< GPIO data register SET, offset: 0x84 */ + __O uint32_t DR_CLEAR; /**< GPIO data register CLEAR, offset: 0x88 */ + __O uint32_t DR_TOGGLE; /**< GPIO data register TOGGLE, offset: 0x8C */ } GPIO_Type; /* ---------------------------------------------------------------------------- @@ -10643,134 +16062,363 @@ typedef struct { */ /*! @name DR - GPIO data register */ +/*! @{ */ #define GPIO_DR_DR_MASK (0xFFFFFFFFU) #define GPIO_DR_DR_SHIFT (0U) #define GPIO_DR_DR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DR_DR_SHIFT)) & GPIO_DR_DR_MASK) +/*! @} */ /*! @name GDIR - GPIO direction register */ +/*! @{ */ #define GPIO_GDIR_GDIR_MASK (0xFFFFFFFFU) #define GPIO_GDIR_GDIR_SHIFT (0U) #define GPIO_GDIR_GDIR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GDIR_GDIR_SHIFT)) & GPIO_GDIR_GDIR_MASK) +/*! @} */ /*! @name PSR - GPIO pad status register */ +/*! @{ */ #define GPIO_PSR_PSR_MASK (0xFFFFFFFFU) #define GPIO_PSR_PSR_SHIFT (0U) #define GPIO_PSR_PSR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSR_PSR_SHIFT)) & GPIO_PSR_PSR_MASK) +/*! @} */ /*! @name ICR1 - GPIO interrupt configuration register1 */ +/*! @{ */ #define GPIO_ICR1_ICR0_MASK (0x3U) #define GPIO_ICR1_ICR0_SHIFT (0U) +/*! ICR0 - ICR0 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ #define GPIO_ICR1_ICR0(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR0_SHIFT)) & GPIO_ICR1_ICR0_MASK) #define GPIO_ICR1_ICR1_MASK (0xCU) #define GPIO_ICR1_ICR1_SHIFT (2U) +/*! ICR1 - ICR1 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ #define GPIO_ICR1_ICR1(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR1_SHIFT)) & GPIO_ICR1_ICR1_MASK) #define GPIO_ICR1_ICR2_MASK (0x30U) #define GPIO_ICR1_ICR2_SHIFT (4U) +/*! ICR2 - ICR2 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ #define GPIO_ICR1_ICR2(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR2_SHIFT)) & GPIO_ICR1_ICR2_MASK) #define GPIO_ICR1_ICR3_MASK (0xC0U) #define GPIO_ICR1_ICR3_SHIFT (6U) +/*! ICR3 - ICR3 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ #define GPIO_ICR1_ICR3(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR3_SHIFT)) & GPIO_ICR1_ICR3_MASK) #define GPIO_ICR1_ICR4_MASK (0x300U) #define GPIO_ICR1_ICR4_SHIFT (8U) +/*! ICR4 - ICR4 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ #define GPIO_ICR1_ICR4(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR4_SHIFT)) & GPIO_ICR1_ICR4_MASK) #define GPIO_ICR1_ICR5_MASK (0xC00U) #define GPIO_ICR1_ICR5_SHIFT (10U) +/*! ICR5 - ICR5 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ #define GPIO_ICR1_ICR5(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR5_SHIFT)) & GPIO_ICR1_ICR5_MASK) #define GPIO_ICR1_ICR6_MASK (0x3000U) #define GPIO_ICR1_ICR6_SHIFT (12U) +/*! ICR6 - ICR6 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ #define GPIO_ICR1_ICR6(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR6_SHIFT)) & GPIO_ICR1_ICR6_MASK) #define GPIO_ICR1_ICR7_MASK (0xC000U) #define GPIO_ICR1_ICR7_SHIFT (14U) +/*! ICR7 - ICR7 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ #define GPIO_ICR1_ICR7(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR7_SHIFT)) & GPIO_ICR1_ICR7_MASK) #define GPIO_ICR1_ICR8_MASK (0x30000U) #define GPIO_ICR1_ICR8_SHIFT (16U) +/*! ICR8 - ICR8 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ #define GPIO_ICR1_ICR8(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR8_SHIFT)) & GPIO_ICR1_ICR8_MASK) #define GPIO_ICR1_ICR9_MASK (0xC0000U) #define GPIO_ICR1_ICR9_SHIFT (18U) +/*! ICR9 - ICR9 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ #define GPIO_ICR1_ICR9(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR9_SHIFT)) & GPIO_ICR1_ICR9_MASK) #define GPIO_ICR1_ICR10_MASK (0x300000U) #define GPIO_ICR1_ICR10_SHIFT (20U) +/*! ICR10 - ICR10 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ #define GPIO_ICR1_ICR10(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR10_SHIFT)) & GPIO_ICR1_ICR10_MASK) #define GPIO_ICR1_ICR11_MASK (0xC00000U) #define GPIO_ICR1_ICR11_SHIFT (22U) +/*! ICR11 - ICR11 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ #define GPIO_ICR1_ICR11(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR11_SHIFT)) & GPIO_ICR1_ICR11_MASK) #define GPIO_ICR1_ICR12_MASK (0x3000000U) #define GPIO_ICR1_ICR12_SHIFT (24U) +/*! ICR12 - ICR12 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ #define GPIO_ICR1_ICR12(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR12_SHIFT)) & GPIO_ICR1_ICR12_MASK) #define GPIO_ICR1_ICR13_MASK (0xC000000U) #define GPIO_ICR1_ICR13_SHIFT (26U) +/*! ICR13 - ICR13 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ #define GPIO_ICR1_ICR13(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR13_SHIFT)) & GPIO_ICR1_ICR13_MASK) #define GPIO_ICR1_ICR14_MASK (0x30000000U) #define GPIO_ICR1_ICR14_SHIFT (28U) +/*! ICR14 - ICR14 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ #define GPIO_ICR1_ICR14(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR14_SHIFT)) & GPIO_ICR1_ICR14_MASK) #define GPIO_ICR1_ICR15_MASK (0xC0000000U) #define GPIO_ICR1_ICR15_SHIFT (30U) +/*! ICR15 - ICR15 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ #define GPIO_ICR1_ICR15(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR15_SHIFT)) & GPIO_ICR1_ICR15_MASK) +/*! @} */ /*! @name ICR2 - GPIO interrupt configuration register2 */ +/*! @{ */ #define GPIO_ICR2_ICR16_MASK (0x3U) #define GPIO_ICR2_ICR16_SHIFT (0U) +/*! ICR16 - ICR16 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ #define GPIO_ICR2_ICR16(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR16_SHIFT)) & GPIO_ICR2_ICR16_MASK) #define GPIO_ICR2_ICR17_MASK (0xCU) #define GPIO_ICR2_ICR17_SHIFT (2U) +/*! ICR17 - ICR17 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ #define GPIO_ICR2_ICR17(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR17_SHIFT)) & GPIO_ICR2_ICR17_MASK) #define GPIO_ICR2_ICR18_MASK (0x30U) #define GPIO_ICR2_ICR18_SHIFT (4U) +/*! ICR18 - ICR18 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ #define GPIO_ICR2_ICR18(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR18_SHIFT)) & GPIO_ICR2_ICR18_MASK) #define GPIO_ICR2_ICR19_MASK (0xC0U) #define GPIO_ICR2_ICR19_SHIFT (6U) +/*! ICR19 - ICR19 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ #define GPIO_ICR2_ICR19(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR19_SHIFT)) & GPIO_ICR2_ICR19_MASK) #define GPIO_ICR2_ICR20_MASK (0x300U) #define GPIO_ICR2_ICR20_SHIFT (8U) +/*! ICR20 - ICR20 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ #define GPIO_ICR2_ICR20(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR20_SHIFT)) & GPIO_ICR2_ICR20_MASK) #define GPIO_ICR2_ICR21_MASK (0xC00U) #define GPIO_ICR2_ICR21_SHIFT (10U) +/*! ICR21 - ICR21 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ #define GPIO_ICR2_ICR21(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR21_SHIFT)) & GPIO_ICR2_ICR21_MASK) #define GPIO_ICR2_ICR22_MASK (0x3000U) #define GPIO_ICR2_ICR22_SHIFT (12U) +/*! ICR22 - ICR22 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ #define GPIO_ICR2_ICR22(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR22_SHIFT)) & GPIO_ICR2_ICR22_MASK) #define GPIO_ICR2_ICR23_MASK (0xC000U) #define GPIO_ICR2_ICR23_SHIFT (14U) +/*! ICR23 - ICR23 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ #define GPIO_ICR2_ICR23(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR23_SHIFT)) & GPIO_ICR2_ICR23_MASK) #define GPIO_ICR2_ICR24_MASK (0x30000U) #define GPIO_ICR2_ICR24_SHIFT (16U) +/*! ICR24 - ICR24 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ #define GPIO_ICR2_ICR24(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR24_SHIFT)) & GPIO_ICR2_ICR24_MASK) #define GPIO_ICR2_ICR25_MASK (0xC0000U) #define GPIO_ICR2_ICR25_SHIFT (18U) +/*! ICR25 - ICR25 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ #define GPIO_ICR2_ICR25(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR25_SHIFT)) & GPIO_ICR2_ICR25_MASK) #define GPIO_ICR2_ICR26_MASK (0x300000U) #define GPIO_ICR2_ICR26_SHIFT (20U) +/*! ICR26 - ICR26 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ #define GPIO_ICR2_ICR26(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR26_SHIFT)) & GPIO_ICR2_ICR26_MASK) #define GPIO_ICR2_ICR27_MASK (0xC00000U) #define GPIO_ICR2_ICR27_SHIFT (22U) +/*! ICR27 - ICR27 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ #define GPIO_ICR2_ICR27(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR27_SHIFT)) & GPIO_ICR2_ICR27_MASK) #define GPIO_ICR2_ICR28_MASK (0x3000000U) #define GPIO_ICR2_ICR28_SHIFT (24U) +/*! ICR28 - ICR28 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ #define GPIO_ICR2_ICR28(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR28_SHIFT)) & GPIO_ICR2_ICR28_MASK) #define GPIO_ICR2_ICR29_MASK (0xC000000U) #define GPIO_ICR2_ICR29_SHIFT (26U) +/*! ICR29 - ICR29 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ #define GPIO_ICR2_ICR29(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR29_SHIFT)) & GPIO_ICR2_ICR29_MASK) #define GPIO_ICR2_ICR30_MASK (0x30000000U) #define GPIO_ICR2_ICR30_SHIFT (28U) +/*! ICR30 - ICR30 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ #define GPIO_ICR2_ICR30(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR30_SHIFT)) & GPIO_ICR2_ICR30_MASK) #define GPIO_ICR2_ICR31_MASK (0xC0000000U) #define GPIO_ICR2_ICR31_SHIFT (30U) +/*! ICR31 - ICR31 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ #define GPIO_ICR2_ICR31(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR31_SHIFT)) & GPIO_ICR2_ICR31_MASK) +/*! @} */ /*! @name IMR - GPIO interrupt mask register */ +/*! @{ */ #define GPIO_IMR_IMR_MASK (0xFFFFFFFFU) #define GPIO_IMR_IMR_SHIFT (0U) #define GPIO_IMR_IMR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_IMR_IMR_SHIFT)) & GPIO_IMR_IMR_MASK) +/*! @} */ /*! @name ISR - GPIO interrupt status register */ +/*! @{ */ #define GPIO_ISR_ISR_MASK (0xFFFFFFFFU) #define GPIO_ISR_ISR_SHIFT (0U) #define GPIO_ISR_ISR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISR_ISR_SHIFT)) & GPIO_ISR_ISR_MASK) +/*! @} */ /*! @name EDGE_SEL - GPIO edge select register */ +/*! @{ */ #define GPIO_EDGE_SEL_GPIO_EDGE_SEL_MASK (0xFFFFFFFFU) #define GPIO_EDGE_SEL_GPIO_EDGE_SEL_SHIFT (0U) #define GPIO_EDGE_SEL_GPIO_EDGE_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPIO_EDGE_SEL_GPIO_EDGE_SEL_SHIFT)) & GPIO_EDGE_SEL_GPIO_EDGE_SEL_MASK) +/*! @} */ + +/*! @name DR_SET - GPIO data register SET */ +/*! @{ */ +#define GPIO_DR_SET_DR_SET_MASK (0xFFFFFFFFU) +#define GPIO_DR_SET_DR_SET_SHIFT (0U) +#define GPIO_DR_SET_DR_SET(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DR_SET_DR_SET_SHIFT)) & GPIO_DR_SET_DR_SET_MASK) +/*! @} */ + +/*! @name DR_CLEAR - GPIO data register CLEAR */ +/*! @{ */ +#define GPIO_DR_CLEAR_DR_CLEAR_MASK (0xFFFFFFFFU) +#define GPIO_DR_CLEAR_DR_CLEAR_SHIFT (0U) +#define GPIO_DR_CLEAR_DR_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DR_CLEAR_DR_CLEAR_SHIFT)) & GPIO_DR_CLEAR_DR_CLEAR_MASK) +/*! @} */ + +/*! @name DR_TOGGLE - GPIO data register TOGGLE */ +/*! @{ */ +#define GPIO_DR_TOGGLE_DR_TOGGLE_MASK (0xFFFFFFFFU) +#define GPIO_DR_TOGGLE_DR_TOGGLE_SHIFT (0U) +#define GPIO_DR_TOGGLE_DR_TOGGLE(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DR_TOGGLE_DR_TOGGLE_SHIFT)) & GPIO_DR_TOGGLE_DR_TOGGLE_MASK) +/*! @} */ /*! @@ -10805,7 +16453,8 @@ typedef struct { #define GPIO_BASE_PTRS { (GPIO_Type *)0u, GPIO1, GPIO2, GPIO3, GPIO4, GPIO5 } /** Interrupt vectors for the GPIO peripheral type */ #define GPIO_IRQS { NotAvail_IRQn, GPIO1_INT0_IRQn, GPIO1_INT1_IRQn, GPIO1_INT2_IRQn, GPIO1_INT3_IRQn, GPIO1_INT4_IRQn, GPIO1_INT5_IRQn, GPIO1_INT6_IRQn, GPIO1_INT7_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn } -#define GPIO_COMBINED_IRQS { NotAvail_IRQn, GPIO1_Combined_16_31_IRQn, GPIO2_Combined_16_31_IRQn, GPIO2_Combined_0_15_IRQn, GPIO3_Combined_16_31_IRQn, GPIO3_Combined_0_15_IRQn, GPIO4_Combined_16_31_IRQn, GPIO4_Combined_0_15_IRQn, GPIO5_Combined_16_31_IRQn, GPIO5_Combined_0_15_IRQn } +#define GPIO_COMBINED_LOW_IRQS { NotAvail_IRQn, GPIO1_Combined_0_15_IRQn, GPIO2_Combined_0_15_IRQn, GPIO3_Combined_0_15_IRQn, GPIO4_Combined_0_15_IRQn, GPIO5_Combined_0_15_IRQn } +#define GPIO_COMBINED_HIGH_IRQS { NotAvail_IRQn, GPIO1_Combined_16_31_IRQn, GPIO2_Combined_16_31_IRQn, GPIO3_Combined_16_31_IRQn, GPIO4_Combined_16_31_IRQn, GPIO5_Combined_16_31_IRQn } /*! * @} @@ -10842,41 +16491,92 @@ typedef struct { */ /*! @name CR - GPT Control Register */ +/*! @{ */ #define GPT_CR_EN_MASK (0x1U) #define GPT_CR_EN_SHIFT (0U) +/*! EN + * 0b0..GPT is disabled. + * 0b1..GPT is enabled. + */ #define GPT_CR_EN(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_EN_SHIFT)) & GPT_CR_EN_MASK) #define GPT_CR_ENMOD_MASK (0x2U) #define GPT_CR_ENMOD_SHIFT (1U) +/*! ENMOD + * 0b0..GPT counter will retain its value when it is disabled. + * 0b1..GPT counter value is reset to 0 when it is disabled. + */ #define GPT_CR_ENMOD(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_ENMOD_SHIFT)) & GPT_CR_ENMOD_MASK) #define GPT_CR_DBGEN_MASK (0x4U) #define GPT_CR_DBGEN_SHIFT (2U) +/*! DBGEN + * 0b0..GPT is disabled in debug mode. + * 0b1..GPT is enabled in debug mode. + */ #define GPT_CR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_DBGEN_SHIFT)) & GPT_CR_DBGEN_MASK) #define GPT_CR_WAITEN_MASK (0x8U) #define GPT_CR_WAITEN_SHIFT (3U) +/*! WAITEN + * 0b0..GPT is disabled in wait mode. + * 0b1..GPT is enabled in wait mode. + */ #define GPT_CR_WAITEN(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_WAITEN_SHIFT)) & GPT_CR_WAITEN_MASK) #define GPT_CR_DOZEEN_MASK (0x10U) #define GPT_CR_DOZEEN_SHIFT (4U) +/*! DOZEEN + * 0b0..GPT is disabled in doze mode. + * 0b1..GPT is enabled in doze mode. + */ #define GPT_CR_DOZEEN(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_DOZEEN_SHIFT)) & GPT_CR_DOZEEN_MASK) #define GPT_CR_STOPEN_MASK (0x20U) #define GPT_CR_STOPEN_SHIFT (5U) +/*! STOPEN + * 0b0..GPT is disabled in Stop mode. + * 0b1..GPT is enabled in Stop mode. + */ #define GPT_CR_STOPEN(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_STOPEN_SHIFT)) & GPT_CR_STOPEN_MASK) #define GPT_CR_CLKSRC_MASK (0x1C0U) #define GPT_CR_CLKSRC_SHIFT (6U) +/*! CLKSRC + * 0b000..No clock + * 0b001..Peripheral Clock (ipg_clk) + * 0b010..High Frequency Reference Clock (ipg_clk_highfreq) + * 0b011..External Clock + * 0b100..Low Frequency Reference Clock (ipg_clk_32k) + * 0b101..Crystal oscillator as Reference Clock (ipg_clk_24M) + */ #define GPT_CR_CLKSRC(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_CLKSRC_SHIFT)) & GPT_CR_CLKSRC_MASK) #define GPT_CR_FRR_MASK (0x200U) #define GPT_CR_FRR_SHIFT (9U) +/*! FRR + * 0b0..Restart mode + * 0b1..Free-Run mode + */ #define GPT_CR_FRR(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_FRR_SHIFT)) & GPT_CR_FRR_MASK) #define GPT_CR_EN_24M_MASK (0x400U) #define GPT_CR_EN_24M_SHIFT (10U) +/*! EN_24M + * 0b0..24M clock disabled + * 0b1..24M clock enabled + */ #define GPT_CR_EN_24M(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_EN_24M_SHIFT)) & GPT_CR_EN_24M_MASK) #define GPT_CR_SWR_MASK (0x8000U) #define GPT_CR_SWR_SHIFT (15U) +/*! SWR + * 0b0..GPT is not in reset state + * 0b1..GPT is in reset state + */ #define GPT_CR_SWR(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_SWR_SHIFT)) & GPT_CR_SWR_MASK) #define GPT_CR_IM1_MASK (0x30000U) #define GPT_CR_IM1_SHIFT (16U) #define GPT_CR_IM1(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_IM1_SHIFT)) & GPT_CR_IM1_MASK) #define GPT_CR_IM2_MASK (0xC0000U) #define GPT_CR_IM2_SHIFT (18U) +/*! IM2 + * 0b00..capture disabled + * 0b01..capture on rising edge only + * 0b10..capture on falling edge only + * 0b11..capture on both edges + */ #define GPT_CR_IM2(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_IM2_SHIFT)) & GPT_CR_IM2_MASK) #define GPT_CR_OM1_MASK (0x700000U) #define GPT_CR_OM1_SHIFT (20U) @@ -10886,6 +16586,13 @@ typedef struct { #define GPT_CR_OM2(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_OM2_SHIFT)) & GPT_CR_OM2_MASK) #define GPT_CR_OM3_MASK (0x1C000000U) #define GPT_CR_OM3_SHIFT (26U) +/*! OM3 + * 0b000..Output disconnected. No response on pin. + * 0b001..Toggle output pin + * 0b010..Clear output pin + * 0b011..Set output pin + * 0b1xx..Generate an active low pulse (that is one input clock wide) on the output pin. + */ #define GPT_CR_OM3(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_OM3_SHIFT)) & GPT_CR_OM3_MASK) #define GPT_CR_FO1_MASK (0x20000000U) #define GPT_CR_FO1_SHIFT (29U) @@ -10895,17 +16602,35 @@ typedef struct { #define GPT_CR_FO2(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_FO2_SHIFT)) & GPT_CR_FO2_MASK) #define GPT_CR_FO3_MASK (0x80000000U) #define GPT_CR_FO3_SHIFT (31U) +/*! FO3 + * 0b0..Writing a 0 has no effect. + * 0b1..Causes the programmed pin action on the timer Output Compare n pin; the OFn flag is not set. + */ #define GPT_CR_FO3(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_FO3_SHIFT)) & GPT_CR_FO3_MASK) +/*! @} */ /*! @name PR - GPT Prescaler Register */ +/*! @{ */ #define GPT_PR_PRESCALER_MASK (0xFFFU) #define GPT_PR_PRESCALER_SHIFT (0U) +/*! PRESCALER + * 0b000000000000..Divide by 1 + * 0b000000000001..Divide by 2 + * 0b111111111111..Divide by 4096 + */ #define GPT_PR_PRESCALER(x) (((uint32_t)(((uint32_t)(x)) << GPT_PR_PRESCALER_SHIFT)) & GPT_PR_PRESCALER_MASK) #define GPT_PR_PRESCALER24M_MASK (0xF000U) #define GPT_PR_PRESCALER24M_SHIFT (12U) +/*! PRESCALER24M + * 0b0000..Divide by 1 + * 0b0001..Divide by 2 + * 0b1111..Divide by 16 + */ #define GPT_PR_PRESCALER24M(x) (((uint32_t)(((uint32_t)(x)) << GPT_PR_PRESCALER24M_SHIFT)) & GPT_PR_PRESCALER24M_MASK) +/*! @} */ /*! @name SR - GPT Status Register */ +/*! @{ */ #define GPT_SR_OF1_MASK (0x1U) #define GPT_SR_OF1_SHIFT (0U) #define GPT_SR_OF1(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_OF1_SHIFT)) & GPT_SR_OF1_MASK) @@ -10914,18 +16639,32 @@ typedef struct { #define GPT_SR_OF2(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_OF2_SHIFT)) & GPT_SR_OF2_MASK) #define GPT_SR_OF3_MASK (0x4U) #define GPT_SR_OF3_SHIFT (2U) +/*! OF3 + * 0b0..Compare event has not occurred. + * 0b1..Compare event has occurred. + */ #define GPT_SR_OF3(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_OF3_SHIFT)) & GPT_SR_OF3_MASK) #define GPT_SR_IF1_MASK (0x8U) #define GPT_SR_IF1_SHIFT (3U) #define GPT_SR_IF1(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_IF1_SHIFT)) & GPT_SR_IF1_MASK) #define GPT_SR_IF2_MASK (0x10U) #define GPT_SR_IF2_SHIFT (4U) +/*! IF2 + * 0b0..Capture event has not occurred. + * 0b1..Capture event has occurred. + */ #define GPT_SR_IF2(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_IF2_SHIFT)) & GPT_SR_IF2_MASK) #define GPT_SR_ROV_MASK (0x20U) #define GPT_SR_ROV_SHIFT (5U) +/*! ROV + * 0b0..Rollover has not occurred. + * 0b1..Rollover has occurred. + */ #define GPT_SR_ROV(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_ROV_SHIFT)) & GPT_SR_ROV_MASK) +/*! @} */ /*! @name IR - GPT Interrupt Register */ +/*! @{ */ #define GPT_IR_OF1IE_MASK (0x1U) #define GPT_IR_OF1IE_SHIFT (0U) #define GPT_IR_OF1IE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_OF1IE_SHIFT)) & GPT_IR_OF1IE_MASK) @@ -10934,37 +16673,56 @@ typedef struct { #define GPT_IR_OF2IE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_OF2IE_SHIFT)) & GPT_IR_OF2IE_MASK) #define GPT_IR_OF3IE_MASK (0x4U) #define GPT_IR_OF3IE_SHIFT (2U) +/*! OF3IE + * 0b0..Output Compare Channel n interrupt is disabled. + * 0b1..Output Compare Channel n interrupt is enabled. + */ #define GPT_IR_OF3IE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_OF3IE_SHIFT)) & GPT_IR_OF3IE_MASK) #define GPT_IR_IF1IE_MASK (0x8U) #define GPT_IR_IF1IE_SHIFT (3U) #define GPT_IR_IF1IE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_IF1IE_SHIFT)) & GPT_IR_IF1IE_MASK) #define GPT_IR_IF2IE_MASK (0x10U) #define GPT_IR_IF2IE_SHIFT (4U) +/*! IF2IE + * 0b0..IF2IE Input Capture n Interrupt Enable is disabled. + * 0b1..IF2IE Input Capture n Interrupt Enable is enabled. + */ #define GPT_IR_IF2IE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_IF2IE_SHIFT)) & GPT_IR_IF2IE_MASK) #define GPT_IR_ROVIE_MASK (0x20U) #define GPT_IR_ROVIE_SHIFT (5U) +/*! ROVIE + * 0b0..Rollover interrupt is disabled. + * 0b1..Rollover interrupt enabled. + */ #define GPT_IR_ROVIE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_ROVIE_SHIFT)) & GPT_IR_ROVIE_MASK) +/*! @} */ /*! @name OCR - GPT Output Compare Register 1..GPT Output Compare Register 3 */ +/*! @{ */ #define GPT_OCR_COMP_MASK (0xFFFFFFFFU) #define GPT_OCR_COMP_SHIFT (0U) #define GPT_OCR_COMP(x) (((uint32_t)(((uint32_t)(x)) << GPT_OCR_COMP_SHIFT)) & GPT_OCR_COMP_MASK) +/*! @} */ /* The count of GPT_OCR */ #define GPT_OCR_COUNT (3U) /*! @name ICR - GPT Input Capture Register 1..GPT Input Capture Register 2 */ +/*! @{ */ #define GPT_ICR_CAPT_MASK (0xFFFFFFFFU) #define GPT_ICR_CAPT_SHIFT (0U) #define GPT_ICR_CAPT(x) (((uint32_t)(((uint32_t)(x)) << GPT_ICR_CAPT_SHIFT)) & GPT_ICR_CAPT_MASK) +/*! @} */ /* The count of GPT_ICR */ #define GPT_ICR_COUNT (2U) /*! @name CNT - GPT Counter Register */ +/*! @{ */ #define GPT_CNT_COUNT_MASK (0xFFFFFFFFU) #define GPT_CNT_COUNT_SHIFT (0U) #define GPT_CNT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << GPT_CNT_COUNT_SHIFT)) & GPT_CNT_COUNT_MASK) +/*! @} */ /*! @@ -11041,8 +16799,12 @@ typedef struct { */ /*! @name VERID - Version ID Register */ +/*! @{ */ #define I2S_VERID_FEATURE_MASK (0xFFFFU) #define I2S_VERID_FEATURE_SHIFT (0U) +/*! FEATURE - Feature Specification Number + * 0b0000000000000000..Standard feature set. + */ #define I2S_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << I2S_VERID_FEATURE_SHIFT)) & I2S_VERID_FEATURE_MASK) #define I2S_VERID_MINOR_MASK (0xFF0000U) #define I2S_VERID_MINOR_SHIFT (16U) @@ -11050,8 +16812,10 @@ typedef struct { #define I2S_VERID_MAJOR_MASK (0xFF000000U) #define I2S_VERID_MAJOR_SHIFT (24U) #define I2S_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << I2S_VERID_MAJOR_SHIFT)) & I2S_VERID_MAJOR_MASK) +/*! @} */ /*! @name PARAM - Parameter Register */ +/*! @{ */ #define I2S_PARAM_DATALINE_MASK (0xFU) #define I2S_PARAM_DATALINE_SHIFT (0U) #define I2S_PARAM_DATALINE(x) (((uint32_t)(((uint32_t)(x)) << I2S_PARAM_DATALINE_SHIFT)) & I2S_PARAM_DATALINE_MASK) @@ -11061,92 +16825,200 @@ typedef struct { #define I2S_PARAM_FRAME_MASK (0xF0000U) #define I2S_PARAM_FRAME_SHIFT (16U) #define I2S_PARAM_FRAME(x) (((uint32_t)(((uint32_t)(x)) << I2S_PARAM_FRAME_SHIFT)) & I2S_PARAM_FRAME_MASK) +/*! @} */ /*! @name TCSR - SAI Transmit Control Register */ +/*! @{ */ #define I2S_TCSR_FRDE_MASK (0x1U) #define I2S_TCSR_FRDE_SHIFT (0U) +/*! FRDE - FIFO Request DMA Enable + * 0b0..Disables the DMA request. + * 0b1..Enables the DMA request. + */ #define I2S_TCSR_FRDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRDE_SHIFT)) & I2S_TCSR_FRDE_MASK) #define I2S_TCSR_FWDE_MASK (0x2U) #define I2S_TCSR_FWDE_SHIFT (1U) +/*! FWDE - FIFO Warning DMA Enable + * 0b0..Disables the DMA request. + * 0b1..Enables the DMA request. + */ #define I2S_TCSR_FWDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWDE_SHIFT)) & I2S_TCSR_FWDE_MASK) #define I2S_TCSR_FRIE_MASK (0x100U) #define I2S_TCSR_FRIE_SHIFT (8U) +/*! FRIE - FIFO Request Interrupt Enable + * 0b0..Disables the interrupt. + * 0b1..Enables the interrupt. + */ #define I2S_TCSR_FRIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRIE_SHIFT)) & I2S_TCSR_FRIE_MASK) #define I2S_TCSR_FWIE_MASK (0x200U) #define I2S_TCSR_FWIE_SHIFT (9U) +/*! FWIE - FIFO Warning Interrupt Enable + * 0b0..Disables the interrupt. + * 0b1..Enables the interrupt. + */ #define I2S_TCSR_FWIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWIE_SHIFT)) & I2S_TCSR_FWIE_MASK) #define I2S_TCSR_FEIE_MASK (0x400U) #define I2S_TCSR_FEIE_SHIFT (10U) +/*! FEIE - FIFO Error Interrupt Enable + * 0b0..Disables the interrupt. + * 0b1..Enables the interrupt. + */ #define I2S_TCSR_FEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEIE_SHIFT)) & I2S_TCSR_FEIE_MASK) #define I2S_TCSR_SEIE_MASK (0x800U) #define I2S_TCSR_SEIE_SHIFT (11U) +/*! SEIE - Sync Error Interrupt Enable + * 0b0..Disables interrupt. + * 0b1..Enables interrupt. + */ #define I2S_TCSR_SEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEIE_SHIFT)) & I2S_TCSR_SEIE_MASK) #define I2S_TCSR_WSIE_MASK (0x1000U) #define I2S_TCSR_WSIE_SHIFT (12U) +/*! WSIE - Word Start Interrupt Enable + * 0b0..Disables interrupt. + * 0b1..Enables interrupt. + */ #define I2S_TCSR_WSIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSIE_SHIFT)) & I2S_TCSR_WSIE_MASK) #define I2S_TCSR_FRF_MASK (0x10000U) #define I2S_TCSR_FRF_SHIFT (16U) +/*! FRF - FIFO Request Flag + * 0b0..Transmit FIFO watermark has not been reached. + * 0b1..Transmit FIFO watermark has been reached. + */ #define I2S_TCSR_FRF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRF_SHIFT)) & I2S_TCSR_FRF_MASK) #define I2S_TCSR_FWF_MASK (0x20000U) #define I2S_TCSR_FWF_SHIFT (17U) +/*! FWF - FIFO Warning Flag + * 0b0..No enabled transmit FIFO is empty. + * 0b1..Enabled transmit FIFO is empty. + */ #define I2S_TCSR_FWF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWF_SHIFT)) & I2S_TCSR_FWF_MASK) #define I2S_TCSR_FEF_MASK (0x40000U) #define I2S_TCSR_FEF_SHIFT (18U) +/*! FEF - FIFO Error Flag + * 0b0..Transmit underrun not detected. + * 0b1..Transmit underrun detected. + */ #define I2S_TCSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEF_SHIFT)) & I2S_TCSR_FEF_MASK) #define I2S_TCSR_SEF_MASK (0x80000U) #define I2S_TCSR_SEF_SHIFT (19U) +/*! SEF - Sync Error Flag + * 0b0..Sync error not detected. + * 0b1..Frame sync error detected. + */ #define I2S_TCSR_SEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEF_SHIFT)) & I2S_TCSR_SEF_MASK) #define I2S_TCSR_WSF_MASK (0x100000U) #define I2S_TCSR_WSF_SHIFT (20U) +/*! WSF - Word Start Flag + * 0b0..Start of word not detected. + * 0b1..Start of word detected. + */ #define I2S_TCSR_WSF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSF_SHIFT)) & I2S_TCSR_WSF_MASK) #define I2S_TCSR_SR_MASK (0x1000000U) #define I2S_TCSR_SR_SHIFT (24U) +/*! SR - Software Reset + * 0b0..No effect. + * 0b1..Software reset. + */ #define I2S_TCSR_SR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SR_SHIFT)) & I2S_TCSR_SR_MASK) #define I2S_TCSR_FR_MASK (0x2000000U) #define I2S_TCSR_FR_SHIFT (25U) +/*! FR - FIFO Reset + * 0b0..No effect. + * 0b1..FIFO reset. + */ #define I2S_TCSR_FR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FR_SHIFT)) & I2S_TCSR_FR_MASK) #define I2S_TCSR_BCE_MASK (0x10000000U) #define I2S_TCSR_BCE_SHIFT (28U) +/*! BCE - Bit Clock Enable + * 0b0..Transmit bit clock is disabled. + * 0b1..Transmit bit clock is enabled. + */ #define I2S_TCSR_BCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_BCE_SHIFT)) & I2S_TCSR_BCE_MASK) #define I2S_TCSR_DBGE_MASK (0x20000000U) #define I2S_TCSR_DBGE_SHIFT (29U) +/*! DBGE - Debug Enable + * 0b0..Transmitter is disabled in Debug mode, after completing the current frame. + * 0b1..Transmitter is enabled in Debug mode. + */ #define I2S_TCSR_DBGE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_DBGE_SHIFT)) & I2S_TCSR_DBGE_MASK) #define I2S_TCSR_STOPE_MASK (0x40000000U) #define I2S_TCSR_STOPE_SHIFT (30U) +/*! STOPE - Stop Enable + * 0b0..Transmitter disabled in Stop mode. + * 0b1..Transmitter enabled in Stop mode. + */ #define I2S_TCSR_STOPE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_STOPE_SHIFT)) & I2S_TCSR_STOPE_MASK) #define I2S_TCSR_TE_MASK (0x80000000U) #define I2S_TCSR_TE_SHIFT (31U) +/*! TE - Transmitter Enable + * 0b0..Transmitter is disabled. + * 0b1..Transmitter is enabled, or transmitter has been disabled and has not yet reached end of frame. + */ #define I2S_TCSR_TE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_TE_SHIFT)) & I2S_TCSR_TE_MASK) +/*! @} */ /*! @name TCR1 - SAI Transmit Configuration 1 Register */ +/*! @{ */ #define I2S_TCR1_TFW_MASK (0x1FU) #define I2S_TCR1_TFW_SHIFT (0U) #define I2S_TCR1_TFW(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR1_TFW_SHIFT)) & I2S_TCR1_TFW_MASK) +/*! @} */ /*! @name TCR2 - SAI Transmit Configuration 2 Register */ +/*! @{ */ #define I2S_TCR2_DIV_MASK (0xFFU) #define I2S_TCR2_DIV_SHIFT (0U) #define I2S_TCR2_DIV(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_DIV_SHIFT)) & I2S_TCR2_DIV_MASK) #define I2S_TCR2_BCD_MASK (0x1000000U) #define I2S_TCR2_BCD_SHIFT (24U) +/*! BCD - Bit Clock Direction + * 0b0..Bit clock is generated externally in Slave mode. + * 0b1..Bit clock is generated internally in Master mode. + */ #define I2S_TCR2_BCD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCD_SHIFT)) & I2S_TCR2_BCD_MASK) #define I2S_TCR2_BCP_MASK (0x2000000U) #define I2S_TCR2_BCP_SHIFT (25U) +/*! BCP - Bit Clock Polarity + * 0b0..Bit clock is active high with drive outputs on rising edge and sample inputs on falling edge. + * 0b1..Bit clock is active low with drive outputs on falling edge and sample inputs on rising edge. + */ #define I2S_TCR2_BCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCP_SHIFT)) & I2S_TCR2_BCP_MASK) #define I2S_TCR2_MSEL_MASK (0xC000000U) #define I2S_TCR2_MSEL_SHIFT (26U) +/*! MSEL - MCLK Select + * 0b00..Bus Clock selected. + * 0b01..Master Clock (MCLK) 1 option selected. + * 0b10..Master Clock (MCLK) 2 option selected. + * 0b11..Master Clock (MCLK) 3 option selected. + */ #define I2S_TCR2_MSEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_MSEL_SHIFT)) & I2S_TCR2_MSEL_MASK) #define I2S_TCR2_BCI_MASK (0x10000000U) #define I2S_TCR2_BCI_SHIFT (28U) +/*! BCI - Bit Clock Input + * 0b0..No effect. + * 0b1..Internal logic is clocked as if bit clock was externally generated. + */ #define I2S_TCR2_BCI(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCI_SHIFT)) & I2S_TCR2_BCI_MASK) #define I2S_TCR2_BCS_MASK (0x20000000U) #define I2S_TCR2_BCS_SHIFT (29U) +/*! BCS - Bit Clock Swap + * 0b0..Use the normal bit clock source. + * 0b1..Swap the bit clock source. + */ #define I2S_TCR2_BCS(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCS_SHIFT)) & I2S_TCR2_BCS_MASK) #define I2S_TCR2_SYNC_MASK (0xC0000000U) #define I2S_TCR2_SYNC_SHIFT (30U) +/*! SYNC - Synchronous Mode + * 0b00..Asynchronous mode. + * 0b01..Synchronous with receiver. + * 0b10..Reserved. + * 0b11..Reserved. + */ #define I2S_TCR2_SYNC(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_SYNC_SHIFT)) & I2S_TCR2_SYNC_MASK) +/*! @} */ /*! @name TCR3 - SAI Transmit Configuration 3 Register */ +/*! @{ */ #define I2S_TCR3_WDFL_MASK (0x1FU) #define I2S_TCR3_WDFL_SHIFT (0U) #define I2S_TCR3_WDFL(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_WDFL_SHIFT)) & I2S_TCR3_WDFL_MASK) @@ -11156,25 +17028,51 @@ typedef struct { #define I2S_TCR3_CFR_MASK (0xF000000U) #define I2S_TCR3_CFR_SHIFT (24U) #define I2S_TCR3_CFR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_CFR_SHIFT)) & I2S_TCR3_CFR_MASK) +/*! @} */ /*! @name TCR4 - SAI Transmit Configuration 4 Register */ +/*! @{ */ #define I2S_TCR4_FSD_MASK (0x1U) #define I2S_TCR4_FSD_SHIFT (0U) +/*! FSD - Frame Sync Direction + * 0b0..Frame sync is generated externally in Slave mode. + * 0b1..Frame sync is generated internally in Master mode. + */ #define I2S_TCR4_FSD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSD_SHIFT)) & I2S_TCR4_FSD_MASK) #define I2S_TCR4_FSP_MASK (0x2U) #define I2S_TCR4_FSP_SHIFT (1U) +/*! FSP - Frame Sync Polarity + * 0b0..Frame sync is active high. + * 0b1..Frame sync is active low. + */ #define I2S_TCR4_FSP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSP_SHIFT)) & I2S_TCR4_FSP_MASK) #define I2S_TCR4_ONDEM_MASK (0x4U) #define I2S_TCR4_ONDEM_SHIFT (2U) +/*! ONDEM - On Demand Mode + * 0b0..Internal frame sync is generated continuously. + * 0b1..Internal frame sync is generated when the FIFO warning flag is clear. + */ #define I2S_TCR4_ONDEM(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_ONDEM_SHIFT)) & I2S_TCR4_ONDEM_MASK) #define I2S_TCR4_FSE_MASK (0x8U) #define I2S_TCR4_FSE_SHIFT (3U) +/*! FSE - Frame Sync Early + * 0b0..Frame sync asserts with the first bit of the frame. + * 0b1..Frame sync asserts one bit before the first bit of the frame. + */ #define I2S_TCR4_FSE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSE_SHIFT)) & I2S_TCR4_FSE_MASK) #define I2S_TCR4_MF_MASK (0x10U) #define I2S_TCR4_MF_SHIFT (4U) +/*! MF - MSB First + * 0b0..LSB is transmitted first. + * 0b1..MSB is transmitted first. + */ #define I2S_TCR4_MF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_MF_SHIFT)) & I2S_TCR4_MF_MASK) #define I2S_TCR4_CHMOD_MASK (0x20U) #define I2S_TCR4_CHMOD_SHIFT (5U) +/*! CHMOD - Channel Mode + * 0b0..TDM mode, transmit data pins are tri-stated when slots are masked or channels are disabled. + * 0b1..Output mode, transmit data pins are never tri-stated and will output zero when slots are masked or channels are disabled. + */ #define I2S_TCR4_CHMOD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_CHMOD_SHIFT)) & I2S_TCR4_CHMOD_MASK) #define I2S_TCR4_SYWD_MASK (0x1F00U) #define I2S_TCR4_SYWD_SHIFT (8U) @@ -11184,15 +17082,33 @@ typedef struct { #define I2S_TCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FRSZ_SHIFT)) & I2S_TCR4_FRSZ_MASK) #define I2S_TCR4_FPACK_MASK (0x3000000U) #define I2S_TCR4_FPACK_SHIFT (24U) +/*! FPACK - FIFO Packing Mode + * 0b00..FIFO packing is disabled + * 0b01..Reserved + * 0b10..8-bit FIFO packing is enabled + * 0b11..16-bit FIFO packing is enabled + */ #define I2S_TCR4_FPACK(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FPACK_SHIFT)) & I2S_TCR4_FPACK_MASK) #define I2S_TCR4_FCOMB_MASK (0xC000000U) #define I2S_TCR4_FCOMB_SHIFT (26U) +/*! FCOMB - FIFO Combine Mode + * 0b00..FIFO combine mode disabled. + * 0b01..FIFO combine mode enabled on FIFO reads (from transmit shift registers). + * 0b10..FIFO combine mode enabled on FIFO writes (by software). + * 0b11..FIFO combine mode enabled on FIFO reads (from transmit shift registers) and writes (by software). + */ #define I2S_TCR4_FCOMB(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FCOMB_SHIFT)) & I2S_TCR4_FCOMB_MASK) #define I2S_TCR4_FCONT_MASK (0x10000000U) #define I2S_TCR4_FCONT_SHIFT (28U) +/*! FCONT - FIFO Continue on Error + * 0b0..On FIFO error, the SAI will continue from the start of the next frame after the FIFO error flag has been cleared. + * 0b1..On FIFO error, the SAI will continue from the same word that caused the FIFO error to set after the FIFO warning flag has been cleared. + */ #define I2S_TCR4_FCONT(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FCONT_SHIFT)) & I2S_TCR4_FCONT_MASK) +/*! @} */ /*! @name TCR5 - SAI Transmit Configuration 5 Register */ +/*! @{ */ #define I2S_TCR5_FBT_MASK (0x1F00U) #define I2S_TCR5_FBT_SHIFT (8U) #define I2S_TCR5_FBT(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_FBT_SHIFT)) & I2S_TCR5_FBT_MASK) @@ -11202,16 +17118,20 @@ typedef struct { #define I2S_TCR5_WNW_MASK (0x1F000000U) #define I2S_TCR5_WNW_SHIFT (24U) #define I2S_TCR5_WNW(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_WNW_SHIFT)) & I2S_TCR5_WNW_MASK) +/*! @} */ /*! @name TDR - SAI Transmit Data Register */ +/*! @{ */ #define I2S_TDR_TDR_MASK (0xFFFFFFFFU) #define I2S_TDR_TDR_SHIFT (0U) #define I2S_TDR_TDR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TDR_TDR_SHIFT)) & I2S_TDR_TDR_MASK) +/*! @} */ /* The count of I2S_TDR */ #define I2S_TDR_COUNT (4U) /*! @name TFR - SAI Transmit FIFO Register */ +/*! @{ */ #define I2S_TFR_RFP_MASK (0x3FU) #define I2S_TFR_RFP_SHIFT (0U) #define I2S_TFR_RFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TFR_RFP_SHIFT)) & I2S_TFR_RFP_MASK) @@ -11220,101 +17140,219 @@ typedef struct { #define I2S_TFR_WFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TFR_WFP_SHIFT)) & I2S_TFR_WFP_MASK) #define I2S_TFR_WCP_MASK (0x80000000U) #define I2S_TFR_WCP_SHIFT (31U) +/*! WCP - Write Channel Pointer + * 0b0..No effect. + * 0b1..FIFO combine is enabled for FIFO writes and this FIFO will be written on the next FIFO write. + */ #define I2S_TFR_WCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TFR_WCP_SHIFT)) & I2S_TFR_WCP_MASK) +/*! @} */ /* The count of I2S_TFR */ #define I2S_TFR_COUNT (4U) /*! @name TMR - SAI Transmit Mask Register */ +/*! @{ */ #define I2S_TMR_TWM_MASK (0xFFFFFFFFU) #define I2S_TMR_TWM_SHIFT (0U) +/*! TWM - Transmit Word Mask + * 0b00000000000000000000000000000000..Word N is enabled. + * 0b00000000000000000000000000000001..Word N is masked. The transmit data pins are tri-stated or drive zero when masked. + */ #define I2S_TMR_TWM(x) (((uint32_t)(((uint32_t)(x)) << I2S_TMR_TWM_SHIFT)) & I2S_TMR_TWM_MASK) +/*! @} */ /*! @name RCSR - SAI Receive Control Register */ +/*! @{ */ #define I2S_RCSR_FRDE_MASK (0x1U) #define I2S_RCSR_FRDE_SHIFT (0U) +/*! FRDE - FIFO Request DMA Enable + * 0b0..Disables the DMA request. + * 0b1..Enables the DMA request. + */ #define I2S_RCSR_FRDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRDE_SHIFT)) & I2S_RCSR_FRDE_MASK) #define I2S_RCSR_FWDE_MASK (0x2U) #define I2S_RCSR_FWDE_SHIFT (1U) +/*! FWDE - FIFO Warning DMA Enable + * 0b0..Disables the DMA request. + * 0b1..Enables the DMA request. + */ #define I2S_RCSR_FWDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWDE_SHIFT)) & I2S_RCSR_FWDE_MASK) #define I2S_RCSR_FRIE_MASK (0x100U) #define I2S_RCSR_FRIE_SHIFT (8U) +/*! FRIE - FIFO Request Interrupt Enable + * 0b0..Disables the interrupt. + * 0b1..Enables the interrupt. + */ #define I2S_RCSR_FRIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRIE_SHIFT)) & I2S_RCSR_FRIE_MASK) #define I2S_RCSR_FWIE_MASK (0x200U) #define I2S_RCSR_FWIE_SHIFT (9U) +/*! FWIE - FIFO Warning Interrupt Enable + * 0b0..Disables the interrupt. + * 0b1..Enables the interrupt. + */ #define I2S_RCSR_FWIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWIE_SHIFT)) & I2S_RCSR_FWIE_MASK) #define I2S_RCSR_FEIE_MASK (0x400U) #define I2S_RCSR_FEIE_SHIFT (10U) +/*! FEIE - FIFO Error Interrupt Enable + * 0b0..Disables the interrupt. + * 0b1..Enables the interrupt. + */ #define I2S_RCSR_FEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEIE_SHIFT)) & I2S_RCSR_FEIE_MASK) #define I2S_RCSR_SEIE_MASK (0x800U) #define I2S_RCSR_SEIE_SHIFT (11U) +/*! SEIE - Sync Error Interrupt Enable + * 0b0..Disables interrupt. + * 0b1..Enables interrupt. + */ #define I2S_RCSR_SEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEIE_SHIFT)) & I2S_RCSR_SEIE_MASK) #define I2S_RCSR_WSIE_MASK (0x1000U) #define I2S_RCSR_WSIE_SHIFT (12U) +/*! WSIE - Word Start Interrupt Enable + * 0b0..Disables interrupt. + * 0b1..Enables interrupt. + */ #define I2S_RCSR_WSIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSIE_SHIFT)) & I2S_RCSR_WSIE_MASK) #define I2S_RCSR_FRF_MASK (0x10000U) #define I2S_RCSR_FRF_SHIFT (16U) +/*! FRF - FIFO Request Flag + * 0b0..Receive FIFO watermark not reached. + * 0b1..Receive FIFO watermark has been reached. + */ #define I2S_RCSR_FRF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRF_SHIFT)) & I2S_RCSR_FRF_MASK) #define I2S_RCSR_FWF_MASK (0x20000U) #define I2S_RCSR_FWF_SHIFT (17U) +/*! FWF - FIFO Warning Flag + * 0b0..No enabled receive FIFO is full. + * 0b1..Enabled receive FIFO is full. + */ #define I2S_RCSR_FWF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWF_SHIFT)) & I2S_RCSR_FWF_MASK) #define I2S_RCSR_FEF_MASK (0x40000U) #define I2S_RCSR_FEF_SHIFT (18U) +/*! FEF - FIFO Error Flag + * 0b0..Receive overflow not detected. + * 0b1..Receive overflow detected. + */ #define I2S_RCSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEF_SHIFT)) & I2S_RCSR_FEF_MASK) #define I2S_RCSR_SEF_MASK (0x80000U) #define I2S_RCSR_SEF_SHIFT (19U) +/*! SEF - Sync Error Flag + * 0b0..Sync error not detected. + * 0b1..Frame sync error detected. + */ #define I2S_RCSR_SEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEF_SHIFT)) & I2S_RCSR_SEF_MASK) #define I2S_RCSR_WSF_MASK (0x100000U) #define I2S_RCSR_WSF_SHIFT (20U) +/*! WSF - Word Start Flag + * 0b0..Start of word not detected. + * 0b1..Start of word detected. + */ #define I2S_RCSR_WSF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSF_SHIFT)) & I2S_RCSR_WSF_MASK) #define I2S_RCSR_SR_MASK (0x1000000U) #define I2S_RCSR_SR_SHIFT (24U) +/*! SR - Software Reset + * 0b0..No effect. + * 0b1..Software reset. + */ #define I2S_RCSR_SR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SR_SHIFT)) & I2S_RCSR_SR_MASK) #define I2S_RCSR_FR_MASK (0x2000000U) #define I2S_RCSR_FR_SHIFT (25U) +/*! FR - FIFO Reset + * 0b0..No effect. + * 0b1..FIFO reset. + */ #define I2S_RCSR_FR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FR_SHIFT)) & I2S_RCSR_FR_MASK) #define I2S_RCSR_BCE_MASK (0x10000000U) #define I2S_RCSR_BCE_SHIFT (28U) +/*! BCE - Bit Clock Enable + * 0b0..Receive bit clock is disabled. + * 0b1..Receive bit clock is enabled. + */ #define I2S_RCSR_BCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_BCE_SHIFT)) & I2S_RCSR_BCE_MASK) #define I2S_RCSR_DBGE_MASK (0x20000000U) #define I2S_RCSR_DBGE_SHIFT (29U) +/*! DBGE - Debug Enable + * 0b0..Receiver is disabled in Debug mode, after completing the current frame. + * 0b1..Receiver is enabled in Debug mode. + */ #define I2S_RCSR_DBGE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_DBGE_SHIFT)) & I2S_RCSR_DBGE_MASK) #define I2S_RCSR_STOPE_MASK (0x40000000U) #define I2S_RCSR_STOPE_SHIFT (30U) +/*! STOPE - Stop Enable + * 0b0..Receiver disabled in Stop mode. + * 0b1..Receiver enabled in Stop mode. + */ #define I2S_RCSR_STOPE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_STOPE_SHIFT)) & I2S_RCSR_STOPE_MASK) #define I2S_RCSR_RE_MASK (0x80000000U) #define I2S_RCSR_RE_SHIFT (31U) +/*! RE - Receiver Enable + * 0b0..Receiver is disabled. + * 0b1..Receiver is enabled, or receiver has been disabled and has not yet reached end of frame. + */ #define I2S_RCSR_RE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_RE_SHIFT)) & I2S_RCSR_RE_MASK) +/*! @} */ /*! @name RCR1 - SAI Receive Configuration 1 Register */ +/*! @{ */ #define I2S_RCR1_RFW_MASK (0x1FU) #define I2S_RCR1_RFW_SHIFT (0U) #define I2S_RCR1_RFW(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR1_RFW_SHIFT)) & I2S_RCR1_RFW_MASK) +/*! @} */ /*! @name RCR2 - SAI Receive Configuration 2 Register */ +/*! @{ */ #define I2S_RCR2_DIV_MASK (0xFFU) #define I2S_RCR2_DIV_SHIFT (0U) #define I2S_RCR2_DIV(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_DIV_SHIFT)) & I2S_RCR2_DIV_MASK) #define I2S_RCR2_BCD_MASK (0x1000000U) #define I2S_RCR2_BCD_SHIFT (24U) +/*! BCD - Bit Clock Direction + * 0b0..Bit clock is generated externally in Slave mode. + * 0b1..Bit clock is generated internally in Master mode. + */ #define I2S_RCR2_BCD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCD_SHIFT)) & I2S_RCR2_BCD_MASK) #define I2S_RCR2_BCP_MASK (0x2000000U) #define I2S_RCR2_BCP_SHIFT (25U) +/*! BCP - Bit Clock Polarity + * 0b0..Bit Clock is active high with drive outputs on rising edge and sample inputs on falling edge. + * 0b1..Bit Clock is active low with drive outputs on falling edge and sample inputs on rising edge. + */ #define I2S_RCR2_BCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCP_SHIFT)) & I2S_RCR2_BCP_MASK) #define I2S_RCR2_MSEL_MASK (0xC000000U) #define I2S_RCR2_MSEL_SHIFT (26U) +/*! MSEL - MCLK Select + * 0b00..Bus Clock selected. + * 0b01..Master Clock (MCLK) 1 option selected. + * 0b10..Master Clock (MCLK) 2 option selected. + * 0b11..Master Clock (MCLK) 3 option selected. + */ #define I2S_RCR2_MSEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_MSEL_SHIFT)) & I2S_RCR2_MSEL_MASK) #define I2S_RCR2_BCI_MASK (0x10000000U) #define I2S_RCR2_BCI_SHIFT (28U) +/*! BCI - Bit Clock Input + * 0b0..No effect. + * 0b1..Internal logic is clocked as if bit clock was externally generated. + */ #define I2S_RCR2_BCI(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCI_SHIFT)) & I2S_RCR2_BCI_MASK) #define I2S_RCR2_BCS_MASK (0x20000000U) #define I2S_RCR2_BCS_SHIFT (29U) +/*! BCS - Bit Clock Swap + * 0b0..Use the normal bit clock source. + * 0b1..Swap the bit clock source. + */ #define I2S_RCR2_BCS(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCS_SHIFT)) & I2S_RCR2_BCS_MASK) #define I2S_RCR2_SYNC_MASK (0xC0000000U) #define I2S_RCR2_SYNC_SHIFT (30U) +/*! SYNC - Synchronous Mode + * 0b00..Asynchronous mode. + * 0b01..Synchronous with transmitter. + * 0b10..Reserved. + * 0b11..Reserved. + */ #define I2S_RCR2_SYNC(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_SYNC_SHIFT)) & I2S_RCR2_SYNC_MASK) +/*! @} */ /*! @name RCR3 - SAI Receive Configuration 3 Register */ +/*! @{ */ #define I2S_RCR3_WDFL_MASK (0x1FU) #define I2S_RCR3_WDFL_SHIFT (0U) #define I2S_RCR3_WDFL(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_WDFL_SHIFT)) & I2S_RCR3_WDFL_MASK) @@ -11324,22 +17362,44 @@ typedef struct { #define I2S_RCR3_CFR_MASK (0xF000000U) #define I2S_RCR3_CFR_SHIFT (24U) #define I2S_RCR3_CFR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_CFR_SHIFT)) & I2S_RCR3_CFR_MASK) +/*! @} */ /*! @name RCR4 - SAI Receive Configuration 4 Register */ +/*! @{ */ #define I2S_RCR4_FSD_MASK (0x1U) #define I2S_RCR4_FSD_SHIFT (0U) +/*! FSD - Frame Sync Direction + * 0b0..Frame Sync is generated externally in Slave mode. + * 0b1..Frame Sync is generated internally in Master mode. + */ #define I2S_RCR4_FSD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSD_SHIFT)) & I2S_RCR4_FSD_MASK) #define I2S_RCR4_FSP_MASK (0x2U) #define I2S_RCR4_FSP_SHIFT (1U) +/*! FSP - Frame Sync Polarity + * 0b0..Frame sync is active high. + * 0b1..Frame sync is active low. + */ #define I2S_RCR4_FSP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSP_SHIFT)) & I2S_RCR4_FSP_MASK) #define I2S_RCR4_ONDEM_MASK (0x4U) #define I2S_RCR4_ONDEM_SHIFT (2U) +/*! ONDEM - On Demand Mode + * 0b0..Internal frame sync is generated continuously. + * 0b1..Internal frame sync is generated when the FIFO warning flag is clear. + */ #define I2S_RCR4_ONDEM(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_ONDEM_SHIFT)) & I2S_RCR4_ONDEM_MASK) #define I2S_RCR4_FSE_MASK (0x8U) #define I2S_RCR4_FSE_SHIFT (3U) +/*! FSE - Frame Sync Early + * 0b0..Frame sync asserts with the first bit of the frame. + * 0b1..Frame sync asserts one bit before the first bit of the frame. + */ #define I2S_RCR4_FSE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSE_SHIFT)) & I2S_RCR4_FSE_MASK) #define I2S_RCR4_MF_MASK (0x10U) #define I2S_RCR4_MF_SHIFT (4U) +/*! MF - MSB First + * 0b0..LSB is received first. + * 0b1..MSB is received first. + */ #define I2S_RCR4_MF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_MF_SHIFT)) & I2S_RCR4_MF_MASK) #define I2S_RCR4_SYWD_MASK (0x1F00U) #define I2S_RCR4_SYWD_SHIFT (8U) @@ -11349,15 +17409,33 @@ typedef struct { #define I2S_RCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FRSZ_SHIFT)) & I2S_RCR4_FRSZ_MASK) #define I2S_RCR4_FPACK_MASK (0x3000000U) #define I2S_RCR4_FPACK_SHIFT (24U) +/*! FPACK - FIFO Packing Mode + * 0b00..FIFO packing is disabled + * 0b01..Reserved. + * 0b10..8-bit FIFO packing is enabled + * 0b11..16-bit FIFO packing is enabled + */ #define I2S_RCR4_FPACK(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FPACK_SHIFT)) & I2S_RCR4_FPACK_MASK) #define I2S_RCR4_FCOMB_MASK (0xC000000U) #define I2S_RCR4_FCOMB_SHIFT (26U) +/*! FCOMB - FIFO Combine Mode + * 0b00..FIFO combine mode disabled. + * 0b01..FIFO combine mode enabled on FIFO writes (from receive shift registers). + * 0b10..FIFO combine mode enabled on FIFO reads (by software). + * 0b11..FIFO combine mode enabled on FIFO writes (from receive shift registers) and reads (by software). + */ #define I2S_RCR4_FCOMB(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FCOMB_SHIFT)) & I2S_RCR4_FCOMB_MASK) #define I2S_RCR4_FCONT_MASK (0x10000000U) #define I2S_RCR4_FCONT_SHIFT (28U) +/*! FCONT - FIFO Continue on Error + * 0b0..On FIFO error, the SAI will continue from the start of the next frame after the FIFO error flag has been cleared. + * 0b1..On FIFO error, the SAI will continue from the same word that caused the FIFO error to set after the FIFO warning flag has been cleared. + */ #define I2S_RCR4_FCONT(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FCONT_SHIFT)) & I2S_RCR4_FCONT_MASK) +/*! @} */ /*! @name RCR5 - SAI Receive Configuration 5 Register */ +/*! @{ */ #define I2S_RCR5_FBT_MASK (0x1F00U) #define I2S_RCR5_FBT_SHIFT (8U) #define I2S_RCR5_FBT(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_FBT_SHIFT)) & I2S_RCR5_FBT_MASK) @@ -11367,33 +17445,48 @@ typedef struct { #define I2S_RCR5_WNW_MASK (0x1F000000U) #define I2S_RCR5_WNW_SHIFT (24U) #define I2S_RCR5_WNW(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_WNW_SHIFT)) & I2S_RCR5_WNW_MASK) +/*! @} */ /*! @name RDR - SAI Receive Data Register */ +/*! @{ */ #define I2S_RDR_RDR_MASK (0xFFFFFFFFU) #define I2S_RDR_RDR_SHIFT (0U) #define I2S_RDR_RDR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RDR_RDR_SHIFT)) & I2S_RDR_RDR_MASK) +/*! @} */ /* The count of I2S_RDR */ #define I2S_RDR_COUNT (4U) /*! @name RFR - SAI Receive FIFO Register */ +/*! @{ */ #define I2S_RFR_RFP_MASK (0x3FU) #define I2S_RFR_RFP_SHIFT (0U) #define I2S_RFR_RFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RFR_RFP_SHIFT)) & I2S_RFR_RFP_MASK) #define I2S_RFR_RCP_MASK (0x8000U) #define I2S_RFR_RCP_SHIFT (15U) +/*! RCP - Receive Channel Pointer + * 0b0..No effect. + * 0b1..FIFO combine is enabled for FIFO reads and this FIFO will be read on the next FIFO read. + */ #define I2S_RFR_RCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RFR_RCP_SHIFT)) & I2S_RFR_RCP_MASK) #define I2S_RFR_WFP_MASK (0x3F0000U) #define I2S_RFR_WFP_SHIFT (16U) #define I2S_RFR_WFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RFR_WFP_SHIFT)) & I2S_RFR_WFP_MASK) +/*! @} */ /* The count of I2S_RFR */ #define I2S_RFR_COUNT (4U) /*! @name RMR - SAI Receive Mask Register */ +/*! @{ */ #define I2S_RMR_RWM_MASK (0xFFFFFFFFU) #define I2S_RMR_RWM_SHIFT (0U) +/*! RWM - Receive Word Mask + * 0b00000000000000000000000000000000..Word N is enabled. + * 0b00000000000000000000000000000001..Word N is masked. + */ #define I2S_RMR_RWM(x) (((uint32_t)(((uint32_t)(x)) << I2S_RMR_RWM_SHIFT)) & I2S_RMR_RWM_MASK) +/*! @} */ /*! @@ -11454,49 +17547,118 @@ typedef struct { */ /*! @name SW_MUX_CTL_PAD - SW_MUX_CTL_PAD_GPIO_EMC_00 SW MUX Control Register..SW_MUX_CTL_PAD_GPIO_SD_B1_11 SW MUX Control Register */ +/*! @{ */ #define IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_MASK (0x7U) #define IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_SHIFT (0U) +/*! MUX_MODE - MUX Mode Select Field. + * 0b000..Select mux mode: ALT0 mux port: LPI2C4_SCL of instance: lpi2c4 + * 0b001..Select mux mode: ALT1 mux port: CCM_PMIC_READY of instance: ccm + * 0b010..Select mux mode: ALT2 mux port: LPUART1_TX of instance: lpuart1 + * 0b011..Select mux mode: ALT3 mux port: WDOG2_WDOG_B of instance: wdog2 + * 0b100..Select mux mode: ALT4 mux port: FLEXPWM1_PWMX02 of instance: flexpwm1 + * 0b101..Select mux mode: ALT5 mux port: GPIO1_IO12 of instance: gpio1 + * 0b110..Select mux mode: ALT6 mux port: ENET_1588_EVENT1_OUT of instance: enet + * 0b111..Select mux mode: ALT7 mux port: NMI_GLUE_NMI of instance: nmi_glue + */ #define IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_SHIFT)) & IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_MASK) #define IOMUXC_SW_MUX_CTL_PAD_SION_MASK (0x10U) #define IOMUXC_SW_MUX_CTL_PAD_SION_SHIFT (4U) +/*! SION - Software Input On Field. + * 0b1..Force input path of pad GPIO_SD_B1_11 + * 0b0..Input Path is determined by functionality + */ #define IOMUXC_SW_MUX_CTL_PAD_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_MUX_CTL_PAD_SION_SHIFT)) & IOMUXC_SW_MUX_CTL_PAD_SION_MASK) +/*! @} */ /* The count of IOMUXC_SW_MUX_CTL_PAD */ #define IOMUXC_SW_MUX_CTL_PAD_COUNT (124U) /*! @name SW_PAD_CTL_PAD - SW_PAD_CTL_PAD_GPIO_EMC_00 SW PAD Control Register..SW_PAD_CTL_PAD_GPIO_SD_B1_11 SW PAD Control Register */ +/*! @{ */ #define IOMUXC_SW_PAD_CTL_PAD_SRE_MASK (0x1U) #define IOMUXC_SW_PAD_CTL_PAD_SRE_SHIFT (0U) +/*! SRE - Slew Rate Field + * 0b0..Slow Slew Rate + * 0b1..Fast Slew Rate + */ #define IOMUXC_SW_PAD_CTL_PAD_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_SRE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_SRE_MASK) #define IOMUXC_SW_PAD_CTL_PAD_DSE_MASK (0x38U) #define IOMUXC_SW_PAD_CTL_PAD_DSE_SHIFT (3U) +/*! DSE - Drive Strength Field + * 0b000..output driver disabled; + * 0b001..R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + * 0b010..R0/2 + * 0b011..R0/3 + * 0b100..R0/4 + * 0b101..R0/5 + * 0b110..R0/6 + * 0b111..R0/7 + */ #define IOMUXC_SW_PAD_CTL_PAD_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_DSE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_DSE_MASK) #define IOMUXC_SW_PAD_CTL_PAD_SPEED_MASK (0xC0U) #define IOMUXC_SW_PAD_CTL_PAD_SPEED_SHIFT (6U) +/*! SPEED - Speed Field + * 0b00..low(50MHz) + * 0b01..medium(100MHz) + * 0b10..medium(100MHz) + * 0b11..max(200MHz) + */ #define IOMUXC_SW_PAD_CTL_PAD_SPEED(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_SPEED_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_SPEED_MASK) #define IOMUXC_SW_PAD_CTL_PAD_ODE_MASK (0x800U) #define IOMUXC_SW_PAD_CTL_PAD_ODE_SHIFT (11U) +/*! ODE - Open Drain Enable Field + * 0b0..Open Drain Disabled + * 0b1..Open Drain Enabled + */ #define IOMUXC_SW_PAD_CTL_PAD_ODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_ODE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_ODE_MASK) #define IOMUXC_SW_PAD_CTL_PAD_PKE_MASK (0x1000U) #define IOMUXC_SW_PAD_CTL_PAD_PKE_SHIFT (12U) +/*! PKE - Pull / Keep Enable Field + * 0b0..Pull/Keeper Disabled + * 0b1..Pull/Keeper Enabled + */ #define IOMUXC_SW_PAD_CTL_PAD_PKE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_PKE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_PKE_MASK) #define IOMUXC_SW_PAD_CTL_PAD_PUE_MASK (0x2000U) #define IOMUXC_SW_PAD_CTL_PAD_PUE_SHIFT (13U) +/*! PUE - Pull / Keep Select Field + * 0b0..Keeper + * 0b1..Pull + */ #define IOMUXC_SW_PAD_CTL_PAD_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_PUE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_PUE_MASK) #define IOMUXC_SW_PAD_CTL_PAD_PUS_MASK (0xC000U) #define IOMUXC_SW_PAD_CTL_PAD_PUS_SHIFT (14U) +/*! PUS - Pull Up / Down Config. Field + * 0b00..100K Ohm Pull Down + * 0b01..47K Ohm Pull Up + * 0b10..100K Ohm Pull Up + * 0b11..22K Ohm Pull Up + */ #define IOMUXC_SW_PAD_CTL_PAD_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_PUS_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_PUS_MASK) #define IOMUXC_SW_PAD_CTL_PAD_HYS_MASK (0x10000U) #define IOMUXC_SW_PAD_CTL_PAD_HYS_SHIFT (16U) +/*! HYS - Hyst. Enable Field + * 0b0..Hysteresis Disabled + * 0b1..Hysteresis Enabled + */ #define IOMUXC_SW_PAD_CTL_PAD_HYS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_HYS_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_HYS_MASK) +/*! @} */ /* The count of IOMUXC_SW_PAD_CTL_PAD */ #define IOMUXC_SW_PAD_CTL_PAD_COUNT (124U) /*! @name SELECT_INPUT - ANATOP_USB_OTG1_ID_SELECT_INPUT DAISY Register..XBAR1_IN23_SELECT_INPUT DAISY Register */ +/*! @{ */ #define IOMUXC_SELECT_INPUT_DAISY_MASK (0x7U) /* Merged from fields with different position or width, of widths (1, 2, 3), largest definition used */ #define IOMUXC_SELECT_INPUT_DAISY_SHIFT (0U) +/*! DAISY - Selecting Pads Involved in Daisy Chain. + * 0b000..Selecting Pad: GPIO_SD_B1_03 for Mode: ALT6 + * 0b001..Selecting Pad: GPIO_AD_B0_12 for Mode: ALT1 + * 0b010..Selecting Pad: GPIO_AD_B1_01 for Mode: ALT4 + * 0b011..Selecting Pad: GPIO_AD_B1_08 for Mode: ALT3 + * 0b100..Selecting Pad: GPIO_EMC_32 for Mode: ALT3 + */ #define IOMUXC_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SELECT_INPUT_DAISY_SHIFT)) & IOMUXC_SELECT_INPUT_DAISY_MASK) /* Merged from fields with different position or width, of widths (1, 2, 3), largest definition used */ +/*! @} */ /* The count of IOMUXC_SELECT_INPUT */ #define IOMUXC_SELECT_INPUT_COUNT (154U) @@ -11571,542 +17733,1266 @@ typedef struct { */ /*! @name GPR1 - GPR1 General Purpose Register */ +/*! @{ */ #define IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL_MASK (0x7U) #define IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL_SHIFT (0U) +/*! SAI1_MCLK1_SEL + * 0b000..ccm.ssi1_clk_root + * 0b001..ccm.ssi2_clk_root + * 0b010..ccm.ssi3_clk_root + * 0b011..iomux.sai1_ipg_clk_sai_mclk + * 0b100..iomux.sai2_ipg_clk_sai_mclk + * 0b101..iomux.sai3_ipg_clk_sai_mclk + * 0b110..Reserved + * 0b111..Reserved + */ #define IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL_SHIFT)) & IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL_MASK) #define IOMUXC_GPR_GPR1_SAI1_MCLK2_SEL_MASK (0x38U) #define IOMUXC_GPR_GPR1_SAI1_MCLK2_SEL_SHIFT (3U) +/*! SAI1_MCLK2_SEL + * 0b000..ccm.ssi1_clk_root + * 0b001..ccm.ssi2_clk_root + * 0b010..ccm.ssi3_clk_root + * 0b011..iomux.sai1_ipg_clk_sai_mclk + * 0b100..iomux.sai2_ipg_clk_sai_mclk + * 0b101..iomux.sai3_ipg_clk_sai_mclk + * 0b110..Reserved + * 0b111..Reserved + */ #define IOMUXC_GPR_GPR1_SAI1_MCLK2_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI1_MCLK2_SEL_SHIFT)) & IOMUXC_GPR_GPR1_SAI1_MCLK2_SEL_MASK) #define IOMUXC_GPR_GPR1_SAI1_MCLK3_SEL_MASK (0xC0U) #define IOMUXC_GPR_GPR1_SAI1_MCLK3_SEL_SHIFT (6U) +/*! SAI1_MCLK3_SEL + * 0b00..ccm.spdif0_clk_root + * 0b01..iomux.spdif_tx_clk2 + * 0b10..spdif.spdif_srclk + * 0b11..spdif.spdif_outclock + */ #define IOMUXC_GPR_GPR1_SAI1_MCLK3_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI1_MCLK3_SEL_SHIFT)) & IOMUXC_GPR_GPR1_SAI1_MCLK3_SEL_MASK) #define IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL_MASK (0x300U) #define IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL_SHIFT (8U) +/*! SAI2_MCLK3_SEL + * 0b00..ccm.spdif0_clk_root + * 0b01..iomux.spdif_tx_clk2 + * 0b10..spdif.spdif_srclk + * 0b11..spdif.spdif_outclock + */ #define IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL_SHIFT)) & IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL_MASK) #define IOMUXC_GPR_GPR1_SAI3_MCLK3_SEL_MASK (0xC00U) #define IOMUXC_GPR_GPR1_SAI3_MCLK3_SEL_SHIFT (10U) +/*! SAI3_MCLK3_SEL + * 0b00..ccm.spdif0_clk_root + * 0b01..iomux.spdif_tx_clk2 + * 0b10..spdif.spdif_srclk + * 0b11..spdif.spdif_outclock + */ #define IOMUXC_GPR_GPR1_SAI3_MCLK3_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI3_MCLK3_SEL_SHIFT)) & IOMUXC_GPR_GPR1_SAI3_MCLK3_SEL_MASK) #define IOMUXC_GPR_GPR1_GINT_MASK (0x1000U) #define IOMUXC_GPR_GPR1_GINT_SHIFT (12U) +/*! GINT + * 0b0..Global interrupt request is not asserted. + * 0b1..Global interrupt request is asserted. + */ #define IOMUXC_GPR_GPR1_GINT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_GINT_SHIFT)) & IOMUXC_GPR_GPR1_GINT_MASK) #define IOMUXC_GPR_GPR1_ENET1_CLK_SEL_MASK (0x2000U) #define IOMUXC_GPR_GPR1_ENET1_CLK_SEL_SHIFT (13U) +/*! ENET1_CLK_SEL + * 0b0..ENET1 TX reference clock driven by ref_enetpll0. This clock is also output to pins via the IOMUX. ENET_REF_CLK1 function. + * 0b1..Gets ENET1 TX reference clock from the ENET1_TX_CLK pin. In this use case, an external OSC provides the clock for both the external PHY and the internal controller. + */ #define IOMUXC_GPR_GPR1_ENET1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_ENET1_CLK_SEL_SHIFT)) & IOMUXC_GPR_GPR1_ENET1_CLK_SEL_MASK) #define IOMUXC_GPR_GPR1_USB_EXP_MODE_MASK (0x8000U) #define IOMUXC_GPR_GPR1_USB_EXP_MODE_SHIFT (15U) +/*! USB_EXP_MODE + * 0b0..Exposure mode is disabled. + * 0b1..Exposure mode is enabled. + */ #define IOMUXC_GPR_GPR1_USB_EXP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_USB_EXP_MODE_SHIFT)) & IOMUXC_GPR_GPR1_USB_EXP_MODE_MASK) #define IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK (0x20000U) #define IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_SHIFT (17U) +/*! ENET1_TX_CLK_DIR + * 0b0..ENET1_TX_CLK output driver is disabled and ENET_REF_CLK1 is a clock input. + * 0b1..ENET1_TX_CLK output driver is enabled and ENET_REF_CLK1 is an output driven by ref_enetpll0. + */ #define IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_SHIFT)) & IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK) #define IOMUXC_GPR_GPR1_SAI1_MCLK_DIR_MASK (0x80000U) #define IOMUXC_GPR_GPR1_SAI1_MCLK_DIR_SHIFT (19U) +/*! SAI1_MCLK_DIR + * 0b0..sai1.MCLK is input signal + * 0b1..sai1.MCLK is output signal + */ #define IOMUXC_GPR_GPR1_SAI1_MCLK_DIR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI1_MCLK_DIR_SHIFT)) & IOMUXC_GPR_GPR1_SAI1_MCLK_DIR_MASK) #define IOMUXC_GPR_GPR1_SAI2_MCLK_DIR_MASK (0x100000U) #define IOMUXC_GPR_GPR1_SAI2_MCLK_DIR_SHIFT (20U) +/*! SAI2_MCLK_DIR + * 0b0..sai2.MCLK is input signal + * 0b1..sai2.MCLK is output signal + */ #define IOMUXC_GPR_GPR1_SAI2_MCLK_DIR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI2_MCLK_DIR_SHIFT)) & IOMUXC_GPR_GPR1_SAI2_MCLK_DIR_MASK) #define IOMUXC_GPR_GPR1_SAI3_MCLK_DIR_MASK (0x200000U) #define IOMUXC_GPR_GPR1_SAI3_MCLK_DIR_SHIFT (21U) +/*! SAI3_MCLK_DIR + * 0b0..sai3.MCLK is input signal + * 0b1..sai3.MCLK is output signal + */ #define IOMUXC_GPR_GPR1_SAI3_MCLK_DIR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI3_MCLK_DIR_SHIFT)) & IOMUXC_GPR_GPR1_SAI3_MCLK_DIR_MASK) #define IOMUXC_GPR_GPR1_EXC_MON_MASK (0x400000U) #define IOMUXC_GPR_GPR1_EXC_MON_SHIFT (22U) +/*! EXC_MON + * 0b0..OKAY response + * 0b1..SLVError response + */ #define IOMUXC_GPR_GPR1_EXC_MON(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_EXC_MON_SHIFT)) & IOMUXC_GPR_GPR1_EXC_MON_MASK) #define IOMUXC_GPR_GPR1_ENET_IPG_CLK_S_EN_MASK (0x800000U) #define IOMUXC_GPR_GPR1_ENET_IPG_CLK_S_EN_SHIFT (23U) +/*! ENET_IPG_CLK_S_EN + * 0b0..ipg_clk_s is gated when there is no IPS access + * 0b1..ipg_clk_s is always on + */ #define IOMUXC_GPR_GPR1_ENET_IPG_CLK_S_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_ENET_IPG_CLK_S_EN_SHIFT)) & IOMUXC_GPR_GPR1_ENET_IPG_CLK_S_EN_MASK) #define IOMUXC_GPR_GPR1_CM7_FORCE_HCLK_EN_MASK (0x80000000U) #define IOMUXC_GPR_GPR1_CM7_FORCE_HCLK_EN_SHIFT (31U) +/*! CM7_FORCE_HCLK_EN + * 0b0..AHB clock is not running (gated) + * 0b1..AHB clock is running (enabled) + */ #define IOMUXC_GPR_GPR1_CM7_FORCE_HCLK_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_CM7_FORCE_HCLK_EN_SHIFT)) & IOMUXC_GPR_GPR1_CM7_FORCE_HCLK_EN_MASK) +/*! @} */ /*! @name GPR2 - GPR2 General Purpose Register */ +/*! @{ */ #define IOMUXC_GPR_GPR2_L2_MEM_EN_POWERSAVING_MASK (0x1000U) #define IOMUXC_GPR_GPR2_L2_MEM_EN_POWERSAVING_SHIFT (12U) +/*! L2_MEM_EN_POWERSAVING + * 0b0..none memory power saving features enabled, SHUTDOWN/DEEPSLEEP/LIGHTSLEEP will have no effect + * 0b1..memory power saving features enabled, set SHUTDOWN/DEEPSLEEP/LIGHTSLEEP(priority high to low) to enable power saving levels + */ #define IOMUXC_GPR_GPR2_L2_MEM_EN_POWERSAVING(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_L2_MEM_EN_POWERSAVING_SHIFT)) & IOMUXC_GPR_GPR2_L2_MEM_EN_POWERSAVING_MASK) #define IOMUXC_GPR_GPR2_L2_MEM_DEEPSLEEP_MASK (0x4000U) #define IOMUXC_GPR_GPR2_L2_MEM_DEEPSLEEP_SHIFT (14U) +/*! L2_MEM_DEEPSLEEP + * 0b0..no force sleep control supported, memory deep sleep mode only entered when whole system in stop mode + * 0b1..force memory into deep sleep mode + */ #define IOMUXC_GPR_GPR2_L2_MEM_DEEPSLEEP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_L2_MEM_DEEPSLEEP_SHIFT)) & IOMUXC_GPR_GPR2_L2_MEM_DEEPSLEEP_MASK) #define IOMUXC_GPR_GPR2_MQS_CLK_DIV_MASK (0xFF0000U) #define IOMUXC_GPR_GPR2_MQS_CLK_DIV_SHIFT (16U) +/*! MQS_CLK_DIV + * 0b00000000..mclk frequency = hmclk frequency + * 0b00000001..mclk frequency = 1/2 * hmclk frequency + * 0b00000010..mclk frequency = 1/3 * hmclk frequency + * 0b11111111..mclk frequency = 1/256 * hmclk frequency + */ #define IOMUXC_GPR_GPR2_MQS_CLK_DIV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_MQS_CLK_DIV_SHIFT)) & IOMUXC_GPR_GPR2_MQS_CLK_DIV_MASK) #define IOMUXC_GPR_GPR2_MQS_SW_RST_MASK (0x1000000U) #define IOMUXC_GPR_GPR2_MQS_SW_RST_SHIFT (24U) +/*! MQS_SW_RST + * 0b0..Exit software reset for MQS + * 0b1..Enable software reset for MQS + */ #define IOMUXC_GPR_GPR2_MQS_SW_RST(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_MQS_SW_RST_SHIFT)) & IOMUXC_GPR_GPR2_MQS_SW_RST_MASK) #define IOMUXC_GPR_GPR2_MQS_EN_MASK (0x2000000U) #define IOMUXC_GPR_GPR2_MQS_EN_SHIFT (25U) +/*! MQS_EN + * 0b0..Disable MQS + * 0b1..Enable MQS + */ #define IOMUXC_GPR_GPR2_MQS_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_MQS_EN_SHIFT)) & IOMUXC_GPR_GPR2_MQS_EN_MASK) #define IOMUXC_GPR_GPR2_MQS_OVERSAMPLE_MASK (0x4000000U) #define IOMUXC_GPR_GPR2_MQS_OVERSAMPLE_SHIFT (26U) +/*! MQS_OVERSAMPLE + * 0b0..32 + * 0b1..64 + */ #define IOMUXC_GPR_GPR2_MQS_OVERSAMPLE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_MQS_OVERSAMPLE_SHIFT)) & IOMUXC_GPR_GPR2_MQS_OVERSAMPLE_MASK) #define IOMUXC_GPR_GPR2_QTIMER1_TMR_CNTS_FREEZE_MASK (0x10000000U) #define IOMUXC_GPR_GPR2_QTIMER1_TMR_CNTS_FREEZE_SHIFT (28U) +/*! QTIMER1_TMR_CNTS_FREEZE + * 0b0..timer counter work normally + * 0b1..reset counter and ouput flags + */ #define IOMUXC_GPR_GPR2_QTIMER1_TMR_CNTS_FREEZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_QTIMER1_TMR_CNTS_FREEZE_SHIFT)) & IOMUXC_GPR_GPR2_QTIMER1_TMR_CNTS_FREEZE_MASK) #define IOMUXC_GPR_GPR2_QTIMER2_TMR_CNTS_FREEZE_MASK (0x20000000U) #define IOMUXC_GPR_GPR2_QTIMER2_TMR_CNTS_FREEZE_SHIFT (29U) +/*! QTIMER2_TMR_CNTS_FREEZE + * 0b0..timer counter work normally + * 0b1..reset counter and ouput flags + */ #define IOMUXC_GPR_GPR2_QTIMER2_TMR_CNTS_FREEZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_QTIMER2_TMR_CNTS_FREEZE_SHIFT)) & IOMUXC_GPR_GPR2_QTIMER2_TMR_CNTS_FREEZE_MASK) #define IOMUXC_GPR_GPR2_QTIMER3_TMR_CNTS_FREEZE_MASK (0x40000000U) #define IOMUXC_GPR_GPR2_QTIMER3_TMR_CNTS_FREEZE_SHIFT (30U) +/*! QTIMER3_TMR_CNTS_FREEZE + * 0b0..timer counter work normally + * 0b1..reset counter and ouput flags + */ #define IOMUXC_GPR_GPR2_QTIMER3_TMR_CNTS_FREEZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_QTIMER3_TMR_CNTS_FREEZE_SHIFT)) & IOMUXC_GPR_GPR2_QTIMER3_TMR_CNTS_FREEZE_MASK) #define IOMUXC_GPR_GPR2_QTIMER4_TMR_CNTS_FREEZE_MASK (0x80000000U) #define IOMUXC_GPR_GPR2_QTIMER4_TMR_CNTS_FREEZE_SHIFT (31U) +/*! QTIMER4_TMR_CNTS_FREEZE + * 0b0..timer counter work normally + * 0b1..reset counter and ouput flags + */ #define IOMUXC_GPR_GPR2_QTIMER4_TMR_CNTS_FREEZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_QTIMER4_TMR_CNTS_FREEZE_SHIFT)) & IOMUXC_GPR_GPR2_QTIMER4_TMR_CNTS_FREEZE_MASK) +/*! @} */ /*! @name GPR3 - GPR3 General Purpose Register */ +/*! @{ */ #define IOMUXC_GPR_GPR3_OCRAM_CTL_MASK (0xFU) #define IOMUXC_GPR_GPR3_OCRAM_CTL_SHIFT (0U) #define IOMUXC_GPR_GPR3_OCRAM_CTL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR3_OCRAM_CTL_SHIFT)) & IOMUXC_GPR_GPR3_OCRAM_CTL_MASK) #define IOMUXC_GPR_GPR3_DCP_KEY_SEL_MASK (0x10U) #define IOMUXC_GPR_GPR3_DCP_KEY_SEL_SHIFT (4U) +/*! DCP_KEY_SEL + * 0b0..Select [127:0] from snvs/ocotp key as dcp key + * 0b1..Select [255:128] from snvs/ocotp key as dcp key + */ #define IOMUXC_GPR_GPR3_DCP_KEY_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR3_DCP_KEY_SEL_SHIFT)) & IOMUXC_GPR_GPR3_DCP_KEY_SEL_MASK) #define IOMUXC_GPR_GPR3_OCRAM_STATUS_MASK (0xF0000U) #define IOMUXC_GPR_GPR3_OCRAM_STATUS_SHIFT (16U) +/*! OCRAM_STATUS + * 0b0000..read data pipeline configuration valid + * 0b0001..read data pipeline control bit changed + */ #define IOMUXC_GPR_GPR3_OCRAM_STATUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR3_OCRAM_STATUS_SHIFT)) & IOMUXC_GPR_GPR3_OCRAM_STATUS_MASK) +/*! @} */ /*! @name GPR4 - GPR4 General Purpose Register */ +/*! @{ */ #define IOMUXC_GPR_GPR4_EDMA_STOP_REQ_MASK (0x1U) #define IOMUXC_GPR_GPR4_EDMA_STOP_REQ_SHIFT (0U) +/*! EDMA_STOP_REQ + * 0b0..stop request off + * 0b1..stop request on + */ #define IOMUXC_GPR_GPR4_EDMA_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_EDMA_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_EDMA_STOP_REQ_MASK) #define IOMUXC_GPR_GPR4_CAN1_STOP_REQ_MASK (0x2U) #define IOMUXC_GPR_GPR4_CAN1_STOP_REQ_SHIFT (1U) +/*! CAN1_STOP_REQ + * 0b0..stop request off + * 0b1..stop request on + */ #define IOMUXC_GPR_GPR4_CAN1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_CAN1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_CAN1_STOP_REQ_MASK) #define IOMUXC_GPR_GPR4_CAN2_STOP_REQ_MASK (0x4U) #define IOMUXC_GPR_GPR4_CAN2_STOP_REQ_SHIFT (2U) +/*! CAN2_STOP_REQ + * 0b0..stop request off + * 0b1..stop request on + */ #define IOMUXC_GPR_GPR4_CAN2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_CAN2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_CAN2_STOP_REQ_MASK) #define IOMUXC_GPR_GPR4_TRNG_STOP_REQ_MASK (0x8U) #define IOMUXC_GPR_GPR4_TRNG_STOP_REQ_SHIFT (3U) +/*! TRNG_STOP_REQ + * 0b0..stop request off + * 0b1..stop request on + */ #define IOMUXC_GPR_GPR4_TRNG_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_TRNG_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_TRNG_STOP_REQ_MASK) #define IOMUXC_GPR_GPR4_ENET_STOP_REQ_MASK (0x10U) #define IOMUXC_GPR_GPR4_ENET_STOP_REQ_SHIFT (4U) +/*! ENET_STOP_REQ + * 0b0..stop request off + * 0b1..stop request on + */ #define IOMUXC_GPR_GPR4_ENET_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_ENET_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_ENET_STOP_REQ_MASK) #define IOMUXC_GPR_GPR4_SAI1_STOP_REQ_MASK (0x20U) #define IOMUXC_GPR_GPR4_SAI1_STOP_REQ_SHIFT (5U) +/*! SAI1_STOP_REQ + * 0b0..stop request off + * 0b1..stop request on + */ #define IOMUXC_GPR_GPR4_SAI1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SAI1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_SAI1_STOP_REQ_MASK) #define IOMUXC_GPR_GPR4_SAI2_STOP_REQ_MASK (0x40U) #define IOMUXC_GPR_GPR4_SAI2_STOP_REQ_SHIFT (6U) +/*! SAI2_STOP_REQ + * 0b0..stop request off + * 0b1..stop request on + */ #define IOMUXC_GPR_GPR4_SAI2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SAI2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_SAI2_STOP_REQ_MASK) #define IOMUXC_GPR_GPR4_SAI3_STOP_REQ_MASK (0x80U) #define IOMUXC_GPR_GPR4_SAI3_STOP_REQ_SHIFT (7U) +/*! SAI3_STOP_REQ + * 0b0..stop request off + * 0b1..stop request on + */ #define IOMUXC_GPR_GPR4_SAI3_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SAI3_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_SAI3_STOP_REQ_MASK) #define IOMUXC_GPR_GPR4_SEMC_STOP_REQ_MASK (0x200U) #define IOMUXC_GPR_GPR4_SEMC_STOP_REQ_SHIFT (9U) +/*! SEMC_STOP_REQ + * 0b0..stop request off + * 0b1..stop request on + */ #define IOMUXC_GPR_GPR4_SEMC_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SEMC_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_SEMC_STOP_REQ_MASK) #define IOMUXC_GPR_GPR4_PIT_STOP_REQ_MASK (0x400U) #define IOMUXC_GPR_GPR4_PIT_STOP_REQ_SHIFT (10U) +/*! PIT_STOP_REQ + * 0b0..stop request off + * 0b1..stop request on + */ #define IOMUXC_GPR_GPR4_PIT_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_PIT_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_PIT_STOP_REQ_MASK) #define IOMUXC_GPR_GPR4_FLEXSPI_STOP_REQ_MASK (0x800U) #define IOMUXC_GPR_GPR4_FLEXSPI_STOP_REQ_SHIFT (11U) +/*! FLEXSPI_STOP_REQ + * 0b0..stop request off + * 0b1..stop request on + */ #define IOMUXC_GPR_GPR4_FLEXSPI_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_FLEXSPI_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_FLEXSPI_STOP_REQ_MASK) #define IOMUXC_GPR_GPR4_FLEXIO1_STOP_REQ_MASK (0x1000U) #define IOMUXC_GPR_GPR4_FLEXIO1_STOP_REQ_SHIFT (12U) +/*! FLEXIO1_STOP_REQ + * 0b0..stop request off + * 0b1..stop request on + */ #define IOMUXC_GPR_GPR4_FLEXIO1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_FLEXIO1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_FLEXIO1_STOP_REQ_MASK) #define IOMUXC_GPR_GPR4_FLEXIO2_STOP_REQ_MASK (0x2000U) #define IOMUXC_GPR_GPR4_FLEXIO2_STOP_REQ_SHIFT (13U) +/*! FLEXIO2_STOP_REQ + * 0b0..stop request off + * 0b1..stop request on + */ #define IOMUXC_GPR_GPR4_FLEXIO2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_FLEXIO2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_FLEXIO2_STOP_REQ_MASK) #define IOMUXC_GPR_GPR4_EDMA_STOP_ACK_MASK (0x10000U) #define IOMUXC_GPR_GPR4_EDMA_STOP_ACK_SHIFT (16U) +/*! EDMA_STOP_ACK + * 0b0..EDMA stop acknowledge is not asserted + * 0b1..EDMA stop acknowledge is asserted (EDMA is in STOP mode). + */ #define IOMUXC_GPR_GPR4_EDMA_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_EDMA_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_EDMA_STOP_ACK_MASK) #define IOMUXC_GPR_GPR4_CAN1_STOP_ACK_MASK (0x20000U) #define IOMUXC_GPR_GPR4_CAN1_STOP_ACK_SHIFT (17U) +/*! CAN1_STOP_ACK + * 0b0..CAN1 stop acknowledge is not asserted + * 0b1..CAN1 stop acknowledge is asserted + */ #define IOMUXC_GPR_GPR4_CAN1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_CAN1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_CAN1_STOP_ACK_MASK) #define IOMUXC_GPR_GPR4_CAN2_STOP_ACK_MASK (0x40000U) #define IOMUXC_GPR_GPR4_CAN2_STOP_ACK_SHIFT (18U) +/*! CAN2_STOP_ACK + * 0b0..CAN2 stop acknowledge is not asserted + * 0b1..CAN2 stop acknowledge is asserted + */ #define IOMUXC_GPR_GPR4_CAN2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_CAN2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_CAN2_STOP_ACK_MASK) #define IOMUXC_GPR_GPR4_TRNG_STOP_ACK_MASK (0x80000U) #define IOMUXC_GPR_GPR4_TRNG_STOP_ACK_SHIFT (19U) +/*! TRNG_STOP_ACK + * 0b0..TRNG stop acknowledge is not asserted + * 0b1..TRNG stop acknowledge is asserted + */ #define IOMUXC_GPR_GPR4_TRNG_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_TRNG_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_TRNG_STOP_ACK_MASK) #define IOMUXC_GPR_GPR4_ENET_STOP_ACK_MASK (0x100000U) #define IOMUXC_GPR_GPR4_ENET_STOP_ACK_SHIFT (20U) +/*! ENET_STOP_ACK + * 0b0..ENET stop acknowledge is not asserted + * 0b1..ENET stop acknowledge is asserted + */ #define IOMUXC_GPR_GPR4_ENET_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_ENET_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_ENET_STOP_ACK_MASK) #define IOMUXC_GPR_GPR4_SAI1_STOP_ACK_MASK (0x200000U) #define IOMUXC_GPR_GPR4_SAI1_STOP_ACK_SHIFT (21U) +/*! SAI1_STOP_ACK + * 0b0..SAI1 stop acknowledge is not asserted + * 0b1..SAI1 stop acknowledge is asserted + */ #define IOMUXC_GPR_GPR4_SAI1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SAI1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_SAI1_STOP_ACK_MASK) #define IOMUXC_GPR_GPR4_SAI2_STOP_ACK_MASK (0x400000U) #define IOMUXC_GPR_GPR4_SAI2_STOP_ACK_SHIFT (22U) +/*! SAI2_STOP_ACK + * 0b0..SAI2 stop acknowledge is not asserted + * 0b1..SAI2 stop acknowledge is asserted + */ #define IOMUXC_GPR_GPR4_SAI2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SAI2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_SAI2_STOP_ACK_MASK) #define IOMUXC_GPR_GPR4_SAI3_STOP_ACK_MASK (0x800000U) #define IOMUXC_GPR_GPR4_SAI3_STOP_ACK_SHIFT (23U) +/*! SAI3_STOP_ACK + * 0b0..SAI3 stop acknowledge is not asserted + * 0b1..SAI3 stop acknowledge is asserted + */ #define IOMUXC_GPR_GPR4_SAI3_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SAI3_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_SAI3_STOP_ACK_MASK) #define IOMUXC_GPR_GPR4_SEMC_STOP_ACK_MASK (0x2000000U) #define IOMUXC_GPR_GPR4_SEMC_STOP_ACK_SHIFT (25U) +/*! SEMC_STOP_ACK + * 0b0..SEMC stop acknowledge is not asserted + * 0b1..SEMC stop acknowledge is asserted + */ #define IOMUXC_GPR_GPR4_SEMC_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SEMC_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_SEMC_STOP_ACK_MASK) #define IOMUXC_GPR_GPR4_PIT_STOP_ACK_MASK (0x4000000U) #define IOMUXC_GPR_GPR4_PIT_STOP_ACK_SHIFT (26U) +/*! PIT_STOP_ACK + * 0b0..PIT stop acknowledge is not asserted + * 0b1..PIT stop acknowledge is asserted + */ #define IOMUXC_GPR_GPR4_PIT_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_PIT_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_PIT_STOP_ACK_MASK) #define IOMUXC_GPR_GPR4_FLEXSPI_STOP_ACK_MASK (0x8000000U) #define IOMUXC_GPR_GPR4_FLEXSPI_STOP_ACK_SHIFT (27U) +/*! FLEXSPI_STOP_ACK + * 0b0..FLEXSPI stop acknowledge is not asserted + * 0b1..FLEXSPI stop acknowledge is asserted + */ #define IOMUXC_GPR_GPR4_FLEXSPI_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_FLEXSPI_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_FLEXSPI_STOP_ACK_MASK) #define IOMUXC_GPR_GPR4_FLEXIO1_STOP_ACK_MASK (0x10000000U) #define IOMUXC_GPR_GPR4_FLEXIO1_STOP_ACK_SHIFT (28U) +/*! FLEXIO1_STOP_ACK + * 0b0..FLEXIO1 stop acknowledge is not asserted + * 0b1..FLEXIO1 stop acknowledge is asserted + */ #define IOMUXC_GPR_GPR4_FLEXIO1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_FLEXIO1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_FLEXIO1_STOP_ACK_MASK) #define IOMUXC_GPR_GPR4_FLEXIO2_STOP_ACK_MASK (0x20000000U) #define IOMUXC_GPR_GPR4_FLEXIO2_STOP_ACK_SHIFT (29U) +/*! FLEXIO2_STOP_ACK + * 0b0..FLEXIO2 stop acknowledge is not asserted + * 0b1..FLEXIO2 stop acknowledge is asserted (FLEXIO2 is in STOP mode) + */ #define IOMUXC_GPR_GPR4_FLEXIO2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_FLEXIO2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_FLEXIO2_STOP_ACK_MASK) +/*! @} */ /*! @name GPR5 - GPR5 General Purpose Register */ +/*! @{ */ #define IOMUXC_GPR_GPR5_WDOG1_MASK_MASK (0x40U) #define IOMUXC_GPR_GPR5_WDOG1_MASK_SHIFT (6U) +/*! WDOG1_MASK + * 0b0..WDOG1 Timeout behaves normally + * 0b1..WDOG1 Timeout is masked + */ #define IOMUXC_GPR_GPR5_WDOG1_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_WDOG1_MASK_SHIFT)) & IOMUXC_GPR_GPR5_WDOG1_MASK_MASK) #define IOMUXC_GPR_GPR5_WDOG2_MASK_MASK (0x80U) #define IOMUXC_GPR_GPR5_WDOG2_MASK_SHIFT (7U) +/*! WDOG2_MASK + * 0b0..WDOG2 Timeout behaves normally + * 0b1..WDOG2 Timeout is masked + */ #define IOMUXC_GPR_GPR5_WDOG2_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_WDOG2_MASK_SHIFT)) & IOMUXC_GPR_GPR5_WDOG2_MASK_MASK) #define IOMUXC_GPR_GPR5_GPT2_CAPIN1_SEL_MASK (0x800000U) #define IOMUXC_GPR_GPR5_GPT2_CAPIN1_SEL_SHIFT (23U) +/*! GPT2_CAPIN1_SEL + * 0b0..source from pad + * 0b1..source from enet1.ipp_do_mac0_timer[3] + */ #define IOMUXC_GPR_GPR5_GPT2_CAPIN1_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_GPT2_CAPIN1_SEL_SHIFT)) & IOMUXC_GPR_GPR5_GPT2_CAPIN1_SEL_MASK) -#define IOMUXC_GPR_GPR5_GPT2_CAPIN2_SEL_MASK (0x1000000U) -#define IOMUXC_GPR_GPR5_GPT2_CAPIN2_SEL_SHIFT (24U) -#define IOMUXC_GPR_GPR5_GPT2_CAPIN2_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_GPT2_CAPIN2_SEL_SHIFT)) & IOMUXC_GPR_GPR5_GPT2_CAPIN2_SEL_MASK) #define IOMUXC_GPR_GPR5_ENET_EVENT3IN_SEL_MASK (0x2000000U) #define IOMUXC_GPR_GPR5_ENET_EVENT3IN_SEL_SHIFT (25U) +/*! ENET_EVENT3IN_SEL + * 0b0..event3 source input from pad + * 0b1..event3 source input from gpt2.ipp_do_cmpout1 + */ #define IOMUXC_GPR_GPR5_ENET_EVENT3IN_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_ENET_EVENT3IN_SEL_SHIFT)) & IOMUXC_GPR_GPR5_ENET_EVENT3IN_SEL_MASK) #define IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK (0x10000000U) #define IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_SHIFT (28U) +/*! VREF_1M_CLK_GPT1 + * 0b0..GPT1 ipg_clk_highfreq driven by IPG_PERCLK + * 0b1..GPT1 ipg_clk_highfreq driven by anatop 1 MHz clock + */ #define IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_SHIFT)) & IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK) #define IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK (0x20000000U) #define IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_SHIFT (29U) +/*! VREF_1M_CLK_GPT2 + * 0b0..GPT2 ipg_clk_highfreq driven by IPG_PERCLK + * 0b1..GPT2 ipg_clk_highfreq driven by anatop 1 MHz clock + */ #define IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_SHIFT)) & IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK) +/*! @} */ /*! @name GPR6 - GPR6 General Purpose Register */ +/*! @{ */ #define IOMUXC_GPR_GPR6_QTIMER1_TRM0_INPUT_SEL_MASK (0x1U) #define IOMUXC_GPR_GPR6_QTIMER1_TRM0_INPUT_SEL_SHIFT (0U) +/*! QTIMER1_TRM0_INPUT_SEL + * 0b0..input from IOMUX + * 0b1..input from XBAR + */ #define IOMUXC_GPR_GPR6_QTIMER1_TRM0_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER1_TRM0_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER1_TRM0_INPUT_SEL_MASK) #define IOMUXC_GPR_GPR6_QTIMER1_TRM1_INPUT_SEL_MASK (0x2U) #define IOMUXC_GPR_GPR6_QTIMER1_TRM1_INPUT_SEL_SHIFT (1U) +/*! QTIMER1_TRM1_INPUT_SEL + * 0b0..input from IOMUX + * 0b1..input from XBAR + */ #define IOMUXC_GPR_GPR6_QTIMER1_TRM1_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER1_TRM1_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER1_TRM1_INPUT_SEL_MASK) #define IOMUXC_GPR_GPR6_QTIMER1_TRM2_INPUT_SEL_MASK (0x4U) #define IOMUXC_GPR_GPR6_QTIMER1_TRM2_INPUT_SEL_SHIFT (2U) +/*! QTIMER1_TRM2_INPUT_SEL + * 0b0..input from IOMUX + * 0b1..input from XBAR + */ #define IOMUXC_GPR_GPR6_QTIMER1_TRM2_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER1_TRM2_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER1_TRM2_INPUT_SEL_MASK) #define IOMUXC_GPR_GPR6_QTIMER1_TRM3_INPUT_SEL_MASK (0x8U) #define IOMUXC_GPR_GPR6_QTIMER1_TRM3_INPUT_SEL_SHIFT (3U) +/*! QTIMER1_TRM3_INPUT_SEL + * 0b0..input from IOMUX + * 0b1..input from XBAR + */ #define IOMUXC_GPR_GPR6_QTIMER1_TRM3_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER1_TRM3_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER1_TRM3_INPUT_SEL_MASK) #define IOMUXC_GPR_GPR6_QTIMER2_TRM0_INPUT_SEL_MASK (0x10U) #define IOMUXC_GPR_GPR6_QTIMER2_TRM0_INPUT_SEL_SHIFT (4U) +/*! QTIMER2_TRM0_INPUT_SEL + * 0b0..input from IOMUX + * 0b1..input from XBAR + */ #define IOMUXC_GPR_GPR6_QTIMER2_TRM0_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER2_TRM0_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER2_TRM0_INPUT_SEL_MASK) #define IOMUXC_GPR_GPR6_QTIMER2_TRM1_INPUT_SEL_MASK (0x20U) #define IOMUXC_GPR_GPR6_QTIMER2_TRM1_INPUT_SEL_SHIFT (5U) +/*! QTIMER2_TRM1_INPUT_SEL + * 0b0..input from IOMUX + * 0b1..input from XBAR + */ #define IOMUXC_GPR_GPR6_QTIMER2_TRM1_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER2_TRM1_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER2_TRM1_INPUT_SEL_MASK) #define IOMUXC_GPR_GPR6_QTIMER2_TRM2_INPUT_SEL_MASK (0x40U) #define IOMUXC_GPR_GPR6_QTIMER2_TRM2_INPUT_SEL_SHIFT (6U) +/*! QTIMER2_TRM2_INPUT_SEL + * 0b0..input from IOMUX + * 0b1..input from XBAR + */ #define IOMUXC_GPR_GPR6_QTIMER2_TRM2_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER2_TRM2_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER2_TRM2_INPUT_SEL_MASK) #define IOMUXC_GPR_GPR6_QTIMER2_TRM3_INPUT_SEL_MASK (0x80U) #define IOMUXC_GPR_GPR6_QTIMER2_TRM3_INPUT_SEL_SHIFT (7U) +/*! QTIMER2_TRM3_INPUT_SEL + * 0b0..input from IOMUX + * 0b1..input from XBAR + */ #define IOMUXC_GPR_GPR6_QTIMER2_TRM3_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER2_TRM3_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER2_TRM3_INPUT_SEL_MASK) #define IOMUXC_GPR_GPR6_QTIMER3_TRM0_INPUT_SEL_MASK (0x100U) #define IOMUXC_GPR_GPR6_QTIMER3_TRM0_INPUT_SEL_SHIFT (8U) +/*! QTIMER3_TRM0_INPUT_SEL + * 0b0..input from IOMUX + * 0b1..input from XBAR + */ #define IOMUXC_GPR_GPR6_QTIMER3_TRM0_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER3_TRM0_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER3_TRM0_INPUT_SEL_MASK) #define IOMUXC_GPR_GPR6_QTIMER3_TRM1_INPUT_SEL_MASK (0x200U) #define IOMUXC_GPR_GPR6_QTIMER3_TRM1_INPUT_SEL_SHIFT (9U) +/*! QTIMER3_TRM1_INPUT_SEL + * 0b0..input from IOMUX + * 0b1..input from XBAR + */ #define IOMUXC_GPR_GPR6_QTIMER3_TRM1_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER3_TRM1_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER3_TRM1_INPUT_SEL_MASK) #define IOMUXC_GPR_GPR6_QTIMER3_TRM2_INPUT_SEL_MASK (0x400U) #define IOMUXC_GPR_GPR6_QTIMER3_TRM2_INPUT_SEL_SHIFT (10U) +/*! QTIMER3_TRM2_INPUT_SEL + * 0b0..input from IOMUX + * 0b1..input from XBAR + */ #define IOMUXC_GPR_GPR6_QTIMER3_TRM2_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER3_TRM2_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER3_TRM2_INPUT_SEL_MASK) #define IOMUXC_GPR_GPR6_QTIMER3_TRM3_INPUT_SEL_MASK (0x800U) #define IOMUXC_GPR_GPR6_QTIMER3_TRM3_INPUT_SEL_SHIFT (11U) +/*! QTIMER3_TRM3_INPUT_SEL + * 0b0..input from IOMUX + * 0b1..input from XBAR + */ #define IOMUXC_GPR_GPR6_QTIMER3_TRM3_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER3_TRM3_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER3_TRM3_INPUT_SEL_MASK) #define IOMUXC_GPR_GPR6_QTIMER4_TRM0_INPUT_SEL_MASK (0x1000U) #define IOMUXC_GPR_GPR6_QTIMER4_TRM0_INPUT_SEL_SHIFT (12U) +/*! QTIMER4_TRM0_INPUT_SEL + * 0b0..input from IOMUX + * 0b1..input from XBAR + */ #define IOMUXC_GPR_GPR6_QTIMER4_TRM0_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER4_TRM0_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER4_TRM0_INPUT_SEL_MASK) #define IOMUXC_GPR_GPR6_QTIMER4_TRM1_INPUT_SEL_MASK (0x2000U) #define IOMUXC_GPR_GPR6_QTIMER4_TRM1_INPUT_SEL_SHIFT (13U) +/*! QTIMER4_TRM1_INPUT_SEL + * 0b0..input from IOMUX + * 0b1..input from XBAR + */ #define IOMUXC_GPR_GPR6_QTIMER4_TRM1_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER4_TRM1_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER4_TRM1_INPUT_SEL_MASK) #define IOMUXC_GPR_GPR6_QTIMER4_TRM2_INPUT_SEL_MASK (0x4000U) #define IOMUXC_GPR_GPR6_QTIMER4_TRM2_INPUT_SEL_SHIFT (14U) +/*! QTIMER4_TRM2_INPUT_SEL + * 0b0..input from IOMUX + * 0b1..input from XBAR + */ #define IOMUXC_GPR_GPR6_QTIMER4_TRM2_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER4_TRM2_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER4_TRM2_INPUT_SEL_MASK) #define IOMUXC_GPR_GPR6_QTIMER4_TRM3_INPUT_SEL_MASK (0x8000U) #define IOMUXC_GPR_GPR6_QTIMER4_TRM3_INPUT_SEL_SHIFT (15U) +/*! QTIMER4_TRM3_INPUT_SEL + * 0b0..input from IOMUX + * 0b1..input from XBAR + */ #define IOMUXC_GPR_GPR6_QTIMER4_TRM3_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER4_TRM3_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER4_TRM3_INPUT_SEL_MASK) #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_4_MASK (0x10000U) #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_4_SHIFT (16U) +/*! IOMUXC_XBAR_DIR_SEL_4 + * 0b0..XBAR_INOUT as input + * 0b1..XBAR_INOUT as output + */ #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_4_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_4_MASK) #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_5_MASK (0x20000U) #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_5_SHIFT (17U) +/*! IOMUXC_XBAR_DIR_SEL_5 + * 0b0..XBAR_INOUT as input + * 0b1..XBAR_INOUT as output + */ #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_5(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_5_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_5_MASK) #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_6_MASK (0x40000U) #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_6_SHIFT (18U) +/*! IOMUXC_XBAR_DIR_SEL_6 + * 0b0..XBAR_INOUT as input + * 0b1..XBAR_INOUT as output + */ #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_6(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_6_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_6_MASK) #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_7_MASK (0x80000U) #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_7_SHIFT (19U) +/*! IOMUXC_XBAR_DIR_SEL_7 + * 0b0..XBAR_INOUT as input + * 0b1..XBAR_INOUT as output + */ #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_7(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_7_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_7_MASK) #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_8_MASK (0x100000U) #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_8_SHIFT (20U) +/*! IOMUXC_XBAR_DIR_SEL_8 + * 0b0..XBAR_INOUT as input + * 0b1..XBAR_INOUT as output + */ #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_8(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_8_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_8_MASK) #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_9_MASK (0x200000U) #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_9_SHIFT (21U) +/*! IOMUXC_XBAR_DIR_SEL_9 + * 0b0..XBAR_INOUT as input + * 0b1..XBAR_INOUT as output + */ #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_9(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_9_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_9_MASK) #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_10_MASK (0x400000U) #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_10_SHIFT (22U) +/*! IOMUXC_XBAR_DIR_SEL_10 + * 0b0..XBAR_INOUT as input + * 0b1..XBAR_INOUT as output + */ #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_10(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_10_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_10_MASK) #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_11_MASK (0x800000U) #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_11_SHIFT (23U) +/*! IOMUXC_XBAR_DIR_SEL_11 + * 0b0..XBAR_INOUT as input + * 0b1..XBAR_INOUT as output + */ #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_11(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_11_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_11_MASK) #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_12_MASK (0x1000000U) #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_12_SHIFT (24U) +/*! IOMUXC_XBAR_DIR_SEL_12 + * 0b0..XBAR_INOUT as input + * 0b1..XBAR_INOUT as output + */ #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_12(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_12_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_12_MASK) #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_13_MASK (0x2000000U) #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_13_SHIFT (25U) +/*! IOMUXC_XBAR_DIR_SEL_13 + * 0b0..XBAR_INOUT as input + * 0b1..XBAR_INOUT as output + */ #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_13(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_13_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_13_MASK) #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_14_MASK (0x4000000U) #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_14_SHIFT (26U) +/*! IOMUXC_XBAR_DIR_SEL_14 + * 0b0..XBAR_INOUT as input + * 0b1..XBAR_INOUT as output + */ #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_14(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_14_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_14_MASK) #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_15_MASK (0x8000000U) #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_15_SHIFT (27U) +/*! IOMUXC_XBAR_DIR_SEL_15 + * 0b0..XBAR_INOUT as input + * 0b1..XBAR_INOUT as output + */ #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_15(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_15_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_15_MASK) #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_16_MASK (0x10000000U) #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_16_SHIFT (28U) +/*! IOMUXC_XBAR_DIR_SEL_16 + * 0b0..XBAR_INOUT as input + * 0b1..XBAR_INOUT as output + */ #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_16(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_16_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_16_MASK) #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_17_MASK (0x20000000U) #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_17_SHIFT (29U) +/*! IOMUXC_XBAR_DIR_SEL_17 + * 0b0..XBAR_INOUT as input + * 0b1..XBAR_INOUT as output + */ #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_17(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_17_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_17_MASK) #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_18_MASK (0x40000000U) #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_18_SHIFT (30U) +/*! IOMUXC_XBAR_DIR_SEL_18 + * 0b0..XBAR_INOUT as input + * 0b1..XBAR_INOUT as output + */ #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_18_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_18_MASK) #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_19_MASK (0x80000000U) #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_19_SHIFT (31U) +/*! IOMUXC_XBAR_DIR_SEL_19 + * 0b0..XBAR_INOUT as input + * 0b1..XBAR_INOUT as output + */ #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_19(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_19_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_19_MASK) +/*! @} */ /*! @name GPR7 - GPR7 General Purpose Register */ +/*! @{ */ #define IOMUXC_GPR_GPR7_LPI2C1_STOP_REQ_MASK (0x1U) #define IOMUXC_GPR_GPR7_LPI2C1_STOP_REQ_SHIFT (0U) +/*! LPI2C1_STOP_REQ + * 0b0..stop request off + * 0b1..stop request on + */ #define IOMUXC_GPR_GPR7_LPI2C1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPI2C1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPI2C1_STOP_REQ_MASK) #define IOMUXC_GPR_GPR7_LPI2C2_STOP_REQ_MASK (0x2U) #define IOMUXC_GPR_GPR7_LPI2C2_STOP_REQ_SHIFT (1U) +/*! LPI2C2_STOP_REQ + * 0b0..stop request off + * 0b1..stop request on + */ #define IOMUXC_GPR_GPR7_LPI2C2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPI2C2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPI2C2_STOP_REQ_MASK) #define IOMUXC_GPR_GPR7_LPI2C3_STOP_REQ_MASK (0x4U) #define IOMUXC_GPR_GPR7_LPI2C3_STOP_REQ_SHIFT (2U) +/*! LPI2C3_STOP_REQ + * 0b0..stop request off + * 0b1..stop request on + */ #define IOMUXC_GPR_GPR7_LPI2C3_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPI2C3_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPI2C3_STOP_REQ_MASK) #define IOMUXC_GPR_GPR7_LPI2C4_STOP_REQ_MASK (0x8U) #define IOMUXC_GPR_GPR7_LPI2C4_STOP_REQ_SHIFT (3U) +/*! LPI2C4_STOP_REQ + * 0b0..stop request off + * 0b1..stop request on + */ #define IOMUXC_GPR_GPR7_LPI2C4_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPI2C4_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPI2C4_STOP_REQ_MASK) #define IOMUXC_GPR_GPR7_LPSPI1_STOP_REQ_MASK (0x10U) #define IOMUXC_GPR_GPR7_LPSPI1_STOP_REQ_SHIFT (4U) +/*! LPSPI1_STOP_REQ + * 0b0..stop request off + * 0b1..stop request on + */ #define IOMUXC_GPR_GPR7_LPSPI1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPSPI1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPSPI1_STOP_REQ_MASK) #define IOMUXC_GPR_GPR7_LPSPI2_STOP_REQ_MASK (0x20U) #define IOMUXC_GPR_GPR7_LPSPI2_STOP_REQ_SHIFT (5U) +/*! LPSPI2_STOP_REQ + * 0b0..stop request off + * 0b1..stop request on + */ #define IOMUXC_GPR_GPR7_LPSPI2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPSPI2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPSPI2_STOP_REQ_MASK) #define IOMUXC_GPR_GPR7_LPSPI3_STOP_REQ_MASK (0x40U) #define IOMUXC_GPR_GPR7_LPSPI3_STOP_REQ_SHIFT (6U) +/*! LPSPI3_STOP_REQ + * 0b0..stop request off + * 0b1..stop request on + */ #define IOMUXC_GPR_GPR7_LPSPI3_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPSPI3_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPSPI3_STOP_REQ_MASK) #define IOMUXC_GPR_GPR7_LPSPI4_STOP_REQ_MASK (0x80U) #define IOMUXC_GPR_GPR7_LPSPI4_STOP_REQ_SHIFT (7U) +/*! LPSPI4_STOP_REQ + * 0b0..stop request off + * 0b1..stop request on + */ #define IOMUXC_GPR_GPR7_LPSPI4_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPSPI4_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPSPI4_STOP_REQ_MASK) #define IOMUXC_GPR_GPR7_LPUART1_STOP_REQ_MASK (0x100U) #define IOMUXC_GPR_GPR7_LPUART1_STOP_REQ_SHIFT (8U) +/*! LPUART1_STOP_REQ + * 0b0..stop request off + * 0b1..stop request on + */ #define IOMUXC_GPR_GPR7_LPUART1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPUART1_STOP_REQ_MASK) #define IOMUXC_GPR_GPR7_LPUART2_STOP_REQ_MASK (0x200U) #define IOMUXC_GPR_GPR7_LPUART2_STOP_REQ_SHIFT (9U) +/*! LPUART2_STOP_REQ + * 0b0..stop request off + * 0b1..stop request on + */ #define IOMUXC_GPR_GPR7_LPUART2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPUART2_STOP_REQ_MASK) #define IOMUXC_GPR_GPR7_LPUART3_STOP_REQ_MASK (0x400U) #define IOMUXC_GPR_GPR7_LPUART3_STOP_REQ_SHIFT (10U) +/*! LPUART3_STOP_REQ + * 0b0..stop request off + * 0b1..stop request on + */ #define IOMUXC_GPR_GPR7_LPUART3_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART3_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPUART3_STOP_REQ_MASK) #define IOMUXC_GPR_GPR7_LPUART4_STOP_REQ_MASK (0x800U) #define IOMUXC_GPR_GPR7_LPUART4_STOP_REQ_SHIFT (11U) +/*! LPUART4_STOP_REQ + * 0b0..stop request off + * 0b1..stop request on + */ #define IOMUXC_GPR_GPR7_LPUART4_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART4_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPUART4_STOP_REQ_MASK) #define IOMUXC_GPR_GPR7_LPUART5_STOP_REQ_MASK (0x1000U) #define IOMUXC_GPR_GPR7_LPUART5_STOP_REQ_SHIFT (12U) +/*! LPUART5_STOP_REQ + * 0b0..stop request off + * 0b1..stop request on + */ #define IOMUXC_GPR_GPR7_LPUART5_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART5_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPUART5_STOP_REQ_MASK) #define IOMUXC_GPR_GPR7_LPUART6_STOP_REQ_MASK (0x2000U) #define IOMUXC_GPR_GPR7_LPUART6_STOP_REQ_SHIFT (13U) +/*! LPUART6_STOP_REQ + * 0b0..stop request off + * 0b1..stop request on + */ #define IOMUXC_GPR_GPR7_LPUART6_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART6_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPUART6_STOP_REQ_MASK) #define IOMUXC_GPR_GPR7_LPUART7_STOP_REQ_MASK (0x4000U) #define IOMUXC_GPR_GPR7_LPUART7_STOP_REQ_SHIFT (14U) +/*! LPUART7_STOP_REQ + * 0b0..stop request off + * 0b1..stop request on + */ #define IOMUXC_GPR_GPR7_LPUART7_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART7_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPUART7_STOP_REQ_MASK) #define IOMUXC_GPR_GPR7_LPUART8_STOP_REQ_MASK (0x8000U) #define IOMUXC_GPR_GPR7_LPUART8_STOP_REQ_SHIFT (15U) +/*! LPUART8_STOP_REQ + * 0b0..stop request off + * 0b1..stop request on + */ #define IOMUXC_GPR_GPR7_LPUART8_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART8_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPUART8_STOP_REQ_MASK) #define IOMUXC_GPR_GPR7_LPI2C1_STOP_ACK_MASK (0x10000U) #define IOMUXC_GPR_GPR7_LPI2C1_STOP_ACK_SHIFT (16U) +/*! LPI2C1_STOP_ACK + * 0b0..stop acknowledge is not asserted + * 0b1..stop acknowledge is asserted (the module is in Stop mode) + */ #define IOMUXC_GPR_GPR7_LPI2C1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPI2C1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPI2C1_STOP_ACK_MASK) #define IOMUXC_GPR_GPR7_LPI2C2_STOP_ACK_MASK (0x20000U) #define IOMUXC_GPR_GPR7_LPI2C2_STOP_ACK_SHIFT (17U) +/*! LPI2C2_STOP_ACK + * 0b0..stop acknowledge is not asserted + * 0b1..stop acknowledge is asserted + */ #define IOMUXC_GPR_GPR7_LPI2C2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPI2C2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPI2C2_STOP_ACK_MASK) #define IOMUXC_GPR_GPR7_LPI2C3_STOP_ACK_MASK (0x40000U) #define IOMUXC_GPR_GPR7_LPI2C3_STOP_ACK_SHIFT (18U) +/*! LPI2C3_STOP_ACK + * 0b0..stop acknowledge is not asserted + * 0b1..stop acknowledge is asserted + */ #define IOMUXC_GPR_GPR7_LPI2C3_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPI2C3_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPI2C3_STOP_ACK_MASK) #define IOMUXC_GPR_GPR7_LPI2C4_STOP_ACK_MASK (0x80000U) #define IOMUXC_GPR_GPR7_LPI2C4_STOP_ACK_SHIFT (19U) +/*! LPI2C4_STOP_ACK + * 0b0..stop acknowledge is not asserted + * 0b1..stop acknowledge is asserted + */ #define IOMUXC_GPR_GPR7_LPI2C4_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPI2C4_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPI2C4_STOP_ACK_MASK) #define IOMUXC_GPR_GPR7_LPSPI1_STOP_ACK_MASK (0x100000U) #define IOMUXC_GPR_GPR7_LPSPI1_STOP_ACK_SHIFT (20U) +/*! LPSPI1_STOP_ACK + * 0b0..stop acknowledge is not asserted + * 0b1..stop acknowledge is asserted + */ #define IOMUXC_GPR_GPR7_LPSPI1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPSPI1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPSPI1_STOP_ACK_MASK) #define IOMUXC_GPR_GPR7_LPSPI2_STOP_ACK_MASK (0x200000U) #define IOMUXC_GPR_GPR7_LPSPI2_STOP_ACK_SHIFT (21U) +/*! LPSPI2_STOP_ACK + * 0b0..stop acknowledge is not asserted + * 0b1..stop acknowledge is asserted + */ #define IOMUXC_GPR_GPR7_LPSPI2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPSPI2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPSPI2_STOP_ACK_MASK) #define IOMUXC_GPR_GPR7_LPSPI3_STOP_ACK_MASK (0x400000U) #define IOMUXC_GPR_GPR7_LPSPI3_STOP_ACK_SHIFT (22U) +/*! LPSPI3_STOP_ACK + * 0b0..stop acknowledge is not asserted + * 0b1..stop acknowledge is asserted + */ #define IOMUXC_GPR_GPR7_LPSPI3_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPSPI3_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPSPI3_STOP_ACK_MASK) #define IOMUXC_GPR_GPR7_LPSPI4_STOP_ACK_MASK (0x800000U) #define IOMUXC_GPR_GPR7_LPSPI4_STOP_ACK_SHIFT (23U) +/*! LPSPI4_STOP_ACK + * 0b0..stop acknowledge is not asserted + * 0b1..stop acknowledge is asserted + */ #define IOMUXC_GPR_GPR7_LPSPI4_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPSPI4_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPSPI4_STOP_ACK_MASK) #define IOMUXC_GPR_GPR7_LPUART1_STOP_ACK_MASK (0x1000000U) #define IOMUXC_GPR_GPR7_LPUART1_STOP_ACK_SHIFT (24U) +/*! LPUART1_STOP_ACK + * 0b0..stop acknowledge is not asserted + * 0b1..stop acknowledge is asserted + */ #define IOMUXC_GPR_GPR7_LPUART1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPUART1_STOP_ACK_MASK) #define IOMUXC_GPR_GPR7_LPUART2_STOP_ACK_MASK (0x2000000U) #define IOMUXC_GPR_GPR7_LPUART2_STOP_ACK_SHIFT (25U) +/*! LPUART2_STOP_ACK + * 0b0..stop acknowledge is not asserted + * 0b1..stop acknowledge is asserted + */ #define IOMUXC_GPR_GPR7_LPUART2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPUART2_STOP_ACK_MASK) #define IOMUXC_GPR_GPR7_LPUART3_STOP_ACK_MASK (0x4000000U) #define IOMUXC_GPR_GPR7_LPUART3_STOP_ACK_SHIFT (26U) +/*! LPUART3_STOP_ACK + * 0b0..stop acknowledge is not asserted + * 0b1..stop acknowledge is asserted + */ #define IOMUXC_GPR_GPR7_LPUART3_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART3_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPUART3_STOP_ACK_MASK) #define IOMUXC_GPR_GPR7_LPUART4_STOP_ACK_MASK (0x8000000U) #define IOMUXC_GPR_GPR7_LPUART4_STOP_ACK_SHIFT (27U) +/*! LPUART4_STOP_ACK + * 0b0..stop acknowledge is not asserted + * 0b1..stop acknowledge is asserted + */ #define IOMUXC_GPR_GPR7_LPUART4_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART4_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPUART4_STOP_ACK_MASK) #define IOMUXC_GPR_GPR7_LPUART5_STOP_ACK_MASK (0x10000000U) #define IOMUXC_GPR_GPR7_LPUART5_STOP_ACK_SHIFT (28U) +/*! LPUART5_STOP_ACK + * 0b0..stop acknowledge is not asserted + * 0b1..stop acknowledge is asserted + */ #define IOMUXC_GPR_GPR7_LPUART5_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART5_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPUART5_STOP_ACK_MASK) #define IOMUXC_GPR_GPR7_LPUART6_STOP_ACK_MASK (0x20000000U) #define IOMUXC_GPR_GPR7_LPUART6_STOP_ACK_SHIFT (29U) +/*! LPUART6_STOP_ACK + * 0b0..stop acknowledge is not asserted + * 0b1..stop acknowledge is asserted + */ #define IOMUXC_GPR_GPR7_LPUART6_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART6_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPUART6_STOP_ACK_MASK) #define IOMUXC_GPR_GPR7_LPUART7_STOP_ACK_MASK (0x40000000U) #define IOMUXC_GPR_GPR7_LPUART7_STOP_ACK_SHIFT (30U) +/*! LPUART7_STOP_ACK + * 0b0..stop acknowledge is not asserted + * 0b1..stop acknowledge is asserted + */ #define IOMUXC_GPR_GPR7_LPUART7_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART7_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPUART7_STOP_ACK_MASK) #define IOMUXC_GPR_GPR7_LPUART8_STOP_ACK_MASK (0x80000000U) #define IOMUXC_GPR_GPR7_LPUART8_STOP_ACK_SHIFT (31U) +/*! LPUART8_STOP_ACK + * 0b0..stop acknowledge is not asserted + * 0b1..stop acknowledge is asserted (the module is in Stop mode) + */ #define IOMUXC_GPR_GPR7_LPUART8_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART8_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPUART8_STOP_ACK_MASK) +/*! @} */ /*! @name GPR8 - GPR8 General Purpose Register */ +/*! @{ */ #define IOMUXC_GPR_GPR8_LPI2C1_IPG_STOP_MODE_MASK (0x1U) #define IOMUXC_GPR_GPR8_LPI2C1_IPG_STOP_MODE_SHIFT (0U) +/*! LPI2C1_IPG_STOP_MODE + * 0b0..the module is functional in Stop mode + * 0b1..the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted + */ #define IOMUXC_GPR_GPR8_LPI2C1_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPI2C1_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPI2C1_IPG_STOP_MODE_MASK) #define IOMUXC_GPR_GPR8_LPI2C1_IPG_DOZE_MASK (0x2U) #define IOMUXC_GPR_GPR8_LPI2C1_IPG_DOZE_SHIFT (1U) +/*! LPI2C1_IPG_DOZE + * 0b0..not in doze mode + * 0b1..in doze mode + */ #define IOMUXC_GPR_GPR8_LPI2C1_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPI2C1_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPI2C1_IPG_DOZE_MASK) #define IOMUXC_GPR_GPR8_LPI2C2_IPG_STOP_MODE_MASK (0x4U) #define IOMUXC_GPR_GPR8_LPI2C2_IPG_STOP_MODE_SHIFT (2U) +/*! LPI2C2_IPG_STOP_MODE + * 0b0..the module is functional in Stop mode + * 0b1..the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted + */ #define IOMUXC_GPR_GPR8_LPI2C2_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPI2C2_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPI2C2_IPG_STOP_MODE_MASK) #define IOMUXC_GPR_GPR8_LPI2C2_IPG_DOZE_MASK (0x8U) #define IOMUXC_GPR_GPR8_LPI2C2_IPG_DOZE_SHIFT (3U) +/*! LPI2C2_IPG_DOZE + * 0b0..not in doze mode + * 0b1..in doze mode + */ #define IOMUXC_GPR_GPR8_LPI2C2_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPI2C2_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPI2C2_IPG_DOZE_MASK) #define IOMUXC_GPR_GPR8_LPI2C3_IPG_STOP_MODE_MASK (0x10U) #define IOMUXC_GPR_GPR8_LPI2C3_IPG_STOP_MODE_SHIFT (4U) +/*! LPI2C3_IPG_STOP_MODE + * 0b0..the module is functional in Stop mode + * 0b1..the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted + */ #define IOMUXC_GPR_GPR8_LPI2C3_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPI2C3_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPI2C3_IPG_STOP_MODE_MASK) #define IOMUXC_GPR_GPR8_LPI2C3_IPG_DOZE_MASK (0x20U) #define IOMUXC_GPR_GPR8_LPI2C3_IPG_DOZE_SHIFT (5U) +/*! LPI2C3_IPG_DOZE + * 0b0..not in doze mode + * 0b1..in doze mode + */ #define IOMUXC_GPR_GPR8_LPI2C3_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPI2C3_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPI2C3_IPG_DOZE_MASK) #define IOMUXC_GPR_GPR8_LPI2C4_IPG_STOP_MODE_MASK (0x40U) #define IOMUXC_GPR_GPR8_LPI2C4_IPG_STOP_MODE_SHIFT (6U) +/*! LPI2C4_IPG_STOP_MODE + * 0b0..the module is functional in Stop mode + * 0b1..the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted + */ #define IOMUXC_GPR_GPR8_LPI2C4_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPI2C4_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPI2C4_IPG_STOP_MODE_MASK) #define IOMUXC_GPR_GPR8_LPI2C4_IPG_DOZE_MASK (0x80U) #define IOMUXC_GPR_GPR8_LPI2C4_IPG_DOZE_SHIFT (7U) +/*! LPI2C4_IPG_DOZE + * 0b0..not in doze mode + * 0b1..in doze mode + */ #define IOMUXC_GPR_GPR8_LPI2C4_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPI2C4_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPI2C4_IPG_DOZE_MASK) #define IOMUXC_GPR_GPR8_LPSPI1_IPG_STOP_MODE_MASK (0x100U) #define IOMUXC_GPR_GPR8_LPSPI1_IPG_STOP_MODE_SHIFT (8U) +/*! LPSPI1_IPG_STOP_MODE + * 0b0..the module is functional in Stop mode + * 0b1..the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted + */ #define IOMUXC_GPR_GPR8_LPSPI1_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPSPI1_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPSPI1_IPG_STOP_MODE_MASK) #define IOMUXC_GPR_GPR8_LPSPI1_IPG_DOZE_MASK (0x200U) #define IOMUXC_GPR_GPR8_LPSPI1_IPG_DOZE_SHIFT (9U) +/*! LPSPI1_IPG_DOZE + * 0b0..not in doze mode + * 0b1..in doze mode + */ #define IOMUXC_GPR_GPR8_LPSPI1_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPSPI1_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPSPI1_IPG_DOZE_MASK) #define IOMUXC_GPR_GPR8_LPSPI2_IPG_STOP_MODE_MASK (0x400U) #define IOMUXC_GPR_GPR8_LPSPI2_IPG_STOP_MODE_SHIFT (10U) +/*! LPSPI2_IPG_STOP_MODE + * 0b0..the module is functional in Stop mode + * 0b1..the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted + */ #define IOMUXC_GPR_GPR8_LPSPI2_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPSPI2_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPSPI2_IPG_STOP_MODE_MASK) #define IOMUXC_GPR_GPR8_LPSPI2_IPG_DOZE_MASK (0x800U) #define IOMUXC_GPR_GPR8_LPSPI2_IPG_DOZE_SHIFT (11U) +/*! LPSPI2_IPG_DOZE + * 0b0..not in doze mode + * 0b1..in doze mode + */ #define IOMUXC_GPR_GPR8_LPSPI2_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPSPI2_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPSPI2_IPG_DOZE_MASK) #define IOMUXC_GPR_GPR8_LPSPI3_IPG_STOP_MODE_MASK (0x1000U) #define IOMUXC_GPR_GPR8_LPSPI3_IPG_STOP_MODE_SHIFT (12U) +/*! LPSPI3_IPG_STOP_MODE + * 0b0..the module is functional in Stop mode + * 0b1..the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted + */ #define IOMUXC_GPR_GPR8_LPSPI3_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPSPI3_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPSPI3_IPG_STOP_MODE_MASK) #define IOMUXC_GPR_GPR8_LPSPI3_IPG_DOZE_MASK (0x2000U) #define IOMUXC_GPR_GPR8_LPSPI3_IPG_DOZE_SHIFT (13U) +/*! LPSPI3_IPG_DOZE + * 0b0..not in doze mode + * 0b1..in doze mode + */ #define IOMUXC_GPR_GPR8_LPSPI3_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPSPI3_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPSPI3_IPG_DOZE_MASK) #define IOMUXC_GPR_GPR8_LPSPI4_IPG_STOP_MODE_MASK (0x4000U) #define IOMUXC_GPR_GPR8_LPSPI4_IPG_STOP_MODE_SHIFT (14U) +/*! LPSPI4_IPG_STOP_MODE + * 0b0..the module is functional in Stop mode + * 0b1..the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted + */ #define IOMUXC_GPR_GPR8_LPSPI4_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPSPI4_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPSPI4_IPG_STOP_MODE_MASK) #define IOMUXC_GPR_GPR8_LPSPI4_IPG_DOZE_MASK (0x8000U) #define IOMUXC_GPR_GPR8_LPSPI4_IPG_DOZE_SHIFT (15U) +/*! LPSPI4_IPG_DOZE + * 0b0..not in doze mode + * 0b1..in doze mode + */ #define IOMUXC_GPR_GPR8_LPSPI4_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPSPI4_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPSPI4_IPG_DOZE_MASK) #define IOMUXC_GPR_GPR8_LPUART1_IPG_STOP_MODE_MASK (0x10000U) #define IOMUXC_GPR_GPR8_LPUART1_IPG_STOP_MODE_SHIFT (16U) +/*! LPUART1_IPG_STOP_MODE + * 0b0..the module is functional in Stop mode + * 0b1..the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted + */ #define IOMUXC_GPR_GPR8_LPUART1_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART1_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART1_IPG_STOP_MODE_MASK) #define IOMUXC_GPR_GPR8_LPUART1_IPG_DOZE_MASK (0x20000U) #define IOMUXC_GPR_GPR8_LPUART1_IPG_DOZE_SHIFT (17U) +/*! LPUART1_IPG_DOZE + * 0b0..not in doze mode + * 0b1..in doze mode + */ #define IOMUXC_GPR_GPR8_LPUART1_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART1_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART1_IPG_DOZE_MASK) #define IOMUXC_GPR_GPR8_LPUART2_IPG_STOP_MODE_MASK (0x40000U) #define IOMUXC_GPR_GPR8_LPUART2_IPG_STOP_MODE_SHIFT (18U) +/*! LPUART2_IPG_STOP_MODE + * 0b0..the module is functional in Stop mode + * 0b1..the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted + */ #define IOMUXC_GPR_GPR8_LPUART2_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART2_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART2_IPG_STOP_MODE_MASK) #define IOMUXC_GPR_GPR8_LPUART2_IPG_DOZE_MASK (0x80000U) #define IOMUXC_GPR_GPR8_LPUART2_IPG_DOZE_SHIFT (19U) +/*! LPUART2_IPG_DOZE + * 0b0..not in doze mode + * 0b1..in doze mode + */ #define IOMUXC_GPR_GPR8_LPUART2_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART2_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART2_IPG_DOZE_MASK) #define IOMUXC_GPR_GPR8_LPUART3_IPG_STOP_MODE_MASK (0x100000U) #define IOMUXC_GPR_GPR8_LPUART3_IPG_STOP_MODE_SHIFT (20U) +/*! LPUART3_IPG_STOP_MODE + * 0b0..the module is functional in Stop mode + * 0b1..the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted + */ #define IOMUXC_GPR_GPR8_LPUART3_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART3_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART3_IPG_STOP_MODE_MASK) #define IOMUXC_GPR_GPR8_LPUART3_IPG_DOZE_MASK (0x200000U) #define IOMUXC_GPR_GPR8_LPUART3_IPG_DOZE_SHIFT (21U) +/*! LPUART3_IPG_DOZE + * 0b0..not in doze mode + * 0b1..in doze mode + */ #define IOMUXC_GPR_GPR8_LPUART3_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART3_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART3_IPG_DOZE_MASK) #define IOMUXC_GPR_GPR8_LPUART4_IPG_STOP_MODE_MASK (0x400000U) #define IOMUXC_GPR_GPR8_LPUART4_IPG_STOP_MODE_SHIFT (22U) +/*! LPUART4_IPG_STOP_MODE + * 0b0..the module is functional in Stop mode + * 0b1..the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted + */ #define IOMUXC_GPR_GPR8_LPUART4_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART4_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART4_IPG_STOP_MODE_MASK) #define IOMUXC_GPR_GPR8_LPUART4_IPG_DOZE_MASK (0x800000U) #define IOMUXC_GPR_GPR8_LPUART4_IPG_DOZE_SHIFT (23U) +/*! LPUART4_IPG_DOZE + * 0b0..not in doze mode + * 0b1..in doze mode + */ #define IOMUXC_GPR_GPR8_LPUART4_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART4_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART4_IPG_DOZE_MASK) #define IOMUXC_GPR_GPR8_LPUART5_IPG_STOP_MODE_MASK (0x1000000U) #define IOMUXC_GPR_GPR8_LPUART5_IPG_STOP_MODE_SHIFT (24U) +/*! LPUART5_IPG_STOP_MODE + * 0b0..the module is functional in Stop mode + * 0b1..the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted + */ #define IOMUXC_GPR_GPR8_LPUART5_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART5_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART5_IPG_STOP_MODE_MASK) #define IOMUXC_GPR_GPR8_LPUART5_IPG_DOZE_MASK (0x2000000U) #define IOMUXC_GPR_GPR8_LPUART5_IPG_DOZE_SHIFT (25U) +/*! LPUART5_IPG_DOZE + * 0b0..not in doze mode + * 0b1..in doze mode + */ #define IOMUXC_GPR_GPR8_LPUART5_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART5_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART5_IPG_DOZE_MASK) #define IOMUXC_GPR_GPR8_LPUART6_IPG_STOP_MODE_MASK (0x4000000U) #define IOMUXC_GPR_GPR8_LPUART6_IPG_STOP_MODE_SHIFT (26U) +/*! LPUART6_IPG_STOP_MODE + * 0b0..the module is functional in Stop mode + * 0b1..the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted + */ #define IOMUXC_GPR_GPR8_LPUART6_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART6_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART6_IPG_STOP_MODE_MASK) #define IOMUXC_GPR_GPR8_LPUART6_IPG_DOZE_MASK (0x8000000U) #define IOMUXC_GPR_GPR8_LPUART6_IPG_DOZE_SHIFT (27U) +/*! LPUART6_IPG_DOZE + * 0b0..not in doze mode + * 0b1..in doze mode + */ #define IOMUXC_GPR_GPR8_LPUART6_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART6_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART6_IPG_DOZE_MASK) #define IOMUXC_GPR_GPR8_LPUART7_IPG_STOP_MODE_MASK (0x10000000U) #define IOMUXC_GPR_GPR8_LPUART7_IPG_STOP_MODE_SHIFT (28U) +/*! LPUART7_IPG_STOP_MODE + * 0b0..the module is functional in Stop mode + * 0b1..the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted + */ #define IOMUXC_GPR_GPR8_LPUART7_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART7_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART7_IPG_STOP_MODE_MASK) #define IOMUXC_GPR_GPR8_LPUART7_IPG_DOZE_MASK (0x20000000U) #define IOMUXC_GPR_GPR8_LPUART7_IPG_DOZE_SHIFT (29U) +/*! LPUART7_IPG_DOZE + * 0b0..not in doze mode + * 0b1..in doze mode + */ #define IOMUXC_GPR_GPR8_LPUART7_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART7_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART7_IPG_DOZE_MASK) #define IOMUXC_GPR_GPR8_LPUART8_IPG_STOP_MODE_MASK (0x40000000U) #define IOMUXC_GPR_GPR8_LPUART8_IPG_STOP_MODE_SHIFT (30U) +/*! LPUART8_IPG_STOP_MODE + * 0b0..the module is functional in Stop mode + * 0b1..the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted + */ #define IOMUXC_GPR_GPR8_LPUART8_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART8_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART8_IPG_STOP_MODE_MASK) #define IOMUXC_GPR_GPR8_LPUART8_IPG_DOZE_MASK (0x80000000U) #define IOMUXC_GPR_GPR8_LPUART8_IPG_DOZE_SHIFT (31U) +/*! LPUART8_IPG_DOZE + * 0b0..not in doze mode + * 0b1..in doze mode + */ #define IOMUXC_GPR_GPR8_LPUART8_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART8_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART8_IPG_DOZE_MASK) +/*! @} */ /*! @name GPR10 - GPR10 General Purpose Register */ +/*! @{ */ #define IOMUXC_GPR_GPR10_NIDEN_MASK (0x1U) #define IOMUXC_GPR_GPR10_NIDEN_SHIFT (0U) +/*! NIDEN + * 0b0..Debug turned off. + * 0b1..Debug enabled (default). + */ #define IOMUXC_GPR_GPR10_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_NIDEN_SHIFT)) & IOMUXC_GPR_GPR10_NIDEN_MASK) #define IOMUXC_GPR_GPR10_DBG_EN_MASK (0x2U) #define IOMUXC_GPR_GPR10_DBG_EN_SHIFT (1U) +/*! DBG_EN + * 0b0..Debug turned off. + * 0b1..Debug enabled (default). + */ #define IOMUXC_GPR_GPR10_DBG_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_DBG_EN_SHIFT)) & IOMUXC_GPR_GPR10_DBG_EN_MASK) #define IOMUXC_GPR_GPR10_SEC_ERR_RESP_MASK (0x4U) #define IOMUXC_GPR_GPR10_SEC_ERR_RESP_SHIFT (2U) +/*! SEC_ERR_RESP + * 0b0..OKEY response + * 0b1..SLVError (default) + */ #define IOMUXC_GPR_GPR10_SEC_ERR_RESP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_SEC_ERR_RESP_SHIFT)) & IOMUXC_GPR_GPR10_SEC_ERR_RESP_MASK) #define IOMUXC_GPR_GPR10_DCPKEY_OCOTP_OR_KEYMUX_MASK (0x10U) #define IOMUXC_GPR_GPR10_DCPKEY_OCOTP_OR_KEYMUX_SHIFT (4U) +/*! DCPKEY_OCOTP_OR_KEYMUX + * 0b0..Select key from Key MUX (SNVS/OTPMK). + * 0b1..Select key from OCOTP (SW_GP2). + */ #define IOMUXC_GPR_GPR10_DCPKEY_OCOTP_OR_KEYMUX(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_DCPKEY_OCOTP_OR_KEYMUX_SHIFT)) & IOMUXC_GPR_GPR10_DCPKEY_OCOTP_OR_KEYMUX_MASK) #define IOMUXC_GPR_GPR10_OCRAM_TZ_EN_MASK (0x100U) #define IOMUXC_GPR_GPR10_OCRAM_TZ_EN_SHIFT (8U) +/*! OCRAM_TZ_EN + * 0b0..The TrustZone feature is disabled. Entire OCRAM space is available for all access types (secure/non-secure/user/supervisor). + * 0b1..The TrustZone feature is enabled. Access to address in the range specified by [ENDADDR:STARTADDR] follows the execution mode access policy described in CSU chapter. + */ #define IOMUXC_GPR_GPR10_OCRAM_TZ_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_OCRAM_TZ_EN_SHIFT)) & IOMUXC_GPR_GPR10_OCRAM_TZ_EN_MASK) #define IOMUXC_GPR_GPR10_OCRAM_TZ_ADDR_MASK (0xFE00U) #define IOMUXC_GPR_GPR10_OCRAM_TZ_ADDR_SHIFT (9U) #define IOMUXC_GPR_GPR10_OCRAM_TZ_ADDR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_OCRAM_TZ_ADDR_SHIFT)) & IOMUXC_GPR_GPR10_OCRAM_TZ_ADDR_MASK) #define IOMUXC_GPR_GPR10_LOCK_NIDEN_MASK (0x10000U) #define IOMUXC_GPR_GPR10_LOCK_NIDEN_SHIFT (16U) +/*! LOCK_NIDEN + * 0b0..Field is not locked + * 0b1..Field is locked (read access only) + */ #define IOMUXC_GPR_GPR10_LOCK_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_LOCK_NIDEN_SHIFT)) & IOMUXC_GPR_GPR10_LOCK_NIDEN_MASK) #define IOMUXC_GPR_GPR10_LOCK_DBG_EN_MASK (0x20000U) #define IOMUXC_GPR_GPR10_LOCK_DBG_EN_SHIFT (17U) +/*! LOCK_DBG_EN + * 0b0..Field is not locked + * 0b1..Field is locked (read access only) + */ #define IOMUXC_GPR_GPR10_LOCK_DBG_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_LOCK_DBG_EN_SHIFT)) & IOMUXC_GPR_GPR10_LOCK_DBG_EN_MASK) #define IOMUXC_GPR_GPR10_LOCK_SEC_ERR_RESP_MASK (0x40000U) #define IOMUXC_GPR_GPR10_LOCK_SEC_ERR_RESP_SHIFT (18U) +/*! LOCK_SEC_ERR_RESP + * 0b0..Field is not locked + * 0b1..Field is locked (read access only) + */ #define IOMUXC_GPR_GPR10_LOCK_SEC_ERR_RESP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_LOCK_SEC_ERR_RESP_SHIFT)) & IOMUXC_GPR_GPR10_LOCK_SEC_ERR_RESP_MASK) #define IOMUXC_GPR_GPR10_LOCK_DCPKEY_OCOTP_OR_KEYMUX_MASK (0x100000U) #define IOMUXC_GPR_GPR10_LOCK_DCPKEY_OCOTP_OR_KEYMUX_SHIFT (20U) +/*! LOCK_DCPKEY_OCOTP_OR_KEYMUX + * 0b0..Field is not locked + * 0b1..Field is locked (read access only) + */ #define IOMUXC_GPR_GPR10_LOCK_DCPKEY_OCOTP_OR_KEYMUX(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_LOCK_DCPKEY_OCOTP_OR_KEYMUX_SHIFT)) & IOMUXC_GPR_GPR10_LOCK_DCPKEY_OCOTP_OR_KEYMUX_MASK) #define IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_EN_MASK (0x1000000U) #define IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_EN_SHIFT (24U) +/*! LOCK_OCRAM_TZ_EN + * 0b0..Field is not locked + * 0b1..Field is locked (read access only) + */ #define IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_EN_SHIFT)) & IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_EN_MASK) #define IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_ADDR_MASK (0xFE000000U) #define IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_ADDR_SHIFT (25U) +/*! LOCK_OCRAM_TZ_ADDR + * 0b0000000..Field is not locked + * 0b0000001..Field is locked (read access only) + */ #define IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_ADDR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_ADDR_SHIFT)) & IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_ADDR_MASK) +/*! @} */ /*! @name GPR11 - GPR11 General Purpose Register */ +/*! @{ */ #define IOMUXC_GPR_GPR11_M7_APC_AC_R0_CTRL_MASK (0x3U) #define IOMUXC_GPR_GPR11_M7_APC_AC_R0_CTRL_SHIFT (0U) +/*! M7_APC_AC_R0_CTRL + * 0b00..No access protection + * 0b01..M7 debug protection enabled + * 0b10..FlexSPI access protection + * 0b11..Both M7 debug and FlexSPI access are protected + */ #define IOMUXC_GPR_GPR11_M7_APC_AC_R0_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_M7_APC_AC_R0_CTRL_SHIFT)) & IOMUXC_GPR_GPR11_M7_APC_AC_R0_CTRL_MASK) #define IOMUXC_GPR_GPR11_M7_APC_AC_R1_CTRL_MASK (0xCU) #define IOMUXC_GPR_GPR11_M7_APC_AC_R1_CTRL_SHIFT (2U) +/*! M7_APC_AC_R1_CTRL + * 0b00..No access protection + * 0b01..M7 debug protection enabled + * 0b10..FlexSPI access protection + * 0b11..Both M7 debug and FlexSPI access are protected + */ #define IOMUXC_GPR_GPR11_M7_APC_AC_R1_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_M7_APC_AC_R1_CTRL_SHIFT)) & IOMUXC_GPR_GPR11_M7_APC_AC_R1_CTRL_MASK) #define IOMUXC_GPR_GPR11_M7_APC_AC_R2_CTRL_MASK (0x30U) #define IOMUXC_GPR_GPR11_M7_APC_AC_R2_CTRL_SHIFT (4U) +/*! M7_APC_AC_R2_CTRL + * 0b00..No access protection + * 0b01..M7 debug protection enabled + * 0b10..FlexSPI access protection + * 0b11..Both M7 debug and FlexSPI access are protected + */ #define IOMUXC_GPR_GPR11_M7_APC_AC_R2_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_M7_APC_AC_R2_CTRL_SHIFT)) & IOMUXC_GPR_GPR11_M7_APC_AC_R2_CTRL_MASK) #define IOMUXC_GPR_GPR11_M7_APC_AC_R3_CTRL_MASK (0xC0U) #define IOMUXC_GPR_GPR11_M7_APC_AC_R3_CTRL_SHIFT (6U) +/*! M7_APC_AC_R3_CTRL + * 0b00..No access protection + * 0b01..M7 debug protection enabled + * 0b10..FlexSPI access protection + * 0b11..Both M7 debug and FlexSPI access are protected + */ #define IOMUXC_GPR_GPR11_M7_APC_AC_R3_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_M7_APC_AC_R3_CTRL_SHIFT)) & IOMUXC_GPR_GPR11_M7_APC_AC_R3_CTRL_MASK) #define IOMUXC_GPR_GPR11_BEE_DE_RX_EN_MASK (0xF00U) #define IOMUXC_GPR_GPR11_BEE_DE_RX_EN_SHIFT (8U) @@ -12126,164 +19012,338 @@ typedef struct { #define IOMUXC_GPR_GPR11_LOCK_BEE_DE_RX_EN_MASK (0xF000000U) #define IOMUXC_GPR_GPR11_LOCK_BEE_DE_RX_EN_SHIFT (24U) #define IOMUXC_GPR_GPR11_LOCK_BEE_DE_RX_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_LOCK_BEE_DE_RX_EN_SHIFT)) & IOMUXC_GPR_GPR11_LOCK_BEE_DE_RX_EN_MASK) +/*! @} */ /*! @name GPR12 - GPR12 General Purpose Register */ +/*! @{ */ #define IOMUXC_GPR_GPR12_FLEXIO1_IPG_STOP_MODE_MASK (0x1U) #define IOMUXC_GPR_GPR12_FLEXIO1_IPG_STOP_MODE_SHIFT (0U) +/*! FLEXIO1_IPG_STOP_MODE + * 0b0..FlexIO1 is functional in Stop mode. + * 0b1..When this bit is equal to 1'b1 and ipg_stop is asserted, FlexIO1 is not functional in Stop mode. + */ #define IOMUXC_GPR_GPR12_FLEXIO1_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_FLEXIO1_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR12_FLEXIO1_IPG_STOP_MODE_MASK) #define IOMUXC_GPR_GPR12_FLEXIO1_IPG_DOZE_MASK (0x2U) #define IOMUXC_GPR_GPR12_FLEXIO1_IPG_DOZE_SHIFT (1U) +/*! FLEXIO1_IPG_DOZE + * 0b0..FLEXIO1 is not in doze mode + * 0b1..FLEXIO1 is in doze mode + */ #define IOMUXC_GPR_GPR12_FLEXIO1_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_FLEXIO1_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR12_FLEXIO1_IPG_DOZE_MASK) #define IOMUXC_GPR_GPR12_FLEXIO2_IPG_STOP_MODE_MASK (0x4U) #define IOMUXC_GPR_GPR12_FLEXIO2_IPG_STOP_MODE_SHIFT (2U) +/*! FLEXIO2_IPG_STOP_MODE + * 0b0..FlexIO2 is functional in Stop mode. + * 0b1..When this bit is equal to 1'b1 and ipg_stop is asserted, FlexIO2 is not functional in Stop mode. + */ #define IOMUXC_GPR_GPR12_FLEXIO2_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_FLEXIO2_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR12_FLEXIO2_IPG_STOP_MODE_MASK) #define IOMUXC_GPR_GPR12_FLEXIO2_IPG_DOZE_MASK (0x8U) #define IOMUXC_GPR_GPR12_FLEXIO2_IPG_DOZE_SHIFT (3U) +/*! FLEXIO2_IPG_DOZE + * 0b0..FLEXIO2 is not in doze mode + * 0b1..FLEXIO2 is in doze mode + */ #define IOMUXC_GPR_GPR12_FLEXIO2_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_FLEXIO2_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR12_FLEXIO2_IPG_DOZE_MASK) #define IOMUXC_GPR_GPR12_ACMP_IPG_STOP_MODE_MASK (0x10U) #define IOMUXC_GPR_GPR12_ACMP_IPG_STOP_MODE_SHIFT (4U) +/*! ACMP_IPG_STOP_MODE + * 0b0..ACMP is functional in Stop mode. + * 0b1..When this bit is equal to 1'b1 and ipg_stop is asserted, ACMP is not functional in Stop mode. + */ #define IOMUXC_GPR_GPR12_ACMP_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_ACMP_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR12_ACMP_IPG_STOP_MODE_MASK) +/*! @} */ /*! @name GPR13 - GPR13 General Purpose Register */ +/*! @{ */ #define IOMUXC_GPR_GPR13_ARCACHE_USDHC_MASK (0x1U) #define IOMUXC_GPR_GPR13_ARCACHE_USDHC_SHIFT (0U) +/*! ARCACHE_USDHC + * 0b0..Cacheable attribute is off for read transactions. + * 0b1..Cacheable attribute is on for read transactions. + */ #define IOMUXC_GPR_GPR13_ARCACHE_USDHC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR13_ARCACHE_USDHC_SHIFT)) & IOMUXC_GPR_GPR13_ARCACHE_USDHC_MASK) #define IOMUXC_GPR_GPR13_AWCACHE_USDHC_MASK (0x2U) #define IOMUXC_GPR_GPR13_AWCACHE_USDHC_SHIFT (1U) +/*! AWCACHE_USDHC + * 0b0..Cacheable attribute is off for write transactions. + * 0b1..Cacheable attribute is on for write transactions. + */ #define IOMUXC_GPR_GPR13_AWCACHE_USDHC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR13_AWCACHE_USDHC_SHIFT)) & IOMUXC_GPR_GPR13_AWCACHE_USDHC_MASK) #define IOMUXC_GPR_GPR13_CACHE_ENET_MASK (0x80U) #define IOMUXC_GPR_GPR13_CACHE_ENET_SHIFT (7U) +/*! CACHE_ENET + * 0b0..Cacheable attribute is off for read/write transactions. + * 0b1..Cacheable attribute is on for read/write transactions. + */ #define IOMUXC_GPR_GPR13_CACHE_ENET(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR13_CACHE_ENET_SHIFT)) & IOMUXC_GPR_GPR13_CACHE_ENET_MASK) #define IOMUXC_GPR_GPR13_CACHE_USB_MASK (0x2000U) #define IOMUXC_GPR_GPR13_CACHE_USB_SHIFT (13U) +/*! CACHE_USB + * 0b0..Cacheable attribute is off for read/write transactions. + * 0b1..Cacheable attribute is on for read/write transactions. + */ #define IOMUXC_GPR_GPR13_CACHE_USB(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR13_CACHE_USB_SHIFT)) & IOMUXC_GPR_GPR13_CACHE_USB_MASK) +/*! @} */ /*! @name GPR14 - GPR14 General Purpose Register */ +/*! @{ */ #define IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_DN_MASK (0x1U) #define IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_DN_SHIFT (0U) +/*! ACMP1_CMP_IGEN_TRIM_DN + * 0b0..no reduce + * 0b1..reduces + */ #define IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_DN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_DN_SHIFT)) & IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_DN_MASK) #define IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_DN_MASK (0x2U) #define IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_DN_SHIFT (1U) +/*! ACMP2_CMP_IGEN_TRIM_DN + * 0b0..no reduce + * 0b1..reduces + */ #define IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_DN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_DN_SHIFT)) & IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_DN_MASK) #define IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_DN_MASK (0x4U) #define IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_DN_SHIFT (2U) +/*! ACMP3_CMP_IGEN_TRIM_DN + * 0b0..no reduce + * 0b1..reduces + */ #define IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_DN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_DN_SHIFT)) & IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_DN_MASK) #define IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_DN_MASK (0x8U) #define IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_DN_SHIFT (3U) +/*! ACMP4_CMP_IGEN_TRIM_DN + * 0b0..no reduce + * 0b1..reduces + */ #define IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_DN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_DN_SHIFT)) & IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_DN_MASK) #define IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_UP_MASK (0x10U) #define IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_UP_SHIFT (4U) +/*! ACMP1_CMP_IGEN_TRIM_UP + * 0b0..no increase + * 0b1..increases + */ #define IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_UP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_UP_SHIFT)) & IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_UP_MASK) #define IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_UP_MASK (0x20U) #define IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_UP_SHIFT (5U) +/*! ACMP2_CMP_IGEN_TRIM_UP + * 0b0..no increase + * 0b1..increases + */ #define IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_UP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_UP_SHIFT)) & IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_UP_MASK) #define IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_UP_MASK (0x40U) #define IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_UP_SHIFT (6U) +/*! ACMP3_CMP_IGEN_TRIM_UP + * 0b0..no increase + * 0b1..increases + */ #define IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_UP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_UP_SHIFT)) & IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_UP_MASK) #define IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_UP_MASK (0x80U) #define IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_UP_SHIFT (7U) +/*! ACMP4_CMP_IGEN_TRIM_UP + * 0b0..no increase + * 0b1..increases + */ #define IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_UP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_UP_SHIFT)) & IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_UP_MASK) #define IOMUXC_GPR_GPR14_ACMP1_SAMPLE_SYNC_EN_MASK (0x100U) #define IOMUXC_GPR_GPR14_ACMP1_SAMPLE_SYNC_EN_SHIFT (8U) +/*! ACMP1_SAMPLE_SYNC_EN + * 0b0..select XBAR output + * 0b1..select synced sample_lv + */ #define IOMUXC_GPR_GPR14_ACMP1_SAMPLE_SYNC_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP1_SAMPLE_SYNC_EN_SHIFT)) & IOMUXC_GPR_GPR14_ACMP1_SAMPLE_SYNC_EN_MASK) #define IOMUXC_GPR_GPR14_ACMP2_SAMPLE_SYNC_EN_MASK (0x200U) #define IOMUXC_GPR_GPR14_ACMP2_SAMPLE_SYNC_EN_SHIFT (9U) +/*! ACMP2_SAMPLE_SYNC_EN + * 0b0..select XBAR output + * 0b1..select synced sample_lv + */ #define IOMUXC_GPR_GPR14_ACMP2_SAMPLE_SYNC_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP2_SAMPLE_SYNC_EN_SHIFT)) & IOMUXC_GPR_GPR14_ACMP2_SAMPLE_SYNC_EN_MASK) #define IOMUXC_GPR_GPR14_ACMP3_SAMPLE_SYNC_EN_MASK (0x400U) #define IOMUXC_GPR_GPR14_ACMP3_SAMPLE_SYNC_EN_SHIFT (10U) +/*! ACMP3_SAMPLE_SYNC_EN + * 0b0..select XBAR output + * 0b1..select synced sample_lv + */ #define IOMUXC_GPR_GPR14_ACMP3_SAMPLE_SYNC_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP3_SAMPLE_SYNC_EN_SHIFT)) & IOMUXC_GPR_GPR14_ACMP3_SAMPLE_SYNC_EN_MASK) #define IOMUXC_GPR_GPR14_ACMP4_SAMPLE_SYNC_EN_MASK (0x800U) #define IOMUXC_GPR_GPR14_ACMP4_SAMPLE_SYNC_EN_SHIFT (11U) +/*! ACMP4_SAMPLE_SYNC_EN + * 0b0..select XBAR output + * 0b1..select synced sample_lv + */ #define IOMUXC_GPR_GPR14_ACMP4_SAMPLE_SYNC_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP4_SAMPLE_SYNC_EN_SHIFT)) & IOMUXC_GPR_GPR14_ACMP4_SAMPLE_SYNC_EN_MASK) -#define IOMUXC_GPR_GPR14_CM7_MX6RT_CFGITCMSZ_MASK (0xF0000U) -#define IOMUXC_GPR_GPR14_CM7_MX6RT_CFGITCMSZ_SHIFT (16U) -#define IOMUXC_GPR_GPR14_CM7_MX6RT_CFGITCMSZ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_CM7_MX6RT_CFGITCMSZ_SHIFT)) & IOMUXC_GPR_GPR14_CM7_MX6RT_CFGITCMSZ_MASK) -#define IOMUXC_GPR_GPR14_CM7_MX6RT_CFGDTCMSZ_MASK (0xF00000U) -#define IOMUXC_GPR_GPR14_CM7_MX6RT_CFGDTCMSZ_SHIFT (20U) -#define IOMUXC_GPR_GPR14_CM7_MX6RT_CFGDTCMSZ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_CM7_MX6RT_CFGDTCMSZ_SHIFT)) & IOMUXC_GPR_GPR14_CM7_MX6RT_CFGDTCMSZ_MASK) +#define IOMUXC_GPR_GPR14_CM7_CFGITCMSZ_MASK (0xF0000U) +#define IOMUXC_GPR_GPR14_CM7_CFGITCMSZ_SHIFT (16U) +/*! CM7_CFGITCMSZ + * 0b0000..0 KB (No ITCM) + * 0b0011..4 KB + * 0b0100..8 KB + * 0b0101..16 KB + * 0b0110..32 KB + * 0b0111..64 KB + * 0b1000..128 KB + * 0b1001..256 KB + * 0b1010..512 KB + */ +#define IOMUXC_GPR_GPR14_CM7_CFGITCMSZ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_CM7_CFGITCMSZ_SHIFT)) & IOMUXC_GPR_GPR14_CM7_CFGITCMSZ_MASK) +#define IOMUXC_GPR_GPR14_CM7_CFGDTCMSZ_MASK (0xF00000U) +#define IOMUXC_GPR_GPR14_CM7_CFGDTCMSZ_SHIFT (20U) +/*! CM7_CFGDTCMSZ + * 0b0000..0 KB (No DTCM) + * 0b0011..4 KB + * 0b0100..8 KB + * 0b0101..16 KB + * 0b0110..32 KB + * 0b0111..64 KB + * 0b1000..128 KB + * 0b1001..256 KB + * 0b1010..512 KB + */ +#define IOMUXC_GPR_GPR14_CM7_CFGDTCMSZ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_CM7_CFGDTCMSZ_SHIFT)) & IOMUXC_GPR_GPR14_CM7_CFGDTCMSZ_MASK) +/*! @} */ /*! @name GPR16 - GPR16 General Purpose Register */ +/*! @{ */ #define IOMUXC_GPR_GPR16_INIT_ITCM_EN_MASK (0x1U) #define IOMUXC_GPR_GPR16_INIT_ITCM_EN_SHIFT (0U) +/*! INIT_ITCM_EN + * 0b0..ITCM is disabled + * 0b1..ITCM is enabled + */ #define IOMUXC_GPR_GPR16_INIT_ITCM_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR16_INIT_ITCM_EN_SHIFT)) & IOMUXC_GPR_GPR16_INIT_ITCM_EN_MASK) #define IOMUXC_GPR_GPR16_INIT_DTCM_EN_MASK (0x2U) #define IOMUXC_GPR_GPR16_INIT_DTCM_EN_SHIFT (1U) +/*! INIT_DTCM_EN + * 0b0..DTCM is disabled + * 0b1..DTCM is enabled + */ #define IOMUXC_GPR_GPR16_INIT_DTCM_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR16_INIT_DTCM_EN_SHIFT)) & IOMUXC_GPR_GPR16_INIT_DTCM_EN_MASK) #define IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL_MASK (0x4U) #define IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL_SHIFT (2U) +/*! FLEXRAM_BANK_CFG_SEL + * 0b0..use fuse value to config + * 0b1..use FLEXRAM_BANK_CFG to config + */ #define IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL_SHIFT)) & IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL_MASK) -#define IOMUXC_GPR_GPR16_CM7_INIT_VTOR_MASK (0xFFFFFF80U) -#define IOMUXC_GPR_GPR16_CM7_INIT_VTOR_SHIFT (7U) -#define IOMUXC_GPR_GPR16_CM7_INIT_VTOR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR16_CM7_INIT_VTOR_SHIFT)) & IOMUXC_GPR_GPR16_CM7_INIT_VTOR_MASK) +/*! @} */ /*! @name GPR17 - GPR17 General Purpose Register */ +/*! @{ */ #define IOMUXC_GPR_GPR17_FLEXRAM_BANK_CFG_MASK (0xFFFFFFFFU) #define IOMUXC_GPR_GPR17_FLEXRAM_BANK_CFG_SHIFT (0U) #define IOMUXC_GPR_GPR17_FLEXRAM_BANK_CFG(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR17_FLEXRAM_BANK_CFG_SHIFT)) & IOMUXC_GPR_GPR17_FLEXRAM_BANK_CFG_MASK) +/*! @} */ /*! @name GPR18 - GPR18 General Purpose Register */ +/*! @{ */ #define IOMUXC_GPR_GPR18_LOCK_M7_APC_AC_R0_BOT_MASK (0x1U) #define IOMUXC_GPR_GPR18_LOCK_M7_APC_AC_R0_BOT_SHIFT (0U) +/*! LOCK_M7_APC_AC_R0_BOT + * 0b0..Register field [31:1] is not locked + * 0b1..Register field [31:1] is locked (read access only) + */ #define IOMUXC_GPR_GPR18_LOCK_M7_APC_AC_R0_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR18_LOCK_M7_APC_AC_R0_BOT_SHIFT)) & IOMUXC_GPR_GPR18_LOCK_M7_APC_AC_R0_BOT_MASK) #define IOMUXC_GPR_GPR18_M7_APC_AC_R0_BOT_MASK (0xFFFFFFF8U) #define IOMUXC_GPR_GPR18_M7_APC_AC_R0_BOT_SHIFT (3U) #define IOMUXC_GPR_GPR18_M7_APC_AC_R0_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR18_M7_APC_AC_R0_BOT_SHIFT)) & IOMUXC_GPR_GPR18_M7_APC_AC_R0_BOT_MASK) +/*! @} */ /*! @name GPR19 - GPR19 General Purpose Register */ +/*! @{ */ #define IOMUXC_GPR_GPR19_LOCK_M7_APC_AC_R0_TOP_MASK (0x1U) #define IOMUXC_GPR_GPR19_LOCK_M7_APC_AC_R0_TOP_SHIFT (0U) +/*! LOCK_M7_APC_AC_R0_TOP + * 0b0..Register field [31:1] is not locked + * 0b1..Register field [31:1] is locked (read access only) + */ #define IOMUXC_GPR_GPR19_LOCK_M7_APC_AC_R0_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR19_LOCK_M7_APC_AC_R0_TOP_SHIFT)) & IOMUXC_GPR_GPR19_LOCK_M7_APC_AC_R0_TOP_MASK) #define IOMUXC_GPR_GPR19_M7_APC_AC_R0_TOP_MASK (0xFFFFFFF8U) #define IOMUXC_GPR_GPR19_M7_APC_AC_R0_TOP_SHIFT (3U) #define IOMUXC_GPR_GPR19_M7_APC_AC_R0_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR19_M7_APC_AC_R0_TOP_SHIFT)) & IOMUXC_GPR_GPR19_M7_APC_AC_R0_TOP_MASK) +/*! @} */ /*! @name GPR20 - GPR20 General Purpose Register */ +/*! @{ */ #define IOMUXC_GPR_GPR20_LOCK_M7_APC_AC_R1_BOT_MASK (0x1U) #define IOMUXC_GPR_GPR20_LOCK_M7_APC_AC_R1_BOT_SHIFT (0U) +/*! LOCK_M7_APC_AC_R1_BOT + * 0b0..Register field [31:1] is not locked + * 0b1..Register field [31:1] is locked (read access only) + */ #define IOMUXC_GPR_GPR20_LOCK_M7_APC_AC_R1_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_LOCK_M7_APC_AC_R1_BOT_SHIFT)) & IOMUXC_GPR_GPR20_LOCK_M7_APC_AC_R1_BOT_MASK) #define IOMUXC_GPR_GPR20_M7_APC_AC_R1_BOT_MASK (0xFFFFFFF8U) #define IOMUXC_GPR_GPR20_M7_APC_AC_R1_BOT_SHIFT (3U) #define IOMUXC_GPR_GPR20_M7_APC_AC_R1_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_M7_APC_AC_R1_BOT_SHIFT)) & IOMUXC_GPR_GPR20_M7_APC_AC_R1_BOT_MASK) +/*! @} */ /*! @name GPR21 - GPR21 General Purpose Register */ +/*! @{ */ #define IOMUXC_GPR_GPR21_LOCK_M7_APC_AC_R1_TOP_MASK (0x1U) #define IOMUXC_GPR_GPR21_LOCK_M7_APC_AC_R1_TOP_SHIFT (0U) +/*! LOCK_M7_APC_AC_R1_TOP + * 0b0..Register field [31:1] is not locked + * 0b1..Register field [31:1] is locked (read access only) + */ #define IOMUXC_GPR_GPR21_LOCK_M7_APC_AC_R1_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR21_LOCK_M7_APC_AC_R1_TOP_SHIFT)) & IOMUXC_GPR_GPR21_LOCK_M7_APC_AC_R1_TOP_MASK) #define IOMUXC_GPR_GPR21_M7_APC_AC_R1_TOP_MASK (0xFFFFFFF8U) #define IOMUXC_GPR_GPR21_M7_APC_AC_R1_TOP_SHIFT (3U) #define IOMUXC_GPR_GPR21_M7_APC_AC_R1_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR21_M7_APC_AC_R1_TOP_SHIFT)) & IOMUXC_GPR_GPR21_M7_APC_AC_R1_TOP_MASK) +/*! @} */ /*! @name GPR22 - GPR22 General Purpose Register */ +/*! @{ */ #define IOMUXC_GPR_GPR22_LOCK_M7_APC_AC_R2_BOT_MASK (0x1U) #define IOMUXC_GPR_GPR22_LOCK_M7_APC_AC_R2_BOT_SHIFT (0U) +/*! LOCK_M7_APC_AC_R2_BOT + * 0b0..Register field [31:1] is not locked + * 0b1..Register field [31:1] is locked (read access only) + */ #define IOMUXC_GPR_GPR22_LOCK_M7_APC_AC_R2_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR22_LOCK_M7_APC_AC_R2_BOT_SHIFT)) & IOMUXC_GPR_GPR22_LOCK_M7_APC_AC_R2_BOT_MASK) #define IOMUXC_GPR_GPR22_M7_APC_AC_R2_BOT_MASK (0xFFFFFFF8U) #define IOMUXC_GPR_GPR22_M7_APC_AC_R2_BOT_SHIFT (3U) #define IOMUXC_GPR_GPR22_M7_APC_AC_R2_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR22_M7_APC_AC_R2_BOT_SHIFT)) & IOMUXC_GPR_GPR22_M7_APC_AC_R2_BOT_MASK) +/*! @} */ /*! @name GPR23 - GPR23 General Purpose Register */ -#define IOMUXC_GPR_GPR23_LOCK_M7_APC_AC_R1_TOP_MASK (0x1U) -#define IOMUXC_GPR_GPR23_LOCK_M7_APC_AC_R1_TOP_SHIFT (0U) -#define IOMUXC_GPR_GPR23_LOCK_M7_APC_AC_R1_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR23_LOCK_M7_APC_AC_R1_TOP_SHIFT)) & IOMUXC_GPR_GPR23_LOCK_M7_APC_AC_R1_TOP_MASK) +/*! @{ */ +#define IOMUXC_GPR_GPR23_LOCK_M7_APC_AC_R2_TOP_MASK (0x1U) +#define IOMUXC_GPR_GPR23_LOCK_M7_APC_AC_R2_TOP_SHIFT (0U) +/*! LOCK_M7_APC_AC_R2_TOP + * 0b0..Register field [31:1] is not locked + * 0b1..Register field [31:1] is locked (read access only) + */ +#define IOMUXC_GPR_GPR23_LOCK_M7_APC_AC_R2_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR23_LOCK_M7_APC_AC_R2_TOP_SHIFT)) & IOMUXC_GPR_GPR23_LOCK_M7_APC_AC_R2_TOP_MASK) #define IOMUXC_GPR_GPR23_M7_APC_AC_R2_TOP_MASK (0xFFFFFFF8U) #define IOMUXC_GPR_GPR23_M7_APC_AC_R2_TOP_SHIFT (3U) #define IOMUXC_GPR_GPR23_M7_APC_AC_R2_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR23_M7_APC_AC_R2_TOP_SHIFT)) & IOMUXC_GPR_GPR23_M7_APC_AC_R2_TOP_MASK) +/*! @} */ /*! @name GPR24 - GPR24 General Purpose Register */ +/*! @{ */ #define IOMUXC_GPR_GPR24_LOCK_M7_APC_AC_R3_BOT_MASK (0x1U) #define IOMUXC_GPR_GPR24_LOCK_M7_APC_AC_R3_BOT_SHIFT (0U) +/*! LOCK_M7_APC_AC_R3_BOT + * 0b0..Register field [31:1] is not locked + * 0b1..Register field [31:1] is locked (read access only) + */ #define IOMUXC_GPR_GPR24_LOCK_M7_APC_AC_R3_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR24_LOCK_M7_APC_AC_R3_BOT_SHIFT)) & IOMUXC_GPR_GPR24_LOCK_M7_APC_AC_R3_BOT_MASK) -#define IOMUXC_GPR_GPR24_M7_APC_AC_R2_BOT_MASK (0xFFFFFFF8U) -#define IOMUXC_GPR_GPR24_M7_APC_AC_R2_BOT_SHIFT (3U) -#define IOMUXC_GPR_GPR24_M7_APC_AC_R2_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR24_M7_APC_AC_R2_BOT_SHIFT)) & IOMUXC_GPR_GPR24_M7_APC_AC_R2_BOT_MASK) +#define IOMUXC_GPR_GPR24_M7_APC_AC_R3_BOT_MASK (0xFFFFFFF8U) +#define IOMUXC_GPR_GPR24_M7_APC_AC_R3_BOT_SHIFT (3U) +#define IOMUXC_GPR_GPR24_M7_APC_AC_R3_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR24_M7_APC_AC_R3_BOT_SHIFT)) & IOMUXC_GPR_GPR24_M7_APC_AC_R3_BOT_MASK) +/*! @} */ /*! @name GPR25 - GPR25 General Purpose Register */ +/*! @{ */ #define IOMUXC_GPR_GPR25_LOCK_M7_APC_AC_R3_TOP_MASK (0x1U) #define IOMUXC_GPR_GPR25_LOCK_M7_APC_AC_R3_TOP_SHIFT (0U) +/*! LOCK_M7_APC_AC_R3_TOP + * 0b0..Register field [31:1] is not locked + * 0b1..Register field [31:1] is locked (read access only) + */ #define IOMUXC_GPR_GPR25_LOCK_M7_APC_AC_R3_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR25_LOCK_M7_APC_AC_R3_TOP_SHIFT)) & IOMUXC_GPR_GPR25_LOCK_M7_APC_AC_R3_TOP_MASK) #define IOMUXC_GPR_GPR25_M7_APC_AC_R3_TOP_MASK (0xFFFFFFF8U) #define IOMUXC_GPR_GPR25_M7_APC_AC_R3_TOP_SHIFT (3U) #define IOMUXC_GPR_GPR25_M7_APC_AC_R3_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR25_M7_APC_AC_R3_TOP_SHIFT)) & IOMUXC_GPR_GPR25_M7_APC_AC_R3_TOP_MASK) +/*! @} */ /*! @@ -12338,184 +19398,460 @@ typedef struct { */ /*! @name SW_MUX_CTL_PAD_WAKEUP - SW_MUX_CTL_PAD_WAKEUP SW MUX Control Register */ +/*! @{ */ #define IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_MUX_MODE_MASK (0x7U) #define IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_MUX_MODE_SHIFT (0U) +/*! MUX_MODE - MUX Mode Select Field. + * 0b101..Select mux mode: ALT5 mux port: GPIO5_IO00 of instance: gpio5 + * 0b111..Select mux mode: ALT7 mux port: NMI_GLUE_NMI of instance: nmi_glue + */ #define IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_MUX_MODE_MASK) #define IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_SION_MASK (0x10U) #define IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_SION_SHIFT (4U) +/*! SION - Software Input On Field. + * 0b1..Force input path of pad WAKEUP + * 0b0..Input Path is determined by functionality + */ #define IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_SION_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_SION_MASK) +/*! @} */ /*! @name SW_MUX_CTL_PAD_PMIC_ON_REQ - SW_MUX_CTL_PAD_PMIC_ON_REQ SW MUX Control Register */ +/*! @{ */ #define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_MUX_MODE_MASK (0x7U) #define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_MUX_MODE_SHIFT (0U) +/*! MUX_MODE - MUX Mode Select Field. + * 0b000..Select mux mode: ALT0 mux port: SNVS_LP_PMIC_ON_REQ of instance: snvs_lp + * 0b101..Select mux mode: ALT5 mux port: GPIO5_IO01 of instance: gpio5 + */ #define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_MUX_MODE_MASK) #define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_SION_MASK (0x10U) #define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_SION_SHIFT (4U) +/*! SION - Software Input On Field. + * 0b1..Force input path of pad PMIC_ON_REQ + * 0b0..Input Path is determined by functionality + */ #define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_SION_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_SION_MASK) +/*! @} */ /*! @name SW_MUX_CTL_PAD_PMIC_STBY_REQ - SW_MUX_CTL_PAD_PMIC_STBY_REQ SW MUX Control Register */ +/*! @{ */ #define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_MUX_MODE_MASK (0x7U) #define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_MUX_MODE_SHIFT (0U) +/*! MUX_MODE - MUX Mode Select Field. + * 0b000..Select mux mode: ALT0 mux port: CCM_PMIC_VSTBY_REQ of instance: ccm + * 0b101..Select mux mode: ALT5 mux port: GPIO5_IO02 of instance: gpio5 + */ #define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_MUX_MODE_MASK) #define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_SION_MASK (0x10U) #define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_SION_SHIFT (4U) +/*! SION - Software Input On Field. + * 0b1..Force input path of pad PMIC_STBY_REQ + * 0b0..Input Path is determined by functionality + */ #define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_SION_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_SION_MASK) +/*! @} */ /*! @name SW_PAD_CTL_PAD_TEST_MODE - SW_PAD_CTL_PAD_TEST_MODE SW PAD Control Register */ +/*! @{ */ #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SRE_MASK (0x1U) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SRE_SHIFT (0U) +/*! SRE - Slew Rate Field + * 0b0..Slow Slew Rate + * 0b1..Fast Slew Rate + */ #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SRE_MASK) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DSE_MASK (0x38U) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DSE_SHIFT (3U) +/*! DSE - Drive Strength Field + * 0b000..output driver disabled; + * 0b001..R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + * 0b010..R0/2 + * 0b011..R0/3 + * 0b100..R0/4 + * 0b101..R0/5 + * 0b110..R0/6 + * 0b111..R0/7 + */ #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DSE_MASK) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SPEED_MASK (0xC0U) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SPEED_SHIFT (6U) +/*! SPEED - Speed Field + * 0b10..medium(100MHz) + */ #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SPEED(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SPEED_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SPEED_MASK) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_ODE_MASK (0x800U) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_ODE_SHIFT (11U) +/*! ODE - Open Drain Enable Field + * 0b0..Open Drain Disabled + * 0b1..Open Drain Enabled + */ #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_ODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_ODE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_ODE_MASK) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PKE_MASK (0x1000U) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PKE_SHIFT (12U) +/*! PKE - Pull / Keep Enable Field + * 0b0..Pull/Keeper Disabled + * 0b1..Pull/Keeper Enabled + */ #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PKE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PKE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PKE_MASK) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUE_MASK (0x2000U) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUE_SHIFT (13U) +/*! PUE - Pull / Keep Select Field + * 0b0..Keeper + * 0b1..Pull + */ #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUE_MASK) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUS_MASK (0xC000U) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUS_SHIFT (14U) +/*! PUS - Pull Up / Down Config. Field + * 0b00..100K Ohm Pull Down + * 0b01..47K Ohm Pull Up + * 0b10..100K Ohm Pull Up + * 0b11..22K Ohm Pull Up + */ #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUS_MASK) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_HYS_MASK (0x10000U) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_HYS_SHIFT (16U) +/*! HYS - Hyst. Enable Field + * 0b0..Hysteresis Disabled + * 0b1..Hysteresis Enabled + */ #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_HYS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_HYS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_HYS_MASK) +/*! @} */ /*! @name SW_PAD_CTL_PAD_POR_B - SW_PAD_CTL_PAD_POR_B SW PAD Control Register */ +/*! @{ */ #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SRE_MASK (0x1U) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SRE_SHIFT (0U) +/*! SRE - Slew Rate Field + * 0b0..Slow Slew Rate + * 0b1..Fast Slew Rate + */ #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SRE_MASK) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DSE_MASK (0x38U) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DSE_SHIFT (3U) +/*! DSE - Drive Strength Field + * 0b000..output driver disabled; + * 0b001..R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + * 0b010..R0/2 + * 0b011..R0/3 + * 0b100..R0/4 + * 0b101..R0/5 + * 0b110..R0/6 + * 0b111..R0/7 + */ #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DSE_MASK) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SPEED_MASK (0xC0U) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SPEED_SHIFT (6U) +/*! SPEED - Speed Field + * 0b10..medium(100MHz) + */ #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SPEED(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SPEED_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SPEED_MASK) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_ODE_MASK (0x800U) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_ODE_SHIFT (11U) +/*! ODE - Open Drain Enable Field + * 0b0..Open Drain Disabled + * 0b1..Open Drain Enabled + */ #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_ODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_ODE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_ODE_MASK) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PKE_MASK (0x1000U) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PKE_SHIFT (12U) +/*! PKE - Pull / Keep Enable Field + * 0b0..Pull/Keeper Disabled + * 0b1..Pull/Keeper Enabled + */ #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PKE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PKE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PKE_MASK) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUE_MASK (0x2000U) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUE_SHIFT (13U) +/*! PUE - Pull / Keep Select Field + * 0b0..Keeper + * 0b1..Pull + */ #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUE_MASK) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUS_MASK (0xC000U) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUS_SHIFT (14U) +/*! PUS - Pull Up / Down Config. Field + * 0b00..100K Ohm Pull Down + * 0b01..47K Ohm Pull Up + * 0b10..100K Ohm Pull Up + * 0b11..22K Ohm Pull Up + */ #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUS_MASK) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_HYS_MASK (0x10000U) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_HYS_SHIFT (16U) +/*! HYS - Hyst. Enable Field + * 0b0..Hysteresis Disabled + * 0b1..Hysteresis Enabled + */ #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_HYS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_HYS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_HYS_MASK) +/*! @} */ /*! @name SW_PAD_CTL_PAD_ONOFF - SW_PAD_CTL_PAD_ONOFF SW PAD Control Register */ +/*! @{ */ #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SRE_MASK (0x1U) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SRE_SHIFT (0U) +/*! SRE - Slew Rate Field + * 0b0..Slow Slew Rate + * 0b1..Fast Slew Rate + */ #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SRE_MASK) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DSE_MASK (0x38U) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DSE_SHIFT (3U) +/*! DSE - Drive Strength Field + * 0b000..output driver disabled; + * 0b001..R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + * 0b010..R0/2 + * 0b011..R0/3 + * 0b100..R0/4 + * 0b101..R0/5 + * 0b110..R0/6 + * 0b111..R0/7 + */ #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DSE_MASK) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SPEED_MASK (0xC0U) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SPEED_SHIFT (6U) +/*! SPEED - Speed Field + * 0b10..medium(100MHz) + */ #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SPEED(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SPEED_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SPEED_MASK) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_ODE_MASK (0x800U) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_ODE_SHIFT (11U) +/*! ODE - Open Drain Enable Field + * 0b0..Open Drain Disabled + * 0b1..Open Drain Enabled + */ #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_ODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_ODE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_ODE_MASK) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PKE_MASK (0x1000U) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PKE_SHIFT (12U) +/*! PKE - Pull / Keep Enable Field + * 0b0..Pull/Keeper Disabled + * 0b1..Pull/Keeper Enabled + */ #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PKE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PKE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PKE_MASK) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUE_MASK (0x2000U) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUE_SHIFT (13U) +/*! PUE - Pull / Keep Select Field + * 0b0..Keeper + * 0b1..Pull + */ #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUE_MASK) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUS_MASK (0xC000U) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUS_SHIFT (14U) +/*! PUS - Pull Up / Down Config. Field + * 0b00..100K Ohm Pull Down + * 0b01..47K Ohm Pull Up + * 0b10..100K Ohm Pull Up + * 0b11..22K Ohm Pull Up + */ #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUS_MASK) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_HYS_MASK (0x10000U) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_HYS_SHIFT (16U) +/*! HYS - Hyst. Enable Field + * 0b0..Hysteresis Disabled + * 0b1..Hysteresis Enabled + */ #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_HYS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_HYS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_HYS_MASK) +/*! @} */ /*! @name SW_PAD_CTL_PAD_WAKEUP - SW_PAD_CTL_PAD_WAKEUP SW PAD Control Register */ +/*! @{ */ #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SRE_MASK (0x1U) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SRE_SHIFT (0U) +/*! SRE - Slew Rate Field + * 0b0..Slow Slew Rate + * 0b1..Fast Slew Rate + */ #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SRE_MASK) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DSE_MASK (0x38U) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DSE_SHIFT (3U) +/*! DSE - Drive Strength Field + * 0b000..output driver disabled; + * 0b001..R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + * 0b010..R0/2 + * 0b011..R0/3 + * 0b100..R0/4 + * 0b101..R0/5 + * 0b110..R0/6 + * 0b111..R0/7 + */ #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DSE_MASK) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SPEED_MASK (0xC0U) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SPEED_SHIFT (6U) +/*! SPEED - Speed Field + * 0b10..medium(100MHz) + */ #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SPEED(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SPEED_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SPEED_MASK) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_ODE_MASK (0x800U) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_ODE_SHIFT (11U) +/*! ODE - Open Drain Enable Field + * 0b0..Open Drain Disabled + * 0b1..Open Drain Enabled + */ #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_ODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_ODE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_ODE_MASK) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PKE_MASK (0x1000U) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PKE_SHIFT (12U) +/*! PKE - Pull / Keep Enable Field + * 0b0..Pull/Keeper Disabled + * 0b1..Pull/Keeper Enabled + */ #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PKE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PKE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PKE_MASK) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUE_MASK (0x2000U) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUE_SHIFT (13U) +/*! PUE - Pull / Keep Select Field + * 0b0..Keeper + * 0b1..Pull + */ #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUE_MASK) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUS_MASK (0xC000U) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUS_SHIFT (14U) +/*! PUS - Pull Up / Down Config. Field + * 0b00..100K Ohm Pull Down + * 0b01..47K Ohm Pull Up + * 0b10..100K Ohm Pull Up + * 0b11..22K Ohm Pull Up + */ #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUS_MASK) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_HYS_MASK (0x10000U) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_HYS_SHIFT (16U) +/*! HYS - Hyst. Enable Field + * 0b0..Hysteresis Disabled + * 0b1..Hysteresis Enabled + */ #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_HYS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_HYS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_HYS_MASK) +/*! @} */ /*! @name SW_PAD_CTL_PAD_PMIC_ON_REQ - SW_PAD_CTL_PAD_PMIC_ON_REQ SW PAD Control Register */ +/*! @{ */ #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SRE_MASK (0x1U) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SRE_SHIFT (0U) +/*! SRE - Slew Rate Field + * 0b0..Slow Slew Rate + * 0b1..Fast Slew Rate + */ #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SRE_MASK) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DSE_MASK (0x38U) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DSE_SHIFT (3U) +/*! DSE - Drive Strength Field + * 0b000..output driver disabled; + * 0b001..R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + * 0b010..R0/2 + * 0b011..R0/3 + * 0b100..R0/4 + * 0b101..R0/5 + * 0b110..R0/6 + * 0b111..R0/7 + */ #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DSE_MASK) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SPEED_MASK (0xC0U) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SPEED_SHIFT (6U) +/*! SPEED - Speed Field + * 0b10..medium(100MHz) + */ #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SPEED(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SPEED_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SPEED_MASK) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_ODE_MASK (0x800U) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_ODE_SHIFT (11U) +/*! ODE - Open Drain Enable Field + * 0b0..Open Drain Disabled + * 0b1..Open Drain Enabled + */ #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_ODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_ODE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_ODE_MASK) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PKE_MASK (0x1000U) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PKE_SHIFT (12U) +/*! PKE - Pull / Keep Enable Field + * 0b0..Pull/Keeper Disabled + * 0b1..Pull/Keeper Enabled + */ #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PKE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PKE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PKE_MASK) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUE_MASK (0x2000U) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUE_SHIFT (13U) +/*! PUE - Pull / Keep Select Field + * 0b0..Keeper + * 0b1..Pull + */ #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUE_MASK) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUS_MASK (0xC000U) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUS_SHIFT (14U) +/*! PUS - Pull Up / Down Config. Field + * 0b00..100K Ohm Pull Down + * 0b01..47K Ohm Pull Up + * 0b10..100K Ohm Pull Up + * 0b11..22K Ohm Pull Up + */ #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUS_MASK) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_HYS_MASK (0x10000U) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_HYS_SHIFT (16U) +/*! HYS - Hyst. Enable Field + * 0b0..Hysteresis Disabled + * 0b1..Hysteresis Enabled + */ #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_HYS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_HYS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_HYS_MASK) +/*! @} */ /*! @name SW_PAD_CTL_PAD_PMIC_STBY_REQ - SW_PAD_CTL_PAD_PMIC_STBY_REQ SW PAD Control Register */ +/*! @{ */ #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SRE_MASK (0x1U) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SRE_SHIFT (0U) +/*! SRE - Slew Rate Field + * 0b0..Slow Slew Rate + * 0b1..Fast Slew Rate + */ #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SRE_MASK) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DSE_MASK (0x38U) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DSE_SHIFT (3U) +/*! DSE - Drive Strength Field + * 0b000..output driver disabled; + * 0b001..R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + * 0b010..R0/2 + * 0b011..R0/3 + * 0b100..R0/4 + * 0b101..R0/5 + * 0b110..R0/6 + * 0b111..R0/7 + */ #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DSE_MASK) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SPEED_MASK (0xC0U) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SPEED_SHIFT (6U) +/*! SPEED - Speed Field + * 0b10..medium(100MHz) + */ #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SPEED(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SPEED_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SPEED_MASK) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_ODE_MASK (0x800U) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_ODE_SHIFT (11U) +/*! ODE - Open Drain Enable Field + * 0b0..Open Drain Disabled + * 0b1..Open Drain Enabled + */ #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_ODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_ODE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_ODE_MASK) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PKE_MASK (0x1000U) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PKE_SHIFT (12U) +/*! PKE - Pull / Keep Enable Field + * 0b0..Pull/Keeper Disabled + * 0b1..Pull/Keeper Enabled + */ #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PKE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PKE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PKE_MASK) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUE_MASK (0x2000U) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUE_SHIFT (13U) +/*! PUE - Pull / Keep Select Field + * 0b0..Keeper + * 0b1..Pull + */ #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUE_MASK) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUS_MASK (0xC000U) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUS_SHIFT (14U) +/*! PUS - Pull Up / Down Config. Field + * 0b00..100K Ohm Pull Down + * 0b01..47K Ohm Pull Up + * 0b10..100K Ohm Pull Up + * 0b11..22K Ohm Pull Up + */ #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUS_MASK) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_HYS_MASK (0x10000U) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_HYS_SHIFT (16U) +/*! HYS - Hyst. Enable Field + * 0b0..Hysteresis Disabled + * 0b1..Hysteresis Enabled + */ #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_HYS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_HYS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_HYS_MASK) +/*! @} */ /*! @@ -12565,6 +19901,7 @@ typedef struct { */ /*! @name GPR3 - GPR3 General Purpose Register */ +/*! @{ */ #define IOMUXC_SNVS_GPR_GPR3_LPSR_MODE_ENABLE_MASK (0x1U) #define IOMUXC_SNVS_GPR_GPR3_LPSR_MODE_ENABLE_SHIFT (0U) #define IOMUXC_SNVS_GPR_GPR3_LPSR_MODE_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR3_LPSR_MODE_ENABLE_SHIFT)) & IOMUXC_SNVS_GPR_GPR3_LPSR_MODE_ENABLE_MASK) @@ -12574,9 +19911,9 @@ typedef struct { #define IOMUXC_SNVS_GPR_GPR3_POR_PULL_TYPE_MASK (0xCU) #define IOMUXC_SNVS_GPR_GPR3_POR_PULL_TYPE_SHIFT (2U) #define IOMUXC_SNVS_GPR_GPR3_POR_PULL_TYPE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR3_POR_PULL_TYPE_SHIFT)) & IOMUXC_SNVS_GPR_GPR3_POR_PULL_TYPE_MASK) -#define IOMUXC_SNVS_GPR_GPR3_DCDC_LOW_BAT_MASK (0x10000U) -#define IOMUXC_SNVS_GPR_GPR3_DCDC_LOW_BAT_SHIFT (16U) -#define IOMUXC_SNVS_GPR_GPR3_DCDC_LOW_BAT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR3_DCDC_LOW_BAT_SHIFT)) & IOMUXC_SNVS_GPR_GPR3_DCDC_LOW_BAT_MASK) +#define IOMUXC_SNVS_GPR_GPR3_DCDC_IN_LOW_VOL_MASK (0x10000U) +#define IOMUXC_SNVS_GPR_GPR3_DCDC_IN_LOW_VOL_SHIFT (16U) +#define IOMUXC_SNVS_GPR_GPR3_DCDC_IN_LOW_VOL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR3_DCDC_IN_LOW_VOL_SHIFT)) & IOMUXC_SNVS_GPR_GPR3_DCDC_IN_LOW_VOL_MASK) #define IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_CUR_MASK (0x20000U) #define IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_CUR_SHIFT (17U) #define IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_CUR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_CUR_SHIFT)) & IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_CUR_MASK) @@ -12586,6 +19923,7 @@ typedef struct { #define IOMUXC_SNVS_GPR_GPR3_DCDC_STS_DC_OK_MASK (0x80000U) #define IOMUXC_SNVS_GPR_GPR3_DCDC_STS_DC_OK_SHIFT (19U) #define IOMUXC_SNVS_GPR_GPR3_DCDC_STS_DC_OK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR3_DCDC_STS_DC_OK_SHIFT)) & IOMUXC_SNVS_GPR_GPR3_DCDC_STS_DC_OK_MASK) +/*! @} */ /*! @@ -12635,48 +19973,96 @@ typedef struct { */ /*! @name KPCR - Keypad Control Register */ +/*! @{ */ #define KPP_KPCR_KRE_MASK (0xFFU) #define KPP_KPCR_KRE_SHIFT (0U) +/*! KRE + * 0b00000000..Row is not included in the keypad key press detect. + * 0b00000001..Row is included in the keypad key press detect. + */ #define KPP_KPCR_KRE(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPCR_KRE_SHIFT)) & KPP_KPCR_KRE_MASK) #define KPP_KPCR_KCO_MASK (0xFF00U) #define KPP_KPCR_KCO_SHIFT (8U) +/*! KCO + * 0b00000000..Column strobe output is totem pole drive. + * 0b00000001..Column strobe output is open drain. + */ #define KPP_KPCR_KCO(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPCR_KCO_SHIFT)) & KPP_KPCR_KCO_MASK) +/*! @} */ /*! @name KPSR - Keypad Status Register */ +/*! @{ */ #define KPP_KPSR_KPKD_MASK (0x1U) #define KPP_KPSR_KPKD_SHIFT (0U) +/*! KPKD + * 0b0..No key presses detected + * 0b1..A key has been depressed + */ #define KPP_KPSR_KPKD(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KPKD_SHIFT)) & KPP_KPSR_KPKD_MASK) #define KPP_KPSR_KPKR_MASK (0x2U) #define KPP_KPSR_KPKR_SHIFT (1U) +/*! KPKR + * 0b0..No key release detected + * 0b1..All keys have been released + */ #define KPP_KPSR_KPKR(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KPKR_SHIFT)) & KPP_KPSR_KPKR_MASK) #define KPP_KPSR_KDSC_MASK (0x4U) #define KPP_KPSR_KDSC_SHIFT (2U) +/*! KDSC + * 0b0..No effect + * 0b1..Set bits that clear the keypad depress synchronizer chain + */ #define KPP_KPSR_KDSC(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KDSC_SHIFT)) & KPP_KPSR_KDSC_MASK) #define KPP_KPSR_KRSS_MASK (0x8U) #define KPP_KPSR_KRSS_SHIFT (3U) +/*! KRSS + * 0b0..No effect + * 0b1..Set bits which sets keypad release synchronizer chain + */ #define KPP_KPSR_KRSS(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KRSS_SHIFT)) & KPP_KPSR_KRSS_MASK) #define KPP_KPSR_KDIE_MASK (0x100U) #define KPP_KPSR_KDIE_SHIFT (8U) +/*! KDIE + * 0b0..No interrupt request is generated when KPKD is set. + * 0b1..An interrupt request is generated when KPKD is set. + */ #define KPP_KPSR_KDIE(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KDIE_SHIFT)) & KPP_KPSR_KDIE_MASK) #define KPP_KPSR_KRIE_MASK (0x200U) #define KPP_KPSR_KRIE_SHIFT (9U) +/*! KRIE + * 0b0..No interrupt request is generated when KPKR is set. + * 0b1..An interrupt request is generated when KPKR is set. + */ #define KPP_KPSR_KRIE(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KRIE_SHIFT)) & KPP_KPSR_KRIE_MASK) +/*! @} */ /*! @name KDDR - Keypad Data Direction Register */ +/*! @{ */ #define KPP_KDDR_KRDD_MASK (0xFFU) #define KPP_KDDR_KRDD_SHIFT (0U) +/*! KRDD + * 0b00000000..ROWn pin configured as an input. + * 0b00000001..ROWn pin configured as an output. + */ #define KPP_KDDR_KRDD(x) (((uint16_t)(((uint16_t)(x)) << KPP_KDDR_KRDD_SHIFT)) & KPP_KDDR_KRDD_MASK) #define KPP_KDDR_KCDD_MASK (0xFF00U) #define KPP_KDDR_KCDD_SHIFT (8U) +/*! KCDD + * 0b00000000..COLn pin is configured as an input. + * 0b00000001..COLn pin is configured as an output. + */ #define KPP_KDDR_KCDD(x) (((uint16_t)(((uint16_t)(x)) << KPP_KDDR_KCDD_SHIFT)) & KPP_KDDR_KCDD_MASK) +/*! @} */ /*! @name KPDR - Keypad Data Register */ +/*! @{ */ #define KPP_KPDR_KRD_MASK (0xFFU) #define KPP_KPDR_KRD_SHIFT (0U) #define KPP_KPDR_KRD(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPDR_KRD_SHIFT)) & KPP_KPDR_KRD_MASK) #define KPP_KPDR_KCD_MASK (0xFF00U) #define KPP_KPDR_KCD_SHIFT (8U) #define KPP_KPDR_KCD(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPDR_KCD_SHIFT)) & KPP_KPDR_KCD_MASK) +/*! @} */ /*! @@ -12764,8 +20150,13 @@ typedef struct { */ /*! @name VERID - Version ID Register */ +/*! @{ */ #define LPI2C_VERID_FEATURE_MASK (0xFFFFU) #define LPI2C_VERID_FEATURE_SHIFT (0U) +/*! FEATURE - Feature Specification Number + * 0b0000000000000010..Master only, with standard feature set + * 0b0000000000000011..Master and slave, with standard feature set + */ #define LPI2C_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_FEATURE_SHIFT)) & LPI2C_VERID_FEATURE_MASK) #define LPI2C_VERID_MINOR_MASK (0xFF0000U) #define LPI2C_VERID_MINOR_SHIFT (16U) @@ -12773,145 +20164,335 @@ typedef struct { #define LPI2C_VERID_MAJOR_MASK (0xFF000000U) #define LPI2C_VERID_MAJOR_SHIFT (24U) #define LPI2C_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_MAJOR_SHIFT)) & LPI2C_VERID_MAJOR_MASK) +/*! @} */ /*! @name PARAM - Parameter Register */ +/*! @{ */ #define LPI2C_PARAM_MTXFIFO_MASK (0xFU) #define LPI2C_PARAM_MTXFIFO_SHIFT (0U) #define LPI2C_PARAM_MTXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_PARAM_MTXFIFO_SHIFT)) & LPI2C_PARAM_MTXFIFO_MASK) #define LPI2C_PARAM_MRXFIFO_MASK (0xF00U) #define LPI2C_PARAM_MRXFIFO_SHIFT (8U) #define LPI2C_PARAM_MRXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_PARAM_MRXFIFO_SHIFT)) & LPI2C_PARAM_MRXFIFO_MASK) +/*! @} */ /*! @name MCR - Master Control Register */ +/*! @{ */ #define LPI2C_MCR_MEN_MASK (0x1U) #define LPI2C_MCR_MEN_SHIFT (0U) +/*! MEN - Master Enable + * 0b0..Master logic is disabled + * 0b1..Master logic is enabled + */ #define LPI2C_MCR_MEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_MEN_SHIFT)) & LPI2C_MCR_MEN_MASK) #define LPI2C_MCR_RST_MASK (0x2U) #define LPI2C_MCR_RST_SHIFT (1U) +/*! RST - Software Reset + * 0b0..Master logic is not reset + * 0b1..Master logic is reset + */ #define LPI2C_MCR_RST(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RST_SHIFT)) & LPI2C_MCR_RST_MASK) #define LPI2C_MCR_DOZEN_MASK (0x4U) #define LPI2C_MCR_DOZEN_SHIFT (2U) +/*! DOZEN - Doze mode enable + * 0b0..Master is enabled in Doze mode + * 0b1..Master is disabled in Doze mode + */ #define LPI2C_MCR_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_DOZEN_SHIFT)) & LPI2C_MCR_DOZEN_MASK) #define LPI2C_MCR_DBGEN_MASK (0x8U) #define LPI2C_MCR_DBGEN_SHIFT (3U) +/*! DBGEN - Debug Enable + * 0b0..Master is disabled in debug mode + * 0b1..Master is enabled in debug mode + */ #define LPI2C_MCR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_DBGEN_SHIFT)) & LPI2C_MCR_DBGEN_MASK) #define LPI2C_MCR_RTF_MASK (0x100U) #define LPI2C_MCR_RTF_SHIFT (8U) +/*! RTF - Reset Transmit FIFO + * 0b0..No effect + * 0b1..Transmit FIFO is reset + */ #define LPI2C_MCR_RTF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RTF_SHIFT)) & LPI2C_MCR_RTF_MASK) #define LPI2C_MCR_RRF_MASK (0x200U) #define LPI2C_MCR_RRF_SHIFT (9U) +/*! RRF - Reset Receive FIFO + * 0b0..No effect + * 0b1..Receive FIFO is reset + */ #define LPI2C_MCR_RRF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RRF_SHIFT)) & LPI2C_MCR_RRF_MASK) +/*! @} */ /*! @name MSR - Master Status Register */ +/*! @{ */ #define LPI2C_MSR_TDF_MASK (0x1U) #define LPI2C_MSR_TDF_SHIFT (0U) +/*! TDF - Transmit Data Flag + * 0b0..Transmit data is not requested + * 0b1..Transmit data is requested + */ #define LPI2C_MSR_TDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_TDF_SHIFT)) & LPI2C_MSR_TDF_MASK) #define LPI2C_MSR_RDF_MASK (0x2U) #define LPI2C_MSR_RDF_SHIFT (1U) +/*! RDF - Receive Data Flag + * 0b0..Receive Data is not ready + * 0b1..Receive data is ready + */ #define LPI2C_MSR_RDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_RDF_SHIFT)) & LPI2C_MSR_RDF_MASK) #define LPI2C_MSR_EPF_MASK (0x100U) #define LPI2C_MSR_EPF_SHIFT (8U) +/*! EPF - End Packet Flag + * 0b0..Master has not generated a STOP or Repeated START condition + * 0b1..Master has generated a STOP or Repeated START condition + */ #define LPI2C_MSR_EPF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_EPF_SHIFT)) & LPI2C_MSR_EPF_MASK) #define LPI2C_MSR_SDF_MASK (0x200U) #define LPI2C_MSR_SDF_SHIFT (9U) +/*! SDF - STOP Detect Flag + * 0b0..Master has not generated a STOP condition + * 0b1..Master has generated a STOP condition + */ #define LPI2C_MSR_SDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_SDF_SHIFT)) & LPI2C_MSR_SDF_MASK) #define LPI2C_MSR_NDF_MASK (0x400U) #define LPI2C_MSR_NDF_SHIFT (10U) +/*! NDF - NACK Detect Flag + * 0b0..Unexpected NACK was not detected + * 0b1..Unexpected NACK was detected + */ #define LPI2C_MSR_NDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_NDF_SHIFT)) & LPI2C_MSR_NDF_MASK) #define LPI2C_MSR_ALF_MASK (0x800U) #define LPI2C_MSR_ALF_SHIFT (11U) +/*! ALF - Arbitration Lost Flag + * 0b0..Master has not lost arbitration + * 0b1..Master has lost arbitration + */ #define LPI2C_MSR_ALF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_ALF_SHIFT)) & LPI2C_MSR_ALF_MASK) #define LPI2C_MSR_FEF_MASK (0x1000U) #define LPI2C_MSR_FEF_SHIFT (12U) +/*! FEF - FIFO Error Flag + * 0b0..No error + * 0b1..Master sending or receiving data without a START condition + */ #define LPI2C_MSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_FEF_SHIFT)) & LPI2C_MSR_FEF_MASK) #define LPI2C_MSR_PLTF_MASK (0x2000U) #define LPI2C_MSR_PLTF_SHIFT (13U) +/*! PLTF - Pin Low Timeout Flag + * 0b0..Pin low timeout has not occurred or is disabled + * 0b1..Pin low timeout has occurred + */ #define LPI2C_MSR_PLTF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_PLTF_SHIFT)) & LPI2C_MSR_PLTF_MASK) #define LPI2C_MSR_DMF_MASK (0x4000U) #define LPI2C_MSR_DMF_SHIFT (14U) +/*! DMF - Data Match Flag + * 0b0..Have not received matching data + * 0b1..Have received matching data + */ #define LPI2C_MSR_DMF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_DMF_SHIFT)) & LPI2C_MSR_DMF_MASK) #define LPI2C_MSR_MBF_MASK (0x1000000U) #define LPI2C_MSR_MBF_SHIFT (24U) +/*! MBF - Master Busy Flag + * 0b0..I2C Master is idle + * 0b1..I2C Master is busy + */ #define LPI2C_MSR_MBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_MBF_SHIFT)) & LPI2C_MSR_MBF_MASK) #define LPI2C_MSR_BBF_MASK (0x2000000U) #define LPI2C_MSR_BBF_SHIFT (25U) +/*! BBF - Bus Busy Flag + * 0b0..I2C Bus is idle + * 0b1..I2C Bus is busy + */ #define LPI2C_MSR_BBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_BBF_SHIFT)) & LPI2C_MSR_BBF_MASK) +/*! @} */ /*! @name MIER - Master Interrupt Enable Register */ +/*! @{ */ #define LPI2C_MIER_TDIE_MASK (0x1U) #define LPI2C_MIER_TDIE_SHIFT (0U) +/*! TDIE - Transmit Data Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ #define LPI2C_MIER_TDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_TDIE_SHIFT)) & LPI2C_MIER_TDIE_MASK) #define LPI2C_MIER_RDIE_MASK (0x2U) #define LPI2C_MIER_RDIE_SHIFT (1U) +/*! RDIE - Receive Data Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ #define LPI2C_MIER_RDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_RDIE_SHIFT)) & LPI2C_MIER_RDIE_MASK) #define LPI2C_MIER_EPIE_MASK (0x100U) #define LPI2C_MIER_EPIE_SHIFT (8U) +/*! EPIE - End Packet Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ #define LPI2C_MIER_EPIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_EPIE_SHIFT)) & LPI2C_MIER_EPIE_MASK) #define LPI2C_MIER_SDIE_MASK (0x200U) #define LPI2C_MIER_SDIE_SHIFT (9U) +/*! SDIE - STOP Detect Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ #define LPI2C_MIER_SDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_SDIE_SHIFT)) & LPI2C_MIER_SDIE_MASK) #define LPI2C_MIER_NDIE_MASK (0x400U) #define LPI2C_MIER_NDIE_SHIFT (10U) +/*! NDIE - NACK Detect Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ #define LPI2C_MIER_NDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_NDIE_SHIFT)) & LPI2C_MIER_NDIE_MASK) #define LPI2C_MIER_ALIE_MASK (0x800U) #define LPI2C_MIER_ALIE_SHIFT (11U) +/*! ALIE - Arbitration Lost Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ #define LPI2C_MIER_ALIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_ALIE_SHIFT)) & LPI2C_MIER_ALIE_MASK) #define LPI2C_MIER_FEIE_MASK (0x1000U) #define LPI2C_MIER_FEIE_SHIFT (12U) +/*! FEIE - FIFO Error Interrupt Enable + * 0b0..Enabled + * 0b1..Disabled + */ #define LPI2C_MIER_FEIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_FEIE_SHIFT)) & LPI2C_MIER_FEIE_MASK) #define LPI2C_MIER_PLTIE_MASK (0x2000U) #define LPI2C_MIER_PLTIE_SHIFT (13U) +/*! PLTIE - Pin Low Timeout Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ #define LPI2C_MIER_PLTIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_PLTIE_SHIFT)) & LPI2C_MIER_PLTIE_MASK) #define LPI2C_MIER_DMIE_MASK (0x4000U) #define LPI2C_MIER_DMIE_SHIFT (14U) +/*! DMIE - Data Match Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ #define LPI2C_MIER_DMIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_DMIE_SHIFT)) & LPI2C_MIER_DMIE_MASK) +/*! @} */ /*! @name MDER - Master DMA Enable Register */ +/*! @{ */ #define LPI2C_MDER_TDDE_MASK (0x1U) #define LPI2C_MDER_TDDE_SHIFT (0U) +/*! TDDE - Transmit Data DMA Enable + * 0b0..DMA request is disabled + * 0b1..DMA request is enabled + */ #define LPI2C_MDER_TDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDER_TDDE_SHIFT)) & LPI2C_MDER_TDDE_MASK) #define LPI2C_MDER_RDDE_MASK (0x2U) #define LPI2C_MDER_RDDE_SHIFT (1U) +/*! RDDE - Receive Data DMA Enable + * 0b0..DMA request is disabled + * 0b1..DMA request is enabled + */ #define LPI2C_MDER_RDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDER_RDDE_SHIFT)) & LPI2C_MDER_RDDE_MASK) +/*! @} */ /*! @name MCFGR0 - Master Configuration Register 0 */ +/*! @{ */ #define LPI2C_MCFGR0_HREN_MASK (0x1U) #define LPI2C_MCFGR0_HREN_SHIFT (0U) +/*! HREN - Host Request Enable + * 0b0..Host request input is disabled + * 0b1..Host request input is enabled + */ #define LPI2C_MCFGR0_HREN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HREN_SHIFT)) & LPI2C_MCFGR0_HREN_MASK) #define LPI2C_MCFGR0_HRPOL_MASK (0x2U) #define LPI2C_MCFGR0_HRPOL_SHIFT (1U) +/*! HRPOL - Host Request Polarity + * 0b0..Active low + * 0b1..Active high + */ #define LPI2C_MCFGR0_HRPOL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HRPOL_SHIFT)) & LPI2C_MCFGR0_HRPOL_MASK) #define LPI2C_MCFGR0_HRSEL_MASK (0x4U) #define LPI2C_MCFGR0_HRSEL_SHIFT (2U) +/*! HRSEL - Host Request Select + * 0b0..Host request input is pin HREQ + * 0b1..Host request input is input trigger + */ #define LPI2C_MCFGR0_HRSEL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HRSEL_SHIFT)) & LPI2C_MCFGR0_HRSEL_MASK) #define LPI2C_MCFGR0_CIRFIFO_MASK (0x100U) #define LPI2C_MCFGR0_CIRFIFO_SHIFT (8U) +/*! CIRFIFO - Circular FIFO Enable + * 0b0..Circular FIFO is disabled + * 0b1..Circular FIFO is enabled + */ #define LPI2C_MCFGR0_CIRFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_CIRFIFO_SHIFT)) & LPI2C_MCFGR0_CIRFIFO_MASK) #define LPI2C_MCFGR0_RDMO_MASK (0x200U) #define LPI2C_MCFGR0_RDMO_SHIFT (9U) +/*! RDMO - Receive Data Match Only + * 0b0..Received data is stored in the receive FIFO + * 0b1..Received data is discarded unless the the Data Match Flag (MSR[DMF]) is set + */ #define LPI2C_MCFGR0_RDMO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_RDMO_SHIFT)) & LPI2C_MCFGR0_RDMO_MASK) +/*! @} */ /*! @name MCFGR1 - Master Configuration Register 1 */ +/*! @{ */ #define LPI2C_MCFGR1_PRESCALE_MASK (0x7U) #define LPI2C_MCFGR1_PRESCALE_SHIFT (0U) +/*! PRESCALE - Prescaler + * 0b000..Divide by 1 + * 0b001..Divide by 2 + * 0b010..Divide by 4 + * 0b011..Divide by 8 + * 0b100..Divide by 16 + * 0b101..Divide by 32 + * 0b110..Divide by 64 + * 0b111..Divide by 128 + */ #define LPI2C_MCFGR1_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_PRESCALE_SHIFT)) & LPI2C_MCFGR1_PRESCALE_MASK) #define LPI2C_MCFGR1_AUTOSTOP_MASK (0x100U) #define LPI2C_MCFGR1_AUTOSTOP_SHIFT (8U) +/*! AUTOSTOP - Automatic STOP Generation + * 0b0..No effect + * 0b1..STOP condition is automatically generated whenever the transmit FIFO is empty and the LPI2C master is busy + */ #define LPI2C_MCFGR1_AUTOSTOP(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_AUTOSTOP_SHIFT)) & LPI2C_MCFGR1_AUTOSTOP_MASK) #define LPI2C_MCFGR1_IGNACK_MASK (0x200U) #define LPI2C_MCFGR1_IGNACK_SHIFT (9U) +/*! IGNACK - IGNACK + * 0b0..LPI2C Master will receive ACK and NACK normally + * 0b1..LPI2C Master will treat a received NACK as if it (NACK) was an ACK + */ #define LPI2C_MCFGR1_IGNACK(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_IGNACK_SHIFT)) & LPI2C_MCFGR1_IGNACK_MASK) #define LPI2C_MCFGR1_TIMECFG_MASK (0x400U) #define LPI2C_MCFGR1_TIMECFG_SHIFT (10U) +/*! TIMECFG - Timeout Configuration + * 0b0..Pin Low Timeout Flag will set if SCL is low for longer than the configured timeout + * 0b1..Pin Low Timeout Flag will set if either SCL or SDA is low for longer than the configured timeout + */ #define LPI2C_MCFGR1_TIMECFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_TIMECFG_SHIFT)) & LPI2C_MCFGR1_TIMECFG_MASK) #define LPI2C_MCFGR1_MATCFG_MASK (0x70000U) #define LPI2C_MCFGR1_MATCFG_SHIFT (16U) +/*! MATCFG - Match Configuration + * 0b000..Match is disabled + * 0b001..Reserved + * 0b010..Match is enabled (1st data word equals MATCH0 OR MATCH1) + * 0b011..Match is enabled (any data word equals MATCH0 OR MATCH1) + * 0b100..Match is enabled (1st data word equals MATCH0 AND 2nd data word equals MATCH1) + * 0b101..Match is enabled (any data word equals MATCH0 AND next data word equals MATCH1) + * 0b110..Match is enabled (1st data word AND MATCH1 equals MATCH0 AND MATCH1) + * 0b111..Match is enabled (any data word AND MATCH1 equals MATCH0 AND MATCH1) + */ #define LPI2C_MCFGR1_MATCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_MATCFG_SHIFT)) & LPI2C_MCFGR1_MATCFG_MASK) #define LPI2C_MCFGR1_PINCFG_MASK (0x7000000U) #define LPI2C_MCFGR1_PINCFG_SHIFT (24U) +/*! PINCFG - Pin Configuration + * 0b000..2-pin open drain mode + * 0b001..2-pin output only mode (ultra-fast mode) + * 0b010..2-pin push-pull mode + * 0b011..4-pin push-pull mode + * 0b100..2-pin open drain mode with separate LPI2C slave + * 0b101..2-pin output only mode (ultra-fast mode) with separate LPI2C slave + * 0b110..2-pin push-pull mode with separate LPI2C slave + * 0b111..4-pin push-pull mode (inverted outputs) + */ #define LPI2C_MCFGR1_PINCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_PINCFG_SHIFT)) & LPI2C_MCFGR1_PINCFG_MASK) +/*! @} */ /*! @name MCFGR2 - Master Configuration Register 2 */ +/*! @{ */ #define LPI2C_MCFGR2_BUSIDLE_MASK (0xFFFU) #define LPI2C_MCFGR2_BUSIDLE_SHIFT (0U) #define LPI2C_MCFGR2_BUSIDLE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_BUSIDLE_SHIFT)) & LPI2C_MCFGR2_BUSIDLE_MASK) @@ -12921,21 +20502,27 @@ typedef struct { #define LPI2C_MCFGR2_FILTSDA_MASK (0xF000000U) #define LPI2C_MCFGR2_FILTSDA_SHIFT (24U) #define LPI2C_MCFGR2_FILTSDA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_FILTSDA_SHIFT)) & LPI2C_MCFGR2_FILTSDA_MASK) +/*! @} */ /*! @name MCFGR3 - Master Configuration Register 3 */ +/*! @{ */ #define LPI2C_MCFGR3_PINLOW_MASK (0xFFF00U) #define LPI2C_MCFGR3_PINLOW_SHIFT (8U) #define LPI2C_MCFGR3_PINLOW(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR3_PINLOW_SHIFT)) & LPI2C_MCFGR3_PINLOW_MASK) +/*! @} */ /*! @name MDMR - Master Data Match Register */ +/*! @{ */ #define LPI2C_MDMR_MATCH0_MASK (0xFFU) #define LPI2C_MDMR_MATCH0_SHIFT (0U) #define LPI2C_MDMR_MATCH0(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDMR_MATCH0_SHIFT)) & LPI2C_MDMR_MATCH0_MASK) #define LPI2C_MDMR_MATCH1_MASK (0xFF0000U) #define LPI2C_MDMR_MATCH1_SHIFT (16U) #define LPI2C_MDMR_MATCH1(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDMR_MATCH1_SHIFT)) & LPI2C_MDMR_MATCH1_MASK) +/*! @} */ /*! @name MCCR0 - Master Clock Configuration Register 0 */ +/*! @{ */ #define LPI2C_MCCR0_CLKLO_MASK (0x3FU) #define LPI2C_MCCR0_CLKLO_SHIFT (0U) #define LPI2C_MCCR0_CLKLO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_CLKLO_SHIFT)) & LPI2C_MCCR0_CLKLO_MASK) @@ -12948,8 +20535,10 @@ typedef struct { #define LPI2C_MCCR0_DATAVD_MASK (0x3F000000U) #define LPI2C_MCCR0_DATAVD_SHIFT (24U) #define LPI2C_MCCR0_DATAVD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_DATAVD_SHIFT)) & LPI2C_MCCR0_DATAVD_MASK) +/*! @} */ /*! @name MCCR1 - Master Clock Configuration Register 1 */ +/*! @{ */ #define LPI2C_MCCR1_CLKLO_MASK (0x3FU) #define LPI2C_MCCR1_CLKLO_SHIFT (0U) #define LPI2C_MCCR1_CLKLO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_CLKLO_SHIFT)) & LPI2C_MCCR1_CLKLO_MASK) @@ -12962,188 +20551,412 @@ typedef struct { #define LPI2C_MCCR1_DATAVD_MASK (0x3F000000U) #define LPI2C_MCCR1_DATAVD_SHIFT (24U) #define LPI2C_MCCR1_DATAVD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_DATAVD_SHIFT)) & LPI2C_MCCR1_DATAVD_MASK) +/*! @} */ /*! @name MFCR - Master FIFO Control Register */ +/*! @{ */ #define LPI2C_MFCR_TXWATER_MASK (0x3U) #define LPI2C_MFCR_TXWATER_SHIFT (0U) #define LPI2C_MFCR_TXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFCR_TXWATER_SHIFT)) & LPI2C_MFCR_TXWATER_MASK) #define LPI2C_MFCR_RXWATER_MASK (0x30000U) #define LPI2C_MFCR_RXWATER_SHIFT (16U) #define LPI2C_MFCR_RXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFCR_RXWATER_SHIFT)) & LPI2C_MFCR_RXWATER_MASK) +/*! @} */ /*! @name MFSR - Master FIFO Status Register */ +/*! @{ */ #define LPI2C_MFSR_TXCOUNT_MASK (0x7U) #define LPI2C_MFSR_TXCOUNT_SHIFT (0U) #define LPI2C_MFSR_TXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFSR_TXCOUNT_SHIFT)) & LPI2C_MFSR_TXCOUNT_MASK) #define LPI2C_MFSR_RXCOUNT_MASK (0x70000U) #define LPI2C_MFSR_RXCOUNT_SHIFT (16U) #define LPI2C_MFSR_RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFSR_RXCOUNT_SHIFT)) & LPI2C_MFSR_RXCOUNT_MASK) +/*! @} */ /*! @name MTDR - Master Transmit Data Register */ +/*! @{ */ #define LPI2C_MTDR_DATA_MASK (0xFFU) #define LPI2C_MTDR_DATA_SHIFT (0U) #define LPI2C_MTDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MTDR_DATA_SHIFT)) & LPI2C_MTDR_DATA_MASK) #define LPI2C_MTDR_CMD_MASK (0x700U) #define LPI2C_MTDR_CMD_SHIFT (8U) +/*! CMD - Command Data + * 0b000..Transmit DATA[7:0] + * 0b001..Receive (DATA[7:0] + 1) bytes + * 0b010..Generate STOP condition + * 0b011..Receive and discard (DATA[7:0] + 1) bytes + * 0b100..Generate (repeated) START and transmit address in DATA[7:0] + * 0b101..Generate (repeated) START and transmit address in DATA[7:0]. This transfer expects a NACK to be returned. + * 0b110..Generate (repeated) START and transmit address in DATA[7:0] using high speed mode + * 0b111..Generate (repeated) START and transmit address in DATA[7:0] using high speed mode. This transfer expects a NACK to be returned. + */ #define LPI2C_MTDR_CMD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MTDR_CMD_SHIFT)) & LPI2C_MTDR_CMD_MASK) +/*! @} */ /*! @name MRDR - Master Receive Data Register */ +/*! @{ */ #define LPI2C_MRDR_DATA_MASK (0xFFU) #define LPI2C_MRDR_DATA_SHIFT (0U) #define LPI2C_MRDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MRDR_DATA_SHIFT)) & LPI2C_MRDR_DATA_MASK) #define LPI2C_MRDR_RXEMPTY_MASK (0x4000U) #define LPI2C_MRDR_RXEMPTY_SHIFT (14U) +/*! RXEMPTY - RX Empty + * 0b0..Receive FIFO is not empty + * 0b1..Receive FIFO is empty + */ #define LPI2C_MRDR_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MRDR_RXEMPTY_SHIFT)) & LPI2C_MRDR_RXEMPTY_MASK) +/*! @} */ /*! @name SCR - Slave Control Register */ +/*! @{ */ #define LPI2C_SCR_SEN_MASK (0x1U) #define LPI2C_SCR_SEN_SHIFT (0U) +/*! SEN - Slave Enable + * 0b0..I2C Slave mode is disabled + * 0b1..I2C Slave mode is enabled + */ #define LPI2C_SCR_SEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_SEN_SHIFT)) & LPI2C_SCR_SEN_MASK) #define LPI2C_SCR_RST_MASK (0x2U) #define LPI2C_SCR_RST_SHIFT (1U) +/*! RST - Software Reset + * 0b0..Slave mode logic is not reset + * 0b1..Slave mode logic is reset + */ #define LPI2C_SCR_RST(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RST_SHIFT)) & LPI2C_SCR_RST_MASK) #define LPI2C_SCR_FILTEN_MASK (0x10U) #define LPI2C_SCR_FILTEN_SHIFT (4U) +/*! FILTEN - Filter Enable + * 0b0..Disable digital filter and output delay counter for slave mode + * 0b1..Enable digital filter and output delay counter for slave mode + */ #define LPI2C_SCR_FILTEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_FILTEN_SHIFT)) & LPI2C_SCR_FILTEN_MASK) #define LPI2C_SCR_FILTDZ_MASK (0x20U) #define LPI2C_SCR_FILTDZ_SHIFT (5U) +/*! FILTDZ - Filter Doze Enable + * 0b0..Filter remains enabled in Doze mode + * 0b1..Filter is disabled in Doze mode + */ #define LPI2C_SCR_FILTDZ(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_FILTDZ_SHIFT)) & LPI2C_SCR_FILTDZ_MASK) #define LPI2C_SCR_RTF_MASK (0x100U) #define LPI2C_SCR_RTF_SHIFT (8U) +/*! RTF - Reset Transmit FIFO + * 0b0..No effect + * 0b1..Transmit Data Register is now empty + */ #define LPI2C_SCR_RTF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RTF_SHIFT)) & LPI2C_SCR_RTF_MASK) #define LPI2C_SCR_RRF_MASK (0x200U) #define LPI2C_SCR_RRF_SHIFT (9U) +/*! RRF - Reset Receive FIFO + * 0b0..No effect + * 0b1..Receive Data Register is now empty + */ #define LPI2C_SCR_RRF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RRF_SHIFT)) & LPI2C_SCR_RRF_MASK) +/*! @} */ /*! @name SSR - Slave Status Register */ +/*! @{ */ #define LPI2C_SSR_TDF_MASK (0x1U) #define LPI2C_SSR_TDF_SHIFT (0U) +/*! TDF - Transmit Data Flag + * 0b0..Transmit data not requested + * 0b1..Transmit data is requested + */ #define LPI2C_SSR_TDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_TDF_SHIFT)) & LPI2C_SSR_TDF_MASK) #define LPI2C_SSR_RDF_MASK (0x2U) #define LPI2C_SSR_RDF_SHIFT (1U) +/*! RDF - Receive Data Flag + * 0b0..Receive data is not ready + * 0b1..Receive data is ready + */ #define LPI2C_SSR_RDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_RDF_SHIFT)) & LPI2C_SSR_RDF_MASK) #define LPI2C_SSR_AVF_MASK (0x4U) #define LPI2C_SSR_AVF_SHIFT (2U) +/*! AVF - Address Valid Flag + * 0b0..Address Status Register is not valid + * 0b1..Address Status Register is valid + */ #define LPI2C_SSR_AVF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AVF_SHIFT)) & LPI2C_SSR_AVF_MASK) #define LPI2C_SSR_TAF_MASK (0x8U) #define LPI2C_SSR_TAF_SHIFT (3U) +/*! TAF - Transmit ACK Flag + * 0b0..Transmit ACK/NACK is not required + * 0b1..Transmit ACK/NACK is required + */ #define LPI2C_SSR_TAF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_TAF_SHIFT)) & LPI2C_SSR_TAF_MASK) #define LPI2C_SSR_RSF_MASK (0x100U) #define LPI2C_SSR_RSF_SHIFT (8U) +/*! RSF - Repeated Start Flag + * 0b0..Slave has not detected a Repeated START condition + * 0b1..Slave has detected a Repeated START condition + */ #define LPI2C_SSR_RSF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_RSF_SHIFT)) & LPI2C_SSR_RSF_MASK) #define LPI2C_SSR_SDF_MASK (0x200U) #define LPI2C_SSR_SDF_SHIFT (9U) +/*! SDF - STOP Detect Flag + * 0b0..Slave has not detected a STOP condition + * 0b1..Slave has detected a STOP condition + */ #define LPI2C_SSR_SDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SDF_SHIFT)) & LPI2C_SSR_SDF_MASK) #define LPI2C_SSR_BEF_MASK (0x400U) #define LPI2C_SSR_BEF_SHIFT (10U) +/*! BEF - Bit Error Flag + * 0b0..Slave has not detected a bit error + * 0b1..Slave has detected a bit error + */ #define LPI2C_SSR_BEF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_BEF_SHIFT)) & LPI2C_SSR_BEF_MASK) #define LPI2C_SSR_FEF_MASK (0x800U) #define LPI2C_SSR_FEF_SHIFT (11U) +/*! FEF - FIFO Error Flag + * 0b0..FIFO underflow or overflow was not detected + * 0b1..FIFO underflow or overflow was detected + */ #define LPI2C_SSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_FEF_SHIFT)) & LPI2C_SSR_FEF_MASK) #define LPI2C_SSR_AM0F_MASK (0x1000U) #define LPI2C_SSR_AM0F_SHIFT (12U) +/*! AM0F - Address Match 0 Flag + * 0b0..Have not received an ADDR0 matching address + * 0b1..Have received an ADDR0 matching address + */ #define LPI2C_SSR_AM0F(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AM0F_SHIFT)) & LPI2C_SSR_AM0F_MASK) #define LPI2C_SSR_AM1F_MASK (0x2000U) #define LPI2C_SSR_AM1F_SHIFT (13U) +/*! AM1F - Address Match 1 Flag + * 0b0..Have not received an ADDR1 or ADDR0/ADDR1 range matching address + * 0b1..Have received an ADDR1 or ADDR0/ADDR1 range matching address + */ #define LPI2C_SSR_AM1F(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AM1F_SHIFT)) & LPI2C_SSR_AM1F_MASK) #define LPI2C_SSR_GCF_MASK (0x4000U) #define LPI2C_SSR_GCF_SHIFT (14U) +/*! GCF - General Call Flag + * 0b0..Slave has not detected the General Call Address or the General Call Address is disabled + * 0b1..Slave has detected the General Call Address + */ #define LPI2C_SSR_GCF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_GCF_SHIFT)) & LPI2C_SSR_GCF_MASK) #define LPI2C_SSR_SARF_MASK (0x8000U) #define LPI2C_SSR_SARF_SHIFT (15U) +/*! SARF - SMBus Alert Response Flag + * 0b0..SMBus Alert Response is disabled or not detected + * 0b1..SMBus Alert Response is enabled and detected + */ #define LPI2C_SSR_SARF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SARF_SHIFT)) & LPI2C_SSR_SARF_MASK) #define LPI2C_SSR_SBF_MASK (0x1000000U) #define LPI2C_SSR_SBF_SHIFT (24U) +/*! SBF - Slave Busy Flag + * 0b0..I2C Slave is idle + * 0b1..I2C Slave is busy + */ #define LPI2C_SSR_SBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SBF_SHIFT)) & LPI2C_SSR_SBF_MASK) #define LPI2C_SSR_BBF_MASK (0x2000000U) #define LPI2C_SSR_BBF_SHIFT (25U) +/*! BBF - Bus Busy Flag + * 0b0..I2C Bus is idle + * 0b1..I2C Bus is busy + */ #define LPI2C_SSR_BBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_BBF_SHIFT)) & LPI2C_SSR_BBF_MASK) +/*! @} */ /*! @name SIER - Slave Interrupt Enable Register */ +/*! @{ */ #define LPI2C_SIER_TDIE_MASK (0x1U) #define LPI2C_SIER_TDIE_SHIFT (0U) +/*! TDIE - Transmit Data Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ #define LPI2C_SIER_TDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_TDIE_SHIFT)) & LPI2C_SIER_TDIE_MASK) #define LPI2C_SIER_RDIE_MASK (0x2U) #define LPI2C_SIER_RDIE_SHIFT (1U) +/*! RDIE - Receive Data Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ #define LPI2C_SIER_RDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_RDIE_SHIFT)) & LPI2C_SIER_RDIE_MASK) #define LPI2C_SIER_AVIE_MASK (0x4U) #define LPI2C_SIER_AVIE_SHIFT (2U) +/*! AVIE - Address Valid Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ #define LPI2C_SIER_AVIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AVIE_SHIFT)) & LPI2C_SIER_AVIE_MASK) #define LPI2C_SIER_TAIE_MASK (0x8U) #define LPI2C_SIER_TAIE_SHIFT (3U) +/*! TAIE - Transmit ACK Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ #define LPI2C_SIER_TAIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_TAIE_SHIFT)) & LPI2C_SIER_TAIE_MASK) #define LPI2C_SIER_RSIE_MASK (0x100U) #define LPI2C_SIER_RSIE_SHIFT (8U) +/*! RSIE - Repeated Start Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ #define LPI2C_SIER_RSIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_RSIE_SHIFT)) & LPI2C_SIER_RSIE_MASK) #define LPI2C_SIER_SDIE_MASK (0x200U) #define LPI2C_SIER_SDIE_SHIFT (9U) +/*! SDIE - STOP Detect Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ #define LPI2C_SIER_SDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_SDIE_SHIFT)) & LPI2C_SIER_SDIE_MASK) #define LPI2C_SIER_BEIE_MASK (0x400U) #define LPI2C_SIER_BEIE_SHIFT (10U) +/*! BEIE - Bit Error Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ #define LPI2C_SIER_BEIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_BEIE_SHIFT)) & LPI2C_SIER_BEIE_MASK) #define LPI2C_SIER_FEIE_MASK (0x800U) #define LPI2C_SIER_FEIE_SHIFT (11U) +/*! FEIE - FIFO Error Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ #define LPI2C_SIER_FEIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_FEIE_SHIFT)) & LPI2C_SIER_FEIE_MASK) #define LPI2C_SIER_AM0IE_MASK (0x1000U) #define LPI2C_SIER_AM0IE_SHIFT (12U) +/*! AM0IE - Address Match 0 Interrupt Enable + * 0b0..Enabled + * 0b1..Disabled + */ #define LPI2C_SIER_AM0IE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AM0IE_SHIFT)) & LPI2C_SIER_AM0IE_MASK) #define LPI2C_SIER_AM1F_MASK (0x2000U) #define LPI2C_SIER_AM1F_SHIFT (13U) +/*! AM1F - Address Match 1 Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ #define LPI2C_SIER_AM1F(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AM1F_SHIFT)) & LPI2C_SIER_AM1F_MASK) #define LPI2C_SIER_GCIE_MASK (0x4000U) #define LPI2C_SIER_GCIE_SHIFT (14U) +/*! GCIE - General Call Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ #define LPI2C_SIER_GCIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_GCIE_SHIFT)) & LPI2C_SIER_GCIE_MASK) #define LPI2C_SIER_SARIE_MASK (0x8000U) #define LPI2C_SIER_SARIE_SHIFT (15U) +/*! SARIE - SMBus Alert Response Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ #define LPI2C_SIER_SARIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_SARIE_SHIFT)) & LPI2C_SIER_SARIE_MASK) +/*! @} */ /*! @name SDER - Slave DMA Enable Register */ +/*! @{ */ #define LPI2C_SDER_TDDE_MASK (0x1U) #define LPI2C_SDER_TDDE_SHIFT (0U) +/*! TDDE - Transmit Data DMA Enable + * 0b0..DMA request is disabled + * 0b1..DMA request is enabled + */ #define LPI2C_SDER_TDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_TDDE_SHIFT)) & LPI2C_SDER_TDDE_MASK) #define LPI2C_SDER_RDDE_MASK (0x2U) #define LPI2C_SDER_RDDE_SHIFT (1U) +/*! RDDE - Receive Data DMA Enable + * 0b0..DMA request is disabled + * 0b1..DMA request is enabled + */ #define LPI2C_SDER_RDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_RDDE_SHIFT)) & LPI2C_SDER_RDDE_MASK) #define LPI2C_SDER_AVDE_MASK (0x4U) #define LPI2C_SDER_AVDE_SHIFT (2U) +/*! AVDE - Address Valid DMA Enable + * 0b0..DMA request is disabled + * 0b1..DMA request is enabled + */ #define LPI2C_SDER_AVDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_AVDE_SHIFT)) & LPI2C_SDER_AVDE_MASK) +/*! @} */ /*! @name SCFGR1 - Slave Configuration Register 1 */ +/*! @{ */ #define LPI2C_SCFGR1_ADRSTALL_MASK (0x1U) #define LPI2C_SCFGR1_ADRSTALL_SHIFT (0U) +/*! ADRSTALL - Address SCL Stall + * 0b0..Clock stretching is disabled + * 0b1..Clock stretching is enabled + */ #define LPI2C_SCFGR1_ADRSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ADRSTALL_SHIFT)) & LPI2C_SCFGR1_ADRSTALL_MASK) #define LPI2C_SCFGR1_RXSTALL_MASK (0x2U) #define LPI2C_SCFGR1_RXSTALL_SHIFT (1U) +/*! RXSTALL - RX SCL Stall + * 0b0..Clock stretching is disabled + * 0b1..Clock stretching is enabled + */ #define LPI2C_SCFGR1_RXSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_RXSTALL_SHIFT)) & LPI2C_SCFGR1_RXSTALL_MASK) #define LPI2C_SCFGR1_TXDSTALL_MASK (0x4U) #define LPI2C_SCFGR1_TXDSTALL_SHIFT (2U) +/*! TXDSTALL - TX Data SCL Stall + * 0b0..Clock stretching is disabled + * 0b1..Clock stretching is enabled + */ #define LPI2C_SCFGR1_TXDSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_TXDSTALL_SHIFT)) & LPI2C_SCFGR1_TXDSTALL_MASK) #define LPI2C_SCFGR1_ACKSTALL_MASK (0x8U) #define LPI2C_SCFGR1_ACKSTALL_SHIFT (3U) +/*! ACKSTALL - ACK SCL Stall + * 0b0..Clock stretching is disabled + * 0b1..Clock stretching is enabled + */ #define LPI2C_SCFGR1_ACKSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ACKSTALL_SHIFT)) & LPI2C_SCFGR1_ACKSTALL_MASK) #define LPI2C_SCFGR1_GCEN_MASK (0x100U) #define LPI2C_SCFGR1_GCEN_SHIFT (8U) +/*! GCEN - General Call Enable + * 0b0..General Call address is disabled + * 0b1..General Call address is enabled + */ #define LPI2C_SCFGR1_GCEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_GCEN_SHIFT)) & LPI2C_SCFGR1_GCEN_MASK) #define LPI2C_SCFGR1_SAEN_MASK (0x200U) #define LPI2C_SCFGR1_SAEN_SHIFT (9U) +/*! SAEN - SMBus Alert Enable + * 0b0..Disables match on SMBus Alert + * 0b1..Enables match on SMBus Alert + */ #define LPI2C_SCFGR1_SAEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_SAEN_SHIFT)) & LPI2C_SCFGR1_SAEN_MASK) #define LPI2C_SCFGR1_TXCFG_MASK (0x400U) #define LPI2C_SCFGR1_TXCFG_SHIFT (10U) +/*! TXCFG - Transmit Flag Configuration + * 0b0..Transmit Data Flag will only assert during a slave-transmit transfer when the Transmit Data register is empty + * 0b1..Transmit Data Flag will assert whenever the Transmit Data register is empty + */ #define LPI2C_SCFGR1_TXCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_TXCFG_SHIFT)) & LPI2C_SCFGR1_TXCFG_MASK) #define LPI2C_SCFGR1_RXCFG_MASK (0x800U) #define LPI2C_SCFGR1_RXCFG_SHIFT (11U) +/*! RXCFG - Receive Data Configuration + * 0b0..Reading the Receive Data register will return received data and clear the Receive Data flag (MSR[RDF]). + * 0b1..Reading the Receive Data register when the Address Valid flag (SSR[AVF])is set, will return the Address Status register and clear the Address Valid flag. Reading the Receive Data register when the Address Valid flag is clear, will return received data and clear the Receive Data flag (MSR[RDF]). + */ #define LPI2C_SCFGR1_RXCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_RXCFG_SHIFT)) & LPI2C_SCFGR1_RXCFG_MASK) #define LPI2C_SCFGR1_IGNACK_MASK (0x1000U) #define LPI2C_SCFGR1_IGNACK_SHIFT (12U) +/*! IGNACK - Ignore NACK + * 0b0..Slave will end transfer when NACK is detected + * 0b1..Slave will not end transfer when NACK detected + */ #define LPI2C_SCFGR1_IGNACK(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_IGNACK_SHIFT)) & LPI2C_SCFGR1_IGNACK_MASK) #define LPI2C_SCFGR1_HSMEN_MASK (0x2000U) #define LPI2C_SCFGR1_HSMEN_SHIFT (13U) +/*! HSMEN - High Speed Mode Enable + * 0b0..Disables detection of HS-mode master code + * 0b1..Enables detection of HS-mode master code + */ #define LPI2C_SCFGR1_HSMEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_HSMEN_SHIFT)) & LPI2C_SCFGR1_HSMEN_MASK) #define LPI2C_SCFGR1_ADDRCFG_MASK (0x70000U) #define LPI2C_SCFGR1_ADDRCFG_SHIFT (16U) +/*! ADDRCFG - Address Configuration + * 0b000..Address match 0 (7-bit) + * 0b001..Address match 0 (10-bit) + * 0b010..Address match 0 (7-bit) or Address match 1 (7-bit) + * 0b011..Address match 0 (10-bit) or Address match 1 (10-bit) + * 0b100..Address match 0 (7-bit) or Address match 1 (10-bit) + * 0b101..Address match 0 (10-bit) or Address match 1 (7-bit) + * 0b110..From Address match 0 (7-bit) to Address match 1 (7-bit) + * 0b111..From Address match 0 (10-bit) to Address match 1 (10-bit) + */ #define LPI2C_SCFGR1_ADDRCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ADDRCFG_SHIFT)) & LPI2C_SCFGR1_ADDRCFG_MASK) +/*! @} */ /*! @name SCFGR2 - Slave Configuration Register 2 */ +/*! @{ */ #define LPI2C_SCFGR2_CLKHOLD_MASK (0xFU) #define LPI2C_SCFGR2_CLKHOLD_SHIFT (0U) #define LPI2C_SCFGR2_CLKHOLD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_CLKHOLD_SHIFT)) & LPI2C_SCFGR2_CLKHOLD_MASK) @@ -13156,43 +20969,70 @@ typedef struct { #define LPI2C_SCFGR2_FILTSDA_MASK (0xF000000U) #define LPI2C_SCFGR2_FILTSDA_SHIFT (24U) #define LPI2C_SCFGR2_FILTSDA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_FILTSDA_SHIFT)) & LPI2C_SCFGR2_FILTSDA_MASK) +/*! @} */ /*! @name SAMR - Slave Address Match Register */ +/*! @{ */ #define LPI2C_SAMR_ADDR0_MASK (0x7FEU) #define LPI2C_SAMR_ADDR0_SHIFT (1U) #define LPI2C_SAMR_ADDR0(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SAMR_ADDR0_SHIFT)) & LPI2C_SAMR_ADDR0_MASK) #define LPI2C_SAMR_ADDR1_MASK (0x7FE0000U) #define LPI2C_SAMR_ADDR1_SHIFT (17U) #define LPI2C_SAMR_ADDR1(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SAMR_ADDR1_SHIFT)) & LPI2C_SAMR_ADDR1_MASK) +/*! @} */ /*! @name SASR - Slave Address Status Register */ +/*! @{ */ #define LPI2C_SASR_RADDR_MASK (0x7FFU) #define LPI2C_SASR_RADDR_SHIFT (0U) #define LPI2C_SASR_RADDR(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SASR_RADDR_SHIFT)) & LPI2C_SASR_RADDR_MASK) #define LPI2C_SASR_ANV_MASK (0x4000U) #define LPI2C_SASR_ANV_SHIFT (14U) +/*! ANV - Address Not Valid + * 0b0..Received Address (RADDR) is valid + * 0b1..Received Address (RADDR) is not valid + */ #define LPI2C_SASR_ANV(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SASR_ANV_SHIFT)) & LPI2C_SASR_ANV_MASK) +/*! @} */ /*! @name STAR - Slave Transmit ACK Register */ +/*! @{ */ #define LPI2C_STAR_TXNACK_MASK (0x1U) #define LPI2C_STAR_TXNACK_SHIFT (0U) +/*! TXNACK - Transmit NACK + * 0b0..Write a Transmit ACK for each received word + * 0b1..Write a Transmit NACK for each received word + */ #define LPI2C_STAR_TXNACK(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_STAR_TXNACK_SHIFT)) & LPI2C_STAR_TXNACK_MASK) +/*! @} */ /*! @name STDR - Slave Transmit Data Register */ +/*! @{ */ #define LPI2C_STDR_DATA_MASK (0xFFU) #define LPI2C_STDR_DATA_SHIFT (0U) #define LPI2C_STDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_STDR_DATA_SHIFT)) & LPI2C_STDR_DATA_MASK) +/*! @} */ /*! @name SRDR - Slave Receive Data Register */ +/*! @{ */ #define LPI2C_SRDR_DATA_MASK (0xFFU) #define LPI2C_SRDR_DATA_SHIFT (0U) #define LPI2C_SRDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_DATA_SHIFT)) & LPI2C_SRDR_DATA_MASK) #define LPI2C_SRDR_RXEMPTY_MASK (0x4000U) #define LPI2C_SRDR_RXEMPTY_SHIFT (14U) +/*! RXEMPTY - RX Empty + * 0b0..The Receive Data Register is not empty + * 0b1..The Receive Data Register is empty + */ #define LPI2C_SRDR_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_RXEMPTY_SHIFT)) & LPI2C_SRDR_RXEMPTY_MASK) #define LPI2C_SRDR_SOF_MASK (0x8000U) #define LPI2C_SRDR_SOF_SHIFT (15U) +/*! SOF - Start Of Frame + * 0b0..Indicates this is not the first data word since a (repeated) START or STOP condition + * 0b1..Indicates this is the first data word since a (repeated) START or STOP condition + */ #define LPI2C_SRDR_SOF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_SOF_SHIFT)) & LPI2C_SRDR_SOF_MASK) +/*! @} */ /*! @@ -13274,8 +21114,12 @@ typedef struct { */ /*! @name VERID - Version ID Register */ +/*! @{ */ #define LPSPI_VERID_FEATURE_MASK (0xFFFFU) #define LPSPI_VERID_FEATURE_SHIFT (0U) +/*! FEATURE - Module Identification Number + * 0b0000000000000100..Standard feature set supporting a 32-bit shift register. + */ #define LPSPI_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_VERID_FEATURE_SHIFT)) & LPSPI_VERID_FEATURE_MASK) #define LPSPI_VERID_MINOR_MASK (0xFF0000U) #define LPSPI_VERID_MINOR_SHIFT (16U) @@ -13283,8 +21127,10 @@ typedef struct { #define LPSPI_VERID_MAJOR_MASK (0xFF000000U) #define LPSPI_VERID_MAJOR_SHIFT (24U) #define LPSPI_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_VERID_MAJOR_SHIFT)) & LPSPI_VERID_MAJOR_MASK) +/*! @} */ /*! @name PARAM - Parameter Register */ +/*! @{ */ #define LPSPI_PARAM_TXFIFO_MASK (0xFFU) #define LPSPI_PARAM_TXFIFO_SHIFT (0U) #define LPSPI_PARAM_TXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_PARAM_TXFIFO_SHIFT)) & LPSPI_PARAM_TXFIFO_MASK) @@ -13294,147 +21140,329 @@ typedef struct { #define LPSPI_PARAM_PCSNUM_MASK (0xFF0000U) #define LPSPI_PARAM_PCSNUM_SHIFT (16U) #define LPSPI_PARAM_PCSNUM(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_PARAM_PCSNUM_SHIFT)) & LPSPI_PARAM_PCSNUM_MASK) +/*! @} */ /*! @name CR - Control Register */ +/*! @{ */ #define LPSPI_CR_MEN_MASK (0x1U) #define LPSPI_CR_MEN_SHIFT (0U) +/*! MEN - Module Enable + * 0b0..Module is disabled + * 0b1..Module is enabled + */ #define LPSPI_CR_MEN(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_MEN_SHIFT)) & LPSPI_CR_MEN_MASK) #define LPSPI_CR_RST_MASK (0x2U) #define LPSPI_CR_RST_SHIFT (1U) +/*! RST - Software Reset + * 0b0..Module is not reset + * 0b1..Module is reset + */ #define LPSPI_CR_RST(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_RST_SHIFT)) & LPSPI_CR_RST_MASK) #define LPSPI_CR_DOZEN_MASK (0x4U) #define LPSPI_CR_DOZEN_SHIFT (2U) +/*! DOZEN - Doze mode enable + * 0b0..Module is enabled in Doze mode + * 0b1..Module is disabled in Doze mode + */ #define LPSPI_CR_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_DOZEN_SHIFT)) & LPSPI_CR_DOZEN_MASK) #define LPSPI_CR_DBGEN_MASK (0x8U) #define LPSPI_CR_DBGEN_SHIFT (3U) +/*! DBGEN - Debug Enable + * 0b0..Module is disabled in debug mode + * 0b1..Module is enabled in debug mode + */ #define LPSPI_CR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_DBGEN_SHIFT)) & LPSPI_CR_DBGEN_MASK) #define LPSPI_CR_RTF_MASK (0x100U) #define LPSPI_CR_RTF_SHIFT (8U) +/*! RTF - Reset Transmit FIFO + * 0b0..No effect + * 0b1..Transmit FIFO is reset + */ #define LPSPI_CR_RTF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_RTF_SHIFT)) & LPSPI_CR_RTF_MASK) #define LPSPI_CR_RRF_MASK (0x200U) #define LPSPI_CR_RRF_SHIFT (9U) +/*! RRF - Reset Receive FIFO + * 0b0..No effect + * 0b1..Receive FIFO is reset + */ #define LPSPI_CR_RRF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_RRF_SHIFT)) & LPSPI_CR_RRF_MASK) +/*! @} */ /*! @name SR - Status Register */ +/*! @{ */ #define LPSPI_SR_TDF_MASK (0x1U) #define LPSPI_SR_TDF_SHIFT (0U) +/*! TDF - Transmit Data Flag + * 0b0..Transmit data not requested + * 0b1..Transmit data is requested + */ #define LPSPI_SR_TDF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_TDF_SHIFT)) & LPSPI_SR_TDF_MASK) #define LPSPI_SR_RDF_MASK (0x2U) #define LPSPI_SR_RDF_SHIFT (1U) +/*! RDF - Receive Data Flag + * 0b0..Receive Data is not ready + * 0b1..Receive data is ready + */ #define LPSPI_SR_RDF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_RDF_SHIFT)) & LPSPI_SR_RDF_MASK) #define LPSPI_SR_WCF_MASK (0x100U) #define LPSPI_SR_WCF_SHIFT (8U) +/*! WCF - Word Complete Flag + * 0b0..Transfer of a received word has not yet completed + * 0b1..Transfer of a received word has completed + */ #define LPSPI_SR_WCF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_WCF_SHIFT)) & LPSPI_SR_WCF_MASK) #define LPSPI_SR_FCF_MASK (0x200U) #define LPSPI_SR_FCF_SHIFT (9U) +/*! FCF - Frame Complete Flag + * 0b0..Frame transfer has not completed + * 0b1..Frame transfer has completed + */ #define LPSPI_SR_FCF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_FCF_SHIFT)) & LPSPI_SR_FCF_MASK) #define LPSPI_SR_TCF_MASK (0x400U) #define LPSPI_SR_TCF_SHIFT (10U) +/*! TCF - Transfer Complete Flag + * 0b0..All transfers have not completed + * 0b1..All transfers have completed + */ #define LPSPI_SR_TCF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_TCF_SHIFT)) & LPSPI_SR_TCF_MASK) #define LPSPI_SR_TEF_MASK (0x800U) #define LPSPI_SR_TEF_SHIFT (11U) +/*! TEF - Transmit Error Flag + * 0b0..Transmit FIFO underrun has not occurred + * 0b1..Transmit FIFO underrun has occurred + */ #define LPSPI_SR_TEF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_TEF_SHIFT)) & LPSPI_SR_TEF_MASK) #define LPSPI_SR_REF_MASK (0x1000U) #define LPSPI_SR_REF_SHIFT (12U) +/*! REF - Receive Error Flag + * 0b0..Receive FIFO has not overflowed + * 0b1..Receive FIFO has overflowed + */ #define LPSPI_SR_REF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_REF_SHIFT)) & LPSPI_SR_REF_MASK) #define LPSPI_SR_DMF_MASK (0x2000U) #define LPSPI_SR_DMF_SHIFT (13U) +/*! DMF - Data Match Flag + * 0b0..Have not received matching data + * 0b1..Have received matching data + */ #define LPSPI_SR_DMF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_DMF_SHIFT)) & LPSPI_SR_DMF_MASK) #define LPSPI_SR_MBF_MASK (0x1000000U) #define LPSPI_SR_MBF_SHIFT (24U) +/*! MBF - Module Busy Flag + * 0b0..LPSPI is idle + * 0b1..LPSPI is busy + */ #define LPSPI_SR_MBF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_MBF_SHIFT)) & LPSPI_SR_MBF_MASK) +/*! @} */ /*! @name IER - Interrupt Enable Register */ +/*! @{ */ #define LPSPI_IER_TDIE_MASK (0x1U) #define LPSPI_IER_TDIE_SHIFT (0U) +/*! TDIE - Transmit Data Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ #define LPSPI_IER_TDIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_TDIE_SHIFT)) & LPSPI_IER_TDIE_MASK) #define LPSPI_IER_RDIE_MASK (0x2U) #define LPSPI_IER_RDIE_SHIFT (1U) +/*! RDIE - Receive Data Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ #define LPSPI_IER_RDIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_RDIE_SHIFT)) & LPSPI_IER_RDIE_MASK) #define LPSPI_IER_WCIE_MASK (0x100U) #define LPSPI_IER_WCIE_SHIFT (8U) +/*! WCIE - Word Complete Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ #define LPSPI_IER_WCIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_WCIE_SHIFT)) & LPSPI_IER_WCIE_MASK) #define LPSPI_IER_FCIE_MASK (0x200U) #define LPSPI_IER_FCIE_SHIFT (9U) +/*! FCIE - Frame Complete Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ #define LPSPI_IER_FCIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_FCIE_SHIFT)) & LPSPI_IER_FCIE_MASK) #define LPSPI_IER_TCIE_MASK (0x400U) #define LPSPI_IER_TCIE_SHIFT (10U) +/*! TCIE - Transfer Complete Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ #define LPSPI_IER_TCIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_TCIE_SHIFT)) & LPSPI_IER_TCIE_MASK) #define LPSPI_IER_TEIE_MASK (0x800U) #define LPSPI_IER_TEIE_SHIFT (11U) +/*! TEIE - Transmit Error Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ #define LPSPI_IER_TEIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_TEIE_SHIFT)) & LPSPI_IER_TEIE_MASK) #define LPSPI_IER_REIE_MASK (0x1000U) #define LPSPI_IER_REIE_SHIFT (12U) +/*! REIE - Receive Error Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ #define LPSPI_IER_REIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_REIE_SHIFT)) & LPSPI_IER_REIE_MASK) #define LPSPI_IER_DMIE_MASK (0x2000U) #define LPSPI_IER_DMIE_SHIFT (13U) +/*! DMIE - Data Match Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ #define LPSPI_IER_DMIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_DMIE_SHIFT)) & LPSPI_IER_DMIE_MASK) +/*! @} */ /*! @name DER - DMA Enable Register */ +/*! @{ */ #define LPSPI_DER_TDDE_MASK (0x1U) #define LPSPI_DER_TDDE_SHIFT (0U) +/*! TDDE - Transmit Data DMA Enable + * 0b0..DMA request is disabled + * 0b1..DMA request is enabled + */ #define LPSPI_DER_TDDE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_DER_TDDE_SHIFT)) & LPSPI_DER_TDDE_MASK) #define LPSPI_DER_RDDE_MASK (0x2U) #define LPSPI_DER_RDDE_SHIFT (1U) +/*! RDDE - Receive Data DMA Enable + * 0b0..DMA request is disabled + * 0b1..DMA request is enabled + */ #define LPSPI_DER_RDDE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_DER_RDDE_SHIFT)) & LPSPI_DER_RDDE_MASK) +/*! @} */ /*! @name CFGR0 - Configuration Register 0 */ +/*! @{ */ #define LPSPI_CFGR0_HREN_MASK (0x1U) #define LPSPI_CFGR0_HREN_SHIFT (0U) +/*! HREN - Host Request Enable + * 0b0..Host request is disabled + * 0b1..Host request is enabled + */ #define LPSPI_CFGR0_HREN(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_HREN_SHIFT)) & LPSPI_CFGR0_HREN_MASK) #define LPSPI_CFGR0_HRPOL_MASK (0x2U) #define LPSPI_CFGR0_HRPOL_SHIFT (1U) +/*! HRPOL - Host Request Polarity + * 0b0..Active low + * 0b1..Active high + */ #define LPSPI_CFGR0_HRPOL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_HRPOL_SHIFT)) & LPSPI_CFGR0_HRPOL_MASK) #define LPSPI_CFGR0_HRSEL_MASK (0x4U) #define LPSPI_CFGR0_HRSEL_SHIFT (2U) +/*! HRSEL - Host Request Select + * 0b0..Host request input is the LPSPI_HREQ pin + * 0b1..Host request input is the input trigger + */ #define LPSPI_CFGR0_HRSEL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_HRSEL_SHIFT)) & LPSPI_CFGR0_HRSEL_MASK) #define LPSPI_CFGR0_CIRFIFO_MASK (0x100U) #define LPSPI_CFGR0_CIRFIFO_SHIFT (8U) +/*! CIRFIFO - Circular FIFO Enable + * 0b0..Circular FIFO is disabled + * 0b1..Circular FIFO is enabled + */ #define LPSPI_CFGR0_CIRFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_CIRFIFO_SHIFT)) & LPSPI_CFGR0_CIRFIFO_MASK) #define LPSPI_CFGR0_RDMO_MASK (0x200U) #define LPSPI_CFGR0_RDMO_SHIFT (9U) +/*! RDMO - Receive Data Match Only + * 0b0..Received data is stored in the receive FIFO as in normal operations + * 0b1..Received data is discarded unless the Data Match Flag (DMF) is set + */ #define LPSPI_CFGR0_RDMO(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_RDMO_SHIFT)) & LPSPI_CFGR0_RDMO_MASK) +/*! @} */ /*! @name CFGR1 - Configuration Register 1 */ +/*! @{ */ #define LPSPI_CFGR1_MASTER_MASK (0x1U) #define LPSPI_CFGR1_MASTER_SHIFT (0U) +/*! MASTER - Master Mode + * 0b0..Slave mode + * 0b1..Master mode + */ #define LPSPI_CFGR1_MASTER(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_MASTER_SHIFT)) & LPSPI_CFGR1_MASTER_MASK) #define LPSPI_CFGR1_SAMPLE_MASK (0x2U) #define LPSPI_CFGR1_SAMPLE_SHIFT (1U) +/*! SAMPLE - Sample Point + * 0b0..Input data is sampled on SCK edge + * 0b1..Input data is sampled on delayed SCK edge + */ #define LPSPI_CFGR1_SAMPLE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_SAMPLE_SHIFT)) & LPSPI_CFGR1_SAMPLE_MASK) #define LPSPI_CFGR1_AUTOPCS_MASK (0x4U) #define LPSPI_CFGR1_AUTOPCS_SHIFT (2U) +/*! AUTOPCS - Automatic PCS + * 0b0..Automatic PCS generation is disabled + * 0b1..Automatic PCS generation is enabled + */ #define LPSPI_CFGR1_AUTOPCS(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_AUTOPCS_SHIFT)) & LPSPI_CFGR1_AUTOPCS_MASK) #define LPSPI_CFGR1_NOSTALL_MASK (0x8U) #define LPSPI_CFGR1_NOSTALL_SHIFT (3U) +/*! NOSTALL - No Stall + * 0b0..Transfers will stall when the transmit FIFO is empty or the receive FIFO is full + * 0b1..Transfers will not stall, allowing transmit FIFO underruns or receive FIFO overruns to occur + */ #define LPSPI_CFGR1_NOSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_NOSTALL_SHIFT)) & LPSPI_CFGR1_NOSTALL_MASK) #define LPSPI_CFGR1_PCSPOL_MASK (0xF00U) #define LPSPI_CFGR1_PCSPOL_SHIFT (8U) +/*! PCSPOL - Peripheral Chip Select Polarity + * 0b0000..The Peripheral Chip Select pin PCSx is active low + * 0b0001..The Peripheral Chip Select pin PCSx is active high + */ #define LPSPI_CFGR1_PCSPOL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PCSPOL_SHIFT)) & LPSPI_CFGR1_PCSPOL_MASK) #define LPSPI_CFGR1_MATCFG_MASK (0x70000U) #define LPSPI_CFGR1_MATCFG_SHIFT (16U) +/*! MATCFG - Match Configuration + * 0b000..Match is disabled + * 0b001..Reserved + * 0b010..010b - Match is enabled, if 1st data word equals MATCH0 OR MATCH1, i.e., (1st data word = MATCH0 + MATCH1) + * 0b011..011b - Match is enabled, if any data word equals MATCH0 OR MATCH1, i.e., (any data word = MATCH0 + MATCH1) + * 0b100..100b - Match is enabled, if 1st data word equals MATCH0 AND 2nd data word equals MATCH1, i.e., [(1st data word = MATCH0) * (2nd data word = MATCH1)] + * 0b101..101b - Match is enabled, if any data word equals MATCH0 AND the next data word equals MATCH1, i.e., [(any data word = MATCH0) * (next data word = MATCH1)] + * 0b110..110b - Match is enabled, if (1st data word AND MATCH1) equals (MATCH0 AND MATCH1), i.e., [(1st data word * MATCH1) = (MATCH0 * MATCH1)] + * 0b111..111b - Match is enabled, if (any data word AND MATCH1) equals (MATCH0 AND MATCH1), i.e., [(any data word * MATCH1) = (MATCH0 * MATCH1)] + */ #define LPSPI_CFGR1_MATCFG(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_MATCFG_SHIFT)) & LPSPI_CFGR1_MATCFG_MASK) #define LPSPI_CFGR1_PINCFG_MASK (0x3000000U) #define LPSPI_CFGR1_PINCFG_SHIFT (24U) +/*! PINCFG - Pin Configuration + * 0b00..SIN is used for input data and SOUT is used for output data + * 0b01..SIN is used for both input and output data + * 0b10..SOUT is used for both input and output data + * 0b11..SOUT is used for input data and SIN is used for output data + */ #define LPSPI_CFGR1_PINCFG(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PINCFG_SHIFT)) & LPSPI_CFGR1_PINCFG_MASK) #define LPSPI_CFGR1_OUTCFG_MASK (0x4000000U) #define LPSPI_CFGR1_OUTCFG_SHIFT (26U) +/*! OUTCFG - Output Config + * 0b0..Output data retains last value when chip select is negated + * 0b1..Output data is tristated when chip select is negated + */ #define LPSPI_CFGR1_OUTCFG(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_OUTCFG_SHIFT)) & LPSPI_CFGR1_OUTCFG_MASK) #define LPSPI_CFGR1_PCSCFG_MASK (0x8000000U) #define LPSPI_CFGR1_PCSCFG_SHIFT (27U) +/*! PCSCFG - Peripheral Chip Select Configuration + * 0b0..PCS[3:2] are enabled + * 0b1..PCS[3:2] are disabled + */ #define LPSPI_CFGR1_PCSCFG(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PCSCFG_SHIFT)) & LPSPI_CFGR1_PCSCFG_MASK) +/*! @} */ /*! @name DMR0 - Data Match Register 0 */ +/*! @{ */ #define LPSPI_DMR0_MATCH0_MASK (0xFFFFFFFFU) #define LPSPI_DMR0_MATCH0_SHIFT (0U) #define LPSPI_DMR0_MATCH0(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_DMR0_MATCH0_SHIFT)) & LPSPI_DMR0_MATCH0_MASK) +/*! @} */ /*! @name DMR1 - Data Match Register 1 */ +/*! @{ */ #define LPSPI_DMR1_MATCH1_MASK (0xFFFFFFFFU) #define LPSPI_DMR1_MATCH1_SHIFT (0U) #define LPSPI_DMR1_MATCH1(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_DMR1_MATCH1_SHIFT)) & LPSPI_DMR1_MATCH1_MASK) +/*! @} */ /*! @name CCR - Clock Configuration Register */ +/*! @{ */ #define LPSPI_CCR_SCKDIV_MASK (0xFFU) #define LPSPI_CCR_SCKDIV_SHIFT (0U) #define LPSPI_CCR_SCKDIV(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_SCKDIV_SHIFT)) & LPSPI_CCR_SCKDIV_MASK) @@ -13447,78 +21475,153 @@ typedef struct { #define LPSPI_CCR_SCKPCS_MASK (0xFF000000U) #define LPSPI_CCR_SCKPCS_SHIFT (24U) #define LPSPI_CCR_SCKPCS(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_SCKPCS_SHIFT)) & LPSPI_CCR_SCKPCS_MASK) +/*! @} */ /*! @name FCR - FIFO Control Register */ +/*! @{ */ #define LPSPI_FCR_TXWATER_MASK (0xFU) #define LPSPI_FCR_TXWATER_SHIFT (0U) #define LPSPI_FCR_TXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_FCR_TXWATER_SHIFT)) & LPSPI_FCR_TXWATER_MASK) #define LPSPI_FCR_RXWATER_MASK (0xF0000U) #define LPSPI_FCR_RXWATER_SHIFT (16U) #define LPSPI_FCR_RXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_FCR_RXWATER_SHIFT)) & LPSPI_FCR_RXWATER_MASK) +/*! @} */ /*! @name FSR - FIFO Status Register */ +/*! @{ */ #define LPSPI_FSR_TXCOUNT_MASK (0x1FU) #define LPSPI_FSR_TXCOUNT_SHIFT (0U) #define LPSPI_FSR_TXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_FSR_TXCOUNT_SHIFT)) & LPSPI_FSR_TXCOUNT_MASK) #define LPSPI_FSR_RXCOUNT_MASK (0x1F0000U) #define LPSPI_FSR_RXCOUNT_SHIFT (16U) #define LPSPI_FSR_RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_FSR_RXCOUNT_SHIFT)) & LPSPI_FSR_RXCOUNT_MASK) +/*! @} */ /*! @name TCR - Transmit Command Register */ +/*! @{ */ #define LPSPI_TCR_FRAMESZ_MASK (0xFFFU) #define LPSPI_TCR_FRAMESZ_SHIFT (0U) #define LPSPI_TCR_FRAMESZ(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_FRAMESZ_SHIFT)) & LPSPI_TCR_FRAMESZ_MASK) #define LPSPI_TCR_WIDTH_MASK (0x30000U) #define LPSPI_TCR_WIDTH_SHIFT (16U) +/*! WIDTH - Transfer Width + * 0b00..1 bit transfer + * 0b01..2 bit transfer + * 0b10..4 bit transfer + * 0b11..Reserved + */ #define LPSPI_TCR_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_WIDTH_SHIFT)) & LPSPI_TCR_WIDTH_MASK) #define LPSPI_TCR_TXMSK_MASK (0x40000U) #define LPSPI_TCR_TXMSK_SHIFT (18U) +/*! TXMSK - Transmit Data Mask + * 0b0..Normal transfer + * 0b1..Mask transmit data + */ #define LPSPI_TCR_TXMSK(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_TXMSK_SHIFT)) & LPSPI_TCR_TXMSK_MASK) #define LPSPI_TCR_RXMSK_MASK (0x80000U) #define LPSPI_TCR_RXMSK_SHIFT (19U) +/*! RXMSK - Receive Data Mask + * 0b0..Normal transfer + * 0b1..Receive data is masked + */ #define LPSPI_TCR_RXMSK(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_RXMSK_SHIFT)) & LPSPI_TCR_RXMSK_MASK) #define LPSPI_TCR_CONTC_MASK (0x100000U) #define LPSPI_TCR_CONTC_SHIFT (20U) +/*! CONTC - Continuing Command + * 0b0..Command word for start of new transfer + * 0b1..Command word for continuing transfer + */ #define LPSPI_TCR_CONTC(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CONTC_SHIFT)) & LPSPI_TCR_CONTC_MASK) #define LPSPI_TCR_CONT_MASK (0x200000U) #define LPSPI_TCR_CONT_SHIFT (21U) +/*! CONT - Continuous Transfer + * 0b0..Continuous transfer is disabled + * 0b1..Continuous transfer is enabled + */ #define LPSPI_TCR_CONT(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CONT_SHIFT)) & LPSPI_TCR_CONT_MASK) #define LPSPI_TCR_BYSW_MASK (0x400000U) #define LPSPI_TCR_BYSW_SHIFT (22U) +/*! BYSW - Byte Swap + * 0b0..Byte swap is disabled + * 0b1..Byte swap is enabled + */ #define LPSPI_TCR_BYSW(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_BYSW_SHIFT)) & LPSPI_TCR_BYSW_MASK) #define LPSPI_TCR_LSBF_MASK (0x800000U) #define LPSPI_TCR_LSBF_SHIFT (23U) +/*! LSBF - LSB First + * 0b0..Data is transferred MSB first + * 0b1..Data is transferred LSB first + */ #define LPSPI_TCR_LSBF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_LSBF_SHIFT)) & LPSPI_TCR_LSBF_MASK) #define LPSPI_TCR_PCS_MASK (0x3000000U) #define LPSPI_TCR_PCS_SHIFT (24U) +/*! PCS - Peripheral Chip Select + * 0b00..Transfer using LPSPI_PCS[0] + * 0b01..Transfer using LPSPI_PCS[1] + * 0b10..Transfer using LPSPI_PCS[2] + * 0b11..Transfer using LPSPI_PCS[3] + */ #define LPSPI_TCR_PCS(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_PCS_SHIFT)) & LPSPI_TCR_PCS_MASK) #define LPSPI_TCR_PRESCALE_MASK (0x38000000U) #define LPSPI_TCR_PRESCALE_SHIFT (27U) +/*! PRESCALE - Prescaler Value + * 0b000..Divide by 1 + * 0b001..Divide by 2 + * 0b010..Divide by 4 + * 0b011..Divide by 8 + * 0b100..Divide by 16 + * 0b101..Divide by 32 + * 0b110..Divide by 64 + * 0b111..Divide by 128 + */ #define LPSPI_TCR_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_PRESCALE_SHIFT)) & LPSPI_TCR_PRESCALE_MASK) #define LPSPI_TCR_CPHA_MASK (0x40000000U) #define LPSPI_TCR_CPHA_SHIFT (30U) +/*! CPHA - Clock Phase + * 0b0..Data is captured on the leading edge of SCK and changed on the following edge of SCK + * 0b1..Data is changed on the leading edge of SCK and captured on the following edge of SCK + */ #define LPSPI_TCR_CPHA(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CPHA_SHIFT)) & LPSPI_TCR_CPHA_MASK) #define LPSPI_TCR_CPOL_MASK (0x80000000U) #define LPSPI_TCR_CPOL_SHIFT (31U) +/*! CPOL - Clock Polarity + * 0b0..The inactive state value of SCK is low + * 0b1..The inactive state value of SCK is high + */ #define LPSPI_TCR_CPOL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CPOL_SHIFT)) & LPSPI_TCR_CPOL_MASK) +/*! @} */ /*! @name TDR - Transmit Data Register */ +/*! @{ */ #define LPSPI_TDR_DATA_MASK (0xFFFFFFFFU) #define LPSPI_TDR_DATA_SHIFT (0U) #define LPSPI_TDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TDR_DATA_SHIFT)) & LPSPI_TDR_DATA_MASK) +/*! @} */ /*! @name RSR - Receive Status Register */ +/*! @{ */ #define LPSPI_RSR_SOF_MASK (0x1U) #define LPSPI_RSR_SOF_SHIFT (0U) +/*! SOF - Start Of Frame + * 0b0..Subsequent data word received after LPSPI_PCS assertion + * 0b1..First data word received after LPSPI_PCS assertion + */ #define LPSPI_RSR_SOF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_RSR_SOF_SHIFT)) & LPSPI_RSR_SOF_MASK) #define LPSPI_RSR_RXEMPTY_MASK (0x2U) #define LPSPI_RSR_RXEMPTY_SHIFT (1U) +/*! RXEMPTY - RX FIFO Empty + * 0b0..RX FIFO is not empty + * 0b1..RX FIFO is empty + */ #define LPSPI_RSR_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_RSR_RXEMPTY_SHIFT)) & LPSPI_RSR_RXEMPTY_MASK) +/*! @} */ /*! @name RDR - Receive Data Register */ +/*! @{ */ #define LPSPI_RDR_DATA_MASK (0xFFFFFFFFU) #define LPSPI_RDR_DATA_SHIFT (0U) #define LPSPI_RDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_RDR_DATA_SHIFT)) & LPSPI_RDR_DATA_MASK) +/*! @} */ /*! @@ -13590,8 +21693,13 @@ typedef struct { */ /*! @name VERID - Version ID Register */ +/*! @{ */ #define LPUART_VERID_FEATURE_MASK (0xFFFFU) #define LPUART_VERID_FEATURE_SHIFT (0U) +/*! FEATURE - Feature Identification Number + * 0b0000000000000001..Standard feature set. + * 0b0000000000000011..Standard feature set with MODEM/IrDA support. + */ #define LPUART_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_VERID_FEATURE_SHIFT)) & LPUART_VERID_FEATURE_MASK) #define LPUART_VERID_MINOR_MASK (0xFF0000U) #define LPUART_VERID_MINOR_SHIFT (16U) @@ -13599,200 +21707,491 @@ typedef struct { #define LPUART_VERID_MAJOR_MASK (0xFF000000U) #define LPUART_VERID_MAJOR_SHIFT (24U) #define LPUART_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_VERID_MAJOR_SHIFT)) & LPUART_VERID_MAJOR_MASK) +/*! @} */ /*! @name PARAM - Parameter Register */ +/*! @{ */ #define LPUART_PARAM_TXFIFO_MASK (0xFFU) #define LPUART_PARAM_TXFIFO_SHIFT (0U) #define LPUART_PARAM_TXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPUART_PARAM_TXFIFO_SHIFT)) & LPUART_PARAM_TXFIFO_MASK) #define LPUART_PARAM_RXFIFO_MASK (0xFF00U) #define LPUART_PARAM_RXFIFO_SHIFT (8U) #define LPUART_PARAM_RXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPUART_PARAM_RXFIFO_SHIFT)) & LPUART_PARAM_RXFIFO_MASK) +/*! @} */ /*! @name GLOBAL - LPUART Global Register */ +/*! @{ */ #define LPUART_GLOBAL_RST_MASK (0x2U) #define LPUART_GLOBAL_RST_SHIFT (1U) +/*! RST - Software Reset + * 0b0..Module is not reset. + * 0b1..Module is reset. + */ #define LPUART_GLOBAL_RST(x) (((uint32_t)(((uint32_t)(x)) << LPUART_GLOBAL_RST_SHIFT)) & LPUART_GLOBAL_RST_MASK) +/*! @} */ /*! @name PINCFG - LPUART Pin Configuration Register */ +/*! @{ */ #define LPUART_PINCFG_TRGSEL_MASK (0x3U) #define LPUART_PINCFG_TRGSEL_SHIFT (0U) +/*! TRGSEL - Trigger Select + * 0b00..Input trigger is disabled. + * 0b01..Input trigger is used instead of RXD pin input. + * 0b10..Input trigger is used instead of CTS_B pin input. + * 0b11..Input trigger is used to modulate the TXD pin output. The TXD pin output (after TXINV configuration) is ANDed with the input trigger. + */ #define LPUART_PINCFG_TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << LPUART_PINCFG_TRGSEL_SHIFT)) & LPUART_PINCFG_TRGSEL_MASK) +/*! @} */ /*! @name BAUD - LPUART Baud Rate Register */ +/*! @{ */ #define LPUART_BAUD_SBR_MASK (0x1FFFU) #define LPUART_BAUD_SBR_SHIFT (0U) #define LPUART_BAUD_SBR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_SBR_SHIFT)) & LPUART_BAUD_SBR_MASK) #define LPUART_BAUD_SBNS_MASK (0x2000U) #define LPUART_BAUD_SBNS_SHIFT (13U) +/*! SBNS - Stop Bit Number Select + * 0b0..One stop bit. + * 0b1..Two stop bits. + */ #define LPUART_BAUD_SBNS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_SBNS_SHIFT)) & LPUART_BAUD_SBNS_MASK) #define LPUART_BAUD_RXEDGIE_MASK (0x4000U) #define LPUART_BAUD_RXEDGIE_SHIFT (14U) +/*! RXEDGIE - RX Input Active Edge Interrupt Enable + * 0b0..Hardware interrupts from STAT[RXEDGIF] are disabled. + * 0b1..Hardware interrupt is requested when STAT[RXEDGIF] flag is 1. + */ #define LPUART_BAUD_RXEDGIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RXEDGIE_SHIFT)) & LPUART_BAUD_RXEDGIE_MASK) #define LPUART_BAUD_LBKDIE_MASK (0x8000U) #define LPUART_BAUD_LBKDIE_SHIFT (15U) +/*! LBKDIE - LIN Break Detect Interrupt Enable + * 0b0..Hardware interrupts from STAT[LBKDIF] flag are disabled (use polling). + * 0b1..Hardware interrupt requested when STAT[LBKDIF] flag is 1. + */ #define LPUART_BAUD_LBKDIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_LBKDIE_SHIFT)) & LPUART_BAUD_LBKDIE_MASK) #define LPUART_BAUD_RESYNCDIS_MASK (0x10000U) #define LPUART_BAUD_RESYNCDIS_SHIFT (16U) +/*! RESYNCDIS - Resynchronization Disable + * 0b0..Resynchronization during received data word is supported + * 0b1..Resynchronization during received data word is disabled + */ #define LPUART_BAUD_RESYNCDIS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RESYNCDIS_SHIFT)) & LPUART_BAUD_RESYNCDIS_MASK) #define LPUART_BAUD_BOTHEDGE_MASK (0x20000U) #define LPUART_BAUD_BOTHEDGE_SHIFT (17U) +/*! BOTHEDGE - Both Edge Sampling + * 0b0..Receiver samples input data using the rising edge of the baud rate clock. + * 0b1..Receiver samples input data using the rising and falling edge of the baud rate clock. + */ #define LPUART_BAUD_BOTHEDGE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_BOTHEDGE_SHIFT)) & LPUART_BAUD_BOTHEDGE_MASK) #define LPUART_BAUD_MATCFG_MASK (0xC0000U) #define LPUART_BAUD_MATCFG_SHIFT (18U) +/*! MATCFG - Match Configuration + * 0b00..Address Match Wakeup + * 0b01..Idle Match Wakeup + * 0b10..Match On and Match Off + * 0b11..Enables RWU on Data Match and Match On/Off for transmitter CTS input + */ #define LPUART_BAUD_MATCFG(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MATCFG_SHIFT)) & LPUART_BAUD_MATCFG_MASK) +#define LPUART_BAUD_RIDMAE_MASK (0x100000U) +#define LPUART_BAUD_RIDMAE_SHIFT (20U) +/*! RIDMAE - Receiver Idle DMA Enable + * 0b0..DMA request disabled. + * 0b1..DMA request enabled. + */ +#define LPUART_BAUD_RIDMAE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RIDMAE_SHIFT)) & LPUART_BAUD_RIDMAE_MASK) #define LPUART_BAUD_RDMAE_MASK (0x200000U) #define LPUART_BAUD_RDMAE_SHIFT (21U) +/*! RDMAE - Receiver Full DMA Enable + * 0b0..DMA request disabled. + * 0b1..DMA request enabled. + */ #define LPUART_BAUD_RDMAE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RDMAE_SHIFT)) & LPUART_BAUD_RDMAE_MASK) #define LPUART_BAUD_TDMAE_MASK (0x800000U) #define LPUART_BAUD_TDMAE_SHIFT (23U) +/*! TDMAE - Transmitter DMA Enable + * 0b0..DMA request disabled. + * 0b1..DMA request enabled. + */ #define LPUART_BAUD_TDMAE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_TDMAE_SHIFT)) & LPUART_BAUD_TDMAE_MASK) #define LPUART_BAUD_OSR_MASK (0x1F000000U) #define LPUART_BAUD_OSR_SHIFT (24U) +/*! OSR - Oversampling Ratio + * 0b00000..Writing 0 to this field will result in an oversampling ratio of 16 + * 0b00001..Reserved + * 0b00010..Reserved + * 0b00011..Oversampling ratio of 4, requires BOTHEDGE to be set. + * 0b00100..Oversampling ratio of 5, requires BOTHEDGE to be set. + * 0b00101..Oversampling ratio of 6, requires BOTHEDGE to be set. + * 0b00110..Oversampling ratio of 7, requires BOTHEDGE to be set. + * 0b00111..Oversampling ratio of 8. + * 0b01000..Oversampling ratio of 9. + * 0b01001..Oversampling ratio of 10. + * 0b01010..Oversampling ratio of 11. + * 0b01011..Oversampling ratio of 12. + * 0b01100..Oversampling ratio of 13. + * 0b01101..Oversampling ratio of 14. + * 0b01110..Oversampling ratio of 15. + * 0b01111..Oversampling ratio of 16. + * 0b10000..Oversampling ratio of 17. + * 0b10001..Oversampling ratio of 18. + * 0b10010..Oversampling ratio of 19. + * 0b10011..Oversampling ratio of 20. + * 0b10100..Oversampling ratio of 21. + * 0b10101..Oversampling ratio of 22. + * 0b10110..Oversampling ratio of 23. + * 0b10111..Oversampling ratio of 24. + * 0b11000..Oversampling ratio of 25. + * 0b11001..Oversampling ratio of 26. + * 0b11010..Oversampling ratio of 27. + * 0b11011..Oversampling ratio of 28. + * 0b11100..Oversampling ratio of 29. + * 0b11101..Oversampling ratio of 30. + * 0b11110..Oversampling ratio of 31. + * 0b11111..Oversampling ratio of 32. + */ #define LPUART_BAUD_OSR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_OSR_SHIFT)) & LPUART_BAUD_OSR_MASK) #define LPUART_BAUD_M10_MASK (0x20000000U) #define LPUART_BAUD_M10_SHIFT (29U) +/*! M10 - 10-bit Mode select + * 0b0..Receiver and transmitter use 7-bit to 9-bit data characters. + * 0b1..Receiver and transmitter use 10-bit data characters. + */ #define LPUART_BAUD_M10(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_M10_SHIFT)) & LPUART_BAUD_M10_MASK) #define LPUART_BAUD_MAEN2_MASK (0x40000000U) #define LPUART_BAUD_MAEN2_SHIFT (30U) +/*! MAEN2 - Match Address Mode Enable 2 + * 0b0..Normal operation. + * 0b1..Enables automatic address matching or data matching mode for MATCH[MA2]. + */ #define LPUART_BAUD_MAEN2(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MAEN2_SHIFT)) & LPUART_BAUD_MAEN2_MASK) #define LPUART_BAUD_MAEN1_MASK (0x80000000U) #define LPUART_BAUD_MAEN1_SHIFT (31U) +/*! MAEN1 - Match Address Mode Enable 1 + * 0b0..Normal operation. + * 0b1..Enables automatic address matching or data matching mode for MATCH[MA1]. + */ #define LPUART_BAUD_MAEN1(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MAEN1_SHIFT)) & LPUART_BAUD_MAEN1_MASK) +/*! @} */ /*! @name STAT - LPUART Status Register */ +/*! @{ */ #define LPUART_STAT_MA2F_MASK (0x4000U) #define LPUART_STAT_MA2F_SHIFT (14U) +/*! MA2F - Match 2 Flag + * 0b0..Received data is not equal to MA2 + * 0b1..Received data is equal to MA2 + */ #define LPUART_STAT_MA2F(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MA2F_SHIFT)) & LPUART_STAT_MA2F_MASK) #define LPUART_STAT_MA1F_MASK (0x8000U) #define LPUART_STAT_MA1F_SHIFT (15U) +/*! MA1F - Match 1 Flag + * 0b0..Received data is not equal to MA1 + * 0b1..Received data is equal to MA1 + */ #define LPUART_STAT_MA1F(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MA1F_SHIFT)) & LPUART_STAT_MA1F_MASK) #define LPUART_STAT_PF_MASK (0x10000U) #define LPUART_STAT_PF_SHIFT (16U) +/*! PF - Parity Error Flag + * 0b0..No parity error. + * 0b1..Parity error. + */ #define LPUART_STAT_PF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_PF_SHIFT)) & LPUART_STAT_PF_MASK) #define LPUART_STAT_FE_MASK (0x20000U) #define LPUART_STAT_FE_SHIFT (17U) +/*! FE - Framing Error Flag + * 0b0..No framing error detected. This does not guarantee the framing is correct. + * 0b1..Framing error. + */ #define LPUART_STAT_FE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_FE_SHIFT)) & LPUART_STAT_FE_MASK) #define LPUART_STAT_NF_MASK (0x40000U) #define LPUART_STAT_NF_SHIFT (18U) +/*! NF - Noise Flag + * 0b0..No noise detected. + * 0b1..Noise detected in the received character in the DATA register. + */ #define LPUART_STAT_NF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_NF_SHIFT)) & LPUART_STAT_NF_MASK) #define LPUART_STAT_OR_MASK (0x80000U) #define LPUART_STAT_OR_SHIFT (19U) +/*! OR - Receiver Overrun Flag + * 0b0..No overrun. + * 0b1..Receive overrun (new LPUART data lost). + */ #define LPUART_STAT_OR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_OR_SHIFT)) & LPUART_STAT_OR_MASK) #define LPUART_STAT_IDLE_MASK (0x100000U) #define LPUART_STAT_IDLE_SHIFT (20U) +/*! IDLE - Idle Line Flag + * 0b0..No idle line detected. + * 0b1..Idle line was detected. + */ #define LPUART_STAT_IDLE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_IDLE_SHIFT)) & LPUART_STAT_IDLE_MASK) #define LPUART_STAT_RDRF_MASK (0x200000U) #define LPUART_STAT_RDRF_SHIFT (21U) +/*! RDRF - Receive Data Register Full Flag + * 0b0..Receive data buffer empty. + * 0b1..Receive data buffer full. + */ #define LPUART_STAT_RDRF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RDRF_SHIFT)) & LPUART_STAT_RDRF_MASK) #define LPUART_STAT_TC_MASK (0x400000U) #define LPUART_STAT_TC_SHIFT (22U) +/*! TC - Transmission Complete Flag + * 0b0..Transmitter active (sending data, a preamble, or a break). + * 0b1..Transmitter idle (transmission activity complete). + */ #define LPUART_STAT_TC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_TC_SHIFT)) & LPUART_STAT_TC_MASK) #define LPUART_STAT_TDRE_MASK (0x800000U) #define LPUART_STAT_TDRE_SHIFT (23U) +/*! TDRE - Transmit Data Register Empty Flag + * 0b0..Transmit data buffer full. + * 0b1..Transmit data buffer empty. + */ #define LPUART_STAT_TDRE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_TDRE_SHIFT)) & LPUART_STAT_TDRE_MASK) #define LPUART_STAT_RAF_MASK (0x1000000U) #define LPUART_STAT_RAF_SHIFT (24U) +/*! RAF - Receiver Active Flag + * 0b0..LPUART receiver idle waiting for a start bit. + * 0b1..LPUART receiver active (RXD input not idle). + */ #define LPUART_STAT_RAF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RAF_SHIFT)) & LPUART_STAT_RAF_MASK) #define LPUART_STAT_LBKDE_MASK (0x2000000U) #define LPUART_STAT_LBKDE_SHIFT (25U) +/*! LBKDE - LIN Break Detection Enable + * 0b0..LIN break detect is disabled, normal break character can be detected. + * 0b1..LIN break detect is enabled. LIN break character is detected at length of 11 bit times (if M = 0) or 12 (if M = 1) or 13 (M10 = 1). + */ #define LPUART_STAT_LBKDE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_LBKDE_SHIFT)) & LPUART_STAT_LBKDE_MASK) #define LPUART_STAT_BRK13_MASK (0x4000000U) #define LPUART_STAT_BRK13_SHIFT (26U) +/*! BRK13 - Break Character Generation Length + * 0b0..Break character is transmitted with length of 9 to 13 bit times. + * 0b1..Break character is transmitted with length of 12 to 15 bit times. + */ #define LPUART_STAT_BRK13(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_BRK13_SHIFT)) & LPUART_STAT_BRK13_MASK) #define LPUART_STAT_RWUID_MASK (0x8000000U) #define LPUART_STAT_RWUID_SHIFT (27U) +/*! RWUID - Receive Wake Up Idle Detect + * 0b0..During receive standby state (RWU = 1), the IDLE bit does not get set upon detection of an idle character. During address match wakeup, the IDLE bit does not set when an address does not match. + * 0b1..During receive standby state (RWU = 1), the IDLE bit gets set upon detection of an idle character. During address match wakeup, the IDLE bit does set when an address does not match. + */ #define LPUART_STAT_RWUID(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RWUID_SHIFT)) & LPUART_STAT_RWUID_MASK) #define LPUART_STAT_RXINV_MASK (0x10000000U) #define LPUART_STAT_RXINV_SHIFT (28U) +/*! RXINV - Receive Data Inversion + * 0b0..Receive data not inverted. + * 0b1..Receive data inverted. + */ #define LPUART_STAT_RXINV(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RXINV_SHIFT)) & LPUART_STAT_RXINV_MASK) #define LPUART_STAT_MSBF_MASK (0x20000000U) #define LPUART_STAT_MSBF_SHIFT (29U) +/*! MSBF - MSB First + * 0b0..LSB (bit0) is the first bit that is transmitted following the start bit. Further, the first bit received after the start bit is identified as bit0. + * 0b1..MSB (bit9, bit8, bit7 or bit6) is the first bit that is transmitted following the start bit depending on the setting of CTRL[M], CTRL[PE] and BAUD[M10]. Further, the first bit received after the start bit is identified as bit9, bit8, bit7 or bit6 depending on the setting of CTRL[M] and CTRL[PE]. + */ #define LPUART_STAT_MSBF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MSBF_SHIFT)) & LPUART_STAT_MSBF_MASK) #define LPUART_STAT_RXEDGIF_MASK (0x40000000U) #define LPUART_STAT_RXEDGIF_SHIFT (30U) +/*! RXEDGIF - RXD Pin Active Edge Interrupt Flag + * 0b0..No active edge on the receive pin has occurred. + * 0b1..An active edge on the receive pin has occurred. + */ #define LPUART_STAT_RXEDGIF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RXEDGIF_SHIFT)) & LPUART_STAT_RXEDGIF_MASK) #define LPUART_STAT_LBKDIF_MASK (0x80000000U) #define LPUART_STAT_LBKDIF_SHIFT (31U) +/*! LBKDIF - LIN Break Detect Interrupt Flag + * 0b0..No LIN break character has been detected. + * 0b1..LIN break character has been detected. + */ #define LPUART_STAT_LBKDIF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_LBKDIF_SHIFT)) & LPUART_STAT_LBKDIF_MASK) +/*! @} */ /*! @name CTRL - LPUART Control Register */ +/*! @{ */ #define LPUART_CTRL_PT_MASK (0x1U) #define LPUART_CTRL_PT_SHIFT (0U) +/*! PT - Parity Type + * 0b0..Even parity. + * 0b1..Odd parity. + */ #define LPUART_CTRL_PT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PT_SHIFT)) & LPUART_CTRL_PT_MASK) #define LPUART_CTRL_PE_MASK (0x2U) #define LPUART_CTRL_PE_SHIFT (1U) +/*! PE - Parity Enable + * 0b0..No hardware parity generation or checking. + * 0b1..Parity enabled. + */ #define LPUART_CTRL_PE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PE_SHIFT)) & LPUART_CTRL_PE_MASK) #define LPUART_CTRL_ILT_MASK (0x4U) #define LPUART_CTRL_ILT_SHIFT (2U) +/*! ILT - Idle Line Type Select + * 0b0..Idle character bit count starts after start bit. + * 0b1..Idle character bit count starts after stop bit. + */ #define LPUART_CTRL_ILT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ILT_SHIFT)) & LPUART_CTRL_ILT_MASK) #define LPUART_CTRL_WAKE_MASK (0x8U) #define LPUART_CTRL_WAKE_SHIFT (3U) +/*! WAKE - Receiver Wakeup Method Select + * 0b0..Configures RWU for idle-line wakeup. + * 0b1..Configures RWU with address-mark wakeup. + */ #define LPUART_CTRL_WAKE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_WAKE_SHIFT)) & LPUART_CTRL_WAKE_MASK) #define LPUART_CTRL_M_MASK (0x10U) #define LPUART_CTRL_M_SHIFT (4U) +/*! M - 9-Bit or 8-Bit Mode Select + * 0b0..Receiver and transmitter use 8-bit data characters. + * 0b1..Receiver and transmitter use 9-bit data characters. + */ #define LPUART_CTRL_M(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_M_SHIFT)) & LPUART_CTRL_M_MASK) #define LPUART_CTRL_RSRC_MASK (0x20U) #define LPUART_CTRL_RSRC_SHIFT (5U) +/*! RSRC - Receiver Source Select + * 0b0..Provided LOOPS is set, RSRC is cleared, selects internal loop back mode and the LPUART does not use the RXD pin. + * 0b1..Single-wire LPUART mode where the TXD pin is connected to the transmitter output and receiver input. + */ #define LPUART_CTRL_RSRC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RSRC_SHIFT)) & LPUART_CTRL_RSRC_MASK) #define LPUART_CTRL_DOZEEN_MASK (0x40U) #define LPUART_CTRL_DOZEEN_SHIFT (6U) +/*! DOZEEN - Doze Enable + * 0b0..LPUART is enabled in Doze mode. + * 0b1..LPUART is disabled in Doze mode. + */ #define LPUART_CTRL_DOZEEN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_DOZEEN_SHIFT)) & LPUART_CTRL_DOZEEN_MASK) #define LPUART_CTRL_LOOPS_MASK (0x80U) #define LPUART_CTRL_LOOPS_SHIFT (7U) +/*! LOOPS - Loop Mode Select + * 0b0..Normal operation - RXD and TXD use separate pins. + * 0b1..Loop mode or single-wire mode where transmitter outputs are internally connected to receiver input (see RSRC bit). + */ #define LPUART_CTRL_LOOPS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_LOOPS_SHIFT)) & LPUART_CTRL_LOOPS_MASK) #define LPUART_CTRL_IDLECFG_MASK (0x700U) #define LPUART_CTRL_IDLECFG_SHIFT (8U) +/*! IDLECFG - Idle Configuration + * 0b000..1 idle character + * 0b001..2 idle characters + * 0b010..4 idle characters + * 0b011..8 idle characters + * 0b100..16 idle characters + * 0b101..32 idle characters + * 0b110..64 idle characters + * 0b111..128 idle characters + */ #define LPUART_CTRL_IDLECFG(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_IDLECFG_SHIFT)) & LPUART_CTRL_IDLECFG_MASK) #define LPUART_CTRL_M7_MASK (0x800U) #define LPUART_CTRL_M7_SHIFT (11U) +/*! M7 - 7-Bit Mode Select + * 0b0..Receiver and transmitter use 8-bit to 10-bit data characters. + * 0b1..Receiver and transmitter use 7-bit data characters. + */ #define LPUART_CTRL_M7(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_M7_SHIFT)) & LPUART_CTRL_M7_MASK) #define LPUART_CTRL_MA2IE_MASK (0x4000U) #define LPUART_CTRL_MA2IE_SHIFT (14U) +/*! MA2IE - Match 2 Interrupt Enable + * 0b0..MA2F interrupt disabled + * 0b1..MA2F interrupt enabled + */ #define LPUART_CTRL_MA2IE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_MA2IE_SHIFT)) & LPUART_CTRL_MA2IE_MASK) #define LPUART_CTRL_MA1IE_MASK (0x8000U) #define LPUART_CTRL_MA1IE_SHIFT (15U) +/*! MA1IE - Match 1 Interrupt Enable + * 0b0..MA1F interrupt disabled + * 0b1..MA1F interrupt enabled + */ #define LPUART_CTRL_MA1IE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_MA1IE_SHIFT)) & LPUART_CTRL_MA1IE_MASK) #define LPUART_CTRL_SBK_MASK (0x10000U) #define LPUART_CTRL_SBK_SHIFT (16U) +/*! SBK - Send Break + * 0b0..Normal transmitter operation. + * 0b1..Queue break character(s) to be sent. + */ #define LPUART_CTRL_SBK(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_SBK_SHIFT)) & LPUART_CTRL_SBK_MASK) #define LPUART_CTRL_RWU_MASK (0x20000U) #define LPUART_CTRL_RWU_SHIFT (17U) +/*! RWU - Receiver Wakeup Control + * 0b0..Normal receiver operation. + * 0b1..LPUART receiver in standby waiting for wakeup condition. + */ #define LPUART_CTRL_RWU(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RWU_SHIFT)) & LPUART_CTRL_RWU_MASK) #define LPUART_CTRL_RE_MASK (0x40000U) #define LPUART_CTRL_RE_SHIFT (18U) +/*! RE - Receiver Enable + * 0b0..Receiver disabled. + * 0b1..Receiver enabled. + */ #define LPUART_CTRL_RE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RE_SHIFT)) & LPUART_CTRL_RE_MASK) #define LPUART_CTRL_TE_MASK (0x80000U) #define LPUART_CTRL_TE_SHIFT (19U) +/*! TE - Transmitter Enable + * 0b0..Transmitter disabled. + * 0b1..Transmitter enabled. + */ #define LPUART_CTRL_TE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TE_SHIFT)) & LPUART_CTRL_TE_MASK) #define LPUART_CTRL_ILIE_MASK (0x100000U) #define LPUART_CTRL_ILIE_SHIFT (20U) +/*! ILIE - Idle Line Interrupt Enable + * 0b0..Hardware interrupts from IDLE disabled; use polling. + * 0b1..Hardware interrupt requested when IDLE flag is 1. + */ #define LPUART_CTRL_ILIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ILIE_SHIFT)) & LPUART_CTRL_ILIE_MASK) #define LPUART_CTRL_RIE_MASK (0x200000U) #define LPUART_CTRL_RIE_SHIFT (21U) +/*! RIE - Receiver Interrupt Enable + * 0b0..Hardware interrupts from RDRF disabled; use polling. + * 0b1..Hardware interrupt requested when RDRF flag is 1. + */ #define LPUART_CTRL_RIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RIE_SHIFT)) & LPUART_CTRL_RIE_MASK) #define LPUART_CTRL_TCIE_MASK (0x400000U) #define LPUART_CTRL_TCIE_SHIFT (22U) +/*! TCIE - Transmission Complete Interrupt Enable for + * 0b0..Hardware interrupts from TC disabled; use polling. + * 0b1..Hardware interrupt requested when TC flag is 1. + */ #define LPUART_CTRL_TCIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TCIE_SHIFT)) & LPUART_CTRL_TCIE_MASK) #define LPUART_CTRL_TIE_MASK (0x800000U) #define LPUART_CTRL_TIE_SHIFT (23U) +/*! TIE - Transmit Interrupt Enable + * 0b0..Hardware interrupts from TDRE disabled; use polling. + * 0b1..Hardware interrupt requested when TDRE flag is 1. + */ #define LPUART_CTRL_TIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TIE_SHIFT)) & LPUART_CTRL_TIE_MASK) #define LPUART_CTRL_PEIE_MASK (0x1000000U) #define LPUART_CTRL_PEIE_SHIFT (24U) +/*! PEIE - Parity Error Interrupt Enable + * 0b0..PF interrupts disabled; use polling). + * 0b1..Hardware interrupt requested when PF is set. + */ #define LPUART_CTRL_PEIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PEIE_SHIFT)) & LPUART_CTRL_PEIE_MASK) #define LPUART_CTRL_FEIE_MASK (0x2000000U) #define LPUART_CTRL_FEIE_SHIFT (25U) +/*! FEIE - Framing Error Interrupt Enable + * 0b0..FE interrupts disabled; use polling. + * 0b1..Hardware interrupt requested when FE is set. + */ #define LPUART_CTRL_FEIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_FEIE_SHIFT)) & LPUART_CTRL_FEIE_MASK) #define LPUART_CTRL_NEIE_MASK (0x4000000U) #define LPUART_CTRL_NEIE_SHIFT (26U) +/*! NEIE - Noise Error Interrupt Enable + * 0b0..NF interrupts disabled; use polling. + * 0b1..Hardware interrupt requested when NF is set. + */ #define LPUART_CTRL_NEIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_NEIE_SHIFT)) & LPUART_CTRL_NEIE_MASK) #define LPUART_CTRL_ORIE_MASK (0x8000000U) #define LPUART_CTRL_ORIE_SHIFT (27U) +/*! ORIE - Overrun Interrupt Enable + * 0b0..OR interrupts disabled; use polling. + * 0b1..Hardware interrupt requested when OR is set. + */ #define LPUART_CTRL_ORIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ORIE_SHIFT)) & LPUART_CTRL_ORIE_MASK) #define LPUART_CTRL_TXINV_MASK (0x10000000U) #define LPUART_CTRL_TXINV_SHIFT (28U) +/*! TXINV - Transmit Data Inversion + * 0b0..Transmit data not inverted. + * 0b1..Transmit data inverted. + */ #define LPUART_CTRL_TXINV(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TXINV_SHIFT)) & LPUART_CTRL_TXINV_MASK) #define LPUART_CTRL_TXDIR_MASK (0x20000000U) #define LPUART_CTRL_TXDIR_SHIFT (29U) +/*! TXDIR - TXD Pin Direction in Single-Wire Mode + * 0b0..TXD pin is an input in single-wire mode. + * 0b1..TXD pin is an output in single-wire mode. + */ #define LPUART_CTRL_TXDIR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TXDIR_SHIFT)) & LPUART_CTRL_TXDIR_MASK) #define LPUART_CTRL_R9T8_MASK (0x40000000U) #define LPUART_CTRL_R9T8_SHIFT (30U) @@ -13800,8 +22199,10 @@ typedef struct { #define LPUART_CTRL_R8T9_MASK (0x80000000U) #define LPUART_CTRL_R8T9_SHIFT (31U) #define LPUART_CTRL_R8T9(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_R8T9_SHIFT)) & LPUART_CTRL_R8T9_MASK) +/*! @} */ /*! @name DATA - LPUART Data Register */ +/*! @{ */ #define LPUART_DATA_R0T0_MASK (0x1U) #define LPUART_DATA_R0T0_SHIFT (0U) #define LPUART_DATA_R0T0(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R0T0_SHIFT)) & LPUART_DATA_R0T0_MASK) @@ -13834,99 +22235,231 @@ typedef struct { #define LPUART_DATA_R9T9(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R9T9_SHIFT)) & LPUART_DATA_R9T9_MASK) #define LPUART_DATA_IDLINE_MASK (0x800U) #define LPUART_DATA_IDLINE_SHIFT (11U) +/*! IDLINE - Idle Line + * 0b0..Receiver was not idle before receiving this character. + * 0b1..Receiver was idle before receiving this character. + */ #define LPUART_DATA_IDLINE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_IDLINE_SHIFT)) & LPUART_DATA_IDLINE_MASK) #define LPUART_DATA_RXEMPT_MASK (0x1000U) #define LPUART_DATA_RXEMPT_SHIFT (12U) +/*! RXEMPT - Receive Buffer Empty + * 0b0..Receive buffer contains valid data. + * 0b1..Receive buffer is empty, data returned on read is not valid. + */ #define LPUART_DATA_RXEMPT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_RXEMPT_SHIFT)) & LPUART_DATA_RXEMPT_MASK) #define LPUART_DATA_FRETSC_MASK (0x2000U) #define LPUART_DATA_FRETSC_SHIFT (13U) +/*! FRETSC - Frame Error / Transmit Special Character + * 0b0..The dataword was received without a frame error on read, or transmit a normal character on write. + * 0b1..The dataword was received with a frame error, or transmit an idle or break character on transmit. + */ #define LPUART_DATA_FRETSC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_FRETSC_SHIFT)) & LPUART_DATA_FRETSC_MASK) #define LPUART_DATA_PARITYE_MASK (0x4000U) #define LPUART_DATA_PARITYE_SHIFT (14U) +/*! PARITYE - PARITYE + * 0b0..The dataword was received without a parity error. + * 0b1..The dataword was received with a parity error. + */ #define LPUART_DATA_PARITYE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_PARITYE_SHIFT)) & LPUART_DATA_PARITYE_MASK) #define LPUART_DATA_NOISY_MASK (0x8000U) #define LPUART_DATA_NOISY_SHIFT (15U) +/*! NOISY - NOISY + * 0b0..The dataword was received without noise. + * 0b1..The data was received with noise. + */ #define LPUART_DATA_NOISY(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_NOISY_SHIFT)) & LPUART_DATA_NOISY_MASK) +/*! @} */ /*! @name MATCH - LPUART Match Address Register */ +/*! @{ */ #define LPUART_MATCH_MA1_MASK (0x3FFU) #define LPUART_MATCH_MA1_SHIFT (0U) #define LPUART_MATCH_MA1(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MATCH_MA1_SHIFT)) & LPUART_MATCH_MA1_MASK) #define LPUART_MATCH_MA2_MASK (0x3FF0000U) #define LPUART_MATCH_MA2_SHIFT (16U) #define LPUART_MATCH_MA2(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MATCH_MA2_SHIFT)) & LPUART_MATCH_MA2_MASK) +/*! @} */ /*! @name MODIR - LPUART Modem IrDA Register */ +/*! @{ */ #define LPUART_MODIR_TXCTSE_MASK (0x1U) #define LPUART_MODIR_TXCTSE_SHIFT (0U) +/*! TXCTSE - Transmitter clear-to-send enable + * 0b0..CTS has no effect on the transmitter. + * 0b1..Enables clear-to-send operation. The transmitter checks the state of CTS each time it is ready to send a character. If CTS is asserted, the character is sent. If CTS is deasserted, the signal TXD remains in the mark state and transmission is delayed until CTS is asserted. Changes in CTS as a character is being sent do not affect its transmission. + */ #define LPUART_MODIR_TXCTSE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSE_SHIFT)) & LPUART_MODIR_TXCTSE_MASK) #define LPUART_MODIR_TXRTSE_MASK (0x2U) #define LPUART_MODIR_TXRTSE_SHIFT (1U) +/*! TXRTSE - Transmitter request-to-send enable + * 0b0..The transmitter has no effect on RTS. + * 0b1..When a character is placed into an empty transmitter data buffer , RTS asserts one bit time before the start bit is transmitted. RTS deasserts one bit time after all characters in the transmitter data buffer and shift register are completely sent, including the last stop bit. + */ #define LPUART_MODIR_TXRTSE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXRTSE_SHIFT)) & LPUART_MODIR_TXRTSE_MASK) #define LPUART_MODIR_TXRTSPOL_MASK (0x4U) #define LPUART_MODIR_TXRTSPOL_SHIFT (2U) +/*! TXRTSPOL - Transmitter request-to-send polarity + * 0b0..Transmitter RTS is active low. + * 0b1..Transmitter RTS is active high. + */ #define LPUART_MODIR_TXRTSPOL(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXRTSPOL_SHIFT)) & LPUART_MODIR_TXRTSPOL_MASK) #define LPUART_MODIR_RXRTSE_MASK (0x8U) #define LPUART_MODIR_RXRTSE_SHIFT (3U) +/*! RXRTSE - Receiver request-to-send enable + * 0b0..The receiver has no effect on RTS. + * 0b1..RTS is deasserted if the receiver data register is full or a start bit has been detected that would cause the receiver data register to become full. RTS is asserted if the receiver data register is not full and has not detected a start bit that would cause the receiver data register to become full. + */ #define LPUART_MODIR_RXRTSE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_RXRTSE_SHIFT)) & LPUART_MODIR_RXRTSE_MASK) #define LPUART_MODIR_TXCTSC_MASK (0x10U) #define LPUART_MODIR_TXCTSC_SHIFT (4U) +/*! TXCTSC - Transmit CTS Configuration + * 0b0..CTS input is sampled at the start of each character. + * 0b1..CTS input is sampled when the transmitter is idle. + */ #define LPUART_MODIR_TXCTSC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSC_SHIFT)) & LPUART_MODIR_TXCTSC_MASK) #define LPUART_MODIR_TXCTSSRC_MASK (0x20U) #define LPUART_MODIR_TXCTSSRC_SHIFT (5U) +/*! TXCTSSRC - Transmit CTS Source + * 0b0..CTS input is the CTS_B pin. + * 0b1..CTS input is the inverted Receiver Match result. + */ #define LPUART_MODIR_TXCTSSRC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSSRC_SHIFT)) & LPUART_MODIR_TXCTSSRC_MASK) #define LPUART_MODIR_RTSWATER_MASK (0x300U) #define LPUART_MODIR_RTSWATER_SHIFT (8U) #define LPUART_MODIR_RTSWATER(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_RTSWATER_SHIFT)) & LPUART_MODIR_RTSWATER_MASK) #define LPUART_MODIR_TNP_MASK (0x30000U) #define LPUART_MODIR_TNP_SHIFT (16U) +/*! TNP - Transmitter narrow pulse + * 0b00..1/OSR. + * 0b01..2/OSR. + * 0b10..3/OSR. + * 0b11..4/OSR. + */ #define LPUART_MODIR_TNP(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TNP_SHIFT)) & LPUART_MODIR_TNP_MASK) #define LPUART_MODIR_IREN_MASK (0x40000U) #define LPUART_MODIR_IREN_SHIFT (18U) +/*! IREN - Infrared enable + * 0b0..IR disabled. + * 0b1..IR enabled. + */ #define LPUART_MODIR_IREN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_IREN_SHIFT)) & LPUART_MODIR_IREN_MASK) +/*! @} */ /*! @name FIFO - LPUART FIFO Register */ +/*! @{ */ #define LPUART_FIFO_RXFIFOSIZE_MASK (0x7U) #define LPUART_FIFO_RXFIFOSIZE_SHIFT (0U) +/*! RXFIFOSIZE - Receive FIFO Buffer Depth + * 0b000..Receive FIFO/Buffer depth = 1 dataword. + * 0b001..Receive FIFO/Buffer depth = 4 datawords. + * 0b010..Receive FIFO/Buffer depth = 8 datawords. + * 0b011..Receive FIFO/Buffer depth = 16 datawords. + * 0b100..Receive FIFO/Buffer depth = 32 datawords. + * 0b101..Receive FIFO/Buffer depth = 64 datawords. + * 0b110..Receive FIFO/Buffer depth = 128 datawords. + * 0b111..Receive FIFO/Buffer depth = 256 datawords. + */ #define LPUART_FIFO_RXFIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXFIFOSIZE_SHIFT)) & LPUART_FIFO_RXFIFOSIZE_MASK) #define LPUART_FIFO_RXFE_MASK (0x8U) #define LPUART_FIFO_RXFE_SHIFT (3U) +/*! RXFE - Receive FIFO Enable + * 0b0..Receive FIFO is not enabled. Buffer is depth 1. + * 0b1..Receive FIFO is enabled. Buffer is depth indicted by RXFIFOSIZE. + */ #define LPUART_FIFO_RXFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXFE_SHIFT)) & LPUART_FIFO_RXFE_MASK) #define LPUART_FIFO_TXFIFOSIZE_MASK (0x70U) #define LPUART_FIFO_TXFIFOSIZE_SHIFT (4U) +/*! TXFIFOSIZE - Transmit FIFO Buffer Depth + * 0b000..Transmit FIFO/Buffer depth = 1 dataword. + * 0b001..Transmit FIFO/Buffer depth = 4 datawords. + * 0b010..Transmit FIFO/Buffer depth = 8 datawords. + * 0b011..Transmit FIFO/Buffer depth = 16 datawords. + * 0b100..Transmit FIFO/Buffer depth = 32 datawords. + * 0b101..Transmit FIFO/Buffer depth = 64 datawords. + * 0b110..Transmit FIFO/Buffer depth = 128 datawords. + * 0b111..Transmit FIFO/Buffer depth = 256 datawords + */ #define LPUART_FIFO_TXFIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXFIFOSIZE_SHIFT)) & LPUART_FIFO_TXFIFOSIZE_MASK) #define LPUART_FIFO_TXFE_MASK (0x80U) #define LPUART_FIFO_TXFE_SHIFT (7U) +/*! TXFE - Transmit FIFO Enable + * 0b0..Transmit FIFO is not enabled. Buffer is depth 1. + * 0b1..Transmit FIFO is enabled. Buffer is depth indicated by TXFIFOSIZE. + */ #define LPUART_FIFO_TXFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXFE_SHIFT)) & LPUART_FIFO_TXFE_MASK) #define LPUART_FIFO_RXUFE_MASK (0x100U) #define LPUART_FIFO_RXUFE_SHIFT (8U) +/*! RXUFE - Receive FIFO Underflow Interrupt Enable + * 0b0..RXUF flag does not generate an interrupt to the host. + * 0b1..RXUF flag generates an interrupt to the host. + */ #define LPUART_FIFO_RXUFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXUFE_SHIFT)) & LPUART_FIFO_RXUFE_MASK) #define LPUART_FIFO_TXOFE_MASK (0x200U) #define LPUART_FIFO_TXOFE_SHIFT (9U) +/*! TXOFE - Transmit FIFO Overflow Interrupt Enable + * 0b0..TXOF flag does not generate an interrupt to the host. + * 0b1..TXOF flag generates an interrupt to the host. + */ #define LPUART_FIFO_TXOFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXOFE_SHIFT)) & LPUART_FIFO_TXOFE_MASK) #define LPUART_FIFO_RXIDEN_MASK (0x1C00U) #define LPUART_FIFO_RXIDEN_SHIFT (10U) +/*! RXIDEN - Receiver Idle Empty Enable + * 0b000..Disable RDRF assertion due to partially filled FIFO when receiver is idle. + * 0b001..Enable RDRF assertion due to partially filled FIFO when receiver is idle for 1 character. + * 0b010..Enable RDRF assertion due to partially filled FIFO when receiver is idle for 2 characters. + * 0b011..Enable RDRF assertion due to partially filled FIFO when receiver is idle for 4 characters. + * 0b100..Enable RDRF assertion due to partially filled FIFO when receiver is idle for 8 characters. + * 0b101..Enable RDRF assertion due to partially filled FIFO when receiver is idle for 16 characters. + * 0b110..Enable RDRF assertion due to partially filled FIFO when receiver is idle for 32 characters. + * 0b111..Enable RDRF assertion due to partially filled FIFO when receiver is idle for 64 characters. + */ #define LPUART_FIFO_RXIDEN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXIDEN_SHIFT)) & LPUART_FIFO_RXIDEN_MASK) #define LPUART_FIFO_RXFLUSH_MASK (0x4000U) #define LPUART_FIFO_RXFLUSH_SHIFT (14U) +/*! RXFLUSH - Receive FIFO/Buffer Flush + * 0b0..No flush operation occurs. + * 0b1..All data in the receive FIFO/buffer is cleared out. + */ #define LPUART_FIFO_RXFLUSH(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXFLUSH_SHIFT)) & LPUART_FIFO_RXFLUSH_MASK) #define LPUART_FIFO_TXFLUSH_MASK (0x8000U) #define LPUART_FIFO_TXFLUSH_SHIFT (15U) +/*! TXFLUSH - Transmit FIFO/Buffer Flush + * 0b0..No flush operation occurs. + * 0b1..All data in the transmit FIFO/Buffer is cleared out. + */ #define LPUART_FIFO_TXFLUSH(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXFLUSH_SHIFT)) & LPUART_FIFO_TXFLUSH_MASK) #define LPUART_FIFO_RXUF_MASK (0x10000U) #define LPUART_FIFO_RXUF_SHIFT (16U) +/*! RXUF - Receiver Buffer Underflow Flag + * 0b0..No receive buffer underflow has occurred since the last time the flag was cleared. + * 0b1..At least one receive buffer underflow has occurred since the last time the flag was cleared. + */ #define LPUART_FIFO_RXUF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXUF_SHIFT)) & LPUART_FIFO_RXUF_MASK) #define LPUART_FIFO_TXOF_MASK (0x20000U) #define LPUART_FIFO_TXOF_SHIFT (17U) +/*! TXOF - Transmitter Buffer Overflow Flag + * 0b0..No transmit buffer overflow has occurred since the last time the flag was cleared. + * 0b1..At least one transmit buffer overflow has occurred since the last time the flag was cleared. + */ #define LPUART_FIFO_TXOF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXOF_SHIFT)) & LPUART_FIFO_TXOF_MASK) #define LPUART_FIFO_RXEMPT_MASK (0x400000U) #define LPUART_FIFO_RXEMPT_SHIFT (22U) +/*! RXEMPT - Receive Buffer/FIFO Empty + * 0b0..Receive buffer is not empty. + * 0b1..Receive buffer is empty. + */ #define LPUART_FIFO_RXEMPT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXEMPT_SHIFT)) & LPUART_FIFO_RXEMPT_MASK) #define LPUART_FIFO_TXEMPT_MASK (0x800000U) #define LPUART_FIFO_TXEMPT_SHIFT (23U) +/*! TXEMPT - Transmit Buffer/FIFO Empty + * 0b0..Transmit buffer is not empty. + * 0b1..Transmit buffer is empty. + */ #define LPUART_FIFO_TXEMPT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXEMPT_SHIFT)) & LPUART_FIFO_TXEMPT_MASK) +/*! @} */ /*! @name WATER - LPUART Watermark Register */ +/*! @{ */ #define LPUART_WATER_TXWATER_MASK (0x3U) #define LPUART_WATER_TXWATER_SHIFT (0U) #define LPUART_WATER_TXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_TXWATER_SHIFT)) & LPUART_WATER_TXWATER_MASK) @@ -13939,6 +22472,7 @@ typedef struct { #define LPUART_WATER_RXCOUNT_MASK (0x7000000U) #define LPUART_WATER_RXCOUNT_SHIFT (24U) #define LPUART_WATER_RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_RXCOUNT_SHIFT)) & LPUART_WATER_RXCOUNT_MASK) +/*! @} */ /*! @@ -14114,6 +22648,7 @@ typedef struct { */ /*! @name CTRL - OTP Controller Control Register */ +/*! @{ */ #define OCOTP_CTRL_ADDR_MASK (0x3FU) #define OCOTP_CTRL_ADDR_SHIFT (0U) #define OCOTP_CTRL_ADDR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_ADDR_SHIFT)) & OCOTP_CTRL_ADDR_MASK) @@ -14129,8 +22664,10 @@ typedef struct { #define OCOTP_CTRL_WR_UNLOCK_MASK (0xFFFF0000U) #define OCOTP_CTRL_WR_UNLOCK_SHIFT (16U) #define OCOTP_CTRL_WR_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_WR_UNLOCK_SHIFT)) & OCOTP_CTRL_WR_UNLOCK_MASK) +/*! @} */ /*! @name CTRL_SET - OTP Controller Control Register */ +/*! @{ */ #define OCOTP_CTRL_SET_ADDR_MASK (0x3FU) #define OCOTP_CTRL_SET_ADDR_SHIFT (0U) #define OCOTP_CTRL_SET_ADDR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_SET_ADDR_SHIFT)) & OCOTP_CTRL_SET_ADDR_MASK) @@ -14146,8 +22683,10 @@ typedef struct { #define OCOTP_CTRL_SET_WR_UNLOCK_MASK (0xFFFF0000U) #define OCOTP_CTRL_SET_WR_UNLOCK_SHIFT (16U) #define OCOTP_CTRL_SET_WR_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_SET_WR_UNLOCK_SHIFT)) & OCOTP_CTRL_SET_WR_UNLOCK_MASK) +/*! @} */ /*! @name CTRL_CLR - OTP Controller Control Register */ +/*! @{ */ #define OCOTP_CTRL_CLR_ADDR_MASK (0x3FU) #define OCOTP_CTRL_CLR_ADDR_SHIFT (0U) #define OCOTP_CTRL_CLR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CLR_ADDR_SHIFT)) & OCOTP_CTRL_CLR_ADDR_MASK) @@ -14163,8 +22702,10 @@ typedef struct { #define OCOTP_CTRL_CLR_WR_UNLOCK_MASK (0xFFFF0000U) #define OCOTP_CTRL_CLR_WR_UNLOCK_SHIFT (16U) #define OCOTP_CTRL_CLR_WR_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CLR_WR_UNLOCK_SHIFT)) & OCOTP_CTRL_CLR_WR_UNLOCK_MASK) +/*! @} */ /*! @name CTRL_TOG - OTP Controller Control Register */ +/*! @{ */ #define OCOTP_CTRL_TOG_ADDR_MASK (0x3FU) #define OCOTP_CTRL_TOG_ADDR_SHIFT (0U) #define OCOTP_CTRL_TOG_ADDR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_TOG_ADDR_SHIFT)) & OCOTP_CTRL_TOG_ADDR_MASK) @@ -14180,8 +22721,10 @@ typedef struct { #define OCOTP_CTRL_TOG_WR_UNLOCK_MASK (0xFFFF0000U) #define OCOTP_CTRL_TOG_WR_UNLOCK_SHIFT (16U) #define OCOTP_CTRL_TOG_WR_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_TOG_WR_UNLOCK_SHIFT)) & OCOTP_CTRL_TOG_WR_UNLOCK_MASK) +/*! @} */ /*! @name TIMING - OTP Controller Timing Register */ +/*! @{ */ #define OCOTP_TIMING_STROBE_PROG_MASK (0xFFFU) #define OCOTP_TIMING_STROBE_PROG_SHIFT (0U) #define OCOTP_TIMING_STROBE_PROG(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_TIMING_STROBE_PROG_SHIFT)) & OCOTP_TIMING_STROBE_PROG_MASK) @@ -14194,23 +22737,31 @@ typedef struct { #define OCOTP_TIMING_WAIT_MASK (0xFC00000U) #define OCOTP_TIMING_WAIT_SHIFT (22U) #define OCOTP_TIMING_WAIT(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_TIMING_WAIT_SHIFT)) & OCOTP_TIMING_WAIT_MASK) +/*! @} */ /*! @name DATA - OTP Controller Write Data Register */ +/*! @{ */ #define OCOTP_DATA_DATA_MASK (0xFFFFFFFFU) #define OCOTP_DATA_DATA_SHIFT (0U) #define OCOTP_DATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_DATA_DATA_SHIFT)) & OCOTP_DATA_DATA_MASK) +/*! @} */ /*! @name READ_CTRL - OTP Controller Write Data Register */ +/*! @{ */ #define OCOTP_READ_CTRL_READ_FUSE_MASK (0x1U) #define OCOTP_READ_CTRL_READ_FUSE_SHIFT (0U) #define OCOTP_READ_CTRL_READ_FUSE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_READ_CTRL_READ_FUSE_SHIFT)) & OCOTP_READ_CTRL_READ_FUSE_MASK) +/*! @} */ /*! @name READ_FUSE_DATA - OTP Controller Read Data Register */ +/*! @{ */ #define OCOTP_READ_FUSE_DATA_DATA_MASK (0xFFFFFFFFU) #define OCOTP_READ_FUSE_DATA_DATA_SHIFT (0U) #define OCOTP_READ_FUSE_DATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_READ_FUSE_DATA_DATA_SHIFT)) & OCOTP_READ_FUSE_DATA_DATA_MASK) +/*! @} */ /*! @name SW_STICKY - Sticky bit Register */ +/*! @{ */ #define OCOTP_SW_STICKY_BLOCK_DTCP_KEY_MASK (0x1U) #define OCOTP_SW_STICKY_BLOCK_DTCP_KEY_SHIFT (0U) #define OCOTP_SW_STICKY_BLOCK_DTCP_KEY(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_STICKY_BLOCK_DTCP_KEY_SHIFT)) & OCOTP_SW_STICKY_BLOCK_DTCP_KEY_MASK) @@ -14226,8 +22777,10 @@ typedef struct { #define OCOTP_SW_STICKY_JTAG_BLOCK_RELEASE_MASK (0x10U) #define OCOTP_SW_STICKY_JTAG_BLOCK_RELEASE_SHIFT (4U) #define OCOTP_SW_STICKY_JTAG_BLOCK_RELEASE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_STICKY_JTAG_BLOCK_RELEASE_SHIFT)) & OCOTP_SW_STICKY_JTAG_BLOCK_RELEASE_MASK) +/*! @} */ /*! @name SCS - Software Controllable Signals Register */ +/*! @{ */ #define OCOTP_SCS_HAB_JDE_MASK (0x1U) #define OCOTP_SCS_HAB_JDE_SHIFT (0U) #define OCOTP_SCS_HAB_JDE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_HAB_JDE_SHIFT)) & OCOTP_SCS_HAB_JDE_MASK) @@ -14237,8 +22790,10 @@ typedef struct { #define OCOTP_SCS_LOCK_MASK (0x80000000U) #define OCOTP_SCS_LOCK_SHIFT (31U) #define OCOTP_SCS_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_LOCK_SHIFT)) & OCOTP_SCS_LOCK_MASK) +/*! @} */ /*! @name SCS_SET - Software Controllable Signals Register */ +/*! @{ */ #define OCOTP_SCS_SET_HAB_JDE_MASK (0x1U) #define OCOTP_SCS_SET_HAB_JDE_SHIFT (0U) #define OCOTP_SCS_SET_HAB_JDE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_SET_HAB_JDE_SHIFT)) & OCOTP_SCS_SET_HAB_JDE_MASK) @@ -14248,8 +22803,10 @@ typedef struct { #define OCOTP_SCS_SET_LOCK_MASK (0x80000000U) #define OCOTP_SCS_SET_LOCK_SHIFT (31U) #define OCOTP_SCS_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_SET_LOCK_SHIFT)) & OCOTP_SCS_SET_LOCK_MASK) +/*! @} */ /*! @name SCS_CLR - Software Controllable Signals Register */ +/*! @{ */ #define OCOTP_SCS_CLR_HAB_JDE_MASK (0x1U) #define OCOTP_SCS_CLR_HAB_JDE_SHIFT (0U) #define OCOTP_SCS_CLR_HAB_JDE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_CLR_HAB_JDE_SHIFT)) & OCOTP_SCS_CLR_HAB_JDE_MASK) @@ -14259,8 +22816,10 @@ typedef struct { #define OCOTP_SCS_CLR_LOCK_MASK (0x80000000U) #define OCOTP_SCS_CLR_LOCK_SHIFT (31U) #define OCOTP_SCS_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_CLR_LOCK_SHIFT)) & OCOTP_SCS_CLR_LOCK_MASK) +/*! @} */ /*! @name SCS_TOG - Software Controllable Signals Register */ +/*! @{ */ #define OCOTP_SCS_TOG_HAB_JDE_MASK (0x1U) #define OCOTP_SCS_TOG_HAB_JDE_SHIFT (0U) #define OCOTP_SCS_TOG_HAB_JDE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_TOG_HAB_JDE_SHIFT)) & OCOTP_SCS_TOG_HAB_JDE_MASK) @@ -14270,8 +22829,10 @@ typedef struct { #define OCOTP_SCS_TOG_LOCK_MASK (0x80000000U) #define OCOTP_SCS_TOG_LOCK_SHIFT (31U) #define OCOTP_SCS_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_TOG_LOCK_SHIFT)) & OCOTP_SCS_TOG_LOCK_MASK) +/*! @} */ /*! @name VERSION - OTP Controller Version Register */ +/*! @{ */ #define OCOTP_VERSION_STEP_MASK (0xFFFFU) #define OCOTP_VERSION_STEP_SHIFT (0U) #define OCOTP_VERSION_STEP(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_VERSION_STEP_SHIFT)) & OCOTP_VERSION_STEP_MASK) @@ -14281,8 +22842,10 @@ typedef struct { #define OCOTP_VERSION_MAJOR_MASK (0xFF000000U) #define OCOTP_VERSION_MAJOR_SHIFT (24U) #define OCOTP_VERSION_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_VERSION_MAJOR_SHIFT)) & OCOTP_VERSION_MAJOR_MASK) +/*! @} */ /*! @name TIMING2 - OTP Controller Timing Register 2 */ +/*! @{ */ #define OCOTP_TIMING2_RELAX_PROG_MASK (0xFFFU) #define OCOTP_TIMING2_RELAX_PROG_SHIFT (0U) #define OCOTP_TIMING2_RELAX_PROG(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_TIMING2_RELAX_PROG_SHIFT)) & OCOTP_TIMING2_RELAX_PROG_MASK) @@ -14292,8 +22855,10 @@ typedef struct { #define OCOTP_TIMING2_RELAX1_MASK (0x1FC00000U) #define OCOTP_TIMING2_RELAX1_SHIFT (22U) #define OCOTP_TIMING2_RELAX1(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_TIMING2_RELAX1_SHIFT)) & OCOTP_TIMING2_RELAX1_MASK) +/*! @} */ /*! @name LOCK - Value of OTP Bank0 Word0 (Lock controls) */ +/*! @{ */ #define OCOTP_LOCK_TESTER_MASK (0x3U) #define OCOTP_LOCK_TESTER_SHIFT (0U) #define OCOTP_LOCK_TESTER(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_TESTER_SHIFT)) & OCOTP_LOCK_TESTER_MASK) @@ -14315,9 +22880,6 @@ typedef struct { #define OCOTP_LOCK_GP2_MASK (0x3000U) #define OCOTP_LOCK_GP2_SHIFT (12U) #define OCOTP_LOCK_GP2(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_GP2_SHIFT)) & OCOTP_LOCK_GP2_MASK) -#define OCOTP_LOCK_SRK_MASK (0x4000U) -#define OCOTP_LOCK_SRK_SHIFT (14U) -#define OCOTP_LOCK_SRK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_SRK_SHIFT)) & OCOTP_LOCK_SRK_MASK) #define OCOTP_LOCK_OTPMK_MSB_MASK (0x8000U) #define OCOTP_LOCK_OTPMK_MSB_SHIFT (15U) #define OCOTP_LOCK_OTPMK_MSB(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_OTPMK_MSB_SHIFT)) & OCOTP_LOCK_OTPMK_MSB_MASK) @@ -14348,196 +22910,273 @@ typedef struct { #define OCOTP_LOCK_FIELD_RETURN_MASK (0xF0000000U) #define OCOTP_LOCK_FIELD_RETURN_SHIFT (28U) #define OCOTP_LOCK_FIELD_RETURN(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_FIELD_RETURN_SHIFT)) & OCOTP_LOCK_FIELD_RETURN_MASK) +/*! @} */ /*! @name CFG0 - Value of OTP Bank0 Word1 (Configuration and Manufacturing Info.) */ +/*! @{ */ #define OCOTP_CFG0_BITS_MASK (0xFFFFFFFFU) #define OCOTP_CFG0_BITS_SHIFT (0U) #define OCOTP_CFG0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CFG0_BITS_SHIFT)) & OCOTP_CFG0_BITS_MASK) +/*! @} */ /*! @name CFG1 - Value of OTP Bank0 Word2 (Configuration and Manufacturing Info.) */ +/*! @{ */ #define OCOTP_CFG1_BITS_MASK (0xFFFFFFFFU) #define OCOTP_CFG1_BITS_SHIFT (0U) #define OCOTP_CFG1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CFG1_BITS_SHIFT)) & OCOTP_CFG1_BITS_MASK) +/*! @} */ /*! @name CFG2 - Value of OTP Bank0 Word3 (Configuration and Manufacturing Info.) */ +/*! @{ */ #define OCOTP_CFG2_BITS_MASK (0xFFFFFFFFU) #define OCOTP_CFG2_BITS_SHIFT (0U) #define OCOTP_CFG2_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CFG2_BITS_SHIFT)) & OCOTP_CFG2_BITS_MASK) +/*! @} */ /*! @name CFG3 - Value of OTP Bank0 Word4 (Configuration and Manufacturing Info.) */ +/*! @{ */ #define OCOTP_CFG3_BITS_MASK (0xFFFFFFFFU) #define OCOTP_CFG3_BITS_SHIFT (0U) #define OCOTP_CFG3_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CFG3_BITS_SHIFT)) & OCOTP_CFG3_BITS_MASK) +/*! @} */ /*! @name CFG4 - Value of OTP Bank0 Word5 (Configuration and Manufacturing Info.) */ +/*! @{ */ #define OCOTP_CFG4_BITS_MASK (0xFFFFFFFFU) #define OCOTP_CFG4_BITS_SHIFT (0U) #define OCOTP_CFG4_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CFG4_BITS_SHIFT)) & OCOTP_CFG4_BITS_MASK) +/*! @} */ /*! @name CFG5 - Value of OTP Bank0 Word6 (Configuration and Manufacturing Info.) */ +/*! @{ */ #define OCOTP_CFG5_BITS_MASK (0xFFFFFFFFU) #define OCOTP_CFG5_BITS_SHIFT (0U) #define OCOTP_CFG5_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CFG5_BITS_SHIFT)) & OCOTP_CFG5_BITS_MASK) +/*! @} */ /*! @name CFG6 - Value of OTP Bank0 Word7 (Configuration and Manufacturing Info.) */ +/*! @{ */ #define OCOTP_CFG6_BITS_MASK (0xFFFFFFFFU) #define OCOTP_CFG6_BITS_SHIFT (0U) #define OCOTP_CFG6_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CFG6_BITS_SHIFT)) & OCOTP_CFG6_BITS_MASK) +/*! @} */ /*! @name MEM0 - Value of OTP Bank1 Word0 (Memory Related Info.) */ +/*! @{ */ #define OCOTP_MEM0_BITS_MASK (0xFFFFFFFFU) #define OCOTP_MEM0_BITS_SHIFT (0U) #define OCOTP_MEM0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MEM0_BITS_SHIFT)) & OCOTP_MEM0_BITS_MASK) +/*! @} */ /*! @name MEM1 - Value of OTP Bank1 Word1 (Memory Related Info.) */ +/*! @{ */ #define OCOTP_MEM1_BITS_MASK (0xFFFFFFFFU) #define OCOTP_MEM1_BITS_SHIFT (0U) #define OCOTP_MEM1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MEM1_BITS_SHIFT)) & OCOTP_MEM1_BITS_MASK) +/*! @} */ /*! @name MEM2 - Value of OTP Bank1 Word2 (Memory Related Info.) */ +/*! @{ */ #define OCOTP_MEM2_BITS_MASK (0xFFFFFFFFU) #define OCOTP_MEM2_BITS_SHIFT (0U) #define OCOTP_MEM2_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MEM2_BITS_SHIFT)) & OCOTP_MEM2_BITS_MASK) +/*! @} */ /*! @name MEM3 - Value of OTP Bank1 Word3 (Memory Related Info.) */ +/*! @{ */ #define OCOTP_MEM3_BITS_MASK (0xFFFFFFFFU) #define OCOTP_MEM3_BITS_SHIFT (0U) #define OCOTP_MEM3_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MEM3_BITS_SHIFT)) & OCOTP_MEM3_BITS_MASK) +/*! @} */ /*! @name MEM4 - Value of OTP Bank1 Word4 (Memory Related Info.) */ +/*! @{ */ #define OCOTP_MEM4_BITS_MASK (0xFFFFFFFFU) #define OCOTP_MEM4_BITS_SHIFT (0U) #define OCOTP_MEM4_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MEM4_BITS_SHIFT)) & OCOTP_MEM4_BITS_MASK) +/*! @} */ /*! @name ANA0 - Value of OTP Bank1 Word5 (Analog Info.) */ +/*! @{ */ #define OCOTP_ANA0_BITS_MASK (0xFFFFFFFFU) #define OCOTP_ANA0_BITS_SHIFT (0U) #define OCOTP_ANA0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_ANA0_BITS_SHIFT)) & OCOTP_ANA0_BITS_MASK) +/*! @} */ /*! @name ANA1 - Value of OTP Bank1 Word6 (Analog Info.) */ +/*! @{ */ #define OCOTP_ANA1_BITS_MASK (0xFFFFFFFFU) #define OCOTP_ANA1_BITS_SHIFT (0U) #define OCOTP_ANA1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_ANA1_BITS_SHIFT)) & OCOTP_ANA1_BITS_MASK) +/*! @} */ /*! @name ANA2 - Value of OTP Bank1 Word7 (Analog Info.) */ +/*! @{ */ #define OCOTP_ANA2_BITS_MASK (0xFFFFFFFFU) #define OCOTP_ANA2_BITS_SHIFT (0U) #define OCOTP_ANA2_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_ANA2_BITS_SHIFT)) & OCOTP_ANA2_BITS_MASK) +/*! @} */ /*! @name SRK0 - Shadow Register for OTP Bank3 Word0 (SRK Hash) */ +/*! @{ */ #define OCOTP_SRK0_BITS_MASK (0xFFFFFFFFU) #define OCOTP_SRK0_BITS_SHIFT (0U) #define OCOTP_SRK0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK0_BITS_SHIFT)) & OCOTP_SRK0_BITS_MASK) +/*! @} */ /*! @name SRK1 - Shadow Register for OTP Bank3 Word1 (SRK Hash) */ +/*! @{ */ #define OCOTP_SRK1_BITS_MASK (0xFFFFFFFFU) #define OCOTP_SRK1_BITS_SHIFT (0U) #define OCOTP_SRK1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK1_BITS_SHIFT)) & OCOTP_SRK1_BITS_MASK) +/*! @} */ /*! @name SRK2 - Shadow Register for OTP Bank3 Word2 (SRK Hash) */ +/*! @{ */ #define OCOTP_SRK2_BITS_MASK (0xFFFFFFFFU) #define OCOTP_SRK2_BITS_SHIFT (0U) #define OCOTP_SRK2_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK2_BITS_SHIFT)) & OCOTP_SRK2_BITS_MASK) +/*! @} */ /*! @name SRK3 - Shadow Register for OTP Bank3 Word3 (SRK Hash) */ +/*! @{ */ #define OCOTP_SRK3_BITS_MASK (0xFFFFFFFFU) #define OCOTP_SRK3_BITS_SHIFT (0U) #define OCOTP_SRK3_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK3_BITS_SHIFT)) & OCOTP_SRK3_BITS_MASK) +/*! @} */ /*! @name SRK4 - Shadow Register for OTP Bank3 Word4 (SRK Hash) */ +/*! @{ */ #define OCOTP_SRK4_BITS_MASK (0xFFFFFFFFU) #define OCOTP_SRK4_BITS_SHIFT (0U) #define OCOTP_SRK4_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK4_BITS_SHIFT)) & OCOTP_SRK4_BITS_MASK) +/*! @} */ /*! @name SRK5 - Shadow Register for OTP Bank3 Word5 (SRK Hash) */ +/*! @{ */ #define OCOTP_SRK5_BITS_MASK (0xFFFFFFFFU) #define OCOTP_SRK5_BITS_SHIFT (0U) #define OCOTP_SRK5_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK5_BITS_SHIFT)) & OCOTP_SRK5_BITS_MASK) +/*! @} */ /*! @name SRK6 - Shadow Register for OTP Bank3 Word6 (SRK Hash) */ +/*! @{ */ #define OCOTP_SRK6_BITS_MASK (0xFFFFFFFFU) #define OCOTP_SRK6_BITS_SHIFT (0U) #define OCOTP_SRK6_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK6_BITS_SHIFT)) & OCOTP_SRK6_BITS_MASK) +/*! @} */ /*! @name SRK7 - Shadow Register for OTP Bank3 Word7 (SRK Hash) */ +/*! @{ */ #define OCOTP_SRK7_BITS_MASK (0xFFFFFFFFU) #define OCOTP_SRK7_BITS_SHIFT (0U) #define OCOTP_SRK7_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK7_BITS_SHIFT)) & OCOTP_SRK7_BITS_MASK) +/*! @} */ /*! @name SJC_RESP0 - Value of OTP Bank4 Word0 (Secure JTAG Response Field) */ +/*! @{ */ #define OCOTP_SJC_RESP0_BITS_MASK (0xFFFFFFFFU) #define OCOTP_SJC_RESP0_BITS_SHIFT (0U) #define OCOTP_SJC_RESP0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SJC_RESP0_BITS_SHIFT)) & OCOTP_SJC_RESP0_BITS_MASK) +/*! @} */ /*! @name SJC_RESP1 - Value of OTP Bank4 Word1 (Secure JTAG Response Field) */ +/*! @{ */ #define OCOTP_SJC_RESP1_BITS_MASK (0xFFFFFFFFU) #define OCOTP_SJC_RESP1_BITS_SHIFT (0U) #define OCOTP_SJC_RESP1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SJC_RESP1_BITS_SHIFT)) & OCOTP_SJC_RESP1_BITS_MASK) +/*! @} */ /*! @name MAC0 - Value of OTP Bank4 Word2 (MAC Address) */ +/*! @{ */ #define OCOTP_MAC0_BITS_MASK (0xFFFFFFFFU) #define OCOTP_MAC0_BITS_SHIFT (0U) #define OCOTP_MAC0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MAC0_BITS_SHIFT)) & OCOTP_MAC0_BITS_MASK) +/*! @} */ /*! @name MAC1 - Value of OTP Bank4 Word3 (MAC Address) */ +/*! @{ */ #define OCOTP_MAC1_BITS_MASK (0xFFFFFFFFU) #define OCOTP_MAC1_BITS_SHIFT (0U) #define OCOTP_MAC1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MAC1_BITS_SHIFT)) & OCOTP_MAC1_BITS_MASK) +/*! @} */ /*! @name GP3 - Value of OTP Bank4 Word4 (MAC Address) */ +/*! @{ */ #define OCOTP_GP3_BITS_MASK (0xFFFFFFFFU) #define OCOTP_GP3_BITS_SHIFT (0U) #define OCOTP_GP3_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_GP3_BITS_SHIFT)) & OCOTP_GP3_BITS_MASK) +/*! @} */ /*! @name GP1 - Value of OTP Bank4 Word6 (General Purpose Customer Defined Info) */ +/*! @{ */ #define OCOTP_GP1_BITS_MASK (0xFFFFFFFFU) #define OCOTP_GP1_BITS_SHIFT (0U) #define OCOTP_GP1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_GP1_BITS_SHIFT)) & OCOTP_GP1_BITS_MASK) +/*! @} */ /*! @name GP2 - Value of OTP Bank4 Word7 (General Purpose Customer Defined Info) */ +/*! @{ */ #define OCOTP_GP2_BITS_MASK (0xFFFFFFFFU) #define OCOTP_GP2_BITS_SHIFT (0U) #define OCOTP_GP2_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_GP2_BITS_SHIFT)) & OCOTP_GP2_BITS_MASK) +/*! @} */ /*! @name SW_GP1 - Value of OTP Bank5 Word0 (SW GP1) */ +/*! @{ */ #define OCOTP_SW_GP1_BITS_MASK (0xFFFFFFFFU) #define OCOTP_SW_GP1_BITS_SHIFT (0U) #define OCOTP_SW_GP1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_GP1_BITS_SHIFT)) & OCOTP_SW_GP1_BITS_MASK) +/*! @} */ /*! @name SW_GP20 - Value of OTP Bank5 Word1 (SW GP2) */ +/*! @{ */ #define OCOTP_SW_GP20_BITS_MASK (0xFFFFFFFFU) #define OCOTP_SW_GP20_BITS_SHIFT (0U) #define OCOTP_SW_GP20_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_GP20_BITS_SHIFT)) & OCOTP_SW_GP20_BITS_MASK) +/*! @} */ /*! @name SW_GP21 - Value of OTP Bank5 Word2 (SW GP2) */ +/*! @{ */ #define OCOTP_SW_GP21_BITS_MASK (0xFFFFFFFFU) #define OCOTP_SW_GP21_BITS_SHIFT (0U) #define OCOTP_SW_GP21_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_GP21_BITS_SHIFT)) & OCOTP_SW_GP21_BITS_MASK) +/*! @} */ /*! @name SW_GP22 - Value of OTP Bank5 Word3 (SW GP2) */ +/*! @{ */ #define OCOTP_SW_GP22_BITS_MASK (0xFFFFFFFFU) #define OCOTP_SW_GP22_BITS_SHIFT (0U) #define OCOTP_SW_GP22_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_GP22_BITS_SHIFT)) & OCOTP_SW_GP22_BITS_MASK) +/*! @} */ /*! @name SW_GP23 - Value of OTP Bank5 Word4 (SW GP2) */ +/*! @{ */ #define OCOTP_SW_GP23_BITS_MASK (0xFFFFFFFFU) #define OCOTP_SW_GP23_BITS_SHIFT (0U) #define OCOTP_SW_GP23_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_GP23_BITS_SHIFT)) & OCOTP_SW_GP23_BITS_MASK) +/*! @} */ /*! @name MISC_CONF0 - Value of OTP Bank5 Word5 (Misc Conf) */ +/*! @{ */ #define OCOTP_MISC_CONF0_BITS_MASK (0xFFFFFFFFU) #define OCOTP_MISC_CONF0_BITS_SHIFT (0U) #define OCOTP_MISC_CONF0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MISC_CONF0_BITS_SHIFT)) & OCOTP_MISC_CONF0_BITS_MASK) +/*! @} */ /*! @name MISC_CONF1 - Value of OTP Bank5 Word6 (Misc Conf) */ +/*! @{ */ #define OCOTP_MISC_CONF1_BITS_MASK (0xFFFFFFFFU) #define OCOTP_MISC_CONF1_BITS_SHIFT (0U) #define OCOTP_MISC_CONF1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MISC_CONF1_BITS_SHIFT)) & OCOTP_MISC_CONF1_BITS_MASK) +/*! @} */ /*! @name SRK_REVOKE - Value of OTP Bank5 Word7 (SRK Revoke) */ +/*! @{ */ #define OCOTP_SRK_REVOKE_BITS_MASK (0xFFFFFFFFU) #define OCOTP_SRK_REVOKE_BITS_SHIFT (0U) #define OCOTP_SRK_REVOKE_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK_REVOKE_BITS_SHIFT)) & OCOTP_SRK_REVOKE_BITS_MASK) +/*! @} */ /*! @@ -14593,56 +23232,88 @@ typedef struct { */ /*! @name MEGA_CTRL - PGC Mega Control Register */ +/*! @{ */ #define PGC_MEGA_CTRL_PCR_MASK (0x1U) #define PGC_MEGA_CTRL_PCR_SHIFT (0U) +/*! PCR + * 0b0..Do not switch off power even if pdn_req is asserted. + * 0b1..Switch off power when pdn_req is asserted. + */ #define PGC_MEGA_CTRL_PCR(x) (((uint32_t)(((uint32_t)(x)) << PGC_MEGA_CTRL_PCR_SHIFT)) & PGC_MEGA_CTRL_PCR_MASK) +/*! @} */ /*! @name MEGA_PUPSCR - PGC Mega Power Up Sequence Control Register */ +/*! @{ */ #define PGC_MEGA_PUPSCR_SW_MASK (0x3FU) #define PGC_MEGA_PUPSCR_SW_SHIFT (0U) #define PGC_MEGA_PUPSCR_SW(x) (((uint32_t)(((uint32_t)(x)) << PGC_MEGA_PUPSCR_SW_SHIFT)) & PGC_MEGA_PUPSCR_SW_MASK) #define PGC_MEGA_PUPSCR_SW2ISO_MASK (0x3F00U) #define PGC_MEGA_PUPSCR_SW2ISO_SHIFT (8U) #define PGC_MEGA_PUPSCR_SW2ISO(x) (((uint32_t)(((uint32_t)(x)) << PGC_MEGA_PUPSCR_SW2ISO_SHIFT)) & PGC_MEGA_PUPSCR_SW2ISO_MASK) +/*! @} */ /*! @name MEGA_PDNSCR - PGC Mega Pull Down Sequence Control Register */ +/*! @{ */ #define PGC_MEGA_PDNSCR_ISO_MASK (0x3FU) #define PGC_MEGA_PDNSCR_ISO_SHIFT (0U) #define PGC_MEGA_PDNSCR_ISO(x) (((uint32_t)(((uint32_t)(x)) << PGC_MEGA_PDNSCR_ISO_SHIFT)) & PGC_MEGA_PDNSCR_ISO_MASK) #define PGC_MEGA_PDNSCR_ISO2SW_MASK (0x3F00U) #define PGC_MEGA_PDNSCR_ISO2SW_SHIFT (8U) #define PGC_MEGA_PDNSCR_ISO2SW(x) (((uint32_t)(((uint32_t)(x)) << PGC_MEGA_PDNSCR_ISO2SW_SHIFT)) & PGC_MEGA_PDNSCR_ISO2SW_MASK) +/*! @} */ /*! @name MEGA_SR - PGC Mega Power Gating Controller Status Register */ +/*! @{ */ #define PGC_MEGA_SR_PSR_MASK (0x1U) #define PGC_MEGA_SR_PSR_SHIFT (0U) +/*! PSR + * 0b0..The target subsystem was not powered down for the previous power-down request. + * 0b1..The target subsystem was powered down for the previous power-down request. + */ #define PGC_MEGA_SR_PSR(x) (((uint32_t)(((uint32_t)(x)) << PGC_MEGA_SR_PSR_SHIFT)) & PGC_MEGA_SR_PSR_MASK) +/*! @} */ /*! @name CPU_CTRL - PGC CPU Control Register */ +/*! @{ */ #define PGC_CPU_CTRL_PCR_MASK (0x1U) #define PGC_CPU_CTRL_PCR_SHIFT (0U) +/*! PCR + * 0b0..Do not switch off power even if pdn_req is asserted. + * 0b1..Switch off power when pdn_req is asserted. + */ #define PGC_CPU_CTRL_PCR(x) (((uint32_t)(((uint32_t)(x)) << PGC_CPU_CTRL_PCR_SHIFT)) & PGC_CPU_CTRL_PCR_MASK) +/*! @} */ /*! @name CPU_PUPSCR - PGC CPU Power Up Sequence Control Register */ +/*! @{ */ #define PGC_CPU_PUPSCR_SW_MASK (0x3FU) #define PGC_CPU_PUPSCR_SW_SHIFT (0U) #define PGC_CPU_PUPSCR_SW(x) (((uint32_t)(((uint32_t)(x)) << PGC_CPU_PUPSCR_SW_SHIFT)) & PGC_CPU_PUPSCR_SW_MASK) #define PGC_CPU_PUPSCR_SW2ISO_MASK (0x3F00U) #define PGC_CPU_PUPSCR_SW2ISO_SHIFT (8U) #define PGC_CPU_PUPSCR_SW2ISO(x) (((uint32_t)(((uint32_t)(x)) << PGC_CPU_PUPSCR_SW2ISO_SHIFT)) & PGC_CPU_PUPSCR_SW2ISO_MASK) +/*! @} */ /*! @name CPU_PDNSCR - PGC CPU Pull Down Sequence Control Register */ +/*! @{ */ #define PGC_CPU_PDNSCR_ISO_MASK (0x3FU) #define PGC_CPU_PDNSCR_ISO_SHIFT (0U) #define PGC_CPU_PDNSCR_ISO(x) (((uint32_t)(((uint32_t)(x)) << PGC_CPU_PDNSCR_ISO_SHIFT)) & PGC_CPU_PDNSCR_ISO_MASK) #define PGC_CPU_PDNSCR_ISO2SW_MASK (0x3F00U) #define PGC_CPU_PDNSCR_ISO2SW_SHIFT (8U) #define PGC_CPU_PDNSCR_ISO2SW(x) (((uint32_t)(((uint32_t)(x)) << PGC_CPU_PDNSCR_ISO2SW_SHIFT)) & PGC_CPU_PDNSCR_ISO2SW_MASK) +/*! @} */ /*! @name CPU_SR - PGC CPU Power Gating Controller Status Register */ +/*! @{ */ #define PGC_CPU_SR_PSR_MASK (0x1U) #define PGC_CPU_SR_PSR_SHIFT (0U) +/*! PSR + * 0b0..The target subsystem was not powered down for the previous power-down request. + * 0b1..The target subsystem was powered down for the previous power-down request. + */ #define PGC_CPU_SR_PSR(x) (((uint32_t)(((uint32_t)(x)) << PGC_CPU_SR_PSR_SHIFT)) & PGC_CPU_SR_PSR_MASK) +/*! @} */ /*! @@ -14699,57 +23370,95 @@ typedef struct { */ /*! @name MCR - PIT Module Control Register */ +/*! @{ */ #define PIT_MCR_FRZ_MASK (0x1U) #define PIT_MCR_FRZ_SHIFT (0U) +/*! FRZ - Freeze + * 0b0..Timers continue to run in Debug mode. + * 0b1..Timers are stopped in Debug mode. + */ #define PIT_MCR_FRZ(x) (((uint32_t)(((uint32_t)(x)) << PIT_MCR_FRZ_SHIFT)) & PIT_MCR_FRZ_MASK) #define PIT_MCR_MDIS_MASK (0x2U) #define PIT_MCR_MDIS_SHIFT (1U) +/*! MDIS - Module Disable - (PIT section) + * 0b0..Clock for standard PIT timers is enabled. + * 0b1..Clock for standard PIT timers is disabled. + */ #define PIT_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << PIT_MCR_MDIS_SHIFT)) & PIT_MCR_MDIS_MASK) +/*! @} */ /*! @name LTMR64H - PIT Upper Lifetime Timer Register */ +/*! @{ */ #define PIT_LTMR64H_LTH_MASK (0xFFFFFFFFU) #define PIT_LTMR64H_LTH_SHIFT (0U) #define PIT_LTMR64H_LTH(x) (((uint32_t)(((uint32_t)(x)) << PIT_LTMR64H_LTH_SHIFT)) & PIT_LTMR64H_LTH_MASK) +/*! @} */ /*! @name LTMR64L - PIT Lower Lifetime Timer Register */ +/*! @{ */ #define PIT_LTMR64L_LTL_MASK (0xFFFFFFFFU) #define PIT_LTMR64L_LTL_SHIFT (0U) #define PIT_LTMR64L_LTL(x) (((uint32_t)(((uint32_t)(x)) << PIT_LTMR64L_LTL_SHIFT)) & PIT_LTMR64L_LTL_MASK) +/*! @} */ /*! @name LDVAL - Timer Load Value Register */ +/*! @{ */ #define PIT_LDVAL_TSV_MASK (0xFFFFFFFFU) #define PIT_LDVAL_TSV_SHIFT (0U) #define PIT_LDVAL_TSV(x) (((uint32_t)(((uint32_t)(x)) << PIT_LDVAL_TSV_SHIFT)) & PIT_LDVAL_TSV_MASK) +/*! @} */ /* The count of PIT_LDVAL */ #define PIT_LDVAL_COUNT (4U) /*! @name CVAL - Current Timer Value Register */ +/*! @{ */ #define PIT_CVAL_TVL_MASK (0xFFFFFFFFU) #define PIT_CVAL_TVL_SHIFT (0U) #define PIT_CVAL_TVL(x) (((uint32_t)(((uint32_t)(x)) << PIT_CVAL_TVL_SHIFT)) & PIT_CVAL_TVL_MASK) +/*! @} */ /* The count of PIT_CVAL */ #define PIT_CVAL_COUNT (4U) /*! @name TCTRL - Timer Control Register */ +/*! @{ */ #define PIT_TCTRL_TEN_MASK (0x1U) #define PIT_TCTRL_TEN_SHIFT (0U) +/*! TEN - Timer Enable + * 0b0..Timer n is disabled. + * 0b1..Timer n is enabled. + */ #define PIT_TCTRL_TEN(x) (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_TEN_SHIFT)) & PIT_TCTRL_TEN_MASK) #define PIT_TCTRL_TIE_MASK (0x2U) #define PIT_TCTRL_TIE_SHIFT (1U) +/*! TIE - Timer Interrupt Enable + * 0b0..Interrupt requests from Timer n are disabled. + * 0b1..Interrupt will be requested whenever TIF is set. + */ #define PIT_TCTRL_TIE(x) (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_TIE_SHIFT)) & PIT_TCTRL_TIE_MASK) #define PIT_TCTRL_CHN_MASK (0x4U) #define PIT_TCTRL_CHN_SHIFT (2U) +/*! CHN - Chain Mode + * 0b0..Timer is not chained. + * 0b1..Timer is chained to previous timer. For example, for Channel 2, if this field is set, Timer 2 is chained to Timer 1. + */ #define PIT_TCTRL_CHN(x) (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_CHN_SHIFT)) & PIT_TCTRL_CHN_MASK) +/*! @} */ /* The count of PIT_TCTRL */ #define PIT_TCTRL_COUNT (4U) /*! @name TFLG - Timer Flag Register */ +/*! @{ */ #define PIT_TFLG_TIF_MASK (0x1U) #define PIT_TFLG_TIF_SHIFT (0U) +/*! TIF - Timer Interrupt Flag + * 0b0..Timeout has not yet occurred. + * 0b1..Timeout has occurred. + */ #define PIT_TFLG_TIF(x) (((uint32_t)(((uint32_t)(x)) << PIT_TFLG_TIF_SHIFT)) & PIT_TFLG_TIF_MASK) +/*! @} */ /* The count of PIT_TFLG */ #define PIT_TFLG_COUNT (4U) @@ -14829,6 +23538,7 @@ typedef struct { */ /*! @name REG_1P1 - Regulator 1P1 Register */ +/*! @{ */ #define PMU_REG_1P1_ENABLE_LINREG_MASK (0x1U) #define PMU_REG_1P1_ENABLE_LINREG_SHIFT (0U) #define PMU_REG_1P1_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_ENABLE_LINREG_SHIFT)) & PMU_REG_1P1_ENABLE_LINREG_MASK) @@ -14846,6 +23556,11 @@ typedef struct { #define PMU_REG_1P1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_BO_OFFSET_SHIFT)) & PMU_REG_1P1_BO_OFFSET_MASK) #define PMU_REG_1P1_OUTPUT_TRG_MASK (0x1F00U) #define PMU_REG_1P1_OUTPUT_TRG_SHIFT (8U) +/*! OUTPUT_TRG + * 0b00100..0.8V + * 0b10000..1.1V + * 0b000x1..1.375V + */ #define PMU_REG_1P1_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_OUTPUT_TRG_SHIFT)) & PMU_REG_1P1_OUTPUT_TRG_MASK) #define PMU_REG_1P1_BO_VDD1P1_MASK (0x10000U) #define PMU_REG_1P1_BO_VDD1P1_SHIFT (16U) @@ -14858,9 +23573,15 @@ typedef struct { #define PMU_REG_1P1_ENABLE_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_ENABLE_WEAK_LINREG_SHIFT)) & PMU_REG_1P1_ENABLE_WEAK_LINREG_MASK) #define PMU_REG_1P1_SELREF_WEAK_LINREG_MASK (0x80000U) #define PMU_REG_1P1_SELREF_WEAK_LINREG_SHIFT (19U) +/*! SELREF_WEAK_LINREG + * 0b0..Weak-linreg output tracks low-power-bandgap voltage + * 0b1..Weak-linreg output tracks VDD_SOC_IN voltage + */ #define PMU_REG_1P1_SELREF_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SELREF_WEAK_LINREG_SHIFT)) & PMU_REG_1P1_SELREF_WEAK_LINREG_MASK) +/*! @} */ /*! @name REG_1P1_SET - Regulator 1P1 Register */ +/*! @{ */ #define PMU_REG_1P1_SET_ENABLE_LINREG_MASK (0x1U) #define PMU_REG_1P1_SET_ENABLE_LINREG_SHIFT (0U) #define PMU_REG_1P1_SET_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_ENABLE_LINREG_SHIFT)) & PMU_REG_1P1_SET_ENABLE_LINREG_MASK) @@ -14878,6 +23599,11 @@ typedef struct { #define PMU_REG_1P1_SET_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_BO_OFFSET_SHIFT)) & PMU_REG_1P1_SET_BO_OFFSET_MASK) #define PMU_REG_1P1_SET_OUTPUT_TRG_MASK (0x1F00U) #define PMU_REG_1P1_SET_OUTPUT_TRG_SHIFT (8U) +/*! OUTPUT_TRG + * 0b00100..0.8V + * 0b10000..1.1V + * 0b000x1..1.375V + */ #define PMU_REG_1P1_SET_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_OUTPUT_TRG_SHIFT)) & PMU_REG_1P1_SET_OUTPUT_TRG_MASK) #define PMU_REG_1P1_SET_BO_VDD1P1_MASK (0x10000U) #define PMU_REG_1P1_SET_BO_VDD1P1_SHIFT (16U) @@ -14890,9 +23616,15 @@ typedef struct { #define PMU_REG_1P1_SET_ENABLE_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_ENABLE_WEAK_LINREG_SHIFT)) & PMU_REG_1P1_SET_ENABLE_WEAK_LINREG_MASK) #define PMU_REG_1P1_SET_SELREF_WEAK_LINREG_MASK (0x80000U) #define PMU_REG_1P1_SET_SELREF_WEAK_LINREG_SHIFT (19U) +/*! SELREF_WEAK_LINREG + * 0b0..Weak-linreg output tracks low-power-bandgap voltage + * 0b1..Weak-linreg output tracks VDD_SOC_IN voltage + */ #define PMU_REG_1P1_SET_SELREF_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_SELREF_WEAK_LINREG_SHIFT)) & PMU_REG_1P1_SET_SELREF_WEAK_LINREG_MASK) +/*! @} */ /*! @name REG_1P1_CLR - Regulator 1P1 Register */ +/*! @{ */ #define PMU_REG_1P1_CLR_ENABLE_LINREG_MASK (0x1U) #define PMU_REG_1P1_CLR_ENABLE_LINREG_SHIFT (0U) #define PMU_REG_1P1_CLR_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_ENABLE_LINREG_SHIFT)) & PMU_REG_1P1_CLR_ENABLE_LINREG_MASK) @@ -14910,6 +23642,11 @@ typedef struct { #define PMU_REG_1P1_CLR_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_BO_OFFSET_SHIFT)) & PMU_REG_1P1_CLR_BO_OFFSET_MASK) #define PMU_REG_1P1_CLR_OUTPUT_TRG_MASK (0x1F00U) #define PMU_REG_1P1_CLR_OUTPUT_TRG_SHIFT (8U) +/*! OUTPUT_TRG + * 0b00100..0.8V + * 0b10000..1.1V + * 0b000x1..1.375V + */ #define PMU_REG_1P1_CLR_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_OUTPUT_TRG_SHIFT)) & PMU_REG_1P1_CLR_OUTPUT_TRG_MASK) #define PMU_REG_1P1_CLR_BO_VDD1P1_MASK (0x10000U) #define PMU_REG_1P1_CLR_BO_VDD1P1_SHIFT (16U) @@ -14922,9 +23659,15 @@ typedef struct { #define PMU_REG_1P1_CLR_ENABLE_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_ENABLE_WEAK_LINREG_SHIFT)) & PMU_REG_1P1_CLR_ENABLE_WEAK_LINREG_MASK) #define PMU_REG_1P1_CLR_SELREF_WEAK_LINREG_MASK (0x80000U) #define PMU_REG_1P1_CLR_SELREF_WEAK_LINREG_SHIFT (19U) +/*! SELREF_WEAK_LINREG + * 0b0..Weak-linreg output tracks low-power-bandgap voltage + * 0b1..Weak-linreg output tracks VDD_SOC_IN voltage + */ #define PMU_REG_1P1_CLR_SELREF_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_SELREF_WEAK_LINREG_SHIFT)) & PMU_REG_1P1_CLR_SELREF_WEAK_LINREG_MASK) +/*! @} */ /*! @name REG_1P1_TOG - Regulator 1P1 Register */ +/*! @{ */ #define PMU_REG_1P1_TOG_ENABLE_LINREG_MASK (0x1U) #define PMU_REG_1P1_TOG_ENABLE_LINREG_SHIFT (0U) #define PMU_REG_1P1_TOG_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_ENABLE_LINREG_SHIFT)) & PMU_REG_1P1_TOG_ENABLE_LINREG_MASK) @@ -14942,6 +23685,11 @@ typedef struct { #define PMU_REG_1P1_TOG_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_BO_OFFSET_SHIFT)) & PMU_REG_1P1_TOG_BO_OFFSET_MASK) #define PMU_REG_1P1_TOG_OUTPUT_TRG_MASK (0x1F00U) #define PMU_REG_1P1_TOG_OUTPUT_TRG_SHIFT (8U) +/*! OUTPUT_TRG + * 0b00100..0.8V + * 0b10000..1.1V + * 0b000x1..1.375V + */ #define PMU_REG_1P1_TOG_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_OUTPUT_TRG_SHIFT)) & PMU_REG_1P1_TOG_OUTPUT_TRG_MASK) #define PMU_REG_1P1_TOG_BO_VDD1P1_MASK (0x10000U) #define PMU_REG_1P1_TOG_BO_VDD1P1_SHIFT (16U) @@ -14954,9 +23702,15 @@ typedef struct { #define PMU_REG_1P1_TOG_ENABLE_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_ENABLE_WEAK_LINREG_SHIFT)) & PMU_REG_1P1_TOG_ENABLE_WEAK_LINREG_MASK) #define PMU_REG_1P1_TOG_SELREF_WEAK_LINREG_MASK (0x80000U) #define PMU_REG_1P1_TOG_SELREF_WEAK_LINREG_SHIFT (19U) +/*! SELREF_WEAK_LINREG + * 0b0..Weak-linreg output tracks low-power-bandgap voltage + * 0b1..Weak-linreg output tracks VDD_SOC_IN voltage + */ #define PMU_REG_1P1_TOG_SELREF_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_SELREF_WEAK_LINREG_SHIFT)) & PMU_REG_1P1_TOG_SELREF_WEAK_LINREG_MASK) +/*! @} */ /*! @name REG_3P0 - Regulator 3P0 Register */ +/*! @{ */ #define PMU_REG_3P0_ENABLE_LINREG_MASK (0x1U) #define PMU_REG_3P0_ENABLE_LINREG_SHIFT (0U) #define PMU_REG_3P0_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_ENABLE_LINREG_SHIFT)) & PMU_REG_3P0_ENABLE_LINREG_MASK) @@ -14971,9 +23725,18 @@ typedef struct { #define PMU_REG_3P0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_BO_OFFSET_SHIFT)) & PMU_REG_3P0_BO_OFFSET_MASK) #define PMU_REG_3P0_VBUS_SEL_MASK (0x80U) #define PMU_REG_3P0_VBUS_SEL_SHIFT (7U) +/*! VBUS_SEL + * 0b1..Utilize VBUS OTG1 power + * 0b0..Utilize VBUS OTG2 power + */ #define PMU_REG_3P0_VBUS_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_VBUS_SEL_SHIFT)) & PMU_REG_3P0_VBUS_SEL_MASK) #define PMU_REG_3P0_OUTPUT_TRG_MASK (0x1F00U) #define PMU_REG_3P0_OUTPUT_TRG_SHIFT (8U) +/*! OUTPUT_TRG + * 0b00000..2.625V + * 0b01111..3.000V + * 0b11111..3.400V + */ #define PMU_REG_3P0_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_OUTPUT_TRG_SHIFT)) & PMU_REG_3P0_OUTPUT_TRG_MASK) #define PMU_REG_3P0_BO_VDD3P0_MASK (0x10000U) #define PMU_REG_3P0_BO_VDD3P0_SHIFT (16U) @@ -14981,8 +23744,10 @@ typedef struct { #define PMU_REG_3P0_OK_VDD3P0_MASK (0x20000U) #define PMU_REG_3P0_OK_VDD3P0_SHIFT (17U) #define PMU_REG_3P0_OK_VDD3P0(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_OK_VDD3P0_SHIFT)) & PMU_REG_3P0_OK_VDD3P0_MASK) +/*! @} */ /*! @name REG_3P0_SET - Regulator 3P0 Register */ +/*! @{ */ #define PMU_REG_3P0_SET_ENABLE_LINREG_MASK (0x1U) #define PMU_REG_3P0_SET_ENABLE_LINREG_SHIFT (0U) #define PMU_REG_3P0_SET_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_SET_ENABLE_LINREG_SHIFT)) & PMU_REG_3P0_SET_ENABLE_LINREG_MASK) @@ -14997,9 +23762,18 @@ typedef struct { #define PMU_REG_3P0_SET_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_SET_BO_OFFSET_SHIFT)) & PMU_REG_3P0_SET_BO_OFFSET_MASK) #define PMU_REG_3P0_SET_VBUS_SEL_MASK (0x80U) #define PMU_REG_3P0_SET_VBUS_SEL_SHIFT (7U) +/*! VBUS_SEL + * 0b1..Utilize VBUS OTG1 power + * 0b0..Utilize VBUS OTG2 power + */ #define PMU_REG_3P0_SET_VBUS_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_SET_VBUS_SEL_SHIFT)) & PMU_REG_3P0_SET_VBUS_SEL_MASK) #define PMU_REG_3P0_SET_OUTPUT_TRG_MASK (0x1F00U) #define PMU_REG_3P0_SET_OUTPUT_TRG_SHIFT (8U) +/*! OUTPUT_TRG + * 0b00000..2.625V + * 0b01111..3.000V + * 0b11111..3.400V + */ #define PMU_REG_3P0_SET_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_SET_OUTPUT_TRG_SHIFT)) & PMU_REG_3P0_SET_OUTPUT_TRG_MASK) #define PMU_REG_3P0_SET_BO_VDD3P0_MASK (0x10000U) #define PMU_REG_3P0_SET_BO_VDD3P0_SHIFT (16U) @@ -15007,8 +23781,10 @@ typedef struct { #define PMU_REG_3P0_SET_OK_VDD3P0_MASK (0x20000U) #define PMU_REG_3P0_SET_OK_VDD3P0_SHIFT (17U) #define PMU_REG_3P0_SET_OK_VDD3P0(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_SET_OK_VDD3P0_SHIFT)) & PMU_REG_3P0_SET_OK_VDD3P0_MASK) +/*! @} */ /*! @name REG_3P0_CLR - Regulator 3P0 Register */ +/*! @{ */ #define PMU_REG_3P0_CLR_ENABLE_LINREG_MASK (0x1U) #define PMU_REG_3P0_CLR_ENABLE_LINREG_SHIFT (0U) #define PMU_REG_3P0_CLR_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_CLR_ENABLE_LINREG_SHIFT)) & PMU_REG_3P0_CLR_ENABLE_LINREG_MASK) @@ -15023,9 +23799,18 @@ typedef struct { #define PMU_REG_3P0_CLR_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_CLR_BO_OFFSET_SHIFT)) & PMU_REG_3P0_CLR_BO_OFFSET_MASK) #define PMU_REG_3P0_CLR_VBUS_SEL_MASK (0x80U) #define PMU_REG_3P0_CLR_VBUS_SEL_SHIFT (7U) +/*! VBUS_SEL + * 0b1..Utilize VBUS OTG1 power + * 0b0..Utilize VBUS OTG2 power + */ #define PMU_REG_3P0_CLR_VBUS_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_CLR_VBUS_SEL_SHIFT)) & PMU_REG_3P0_CLR_VBUS_SEL_MASK) #define PMU_REG_3P0_CLR_OUTPUT_TRG_MASK (0x1F00U) #define PMU_REG_3P0_CLR_OUTPUT_TRG_SHIFT (8U) +/*! OUTPUT_TRG + * 0b00000..2.625V + * 0b01111..3.000V + * 0b11111..3.400V + */ #define PMU_REG_3P0_CLR_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_CLR_OUTPUT_TRG_SHIFT)) & PMU_REG_3P0_CLR_OUTPUT_TRG_MASK) #define PMU_REG_3P0_CLR_BO_VDD3P0_MASK (0x10000U) #define PMU_REG_3P0_CLR_BO_VDD3P0_SHIFT (16U) @@ -15033,8 +23818,10 @@ typedef struct { #define PMU_REG_3P0_CLR_OK_VDD3P0_MASK (0x20000U) #define PMU_REG_3P0_CLR_OK_VDD3P0_SHIFT (17U) #define PMU_REG_3P0_CLR_OK_VDD3P0(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_CLR_OK_VDD3P0_SHIFT)) & PMU_REG_3P0_CLR_OK_VDD3P0_MASK) +/*! @} */ /*! @name REG_3P0_TOG - Regulator 3P0 Register */ +/*! @{ */ #define PMU_REG_3P0_TOG_ENABLE_LINREG_MASK (0x1U) #define PMU_REG_3P0_TOG_ENABLE_LINREG_SHIFT (0U) #define PMU_REG_3P0_TOG_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_TOG_ENABLE_LINREG_SHIFT)) & PMU_REG_3P0_TOG_ENABLE_LINREG_MASK) @@ -15049,9 +23836,18 @@ typedef struct { #define PMU_REG_3P0_TOG_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_TOG_BO_OFFSET_SHIFT)) & PMU_REG_3P0_TOG_BO_OFFSET_MASK) #define PMU_REG_3P0_TOG_VBUS_SEL_MASK (0x80U) #define PMU_REG_3P0_TOG_VBUS_SEL_SHIFT (7U) +/*! VBUS_SEL + * 0b1..Utilize VBUS OTG1 power + * 0b0..Utilize VBUS OTG2 power + */ #define PMU_REG_3P0_TOG_VBUS_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_TOG_VBUS_SEL_SHIFT)) & PMU_REG_3P0_TOG_VBUS_SEL_MASK) #define PMU_REG_3P0_TOG_OUTPUT_TRG_MASK (0x1F00U) #define PMU_REG_3P0_TOG_OUTPUT_TRG_SHIFT (8U) +/*! OUTPUT_TRG + * 0b00000..2.625V + * 0b01111..3.000V + * 0b11111..3.400V + */ #define PMU_REG_3P0_TOG_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_TOG_OUTPUT_TRG_SHIFT)) & PMU_REG_3P0_TOG_OUTPUT_TRG_MASK) #define PMU_REG_3P0_TOG_BO_VDD3P0_MASK (0x10000U) #define PMU_REG_3P0_TOG_BO_VDD3P0_SHIFT (16U) @@ -15059,8 +23855,10 @@ typedef struct { #define PMU_REG_3P0_TOG_OK_VDD3P0_MASK (0x20000U) #define PMU_REG_3P0_TOG_OK_VDD3P0_SHIFT (17U) #define PMU_REG_3P0_TOG_OK_VDD3P0(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_TOG_OK_VDD3P0_SHIFT)) & PMU_REG_3P0_TOG_OK_VDD3P0_MASK) +/*! @} */ /*! @name REG_2P5 - Regulator 2P5 Register */ +/*! @{ */ #define PMU_REG_2P5_ENABLE_LINREG_MASK (0x1U) #define PMU_REG_2P5_ENABLE_LINREG_SHIFT (0U) #define PMU_REG_2P5_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_ENABLE_LINREG_SHIFT)) & PMU_REG_2P5_ENABLE_LINREG_MASK) @@ -15078,6 +23876,11 @@ typedef struct { #define PMU_REG_2P5_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_BO_OFFSET_SHIFT)) & PMU_REG_2P5_BO_OFFSET_MASK) #define PMU_REG_2P5_OUTPUT_TRG_MASK (0x1F00U) #define PMU_REG_2P5_OUTPUT_TRG_SHIFT (8U) +/*! OUTPUT_TRG + * 0b00000..2.10V + * 0b10000..2.50V + * 0b11111..2.875V + */ #define PMU_REG_2P5_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_OUTPUT_TRG_SHIFT)) & PMU_REG_2P5_OUTPUT_TRG_MASK) #define PMU_REG_2P5_BO_VDD2P5_MASK (0x10000U) #define PMU_REG_2P5_BO_VDD2P5_SHIFT (16U) @@ -15088,8 +23891,10 @@ typedef struct { #define PMU_REG_2P5_ENABLE_WEAK_LINREG_MASK (0x40000U) #define PMU_REG_2P5_ENABLE_WEAK_LINREG_SHIFT (18U) #define PMU_REG_2P5_ENABLE_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_ENABLE_WEAK_LINREG_SHIFT)) & PMU_REG_2P5_ENABLE_WEAK_LINREG_MASK) +/*! @} */ /*! @name REG_2P5_SET - Regulator 2P5 Register */ +/*! @{ */ #define PMU_REG_2P5_SET_ENABLE_LINREG_MASK (0x1U) #define PMU_REG_2P5_SET_ENABLE_LINREG_SHIFT (0U) #define PMU_REG_2P5_SET_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_SET_ENABLE_LINREG_SHIFT)) & PMU_REG_2P5_SET_ENABLE_LINREG_MASK) @@ -15107,6 +23912,11 @@ typedef struct { #define PMU_REG_2P5_SET_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_SET_BO_OFFSET_SHIFT)) & PMU_REG_2P5_SET_BO_OFFSET_MASK) #define PMU_REG_2P5_SET_OUTPUT_TRG_MASK (0x1F00U) #define PMU_REG_2P5_SET_OUTPUT_TRG_SHIFT (8U) +/*! OUTPUT_TRG + * 0b00000..2.10V + * 0b10000..2.50V + * 0b11111..2.875V + */ #define PMU_REG_2P5_SET_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_SET_OUTPUT_TRG_SHIFT)) & PMU_REG_2P5_SET_OUTPUT_TRG_MASK) #define PMU_REG_2P5_SET_BO_VDD2P5_MASK (0x10000U) #define PMU_REG_2P5_SET_BO_VDD2P5_SHIFT (16U) @@ -15117,8 +23927,10 @@ typedef struct { #define PMU_REG_2P5_SET_ENABLE_WEAK_LINREG_MASK (0x40000U) #define PMU_REG_2P5_SET_ENABLE_WEAK_LINREG_SHIFT (18U) #define PMU_REG_2P5_SET_ENABLE_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_SET_ENABLE_WEAK_LINREG_SHIFT)) & PMU_REG_2P5_SET_ENABLE_WEAK_LINREG_MASK) +/*! @} */ /*! @name REG_2P5_CLR - Regulator 2P5 Register */ +/*! @{ */ #define PMU_REG_2P5_CLR_ENABLE_LINREG_MASK (0x1U) #define PMU_REG_2P5_CLR_ENABLE_LINREG_SHIFT (0U) #define PMU_REG_2P5_CLR_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_CLR_ENABLE_LINREG_SHIFT)) & PMU_REG_2P5_CLR_ENABLE_LINREG_MASK) @@ -15136,6 +23948,11 @@ typedef struct { #define PMU_REG_2P5_CLR_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_CLR_BO_OFFSET_SHIFT)) & PMU_REG_2P5_CLR_BO_OFFSET_MASK) #define PMU_REG_2P5_CLR_OUTPUT_TRG_MASK (0x1F00U) #define PMU_REG_2P5_CLR_OUTPUT_TRG_SHIFT (8U) +/*! OUTPUT_TRG + * 0b00000..2.10V + * 0b10000..2.50V + * 0b11111..2.875V + */ #define PMU_REG_2P5_CLR_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_CLR_OUTPUT_TRG_SHIFT)) & PMU_REG_2P5_CLR_OUTPUT_TRG_MASK) #define PMU_REG_2P5_CLR_BO_VDD2P5_MASK (0x10000U) #define PMU_REG_2P5_CLR_BO_VDD2P5_SHIFT (16U) @@ -15146,8 +23963,10 @@ typedef struct { #define PMU_REG_2P5_CLR_ENABLE_WEAK_LINREG_MASK (0x40000U) #define PMU_REG_2P5_CLR_ENABLE_WEAK_LINREG_SHIFT (18U) #define PMU_REG_2P5_CLR_ENABLE_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_CLR_ENABLE_WEAK_LINREG_SHIFT)) & PMU_REG_2P5_CLR_ENABLE_WEAK_LINREG_MASK) +/*! @} */ /*! @name REG_2P5_TOG - Regulator 2P5 Register */ +/*! @{ */ #define PMU_REG_2P5_TOG_ENABLE_LINREG_MASK (0x1U) #define PMU_REG_2P5_TOG_ENABLE_LINREG_SHIFT (0U) #define PMU_REG_2P5_TOG_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_TOG_ENABLE_LINREG_SHIFT)) & PMU_REG_2P5_TOG_ENABLE_LINREG_MASK) @@ -15165,6 +23984,11 @@ typedef struct { #define PMU_REG_2P5_TOG_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_TOG_BO_OFFSET_SHIFT)) & PMU_REG_2P5_TOG_BO_OFFSET_MASK) #define PMU_REG_2P5_TOG_OUTPUT_TRG_MASK (0x1F00U) #define PMU_REG_2P5_TOG_OUTPUT_TRG_SHIFT (8U) +/*! OUTPUT_TRG + * 0b00000..2.10V + * 0b10000..2.50V + * 0b11111..2.875V + */ #define PMU_REG_2P5_TOG_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_TOG_OUTPUT_TRG_SHIFT)) & PMU_REG_2P5_TOG_OUTPUT_TRG_MASK) #define PMU_REG_2P5_TOG_BO_VDD2P5_MASK (0x10000U) #define PMU_REG_2P5_TOG_BO_VDD2P5_SHIFT (16U) @@ -15175,84 +23999,520 @@ typedef struct { #define PMU_REG_2P5_TOG_ENABLE_WEAK_LINREG_MASK (0x40000U) #define PMU_REG_2P5_TOG_ENABLE_WEAK_LINREG_SHIFT (18U) #define PMU_REG_2P5_TOG_ENABLE_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_TOG_ENABLE_WEAK_LINREG_SHIFT)) & PMU_REG_2P5_TOG_ENABLE_WEAK_LINREG_MASK) +/*! @} */ /*! @name REG_CORE - Digital Regulator Core Register */ +/*! @{ */ #define PMU_REG_CORE_REG0_TARG_MASK (0x1FU) #define PMU_REG_CORE_REG0_TARG_SHIFT (0U) +/*! REG0_TARG + * 0b00000..Power gated off + * 0b00001..Target core voltage = 0.725V + * 0b00010..Target core voltage = 0.750V + * 0b00011..Target core voltage = 0.775V + * 0b10000..Target core voltage = 1.100V + * 0b11110..Target core voltage = 1.450V + * 0b11111..Power FET switched full on. No regulation. + */ #define PMU_REG_CORE_REG0_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_REG0_TARG_SHIFT)) & PMU_REG_CORE_REG0_TARG_MASK) +#define PMU_REG_CORE_REG0_ADJ_MASK (0x1E0U) +#define PMU_REG_CORE_REG0_ADJ_SHIFT (5U) +/*! REG0_ADJ - This bit field defines the adjustment bits to calibrate the target value of Reg0. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register. + * 0b0000..No adjustment + * 0b0001..+ 0.25% + * 0b0010..+ 0.50% + * 0b0011..+ 0.75% + * 0b0100..+ 1.00% + * 0b0101..+ 1.25% + * 0b0110..+ 1.50% + * 0b0111..+ 1.75% + * 0b1000..- 0.25% + * 0b1001..- 0.50% + * 0b1010..- 0.75% + * 0b1011..- 1.00% + * 0b1100..- 1.25% + * 0b1101..- 1.50% + * 0b1110..- 1.75% + * 0b1111..- 2.00% + */ +#define PMU_REG_CORE_REG0_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_REG0_ADJ_SHIFT)) & PMU_REG_CORE_REG0_ADJ_MASK) +#define PMU_REG_CORE_REG1_TARG_MASK (0x3E00U) +#define PMU_REG_CORE_REG1_TARG_SHIFT (9U) +/*! REG1_TARG - This bit field defines the target voltage for the vpu/gpu power domain. Single bit increments reflect 25mV core voltage steps. Not all steps will make sense to use either because of input supply limitations or load operation. + * 0b00000..Power gated off + * 0b00001..Target core voltage = 0.725V + * 0b00010..Target core voltage = 0.750V + * 0b00011..Target core voltage = 0.775V + * 0b10000..Target core voltage = 1.100V + * 0b11110..Target core voltage = 1.450V + * 0b11111..Power FET switched full on. No regulation. + */ +#define PMU_REG_CORE_REG1_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_REG1_TARG_SHIFT)) & PMU_REG_CORE_REG1_TARG_MASK) +#define PMU_REG_CORE_REG1_ADJ_MASK (0x3C000U) +#define PMU_REG_CORE_REG1_ADJ_SHIFT (14U) +/*! REG1_ADJ - This bit field defines the adjustment bits to calibrate the target value of Reg1. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register. + * 0b0000..No adjustment + * 0b0001..+ 0.25% + * 0b0010..+ 0.50% + * 0b0011..+ 0.75% + * 0b0100..+ 1.00% + * 0b0101..+ 1.25% + * 0b0110..+ 1.50% + * 0b0111..+ 1.75% + * 0b1000..- 0.25% + * 0b1001..- 0.50% + * 0b1010..- 0.75% + * 0b1011..- 1.00% + * 0b1100..- 1.25% + * 0b1101..- 1.50% + * 0b1110..- 1.75% + * 0b1111..- 2.00% + */ +#define PMU_REG_CORE_REG1_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_REG1_ADJ_SHIFT)) & PMU_REG_CORE_REG1_ADJ_MASK) #define PMU_REG_CORE_REG2_TARG_MASK (0x7C0000U) #define PMU_REG_CORE_REG2_TARG_SHIFT (18U) +/*! REG2_TARG + * 0b00000..Power gated off + * 0b00001..Target core voltage = 0.725V + * 0b00010..Target core voltage = 0.750V + * 0b00011..Target core voltage = 0.775V + * 0b10000..Target core voltage = 1.100V + * 0b11110..Target core voltage = 1.450V + * 0b11111..Power FET switched full on. No regulation. + */ #define PMU_REG_CORE_REG2_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_REG2_TARG_SHIFT)) & PMU_REG_CORE_REG2_TARG_MASK) +#define PMU_REG_CORE_REG2_ADJ_MASK (0x7800000U) +#define PMU_REG_CORE_REG2_ADJ_SHIFT (23U) +/*! REG2_ADJ - This bit field defines the adjustment bits to calibrate the target value of Reg2. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register. + * 0b0000..No adjustment + * 0b0001..+ 0.25% + * 0b0010..+ 0.50% + * 0b0011..+ 0.75% + * 0b0100..+ 1.00% + * 0b0101..+ 1.25% + * 0b0110..+ 1.50% + * 0b0111..+ 1.75% + * 0b1000..- 0.25% + * 0b1001..- 0.50% + * 0b1010..- 0.75% + * 0b1011..- 1.00% + * 0b1100..- 1.25% + * 0b1101..- 1.50% + * 0b1110..- 1.75% + * 0b1111..- 2.00% + */ +#define PMU_REG_CORE_REG2_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_REG2_ADJ_SHIFT)) & PMU_REG_CORE_REG2_ADJ_MASK) #define PMU_REG_CORE_RAMP_RATE_MASK (0x18000000U) #define PMU_REG_CORE_RAMP_RATE_SHIFT (27U) +/*! RAMP_RATE + * 0b00..Fast + * 0b01..Medium Fast + * 0b10..Medium Slow + * 0b11..Slow + */ #define PMU_REG_CORE_RAMP_RATE(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_RAMP_RATE_SHIFT)) & PMU_REG_CORE_RAMP_RATE_MASK) #define PMU_REG_CORE_FET_ODRIVE_MASK (0x20000000U) #define PMU_REG_CORE_FET_ODRIVE_SHIFT (29U) #define PMU_REG_CORE_FET_ODRIVE(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_FET_ODRIVE_SHIFT)) & PMU_REG_CORE_FET_ODRIVE_MASK) +/*! @} */ /*! @name REG_CORE_SET - Digital Regulator Core Register */ +/*! @{ */ #define PMU_REG_CORE_SET_REG0_TARG_MASK (0x1FU) #define PMU_REG_CORE_SET_REG0_TARG_SHIFT (0U) +/*! REG0_TARG + * 0b00000..Power gated off + * 0b00001..Target core voltage = 0.725V + * 0b00010..Target core voltage = 0.750V + * 0b00011..Target core voltage = 0.775V + * 0b10000..Target core voltage = 1.100V + * 0b11110..Target core voltage = 1.450V + * 0b11111..Power FET switched full on. No regulation. + */ #define PMU_REG_CORE_SET_REG0_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_SET_REG0_TARG_SHIFT)) & PMU_REG_CORE_SET_REG0_TARG_MASK) +#define PMU_REG_CORE_SET_REG0_ADJ_MASK (0x1E0U) +#define PMU_REG_CORE_SET_REG0_ADJ_SHIFT (5U) +/*! REG0_ADJ - This bit field defines the adjustment bits to calibrate the target value of Reg0. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register. + * 0b0000..No adjustment + * 0b0001..+ 0.25% + * 0b0010..+ 0.50% + * 0b0011..+ 0.75% + * 0b0100..+ 1.00% + * 0b0101..+ 1.25% + * 0b0110..+ 1.50% + * 0b0111..+ 1.75% + * 0b1000..- 0.25% + * 0b1001..- 0.50% + * 0b1010..- 0.75% + * 0b1011..- 1.00% + * 0b1100..- 1.25% + * 0b1101..- 1.50% + * 0b1110..- 1.75% + * 0b1111..- 2.00% + */ +#define PMU_REG_CORE_SET_REG0_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_SET_REG0_ADJ_SHIFT)) & PMU_REG_CORE_SET_REG0_ADJ_MASK) +#define PMU_REG_CORE_SET_REG1_TARG_MASK (0x3E00U) +#define PMU_REG_CORE_SET_REG1_TARG_SHIFT (9U) +/*! REG1_TARG - This bit field defines the target voltage for the vpu/gpu power domain. Single bit increments reflect 25mV core voltage steps. Not all steps will make sense to use either because of input supply limitations or load operation. + * 0b00000..Power gated off + * 0b00001..Target core voltage = 0.725V + * 0b00010..Target core voltage = 0.750V + * 0b00011..Target core voltage = 0.775V + * 0b10000..Target core voltage = 1.100V + * 0b11110..Target core voltage = 1.450V + * 0b11111..Power FET switched full on. No regulation. + */ +#define PMU_REG_CORE_SET_REG1_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_SET_REG1_TARG_SHIFT)) & PMU_REG_CORE_SET_REG1_TARG_MASK) +#define PMU_REG_CORE_SET_REG1_ADJ_MASK (0x3C000U) +#define PMU_REG_CORE_SET_REG1_ADJ_SHIFT (14U) +/*! REG1_ADJ - This bit field defines the adjustment bits to calibrate the target value of Reg1. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register. + * 0b0000..No adjustment + * 0b0001..+ 0.25% + * 0b0010..+ 0.50% + * 0b0011..+ 0.75% + * 0b0100..+ 1.00% + * 0b0101..+ 1.25% + * 0b0110..+ 1.50% + * 0b0111..+ 1.75% + * 0b1000..- 0.25% + * 0b1001..- 0.50% + * 0b1010..- 0.75% + * 0b1011..- 1.00% + * 0b1100..- 1.25% + * 0b1101..- 1.50% + * 0b1110..- 1.75% + * 0b1111..- 2.00% + */ +#define PMU_REG_CORE_SET_REG1_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_SET_REG1_ADJ_SHIFT)) & PMU_REG_CORE_SET_REG1_ADJ_MASK) #define PMU_REG_CORE_SET_REG2_TARG_MASK (0x7C0000U) #define PMU_REG_CORE_SET_REG2_TARG_SHIFT (18U) +/*! REG2_TARG + * 0b00000..Power gated off + * 0b00001..Target core voltage = 0.725V + * 0b00010..Target core voltage = 0.750V + * 0b00011..Target core voltage = 0.775V + * 0b10000..Target core voltage = 1.100V + * 0b11110..Target core voltage = 1.450V + * 0b11111..Power FET switched full on. No regulation. + */ #define PMU_REG_CORE_SET_REG2_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_SET_REG2_TARG_SHIFT)) & PMU_REG_CORE_SET_REG2_TARG_MASK) +#define PMU_REG_CORE_SET_REG2_ADJ_MASK (0x7800000U) +#define PMU_REG_CORE_SET_REG2_ADJ_SHIFT (23U) +/*! REG2_ADJ - This bit field defines the adjustment bits to calibrate the target value of Reg2. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register. + * 0b0000..No adjustment + * 0b0001..+ 0.25% + * 0b0010..+ 0.50% + * 0b0011..+ 0.75% + * 0b0100..+ 1.00% + * 0b0101..+ 1.25% + * 0b0110..+ 1.50% + * 0b0111..+ 1.75% + * 0b1000..- 0.25% + * 0b1001..- 0.50% + * 0b1010..- 0.75% + * 0b1011..- 1.00% + * 0b1100..- 1.25% + * 0b1101..- 1.50% + * 0b1110..- 1.75% + * 0b1111..- 2.00% + */ +#define PMU_REG_CORE_SET_REG2_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_SET_REG2_ADJ_SHIFT)) & PMU_REG_CORE_SET_REG2_ADJ_MASK) #define PMU_REG_CORE_SET_RAMP_RATE_MASK (0x18000000U) #define PMU_REG_CORE_SET_RAMP_RATE_SHIFT (27U) +/*! RAMP_RATE + * 0b00..Fast + * 0b01..Medium Fast + * 0b10..Medium Slow + * 0b11..Slow + */ #define PMU_REG_CORE_SET_RAMP_RATE(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_SET_RAMP_RATE_SHIFT)) & PMU_REG_CORE_SET_RAMP_RATE_MASK) #define PMU_REG_CORE_SET_FET_ODRIVE_MASK (0x20000000U) #define PMU_REG_CORE_SET_FET_ODRIVE_SHIFT (29U) #define PMU_REG_CORE_SET_FET_ODRIVE(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_SET_FET_ODRIVE_SHIFT)) & PMU_REG_CORE_SET_FET_ODRIVE_MASK) +/*! @} */ /*! @name REG_CORE_CLR - Digital Regulator Core Register */ +/*! @{ */ #define PMU_REG_CORE_CLR_REG0_TARG_MASK (0x1FU) #define PMU_REG_CORE_CLR_REG0_TARG_SHIFT (0U) +/*! REG0_TARG + * 0b00000..Power gated off + * 0b00001..Target core voltage = 0.725V + * 0b00010..Target core voltage = 0.750V + * 0b00011..Target core voltage = 0.775V + * 0b10000..Target core voltage = 1.100V + * 0b11110..Target core voltage = 1.450V + * 0b11111..Power FET switched full on. No regulation. + */ #define PMU_REG_CORE_CLR_REG0_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_CLR_REG0_TARG_SHIFT)) & PMU_REG_CORE_CLR_REG0_TARG_MASK) +#define PMU_REG_CORE_CLR_REG0_ADJ_MASK (0x1E0U) +#define PMU_REG_CORE_CLR_REG0_ADJ_SHIFT (5U) +/*! REG0_ADJ - This bit field defines the adjustment bits to calibrate the target value of Reg0. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register. + * 0b0000..No adjustment + * 0b0001..+ 0.25% + * 0b0010..+ 0.50% + * 0b0011..+ 0.75% + * 0b0100..+ 1.00% + * 0b0101..+ 1.25% + * 0b0110..+ 1.50% + * 0b0111..+ 1.75% + * 0b1000..- 0.25% + * 0b1001..- 0.50% + * 0b1010..- 0.75% + * 0b1011..- 1.00% + * 0b1100..- 1.25% + * 0b1101..- 1.50% + * 0b1110..- 1.75% + * 0b1111..- 2.00% + */ +#define PMU_REG_CORE_CLR_REG0_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_CLR_REG0_ADJ_SHIFT)) & PMU_REG_CORE_CLR_REG0_ADJ_MASK) +#define PMU_REG_CORE_CLR_REG1_TARG_MASK (0x3E00U) +#define PMU_REG_CORE_CLR_REG1_TARG_SHIFT (9U) +/*! REG1_TARG - This bit field defines the target voltage for the vpu/gpu power domain. Single bit increments reflect 25mV core voltage steps. Not all steps will make sense to use either because of input supply limitations or load operation. + * 0b00000..Power gated off + * 0b00001..Target core voltage = 0.725V + * 0b00010..Target core voltage = 0.750V + * 0b00011..Target core voltage = 0.775V + * 0b10000..Target core voltage = 1.100V + * 0b11110..Target core voltage = 1.450V + * 0b11111..Power FET switched full on. No regulation. + */ +#define PMU_REG_CORE_CLR_REG1_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_CLR_REG1_TARG_SHIFT)) & PMU_REG_CORE_CLR_REG1_TARG_MASK) +#define PMU_REG_CORE_CLR_REG1_ADJ_MASK (0x3C000U) +#define PMU_REG_CORE_CLR_REG1_ADJ_SHIFT (14U) +/*! REG1_ADJ - This bit field defines the adjustment bits to calibrate the target value of Reg1. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register. + * 0b0000..No adjustment + * 0b0001..+ 0.25% + * 0b0010..+ 0.50% + * 0b0011..+ 0.75% + * 0b0100..+ 1.00% + * 0b0101..+ 1.25% + * 0b0110..+ 1.50% + * 0b0111..+ 1.75% + * 0b1000..- 0.25% + * 0b1001..- 0.50% + * 0b1010..- 0.75% + * 0b1011..- 1.00% + * 0b1100..- 1.25% + * 0b1101..- 1.50% + * 0b1110..- 1.75% + * 0b1111..- 2.00% + */ +#define PMU_REG_CORE_CLR_REG1_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_CLR_REG1_ADJ_SHIFT)) & PMU_REG_CORE_CLR_REG1_ADJ_MASK) #define PMU_REG_CORE_CLR_REG2_TARG_MASK (0x7C0000U) #define PMU_REG_CORE_CLR_REG2_TARG_SHIFT (18U) +/*! REG2_TARG + * 0b00000..Power gated off + * 0b00001..Target core voltage = 0.725V + * 0b00010..Target core voltage = 0.750V + * 0b00011..Target core voltage = 0.775V + * 0b10000..Target core voltage = 1.100V + * 0b11110..Target core voltage = 1.450V + * 0b11111..Power FET switched full on. No regulation. + */ #define PMU_REG_CORE_CLR_REG2_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_CLR_REG2_TARG_SHIFT)) & PMU_REG_CORE_CLR_REG2_TARG_MASK) +#define PMU_REG_CORE_CLR_REG2_ADJ_MASK (0x7800000U) +#define PMU_REG_CORE_CLR_REG2_ADJ_SHIFT (23U) +/*! REG2_ADJ - This bit field defines the adjustment bits to calibrate the target value of Reg2. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register. + * 0b0000..No adjustment + * 0b0001..+ 0.25% + * 0b0010..+ 0.50% + * 0b0011..+ 0.75% + * 0b0100..+ 1.00% + * 0b0101..+ 1.25% + * 0b0110..+ 1.50% + * 0b0111..+ 1.75% + * 0b1000..- 0.25% + * 0b1001..- 0.50% + * 0b1010..- 0.75% + * 0b1011..- 1.00% + * 0b1100..- 1.25% + * 0b1101..- 1.50% + * 0b1110..- 1.75% + * 0b1111..- 2.00% + */ +#define PMU_REG_CORE_CLR_REG2_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_CLR_REG2_ADJ_SHIFT)) & PMU_REG_CORE_CLR_REG2_ADJ_MASK) #define PMU_REG_CORE_CLR_RAMP_RATE_MASK (0x18000000U) #define PMU_REG_CORE_CLR_RAMP_RATE_SHIFT (27U) +/*! RAMP_RATE + * 0b00..Fast + * 0b01..Medium Fast + * 0b10..Medium Slow + * 0b11..Slow + */ #define PMU_REG_CORE_CLR_RAMP_RATE(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_CLR_RAMP_RATE_SHIFT)) & PMU_REG_CORE_CLR_RAMP_RATE_MASK) #define PMU_REG_CORE_CLR_FET_ODRIVE_MASK (0x20000000U) #define PMU_REG_CORE_CLR_FET_ODRIVE_SHIFT (29U) #define PMU_REG_CORE_CLR_FET_ODRIVE(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_CLR_FET_ODRIVE_SHIFT)) & PMU_REG_CORE_CLR_FET_ODRIVE_MASK) +/*! @} */ /*! @name REG_CORE_TOG - Digital Regulator Core Register */ +/*! @{ */ #define PMU_REG_CORE_TOG_REG0_TARG_MASK (0x1FU) #define PMU_REG_CORE_TOG_REG0_TARG_SHIFT (0U) +/*! REG0_TARG + * 0b00000..Power gated off + * 0b00001..Target core voltage = 0.725V + * 0b00010..Target core voltage = 0.750V + * 0b00011..Target core voltage = 0.775V + * 0b10000..Target core voltage = 1.100V + * 0b11110..Target core voltage = 1.450V + * 0b11111..Power FET switched full on. No regulation. + */ #define PMU_REG_CORE_TOG_REG0_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_TOG_REG0_TARG_SHIFT)) & PMU_REG_CORE_TOG_REG0_TARG_MASK) +#define PMU_REG_CORE_TOG_REG0_ADJ_MASK (0x1E0U) +#define PMU_REG_CORE_TOG_REG0_ADJ_SHIFT (5U) +/*! REG0_ADJ - This bit field defines the adjustment bits to calibrate the target value of Reg0. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register. + * 0b0000..No adjustment + * 0b0001..+ 0.25% + * 0b0010..+ 0.50% + * 0b0011..+ 0.75% + * 0b0100..+ 1.00% + * 0b0101..+ 1.25% + * 0b0110..+ 1.50% + * 0b0111..+ 1.75% + * 0b1000..- 0.25% + * 0b1001..- 0.50% + * 0b1010..- 0.75% + * 0b1011..- 1.00% + * 0b1100..- 1.25% + * 0b1101..- 1.50% + * 0b1110..- 1.75% + * 0b1111..- 2.00% + */ +#define PMU_REG_CORE_TOG_REG0_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_TOG_REG0_ADJ_SHIFT)) & PMU_REG_CORE_TOG_REG0_ADJ_MASK) +#define PMU_REG_CORE_TOG_REG1_TARG_MASK (0x3E00U) +#define PMU_REG_CORE_TOG_REG1_TARG_SHIFT (9U) +/*! REG1_TARG - This bit field defines the target voltage for the vpu/gpu power domain. Single bit increments reflect 25mV core voltage steps. Not all steps will make sense to use either because of input supply limitations or load operation. + * 0b00000..Power gated off + * 0b00001..Target core voltage = 0.725V + * 0b00010..Target core voltage = 0.750V + * 0b00011..Target core voltage = 0.775V + * 0b10000..Target core voltage = 1.100V + * 0b11110..Target core voltage = 1.450V + * 0b11111..Power FET switched full on. No regulation. + */ +#define PMU_REG_CORE_TOG_REG1_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_TOG_REG1_TARG_SHIFT)) & PMU_REG_CORE_TOG_REG1_TARG_MASK) +#define PMU_REG_CORE_TOG_REG1_ADJ_MASK (0x3C000U) +#define PMU_REG_CORE_TOG_REG1_ADJ_SHIFT (14U) +/*! REG1_ADJ - This bit field defines the adjustment bits to calibrate the target value of Reg1. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register. + * 0b0000..No adjustment + * 0b0001..+ 0.25% + * 0b0010..+ 0.50% + * 0b0011..+ 0.75% + * 0b0100..+ 1.00% + * 0b0101..+ 1.25% + * 0b0110..+ 1.50% + * 0b0111..+ 1.75% + * 0b1000..- 0.25% + * 0b1001..- 0.50% + * 0b1010..- 0.75% + * 0b1011..- 1.00% + * 0b1100..- 1.25% + * 0b1101..- 1.50% + * 0b1110..- 1.75% + * 0b1111..- 2.00% + */ +#define PMU_REG_CORE_TOG_REG1_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_TOG_REG1_ADJ_SHIFT)) & PMU_REG_CORE_TOG_REG1_ADJ_MASK) #define PMU_REG_CORE_TOG_REG2_TARG_MASK (0x7C0000U) #define PMU_REG_CORE_TOG_REG2_TARG_SHIFT (18U) +/*! REG2_TARG + * 0b00000..Power gated off + * 0b00001..Target core voltage = 0.725V + * 0b00010..Target core voltage = 0.750V + * 0b00011..Target core voltage = 0.775V + * 0b10000..Target core voltage = 1.100V + * 0b11110..Target core voltage = 1.450V + * 0b11111..Power FET switched full on. No regulation. + */ #define PMU_REG_CORE_TOG_REG2_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_TOG_REG2_TARG_SHIFT)) & PMU_REG_CORE_TOG_REG2_TARG_MASK) +#define PMU_REG_CORE_TOG_REG2_ADJ_MASK (0x7800000U) +#define PMU_REG_CORE_TOG_REG2_ADJ_SHIFT (23U) +/*! REG2_ADJ - This bit field defines the adjustment bits to calibrate the target value of Reg2. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register. + * 0b0000..No adjustment + * 0b0001..+ 0.25% + * 0b0010..+ 0.50% + * 0b0011..+ 0.75% + * 0b0100..+ 1.00% + * 0b0101..+ 1.25% + * 0b0110..+ 1.50% + * 0b0111..+ 1.75% + * 0b1000..- 0.25% + * 0b1001..- 0.50% + * 0b1010..- 0.75% + * 0b1011..- 1.00% + * 0b1100..- 1.25% + * 0b1101..- 1.50% + * 0b1110..- 1.75% + * 0b1111..- 2.00% + */ +#define PMU_REG_CORE_TOG_REG2_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_TOG_REG2_ADJ_SHIFT)) & PMU_REG_CORE_TOG_REG2_ADJ_MASK) #define PMU_REG_CORE_TOG_RAMP_RATE_MASK (0x18000000U) #define PMU_REG_CORE_TOG_RAMP_RATE_SHIFT (27U) +/*! RAMP_RATE + * 0b00..Fast + * 0b01..Medium Fast + * 0b10..Medium Slow + * 0b11..Slow + */ #define PMU_REG_CORE_TOG_RAMP_RATE(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_TOG_RAMP_RATE_SHIFT)) & PMU_REG_CORE_TOG_RAMP_RATE_MASK) #define PMU_REG_CORE_TOG_FET_ODRIVE_MASK (0x20000000U) #define PMU_REG_CORE_TOG_FET_ODRIVE_SHIFT (29U) #define PMU_REG_CORE_TOG_FET_ODRIVE(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_TOG_FET_ODRIVE_SHIFT)) & PMU_REG_CORE_TOG_FET_ODRIVE_MASK) +/*! @} */ /*! @name MISC0 - Miscellaneous Register 0 */ +/*! @{ */ #define PMU_MISC0_REFTOP_PWD_MASK (0x1U) #define PMU_MISC0_REFTOP_PWD_SHIFT (0U) #define PMU_MISC0_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_REFTOP_PWD_SHIFT)) & PMU_MISC0_REFTOP_PWD_MASK) #define PMU_MISC0_REFTOP_SELFBIASOFF_MASK (0x8U) #define PMU_MISC0_REFTOP_SELFBIASOFF_SHIFT (3U) +/*! REFTOP_SELFBIASOFF + * 0b0..Uses coarse bias currents for startup + * 0b1..Uses bandgap-based bias currents for best performance. + */ #define PMU_MISC0_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_REFTOP_SELFBIASOFF_SHIFT)) & PMU_MISC0_REFTOP_SELFBIASOFF_MASK) #define PMU_MISC0_REFTOP_VBGADJ_MASK (0x70U) #define PMU_MISC0_REFTOP_VBGADJ_SHIFT (4U) +/*! REFTOP_VBGADJ + * 0b000..Nominal VBG + * 0b001..VBG+0.78% + * 0b010..VBG+1.56% + * 0b011..VBG+2.34% + * 0b100..VBG-0.78% + * 0b101..VBG-1.56% + * 0b110..VBG-2.34% + * 0b111..VBG-3.12% + */ #define PMU_MISC0_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_REFTOP_VBGADJ_SHIFT)) & PMU_MISC0_REFTOP_VBGADJ_MASK) #define PMU_MISC0_REFTOP_VBGUP_MASK (0x80U) #define PMU_MISC0_REFTOP_VBGUP_SHIFT (7U) #define PMU_MISC0_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_REFTOP_VBGUP_SHIFT)) & PMU_MISC0_REFTOP_VBGUP_MASK) #define PMU_MISC0_STOP_MODE_CONFIG_MASK (0xC00U) #define PMU_MISC0_STOP_MODE_CONFIG_SHIFT (10U) +/*! STOP_MODE_CONFIG + * 0b00..SUSPEND (DSM) + * 0b01..Analog regulators are ON. + * 0b10..STOP (lower power) + * 0b11..STOP (very lower power) + */ #define PMU_MISC0_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_STOP_MODE_CONFIG_SHIFT)) & PMU_MISC0_STOP_MODE_CONFIG_MASK) #define PMU_MISC0_DISCON_HIGH_SNVS_MASK (0x1000U) #define PMU_MISC0_DISCON_HIGH_SNVS_SHIFT (12U) +/*! DISCON_HIGH_SNVS + * 0b0..Turn on the switch + * 0b1..Turn off the switch + */ #define PMU_MISC0_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_DISCON_HIGH_SNVS_SHIFT)) & PMU_MISC0_DISCON_HIGH_SNVS_MASK) #define PMU_MISC0_OSC_I_MASK (0x6000U) #define PMU_MISC0_OSC_I_SHIFT (13U) +/*! OSC_I + * 0b00..Nominal + * 0b01..Decrease current by 12.5% + * 0b10..Decrease current by 25.0% + * 0b11..Decrease current by 37.5% + */ #define PMU_MISC0_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_OSC_I_SHIFT)) & PMU_MISC0_OSC_I_MASK) #define PMU_MISC0_OSC_XTALOK_MASK (0x8000U) #define PMU_MISC0_OSC_XTALOK_SHIFT (15U) @@ -15262,41 +24522,95 @@ typedef struct { #define PMU_MISC0_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_OSC_XTALOK_EN_SHIFT)) & PMU_MISC0_OSC_XTALOK_EN_MASK) #define PMU_MISC0_CLKGATE_CTRL_MASK (0x2000000U) #define PMU_MISC0_CLKGATE_CTRL_SHIFT (25U) +/*! CLKGATE_CTRL + * 0b0..Allow the logic to automatically gate the clock when the XTAL is powered down. + * 0b1..Prevent the logic from ever gating off the clock. + */ #define PMU_MISC0_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLKGATE_CTRL_SHIFT)) & PMU_MISC0_CLKGATE_CTRL_MASK) #define PMU_MISC0_CLKGATE_DELAY_MASK (0x1C000000U) #define PMU_MISC0_CLKGATE_DELAY_SHIFT (26U) +/*! CLKGATE_DELAY + * 0b000..0.5ms + * 0b001..1.0ms + * 0b010..2.0ms + * 0b011..3.0ms + * 0b100..4.0ms + * 0b101..5.0ms + * 0b110..6.0ms + * 0b111..7.0ms + */ #define PMU_MISC0_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLKGATE_DELAY_SHIFT)) & PMU_MISC0_CLKGATE_DELAY_MASK) #define PMU_MISC0_RTC_XTAL_SOURCE_MASK (0x20000000U) #define PMU_MISC0_RTC_XTAL_SOURCE_SHIFT (29U) +/*! RTC_XTAL_SOURCE + * 0b0..Internal ring oscillator + * 0b1..RTC_XTAL + */ #define PMU_MISC0_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_RTC_XTAL_SOURCE_SHIFT)) & PMU_MISC0_RTC_XTAL_SOURCE_MASK) #define PMU_MISC0_XTAL_24M_PWD_MASK (0x40000000U) #define PMU_MISC0_XTAL_24M_PWD_SHIFT (30U) #define PMU_MISC0_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_XTAL_24M_PWD_SHIFT)) & PMU_MISC0_XTAL_24M_PWD_MASK) #define PMU_MISC0_VID_PLL_PREDIV_MASK (0x80000000U) #define PMU_MISC0_VID_PLL_PREDIV_SHIFT (31U) +/*! VID_PLL_PREDIV + * 0b0..Divide by 1 + * 0b1..Divide by 2 + */ #define PMU_MISC0_VID_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_VID_PLL_PREDIV_SHIFT)) & PMU_MISC0_VID_PLL_PREDIV_MASK) +/*! @} */ /*! @name MISC0_SET - Miscellaneous Register 0 */ +/*! @{ */ #define PMU_MISC0_SET_REFTOP_PWD_MASK (0x1U) #define PMU_MISC0_SET_REFTOP_PWD_SHIFT (0U) #define PMU_MISC0_SET_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_REFTOP_PWD_SHIFT)) & PMU_MISC0_SET_REFTOP_PWD_MASK) #define PMU_MISC0_SET_REFTOP_SELFBIASOFF_MASK (0x8U) #define PMU_MISC0_SET_REFTOP_SELFBIASOFF_SHIFT (3U) +/*! REFTOP_SELFBIASOFF + * 0b0..Uses coarse bias currents for startup + * 0b1..Uses bandgap-based bias currents for best performance. + */ #define PMU_MISC0_SET_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_REFTOP_SELFBIASOFF_SHIFT)) & PMU_MISC0_SET_REFTOP_SELFBIASOFF_MASK) #define PMU_MISC0_SET_REFTOP_VBGADJ_MASK (0x70U) #define PMU_MISC0_SET_REFTOP_VBGADJ_SHIFT (4U) +/*! REFTOP_VBGADJ + * 0b000..Nominal VBG + * 0b001..VBG+0.78% + * 0b010..VBG+1.56% + * 0b011..VBG+2.34% + * 0b100..VBG-0.78% + * 0b101..VBG-1.56% + * 0b110..VBG-2.34% + * 0b111..VBG-3.12% + */ #define PMU_MISC0_SET_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_REFTOP_VBGADJ_SHIFT)) & PMU_MISC0_SET_REFTOP_VBGADJ_MASK) #define PMU_MISC0_SET_REFTOP_VBGUP_MASK (0x80U) #define PMU_MISC0_SET_REFTOP_VBGUP_SHIFT (7U) #define PMU_MISC0_SET_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_REFTOP_VBGUP_SHIFT)) & PMU_MISC0_SET_REFTOP_VBGUP_MASK) #define PMU_MISC0_SET_STOP_MODE_CONFIG_MASK (0xC00U) #define PMU_MISC0_SET_STOP_MODE_CONFIG_SHIFT (10U) +/*! STOP_MODE_CONFIG + * 0b00..SUSPEND (DSM) + * 0b01..Analog regulators are ON. + * 0b10..STOP (lower power) + * 0b11..STOP (very lower power) + */ #define PMU_MISC0_SET_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_STOP_MODE_CONFIG_SHIFT)) & PMU_MISC0_SET_STOP_MODE_CONFIG_MASK) #define PMU_MISC0_SET_DISCON_HIGH_SNVS_MASK (0x1000U) #define PMU_MISC0_SET_DISCON_HIGH_SNVS_SHIFT (12U) +/*! DISCON_HIGH_SNVS + * 0b0..Turn on the switch + * 0b1..Turn off the switch + */ #define PMU_MISC0_SET_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_DISCON_HIGH_SNVS_SHIFT)) & PMU_MISC0_SET_DISCON_HIGH_SNVS_MASK) #define PMU_MISC0_SET_OSC_I_MASK (0x6000U) #define PMU_MISC0_SET_OSC_I_SHIFT (13U) +/*! OSC_I + * 0b00..Nominal + * 0b01..Decrease current by 12.5% + * 0b10..Decrease current by 25.0% + * 0b11..Decrease current by 37.5% + */ #define PMU_MISC0_SET_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_OSC_I_SHIFT)) & PMU_MISC0_SET_OSC_I_MASK) #define PMU_MISC0_SET_OSC_XTALOK_MASK (0x8000U) #define PMU_MISC0_SET_OSC_XTALOK_SHIFT (15U) @@ -15306,41 +24620,95 @@ typedef struct { #define PMU_MISC0_SET_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_OSC_XTALOK_EN_SHIFT)) & PMU_MISC0_SET_OSC_XTALOK_EN_MASK) #define PMU_MISC0_SET_CLKGATE_CTRL_MASK (0x2000000U) #define PMU_MISC0_SET_CLKGATE_CTRL_SHIFT (25U) +/*! CLKGATE_CTRL + * 0b0..Allow the logic to automatically gate the clock when the XTAL is powered down. + * 0b1..Prevent the logic from ever gating off the clock. + */ #define PMU_MISC0_SET_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_CLKGATE_CTRL_SHIFT)) & PMU_MISC0_SET_CLKGATE_CTRL_MASK) #define PMU_MISC0_SET_CLKGATE_DELAY_MASK (0x1C000000U) #define PMU_MISC0_SET_CLKGATE_DELAY_SHIFT (26U) +/*! CLKGATE_DELAY + * 0b000..0.5ms + * 0b001..1.0ms + * 0b010..2.0ms + * 0b011..3.0ms + * 0b100..4.0ms + * 0b101..5.0ms + * 0b110..6.0ms + * 0b111..7.0ms + */ #define PMU_MISC0_SET_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_CLKGATE_DELAY_SHIFT)) & PMU_MISC0_SET_CLKGATE_DELAY_MASK) #define PMU_MISC0_SET_RTC_XTAL_SOURCE_MASK (0x20000000U) #define PMU_MISC0_SET_RTC_XTAL_SOURCE_SHIFT (29U) +/*! RTC_XTAL_SOURCE + * 0b0..Internal ring oscillator + * 0b1..RTC_XTAL + */ #define PMU_MISC0_SET_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_RTC_XTAL_SOURCE_SHIFT)) & PMU_MISC0_SET_RTC_XTAL_SOURCE_MASK) #define PMU_MISC0_SET_XTAL_24M_PWD_MASK (0x40000000U) #define PMU_MISC0_SET_XTAL_24M_PWD_SHIFT (30U) #define PMU_MISC0_SET_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_XTAL_24M_PWD_SHIFT)) & PMU_MISC0_SET_XTAL_24M_PWD_MASK) #define PMU_MISC0_SET_VID_PLL_PREDIV_MASK (0x80000000U) #define PMU_MISC0_SET_VID_PLL_PREDIV_SHIFT (31U) +/*! VID_PLL_PREDIV + * 0b0..Divide by 1 + * 0b1..Divide by 2 + */ #define PMU_MISC0_SET_VID_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_VID_PLL_PREDIV_SHIFT)) & PMU_MISC0_SET_VID_PLL_PREDIV_MASK) +/*! @} */ /*! @name MISC0_CLR - Miscellaneous Register 0 */ +/*! @{ */ #define PMU_MISC0_CLR_REFTOP_PWD_MASK (0x1U) #define PMU_MISC0_CLR_REFTOP_PWD_SHIFT (0U) #define PMU_MISC0_CLR_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_REFTOP_PWD_SHIFT)) & PMU_MISC0_CLR_REFTOP_PWD_MASK) #define PMU_MISC0_CLR_REFTOP_SELFBIASOFF_MASK (0x8U) #define PMU_MISC0_CLR_REFTOP_SELFBIASOFF_SHIFT (3U) +/*! REFTOP_SELFBIASOFF + * 0b0..Uses coarse bias currents for startup + * 0b1..Uses bandgap-based bias currents for best performance. + */ #define PMU_MISC0_CLR_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_REFTOP_SELFBIASOFF_SHIFT)) & PMU_MISC0_CLR_REFTOP_SELFBIASOFF_MASK) #define PMU_MISC0_CLR_REFTOP_VBGADJ_MASK (0x70U) #define PMU_MISC0_CLR_REFTOP_VBGADJ_SHIFT (4U) +/*! REFTOP_VBGADJ + * 0b000..Nominal VBG + * 0b001..VBG+0.78% + * 0b010..VBG+1.56% + * 0b011..VBG+2.34% + * 0b100..VBG-0.78% + * 0b101..VBG-1.56% + * 0b110..VBG-2.34% + * 0b111..VBG-3.12% + */ #define PMU_MISC0_CLR_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_REFTOP_VBGADJ_SHIFT)) & PMU_MISC0_CLR_REFTOP_VBGADJ_MASK) #define PMU_MISC0_CLR_REFTOP_VBGUP_MASK (0x80U) #define PMU_MISC0_CLR_REFTOP_VBGUP_SHIFT (7U) #define PMU_MISC0_CLR_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_REFTOP_VBGUP_SHIFT)) & PMU_MISC0_CLR_REFTOP_VBGUP_MASK) #define PMU_MISC0_CLR_STOP_MODE_CONFIG_MASK (0xC00U) #define PMU_MISC0_CLR_STOP_MODE_CONFIG_SHIFT (10U) +/*! STOP_MODE_CONFIG + * 0b00..SUSPEND (DSM) + * 0b01..Analog regulators are ON. + * 0b10..STOP (lower power) + * 0b11..STOP (very lower power) + */ #define PMU_MISC0_CLR_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_STOP_MODE_CONFIG_SHIFT)) & PMU_MISC0_CLR_STOP_MODE_CONFIG_MASK) #define PMU_MISC0_CLR_DISCON_HIGH_SNVS_MASK (0x1000U) #define PMU_MISC0_CLR_DISCON_HIGH_SNVS_SHIFT (12U) +/*! DISCON_HIGH_SNVS + * 0b0..Turn on the switch + * 0b1..Turn off the switch + */ #define PMU_MISC0_CLR_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_DISCON_HIGH_SNVS_SHIFT)) & PMU_MISC0_CLR_DISCON_HIGH_SNVS_MASK) #define PMU_MISC0_CLR_OSC_I_MASK (0x6000U) #define PMU_MISC0_CLR_OSC_I_SHIFT (13U) +/*! OSC_I + * 0b00..Nominal + * 0b01..Decrease current by 12.5% + * 0b10..Decrease current by 25.0% + * 0b11..Decrease current by 37.5% + */ #define PMU_MISC0_CLR_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_OSC_I_SHIFT)) & PMU_MISC0_CLR_OSC_I_MASK) #define PMU_MISC0_CLR_OSC_XTALOK_MASK (0x8000U) #define PMU_MISC0_CLR_OSC_XTALOK_SHIFT (15U) @@ -15350,41 +24718,95 @@ typedef struct { #define PMU_MISC0_CLR_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_OSC_XTALOK_EN_SHIFT)) & PMU_MISC0_CLR_OSC_XTALOK_EN_MASK) #define PMU_MISC0_CLR_CLKGATE_CTRL_MASK (0x2000000U) #define PMU_MISC0_CLR_CLKGATE_CTRL_SHIFT (25U) +/*! CLKGATE_CTRL + * 0b0..Allow the logic to automatically gate the clock when the XTAL is powered down. + * 0b1..Prevent the logic from ever gating off the clock. + */ #define PMU_MISC0_CLR_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_CLKGATE_CTRL_SHIFT)) & PMU_MISC0_CLR_CLKGATE_CTRL_MASK) #define PMU_MISC0_CLR_CLKGATE_DELAY_MASK (0x1C000000U) #define PMU_MISC0_CLR_CLKGATE_DELAY_SHIFT (26U) +/*! CLKGATE_DELAY + * 0b000..0.5ms + * 0b001..1.0ms + * 0b010..2.0ms + * 0b011..3.0ms + * 0b100..4.0ms + * 0b101..5.0ms + * 0b110..6.0ms + * 0b111..7.0ms + */ #define PMU_MISC0_CLR_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_CLKGATE_DELAY_SHIFT)) & PMU_MISC0_CLR_CLKGATE_DELAY_MASK) #define PMU_MISC0_CLR_RTC_XTAL_SOURCE_MASK (0x20000000U) #define PMU_MISC0_CLR_RTC_XTAL_SOURCE_SHIFT (29U) +/*! RTC_XTAL_SOURCE + * 0b0..Internal ring oscillator + * 0b1..RTC_XTAL + */ #define PMU_MISC0_CLR_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_RTC_XTAL_SOURCE_SHIFT)) & PMU_MISC0_CLR_RTC_XTAL_SOURCE_MASK) #define PMU_MISC0_CLR_XTAL_24M_PWD_MASK (0x40000000U) #define PMU_MISC0_CLR_XTAL_24M_PWD_SHIFT (30U) #define PMU_MISC0_CLR_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_XTAL_24M_PWD_SHIFT)) & PMU_MISC0_CLR_XTAL_24M_PWD_MASK) #define PMU_MISC0_CLR_VID_PLL_PREDIV_MASK (0x80000000U) #define PMU_MISC0_CLR_VID_PLL_PREDIV_SHIFT (31U) +/*! VID_PLL_PREDIV + * 0b0..Divide by 1 + * 0b1..Divide by 2 + */ #define PMU_MISC0_CLR_VID_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_VID_PLL_PREDIV_SHIFT)) & PMU_MISC0_CLR_VID_PLL_PREDIV_MASK) +/*! @} */ /*! @name MISC0_TOG - Miscellaneous Register 0 */ +/*! @{ */ #define PMU_MISC0_TOG_REFTOP_PWD_MASK (0x1U) #define PMU_MISC0_TOG_REFTOP_PWD_SHIFT (0U) #define PMU_MISC0_TOG_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_REFTOP_PWD_SHIFT)) & PMU_MISC0_TOG_REFTOP_PWD_MASK) #define PMU_MISC0_TOG_REFTOP_SELFBIASOFF_MASK (0x8U) #define PMU_MISC0_TOG_REFTOP_SELFBIASOFF_SHIFT (3U) +/*! REFTOP_SELFBIASOFF + * 0b0..Uses coarse bias currents for startup + * 0b1..Uses bandgap-based bias currents for best performance. + */ #define PMU_MISC0_TOG_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_REFTOP_SELFBIASOFF_SHIFT)) & PMU_MISC0_TOG_REFTOP_SELFBIASOFF_MASK) #define PMU_MISC0_TOG_REFTOP_VBGADJ_MASK (0x70U) #define PMU_MISC0_TOG_REFTOP_VBGADJ_SHIFT (4U) +/*! REFTOP_VBGADJ + * 0b000..Nominal VBG + * 0b001..VBG+0.78% + * 0b010..VBG+1.56% + * 0b011..VBG+2.34% + * 0b100..VBG-0.78% + * 0b101..VBG-1.56% + * 0b110..VBG-2.34% + * 0b111..VBG-3.12% + */ #define PMU_MISC0_TOG_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_REFTOP_VBGADJ_SHIFT)) & PMU_MISC0_TOG_REFTOP_VBGADJ_MASK) #define PMU_MISC0_TOG_REFTOP_VBGUP_MASK (0x80U) #define PMU_MISC0_TOG_REFTOP_VBGUP_SHIFT (7U) #define PMU_MISC0_TOG_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_REFTOP_VBGUP_SHIFT)) & PMU_MISC0_TOG_REFTOP_VBGUP_MASK) #define PMU_MISC0_TOG_STOP_MODE_CONFIG_MASK (0xC00U) #define PMU_MISC0_TOG_STOP_MODE_CONFIG_SHIFT (10U) +/*! STOP_MODE_CONFIG + * 0b00..SUSPEND (DSM) + * 0b01..Analog regulators are ON. + * 0b10..STOP (lower power) + * 0b11..STOP (very lower power) + */ #define PMU_MISC0_TOG_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_STOP_MODE_CONFIG_SHIFT)) & PMU_MISC0_TOG_STOP_MODE_CONFIG_MASK) #define PMU_MISC0_TOG_DISCON_HIGH_SNVS_MASK (0x1000U) #define PMU_MISC0_TOG_DISCON_HIGH_SNVS_SHIFT (12U) +/*! DISCON_HIGH_SNVS + * 0b0..Turn on the switch + * 0b1..Turn off the switch + */ #define PMU_MISC0_TOG_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_DISCON_HIGH_SNVS_SHIFT)) & PMU_MISC0_TOG_DISCON_HIGH_SNVS_MASK) #define PMU_MISC0_TOG_OSC_I_MASK (0x6000U) #define PMU_MISC0_TOG_OSC_I_SHIFT (13U) +/*! OSC_I + * 0b00..Nominal + * 0b01..Decrease current by 12.5% + * 0b10..Decrease current by 25.0% + * 0b11..Decrease current by 37.5% + */ #define PMU_MISC0_TOG_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_OSC_I_SHIFT)) & PMU_MISC0_TOG_OSC_I_MASK) #define PMU_MISC0_TOG_OSC_XTALOK_MASK (0x8000U) #define PMU_MISC0_TOG_OSC_XTALOK_SHIFT (15U) @@ -15394,30 +24816,104 @@ typedef struct { #define PMU_MISC0_TOG_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_OSC_XTALOK_EN_SHIFT)) & PMU_MISC0_TOG_OSC_XTALOK_EN_MASK) #define PMU_MISC0_TOG_CLKGATE_CTRL_MASK (0x2000000U) #define PMU_MISC0_TOG_CLKGATE_CTRL_SHIFT (25U) +/*! CLKGATE_CTRL + * 0b0..Allow the logic to automatically gate the clock when the XTAL is powered down. + * 0b1..Prevent the logic from ever gating off the clock. + */ #define PMU_MISC0_TOG_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_CLKGATE_CTRL_SHIFT)) & PMU_MISC0_TOG_CLKGATE_CTRL_MASK) #define PMU_MISC0_TOG_CLKGATE_DELAY_MASK (0x1C000000U) #define PMU_MISC0_TOG_CLKGATE_DELAY_SHIFT (26U) +/*! CLKGATE_DELAY + * 0b000..0.5ms + * 0b001..1.0ms + * 0b010..2.0ms + * 0b011..3.0ms + * 0b100..4.0ms + * 0b101..5.0ms + * 0b110..6.0ms + * 0b111..7.0ms + */ #define PMU_MISC0_TOG_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_CLKGATE_DELAY_SHIFT)) & PMU_MISC0_TOG_CLKGATE_DELAY_MASK) #define PMU_MISC0_TOG_RTC_XTAL_SOURCE_MASK (0x20000000U) #define PMU_MISC0_TOG_RTC_XTAL_SOURCE_SHIFT (29U) +/*! RTC_XTAL_SOURCE + * 0b0..Internal ring oscillator + * 0b1..RTC_XTAL + */ #define PMU_MISC0_TOG_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_RTC_XTAL_SOURCE_SHIFT)) & PMU_MISC0_TOG_RTC_XTAL_SOURCE_MASK) #define PMU_MISC0_TOG_XTAL_24M_PWD_MASK (0x40000000U) #define PMU_MISC0_TOG_XTAL_24M_PWD_SHIFT (30U) #define PMU_MISC0_TOG_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_XTAL_24M_PWD_SHIFT)) & PMU_MISC0_TOG_XTAL_24M_PWD_MASK) #define PMU_MISC0_TOG_VID_PLL_PREDIV_MASK (0x80000000U) #define PMU_MISC0_TOG_VID_PLL_PREDIV_SHIFT (31U) +/*! VID_PLL_PREDIV + * 0b0..Divide by 1 + * 0b1..Divide by 2 + */ #define PMU_MISC0_TOG_VID_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_VID_PLL_PREDIV_SHIFT)) & PMU_MISC0_TOG_VID_PLL_PREDIV_MASK) +/*! @} */ /*! @name MISC1 - Miscellaneous Register 1 */ +/*! @{ */ #define PMU_MISC1_LVDS1_CLK_SEL_MASK (0x1FU) #define PMU_MISC1_LVDS1_CLK_SEL_SHIFT (0U) +/*! LVDS1_CLK_SEL + * 0b00000..Arm PLL + * 0b00001..System PLL + * 0b00010..ref_pfd4_clk == pll2_pfd0_clk + * 0b00011..ref_pfd5_clk == pll2_pfd1_clk + * 0b00100..ref_pfd6_clk == pll2_pfd2_clk + * 0b00101..ref_pfd7_clk == pll2_pfd3_clk + * 0b00110..Audio PLL + * 0b00111..Video PLL + * 0b01001..ethernet ref clock (ENET_PLL) + * 0b01100..USB1 PLL clock + * 0b01101..USB2 PLL clock + * 0b01110..ref_pfd0_clk == pll3_pfd0_clk + * 0b01111..ref_pfd1_clk == pll3_pfd1_clk + * 0b10000..ref_pfd2_clk == pll3_pfd2_clk + * 0b10001..ref_pfd3_clk == pll3_pfd3_clk + * 0b10010..xtal (24M) + */ #define PMU_MISC1_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_LVDS1_CLK_SEL_SHIFT)) & PMU_MISC1_LVDS1_CLK_SEL_MASK) +#define PMU_MISC1_LVDS2_CLK_SEL_MASK (0x3E0U) +#define PMU_MISC1_LVDS2_CLK_SEL_SHIFT (5U) +/*! LVDS2_CLK_SEL + * 0b00000..Arm PLL + * 0b00001..System PLL + * 0b00010..ref_pfd4_clk == pll2_pfd0_clk + * 0b00011..ref_pfd5_clk == pll2_pfd1_clk + * 0b00100..ref_pfd6_clk == pll2_pfd2_clk + * 0b00101..ref_pfd7_clk == pll2_pfd3_clk + * 0b00110..Audio PLL + * 0b00111..Video PLL + * 0b01000..MLB PLL + * 0b01001..ethernet ref clock (ENET_PLL) + * 0b01010..PCIe ref clock (125M) + * 0b01011..SATA ref clock (100M) + * 0b01100..USB1 PLL clock + * 0b01101..USB2 PLL clock + * 0b01110..ref_pfd0_clk == pll3_pfd0_clk + * 0b01111..ref_pfd1_clk == pll3_pfd1_clk + * 0b10000..ref_pfd2_clk == pll3_pfd2_clk + * 0b10001..ref_pfd3_clk == pll3_pfd3_clk + * 0b10010..xtal (24M) + * 0b10011..LVDS1 (loopback) + * 0b10100..LVDS2 (not useful) + */ +#define PMU_MISC1_LVDS2_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_LVDS2_CLK_SEL_SHIFT)) & PMU_MISC1_LVDS2_CLK_SEL_MASK) #define PMU_MISC1_LVDSCLK1_OBEN_MASK (0x400U) #define PMU_MISC1_LVDSCLK1_OBEN_SHIFT (10U) #define PMU_MISC1_LVDSCLK1_OBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_LVDSCLK1_OBEN_SHIFT)) & PMU_MISC1_LVDSCLK1_OBEN_MASK) +#define PMU_MISC1_LVDSCLK2_OBEN_MASK (0x800U) +#define PMU_MISC1_LVDSCLK2_OBEN_SHIFT (11U) +#define PMU_MISC1_LVDSCLK2_OBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_LVDSCLK2_OBEN_SHIFT)) & PMU_MISC1_LVDSCLK2_OBEN_MASK) #define PMU_MISC1_LVDSCLK1_IBEN_MASK (0x1000U) #define PMU_MISC1_LVDSCLK1_IBEN_SHIFT (12U) #define PMU_MISC1_LVDSCLK1_IBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_LVDSCLK1_IBEN_SHIFT)) & PMU_MISC1_LVDSCLK1_IBEN_MASK) +#define PMU_MISC1_LVDSCLK2_IBEN_MASK (0x2000U) +#define PMU_MISC1_LVDSCLK2_IBEN_SHIFT (13U) +#define PMU_MISC1_LVDSCLK2_IBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_LVDSCLK2_IBEN_SHIFT)) & PMU_MISC1_LVDSCLK2_IBEN_MASK) #define PMU_MISC1_PFD_480_AUTOGATE_EN_MASK (0x10000U) #define PMU_MISC1_PFD_480_AUTOGATE_EN_SHIFT (16U) #define PMU_MISC1_PFD_480_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_PFD_480_AUTOGATE_EN_SHIFT)) & PMU_MISC1_PFD_480_AUTOGATE_EN_MASK) @@ -15439,17 +24935,69 @@ typedef struct { #define PMU_MISC1_IRQ_DIG_BO_MASK (0x80000000U) #define PMU_MISC1_IRQ_DIG_BO_SHIFT (31U) #define PMU_MISC1_IRQ_DIG_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_IRQ_DIG_BO_SHIFT)) & PMU_MISC1_IRQ_DIG_BO_MASK) +/*! @} */ /*! @name MISC1_SET - Miscellaneous Register 1 */ +/*! @{ */ #define PMU_MISC1_SET_LVDS1_CLK_SEL_MASK (0x1FU) #define PMU_MISC1_SET_LVDS1_CLK_SEL_SHIFT (0U) +/*! LVDS1_CLK_SEL + * 0b00000..Arm PLL + * 0b00001..System PLL + * 0b00010..ref_pfd4_clk == pll2_pfd0_clk + * 0b00011..ref_pfd5_clk == pll2_pfd1_clk + * 0b00100..ref_pfd6_clk == pll2_pfd2_clk + * 0b00101..ref_pfd7_clk == pll2_pfd3_clk + * 0b00110..Audio PLL + * 0b00111..Video PLL + * 0b01001..ethernet ref clock (ENET_PLL) + * 0b01100..USB1 PLL clock + * 0b01101..USB2 PLL clock + * 0b01110..ref_pfd0_clk == pll3_pfd0_clk + * 0b01111..ref_pfd1_clk == pll3_pfd1_clk + * 0b10000..ref_pfd2_clk == pll3_pfd2_clk + * 0b10001..ref_pfd3_clk == pll3_pfd3_clk + * 0b10010..xtal (24M) + */ #define PMU_MISC1_SET_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_LVDS1_CLK_SEL_SHIFT)) & PMU_MISC1_SET_LVDS1_CLK_SEL_MASK) +#define PMU_MISC1_SET_LVDS2_CLK_SEL_MASK (0x3E0U) +#define PMU_MISC1_SET_LVDS2_CLK_SEL_SHIFT (5U) +/*! LVDS2_CLK_SEL + * 0b00000..Arm PLL + * 0b00001..System PLL + * 0b00010..ref_pfd4_clk == pll2_pfd0_clk + * 0b00011..ref_pfd5_clk == pll2_pfd1_clk + * 0b00100..ref_pfd6_clk == pll2_pfd2_clk + * 0b00101..ref_pfd7_clk == pll2_pfd3_clk + * 0b00110..Audio PLL + * 0b00111..Video PLL + * 0b01000..MLB PLL + * 0b01001..ethernet ref clock (ENET_PLL) + * 0b01010..PCIe ref clock (125M) + * 0b01011..SATA ref clock (100M) + * 0b01100..USB1 PLL clock + * 0b01101..USB2 PLL clock + * 0b01110..ref_pfd0_clk == pll3_pfd0_clk + * 0b01111..ref_pfd1_clk == pll3_pfd1_clk + * 0b10000..ref_pfd2_clk == pll3_pfd2_clk + * 0b10001..ref_pfd3_clk == pll3_pfd3_clk + * 0b10010..xtal (24M) + * 0b10011..LVDS1 (loopback) + * 0b10100..LVDS2 (not useful) + */ +#define PMU_MISC1_SET_LVDS2_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_LVDS2_CLK_SEL_SHIFT)) & PMU_MISC1_SET_LVDS2_CLK_SEL_MASK) #define PMU_MISC1_SET_LVDSCLK1_OBEN_MASK (0x400U) #define PMU_MISC1_SET_LVDSCLK1_OBEN_SHIFT (10U) #define PMU_MISC1_SET_LVDSCLK1_OBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_LVDSCLK1_OBEN_SHIFT)) & PMU_MISC1_SET_LVDSCLK1_OBEN_MASK) +#define PMU_MISC1_SET_LVDSCLK2_OBEN_MASK (0x800U) +#define PMU_MISC1_SET_LVDSCLK2_OBEN_SHIFT (11U) +#define PMU_MISC1_SET_LVDSCLK2_OBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_LVDSCLK2_OBEN_SHIFT)) & PMU_MISC1_SET_LVDSCLK2_OBEN_MASK) #define PMU_MISC1_SET_LVDSCLK1_IBEN_MASK (0x1000U) #define PMU_MISC1_SET_LVDSCLK1_IBEN_SHIFT (12U) #define PMU_MISC1_SET_LVDSCLK1_IBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_LVDSCLK1_IBEN_SHIFT)) & PMU_MISC1_SET_LVDSCLK1_IBEN_MASK) +#define PMU_MISC1_SET_LVDSCLK2_IBEN_MASK (0x2000U) +#define PMU_MISC1_SET_LVDSCLK2_IBEN_SHIFT (13U) +#define PMU_MISC1_SET_LVDSCLK2_IBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_LVDSCLK2_IBEN_SHIFT)) & PMU_MISC1_SET_LVDSCLK2_IBEN_MASK) #define PMU_MISC1_SET_PFD_480_AUTOGATE_EN_MASK (0x10000U) #define PMU_MISC1_SET_PFD_480_AUTOGATE_EN_SHIFT (16U) #define PMU_MISC1_SET_PFD_480_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_PFD_480_AUTOGATE_EN_SHIFT)) & PMU_MISC1_SET_PFD_480_AUTOGATE_EN_MASK) @@ -15471,17 +25019,69 @@ typedef struct { #define PMU_MISC1_SET_IRQ_DIG_BO_MASK (0x80000000U) #define PMU_MISC1_SET_IRQ_DIG_BO_SHIFT (31U) #define PMU_MISC1_SET_IRQ_DIG_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_IRQ_DIG_BO_SHIFT)) & PMU_MISC1_SET_IRQ_DIG_BO_MASK) +/*! @} */ /*! @name MISC1_CLR - Miscellaneous Register 1 */ +/*! @{ */ #define PMU_MISC1_CLR_LVDS1_CLK_SEL_MASK (0x1FU) #define PMU_MISC1_CLR_LVDS1_CLK_SEL_SHIFT (0U) +/*! LVDS1_CLK_SEL + * 0b00000..Arm PLL + * 0b00001..System PLL + * 0b00010..ref_pfd4_clk == pll2_pfd0_clk + * 0b00011..ref_pfd5_clk == pll2_pfd1_clk + * 0b00100..ref_pfd6_clk == pll2_pfd2_clk + * 0b00101..ref_pfd7_clk == pll2_pfd3_clk + * 0b00110..Audio PLL + * 0b00111..Video PLL + * 0b01001..ethernet ref clock (ENET_PLL) + * 0b01100..USB1 PLL clock + * 0b01101..USB2 PLL clock + * 0b01110..ref_pfd0_clk == pll3_pfd0_clk + * 0b01111..ref_pfd1_clk == pll3_pfd1_clk + * 0b10000..ref_pfd2_clk == pll3_pfd2_clk + * 0b10001..ref_pfd3_clk == pll3_pfd3_clk + * 0b10010..xtal (24M) + */ #define PMU_MISC1_CLR_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_LVDS1_CLK_SEL_SHIFT)) & PMU_MISC1_CLR_LVDS1_CLK_SEL_MASK) +#define PMU_MISC1_CLR_LVDS2_CLK_SEL_MASK (0x3E0U) +#define PMU_MISC1_CLR_LVDS2_CLK_SEL_SHIFT (5U) +/*! LVDS2_CLK_SEL + * 0b00000..Arm PLL + * 0b00001..System PLL + * 0b00010..ref_pfd4_clk == pll2_pfd0_clk + * 0b00011..ref_pfd5_clk == pll2_pfd1_clk + * 0b00100..ref_pfd6_clk == pll2_pfd2_clk + * 0b00101..ref_pfd7_clk == pll2_pfd3_clk + * 0b00110..Audio PLL + * 0b00111..Video PLL + * 0b01000..MLB PLL + * 0b01001..ethernet ref clock (ENET_PLL) + * 0b01010..PCIe ref clock (125M) + * 0b01011..SATA ref clock (100M) + * 0b01100..USB1 PLL clock + * 0b01101..USB2 PLL clock + * 0b01110..ref_pfd0_clk == pll3_pfd0_clk + * 0b01111..ref_pfd1_clk == pll3_pfd1_clk + * 0b10000..ref_pfd2_clk == pll3_pfd2_clk + * 0b10001..ref_pfd3_clk == pll3_pfd3_clk + * 0b10010..xtal (24M) + * 0b10011..LVDS1 (loopback) + * 0b10100..LVDS2 (not useful) + */ +#define PMU_MISC1_CLR_LVDS2_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_LVDS2_CLK_SEL_SHIFT)) & PMU_MISC1_CLR_LVDS2_CLK_SEL_MASK) #define PMU_MISC1_CLR_LVDSCLK1_OBEN_MASK (0x400U) #define PMU_MISC1_CLR_LVDSCLK1_OBEN_SHIFT (10U) #define PMU_MISC1_CLR_LVDSCLK1_OBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_LVDSCLK1_OBEN_SHIFT)) & PMU_MISC1_CLR_LVDSCLK1_OBEN_MASK) +#define PMU_MISC1_CLR_LVDSCLK2_OBEN_MASK (0x800U) +#define PMU_MISC1_CLR_LVDSCLK2_OBEN_SHIFT (11U) +#define PMU_MISC1_CLR_LVDSCLK2_OBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_LVDSCLK2_OBEN_SHIFT)) & PMU_MISC1_CLR_LVDSCLK2_OBEN_MASK) #define PMU_MISC1_CLR_LVDSCLK1_IBEN_MASK (0x1000U) #define PMU_MISC1_CLR_LVDSCLK1_IBEN_SHIFT (12U) #define PMU_MISC1_CLR_LVDSCLK1_IBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_LVDSCLK1_IBEN_SHIFT)) & PMU_MISC1_CLR_LVDSCLK1_IBEN_MASK) +#define PMU_MISC1_CLR_LVDSCLK2_IBEN_MASK (0x2000U) +#define PMU_MISC1_CLR_LVDSCLK2_IBEN_SHIFT (13U) +#define PMU_MISC1_CLR_LVDSCLK2_IBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_LVDSCLK2_IBEN_SHIFT)) & PMU_MISC1_CLR_LVDSCLK2_IBEN_MASK) #define PMU_MISC1_CLR_PFD_480_AUTOGATE_EN_MASK (0x10000U) #define PMU_MISC1_CLR_PFD_480_AUTOGATE_EN_SHIFT (16U) #define PMU_MISC1_CLR_PFD_480_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_PFD_480_AUTOGATE_EN_SHIFT)) & PMU_MISC1_CLR_PFD_480_AUTOGATE_EN_MASK) @@ -15503,17 +25103,69 @@ typedef struct { #define PMU_MISC1_CLR_IRQ_DIG_BO_MASK (0x80000000U) #define PMU_MISC1_CLR_IRQ_DIG_BO_SHIFT (31U) #define PMU_MISC1_CLR_IRQ_DIG_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_IRQ_DIG_BO_SHIFT)) & PMU_MISC1_CLR_IRQ_DIG_BO_MASK) +/*! @} */ /*! @name MISC1_TOG - Miscellaneous Register 1 */ +/*! @{ */ #define PMU_MISC1_TOG_LVDS1_CLK_SEL_MASK (0x1FU) #define PMU_MISC1_TOG_LVDS1_CLK_SEL_SHIFT (0U) +/*! LVDS1_CLK_SEL + * 0b00000..Arm PLL + * 0b00001..System PLL + * 0b00010..ref_pfd4_clk == pll2_pfd0_clk + * 0b00011..ref_pfd5_clk == pll2_pfd1_clk + * 0b00100..ref_pfd6_clk == pll2_pfd2_clk + * 0b00101..ref_pfd7_clk == pll2_pfd3_clk + * 0b00110..Audio PLL + * 0b00111..Video PLL + * 0b01001..ethernet ref clock (ENET_PLL) + * 0b01100..USB1 PLL clock + * 0b01101..USB2 PLL clock + * 0b01110..ref_pfd0_clk == pll3_pfd0_clk + * 0b01111..ref_pfd1_clk == pll3_pfd1_clk + * 0b10000..ref_pfd2_clk == pll3_pfd2_clk + * 0b10001..ref_pfd3_clk == pll3_pfd3_clk + * 0b10010..xtal (24M) + */ #define PMU_MISC1_TOG_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_LVDS1_CLK_SEL_SHIFT)) & PMU_MISC1_TOG_LVDS1_CLK_SEL_MASK) +#define PMU_MISC1_TOG_LVDS2_CLK_SEL_MASK (0x3E0U) +#define PMU_MISC1_TOG_LVDS2_CLK_SEL_SHIFT (5U) +/*! LVDS2_CLK_SEL + * 0b00000..Arm PLL + * 0b00001..System PLL + * 0b00010..ref_pfd4_clk == pll2_pfd0_clk + * 0b00011..ref_pfd5_clk == pll2_pfd1_clk + * 0b00100..ref_pfd6_clk == pll2_pfd2_clk + * 0b00101..ref_pfd7_clk == pll2_pfd3_clk + * 0b00110..Audio PLL + * 0b00111..Video PLL + * 0b01000..MLB PLL + * 0b01001..ethernet ref clock (ENET_PLL) + * 0b01010..PCIe ref clock (125M) + * 0b01011..SATA ref clock (100M) + * 0b01100..USB1 PLL clock + * 0b01101..USB2 PLL clock + * 0b01110..ref_pfd0_clk == pll3_pfd0_clk + * 0b01111..ref_pfd1_clk == pll3_pfd1_clk + * 0b10000..ref_pfd2_clk == pll3_pfd2_clk + * 0b10001..ref_pfd3_clk == pll3_pfd3_clk + * 0b10010..xtal (24M) + * 0b10011..LVDS1 (loopback) + * 0b10100..LVDS2 (not useful) + */ +#define PMU_MISC1_TOG_LVDS2_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_LVDS2_CLK_SEL_SHIFT)) & PMU_MISC1_TOG_LVDS2_CLK_SEL_MASK) #define PMU_MISC1_TOG_LVDSCLK1_OBEN_MASK (0x400U) #define PMU_MISC1_TOG_LVDSCLK1_OBEN_SHIFT (10U) #define PMU_MISC1_TOG_LVDSCLK1_OBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_LVDSCLK1_OBEN_SHIFT)) & PMU_MISC1_TOG_LVDSCLK1_OBEN_MASK) +#define PMU_MISC1_TOG_LVDSCLK2_OBEN_MASK (0x800U) +#define PMU_MISC1_TOG_LVDSCLK2_OBEN_SHIFT (11U) +#define PMU_MISC1_TOG_LVDSCLK2_OBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_LVDSCLK2_OBEN_SHIFT)) & PMU_MISC1_TOG_LVDSCLK2_OBEN_MASK) #define PMU_MISC1_TOG_LVDSCLK1_IBEN_MASK (0x1000U) #define PMU_MISC1_TOG_LVDSCLK1_IBEN_SHIFT (12U) #define PMU_MISC1_TOG_LVDSCLK1_IBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_LVDSCLK1_IBEN_SHIFT)) & PMU_MISC1_TOG_LVDSCLK1_IBEN_MASK) +#define PMU_MISC1_TOG_LVDSCLK2_IBEN_MASK (0x2000U) +#define PMU_MISC1_TOG_LVDSCLK2_IBEN_SHIFT (13U) +#define PMU_MISC1_TOG_LVDSCLK2_IBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_LVDSCLK2_IBEN_SHIFT)) & PMU_MISC1_TOG_LVDSCLK2_IBEN_MASK) #define PMU_MISC1_TOG_PFD_480_AUTOGATE_EN_MASK (0x10000U) #define PMU_MISC1_TOG_PFD_480_AUTOGATE_EN_SHIFT (16U) #define PMU_MISC1_TOG_PFD_480_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_PFD_480_AUTOGATE_EN_SHIFT)) & PMU_MISC1_TOG_PFD_480_AUTOGATE_EN_MASK) @@ -15535,13 +25187,22 @@ typedef struct { #define PMU_MISC1_TOG_IRQ_DIG_BO_MASK (0x80000000U) #define PMU_MISC1_TOG_IRQ_DIG_BO_SHIFT (31U) #define PMU_MISC1_TOG_IRQ_DIG_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_IRQ_DIG_BO_SHIFT)) & PMU_MISC1_TOG_IRQ_DIG_BO_MASK) +/*! @} */ /*! @name MISC2 - Miscellaneous Control Register */ +/*! @{ */ #define PMU_MISC2_REG0_BO_OFFSET_MASK (0x7U) #define PMU_MISC2_REG0_BO_OFFSET_SHIFT (0U) +/*! REG0_BO_OFFSET + * 0b100..Brownout offset = 0.100V + * 0b111..Brownout offset = 0.175V + */ #define PMU_MISC2_REG0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG0_BO_OFFSET_SHIFT)) & PMU_MISC2_REG0_BO_OFFSET_MASK) #define PMU_MISC2_REG0_BO_STATUS_MASK (0x8U) #define PMU_MISC2_REG0_BO_STATUS_SHIFT (3U) +/*! REG0_BO_STATUS + * 0b1..Brownout, supply is below target minus brownout offset. + */ #define PMU_MISC2_REG0_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG0_BO_STATUS_SHIFT)) & PMU_MISC2_REG0_BO_STATUS_MASK) #define PMU_MISC2_REG0_ENABLE_BO_MASK (0x20U) #define PMU_MISC2_REG0_ENABLE_BO_SHIFT (5U) @@ -15549,11 +25210,35 @@ typedef struct { #define PMU_MISC2_PLL3_disable_MASK (0x80U) #define PMU_MISC2_PLL3_disable_SHIFT (7U) #define PMU_MISC2_PLL3_disable(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_PLL3_disable_SHIFT)) & PMU_MISC2_PLL3_disable_MASK) +#define PMU_MISC2_REG1_BO_OFFSET_MASK (0x700U) +#define PMU_MISC2_REG1_BO_OFFSET_SHIFT (8U) +/*! REG1_BO_OFFSET + * 0b100..Brownout offset = 0.100V + * 0b111..Brownout offset = 0.175V + */ +#define PMU_MISC2_REG1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG1_BO_OFFSET_SHIFT)) & PMU_MISC2_REG1_BO_OFFSET_MASK) +#define PMU_MISC2_REG1_BO_STATUS_MASK (0x800U) +#define PMU_MISC2_REG1_BO_STATUS_SHIFT (11U) +/*! REG1_BO_STATUS + * 0b1..Brownout, supply is below target minus brownout offset. + */ +#define PMU_MISC2_REG1_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG1_BO_STATUS_SHIFT)) & PMU_MISC2_REG1_BO_STATUS_MASK) +#define PMU_MISC2_REG1_ENABLE_BO_MASK (0x2000U) +#define PMU_MISC2_REG1_ENABLE_BO_SHIFT (13U) +#define PMU_MISC2_REG1_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG1_ENABLE_BO_SHIFT)) & PMU_MISC2_REG1_ENABLE_BO_MASK) #define PMU_MISC2_AUDIO_DIV_LSB_MASK (0x8000U) #define PMU_MISC2_AUDIO_DIV_LSB_SHIFT (15U) +/*! AUDIO_DIV_LSB + * 0b0..divide by 1 (Default) + * 0b1..divide by 2 + */ #define PMU_MISC2_AUDIO_DIV_LSB(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_AUDIO_DIV_LSB_SHIFT)) & PMU_MISC2_AUDIO_DIV_LSB_MASK) #define PMU_MISC2_REG2_BO_OFFSET_MASK (0x70000U) #define PMU_MISC2_REG2_BO_OFFSET_SHIFT (16U) +/*! REG2_BO_OFFSET + * 0b100..Brownout offset = 0.100V + * 0b111..Brownout offset = 0.175V + */ #define PMU_MISC2_REG2_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG2_BO_OFFSET_SHIFT)) & PMU_MISC2_REG2_BO_OFFSET_MASK) #define PMU_MISC2_REG2_BO_STATUS_MASK (0x80000U) #define PMU_MISC2_REG2_BO_STATUS_SHIFT (19U) @@ -15566,23 +25251,63 @@ typedef struct { #define PMU_MISC2_REG2_OK(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG2_OK_SHIFT)) & PMU_MISC2_REG2_OK_MASK) #define PMU_MISC2_AUDIO_DIV_MSB_MASK (0x800000U) #define PMU_MISC2_AUDIO_DIV_MSB_SHIFT (23U) +/*! AUDIO_DIV_MSB + * 0b0..divide by 1 (Default) + * 0b1..divide by 2 + */ #define PMU_MISC2_AUDIO_DIV_MSB(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_AUDIO_DIV_MSB_SHIFT)) & PMU_MISC2_AUDIO_DIV_MSB_MASK) #define PMU_MISC2_REG0_STEP_TIME_MASK (0x3000000U) #define PMU_MISC2_REG0_STEP_TIME_SHIFT (24U) +/*! REG0_STEP_TIME + * 0b00..64 + * 0b01..128 + * 0b10..256 + * 0b11..512 + */ #define PMU_MISC2_REG0_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG0_STEP_TIME_SHIFT)) & PMU_MISC2_REG0_STEP_TIME_MASK) +#define PMU_MISC2_REG1_STEP_TIME_MASK (0xC000000U) +#define PMU_MISC2_REG1_STEP_TIME_SHIFT (26U) +/*! REG1_STEP_TIME + * 0b00..64 + * 0b01..128 + * 0b10..256 + * 0b11..512 + */ +#define PMU_MISC2_REG1_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG1_STEP_TIME_SHIFT)) & PMU_MISC2_REG1_STEP_TIME_MASK) #define PMU_MISC2_REG2_STEP_TIME_MASK (0x30000000U) #define PMU_MISC2_REG2_STEP_TIME_SHIFT (28U) +/*! REG2_STEP_TIME + * 0b00..64 + * 0b01..128 + * 0b10..256 + * 0b11..512 + */ #define PMU_MISC2_REG2_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG2_STEP_TIME_SHIFT)) & PMU_MISC2_REG2_STEP_TIME_MASK) #define PMU_MISC2_VIDEO_DIV_MASK (0xC0000000U) #define PMU_MISC2_VIDEO_DIV_SHIFT (30U) +/*! VIDEO_DIV + * 0b00..divide by 1 (Default) + * 0b01..divide by 2 + * 0b10..divide by 1 + * 0b11..divide by 4 + */ #define PMU_MISC2_VIDEO_DIV(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_VIDEO_DIV_SHIFT)) & PMU_MISC2_VIDEO_DIV_MASK) +/*! @} */ /*! @name MISC2_SET - Miscellaneous Control Register */ +/*! @{ */ #define PMU_MISC2_SET_REG0_BO_OFFSET_MASK (0x7U) #define PMU_MISC2_SET_REG0_BO_OFFSET_SHIFT (0U) +/*! REG0_BO_OFFSET + * 0b100..Brownout offset = 0.100V + * 0b111..Brownout offset = 0.175V + */ #define PMU_MISC2_SET_REG0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG0_BO_OFFSET_SHIFT)) & PMU_MISC2_SET_REG0_BO_OFFSET_MASK) #define PMU_MISC2_SET_REG0_BO_STATUS_MASK (0x8U) #define PMU_MISC2_SET_REG0_BO_STATUS_SHIFT (3U) +/*! REG0_BO_STATUS + * 0b1..Brownout, supply is below target minus brownout offset. + */ #define PMU_MISC2_SET_REG0_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG0_BO_STATUS_SHIFT)) & PMU_MISC2_SET_REG0_BO_STATUS_MASK) #define PMU_MISC2_SET_REG0_ENABLE_BO_MASK (0x20U) #define PMU_MISC2_SET_REG0_ENABLE_BO_SHIFT (5U) @@ -15590,11 +25315,35 @@ typedef struct { #define PMU_MISC2_SET_PLL3_disable_MASK (0x80U) #define PMU_MISC2_SET_PLL3_disable_SHIFT (7U) #define PMU_MISC2_SET_PLL3_disable(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_PLL3_disable_SHIFT)) & PMU_MISC2_SET_PLL3_disable_MASK) +#define PMU_MISC2_SET_REG1_BO_OFFSET_MASK (0x700U) +#define PMU_MISC2_SET_REG1_BO_OFFSET_SHIFT (8U) +/*! REG1_BO_OFFSET + * 0b100..Brownout offset = 0.100V + * 0b111..Brownout offset = 0.175V + */ +#define PMU_MISC2_SET_REG1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG1_BO_OFFSET_SHIFT)) & PMU_MISC2_SET_REG1_BO_OFFSET_MASK) +#define PMU_MISC2_SET_REG1_BO_STATUS_MASK (0x800U) +#define PMU_MISC2_SET_REG1_BO_STATUS_SHIFT (11U) +/*! REG1_BO_STATUS + * 0b1..Brownout, supply is below target minus brownout offset. + */ +#define PMU_MISC2_SET_REG1_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG1_BO_STATUS_SHIFT)) & PMU_MISC2_SET_REG1_BO_STATUS_MASK) +#define PMU_MISC2_SET_REG1_ENABLE_BO_MASK (0x2000U) +#define PMU_MISC2_SET_REG1_ENABLE_BO_SHIFT (13U) +#define PMU_MISC2_SET_REG1_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG1_ENABLE_BO_SHIFT)) & PMU_MISC2_SET_REG1_ENABLE_BO_MASK) #define PMU_MISC2_SET_AUDIO_DIV_LSB_MASK (0x8000U) #define PMU_MISC2_SET_AUDIO_DIV_LSB_SHIFT (15U) +/*! AUDIO_DIV_LSB + * 0b0..divide by 1 (Default) + * 0b1..divide by 2 + */ #define PMU_MISC2_SET_AUDIO_DIV_LSB(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_AUDIO_DIV_LSB_SHIFT)) & PMU_MISC2_SET_AUDIO_DIV_LSB_MASK) #define PMU_MISC2_SET_REG2_BO_OFFSET_MASK (0x70000U) #define PMU_MISC2_SET_REG2_BO_OFFSET_SHIFT (16U) +/*! REG2_BO_OFFSET + * 0b100..Brownout offset = 0.100V + * 0b111..Brownout offset = 0.175V + */ #define PMU_MISC2_SET_REG2_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG2_BO_OFFSET_SHIFT)) & PMU_MISC2_SET_REG2_BO_OFFSET_MASK) #define PMU_MISC2_SET_REG2_BO_STATUS_MASK (0x80000U) #define PMU_MISC2_SET_REG2_BO_STATUS_SHIFT (19U) @@ -15607,23 +25356,63 @@ typedef struct { #define PMU_MISC2_SET_REG2_OK(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG2_OK_SHIFT)) & PMU_MISC2_SET_REG2_OK_MASK) #define PMU_MISC2_SET_AUDIO_DIV_MSB_MASK (0x800000U) #define PMU_MISC2_SET_AUDIO_DIV_MSB_SHIFT (23U) +/*! AUDIO_DIV_MSB + * 0b0..divide by 1 (Default) + * 0b1..divide by 2 + */ #define PMU_MISC2_SET_AUDIO_DIV_MSB(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_AUDIO_DIV_MSB_SHIFT)) & PMU_MISC2_SET_AUDIO_DIV_MSB_MASK) #define PMU_MISC2_SET_REG0_STEP_TIME_MASK (0x3000000U) #define PMU_MISC2_SET_REG0_STEP_TIME_SHIFT (24U) +/*! REG0_STEP_TIME + * 0b00..64 + * 0b01..128 + * 0b10..256 + * 0b11..512 + */ #define PMU_MISC2_SET_REG0_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG0_STEP_TIME_SHIFT)) & PMU_MISC2_SET_REG0_STEP_TIME_MASK) +#define PMU_MISC2_SET_REG1_STEP_TIME_MASK (0xC000000U) +#define PMU_MISC2_SET_REG1_STEP_TIME_SHIFT (26U) +/*! REG1_STEP_TIME + * 0b00..64 + * 0b01..128 + * 0b10..256 + * 0b11..512 + */ +#define PMU_MISC2_SET_REG1_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG1_STEP_TIME_SHIFT)) & PMU_MISC2_SET_REG1_STEP_TIME_MASK) #define PMU_MISC2_SET_REG2_STEP_TIME_MASK (0x30000000U) #define PMU_MISC2_SET_REG2_STEP_TIME_SHIFT (28U) +/*! REG2_STEP_TIME + * 0b00..64 + * 0b01..128 + * 0b10..256 + * 0b11..512 + */ #define PMU_MISC2_SET_REG2_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG2_STEP_TIME_SHIFT)) & PMU_MISC2_SET_REG2_STEP_TIME_MASK) #define PMU_MISC2_SET_VIDEO_DIV_MASK (0xC0000000U) #define PMU_MISC2_SET_VIDEO_DIV_SHIFT (30U) +/*! VIDEO_DIV + * 0b00..divide by 1 (Default) + * 0b01..divide by 2 + * 0b10..divide by 1 + * 0b11..divide by 4 + */ #define PMU_MISC2_SET_VIDEO_DIV(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_VIDEO_DIV_SHIFT)) & PMU_MISC2_SET_VIDEO_DIV_MASK) +/*! @} */ /*! @name MISC2_CLR - Miscellaneous Control Register */ +/*! @{ */ #define PMU_MISC2_CLR_REG0_BO_OFFSET_MASK (0x7U) #define PMU_MISC2_CLR_REG0_BO_OFFSET_SHIFT (0U) +/*! REG0_BO_OFFSET + * 0b100..Brownout offset = 0.100V + * 0b111..Brownout offset = 0.175V + */ #define PMU_MISC2_CLR_REG0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG0_BO_OFFSET_SHIFT)) & PMU_MISC2_CLR_REG0_BO_OFFSET_MASK) #define PMU_MISC2_CLR_REG0_BO_STATUS_MASK (0x8U) #define PMU_MISC2_CLR_REG0_BO_STATUS_SHIFT (3U) +/*! REG0_BO_STATUS + * 0b1..Brownout, supply is below target minus brownout offset. + */ #define PMU_MISC2_CLR_REG0_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG0_BO_STATUS_SHIFT)) & PMU_MISC2_CLR_REG0_BO_STATUS_MASK) #define PMU_MISC2_CLR_REG0_ENABLE_BO_MASK (0x20U) #define PMU_MISC2_CLR_REG0_ENABLE_BO_SHIFT (5U) @@ -15631,11 +25420,35 @@ typedef struct { #define PMU_MISC2_CLR_PLL3_disable_MASK (0x80U) #define PMU_MISC2_CLR_PLL3_disable_SHIFT (7U) #define PMU_MISC2_CLR_PLL3_disable(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_PLL3_disable_SHIFT)) & PMU_MISC2_CLR_PLL3_disable_MASK) +#define PMU_MISC2_CLR_REG1_BO_OFFSET_MASK (0x700U) +#define PMU_MISC2_CLR_REG1_BO_OFFSET_SHIFT (8U) +/*! REG1_BO_OFFSET + * 0b100..Brownout offset = 0.100V + * 0b111..Brownout offset = 0.175V + */ +#define PMU_MISC2_CLR_REG1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG1_BO_OFFSET_SHIFT)) & PMU_MISC2_CLR_REG1_BO_OFFSET_MASK) +#define PMU_MISC2_CLR_REG1_BO_STATUS_MASK (0x800U) +#define PMU_MISC2_CLR_REG1_BO_STATUS_SHIFT (11U) +/*! REG1_BO_STATUS + * 0b1..Brownout, supply is below target minus brownout offset. + */ +#define PMU_MISC2_CLR_REG1_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG1_BO_STATUS_SHIFT)) & PMU_MISC2_CLR_REG1_BO_STATUS_MASK) +#define PMU_MISC2_CLR_REG1_ENABLE_BO_MASK (0x2000U) +#define PMU_MISC2_CLR_REG1_ENABLE_BO_SHIFT (13U) +#define PMU_MISC2_CLR_REG1_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG1_ENABLE_BO_SHIFT)) & PMU_MISC2_CLR_REG1_ENABLE_BO_MASK) #define PMU_MISC2_CLR_AUDIO_DIV_LSB_MASK (0x8000U) #define PMU_MISC2_CLR_AUDIO_DIV_LSB_SHIFT (15U) +/*! AUDIO_DIV_LSB + * 0b0..divide by 1 (Default) + * 0b1..divide by 2 + */ #define PMU_MISC2_CLR_AUDIO_DIV_LSB(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_AUDIO_DIV_LSB_SHIFT)) & PMU_MISC2_CLR_AUDIO_DIV_LSB_MASK) #define PMU_MISC2_CLR_REG2_BO_OFFSET_MASK (0x70000U) #define PMU_MISC2_CLR_REG2_BO_OFFSET_SHIFT (16U) +/*! REG2_BO_OFFSET + * 0b100..Brownout offset = 0.100V + * 0b111..Brownout offset = 0.175V + */ #define PMU_MISC2_CLR_REG2_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG2_BO_OFFSET_SHIFT)) & PMU_MISC2_CLR_REG2_BO_OFFSET_MASK) #define PMU_MISC2_CLR_REG2_BO_STATUS_MASK (0x80000U) #define PMU_MISC2_CLR_REG2_BO_STATUS_SHIFT (19U) @@ -15648,23 +25461,63 @@ typedef struct { #define PMU_MISC2_CLR_REG2_OK(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG2_OK_SHIFT)) & PMU_MISC2_CLR_REG2_OK_MASK) #define PMU_MISC2_CLR_AUDIO_DIV_MSB_MASK (0x800000U) #define PMU_MISC2_CLR_AUDIO_DIV_MSB_SHIFT (23U) +/*! AUDIO_DIV_MSB + * 0b0..divide by 1 (Default) + * 0b1..divide by 2 + */ #define PMU_MISC2_CLR_AUDIO_DIV_MSB(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_AUDIO_DIV_MSB_SHIFT)) & PMU_MISC2_CLR_AUDIO_DIV_MSB_MASK) #define PMU_MISC2_CLR_REG0_STEP_TIME_MASK (0x3000000U) #define PMU_MISC2_CLR_REG0_STEP_TIME_SHIFT (24U) +/*! REG0_STEP_TIME + * 0b00..64 + * 0b01..128 + * 0b10..256 + * 0b11..512 + */ #define PMU_MISC2_CLR_REG0_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG0_STEP_TIME_SHIFT)) & PMU_MISC2_CLR_REG0_STEP_TIME_MASK) +#define PMU_MISC2_CLR_REG1_STEP_TIME_MASK (0xC000000U) +#define PMU_MISC2_CLR_REG1_STEP_TIME_SHIFT (26U) +/*! REG1_STEP_TIME + * 0b00..64 + * 0b01..128 + * 0b10..256 + * 0b11..512 + */ +#define PMU_MISC2_CLR_REG1_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG1_STEP_TIME_SHIFT)) & PMU_MISC2_CLR_REG1_STEP_TIME_MASK) #define PMU_MISC2_CLR_REG2_STEP_TIME_MASK (0x30000000U) #define PMU_MISC2_CLR_REG2_STEP_TIME_SHIFT (28U) +/*! REG2_STEP_TIME + * 0b00..64 + * 0b01..128 + * 0b10..256 + * 0b11..512 + */ #define PMU_MISC2_CLR_REG2_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG2_STEP_TIME_SHIFT)) & PMU_MISC2_CLR_REG2_STEP_TIME_MASK) #define PMU_MISC2_CLR_VIDEO_DIV_MASK (0xC0000000U) #define PMU_MISC2_CLR_VIDEO_DIV_SHIFT (30U) +/*! VIDEO_DIV + * 0b00..divide by 1 (Default) + * 0b01..divide by 2 + * 0b10..divide by 1 + * 0b11..divide by 4 + */ #define PMU_MISC2_CLR_VIDEO_DIV(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_VIDEO_DIV_SHIFT)) & PMU_MISC2_CLR_VIDEO_DIV_MASK) +/*! @} */ /*! @name MISC2_TOG - Miscellaneous Control Register */ +/*! @{ */ #define PMU_MISC2_TOG_REG0_BO_OFFSET_MASK (0x7U) #define PMU_MISC2_TOG_REG0_BO_OFFSET_SHIFT (0U) +/*! REG0_BO_OFFSET + * 0b100..Brownout offset = 0.100V + * 0b111..Brownout offset = 0.175V + */ #define PMU_MISC2_TOG_REG0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG0_BO_OFFSET_SHIFT)) & PMU_MISC2_TOG_REG0_BO_OFFSET_MASK) #define PMU_MISC2_TOG_REG0_BO_STATUS_MASK (0x8U) #define PMU_MISC2_TOG_REG0_BO_STATUS_SHIFT (3U) +/*! REG0_BO_STATUS + * 0b1..Brownout, supply is below target minus brownout offset. + */ #define PMU_MISC2_TOG_REG0_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG0_BO_STATUS_SHIFT)) & PMU_MISC2_TOG_REG0_BO_STATUS_MASK) #define PMU_MISC2_TOG_REG0_ENABLE_BO_MASK (0x20U) #define PMU_MISC2_TOG_REG0_ENABLE_BO_SHIFT (5U) @@ -15672,11 +25525,35 @@ typedef struct { #define PMU_MISC2_TOG_PLL3_disable_MASK (0x80U) #define PMU_MISC2_TOG_PLL3_disable_SHIFT (7U) #define PMU_MISC2_TOG_PLL3_disable(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_PLL3_disable_SHIFT)) & PMU_MISC2_TOG_PLL3_disable_MASK) +#define PMU_MISC2_TOG_REG1_BO_OFFSET_MASK (0x700U) +#define PMU_MISC2_TOG_REG1_BO_OFFSET_SHIFT (8U) +/*! REG1_BO_OFFSET + * 0b100..Brownout offset = 0.100V + * 0b111..Brownout offset = 0.175V + */ +#define PMU_MISC2_TOG_REG1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG1_BO_OFFSET_SHIFT)) & PMU_MISC2_TOG_REG1_BO_OFFSET_MASK) +#define PMU_MISC2_TOG_REG1_BO_STATUS_MASK (0x800U) +#define PMU_MISC2_TOG_REG1_BO_STATUS_SHIFT (11U) +/*! REG1_BO_STATUS + * 0b1..Brownout, supply is below target minus brownout offset. + */ +#define PMU_MISC2_TOG_REG1_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG1_BO_STATUS_SHIFT)) & PMU_MISC2_TOG_REG1_BO_STATUS_MASK) +#define PMU_MISC2_TOG_REG1_ENABLE_BO_MASK (0x2000U) +#define PMU_MISC2_TOG_REG1_ENABLE_BO_SHIFT (13U) +#define PMU_MISC2_TOG_REG1_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG1_ENABLE_BO_SHIFT)) & PMU_MISC2_TOG_REG1_ENABLE_BO_MASK) #define PMU_MISC2_TOG_AUDIO_DIV_LSB_MASK (0x8000U) #define PMU_MISC2_TOG_AUDIO_DIV_LSB_SHIFT (15U) +/*! AUDIO_DIV_LSB + * 0b0..divide by 1 (Default) + * 0b1..divide by 2 + */ #define PMU_MISC2_TOG_AUDIO_DIV_LSB(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_AUDIO_DIV_LSB_SHIFT)) & PMU_MISC2_TOG_AUDIO_DIV_LSB_MASK) #define PMU_MISC2_TOG_REG2_BO_OFFSET_MASK (0x70000U) #define PMU_MISC2_TOG_REG2_BO_OFFSET_SHIFT (16U) +/*! REG2_BO_OFFSET + * 0b100..Brownout offset = 0.100V + * 0b111..Brownout offset = 0.175V + */ #define PMU_MISC2_TOG_REG2_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG2_BO_OFFSET_SHIFT)) & PMU_MISC2_TOG_REG2_BO_OFFSET_MASK) #define PMU_MISC2_TOG_REG2_BO_STATUS_MASK (0x80000U) #define PMU_MISC2_TOG_REG2_BO_STATUS_SHIFT (19U) @@ -15689,16 +25566,48 @@ typedef struct { #define PMU_MISC2_TOG_REG2_OK(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG2_OK_SHIFT)) & PMU_MISC2_TOG_REG2_OK_MASK) #define PMU_MISC2_TOG_AUDIO_DIV_MSB_MASK (0x800000U) #define PMU_MISC2_TOG_AUDIO_DIV_MSB_SHIFT (23U) +/*! AUDIO_DIV_MSB + * 0b0..divide by 1 (Default) + * 0b1..divide by 2 + */ #define PMU_MISC2_TOG_AUDIO_DIV_MSB(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_AUDIO_DIV_MSB_SHIFT)) & PMU_MISC2_TOG_AUDIO_DIV_MSB_MASK) #define PMU_MISC2_TOG_REG0_STEP_TIME_MASK (0x3000000U) #define PMU_MISC2_TOG_REG0_STEP_TIME_SHIFT (24U) +/*! REG0_STEP_TIME + * 0b00..64 + * 0b01..128 + * 0b10..256 + * 0b11..512 + */ #define PMU_MISC2_TOG_REG0_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG0_STEP_TIME_SHIFT)) & PMU_MISC2_TOG_REG0_STEP_TIME_MASK) +#define PMU_MISC2_TOG_REG1_STEP_TIME_MASK (0xC000000U) +#define PMU_MISC2_TOG_REG1_STEP_TIME_SHIFT (26U) +/*! REG1_STEP_TIME + * 0b00..64 + * 0b01..128 + * 0b10..256 + * 0b11..512 + */ +#define PMU_MISC2_TOG_REG1_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG1_STEP_TIME_SHIFT)) & PMU_MISC2_TOG_REG1_STEP_TIME_MASK) #define PMU_MISC2_TOG_REG2_STEP_TIME_MASK (0x30000000U) #define PMU_MISC2_TOG_REG2_STEP_TIME_SHIFT (28U) +/*! REG2_STEP_TIME + * 0b00..64 + * 0b01..128 + * 0b10..256 + * 0b11..512 + */ #define PMU_MISC2_TOG_REG2_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG2_STEP_TIME_SHIFT)) & PMU_MISC2_TOG_REG2_STEP_TIME_MASK) #define PMU_MISC2_TOG_VIDEO_DIV_MASK (0xC0000000U) #define PMU_MISC2_TOG_VIDEO_DIV_SHIFT (30U) +/*! VIDEO_DIV + * 0b00..divide by 1 (Default) + * 0b01..divide by 2 + * 0b10..divide by 1 + * 0b11..divide by 4 + */ #define PMU_MISC2_TOG_VIDEO_DIV(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_VIDEO_DIV_SHIFT)) & PMU_MISC2_TOG_VIDEO_DIV_MASK) +/*! @} */ /*! @@ -15801,39 +25710,74 @@ typedef struct { */ /*! @name CNT - Counter Register */ +/*! @{ */ #define PWM_CNT_CNT_MASK (0xFFFFU) #define PWM_CNT_CNT_SHIFT (0U) #define PWM_CNT_CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CNT_CNT_SHIFT)) & PWM_CNT_CNT_MASK) +/*! @} */ /* The count of PWM_CNT */ #define PWM_CNT_COUNT (4U) /*! @name INIT - Initial Count Register */ +/*! @{ */ #define PWM_INIT_INIT_MASK (0xFFFFU) #define PWM_INIT_INIT_SHIFT (0U) #define PWM_INIT_INIT(x) (((uint16_t)(((uint16_t)(x)) << PWM_INIT_INIT_SHIFT)) & PWM_INIT_INIT_MASK) +/*! @} */ /* The count of PWM_INIT */ #define PWM_INIT_COUNT (4U) /*! @name CTRL2 - Control 2 Register */ +/*! @{ */ #define PWM_CTRL2_CLK_SEL_MASK (0x3U) #define PWM_CTRL2_CLK_SEL_SHIFT (0U) +/*! CLK_SEL - Clock Source Select + * 0b00..The IPBus clock is used as the clock for the local prescaler and counter. + * 0b01..EXT_CLK is used as the clock for the local prescaler and counter. + * 0b10..Submodule 0's clock (AUX_CLK) is used as the source clock for the local prescaler and counter. This setting should not be used in submodule 0 as it will force the clock to logic 0. + * 0b11..reserved + */ #define PWM_CTRL2_CLK_SEL(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_CLK_SEL_SHIFT)) & PWM_CTRL2_CLK_SEL_MASK) #define PWM_CTRL2_RELOAD_SEL_MASK (0x4U) #define PWM_CTRL2_RELOAD_SEL_SHIFT (2U) +/*! RELOAD_SEL - Reload Source Select + * 0b0..The local RELOAD signal is used to reload registers. + * 0b1..The master RELOAD signal (from submodule 0) is used to reload registers. This setting should not be used in submodule 0 as it will force the RELOAD signal to logic 0. + */ #define PWM_CTRL2_RELOAD_SEL(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_RELOAD_SEL_SHIFT)) & PWM_CTRL2_RELOAD_SEL_MASK) #define PWM_CTRL2_FORCE_SEL_MASK (0x38U) #define PWM_CTRL2_FORCE_SEL_SHIFT (3U) +/*! FORCE_SEL - This read/write bit determines the source of the FORCE OUTPUT signal for this submodule. + * 0b000..The local force signal, CTRL2[FORCE], from this submodule is used to force updates. + * 0b001..The master force signal from submodule 0 is used to force updates. This setting should not be used in submodule 0 as it will hold the FORCE OUTPUT signal to logic 0. + * 0b010..The local reload signal from this submodule is used to force updates without regard to the state of LDOK. + * 0b011..The master reload signal from submodule0 is used to force updates if LDOK is set. This setting should not be used in submodule0 as it will hold the FORCE OUTPUT signal to logic 0. + * 0b100..The local sync signal from this submodule is used to force updates. + * 0b101..The master sync signal from submodule0 is used to force updates. This setting should not be used in submodule0 as it will hold the FORCE OUTPUT signal to logic 0. + * 0b110..The external force signal, EXT_FORCE, from outside the PWM module causes updates. + * 0b111..The external sync signal, EXT_SYNC, from outside the PWM module causes updates. + */ #define PWM_CTRL2_FORCE_SEL(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_FORCE_SEL_SHIFT)) & PWM_CTRL2_FORCE_SEL_MASK) #define PWM_CTRL2_FORCE_MASK (0x40U) #define PWM_CTRL2_FORCE_SHIFT (6U) #define PWM_CTRL2_FORCE(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_FORCE_SHIFT)) & PWM_CTRL2_FORCE_MASK) #define PWM_CTRL2_FRCEN_MASK (0x80U) #define PWM_CTRL2_FRCEN_SHIFT (7U) +/*! FRCEN - FRCEN + * 0b0..Initialization from a FORCE_OUT is disabled. + * 0b1..Initialization from a FORCE_OUT is enabled. + */ #define PWM_CTRL2_FRCEN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_FRCEN_SHIFT)) & PWM_CTRL2_FRCEN_MASK) #define PWM_CTRL2_INIT_SEL_MASK (0x300U) #define PWM_CTRL2_INIT_SEL_SHIFT (8U) +/*! INIT_SEL - Initialization Control Select + * 0b00..Local sync (PWM_X) causes initialization. + * 0b01..Master reload from submodule 0 causes initialization. This setting should not be used in submodule 0 as it will force the INIT signal to logic 0. The submodule counter will only reinitialize when a master reload occurs. + * 0b10..Master sync from submodule 0 causes initialization. This setting should not be used in submodule 0 as it will force the INIT signal to logic 0. + * 0b11..EXT_SYNC causes initialization. + */ #define PWM_CTRL2_INIT_SEL(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_INIT_SEL_SHIFT)) & PWM_CTRL2_INIT_SEL_MASK) #define PWM_CTRL2_PWMX_INIT_MASK (0x400U) #define PWM_CTRL2_PWMX_INIT_SHIFT (10U) @@ -15846,6 +25790,10 @@ typedef struct { #define PWM_CTRL2_PWM23_INIT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_PWM23_INIT_SHIFT)) & PWM_CTRL2_PWM23_INIT_MASK) #define PWM_CTRL2_INDEP_MASK (0x2000U) #define PWM_CTRL2_INDEP_SHIFT (13U) +/*! INDEP - Independent or Complementary Pair Operation + * 0b0..PWM_A and PWM_B form a complementary PWM pair. + * 0b1..PWM_A and PWM_B outputs are independent PWMs. + */ #define PWM_CTRL2_INDEP(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_INDEP_SHIFT)) & PWM_CTRL2_INDEP_MASK) #define PWM_CTRL2_WAITEN_MASK (0x4000U) #define PWM_CTRL2_WAITEN_SHIFT (14U) @@ -15853,171 +25801,301 @@ typedef struct { #define PWM_CTRL2_DBGEN_MASK (0x8000U) #define PWM_CTRL2_DBGEN_SHIFT (15U) #define PWM_CTRL2_DBGEN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_DBGEN_SHIFT)) & PWM_CTRL2_DBGEN_MASK) +/*! @} */ /* The count of PWM_CTRL2 */ #define PWM_CTRL2_COUNT (4U) /*! @name CTRL - Control Register */ +/*! @{ */ #define PWM_CTRL_DBLEN_MASK (0x1U) #define PWM_CTRL_DBLEN_SHIFT (0U) +/*! DBLEN - Double Switching Enable + * 0b0..Double switching disabled. + * 0b1..Double switching enabled. + */ #define PWM_CTRL_DBLEN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_DBLEN_SHIFT)) & PWM_CTRL_DBLEN_MASK) #define PWM_CTRL_DBLX_MASK (0x2U) #define PWM_CTRL_DBLX_SHIFT (1U) +/*! DBLX - PWMX Double Switching Enable + * 0b0..PWMX double pulse disabled. + * 0b1..PWMX double pulse enabled. + */ #define PWM_CTRL_DBLX(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_DBLX_SHIFT)) & PWM_CTRL_DBLX_MASK) #define PWM_CTRL_LDMOD_MASK (0x4U) #define PWM_CTRL_LDMOD_SHIFT (2U) +/*! LDMOD - Load Mode Select + * 0b0..Buffered registers of this submodule are loaded and take effect at the next PWM reload if MCTRL[LDOK] is set. + * 0b1..Buffered registers of this submodule are loaded and take effect immediately upon MCTRL[LDOK] being set. In this case it is not necessary to set CTRL[FULL] or CTRL[HALF]. + */ #define PWM_CTRL_LDMOD(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_LDMOD_SHIFT)) & PWM_CTRL_LDMOD_MASK) #define PWM_CTRL_SPLIT_MASK (0x8U) #define PWM_CTRL_SPLIT_SHIFT (3U) +/*! SPLIT - Split the DBLPWM signal to PWMA and PWMB + * 0b0..DBLPWM is not split. PWMA and PWMB each have double pulses. + * 0b1..DBLPWM is split to PWMA and PWMB. + */ #define PWM_CTRL_SPLIT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_SPLIT_SHIFT)) & PWM_CTRL_SPLIT_MASK) #define PWM_CTRL_PRSC_MASK (0x70U) #define PWM_CTRL_PRSC_SHIFT (4U) +/*! PRSC - Prescaler + * 0b000..PWM clock frequency = fclk + * 0b001..PWM clock frequency = fclk/2 + * 0b010..PWM clock frequency = fclk/4 + * 0b011..PWM clock frequency = fclk/8 + * 0b100..PWM clock frequency = fclk/16 + * 0b101..PWM clock frequency = fclk/32 + * 0b110..PWM clock frequency = fclk/64 + * 0b111..PWM clock frequency = fclk/128 + */ #define PWM_CTRL_PRSC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_PRSC_SHIFT)) & PWM_CTRL_PRSC_MASK) #define PWM_CTRL_COMPMODE_MASK (0x80U) #define PWM_CTRL_COMPMODE_SHIFT (7U) +/*! COMPMODE - Compare Mode + * 0b0..The VAL* registers and the PWM counter are compared using an "equal to" method. This means that PWM edges are only produced when the counter is equal to one of the VAL* register values. This implies that a PWMA output that is high at the end of a period will maintain this state until a match with VAL3 clears the output in the following period. + * 0b1..The VAL* registers and the PWM counter are compared using an "equal to or greater than" method. This means that PWM edges are produced when the counter is equal to or greater than one of the VAL* register values. This implies that a PWMA output that is high at the end of a period could go low at the start of the next period if the starting counter value is greater than (but not necessarily equal to) the new VAL3 value. + */ #define PWM_CTRL_COMPMODE(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_COMPMODE_SHIFT)) & PWM_CTRL_COMPMODE_MASK) #define PWM_CTRL_DT_MASK (0x300U) #define PWM_CTRL_DT_SHIFT (8U) #define PWM_CTRL_DT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_DT_SHIFT)) & PWM_CTRL_DT_MASK) #define PWM_CTRL_FULL_MASK (0x400U) #define PWM_CTRL_FULL_SHIFT (10U) +/*! FULL - Full Cycle Reload + * 0b0..Full-cycle reloads disabled. + * 0b1..Full-cycle reloads enabled. + */ #define PWM_CTRL_FULL(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_FULL_SHIFT)) & PWM_CTRL_FULL_MASK) #define PWM_CTRL_HALF_MASK (0x800U) #define PWM_CTRL_HALF_SHIFT (11U) +/*! HALF - Half Cycle Reload + * 0b0..Half-cycle reloads disabled. + * 0b1..Half-cycle reloads enabled. + */ #define PWM_CTRL_HALF(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_HALF_SHIFT)) & PWM_CTRL_HALF_MASK) #define PWM_CTRL_LDFQ_MASK (0xF000U) #define PWM_CTRL_LDFQ_SHIFT (12U) +/*! LDFQ - Load Frequency + * 0b0000..Every PWM opportunity + * 0b0001..Every 2 PWM opportunities + * 0b0010..Every 3 PWM opportunities + * 0b0011..Every 4 PWM opportunities + * 0b0100..Every 5 PWM opportunities + * 0b0101..Every 6 PWM opportunities + * 0b0110..Every 7 PWM opportunities + * 0b0111..Every 8 PWM opportunities + * 0b1000..Every 9 PWM opportunities + * 0b1001..Every 10 PWM opportunities + * 0b1010..Every 11 PWM opportunities + * 0b1011..Every 12 PWM opportunities + * 0b1100..Every 13 PWM opportunities + * 0b1101..Every 14 PWM opportunities + * 0b1110..Every 15 PWM opportunities + * 0b1111..Every 16 PWM opportunities + */ #define PWM_CTRL_LDFQ(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_LDFQ_SHIFT)) & PWM_CTRL_LDFQ_MASK) +/*! @} */ /* The count of PWM_CTRL */ #define PWM_CTRL_COUNT (4U) /*! @name VAL0 - Value Register 0 */ +/*! @{ */ #define PWM_VAL0_VAL0_MASK (0xFFFFU) #define PWM_VAL0_VAL0_SHIFT (0U) #define PWM_VAL0_VAL0(x) (((uint16_t)(((uint16_t)(x)) << PWM_VAL0_VAL0_SHIFT)) & PWM_VAL0_VAL0_MASK) +/*! @} */ /* The count of PWM_VAL0 */ #define PWM_VAL0_COUNT (4U) /*! @name FRACVAL1 - Fractional Value Register 1 */ +/*! @{ */ #define PWM_FRACVAL1_FRACVAL1_MASK (0xF800U) #define PWM_FRACVAL1_FRACVAL1_SHIFT (11U) #define PWM_FRACVAL1_FRACVAL1(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRACVAL1_FRACVAL1_SHIFT)) & PWM_FRACVAL1_FRACVAL1_MASK) +/*! @} */ /* The count of PWM_FRACVAL1 */ #define PWM_FRACVAL1_COUNT (4U) /*! @name VAL1 - Value Register 1 */ +/*! @{ */ #define PWM_VAL1_VAL1_MASK (0xFFFFU) #define PWM_VAL1_VAL1_SHIFT (0U) #define PWM_VAL1_VAL1(x) (((uint16_t)(((uint16_t)(x)) << PWM_VAL1_VAL1_SHIFT)) & PWM_VAL1_VAL1_MASK) +/*! @} */ /* The count of PWM_VAL1 */ #define PWM_VAL1_COUNT (4U) /*! @name FRACVAL2 - Fractional Value Register 2 */ +/*! @{ */ #define PWM_FRACVAL2_FRACVAL2_MASK (0xF800U) #define PWM_FRACVAL2_FRACVAL2_SHIFT (11U) #define PWM_FRACVAL2_FRACVAL2(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRACVAL2_FRACVAL2_SHIFT)) & PWM_FRACVAL2_FRACVAL2_MASK) +/*! @} */ /* The count of PWM_FRACVAL2 */ #define PWM_FRACVAL2_COUNT (4U) /*! @name VAL2 - Value Register 2 */ +/*! @{ */ #define PWM_VAL2_VAL2_MASK (0xFFFFU) #define PWM_VAL2_VAL2_SHIFT (0U) #define PWM_VAL2_VAL2(x) (((uint16_t)(((uint16_t)(x)) << PWM_VAL2_VAL2_SHIFT)) & PWM_VAL2_VAL2_MASK) +/*! @} */ /* The count of PWM_VAL2 */ #define PWM_VAL2_COUNT (4U) /*! @name FRACVAL3 - Fractional Value Register 3 */ +/*! @{ */ #define PWM_FRACVAL3_FRACVAL3_MASK (0xF800U) #define PWM_FRACVAL3_FRACVAL3_SHIFT (11U) #define PWM_FRACVAL3_FRACVAL3(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRACVAL3_FRACVAL3_SHIFT)) & PWM_FRACVAL3_FRACVAL3_MASK) +/*! @} */ /* The count of PWM_FRACVAL3 */ #define PWM_FRACVAL3_COUNT (4U) /*! @name VAL3 - Value Register 3 */ +/*! @{ */ #define PWM_VAL3_VAL3_MASK (0xFFFFU) #define PWM_VAL3_VAL3_SHIFT (0U) #define PWM_VAL3_VAL3(x) (((uint16_t)(((uint16_t)(x)) << PWM_VAL3_VAL3_SHIFT)) & PWM_VAL3_VAL3_MASK) +/*! @} */ /* The count of PWM_VAL3 */ #define PWM_VAL3_COUNT (4U) /*! @name FRACVAL4 - Fractional Value Register 4 */ +/*! @{ */ #define PWM_FRACVAL4_FRACVAL4_MASK (0xF800U) #define PWM_FRACVAL4_FRACVAL4_SHIFT (11U) #define PWM_FRACVAL4_FRACVAL4(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRACVAL4_FRACVAL4_SHIFT)) & PWM_FRACVAL4_FRACVAL4_MASK) +/*! @} */ /* The count of PWM_FRACVAL4 */ #define PWM_FRACVAL4_COUNT (4U) /*! @name VAL4 - Value Register 4 */ +/*! @{ */ #define PWM_VAL4_VAL4_MASK (0xFFFFU) #define PWM_VAL4_VAL4_SHIFT (0U) #define PWM_VAL4_VAL4(x) (((uint16_t)(((uint16_t)(x)) << PWM_VAL4_VAL4_SHIFT)) & PWM_VAL4_VAL4_MASK) +/*! @} */ /* The count of PWM_VAL4 */ #define PWM_VAL4_COUNT (4U) /*! @name FRACVAL5 - Fractional Value Register 5 */ +/*! @{ */ #define PWM_FRACVAL5_FRACVAL5_MASK (0xF800U) #define PWM_FRACVAL5_FRACVAL5_SHIFT (11U) #define PWM_FRACVAL5_FRACVAL5(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRACVAL5_FRACVAL5_SHIFT)) & PWM_FRACVAL5_FRACVAL5_MASK) +/*! @} */ /* The count of PWM_FRACVAL5 */ #define PWM_FRACVAL5_COUNT (4U) /*! @name VAL5 - Value Register 5 */ +/*! @{ */ #define PWM_VAL5_VAL5_MASK (0xFFFFU) #define PWM_VAL5_VAL5_SHIFT (0U) #define PWM_VAL5_VAL5(x) (((uint16_t)(((uint16_t)(x)) << PWM_VAL5_VAL5_SHIFT)) & PWM_VAL5_VAL5_MASK) +/*! @} */ /* The count of PWM_VAL5 */ #define PWM_VAL5_COUNT (4U) /*! @name FRCTRL - Fractional Control Register */ +/*! @{ */ #define PWM_FRCTRL_FRAC1_EN_MASK (0x2U) #define PWM_FRCTRL_FRAC1_EN_SHIFT (1U) +/*! FRAC1_EN - Fractional Cycle PWM Period Enable + * 0b0..Disable fractional cycle length for the PWM period. + * 0b1..Enable fractional cycle length for the PWM period. + */ #define PWM_FRCTRL_FRAC1_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRCTRL_FRAC1_EN_SHIFT)) & PWM_FRCTRL_FRAC1_EN_MASK) #define PWM_FRCTRL_FRAC23_EN_MASK (0x4U) #define PWM_FRCTRL_FRAC23_EN_SHIFT (2U) +/*! FRAC23_EN - Fractional Cycle Placement Enable for PWM_A + * 0b0..Disable fractional cycle placement for PWM_A. + * 0b1..Enable fractional cycle placement for PWM_A. + */ #define PWM_FRCTRL_FRAC23_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRCTRL_FRAC23_EN_SHIFT)) & PWM_FRCTRL_FRAC23_EN_MASK) #define PWM_FRCTRL_FRAC45_EN_MASK (0x10U) #define PWM_FRCTRL_FRAC45_EN_SHIFT (4U) +/*! FRAC45_EN - Fractional Cycle Placement Enable for PWM_B + * 0b0..Disable fractional cycle placement for PWM_B. + * 0b1..Enable fractional cycle placement for PWM_B. + */ #define PWM_FRCTRL_FRAC45_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRCTRL_FRAC45_EN_SHIFT)) & PWM_FRCTRL_FRAC45_EN_MASK) #define PWM_FRCTRL_FRAC_PU_MASK (0x100U) #define PWM_FRCTRL_FRAC_PU_SHIFT (8U) +/*! FRAC_PU - Fractional Delay Circuit Power Up + * 0b0..Turn off fractional delay logic. + * 0b1..Power up fractional delay logic. + */ #define PWM_FRCTRL_FRAC_PU(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRCTRL_FRAC_PU_SHIFT)) & PWM_FRCTRL_FRAC_PU_MASK) #define PWM_FRCTRL_TEST_MASK (0x8000U) #define PWM_FRCTRL_TEST_SHIFT (15U) #define PWM_FRCTRL_TEST(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRCTRL_TEST_SHIFT)) & PWM_FRCTRL_TEST_MASK) +/*! @} */ /* The count of PWM_FRCTRL */ #define PWM_FRCTRL_COUNT (4U) /*! @name OCTRL - Output Control Register */ +/*! @{ */ #define PWM_OCTRL_PWMXFS_MASK (0x3U) #define PWM_OCTRL_PWMXFS_SHIFT (0U) +/*! PWMXFS - PWM_X Fault State + * 0b00..Output is forced to logic 0 state prior to consideration of output polarity control. + * 0b01..Output is forced to logic 1 state prior to consideration of output polarity control. + * 0b10..Output is tristated. + * 0b11..Output is tristated. + */ #define PWM_OCTRL_PWMXFS(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMXFS_SHIFT)) & PWM_OCTRL_PWMXFS_MASK) #define PWM_OCTRL_PWMBFS_MASK (0xCU) #define PWM_OCTRL_PWMBFS_SHIFT (2U) +/*! PWMBFS - PWM_B Fault State + * 0b00..Output is forced to logic 0 state prior to consideration of output polarity control. + * 0b01..Output is forced to logic 1 state prior to consideration of output polarity control. + * 0b10..Output is tristated. + * 0b11..Output is tristated. + */ #define PWM_OCTRL_PWMBFS(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMBFS_SHIFT)) & PWM_OCTRL_PWMBFS_MASK) #define PWM_OCTRL_PWMAFS_MASK (0x30U) #define PWM_OCTRL_PWMAFS_SHIFT (4U) +/*! PWMAFS - PWM_A Fault State + * 0b00..Output is forced to logic 0 state prior to consideration of output polarity control. + * 0b01..Output is forced to logic 1 state prior to consideration of output polarity control. + * 0b10..Output is tristated. + * 0b11..Output is tristated. + */ #define PWM_OCTRL_PWMAFS(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMAFS_SHIFT)) & PWM_OCTRL_PWMAFS_MASK) #define PWM_OCTRL_POLX_MASK (0x100U) #define PWM_OCTRL_POLX_SHIFT (8U) +/*! POLX - PWM_X Output Polarity + * 0b0..PWM_X output not inverted. A high level on the PWM_X pin represents the "on" or "active" state. + * 0b1..PWM_X output inverted. A low level on the PWM_X pin represents the "on" or "active" state. + */ #define PWM_OCTRL_POLX(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_POLX_SHIFT)) & PWM_OCTRL_POLX_MASK) #define PWM_OCTRL_POLB_MASK (0x200U) #define PWM_OCTRL_POLB_SHIFT (9U) +/*! POLB - PWM_B Output Polarity + * 0b0..PWM_B output not inverted. A high level on the PWM_B pin represents the "on" or "active" state. + * 0b1..PWM_B output inverted. A low level on the PWM_B pin represents the "on" or "active" state. + */ #define PWM_OCTRL_POLB(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_POLB_SHIFT)) & PWM_OCTRL_POLB_MASK) #define PWM_OCTRL_POLA_MASK (0x400U) #define PWM_OCTRL_POLA_SHIFT (10U) +/*! POLA - PWM_A Output Polarity + * 0b0..PWM_A output not inverted. A high level on the PWM_A pin represents the "on" or "active" state. + * 0b1..PWM_A output inverted. A low level on the PWM_A pin represents the "on" or "active" state. + */ #define PWM_OCTRL_POLA(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_POLA_SHIFT)) & PWM_OCTRL_POLA_MASK) #define PWM_OCTRL_PWMX_IN_MASK (0x2000U) #define PWM_OCTRL_PWMX_IN_SHIFT (13U) @@ -16028,13 +26106,19 @@ typedef struct { #define PWM_OCTRL_PWMA_IN_MASK (0x8000U) #define PWM_OCTRL_PWMA_IN_SHIFT (15U) #define PWM_OCTRL_PWMA_IN(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMA_IN_SHIFT)) & PWM_OCTRL_PWMA_IN_MASK) +/*! @} */ /* The count of PWM_OCTRL */ #define PWM_OCTRL_COUNT (4U) /*! @name STS - Status Register */ +/*! @{ */ #define PWM_STS_CMPF_MASK (0x3FU) #define PWM_STS_CMPF_SHIFT (0U) +/*! CMPF - Compare Flags + * 0b000000..No compare event has occurred for a particular VALx value. + * 0b000001..A compare event has occurred for a particular VALx value. + */ #define PWM_STS_CMPF(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_CMPF_SHIFT)) & PWM_STS_CMPF_MASK) #define PWM_STS_CFX0_MASK (0x40U) #define PWM_STS_CFX0_SHIFT (6U) @@ -16056,50 +26140,102 @@ typedef struct { #define PWM_STS_CFA1(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFA1_SHIFT)) & PWM_STS_CFA1_MASK) #define PWM_STS_RF_MASK (0x1000U) #define PWM_STS_RF_SHIFT (12U) +/*! RF - Reload Flag + * 0b0..No new reload cycle since last STS[RF] clearing + * 0b1..New reload cycle since last STS[RF] clearing + */ #define PWM_STS_RF(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_RF_SHIFT)) & PWM_STS_RF_MASK) #define PWM_STS_REF_MASK (0x2000U) #define PWM_STS_REF_SHIFT (13U) +/*! REF - Reload Error Flag + * 0b0..No reload error occurred. + * 0b1..Reload signal occurred with non-coherent data and MCTRL[LDOK] = 0. + */ #define PWM_STS_REF(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_REF_SHIFT)) & PWM_STS_REF_MASK) #define PWM_STS_RUF_MASK (0x4000U) #define PWM_STS_RUF_SHIFT (14U) +/*! RUF - Registers Updated Flag + * 0b0..No register update has occurred since last reload. + * 0b1..At least one of the double buffered registers has been updated since the last reload. + */ #define PWM_STS_RUF(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_RUF_SHIFT)) & PWM_STS_RUF_MASK) +/*! @} */ /* The count of PWM_STS */ #define PWM_STS_COUNT (4U) /*! @name INTEN - Interrupt Enable Register */ +/*! @{ */ #define PWM_INTEN_CMPIE_MASK (0x3FU) #define PWM_INTEN_CMPIE_SHIFT (0U) +/*! CMPIE - Compare Interrupt Enables + * 0b000000..The corresponding STS[CMPF] bit will not cause an interrupt request. + * 0b000001..The corresponding STS[CMPF] bit will cause an interrupt request. + */ #define PWM_INTEN_CMPIE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CMPIE_SHIFT)) & PWM_INTEN_CMPIE_MASK) #define PWM_INTEN_CX0IE_MASK (0x40U) #define PWM_INTEN_CX0IE_SHIFT (6U) +/*! CX0IE - Capture X 0 Interrupt Enable + * 0b0..Interrupt request disabled for STS[CFX0]. + * 0b1..Interrupt request enabled for STS[CFX0]. + */ #define PWM_INTEN_CX0IE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CX0IE_SHIFT)) & PWM_INTEN_CX0IE_MASK) #define PWM_INTEN_CX1IE_MASK (0x80U) #define PWM_INTEN_CX1IE_SHIFT (7U) +/*! CX1IE - Capture X 1 Interrupt Enable + * 0b0..Interrupt request disabled for STS[CFX1]. + * 0b1..Interrupt request enabled for STS[CFX1]. + */ #define PWM_INTEN_CX1IE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CX1IE_SHIFT)) & PWM_INTEN_CX1IE_MASK) #define PWM_INTEN_CB0IE_MASK (0x100U) #define PWM_INTEN_CB0IE_SHIFT (8U) +/*! CB0IE - Capture B 0 Interrupt Enable + * 0b0..Interrupt request disabled for STS[CFB0]. + * 0b1..Interrupt request enabled for STS[CFB0]. + */ #define PWM_INTEN_CB0IE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CB0IE_SHIFT)) & PWM_INTEN_CB0IE_MASK) #define PWM_INTEN_CB1IE_MASK (0x200U) #define PWM_INTEN_CB1IE_SHIFT (9U) +/*! CB1IE - Capture B 1 Interrupt Enable + * 0b0..Interrupt request disabled for STS[CFB1]. + * 0b1..Interrupt request enabled for STS[CFB1]. + */ #define PWM_INTEN_CB1IE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CB1IE_SHIFT)) & PWM_INTEN_CB1IE_MASK) #define PWM_INTEN_CA0IE_MASK (0x400U) #define PWM_INTEN_CA0IE_SHIFT (10U) +/*! CA0IE - Capture A 0 Interrupt Enable + * 0b0..Interrupt request disabled for STS[CFA0]. + * 0b1..Interrupt request enabled for STS[CFA0]. + */ #define PWM_INTEN_CA0IE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CA0IE_SHIFT)) & PWM_INTEN_CA0IE_MASK) #define PWM_INTEN_CA1IE_MASK (0x800U) #define PWM_INTEN_CA1IE_SHIFT (11U) +/*! CA1IE - Capture A 1 Interrupt Enable + * 0b0..Interrupt request disabled for STS[CFA1]. + * 0b1..Interrupt request enabled for STS[CFA1]. + */ #define PWM_INTEN_CA1IE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CA1IE_SHIFT)) & PWM_INTEN_CA1IE_MASK) #define PWM_INTEN_RIE_MASK (0x1000U) #define PWM_INTEN_RIE_SHIFT (12U) +/*! RIE - Reload Interrupt Enable + * 0b0..STS[RF] CPU interrupt requests disabled + * 0b1..STS[RF] CPU interrupt requests enabled + */ #define PWM_INTEN_RIE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_RIE_SHIFT)) & PWM_INTEN_RIE_MASK) #define PWM_INTEN_REIE_MASK (0x2000U) #define PWM_INTEN_REIE_SHIFT (13U) +/*! REIE - Reload Error Interrupt Enable + * 0b0..STS[REF] CPU interrupt requests disabled + * 0b1..STS[REF] CPU interrupt requests enabled + */ #define PWM_INTEN_REIE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_REIE_SHIFT)) & PWM_INTEN_REIE_MASK) +/*! @} */ /* The count of PWM_INTEN */ #define PWM_INTEN_COUNT (4U) /*! @name DMAEN - DMA Enable Register */ +/*! @{ */ #define PWM_DMAEN_CX0DE_MASK (0x1U) #define PWM_DMAEN_CX0DE_SHIFT (0U) #define PWM_DMAEN_CX0DE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CX0DE_SHIFT)) & PWM_DMAEN_CX0DE_MASK) @@ -16120,35 +26256,69 @@ typedef struct { #define PWM_DMAEN_CA1DE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CA1DE_SHIFT)) & PWM_DMAEN_CA1DE_MASK) #define PWM_DMAEN_CAPTDE_MASK (0xC0U) #define PWM_DMAEN_CAPTDE_SHIFT (6U) +/*! CAPTDE - Capture DMA Enable Source Select + * 0b00..Read DMA requests disabled. + * 0b01..Exceeding a FIFO watermark sets the DMA read request. This requires at least one of DMAEN[CA1DE], DMAEN[CA0DE], DMAEN[CB1DE], DMAEN[CB0DE], DMAEN[CX1DE], or DMAEN[CX0DE] to also be set in order to determine to which watermark(s) the DMA request is sensitive. + * 0b10..A local sync (VAL1 matches counter) sets the read DMA request. + * 0b11..A local reload (STS[RF] being set) sets the read DMA request. + */ #define PWM_DMAEN_CAPTDE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CAPTDE_SHIFT)) & PWM_DMAEN_CAPTDE_MASK) #define PWM_DMAEN_FAND_MASK (0x100U) #define PWM_DMAEN_FAND_SHIFT (8U) +/*! FAND - FIFO Watermark AND Control + * 0b0..Selected FIFO watermarks are OR'ed together. + * 0b1..Selected FIFO watermarks are AND'ed together. + */ #define PWM_DMAEN_FAND(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_FAND_SHIFT)) & PWM_DMAEN_FAND_MASK) #define PWM_DMAEN_VALDE_MASK (0x200U) #define PWM_DMAEN_VALDE_SHIFT (9U) +/*! VALDE - Value Registers DMA Enable + * 0b0..DMA write requests disabled + * 0b1..DMA write requests for the VALx and FRACVALx registers enabled + */ #define PWM_DMAEN_VALDE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_VALDE_SHIFT)) & PWM_DMAEN_VALDE_MASK) +/*! @} */ /* The count of PWM_DMAEN */ #define PWM_DMAEN_COUNT (4U) /*! @name TCTRL - Output Trigger Control Register */ +/*! @{ */ #define PWM_TCTRL_OUT_TRIG_EN_MASK (0x3FU) #define PWM_TCTRL_OUT_TRIG_EN_SHIFT (0U) +/*! OUT_TRIG_EN - Output Trigger Enables + * 0b000000..PWM_OUT_TRIGx will not set when the counter value matches the VALx value. + * 0b000001..PWM_OUT_TRIGx will set when the counter value matches the VALx value. + */ #define PWM_TCTRL_OUT_TRIG_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_TCTRL_OUT_TRIG_EN_SHIFT)) & PWM_TCTRL_OUT_TRIG_EN_MASK) #define PWM_TCTRL_TRGFRQ_MASK (0x1000U) #define PWM_TCTRL_TRGFRQ_SHIFT (12U) +/*! TRGFRQ - Trigger frequency + * 0b0..Trigger outputs are generated during every PWM period even if the PWM is not reloaded every period due to CTRL[LDFQ] being non-zero. + * 0b1..Trigger outputs are generated only during the final PWM period prior to a reload opportunity when the PWM is not reloaded every period due to CTRL[LDFQ] being non-zero. + */ #define PWM_TCTRL_TRGFRQ(x) (((uint16_t)(((uint16_t)(x)) << PWM_TCTRL_TRGFRQ_SHIFT)) & PWM_TCTRL_TRGFRQ_MASK) #define PWM_TCTRL_PWBOT1_MASK (0x4000U) #define PWM_TCTRL_PWBOT1_SHIFT (14U) +/*! PWBOT1 - Output Trigger 1 Source Select + * 0b0..Route the PWM_OUT_TRIG1 signal to PWM_OUT_TRIG1 port. + * 0b1..Route the PWMB output to the PWM_OUT_TRIG1 port. + */ #define PWM_TCTRL_PWBOT1(x) (((uint16_t)(((uint16_t)(x)) << PWM_TCTRL_PWBOT1_SHIFT)) & PWM_TCTRL_PWBOT1_MASK) #define PWM_TCTRL_PWAOT0_MASK (0x8000U) #define PWM_TCTRL_PWAOT0_SHIFT (15U) +/*! PWAOT0 - Output Trigger 0 Source Select + * 0b0..Route the PWM_OUT_TRIG0 signal to PWM_OUT_TRIG0 port. + * 0b1..Route the PWMA output to the PWM_OUT_TRIG0 port. + */ #define PWM_TCTRL_PWAOT0(x) (((uint16_t)(((uint16_t)(x)) << PWM_TCTRL_PWAOT0_SHIFT)) & PWM_TCTRL_PWAOT0_MASK) +/*! @} */ /* The count of PWM_TCTRL */ #define PWM_TCTRL_COUNT (4U) /*! @name DISMAP - Fault Disable Mapping Register 0..Fault Disable Mapping Register 1 */ +/*! @{ */ #define PWM_DISMAP_DIS0A_MASK (0xFU) #define PWM_DISMAP_DIS0A_SHIFT (0U) #define PWM_DISMAP_DIS0A(x) (((uint16_t)(((uint16_t)(x)) << PWM_DISMAP_DIS0A_SHIFT)) & PWM_DISMAP_DIS0A_MASK) @@ -16161,12 +26331,13 @@ typedef struct { #define PWM_DISMAP_DIS1B_MASK (0xF0U) #define PWM_DISMAP_DIS1B_SHIFT (4U) #define PWM_DISMAP_DIS1B(x) (((uint16_t)(((uint16_t)(x)) << PWM_DISMAP_DIS1B_SHIFT)) & PWM_DISMAP_DIS1B_MASK) -#define PWM_DISMAP_DIS1X_MASK (0xF00U) -#define PWM_DISMAP_DIS1X_SHIFT (8U) -#define PWM_DISMAP_DIS1X(x) (((uint16_t)(((uint16_t)(x)) << PWM_DISMAP_DIS1X_SHIFT)) & PWM_DISMAP_DIS1X_MASK) #define PWM_DISMAP_DIS0X_MASK (0xF00U) #define PWM_DISMAP_DIS0X_SHIFT (8U) #define PWM_DISMAP_DIS0X(x) (((uint16_t)(((uint16_t)(x)) << PWM_DISMAP_DIS0X_SHIFT)) & PWM_DISMAP_DIS0X_MASK) +#define PWM_DISMAP_DIS1X_MASK (0xF00U) +#define PWM_DISMAP_DIS1X_SHIFT (8U) +#define PWM_DISMAP_DIS1X(x) (((uint16_t)(((uint16_t)(x)) << PWM_DISMAP_DIS1X_SHIFT)) & PWM_DISMAP_DIS1X_MASK) +/*! @} */ /* The count of PWM_DISMAP */ #define PWM_DISMAP_COUNT (4U) @@ -16175,39 +26346,72 @@ typedef struct { #define PWM_DISMAP_COUNT2 (2U) /*! @name DTCNT0 - Deadtime Count Register 0 */ +/*! @{ */ #define PWM_DTCNT0_DTCNT0_MASK (0xFFFFU) #define PWM_DTCNT0_DTCNT0_SHIFT (0U) #define PWM_DTCNT0_DTCNT0(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTCNT0_DTCNT0_SHIFT)) & PWM_DTCNT0_DTCNT0_MASK) +/*! @} */ /* The count of PWM_DTCNT0 */ #define PWM_DTCNT0_COUNT (4U) /*! @name DTCNT1 - Deadtime Count Register 1 */ +/*! @{ */ #define PWM_DTCNT1_DTCNT1_MASK (0xFFFFU) #define PWM_DTCNT1_DTCNT1_SHIFT (0U) #define PWM_DTCNT1_DTCNT1(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTCNT1_DTCNT1_SHIFT)) & PWM_DTCNT1_DTCNT1_MASK) +/*! @} */ /* The count of PWM_DTCNT1 */ #define PWM_DTCNT1_COUNT (4U) /*! @name CAPTCTRLA - Capture Control A Register */ +/*! @{ */ #define PWM_CAPTCTRLA_ARMA_MASK (0x1U) #define PWM_CAPTCTRLA_ARMA_SHIFT (0U) +/*! ARMA - Arm A + * 0b0..Input capture operation is disabled. + * 0b1..Input capture operation as specified by CAPTCTRLA[EDGAx] is enabled. + */ #define PWM_CAPTCTRLA_ARMA(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_ARMA_SHIFT)) & PWM_CAPTCTRLA_ARMA_MASK) #define PWM_CAPTCTRLA_ONESHOTA_MASK (0x2U) #define PWM_CAPTCTRLA_ONESHOTA_SHIFT (1U) +/*! ONESHOTA - One Shot Mode A + * 0b0..Free running mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after CAPTCTRLA[ARMA] is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and capture circuit 0 is re-armed. The process continues indefinitely.If only one of the capture circuits is enabled, then captures continue indefinitely on the enabled capture circuit. + * 0b1..One shot mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after CAPTCTRLA[ARMA] is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and CAPTCTRLA[ARMA] is cleared. No further captures will be performed until CAPTCTRLA[ARMA] is set again.If only one of the capture circuits is enabled, then a single capture will occur on the enabled capture circuit and CAPTCTRLA[ARMA] is then cleared. + */ #define PWM_CAPTCTRLA_ONESHOTA(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_ONESHOTA_SHIFT)) & PWM_CAPTCTRLA_ONESHOTA_MASK) #define PWM_CAPTCTRLA_EDGA0_MASK (0xCU) #define PWM_CAPTCTRLA_EDGA0_SHIFT (2U) +/*! EDGA0 - Edge A 0 + * 0b00..Disabled + * 0b01..Capture falling edges + * 0b10..Capture rising edges + * 0b11..Capture any edge + */ #define PWM_CAPTCTRLA_EDGA0(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_EDGA0_SHIFT)) & PWM_CAPTCTRLA_EDGA0_MASK) #define PWM_CAPTCTRLA_EDGA1_MASK (0x30U) #define PWM_CAPTCTRLA_EDGA1_SHIFT (4U) +/*! EDGA1 - Edge A 1 + * 0b00..Disabled + * 0b01..Capture falling edges + * 0b10..Capture rising edges + * 0b11..Capture any edge + */ #define PWM_CAPTCTRLA_EDGA1(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_EDGA1_SHIFT)) & PWM_CAPTCTRLA_EDGA1_MASK) #define PWM_CAPTCTRLA_INP_SELA_MASK (0x40U) #define PWM_CAPTCTRLA_INP_SELA_SHIFT (6U) +/*! INP_SELA - Input Select A + * 0b0..Raw PWM_A input signal selected as source. + * 0b1..Output of edge counter/compare selected as source. Note that when this bitfield is set to 1, the internal edge counter is enabled and the rising and/or falling edges specified by the CAPTCTRLA[EDGA0] and CAPTCTRLA[EDGA1] fields are ignored. The software must still place a value other than 00 in either or both of the CAPTCTLRA[EDGA0] and/or CAPTCTRLA[EDGA1] fields in order to enable one or both of the capture registers. + */ #define PWM_CAPTCTRLA_INP_SELA(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_INP_SELA_SHIFT)) & PWM_CAPTCTRLA_INP_SELA_MASK) #define PWM_CAPTCTRLA_EDGCNTA_EN_MASK (0x80U) #define PWM_CAPTCTRLA_EDGCNTA_EN_SHIFT (7U) +/*! EDGCNTA_EN - Edge Counter A Enable + * 0b0..Edge counter disabled and held in reset + * 0b1..Edge counter enabled + */ #define PWM_CAPTCTRLA_EDGCNTA_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_EDGCNTA_EN_SHIFT)) & PWM_CAPTCTRLA_EDGCNTA_EN_MASK) #define PWM_CAPTCTRLA_CFAWM_MASK (0x300U) #define PWM_CAPTCTRLA_CFAWM_SHIFT (8U) @@ -16218,39 +26422,71 @@ typedef struct { #define PWM_CAPTCTRLA_CA1CNT_MASK (0xE000U) #define PWM_CAPTCTRLA_CA1CNT_SHIFT (13U) #define PWM_CAPTCTRLA_CA1CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_CA1CNT_SHIFT)) & PWM_CAPTCTRLA_CA1CNT_MASK) +/*! @} */ /* The count of PWM_CAPTCTRLA */ #define PWM_CAPTCTRLA_COUNT (4U) /*! @name CAPTCOMPA - Capture Compare A Register */ +/*! @{ */ #define PWM_CAPTCOMPA_EDGCMPA_MASK (0xFFU) #define PWM_CAPTCOMPA_EDGCMPA_SHIFT (0U) #define PWM_CAPTCOMPA_EDGCMPA(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPA_EDGCMPA_SHIFT)) & PWM_CAPTCOMPA_EDGCMPA_MASK) #define PWM_CAPTCOMPA_EDGCNTA_MASK (0xFF00U) #define PWM_CAPTCOMPA_EDGCNTA_SHIFT (8U) #define PWM_CAPTCOMPA_EDGCNTA(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPA_EDGCNTA_SHIFT)) & PWM_CAPTCOMPA_EDGCNTA_MASK) +/*! @} */ /* The count of PWM_CAPTCOMPA */ #define PWM_CAPTCOMPA_COUNT (4U) /*! @name CAPTCTRLB - Capture Control B Register */ +/*! @{ */ #define PWM_CAPTCTRLB_ARMB_MASK (0x1U) #define PWM_CAPTCTRLB_ARMB_SHIFT (0U) +/*! ARMB - Arm B + * 0b0..Input capture operation is disabled. + * 0b1..Input capture operation as specified by CAPTCTRLB[EDGBx] is enabled. + */ #define PWM_CAPTCTRLB_ARMB(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_ARMB_SHIFT)) & PWM_CAPTCTRLB_ARMB_MASK) #define PWM_CAPTCTRLB_ONESHOTB_MASK (0x2U) #define PWM_CAPTCTRLB_ONESHOTB_SHIFT (1U) +/*! ONESHOTB - One Shot Mode B + * 0b0..Free running mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after CAPTCTRLB[ARMB] is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and capture circuit 0 is re-armed. The process continues indefinitely.If only one of the capture circuits is enabled, then captures continue indefinitely on the enabled capture circuit. + * 0b1..One shot mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after CAPTCTRLB[ARMB] is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and CAPTCTRLB[ARMB] is cleared. No further captures will be performed until CAPTCTRLB[ARMB] is set again.If only one of the capture circuits is enabled, then a single capture will occur on the enabled capture circuit and CAPTCTRLB[ARMB] is then cleared. + */ #define PWM_CAPTCTRLB_ONESHOTB(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_ONESHOTB_SHIFT)) & PWM_CAPTCTRLB_ONESHOTB_MASK) #define PWM_CAPTCTRLB_EDGB0_MASK (0xCU) #define PWM_CAPTCTRLB_EDGB0_SHIFT (2U) +/*! EDGB0 - Edge B 0 + * 0b00..Disabled + * 0b01..Capture falling edges + * 0b10..Capture rising edges + * 0b11..Capture any edge + */ #define PWM_CAPTCTRLB_EDGB0(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_EDGB0_SHIFT)) & PWM_CAPTCTRLB_EDGB0_MASK) #define PWM_CAPTCTRLB_EDGB1_MASK (0x30U) #define PWM_CAPTCTRLB_EDGB1_SHIFT (4U) +/*! EDGB1 - Edge B 1 + * 0b00..Disabled + * 0b01..Capture falling edges + * 0b10..Capture rising edges + * 0b11..Capture any edge + */ #define PWM_CAPTCTRLB_EDGB1(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_EDGB1_SHIFT)) & PWM_CAPTCTRLB_EDGB1_MASK) #define PWM_CAPTCTRLB_INP_SELB_MASK (0x40U) #define PWM_CAPTCTRLB_INP_SELB_SHIFT (6U) +/*! INP_SELB - Input Select B + * 0b0..Raw PWM_B input signal selected as source. + * 0b1..Output of edge counter/compare selected as source. Note that when this bitfield is set to 1, the internal edge counter is enabled and the rising and/or falling edges specified by the CAPTCTRLB[EDGB0] and CAPTCTRLB[EDGB1] fields are ignored. The software must still place a value other than 00 in either or both of the CAPTCTLRB[EDGB0] and/or CAPTCTRLB[EDGB1] fields in order to enable one or both of the capture registers. + */ #define PWM_CAPTCTRLB_INP_SELB(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_INP_SELB_SHIFT)) & PWM_CAPTCTRLB_INP_SELB_MASK) #define PWM_CAPTCTRLB_EDGCNTB_EN_MASK (0x80U) #define PWM_CAPTCTRLB_EDGCNTB_EN_SHIFT (7U) +/*! EDGCNTB_EN - Edge Counter B Enable + * 0b0..Edge counter disabled and held in reset + * 0b1..Edge counter enabled + */ #define PWM_CAPTCTRLB_EDGCNTB_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_EDGCNTB_EN_SHIFT)) & PWM_CAPTCTRLB_EDGCNTB_EN_MASK) #define PWM_CAPTCTRLB_CFBWM_MASK (0x300U) #define PWM_CAPTCTRLB_CFBWM_SHIFT (8U) @@ -16261,39 +26497,71 @@ typedef struct { #define PWM_CAPTCTRLB_CB1CNT_MASK (0xE000U) #define PWM_CAPTCTRLB_CB1CNT_SHIFT (13U) #define PWM_CAPTCTRLB_CB1CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_CB1CNT_SHIFT)) & PWM_CAPTCTRLB_CB1CNT_MASK) +/*! @} */ /* The count of PWM_CAPTCTRLB */ #define PWM_CAPTCTRLB_COUNT (4U) /*! @name CAPTCOMPB - Capture Compare B Register */ +/*! @{ */ #define PWM_CAPTCOMPB_EDGCMPB_MASK (0xFFU) #define PWM_CAPTCOMPB_EDGCMPB_SHIFT (0U) #define PWM_CAPTCOMPB_EDGCMPB(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPB_EDGCMPB_SHIFT)) & PWM_CAPTCOMPB_EDGCMPB_MASK) #define PWM_CAPTCOMPB_EDGCNTB_MASK (0xFF00U) #define PWM_CAPTCOMPB_EDGCNTB_SHIFT (8U) #define PWM_CAPTCOMPB_EDGCNTB(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPB_EDGCNTB_SHIFT)) & PWM_CAPTCOMPB_EDGCNTB_MASK) +/*! @} */ /* The count of PWM_CAPTCOMPB */ #define PWM_CAPTCOMPB_COUNT (4U) /*! @name CAPTCTRLX - Capture Control X Register */ +/*! @{ */ #define PWM_CAPTCTRLX_ARMX_MASK (0x1U) #define PWM_CAPTCTRLX_ARMX_SHIFT (0U) +/*! ARMX - Arm X + * 0b0..Input capture operation is disabled. + * 0b1..Input capture operation as specified by CAPTCTRLX[EDGXx] is enabled. + */ #define PWM_CAPTCTRLX_ARMX(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_ARMX_SHIFT)) & PWM_CAPTCTRLX_ARMX_MASK) #define PWM_CAPTCTRLX_ONESHOTX_MASK (0x2U) #define PWM_CAPTCTRLX_ONESHOTX_SHIFT (1U) +/*! ONESHOTX - One Shot Mode Aux + * 0b0..Free running mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after the ARMX bit is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and capture circuit 0 is re-armed. The process continues indefinitely.If only one of the capture circuits is enabled, then captures continue indefinitely on the enabled capture circuit. + * 0b1..One shot mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after the ARMX bit is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and the ARMX bit is cleared. No further captures will be performed until the ARMX bit is set again.If only one of the capture circuits is enabled, then a single capture will occur on the enabled capture circuit and the ARMX bit is then cleared. + */ #define PWM_CAPTCTRLX_ONESHOTX(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_ONESHOTX_SHIFT)) & PWM_CAPTCTRLX_ONESHOTX_MASK) #define PWM_CAPTCTRLX_EDGX0_MASK (0xCU) #define PWM_CAPTCTRLX_EDGX0_SHIFT (2U) +/*! EDGX0 - Edge X 0 + * 0b00..Disabled + * 0b01..Capture falling edges + * 0b10..Capture rising edges + * 0b11..Capture any edge + */ #define PWM_CAPTCTRLX_EDGX0(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_EDGX0_SHIFT)) & PWM_CAPTCTRLX_EDGX0_MASK) #define PWM_CAPTCTRLX_EDGX1_MASK (0x30U) #define PWM_CAPTCTRLX_EDGX1_SHIFT (4U) +/*! EDGX1 - Edge X 1 + * 0b00..Disabled + * 0b01..Capture falling edges + * 0b10..Capture rising edges + * 0b11..Capture any edge + */ #define PWM_CAPTCTRLX_EDGX1(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_EDGX1_SHIFT)) & PWM_CAPTCTRLX_EDGX1_MASK) #define PWM_CAPTCTRLX_INP_SELX_MASK (0x40U) #define PWM_CAPTCTRLX_INP_SELX_SHIFT (6U) +/*! INP_SELX - Input Select X + * 0b0..Raw PWM_X input signal selected as source. + * 0b1..Output of edge counter/compare selected as source. Note that when this bitfield is set to 1, the internal edge counter is enabled and the rising and/or falling edges specified by the CAPTCTRLX[EDGX0] and CAPTCTRLX[EDGX1] fields are ignored. The software must still place a value other than 00 in either or both of the CAPTCTLRX[EDGX0] and/or CAPTCTRLX[EDGX1] fields in order to enable one or both of the capture registers. + */ #define PWM_CAPTCTRLX_INP_SELX(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_INP_SELX_SHIFT)) & PWM_CAPTCTRLX_INP_SELX_MASK) #define PWM_CAPTCTRLX_EDGCNTX_EN_MASK (0x80U) #define PWM_CAPTCTRLX_EDGCNTX_EN_SHIFT (7U) +/*! EDGCNTX_EN - Edge Counter X Enable + * 0b0..Edge counter disabled and held in reset + * 0b1..Edge counter enabled + */ #define PWM_CAPTCTRLX_EDGCNTX_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_EDGCNTX_EN_SHIFT)) & PWM_CAPTCTRLX_EDGCNTX_EN_MASK) #define PWM_CAPTCTRLX_CFXWM_MASK (0x300U) #define PWM_CAPTCTRLX_CFXWM_SHIFT (8U) @@ -16304,242 +26572,440 @@ typedef struct { #define PWM_CAPTCTRLX_CX1CNT_MASK (0xE000U) #define PWM_CAPTCTRLX_CX1CNT_SHIFT (13U) #define PWM_CAPTCTRLX_CX1CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_CX1CNT_SHIFT)) & PWM_CAPTCTRLX_CX1CNT_MASK) +/*! @} */ /* The count of PWM_CAPTCTRLX */ #define PWM_CAPTCTRLX_COUNT (4U) /*! @name CAPTCOMPX - Capture Compare X Register */ +/*! @{ */ #define PWM_CAPTCOMPX_EDGCMPX_MASK (0xFFU) #define PWM_CAPTCOMPX_EDGCMPX_SHIFT (0U) #define PWM_CAPTCOMPX_EDGCMPX(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPX_EDGCMPX_SHIFT)) & PWM_CAPTCOMPX_EDGCMPX_MASK) #define PWM_CAPTCOMPX_EDGCNTX_MASK (0xFF00U) #define PWM_CAPTCOMPX_EDGCNTX_SHIFT (8U) #define PWM_CAPTCOMPX_EDGCNTX(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPX_EDGCNTX_SHIFT)) & PWM_CAPTCOMPX_EDGCNTX_MASK) +/*! @} */ /* The count of PWM_CAPTCOMPX */ #define PWM_CAPTCOMPX_COUNT (4U) /*! @name CVAL0 - Capture Value 0 Register */ +/*! @{ */ #define PWM_CVAL0_CAPTVAL0_MASK (0xFFFFU) #define PWM_CVAL0_CAPTVAL0_SHIFT (0U) #define PWM_CVAL0_CAPTVAL0(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL0_CAPTVAL0_SHIFT)) & PWM_CVAL0_CAPTVAL0_MASK) +/*! @} */ /* The count of PWM_CVAL0 */ #define PWM_CVAL0_COUNT (4U) /*! @name CVAL0CYC - Capture Value 0 Cycle Register */ +/*! @{ */ #define PWM_CVAL0CYC_CVAL0CYC_MASK (0xFU) #define PWM_CVAL0CYC_CVAL0CYC_SHIFT (0U) #define PWM_CVAL0CYC_CVAL0CYC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL0CYC_CVAL0CYC_SHIFT)) & PWM_CVAL0CYC_CVAL0CYC_MASK) +/*! @} */ /* The count of PWM_CVAL0CYC */ #define PWM_CVAL0CYC_COUNT (4U) /*! @name CVAL1 - Capture Value 1 Register */ +/*! @{ */ #define PWM_CVAL1_CAPTVAL1_MASK (0xFFFFU) #define PWM_CVAL1_CAPTVAL1_SHIFT (0U) #define PWM_CVAL1_CAPTVAL1(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL1_CAPTVAL1_SHIFT)) & PWM_CVAL1_CAPTVAL1_MASK) +/*! @} */ /* The count of PWM_CVAL1 */ #define PWM_CVAL1_COUNT (4U) /*! @name CVAL1CYC - Capture Value 1 Cycle Register */ +/*! @{ */ #define PWM_CVAL1CYC_CVAL1CYC_MASK (0xFU) #define PWM_CVAL1CYC_CVAL1CYC_SHIFT (0U) #define PWM_CVAL1CYC_CVAL1CYC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL1CYC_CVAL1CYC_SHIFT)) & PWM_CVAL1CYC_CVAL1CYC_MASK) +/*! @} */ /* The count of PWM_CVAL1CYC */ #define PWM_CVAL1CYC_COUNT (4U) /*! @name CVAL2 - Capture Value 2 Register */ +/*! @{ */ #define PWM_CVAL2_CAPTVAL2_MASK (0xFFFFU) #define PWM_CVAL2_CAPTVAL2_SHIFT (0U) #define PWM_CVAL2_CAPTVAL2(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL2_CAPTVAL2_SHIFT)) & PWM_CVAL2_CAPTVAL2_MASK) +/*! @} */ /* The count of PWM_CVAL2 */ #define PWM_CVAL2_COUNT (4U) /*! @name CVAL2CYC - Capture Value 2 Cycle Register */ +/*! @{ */ #define PWM_CVAL2CYC_CVAL2CYC_MASK (0xFU) #define PWM_CVAL2CYC_CVAL2CYC_SHIFT (0U) #define PWM_CVAL2CYC_CVAL2CYC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL2CYC_CVAL2CYC_SHIFT)) & PWM_CVAL2CYC_CVAL2CYC_MASK) +/*! @} */ /* The count of PWM_CVAL2CYC */ #define PWM_CVAL2CYC_COUNT (4U) /*! @name CVAL3 - Capture Value 3 Register */ +/*! @{ */ #define PWM_CVAL3_CAPTVAL3_MASK (0xFFFFU) #define PWM_CVAL3_CAPTVAL3_SHIFT (0U) #define PWM_CVAL3_CAPTVAL3(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL3_CAPTVAL3_SHIFT)) & PWM_CVAL3_CAPTVAL3_MASK) +/*! @} */ /* The count of PWM_CVAL3 */ #define PWM_CVAL3_COUNT (4U) /*! @name CVAL3CYC - Capture Value 3 Cycle Register */ +/*! @{ */ #define PWM_CVAL3CYC_CVAL3CYC_MASK (0xFU) #define PWM_CVAL3CYC_CVAL3CYC_SHIFT (0U) #define PWM_CVAL3CYC_CVAL3CYC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL3CYC_CVAL3CYC_SHIFT)) & PWM_CVAL3CYC_CVAL3CYC_MASK) +/*! @} */ /* The count of PWM_CVAL3CYC */ #define PWM_CVAL3CYC_COUNT (4U) /*! @name CVAL4 - Capture Value 4 Register */ +/*! @{ */ #define PWM_CVAL4_CAPTVAL4_MASK (0xFFFFU) #define PWM_CVAL4_CAPTVAL4_SHIFT (0U) #define PWM_CVAL4_CAPTVAL4(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL4_CAPTVAL4_SHIFT)) & PWM_CVAL4_CAPTVAL4_MASK) +/*! @} */ /* The count of PWM_CVAL4 */ #define PWM_CVAL4_COUNT (4U) /*! @name CVAL4CYC - Capture Value 4 Cycle Register */ +/*! @{ */ #define PWM_CVAL4CYC_CVAL4CYC_MASK (0xFU) #define PWM_CVAL4CYC_CVAL4CYC_SHIFT (0U) #define PWM_CVAL4CYC_CVAL4CYC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL4CYC_CVAL4CYC_SHIFT)) & PWM_CVAL4CYC_CVAL4CYC_MASK) +/*! @} */ /* The count of PWM_CVAL4CYC */ #define PWM_CVAL4CYC_COUNT (4U) /*! @name CVAL5 - Capture Value 5 Register */ +/*! @{ */ #define PWM_CVAL5_CAPTVAL5_MASK (0xFFFFU) #define PWM_CVAL5_CAPTVAL5_SHIFT (0U) #define PWM_CVAL5_CAPTVAL5(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL5_CAPTVAL5_SHIFT)) & PWM_CVAL5_CAPTVAL5_MASK) +/*! @} */ /* The count of PWM_CVAL5 */ #define PWM_CVAL5_COUNT (4U) /*! @name CVAL5CYC - Capture Value 5 Cycle Register */ +/*! @{ */ #define PWM_CVAL5CYC_CVAL5CYC_MASK (0xFU) #define PWM_CVAL5CYC_CVAL5CYC_SHIFT (0U) #define PWM_CVAL5CYC_CVAL5CYC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL5CYC_CVAL5CYC_SHIFT)) & PWM_CVAL5CYC_CVAL5CYC_MASK) +/*! @} */ /* The count of PWM_CVAL5CYC */ #define PWM_CVAL5CYC_COUNT (4U) /*! @name OUTEN - Output Enable Register */ +/*! @{ */ #define PWM_OUTEN_PWMX_EN_MASK (0xFU) #define PWM_OUTEN_PWMX_EN_SHIFT (0U) +/*! PWMX_EN - PWM_X Output Enables + * 0b0000..PWM_X output disabled. + * 0b0001..PWM_X output enabled. + */ #define PWM_OUTEN_PWMX_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_OUTEN_PWMX_EN_SHIFT)) & PWM_OUTEN_PWMX_EN_MASK) #define PWM_OUTEN_PWMB_EN_MASK (0xF0U) #define PWM_OUTEN_PWMB_EN_SHIFT (4U) +/*! PWMB_EN - PWM_B Output Enables + * 0b0000..PWM_B output disabled. + * 0b0001..PWM_B output enabled. + */ #define PWM_OUTEN_PWMB_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_OUTEN_PWMB_EN_SHIFT)) & PWM_OUTEN_PWMB_EN_MASK) #define PWM_OUTEN_PWMA_EN_MASK (0xF00U) #define PWM_OUTEN_PWMA_EN_SHIFT (8U) +/*! PWMA_EN - PWM_A Output Enables + * 0b0000..PWM_A output disabled. + * 0b0001..PWM_A output enabled. + */ #define PWM_OUTEN_PWMA_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_OUTEN_PWMA_EN_SHIFT)) & PWM_OUTEN_PWMA_EN_MASK) +/*! @} */ /*! @name MASK - Mask Register */ +/*! @{ */ #define PWM_MASK_MASKX_MASK (0xFU) #define PWM_MASK_MASKX_SHIFT (0U) +/*! MASKX - PWM_X Masks + * 0b0000..PWM_X output normal. + * 0b0001..PWM_X output masked. + */ #define PWM_MASK_MASKX(x) (((uint16_t)(((uint16_t)(x)) << PWM_MASK_MASKX_SHIFT)) & PWM_MASK_MASKX_MASK) #define PWM_MASK_MASKB_MASK (0xF0U) #define PWM_MASK_MASKB_SHIFT (4U) +/*! MASKB - PWM_B Masks + * 0b0000..PWM_B output normal. + * 0b0001..PWM_B output masked. + */ #define PWM_MASK_MASKB(x) (((uint16_t)(((uint16_t)(x)) << PWM_MASK_MASKB_SHIFT)) & PWM_MASK_MASKB_MASK) #define PWM_MASK_MASKA_MASK (0xF00U) #define PWM_MASK_MASKA_SHIFT (8U) +/*! MASKA - PWM_A Masks + * 0b0000..PWM_A output normal. + * 0b0001..PWM_A output masked. + */ #define PWM_MASK_MASKA(x) (((uint16_t)(((uint16_t)(x)) << PWM_MASK_MASKA_SHIFT)) & PWM_MASK_MASKA_MASK) #define PWM_MASK_UPDATE_MASK_MASK (0xF000U) #define PWM_MASK_UPDATE_MASK_SHIFT (12U) +/*! UPDATE_MASK - Update Mask Bits Immediately + * 0b0000..Normal operation. MASK* bits within the corresponding submodule are not updated until a FORCE_OUT event occurs within the submodule. + * 0b0001..Immediate operation. MASK* bits within the corresponding submodule are updated on the following clock edge after setting this bit. + */ #define PWM_MASK_UPDATE_MASK(x) (((uint16_t)(((uint16_t)(x)) << PWM_MASK_UPDATE_MASK_SHIFT)) & PWM_MASK_UPDATE_MASK_MASK) +/*! @} */ /*! @name SWCOUT - Software Controlled Output Register */ +/*! @{ */ #define PWM_SWCOUT_SM0OUT45_MASK (0x1U) #define PWM_SWCOUT_SM0OUT45_SHIFT (0U) +/*! SM0OUT45 - Submodule 0 Software Controlled Output 45 + * 0b0..A logic 0 is supplied to the deadtime generator of submodule 0 instead of PWM45. + * 0b1..A logic 1 is supplied to the deadtime generator of submodule 0 instead of PWM45. + */ #define PWM_SWCOUT_SM0OUT45(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM0OUT45_SHIFT)) & PWM_SWCOUT_SM0OUT45_MASK) #define PWM_SWCOUT_SM0OUT23_MASK (0x2U) #define PWM_SWCOUT_SM0OUT23_SHIFT (1U) +/*! SM0OUT23 - Submodule 0 Software Controlled Output 23 + * 0b0..A logic 0 is supplied to the deadtime generator of submodule 0 instead of PWM23. + * 0b1..A logic 1 is supplied to the deadtime generator of submodule 0 instead of PWM23. + */ #define PWM_SWCOUT_SM0OUT23(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM0OUT23_SHIFT)) & PWM_SWCOUT_SM0OUT23_MASK) #define PWM_SWCOUT_SM1OUT45_MASK (0x4U) #define PWM_SWCOUT_SM1OUT45_SHIFT (2U) +/*! SM1OUT45 - Submodule 1 Software Controlled Output 45 + * 0b0..A logic 0 is supplied to the deadtime generator of submodule 1 instead of PWM45. + * 0b1..A logic 1 is supplied to the deadtime generator of submodule 1 instead of PWM45. + */ #define PWM_SWCOUT_SM1OUT45(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM1OUT45_SHIFT)) & PWM_SWCOUT_SM1OUT45_MASK) #define PWM_SWCOUT_SM1OUT23_MASK (0x8U) #define PWM_SWCOUT_SM1OUT23_SHIFT (3U) +/*! SM1OUT23 - Submodule 1 Software Controlled Output 23 + * 0b0..A logic 0 is supplied to the deadtime generator of submodule 1 instead of PWM23. + * 0b1..A logic 1 is supplied to the deadtime generator of submodule 1 instead of PWM23. + */ #define PWM_SWCOUT_SM1OUT23(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM1OUT23_SHIFT)) & PWM_SWCOUT_SM1OUT23_MASK) #define PWM_SWCOUT_SM2OUT45_MASK (0x10U) #define PWM_SWCOUT_SM2OUT45_SHIFT (4U) +/*! SM2OUT45 - Submodule 2 Software Controlled Output 45 + * 0b0..A logic 0 is supplied to the deadtime generator of submodule 2 instead of PWM45. + * 0b1..A logic 1 is supplied to the deadtime generator of submodule 2 instead of PWM45. + */ #define PWM_SWCOUT_SM2OUT45(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM2OUT45_SHIFT)) & PWM_SWCOUT_SM2OUT45_MASK) #define PWM_SWCOUT_SM2OUT23_MASK (0x20U) #define PWM_SWCOUT_SM2OUT23_SHIFT (5U) +/*! SM2OUT23 - Submodule 2 Software Controlled Output 23 + * 0b0..A logic 0 is supplied to the deadtime generator of submodule 2 instead of PWM23. + * 0b1..A logic 1 is supplied to the deadtime generator of submodule 2 instead of PWM23. + */ #define PWM_SWCOUT_SM2OUT23(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM2OUT23_SHIFT)) & PWM_SWCOUT_SM2OUT23_MASK) #define PWM_SWCOUT_SM3OUT45_MASK (0x40U) #define PWM_SWCOUT_SM3OUT45_SHIFT (6U) +/*! SM3OUT45 - Submodule 3 Software Controlled Output 45 + * 0b0..A logic 0 is supplied to the deadtime generator of submodule 3 instead of PWM45. + * 0b1..A logic 1 is supplied to the deadtime generator of submodule 3 instead of PWM45. + */ #define PWM_SWCOUT_SM3OUT45(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM3OUT45_SHIFT)) & PWM_SWCOUT_SM3OUT45_MASK) #define PWM_SWCOUT_SM3OUT23_MASK (0x80U) #define PWM_SWCOUT_SM3OUT23_SHIFT (7U) +/*! SM3OUT23 - Submodule 3 Software Controlled Output 23 + * 0b0..A logic 0 is supplied to the deadtime generator of submodule 3 instead of PWM23. + * 0b1..A logic 1 is supplied to the deadtime generator of submodule 3 instead of PWM23. + */ #define PWM_SWCOUT_SM3OUT23(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM3OUT23_SHIFT)) & PWM_SWCOUT_SM3OUT23_MASK) +/*! @} */ /*! @name DTSRCSEL - PWM Source Select Register */ +/*! @{ */ #define PWM_DTSRCSEL_SM0SEL45_MASK (0x3U) #define PWM_DTSRCSEL_SM0SEL45_SHIFT (0U) +/*! SM0SEL45 - Submodule 0 PWM45 Control Select + * 0b00..Generated SM0PWM45 signal is used by the deadtime logic. + * 0b01..Inverted generated SM0PWM45 signal is used by the deadtime logic. + * 0b10..SWCOUT[SM0OUT45] is used by the deadtime logic. + * 0b11..PWM0_EXTB signal is used by the deadtime logic. + */ #define PWM_DTSRCSEL_SM0SEL45(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM0SEL45_SHIFT)) & PWM_DTSRCSEL_SM0SEL45_MASK) #define PWM_DTSRCSEL_SM0SEL23_MASK (0xCU) #define PWM_DTSRCSEL_SM0SEL23_SHIFT (2U) +/*! SM0SEL23 - Submodule 0 PWM23 Control Select + * 0b00..Generated SM0PWM23 signal is used by the deadtime logic. + * 0b01..Inverted generated SM0PWM23 signal is used by the deadtime logic. + * 0b10..SWCOUT[SM0OUT23] is used by the deadtime logic. + * 0b11..PWM0_EXTA signal is used by the deadtime logic. + */ #define PWM_DTSRCSEL_SM0SEL23(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM0SEL23_SHIFT)) & PWM_DTSRCSEL_SM0SEL23_MASK) #define PWM_DTSRCSEL_SM1SEL45_MASK (0x30U) #define PWM_DTSRCSEL_SM1SEL45_SHIFT (4U) +/*! SM1SEL45 - Submodule 1 PWM45 Control Select + * 0b00..Generated SM1PWM45 signal is used by the deadtime logic. + * 0b01..Inverted generated SM1PWM45 signal is used by the deadtime logic. + * 0b10..SWCOUT[SM1OUT45] is used by the deadtime logic. + * 0b11..PWM1_EXTB signal is used by the deadtime logic. + */ #define PWM_DTSRCSEL_SM1SEL45(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM1SEL45_SHIFT)) & PWM_DTSRCSEL_SM1SEL45_MASK) #define PWM_DTSRCSEL_SM1SEL23_MASK (0xC0U) #define PWM_DTSRCSEL_SM1SEL23_SHIFT (6U) +/*! SM1SEL23 - Submodule 1 PWM23 Control Select + * 0b00..Generated SM1PWM23 signal is used by the deadtime logic. + * 0b01..Inverted generated SM1PWM23 signal is used by the deadtime logic. + * 0b10..SWCOUT[SM1OUT23] is used by the deadtime logic. + * 0b11..PWM1_EXTA signal is used by the deadtime logic. + */ #define PWM_DTSRCSEL_SM1SEL23(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM1SEL23_SHIFT)) & PWM_DTSRCSEL_SM1SEL23_MASK) #define PWM_DTSRCSEL_SM2SEL45_MASK (0x300U) #define PWM_DTSRCSEL_SM2SEL45_SHIFT (8U) +/*! SM2SEL45 - Submodule 2 PWM45 Control Select + * 0b00..Generated SM2PWM45 signal is used by the deadtime logic. + * 0b01..Inverted generated SM2PWM45 signal is used by the deadtime logic. + * 0b10..SWCOUT[SM2OUT45] is used by the deadtime logic. + * 0b11..PWM2_EXTB signal is used by the deadtime logic. + */ #define PWM_DTSRCSEL_SM2SEL45(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM2SEL45_SHIFT)) & PWM_DTSRCSEL_SM2SEL45_MASK) #define PWM_DTSRCSEL_SM2SEL23_MASK (0xC00U) #define PWM_DTSRCSEL_SM2SEL23_SHIFT (10U) +/*! SM2SEL23 - Submodule 2 PWM23 Control Select + * 0b00..Generated SM2PWM23 signal is used by the deadtime logic. + * 0b01..Inverted generated SM2PWM23 signal is used by the deadtime logic. + * 0b10..SWCOUT[SM2OUT23] is used by the deadtime logic. + * 0b11..PWM2_EXTA signal is used by the deadtime logic. + */ #define PWM_DTSRCSEL_SM2SEL23(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM2SEL23_SHIFT)) & PWM_DTSRCSEL_SM2SEL23_MASK) #define PWM_DTSRCSEL_SM3SEL45_MASK (0x3000U) #define PWM_DTSRCSEL_SM3SEL45_SHIFT (12U) +/*! SM3SEL45 - Submodule 3 PWM45 Control Select + * 0b00..Generated SM3PWM45 signal is used by the deadtime logic. + * 0b01..Inverted generated SM3PWM45 signal is used by the deadtime logic. + * 0b10..SWCOUT[SM3OUT45] is used by the deadtime logic. + * 0b11..PWM3_EXTB signal is used by the deadtime logic. + */ #define PWM_DTSRCSEL_SM3SEL45(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM3SEL45_SHIFT)) & PWM_DTSRCSEL_SM3SEL45_MASK) #define PWM_DTSRCSEL_SM3SEL23_MASK (0xC000U) #define PWM_DTSRCSEL_SM3SEL23_SHIFT (14U) +/*! SM3SEL23 - Submodule 3 PWM23 Control Select + * 0b00..Generated SM3PWM23 signal is used by the deadtime logic. + * 0b01..Inverted generated SM3PWM23 signal is used by the deadtime logic. + * 0b10..SWCOUT[SM3OUT23] is used by the deadtime logic. + * 0b11..PWM3_EXTA signal is used by the deadtime logic. + */ #define PWM_DTSRCSEL_SM3SEL23(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM3SEL23_SHIFT)) & PWM_DTSRCSEL_SM3SEL23_MASK) +/*! @} */ /*! @name MCTRL - Master Control Register */ +/*! @{ */ #define PWM_MCTRL_LDOK_MASK (0xFU) #define PWM_MCTRL_LDOK_SHIFT (0U) +/*! LDOK - Load Okay + * 0b0000..Do not load new values. + * 0b0001..Load prescaler, modulus, and PWM values of the corresponding submodule. + */ #define PWM_MCTRL_LDOK(x) (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL_LDOK_SHIFT)) & PWM_MCTRL_LDOK_MASK) #define PWM_MCTRL_CLDOK_MASK (0xF0U) #define PWM_MCTRL_CLDOK_SHIFT (4U) #define PWM_MCTRL_CLDOK(x) (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL_CLDOK_SHIFT)) & PWM_MCTRL_CLDOK_MASK) #define PWM_MCTRL_RUN_MASK (0xF00U) #define PWM_MCTRL_RUN_SHIFT (8U) +/*! RUN - Run + * 0b0000..PWM generator is disabled in the corresponding submodule. + * 0b0001..PWM generator is enabled in the corresponding submodule. + */ #define PWM_MCTRL_RUN(x) (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL_RUN_SHIFT)) & PWM_MCTRL_RUN_MASK) #define PWM_MCTRL_IPOL_MASK (0xF000U) #define PWM_MCTRL_IPOL_SHIFT (12U) +/*! IPOL - Current Polarity + * 0b0000..PWM23 is used to generate complementary PWM pair in the corresponding submodule. + * 0b0001..PWM45 is used to generate complementary PWM pair in the corresponding submodule. + */ #define PWM_MCTRL_IPOL(x) (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL_IPOL_SHIFT)) & PWM_MCTRL_IPOL_MASK) +/*! @} */ /*! @name MCTRL2 - Master Control 2 Register */ +/*! @{ */ #define PWM_MCTRL2_MONPLL_MASK (0x3U) #define PWM_MCTRL2_MONPLL_SHIFT (0U) +/*! MONPLL - Monitor PLL State + * 0b00..Not locked. Do not monitor PLL operation. Resetting of the fractional delay block in case of PLL losing lock will be controlled by software. + * 0b01..Not locked. Monitor PLL operation to automatically disable the fractional delay block when the PLL encounters problems. + * 0b10..Locked. Do not monitor PLL operation. Resetting of the fractional delay block in case of PLL losing lock will be controlled by software. These bits are write protected until the next reset. + * 0b11..Locked. Monitor PLL operation to automatically disable the fractional delay block when the PLL encounters problems. These bits are write protected until the next reset. + */ #define PWM_MCTRL2_MONPLL(x) (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL2_MONPLL_SHIFT)) & PWM_MCTRL2_MONPLL_MASK) +/*! @} */ /*! @name FCTRL - Fault Control Register */ +/*! @{ */ #define PWM_FCTRL_FIE_MASK (0xFU) #define PWM_FCTRL_FIE_SHIFT (0U) +/*! FIE - Fault Interrupt Enables + * 0b0000..FAULTx CPU interrupt requests disabled. + * 0b0001..FAULTx CPU interrupt requests enabled. + */ #define PWM_FCTRL_FIE(x) (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL_FIE_SHIFT)) & PWM_FCTRL_FIE_MASK) #define PWM_FCTRL_FSAFE_MASK (0xF0U) #define PWM_FCTRL_FSAFE_SHIFT (4U) +/*! FSAFE - Fault Safety Mode + * 0b0000..Normal mode. PWM outputs disabled by this fault are not enabled until FSTS[FFLAGx] is clear at the start of a half cycle or full cycle depending on the state of FSTS[FFULL] without regard to the state of FSTS[FFPINx]. The PWM outputs disabled by this fault input will not be re-enabled until the actual FAULTx input signal de-asserts since the fault input will combinationally disable the PWM outputs (as programmed in DISMAPn). + * 0b0001..Safe mode. PWM outputs disabled by this fault are not enabled until FSTS[FFLAGx] is clear and FSTS[FFPINx] is clear at the start of a half cycle or full cycle depending on the state of FSTS[FFULL]. + */ #define PWM_FCTRL_FSAFE(x) (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL_FSAFE_SHIFT)) & PWM_FCTRL_FSAFE_MASK) #define PWM_FCTRL_FAUTO_MASK (0xF00U) #define PWM_FCTRL_FAUTO_SHIFT (8U) +/*! FAUTO - Automatic Fault Clearing + * 0b0000..Manual fault clearing. PWM outputs disabled by this fault are not enabled until FSTS[FFLAGx] is clear at the start of a half cycle or full cycle depending the state of FSTS[FFULL]. This is further controlled by FCTRL[FSAFE]. + * 0b0001..Automatic fault clearing. PWM outputs disabled by this fault are enabled when FSTS[FFPINx] is clear at the start of a half cycle or full cycle depending on the state of FSTS[FFULL] without regard to the state of FSTS[FFLAGx]. + */ #define PWM_FCTRL_FAUTO(x) (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL_FAUTO_SHIFT)) & PWM_FCTRL_FAUTO_MASK) #define PWM_FCTRL_FLVL_MASK (0xF000U) #define PWM_FCTRL_FLVL_SHIFT (12U) +/*! FLVL - Fault Level + * 0b0000..A logic 0 on the fault input indicates a fault condition. + * 0b0001..A logic 1 on the fault input indicates a fault condition. + */ #define PWM_FCTRL_FLVL(x) (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL_FLVL_SHIFT)) & PWM_FCTRL_FLVL_MASK) +/*! @} */ /*! @name FSTS - Fault Status Register */ +/*! @{ */ #define PWM_FSTS_FFLAG_MASK (0xFU) #define PWM_FSTS_FFLAG_SHIFT (0U) +/*! FFLAG - Fault Flags + * 0b0000..No fault on the FAULTx pin. + * 0b0001..Fault on the FAULTx pin. + */ #define PWM_FSTS_FFLAG(x) (((uint16_t)(((uint16_t)(x)) << PWM_FSTS_FFLAG_SHIFT)) & PWM_FSTS_FFLAG_MASK) #define PWM_FSTS_FFULL_MASK (0xF0U) #define PWM_FSTS_FFULL_SHIFT (4U) +/*! FFULL - Full Cycle + * 0b0000..PWM outputs are not re-enabled at the start of a full cycle + * 0b0001..PWM outputs are re-enabled at the start of a full cycle + */ #define PWM_FSTS_FFULL(x) (((uint16_t)(((uint16_t)(x)) << PWM_FSTS_FFULL_SHIFT)) & PWM_FSTS_FFULL_MASK) #define PWM_FSTS_FFPIN_MASK (0xF00U) #define PWM_FSTS_FFPIN_SHIFT (8U) #define PWM_FSTS_FFPIN(x) (((uint16_t)(((uint16_t)(x)) << PWM_FSTS_FFPIN_SHIFT)) & PWM_FSTS_FFPIN_MASK) #define PWM_FSTS_FHALF_MASK (0xF000U) #define PWM_FSTS_FHALF_SHIFT (12U) +/*! FHALF - Half Cycle Fault Recovery + * 0b0000..PWM outputs are not re-enabled at the start of a half cycle. + * 0b0001..PWM outputs are re-enabled at the start of a half cycle (as defined by VAL0). + */ #define PWM_FSTS_FHALF(x) (((uint16_t)(((uint16_t)(x)) << PWM_FSTS_FHALF_SHIFT)) & PWM_FSTS_FHALF_MASK) +/*! @} */ /*! @name FFILT - Fault Filter Register */ +/*! @{ */ #define PWM_FFILT_FILT_PER_MASK (0xFFU) #define PWM_FFILT_FILT_PER_SHIFT (0U) #define PWM_FFILT_FILT_PER(x) (((uint16_t)(((uint16_t)(x)) << PWM_FFILT_FILT_PER_SHIFT)) & PWM_FFILT_FILT_PER_MASK) @@ -16548,17 +27014,34 @@ typedef struct { #define PWM_FFILT_FILT_CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_FFILT_FILT_CNT_SHIFT)) & PWM_FFILT_FILT_CNT_MASK) #define PWM_FFILT_GSTR_MASK (0x8000U) #define PWM_FFILT_GSTR_SHIFT (15U) +/*! GSTR - Fault Glitch Stretch Enable + * 0b0..Fault input glitch stretching is disabled. + * 0b1..Input fault signals will be stretched to at least 2 IPBus clock cycles. + */ #define PWM_FFILT_GSTR(x) (((uint16_t)(((uint16_t)(x)) << PWM_FFILT_GSTR_SHIFT)) & PWM_FFILT_GSTR_MASK) +/*! @} */ /*! @name FTST - Fault Test Register */ +/*! @{ */ #define PWM_FTST_FTEST_MASK (0x1U) #define PWM_FTST_FTEST_SHIFT (0U) +/*! FTEST - Fault Test + * 0b0..No fault + * 0b1..Cause a simulated fault + */ #define PWM_FTST_FTEST(x) (((uint16_t)(((uint16_t)(x)) << PWM_FTST_FTEST_SHIFT)) & PWM_FTST_FTEST_MASK) +/*! @} */ /*! @name FCTRL2 - Fault Control 2 Register */ +/*! @{ */ #define PWM_FCTRL2_NOCOMB_MASK (0xFU) #define PWM_FCTRL2_NOCOMB_SHIFT (0U) +/*! NOCOMB - No Combinational Path From Fault Input To PWM Output + * 0b0000..There is a combinational link from the fault inputs to the PWM outputs. The fault inputs are combined with the filtered and latched fault signals to disable the PWM outputs. + * 0b0001..The direct combinational path from the fault inputs to the PWM outputs is disabled and the filtered and latched fault signals are used to disable the PWM outputs. + */ #define PWM_FCTRL2_NOCOMB(x) (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL2_NOCOMB_SHIFT)) & PWM_FCTRL2_NOCOMB_MASK) +/*! @} */ /*! @@ -16630,44 +27113,79 @@ typedef struct { */ /*! @name ROMPATCHD - ROMC Data Registers */ +/*! @{ */ #define ROMC_ROMPATCHD_DATAX_MASK (0xFFFFFFFFU) #define ROMC_ROMPATCHD_DATAX_SHIFT (0U) #define ROMC_ROMPATCHD_DATAX(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHD_DATAX_SHIFT)) & ROMC_ROMPATCHD_DATAX_MASK) +/*! @} */ /* The count of ROMC_ROMPATCHD */ #define ROMC_ROMPATCHD_COUNT (8U) /*! @name ROMPATCHCNTL - ROMC Control Register */ +/*! @{ */ #define ROMC_ROMPATCHCNTL_DATAFIX_MASK (0xFFU) #define ROMC_ROMPATCHCNTL_DATAFIX_SHIFT (0U) +/*! DATAFIX + * 0b00000000..Address comparator triggers a opcode patch + * 0b00000001..Address comparator triggers a data fix + */ #define ROMC_ROMPATCHCNTL_DATAFIX(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHCNTL_DATAFIX_SHIFT)) & ROMC_ROMPATCHCNTL_DATAFIX_MASK) #define ROMC_ROMPATCHCNTL_DIS_MASK (0x20000000U) #define ROMC_ROMPATCHCNTL_DIS_SHIFT (29U) +/*! DIS + * 0b0..Does not affect any ROMC functions (default) + * 0b1..Disable all ROMC functions: data fixing, and opcode patching + */ #define ROMC_ROMPATCHCNTL_DIS(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHCNTL_DIS_SHIFT)) & ROMC_ROMPATCHCNTL_DIS_MASK) +/*! @} */ /*! @name ROMPATCHENL - ROMC Enable Register Low */ +/*! @{ */ #define ROMC_ROMPATCHENL_ENABLE_MASK (0xFFFFU) #define ROMC_ROMPATCHENL_ENABLE_SHIFT (0U) +/*! ENABLE + * 0b0000000000000000..Address comparator disabled + * 0b0000000000000001..Address comparator enabled, ROMC will trigger a opcode patch or data fix event upon matching of the associated address + */ #define ROMC_ROMPATCHENL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHENL_ENABLE_SHIFT)) & ROMC_ROMPATCHENL_ENABLE_MASK) +/*! @} */ /*! @name ROMPATCHA - ROMC Address Registers */ +/*! @{ */ #define ROMC_ROMPATCHA_THUMBX_MASK (0x1U) #define ROMC_ROMPATCHA_THUMBX_SHIFT (0U) +/*! THUMBX + * 0b0..Arm patch + * 0b1..THUMB patch (ignore if data fix) + */ #define ROMC_ROMPATCHA_THUMBX(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHA_THUMBX_SHIFT)) & ROMC_ROMPATCHA_THUMBX_MASK) #define ROMC_ROMPATCHA_ADDRX_MASK (0x7FFFFEU) #define ROMC_ROMPATCHA_ADDRX_SHIFT (1U) #define ROMC_ROMPATCHA_ADDRX(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHA_ADDRX_SHIFT)) & ROMC_ROMPATCHA_ADDRX_MASK) +/*! @} */ /* The count of ROMC_ROMPATCHA */ #define ROMC_ROMPATCHA_COUNT (16U) /*! @name ROMPATCHSR - ROMC Status Register */ +/*! @{ */ #define ROMC_ROMPATCHSR_SOURCE_MASK (0x3FU) #define ROMC_ROMPATCHSR_SOURCE_SHIFT (0U) +/*! SOURCE + * 0b000000..Address Comparator 0 matched + * 0b000001..Address Comparator 1 matched + * 0b001111..Address Comparator 15 matched + */ #define ROMC_ROMPATCHSR_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHSR_SOURCE_SHIFT)) & ROMC_ROMPATCHSR_SOURCE_MASK) #define ROMC_ROMPATCHSR_SW_MASK (0x20000U) #define ROMC_ROMPATCHSR_SW_SHIFT (17U) +/*! SW + * 0b0..no event or comparator collisions + * 0b1..a collision has occurred + */ #define ROMC_ROMPATCHSR_SW(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHSR_SW_SHIFT)) & ROMC_ROMPATCHSR_SW_MASK) +/*! @} */ /*! @@ -16717,72 +27235,140 @@ typedef struct { */ /*! @name CS - Watchdog Control and Status Register */ +/*! @{ */ #define RTWDOG_CS_STOP_MASK (0x1U) #define RTWDOG_CS_STOP_SHIFT (0U) +/*! STOP - Stop Enable + * 0b0..Watchdog disabled in chip stop mode. + * 0b1..Watchdog enabled in chip stop mode. + */ #define RTWDOG_CS_STOP(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_STOP_SHIFT)) & RTWDOG_CS_STOP_MASK) #define RTWDOG_CS_WAIT_MASK (0x2U) #define RTWDOG_CS_WAIT_SHIFT (1U) +/*! WAIT - Wait Enable + * 0b0..Watchdog disabled in chip wait mode. + * 0b1..Watchdog enabled in chip wait mode. + */ #define RTWDOG_CS_WAIT(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_WAIT_SHIFT)) & RTWDOG_CS_WAIT_MASK) #define RTWDOG_CS_DBG_MASK (0x4U) #define RTWDOG_CS_DBG_SHIFT (2U) +/*! DBG - Debug Enable + * 0b0..Watchdog disabled in chip debug mode. + * 0b1..Watchdog enabled in chip debug mode. + */ #define RTWDOG_CS_DBG(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_DBG_SHIFT)) & RTWDOG_CS_DBG_MASK) #define RTWDOG_CS_TST_MASK (0x18U) #define RTWDOG_CS_TST_SHIFT (3U) +/*! TST - Watchdog Test + * 0b00..Watchdog test mode disabled. + * 0b01..Watchdog user mode enabled. (Watchdog test mode disabled.) After testing the watchdog, software should use this setting to indicate that the watchdog is functioning normally in user mode. + * 0b10..Watchdog test mode enabled, only the low byte is used. CNT[CNTLOW] is compared with TOVAL[TOVALLOW]. + * 0b11..Watchdog test mode enabled, only the high byte is used. CNT[CNTHIGH] is compared with TOVAL[TOVALHIGH]. + */ #define RTWDOG_CS_TST(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_TST_SHIFT)) & RTWDOG_CS_TST_MASK) #define RTWDOG_CS_UPDATE_MASK (0x20U) #define RTWDOG_CS_UPDATE_SHIFT (5U) +/*! UPDATE - Allow updates + * 0b0..Updates not allowed. After the initial configuration, the watchdog cannot be later modified without forcing a reset. + * 0b1..Updates allowed. Software can modify the watchdog configuration registers within 128 bus clocks after performing the unlock write sequence. + */ #define RTWDOG_CS_UPDATE(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_UPDATE_SHIFT)) & RTWDOG_CS_UPDATE_MASK) #define RTWDOG_CS_INT_MASK (0x40U) #define RTWDOG_CS_INT_SHIFT (6U) +/*! INT - Watchdog Interrupt + * 0b0..Watchdog interrupts are disabled. Watchdog resets are not delayed. + * 0b1..Watchdog interrupts are enabled. Watchdog resets are delayed by 128 bus clocks from the interrupt vector fetch. + */ #define RTWDOG_CS_INT(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_INT_SHIFT)) & RTWDOG_CS_INT_MASK) #define RTWDOG_CS_EN_MASK (0x80U) #define RTWDOG_CS_EN_SHIFT (7U) +/*! EN - Watchdog Enable + * 0b0..Watchdog disabled. + * 0b1..Watchdog enabled. + */ #define RTWDOG_CS_EN(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_EN_SHIFT)) & RTWDOG_CS_EN_MASK) #define RTWDOG_CS_CLK_MASK (0x300U) #define RTWDOG_CS_CLK_SHIFT (8U) +/*! CLK - Watchdog Clock + * 0b00..Bus clock + * 0b01..LPO clock + * 0b10..INTCLK (internal clock) + * 0b11..ERCLK (external reference clock) + */ #define RTWDOG_CS_CLK(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_CLK_SHIFT)) & RTWDOG_CS_CLK_MASK) #define RTWDOG_CS_RCS_MASK (0x400U) #define RTWDOG_CS_RCS_SHIFT (10U) +/*! RCS - Reconfiguration Success + * 0b0..Reconfiguring WDOG. + * 0b1..Reconfiguration is successful. + */ #define RTWDOG_CS_RCS(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_RCS_SHIFT)) & RTWDOG_CS_RCS_MASK) #define RTWDOG_CS_ULK_MASK (0x800U) #define RTWDOG_CS_ULK_SHIFT (11U) +/*! ULK - Unlock status + * 0b0..WDOG is locked. + * 0b1..WDOG is unlocked. + */ #define RTWDOG_CS_ULK(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_ULK_SHIFT)) & RTWDOG_CS_ULK_MASK) #define RTWDOG_CS_PRES_MASK (0x1000U) #define RTWDOG_CS_PRES_SHIFT (12U) +/*! PRES - Watchdog prescaler + * 0b0..256 prescaler disabled. + * 0b1..256 prescaler enabled. + */ #define RTWDOG_CS_PRES(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_PRES_SHIFT)) & RTWDOG_CS_PRES_MASK) #define RTWDOG_CS_CMD32EN_MASK (0x2000U) #define RTWDOG_CS_CMD32EN_SHIFT (13U) +/*! CMD32EN - Enables or disables WDOG support for 32-bit (otherwise 16-bit or 8-bit) refresh/unlock command write words + * 0b0..Disables support for 32-bit refresh/unlock command write words. Only 16-bit or 8-bit is supported. + * 0b1..Enables support for 32-bit refresh/unlock command write words. 16-bit or 8-bit is NOT supported. + */ #define RTWDOG_CS_CMD32EN(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_CMD32EN_SHIFT)) & RTWDOG_CS_CMD32EN_MASK) #define RTWDOG_CS_FLG_MASK (0x4000U) #define RTWDOG_CS_FLG_SHIFT (14U) +/*! FLG - Watchdog Interrupt Flag + * 0b0..No interrupt occurred. + * 0b1..An interrupt occurred. + */ #define RTWDOG_CS_FLG(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_FLG_SHIFT)) & RTWDOG_CS_FLG_MASK) #define RTWDOG_CS_WIN_MASK (0x8000U) #define RTWDOG_CS_WIN_SHIFT (15U) +/*! WIN - Watchdog Window + * 0b0..Window mode disabled. + * 0b1..Window mode enabled. + */ #define RTWDOG_CS_WIN(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_WIN_SHIFT)) & RTWDOG_CS_WIN_MASK) +/*! @} */ /*! @name CNT - Watchdog Counter Register */ +/*! @{ */ #define RTWDOG_CNT_CNTLOW_MASK (0xFFU) #define RTWDOG_CNT_CNTLOW_SHIFT (0U) #define RTWDOG_CNT_CNTLOW(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CNT_CNTLOW_SHIFT)) & RTWDOG_CNT_CNTLOW_MASK) #define RTWDOG_CNT_CNTHIGH_MASK (0xFF00U) #define RTWDOG_CNT_CNTHIGH_SHIFT (8U) #define RTWDOG_CNT_CNTHIGH(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CNT_CNTHIGH_SHIFT)) & RTWDOG_CNT_CNTHIGH_MASK) +/*! @} */ /*! @name TOVAL - Watchdog Timeout Value Register */ +/*! @{ */ #define RTWDOG_TOVAL_TOVALLOW_MASK (0xFFU) #define RTWDOG_TOVAL_TOVALLOW_SHIFT (0U) #define RTWDOG_TOVAL_TOVALLOW(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_TOVAL_TOVALLOW_SHIFT)) & RTWDOG_TOVAL_TOVALLOW_MASK) #define RTWDOG_TOVAL_TOVALHIGH_MASK (0xFF00U) #define RTWDOG_TOVAL_TOVALHIGH_SHIFT (8U) #define RTWDOG_TOVAL_TOVALHIGH(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_TOVAL_TOVALHIGH_SHIFT)) & RTWDOG_TOVAL_TOVALHIGH_MASK) +/*! @} */ /*! @name WIN - Watchdog Window Register */ +/*! @{ */ #define RTWDOG_WIN_WINLOW_MASK (0xFFU) #define RTWDOG_WIN_WINLOW_SHIFT (0U) #define RTWDOG_WIN_WINLOW(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_WIN_WINLOW_SHIFT)) & RTWDOG_WIN_WINLOW_MASK) #define RTWDOG_WIN_WINHIGH_MASK (0xFF00U) #define RTWDOG_WIN_WINHIGH_SHIFT (8U) #define RTWDOG_WIN_WINHIGH(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_WIN_WINHIGH_SHIFT)) & RTWDOG_WIN_WINHIGH_MASK) +/*! @} */ /*! @@ -16885,49 +27471,135 @@ typedef struct { */ /*! @name MCR - Module Control Register */ +/*! @{ */ #define SEMC_MCR_SWRST_MASK (0x1U) #define SEMC_MCR_SWRST_SHIFT (0U) #define SEMC_MCR_SWRST(x) (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_SWRST_SHIFT)) & SEMC_MCR_SWRST_MASK) #define SEMC_MCR_MDIS_MASK (0x2U) #define SEMC_MCR_MDIS_SHIFT (1U) +/*! MDIS - Module Disable + * 0b0..Module enabled + * 0b1..Module disabled. + */ #define SEMC_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_MDIS_SHIFT)) & SEMC_MCR_MDIS_MASK) #define SEMC_MCR_DQSMD_MASK (0x4U) #define SEMC_MCR_DQSMD_SHIFT (2U) +/*! DQSMD - DQS (read strobe) mode + * 0b0..Dummy read strobe loopbacked internally + * 0b1..Dummy read strobe loopbacked from DQS pad + */ #define SEMC_MCR_DQSMD(x) (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_DQSMD_SHIFT)) & SEMC_MCR_DQSMD_MASK) #define SEMC_MCR_WPOL0_MASK (0x40U) #define SEMC_MCR_WPOL0_SHIFT (6U) +/*! WPOL0 - WAIT/RDY# polarity for NOR/PSRAM + * 0b0..Low active + * 0b1..High active + */ #define SEMC_MCR_WPOL0(x) (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_WPOL0_SHIFT)) & SEMC_MCR_WPOL0_MASK) #define SEMC_MCR_WPOL1_MASK (0x80U) #define SEMC_MCR_WPOL1_SHIFT (7U) +/*! WPOL1 - WAIT/RDY# polarity for NAND + * 0b0..Low active + * 0b1..High active + */ #define SEMC_MCR_WPOL1(x) (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_WPOL1_SHIFT)) & SEMC_MCR_WPOL1_MASK) #define SEMC_MCR_CTO_MASK (0xFF0000U) #define SEMC_MCR_CTO_SHIFT (16U) #define SEMC_MCR_CTO(x) (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_CTO_SHIFT)) & SEMC_MCR_CTO_MASK) #define SEMC_MCR_BTO_MASK (0x1F000000U) #define SEMC_MCR_BTO_SHIFT (24U) +/*! BTO - Bus timeout cycles + * 0b00000..255*1 + * 0b00001-0b11110..255*2 - 255*2^30 + * 0b11111..255*2^31 + */ #define SEMC_MCR_BTO(x) (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_BTO_SHIFT)) & SEMC_MCR_BTO_MASK) +/*! @} */ /*! @name IOCR - IO Mux Control Register */ +/*! @{ */ #define SEMC_IOCR_MUX_A8_MASK (0x7U) #define SEMC_IOCR_MUX_A8_SHIFT (0U) +/*! MUX_A8 - SEMC_A8 output selection + * 0b000..SDRAM Address bit (A8) + * 0b001..NAND CE# + * 0b010..NOR CE# + * 0b011..PSRAM CE# + * 0b100..DBI CSX + * 0b101..SDRAM Address bit (A8) + * 0b110..SDRAM Address bit (A8) + * 0b111..SDRAM Address bit (A8) + */ #define SEMC_IOCR_MUX_A8(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_A8_SHIFT)) & SEMC_IOCR_MUX_A8_MASK) #define SEMC_IOCR_MUX_CSX0_MASK (0x38U) #define SEMC_IOCR_MUX_CSX0_SHIFT (3U) +/*! MUX_CSX0 - SEMC_CSX0 output selection + * 0b000..NOR/PSRAM Address bit 24 (A24) + * 0b001..SDRAM CS1 + * 0b010..SDRAM CS2 + * 0b011..SDRAM CS3 + * 0b100..NAND CE# + * 0b101..NOR CE# + * 0b110..PSRAM CE# + * 0b111..DBI CSX + */ #define SEMC_IOCR_MUX_CSX0(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_CSX0_SHIFT)) & SEMC_IOCR_MUX_CSX0_MASK) #define SEMC_IOCR_MUX_CSX1_MASK (0x1C0U) #define SEMC_IOCR_MUX_CSX1_SHIFT (6U) +/*! MUX_CSX1 - SEMC_CSX1 output selection + * 0b000..NOR/PSRAM Address bit 25 (A25) + * 0b001..SDRAM CS1 + * 0b010..SDRAM CS2 + * 0b011..SDRAM CS3 + * 0b100..NAND CE# + * 0b101..NOR CE# + * 0b110..PSRAM CE# + * 0b111..DBI CSX + */ #define SEMC_IOCR_MUX_CSX1(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_CSX1_SHIFT)) & SEMC_IOCR_MUX_CSX1_MASK) #define SEMC_IOCR_MUX_CSX2_MASK (0xE00U) #define SEMC_IOCR_MUX_CSX2_SHIFT (9U) +/*! MUX_CSX2 - SEMC_CSX2 output selection + * 0b000..NOR/PSRAM Address bit 26 (A26) + * 0b001..SDRAM CS1 + * 0b010..SDRAM CS2 + * 0b011..SDRAM CS3 + * 0b100..NAND CE# + * 0b101..NOR CE# + * 0b110..PSRAM CE# + * 0b111..DBI CSX + */ #define SEMC_IOCR_MUX_CSX2(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_CSX2_SHIFT)) & SEMC_IOCR_MUX_CSX2_MASK) #define SEMC_IOCR_MUX_CSX3_MASK (0x7000U) #define SEMC_IOCR_MUX_CSX3_SHIFT (12U) +/*! MUX_CSX3 - SEMC_CSX3 output selection + * 0b000..NOR/PSRAM Address bit 27 (A27) + * 0b001..SDRAM CS1 + * 0b010..SDRAM CS2 + * 0b011..SDRAM CS3 + * 0b100..NAND CE# + * 0b101..NOR CE# + * 0b110..PSRAM CE# + * 0b111..DBI CSX + */ #define SEMC_IOCR_MUX_CSX3(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_CSX3_SHIFT)) & SEMC_IOCR_MUX_CSX3_MASK) #define SEMC_IOCR_MUX_RDY_MASK (0x38000U) #define SEMC_IOCR_MUX_RDY_SHIFT (15U) +/*! MUX_RDY - SEMC_RDY function selection + * 0b000..NAND Ready/Wait# input + * 0b001..SDRAM CS1 + * 0b010..SDRAM CS2 + * 0b011..SDRAM CS3 + * 0b100..NOR CE# + * 0b101..PSRAM CE# + * 0b110..DBI CSX + * 0b111..NOR/PSRAM Address bit 27 + */ #define SEMC_IOCR_MUX_RDY(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_RDY_SHIFT)) & SEMC_IOCR_MUX_RDY_MASK) +/*! @} */ /*! @name BMCR0 - Master Bus (AXI) Control Register 0 */ +/*! @{ */ #define SEMC_BMCR0_WQOS_MASK (0xFU) #define SEMC_BMCR0_WQOS_SHIFT (0U) #define SEMC_BMCR0_WQOS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR0_WQOS_SHIFT)) & SEMC_BMCR0_WQOS_MASK) @@ -16940,8 +27612,10 @@ typedef struct { #define SEMC_BMCR0_WRWS_MASK (0xFF0000U) #define SEMC_BMCR0_WRWS_SHIFT (16U) #define SEMC_BMCR0_WRWS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR0_WRWS_SHIFT)) & SEMC_BMCR0_WRWS_MASK) +/*! @} */ /*! @name BMCR1 - Master Bus (AXI) Control Register 1 */ +/*! @{ */ #define SEMC_BMCR1_WQOS_MASK (0xFU) #define SEMC_BMCR1_WQOS_SHIFT (0U) #define SEMC_BMCR1_WQOS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR1_WQOS_SHIFT)) & SEMC_BMCR1_WQOS_MASK) @@ -16957,22 +27631,60 @@ typedef struct { #define SEMC_BMCR1_WBR_MASK (0xFF000000U) #define SEMC_BMCR1_WBR_SHIFT (24U) #define SEMC_BMCR1_WBR(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR1_WBR_SHIFT)) & SEMC_BMCR1_WBR_MASK) +/*! @} */ /*! @name BR - Base Register 0 (For SDRAM CS0 device)..Base Register 8 (For NAND device) */ +/*! @{ */ #define SEMC_BR_VLD_MASK (0x1U) #define SEMC_BR_VLD_SHIFT (0U) #define SEMC_BR_VLD(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BR_VLD_SHIFT)) & SEMC_BR_VLD_MASK) #define SEMC_BR_MS_MASK (0x3EU) #define SEMC_BR_MS_SHIFT (1U) +/*! MS - Memory size + * 0b00000..4KB + * 0b00001..8KB + * 0b00010..16KB + * 0b00011..32KB + * 0b00100..64KB + * 0b00101..128KB + * 0b00110..256KB + * 0b00111..512KB + * 0b01000..1MB + * 0b01001..2MB + * 0b01010..4MB + * 0b01011..8MB + * 0b01100..16MB + * 0b01101..32MB + * 0b01110..64MB + * 0b01111..128MB + * 0b10000..256MB + * 0b10001..512MB + * 0b10010..1GB + * 0b10011..2GB + * 0b10100..4GB + * 0b10101..4GB + * 0b10110..4GB + * 0b10111..4GB + * 0b11000..4GB + * 0b11001..4GB + * 0b11010..4GB + * 0b11011..4GB + * 0b11100..4GB + * 0b11101..4GB + * 0b11110..4GB + * 0b11111..4GB + */ #define SEMC_BR_MS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BR_MS_SHIFT)) & SEMC_BR_MS_MASK) #define SEMC_BR_BA_MASK (0xFFFFF000U) #define SEMC_BR_BA_SHIFT (12U) #define SEMC_BR_BA(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BR_BA_SHIFT)) & SEMC_BR_BA_MASK) +/*! @} */ /* The count of SEMC_BR */ #define SEMC_BR_COUNT (9U) /*! @name INTEN - Interrupt Enable Register */ +/*! @{ */ #define SEMC_INTEN_IPCMDDONEEN_MASK (0x1U) #define SEMC_INTEN_IPCMDDONEEN_SHIFT (0U) #define SEMC_INTEN_IPCMDDONEEN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_IPCMDDONEEN_SHIFT)) & SEMC_INTEN_IPCMDDONEEN_MASK) @@ -16987,12 +27699,22 @@ typedef struct { #define SEMC_INTEN_AXIBUSERREN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_AXIBUSERREN_SHIFT)) & SEMC_INTEN_AXIBUSERREN_MASK) #define SEMC_INTEN_NDPAGEENDEN_MASK (0x10U) #define SEMC_INTEN_NDPAGEENDEN_SHIFT (4U) +/*! NDPAGEENDEN - This bit enable/disable the NDPAGEEND interrupt generation. + * 0b0..Disable + * 0b1..Enable + */ #define SEMC_INTEN_NDPAGEENDEN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_NDPAGEENDEN_SHIFT)) & SEMC_INTEN_NDPAGEENDEN_MASK) #define SEMC_INTEN_NDNOPENDEN_MASK (0x20U) #define SEMC_INTEN_NDNOPENDEN_SHIFT (5U) +/*! NDNOPENDEN - This bit enable/disable the NDNOPEND interrupt generation. + * 0b0..Disable + * 0b1..Enable + */ #define SEMC_INTEN_NDNOPENDEN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_NDNOPENDEN_SHIFT)) & SEMC_INTEN_NDNOPENDEN_MASK) +/*! @} */ /*! @name INTR - Interrupt Enable Register */ +/*! @{ */ #define SEMC_INTR_IPCMDDONE_MASK (0x1U) #define SEMC_INTR_IPCMDDONE_SHIFT (0U) #define SEMC_INTR_IPCMDDONE(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_IPCMDDONE_SHIFT)) & SEMC_INTR_IPCMDDONE_MASK) @@ -17011,22 +27733,52 @@ typedef struct { #define SEMC_INTR_NDNOPEND_MASK (0x20U) #define SEMC_INTR_NDNOPEND_SHIFT (5U) #define SEMC_INTR_NDNOPEND(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_NDNOPEND_SHIFT)) & SEMC_INTR_NDNOPEND_MASK) +/*! @} */ /*! @name SDRAMCR0 - SDRAM control register 0 */ +/*! @{ */ #define SEMC_SDRAMCR0_PS_MASK (0x1U) #define SEMC_SDRAMCR0_PS_SHIFT (0U) +/*! PS - Port Size + * 0b0..8bit + * 0b1..16bit + */ #define SEMC_SDRAMCR0_PS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR0_PS_SHIFT)) & SEMC_SDRAMCR0_PS_MASK) #define SEMC_SDRAMCR0_BL_MASK (0x70U) #define SEMC_SDRAMCR0_BL_SHIFT (4U) +/*! BL - Burst Length + * 0b000..1 + * 0b001..2 + * 0b010..4 + * 0b011..8 + * 0b100..8 + * 0b101..8 + * 0b110..8 + * 0b111..8 + */ #define SEMC_SDRAMCR0_BL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR0_BL_SHIFT)) & SEMC_SDRAMCR0_BL_MASK) #define SEMC_SDRAMCR0_COL_MASK (0x300U) #define SEMC_SDRAMCR0_COL_SHIFT (8U) +/*! COL - Column address bit number + * 0b00..12 bit + * 0b01..11 bit + * 0b10..10 bit + * 0b11..9 bit + */ #define SEMC_SDRAMCR0_COL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR0_COL_SHIFT)) & SEMC_SDRAMCR0_COL_MASK) #define SEMC_SDRAMCR0_CL_MASK (0xC00U) #define SEMC_SDRAMCR0_CL_SHIFT (10U) +/*! CL - CAS Latency + * 0b00..1 + * 0b01..1 + * 0b10..2 + * 0b11..3 + */ #define SEMC_SDRAMCR0_CL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR0_CL_SHIFT)) & SEMC_SDRAMCR0_CL_MASK) +/*! @} */ /*! @name SDRAMCR1 - SDRAM control register 1 */ +/*! @{ */ #define SEMC_SDRAMCR1_PRE2ACT_MASK (0xFU) #define SEMC_SDRAMCR1_PRE2ACT_SHIFT (0U) #define SEMC_SDRAMCR1_PRE2ACT(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR1_PRE2ACT_SHIFT)) & SEMC_SDRAMCR1_PRE2ACT_MASK) @@ -17045,8 +27797,10 @@ typedef struct { #define SEMC_SDRAMCR1_ACT2PRE_MASK (0xF00000U) #define SEMC_SDRAMCR1_ACT2PRE_SHIFT (20U) #define SEMC_SDRAMCR1_ACT2PRE(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR1_ACT2PRE_SHIFT)) & SEMC_SDRAMCR1_ACT2PRE_MASK) +/*! @} */ /*! @name SDRAMCR2 - SDRAM control register 2 */ +/*! @{ */ #define SEMC_SDRAMCR2_SRRC_MASK (0xFFU) #define SEMC_SDRAMCR2_SRRC_SHIFT (0U) #define SEMC_SDRAMCR2_SRRC(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR2_SRRC_SHIFT)) & SEMC_SDRAMCR2_SRRC_MASK) @@ -17058,40 +27812,100 @@ typedef struct { #define SEMC_SDRAMCR2_ACT2ACT(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR2_ACT2ACT_SHIFT)) & SEMC_SDRAMCR2_ACT2ACT_MASK) #define SEMC_SDRAMCR2_ITO_MASK (0xFF000000U) #define SEMC_SDRAMCR2_ITO_SHIFT (24U) +/*! ITO - SDRAM Idle timeout + * 0b00000000..IDLE timeout period is 256*Prescale period. + * 0b00000001-0b11111111..IDLE timeout period is ITO*Prescale period. + */ #define SEMC_SDRAMCR2_ITO(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR2_ITO_SHIFT)) & SEMC_SDRAMCR2_ITO_MASK) +/*! @} */ /*! @name SDRAMCR3 - SDRAM control register 3 */ +/*! @{ */ #define SEMC_SDRAMCR3_REN_MASK (0x1U) #define SEMC_SDRAMCR3_REN_SHIFT (0U) #define SEMC_SDRAMCR3_REN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR3_REN_SHIFT)) & SEMC_SDRAMCR3_REN_MASK) #define SEMC_SDRAMCR3_REBL_MASK (0xEU) #define SEMC_SDRAMCR3_REBL_SHIFT (1U) +/*! REBL - Refresh burst length + * 0b000..1 + * 0b001..2 + * 0b010..3 + * 0b011..4 + * 0b100..5 + * 0b101..6 + * 0b110..7 + * 0b111..8 + */ #define SEMC_SDRAMCR3_REBL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR3_REBL_SHIFT)) & SEMC_SDRAMCR3_REBL_MASK) #define SEMC_SDRAMCR3_PRESCALE_MASK (0xFF00U) #define SEMC_SDRAMCR3_PRESCALE_SHIFT (8U) +/*! PRESCALE - Prescaler timer period + * 0b00000000..256*16 cycle + * 0b00000001-0b11111111..PRESCALE*16 cycle + */ #define SEMC_SDRAMCR3_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR3_PRESCALE_SHIFT)) & SEMC_SDRAMCR3_PRESCALE_MASK) #define SEMC_SDRAMCR3_RT_MASK (0xFF0000U) #define SEMC_SDRAMCR3_RT_SHIFT (16U) +/*! RT - Refresh timer period + * 0b00000000..256*Prescaler period + * 0b00000001-0b11111111..RT*Prescaler period + */ #define SEMC_SDRAMCR3_RT(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR3_RT_SHIFT)) & SEMC_SDRAMCR3_RT_MASK) #define SEMC_SDRAMCR3_UT_MASK (0xFF000000U) #define SEMC_SDRAMCR3_UT_SHIFT (24U) +/*! UT - Refresh urgent threshold + * 0b00000000..256*Prescaler period + * 0b00000001-0b11111111..UT*Prescaler period + */ #define SEMC_SDRAMCR3_UT(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR3_UT_SHIFT)) & SEMC_SDRAMCR3_UT_MASK) +/*! @} */ /*! @name NANDCR0 - NAND control register 0 */ +/*! @{ */ #define SEMC_NANDCR0_PS_MASK (0x1U) #define SEMC_NANDCR0_PS_SHIFT (0U) +/*! PS - Port Size + * 0b0..8bit + * 0b1..16bit + */ #define SEMC_NANDCR0_PS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR0_PS_SHIFT)) & SEMC_NANDCR0_PS_MASK) #define SEMC_NANDCR0_BL_MASK (0x70U) #define SEMC_NANDCR0_BL_SHIFT (4U) +/*! BL - Burst Length + * 0b000..1 + * 0b001..2 + * 0b010..4 + * 0b011..8 + * 0b100..16 + * 0b101..32 + * 0b110..64 + * 0b111..64 + */ #define SEMC_NANDCR0_BL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR0_BL_SHIFT)) & SEMC_NANDCR0_BL_MASK) #define SEMC_NANDCR0_EDO_MASK (0x80U) #define SEMC_NANDCR0_EDO_SHIFT (7U) +/*! EDO - EDO mode enabled + * 0b0..EDO mode disabled + * 0b1..EDO mode enabled + */ #define SEMC_NANDCR0_EDO(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR0_EDO_SHIFT)) & SEMC_NANDCR0_EDO_MASK) #define SEMC_NANDCR0_COL_MASK (0x700U) #define SEMC_NANDCR0_COL_SHIFT (8U) +/*! COL - Column address bit number + * 0b000..16 + * 0b001..15 + * 0b010..14 + * 0b011..13 + * 0b100..12 + * 0b101..11 + * 0b110..10 + * 0b111..9 + */ #define SEMC_NANDCR0_COL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR0_COL_SHIFT)) & SEMC_NANDCR0_COL_MASK) +/*! @} */ /*! @name NANDCR1 - NAND control register 1 */ +/*! @{ */ #define SEMC_NANDCR1_CES_MASK (0xFU) #define SEMC_NANDCR1_CES_SHIFT (0U) #define SEMC_NANDCR1_CES(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_CES_SHIFT)) & SEMC_NANDCR1_CES_MASK) @@ -17116,8 +27930,10 @@ typedef struct { #define SEMC_NANDCR1_CEITV_MASK (0xF0000000U) #define SEMC_NANDCR1_CEITV_SHIFT (28U) #define SEMC_NANDCR1_CEITV(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_CEITV_SHIFT)) & SEMC_NANDCR1_CEITV_MASK) +/*! @} */ /*! @name NANDCR2 - NAND control register 2 */ +/*! @{ */ #define SEMC_NANDCR2_TWHR_MASK (0x3FU) #define SEMC_NANDCR2_TWHR_SHIFT (0U) #define SEMC_NANDCR2_TWHR(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR2_TWHR_SHIFT)) & SEMC_NANDCR2_TWHR_MASK) @@ -17133,8 +27949,10 @@ typedef struct { #define SEMC_NANDCR2_TWB_MASK (0x3F000000U) #define SEMC_NANDCR2_TWB_SHIFT (24U) #define SEMC_NANDCR2_TWB(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR2_TWB_SHIFT)) & SEMC_NANDCR2_TWB_MASK) +/*! @} */ /*! @name NANDCR3 - NAND control register 3 */ +/*! @{ */ #define SEMC_NANDCR3_NDOPT1_MASK (0x1U) #define SEMC_NANDCR3_NDOPT1_SHIFT (0U) #define SEMC_NANDCR3_NDOPT1(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR3_NDOPT1_SHIFT)) & SEMC_NANDCR3_NDOPT1_MASK) @@ -17144,25 +27962,71 @@ typedef struct { #define SEMC_NANDCR3_NDOPT3_MASK (0x4U) #define SEMC_NANDCR3_NDOPT3_SHIFT (2U) #define SEMC_NANDCR3_NDOPT3(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR3_NDOPT3_SHIFT)) & SEMC_NANDCR3_NDOPT3_MASK) +/*! @} */ /*! @name NORCR0 - NOR control register 0 */ +/*! @{ */ #define SEMC_NORCR0_PS_MASK (0x1U) #define SEMC_NORCR0_PS_SHIFT (0U) +/*! PS - Port Size + * 0b0..8bit + * 0b1..16bit + */ #define SEMC_NORCR0_PS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_PS_SHIFT)) & SEMC_NORCR0_PS_MASK) #define SEMC_NORCR0_BL_MASK (0x70U) #define SEMC_NORCR0_BL_SHIFT (4U) +/*! BL - Burst Length + * 0b000..1 + * 0b001..2 + * 0b010..4 + * 0b011..8 + * 0b100..16 + * 0b101..32 + * 0b110..64 + * 0b111..64 + */ #define SEMC_NORCR0_BL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_BL_SHIFT)) & SEMC_NORCR0_BL_MASK) #define SEMC_NORCR0_AM_MASK (0x300U) #define SEMC_NORCR0_AM_SHIFT (8U) +/*! AM - Address Mode + * 0b00..Address/Data MUX mode + * 0b01..Advanced Address/Data MUX mode + * 0b10..Address/Data non-MUX mode + * 0b11..Address/Data non-MUX mode + */ #define SEMC_NORCR0_AM(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_AM_SHIFT)) & SEMC_NORCR0_AM_MASK) #define SEMC_NORCR0_ADVP_MASK (0x400U) #define SEMC_NORCR0_ADVP_SHIFT (10U) +/*! ADVP - ADV# polarity + * 0b0..ADV# is Low Active. In ASYNC mode, device sample address with ADV# rise edge; In SYNC mode, device sample address when ADV# is LOW. + * 0b1..ADV# is High Active. In ASYNC mode, device sample address with ADV# fall edge; In SYNC mode, device sample address when ADV# is HIGH. + */ #define SEMC_NORCR0_ADVP(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_ADVP_SHIFT)) & SEMC_NORCR0_ADVP_MASK) #define SEMC_NORCR0_COL_MASK (0xF000U) #define SEMC_NORCR0_COL_SHIFT (12U) +/*! COL - Column Address bit width + * 0b0000..12 Bits + * 0b0001..11 Bits + * 0b0010..10 Bits + * 0b0011..9 Bits + * 0b0100..8 Bits + * 0b0101..7 Bits + * 0b0110..6 Bits + * 0b0111..5 Bits + * 0b1000..4 Bits + * 0b1001..3 Bits + * 0b1010..2 Bits + * 0b1011..12 Bits + * 0b1100..12 Bits + * 0b1101..12 Bits + * 0b1110..12 Bits + * 0b1111..12 Bits + */ #define SEMC_NORCR0_COL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_COL_SHIFT)) & SEMC_NORCR0_COL_MASK) +/*! @} */ /*! @name NORCR1 - NOR control register 1 */ +/*! @{ */ #define SEMC_NORCR1_CES_MASK (0xFU) #define SEMC_NORCR1_CES_SHIFT (0U) #define SEMC_NORCR1_CES(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_CES_SHIFT)) & SEMC_NORCR1_CES_MASK) @@ -17187,8 +28051,10 @@ typedef struct { #define SEMC_NORCR1_REH_MASK (0xF0000000U) #define SEMC_NORCR1_REH_SHIFT (28U) #define SEMC_NORCR1_REH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_REH_SHIFT)) & SEMC_NORCR1_REH_MASK) +/*! @} */ /*! @name NORCR2 - NOR control register 2 */ +/*! @{ */ #define SEMC_NORCR2_WDS_MASK (0xFU) #define SEMC_NORCR2_WDS_SHIFT (0U) #define SEMC_NORCR2_WDS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_WDS_SHIFT)) & SEMC_NORCR2_WDS_MASK) @@ -17210,25 +28076,71 @@ typedef struct { #define SEMC_NORCR2_CEITV_MASK (0xF000000U) #define SEMC_NORCR2_CEITV_SHIFT (24U) #define SEMC_NORCR2_CEITV(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_CEITV_SHIFT)) & SEMC_NORCR2_CEITV_MASK) +/*! @} */ /*! @name SRAMCR0 - SRAM control register 0 */ +/*! @{ */ #define SEMC_SRAMCR0_PS_MASK (0x1U) #define SEMC_SRAMCR0_PS_SHIFT (0U) +/*! PS - Port Size + * 0b0..8bit + * 0b1..16bit + */ #define SEMC_SRAMCR0_PS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_PS_SHIFT)) & SEMC_SRAMCR0_PS_MASK) #define SEMC_SRAMCR0_BL_MASK (0x70U) #define SEMC_SRAMCR0_BL_SHIFT (4U) +/*! BL - Burst Length + * 0b000..1 + * 0b001..2 + * 0b010..4 + * 0b011..8 + * 0b100..16 + * 0b101..32 + * 0b110..64 + * 0b111..64 + */ #define SEMC_SRAMCR0_BL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_BL_SHIFT)) & SEMC_SRAMCR0_BL_MASK) #define SEMC_SRAMCR0_AM_MASK (0x300U) #define SEMC_SRAMCR0_AM_SHIFT (8U) +/*! AM - Address Mode + * 0b00..Address/Data MUX mode + * 0b01..Advanced Address/Data MUX mode + * 0b10..Address/Data non-MUX mode + * 0b11..Address/Data non-MUX mode + */ #define SEMC_SRAMCR0_AM(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_AM_SHIFT)) & SEMC_SRAMCR0_AM_MASK) #define SEMC_SRAMCR0_ADVP_MASK (0x400U) #define SEMC_SRAMCR0_ADVP_SHIFT (10U) +/*! ADVP - ADV# polarity + * 0b0..ADV# is Low Active. In ASYNC mode, device sample address with ADV# rise edge; In SYNC mode, device sample address when ADV# is LOW. + * 0b1..ADV# is High Active. In ASYNC mode, device sample address with ADV# fall edge; In SYNC mode, device sample address when ADV# is HIGH. + */ #define SEMC_SRAMCR0_ADVP(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_ADVP_SHIFT)) & SEMC_SRAMCR0_ADVP_MASK) #define SEMC_SRAMCR0_COL_MASK (0xF000U) #define SEMC_SRAMCR0_COL_SHIFT (12U) +/*! COL - Column Address bit width + * 0b0000..12 Bits + * 0b0001..11 Bits + * 0b0010..10 Bits + * 0b0011..9 Bits + * 0b0100..8 Bits + * 0b0101..7 Bits + * 0b0110..6 Bits + * 0b0111..5 Bits + * 0b1000..4 Bits + * 0b1001..3 Bits + * 0b1010..2 Bits + * 0b1011..12 Bits + * 0b1100..12 Bits + * 0b1101..12 Bits + * 0b1110..12 Bits + * 0b1111..12 Bits + */ #define SEMC_SRAMCR0_COL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_COL_SHIFT)) & SEMC_SRAMCR0_COL_MASK) +/*! @} */ /*! @name SRAMCR1 - SRAM control register 1 */ +/*! @{ */ #define SEMC_SRAMCR1_CES_MASK (0xFU) #define SEMC_SRAMCR1_CES_SHIFT (0U) #define SEMC_SRAMCR1_CES(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_CES_SHIFT)) & SEMC_SRAMCR1_CES_MASK) @@ -17253,8 +28165,10 @@ typedef struct { #define SEMC_SRAMCR1_REH_MASK (0xF0000000U) #define SEMC_SRAMCR1_REH_SHIFT (28U) #define SEMC_SRAMCR1_REH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_REH_SHIFT)) & SEMC_SRAMCR1_REH_MASK) +/*! @} */ /*! @name SRAMCR2 - SRAM control register 2 */ +/*! @{ */ #define SEMC_SRAMCR2_WDS_MASK (0xFU) #define SEMC_SRAMCR2_WDS_SHIFT (0U) #define SEMC_SRAMCR2_WDS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_WDS_SHIFT)) & SEMC_SRAMCR2_WDS_MASK) @@ -17276,19 +28190,55 @@ typedef struct { #define SEMC_SRAMCR2_CEITV_MASK (0xF000000U) #define SEMC_SRAMCR2_CEITV_SHIFT (24U) #define SEMC_SRAMCR2_CEITV(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_CEITV_SHIFT)) & SEMC_SRAMCR2_CEITV_MASK) +/*! @} */ /*! @name DBICR0 - DBI-B control register 0 */ +/*! @{ */ #define SEMC_DBICR0_PS_MASK (0x1U) #define SEMC_DBICR0_PS_SHIFT (0U) +/*! PS - Port Size + * 0b0..8bit + * 0b1..16bit + */ #define SEMC_DBICR0_PS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR0_PS_SHIFT)) & SEMC_DBICR0_PS_MASK) #define SEMC_DBICR0_BL_MASK (0x70U) #define SEMC_DBICR0_BL_SHIFT (4U) +/*! BL - Burst Length + * 0b000..1 + * 0b001..2 + * 0b010..4 + * 0b011..8 + * 0b100..16 + * 0b101..32 + * 0b110..64 + * 0b111..64 + */ #define SEMC_DBICR0_BL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR0_BL_SHIFT)) & SEMC_DBICR0_BL_MASK) #define SEMC_DBICR0_COL_MASK (0xF000U) #define SEMC_DBICR0_COL_SHIFT (12U) +/*! COL - Column Address bit width + * 0b0000..12 Bits + * 0b0001..11 Bits + * 0b0010..10 Bits + * 0b0011..9 Bits + * 0b0100..8 Bits + * 0b0101..7 Bits + * 0b0110..6 Bits + * 0b0111..5 Bits + * 0b1000..4 Bits + * 0b1001..3 Bits + * 0b1010..2 Bits + * 0b1011..12 Bits + * 0b1100..12 Bits + * 0b1101..12 Bits + * 0b1110..12 Bits + * 0b1111..12 Bits + */ #define SEMC_DBICR0_COL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR0_COL_SHIFT)) & SEMC_DBICR0_COL_MASK) +/*! @} */ /*! @name DBICR1 - DBI-B control register 1 */ +/*! @{ */ #define SEMC_DBICR1_CES_MASK (0xFU) #define SEMC_DBICR1_CES_SHIFT (0U) #define SEMC_DBICR1_CES(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_CES_SHIFT)) & SEMC_DBICR1_CES_MASK) @@ -17310,66 +28260,125 @@ typedef struct { #define SEMC_DBICR1_CEITV_MASK (0xF000000U) #define SEMC_DBICR1_CEITV_SHIFT (24U) #define SEMC_DBICR1_CEITV(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_CEITV_SHIFT)) & SEMC_DBICR1_CEITV_MASK) +#define SEMC_DBICR1_REL2_MASK (0x30000000U) +#define SEMC_DBICR1_REL2_SHIFT (28U) +#define SEMC_DBICR1_REL2(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_REL2_SHIFT)) & SEMC_DBICR1_REL2_MASK) +#define SEMC_DBICR1_REH2_MASK (0xC0000000U) +#define SEMC_DBICR1_REH2_SHIFT (30U) +#define SEMC_DBICR1_REH2(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_REH2_SHIFT)) & SEMC_DBICR1_REH2_MASK) +/*! @} */ /*! @name IPCR0 - IP Command control register 0 */ +/*! @{ */ #define SEMC_IPCR0_SA_MASK (0xFFFFFFFFU) #define SEMC_IPCR0_SA_SHIFT (0U) #define SEMC_IPCR0_SA(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR0_SA_SHIFT)) & SEMC_IPCR0_SA_MASK) +/*! @} */ /*! @name IPCR1 - IP Command control register 1 */ +/*! @{ */ #define SEMC_IPCR1_DATSZ_MASK (0x7U) #define SEMC_IPCR1_DATSZ_SHIFT (0U) +/*! DATSZ - Data Size in Byte + * 0b000..4 + * 0b001..1 + * 0b010..2 + * 0b011..3 + * 0b100..4 + * 0b101..4 + * 0b110..4 + * 0b111..4 + */ #define SEMC_IPCR1_DATSZ(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR1_DATSZ_SHIFT)) & SEMC_IPCR1_DATSZ_MASK) +/*! @} */ /*! @name IPCR2 - IP Command control register 2 */ +/*! @{ */ #define SEMC_IPCR2_BM0_MASK (0x1U) #define SEMC_IPCR2_BM0_SHIFT (0U) +/*! BM0 - Byte Mask for Byte 0 (IPTXD bit 7:0) + * 0b0..Byte Unmasked + * 0b1..Byte Masked + */ #define SEMC_IPCR2_BM0(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR2_BM0_SHIFT)) & SEMC_IPCR2_BM0_MASK) #define SEMC_IPCR2_BM1_MASK (0x2U) #define SEMC_IPCR2_BM1_SHIFT (1U) +/*! BM1 - Byte Mask for Byte 1 (IPTXD bit 15:8) + * 0b0..Byte Unmasked + * 0b1..Byte Masked + */ #define SEMC_IPCR2_BM1(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR2_BM1_SHIFT)) & SEMC_IPCR2_BM1_MASK) #define SEMC_IPCR2_BM2_MASK (0x4U) #define SEMC_IPCR2_BM2_SHIFT (2U) +/*! BM2 - Byte Mask for Byte 2 (IPTXD bit 23:16) + * 0b0..Byte Unmasked + * 0b1..Byte Masked + */ #define SEMC_IPCR2_BM2(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR2_BM2_SHIFT)) & SEMC_IPCR2_BM2_MASK) #define SEMC_IPCR2_BM3_MASK (0x8U) #define SEMC_IPCR2_BM3_SHIFT (3U) +/*! BM3 - Byte Mask for Byte 3 (IPTXD bit 31:24) + * 0b0..Byte Unmasked + * 0b1..Byte Masked + */ #define SEMC_IPCR2_BM3(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR2_BM3_SHIFT)) & SEMC_IPCR2_BM3_MASK) +/*! @} */ /*! @name IPCMD - IP Command register */ +/*! @{ */ #define SEMC_IPCMD_CMD_MASK (0xFFFFU) #define SEMC_IPCMD_CMD_SHIFT (0U) #define SEMC_IPCMD_CMD(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCMD_CMD_SHIFT)) & SEMC_IPCMD_CMD_MASK) #define SEMC_IPCMD_KEY_MASK (0xFFFF0000U) #define SEMC_IPCMD_KEY_SHIFT (16U) #define SEMC_IPCMD_KEY(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCMD_KEY_SHIFT)) & SEMC_IPCMD_KEY_MASK) +/*! @} */ /*! @name IPTXDAT - TX DATA register (for IP Command) */ +/*! @{ */ #define SEMC_IPTXDAT_DAT_MASK (0xFFFFFFFFU) #define SEMC_IPTXDAT_DAT_SHIFT (0U) #define SEMC_IPTXDAT_DAT(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPTXDAT_DAT_SHIFT)) & SEMC_IPTXDAT_DAT_MASK) +/*! @} */ /*! @name IPRXDAT - RX DATA register (for IP Command) */ +/*! @{ */ #define SEMC_IPRXDAT_DAT_MASK (0xFFFFFFFFU) #define SEMC_IPRXDAT_DAT_SHIFT (0U) #define SEMC_IPRXDAT_DAT(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPRXDAT_DAT_SHIFT)) & SEMC_IPRXDAT_DAT_MASK) +/*! @} */ /*! @name STS0 - Status register 0 */ +/*! @{ */ #define SEMC_STS0_IDLE_MASK (0x1U) #define SEMC_STS0_IDLE_SHIFT (0U) #define SEMC_STS0_IDLE(x) (((uint32_t)(((uint32_t)(x)) << SEMC_STS0_IDLE_SHIFT)) & SEMC_STS0_IDLE_MASK) #define SEMC_STS0_NARDY_MASK (0x2U) #define SEMC_STS0_NARDY_SHIFT (1U) +/*! NARDY - Indicating NAND device Ready/WAIT# pin level. + * 0b0..NAND device is not ready + * 0b1..NAND device is ready + */ #define SEMC_STS0_NARDY(x) (((uint32_t)(((uint32_t)(x)) << SEMC_STS0_NARDY_SHIFT)) & SEMC_STS0_NARDY_MASK) +/*! @} */ /*! @name STS2 - Status register 2 */ +/*! @{ */ #define SEMC_STS2_NDWRPEND_MASK (0x8U) #define SEMC_STS2_NDWRPEND_SHIFT (3U) +/*! NDWRPEND - This field indicating whether there is pending AXI command (write) to NAND device. + * 0b0..No pending + * 0b1..Pending + */ #define SEMC_STS2_NDWRPEND(x) (((uint32_t)(((uint32_t)(x)) << SEMC_STS2_NDWRPEND_SHIFT)) & SEMC_STS2_NDWRPEND_MASK) +/*! @} */ /*! @name STS12 - Status register 12 */ +/*! @{ */ #define SEMC_STS12_NDADDR_MASK (0xFFFFFFFFU) #define SEMC_STS12_NDADDR_SHIFT (0U) #define SEMC_STS12_NDADDR(x) (((uint32_t)(((uint32_t)(x)) << SEMC_STS12_NDADDR_SHIFT)) & SEMC_STS12_NDADDR_MASK) +/*! @} */ /*! @@ -17436,8 +28445,8 @@ typedef struct { uint8_t RESERVED_1[4]; __IO uint32_t LPGPR_ALIAS[4]; /**< SNVS_LP General Purpose Registers 0 .. 3, array offset: 0x90, array step: 0x4 */ uint8_t RESERVED_2[96]; - __IO uint32_t LPGPR[4]; /**< SNVS_LP General Purpose Registers 0 .. 3, array offset: 0x100, array step: 0x4 */ - uint8_t RESERVED_3[2792]; + __IO uint32_t LPGPR[8]; /**< SNVS_LP General Purpose Registers 0 .. 7, array offset: 0x100, array step: 0x4 */ + uint8_t RESERVED_3[2776]; __I uint32_t HPVIDR1; /**< SNVS_HP Version ID Register 1, offset: 0xBF8 */ __I uint32_t HPVIDR2; /**< SNVS_HP Version ID Register 2, offset: 0xBFC */ } SNVS_Type; @@ -17452,58 +28461,125 @@ typedef struct { */ /*! @name HPLR - SNVS_HP Lock Register */ +/*! @{ */ #define SNVS_HPLR_ZMK_WSL_MASK (0x1U) #define SNVS_HPLR_ZMK_WSL_SHIFT (0U) +/*! ZMK_WSL + * 0b0..Write access is allowed + * 0b1..Write access is not allowed + */ #define SNVS_HPLR_ZMK_WSL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_ZMK_WSL_SHIFT)) & SNVS_HPLR_ZMK_WSL_MASK) #define SNVS_HPLR_ZMK_RSL_MASK (0x2U) #define SNVS_HPLR_ZMK_RSL_SHIFT (1U) +/*! ZMK_RSL + * 0b0..Read access is allowed (only in software Programming mode) + * 0b1..Read access is not allowed + */ #define SNVS_HPLR_ZMK_RSL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_ZMK_RSL_SHIFT)) & SNVS_HPLR_ZMK_RSL_MASK) #define SNVS_HPLR_SRTC_SL_MASK (0x4U) #define SNVS_HPLR_SRTC_SL_SHIFT (2U) +/*! SRTC_SL + * 0b0..Write access is allowed + * 0b1..Write access is not allowed + */ #define SNVS_HPLR_SRTC_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_SRTC_SL_SHIFT)) & SNVS_HPLR_SRTC_SL_MASK) #define SNVS_HPLR_LPCALB_SL_MASK (0x8U) #define SNVS_HPLR_LPCALB_SL_SHIFT (3U) +/*! LPCALB_SL + * 0b0..Write access is allowed + * 0b1..Write access is not allowed + */ #define SNVS_HPLR_LPCALB_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_LPCALB_SL_SHIFT)) & SNVS_HPLR_LPCALB_SL_MASK) #define SNVS_HPLR_MC_SL_MASK (0x10U) #define SNVS_HPLR_MC_SL_SHIFT (4U) +/*! MC_SL + * 0b0..Write access (increment) is allowed + * 0b1..Write access (increment) is not allowed + */ #define SNVS_HPLR_MC_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_MC_SL_SHIFT)) & SNVS_HPLR_MC_SL_MASK) #define SNVS_HPLR_GPR_SL_MASK (0x20U) #define SNVS_HPLR_GPR_SL_SHIFT (5U) +/*! GPR_SL + * 0b0..Write access is allowed + * 0b1..Write access is not allowed + */ #define SNVS_HPLR_GPR_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_GPR_SL_SHIFT)) & SNVS_HPLR_GPR_SL_MASK) #define SNVS_HPLR_LPSVCR_SL_MASK (0x40U) #define SNVS_HPLR_LPSVCR_SL_SHIFT (6U) +/*! LPSVCR_SL + * 0b0..Write access is allowed + * 0b1..Write access is not allowed + */ #define SNVS_HPLR_LPSVCR_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_LPSVCR_SL_SHIFT)) & SNVS_HPLR_LPSVCR_SL_MASK) #define SNVS_HPLR_LPTDCR_SL_MASK (0x100U) #define SNVS_HPLR_LPTDCR_SL_SHIFT (8U) +/*! LPTDCR_SL + * 0b0..Write access is allowed + * 0b1..Write access is not allowed + */ #define SNVS_HPLR_LPTDCR_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_LPTDCR_SL_SHIFT)) & SNVS_HPLR_LPTDCR_SL_MASK) #define SNVS_HPLR_MKS_SL_MASK (0x200U) #define SNVS_HPLR_MKS_SL_SHIFT (9U) +/*! MKS_SL + * 0b0..Write access is allowed + * 0b1..Write access is not allowed + */ #define SNVS_HPLR_MKS_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_MKS_SL_SHIFT)) & SNVS_HPLR_MKS_SL_MASK) #define SNVS_HPLR_HPSVCR_L_MASK (0x10000U) #define SNVS_HPLR_HPSVCR_L_SHIFT (16U) +/*! HPSVCR_L + * 0b0..Write access is allowed + * 0b1..Write access is not allowed + */ #define SNVS_HPLR_HPSVCR_L(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_HPSVCR_L_SHIFT)) & SNVS_HPLR_HPSVCR_L_MASK) #define SNVS_HPLR_HPSICR_L_MASK (0x20000U) #define SNVS_HPLR_HPSICR_L_SHIFT (17U) +/*! HPSICR_L + * 0b0..Write access is allowed + * 0b1..Write access is not allowed + */ #define SNVS_HPLR_HPSICR_L(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_HPSICR_L_SHIFT)) & SNVS_HPLR_HPSICR_L_MASK) #define SNVS_HPLR_HAC_L_MASK (0x40000U) #define SNVS_HPLR_HAC_L_SHIFT (18U) +/*! HAC_L + * 0b0..Write access is allowed + * 0b1..Write access is not allowed + */ #define SNVS_HPLR_HAC_L(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_HAC_L_SHIFT)) & SNVS_HPLR_HAC_L_MASK) +/*! @} */ /*! @name HPCOMR - SNVS_HP Command Register */ +/*! @{ */ #define SNVS_HPCOMR_SSM_ST_MASK (0x1U) #define SNVS_HPCOMR_SSM_ST_SHIFT (0U) #define SNVS_HPCOMR_SSM_ST(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SSM_ST_SHIFT)) & SNVS_HPCOMR_SSM_ST_MASK) #define SNVS_HPCOMR_SSM_ST_DIS_MASK (0x2U) #define SNVS_HPCOMR_SSM_ST_DIS_SHIFT (1U) +/*! SSM_ST_DIS + * 0b0..Secure to Trusted State transition is enabled + * 0b1..Secure to Trusted State transition is disabled + */ #define SNVS_HPCOMR_SSM_ST_DIS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SSM_ST_DIS_SHIFT)) & SNVS_HPCOMR_SSM_ST_DIS_MASK) #define SNVS_HPCOMR_SSM_SFNS_DIS_MASK (0x4U) #define SNVS_HPCOMR_SSM_SFNS_DIS_SHIFT (2U) +/*! SSM_SFNS_DIS + * 0b0..Soft Fail to Non-Secure State transition is enabled + * 0b1..Soft Fail to Non-Secure State transition is disabled + */ #define SNVS_HPCOMR_SSM_SFNS_DIS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SSM_SFNS_DIS_SHIFT)) & SNVS_HPCOMR_SSM_SFNS_DIS_MASK) #define SNVS_HPCOMR_LP_SWR_MASK (0x10U) #define SNVS_HPCOMR_LP_SWR_SHIFT (4U) +/*! LP_SWR + * 0b0..No Action + * 0b1..Reset LP section + */ #define SNVS_HPCOMR_LP_SWR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_LP_SWR_SHIFT)) & SNVS_HPCOMR_LP_SWR_MASK) #define SNVS_HPCOMR_LP_SWR_DIS_MASK (0x20U) #define SNVS_HPCOMR_LP_SWR_DIS_SHIFT (5U) +/*! LP_SWR_DIS + * 0b0..LP software reset is enabled + * 0b1..LP software reset is disabled + */ #define SNVS_HPCOMR_LP_SWR_DIS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_LP_SWR_DIS_SHIFT)) & SNVS_HPCOMR_LP_SWR_DIS_MASK) #define SNVS_HPCOMR_SW_SV_MASK (0x100U) #define SNVS_HPCOMR_SW_SV_SHIFT (8U) @@ -17516,18 +28592,38 @@ typedef struct { #define SNVS_HPCOMR_SW_LPSV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SW_LPSV_SHIFT)) & SNVS_HPCOMR_SW_LPSV_MASK) #define SNVS_HPCOMR_PROG_ZMK_MASK (0x1000U) #define SNVS_HPCOMR_PROG_ZMK_SHIFT (12U) +/*! PROG_ZMK + * 0b0..No Action + * 0b1..Activate hardware key programming mechanism + */ #define SNVS_HPCOMR_PROG_ZMK(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_PROG_ZMK_SHIFT)) & SNVS_HPCOMR_PROG_ZMK_MASK) #define SNVS_HPCOMR_MKS_EN_MASK (0x2000U) #define SNVS_HPCOMR_MKS_EN_SHIFT (13U) +/*! MKS_EN + * 0b0..OTP master key is selected as an SNVS master key + * 0b1..SNVS master key is selected according to the setting of the MASTER_KEY_SEL field of LPMKCR + */ #define SNVS_HPCOMR_MKS_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_MKS_EN_SHIFT)) & SNVS_HPCOMR_MKS_EN_MASK) #define SNVS_HPCOMR_HAC_EN_MASK (0x10000U) #define SNVS_HPCOMR_HAC_EN_SHIFT (16U) +/*! HAC_EN + * 0b0..High Assurance Counter is disabled + * 0b1..High Assurance Counter is enabled + */ #define SNVS_HPCOMR_HAC_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_HAC_EN_SHIFT)) & SNVS_HPCOMR_HAC_EN_MASK) #define SNVS_HPCOMR_HAC_LOAD_MASK (0x20000U) #define SNVS_HPCOMR_HAC_LOAD_SHIFT (17U) +/*! HAC_LOAD + * 0b0..No Action + * 0b1..Load the HAC + */ #define SNVS_HPCOMR_HAC_LOAD(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_HAC_LOAD_SHIFT)) & SNVS_HPCOMR_HAC_LOAD_MASK) #define SNVS_HPCOMR_HAC_CLEAR_MASK (0x40000U) #define SNVS_HPCOMR_HAC_CLEAR_SHIFT (18U) +/*! HAC_CLEAR + * 0b0..No Action + * 0b1..Clear the HAC + */ #define SNVS_HPCOMR_HAC_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_HAC_CLEAR_SHIFT)) & SNVS_HPCOMR_HAC_CLEAR_MASK) #define SNVS_HPCOMR_HAC_STOP_MASK (0x80000U) #define SNVS_HPCOMR_HAC_STOP_SHIFT (19U) @@ -17535,28 +28631,85 @@ typedef struct { #define SNVS_HPCOMR_NPSWA_EN_MASK (0x80000000U) #define SNVS_HPCOMR_NPSWA_EN_SHIFT (31U) #define SNVS_HPCOMR_NPSWA_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_NPSWA_EN_SHIFT)) & SNVS_HPCOMR_NPSWA_EN_MASK) +/*! @} */ /*! @name HPCR - SNVS_HP Control Register */ +/*! @{ */ #define SNVS_HPCR_RTC_EN_MASK (0x1U) #define SNVS_HPCR_RTC_EN_SHIFT (0U) +/*! RTC_EN + * 0b0..RTC is disabled + * 0b1..RTC is enabled + */ #define SNVS_HPCR_RTC_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_RTC_EN_SHIFT)) & SNVS_HPCR_RTC_EN_MASK) #define SNVS_HPCR_HPTA_EN_MASK (0x2U) #define SNVS_HPCR_HPTA_EN_SHIFT (1U) +/*! HPTA_EN + * 0b0..HP Time Alarm Interrupt is disabled + * 0b1..HP Time Alarm Interrupt is enabled + */ #define SNVS_HPCR_HPTA_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_HPTA_EN_SHIFT)) & SNVS_HPCR_HPTA_EN_MASK) +#define SNVS_HPCR_DIS_PI_MASK (0x4U) +#define SNVS_HPCR_DIS_PI_SHIFT (2U) +/*! DIS_PI + * 0b0..Periodic interrupt will trigger a functional interrupt + * 0b1..Disable periodic interrupt in the function interrupt + */ +#define SNVS_HPCR_DIS_PI(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_DIS_PI_SHIFT)) & SNVS_HPCR_DIS_PI_MASK) #define SNVS_HPCR_PI_EN_MASK (0x8U) #define SNVS_HPCR_PI_EN_SHIFT (3U) +/*! PI_EN + * 0b0..HP Periodic Interrupt is disabled + * 0b1..HP Periodic Interrupt is enabled + */ #define SNVS_HPCR_PI_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_PI_EN_SHIFT)) & SNVS_HPCR_PI_EN_MASK) #define SNVS_HPCR_PI_FREQ_MASK (0xF0U) #define SNVS_HPCR_PI_FREQ_SHIFT (4U) +/*! PI_FREQ + * 0b0000..- bit 0 of the HPRTCLR is selected as a source of the periodic interrupt + * 0b0001..- bit 1 of the HPRTCLR is selected as a source of the periodic interrupt + * 0b0010..- bit 2 of the HPRTCLR is selected as a source of the periodic interrupt + * 0b0011..- bit 3 of the HPRTCLR is selected as a source of the periodic interrupt + * 0b0100..- bit 4 of the HPRTCLR is selected as a source of the periodic interrupt + * 0b0101..- bit 5 of the HPRTCLR is selected as a source of the periodic interrupt + * 0b0110..- bit 6 of the HPRTCLR is selected as a source of the periodic interrupt + * 0b0111..- bit 7 of the HPRTCLR is selected as a source of the periodic interrupt + * 0b1000..- bit 8 of the HPRTCLR is selected as a source of the periodic interrupt + * 0b1001..- bit 9 of the HPRTCLR is selected as a source of the periodic interrupt + * 0b1010..- bit 10 of the HPRTCLR is selected as a source of the periodic interrupt + * 0b1011..- bit 11 of the HPRTCLR is selected as a source of the periodic interrupt + * 0b1100..- bit 12 of the HPRTCLR is selected as a source of the periodic interrupt + * 0b1101..- bit 13 of the HPRTCLR is selected as a source of the periodic interrupt + * 0b1110..- bit 14 of the HPRTCLR is selected as a source of the periodic interrupt + * 0b1111..- bit 15 of the HPRTCLR is selected as a source of the periodic interrupt + */ #define SNVS_HPCR_PI_FREQ(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_PI_FREQ_SHIFT)) & SNVS_HPCR_PI_FREQ_MASK) #define SNVS_HPCR_HPCALB_EN_MASK (0x100U) #define SNVS_HPCR_HPCALB_EN_SHIFT (8U) +/*! HPCALB_EN + * 0b0..HP Timer calibration disabled + * 0b1..HP Timer calibration enabled + */ #define SNVS_HPCR_HPCALB_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_HPCALB_EN_SHIFT)) & SNVS_HPCR_HPCALB_EN_MASK) #define SNVS_HPCR_HPCALB_VAL_MASK (0x7C00U) #define SNVS_HPCR_HPCALB_VAL_SHIFT (10U) +/*! HPCALB_VAL + * 0b00000..+0 counts per each 32768 ticks of the counter + * 0b00001..+1 counts per each 32768 ticks of the counter + * 0b00010..+2 counts per each 32768 ticks of the counter + * 0b01111..+15 counts per each 32768 ticks of the counter + * 0b10000..-16 counts per each 32768 ticks of the counter + * 0b10001..-15 counts per each 32768 ticks of the counter + * 0b11110..-2 counts per each 32768 ticks of the counter + * 0b11111..-1 counts per each 32768 ticks of the counter + */ #define SNVS_HPCR_HPCALB_VAL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_HPCALB_VAL_SHIFT)) & SNVS_HPCR_HPCALB_VAL_MASK) #define SNVS_HPCR_HP_TS_MASK (0x10000U) #define SNVS_HPCR_HP_TS_SHIFT (16U) +/*! HP_TS + * 0b0..No Action + * 0b1..Synchronize the HP Time Counter to the LP Time Counter + */ #define SNVS_HPCR_HP_TS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_HP_TS_SHIFT)) & SNVS_HPCR_HP_TS_MASK) #define SNVS_HPCR_BTN_CONFIG_MASK (0x7000000U) #define SNVS_HPCR_BTN_CONFIG_SHIFT (24U) @@ -17564,59 +28717,131 @@ typedef struct { #define SNVS_HPCR_BTN_MASK_MASK (0x8000000U) #define SNVS_HPCR_BTN_MASK_SHIFT (27U) #define SNVS_HPCR_BTN_MASK(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_BTN_MASK_SHIFT)) & SNVS_HPCR_BTN_MASK_MASK) +/*! @} */ /*! @name HPSICR - SNVS_HP Security Interrupt Control Register */ +/*! @{ */ #define SNVS_HPSICR_SV0_EN_MASK (0x1U) #define SNVS_HPSICR_SV0_EN_SHIFT (0U) +/*! SV0_EN + * 0b0..Security Violation 0 Interrupt is Disabled + * 0b1..Security Violation 0 Interrupt is Enabled + */ #define SNVS_HPSICR_SV0_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_SV0_EN_SHIFT)) & SNVS_HPSICR_SV0_EN_MASK) #define SNVS_HPSICR_SV1_EN_MASK (0x2U) #define SNVS_HPSICR_SV1_EN_SHIFT (1U) +/*! SV1_EN + * 0b0..Security Violation 1 Interrupt is Disabled + * 0b1..Security Violation 1 Interrupt is Enabled + */ #define SNVS_HPSICR_SV1_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_SV1_EN_SHIFT)) & SNVS_HPSICR_SV1_EN_MASK) #define SNVS_HPSICR_SV2_EN_MASK (0x4U) #define SNVS_HPSICR_SV2_EN_SHIFT (2U) +/*! SV2_EN + * 0b0..Security Violation 2 Interrupt is Disabled + * 0b1..Security Violation 2 Interrupt is Enabled + */ #define SNVS_HPSICR_SV2_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_SV2_EN_SHIFT)) & SNVS_HPSICR_SV2_EN_MASK) #define SNVS_HPSICR_SV3_EN_MASK (0x8U) #define SNVS_HPSICR_SV3_EN_SHIFT (3U) +/*! SV3_EN + * 0b0..Security Violation 3 Interrupt is Disabled + * 0b1..Security Violation 3 Interrupt is Enabled + */ #define SNVS_HPSICR_SV3_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_SV3_EN_SHIFT)) & SNVS_HPSICR_SV3_EN_MASK) #define SNVS_HPSICR_SV4_EN_MASK (0x10U) #define SNVS_HPSICR_SV4_EN_SHIFT (4U) +/*! SV4_EN + * 0b0..Security Violation 4 Interrupt is Disabled + * 0b1..Security Violation 4 Interrupt is Enabled + */ #define SNVS_HPSICR_SV4_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_SV4_EN_SHIFT)) & SNVS_HPSICR_SV4_EN_MASK) #define SNVS_HPSICR_SV5_EN_MASK (0x20U) #define SNVS_HPSICR_SV5_EN_SHIFT (5U) +/*! SV5_EN + * 0b0..Security Violation 5 Interrupt is Disabled + * 0b1..Security Violation 5 Interrupt is Enabled + */ #define SNVS_HPSICR_SV5_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_SV5_EN_SHIFT)) & SNVS_HPSICR_SV5_EN_MASK) #define SNVS_HPSICR_LPSVI_EN_MASK (0x80000000U) #define SNVS_HPSICR_LPSVI_EN_SHIFT (31U) +/*! LPSVI_EN + * 0b0..LP Security Violation Interrupt is Disabled + * 0b1..LP Security Violation Interrupt is Enabled + */ #define SNVS_HPSICR_LPSVI_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_LPSVI_EN_SHIFT)) & SNVS_HPSICR_LPSVI_EN_MASK) +/*! @} */ /*! @name HPSVCR - SNVS_HP Security Violation Control Register */ +/*! @{ */ #define SNVS_HPSVCR_SV0_CFG_MASK (0x1U) #define SNVS_HPSVCR_SV0_CFG_SHIFT (0U) +/*! SV0_CFG + * 0b0..Security Violation 0 is a non-fatal violation + * 0b1..Security Violation 0 is a fatal violation + */ #define SNVS_HPSVCR_SV0_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_SV0_CFG_SHIFT)) & SNVS_HPSVCR_SV0_CFG_MASK) #define SNVS_HPSVCR_SV1_CFG_MASK (0x2U) #define SNVS_HPSVCR_SV1_CFG_SHIFT (1U) +/*! SV1_CFG + * 0b0..Security Violation 1 is a non-fatal violation + * 0b1..Security Violation 1 is a fatal violation + */ #define SNVS_HPSVCR_SV1_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_SV1_CFG_SHIFT)) & SNVS_HPSVCR_SV1_CFG_MASK) #define SNVS_HPSVCR_SV2_CFG_MASK (0x4U) #define SNVS_HPSVCR_SV2_CFG_SHIFT (2U) +/*! SV2_CFG + * 0b0..Security Violation 2 is a non-fatal violation + * 0b1..Security Violation 2 is a fatal violation + */ #define SNVS_HPSVCR_SV2_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_SV2_CFG_SHIFT)) & SNVS_HPSVCR_SV2_CFG_MASK) #define SNVS_HPSVCR_SV3_CFG_MASK (0x8U) #define SNVS_HPSVCR_SV3_CFG_SHIFT (3U) +/*! SV3_CFG + * 0b0..Security Violation 3 is a non-fatal violation + * 0b1..Security Violation 3 is a fatal violation + */ #define SNVS_HPSVCR_SV3_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_SV3_CFG_SHIFT)) & SNVS_HPSVCR_SV3_CFG_MASK) #define SNVS_HPSVCR_SV4_CFG_MASK (0x10U) #define SNVS_HPSVCR_SV4_CFG_SHIFT (4U) +/*! SV4_CFG + * 0b0..Security Violation 4 is a non-fatal violation + * 0b1..Security Violation 4 is a fatal violation + */ #define SNVS_HPSVCR_SV4_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_SV4_CFG_SHIFT)) & SNVS_HPSVCR_SV4_CFG_MASK) #define SNVS_HPSVCR_SV5_CFG_MASK (0x60U) #define SNVS_HPSVCR_SV5_CFG_SHIFT (5U) +/*! SV5_CFG + * 0b00..Security Violation 5 is disabled + * 0b01..Security Violation 5 is a non-fatal violation + * 0b1x..Security Violation 5 is a fatal violation + */ #define SNVS_HPSVCR_SV5_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_SV5_CFG_SHIFT)) & SNVS_HPSVCR_SV5_CFG_MASK) #define SNVS_HPSVCR_LPSV_CFG_MASK (0xC0000000U) #define SNVS_HPSVCR_LPSV_CFG_SHIFT (30U) +/*! LPSV_CFG + * 0b00..LP security violation is disabled + * 0b01..LP security violation is a non-fatal violation + * 0b1x..LP security violation is a fatal violation + */ #define SNVS_HPSVCR_LPSV_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_LPSV_CFG_SHIFT)) & SNVS_HPSVCR_LPSV_CFG_MASK) +/*! @} */ /*! @name HPSR - SNVS_HP Status Register */ +/*! @{ */ #define SNVS_HPSR_HPTA_MASK (0x1U) #define SNVS_HPSR_HPTA_SHIFT (0U) +/*! HPTA + * 0b0..No time alarm interrupt occurred. + * 0b1..A time alarm interrupt occurred. + */ #define SNVS_HPSR_HPTA(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_HPTA_SHIFT)) & SNVS_HPSR_HPTA_MASK) #define SNVS_HPSR_PI_MASK (0x2U) #define SNVS_HPSR_PI_SHIFT (1U) +/*! PI + * 0b0..No periodic interrupt occurred. + * 0b1..A periodic interrupt occurred. + */ #define SNVS_HPSR_PI(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_PI_SHIFT)) & SNVS_HPSR_PI_MASK) #define SNVS_HPSR_LPDIS_MASK (0x10U) #define SNVS_HPSR_LPDIS_SHIFT (4U) @@ -17629,41 +28854,88 @@ typedef struct { #define SNVS_HPSR_BI(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_BI_SHIFT)) & SNVS_HPSR_BI_MASK) #define SNVS_HPSR_SSM_STATE_MASK (0xF00U) #define SNVS_HPSR_SSM_STATE_SHIFT (8U) +/*! SSM_STATE + * 0b0000..Init + * 0b0001..Hard Fail + * 0b0011..Soft Fail + * 0b1000..Init Intermediate (transition state between Init and Check - SSM stays in this state only one clock cycle) + * 0b1001..Check + * 0b1011..Non-Secure + * 0b1101..Trusted + * 0b1111..Secure + */ #define SNVS_HPSR_SSM_STATE(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_SSM_STATE_SHIFT)) & SNVS_HPSR_SSM_STATE_MASK) -#define SNVS_HPSR_SYS_SECURITY_CFG_MASK (0x7000U) -#define SNVS_HPSR_SYS_SECURITY_CFG_SHIFT (12U) -#define SNVS_HPSR_SYS_SECURITY_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_SYS_SECURITY_CFG_SHIFT)) & SNVS_HPSR_SYS_SECURITY_CFG_MASK) -#define SNVS_HPSR_SYS_SECURE_BOOT_MASK (0x8000U) -#define SNVS_HPSR_SYS_SECURE_BOOT_SHIFT (15U) -#define SNVS_HPSR_SYS_SECURE_BOOT(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_SYS_SECURE_BOOT_SHIFT)) & SNVS_HPSR_SYS_SECURE_BOOT_MASK) +#define SNVS_HPSR_SECURITY_CONFIG_MASK (0xF000U) +#define SNVS_HPSR_SECURITY_CONFIG_SHIFT (12U) +/*! SECURITY_CONFIG + * 0b0000, 0b1000..FAB configuration + * 0b0001, 0b0010, 0b0011..OPEN configuration + * 0b1010, 0b1001, 0b1011..CLOSED configuration + * 0bx1xx..FIELD RETURN configuration + */ +#define SNVS_HPSR_SECURITY_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_SECURITY_CONFIG_SHIFT)) & SNVS_HPSR_SECURITY_CONFIG_MASK) #define SNVS_HPSR_OTPMK_SYNDROME_MASK (0x1FF0000U) #define SNVS_HPSR_OTPMK_SYNDROME_SHIFT (16U) #define SNVS_HPSR_OTPMK_SYNDROME(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_OTPMK_SYNDROME_SHIFT)) & SNVS_HPSR_OTPMK_SYNDROME_MASK) #define SNVS_HPSR_OTPMK_ZERO_MASK (0x8000000U) #define SNVS_HPSR_OTPMK_ZERO_SHIFT (27U) +/*! OTPMK_ZERO + * 0b0..The OTPMK is not zero. + * 0b1..The OTPMK is zero. + */ #define SNVS_HPSR_OTPMK_ZERO(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_OTPMK_ZERO_SHIFT)) & SNVS_HPSR_OTPMK_ZERO_MASK) #define SNVS_HPSR_ZMK_ZERO_MASK (0x80000000U) #define SNVS_HPSR_ZMK_ZERO_SHIFT (31U) +/*! ZMK_ZERO + * 0b0..The ZMK is not zero. + * 0b1..The ZMK is zero. + */ #define SNVS_HPSR_ZMK_ZERO(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_ZMK_ZERO_SHIFT)) & SNVS_HPSR_ZMK_ZERO_MASK) +/*! @} */ /*! @name HPSVSR - SNVS_HP Security Violation Status Register */ +/*! @{ */ #define SNVS_HPSVSR_SV0_MASK (0x1U) #define SNVS_HPSVSR_SV0_SHIFT (0U) +/*! SV0 + * 0b0..No Security Violation 0 security violation was detected. + * 0b1..Security Violation 0 security violation was detected. + */ #define SNVS_HPSVSR_SV0(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SV0_SHIFT)) & SNVS_HPSVSR_SV0_MASK) #define SNVS_HPSVSR_SV1_MASK (0x2U) #define SNVS_HPSVSR_SV1_SHIFT (1U) +/*! SV1 + * 0b0..No Security Violation 1 security violation was detected. + * 0b1..Security Violation 1 security violation was detected. + */ #define SNVS_HPSVSR_SV1(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SV1_SHIFT)) & SNVS_HPSVSR_SV1_MASK) #define SNVS_HPSVSR_SV2_MASK (0x4U) #define SNVS_HPSVSR_SV2_SHIFT (2U) +/*! SV2 + * 0b0..No Security Violation 2 security violation was detected. + * 0b1..Security Violation 2 security violation was detected. + */ #define SNVS_HPSVSR_SV2(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SV2_SHIFT)) & SNVS_HPSVSR_SV2_MASK) #define SNVS_HPSVSR_SV3_MASK (0x8U) #define SNVS_HPSVSR_SV3_SHIFT (3U) +/*! SV3 + * 0b0..No Security Violation 3 security violation was detected. + * 0b1..Security Violation 3 security violation was detected. + */ #define SNVS_HPSVSR_SV3(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SV3_SHIFT)) & SNVS_HPSVSR_SV3_MASK) #define SNVS_HPSVSR_SV4_MASK (0x10U) #define SNVS_HPSVSR_SV4_SHIFT (4U) +/*! SV4 + * 0b0..No Security Violation 4 security violation was detected. + * 0b1..Security Violation 4 security violation was detected. + */ #define SNVS_HPSVSR_SV4(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SV4_SHIFT)) & SNVS_HPSVSR_SV4_MASK) #define SNVS_HPSVSR_SV5_MASK (0x20U) #define SNVS_HPSVSR_SV5_SHIFT (5U) +/*! SV5 + * 0b0..No Security Violation 5 security violation was detected. + * 0b1..Security Violation 5 security violation was detected. + */ #define SNVS_HPSVSR_SV5(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SV5_SHIFT)) & SNVS_HPSVSR_SV5_MASK) #define SNVS_HPSVSR_SW_SV_MASK (0x2000U) #define SNVS_HPSVSR_SW_SV_SHIFT (13U) @@ -17679,100 +28951,194 @@ typedef struct { #define SNVS_HPSVSR_ZMK_SYNDROME(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_ZMK_SYNDROME_SHIFT)) & SNVS_HPSVSR_ZMK_SYNDROME_MASK) #define SNVS_HPSVSR_ZMK_ECC_FAIL_MASK (0x8000000U) #define SNVS_HPSVSR_ZMK_ECC_FAIL_SHIFT (27U) +/*! ZMK_ECC_FAIL + * 0b0..ZMK ECC Failure was not detected. + * 0b1..ZMK ECC Failure was detected. + */ #define SNVS_HPSVSR_ZMK_ECC_FAIL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_ZMK_ECC_FAIL_SHIFT)) & SNVS_HPSVSR_ZMK_ECC_FAIL_MASK) #define SNVS_HPSVSR_LP_SEC_VIO_MASK (0x80000000U) #define SNVS_HPSVSR_LP_SEC_VIO_SHIFT (31U) #define SNVS_HPSVSR_LP_SEC_VIO(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_LP_SEC_VIO_SHIFT)) & SNVS_HPSVSR_LP_SEC_VIO_MASK) +/*! @} */ /*! @name HPHACIVR - SNVS_HP High Assurance Counter IV Register */ +/*! @{ */ #define SNVS_HPHACIVR_HAC_COUNTER_IV_MASK (0xFFFFFFFFU) #define SNVS_HPHACIVR_HAC_COUNTER_IV_SHIFT (0U) #define SNVS_HPHACIVR_HAC_COUNTER_IV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPHACIVR_HAC_COUNTER_IV_SHIFT)) & SNVS_HPHACIVR_HAC_COUNTER_IV_MASK) +/*! @} */ /*! @name HPHACR - SNVS_HP High Assurance Counter Register */ +/*! @{ */ #define SNVS_HPHACR_HAC_COUNTER_MASK (0xFFFFFFFFU) #define SNVS_HPHACR_HAC_COUNTER_SHIFT (0U) #define SNVS_HPHACR_HAC_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPHACR_HAC_COUNTER_SHIFT)) & SNVS_HPHACR_HAC_COUNTER_MASK) +/*! @} */ /*! @name HPRTCMR - SNVS_HP Real Time Counter MSB Register */ +/*! @{ */ #define SNVS_HPRTCMR_RTC_MASK (0x7FFFU) #define SNVS_HPRTCMR_RTC_SHIFT (0U) #define SNVS_HPRTCMR_RTC(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPRTCMR_RTC_SHIFT)) & SNVS_HPRTCMR_RTC_MASK) +/*! @} */ /*! @name HPRTCLR - SNVS_HP Real Time Counter LSB Register */ +/*! @{ */ #define SNVS_HPRTCLR_RTC_MASK (0xFFFFFFFFU) #define SNVS_HPRTCLR_RTC_SHIFT (0U) #define SNVS_HPRTCLR_RTC(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPRTCLR_RTC_SHIFT)) & SNVS_HPRTCLR_RTC_MASK) +/*! @} */ /*! @name HPTAMR - SNVS_HP Time Alarm MSB Register */ +/*! @{ */ #define SNVS_HPTAMR_HPTA_MS_MASK (0x7FFFU) #define SNVS_HPTAMR_HPTA_MS_SHIFT (0U) #define SNVS_HPTAMR_HPTA_MS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPTAMR_HPTA_MS_SHIFT)) & SNVS_HPTAMR_HPTA_MS_MASK) +/*! @} */ /*! @name HPTALR - SNVS_HP Time Alarm LSB Register */ +/*! @{ */ #define SNVS_HPTALR_HPTA_LS_MASK (0xFFFFFFFFU) #define SNVS_HPTALR_HPTA_LS_SHIFT (0U) #define SNVS_HPTALR_HPTA_LS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPTALR_HPTA_LS_SHIFT)) & SNVS_HPTALR_HPTA_LS_MASK) +/*! @} */ /*! @name LPLR - SNVS_LP Lock Register */ +/*! @{ */ #define SNVS_LPLR_ZMK_WHL_MASK (0x1U) #define SNVS_LPLR_ZMK_WHL_SHIFT (0U) +/*! ZMK_WHL + * 0b0..Write access is allowed. + * 0b1..Write access is not allowed. + */ #define SNVS_LPLR_ZMK_WHL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_ZMK_WHL_SHIFT)) & SNVS_LPLR_ZMK_WHL_MASK) #define SNVS_LPLR_ZMK_RHL_MASK (0x2U) #define SNVS_LPLR_ZMK_RHL_SHIFT (1U) +/*! ZMK_RHL + * 0b0..Read access is allowed (only in software programming mode). + * 0b1..Read access is not allowed. + */ #define SNVS_LPLR_ZMK_RHL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_ZMK_RHL_SHIFT)) & SNVS_LPLR_ZMK_RHL_MASK) #define SNVS_LPLR_SRTC_HL_MASK (0x4U) #define SNVS_LPLR_SRTC_HL_SHIFT (2U) +/*! SRTC_HL + * 0b0..Write access is allowed. + * 0b1..Write access is not allowed. + */ #define SNVS_LPLR_SRTC_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_SRTC_HL_SHIFT)) & SNVS_LPLR_SRTC_HL_MASK) #define SNVS_LPLR_LPCALB_HL_MASK (0x8U) #define SNVS_LPLR_LPCALB_HL_SHIFT (3U) +/*! LPCALB_HL + * 0b0..Write access is allowed. + * 0b1..Write access is not allowed. + */ #define SNVS_LPLR_LPCALB_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_LPCALB_HL_SHIFT)) & SNVS_LPLR_LPCALB_HL_MASK) #define SNVS_LPLR_MC_HL_MASK (0x10U) #define SNVS_LPLR_MC_HL_SHIFT (4U) +/*! MC_HL + * 0b0..Write access (increment) is allowed. + * 0b1..Write access (increment) is not allowed. + */ #define SNVS_LPLR_MC_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_MC_HL_SHIFT)) & SNVS_LPLR_MC_HL_MASK) #define SNVS_LPLR_GPR_HL_MASK (0x20U) #define SNVS_LPLR_GPR_HL_SHIFT (5U) +/*! GPR_HL + * 0b0..Write access is allowed. + * 0b1..Write access is not allowed. + */ #define SNVS_LPLR_GPR_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_GPR_HL_SHIFT)) & SNVS_LPLR_GPR_HL_MASK) #define SNVS_LPLR_LPSVCR_HL_MASK (0x40U) #define SNVS_LPLR_LPSVCR_HL_SHIFT (6U) +/*! LPSVCR_HL + * 0b0..Write access is allowed. + * 0b1..Write access is not allowed. + */ #define SNVS_LPLR_LPSVCR_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_LPSVCR_HL_SHIFT)) & SNVS_LPLR_LPSVCR_HL_MASK) #define SNVS_LPLR_LPTDCR_HL_MASK (0x100U) #define SNVS_LPLR_LPTDCR_HL_SHIFT (8U) +/*! LPTDCR_HL + * 0b0..Write access is allowed. + * 0b1..Write access is not allowed. + */ #define SNVS_LPLR_LPTDCR_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_LPTDCR_HL_SHIFT)) & SNVS_LPLR_LPTDCR_HL_MASK) #define SNVS_LPLR_MKS_HL_MASK (0x200U) #define SNVS_LPLR_MKS_HL_SHIFT (9U) +/*! MKS_HL + * 0b0..Write access is allowed. + * 0b1..Write access is not allowed. + */ #define SNVS_LPLR_MKS_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_MKS_HL_SHIFT)) & SNVS_LPLR_MKS_HL_MASK) +/*! @} */ /*! @name LPCR - SNVS_LP Control Register */ +/*! @{ */ #define SNVS_LPCR_SRTC_ENV_MASK (0x1U) #define SNVS_LPCR_SRTC_ENV_SHIFT (0U) +/*! SRTC_ENV + * 0b0..SRTC is disabled or invalid. + * 0b1..SRTC is enabled and valid. + */ #define SNVS_LPCR_SRTC_ENV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_SRTC_ENV_SHIFT)) & SNVS_LPCR_SRTC_ENV_MASK) #define SNVS_LPCR_LPTA_EN_MASK (0x2U) #define SNVS_LPCR_LPTA_EN_SHIFT (1U) +/*! LPTA_EN + * 0b0..LP time alarm interrupt is disabled. + * 0b1..LP time alarm interrupt is enabled. + */ #define SNVS_LPCR_LPTA_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_LPTA_EN_SHIFT)) & SNVS_LPCR_LPTA_EN_MASK) #define SNVS_LPCR_MC_ENV_MASK (0x4U) #define SNVS_LPCR_MC_ENV_SHIFT (2U) +/*! MC_ENV + * 0b0..MC is disabled or invalid. + * 0b1..MC is enabled and valid. + */ #define SNVS_LPCR_MC_ENV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_MC_ENV_SHIFT)) & SNVS_LPCR_MC_ENV_MASK) #define SNVS_LPCR_LPWUI_EN_MASK (0x8U) #define SNVS_LPCR_LPWUI_EN_SHIFT (3U) #define SNVS_LPCR_LPWUI_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_LPWUI_EN_SHIFT)) & SNVS_LPCR_LPWUI_EN_MASK) #define SNVS_LPCR_SRTC_INV_EN_MASK (0x10U) #define SNVS_LPCR_SRTC_INV_EN_SHIFT (4U) +/*! SRTC_INV_EN + * 0b0..SRTC stays valid in the case of security violation. + * 0b1..SRTC is invalidated in the case of security violation. + */ #define SNVS_LPCR_SRTC_INV_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_SRTC_INV_EN_SHIFT)) & SNVS_LPCR_SRTC_INV_EN_MASK) #define SNVS_LPCR_DP_EN_MASK (0x20U) #define SNVS_LPCR_DP_EN_SHIFT (5U) +/*! DP_EN + * 0b0..Smart PMIC enabled. + * 0b1..Dumb PMIC enabled. + */ #define SNVS_LPCR_DP_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_DP_EN_SHIFT)) & SNVS_LPCR_DP_EN_MASK) #define SNVS_LPCR_TOP_MASK (0x40U) #define SNVS_LPCR_TOP_SHIFT (6U) +/*! TOP + * 0b0..Leave system power on. + * 0b1..Turn off system power. + */ #define SNVS_LPCR_TOP(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_TOP_SHIFT)) & SNVS_LPCR_TOP_MASK) #define SNVS_LPCR_PWR_GLITCH_EN_MASK (0x80U) #define SNVS_LPCR_PWR_GLITCH_EN_SHIFT (7U) #define SNVS_LPCR_PWR_GLITCH_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_PWR_GLITCH_EN_SHIFT)) & SNVS_LPCR_PWR_GLITCH_EN_MASK) #define SNVS_LPCR_LPCALB_EN_MASK (0x100U) #define SNVS_LPCR_LPCALB_EN_SHIFT (8U) +/*! LPCALB_EN + * 0b0..SRTC Time calibration is disabled. + * 0b1..SRTC Time calibration is enabled. + */ #define SNVS_LPCR_LPCALB_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_LPCALB_EN_SHIFT)) & SNVS_LPCR_LPCALB_EN_MASK) #define SNVS_LPCR_LPCALB_VAL_MASK (0x7C00U) #define SNVS_LPCR_LPCALB_VAL_SHIFT (10U) +/*! LPCALB_VAL + * 0b00000..+0 counts per each 32768 ticks of the counter clock + * 0b00001..+1 counts per each 32768 ticks of the counter clock + * 0b00010..+2 counts per each 32768 ticks of the counter clock + * 0b01111..+15 counts per each 32768 ticks of the counter clock + * 0b10000..-16 counts per each 32768 ticks of the counter clock + * 0b10001..-15 counts per each 32768 ticks of the counter clock + * 0b11110..-2 counts per each 32768 ticks of the counter clock + * 0b11111..-1 counts per each 32768 ticks of the counter clock + */ #define SNVS_LPCR_LPCALB_VAL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_LPCALB_VAL_SHIFT)) & SNVS_LPCR_LPCALB_VAL_MASK) #define SNVS_LPCR_BTN_PRESS_TIME_MASK (0x30000U) #define SNVS_LPCR_BTN_PRESS_TIME_SHIFT (16U) @@ -17792,56 +29158,119 @@ typedef struct { #define SNVS_LPCR_GPR_Z_DIS_MASK (0x1000000U) #define SNVS_LPCR_GPR_Z_DIS_SHIFT (24U) #define SNVS_LPCR_GPR_Z_DIS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_GPR_Z_DIS_SHIFT)) & SNVS_LPCR_GPR_Z_DIS_MASK) +/*! @} */ /*! @name LPMKCR - SNVS_LP Master Key Control Register */ +/*! @{ */ #define SNVS_LPMKCR_MASTER_KEY_SEL_MASK (0x3U) #define SNVS_LPMKCR_MASTER_KEY_SEL_SHIFT (0U) +/*! MASTER_KEY_SEL + * 0b0x..Select one time programmable master key. + * 0b10..Select zeroizable master key when MKS_EN bit is set . + * 0b11..Select combined master key when MKS_EN bit is set . + */ #define SNVS_LPMKCR_MASTER_KEY_SEL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPMKCR_MASTER_KEY_SEL_SHIFT)) & SNVS_LPMKCR_MASTER_KEY_SEL_MASK) #define SNVS_LPMKCR_ZMK_HWP_MASK (0x4U) #define SNVS_LPMKCR_ZMK_HWP_SHIFT (2U) +/*! ZMK_HWP + * 0b0..ZMK is in the software programming mode. + * 0b1..ZMK is in the hardware programming mode. + */ #define SNVS_LPMKCR_ZMK_HWP(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPMKCR_ZMK_HWP_SHIFT)) & SNVS_LPMKCR_ZMK_HWP_MASK) #define SNVS_LPMKCR_ZMK_VAL_MASK (0x8U) #define SNVS_LPMKCR_ZMK_VAL_SHIFT (3U) +/*! ZMK_VAL + * 0b0..ZMK is not valid. + * 0b1..ZMK is valid. + */ #define SNVS_LPMKCR_ZMK_VAL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPMKCR_ZMK_VAL_SHIFT)) & SNVS_LPMKCR_ZMK_VAL_MASK) #define SNVS_LPMKCR_ZMK_ECC_EN_MASK (0x10U) #define SNVS_LPMKCR_ZMK_ECC_EN_SHIFT (4U) +/*! ZMK_ECC_EN + * 0b0..ZMK ECC check is disabled. + * 0b1..ZMK ECC check is enabled. + */ #define SNVS_LPMKCR_ZMK_ECC_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPMKCR_ZMK_ECC_EN_SHIFT)) & SNVS_LPMKCR_ZMK_ECC_EN_MASK) #define SNVS_LPMKCR_ZMK_ECC_VALUE_MASK (0xFF80U) #define SNVS_LPMKCR_ZMK_ECC_VALUE_SHIFT (7U) #define SNVS_LPMKCR_ZMK_ECC_VALUE(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPMKCR_ZMK_ECC_VALUE_SHIFT)) & SNVS_LPMKCR_ZMK_ECC_VALUE_MASK) +/*! @} */ /*! @name LPSVCR - SNVS_LP Security Violation Control Register */ +/*! @{ */ #define SNVS_LPSVCR_SV0_EN_MASK (0x1U) #define SNVS_LPSVCR_SV0_EN_SHIFT (0U) +/*! SV0_EN + * 0b0..Security Violation 0 is disabled in the LP domain. + * 0b1..Security Violation 0 is enabled in the LP domain. + */ #define SNVS_LPSVCR_SV0_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_SV0_EN_SHIFT)) & SNVS_LPSVCR_SV0_EN_MASK) #define SNVS_LPSVCR_SV1_EN_MASK (0x2U) #define SNVS_LPSVCR_SV1_EN_SHIFT (1U) +/*! SV1_EN + * 0b0..Security Violation 1 is disabled in the LP domain. + * 0b1..Security Violation 1 is enabled in the LP domain. + */ #define SNVS_LPSVCR_SV1_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_SV1_EN_SHIFT)) & SNVS_LPSVCR_SV1_EN_MASK) #define SNVS_LPSVCR_SV2_EN_MASK (0x4U) #define SNVS_LPSVCR_SV2_EN_SHIFT (2U) +/*! SV2_EN + * 0b0..Security Violation 2 is disabled in the LP domain. + * 0b1..Security Violation 2 is enabled in the LP domain. + */ #define SNVS_LPSVCR_SV2_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_SV2_EN_SHIFT)) & SNVS_LPSVCR_SV2_EN_MASK) #define SNVS_LPSVCR_SV3_EN_MASK (0x8U) #define SNVS_LPSVCR_SV3_EN_SHIFT (3U) +/*! SV3_EN + * 0b0..Security Violation 3 is disabled in the LP domain. + * 0b1..Security Violation 3 is enabled in the LP domain. + */ #define SNVS_LPSVCR_SV3_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_SV3_EN_SHIFT)) & SNVS_LPSVCR_SV3_EN_MASK) #define SNVS_LPSVCR_SV4_EN_MASK (0x10U) #define SNVS_LPSVCR_SV4_EN_SHIFT (4U) +/*! SV4_EN + * 0b0..Security Violation 4 is disabled in the LP domain. + * 0b1..Security Violation 4 is enabled in the LP domain. + */ #define SNVS_LPSVCR_SV4_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_SV4_EN_SHIFT)) & SNVS_LPSVCR_SV4_EN_MASK) #define SNVS_LPSVCR_SV5_EN_MASK (0x20U) #define SNVS_LPSVCR_SV5_EN_SHIFT (5U) +/*! SV5_EN + * 0b0..Security Violation 5 is disabled in the LP domain. + * 0b1..Security Violation 5 is enabled in the LP domain. + */ #define SNVS_LPSVCR_SV5_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_SV5_EN_SHIFT)) & SNVS_LPSVCR_SV5_EN_MASK) +/*! @} */ /*! @name LPTDCR - SNVS_LP Tamper Detectors Configuration Register */ +/*! @{ */ #define SNVS_LPTDCR_SRTCR_EN_MASK (0x2U) #define SNVS_LPTDCR_SRTCR_EN_SHIFT (1U) +/*! SRTCR_EN + * 0b0..SRTC rollover is disabled. + * 0b1..SRTC rollover is enabled. + */ #define SNVS_LPTDCR_SRTCR_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_SRTCR_EN_SHIFT)) & SNVS_LPTDCR_SRTCR_EN_MASK) #define SNVS_LPTDCR_MCR_EN_MASK (0x4U) #define SNVS_LPTDCR_MCR_EN_SHIFT (2U) +/*! MCR_EN + * 0b0..MC rollover is disabled. + * 0b1..MC rollover is enabled. + */ #define SNVS_LPTDCR_MCR_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_MCR_EN_SHIFT)) & SNVS_LPTDCR_MCR_EN_MASK) #define SNVS_LPTDCR_ET1_EN_MASK (0x200U) #define SNVS_LPTDCR_ET1_EN_SHIFT (9U) +/*! ET1_EN + * 0b0..External tamper 1 is disabled. + * 0b1..External tamper 1 is enabled. + */ #define SNVS_LPTDCR_ET1_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_ET1_EN_SHIFT)) & SNVS_LPTDCR_ET1_EN_MASK) #define SNVS_LPTDCR_ET1P_MASK (0x800U) #define SNVS_LPTDCR_ET1P_SHIFT (11U) +/*! ET1P + * 0b0..External tamper 1 is active low. + * 0b1..External tamper 1 is active high. + */ #define SNVS_LPTDCR_ET1P(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_ET1P_SHIFT)) & SNVS_LPTDCR_ET1P_MASK) #define SNVS_LPTDCR_PFD_OBSERV_MASK (0x4000U) #define SNVS_LPTDCR_PFD_OBSERV_SHIFT (14U) @@ -17851,106 +29280,174 @@ typedef struct { #define SNVS_LPTDCR_POR_OBSERV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_POR_OBSERV_SHIFT)) & SNVS_LPTDCR_POR_OBSERV_MASK) #define SNVS_LPTDCR_OSCB_MASK (0x10000000U) #define SNVS_LPTDCR_OSCB_SHIFT (28U) +/*! OSCB + * 0b0..Normal SRTC clock oscillator not bypassed. + * 0b1..Normal SRTC clock oscillator bypassed. Alternate clock can drive the SRTC clock source. + */ #define SNVS_LPTDCR_OSCB(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_OSCB_SHIFT)) & SNVS_LPTDCR_OSCB_MASK) +/*! @} */ /*! @name LPSR - SNVS_LP Status Register */ +/*! @{ */ #define SNVS_LPSR_LPTA_MASK (0x1U) #define SNVS_LPSR_LPTA_SHIFT (0U) +/*! LPTA + * 0b0..No time alarm interrupt occurred. + * 0b1..A time alarm interrupt occurred. + */ #define SNVS_LPSR_LPTA(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_LPTA_SHIFT)) & SNVS_LPSR_LPTA_MASK) #define SNVS_LPSR_SRTCR_MASK (0x2U) #define SNVS_LPSR_SRTCR_SHIFT (1U) +/*! SRTCR + * 0b0..SRTC has not reached its maximum value. + * 0b1..SRTC has reached its maximum value. + */ #define SNVS_LPSR_SRTCR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_SRTCR_SHIFT)) & SNVS_LPSR_SRTCR_MASK) #define SNVS_LPSR_MCR_MASK (0x4U) #define SNVS_LPSR_MCR_SHIFT (2U) +/*! MCR + * 0b0..MC has not reached its maximum value. + * 0b1..MC has reached its maximum value. + */ #define SNVS_LPSR_MCR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_MCR_SHIFT)) & SNVS_LPSR_MCR_MASK) #define SNVS_LPSR_PGD_MASK (0x8U) #define SNVS_LPSR_PGD_SHIFT (3U) #define SNVS_LPSR_PGD(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_PGD_SHIFT)) & SNVS_LPSR_PGD_MASK) #define SNVS_LPSR_ET1D_MASK (0x200U) #define SNVS_LPSR_ET1D_SHIFT (9U) +/*! ET1D + * 0b0..External tampering 1 not detected. + * 0b1..External tampering 1 detected. + */ #define SNVS_LPSR_ET1D(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_ET1D_SHIFT)) & SNVS_LPSR_ET1D_MASK) #define SNVS_LPSR_ESVD_MASK (0x10000U) #define SNVS_LPSR_ESVD_SHIFT (16U) +/*! ESVD + * 0b0..No external security violation. + * 0b1..External security violation is detected. + */ #define SNVS_LPSR_ESVD(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_ESVD_SHIFT)) & SNVS_LPSR_ESVD_MASK) #define SNVS_LPSR_EO_MASK (0x20000U) #define SNVS_LPSR_EO_SHIFT (17U) +/*! EO + * 0b0..Emergency off was not detected. + * 0b1..Emergency off was detected. + */ #define SNVS_LPSR_EO(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_EO_SHIFT)) & SNVS_LPSR_EO_MASK) #define SNVS_LPSR_SPO_MASK (0x40000U) #define SNVS_LPSR_SPO_SHIFT (18U) +/*! SPO + * 0b0..Set Power Off was not detected. + * 0b1..Set Power Off was detected. + */ #define SNVS_LPSR_SPO(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_SPO_SHIFT)) & SNVS_LPSR_SPO_MASK) #define SNVS_LPSR_SED_MASK (0x100000U) #define SNVS_LPSR_SED_SHIFT (20U) +/*! SED + * 0b0..Scan exit was not detected. + * 0b1..Scan exit was detected. + */ #define SNVS_LPSR_SED(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_SED_SHIFT)) & SNVS_LPSR_SED_MASK) #define SNVS_LPSR_LPNS_MASK (0x40000000U) #define SNVS_LPSR_LPNS_SHIFT (30U) +/*! LPNS + * 0b0..LP section was not programmed in the non-secure state. + * 0b1..LP section was programmed in the non-secure state. + */ #define SNVS_LPSR_LPNS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_LPNS_SHIFT)) & SNVS_LPSR_LPNS_MASK) #define SNVS_LPSR_LPS_MASK (0x80000000U) #define SNVS_LPSR_LPS_SHIFT (31U) +/*! LPS + * 0b0..LP section was not programmed in secure or trusted state. + * 0b1..LP section was programmed in secure or trusted state. + */ #define SNVS_LPSR_LPS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_LPS_SHIFT)) & SNVS_LPSR_LPS_MASK) +/*! @} */ /*! @name LPSRTCMR - SNVS_LP Secure Real Time Counter MSB Register */ +/*! @{ */ #define SNVS_LPSRTCMR_SRTC_MASK (0x7FFFU) #define SNVS_LPSRTCMR_SRTC_SHIFT (0U) #define SNVS_LPSRTCMR_SRTC(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSRTCMR_SRTC_SHIFT)) & SNVS_LPSRTCMR_SRTC_MASK) +/*! @} */ /*! @name LPSRTCLR - SNVS_LP Secure Real Time Counter LSB Register */ +/*! @{ */ #define SNVS_LPSRTCLR_SRTC_MASK (0xFFFFFFFFU) #define SNVS_LPSRTCLR_SRTC_SHIFT (0U) #define SNVS_LPSRTCLR_SRTC(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSRTCLR_SRTC_SHIFT)) & SNVS_LPSRTCLR_SRTC_MASK) +/*! @} */ /*! @name LPTAR - SNVS_LP Time Alarm Register */ +/*! @{ */ #define SNVS_LPTAR_LPTA_MASK (0xFFFFFFFFU) #define SNVS_LPTAR_LPTA_SHIFT (0U) #define SNVS_LPTAR_LPTA(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTAR_LPTA_SHIFT)) & SNVS_LPTAR_LPTA_MASK) +/*! @} */ /*! @name LPSMCMR - SNVS_LP Secure Monotonic Counter MSB Register */ +/*! @{ */ #define SNVS_LPSMCMR_MON_COUNTER_MASK (0xFFFFU) #define SNVS_LPSMCMR_MON_COUNTER_SHIFT (0U) #define SNVS_LPSMCMR_MON_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSMCMR_MON_COUNTER_SHIFT)) & SNVS_LPSMCMR_MON_COUNTER_MASK) #define SNVS_LPSMCMR_MC_ERA_BITS_MASK (0xFFFF0000U) #define SNVS_LPSMCMR_MC_ERA_BITS_SHIFT (16U) #define SNVS_LPSMCMR_MC_ERA_BITS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSMCMR_MC_ERA_BITS_SHIFT)) & SNVS_LPSMCMR_MC_ERA_BITS_MASK) +/*! @} */ /*! @name LPSMCLR - SNVS_LP Secure Monotonic Counter LSB Register */ +/*! @{ */ #define SNVS_LPSMCLR_MON_COUNTER_MASK (0xFFFFFFFFU) #define SNVS_LPSMCLR_MON_COUNTER_SHIFT (0U) #define SNVS_LPSMCLR_MON_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSMCLR_MON_COUNTER_SHIFT)) & SNVS_LPSMCLR_MON_COUNTER_MASK) +/*! @} */ /*! @name LPPGDR - SNVS_LP Power Glitch Detector Register */ +/*! @{ */ #define SNVS_LPPGDR_PGD_MASK (0xFFFFFFFFU) #define SNVS_LPPGDR_PGD_SHIFT (0U) #define SNVS_LPPGDR_PGD(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPPGDR_PGD_SHIFT)) & SNVS_LPPGDR_PGD_MASK) +/*! @} */ /*! @name LPGPR0_LEGACY_ALIAS - SNVS_LP General Purpose Register 0 (legacy alias) */ +/*! @{ */ #define SNVS_LPGPR0_LEGACY_ALIAS_GPR_MASK (0xFFFFFFFFU) #define SNVS_LPGPR0_LEGACY_ALIAS_GPR_SHIFT (0U) #define SNVS_LPGPR0_LEGACY_ALIAS_GPR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPGPR0_LEGACY_ALIAS_GPR_SHIFT)) & SNVS_LPGPR0_LEGACY_ALIAS_GPR_MASK) +/*! @} */ /*! @name LPZMKR - SNVS_LP Zeroizable Master Key Register */ +/*! @{ */ #define SNVS_LPZMKR_ZMK_MASK (0xFFFFFFFFU) #define SNVS_LPZMKR_ZMK_SHIFT (0U) #define SNVS_LPZMKR_ZMK(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPZMKR_ZMK_SHIFT)) & SNVS_LPZMKR_ZMK_MASK) +/*! @} */ /* The count of SNVS_LPZMKR */ #define SNVS_LPZMKR_COUNT (8U) /*! @name LPGPR_ALIAS - SNVS_LP General Purpose Registers 0 .. 3 */ +/*! @{ */ #define SNVS_LPGPR_ALIAS_GPR_MASK (0xFFFFFFFFU) #define SNVS_LPGPR_ALIAS_GPR_SHIFT (0U) #define SNVS_LPGPR_ALIAS_GPR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPGPR_ALIAS_GPR_SHIFT)) & SNVS_LPGPR_ALIAS_GPR_MASK) +/*! @} */ /* The count of SNVS_LPGPR_ALIAS */ #define SNVS_LPGPR_ALIAS_COUNT (4U) -/*! @name LPGPR - SNVS_LP General Purpose Registers 0 .. 3 */ +/*! @name LPGPR - SNVS_LP General Purpose Registers 0 .. 7 */ +/*! @{ */ #define SNVS_LPGPR_GPR_MASK (0xFFFFFFFFU) #define SNVS_LPGPR_GPR_SHIFT (0U) #define SNVS_LPGPR_GPR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPGPR_GPR_SHIFT)) & SNVS_LPGPR_GPR_MASK) +/*! @} */ /* The count of SNVS_LPGPR */ -#define SNVS_LPGPR_COUNT (4U) +#define SNVS_LPGPR_COUNT (8U) /*! @name HPVIDR1 - SNVS_HP Version ID Register 1 */ +/*! @{ */ #define SNVS_HPVIDR1_MINOR_REV_MASK (0xFFU) #define SNVS_HPVIDR1_MINOR_REV_SHIFT (0U) #define SNVS_HPVIDR1_MINOR_REV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR1_MINOR_REV_SHIFT)) & SNVS_HPVIDR1_MINOR_REV_MASK) @@ -17960,8 +29457,10 @@ typedef struct { #define SNVS_HPVIDR1_IP_ID_MASK (0xFFFF0000U) #define SNVS_HPVIDR1_IP_ID_SHIFT (16U) #define SNVS_HPVIDR1_IP_ID(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR1_IP_ID_SHIFT)) & SNVS_HPVIDR1_IP_ID_MASK) +/*! @} */ /*! @name HPVIDR2 - SNVS_HP Version ID Register 2 */ +/*! @{ */ #define SNVS_HPVIDR2_CONFIG_OPT_MASK (0xFFU) #define SNVS_HPVIDR2_CONFIG_OPT_SHIFT (0U) #define SNVS_HPVIDR2_CONFIG_OPT(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR2_CONFIG_OPT_SHIFT)) & SNVS_HPVIDR2_CONFIG_OPT_MASK) @@ -17974,6 +29473,7 @@ typedef struct { #define SNVS_HPVIDR2_IP_ERA_MASK (0xFF000000U) #define SNVS_HPVIDR2_IP_ERA_SHIFT (24U) #define SNVS_HPVIDR2_IP_ERA(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR2_IP_ERA_SHIFT)) & SNVS_HPVIDR2_IP_ERA_MASK) +/*! @} */ /*! @@ -18045,14 +29545,30 @@ typedef struct { */ /*! @name SCR - SPDIF Configuration Register */ +/*! @{ */ #define SPDIF_SCR_USRC_SEL_MASK (0x3U) #define SPDIF_SCR_USRC_SEL_SHIFT (0U) +/*! USrc_Sel + * 0b00..No embedded U channel + * 0b01..U channel from SPDIF receive block (CD mode) + * 0b10..Reserved + * 0b11..U channel from on chip transmitter + */ #define SPDIF_SCR_USRC_SEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_USRC_SEL_SHIFT)) & SPDIF_SCR_USRC_SEL_MASK) #define SPDIF_SCR_TXSEL_MASK (0x1CU) #define SPDIF_SCR_TXSEL_SHIFT (2U) +/*! TxSel + * 0b000..Off and output 0 + * 0b001..Feed-through SPDIFIN + * 0b101..Tx Normal operation + */ #define SPDIF_SCR_TXSEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_TXSEL_SHIFT)) & SPDIF_SCR_TXSEL_MASK) #define SPDIF_SCR_VALCTRL_MASK (0x20U) #define SPDIF_SCR_VALCTRL_SHIFT (5U) +/*! ValCtrl + * 0b0..Outgoing Validity always set + * 0b1..Outgoing Validity always clear + */ #define SPDIF_SCR_VALCTRL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_VALCTRL_SHIFT)) & SPDIF_SCR_VALCTRL_MASK) #define SPDIF_SCR_DMA_TX_EN_MASK (0x100U) #define SPDIF_SCR_DMA_TX_EN_SHIFT (8U) @@ -18062,6 +29578,12 @@ typedef struct { #define SPDIF_SCR_DMA_RX_EN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_DMA_RX_EN_SHIFT)) & SPDIF_SCR_DMA_RX_EN_MASK) #define SPDIF_SCR_TXFIFO_CTRL_MASK (0xC00U) #define SPDIF_SCR_TXFIFO_CTRL_SHIFT (10U) +/*! TxFIFO_Ctrl + * 0b00..Send out digital zero on SPDIF Tx + * 0b01..Tx Normal operation + * 0b10..Reset to 1 sample remaining + * 0b11..Reserved + */ #define SPDIF_SCR_TXFIFO_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_TXFIFO_CTRL_SHIFT)) & SPDIF_SCR_TXFIFO_CTRL_MASK) #define SPDIF_SCR_SOFT_RESET_MASK (0x1000U) #define SPDIF_SCR_SOFT_RESET_SHIFT (12U) @@ -18071,43 +29593,102 @@ typedef struct { #define SPDIF_SCR_LOW_POWER(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_LOW_POWER_SHIFT)) & SPDIF_SCR_LOW_POWER_MASK) #define SPDIF_SCR_TXFIFOEMPTY_SEL_MASK (0x18000U) #define SPDIF_SCR_TXFIFOEMPTY_SEL_SHIFT (15U) +/*! TxFIFOEmpty_Sel + * 0b00..Empty interrupt if 0 sample in Tx left and right FIFOs + * 0b01..Empty interrupt if at most 4 sample in Tx left and right FIFOs + * 0b10..Empty interrupt if at most 8 sample in Tx left and right FIFOs + * 0b11..Empty interrupt if at most 12 sample in Tx left and right FIFOs + */ #define SPDIF_SCR_TXFIFOEMPTY_SEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_TXFIFOEMPTY_SEL_SHIFT)) & SPDIF_SCR_TXFIFOEMPTY_SEL_MASK) #define SPDIF_SCR_TXAUTOSYNC_MASK (0x20000U) #define SPDIF_SCR_TXAUTOSYNC_SHIFT (17U) +/*! TxAutoSync + * 0b0..Tx FIFO auto sync off + * 0b1..Tx FIFO auto sync on + */ #define SPDIF_SCR_TXAUTOSYNC(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_TXAUTOSYNC_SHIFT)) & SPDIF_SCR_TXAUTOSYNC_MASK) #define SPDIF_SCR_RXAUTOSYNC_MASK (0x40000U) #define SPDIF_SCR_RXAUTOSYNC_SHIFT (18U) +/*! RxAutoSync + * 0b0..Rx FIFO auto sync off + * 0b1..RxFIFO auto sync on + */ #define SPDIF_SCR_RXAUTOSYNC(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_RXAUTOSYNC_SHIFT)) & SPDIF_SCR_RXAUTOSYNC_MASK) #define SPDIF_SCR_RXFIFOFULL_SEL_MASK (0x180000U) #define SPDIF_SCR_RXFIFOFULL_SEL_SHIFT (19U) +/*! RxFIFOFull_Sel + * 0b00..Full interrupt if at least 1 sample in Rx left and right FIFOs + * 0b01..Full interrupt if at least 4 sample in Rx left and right FIFOs + * 0b10..Full interrupt if at least 8 sample in Rx left and right FIFOs + * 0b11..Full interrupt if at least 16 sample in Rx left and right FIFO + */ #define SPDIF_SCR_RXFIFOFULL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_RXFIFOFULL_SEL_SHIFT)) & SPDIF_SCR_RXFIFOFULL_SEL_MASK) #define SPDIF_SCR_RXFIFO_RST_MASK (0x200000U) #define SPDIF_SCR_RXFIFO_RST_SHIFT (21U) +/*! RxFIFO_Rst + * 0b0..Normal operation + * 0b1..Reset register to 1 sample remaining + */ #define SPDIF_SCR_RXFIFO_RST(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_RXFIFO_RST_SHIFT)) & SPDIF_SCR_RXFIFO_RST_MASK) #define SPDIF_SCR_RXFIFO_OFF_ON_MASK (0x400000U) #define SPDIF_SCR_RXFIFO_OFF_ON_SHIFT (22U) +/*! RxFIFO_Off_On + * 0b0..SPDIF Rx FIFO is on + * 0b1..SPDIF Rx FIFO is off. Does not accept data from interface + */ #define SPDIF_SCR_RXFIFO_OFF_ON(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_RXFIFO_OFF_ON_SHIFT)) & SPDIF_SCR_RXFIFO_OFF_ON_MASK) #define SPDIF_SCR_RXFIFO_CTRL_MASK (0x800000U) #define SPDIF_SCR_RXFIFO_CTRL_SHIFT (23U) +/*! RxFIFO_Ctrl + * 0b0..Normal operation + * 0b1..Always read zero from Rx data register + */ #define SPDIF_SCR_RXFIFO_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_RXFIFO_CTRL_SHIFT)) & SPDIF_SCR_RXFIFO_CTRL_MASK) +/*! @} */ /*! @name SRCD - CDText Control Register */ +/*! @{ */ #define SPDIF_SRCD_USYNCMODE_MASK (0x2U) #define SPDIF_SRCD_USYNCMODE_SHIFT (1U) +/*! USyncMode + * 0b0..Non-CD data + * 0b1..CD user channel subcode + */ #define SPDIF_SRCD_USYNCMODE(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRCD_USYNCMODE_SHIFT)) & SPDIF_SRCD_USYNCMODE_MASK) +/*! @} */ /*! @name SRPC - PhaseConfig Register */ +/*! @{ */ #define SPDIF_SRPC_GAINSEL_MASK (0x38U) #define SPDIF_SRPC_GAINSEL_SHIFT (3U) +/*! GainSel + * 0b000..24*(2**10) + * 0b001..16*(2**10) + * 0b010..12*(2**10) + * 0b011..8*(2**10) + * 0b100..6*(2**10) + * 0b101..4*(2**10) + * 0b110..3*(2**10) + */ #define SPDIF_SRPC_GAINSEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRPC_GAINSEL_SHIFT)) & SPDIF_SRPC_GAINSEL_MASK) #define SPDIF_SRPC_LOCK_MASK (0x40U) #define SPDIF_SRPC_LOCK_SHIFT (6U) #define SPDIF_SRPC_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRPC_LOCK_SHIFT)) & SPDIF_SRPC_LOCK_MASK) #define SPDIF_SRPC_CLKSRC_SEL_MASK (0x780U) #define SPDIF_SRPC_CLKSRC_SEL_SHIFT (7U) +/*! ClkSrc_Sel + * 0b0000..if (DPLL Locked) SPDIF_RxClk else REF_CLK_32K (XTALOSC) + * 0b0001..if (DPLL Locked) SPDIF_RxClk else tx_clk (SPDIF0_CLK_ROOT) + * 0b0011..if (DPLL Locked) SPDIF_RxClk else SPDIF_EXT_CLK + * 0b0101..REF_CLK_32K (XTALOSC) + * 0b0110..tx_clk (SPDIF0_CLK_ROOT) + * 0b1000..SPDIF_EXT_CLK + */ #define SPDIF_SRPC_CLKSRC_SEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRPC_CLKSRC_SEL_SHIFT)) & SPDIF_SRPC_CLKSRC_SEL_MASK) +/*! @} */ /*! @name SIE - InterruptEn Register */ +/*! @{ */ #define SPDIF_SIE_RXFIFOFUL_MASK (0x1U) #define SPDIF_SIE_RXFIFOFUL_SHIFT (0U) #define SPDIF_SIE_RXFIFOFUL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_RXFIFOFUL_SHIFT)) & SPDIF_SIE_RXFIFOFUL_MASK) @@ -18162,8 +29743,10 @@ typedef struct { #define SPDIF_SIE_LOCK_MASK (0x100000U) #define SPDIF_SIE_LOCK_SHIFT (20U) #define SPDIF_SIE_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_LOCK_SHIFT)) & SPDIF_SIE_LOCK_MASK) +/*! @} */ /*! @name SIC - InterruptClear Register */ +/*! @{ */ #define SPDIF_SIC_LOCKLOSS_MASK (0x4U) #define SPDIF_SIC_LOCKLOSS_SHIFT (2U) #define SPDIF_SIC_LOCKLOSS(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_LOCKLOSS_SHIFT)) & SPDIF_SIC_LOCKLOSS_MASK) @@ -18206,8 +29789,10 @@ typedef struct { #define SPDIF_SIC_LOCK_MASK (0x100000U) #define SPDIF_SIC_LOCK_SHIFT (20U) #define SPDIF_SIC_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_LOCK_SHIFT)) & SPDIF_SIC_LOCK_MASK) +/*! @} */ /*! @name SIS - InterruptStat Register */ +/*! @{ */ #define SPDIF_SIS_RXFIFOFUL_MASK (0x1U) #define SPDIF_SIS_RXFIFOFUL_SHIFT (0U) #define SPDIF_SIS_RXFIFOFUL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_RXFIFOFUL_SHIFT)) & SPDIF_SIS_RXFIFOFUL_MASK) @@ -18262,75 +29847,120 @@ typedef struct { #define SPDIF_SIS_LOCK_MASK (0x100000U) #define SPDIF_SIS_LOCK_SHIFT (20U) #define SPDIF_SIS_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_LOCK_SHIFT)) & SPDIF_SIS_LOCK_MASK) +/*! @} */ /*! @name SRL - SPDIFRxLeft Register */ +/*! @{ */ #define SPDIF_SRL_RXDATALEFT_MASK (0xFFFFFFU) #define SPDIF_SRL_RXDATALEFT_SHIFT (0U) #define SPDIF_SRL_RXDATALEFT(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRL_RXDATALEFT_SHIFT)) & SPDIF_SRL_RXDATALEFT_MASK) +/*! @} */ /*! @name SRR - SPDIFRxRight Register */ +/*! @{ */ #define SPDIF_SRR_RXDATARIGHT_MASK (0xFFFFFFU) #define SPDIF_SRR_RXDATARIGHT_SHIFT (0U) #define SPDIF_SRR_RXDATARIGHT(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRR_RXDATARIGHT_SHIFT)) & SPDIF_SRR_RXDATARIGHT_MASK) +/*! @} */ /*! @name SRCSH - SPDIFRxCChannel_h Register */ +/*! @{ */ #define SPDIF_SRCSH_RXCCHANNEL_H_MASK (0xFFFFFFU) #define SPDIF_SRCSH_RXCCHANNEL_H_SHIFT (0U) #define SPDIF_SRCSH_RXCCHANNEL_H(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRCSH_RXCCHANNEL_H_SHIFT)) & SPDIF_SRCSH_RXCCHANNEL_H_MASK) +/*! @} */ /*! @name SRCSL - SPDIFRxCChannel_l Register */ +/*! @{ */ #define SPDIF_SRCSL_RXCCHANNEL_L_MASK (0xFFFFFFU) #define SPDIF_SRCSL_RXCCHANNEL_L_SHIFT (0U) #define SPDIF_SRCSL_RXCCHANNEL_L(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRCSL_RXCCHANNEL_L_SHIFT)) & SPDIF_SRCSL_RXCCHANNEL_L_MASK) +/*! @} */ /*! @name SRU - UchannelRx Register */ +/*! @{ */ #define SPDIF_SRU_RXUCHANNEL_MASK (0xFFFFFFU) #define SPDIF_SRU_RXUCHANNEL_SHIFT (0U) #define SPDIF_SRU_RXUCHANNEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRU_RXUCHANNEL_SHIFT)) & SPDIF_SRU_RXUCHANNEL_MASK) +/*! @} */ /*! @name SRQ - QchannelRx Register */ +/*! @{ */ #define SPDIF_SRQ_RXQCHANNEL_MASK (0xFFFFFFU) #define SPDIF_SRQ_RXQCHANNEL_SHIFT (0U) #define SPDIF_SRQ_RXQCHANNEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRQ_RXQCHANNEL_SHIFT)) & SPDIF_SRQ_RXQCHANNEL_MASK) +/*! @} */ /*! @name STL - SPDIFTxLeft Register */ +/*! @{ */ #define SPDIF_STL_TXDATALEFT_MASK (0xFFFFFFU) #define SPDIF_STL_TXDATALEFT_SHIFT (0U) #define SPDIF_STL_TXDATALEFT(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STL_TXDATALEFT_SHIFT)) & SPDIF_STL_TXDATALEFT_MASK) +/*! @} */ /*! @name STR - SPDIFTxRight Register */ +/*! @{ */ #define SPDIF_STR_TXDATARIGHT_MASK (0xFFFFFFU) #define SPDIF_STR_TXDATARIGHT_SHIFT (0U) #define SPDIF_STR_TXDATARIGHT(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STR_TXDATARIGHT_SHIFT)) & SPDIF_STR_TXDATARIGHT_MASK) +/*! @} */ /*! @name STCSCH - SPDIFTxCChannelCons_h Register */ +/*! @{ */ #define SPDIF_STCSCH_TXCCHANNELCONS_H_MASK (0xFFFFFFU) #define SPDIF_STCSCH_TXCCHANNELCONS_H_SHIFT (0U) #define SPDIF_STCSCH_TXCCHANNELCONS_H(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STCSCH_TXCCHANNELCONS_H_SHIFT)) & SPDIF_STCSCH_TXCCHANNELCONS_H_MASK) +/*! @} */ /*! @name STCSCL - SPDIFTxCChannelCons_l Register */ +/*! @{ */ #define SPDIF_STCSCL_TXCCHANNELCONS_L_MASK (0xFFFFFFU) #define SPDIF_STCSCL_TXCCHANNELCONS_L_SHIFT (0U) #define SPDIF_STCSCL_TXCCHANNELCONS_L(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STCSCL_TXCCHANNELCONS_L_SHIFT)) & SPDIF_STCSCL_TXCCHANNELCONS_L_MASK) +/*! @} */ /*! @name SRFM - FreqMeas Register */ +/*! @{ */ #define SPDIF_SRFM_FREQMEAS_MASK (0xFFFFFFU) #define SPDIF_SRFM_FREQMEAS_SHIFT (0U) #define SPDIF_SRFM_FREQMEAS(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRFM_FREQMEAS_SHIFT)) & SPDIF_SRFM_FREQMEAS_MASK) +/*! @} */ /*! @name STC - SPDIFTxClk Register */ +/*! @{ */ #define SPDIF_STC_TXCLK_DF_MASK (0x7FU) #define SPDIF_STC_TXCLK_DF_SHIFT (0U) +/*! TxClk_DF + * 0b0000000..divider factor is 1 + * 0b0000001..divider factor is 2 + * 0b1111111..divider factor is 128 + */ #define SPDIF_STC_TXCLK_DF(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STC_TXCLK_DF_SHIFT)) & SPDIF_STC_TXCLK_DF_MASK) #define SPDIF_STC_TX_ALL_CLK_EN_MASK (0x80U) #define SPDIF_STC_TX_ALL_CLK_EN_SHIFT (7U) +/*! tx_all_clk_en + * 0b0..disable transfer clock. + * 0b1..enable transfer clock. + */ #define SPDIF_STC_TX_ALL_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STC_TX_ALL_CLK_EN_SHIFT)) & SPDIF_STC_TX_ALL_CLK_EN_MASK) #define SPDIF_STC_TXCLK_SOURCE_MASK (0x700U) #define SPDIF_STC_TXCLK_SOURCE_SHIFT (8U) +/*! TxClk_Source + * 0b000..REF_CLK_32K input (XTALOSC 32 kHz clock) + * 0b001..tx_clk input (from SPDIF0_CLK_ROOT. See CCM.) + * 0b011..SPDIF_EXT_CLK, from pads + * 0b101..ipg_clk input (frequency divided) + */ #define SPDIF_STC_TXCLK_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STC_TXCLK_SOURCE_SHIFT)) & SPDIF_STC_TXCLK_SOURCE_MASK) #define SPDIF_STC_SYSCLK_DF_MASK (0xFF800U) #define SPDIF_STC_SYSCLK_DF_SHIFT (11U) +/*! SYSCLK_DF + * 0b000000000..no clock signal + * 0b000000001..divider factor is 2 + * 0b111111111..divider factor is 512 + */ #define SPDIF_STC_SYSCLK_DF(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STC_SYSCLK_DF_SHIFT)) & SPDIF_STC_SYSCLK_DF_MASK) +/*! @} */ /*! @@ -18384,26 +30014,46 @@ typedef struct { */ /*! @name SCR - SRC Control Register */ -#define SRC_SCR_LOCKUP_RST_MASK (0x10U) -#define SRC_SCR_LOCKUP_RST_SHIFT (4U) -#define SRC_SCR_LOCKUP_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_LOCKUP_RST_SHIFT)) & SRC_SCR_LOCKUP_RST_MASK) +/*! @{ */ #define SRC_SCR_MASK_WDOG_RST_MASK (0x780U) #define SRC_SCR_MASK_WDOG_RST_SHIFT (7U) +/*! mask_wdog_rst + * 0b0101..wdog_rst_b is masked + * 0b1010..wdog_rst_b is not masked (default) + */ #define SRC_SCR_MASK_WDOG_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_MASK_WDOG_RST_SHIFT)) & SRC_SCR_MASK_WDOG_RST_MASK) #define SRC_SCR_CORE0_RST_MASK (0x2000U) #define SRC_SCR_CORE0_RST_SHIFT (13U) +/*! core0_rst + * 0b0..do not assert core0 reset + * 0b1..assert core0 reset + */ #define SRC_SCR_CORE0_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_CORE0_RST_SHIFT)) & SRC_SCR_CORE0_RST_MASK) #define SRC_SCR_CORE0_DBG_RST_MASK (0x20000U) #define SRC_SCR_CORE0_DBG_RST_SHIFT (17U) +/*! core0_dbg_rst + * 0b0..do not assert core0 debug reset + * 0b1..assert core0 debug reset + */ #define SRC_SCR_CORE0_DBG_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_CORE0_DBG_RST_SHIFT)) & SRC_SCR_CORE0_DBG_RST_MASK) #define SRC_SCR_DBG_RST_MSK_PG_MASK (0x2000000U) #define SRC_SCR_DBG_RST_MSK_PG_SHIFT (25U) +/*! dbg_rst_msk_pg + * 0b0..do not mask core debug resets (debug resets will be asserted after power gating event) + * 0b1..mask core debug resets (debug resets won't be asserted after power gating event) + */ #define SRC_SCR_DBG_RST_MSK_PG(x) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_DBG_RST_MSK_PG_SHIFT)) & SRC_SCR_DBG_RST_MSK_PG_MASK) #define SRC_SCR_MASK_WDOG3_RST_MASK (0xF0000000U) #define SRC_SCR_MASK_WDOG3_RST_SHIFT (28U) +/*! mask_wdog3_rst + * 0b0101..wdog3_rst_b is masked + * 0b1010..wdog3_rst_b is not masked + */ #define SRC_SCR_MASK_WDOG3_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_MASK_WDOG3_RST_SHIFT)) & SRC_SCR_MASK_WDOG3_RST_MASK) +/*! @} */ /*! @name SBMR1 - SRC Boot Mode Register 1 */ +/*! @{ */ #define SRC_SBMR1_BOOT_CFG1_MASK (0xFFU) #define SRC_SBMR1_BOOT_CFG1_SHIFT (0U) #define SRC_SBMR1_BOOT_CFG1(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR1_BOOT_CFG1_SHIFT)) & SRC_SBMR1_BOOT_CFG1_MASK) @@ -18416,37 +30066,77 @@ typedef struct { #define SRC_SBMR1_BOOT_CFG4_MASK (0xFF000000U) #define SRC_SBMR1_BOOT_CFG4_SHIFT (24U) #define SRC_SBMR1_BOOT_CFG4(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR1_BOOT_CFG4_SHIFT)) & SRC_SBMR1_BOOT_CFG4_MASK) +/*! @} */ /*! @name SRSR - SRC Reset Status Register */ +/*! @{ */ #define SRC_SRSR_IPP_RESET_B_MASK (0x1U) #define SRC_SRSR_IPP_RESET_B_SHIFT (0U) +/*! ipp_reset_b + * 0b0..Reset is not a result of ipp_reset_b pin. + * 0b1..Reset is a result of ipp_reset_b pin. + */ #define SRC_SRSR_IPP_RESET_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_IPP_RESET_B_SHIFT)) & SRC_SRSR_IPP_RESET_B_MASK) #define SRC_SRSR_LOCKUP_SYSRESETREQ_MASK (0x2U) #define SRC_SRSR_LOCKUP_SYSRESETREQ_SHIFT (1U) +/*! lockup_sysresetreq + * 0b0..Reset is not a result of the mentioned case. + * 0b1..Reset is a result of the mentioned case. + */ #define SRC_SRSR_LOCKUP_SYSRESETREQ(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_LOCKUP_SYSRESETREQ_SHIFT)) & SRC_SRSR_LOCKUP_SYSRESETREQ_MASK) #define SRC_SRSR_CSU_RESET_B_MASK (0x4U) #define SRC_SRSR_CSU_RESET_B_SHIFT (2U) +/*! csu_reset_b + * 0b0..Reset is not a result of the csu_reset_b event. + * 0b1..Reset is a result of the csu_reset_b event. + */ #define SRC_SRSR_CSU_RESET_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_CSU_RESET_B_SHIFT)) & SRC_SRSR_CSU_RESET_B_MASK) #define SRC_SRSR_IPP_USER_RESET_B_MASK (0x8U) #define SRC_SRSR_IPP_USER_RESET_B_SHIFT (3U) +/*! ipp_user_reset_b + * 0b0..Reset is not a result of the ipp_user_reset_b qualified as COLD reset event. + * 0b1..Reset is a result of the ipp_user_reset_b qualified as COLD reset event. + */ #define SRC_SRSR_IPP_USER_RESET_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_IPP_USER_RESET_B_SHIFT)) & SRC_SRSR_IPP_USER_RESET_B_MASK) #define SRC_SRSR_WDOG_RST_B_MASK (0x10U) #define SRC_SRSR_WDOG_RST_B_SHIFT (4U) +/*! wdog_rst_b + * 0b0..Reset is not a result of the watchdog time-out event. + * 0b1..Reset is a result of the watchdog time-out event. + */ #define SRC_SRSR_WDOG_RST_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_WDOG_RST_B_SHIFT)) & SRC_SRSR_WDOG_RST_B_MASK) #define SRC_SRSR_JTAG_RST_B_MASK (0x20U) #define SRC_SRSR_JTAG_RST_B_SHIFT (5U) +/*! jtag_rst_b + * 0b0..Reset is not a result of HIGH-Z reset from JTAG. + * 0b1..Reset is a result of HIGH-Z reset from JTAG. + */ #define SRC_SRSR_JTAG_RST_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_JTAG_RST_B_SHIFT)) & SRC_SRSR_JTAG_RST_B_MASK) #define SRC_SRSR_JTAG_SW_RST_MASK (0x40U) #define SRC_SRSR_JTAG_SW_RST_SHIFT (6U) +/*! jtag_sw_rst + * 0b0..Reset is not a result of software reset from JTAG. + * 0b1..Reset is a result of software reset from JTAG. + */ #define SRC_SRSR_JTAG_SW_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_JTAG_SW_RST_SHIFT)) & SRC_SRSR_JTAG_SW_RST_MASK) #define SRC_SRSR_WDOG3_RST_B_MASK (0x80U) #define SRC_SRSR_WDOG3_RST_B_SHIFT (7U) +/*! wdog3_rst_b + * 0b0..Reset is not a result of the watchdog3 time-out event. + * 0b1..Reset is a result of the watchdog3 time-out event. + */ #define SRC_SRSR_WDOG3_RST_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_WDOG3_RST_B_SHIFT)) & SRC_SRSR_WDOG3_RST_B_MASK) #define SRC_SRSR_TEMPSENSE_RST_B_MASK (0x100U) #define SRC_SRSR_TEMPSENSE_RST_B_SHIFT (8U) +/*! tempsense_rst_b + * 0b0..Reset is not a result of software reset from Temperature Sensor. + * 0b1..Reset is a result of software reset from Temperature Sensor. + */ #define SRC_SRSR_TEMPSENSE_RST_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_TEMPSENSE_RST_B_SHIFT)) & SRC_SRSR_TEMPSENSE_RST_B_MASK) +/*! @} */ /*! @name SBMR2 - SRC Boot Mode Register 2 */ +/*! @{ */ #define SRC_SBMR2_SEC_CONFIG_MASK (0x3U) #define SRC_SBMR2_SEC_CONFIG_SHIFT (0U) #define SRC_SBMR2_SEC_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR2_SEC_CONFIG_SHIFT)) & SRC_SBMR2_SEC_CONFIG_MASK) @@ -18459,14 +30149,17 @@ typedef struct { #define SRC_SBMR2_BMOD_MASK (0x3000000U) #define SRC_SBMR2_BMOD_SHIFT (24U) #define SRC_SBMR2_BMOD(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR2_BMOD_SHIFT)) & SRC_SBMR2_BMOD_MASK) +/*! @} */ /*! @name GPR - SRC General Purpose Register 1..SRC General Purpose Register 10 */ -#define SRC_GPR_PERSISTENT_ENTRY0_MASK (0xFFFFFFFFU) -#define SRC_GPR_PERSISTENT_ENTRY0_SHIFT (0U) -#define SRC_GPR_PERSISTENT_ENTRY0(x) (((uint32_t)(((uint32_t)(x)) << SRC_GPR_PERSISTENT_ENTRY0_SHIFT)) & SRC_GPR_PERSISTENT_ENTRY0_MASK) +/*! @{ */ #define SRC_GPR_PERSISTENT_ARG0_MASK (0xFFFFFFFFU) #define SRC_GPR_PERSISTENT_ARG0_SHIFT (0U) #define SRC_GPR_PERSISTENT_ARG0(x) (((uint32_t)(((uint32_t)(x)) << SRC_GPR_PERSISTENT_ARG0_SHIFT)) & SRC_GPR_PERSISTENT_ARG0_MASK) +#define SRC_GPR_PERSISTENT_ENTRY0_MASK (0xFFFFFFFFU) +#define SRC_GPR_PERSISTENT_ENTRY0_SHIFT (0U) +#define SRC_GPR_PERSISTENT_ENTRY0(x) (((uint32_t)(((uint32_t)(x)) << SRC_GPR_PERSISTENT_ENTRY0_SHIFT)) & SRC_GPR_PERSISTENT_ENTRY0_MASK) +/*! @} */ /* The count of SRC_GPR */ #define SRC_GPR_COUNT (10U) @@ -18557,14 +30250,27 @@ typedef struct { */ /*! @name TEMPSENSE0 - Tempsensor Control Register 0 */ +/*! @{ */ #define TEMPMON_TEMPSENSE0_POWER_DOWN_MASK (0x1U) #define TEMPMON_TEMPSENSE0_POWER_DOWN_SHIFT (0U) +/*! POWER_DOWN + * 0b0..Enable power to the temperature sensor. + * 0b1..Power down the temperature sensor. + */ #define TEMPMON_TEMPSENSE0_POWER_DOWN(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_POWER_DOWN_SHIFT)) & TEMPMON_TEMPSENSE0_POWER_DOWN_MASK) #define TEMPMON_TEMPSENSE0_MEASURE_TEMP_MASK (0x2U) #define TEMPMON_TEMPSENSE0_MEASURE_TEMP_SHIFT (1U) +/*! MEASURE_TEMP + * 0b0..Do not start the measurement process. + * 0b1..Start the measurement process. + */ #define TEMPMON_TEMPSENSE0_MEASURE_TEMP(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_MEASURE_TEMP_SHIFT)) & TEMPMON_TEMPSENSE0_MEASURE_TEMP_MASK) #define TEMPMON_TEMPSENSE0_FINISHED_MASK (0x4U) #define TEMPMON_TEMPSENSE0_FINISHED_SHIFT (2U) +/*! FINISHED + * 0b0..Last measurement is not ready yet. + * 0b1..Last measurement is valid. + */ #define TEMPMON_TEMPSENSE0_FINISHED(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_FINISHED_SHIFT)) & TEMPMON_TEMPSENSE0_FINISHED_MASK) #define TEMPMON_TEMPSENSE0_TEMP_CNT_MASK (0xFFF00U) #define TEMPMON_TEMPSENSE0_TEMP_CNT_SHIFT (8U) @@ -18572,16 +30278,30 @@ typedef struct { #define TEMPMON_TEMPSENSE0_ALARM_VALUE_MASK (0xFFF00000U) #define TEMPMON_TEMPSENSE0_ALARM_VALUE_SHIFT (20U) #define TEMPMON_TEMPSENSE0_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE0_ALARM_VALUE_MASK) +/*! @} */ /*! @name TEMPSENSE0_SET - Tempsensor Control Register 0 */ +/*! @{ */ #define TEMPMON_TEMPSENSE0_SET_POWER_DOWN_MASK (0x1U) #define TEMPMON_TEMPSENSE0_SET_POWER_DOWN_SHIFT (0U) +/*! POWER_DOWN + * 0b0..Enable power to the temperature sensor. + * 0b1..Power down the temperature sensor. + */ #define TEMPMON_TEMPSENSE0_SET_POWER_DOWN(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_SET_POWER_DOWN_SHIFT)) & TEMPMON_TEMPSENSE0_SET_POWER_DOWN_MASK) #define TEMPMON_TEMPSENSE0_SET_MEASURE_TEMP_MASK (0x2U) #define TEMPMON_TEMPSENSE0_SET_MEASURE_TEMP_SHIFT (1U) +/*! MEASURE_TEMP + * 0b0..Do not start the measurement process. + * 0b1..Start the measurement process. + */ #define TEMPMON_TEMPSENSE0_SET_MEASURE_TEMP(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_SET_MEASURE_TEMP_SHIFT)) & TEMPMON_TEMPSENSE0_SET_MEASURE_TEMP_MASK) #define TEMPMON_TEMPSENSE0_SET_FINISHED_MASK (0x4U) #define TEMPMON_TEMPSENSE0_SET_FINISHED_SHIFT (2U) +/*! FINISHED + * 0b0..Last measurement is not ready yet. + * 0b1..Last measurement is valid. + */ #define TEMPMON_TEMPSENSE0_SET_FINISHED(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_SET_FINISHED_SHIFT)) & TEMPMON_TEMPSENSE0_SET_FINISHED_MASK) #define TEMPMON_TEMPSENSE0_SET_TEMP_CNT_MASK (0xFFF00U) #define TEMPMON_TEMPSENSE0_SET_TEMP_CNT_SHIFT (8U) @@ -18589,16 +30309,30 @@ typedef struct { #define TEMPMON_TEMPSENSE0_SET_ALARM_VALUE_MASK (0xFFF00000U) #define TEMPMON_TEMPSENSE0_SET_ALARM_VALUE_SHIFT (20U) #define TEMPMON_TEMPSENSE0_SET_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_SET_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE0_SET_ALARM_VALUE_MASK) +/*! @} */ /*! @name TEMPSENSE0_CLR - Tempsensor Control Register 0 */ +/*! @{ */ #define TEMPMON_TEMPSENSE0_CLR_POWER_DOWN_MASK (0x1U) #define TEMPMON_TEMPSENSE0_CLR_POWER_DOWN_SHIFT (0U) +/*! POWER_DOWN + * 0b0..Enable power to the temperature sensor. + * 0b1..Power down the temperature sensor. + */ #define TEMPMON_TEMPSENSE0_CLR_POWER_DOWN(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_CLR_POWER_DOWN_SHIFT)) & TEMPMON_TEMPSENSE0_CLR_POWER_DOWN_MASK) #define TEMPMON_TEMPSENSE0_CLR_MEASURE_TEMP_MASK (0x2U) #define TEMPMON_TEMPSENSE0_CLR_MEASURE_TEMP_SHIFT (1U) +/*! MEASURE_TEMP + * 0b0..Do not start the measurement process. + * 0b1..Start the measurement process. + */ #define TEMPMON_TEMPSENSE0_CLR_MEASURE_TEMP(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_CLR_MEASURE_TEMP_SHIFT)) & TEMPMON_TEMPSENSE0_CLR_MEASURE_TEMP_MASK) #define TEMPMON_TEMPSENSE0_CLR_FINISHED_MASK (0x4U) #define TEMPMON_TEMPSENSE0_CLR_FINISHED_SHIFT (2U) +/*! FINISHED + * 0b0..Last measurement is not ready yet. + * 0b1..Last measurement is valid. + */ #define TEMPMON_TEMPSENSE0_CLR_FINISHED(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_CLR_FINISHED_SHIFT)) & TEMPMON_TEMPSENSE0_CLR_FINISHED_MASK) #define TEMPMON_TEMPSENSE0_CLR_TEMP_CNT_MASK (0xFFF00U) #define TEMPMON_TEMPSENSE0_CLR_TEMP_CNT_SHIFT (8U) @@ -18606,16 +30340,30 @@ typedef struct { #define TEMPMON_TEMPSENSE0_CLR_ALARM_VALUE_MASK (0xFFF00000U) #define TEMPMON_TEMPSENSE0_CLR_ALARM_VALUE_SHIFT (20U) #define TEMPMON_TEMPSENSE0_CLR_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_CLR_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE0_CLR_ALARM_VALUE_MASK) +/*! @} */ /*! @name TEMPSENSE0_TOG - Tempsensor Control Register 0 */ +/*! @{ */ #define TEMPMON_TEMPSENSE0_TOG_POWER_DOWN_MASK (0x1U) #define TEMPMON_TEMPSENSE0_TOG_POWER_DOWN_SHIFT (0U) +/*! POWER_DOWN + * 0b0..Enable power to the temperature sensor. + * 0b1..Power down the temperature sensor. + */ #define TEMPMON_TEMPSENSE0_TOG_POWER_DOWN(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_TOG_POWER_DOWN_SHIFT)) & TEMPMON_TEMPSENSE0_TOG_POWER_DOWN_MASK) #define TEMPMON_TEMPSENSE0_TOG_MEASURE_TEMP_MASK (0x2U) #define TEMPMON_TEMPSENSE0_TOG_MEASURE_TEMP_SHIFT (1U) +/*! MEASURE_TEMP + * 0b0..Do not start the measurement process. + * 0b1..Start the measurement process. + */ #define TEMPMON_TEMPSENSE0_TOG_MEASURE_TEMP(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_TOG_MEASURE_TEMP_SHIFT)) & TEMPMON_TEMPSENSE0_TOG_MEASURE_TEMP_MASK) #define TEMPMON_TEMPSENSE0_TOG_FINISHED_MASK (0x4U) #define TEMPMON_TEMPSENSE0_TOG_FINISHED_SHIFT (2U) +/*! FINISHED + * 0b0..Last measurement is not ready yet. + * 0b1..Last measurement is valid. + */ #define TEMPMON_TEMPSENSE0_TOG_FINISHED(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_TOG_FINISHED_SHIFT)) & TEMPMON_TEMPSENSE0_TOG_FINISHED_MASK) #define TEMPMON_TEMPSENSE0_TOG_TEMP_CNT_MASK (0xFFF00U) #define TEMPMON_TEMPSENSE0_TOG_TEMP_CNT_SHIFT (8U) @@ -18623,58 +30371,75 @@ typedef struct { #define TEMPMON_TEMPSENSE0_TOG_ALARM_VALUE_MASK (0xFFF00000U) #define TEMPMON_TEMPSENSE0_TOG_ALARM_VALUE_SHIFT (20U) #define TEMPMON_TEMPSENSE0_TOG_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_TOG_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE0_TOG_ALARM_VALUE_MASK) +/*! @} */ /*! @name TEMPSENSE1 - Tempsensor Control Register 1 */ +/*! @{ */ #define TEMPMON_TEMPSENSE1_MEASURE_FREQ_MASK (0xFFFFU) #define TEMPMON_TEMPSENSE1_MEASURE_FREQ_SHIFT (0U) #define TEMPMON_TEMPSENSE1_MEASURE_FREQ(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE1_MEASURE_FREQ_SHIFT)) & TEMPMON_TEMPSENSE1_MEASURE_FREQ_MASK) +/*! @} */ /*! @name TEMPSENSE1_SET - Tempsensor Control Register 1 */ +/*! @{ */ #define TEMPMON_TEMPSENSE1_SET_MEASURE_FREQ_MASK (0xFFFFU) #define TEMPMON_TEMPSENSE1_SET_MEASURE_FREQ_SHIFT (0U) #define TEMPMON_TEMPSENSE1_SET_MEASURE_FREQ(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE1_SET_MEASURE_FREQ_SHIFT)) & TEMPMON_TEMPSENSE1_SET_MEASURE_FREQ_MASK) +/*! @} */ /*! @name TEMPSENSE1_CLR - Tempsensor Control Register 1 */ +/*! @{ */ #define TEMPMON_TEMPSENSE1_CLR_MEASURE_FREQ_MASK (0xFFFFU) #define TEMPMON_TEMPSENSE1_CLR_MEASURE_FREQ_SHIFT (0U) #define TEMPMON_TEMPSENSE1_CLR_MEASURE_FREQ(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE1_CLR_MEASURE_FREQ_SHIFT)) & TEMPMON_TEMPSENSE1_CLR_MEASURE_FREQ_MASK) +/*! @} */ /*! @name TEMPSENSE1_TOG - Tempsensor Control Register 1 */ +/*! @{ */ #define TEMPMON_TEMPSENSE1_TOG_MEASURE_FREQ_MASK (0xFFFFU) #define TEMPMON_TEMPSENSE1_TOG_MEASURE_FREQ_SHIFT (0U) #define TEMPMON_TEMPSENSE1_TOG_MEASURE_FREQ(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE1_TOG_MEASURE_FREQ_SHIFT)) & TEMPMON_TEMPSENSE1_TOG_MEASURE_FREQ_MASK) +/*! @} */ /*! @name TEMPSENSE2 - Tempsensor Control Register 2 */ +/*! @{ */ #define TEMPMON_TEMPSENSE2_LOW_ALARM_VALUE_MASK (0xFFFU) #define TEMPMON_TEMPSENSE2_LOW_ALARM_VALUE_SHIFT (0U) #define TEMPMON_TEMPSENSE2_LOW_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE2_LOW_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE2_LOW_ALARM_VALUE_MASK) #define TEMPMON_TEMPSENSE2_PANIC_ALARM_VALUE_MASK (0xFFF0000U) #define TEMPMON_TEMPSENSE2_PANIC_ALARM_VALUE_SHIFT (16U) #define TEMPMON_TEMPSENSE2_PANIC_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE2_PANIC_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE2_PANIC_ALARM_VALUE_MASK) +/*! @} */ /*! @name TEMPSENSE2_SET - Tempsensor Control Register 2 */ +/*! @{ */ #define TEMPMON_TEMPSENSE2_SET_LOW_ALARM_VALUE_MASK (0xFFFU) #define TEMPMON_TEMPSENSE2_SET_LOW_ALARM_VALUE_SHIFT (0U) #define TEMPMON_TEMPSENSE2_SET_LOW_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE2_SET_LOW_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE2_SET_LOW_ALARM_VALUE_MASK) #define TEMPMON_TEMPSENSE2_SET_PANIC_ALARM_VALUE_MASK (0xFFF0000U) #define TEMPMON_TEMPSENSE2_SET_PANIC_ALARM_VALUE_SHIFT (16U) #define TEMPMON_TEMPSENSE2_SET_PANIC_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE2_SET_PANIC_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE2_SET_PANIC_ALARM_VALUE_MASK) +/*! @} */ /*! @name TEMPSENSE2_CLR - Tempsensor Control Register 2 */ +/*! @{ */ #define TEMPMON_TEMPSENSE2_CLR_LOW_ALARM_VALUE_MASK (0xFFFU) #define TEMPMON_TEMPSENSE2_CLR_LOW_ALARM_VALUE_SHIFT (0U) #define TEMPMON_TEMPSENSE2_CLR_LOW_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE2_CLR_LOW_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE2_CLR_LOW_ALARM_VALUE_MASK) #define TEMPMON_TEMPSENSE2_CLR_PANIC_ALARM_VALUE_MASK (0xFFF0000U) #define TEMPMON_TEMPSENSE2_CLR_PANIC_ALARM_VALUE_SHIFT (16U) #define TEMPMON_TEMPSENSE2_CLR_PANIC_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE2_CLR_PANIC_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE2_CLR_PANIC_ALARM_VALUE_MASK) +/*! @} */ /*! @name TEMPSENSE2_TOG - Tempsensor Control Register 2 */ +/*! @{ */ #define TEMPMON_TEMPSENSE2_TOG_LOW_ALARM_VALUE_MASK (0xFFFU) #define TEMPMON_TEMPSENSE2_TOG_LOW_ALARM_VALUE_SHIFT (0U) #define TEMPMON_TEMPSENSE2_TOG_LOW_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE2_TOG_LOW_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE2_TOG_LOW_ALARM_VALUE_MASK) #define TEMPMON_TEMPSENSE2_TOG_PANIC_ALARM_VALUE_MASK (0xFFF0000U) #define TEMPMON_TEMPSENSE2_TOG_PANIC_ALARM_VALUE_SHIFT (16U) #define TEMPMON_TEMPSENSE2_TOG_PANIC_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE2_TOG_PANIC_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE2_TOG_PANIC_ALARM_VALUE_MASK) +/*! @} */ /*! @@ -18737,88 +30502,171 @@ typedef struct { */ /*! @name COMP1 - Timer Channel Compare Register 1 */ +/*! @{ */ #define TMR_COMP1_COMPARISON_1_MASK (0xFFFFU) #define TMR_COMP1_COMPARISON_1_SHIFT (0U) #define TMR_COMP1_COMPARISON_1(x) (((uint16_t)(((uint16_t)(x)) << TMR_COMP1_COMPARISON_1_SHIFT)) & TMR_COMP1_COMPARISON_1_MASK) +/*! @} */ /* The count of TMR_COMP1 */ #define TMR_COMP1_COUNT (4U) /*! @name COMP2 - Timer Channel Compare Register 2 */ +/*! @{ */ #define TMR_COMP2_COMPARISON_2_MASK (0xFFFFU) #define TMR_COMP2_COMPARISON_2_SHIFT (0U) #define TMR_COMP2_COMPARISON_2(x) (((uint16_t)(((uint16_t)(x)) << TMR_COMP2_COMPARISON_2_SHIFT)) & TMR_COMP2_COMPARISON_2_MASK) +/*! @} */ /* The count of TMR_COMP2 */ #define TMR_COMP2_COUNT (4U) /*! @name CAPT - Timer Channel Capture Register */ +/*! @{ */ #define TMR_CAPT_CAPTURE_MASK (0xFFFFU) #define TMR_CAPT_CAPTURE_SHIFT (0U) #define TMR_CAPT_CAPTURE(x) (((uint16_t)(((uint16_t)(x)) << TMR_CAPT_CAPTURE_SHIFT)) & TMR_CAPT_CAPTURE_MASK) +/*! @} */ /* The count of TMR_CAPT */ #define TMR_CAPT_COUNT (4U) /*! @name LOAD - Timer Channel Load Register */ +/*! @{ */ #define TMR_LOAD_LOAD_MASK (0xFFFFU) #define TMR_LOAD_LOAD_SHIFT (0U) #define TMR_LOAD_LOAD(x) (((uint16_t)(((uint16_t)(x)) << TMR_LOAD_LOAD_SHIFT)) & TMR_LOAD_LOAD_MASK) +/*! @} */ /* The count of TMR_LOAD */ #define TMR_LOAD_COUNT (4U) /*! @name HOLD - Timer Channel Hold Register */ +/*! @{ */ #define TMR_HOLD_HOLD_MASK (0xFFFFU) #define TMR_HOLD_HOLD_SHIFT (0U) #define TMR_HOLD_HOLD(x) (((uint16_t)(((uint16_t)(x)) << TMR_HOLD_HOLD_SHIFT)) & TMR_HOLD_HOLD_MASK) +/*! @} */ /* The count of TMR_HOLD */ #define TMR_HOLD_COUNT (4U) /*! @name CNTR - Timer Channel Counter Register */ +/*! @{ */ #define TMR_CNTR_COUNTER_MASK (0xFFFFU) #define TMR_CNTR_COUNTER_SHIFT (0U) #define TMR_CNTR_COUNTER(x) (((uint16_t)(((uint16_t)(x)) << TMR_CNTR_COUNTER_SHIFT)) & TMR_CNTR_COUNTER_MASK) +/*! @} */ /* The count of TMR_CNTR */ #define TMR_CNTR_COUNT (4U) /*! @name CTRL - Timer Channel Control Register */ +/*! @{ */ #define TMR_CTRL_OUTMODE_MASK (0x7U) #define TMR_CTRL_OUTMODE_SHIFT (0U) +/*! OUTMODE - Output Mode + * 0b000..Asserted while counter is active + * 0b001..Clear OFLAG output on successful compare + * 0b010..Set OFLAG output on successful compare + * 0b011..Toggle OFLAG output on successful compare + * 0b100..Toggle OFLAG output using alternating compare registers + * 0b101..Set on compare, cleared on secondary source input edge + * 0b110..Set on compare, cleared on counter rollover + * 0b111..Enable gated clock output while counter is active + */ #define TMR_CTRL_OUTMODE(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_OUTMODE_SHIFT)) & TMR_CTRL_OUTMODE_MASK) #define TMR_CTRL_COINIT_MASK (0x8U) #define TMR_CTRL_COINIT_SHIFT (3U) +/*! COINIT - Co-Channel Initialization + * 0b0..Co-channel counter/timers cannot force a re-initialization of this counter/timer + * 0b1..Co-channel counter/timers may force a re-initialization of this counter/timer + */ #define TMR_CTRL_COINIT(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_COINIT_SHIFT)) & TMR_CTRL_COINIT_MASK) #define TMR_CTRL_DIR_MASK (0x10U) #define TMR_CTRL_DIR_SHIFT (4U) +/*! DIR - Count Direction + * 0b0..Count up. + * 0b1..Count down. + */ #define TMR_CTRL_DIR(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_DIR_SHIFT)) & TMR_CTRL_DIR_MASK) #define TMR_CTRL_LENGTH_MASK (0x20U) #define TMR_CTRL_LENGTH_SHIFT (5U) +/*! LENGTH - Count Length + * 0b0..Count until roll over at $FFFF and continue from $0000. + * 0b1..Count until compare, then re-initialize. If counting up, a successful compare occurs when the counter reaches a COMP1 value. If counting down, a successful compare occurs when the counter reaches a COMP2 value. When output mode $4 is used, alternating values of COMP1 and COMP2 are used to generate successful comparisons. For example, the counter counts until a COMP1 value is reached, re-initializes, counts until COMP2 value is reached, re-initializes, counts until COMP1 value is reached, and so on. + */ #define TMR_CTRL_LENGTH(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_LENGTH_SHIFT)) & TMR_CTRL_LENGTH_MASK) #define TMR_CTRL_ONCE_MASK (0x40U) #define TMR_CTRL_ONCE_SHIFT (6U) +/*! ONCE - Count Once + * 0b0..Count repeatedly. + * 0b1..Count until compare and then stop. If counting up, a successful compare occurs when the counter reaches a COMP1 value. If counting down, a successful compare occurs when the counter reaches a COMP2 value. When output mode $4 is used, the counter re-initializes after reaching the COMP1 value, continues to count to the COMP2 value, and then stops. + */ #define TMR_CTRL_ONCE(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_ONCE_SHIFT)) & TMR_CTRL_ONCE_MASK) #define TMR_CTRL_SCS_MASK (0x180U) #define TMR_CTRL_SCS_SHIFT (7U) +/*! SCS - Secondary Count Source + * 0b00..Counter 0 input pin + * 0b01..Counter 1 input pin + * 0b10..Counter 2 input pin + * 0b11..Counter 3 input pin + */ #define TMR_CTRL_SCS(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_SCS_SHIFT)) & TMR_CTRL_SCS_MASK) #define TMR_CTRL_PCS_MASK (0x1E00U) #define TMR_CTRL_PCS_SHIFT (9U) +/*! PCS - Primary Count Source + * 0b0000..Counter 0 input pin + * 0b0001..Counter 1 input pin + * 0b0010..Counter 2 input pin + * 0b0011..Counter 3 input pin + * 0b0100..Counter 0 output + * 0b0101..Counter 1 output + * 0b0110..Counter 2 output + * 0b0111..Counter 3 output + * 0b1000..IP bus clock divide by 1 prescaler + * 0b1001..IP bus clock divide by 2 prescaler + * 0b1010..IP bus clock divide by 4 prescaler + * 0b1011..IP bus clock divide by 8 prescaler + * 0b1100..IP bus clock divide by 16 prescaler + * 0b1101..IP bus clock divide by 32 prescaler + * 0b1110..IP bus clock divide by 64 prescaler + * 0b1111..IP bus clock divide by 128 prescaler + */ #define TMR_CTRL_PCS(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_PCS_SHIFT)) & TMR_CTRL_PCS_MASK) #define TMR_CTRL_CM_MASK (0xE000U) #define TMR_CTRL_CM_SHIFT (13U) +/*! CM - Count Mode + * 0b000..No operation + * 0b001..Count rising edges of primary sourceRising edges are counted only when SCTRL[IPS] = 0. Falling edges are counted when SCTRL[IPS] = 1. If the primary count source is IP bus clock divide by 1, only rising edges are counted regardless of the value of SCTRL[IPS]. + * 0b010..Count rising and falling edges of primary sourceIP bus clock divide by 1 cannot be used as a primary count source in edge count mode. + * 0b011..Count rising edges of primary source while secondary input high active + * 0b100..Quadrature count mode, uses primary and secondary sources + * 0b101..Count rising edges of primary source; secondary source specifies directionRising edges are counted only when SCTRL[IPS] = 0. Falling edges are counted when SCTRL[IPS] = 1. + * 0b110..Edge of secondary source triggers primary count until compare + * 0b111..Cascaded counter mode (up/down)The primary count source must be set to one of the counter outputs. + */ #define TMR_CTRL_CM(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_CM_SHIFT)) & TMR_CTRL_CM_MASK) +/*! @} */ /* The count of TMR_CTRL */ #define TMR_CTRL_COUNT (4U) /*! @name SCTRL - Timer Channel Status and Control Register */ +/*! @{ */ #define TMR_SCTRL_OEN_MASK (0x1U) #define TMR_SCTRL_OEN_SHIFT (0U) +/*! OEN - Output Enable + * 0b0..The external pin is configured as an input. + * 0b1..The OFLAG output signal is driven on the external pin. Other timer groups using this external pin as their input see the driven value. The polarity of the signal is determined by OPS. + */ #define TMR_SCTRL_OEN(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_OEN_SHIFT)) & TMR_SCTRL_OEN_MASK) #define TMR_SCTRL_OPS_MASK (0x2U) #define TMR_SCTRL_OPS_SHIFT (1U) +/*! OPS - Output Polarity Select + * 0b0..True polarity. + * 0b1..Inverted polarity. + */ #define TMR_SCTRL_OPS(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_OPS_SHIFT)) & TMR_SCTRL_OPS_MASK) #define TMR_SCTRL_FORCE_MASK (0x4U) #define TMR_SCTRL_FORCE_SHIFT (2U) @@ -18834,6 +30682,12 @@ typedef struct { #define TMR_SCTRL_MSTR(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_MSTR_SHIFT)) & TMR_SCTRL_MSTR_MASK) #define TMR_SCTRL_CAPTURE_MODE_MASK (0xC0U) #define TMR_SCTRL_CAPTURE_MODE_SHIFT (6U) +/*! CAPTURE_MODE - Input Capture Mode + * 0b00..Capture function is disabled + * 0b01..Load capture register on rising edge (when IPS=0) or falling edge (when IPS=1) of input + * 0b10..Load capture register on falling edge (when IPS=0) or rising edge (when IPS=1) of input + * 0b11..Load capture register on both edges of input + */ #define TMR_SCTRL_CAPTURE_MODE(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_CAPTURE_MODE_SHIFT)) & TMR_SCTRL_CAPTURE_MODE_MASK) #define TMR_SCTRL_INPUT_MASK (0x100U) #define TMR_SCTRL_INPUT_SHIFT (8U) @@ -18859,32 +30713,50 @@ typedef struct { #define TMR_SCTRL_TCF_MASK (0x8000U) #define TMR_SCTRL_TCF_SHIFT (15U) #define TMR_SCTRL_TCF(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_TCF_SHIFT)) & TMR_SCTRL_TCF_MASK) +/*! @} */ /* The count of TMR_SCTRL */ #define TMR_SCTRL_COUNT (4U) /*! @name CMPLD1 - Timer Channel Comparator Load Register 1 */ +/*! @{ */ #define TMR_CMPLD1_COMPARATOR_LOAD_1_MASK (0xFFFFU) #define TMR_CMPLD1_COMPARATOR_LOAD_1_SHIFT (0U) #define TMR_CMPLD1_COMPARATOR_LOAD_1(x) (((uint16_t)(((uint16_t)(x)) << TMR_CMPLD1_COMPARATOR_LOAD_1_SHIFT)) & TMR_CMPLD1_COMPARATOR_LOAD_1_MASK) +/*! @} */ /* The count of TMR_CMPLD1 */ #define TMR_CMPLD1_COUNT (4U) /*! @name CMPLD2 - Timer Channel Comparator Load Register 2 */ +/*! @{ */ #define TMR_CMPLD2_COMPARATOR_LOAD_2_MASK (0xFFFFU) #define TMR_CMPLD2_COMPARATOR_LOAD_2_SHIFT (0U) #define TMR_CMPLD2_COMPARATOR_LOAD_2(x) (((uint16_t)(((uint16_t)(x)) << TMR_CMPLD2_COMPARATOR_LOAD_2_SHIFT)) & TMR_CMPLD2_COMPARATOR_LOAD_2_MASK) +/*! @} */ /* The count of TMR_CMPLD2 */ #define TMR_CMPLD2_COUNT (4U) /*! @name CSCTRL - Timer Channel Comparator Status and Control Register */ +/*! @{ */ #define TMR_CSCTRL_CL1_MASK (0x3U) #define TMR_CSCTRL_CL1_SHIFT (0U) +/*! CL1 - Compare Load Control 1 + * 0b00..Never preload + * 0b01..Load upon successful compare with the value in COMP1 + * 0b10..Load upon successful compare with the value in COMP2 + * 0b11..Reserved + */ #define TMR_CSCTRL_CL1(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_CL1_SHIFT)) & TMR_CSCTRL_CL1_MASK) #define TMR_CSCTRL_CL2_MASK (0xCU) #define TMR_CSCTRL_CL2_SHIFT (2U) +/*! CL2 - Compare Load Control 2 + * 0b00..Never preload + * 0b01..Load upon successful compare with the value in COMP1 + * 0b10..Load upon successful compare with the value in COMP2 + * 0b11..Reserved + */ #define TMR_CSCTRL_CL2(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_CL2_SHIFT)) & TMR_CSCTRL_CL2_MASK) #define TMR_CSCTRL_TCF1_MASK (0x10U) #define TMR_CSCTRL_TCF1_SHIFT (4U) @@ -18900,38 +30772,68 @@ typedef struct { #define TMR_CSCTRL_TCF2EN(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_TCF2EN_SHIFT)) & TMR_CSCTRL_TCF2EN_MASK) #define TMR_CSCTRL_UP_MASK (0x200U) #define TMR_CSCTRL_UP_SHIFT (9U) +/*! UP - Counting Direction Indicator + * 0b0..The last count was in the DOWN direction. + * 0b1..The last count was in the UP direction. + */ #define TMR_CSCTRL_UP(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_UP_SHIFT)) & TMR_CSCTRL_UP_MASK) #define TMR_CSCTRL_TCI_MASK (0x400U) #define TMR_CSCTRL_TCI_SHIFT (10U) +/*! TCI - Triggered Count Initialization Control + * 0b0..Stop counter upon receiving a second trigger event while still counting from the first trigger event. + * 0b1..Reload the counter upon receiving a second trigger event while still counting from the first trigger event. + */ #define TMR_CSCTRL_TCI(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_TCI_SHIFT)) & TMR_CSCTRL_TCI_MASK) #define TMR_CSCTRL_ROC_MASK (0x800U) #define TMR_CSCTRL_ROC_SHIFT (11U) +/*! ROC - Reload on Capture + * 0b0..Do not reload the counter on a capture event. + * 0b1..Reload the counter on a capture event. + */ #define TMR_CSCTRL_ROC(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_ROC_SHIFT)) & TMR_CSCTRL_ROC_MASK) #define TMR_CSCTRL_ALT_LOAD_MASK (0x1000U) #define TMR_CSCTRL_ALT_LOAD_SHIFT (12U) +/*! ALT_LOAD - Alternative Load Enable + * 0b0..Counter can be re-initialized only with the LOAD register. + * 0b1..Counter can be re-initialized with the LOAD or CMPLD2 registers depending on count direction. + */ #define TMR_CSCTRL_ALT_LOAD(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_ALT_LOAD_SHIFT)) & TMR_CSCTRL_ALT_LOAD_MASK) #define TMR_CSCTRL_FAULT_MASK (0x2000U) #define TMR_CSCTRL_FAULT_SHIFT (13U) +/*! FAULT - Fault Enable + * 0b0..Fault function disabled. + * 0b1..Fault function enabled. + */ #define TMR_CSCTRL_FAULT(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_FAULT_SHIFT)) & TMR_CSCTRL_FAULT_MASK) #define TMR_CSCTRL_DBG_EN_MASK (0xC000U) #define TMR_CSCTRL_DBG_EN_SHIFT (14U) +/*! DBG_EN - Debug Actions Enable + * 0b00..Continue with normal operation during debug mode. (default) + * 0b01..Halt TMR counter during debug mode. + * 0b10..Force TMR output to logic 0 (prior to consideration of SCTRL[OPS]). + * 0b11..Both halt counter and force output to 0 during debug mode. + */ #define TMR_CSCTRL_DBG_EN(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_DBG_EN_SHIFT)) & TMR_CSCTRL_DBG_EN_MASK) +/*! @} */ /* The count of TMR_CSCTRL */ #define TMR_CSCTRL_COUNT (4U) /*! @name FILT - Timer Channel Input Filter Register */ +/*! @{ */ #define TMR_FILT_FILT_PER_MASK (0xFFU) #define TMR_FILT_FILT_PER_SHIFT (0U) #define TMR_FILT_FILT_PER(x) (((uint16_t)(((uint16_t)(x)) << TMR_FILT_FILT_PER_SHIFT)) & TMR_FILT_FILT_PER_MASK) #define TMR_FILT_FILT_CNT_MASK (0x700U) #define TMR_FILT_FILT_CNT_SHIFT (8U) #define TMR_FILT_FILT_CNT(x) (((uint16_t)(((uint16_t)(x)) << TMR_FILT_FILT_CNT_SHIFT)) & TMR_FILT_FILT_CNT_MASK) +/*! @} */ /* The count of TMR_FILT */ #define TMR_FILT_COUNT (4U) /*! @name DMA - Timer Channel DMA Enable Register */ +/*! @{ */ #define TMR_DMA_IEFDE_MASK (0x1U) #define TMR_DMA_IEFDE_SHIFT (0U) #define TMR_DMA_IEFDE(x) (((uint16_t)(((uint16_t)(x)) << TMR_DMA_IEFDE_SHIFT)) & TMR_DMA_IEFDE_MASK) @@ -18941,14 +30843,21 @@ typedef struct { #define TMR_DMA_CMPLD2DE_MASK (0x4U) #define TMR_DMA_CMPLD2DE_SHIFT (2U) #define TMR_DMA_CMPLD2DE(x) (((uint16_t)(((uint16_t)(x)) << TMR_DMA_CMPLD2DE_SHIFT)) & TMR_DMA_CMPLD2DE_MASK) +/*! @} */ /* The count of TMR_DMA */ #define TMR_DMA_COUNT (4U) /*! @name ENBL - Timer Channel Enable Register */ +/*! @{ */ #define TMR_ENBL_ENBL_MASK (0xFU) #define TMR_ENBL_ENBL_SHIFT (0U) +/*! ENBL - Timer Channel Enable + * 0b0000..Timer channel is disabled. + * 0b0001..Timer channel is enabled. (default) + */ #define TMR_ENBL_ENBL(x) (((uint16_t)(((uint16_t)(x)) << TMR_ENBL_ENBL_SHIFT)) & TMR_ENBL_ENBL_MASK) +/*! @} */ /* The count of TMR_ENBL */ #define TMR_ENBL_COUNT (4U) @@ -19073,11 +30982,24 @@ typedef struct { */ /*! @name MCTL - Miscellaneous Control Register */ +/*! @{ */ #define TRNG_MCTL_SAMP_MODE_MASK (0x3U) #define TRNG_MCTL_SAMP_MODE_SHIFT (0U) +/*! SAMP_MODE + * 0b00..use Von Neumann data into both Entropy shifter and Statistical Checker + * 0b01..use raw data into both Entropy shifter and Statistical Checker + * 0b10..use Von Neumann data into Entropy shifter. Use raw data into Statistical Checker + * 0b11..undefined/reserved. + */ #define TRNG_MCTL_SAMP_MODE(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_SAMP_MODE_SHIFT)) & TRNG_MCTL_SAMP_MODE_MASK) #define TRNG_MCTL_OSC_DIV_MASK (0xCU) #define TRNG_MCTL_OSC_DIV_SHIFT (2U) +/*! OSC_DIV + * 0b00..use ring oscillator with no divide + * 0b01..use ring oscillator divided-by-2 + * 0b10..use ring oscillator divided-by-4 + * 0b11..use ring oscillator divided-by-8 + */ #define TRNG_MCTL_OSC_DIV(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_OSC_DIV_SHIFT)) & TRNG_MCTL_OSC_DIV_MASK) #define TRNG_MCTL_UNUSED4_MASK (0x10U) #define TRNG_MCTL_UNUSED4_SHIFT (4U) @@ -19115,173 +31037,223 @@ typedef struct { #define TRNG_MCTL_PRGM_MASK (0x10000U) #define TRNG_MCTL_PRGM_SHIFT (16U) #define TRNG_MCTL_PRGM(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_PRGM_SHIFT)) & TRNG_MCTL_PRGM_MASK) +/*! @} */ /*! @name SCMISC - Statistical Check Miscellaneous Register */ +/*! @{ */ #define TRNG_SCMISC_LRUN_MAX_MASK (0xFFU) #define TRNG_SCMISC_LRUN_MAX_SHIFT (0U) #define TRNG_SCMISC_LRUN_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCMISC_LRUN_MAX_SHIFT)) & TRNG_SCMISC_LRUN_MAX_MASK) #define TRNG_SCMISC_RTY_CT_MASK (0xF0000U) #define TRNG_SCMISC_RTY_CT_SHIFT (16U) #define TRNG_SCMISC_RTY_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCMISC_RTY_CT_SHIFT)) & TRNG_SCMISC_RTY_CT_MASK) +/*! @} */ /*! @name PKRRNG - Poker Range Register */ +/*! @{ */ #define TRNG_PKRRNG_PKR_RNG_MASK (0xFFFFU) #define TRNG_PKRRNG_PKR_RNG_SHIFT (0U) #define TRNG_PKRRNG_PKR_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRRNG_PKR_RNG_SHIFT)) & TRNG_PKRRNG_PKR_RNG_MASK) +/*! @} */ /*! @name PKRMAX - Poker Maximum Limit Register */ +/*! @{ */ #define TRNG_PKRMAX_PKR_MAX_MASK (0xFFFFFFU) #define TRNG_PKRMAX_PKR_MAX_SHIFT (0U) #define TRNG_PKRMAX_PKR_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRMAX_PKR_MAX_SHIFT)) & TRNG_PKRMAX_PKR_MAX_MASK) +/*! @} */ /*! @name PKRSQ - Poker Square Calculation Result Register */ +/*! @{ */ #define TRNG_PKRSQ_PKR_SQ_MASK (0xFFFFFFU) #define TRNG_PKRSQ_PKR_SQ_SHIFT (0U) #define TRNG_PKRSQ_PKR_SQ(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRSQ_PKR_SQ_SHIFT)) & TRNG_PKRSQ_PKR_SQ_MASK) +/*! @} */ /*! @name SDCTL - Seed Control Register */ +/*! @{ */ #define TRNG_SDCTL_SAMP_SIZE_MASK (0xFFFFU) #define TRNG_SDCTL_SAMP_SIZE_SHIFT (0U) #define TRNG_SDCTL_SAMP_SIZE(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SDCTL_SAMP_SIZE_SHIFT)) & TRNG_SDCTL_SAMP_SIZE_MASK) #define TRNG_SDCTL_ENT_DLY_MASK (0xFFFF0000U) #define TRNG_SDCTL_ENT_DLY_SHIFT (16U) #define TRNG_SDCTL_ENT_DLY(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SDCTL_ENT_DLY_SHIFT)) & TRNG_SDCTL_ENT_DLY_MASK) +/*! @} */ /*! @name SBLIM - Sparse Bit Limit Register */ +/*! @{ */ #define TRNG_SBLIM_SB_LIM_MASK (0x3FFU) #define TRNG_SBLIM_SB_LIM_SHIFT (0U) #define TRNG_SBLIM_SB_LIM(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SBLIM_SB_LIM_SHIFT)) & TRNG_SBLIM_SB_LIM_MASK) +/*! @} */ /*! @name TOTSAM - Total Samples Register */ +/*! @{ */ #define TRNG_TOTSAM_TOT_SAM_MASK (0xFFFFFU) #define TRNG_TOTSAM_TOT_SAM_SHIFT (0U) #define TRNG_TOTSAM_TOT_SAM(x) (((uint32_t)(((uint32_t)(x)) << TRNG_TOTSAM_TOT_SAM_SHIFT)) & TRNG_TOTSAM_TOT_SAM_MASK) +/*! @} */ /*! @name FRQMIN - Frequency Count Minimum Limit Register */ +/*! @{ */ #define TRNG_FRQMIN_FRQ_MIN_MASK (0x3FFFFFU) #define TRNG_FRQMIN_FRQ_MIN_SHIFT (0U) #define TRNG_FRQMIN_FRQ_MIN(x) (((uint32_t)(((uint32_t)(x)) << TRNG_FRQMIN_FRQ_MIN_SHIFT)) & TRNG_FRQMIN_FRQ_MIN_MASK) +/*! @} */ /*! @name FRQCNT - Frequency Count Register */ +/*! @{ */ #define TRNG_FRQCNT_FRQ_CT_MASK (0x3FFFFFU) #define TRNG_FRQCNT_FRQ_CT_SHIFT (0U) #define TRNG_FRQCNT_FRQ_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_FRQCNT_FRQ_CT_SHIFT)) & TRNG_FRQCNT_FRQ_CT_MASK) +/*! @} */ /*! @name FRQMAX - Frequency Count Maximum Limit Register */ +/*! @{ */ #define TRNG_FRQMAX_FRQ_MAX_MASK (0x3FFFFFU) #define TRNG_FRQMAX_FRQ_MAX_SHIFT (0U) #define TRNG_FRQMAX_FRQ_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_FRQMAX_FRQ_MAX_SHIFT)) & TRNG_FRQMAX_FRQ_MAX_MASK) +/*! @} */ /*! @name SCMC - Statistical Check Monobit Count Register */ +/*! @{ */ #define TRNG_SCMC_MONO_CT_MASK (0xFFFFU) #define TRNG_SCMC_MONO_CT_SHIFT (0U) #define TRNG_SCMC_MONO_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCMC_MONO_CT_SHIFT)) & TRNG_SCMC_MONO_CT_MASK) +/*! @} */ /*! @name SCML - Statistical Check Monobit Limit Register */ +/*! @{ */ #define TRNG_SCML_MONO_MAX_MASK (0xFFFFU) #define TRNG_SCML_MONO_MAX_SHIFT (0U) #define TRNG_SCML_MONO_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCML_MONO_MAX_SHIFT)) & TRNG_SCML_MONO_MAX_MASK) #define TRNG_SCML_MONO_RNG_MASK (0xFFFF0000U) #define TRNG_SCML_MONO_RNG_SHIFT (16U) #define TRNG_SCML_MONO_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCML_MONO_RNG_SHIFT)) & TRNG_SCML_MONO_RNG_MASK) +/*! @} */ /*! @name SCR1C - Statistical Check Run Length 1 Count Register */ +/*! @{ */ #define TRNG_SCR1C_R1_0_CT_MASK (0x7FFFU) #define TRNG_SCR1C_R1_0_CT_SHIFT (0U) #define TRNG_SCR1C_R1_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR1C_R1_0_CT_SHIFT)) & TRNG_SCR1C_R1_0_CT_MASK) #define TRNG_SCR1C_R1_1_CT_MASK (0x7FFF0000U) #define TRNG_SCR1C_R1_1_CT_SHIFT (16U) #define TRNG_SCR1C_R1_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR1C_R1_1_CT_SHIFT)) & TRNG_SCR1C_R1_1_CT_MASK) +/*! @} */ /*! @name SCR1L - Statistical Check Run Length 1 Limit Register */ +/*! @{ */ #define TRNG_SCR1L_RUN1_MAX_MASK (0x7FFFU) #define TRNG_SCR1L_RUN1_MAX_SHIFT (0U) #define TRNG_SCR1L_RUN1_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR1L_RUN1_MAX_SHIFT)) & TRNG_SCR1L_RUN1_MAX_MASK) #define TRNG_SCR1L_RUN1_RNG_MASK (0x7FFF0000U) #define TRNG_SCR1L_RUN1_RNG_SHIFT (16U) #define TRNG_SCR1L_RUN1_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR1L_RUN1_RNG_SHIFT)) & TRNG_SCR1L_RUN1_RNG_MASK) +/*! @} */ /*! @name SCR2C - Statistical Check Run Length 2 Count Register */ +/*! @{ */ #define TRNG_SCR2C_R2_0_CT_MASK (0x3FFFU) #define TRNG_SCR2C_R2_0_CT_SHIFT (0U) #define TRNG_SCR2C_R2_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR2C_R2_0_CT_SHIFT)) & TRNG_SCR2C_R2_0_CT_MASK) #define TRNG_SCR2C_R2_1_CT_MASK (0x3FFF0000U) #define TRNG_SCR2C_R2_1_CT_SHIFT (16U) #define TRNG_SCR2C_R2_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR2C_R2_1_CT_SHIFT)) & TRNG_SCR2C_R2_1_CT_MASK) +/*! @} */ /*! @name SCR2L - Statistical Check Run Length 2 Limit Register */ +/*! @{ */ #define TRNG_SCR2L_RUN2_MAX_MASK (0x3FFFU) #define TRNG_SCR2L_RUN2_MAX_SHIFT (0U) #define TRNG_SCR2L_RUN2_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR2L_RUN2_MAX_SHIFT)) & TRNG_SCR2L_RUN2_MAX_MASK) #define TRNG_SCR2L_RUN2_RNG_MASK (0x3FFF0000U) #define TRNG_SCR2L_RUN2_RNG_SHIFT (16U) #define TRNG_SCR2L_RUN2_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR2L_RUN2_RNG_SHIFT)) & TRNG_SCR2L_RUN2_RNG_MASK) +/*! @} */ /*! @name SCR3C - Statistical Check Run Length 3 Count Register */ +/*! @{ */ #define TRNG_SCR3C_R3_0_CT_MASK (0x1FFFU) #define TRNG_SCR3C_R3_0_CT_SHIFT (0U) #define TRNG_SCR3C_R3_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR3C_R3_0_CT_SHIFT)) & TRNG_SCR3C_R3_0_CT_MASK) #define TRNG_SCR3C_R3_1_CT_MASK (0x1FFF0000U) #define TRNG_SCR3C_R3_1_CT_SHIFT (16U) #define TRNG_SCR3C_R3_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR3C_R3_1_CT_SHIFT)) & TRNG_SCR3C_R3_1_CT_MASK) +/*! @} */ /*! @name SCR3L - Statistical Check Run Length 3 Limit Register */ +/*! @{ */ #define TRNG_SCR3L_RUN3_MAX_MASK (0x1FFFU) #define TRNG_SCR3L_RUN3_MAX_SHIFT (0U) #define TRNG_SCR3L_RUN3_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR3L_RUN3_MAX_SHIFT)) & TRNG_SCR3L_RUN3_MAX_MASK) #define TRNG_SCR3L_RUN3_RNG_MASK (0x1FFF0000U) #define TRNG_SCR3L_RUN3_RNG_SHIFT (16U) #define TRNG_SCR3L_RUN3_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR3L_RUN3_RNG_SHIFT)) & TRNG_SCR3L_RUN3_RNG_MASK) +/*! @} */ /*! @name SCR4C - Statistical Check Run Length 4 Count Register */ +/*! @{ */ #define TRNG_SCR4C_R4_0_CT_MASK (0xFFFU) #define TRNG_SCR4C_R4_0_CT_SHIFT (0U) #define TRNG_SCR4C_R4_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR4C_R4_0_CT_SHIFT)) & TRNG_SCR4C_R4_0_CT_MASK) #define TRNG_SCR4C_R4_1_CT_MASK (0xFFF0000U) #define TRNG_SCR4C_R4_1_CT_SHIFT (16U) #define TRNG_SCR4C_R4_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR4C_R4_1_CT_SHIFT)) & TRNG_SCR4C_R4_1_CT_MASK) +/*! @} */ /*! @name SCR4L - Statistical Check Run Length 4 Limit Register */ +/*! @{ */ #define TRNG_SCR4L_RUN4_MAX_MASK (0xFFFU) #define TRNG_SCR4L_RUN4_MAX_SHIFT (0U) #define TRNG_SCR4L_RUN4_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR4L_RUN4_MAX_SHIFT)) & TRNG_SCR4L_RUN4_MAX_MASK) #define TRNG_SCR4L_RUN4_RNG_MASK (0xFFF0000U) #define TRNG_SCR4L_RUN4_RNG_SHIFT (16U) #define TRNG_SCR4L_RUN4_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR4L_RUN4_RNG_SHIFT)) & TRNG_SCR4L_RUN4_RNG_MASK) +/*! @} */ /*! @name SCR5C - Statistical Check Run Length 5 Count Register */ +/*! @{ */ #define TRNG_SCR5C_R5_0_CT_MASK (0x7FFU) #define TRNG_SCR5C_R5_0_CT_SHIFT (0U) #define TRNG_SCR5C_R5_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR5C_R5_0_CT_SHIFT)) & TRNG_SCR5C_R5_0_CT_MASK) #define TRNG_SCR5C_R5_1_CT_MASK (0x7FF0000U) #define TRNG_SCR5C_R5_1_CT_SHIFT (16U) #define TRNG_SCR5C_R5_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR5C_R5_1_CT_SHIFT)) & TRNG_SCR5C_R5_1_CT_MASK) +/*! @} */ /*! @name SCR5L - Statistical Check Run Length 5 Limit Register */ +/*! @{ */ #define TRNG_SCR5L_RUN5_MAX_MASK (0x7FFU) #define TRNG_SCR5L_RUN5_MAX_SHIFT (0U) #define TRNG_SCR5L_RUN5_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR5L_RUN5_MAX_SHIFT)) & TRNG_SCR5L_RUN5_MAX_MASK) #define TRNG_SCR5L_RUN5_RNG_MASK (0x7FF0000U) #define TRNG_SCR5L_RUN5_RNG_SHIFT (16U) #define TRNG_SCR5L_RUN5_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR5L_RUN5_RNG_SHIFT)) & TRNG_SCR5L_RUN5_RNG_MASK) +/*! @} */ /*! @name SCR6PC - Statistical Check Run Length 6+ Count Register */ +/*! @{ */ #define TRNG_SCR6PC_R6P_0_CT_MASK (0x7FFU) #define TRNG_SCR6PC_R6P_0_CT_SHIFT (0U) #define TRNG_SCR6PC_R6P_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR6PC_R6P_0_CT_SHIFT)) & TRNG_SCR6PC_R6P_0_CT_MASK) #define TRNG_SCR6PC_R6P_1_CT_MASK (0x7FF0000U) #define TRNG_SCR6PC_R6P_1_CT_SHIFT (16U) #define TRNG_SCR6PC_R6P_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR6PC_R6P_1_CT_SHIFT)) & TRNG_SCR6PC_R6P_1_CT_MASK) +/*! @} */ /*! @name SCR6PL - Statistical Check Run Length 6+ Limit Register */ +/*! @{ */ #define TRNG_SCR6PL_RUN6P_MAX_MASK (0x7FFU) #define TRNG_SCR6PL_RUN6P_MAX_SHIFT (0U) #define TRNG_SCR6PL_RUN6P_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR6PL_RUN6P_MAX_SHIFT)) & TRNG_SCR6PL_RUN6P_MAX_MASK) #define TRNG_SCR6PL_RUN6P_RNG_MASK (0x7FF0000U) #define TRNG_SCR6PL_RUN6P_RNG_SHIFT (16U) #define TRNG_SCR6PL_RUN6P_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR6PL_RUN6P_RNG_SHIFT)) & TRNG_SCR6PL_RUN6P_RNG_MASK) +/*! @} */ /*! @name STATUS - Status Register */ +/*! @{ */ #define TRNG_STATUS_TF1BR0_MASK (0x1U) #define TRNG_STATUS_TF1BR0_SHIFT (0U) #define TRNG_STATUS_TF1BR0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF1BR0_SHIFT)) & TRNG_STATUS_TF1BR0_MASK) @@ -19333,150 +31305,242 @@ typedef struct { #define TRNG_STATUS_RETRY_CT_MASK (0xF0000U) #define TRNG_STATUS_RETRY_CT_SHIFT (16U) #define TRNG_STATUS_RETRY_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_RETRY_CT_SHIFT)) & TRNG_STATUS_RETRY_CT_MASK) +/*! @} */ /*! @name ENT - Entropy Read Register */ +/*! @{ */ #define TRNG_ENT_ENT_MASK (0xFFFFFFFFU) #define TRNG_ENT_ENT_SHIFT (0U) #define TRNG_ENT_ENT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_ENT_ENT_SHIFT)) & TRNG_ENT_ENT_MASK) +/*! @} */ /* The count of TRNG_ENT */ #define TRNG_ENT_COUNT (16U) /*! @name PKRCNT10 - Statistical Check Poker Count 1 and 0 Register */ +/*! @{ */ #define TRNG_PKRCNT10_PKR_0_CT_MASK (0xFFFFU) #define TRNG_PKRCNT10_PKR_0_CT_SHIFT (0U) #define TRNG_PKRCNT10_PKR_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT10_PKR_0_CT_SHIFT)) & TRNG_PKRCNT10_PKR_0_CT_MASK) #define TRNG_PKRCNT10_PKR_1_CT_MASK (0xFFFF0000U) #define TRNG_PKRCNT10_PKR_1_CT_SHIFT (16U) #define TRNG_PKRCNT10_PKR_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT10_PKR_1_CT_SHIFT)) & TRNG_PKRCNT10_PKR_1_CT_MASK) +/*! @} */ /*! @name PKRCNT32 - Statistical Check Poker Count 3 and 2 Register */ +/*! @{ */ #define TRNG_PKRCNT32_PKR_2_CT_MASK (0xFFFFU) #define TRNG_PKRCNT32_PKR_2_CT_SHIFT (0U) #define TRNG_PKRCNT32_PKR_2_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT32_PKR_2_CT_SHIFT)) & TRNG_PKRCNT32_PKR_2_CT_MASK) #define TRNG_PKRCNT32_PKR_3_CT_MASK (0xFFFF0000U) #define TRNG_PKRCNT32_PKR_3_CT_SHIFT (16U) #define TRNG_PKRCNT32_PKR_3_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT32_PKR_3_CT_SHIFT)) & TRNG_PKRCNT32_PKR_3_CT_MASK) +/*! @} */ /*! @name PKRCNT54 - Statistical Check Poker Count 5 and 4 Register */ +/*! @{ */ #define TRNG_PKRCNT54_PKR_4_CT_MASK (0xFFFFU) #define TRNG_PKRCNT54_PKR_4_CT_SHIFT (0U) #define TRNG_PKRCNT54_PKR_4_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT54_PKR_4_CT_SHIFT)) & TRNG_PKRCNT54_PKR_4_CT_MASK) #define TRNG_PKRCNT54_PKR_5_CT_MASK (0xFFFF0000U) #define TRNG_PKRCNT54_PKR_5_CT_SHIFT (16U) #define TRNG_PKRCNT54_PKR_5_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT54_PKR_5_CT_SHIFT)) & TRNG_PKRCNT54_PKR_5_CT_MASK) +/*! @} */ /*! @name PKRCNT76 - Statistical Check Poker Count 7 and 6 Register */ +/*! @{ */ #define TRNG_PKRCNT76_PKR_6_CT_MASK (0xFFFFU) #define TRNG_PKRCNT76_PKR_6_CT_SHIFT (0U) #define TRNG_PKRCNT76_PKR_6_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT76_PKR_6_CT_SHIFT)) & TRNG_PKRCNT76_PKR_6_CT_MASK) #define TRNG_PKRCNT76_PKR_7_CT_MASK (0xFFFF0000U) #define TRNG_PKRCNT76_PKR_7_CT_SHIFT (16U) #define TRNG_PKRCNT76_PKR_7_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT76_PKR_7_CT_SHIFT)) & TRNG_PKRCNT76_PKR_7_CT_MASK) +/*! @} */ /*! @name PKRCNT98 - Statistical Check Poker Count 9 and 8 Register */ +/*! @{ */ #define TRNG_PKRCNT98_PKR_8_CT_MASK (0xFFFFU) #define TRNG_PKRCNT98_PKR_8_CT_SHIFT (0U) #define TRNG_PKRCNT98_PKR_8_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT98_PKR_8_CT_SHIFT)) & TRNG_PKRCNT98_PKR_8_CT_MASK) #define TRNG_PKRCNT98_PKR_9_CT_MASK (0xFFFF0000U) #define TRNG_PKRCNT98_PKR_9_CT_SHIFT (16U) #define TRNG_PKRCNT98_PKR_9_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT98_PKR_9_CT_SHIFT)) & TRNG_PKRCNT98_PKR_9_CT_MASK) +/*! @} */ /*! @name PKRCNTBA - Statistical Check Poker Count B and A Register */ +/*! @{ */ #define TRNG_PKRCNTBA_PKR_A_CT_MASK (0xFFFFU) #define TRNG_PKRCNTBA_PKR_A_CT_SHIFT (0U) #define TRNG_PKRCNTBA_PKR_A_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTBA_PKR_A_CT_SHIFT)) & TRNG_PKRCNTBA_PKR_A_CT_MASK) #define TRNG_PKRCNTBA_PKR_B_CT_MASK (0xFFFF0000U) #define TRNG_PKRCNTBA_PKR_B_CT_SHIFT (16U) #define TRNG_PKRCNTBA_PKR_B_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTBA_PKR_B_CT_SHIFT)) & TRNG_PKRCNTBA_PKR_B_CT_MASK) +/*! @} */ /*! @name PKRCNTDC - Statistical Check Poker Count D and C Register */ +/*! @{ */ #define TRNG_PKRCNTDC_PKR_C_CT_MASK (0xFFFFU) #define TRNG_PKRCNTDC_PKR_C_CT_SHIFT (0U) #define TRNG_PKRCNTDC_PKR_C_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTDC_PKR_C_CT_SHIFT)) & TRNG_PKRCNTDC_PKR_C_CT_MASK) #define TRNG_PKRCNTDC_PKR_D_CT_MASK (0xFFFF0000U) #define TRNG_PKRCNTDC_PKR_D_CT_SHIFT (16U) #define TRNG_PKRCNTDC_PKR_D_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTDC_PKR_D_CT_SHIFT)) & TRNG_PKRCNTDC_PKR_D_CT_MASK) +/*! @} */ /*! @name PKRCNTFE - Statistical Check Poker Count F and E Register */ +/*! @{ */ #define TRNG_PKRCNTFE_PKR_E_CT_MASK (0xFFFFU) #define TRNG_PKRCNTFE_PKR_E_CT_SHIFT (0U) #define TRNG_PKRCNTFE_PKR_E_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTFE_PKR_E_CT_SHIFT)) & TRNG_PKRCNTFE_PKR_E_CT_MASK) #define TRNG_PKRCNTFE_PKR_F_CT_MASK (0xFFFF0000U) #define TRNG_PKRCNTFE_PKR_F_CT_SHIFT (16U) #define TRNG_PKRCNTFE_PKR_F_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTFE_PKR_F_CT_SHIFT)) & TRNG_PKRCNTFE_PKR_F_CT_MASK) +/*! @} */ /*! @name SEC_CFG - Security Configuration Register */ +/*! @{ */ #define TRNG_SEC_CFG_UNUSED0_MASK (0x1U) #define TRNG_SEC_CFG_UNUSED0_SHIFT (0U) #define TRNG_SEC_CFG_UNUSED0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SEC_CFG_UNUSED0_SHIFT)) & TRNG_SEC_CFG_UNUSED0_MASK) #define TRNG_SEC_CFG_NO_PRGM_MASK (0x2U) #define TRNG_SEC_CFG_NO_PRGM_SHIFT (1U) +/*! NO_PRGM + * 0b0..Programability of registers controlled only by the Miscellaneous Control Register's access mode bit. + * 0b1..Overides Miscellaneous Control Register access mode and prevents TRNG register programming. + */ #define TRNG_SEC_CFG_NO_PRGM(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SEC_CFG_NO_PRGM_SHIFT)) & TRNG_SEC_CFG_NO_PRGM_MASK) #define TRNG_SEC_CFG_UNUSED2_MASK (0x4U) #define TRNG_SEC_CFG_UNUSED2_SHIFT (2U) #define TRNG_SEC_CFG_UNUSED2(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SEC_CFG_UNUSED2_SHIFT)) & TRNG_SEC_CFG_UNUSED2_MASK) +/*! @} */ /*! @name INT_CTRL - Interrupt Control Register */ +/*! @{ */ #define TRNG_INT_CTRL_HW_ERR_MASK (0x1U) #define TRNG_INT_CTRL_HW_ERR_SHIFT (0U) +/*! HW_ERR + * 0b0..Corresponding bit of INT_STATUS register cleared. + * 0b1..Corresponding bit of INT_STATUS register active. + */ #define TRNG_INT_CTRL_HW_ERR(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_CTRL_HW_ERR_SHIFT)) & TRNG_INT_CTRL_HW_ERR_MASK) #define TRNG_INT_CTRL_ENT_VAL_MASK (0x2U) #define TRNG_INT_CTRL_ENT_VAL_SHIFT (1U) +/*! ENT_VAL + * 0b0..Same behavior as bit 0 of this register. + * 0b1..Same behavior as bit 0 of this register. + */ #define TRNG_INT_CTRL_ENT_VAL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_CTRL_ENT_VAL_SHIFT)) & TRNG_INT_CTRL_ENT_VAL_MASK) #define TRNG_INT_CTRL_FRQ_CT_FAIL_MASK (0x4U) #define TRNG_INT_CTRL_FRQ_CT_FAIL_SHIFT (2U) +/*! FRQ_CT_FAIL + * 0b0..Same behavior as bit 0 of this register. + * 0b1..Same behavior as bit 0 of this register. + */ #define TRNG_INT_CTRL_FRQ_CT_FAIL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_CTRL_FRQ_CT_FAIL_SHIFT)) & TRNG_INT_CTRL_FRQ_CT_FAIL_MASK) #define TRNG_INT_CTRL_UNUSED_MASK (0xFFFFFFF8U) #define TRNG_INT_CTRL_UNUSED_SHIFT (3U) #define TRNG_INT_CTRL_UNUSED(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_CTRL_UNUSED_SHIFT)) & TRNG_INT_CTRL_UNUSED_MASK) +/*! @} */ /*! @name INT_MASK - Mask Register */ +/*! @{ */ #define TRNG_INT_MASK_HW_ERR_MASK (0x1U) #define TRNG_INT_MASK_HW_ERR_SHIFT (0U) +/*! HW_ERR + * 0b0..Corresponding interrupt of INT_STATUS is masked. + * 0b1..Corresponding bit of INT_STATUS is active. + */ #define TRNG_INT_MASK_HW_ERR(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_MASK_HW_ERR_SHIFT)) & TRNG_INT_MASK_HW_ERR_MASK) #define TRNG_INT_MASK_ENT_VAL_MASK (0x2U) #define TRNG_INT_MASK_ENT_VAL_SHIFT (1U) +/*! ENT_VAL + * 0b0..Same behavior as bit 0 of this register. + * 0b1..Same behavior as bit 0 of this register. + */ #define TRNG_INT_MASK_ENT_VAL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_MASK_ENT_VAL_SHIFT)) & TRNG_INT_MASK_ENT_VAL_MASK) #define TRNG_INT_MASK_FRQ_CT_FAIL_MASK (0x4U) #define TRNG_INT_MASK_FRQ_CT_FAIL_SHIFT (2U) +/*! FRQ_CT_FAIL + * 0b0..Same behavior as bit 0 of this register. + * 0b1..Same behavior as bit 0 of this register. + */ #define TRNG_INT_MASK_FRQ_CT_FAIL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_MASK_FRQ_CT_FAIL_SHIFT)) & TRNG_INT_MASK_FRQ_CT_FAIL_MASK) +/*! @} */ /*! @name INT_STATUS - Interrupt Status Register */ +/*! @{ */ #define TRNG_INT_STATUS_HW_ERR_MASK (0x1U) #define TRNG_INT_STATUS_HW_ERR_SHIFT (0U) +/*! HW_ERR + * 0b0..no error + * 0b1..error detected. + */ #define TRNG_INT_STATUS_HW_ERR(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_STATUS_HW_ERR_SHIFT)) & TRNG_INT_STATUS_HW_ERR_MASK) #define TRNG_INT_STATUS_ENT_VAL_MASK (0x2U) #define TRNG_INT_STATUS_ENT_VAL_SHIFT (1U) +/*! ENT_VAL + * 0b0..Busy generation entropy. Any value read is invalid. + * 0b1..TRNG can be stopped and entropy is valid if read. + */ #define TRNG_INT_STATUS_ENT_VAL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_STATUS_ENT_VAL_SHIFT)) & TRNG_INT_STATUS_ENT_VAL_MASK) #define TRNG_INT_STATUS_FRQ_CT_FAIL_MASK (0x4U) #define TRNG_INT_STATUS_FRQ_CT_FAIL_SHIFT (2U) +/*! FRQ_CT_FAIL + * 0b0..No hardware nor self test frequency errors. + * 0b1..The frequency counter has detected a failure. + */ #define TRNG_INT_STATUS_FRQ_CT_FAIL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_STATUS_FRQ_CT_FAIL_SHIFT)) & TRNG_INT_STATUS_FRQ_CT_FAIL_MASK) +/*! @} */ /*! @name VID1 - Version ID Register (MS) */ +/*! @{ */ #define TRNG_VID1_MIN_REV_MASK (0xFFU) #define TRNG_VID1_MIN_REV_SHIFT (0U) +/*! MIN_REV + * 0b00000000..Minor revision number for TRNG. + */ #define TRNG_VID1_MIN_REV(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID1_MIN_REV_SHIFT)) & TRNG_VID1_MIN_REV_MASK) #define TRNG_VID1_MAJ_REV_MASK (0xFF00U) #define TRNG_VID1_MAJ_REV_SHIFT (8U) +/*! MAJ_REV + * 0b00000001..Major revision number for TRNG. + */ #define TRNG_VID1_MAJ_REV(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID1_MAJ_REV_SHIFT)) & TRNG_VID1_MAJ_REV_MASK) #define TRNG_VID1_IP_ID_MASK (0xFFFF0000U) #define TRNG_VID1_IP_ID_SHIFT (16U) +/*! IP_ID + * 0b0000000000110000..ID for TRNG. + */ #define TRNG_VID1_IP_ID(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID1_IP_ID_SHIFT)) & TRNG_VID1_IP_ID_MASK) +/*! @} */ /*! @name VID2 - Version ID Register (LS) */ +/*! @{ */ #define TRNG_VID2_CONFIG_OPT_MASK (0xFFU) #define TRNG_VID2_CONFIG_OPT_SHIFT (0U) +/*! CONFIG_OPT + * 0b00000000..TRNG_CONFIG_OPT for TRNG. + */ #define TRNG_VID2_CONFIG_OPT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID2_CONFIG_OPT_SHIFT)) & TRNG_VID2_CONFIG_OPT_MASK) #define TRNG_VID2_ECO_REV_MASK (0xFF00U) #define TRNG_VID2_ECO_REV_SHIFT (8U) +/*! ECO_REV + * 0b00000000..TRNG_ECO_REV for TRNG. + */ #define TRNG_VID2_ECO_REV(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID2_ECO_REV_SHIFT)) & TRNG_VID2_ECO_REV_MASK) #define TRNG_VID2_INTG_OPT_MASK (0xFF0000U) #define TRNG_VID2_INTG_OPT_SHIFT (16U) +/*! INTG_OPT + * 0b00000000..INTG_OPT for TRNG. + */ #define TRNG_VID2_INTG_OPT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID2_INTG_OPT_SHIFT)) & TRNG_VID2_INTG_OPT_MASK) #define TRNG_VID2_ERA_MASK (0xFF000000U) #define TRNG_VID2_ERA_SHIFT (24U) +/*! ERA + * 0b00000000..COMPILE_OPT for TRNG. + */ #define TRNG_VID2_ERA(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID2_ERA_SHIFT)) & TRNG_VID2_ERA_MASK) +/*! @} */ /*! @@ -19512,9 +31576,9 @@ typedef struct { /** TSC - Register Layout Typedef */ typedef struct { - __IO uint32_t BASIC_SETTING; /**< PS Input Buffer Address, offset: 0x0 */ + __IO uint32_t BASIC_SETTING; /**< , offset: 0x0 */ uint8_t RESERVED_0[12]; - __IO uint32_t PS_INPUT_BUFFER_ADDR; /**< PS Input Buffer Address, offset: 0x10 */ + __IO uint32_t PRE_CHARGE_TIME; /**< , offset: 0x10 */ uint8_t RESERVED_1[12]; __IO uint32_t FLOW_CONTROL; /**< Flow Control, offset: 0x20 */ uint8_t RESERVED_2[12]; @@ -19540,87 +31604,166 @@ typedef struct { * @{ */ -/*! @name BASIC_SETTING - PS Input Buffer Address */ +/*! @name BASIC_SETTING - */ +/*! @{ */ #define TSC_BASIC_SETTING_AUTO_MEASURE_MASK (0x1U) #define TSC_BASIC_SETTING_AUTO_MEASURE_SHIFT (0U) +/*! AUTO_MEASURE - Auto Measure + * 0b0..Disable Auto Measure + * 0b1..Auto Measure + */ #define TSC_BASIC_SETTING_AUTO_MEASURE(x) (((uint32_t)(((uint32_t)(x)) << TSC_BASIC_SETTING_AUTO_MEASURE_SHIFT)) & TSC_BASIC_SETTING_AUTO_MEASURE_MASK) #define TSC_BASIC_SETTING_4_5_WIRE_MASK (0x10U) #define TSC_BASIC_SETTING_4_5_WIRE_SHIFT (4U) +/*! 4_5_WIRE - 4/5 Wire detection + * 0b0..4-Wire Detection Mode + * 0b1..5-Wire Detection Mode + */ #define TSC_BASIC_SETTING_4_5_WIRE(x) (((uint32_t)(((uint32_t)(x)) << TSC_BASIC_SETTING_4_5_WIRE_SHIFT)) & TSC_BASIC_SETTING_4_5_WIRE_MASK) #define TSC_BASIC_SETTING_MEASURE_DELAY_TIME_MASK (0xFFFFFF00U) #define TSC_BASIC_SETTING_MEASURE_DELAY_TIME_SHIFT (8U) #define TSC_BASIC_SETTING_MEASURE_DELAY_TIME(x) (((uint32_t)(((uint32_t)(x)) << TSC_BASIC_SETTING_MEASURE_DELAY_TIME_SHIFT)) & TSC_BASIC_SETTING_MEASURE_DELAY_TIME_MASK) +/*! @} */ -/*! @name PS_INPUT_BUFFER_ADDR - PS Input Buffer Address */ -#define TSC_PS_INPUT_BUFFER_ADDR_PRE_CHARGE_TIME_MASK (0xFFFFFFFFU) -#define TSC_PS_INPUT_BUFFER_ADDR_PRE_CHARGE_TIME_SHIFT (0U) -#define TSC_PS_INPUT_BUFFER_ADDR_PRE_CHARGE_TIME(x) (((uint32_t)(((uint32_t)(x)) << TSC_PS_INPUT_BUFFER_ADDR_PRE_CHARGE_TIME_SHIFT)) & TSC_PS_INPUT_BUFFER_ADDR_PRE_CHARGE_TIME_MASK) +/*! @name PRE_CHARGE_TIME - */ +/*! @{ */ +#define TSC_PRE_CHARGE_TIME_PRE_CHARGE_TIME_MASK (0xFFFFFFFFU) +#define TSC_PRE_CHARGE_TIME_PRE_CHARGE_TIME_SHIFT (0U) +#define TSC_PRE_CHARGE_TIME_PRE_CHARGE_TIME(x) (((uint32_t)(((uint32_t)(x)) << TSC_PRE_CHARGE_TIME_PRE_CHARGE_TIME_SHIFT)) & TSC_PRE_CHARGE_TIME_PRE_CHARGE_TIME_MASK) +/*! @} */ /*! @name FLOW_CONTROL - Flow Control */ +/*! @{ */ #define TSC_FLOW_CONTROL_SW_RST_MASK (0x1U) #define TSC_FLOW_CONTROL_SW_RST_SHIFT (0U) #define TSC_FLOW_CONTROL_SW_RST(x) (((uint32_t)(((uint32_t)(x)) << TSC_FLOW_CONTROL_SW_RST_SHIFT)) & TSC_FLOW_CONTROL_SW_RST_MASK) #define TSC_FLOW_CONTROL_START_MEASURE_MASK (0x10U) #define TSC_FLOW_CONTROL_START_MEASURE_SHIFT (4U) +/*! START_MEASURE - Start Measure + * 0b0..Do not start measure for now + * 0b1..Start measure the X/Y coordinate value + */ #define TSC_FLOW_CONTROL_START_MEASURE(x) (((uint32_t)(((uint32_t)(x)) << TSC_FLOW_CONTROL_START_MEASURE_SHIFT)) & TSC_FLOW_CONTROL_START_MEASURE_MASK) #define TSC_FLOW_CONTROL_DROP_MEASURE_MASK (0x100U) #define TSC_FLOW_CONTROL_DROP_MEASURE_SHIFT (8U) +/*! DROP_MEASURE - Drop Measure + * 0b0..Do not drop measure for now + * 0b1..Drop the measure and controller return to idle status + */ #define TSC_FLOW_CONTROL_DROP_MEASURE(x) (((uint32_t)(((uint32_t)(x)) << TSC_FLOW_CONTROL_DROP_MEASURE_SHIFT)) & TSC_FLOW_CONTROL_DROP_MEASURE_MASK) #define TSC_FLOW_CONTROL_START_SENSE_MASK (0x1000U) #define TSC_FLOW_CONTROL_START_SENSE_SHIFT (12U) +/*! START_SENSE - Start Sense + * 0b0..Stay at idle status + * 0b1..Start sense detection and (if auto_measure set to 1) measure after detect a touch + */ #define TSC_FLOW_CONTROL_START_SENSE(x) (((uint32_t)(((uint32_t)(x)) << TSC_FLOW_CONTROL_START_SENSE_SHIFT)) & TSC_FLOW_CONTROL_START_SENSE_MASK) #define TSC_FLOW_CONTROL_DISABLE_MASK (0x10000U) #define TSC_FLOW_CONTROL_DISABLE_SHIFT (16U) +/*! DISABLE + * 0b0..Leave HW state machine control + * 0b1..SW set to idle status + */ #define TSC_FLOW_CONTROL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << TSC_FLOW_CONTROL_DISABLE_SHIFT)) & TSC_FLOW_CONTROL_DISABLE_MASK) +/*! @} */ /*! @name MEASEURE_VALUE - Measure Value */ +/*! @{ */ #define TSC_MEASEURE_VALUE_Y_VALUE_MASK (0xFFFU) #define TSC_MEASEURE_VALUE_Y_VALUE_SHIFT (0U) #define TSC_MEASEURE_VALUE_Y_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TSC_MEASEURE_VALUE_Y_VALUE_SHIFT)) & TSC_MEASEURE_VALUE_Y_VALUE_MASK) #define TSC_MEASEURE_VALUE_X_VALUE_MASK (0xFFF0000U) #define TSC_MEASEURE_VALUE_X_VALUE_SHIFT (16U) #define TSC_MEASEURE_VALUE_X_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TSC_MEASEURE_VALUE_X_VALUE_SHIFT)) & TSC_MEASEURE_VALUE_X_VALUE_MASK) +/*! @} */ /*! @name INT_EN - Interrupt Enable */ +/*! @{ */ #define TSC_INT_EN_MEASURE_INT_EN_MASK (0x1U) #define TSC_INT_EN_MEASURE_INT_EN_SHIFT (0U) +/*! MEASURE_INT_EN - Measure Interrupt Enable + * 0b0..Disable measure interrupt + * 0b1..Enable measure interrupt + */ #define TSC_INT_EN_MEASURE_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << TSC_INT_EN_MEASURE_INT_EN_SHIFT)) & TSC_INT_EN_MEASURE_INT_EN_MASK) #define TSC_INT_EN_DETECT_INT_EN_MASK (0x10U) #define TSC_INT_EN_DETECT_INT_EN_SHIFT (4U) +/*! DETECT_INT_EN - Detect Interrupt Enable + * 0b0..Disable detect interrupt + * 0b1..Enable detect interrupt + */ #define TSC_INT_EN_DETECT_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << TSC_INT_EN_DETECT_INT_EN_SHIFT)) & TSC_INT_EN_DETECT_INT_EN_MASK) #define TSC_INT_EN_IDLE_SW_INT_EN_MASK (0x1000U) #define TSC_INT_EN_IDLE_SW_INT_EN_SHIFT (12U) +/*! IDLE_SW_INT_EN - Idle Software Interrupt Enable + * 0b0..Disable idle software interrupt + * 0b1..Enable idle software interrupt + */ #define TSC_INT_EN_IDLE_SW_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << TSC_INT_EN_IDLE_SW_INT_EN_SHIFT)) & TSC_INT_EN_IDLE_SW_INT_EN_MASK) +/*! @} */ /*! @name INT_SIG_EN - Interrupt Signal Enable */ +/*! @{ */ #define TSC_INT_SIG_EN_MEASURE_SIG_EN_MASK (0x1U) #define TSC_INT_SIG_EN_MEASURE_SIG_EN_SHIFT (0U) #define TSC_INT_SIG_EN_MEASURE_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << TSC_INT_SIG_EN_MEASURE_SIG_EN_SHIFT)) & TSC_INT_SIG_EN_MEASURE_SIG_EN_MASK) #define TSC_INT_SIG_EN_DETECT_SIG_EN_MASK (0x10U) #define TSC_INT_SIG_EN_DETECT_SIG_EN_SHIFT (4U) +/*! DETECT_SIG_EN - Detect Signal Enable + * 0b0..Disable detect signal + * 0b1..Enable detect signal + */ #define TSC_INT_SIG_EN_DETECT_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << TSC_INT_SIG_EN_DETECT_SIG_EN_SHIFT)) & TSC_INT_SIG_EN_DETECT_SIG_EN_MASK) #define TSC_INT_SIG_EN_VALID_SIG_EN_MASK (0x100U) #define TSC_INT_SIG_EN_VALID_SIG_EN_SHIFT (8U) +/*! VALID_SIG_EN - Valid Signal Enable + * 0b0..Disable valid signal + * 0b1..Enable valid signal + */ #define TSC_INT_SIG_EN_VALID_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << TSC_INT_SIG_EN_VALID_SIG_EN_SHIFT)) & TSC_INT_SIG_EN_VALID_SIG_EN_MASK) #define TSC_INT_SIG_EN_IDLE_SW_SIG_EN_MASK (0x1000U) #define TSC_INT_SIG_EN_IDLE_SW_SIG_EN_SHIFT (12U) +/*! IDLE_SW_SIG_EN - Idle Software Signal Enable + * 0b0..Disable idle software signal + * 0b1..Enable idle software signal + */ #define TSC_INT_SIG_EN_IDLE_SW_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << TSC_INT_SIG_EN_IDLE_SW_SIG_EN_SHIFT)) & TSC_INT_SIG_EN_IDLE_SW_SIG_EN_MASK) +/*! @} */ /*! @name INT_STATUS - Intterrupt Status */ +/*! @{ */ #define TSC_INT_STATUS_MEASURE_MASK (0x1U) #define TSC_INT_STATUS_MEASURE_SHIFT (0U) +/*! MEASURE - Measure Signal + * 0b0..Does not exist a measure signal + * 0b1..Exist a measure signal + */ #define TSC_INT_STATUS_MEASURE(x) (((uint32_t)(((uint32_t)(x)) << TSC_INT_STATUS_MEASURE_SHIFT)) & TSC_INT_STATUS_MEASURE_MASK) #define TSC_INT_STATUS_DETECT_MASK (0x10U) #define TSC_INT_STATUS_DETECT_SHIFT (4U) +/*! DETECT - Detect Signal + * 0b0..Does not exist a detect signal + * 0b1..Exist detect signal + */ #define TSC_INT_STATUS_DETECT(x) (((uint32_t)(((uint32_t)(x)) << TSC_INT_STATUS_DETECT_SHIFT)) & TSC_INT_STATUS_DETECT_MASK) #define TSC_INT_STATUS_VALID_MASK (0x100U) #define TSC_INT_STATUS_VALID_SHIFT (8U) +/*! VALID - Valid Signal + * 0b0..There is no touch detected after measurement, indicates that the measured value is not valid + * 0b1..There is touch detection after measurement, indicates that the measure is valid + */ #define TSC_INT_STATUS_VALID(x) (((uint32_t)(((uint32_t)(x)) << TSC_INT_STATUS_VALID_SHIFT)) & TSC_INT_STATUS_VALID_MASK) #define TSC_INT_STATUS_IDLE_SW_MASK (0x1000U) #define TSC_INT_STATUS_IDLE_SW_SHIFT (12U) +/*! IDLE_SW - Idle Software + * 0b0..Haven't return to idle status + * 0b1..Already return to idle status + */ #define TSC_INT_STATUS_IDLE_SW(x) (((uint32_t)(((uint32_t)(x)) << TSC_INT_STATUS_IDLE_SW_SHIFT)) & TSC_INT_STATUS_IDLE_SW_MASK) +/*! @} */ /*! @name DEBUG_MODE - */ +/*! @{ */ #define TSC_DEBUG_MODE_ADC_CONV_VALUE_MASK (0xFFFU) #define TSC_DEBUG_MODE_ADC_CONV_VALUE_SHIFT (0U) #define TSC_DEBUG_MODE_ADC_CONV_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE_ADC_CONV_VALUE_SHIFT)) & TSC_DEBUG_MODE_ADC_CONV_VALUE_MASK) @@ -19632,84 +31775,198 @@ typedef struct { #define TSC_DEBUG_MODE_EXT_HWTS(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE_EXT_HWTS_SHIFT)) & TSC_DEBUG_MODE_EXT_HWTS_MASK) #define TSC_DEBUG_MODE_TRIGGER_MASK (0x1000000U) #define TSC_DEBUG_MODE_TRIGGER_SHIFT (24U) +/*! TRIGGER - Trigger + * 0b0..No hardware trigger signal + * 0b1..Hardware trigger signal, the signal must last at least 1 ips clock period + */ #define TSC_DEBUG_MODE_TRIGGER(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE_TRIGGER_SHIFT)) & TSC_DEBUG_MODE_TRIGGER_MASK) #define TSC_DEBUG_MODE_ADC_COCO_CLEAR_MASK (0x2000000U) #define TSC_DEBUG_MODE_ADC_COCO_CLEAR_SHIFT (25U) +/*! ADC_COCO_CLEAR - ADC Coco Clear + * 0b0..No ADC COCO clear + * 0b1..Set ADC COCO clear + */ #define TSC_DEBUG_MODE_ADC_COCO_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE_ADC_COCO_CLEAR_SHIFT)) & TSC_DEBUG_MODE_ADC_COCO_CLEAR_MASK) #define TSC_DEBUG_MODE_ADC_COCO_CLEAR_DISABLE_MASK (0x4000000U) #define TSC_DEBUG_MODE_ADC_COCO_CLEAR_DISABLE_SHIFT (26U) +/*! ADC_COCO_CLEAR_DISABLE - ADC COCO Clear Disable + * 0b0..Allow TSC hardware generates ADC COCO clear + * 0b1..Prevent TSC from generate ADC COCO clear signal + */ #define TSC_DEBUG_MODE_ADC_COCO_CLEAR_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE_ADC_COCO_CLEAR_DISABLE_SHIFT)) & TSC_DEBUG_MODE_ADC_COCO_CLEAR_DISABLE_MASK) #define TSC_DEBUG_MODE_DEBUG_EN_MASK (0x10000000U) #define TSC_DEBUG_MODE_DEBUG_EN_SHIFT (28U) +/*! DEBUG_EN - Debug Enable + * 0b0..Enable debug mode + * 0b1..Disable debug mode + */ #define TSC_DEBUG_MODE_DEBUG_EN(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE_DEBUG_EN_SHIFT)) & TSC_DEBUG_MODE_DEBUG_EN_MASK) +/*! @} */ /*! @name DEBUG_MODE2 - */ +/*! @{ */ #define TSC_DEBUG_MODE2_XPUL_PULL_DOWN_MASK (0x1U) #define TSC_DEBUG_MODE2_XPUL_PULL_DOWN_SHIFT (0U) +/*! XPUL_PULL_DOWN - XPUL Wire Pull Down Switch + * 0b0..Close the switch + * 0b1..Open up the switch + */ #define TSC_DEBUG_MODE2_XPUL_PULL_DOWN(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_XPUL_PULL_DOWN_SHIFT)) & TSC_DEBUG_MODE2_XPUL_PULL_DOWN_MASK) #define TSC_DEBUG_MODE2_XPUL_PULL_UP_MASK (0x2U) #define TSC_DEBUG_MODE2_XPUL_PULL_UP_SHIFT (1U) +/*! XPUL_PULL_UP - XPUL Wire Pull Up Switch + * 0b0..Close the switch + * 0b1..Open up the switch + */ #define TSC_DEBUG_MODE2_XPUL_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_XPUL_PULL_UP_SHIFT)) & TSC_DEBUG_MODE2_XPUL_PULL_UP_MASK) #define TSC_DEBUG_MODE2_XPUL_200K_PULL_UP_MASK (0x4U) #define TSC_DEBUG_MODE2_XPUL_200K_PULL_UP_SHIFT (2U) +/*! XPUL_200K_PULL_UP - XPUL Wire 200K Pull Up Switch + * 0b0..Close the switch + * 0b1..Open up the switch + */ #define TSC_DEBUG_MODE2_XPUL_200K_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_XPUL_200K_PULL_UP_SHIFT)) & TSC_DEBUG_MODE2_XPUL_200K_PULL_UP_MASK) #define TSC_DEBUG_MODE2_XNUR_PULL_DOWN_MASK (0x8U) #define TSC_DEBUG_MODE2_XNUR_PULL_DOWN_SHIFT (3U) +/*! XNUR_PULL_DOWN - XNUR Wire Pull Down Switch + * 0b0..Close the switch + * 0b1..Open up the switch + */ #define TSC_DEBUG_MODE2_XNUR_PULL_DOWN(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_XNUR_PULL_DOWN_SHIFT)) & TSC_DEBUG_MODE2_XNUR_PULL_DOWN_MASK) #define TSC_DEBUG_MODE2_XNUR_PULL_UP_MASK (0x10U) #define TSC_DEBUG_MODE2_XNUR_PULL_UP_SHIFT (4U) +/*! XNUR_PULL_UP - XNUR Wire Pull Up Switch + * 0b0..Close the switch + * 0b1..Open up the switch + */ #define TSC_DEBUG_MODE2_XNUR_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_XNUR_PULL_UP_SHIFT)) & TSC_DEBUG_MODE2_XNUR_PULL_UP_MASK) #define TSC_DEBUG_MODE2_XNUR_200K_PULL_UP_MASK (0x20U) #define TSC_DEBUG_MODE2_XNUR_200K_PULL_UP_SHIFT (5U) +/*! XNUR_200K_PULL_UP - XNUR Wire 200K Pull Up Switch + * 0b0..Close the switch + * 0b1..Open up the switch + */ #define TSC_DEBUG_MODE2_XNUR_200K_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_XNUR_200K_PULL_UP_SHIFT)) & TSC_DEBUG_MODE2_XNUR_200K_PULL_UP_MASK) #define TSC_DEBUG_MODE2_YPLL_PULL_DOWN_MASK (0x40U) #define TSC_DEBUG_MODE2_YPLL_PULL_DOWN_SHIFT (6U) +/*! YPLL_PULL_DOWN - YPLL Wire Pull Down Switch + * 0b0..Close the switch + * 0b1..Open up the switch + */ #define TSC_DEBUG_MODE2_YPLL_PULL_DOWN(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_YPLL_PULL_DOWN_SHIFT)) & TSC_DEBUG_MODE2_YPLL_PULL_DOWN_MASK) #define TSC_DEBUG_MODE2_YPLL_PULL_UP_MASK (0x80U) #define TSC_DEBUG_MODE2_YPLL_PULL_UP_SHIFT (7U) +/*! YPLL_PULL_UP - YPLL Wire Pull Up Switch + * 0b0..Close the switch + * 0b1..Open the switch + */ #define TSC_DEBUG_MODE2_YPLL_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_YPLL_PULL_UP_SHIFT)) & TSC_DEBUG_MODE2_YPLL_PULL_UP_MASK) #define TSC_DEBUG_MODE2_YPLL_200K_PULL_UP_MASK (0x100U) #define TSC_DEBUG_MODE2_YPLL_200K_PULL_UP_SHIFT (8U) +/*! YPLL_200K_PULL_UP - YPLL Wire 200K Pull Up Switch + * 0b0..Close the switch + * 0b1..Open up the switch + */ #define TSC_DEBUG_MODE2_YPLL_200K_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_YPLL_200K_PULL_UP_SHIFT)) & TSC_DEBUG_MODE2_YPLL_200K_PULL_UP_MASK) #define TSC_DEBUG_MODE2_YNLR_PULL_DOWN_MASK (0x200U) #define TSC_DEBUG_MODE2_YNLR_PULL_DOWN_SHIFT (9U) +/*! YNLR_PULL_DOWN - YNLR Wire Pull Down Switch + * 0b0..Close the switch + * 0b1..Open up the switch + */ #define TSC_DEBUG_MODE2_YNLR_PULL_DOWN(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_YNLR_PULL_DOWN_SHIFT)) & TSC_DEBUG_MODE2_YNLR_PULL_DOWN_MASK) #define TSC_DEBUG_MODE2_YNLR_PULL_UP_MASK (0x400U) #define TSC_DEBUG_MODE2_YNLR_PULL_UP_SHIFT (10U) +/*! YNLR_PULL_UP - YNLR Wire Pull Up Switch + * 0b0..Close the switch + * 0b1..Open up the switch + */ #define TSC_DEBUG_MODE2_YNLR_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_YNLR_PULL_UP_SHIFT)) & TSC_DEBUG_MODE2_YNLR_PULL_UP_MASK) #define TSC_DEBUG_MODE2_YNLR_200K_PULL_UP_MASK (0x800U) #define TSC_DEBUG_MODE2_YNLR_200K_PULL_UP_SHIFT (11U) +/*! YNLR_200K_PULL_UP - YNLR Wire 200K Pull Up Switch + * 0b0..Close the switch + * 0b1..Open up the switch + */ #define TSC_DEBUG_MODE2_YNLR_200K_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_YNLR_200K_PULL_UP_SHIFT)) & TSC_DEBUG_MODE2_YNLR_200K_PULL_UP_MASK) #define TSC_DEBUG_MODE2_WIPER_PULL_DOWN_MASK (0x1000U) #define TSC_DEBUG_MODE2_WIPER_PULL_DOWN_SHIFT (12U) +/*! WIPER_PULL_DOWN - Wiper Wire Pull Down Switch + * 0b0..Close the switch + * 0b1..Open up the switch + */ #define TSC_DEBUG_MODE2_WIPER_PULL_DOWN(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_WIPER_PULL_DOWN_SHIFT)) & TSC_DEBUG_MODE2_WIPER_PULL_DOWN_MASK) #define TSC_DEBUG_MODE2_WIPER_PULL_UP_MASK (0x2000U) #define TSC_DEBUG_MODE2_WIPER_PULL_UP_SHIFT (13U) +/*! WIPER_PULL_UP - Wiper Wire Pull Up Switch + * 0b0..Close the switch + * 0b1..Open up the switch + */ #define TSC_DEBUG_MODE2_WIPER_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_WIPER_PULL_UP_SHIFT)) & TSC_DEBUG_MODE2_WIPER_PULL_UP_MASK) #define TSC_DEBUG_MODE2_WIPER_200K_PULL_UP_MASK (0x4000U) #define TSC_DEBUG_MODE2_WIPER_200K_PULL_UP_SHIFT (14U) +/*! WIPER_200K_PULL_UP - Wiper Wire 200K Pull Up Switch + * 0b0..Close the switch + * 0b1..Open up the switch + */ #define TSC_DEBUG_MODE2_WIPER_200K_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_WIPER_200K_PULL_UP_SHIFT)) & TSC_DEBUG_MODE2_WIPER_200K_PULL_UP_MASK) #define TSC_DEBUG_MODE2_DETECT_FOUR_WIRE_MASK (0x10000U) #define TSC_DEBUG_MODE2_DETECT_FOUR_WIRE_SHIFT (16U) +/*! DETECT_FOUR_WIRE - Detect Four Wire + * 0b0..No detect signal + * 0b1..Yes, there is a detect on the touch screen. + */ #define TSC_DEBUG_MODE2_DETECT_FOUR_WIRE(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_DETECT_FOUR_WIRE_SHIFT)) & TSC_DEBUG_MODE2_DETECT_FOUR_WIRE_MASK) #define TSC_DEBUG_MODE2_DETECT_FIVE_WIRE_MASK (0x20000U) #define TSC_DEBUG_MODE2_DETECT_FIVE_WIRE_SHIFT (17U) +/*! DETECT_FIVE_WIRE - Detect Five Wire + * 0b0..No detect signal + * 0b1..Yes, there is a detect on the touch screen. + */ #define TSC_DEBUG_MODE2_DETECT_FIVE_WIRE(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_DETECT_FIVE_WIRE_SHIFT)) & TSC_DEBUG_MODE2_DETECT_FIVE_WIRE_MASK) #define TSC_DEBUG_MODE2_STATE_MACHINE_MASK (0x700000U) #define TSC_DEBUG_MODE2_STATE_MACHINE_SHIFT (20U) +/*! STATE_MACHINE - State Machine + * 0b000..Idle + * 0b001..Pre-charge + * 0b010..Detect + * 0b011..X-measure + * 0b100..Y-measure + * 0b101..Pre-charge + * 0b110..Detect + */ #define TSC_DEBUG_MODE2_STATE_MACHINE(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_STATE_MACHINE_SHIFT)) & TSC_DEBUG_MODE2_STATE_MACHINE_MASK) #define TSC_DEBUG_MODE2_INTERMEDIATE_MASK (0x800000U) #define TSC_DEBUG_MODE2_INTERMEDIATE_SHIFT (23U) +/*! INTERMEDIATE - Intermediate State + * 0b0..Not in intermedia + * 0b1..Intermedia + */ #define TSC_DEBUG_MODE2_INTERMEDIATE(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_INTERMEDIATE_SHIFT)) & TSC_DEBUG_MODE2_INTERMEDIATE_MASK) #define TSC_DEBUG_MODE2_DETECT_ENABLE_FOUR_WIRE_MASK (0x1000000U) #define TSC_DEBUG_MODE2_DETECT_ENABLE_FOUR_WIRE_SHIFT (24U) +/*! DETECT_ENABLE_FOUR_WIRE - Detect Enable Four Wire + * 0b0..Do not read four wire detect value, read default value from analogue + * 0b1..Read four wire detect status from analogue + */ #define TSC_DEBUG_MODE2_DETECT_ENABLE_FOUR_WIRE(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_DETECT_ENABLE_FOUR_WIRE_SHIFT)) & TSC_DEBUG_MODE2_DETECT_ENABLE_FOUR_WIRE_MASK) #define TSC_DEBUG_MODE2_DETECT_ENABLE_FIVE_WIRE_MASK (0x10000000U) #define TSC_DEBUG_MODE2_DETECT_ENABLE_FIVE_WIRE_SHIFT (28U) +/*! DETECT_ENABLE_FIVE_WIRE - Detect Enable Five Wire + * 0b0..Do not read five wire detect value, read default value from analogue + * 0b1..Read five wire detect status from analogue + */ #define TSC_DEBUG_MODE2_DETECT_ENABLE_FIVE_WIRE(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_DETECT_ENABLE_FIVE_WIRE_SHIFT)) & TSC_DEBUG_MODE2_DETECT_ENABLE_FIVE_WIRE_MASK) #define TSC_DEBUG_MODE2_DE_GLITCH_MASK (0x60000000U) #define TSC_DEBUG_MODE2_DE_GLITCH_SHIFT (29U) +/*! DE_GLITCH + * 0b00..Normal function: 0x1fff ipg clock cycles; Low power mode: 0x9 low power clock cycles + * 0b01..Normal function: 0xfff ipg clock cycles; Low power mode: :0x7 low power clock cycles + * 0b10..Normal function: 0x7ff ipg clock cycles; Low power mode:0x5 low power clock cycles + * 0b11..Normal function: 0x3 ipg clock cycles; Low power mode:0x3 low power clock cycles + */ #define TSC_DEBUG_MODE2_DE_GLITCH(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_DE_GLITCH_SHIFT)) & TSC_DEBUG_MODE2_DE_GLITCH_MASK) +/*! @} */ /*! @@ -19816,6 +32073,7 @@ typedef struct { */ /*! @name ID - Identification register */ +/*! @{ */ #define USB_ID_ID_MASK (0x3FU) #define USB_ID_ID_SHIFT (0U) #define USB_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << USB_ID_ID_SHIFT)) & USB_ID_ID_MASK) @@ -19825,104 +32083,194 @@ typedef struct { #define USB_ID_REVISION_MASK (0xFF0000U) #define USB_ID_REVISION_SHIFT (16U) #define USB_ID_REVISION(x) (((uint32_t)(((uint32_t)(x)) << USB_ID_REVISION_SHIFT)) & USB_ID_REVISION_MASK) +/*! @} */ /*! @name HWGENERAL - Hardware General */ +/*! @{ */ #define USB_HWGENERAL_PHYW_MASK (0x30U) #define USB_HWGENERAL_PHYW_SHIFT (4U) +/*! PHYW + * 0b00..8 bit wide data bus Software non-programmable + * 0b01..16 bit wide data bus Software non-programmable + * 0b10..Reset to 8 bit wide data bus Software programmable + * 0b11..Reset to 16 bit wide data bus Software programmable + */ #define USB_HWGENERAL_PHYW(x) (((uint32_t)(((uint32_t)(x)) << USB_HWGENERAL_PHYW_SHIFT)) & USB_HWGENERAL_PHYW_MASK) #define USB_HWGENERAL_PHYM_MASK (0x1C0U) #define USB_HWGENERAL_PHYM_SHIFT (6U) +/*! PHYM + * 0b000..UTMI/UMTI+ + * 0b001..ULPI DDR + * 0b010..ULPI + * 0b011..Serial Only + * 0b100..Software programmable - reset to UTMI/UTMI+ + * 0b101..Software programmable - reset to ULPI DDR + * 0b110..Software programmable - reset to ULPI + * 0b111..Software programmable - reset to Serial + */ #define USB_HWGENERAL_PHYM(x) (((uint32_t)(((uint32_t)(x)) << USB_HWGENERAL_PHYM_SHIFT)) & USB_HWGENERAL_PHYM_MASK) #define USB_HWGENERAL_SM_MASK (0x600U) #define USB_HWGENERAL_SM_SHIFT (9U) +/*! SM + * 0b00..No Serial Engine, always use parallel signalling. + * 0b01..Serial Engine present, always use serial signalling for FS/LS. + * 0b10..Software programmable - Reset to use parallel signalling for FS/LS + * 0b11..Software programmable - Reset to use serial signalling for FS/LS + */ #define USB_HWGENERAL_SM(x) (((uint32_t)(((uint32_t)(x)) << USB_HWGENERAL_SM_SHIFT)) & USB_HWGENERAL_SM_MASK) +/*! @} */ /*! @name HWHOST - Host Hardware Parameters */ +/*! @{ */ #define USB_HWHOST_HC_MASK (0x1U) #define USB_HWHOST_HC_SHIFT (0U) +/*! HC + * 0b1..Supported + * 0b0..Not supported + */ #define USB_HWHOST_HC(x) (((uint32_t)(((uint32_t)(x)) << USB_HWHOST_HC_SHIFT)) & USB_HWHOST_HC_MASK) #define USB_HWHOST_NPORT_MASK (0xEU) #define USB_HWHOST_NPORT_SHIFT (1U) #define USB_HWHOST_NPORT(x) (((uint32_t)(((uint32_t)(x)) << USB_HWHOST_NPORT_SHIFT)) & USB_HWHOST_NPORT_MASK) +/*! @} */ /*! @name HWDEVICE - Device Hardware Parameters */ +/*! @{ */ #define USB_HWDEVICE_DC_MASK (0x1U) #define USB_HWDEVICE_DC_SHIFT (0U) +/*! DC + * 0b1..Supported + * 0b0..Not supported + */ #define USB_HWDEVICE_DC(x) (((uint32_t)(((uint32_t)(x)) << USB_HWDEVICE_DC_SHIFT)) & USB_HWDEVICE_DC_MASK) #define USB_HWDEVICE_DEVEP_MASK (0x3EU) #define USB_HWDEVICE_DEVEP_SHIFT (1U) #define USB_HWDEVICE_DEVEP(x) (((uint32_t)(((uint32_t)(x)) << USB_HWDEVICE_DEVEP_SHIFT)) & USB_HWDEVICE_DEVEP_MASK) +/*! @} */ /*! @name HWTXBUF - TX Buffer Hardware Parameters */ +/*! @{ */ #define USB_HWTXBUF_TXBURST_MASK (0xFFU) #define USB_HWTXBUF_TXBURST_SHIFT (0U) #define USB_HWTXBUF_TXBURST(x) (((uint32_t)(((uint32_t)(x)) << USB_HWTXBUF_TXBURST_SHIFT)) & USB_HWTXBUF_TXBURST_MASK) #define USB_HWTXBUF_TXCHANADD_MASK (0xFF0000U) #define USB_HWTXBUF_TXCHANADD_SHIFT (16U) #define USB_HWTXBUF_TXCHANADD(x) (((uint32_t)(((uint32_t)(x)) << USB_HWTXBUF_TXCHANADD_SHIFT)) & USB_HWTXBUF_TXCHANADD_MASK) +/*! @} */ /*! @name HWRXBUF - RX Buffer Hardware Parameters */ +/*! @{ */ #define USB_HWRXBUF_RXBURST_MASK (0xFFU) #define USB_HWRXBUF_RXBURST_SHIFT (0U) #define USB_HWRXBUF_RXBURST(x) (((uint32_t)(((uint32_t)(x)) << USB_HWRXBUF_RXBURST_SHIFT)) & USB_HWRXBUF_RXBURST_MASK) #define USB_HWRXBUF_RXADD_MASK (0xFF00U) #define USB_HWRXBUF_RXADD_SHIFT (8U) #define USB_HWRXBUF_RXADD(x) (((uint32_t)(((uint32_t)(x)) << USB_HWRXBUF_RXADD_SHIFT)) & USB_HWRXBUF_RXADD_MASK) +/*! @} */ /*! @name GPTIMER0LD - General Purpose Timer #0 Load */ +/*! @{ */ #define USB_GPTIMER0LD_GPTLD_MASK (0xFFFFFFU) #define USB_GPTIMER0LD_GPTLD_SHIFT (0U) #define USB_GPTIMER0LD_GPTLD(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER0LD_GPTLD_SHIFT)) & USB_GPTIMER0LD_GPTLD_MASK) +/*! @} */ /*! @name GPTIMER0CTRL - General Purpose Timer #0 Controller */ +/*! @{ */ #define USB_GPTIMER0CTRL_GPTCNT_MASK (0xFFFFFFU) #define USB_GPTIMER0CTRL_GPTCNT_SHIFT (0U) #define USB_GPTIMER0CTRL_GPTCNT(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER0CTRL_GPTCNT_SHIFT)) & USB_GPTIMER0CTRL_GPTCNT_MASK) #define USB_GPTIMER0CTRL_GPTMODE_MASK (0x1000000U) #define USB_GPTIMER0CTRL_GPTMODE_SHIFT (24U) +/*! GPTMODE + * 0b0..One Shot Mode + * 0b1..Repeat Mode + */ #define USB_GPTIMER0CTRL_GPTMODE(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER0CTRL_GPTMODE_SHIFT)) & USB_GPTIMER0CTRL_GPTMODE_MASK) #define USB_GPTIMER0CTRL_GPTRST_MASK (0x40000000U) #define USB_GPTIMER0CTRL_GPTRST_SHIFT (30U) +/*! GPTRST + * 0b0..No action + * 0b1..Load counter value from GPTLD bits in n_GPTIMER0LD + */ #define USB_GPTIMER0CTRL_GPTRST(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER0CTRL_GPTRST_SHIFT)) & USB_GPTIMER0CTRL_GPTRST_MASK) #define USB_GPTIMER0CTRL_GPTRUN_MASK (0x80000000U) #define USB_GPTIMER0CTRL_GPTRUN_SHIFT (31U) +/*! GPTRUN + * 0b0..Stop counting + * 0b1..Run + */ #define USB_GPTIMER0CTRL_GPTRUN(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER0CTRL_GPTRUN_SHIFT)) & USB_GPTIMER0CTRL_GPTRUN_MASK) +/*! @} */ /*! @name GPTIMER1LD - General Purpose Timer #1 Load */ +/*! @{ */ #define USB_GPTIMER1LD_GPTLD_MASK (0xFFFFFFU) #define USB_GPTIMER1LD_GPTLD_SHIFT (0U) #define USB_GPTIMER1LD_GPTLD(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER1LD_GPTLD_SHIFT)) & USB_GPTIMER1LD_GPTLD_MASK) +/*! @} */ /*! @name GPTIMER1CTRL - General Purpose Timer #1 Controller */ +/*! @{ */ #define USB_GPTIMER1CTRL_GPTCNT_MASK (0xFFFFFFU) #define USB_GPTIMER1CTRL_GPTCNT_SHIFT (0U) #define USB_GPTIMER1CTRL_GPTCNT(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER1CTRL_GPTCNT_SHIFT)) & USB_GPTIMER1CTRL_GPTCNT_MASK) #define USB_GPTIMER1CTRL_GPTMODE_MASK (0x1000000U) #define USB_GPTIMER1CTRL_GPTMODE_SHIFT (24U) +/*! GPTMODE + * 0b0..One Shot Mode + * 0b1..Repeat Mode + */ #define USB_GPTIMER1CTRL_GPTMODE(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER1CTRL_GPTMODE_SHIFT)) & USB_GPTIMER1CTRL_GPTMODE_MASK) #define USB_GPTIMER1CTRL_GPTRST_MASK (0x40000000U) #define USB_GPTIMER1CTRL_GPTRST_SHIFT (30U) +/*! GPTRST + * 0b0..No action + * 0b1..Load counter value from GPTLD bits in USB_n_GPTIMER0LD + */ #define USB_GPTIMER1CTRL_GPTRST(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER1CTRL_GPTRST_SHIFT)) & USB_GPTIMER1CTRL_GPTRST_MASK) #define USB_GPTIMER1CTRL_GPTRUN_MASK (0x80000000U) #define USB_GPTIMER1CTRL_GPTRUN_SHIFT (31U) +/*! GPTRUN + * 0b0..Stop counting + * 0b1..Run + */ #define USB_GPTIMER1CTRL_GPTRUN(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER1CTRL_GPTRUN_SHIFT)) & USB_GPTIMER1CTRL_GPTRUN_MASK) +/*! @} */ /*! @name SBUSCFG - System Bus Config */ +/*! @{ */ #define USB_SBUSCFG_AHBBRST_MASK (0x7U) #define USB_SBUSCFG_AHBBRST_SHIFT (0U) +/*! AHBBRST + * 0b000..Incremental burst of unspecified length only + * 0b001..INCR4 burst, then single transfer + * 0b010..INCR8 burst, INCR4 burst, then single transfer + * 0b011..INCR16 burst, INCR8 burst, INCR4 burst, then single transfer + * 0b100..Reserved, don't use + * 0b101..INCR4 burst, then incremental burst of unspecified length + * 0b110..INCR8 burst, INCR4 burst, then incremental burst of unspecified length + * 0b111..INCR16 burst, INCR8 burst, INCR4 burst, then incremental burst of unspecified length + */ #define USB_SBUSCFG_AHBBRST(x) (((uint32_t)(((uint32_t)(x)) << USB_SBUSCFG_AHBBRST_SHIFT)) & USB_SBUSCFG_AHBBRST_MASK) +/*! @} */ /*! @name CAPLENGTH - Capability Registers Length */ +/*! @{ */ #define USB_CAPLENGTH_CAPLENGTH_MASK (0xFFU) #define USB_CAPLENGTH_CAPLENGTH_SHIFT (0U) #define USB_CAPLENGTH_CAPLENGTH(x) (((uint8_t)(((uint8_t)(x)) << USB_CAPLENGTH_CAPLENGTH_SHIFT)) & USB_CAPLENGTH_CAPLENGTH_MASK) +/*! @} */ /*! @name HCIVERSION - Host Controller Interface Version */ +/*! @{ */ #define USB_HCIVERSION_HCIVERSION_MASK (0xFFFFU) #define USB_HCIVERSION_HCIVERSION_SHIFT (0U) #define USB_HCIVERSION_HCIVERSION(x) (((uint16_t)(((uint16_t)(x)) << USB_HCIVERSION_HCIVERSION_SHIFT)) & USB_HCIVERSION_HCIVERSION_MASK) +/*! @} */ /*! @name HCSPARAMS - Host Controller Structural Parameters */ +/*! @{ */ #define USB_HCSPARAMS_N_PORTS_MASK (0xFU) #define USB_HCSPARAMS_N_PORTS_SHIFT (0U) #define USB_HCSPARAMS_N_PORTS(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_N_PORTS_SHIFT)) & USB_HCSPARAMS_N_PORTS_MASK) @@ -19934,6 +32282,10 @@ typedef struct { #define USB_HCSPARAMS_N_PCC(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_N_PCC_SHIFT)) & USB_HCSPARAMS_N_PCC_MASK) #define USB_HCSPARAMS_N_CC_MASK (0xF000U) #define USB_HCSPARAMS_N_CC_SHIFT (12U) +/*! N_CC + * 0b0000..There is no internal Companion Controller and port-ownership hand-off is not supported. + * 0b0001..There are internal companion controller(s) and port-ownership hand-offs is supported. + */ #define USB_HCSPARAMS_N_CC(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_N_CC_SHIFT)) & USB_HCSPARAMS_N_CC_MASK) #define USB_HCSPARAMS_PI_MASK (0x10000U) #define USB_HCSPARAMS_PI_SHIFT (16U) @@ -19944,8 +32296,10 @@ typedef struct { #define USB_HCSPARAMS_N_TT_MASK (0xF000000U) #define USB_HCSPARAMS_N_TT_SHIFT (24U) #define USB_HCSPARAMS_N_TT(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_N_TT_SHIFT)) & USB_HCSPARAMS_N_TT_MASK) +/*! @} */ /*! @name HCCPARAMS - Host Controller Capability Parameters */ +/*! @{ */ #define USB_HCCPARAMS_ADC_MASK (0x1U) #define USB_HCCPARAMS_ADC_SHIFT (0U) #define USB_HCCPARAMS_ADC(x) (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS_ADC_SHIFT)) & USB_HCCPARAMS_ADC_MASK) @@ -19961,13 +32315,17 @@ typedef struct { #define USB_HCCPARAMS_EECP_MASK (0xFF00U) #define USB_HCCPARAMS_EECP_SHIFT (8U) #define USB_HCCPARAMS_EECP(x) (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS_EECP_SHIFT)) & USB_HCCPARAMS_EECP_MASK) +/*! @} */ /*! @name DCIVERSION - Device Controller Interface Version */ +/*! @{ */ #define USB_DCIVERSION_DCIVERSION_MASK (0xFFFFU) #define USB_DCIVERSION_DCIVERSION_SHIFT (0U) #define USB_DCIVERSION_DCIVERSION(x) (((uint16_t)(((uint16_t)(x)) << USB_DCIVERSION_DCIVERSION_SHIFT)) & USB_DCIVERSION_DCIVERSION_MASK) +/*! @} */ /*! @name DCCPARAMS - Device Controller Capability Parameters */ +/*! @{ */ #define USB_DCCPARAMS_DEN_MASK (0x1FU) #define USB_DCCPARAMS_DEN_SHIFT (0U) #define USB_DCCPARAMS_DEN(x) (((uint32_t)(((uint32_t)(x)) << USB_DCCPARAMS_DEN_SHIFT)) & USB_DCCPARAMS_DEN_MASK) @@ -19977,8 +32335,10 @@ typedef struct { #define USB_DCCPARAMS_HC_MASK (0x100U) #define USB_DCCPARAMS_HC_SHIFT (8U) #define USB_DCCPARAMS_HC(x) (((uint32_t)(((uint32_t)(x)) << USB_DCCPARAMS_HC_SHIFT)) & USB_DCCPARAMS_HC_MASK) +/*! @} */ /*! @name USBCMD - USB Command Register */ +/*! @{ */ #define USB_USBCMD_RS_MASK (0x1U) #define USB_USBCMD_RS_SHIFT (0U) #define USB_USBCMD_RS(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_RS_SHIFT)) & USB_USBCMD_RS_MASK) @@ -19990,9 +32350,17 @@ typedef struct { #define USB_USBCMD_FS_1(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_FS_1_SHIFT)) & USB_USBCMD_FS_1_MASK) #define USB_USBCMD_PSE_MASK (0x10U) #define USB_USBCMD_PSE_SHIFT (4U) +/*! PSE + * 0b0..Do not process the Periodic Schedule + * 0b1..Use the PERIODICLISTBASE register to access the Periodic Schedule. + */ #define USB_USBCMD_PSE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_PSE_SHIFT)) & USB_USBCMD_PSE_MASK) #define USB_USBCMD_ASE_MASK (0x20U) #define USB_USBCMD_ASE_SHIFT (5U) +/*! ASE + * 0b0..Do not process the Asynchronous Schedule. + * 0b1..Use the ASYNCLISTADDR register to access the Asynchronous Schedule. + */ #define USB_USBCMD_ASE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_ASE_SHIFT)) & USB_USBCMD_ASE_MASK) #define USB_USBCMD_IAA_MASK (0x40U) #define USB_USBCMD_IAA_SHIFT (6U) @@ -20011,12 +32379,28 @@ typedef struct { #define USB_USBCMD_SUTW(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_SUTW_SHIFT)) & USB_USBCMD_SUTW_MASK) #define USB_USBCMD_FS_2_MASK (0x8000U) #define USB_USBCMD_FS_2_SHIFT (15U) +/*! FS_2 + * 0b0..1024 elements (4096 bytes) Default value + * 0b1..512 elements (2048 bytes) + */ #define USB_USBCMD_FS_2(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_FS_2_SHIFT)) & USB_USBCMD_FS_2_MASK) #define USB_USBCMD_ITC_MASK (0xFF0000U) #define USB_USBCMD_ITC_SHIFT (16U) +/*! ITC + * 0b00000000..Immediate (no threshold) + * 0b00000001..1 micro-frame + * 0b00000010..2 micro-frames + * 0b00000100..4 micro-frames + * 0b00001000..8 micro-frames + * 0b00010000..16 micro-frames + * 0b00100000..32 micro-frames + * 0b01000000..64 micro-frames + */ #define USB_USBCMD_ITC(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_ITC_SHIFT)) & USB_USBCMD_ITC_MASK) +/*! @} */ /*! @name USBSTS - USB Status Register */ +/*! @{ */ #define USB_USBSTS_UI_MASK (0x1U) #define USB_USBSTS_UI_SHIFT (0U) #define USB_USBSTS_UI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_UI_SHIFT)) & USB_USBSTS_UI_MASK) @@ -20068,8 +32452,10 @@ typedef struct { #define USB_USBSTS_TI1_MASK (0x2000000U) #define USB_USBSTS_TI1_SHIFT (25U) #define USB_USBSTS_TI1(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_TI1_SHIFT)) & USB_USBSTS_TI1_MASK) +/*! @} */ /*! @name USBINTR - Interrupt Enable Register */ +/*! @{ */ #define USB_USBINTR_UE_MASK (0x1U) #define USB_USBINTR_UE_SHIFT (0U) #define USB_USBINTR_UE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_UE_SHIFT)) & USB_USBINTR_UE_MASK) @@ -20115,44 +32501,68 @@ typedef struct { #define USB_USBINTR_TIE1_MASK (0x2000000U) #define USB_USBINTR_TIE1_SHIFT (25U) #define USB_USBINTR_TIE1(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_TIE1_SHIFT)) & USB_USBINTR_TIE1_MASK) +/*! @} */ /*! @name FRINDEX - USB Frame Index */ +/*! @{ */ #define USB_FRINDEX_FRINDEX_MASK (0x3FFFU) #define USB_FRINDEX_FRINDEX_SHIFT (0U) +/*! FRINDEX + * 0b00000000000000..(1024) 12 + * 0b00000000000001..(512) 11 + * 0b00000000000010..(256) 10 + * 0b00000000000011..(128) 9 + * 0b00000000000100..(64) 8 + * 0b00000000000101..(32) 7 + * 0b00000000000110..(16) 6 + * 0b00000000000111..(8) 5 + */ #define USB_FRINDEX_FRINDEX(x) (((uint32_t)(((uint32_t)(x)) << USB_FRINDEX_FRINDEX_SHIFT)) & USB_FRINDEX_FRINDEX_MASK) +/*! @} */ /*! @name DEVICEADDR - Device Address */ +/*! @{ */ #define USB_DEVICEADDR_USBADRA_MASK (0x1000000U) #define USB_DEVICEADDR_USBADRA_SHIFT (24U) #define USB_DEVICEADDR_USBADRA(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVICEADDR_USBADRA_SHIFT)) & USB_DEVICEADDR_USBADRA_MASK) #define USB_DEVICEADDR_USBADR_MASK (0xFE000000U) #define USB_DEVICEADDR_USBADR_SHIFT (25U) #define USB_DEVICEADDR_USBADR(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVICEADDR_USBADR_SHIFT)) & USB_DEVICEADDR_USBADR_MASK) +/*! @} */ /*! @name PERIODICLISTBASE - Frame List Base Address */ +/*! @{ */ #define USB_PERIODICLISTBASE_BASEADR_MASK (0xFFFFF000U) #define USB_PERIODICLISTBASE_BASEADR_SHIFT (12U) #define USB_PERIODICLISTBASE_BASEADR(x) (((uint32_t)(((uint32_t)(x)) << USB_PERIODICLISTBASE_BASEADR_SHIFT)) & USB_PERIODICLISTBASE_BASEADR_MASK) +/*! @} */ /*! @name ASYNCLISTADDR - Next Asynch. Address */ +/*! @{ */ #define USB_ASYNCLISTADDR_ASYBASE_MASK (0xFFFFFFE0U) #define USB_ASYNCLISTADDR_ASYBASE_SHIFT (5U) #define USB_ASYNCLISTADDR_ASYBASE(x) (((uint32_t)(((uint32_t)(x)) << USB_ASYNCLISTADDR_ASYBASE_SHIFT)) & USB_ASYNCLISTADDR_ASYBASE_MASK) +/*! @} */ /*! @name ENDPTLISTADDR - Endpoint List Address */ +/*! @{ */ #define USB_ENDPTLISTADDR_EPBASE_MASK (0xFFFFF800U) #define USB_ENDPTLISTADDR_EPBASE_SHIFT (11U) #define USB_ENDPTLISTADDR_EPBASE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTLISTADDR_EPBASE_SHIFT)) & USB_ENDPTLISTADDR_EPBASE_MASK) +/*! @} */ /*! @name BURSTSIZE - Programmable Burst Size */ +/*! @{ */ #define USB_BURSTSIZE_RXPBURST_MASK (0xFFU) #define USB_BURSTSIZE_RXPBURST_SHIFT (0U) #define USB_BURSTSIZE_RXPBURST(x) (((uint32_t)(((uint32_t)(x)) << USB_BURSTSIZE_RXPBURST_SHIFT)) & USB_BURSTSIZE_RXPBURST_MASK) #define USB_BURSTSIZE_TXPBURST_MASK (0x1FF00U) #define USB_BURSTSIZE_TXPBURST_SHIFT (8U) #define USB_BURSTSIZE_TXPBURST(x) (((uint32_t)(((uint32_t)(x)) << USB_BURSTSIZE_TXPBURST_SHIFT)) & USB_BURSTSIZE_TXPBURST_MASK) +/*! @} */ /*! @name TXFILLTUNING - TX FIFO Fill Tuning */ +/*! @{ */ #define USB_TXFILLTUNING_TXSCHOH_MASK (0xFFU) #define USB_TXFILLTUNING_TXSCHOH_SHIFT (0U) #define USB_TXFILLTUNING_TXSCHOH(x) (((uint32_t)(((uint32_t)(x)) << USB_TXFILLTUNING_TXSCHOH_SHIFT)) & USB_TXFILLTUNING_TXSCHOH_MASK) @@ -20162,29 +32572,41 @@ typedef struct { #define USB_TXFILLTUNING_TXFIFOTHRES_MASK (0x3F0000U) #define USB_TXFILLTUNING_TXFIFOTHRES_SHIFT (16U) #define USB_TXFILLTUNING_TXFIFOTHRES(x) (((uint32_t)(((uint32_t)(x)) << USB_TXFILLTUNING_TXFIFOTHRES_SHIFT)) & USB_TXFILLTUNING_TXFIFOTHRES_MASK) +/*! @} */ /*! @name ENDPTNAK - Endpoint NAK */ +/*! @{ */ #define USB_ENDPTNAK_EPRN_MASK (0xFFU) #define USB_ENDPTNAK_EPRN_SHIFT (0U) #define USB_ENDPTNAK_EPRN(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTNAK_EPRN_SHIFT)) & USB_ENDPTNAK_EPRN_MASK) #define USB_ENDPTNAK_EPTN_MASK (0xFF0000U) #define USB_ENDPTNAK_EPTN_SHIFT (16U) #define USB_ENDPTNAK_EPTN(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTNAK_EPTN_SHIFT)) & USB_ENDPTNAK_EPTN_MASK) +/*! @} */ /*! @name ENDPTNAKEN - Endpoint NAK Enable */ +/*! @{ */ #define USB_ENDPTNAKEN_EPRNE_MASK (0xFFU) #define USB_ENDPTNAKEN_EPRNE_SHIFT (0U) #define USB_ENDPTNAKEN_EPRNE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTNAKEN_EPRNE_SHIFT)) & USB_ENDPTNAKEN_EPRNE_MASK) #define USB_ENDPTNAKEN_EPTNE_MASK (0xFF0000U) #define USB_ENDPTNAKEN_EPTNE_SHIFT (16U) #define USB_ENDPTNAKEN_EPTNE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTNAKEN_EPTNE_SHIFT)) & USB_ENDPTNAKEN_EPTNE_MASK) +/*! @} */ /*! @name CONFIGFLAG - Configure Flag Register */ +/*! @{ */ #define USB_CONFIGFLAG_CF_MASK (0x1U) #define USB_CONFIGFLAG_CF_SHIFT (0U) +/*! CF + * 0b0..Port routing control logic default-routes each port to an implementation dependent classic host controller. + * 0b1..Port routing control logic default-routes all ports to this host controller. + */ #define USB_CONFIGFLAG_CF(x) (((uint32_t)(((uint32_t)(x)) << USB_CONFIGFLAG_CF_SHIFT)) & USB_CONFIGFLAG_CF_MASK) +/*! @} */ /*! @name PORTSC1 - Port Status & Control */ +/*! @{ */ #define USB_PORTSC1_CCS_MASK (0x1U) #define USB_PORTSC1_CCS_SHIFT (0U) #define USB_PORTSC1_CCS(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_CCS_SHIFT)) & USB_PORTSC1_CCS_MASK) @@ -20199,6 +32621,10 @@ typedef struct { #define USB_PORTSC1_PEC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PEC_SHIFT)) & USB_PORTSC1_PEC_MASK) #define USB_PORTSC1_OCA_MASK (0x10U) #define USB_PORTSC1_OCA_SHIFT (4U) +/*! OCA + * 0b1..This port currently has an over-current condition + * 0b0..This port does not have an over-current condition. + */ #define USB_PORTSC1_OCA(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_OCA_SHIFT)) & USB_PORTSC1_OCA_MASK) #define USB_PORTSC1_OCC_MASK (0x20U) #define USB_PORTSC1_OCC_SHIFT (5U) @@ -20217,6 +32643,12 @@ typedef struct { #define USB_PORTSC1_HSP(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_HSP_SHIFT)) & USB_PORTSC1_HSP_MASK) #define USB_PORTSC1_LS_MASK (0xC00U) #define USB_PORTSC1_LS_SHIFT (10U) +/*! LS + * 0b00..SE0 + * 0b10..J-state + * 0b01..K-state + * 0b11..Undefined + */ #define USB_PORTSC1_LS(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_LS_SHIFT)) & USB_PORTSC1_LS_MASK) #define USB_PORTSC1_PP_MASK (0x1000U) #define USB_PORTSC1_PP_SHIFT (12U) @@ -20226,9 +32658,25 @@ typedef struct { #define USB_PORTSC1_PO(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PO_SHIFT)) & USB_PORTSC1_PO_MASK) #define USB_PORTSC1_PIC_MASK (0xC000U) #define USB_PORTSC1_PIC_SHIFT (14U) +/*! PIC + * 0b00..Port indicators are off + * 0b01..Amber + * 0b10..Green + * 0b11..Undefined + */ #define USB_PORTSC1_PIC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PIC_SHIFT)) & USB_PORTSC1_PIC_MASK) #define USB_PORTSC1_PTC_MASK (0xF0000U) #define USB_PORTSC1_PTC_SHIFT (16U) +/*! PTC + * 0b0000..TEST_MODE_DISABLE + * 0b0001..J_STATE + * 0b0010..K_STATE + * 0b0011..SE0 (host) / NAK (device) + * 0b0100..Packet + * 0b0101..FORCE_ENABLE_HS + * 0b0110..FORCE_ENABLE_FS + * 0b0111..FORCE_ENABLE_LS + */ #define USB_PORTSC1_PTC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PTC_SHIFT)) & USB_PORTSC1_PTC_MASK) #define USB_PORTSC1_WKCN_MASK (0x100000U) #define USB_PORTSC1_WKCN_SHIFT (20U) @@ -20241,18 +32689,36 @@ typedef struct { #define USB_PORTSC1_WKOC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_WKOC_SHIFT)) & USB_PORTSC1_WKOC_MASK) #define USB_PORTSC1_PHCD_MASK (0x800000U) #define USB_PORTSC1_PHCD_SHIFT (23U) +/*! PHCD + * 0b1..Disable PHY clock + * 0b0..Enable PHY clock + */ #define USB_PORTSC1_PHCD(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PHCD_SHIFT)) & USB_PORTSC1_PHCD_MASK) #define USB_PORTSC1_PFSC_MASK (0x1000000U) #define USB_PORTSC1_PFSC_SHIFT (24U) +/*! PFSC + * 0b1..Forced to full speed + * 0b0..Normal operation + */ #define USB_PORTSC1_PFSC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PFSC_SHIFT)) & USB_PORTSC1_PFSC_MASK) #define USB_PORTSC1_PTS_2_MASK (0x2000000U) #define USB_PORTSC1_PTS_2_SHIFT (25U) #define USB_PORTSC1_PTS_2(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PTS_2_SHIFT)) & USB_PORTSC1_PTS_2_MASK) #define USB_PORTSC1_PSPD_MASK (0xC000000U) #define USB_PORTSC1_PSPD_SHIFT (26U) +/*! PSPD + * 0b00..Full Speed + * 0b01..Low Speed + * 0b10..High Speed + * 0b11..Undefined + */ #define USB_PORTSC1_PSPD(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PSPD_SHIFT)) & USB_PORTSC1_PSPD_MASK) #define USB_PORTSC1_PTW_MASK (0x10000000U) #define USB_PORTSC1_PTW_SHIFT (28U) +/*! PTW + * 0b0..Select the 8-bit UTMI interface [60MHz] + * 0b1..Select the 16-bit UTMI interface [30MHz] + */ #define USB_PORTSC1_PTW(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PTW_SHIFT)) & USB_PORTSC1_PTW_MASK) #define USB_PORTSC1_STS_MASK (0x20000000U) #define USB_PORTSC1_STS_SHIFT (29U) @@ -20260,8 +32726,10 @@ typedef struct { #define USB_PORTSC1_PTS_1_MASK (0xC0000000U) #define USB_PORTSC1_PTS_1_SHIFT (30U) #define USB_PORTSC1_PTS_1(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PTS_1_SHIFT)) & USB_PORTSC1_PTS_1_MASK) +/*! @} */ /*! @name OTGSC - On-The-Go Status & control */ +/*! @{ */ #define USB_OTGSC_VD_MASK (0x1U) #define USB_OTGSC_VD_SHIFT (0U) #define USB_OTGSC_VD(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_VD_SHIFT)) & USB_OTGSC_VD_MASK) @@ -20340,59 +32808,87 @@ typedef struct { #define USB_OTGSC_DPIE_MASK (0x40000000U) #define USB_OTGSC_DPIE_SHIFT (30U) #define USB_OTGSC_DPIE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_DPIE_SHIFT)) & USB_OTGSC_DPIE_MASK) +/*! @} */ /*! @name USBMODE - USB Device Mode */ +/*! @{ */ #define USB_USBMODE_CM_MASK (0x3U) #define USB_USBMODE_CM_SHIFT (0U) +/*! CM + * 0b00..Idle [Default for combination host/device] + * 0b01..Reserved + * 0b10..Device Controller [Default for device only controller] + * 0b11..Host Controller [Default for host only controller] + */ #define USB_USBMODE_CM(x) (((uint32_t)(((uint32_t)(x)) << USB_USBMODE_CM_SHIFT)) & USB_USBMODE_CM_MASK) #define USB_USBMODE_ES_MASK (0x4U) #define USB_USBMODE_ES_SHIFT (2U) +/*! ES + * 0b0..Little Endian [Default] + * 0b1..Big Endian + */ #define USB_USBMODE_ES(x) (((uint32_t)(((uint32_t)(x)) << USB_USBMODE_ES_SHIFT)) & USB_USBMODE_ES_MASK) #define USB_USBMODE_SLOM_MASK (0x8U) #define USB_USBMODE_SLOM_SHIFT (3U) +/*! SLOM + * 0b0..Setup Lockouts On (default); + * 0b1..Setup Lockouts Off (DCD requires use of Setup Data Buffer Tripwire in USBCMDUSB Command Register . + */ #define USB_USBMODE_SLOM(x) (((uint32_t)(((uint32_t)(x)) << USB_USBMODE_SLOM_SHIFT)) & USB_USBMODE_SLOM_MASK) #define USB_USBMODE_SDIS_MASK (0x10U) #define USB_USBMODE_SDIS_SHIFT (4U) #define USB_USBMODE_SDIS(x) (((uint32_t)(((uint32_t)(x)) << USB_USBMODE_SDIS_SHIFT)) & USB_USBMODE_SDIS_MASK) +/*! @} */ /*! @name ENDPTSETUPSTAT - Endpoint Setup Status */ +/*! @{ */ #define USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_MASK (0xFFFFU) #define USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_SHIFT (0U) #define USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_SHIFT)) & USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_MASK) +/*! @} */ /*! @name ENDPTPRIME - Endpoint Prime */ +/*! @{ */ #define USB_ENDPTPRIME_PERB_MASK (0xFFU) #define USB_ENDPTPRIME_PERB_SHIFT (0U) #define USB_ENDPTPRIME_PERB(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTPRIME_PERB_SHIFT)) & USB_ENDPTPRIME_PERB_MASK) #define USB_ENDPTPRIME_PETB_MASK (0xFF0000U) #define USB_ENDPTPRIME_PETB_SHIFT (16U) #define USB_ENDPTPRIME_PETB(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTPRIME_PETB_SHIFT)) & USB_ENDPTPRIME_PETB_MASK) +/*! @} */ /*! @name ENDPTFLUSH - Endpoint Flush */ +/*! @{ */ #define USB_ENDPTFLUSH_FERB_MASK (0xFFU) #define USB_ENDPTFLUSH_FERB_SHIFT (0U) #define USB_ENDPTFLUSH_FERB(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTFLUSH_FERB_SHIFT)) & USB_ENDPTFLUSH_FERB_MASK) #define USB_ENDPTFLUSH_FETB_MASK (0xFF0000U) #define USB_ENDPTFLUSH_FETB_SHIFT (16U) #define USB_ENDPTFLUSH_FETB(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTFLUSH_FETB_SHIFT)) & USB_ENDPTFLUSH_FETB_MASK) +/*! @} */ /*! @name ENDPTSTAT - Endpoint Status */ +/*! @{ */ #define USB_ENDPTSTAT_ERBR_MASK (0xFFU) #define USB_ENDPTSTAT_ERBR_SHIFT (0U) #define USB_ENDPTSTAT_ERBR(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTSTAT_ERBR_SHIFT)) & USB_ENDPTSTAT_ERBR_MASK) #define USB_ENDPTSTAT_ETBR_MASK (0xFF0000U) #define USB_ENDPTSTAT_ETBR_SHIFT (16U) #define USB_ENDPTSTAT_ETBR(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTSTAT_ETBR_SHIFT)) & USB_ENDPTSTAT_ETBR_MASK) +/*! @} */ /*! @name ENDPTCOMPLETE - Endpoint Complete */ +/*! @{ */ #define USB_ENDPTCOMPLETE_ERCE_MASK (0xFFU) #define USB_ENDPTCOMPLETE_ERCE_SHIFT (0U) #define USB_ENDPTCOMPLETE_ERCE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCOMPLETE_ERCE_SHIFT)) & USB_ENDPTCOMPLETE_ERCE_MASK) #define USB_ENDPTCOMPLETE_ETCE_MASK (0xFF0000U) #define USB_ENDPTCOMPLETE_ETCE_SHIFT (16U) #define USB_ENDPTCOMPLETE_ETCE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCOMPLETE_ETCE_SHIFT)) & USB_ENDPTCOMPLETE_ETCE_MASK) +/*! @} */ /*! @name ENDPTCTRL0 - Endpoint Control0 */ +/*! @{ */ #define USB_ENDPTCTRL0_RXS_MASK (0x1U) #define USB_ENDPTCTRL0_RXS_SHIFT (0U) #define USB_ENDPTCTRL0_RXS(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_RXS_SHIFT)) & USB_ENDPTCTRL0_RXS_MASK) @@ -20411,8 +32907,10 @@ typedef struct { #define USB_ENDPTCTRL0_TXE_MASK (0x800000U) #define USB_ENDPTCTRL0_TXE_SHIFT (23U) #define USB_ENDPTCTRL0_TXE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_TXE_SHIFT)) & USB_ENDPTCTRL0_TXE_MASK) +/*! @} */ /*! @name ENDPTCTRL - Endpoint Control 1..Endpoint Control 7 */ +/*! @{ */ #define USB_ENDPTCTRL_RXS_MASK (0x1U) #define USB_ENDPTCTRL_RXS_SHIFT (0U) #define USB_ENDPTCTRL_RXS(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXS_SHIFT)) & USB_ENDPTCTRL_RXS_MASK) @@ -20449,6 +32947,7 @@ typedef struct { #define USB_ENDPTCTRL_TXE_MASK (0x800000U) #define USB_ENDPTCTRL_TXE_SHIFT (23U) #define USB_ENDPTCTRL_TXE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXE_SHIFT)) & USB_ENDPTCTRL_TXE_MASK) +/*! @} */ /* The count of USB_ENDPTCTRL */ #define USB_ENDPTCTRL_COUNT (7U) @@ -21078,41 +33577,89 @@ typedef struct { */ /*! @name USB_OTGn_CTRL - USB OTG1 Control Register..USB OTG2 Control Register */ +/*! @{ */ #define USBNC_USB_OTGn_CTRL_OVER_CUR_DIS_MASK (0x80U) #define USBNC_USB_OTGn_CTRL_OVER_CUR_DIS_SHIFT (7U) +/*! OVER_CUR_DIS + * 0b1..Disables overcurrent detection + * 0b0..Enables overcurrent detection + */ #define USBNC_USB_OTGn_CTRL_OVER_CUR_DIS(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_OVER_CUR_DIS_SHIFT)) & USBNC_USB_OTGn_CTRL_OVER_CUR_DIS_MASK) #define USBNC_USB_OTGn_CTRL_OVER_CUR_POL_MASK (0x100U) #define USBNC_USB_OTGn_CTRL_OVER_CUR_POL_SHIFT (8U) +/*! OVER_CUR_POL + * 0b1..Low active (low on this signal represents an overcurrent condition) + * 0b0..High active (high on this signal represents an overcurrent condition) + */ #define USBNC_USB_OTGn_CTRL_OVER_CUR_POL(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_OVER_CUR_POL_SHIFT)) & USBNC_USB_OTGn_CTRL_OVER_CUR_POL_MASK) #define USBNC_USB_OTGn_CTRL_PWR_POL_MASK (0x200U) #define USBNC_USB_OTGn_CTRL_PWR_POL_SHIFT (9U) +/*! PWR_POL + * 0b1..PMIC Power Pin is High active. + * 0b0..PMIC Power Pin is Low active. + */ #define USBNC_USB_OTGn_CTRL_PWR_POL(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_PWR_POL_SHIFT)) & USBNC_USB_OTGn_CTRL_PWR_POL_MASK) #define USBNC_USB_OTGn_CTRL_WIE_MASK (0x400U) #define USBNC_USB_OTGn_CTRL_WIE_SHIFT (10U) +/*! WIE + * 0b1..Interrupt Enabled + * 0b0..Interrupt Disabled + */ #define USBNC_USB_OTGn_CTRL_WIE(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_WIE_SHIFT)) & USBNC_USB_OTGn_CTRL_WIE_MASK) #define USBNC_USB_OTGn_CTRL_WKUP_SW_EN_MASK (0x4000U) #define USBNC_USB_OTGn_CTRL_WKUP_SW_EN_SHIFT (14U) +/*! WKUP_SW_EN + * 0b1..Enable + * 0b0..Disable + */ #define USBNC_USB_OTGn_CTRL_WKUP_SW_EN(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_WKUP_SW_EN_SHIFT)) & USBNC_USB_OTGn_CTRL_WKUP_SW_EN_MASK) #define USBNC_USB_OTGn_CTRL_WKUP_SW_MASK (0x8000U) #define USBNC_USB_OTGn_CTRL_WKUP_SW_SHIFT (15U) +/*! WKUP_SW + * 0b1..Force wake-up + * 0b0..Inactive + */ #define USBNC_USB_OTGn_CTRL_WKUP_SW(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_WKUP_SW_SHIFT)) & USBNC_USB_OTGn_CTRL_WKUP_SW_MASK) #define USBNC_USB_OTGn_CTRL_WKUP_ID_EN_MASK (0x10000U) #define USBNC_USB_OTGn_CTRL_WKUP_ID_EN_SHIFT (16U) +/*! WKUP_ID_EN + * 0b1..Enable + * 0b0..Disable + */ #define USBNC_USB_OTGn_CTRL_WKUP_ID_EN(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_WKUP_ID_EN_SHIFT)) & USBNC_USB_OTGn_CTRL_WKUP_ID_EN_MASK) #define USBNC_USB_OTGn_CTRL_WKUP_VBUS_EN_MASK (0x20000U) #define USBNC_USB_OTGn_CTRL_WKUP_VBUS_EN_SHIFT (17U) +/*! WKUP_VBUS_EN + * 0b1..Enable + * 0b0..Disable + */ #define USBNC_USB_OTGn_CTRL_WKUP_VBUS_EN(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_WKUP_VBUS_EN_SHIFT)) & USBNC_USB_OTGn_CTRL_WKUP_VBUS_EN_MASK) #define USBNC_USB_OTGn_CTRL_WKUP_DPDM_EN_MASK (0x20000000U) #define USBNC_USB_OTGn_CTRL_WKUP_DPDM_EN_SHIFT (29U) +/*! WKUP_DPDM_EN + * 0b1..(Default) DPDM changes wake-up to be enabled, it is for device only. + * 0b0..DPDM changes wake-up to be disabled only when VBUS is 0. + */ #define USBNC_USB_OTGn_CTRL_WKUP_DPDM_EN(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_WKUP_DPDM_EN_SHIFT)) & USBNC_USB_OTGn_CTRL_WKUP_DPDM_EN_MASK) #define USBNC_USB_OTGn_CTRL_WIR_MASK (0x80000000U) #define USBNC_USB_OTGn_CTRL_WIR_SHIFT (31U) +/*! WIR + * 0b1..Wake-up Interrupt Request received + * 0b0..No wake-up interrupt request received + */ #define USBNC_USB_OTGn_CTRL_WIR(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_WIR_SHIFT)) & USBNC_USB_OTGn_CTRL_WIR_MASK) +/*! @} */ /*! @name USB_OTGn_PHY_CTRL_0 - OTG1 UTMI PHY Control 0 Register..OTG2 UTMI PHY Control 0 Register */ +/*! @{ */ #define USBNC_USB_OTGn_PHY_CTRL_0_UTMI_CLK_VLD_MASK (0x80000000U) #define USBNC_USB_OTGn_PHY_CTRL_0_UTMI_CLK_VLD_SHIFT (31U) +/*! UTMI_CLK_VLD + * 0b1..Valid + * 0b0..Invalid + */ #define USBNC_USB_OTGn_PHY_CTRL_0_UTMI_CLK_VLD(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_PHY_CTRL_0_UTMI_CLK_VLD_SHIFT)) & USBNC_USB_OTGn_PHY_CTRL_0_UTMI_CLK_VLD_MASK) +/*! @} */ /*! @@ -21191,6 +33738,7 @@ typedef struct { */ /*! @name PWD - USB PHY Power-Down Register */ +/*! @{ */ #define USBPHY_PWD_RSVD0_MASK (0x3FFU) #define USBPHY_PWD_RSVD0_SHIFT (0U) #define USBPHY_PWD_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RSVD0_SHIFT)) & USBPHY_PWD_RSVD0_MASK) @@ -21221,8 +33769,10 @@ typedef struct { #define USBPHY_PWD_RSVD2_MASK (0xFFE00000U) #define USBPHY_PWD_RSVD2_SHIFT (21U) #define USBPHY_PWD_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RSVD2_SHIFT)) & USBPHY_PWD_RSVD2_MASK) +/*! @} */ /*! @name PWD_SET - USB PHY Power-Down Register */ +/*! @{ */ #define USBPHY_PWD_SET_RSVD0_MASK (0x3FFU) #define USBPHY_PWD_SET_RSVD0_SHIFT (0U) #define USBPHY_PWD_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RSVD0_SHIFT)) & USBPHY_PWD_SET_RSVD0_MASK) @@ -21253,8 +33803,10 @@ typedef struct { #define USBPHY_PWD_SET_RSVD2_MASK (0xFFE00000U) #define USBPHY_PWD_SET_RSVD2_SHIFT (21U) #define USBPHY_PWD_SET_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RSVD2_SHIFT)) & USBPHY_PWD_SET_RSVD2_MASK) +/*! @} */ /*! @name PWD_CLR - USB PHY Power-Down Register */ +/*! @{ */ #define USBPHY_PWD_CLR_RSVD0_MASK (0x3FFU) #define USBPHY_PWD_CLR_RSVD0_SHIFT (0U) #define USBPHY_PWD_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RSVD0_SHIFT)) & USBPHY_PWD_CLR_RSVD0_MASK) @@ -21285,8 +33837,10 @@ typedef struct { #define USBPHY_PWD_CLR_RSVD2_MASK (0xFFE00000U) #define USBPHY_PWD_CLR_RSVD2_SHIFT (21U) #define USBPHY_PWD_CLR_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RSVD2_SHIFT)) & USBPHY_PWD_CLR_RSVD2_MASK) +/*! @} */ /*! @name PWD_TOG - USB PHY Power-Down Register */ +/*! @{ */ #define USBPHY_PWD_TOG_RSVD0_MASK (0x3FFU) #define USBPHY_PWD_TOG_RSVD0_SHIFT (0U) #define USBPHY_PWD_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RSVD0_SHIFT)) & USBPHY_PWD_TOG_RSVD0_MASK) @@ -21317,8 +33871,10 @@ typedef struct { #define USBPHY_PWD_TOG_RSVD2_MASK (0xFFE00000U) #define USBPHY_PWD_TOG_RSVD2_SHIFT (21U) #define USBPHY_PWD_TOG_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RSVD2_SHIFT)) & USBPHY_PWD_TOG_RSVD2_MASK) +/*! @} */ /*! @name TX - USB PHY Transmitter Control Register */ +/*! @{ */ #define USBPHY_TX_D_CAL_MASK (0xFU) #define USBPHY_TX_D_CAL_SHIFT (0U) #define USBPHY_TX_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_D_CAL_SHIFT)) & USBPHY_TX_D_CAL_MASK) @@ -21343,8 +33899,10 @@ typedef struct { #define USBPHY_TX_RSVD5_MASK (0xE0000000U) #define USBPHY_TX_RSVD5_SHIFT (29U) #define USBPHY_TX_RSVD5(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_RSVD5_SHIFT)) & USBPHY_TX_RSVD5_MASK) +/*! @} */ /*! @name TX_SET - USB PHY Transmitter Control Register */ +/*! @{ */ #define USBPHY_TX_SET_D_CAL_MASK (0xFU) #define USBPHY_TX_SET_D_CAL_SHIFT (0U) #define USBPHY_TX_SET_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_D_CAL_SHIFT)) & USBPHY_TX_SET_D_CAL_MASK) @@ -21369,8 +33927,10 @@ typedef struct { #define USBPHY_TX_SET_RSVD5_MASK (0xE0000000U) #define USBPHY_TX_SET_RSVD5_SHIFT (29U) #define USBPHY_TX_SET_RSVD5(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_RSVD5_SHIFT)) & USBPHY_TX_SET_RSVD5_MASK) +/*! @} */ /*! @name TX_CLR - USB PHY Transmitter Control Register */ +/*! @{ */ #define USBPHY_TX_CLR_D_CAL_MASK (0xFU) #define USBPHY_TX_CLR_D_CAL_SHIFT (0U) #define USBPHY_TX_CLR_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_D_CAL_SHIFT)) & USBPHY_TX_CLR_D_CAL_MASK) @@ -21395,8 +33955,10 @@ typedef struct { #define USBPHY_TX_CLR_RSVD5_MASK (0xE0000000U) #define USBPHY_TX_CLR_RSVD5_SHIFT (29U) #define USBPHY_TX_CLR_RSVD5(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_RSVD5_SHIFT)) & USBPHY_TX_CLR_RSVD5_MASK) +/*! @} */ /*! @name TX_TOG - USB PHY Transmitter Control Register */ +/*! @{ */ #define USBPHY_TX_TOG_D_CAL_MASK (0xFU) #define USBPHY_TX_TOG_D_CAL_SHIFT (0U) #define USBPHY_TX_TOG_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_D_CAL_SHIFT)) & USBPHY_TX_TOG_D_CAL_MASK) @@ -21421,8 +33983,10 @@ typedef struct { #define USBPHY_TX_TOG_RSVD5_MASK (0xE0000000U) #define USBPHY_TX_TOG_RSVD5_SHIFT (29U) #define USBPHY_TX_TOG_RSVD5(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_RSVD5_SHIFT)) & USBPHY_TX_TOG_RSVD5_MASK) +/*! @} */ /*! @name RX - USB PHY Receiver Control Register */ +/*! @{ */ #define USBPHY_RX_ENVADJ_MASK (0x7U) #define USBPHY_RX_ENVADJ_SHIFT (0U) #define USBPHY_RX_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_ENVADJ_SHIFT)) & USBPHY_RX_ENVADJ_MASK) @@ -21441,8 +34005,10 @@ typedef struct { #define USBPHY_RX_RSVD2_MASK (0xFF800000U) #define USBPHY_RX_RSVD2_SHIFT (23U) #define USBPHY_RX_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_RSVD2_SHIFT)) & USBPHY_RX_RSVD2_MASK) +/*! @} */ /*! @name RX_SET - USB PHY Receiver Control Register */ +/*! @{ */ #define USBPHY_RX_SET_ENVADJ_MASK (0x7U) #define USBPHY_RX_SET_ENVADJ_SHIFT (0U) #define USBPHY_RX_SET_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_ENVADJ_SHIFT)) & USBPHY_RX_SET_ENVADJ_MASK) @@ -21461,8 +34027,10 @@ typedef struct { #define USBPHY_RX_SET_RSVD2_MASK (0xFF800000U) #define USBPHY_RX_SET_RSVD2_SHIFT (23U) #define USBPHY_RX_SET_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_RSVD2_SHIFT)) & USBPHY_RX_SET_RSVD2_MASK) +/*! @} */ /*! @name RX_CLR - USB PHY Receiver Control Register */ +/*! @{ */ #define USBPHY_RX_CLR_ENVADJ_MASK (0x7U) #define USBPHY_RX_CLR_ENVADJ_SHIFT (0U) #define USBPHY_RX_CLR_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_ENVADJ_SHIFT)) & USBPHY_RX_CLR_ENVADJ_MASK) @@ -21481,8 +34049,10 @@ typedef struct { #define USBPHY_RX_CLR_RSVD2_MASK (0xFF800000U) #define USBPHY_RX_CLR_RSVD2_SHIFT (23U) #define USBPHY_RX_CLR_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_RSVD2_SHIFT)) & USBPHY_RX_CLR_RSVD2_MASK) +/*! @} */ /*! @name RX_TOG - USB PHY Receiver Control Register */ +/*! @{ */ #define USBPHY_RX_TOG_ENVADJ_MASK (0x7U) #define USBPHY_RX_TOG_ENVADJ_SHIFT (0U) #define USBPHY_RX_TOG_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_ENVADJ_SHIFT)) & USBPHY_RX_TOG_ENVADJ_MASK) @@ -21501,8 +34071,10 @@ typedef struct { #define USBPHY_RX_TOG_RSVD2_MASK (0xFF800000U) #define USBPHY_RX_TOG_RSVD2_SHIFT (23U) #define USBPHY_RX_TOG_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_RSVD2_SHIFT)) & USBPHY_RX_TOG_RSVD2_MASK) +/*! @} */ /*! @name CTRL - USB PHY General Control Register */ +/*! @{ */ #define USBPHY_CTRL_ENOTG_ID_CHG_IRQ_MASK (0x1U) #define USBPHY_CTRL_ENOTG_ID_CHG_IRQ_SHIFT (0U) #define USBPHY_CTRL_ENOTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENOTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_ENOTG_ID_CHG_IRQ_MASK) @@ -21596,8 +34168,10 @@ typedef struct { #define USBPHY_CTRL_SFTRST_MASK (0x80000000U) #define USBPHY_CTRL_SFTRST_SHIFT (31U) #define USBPHY_CTRL_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SFTRST_SHIFT)) & USBPHY_CTRL_SFTRST_MASK) +/*! @} */ /*! @name CTRL_SET - USB PHY General Control Register */ +/*! @{ */ #define USBPHY_CTRL_SET_ENOTG_ID_CHG_IRQ_MASK (0x1U) #define USBPHY_CTRL_SET_ENOTG_ID_CHG_IRQ_SHIFT (0U) #define USBPHY_CTRL_SET_ENOTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENOTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_SET_ENOTG_ID_CHG_IRQ_MASK) @@ -21691,8 +34265,10 @@ typedef struct { #define USBPHY_CTRL_SET_SFTRST_MASK (0x80000000U) #define USBPHY_CTRL_SET_SFTRST_SHIFT (31U) #define USBPHY_CTRL_SET_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_SFTRST_SHIFT)) & USBPHY_CTRL_SET_SFTRST_MASK) +/*! @} */ /*! @name CTRL_CLR - USB PHY General Control Register */ +/*! @{ */ #define USBPHY_CTRL_CLR_ENOTG_ID_CHG_IRQ_MASK (0x1U) #define USBPHY_CTRL_CLR_ENOTG_ID_CHG_IRQ_SHIFT (0U) #define USBPHY_CTRL_CLR_ENOTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENOTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_CLR_ENOTG_ID_CHG_IRQ_MASK) @@ -21786,8 +34362,10 @@ typedef struct { #define USBPHY_CTRL_CLR_SFTRST_MASK (0x80000000U) #define USBPHY_CTRL_CLR_SFTRST_SHIFT (31U) #define USBPHY_CTRL_CLR_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_SFTRST_SHIFT)) & USBPHY_CTRL_CLR_SFTRST_MASK) +/*! @} */ /*! @name CTRL_TOG - USB PHY General Control Register */ +/*! @{ */ #define USBPHY_CTRL_TOG_ENOTG_ID_CHG_IRQ_MASK (0x1U) #define USBPHY_CTRL_TOG_ENOTG_ID_CHG_IRQ_SHIFT (0U) #define USBPHY_CTRL_TOG_ENOTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENOTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_TOG_ENOTG_ID_CHG_IRQ_MASK) @@ -21881,8 +34459,10 @@ typedef struct { #define USBPHY_CTRL_TOG_SFTRST_MASK (0x80000000U) #define USBPHY_CTRL_TOG_SFTRST_SHIFT (31U) #define USBPHY_CTRL_TOG_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_SFTRST_SHIFT)) & USBPHY_CTRL_TOG_SFTRST_MASK) +/*! @} */ /*! @name STATUS - USB PHY Status Register */ +/*! @{ */ #define USBPHY_STATUS_RSVD0_MASK (0x7U) #define USBPHY_STATUS_RSVD0_SHIFT (0U) #define USBPHY_STATUS_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_RSVD0_SHIFT)) & USBPHY_STATUS_RSVD0_MASK) @@ -21910,8 +34490,10 @@ typedef struct { #define USBPHY_STATUS_RSVD4_MASK (0xFFFFF800U) #define USBPHY_STATUS_RSVD4_SHIFT (11U) #define USBPHY_STATUS_RSVD4(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_RSVD4_SHIFT)) & USBPHY_STATUS_RSVD4_MASK) +/*! @} */ /*! @name DEBUG - USB PHY Debug Register */ +/*! @{ */ #define USBPHY_DEBUG_OTGIDPIOLOCK_MASK (0x1U) #define USBPHY_DEBUG_OTGIDPIOLOCK_SHIFT (0U) #define USBPHY_DEBUG_OTGIDPIOLOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG_OTGIDPIOLOCK_MASK) @@ -21957,8 +34539,10 @@ typedef struct { #define USBPHY_DEBUG_RSVD3_MASK (0x80000000U) #define USBPHY_DEBUG_RSVD3_SHIFT (31U) #define USBPHY_DEBUG_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_RSVD3_SHIFT)) & USBPHY_DEBUG_RSVD3_MASK) +/*! @} */ /*! @name DEBUG_SET - USB PHY Debug Register */ +/*! @{ */ #define USBPHY_DEBUG_SET_OTGIDPIOLOCK_MASK (0x1U) #define USBPHY_DEBUG_SET_OTGIDPIOLOCK_SHIFT (0U) #define USBPHY_DEBUG_SET_OTGIDPIOLOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG_SET_OTGIDPIOLOCK_MASK) @@ -22004,8 +34588,10 @@ typedef struct { #define USBPHY_DEBUG_SET_RSVD3_MASK (0x80000000U) #define USBPHY_DEBUG_SET_RSVD3_SHIFT (31U) #define USBPHY_DEBUG_SET_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_RSVD3_SHIFT)) & USBPHY_DEBUG_SET_RSVD3_MASK) +/*! @} */ /*! @name DEBUG_CLR - USB PHY Debug Register */ +/*! @{ */ #define USBPHY_DEBUG_CLR_OTGIDPIOLOCK_MASK (0x1U) #define USBPHY_DEBUG_CLR_OTGIDPIOLOCK_SHIFT (0U) #define USBPHY_DEBUG_CLR_OTGIDPIOLOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG_CLR_OTGIDPIOLOCK_MASK) @@ -22051,8 +34637,10 @@ typedef struct { #define USBPHY_DEBUG_CLR_RSVD3_MASK (0x80000000U) #define USBPHY_DEBUG_CLR_RSVD3_SHIFT (31U) #define USBPHY_DEBUG_CLR_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_RSVD3_SHIFT)) & USBPHY_DEBUG_CLR_RSVD3_MASK) +/*! @} */ /*! @name DEBUG_TOG - USB PHY Debug Register */ +/*! @{ */ #define USBPHY_DEBUG_TOG_OTGIDPIOLOCK_MASK (0x1U) #define USBPHY_DEBUG_TOG_OTGIDPIOLOCK_SHIFT (0U) #define USBPHY_DEBUG_TOG_OTGIDPIOLOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG_TOG_OTGIDPIOLOCK_MASK) @@ -22098,8 +34686,10 @@ typedef struct { #define USBPHY_DEBUG_TOG_RSVD3_MASK (0x80000000U) #define USBPHY_DEBUG_TOG_RSVD3_SHIFT (31U) #define USBPHY_DEBUG_TOG_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_RSVD3_SHIFT)) & USBPHY_DEBUG_TOG_RSVD3_MASK) +/*! @} */ /*! @name DEBUG0_STATUS - UTMI Debug Status Register 0 */ +/*! @{ */ #define USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT_MASK (0xFFFFU) #define USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT_SHIFT (0U) #define USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT_SHIFT)) & USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT_MASK) @@ -22109,8 +34699,10 @@ typedef struct { #define USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_MASK (0xFC000000U) #define USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_SHIFT (26U) #define USBPHY_DEBUG0_STATUS_SQUELCH_COUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_SHIFT)) & USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_MASK) +/*! @} */ /*! @name DEBUG1 - UTMI Debug Status Register 1 */ +/*! @{ */ #define USBPHY_DEBUG1_RSVD0_MASK (0x1FFFU) #define USBPHY_DEBUG1_RSVD0_SHIFT (0U) #define USBPHY_DEBUG1_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_RSVD0_SHIFT)) & USBPHY_DEBUG1_RSVD0_MASK) @@ -22120,8 +34712,10 @@ typedef struct { #define USBPHY_DEBUG1_RSVD1_MASK (0xFFFF8000U) #define USBPHY_DEBUG1_RSVD1_SHIFT (15U) #define USBPHY_DEBUG1_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_RSVD1_SHIFT)) & USBPHY_DEBUG1_RSVD1_MASK) +/*! @} */ /*! @name DEBUG1_SET - UTMI Debug Status Register 1 */ +/*! @{ */ #define USBPHY_DEBUG1_SET_RSVD0_MASK (0x1FFFU) #define USBPHY_DEBUG1_SET_RSVD0_SHIFT (0U) #define USBPHY_DEBUG1_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_SET_RSVD0_SHIFT)) & USBPHY_DEBUG1_SET_RSVD0_MASK) @@ -22131,8 +34725,10 @@ typedef struct { #define USBPHY_DEBUG1_SET_RSVD1_MASK (0xFFFF8000U) #define USBPHY_DEBUG1_SET_RSVD1_SHIFT (15U) #define USBPHY_DEBUG1_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_SET_RSVD1_SHIFT)) & USBPHY_DEBUG1_SET_RSVD1_MASK) +/*! @} */ /*! @name DEBUG1_CLR - UTMI Debug Status Register 1 */ +/*! @{ */ #define USBPHY_DEBUG1_CLR_RSVD0_MASK (0x1FFFU) #define USBPHY_DEBUG1_CLR_RSVD0_SHIFT (0U) #define USBPHY_DEBUG1_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_CLR_RSVD0_SHIFT)) & USBPHY_DEBUG1_CLR_RSVD0_MASK) @@ -22142,8 +34738,10 @@ typedef struct { #define USBPHY_DEBUG1_CLR_RSVD1_MASK (0xFFFF8000U) #define USBPHY_DEBUG1_CLR_RSVD1_SHIFT (15U) #define USBPHY_DEBUG1_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_CLR_RSVD1_SHIFT)) & USBPHY_DEBUG1_CLR_RSVD1_MASK) +/*! @} */ /*! @name DEBUG1_TOG - UTMI Debug Status Register 1 */ +/*! @{ */ #define USBPHY_DEBUG1_TOG_RSVD0_MASK (0x1FFFU) #define USBPHY_DEBUG1_TOG_RSVD0_SHIFT (0U) #define USBPHY_DEBUG1_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_TOG_RSVD0_SHIFT)) & USBPHY_DEBUG1_TOG_RSVD0_MASK) @@ -22153,8 +34751,10 @@ typedef struct { #define USBPHY_DEBUG1_TOG_RSVD1_MASK (0xFFFF8000U) #define USBPHY_DEBUG1_TOG_RSVD1_SHIFT (15U) #define USBPHY_DEBUG1_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_TOG_RSVD1_SHIFT)) & USBPHY_DEBUG1_TOG_RSVD1_MASK) +/*! @} */ /*! @name VERSION - UTMI RTL Version */ +/*! @{ */ #define USBPHY_VERSION_STEP_MASK (0xFFFFU) #define USBPHY_VERSION_STEP_SHIFT (0U) #define USBPHY_VERSION_STEP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_VERSION_STEP_SHIFT)) & USBPHY_VERSION_STEP_MASK) @@ -22164,6 +34764,7 @@ typedef struct { #define USBPHY_VERSION_MAJOR_MASK (0xFF000000U) #define USBPHY_VERSION_MAJOR_SHIFT (24U) #define USBPHY_VERSION_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_VERSION_MAJOR_SHIFT)) & USBPHY_VERSION_MAJOR_MASK) +/*! @} */ /*! @@ -22243,8 +34844,19 @@ typedef struct { */ /*! @name VBUS_DETECT - USB VBUS Detect Register */ +/*! @{ */ #define USB_ANALOG_VBUS_DETECT_VBUSVALID_THRESH_MASK (0x7U) #define USB_ANALOG_VBUS_DETECT_VBUSVALID_THRESH_SHIFT (0U) +/*! VBUSVALID_THRESH + * 0b000..4.0V + * 0b001..4.1V + * 0b010..4.2V + * 0b011..4.3V + * 0b100..4.4V (default) + * 0b101..4.5V + * 0b110..4.6V + * 0b111..4.7V + */ #define USB_ANALOG_VBUS_DETECT_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_VBUSVALID_THRESH_SHIFT)) & USB_ANALOG_VBUS_DETECT_VBUSVALID_THRESH_MASK) #define USB_ANALOG_VBUS_DETECT_VBUSVALID_PWRUP_CMPS_MASK (0x100000U) #define USB_ANALOG_VBUS_DETECT_VBUSVALID_PWRUP_CMPS_SHIFT (20U) @@ -22255,13 +34867,25 @@ typedef struct { #define USB_ANALOG_VBUS_DETECT_CHARGE_VBUS_MASK (0x8000000U) #define USB_ANALOG_VBUS_DETECT_CHARGE_VBUS_SHIFT (27U) #define USB_ANALOG_VBUS_DETECT_CHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_CHARGE_VBUS_SHIFT)) & USB_ANALOG_VBUS_DETECT_CHARGE_VBUS_MASK) +/*! @} */ /* The count of USB_ANALOG_VBUS_DETECT */ #define USB_ANALOG_VBUS_DETECT_COUNT (2U) /*! @name VBUS_DETECT_SET - USB VBUS Detect Register */ +/*! @{ */ #define USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_THRESH_MASK (0x7U) #define USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_THRESH_SHIFT (0U) +/*! VBUSVALID_THRESH + * 0b000..4.0V + * 0b001..4.1V + * 0b010..4.2V + * 0b011..4.3V + * 0b100..4.4V (default) + * 0b101..4.5V + * 0b110..4.6V + * 0b111..4.7V + */ #define USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_THRESH_SHIFT)) & USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_THRESH_MASK) #define USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_PWRUP_CMPS_MASK (0x100000U) #define USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_PWRUP_CMPS_SHIFT (20U) @@ -22272,13 +34896,25 @@ typedef struct { #define USB_ANALOG_VBUS_DETECT_SET_CHARGE_VBUS_MASK (0x8000000U) #define USB_ANALOG_VBUS_DETECT_SET_CHARGE_VBUS_SHIFT (27U) #define USB_ANALOG_VBUS_DETECT_SET_CHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_SET_CHARGE_VBUS_SHIFT)) & USB_ANALOG_VBUS_DETECT_SET_CHARGE_VBUS_MASK) +/*! @} */ /* The count of USB_ANALOG_VBUS_DETECT_SET */ #define USB_ANALOG_VBUS_DETECT_SET_COUNT (2U) /*! @name VBUS_DETECT_CLR - USB VBUS Detect Register */ +/*! @{ */ #define USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_THRESH_MASK (0x7U) #define USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_THRESH_SHIFT (0U) +/*! VBUSVALID_THRESH + * 0b000..4.0V + * 0b001..4.1V + * 0b010..4.2V + * 0b011..4.3V + * 0b100..4.4V (default) + * 0b101..4.5V + * 0b110..4.6V + * 0b111..4.7V + */ #define USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_THRESH_SHIFT)) & USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_THRESH_MASK) #define USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_PWRUP_CMPS_MASK (0x100000U) #define USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_PWRUP_CMPS_SHIFT (20U) @@ -22289,13 +34925,25 @@ typedef struct { #define USB_ANALOG_VBUS_DETECT_CLR_CHARGE_VBUS_MASK (0x8000000U) #define USB_ANALOG_VBUS_DETECT_CLR_CHARGE_VBUS_SHIFT (27U) #define USB_ANALOG_VBUS_DETECT_CLR_CHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_CLR_CHARGE_VBUS_SHIFT)) & USB_ANALOG_VBUS_DETECT_CLR_CHARGE_VBUS_MASK) +/*! @} */ /* The count of USB_ANALOG_VBUS_DETECT_CLR */ #define USB_ANALOG_VBUS_DETECT_CLR_COUNT (2U) /*! @name VBUS_DETECT_TOG - USB VBUS Detect Register */ +/*! @{ */ #define USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_THRESH_MASK (0x7U) #define USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_THRESH_SHIFT (0U) +/*! VBUSVALID_THRESH + * 0b000..4.0V + * 0b001..4.1V + * 0b010..4.2V + * 0b011..4.3V + * 0b100..4.4V (default) + * 0b101..4.5V + * 0b110..4.6V + * 0b111..4.7V + */ #define USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_THRESH_SHIFT)) & USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_THRESH_MASK) #define USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_PWRUP_CMPS_MASK (0x100000U) #define USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_PWRUP_CMPS_SHIFT (20U) @@ -22306,67 +34954,125 @@ typedef struct { #define USB_ANALOG_VBUS_DETECT_TOG_CHARGE_VBUS_MASK (0x8000000U) #define USB_ANALOG_VBUS_DETECT_TOG_CHARGE_VBUS_SHIFT (27U) #define USB_ANALOG_VBUS_DETECT_TOG_CHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_TOG_CHARGE_VBUS_SHIFT)) & USB_ANALOG_VBUS_DETECT_TOG_CHARGE_VBUS_MASK) +/*! @} */ /* The count of USB_ANALOG_VBUS_DETECT_TOG */ #define USB_ANALOG_VBUS_DETECT_TOG_COUNT (2U) /*! @name CHRG_DETECT - USB Charger Detect Register */ +/*! @{ */ #define USB_ANALOG_CHRG_DETECT_CHK_CONTACT_MASK (0x40000U) #define USB_ANALOG_CHRG_DETECT_CHK_CONTACT_SHIFT (18U) +/*! CHK_CONTACT - Check the contact of USB plug + * 0b0..Do not check the contact of USB plug. + * 0b1..Check whether the USB plug has been in contact with each other + */ #define USB_ANALOG_CHRG_DETECT_CHK_CONTACT(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_CHK_CONTACT_SHIFT)) & USB_ANALOG_CHRG_DETECT_CHK_CONTACT_MASK) #define USB_ANALOG_CHRG_DETECT_CHK_CHRG_B_MASK (0x80000U) #define USB_ANALOG_CHRG_DETECT_CHK_CHRG_B_SHIFT (19U) +/*! CHK_CHRG_B - Check the charger connection + * 0b0..Check whether a charger (either a dedicated charger or a host charger) is connected to USB port. + * 0b1..Do not check whether a charger is connected to the USB port. + */ #define USB_ANALOG_CHRG_DETECT_CHK_CHRG_B(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_CHK_CHRG_B_SHIFT)) & USB_ANALOG_CHRG_DETECT_CHK_CHRG_B_MASK) #define USB_ANALOG_CHRG_DETECT_EN_B_MASK (0x100000U) #define USB_ANALOG_CHRG_DETECT_EN_B_SHIFT (20U) +/*! EN_B + * 0b0..Enable the charger detector. + * 0b1..Disable the charger detector. + */ #define USB_ANALOG_CHRG_DETECT_EN_B(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_EN_B_SHIFT)) & USB_ANALOG_CHRG_DETECT_EN_B_MASK) +/*! @} */ /* The count of USB_ANALOG_CHRG_DETECT */ #define USB_ANALOG_CHRG_DETECT_COUNT (2U) /*! @name CHRG_DETECT_SET - USB Charger Detect Register */ +/*! @{ */ #define USB_ANALOG_CHRG_DETECT_SET_CHK_CONTACT_MASK (0x40000U) #define USB_ANALOG_CHRG_DETECT_SET_CHK_CONTACT_SHIFT (18U) +/*! CHK_CONTACT - Check the contact of USB plug + * 0b0..Do not check the contact of USB plug. + * 0b1..Check whether the USB plug has been in contact with each other + */ #define USB_ANALOG_CHRG_DETECT_SET_CHK_CONTACT(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_SET_CHK_CONTACT_SHIFT)) & USB_ANALOG_CHRG_DETECT_SET_CHK_CONTACT_MASK) #define USB_ANALOG_CHRG_DETECT_SET_CHK_CHRG_B_MASK (0x80000U) #define USB_ANALOG_CHRG_DETECT_SET_CHK_CHRG_B_SHIFT (19U) +/*! CHK_CHRG_B - Check the charger connection + * 0b0..Check whether a charger (either a dedicated charger or a host charger) is connected to USB port. + * 0b1..Do not check whether a charger is connected to the USB port. + */ #define USB_ANALOG_CHRG_DETECT_SET_CHK_CHRG_B(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_SET_CHK_CHRG_B_SHIFT)) & USB_ANALOG_CHRG_DETECT_SET_CHK_CHRG_B_MASK) #define USB_ANALOG_CHRG_DETECT_SET_EN_B_MASK (0x100000U) #define USB_ANALOG_CHRG_DETECT_SET_EN_B_SHIFT (20U) +/*! EN_B + * 0b0..Enable the charger detector. + * 0b1..Disable the charger detector. + */ #define USB_ANALOG_CHRG_DETECT_SET_EN_B(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_SET_EN_B_SHIFT)) & USB_ANALOG_CHRG_DETECT_SET_EN_B_MASK) +/*! @} */ /* The count of USB_ANALOG_CHRG_DETECT_SET */ #define USB_ANALOG_CHRG_DETECT_SET_COUNT (2U) /*! @name CHRG_DETECT_CLR - USB Charger Detect Register */ +/*! @{ */ #define USB_ANALOG_CHRG_DETECT_CLR_CHK_CONTACT_MASK (0x40000U) #define USB_ANALOG_CHRG_DETECT_CLR_CHK_CONTACT_SHIFT (18U) +/*! CHK_CONTACT - Check the contact of USB plug + * 0b0..Do not check the contact of USB plug. + * 0b1..Check whether the USB plug has been in contact with each other + */ #define USB_ANALOG_CHRG_DETECT_CLR_CHK_CONTACT(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_CLR_CHK_CONTACT_SHIFT)) & USB_ANALOG_CHRG_DETECT_CLR_CHK_CONTACT_MASK) #define USB_ANALOG_CHRG_DETECT_CLR_CHK_CHRG_B_MASK (0x80000U) #define USB_ANALOG_CHRG_DETECT_CLR_CHK_CHRG_B_SHIFT (19U) +/*! CHK_CHRG_B - Check the charger connection + * 0b0..Check whether a charger (either a dedicated charger or a host charger) is connected to USB port. + * 0b1..Do not check whether a charger is connected to the USB port. + */ #define USB_ANALOG_CHRG_DETECT_CLR_CHK_CHRG_B(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_CLR_CHK_CHRG_B_SHIFT)) & USB_ANALOG_CHRG_DETECT_CLR_CHK_CHRG_B_MASK) #define USB_ANALOG_CHRG_DETECT_CLR_EN_B_MASK (0x100000U) #define USB_ANALOG_CHRG_DETECT_CLR_EN_B_SHIFT (20U) +/*! EN_B + * 0b0..Enable the charger detector. + * 0b1..Disable the charger detector. + */ #define USB_ANALOG_CHRG_DETECT_CLR_EN_B(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_CLR_EN_B_SHIFT)) & USB_ANALOG_CHRG_DETECT_CLR_EN_B_MASK) +/*! @} */ /* The count of USB_ANALOG_CHRG_DETECT_CLR */ #define USB_ANALOG_CHRG_DETECT_CLR_COUNT (2U) /*! @name CHRG_DETECT_TOG - USB Charger Detect Register */ +/*! @{ */ #define USB_ANALOG_CHRG_DETECT_TOG_CHK_CONTACT_MASK (0x40000U) #define USB_ANALOG_CHRG_DETECT_TOG_CHK_CONTACT_SHIFT (18U) +/*! CHK_CONTACT - Check the contact of USB plug + * 0b0..Do not check the contact of USB plug. + * 0b1..Check whether the USB plug has been in contact with each other + */ #define USB_ANALOG_CHRG_DETECT_TOG_CHK_CONTACT(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_TOG_CHK_CONTACT_SHIFT)) & USB_ANALOG_CHRG_DETECT_TOG_CHK_CONTACT_MASK) #define USB_ANALOG_CHRG_DETECT_TOG_CHK_CHRG_B_MASK (0x80000U) #define USB_ANALOG_CHRG_DETECT_TOG_CHK_CHRG_B_SHIFT (19U) +/*! CHK_CHRG_B - Check the charger connection + * 0b0..Check whether a charger (either a dedicated charger or a host charger) is connected to USB port. + * 0b1..Do not check whether a charger is connected to the USB port. + */ #define USB_ANALOG_CHRG_DETECT_TOG_CHK_CHRG_B(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_TOG_CHK_CHRG_B_SHIFT)) & USB_ANALOG_CHRG_DETECT_TOG_CHK_CHRG_B_MASK) #define USB_ANALOG_CHRG_DETECT_TOG_EN_B_MASK (0x100000U) #define USB_ANALOG_CHRG_DETECT_TOG_EN_B_SHIFT (20U) +/*! EN_B + * 0b0..Enable the charger detector. + * 0b1..Disable the charger detector. + */ #define USB_ANALOG_CHRG_DETECT_TOG_EN_B(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_TOG_EN_B_SHIFT)) & USB_ANALOG_CHRG_DETECT_TOG_EN_B_MASK) +/*! @} */ /* The count of USB_ANALOG_CHRG_DETECT_TOG */ #define USB_ANALOG_CHRG_DETECT_TOG_COUNT (2U) /*! @name VBUS_DETECT_STAT - USB VBUS Detect Status Register */ +/*! @{ */ #define USB_ANALOG_VBUS_DETECT_STAT_SESSEND_MASK (0x1U) #define USB_ANALOG_VBUS_DETECT_STAT_SESSEND_SHIFT (0U) #define USB_ANALOG_VBUS_DETECT_STAT_SESSEND(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_STAT_SESSEND_SHIFT)) & USB_ANALOG_VBUS_DETECT_STAT_SESSEND_MASK) @@ -22379,16 +35085,26 @@ typedef struct { #define USB_ANALOG_VBUS_DETECT_STAT_VBUS_VALID_MASK (0x8U) #define USB_ANALOG_VBUS_DETECT_STAT_VBUS_VALID_SHIFT (3U) #define USB_ANALOG_VBUS_DETECT_STAT_VBUS_VALID(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_STAT_VBUS_VALID_SHIFT)) & USB_ANALOG_VBUS_DETECT_STAT_VBUS_VALID_MASK) +/*! @} */ /* The count of USB_ANALOG_VBUS_DETECT_STAT */ #define USB_ANALOG_VBUS_DETECT_STAT_COUNT (2U) /*! @name CHRG_DETECT_STAT - USB Charger Detect Status Register */ +/*! @{ */ #define USB_ANALOG_CHRG_DETECT_STAT_PLUG_CONTACT_MASK (0x1U) #define USB_ANALOG_CHRG_DETECT_STAT_PLUG_CONTACT_SHIFT (0U) +/*! PLUG_CONTACT + * 0b0..The USB plug has not made contact. + * 0b1..The USB plug has made good contact. + */ #define USB_ANALOG_CHRG_DETECT_STAT_PLUG_CONTACT(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_STAT_PLUG_CONTACT_SHIFT)) & USB_ANALOG_CHRG_DETECT_STAT_PLUG_CONTACT_MASK) #define USB_ANALOG_CHRG_DETECT_STAT_CHRG_DETECTED_MASK (0x2U) #define USB_ANALOG_CHRG_DETECT_STAT_CHRG_DETECTED_SHIFT (1U) +/*! CHRG_DETECTED + * 0b0..The USB port is not connected to a charger. + * 0b1..A charger (either a dedicated charger or a host charger) is connected to the USB port. + */ #define USB_ANALOG_CHRG_DETECT_STAT_CHRG_DETECTED(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_STAT_CHRG_DETECTED_SHIFT)) & USB_ANALOG_CHRG_DETECT_STAT_CHRG_DETECTED_MASK) #define USB_ANALOG_CHRG_DETECT_STAT_DM_STATE_MASK (0x4U) #define USB_ANALOG_CHRG_DETECT_STAT_DM_STATE_SHIFT (2U) @@ -22396,11 +35112,13 @@ typedef struct { #define USB_ANALOG_CHRG_DETECT_STAT_DP_STATE_MASK (0x8U) #define USB_ANALOG_CHRG_DETECT_STAT_DP_STATE_SHIFT (3U) #define USB_ANALOG_CHRG_DETECT_STAT_DP_STATE(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_STAT_DP_STATE_SHIFT)) & USB_ANALOG_CHRG_DETECT_STAT_DP_STATE_MASK) +/*! @} */ /* The count of USB_ANALOG_CHRG_DETECT_STAT */ #define USB_ANALOG_CHRG_DETECT_STAT_COUNT (2U) /*! @name MISC - USB Misc Register */ +/*! @{ */ #define USB_ANALOG_MISC_HS_USE_EXTERNAL_R_MASK (0x1U) #define USB_ANALOG_MISC_HS_USE_EXTERNAL_R_SHIFT (0U) #define USB_ANALOG_MISC_HS_USE_EXTERNAL_R(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_HS_USE_EXTERNAL_R_SHIFT)) & USB_ANALOG_MISC_HS_USE_EXTERNAL_R_MASK) @@ -22410,11 +35128,13 @@ typedef struct { #define USB_ANALOG_MISC_EN_CLK_UTMI_MASK (0x40000000U) #define USB_ANALOG_MISC_EN_CLK_UTMI_SHIFT (30U) #define USB_ANALOG_MISC_EN_CLK_UTMI(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_EN_CLK_UTMI_SHIFT)) & USB_ANALOG_MISC_EN_CLK_UTMI_MASK) +/*! @} */ /* The count of USB_ANALOG_MISC */ #define USB_ANALOG_MISC_COUNT (2U) /*! @name MISC_SET - USB Misc Register */ +/*! @{ */ #define USB_ANALOG_MISC_SET_HS_USE_EXTERNAL_R_MASK (0x1U) #define USB_ANALOG_MISC_SET_HS_USE_EXTERNAL_R_SHIFT (0U) #define USB_ANALOG_MISC_SET_HS_USE_EXTERNAL_R(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_SET_HS_USE_EXTERNAL_R_SHIFT)) & USB_ANALOG_MISC_SET_HS_USE_EXTERNAL_R_MASK) @@ -22424,11 +35144,13 @@ typedef struct { #define USB_ANALOG_MISC_SET_EN_CLK_UTMI_MASK (0x40000000U) #define USB_ANALOG_MISC_SET_EN_CLK_UTMI_SHIFT (30U) #define USB_ANALOG_MISC_SET_EN_CLK_UTMI(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_SET_EN_CLK_UTMI_SHIFT)) & USB_ANALOG_MISC_SET_EN_CLK_UTMI_MASK) +/*! @} */ /* The count of USB_ANALOG_MISC_SET */ #define USB_ANALOG_MISC_SET_COUNT (2U) /*! @name MISC_CLR - USB Misc Register */ +/*! @{ */ #define USB_ANALOG_MISC_CLR_HS_USE_EXTERNAL_R_MASK (0x1U) #define USB_ANALOG_MISC_CLR_HS_USE_EXTERNAL_R_SHIFT (0U) #define USB_ANALOG_MISC_CLR_HS_USE_EXTERNAL_R(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_CLR_HS_USE_EXTERNAL_R_SHIFT)) & USB_ANALOG_MISC_CLR_HS_USE_EXTERNAL_R_MASK) @@ -22438,11 +35160,13 @@ typedef struct { #define USB_ANALOG_MISC_CLR_EN_CLK_UTMI_MASK (0x40000000U) #define USB_ANALOG_MISC_CLR_EN_CLK_UTMI_SHIFT (30U) #define USB_ANALOG_MISC_CLR_EN_CLK_UTMI(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_CLR_EN_CLK_UTMI_SHIFT)) & USB_ANALOG_MISC_CLR_EN_CLK_UTMI_MASK) +/*! @} */ /* The count of USB_ANALOG_MISC_CLR */ #define USB_ANALOG_MISC_CLR_COUNT (2U) /*! @name MISC_TOG - USB Misc Register */ +/*! @{ */ #define USB_ANALOG_MISC_TOG_HS_USE_EXTERNAL_R_MASK (0x1U) #define USB_ANALOG_MISC_TOG_HS_USE_EXTERNAL_R_SHIFT (0U) #define USB_ANALOG_MISC_TOG_HS_USE_EXTERNAL_R(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_TOG_HS_USE_EXTERNAL_R_SHIFT)) & USB_ANALOG_MISC_TOG_HS_USE_EXTERNAL_R_MASK) @@ -22452,20 +35176,20 @@ typedef struct { #define USB_ANALOG_MISC_TOG_EN_CLK_UTMI_MASK (0x40000000U) #define USB_ANALOG_MISC_TOG_EN_CLK_UTMI_SHIFT (30U) #define USB_ANALOG_MISC_TOG_EN_CLK_UTMI(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_TOG_EN_CLK_UTMI_SHIFT)) & USB_ANALOG_MISC_TOG_EN_CLK_UTMI_MASK) +/*! @} */ /* The count of USB_ANALOG_MISC_TOG */ #define USB_ANALOG_MISC_TOG_COUNT (2U) /*! @name DIGPROG - Chip Silicon Version */ -#define USB_ANALOG_DIGPROG_MINOR_MASK (0xFFU) -#define USB_ANALOG_DIGPROG_MINOR_SHIFT (0U) -#define USB_ANALOG_DIGPROG_MINOR(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_DIGPROG_MINOR_SHIFT)) & USB_ANALOG_DIGPROG_MINOR_MASK) -#define USB_ANALOG_DIGPROG_MAJOR_LOWER_MASK (0xFF00U) -#define USB_ANALOG_DIGPROG_MAJOR_LOWER_SHIFT (8U) -#define USB_ANALOG_DIGPROG_MAJOR_LOWER(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_DIGPROG_MAJOR_LOWER_SHIFT)) & USB_ANALOG_DIGPROG_MAJOR_LOWER_MASK) -#define USB_ANALOG_DIGPROG_MAJOR_UPPER_MASK (0xFF0000U) -#define USB_ANALOG_DIGPROG_MAJOR_UPPER_SHIFT (16U) -#define USB_ANALOG_DIGPROG_MAJOR_UPPER(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_DIGPROG_MAJOR_UPPER_SHIFT)) & USB_ANALOG_DIGPROG_MAJOR_UPPER_MASK) +/*! @{ */ +#define USB_ANALOG_DIGPROG_SILICON_REVISION_MASK (0xFFFFFFFFU) +#define USB_ANALOG_DIGPROG_SILICON_REVISION_SHIFT (0U) +/*! SILICON_REVISION + * 0b00000000011010100000000000000001..Silicon revision 1.1 + */ +#define USB_ANALOG_DIGPROG_SILICON_REVISION(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_DIGPROG_SILICON_REVISION_SHIFT)) & USB_ANALOG_DIGPROG_SILICON_REVISION_MASK) +/*! @} */ /*! @@ -22543,201 +35267,439 @@ typedef struct { */ /*! @name DS_ADDR - DMA System Address */ +/*! @{ */ #define USDHC_DS_ADDR_DS_ADDR_MASK (0xFFFFFFFFU) #define USDHC_DS_ADDR_DS_ADDR_SHIFT (0U) #define USDHC_DS_ADDR_DS_ADDR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DS_ADDR_DS_ADDR_SHIFT)) & USDHC_DS_ADDR_DS_ADDR_MASK) +/*! @} */ /*! @name BLK_ATT - Block Attributes */ +/*! @{ */ #define USDHC_BLK_ATT_BLKSIZE_MASK (0x1FFFU) #define USDHC_BLK_ATT_BLKSIZE_SHIFT (0U) +/*! BLKSIZE - Block Size + * 0b1000000000000..4096 Bytes + * 0b0100000000000..2048 Bytes + * 0b0001000000000..512 Bytes + * 0b0000111111111..511 Bytes + * 0b0000000000100..4 Bytes + * 0b0000000000011..3 Bytes + * 0b0000000000010..2 Bytes + * 0b0000000000001..1 Byte + * 0b0000000000000..No data transfer + */ #define USDHC_BLK_ATT_BLKSIZE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_BLK_ATT_BLKSIZE_SHIFT)) & USDHC_BLK_ATT_BLKSIZE_MASK) #define USDHC_BLK_ATT_BLKCNT_MASK (0xFFFF0000U) #define USDHC_BLK_ATT_BLKCNT_SHIFT (16U) +/*! BLKCNT - Block Count + * 0b1111111111111111..65535 blocks + * 0b0000000000000010..2 blocks + * 0b0000000000000001..1 block + * 0b0000000000000000..Stop Count + */ #define USDHC_BLK_ATT_BLKCNT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_BLK_ATT_BLKCNT_SHIFT)) & USDHC_BLK_ATT_BLKCNT_MASK) +/*! @} */ /*! @name CMD_ARG - Command Argument */ +/*! @{ */ #define USDHC_CMD_ARG_CMDARG_MASK (0xFFFFFFFFU) #define USDHC_CMD_ARG_CMDARG_SHIFT (0U) #define USDHC_CMD_ARG_CMDARG(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_ARG_CMDARG_SHIFT)) & USDHC_CMD_ARG_CMDARG_MASK) +/*! @} */ /*! @name CMD_XFR_TYP - Command Transfer Type */ +/*! @{ */ #define USDHC_CMD_XFR_TYP_RSPTYP_MASK (0x30000U) #define USDHC_CMD_XFR_TYP_RSPTYP_SHIFT (16U) +/*! RSPTYP - Response Type Select + * 0b00..No Response + * 0b01..Response Length 136 + * 0b10..Response Length 48 + * 0b11..Response Length 48, check Busy after response + */ #define USDHC_CMD_XFR_TYP_RSPTYP(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_RSPTYP_SHIFT)) & USDHC_CMD_XFR_TYP_RSPTYP_MASK) #define USDHC_CMD_XFR_TYP_CCCEN_MASK (0x80000U) #define USDHC_CMD_XFR_TYP_CCCEN_SHIFT (19U) +/*! CCCEN - Command CRC Check Enable + * 0b1..Enable + * 0b0..Disable + */ #define USDHC_CMD_XFR_TYP_CCCEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CCCEN_SHIFT)) & USDHC_CMD_XFR_TYP_CCCEN_MASK) #define USDHC_CMD_XFR_TYP_CICEN_MASK (0x100000U) #define USDHC_CMD_XFR_TYP_CICEN_SHIFT (20U) +/*! CICEN - Command Index Check Enable + * 0b1..Enable + * 0b0..Disable + */ #define USDHC_CMD_XFR_TYP_CICEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CICEN_SHIFT)) & USDHC_CMD_XFR_TYP_CICEN_MASK) #define USDHC_CMD_XFR_TYP_DPSEL_MASK (0x200000U) #define USDHC_CMD_XFR_TYP_DPSEL_SHIFT (21U) +/*! DPSEL - Data Present Select + * 0b1..Data Present + * 0b0..No Data Present + */ #define USDHC_CMD_XFR_TYP_DPSEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_DPSEL_SHIFT)) & USDHC_CMD_XFR_TYP_DPSEL_MASK) #define USDHC_CMD_XFR_TYP_CMDTYP_MASK (0xC00000U) #define USDHC_CMD_XFR_TYP_CMDTYP_SHIFT (22U) +/*! CMDTYP - Command Type + * 0b11..Abort CMD12, CMD52 for writing I/O Abort in CCCR + * 0b10..Resume CMD52 for writing Function Select in CCCR + * 0b01..Suspend CMD52 for writing Bus Suspend in CCCR + * 0b00..Normal Other commands + */ #define USDHC_CMD_XFR_TYP_CMDTYP(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CMDTYP_SHIFT)) & USDHC_CMD_XFR_TYP_CMDTYP_MASK) #define USDHC_CMD_XFR_TYP_CMDINX_MASK (0x3F000000U) #define USDHC_CMD_XFR_TYP_CMDINX_SHIFT (24U) #define USDHC_CMD_XFR_TYP_CMDINX(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CMDINX_SHIFT)) & USDHC_CMD_XFR_TYP_CMDINX_MASK) +/*! @} */ /*! @name CMD_RSP0 - Command Response0 */ +/*! @{ */ #define USDHC_CMD_RSP0_CMDRSP0_MASK (0xFFFFFFFFU) #define USDHC_CMD_RSP0_CMDRSP0_SHIFT (0U) #define USDHC_CMD_RSP0_CMDRSP0(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP0_CMDRSP0_SHIFT)) & USDHC_CMD_RSP0_CMDRSP0_MASK) +/*! @} */ /*! @name CMD_RSP1 - Command Response1 */ +/*! @{ */ #define USDHC_CMD_RSP1_CMDRSP1_MASK (0xFFFFFFFFU) #define USDHC_CMD_RSP1_CMDRSP1_SHIFT (0U) #define USDHC_CMD_RSP1_CMDRSP1(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP1_CMDRSP1_SHIFT)) & USDHC_CMD_RSP1_CMDRSP1_MASK) +/*! @} */ /*! @name CMD_RSP2 - Command Response2 */ +/*! @{ */ #define USDHC_CMD_RSP2_CMDRSP2_MASK (0xFFFFFFFFU) #define USDHC_CMD_RSP2_CMDRSP2_SHIFT (0U) #define USDHC_CMD_RSP2_CMDRSP2(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP2_CMDRSP2_SHIFT)) & USDHC_CMD_RSP2_CMDRSP2_MASK) +/*! @} */ /*! @name CMD_RSP3 - Command Response3 */ +/*! @{ */ #define USDHC_CMD_RSP3_CMDRSP3_MASK (0xFFFFFFFFU) #define USDHC_CMD_RSP3_CMDRSP3_SHIFT (0U) #define USDHC_CMD_RSP3_CMDRSP3(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP3_CMDRSP3_SHIFT)) & USDHC_CMD_RSP3_CMDRSP3_MASK) +/*! @} */ /*! @name DATA_BUFF_ACC_PORT - Data Buffer Access Port */ +/*! @{ */ #define USDHC_DATA_BUFF_ACC_PORT_DATCONT_MASK (0xFFFFFFFFU) #define USDHC_DATA_BUFF_ACC_PORT_DATCONT_SHIFT (0U) #define USDHC_DATA_BUFF_ACC_PORT_DATCONT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DATA_BUFF_ACC_PORT_DATCONT_SHIFT)) & USDHC_DATA_BUFF_ACC_PORT_DATCONT_MASK) +/*! @} */ /*! @name PRES_STATE - Present State */ +/*! @{ */ #define USDHC_PRES_STATE_CIHB_MASK (0x1U) #define USDHC_PRES_STATE_CIHB_SHIFT (0U) +/*! CIHB - Command Inhibit (CMD) + * 0b1..Cannot issue command + * 0b0..Can issue command using only CMD line + */ #define USDHC_PRES_STATE_CIHB(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CIHB_SHIFT)) & USDHC_PRES_STATE_CIHB_MASK) #define USDHC_PRES_STATE_CDIHB_MASK (0x2U) #define USDHC_PRES_STATE_CDIHB_SHIFT (1U) +/*! CDIHB - Command Inhibit (DATA) + * 0b1..Cannot issue command which uses the DATA line + * 0b0..Can issue command which uses the DATA line + */ #define USDHC_PRES_STATE_CDIHB(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CDIHB_SHIFT)) & USDHC_PRES_STATE_CDIHB_MASK) #define USDHC_PRES_STATE_DLA_MASK (0x4U) #define USDHC_PRES_STATE_DLA_SHIFT (2U) +/*! DLA - Data Line Active + * 0b1..DATA Line Active + * 0b0..DATA Line Inactive + */ #define USDHC_PRES_STATE_DLA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_DLA_SHIFT)) & USDHC_PRES_STATE_DLA_MASK) #define USDHC_PRES_STATE_SDSTB_MASK (0x8U) #define USDHC_PRES_STATE_SDSTB_SHIFT (3U) +/*! SDSTB - SD Clock Stable + * 0b1..Clock is stable. + * 0b0..Clock is changing frequency and not stable. + */ #define USDHC_PRES_STATE_SDSTB(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_SDSTB_SHIFT)) & USDHC_PRES_STATE_SDSTB_MASK) #define USDHC_PRES_STATE_IPGOFF_MASK (0x10U) #define USDHC_PRES_STATE_IPGOFF_SHIFT (4U) +/*! IPGOFF - IPG_CLK Gated Off Internally + * 0b1..IPG_CLK is gated off. + * 0b0..IPG_CLK is active. + */ #define USDHC_PRES_STATE_IPGOFF(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_IPGOFF_SHIFT)) & USDHC_PRES_STATE_IPGOFF_MASK) #define USDHC_PRES_STATE_HCKOFF_MASK (0x20U) #define USDHC_PRES_STATE_HCKOFF_SHIFT (5U) +/*! HCKOFF - HCLK Gated Off Internally + * 0b1..HCLK is gated off. + * 0b0..HCLK is active. + */ #define USDHC_PRES_STATE_HCKOFF(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_HCKOFF_SHIFT)) & USDHC_PRES_STATE_HCKOFF_MASK) #define USDHC_PRES_STATE_PEROFF_MASK (0x40U) #define USDHC_PRES_STATE_PEROFF_SHIFT (6U) +/*! PEROFF - IPG_PERCLK Gated Off Internally + * 0b1..IPG_PERCLK is gated off. + * 0b0..IPG_PERCLK is active. + */ #define USDHC_PRES_STATE_PEROFF(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_PEROFF_SHIFT)) & USDHC_PRES_STATE_PEROFF_MASK) #define USDHC_PRES_STATE_SDOFF_MASK (0x80U) #define USDHC_PRES_STATE_SDOFF_SHIFT (7U) +/*! SDOFF - SD Clock Gated Off Internally + * 0b1..SD Clock is gated off. + * 0b0..SD Clock is active. + */ #define USDHC_PRES_STATE_SDOFF(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_SDOFF_SHIFT)) & USDHC_PRES_STATE_SDOFF_MASK) #define USDHC_PRES_STATE_WTA_MASK (0x100U) #define USDHC_PRES_STATE_WTA_SHIFT (8U) +/*! WTA - Write Transfer Active + * 0b1..Transferring data + * 0b0..No valid data + */ #define USDHC_PRES_STATE_WTA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_WTA_SHIFT)) & USDHC_PRES_STATE_WTA_MASK) #define USDHC_PRES_STATE_RTA_MASK (0x200U) #define USDHC_PRES_STATE_RTA_SHIFT (9U) +/*! RTA - Read Transfer Active + * 0b1..Transferring data + * 0b0..No valid data + */ #define USDHC_PRES_STATE_RTA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_RTA_SHIFT)) & USDHC_PRES_STATE_RTA_MASK) #define USDHC_PRES_STATE_BWEN_MASK (0x400U) #define USDHC_PRES_STATE_BWEN_SHIFT (10U) +/*! BWEN - Buffer Write Enable + * 0b1..Write enable + * 0b0..Write disable + */ #define USDHC_PRES_STATE_BWEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_BWEN_SHIFT)) & USDHC_PRES_STATE_BWEN_MASK) #define USDHC_PRES_STATE_BREN_MASK (0x800U) #define USDHC_PRES_STATE_BREN_SHIFT (11U) +/*! BREN - Buffer Read Enable + * 0b1..Read enable + * 0b0..Read disable + */ #define USDHC_PRES_STATE_BREN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_BREN_SHIFT)) & USDHC_PRES_STATE_BREN_MASK) #define USDHC_PRES_STATE_RTR_MASK (0x1000U) #define USDHC_PRES_STATE_RTR_SHIFT (12U) +/*! RTR - Re-Tuning Request (only for SD3.0 SDR104 mode and EMMC HS200 mode) + * 0b1..Sampling clock needs re-tuning + * 0b0..Fixed or well tuned sampling clock + */ #define USDHC_PRES_STATE_RTR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_RTR_SHIFT)) & USDHC_PRES_STATE_RTR_MASK) #define USDHC_PRES_STATE_TSCD_MASK (0x8000U) #define USDHC_PRES_STATE_TSCD_SHIFT (15U) +/*! TSCD - Tape Select Change Done + * 0b1..Delay cell select change is finished. + * 0b0..Delay cell select change is not finished. + */ #define USDHC_PRES_STATE_TSCD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_TSCD_SHIFT)) & USDHC_PRES_STATE_TSCD_MASK) #define USDHC_PRES_STATE_CINST_MASK (0x10000U) #define USDHC_PRES_STATE_CINST_SHIFT (16U) +/*! CINST - Card Inserted + * 0b1..Card Inserted + * 0b0..Power on Reset or No Card + */ #define USDHC_PRES_STATE_CINST(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CINST_SHIFT)) & USDHC_PRES_STATE_CINST_MASK) #define USDHC_PRES_STATE_CDPL_MASK (0x40000U) #define USDHC_PRES_STATE_CDPL_SHIFT (18U) +/*! CDPL - Card Detect Pin Level + * 0b1..Card present (CD_B = 0) + * 0b0..No card present (CD_B = 1) + */ #define USDHC_PRES_STATE_CDPL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CDPL_SHIFT)) & USDHC_PRES_STATE_CDPL_MASK) #define USDHC_PRES_STATE_WPSPL_MASK (0x80000U) #define USDHC_PRES_STATE_WPSPL_SHIFT (19U) +/*! WPSPL - Write Protect Switch Pin Level + * 0b1..Write enabled (WP = 0) + * 0b0..Write protected (WP = 1) + */ #define USDHC_PRES_STATE_WPSPL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_WPSPL_SHIFT)) & USDHC_PRES_STATE_WPSPL_MASK) #define USDHC_PRES_STATE_CLSL_MASK (0x800000U) #define USDHC_PRES_STATE_CLSL_SHIFT (23U) #define USDHC_PRES_STATE_CLSL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CLSL_SHIFT)) & USDHC_PRES_STATE_CLSL_MASK) #define USDHC_PRES_STATE_DLSL_MASK (0xFF000000U) #define USDHC_PRES_STATE_DLSL_SHIFT (24U) +/*! DLSL - DATA[7:0] Line Signal Level + * 0b00000111..Data 7 line signal level + * 0b00000110..Data 6 line signal level + * 0b00000101..Data 5 line signal level + * 0b00000100..Data 4 line signal level + * 0b00000011..Data 3 line signal level + * 0b00000010..Data 2 line signal level + * 0b00000001..Data 1 line signal level + * 0b00000000..Data 0 line signal level + */ #define USDHC_PRES_STATE_DLSL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_DLSL_SHIFT)) & USDHC_PRES_STATE_DLSL_MASK) +/*! @} */ /*! @name PROT_CTRL - Protocol Control */ +/*! @{ */ #define USDHC_PROT_CTRL_LCTL_MASK (0x1U) #define USDHC_PROT_CTRL_LCTL_SHIFT (0U) +/*! LCTL - LED Control + * 0b1..LED on + * 0b0..LED off + */ #define USDHC_PROT_CTRL_LCTL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_LCTL_SHIFT)) & USDHC_PROT_CTRL_LCTL_MASK) #define USDHC_PROT_CTRL_DTW_MASK (0x6U) #define USDHC_PROT_CTRL_DTW_SHIFT (1U) +/*! DTW - Data Transfer Width + * 0b10..8-bit mode + * 0b01..4-bit mode + * 0b00..1-bit mode + * 0b11..Reserved + */ #define USDHC_PROT_CTRL_DTW(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_DTW_SHIFT)) & USDHC_PROT_CTRL_DTW_MASK) #define USDHC_PROT_CTRL_D3CD_MASK (0x8U) #define USDHC_PROT_CTRL_D3CD_SHIFT (3U) +/*! D3CD - DATA3 as Card Detection Pin + * 0b1..DATA3 as Card Detection Pin + * 0b0..DATA3 does not monitor Card Insertion + */ #define USDHC_PROT_CTRL_D3CD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_D3CD_SHIFT)) & USDHC_PROT_CTRL_D3CD_MASK) #define USDHC_PROT_CTRL_EMODE_MASK (0x30U) #define USDHC_PROT_CTRL_EMODE_SHIFT (4U) +/*! EMODE - Endian Mode + * 0b00..Big Endian Mode + * 0b01..Half Word Big Endian Mode + * 0b10..Little Endian Mode + * 0b11..Reserved + */ #define USDHC_PROT_CTRL_EMODE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_EMODE_SHIFT)) & USDHC_PROT_CTRL_EMODE_MASK) #define USDHC_PROT_CTRL_CDTL_MASK (0x40U) #define USDHC_PROT_CTRL_CDTL_SHIFT (6U) +/*! CDTL - Card Detect Test Level + * 0b1..Card Detect Test Level is 1, card inserted + * 0b0..Card Detect Test Level is 0, no card inserted + */ #define USDHC_PROT_CTRL_CDTL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_CDTL_SHIFT)) & USDHC_PROT_CTRL_CDTL_MASK) #define USDHC_PROT_CTRL_CDSS_MASK (0x80U) #define USDHC_PROT_CTRL_CDSS_SHIFT (7U) +/*! CDSS - Card Detect Signal Selection + * 0b1..Card Detection Test Level is selected (for test purpose). + * 0b0..Card Detection Level is selected (for normal purpose). + */ #define USDHC_PROT_CTRL_CDSS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_CDSS_SHIFT)) & USDHC_PROT_CTRL_CDSS_MASK) #define USDHC_PROT_CTRL_DMASEL_MASK (0x300U) #define USDHC_PROT_CTRL_DMASEL_SHIFT (8U) +/*! DMASEL - DMA Select + * 0b00..No DMA or Simple DMA is selected + * 0b01..ADMA1 is selected + * 0b10..ADMA2 is selected + * 0b11..reserved + */ #define USDHC_PROT_CTRL_DMASEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_DMASEL_SHIFT)) & USDHC_PROT_CTRL_DMASEL_MASK) #define USDHC_PROT_CTRL_SABGREQ_MASK (0x10000U) #define USDHC_PROT_CTRL_SABGREQ_SHIFT (16U) +/*! SABGREQ - Stop At Block Gap Request + * 0b1..Stop + * 0b0..Transfer + */ #define USDHC_PROT_CTRL_SABGREQ(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_SABGREQ_SHIFT)) & USDHC_PROT_CTRL_SABGREQ_MASK) #define USDHC_PROT_CTRL_CREQ_MASK (0x20000U) #define USDHC_PROT_CTRL_CREQ_SHIFT (17U) +/*! CREQ - Continue Request + * 0b1..Restart + * 0b0..No effect + */ #define USDHC_PROT_CTRL_CREQ(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_CREQ_SHIFT)) & USDHC_PROT_CTRL_CREQ_MASK) #define USDHC_PROT_CTRL_RWCTL_MASK (0x40000U) #define USDHC_PROT_CTRL_RWCTL_SHIFT (18U) +/*! RWCTL - Read Wait Control + * 0b1..Enable Read Wait Control, and assert Read Wait without stopping SD Clock at block gap when SABGREQ bit is set + * 0b0..Disable Read Wait Control, and stop SD Clock at block gap when SABGREQ bit is set + */ #define USDHC_PROT_CTRL_RWCTL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_RWCTL_SHIFT)) & USDHC_PROT_CTRL_RWCTL_MASK) #define USDHC_PROT_CTRL_IABG_MASK (0x80000U) #define USDHC_PROT_CTRL_IABG_SHIFT (19U) +/*! IABG - Interrupt At Block Gap + * 0b1..Enabled + * 0b0..Disabled + */ #define USDHC_PROT_CTRL_IABG(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_IABG_SHIFT)) & USDHC_PROT_CTRL_IABG_MASK) #define USDHC_PROT_CTRL_RD_DONE_NO_8CLK_MASK (0x100000U) #define USDHC_PROT_CTRL_RD_DONE_NO_8CLK_SHIFT (20U) #define USDHC_PROT_CTRL_RD_DONE_NO_8CLK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_RD_DONE_NO_8CLK_SHIFT)) & USDHC_PROT_CTRL_RD_DONE_NO_8CLK_MASK) #define USDHC_PROT_CTRL_WECINT_MASK (0x1000000U) #define USDHC_PROT_CTRL_WECINT_SHIFT (24U) +/*! WECINT - Wakeup Event Enable On Card Interrupt + * 0b1..Enable + * 0b0..Disable + */ #define USDHC_PROT_CTRL_WECINT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_WECINT_SHIFT)) & USDHC_PROT_CTRL_WECINT_MASK) #define USDHC_PROT_CTRL_WECINS_MASK (0x2000000U) #define USDHC_PROT_CTRL_WECINS_SHIFT (25U) +/*! WECINS - Wakeup Event Enable On SD Card Insertion + * 0b1..Enable + * 0b0..Disable + */ #define USDHC_PROT_CTRL_WECINS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_WECINS_SHIFT)) & USDHC_PROT_CTRL_WECINS_MASK) #define USDHC_PROT_CTRL_WECRM_MASK (0x4000000U) #define USDHC_PROT_CTRL_WECRM_SHIFT (26U) +/*! WECRM - Wakeup Event Enable On SD Card Removal + * 0b1..Enable + * 0b0..Disable + */ #define USDHC_PROT_CTRL_WECRM(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_WECRM_SHIFT)) & USDHC_PROT_CTRL_WECRM_MASK) #define USDHC_PROT_CTRL_BURST_LEN_EN_MASK (0x38000000U) #define USDHC_PROT_CTRL_BURST_LEN_EN_SHIFT (27U) +/*! BURST_LEN_EN - BURST length enable for INCR, INCR4 / INCR8 / INCR16, INCR4-WRAP / INCR8-WRAP / INCR16-WRAP + * 0bxx1..Burst length is enabled for INCR + * 0bx1x..Burst length is enabled for INCR4 / INCR8 / INCR16 + * 0b1xx..Burst length is enabled for INCR4-WRAP / INCR8-WRAP / INCR16-WRAP + */ #define USDHC_PROT_CTRL_BURST_LEN_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_BURST_LEN_EN_SHIFT)) & USDHC_PROT_CTRL_BURST_LEN_EN_MASK) #define USDHC_PROT_CTRL_NON_EXACT_BLK_RD_MASK (0x40000000U) #define USDHC_PROT_CTRL_NON_EXACT_BLK_RD_SHIFT (30U) +/*! NON_EXACT_BLK_RD - NON_EXACT_BLK_RD + * 0b1..The block read is non-exact block read. Host driver needs to issue abort command to terminate this multi-block read. + * 0b0..The block read is exact block read. Host driver doesn't need to issue abort command to terminate this multi-block read. + */ #define USDHC_PROT_CTRL_NON_EXACT_BLK_RD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_NON_EXACT_BLK_RD_SHIFT)) & USDHC_PROT_CTRL_NON_EXACT_BLK_RD_MASK) +/*! @} */ /*! @name SYS_CTRL - System Control */ +/*! @{ */ #define USDHC_SYS_CTRL_DVS_MASK (0xF0U) #define USDHC_SYS_CTRL_DVS_SHIFT (4U) +/*! DVS - Divisor + * 0b0000..Divide-by-1 + * 0b0001..Divide-by-2 + * 0b1110..Divide-by-15 + * 0b1111..Divide-by-16 + */ #define USDHC_SYS_CTRL_DVS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_DVS_SHIFT)) & USDHC_SYS_CTRL_DVS_MASK) #define USDHC_SYS_CTRL_SDCLKFS_MASK (0xFF00U) #define USDHC_SYS_CTRL_SDCLKFS_SHIFT (8U) #define USDHC_SYS_CTRL_SDCLKFS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_SDCLKFS_SHIFT)) & USDHC_SYS_CTRL_SDCLKFS_MASK) #define USDHC_SYS_CTRL_DTOCV_MASK (0xF0000U) #define USDHC_SYS_CTRL_DTOCV_SHIFT (16U) +/*! DTOCV - Data Timeout Counter Value + * 0b1111..SDCLK x 2 29 + * 0b1110..SDCLK x 2 28 + * 0b1101..SDCLK x 2 27 + * 0b0001..SDCLK x 2 15 + * 0b0000..SDCLK x 2 14 + */ #define USDHC_SYS_CTRL_DTOCV(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_DTOCV_SHIFT)) & USDHC_SYS_CTRL_DTOCV_MASK) #define USDHC_SYS_CTRL_IPP_RST_N_MASK (0x800000U) #define USDHC_SYS_CTRL_IPP_RST_N_SHIFT (23U) #define USDHC_SYS_CTRL_IPP_RST_N(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_IPP_RST_N_SHIFT)) & USDHC_SYS_CTRL_IPP_RST_N_MASK) #define USDHC_SYS_CTRL_RSTA_MASK (0x1000000U) #define USDHC_SYS_CTRL_RSTA_SHIFT (24U) +/*! RSTA - Software Reset For ALL + * 0b1..Reset + * 0b0..No Reset + */ #define USDHC_SYS_CTRL_RSTA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTA_SHIFT)) & USDHC_SYS_CTRL_RSTA_MASK) #define USDHC_SYS_CTRL_RSTC_MASK (0x2000000U) #define USDHC_SYS_CTRL_RSTC_SHIFT (25U) +/*! RSTC - Software Reset For CMD Line + * 0b1..Reset + * 0b0..No Reset + */ #define USDHC_SYS_CTRL_RSTC(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTC_SHIFT)) & USDHC_SYS_CTRL_RSTC_MASK) #define USDHC_SYS_CTRL_RSTD_MASK (0x4000000U) #define USDHC_SYS_CTRL_RSTD_SHIFT (26U) +/*! RSTD - Software Reset For DATA Line + * 0b1..Reset + * 0b0..No Reset + */ #define USDHC_SYS_CTRL_RSTD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTD_SHIFT)) & USDHC_SYS_CTRL_RSTD_MASK) #define USDHC_SYS_CTRL_INITA_MASK (0x8000000U) #define USDHC_SYS_CTRL_INITA_SHIFT (27U) @@ -22745,229 +35707,511 @@ typedef struct { #define USDHC_SYS_CTRL_RSTT_MASK (0x10000000U) #define USDHC_SYS_CTRL_RSTT_SHIFT (28U) #define USDHC_SYS_CTRL_RSTT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTT_SHIFT)) & USDHC_SYS_CTRL_RSTT_MASK) +/*! @} */ /*! @name INT_STATUS - Interrupt Status */ +/*! @{ */ #define USDHC_INT_STATUS_CC_MASK (0x1U) #define USDHC_INT_STATUS_CC_SHIFT (0U) +/*! CC - Command Complete + * 0b1..Command complete + * 0b0..Command not complete + */ #define USDHC_INT_STATUS_CC(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CC_SHIFT)) & USDHC_INT_STATUS_CC_MASK) #define USDHC_INT_STATUS_TC_MASK (0x2U) #define USDHC_INT_STATUS_TC_SHIFT (1U) +/*! TC - Transfer Complete + * 0b1..Transfer complete + * 0b0..Transfer not complete + */ #define USDHC_INT_STATUS_TC(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_TC_SHIFT)) & USDHC_INT_STATUS_TC_MASK) #define USDHC_INT_STATUS_BGE_MASK (0x4U) #define USDHC_INT_STATUS_BGE_SHIFT (2U) +/*! BGE - Block Gap Event + * 0b1..Transaction stopped at block gap + * 0b0..No block gap event + */ #define USDHC_INT_STATUS_BGE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_BGE_SHIFT)) & USDHC_INT_STATUS_BGE_MASK) #define USDHC_INT_STATUS_DINT_MASK (0x8U) #define USDHC_INT_STATUS_DINT_SHIFT (3U) +/*! DINT - DMA Interrupt + * 0b1..DMA Interrupt is generated + * 0b0..No DMA Interrupt + */ #define USDHC_INT_STATUS_DINT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DINT_SHIFT)) & USDHC_INT_STATUS_DINT_MASK) #define USDHC_INT_STATUS_BWR_MASK (0x10U) #define USDHC_INT_STATUS_BWR_SHIFT (4U) +/*! BWR - Buffer Write Ready + * 0b1..Ready to write buffer: + * 0b0..Not ready to write buffer + */ #define USDHC_INT_STATUS_BWR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_BWR_SHIFT)) & USDHC_INT_STATUS_BWR_MASK) #define USDHC_INT_STATUS_BRR_MASK (0x20U) #define USDHC_INT_STATUS_BRR_SHIFT (5U) +/*! BRR - Buffer Read Ready + * 0b1..Ready to read buffer + * 0b0..Not ready to read buffer + */ #define USDHC_INT_STATUS_BRR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_BRR_SHIFT)) & USDHC_INT_STATUS_BRR_MASK) #define USDHC_INT_STATUS_CINS_MASK (0x40U) #define USDHC_INT_STATUS_CINS_SHIFT (6U) +/*! CINS - Card Insertion + * 0b1..Card inserted + * 0b0..Card state unstable or removed + */ #define USDHC_INT_STATUS_CINS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CINS_SHIFT)) & USDHC_INT_STATUS_CINS_MASK) #define USDHC_INT_STATUS_CRM_MASK (0x80U) #define USDHC_INT_STATUS_CRM_SHIFT (7U) +/*! CRM - Card Removal + * 0b1..Card removed + * 0b0..Card state unstable or inserted + */ #define USDHC_INT_STATUS_CRM(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CRM_SHIFT)) & USDHC_INT_STATUS_CRM_MASK) #define USDHC_INT_STATUS_CINT_MASK (0x100U) #define USDHC_INT_STATUS_CINT_SHIFT (8U) +/*! CINT - Card Interrupt + * 0b1..Generate Card Interrupt + * 0b0..No Card Interrupt + */ #define USDHC_INT_STATUS_CINT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CINT_SHIFT)) & USDHC_INT_STATUS_CINT_MASK) #define USDHC_INT_STATUS_RTE_MASK (0x1000U) #define USDHC_INT_STATUS_RTE_SHIFT (12U) +/*! RTE - Re-Tuning Event: (only for SD3.0 SDR104 mode and EMMC HS200 mode) + * 0b1..Re-Tuning should be performed + * 0b0..Re-Tuning is not required + */ #define USDHC_INT_STATUS_RTE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_RTE_SHIFT)) & USDHC_INT_STATUS_RTE_MASK) #define USDHC_INT_STATUS_TP_MASK (0x4000U) #define USDHC_INT_STATUS_TP_SHIFT (14U) #define USDHC_INT_STATUS_TP(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_TP_SHIFT)) & USDHC_INT_STATUS_TP_MASK) #define USDHC_INT_STATUS_CTOE_MASK (0x10000U) #define USDHC_INT_STATUS_CTOE_SHIFT (16U) +/*! CTOE - Command Timeout Error + * 0b1..Time out + * 0b0..No Error + */ #define USDHC_INT_STATUS_CTOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CTOE_SHIFT)) & USDHC_INT_STATUS_CTOE_MASK) #define USDHC_INT_STATUS_CCE_MASK (0x20000U) #define USDHC_INT_STATUS_CCE_SHIFT (17U) +/*! CCE - Command CRC Error + * 0b1..CRC Error Generated. + * 0b0..No Error + */ #define USDHC_INT_STATUS_CCE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CCE_SHIFT)) & USDHC_INT_STATUS_CCE_MASK) #define USDHC_INT_STATUS_CEBE_MASK (0x40000U) #define USDHC_INT_STATUS_CEBE_SHIFT (18U) +/*! CEBE - Command End Bit Error + * 0b1..End Bit Error Generated + * 0b0..No Error + */ #define USDHC_INT_STATUS_CEBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CEBE_SHIFT)) & USDHC_INT_STATUS_CEBE_MASK) #define USDHC_INT_STATUS_CIE_MASK (0x80000U) #define USDHC_INT_STATUS_CIE_SHIFT (19U) +/*! CIE - Command Index Error + * 0b1..Error + * 0b0..No Error + */ #define USDHC_INT_STATUS_CIE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CIE_SHIFT)) & USDHC_INT_STATUS_CIE_MASK) #define USDHC_INT_STATUS_DTOE_MASK (0x100000U) #define USDHC_INT_STATUS_DTOE_SHIFT (20U) +/*! DTOE - Data Timeout Error + * 0b1..Time out + * 0b0..No Error + */ #define USDHC_INT_STATUS_DTOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DTOE_SHIFT)) & USDHC_INT_STATUS_DTOE_MASK) #define USDHC_INT_STATUS_DCE_MASK (0x200000U) #define USDHC_INT_STATUS_DCE_SHIFT (21U) +/*! DCE - Data CRC Error + * 0b1..Error + * 0b0..No Error + */ #define USDHC_INT_STATUS_DCE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DCE_SHIFT)) & USDHC_INT_STATUS_DCE_MASK) #define USDHC_INT_STATUS_DEBE_MASK (0x400000U) #define USDHC_INT_STATUS_DEBE_SHIFT (22U) +/*! DEBE - Data End Bit Error + * 0b1..Error + * 0b0..No Error + */ #define USDHC_INT_STATUS_DEBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DEBE_SHIFT)) & USDHC_INT_STATUS_DEBE_MASK) #define USDHC_INT_STATUS_AC12E_MASK (0x1000000U) #define USDHC_INT_STATUS_AC12E_SHIFT (24U) +/*! AC12E - Auto CMD12 Error + * 0b1..Error + * 0b0..No Error + */ #define USDHC_INT_STATUS_AC12E(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_AC12E_SHIFT)) & USDHC_INT_STATUS_AC12E_MASK) #define USDHC_INT_STATUS_TNE_MASK (0x4000000U) #define USDHC_INT_STATUS_TNE_SHIFT (26U) #define USDHC_INT_STATUS_TNE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_TNE_SHIFT)) & USDHC_INT_STATUS_TNE_MASK) #define USDHC_INT_STATUS_DMAE_MASK (0x10000000U) #define USDHC_INT_STATUS_DMAE_SHIFT (28U) +/*! DMAE - DMA Error + * 0b1..Error + * 0b0..No Error + */ #define USDHC_INT_STATUS_DMAE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DMAE_SHIFT)) & USDHC_INT_STATUS_DMAE_MASK) +/*! @} */ /*! @name INT_STATUS_EN - Interrupt Status Enable */ +/*! @{ */ #define USDHC_INT_STATUS_EN_CCSEN_MASK (0x1U) #define USDHC_INT_STATUS_EN_CCSEN_SHIFT (0U) +/*! CCSEN - Command Complete Status Enable + * 0b1..Enabled + * 0b0..Masked + */ #define USDHC_INT_STATUS_EN_CCSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CCSEN_SHIFT)) & USDHC_INT_STATUS_EN_CCSEN_MASK) #define USDHC_INT_STATUS_EN_TCSEN_MASK (0x2U) #define USDHC_INT_STATUS_EN_TCSEN_SHIFT (1U) +/*! TCSEN - Transfer Complete Status Enable + * 0b1..Enabled + * 0b0..Masked + */ #define USDHC_INT_STATUS_EN_TCSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_TCSEN_SHIFT)) & USDHC_INT_STATUS_EN_TCSEN_MASK) #define USDHC_INT_STATUS_EN_BGESEN_MASK (0x4U) #define USDHC_INT_STATUS_EN_BGESEN_SHIFT (2U) +/*! BGESEN - Block Gap Event Status Enable + * 0b1..Enabled + * 0b0..Masked + */ #define USDHC_INT_STATUS_EN_BGESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_BGESEN_SHIFT)) & USDHC_INT_STATUS_EN_BGESEN_MASK) #define USDHC_INT_STATUS_EN_DINTSEN_MASK (0x8U) #define USDHC_INT_STATUS_EN_DINTSEN_SHIFT (3U) +/*! DINTSEN - DMA Interrupt Status Enable + * 0b1..Enabled + * 0b0..Masked + */ #define USDHC_INT_STATUS_EN_DINTSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DINTSEN_SHIFT)) & USDHC_INT_STATUS_EN_DINTSEN_MASK) #define USDHC_INT_STATUS_EN_BWRSEN_MASK (0x10U) #define USDHC_INT_STATUS_EN_BWRSEN_SHIFT (4U) +/*! BWRSEN - Buffer Write Ready Status Enable + * 0b1..Enabled + * 0b0..Masked + */ #define USDHC_INT_STATUS_EN_BWRSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_BWRSEN_SHIFT)) & USDHC_INT_STATUS_EN_BWRSEN_MASK) #define USDHC_INT_STATUS_EN_BRRSEN_MASK (0x20U) #define USDHC_INT_STATUS_EN_BRRSEN_SHIFT (5U) +/*! BRRSEN - Buffer Read Ready Status Enable + * 0b1..Enabled + * 0b0..Masked + */ #define USDHC_INT_STATUS_EN_BRRSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_BRRSEN_SHIFT)) & USDHC_INT_STATUS_EN_BRRSEN_MASK) #define USDHC_INT_STATUS_EN_CINSSEN_MASK (0x40U) #define USDHC_INT_STATUS_EN_CINSSEN_SHIFT (6U) +/*! CINSSEN - Card Insertion Status Enable + * 0b1..Enabled + * 0b0..Masked + */ #define USDHC_INT_STATUS_EN_CINSSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CINSSEN_SHIFT)) & USDHC_INT_STATUS_EN_CINSSEN_MASK) #define USDHC_INT_STATUS_EN_CRMSEN_MASK (0x80U) #define USDHC_INT_STATUS_EN_CRMSEN_SHIFT (7U) +/*! CRMSEN - Card Removal Status Enable + * 0b1..Enabled + * 0b0..Masked + */ #define USDHC_INT_STATUS_EN_CRMSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CRMSEN_SHIFT)) & USDHC_INT_STATUS_EN_CRMSEN_MASK) #define USDHC_INT_STATUS_EN_CINTSEN_MASK (0x100U) #define USDHC_INT_STATUS_EN_CINTSEN_SHIFT (8U) +/*! CINTSEN - Card Interrupt Status Enable + * 0b1..Enabled + * 0b0..Masked + */ #define USDHC_INT_STATUS_EN_CINTSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CINTSEN_SHIFT)) & USDHC_INT_STATUS_EN_CINTSEN_MASK) #define USDHC_INT_STATUS_EN_RTESEN_MASK (0x1000U) #define USDHC_INT_STATUS_EN_RTESEN_SHIFT (12U) +/*! RTESEN - Re-Tuning Event Status Enable + * 0b1..Enabled + * 0b0..Masked + */ #define USDHC_INT_STATUS_EN_RTESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_RTESEN_SHIFT)) & USDHC_INT_STATUS_EN_RTESEN_MASK) #define USDHC_INT_STATUS_EN_TPSEN_MASK (0x4000U) #define USDHC_INT_STATUS_EN_TPSEN_SHIFT (14U) +/*! TPSEN - Tuning Pass Status Enable + * 0b1..Enabled + * 0b0..Masked + */ #define USDHC_INT_STATUS_EN_TPSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_TPSEN_SHIFT)) & USDHC_INT_STATUS_EN_TPSEN_MASK) #define USDHC_INT_STATUS_EN_CTOESEN_MASK (0x10000U) #define USDHC_INT_STATUS_EN_CTOESEN_SHIFT (16U) +/*! CTOESEN - Command Timeout Error Status Enable + * 0b1..Enabled + * 0b0..Masked + */ #define USDHC_INT_STATUS_EN_CTOESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CTOESEN_SHIFT)) & USDHC_INT_STATUS_EN_CTOESEN_MASK) #define USDHC_INT_STATUS_EN_CCESEN_MASK (0x20000U) #define USDHC_INT_STATUS_EN_CCESEN_SHIFT (17U) +/*! CCESEN - Command CRC Error Status Enable + * 0b1..Enabled + * 0b0..Masked + */ #define USDHC_INT_STATUS_EN_CCESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CCESEN_SHIFT)) & USDHC_INT_STATUS_EN_CCESEN_MASK) #define USDHC_INT_STATUS_EN_CEBESEN_MASK (0x40000U) #define USDHC_INT_STATUS_EN_CEBESEN_SHIFT (18U) +/*! CEBESEN - Command End Bit Error Status Enable + * 0b1..Enabled + * 0b0..Masked + */ #define USDHC_INT_STATUS_EN_CEBESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CEBESEN_SHIFT)) & USDHC_INT_STATUS_EN_CEBESEN_MASK) #define USDHC_INT_STATUS_EN_CIESEN_MASK (0x80000U) #define USDHC_INT_STATUS_EN_CIESEN_SHIFT (19U) +/*! CIESEN - Command Index Error Status Enable + * 0b1..Enabled + * 0b0..Masked + */ #define USDHC_INT_STATUS_EN_CIESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CIESEN_SHIFT)) & USDHC_INT_STATUS_EN_CIESEN_MASK) #define USDHC_INT_STATUS_EN_DTOESEN_MASK (0x100000U) #define USDHC_INT_STATUS_EN_DTOESEN_SHIFT (20U) +/*! DTOESEN - Data Timeout Error Status Enable + * 0b1..Enabled + * 0b0..Masked + */ #define USDHC_INT_STATUS_EN_DTOESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DTOESEN_SHIFT)) & USDHC_INT_STATUS_EN_DTOESEN_MASK) #define USDHC_INT_STATUS_EN_DCESEN_MASK (0x200000U) #define USDHC_INT_STATUS_EN_DCESEN_SHIFT (21U) +/*! DCESEN - Data CRC Error Status Enable + * 0b1..Enabled + * 0b0..Masked + */ #define USDHC_INT_STATUS_EN_DCESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DCESEN_SHIFT)) & USDHC_INT_STATUS_EN_DCESEN_MASK) #define USDHC_INT_STATUS_EN_DEBESEN_MASK (0x400000U) #define USDHC_INT_STATUS_EN_DEBESEN_SHIFT (22U) +/*! DEBESEN - Data End Bit Error Status Enable + * 0b1..Enabled + * 0b0..Masked + */ #define USDHC_INT_STATUS_EN_DEBESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DEBESEN_SHIFT)) & USDHC_INT_STATUS_EN_DEBESEN_MASK) #define USDHC_INT_STATUS_EN_AC12ESEN_MASK (0x1000000U) #define USDHC_INT_STATUS_EN_AC12ESEN_SHIFT (24U) +/*! AC12ESEN - Auto CMD12 Error Status Enable + * 0b1..Enabled + * 0b0..Masked + */ #define USDHC_INT_STATUS_EN_AC12ESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_AC12ESEN_SHIFT)) & USDHC_INT_STATUS_EN_AC12ESEN_MASK) #define USDHC_INT_STATUS_EN_TNESEN_MASK (0x4000000U) #define USDHC_INT_STATUS_EN_TNESEN_SHIFT (26U) +/*! TNESEN - Tuning Error Status Enable + * 0b1..Enabled + * 0b0..Masked + */ #define USDHC_INT_STATUS_EN_TNESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_TNESEN_SHIFT)) & USDHC_INT_STATUS_EN_TNESEN_MASK) #define USDHC_INT_STATUS_EN_DMAESEN_MASK (0x10000000U) #define USDHC_INT_STATUS_EN_DMAESEN_SHIFT (28U) +/*! DMAESEN - DMA Error Status Enable + * 0b1..Enabled + * 0b0..Masked + */ #define USDHC_INT_STATUS_EN_DMAESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DMAESEN_SHIFT)) & USDHC_INT_STATUS_EN_DMAESEN_MASK) +/*! @} */ /*! @name INT_SIGNAL_EN - Interrupt Signal Enable */ +/*! @{ */ #define USDHC_INT_SIGNAL_EN_CCIEN_MASK (0x1U) #define USDHC_INT_SIGNAL_EN_CCIEN_SHIFT (0U) +/*! CCIEN - Command Complete Interrupt Enable + * 0b1..Enabled + * 0b0..Masked + */ #define USDHC_INT_SIGNAL_EN_CCIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CCIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CCIEN_MASK) #define USDHC_INT_SIGNAL_EN_TCIEN_MASK (0x2U) #define USDHC_INT_SIGNAL_EN_TCIEN_SHIFT (1U) +/*! TCIEN - Transfer Complete Interrupt Enable + * 0b1..Enabled + * 0b0..Masked + */ #define USDHC_INT_SIGNAL_EN_TCIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_TCIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_TCIEN_MASK) #define USDHC_INT_SIGNAL_EN_BGEIEN_MASK (0x4U) #define USDHC_INT_SIGNAL_EN_BGEIEN_SHIFT (2U) +/*! BGEIEN - Block Gap Event Interrupt Enable + * 0b1..Enabled + * 0b0..Masked + */ #define USDHC_INT_SIGNAL_EN_BGEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_BGEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_BGEIEN_MASK) #define USDHC_INT_SIGNAL_EN_DINTIEN_MASK (0x8U) #define USDHC_INT_SIGNAL_EN_DINTIEN_SHIFT (3U) +/*! DINTIEN - DMA Interrupt Enable + * 0b1..Enabled + * 0b0..Masked + */ #define USDHC_INT_SIGNAL_EN_DINTIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DINTIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DINTIEN_MASK) #define USDHC_INT_SIGNAL_EN_BWRIEN_MASK (0x10U) #define USDHC_INT_SIGNAL_EN_BWRIEN_SHIFT (4U) +/*! BWRIEN - Buffer Write Ready Interrupt Enable + * 0b1..Enabled + * 0b0..Masked + */ #define USDHC_INT_SIGNAL_EN_BWRIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_BWRIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_BWRIEN_MASK) #define USDHC_INT_SIGNAL_EN_BRRIEN_MASK (0x20U) #define USDHC_INT_SIGNAL_EN_BRRIEN_SHIFT (5U) +/*! BRRIEN - Buffer Read Ready Interrupt Enable + * 0b1..Enabled + * 0b0..Masked + */ #define USDHC_INT_SIGNAL_EN_BRRIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_BRRIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_BRRIEN_MASK) #define USDHC_INT_SIGNAL_EN_CINSIEN_MASK (0x40U) #define USDHC_INT_SIGNAL_EN_CINSIEN_SHIFT (6U) +/*! CINSIEN - Card Insertion Interrupt Enable + * 0b1..Enabled + * 0b0..Masked + */ #define USDHC_INT_SIGNAL_EN_CINSIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CINSIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CINSIEN_MASK) #define USDHC_INT_SIGNAL_EN_CRMIEN_MASK (0x80U) #define USDHC_INT_SIGNAL_EN_CRMIEN_SHIFT (7U) +/*! CRMIEN - Card Removal Interrupt Enable + * 0b1..Enabled + * 0b0..Masked + */ #define USDHC_INT_SIGNAL_EN_CRMIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CRMIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CRMIEN_MASK) #define USDHC_INT_SIGNAL_EN_CINTIEN_MASK (0x100U) #define USDHC_INT_SIGNAL_EN_CINTIEN_SHIFT (8U) +/*! CINTIEN - Card Interrupt Interrupt Enable + * 0b1..Enabled + * 0b0..Masked + */ #define USDHC_INT_SIGNAL_EN_CINTIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CINTIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CINTIEN_MASK) #define USDHC_INT_SIGNAL_EN_RTEIEN_MASK (0x1000U) #define USDHC_INT_SIGNAL_EN_RTEIEN_SHIFT (12U) +/*! RTEIEN - Re-Tuning Event Interrupt Enable + * 0b1..Enabled + * 0b0..Masked + */ #define USDHC_INT_SIGNAL_EN_RTEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_RTEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_RTEIEN_MASK) #define USDHC_INT_SIGNAL_EN_TPIEN_MASK (0x4000U) #define USDHC_INT_SIGNAL_EN_TPIEN_SHIFT (14U) +/*! TPIEN - Tuning Pass Interrupt Enable + * 0b1..Enabled + * 0b0..Masked + */ #define USDHC_INT_SIGNAL_EN_TPIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_TPIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_TPIEN_MASK) #define USDHC_INT_SIGNAL_EN_CTOEIEN_MASK (0x10000U) #define USDHC_INT_SIGNAL_EN_CTOEIEN_SHIFT (16U) +/*! CTOEIEN - Command Timeout Error Interrupt Enable + * 0b1..Enabled + * 0b0..Masked + */ #define USDHC_INT_SIGNAL_EN_CTOEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CTOEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CTOEIEN_MASK) #define USDHC_INT_SIGNAL_EN_CCEIEN_MASK (0x20000U) #define USDHC_INT_SIGNAL_EN_CCEIEN_SHIFT (17U) +/*! CCEIEN - Command CRC Error Interrupt Enable + * 0b1..Enabled + * 0b0..Masked + */ #define USDHC_INT_SIGNAL_EN_CCEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CCEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CCEIEN_MASK) #define USDHC_INT_SIGNAL_EN_CEBEIEN_MASK (0x40000U) #define USDHC_INT_SIGNAL_EN_CEBEIEN_SHIFT (18U) +/*! CEBEIEN - Command End Bit Error Interrupt Enable + * 0b1..Enabled + * 0b0..Masked + */ #define USDHC_INT_SIGNAL_EN_CEBEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CEBEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CEBEIEN_MASK) #define USDHC_INT_SIGNAL_EN_CIEIEN_MASK (0x80000U) #define USDHC_INT_SIGNAL_EN_CIEIEN_SHIFT (19U) +/*! CIEIEN - Command Index Error Interrupt Enable + * 0b1..Enabled + * 0b0..Masked + */ #define USDHC_INT_SIGNAL_EN_CIEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CIEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CIEIEN_MASK) #define USDHC_INT_SIGNAL_EN_DTOEIEN_MASK (0x100000U) #define USDHC_INT_SIGNAL_EN_DTOEIEN_SHIFT (20U) +/*! DTOEIEN - Data Timeout Error Interrupt Enable + * 0b1..Enabled + * 0b0..Masked + */ #define USDHC_INT_SIGNAL_EN_DTOEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DTOEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DTOEIEN_MASK) #define USDHC_INT_SIGNAL_EN_DCEIEN_MASK (0x200000U) #define USDHC_INT_SIGNAL_EN_DCEIEN_SHIFT (21U) +/*! DCEIEN - Data CRC Error Interrupt Enable + * 0b1..Enabled + * 0b0..Masked + */ #define USDHC_INT_SIGNAL_EN_DCEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DCEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DCEIEN_MASK) #define USDHC_INT_SIGNAL_EN_DEBEIEN_MASK (0x400000U) #define USDHC_INT_SIGNAL_EN_DEBEIEN_SHIFT (22U) +/*! DEBEIEN - Data End Bit Error Interrupt Enable + * 0b1..Enabled + * 0b0..Masked + */ #define USDHC_INT_SIGNAL_EN_DEBEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DEBEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DEBEIEN_MASK) #define USDHC_INT_SIGNAL_EN_AC12EIEN_MASK (0x1000000U) #define USDHC_INT_SIGNAL_EN_AC12EIEN_SHIFT (24U) +/*! AC12EIEN - Auto CMD12 Error Interrupt Enable + * 0b1..Enabled + * 0b0..Masked + */ #define USDHC_INT_SIGNAL_EN_AC12EIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_AC12EIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_AC12EIEN_MASK) #define USDHC_INT_SIGNAL_EN_TNEIEN_MASK (0x4000000U) #define USDHC_INT_SIGNAL_EN_TNEIEN_SHIFT (26U) +/*! TNEIEN - Tuning Error Interrupt Enable + * 0b1..Enabled + * 0b0..Masked + */ #define USDHC_INT_SIGNAL_EN_TNEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_TNEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_TNEIEN_MASK) #define USDHC_INT_SIGNAL_EN_DMAEIEN_MASK (0x10000000U) #define USDHC_INT_SIGNAL_EN_DMAEIEN_SHIFT (28U) +/*! DMAEIEN - DMA Error Interrupt Enable + * 0b1..Enable + * 0b0..Masked + */ #define USDHC_INT_SIGNAL_EN_DMAEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DMAEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DMAEIEN_MASK) +/*! @} */ /*! @name AUTOCMD12_ERR_STATUS - Auto CMD12 Error Status */ +/*! @{ */ #define USDHC_AUTOCMD12_ERR_STATUS_AC12NE_MASK (0x1U) #define USDHC_AUTOCMD12_ERR_STATUS_AC12NE_SHIFT (0U) +/*! AC12NE - Auto CMD12 Not Executed + * 0b1..Not executed + * 0b0..Executed + */ #define USDHC_AUTOCMD12_ERR_STATUS_AC12NE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12NE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12NE_MASK) #define USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_MASK (0x2U) #define USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_SHIFT (1U) +/*! AC12TOE - Auto CMD12 / 23 Timeout Error + * 0b1..Time out + * 0b0..No error + */ #define USDHC_AUTOCMD12_ERR_STATUS_AC12TOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_MASK) #define USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_MASK (0x4U) #define USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_SHIFT (2U) +/*! AC12EBE - Auto CMD12 / 23 End Bit Error + * 0b1..End Bit Error Generated + * 0b0..No error + */ #define USDHC_AUTOCMD12_ERR_STATUS_AC12EBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_MASK) #define USDHC_AUTOCMD12_ERR_STATUS_AC12CE_MASK (0x8U) #define USDHC_AUTOCMD12_ERR_STATUS_AC12CE_SHIFT (3U) +/*! AC12CE - Auto CMD12 / 23 CRC Error + * 0b1..CRC Error Met in Auto CMD12/23 Response + * 0b0..No CRC error + */ #define USDHC_AUTOCMD12_ERR_STATUS_AC12CE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12CE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12CE_MASK) #define USDHC_AUTOCMD12_ERR_STATUS_AC12IE_MASK (0x10U) #define USDHC_AUTOCMD12_ERR_STATUS_AC12IE_SHIFT (4U) +/*! AC12IE - Auto CMD12 / 23 Index Error + * 0b1..Error, the CMD index in response is not CMD12/23 + * 0b0..No error + */ #define USDHC_AUTOCMD12_ERR_STATUS_AC12IE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12IE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12IE_MASK) #define USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_MASK (0x80U) #define USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_SHIFT (7U) +/*! CNIBAC12E - Command Not Issued By Auto CMD12 Error + * 0b1..Not Issued + * 0b0..No error + */ #define USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_MASK) #define USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_MASK (0x400000U) #define USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_SHIFT (22U) #define USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_MASK) #define USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_MASK (0x800000U) #define USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_SHIFT (23U) +/*! SMP_CLK_SEL - Sample Clock Select + * 0b1..Tuned clock is used to sample data + * 0b0..Fixed clock is used to sample data + */ #define USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_MASK) +/*! @} */ /*! @name HOST_CTRL_CAP - Host Controller Capabilities */ +/*! @{ */ #define USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_MASK (0x1U) #define USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_SHIFT (0U) #define USDHC_HOST_CTRL_CAP_SDR50_SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_SHIFT)) & USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_MASK) @@ -22982,36 +36226,82 @@ typedef struct { #define USDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING_SHIFT)) & USDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING_MASK) #define USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_MASK (0x2000U) #define USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_SHIFT (13U) +/*! USE_TUNING_SDR50 - Use Tuning for SDR50 + * 0b1..SDR50 requires tuning + * 0b0..SDR does not require tuning + */ #define USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_SHIFT)) & USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_MASK) #define USDHC_HOST_CTRL_CAP_RETUNING_MODE_MASK (0xC000U) #define USDHC_HOST_CTRL_CAP_RETUNING_MODE_SHIFT (14U) +/*! RETUNING_MODE - Retuning Mode + * 0b00..Mode 1 + * 0b01..Mode 2 + * 0b10..Mode 3 + * 0b11..Reserved + */ #define USDHC_HOST_CTRL_CAP_RETUNING_MODE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_RETUNING_MODE_SHIFT)) & USDHC_HOST_CTRL_CAP_RETUNING_MODE_MASK) #define USDHC_HOST_CTRL_CAP_MBL_MASK (0x70000U) #define USDHC_HOST_CTRL_CAP_MBL_SHIFT (16U) +/*! MBL - Max Block Length + * 0b000..512 bytes + * 0b001..1024 bytes + * 0b010..2048 bytes + * 0b011..4096 bytes + */ #define USDHC_HOST_CTRL_CAP_MBL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_MBL_SHIFT)) & USDHC_HOST_CTRL_CAP_MBL_MASK) #define USDHC_HOST_CTRL_CAP_ADMAS_MASK (0x100000U) #define USDHC_HOST_CTRL_CAP_ADMAS_SHIFT (20U) +/*! ADMAS - ADMA Support + * 0b1..Advanced DMA Supported + * 0b0..Advanced DMA Not supported + */ #define USDHC_HOST_CTRL_CAP_ADMAS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_ADMAS_SHIFT)) & USDHC_HOST_CTRL_CAP_ADMAS_MASK) #define USDHC_HOST_CTRL_CAP_HSS_MASK (0x200000U) #define USDHC_HOST_CTRL_CAP_HSS_SHIFT (21U) +/*! HSS - High Speed Support + * 0b1..High Speed Supported + * 0b0..High Speed Not Supported + */ #define USDHC_HOST_CTRL_CAP_HSS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_HSS_SHIFT)) & USDHC_HOST_CTRL_CAP_HSS_MASK) #define USDHC_HOST_CTRL_CAP_DMAS_MASK (0x400000U) #define USDHC_HOST_CTRL_CAP_DMAS_SHIFT (22U) +/*! DMAS - DMA Support + * 0b1..DMA Supported + * 0b0..DMA not supported + */ #define USDHC_HOST_CTRL_CAP_DMAS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_DMAS_SHIFT)) & USDHC_HOST_CTRL_CAP_DMAS_MASK) #define USDHC_HOST_CTRL_CAP_SRS_MASK (0x800000U) #define USDHC_HOST_CTRL_CAP_SRS_SHIFT (23U) +/*! SRS - Suspend / Resume Support + * 0b1..Supported + * 0b0..Not supported + */ #define USDHC_HOST_CTRL_CAP_SRS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_SRS_SHIFT)) & USDHC_HOST_CTRL_CAP_SRS_MASK) #define USDHC_HOST_CTRL_CAP_VS33_MASK (0x1000000U) #define USDHC_HOST_CTRL_CAP_VS33_SHIFT (24U) +/*! VS33 - Voltage Support 3.3V + * 0b1..3.3V supported + * 0b0..3.3V not supported + */ #define USDHC_HOST_CTRL_CAP_VS33(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_VS33_SHIFT)) & USDHC_HOST_CTRL_CAP_VS33_MASK) #define USDHC_HOST_CTRL_CAP_VS30_MASK (0x2000000U) #define USDHC_HOST_CTRL_CAP_VS30_SHIFT (25U) +/*! VS30 - Voltage Support 3.0 V + * 0b1..3.0V supported + * 0b0..3.0V not supported + */ #define USDHC_HOST_CTRL_CAP_VS30(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_VS30_SHIFT)) & USDHC_HOST_CTRL_CAP_VS30_MASK) #define USDHC_HOST_CTRL_CAP_VS18_MASK (0x4000000U) #define USDHC_HOST_CTRL_CAP_VS18_SHIFT (26U) +/*! VS18 - Voltage Support 1.8 V + * 0b1..1.8V supported + * 0b0..1.8V not supported + */ #define USDHC_HOST_CTRL_CAP_VS18(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_VS18_SHIFT)) & USDHC_HOST_CTRL_CAP_VS18_MASK) +/*! @} */ /*! @name WTMK_LVL - Watermark Level */ +/*! @{ */ #define USDHC_WTMK_LVL_RD_WML_MASK (0xFFU) #define USDHC_WTMK_LVL_RD_WML_SHIFT (0U) #define USDHC_WTMK_LVL_RD_WML(x) (((uint32_t)(((uint32_t)(x)) << USDHC_WTMK_LVL_RD_WML_SHIFT)) & USDHC_WTMK_LVL_RD_WML_MASK) @@ -23024,25 +36314,47 @@ typedef struct { #define USDHC_WTMK_LVL_WR_BRST_LEN_MASK (0x1F000000U) #define USDHC_WTMK_LVL_WR_BRST_LEN_SHIFT (24U) #define USDHC_WTMK_LVL_WR_BRST_LEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_WTMK_LVL_WR_BRST_LEN_SHIFT)) & USDHC_WTMK_LVL_WR_BRST_LEN_MASK) +/*! @} */ /*! @name MIX_CTRL - Mixer Control */ +/*! @{ */ #define USDHC_MIX_CTRL_DMAEN_MASK (0x1U) #define USDHC_MIX_CTRL_DMAEN_SHIFT (0U) +/*! DMAEN - DMA Enable + * 0b1..Enable + * 0b0..Disable + */ #define USDHC_MIX_CTRL_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_DMAEN_SHIFT)) & USDHC_MIX_CTRL_DMAEN_MASK) #define USDHC_MIX_CTRL_BCEN_MASK (0x2U) #define USDHC_MIX_CTRL_BCEN_SHIFT (1U) +/*! BCEN - Block Count Enable + * 0b1..Enable + * 0b0..Disable + */ #define USDHC_MIX_CTRL_BCEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_BCEN_SHIFT)) & USDHC_MIX_CTRL_BCEN_MASK) #define USDHC_MIX_CTRL_AC12EN_MASK (0x4U) #define USDHC_MIX_CTRL_AC12EN_SHIFT (2U) +/*! AC12EN - Auto CMD12 Enable + * 0b1..Enable + * 0b0..Disable + */ #define USDHC_MIX_CTRL_AC12EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_AC12EN_SHIFT)) & USDHC_MIX_CTRL_AC12EN_MASK) #define USDHC_MIX_CTRL_DDR_EN_MASK (0x8U) #define USDHC_MIX_CTRL_DDR_EN_SHIFT (3U) #define USDHC_MIX_CTRL_DDR_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_DDR_EN_SHIFT)) & USDHC_MIX_CTRL_DDR_EN_MASK) #define USDHC_MIX_CTRL_DTDSEL_MASK (0x10U) #define USDHC_MIX_CTRL_DTDSEL_SHIFT (4U) +/*! DTDSEL - Data Transfer Direction Select + * 0b1..Read (Card to Host) + * 0b0..Write (Host to Card) + */ #define USDHC_MIX_CTRL_DTDSEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_DTDSEL_SHIFT)) & USDHC_MIX_CTRL_DTDSEL_MASK) #define USDHC_MIX_CTRL_MSBSEL_MASK (0x20U) #define USDHC_MIX_CTRL_MSBSEL_SHIFT (5U) +/*! MSBSEL - Multi / Single Block Select + * 0b1..Multiple Blocks + * 0b0..Single Block + */ #define USDHC_MIX_CTRL_MSBSEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_MSBSEL_SHIFT)) & USDHC_MIX_CTRL_MSBSEL_MASK) #define USDHC_MIX_CTRL_NIBBLE_POS_MASK (0x40U) #define USDHC_MIX_CTRL_NIBBLE_POS_SHIFT (6U) @@ -23052,18 +36364,36 @@ typedef struct { #define USDHC_MIX_CTRL_AC23EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_AC23EN_SHIFT)) & USDHC_MIX_CTRL_AC23EN_MASK) #define USDHC_MIX_CTRL_EXE_TUNE_MASK (0x400000U) #define USDHC_MIX_CTRL_EXE_TUNE_SHIFT (22U) +/*! EXE_TUNE - Execute Tuning: (Only used for SD3.0, SDR104 mode and EMMC HS200 mode) + * 0b1..Execute Tuning + * 0b0..Not Tuned or Tuning Completed + */ #define USDHC_MIX_CTRL_EXE_TUNE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_EXE_TUNE_SHIFT)) & USDHC_MIX_CTRL_EXE_TUNE_MASK) #define USDHC_MIX_CTRL_SMP_CLK_SEL_MASK (0x800000U) #define USDHC_MIX_CTRL_SMP_CLK_SEL_SHIFT (23U) +/*! SMP_CLK_SEL - SMP_CLK_SEL + * 0b1..Tuned clock is used to sample data / cmd + * 0b0..Fixed clock is used to sample data / cmd + */ #define USDHC_MIX_CTRL_SMP_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_SMP_CLK_SEL_SHIFT)) & USDHC_MIX_CTRL_SMP_CLK_SEL_MASK) #define USDHC_MIX_CTRL_AUTO_TUNE_EN_MASK (0x1000000U) #define USDHC_MIX_CTRL_AUTO_TUNE_EN_SHIFT (24U) +/*! AUTO_TUNE_EN - Auto Tuning Enable (Only used for SD3.0, SDR104 mode and and EMMC HS200 mode) + * 0b1..Enable auto tuning + * 0b0..Disable auto tuning + */ #define USDHC_MIX_CTRL_AUTO_TUNE_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_AUTO_TUNE_EN_SHIFT)) & USDHC_MIX_CTRL_AUTO_TUNE_EN_MASK) #define USDHC_MIX_CTRL_FBCLK_SEL_MASK (0x2000000U) #define USDHC_MIX_CTRL_FBCLK_SEL_SHIFT (25U) +/*! FBCLK_SEL - Feedback Clock Source Selection (Only used for SD3.0, SDR104 mode and EMMC HS200 mode) + * 0b1..Feedback clock comes from the ipp_card_clk_out + * 0b0..Feedback clock comes from the loopback CLK + */ #define USDHC_MIX_CTRL_FBCLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_FBCLK_SEL_SHIFT)) & USDHC_MIX_CTRL_FBCLK_SEL_MASK) +/*! @} */ /*! @name FORCE_EVENT - Force Event */ +/*! @{ */ #define USDHC_FORCE_EVENT_FEVTAC12NE_MASK (0x1U) #define USDHC_FORCE_EVENT_FEVTAC12NE_SHIFT (0U) #define USDHC_FORCE_EVENT_FEVTAC12NE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12NE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12NE_MASK) @@ -23115,24 +36445,38 @@ typedef struct { #define USDHC_FORCE_EVENT_FEVTCINT_MASK (0x80000000U) #define USDHC_FORCE_EVENT_FEVTCINT_SHIFT (31U) #define USDHC_FORCE_EVENT_FEVTCINT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCINT_SHIFT)) & USDHC_FORCE_EVENT_FEVTCINT_MASK) +/*! @} */ /*! @name ADMA_ERR_STATUS - ADMA Error Status Register */ +/*! @{ */ #define USDHC_ADMA_ERR_STATUS_ADMAES_MASK (0x3U) #define USDHC_ADMA_ERR_STATUS_ADMAES_SHIFT (0U) #define USDHC_ADMA_ERR_STATUS_ADMAES(x) (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_ERR_STATUS_ADMAES_SHIFT)) & USDHC_ADMA_ERR_STATUS_ADMAES_MASK) #define USDHC_ADMA_ERR_STATUS_ADMALME_MASK (0x4U) #define USDHC_ADMA_ERR_STATUS_ADMALME_SHIFT (2U) +/*! ADMALME - ADMA Length Mismatch Error + * 0b1..Error + * 0b0..No Error + */ #define USDHC_ADMA_ERR_STATUS_ADMALME(x) (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_ERR_STATUS_ADMALME_SHIFT)) & USDHC_ADMA_ERR_STATUS_ADMALME_MASK) #define USDHC_ADMA_ERR_STATUS_ADMADCE_MASK (0x8U) #define USDHC_ADMA_ERR_STATUS_ADMADCE_SHIFT (3U) +/*! ADMADCE - ADMA Descriptor Error + * 0b1..Error + * 0b0..No Error + */ #define USDHC_ADMA_ERR_STATUS_ADMADCE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_ERR_STATUS_ADMADCE_SHIFT)) & USDHC_ADMA_ERR_STATUS_ADMADCE_MASK) +/*! @} */ /*! @name ADMA_SYS_ADDR - ADMA System Address */ +/*! @{ */ #define USDHC_ADMA_SYS_ADDR_ADS_ADDR_MASK (0xFFFFFFFCU) #define USDHC_ADMA_SYS_ADDR_ADS_ADDR_SHIFT (2U) #define USDHC_ADMA_SYS_ADDR_ADS_ADDR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_SYS_ADDR_ADS_ADDR_SHIFT)) & USDHC_ADMA_SYS_ADDR_ADS_ADDR_MASK) +/*! @} */ /*! @name DLL_CTRL - DLL (Delay Line) Control */ +/*! @{ */ #define USDHC_DLL_CTRL_DLL_CTRL_ENABLE_MASK (0x1U) #define USDHC_DLL_CTRL_DLL_CTRL_ENABLE_SHIFT (0U) #define USDHC_DLL_CTRL_DLL_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_ENABLE_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_ENABLE_MASK) @@ -23163,8 +36507,10 @@ typedef struct { #define USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_MASK (0xF0000000U) #define USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_SHIFT (28U) #define USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_MASK) +/*! @} */ /*! @name DLL_STATUS - DLL Status */ +/*! @{ */ #define USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_MASK (0x1U) #define USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_SHIFT (0U) #define USDHC_DLL_STATUS_DLL_STS_SLV_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_MASK) @@ -23177,8 +36523,10 @@ typedef struct { #define USDHC_DLL_STATUS_DLL_STS_REF_SEL_MASK (0xFE00U) #define USDHC_DLL_STATUS_DLL_STS_REF_SEL_SHIFT (9U) #define USDHC_DLL_STATUS_DLL_STS_REF_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_REF_SEL_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_REF_SEL_MASK) +/*! @} */ /*! @name CLK_TUNE_CTRL_STATUS - CLK Tuning Control and Status */ +/*! @{ */ #define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_MASK (0xFU) #define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_SHIFT (0U) #define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_MASK) @@ -23203,53 +36551,115 @@ typedef struct { #define USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_MASK (0x80000000U) #define USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_SHIFT (31U) #define USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_MASK) +/*! @} */ /*! @name VEND_SPEC - Vendor Specific Register */ +/*! @{ */ #define USDHC_VEND_SPEC_VSELECT_MASK (0x2U) #define USDHC_VEND_SPEC_VSELECT_SHIFT (1U) +/*! VSELECT - Voltage Selection + * 0b1..Change the voltage to low voltage range, around 1.8 V + * 0b0..Change the voltage to high voltage range, around 3.0 V + */ #define USDHC_VEND_SPEC_VSELECT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_VSELECT_SHIFT)) & USDHC_VEND_SPEC_VSELECT_MASK) #define USDHC_VEND_SPEC_CONFLICT_CHK_EN_MASK (0x4U) #define USDHC_VEND_SPEC_CONFLICT_CHK_EN_SHIFT (2U) +/*! CONFLICT_CHK_EN - Conflict check enable. + * 0b0..Conflict check disable + * 0b1..Conflict check enable + */ #define USDHC_VEND_SPEC_CONFLICT_CHK_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_CONFLICT_CHK_EN_SHIFT)) & USDHC_VEND_SPEC_CONFLICT_CHK_EN_MASK) #define USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_MASK (0x8U) #define USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_SHIFT (3U) +/*! AC12_WR_CHKBUSY_EN - AC12_WR_CHKBUSY_EN + * 0b0..Do not check busy after auto CMD12 for write data packet + * 0b1..Check busy after auto CMD12 for write data packet + */ #define USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_SHIFT)) & USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_MASK) #define USDHC_VEND_SPEC_FRC_SDCLK_ON_MASK (0x100U) #define USDHC_VEND_SPEC_FRC_SDCLK_ON_SHIFT (8U) +/*! FRC_SDCLK_ON - FRC_SDCLK_ON + * 0b0..CLK active or inactive is fully controlled by the hardware. + * 0b1..Force CLK active. + */ #define USDHC_VEND_SPEC_FRC_SDCLK_ON(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_FRC_SDCLK_ON_SHIFT)) & USDHC_VEND_SPEC_FRC_SDCLK_ON_MASK) #define USDHC_VEND_SPEC_CRC_CHK_DIS_MASK (0x8000U) #define USDHC_VEND_SPEC_CRC_CHK_DIS_SHIFT (15U) +/*! CRC_CHK_DIS - CRC Check Disable + * 0b0..Check CRC16 for every read data packet and check CRC bits for every write data packet + * 0b1..Ignore CRC16 check for every read data packet and ignore CRC bits check for every write data packet + */ #define USDHC_VEND_SPEC_CRC_CHK_DIS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_CRC_CHK_DIS_SHIFT)) & USDHC_VEND_SPEC_CRC_CHK_DIS_MASK) #define USDHC_VEND_SPEC_CMD_BYTE_EN_MASK (0x80000000U) #define USDHC_VEND_SPEC_CMD_BYTE_EN_SHIFT (31U) +/*! CMD_BYTE_EN - CMD_BYTE_EN + * 0b0..Disable + * 0b1..Enable + */ #define USDHC_VEND_SPEC_CMD_BYTE_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_CMD_BYTE_EN_SHIFT)) & USDHC_VEND_SPEC_CMD_BYTE_EN_MASK) +/*! @} */ /*! @name MMC_BOOT - MMC Boot Register */ +/*! @{ */ #define USDHC_MMC_BOOT_DTOCV_ACK_MASK (0xFU) #define USDHC_MMC_BOOT_DTOCV_ACK_SHIFT (0U) +/*! DTOCV_ACK - DTOCV_ACK + * 0b0000..SDCLK x 2^14 + * 0b0001..SDCLK x 2^15 + * 0b0010..SDCLK x 2^16 + * 0b0011..SDCLK x 2^17 + * 0b0100..SDCLK x 2^18 + * 0b0101..SDCLK x 2^19 + * 0b0110..SDCLK x 2^20 + * 0b0111..SDCLK x 2^21 + * 0b1110..SDCLK x 2^28 + * 0b1111..SDCLK x 2^29 + */ #define USDHC_MMC_BOOT_DTOCV_ACK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_DTOCV_ACK_SHIFT)) & USDHC_MMC_BOOT_DTOCV_ACK_MASK) #define USDHC_MMC_BOOT_BOOT_ACK_MASK (0x10U) #define USDHC_MMC_BOOT_BOOT_ACK_SHIFT (4U) +/*! BOOT_ACK - BOOT_ACK + * 0b0..No ack + * 0b1..Ack + */ #define USDHC_MMC_BOOT_BOOT_ACK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_ACK_SHIFT)) & USDHC_MMC_BOOT_BOOT_ACK_MASK) #define USDHC_MMC_BOOT_BOOT_MODE_MASK (0x20U) #define USDHC_MMC_BOOT_BOOT_MODE_SHIFT (5U) +/*! BOOT_MODE - BOOT_MODE + * 0b0..Normal boot + * 0b1..Alternative boot + */ #define USDHC_MMC_BOOT_BOOT_MODE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_MODE_SHIFT)) & USDHC_MMC_BOOT_BOOT_MODE_MASK) #define USDHC_MMC_BOOT_BOOT_EN_MASK (0x40U) #define USDHC_MMC_BOOT_BOOT_EN_SHIFT (6U) +/*! BOOT_EN - BOOT_EN + * 0b0..Fast boot disable + * 0b1..Fast boot enable + */ #define USDHC_MMC_BOOT_BOOT_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_EN_SHIFT)) & USDHC_MMC_BOOT_BOOT_EN_MASK) #define USDHC_MMC_BOOT_AUTO_SABG_EN_MASK (0x80U) #define USDHC_MMC_BOOT_AUTO_SABG_EN_SHIFT (7U) #define USDHC_MMC_BOOT_AUTO_SABG_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_AUTO_SABG_EN_SHIFT)) & USDHC_MMC_BOOT_AUTO_SABG_EN_MASK) #define USDHC_MMC_BOOT_DISABLE_TIME_OUT_MASK (0x100U) #define USDHC_MMC_BOOT_DISABLE_TIME_OUT_SHIFT (8U) +/*! DISABLE_TIME_OUT - Disable Time Out + * 0b0..Enable time out + * 0b1..Disable time out + */ #define USDHC_MMC_BOOT_DISABLE_TIME_OUT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_DISABLE_TIME_OUT_SHIFT)) & USDHC_MMC_BOOT_DISABLE_TIME_OUT_MASK) #define USDHC_MMC_BOOT_BOOT_BLK_CNT_MASK (0xFFFF0000U) #define USDHC_MMC_BOOT_BOOT_BLK_CNT_SHIFT (16U) #define USDHC_MMC_BOOT_BOOT_BLK_CNT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_BLK_CNT_SHIFT)) & USDHC_MMC_BOOT_BOOT_BLK_CNT_MASK) +/*! @} */ /*! @name VEND_SPEC2 - Vendor Specific 2 Register */ +/*! @{ */ #define USDHC_VEND_SPEC2_CARD_INT_D3_TEST_MASK (0x8U) #define USDHC_VEND_SPEC2_CARD_INT_D3_TEST_SHIFT (3U) +/*! CARD_INT_D3_TEST - Card Interrupt Detection Test + * 0b0..Check the card interrupt only when DATA3 is high. + * 0b1..Check the card interrupt by ignoring the status of DATA3. + */ #define USDHC_VEND_SPEC2_CARD_INT_D3_TEST(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_CARD_INT_D3_TEST_SHIFT)) & USDHC_VEND_SPEC2_CARD_INT_D3_TEST_MASK) #define USDHC_VEND_SPEC2_TUNING_8bit_EN_MASK (0x10U) #define USDHC_VEND_SPEC2_TUNING_8bit_EN_SHIFT (4U) @@ -23259,15 +36669,28 @@ typedef struct { #define USDHC_VEND_SPEC2_TUNING_1bit_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_TUNING_1bit_EN_SHIFT)) & USDHC_VEND_SPEC2_TUNING_1bit_EN_MASK) #define USDHC_VEND_SPEC2_TUNING_CMD_EN_MASK (0x40U) #define USDHC_VEND_SPEC2_TUNING_CMD_EN_SHIFT (6U) +/*! TUNING_CMD_EN - TUNING_CMD_EN + * 0b0..Auto tuning circuit does not check the CMD line. + * 0b1..Auto tuning circuit checks the CMD line. + */ #define USDHC_VEND_SPEC2_TUNING_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_TUNING_CMD_EN_SHIFT)) & USDHC_VEND_SPEC2_TUNING_CMD_EN_MASK) #define USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_MASK (0x1000U) #define USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_SHIFT (12U) +/*! ACMD23_ARGU2_EN - Argument2 register enable for ACMD23 + * 0b1..Argument2 register enable for ACMD23 sharing with SDMA system address register. Default is enable. + * 0b0..Disable + */ #define USDHC_VEND_SPEC2_ACMD23_ARGU2_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_SHIFT)) & USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_MASK) -#define USDHC_VEND_SPEC2_AHB_RST_MASK (0x4000U) -#define USDHC_VEND_SPEC2_AHB_RST_SHIFT (14U) -#define USDHC_VEND_SPEC2_AHB_RST(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_AHB_RST_SHIFT)) & USDHC_VEND_SPEC2_AHB_RST_MASK) +#define USDHC_VEND_SPEC2_PART_DLL_DEBUG_MASK (0x2000U) +#define USDHC_VEND_SPEC2_PART_DLL_DEBUG_SHIFT (13U) +#define USDHC_VEND_SPEC2_PART_DLL_DEBUG(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_PART_DLL_DEBUG_SHIFT)) & USDHC_VEND_SPEC2_PART_DLL_DEBUG_MASK) +#define USDHC_VEND_SPEC2_BUS_RST_MASK (0x4000U) +#define USDHC_VEND_SPEC2_BUS_RST_SHIFT (14U) +#define USDHC_VEND_SPEC2_BUS_RST(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_BUS_RST_SHIFT)) & USDHC_VEND_SPEC2_BUS_RST_MASK) +/*! @} */ /*! @name TUNING_CTRL - Tuning Control Register */ +/*! @{ */ #define USDHC_TUNING_CTRL_TUNING_START_TAP_MASK (0xFFU) #define USDHC_TUNING_CTRL_TUNING_START_TAP_SHIFT (0U) #define USDHC_TUNING_CTRL_TUNING_START_TAP(x) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_START_TAP_SHIFT)) & USDHC_TUNING_CTRL_TUNING_START_TAP_MASK) @@ -23283,6 +36706,7 @@ typedef struct { #define USDHC_TUNING_CTRL_STD_TUNING_EN_MASK (0x1000000U) #define USDHC_TUNING_CTRL_STD_TUNING_EN_SHIFT (24U) #define USDHC_TUNING_CTRL_STD_TUNING_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_STD_TUNING_EN_SHIFT)) & USDHC_TUNING_CTRL_STD_TUNING_EN_MASK) +/*! @} */ /*! @@ -23339,65 +36763,148 @@ typedef struct { */ /*! @name WCR - Watchdog Control Register */ +/*! @{ */ #define WDOG_WCR_WDZST_MASK (0x1U) #define WDOG_WCR_WDZST_SHIFT (0U) +/*! WDZST - WDZST + * 0b0..Continue timer operation (Default). + * 0b1..Suspend the watchdog timer. + */ #define WDOG_WCR_WDZST(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDZST_SHIFT)) & WDOG_WCR_WDZST_MASK) #define WDOG_WCR_WDBG_MASK (0x2U) #define WDOG_WCR_WDBG_SHIFT (1U) +/*! WDBG - WDBG + * 0b0..Continue WDOG timer operation (Default). + * 0b1..Suspend the watchdog timer. + */ #define WDOG_WCR_WDBG(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDBG_SHIFT)) & WDOG_WCR_WDBG_MASK) #define WDOG_WCR_WDE_MASK (0x4U) #define WDOG_WCR_WDE_SHIFT (2U) +/*! WDE - WDE + * 0b0..Disable the Watchdog (Default). + * 0b1..Enable the Watchdog. + */ #define WDOG_WCR_WDE(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDE_SHIFT)) & WDOG_WCR_WDE_MASK) #define WDOG_WCR_WDT_MASK (0x8U) #define WDOG_WCR_WDT_SHIFT (3U) +/*! WDT - WDT + * 0b0..No effect on WDOG_B (Default). + * 0b1..Assert WDOG_B upon a Watchdog Time-out event. + */ #define WDOG_WCR_WDT(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDT_SHIFT)) & WDOG_WCR_WDT_MASK) #define WDOG_WCR_SRS_MASK (0x10U) #define WDOG_WCR_SRS_SHIFT (4U) +/*! SRS - SRS + * 0b0..Assert system reset signal. + * 0b1..No effect on the system (Default). + */ #define WDOG_WCR_SRS(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_SRS_SHIFT)) & WDOG_WCR_SRS_MASK) #define WDOG_WCR_WDA_MASK (0x20U) #define WDOG_WCR_WDA_SHIFT (5U) +/*! WDA - WDA + * 0b0..Assert WDOG_B output. + * 0b1..No effect on system (Default). + */ #define WDOG_WCR_WDA(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDA_SHIFT)) & WDOG_WCR_WDA_MASK) #define WDOG_WCR_SRE_MASK (0x40U) #define WDOG_WCR_SRE_SHIFT (6U) +/*! SRE - software reset extension, an option way to generate software reset + * 0b0..using original way to generate software reset (default) + * 0b1..using new way to generate software reset. + */ #define WDOG_WCR_SRE(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_SRE_SHIFT)) & WDOG_WCR_SRE_MASK) #define WDOG_WCR_WDW_MASK (0x80U) #define WDOG_WCR_WDW_SHIFT (7U) +/*! WDW - WDW + * 0b0..Continue WDOG timer operation (Default). + * 0b1..Suspend WDOG timer operation. + */ #define WDOG_WCR_WDW(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDW_SHIFT)) & WDOG_WCR_WDW_MASK) #define WDOG_WCR_WT_MASK (0xFF00U) #define WDOG_WCR_WT_SHIFT (8U) +/*! WT - WT + * 0b00000000..- 0.5 Seconds (Default). + * 0b00000001..- 1.0 Seconds. + * 0b00000010..- 1.5 Seconds. + * 0b00000011..- 2.0 Seconds. + * 0b11111111..- 128 Seconds. + */ #define WDOG_WCR_WT(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WT_SHIFT)) & WDOG_WCR_WT_MASK) +/*! @} */ /*! @name WSR - Watchdog Service Register */ +/*! @{ */ #define WDOG_WSR_WSR_MASK (0xFFFFU) #define WDOG_WSR_WSR_SHIFT (0U) +/*! WSR - WSR + * 0b0101010101010101..Write to the Watchdog Service Register (WDOG_WSR). + * 0b1010101010101010..Write to the Watchdog Service Register (WDOG_WSR). + */ #define WDOG_WSR_WSR(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WSR_WSR_SHIFT)) & WDOG_WSR_WSR_MASK) +/*! @} */ /*! @name WRSR - Watchdog Reset Status Register */ +/*! @{ */ #define WDOG_WRSR_SFTW_MASK (0x1U) #define WDOG_WRSR_SFTW_SHIFT (0U) +/*! SFTW - SFTW + * 0b0..Reset is not the result of a software reset. + * 0b1..Reset is the result of a software reset. + */ #define WDOG_WRSR_SFTW(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WRSR_SFTW_SHIFT)) & WDOG_WRSR_SFTW_MASK) #define WDOG_WRSR_TOUT_MASK (0x2U) #define WDOG_WRSR_TOUT_SHIFT (1U) +/*! TOUT - TOUT + * 0b0..Reset is not the result of a WDOG timeout. + * 0b1..Reset is the result of a WDOG timeout. + */ #define WDOG_WRSR_TOUT(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WRSR_TOUT_SHIFT)) & WDOG_WRSR_TOUT_MASK) #define WDOG_WRSR_POR_MASK (0x10U) #define WDOG_WRSR_POR_SHIFT (4U) +/*! POR - POR + * 0b0..Reset is not the result of a power on reset. + * 0b1..Reset is the result of a power on reset. + */ #define WDOG_WRSR_POR(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WRSR_POR_SHIFT)) & WDOG_WRSR_POR_MASK) +/*! @} */ /*! @name WICR - Watchdog Interrupt Control Register */ +/*! @{ */ #define WDOG_WICR_WICT_MASK (0xFFU) #define WDOG_WICR_WICT_SHIFT (0U) +/*! WICT - WICT + * 0b00000000..WICT[7:0] = Time duration between interrupt and time-out is 0 seconds. + * 0b00000001..WICT[7:0] = Time duration between interrupt and time-out is 0.5 seconds. + * 0b00000100..WICT[7:0] = Time duration between interrupt and time-out is 2 seconds (Default). + * 0b11111111..WICT[7:0] = Time duration between interrupt and time-out is 127.5 seconds. + */ #define WDOG_WICR_WICT(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WICR_WICT_SHIFT)) & WDOG_WICR_WICT_MASK) #define WDOG_WICR_WTIS_MASK (0x4000U) #define WDOG_WICR_WTIS_SHIFT (14U) +/*! WTIS - WTIS + * 0b0..No interrupt has occurred (Default). + * 0b1..Interrupt has occurred + */ #define WDOG_WICR_WTIS(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WICR_WTIS_SHIFT)) & WDOG_WICR_WTIS_MASK) #define WDOG_WICR_WIE_MASK (0x8000U) #define WDOG_WICR_WIE_SHIFT (15U) +/*! WIE - WIE + * 0b0..Disable Interrupt (Default). + * 0b1..Enable Interrupt. + */ #define WDOG_WICR_WIE(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WICR_WIE_SHIFT)) & WDOG_WICR_WIE_MASK) +/*! @} */ /*! @name WMCR - Watchdog Miscellaneous Control Register */ +/*! @{ */ #define WDOG_WMCR_PDE_MASK (0x1U) #define WDOG_WMCR_PDE_SHIFT (0U) +/*! PDE - PDE + * 0b0..Power Down Counter of WDOG is disabled. + * 0b1..Power Down Counter of WDOG is enabled (Default). + */ #define WDOG_WMCR_PDE(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WMCR_PDE_SHIFT)) & WDOG_WMCR_PDE_MASK) +/*! @} */ /*! @@ -23517,584 +37024,792 @@ typedef struct { */ /*! @name SEL0 - Crossbar A Select Register 0 */ +/*! @{ */ #define XBARA_SEL0_SEL0_MASK (0x7FU) #define XBARA_SEL0_SEL0_SHIFT (0U) #define XBARA_SEL0_SEL0(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL0_SEL0_SHIFT)) & XBARA_SEL0_SEL0_MASK) #define XBARA_SEL0_SEL1_MASK (0x7F00U) #define XBARA_SEL0_SEL1_SHIFT (8U) #define XBARA_SEL0_SEL1(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL0_SEL1_SHIFT)) & XBARA_SEL0_SEL1_MASK) +/*! @} */ /*! @name SEL1 - Crossbar A Select Register 1 */ +/*! @{ */ #define XBARA_SEL1_SEL2_MASK (0x7FU) #define XBARA_SEL1_SEL2_SHIFT (0U) #define XBARA_SEL1_SEL2(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL1_SEL2_SHIFT)) & XBARA_SEL1_SEL2_MASK) #define XBARA_SEL1_SEL3_MASK (0x7F00U) #define XBARA_SEL1_SEL3_SHIFT (8U) #define XBARA_SEL1_SEL3(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL1_SEL3_SHIFT)) & XBARA_SEL1_SEL3_MASK) +/*! @} */ /*! @name SEL2 - Crossbar A Select Register 2 */ +/*! @{ */ #define XBARA_SEL2_SEL4_MASK (0x7FU) #define XBARA_SEL2_SEL4_SHIFT (0U) #define XBARA_SEL2_SEL4(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL2_SEL4_SHIFT)) & XBARA_SEL2_SEL4_MASK) #define XBARA_SEL2_SEL5_MASK (0x7F00U) #define XBARA_SEL2_SEL5_SHIFT (8U) #define XBARA_SEL2_SEL5(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL2_SEL5_SHIFT)) & XBARA_SEL2_SEL5_MASK) +/*! @} */ /*! @name SEL3 - Crossbar A Select Register 3 */ +/*! @{ */ #define XBARA_SEL3_SEL6_MASK (0x7FU) #define XBARA_SEL3_SEL6_SHIFT (0U) #define XBARA_SEL3_SEL6(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL3_SEL6_SHIFT)) & XBARA_SEL3_SEL6_MASK) #define XBARA_SEL3_SEL7_MASK (0x7F00U) #define XBARA_SEL3_SEL7_SHIFT (8U) #define XBARA_SEL3_SEL7(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL3_SEL7_SHIFT)) & XBARA_SEL3_SEL7_MASK) +/*! @} */ /*! @name SEL4 - Crossbar A Select Register 4 */ +/*! @{ */ #define XBARA_SEL4_SEL8_MASK (0x7FU) #define XBARA_SEL4_SEL8_SHIFT (0U) #define XBARA_SEL4_SEL8(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL4_SEL8_SHIFT)) & XBARA_SEL4_SEL8_MASK) #define XBARA_SEL4_SEL9_MASK (0x7F00U) #define XBARA_SEL4_SEL9_SHIFT (8U) #define XBARA_SEL4_SEL9(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL4_SEL9_SHIFT)) & XBARA_SEL4_SEL9_MASK) +/*! @} */ /*! @name SEL5 - Crossbar A Select Register 5 */ +/*! @{ */ #define XBARA_SEL5_SEL10_MASK (0x7FU) #define XBARA_SEL5_SEL10_SHIFT (0U) #define XBARA_SEL5_SEL10(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL5_SEL10_SHIFT)) & XBARA_SEL5_SEL10_MASK) #define XBARA_SEL5_SEL11_MASK (0x7F00U) #define XBARA_SEL5_SEL11_SHIFT (8U) #define XBARA_SEL5_SEL11(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL5_SEL11_SHIFT)) & XBARA_SEL5_SEL11_MASK) +/*! @} */ /*! @name SEL6 - Crossbar A Select Register 6 */ +/*! @{ */ #define XBARA_SEL6_SEL12_MASK (0x7FU) #define XBARA_SEL6_SEL12_SHIFT (0U) #define XBARA_SEL6_SEL12(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL6_SEL12_SHIFT)) & XBARA_SEL6_SEL12_MASK) #define XBARA_SEL6_SEL13_MASK (0x7F00U) #define XBARA_SEL6_SEL13_SHIFT (8U) #define XBARA_SEL6_SEL13(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL6_SEL13_SHIFT)) & XBARA_SEL6_SEL13_MASK) +/*! @} */ /*! @name SEL7 - Crossbar A Select Register 7 */ +/*! @{ */ #define XBARA_SEL7_SEL14_MASK (0x7FU) #define XBARA_SEL7_SEL14_SHIFT (0U) #define XBARA_SEL7_SEL14(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL7_SEL14_SHIFT)) & XBARA_SEL7_SEL14_MASK) #define XBARA_SEL7_SEL15_MASK (0x7F00U) #define XBARA_SEL7_SEL15_SHIFT (8U) #define XBARA_SEL7_SEL15(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL7_SEL15_SHIFT)) & XBARA_SEL7_SEL15_MASK) +/*! @} */ /*! @name SEL8 - Crossbar A Select Register 8 */ +/*! @{ */ #define XBARA_SEL8_SEL16_MASK (0x7FU) #define XBARA_SEL8_SEL16_SHIFT (0U) #define XBARA_SEL8_SEL16(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL8_SEL16_SHIFT)) & XBARA_SEL8_SEL16_MASK) #define XBARA_SEL8_SEL17_MASK (0x7F00U) #define XBARA_SEL8_SEL17_SHIFT (8U) #define XBARA_SEL8_SEL17(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL8_SEL17_SHIFT)) & XBARA_SEL8_SEL17_MASK) +/*! @} */ /*! @name SEL9 - Crossbar A Select Register 9 */ +/*! @{ */ #define XBARA_SEL9_SEL18_MASK (0x7FU) #define XBARA_SEL9_SEL18_SHIFT (0U) #define XBARA_SEL9_SEL18(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL9_SEL18_SHIFT)) & XBARA_SEL9_SEL18_MASK) #define XBARA_SEL9_SEL19_MASK (0x7F00U) #define XBARA_SEL9_SEL19_SHIFT (8U) #define XBARA_SEL9_SEL19(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL9_SEL19_SHIFT)) & XBARA_SEL9_SEL19_MASK) +/*! @} */ /*! @name SEL10 - Crossbar A Select Register 10 */ +/*! @{ */ #define XBARA_SEL10_SEL20_MASK (0x7FU) #define XBARA_SEL10_SEL20_SHIFT (0U) #define XBARA_SEL10_SEL20(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL10_SEL20_SHIFT)) & XBARA_SEL10_SEL20_MASK) #define XBARA_SEL10_SEL21_MASK (0x7F00U) #define XBARA_SEL10_SEL21_SHIFT (8U) #define XBARA_SEL10_SEL21(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL10_SEL21_SHIFT)) & XBARA_SEL10_SEL21_MASK) +/*! @} */ /*! @name SEL11 - Crossbar A Select Register 11 */ +/*! @{ */ #define XBARA_SEL11_SEL22_MASK (0x7FU) #define XBARA_SEL11_SEL22_SHIFT (0U) #define XBARA_SEL11_SEL22(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL11_SEL22_SHIFT)) & XBARA_SEL11_SEL22_MASK) #define XBARA_SEL11_SEL23_MASK (0x7F00U) #define XBARA_SEL11_SEL23_SHIFT (8U) #define XBARA_SEL11_SEL23(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL11_SEL23_SHIFT)) & XBARA_SEL11_SEL23_MASK) +/*! @} */ /*! @name SEL12 - Crossbar A Select Register 12 */ +/*! @{ */ #define XBARA_SEL12_SEL24_MASK (0x7FU) #define XBARA_SEL12_SEL24_SHIFT (0U) #define XBARA_SEL12_SEL24(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL12_SEL24_SHIFT)) & XBARA_SEL12_SEL24_MASK) #define XBARA_SEL12_SEL25_MASK (0x7F00U) #define XBARA_SEL12_SEL25_SHIFT (8U) #define XBARA_SEL12_SEL25(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL12_SEL25_SHIFT)) & XBARA_SEL12_SEL25_MASK) +/*! @} */ /*! @name SEL13 - Crossbar A Select Register 13 */ +/*! @{ */ #define XBARA_SEL13_SEL26_MASK (0x7FU) #define XBARA_SEL13_SEL26_SHIFT (0U) #define XBARA_SEL13_SEL26(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL13_SEL26_SHIFT)) & XBARA_SEL13_SEL26_MASK) #define XBARA_SEL13_SEL27_MASK (0x7F00U) #define XBARA_SEL13_SEL27_SHIFT (8U) #define XBARA_SEL13_SEL27(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL13_SEL27_SHIFT)) & XBARA_SEL13_SEL27_MASK) +/*! @} */ /*! @name SEL14 - Crossbar A Select Register 14 */ +/*! @{ */ #define XBARA_SEL14_SEL28_MASK (0x7FU) #define XBARA_SEL14_SEL28_SHIFT (0U) #define XBARA_SEL14_SEL28(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL14_SEL28_SHIFT)) & XBARA_SEL14_SEL28_MASK) #define XBARA_SEL14_SEL29_MASK (0x7F00U) #define XBARA_SEL14_SEL29_SHIFT (8U) #define XBARA_SEL14_SEL29(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL14_SEL29_SHIFT)) & XBARA_SEL14_SEL29_MASK) +/*! @} */ /*! @name SEL15 - Crossbar A Select Register 15 */ +/*! @{ */ #define XBARA_SEL15_SEL30_MASK (0x7FU) #define XBARA_SEL15_SEL30_SHIFT (0U) #define XBARA_SEL15_SEL30(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL15_SEL30_SHIFT)) & XBARA_SEL15_SEL30_MASK) #define XBARA_SEL15_SEL31_MASK (0x7F00U) #define XBARA_SEL15_SEL31_SHIFT (8U) #define XBARA_SEL15_SEL31(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL15_SEL31_SHIFT)) & XBARA_SEL15_SEL31_MASK) +/*! @} */ /*! @name SEL16 - Crossbar A Select Register 16 */ +/*! @{ */ #define XBARA_SEL16_SEL32_MASK (0x7FU) #define XBARA_SEL16_SEL32_SHIFT (0U) #define XBARA_SEL16_SEL32(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL16_SEL32_SHIFT)) & XBARA_SEL16_SEL32_MASK) #define XBARA_SEL16_SEL33_MASK (0x7F00U) #define XBARA_SEL16_SEL33_SHIFT (8U) #define XBARA_SEL16_SEL33(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL16_SEL33_SHIFT)) & XBARA_SEL16_SEL33_MASK) +/*! @} */ /*! @name SEL17 - Crossbar A Select Register 17 */ +/*! @{ */ #define XBARA_SEL17_SEL34_MASK (0x7FU) #define XBARA_SEL17_SEL34_SHIFT (0U) #define XBARA_SEL17_SEL34(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL17_SEL34_SHIFT)) & XBARA_SEL17_SEL34_MASK) #define XBARA_SEL17_SEL35_MASK (0x7F00U) #define XBARA_SEL17_SEL35_SHIFT (8U) #define XBARA_SEL17_SEL35(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL17_SEL35_SHIFT)) & XBARA_SEL17_SEL35_MASK) +/*! @} */ /*! @name SEL18 - Crossbar A Select Register 18 */ +/*! @{ */ #define XBARA_SEL18_SEL36_MASK (0x7FU) #define XBARA_SEL18_SEL36_SHIFT (0U) #define XBARA_SEL18_SEL36(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL18_SEL36_SHIFT)) & XBARA_SEL18_SEL36_MASK) #define XBARA_SEL18_SEL37_MASK (0x7F00U) #define XBARA_SEL18_SEL37_SHIFT (8U) #define XBARA_SEL18_SEL37(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL18_SEL37_SHIFT)) & XBARA_SEL18_SEL37_MASK) +/*! @} */ /*! @name SEL19 - Crossbar A Select Register 19 */ +/*! @{ */ #define XBARA_SEL19_SEL38_MASK (0x7FU) #define XBARA_SEL19_SEL38_SHIFT (0U) #define XBARA_SEL19_SEL38(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL19_SEL38_SHIFT)) & XBARA_SEL19_SEL38_MASK) #define XBARA_SEL19_SEL39_MASK (0x7F00U) #define XBARA_SEL19_SEL39_SHIFT (8U) #define XBARA_SEL19_SEL39(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL19_SEL39_SHIFT)) & XBARA_SEL19_SEL39_MASK) +/*! @} */ /*! @name SEL20 - Crossbar A Select Register 20 */ +/*! @{ */ #define XBARA_SEL20_SEL40_MASK (0x7FU) #define XBARA_SEL20_SEL40_SHIFT (0U) #define XBARA_SEL20_SEL40(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL20_SEL40_SHIFT)) & XBARA_SEL20_SEL40_MASK) #define XBARA_SEL20_SEL41_MASK (0x7F00U) #define XBARA_SEL20_SEL41_SHIFT (8U) #define XBARA_SEL20_SEL41(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL20_SEL41_SHIFT)) & XBARA_SEL20_SEL41_MASK) +/*! @} */ /*! @name SEL21 - Crossbar A Select Register 21 */ +/*! @{ */ #define XBARA_SEL21_SEL42_MASK (0x7FU) #define XBARA_SEL21_SEL42_SHIFT (0U) #define XBARA_SEL21_SEL42(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL21_SEL42_SHIFT)) & XBARA_SEL21_SEL42_MASK) #define XBARA_SEL21_SEL43_MASK (0x7F00U) #define XBARA_SEL21_SEL43_SHIFT (8U) #define XBARA_SEL21_SEL43(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL21_SEL43_SHIFT)) & XBARA_SEL21_SEL43_MASK) +/*! @} */ /*! @name SEL22 - Crossbar A Select Register 22 */ +/*! @{ */ #define XBARA_SEL22_SEL44_MASK (0x7FU) #define XBARA_SEL22_SEL44_SHIFT (0U) #define XBARA_SEL22_SEL44(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL22_SEL44_SHIFT)) & XBARA_SEL22_SEL44_MASK) #define XBARA_SEL22_SEL45_MASK (0x7F00U) #define XBARA_SEL22_SEL45_SHIFT (8U) #define XBARA_SEL22_SEL45(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL22_SEL45_SHIFT)) & XBARA_SEL22_SEL45_MASK) +/*! @} */ /*! @name SEL23 - Crossbar A Select Register 23 */ +/*! @{ */ #define XBARA_SEL23_SEL46_MASK (0x7FU) #define XBARA_SEL23_SEL46_SHIFT (0U) #define XBARA_SEL23_SEL46(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL23_SEL46_SHIFT)) & XBARA_SEL23_SEL46_MASK) #define XBARA_SEL23_SEL47_MASK (0x7F00U) #define XBARA_SEL23_SEL47_SHIFT (8U) #define XBARA_SEL23_SEL47(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL23_SEL47_SHIFT)) & XBARA_SEL23_SEL47_MASK) +/*! @} */ /*! @name SEL24 - Crossbar A Select Register 24 */ +/*! @{ */ #define XBARA_SEL24_SEL48_MASK (0x7FU) #define XBARA_SEL24_SEL48_SHIFT (0U) #define XBARA_SEL24_SEL48(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL24_SEL48_SHIFT)) & XBARA_SEL24_SEL48_MASK) #define XBARA_SEL24_SEL49_MASK (0x7F00U) #define XBARA_SEL24_SEL49_SHIFT (8U) #define XBARA_SEL24_SEL49(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL24_SEL49_SHIFT)) & XBARA_SEL24_SEL49_MASK) +/*! @} */ /*! @name SEL25 - Crossbar A Select Register 25 */ +/*! @{ */ #define XBARA_SEL25_SEL50_MASK (0x7FU) #define XBARA_SEL25_SEL50_SHIFT (0U) #define XBARA_SEL25_SEL50(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL25_SEL50_SHIFT)) & XBARA_SEL25_SEL50_MASK) #define XBARA_SEL25_SEL51_MASK (0x7F00U) #define XBARA_SEL25_SEL51_SHIFT (8U) #define XBARA_SEL25_SEL51(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL25_SEL51_SHIFT)) & XBARA_SEL25_SEL51_MASK) +/*! @} */ /*! @name SEL26 - Crossbar A Select Register 26 */ +/*! @{ */ #define XBARA_SEL26_SEL52_MASK (0x7FU) #define XBARA_SEL26_SEL52_SHIFT (0U) #define XBARA_SEL26_SEL52(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL26_SEL52_SHIFT)) & XBARA_SEL26_SEL52_MASK) #define XBARA_SEL26_SEL53_MASK (0x7F00U) #define XBARA_SEL26_SEL53_SHIFT (8U) #define XBARA_SEL26_SEL53(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL26_SEL53_SHIFT)) & XBARA_SEL26_SEL53_MASK) +/*! @} */ /*! @name SEL27 - Crossbar A Select Register 27 */ +/*! @{ */ #define XBARA_SEL27_SEL54_MASK (0x7FU) #define XBARA_SEL27_SEL54_SHIFT (0U) #define XBARA_SEL27_SEL54(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL27_SEL54_SHIFT)) & XBARA_SEL27_SEL54_MASK) #define XBARA_SEL27_SEL55_MASK (0x7F00U) #define XBARA_SEL27_SEL55_SHIFT (8U) #define XBARA_SEL27_SEL55(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL27_SEL55_SHIFT)) & XBARA_SEL27_SEL55_MASK) +/*! @} */ /*! @name SEL28 - Crossbar A Select Register 28 */ +/*! @{ */ #define XBARA_SEL28_SEL56_MASK (0x7FU) #define XBARA_SEL28_SEL56_SHIFT (0U) #define XBARA_SEL28_SEL56(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL28_SEL56_SHIFT)) & XBARA_SEL28_SEL56_MASK) #define XBARA_SEL28_SEL57_MASK (0x7F00U) #define XBARA_SEL28_SEL57_SHIFT (8U) #define XBARA_SEL28_SEL57(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL28_SEL57_SHIFT)) & XBARA_SEL28_SEL57_MASK) +/*! @} */ /*! @name SEL29 - Crossbar A Select Register 29 */ +/*! @{ */ #define XBARA_SEL29_SEL58_MASK (0x7FU) #define XBARA_SEL29_SEL58_SHIFT (0U) #define XBARA_SEL29_SEL58(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL29_SEL58_SHIFT)) & XBARA_SEL29_SEL58_MASK) #define XBARA_SEL29_SEL59_MASK (0x7F00U) #define XBARA_SEL29_SEL59_SHIFT (8U) #define XBARA_SEL29_SEL59(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL29_SEL59_SHIFT)) & XBARA_SEL29_SEL59_MASK) +/*! @} */ /*! @name SEL30 - Crossbar A Select Register 30 */ +/*! @{ */ #define XBARA_SEL30_SEL60_MASK (0x7FU) #define XBARA_SEL30_SEL60_SHIFT (0U) #define XBARA_SEL30_SEL60(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL30_SEL60_SHIFT)) & XBARA_SEL30_SEL60_MASK) #define XBARA_SEL30_SEL61_MASK (0x7F00U) #define XBARA_SEL30_SEL61_SHIFT (8U) #define XBARA_SEL30_SEL61(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL30_SEL61_SHIFT)) & XBARA_SEL30_SEL61_MASK) +/*! @} */ /*! @name SEL31 - Crossbar A Select Register 31 */ +/*! @{ */ #define XBARA_SEL31_SEL62_MASK (0x7FU) #define XBARA_SEL31_SEL62_SHIFT (0U) #define XBARA_SEL31_SEL62(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL31_SEL62_SHIFT)) & XBARA_SEL31_SEL62_MASK) #define XBARA_SEL31_SEL63_MASK (0x7F00U) #define XBARA_SEL31_SEL63_SHIFT (8U) #define XBARA_SEL31_SEL63(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL31_SEL63_SHIFT)) & XBARA_SEL31_SEL63_MASK) +/*! @} */ /*! @name SEL32 - Crossbar A Select Register 32 */ +/*! @{ */ #define XBARA_SEL32_SEL64_MASK (0x7FU) #define XBARA_SEL32_SEL64_SHIFT (0U) #define XBARA_SEL32_SEL64(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL32_SEL64_SHIFT)) & XBARA_SEL32_SEL64_MASK) #define XBARA_SEL32_SEL65_MASK (0x7F00U) #define XBARA_SEL32_SEL65_SHIFT (8U) #define XBARA_SEL32_SEL65(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL32_SEL65_SHIFT)) & XBARA_SEL32_SEL65_MASK) +/*! @} */ /*! @name SEL33 - Crossbar A Select Register 33 */ +/*! @{ */ #define XBARA_SEL33_SEL66_MASK (0x7FU) #define XBARA_SEL33_SEL66_SHIFT (0U) #define XBARA_SEL33_SEL66(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL33_SEL66_SHIFT)) & XBARA_SEL33_SEL66_MASK) #define XBARA_SEL33_SEL67_MASK (0x7F00U) #define XBARA_SEL33_SEL67_SHIFT (8U) #define XBARA_SEL33_SEL67(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL33_SEL67_SHIFT)) & XBARA_SEL33_SEL67_MASK) +/*! @} */ /*! @name SEL34 - Crossbar A Select Register 34 */ +/*! @{ */ #define XBARA_SEL34_SEL68_MASK (0x7FU) #define XBARA_SEL34_SEL68_SHIFT (0U) #define XBARA_SEL34_SEL68(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL34_SEL68_SHIFT)) & XBARA_SEL34_SEL68_MASK) #define XBARA_SEL34_SEL69_MASK (0x7F00U) #define XBARA_SEL34_SEL69_SHIFT (8U) #define XBARA_SEL34_SEL69(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL34_SEL69_SHIFT)) & XBARA_SEL34_SEL69_MASK) +/*! @} */ /*! @name SEL35 - Crossbar A Select Register 35 */ +/*! @{ */ #define XBARA_SEL35_SEL70_MASK (0x7FU) #define XBARA_SEL35_SEL70_SHIFT (0U) #define XBARA_SEL35_SEL70(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL35_SEL70_SHIFT)) & XBARA_SEL35_SEL70_MASK) #define XBARA_SEL35_SEL71_MASK (0x7F00U) #define XBARA_SEL35_SEL71_SHIFT (8U) #define XBARA_SEL35_SEL71(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL35_SEL71_SHIFT)) & XBARA_SEL35_SEL71_MASK) +/*! @} */ /*! @name SEL36 - Crossbar A Select Register 36 */ +/*! @{ */ #define XBARA_SEL36_SEL72_MASK (0x7FU) #define XBARA_SEL36_SEL72_SHIFT (0U) #define XBARA_SEL36_SEL72(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL36_SEL72_SHIFT)) & XBARA_SEL36_SEL72_MASK) #define XBARA_SEL36_SEL73_MASK (0x7F00U) #define XBARA_SEL36_SEL73_SHIFT (8U) #define XBARA_SEL36_SEL73(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL36_SEL73_SHIFT)) & XBARA_SEL36_SEL73_MASK) +/*! @} */ /*! @name SEL37 - Crossbar A Select Register 37 */ +/*! @{ */ #define XBARA_SEL37_SEL74_MASK (0x7FU) #define XBARA_SEL37_SEL74_SHIFT (0U) #define XBARA_SEL37_SEL74(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL37_SEL74_SHIFT)) & XBARA_SEL37_SEL74_MASK) #define XBARA_SEL37_SEL75_MASK (0x7F00U) #define XBARA_SEL37_SEL75_SHIFT (8U) #define XBARA_SEL37_SEL75(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL37_SEL75_SHIFT)) & XBARA_SEL37_SEL75_MASK) +/*! @} */ /*! @name SEL38 - Crossbar A Select Register 38 */ +/*! @{ */ #define XBARA_SEL38_SEL76_MASK (0x7FU) #define XBARA_SEL38_SEL76_SHIFT (0U) #define XBARA_SEL38_SEL76(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL38_SEL76_SHIFT)) & XBARA_SEL38_SEL76_MASK) #define XBARA_SEL38_SEL77_MASK (0x7F00U) #define XBARA_SEL38_SEL77_SHIFT (8U) #define XBARA_SEL38_SEL77(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL38_SEL77_SHIFT)) & XBARA_SEL38_SEL77_MASK) +/*! @} */ /*! @name SEL39 - Crossbar A Select Register 39 */ +/*! @{ */ #define XBARA_SEL39_SEL78_MASK (0x7FU) #define XBARA_SEL39_SEL78_SHIFT (0U) #define XBARA_SEL39_SEL78(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL39_SEL78_SHIFT)) & XBARA_SEL39_SEL78_MASK) #define XBARA_SEL39_SEL79_MASK (0x7F00U) #define XBARA_SEL39_SEL79_SHIFT (8U) #define XBARA_SEL39_SEL79(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL39_SEL79_SHIFT)) & XBARA_SEL39_SEL79_MASK) +/*! @} */ /*! @name SEL40 - Crossbar A Select Register 40 */ +/*! @{ */ #define XBARA_SEL40_SEL80_MASK (0x7FU) #define XBARA_SEL40_SEL80_SHIFT (0U) #define XBARA_SEL40_SEL80(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL40_SEL80_SHIFT)) & XBARA_SEL40_SEL80_MASK) #define XBARA_SEL40_SEL81_MASK (0x7F00U) #define XBARA_SEL40_SEL81_SHIFT (8U) #define XBARA_SEL40_SEL81(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL40_SEL81_SHIFT)) & XBARA_SEL40_SEL81_MASK) +/*! @} */ /*! @name SEL41 - Crossbar A Select Register 41 */ +/*! @{ */ #define XBARA_SEL41_SEL82_MASK (0x7FU) #define XBARA_SEL41_SEL82_SHIFT (0U) #define XBARA_SEL41_SEL82(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL41_SEL82_SHIFT)) & XBARA_SEL41_SEL82_MASK) #define XBARA_SEL41_SEL83_MASK (0x7F00U) #define XBARA_SEL41_SEL83_SHIFT (8U) #define XBARA_SEL41_SEL83(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL41_SEL83_SHIFT)) & XBARA_SEL41_SEL83_MASK) +/*! @} */ /*! @name SEL42 - Crossbar A Select Register 42 */ +/*! @{ */ #define XBARA_SEL42_SEL84_MASK (0x7FU) #define XBARA_SEL42_SEL84_SHIFT (0U) #define XBARA_SEL42_SEL84(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL42_SEL84_SHIFT)) & XBARA_SEL42_SEL84_MASK) #define XBARA_SEL42_SEL85_MASK (0x7F00U) #define XBARA_SEL42_SEL85_SHIFT (8U) #define XBARA_SEL42_SEL85(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL42_SEL85_SHIFT)) & XBARA_SEL42_SEL85_MASK) +/*! @} */ /*! @name SEL43 - Crossbar A Select Register 43 */ +/*! @{ */ #define XBARA_SEL43_SEL86_MASK (0x7FU) #define XBARA_SEL43_SEL86_SHIFT (0U) #define XBARA_SEL43_SEL86(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL43_SEL86_SHIFT)) & XBARA_SEL43_SEL86_MASK) #define XBARA_SEL43_SEL87_MASK (0x7F00U) #define XBARA_SEL43_SEL87_SHIFT (8U) #define XBARA_SEL43_SEL87(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL43_SEL87_SHIFT)) & XBARA_SEL43_SEL87_MASK) +/*! @} */ /*! @name SEL44 - Crossbar A Select Register 44 */ +/*! @{ */ #define XBARA_SEL44_SEL88_MASK (0x7FU) #define XBARA_SEL44_SEL88_SHIFT (0U) #define XBARA_SEL44_SEL88(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL44_SEL88_SHIFT)) & XBARA_SEL44_SEL88_MASK) #define XBARA_SEL44_SEL89_MASK (0x7F00U) #define XBARA_SEL44_SEL89_SHIFT (8U) #define XBARA_SEL44_SEL89(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL44_SEL89_SHIFT)) & XBARA_SEL44_SEL89_MASK) +/*! @} */ /*! @name SEL45 - Crossbar A Select Register 45 */ +/*! @{ */ #define XBARA_SEL45_SEL90_MASK (0x7FU) #define XBARA_SEL45_SEL90_SHIFT (0U) #define XBARA_SEL45_SEL90(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL45_SEL90_SHIFT)) & XBARA_SEL45_SEL90_MASK) #define XBARA_SEL45_SEL91_MASK (0x7F00U) #define XBARA_SEL45_SEL91_SHIFT (8U) #define XBARA_SEL45_SEL91(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL45_SEL91_SHIFT)) & XBARA_SEL45_SEL91_MASK) +/*! @} */ /*! @name SEL46 - Crossbar A Select Register 46 */ +/*! @{ */ #define XBARA_SEL46_SEL92_MASK (0x7FU) #define XBARA_SEL46_SEL92_SHIFT (0U) #define XBARA_SEL46_SEL92(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL46_SEL92_SHIFT)) & XBARA_SEL46_SEL92_MASK) #define XBARA_SEL46_SEL93_MASK (0x7F00U) #define XBARA_SEL46_SEL93_SHIFT (8U) #define XBARA_SEL46_SEL93(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL46_SEL93_SHIFT)) & XBARA_SEL46_SEL93_MASK) +/*! @} */ /*! @name SEL47 - Crossbar A Select Register 47 */ +/*! @{ */ #define XBARA_SEL47_SEL94_MASK (0x7FU) #define XBARA_SEL47_SEL94_SHIFT (0U) #define XBARA_SEL47_SEL94(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL47_SEL94_SHIFT)) & XBARA_SEL47_SEL94_MASK) #define XBARA_SEL47_SEL95_MASK (0x7F00U) #define XBARA_SEL47_SEL95_SHIFT (8U) #define XBARA_SEL47_SEL95(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL47_SEL95_SHIFT)) & XBARA_SEL47_SEL95_MASK) +/*! @} */ /*! @name SEL48 - Crossbar A Select Register 48 */ +/*! @{ */ #define XBARA_SEL48_SEL96_MASK (0x7FU) #define XBARA_SEL48_SEL96_SHIFT (0U) #define XBARA_SEL48_SEL96(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL48_SEL96_SHIFT)) & XBARA_SEL48_SEL96_MASK) #define XBARA_SEL48_SEL97_MASK (0x7F00U) #define XBARA_SEL48_SEL97_SHIFT (8U) #define XBARA_SEL48_SEL97(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL48_SEL97_SHIFT)) & XBARA_SEL48_SEL97_MASK) +/*! @} */ /*! @name SEL49 - Crossbar A Select Register 49 */ +/*! @{ */ #define XBARA_SEL49_SEL98_MASK (0x7FU) #define XBARA_SEL49_SEL98_SHIFT (0U) #define XBARA_SEL49_SEL98(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL49_SEL98_SHIFT)) & XBARA_SEL49_SEL98_MASK) #define XBARA_SEL49_SEL99_MASK (0x7F00U) #define XBARA_SEL49_SEL99_SHIFT (8U) #define XBARA_SEL49_SEL99(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL49_SEL99_SHIFT)) & XBARA_SEL49_SEL99_MASK) +/*! @} */ /*! @name SEL50 - Crossbar A Select Register 50 */ +/*! @{ */ #define XBARA_SEL50_SEL100_MASK (0x7FU) #define XBARA_SEL50_SEL100_SHIFT (0U) #define XBARA_SEL50_SEL100(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL50_SEL100_SHIFT)) & XBARA_SEL50_SEL100_MASK) #define XBARA_SEL50_SEL101_MASK (0x7F00U) #define XBARA_SEL50_SEL101_SHIFT (8U) #define XBARA_SEL50_SEL101(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL50_SEL101_SHIFT)) & XBARA_SEL50_SEL101_MASK) +/*! @} */ /*! @name SEL51 - Crossbar A Select Register 51 */ +/*! @{ */ #define XBARA_SEL51_SEL102_MASK (0x7FU) #define XBARA_SEL51_SEL102_SHIFT (0U) #define XBARA_SEL51_SEL102(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL51_SEL102_SHIFT)) & XBARA_SEL51_SEL102_MASK) #define XBARA_SEL51_SEL103_MASK (0x7F00U) #define XBARA_SEL51_SEL103_SHIFT (8U) #define XBARA_SEL51_SEL103(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL51_SEL103_SHIFT)) & XBARA_SEL51_SEL103_MASK) +/*! @} */ /*! @name SEL52 - Crossbar A Select Register 52 */ +/*! @{ */ #define XBARA_SEL52_SEL104_MASK (0x7FU) #define XBARA_SEL52_SEL104_SHIFT (0U) #define XBARA_SEL52_SEL104(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL52_SEL104_SHIFT)) & XBARA_SEL52_SEL104_MASK) #define XBARA_SEL52_SEL105_MASK (0x7F00U) #define XBARA_SEL52_SEL105_SHIFT (8U) #define XBARA_SEL52_SEL105(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL52_SEL105_SHIFT)) & XBARA_SEL52_SEL105_MASK) +/*! @} */ /*! @name SEL53 - Crossbar A Select Register 53 */ +/*! @{ */ #define XBARA_SEL53_SEL106_MASK (0x7FU) #define XBARA_SEL53_SEL106_SHIFT (0U) #define XBARA_SEL53_SEL106(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL53_SEL106_SHIFT)) & XBARA_SEL53_SEL106_MASK) #define XBARA_SEL53_SEL107_MASK (0x7F00U) #define XBARA_SEL53_SEL107_SHIFT (8U) #define XBARA_SEL53_SEL107(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL53_SEL107_SHIFT)) & XBARA_SEL53_SEL107_MASK) +/*! @} */ /*! @name SEL54 - Crossbar A Select Register 54 */ +/*! @{ */ #define XBARA_SEL54_SEL108_MASK (0x7FU) #define XBARA_SEL54_SEL108_SHIFT (0U) #define XBARA_SEL54_SEL108(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL54_SEL108_SHIFT)) & XBARA_SEL54_SEL108_MASK) #define XBARA_SEL54_SEL109_MASK (0x7F00U) #define XBARA_SEL54_SEL109_SHIFT (8U) #define XBARA_SEL54_SEL109(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL54_SEL109_SHIFT)) & XBARA_SEL54_SEL109_MASK) +/*! @} */ /*! @name SEL55 - Crossbar A Select Register 55 */ +/*! @{ */ #define XBARA_SEL55_SEL110_MASK (0x7FU) #define XBARA_SEL55_SEL110_SHIFT (0U) #define XBARA_SEL55_SEL110(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL55_SEL110_SHIFT)) & XBARA_SEL55_SEL110_MASK) #define XBARA_SEL55_SEL111_MASK (0x7F00U) #define XBARA_SEL55_SEL111_SHIFT (8U) #define XBARA_SEL55_SEL111(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL55_SEL111_SHIFT)) & XBARA_SEL55_SEL111_MASK) +/*! @} */ /*! @name SEL56 - Crossbar A Select Register 56 */ +/*! @{ */ #define XBARA_SEL56_SEL112_MASK (0x7FU) #define XBARA_SEL56_SEL112_SHIFT (0U) #define XBARA_SEL56_SEL112(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL56_SEL112_SHIFT)) & XBARA_SEL56_SEL112_MASK) #define XBARA_SEL56_SEL113_MASK (0x7F00U) #define XBARA_SEL56_SEL113_SHIFT (8U) #define XBARA_SEL56_SEL113(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL56_SEL113_SHIFT)) & XBARA_SEL56_SEL113_MASK) +/*! @} */ /*! @name SEL57 - Crossbar A Select Register 57 */ +/*! @{ */ #define XBARA_SEL57_SEL114_MASK (0x7FU) #define XBARA_SEL57_SEL114_SHIFT (0U) #define XBARA_SEL57_SEL114(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL57_SEL114_SHIFT)) & XBARA_SEL57_SEL114_MASK) #define XBARA_SEL57_SEL115_MASK (0x7F00U) #define XBARA_SEL57_SEL115_SHIFT (8U) #define XBARA_SEL57_SEL115(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL57_SEL115_SHIFT)) & XBARA_SEL57_SEL115_MASK) +/*! @} */ /*! @name SEL58 - Crossbar A Select Register 58 */ +/*! @{ */ #define XBARA_SEL58_SEL116_MASK (0x7FU) #define XBARA_SEL58_SEL116_SHIFT (0U) #define XBARA_SEL58_SEL116(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL58_SEL116_SHIFT)) & XBARA_SEL58_SEL116_MASK) #define XBARA_SEL58_SEL117_MASK (0x7F00U) #define XBARA_SEL58_SEL117_SHIFT (8U) #define XBARA_SEL58_SEL117(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL58_SEL117_SHIFT)) & XBARA_SEL58_SEL117_MASK) +/*! @} */ /*! @name SEL59 - Crossbar A Select Register 59 */ +/*! @{ */ #define XBARA_SEL59_SEL118_MASK (0x7FU) #define XBARA_SEL59_SEL118_SHIFT (0U) #define XBARA_SEL59_SEL118(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL59_SEL118_SHIFT)) & XBARA_SEL59_SEL118_MASK) #define XBARA_SEL59_SEL119_MASK (0x7F00U) #define XBARA_SEL59_SEL119_SHIFT (8U) #define XBARA_SEL59_SEL119(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL59_SEL119_SHIFT)) & XBARA_SEL59_SEL119_MASK) +/*! @} */ /*! @name SEL60 - Crossbar A Select Register 60 */ +/*! @{ */ #define XBARA_SEL60_SEL120_MASK (0x7FU) #define XBARA_SEL60_SEL120_SHIFT (0U) #define XBARA_SEL60_SEL120(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL60_SEL120_SHIFT)) & XBARA_SEL60_SEL120_MASK) #define XBARA_SEL60_SEL121_MASK (0x7F00U) #define XBARA_SEL60_SEL121_SHIFT (8U) #define XBARA_SEL60_SEL121(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL60_SEL121_SHIFT)) & XBARA_SEL60_SEL121_MASK) +/*! @} */ /*! @name SEL61 - Crossbar A Select Register 61 */ +/*! @{ */ #define XBARA_SEL61_SEL122_MASK (0x7FU) #define XBARA_SEL61_SEL122_SHIFT (0U) #define XBARA_SEL61_SEL122(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL61_SEL122_SHIFT)) & XBARA_SEL61_SEL122_MASK) #define XBARA_SEL61_SEL123_MASK (0x7F00U) #define XBARA_SEL61_SEL123_SHIFT (8U) #define XBARA_SEL61_SEL123(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL61_SEL123_SHIFT)) & XBARA_SEL61_SEL123_MASK) +/*! @} */ /*! @name SEL62 - Crossbar A Select Register 62 */ +/*! @{ */ #define XBARA_SEL62_SEL124_MASK (0x7FU) #define XBARA_SEL62_SEL124_SHIFT (0U) #define XBARA_SEL62_SEL124(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL62_SEL124_SHIFT)) & XBARA_SEL62_SEL124_MASK) #define XBARA_SEL62_SEL125_MASK (0x7F00U) #define XBARA_SEL62_SEL125_SHIFT (8U) #define XBARA_SEL62_SEL125(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL62_SEL125_SHIFT)) & XBARA_SEL62_SEL125_MASK) +/*! @} */ /*! @name SEL63 - Crossbar A Select Register 63 */ +/*! @{ */ #define XBARA_SEL63_SEL126_MASK (0x7FU) #define XBARA_SEL63_SEL126_SHIFT (0U) #define XBARA_SEL63_SEL126(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL63_SEL126_SHIFT)) & XBARA_SEL63_SEL126_MASK) #define XBARA_SEL63_SEL127_MASK (0x7F00U) #define XBARA_SEL63_SEL127_SHIFT (8U) #define XBARA_SEL63_SEL127(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL63_SEL127_SHIFT)) & XBARA_SEL63_SEL127_MASK) +/*! @} */ /*! @name SEL64 - Crossbar A Select Register 64 */ +/*! @{ */ #define XBARA_SEL64_SEL128_MASK (0x7FU) #define XBARA_SEL64_SEL128_SHIFT (0U) #define XBARA_SEL64_SEL128(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL64_SEL128_SHIFT)) & XBARA_SEL64_SEL128_MASK) #define XBARA_SEL64_SEL129_MASK (0x7F00U) #define XBARA_SEL64_SEL129_SHIFT (8U) #define XBARA_SEL64_SEL129(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL64_SEL129_SHIFT)) & XBARA_SEL64_SEL129_MASK) +/*! @} */ /*! @name SEL65 - Crossbar A Select Register 65 */ +/*! @{ */ #define XBARA_SEL65_SEL130_MASK (0x7FU) #define XBARA_SEL65_SEL130_SHIFT (0U) #define XBARA_SEL65_SEL130(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL65_SEL130_SHIFT)) & XBARA_SEL65_SEL130_MASK) #define XBARA_SEL65_SEL131_MASK (0x7F00U) #define XBARA_SEL65_SEL131_SHIFT (8U) #define XBARA_SEL65_SEL131(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL65_SEL131_SHIFT)) & XBARA_SEL65_SEL131_MASK) +/*! @} */ /*! @name CTRL0 - Crossbar A Control Register 0 */ +/*! @{ */ #define XBARA_CTRL0_DEN0_MASK (0x1U) #define XBARA_CTRL0_DEN0_SHIFT (0U) +/*! DEN0 - DMA Enable for XBAR_OUT0 + * 0b0..DMA disabled + * 0b1..DMA enabled + */ #define XBARA_CTRL0_DEN0(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_DEN0_SHIFT)) & XBARA_CTRL0_DEN0_MASK) #define XBARA_CTRL0_IEN0_MASK (0x2U) #define XBARA_CTRL0_IEN0_SHIFT (1U) +/*! IEN0 - Interrupt Enable for XBAR_OUT0 + * 0b0..Interrupt disabled + * 0b1..Interrupt enabled + */ #define XBARA_CTRL0_IEN0(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_IEN0_SHIFT)) & XBARA_CTRL0_IEN0_MASK) #define XBARA_CTRL0_EDGE0_MASK (0xCU) #define XBARA_CTRL0_EDGE0_SHIFT (2U) +/*! EDGE0 - Active edge for edge detection on XBAR_OUT0 + * 0b00..STS0 never asserts + * 0b01..STS0 asserts on rising edges of XBAR_OUT0 + * 0b10..STS0 asserts on falling edges of XBAR_OUT0 + * 0b11..STS0 asserts on rising and falling edges of XBAR_OUT0 + */ #define XBARA_CTRL0_EDGE0(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_EDGE0_SHIFT)) & XBARA_CTRL0_EDGE0_MASK) #define XBARA_CTRL0_STS0_MASK (0x10U) #define XBARA_CTRL0_STS0_SHIFT (4U) +/*! STS0 - Edge detection status for XBAR_OUT0 + * 0b0..Active edge not yet detected on XBAR_OUT0 + * 0b1..Active edge detected on XBAR_OUT0 + */ #define XBARA_CTRL0_STS0(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_STS0_SHIFT)) & XBARA_CTRL0_STS0_MASK) #define XBARA_CTRL0_DEN1_MASK (0x100U) #define XBARA_CTRL0_DEN1_SHIFT (8U) +/*! DEN1 - DMA Enable for XBAR_OUT1 + * 0b0..DMA disabled + * 0b1..DMA enabled + */ #define XBARA_CTRL0_DEN1(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_DEN1_SHIFT)) & XBARA_CTRL0_DEN1_MASK) #define XBARA_CTRL0_IEN1_MASK (0x200U) #define XBARA_CTRL0_IEN1_SHIFT (9U) +/*! IEN1 - Interrupt Enable for XBAR_OUT1 + * 0b0..Interrupt disabled + * 0b1..Interrupt enabled + */ #define XBARA_CTRL0_IEN1(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_IEN1_SHIFT)) & XBARA_CTRL0_IEN1_MASK) #define XBARA_CTRL0_EDGE1_MASK (0xC00U) #define XBARA_CTRL0_EDGE1_SHIFT (10U) +/*! EDGE1 - Active edge for edge detection on XBAR_OUT1 + * 0b00..STS1 never asserts + * 0b01..STS1 asserts on rising edges of XBAR_OUT1 + * 0b10..STS1 asserts on falling edges of XBAR_OUT1 + * 0b11..STS1 asserts on rising and falling edges of XBAR_OUT1 + */ #define XBARA_CTRL0_EDGE1(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_EDGE1_SHIFT)) & XBARA_CTRL0_EDGE1_MASK) #define XBARA_CTRL0_STS1_MASK (0x1000U) #define XBARA_CTRL0_STS1_SHIFT (12U) +/*! STS1 - Edge detection status for XBAR_OUT1 + * 0b0..Active edge not yet detected on XBAR_OUT1 + * 0b1..Active edge detected on XBAR_OUT1 + */ #define XBARA_CTRL0_STS1(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_STS1_SHIFT)) & XBARA_CTRL0_STS1_MASK) +/*! @} */ /*! @name CTRL1 - Crossbar A Control Register 1 */ +/*! @{ */ #define XBARA_CTRL1_DEN2_MASK (0x1U) #define XBARA_CTRL1_DEN2_SHIFT (0U) +/*! DEN2 - DMA Enable for XBAR_OUT2 + * 0b0..DMA disabled + * 0b1..DMA enabled + */ #define XBARA_CTRL1_DEN2(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_DEN2_SHIFT)) & XBARA_CTRL1_DEN2_MASK) #define XBARA_CTRL1_IEN2_MASK (0x2U) #define XBARA_CTRL1_IEN2_SHIFT (1U) +/*! IEN2 - Interrupt Enable for XBAR_OUT2 + * 0b0..Interrupt disabled + * 0b1..Interrupt enabled + */ #define XBARA_CTRL1_IEN2(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_IEN2_SHIFT)) & XBARA_CTRL1_IEN2_MASK) #define XBARA_CTRL1_EDGE2_MASK (0xCU) #define XBARA_CTRL1_EDGE2_SHIFT (2U) +/*! EDGE2 - Active edge for edge detection on XBAR_OUT2 + * 0b00..STS2 never asserts + * 0b01..STS2 asserts on rising edges of XBAR_OUT2 + * 0b10..STS2 asserts on falling edges of XBAR_OUT2 + * 0b11..STS2 asserts on rising and falling edges of XBAR_OUT2 + */ #define XBARA_CTRL1_EDGE2(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_EDGE2_SHIFT)) & XBARA_CTRL1_EDGE2_MASK) #define XBARA_CTRL1_STS2_MASK (0x10U) #define XBARA_CTRL1_STS2_SHIFT (4U) +/*! STS2 - Edge detection status for XBAR_OUT2 + * 0b0..Active edge not yet detected on XBAR_OUT2 + * 0b1..Active edge detected on XBAR_OUT2 + */ #define XBARA_CTRL1_STS2(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_STS2_SHIFT)) & XBARA_CTRL1_STS2_MASK) #define XBARA_CTRL1_DEN3_MASK (0x100U) #define XBARA_CTRL1_DEN3_SHIFT (8U) +/*! DEN3 - DMA Enable for XBAR_OUT3 + * 0b0..DMA disabled + * 0b1..DMA enabled + */ #define XBARA_CTRL1_DEN3(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_DEN3_SHIFT)) & XBARA_CTRL1_DEN3_MASK) #define XBARA_CTRL1_IEN3_MASK (0x200U) #define XBARA_CTRL1_IEN3_SHIFT (9U) +/*! IEN3 - Interrupt Enable for XBAR_OUT3 + * 0b0..Interrupt disabled + * 0b1..Interrupt enabled + */ #define XBARA_CTRL1_IEN3(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_IEN3_SHIFT)) & XBARA_CTRL1_IEN3_MASK) #define XBARA_CTRL1_EDGE3_MASK (0xC00U) #define XBARA_CTRL1_EDGE3_SHIFT (10U) +/*! EDGE3 - Active edge for edge detection on XBAR_OUT3 + * 0b00..STS3 never asserts + * 0b01..STS3 asserts on rising edges of XBAR_OUT3 + * 0b10..STS3 asserts on falling edges of XBAR_OUT3 + * 0b11..STS3 asserts on rising and falling edges of XBAR_OUT3 + */ #define XBARA_CTRL1_EDGE3(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_EDGE3_SHIFT)) & XBARA_CTRL1_EDGE3_MASK) #define XBARA_CTRL1_STS3_MASK (0x1000U) #define XBARA_CTRL1_STS3_SHIFT (12U) +/*! STS3 - Edge detection status for XBAR_OUT3 + * 0b0..Active edge not yet detected on XBAR_OUT3 + * 0b1..Active edge detected on XBAR_OUT3 + */ #define XBARA_CTRL1_STS3(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_STS3_SHIFT)) & XBARA_CTRL1_STS3_MASK) +/*! @} */ /*! @@ -24148,68 +37863,84 @@ typedef struct { */ /*! @name SEL0 - Crossbar B Select Register 0 */ +/*! @{ */ #define XBARB_SEL0_SEL0_MASK (0x3FU) #define XBARB_SEL0_SEL0_SHIFT (0U) #define XBARB_SEL0_SEL0(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL0_SEL0_SHIFT)) & XBARB_SEL0_SEL0_MASK) #define XBARB_SEL0_SEL1_MASK (0x3F00U) #define XBARB_SEL0_SEL1_SHIFT (8U) #define XBARB_SEL0_SEL1(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL0_SEL1_SHIFT)) & XBARB_SEL0_SEL1_MASK) +/*! @} */ /*! @name SEL1 - Crossbar B Select Register 1 */ +/*! @{ */ #define XBARB_SEL1_SEL2_MASK (0x3FU) #define XBARB_SEL1_SEL2_SHIFT (0U) #define XBARB_SEL1_SEL2(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL1_SEL2_SHIFT)) & XBARB_SEL1_SEL2_MASK) #define XBARB_SEL1_SEL3_MASK (0x3F00U) #define XBARB_SEL1_SEL3_SHIFT (8U) #define XBARB_SEL1_SEL3(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL1_SEL3_SHIFT)) & XBARB_SEL1_SEL3_MASK) +/*! @} */ /*! @name SEL2 - Crossbar B Select Register 2 */ +/*! @{ */ #define XBARB_SEL2_SEL4_MASK (0x3FU) #define XBARB_SEL2_SEL4_SHIFT (0U) #define XBARB_SEL2_SEL4(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL2_SEL4_SHIFT)) & XBARB_SEL2_SEL4_MASK) #define XBARB_SEL2_SEL5_MASK (0x3F00U) #define XBARB_SEL2_SEL5_SHIFT (8U) #define XBARB_SEL2_SEL5(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL2_SEL5_SHIFT)) & XBARB_SEL2_SEL5_MASK) +/*! @} */ /*! @name SEL3 - Crossbar B Select Register 3 */ +/*! @{ */ #define XBARB_SEL3_SEL6_MASK (0x3FU) #define XBARB_SEL3_SEL6_SHIFT (0U) #define XBARB_SEL3_SEL6(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL3_SEL6_SHIFT)) & XBARB_SEL3_SEL6_MASK) #define XBARB_SEL3_SEL7_MASK (0x3F00U) #define XBARB_SEL3_SEL7_SHIFT (8U) #define XBARB_SEL3_SEL7(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL3_SEL7_SHIFT)) & XBARB_SEL3_SEL7_MASK) +/*! @} */ /*! @name SEL4 - Crossbar B Select Register 4 */ +/*! @{ */ #define XBARB_SEL4_SEL8_MASK (0x3FU) #define XBARB_SEL4_SEL8_SHIFT (0U) #define XBARB_SEL4_SEL8(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL4_SEL8_SHIFT)) & XBARB_SEL4_SEL8_MASK) #define XBARB_SEL4_SEL9_MASK (0x3F00U) #define XBARB_SEL4_SEL9_SHIFT (8U) #define XBARB_SEL4_SEL9(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL4_SEL9_SHIFT)) & XBARB_SEL4_SEL9_MASK) +/*! @} */ /*! @name SEL5 - Crossbar B Select Register 5 */ +/*! @{ */ #define XBARB_SEL5_SEL10_MASK (0x3FU) #define XBARB_SEL5_SEL10_SHIFT (0U) #define XBARB_SEL5_SEL10(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL5_SEL10_SHIFT)) & XBARB_SEL5_SEL10_MASK) #define XBARB_SEL5_SEL11_MASK (0x3F00U) #define XBARB_SEL5_SEL11_SHIFT (8U) #define XBARB_SEL5_SEL11(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL5_SEL11_SHIFT)) & XBARB_SEL5_SEL11_MASK) +/*! @} */ /*! @name SEL6 - Crossbar B Select Register 6 */ +/*! @{ */ #define XBARB_SEL6_SEL12_MASK (0x3FU) #define XBARB_SEL6_SEL12_SHIFT (0U) #define XBARB_SEL6_SEL12(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL6_SEL12_SHIFT)) & XBARB_SEL6_SEL12_MASK) #define XBARB_SEL6_SEL13_MASK (0x3F00U) #define XBARB_SEL6_SEL13_SHIFT (8U) #define XBARB_SEL6_SEL13(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL6_SEL13_SHIFT)) & XBARB_SEL6_SEL13_MASK) +/*! @} */ /*! @name SEL7 - Crossbar B Select Register 7 */ +/*! @{ */ #define XBARB_SEL7_SEL14_MASK (0x3FU) #define XBARB_SEL7_SEL14_SHIFT (0U) #define XBARB_SEL7_SEL14(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL7_SEL14_SHIFT)) & XBARB_SEL7_SEL14_MASK) #define XBARB_SEL7_SEL15_MASK (0x3F00U) #define XBARB_SEL7_SEL15_SHIFT (8U) #define XBARB_SEL7_SEL15(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL7_SEL15_SHIFT)) & XBARB_SEL7_SEL15_MASK) +/*! @} */ /*! @@ -24282,26 +38013,57 @@ typedef struct { */ /*! @name MISC0 - Miscellaneous Register 0 */ +/*! @{ */ #define XTALOSC24M_MISC0_REFTOP_PWD_MASK (0x1U) #define XTALOSC24M_MISC0_REFTOP_PWD_SHIFT (0U) #define XTALOSC24M_MISC0_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_REFTOP_PWD_SHIFT)) & XTALOSC24M_MISC0_REFTOP_PWD_MASK) #define XTALOSC24M_MISC0_REFTOP_SELFBIASOFF_MASK (0x8U) #define XTALOSC24M_MISC0_REFTOP_SELFBIASOFF_SHIFT (3U) +/*! REFTOP_SELFBIASOFF + * 0b0..Uses coarse bias currents for startup + * 0b1..Uses bandgap-based bias currents for best performance. + */ #define XTALOSC24M_MISC0_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_REFTOP_SELFBIASOFF_SHIFT)) & XTALOSC24M_MISC0_REFTOP_SELFBIASOFF_MASK) #define XTALOSC24M_MISC0_REFTOP_VBGADJ_MASK (0x70U) #define XTALOSC24M_MISC0_REFTOP_VBGADJ_SHIFT (4U) +/*! REFTOP_VBGADJ + * 0b000..Nominal VBG + * 0b001..VBG+0.78% + * 0b010..VBG+1.56% + * 0b011..VBG+2.34% + * 0b100..VBG-0.78% + * 0b101..VBG-1.56% + * 0b110..VBG-2.34% + * 0b111..VBG-3.12% + */ #define XTALOSC24M_MISC0_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_REFTOP_VBGADJ_SHIFT)) & XTALOSC24M_MISC0_REFTOP_VBGADJ_MASK) #define XTALOSC24M_MISC0_REFTOP_VBGUP_MASK (0x80U) #define XTALOSC24M_MISC0_REFTOP_VBGUP_SHIFT (7U) #define XTALOSC24M_MISC0_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_REFTOP_VBGUP_SHIFT)) & XTALOSC24M_MISC0_REFTOP_VBGUP_MASK) #define XTALOSC24M_MISC0_STOP_MODE_CONFIG_MASK (0xC00U) #define XTALOSC24M_MISC0_STOP_MODE_CONFIG_SHIFT (10U) +/*! STOP_MODE_CONFIG + * 0b00..All analog except rtc powered down on stop mode assertion. XtalOsc=on, RCOsc=off; + * 0b01..Certain analog functions such as certain regulators left up. XtalOsc=on, RCOsc=off; + * 0b10..XtalOsc=off, RCOsc=on, Old BG=on, New BG=off. + * 0b11..XtalOsc=off, RCOsc=on, Old BG=off, New BG=on. + */ #define XTALOSC24M_MISC0_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_STOP_MODE_CONFIG_SHIFT)) & XTALOSC24M_MISC0_STOP_MODE_CONFIG_MASK) #define XTALOSC24M_MISC0_DISCON_HIGH_SNVS_MASK (0x1000U) #define XTALOSC24M_MISC0_DISCON_HIGH_SNVS_SHIFT (12U) +/*! DISCON_HIGH_SNVS + * 0b0..Turn on the switch + * 0b1..Turn off the switch + */ #define XTALOSC24M_MISC0_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_DISCON_HIGH_SNVS_SHIFT)) & XTALOSC24M_MISC0_DISCON_HIGH_SNVS_MASK) #define XTALOSC24M_MISC0_OSC_I_MASK (0x6000U) #define XTALOSC24M_MISC0_OSC_I_SHIFT (13U) +/*! OSC_I + * 0b00..Nominal + * 0b01..Decrease current by 12.5% + * 0b10..Decrease current by 25.0% + * 0b11..Decrease current by 37.5% + */ #define XTALOSC24M_MISC0_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_OSC_I_SHIFT)) & XTALOSC24M_MISC0_OSC_I_MASK) #define XTALOSC24M_MISC0_OSC_XTALOK_MASK (0x8000U) #define XTALOSC24M_MISC0_OSC_XTALOK_SHIFT (15U) @@ -24311,41 +38073,95 @@ typedef struct { #define XTALOSC24M_MISC0_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_OSC_XTALOK_EN_SHIFT)) & XTALOSC24M_MISC0_OSC_XTALOK_EN_MASK) #define XTALOSC24M_MISC0_CLKGATE_CTRL_MASK (0x2000000U) #define XTALOSC24M_MISC0_CLKGATE_CTRL_SHIFT (25U) +/*! CLKGATE_CTRL + * 0b0..Allow the logic to automatically gate the clock when the XTAL is powered down. + * 0b1..Prevent the logic from ever gating off the clock. + */ #define XTALOSC24M_MISC0_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLKGATE_CTRL_SHIFT)) & XTALOSC24M_MISC0_CLKGATE_CTRL_MASK) #define XTALOSC24M_MISC0_CLKGATE_DELAY_MASK (0x1C000000U) #define XTALOSC24M_MISC0_CLKGATE_DELAY_SHIFT (26U) +/*! CLKGATE_DELAY + * 0b000..0.5ms + * 0b001..1.0ms + * 0b010..2.0ms + * 0b011..3.0ms + * 0b100..4.0ms + * 0b101..5.0ms + * 0b110..6.0ms + * 0b111..7.0ms + */ #define XTALOSC24M_MISC0_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLKGATE_DELAY_SHIFT)) & XTALOSC24M_MISC0_CLKGATE_DELAY_MASK) #define XTALOSC24M_MISC0_RTC_XTAL_SOURCE_MASK (0x20000000U) #define XTALOSC24M_MISC0_RTC_XTAL_SOURCE_SHIFT (29U) +/*! RTC_XTAL_SOURCE + * 0b0..Internal ring oscillator + * 0b1..RTC_XTAL + */ #define XTALOSC24M_MISC0_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_RTC_XTAL_SOURCE_SHIFT)) & XTALOSC24M_MISC0_RTC_XTAL_SOURCE_MASK) #define XTALOSC24M_MISC0_XTAL_24M_PWD_MASK (0x40000000U) #define XTALOSC24M_MISC0_XTAL_24M_PWD_SHIFT (30U) #define XTALOSC24M_MISC0_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_XTAL_24M_PWD_SHIFT)) & XTALOSC24M_MISC0_XTAL_24M_PWD_MASK) #define XTALOSC24M_MISC0_VID_PLL_PREDIV_MASK (0x80000000U) #define XTALOSC24M_MISC0_VID_PLL_PREDIV_SHIFT (31U) +/*! VID_PLL_PREDIV + * 0b0..Divide by 1 + * 0b1..Divide by 2 + */ #define XTALOSC24M_MISC0_VID_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_VID_PLL_PREDIV_SHIFT)) & XTALOSC24M_MISC0_VID_PLL_PREDIV_MASK) +/*! @} */ /*! @name MISC0_SET - Miscellaneous Register 0 */ +/*! @{ */ #define XTALOSC24M_MISC0_SET_REFTOP_PWD_MASK (0x1U) #define XTALOSC24M_MISC0_SET_REFTOP_PWD_SHIFT (0U) #define XTALOSC24M_MISC0_SET_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_REFTOP_PWD_SHIFT)) & XTALOSC24M_MISC0_SET_REFTOP_PWD_MASK) #define XTALOSC24M_MISC0_SET_REFTOP_SELFBIASOFF_MASK (0x8U) #define XTALOSC24M_MISC0_SET_REFTOP_SELFBIASOFF_SHIFT (3U) +/*! REFTOP_SELFBIASOFF + * 0b0..Uses coarse bias currents for startup + * 0b1..Uses bandgap-based bias currents for best performance. + */ #define XTALOSC24M_MISC0_SET_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_REFTOP_SELFBIASOFF_SHIFT)) & XTALOSC24M_MISC0_SET_REFTOP_SELFBIASOFF_MASK) #define XTALOSC24M_MISC0_SET_REFTOP_VBGADJ_MASK (0x70U) #define XTALOSC24M_MISC0_SET_REFTOP_VBGADJ_SHIFT (4U) +/*! REFTOP_VBGADJ + * 0b000..Nominal VBG + * 0b001..VBG+0.78% + * 0b010..VBG+1.56% + * 0b011..VBG+2.34% + * 0b100..VBG-0.78% + * 0b101..VBG-1.56% + * 0b110..VBG-2.34% + * 0b111..VBG-3.12% + */ #define XTALOSC24M_MISC0_SET_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_REFTOP_VBGADJ_SHIFT)) & XTALOSC24M_MISC0_SET_REFTOP_VBGADJ_MASK) #define XTALOSC24M_MISC0_SET_REFTOP_VBGUP_MASK (0x80U) #define XTALOSC24M_MISC0_SET_REFTOP_VBGUP_SHIFT (7U) #define XTALOSC24M_MISC0_SET_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_REFTOP_VBGUP_SHIFT)) & XTALOSC24M_MISC0_SET_REFTOP_VBGUP_MASK) #define XTALOSC24M_MISC0_SET_STOP_MODE_CONFIG_MASK (0xC00U) #define XTALOSC24M_MISC0_SET_STOP_MODE_CONFIG_SHIFT (10U) +/*! STOP_MODE_CONFIG + * 0b00..All analog except rtc powered down on stop mode assertion. XtalOsc=on, RCOsc=off; + * 0b01..Certain analog functions such as certain regulators left up. XtalOsc=on, RCOsc=off; + * 0b10..XtalOsc=off, RCOsc=on, Old BG=on, New BG=off. + * 0b11..XtalOsc=off, RCOsc=on, Old BG=off, New BG=on. + */ #define XTALOSC24M_MISC0_SET_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_STOP_MODE_CONFIG_SHIFT)) & XTALOSC24M_MISC0_SET_STOP_MODE_CONFIG_MASK) #define XTALOSC24M_MISC0_SET_DISCON_HIGH_SNVS_MASK (0x1000U) #define XTALOSC24M_MISC0_SET_DISCON_HIGH_SNVS_SHIFT (12U) +/*! DISCON_HIGH_SNVS + * 0b0..Turn on the switch + * 0b1..Turn off the switch + */ #define XTALOSC24M_MISC0_SET_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_DISCON_HIGH_SNVS_SHIFT)) & XTALOSC24M_MISC0_SET_DISCON_HIGH_SNVS_MASK) #define XTALOSC24M_MISC0_SET_OSC_I_MASK (0x6000U) #define XTALOSC24M_MISC0_SET_OSC_I_SHIFT (13U) +/*! OSC_I + * 0b00..Nominal + * 0b01..Decrease current by 12.5% + * 0b10..Decrease current by 25.0% + * 0b11..Decrease current by 37.5% + */ #define XTALOSC24M_MISC0_SET_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_OSC_I_SHIFT)) & XTALOSC24M_MISC0_SET_OSC_I_MASK) #define XTALOSC24M_MISC0_SET_OSC_XTALOK_MASK (0x8000U) #define XTALOSC24M_MISC0_SET_OSC_XTALOK_SHIFT (15U) @@ -24355,41 +38171,95 @@ typedef struct { #define XTALOSC24M_MISC0_SET_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_OSC_XTALOK_EN_SHIFT)) & XTALOSC24M_MISC0_SET_OSC_XTALOK_EN_MASK) #define XTALOSC24M_MISC0_SET_CLKGATE_CTRL_MASK (0x2000000U) #define XTALOSC24M_MISC0_SET_CLKGATE_CTRL_SHIFT (25U) +/*! CLKGATE_CTRL + * 0b0..Allow the logic to automatically gate the clock when the XTAL is powered down. + * 0b1..Prevent the logic from ever gating off the clock. + */ #define XTALOSC24M_MISC0_SET_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_CLKGATE_CTRL_SHIFT)) & XTALOSC24M_MISC0_SET_CLKGATE_CTRL_MASK) #define XTALOSC24M_MISC0_SET_CLKGATE_DELAY_MASK (0x1C000000U) #define XTALOSC24M_MISC0_SET_CLKGATE_DELAY_SHIFT (26U) +/*! CLKGATE_DELAY + * 0b000..0.5ms + * 0b001..1.0ms + * 0b010..2.0ms + * 0b011..3.0ms + * 0b100..4.0ms + * 0b101..5.0ms + * 0b110..6.0ms + * 0b111..7.0ms + */ #define XTALOSC24M_MISC0_SET_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_CLKGATE_DELAY_SHIFT)) & XTALOSC24M_MISC0_SET_CLKGATE_DELAY_MASK) #define XTALOSC24M_MISC0_SET_RTC_XTAL_SOURCE_MASK (0x20000000U) #define XTALOSC24M_MISC0_SET_RTC_XTAL_SOURCE_SHIFT (29U) +/*! RTC_XTAL_SOURCE + * 0b0..Internal ring oscillator + * 0b1..RTC_XTAL + */ #define XTALOSC24M_MISC0_SET_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_RTC_XTAL_SOURCE_SHIFT)) & XTALOSC24M_MISC0_SET_RTC_XTAL_SOURCE_MASK) #define XTALOSC24M_MISC0_SET_XTAL_24M_PWD_MASK (0x40000000U) #define XTALOSC24M_MISC0_SET_XTAL_24M_PWD_SHIFT (30U) #define XTALOSC24M_MISC0_SET_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_XTAL_24M_PWD_SHIFT)) & XTALOSC24M_MISC0_SET_XTAL_24M_PWD_MASK) #define XTALOSC24M_MISC0_SET_VID_PLL_PREDIV_MASK (0x80000000U) #define XTALOSC24M_MISC0_SET_VID_PLL_PREDIV_SHIFT (31U) +/*! VID_PLL_PREDIV + * 0b0..Divide by 1 + * 0b1..Divide by 2 + */ #define XTALOSC24M_MISC0_SET_VID_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_VID_PLL_PREDIV_SHIFT)) & XTALOSC24M_MISC0_SET_VID_PLL_PREDIV_MASK) +/*! @} */ /*! @name MISC0_CLR - Miscellaneous Register 0 */ +/*! @{ */ #define XTALOSC24M_MISC0_CLR_REFTOP_PWD_MASK (0x1U) #define XTALOSC24M_MISC0_CLR_REFTOP_PWD_SHIFT (0U) #define XTALOSC24M_MISC0_CLR_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_REFTOP_PWD_SHIFT)) & XTALOSC24M_MISC0_CLR_REFTOP_PWD_MASK) #define XTALOSC24M_MISC0_CLR_REFTOP_SELFBIASOFF_MASK (0x8U) #define XTALOSC24M_MISC0_CLR_REFTOP_SELFBIASOFF_SHIFT (3U) +/*! REFTOP_SELFBIASOFF + * 0b0..Uses coarse bias currents for startup + * 0b1..Uses bandgap-based bias currents for best performance. + */ #define XTALOSC24M_MISC0_CLR_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_REFTOP_SELFBIASOFF_SHIFT)) & XTALOSC24M_MISC0_CLR_REFTOP_SELFBIASOFF_MASK) #define XTALOSC24M_MISC0_CLR_REFTOP_VBGADJ_MASK (0x70U) #define XTALOSC24M_MISC0_CLR_REFTOP_VBGADJ_SHIFT (4U) +/*! REFTOP_VBGADJ + * 0b000..Nominal VBG + * 0b001..VBG+0.78% + * 0b010..VBG+1.56% + * 0b011..VBG+2.34% + * 0b100..VBG-0.78% + * 0b101..VBG-1.56% + * 0b110..VBG-2.34% + * 0b111..VBG-3.12% + */ #define XTALOSC24M_MISC0_CLR_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_REFTOP_VBGADJ_SHIFT)) & XTALOSC24M_MISC0_CLR_REFTOP_VBGADJ_MASK) #define XTALOSC24M_MISC0_CLR_REFTOP_VBGUP_MASK (0x80U) #define XTALOSC24M_MISC0_CLR_REFTOP_VBGUP_SHIFT (7U) #define XTALOSC24M_MISC0_CLR_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_REFTOP_VBGUP_SHIFT)) & XTALOSC24M_MISC0_CLR_REFTOP_VBGUP_MASK) #define XTALOSC24M_MISC0_CLR_STOP_MODE_CONFIG_MASK (0xC00U) #define XTALOSC24M_MISC0_CLR_STOP_MODE_CONFIG_SHIFT (10U) +/*! STOP_MODE_CONFIG + * 0b00..All analog except rtc powered down on stop mode assertion. XtalOsc=on, RCOsc=off; + * 0b01..Certain analog functions such as certain regulators left up. XtalOsc=on, RCOsc=off; + * 0b10..XtalOsc=off, RCOsc=on, Old BG=on, New BG=off. + * 0b11..XtalOsc=off, RCOsc=on, Old BG=off, New BG=on. + */ #define XTALOSC24M_MISC0_CLR_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_STOP_MODE_CONFIG_SHIFT)) & XTALOSC24M_MISC0_CLR_STOP_MODE_CONFIG_MASK) #define XTALOSC24M_MISC0_CLR_DISCON_HIGH_SNVS_MASK (0x1000U) #define XTALOSC24M_MISC0_CLR_DISCON_HIGH_SNVS_SHIFT (12U) +/*! DISCON_HIGH_SNVS + * 0b0..Turn on the switch + * 0b1..Turn off the switch + */ #define XTALOSC24M_MISC0_CLR_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_DISCON_HIGH_SNVS_SHIFT)) & XTALOSC24M_MISC0_CLR_DISCON_HIGH_SNVS_MASK) #define XTALOSC24M_MISC0_CLR_OSC_I_MASK (0x6000U) #define XTALOSC24M_MISC0_CLR_OSC_I_SHIFT (13U) +/*! OSC_I + * 0b00..Nominal + * 0b01..Decrease current by 12.5% + * 0b10..Decrease current by 25.0% + * 0b11..Decrease current by 37.5% + */ #define XTALOSC24M_MISC0_CLR_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_OSC_I_SHIFT)) & XTALOSC24M_MISC0_CLR_OSC_I_MASK) #define XTALOSC24M_MISC0_CLR_OSC_XTALOK_MASK (0x8000U) #define XTALOSC24M_MISC0_CLR_OSC_XTALOK_SHIFT (15U) @@ -24399,41 +38269,95 @@ typedef struct { #define XTALOSC24M_MISC0_CLR_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_OSC_XTALOK_EN_SHIFT)) & XTALOSC24M_MISC0_CLR_OSC_XTALOK_EN_MASK) #define XTALOSC24M_MISC0_CLR_CLKGATE_CTRL_MASK (0x2000000U) #define XTALOSC24M_MISC0_CLR_CLKGATE_CTRL_SHIFT (25U) +/*! CLKGATE_CTRL + * 0b0..Allow the logic to automatically gate the clock when the XTAL is powered down. + * 0b1..Prevent the logic from ever gating off the clock. + */ #define XTALOSC24M_MISC0_CLR_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_CLKGATE_CTRL_SHIFT)) & XTALOSC24M_MISC0_CLR_CLKGATE_CTRL_MASK) #define XTALOSC24M_MISC0_CLR_CLKGATE_DELAY_MASK (0x1C000000U) #define XTALOSC24M_MISC0_CLR_CLKGATE_DELAY_SHIFT (26U) +/*! CLKGATE_DELAY + * 0b000..0.5ms + * 0b001..1.0ms + * 0b010..2.0ms + * 0b011..3.0ms + * 0b100..4.0ms + * 0b101..5.0ms + * 0b110..6.0ms + * 0b111..7.0ms + */ #define XTALOSC24M_MISC0_CLR_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_CLKGATE_DELAY_SHIFT)) & XTALOSC24M_MISC0_CLR_CLKGATE_DELAY_MASK) #define XTALOSC24M_MISC0_CLR_RTC_XTAL_SOURCE_MASK (0x20000000U) #define XTALOSC24M_MISC0_CLR_RTC_XTAL_SOURCE_SHIFT (29U) +/*! RTC_XTAL_SOURCE + * 0b0..Internal ring oscillator + * 0b1..RTC_XTAL + */ #define XTALOSC24M_MISC0_CLR_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_RTC_XTAL_SOURCE_SHIFT)) & XTALOSC24M_MISC0_CLR_RTC_XTAL_SOURCE_MASK) #define XTALOSC24M_MISC0_CLR_XTAL_24M_PWD_MASK (0x40000000U) #define XTALOSC24M_MISC0_CLR_XTAL_24M_PWD_SHIFT (30U) #define XTALOSC24M_MISC0_CLR_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_XTAL_24M_PWD_SHIFT)) & XTALOSC24M_MISC0_CLR_XTAL_24M_PWD_MASK) #define XTALOSC24M_MISC0_CLR_VID_PLL_PREDIV_MASK (0x80000000U) #define XTALOSC24M_MISC0_CLR_VID_PLL_PREDIV_SHIFT (31U) +/*! VID_PLL_PREDIV + * 0b0..Divide by 1 + * 0b1..Divide by 2 + */ #define XTALOSC24M_MISC0_CLR_VID_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_VID_PLL_PREDIV_SHIFT)) & XTALOSC24M_MISC0_CLR_VID_PLL_PREDIV_MASK) +/*! @} */ /*! @name MISC0_TOG - Miscellaneous Register 0 */ +/*! @{ */ #define XTALOSC24M_MISC0_TOG_REFTOP_PWD_MASK (0x1U) #define XTALOSC24M_MISC0_TOG_REFTOP_PWD_SHIFT (0U) #define XTALOSC24M_MISC0_TOG_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_REFTOP_PWD_SHIFT)) & XTALOSC24M_MISC0_TOG_REFTOP_PWD_MASK) #define XTALOSC24M_MISC0_TOG_REFTOP_SELFBIASOFF_MASK (0x8U) #define XTALOSC24M_MISC0_TOG_REFTOP_SELFBIASOFF_SHIFT (3U) +/*! REFTOP_SELFBIASOFF + * 0b0..Uses coarse bias currents for startup + * 0b1..Uses bandgap-based bias currents for best performance. + */ #define XTALOSC24M_MISC0_TOG_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_REFTOP_SELFBIASOFF_SHIFT)) & XTALOSC24M_MISC0_TOG_REFTOP_SELFBIASOFF_MASK) #define XTALOSC24M_MISC0_TOG_REFTOP_VBGADJ_MASK (0x70U) #define XTALOSC24M_MISC0_TOG_REFTOP_VBGADJ_SHIFT (4U) +/*! REFTOP_VBGADJ + * 0b000..Nominal VBG + * 0b001..VBG+0.78% + * 0b010..VBG+1.56% + * 0b011..VBG+2.34% + * 0b100..VBG-0.78% + * 0b101..VBG-1.56% + * 0b110..VBG-2.34% + * 0b111..VBG-3.12% + */ #define XTALOSC24M_MISC0_TOG_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_REFTOP_VBGADJ_SHIFT)) & XTALOSC24M_MISC0_TOG_REFTOP_VBGADJ_MASK) #define XTALOSC24M_MISC0_TOG_REFTOP_VBGUP_MASK (0x80U) #define XTALOSC24M_MISC0_TOG_REFTOP_VBGUP_SHIFT (7U) #define XTALOSC24M_MISC0_TOG_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_REFTOP_VBGUP_SHIFT)) & XTALOSC24M_MISC0_TOG_REFTOP_VBGUP_MASK) #define XTALOSC24M_MISC0_TOG_STOP_MODE_CONFIG_MASK (0xC00U) #define XTALOSC24M_MISC0_TOG_STOP_MODE_CONFIG_SHIFT (10U) +/*! STOP_MODE_CONFIG + * 0b00..All analog except rtc powered down on stop mode assertion. XtalOsc=on, RCOsc=off; + * 0b01..Certain analog functions such as certain regulators left up. XtalOsc=on, RCOsc=off; + * 0b10..XtalOsc=off, RCOsc=on, Old BG=on, New BG=off. + * 0b11..XtalOsc=off, RCOsc=on, Old BG=off, New BG=on. + */ #define XTALOSC24M_MISC0_TOG_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_STOP_MODE_CONFIG_SHIFT)) & XTALOSC24M_MISC0_TOG_STOP_MODE_CONFIG_MASK) #define XTALOSC24M_MISC0_TOG_DISCON_HIGH_SNVS_MASK (0x1000U) #define XTALOSC24M_MISC0_TOG_DISCON_HIGH_SNVS_SHIFT (12U) +/*! DISCON_HIGH_SNVS + * 0b0..Turn on the switch + * 0b1..Turn off the switch + */ #define XTALOSC24M_MISC0_TOG_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_DISCON_HIGH_SNVS_SHIFT)) & XTALOSC24M_MISC0_TOG_DISCON_HIGH_SNVS_MASK) #define XTALOSC24M_MISC0_TOG_OSC_I_MASK (0x6000U) #define XTALOSC24M_MISC0_TOG_OSC_I_SHIFT (13U) +/*! OSC_I + * 0b00..Nominal + * 0b01..Decrease current by 12.5% + * 0b10..Decrease current by 25.0% + * 0b11..Decrease current by 37.5% + */ #define XTALOSC24M_MISC0_TOG_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_OSC_I_SHIFT)) & XTALOSC24M_MISC0_TOG_OSC_I_MASK) #define XTALOSC24M_MISC0_TOG_OSC_XTALOK_MASK (0x8000U) #define XTALOSC24M_MISC0_TOG_OSC_XTALOK_SHIFT (15U) @@ -24443,32 +38367,65 @@ typedef struct { #define XTALOSC24M_MISC0_TOG_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_OSC_XTALOK_EN_SHIFT)) & XTALOSC24M_MISC0_TOG_OSC_XTALOK_EN_MASK) #define XTALOSC24M_MISC0_TOG_CLKGATE_CTRL_MASK (0x2000000U) #define XTALOSC24M_MISC0_TOG_CLKGATE_CTRL_SHIFT (25U) +/*! CLKGATE_CTRL + * 0b0..Allow the logic to automatically gate the clock when the XTAL is powered down. + * 0b1..Prevent the logic from ever gating off the clock. + */ #define XTALOSC24M_MISC0_TOG_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_CLKGATE_CTRL_SHIFT)) & XTALOSC24M_MISC0_TOG_CLKGATE_CTRL_MASK) #define XTALOSC24M_MISC0_TOG_CLKGATE_DELAY_MASK (0x1C000000U) #define XTALOSC24M_MISC0_TOG_CLKGATE_DELAY_SHIFT (26U) +/*! CLKGATE_DELAY + * 0b000..0.5ms + * 0b001..1.0ms + * 0b010..2.0ms + * 0b011..3.0ms + * 0b100..4.0ms + * 0b101..5.0ms + * 0b110..6.0ms + * 0b111..7.0ms + */ #define XTALOSC24M_MISC0_TOG_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_CLKGATE_DELAY_SHIFT)) & XTALOSC24M_MISC0_TOG_CLKGATE_DELAY_MASK) #define XTALOSC24M_MISC0_TOG_RTC_XTAL_SOURCE_MASK (0x20000000U) #define XTALOSC24M_MISC0_TOG_RTC_XTAL_SOURCE_SHIFT (29U) +/*! RTC_XTAL_SOURCE + * 0b0..Internal ring oscillator + * 0b1..RTC_XTAL + */ #define XTALOSC24M_MISC0_TOG_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_RTC_XTAL_SOURCE_SHIFT)) & XTALOSC24M_MISC0_TOG_RTC_XTAL_SOURCE_MASK) #define XTALOSC24M_MISC0_TOG_XTAL_24M_PWD_MASK (0x40000000U) #define XTALOSC24M_MISC0_TOG_XTAL_24M_PWD_SHIFT (30U) #define XTALOSC24M_MISC0_TOG_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_XTAL_24M_PWD_SHIFT)) & XTALOSC24M_MISC0_TOG_XTAL_24M_PWD_MASK) #define XTALOSC24M_MISC0_TOG_VID_PLL_PREDIV_MASK (0x80000000U) #define XTALOSC24M_MISC0_TOG_VID_PLL_PREDIV_SHIFT (31U) +/*! VID_PLL_PREDIV + * 0b0..Divide by 1 + * 0b1..Divide by 2 + */ #define XTALOSC24M_MISC0_TOG_VID_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_VID_PLL_PREDIV_SHIFT)) & XTALOSC24M_MISC0_TOG_VID_PLL_PREDIV_MASK) +/*! @} */ /*! @name LOWPWR_CTRL - XTAL OSC (LP) Control Register */ +/*! @{ */ #define XTALOSC24M_LOWPWR_CTRL_RC_OSC_EN_MASK (0x1U) #define XTALOSC24M_LOWPWR_CTRL_RC_OSC_EN_SHIFT (0U) +/*! RC_OSC_EN + * 0b0..Use XTAL OSC to source the 24MHz clock + * 0b1..Use RC OSC + */ #define XTALOSC24M_LOWPWR_CTRL_RC_OSC_EN(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_RC_OSC_EN_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_RC_OSC_EN_MASK) -#define XTALOSC24M_LOWPWR_CTRL_RC_OSC_PROG_MASK (0xEU) -#define XTALOSC24M_LOWPWR_CTRL_RC_OSC_PROG_SHIFT (1U) -#define XTALOSC24M_LOWPWR_CTRL_RC_OSC_PROG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_RC_OSC_PROG_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_RC_OSC_PROG_MASK) #define XTALOSC24M_LOWPWR_CTRL_OSC_SEL_MASK (0x10U) #define XTALOSC24M_LOWPWR_CTRL_OSC_SEL_SHIFT (4U) +/*! OSC_SEL + * 0b0..XTAL OSC + * 0b1..RC OSC + */ #define XTALOSC24M_LOWPWR_CTRL_OSC_SEL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_OSC_SEL_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_OSC_SEL_MASK) #define XTALOSC24M_LOWPWR_CTRL_LPBG_SEL_MASK (0x20U) #define XTALOSC24M_LOWPWR_CTRL_LPBG_SEL_SHIFT (5U) +/*! LPBG_SEL + * 0b0..Normal power bandgap + * 0b1..Low power bandgap + */ #define XTALOSC24M_LOWPWR_CTRL_LPBG_SEL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_LPBG_SEL_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_LPBG_SEL_MASK) #define XTALOSC24M_LOWPWR_CTRL_LPBG_TEST_MASK (0x40U) #define XTALOSC24M_LOWPWR_CTRL_LPBG_TEST_SHIFT (6U) @@ -24493,26 +38450,50 @@ typedef struct { #define XTALOSC24M_LOWPWR_CTRL_RCOSC_CG_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_RCOSC_CG_OVERRIDE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_RCOSC_CG_OVERRIDE_MASK) #define XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_DELAY_MASK (0xC000U) #define XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_DELAY_SHIFT (14U) +/*! XTALOSC_PWRUP_DELAY + * 0b00..0.25ms + * 0b01..0.5ms + * 0b10..1ms + * 0b11..2ms + */ #define XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_DELAY(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_DELAY_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_DELAY_MASK) #define XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_STAT_MASK (0x10000U) #define XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_STAT_SHIFT (16U) +/*! XTALOSC_PWRUP_STAT + * 0b0..Not stable + * 0b1..Stable and ready to use + */ #define XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_STAT(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_STAT_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_STAT_MASK) #define XTALOSC24M_LOWPWR_CTRL_MIX_PWRGATE_MASK (0x20000U) #define XTALOSC24M_LOWPWR_CTRL_MIX_PWRGATE_SHIFT (17U) #define XTALOSC24M_LOWPWR_CTRL_MIX_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_MIX_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_MIX_PWRGATE_MASK) +#define XTALOSC24M_LOWPWR_CTRL_GPU_PWRGATE_MASK (0x40000U) +#define XTALOSC24M_LOWPWR_CTRL_GPU_PWRGATE_SHIFT (18U) +#define XTALOSC24M_LOWPWR_CTRL_GPU_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_GPU_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_GPU_PWRGATE_MASK) +/*! @} */ /*! @name LOWPWR_CTRL_SET - XTAL OSC (LP) Control Register */ +/*! @{ */ #define XTALOSC24M_LOWPWR_CTRL_SET_RC_OSC_EN_MASK (0x1U) #define XTALOSC24M_LOWPWR_CTRL_SET_RC_OSC_EN_SHIFT (0U) +/*! RC_OSC_EN + * 0b0..Use XTAL OSC to source the 24MHz clock + * 0b1..Use RC OSC + */ #define XTALOSC24M_LOWPWR_CTRL_SET_RC_OSC_EN(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_RC_OSC_EN_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_RC_OSC_EN_MASK) -#define XTALOSC24M_LOWPWR_CTRL_SET_RC_OSC_PROG_MASK (0xEU) -#define XTALOSC24M_LOWPWR_CTRL_SET_RC_OSC_PROG_SHIFT (1U) -#define XTALOSC24M_LOWPWR_CTRL_SET_RC_OSC_PROG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_RC_OSC_PROG_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_RC_OSC_PROG_MASK) #define XTALOSC24M_LOWPWR_CTRL_SET_OSC_SEL_MASK (0x10U) #define XTALOSC24M_LOWPWR_CTRL_SET_OSC_SEL_SHIFT (4U) +/*! OSC_SEL + * 0b0..XTAL OSC + * 0b1..RC OSC + */ #define XTALOSC24M_LOWPWR_CTRL_SET_OSC_SEL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_OSC_SEL_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_OSC_SEL_MASK) #define XTALOSC24M_LOWPWR_CTRL_SET_LPBG_SEL_MASK (0x20U) #define XTALOSC24M_LOWPWR_CTRL_SET_LPBG_SEL_SHIFT (5U) +/*! LPBG_SEL + * 0b0..Normal power bandgap + * 0b1..Low power bandgap + */ #define XTALOSC24M_LOWPWR_CTRL_SET_LPBG_SEL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_LPBG_SEL_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_LPBG_SEL_MASK) #define XTALOSC24M_LOWPWR_CTRL_SET_LPBG_TEST_MASK (0x40U) #define XTALOSC24M_LOWPWR_CTRL_SET_LPBG_TEST_SHIFT (6U) @@ -24537,26 +38518,50 @@ typedef struct { #define XTALOSC24M_LOWPWR_CTRL_SET_RCOSC_CG_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_RCOSC_CG_OVERRIDE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_RCOSC_CG_OVERRIDE_MASK) #define XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_DELAY_MASK (0xC000U) #define XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_DELAY_SHIFT (14U) +/*! XTALOSC_PWRUP_DELAY + * 0b00..0.25ms + * 0b01..0.5ms + * 0b10..1ms + * 0b11..2ms + */ #define XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_DELAY(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_DELAY_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_DELAY_MASK) #define XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_STAT_MASK (0x10000U) #define XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_STAT_SHIFT (16U) +/*! XTALOSC_PWRUP_STAT + * 0b0..Not stable + * 0b1..Stable and ready to use + */ #define XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_STAT(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_STAT_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_STAT_MASK) #define XTALOSC24M_LOWPWR_CTRL_SET_MIX_PWRGATE_MASK (0x20000U) #define XTALOSC24M_LOWPWR_CTRL_SET_MIX_PWRGATE_SHIFT (17U) #define XTALOSC24M_LOWPWR_CTRL_SET_MIX_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_MIX_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_MIX_PWRGATE_MASK) +#define XTALOSC24M_LOWPWR_CTRL_SET_GPU_PWRGATE_MASK (0x40000U) +#define XTALOSC24M_LOWPWR_CTRL_SET_GPU_PWRGATE_SHIFT (18U) +#define XTALOSC24M_LOWPWR_CTRL_SET_GPU_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_GPU_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_GPU_PWRGATE_MASK) +/*! @} */ /*! @name LOWPWR_CTRL_CLR - XTAL OSC (LP) Control Register */ +/*! @{ */ #define XTALOSC24M_LOWPWR_CTRL_CLR_RC_OSC_EN_MASK (0x1U) #define XTALOSC24M_LOWPWR_CTRL_CLR_RC_OSC_EN_SHIFT (0U) +/*! RC_OSC_EN + * 0b0..Use XTAL OSC to source the 24MHz clock + * 0b1..Use RC OSC + */ #define XTALOSC24M_LOWPWR_CTRL_CLR_RC_OSC_EN(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_RC_OSC_EN_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_RC_OSC_EN_MASK) -#define XTALOSC24M_LOWPWR_CTRL_CLR_RC_OSC_PROG_MASK (0xEU) -#define XTALOSC24M_LOWPWR_CTRL_CLR_RC_OSC_PROG_SHIFT (1U) -#define XTALOSC24M_LOWPWR_CTRL_CLR_RC_OSC_PROG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_RC_OSC_PROG_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_RC_OSC_PROG_MASK) #define XTALOSC24M_LOWPWR_CTRL_CLR_OSC_SEL_MASK (0x10U) #define XTALOSC24M_LOWPWR_CTRL_CLR_OSC_SEL_SHIFT (4U) +/*! OSC_SEL + * 0b0..XTAL OSC + * 0b1..RC OSC + */ #define XTALOSC24M_LOWPWR_CTRL_CLR_OSC_SEL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_OSC_SEL_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_OSC_SEL_MASK) #define XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_SEL_MASK (0x20U) #define XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_SEL_SHIFT (5U) +/*! LPBG_SEL + * 0b0..Normal power bandgap + * 0b1..Low power bandgap + */ #define XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_SEL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_SEL_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_SEL_MASK) #define XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_TEST_MASK (0x40U) #define XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_TEST_SHIFT (6U) @@ -24581,26 +38586,50 @@ typedef struct { #define XTALOSC24M_LOWPWR_CTRL_CLR_RCOSC_CG_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_RCOSC_CG_OVERRIDE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_RCOSC_CG_OVERRIDE_MASK) #define XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_DELAY_MASK (0xC000U) #define XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_DELAY_SHIFT (14U) +/*! XTALOSC_PWRUP_DELAY + * 0b00..0.25ms + * 0b01..0.5ms + * 0b10..1ms + * 0b11..2ms + */ #define XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_DELAY(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_DELAY_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_DELAY_MASK) #define XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_STAT_MASK (0x10000U) #define XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_STAT_SHIFT (16U) +/*! XTALOSC_PWRUP_STAT + * 0b0..Not stable + * 0b1..Stable and ready to use + */ #define XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_STAT(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_STAT_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_STAT_MASK) #define XTALOSC24M_LOWPWR_CTRL_CLR_MIX_PWRGATE_MASK (0x20000U) #define XTALOSC24M_LOWPWR_CTRL_CLR_MIX_PWRGATE_SHIFT (17U) #define XTALOSC24M_LOWPWR_CTRL_CLR_MIX_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_MIX_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_MIX_PWRGATE_MASK) +#define XTALOSC24M_LOWPWR_CTRL_CLR_GPU_PWRGATE_MASK (0x40000U) +#define XTALOSC24M_LOWPWR_CTRL_CLR_GPU_PWRGATE_SHIFT (18U) +#define XTALOSC24M_LOWPWR_CTRL_CLR_GPU_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_GPU_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_GPU_PWRGATE_MASK) +/*! @} */ /*! @name LOWPWR_CTRL_TOG - XTAL OSC (LP) Control Register */ +/*! @{ */ #define XTALOSC24M_LOWPWR_CTRL_TOG_RC_OSC_EN_MASK (0x1U) #define XTALOSC24M_LOWPWR_CTRL_TOG_RC_OSC_EN_SHIFT (0U) +/*! RC_OSC_EN + * 0b0..Use XTAL OSC to source the 24MHz clock + * 0b1..Use RC OSC + */ #define XTALOSC24M_LOWPWR_CTRL_TOG_RC_OSC_EN(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_RC_OSC_EN_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_RC_OSC_EN_MASK) -#define XTALOSC24M_LOWPWR_CTRL_TOG_RC_OSC_PROG_MASK (0xEU) -#define XTALOSC24M_LOWPWR_CTRL_TOG_RC_OSC_PROG_SHIFT (1U) -#define XTALOSC24M_LOWPWR_CTRL_TOG_RC_OSC_PROG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_RC_OSC_PROG_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_RC_OSC_PROG_MASK) #define XTALOSC24M_LOWPWR_CTRL_TOG_OSC_SEL_MASK (0x10U) #define XTALOSC24M_LOWPWR_CTRL_TOG_OSC_SEL_SHIFT (4U) +/*! OSC_SEL + * 0b0..XTAL OSC + * 0b1..RC OSC + */ #define XTALOSC24M_LOWPWR_CTRL_TOG_OSC_SEL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_OSC_SEL_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_OSC_SEL_MASK) #define XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_SEL_MASK (0x20U) #define XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_SEL_SHIFT (5U) +/*! LPBG_SEL + * 0b0..Normal power bandgap + * 0b1..Low power bandgap + */ #define XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_SEL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_SEL_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_SEL_MASK) #define XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_TEST_MASK (0x40U) #define XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_TEST_SHIFT (6U) @@ -24625,15 +38654,30 @@ typedef struct { #define XTALOSC24M_LOWPWR_CTRL_TOG_RCOSC_CG_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_RCOSC_CG_OVERRIDE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_RCOSC_CG_OVERRIDE_MASK) #define XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_DELAY_MASK (0xC000U) #define XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_DELAY_SHIFT (14U) +/*! XTALOSC_PWRUP_DELAY + * 0b00..0.25ms + * 0b01..0.5ms + * 0b10..1ms + * 0b11..2ms + */ #define XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_DELAY(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_DELAY_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_DELAY_MASK) #define XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_STAT_MASK (0x10000U) #define XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_STAT_SHIFT (16U) +/*! XTALOSC_PWRUP_STAT + * 0b0..Not stable + * 0b1..Stable and ready to use + */ #define XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_STAT(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_STAT_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_STAT_MASK) #define XTALOSC24M_LOWPWR_CTRL_TOG_MIX_PWRGATE_MASK (0x20000U) #define XTALOSC24M_LOWPWR_CTRL_TOG_MIX_PWRGATE_SHIFT (17U) #define XTALOSC24M_LOWPWR_CTRL_TOG_MIX_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_MIX_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_MIX_PWRGATE_MASK) +#define XTALOSC24M_LOWPWR_CTRL_TOG_GPU_PWRGATE_MASK (0x40000U) +#define XTALOSC24M_LOWPWR_CTRL_TOG_GPU_PWRGATE_SHIFT (18U) +#define XTALOSC24M_LOWPWR_CTRL_TOG_GPU_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_GPU_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_GPU_PWRGATE_MASK) +/*! @} */ /*! @name OSC_CONFIG0 - XTAL OSC Configuration 0 Register */ +/*! @{ */ #define XTALOSC24M_OSC_CONFIG0_START_MASK (0x1U) #define XTALOSC24M_OSC_CONFIG0_START_SHIFT (0U) #define XTALOSC24M_OSC_CONFIG0_START(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_START_SHIFT)) & XTALOSC24M_OSC_CONFIG0_START_MASK) @@ -24658,8 +38702,10 @@ typedef struct { #define XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_CUR_MASK (0xFF000000U) #define XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_CUR_SHIFT (24U) #define XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_CUR(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_CUR_SHIFT)) & XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_CUR_MASK) +/*! @} */ /*! @name OSC_CONFIG0_SET - XTAL OSC Configuration 0 Register */ +/*! @{ */ #define XTALOSC24M_OSC_CONFIG0_SET_START_MASK (0x1U) #define XTALOSC24M_OSC_CONFIG0_SET_START_SHIFT (0U) #define XTALOSC24M_OSC_CONFIG0_SET_START(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_SET_START_SHIFT)) & XTALOSC24M_OSC_CONFIG0_SET_START_MASK) @@ -24684,8 +38730,10 @@ typedef struct { #define XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_CUR_MASK (0xFF000000U) #define XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_CUR_SHIFT (24U) #define XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_CUR(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_CUR_SHIFT)) & XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_CUR_MASK) +/*! @} */ /*! @name OSC_CONFIG0_CLR - XTAL OSC Configuration 0 Register */ +/*! @{ */ #define XTALOSC24M_OSC_CONFIG0_CLR_START_MASK (0x1U) #define XTALOSC24M_OSC_CONFIG0_CLR_START_SHIFT (0U) #define XTALOSC24M_OSC_CONFIG0_CLR_START(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_CLR_START_SHIFT)) & XTALOSC24M_OSC_CONFIG0_CLR_START_MASK) @@ -24710,8 +38758,10 @@ typedef struct { #define XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_CUR_MASK (0xFF000000U) #define XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_CUR_SHIFT (24U) #define XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_CUR(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_CUR_SHIFT)) & XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_CUR_MASK) +/*! @} */ /*! @name OSC_CONFIG0_TOG - XTAL OSC Configuration 0 Register */ +/*! @{ */ #define XTALOSC24M_OSC_CONFIG0_TOG_START_MASK (0x1U) #define XTALOSC24M_OSC_CONFIG0_TOG_START_SHIFT (0U) #define XTALOSC24M_OSC_CONFIG0_TOG_START(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_TOG_START_SHIFT)) & XTALOSC24M_OSC_CONFIG0_TOG_START_MASK) @@ -24736,40 +38786,50 @@ typedef struct { #define XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_CUR_MASK (0xFF000000U) #define XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_CUR_SHIFT (24U) #define XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_CUR(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_CUR_SHIFT)) & XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_CUR_MASK) +/*! @} */ /*! @name OSC_CONFIG1 - XTAL OSC Configuration 1 Register */ +/*! @{ */ #define XTALOSC24M_OSC_CONFIG1_COUNT_RC_TRG_MASK (0xFFFU) #define XTALOSC24M_OSC_CONFIG1_COUNT_RC_TRG_SHIFT (0U) #define XTALOSC24M_OSC_CONFIG1_COUNT_RC_TRG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG1_COUNT_RC_TRG_SHIFT)) & XTALOSC24M_OSC_CONFIG1_COUNT_RC_TRG_MASK) #define XTALOSC24M_OSC_CONFIG1_COUNT_RC_CUR_MASK (0xFFF00000U) #define XTALOSC24M_OSC_CONFIG1_COUNT_RC_CUR_SHIFT (20U) #define XTALOSC24M_OSC_CONFIG1_COUNT_RC_CUR(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG1_COUNT_RC_CUR_SHIFT)) & XTALOSC24M_OSC_CONFIG1_COUNT_RC_CUR_MASK) +/*! @} */ /*! @name OSC_CONFIG1_SET - XTAL OSC Configuration 1 Register */ +/*! @{ */ #define XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_TRG_MASK (0xFFFU) #define XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_TRG_SHIFT (0U) #define XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_TRG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_TRG_SHIFT)) & XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_TRG_MASK) #define XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_CUR_MASK (0xFFF00000U) #define XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_CUR_SHIFT (20U) #define XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_CUR(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_CUR_SHIFT)) & XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_CUR_MASK) +/*! @} */ /*! @name OSC_CONFIG1_CLR - XTAL OSC Configuration 1 Register */ +/*! @{ */ #define XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_TRG_MASK (0xFFFU) #define XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_TRG_SHIFT (0U) #define XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_TRG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_TRG_SHIFT)) & XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_TRG_MASK) #define XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_CUR_MASK (0xFFF00000U) #define XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_CUR_SHIFT (20U) #define XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_CUR(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_CUR_SHIFT)) & XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_CUR_MASK) +/*! @} */ /*! @name OSC_CONFIG1_TOG - XTAL OSC Configuration 1 Register */ +/*! @{ */ #define XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_TRG_MASK (0xFFFU) #define XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_TRG_SHIFT (0U) #define XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_TRG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_TRG_SHIFT)) & XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_TRG_MASK) #define XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_CUR_MASK (0xFFF00000U) #define XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_CUR_SHIFT (20U) #define XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_CUR(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_CUR_SHIFT)) & XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_CUR_MASK) +/*! @} */ /*! @name OSC_CONFIG2 - XTAL OSC Configuration 2 Register */ +/*! @{ */ #define XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG_MASK (0xFFFU) #define XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG_SHIFT (0U) #define XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG_SHIFT)) & XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG_MASK) @@ -24782,8 +38842,10 @@ typedef struct { #define XTALOSC24M_OSC_CONFIG2_CLK_1M_ERR_FL_MASK (0x80000000U) #define XTALOSC24M_OSC_CONFIG2_CLK_1M_ERR_FL_SHIFT (31U) #define XTALOSC24M_OSC_CONFIG2_CLK_1M_ERR_FL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_CLK_1M_ERR_FL_SHIFT)) & XTALOSC24M_OSC_CONFIG2_CLK_1M_ERR_FL_MASK) +/*! @} */ /*! @name OSC_CONFIG2_SET - XTAL OSC Configuration 2 Register */ +/*! @{ */ #define XTALOSC24M_OSC_CONFIG2_SET_COUNT_1M_TRG_MASK (0xFFFU) #define XTALOSC24M_OSC_CONFIG2_SET_COUNT_1M_TRG_SHIFT (0U) #define XTALOSC24M_OSC_CONFIG2_SET_COUNT_1M_TRG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_SET_COUNT_1M_TRG_SHIFT)) & XTALOSC24M_OSC_CONFIG2_SET_COUNT_1M_TRG_MASK) @@ -24796,8 +38858,10 @@ typedef struct { #define XTALOSC24M_OSC_CONFIG2_SET_CLK_1M_ERR_FL_MASK (0x80000000U) #define XTALOSC24M_OSC_CONFIG2_SET_CLK_1M_ERR_FL_SHIFT (31U) #define XTALOSC24M_OSC_CONFIG2_SET_CLK_1M_ERR_FL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_SET_CLK_1M_ERR_FL_SHIFT)) & XTALOSC24M_OSC_CONFIG2_SET_CLK_1M_ERR_FL_MASK) +/*! @} */ /*! @name OSC_CONFIG2_CLR - XTAL OSC Configuration 2 Register */ +/*! @{ */ #define XTALOSC24M_OSC_CONFIG2_CLR_COUNT_1M_TRG_MASK (0xFFFU) #define XTALOSC24M_OSC_CONFIG2_CLR_COUNT_1M_TRG_SHIFT (0U) #define XTALOSC24M_OSC_CONFIG2_CLR_COUNT_1M_TRG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_CLR_COUNT_1M_TRG_SHIFT)) & XTALOSC24M_OSC_CONFIG2_CLR_COUNT_1M_TRG_MASK) @@ -24810,8 +38874,10 @@ typedef struct { #define XTALOSC24M_OSC_CONFIG2_CLR_CLK_1M_ERR_FL_MASK (0x80000000U) #define XTALOSC24M_OSC_CONFIG2_CLR_CLK_1M_ERR_FL_SHIFT (31U) #define XTALOSC24M_OSC_CONFIG2_CLR_CLK_1M_ERR_FL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_CLR_CLK_1M_ERR_FL_SHIFT)) & XTALOSC24M_OSC_CONFIG2_CLR_CLK_1M_ERR_FL_MASK) +/*! @} */ /*! @name OSC_CONFIG2_TOG - XTAL OSC Configuration 2 Register */ +/*! @{ */ #define XTALOSC24M_OSC_CONFIG2_TOG_COUNT_1M_TRG_MASK (0xFFFU) #define XTALOSC24M_OSC_CONFIG2_TOG_COUNT_1M_TRG_SHIFT (0U) #define XTALOSC24M_OSC_CONFIG2_TOG_COUNT_1M_TRG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_TOG_COUNT_1M_TRG_SHIFT)) & XTALOSC24M_OSC_CONFIG2_TOG_COUNT_1M_TRG_MASK) @@ -24824,6 +38890,7 @@ typedef struct { #define XTALOSC24M_OSC_CONFIG2_TOG_CLK_1M_ERR_FL_MASK (0x80000000U) #define XTALOSC24M_OSC_CONFIG2_TOG_CLK_1M_ERR_FL_SHIFT (31U) #define XTALOSC24M_OSC_CONFIG2_TOG_CLK_1M_ERR_FL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_TOG_CLK_1M_ERR_FL_SHIFT)) & XTALOSC24M_OSC_CONFIG2_TOG_CLK_1M_ERR_FL_MASK) +/*! @} */ /*! @@ -24851,7 +38918,11 @@ typedef struct { */ #if defined(__ARMCC_VERSION) - #pragma pop + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop + #else + #pragma pop + #endif #elif defined(__CWCC__) #pragma pop #elif defined(__GNUC__) diff --git a/ext/hal/nxp/mcux/devices/MIMXRT1051/MIMXRT1051.xml b/ext/hal/nxp/mcux/devices/MIMXRT1051/MIMXRT1051.xml index c3e6090ef26..1968640c59a 100644 --- a/ext/hal/nxp/mcux/devices/MIMXRT1051/MIMXRT1051.xml +++ b/ext/hal/nxp/mcux/devices/MIMXRT1051/MIMXRT1051.xml @@ -3,32 +3,12 @@ nxp.com MIMXRT1051 1.0 - MIMXRT1051DVL6A + MIMXRT1051DVL6B -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: +Copyright 2016-2018 NXP +All rights reserved. -1. Redistributions of source code must retain the above copyright notice, this list - of conditions and the following disclaimer. - -2. Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. - -3. Neither the name of the copyright holder nor the names of its - contributors may be used to endorse or promote products derived from this - software without specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +SPDX-License-Identifier: BSD-3-Clause CM7 @@ -2154,22 +2134,22 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. read-write - DCDC_LOW_BAT - DCDC low battery detect + DCDC_IN_LOW_VOL + DCDC_IN low voltage detect. 16 1 read-only DCDC_OVER_CUR - DCDC over current alert + DCDC output over current alert 17 1 read-only DCDC_OVER_VOL - DCDC over voltage alert + DCDC output over voltage alert 18 1 read-only @@ -3588,17 +3568,17 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. SAI1_MCLK1_SEL_3 - iomux.sai1_ipg_clk_sai_mclk[2] + iomux.sai1_ipg_clk_sai_mclk 0x3 SAI1_MCLK1_SEL_4 - iomux.sai2_ipg_clk_sai_mclk[2] + iomux.sai2_ipg_clk_sai_mclk 0x4 SAI1_MCLK1_SEL_5 - iomux.sai3_ipg_clk_sai_mclk[2] + iomux.sai3_ipg_clk_sai_mclk 0x5 @@ -3627,17 +3607,17 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. SAI1_MCLK2_SEL_3 - iomux.sai1_ipg_clk_sai_mclk[2] + iomux.sai1_ipg_clk_sai_mclk 0x3 SAI1_MCLK2_SEL_4 - iomux.sai2_ipg_clk_sai_mclk[2] + iomux.sai2_ipg_clk_sai_mclk 0x4 SAI1_MCLK2_SEL_5 - iomux.sai3_ipg_clk_sai_mclk[2] + iomux.sai3_ipg_clk_sai_mclk 0x5 @@ -3731,7 +3711,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. GINT - Global interrupt "0" bit (connected to ARM M7 IRQ#0 and GPC) + Global interrupt bit (connected to ARM M7 IRQ#41 and GPC) 12 1 read-write @@ -3757,7 +3737,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ENET1_CLK_SEL_0 - ENET1 TX reference clock driven by ref_enetpll. This clock is also output to pins via the IOMUX. ENET_REF_CLK1 function. + ENET1 TX reference clock driven by ref_enetpll0. This clock is also output to pins via the IOMUX. ENET_REF_CLK1 function. 0 @@ -3788,76 +3768,76 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ENET1_TX_CLK_DIR - ENET1_TX_CLK data direction control when anatop. ENET_REF_CLK1 is selected (ALT1) + ENET1_TX_CLK data direction control when ENET_REF_CLK1 ALT is selected. 17 1 read-write ENET1_TX_CLK_DIR_0 - ENET1_TX_CLK output driver is disabled when configured for ALT1 + ENET1_TX_CLK output driver is disabled and ENET_REF_CLK1 is a clock input. 0 ENET1_TX_CLK_DIR_1 - ENET1_TX_CLK output driver is enabled when configured for ALT1 + ENET1_TX_CLK output driver is enabled and ENET_REF_CLK1 is an output driven by ref_enetpll0. 0x1 SAI1_MCLK_DIR - LCD_DATA00 data direction control when sai1.MCLK is selected (ALT8) + sai1.MCLK signal direction control 19 1 read-write SAI1_MCLK_DIR_0 - LCD_DATA00 output driver is disabled when configured for ALT8 + sai1.MCLK is input signal 0 SAI1_MCLK_DIR_1 - LCD_DATA00 output driver is enabled when configured for ALT8 + sai1.MCLK is output signal 0x1 SAI2_MCLK_DIR - SD1_CLK data direction control when sai2.MCLK is selected (ALT2) + sai2.MCLK signal direction control 20 1 read-write SAI2_MCLK_DIR_0 - SD1_CLK output driver is disabled when configured for ALT2 + sai2.MCLK is input signal 0 SAI2_MCLK_DIR_1 - SD1_CLK output driver is enabled when configured for ALT2 + sai2.MCLK is output signal 0x1 SAI3_MCLK_DIR - LCD_CLK data direction control when sai3.MCLK is selected (ALT3) + sai3.MCLK signal direction control 21 1 read-write SAI3_MCLK_DIR_0 - LCD_CLK output driver is disabled when configured for ALT3 + sai3.MCLK is input signal 0 SAI3_MCLK_DIR_1 - LCD_CLK output driver is enabled when configured for ALT3 + sai3.MCLK is output signal 0x1 @@ -3876,7 +3856,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. EXC_MON_1 - SLVError response (default) + SLVError response 0x1 @@ -3932,7 +3912,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. L2_MEM_EN_POWERSAVING - enable power saving features on L2 memory + enable power saving features on memory 12 1 read-write @@ -4138,7 +4118,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0xC 32 read-write - 0xFF0 + 0xFFF0 0xFFFFFFFF @@ -4510,12 +4490,12 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. TRNG_STOP_ACK_0 - ENET1 stop acknowledge is not asserted + TRNG stop acknowledge is not asserted 0 TRNG_STOP_ACK_1 - ENET1 stop acknowledge is asserted + TRNG stop acknowledge is asserted 0x1 @@ -4529,12 +4509,12 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ENET_STOP_ACK_0 - ENET2 stop acknowledge is not asserted + ENET stop acknowledge is not asserted 0 ENET_STOP_ACK_1 - ENET2 stop acknowledge is asserted + ENET stop acknowledge is asserted 0x1 @@ -4759,25 +4739,6 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - - GPT2_CAPIN2_SEL - GPT2 input capture channel 2 source select - 24 - 1 - read-write - - - GPT2_CAPIN2_SEL_0 - source from pad - 0 - - - GPT2_CAPIN2_SEL_1 - source from enet2.ipp_do_mac0_timer[3] - 0x1 - - - ENET_EVENT3IN_SEL ENET input timer event3 source select @@ -7298,7 +7259,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0x38 32 read-write - 0 + 0xAA0000 0xFFFFFFFF @@ -7530,108 +7491,108 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - CM7_MX6RT_CFGITCMSZ + CM7_CFGITCMSZ ITCM total size configuration 16 4 read-write - CM7_MX6RT_CFGITCMSZ_0 + CM7_CFGITCMSZ_0 0 KB (No ITCM) 0 - CM7_MX6RT_CFGITCMSZ_3 + CM7_CFGITCMSZ_3 4 KB 0x3 - CM7_MX6RT_CFGITCMSZ_4 + CM7_CFGITCMSZ_4 8 KB 0x4 - CM7_MX6RT_CFGITCMSZ_5 + CM7_CFGITCMSZ_5 16 KB 0x5 - CM7_MX6RT_CFGITCMSZ_6 + CM7_CFGITCMSZ_6 32 KB 0x6 - CM7_MX6RT_CFGITCMSZ_7 + CM7_CFGITCMSZ_7 64 KB 0x7 - CM7_MX6RT_CFGITCMSZ_8 + CM7_CFGITCMSZ_8 128 KB 0x8 - CM7_MX6RT_CFGITCMSZ_9 + CM7_CFGITCMSZ_9 256 KB 0x9 - CM7_MX6RT_CFGITCMSZ_10 + CM7_CFGITCMSZ_10 512 KB 0xA - CM7_MX6RT_CFGDTCMSZ + CM7_CFGDTCMSZ DTCM total size configuration 20 4 read-write - CM7_MX6RT_CFGDTCMSZ_0 + CM7_CFGDTCMSZ_0 0 KB (No DTCM) 0 - CM7_MX6RT_CFGDTCMSZ_3 + CM7_CFGDTCMSZ_3 4 KB 0x3 - CM7_MX6RT_CFGDTCMSZ_4 + CM7_CFGDTCMSZ_4 8 KB 0x4 - CM7_MX6RT_CFGDTCMSZ_5 + CM7_CFGDTCMSZ_5 16 KB 0x5 - CM7_MX6RT_CFGDTCMSZ_6 + CM7_CFGDTCMSZ_6 32 KB 0x6 - CM7_MX6RT_CFGDTCMSZ_7 + CM7_CFGDTCMSZ_7 64 KB 0x7 - CM7_MX6RT_CFGDTCMSZ_8 + CM7_CFGDTCMSZ_8 128 KB 0x8 - CM7_MX6RT_CFGDTCMSZ_9 + CM7_CFGDTCMSZ_9 256 KB 0x9 - CM7_MX6RT_CFGDTCMSZ_10 + CM7_CFGDTCMSZ_10 512 KB 0xA @@ -7714,13 +7675,6 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - - CM7_INIT_VTOR - Vector table offset register out of reset - 7 - 25 - read-write - @@ -7936,19 +7890,19 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0xFFFFFFFF - LOCK_M7_APC_AC_R1_TOP + LOCK_M7_APC_AC_R2_TOP lock M7_APC_AC_R2_TOP field for changes 0 1 read-write - LOCK_M7_APC_AC_R1_TOP_0 + LOCK_M7_APC_AC_R2_TOP_0 Register field [31:1] is not locked 0 - LOCK_M7_APC_AC_R1_TOP_1 + LOCK_M7_APC_AC_R2_TOP_1 Register field [31:1] is locked (read access only) 0x1 @@ -7992,7 +7946,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - M7_APC_AC_R2_BOT + M7_APC_AC_R3_BOT APC end address of memory region-3 3 29 @@ -8108,145 +8062,6 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 1 read-write - - Reserved - Reserved - 3 - 29 - read-only - - - - - OCRAM_MAGIC_ADDR - OCRAM Magic Address Register - 0x4 - 32 - read-write - 0 - 0xFFFFFFFF - - - OCRAM_WR_RD_SEL - OCRAM Write Read Select - 0 - 1 - read-write - - - OCRAM_WR_RD_SEL_0 - When OCRAM read access hits magic address, it will generate interrupt. - 0 - - - OCRAM_WR_RD_SEL_1 - When OCRAM write access hits magic address, it will generate interrupt. - 0x1 - - - - - OCRAM_MAGIC_ADDR - OCRAM Magic Address - 1 - 16 - read-write - - - Reserved - Reserved - 17 - 15 - read-only - - - - - DTCM_MAGIC_ADDR - DTCM Magic Address Register - 0x8 - 32 - read-write - 0 - 0xFFFFFFFF - - - DTCM_WR_RD_SEL - DTCM Write Read Select - 0 - 1 - read-write - - - DTCM_WR_RD_SEL_0 - When DTCM read access hits magic address, it will generate interrupt. - 0 - - - DTCM_WR_RD_SEL_1 - When DTCM write access hits magic address, it will generate interrupt. - 0x1 - - - - - DTCM_MAGIC_ADDR - DTCM Magic Address - 1 - 16 - read-write - - - Reserved - Reserved - 17 - 15 - read-only - - - - - ITCM_MAGIC_ADDR - ITCM Magic Address Register - 0xC - 32 - read-write - 0 - 0xFFFFFFFF - - - ITCM_WR_RD_SEL - ITCM Write Read Select - 0 - 1 - read-write - - - ITCM_WR_RD_SEL_0 - When ITCM read access hits magic address, it will generate interrupt. - 0 - - - ITCM_WR_RD_SEL_1 - When ITCM write access hits magic address, it will generate interrupt. - 0x1 - - - - - ITCM_MAGIC_ADDR - ITCM Magic Address - 1 - 16 - read-write - - - Reserved - Reserved - 17 - 15 - read-only - @@ -8258,66 +8073,6 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 0xFFFFFFFF - - ITCM_MAM_STATUS - ITCM Magic Address Match Status - 0 - 1 - read-write - oneToClear - - - ITCM_MAM_STATUS_0 - ITCM did not access magic address. - 0 - - - ITCM_MAM_STATUS_1 - ITCM accessed magic address. - 0x1 - - - - - DTCM_MAM_STATUS - DTCM Magic Address Match Status - 1 - 1 - read-write - oneToClear - - - DTCM_MAM_STATUS_0 - DTCM did not access magic address. - 0 - - - DTCM_MAM_STATUS_1 - DTCM accessed magic address. - 0x1 - - - - - OCRAM_MAM_STATUS - OCRAM Magic Address Match Status - 2 - 1 - read-write - oneToClear - - - OCRAM_MAM_STATUS_0 - OCRAM did not access magic address. - 0 - - - OCRAM_MAM_STATUS_1 - OCRAM accessed magic address. - 0x1 - - - ITCM_ERR_STATUS ITCM Access Error Status @@ -8378,13 +8133,6 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - - Reserved - Reserved - 6 - 26 - read-only - @@ -8396,63 +8144,6 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 0xFFFFFFFF - - ITCM_MAM_STAT_EN - ITCM Magic Address Match Status Enable - 0 - 1 - read-write - - - ITCM_MAM_STAT_EN_0 - Masked - 0 - - - ITCM_MAM_STAT_EN_1 - Enabled - 0x1 - - - - - DTCM_MAM_STAT_EN - DTCM Magic Address Match Status Enable - 1 - 1 - read-write - - - DTCM_MAM_STAT_EN_0 - Masked - 0 - - - DTCM_MAM_STAT_EN_1 - Enabled - 0x1 - - - - - OCRAM_MAM_STAT_EN - OCRAM Magic Address Match Status Enable - 2 - 1 - read-write - - - OCRAM_MAM_STAT_EN_0 - Masked - 0 - - - OCRAM_MAM_STAT_EN_1 - Enabled - 0x1 - - - ITCM_ERR_STAT_EN ITCM Access Error Status Enable @@ -8510,13 +8201,6 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - - Reserved - Reserved - 6 - 26 - read-only - @@ -8528,63 +8212,6 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 0xFFFFFFFF - - ITCM_MAM_SIG_EN - ITCM Magic Address Match Interrupt Enable - 0 - 1 - read-write - - - ITCM_MAM_SIG_EN_0 - Masked - 0 - - - ITCM_MAM_SIG_EN_1 - Enabled - 0x1 - - - - - DTCM_MAM_SIG_EN - DTCM Magic Address Match Interrupt Enable - 1 - 1 - read-write - - - DTCM_MAM_SIG_EN_0 - Masked - 0 - - - DTCM_MAM_SIG_EN_1 - Enabled - 0x1 - - - - - OCRAM_MAM_SIG_EN - OCRAM Magic Address Match Interrupt Enable - 2 - 1 - read-write - - - OCRAM_MAM_SIG_EN_0 - Masked - 0 - - - OCRAM_MAM_SIG_EN_1 - Enabled - 0x1 - - - ITCM_ERR_SIG_EN ITCM Access Error Interrupt Enable @@ -8642,13 +8269,6 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - - Reserved - Reserved - 6 - 26 - read-only - @@ -12149,7 +11769,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. LP_SWR - LP Software Reset When set to 1, the registers in the SNVS_LP section are reset + LP Software Reset When set to 1, most registers in the SNVS_LP section are reset, but the following registers are not reset by an LP software reset: Secure Real Time Counter Time Alarm Register This bit cannot be set when the LP_SWR_DIS bit is set 4 1 write-only @@ -12364,6 +11984,25 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + + DIS_PI + Disable periodic interrupt in the functional interrupt + 2 + 1 + read-write + + + DIS_PI_0 + Periodic interrupt will trigger a functional interrupt + 0 + + + DIS_PI_1 + Disable periodic interrupt in the function interrupt + 0x1 + + + PI_EN HP Periodic Interrupt Enable The periodic interrupt can be generated only if the HP Real Time Counter is enabled @@ -12879,7 +12518,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0x14 32 read-write - 0x8000B000 + 0x80003000 0xFFFFFFFF @@ -12994,41 +12633,59 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - SYS_SECURITY_CFG - System Security Configuration This field indicates the security configuration of SNVS, defined as follows: + SECURITY_CONFIG + Security Configuration This field reflects the settings of the sys_secure_boot input and the three security configuration inputs to SNVS 12 - 3 + 4 read-only - SYS_SECURITY_CFG_0 - Fab Configuration - the default configuration of newly fabricated chips + FAB_CONFIG + FAB configuration 0 - SYS_SECURITY_CFG_1 - Open Configuration - the configuration after NXP-programmable fuses have been blown + OPEN_CONFIG + OPEN configuration 0x1 - SYS_SECURITY_CFG_3 - Closed Configuration - the configuration after OEM-programmable fuses have been blown + OPEN_CONFIG + OPEN configuration + 0x2 + + + OPEN_CONFIG + OPEN configuration 0x3 - SYS_SECURITY_CFG_7 - Field Return Configuration - the configuration of chips that are returned to NXP for analysis - 0x7 + FIELD_RETURN_CONFIG + FIELD RETURN configuration + #x1xx + + + FAB_CONFIG + FAB configuration + 0x8 + + + CLOSED_CONFIG + CLOSED configuration + 0x9 + + + CLOSED_CONFIG + CLOSED configuration + 0xA + + + CLOSED_CONFIG + CLOSED configuration + 0xB - - SYS_SECURE_BOOT - System Secure Boot If SYS_SECURE_BOOT is 1, the chip boots from internal ROM. - 15 - 1 - read-only - OTPMK_SYNDROME One Time Programmable Master Key Syndrome In the case of a single-bit error, the eight lower bits of this value indicate the bit number of error location @@ -13558,7 +13215,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0x38 32 read-write - 0 + 0x20 0xFFFFFFFF @@ -14434,7 +14091,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. MC_ERA_BITS - Monotonic Counter Era Bits These bits are inputs to the module and typically connect to fuses. + Monotonic Counter Era Bits These bits are inputs to the module and typically connect to fuses 16 16 read-only @@ -14536,10 +14193,10 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - 4 + 8 0x4 LPGPR[%s] - SNVS_LP General Purpose Registers 0 .. 3 + SNVS_LP General Purpose Registers 0 .. 7 0x100 32 read-write @@ -14940,8 +14597,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. DIV_SELECT This field controls the PLL loop divider. 0 - Fout=Fref*20; 1 - Fout=Fref*22. - 0 - 2 + 1 + 1 read-write @@ -14994,16 +14651,6 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. Select the CLK1_N / CLK1_P as source. 0x1 - - GPANAIO - GPANAIO - 0x2 - - - CHRG_DET_B - CHRG_DET_B - 0x3 - @@ -15034,8 +14681,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. DIV_SELECT This field controls the PLL loop divider. 0 - Fout=Fref*20; 1 - Fout=Fref*22. - 0 - 2 + 1 + 1 read-write @@ -15088,16 +14735,6 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. Select the CLK1_N / CLK1_P as source. 0x1 - - GPANAIO - GPANAIO - 0x2 - - - CHRG_DET_B - CHRG_DET_B - 0x3 - @@ -15128,8 +14765,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. DIV_SELECT This field controls the PLL loop divider. 0 - Fout=Fref*20; 1 - Fout=Fref*22. - 0 - 2 + 1 + 1 read-write @@ -15182,16 +14819,6 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. Select the CLK1_N / CLK1_P as source. 0x1 - - GPANAIO - GPANAIO - 0x2 - - - CHRG_DET_B - CHRG_DET_B - 0x3 - @@ -15222,8 +14849,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. DIV_SELECT This field controls the PLL loop divider. 0 - Fout=Fref*20; 1 - Fout=Fref*22. - 0 - 2 + 1 + 1 read-write @@ -15276,16 +14903,6 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. Select the CLK1_N / CLK1_P as source. 0x1 - - GPANAIO - GPANAIO - 0x2 - - - CHRG_DET_B - CHRG_DET_B - 0x3 - @@ -15316,8 +14933,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. DIV_SELECT This field controls the PLL loop divider. 0 - Fout=Fref*20; 1 - Fout=Fref*22. - 0 - 2 + 1 + 1 read-write @@ -15388,8 +15005,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. DIV_SELECT This field controls the PLL loop divider. 0 - Fout=Fref*20; 1 - Fout=Fref*22. - 0 - 2 + 1 + 1 read-write @@ -15460,8 +15077,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. DIV_SELECT This field controls the PLL loop divider. 0 - Fout=Fref*20; 1 - Fout=Fref*22. - 0 - 2 + 1 + 1 read-write @@ -15532,8 +15149,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. DIV_SELECT This field controls the PLL loop divider. 0 - Fout=Fref*20; 1 - Fout=Fref*22. - 0 - 2 + 1 + 1 read-write @@ -15639,16 +15256,6 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. Select the CLK1_N / CLK1_P as source. 0x1 - - GPANAIO - GPANAIO - 0x2 - - - CHRG_DET_B - CHRG_DET_B - 0x3 - @@ -15721,16 +15328,6 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. Select the CLK1_N / CLK1_P as source. 0x1 - - GPANAIO - GPANAIO - 0x2 - - - CHRG_DET_B - CHRG_DET_B - 0x3 - @@ -15803,16 +15400,6 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. Select the CLK1_N / CLK1_P as source. 0x1 - - GPANAIO - GPANAIO - 0x2 - - - CHRG_DET_B - CHRG_DET_B - 0x3 - @@ -15885,16 +15472,6 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. Select the CLK1_N / CLK1_P as source. 0x1 - - GPANAIO - GPANAIO - 0x2 - - - CHRG_DET_B - CHRG_DET_B - 0x3 - @@ -16850,62 +16427,11 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0xFFFFFFFF - ENET0_DIV_SELECT - Controls the frequency of the ethernet0 reference clock. + DIV_SELECT + Controls the frequency of the ethernet reference clock 0 2 read-write - - - ENET0_DIV_SELECT_0 - 25MHz - 0 - - - ENET0_DIV_SELECT_1 - 50MHz - 0x1 - - - ENET0_DIV_SELECT_2 - 100MHz (not 50% duty cycle) - 0x2 - - - ENET0_DIV_SELECT_3 - 125MHz - 0x3 - - - - - ENET1_DIV_SELECT - Controls the frequency of the ethernet1 reference clock. - 2 - 2 - read-write - - - ENET1_DIV_SELECT_0 - 25MHz - 0 - - - ENET1_DIV_SELECT_1 - 50MHz - 0x1 - - - ENET1_DIV_SELECT_2 - 100MHz (not 50% duty cycle) - 0x2 - - - ENET1_DIV_SELECT_3 - 125MHz - 0x3 - - POWERDOWN @@ -16915,8 +16441,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. read-write - ENET1_125M_EN - Enable the PLL providing the ENET1 125 MHz reference clock. + ENABLE + Enable the ethernet clock output. 13 1 read-write @@ -16954,20 +16480,6 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 1 read-write - - ENABLE_125M - Enables an offset in the phase frequency detector. - 19 - 1 - read-write - - - ENET2_125M_EN - Enable the PLL providing the ENET2 125 MHz reference clock - 20 - 1 - read-write - ENET_25M_REF_EN Enable the PLL providing ENET 25 MHz reference clock @@ -16994,62 +16506,11 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0xFFFFFFFF - ENET0_DIV_SELECT - Controls the frequency of the ethernet0 reference clock. + DIV_SELECT + Controls the frequency of the ethernet reference clock 0 2 read-write - - - ENET0_DIV_SELECT_0 - 25MHz - 0 - - - ENET0_DIV_SELECT_1 - 50MHz - 0x1 - - - ENET0_DIV_SELECT_2 - 100MHz (not 50% duty cycle) - 0x2 - - - ENET0_DIV_SELECT_3 - 125MHz - 0x3 - - - - - ENET1_DIV_SELECT - Controls the frequency of the ethernet1 reference clock. - 2 - 2 - read-write - - - ENET1_DIV_SELECT_0 - 25MHz - 0 - - - ENET1_DIV_SELECT_1 - 50MHz - 0x1 - - - ENET1_DIV_SELECT_2 - 100MHz (not 50% duty cycle) - 0x2 - - - ENET1_DIV_SELECT_3 - 125MHz - 0x3 - - POWERDOWN @@ -17059,8 +16520,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. read-write - ENET1_125M_EN - Enable the PLL providing the ENET1 125 MHz reference clock. + ENABLE + Enable the ethernet clock output. 13 1 read-write @@ -17098,20 +16559,6 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 1 read-write - - ENABLE_125M - Enables an offset in the phase frequency detector. - 19 - 1 - read-write - - - ENET2_125M_EN - Enable the PLL providing the ENET2 125 MHz reference clock - 20 - 1 - read-write - ENET_25M_REF_EN Enable the PLL providing ENET 25 MHz reference clock @@ -17138,62 +16585,11 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0xFFFFFFFF - ENET0_DIV_SELECT - Controls the frequency of the ethernet0 reference clock. + DIV_SELECT + Controls the frequency of the ethernet reference clock 0 2 read-write - - - ENET0_DIV_SELECT_0 - 25MHz - 0 - - - ENET0_DIV_SELECT_1 - 50MHz - 0x1 - - - ENET0_DIV_SELECT_2 - 100MHz (not 50% duty cycle) - 0x2 - - - ENET0_DIV_SELECT_3 - 125MHz - 0x3 - - - - - ENET1_DIV_SELECT - Controls the frequency of the ethernet1 reference clock. - 2 - 2 - read-write - - - ENET1_DIV_SELECT_0 - 25MHz - 0 - - - ENET1_DIV_SELECT_1 - 50MHz - 0x1 - - - ENET1_DIV_SELECT_2 - 100MHz (not 50% duty cycle) - 0x2 - - - ENET1_DIV_SELECT_3 - 125MHz - 0x3 - - POWERDOWN @@ -17203,8 +16599,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. read-write - ENET1_125M_EN - Enable the PLL providing the ENET1 125 MHz reference clock. + ENABLE + Enable the ethernet clock output. 13 1 read-write @@ -17242,20 +16638,6 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 1 read-write - - ENABLE_125M - Enables an offset in the phase frequency detector. - 19 - 1 - read-write - - - ENET2_125M_EN - Enable the PLL providing the ENET2 125 MHz reference clock - 20 - 1 - read-write - ENET_25M_REF_EN Enable the PLL providing ENET 25 MHz reference clock @@ -17282,62 +16664,11 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0xFFFFFFFF - ENET0_DIV_SELECT - Controls the frequency of the ethernet0 reference clock. + DIV_SELECT + Controls the frequency of the ethernet reference clock 0 2 read-write - - - ENET0_DIV_SELECT_0 - 25MHz - 0 - - - ENET0_DIV_SELECT_1 - 50MHz - 0x1 - - - ENET0_DIV_SELECT_2 - 100MHz (not 50% duty cycle) - 0x2 - - - ENET0_DIV_SELECT_3 - 125MHz - 0x3 - - - - - ENET1_DIV_SELECT - Controls the frequency of the ethernet1 reference clock. - 2 - 2 - read-write - - - ENET1_DIV_SELECT_0 - 25MHz - 0 - - - ENET1_DIV_SELECT_1 - 50MHz - 0x1 - - - ENET1_DIV_SELECT_2 - 100MHz (not 50% duty cycle) - 0x2 - - - ENET1_DIV_SELECT_3 - 125MHz - 0x3 - - POWERDOWN @@ -17347,8 +16678,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. read-write - ENET1_125M_EN - Enable the PLL providing the ENET1 125 MHz reference clock. + ENABLE + Enable the ethernet clock output. 13 1 read-write @@ -17386,20 +16717,6 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 1 read-write - - ENABLE_125M - Enables an offset in the phase frequency detector. - 19 - 1 - read-write - - - ENET2_125M_EN - Enable the PLL providing the ENET2 125 MHz reference clock - 20 - 1 - read-write - ENET_25M_REF_EN Enable the PLL providing ENET 25 MHz reference clock @@ -18452,25 +17769,6 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 1 read-write - - VID_PLL_PREDIV - Predivider for the source clock of the PLL's. - 31 - 1 - read-write - - - VID_PLL_PREDIV_0 - Divide by 1 - 0 - - - VID_PLL_PREDIV_1 - Divide by 2 - 0x1 - - - @@ -18749,25 +18047,6 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 1 read-write - - VID_PLL_PREDIV - Predivider for the source clock of the PLL's. - 31 - 1 - read-write - - - VID_PLL_PREDIV_0 - Divide by 1 - 0 - - - VID_PLL_PREDIV_1 - Divide by 2 - 0x1 - - - @@ -19046,25 +18325,6 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 1 read-write - - VID_PLL_PREDIV - Predivider for the source clock of the PLL's. - 31 - 1 - read-write - - - VID_PLL_PREDIV_0 - Divide by 1 - 0 - - - VID_PLL_PREDIV_1 - Divide by 2 - 0x1 - - - @@ -19343,25 +18603,6 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 1 read-write - - VID_PLL_PREDIV - Predivider for the source clock of the PLL's. - 31 - 1 - read-write - - - VID_PLL_PREDIV_0 - Divide by 1 - 0 - - - VID_PLL_PREDIV_1 - Divide by 2 - 0x1 - - - @@ -21322,6 +20563,10 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0x180 registers + + PMU_EVENT + 61 + REG_1P1 @@ -21421,7 +20666,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. SELREF_WEAK_LINREG_1 - Weak-linreg output tracks VDD_SOC_CAP voltage + Weak-linreg output tracks VDD_SOC_IN voltage 0x1 @@ -21526,7 +20771,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. SELREF_WEAK_LINREG_1 - Weak-linreg output tracks VDD_SOC_CAP voltage + Weak-linreg output tracks VDD_SOC_IN voltage 0x1 @@ -21631,7 +20876,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. SELREF_WEAK_LINREG_1 - Weak-linreg output tracks VDD_SOC_CAP voltage + Weak-linreg output tracks VDD_SOC_IN voltage 0x1 @@ -21736,7 +20981,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. SELREF_WEAK_LINREG_1 - Weak-linreg output tracks VDD_SOC_CAP voltage + Weak-linreg output tracks VDD_SOC_IN voltage 0x1 @@ -22544,6 +21789,228 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + + REG0_ADJ + This bit field defines the adjustment bits to calibrate the target value of Reg0. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register. + 5 + 4 + read-write + + + REG0_ADJ_0 + No adjustment + 0 + + + REG0_ADJ_1 + + 0.25% + 0x1 + + + REG0_ADJ_2 + + 0.50% + 0x2 + + + REG0_ADJ_3 + + 0.75% + 0x3 + + + REG0_ADJ_4 + + 1.00% + 0x4 + + + REG0_ADJ_5 + + 1.25% + 0x5 + + + REG0_ADJ_6 + + 1.50% + 0x6 + + + REG0_ADJ_7 + + 1.75% + 0x7 + + + REG0_ADJ_8 + - 0.25% + 0x8 + + + REG0_ADJ_9 + - 0.50% + 0x9 + + + REG0_ADJ_10 + - 0.75% + 0xA + + + REG0_ADJ_11 + - 1.00% + 0xB + + + REG0_ADJ_12 + - 1.25% + 0xC + + + REG0_ADJ_13 + - 1.50% + 0xD + + + REG0_ADJ_14 + - 1.75% + 0xE + + + REG0_ADJ_15 + - 2.00% + 0xF + + + + + REG1_TARG + This bit field defines the target voltage for the vpu/gpu power domain. Single bit increments reflect 25mV core voltage steps. Not all steps will make sense to use either because of input supply limitations or load operation. + 9 + 5 + read-write + + + REG1_TARG_0 + Power gated off + 0 + + + REG1_TARG_1 + Target core voltage = 0.725V + 0x1 + + + REG1_TARG_2 + Target core voltage = 0.750V + 0x2 + + + REG1_TARG_3 + Target core voltage = 0.775V + 0x3 + + + REG1_TARG_16 + Target core voltage = 1.100V + 0x10 + + + REG1_TARG_30 + Target core voltage = 1.450V + 0x1E + + + REG1_TARG_31 + Power FET switched full on. No regulation. + 0x1F + + + + + REG1_ADJ + This bit field defines the adjustment bits to calibrate the target value of Reg1. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register. + 14 + 4 + read-write + + + REG1_ADJ_0 + No adjustment + 0 + + + REG1_ADJ_1 + + 0.25% + 0x1 + + + REG1_ADJ_2 + + 0.50% + 0x2 + + + REG1_ADJ_3 + + 0.75% + 0x3 + + + REG1_ADJ_4 + + 1.00% + 0x4 + + + REG1_ADJ_5 + + 1.25% + 0x5 + + + REG1_ADJ_6 + + 1.50% + 0x6 + + + REG1_ADJ_7 + + 1.75% + 0x7 + + + REG1_ADJ_8 + - 0.25% + 0x8 + + + REG1_ADJ_9 + - 0.50% + 0x9 + + + REG1_ADJ_10 + - 0.75% + 0xA + + + REG1_ADJ_11 + - 1.00% + 0xB + + + REG1_ADJ_12 + - 1.25% + 0xC + + + REG1_ADJ_13 + - 1.50% + 0xD + + + REG1_ADJ_14 + - 1.75% + 0xE + + + REG1_ADJ_15 + - 2.00% + 0xF + + + REG2_TARG This field defines the target voltage for the SOC power domain @@ -22588,6 +22055,95 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + + REG2_ADJ + This bit field defines the adjustment bits to calibrate the target value of Reg2. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register. + 23 + 4 + read-write + + + REG2_ADJ_0 + No adjustment + 0 + + + REG2_ADJ_1 + + 0.25% + 0x1 + + + REG2_ADJ_2 + + 0.50% + 0x2 + + + REG2_ADJ_3 + + 0.75% + 0x3 + + + REG2_ADJ_4 + + 1.00% + 0x4 + + + REG2_ADJ_5 + + 1.25% + 0x5 + + + REG2_ADJ_6 + + 1.50% + 0x6 + + + REG2_ADJ_7 + + 1.75% + 0x7 + + + REG2_ADJ_8 + - 0.25% + 0x8 + + + REG2_ADJ_9 + - 0.50% + 0x9 + + + REG2_ADJ_10 + - 0.75% + 0xA + + + REG2_ADJ_11 + - 1.00% + 0xB + + + REG2_ADJ_12 + - 1.25% + 0xC + + + REG2_ADJ_13 + - 1.50% + 0xD + + + REG2_ADJ_14 + - 1.75% + 0xE + + + REG2_ADJ_15 + - 2.00% + 0xF + + + RAMP_RATE Regulator voltage ramp rate. @@ -22679,6 +22235,228 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + + REG0_ADJ + This bit field defines the adjustment bits to calibrate the target value of Reg0. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register. + 5 + 4 + read-write + + + REG0_ADJ_0 + No adjustment + 0 + + + REG0_ADJ_1 + + 0.25% + 0x1 + + + REG0_ADJ_2 + + 0.50% + 0x2 + + + REG0_ADJ_3 + + 0.75% + 0x3 + + + REG0_ADJ_4 + + 1.00% + 0x4 + + + REG0_ADJ_5 + + 1.25% + 0x5 + + + REG0_ADJ_6 + + 1.50% + 0x6 + + + REG0_ADJ_7 + + 1.75% + 0x7 + + + REG0_ADJ_8 + - 0.25% + 0x8 + + + REG0_ADJ_9 + - 0.50% + 0x9 + + + REG0_ADJ_10 + - 0.75% + 0xA + + + REG0_ADJ_11 + - 1.00% + 0xB + + + REG0_ADJ_12 + - 1.25% + 0xC + + + REG0_ADJ_13 + - 1.50% + 0xD + + + REG0_ADJ_14 + - 1.75% + 0xE + + + REG0_ADJ_15 + - 2.00% + 0xF + + + + + REG1_TARG + This bit field defines the target voltage for the vpu/gpu power domain. Single bit increments reflect 25mV core voltage steps. Not all steps will make sense to use either because of input supply limitations or load operation. + 9 + 5 + read-write + + + REG1_TARG_0 + Power gated off + 0 + + + REG1_TARG_1 + Target core voltage = 0.725V + 0x1 + + + REG1_TARG_2 + Target core voltage = 0.750V + 0x2 + + + REG1_TARG_3 + Target core voltage = 0.775V + 0x3 + + + REG1_TARG_16 + Target core voltage = 1.100V + 0x10 + + + REG1_TARG_30 + Target core voltage = 1.450V + 0x1E + + + REG1_TARG_31 + Power FET switched full on. No regulation. + 0x1F + + + + + REG1_ADJ + This bit field defines the adjustment bits to calibrate the target value of Reg1. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register. + 14 + 4 + read-write + + + REG1_ADJ_0 + No adjustment + 0 + + + REG1_ADJ_1 + + 0.25% + 0x1 + + + REG1_ADJ_2 + + 0.50% + 0x2 + + + REG1_ADJ_3 + + 0.75% + 0x3 + + + REG1_ADJ_4 + + 1.00% + 0x4 + + + REG1_ADJ_5 + + 1.25% + 0x5 + + + REG1_ADJ_6 + + 1.50% + 0x6 + + + REG1_ADJ_7 + + 1.75% + 0x7 + + + REG1_ADJ_8 + - 0.25% + 0x8 + + + REG1_ADJ_9 + - 0.50% + 0x9 + + + REG1_ADJ_10 + - 0.75% + 0xA + + + REG1_ADJ_11 + - 1.00% + 0xB + + + REG1_ADJ_12 + - 1.25% + 0xC + + + REG1_ADJ_13 + - 1.50% + 0xD + + + REG1_ADJ_14 + - 1.75% + 0xE + + + REG1_ADJ_15 + - 2.00% + 0xF + + + REG2_TARG This field defines the target voltage for the SOC power domain @@ -22723,6 +22501,95 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + + REG2_ADJ + This bit field defines the adjustment bits to calibrate the target value of Reg2. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register. + 23 + 4 + read-write + + + REG2_ADJ_0 + No adjustment + 0 + + + REG2_ADJ_1 + + 0.25% + 0x1 + + + REG2_ADJ_2 + + 0.50% + 0x2 + + + REG2_ADJ_3 + + 0.75% + 0x3 + + + REG2_ADJ_4 + + 1.00% + 0x4 + + + REG2_ADJ_5 + + 1.25% + 0x5 + + + REG2_ADJ_6 + + 1.50% + 0x6 + + + REG2_ADJ_7 + + 1.75% + 0x7 + + + REG2_ADJ_8 + - 0.25% + 0x8 + + + REG2_ADJ_9 + - 0.50% + 0x9 + + + REG2_ADJ_10 + - 0.75% + 0xA + + + REG2_ADJ_11 + - 1.00% + 0xB + + + REG2_ADJ_12 + - 1.25% + 0xC + + + REG2_ADJ_13 + - 1.50% + 0xD + + + REG2_ADJ_14 + - 1.75% + 0xE + + + REG2_ADJ_15 + - 2.00% + 0xF + + + RAMP_RATE Regulator voltage ramp rate. @@ -22814,6 +22681,228 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + + REG0_ADJ + This bit field defines the adjustment bits to calibrate the target value of Reg0. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register. + 5 + 4 + read-write + + + REG0_ADJ_0 + No adjustment + 0 + + + REG0_ADJ_1 + + 0.25% + 0x1 + + + REG0_ADJ_2 + + 0.50% + 0x2 + + + REG0_ADJ_3 + + 0.75% + 0x3 + + + REG0_ADJ_4 + + 1.00% + 0x4 + + + REG0_ADJ_5 + + 1.25% + 0x5 + + + REG0_ADJ_6 + + 1.50% + 0x6 + + + REG0_ADJ_7 + + 1.75% + 0x7 + + + REG0_ADJ_8 + - 0.25% + 0x8 + + + REG0_ADJ_9 + - 0.50% + 0x9 + + + REG0_ADJ_10 + - 0.75% + 0xA + + + REG0_ADJ_11 + - 1.00% + 0xB + + + REG0_ADJ_12 + - 1.25% + 0xC + + + REG0_ADJ_13 + - 1.50% + 0xD + + + REG0_ADJ_14 + - 1.75% + 0xE + + + REG0_ADJ_15 + - 2.00% + 0xF + + + + + REG1_TARG + This bit field defines the target voltage for the vpu/gpu power domain. Single bit increments reflect 25mV core voltage steps. Not all steps will make sense to use either because of input supply limitations or load operation. + 9 + 5 + read-write + + + REG1_TARG_0 + Power gated off + 0 + + + REG1_TARG_1 + Target core voltage = 0.725V + 0x1 + + + REG1_TARG_2 + Target core voltage = 0.750V + 0x2 + + + REG1_TARG_3 + Target core voltage = 0.775V + 0x3 + + + REG1_TARG_16 + Target core voltage = 1.100V + 0x10 + + + REG1_TARG_30 + Target core voltage = 1.450V + 0x1E + + + REG1_TARG_31 + Power FET switched full on. No regulation. + 0x1F + + + + + REG1_ADJ + This bit field defines the adjustment bits to calibrate the target value of Reg1. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register. + 14 + 4 + read-write + + + REG1_ADJ_0 + No adjustment + 0 + + + REG1_ADJ_1 + + 0.25% + 0x1 + + + REG1_ADJ_2 + + 0.50% + 0x2 + + + REG1_ADJ_3 + + 0.75% + 0x3 + + + REG1_ADJ_4 + + 1.00% + 0x4 + + + REG1_ADJ_5 + + 1.25% + 0x5 + + + REG1_ADJ_6 + + 1.50% + 0x6 + + + REG1_ADJ_7 + + 1.75% + 0x7 + + + REG1_ADJ_8 + - 0.25% + 0x8 + + + REG1_ADJ_9 + - 0.50% + 0x9 + + + REG1_ADJ_10 + - 0.75% + 0xA + + + REG1_ADJ_11 + - 1.00% + 0xB + + + REG1_ADJ_12 + - 1.25% + 0xC + + + REG1_ADJ_13 + - 1.50% + 0xD + + + REG1_ADJ_14 + - 1.75% + 0xE + + + REG1_ADJ_15 + - 2.00% + 0xF + + + REG2_TARG This field defines the target voltage for the SOC power domain @@ -22858,6 +22947,95 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + + REG2_ADJ + This bit field defines the adjustment bits to calibrate the target value of Reg2. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register. + 23 + 4 + read-write + + + REG2_ADJ_0 + No adjustment + 0 + + + REG2_ADJ_1 + + 0.25% + 0x1 + + + REG2_ADJ_2 + + 0.50% + 0x2 + + + REG2_ADJ_3 + + 0.75% + 0x3 + + + REG2_ADJ_4 + + 1.00% + 0x4 + + + REG2_ADJ_5 + + 1.25% + 0x5 + + + REG2_ADJ_6 + + 1.50% + 0x6 + + + REG2_ADJ_7 + + 1.75% + 0x7 + + + REG2_ADJ_8 + - 0.25% + 0x8 + + + REG2_ADJ_9 + - 0.50% + 0x9 + + + REG2_ADJ_10 + - 0.75% + 0xA + + + REG2_ADJ_11 + - 1.00% + 0xB + + + REG2_ADJ_12 + - 1.25% + 0xC + + + REG2_ADJ_13 + - 1.50% + 0xD + + + REG2_ADJ_14 + - 1.75% + 0xE + + + REG2_ADJ_15 + - 2.00% + 0xF + + + RAMP_RATE Regulator voltage ramp rate. @@ -22949,6 +23127,228 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + + REG0_ADJ + This bit field defines the adjustment bits to calibrate the target value of Reg0. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register. + 5 + 4 + read-write + + + REG0_ADJ_0 + No adjustment + 0 + + + REG0_ADJ_1 + + 0.25% + 0x1 + + + REG0_ADJ_2 + + 0.50% + 0x2 + + + REG0_ADJ_3 + + 0.75% + 0x3 + + + REG0_ADJ_4 + + 1.00% + 0x4 + + + REG0_ADJ_5 + + 1.25% + 0x5 + + + REG0_ADJ_6 + + 1.50% + 0x6 + + + REG0_ADJ_7 + + 1.75% + 0x7 + + + REG0_ADJ_8 + - 0.25% + 0x8 + + + REG0_ADJ_9 + - 0.50% + 0x9 + + + REG0_ADJ_10 + - 0.75% + 0xA + + + REG0_ADJ_11 + - 1.00% + 0xB + + + REG0_ADJ_12 + - 1.25% + 0xC + + + REG0_ADJ_13 + - 1.50% + 0xD + + + REG0_ADJ_14 + - 1.75% + 0xE + + + REG0_ADJ_15 + - 2.00% + 0xF + + + + + REG1_TARG + This bit field defines the target voltage for the vpu/gpu power domain. Single bit increments reflect 25mV core voltage steps. Not all steps will make sense to use either because of input supply limitations or load operation. + 9 + 5 + read-write + + + REG1_TARG_0 + Power gated off + 0 + + + REG1_TARG_1 + Target core voltage = 0.725V + 0x1 + + + REG1_TARG_2 + Target core voltage = 0.750V + 0x2 + + + REG1_TARG_3 + Target core voltage = 0.775V + 0x3 + + + REG1_TARG_16 + Target core voltage = 1.100V + 0x10 + + + REG1_TARG_30 + Target core voltage = 1.450V + 0x1E + + + REG1_TARG_31 + Power FET switched full on. No regulation. + 0x1F + + + + + REG1_ADJ + This bit field defines the adjustment bits to calibrate the target value of Reg1. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register. + 14 + 4 + read-write + + + REG1_ADJ_0 + No adjustment + 0 + + + REG1_ADJ_1 + + 0.25% + 0x1 + + + REG1_ADJ_2 + + 0.50% + 0x2 + + + REG1_ADJ_3 + + 0.75% + 0x3 + + + REG1_ADJ_4 + + 1.00% + 0x4 + + + REG1_ADJ_5 + + 1.25% + 0x5 + + + REG1_ADJ_6 + + 1.50% + 0x6 + + + REG1_ADJ_7 + + 1.75% + 0x7 + + + REG1_ADJ_8 + - 0.25% + 0x8 + + + REG1_ADJ_9 + - 0.50% + 0x9 + + + REG1_ADJ_10 + - 0.75% + 0xA + + + REG1_ADJ_11 + - 1.00% + 0xB + + + REG1_ADJ_12 + - 1.25% + 0xC + + + REG1_ADJ_13 + - 1.50% + 0xD + + + REG1_ADJ_14 + - 1.75% + 0xE + + + REG1_ADJ_15 + - 2.00% + 0xF + + + REG2_TARG This field defines the target voltage for the SOC power domain @@ -22993,6 +23393,95 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + + REG2_ADJ + This bit field defines the adjustment bits to calibrate the target value of Reg2. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register. + 23 + 4 + read-write + + + REG2_ADJ_0 + No adjustment + 0 + + + REG2_ADJ_1 + + 0.25% + 0x1 + + + REG2_ADJ_2 + + 0.50% + 0x2 + + + REG2_ADJ_3 + + 0.75% + 0x3 + + + REG2_ADJ_4 + + 1.00% + 0x4 + + + REG2_ADJ_5 + + 1.25% + 0x5 + + + REG2_ADJ_6 + + 1.50% + 0x6 + + + REG2_ADJ_7 + + 1.75% + 0x7 + + + REG2_ADJ_8 + - 0.25% + 0x8 + + + REG2_ADJ_9 + - 0.50% + 0x9 + + + REG2_ADJ_10 + - 0.75% + 0xA + + + REG2_ADJ_11 + - 1.00% + 0xB + + + REG2_ADJ_12 + - 1.25% + 0xC + + + REG2_ADJ_13 + - 1.50% + 0xD + + + REG2_ADJ_14 + - 1.75% + 0xE + + + REG2_ADJ_15 + - 2.00% + 0xF + + + RAMP_RATE Regulator voltage ramp rate. @@ -24317,6 +24806,120 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + + LVDS2_CLK_SEL + This field selects the clk to be routed to anaclk2/2b.Not related to PMU. + 5 + 5 + read-write + + + ARM_PLL + Arm PLL + 0 + + + SYS_PLL + System PLL + 0x1 + + + PFD4 + ref_pfd4_clk == pll2_pfd0_clk + 0x2 + + + PFD5 + ref_pfd5_clk == pll2_pfd1_clk + 0x3 + + + PFD6 + ref_pfd6_clk == pll2_pfd2_clk + 0x4 + + + PFD7 + ref_pfd7_clk == pll2_pfd3_clk + 0x5 + + + AUDIO_PLL + Audio PLL + 0x6 + + + VIDEO_PLL + Video PLL + 0x7 + + + MLB_PLL + MLB PLL + 0x8 + + + ETHERNET_REF + ethernet ref clock (ENET_PLL) + 0x9 + + + PCIE_REF + PCIe ref clock (125M) + 0xA + + + SATA_REF + SATA ref clock (100M) + 0xB + + + USB1_PLL + USB1 PLL clock + 0xC + + + USB2_PLL + USB2 PLL clock + 0xD + + + PFD0 + ref_pfd0_clk == pll3_pfd0_clk + 0xE + + + PFD1 + ref_pfd1_clk == pll3_pfd1_clk + 0xF + + + PFD2 + ref_pfd2_clk == pll3_pfd2_clk + 0x10 + + + PFD3 + ref_pfd3_clk == pll3_pfd3_clk + 0x11 + + + XTAL + xtal (24M) + 0x12 + + + LVDS1 + LVDS1 (loopback) + 0x13 + + + LVDS2 + LVDS2 (not useful) + 0x14 + + + LVDSCLK1_OBEN This enables the LVDS output buffer for anaclk1/1b @@ -24324,6 +24927,13 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 1 read-write + + LVDSCLK2_OBEN + This enables the LVDS output buffer for anaclk2/2b + 11 + 1 + read-write + LVDSCLK1_IBEN This enables the LVDS input buffer for anaclk1/1b @@ -24331,6 +24941,13 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 1 read-write + + LVDSCLK2_IBEN + This enables the LVDS input buffer for anaclk2/2b + 13 + 1 + read-write + PFD_480_AUTOGATE_EN This enables a feature that will clkgate (reset) all PFD_480 clocks anytime the USB1_PLL_480 is unlocked or powered off @@ -24485,6 +25102,120 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + + LVDS2_CLK_SEL + This field selects the clk to be routed to anaclk2/2b.Not related to PMU. + 5 + 5 + read-write + + + ARM_PLL + Arm PLL + 0 + + + SYS_PLL + System PLL + 0x1 + + + PFD4 + ref_pfd4_clk == pll2_pfd0_clk + 0x2 + + + PFD5 + ref_pfd5_clk == pll2_pfd1_clk + 0x3 + + + PFD6 + ref_pfd6_clk == pll2_pfd2_clk + 0x4 + + + PFD7 + ref_pfd7_clk == pll2_pfd3_clk + 0x5 + + + AUDIO_PLL + Audio PLL + 0x6 + + + VIDEO_PLL + Video PLL + 0x7 + + + MLB_PLL + MLB PLL + 0x8 + + + ETHERNET_REF + ethernet ref clock (ENET_PLL) + 0x9 + + + PCIE_REF + PCIe ref clock (125M) + 0xA + + + SATA_REF + SATA ref clock (100M) + 0xB + + + USB1_PLL + USB1 PLL clock + 0xC + + + USB2_PLL + USB2 PLL clock + 0xD + + + PFD0 + ref_pfd0_clk == pll3_pfd0_clk + 0xE + + + PFD1 + ref_pfd1_clk == pll3_pfd1_clk + 0xF + + + PFD2 + ref_pfd2_clk == pll3_pfd2_clk + 0x10 + + + PFD3 + ref_pfd3_clk == pll3_pfd3_clk + 0x11 + + + XTAL + xtal (24M) + 0x12 + + + LVDS1 + LVDS1 (loopback) + 0x13 + + + LVDS2 + LVDS2 (not useful) + 0x14 + + + LVDSCLK1_OBEN This enables the LVDS output buffer for anaclk1/1b @@ -24492,6 +25223,13 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 1 read-write + + LVDSCLK2_OBEN + This enables the LVDS output buffer for anaclk2/2b + 11 + 1 + read-write + LVDSCLK1_IBEN This enables the LVDS input buffer for anaclk1/1b @@ -24499,6 +25237,13 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 1 read-write + + LVDSCLK2_IBEN + This enables the LVDS input buffer for anaclk2/2b + 13 + 1 + read-write + PFD_480_AUTOGATE_EN This enables a feature that will clkgate (reset) all PFD_480 clocks anytime the USB1_PLL_480 is unlocked or powered off @@ -24653,6 +25398,120 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + + LVDS2_CLK_SEL + This field selects the clk to be routed to anaclk2/2b.Not related to PMU. + 5 + 5 + read-write + + + ARM_PLL + Arm PLL + 0 + + + SYS_PLL + System PLL + 0x1 + + + PFD4 + ref_pfd4_clk == pll2_pfd0_clk + 0x2 + + + PFD5 + ref_pfd5_clk == pll2_pfd1_clk + 0x3 + + + PFD6 + ref_pfd6_clk == pll2_pfd2_clk + 0x4 + + + PFD7 + ref_pfd7_clk == pll2_pfd3_clk + 0x5 + + + AUDIO_PLL + Audio PLL + 0x6 + + + VIDEO_PLL + Video PLL + 0x7 + + + MLB_PLL + MLB PLL + 0x8 + + + ETHERNET_REF + ethernet ref clock (ENET_PLL) + 0x9 + + + PCIE_REF + PCIe ref clock (125M) + 0xA + + + SATA_REF + SATA ref clock (100M) + 0xB + + + USB1_PLL + USB1 PLL clock + 0xC + + + USB2_PLL + USB2 PLL clock + 0xD + + + PFD0 + ref_pfd0_clk == pll3_pfd0_clk + 0xE + + + PFD1 + ref_pfd1_clk == pll3_pfd1_clk + 0xF + + + PFD2 + ref_pfd2_clk == pll3_pfd2_clk + 0x10 + + + PFD3 + ref_pfd3_clk == pll3_pfd3_clk + 0x11 + + + XTAL + xtal (24M) + 0x12 + + + LVDS1 + LVDS1 (loopback) + 0x13 + + + LVDS2 + LVDS2 (not useful) + 0x14 + + + LVDSCLK1_OBEN This enables the LVDS output buffer for anaclk1/1b @@ -24660,6 +25519,13 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 1 read-write + + LVDSCLK2_OBEN + This enables the LVDS output buffer for anaclk2/2b + 11 + 1 + read-write + LVDSCLK1_IBEN This enables the LVDS input buffer for anaclk1/1b @@ -24667,6 +25533,13 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 1 read-write + + LVDSCLK2_IBEN + This enables the LVDS input buffer for anaclk2/2b + 13 + 1 + read-write + PFD_480_AUTOGATE_EN This enables a feature that will clkgate (reset) all PFD_480 clocks anytime the USB1_PLL_480 is unlocked or powered off @@ -24821,6 +25694,120 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + + LVDS2_CLK_SEL + This field selects the clk to be routed to anaclk2/2b.Not related to PMU. + 5 + 5 + read-write + + + ARM_PLL + Arm PLL + 0 + + + SYS_PLL + System PLL + 0x1 + + + PFD4 + ref_pfd4_clk == pll2_pfd0_clk + 0x2 + + + PFD5 + ref_pfd5_clk == pll2_pfd1_clk + 0x3 + + + PFD6 + ref_pfd6_clk == pll2_pfd2_clk + 0x4 + + + PFD7 + ref_pfd7_clk == pll2_pfd3_clk + 0x5 + + + AUDIO_PLL + Audio PLL + 0x6 + + + VIDEO_PLL + Video PLL + 0x7 + + + MLB_PLL + MLB PLL + 0x8 + + + ETHERNET_REF + ethernet ref clock (ENET_PLL) + 0x9 + + + PCIE_REF + PCIe ref clock (125M) + 0xA + + + SATA_REF + SATA ref clock (100M) + 0xB + + + USB1_PLL + USB1 PLL clock + 0xC + + + USB2_PLL + USB2 PLL clock + 0xD + + + PFD0 + ref_pfd0_clk == pll3_pfd0_clk + 0xE + + + PFD1 + ref_pfd1_clk == pll3_pfd1_clk + 0xF + + + PFD2 + ref_pfd2_clk == pll3_pfd2_clk + 0x10 + + + PFD3 + ref_pfd3_clk == pll3_pfd3_clk + 0x11 + + + XTAL + xtal (24M) + 0x12 + + + LVDS1 + LVDS1 (loopback) + 0x13 + + + LVDS2 + LVDS2 (not useful) + 0x14 + + + LVDSCLK1_OBEN This enables the LVDS output buffer for anaclk1/1b @@ -24828,6 +25815,13 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 1 read-write + + LVDSCLK2_OBEN + This enables the LVDS output buffer for anaclk2/2b + 11 + 1 + read-write + LVDSCLK1_IBEN This enables the LVDS input buffer for anaclk1/1b @@ -24835,6 +25829,13 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 1 read-write + + LVDSCLK2_IBEN + This enables the LVDS input buffer for anaclk2/2b + 13 + 1 + read-write + PFD_480_AUTOGATE_EN This enables a feature that will clkgate (reset) all PFD_480 clocks anytime the USB1_PLL_480 is unlocked or powered off @@ -24947,6 +25948,46 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 1 read-write + + REG1_BO_OFFSET + This field defines the brown out voltage offset for the xPU power domain + 8 + 3 + read-only + + + REG1_BO_OFFSET_4 + Brownout offset = 0.100V + 0x4 + + + REG1_BO_OFFSET_7 + Brownout offset = 0.175V + 0x7 + + + + + REG1_BO_STATUS + Reg1 brownout status bit. + 11 + 1 + read-only + + + REG1_BO_STATUS_1 + Brownout, supply is below target minus brownout offset. + 0x1 + + + + + REG1_ENABLE_BO + Enables the brownout detection. + 13 + 1 + read-write + AUDIO_DIV_LSB LSB of Post-divider for Audio PLL @@ -25054,6 +26095,35 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + + REG1_STEP_TIME + Number of clock periods (24MHz clock). + 26 + 2 + read-write + + + 64_CLOCKS + 64 + 0 + + + 128_CLOCKS + 128 + 0x1 + + + 256_CLOCKS + 256 + 0x2 + + + 512_CLOCKS + 512 + 0x3 + + + REG2_STEP_TIME Number of clock periods (24MHz clock). @@ -25170,6 +26240,46 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 1 read-write + + REG1_BO_OFFSET + This field defines the brown out voltage offset for the xPU power domain + 8 + 3 + read-only + + + REG1_BO_OFFSET_4 + Brownout offset = 0.100V + 0x4 + + + REG1_BO_OFFSET_7 + Brownout offset = 0.175V + 0x7 + + + + + REG1_BO_STATUS + Reg1 brownout status bit. + 11 + 1 + read-only + + + REG1_BO_STATUS_1 + Brownout, supply is below target minus brownout offset. + 0x1 + + + + + REG1_ENABLE_BO + Enables the brownout detection. + 13 + 1 + read-write + AUDIO_DIV_LSB LSB of Post-divider for Audio PLL @@ -25277,6 +26387,35 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + + REG1_STEP_TIME + Number of clock periods (24MHz clock). + 26 + 2 + read-write + + + 64_CLOCKS + 64 + 0 + + + 128_CLOCKS + 128 + 0x1 + + + 256_CLOCKS + 256 + 0x2 + + + 512_CLOCKS + 512 + 0x3 + + + REG2_STEP_TIME Number of clock periods (24MHz clock). @@ -25393,6 +26532,46 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 1 read-write + + REG1_BO_OFFSET + This field defines the brown out voltage offset for the xPU power domain + 8 + 3 + read-only + + + REG1_BO_OFFSET_4 + Brownout offset = 0.100V + 0x4 + + + REG1_BO_OFFSET_7 + Brownout offset = 0.175V + 0x7 + + + + + REG1_BO_STATUS + Reg1 brownout status bit. + 11 + 1 + read-only + + + REG1_BO_STATUS_1 + Brownout, supply is below target minus brownout offset. + 0x1 + + + + + REG1_ENABLE_BO + Enables the brownout detection. + 13 + 1 + read-write + AUDIO_DIV_LSB LSB of Post-divider for Audio PLL @@ -25500,6 +26679,35 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + + REG1_STEP_TIME + Number of clock periods (24MHz clock). + 26 + 2 + read-write + + + 64_CLOCKS + 64 + 0 + + + 128_CLOCKS + 128 + 0x1 + + + 256_CLOCKS + 256 + 0x2 + + + 512_CLOCKS + 512 + 0x3 + + + REG2_STEP_TIME Number of clock periods (24MHz clock). @@ -25616,6 +26824,46 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 1 read-write + + REG1_BO_OFFSET + This field defines the brown out voltage offset for the xPU power domain + 8 + 3 + read-only + + + REG1_BO_OFFSET_4 + Brownout offset = 0.100V + 0x4 + + + REG1_BO_OFFSET_7 + Brownout offset = 0.175V + 0x7 + + + + + REG1_BO_STATUS + Reg1 brownout status bit. + 11 + 1 + read-only + + + REG1_BO_STATUS_1 + Brownout, supply is below target minus brownout offset. + 0x1 + + + + + REG1_ENABLE_BO + Enables the brownout detection. + 13 + 1 + read-write + AUDIO_DIV_LSB LSB of Post-divider for Audio PLL @@ -25723,6 +26971,35 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + + REG1_STEP_TIME + Number of clock periods (24MHz clock). + 26 + 2 + read-write + + + 64_CLOCKS + 64 + 0 + + + 128_CLOCKS + 128 + 0x1 + + + 256_CLOCKS + 256 + 0x2 + + + 512_CLOCKS + 512 + 0x3 + + + REG2_STEP_TIME Number of clock periods (24MHz clock). @@ -25797,6 +27074,14 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0x2A0 registers + + TEMP_LOW_HIGH + 63 + + + TEMP_PANIC + 64 + TEMPSENSE0 @@ -27971,64 +29256,23 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0x260 32 read-only - 0x640000 + 0x6A0001 0xFFFFFFFF - MINOR - MINOR lower byte - Read-only value representing a minor silicon revision. + SILICON_REVISION + Chip silicon revision 0 - 8 + 32 read-only - MINOR_0 - silicon revision x.0 - 0 - - - MINOR_1 - silicon revision x.1 - 0x1 - - - MINOR_2 - silicon revision x.2 - 0x2 - - - MINOR_3 - silicon revision x.3 - 0x3 + SILICON_REVISION_6946817 + Silicon revision 1.1 + 0x6A0001 - - MAJOR_LOWER - MAJOR lower byte - Read-only value representing a major silicon revision. - 8 - 8 - read-only - - - MAJOR_LOWER_0 - silicon revision 1.x - 0 - - - MAJOR_LOWER_1 - silicon revision 2.x - 0x1 - - - - - MAJOR_UPPER - MAJOR upper byte-Read-only value representing the chip type. - 16 - 8 - read-only - @@ -29240,7 +30484,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0x270 32 read-write - 0x4009 + 0x4001 0xFFFFFFFF @@ -29262,13 +30506,6 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - - RC_OSC_PROG - RC osc. tuning values. - 1 - 3 - read-write - OSC_SEL Select the source for the 24MHz clock. @@ -29411,6 +30648,13 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 1 read-write + + GPU_PWRGATE + GPU power gate control. Used as software mask. Set to zero to force ungated. + 18 + 1 + read-write + @@ -29419,7 +30663,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0x274 32 read-write - 0x4009 + 0x4001 0xFFFFFFFF @@ -29441,13 +30685,6 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - - RC_OSC_PROG - RC osc. tuning values. - 1 - 3 - read-write - OSC_SEL Select the source for the 24MHz clock. @@ -29590,6 +30827,13 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 1 read-write + + GPU_PWRGATE + GPU power gate control. Used as software mask. Set to zero to force ungated. + 18 + 1 + read-write + @@ -29598,7 +30842,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0x278 32 read-write - 0x4009 + 0x4001 0xFFFFFFFF @@ -29620,13 +30864,6 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - - RC_OSC_PROG - RC osc. tuning values. - 1 - 3 - read-write - OSC_SEL Select the source for the 24MHz clock. @@ -29769,6 +31006,13 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 1 read-write + + GPU_PWRGATE + GPU power gate control. Used as software mask. Set to zero to force ungated. + 18 + 1 + read-write + @@ -29777,7 +31021,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0x27C 32 read-write - 0x4009 + 0x4001 0xFFFFFFFF @@ -29799,13 +31043,6 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - - RC_OSC_PROG - RC osc. tuning values. - 1 - 3 - read-write - OSC_SEL Select the source for the 24MHz clock. @@ -29948,6 +31185,13 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 1 read-write + + GPU_PWRGATE + GPU power gate control. Used as software mask. Set to zero to force ungated. + 18 + 1 + read-write + @@ -30329,7 +31573,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. COUNT_1M_TRG - The target count used to tune the RC OSC frequency + The target count used to tune the 1MHz clock frequency 0 12 read-write @@ -30343,14 +31587,14 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. MUX_1M - Mux the corrected or uncorrected 1MHz clock to the output. + Mux the corrected or uncorrected 1MHz clock to the output 17 1 read-write CLK_1M_ERR_FL - Flag indicates that the count_1m count wasn't reached within 1 32KHz period + Flag indicates that the count_1m count wasn't reached within 1 32kHz period 31 1 read-write @@ -30368,7 +31612,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. COUNT_1M_TRG - The target count used to tune the RC OSC frequency + The target count used to tune the 1MHz clock frequency 0 12 read-write @@ -30382,14 +31626,14 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. MUX_1M - Mux the corrected or uncorrected 1MHz clock to the output. + Mux the corrected or uncorrected 1MHz clock to the output 17 1 read-write CLK_1M_ERR_FL - Flag indicates that the count_1m count wasn't reached within 1 32KHz period + Flag indicates that the count_1m count wasn't reached within 1 32kHz period 31 1 read-write @@ -30407,7 +31651,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. COUNT_1M_TRG - The target count used to tune the RC OSC frequency + The target count used to tune the 1MHz clock frequency 0 12 read-write @@ -30421,14 +31665,14 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. MUX_1M - Mux the corrected or uncorrected 1MHz clock to the output. + Mux the corrected or uncorrected 1MHz clock to the output 17 1 read-write CLK_1M_ERR_FL - Flag indicates that the count_1m count wasn't reached within 1 32KHz period + Flag indicates that the count_1m count wasn't reached within 1 32kHz period 31 1 read-write @@ -30446,7 +31690,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. COUNT_1M_TRG - The target count used to tune the RC OSC frequency + The target count used to tune the 1MHz clock frequency 0 12 read-write @@ -30460,14 +31704,14 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. MUX_1M - Mux the corrected or uncorrected 1MHz clock to the output. + Mux the corrected or uncorrected 1MHz clock to the output 17 1 read-write CLK_1M_ERR_FL - Flag indicates that the count_1m count wasn't reached within 1 32KHz period + Flag indicates that the count_1m count wasn't reached within 1 32kHz period 31 1 read-write @@ -32913,7 +34157,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0x80 32 read-only - 0x4020000 + 0x4030000 0xFFFFFFFF @@ -34522,7 +35766,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. BASIC_SETTING - PS Input Buffer Address + no description available 0 32 read-write @@ -34577,8 +35821,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - PS_INPUT_BUFFER_ADDR - PS Input Buffer Address + PRE_CHARGE_TIME + no description available 0x10 32 read-write @@ -34587,22 +35831,10 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. PRE_CHARGE_TIME - Auto Measure + Before detection, the top screen needs some time before being pulled up to a high voltage. 0 32 read-write - - - PRE_CHARGE_TIME_0 - Disable Auto Measure - 0 - - - PRE_CHARGE_TIME_1 - Auto Measure - 0x1 - - @@ -34743,9 +35975,14 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. MEASURE_INT_EN_0 - Disable measure + Disable measure interrupt 0 + + MEASURE_INT_EN_1 + Enable measure interrupt + 0x1 + @@ -40291,10 +41528,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - 32 - 0x1 - 3,2,1,0,7,6,5,4,11,10,9,8,15,14,13,12,19,18,17,16,23,22,21,20,27,26,25,24,31,30,29,28 - DCHPRI%s + DCHPRI3 Channel n Priority Register 0x100 8 @@ -40356,6 +41590,1959 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + + DCHPRI2 + Channel n Priority Register + 0x101 + 8 + read-write + 0x2 + 0xFF + + + CHPRI + Channel n Arbitration Priority + 0 + 4 + read-write + + + GRPPRI + Channel n Current Group Priority + 4 + 2 + read-only + + + DPA + Disable Preempt Ability. This field resets to 0. + 6 + 1 + read-write + + + DPA_0 + Channel n can suspend a lower priority channel. + 0 + + + DPA_1 + Channel n cannot suspend any channel, regardless of channel priority. + 0x1 + + + + + ECP + Enable Channel Preemption. This field resets to 0. + 7 + 1 + read-write + + + ECP_0 + Channel n cannot be suspended by a higher priority channel's service request. + 0 + + + ECP_1 + Channel n can be temporarily suspended by the service request of a higher priority channel. + 0x1 + + + + + + + DCHPRI1 + Channel n Priority Register + 0x102 + 8 + read-write + 0x1 + 0xFF + + + CHPRI + Channel n Arbitration Priority + 0 + 4 + read-write + + + GRPPRI + Channel n Current Group Priority + 4 + 2 + read-only + + + DPA + Disable Preempt Ability. This field resets to 0. + 6 + 1 + read-write + + + DPA_0 + Channel n can suspend a lower priority channel. + 0 + + + DPA_1 + Channel n cannot suspend any channel, regardless of channel priority. + 0x1 + + + + + ECP + Enable Channel Preemption. This field resets to 0. + 7 + 1 + read-write + + + ECP_0 + Channel n cannot be suspended by a higher priority channel's service request. + 0 + + + ECP_1 + Channel n can be temporarily suspended by the service request of a higher priority channel. + 0x1 + + + + + + + DCHPRI0 + Channel n Priority Register + 0x103 + 8 + read-write + 0 + 0xFF + + + CHPRI + Channel n Arbitration Priority + 0 + 4 + read-write + + + GRPPRI + Channel n Current Group Priority + 4 + 2 + read-only + + + DPA + Disable Preempt Ability. This field resets to 0. + 6 + 1 + read-write + + + DPA_0 + Channel n can suspend a lower priority channel. + 0 + + + DPA_1 + Channel n cannot suspend any channel, regardless of channel priority. + 0x1 + + + + + ECP + Enable Channel Preemption. This field resets to 0. + 7 + 1 + read-write + + + ECP_0 + Channel n cannot be suspended by a higher priority channel's service request. + 0 + + + ECP_1 + Channel n can be temporarily suspended by the service request of a higher priority channel. + 0x1 + + + + + + + DCHPRI7 + Channel n Priority Register + 0x104 + 8 + read-write + 0x7 + 0xFF + + + CHPRI + Channel n Arbitration Priority + 0 + 4 + read-write + + + GRPPRI + Channel n Current Group Priority + 4 + 2 + read-only + + + DPA + Disable Preempt Ability. This field resets to 0. + 6 + 1 + read-write + + + DPA_0 + Channel n can suspend a lower priority channel. + 0 + + + DPA_1 + Channel n cannot suspend any channel, regardless of channel priority. + 0x1 + + + + + ECP + Enable Channel Preemption. This field resets to 0. + 7 + 1 + read-write + + + ECP_0 + Channel n cannot be suspended by a higher priority channel's service request. + 0 + + + ECP_1 + Channel n can be temporarily suspended by the service request of a higher priority channel. + 0x1 + + + + + + + DCHPRI6 + Channel n Priority Register + 0x105 + 8 + read-write + 0x6 + 0xFF + + + CHPRI + Channel n Arbitration Priority + 0 + 4 + read-write + + + GRPPRI + Channel n Current Group Priority + 4 + 2 + read-only + + + DPA + Disable Preempt Ability. This field resets to 0. + 6 + 1 + read-write + + + DPA_0 + Channel n can suspend a lower priority channel. + 0 + + + DPA_1 + Channel n cannot suspend any channel, regardless of channel priority. + 0x1 + + + + + ECP + Enable Channel Preemption. This field resets to 0. + 7 + 1 + read-write + + + ECP_0 + Channel n cannot be suspended by a higher priority channel's service request. + 0 + + + ECP_1 + Channel n can be temporarily suspended by the service request of a higher priority channel. + 0x1 + + + + + + + DCHPRI5 + Channel n Priority Register + 0x106 + 8 + read-write + 0x5 + 0xFF + + + CHPRI + Channel n Arbitration Priority + 0 + 4 + read-write + + + GRPPRI + Channel n Current Group Priority + 4 + 2 + read-only + + + DPA + Disable Preempt Ability. This field resets to 0. + 6 + 1 + read-write + + + DPA_0 + Channel n can suspend a lower priority channel. + 0 + + + DPA_1 + Channel n cannot suspend any channel, regardless of channel priority. + 0x1 + + + + + ECP + Enable Channel Preemption. This field resets to 0. + 7 + 1 + read-write + + + ECP_0 + Channel n cannot be suspended by a higher priority channel's service request. + 0 + + + ECP_1 + Channel n can be temporarily suspended by the service request of a higher priority channel. + 0x1 + + + + + + + DCHPRI4 + Channel n Priority Register + 0x107 + 8 + read-write + 0x4 + 0xFF + + + CHPRI + Channel n Arbitration Priority + 0 + 4 + read-write + + + GRPPRI + Channel n Current Group Priority + 4 + 2 + read-only + + + DPA + Disable Preempt Ability. This field resets to 0. + 6 + 1 + read-write + + + DPA_0 + Channel n can suspend a lower priority channel. + 0 + + + DPA_1 + Channel n cannot suspend any channel, regardless of channel priority. + 0x1 + + + + + ECP + Enable Channel Preemption. This field resets to 0. + 7 + 1 + read-write + + + ECP_0 + Channel n cannot be suspended by a higher priority channel's service request. + 0 + + + ECP_1 + Channel n can be temporarily suspended by the service request of a higher priority channel. + 0x1 + + + + + + + DCHPRI11 + Channel n Priority Register + 0x108 + 8 + read-write + 0xB + 0xFF + + + CHPRI + Channel n Arbitration Priority + 0 + 4 + read-write + + + GRPPRI + Channel n Current Group Priority + 4 + 2 + read-only + + + DPA + Disable Preempt Ability. This field resets to 0. + 6 + 1 + read-write + + + DPA_0 + Channel n can suspend a lower priority channel. + 0 + + + DPA_1 + Channel n cannot suspend any channel, regardless of channel priority. + 0x1 + + + + + ECP + Enable Channel Preemption. This field resets to 0. + 7 + 1 + read-write + + + ECP_0 + Channel n cannot be suspended by a higher priority channel's service request. + 0 + + + ECP_1 + Channel n can be temporarily suspended by the service request of a higher priority channel. + 0x1 + + + + + + + DCHPRI10 + Channel n Priority Register + 0x109 + 8 + read-write + 0xA + 0xFF + + + CHPRI + Channel n Arbitration Priority + 0 + 4 + read-write + + + GRPPRI + Channel n Current Group Priority + 4 + 2 + read-only + + + DPA + Disable Preempt Ability. This field resets to 0. + 6 + 1 + read-write + + + DPA_0 + Channel n can suspend a lower priority channel. + 0 + + + DPA_1 + Channel n cannot suspend any channel, regardless of channel priority. + 0x1 + + + + + ECP + Enable Channel Preemption. This field resets to 0. + 7 + 1 + read-write + + + ECP_0 + Channel n cannot be suspended by a higher priority channel's service request. + 0 + + + ECP_1 + Channel n can be temporarily suspended by the service request of a higher priority channel. + 0x1 + + + + + + + DCHPRI9 + Channel n Priority Register + 0x10A + 8 + read-write + 0x9 + 0xFF + + + CHPRI + Channel n Arbitration Priority + 0 + 4 + read-write + + + GRPPRI + Channel n Current Group Priority + 4 + 2 + read-only + + + DPA + Disable Preempt Ability. This field resets to 0. + 6 + 1 + read-write + + + DPA_0 + Channel n can suspend a lower priority channel. + 0 + + + DPA_1 + Channel n cannot suspend any channel, regardless of channel priority. + 0x1 + + + + + ECP + Enable Channel Preemption. This field resets to 0. + 7 + 1 + read-write + + + ECP_0 + Channel n cannot be suspended by a higher priority channel's service request. + 0 + + + ECP_1 + Channel n can be temporarily suspended by the service request of a higher priority channel. + 0x1 + + + + + + + DCHPRI8 + Channel n Priority Register + 0x10B + 8 + read-write + 0x8 + 0xFF + + + CHPRI + Channel n Arbitration Priority + 0 + 4 + read-write + + + GRPPRI + Channel n Current Group Priority + 4 + 2 + read-only + + + DPA + Disable Preempt Ability. This field resets to 0. + 6 + 1 + read-write + + + DPA_0 + Channel n can suspend a lower priority channel. + 0 + + + DPA_1 + Channel n cannot suspend any channel, regardless of channel priority. + 0x1 + + + + + ECP + Enable Channel Preemption. This field resets to 0. + 7 + 1 + read-write + + + ECP_0 + Channel n cannot be suspended by a higher priority channel's service request. + 0 + + + ECP_1 + Channel n can be temporarily suspended by the service request of a higher priority channel. + 0x1 + + + + + + + DCHPRI15 + Channel n Priority Register + 0x10C + 8 + read-write + 0xF + 0xFF + + + CHPRI + Channel n Arbitration Priority + 0 + 4 + read-write + + + GRPPRI + Channel n Current Group Priority + 4 + 2 + read-only + + + DPA + Disable Preempt Ability. This field resets to 0. + 6 + 1 + read-write + + + DPA_0 + Channel n can suspend a lower priority channel. + 0 + + + DPA_1 + Channel n cannot suspend any channel, regardless of channel priority. + 0x1 + + + + + ECP + Enable Channel Preemption. This field resets to 0. + 7 + 1 + read-write + + + ECP_0 + Channel n cannot be suspended by a higher priority channel's service request. + 0 + + + ECP_1 + Channel n can be temporarily suspended by the service request of a higher priority channel. + 0x1 + + + + + + + DCHPRI14 + Channel n Priority Register + 0x10D + 8 + read-write + 0xE + 0xFF + + + CHPRI + Channel n Arbitration Priority + 0 + 4 + read-write + + + GRPPRI + Channel n Current Group Priority + 4 + 2 + read-only + + + DPA + Disable Preempt Ability. This field resets to 0. + 6 + 1 + read-write + + + DPA_0 + Channel n can suspend a lower priority channel. + 0 + + + DPA_1 + Channel n cannot suspend any channel, regardless of channel priority. + 0x1 + + + + + ECP + Enable Channel Preemption. This field resets to 0. + 7 + 1 + read-write + + + ECP_0 + Channel n cannot be suspended by a higher priority channel's service request. + 0 + + + ECP_1 + Channel n can be temporarily suspended by the service request of a higher priority channel. + 0x1 + + + + + + + DCHPRI13 + Channel n Priority Register + 0x10E + 8 + read-write + 0xD + 0xFF + + + CHPRI + Channel n Arbitration Priority + 0 + 4 + read-write + + + GRPPRI + Channel n Current Group Priority + 4 + 2 + read-only + + + DPA + Disable Preempt Ability. This field resets to 0. + 6 + 1 + read-write + + + DPA_0 + Channel n can suspend a lower priority channel. + 0 + + + DPA_1 + Channel n cannot suspend any channel, regardless of channel priority. + 0x1 + + + + + ECP + Enable Channel Preemption. This field resets to 0. + 7 + 1 + read-write + + + ECP_0 + Channel n cannot be suspended by a higher priority channel's service request. + 0 + + + ECP_1 + Channel n can be temporarily suspended by the service request of a higher priority channel. + 0x1 + + + + + + + DCHPRI12 + Channel n Priority Register + 0x10F + 8 + read-write + 0xC + 0xFF + + + CHPRI + Channel n Arbitration Priority + 0 + 4 + read-write + + + GRPPRI + Channel n Current Group Priority + 4 + 2 + read-only + + + DPA + Disable Preempt Ability. This field resets to 0. + 6 + 1 + read-write + + + DPA_0 + Channel n can suspend a lower priority channel. + 0 + + + DPA_1 + Channel n cannot suspend any channel, regardless of channel priority. + 0x1 + + + + + ECP + Enable Channel Preemption. This field resets to 0. + 7 + 1 + read-write + + + ECP_0 + Channel n cannot be suspended by a higher priority channel's service request. + 0 + + + ECP_1 + Channel n can be temporarily suspended by the service request of a higher priority channel. + 0x1 + + + + + + + DCHPRI19 + Channel n Priority Register + 0x110 + 8 + read-write + 0x13 + 0xFF + + + CHPRI + Channel n Arbitration Priority + 0 + 4 + read-write + + + GRPPRI + Channel n Current Group Priority + 4 + 2 + read-only + + + DPA + Disable Preempt Ability. This field resets to 0. + 6 + 1 + read-write + + + DPA_0 + Channel n can suspend a lower priority channel. + 0 + + + DPA_1 + Channel n cannot suspend any channel, regardless of channel priority. + 0x1 + + + + + ECP + Enable Channel Preemption. This field resets to 0. + 7 + 1 + read-write + + + ECP_0 + Channel n cannot be suspended by a higher priority channel's service request. + 0 + + + ECP_1 + Channel n can be temporarily suspended by the service request of a higher priority channel. + 0x1 + + + + + + + DCHPRI18 + Channel n Priority Register + 0x111 + 8 + read-write + 0x12 + 0xFF + + + CHPRI + Channel n Arbitration Priority + 0 + 4 + read-write + + + GRPPRI + Channel n Current Group Priority + 4 + 2 + read-only + + + DPA + Disable Preempt Ability. This field resets to 0. + 6 + 1 + read-write + + + DPA_0 + Channel n can suspend a lower priority channel. + 0 + + + DPA_1 + Channel n cannot suspend any channel, regardless of channel priority. + 0x1 + + + + + ECP + Enable Channel Preemption. This field resets to 0. + 7 + 1 + read-write + + + ECP_0 + Channel n cannot be suspended by a higher priority channel's service request. + 0 + + + ECP_1 + Channel n can be temporarily suspended by the service request of a higher priority channel. + 0x1 + + + + + + + DCHPRI17 + Channel n Priority Register + 0x112 + 8 + read-write + 0x11 + 0xFF + + + CHPRI + Channel n Arbitration Priority + 0 + 4 + read-write + + + GRPPRI + Channel n Current Group Priority + 4 + 2 + read-only + + + DPA + Disable Preempt Ability. This field resets to 0. + 6 + 1 + read-write + + + DPA_0 + Channel n can suspend a lower priority channel. + 0 + + + DPA_1 + Channel n cannot suspend any channel, regardless of channel priority. + 0x1 + + + + + ECP + Enable Channel Preemption. This field resets to 0. + 7 + 1 + read-write + + + ECP_0 + Channel n cannot be suspended by a higher priority channel's service request. + 0 + + + ECP_1 + Channel n can be temporarily suspended by the service request of a higher priority channel. + 0x1 + + + + + + + DCHPRI16 + Channel n Priority Register + 0x113 + 8 + read-write + 0x10 + 0xFF + + + CHPRI + Channel n Arbitration Priority + 0 + 4 + read-write + + + GRPPRI + Channel n Current Group Priority + 4 + 2 + read-only + + + DPA + Disable Preempt Ability. This field resets to 0. + 6 + 1 + read-write + + + DPA_0 + Channel n can suspend a lower priority channel. + 0 + + + DPA_1 + Channel n cannot suspend any channel, regardless of channel priority. + 0x1 + + + + + ECP + Enable Channel Preemption. This field resets to 0. + 7 + 1 + read-write + + + ECP_0 + Channel n cannot be suspended by a higher priority channel's service request. + 0 + + + ECP_1 + Channel n can be temporarily suspended by the service request of a higher priority channel. + 0x1 + + + + + + + DCHPRI23 + Channel n Priority Register + 0x114 + 8 + read-write + 0x17 + 0xFF + + + CHPRI + Channel n Arbitration Priority + 0 + 4 + read-write + + + GRPPRI + Channel n Current Group Priority + 4 + 2 + read-only + + + DPA + Disable Preempt Ability. This field resets to 0. + 6 + 1 + read-write + + + DPA_0 + Channel n can suspend a lower priority channel. + 0 + + + DPA_1 + Channel n cannot suspend any channel, regardless of channel priority. + 0x1 + + + + + ECP + Enable Channel Preemption. This field resets to 0. + 7 + 1 + read-write + + + ECP_0 + Channel n cannot be suspended by a higher priority channel's service request. + 0 + + + ECP_1 + Channel n can be temporarily suspended by the service request of a higher priority channel. + 0x1 + + + + + + + DCHPRI22 + Channel n Priority Register + 0x115 + 8 + read-write + 0x16 + 0xFF + + + CHPRI + Channel n Arbitration Priority + 0 + 4 + read-write + + + GRPPRI + Channel n Current Group Priority + 4 + 2 + read-only + + + DPA + Disable Preempt Ability. This field resets to 0. + 6 + 1 + read-write + + + DPA_0 + Channel n can suspend a lower priority channel. + 0 + + + DPA_1 + Channel n cannot suspend any channel, regardless of channel priority. + 0x1 + + + + + ECP + Enable Channel Preemption. This field resets to 0. + 7 + 1 + read-write + + + ECP_0 + Channel n cannot be suspended by a higher priority channel's service request. + 0 + + + ECP_1 + Channel n can be temporarily suspended by the service request of a higher priority channel. + 0x1 + + + + + + + DCHPRI21 + Channel n Priority Register + 0x116 + 8 + read-write + 0x15 + 0xFF + + + CHPRI + Channel n Arbitration Priority + 0 + 4 + read-write + + + GRPPRI + Channel n Current Group Priority + 4 + 2 + read-only + + + DPA + Disable Preempt Ability. This field resets to 0. + 6 + 1 + read-write + + + DPA_0 + Channel n can suspend a lower priority channel. + 0 + + + DPA_1 + Channel n cannot suspend any channel, regardless of channel priority. + 0x1 + + + + + ECP + Enable Channel Preemption. This field resets to 0. + 7 + 1 + read-write + + + ECP_0 + Channel n cannot be suspended by a higher priority channel's service request. + 0 + + + ECP_1 + Channel n can be temporarily suspended by the service request of a higher priority channel. + 0x1 + + + + + + + DCHPRI20 + Channel n Priority Register + 0x117 + 8 + read-write + 0x14 + 0xFF + + + CHPRI + Channel n Arbitration Priority + 0 + 4 + read-write + + + GRPPRI + Channel n Current Group Priority + 4 + 2 + read-only + + + DPA + Disable Preempt Ability. This field resets to 0. + 6 + 1 + read-write + + + DPA_0 + Channel n can suspend a lower priority channel. + 0 + + + DPA_1 + Channel n cannot suspend any channel, regardless of channel priority. + 0x1 + + + + + ECP + Enable Channel Preemption. This field resets to 0. + 7 + 1 + read-write + + + ECP_0 + Channel n cannot be suspended by a higher priority channel's service request. + 0 + + + ECP_1 + Channel n can be temporarily suspended by the service request of a higher priority channel. + 0x1 + + + + + + + DCHPRI27 + Channel n Priority Register + 0x118 + 8 + read-write + 0x1B + 0xFF + + + CHPRI + Channel n Arbitration Priority + 0 + 4 + read-write + + + GRPPRI + Channel n Current Group Priority + 4 + 2 + read-only + + + DPA + Disable Preempt Ability. This field resets to 0. + 6 + 1 + read-write + + + DPA_0 + Channel n can suspend a lower priority channel. + 0 + + + DPA_1 + Channel n cannot suspend any channel, regardless of channel priority. + 0x1 + + + + + ECP + Enable Channel Preemption. This field resets to 0. + 7 + 1 + read-write + + + ECP_0 + Channel n cannot be suspended by a higher priority channel's service request. + 0 + + + ECP_1 + Channel n can be temporarily suspended by the service request of a higher priority channel. + 0x1 + + + + + + + DCHPRI26 + Channel n Priority Register + 0x119 + 8 + read-write + 0x1A + 0xFF + + + CHPRI + Channel n Arbitration Priority + 0 + 4 + read-write + + + GRPPRI + Channel n Current Group Priority + 4 + 2 + read-only + + + DPA + Disable Preempt Ability. This field resets to 0. + 6 + 1 + read-write + + + DPA_0 + Channel n can suspend a lower priority channel. + 0 + + + DPA_1 + Channel n cannot suspend any channel, regardless of channel priority. + 0x1 + + + + + ECP + Enable Channel Preemption. This field resets to 0. + 7 + 1 + read-write + + + ECP_0 + Channel n cannot be suspended by a higher priority channel's service request. + 0 + + + ECP_1 + Channel n can be temporarily suspended by the service request of a higher priority channel. + 0x1 + + + + + + + DCHPRI25 + Channel n Priority Register + 0x11A + 8 + read-write + 0x19 + 0xFF + + + CHPRI + Channel n Arbitration Priority + 0 + 4 + read-write + + + GRPPRI + Channel n Current Group Priority + 4 + 2 + read-only + + + DPA + Disable Preempt Ability. This field resets to 0. + 6 + 1 + read-write + + + DPA_0 + Channel n can suspend a lower priority channel. + 0 + + + DPA_1 + Channel n cannot suspend any channel, regardless of channel priority. + 0x1 + + + + + ECP + Enable Channel Preemption. This field resets to 0. + 7 + 1 + read-write + + + ECP_0 + Channel n cannot be suspended by a higher priority channel's service request. + 0 + + + ECP_1 + Channel n can be temporarily suspended by the service request of a higher priority channel. + 0x1 + + + + + + + DCHPRI24 + Channel n Priority Register + 0x11B + 8 + read-write + 0x18 + 0xFF + + + CHPRI + Channel n Arbitration Priority + 0 + 4 + read-write + + + GRPPRI + Channel n Current Group Priority + 4 + 2 + read-only + + + DPA + Disable Preempt Ability. This field resets to 0. + 6 + 1 + read-write + + + DPA_0 + Channel n can suspend a lower priority channel. + 0 + + + DPA_1 + Channel n cannot suspend any channel, regardless of channel priority. + 0x1 + + + + + ECP + Enable Channel Preemption. This field resets to 0. + 7 + 1 + read-write + + + ECP_0 + Channel n cannot be suspended by a higher priority channel's service request. + 0 + + + ECP_1 + Channel n can be temporarily suspended by the service request of a higher priority channel. + 0x1 + + + + + + + DCHPRI31 + Channel n Priority Register + 0x11C + 8 + read-write + 0x1F + 0xFF + + + CHPRI + Channel n Arbitration Priority + 0 + 4 + read-write + + + GRPPRI + Channel n Current Group Priority + 4 + 2 + read-only + + + DPA + Disable Preempt Ability. This field resets to 0. + 6 + 1 + read-write + + + DPA_0 + Channel n can suspend a lower priority channel. + 0 + + + DPA_1 + Channel n cannot suspend any channel, regardless of channel priority. + 0x1 + + + + + ECP + Enable Channel Preemption. This field resets to 0. + 7 + 1 + read-write + + + ECP_0 + Channel n cannot be suspended by a higher priority channel's service request. + 0 + + + ECP_1 + Channel n can be temporarily suspended by the service request of a higher priority channel. + 0x1 + + + + + + + DCHPRI30 + Channel n Priority Register + 0x11D + 8 + read-write + 0x1E + 0xFF + + + CHPRI + Channel n Arbitration Priority + 0 + 4 + read-write + + + GRPPRI + Channel n Current Group Priority + 4 + 2 + read-only + + + DPA + Disable Preempt Ability. This field resets to 0. + 6 + 1 + read-write + + + DPA_0 + Channel n can suspend a lower priority channel. + 0 + + + DPA_1 + Channel n cannot suspend any channel, regardless of channel priority. + 0x1 + + + + + ECP + Enable Channel Preemption. This field resets to 0. + 7 + 1 + read-write + + + ECP_0 + Channel n cannot be suspended by a higher priority channel's service request. + 0 + + + ECP_1 + Channel n can be temporarily suspended by the service request of a higher priority channel. + 0x1 + + + + + + + DCHPRI29 + Channel n Priority Register + 0x11E + 8 + read-write + 0x1D + 0xFF + + + CHPRI + Channel n Arbitration Priority + 0 + 4 + read-write + + + GRPPRI + Channel n Current Group Priority + 4 + 2 + read-only + + + DPA + Disable Preempt Ability. This field resets to 0. + 6 + 1 + read-write + + + DPA_0 + Channel n can suspend a lower priority channel. + 0 + + + DPA_1 + Channel n cannot suspend any channel, regardless of channel priority. + 0x1 + + + + + ECP + Enable Channel Preemption. This field resets to 0. + 7 + 1 + read-write + + + ECP_0 + Channel n cannot be suspended by a higher priority channel's service request. + 0 + + + ECP_1 + Channel n can be temporarily suspended by the service request of a higher priority channel. + 0x1 + + + + + + + DCHPRI28 + Channel n Priority Register + 0x11F + 8 + read-write + 0x1C + 0xFF + + + CHPRI + Channel n Arbitration Priority + 0 + 4 + read-write + + + GRPPRI + Channel n Current Group Priority + 4 + 2 + read-only + + + DPA + Disable Preempt Ability. This field resets to 0. + 6 + 1 + read-write + + + DPA_0 + Channel n can suspend a lower priority channel. + 0 + + + DPA_1 + Channel n cannot suspend any channel, regardless of channel priority. + 0x1 + + + + + ECP + Enable Channel Preemption. This field resets to 0. + 7 + 1 + read-write + + + ECP_0 + Channel n cannot be suspended by a higher priority channel's service request. + 0 + + + ECP_1 + Channel n can be temporarily suspended by the service request of a higher priority channel. + 0x1 + + + + + TCD0_SADDR TCD Source Address @@ -63467,28 +66654,9 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 32 read-write - 0x500 + 0xA0480520 0xFFFFFFFF - - lockup_rst - lockup reset enable bit - 4 - 1 - read-write - - - lockup_rst_0 - disabled - 0 - - - lockup_rst_1 - enabled - 0x1 - - - mask_wdog_rst Mask wdog_rst_b source @@ -63990,7 +67158,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 32 read-write - 0x401167F + 0x401107F 0xFFFFFFFF @@ -64180,7 +67348,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0x10 32 read-write - 0 + 0x1 0xFFFFFFFF @@ -64240,7 +67408,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0x14 32 read-write - 0xB8600 + 0xA8300 0xFFFFFFFF @@ -64283,7 +67451,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. IPG_PODF - Divider for ipg podf + Divider for ipg podf. 8 2 read-write @@ -64484,7 +67652,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0x18 32 read-write - 0x2DA28324 + 0x2DAE8324 0xFFFFFFFF @@ -64704,7 +67872,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0x1C 32 read-write - 0x4900080 + 0x4900000 0xFFFFFFFF @@ -64971,12 +68139,12 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0x20 32 read-write - 0x3192C06 + 0x13192F06 0xFFFFFFFF CAN_CLK_PODF - Divider for can clock podf. + Divider for CAN clock podf. 2 6 read-write @@ -65000,7 +68168,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. CAN_CLK_SEL - Selector for FlexCAN clock multiplexer + Selector for CAN clock multiplexer 8 2 read-write @@ -65020,6 +68188,11 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. derive clock from pll3_sw_clk divided clock (80M) 0x2 + + CAN_CLK_SEL_3 + Disable FlexCAN clock + 0x3 + @@ -65059,7 +68232,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0x24 32 read-write - 0x490B00 + 0x6490B00 0xFFFFFFFF @@ -65202,7 +68375,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. TRACE_PODF Divider for trace clock. Divider should be updated when output clock is gated. 25 - 3 + 2 read-write @@ -65225,26 +68398,6 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. divide by 4 0x3 - - TRACE_PODF_4 - divide by 5 - 0x4 - - - TRACE_PODF_5 - divide by 6 - 0x5 - - - TRACE_PODF_6 - divide by 7 - 0x6 - - - TRACE_PODF_7 - divide by 8 - 0x7 - @@ -65500,7 +68653,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0x2C 32 read-write - 0x336C1 + 0x7336C1 0xFFFFFFFF @@ -65744,43 +68897,9 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0x38 32 read-write - 0x29B48 + 0x29150 0xFFFFFFFF - - LCDIF_CLK_SEL - Selector for LCDIF root clock multiplexer - 9 - 3 - read-write - - - LCDIF_CLK_SEL_0 - derive clock from divided pre-muxed LCDIF clock - 0 - - - LCDIF_CLK_SEL_1 - derive clock from ipp_di0_clk - 0x1 - - - LCDIF_CLK_SEL_2 - derive clock from ipp_di1_clk - 0x2 - - - LCDIF_CLK_SEL_3 - derive clock from ldb_di0_clk - 0x3 - - - LCDIF_CLK_SEL_4 - derive clock from ldb_di1_clk - 0x4 - - - LCDIF_PRED Pre-divider for lcdif clock. Divider should be updated when output clock is gated. @@ -65915,7 +69034,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0x3C 32 read-write - 0x14841 + 0x30841 0xFFFFFFFF @@ -66645,16 +69764,26 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 4 read-write + + CLKO1_SEL_0 + USB1 PLL clock (divided by 2) + 0 + + + CLKO1_SEL_1 + SYS PLL clock (divided by 2) + 0x1 + + + CLKO1_SEL_3 + VIDEO PLL clock (divided by 2) + 0x3 + CLKO1_SEL_5 semc_clk_root 0x5 - - CLKO1_SEL_6 - enc_clk_root - 0x6 - CLKO1_SEL_10 lcdif_pix_clk_root @@ -66798,7 +69927,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. CLKO2_SEL_11 - csi_core + csi_clk_root 0xB @@ -67061,14 +70190,14 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. CG3 - Reserved + flexspi_exsc clock (flexspi_exsc_clk_enable) 6 2 read-write CG4 - Reserved + sim_m or sim_main register access clock (sim_m_mainclk_r_enable) 8 2 read-write @@ -67226,21 +70355,21 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. CG9 - Reserved + semc_exsc clock (semc_exsc_clk_enable) 18 2 read-write CG10 - gpt bus clock (gpt_clk_enable) + gpt1 bus clock (gpt_clk_enable) 20 2 read-write CG11 - gpt serial clock (gpt_serial_clk_enable) + gpt1 serial clock (gpt_serial_clk_enable) 22 2 read-write @@ -67268,7 +70397,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. CG15 - gpio5 clock (gpio5_clk_enable) + Reserved 30 2 read-write @@ -67286,7 +70415,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. CG0 - Reserved + ocram_exsc clock (ocram_exsc_clk_enable) 0 2 read-write @@ -67444,7 +70573,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. CG5 - LCDIF pix clock (LCDIF_pix_clk_enable) + lcdif pix clock (lcdif_pix_clk_enable) 10 2 read-write @@ -67532,7 +70661,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. CG0 - Reserved + sim_m7 register access clock (sim_m7_mainclk_r_enable) 0 2 read-write @@ -67813,7 +70942,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. CG5 - flexspi clocks (flexspi_clk_enable) + flexspi clocks (flexspi_clk_enable) sim_ems_clk_enable must also be cleared, when flexspi_clk_enable is cleared 10 2 read-write @@ -67876,14 +71005,14 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. CG14 - timer2 clocks (timer4_clk_enable) + timer2 clocks (timer2_clk_enable) 28 2 read-write CG15 - timer3 clocks (timer4_clk_enable) + timer3 clocks (timer3_clk_enable) 30 2 read-write @@ -68152,14 +71281,14 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. THUMBX - THUMB Comparator Select - Indicates that this address will trigger a THUMB opcode patch or an ARM opcode patch + THUMB Comparator Select - Indicates that this address will trigger a THUMB opcode patch or an Arm opcode patch 0 1 read-write THUMBX_0 - ARM patch + Arm patch 0 @@ -68434,12 +71563,12 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. RXEDGIE_0 - Hardware interrupts from LPUART_STAT[RXEDGIF] disabled. + Hardware interrupts from STAT[RXEDGIF] are disabled. 0 RXEDGIE_1 - Hardware interrupt requested when LPUART_STAT[RXEDGIF] flag is 1. + Hardware interrupt is requested when STAT[RXEDGIF] flag is 1. 0x1 @@ -68453,12 +71582,12 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. LBKDIE_0 - Hardware interrupts from LPUART_STAT[LBKDIF] disabled (use polling). + Hardware interrupts from STAT[LBKDIF] flag are disabled (use polling). 0 LBKDIE_1 - Hardware interrupt requested when LPUART_STAT[LBKDIF] flag is 1. + Hardware interrupt requested when STAT[LBKDIF] flag is 1. 0x1 @@ -68530,6 +71659,25 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + + RIDMAE + Receiver Idle DMA Enable + 20 + 1 + read-write + + + RIDMAE_0 + DMA request disabled. + 0 + + + RIDMAE_1 + DMA request enabled. + 0x1 + + + RDMAE Receiver Full DMA Enable @@ -68890,7 +72038,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. NF_1 - Noise detected in the received character in LPUART_DATA. + Noise detected in the received character in the DATA register. 0x1 @@ -70089,7 +73237,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. RXFIFOSIZE - Receive FIFO. Buffer Depth + Receive FIFO Buffer Depth 0 3 read-only @@ -70145,7 +73293,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. RXFE_0 - Receive FIFO is not enabled. Buffer is depth 1. (Legacy support) + Receive FIFO is not enabled. Buffer is depth 1. 0 @@ -70157,7 +73305,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. TXFIFOSIZE - Transmit FIFO. Buffer Depth + Transmit FIFO Buffer Depth 4 3 read-only @@ -70213,7 +73361,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. TXFE_0 - Transmit FIFO is not enabled. Buffer is depth 1. (Legacy support). + Transmit FIFO is not enabled. Buffer is depth 1. 0 @@ -71523,12 +74671,12 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. TIMDIS_2 - Timer disabled on Timer compare + Timer disabled on Timer compare (upper 8-bits match and decrement) 0x2 TIMDIS_3 - Timer disabled on Timer compare and Trigger Low + Timer disabled on Timer compare (upper 8-bits match and decrement) and Trigger Low 0x3 @@ -71752,7 +74900,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0x401B8000 0 - 0x20 + 0x90 registers @@ -72855,6 +76003,60 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + + DR_SET + GPIO data register SET + 0x84 + 32 + write-only + 0 + 0xFFFFFFFF + + + DR_SET + DR_SET + 0 + 32 + write-only + + + + + DR_CLEAR + GPIO data register CLEAR + 0x88 + 32 + write-only + 0 + 0xFFFFFFFF + + + DR_CLEAR + DR_CLEAR + 0 + 32 + write-only + + + + + DR_TOGGLE + GPIO data register TOGGLE + 0x8C + 32 + write-only + 0 + 0xFFFFFFFF + + + DR_TOGGLE + DR_TOGGLE + 0 + 32 + write-only + + + @@ -72864,7 +76066,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0x400C0000 0 - 0x20 + 0x90 registers @@ -72883,7 +76085,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0x401BC000 0 - 0x20 + 0x90 registers @@ -72902,7 +76104,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0x401C0000 0 - 0x20 + 0x90 registers @@ -72921,7 +76123,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0x401C4000 0 - 0x20 + 0x90 registers @@ -73282,7 +76484,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. FRZ - The FRZ bit specifies the FLEXCAN behavior when the HALT bit in the MCR Register is set or when Debug Mode is requested at ARM level + The FRZ bit specifies the FLEXCAN behavior when the HALT bit in the MCR Register is set or when Debug Mode is requested at Arm level 30 1 read-write @@ -73700,7 +76902,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. WAKINT - When FLEXCAN is Stop Mode and a recessive to dominant transition is detected on the CAN bus and if the WAK_MSK bit in the MCR Register is set, an interrupt is generated to the ARM + When FLEXCAN is Stop Mode and a recessive to dominant transition is detected on the CAN bus and if the WAK_MSK bit in the MCR Register is set, an interrupt is generated to the Arm 0 1 read-write @@ -74473,6 +77675,94 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + + DBG1 + Debug 1 register + 0x58 + 32 + read-only + 0x10000 + 0xFFFFFFFF + + + CFSM + CAN Finite State Machine + 0 + 6 + read-only + + + CBN + CAN Bit Number + 24 + 5 + read-only + + + + + DBG2 + Debug 2 register + 0x5C + 32 + read-only + 0 + 0xFFFFFFFF + + + RMP + Rx Matching Pointer + 0 + 7 + read-only + + + MPP + Matching Process in Progress + 7 + 1 + read-only + + + MPP_0 + No matching process ongoing. + 0 + + + MPP_1 + Matching process is in progress. + 0x1 + + + + + TAP + Tx Arbitration Pointer + 8 + 7 + read-only + + + APP + Arbitration Process in Progress + 15 + 1 + read-only + + + APP_0 + No matching process ongoing. + 0 + + + APP_1 + Matching process is in progress. + 0x1 + + + + + CS0 Message Buffer 0 CS Register @@ -86783,6 +90073,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 6 read-write + oneToSet BUSY @@ -86790,6 +90081,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 8 1 read-only + oneToSet ERROR @@ -86797,6 +90089,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 9 1 read-write + oneToSet RELOAD_SHADOWS @@ -86804,6 +90097,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 10 1 read-write + oneToSet WR_UNLOCK @@ -86811,6 +90105,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 16 16 read-write + oneToSet @@ -86829,6 +90124,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 6 read-write + oneToClear BUSY @@ -86836,6 +90132,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 8 1 read-only + oneToClear ERROR @@ -86843,6 +90140,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 9 1 read-write + oneToClear RELOAD_SHADOWS @@ -86850,6 +90148,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 10 1 read-write + oneToClear WR_UNLOCK @@ -86857,6 +90156,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 16 16 read-write + oneToClear @@ -86875,6 +90175,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 6 read-write + oneToToggle BUSY @@ -86882,6 +90183,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 8 1 read-only + oneToToggle ERROR @@ -86889,6 +90191,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 9 1 read-write + oneToToggle RELOAD_SHADOWS @@ -86896,6 +90199,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 10 1 read-write + oneToToggle WR_UNLOCK @@ -86903,6 +90207,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 16 16 read-write + oneToToggle @@ -87092,6 +90397,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 1 read-write + oneToSet SPARE @@ -87099,6 +90405,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 1 30 read-write + oneToSet LOCK @@ -87106,6 +90413,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 1 read-write + oneToSet @@ -87124,6 +90432,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 1 read-write + oneToClear SPARE @@ -87131,6 +90440,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 1 30 read-write + oneToClear LOCK @@ -87138,6 +90448,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 1 read-write + oneToClear @@ -87156,6 +90467,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 1 read-write + oneToToggle SPARE @@ -87163,6 +90475,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 1 30 read-write + oneToToggle LOCK @@ -87170,6 +90483,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 1 read-write + oneToToggle @@ -87295,13 +90609,6 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2 read-only - - SRK - Status of shadow register and OTP write lock for srk region - 14 - 1 - read-only - OTPMK_MSB Status of shadow register read and write, OTP read and write lock for otpmk region (MSB) @@ -88118,11 +91425,6 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. Select mux mode: ALT5 mux port: GPIO4_IO00 of instance: gpio4 0x5 - - ALT7 - Select mux mode: ALT7 mux port: JTAG_DONE of instance: JTAG - 0x7 - @@ -88192,11 +91494,6 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. Select mux mode: ALT5 mux port: GPIO4_IO01 of instance: gpio4 0x5 - - ALT7 - Select mux mode: ALT7 mux port: JTAG_DE_B of instance: JTAG - 0x7 - @@ -88266,11 +91563,6 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. Select mux mode: ALT5 mux port: GPIO4_IO02 of instance: gpio4 0x5 - - ALT7 - Select mux mode: ALT7 mux port: JTAG_FAIL of instance: JTAG - 0x7 - @@ -88340,11 +91632,6 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. Select mux mode: ALT5 mux port: GPIO4_IO03 of instance: gpio4 0x5 - - ALT7 - Select mux mode: ALT7 mux port: JTAG_ACTIVE of instance: JTAG - 0x7 - @@ -92034,6 +95321,11 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. Select mux mode: ALT6 mux port: ENET_1588_EVENT1_OUT of instance: enet 0x6 + + ALT7 + Select mux mode: ALT7 mux port: NMI_GLUE_NMI of instance: nmi_glue + 0x7 + @@ -93880,6 +97172,11 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. Select mux mode: ALT2 mux port: LPI2C2_SCL of instance: lpi2c2 0x2 + + ALT3 + Select mux mode: ALT3 mux port: ARM_CM7_TRACE00 of instance: cm7_mx6rt + 0x3 + ALT4 Select mux mode: ALT4 mux port: FLEXIO2_FLEXIO04 of instance: flexio2 @@ -93949,6 +97246,11 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. Select mux mode: ALT2 mux port: LPI2C2_SDA of instance: lpi2c2 0x2 + + ALT3 + Select mux mode: ALT3 mux port: ARM_CM7_TRACE01 of instance: cm7_mx6rt + 0x3 + ALT4 Select mux mode: ALT4 mux port: FLEXIO2_FLEXIO05 of instance: flexio2 @@ -94018,6 +97320,11 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. Select mux mode: ALT2 mux port: FLEXPWM2_PWMA00 of instance: flexpwm2 0x2 + + ALT3 + Select mux mode: ALT3 mux port: ARM_CM7_TRACE02 of instance: cm7_mx6rt + 0x3 + ALT4 Select mux mode: ALT4 mux port: FLEXIO2_FLEXIO06 of instance: flexio2 @@ -94087,6 +97394,11 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. Select mux mode: ALT2 mux port: FLEXPWM2_PWMB00 of instance: flexpwm2 0x2 + + ALT3 + Select mux mode: ALT3 mux port: ARM_CM7_TRACE03 of instance: cm7_mx6rt + 0x3 + ALT4 Select mux mode: ALT4 mux port: FLEXIO2_FLEXIO07 of instance: flexio2 @@ -94447,6 +97759,11 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. Select mux mode: ALT1 mux port: XBAR1_INOUT10 of instance: xbar1 0x1 + + ALT2 + Select mux mode: ALT2 mux port: ARM_CM7_TRACE_CLK of instance: cm7_mx6rt + 0x2 + ALT3 Select mux mode: ALT3 mux port: SAI1_TX_DATA01 of instance: sai1 @@ -94516,6 +97833,11 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. Select mux mode: ALT1 mux port: XBAR1_INOUT11 of instance: xbar1 0x1 + + ALT2 + Select mux mode: ALT2 mux port: ARM_CM7_TRACE_SWO of instance: cm7_mx6rt + 0x2 + ALT3 Select mux mode: ALT3 mux port: SAI1_MCLK of instance: sai1 @@ -95049,11 +98371,6 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. Select mux mode: ALT5 mux port: GPIO2_IO20 of instance: gpio2 0x5 - - ALT6 - Select mux mode: ALT6 mux port: CSU_CSU_ALARM_AUT02 of instance: csu - 0x6 - @@ -95123,11 +98440,6 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. Select mux mode: ALT5 mux port: GPIO2_IO21 of instance: gpio2 0x5 - - ALT6 - Select mux mode: ALT6 mux port: CSU_CSU_ALARM_AUT01 of instance: csu - 0x6 - @@ -95197,11 +98509,6 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. Select mux mode: ALT5 mux port: GPIO2_IO22 of instance: gpio2 0x5 - - ALT6 - Select mux mode: ALT6 mux port: CSU_CSU_ALARM_AUT00 of instance: csu - 0x6 - @@ -95271,11 +98578,6 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. Select mux mode: ALT5 mux port: GPIO2_IO23 of instance: gpio2 0x5 - - ALT6 - Select mux mode: ALT6 mux port: CSU_CSU_INT_DEB of instance: csu - 0x6 - @@ -96435,11 +99737,6 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. Select mux mode: ALT5 mux port: GPIO3_IO01 of instance: gpio3 0x5 - - ALT6 - Select mux mode: ALT6 mux port: CCM_DI0_EXT_CLK of instance: ccm - 0x6 - @@ -96869,11 +100166,6 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. Select mux mode: ALT5 mux port: GPIO3_IO07 of instance: gpio3 0x5 - - ALT6 - Select mux mode: ALT6 mux port: CCM_REF_EN_B of instance: ccm - 0x6 - @@ -97086,11 +100378,6 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. Select mux mode: ALT5 mux port: GPIO3_IO10 of instance: gpio3 0x5 - - ALT6 - Select mux mode: ALT6 mux port: SRC_SYSTEM_RESET of instance: src - 0x6 - @@ -97160,11 +100447,6 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. Select mux mode: ALT5 mux port: GPIO3_IO11 of instance: gpio3 0x5 - - ALT6 - Select mux mode: ALT6 mux port: SRC_EARLY_RESET of instance: src - 0x6 - @@ -97229,8 +100511,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -97442,8 +100724,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -97655,8 +100937,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -97868,8 +101150,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -98081,8 +101363,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -98294,8 +101576,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -98507,8 +101789,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -98720,8 +102002,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -98933,8 +102215,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -99146,8 +102428,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -99359,8 +102641,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -99572,8 +102854,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -99785,8 +103067,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -99998,8 +103280,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -100211,8 +103493,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -100424,8 +103706,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -100637,8 +103919,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -100850,8 +104132,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -101063,8 +104345,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -101276,8 +104558,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -101489,8 +104771,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -101702,8 +104984,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -101915,8 +105197,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -102128,8 +105410,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -102341,8 +105623,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -102554,8 +105836,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -102767,8 +106049,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -102980,8 +106262,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -103193,8 +106475,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -103406,8 +106688,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -103619,8 +106901,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -103832,8 +107114,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -104045,8 +107327,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -104258,8 +107540,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -104471,8 +107753,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -104684,8 +107966,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -104897,8 +108179,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -105110,8 +108392,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -105323,8 +108605,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -105536,8 +108818,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -105749,8 +109031,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -105962,8 +109244,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -106175,8 +109457,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -106388,8 +109670,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -106601,8 +109883,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -106814,8 +110096,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -107027,8 +110309,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -107240,8 +110522,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -107453,8 +110735,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -107666,8 +110948,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -107879,8 +111161,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -108092,8 +111374,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -108305,8 +111587,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -108518,8 +111800,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -108731,8 +112013,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -108944,8 +112226,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -109157,8 +112439,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -109370,8 +112652,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -109583,8 +112865,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -109796,8 +113078,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -110009,8 +113291,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -110222,8 +113504,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -110435,8 +113717,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -110648,8 +113930,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -110861,8 +114143,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -111074,8 +114356,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -111287,8 +114569,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -111500,8 +114782,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -111713,8 +114995,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -111926,8 +115208,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -112139,8 +115421,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -112352,8 +115634,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -112565,8 +115847,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -112778,8 +116060,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -112991,8 +116273,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -113204,8 +116486,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -113417,8 +116699,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -113630,8 +116912,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -113843,8 +117125,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -114056,8 +117338,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -114269,8 +117551,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -114482,8 +117764,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -114695,8 +117977,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -114908,8 +118190,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -115121,8 +118403,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -115334,8 +118616,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -115547,8 +118829,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -115760,8 +119042,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -115973,8 +119255,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -116186,8 +119468,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -116399,8 +119681,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -116612,8 +119894,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -116825,8 +120107,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -117038,8 +120320,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -117251,8 +120533,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -117464,8 +120746,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -117677,8 +120959,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -117890,8 +121172,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -118103,8 +121385,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -118316,8 +121598,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -118529,8 +121811,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -118742,8 +122024,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -118955,8 +122237,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -119168,8 +122450,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -119381,8 +122663,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -119594,8 +122876,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -119807,8 +123089,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -120020,8 +123302,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -120233,8 +123515,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -120446,8 +123728,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -120659,8 +123941,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -120872,8 +124154,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -121085,8 +124367,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -121298,8 +124580,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -121511,8 +124793,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -121724,8 +125006,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -121937,8 +125219,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -122150,8 +125432,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -122363,8 +125645,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -122576,8 +125858,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -122789,8 +126071,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -123002,8 +126284,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -123215,8 +126497,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -123428,8 +126710,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -126557,12 +129839,12 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. read-write - SELECT_GPIO_AD_B0_12_ALT7 + GPIO_AD_B0_12_ALT7 Selecting Pad: GPIO_AD_B0_12 for Mode: ALT7 0 - SELECT_WAKEUP_ALT7 + WAKEUP_ALT7 Selecting Pad: WAKEUP for Mode: ALT7 0x1 @@ -129339,10 +132621,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - 4 - 0x4 - 0,1,2,3 - AHBRXBUFCR0%s + AHBRXBUF0CR0 AHB RX Buffer 0 Control Register 0 0x20 32 @@ -129371,13 +132650,134 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2 read-write + + PREFETCHEN + AHB Read Prefetch Enable for current AHB RX Buffer corresponding Master. + 31 + 1 + read-write + - 4 - 0x4 - A1,A2,B1,B2 - FLSHCR0%s + AHBRXBUF1CR0 + AHB RX Buffer 1 Control Register 0 + 0x24 + 32 + read-write + 0x80010020 + 0xFFFFFFFF + + + BUFSZ + AHB RX Buffer Size in 64 bits.Refer AHB RX Buffer Management for more details. + 0 + 8 + read-write + + + MSTRID + This AHB RX Buffer is assigned according to AHB Master with ID (MSTR_ID). Please refer to for AHB RX Buffer allocation. + 16 + 4 + read-write + + + PRIORITY + This priority for AHB Master Read which this AHB RX Buffer is assigned. Refer for more details. + 24 + 2 + read-write + + + PREFETCHEN + AHB Read Prefetch Enable for current AHB RX Buffer corresponding Master. + 31 + 1 + read-write + + + + + AHBRXBUF2CR0 + AHB RX Buffer 2 Control Register 0 + 0x28 + 32 + read-write + 0x80020020 + 0xFFFFFFFF + + + BUFSZ + AHB RX Buffer Size in 64 bits.Refer AHB RX Buffer Management for more details. + 0 + 8 + read-write + + + MSTRID + This AHB RX Buffer is assigned according to AHB Master with ID (MSTR_ID). Please refer to for AHB RX Buffer allocation. + 16 + 4 + read-write + + + PRIORITY + This priority for AHB Master Read which this AHB RX Buffer is assigned. Refer for more details. + 24 + 2 + read-write + + + PREFETCHEN + AHB Read Prefetch Enable for current AHB RX Buffer corresponding Master. + 31 + 1 + read-write + + + + + AHBRXBUF3CR0 + AHB RX Buffer 3 Control Register 0 + 0x2C + 32 + read-write + 0x80030020 + 0xFFFFFFFF + + + BUFSZ + AHB RX Buffer Size in 64 bits.Refer AHB RX Buffer Management for more details. + 0 + 8 + read-write + + + MSTRID + This AHB RX Buffer is assigned according to AHB Master with ID (MSTR_ID). Please refer to for AHB RX Buffer allocation. + 16 + 4 + read-write + + + PRIORITY + This priority for AHB Master Read which this AHB RX Buffer is assigned. Refer for more details. + 24 + 2 + read-write + + + PREFETCHEN + AHB Read Prefetch Enable for current AHB RX Buffer corresponding Master. + 31 + 1 + read-write + + + + + FLSHA1CR0 Flash A1 Control Register 0 0x60 32 @@ -129394,6 +132794,60 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + + FLSHA2CR0 + Flash A2 Control Register 0 + 0x64 + 32 + read-write + 0x10000 + 0xFFFFFFFF + + + FLSHSZ + Flash Size in KByte. + 0 + 23 + read-write + + + + + FLSHB1CR0 + Flash B1 Control Register 0 + 0x68 + 32 + read-write + 0x10000 + 0xFFFFFFFF + + + FLSHSZ + Flash Size in KByte. + 0 + 23 + read-write + + + + + FLSHB2CR0 + Flash B2 Control Register 0 + 0x6C + 32 + read-write + 0x10000 + 0xFFFFFFFF + + + FLSHSZ + Flash Size in KByte. + 0 + 23 + read-write + + + 4 0x4 @@ -131369,7 +134823,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0x2C 32 read-write - 0x8080800F + 0x80800F 0xFFFFFFFF @@ -133596,7 +137050,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0x60 32 read-write - 0x200 + 0 0xFFFFFFFF @@ -133677,7 +137131,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0x64 32 read-only - 0 + 0x200 0xFFFFFFFF @@ -134143,8 +137597,15 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - AHB_RST - AHB BUS reset + PART_DLL_DEBUG + debug for part dll + 13 + 1 + read-write + + + BUS_RST + BUS reset 14 1 read-write @@ -138813,7 +142274,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0x164 32 read-write - 0xA0000 + 0 0xFFFFFFFF @@ -140692,7 +144153,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. MDIS_1 - Master disabled. + Module disabled. 0x1 @@ -142193,7 +145654,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0x24 32 read-write - 0x9000001E + 0x90000018 0xFFFFFFFF @@ -142387,7 +145848,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0x28 32 read-write - 0x9800001C + 0x98000018 0xFFFFFFFF @@ -143006,7 +146467,6 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 4 1 read-write - oneToClear NDPAGEENDEN_0 @@ -143026,7 +146486,6 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 5 1 read-write - oneToClear NDNOPENDEN_0 @@ -144829,14 +148288,14 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. REL - RDX Low Time + RDX Low Time bit [3:0] 16 4 read-write REH - RDX High Time + RDX High Time bit [3:0] 20 4 read-write @@ -144848,6 +148307,20 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 4 read-write + + REL2 + RDX Low Time bit [5:4] + 28 + 2 + read-write + + + REH2 + RDX High Time bit [5:4] + 30 + 2 + read-write + @@ -150013,12 +153486,12 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. RST_0 - Master logic is not reset + Module is not reset 0 RST_1 - Master logic is reset + Module is reset 0x1 @@ -151431,9 +154904,16 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 8 read-write + + DMA_MODE_SEL + 1'b0: Trig DMA_REQ with latched signal, REQ will be cleared when ACK and source request cleared + 29 + 1 + read-write + TSC_BYPASS - 1'b1: TSC is bypassed; 1'b0: TSC not bypassed; + 1'b1: TSC is bypassed to ADC2. 1'b0: TSC not bypassed. To use ADC2, this bit should be cleared. 30 1 read-write @@ -151905,7 +155385,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. HWTS0 - CHAIN0 HWTS ADC hardware trigger selection + CHAIN0 HWTS ADC hardware trigger selection. For more information, see the ADC chapter. 4 8 read-write @@ -151933,7 +155413,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. HWTS1 - CHAIN1 HWTS ADC hardware trigger selection + CHAIN1 HWTS ADC hardware trigger selection. For more information, see the ADC chapter. 20 8 read-write @@ -170021,7 +173501,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. AC_PROT_EN - Enable access permission control + Enable access permission control When AC_PROT_EN is asserted, all encrypted regions are limited to be ARM core access only 6 1 read-write @@ -170208,7 +173688,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ADDR_OFFSET0 - Address offset used to remap received address to output address of memory region0 + Signed offset for BEE region 0 0 16 read-write @@ -170232,14 +173712,14 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0xFFFFFFFF - ADDR_OFFSET0 - Address offset used to remap received address to output address of memory region1 + ADDR_OFFSET1 + Signed offset for BEE region 1 0 16 read-write - ADDR_OFFSET0_LOCK + ADDR_OFFSET1_LOCK Lock bits for addr_offset1 16 16 @@ -170330,7 +173810,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. IRQ_VEC - bit 7: Protected region-3 access violation bit 6: Protected region-2 access violation bit 5: Protected region-1 access violation bit 4: Protected region-0 access violation bit 3: Region-1 read channel security violation bit 2: Read channel illegal access detected bit 1: Region-0 Read channel security violation bit 0: Disable abort + bit 7: Protected region-3 access violation bit 6: Protected region-2 access violation bit 5: Protected region-1 access violation bit 4: Protected region-0 access violation bit 3: Region-1 read channel security violation bit 2: Read channel illegal access detected bit 1: Region-0 read channel security violation bit 0: Disable abort 0 8 read-write @@ -170338,7 +173818,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. BEE_IDLE - Lock bits for addr_offset1 + 1'b1: BEE is idle; 1'b0: BEE is active 8 1 read-only @@ -177793,19 +181273,19 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 60 - ANATOP_EVENT0 + PMU_EVENT 61 - ANATOP_EVENT1 + Reserved78 62 - ANATOP_TAMP_LOW_HIGH + TEMP_LOW_HIGH 63 - ANATOP_TEMP_PANIC + TEMP_PANIC 64 @@ -178152,38 +181632,6 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. PWM4_FAULT 151 - - Reserved168 - 152 - - - Reserved169 - 153 - - - Reserved170 - 154 - - - Reserved171 - 155 - - - Reserved172 - 156 - - - Reserved173 - 157 - - - SJC_ARM_DEBUG - 158 - - - NMI_WAKEUP - 159 - NVICISER0 @@ -179764,7 +183212,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. PRI61 - Priority of the INT_ANATOP_EVENT0 interrupt 61 + Priority of the INT_PMU_EVENT interrupt 61 4 4 read-write @@ -179782,7 +183230,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. PRI62 - Priority of the INT_ANATOP_EVENT1 interrupt 62 + Priority of the INT_Reserved78 interrupt 62 4 4 read-write @@ -179800,7 +183248,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. PRI63 - Priority of the INT_ANATOP_TAMP_LOW_HIGH interrupt 63 + Priority of the INT_TEMP_LOW_HIGH interrupt 63 4 4 read-write @@ -179818,7 +183266,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. PRI64 - Priority of the INT_ANATOP_TEMP_PANIC interrupt 64 + Priority of the INT_TEMP_PANIC interrupt 64 4 4 read-write @@ -181391,150 +184839,6 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - - NVICIP152 - Interrupt Priority Register 152 - 0x398 - 8 - read-write - 0 - 0xFF - - - PRI152 - Priority of the INT_Reserved168 interrupt 152 - 4 - 4 - read-write - - - - - NVICIP153 - Interrupt Priority Register 153 - 0x399 - 8 - read-write - 0 - 0xFF - - - PRI153 - Priority of the INT_Reserved169 interrupt 153 - 4 - 4 - read-write - - - - - NVICIP154 - Interrupt Priority Register 154 - 0x39A - 8 - read-write - 0 - 0xFF - - - PRI154 - Priority of the INT_Reserved170 interrupt 154 - 4 - 4 - read-write - - - - - NVICIP155 - Interrupt Priority Register 155 - 0x39B - 8 - read-write - 0 - 0xFF - - - PRI155 - Priority of the INT_Reserved171 interrupt 155 - 4 - 4 - read-write - - - - - NVICIP156 - Interrupt Priority Register 156 - 0x39C - 8 - read-write - 0 - 0xFF - - - PRI156 - Priority of the INT_Reserved172 interrupt 156 - 4 - 4 - read-write - - - - - NVICIP157 - Interrupt Priority Register 157 - 0x39D - 8 - read-write - 0 - 0xFF - - - PRI157 - Priority of the INT_Reserved173 interrupt 157 - 4 - 4 - read-write - - - - - NVICIP158 - Interrupt Priority Register 158 - 0x39E - 8 - read-write - 0 - 0xFF - - - PRI158 - Priority of the INT_SJC_ARM_DEBUG interrupt 158 - 4 - 4 - read-write - - - - - NVICIP159 - Interrupt Priority Register 159 - 0x39F - 8 - read-write - 0 - 0xFF - - - PRI159 - Priority of the INT_NMI_WAKEUP interrupt 159 - 4 - 4 - read-write - - - NVICSTIR Software Trigger Interrupt Register diff --git a/ext/hal/nxp/mcux/devices/MIMXRT1051/MIMXRT1051_features.h b/ext/hal/nxp/mcux/devices/MIMXRT1051/MIMXRT1051_features.h index 2c796d606c3..6029beffc98 100644 --- a/ext/hal/nxp/mcux/devices/MIMXRT1051/MIMXRT1051_features.h +++ b/ext/hal/nxp/mcux/devices/MIMXRT1051/MIMXRT1051_features.h @@ -1,37 +1,16 @@ /* ** ################################################################### -** Version: rev. 0.1, 2017-01-10 -** Build: b171017 +** Version: rev. 1.1, 2018-11-16 +** Build: b181120 ** ** Abstract: ** Chip specific module features. ** ** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2017 NXP -** Redistribution and use in source and binary forms, with or without modification, -** are permitted provided that the following conditions are met: +** Copyright 2016-2018 NXP +** All rights reserved. ** -** 1. Redistributions of source code must retain the above copyright notice, this list -** of conditions and the following disclaimer. -** -** 2. Redistributions in binary form must reproduce the above copyright notice, this -** list of conditions and the following disclaimer in the documentation and/or -** other materials provided with the distribution. -** -** 3. Neither the name of the copyright holder nor the names of its -** contributors may be used to endorse or promote products derived from this -** software without specific prior written permission. -** -** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** SPDX-License-Identifier: BSD-3-Clause ** ** http: www.nxp.com ** mail: support@nxp.com @@ -39,6 +18,12 @@ ** Revisions: ** - rev. 0.1 (2017-01-10) ** Initial version. +** - rev. 1.0 (2018-09-21) +** Update interrupt vector table and dma request source. +** Update register BEE_ADDR_OFFSET1's bitfield name to ADDR_OFFSET1. +** Split GPIO_COMBINED_IRQS to GPIO_COMBINED_LOW_IRQS and GPIO_COMBINED_HIGH_IRQS. +** - rev. 1.1 (2018-11-16) +** Update feature files to align with IMXRT1050RM Rev.1. ** ** ################################################################### */ @@ -48,532 +33,104 @@ /* SOC module features */ -/* @brief ACMP availability on the SoC. */ -#define FSL_FEATURE_SOC_ACMP_COUNT (0) /* @brief ADC availability on the SoC. */ #define FSL_FEATURE_SOC_ADC_COUNT (2) -/* @brief ADC12 availability on the SoC. */ -#define FSL_FEATURE_SOC_ADC12_COUNT (0) -/* @brief ADC16 availability on the SoC. */ -#define FSL_FEATURE_SOC_ADC16_COUNT (0) -/* @brief ADC_5HC availability on the SoC. */ -#define FSL_FEATURE_SOC_ADC_5HC_COUNT (0) -/* @brief AES availability on the SoC. */ -#define FSL_FEATURE_SOC_AES_COUNT (0) -/* @brief AFE availability on the SoC. */ -#define FSL_FEATURE_SOC_AFE_COUNT (0) -/* @brief AGC availability on the SoC. */ -#define FSL_FEATURE_SOC_AGC_COUNT (0) -/* @brief AIPS availability on the SoC. */ -#define FSL_FEATURE_SOC_AIPS_COUNT (0) /* @brief AIPSTZ availability on the SoC. */ #define FSL_FEATURE_SOC_AIPSTZ_COUNT (4) -/* @brief ANATOP availability on the SoC. */ -#define FSL_FEATURE_SOC_ANATOP_COUNT (0) /* @brief AOI availability on the SoC. */ #define FSL_FEATURE_SOC_AOI_COUNT (2) -/* @brief APBH availability on the SoC. */ -#define FSL_FEATURE_SOC_APBH_COUNT (0) -/* @brief ASMC availability on the SoC. */ -#define FSL_FEATURE_SOC_ASMC_COUNT (0) -/* @brief ASRC availability on the SoC. */ -#define FSL_FEATURE_SOC_ASRC_COUNT (0) -/* @brief ASYNC_SYSCON availability on the SoC. */ -#define FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT (0) -/* @brief ATX availability on the SoC. */ -#define FSL_FEATURE_SOC_ATX_COUNT (0) -/* @brief AXBS availability on the SoC. */ -#define FSL_FEATURE_SOC_AXBS_COUNT (0) -/* @brief BCH availability on the SoC. */ -#define FSL_FEATURE_SOC_BCH_COUNT (0) -/* @brief BLEDP availability on the SoC. */ -#define FSL_FEATURE_SOC_BLEDP_COUNT (0) -/* @brief BOD availability on the SoC. */ -#define FSL_FEATURE_SOC_BOD_COUNT (0) -/* @brief CAAM availability on the SoC. */ -#define FSL_FEATURE_SOC_CAAM_COUNT (0) -/* @brief CADC availability on the SoC. */ -#define FSL_FEATURE_SOC_CADC_COUNT (0) -/* @brief CALIB availability on the SoC. */ -#define FSL_FEATURE_SOC_CALIB_COUNT (0) -/* @brief CAN availability on the SoC. */ -#define FSL_FEATURE_SOC_CAN_COUNT (0) -/* @brief CAU availability on the SoC. */ -#define FSL_FEATURE_SOC_CAU_COUNT (0) -/* @brief CAU3 availability on the SoC. */ -#define FSL_FEATURE_SOC_CAU3_COUNT (0) /* @brief CCM availability on the SoC. */ #define FSL_FEATURE_SOC_CCM_COUNT (1) /* @brief CCM_ANALOG availability on the SoC. */ #define FSL_FEATURE_SOC_CCM_ANALOG_COUNT (1) -/* @brief CHRG availability on the SoC. */ -#define FSL_FEATURE_SOC_CHRG_COUNT (0) -/* @brief CLKCTL0 availability on the SoC. */ -#define FSL_FEATURE_SOC_CLKCTL0_COUNT (0) -/* @brief CLKCTL1 availability on the SoC. */ -#define FSL_FEATURE_SOC_CLKCTL1_COUNT (0) /* @brief CMP availability on the SoC. */ #define FSL_FEATURE_SOC_CMP_COUNT (4) -/* @brief CMT availability on the SoC. */ -#define FSL_FEATURE_SOC_CMT_COUNT (0) -/* @brief CNC availability on the SoC. */ -#define FSL_FEATURE_SOC_CNC_COUNT (0) -/* @brief COP availability on the SoC. */ -#define FSL_FEATURE_SOC_COP_COUNT (0) -/* @brief CRC availability on the SoC. */ -#define FSL_FEATURE_SOC_CRC_COUNT (0) -/* @brief CS availability on the SoC. */ -#define FSL_FEATURE_SOC_CS_COUNT (0) -/* @brief CSI availability on the SoC. */ -#define FSL_FEATURE_SOC_CSI_COUNT (0) -/* @brief CT32B availability on the SoC. */ -#define FSL_FEATURE_SOC_CT32B_COUNT (0) -/* @brief CTI availability on the SoC. */ -#define FSL_FEATURE_SOC_CTI_COUNT (0) -/* @brief CTIMER availability on the SoC. */ -#define FSL_FEATURE_SOC_CTIMER_COUNT (0) -/* @brief DAC availability on the SoC. */ -#define FSL_FEATURE_SOC_DAC_COUNT (0) -/* @brief DAC32 availability on the SoC. */ -#define FSL_FEATURE_SOC_DAC32_COUNT (0) /* @brief DCDC availability on the SoC. */ #define FSL_FEATURE_SOC_DCDC_COUNT (1) /* @brief DCP availability on the SoC. */ #define FSL_FEATURE_SOC_DCP_COUNT (1) -/* @brief DDR availability on the SoC. */ -#define FSL_FEATURE_SOC_DDR_COUNT (0) -/* @brief DDRC availability on the SoC. */ -#define FSL_FEATURE_SOC_DDRC_COUNT (0) -/* @brief DDRC_MP availability on the SoC. */ -#define FSL_FEATURE_SOC_DDRC_MP_COUNT (0) -/* @brief DDR_PHY availability on the SoC. */ -#define FSL_FEATURE_SOC_DDR_PHY_COUNT (0) -/* @brief DMA availability on the SoC. */ -#define FSL_FEATURE_SOC_DMA_COUNT (0) /* @brief DMAMUX availability on the SoC. */ #define FSL_FEATURE_SOC_DMAMUX_COUNT (1) -/* @brief DMIC availability on the SoC. */ -#define FSL_FEATURE_SOC_DMIC_COUNT (0) -/* @brief DRY availability on the SoC. */ -#define FSL_FEATURE_SOC_DRY_COUNT (0) -/* @brief DSPI availability on the SoC. */ -#define FSL_FEATURE_SOC_DSPI_COUNT (0) -/* @brief ECSPI availability on the SoC. */ -#define FSL_FEATURE_SOC_ECSPI_COUNT (0) /* @brief EDMA availability on the SoC. */ #define FSL_FEATURE_SOC_EDMA_COUNT (1) -/* @brief EEPROM availability on the SoC. */ -#define FSL_FEATURE_SOC_EEPROM_COUNT (0) -/* @brief EIM availability on the SoC. */ -#define FSL_FEATURE_SOC_EIM_COUNT (0) -/* @brief EMC availability on the SoC. */ -#define FSL_FEATURE_SOC_EMC_COUNT (0) -/* @brief EMVSIM availability on the SoC. */ -#define FSL_FEATURE_SOC_EMVSIM_COUNT (0) /* @brief ENC availability on the SoC. */ #define FSL_FEATURE_SOC_ENC_COUNT (4) /* @brief ENET availability on the SoC. */ #define FSL_FEATURE_SOC_ENET_COUNT (1) -/* @brief EPDC availability on the SoC. */ -#define FSL_FEATURE_SOC_EPDC_COUNT (0) -/* @brief EPIT availability on the SoC. */ -#define FSL_FEATURE_SOC_EPIT_COUNT (0) -/* @brief ESAI availability on the SoC. */ -#define FSL_FEATURE_SOC_ESAI_COUNT (0) /* @brief EWM availability on the SoC. */ #define FSL_FEATURE_SOC_EWM_COUNT (1) -/* @brief FB availability on the SoC. */ -#define FSL_FEATURE_SOC_FB_COUNT (0) -/* @brief FGPIO availability on the SoC. */ -#define FSL_FEATURE_SOC_FGPIO_COUNT (0) -/* @brief FLASH availability on the SoC. */ -#define FSL_FEATURE_SOC_FLASH_COUNT (0) /* @brief FLEXCAN availability on the SoC. */ #define FSL_FEATURE_SOC_FLEXCAN_COUNT (2) -/* @brief FLEXCOMM availability on the SoC. */ -#define FSL_FEATURE_SOC_FLEXCOMM_COUNT (0) /* @brief FLEXIO availability on the SoC. */ #define FSL_FEATURE_SOC_FLEXIO_COUNT (2) /* @brief FLEXRAM availability on the SoC. */ #define FSL_FEATURE_SOC_FLEXRAM_COUNT (1) /* @brief FLEXSPI availability on the SoC. */ #define FSL_FEATURE_SOC_FLEXSPI_COUNT (1) -/* @brief FMC availability on the SoC. */ -#define FSL_FEATURE_SOC_FMC_COUNT (0) -/* @brief FREQME availability on the SoC. */ -#define FSL_FEATURE_SOC_FREQME_COUNT (0) -/* @brief FSKDT availability on the SoC. */ -#define FSL_FEATURE_SOC_FSKDT_COUNT (0) -/* @brief FSP availability on the SoC. */ -#define FSL_FEATURE_SOC_FSP_COUNT (0) -/* @brief FTFA availability on the SoC. */ -#define FSL_FEATURE_SOC_FTFA_COUNT (0) -/* @brief FTFE availability on the SoC. */ -#define FSL_FEATURE_SOC_FTFE_COUNT (0) -/* @brief FTFL availability on the SoC. */ -#define FSL_FEATURE_SOC_FTFL_COUNT (0) -/* @brief FTM availability on the SoC. */ -#define FSL_FEATURE_SOC_FTM_COUNT (0) -/* @brief FTMRA availability on the SoC. */ -#define FSL_FEATURE_SOC_FTMRA_COUNT (0) -/* @brief FTMRE availability on the SoC. */ -#define FSL_FEATURE_SOC_FTMRE_COUNT (0) -/* @brief FTMRH availability on the SoC. */ -#define FSL_FEATURE_SOC_FTMRH_COUNT (0) -/* @brief GINT availability on the SoC. */ -#define FSL_FEATURE_SOC_GINT_COUNT (0) /* @brief GPC availability on the SoC. */ #define FSL_FEATURE_SOC_GPC_COUNT (1) -/* @brief GPC_PGC availability on the SoC. */ -#define FSL_FEATURE_SOC_GPC_PGC_COUNT (0) -/* @brief GPIO availability on the SoC. */ -#define FSL_FEATURE_SOC_GPIO_COUNT (0) -/* @brief GPMI availability on the SoC. */ -#define FSL_FEATURE_SOC_GPMI_COUNT (0) /* @brief GPT availability on the SoC. */ #define FSL_FEATURE_SOC_GPT_COUNT (2) -/* @brief HASH availability on the SoC. */ -#define FSL_FEATURE_SOC_HASH_COUNT (0) -/* @brief HSADC availability on the SoC. */ -#define FSL_FEATURE_SOC_HSADC_COUNT (0) -/* @brief I2C availability on the SoC. */ -#define FSL_FEATURE_SOC_I2C_COUNT (0) /* @brief I2S availability on the SoC. */ #define FSL_FEATURE_SOC_I2S_COUNT (3) -/* @brief ICS availability on the SoC. */ -#define FSL_FEATURE_SOC_ICS_COUNT (0) -/* @brief IEE availability on the SoC. */ -#define FSL_FEATURE_SOC_IEE_COUNT (0) -/* @brief IEER availability on the SoC. */ -#define FSL_FEATURE_SOC_IEER_COUNT (0) /* @brief IGPIO availability on the SoC. */ #define FSL_FEATURE_SOC_IGPIO_COUNT (5) -/* @brief II2C availability on the SoC. */ -#define FSL_FEATURE_SOC_II2C_COUNT (0) -/* @brief INPUTMUX availability on the SoC. */ -#define FSL_FEATURE_SOC_INPUTMUX_COUNT (0) -/* @brief INTMUX availability on the SoC. */ -#define FSL_FEATURE_SOC_INTMUX_COUNT (0) -/* @brief IOCON availability on the SoC. */ -#define FSL_FEATURE_SOC_IOCON_COUNT (0) /* @brief IOMUXC availability on the SoC. */ #define FSL_FEATURE_SOC_IOMUXC_COUNT (1) /* @brief IOMUXC_GPR availability on the SoC. */ #define FSL_FEATURE_SOC_IOMUXC_GPR_COUNT (1) -/* @brief IOMUXC_LPSR availability on the SoC. */ -#define FSL_FEATURE_SOC_IOMUXC_LPSR_COUNT (0) -/* @brief IOMUXC_LPSR_GPR availability on the SoC. */ -#define FSL_FEATURE_SOC_IOMUXC_LPSR_GPR_COUNT (0) /* @brief IOMUXC_SNVS availability on the SoC. */ #define FSL_FEATURE_SOC_IOMUXC_SNVS_COUNT (1) -/* @brief IOPCTL availability on the SoC. */ -#define FSL_FEATURE_SOC_IOPCTL_COUNT (0) -/* @brief IPWM availability on the SoC. */ -#define FSL_FEATURE_SOC_IPWM_COUNT (0) -/* @brief IRQ availability on the SoC. */ -#define FSL_FEATURE_SOC_IRQ_COUNT (0) -/* @brief IUART availability on the SoC. */ -#define FSL_FEATURE_SOC_IUART_COUNT (0) -/* @brief KBI availability on the SoC. */ -#define FSL_FEATURE_SOC_KBI_COUNT (0) /* @brief KPP availability on the SoC. */ #define FSL_FEATURE_SOC_KPP_COUNT (1) -/* @brief L2CACHEC availability on the SoC. */ -#define FSL_FEATURE_SOC_L2CACHEC_COUNT (0) -/* @brief LCD availability on the SoC. */ -#define FSL_FEATURE_SOC_LCD_COUNT (0) -/* @brief LCDC availability on the SoC. */ -#define FSL_FEATURE_SOC_LCDC_COUNT (0) -/* @brief LCDIF availability on the SoC. */ -#define FSL_FEATURE_SOC_LCDIF_COUNT (0) -/* @brief LDO availability on the SoC. */ -#define FSL_FEATURE_SOC_LDO_COUNT (0) -/* @brief LLWU availability on the SoC. */ -#define FSL_FEATURE_SOC_LLWU_COUNT (0) -/* @brief LMEM availability on the SoC. */ -#define FSL_FEATURE_SOC_LMEM_COUNT (0) -/* @brief LPADC availability on the SoC. */ -#define FSL_FEATURE_SOC_LPADC_COUNT (0) -/* @brief LPCMP availability on the SoC. */ -#define FSL_FEATURE_SOC_LPCMP_COUNT (0) -/* @brief LPDAC availability on the SoC. */ -#define FSL_FEATURE_SOC_LPDAC_COUNT (0) /* @brief LPI2C availability on the SoC. */ #define FSL_FEATURE_SOC_LPI2C_COUNT (4) -/* @brief LPIT availability on the SoC. */ -#define FSL_FEATURE_SOC_LPIT_COUNT (0) -/* @brief LPSCI availability on the SoC. */ -#define FSL_FEATURE_SOC_LPSCI_COUNT (0) /* @brief LPSPI availability on the SoC. */ #define FSL_FEATURE_SOC_LPSPI_COUNT (4) -/* @brief LPTMR availability on the SoC. */ -#define FSL_FEATURE_SOC_LPTMR_COUNT (0) -/* @brief LPTPM availability on the SoC. */ -#define FSL_FEATURE_SOC_LPTPM_COUNT (0) /* @brief LPUART availability on the SoC. */ #define FSL_FEATURE_SOC_LPUART_COUNT (8) -/* @brief LTC availability on the SoC. */ -#define FSL_FEATURE_SOC_LTC_COUNT (0) -/* @brief MAILBOX availability on the SoC. */ -#define FSL_FEATURE_SOC_MAILBOX_COUNT (0) -/* @brief MC availability on the SoC. */ -#define FSL_FEATURE_SOC_MC_COUNT (0) -/* @brief MCG availability on the SoC. */ -#define FSL_FEATURE_SOC_MCG_COUNT (0) -/* @brief MCGLITE availability on the SoC. */ -#define FSL_FEATURE_SOC_MCGLITE_COUNT (0) -/* @brief MCM availability on the SoC. */ -#define FSL_FEATURE_SOC_MCM_COUNT (0) -/* @brief MIPI_CSI2 availability on the SoC. */ -#define FSL_FEATURE_SOC_MIPI_CSI2_COUNT (0) -/* @brief MIPI_CSI2RX availability on the SoC. */ -#define FSL_FEATURE_SOC_MIPI_CSI2RX_COUNT (0) -/* @brief MIPI_DSI availability on the SoC. */ -#define FSL_FEATURE_SOC_MIPI_DSI_COUNT (0) -/* @brief MIPI_DSI_HOST availability on the SoC. */ -#define FSL_FEATURE_SOC_MIPI_DSI_HOST_COUNT (0) -/* @brief MMAU availability on the SoC. */ -#define FSL_FEATURE_SOC_MMAU_COUNT (0) -/* @brief MMCAU availability on the SoC. */ -#define FSL_FEATURE_SOC_MMCAU_COUNT (0) -/* @brief MMDC availability on the SoC. */ -#define FSL_FEATURE_SOC_MMDC_COUNT (0) -/* @brief MMDVSQ availability on the SoC. */ -#define FSL_FEATURE_SOC_MMDVSQ_COUNT (0) -/* @brief MPU availability on the SoC. */ -#define FSL_FEATURE_SOC_MPU_COUNT (0) -/* @brief MRT availability on the SoC. */ -#define FSL_FEATURE_SOC_MRT_COUNT (0) -/* @brief MSCAN availability on the SoC. */ -#define FSL_FEATURE_SOC_MSCAN_COUNT (0) -/* @brief MSCM availability on the SoC. */ -#define FSL_FEATURE_SOC_MSCM_COUNT (0) -/* @brief MTB availability on the SoC. */ -#define FSL_FEATURE_SOC_MTB_COUNT (0) -/* @brief MTBDWT availability on the SoC. */ -#define FSL_FEATURE_SOC_MTBDWT_COUNT (0) -/* @brief MU availability on the SoC. */ -#define FSL_FEATURE_SOC_MU_COUNT (0) -/* @brief NFC availability on the SoC. */ -#define FSL_FEATURE_SOC_NFC_COUNT (0) /* @brief OCOTP availability on the SoC. */ #define FSL_FEATURE_SOC_OCOTP_COUNT (1) -/* @brief OPAMP availability on the SoC. */ -#define FSL_FEATURE_SOC_OPAMP_COUNT (0) -/* @brief OTPC availability on the SoC. */ -#define FSL_FEATURE_SOC_OTPC_COUNT (0) -/* @brief OSC availability on the SoC. */ -#define FSL_FEATURE_SOC_OSC_COUNT (0) -/* @brief OSC32 availability on the SoC. */ -#define FSL_FEATURE_SOC_OSC32_COUNT (0) -/* @brief OTFAD availability on the SoC. */ -#define FSL_FEATURE_SOC_OTFAD_COUNT (0) -/* @brief PCC availability on the SoC. */ -#define FSL_FEATURE_SOC_PCC_COUNT (0) -/* @brief PCIE_PHY_CMN availability on the SoC. */ -#define FSL_FEATURE_SOC_PCIE_PHY_CMN_COUNT (0) -/* @brief PCIE_PHY_TRSV availability on the SoC. */ -#define FSL_FEATURE_SOC_PCIE_PHY_TRSV_COUNT (0) -/* @brief PDB availability on the SoC. */ -#define FSL_FEATURE_SOC_PDB_COUNT (0) -/* @brief PGA availability on the SoC. */ -#define FSL_FEATURE_SOC_PGA_COUNT (0) -/* @brief PIMCTL availability on the SoC. */ -#define FSL_FEATURE_SOC_PIMCTL_COUNT (0) -/* @brief PINT availability on the SoC. */ -#define FSL_FEATURE_SOC_PINT_COUNT (0) /* @brief PIT availability on the SoC. */ #define FSL_FEATURE_SOC_PIT_COUNT (1) -/* @brief PMC availability on the SoC. */ -#define FSL_FEATURE_SOC_PMC_COUNT (0) /* @brief PMU availability on the SoC. */ #define FSL_FEATURE_SOC_PMU_COUNT (1) -/* @brief POWERQUAD availability on the SoC. */ -#define FSL_FEATURE_SOC_POWERQUAD_COUNT (0) -/* @brief PORT availability on the SoC. */ -#define FSL_FEATURE_SOC_PORT_COUNT (0) -/* @brief PROP availability on the SoC. */ -#define FSL_FEATURE_SOC_PROP_COUNT (0) /* @brief PWM availability on the SoC. */ #define FSL_FEATURE_SOC_PWM_COUNT (4) -/* @brief PWT availability on the SoC. */ -#define FSL_FEATURE_SOC_PWT_COUNT (0) -/* @brief PXP availability on the SoC. */ -#define FSL_FEATURE_SOC_PXP_COUNT (0) -/* @brief QDDKEY availability on the SoC. */ -#define FSL_FEATURE_SOC_QDDKEY_COUNT (0) -/* @brief QDEC availability on the SoC. */ -#define FSL_FEATURE_SOC_QDEC_COUNT (0) -/* @brief QuadSPI availability on the SoC. */ -#define FSL_FEATURE_SOC_QuadSPI_COUNT (0) -/* @brief RCM availability on the SoC. */ -#define FSL_FEATURE_SOC_RCM_COUNT (0) -/* @brief RDC availability on the SoC. */ -#define FSL_FEATURE_SOC_RDC_COUNT (0) -/* @brief RDC_SEMAPHORE availability on the SoC. */ -#define FSL_FEATURE_SOC_RDC_SEMAPHORE_COUNT (0) -/* @brief RFSYS availability on the SoC. */ -#define FSL_FEATURE_SOC_RFSYS_COUNT (0) -/* @brief RFVBAT availability on the SoC. */ -#define FSL_FEATURE_SOC_RFVBAT_COUNT (0) -/* @brief RIT availability on the SoC. */ -#define FSL_FEATURE_SOC_RIT_COUNT (0) -/* @brief RNG availability on the SoC. */ -#define FSL_FEATURE_SOC_RNG_COUNT (0) -/* @brief RNGB availability on the SoC. */ -#define FSL_FEATURE_SOC_RNGB_COUNT (0) -/* @brief ROM availability on the SoC. */ -#define FSL_FEATURE_SOC_ROM_COUNT (0) /* @brief ROMC availability on the SoC. */ #define FSL_FEATURE_SOC_ROMC_COUNT (1) -/* @brief RSIM availability on the SoC. */ -#define FSL_FEATURE_SOC_RSIM_COUNT (0) -/* @brief RSTCTL0 availability on the SoC. */ -#define FSL_FEATURE_SOC_RSTCTL0_COUNT (0) -/* @brief RSTCTL1 availability on the SoC. */ -#define FSL_FEATURE_SOC_RSTCTL1_COUNT (0) -/* @brief RTC availability on the SoC. */ -#define FSL_FEATURE_SOC_RTC_COUNT (0) -/* @brief SCG availability on the SoC. */ -#define FSL_FEATURE_SOC_SCG_COUNT (0) -/* @brief SCI availability on the SoC. */ -#define FSL_FEATURE_SOC_SCI_COUNT (0) -/* @brief SCT availability on the SoC. */ -#define FSL_FEATURE_SOC_SCT_COUNT (0) -/* @brief SDHC availability on the SoC. */ -#define FSL_FEATURE_SOC_SDHC_COUNT (0) -/* @brief SDIF availability on the SoC. */ -#define FSL_FEATURE_SOC_SDIF_COUNT (0) -/* @brief SDIO availability on the SoC. */ -#define FSL_FEATURE_SOC_SDIO_COUNT (0) -/* @brief SDMA availability on the SoC. */ -#define FSL_FEATURE_SOC_SDMA_COUNT (0) -/* @brief SDMAARM availability on the SoC. */ -#define FSL_FEATURE_SOC_SDMAARM_COUNT (0) -/* @brief SDMABP availability on the SoC. */ -#define FSL_FEATURE_SOC_SDMABP_COUNT (0) -/* @brief SDMACORE availability on the SoC. */ -#define FSL_FEATURE_SOC_SDMACORE_COUNT (0) -/* @brief SDMCORE availability on the SoC. */ -#define FSL_FEATURE_SOC_SDMCORE_COUNT (0) -/* @brief SDRAM availability on the SoC. */ -#define FSL_FEATURE_SOC_SDRAM_COUNT (0) -/* @brief SEMA4 availability on the SoC. */ -#define FSL_FEATURE_SOC_SEMA4_COUNT (0) -/* @brief SEMA42 availability on the SoC. */ -#define FSL_FEATURE_SOC_SEMA42_COUNT (0) /* @brief SEMC availability on the SoC. */ #define FSL_FEATURE_SOC_SEMC_COUNT (1) -/* @brief SHA availability on the SoC. */ -#define FSL_FEATURE_SOC_SHA_COUNT (0) -/* @brief SIM availability on the SoC. */ -#define FSL_FEATURE_SOC_SIM_COUNT (0) -/* @brief SJC availability on the SoC. */ -#define FSL_FEATURE_SOC_SJC_COUNT (0) -/* @brief SLCD availability on the SoC. */ -#define FSL_FEATURE_SOC_SLCD_COUNT (0) -/* @brief SMARTCARD availability on the SoC. */ -#define FSL_FEATURE_SOC_SMARTCARD_COUNT (0) -/* @brief SMC availability on the SoC. */ -#define FSL_FEATURE_SOC_SMC_COUNT (0) /* @brief SNVS availability on the SoC. */ #define FSL_FEATURE_SOC_SNVS_COUNT (1) -/* @brief SPBA availability on the SoC. */ -#define FSL_FEATURE_SOC_SPBA_COUNT (0) /* @brief SPDIF availability on the SoC. */ #define FSL_FEATURE_SOC_SPDIF_COUNT (1) -/* @brief SPI availability on the SoC. */ -#define FSL_FEATURE_SOC_SPI_COUNT (0) -/* @brief SPIFI availability on the SoC. */ -#define FSL_FEATURE_SOC_SPIFI_COUNT (0) -/* @brief SPM availability on the SoC. */ -#define FSL_FEATURE_SOC_SPM_COUNT (0) /* @brief SRC availability on the SoC. */ #define FSL_FEATURE_SOC_SRC_COUNT (1) -/* @brief SYSCON availability on the SoC. */ -#define FSL_FEATURE_SOC_SYSCON_COUNT (0) -/* @brief SYSCTL0 availability on the SoC. */ -#define FSL_FEATURE_SOC_SYSCTL0_COUNT (0) -/* @brief SYSCTL1 availability on the SoC. */ -#define FSL_FEATURE_SOC_SYSCTL1_COUNT (0) /* @brief TEMPMON availability on the SoC. */ #define FSL_FEATURE_SOC_TEMPMON_COUNT (1) /* @brief TMR availability on the SoC. */ #define FSL_FEATURE_SOC_TMR_COUNT (4) -/* @brief TPM availability on the SoC. */ -#define FSL_FEATURE_SOC_TPM_COUNT (0) -/* @brief TRGMUX availability on the SoC. */ -#define FSL_FEATURE_SOC_TRGMUX_COUNT (0) -/* @brief TRIAMP availability on the SoC. */ -#define FSL_FEATURE_SOC_TRIAMP_COUNT (0) /* @brief TRNG availability on the SoC. */ #define FSL_FEATURE_SOC_TRNG_COUNT (1) /* @brief TSC availability on the SoC. */ #define FSL_FEATURE_SOC_TSC_COUNT (1) -/* @brief TSI availability on the SoC. */ -#define FSL_FEATURE_SOC_TSI_COUNT (0) -/* @brief TSTMR availability on the SoC. */ -#define FSL_FEATURE_SOC_TSTMR_COUNT (0) -/* @brief UART availability on the SoC. */ -#define FSL_FEATURE_SOC_UART_COUNT (0) -/* @brief USART availability on the SoC. */ -#define FSL_FEATURE_SOC_USART_COUNT (0) -/* @brief USB availability on the SoC. */ -#define FSL_FEATURE_SOC_USB_COUNT (0) /* @brief USBHS availability on the SoC. */ #define FSL_FEATURE_SOC_USBHS_COUNT (2) -/* @brief USBDCD availability on the SoC. */ -#define FSL_FEATURE_SOC_USBDCD_COUNT (0) -/* @brief USBFSH availability on the SoC. */ -#define FSL_FEATURE_SOC_USBFSH_COUNT (0) -/* @brief USBHSD availability on the SoC. */ -#define FSL_FEATURE_SOC_USBHSD_COUNT (0) -/* @brief USBHSDCD availability on the SoC. */ -#define FSL_FEATURE_SOC_USBHSDCD_COUNT (0) -/* @brief USBHSH availability on the SoC. */ -#define FSL_FEATURE_SOC_USBHSH_COUNT (0) /* @brief USBNC availability on the SoC. */ #define FSL_FEATURE_SOC_USBNC_COUNT (2) /* @brief USBPHY availability on the SoC. */ #define FSL_FEATURE_SOC_USBPHY_COUNT (2) -/* @brief USB_HSIC availability on the SoC. */ -#define FSL_FEATURE_SOC_USB_HSIC_COUNT (0) -/* @brief USB_OTG availability on the SoC. */ -#define FSL_FEATURE_SOC_USB_OTG_COUNT (0) -/* @brief USBVREG availability on the SoC. */ -#define FSL_FEATURE_SOC_USBVREG_COUNT (0) /* @brief USDHC availability on the SoC. */ #define FSL_FEATURE_SOC_USDHC_COUNT (2) -/* @brief UTICK availability on the SoC. */ -#define FSL_FEATURE_SOC_UTICK_COUNT (0) -/* @brief VIU availability on the SoC. */ -#define FSL_FEATURE_SOC_VIU_COUNT (0) -/* @brief VREF availability on the SoC. */ -#define FSL_FEATURE_SOC_VREF_COUNT (0) -/* @brief VFIFO availability on the SoC. */ -#define FSL_FEATURE_SOC_VFIFO_COUNT (0) /* @brief WDOG availability on the SoC. */ #define FSL_FEATURE_SOC_WDOG_COUNT (2) -/* @brief WKPU availability on the SoC. */ -#define FSL_FEATURE_SOC_WKPU_COUNT (0) -/* @brief WWDT availability on the SoC. */ -#define FSL_FEATURE_SOC_WWDT_COUNT (0) -/* @brief XBAR availability on the SoC. */ -#define FSL_FEATURE_SOC_XBAR_COUNT (0) /* @brief XBARA availability on the SoC. */ #define FSL_FEATURE_SOC_XBARA_COUNT (1) /* @brief XBARB availability on the SoC. */ #define FSL_FEATURE_SOC_XBARB_COUNT (2) -/* @brief XCVR availability on the SoC. */ -#define FSL_FEATURE_SOC_XCVR_COUNT (0) -/* @brief XRDC availability on the SoC. */ -#define FSL_FEATURE_SOC_XRDC_COUNT (0) -/* @brief XTALOSC availability on the SoC. */ -#define FSL_FEATURE_SOC_XTALOSC_COUNT (0) /* @brief XTALOSC24M availability on the SoC. */ #define FSL_FEATURE_SOC_XTALOSC24M_COUNT (1) -/* @brief ZLL availability on the SoC. */ -#define FSL_FEATURE_SOC_ZLL_COUNT (0) /* ADC module features */ @@ -582,6 +139,11 @@ /* @brief Remove ALT Clock selection feature. */ #define FSL_FEATURE_ADC_SUPPORT_ALTCLK_REMOVE (1) +/* ADC_ETC module features */ + +/* @brief Has DMA model control(bit field CTRL[DMA_MODE_SEL]). */ +#define FSL_FEATURE_ADC_ETC_HAS_CTRL_DMA_MODE_SEL (1) + /* AOI module features */ /* @brief Maximum value of input mux. */ @@ -595,20 +157,34 @@ #define FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(x) (64) /* @brief Has doze mode support (register bit field MCR[DOZE]). */ #define FSL_FEATURE_FLEXCAN_HAS_DOZE_MODE_SUPPORT (0) +/* @brief Insatnce has doze mode support (register bit field MCR[DOZE]). */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_DOZE_MODE_SUPPORTn(x) (0) /* @brief Has a glitch filter on the receive pin (register bit field MCR[WAKSRC]). */ #define FSL_FEATURE_FLEXCAN_HAS_GLITCH_FILTER (1) /* @brief Has extended interrupt mask and flag register (register IMASK2, IFLAG2). */ #define FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER (1) -/* @brief Has extended bit timing register (register CBT). */ -#define FSL_FEATURE_FLEXCAN_HAS_EXTENDED_TIMING_REGISTER (0) +/* @brief Instance has extended bit timing register (register CBT). */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_EXTENDED_TIMING_REGISTERn(x) (0) /* @brief Has a receive FIFO DMA feature (register bit field MCR[DMA]). */ #define FSL_FEATURE_FLEXCAN_HAS_RX_FIFO_DMA (0) +/* @brief Instance has a receive FIFO DMA feature (register bit field MCR[DMA]). */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_RX_FIFO_DMAn(x) (0) /* @brief Remove CAN Engine Clock Source Selection from unsupported part. */ #define FSL_FEATURE_FLEXCAN_SUPPORT_ENGINE_CLK_SEL_REMOVE (1) +/* @brief Instance remove CAN Engine Clock Source Selection from unsupported part. */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_SUPPORT_ENGINE_CLK_SEL_REMOVEn(x) (1) /* @brief Is affected by errata with ID 5641 (Module does not transmit a message that is enabled to be transmitted at a specific moment during the arbitration process). */ #define FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641 (0) +/* @brief Is affected by errata with ID 5829 (FlexCAN: FlexCAN does not transmit a message that is enabled to be transmitted in a specific moment during the arbitration process). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_5829 (1) +/* @brief Is affected by errata with ID 6032 (FlexCAN: A frame with wrong ID or payload is transmitted into the CAN bus when the Message Buffer under transmission is either aborted or deactivated while the CAN bus is in the Bus Idle state). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_6032 (1) +/* @brief Is affected by errata with ID 9595 (FlexCAN: Corrupt frame possible if the Freeze Mode or the Low-Power Mode are entered during a Bus-Off state). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_9595 (1) /* @brief Has CAN with Flexible Data rate (CAN FD) protocol. */ #define FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE (0) +/* @brief CAN instance support Flexible Data rate (CAN FD) protocol. */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_FLEXIBLE_DATA_RATEn(x) (0) /* @brief Has extra MB interrupt or common one. */ #define FSL_FEATURE_FLEXCAN_HAS_EXTRA_MB_INT (1) @@ -666,10 +242,40 @@ /* @brief Has Additional 1588 Timer Channel Interrupt. */ #define FSL_FEATURE_ENET_HAS_ADD_1588_TIMER_CHN_INT (0) +/* EWM module features */ + +/* @brief Has clock select (register CLKCTRL). */ +#define FSL_FEATURE_EWM_HAS_CLOCK_SELECT (1) +/* @brief Has clock prescaler (register CLKPRESCALER). */ +#define FSL_FEATURE_EWM_HAS_PRESCALER (1) + +/* FLEXIO module features */ + +/* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */ +#define FSL_FEATURE_FLEXIO_HAS_SHIFTER_STATUS (1) +/* @brief Has Pin Data Input Register (FLEXIO_PIN) */ +#define FSL_FEATURE_FLEXIO_HAS_PIN_STATUS (1) +/* @brief Has Shifter Buffer N Nibble Byte Swapped Register (FLEXIO_SHIFTBUFNBSn) */ +#define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_BYTE_SWAP (1) +/* @brief Has Shifter Buffer N Half Word Swapped Register (FLEXIO_SHIFTBUFHWSn) */ +#define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_HALF_WORD_SWAP (1) +/* @brief Has Shifter Buffer N Nibble Swapped Register (FLEXIO_SHIFTBUFNISn) */ +#define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_SWAP (1) +/* @brief Supports Shifter State Mode (FLEXIO_SHIFTCTLn[SMOD]) */ +#define FSL_FEATURE_FLEXIO_HAS_STATE_MODE (1) +/* @brief Supports Shifter Logic Mode (FLEXIO_SHIFTCTLn[SMOD]) */ +#define FSL_FEATURE_FLEXIO_HAS_LOGIC_MODE (1) +/* @brief Supports paralle width (FLEXIO_SHIFTCFGn[PWIDTH]) */ +#define FSL_FEATURE_FLEXIO_HAS_PARALLEL_WIDTH (1) +/* @brief Reset value of the FLEXIO_VERID register */ +#define FSL_FEATURE_FLEXIO_VERID_RESET_VALUE (0x1010001) +/* @brief Reset value of the FLEXIO_PARAM register */ +#define FSL_FEATURE_FLEXIO_PARAM_RESET_VALUE (0x2200404) + /* FLEXRAM module features */ /* @brief Bank size */ -#define FSL_FEATURE_FLEXRAM_INTERNAL_RAM_BANK_SIZE (32 * 1024) +#define FSL_FEATURE_FLEXRAM_INTERNAL_RAM_BANK_SIZE (32768) /* @brief Total Bank numbers */ #define FSL_FEATURE_FLEXRAM_INTERNAL_RAM_TOTAL_BANK_NUMBERS (16) @@ -697,6 +303,15 @@ /* @brief Supports IRQ 0-31. */ #define FSL_FEATURE_GPC_HAS_IRQ_0_31 (1) +/* IGPIO module features */ + +/* @brief Has data register set DR_SET. */ +#define FSL_FEATURE_IGPIO_HAS_DR_SET (1) +/* @brief Has data register clear DR_CLEAR. */ +#define FSL_FEATURE_IGPIO_HAS_DR_CLEAR (1) +/* @brief Has data register toggle DR_TOGGLE. */ +#define FSL_FEATURE_IGPIO_HAS_DR_TOGGLE (1) + /* LPI2C module features */ /* @brief Has separate DMA RX and TX requests. */ @@ -787,7 +402,7 @@ /* @brief Lowest interrupt request number. */ #define FSL_FEATURE_INTERRUPT_IRQ_MIN (-14) /* @brief Highest interrupt request number. */ -#define FSL_FEATURE_INTERRUPT_IRQ_MAX (159) +#define FSL_FEATURE_INTERRUPT_IRQ_MAX (151) /* OCOTP module features */ @@ -865,8 +480,19 @@ #define FSL_FEATURE_SAI_INT_SOURCE_NUM (2) /* @brief Has register of MCR. */ #define FSL_FEATURE_SAI_HAS_MCR (0) +/* @brief Has bit field MICS of the MCR register. */ +#define FSL_FEATURE_SAI_HAS_NO_MCR_MICS (1) /* @brief Has register of MDR */ #define FSL_FEATURE_SAI_HAS_MDR (0) +/* @brief Has support the BCLK bypass mode when BCLK = MCLK. */ +#define FSL_FEATURE_SAI_HAS_BCLK_BYPASS (0) + +/* SEMC module features */ + +/* @brief Has WDH time in NOR controller (register bit field NORCR2[WDH]). */ +#define FSL_FEATURE_SEMC_HAS_NOR_WDH_TIME (1) +/* @brief Has WDS time in NOR controller (register bit field NORCR2[WDS]).) */ +#define FSL_FEATURE_SEMC_HAS_NOR_WDS_TIME (1) /* SNVS module features */ @@ -892,7 +518,7 @@ /* @brief There is CORE0_RST bit in SCR register. */ #define FSL_FEATURE_SRC_HAS_SCR_CORE0_RST (1) /* @brief There is LOCKUP_RST bit in SCR register. */ -#define FSL_FEATURE_SRC_HAS_SCR_LOCKUP_RST (1) +#define FSL_FEATURE_SRC_HAS_SCR_LOCKUP_RST (0) /* @brief There is SWRC bit in SCR register. */ #define FSL_FEATURE_SRC_HAS_SCR_SWRC (0) /* @brief There is EIM_RST bit in SCR register. */ diff --git a/ext/hal/nxp/mcux/devices/MIMXRT1051/fsl_clock.c b/ext/hal/nxp/mcux/devices/MIMXRT1051/fsl_clock.c new file mode 100644 index 00000000000..6bca872f501 --- /dev/null +++ b/ext/hal/nxp/mcux/devices/MIMXRT1051/fsl_clock.c @@ -0,0 +1,1207 @@ +/* + * Copyright 2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_clock.h" +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.clock" +#endif + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/* To make full use of CM7 hardware FPU, use double instead of uint64_t in clock driver to +achieve better performance, it is depend on the IDE Floating point settings, if double precision is selected +in IDE, clock_64b_t will switch to double type automatically. only support IAR and MDK here */ +#if __FPU_USED + +#if ((defined(__ICCARM__)) || (defined(__GNUC__))) + +#if (__ARMVFP__ >= __ARMFPV5__) && \ + (__ARM_FP == 0xE) /*0xe implies support for half, single and double precision operations*/ +typedef double clock_64b_t; +#else +typedef uint64_t clock_64b_t; +#endif + +#elif defined(__CC_ARM) || defined(__ARMCC_VERSION) + +#if defined __TARGET_FPU_FPV5_D16 +typedef double clock_64b_t; +#else +typedef uint64_t clock_64b_t; +#endif + +#else +typedef uint64_t clock_64b_t; +#endif + +#else +typedef uint64_t clock_64b_t; +#endif + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/* External XTAL (OSC) clock frequency. */ +volatile uint32_t g_xtalFreq; +/* External RTC XTAL clock frequency. */ +volatile uint32_t g_rtcXtalFreq; + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/*! + * @brief Get the periph clock frequency. + * + * @return Periph clock frequency in Hz. + */ +static uint32_t CLOCK_GetPeriphClkFreq(void); + +/******************************************************************************* + * Code + ******************************************************************************/ + +static uint32_t CLOCK_GetPeriphClkFreq(void) +{ + uint32_t freq; + + /* Periph_clk2_clk ---> Periph_clk */ + if (CCM->CBCDR & CCM_CBCDR_PERIPH_CLK_SEL_MASK) + { + switch (CCM->CBCMR & CCM_CBCMR_PERIPH_CLK2_SEL_MASK) + { + /* Pll3_sw_clk ---> Periph_clk2_clk ---> Periph_clk */ + case CCM_CBCMR_PERIPH_CLK2_SEL(0U): + freq = CLOCK_GetPllFreq(kCLOCK_PllUsb1); + break; + + /* Osc_clk ---> Periph_clk2_clk ---> Periph_clk */ + case CCM_CBCMR_PERIPH_CLK2_SEL(1U): + freq = CLOCK_GetOscFreq(); + break; + + case CCM_CBCMR_PERIPH_CLK2_SEL(2U): + freq = CLOCK_GetPllFreq(kCLOCK_PllSys); + break; + + case CCM_CBCMR_PERIPH_CLK2_SEL(3U): + default: + freq = 0U; + break; + } + + freq /= (((CCM->CBCDR & CCM_CBCDR_PERIPH_CLK2_PODF_MASK) >> CCM_CBCDR_PERIPH_CLK2_PODF_SHIFT) + 1U); + } + /* Pre_Periph_clk ---> Periph_clk */ + else + { + switch (CCM->CBCMR & CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK) + { + /* PLL2 ---> Pre_Periph_clk ---> Periph_clk */ + case CCM_CBCMR_PRE_PERIPH_CLK_SEL(0U): + freq = CLOCK_GetPllFreq(kCLOCK_PllSys); + break; + + /* PLL2 PFD2 ---> Pre_Periph_clk ---> Periph_clk */ + case CCM_CBCMR_PRE_PERIPH_CLK_SEL(1U): + freq = CLOCK_GetSysPfdFreq(kCLOCK_Pfd2); + break; + + /* PLL2 PFD0 ---> Pre_Periph_clk ---> Periph_clk */ + case CCM_CBCMR_PRE_PERIPH_CLK_SEL(2U): + freq = CLOCK_GetSysPfdFreq(kCLOCK_Pfd0); + break; + + /* PLL1 divided(/2) ---> Pre_Periph_clk ---> Periph_clk */ + case CCM_CBCMR_PRE_PERIPH_CLK_SEL(3U): + freq = CLOCK_GetPllFreq(kCLOCK_PllArm) / + (((CCM->CACRR & CCM_CACRR_ARM_PODF_MASK) >> CCM_CACRR_ARM_PODF_SHIFT) + 1U); + break; + + default: + freq = 0U; + break; + } + } + + return freq; +} + +/*! + * brief Initialize the external 24MHz clock. + * + * This function supports two modes: + * 1. Use external crystal oscillator. + * 2. Bypass the external crystal oscillator, using input source clock directly. + * + * After this function, please call ref CLOCK_SetXtal0Freq to inform clock driver + * the external clock frequency. + * + * param bypassXtalOsc Pass in true to bypass the external crystal oscillator. + * note This device does not support bypass external crystal oscillator, so + * the input parameter should always be false. + */ +void CLOCK_InitExternalClk(bool bypassXtalOsc) +{ + /* This device does not support bypass XTAL OSC. */ + assert(!bypassXtalOsc); + + CCM_ANALOG->MISC0_CLR = CCM_ANALOG_MISC0_XTAL_24M_PWD_MASK; /* Power up */ + while ((XTALOSC24M->LOWPWR_CTRL & XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_STAT_MASK) == 0) + { + } + CCM_ANALOG->MISC0_SET = CCM_ANALOG_MISC0_OSC_XTALOK_EN_MASK; /* detect freq */ + while ((CCM_ANALOG->MISC0 & CCM_ANALOG_MISC0_OSC_XTALOK_MASK) == 0) + { + } + CCM_ANALOG->MISC0_CLR = CCM_ANALOG_MISC0_OSC_XTALOK_EN_MASK; +} + +/*! + * brief Deinitialize the external 24MHz clock. + * + * This function disables the external 24MHz clock. + * + * After this function, please call ref CLOCK_SetXtal0Freq to set external clock + * frequency to 0. + */ +void CLOCK_DeinitExternalClk(void) +{ + CCM_ANALOG->MISC0_SET = CCM_ANALOG_MISC0_XTAL_24M_PWD_MASK; /* Power down */ +} + +/*! + * brief Switch the OSC. + * + * This function switches the OSC source for SoC. + * + * param osc OSC source to switch to. + */ +void CLOCK_SwitchOsc(clock_osc_t osc) +{ + if (osc == kCLOCK_RcOsc) + XTALOSC24M->LOWPWR_CTRL_SET = XTALOSC24M_LOWPWR_CTRL_SET_OSC_SEL_MASK; + else + XTALOSC24M->LOWPWR_CTRL_CLR = XTALOSC24M_LOWPWR_CTRL_CLR_OSC_SEL_MASK; +} + +/*! + * brief Initialize the RC oscillator 24MHz clock. + */ +void CLOCK_InitRcOsc24M(void) +{ + XTALOSC24M->LOWPWR_CTRL |= XTALOSC24M_LOWPWR_CTRL_RC_OSC_EN_MASK; +} + +/*! + * brief Power down the RCOSC 24M clock. + */ +void CLOCK_DeinitRcOsc24M(void) +{ + XTALOSC24M->LOWPWR_CTRL &= ~XTALOSC24M_LOWPWR_CTRL_RC_OSC_EN_MASK; +} + +/*! + * brief Gets the AHB clock frequency. + * + * return The AHB clock frequency value in hertz. + */ +uint32_t CLOCK_GetAhbFreq(void) +{ + return CLOCK_GetPeriphClkFreq() / (((CCM->CBCDR & CCM_CBCDR_AHB_PODF_MASK) >> CCM_CBCDR_AHB_PODF_SHIFT) + 1U); +} + +/*! + * brief Gets the SEMC clock frequency. + * + * return The SEMC clock frequency value in hertz. + */ +uint32_t CLOCK_GetSemcFreq(void) +{ + uint32_t freq; + + /* SEMC alternative clock ---> SEMC Clock */ + if (CCM->CBCDR & CCM_CBCDR_SEMC_CLK_SEL_MASK) + { + /* PLL3 PFD1 ---> SEMC alternative clock ---> SEMC Clock */ + if (CCM->CBCDR & CCM_CBCDR_SEMC_ALT_CLK_SEL_MASK) + { + freq = CLOCK_GetUsb1PfdFreq(kCLOCK_Pfd1); + } + /* PLL2 PFD2 ---> SEMC alternative clock ---> SEMC Clock */ + else + { + freq = CLOCK_GetSysPfdFreq(kCLOCK_Pfd2); + } + } + /* Periph_clk ---> SEMC Clock */ + else + { + freq = CLOCK_GetPeriphClkFreq(); + } + + freq /= (((CCM->CBCDR & CCM_CBCDR_SEMC_PODF_MASK) >> CCM_CBCDR_SEMC_PODF_SHIFT) + 1U); + + return freq; +} + +/*! + * brief Gets the IPG clock frequency. + * + * return The IPG clock frequency value in hertz. + */ +uint32_t CLOCK_GetIpgFreq(void) +{ + return CLOCK_GetAhbFreq() / (((CCM->CBCDR & CCM_CBCDR_IPG_PODF_MASK) >> CCM_CBCDR_IPG_PODF_SHIFT) + 1U); +} + +uint32_t CLOCK_GetPerClkFreq(void) +{ + uint32_t freq; + + /* Osc_clk ---> PER Clock*/ + if (CCM->CSCMR1 & CCM_CSCMR1_PERCLK_CLK_SEL_MASK) + { + freq = CLOCK_GetOscFreq(); + } + /* Periph_clk ---> AHB Clock ---> IPG Clock ---> PER Clock */ + else + { + freq = CLOCK_GetFreq(kCLOCK_IpgClk); + } + + freq /= (((CCM->CSCMR1 & CCM_CSCMR1_PERCLK_PODF_MASK) >> CCM_CSCMR1_PERCLK_PODF_SHIFT) + 1U); + + return freq; +} + +/*! + * brief Gets the clock frequency for a specific clock name. + * + * This function checks the current clock configurations and then calculates + * the clock frequency for a specific clock name defined in clock_name_t. + * + * param clockName Clock names defined in clock_name_t + * return Clock frequency value in hertz + */ +uint32_t CLOCK_GetFreq(clock_name_t name) +{ + uint32_t freq; + + switch (name) + { + case kCLOCK_CpuClk: + case kCLOCK_AhbClk: + freq = CLOCK_GetAhbFreq(); + break; + + case kCLOCK_SemcClk: + freq = CLOCK_GetSemcFreq(); + break; + + case kCLOCK_IpgClk: + freq = CLOCK_GetIpgFreq(); + break; + + case kCLOCK_PerClk: + freq = CLOCK_GetPerClkFreq(); + break; + + case kCLOCK_OscClk: + freq = CLOCK_GetOscFreq(); + break; + case kCLOCK_RtcClk: + freq = CLOCK_GetRtcFreq(); + break; + case kCLOCK_ArmPllClk: + freq = CLOCK_GetPllFreq(kCLOCK_PllArm); + break; + case kCLOCK_Usb1PllClk: + freq = CLOCK_GetPllFreq(kCLOCK_PllUsb1); + break; + case kCLOCK_Usb1PllPfd0Clk: + freq = CLOCK_GetUsb1PfdFreq(kCLOCK_Pfd0); + break; + case kCLOCK_Usb1PllPfd1Clk: + freq = CLOCK_GetUsb1PfdFreq(kCLOCK_Pfd1); + break; + case kCLOCK_Usb1PllPfd2Clk: + freq = CLOCK_GetUsb1PfdFreq(kCLOCK_Pfd2); + break; + case kCLOCK_Usb1PllPfd3Clk: + freq = CLOCK_GetUsb1PfdFreq(kCLOCK_Pfd3); + break; + case kCLOCK_Usb2PllClk: + freq = CLOCK_GetPllFreq(kCLOCK_PllUsb2); + break; + case kCLOCK_SysPllClk: + freq = CLOCK_GetPllFreq(kCLOCK_PllSys); + break; + case kCLOCK_SysPllPfd0Clk: + freq = CLOCK_GetSysPfdFreq(kCLOCK_Pfd0); + break; + case kCLOCK_SysPllPfd1Clk: + freq = CLOCK_GetSysPfdFreq(kCLOCK_Pfd1); + break; + case kCLOCK_SysPllPfd2Clk: + freq = CLOCK_GetSysPfdFreq(kCLOCK_Pfd2); + break; + case kCLOCK_SysPllPfd3Clk: + freq = CLOCK_GetSysPfdFreq(kCLOCK_Pfd3); + break; + case kCLOCK_EnetPll0Clk: + freq = CLOCK_GetPllFreq(kCLOCK_PllEnet); + break; + case kCLOCK_EnetPll1Clk: + freq = CLOCK_GetPllFreq(kCLOCK_PllEnet25M); + break; + case kCLOCK_AudioPllClk: + freq = CLOCK_GetPllFreq(kCLOCK_PllAudio); + break; + case kCLOCK_VideoPllClk: + freq = CLOCK_GetPllFreq(kCLOCK_PllVideo); + break; + default: + freq = 0U; + break; + } + + return freq; +} + +/*! brief Enable USB HS clock. + * + * This function only enables the access to USB HS prepheral, upper layer + * should first call the ref CLOCK_EnableUsbhs0PhyPllClock to enable the PHY + * clock to use USB HS. + * + * param src USB HS does not care about the clock source, here must be ref kCLOCK_UsbSrcUnused. + * param freq USB HS does not care about the clock source, so this parameter is ignored. + * retval true The clock is set successfully. + * retval false The clock source is invalid to get proper USB HS clock. + */ +bool CLOCK_EnableUsbhs0Clock(clock_usb_src_t src, uint32_t freq) +{ + CCM->CCGR6 |= CCM_CCGR6_CG0_MASK; + USB1->USBCMD |= USBHS_USBCMD_RST_MASK; + for (volatile uint32_t i = 0; i < 400000; + i++) /* Add a delay between RST and RS so make sure there is a DP pullup sequence*/ + { + __ASM("nop"); + } + PMU->REG_3P0 = (PMU->REG_3P0 & (~PMU_REG_3P0_OUTPUT_TRG_MASK)) | + (PMU_REG_3P0_OUTPUT_TRG(0x17) | PMU_REG_3P0_ENABLE_LINREG_MASK); + return true; +} + +/*! brief Enable USB HS clock. + * + * This function only enables the access to USB HS prepheral, upper layer + * should first call the ref CLOCK_EnableUsbhs0PhyPllClock to enable the PHY + * clock to use USB HS. + * + * param src USB HS does not care about the clock source, here must be ref kCLOCK_UsbSrcUnused. + * param freq USB HS does not care about the clock source, so this parameter is ignored. + * retval true The clock is set successfully. + * retval false The clock source is invalid to get proper USB HS clock. + */ +bool CLOCK_EnableUsbhs1Clock(clock_usb_src_t src, uint32_t freq) +{ + CCM->CCGR6 |= CCM_CCGR6_CG0_MASK; + USB2->USBCMD |= USBHS_USBCMD_RST_MASK; + for (volatile uint32_t i = 0; i < 400000; + i++) /* Add a delay between RST and RS so make sure there is a DP pullup sequence*/ + { + __ASM("nop"); + } + PMU->REG_3P0 = (PMU->REG_3P0 & (~PMU_REG_3P0_OUTPUT_TRG_MASK)) | + (PMU_REG_3P0_OUTPUT_TRG(0x17) | PMU_REG_3P0_ENABLE_LINREG_MASK); + return true; +} + +/*! brief Enable USB HS PHY PLL clock. + * + * This function enables the internal 480MHz USB PHY PLL clock. + * + * param src USB HS PHY PLL clock source. + * param freq The frequency specified by src. + * retval true The clock is set successfully. + * retval false The clock source is invalid to get proper USB HS clock. + */ +bool CLOCK_EnableUsbhs0PhyPllClock(clock_usb_phy_src_t src, uint32_t freq) +{ + const clock_usb_pll_config_t g_ccmConfigUsbPll = {.loopDivider = 0U}; + if (CCM_ANALOG->PLL_USB1 & CCM_ANALOG_PLL_USB1_ENABLE_MASK) + { + CCM_ANALOG->PLL_USB1 |= CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK; + } + else + { + CLOCK_InitUsb1Pll(&g_ccmConfigUsbPll); + } + USBPHY1->CTRL &= ~USBPHY_CTRL_SFTRST_MASK; /* release PHY from reset */ + USBPHY1->CTRL &= ~USBPHY_CTRL_CLKGATE_MASK; + + USBPHY1->PWD = 0; + USBPHY1->CTRL |= USBPHY_CTRL_ENAUTOCLR_PHY_PWD_MASK | USBPHY_CTRL_ENAUTOCLR_CLKGATE_MASK | + USBPHY_CTRL_ENUTMILEVEL2_MASK | USBPHY_CTRL_ENUTMILEVEL3_MASK; + return true; +} + +/*! brief Disable USB HS PHY PLL clock. + * + * This function disables USB HS PHY PLL clock. + */ +void CLOCK_DisableUsbhs0PhyPllClock(void) +{ + CCM_ANALOG->PLL_USB1 &= ~CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK; + USBPHY1->CTRL |= USBPHY_CTRL_CLKGATE_MASK; /* Set to 1U to gate clocks */ +} + +/*! + * brief Initialize the ARM PLL. + * + * This function initialize the ARM PLL with specific settings + * + * param config configuration to set to PLL. + */ +void CLOCK_InitArmPll(const clock_arm_pll_config_t *config) +{ + /* Bypass PLL first */ + CCM_ANALOG->PLL_ARM = (CCM_ANALOG->PLL_ARM & (~CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_MASK)) | + CCM_ANALOG_PLL_ARM_BYPASS_MASK | CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC(config->src); + + CCM_ANALOG->PLL_ARM = + (CCM_ANALOG->PLL_ARM & (~(CCM_ANALOG_PLL_ARM_DIV_SELECT_MASK | CCM_ANALOG_PLL_ARM_POWERDOWN_MASK))) | + CCM_ANALOG_PLL_ARM_ENABLE_MASK | CCM_ANALOG_PLL_ARM_DIV_SELECT(config->loopDivider); + + while ((CCM_ANALOG->PLL_ARM & CCM_ANALOG_PLL_ARM_LOCK_MASK) == 0) + { + } + + /* Disable Bypass */ + CCM_ANALOG->PLL_ARM &= ~CCM_ANALOG_PLL_ARM_BYPASS_MASK; +} + +/*! + * brief De-initialize the ARM PLL. + */ +void CLOCK_DeinitArmPll(void) +{ + CCM_ANALOG->PLL_ARM = CCM_ANALOG_PLL_ARM_POWERDOWN_MASK; +} + +/*! + * brief Initialize the System PLL. + * + * This function initializes the System PLL with specific settings + * + * param config Configuration to set to PLL. + */ +void CLOCK_InitSysPll(const clock_sys_pll_config_t *config) +{ + /* Bypass PLL first */ + CCM_ANALOG->PLL_SYS = (CCM_ANALOG->PLL_SYS & (~CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_MASK)) | + CCM_ANALOG_PLL_SYS_BYPASS_MASK | CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC(config->src); + + CCM_ANALOG->PLL_SYS = + (CCM_ANALOG->PLL_SYS & (~(CCM_ANALOG_PLL_SYS_DIV_SELECT_MASK | CCM_ANALOG_PLL_SYS_POWERDOWN_MASK))) | + CCM_ANALOG_PLL_SYS_ENABLE_MASK | CCM_ANALOG_PLL_SYS_DIV_SELECT(config->loopDivider); + + /* Initialize the fractional mode */ + CCM_ANALOG->PLL_SYS_NUM = CCM_ANALOG_PLL_SYS_NUM_A(config->numerator); + CCM_ANALOG->PLL_SYS_DENOM = CCM_ANALOG_PLL_SYS_DENOM_B(config->denominator); + + /* Initialize the spread spectrum mode */ + CCM_ANALOG->PLL_SYS_SS = CCM_ANALOG_PLL_SYS_SS_STEP(config->ss_step) | + CCM_ANALOG_PLL_SYS_SS_ENABLE(config->ss_enable) | + CCM_ANALOG_PLL_SYS_SS_STOP(config->ss_stop); + + while ((CCM_ANALOG->PLL_SYS & CCM_ANALOG_PLL_SYS_LOCK_MASK) == 0) + { + } + + /* Disable Bypass */ + CCM_ANALOG->PLL_SYS &= ~CCM_ANALOG_PLL_SYS_BYPASS_MASK; +} + +/*! + * brief De-initialize the System PLL. + */ +void CLOCK_DeinitSysPll(void) +{ + CCM_ANALOG->PLL_SYS = CCM_ANALOG_PLL_SYS_POWERDOWN_MASK; +} + +/*! + * brief Initialize the USB1 PLL. + * + * This function initializes the USB1 PLL with specific settings + * + * param config Configuration to set to PLL. + */ +void CLOCK_InitUsb1Pll(const clock_usb_pll_config_t *config) +{ + /* Bypass PLL first */ + CCM_ANALOG->PLL_USB1 = (CCM_ANALOG->PLL_USB1 & (~CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_MASK)) | + CCM_ANALOG_PLL_USB1_BYPASS_MASK | CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC(config->src); + + CCM_ANALOG->PLL_USB1 = (CCM_ANALOG->PLL_USB1 & (~CCM_ANALOG_PLL_USB1_DIV_SELECT_MASK)) | + CCM_ANALOG_PLL_USB1_ENABLE_MASK | CCM_ANALOG_PLL_USB1_POWER_MASK | + CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK | CCM_ANALOG_PLL_USB1_DIV_SELECT(config->loopDivider); + + while ((CCM_ANALOG->PLL_USB1 & CCM_ANALOG_PLL_USB1_LOCK_MASK) == 0) + { + } + + /* Disable Bypass */ + CCM_ANALOG->PLL_USB1 &= ~CCM_ANALOG_PLL_USB1_BYPASS_MASK; +} + +/*! + * brief Deinitialize the USB1 PLL. + */ +void CLOCK_DeinitUsb1Pll(void) +{ + CCM_ANALOG->PLL_USB1 = 0U; +} + +/*! + * brief Initialize the USB2 PLL. + * + * This function initializes the USB2 PLL with specific settings + * + * param config Configuration to set to PLL. + */ +void CLOCK_InitUsb2Pll(const clock_usb_pll_config_t *config) +{ + /* Bypass PLL first */ + CCM_ANALOG->PLL_USB2 = (CCM_ANALOG->PLL_USB2 & (~CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC_MASK)) | + CCM_ANALOG_PLL_USB2_BYPASS_MASK | CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC(config->src); + + CCM_ANALOG->PLL_USB2 = (CCM_ANALOG->PLL_USB2 & (~CCM_ANALOG_PLL_USB2_DIV_SELECT_MASK)) | + CCM_ANALOG_PLL_USB2_ENABLE_MASK | CCM_ANALOG_PLL_USB2_POWER_MASK | + CCM_ANALOG_PLL_USB2_EN_USB_CLKS_MASK | CCM_ANALOG_PLL_USB2_DIV_SELECT(config->loopDivider); + + while ((CCM_ANALOG->PLL_USB2 & CCM_ANALOG_PLL_USB2_LOCK_MASK) == 0) + { + } + + /* Disable Bypass */ + CCM_ANALOG->PLL_USB2 &= ~CCM_ANALOG_PLL_USB2_BYPASS_MASK; +} + +/*! + * brief Deinitialize the USB2 PLL. + */ +void CLOCK_DeinitUsb2Pll(void) +{ + CCM_ANALOG->PLL_USB2 = 0U; +} + +/*! + * brief Initializes the Audio PLL. + * + * This function initializes the Audio PLL with specific settings + * + * param config Configuration to set to PLL. + */ +void CLOCK_InitAudioPll(const clock_audio_pll_config_t *config) +{ + uint32_t pllAudio; + uint32_t misc2 = 0; + + /* Bypass PLL first */ + CCM_ANALOG->PLL_AUDIO = (CCM_ANALOG->PLL_AUDIO & (~CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_MASK)) | + CCM_ANALOG_PLL_AUDIO_BYPASS_MASK | CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC(config->src); + + CCM_ANALOG->PLL_AUDIO_NUM = CCM_ANALOG_PLL_AUDIO_NUM_A(config->numerator); + CCM_ANALOG->PLL_AUDIO_DENOM = CCM_ANALOG_PLL_AUDIO_DENOM_B(config->denominator); + + /* + * Set post divider: + * + * ------------------------------------------------------------------------ + * | config->postDivider | PLL_AUDIO[POST_DIV_SELECT] | MISC2[AUDIO_DIV] | + * ------------------------------------------------------------------------ + * | 1 | 2 | 0 | + * ------------------------------------------------------------------------ + * | 2 | 1 | 0 | + * ------------------------------------------------------------------------ + * | 4 | 2 | 3 | + * ------------------------------------------------------------------------ + * | 8 | 1 | 3 | + * ------------------------------------------------------------------------ + * | 16 | 0 | 3 | + * ------------------------------------------------------------------------ + */ + pllAudio = + (CCM_ANALOG->PLL_AUDIO & (~(CCM_ANALOG_PLL_AUDIO_DIV_SELECT_MASK | CCM_ANALOG_PLL_AUDIO_POWERDOWN_MASK))) | + CCM_ANALOG_PLL_AUDIO_ENABLE_MASK | CCM_ANALOG_PLL_AUDIO_DIV_SELECT(config->loopDivider); + + switch (config->postDivider) + { + case 16: + pllAudio |= CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT(0); + misc2 = CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK | CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK; + break; + + case 8: + pllAudio |= CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT(1); + misc2 = CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK | CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK; + break; + + case 4: + pllAudio |= CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT(2); + misc2 = CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK | CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK; + break; + + case 2: + pllAudio |= CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT(1); + break; + + default: + pllAudio |= CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT(2); + break; + } + + CCM_ANALOG->MISC2 = + (CCM_ANALOG->MISC2 & ~(CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK | CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK)) | misc2; + + CCM_ANALOG->PLL_AUDIO = pllAudio; + + while ((CCM_ANALOG->PLL_AUDIO & CCM_ANALOG_PLL_AUDIO_LOCK_MASK) == 0) + { + } + + /* Disable Bypass */ + CCM_ANALOG->PLL_AUDIO &= ~CCM_ANALOG_PLL_AUDIO_BYPASS_MASK; +} + +/*! + * brief De-initialize the Audio PLL. + */ +void CLOCK_DeinitAudioPll(void) +{ + CCM_ANALOG->PLL_AUDIO = CCM_ANALOG_PLL_AUDIO_POWERDOWN_MASK; +} + +/*! + * brief Initialize the video PLL. + * + * This function configures the Video PLL with specific settings + * + * param config configuration to set to PLL. + */ +void CLOCK_InitVideoPll(const clock_video_pll_config_t *config) +{ + uint32_t pllVideo; + uint32_t misc2 = 0; + + /* Bypass PLL first */ + CCM_ANALOG->PLL_VIDEO = (CCM_ANALOG->PLL_VIDEO & (~CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_MASK)) | + CCM_ANALOG_PLL_VIDEO_BYPASS_MASK | CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC(config->src); + + CCM_ANALOG->PLL_VIDEO_NUM = CCM_ANALOG_PLL_VIDEO_NUM_A(config->numerator); + CCM_ANALOG->PLL_VIDEO_DENOM = CCM_ANALOG_PLL_VIDEO_DENOM_B(config->denominator); + + /* + * Set post divider: + * + * ------------------------------------------------------------------------ + * | config->postDivider | PLL_VIDEO[POST_DIV_SELECT] | MISC2[VIDEO_DIV] | + * ------------------------------------------------------------------------ + * | 1 | 2 | 0 | + * ------------------------------------------------------------------------ + * | 2 | 1 | 0 | + * ------------------------------------------------------------------------ + * | 4 | 2 | 3 | + * ------------------------------------------------------------------------ + * | 8 | 1 | 3 | + * ------------------------------------------------------------------------ + * | 16 | 0 | 3 | + * ------------------------------------------------------------------------ + */ + pllVideo = + (CCM_ANALOG->PLL_VIDEO & (~(CCM_ANALOG_PLL_VIDEO_DIV_SELECT_MASK | CCM_ANALOG_PLL_VIDEO_POWERDOWN_MASK))) | + CCM_ANALOG_PLL_VIDEO_ENABLE_MASK | CCM_ANALOG_PLL_VIDEO_DIV_SELECT(config->loopDivider); + + switch (config->postDivider) + { + case 16: + pllVideo |= CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT(0); + misc2 = CCM_ANALOG_MISC2_VIDEO_DIV(3); + break; + + case 8: + pllVideo |= CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT(1); + misc2 = CCM_ANALOG_MISC2_VIDEO_DIV(3); + break; + + case 4: + pllVideo |= CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT(2); + misc2 = CCM_ANALOG_MISC2_VIDEO_DIV(3); + break; + + case 2: + pllVideo |= CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT(1); + break; + + default: + pllVideo |= CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT(2); + break; + } + + CCM_ANALOG->MISC2 = (CCM_ANALOG->MISC2 & ~CCM_ANALOG_MISC2_VIDEO_DIV_MASK) | misc2; + + CCM_ANALOG->PLL_VIDEO = pllVideo; + + while ((CCM_ANALOG->PLL_VIDEO & CCM_ANALOG_PLL_VIDEO_LOCK_MASK) == 0) + { + } + + /* Disable Bypass */ + CCM_ANALOG->PLL_VIDEO &= ~CCM_ANALOG_PLL_VIDEO_BYPASS_MASK; +} + +/*! + * brief De-initialize the Video PLL. + */ +void CLOCK_DeinitVideoPll(void) +{ + CCM_ANALOG->PLL_VIDEO = CCM_ANALOG_PLL_VIDEO_POWERDOWN_MASK; +} + +/*! + * brief Initialize the ENET PLL. + * + * This function initializes the ENET PLL with specific settings. + * + * param config Configuration to set to PLL. + */ +void CLOCK_InitEnetPll(const clock_enet_pll_config_t *config) +{ + uint32_t enet_pll = CCM_ANALOG_PLL_ENET_DIV_SELECT(config->loopDivider); + + CCM_ANALOG->PLL_ENET = (CCM_ANALOG->PLL_ENET & (~CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_MASK)) | + CCM_ANALOG_PLL_ENET_BYPASS_MASK | CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC(config->src); + + if (config->enableClkOutput) + { + enet_pll |= CCM_ANALOG_PLL_ENET_ENABLE_MASK; + } + + if (config->enableClkOutput25M) + { + enet_pll |= CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_MASK; + } + + CCM_ANALOG->PLL_ENET = + (CCM_ANALOG->PLL_ENET & (~(CCM_ANALOG_PLL_ENET_DIV_SELECT_MASK | CCM_ANALOG_PLL_ENET_POWERDOWN_MASK))) | + enet_pll; + + /* Wait for stable */ + while ((CCM_ANALOG->PLL_ENET & CCM_ANALOG_PLL_ENET_LOCK_MASK) == 0) + { + } + + /* Disable Bypass */ + CCM_ANALOG->PLL_ENET &= ~CCM_ANALOG_PLL_ENET_BYPASS_MASK; +} + +/*! + * brief Deinitialize the ENET PLL. + * + * This function disables the ENET PLL. + */ +void CLOCK_DeinitEnetPll(void) +{ + CCM_ANALOG->PLL_ENET = CCM_ANALOG_PLL_ENET_POWERDOWN_MASK; +} + +/*! + * brief Get current PLL output frequency. + * + * This function get current output frequency of specific PLL + * + * param pll pll name to get frequency. + * return The PLL output frequency in hertz. + */ +uint32_t CLOCK_GetPllFreq(clock_pll_t pll) +{ + uint32_t freq; + uint32_t divSelect; + clock_64b_t freqTmp; + + const uint32_t enetRefClkFreq[] = { + 25000000U, /* 25M */ + 50000000U, /* 50M */ + 100000000U, /* 100M */ + 125000000U /* 125M */ + }; + + /* check if PLL is enabled */ + if (!CLOCK_IsPllEnabled(CCM_ANALOG, pll)) + { + return 0U; + } + + /* get pll reference clock */ + freq = CLOCK_GetPllBypassRefClk(CCM_ANALOG, pll); + + /* check if pll is bypassed */ + if (CLOCK_IsPllBypassed(CCM_ANALOG, pll)) + { + return freq; + } + + switch (pll) + { + case kCLOCK_PllArm: + freq = ((freq * ((CCM_ANALOG->PLL_ARM & CCM_ANALOG_PLL_ARM_DIV_SELECT_MASK) >> + CCM_ANALOG_PLL_ARM_DIV_SELECT_SHIFT)) >> + 1U); + break; + case kCLOCK_PllSys: + /* PLL output frequency = Fref * (DIV_SELECT + NUM/DENOM). */ + freqTmp = ((clock_64b_t)freq * ((clock_64b_t)(CCM_ANALOG->PLL_SYS_NUM))) / + ((clock_64b_t)(CCM_ANALOG->PLL_SYS_DENOM)); + + if (CCM_ANALOG->PLL_SYS & CCM_ANALOG_PLL_SYS_DIV_SELECT_MASK) + { + freq *= 22U; + } + else + { + freq *= 20U; + } + + freq += (uint32_t)freqTmp; + break; + + case kCLOCK_PllUsb1: + freq = (freq * ((CCM_ANALOG->PLL_USB1 & CCM_ANALOG_PLL_USB1_DIV_SELECT_MASK) ? 22U : 20U)); + break; + + case kCLOCK_PllAudio: + /* PLL output frequency = Fref * (DIV_SELECT + NUM/DENOM). */ + divSelect = + (CCM_ANALOG->PLL_AUDIO & CCM_ANALOG_PLL_AUDIO_DIV_SELECT_MASK) >> CCM_ANALOG_PLL_AUDIO_DIV_SELECT_SHIFT; + + freqTmp = ((clock_64b_t)freq * ((clock_64b_t)(CCM_ANALOG->PLL_AUDIO_NUM))) / + ((clock_64b_t)(CCM_ANALOG->PLL_AUDIO_DENOM)); + + freq = freq * divSelect + (uint32_t)freqTmp; + + /* AUDIO PLL output = PLL output frequency / POSTDIV. */ + + /* + * Post divider: + * + * PLL_AUDIO[POST_DIV_SELECT]: + * 0x00: 4 + * 0x01: 2 + * 0x02: 1 + * + * MISC2[AUDO_DIV]: + * 0x00: 1 + * 0x01: 2 + * 0x02: 1 + * 0x03: 4 + */ + switch (CCM_ANALOG->PLL_AUDIO & CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_MASK) + { + case CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT(0U): + freq = freq >> 2U; + break; + + case CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT(1U): + freq = freq >> 1U; + break; + + default: + break; + } + + switch (CCM_ANALOG->MISC2 & (CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK | CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK)) + { + case CCM_ANALOG_MISC2_AUDIO_DIV_MSB(1) | CCM_ANALOG_MISC2_AUDIO_DIV_LSB(1): + freq >>= 2U; + break; + + case CCM_ANALOG_MISC2_AUDIO_DIV_MSB(0) | CCM_ANALOG_MISC2_AUDIO_DIV_LSB(1): + freq >>= 1U; + break; + + default: + break; + } + break; + + case kCLOCK_PllVideo: + /* PLL output frequency = Fref * (DIV_SELECT + NUM/DENOM). */ + divSelect = + (CCM_ANALOG->PLL_VIDEO & CCM_ANALOG_PLL_VIDEO_DIV_SELECT_MASK) >> CCM_ANALOG_PLL_VIDEO_DIV_SELECT_SHIFT; + + freqTmp = ((clock_64b_t)freq * ((clock_64b_t)(CCM_ANALOG->PLL_VIDEO_NUM))) / + ((clock_64b_t)(CCM_ANALOG->PLL_VIDEO_DENOM)); + + freq = freq * divSelect + (uint32_t)freqTmp; + + /* VIDEO PLL output = PLL output frequency / POSTDIV. */ + + /* + * Post divider: + * + * PLL_VIDEO[POST_DIV_SELECT]: + * 0x00: 4 + * 0x01: 2 + * 0x02: 1 + * + * MISC2[VIDEO_DIV]: + * 0x00: 1 + * 0x01: 2 + * 0x02: 1 + * 0x03: 4 + */ + switch (CCM_ANALOG->PLL_VIDEO & CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT_MASK) + { + case CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT(0U): + freq = freq >> 2U; + break; + + case CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT(1U): + freq = freq >> 1U; + break; + + default: + break; + } + + switch (CCM_ANALOG->MISC2 & CCM_ANALOG_MISC2_VIDEO_DIV_MASK) + { + case CCM_ANALOG_MISC2_VIDEO_DIV(3): + freq >>= 2U; + break; + + case CCM_ANALOG_MISC2_VIDEO_DIV(1): + freq >>= 1U; + break; + + default: + break; + } + break; + case kCLOCK_PllEnet: + divSelect = + (CCM_ANALOG->PLL_ENET & CCM_ANALOG_PLL_ENET_DIV_SELECT_MASK) >> CCM_ANALOG_PLL_ENET_DIV_SELECT_SHIFT; + freq = enetRefClkFreq[divSelect]; + break; + + case kCLOCK_PllEnet25M: + /* ref_enetpll1 if fixed at 25MHz. */ + freq = 25000000UL; + break; + + case kCLOCK_PllUsb2: + freq = (freq * ((CCM_ANALOG->PLL_USB2 & CCM_ANALOG_PLL_USB2_DIV_SELECT_MASK) ? 22U : 20U)); + break; + default: + freq = 0U; + break; + } + + return freq; +} + +/*! + * brief Initialize the System PLL PFD. + * + * This function initializes the System PLL PFD. During new value setting, + * the clock output is disabled to prevent glitch. + * + * param pfd Which PFD clock to enable. + * param pfdFrac The PFD FRAC value. + * note It is recommended that PFD settings are kept between 12-35. + */ +void CLOCK_InitSysPfd(clock_pfd_t pfd, uint8_t pfdFrac) +{ + uint32_t pfdIndex = (uint32_t)pfd; + uint32_t pfd528; + + pfd528 = CCM_ANALOG->PFD_528 & + ~((CCM_ANALOG_PFD_528_PFD0_CLKGATE_MASK | CCM_ANALOG_PFD_528_PFD0_FRAC_MASK) << (8 * pfdIndex)); + + /* Disable the clock output first. */ + CCM_ANALOG->PFD_528 = pfd528 | (CCM_ANALOG_PFD_528_PFD0_CLKGATE_MASK << (8 * pfdIndex)); + + /* Set the new value and enable output. */ + CCM_ANALOG->PFD_528 = pfd528 | (CCM_ANALOG_PFD_528_PFD0_FRAC(pfdFrac) << (8 * pfdIndex)); +} + +/*! + * brief De-initialize the System PLL PFD. + * + * This function disables the System PLL PFD. + * + * param pfd Which PFD clock to disable. + */ +void CLOCK_DeinitSysPfd(clock_pfd_t pfd) +{ + CCM_ANALOG->PFD_528 |= CCM_ANALOG_PFD_528_PFD0_CLKGATE_MASK << (8 * pfd); +} + +/*! + * brief Initialize the USB1 PLL PFD. + * + * This function initializes the USB1 PLL PFD. During new value setting, + * the clock output is disabled to prevent glitch. + * + * param pfd Which PFD clock to enable. + * param pfdFrac The PFD FRAC value. + * note It is recommended that PFD settings are kept between 12-35. + */ +void CLOCK_InitUsb1Pfd(clock_pfd_t pfd, uint8_t pfdFrac) +{ + uint32_t pfdIndex = (uint32_t)pfd; + uint32_t pfd480; + + pfd480 = CCM_ANALOG->PFD_480 & + ~((CCM_ANALOG_PFD_480_PFD0_CLKGATE_MASK | CCM_ANALOG_PFD_480_PFD0_FRAC_MASK) << (8 * pfdIndex)); + + /* Disable the clock output first. */ + CCM_ANALOG->PFD_480 = pfd480 | (CCM_ANALOG_PFD_480_PFD0_CLKGATE_MASK << (8 * pfdIndex)); + + /* Set the new value and enable output. */ + CCM_ANALOG->PFD_480 = pfd480 | (CCM_ANALOG_PFD_480_PFD0_FRAC(pfdFrac) << (8 * pfdIndex)); +} + +/*! + * brief De-initialize the USB1 PLL PFD. + * + * This function disables the USB1 PLL PFD. + * + * param pfd Which PFD clock to disable. + */ +void CLOCK_DeinitUsb1Pfd(clock_pfd_t pfd) +{ + CCM_ANALOG->PFD_480 |= CCM_ANALOG_PFD_480_PFD0_CLKGATE_MASK << (8 * pfd); +} + +/*! + * brief Get current System PLL PFD output frequency. + * + * This function get current output frequency of specific System PLL PFD + * + * param pfd pfd name to get frequency. + * return The PFD output frequency in hertz. + */ +uint32_t CLOCK_GetSysPfdFreq(clock_pfd_t pfd) +{ + uint32_t freq = CLOCK_GetPllFreq(kCLOCK_PllSys); + + switch (pfd) + { + case kCLOCK_Pfd0: + freq /= ((CCM_ANALOG->PFD_528 & CCM_ANALOG_PFD_528_PFD0_FRAC_MASK) >> CCM_ANALOG_PFD_528_PFD0_FRAC_SHIFT); + break; + + case kCLOCK_Pfd1: + freq /= ((CCM_ANALOG->PFD_528 & CCM_ANALOG_PFD_528_PFD1_FRAC_MASK) >> CCM_ANALOG_PFD_528_PFD1_FRAC_SHIFT); + break; + + case kCLOCK_Pfd2: + freq /= ((CCM_ANALOG->PFD_528 & CCM_ANALOG_PFD_528_PFD2_FRAC_MASK) >> CCM_ANALOG_PFD_528_PFD2_FRAC_SHIFT); + break; + + case kCLOCK_Pfd3: + freq /= ((CCM_ANALOG->PFD_528 & CCM_ANALOG_PFD_528_PFD3_FRAC_MASK) >> CCM_ANALOG_PFD_528_PFD3_FRAC_SHIFT); + break; + + default: + freq = 0U; + break; + } + freq *= 18U; + + return freq; +} + +/*! + * brief Get current USB1 PLL PFD output frequency. + * + * This function get current output frequency of specific USB1 PLL PFD + * + * param pfd pfd name to get frequency. + * return The PFD output frequency in hertz. + */ +uint32_t CLOCK_GetUsb1PfdFreq(clock_pfd_t pfd) +{ + uint32_t freq = CLOCK_GetPllFreq(kCLOCK_PllUsb1); + + switch (pfd) + { + case kCLOCK_Pfd0: + freq /= ((CCM_ANALOG->PFD_480 & CCM_ANALOG_PFD_480_PFD0_FRAC_MASK) >> CCM_ANALOG_PFD_480_PFD0_FRAC_SHIFT); + break; + + case kCLOCK_Pfd1: + freq /= ((CCM_ANALOG->PFD_480 & CCM_ANALOG_PFD_480_PFD1_FRAC_MASK) >> CCM_ANALOG_PFD_480_PFD1_FRAC_SHIFT); + break; + + case kCLOCK_Pfd2: + freq /= ((CCM_ANALOG->PFD_480 & CCM_ANALOG_PFD_480_PFD2_FRAC_MASK) >> CCM_ANALOG_PFD_480_PFD2_FRAC_SHIFT); + break; + + case kCLOCK_Pfd3: + freq /= ((CCM_ANALOG->PFD_480 & CCM_ANALOG_PFD_480_PFD3_FRAC_MASK) >> CCM_ANALOG_PFD_480_PFD3_FRAC_SHIFT); + break; + + default: + freq = 0U; + break; + } + freq *= 18U; + + return freq; +} + +/*! brief Enable USB HS PHY PLL clock. + * + * This function enables the internal 480MHz USB PHY PLL clock. + * + * param src USB HS PHY PLL clock source. + * param freq The frequency specified by src. + * retval true The clock is set successfully. + * retval false The clock source is invalid to get proper USB HS clock. + */ +bool CLOCK_EnableUsbhs1PhyPllClock(clock_usb_phy_src_t src, uint32_t freq) +{ + const clock_usb_pll_config_t g_ccmConfigUsbPll = {.loopDivider = 0U}; + CLOCK_InitUsb2Pll(&g_ccmConfigUsbPll); + USBPHY2->CTRL &= ~USBPHY_CTRL_SFTRST_MASK; /* release PHY from reset */ + USBPHY2->CTRL &= ~USBPHY_CTRL_CLKGATE_MASK; + + USBPHY2->PWD = 0; + USBPHY2->CTRL |= USBPHY_CTRL_ENAUTOCLR_PHY_PWD_MASK | USBPHY_CTRL_ENAUTOCLR_CLKGATE_MASK | + USBPHY_CTRL_ENUTMILEVEL2_MASK | USBPHY_CTRL_ENUTMILEVEL3_MASK; + + return true; +} + +/*! brief Disable USB HS PHY PLL clock. + * + * This function disables USB HS PHY PLL clock. + */ +void CLOCK_DisableUsbhs1PhyPllClock(void) +{ + CCM_ANALOG->PLL_USB2 &= ~CCM_ANALOG_PLL_USB2_EN_USB_CLKS_MASK; + USBPHY2->CTRL |= USBPHY_CTRL_CLKGATE_MASK; /* Set to 1U to gate clocks */ +} diff --git a/ext/hal/nxp/mcux/devices/MIMXRT1051/fsl_clock.h b/ext/hal/nxp/mcux/devices/MIMXRT1051/fsl_clock.h new file mode 100644 index 00000000000..5a24dc63363 --- /dev/null +++ b/ext/hal/nxp/mcux/devices/MIMXRT1051/fsl_clock.h @@ -0,0 +1,1471 @@ +/* + * Copyright 2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _FSL_CLOCK_H_ +#define _FSL_CLOCK_H_ + +#include "fsl_common.h" + +/*! @addtogroup clock */ +/*! @{ */ + +/*! @file */ + +/******************************************************************************* + * Configurations + ******************************************************************************/ + +/*! @brief Configure whether driver controls clock + * + * When set to 0, peripheral drivers will enable clock in initialize function + * and disable clock in de-initialize function. When set to 1, peripheral + * driver will not control the clock, application could control the clock out of + * the driver. + * + * @note All drivers share this feature switcher. If it is set to 1, application + * should handle clock enable and disable for all drivers. + */ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)) +#define FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL 0 +#endif + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief CLOCK driver version 2.1.5. */ +#define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 1, 5)) + +/* analog pll definition */ +#define CCM_ANALOG_PLL_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_BYPASS_CLK_SRC_SHIFT (14U) + +/*@}*/ +#define CCM_TUPLE(reg, shift, mask, busyShift) \ + ((((uint32_t)(&((CCM_Type *)0U)->reg)) & 0xFFU) | ((shift) << 8U) | ((((mask) >> (shift)) & 0x1FFFU) << 13U) | \ + ((busyShift) << 26U)) +#define CCM_TUPLE_REG(base, tuple) (*((volatile uint32_t *)(((uint32_t)(base)) + ((tuple)&0xFFU)))) +#define CCM_TUPLE_SHIFT(tuple) (((tuple) >> 8U) & 0x1FU) +#define CCM_TUPLE_MASK(tuple) ((uint32_t)((((tuple) >> 13U) & 0x1FFFU) << ((((tuple) >> 8U) & 0x1FU)))) +#define CCM_TUPLE_BUSY_SHIFT(tuple) (((tuple) >> 26U) & 0x3FU) + +#define CCM_NO_BUSY_WAIT (0x20U) + +/*! + * @brief CCM ANALOG tuple macros to map corresponding registers and bit fields. + */ +#define CCM_ANALOG_TUPLE(reg, shift) ((((uint32_t)(&((CCM_ANALOG_Type *)0U)->reg) & 0xFFFU) << 16U) | (shift)) +#define CCM_ANALOG_TUPLE_SHIFT(tuple) (((uint32_t)tuple) & 0x1FU) +#define CCM_ANALOG_TUPLE_REG_OFF(base, tuple, off) \ + (*((volatile uint32_t *)((uint32_t)base + (((uint32_t)tuple >> 16U) & 0xFFFU) + off))) +#define CCM_ANALOG_TUPLE_REG(base, tuple) CCM_ANALOG_TUPLE_REG_OFF(base, tuple, 0U) + +/*! + * @brief clock1PN frequency. + */ +#define CLKPN_FREQ 0U + +/*! @brief External XTAL (24M OSC/SYSOSC) clock frequency. + * + * The XTAL (24M OSC/SYSOSC) clock frequency in Hz, when the clock is setup, use the + * function CLOCK_SetXtalFreq to set the value in to clock driver. For example, + * if XTAL is 24MHz, + * @code + * CLOCK_InitExternalClk(false); // Setup the 24M OSC/SYSOSC + * CLOCK_SetXtalFreq(240000000); // Set the XTAL value to clock driver. + * @endcode + */ +extern volatile uint32_t g_xtalFreq; + +/*! @brief External RTC XTAL (32K OSC) clock frequency. + * + * The RTC XTAL (32K OSC) clock frequency in Hz, when the clock is setup, use the + * function CLOCK_SetRtcXtalFreq to set the value in to clock driver. + */ +extern volatile uint32_t g_rtcXtalFreq; + +/* For compatible with other platforms */ +#define CLOCK_SetXtal0Freq CLOCK_SetXtalFreq +#define CLOCK_SetXtal32Freq CLOCK_SetRtcXtalFreq + +/*! @brief Clock ip name array for ADC. */ +#define ADC_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_Adc1, kCLOCK_Adc2 \ + } + +/*! @brief Clock ip name array for AOI. */ +#define AOI_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_Aoi1, kCLOCK_Aoi2 \ + } + +/*! @brief Clock ip name array for BEE. */ +#define BEE_CLOCKS \ + { \ + kCLOCK_Bee \ + } + +/*! @brief Clock ip name array for CMP. */ +#define CMP_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_Acmp1, kCLOCK_Acmp2, kCLOCK_Acmp3, kCLOCK_Acmp4 \ + } + +/*! @brief Clock ip name array for CSI. */ +#define CSI_CLOCKS \ + { \ + kCLOCK_Csi \ + } + +/*! @brief Clock ip name array for DCDC. */ +#define DCDC_CLOCKS \ + { \ + kCLOCK_Dcdc \ + } + +/*! @brief Clock ip name array for DCP. */ +#define DCP_CLOCKS \ + { \ + kCLOCK_Dcp \ + } + +/*! @brief Clock ip name array for DMAMUX_CLOCKS. */ +#define DMAMUX_CLOCKS \ + { \ + kCLOCK_Dma \ + } + +/*! @brief Clock ip name array for DMA. */ +#define EDMA_CLOCKS \ + { \ + kCLOCK_Dma \ + } + +/*! @brief Clock ip name array for ENC. */ +#define ENC_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_Enc1, kCLOCK_Enc2, kCLOCK_Enc3, kCLOCK_Enc4 \ + } + +/*! @brief Clock ip name array for ENET. */ +#define ENET_CLOCKS \ + { \ + kCLOCK_Enet \ + } + +/*! @brief Clock ip name array for EWM. */ +#define EWM_CLOCKS \ + { \ + kCLOCK_Ewm0 \ + } + +/*! @brief Clock ip name array for FLEXCAN. */ +#define FLEXCAN_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_Can1, kCLOCK_Can2 \ + } + +/*! @brief Clock ip name array for FLEXCAN Peripheral clock. */ +#define FLEXCAN_PERIPH_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_Can1S, kCLOCK_Can2S \ + } + +/*! @brief Clock ip name array for FLEXIO. */ +#define FLEXIO_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_Flexio1, kCLOCK_Flexio2 \ + } + +/*! @brief Clock ip name array for FLEXRAM. */ +#define FLEXRAM_CLOCKS \ + { \ + kCLOCK_FlexRam \ + } + +/*! @brief Clock ip name array for FLEXSPI. */ +#define FLEXSPI_CLOCKS \ + { \ + kCLOCK_FlexSpi \ + } + +/*! @brief Clock ip name array for FLEXSPI EXSC. */ +#define FLEXSPI_EXSC_CLOCKS \ + { \ + kCLOCK_FlexSpiExsc \ + } + +/*! @brief Clock ip name array for GPIO. */ +#define GPIO_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_Gpio1, kCLOCK_Gpio2, kCLOCK_Gpio3, kCLOCK_Gpio4, kCLOCK_Gpio5 \ + } + +/*! @brief Clock ip name array for GPT. */ +#define GPT_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_Gpt1, kCLOCK_Gpt2 \ + } + +/*! @brief Clock ip name array for KPP. */ +#define KPP_CLOCKS \ + { \ + kCLOCK_Kpp \ + } + +/*! @brief Clock ip name array for LCDIF. */ +#define LCDIF_CLOCKS \ + { \ + kCLOCK_Lcd \ + } + +/*! @brief Clock ip name array for LCDIF PIXEL. */ +#define LCDIF_PERIPH_CLOCKS \ + { \ + kCLOCK_LcdPixel \ + } + +/*! @brief Clock ip name array for LPI2C. */ +#define LPI2C_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_Lpi2c1, kCLOCK_Lpi2c2, kCLOCK_Lpi2c3, kCLOCK_Lpi2c4 \ + } + +/*! @brief Clock ip name array for LPSPI. */ +#define LPSPI_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_Lpspi1, kCLOCK_Lpspi2, kCLOCK_Lpspi3, kCLOCK_Lpspi4 \ + } + +/*! @brief Clock ip name array for LPUART. */ +#define LPUART_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_Lpuart1, kCLOCK_Lpuart2, kCLOCK_Lpuart3, kCLOCK_Lpuart4, kCLOCK_Lpuart5, \ + kCLOCK_Lpuart6, kCLOCK_Lpuart7, kCLOCK_Lpuart8 \ + } + +/*! @brief Clock ip name array for MQS. */ +#define MQS_CLOCKS \ + { \ + kCLOCK_Mqs \ + } + +/*! @brief Clock ip name array for OCRAM EXSC. */ +#define OCRAM_EXSC_CLOCKS \ + { \ + kCLOCK_OcramExsc \ + } + +/*! @brief Clock ip name array for PIT. */ +#define PIT_CLOCKS \ + { \ + kCLOCK_Pit \ + } + +/*! @brief Clock ip name array for PWM. */ +#define PWM_CLOCKS \ + { \ + { \ + kCLOCK_IpInvalid, kCLOCK_IpInvalid, kCLOCK_IpInvalid, kCLOCK_IpInvalid \ + } \ + , {kCLOCK_Pwm1, kCLOCK_Pwm1, kCLOCK_Pwm1, kCLOCK_Pwm1}, {kCLOCK_Pwm2, kCLOCK_Pwm2, kCLOCK_Pwm2, kCLOCK_Pwm2}, \ + {kCLOCK_Pwm3, kCLOCK_Pwm3, kCLOCK_Pwm3, kCLOCK_Pwm3}, \ + { \ + kCLOCK_Pwm4, kCLOCK_Pwm4, kCLOCK_Pwm4, kCLOCK_Pwm4 \ + } \ + } + +/*! @brief Clock ip name array for PXP. */ +#define PXP_CLOCKS \ + { \ + kCLOCK_Pxp \ + } + +/*! @brief Clock ip name array for RTWDOG. */ +#define RTWDOG_CLOCKS \ + { \ + kCLOCK_Wdog3 \ + } + +/*! @brief Clock ip name array for SAI. */ +#define SAI_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_Sai1, kCLOCK_Sai2, kCLOCK_Sai3 \ + } + +/*! @brief Clock ip name array for SEMC. */ +#define SEMC_CLOCKS \ + { \ + kCLOCK_Semc \ + } + +/*! @brief Clock ip name array for SEMC EXSC. */ +#define SEMC_EXSC_CLOCKS \ + { \ + kCLOCK_SemcExsc \ + } + +/*! @brief Clock ip name array for QTIMER. */ +#define TMR_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_Timer1, kCLOCK_Timer2, kCLOCK_Timer3, kCLOCK_Timer4 \ + } + +/*! @brief Clock ip name array for TRNG. */ +#define TRNG_CLOCKS \ + { \ + kCLOCK_Trng \ + } + +/*! @brief Clock ip name array for TSC. */ +#define TSC_CLOCKS \ + { \ + kCLOCK_Tsc \ + } + +/*! @brief Clock ip name array for WDOG. */ +#define WDOG_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_Wdog1, kCLOCK_Wdog2 \ + } + +/*! @brief Clock ip name array for USDHC. */ +#define USDHC_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_Usdhc1, kCLOCK_Usdhc2 \ + } + +/*! @brief Clock ip name array for SPDIF. */ +#define SPDIF_CLOCKS \ + { \ + kCLOCK_Spdif \ + } + +/*! @brief Clock ip name array for XBARA. */ +#define XBARA_CLOCKS \ + { \ + kCLOCK_Xbar1 \ + } + +/*! @brief Clock ip name array for XBARB. */ +#define XBARB_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_IpInvalid, kCLOCK_Xbar2, kCLOCK_Xbar3 \ + } + +/*! @brief Clock name used to get clock frequency. */ +typedef enum _clock_name +{ + kCLOCK_CpuClk = 0x0U, /*!< CPU clock */ + kCLOCK_AhbClk = 0x1U, /*!< AHB clock */ + kCLOCK_SemcClk = 0x2U, /*!< SEMC clock */ + kCLOCK_IpgClk = 0x3U, /*!< IPG clock */ + kCLOCK_PerClk = 0x4U, /*!< PER clock */ + + kCLOCK_OscClk = 0x5U, /*!< OSC clock selected by PMU_LOWPWR_CTRL[OSC_SEL]. */ + kCLOCK_RtcClk = 0x6U, /*!< RTC clock. (RTCCLK) */ + + kCLOCK_ArmPllClk = 0x7U, /*!< ARMPLLCLK. */ + + kCLOCK_Usb1PllClk = 0x8U, /*!< USB1PLLCLK. */ + kCLOCK_Usb1PllPfd0Clk = 0x9U, /*!< USB1PLLPDF0CLK. */ + kCLOCK_Usb1PllPfd1Clk = 0xAU, /*!< USB1PLLPFD1CLK. */ + kCLOCK_Usb1PllPfd2Clk = 0xBU, /*!< USB1PLLPFD2CLK. */ + kCLOCK_Usb1PllPfd3Clk = 0xCU, /*!< USB1PLLPFD3CLK. */ + + kCLOCK_Usb2PllClk = 0xDU, /*!< USB2PLLCLK. */ + + kCLOCK_SysPllClk = 0xEU, /*!< SYSPLLCLK. */ + kCLOCK_SysPllPfd0Clk = 0xFU, /*!< SYSPLLPDF0CLK. */ + kCLOCK_SysPllPfd1Clk = 0x10U, /*!< SYSPLLPFD1CLK. */ + kCLOCK_SysPllPfd2Clk = 0x11U, /*!< SYSPLLPFD2CLK. */ + kCLOCK_SysPllPfd3Clk = 0x12U, /*!< SYSPLLPFD3CLK. */ + + kCLOCK_EnetPll0Clk = 0x13U, /*!< Enet PLLCLK ref_enetpll0. */ + kCLOCK_EnetPll1Clk = 0x14U, /*!< Enet PLLCLK ref_enetpll1. */ + + kCLOCK_AudioPllClk = 0x15U, /*!< Audio PLLCLK. */ + kCLOCK_VideoPllClk = 0x16U, /*!< Video PLLCLK. */ +} clock_name_t; + +#define kCLOCK_CoreSysClk kCLOCK_CpuClk /*!< For compatible with other platforms without CCM. */ +#define CLOCK_GetCoreSysClkFreq CLOCK_GetCpuClkFreq /*!< For compatible with other platforms without CCM. */ + +/*! + * @brief CCM CCGR gate control for each module independently. + */ +typedef enum _clock_ip_name +{ + kCLOCK_IpInvalid = -1, + + /* CCM CCGR0 */ + kCLOCK_Aips_tz1 = (0U << 8U) | CCM_CCGR0_CG0_SHIFT, /*!< CCGR0, CG0 */ + kCLOCK_Aips_tz2 = (0U << 8U) | CCM_CCGR0_CG1_SHIFT, /*!< CCGR0, CG1 */ + kCLOCK_Mqs = (0U << 8U) | CCM_CCGR0_CG2_SHIFT, /*!< CCGR0, CG2 */ + kCLOCK_FlexSpiExsc = (0U << 8U) | CCM_CCGR0_CG3_SHIFT, /*!< CCGR0, CG3 */ + kCLOCK_Sim_M_Main = (0U << 8U) | CCM_CCGR0_CG4_SHIFT, /*!< CCGR0, CG4 */ + kCLOCK_Dcp = (0U << 8U) | CCM_CCGR0_CG5_SHIFT, /*!< CCGR0, CG5 */ + kCLOCK_Lpuart3 = (0U << 8U) | CCM_CCGR0_CG6_SHIFT, /*!< CCGR0, CG6 */ + kCLOCK_Can1 = (0U << 8U) | CCM_CCGR0_CG7_SHIFT, /*!< CCGR0, CG7 */ + kCLOCK_Can1S = (0U << 8U) | CCM_CCGR0_CG8_SHIFT, /*!< CCGR0, CG8 */ + kCLOCK_Can2 = (0U << 8U) | CCM_CCGR0_CG9_SHIFT, /*!< CCGR0, CG9 */ + kCLOCK_Can2S = (0U << 8U) | CCM_CCGR0_CG10_SHIFT, /*!< CCGR0, CG10 */ + kCLOCK_Trace = (0U << 8U) | CCM_CCGR0_CG11_SHIFT, /*!< CCGR0, CG11 */ + kCLOCK_Gpt2 = (0U << 8U) | CCM_CCGR0_CG12_SHIFT, /*!< CCGR0, CG12 */ + kCLOCK_Gpt2S = (0U << 8U) | CCM_CCGR0_CG13_SHIFT, /*!< CCGR0, CG13 */ + kCLOCK_Lpuart2 = (0U << 8U) | CCM_CCGR0_CG14_SHIFT, /*!< CCGR0, CG14 */ + kCLOCK_Gpio2 = (0U << 8U) | CCM_CCGR0_CG15_SHIFT, /*!< CCGR0, CG15 */ + + /* CCM CCGR1 */ + kCLOCK_Lpspi1 = (1U << 8U) | CCM_CCGR1_CG0_SHIFT, /*!< CCGR1, CG0 */ + kCLOCK_Lpspi2 = (1U << 8U) | CCM_CCGR1_CG1_SHIFT, /*!< CCGR1, CG1 */ + kCLOCK_Lpspi3 = (1U << 8U) | CCM_CCGR1_CG2_SHIFT, /*!< CCGR1, CG2 */ + kCLOCK_Lpspi4 = (1U << 8U) | CCM_CCGR1_CG3_SHIFT, /*!< CCGR1, CG3 */ + kCLOCK_Adc2 = (1U << 8U) | CCM_CCGR1_CG4_SHIFT, /*!< CCGR1, CG4 */ + kCLOCK_Enet = (1U << 8U) | CCM_CCGR1_CG5_SHIFT, /*!< CCGR1, CG5 */ + kCLOCK_Pit = (1U << 8U) | CCM_CCGR1_CG6_SHIFT, /*!< CCGR1, CG6 */ + kCLOCK_Aoi2 = (1U << 8U) | CCM_CCGR1_CG7_SHIFT, /*!< CCGR1, CG7 */ + kCLOCK_Adc1 = (1U << 8U) | CCM_CCGR1_CG8_SHIFT, /*!< CCGR1, CG8 */ + kCLOCK_SemcExsc = (1U << 8U) | CCM_CCGR1_CG9_SHIFT, /*!< CCGR1, CG9 */ + kCLOCK_Gpt1 = (1U << 8U) | CCM_CCGR1_CG10_SHIFT, /*!< CCGR1, CG10 */ + kCLOCK_Gpt1S = (1U << 8U) | CCM_CCGR1_CG11_SHIFT, /*!< CCGR1, CG11 */ + kCLOCK_Lpuart4 = (1U << 8U) | CCM_CCGR1_CG12_SHIFT, /*!< CCGR1, CG12 */ + kCLOCK_Gpio1 = (1U << 8U) | CCM_CCGR1_CG13_SHIFT, /*!< CCGR1, CG13 */ + kCLOCK_Csu = (1U << 8U) | CCM_CCGR1_CG14_SHIFT, /*!< CCGR1, CG14 */ + kCLOCK_Gpio5 = (1U << 8U) | CCM_CCGR1_CG15_SHIFT, /*!< CCGR1, CG15 */ + + /* CCM CCGR2 */ + kCLOCK_OcramExsc = (2U << 8U) | CCM_CCGR2_CG0_SHIFT, /*!< CCGR2, CG0 */ + kCLOCK_Csi = (2U << 8U) | CCM_CCGR2_CG1_SHIFT, /*!< CCGR2, CG1 */ + kCLOCK_IomuxcSnvs = (2U << 8U) | CCM_CCGR2_CG2_SHIFT, /*!< CCGR2, CG2 */ + kCLOCK_Lpi2c1 = (2U << 8U) | CCM_CCGR2_CG3_SHIFT, /*!< CCGR2, CG3 */ + kCLOCK_Lpi2c2 = (2U << 8U) | CCM_CCGR2_CG4_SHIFT, /*!< CCGR2, CG4 */ + kCLOCK_Lpi2c3 = (2U << 8U) | CCM_CCGR2_CG5_SHIFT, /*!< CCGR2, CG5 */ + kCLOCK_Ocotp = (2U << 8U) | CCM_CCGR2_CG6_SHIFT, /*!< CCGR2, CG6 */ + kCLOCK_Xbar3 = (2U << 8U) | CCM_CCGR2_CG7_SHIFT, /*!< CCGR2, CG7 */ + kCLOCK_Ipmux1 = (2U << 8U) | CCM_CCGR2_CG8_SHIFT, /*!< CCGR2, CG8 */ + kCLOCK_Ipmux2 = (2U << 8U) | CCM_CCGR2_CG9_SHIFT, /*!< CCGR2, CG9 */ + kCLOCK_Ipmux3 = (2U << 8U) | CCM_CCGR2_CG10_SHIFT, /*!< CCGR2, CG10 */ + kCLOCK_Xbar1 = (2U << 8U) | CCM_CCGR2_CG11_SHIFT, /*!< CCGR2, CG11 */ + kCLOCK_Xbar2 = (2U << 8U) | CCM_CCGR2_CG12_SHIFT, /*!< CCGR2, CG12 */ + kCLOCK_Gpio3 = (2U << 8U) | CCM_CCGR2_CG13_SHIFT, /*!< CCGR2, CG13 */ + kCLOCK_Lcd = (2U << 8U) | CCM_CCGR2_CG14_SHIFT, /*!< CCGR2, CG14 */ + kCLOCK_Pxp = (2U << 8U) | CCM_CCGR2_CG15_SHIFT, /*!< CCGR2, CG15 */ + + /* CCM CCGR3 */ + kCLOCK_Flexio2 = (3U << 8U) | CCM_CCGR3_CG0_SHIFT, /*!< CCGR3, CG0 */ + kCLOCK_Lpuart5 = (3U << 8U) | CCM_CCGR3_CG1_SHIFT, /*!< CCGR3, CG1 */ + kCLOCK_Semc = (3U << 8U) | CCM_CCGR3_CG2_SHIFT, /*!< CCGR3, CG2 */ + kCLOCK_Lpuart6 = (3U << 8U) | CCM_CCGR3_CG3_SHIFT, /*!< CCGR3, CG3 */ + kCLOCK_Aoi1 = (3U << 8U) | CCM_CCGR3_CG4_SHIFT, /*!< CCGR3, CG4 */ + kCLOCK_LcdPixel = (3U << 8U) | CCM_CCGR3_CG5_SHIFT, /*!< CCGR3, CG5 */ + kCLOCK_Gpio4 = (3U << 8U) | CCM_CCGR3_CG6_SHIFT, /*!< CCGR3, CG6 */ + kCLOCK_Ewm0 = (3U << 8U) | CCM_CCGR3_CG7_SHIFT, /*!< CCGR3, CG7 */ + kCLOCK_Wdog1 = (3U << 8U) | CCM_CCGR3_CG8_SHIFT, /*!< CCGR3, CG8 */ + kCLOCK_FlexRam = (3U << 8U) | CCM_CCGR3_CG9_SHIFT, /*!< CCGR3, CG9 */ + kCLOCK_Acmp1 = (3U << 8U) | CCM_CCGR3_CG10_SHIFT, /*!< CCGR3, CG10 */ + kCLOCK_Acmp2 = (3U << 8U) | CCM_CCGR3_CG11_SHIFT, /*!< CCGR3, CG11 */ + kCLOCK_Acmp3 = (3U << 8U) | CCM_CCGR3_CG12_SHIFT, /*!< CCGR3, CG12 */ + kCLOCK_Acmp4 = (3U << 8U) | CCM_CCGR3_CG13_SHIFT, /*!< CCGR3, CG13 */ + kCLOCK_Ocram = (3U << 8U) | CCM_CCGR3_CG14_SHIFT, /*!< CCGR3, CG14 */ + kCLOCK_IomuxcSnvsGpr = (3U << 8U) | CCM_CCGR3_CG15_SHIFT, /*!< CCGR3, CG15 */ + + /* CCM CCGR4 */ + kCLOCK_Iomuxc = (4U << 8U) | CCM_CCGR4_CG1_SHIFT, /*!< CCGR4, CG1 */ + kCLOCK_IomuxcGpr = (4U << 8U) | CCM_CCGR4_CG2_SHIFT, /*!< CCGR4, CG2 */ + kCLOCK_Bee = (4U << 8U) | CCM_CCGR4_CG3_SHIFT, /*!< CCGR4, CG3 */ + kCLOCK_SimM7 = (4U << 8U) | CCM_CCGR4_CG4_SHIFT, /*!< CCGR4, CG4 */ + kCLOCK_Tsc = (4U << 8U) | CCM_CCGR4_CG5_SHIFT, /*!< CCGR4, CG5 */ + kCLOCK_SimM = (4U << 8U) | CCM_CCGR4_CG6_SHIFT, /*!< CCGR4, CG6 */ + kCLOCK_SimEms = (4U << 8U) | CCM_CCGR4_CG7_SHIFT, /*!< CCGR4, CG7 */ + kCLOCK_Pwm1 = (4U << 8U) | CCM_CCGR4_CG8_SHIFT, /*!< CCGR4, CG8 */ + kCLOCK_Pwm2 = (4U << 8U) | CCM_CCGR4_CG9_SHIFT, /*!< CCGR4, CG9 */ + kCLOCK_Pwm3 = (4U << 8U) | CCM_CCGR4_CG10_SHIFT, /*!< CCGR4, CG10 */ + kCLOCK_Pwm4 = (4U << 8U) | CCM_CCGR4_CG11_SHIFT, /*!< CCGR4, CG11 */ + kCLOCK_Enc1 = (4U << 8U) | CCM_CCGR4_CG12_SHIFT, /*!< CCGR4, CG12 */ + kCLOCK_Enc2 = (4U << 8U) | CCM_CCGR4_CG13_SHIFT, /*!< CCGR4, CG13 */ + kCLOCK_Enc3 = (4U << 8U) | CCM_CCGR4_CG14_SHIFT, /*!< CCGR4, CG14 */ + kCLOCK_Enc4 = (4U << 8U) | CCM_CCGR4_CG15_SHIFT, /*!< CCGR4, CG15 */ + + /* CCM CCGR5 */ + kCLOCK_Rom = (5U << 8U) | CCM_CCGR5_CG0_SHIFT, /*!< CCGR5, CG0 */ + kCLOCK_Flexio1 = (5U << 8U) | CCM_CCGR5_CG1_SHIFT, /*!< CCGR5, CG1 */ + kCLOCK_Wdog3 = (5U << 8U) | CCM_CCGR5_CG2_SHIFT, /*!< CCGR5, CG2 */ + kCLOCK_Dma = (5U << 8U) | CCM_CCGR5_CG3_SHIFT, /*!< CCGR5, CG3 */ + kCLOCK_Kpp = (5U << 8U) | CCM_CCGR5_CG4_SHIFT, /*!< CCGR5, CG4 */ + kCLOCK_Wdog2 = (5U << 8U) | CCM_CCGR5_CG5_SHIFT, /*!< CCGR5, CG5 */ + kCLOCK_Aips_tz4 = (5U << 8U) | CCM_CCGR5_CG6_SHIFT, /*!< CCGR5, CG6 */ + kCLOCK_Spdif = (5U << 8U) | CCM_CCGR5_CG7_SHIFT, /*!< CCGR5, CG7 */ + kCLOCK_SimMain = (5U << 8U) | CCM_CCGR5_CG8_SHIFT, /*!< CCGR5, CG8 */ + kCLOCK_Sai1 = (5U << 8U) | CCM_CCGR5_CG9_SHIFT, /*!< CCGR5, CG9 */ + kCLOCK_Sai2 = (5U << 8U) | CCM_CCGR5_CG10_SHIFT, /*!< CCGR5, CG10 */ + kCLOCK_Sai3 = (5U << 8U) | CCM_CCGR5_CG11_SHIFT, /*!< CCGR5, CG11 */ + kCLOCK_Lpuart1 = (5U << 8U) | CCM_CCGR5_CG12_SHIFT, /*!< CCGR5, CG12 */ + kCLOCK_Lpuart7 = (5U << 8U) | CCM_CCGR5_CG13_SHIFT, /*!< CCGR5, CG13 */ + kCLOCK_SnvsHp = (5U << 8U) | CCM_CCGR5_CG14_SHIFT, /*!< CCGR5, CG14 */ + kCLOCK_SnvsLp = (5U << 8U) | CCM_CCGR5_CG15_SHIFT, /*!< CCGR5, CG15 */ + + /* CCM CCGR6 */ + kCLOCK_UsbOh3 = (6U << 8U) | CCM_CCGR6_CG0_SHIFT, /*!< CCGR6, CG0 */ + kCLOCK_Usdhc1 = (6U << 8U) | CCM_CCGR6_CG1_SHIFT, /*!< CCGR6, CG1 */ + kCLOCK_Usdhc2 = (6U << 8U) | CCM_CCGR6_CG2_SHIFT, /*!< CCGR6, CG2 */ + kCLOCK_Dcdc = (6U << 8U) | CCM_CCGR6_CG3_SHIFT, /*!< CCGR6, CG3 */ + kCLOCK_Ipmux4 = (6U << 8U) | CCM_CCGR6_CG4_SHIFT, /*!< CCGR6, CG4 */ + kCLOCK_FlexSpi = (6U << 8U) | CCM_CCGR6_CG5_SHIFT, /*!< CCGR6, CG5 */ + kCLOCK_Trng = (6U << 8U) | CCM_CCGR6_CG6_SHIFT, /*!< CCGR6, CG6 */ + kCLOCK_Lpuart8 = (6U << 8U) | CCM_CCGR6_CG7_SHIFT, /*!< CCGR6, CG7 */ + kCLOCK_Timer4 = (6U << 8U) | CCM_CCGR6_CG8_SHIFT, /*!< CCGR6, CG8 */ + kCLOCK_Aips_tz3 = (6U << 8U) | CCM_CCGR6_CG9_SHIFT, /*!< CCGR6, CG9 */ + kCLOCK_SimPer = (6U << 8U) | CCM_CCGR6_CG10_SHIFT, /*!< CCGR6, CG10 */ + kCLOCK_Anadig = (6U << 8U) | CCM_CCGR6_CG11_SHIFT, /*!< CCGR6, CG11 */ + kCLOCK_Lpi2c4 = (6U << 8U) | CCM_CCGR6_CG12_SHIFT, /*!< CCGR6, CG12 */ + kCLOCK_Timer1 = (6U << 8U) | CCM_CCGR6_CG13_SHIFT, /*!< CCGR6, CG13 */ + kCLOCK_Timer2 = (6U << 8U) | CCM_CCGR6_CG14_SHIFT, /*!< CCGR6, CG14 */ + kCLOCK_Timer3 = (6U << 8U) | CCM_CCGR6_CG15_SHIFT, /*!< CCGR6, CG15 */ + +} clock_ip_name_t; + +/*! @brief OSC 24M sorce select */ +typedef enum _clock_osc +{ + kCLOCK_RcOsc = 0U, /*!< On chip OSC. */ + kCLOCK_XtalOsc = 1U, /*!< 24M Xtal OSC */ +} clock_osc_t; + +/*! @brief Clock gate value */ +typedef enum _clock_gate_value +{ + kCLOCK_ClockNotNeeded = 0U, /*!< Clock is off during all modes. */ + kCLOCK_ClockNeededRun = 1U, /*!< Clock is on in run mode, but off in WAIT and STOP modes */ + kCLOCK_ClockNeededRunWait = 3U, /*!< Clock is on during all modes, except STOP mode */ +} clock_gate_value_t; + +/*! @brief System clock mode */ +typedef enum _clock_mode_t +{ + kCLOCK_ModeRun = 0U, /*!< Remain in run mode. */ + kCLOCK_ModeWait = 1U, /*!< Transfer to wait mode. */ + kCLOCK_ModeStop = 2U, /*!< Transfer to stop mode. */ +} clock_mode_t; + +/*! + * @brief MUX control names for clock mux setting. + * + * These constants define the mux control names for clock mux setting.\n + * - 0:7: REG offset to CCM_BASE in bytes. + * - 8:15: Root clock setting bit field shift. + * - 16:31: Root clock setting bit field width. + */ +typedef enum _clock_mux +{ + kCLOCK_Pll3SwMux = CCM_TUPLE(CCSR, + CCM_CCSR_PLL3_SW_CLK_SEL_SHIFT, + CCM_CCSR_PLL3_SW_CLK_SEL_MASK, + CCM_NO_BUSY_WAIT), /*!< pll3_sw_clk mux name */ + + kCLOCK_PeriphMux = CCM_TUPLE(CBCDR, + CCM_CBCDR_PERIPH_CLK_SEL_SHIFT, + CCM_CBCDR_PERIPH_CLK_SEL_MASK, + CCM_CDHIPR_PERIPH_CLK_SEL_BUSY_SHIFT), /*!< periph mux name */ + kCLOCK_SemcAltMux = CCM_TUPLE(CBCDR, + CCM_CBCDR_SEMC_ALT_CLK_SEL_SHIFT, + CCM_CBCDR_SEMC_ALT_CLK_SEL_MASK, + CCM_NO_BUSY_WAIT), /*!< semc mux name */ + kCLOCK_SemcMux = CCM_TUPLE( + CBCDR, CCM_CBCDR_SEMC_CLK_SEL_SHIFT, CCM_CBCDR_SEMC_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), /*!< semc mux name */ + + kCLOCK_PrePeriphMux = CCM_TUPLE(CBCMR, + CCM_CBCMR_PRE_PERIPH_CLK_SEL_SHIFT, + CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK, + CCM_NO_BUSY_WAIT), /*!< pre-periph mux name */ + kCLOCK_TraceMux = CCM_TUPLE( + CBCMR, CCM_CBCMR_TRACE_CLK_SEL_SHIFT, CCM_CBCMR_TRACE_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), /*!< trace mux name */ + kCLOCK_PeriphClk2Mux = CCM_TUPLE(CBCMR, + CCM_CBCMR_PERIPH_CLK2_SEL_SHIFT, + CCM_CBCMR_PERIPH_CLK2_SEL_MASK, + CCM_NO_BUSY_WAIT), /*!< periph clock2 mux name */ + kCLOCK_LpspiMux = CCM_TUPLE( + CBCMR, CCM_CBCMR_LPSPI_CLK_SEL_SHIFT, CCM_CBCMR_LPSPI_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), /*!< lpspi mux name */ + + kCLOCK_FlexspiMux = CCM_TUPLE(CSCMR1, + CCM_CSCMR1_FLEXSPI_CLK_SEL_SHIFT, + CCM_CSCMR1_FLEXSPI_CLK_SEL_MASK, + CCM_NO_BUSY_WAIT), /*!< flexspi mux name */ + kCLOCK_Usdhc2Mux = CCM_TUPLE(CSCMR1, + CCM_CSCMR1_USDHC2_CLK_SEL_SHIFT, + CCM_CSCMR1_USDHC2_CLK_SEL_MASK, + CCM_NO_BUSY_WAIT), /*!< usdhc2 mux name */ + kCLOCK_Usdhc1Mux = CCM_TUPLE(CSCMR1, + CCM_CSCMR1_USDHC1_CLK_SEL_SHIFT, + CCM_CSCMR1_USDHC1_CLK_SEL_MASK, + CCM_NO_BUSY_WAIT), /*!< usdhc1 mux name */ + kCLOCK_Sai3Mux = CCM_TUPLE( + CSCMR1, CCM_CSCMR1_SAI3_CLK_SEL_SHIFT, CCM_CSCMR1_SAI3_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), /*!< sai3 mux name */ + kCLOCK_Sai2Mux = CCM_TUPLE( + CSCMR1, CCM_CSCMR1_SAI2_CLK_SEL_SHIFT, CCM_CSCMR1_SAI2_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), /*!< sai2 mux name */ + kCLOCK_Sai1Mux = CCM_TUPLE( + CSCMR1, CCM_CSCMR1_SAI1_CLK_SEL_SHIFT, CCM_CSCMR1_SAI1_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), /*!< sai1 mux name */ + kCLOCK_PerclkMux = CCM_TUPLE(CSCMR1, + CCM_CSCMR1_PERCLK_CLK_SEL_SHIFT, + CCM_CSCMR1_PERCLK_CLK_SEL_MASK, + CCM_NO_BUSY_WAIT), /*!< perclk mux name */ + + kCLOCK_Flexio2Mux = CCM_TUPLE(CSCMR2, + CCM_CSCMR2_FLEXIO2_CLK_SEL_SHIFT, + CCM_CSCMR2_FLEXIO2_CLK_SEL_MASK, + CCM_NO_BUSY_WAIT), /*!< flexio2 mux name */ + kCLOCK_CanMux = CCM_TUPLE( + CSCMR2, CCM_CSCMR2_CAN_CLK_SEL_SHIFT, CCM_CSCMR2_CAN_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), /*!< can mux name */ + + kCLOCK_UartMux = CCM_TUPLE( + CSCDR1, CCM_CSCDR1_UART_CLK_SEL_SHIFT, CCM_CSCDR1_UART_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), /*!< uart mux name */ + + kCLOCK_SpdifMux = CCM_TUPLE( + CDCDR, CCM_CDCDR_SPDIF0_CLK_SEL_SHIFT, CCM_CDCDR_SPDIF0_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), /*!< spdif mux name */ + kCLOCK_Flexio1Mux = CCM_TUPLE(CDCDR, + CCM_CDCDR_FLEXIO1_CLK_SEL_SHIFT, + CCM_CDCDR_FLEXIO1_CLK_SEL_MASK, + CCM_NO_BUSY_WAIT), /*!< flexio1 mux name */ + + kCLOCK_Lpi2cMux = CCM_TUPLE( + CSCDR2, CCM_CSCDR2_LPI2C_CLK_SEL_SHIFT, CCM_CSCDR2_LPI2C_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), /*!< lpi2c mux name */ + kCLOCK_LcdifPreMux = CCM_TUPLE(CSCDR2, + CCM_CSCDR2_LCDIF_PRE_CLK_SEL_SHIFT, + CCM_CSCDR2_LCDIF_PRE_CLK_SEL_MASK, + CCM_NO_BUSY_WAIT), /*!< lcdif pre mux name */ + + kCLOCK_CsiMux = CCM_TUPLE( + CSCDR3, CCM_CSCDR3_CSI_CLK_SEL_SHIFT, CCM_CSCDR3_CSI_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), /*!< csi mux name */ +} clock_mux_t; + +/*! + * @brief DIV control names for clock div setting. + * + * These constants define div control names for clock div setting.\n + * - 0:7: REG offset to CCM_BASE in bytes. + * - 8:15: Root clock setting bit field shift. + * - 16:31: Root clock setting bit field width. + */ +typedef enum _clock_div +{ + kCLOCK_ArmDiv = CCM_TUPLE( + CACRR, CCM_CACRR_ARM_PODF_SHIFT, CCM_CACRR_ARM_PODF_MASK, CCM_CDHIPR_ARM_PODF_BUSY_SHIFT), /*!< core div name */ + + kCLOCK_PeriphClk2Div = CCM_TUPLE(CBCDR, + CCM_CBCDR_PERIPH_CLK2_PODF_SHIFT, + CCM_CBCDR_PERIPH_CLK2_PODF_MASK, + CCM_NO_BUSY_WAIT), /*!< periph clock2 div name */ + kCLOCK_SemcDiv = CCM_TUPLE(CBCDR, + CCM_CBCDR_SEMC_PODF_SHIFT, + CCM_CBCDR_SEMC_PODF_MASK, + CCM_CDHIPR_SEMC_PODF_BUSY_SHIFT), /*!< semc div name */ + kCLOCK_AhbDiv = CCM_TUPLE( + CBCDR, CCM_CBCDR_AHB_PODF_SHIFT, CCM_CBCDR_AHB_PODF_MASK, CCM_CDHIPR_AHB_PODF_BUSY_SHIFT), /*!< ahb div name */ + kCLOCK_IpgDiv = + CCM_TUPLE(CBCDR, CCM_CBCDR_IPG_PODF_SHIFT, CCM_CBCDR_IPG_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< ipg div name */ + + kCLOCK_LpspiDiv = CCM_TUPLE( + CBCMR, CCM_CBCMR_LPSPI_PODF_SHIFT, CCM_CBCMR_LPSPI_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< lpspi div name */ + kCLOCK_LcdifDiv = CCM_TUPLE( + CBCMR, CCM_CBCMR_LCDIF_PODF_SHIFT, CCM_CBCMR_LCDIF_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< lcdif div name */ + + kCLOCK_FlexspiDiv = CCM_TUPLE( + CSCMR1, CCM_CSCMR1_FLEXSPI_PODF_SHIFT, CCM_CSCMR1_FLEXSPI_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< flexspi div name */ + kCLOCK_PerclkDiv = CCM_TUPLE( + CSCMR1, CCM_CSCMR1_PERCLK_PODF_SHIFT, CCM_CSCMR1_PERCLK_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< perclk div name */ + + kCLOCK_CanDiv = CCM_TUPLE( + CSCMR2, CCM_CSCMR2_CAN_CLK_PODF_SHIFT, CCM_CSCMR2_CAN_CLK_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< can div name */ + + kCLOCK_TraceDiv = CCM_TUPLE( + CSCDR1, CCM_CSCDR1_TRACE_PODF_SHIFT, CCM_CSCDR1_TRACE_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< trace div name */ + kCLOCK_Usdhc2Div = CCM_TUPLE( + CSCDR1, CCM_CSCDR1_USDHC2_PODF_SHIFT, CCM_CSCDR1_USDHC2_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< usdhc2 div name */ + kCLOCK_Usdhc1Div = CCM_TUPLE( + CSCDR1, CCM_CSCDR1_USDHC1_PODF_SHIFT, CCM_CSCDR1_USDHC1_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< usdhc1 div name */ + kCLOCK_UartDiv = CCM_TUPLE( + CSCDR1, CCM_CSCDR1_UART_CLK_PODF_SHIFT, CCM_CSCDR1_UART_CLK_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< uart div name */ + + kCLOCK_Flexio2Div = CCM_TUPLE(CS1CDR, + CCM_CS1CDR_FLEXIO2_CLK_PODF_SHIFT, + CCM_CS1CDR_FLEXIO2_CLK_PODF_MASK, + CCM_NO_BUSY_WAIT), /*!< flexio2 pre div name */ + kCLOCK_Sai3PreDiv = CCM_TUPLE(CS1CDR, + CCM_CS1CDR_SAI3_CLK_PRED_SHIFT, + CCM_CS1CDR_SAI3_CLK_PRED_MASK, + CCM_NO_BUSY_WAIT), /*!< sai3 pre div name */ + kCLOCK_Sai3Div = CCM_TUPLE( + CS1CDR, CCM_CS1CDR_SAI3_CLK_PODF_SHIFT, CCM_CS1CDR_SAI3_CLK_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< sai3 div name */ + kCLOCK_Flexio2PreDiv = CCM_TUPLE(CS1CDR, + CCM_CS1CDR_FLEXIO2_CLK_PRED_SHIFT, + CCM_CS1CDR_FLEXIO2_CLK_PRED_MASK, + CCM_NO_BUSY_WAIT), /*!< sai3 pre div name */ + kCLOCK_Sai1PreDiv = CCM_TUPLE(CS1CDR, + CCM_CS1CDR_SAI1_CLK_PRED_SHIFT, + CCM_CS1CDR_SAI1_CLK_PRED_MASK, + CCM_NO_BUSY_WAIT), /*!< sai1 pre div name */ + kCLOCK_Sai1Div = CCM_TUPLE( + CS1CDR, CCM_CS1CDR_SAI1_CLK_PODF_SHIFT, CCM_CS1CDR_SAI1_CLK_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< sai1 div name */ + + kCLOCK_Sai2PreDiv = CCM_TUPLE(CS2CDR, + CCM_CS2CDR_SAI2_CLK_PRED_SHIFT, + CCM_CS2CDR_SAI2_CLK_PRED_MASK, + CCM_NO_BUSY_WAIT), /*!< sai2 pre div name */ + kCLOCK_Sai2Div = CCM_TUPLE( + CS2CDR, CCM_CS2CDR_SAI2_CLK_PODF_SHIFT, CCM_CS2CDR_SAI2_CLK_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< sai2 div name */ + + kCLOCK_Spdif0PreDiv = CCM_TUPLE(CDCDR, + CCM_CDCDR_SPDIF0_CLK_PRED_SHIFT, + CCM_CDCDR_SPDIF0_CLK_PRED_MASK, + CCM_NO_BUSY_WAIT), /*!< spdif pre div name */ + kCLOCK_Spdif0Div = CCM_TUPLE(CDCDR, + CCM_CDCDR_SPDIF0_CLK_PODF_SHIFT, + CCM_CDCDR_SPDIF0_CLK_PODF_MASK, + CCM_NO_BUSY_WAIT), /*!< spdif div name */ + kCLOCK_Flexio1PreDiv = CCM_TUPLE(CDCDR, + CCM_CDCDR_FLEXIO1_CLK_PRED_SHIFT, + CCM_CDCDR_FLEXIO1_CLK_PRED_MASK, + CCM_NO_BUSY_WAIT), /*!< flexio1 pre div name */ + kCLOCK_Flexio1Div = CCM_TUPLE(CDCDR, + CCM_CDCDR_FLEXIO1_CLK_PODF_SHIFT, + CCM_CDCDR_FLEXIO1_CLK_PODF_MASK, + CCM_NO_BUSY_WAIT), /*!< flexio1 div name */ + + kCLOCK_Lpi2cDiv = CCM_TUPLE(CSCDR2, + CCM_CSCDR2_LPI2C_CLK_PODF_SHIFT, + CCM_CSCDR2_LPI2C_CLK_PODF_MASK, + CCM_NO_BUSY_WAIT), /*!< lpi2c div name */ + kCLOCK_LcdifPreDiv = CCM_TUPLE( + CSCDR2, CCM_CSCDR2_LCDIF_PRED_SHIFT, CCM_CSCDR2_LCDIF_PRED_MASK, CCM_NO_BUSY_WAIT), /*!< lcdif pre div name */ + + kCLOCK_CsiDiv = + CCM_TUPLE(CSCDR3, CCM_CSCDR3_CSI_PODF_SHIFT, CCM_CSCDR3_CSI_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< csi div name */ +} clock_div_t; + +/*! @brief USB clock source definition. */ +typedef enum _clock_usb_src +{ + kCLOCK_Usb480M = 0, /*!< Use 480M. */ + kCLOCK_UsbSrcUnused = 0xFFFFFFFFU, /*!< Used when the function does not + care the clock source. */ +} clock_usb_src_t; + +/*! @brief Source of the USB HS PHY. */ +typedef enum _clock_usb_phy_src +{ + kCLOCK_Usbphy480M = 0, /*!< Use 480M. */ +} clock_usb_phy_src_t; + +/*!@brief PLL clock source, bypass cloco source also */ +enum _clock_pll_clk_src +{ + kCLOCK_PllClkSrc24M = 0U, /*!< Pll clock source 24M */ + kCLOCK_PllSrcClkPN = 1U, /*!< Pll clock source CLK1_P and CLK1_N */ +}; + +/*! @brief PLL configuration for ARM */ +typedef struct _clock_arm_pll_config +{ + uint32_t loopDivider; /*!< PLL loop divider. Valid range for divider value: 54-108. Fout=Fin*loopDivider/2. */ + uint8_t src; /*!< Pll clock source, reference _clock_pll_clk_src */ +} clock_arm_pll_config_t; + +/*! @brief PLL configuration for USB */ +typedef struct _clock_usb_pll_config +{ + uint8_t loopDivider; /*!< PLL loop divider. + 0 - Fout=Fref*20; + 1 - Fout=Fref*22 */ + uint8_t src; /*!< Pll clock source, reference _clock_pll_clk_src */ + +} clock_usb_pll_config_t; + +/*! @brief PLL configuration for System */ +typedef struct _clock_sys_pll_config +{ + uint8_t loopDivider; /*!< PLL loop divider. Intended to be 1 (528M). + 0 - Fout=Fref*20; + 1 - Fout=Fref*22 */ + uint32_t numerator; /*!< 30 bit numerator of fractional loop divider.*/ + uint32_t denominator; /*!< 30 bit denominator of fractional loop divider */ + uint8_t src; /*!< Pll clock source, reference _clock_pll_clk_src */ + uint16_t ss_stop; /*!< Stop value to get frequency change. */ + uint8_t ss_enable; /*!< Enable spread spectrum modulation */ + uint16_t ss_step; /*!< Step value to get frequency change step. */ + +} clock_sys_pll_config_t; + +/*! @brief PLL configuration for AUDIO and VIDEO */ +typedef struct _clock_audio_pll_config +{ + uint8_t loopDivider; /*!< PLL loop divider. Valid range for DIV_SELECT divider value: 27~54. */ + uint8_t postDivider; /*!< Divider after the PLL, should only be 1, 2, 4, 8, 16. */ + uint32_t numerator; /*!< 30 bit numerator of fractional loop divider.*/ + uint32_t denominator; /*!< 30 bit denominator of fractional loop divider */ + uint8_t src; /*!< Pll clock source, reference _clock_pll_clk_src */ +} clock_audio_pll_config_t; + +/*! @brief PLL configuration for AUDIO and VIDEO */ +typedef struct _clock_video_pll_config +{ + uint8_t loopDivider; /*!< PLL loop divider. Valid range for DIV_SELECT divider value: 27~54. */ + uint8_t postDivider; /*!< Divider after the PLL, should only be 1, 2, 4, 8, 16. */ + uint32_t numerator; /*!< 30 bit numerator of fractional loop divider.*/ + uint32_t denominator; /*!< 30 bit denominator of fractional loop divider */ + uint8_t src; /*!< Pll clock source, reference _clock_pll_clk_src */ + +} clock_video_pll_config_t; + +/*! @brief PLL configuration for ENET */ +typedef struct _clock_enet_pll_config +{ + bool enableClkOutput; /*!< Power on and enable PLL clock output for ENET0 (ref_enetpll0). */ + + bool enableClkOutput25M; /*!< Power on and enable PLL clock output for ENET1 (ref_enetpll1). */ + uint8_t loopDivider; /*!< Controls the frequency of the ENET0 reference clock. + b00 25MHz + b01 50MHz + b10 100MHz (not 50% duty cycle) + b11 125MHz */ + uint8_t src; /*!< Pll clock source, reference _clock_pll_clk_src */ + +} clock_enet_pll_config_t; + +/*! @brief PLL name */ +typedef enum _clock_pll +{ + kCLOCK_PllArm = CCM_ANALOG_TUPLE(PLL_ARM, CCM_ANALOG_PLL_ARM_ENABLE_SHIFT), /*!< PLL ARM */ + kCLOCK_PllSys = CCM_ANALOG_TUPLE(PLL_SYS, CCM_ANALOG_PLL_SYS_ENABLE_SHIFT), /*!< PLL SYS */ + kCLOCK_PllUsb1 = CCM_ANALOG_TUPLE(PLL_USB1, CCM_ANALOG_PLL_USB1_ENABLE_SHIFT), /*!< PLL USB1 */ + kCLOCK_PllAudio = CCM_ANALOG_TUPLE(PLL_AUDIO, CCM_ANALOG_PLL_AUDIO_ENABLE_SHIFT), /*!< PLL Audio */ + kCLOCK_PllVideo = CCM_ANALOG_TUPLE(PLL_VIDEO, CCM_ANALOG_PLL_VIDEO_ENABLE_SHIFT), /*!< PLL Video */ + + kCLOCK_PllEnet = CCM_ANALOG_TUPLE(PLL_ENET, CCM_ANALOG_PLL_ENET_ENABLE_SHIFT), /*!< PLL Enet0 */ + + kCLOCK_PllEnet25M = CCM_ANALOG_TUPLE(PLL_ENET, CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_SHIFT), /*!< PLL Enet1 */ + + kCLOCK_PllUsb2 = CCM_ANALOG_TUPLE(PLL_USB2, CCM_ANALOG_PLL_USB2_ENABLE_SHIFT), /*!< PLL USB2 */ + +} clock_pll_t; + +/*! @brief PLL PFD name */ +typedef enum _clock_pfd +{ + kCLOCK_Pfd0 = 0U, /*!< PLL PFD0 */ + kCLOCK_Pfd1 = 1U, /*!< PLL PFD1 */ + kCLOCK_Pfd2 = 2U, /*!< PLL PFD2 */ + kCLOCK_Pfd3 = 3U, /*!< PLL PFD3 */ +} clock_pfd_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/*! + * @brief Set CCM MUX node to certain value. + * + * @param mux Which mux node to set, see \ref clock_mux_t. + * @param value Clock mux value to set, different mux has different value range. + */ +static inline void CLOCK_SetMux(clock_mux_t mux, uint32_t value) +{ + uint32_t busyShift; + + busyShift = CCM_TUPLE_BUSY_SHIFT(mux); + CCM_TUPLE_REG(CCM, mux) = (CCM_TUPLE_REG(CCM, mux) & (~CCM_TUPLE_MASK(mux))) | + (((uint32_t)((value) << CCM_TUPLE_SHIFT(mux))) & CCM_TUPLE_MASK(mux)); + + assert(busyShift <= CCM_NO_BUSY_WAIT); + + /* Clock switch need Handshake? */ + if (CCM_NO_BUSY_WAIT != busyShift) + { + /* Wait until CCM internal handshake finish. */ + while (CCM->CDHIPR & (1U << busyShift)) + { + } + } +} + +/*! + * @brief Get CCM MUX value. + * + * @param mux Which mux node to get, see \ref clock_mux_t. + * @return Clock mux value. + */ +static inline uint32_t CLOCK_GetMux(clock_mux_t mux) +{ + return (CCM_TUPLE_REG(CCM, mux) & CCM_TUPLE_MASK(mux)) >> CCM_TUPLE_SHIFT(mux); +} + +/*! + * @brief Set CCM DIV node to certain value. + * + * @param divider Which div node to set, see \ref clock_div_t. + * @param value Clock div value to set, different divider has different value range. + */ +static inline void CLOCK_SetDiv(clock_div_t divider, uint32_t value) +{ + uint32_t busyShift; + + busyShift = CCM_TUPLE_BUSY_SHIFT(divider); + CCM_TUPLE_REG(CCM, divider) = (CCM_TUPLE_REG(CCM, divider) & (~CCM_TUPLE_MASK(divider))) | + (((uint32_t)((value) << CCM_TUPLE_SHIFT(divider))) & CCM_TUPLE_MASK(divider)); + + assert(busyShift <= CCM_NO_BUSY_WAIT); + + /* Clock switch need Handshake? */ + if (CCM_NO_BUSY_WAIT != busyShift) + { + /* Wait until CCM internal handshake finish. */ + while (CCM->CDHIPR & (1U << busyShift)) + { + } + } +} + +/*! + * @brief Get CCM DIV node value. + * + * @param divider Which div node to get, see \ref clock_div_t. + */ +static inline uint32_t CLOCK_GetDiv(clock_div_t divider) +{ + return ((CCM_TUPLE_REG(CCM, divider) & CCM_TUPLE_MASK(divider)) >> CCM_TUPLE_SHIFT(divider)); +} + +/*! + * @brief Control the clock gate for specific IP. + * + * @param name Which clock to enable, see \ref clock_ip_name_t. + * @param value Clock gate value to set, see \ref clock_gate_value_t. + */ +static inline void CLOCK_ControlGate(clock_ip_name_t name, clock_gate_value_t value) +{ + uint32_t index = ((uint32_t)name) >> 8U; + uint32_t shift = ((uint32_t)name) & 0x1FU; + volatile uint32_t *reg; + + assert(index <= 6); + + reg = ((volatile uint32_t *)&CCM->CCGR0) + index; + *reg = ((*reg) & ~(3U << shift)) | (((uint32_t)value) << shift); +} + +/*! + * @brief Enable the clock for specific IP. + * + * @param name Which clock to enable, see \ref clock_ip_name_t. + */ +static inline void CLOCK_EnableClock(clock_ip_name_t name) +{ + CLOCK_ControlGate(name, kCLOCK_ClockNeededRunWait); +} + +/*! + * @brief Disable the clock for specific IP. + * + * @param name Which clock to disable, see \ref clock_ip_name_t. + */ +static inline void CLOCK_DisableClock(clock_ip_name_t name) +{ + CLOCK_ControlGate(name, kCLOCK_ClockNotNeeded); +} + +/*! + * @brief Setting the low power mode that system will enter on next assertion of dsm_request signal. + * + * @param mode Which mode to enter, see \ref clock_mode_t. + */ +static inline void CLOCK_SetMode(clock_mode_t mode) +{ + CCM->CLPCR = (CCM->CLPCR & ~CCM_CLPCR_LPM_MASK) | CCM_CLPCR_LPM((uint32_t)mode); +} + +/*! + * @brief Gets the OSC clock frequency. + * + * This function will return the external XTAL OSC frequency if it is selected as the source of OSC, + * otherwise internal 24MHz RC OSC frequency will be returned. + * + * @param osc OSC type to get frequency. + * + * @return Clock frequency; If the clock is invalid, returns 0. + */ +static inline uint32_t CLOCK_GetOscFreq(void) +{ + return (XTALOSC24M->LOWPWR_CTRL & XTALOSC24M_LOWPWR_CTRL_OSC_SEL_MASK) ? 24000000UL : g_xtalFreq; +} + +/*! + * @brief Gets the AHB clock frequency. + * + * @return The AHB clock frequency value in hertz. + */ +uint32_t CLOCK_GetAhbFreq(void); + +/*! + * @brief Gets the SEMC clock frequency. + * + * @return The SEMC clock frequency value in hertz. + */ +uint32_t CLOCK_GetSemcFreq(void); + +/*! + * @brief Gets the IPG clock frequency. + * + * @return The IPG clock frequency value in hertz. + */ +uint32_t CLOCK_GetIpgFreq(void); + +/*! + * @brief Gets the PER clock frequency. + * + * @return The PER clock frequency value in hertz. + */ +uint32_t CLOCK_GetPerFreq(void); + +/*! + * @brief Gets the clock frequency for a specific clock name. + * + * This function checks the current clock configurations and then calculates + * the clock frequency for a specific clock name defined in clock_name_t. + * + * @param clockName Clock names defined in clock_name_t + * @return Clock frequency value in hertz + */ +uint32_t CLOCK_GetFreq(clock_name_t name); + +/*! + * @brief Get the CCM CPU/core/system frequency. + * + * @return Clock frequency; If the clock is invalid, returns 0. + */ +static inline uint32_t CLOCK_GetCpuClkFreq(void) +{ + return CLOCK_GetFreq(kCLOCK_CpuClk); +} + +/*! + * @name OSC operations + * @{ + */ + +/*! + * @brief Initialize the external 24MHz clock. + * + * This function supports two modes: + * 1. Use external crystal oscillator. + * 2. Bypass the external crystal oscillator, using input source clock directly. + * + * After this function, please call @ref CLOCK_SetXtal0Freq to inform clock driver + * the external clock frequency. + * + * @param bypassXtalOsc Pass in true to bypass the external crystal oscillator. + * @note This device does not support bypass external crystal oscillator, so + * the input parameter should always be false. + */ +void CLOCK_InitExternalClk(bool bypassXtalOsc); + +/*! + * @brief Deinitialize the external 24MHz clock. + * + * This function disables the external 24MHz clock. + * + * After this function, please call @ref CLOCK_SetXtal0Freq to set external clock + * frequency to 0. + */ +void CLOCK_DeinitExternalClk(void); + +/*! + * @brief Switch the OSC. + * + * This function switches the OSC source for SoC. + * + * @param osc OSC source to switch to. + */ +void CLOCK_SwitchOsc(clock_osc_t osc); + +/*! + * @brief Gets the RTC clock frequency. + * + * @return Clock frequency; If the clock is invalid, returns 0. + */ +static inline uint32_t CLOCK_GetRtcFreq(void) +{ + return 32768U; +} + +/*! + * @brief Set the XTAL (24M OSC) frequency based on board setting. + * + * @param freq The XTAL input clock frequency in Hz. + */ +static inline void CLOCK_SetXtalFreq(uint32_t freq) +{ + g_xtalFreq = freq; +} + +/*! + * @brief Set the RTC XTAL (32K OSC) frequency based on board setting. + * + * @param freq The RTC XTAL input clock frequency in Hz. + */ +static inline void CLOCK_SetRtcXtalFreq(uint32_t freq) +{ + g_rtcXtalFreq = freq; +} + +/*! + * @brief Initialize the RC oscillator 24MHz clock. + */ +void CLOCK_InitRcOsc24M(void); + +/*! + * @brief Power down the RCOSC 24M clock. + */ +void CLOCK_DeinitRcOsc24M(void); +/* @} */ + +/*! @brief Enable USB HS clock. + * + * This function only enables the access to USB HS prepheral, upper layer + * should first call the @ref CLOCK_EnableUsbhs0PhyPllClock to enable the PHY + * clock to use USB HS. + * + * @param src USB HS does not care about the clock source, here must be @ref kCLOCK_UsbSrcUnused. + * @param freq USB HS does not care about the clock source, so this parameter is ignored. + * @retval true The clock is set successfully. + * @retval false The clock source is invalid to get proper USB HS clock. + */ +bool CLOCK_EnableUsbhs0Clock(clock_usb_src_t src, uint32_t freq); + +/*! @brief Enable USB HS clock. + * + * This function only enables the access to USB HS prepheral, upper layer + * should first call the @ref CLOCK_EnableUsbhs0PhyPllClock to enable the PHY + * clock to use USB HS. + * + * @param src USB HS does not care about the clock source, here must be @ref kCLOCK_UsbSrcUnused. + * @param freq USB HS does not care about the clock source, so this parameter is ignored. + * @retval true The clock is set successfully. + * @retval false The clock source is invalid to get proper USB HS clock. + */ +bool CLOCK_EnableUsbhs1Clock(clock_usb_src_t src, uint32_t freq); + +/*! @brief Disable USB HS PHY PLL clock. + * + * This function disables USB HS PHY PLL clock. + */ +void CLOCK_DisableUsbhs1PhyPllClock(void); + +/* @} */ + +/*! + * @name PLL/PFD operations + * @{ + */ +/*! + * @brief PLL bypass setting + * + * @param base CCM_ANALOG base pointer. + * @param pll PLL control name (see @ref ccm_analog_pll_control_t enumeration) + * @param bypass Bypass the PLL. + * - true: Bypass the PLL. + * - false:Not bypass the PLL. + */ +static inline void CLOCK_SetPllBypass(CCM_ANALOG_Type *base, clock_pll_t pll, bool bypass) +{ + if (bypass) + { + CCM_ANALOG_TUPLE_REG_OFF(base, pll, 4U) = 1U << CCM_ANALOG_PLL_BYPASS_SHIFT; + } + else + { + CCM_ANALOG_TUPLE_REG_OFF(base, pll, 8U) = 1U << CCM_ANALOG_PLL_BYPASS_SHIFT; + } +} + +/*! + * @brief Check if PLL is bypassed + * + * @param base CCM_ANALOG base pointer. + * @param pll PLL control name (see @ref ccm_analog_pll_control_t enumeration) + * @return PLL bypass status. + * - true: The PLL is bypassed. + * - false: The PLL is not bypassed. + */ +static inline bool CLOCK_IsPllBypassed(CCM_ANALOG_Type *base, clock_pll_t pll) +{ + return (bool)(CCM_ANALOG_TUPLE_REG(base, pll) & (1U << CCM_ANALOG_PLL_BYPASS_SHIFT)); +} + +/*! + * @brief Check if PLL is enabled + * + * @param base CCM_ANALOG base pointer. + * @param pll PLL control name (see @ref ccm_analog_pll_control_t enumeration) + * @return PLL bypass status. + * - true: The PLL is enabled. + * - false: The PLL is not enabled. + */ +static inline bool CLOCK_IsPllEnabled(CCM_ANALOG_Type *base, clock_pll_t pll) +{ + return (bool)(CCM_ANALOG_TUPLE_REG(base, pll) & (1U << CCM_ANALOG_TUPLE_SHIFT(pll))); +} + +/*! + * @brief PLL bypass clock source setting. + * Note: change the bypass clock source also change the pll reference clock source. + * + * @param base CCM_ANALOG base pointer. + * @param pll PLL control name (see @ref ccm_analog_pll_control_t enumeration) + * @param src Bypass clock source, reference _clock_pll_bypass_clk_src. + */ +static inline void CLOCK_SetPllBypassRefClkSrc(CCM_ANALOG_Type *base, clock_pll_t pll, uint32_t src) +{ + CCM_ANALOG_TUPLE_REG(base, pll) |= (CCM_ANALOG_TUPLE_REG(base, pll) & (~CCM_ANALOG_PLL_BYPASS_CLK_SRC_MASK)) | src; +} + +/*! + * @brief Get PLL bypass clock value, it is PLL reference clock actually. + * If CLOCK1_P,CLOCK1_N is choose as the pll bypass clock source, please implement the CLKPN_FREQ define, otherwise 0 + * will be returned. + * @param base CCM_ANALOG base pointer. + * @param pll PLL control name (see @ref ccm_analog_pll_control_t enumeration) + * @retval bypass reference clock frequency value. + */ +static inline uint32_t CLOCK_GetPllBypassRefClk(CCM_ANALOG_Type *base, clock_pll_t pll) +{ + return (((CCM_ANALOG_TUPLE_REG(base, pll) & CCM_ANALOG_PLL_BYPASS_CLK_SRC_MASK) >> + CCM_ANALOG_PLL_BYPASS_CLK_SRC_SHIFT) == kCLOCK_PllClkSrc24M) ? + CLOCK_GetOscFreq() : + CLKPN_FREQ; +} + +/*! + * @brief Initialize the ARM PLL. + * + * This function initialize the ARM PLL with specific settings + * + * @param config configuration to set to PLL. + */ +void CLOCK_InitArmPll(const clock_arm_pll_config_t *config); + +/*! + * @brief De-initialize the ARM PLL. + */ +void CLOCK_DeinitArmPll(void); + +/*! + * @brief Initialize the System PLL. + * + * This function initializes the System PLL with specific settings + * + * @param config Configuration to set to PLL. + */ +void CLOCK_InitSysPll(const clock_sys_pll_config_t *config); + +/*! + * @brief De-initialize the System PLL. + */ +void CLOCK_DeinitSysPll(void); + +/*! + * @brief Initialize the USB1 PLL. + * + * This function initializes the USB1 PLL with specific settings + * + * @param config Configuration to set to PLL. + */ +void CLOCK_InitUsb1Pll(const clock_usb_pll_config_t *config); + +/*! + * @brief Deinitialize the USB1 PLL. + */ +void CLOCK_DeinitUsb1Pll(void); + +/*! + * @brief Initialize the USB2 PLL. + * + * This function initializes the USB2 PLL with specific settings + * + * @param config Configuration to set to PLL. + */ +void CLOCK_InitUsb2Pll(const clock_usb_pll_config_t *config); + +/*! + * @brief Deinitialize the USB2 PLL. + */ +void CLOCK_DeinitUsb2Pll(void); + +/*! + * @brief Initializes the Audio PLL. + * + * This function initializes the Audio PLL with specific settings + * + * @param config Configuration to set to PLL. + */ +void CLOCK_InitAudioPll(const clock_audio_pll_config_t *config); + +/*! + * @brief De-initialize the Audio PLL. + */ +void CLOCK_DeinitAudioPll(void); + +/*! + * @brief Initialize the video PLL. + * + * This function configures the Video PLL with specific settings + * + * @param config configuration to set to PLL. + */ +void CLOCK_InitVideoPll(const clock_video_pll_config_t *config); + +/*! + * @brief De-initialize the Video PLL. + */ +void CLOCK_DeinitVideoPll(void); +/*! + * @brief Initialize the ENET PLL. + * + * This function initializes the ENET PLL with specific settings. + * + * @param config Configuration to set to PLL. + */ +void CLOCK_InitEnetPll(const clock_enet_pll_config_t *config); + +/*! + * @brief Deinitialize the ENET PLL. + * + * This function disables the ENET PLL. + */ +void CLOCK_DeinitEnetPll(void); + +/*! + * @brief Get current PLL output frequency. + * + * This function get current output frequency of specific PLL + * + * @param pll pll name to get frequency. + * @return The PLL output frequency in hertz. + */ +uint32_t CLOCK_GetPllFreq(clock_pll_t pll); + +/*! + * @brief Initialize the System PLL PFD. + * + * This function initializes the System PLL PFD. During new value setting, + * the clock output is disabled to prevent glitch. + * + * @param pfd Which PFD clock to enable. + * @param pfdFrac The PFD FRAC value. + * @note It is recommended that PFD settings are kept between 12-35. + */ +void CLOCK_InitSysPfd(clock_pfd_t pfd, uint8_t pfdFrac); + +/*! + * @brief De-initialize the System PLL PFD. + * + * This function disables the System PLL PFD. + * + * @param pfd Which PFD clock to disable. + */ +void CLOCK_DeinitSysPfd(clock_pfd_t pfd); + +/*! + * @brief Initialize the USB1 PLL PFD. + * + * This function initializes the USB1 PLL PFD. During new value setting, + * the clock output is disabled to prevent glitch. + * + * @param pfd Which PFD clock to enable. + * @param pfdFrac The PFD FRAC value. + * @note It is recommended that PFD settings are kept between 12-35. + */ +void CLOCK_InitUsb1Pfd(clock_pfd_t pfd, uint8_t pfdFrac); + +/*! + * @brief De-initialize the USB1 PLL PFD. + * + * This function disables the USB1 PLL PFD. + * + * @param pfd Which PFD clock to disable. + */ +void CLOCK_DeinitUsb1Pfd(clock_pfd_t pfd); + +/*! + * @brief Get current System PLL PFD output frequency. + * + * This function get current output frequency of specific System PLL PFD + * + * @param pfd pfd name to get frequency. + * @return The PFD output frequency in hertz. + */ +uint32_t CLOCK_GetSysPfdFreq(clock_pfd_t pfd); + +/*! + * @brief Get current USB1 PLL PFD output frequency. + * + * This function get current output frequency of specific USB1 PLL PFD + * + * @param pfd pfd name to get frequency. + * @return The PFD output frequency in hertz. + */ +uint32_t CLOCK_GetUsb1PfdFreq(clock_pfd_t pfd); + +/*! @brief Enable USB HS PHY PLL clock. + * + * This function enables the internal 480MHz USB PHY PLL clock. + * + * @param src USB HS PHY PLL clock source. + * @param freq The frequency specified by src. + * @retval true The clock is set successfully. + * @retval false The clock source is invalid to get proper USB HS clock. + */ +bool CLOCK_EnableUsbhs0PhyPllClock(clock_usb_phy_src_t src, uint32_t freq); + +/*! @brief Disable USB HS PHY PLL clock. + * + * This function disables USB HS PHY PLL clock. + */ +void CLOCK_DisableUsbhs0PhyPllClock(void); + +/*! @brief Enable USB HS PHY PLL clock. + * + * This function enables the internal 480MHz USB PHY PLL clock. + * + * @param src USB HS PHY PLL clock source. + * @param freq The frequency specified by src. + * @retval true The clock is set successfully. + * @retval false The clock source is invalid to get proper USB HS clock. + */ +bool CLOCK_EnableUsbhs1PhyPllClock(clock_usb_phy_src_t src, uint32_t freq); + +/*! @brief Disable USB HS PHY PLL clock. + * + * This function disables USB HS PHY PLL clock. + */ +void CLOCK_DisableUsbhs1PhyPllClock(void); + +/* @} */ + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +/*! @} */ + +#endif /* _FSL_CLOCK_H_ */ diff --git a/ext/hal/nxp/mcux/devices/MIMXRT1051/fsl_device_registers.h b/ext/hal/nxp/mcux/devices/MIMXRT1051/fsl_device_registers.h index 867ce7c8440..5dfed3ea95f 100644 --- a/ext/hal/nxp/mcux/devices/MIMXRT1051/fsl_device_registers.h +++ b/ext/hal/nxp/mcux/devices/MIMXRT1051/fsl_device_registers.h @@ -1,30 +1,9 @@ /* * Copyright 2014-2016 Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * Copyright 2016-2018 NXP + * All rights reserved. * - * 1. Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * 3. Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * SPDX-License-Identifier: BSD-3-Clause * */ @@ -36,7 +15,7 @@ * * The CPU macro should be declared in the project or makefile. */ -#if (defined(CPU_MIMXRT1051CVL5A) || defined(CPU_MIMXRT1051DVL6A)) +#if (defined(CPU_MIMXRT1051CVJ5B) || defined(CPU_MIMXRT1051CVL5B) || defined(CPU_MIMXRT1051DVL6B)) #define MIMXRT1051_SERIES diff --git a/ext/hal/nxp/mcux/devices/MIMXRT1051/fsl_iomuxc.h b/ext/hal/nxp/mcux/devices/MIMXRT1051/fsl_iomuxc.h new file mode 100644 index 00000000000..4477c44887f --- /dev/null +++ b/ext/hal/nxp/mcux/devices/MIMXRT1051/fsl_iomuxc.h @@ -0,0 +1,1244 @@ +/* + * Copyright 2016 Freescale Semiconductor, Inc. + * Copyright 2016-2018 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _FSL_IOMUXC_H_ +#define _FSL_IOMUXC_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup iomuxc_driver + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.iomuxc" +#endif + +/*! @name Driver version */ +/*@{*/ +/*! @brief IOMUXC driver version 2.0.0. */ +#define FSL_IOMUXC_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) +/*@}*/ + +/*! @name Pin function ID */ +/*@{*/ +/*! @brief The pin function ID is a tuple of */ +#define IOMUXC_SNVS_WAKEUP_GPIO5_IO00 0x400A8000U, 0x5U, 0, 0, 0x400A8018U +#define IOMUXC_SNVS_WAKEUP_NMI_GLUE_NMI 0x400A8000U, 0x7U, 0x401F8568U, 0x1U, 0x400A8018U + +#define IOMUXC_SNVS_PMIC_ON_REQ_SNVS_LP_PMIC_ON_REQ 0x400A8004U, 0x0U, 0, 0, 0x400A801CU +#define IOMUXC_SNVS_PMIC_ON_REQ_GPIO5_IO01 0x400A8004U, 0x5U, 0, 0, 0x400A801CU + +#define IOMUXC_SNVS_PMIC_STBY_REQ_CCM_PMIC_VSTBY_REQ 0x400A8008U, 0x0U, 0, 0, 0x400A8020U +#define IOMUXC_SNVS_PMIC_STBY_REQ_GPIO5_IO02 0x400A8008U, 0x5U, 0, 0, 0x400A8020U + +#define IOMUXC_SNVS_TEST_MODE 0, 0, 0, 0, 0x400A800CU + +#define IOMUXC_SNVS_POR_B 0, 0, 0, 0, 0x400A8010U + +#define IOMUXC_SNVS_ONOFF 0, 0, 0, 0, 0x400A8014U + +#define IOMUXC_GPIO_EMC_00_SEMC_DATA00 0x401F8014U, 0x0U, 0, 0, 0x401F8204U +#define IOMUXC_GPIO_EMC_00_FLEXPWM4_PWMA00 0x401F8014U, 0x1U, 0x401F8494U, 0x0U, 0x401F8204U +#define IOMUXC_GPIO_EMC_00_LPSPI2_SCK 0x401F8014U, 0x2U, 0x401F8500U, 0x1U, 0x401F8204U +#define IOMUXC_GPIO_EMC_00_XBAR1_XBAR_IN02 0x401F8014U, 0x3U, 0x401F860CU, 0x0U, 0x401F8204U +#define IOMUXC_GPIO_EMC_00_FLEXIO1_FLEXIO00 0x401F8014U, 0x4U, 0, 0, 0x401F8204U +#define IOMUXC_GPIO_EMC_00_GPIO4_IO00 0x401F8014U, 0x5U, 0, 0, 0x401F8204U + +#define IOMUXC_GPIO_EMC_01_SEMC_DATA01 0x401F8018U, 0x0U, 0, 0, 0x401F8208U +#define IOMUXC_GPIO_EMC_01_FLEXPWM4_PWMB00 0x401F8018U, 0x1U, 0, 0, 0x401F8208U +#define IOMUXC_GPIO_EMC_01_LPSPI2_PCS0 0x401F8018U, 0x2U, 0x401F84FCU, 0x1U, 0x401F8208U +#define IOMUXC_GPIO_EMC_01_XBAR1_IN03 0x401F8018U, 0x3U, 0x401F8610U, 0x0U, 0x401F8208U +#define IOMUXC_GPIO_EMC_01_FLEXIO1_FLEXIO01 0x401F8018U, 0x4U, 0, 0, 0x401F8208U +#define IOMUXC_GPIO_EMC_01_GPIO4_IO01 0x401F8018U, 0x5U, 0, 0, 0x401F8208U + +#define IOMUXC_GPIO_EMC_02_SEMC_DATA02 0x401F801CU, 0x0U, 0, 0, 0x401F820CU +#define IOMUXC_GPIO_EMC_02_FLEXPWM4_PWMA01 0x401F801CU, 0x1U, 0x401F8498U, 0x0U, 0x401F820CU +#define IOMUXC_GPIO_EMC_02_LPSPI2_SDO 0x401F801CU, 0x2U, 0x401F8508U, 0x1U, 0x401F820CU +#define IOMUXC_GPIO_EMC_02_XBAR1_INOUT04 0x401F801CU, 0x3U, 0x401F8614U, 0x0U, 0x401F820CU +#define IOMUXC_GPIO_EMC_02_FLEXIO1_FLEXIO02 0x401F801CU, 0x4U, 0, 0, 0x401F820CU +#define IOMUXC_GPIO_EMC_02_GPIO4_IO02 0x401F801CU, 0x5U, 0, 0, 0x401F820CU + +#define IOMUXC_GPIO_EMC_03_SEMC_DATA03 0x401F8020U, 0x0U, 0, 0, 0x401F8210U +#define IOMUXC_GPIO_EMC_03_FLEXPWM4_PWMB01 0x401F8020U, 0x1U, 0, 0, 0x401F8210U +#define IOMUXC_GPIO_EMC_03_LPSPI2_SDI 0x401F8020U, 0x2U, 0x401F8504U, 0x1U, 0x401F8210U +#define IOMUXC_GPIO_EMC_03_XBAR1_INOUT05 0x401F8020U, 0x3U, 0x401F8618U, 0x0U, 0x401F8210U +#define IOMUXC_GPIO_EMC_03_FLEXIO1_FLEXIO03 0x401F8020U, 0x4U, 0, 0, 0x401F8210U +#define IOMUXC_GPIO_EMC_03_GPIO4_IO03 0x401F8020U, 0x5U, 0, 0, 0x401F8210U + +#define IOMUXC_GPIO_EMC_04_SEMC_DATA04 0x401F8024U, 0x0U, 0, 0, 0x401F8214U +#define IOMUXC_GPIO_EMC_04_FLEXPWM4_PWMA02 0x401F8024U, 0x1U, 0x401F849CU, 0x0U, 0x401F8214U +#define IOMUXC_GPIO_EMC_04_SAI2_TX_DATA 0x401F8024U, 0x2U, 0, 0, 0x401F8214U +#define IOMUXC_GPIO_EMC_04_XBAR1_INOUT06 0x401F8024U, 0x3U, 0x401F861CU, 0x0U, 0x401F8214U +#define IOMUXC_GPIO_EMC_04_FLEXIO1_FLEXIO04 0x401F8024U, 0x4U, 0, 0, 0x401F8214U +#define IOMUXC_GPIO_EMC_04_GPIO4_IO04 0x401F8024U, 0x5U, 0, 0, 0x401F8214U + +#define IOMUXC_GPIO_EMC_05_SEMC_DATA05 0x401F8028U, 0x0U, 0, 0, 0x401F8218U +#define IOMUXC_GPIO_EMC_05_FLEXPWM4_PWMB02 0x401F8028U, 0x1U, 0, 0, 0x401F8218U +#define IOMUXC_GPIO_EMC_05_SAI2_TX_SYNC 0x401F8028U, 0x2U, 0x401F85C4U, 0x0U, 0x401F8218U +#define IOMUXC_GPIO_EMC_05_XBAR1_INOUT07 0x401F8028U, 0x3U, 0x401F8620U, 0x0U, 0x401F8218U +#define IOMUXC_GPIO_EMC_05_FLEXIO1_FLEXIO05 0x401F8028U, 0x4U, 0, 0, 0x401F8218U +#define IOMUXC_GPIO_EMC_05_GPIO4_IO05 0x401F8028U, 0x5U, 0, 0, 0x401F8218U + +#define IOMUXC_GPIO_EMC_06_SEMC_DATA06 0x401F802CU, 0x0U, 0, 0, 0x401F821CU +#define IOMUXC_GPIO_EMC_06_FLEXPWM2_PWMA00 0x401F802CU, 0x1U, 0x401F8478U, 0x0U, 0x401F821CU +#define IOMUXC_GPIO_EMC_06_SAI2_TX_BCLK 0x401F802CU, 0x2U, 0x401F85C0U, 0x0U, 0x401F821CU +#define IOMUXC_GPIO_EMC_06_XBAR1_INOUT08 0x401F802CU, 0x3U, 0x401F8624U, 0x0U, 0x401F821CU +#define IOMUXC_GPIO_EMC_06_FLEXIO1_FLEXIO06 0x401F802CU, 0x4U, 0, 0, 0x401F821CU +#define IOMUXC_GPIO_EMC_06_GPIO4_IO06 0x401F802CU, 0x5U, 0, 0, 0x401F821CU + +#define IOMUXC_GPIO_EMC_07_SEMC_DATA07 0x401F8030U, 0x0U, 0, 0, 0x401F8220U +#define IOMUXC_GPIO_EMC_07_FLEXPWM2_PWMB00 0x401F8030U, 0x1U, 0x401F8488U, 0x0U, 0x401F8220U +#define IOMUXC_GPIO_EMC_07_SAI2_MCLK 0x401F8030U, 0x2U, 0x401F85B0U, 0x0U, 0x401F8220U +#define IOMUXC_GPIO_EMC_07_XBAR1_INOUT09 0x401F8030U, 0x3U, 0x401F8628U, 0x0U, 0x401F8220U +#define IOMUXC_GPIO_EMC_07_FLEXIO1_FLEXIO07 0x401F8030U, 0x4U, 0, 0, 0x401F8220U +#define IOMUXC_GPIO_EMC_07_GPIO4_IO07 0x401F8030U, 0x5U, 0, 0, 0x401F8220U + +#define IOMUXC_GPIO_EMC_08_SEMC_DM00 0x401F8034U, 0x0U, 0, 0, 0x401F8224U +#define IOMUXC_GPIO_EMC_08_FLEXPWM2_PWMA01 0x401F8034U, 0x1U, 0x401F847CU, 0x0U, 0x401F8224U +#define IOMUXC_GPIO_EMC_08_SAI2_RX_DATA 0x401F8034U, 0x2U, 0x401F85B8U, 0x0U, 0x401F8224U +#define IOMUXC_GPIO_EMC_08_XBAR1_INOUT17 0x401F8034U, 0x3U, 0x401F862CU, 0x0U, 0x401F8224U +#define IOMUXC_GPIO_EMC_08_FLEXIO1_FLEXIO08 0x401F8034U, 0x4U, 0, 0, 0x401F8224U +#define IOMUXC_GPIO_EMC_08_GPIO4_IO08 0x401F8034U, 0x5U, 0, 0, 0x401F8224U + +#define IOMUXC_GPIO_EMC_09_SEMC_ADDR00 0x401F8038U, 0x0U, 0, 0, 0x401F8228U +#define IOMUXC_GPIO_EMC_09_FLEXPWM2_PWMB01 0x401F8038U, 0x1U, 0x401F848CU, 0x0U, 0x401F8228U +#define IOMUXC_GPIO_EMC_09_SAI2_RX_SYNC 0x401F8038U, 0x2U, 0x401F85BCU, 0x0U, 0x401F8228U +#define IOMUXC_GPIO_EMC_09_FLEXCAN2_TX 0x401F8038U, 0x3U, 0, 0, 0x401F8228U +#define IOMUXC_GPIO_EMC_09_FLEXIO1_FLEXIO09 0x401F8038U, 0x4U, 0, 0, 0x401F8228U +#define IOMUXC_GPIO_EMC_09_GPIO4_IO09 0x401F8038U, 0x5U, 0, 0, 0x401F8228U + +#define IOMUXC_GPIO_EMC_10_SEMC_ADDR01 0x401F803CU, 0x0U, 0, 0, 0x401F822CU +#define IOMUXC_GPIO_EMC_10_FLEXPWM2_PWMA02 0x401F803CU, 0x1U, 0x401F8480U, 0x0U, 0x401F822CU +#define IOMUXC_GPIO_EMC_10_SAI2_RX_BCLK 0x401F803CU, 0x2U, 0x401F85B4U, 0x0U, 0x401F822CU +#define IOMUXC_GPIO_EMC_10_FLEXCAN2_RX 0x401F803CU, 0x3U, 0x401F8450U, 0x0U, 0x401F822CU +#define IOMUXC_GPIO_EMC_10_FLEXIO1_FLEXIO10 0x401F803CU, 0x4U, 0, 0, 0x401F822CU +#define IOMUXC_GPIO_EMC_10_GPIO4_IO10 0x401F803CU, 0x5U, 0, 0, 0x401F822CU + +#define IOMUXC_GPIO_EMC_11_SEMC_ADDR02 0x401F8040U, 0x0U, 0, 0, 0x401F8230U +#define IOMUXC_GPIO_EMC_11_FLEXPWM2_PWMB02 0x401F8040U, 0x1U, 0x401F8490U, 0x0U, 0x401F8230U +#define IOMUXC_GPIO_EMC_11_LPI2C4_SDA 0x401F8040U, 0x2U, 0x401F84E8U, 0x0U, 0x401F8230U +#define IOMUXC_GPIO_EMC_11_USDHC2_RESET_B 0x401F8040U, 0x3U, 0, 0, 0x401F8230U +#define IOMUXC_GPIO_EMC_11_FLEXIO1_FLEXIO11 0x401F8040U, 0x4U, 0, 0, 0x401F8230U +#define IOMUXC_GPIO_EMC_11_GPIO4_IO11 0x401F8040U, 0x5U, 0, 0, 0x401F8230U + +#define IOMUXC_GPIO_EMC_12_SEMC_ADDR03 0x401F8044U, 0x0U, 0, 0, 0x401F8234U +#define IOMUXC_GPIO_EMC_12_XBAR1_IN24 0x401F8044U, 0x1U, 0x401F8640U, 0x0U, 0x401F8234U +#define IOMUXC_GPIO_EMC_12_LPI2C4_SCL 0x401F8044U, 0x2U, 0x401F84E4U, 0x0U, 0x401F8234U +#define IOMUXC_GPIO_EMC_12_USDHC1_WP 0x401F8044U, 0x3U, 0x401F85D8U, 0x0U, 0x401F8234U +#define IOMUXC_GPIO_EMC_12_FLEXPWM1_PWMA03 0x401F8044U, 0x4U, 0x401F8454U, 0x1U, 0x401F8234U +#define IOMUXC_GPIO_EMC_12_GPIO4_IO12 0x401F8044U, 0x5U, 0, 0, 0x401F8234U + +#define IOMUXC_GPIO_EMC_13_SEMC_ADDR04 0x401F8048U, 0x0U, 0, 0, 0x401F8238U +#define IOMUXC_GPIO_EMC_13_XBAR1_IN25 0x401F8048U, 0x1U, 0x401F8650U, 0x1U, 0x401F8238U +#define IOMUXC_GPIO_EMC_13_LPUART3_TX 0x401F8048U, 0x2U, 0x401F853CU, 0x1U, 0x401F8238U +#define IOMUXC_GPIO_EMC_13_MQS_RIGHT 0x401F8048U, 0x3U, 0, 0, 0x401F8238U +#define IOMUXC_GPIO_EMC_13_FLEXPWM1_PWMB03 0x401F8048U, 0x4U, 0x401F8464U, 0x1U, 0x401F8238U +#define IOMUXC_GPIO_EMC_13_GPIO4_IO13 0x401F8048U, 0x5U, 0, 0, 0x401F8238U + +#define IOMUXC_GPIO_EMC_14_SEMC_ADDR05 0x401F804CU, 0x0U, 0, 0, 0x401F823CU +#define IOMUXC_GPIO_EMC_14_XBAR1_INOUT19 0x401F804CU, 0x1U, 0x401F8654U, 0x0U, 0x401F823CU +#define IOMUXC_GPIO_EMC_14_LPUART3_RX 0x401F804CU, 0x2U, 0x401F8538U, 0x1U, 0x401F823CU +#define IOMUXC_GPIO_EMC_14_MQS_LEFT 0x401F804CU, 0x3U, 0, 0, 0x401F823CU +#define IOMUXC_GPIO_EMC_14_LPSPI2_PCS1 0x401F804CU, 0x4U, 0, 0, 0x401F823CU +#define IOMUXC_GPIO_EMC_14_GPIO4_IO14 0x401F804CU, 0x5U, 0, 0, 0x401F823CU + +#define IOMUXC_GPIO_EMC_15_SEMC_ADDR06 0x401F8050U, 0x0U, 0, 0, 0x401F8240U +#define IOMUXC_GPIO_EMC_15_XBAR1_IN20 0x401F8050U, 0x1U, 0x401F8634U, 0x0U, 0x401F8240U +#define IOMUXC_GPIO_EMC_15_LPUART3_CTS_B 0x401F8050U, 0x2U, 0x401F8534U, 0x0U, 0x401F8240U +#define IOMUXC_GPIO_EMC_15_SPDIF_OUT 0x401F8050U, 0x3U, 0, 0, 0x401F8240U +#define IOMUXC_GPIO_EMC_15_QTIMER3_TIMER0 0x401F8050U, 0x4U, 0x401F857CU, 0x0U, 0x401F8240U +#define IOMUXC_GPIO_EMC_15_GPIO4_IO15 0x401F8050U, 0x5U, 0, 0, 0x401F8240U + +#define IOMUXC_GPIO_EMC_16_SEMC_ADDR07 0x401F8054U, 0x0U, 0, 0, 0x401F8244U +#define IOMUXC_GPIO_EMC_16_XBAR1_IN21 0x401F8054U, 0x1U, 0x401F8658U, 0x0U, 0x401F8244U +#define IOMUXC_GPIO_EMC_16_LPUART3_RTS_B 0x401F8054U, 0x2U, 0, 0, 0x401F8244U +#define IOMUXC_GPIO_EMC_16_SPDIF_IN 0x401F8054U, 0x3U, 0x401F85C8U, 0x1U, 0x401F8244U +#define IOMUXC_GPIO_EMC_16_QTIMER3_TIMER1 0x401F8054U, 0x4U, 0x401F8580U, 0x1U, 0x401F8244U +#define IOMUXC_GPIO_EMC_16_GPIO4_IO16 0x401F8054U, 0x5U, 0, 0, 0x401F8244U + +#define IOMUXC_GPIO_EMC_17_SEMC_ADDR08 0x401F8058U, 0x0U, 0, 0, 0x401F8248U +#define IOMUXC_GPIO_EMC_17_FLEXPWM4_PWMA03 0x401F8058U, 0x1U, 0x401F84A0U, 0x0U, 0x401F8248U +#define IOMUXC_GPIO_EMC_17_LPUART4_CTS_B 0x401F8058U, 0x2U, 0, 0, 0x401F8248U +#define IOMUXC_GPIO_EMC_17_FLEXCAN1_TX 0x401F8058U, 0x3U, 0, 0, 0x401F8248U +#define IOMUXC_GPIO_EMC_17_QTIMER3_TIMER2 0x401F8058U, 0x4U, 0x401F8584U, 0x0U, 0x401F8248U +#define IOMUXC_GPIO_EMC_17_GPIO4_IO17 0x401F8058U, 0x5U, 0, 0, 0x401F8248U + +#define IOMUXC_GPIO_EMC_18_SEMC_ADDR09 0x401F805CU, 0x0U, 0, 0, 0x401F824CU +#define IOMUXC_GPIO_EMC_18_FLEXPWM4_PWMB03 0x401F805CU, 0x1U, 0, 0, 0x401F824CU +#define IOMUXC_GPIO_EMC_18_LPUART4_RTS_B 0x401F805CU, 0x2U, 0, 0, 0x401F824CU +#define IOMUXC_GPIO_EMC_18_FLEXCAN1_RX 0x401F805CU, 0x3U, 0x401F844CU, 0x1U, 0x401F824CU +#define IOMUXC_GPIO_EMC_18_QTIMER3_TIMER3 0x401F805CU, 0x4U, 0x401F8588U, 0x0U, 0x401F824CU +#define IOMUXC_GPIO_EMC_18_GPIO4_IO18 0x401F805CU, 0x5U, 0, 0, 0x401F824CU +#define IOMUXC_GPIO_EMC_18_SNVS_VIO_5_CTL 0x401F805CU, 0x6U, 0, 0, 0x401F824CU + +#define IOMUXC_GPIO_EMC_19_SEMC_ADDR11 0x401F8060U, 0x0U, 0, 0, 0x401F8250U +#define IOMUXC_GPIO_EMC_19_FLEXPWM2_PWMA03 0x401F8060U, 0x1U, 0x401F8474U, 0x1U, 0x401F8250U +#define IOMUXC_GPIO_EMC_19_LPUART4_TX 0x401F8060U, 0x2U, 0x401F8544U, 0x1U, 0x401F8250U +#define IOMUXC_GPIO_EMC_19_ENET_RDATA01 0x401F8060U, 0x3U, 0x401F8438U, 0x0U, 0x401F8250U +#define IOMUXC_GPIO_EMC_19_QTIMER2_TIMER0 0x401F8060U, 0x4U, 0x401F856CU, 0x0U, 0x401F8250U +#define IOMUXC_GPIO_EMC_19_GPIO4_IO19 0x401F8060U, 0x5U, 0, 0, 0x401F8250U +#define IOMUXC_GPIO_EMC_19_SNVS_VIO_5 0x401F8060U, 0x6U, 0, 0, 0x401F8250U + +#define IOMUXC_GPIO_EMC_20_SEMC_ADDR12 0x401F8064U, 0x0U, 0, 0, 0x401F8254U +#define IOMUXC_GPIO_EMC_20_FLEXPWM2_PWMB03 0x401F8064U, 0x1U, 0x401F8484U, 0x1U, 0x401F8254U +#define IOMUXC_GPIO_EMC_20_LPUART4_RX 0x401F8064U, 0x2U, 0x401F8540U, 0x1U, 0x401F8254U +#define IOMUXC_GPIO_EMC_20_ENET_RDATA00 0x401F8064U, 0x3U, 0x401F8434U, 0x0U, 0x401F8254U +#define IOMUXC_GPIO_EMC_20_QTIMER2_TIMER1 0x401F8064U, 0x4U, 0x401F8570U, 0x0U, 0x401F8254U +#define IOMUXC_GPIO_EMC_20_GPIO4_IO20 0x401F8064U, 0x5U, 0, 0, 0x401F8254U + +#define IOMUXC_GPIO_EMC_21_SEMC_BA0 0x401F8068U, 0x0U, 0, 0, 0x401F8258U +#define IOMUXC_GPIO_EMC_21_FLEXPWM3_PWMA03 0x401F8068U, 0x1U, 0, 0, 0x401F8258U +#define IOMUXC_GPIO_EMC_21_LPI2C3_SDA 0x401F8068U, 0x2U, 0x401F84E0U, 0x0U, 0x401F8258U +#define IOMUXC_GPIO_EMC_21_ENET_TDATA01 0x401F8068U, 0x3U, 0, 0, 0x401F8258U +#define IOMUXC_GPIO_EMC_21_QTIMER2_TIMER2 0x401F8068U, 0x4U, 0x401F8574U, 0x0U, 0x401F8258U +#define IOMUXC_GPIO_EMC_21_GPIO4_IO21 0x401F8068U, 0x5U, 0, 0, 0x401F8258U + +#define IOMUXC_GPIO_EMC_22_SEMC_BA1 0x401F806CU, 0x0U, 0, 0, 0x401F825CU +#define IOMUXC_GPIO_EMC_22_FLEXPWM3_PWMB03 0x401F806CU, 0x1U, 0, 0, 0x401F825CU +#define IOMUXC_GPIO_EMC_22_LPI2C3_SCL 0x401F806CU, 0x2U, 0x401F84DCU, 0x0U, 0x401F825CU +#define IOMUXC_GPIO_EMC_22_ENET_TDATA00 0x401F806CU, 0x3U, 0, 0, 0x401F825CU +#define IOMUXC_GPIO_EMC_22_QTIMER2_TIMER3 0x401F806CU, 0x4U, 0x401F8578U, 0x0U, 0x401F825CU +#define IOMUXC_GPIO_EMC_22_GPIO4_IO22 0x401F806CU, 0x5U, 0, 0, 0x401F825CU + +#define IOMUXC_GPIO_EMC_23_SEMC_ADDR10 0x401F8070U, 0x0U, 0, 0, 0x401F8260U +#define IOMUXC_GPIO_EMC_23_FLEXPWM1_PWMA00 0x401F8070U, 0x1U, 0x401F8458U, 0x0U, 0x401F8260U +#define IOMUXC_GPIO_EMC_23_LPUART5_TX 0x401F8070U, 0x2U, 0x401F854CU, 0x0U, 0x401F8260U +#define IOMUXC_GPIO_EMC_23_ENET_RX_EN 0x401F8070U, 0x3U, 0x401F843CU, 0x0U, 0x401F8260U +#define IOMUXC_GPIO_EMC_23_GPT1_CAPTURE2 0x401F8070U, 0x4U, 0, 0, 0x401F8260U +#define IOMUXC_GPIO_EMC_23_GPIO4_IO23 0x401F8070U, 0x5U, 0, 0, 0x401F8260U + +#define IOMUXC_GPIO_EMC_24_SEMC_CAS 0x401F8074U, 0x0U, 0, 0, 0x401F8264U +#define IOMUXC_GPIO_EMC_24_FLEXPWM1_PWMB00 0x401F8074U, 0x1U, 0x401F8468U, 0x0U, 0x401F8264U +#define IOMUXC_GPIO_EMC_24_LPUART5_RX 0x401F8074U, 0x2U, 0x401F8548U, 0x0U, 0x401F8264U +#define IOMUXC_GPIO_EMC_24_ENET_TX_EN 0x401F8074U, 0x3U, 0, 0, 0x401F8264U +#define IOMUXC_GPIO_EMC_24_GPT1_CAPTURE1 0x401F8074U, 0x4U, 0, 0, 0x401F8264U +#define IOMUXC_GPIO_EMC_24_GPIO4_IO24 0x401F8074U, 0x5U, 0, 0, 0x401F8264U + +#define IOMUXC_GPIO_EMC_25_SEMC_RAS 0x401F8078U, 0x0U, 0, 0, 0x401F8268U +#define IOMUXC_GPIO_EMC_25_FLEXPWM1_PWMA01 0x401F8078U, 0x1U, 0x401F845CU, 0x0U, 0x401F8268U +#define IOMUXC_GPIO_EMC_25_LPUART6_TX 0x401F8078U, 0x2U, 0x401F8554U, 0x0U, 0x401F8268U +#define IOMUXC_GPIO_EMC_25_ENET_TX_CLK 0x401F8078U, 0x3U, 0x401F8448U, 0x0U, 0x401F8268U +#define IOMUXC_GPIO_EMC_25_ENET_REF_CLK 0x401F8078U, 0x4U, 0x401F842CU, 0x0U, 0x401F8268U +#define IOMUXC_GPIO_EMC_25_GPIO4_IO25 0x401F8078U, 0x5U, 0, 0, 0x401F8268U + +#define IOMUXC_GPIO_EMC_26_SEMC_CLK 0x401F807CU, 0x0U, 0, 0, 0x401F826CU +#define IOMUXC_GPIO_EMC_26_FLEXPWM1_PWMB01 0x401F807CU, 0x1U, 0x401F846CU, 0x0U, 0x401F826CU +#define IOMUXC_GPIO_EMC_26_LPUART6_RX 0x401F807CU, 0x2U, 0x401F8550U, 0x0U, 0x401F826CU +#define IOMUXC_GPIO_EMC_26_ENET_RX_ER 0x401F807CU, 0x3U, 0x401F8440U, 0x0U, 0x401F826CU +#define IOMUXC_GPIO_EMC_26_FLEXIO1_FLEXIO12 0x401F807CU, 0x4U, 0, 0, 0x401F826CU +#define IOMUXC_GPIO_EMC_26_GPIO4_IO26 0x401F807CU, 0x5U, 0, 0, 0x401F826CU + +#define IOMUXC_GPIO_EMC_27_SEMC_CKE 0x401F8080U, 0x0U, 0, 0, 0x401F8270U +#define IOMUXC_GPIO_EMC_27_FLEXPWM1_PWMA02 0x401F8080U, 0x1U, 0x401F8460U, 0x0U, 0x401F8270U +#define IOMUXC_GPIO_EMC_27_LPUART5_RTS_B 0x401F8080U, 0x2U, 0, 0, 0x401F8270U +#define IOMUXC_GPIO_EMC_27_LPSPI1_SCK 0x401F8080U, 0x3U, 0x401F84F0U, 0x0U, 0x401F8270U +#define IOMUXC_GPIO_EMC_27_FLEXIO1_FLEXIO13 0x401F8080U, 0x4U, 0, 0, 0x401F8270U +#define IOMUXC_GPIO_EMC_27_GPIO4_IO27 0x401F8080U, 0x5U, 0, 0, 0x401F8270U + +#define IOMUXC_GPIO_EMC_28_SEMC_WE 0x401F8084U, 0x0U, 0, 0, 0x401F8274U +#define IOMUXC_GPIO_EMC_28_FLEXPWM1_PWMB02 0x401F8084U, 0x1U, 0x401F8470U, 0x0U, 0x401F8274U +#define IOMUXC_GPIO_EMC_28_LPUART5_CTS_B 0x401F8084U, 0x2U, 0, 0, 0x401F8274U +#define IOMUXC_GPIO_EMC_28_LPSPI1_SDO 0x401F8084U, 0x3U, 0x401F84F8U, 0x0U, 0x401F8274U +#define IOMUXC_GPIO_EMC_28_FLEXIO1_FLEXIO14 0x401F8084U, 0x4U, 0, 0, 0x401F8274U +#define IOMUXC_GPIO_EMC_28_GPIO4_IO28 0x401F8084U, 0x5U, 0, 0, 0x401F8274U + +#define IOMUXC_GPIO_EMC_29_SEMC_CS0 0x401F8088U, 0x0U, 0, 0, 0x401F8278U +#define IOMUXC_GPIO_EMC_29_FLEXPWM3_PWMA00 0x401F8088U, 0x1U, 0, 0, 0x401F8278U +#define IOMUXC_GPIO_EMC_29_LPUART6_RTS_B 0x401F8088U, 0x2U, 0, 0, 0x401F8278U +#define IOMUXC_GPIO_EMC_29_LPSPI1_SDI 0x401F8088U, 0x3U, 0x401F84F4U, 0x0U, 0x401F8278U +#define IOMUXC_GPIO_EMC_29_FLEXIO1_FLEXIO15 0x401F8088U, 0x4U, 0, 0, 0x401F8278U +#define IOMUXC_GPIO_EMC_29_GPIO4_IO29 0x401F8088U, 0x5U, 0, 0, 0x401F8278U + +#define IOMUXC_GPIO_EMC_30_SEMC_DATA08 0x401F808CU, 0x0U, 0, 0, 0x401F827CU +#define IOMUXC_GPIO_EMC_30_FLEXPWM3_PWMB00 0x401F808CU, 0x1U, 0, 0, 0x401F827CU +#define IOMUXC_GPIO_EMC_30_LPUART6_CTS_B 0x401F808CU, 0x2U, 0, 0, 0x401F827CU +#define IOMUXC_GPIO_EMC_30_LPSPI1_PCS0 0x401F808CU, 0x3U, 0x401F84ECU, 0x1U, 0x401F827CU +#define IOMUXC_GPIO_EMC_30_CSI_DATA23 0x401F808CU, 0x4U, 0, 0, 0x401F827CU +#define IOMUXC_GPIO_EMC_30_GPIO4_IO30 0x401F808CU, 0x5U, 0, 0, 0x401F827CU + +#define IOMUXC_GPIO_EMC_31_SEMC_DATA09 0x401F8090U, 0x0U, 0, 0, 0x401F8280U +#define IOMUXC_GPIO_EMC_31_FLEXPWM3_PWMA01 0x401F8090U, 0x1U, 0, 0, 0x401F8280U +#define IOMUXC_GPIO_EMC_31_LPUART7_TX 0x401F8090U, 0x2U, 0x401F855CU, 0x1U, 0x401F8280U +#define IOMUXC_GPIO_EMC_31_LPSPI1_PCS1 0x401F8090U, 0x3U, 0, 0, 0x401F8280U +#define IOMUXC_GPIO_EMC_31_CSI_DATA22 0x401F8090U, 0x4U, 0, 0, 0x401F8280U +#define IOMUXC_GPIO_EMC_31_GPIO4_IO31 0x401F8090U, 0x5U, 0, 0, 0x401F8280U + +#define IOMUXC_GPIO_EMC_32_SEMC_DATA10 0x401F8094U, 0x0U, 0, 0, 0x401F8284U +#define IOMUXC_GPIO_EMC_32_FLEXPWM3_PWMB01 0x401F8094U, 0x1U, 0, 0, 0x401F8284U +#define IOMUXC_GPIO_EMC_32_LPUART7_RX 0x401F8094U, 0x2U, 0x401F8558U, 0x1U, 0x401F8284U +#define IOMUXC_GPIO_EMC_32_CCM_PMIC_RDY 0x401F8094U, 0x3U, 0x401F83FCU, 0x4U, 0x401F8284U +#define IOMUXC_GPIO_EMC_32_CSI_DATA21 0x401F8094U, 0x4U, 0, 0, 0x401F8284U +#define IOMUXC_GPIO_EMC_32_GPIO3_IO18 0x401F8094U, 0x5U, 0, 0, 0x401F8284U + +#define IOMUXC_GPIO_EMC_33_SEMC_DATA11 0x401F8098U, 0x0U, 0, 0, 0x401F8288U +#define IOMUXC_GPIO_EMC_33_FLEXPWM3_PWMA02 0x401F8098U, 0x1U, 0, 0, 0x401F8288U +#define IOMUXC_GPIO_EMC_33_USDHC1_RESET_B 0x401F8098U, 0x2U, 0, 0, 0x401F8288U +#define IOMUXC_GPIO_EMC_33_SAI3_RX_DATA 0x401F8098U, 0x3U, 0, 0, 0x401F8288U +#define IOMUXC_GPIO_EMC_33_CSI_DATA20 0x401F8098U, 0x4U, 0, 0, 0x401F8288U +#define IOMUXC_GPIO_EMC_33_GPIO3_IO19 0x401F8098U, 0x5U, 0, 0, 0x401F8288U + +#define IOMUXC_GPIO_EMC_34_SEMC_DATA12 0x401F809CU, 0x0U, 0, 0, 0x401F828CU +#define IOMUXC_GPIO_EMC_34_FLEXPWM3_PWMB02 0x401F809CU, 0x1U, 0, 0, 0x401F828CU +#define IOMUXC_GPIO_EMC_34_USDHC1_VSELECT 0x401F809CU, 0x2U, 0, 0, 0x401F828CU +#define IOMUXC_GPIO_EMC_34_SAI3_RX_SYNC 0x401F809CU, 0x3U, 0, 0, 0x401F828CU +#define IOMUXC_GPIO_EMC_34_CSI_DATA19 0x401F809CU, 0x4U, 0, 0, 0x401F828CU +#define IOMUXC_GPIO_EMC_34_GPIO3_IO20 0x401F809CU, 0x5U, 0, 0, 0x401F828CU + +#define IOMUXC_GPIO_EMC_35_SEMC_DATA13 0x401F80A0U, 0x0U, 0, 0, 0x401F8290U +#define IOMUXC_GPIO_EMC_35_XBAR1_INOUT18 0x401F80A0U, 0x1U, 0x401F8630U, 0x0U, 0x401F8290U +#define IOMUXC_GPIO_EMC_35_GPT1_COMPARE1 0x401F80A0U, 0x2U, 0, 0, 0x401F8290U +#define IOMUXC_GPIO_EMC_35_SAI3_RX_BCLK 0x401F80A0U, 0x3U, 0, 0, 0x401F8290U +#define IOMUXC_GPIO_EMC_35_CSI_DATA18 0x401F80A0U, 0x4U, 0, 0, 0x401F8290U +#define IOMUXC_GPIO_EMC_35_GPIO3_IO21 0x401F80A0U, 0x5U, 0, 0, 0x401F8290U +#define IOMUXC_GPIO_EMC_35_USDHC1_CD_B 0x401F80A0U, 0x6U, 0x401F85D4U, 0x0U, 0x401F8290U + +#define IOMUXC_GPIO_EMC_36_SEMC_DATA14 0x401F80A4U, 0x0U, 0, 0, 0x401F8294U +#define IOMUXC_GPIO_EMC_36_XBAR1_IN22 0x401F80A4U, 0x1U, 0x401F8638U, 0x0U, 0x401F8294U +#define IOMUXC_GPIO_EMC_36_GPT1_COMPARE2 0x401F80A4U, 0x2U, 0, 0, 0x401F8294U +#define IOMUXC_GPIO_EMC_36_SAI3_TX_DATA 0x401F80A4U, 0x3U, 0, 0, 0x401F8294U +#define IOMUXC_GPIO_EMC_36_CSI_DATA17 0x401F80A4U, 0x4U, 0, 0, 0x401F8294U +#define IOMUXC_GPIO_EMC_36_GPIO3_IO22 0x401F80A4U, 0x5U, 0, 0, 0x401F8294U +#define IOMUXC_GPIO_EMC_36_USDHC1_WP 0x401F80A4U, 0x6U, 0x401F85D8U, 0x1U, 0x401F8294U + +#define IOMUXC_GPIO_EMC_37_SEMC_DATA15 0x401F80A8U, 0x0U, 0, 0, 0x401F8298U +#define IOMUXC_GPIO_EMC_37_XBAR1_IN23 0x401F80A8U, 0x1U, 0x401F863CU, 0x0U, 0x401F8298U +#define IOMUXC_GPIO_EMC_37_GPT1_COMPARE3 0x401F80A8U, 0x2U, 0, 0, 0x401F8298U +#define IOMUXC_GPIO_EMC_37_SAI3_MCLK 0x401F80A8U, 0x3U, 0, 0, 0x401F8298U +#define IOMUXC_GPIO_EMC_37_CSI_DATA16 0x401F80A8U, 0x4U, 0, 0, 0x401F8298U +#define IOMUXC_GPIO_EMC_37_GPIO3_IO23 0x401F80A8U, 0x5U, 0, 0, 0x401F8298U +#define IOMUXC_GPIO_EMC_37_USDHC2_WP 0x401F80A8U, 0x6U, 0x401F8608U, 0x0U, 0x401F8298U + +#define IOMUXC_GPIO_EMC_38_SEMC_DM01 0x401F80ACU, 0x0U, 0, 0, 0x401F829CU +#define IOMUXC_GPIO_EMC_38_FLEXPWM1_PWMA03 0x401F80ACU, 0x1U, 0x401F8454U, 0x2U, 0x401F829CU +#define IOMUXC_GPIO_EMC_38_LPUART8_TX 0x401F80ACU, 0x2U, 0x401F8564U, 0x2U, 0x401F829CU +#define IOMUXC_GPIO_EMC_38_SAI3_TX_BCLK 0x401F80ACU, 0x3U, 0, 0, 0x401F829CU +#define IOMUXC_GPIO_EMC_38_CSI_FIELD 0x401F80ACU, 0x4U, 0, 0, 0x401F829CU +#define IOMUXC_GPIO_EMC_38_GPIO3_IO24 0x401F80ACU, 0x5U, 0, 0, 0x401F829CU +#define IOMUXC_GPIO_EMC_38_USDHC2_VSELECT 0x401F80ACU, 0x6U, 0, 0, 0x401F829CU + +#define IOMUXC_GPIO_EMC_39_SEMC_DQS 0x401F80B0U, 0x0U, 0, 0, 0x401F82A0U +#define IOMUXC_GPIO_EMC_39_FLEXPWM1_PWMB03 0x401F80B0U, 0x1U, 0x401F8464U, 0x2U, 0x401F82A0U +#define IOMUXC_GPIO_EMC_39_LPUART8_RX 0x401F80B0U, 0x2U, 0x401F8560U, 0x2U, 0x401F82A0U +#define IOMUXC_GPIO_EMC_39_SAI3_TX_SYNC 0x401F80B0U, 0x3U, 0, 0, 0x401F82A0U +#define IOMUXC_GPIO_EMC_39_WDOG1_WDOG_B 0x401F80B0U, 0x4U, 0, 0, 0x401F82A0U +#define IOMUXC_GPIO_EMC_39_GPIO3_IO25 0x401F80B0U, 0x5U, 0, 0, 0x401F82A0U +#define IOMUXC_GPIO_EMC_39_USDHC2_CD_B 0x401F80B0U, 0x6U, 0x401F85E0U, 0x1U, 0x401F82A0U + +#define IOMUXC_GPIO_EMC_40_SEMC_RDY 0x401F80B4U, 0x0U, 0, 0, 0x401F82A4U +#define IOMUXC_GPIO_EMC_40_GPT2_CAPTURE2 0x401F80B4U, 0x1U, 0, 0, 0x401F82A4U +#define IOMUXC_GPIO_EMC_40_LPSPI1_PCS2 0x401F80B4U, 0x2U, 0, 0, 0x401F82A4U +#define IOMUXC_GPIO_EMC_40_USB_OTG2_OC 0x401F80B4U, 0x3U, 0x401F85CCU, 0x1U, 0x401F82A4U +#define IOMUXC_GPIO_EMC_40_ENET_MDC 0x401F80B4U, 0x4U, 0, 0, 0x401F82A4U +#define IOMUXC_GPIO_EMC_40_GPIO3_IO26 0x401F80B4U, 0x5U, 0, 0, 0x401F82A4U +#define IOMUXC_GPIO_EMC_40_USDHC2_RESET_B 0x401F80B4U, 0x6U, 0, 0, 0x401F82A4U + +#define IOMUXC_GPIO_EMC_41_SEMC_CSX00 0x401F80B8U, 0x0U, 0, 0, 0x401F82A8U +#define IOMUXC_GPIO_EMC_41_GPT2_CAPTURE1 0x401F80B8U, 0x1U, 0, 0, 0x401F82A8U +#define IOMUXC_GPIO_EMC_41_LPSPI1_PCS3 0x401F80B8U, 0x2U, 0, 0, 0x401F82A8U +#define IOMUXC_GPIO_EMC_41_USB_OTG2_PWR 0x401F80B8U, 0x3U, 0, 0, 0x401F82A8U +#define IOMUXC_GPIO_EMC_41_ENET_MDIO 0x401F80B8U, 0x4U, 0x401F8430U, 0x1U, 0x401F82A8U +#define IOMUXC_GPIO_EMC_41_GPIO3_IO27 0x401F80B8U, 0x5U, 0, 0, 0x401F82A8U +#define IOMUXC_GPIO_EMC_41_USDHC1_VSELECT 0x401F80B8U, 0x6U, 0, 0, 0x401F82A8U + +#define IOMUXC_GPIO_AD_B0_00_FLEXPWM2_PWMA03 0x401F80BCU, 0x0U, 0x401F8474U, 0x2U, 0x401F82ACU +#define IOMUXC_GPIO_AD_B0_00_XBAR1_INOUT14 0x401F80BCU, 0x1U, 0x401F8644U, 0x0U, 0x401F82ACU +#define IOMUXC_GPIO_AD_B0_00_REF_CLK_32K 0x401F80BCU, 0x2U, 0, 0, 0x401F82ACU +#define IOMUXC_GPIO_AD_B0_00_USB_OTG2_ID 0x401F80BCU, 0x3U, 0x401F83F8U, 0x0U, 0x401F82ACU +#define IOMUXC_GPIO_AD_B0_00_LPI2C1_SCLS 0x401F80BCU, 0x4U, 0, 0, 0x401F82ACU +#define IOMUXC_GPIO_AD_B0_00_GPIO1_IO00 0x401F80BCU, 0x5U, 0, 0, 0x401F82ACU +#define IOMUXC_GPIO_AD_B0_00_USDHC1_RESET_B 0x401F80BCU, 0x6U, 0, 0, 0x401F82ACU +#define IOMUXC_GPIO_AD_B0_00_LPSPI3_SCK 0x401F80BCU, 0x7U, 0x401F8510U, 0x0U, 0x401F82ACU + +#define IOMUXC_GPIO_AD_B0_01_FLEXPWM2_PWMB03 0x401F80C0U, 0x0U, 0x401F8484U, 0x2U, 0x401F82B0U +#define IOMUXC_GPIO_AD_B0_01_XBAR1_INOUT15 0x401F80C0U, 0x1U, 0x401F8648U, 0x0U, 0x401F82B0U +#define IOMUXC_GPIO_AD_B0_01_REF_CLK_24M 0x401F80C0U, 0x2U, 0, 0, 0x401F82B0U +#define IOMUXC_GPIO_AD_B0_01_USB_OTG1_ID 0x401F80C0U, 0x3U, 0x401F83F4U, 0x0U, 0x401F82B0U +#define IOMUXC_GPIO_AD_B0_01_LPI2C1_SDAS 0x401F80C0U, 0x4U, 0, 0, 0x401F82B0U +#define IOMUXC_GPIO_AD_B0_01_GPIO1_IO01 0x401F80C0U, 0x5U, 0, 0, 0x401F82B0U +#define IOMUXC_GPIO_AD_B0_01_EWM_OUT_B 0x401F80C0U, 0x6U, 0, 0, 0x401F82B0U +#define IOMUXC_GPIO_AD_B0_01_LPSPI3_SDO 0x401F80C0U, 0x7U, 0x401F8518U, 0x0U, 0x401F82B0U + +#define IOMUXC_GPIO_AD_B0_02_FLEXCAN2_TX 0x401F80C4U, 0x0U, 0, 0, 0x401F82B4U +#define IOMUXC_GPIO_AD_B0_02_XBAR1_INOUT16 0x401F80C4U, 0x1U, 0x401F864CU, 0x0U, 0x401F82B4U +#define IOMUXC_GPIO_AD_B0_02_LPUART6_TX 0x401F80C4U, 0x2U, 0x401F8554U, 0x1U, 0x401F82B4U +#define IOMUXC_GPIO_AD_B0_02_USB_OTG1_PWR 0x401F80C4U, 0x3U, 0, 0, 0x401F82B4U +#define IOMUXC_GPIO_AD_B0_02_FLEXPWM1_PWMX00 0x401F80C4U, 0x4U, 0, 0, 0x401F82B4U +#define IOMUXC_GPIO_AD_B0_02_GPIO1_IO02 0x401F80C4U, 0x5U, 0, 0, 0x401F82B4U +#define IOMUXC_GPIO_AD_B0_02_LPI2C1_HREQ 0x401F80C4U, 0x6U, 0, 0, 0x401F82B4U +#define IOMUXC_GPIO_AD_B0_02_LPSPI3_SDI 0x401F80C4U, 0x7U, 0x401F8514U, 0x0U, 0x401F82B4U + +#define IOMUXC_GPIO_AD_B0_03_FLEXCAN2_RX 0x401F80C8U, 0x0U, 0x401F8450U, 0x1U, 0x401F82B8U +#define IOMUXC_GPIO_AD_B0_03_XBAR1_INOUT17 0x401F80C8U, 0x1U, 0x401F862CU, 0x1U, 0x401F82B8U +#define IOMUXC_GPIO_AD_B0_03_LPUART6_RX 0x401F80C8U, 0x2U, 0x401F8550U, 0x1U, 0x401F82B8U +#define IOMUXC_GPIO_AD_B0_03_USB_OTG1_OC 0x401F80C8U, 0x3U, 0x401F85D0U, 0x0U, 0x401F82B8U +#define IOMUXC_GPIO_AD_B0_03_FLEXPWM1_PWMX01 0x401F80C8U, 0x4U, 0, 0, 0x401F82B8U +#define IOMUXC_GPIO_AD_B0_03_GPIO1_IO03 0x401F80C8U, 0x5U, 0, 0, 0x401F82B8U +#define IOMUXC_GPIO_AD_B0_03_REF_CLK_24M 0x401F80C8U, 0x6U, 0, 0, 0x401F82B8U +#define IOMUXC_GPIO_AD_B0_03_LPSPI3_PCS0 0x401F80C8U, 0x7U, 0x401F850CU, 0x0U, 0x401F82B8U + +#define IOMUXC_GPIO_AD_B0_04_SRC_BOOT_MODE00 0x401F80CCU, 0x0U, 0, 0, 0x401F82BCU +#define IOMUXC_GPIO_AD_B0_04_MQS_RIGHT 0x401F80CCU, 0x1U, 0, 0, 0x401F82BCU +#define IOMUXC_GPIO_AD_B0_04_ENET_TX_DATA03 0x401F80CCU, 0x2U, 0, 0, 0x401F82BCU +#define IOMUXC_GPIO_AD_B0_04_SAI2_TX_SYNC 0x401F80CCU, 0x3U, 0x401F85C4U, 0x1U, 0x401F82BCU +#define IOMUXC_GPIO_AD_B0_04_CSI_DATA09 0x401F80CCU, 0x4U, 0x401F841CU, 0x1U, 0x401F82BCU +#define IOMUXC_GPIO_AD_B0_04_GPIO1_IO04 0x401F80CCU, 0x5U, 0, 0, 0x401F82BCU +#define IOMUXC_GPIO_AD_B0_04_PIT_TRIGGER00 0x401F80CCU, 0x6U, 0, 0, 0x401F82BCU +#define IOMUXC_GPIO_AD_B0_04_LPSPI3_PCS1 0x401F80CCU, 0x7U, 0, 0, 0x401F82BCU + +#define IOMUXC_GPIO_AD_B0_05_SRC_BOOT_MODE01 0x401F80D0U, 0x0U, 0, 0, 0x401F82C0U +#define IOMUXC_GPIO_AD_B0_05_MQS_LEFT 0x401F80D0U, 0x1U, 0, 0, 0x401F82C0U +#define IOMUXC_GPIO_AD_B0_05_ENET_TX_DATA02 0x401F80D0U, 0x2U, 0, 0, 0x401F82C0U +#define IOMUXC_GPIO_AD_B0_05_SAI2_TX_BCLK 0x401F80D0U, 0x3U, 0x401F85C0U, 0x1U, 0x401F82C0U +#define IOMUXC_GPIO_AD_B0_05_CSI_DATA08 0x401F80D0U, 0x4U, 0x401F8418U, 0x1U, 0x401F82C0U +#define IOMUXC_GPIO_AD_B0_05_GPIO1_IO05 0x401F80D0U, 0x5U, 0, 0, 0x401F82C0U +#define IOMUXC_GPIO_AD_B0_05_XBAR1_INOUT17 0x401F80D0U, 0x6U, 0x401F862CU, 0x2U, 0x401F82C0U +#define IOMUXC_GPIO_AD_B0_05_LPSPI3_PCS2 0x401F80D0U, 0x7U, 0, 0, 0x401F82C0U + +#define IOMUXC_GPIO_AD_B0_06_JTAG_TMS 0x401F80D4U, 0x0U, 0, 0, 0x401F82C4U +#define IOMUXC_GPIO_AD_B0_06_GPT2_COMPARE1 0x401F80D4U, 0x1U, 0, 0, 0x401F82C4U +#define IOMUXC_GPIO_AD_B0_06_ENET_RX_CLK 0x401F80D4U, 0x2U, 0, 0, 0x401F82C4U +#define IOMUXC_GPIO_AD_B0_06_SAI2_RX_BCLK 0x401F80D4U, 0x3U, 0x401F85B4U, 0x1U, 0x401F82C4U +#define IOMUXC_GPIO_AD_B0_06_CSI_DATA07 0x401F80D4U, 0x4U, 0x401F8414U, 0x1U, 0x401F82C4U +#define IOMUXC_GPIO_AD_B0_06_GPIO1_IO06 0x401F80D4U, 0x5U, 0, 0, 0x401F82C4U +#define IOMUXC_GPIO_AD_B0_06_XBAR1_INOUT18 0x401F80D4U, 0x6U, 0x401F8630U, 0x1U, 0x401F82C4U +#define IOMUXC_GPIO_AD_B0_06_LPSPI3_PCS3 0x401F80D4U, 0x7U, 0, 0, 0x401F82C4U + +#define IOMUXC_GPIO_AD_B0_07_JTAG_TCK 0x401F80D8U, 0x0U, 0, 0, 0x401F82C8U +#define IOMUXC_GPIO_AD_B0_07_GPT2_COMPARE2 0x401F80D8U, 0x1U, 0, 0, 0x401F82C8U +#define IOMUXC_GPIO_AD_B0_07_ENET_TX_ER 0x401F80D8U, 0x2U, 0, 0, 0x401F82C8U +#define IOMUXC_GPIO_AD_B0_07_SAI2_RX_SYNC 0x401F80D8U, 0x3U, 0x401F85BCU, 0x1U, 0x401F82C8U +#define IOMUXC_GPIO_AD_B0_07_CSI_DATA06 0x401F80D8U, 0x4U, 0x401F8410U, 0x1U, 0x401F82C8U +#define IOMUXC_GPIO_AD_B0_07_GPIO1_IO07 0x401F80D8U, 0x5U, 0, 0, 0x401F82C8U +#define IOMUXC_GPIO_AD_B0_07_XBAR1_INOUT19 0x401F80D8U, 0x6U, 0x401F8654U, 0x1U, 0x401F82C8U +#define IOMUXC_GPIO_AD_B0_07_ENET_1588_EVENT3_OUT 0x401F80D8U, 0x7U, 0, 0, 0x401F82C8U + +#define IOMUXC_GPIO_AD_B0_08_JTAG_MOD 0x401F80DCU, 0x0U, 0, 0, 0x401F82CCU +#define IOMUXC_GPIO_AD_B0_08_GPT2_COMPARE3 0x401F80DCU, 0x1U, 0, 0, 0x401F82CCU +#define IOMUXC_GPIO_AD_B0_08_ENET_RX_DATA03 0x401F80DCU, 0x2U, 0, 0, 0x401F82CCU +#define IOMUXC_GPIO_AD_B0_08_SAI2_RX_DATA 0x401F80DCU, 0x3U, 0x401F85B8U, 0x1U, 0x401F82CCU +#define IOMUXC_GPIO_AD_B0_08_CSI_DATA05 0x401F80DCU, 0x4U, 0x401F840CU, 0x1U, 0x401F82CCU +#define IOMUXC_GPIO_AD_B0_08_GPIO1_IO08 0x401F80DCU, 0x5U, 0, 0, 0x401F82CCU +#define IOMUXC_GPIO_AD_B0_08_XBAR1_IN20 0x401F80DCU, 0x6U, 0x401F8634U, 0x1U, 0x401F82CCU +#define IOMUXC_GPIO_AD_B0_08_ENET_1588_EVENT3_IN 0x401F80DCU, 0x7U, 0, 0, 0x401F82CCU + +#define IOMUXC_GPIO_AD_B0_09_JTAG_TDI 0x401F80E0U, 0x0U, 0, 0, 0x401F82D0U +#define IOMUXC_GPIO_AD_B0_09_FLEXPWM2_PWMA03 0x401F80E0U, 0x1U, 0x401F8474U, 0x3U, 0x401F82D0U +#define IOMUXC_GPIO_AD_B0_09_ENET_RX_DATA02 0x401F80E0U, 0x2U, 0, 0, 0x401F82D0U +#define IOMUXC_GPIO_AD_B0_09_SAI2_TX_DATA 0x401F80E0U, 0x3U, 0, 0, 0x401F82D0U +#define IOMUXC_GPIO_AD_B0_09_CSI_DATA04 0x401F80E0U, 0x4U, 0x401F8408U, 0x1U, 0x401F82D0U +#define IOMUXC_GPIO_AD_B0_09_GPIO1_IO09 0x401F80E0U, 0x5U, 0, 0, 0x401F82D0U +#define IOMUXC_GPIO_AD_B0_09_XBAR1_IN21 0x401F80E0U, 0x6U, 0x401F8658U, 0x1U, 0x401F82D0U +#define IOMUXC_GPIO_AD_B0_09_GPT2_CLK 0x401F80E0U, 0x7U, 0, 0, 0x401F82D0U + +#define IOMUXC_GPIO_AD_B0_10_JTAG_TDO 0x401F80E4U, 0x0U, 0, 0, 0x401F82D4U +#define IOMUXC_GPIO_AD_B0_10_FLEXPWM1_PWMA03 0x401F80E4U, 0x1U, 0x401F8454U, 0x3U, 0x401F82D4U +#define IOMUXC_GPIO_AD_B0_10_ENET_CRS 0x401F80E4U, 0x2U, 0, 0, 0x401F82D4U +#define IOMUXC_GPIO_AD_B0_10_SAI2_MCLK 0x401F80E4U, 0x3U, 0x401F85B0U, 0x1U, 0x401F82D4U +#define IOMUXC_GPIO_AD_B0_10_CSI_DATA03 0x401F80E4U, 0x4U, 0x401F8404U, 0x1U, 0x401F82D4U +#define IOMUXC_GPIO_AD_B0_10_GPIO1_IO10 0x401F80E4U, 0x5U, 0, 0, 0x401F82D4U +#define IOMUXC_GPIO_AD_B0_10_XBAR1_IN22 0x401F80E4U, 0x6U, 0x401F8638U, 0x1U, 0x401F82D4U +#define IOMUXC_GPIO_AD_B0_10_ENET_1588_EVENT0_OUT 0x401F80E4U, 0x7U, 0, 0, 0x401F82D4U + +#define IOMUXC_GPIO_AD_B0_11_JTAG_TRSTB 0x401F80E8U, 0x0U, 0, 0, 0x401F82D8U +#define IOMUXC_GPIO_AD_B0_11_FLEXPWM1_PWMB03 0x401F80E8U, 0x1U, 0x401F8464U, 0x3U, 0x401F82D8U +#define IOMUXC_GPIO_AD_B0_11_ENET_COL 0x401F80E8U, 0x2U, 0, 0, 0x401F82D8U +#define IOMUXC_GPIO_AD_B0_11_WDOG1_WDOG_B 0x401F80E8U, 0x3U, 0, 0, 0x401F82D8U +#define IOMUXC_GPIO_AD_B0_11_CSI_DATA02 0x401F80E8U, 0x4U, 0x401F8400U, 0x1U, 0x401F82D8U +#define IOMUXC_GPIO_AD_B0_11_GPIO1_IO11 0x401F80E8U, 0x5U, 0, 0, 0x401F82D8U +#define IOMUXC_GPIO_AD_B0_11_XBAR1_IN23 0x401F80E8U, 0x6U, 0x401F863CU, 0x1U, 0x401F82D8U +#define IOMUXC_GPIO_AD_B0_11_ENET_1588_EVENT0_IN 0x401F80E8U, 0x7U, 0x401F8444U, 0x1U, 0x401F82D8U + +#define IOMUXC_GPIO_AD_B0_12_LPI2C4_SCL 0x401F80ECU, 0x0U, 0x401F84E4U, 0x1U, 0x401F82DCU +#define IOMUXC_GPIO_AD_B0_12_CCM_PMIC_READY 0x401F80ECU, 0x1U, 0x401F83FCU, 0x1U, 0x401F82DCU +#define IOMUXC_GPIO_AD_B0_12_LPUART1_TX 0x401F80ECU, 0x2U, 0, 0, 0x401F82DCU +#define IOMUXC_GPIO_AD_B0_12_WDOG2_WDOG_B 0x401F80ECU, 0x3U, 0, 0, 0x401F82DCU +#define IOMUXC_GPIO_AD_B0_12_FLEXPWM1_PWMX02 0x401F80ECU, 0x4U, 0, 0, 0x401F82DCU +#define IOMUXC_GPIO_AD_B0_12_GPIO1_IO12 0x401F80ECU, 0x5U, 0, 0, 0x401F82DCU +#define IOMUXC_GPIO_AD_B0_12_ENET_1588_EVENT1_OUT 0x401F80ECU, 0x6U, 0, 0, 0x401F82DCU +#define IOMUXC_GPIO_AD_B0_12_NMI_GLUE_NMI 0x401F80ECU, 0x7U, 0x401F8568U, 0x0U, 0x401F82DCU + +#define IOMUXC_GPIO_AD_B0_13_LPI2C4_SDA 0x401F80F0U, 0x0U, 0x401F84E8U, 0x1U, 0x401F82E0U +#define IOMUXC_GPIO_AD_B0_13_GPT1_CLK 0x401F80F0U, 0x1U, 0, 0, 0x401F82E0U +#define IOMUXC_GPIO_AD_B0_13_LPUART1_RX 0x401F80F0U, 0x2U, 0, 0, 0x401F82E0U +#define IOMUXC_GPIO_AD_B0_13_EWM_OUT_B 0x401F80F0U, 0x3U, 0, 0, 0x401F82E0U +#define IOMUXC_GPIO_AD_B0_13_FLEXPWM1_PWMX03 0x401F80F0U, 0x4U, 0, 0, 0x401F82E0U +#define IOMUXC_GPIO_AD_B0_13_GPIO1_IO13 0x401F80F0U, 0x5U, 0, 0, 0x401F82E0U +#define IOMUXC_GPIO_AD_B0_13_ENET_1588_EVENT1_IN 0x401F80F0U, 0x6U, 0, 0, 0x401F82E0U +#define IOMUXC_GPIO_AD_B0_13_REF_CLK_24M 0x401F80F0U, 0x7U, 0, 0, 0x401F82E0U + +#define IOMUXC_GPIO_AD_B0_14_USB_OTG2_OC 0x401F80F4U, 0x0U, 0x401F85CCU, 0x0U, 0x401F82E4U +#define IOMUXC_GPIO_AD_B0_14_XBAR1_IN24 0x401F80F4U, 0x1U, 0x401F8640U, 0x1U, 0x401F82E4U +#define IOMUXC_GPIO_AD_B0_14_LPUART1_CTS_B 0x401F80F4U, 0x2U, 0, 0, 0x401F82E4U +#define IOMUXC_GPIO_AD_B0_14_ENET_1588_EVENT0_OUT 0x401F80F4U, 0x3U, 0, 0, 0x401F82E4U +#define IOMUXC_GPIO_AD_B0_14_CSI_VSYNC 0x401F80F4U, 0x4U, 0x401F8428U, 0x0U, 0x401F82E4U +#define IOMUXC_GPIO_AD_B0_14_GPIO1_IO14 0x401F80F4U, 0x5U, 0, 0, 0x401F82E4U +#define IOMUXC_GPIO_AD_B0_14_FLEXCAN2_TX 0x401F80F4U, 0x6U, 0, 0, 0x401F82E4U + +#define IOMUXC_GPIO_AD_B0_15_USB_OTG2_PWR 0x401F80F8U, 0x0U, 0, 0, 0x401F82E8U +#define IOMUXC_GPIO_AD_B0_15_XBAR1_IN25 0x401F80F8U, 0x1U, 0x401F8650U, 0x0U, 0x401F82E8U +#define IOMUXC_GPIO_AD_B0_15_LPUART1_RTS_B 0x401F80F8U, 0x2U, 0, 0, 0x401F82E8U +#define IOMUXC_GPIO_AD_B0_15_ENET_1588_EVENT0_IN 0x401F80F8U, 0x3U, 0x401F8444U, 0x0U, 0x401F82E8U +#define IOMUXC_GPIO_AD_B0_15_CSI_HSYNC 0x401F80F8U, 0x4U, 0x401F8420U, 0x0U, 0x401F82E8U +#define IOMUXC_GPIO_AD_B0_15_GPIO1_IO15 0x401F80F8U, 0x5U, 0, 0, 0x401F82E8U +#define IOMUXC_GPIO_AD_B0_15_FLEXCAN2_RX 0x401F80F8U, 0x6U, 0x401F8450U, 0x2U, 0x401F82E8U +#define IOMUXC_GPIO_AD_B0_15_WDOG1_WDOG_RST_B_DEB 0x401F80F8U, 0x7U, 0, 0, 0x401F82E8U + +#define IOMUXC_GPIO_AD_B1_00_USB_OTG2_ID 0x401F80FCU, 0x0U, 0x401F83F8U, 0x1U, 0x401F82ECU +#define IOMUXC_GPIO_AD_B1_00_QTIMER3_TIMER0 0x401F80FCU, 0x1U, 0x401F857CU, 0x1U, 0x401F82ECU +#define IOMUXC_GPIO_AD_B1_00_LPUART2_CTS_B 0x401F80FCU, 0x2U, 0, 0, 0x401F82ECU +#define IOMUXC_GPIO_AD_B1_00_LPI2C1_SCL 0x401F80FCU, 0x3U, 0x401F84CCU, 0x1U, 0x401F82ECU +#define IOMUXC_GPIO_AD_B1_00_WDOG1_B 0x401F80FCU, 0x4U, 0, 0, 0x401F82ECU +#define IOMUXC_GPIO_AD_B1_00_GPIO1_IO16 0x401F80FCU, 0x5U, 0, 0, 0x401F82ECU +#define IOMUXC_GPIO_AD_B1_00_USDHC1_WP 0x401F80FCU, 0x6U, 0x401F85D8U, 0x2U, 0x401F82ECU +#define IOMUXC_GPIO_AD_B1_00_KPP_ROW07 0x401F80FCU, 0x7U, 0, 0, 0x401F82ECU + +#define IOMUXC_GPIO_AD_B1_01_USB_OTG1_PWR 0x401F8100U, 0x0U, 0, 0, 0x401F82F0U +#define IOMUXC_GPIO_AD_B1_01_QTIMER3_TIMER1 0x401F8100U, 0x1U, 0x401F8580U, 0x0U, 0x401F82F0U +#define IOMUXC_GPIO_AD_B1_01_LPUART2_RTS_B 0x401F8100U, 0x2U, 0, 0, 0x401F82F0U +#define IOMUXC_GPIO_AD_B1_01_LPI2C1_SDA 0x401F8100U, 0x3U, 0x401F84D0U, 0x1U, 0x401F82F0U +#define IOMUXC_GPIO_AD_B1_01_CCM_PMIC_READY 0x401F8100U, 0x4U, 0x401F83FCU, 0x2U, 0x401F82F0U +#define IOMUXC_GPIO_AD_B1_01_GPIO1_IO17 0x401F8100U, 0x5U, 0, 0, 0x401F82F0U +#define IOMUXC_GPIO_AD_B1_01_USDHC1_VSELECT 0x401F8100U, 0x6U, 0, 0, 0x401F82F0U +#define IOMUXC_GPIO_AD_B1_01_KPP_COL07 0x401F8100U, 0x7U, 0, 0, 0x401F82F0U + +#define IOMUXC_GPIO_AD_B1_02_USB_OTG1_ID 0x401F8104U, 0x0U, 0x401F83F4U, 0x1U, 0x401F82F4U +#define IOMUXC_GPIO_AD_B1_02_QTIMER3_TIMER2 0x401F8104U, 0x1U, 0x401F8584U, 0x1U, 0x401F82F4U +#define IOMUXC_GPIO_AD_B1_02_LPUART2_TX 0x401F8104U, 0x2U, 0x401F8530U, 0x1U, 0x401F82F4U +#define IOMUXC_GPIO_AD_B1_02_SPDIF_OUT 0x401F8104U, 0x3U, 0, 0, 0x401F82F4U +#define IOMUXC_GPIO_AD_B1_02_ENET_1588_EVENT2_OUT 0x401F8104U, 0x4U, 0, 0, 0x401F82F4U +#define IOMUXC_GPIO_AD_B1_02_GPIO1_IO18 0x401F8104U, 0x5U, 0, 0, 0x401F82F4U +#define IOMUXC_GPIO_AD_B1_02_USDHC1_CD_B 0x401F8104U, 0x6U, 0x401F85D4U, 0x1U, 0x401F82F4U +#define IOMUXC_GPIO_AD_B1_02_KPP_ROW06 0x401F8104U, 0x7U, 0, 0, 0x401F82F4U + +#define IOMUXC_GPIO_AD_B1_03_USB_OTG1_OC 0x401F8108U, 0x0U, 0x401F85D0U, 0x1U, 0x401F82F8U +#define IOMUXC_GPIO_AD_B1_03_QTIMER3_TIMER3 0x401F8108U, 0x1U, 0x401F8588U, 0x1U, 0x401F82F8U +#define IOMUXC_GPIO_AD_B1_03_LPUART2_RX 0x401F8108U, 0x2U, 0x401F852CU, 0x1U, 0x401F82F8U +#define IOMUXC_GPIO_AD_B1_03_SPDIF_IN 0x401F8108U, 0x3U, 0x401F85C8U, 0x0U, 0x401F82F8U +#define IOMUXC_GPIO_AD_B1_03_ENET_1588_EVENT2_IN 0x401F8108U, 0x4U, 0, 0, 0x401F82F8U +#define IOMUXC_GPIO_AD_B1_03_GPIO1_IO19 0x401F8108U, 0x5U, 0, 0, 0x401F82F8U +#define IOMUXC_GPIO_AD_B1_03_USDHC2_CD_B 0x401F8108U, 0x6U, 0x401F85E0U, 0x0U, 0x401F82F8U +#define IOMUXC_GPIO_AD_B1_03_KPP_COL06 0x401F8108U, 0x7U, 0, 0, 0x401F82F8U + +#define IOMUXC_GPIO_AD_B1_04_FLEXSPIB_DATA03 0x401F810CU, 0x0U, 0x401F84C4U, 0x1U, 0x401F82FCU +#define IOMUXC_GPIO_AD_B1_04_ENET_MDC 0x401F810CU, 0x1U, 0, 0, 0x401F82FCU +#define IOMUXC_GPIO_AD_B1_04_LPUART3_CTS_B 0x401F810CU, 0x2U, 0x401F8534U, 0x1U, 0x401F82FCU +#define IOMUXC_GPIO_AD_B1_04_SPDIF_SR_CLK 0x401F810CU, 0x3U, 0, 0, 0x401F82FCU +#define IOMUXC_GPIO_AD_B1_04_CSI_PIXCLK 0x401F810CU, 0x4U, 0x401F8424U, 0x0U, 0x401F82FCU +#define IOMUXC_GPIO_AD_B1_04_GPIO1_IO20 0x401F810CU, 0x5U, 0, 0, 0x401F82FCU +#define IOMUXC_GPIO_AD_B1_04_USDHC2_DATA0 0x401F810CU, 0x6U, 0x401F85E8U, 0x1U, 0x401F82FCU +#define IOMUXC_GPIO_AD_B1_04_KPP_ROW05 0x401F810CU, 0x7U, 0, 0, 0x401F82FCU + +#define IOMUXC_GPIO_AD_B1_05_FLEXSPIB_DATA02 0x401F8110U, 0x0U, 0x401F84C0U, 0x1U, 0x401F8300U +#define IOMUXC_GPIO_AD_B1_05_ENET_MDIO 0x401F8110U, 0x1U, 0x401F8430U, 0x0U, 0x401F8300U +#define IOMUXC_GPIO_AD_B1_05_LPUART3_RTS_B 0x401F8110U, 0x2U, 0, 0, 0x401F8300U +#define IOMUXC_GPIO_AD_B1_05_SPDIF_OUT 0x401F8110U, 0x3U, 0, 0, 0x401F8300U +#define IOMUXC_GPIO_AD_B1_05_CSI_MCLK 0x401F8110U, 0x4U, 0, 0, 0x401F8300U +#define IOMUXC_GPIO_AD_B1_05_GPIO1_IO21 0x401F8110U, 0x5U, 0, 0, 0x401F8300U +#define IOMUXC_GPIO_AD_B1_05_USDHC2_DATA1 0x401F8110U, 0x6U, 0x401F85ECU, 0x1U, 0x401F8300U +#define IOMUXC_GPIO_AD_B1_05_KPP_COL05 0x401F8110U, 0x7U, 0, 0, 0x401F8300U + +#define IOMUXC_GPIO_AD_B1_06_FLEXSPIB_DATA01 0x401F8114U, 0x0U, 0x401F84BCU, 0x1U, 0x401F8304U +#define IOMUXC_GPIO_AD_B1_06_LPI2C3_SDA 0x401F8114U, 0x1U, 0x401F84E0U, 0x2U, 0x401F8304U +#define IOMUXC_GPIO_AD_B1_06_LPUART3_TX 0x401F8114U, 0x2U, 0x401F853CU, 0x0U, 0x401F8304U +#define IOMUXC_GPIO_AD_B1_06_SPDIF_LOCK 0x401F8114U, 0x3U, 0, 0, 0x401F8304U +#define IOMUXC_GPIO_AD_B1_06_CSI_VSYNC 0x401F8114U, 0x4U, 0x401F8428U, 0x1U, 0x401F8304U +#define IOMUXC_GPIO_AD_B1_06_GPIO1_IO22 0x401F8114U, 0x5U, 0, 0, 0x401F8304U +#define IOMUXC_GPIO_AD_B1_06_USDHC2_DATA2 0x401F8114U, 0x6U, 0x401F85F0U, 0x1U, 0x401F8304U +#define IOMUXC_GPIO_AD_B1_06_KPP_ROW04 0x401F8114U, 0x7U, 0, 0, 0x401F8304U + +#define IOMUXC_GPIO_AD_B1_07_FLEXSPIB_DATA00 0x401F8118U, 0x0U, 0x401F84B8U, 0x1U, 0x401F8308U +#define IOMUXC_GPIO_AD_B1_07_LPI2C3_SCL 0x401F8118U, 0x1U, 0x401F84DCU, 0x2U, 0x401F8308U +#define IOMUXC_GPIO_AD_B1_07_LPUART3_RX 0x401F8118U, 0x2U, 0x401F8538U, 0x0U, 0x401F8308U +#define IOMUXC_GPIO_AD_B1_07_SPDIF_EXT_CLK 0x401F8118U, 0x3U, 0, 0, 0x401F8308U +#define IOMUXC_GPIO_AD_B1_07_CSI_HSYNC 0x401F8118U, 0x4U, 0x401F8420U, 0x1U, 0x401F8308U +#define IOMUXC_GPIO_AD_B1_07_GPIO1_IO23 0x401F8118U, 0x5U, 0, 0, 0x401F8308U +#define IOMUXC_GPIO_AD_B1_07_USDHC2_DATA3 0x401F8118U, 0x6U, 0x401F85F4U, 0x1U, 0x401F8308U +#define IOMUXC_GPIO_AD_B1_07_KPP_COL04 0x401F8118U, 0x7U, 0, 0, 0x401F8308U + +#define IOMUXC_GPIO_AD_B1_08_FLEXSPIA_SS1_B 0x401F811CU, 0x0U, 0, 0, 0x401F830CU +#define IOMUXC_GPIO_AD_B1_08_FLEXPWM4_PWMA00 0x401F811CU, 0x1U, 0x401F8494U, 0x1U, 0x401F830CU +#define IOMUXC_GPIO_AD_B1_08_FLEXCAN1_TX 0x401F811CU, 0x2U, 0, 0, 0x401F830CU +#define IOMUXC_GPIO_AD_B1_08_CCM_PMIC_READY 0x401F811CU, 0x3U, 0x401F83FCU, 0x3U, 0x401F830CU +#define IOMUXC_GPIO_AD_B1_08_CSI_DATA09 0x401F811CU, 0x4U, 0x401F841CU, 0x0U, 0x401F830CU +#define IOMUXC_GPIO_AD_B1_08_GPIO1_IO24 0x401F811CU, 0x5U, 0, 0, 0x401F830CU +#define IOMUXC_GPIO_AD_B1_08_USDHC2_CMD 0x401F811CU, 0x6U, 0x401F85E4U, 0x1U, 0x401F830CU +#define IOMUXC_GPIO_AD_B1_08_KPP_ROW03 0x401F811CU, 0x7U, 0, 0, 0x401F830CU + +#define IOMUXC_GPIO_AD_B1_09_FLEXSPIA_DQS 0x401F8120U, 0x0U, 0x401F84A4U, 0x1U, 0x401F8310U +#define IOMUXC_GPIO_AD_B1_09_FLEXPWM4_PWMA01 0x401F8120U, 0x1U, 0x401F8498U, 0x1U, 0x401F8310U +#define IOMUXC_GPIO_AD_B1_09_FLEXCAN1_RX 0x401F8120U, 0x2U, 0x401F844CU, 0x2U, 0x401F8310U +#define IOMUXC_GPIO_AD_B1_09_SAI1_MCLK 0x401F8120U, 0x3U, 0x401F858CU, 0x1U, 0x401F8310U +#define IOMUXC_GPIO_AD_B1_09_CSI_DATA08 0x401F8120U, 0x4U, 0x401F8418U, 0x0U, 0x401F8310U +#define IOMUXC_GPIO_AD_B1_09_GPIO1_IO25 0x401F8120U, 0x5U, 0, 0, 0x401F8310U +#define IOMUXC_GPIO_AD_B1_09_USDHC2_CLK 0x401F8120U, 0x6U, 0x401F85DCU, 0x1U, 0x401F8310U +#define IOMUXC_GPIO_AD_B1_09_KPP_COL03 0x401F8120U, 0x7U, 0, 0, 0x401F8310U + +#define IOMUXC_GPIO_AD_B1_10_FLEXSPIA_DATA03 0x401F8124U, 0x0U, 0x401F84B4U, 0x1U, 0x401F8314U +#define IOMUXC_GPIO_AD_B1_10_WDOG1_B 0x401F8124U, 0x1U, 0, 0, 0x401F8314U +#define IOMUXC_GPIO_AD_B1_10_LPUART8_TX 0x401F8124U, 0x2U, 0x401F8564U, 0x1U, 0x401F8314U +#define IOMUXC_GPIO_AD_B1_10_SAI1_RX_SYNC 0x401F8124U, 0x3U, 0x401F85A4U, 0x1U, 0x401F8314U +#define IOMUXC_GPIO_AD_B1_10_CSI_DATA07 0x401F8124U, 0x4U, 0x401F8414U, 0x0U, 0x401F8314U +#define IOMUXC_GPIO_AD_B1_10_GPIO1_IO26 0x401F8124U, 0x5U, 0, 0, 0x401F8314U +#define IOMUXC_GPIO_AD_B1_10_USDHC2_WP 0x401F8124U, 0x6U, 0x401F8608U, 0x1U, 0x401F8314U +#define IOMUXC_GPIO_AD_B1_10_KPP_ROW02 0x401F8124U, 0x7U, 0, 0, 0x401F8314U + +#define IOMUXC_GPIO_AD_B1_11_FLEXSPIA_DATA02 0x401F8128U, 0x0U, 0x401F84B0U, 0x1U, 0x401F8318U +#define IOMUXC_GPIO_AD_B1_11_EWM_OUT_B 0x401F8128U, 0x1U, 0, 0, 0x401F8318U +#define IOMUXC_GPIO_AD_B1_11_LPUART8_RX 0x401F8128U, 0x2U, 0x401F8560U, 0x1U, 0x401F8318U +#define IOMUXC_GPIO_AD_B1_11_SAI1_RX_BCLK 0x401F8128U, 0x3U, 0x401F8590U, 0x1U, 0x401F8318U +#define IOMUXC_GPIO_AD_B1_11_CSI_DATA06 0x401F8128U, 0x4U, 0x401F8410U, 0x0U, 0x401F8318U +#define IOMUXC_GPIO_AD_B1_11_GPIO1_IO27 0x401F8128U, 0x5U, 0, 0, 0x401F8318U +#define IOMUXC_GPIO_AD_B1_11_USDHC2_RESET_B 0x401F8128U, 0x6U, 0, 0, 0x401F8318U +#define IOMUXC_GPIO_AD_B1_11_KPP_COL02 0x401F8128U, 0x7U, 0, 0, 0x401F8318U + +#define IOMUXC_GPIO_AD_B1_12_FLEXSPIA_DATA01 0x401F812CU, 0x0U, 0x401F84ACU, 0x1U, 0x401F831CU +#define IOMUXC_GPIO_AD_B1_12_ACMP_OUT00 0x401F812CU, 0x1U, 0, 0, 0x401F831CU +#define IOMUXC_GPIO_AD_B1_12_LPSPI3_PCS0 0x401F812CU, 0x2U, 0x401F850CU, 0x1U, 0x401F831CU +#define IOMUXC_GPIO_AD_B1_12_SAI1_RX_DATA00 0x401F812CU, 0x3U, 0x401F8594U, 0x1U, 0x401F831CU +#define IOMUXC_GPIO_AD_B1_12_CSI_DATA05 0x401F812CU, 0x4U, 0x401F840CU, 0x0U, 0x401F831CU +#define IOMUXC_GPIO_AD_B1_12_GPIO1_IO28 0x401F812CU, 0x5U, 0, 0, 0x401F831CU +#define IOMUXC_GPIO_AD_B1_12_USDHC2_DATA4 0x401F812CU, 0x6U, 0x401F85F8U, 0x1U, 0x401F831CU +#define IOMUXC_GPIO_AD_B1_12_KPP_ROW01 0x401F812CU, 0x7U, 0, 0, 0x401F831CU + +#define IOMUXC_GPIO_AD_B1_13_FLEXSPIA_DATA00 0x401F8130U, 0x0U, 0x401F84A8U, 0x1U, 0x401F8320U +#define IOMUXC_GPIO_AD_B1_13_ACMP_OUT01 0x401F8130U, 0x1U, 0, 0, 0x401F8320U +#define IOMUXC_GPIO_AD_B1_13_LPSPI3_SDI 0x401F8130U, 0x2U, 0x401F8514U, 0x1U, 0x401F8320U +#define IOMUXC_GPIO_AD_B1_13_SAI1_TX_DATA00 0x401F8130U, 0x3U, 0, 0, 0x401F8320U +#define IOMUXC_GPIO_AD_B1_13_CSI_DATA04 0x401F8130U, 0x4U, 0x401F8408U, 0x0U, 0x401F8320U +#define IOMUXC_GPIO_AD_B1_13_GPIO1_IO29 0x401F8130U, 0x5U, 0, 0, 0x401F8320U +#define IOMUXC_GPIO_AD_B1_13_USDHC2_DATA5 0x401F8130U, 0x6U, 0x401F85FCU, 0x1U, 0x401F8320U +#define IOMUXC_GPIO_AD_B1_13_KPP_COL01 0x401F8130U, 0x7U, 0, 0, 0x401F8320U + +#define IOMUXC_GPIO_AD_B1_14_FLEXSPIA_SCLK 0x401F8134U, 0x0U, 0x401F84C8U, 0x1U, 0x401F8324U +#define IOMUXC_GPIO_AD_B1_14_ACMP_OUT02 0x401F8134U, 0x1U, 0, 0, 0x401F8324U +#define IOMUXC_GPIO_AD_B1_14_LPSPI3_SDO 0x401F8134U, 0x2U, 0x401F8518U, 0x1U, 0x401F8324U +#define IOMUXC_GPIO_AD_B1_14_SAI1_TX_BCLK 0x401F8134U, 0x3U, 0x401F85A8U, 0x1U, 0x401F8324U +#define IOMUXC_GPIO_AD_B1_14_CSI_DATA03 0x401F8134U, 0x4U, 0x401F8404U, 0x0U, 0x401F8324U +#define IOMUXC_GPIO_AD_B1_14_GPIO1_IO30 0x401F8134U, 0x5U, 0, 0, 0x401F8324U +#define IOMUXC_GPIO_AD_B1_14_USDHC2_DATA6 0x401F8134U, 0x6U, 0x401F8600U, 0x1U, 0x401F8324U +#define IOMUXC_GPIO_AD_B1_14_KPP_ROW00 0x401F8134U, 0x7U, 0, 0, 0x401F8324U + +#define IOMUXC_GPIO_AD_B1_15_FLEXSPIA_SS0_B 0x401F8138U, 0x0U, 0, 0, 0x401F8328U +#define IOMUXC_GPIO_AD_B1_15_ACMP_OUT03 0x401F8138U, 0x1U, 0, 0, 0x401F8328U +#define IOMUXC_GPIO_AD_B1_15_LPSPI3_SCK 0x401F8138U, 0x2U, 0, 0, 0x401F8328U +#define IOMUXC_GPIO_AD_B1_15_SAI1_TX_SYNC 0x401F8138U, 0x3U, 0x401F85ACU, 0x1U, 0x401F8328U +#define IOMUXC_GPIO_AD_B1_15_CSI_DATA02 0x401F8138U, 0x4U, 0x401F8400U, 0x0U, 0x401F8328U +#define IOMUXC_GPIO_AD_B1_15_GPIO1_IO31 0x401F8138U, 0x5U, 0, 0, 0x401F8328U +#define IOMUXC_GPIO_AD_B1_15_USDHC2_DATA7 0x401F8138U, 0x6U, 0x401F8604U, 0x1U, 0x401F8328U +#define IOMUXC_GPIO_AD_B1_15_KPP_COL00 0x401F8138U, 0x7U, 0, 0, 0x401F8328U + +#define IOMUXC_GPIO_B0_00_LCD_CLK 0x401F813CU, 0x0U, 0, 0, 0x401F832CU +#define IOMUXC_GPIO_B0_00_QTIMER1_TIMER0 0x401F813CU, 0x1U, 0, 0, 0x401F832CU +#define IOMUXC_GPIO_B0_00_MQS_RIGHT 0x401F813CU, 0x2U, 0, 0, 0x401F832CU +#define IOMUXC_GPIO_B0_00_LPSPI4_PCS0 0x401F813CU, 0x3U, 0x401F851CU, 0x0U, 0x401F832CU +#define IOMUXC_GPIO_B0_00_FLEXIO2_FLEXIO00 0x401F813CU, 0x4U, 0, 0, 0x401F832CU +#define IOMUXC_GPIO_B0_00_GPIO2_IO00 0x401F813CU, 0x5U, 0, 0, 0x401F832CU +#define IOMUXC_GPIO_B0_00_SEMC_CSX01 0x401F813CU, 0x6U, 0, 0, 0x401F832CU + +#define IOMUXC_GPIO_B0_01_LCD_ENABLE 0x401F8140U, 0x0U, 0, 0, 0x401F8330U +#define IOMUXC_GPIO_B0_01_QTIMER1_TIMER1 0x401F8140U, 0x1U, 0, 0, 0x401F8330U +#define IOMUXC_GPIO_B0_01_MQS_LEFT 0x401F8140U, 0x2U, 0, 0, 0x401F8330U +#define IOMUXC_GPIO_B0_01_LPSPI4_SDI 0x401F8140U, 0x3U, 0x401F8524U, 0x0U, 0x401F8330U +#define IOMUXC_GPIO_B0_01_FLEXIO2_FLEXIO01 0x401F8140U, 0x4U, 0, 0, 0x401F8330U +#define IOMUXC_GPIO_B0_01_GPIO2_IO01 0x401F8140U, 0x5U, 0, 0, 0x401F8330U +#define IOMUXC_GPIO_B0_01_SEMC_CSX02 0x401F8140U, 0x6U, 0, 0, 0x401F8330U + +#define IOMUXC_GPIO_B0_02_LCD_HSYNC 0x401F8144U, 0x0U, 0, 0, 0x401F8334U +#define IOMUXC_GPIO_B0_02_QTIMER1_TIMER2 0x401F8144U, 0x1U, 0, 0, 0x401F8334U +#define IOMUXC_GPIO_B0_02_FLEXCAN1_TX 0x401F8144U, 0x2U, 0, 0, 0x401F8334U +#define IOMUXC_GPIO_B0_02_LPSPI4_SDO 0x401F8144U, 0x3U, 0x401F8528U, 0x0U, 0x401F8334U +#define IOMUXC_GPIO_B0_02_FLEXIO2_FLEXIO02 0x401F8144U, 0x4U, 0, 0, 0x401F8334U +#define IOMUXC_GPIO_B0_02_GPIO2_IO02 0x401F8144U, 0x5U, 0, 0, 0x401F8334U +#define IOMUXC_GPIO_B0_02_SEMC_CSX03 0x401F8144U, 0x6U, 0, 0, 0x401F8334U + +#define IOMUXC_GPIO_B0_03_LCD_VSYNC 0x401F8148U, 0x0U, 0, 0, 0x401F8338U +#define IOMUXC_GPIO_B0_03_QTIMER2_TIMER0 0x401F8148U, 0x1U, 0x401F856CU, 0x1U, 0x401F8338U +#define IOMUXC_GPIO_B0_03_FLEXCAN1_RX 0x401F8148U, 0x2U, 0x401F844CU, 0x3U, 0x401F8338U +#define IOMUXC_GPIO_B0_03_LPSPI4_SCK 0x401F8148U, 0x3U, 0x401F8520U, 0x0U, 0x401F8338U +#define IOMUXC_GPIO_B0_03_FLEXIO2_FLEXIO03 0x401F8148U, 0x4U, 0, 0, 0x401F8338U +#define IOMUXC_GPIO_B0_03_GPIO2_IO03 0x401F8148U, 0x5U, 0, 0, 0x401F8338U +#define IOMUXC_GPIO_B0_03_WDOG2_RESET_B_DEB 0x401F8148U, 0x6U, 0, 0, 0x401F8338U + +#define IOMUXC_GPIO_B0_04_LCD_DATA00 0x401F814CU, 0x0U, 0, 0, 0x401F833CU +#define IOMUXC_GPIO_B0_04_QTIMER2_TIMER1 0x401F814CU, 0x1U, 0x401F8570U, 0x1U, 0x401F833CU +#define IOMUXC_GPIO_B0_04_LPI2C2_SCL 0x401F814CU, 0x2U, 0x401F84D4U, 0x1U, 0x401F833CU +#define IOMUXC_GPIO_B0_04_ARM_CM7_TRACE00 0x401F814CU, 0x3U, 0, 0, 0x401F833CU +#define IOMUXC_GPIO_B0_04_FLEXIO2_FLEXIO04 0x401F814CU, 0x4U, 0, 0, 0x401F833CU +#define IOMUXC_GPIO_B0_04_GPIO2_IO04 0x401F814CU, 0x5U, 0, 0, 0x401F833CU +#define IOMUXC_GPIO_B0_04_SRC_BOOT_CFG00 0x401F814CU, 0x6U, 0, 0, 0x401F833CU + +#define IOMUXC_GPIO_B0_05_LCD_DATA01 0x401F8150U, 0x0U, 0, 0, 0x401F8340U +#define IOMUXC_GPIO_B0_05_QTIMER2_TIMER2 0x401F8150U, 0x1U, 0x401F8574U, 0x1U, 0x401F8340U +#define IOMUXC_GPIO_B0_05_LPI2C2_SDA 0x401F8150U, 0x2U, 0x401F84D8U, 0x1U, 0x401F8340U +#define IOMUXC_GPIO_B0_05_ARM_CM7_TRACE01 0x401F8150U, 0x3U, 0, 0, 0x401F8340U +#define IOMUXC_GPIO_B0_05_FLEXIO2_FLEXIO05 0x401F8150U, 0x4U, 0, 0, 0x401F8340U +#define IOMUXC_GPIO_B0_05_GPIO2_IO05 0x401F8150U, 0x5U, 0, 0, 0x401F8340U +#define IOMUXC_GPIO_B0_05_SRC_BOOT_CFG01 0x401F8150U, 0x6U, 0, 0, 0x401F8340U + +#define IOMUXC_GPIO_B0_06_LCD_DATA02 0x401F8154U, 0x0U, 0, 0, 0x401F8344U +#define IOMUXC_GPIO_B0_06_QTIMER3_TIMER0 0x401F8154U, 0x1U, 0x401F857CU, 0x2U, 0x401F8344U +#define IOMUXC_GPIO_B0_06_FLEXPWM2_PWMA00 0x401F8154U, 0x2U, 0x401F8478U, 0x1U, 0x401F8344U +#define IOMUXC_GPIO_B0_06_ARM_CM7_TRACE02 0x401F8154U, 0x3U, 0, 0, 0x401F8344U +#define IOMUXC_GPIO_B0_06_FLEXIO2_FLEXIO06 0x401F8154U, 0x4U, 0, 0, 0x401F8344U +#define IOMUXC_GPIO_B0_06_GPIO2_IO06 0x401F8154U, 0x5U, 0, 0, 0x401F8344U +#define IOMUXC_GPIO_B0_06_SRC_BOOT_CFG02 0x401F8154U, 0x6U, 0, 0, 0x401F8344U + +#define IOMUXC_GPIO_B0_07_LCD_DATA03 0x401F8158U, 0x0U, 0, 0, 0x401F8348U +#define IOMUXC_GPIO_B0_07_QTIMER3_TIMER1 0x401F8158U, 0x1U, 0x401F8580U, 0x2U, 0x401F8348U +#define IOMUXC_GPIO_B0_07_FLEXPWM2_PWMB00 0x401F8158U, 0x2U, 0x401F8488U, 0x1U, 0x401F8348U +#define IOMUXC_GPIO_B0_07_ARM_CM7_TRACE03 0x401F8158U, 0x3U, 0, 0, 0x401F8348U +#define IOMUXC_GPIO_B0_07_FLEXIO2_FLEXIO07 0x401F8158U, 0x4U, 0, 0, 0x401F8348U +#define IOMUXC_GPIO_B0_07_GPIO2_IO07 0x401F8158U, 0x5U, 0, 0, 0x401F8348U +#define IOMUXC_GPIO_B0_07_SRC_BOOT_CFG03 0x401F8158U, 0x6U, 0, 0, 0x401F8348U + +#define IOMUXC_GPIO_B0_08_LCD_DATA04 0x401F815CU, 0x0U, 0, 0, 0x401F834CU +#define IOMUXC_GPIO_B0_08_QTIMER3_TIMER2 0x401F815CU, 0x1U, 0x401F8584U, 0x2U, 0x401F834CU +#define IOMUXC_GPIO_B0_08_FLEXPWM2_PWMA01 0x401F815CU, 0x2U, 0x401F847CU, 0x1U, 0x401F834CU +#define IOMUXC_GPIO_B0_08_LPUART3_TX 0x401F815CU, 0x3U, 0x401F853CU, 0x2U, 0x401F834CU +#define IOMUXC_GPIO_B0_08_FLEXIO2_FLEXIO08 0x401F815CU, 0x4U, 0, 0, 0x401F834CU +#define IOMUXC_GPIO_B0_08_GPIO2_IO08 0x401F815CU, 0x5U, 0, 0, 0x401F834CU +#define IOMUXC_GPIO_B0_08_SRC_BOOT_CFG04 0x401F815CU, 0x6U, 0, 0, 0x401F834CU + +#define IOMUXC_GPIO_B0_09_LCD_DATA05 0x401F8160U, 0x0U, 0, 0, 0x401F8350U +#define IOMUXC_GPIO_B0_09_QTIMER4_TIMER0 0x401F8160U, 0x1U, 0, 0, 0x401F8350U +#define IOMUXC_GPIO_B0_09_FLEXPWM2_PWMB01 0x401F8160U, 0x2U, 0x401F848CU, 0x1U, 0x401F8350U +#define IOMUXC_GPIO_B0_09_LPUART3_RX 0x401F8160U, 0x3U, 0x401F8538U, 0x2U, 0x401F8350U +#define IOMUXC_GPIO_B0_09_FLEXIO2_FLEXIO09 0x401F8160U, 0x4U, 0, 0, 0x401F8350U +#define IOMUXC_GPIO_B0_09_GPIO2_IO09 0x401F8160U, 0x5U, 0, 0, 0x401F8350U +#define IOMUXC_GPIO_B0_09_SRC_BOOT_CFG05 0x401F8160U, 0x6U, 0, 0, 0x401F8350U + +#define IOMUXC_GPIO_B0_10_LCD_DATA06 0x401F8164U, 0x0U, 0, 0, 0x401F8354U +#define IOMUXC_GPIO_B0_10_QTIMER4_TIMER1 0x401F8164U, 0x1U, 0, 0, 0x401F8354U +#define IOMUXC_GPIO_B0_10_FLEXPWM2_PWMA02 0x401F8164U, 0x2U, 0x401F8480U, 0x1U, 0x401F8354U +#define IOMUXC_GPIO_B0_10_SAI1_TX_DATA03 0x401F8164U, 0x3U, 0x401F8598U, 0x1U, 0x401F8354U +#define IOMUXC_GPIO_B0_10_FLEXIO2_FLEXIO10 0x401F8164U, 0x4U, 0, 0, 0x401F8354U +#define IOMUXC_GPIO_B0_10_GPIO2_IO10 0x401F8164U, 0x5U, 0, 0, 0x401F8354U +#define IOMUXC_GPIO_B0_10_SRC_BOOT_CFG06 0x401F8164U, 0x6U, 0, 0, 0x401F8354U + +#define IOMUXC_GPIO_B0_11_LCD_DATA07 0x401F8168U, 0x0U, 0, 0, 0x401F8358U +#define IOMUXC_GPIO_B0_11_QTIMER4_TIMER2 0x401F8168U, 0x1U, 0, 0, 0x401F8358U +#define IOMUXC_GPIO_B0_11_FLEXPWM2_PWMB02 0x401F8168U, 0x2U, 0x401F8490U, 0x1U, 0x401F8358U +#define IOMUXC_GPIO_B0_11_SAI1_TX_DATA02 0x401F8168U, 0x3U, 0x401F859CU, 0x1U, 0x401F8358U +#define IOMUXC_GPIO_B0_11_FLEXIO2_FLEXIO11 0x401F8168U, 0x4U, 0, 0, 0x401F8358U +#define IOMUXC_GPIO_B0_11_GPIO2_IO11 0x401F8168U, 0x5U, 0, 0, 0x401F8358U +#define IOMUXC_GPIO_B0_11_SRC_BOOT_CFG07 0x401F8168U, 0x6U, 0, 0, 0x401F8358U + +#define IOMUXC_GPIO_B0_12_LCD_DATA08 0x401F816CU, 0x0U, 0, 0, 0x401F835CU +#define IOMUXC_GPIO_B0_12_XBAR1_INOUT10 0x401F816CU, 0x1U, 0, 0, 0x401F835CU +#define IOMUXC_GPIO_B0_12_ARM_CM7_TRACE_CLK 0x401F816CU, 0x2U, 0, 0, 0x401F835CU +#define IOMUXC_GPIO_B0_12_SAI1_TX_DATA01 0x401F816CU, 0x3U, 0x401F85A0U, 0x1U, 0x401F835CU +#define IOMUXC_GPIO_B0_12_FLEXIO2_FLEXIO12 0x401F816CU, 0x4U, 0, 0, 0x401F835CU +#define IOMUXC_GPIO_B0_12_GPIO2_IO12 0x401F816CU, 0x5U, 0, 0, 0x401F835CU +#define IOMUXC_GPIO_B0_12_SRC_BOOT_CFG08 0x401F816CU, 0x6U, 0, 0, 0x401F835CU + +#define IOMUXC_GPIO_B0_13_LCD_DATA09 0x401F8170U, 0x0U, 0, 0, 0x401F8360U +#define IOMUXC_GPIO_B0_13_XBAR1_INOUT11 0x401F8170U, 0x1U, 0, 0, 0x401F8360U +#define IOMUXC_GPIO_B0_13_ARM_CM7_TRACE_SWO 0x401F8170U, 0x2U, 0, 0, 0x401F8360U +#define IOMUXC_GPIO_B0_13_SAI1_MCLK 0x401F8170U, 0x3U, 0x401F858CU, 0x2U, 0x401F8360U +#define IOMUXC_GPIO_B0_13_FLEXIO2_FLEXIO13 0x401F8170U, 0x4U, 0, 0, 0x401F8360U +#define IOMUXC_GPIO_B0_13_GPIO2_IO13 0x401F8170U, 0x5U, 0, 0, 0x401F8360U +#define IOMUXC_GPIO_B0_13_SRC_BOOT_CFG09 0x401F8170U, 0x6U, 0, 0, 0x401F8360U + +#define IOMUXC_GPIO_B0_14_LCD_DATA10 0x401F8174U, 0x0U, 0, 0, 0x401F8364U +#define IOMUXC_GPIO_B0_14_XBAR1_INOUT12 0x401F8174U, 0x1U, 0, 0, 0x401F8364U +#define IOMUXC_GPIO_B0_14_ARM_CM7_TXEV 0x401F8174U, 0x2U, 0, 0, 0x401F8364U +#define IOMUXC_GPIO_B0_14_SAI1_RX_SYNC 0x401F8174U, 0x3U, 0x401F85A4U, 0x2U, 0x401F8364U +#define IOMUXC_GPIO_B0_14_FLEXIO2_FLEXIO14 0x401F8174U, 0x4U, 0, 0, 0x401F8364U +#define IOMUXC_GPIO_B0_14_GPIO2_IO14 0x401F8174U, 0x5U, 0, 0, 0x401F8364U +#define IOMUXC_GPIO_B0_14_SRC_BOOT_CFG10 0x401F8174U, 0x6U, 0, 0, 0x401F8364U + +#define IOMUXC_GPIO_B0_15_LCD_DATA11 0x401F8178U, 0x0U, 0, 0, 0x401F8368U +#define IOMUXC_GPIO_B0_15_XBAR1_INOUT13 0x401F8178U, 0x1U, 0, 0, 0x401F8368U +#define IOMUXC_GPIO_B0_15_ARM_CM7_RXEV 0x401F8178U, 0x2U, 0, 0, 0x401F8368U +#define IOMUXC_GPIO_B0_15_SAI1_RX_BCLK 0x401F8178U, 0x3U, 0x401F8590U, 0x2U, 0x401F8368U +#define IOMUXC_GPIO_B0_15_FLEXIO2_FLEXIO15 0x401F8178U, 0x4U, 0, 0, 0x401F8368U +#define IOMUXC_GPIO_B0_15_GPIO2_IO15 0x401F8178U, 0x5U, 0, 0, 0x401F8368U +#define IOMUXC_GPIO_B0_15_SRC_BOOT_CFG11 0x401F8178U, 0x6U, 0, 0, 0x401F8368U + +#define IOMUXC_GPIO_B1_00_LCD_DATA12 0x401F817CU, 0x0U, 0, 0, 0x401F836CU +#define IOMUXC_GPIO_B1_00_XBAR1_INOUT14 0x401F817CU, 0x1U, 0x401F8644U, 0x1U, 0x401F836CU +#define IOMUXC_GPIO_B1_00_LPUART4_TX 0x401F817CU, 0x2U, 0x401F8544U, 0x2U, 0x401F836CU +#define IOMUXC_GPIO_B1_00_SAI1_RX_DATA00 0x401F817CU, 0x3U, 0x401F8594U, 0x2U, 0x401F836CU +#define IOMUXC_GPIO_B1_00_FLEXIO2_FLEXIO16 0x401F817CU, 0x4U, 0, 0, 0x401F836CU +#define IOMUXC_GPIO_B1_00_GPIO2_IO16 0x401F817CU, 0x5U, 0, 0, 0x401F836CU +#define IOMUXC_GPIO_B1_00_FLEXPWM1_PWMA03 0x401F817CU, 0x6U, 0x401F8454U, 0x4U, 0x401F836CU + +#define IOMUXC_GPIO_B1_01_LCD_DATA13 0x401F8180U, 0x0U, 0, 0, 0x401F8370U +#define IOMUXC_GPIO_B1_01_XBAR1_INOUT15 0x401F8180U, 0x1U, 0x401F8648U, 0x1U, 0x401F8370U +#define IOMUXC_GPIO_B1_01_LPUART4_RX 0x401F8180U, 0x2U, 0x401F8540U, 0x2U, 0x401F8370U +#define IOMUXC_GPIO_B1_01_SAI1_TX_DATA00 0x401F8180U, 0x3U, 0, 0, 0x401F8370U +#define IOMUXC_GPIO_B1_01_FLEXIO2_FLEXIO17 0x401F8180U, 0x4U, 0, 0, 0x401F8370U +#define IOMUXC_GPIO_B1_01_GPIO2_IO17 0x401F8180U, 0x5U, 0, 0, 0x401F8370U +#define IOMUXC_GPIO_B1_01_FLEXPWM1_PWMB03 0x401F8180U, 0x6U, 0x401F8464U, 0x4U, 0x401F8370U + +#define IOMUXC_GPIO_B1_02_LCD_DATA14 0x401F8184U, 0x0U, 0, 0, 0x401F8374U +#define IOMUXC_GPIO_B1_02_XBAR1_INOUT16 0x401F8184U, 0x1U, 0x401F864CU, 0x1U, 0x401F8374U +#define IOMUXC_GPIO_B1_02_LPSPI4_PCS2 0x401F8184U, 0x2U, 0, 0, 0x401F8374U +#define IOMUXC_GPIO_B1_02_SAI1_TX_BCLK 0x401F8184U, 0x3U, 0x401F85A8U, 0x2U, 0x401F8374U +#define IOMUXC_GPIO_B1_02_FLEXIO2_FLEXIO18 0x401F8184U, 0x4U, 0, 0, 0x401F8374U +#define IOMUXC_GPIO_B1_02_GPIO2_IO18 0x401F8184U, 0x5U, 0, 0, 0x401F8374U +#define IOMUXC_GPIO_B1_02_FLEXPWM2_PWMA03 0x401F8184U, 0x6U, 0x401F8474U, 0x4U, 0x401F8374U + +#define IOMUXC_GPIO_B1_03_LCD_DATA15 0x401F8188U, 0x0U, 0, 0, 0x401F8378U +#define IOMUXC_GPIO_B1_03_XBAR1_INOUT17 0x401F8188U, 0x1U, 0x401F862CU, 0x3U, 0x401F8378U +#define IOMUXC_GPIO_B1_03_LPSPI4_PCS1 0x401F8188U, 0x2U, 0, 0, 0x401F8378U +#define IOMUXC_GPIO_B1_03_SAI1_TX_SYNC 0x401F8188U, 0x3U, 0x401F85ACU, 0x2U, 0x401F8378U +#define IOMUXC_GPIO_B1_03_FLEXIO2_FLEXIO19 0x401F8188U, 0x4U, 0, 0, 0x401F8378U +#define IOMUXC_GPIO_B1_03_GPIO2_IO19 0x401F8188U, 0x5U, 0, 0, 0x401F8378U +#define IOMUXC_GPIO_B1_03_FLEXPWM2_PWMB03 0x401F8188U, 0x6U, 0x401F8484U, 0x3U, 0x401F8378U + +#define IOMUXC_GPIO_B1_04_LCD_DATA16 0x401F818CU, 0x0U, 0, 0, 0x401F837CU +#define IOMUXC_GPIO_B1_04_LPSPI4_PCS0 0x401F818CU, 0x1U, 0x401F851CU, 0x1U, 0x401F837CU +#define IOMUXC_GPIO_B1_04_CSI_DATA15 0x401F818CU, 0x2U, 0, 0, 0x401F837CU +#define IOMUXC_GPIO_B1_04_ENET_RX_DATA00 0x401F818CU, 0x3U, 0x401F8434U, 0x1U, 0x401F837CU +#define IOMUXC_GPIO_B1_04_FLEXIO2_FLEXIO20 0x401F818CU, 0x4U, 0, 0, 0x401F837CU +#define IOMUXC_GPIO_B1_04_GPIO2_IO20 0x401F818CU, 0x5U, 0, 0, 0x401F837CU + +#define IOMUXC_GPIO_B1_05_LCD_DATA17 0x401F8190U, 0x0U, 0, 0, 0x401F8380U +#define IOMUXC_GPIO_B1_05_LPSPI4_SDI 0x401F8190U, 0x1U, 0x401F8524U, 0x1U, 0x401F8380U +#define IOMUXC_GPIO_B1_05_CSI_DATA14 0x401F8190U, 0x2U, 0, 0, 0x401F8380U +#define IOMUXC_GPIO_B1_05_ENET_RX_DATA01 0x401F8190U, 0x3U, 0x401F8438U, 0x1U, 0x401F8380U +#define IOMUXC_GPIO_B1_05_FLEXIO2_FLEXIO21 0x401F8190U, 0x4U, 0, 0, 0x401F8380U +#define IOMUXC_GPIO_B1_05_GPIO2_IO21 0x401F8190U, 0x5U, 0, 0, 0x401F8380U + +#define IOMUXC_GPIO_B1_06_LCD_DATA18 0x401F8194U, 0x0U, 0, 0, 0x401F8384U +#define IOMUXC_GPIO_B1_06_LPSPI4_SDO 0x401F8194U, 0x1U, 0x401F8528U, 0x1U, 0x401F8384U +#define IOMUXC_GPIO_B1_06_CSI_DATA13 0x401F8194U, 0x2U, 0, 0, 0x401F8384U +#define IOMUXC_GPIO_B1_06_ENET_RX_EN 0x401F8194U, 0x3U, 0x401F843CU, 0x1U, 0x401F8384U +#define IOMUXC_GPIO_B1_06_FLEXIO2_FLEXIO22 0x401F8194U, 0x4U, 0, 0, 0x401F8384U +#define IOMUXC_GPIO_B1_06_GPIO2_IO22 0x401F8194U, 0x5U, 0, 0, 0x401F8384U + +#define IOMUXC_GPIO_B1_07_LCD_DATA19 0x401F8198U, 0x0U, 0, 0, 0x401F8388U +#define IOMUXC_GPIO_B1_07_LPSPI4_SCK 0x401F8198U, 0x1U, 0x401F8520U, 0x1U, 0x401F8388U +#define IOMUXC_GPIO_B1_07_CSI_DATA12 0x401F8198U, 0x2U, 0, 0, 0x401F8388U +#define IOMUXC_GPIO_B1_07_ENET_TX_DATA00 0x401F8198U, 0x3U, 0, 0, 0x401F8388U +#define IOMUXC_GPIO_B1_07_FLEXIO2_FLEXIO23 0x401F8198U, 0x4U, 0, 0, 0x401F8388U +#define IOMUXC_GPIO_B1_07_GPIO2_IO23 0x401F8198U, 0x5U, 0, 0, 0x401F8388U + +#define IOMUXC_GPIO_B1_08_LCD_DATA20 0x401F819CU, 0x0U, 0, 0, 0x401F838CU +#define IOMUXC_GPIO_B1_08_QTIMER1_TIMER3 0x401F819CU, 0x1U, 0, 0, 0x401F838CU +#define IOMUXC_GPIO_B1_08_CSI_DATA11 0x401F819CU, 0x2U, 0, 0, 0x401F838CU +#define IOMUXC_GPIO_B1_08_ENET_TX_DATA01 0x401F819CU, 0x3U, 0, 0, 0x401F838CU +#define IOMUXC_GPIO_B1_08_FLEXIO2_FLEXIO24 0x401F819CU, 0x4U, 0, 0, 0x401F838CU +#define IOMUXC_GPIO_B1_08_GPIO2_IO24 0x401F819CU, 0x5U, 0, 0, 0x401F838CU +#define IOMUXC_GPIO_B1_08_FLEXCAN2_TX 0x401F819CU, 0x6U, 0, 0, 0x401F838CU + +#define IOMUXC_GPIO_B1_09_LCD_DATA21 0x401F81A0U, 0x0U, 0, 0, 0x401F8390U +#define IOMUXC_GPIO_B1_09_QTIMER2_TIMER3 0x401F81A0U, 0x1U, 0x401F8578U, 0x1U, 0x401F8390U +#define IOMUXC_GPIO_B1_09_CSI_DATA10 0x401F81A0U, 0x2U, 0, 0, 0x401F8390U +#define IOMUXC_GPIO_B1_09_ENET_TX_EN 0x401F81A0U, 0x3U, 0, 0, 0x401F8390U +#define IOMUXC_GPIO_B1_09_FLEXIO2_FLEXIO25 0x401F81A0U, 0x4U, 0, 0, 0x401F8390U +#define IOMUXC_GPIO_B1_09_GPIO2_IO25 0x401F81A0U, 0x5U, 0, 0, 0x401F8390U +#define IOMUXC_GPIO_B1_09_FLEXCAN2_RX 0x401F81A0U, 0x6U, 0x401F8450U, 0x3U, 0x401F8390U + +#define IOMUXC_GPIO_B1_10_LCD_DATA22 0x401F81A4U, 0x0U, 0, 0, 0x401F8394U +#define IOMUXC_GPIO_B1_10_QTIMER3_TIMER3 0x401F81A4U, 0x1U, 0x401F8588U, 0x2U, 0x401F8394U +#define IOMUXC_GPIO_B1_10_CSI_DATA00 0x401F81A4U, 0x2U, 0, 0, 0x401F8394U +#define IOMUXC_GPIO_B1_10_ENET_TX_CLK 0x401F81A4U, 0x3U, 0x401F8448U, 0x1U, 0x401F8394U +#define IOMUXC_GPIO_B1_10_FLEXIO2_FLEXIO26 0x401F81A4U, 0x4U, 0, 0, 0x401F8394U +#define IOMUXC_GPIO_B1_10_GPIO2_IO26 0x401F81A4U, 0x5U, 0, 0, 0x401F8394U +#define IOMUXC_GPIO_B1_10_ENET_REF_CLK 0x401F81A4U, 0x6U, 0x401F842CU, 0x1U, 0x401F8394U + +#define IOMUXC_GPIO_B1_11_LCD_DATA23 0x401F81A8U, 0x0U, 0, 0, 0x401F8398U +#define IOMUXC_GPIO_B1_11_QTIMER4_TIMER3 0x401F81A8U, 0x1U, 0, 0, 0x401F8398U +#define IOMUXC_GPIO_B1_11_CSI_DATA01 0x401F81A8U, 0x2U, 0, 0, 0x401F8398U +#define IOMUXC_GPIO_B1_11_ENET_RX_ER 0x401F81A8U, 0x3U, 0x401F8440U, 0x1U, 0x401F8398U +#define IOMUXC_GPIO_B1_11_FLEXIO2_FLEXIO27 0x401F81A8U, 0x4U, 0, 0, 0x401F8398U +#define IOMUXC_GPIO_B1_11_GPIO2_IO27 0x401F81A8U, 0x5U, 0, 0, 0x401F8398U +#define IOMUXC_GPIO_B1_11_LPSPI4_PCS3 0x401F81A8U, 0x6U, 0, 0, 0x401F8398U + +#define IOMUXC_GPIO_B1_12_LPUART5_TX 0x401F81ACU, 0x1U, 0x401F854CU, 0x1U, 0x401F839CU +#define IOMUXC_GPIO_B1_12_CSI_PIXCLK 0x401F81ACU, 0x2U, 0x401F8424U, 0x1U, 0x401F839CU +#define IOMUXC_GPIO_B1_12_ENET_1588_EVENT0_IN 0x401F81ACU, 0x3U, 0x401F8444U, 0x2U, 0x401F839CU +#define IOMUXC_GPIO_B1_12_FLEXIO2_FLEXIO28 0x401F81ACU, 0x4U, 0, 0, 0x401F839CU +#define IOMUXC_GPIO_B1_12_GPIO2_IO28 0x401F81ACU, 0x5U, 0, 0, 0x401F839CU +#define IOMUXC_GPIO_B1_12_USDHC1_CD_B 0x401F81ACU, 0x6U, 0x401F85D4U, 0x2U, 0x401F839CU + +#define IOMUXC_GPIO_B1_13_WDOG1_B 0x401F81B0U, 0x0U, 0, 0, 0x401F83A0U +#define IOMUXC_GPIO_B1_13_LPUART5_RX 0x401F81B0U, 0x1U, 0x401F8548U, 0x1U, 0x401F83A0U +#define IOMUXC_GPIO_B1_13_CSI_VSYNC 0x401F81B0U, 0x2U, 0x401F8428U, 0x2U, 0x401F83A0U +#define IOMUXC_GPIO_B1_13_ENET_1588_EVENT0_OUT 0x401F81B0U, 0x3U, 0, 0, 0x401F83A0U +#define IOMUXC_GPIO_B1_13_FLEXIO2_FLEXIO29 0x401F81B0U, 0x4U, 0, 0, 0x401F83A0U +#define IOMUXC_GPIO_B1_13_GPIO2_IO29 0x401F81B0U, 0x5U, 0, 0, 0x401F83A0U +#define IOMUXC_GPIO_B1_13_USDHC1_WP 0x401F81B0U, 0x6U, 0x401F85D8U, 0x3U, 0x401F83A0U + +#define IOMUXC_GPIO_B1_14_ENET_MDC 0x401F81B4U, 0x0U, 0, 0, 0x401F83A4U +#define IOMUXC_GPIO_B1_14_FLEXPWM4_PWMA02 0x401F81B4U, 0x1U, 0x401F849CU, 0x1U, 0x401F83A4U +#define IOMUXC_GPIO_B1_14_CSI_HSYNC 0x401F81B4U, 0x2U, 0x401F8420U, 0x2U, 0x401F83A4U +#define IOMUXC_GPIO_B1_14_XBAR1_IN02 0x401F81B4U, 0x3U, 0x401F860CU, 0x1U, 0x401F83A4U +#define IOMUXC_GPIO_B1_14_FLEXIO2_FLEXIO30 0x401F81B4U, 0x4U, 0, 0, 0x401F83A4U +#define IOMUXC_GPIO_B1_14_GPIO2_IO30 0x401F81B4U, 0x5U, 0, 0, 0x401F83A4U +#define IOMUXC_GPIO_B1_14_USDHC1_VSELECT 0x401F81B4U, 0x6U, 0, 0, 0x401F83A4U + +#define IOMUXC_GPIO_B1_15_ENET_MDIO 0x401F81B8U, 0x0U, 0x401F8430U, 0x2U, 0x401F83A8U +#define IOMUXC_GPIO_B1_15_FLEXPWM4_PWMA03 0x401F81B8U, 0x1U, 0x401F84A0U, 0x1U, 0x401F83A8U +#define IOMUXC_GPIO_B1_15_CSI_MCLK 0x401F81B8U, 0x2U, 0, 0, 0x401F83A8U +#define IOMUXC_GPIO_B1_15_XBAR1_IN03 0x401F81B8U, 0x3U, 0x401F8610U, 0x1U, 0x401F83A8U +#define IOMUXC_GPIO_B1_15_FLEXIO2_FLEXIO31 0x401F81B8U, 0x4U, 0, 0, 0x401F83A8U +#define IOMUXC_GPIO_B1_15_GPIO2_IO31 0x401F81B8U, 0x5U, 0, 0, 0x401F83A8U +#define IOMUXC_GPIO_B1_15_USDHC1_RESET_B 0x401F81B8U, 0x6U, 0, 0, 0x401F83A8U + +#define IOMUXC_GPIO_SD_B0_00_USDHC1_CMD 0x401F81BCU, 0x0U, 0, 0, 0x401F83ACU +#define IOMUXC_GPIO_SD_B0_00_FLEXPWM1_PWMA00 0x401F81BCU, 0x1U, 0x401F8458U, 0x1U, 0x401F83ACU +#define IOMUXC_GPIO_SD_B0_00_LPI2C3_SCL 0x401F81BCU, 0x2U, 0x401F84DCU, 0x1U, 0x401F83ACU +#define IOMUXC_GPIO_SD_B0_00_XBAR1_INOUT04 0x401F81BCU, 0x3U, 0x401F8614U, 0x1U, 0x401F83ACU +#define IOMUXC_GPIO_SD_B0_00_LPSPI1_SCK 0x401F81BCU, 0x4U, 0x401F84F0U, 0x1U, 0x401F83ACU +#define IOMUXC_GPIO_SD_B0_00_GPIO3_IO12 0x401F81BCU, 0x5U, 0, 0, 0x401F83ACU +#define IOMUXC_GPIO_SD_B0_00_FLEXSPIA_SS1_B 0x401F81BCU, 0x6U, 0, 0, 0x401F83ACU + +#define IOMUXC_GPIO_SD_B0_01_USDHC1_CLK 0x401F81C0U, 0x0U, 0, 0, 0x401F83B0U +#define IOMUXC_GPIO_SD_B0_01_FLEXPWM1_PWMB00 0x401F81C0U, 0x1U, 0x401F8468U, 0x1U, 0x401F83B0U +#define IOMUXC_GPIO_SD_B0_01_LPI2C3_SDA 0x401F81C0U, 0x2U, 0x401F84E0U, 0x1U, 0x401F83B0U +#define IOMUXC_GPIO_SD_B0_01_XBAR1_INOUT05 0x401F81C0U, 0x3U, 0x401F8618U, 0x1U, 0x401F83B0U +#define IOMUXC_GPIO_SD_B0_01_LPSPI1_PCS0 0x401F81C0U, 0x4U, 0x401F84ECU, 0x0U, 0x401F83B0U +#define IOMUXC_GPIO_SD_B0_01_GPIO3_IO13 0x401F81C0U, 0x5U, 0, 0, 0x401F83B0U +#define IOMUXC_GPIO_SD_B0_01_FLEXSPIB_SS1_B 0x401F81C0U, 0x6U, 0, 0, 0x401F83B0U + +#define IOMUXC_GPIO_SD_B0_02_USDHC1_DATA0 0x401F81C4U, 0x0U, 0, 0, 0x401F83B4U +#define IOMUXC_GPIO_SD_B0_02_FLEXPWM1_PWMA01 0x401F81C4U, 0x1U, 0x401F845CU, 0x1U, 0x401F83B4U +#define IOMUXC_GPIO_SD_B0_02_LPUART8_CTS_B 0x401F81C4U, 0x2U, 0, 0, 0x401F83B4U +#define IOMUXC_GPIO_SD_B0_02_XBAR1_INOUT06 0x401F81C4U, 0x3U, 0x401F861CU, 0x1U, 0x401F83B4U +#define IOMUXC_GPIO_SD_B0_02_LPSPI1_SDO 0x401F81C4U, 0x4U, 0x401F84F8U, 0x1U, 0x401F83B4U +#define IOMUXC_GPIO_SD_B0_02_GPIO3_IO14 0x401F81C4U, 0x5U, 0, 0, 0x401F83B4U + +#define IOMUXC_GPIO_SD_B0_03_USDHC1_DATA1 0x401F81C8U, 0x0U, 0, 0, 0x401F83B8U +#define IOMUXC_GPIO_SD_B0_03_FLEXPWM1_PWMB01 0x401F81C8U, 0x1U, 0x401F846CU, 0x1U, 0x401F83B8U +#define IOMUXC_GPIO_SD_B0_03_LPUART8_RTS_B 0x401F81C8U, 0x2U, 0, 0, 0x401F83B8U +#define IOMUXC_GPIO_SD_B0_03_XBAR1_INOUT07 0x401F81C8U, 0x3U, 0x401F8620U, 0x1U, 0x401F83B8U +#define IOMUXC_GPIO_SD_B0_03_LPSPI1_SDI 0x401F81C8U, 0x4U, 0x401F84F4U, 0x1U, 0x401F83B8U +#define IOMUXC_GPIO_SD_B0_03_GPIO3_IO15 0x401F81C8U, 0x5U, 0, 0, 0x401F83B8U + +#define IOMUXC_GPIO_SD_B0_04_USDHC1_DATA2 0x401F81CCU, 0x0U, 0, 0, 0x401F83BCU +#define IOMUXC_GPIO_SD_B0_04_FLEXPWM1_PWMA02 0x401F81CCU, 0x1U, 0x401F8460U, 0x1U, 0x401F83BCU +#define IOMUXC_GPIO_SD_B0_04_LPUART8_TX 0x401F81CCU, 0x2U, 0x401F8564U, 0x0U, 0x401F83BCU +#define IOMUXC_GPIO_SD_B0_04_XBAR1_INOUT08 0x401F81CCU, 0x3U, 0x401F8624U, 0x1U, 0x401F83BCU +#define IOMUXC_GPIO_SD_B0_04_FLEXSPIB_SS0_B 0x401F81CCU, 0x4U, 0, 0, 0x401F83BCU +#define IOMUXC_GPIO_SD_B0_04_GPIO3_IO16 0x401F81CCU, 0x5U, 0, 0, 0x401F83BCU +#define IOMUXC_GPIO_SD_B0_04_CCM_CLKO1 0x401F81CCU, 0x6U, 0, 0, 0x401F83BCU + +#define IOMUXC_GPIO_SD_B0_05_USDHC1_DATA3 0x401F81D0U, 0x0U, 0, 0, 0x401F83C0U +#define IOMUXC_GPIO_SD_B0_05_FLEXPWM1_PWMB02 0x401F81D0U, 0x1U, 0x401F8470U, 0x1U, 0x401F83C0U +#define IOMUXC_GPIO_SD_B0_05_LPUART8_RX 0x401F81D0U, 0x2U, 0x401F8560U, 0x0U, 0x401F83C0U +#define IOMUXC_GPIO_SD_B0_05_XBAR1_INOUT09 0x401F81D0U, 0x3U, 0x401F8628U, 0x1U, 0x401F83C0U +#define IOMUXC_GPIO_SD_B0_05_FLEXSPIB_DQS 0x401F81D0U, 0x4U, 0, 0, 0x401F83C0U +#define IOMUXC_GPIO_SD_B0_05_GPIO3_IO17 0x401F81D0U, 0x5U, 0, 0, 0x401F83C0U +#define IOMUXC_GPIO_SD_B0_05_CCM_CLKO2 0x401F81D0U, 0x6U, 0, 0, 0x401F83C0U + +#define IOMUXC_GPIO_SD_B1_00_USDHC2_DATA3 0x401F81D4U, 0x0U, 0x401F85F4U, 0x0U, 0x401F83C4U +#define IOMUXC_GPIO_SD_B1_00_FLEXSPIB_DATA03 0x401F81D4U, 0x1U, 0x401F84C4U, 0x0U, 0x401F83C4U +#define IOMUXC_GPIO_SD_B1_00_FLEXPWM1_PWMA03 0x401F81D4U, 0x2U, 0x401F8454U, 0x0U, 0x401F83C4U +#define IOMUXC_GPIO_SD_B1_00_SAI1_TX_DATA03 0x401F81D4U, 0x3U, 0x401F8598U, 0x0U, 0x401F83C4U +#define IOMUXC_GPIO_SD_B1_00_LPUART4_TX 0x401F81D4U, 0x4U, 0x401F8544U, 0x0U, 0x401F83C4U +#define IOMUXC_GPIO_SD_B1_00_GPIO3_IO00 0x401F81D4U, 0x5U, 0, 0, 0x401F83C4U + +#define IOMUXC_GPIO_SD_B1_01_USDHC2_DATA2 0x401F81D8U, 0x0U, 0x401F85F0U, 0x0U, 0x401F83C8U +#define IOMUXC_GPIO_SD_B1_01_FLEXSPIB_DATA02 0x401F81D8U, 0x1U, 0x401F84C0U, 0x0U, 0x401F83C8U +#define IOMUXC_GPIO_SD_B1_01_FLEXPWM1_PWMB03 0x401F81D8U, 0x2U, 0x401F8464U, 0x0U, 0x401F83C8U +#define IOMUXC_GPIO_SD_B1_01_SAI1_TX_DATA02 0x401F81D8U, 0x3U, 0x401F859CU, 0x0U, 0x401F83C8U +#define IOMUXC_GPIO_SD_B1_01_LPUART4_RX 0x401F81D8U, 0x4U, 0x401F8540U, 0x0U, 0x401F83C8U +#define IOMUXC_GPIO_SD_B1_01_GPIO3_IO01 0x401F81D8U, 0x5U, 0, 0, 0x401F83C8U + +#define IOMUXC_GPIO_SD_B1_02_USDHC2_DATA1 0x401F81DCU, 0x0U, 0x401F85ECU, 0x0U, 0x401F83CCU +#define IOMUXC_GPIO_SD_B1_02_FLEXSPIB_DATA01 0x401F81DCU, 0x1U, 0x401F84BCU, 0x0U, 0x401F83CCU +#define IOMUXC_GPIO_SD_B1_02_FLEXPWM2_PWMA03 0x401F81DCU, 0x2U, 0x401F8474U, 0x0U, 0x401F83CCU +#define IOMUXC_GPIO_SD_B1_02_SAI1_TX_DATA01 0x401F81DCU, 0x3U, 0x401F85A0U, 0x0U, 0x401F83CCU +#define IOMUXC_GPIO_SD_B1_02_FLEXCAN1_TX 0x401F81DCU, 0x4U, 0, 0, 0x401F83CCU +#define IOMUXC_GPIO_SD_B1_02_GPIO3_IO02 0x401F81DCU, 0x5U, 0, 0, 0x401F83CCU +#define IOMUXC_GPIO_SD_B1_02_CCM_WAIT 0x401F81DCU, 0x6U, 0, 0, 0x401F83CCU + +#define IOMUXC_GPIO_SD_B1_03_USDHC2_DATA0 0x401F81E0U, 0x0U, 0x401F85E8U, 0x0U, 0x401F83D0U +#define IOMUXC_GPIO_SD_B1_03_FLEXSPIB_DATA00 0x401F81E0U, 0x1U, 0x401F84B8U, 0x0U, 0x401F83D0U +#define IOMUXC_GPIO_SD_B1_03_FLEXPWM2_PWMB03 0x401F81E0U, 0x2U, 0x401F8484U, 0x0U, 0x401F83D0U +#define IOMUXC_GPIO_SD_B1_03_SAI1_MCLK 0x401F81E0U, 0x3U, 0x401F858CU, 0x0U, 0x401F83D0U +#define IOMUXC_GPIO_SD_B1_03_FLEXCAN1_RX 0x401F81E0U, 0x4U, 0x401F844CU, 0x0U, 0x401F83D0U +#define IOMUXC_GPIO_SD_B1_03_GPIO3_IO03 0x401F81E0U, 0x5U, 0, 0, 0x401F83D0U +#define IOMUXC_GPIO_SD_B1_03_CCM_PMIC_READY 0x401F81E0U, 0x6U, 0x401F83FCU, 0x0U, 0x401F83D0U + +#define IOMUXC_GPIO_SD_B1_04_USDHC2_CLK 0x401F81E4U, 0x0U, 0x401F85DCU, 0x0U, 0x401F83D4U +#define IOMUXC_GPIO_SD_B1_04_FLEXSPIB_SCLK 0x401F81E4U, 0x1U, 0, 0, 0x401F83D4U +#define IOMUXC_GPIO_SD_B1_04_LPI2C1_SCL 0x401F81E4U, 0x2U, 0x401F84CCU, 0x0U, 0x401F83D4U +#define IOMUXC_GPIO_SD_B1_04_SAI1_RX_SYNC 0x401F81E4U, 0x3U, 0x401F85A4U, 0x0U, 0x401F83D4U +#define IOMUXC_GPIO_SD_B1_04_FLEXSPIA_SS1_B 0x401F81E4U, 0x4U, 0, 0, 0x401F83D4U +#define IOMUXC_GPIO_SD_B1_04_GPIO3_IO04 0x401F81E4U, 0x5U, 0, 0, 0x401F83D4U +#define IOMUXC_GPIO_SD_B1_04_CCM_STOP 0x401F81E4U, 0x6U, 0, 0, 0x401F83D4U + +#define IOMUXC_GPIO_SD_B1_05_USDHC2_CMD 0x401F81E8U, 0x0U, 0x401F85E4U, 0x0U, 0x401F83D8U +#define IOMUXC_GPIO_SD_B1_05_FLEXSPIA_DQS 0x401F81E8U, 0x1U, 0x401F84A4U, 0x0U, 0x401F83D8U +#define IOMUXC_GPIO_SD_B1_05_LPI2C1_SDA 0x401F81E8U, 0x2U, 0x401F84D0U, 0x0U, 0x401F83D8U +#define IOMUXC_GPIO_SD_B1_05_SAI1_RX_BCLK 0x401F81E8U, 0x3U, 0x401F8590U, 0x0U, 0x401F83D8U +#define IOMUXC_GPIO_SD_B1_05_FLEXSPIB_SS0_B 0x401F81E8U, 0x4U, 0, 0, 0x401F83D8U +#define IOMUXC_GPIO_SD_B1_05_GPIO3_IO05 0x401F81E8U, 0x5U, 0, 0, 0x401F83D8U + +#define IOMUXC_GPIO_SD_B1_06_USDHC2_RESET_B 0x401F81ECU, 0x0U, 0, 0, 0x401F83DCU +#define IOMUXC_GPIO_SD_B1_06_FLEXSPIA_SS0_B 0x401F81ECU, 0x1U, 0, 0, 0x401F83DCU +#define IOMUXC_GPIO_SD_B1_06_LPUART7_CTS_B 0x401F81ECU, 0x2U, 0, 0, 0x401F83DCU +#define IOMUXC_GPIO_SD_B1_06_SAI1_RX_DATA00 0x401F81ECU, 0x3U, 0x401F8594U, 0x0U, 0x401F83DCU +#define IOMUXC_GPIO_SD_B1_06_LPSPI2_PCS0 0x401F81ECU, 0x4U, 0x401F84FCU, 0x0U, 0x401F83DCU +#define IOMUXC_GPIO_SD_B1_06_GPIO3_IO06 0x401F81ECU, 0x5U, 0, 0, 0x401F83DCU + +#define IOMUXC_GPIO_SD_B1_07_SEMC_CSX01 0x401F81F0U, 0x0U, 0, 0, 0x401F83E0U +#define IOMUXC_GPIO_SD_B1_07_FLEXSPIA_SCLK 0x401F81F0U, 0x1U, 0x401F84C8U, 0x0U, 0x401F83E0U +#define IOMUXC_GPIO_SD_B1_07_LPUART7_RTS_B 0x401F81F0U, 0x2U, 0, 0, 0x401F83E0U +#define IOMUXC_GPIO_SD_B1_07_SAI1_TX_DATA00 0x401F81F0U, 0x3U, 0, 0, 0x401F83E0U +#define IOMUXC_GPIO_SD_B1_07_LPSPI2_SCK 0x401F81F0U, 0x4U, 0x401F8500U, 0x0U, 0x401F83E0U +#define IOMUXC_GPIO_SD_B1_07_GPIO3_IO07 0x401F81F0U, 0x5U, 0, 0, 0x401F83E0U + +#define IOMUXC_GPIO_SD_B1_08_USDHC2_DATA4 0x401F81F4U, 0x0U, 0x401F85F8U, 0x0U, 0x401F83E4U +#define IOMUXC_GPIO_SD_B1_08_FLEXSPIA_DATA00 0x401F81F4U, 0x1U, 0x401F84A8U, 0x0U, 0x401F83E4U +#define IOMUXC_GPIO_SD_B1_08_LPUART7_TX 0x401F81F4U, 0x2U, 0x401F855CU, 0x0U, 0x401F83E4U +#define IOMUXC_GPIO_SD_B1_08_SAI1_TX_BCLK 0x401F81F4U, 0x3U, 0x401F85A8U, 0x0U, 0x401F83E4U +#define IOMUXC_GPIO_SD_B1_08_LPSPI2_SD0 0x401F81F4U, 0x4U, 0x401F8508U, 0x0U, 0x401F83E4U +#define IOMUXC_GPIO_SD_B1_08_GPIO3_IO08 0x401F81F4U, 0x5U, 0, 0, 0x401F83E4U +#define IOMUXC_GPIO_SD_B1_08_SEMC_CSX02 0x401F81F4U, 0x6U, 0, 0, 0x401F83E4U + +#define IOMUXC_GPIO_SD_B1_09_USDHC2_DATA5 0x401F81F8U, 0x0U, 0x401F85FCU, 0x0U, 0x401F83E8U +#define IOMUXC_GPIO_SD_B1_09_FLEXSPIA_DATA01 0x401F81F8U, 0x1U, 0x401F84ACU, 0x0U, 0x401F83E8U +#define IOMUXC_GPIO_SD_B1_09_LPUART7_RX 0x401F81F8U, 0x2U, 0x401F8558U, 0x0U, 0x401F83E8U +#define IOMUXC_GPIO_SD_B1_09_SAI1_TX_SYNC 0x401F81F8U, 0x3U, 0x401F85ACU, 0x0U, 0x401F83E8U +#define IOMUXC_GPIO_SD_B1_09_LPSPI2_SDI 0x401F81F8U, 0x4U, 0x401F8504U, 0x0U, 0x401F83E8U +#define IOMUXC_GPIO_SD_B1_09_GPIO3_IO09 0x401F81F8U, 0x5U, 0, 0, 0x401F83E8U + +#define IOMUXC_GPIO_SD_B1_10_USDHC2_DATA6 0x401F81FCU, 0x0U, 0x401F8600U, 0x0U, 0x401F83ECU +#define IOMUXC_GPIO_SD_B1_10_FLEXSPIA_DATA02 0x401F81FCU, 0x1U, 0x401F84B0U, 0x0U, 0x401F83ECU +#define IOMUXC_GPIO_SD_B1_10_LPUART2_RX 0x401F81FCU, 0x2U, 0x401F852CU, 0x0U, 0x401F83ECU +#define IOMUXC_GPIO_SD_B1_10_LPI2C2_SDA 0x401F81FCU, 0x3U, 0x401F84D8U, 0x0U, 0x401F83ECU +#define IOMUXC_GPIO_SD_B1_10_LPSPI2_PCS2 0x401F81FCU, 0x4U, 0, 0, 0x401F83ECU +#define IOMUXC_GPIO_SD_B1_10_GPIO3_IO10 0x401F81FCU, 0x5U, 0, 0, 0x401F83ECU + +#define IOMUXC_GPIO_SD_B1_11_USDHC2_DATA7 0x401F8200U, 0x0U, 0x401F8604U, 0x0U, 0x401F83F0U +#define IOMUXC_GPIO_SD_B1_11_FLEXSPIA_DATA03 0x401F8200U, 0x1U, 0x401F84B4U, 0x0U, 0x401F83F0U +#define IOMUXC_GPIO_SD_B1_11_LPUART2_TX 0x401F8200U, 0x2U, 0x401F8530U, 0x0U, 0x401F83F0U +#define IOMUXC_GPIO_SD_B1_11_LPI2C2_SCL 0x401F8200U, 0x3U, 0x401F84D4U, 0x0U, 0x401F83F0U +#define IOMUXC_GPIO_SD_B1_11_LPSPI2_PCS3 0x401F8200U, 0x4U, 0, 0, 0x401F83F0U +#define IOMUXC_GPIO_SD_B1_11_GPIO3_IO11 0x401F8200U, 0x5U, 0, 0, 0x401F83F0U + +#define IOMUXC_GPR_SAIMCLK_LOWBITMASK (0x7U) +#define IOMUXC_GPR_SAIMCLK_HIGHBITMASK (0x3U) + +typedef enum _iomuxc_gpr_mode +{ + kIOMUXC_GPR_GlobalInterruptRequest = IOMUXC_GPR_GPR1_GINT_MASK, + kIOMUXC_GPR_ENET1RefClkMode = IOMUXC_GPR_GPR1_ENET1_CLK_SEL_MASK, + kIOMUXC_GPR_USBExposureMode = IOMUXC_GPR_GPR1_USB_EXP_MODE_MASK, + kIOMUXC_GPR_ENET1TxClkOutputDir = IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK, + kIOMUXC_GPR_SAI1MClkOutputDir = IOMUXC_GPR_GPR1_SAI1_MCLK_DIR_MASK, + kIOMUXC_GPR_SAI2MClkOutputDir = IOMUXC_GPR_GPR1_SAI2_MCLK_DIR_MASK, + kIOMUXC_GPR_SAI3MClkOutputDir = IOMUXC_GPR_GPR1_SAI3_MCLK_DIR_MASK, + kIOMUXC_GPR_ExcMonitorSlavErrResponse = IOMUXC_GPR_GPR1_EXC_MON_MASK, + kIOMUXC_GPR_ENETIpgClkOn = IOMUXC_GPR_GPR1_ENET_IPG_CLK_S_EN_MASK, + kIOMUXC_GPR_AHBClockEnable = IOMUXC_GPR_GPR1_CM7_FORCE_HCLK_EN_MASK, +} iomuxc_gpr_mode_t; + +typedef enum _iomuxc_gpr_saimclk +{ + kIOMUXC_GPR_SAI1MClk1Sel = IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL_SHIFT, + kIOMUXC_GPR_SAI1MClk2Sel = IOMUXC_GPR_GPR1_SAI1_MCLK2_SEL_SHIFT, + kIOMUXC_GPR_SAI1MClk3Sel = IOMUXC_GPR_GPR1_SAI1_MCLK3_SEL_SHIFT, + kIOMUXC_GPR_SAI2MClk3Sel = IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL_SHIFT, + kIOMUXC_GPR_SAI3MClk3Sel = IOMUXC_GPR_GPR1_SAI3_MCLK3_SEL_SHIFT, +} iomuxc_gpr_saimclk_t; + +typedef enum _iomuxc_mqs_pwm_oversample_rate +{ + kIOMUXC_MqsPwmOverSampleRate32 = 0, /* MQS PWM over sampling rate 32. */ + kIOMUXC_MqsPwmOverSampleRate64 = 1 /* MQS PWM over sampling rate 64. */ +} iomuxc_mqs_pwm_oversample_rate_t; + +/*@}*/ + +#if defined(__cplusplus) +extern "C" { +#endif /*_cplusplus */ + +/*! @name Configuration */ +/*@{*/ + +/*! + * @brief Sets the IOMUXC pin mux mode. + * @note The first five parameters can be filled with the pin function ID macros. + * + * This is an example to set the PTA6 as the lpuart0_tx: + * @code + * IOMUXC_SetPinMux(IOMUXC_PTA6_LPUART0_TX, 0); + * @endcode + * + * This is an example to set the PTA0 as GPIOA0: + * @code + * IOMUXC_SetPinMux(IOMUXC_PTA0_GPIOA0, 0); + * @endcode + * + * @param muxRegister The pin mux register. + * @param muxMode The pin mux mode. + * @param inputRegister The select input register. + * @param inputDaisy The input daisy. + * @param configRegister The config register. + * @param inputOnfield Software input on field. + */ +static inline void IOMUXC_SetPinMux(uint32_t muxRegister, + uint32_t muxMode, + uint32_t inputRegister, + uint32_t inputDaisy, + uint32_t configRegister, + uint32_t inputOnfield) +{ + *((volatile uint32_t *)muxRegister) = + IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(muxMode) | IOMUXC_SW_MUX_CTL_PAD_SION(inputOnfield); + + if (inputRegister) + { + *((volatile uint32_t *)inputRegister) = inputDaisy; + } +} + +/*! + * @brief Sets the IOMUXC pin configuration. + * @note The previous five parameters can be filled with the pin function ID macros. + * + * This is an example to set pin configuration for IOMUXC_PTA3_LPI2C0_SCLS: + * @code + * IOMUXC_SetPinConfig(IOMUXC_PTA3_LPI2C0_SCLS,IOMUXC_SW_PAD_CTL_PAD_PUS_MASK|IOMUXC_SW_PAD_CTL_PAD_PUS(2U)) + * @endcode + * + * @param muxRegister The pin mux register. + * @param muxMode The pin mux mode. + * @param inputRegister The select input register. + * @param inputDaisy The input daisy. + * @param configRegister The config register. + * @param configValue The pin config value. + */ +static inline void IOMUXC_SetPinConfig(uint32_t muxRegister, + uint32_t muxMode, + uint32_t inputRegister, + uint32_t inputDaisy, + uint32_t configRegister, + uint32_t configValue) +{ + if (configRegister) + { + *((volatile uint32_t *)configRegister) = configValue; + } +} + +/*! + * @brief Sets IOMUXC general configuration for some mode. + * + * @param base The IOMUXC GPR base address. + * @param mode The mode for setting. the mode is the logical OR of "iomuxc_gpr_mode" + * @param enable True enable false disable. + */ +static inline void IOMUXC_EnableMode(IOMUXC_GPR_Type *base, uint32_t mode, bool enable) +{ + mode &= ~(IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL_MASK + | IOMUXC_GPR_GPR1_SAI1_MCLK2_SEL_MASK + | IOMUXC_GPR_GPR1_SAI1_MCLK3_SEL_MASK + | IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL_MASK + | IOMUXC_GPR_GPR1_SAI3_MCLK3_SEL_MASK); + + if (enable) + { + base->GPR1 |= mode; + } + else + { + base->GPR1 &= ~mode; + } +} + +/*! + * @brief Sets IOMUXC general configuration for SAI MCLK selection. + * + * @param base The IOMUXC GPR base address. + * @param mclk The SAI MCLK. + * @param clkSrc The clock source. Take refer to register setting details for the clock source in RM. + */ +static inline void IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR_Type *base, iomuxc_gpr_saimclk_t mclk, uint8_t clkSrc) +{ + uint32_t gpr; + + if (mclk > kIOMUXC_GPR_SAI1MClk2Sel) + { + gpr = base->GPR1 & ~(IOMUXC_GPR_SAIMCLK_HIGHBITMASK << mclk); + base->GPR1 = ((clkSrc & IOMUXC_GPR_SAIMCLK_HIGHBITMASK) << mclk) | gpr; + } + else + { + gpr = base->GPR1 & ~(IOMUXC_GPR_SAIMCLK_LOWBITMASK << mclk); + base->GPR1 = ((clkSrc & IOMUXC_GPR_SAIMCLK_LOWBITMASK) << mclk) | gpr; + } +} + +/*! + * @brief Enters or exit MQS software reset. + * + * @param base The IOMUXC GPR base address. + * @param enable Enter or exit MQS software reset. + */ +static inline void IOMUXC_MQSEnterSoftwareReset(IOMUXC_GPR_Type *base, bool enable) +{ + if (enable) + { + base->GPR2 |= IOMUXC_GPR_GPR2_MQS_SW_RST_MASK; + } + else + { + base->GPR2 &= ~IOMUXC_GPR_GPR2_MQS_SW_RST_MASK; + } +} + + +/*! + * @brief Enables or disables MQS. + * + * @param base The IOMUXC GPR base address. + * @param enable Enable or disable the MQS. + */ +static inline void IOMUXC_MQSEnable(IOMUXC_GPR_Type *base, bool enable) +{ + if (enable) + { + base->GPR2 |= IOMUXC_GPR_GPR2_MQS_EN_MASK; + } + else + { + base->GPR2 &= ~IOMUXC_GPR_GPR2_MQS_EN_MASK; + } +} + +/*! + * @brief Configure MQS PWM oversampling rate compared with mclk and divider ratio control for mclk from hmclk. + * + * @param base The IOMUXC GPR base address. + * @param rate The MQS PWM oversampling rate, refer to "iomuxc_mqs_pwm_oversample_rate_t". + * @param divider The divider ratio control for mclk from hmclk. mclk freq = 1 /(divider + 1) * hmclk freq. + */ + +static inline void IOMUXC_MQSConfig(IOMUXC_GPR_Type *base, iomuxc_mqs_pwm_oversample_rate_t rate, uint8_t divider) +{ + uint32_t gpr = base->GPR2 & ~(IOMUXC_GPR_GPR2_MQS_OVERSAMPLE_MASK | IOMUXC_GPR_GPR2_MQS_CLK_DIV_MASK); + + base->GPR2 = gpr | IOMUXC_GPR_GPR2_MQS_OVERSAMPLE(rate) | IOMUXC_GPR_GPR2_MQS_CLK_DIV(divider); +} + +/*@}*/ + +#if defined(__cplusplus) +} +#endif /*_cplusplus */ + +/*! @}*/ + +#endif /* _FSL_IOMUXC_H_ */ + diff --git a/ext/hal/nxp/mcux/devices/MIMXRT1051/system_MIMXRT1051.c b/ext/hal/nxp/mcux/devices/MIMXRT1051/system_MIMXRT1051.c index 8f1de0f8f7d..8fb43e0566e 100644 --- a/ext/hal/nxp/mcux/devices/MIMXRT1051/system_MIMXRT1051.c +++ b/ext/hal/nxp/mcux/devices/MIMXRT1051/system_MIMXRT1051.c @@ -1,17 +1,18 @@ /* ** ################################################################### -** Processors: MIMXRT1051CVL5A -** MIMXRT1051DVL6A +** Processors: MIMXRT1051CVJ5B +** MIMXRT1051CVL5B +** MIMXRT1051DVL6B ** -** Compilers: Keil ARM C/C++ Compiler -** Freescale C/C++ for Embedded ARM +** Compilers: Freescale C/C++ for Embedded ARM ** GNU C Compiler ** IAR ANSI C/C++ Compiler for ARM +** Keil ARM C/C++ Compiler ** MCUXpresso Compiler ** -** Reference manual: IMXRT1050RM Rev.C, 08/2017 -** Version: rev. 0.1, 2017-01-10 -** Build: b170927 +** Reference manual: IMXRT1050RM Rev.2.1, 12/2018 +** Version: rev. 1.2, 2018-11-27 +** Build: b181205 ** ** Abstract: ** Provides a system configuration function and a global variable that @@ -19,31 +20,10 @@ ** the oscillator (PLL) that is part of the microcontroller device. ** ** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2017 NXP -** Redistribution and use in source and binary forms, with or without modification, -** are permitted provided that the following conditions are met: +** Copyright 2016-2018 NXP +** All rights reserved. ** -** 1. Redistributions of source code must retain the above copyright notice, this list -** of conditions and the following disclaimer. -** -** 2. Redistributions in binary form must reproduce the above copyright notice, this -** list of conditions and the following disclaimer in the documentation and/or -** other materials provided with the distribution. -** -** 3. Neither the name of the copyright holder nor the names of its -** contributors may be used to endorse or promote products derived from this -** software without specific prior written permission. -** -** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** SPDX-License-Identifier: BSD-3-Clause ** ** http: www.nxp.com ** mail: support@nxp.com @@ -51,14 +31,22 @@ ** Revisions: ** - rev. 0.1 (2017-01-10) ** Initial version. +** - rev. 1.0 (2018-09-21) +** Update interrupt vector table and dma request source. +** Update register BEE_ADDR_OFFSET1's bitfield name to ADDR_OFFSET1. +** Split GPIO_COMBINED_IRQS to GPIO_COMBINED_LOW_IRQS and GPIO_COMBINED_HIGH_IRQS. +** - rev. 1.1 (2018-11-16) +** Update header files to align with IMXRT1050RM Rev.1. +** - rev. 1.2 (2018-11-27) +** Update header files to align with IMXRT1050RM Rev.2.1. ** ** ################################################################### */ /*! * @file MIMXRT1051 - * @version 0.1 - * @date 2017-01-10 + * @version 1.2 + * @date 2018-11-27 * @brief Device specific configuration file for MIMXRT1051 (implementation file) * * Provides a system configuration function and a global variable that contains @@ -86,6 +74,15 @@ void SystemInit (void) { SCB->CPACR |= ((3UL << 10*2) | (3UL << 11*2)); /* set CP10, CP11 Full Access */ #endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */ +#if defined(__MCUXPRESSO) + extern uint32_t g_pfnVectors[]; // Vector table defined in startup code + SCB->VTOR = (uint32_t)g_pfnVectors; +#endif + +/* Disable Watchdog Power Down Counter */ +WDOG1->WMCR &= ~WDOG_WMCR_PDE_MASK; +WDOG2->WMCR &= ~WDOG_WMCR_PDE_MASK; + /* Watchdog disable */ #if (DISABLE_WDOG) @@ -110,12 +107,17 @@ void SystemInit (void) { /* Enable instruction and data caches */ #if defined(__ICACHE_PRESENT) && __ICACHE_PRESENT - SCB_EnableICache(); + if (SCB_CCR_IC_Msk != (SCB_CCR_IC_Msk & SCB->CCR)) { + SCB_EnableICache(); + } #endif #if defined(__DCACHE_PRESENT) && __DCACHE_PRESENT - SCB_EnableDCache(); + if (SCB_CCR_DC_Msk != (SCB_CCR_DC_Msk & SCB->CCR)) { + SCB_EnableDCache(); + } #endif + SystemInitHook(); } /* ---------------------------------------------------------------------------- @@ -135,15 +137,26 @@ void SystemCoreClockUpdate (void) { { /* Pll3_sw_clk ---> Periph_clk2_clk ---> Periph_clk */ case CCM_CBCMR_PERIPH_CLK2_SEL(0U): - freq = (24000000UL * ((CCM_ANALOG->PLL_USB1 & CCM_ANALOG_PLL_USB1_DIV_SELECT_MASK) ? 22U : 20U)); + if(CCM_ANALOG->PLL_USB1 & CCM_ANALOG_PLL_USB1_BYPASS_MASK) + { + freq = (((CCM_ANALOG->PLL_USB1 & CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_MASK) >> CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_SHIFT) == 0U) ? + CPU_XTAL_CLK_HZ : CPU_CLK1_HZ; + } + else + { + freq = (CPU_XTAL_CLK_HZ * ((CCM_ANALOG->PLL_USB1 & CCM_ANALOG_PLL_USB1_DIV_SELECT_MASK) ? 22U : 20U)); + } break; /* Osc_clk ---> Periph_clk2_clk ---> Periph_clk */ case CCM_CBCMR_PERIPH_CLK2_SEL(1U): - freq = 24000000UL; + freq = CPU_XTAL_CLK_HZ; break; case CCM_CBCMR_PERIPH_CLK2_SEL(2U): + freq = (((CCM_ANALOG->PLL_SYS & CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_MASK) >> CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_SHIFT) == 0U) ? + CPU_XTAL_CLK_HZ : CPU_CLK1_HZ; + case CCM_CBCMR_PERIPH_CLK2_SEL(3U): default: freq = 0U; @@ -155,11 +168,29 @@ void SystemCoreClockUpdate (void) { /* Pre_Periph_clk ---> Periph_clk */ else { - PLL1MainClock = ((24000000UL * ((CCM_ANALOG->PLL_ARM & CCM_ANALOG_PLL_ARM_DIV_SELECT_MASK) >> - CCM_ANALOG_PLL_ARM_DIV_SELECT_SHIFT)) >> 1U); + /* check if pll is bypassed */ + if(CCM_ANALOG->PLL_ARM & CCM_ANALOG_PLL_ARM_BYPASS_MASK) + { + PLL1MainClock = (((CCM_ANALOG->PLL_ARM & CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_MASK) >> CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_SHIFT) == 0U) ? + CPU_XTAL_CLK_HZ : CPU_CLK1_HZ; + } + else + { + PLL1MainClock = ((CPU_XTAL_CLK_HZ * ((CCM_ANALOG->PLL_ARM & CCM_ANALOG_PLL_ARM_DIV_SELECT_MASK) >> + CCM_ANALOG_PLL_ARM_DIV_SELECT_SHIFT)) >> 1U); + } - PLL2MainClock = (24000000UL * ((CCM_ANALOG->PLL_SYS & CCM_ANALOG_PLL_SYS_DIV_SELECT_MASK) ? 22U : 20U)); - PLL2MainClock += ((uint64_t)24000000UL * ((uint64_t)(CCM_ANALOG->PLL_SYS_NUM))) / ((uint64_t)(CCM_ANALOG->PLL_SYS_DENOM)); + /* check if pll is bypassed */ + if(CCM_ANALOG->PLL_SYS & CCM_ANALOG_PLL_SYS_BYPASS_MASK) + { + PLL2MainClock = (((CCM_ANALOG->PLL_SYS & CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_MASK) >> CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_SHIFT) == 0U) ? + CPU_XTAL_CLK_HZ : CPU_CLK1_HZ; + } + else + { + PLL2MainClock = (CPU_XTAL_CLK_HZ * ((CCM_ANALOG->PLL_SYS & CCM_ANALOG_PLL_SYS_DIV_SELECT_MASK) ? 22U : 20U)); + } + PLL2MainClock += ((uint64_t)CPU_XTAL_CLK_HZ * ((uint64_t)(CCM_ANALOG->PLL_SYS_NUM))) / ((uint64_t)(CCM_ANALOG->PLL_SYS_DENOM)); switch (CCM->CBCMR & CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK) @@ -193,3 +224,11 @@ void SystemCoreClockUpdate (void) { SystemCoreClock = (freq / (((CCM->CBCDR & CCM_CBCDR_AHB_PODF_MASK) >> CCM_CBCDR_AHB_PODF_SHIFT) + 1U)); } + +/* ---------------------------------------------------------------------------- + -- SystemInitHook() + ---------------------------------------------------------------------------- */ + +__attribute__ ((weak)) void SystemInitHook (void) { + /* Void implementation of the weak function. */ +} diff --git a/ext/hal/nxp/mcux/devices/MIMXRT1051/system_MIMXRT1051.h b/ext/hal/nxp/mcux/devices/MIMXRT1051/system_MIMXRT1051.h index 8c2ab733bed..24e5a888c5b 100644 --- a/ext/hal/nxp/mcux/devices/MIMXRT1051/system_MIMXRT1051.h +++ b/ext/hal/nxp/mcux/devices/MIMXRT1051/system_MIMXRT1051.h @@ -1,17 +1,18 @@ /* ** ################################################################### -** Processors: MIMXRT1051CVL5A -** MIMXRT1051DVL6A +** Processors: MIMXRT1051CVJ5B +** MIMXRT1051CVL5B +** MIMXRT1051DVL6B ** -** Compilers: Keil ARM C/C++ Compiler -** Freescale C/C++ for Embedded ARM +** Compilers: Freescale C/C++ for Embedded ARM ** GNU C Compiler ** IAR ANSI C/C++ Compiler for ARM +** Keil ARM C/C++ Compiler ** MCUXpresso Compiler ** -** Reference manual: IMXRT1050RM Rev.C, 08/2017 -** Version: rev. 0.1, 2017-01-10 -** Build: b170927 +** Reference manual: IMXRT1050RM Rev.2.1, 12/2018 +** Version: rev. 1.2, 2018-11-27 +** Build: b181205 ** ** Abstract: ** Provides a system configuration function and a global variable that @@ -19,31 +20,10 @@ ** the oscillator (PLL) that is part of the microcontroller device. ** ** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2017 NXP -** Redistribution and use in source and binary forms, with or without modification, -** are permitted provided that the following conditions are met: +** Copyright 2016-2018 NXP +** All rights reserved. ** -** 1. Redistributions of source code must retain the above copyright notice, this list -** of conditions and the following disclaimer. -** -** 2. Redistributions in binary form must reproduce the above copyright notice, this -** list of conditions and the following disclaimer in the documentation and/or -** other materials provided with the distribution. -** -** 3. Neither the name of the copyright holder nor the names of its -** contributors may be used to endorse or promote products derived from this -** software without specific prior written permission. -** -** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** SPDX-License-Identifier: BSD-3-Clause ** ** http: www.nxp.com ** mail: support@nxp.com @@ -51,14 +31,22 @@ ** Revisions: ** - rev. 0.1 (2017-01-10) ** Initial version. +** - rev. 1.0 (2018-09-21) +** Update interrupt vector table and dma request source. +** Update register BEE_ADDR_OFFSET1's bitfield name to ADDR_OFFSET1. +** Split GPIO_COMBINED_IRQS to GPIO_COMBINED_LOW_IRQS and GPIO_COMBINED_HIGH_IRQS. +** - rev. 1.1 (2018-11-16) +** Update header files to align with IMXRT1050RM Rev.1. +** - rev. 1.2 (2018-11-27) +** Update header files to align with IMXRT1050RM Rev.2.1. ** ** ################################################################### */ /*! * @file MIMXRT1051 - * @version 0.1 - * @date 2017-01-10 + * @version 1.2 + * @date 2018-11-27 * @brief Device specific configuration file for MIMXRT1051 (header file) * * Provides a system configuration function and a global variable that contains @@ -84,6 +72,9 @@ extern "C" { #define CPU_XTAL_CLK_HZ 24000000UL /* Value of the external crystal or oscillator clock frequency in Hz */ +#define CPU_CLK1_HZ 0UL /* Value of the CLK1 (select the CLK1_N/CLK1_P as source) frequency in Hz */ + /* If CLOCK1_P,CLOCK1_N is choose as the pll bypass clock source, please implement the CLKPN_FREQ define, otherwise 0 will be returned. */ + #define DEFAULT_SYSTEM_CLOCK 528000000UL /* Default System clock value */ @@ -116,6 +107,18 @@ void SystemInit (void); */ void SystemCoreClockUpdate (void); +/** + * @brief SystemInit function hook. + * + * This weak function allows to call specific initialization code during the + * SystemInit() execution.This can be used when an application specific code needs + * to be called as close to the reset entry as possible (for example the Multicore + * Manager MCMGR_EarlyInit() function call). + * NOTE: No global r/w variables can be used in this hook function because the + * initialization of these variables happens after this function. + */ +void SystemInitHook (void); + #ifdef __cplusplus } #endif diff --git a/ext/hal/nxp/mcux/devices/MIMXRT1052/MIMXRT1052.h b/ext/hal/nxp/mcux/devices/MIMXRT1052/MIMXRT1052.h index 1051560b70d..552c36a163c 100644 --- a/ext/hal/nxp/mcux/devices/MIMXRT1052/MIMXRT1052.h +++ b/ext/hal/nxp/mcux/devices/MIMXRT1052/MIMXRT1052.h @@ -1,47 +1,28 @@ /* ** ################################################################### -** Processors: MIMXRT1052CVL5A -** MIMXRT1052DVL6A +** Processors: MIMXRT1052CVJ5B +** MIMXRT1052CVL5B +** MIMXRT1052DVJ6B +** MIMXRT1052DVL6B ** -** Compilers: Keil ARM C/C++ Compiler -** Freescale C/C++ for Embedded ARM +** Compilers: Freescale C/C++ for Embedded ARM ** GNU C Compiler ** IAR ANSI C/C++ Compiler for ARM +** Keil ARM C/C++ Compiler ** MCUXpresso Compiler ** -** Reference manual: IMXRT1050RM Rev.C, 08/2017 -** Version: rev. 0.1, 2017-01-10 -** Build: b171011 +** Reference manual: IMXRT1050RM Rev.2.1, 12/2018 +** Version: rev. 1.2, 2018-11-27 +** Build: b181205 ** ** Abstract: ** CMSIS Peripheral Access Layer for MIMXRT1052 ** ** Copyright 1997-2016 Freescale Semiconductor, Inc. -** Copyright 2016-2017 NXP -** Redistribution and use in source and binary forms, with or without modification, -** are permitted provided that the following conditions are met: +** Copyright 2016-2018 NXP +** All rights reserved. ** -** 1. Redistributions of source code must retain the above copyright notice, this list -** of conditions and the following disclaimer. -** -** 2. Redistributions in binary form must reproduce the above copyright notice, this -** list of conditions and the following disclaimer in the documentation and/or -** other materials provided with the distribution. -** -** 3. Neither the name of the copyright holder nor the names of its -** contributors may be used to endorse or promote products derived from this -** software without specific prior written permission. -** -** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** SPDX-License-Identifier: BSD-3-Clause ** ** http: www.nxp.com ** mail: support@nxp.com @@ -49,14 +30,22 @@ ** Revisions: ** - rev. 0.1 (2017-01-10) ** Initial version. +** - rev. 1.0 (2018-09-21) +** Update interrupt vector table and dma request source. +** Update register BEE_ADDR_OFFSET1's bitfield name to ADDR_OFFSET1. +** Split GPIO_COMBINED_IRQS to GPIO_COMBINED_LOW_IRQS and GPIO_COMBINED_HIGH_IRQS. +** - rev. 1.1 (2018-11-16) +** Update header files to align with IMXRT1050RM Rev.1. +** - rev. 1.2 (2018-11-27) +** Update header files to align with IMXRT1050RM Rev.2.1. ** ** ################################################################### */ /*! * @file MIMXRT1052.h - * @version 0.1 - * @date 2017-01-10 + * @version 1.2 + * @date 2018-11-27 * @brief CMSIS Peripheral Access Layer for MIMXRT1052 * * CMSIS Peripheral Access Layer for MIMXRT1052 @@ -67,9 +56,9 @@ /** Memory map major version (memory maps with equal major version number are * compatible) */ -#define MCU_MEM_MAP_VERSION 0x0000U +#define MCU_MEM_MAP_VERSION 0x0100U /** Memory map minor version */ -#define MCU_MEM_MAP_VERSION_MINOR 0x0001U +#define MCU_MEM_MAP_VERSION_MINOR 0x0002U /* ---------------------------------------------------------------------------- @@ -82,7 +71,7 @@ */ /** Interrupt Number Definitions */ -#define NUMBER_OF_INT_VECTORS 176 /**< Number of interrupts in the Vector table */ +#define NUMBER_OF_INT_VECTORS 168 /**< Number of interrupts in the Vector table */ typedef enum IRQn { /* Auxiliary constants */ @@ -161,10 +150,10 @@ typedef enum IRQn { SAI3_RX_IRQn = 58, /**< SAI3 interrupt */ SAI3_TX_IRQn = 59, /**< SAI3 interrupt */ SPDIF_IRQn = 60, /**< SPDIF interrupt */ - ANATOP_EVENT0_IRQn = 61, /**< ANATOP interrupt */ - ANATOP_EVENT1_IRQn = 62, /**< ANATOP interrupt */ - ANATOP_TAMP_LOW_HIGH_IRQn = 63, /**< ANATOP interrupt */ - ANATOP_TEMP_PANIC_IRQn = 64, /**< ANATOP interrupt */ + PMU_EVENT_IRQn = 61, /**< Brown-out event interrupt */ + Reserved78_IRQn = 62, /**< Reserved interrupt */ + TEMP_LOW_HIGH_IRQn = 63, /**< TempSensor low/high interrupt */ + TEMP_PANIC_IRQn = 64, /**< TempSensor panic interrupt */ USB_PHY1_IRQn = 65, /**< USBPHY (UTMI0), Interrupt */ USB_PHY2_IRQn = 66, /**< USBPHY (UTMI0), Interrupt */ ADC1_IRQn = 67, /**< ADC1 interrupt */ @@ -251,15 +240,7 @@ typedef enum IRQn { PWM4_1_IRQn = 148, /**< PWM4 capture 1, compare 1, or reload 0 interrupt */ PWM4_2_IRQn = 149, /**< PWM4 capture 2, compare 2, or reload 0 interrupt */ PWM4_3_IRQn = 150, /**< PWM4 capture 3, compare 3, or reload 0 interrupt */ - PWM4_FAULT_IRQn = 151, /**< PWM4 fault or reload error interrupt */ - Reserved168_IRQn = 152, /**< Reserved interrupt */ - Reserved169_IRQn = 153, /**< Reserved interrupt */ - Reserved170_IRQn = 154, /**< Reserved interrupt */ - Reserved171_IRQn = 155, /**< Reserved interrupt */ - Reserved172_IRQn = 156, /**< Reserved interrupt */ - Reserved173_IRQn = 157, /**< Reserved interrupt */ - SJC_ARM_DEBUG_IRQn = 158, /**< SJC ARM debug interrupt */ - NMI_WAKEUP_IRQn = 159 /**< NMI wake up */ + PWM4_FAULT_IRQn = 151 /**< PWM4 fault or reload error interrupt */ } IRQn_Type; /*! @@ -304,21 +285,24 @@ typedef enum IRQn { /** Mapping Information */ /*! * @addtogroup edma_request - * @{ */ + * @{ + */ /******************************************************************************* * Definitions -*******************************************************************************/ + ******************************************************************************/ /*! - * @brief Enumeration for the DMA0 hardware request + * @brief Structure for the DMA hardware request * - * Defines the enumeration for the DMA0 hardware request collections. + * Defines the structure for the DMA hardware request collections. The user can configure the + * hardware request into DMAMUX to trigger the DMA transfer accordingly. The index + * of the hardware request varies according to the to SoC. */ typedef enum _dma_request_source { - kDmaRequestMuxFlexIO1Request0Request1 = 0|0x100U, /**< FlexIO1 */ - kDmaRequestMuxFlexIO2Request0Request1 = 1|0x100U, /**< FlexIO2 */ + kDmaRequestMuxFlexIO1Request0Request1 = 0|0x100U, /**< FlexIO1 Request0 and Request1 */ + kDmaRequestMuxFlexIO2Request0Request1 = 1|0x100U, /**< FlexIO2 Request0 and Request1 */ kDmaRequestMuxLPUART1Tx = 2|0x100U, /**< LPUART1 Transmit */ kDmaRequestMuxLPUART1Rx = 3|0x100U, /**< LPUART1 Receive */ kDmaRequestMuxLPUART3Tx = 4|0x100U, /**< LPUART3 Transmit */ @@ -334,14 +318,14 @@ typedef enum _dma_request_source kDmaRequestMuxLPSPI3Tx = 16|0x100U, /**< LPSPI3 Transmit */ kDmaRequestMuxLPI2C1 = 17|0x100U, /**< LPI2C1 */ kDmaRequestMuxLPI2C3 = 18|0x100U, /**< LPI2C3 */ - kDmaRequestMuxSai1Rx = 19|0x100U, /**< Sai1 Receive */ - kDmaRequestMuxSai1Tx = 20|0x100U, /**< Sai1 Transmit */ - kDmaRequestMuxSai2Rx = 21|0x100U, /**< Sai2 Receive */ - kDmaRequestMuxSai2Tx = 22|0x100U, /**< Sai2 Transmit */ + kDmaRequestMuxSai1Rx = 19|0x100U, /**< SAI1 Receive */ + kDmaRequestMuxSai1Tx = 20|0x100U, /**< SAI1 Transmit */ + kDmaRequestMuxSai2Rx = 21|0x100U, /**< SAI2 Receive */ + kDmaRequestMuxSai2Tx = 22|0x100U, /**< SAI2 Transmit */ kDmaRequestMuxADC_ETC = 23|0x100U, /**< ADC_ETC */ kDmaRequestMuxADC1 = 24|0x100U, /**< ADC1 */ kDmaRequestMuxACMP1 = 25|0x100U, /**< ACMP1 */ - kDmaRequestMuxACMP2 = 26|0x100U, /**< ACMP2 */ + kDmaRequestMuxACMP3 = 26|0x100U, /**< ACMP3 */ kDmaRequestMuxFlexSPIRx = 28|0x100U, /**< FlexSPI Receive */ kDmaRequestMuxFlexSPITx = 29|0x100U, /**< FlexSPI Transmit */ kDmaRequestMuxXBAR1Request0 = 30|0x100U, /**< XBAR1 Request 0 */ @@ -362,20 +346,20 @@ typedef enum _dma_request_source kDmaRequestMuxFlexPWM3ValueSub1 = 45|0x100U, /**< FlexPWM3 Value sub-module1 */ kDmaRequestMuxFlexPWM3ValueSub2 = 46|0x100U, /**< FlexPWM3 Value sub-module2 */ kDmaRequestMuxFlexPWM3ValueSub3 = 47|0x100U, /**< FlexPWM3 Value sub-module3 */ - kDmaRequestMuxQTIMER1CaptTimer0 = 48|0x100U, /**< QTIMER1 Capture timer 0 */ - kDmaRequestMuxQTIMER1CaptTimer1 = 49|0x100U, /**< QTIMER1 Capture timer 1 */ - kDmaRequestMuxQTIMER1CaptTimer2 = 50|0x100U, /**< QTIMER1 Capture timer 2 */ - kDmaRequestMuxQTIMER1CaptTimer3 = 51|0x100U, /**< QTIMER1 Capture timer 3 */ - kDmaRequestMuxQTIMER1Cmpld1Timer0Cmpld2Timer1 = 52|0x100U, /**< QTIMER1 cmpld1 in timer 0 or cmpld2 in timer 1 */ - kDmaRequestMuxQTIMER1Cmpld1Timer1Cmpld2Timer0 = 53|0x100U, /**< QTIMER1 cmpld1 in timer 1 or cmpld2 in timer 0 */ - kDmaRequestMuxQTIMER1Cmpld1Timer2Cmpld2Timer3 = 54|0x100U, /**< QTIMER1 cmpld1 in timer 2 or cmpld2 in timer 3 */ - kDmaRequestMuxQTIMER1Cmpld1Timer3Cmpld2Timer2 = 55|0x100U, /**< QTIMER1 cmpld1 in timer 3 or cmpld2 in timer 2 */ - kDmaRequestMuxQTIMER3CaptTimer0Cmpld1Timer0Cmpld2Timer1 = 56|0x100U, /**< QTIMER3 capture timer 0, cmpld1 in timer 0 or cmpld2 in timer 1 */ - kDmaRequestMuxQTIMER3CaptTimer1Cmpld1Timer0Cmpld2Timer1 = 57|0x100U, /**< QTIMER3 capture timer 1, cmpld1 in timer 0 or cmpld2 in timer 1 */ - kDmaRequestMuxQTIMER3CaptTimer2Cmpld1Timer0Cmpld2Timer1 = 58|0x100U, /**< QTIMER3 capture timer 2, cmpld1 in timer 0 or cmpld2 in timer 1 */ - kDmaRequestMuxQTIMER3CaptTimer3Cmpld1Timer0Cmpld2Timer1 = 59|0x100U, /**< QTIMER3 capture timer 3, cmpld1 in timer 0 or cmpld2 in timer 1 */ - kDmaRequestMuxFlexIO1Request2Request3 = 64|0x100U, /**< FlexIO1 */ - kDmaRequestMuxFlexIO2Request2Request3 = 65|0x100U, /**< FlexIO2 */ + kDmaRequestMuxQTIMER1CaptTimer0 = 48|0x100U, /**< TMR1 Capture timer 0 */ + kDmaRequestMuxQTIMER1CaptTimer1 = 49|0x100U, /**< TMR1 Capture timer 1 */ + kDmaRequestMuxQTIMER1CaptTimer2 = 50|0x100U, /**< TMR1 Capture timer 2 */ + kDmaRequestMuxQTIMER1CaptTimer3 = 51|0x100U, /**< TMR1 Capture timer 3 */ + kDmaRequestMuxQTIMER1Cmpld1Timer0Cmpld2Timer1 = 52|0x100U, /**< TMR1 cmpld1 in timer 0 or cmpld2 in timer 1 */ + kDmaRequestMuxQTIMER1Cmpld1Timer1Cmpld2Timer0 = 53|0x100U, /**< TMR1 cmpld1 in timer 1 or cmpld2 in timer 0 */ + kDmaRequestMuxQTIMER1Cmpld1Timer2Cmpld2Timer3 = 54|0x100U, /**< TMR1 cmpld1 in timer 2 or cmpld2 in timer 3 */ + kDmaRequestMuxQTIMER1Cmpld1Timer3Cmpld2Timer2 = 55|0x100U, /**< TMR1 cmpld1 in timer 3 or cmpld2 in timer 2 */ + kDmaRequestMuxQTIMER3CaptTimer0Cmpld1Timer0Cmpld2Timer1 = 56|0x100U, /**< TMR3 capture timer 0, cmpld1 in timer 0 or cmpld2 in timer 1 */ + kDmaRequestMuxQTIMER3CaptTimer1Cmpld1Timer1Cmpld2Timer0 = 57|0x100U, /**< TMR3 capture timer 1, cmpld1 in timer 1 or cmpld2 in timer 0 */ + kDmaRequestMuxQTIMER3CaptTimer2Cmpld1Timer2Cmpld2Timer3 = 58|0x100U, /**< TMR3 capture timer 2, cmpld1 in timer 2 or cmpld2 in timer 3 */ + kDmaRequestMuxQTIMER3CaptTimer3Cmpld1Timer3Cmpld2Timer2 = 59|0x100U, /**< TMR3 capture timer 3, cmpld1 in timer 3 or cmpld2 in timer 2 */ + kDmaRequestMuxFlexIO1Request2Request3 = 64|0x100U, /**< FlexIO1 Request2 and Request3 */ + kDmaRequestMuxFlexIO2Request2Request3 = 65|0x100U, /**< FlexIO2 Request2 and Request3 */ kDmaRequestMuxLPUART2Tx = 66|0x100U, /**< LPUART2 Transmit */ kDmaRequestMuxLPUART2Rx = 67|0x100U, /**< LPUART2 Receive */ kDmaRequestMuxLPUART4Tx = 68|0x100U, /**< LPUART4 Transmit */ @@ -392,15 +376,15 @@ typedef enum _dma_request_source kDmaRequestMuxLPSPI4Tx = 80|0x100U, /**< LPSPI4 Transmit */ kDmaRequestMuxLPI2C2 = 81|0x100U, /**< LPI2C2 */ kDmaRequestMuxLPI2C4 = 82|0x100U, /**< LPI2C4 */ - kDmaRequestMuxSai3Rx = 83|0x100U, /**< Sai3 Receive */ - kDmaRequestMuxSai3Tx = 84|0x100U, /**< Sai3 Transmit */ - kDmaRequestMuxSpdifRx = 85|0x100U, /**< Spdif Receive */ - kDmaRequestMuxSpdifTx = 86|0x100U, /**< Spdif Transmit */ + kDmaRequestMuxSai3Rx = 83|0x100U, /**< SAI3 Receive */ + kDmaRequestMuxSai3Tx = 84|0x100U, /**< SAI3 Transmit */ + kDmaRequestMuxSpdifRx = 85|0x100U, /**< SPDIF Receive */ + kDmaRequestMuxSpdifTx = 86|0x100U, /**< SPDIF Transmit */ kDmaRequestMuxADC2 = 88|0x100U, /**< ADC2 */ - kDmaRequestMuxACMP3 = 89|0x100U, /**< ACMP3 */ + kDmaRequestMuxACMP2 = 89|0x100U, /**< ACMP2 */ kDmaRequestMuxACMP4 = 90|0x100U, /**< ACMP4 */ - kDmaRequestMuxEnetTimer0 = 92|0x100U, /**< Enet Timer0 */ - kDmaRequestMuxEnetTimer1 = 93|0x100U, /**< Enet Timer1 */ + kDmaRequestMuxEnetTimer0 = 92|0x100U, /**< ENET Timer0 */ + kDmaRequestMuxEnetTimer1 = 93|0x100U, /**< ENET Timer1 */ kDmaRequestMuxXBAR1Request2 = 94|0x100U, /**< XBAR1 Request 2 */ kDmaRequestMuxXBAR1Request3 = 95|0x100U, /**< XBAR1 Request 3 */ kDmaRequestMuxFlexPWM2CaptureSub0 = 96|0x100U, /**< FlexPWM2 Capture sub-module0 */ @@ -419,20 +403,22 @@ typedef enum _dma_request_source kDmaRequestMuxFlexPWM4ValueSub1 = 109|0x100U, /**< FlexPWM4 Value sub-module1 */ kDmaRequestMuxFlexPWM4ValueSub2 = 110|0x100U, /**< FlexPWM4 Value sub-module2 */ kDmaRequestMuxFlexPWM4ValueSub3 = 111|0x100U, /**< FlexPWM4 Value sub-module3 */ - kDmaRequestMuxQTIMER2CaptTimer0 = 112|0x100U, /**< QTIMER2 Capture timer 0 */ - kDmaRequestMuxQTIMER2CaptTimer1 = 113|0x100U, /**< QTIMER2 Capture timer 1 */ - kDmaRequestMuxQTIMER2CaptTimer2 = 114|0x100U, /**< QTIMER2 Capture timer 2 */ - kDmaRequestMuxQTIMER2CaptTimer3 = 115|0x100U, /**< QTIMER2 Capture timer 3 */ - kDmaRequestMuxQTIMER2Cmpld1Timer0Cmpld2Timer1 = 116|0x100U, /**< QTIMER2 cmpld1 in timer 0 or cmpld2 in timer 1 */ - kDmaRequestMuxQTIMER2Cmpld1Timer1Cmpld2Timer0 = 117|0x100U, /**< QTIMER2 cmpld1 in timer 1 or cmpld2 in timer 0 */ - kDmaRequestMuxQTIMER2Cmpld1Timer2Cmpld2Timer3 = 118|0x100U, /**< QTIMER2 cmpld1 in timer 2 or cmpld2 in timer 3 */ - kDmaRequestMuxQTIMER2Cmpld1Timer3Cmpld2Timer2 = 119|0x100U, /**< QTIMER2 cmpld1 in timer 3 or cmpld2 in timer 2 */ - kDmaRequestMuxQTIMER4CaptTimer0Cmpld1Timer0Cmpld2Timer1 = 120|0x100U, /**< QTIMER4 capture timer 0, cmpld1 in timer 0 or cmpld2 in timer 1 */ - kDmaRequestMuxQTIMER4CaptTimer1Cmpld1Timer0Cmpld2Timer1 = 121|0x100U, /**< QTIMER4 capture timer 1, cmpld1 in timer 0 or cmpld2 in timer 1 */ - kDmaRequestMuxQTIMER4CaptTimer2Cmpld1Timer0Cmpld2Timer1 = 122|0x100U, /**< QTIMER4 capture timer 2, cmpld1 in timer 0 or cmpld2 in timer 1 */ - kDmaRequestMuxQTIMER4CaptTimer3Cmpld1Timer0Cmpld2Timer1 = 123|0x100U, /**< QTIMER4 capture timer 3, cmpld1 in timer 0 or cmpld2 in timer 1 */ + kDmaRequestMuxQTIMER2CaptTimer0 = 112|0x100U, /**< TMR2 Capture timer 0 */ + kDmaRequestMuxQTIMER2CaptTimer1 = 113|0x100U, /**< TMR2 Capture timer 1 */ + kDmaRequestMuxQTIMER2CaptTimer2 = 114|0x100U, /**< TMR2 Capture timer 2 */ + kDmaRequestMuxQTIMER2CaptTimer3 = 115|0x100U, /**< TMR2 Capture timer 3 */ + kDmaRequestMuxQTIMER2Cmpld1Timer0Cmpld2Timer1 = 116|0x100U, /**< TMR2 cmpld1 in timer 0 or cmpld2 in timer 1 */ + kDmaRequestMuxQTIMER2Cmpld1Timer1Cmpld2Timer0 = 117|0x100U, /**< TMR2 cmpld1 in timer 1 or cmpld2 in timer 0 */ + kDmaRequestMuxQTIMER2Cmpld1Timer2Cmpld2Timer3 = 118|0x100U, /**< TMR2 cmpld1 in timer 2 or cmpld2 in timer 3 */ + kDmaRequestMuxQTIMER2Cmpld1Timer3Cmpld2Timer2 = 119|0x100U, /**< TMR2 cmpld1 in timer 3 or cmpld2 in timer 2 */ + kDmaRequestMuxQTIMER4CaptTimer0Cmpld1Timer0Cmpld2Timer1 = 120|0x100U, /**< TMR4 capture timer 0, cmpld1 in timer 0 or cmpld2 in timer 1 */ + kDmaRequestMuxQTIMER4CaptTimer1Cmpld1Timer1Cmpld2Timer0 = 121|0x100U, /**< TMR4 capture timer 1, cmpld1 in timer 1 or cmpld2 in timer 0 */ + kDmaRequestMuxQTIMER4CaptTimer2Cmpld1Timer2Cmpld2Timer3 = 122|0x100U, /**< TMR4 capture timer 2, cmpld1 in timer 2 or cmpld2 in timer 3 */ + kDmaRequestMuxQTIMER4CaptTimer3Cmpld1Timer3Cmpld2Timer2 = 123|0x100U, /**< TMR4 capture timer 3, cmpld1 in timer 3 or cmpld2 in timer 2 */ } dma_request_source_t; +/* @} */ + /*! * @addtogroup iomuxc_pads * @{ */ @@ -574,6 +560,8 @@ typedef enum _iomuxc_sw_mux_ctl_pad kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_11 = 123U, /**< IOMUXC SW_MUX_CTL_PAD index */ } iomuxc_sw_mux_ctl_pad_t; +/* @} */ + /*! * @addtogroup iomuxc_pads * @{ */ @@ -715,6 +703,8 @@ typedef enum _iomuxc_sw_pad_ctl_pad kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_11 = 123U, /**< IOMUXC SW_PAD_CTL_PAD index */ } iomuxc_sw_pad_ctl_pad_t; +/* @} */ + /*! * @brief Enumeration for the IOMUXC select input * @@ -878,8 +868,6 @@ typedef enum _iomuxc_select_input kIOMUXC_XBAR1_IN21_SELECT_INPUT = 153U, /**< IOMUXC select input index */ } iomuxc_select_input_t; -/* @} */ - typedef enum _xbar_input_signal { kXBARA1_InputLogicLow = 0|0x100U, /**< LOGIC_LOW output assigned to XBARA1_IN0 input. */ @@ -1276,8 +1264,12 @@ typedef enum _xbar_output_signal */ #if defined(__ARMCC_VERSION) - #pragma push - #pragma anon_unions + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #else + #pragma push + #pragma anon_unions + #endif #elif defined(__CWCC__) #pragma push #pragma cpp_extensions on @@ -1321,121 +1313,251 @@ typedef struct { */ /*! @name HC - Control register for hardware triggers */ +/*! @{ */ #define ADC_HC_ADCH_MASK (0x1FU) #define ADC_HC_ADCH_SHIFT (0U) +/*! ADCH - Input Channel Select + * 0b10000..External channel selection from ADC_ETC + * 0b11000..Reserved. + * 0b11001..VREFSH = internal channel, for ADC self-test, hard connected to VRH internally + * 0b11010..Reserved. + * 0b11011..Reserved. + * 0b11111..Conversion Disabled. Hardware Triggers will not initiate any conversion. + */ #define ADC_HC_ADCH(x) (((uint32_t)(((uint32_t)(x)) << ADC_HC_ADCH_SHIFT)) & ADC_HC_ADCH_MASK) #define ADC_HC_AIEN_MASK (0x80U) #define ADC_HC_AIEN_SHIFT (7U) +/*! AIEN - Conversion Complete Interrupt Enable/Disable Control + * 0b1..Conversion complete interrupt enabled + * 0b0..Conversion complete interrupt disabled + */ #define ADC_HC_AIEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_HC_AIEN_SHIFT)) & ADC_HC_AIEN_MASK) +/*! @} */ /* The count of ADC_HC */ #define ADC_HC_COUNT (8U) /*! @name HS - Status register for HW triggers */ +/*! @{ */ #define ADC_HS_COCO0_MASK (0x1U) #define ADC_HS_COCO0_SHIFT (0U) #define ADC_HS_COCO0(x) (((uint32_t)(((uint32_t)(x)) << ADC_HS_COCO0_SHIFT)) & ADC_HS_COCO0_MASK) +/*! @} */ /*! @name R - Data result register for HW triggers */ +/*! @{ */ #define ADC_R_CDATA_MASK (0xFFFU) #define ADC_R_CDATA_SHIFT (0U) #define ADC_R_CDATA(x) (((uint32_t)(((uint32_t)(x)) << ADC_R_CDATA_SHIFT)) & ADC_R_CDATA_MASK) +/*! @} */ /* The count of ADC_R */ #define ADC_R_COUNT (8U) /*! @name CFG - Configuration register */ +/*! @{ */ #define ADC_CFG_ADICLK_MASK (0x3U) #define ADC_CFG_ADICLK_SHIFT (0U) +/*! ADICLK - Input Clock Select + * 0b00..IPG clock + * 0b01..IPG clock divided by 2 + * 0b10..Reserved + * 0b11..Asynchronous clock (ADACK) + */ #define ADC_CFG_ADICLK(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADICLK_SHIFT)) & ADC_CFG_ADICLK_MASK) #define ADC_CFG_MODE_MASK (0xCU) #define ADC_CFG_MODE_SHIFT (2U) +/*! MODE - Conversion Mode Selection + * 0b00..8-bit conversion + * 0b01..10-bit conversion + * 0b10..12-bit conversion + * 0b11..Reserved + */ #define ADC_CFG_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_MODE_SHIFT)) & ADC_CFG_MODE_MASK) #define ADC_CFG_ADLSMP_MASK (0x10U) #define ADC_CFG_ADLSMP_SHIFT (4U) +/*! ADLSMP - Long Sample Time Configuration + * 0b0..Short sample mode. + * 0b1..Long sample mode. + */ #define ADC_CFG_ADLSMP(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADLSMP_SHIFT)) & ADC_CFG_ADLSMP_MASK) #define ADC_CFG_ADIV_MASK (0x60U) #define ADC_CFG_ADIV_SHIFT (5U) +/*! ADIV - Clock Divide Select + * 0b00..Input clock + * 0b01..Input clock / 2 + * 0b10..Input clock / 4 + * 0b11..Input clock / 8 + */ #define ADC_CFG_ADIV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADIV_SHIFT)) & ADC_CFG_ADIV_MASK) #define ADC_CFG_ADLPC_MASK (0x80U) #define ADC_CFG_ADLPC_SHIFT (7U) +/*! ADLPC - Low-Power Configuration + * 0b0..ADC hard block not in low power mode. + * 0b1..ADC hard block in low power mode. + */ #define ADC_CFG_ADLPC(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADLPC_SHIFT)) & ADC_CFG_ADLPC_MASK) #define ADC_CFG_ADSTS_MASK (0x300U) #define ADC_CFG_ADSTS_SHIFT (8U) +/*! ADSTS + * 0b00..Sample period (ADC clocks) = 2 if ADLSMP=0b Sample period (ADC clocks) = 12 if ADLSMP=1b + * 0b01..Sample period (ADC clocks) = 4 if ADLSMP=0b Sample period (ADC clocks) = 16 if ADLSMP=1b + * 0b10..Sample period (ADC clocks) = 6 if ADLSMP=0b Sample period (ADC clocks) = 20 if ADLSMP=1b + * 0b11..Sample period (ADC clocks) = 8 if ADLSMP=0b Sample period (ADC clocks) = 24 if ADLSMP=1b + */ #define ADC_CFG_ADSTS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADSTS_SHIFT)) & ADC_CFG_ADSTS_MASK) #define ADC_CFG_ADHSC_MASK (0x400U) #define ADC_CFG_ADHSC_SHIFT (10U) +/*! ADHSC - High Speed Configuration + * 0b0..Normal conversion selected. + * 0b1..High speed conversion selected. + */ #define ADC_CFG_ADHSC(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADHSC_SHIFT)) & ADC_CFG_ADHSC_MASK) #define ADC_CFG_REFSEL_MASK (0x1800U) #define ADC_CFG_REFSEL_SHIFT (11U) +/*! REFSEL - Voltage Reference Selection + * 0b00..Selects VREFH/VREFL as reference voltage. + * 0b01..Reserved + * 0b10..Reserved + * 0b11..Reserved + */ #define ADC_CFG_REFSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_REFSEL_SHIFT)) & ADC_CFG_REFSEL_MASK) #define ADC_CFG_ADTRG_MASK (0x2000U) #define ADC_CFG_ADTRG_SHIFT (13U) +/*! ADTRG - Conversion Trigger Select + * 0b0..Software trigger selected + * 0b1..Hardware trigger selected + */ #define ADC_CFG_ADTRG(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADTRG_SHIFT)) & ADC_CFG_ADTRG_MASK) #define ADC_CFG_AVGS_MASK (0xC000U) #define ADC_CFG_AVGS_SHIFT (14U) +/*! AVGS - Hardware Average select + * 0b00..4 samples averaged + * 0b01..8 samples averaged + * 0b10..16 samples averaged + * 0b11..32 samples averaged + */ #define ADC_CFG_AVGS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_AVGS_SHIFT)) & ADC_CFG_AVGS_MASK) #define ADC_CFG_OVWREN_MASK (0x10000U) #define ADC_CFG_OVWREN_SHIFT (16U) +/*! OVWREN - Data Overwrite Enable + * 0b1..Enable the overwriting. + * 0b0..Disable the overwriting. Existing Data in Data result register will not be overwritten by subsequent converted data. + */ #define ADC_CFG_OVWREN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_OVWREN_SHIFT)) & ADC_CFG_OVWREN_MASK) +/*! @} */ /*! @name GC - General control register */ +/*! @{ */ #define ADC_GC_ADACKEN_MASK (0x1U) #define ADC_GC_ADACKEN_SHIFT (0U) +/*! ADACKEN - Asynchronous clock output enable + * 0b0..Asynchronous clock output disabled; Asynchronous clock only enabled if selected by ADICLK and a conversion is active. + * 0b1..Asynchronous clock and clock output enabled regardless of the state of the ADC + */ #define ADC_GC_ADACKEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_ADACKEN_SHIFT)) & ADC_GC_ADACKEN_MASK) #define ADC_GC_DMAEN_MASK (0x2U) #define ADC_GC_DMAEN_SHIFT (1U) +/*! DMAEN - DMA Enable + * 0b0..DMA disabled (default) + * 0b1..DMA enabled + */ #define ADC_GC_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_DMAEN_SHIFT)) & ADC_GC_DMAEN_MASK) #define ADC_GC_ACREN_MASK (0x4U) #define ADC_GC_ACREN_SHIFT (2U) +/*! ACREN - Compare Function Range Enable + * 0b0..Range function disabled. Only the compare value 1 of ADC_CV register (CV1) is compared. + * 0b1..Range function enabled. Both compare values of ADC_CV registers (CV1 and CV2) are compared. + */ #define ADC_GC_ACREN(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_ACREN_SHIFT)) & ADC_GC_ACREN_MASK) #define ADC_GC_ACFGT_MASK (0x8U) #define ADC_GC_ACFGT_SHIFT (3U) +/*! ACFGT - Compare Function Greater Than Enable + * 0b0..Configures "Less Than Threshold, Outside Range Not Inclusive and Inside Range Not Inclusive" functionality based on the values placed in the ADC_CV register. + * 0b1..Configures "Greater Than Or Equal To Threshold, Outside Range Inclusive and Inside Range Inclusive" functionality based on the values placed in the ADC_CV registers. + */ #define ADC_GC_ACFGT(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_ACFGT_SHIFT)) & ADC_GC_ACFGT_MASK) #define ADC_GC_ACFE_MASK (0x10U) #define ADC_GC_ACFE_SHIFT (4U) +/*! ACFE - Compare Function Enable + * 0b0..Compare function disabled + * 0b1..Compare function enabled + */ #define ADC_GC_ACFE(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_ACFE_SHIFT)) & ADC_GC_ACFE_MASK) #define ADC_GC_AVGE_MASK (0x20U) #define ADC_GC_AVGE_SHIFT (5U) +/*! AVGE - Hardware average enable + * 0b0..Hardware average function disabled + * 0b1..Hardware average function enabled + */ #define ADC_GC_AVGE(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_AVGE_SHIFT)) & ADC_GC_AVGE_MASK) #define ADC_GC_ADCO_MASK (0x40U) #define ADC_GC_ADCO_SHIFT (6U) +/*! ADCO - Continuous Conversion Enable + * 0b0..One conversion or one set of conversions if the hardware average function is enabled (AVGE=1) after initiating a conversion. + * 0b1..Continuous conversions or sets of conversions if the hardware average function is enabled (AVGE=1) after initiating a conversion. + */ #define ADC_GC_ADCO(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_ADCO_SHIFT)) & ADC_GC_ADCO_MASK) #define ADC_GC_CAL_MASK (0x80U) #define ADC_GC_CAL_SHIFT (7U) #define ADC_GC_CAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_CAL_SHIFT)) & ADC_GC_CAL_MASK) +/*! @} */ /*! @name GS - General status register */ +/*! @{ */ #define ADC_GS_ADACT_MASK (0x1U) #define ADC_GS_ADACT_SHIFT (0U) +/*! ADACT - Conversion Active + * 0b0..Conversion not in progress. + * 0b1..Conversion in progress. + */ #define ADC_GS_ADACT(x) (((uint32_t)(((uint32_t)(x)) << ADC_GS_ADACT_SHIFT)) & ADC_GS_ADACT_MASK) #define ADC_GS_CALF_MASK (0x2U) #define ADC_GS_CALF_SHIFT (1U) +/*! CALF - Calibration Failed Flag + * 0b0..Calibration completed normally. + * 0b1..Calibration failed. ADC accuracy specifications are not guaranteed. + */ #define ADC_GS_CALF(x) (((uint32_t)(((uint32_t)(x)) << ADC_GS_CALF_SHIFT)) & ADC_GS_CALF_MASK) #define ADC_GS_AWKST_MASK (0x4U) #define ADC_GS_AWKST_SHIFT (2U) +/*! AWKST - Asynchronous wakeup interrupt status + * 0b1..Asynchronous wake up interrupt occurred in stop mode. + * 0b0..No asynchronous interrupt. + */ #define ADC_GS_AWKST(x) (((uint32_t)(((uint32_t)(x)) << ADC_GS_AWKST_SHIFT)) & ADC_GS_AWKST_MASK) +/*! @} */ /*! @name CV - Compare value register */ +/*! @{ */ #define ADC_CV_CV1_MASK (0xFFFU) #define ADC_CV_CV1_SHIFT (0U) #define ADC_CV_CV1(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV_CV1_SHIFT)) & ADC_CV_CV1_MASK) #define ADC_CV_CV2_MASK (0xFFF0000U) #define ADC_CV_CV2_SHIFT (16U) #define ADC_CV_CV2(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV_CV2_SHIFT)) & ADC_CV_CV2_MASK) +/*! @} */ /*! @name OFS - Offset correction value register */ +/*! @{ */ #define ADC_OFS_OFS_MASK (0xFFFU) #define ADC_OFS_OFS_SHIFT (0U) #define ADC_OFS_OFS(x) (((uint32_t)(((uint32_t)(x)) << ADC_OFS_OFS_SHIFT)) & ADC_OFS_OFS_MASK) #define ADC_OFS_SIGN_MASK (0x1000U) #define ADC_OFS_SIGN_SHIFT (12U) +/*! SIGN - Sign bit + * 0b0..The offset value is added with the raw result + * 0b1..The offset value is subtracted from the raw converted value + */ #define ADC_OFS_SIGN(x) (((uint32_t)(((uint32_t)(x)) << ADC_OFS_SIGN_SHIFT)) & ADC_OFS_SIGN_MASK) +/*! @} */ /*! @name CAL - Calibration value register */ +/*! @{ */ #define ADC_CAL_CAL_CODE_MASK (0xFU) #define ADC_CAL_CAL_CODE_SHIFT (0U) #define ADC_CAL_CAL_CODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_CAL_CODE_SHIFT)) & ADC_CAL_CAL_CODE_MASK) +/*! @} */ /*! @@ -1480,16 +1602,8 @@ typedef struct { __IO uint32_t DONE2_ERR_IRQ; /**< ETC DONE_2 and DONE_ERR IRQ State Register, offset: 0x8 */ __IO uint32_t DMA_CTRL; /**< ETC DMA control Register, offset: 0xC */ struct { /* offset: 0x10, array step: 0x28 */ - __IO uint32_t TRIGn_CTRL; /**< - ETC_TRIG0 Control Register - .. - ETC_TRIG7 Control Register - , array offset: 0x10, array step: 0x28 */ - __IO uint32_t TRIGn_COUNTER; /**< - ETC_TRIG0 Counter Register - .. - ETC_TRIG7 Counter Register - , array offset: 0x14, array step: 0x28 */ + __IO uint32_t TRIGn_CTRL; /**< ETC_TRIG0 Control Register..ETC_TRIG7 Control Register, array offset: 0x10, array step: 0x28 */ + __IO uint32_t TRIGn_COUNTER; /**< ETC_TRIG0 Counter Register..ETC_TRIG7 Counter Register, array offset: 0x14, array step: 0x28 */ __IO uint32_t TRIGn_CHAIN_1_0; /**< ETC_TRIG Chain 0/1 Register, array offset: 0x18, array step: 0x28 */ __IO uint32_t TRIGn_CHAIN_3_2; /**< ETC_TRIG Chain 2/3 Register, array offset: 0x1C, array step: 0x28 */ __IO uint32_t TRIGn_CHAIN_5_4; /**< ETC_TRIG Chain 4/5 Register, array offset: 0x20, array step: 0x28 */ @@ -1511,6 +1625,7 @@ typedef struct { */ /*! @name CTRL - ADC_ETC Global Control Register */ +/*! @{ */ #define ADC_ETC_CTRL_TRIG_ENABLE_MASK (0xFFU) #define ADC_ETC_CTRL_TRIG_ENABLE_SHIFT (0U) #define ADC_ETC_CTRL_TRIG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_TRIG_ENABLE_SHIFT)) & ADC_ETC_CTRL_TRIG_ENABLE_MASK) @@ -1529,14 +1644,19 @@ typedef struct { #define ADC_ETC_CTRL_PRE_DIVIDER_MASK (0xFF0000U) #define ADC_ETC_CTRL_PRE_DIVIDER_SHIFT (16U) #define ADC_ETC_CTRL_PRE_DIVIDER(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_PRE_DIVIDER_SHIFT)) & ADC_ETC_CTRL_PRE_DIVIDER_MASK) +#define ADC_ETC_CTRL_DMA_MODE_SEL_MASK (0x20000000U) +#define ADC_ETC_CTRL_DMA_MODE_SEL_SHIFT (29U) +#define ADC_ETC_CTRL_DMA_MODE_SEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_DMA_MODE_SEL_SHIFT)) & ADC_ETC_CTRL_DMA_MODE_SEL_MASK) #define ADC_ETC_CTRL_TSC_BYPASS_MASK (0x40000000U) #define ADC_ETC_CTRL_TSC_BYPASS_SHIFT (30U) #define ADC_ETC_CTRL_TSC_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_TSC_BYPASS_SHIFT)) & ADC_ETC_CTRL_TSC_BYPASS_MASK) #define ADC_ETC_CTRL_SOFTRST_MASK (0x80000000U) #define ADC_ETC_CTRL_SOFTRST_SHIFT (31U) #define ADC_ETC_CTRL_SOFTRST(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_SOFTRST_SHIFT)) & ADC_ETC_CTRL_SOFTRST_MASK) +/*! @} */ /*! @name DONE0_1_IRQ - ETC DONE0 and DONE1 IRQ State Register */ +/*! @{ */ #define ADC_ETC_DONE0_1_IRQ_TRIG0_DONE0_MASK (0x1U) #define ADC_ETC_DONE0_1_IRQ_TRIG0_DONE0_SHIFT (0U) #define ADC_ETC_DONE0_1_IRQ_TRIG0_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG0_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG0_DONE0_MASK) @@ -1585,8 +1705,10 @@ typedef struct { #define ADC_ETC_DONE0_1_IRQ_TRIG7_DONE1_MASK (0x800000U) #define ADC_ETC_DONE0_1_IRQ_TRIG7_DONE1_SHIFT (23U) #define ADC_ETC_DONE0_1_IRQ_TRIG7_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG7_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG7_DONE1_MASK) +/*! @} */ /*! @name DONE2_ERR_IRQ - ETC DONE_2 and DONE_ERR IRQ State Register */ +/*! @{ */ #define ADC_ETC_DONE2_ERR_IRQ_TRIG0_DONE2_MASK (0x1U) #define ADC_ETC_DONE2_ERR_IRQ_TRIG0_DONE2_SHIFT (0U) #define ADC_ETC_DONE2_ERR_IRQ_TRIG0_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG0_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG0_DONE2_MASK) @@ -1635,8 +1757,10 @@ typedef struct { #define ADC_ETC_DONE2_ERR_IRQ_TRIG7_ERR_MASK (0x800000U) #define ADC_ETC_DONE2_ERR_IRQ_TRIG7_ERR_SHIFT (23U) #define ADC_ETC_DONE2_ERR_IRQ_TRIG7_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG7_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG7_ERR_MASK) +/*! @} */ /*! @name DMA_CTRL - ETC DMA control Register */ +/*! @{ */ #define ADC_ETC_DMA_CTRL_TRIG0_ENABLE_MASK (0x1U) #define ADC_ETC_DMA_CTRL_TRIG0_ENABLE_SHIFT (0U) #define ADC_ETC_DMA_CTRL_TRIG0_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG0_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG0_ENABLE_MASK) @@ -1685,12 +1809,10 @@ typedef struct { #define ADC_ETC_DMA_CTRL_TRIG7_REQ_MASK (0x800000U) #define ADC_ETC_DMA_CTRL_TRIG7_REQ_SHIFT (23U) #define ADC_ETC_DMA_CTRL_TRIG7_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG7_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG7_REQ_MASK) +/*! @} */ -/*! @name TRIGn_CTRL - - ETC_TRIG0 Control Register - .. - ETC_TRIG7 Control Register - */ +/*! @name TRIGn_CTRL - ETC_TRIG0 Control Register..ETC_TRIG7 Control Register */ +/*! @{ */ #define ADC_ETC_TRIGn_CTRL_SW_TRIG_MASK (0x1U) #define ADC_ETC_TRIGn_CTRL_SW_TRIG_SHIFT (0U) #define ADC_ETC_TRIGn_CTRL_SW_TRIG(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CTRL_SW_TRIG_SHIFT)) & ADC_ETC_TRIGn_CTRL_SW_TRIG_MASK) @@ -1706,26 +1828,26 @@ typedef struct { #define ADC_ETC_TRIGn_CTRL_SYNC_MODE_MASK (0x10000U) #define ADC_ETC_TRIGn_CTRL_SYNC_MODE_SHIFT (16U) #define ADC_ETC_TRIGn_CTRL_SYNC_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CTRL_SYNC_MODE_SHIFT)) & ADC_ETC_TRIGn_CTRL_SYNC_MODE_MASK) +/*! @} */ /* The count of ADC_ETC_TRIGn_CTRL */ #define ADC_ETC_TRIGn_CTRL_COUNT (8U) -/*! @name TRIGn_COUNTER - - ETC_TRIG0 Counter Register - .. - ETC_TRIG7 Counter Register - */ +/*! @name TRIGn_COUNTER - ETC_TRIG0 Counter Register..ETC_TRIG7 Counter Register */ +/*! @{ */ #define ADC_ETC_TRIGn_COUNTER_INIT_DELAY_MASK (0xFFFFU) #define ADC_ETC_TRIGn_COUNTER_INIT_DELAY_SHIFT (0U) #define ADC_ETC_TRIGn_COUNTER_INIT_DELAY(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_COUNTER_INIT_DELAY_SHIFT)) & ADC_ETC_TRIGn_COUNTER_INIT_DELAY_MASK) #define ADC_ETC_TRIGn_COUNTER_SAMPLE_INTERVAL_MASK (0xFFFF0000U) #define ADC_ETC_TRIGn_COUNTER_SAMPLE_INTERVAL_SHIFT (16U) #define ADC_ETC_TRIGn_COUNTER_SAMPLE_INTERVAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_COUNTER_SAMPLE_INTERVAL_SHIFT)) & ADC_ETC_TRIGn_COUNTER_SAMPLE_INTERVAL_MASK) +/*! @} */ /* The count of ADC_ETC_TRIGn_COUNTER */ #define ADC_ETC_TRIGn_COUNTER_COUNT (8U) /*! @name TRIGn_CHAIN_1_0 - ETC_TRIG Chain 0/1 Register */ +/*! @{ */ #define ADC_ETC_TRIGn_CHAIN_1_0_CSEL0_MASK (0xFU) #define ADC_ETC_TRIGn_CHAIN_1_0_CSEL0_SHIFT (0U) #define ADC_ETC_TRIGn_CHAIN_1_0_CSEL0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_CSEL0_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_CSEL0_MASK) @@ -1750,11 +1872,13 @@ typedef struct { #define ADC_ETC_TRIGn_CHAIN_1_0_IE1_MASK (0x60000000U) #define ADC_ETC_TRIGn_CHAIN_1_0_IE1_SHIFT (29U) #define ADC_ETC_TRIGn_CHAIN_1_0_IE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_IE1_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_IE1_MASK) +/*! @} */ /* The count of ADC_ETC_TRIGn_CHAIN_1_0 */ #define ADC_ETC_TRIGn_CHAIN_1_0_COUNT (8U) /*! @name TRIGn_CHAIN_3_2 - ETC_TRIG Chain 2/3 Register */ +/*! @{ */ #define ADC_ETC_TRIGn_CHAIN_3_2_CSEL2_MASK (0xFU) #define ADC_ETC_TRIGn_CHAIN_3_2_CSEL2_SHIFT (0U) #define ADC_ETC_TRIGn_CHAIN_3_2_CSEL2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_CSEL2_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_CSEL2_MASK) @@ -1779,11 +1903,13 @@ typedef struct { #define ADC_ETC_TRIGn_CHAIN_3_2_IE3_MASK (0x60000000U) #define ADC_ETC_TRIGn_CHAIN_3_2_IE3_SHIFT (29U) #define ADC_ETC_TRIGn_CHAIN_3_2_IE3(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_IE3_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_IE3_MASK) +/*! @} */ /* The count of ADC_ETC_TRIGn_CHAIN_3_2 */ #define ADC_ETC_TRIGn_CHAIN_3_2_COUNT (8U) /*! @name TRIGn_CHAIN_5_4 - ETC_TRIG Chain 4/5 Register */ +/*! @{ */ #define ADC_ETC_TRIGn_CHAIN_5_4_CSEL4_MASK (0xFU) #define ADC_ETC_TRIGn_CHAIN_5_4_CSEL4_SHIFT (0U) #define ADC_ETC_TRIGn_CHAIN_5_4_CSEL4(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_CSEL4_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_CSEL4_MASK) @@ -1808,11 +1934,13 @@ typedef struct { #define ADC_ETC_TRIGn_CHAIN_5_4_IE5_MASK (0x60000000U) #define ADC_ETC_TRIGn_CHAIN_5_4_IE5_SHIFT (29U) #define ADC_ETC_TRIGn_CHAIN_5_4_IE5(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_IE5_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_IE5_MASK) +/*! @} */ /* The count of ADC_ETC_TRIGn_CHAIN_5_4 */ #define ADC_ETC_TRIGn_CHAIN_5_4_COUNT (8U) /*! @name TRIGn_CHAIN_7_6 - ETC_TRIG Chain 6/7 Register */ +/*! @{ */ #define ADC_ETC_TRIGn_CHAIN_7_6_CSEL6_MASK (0xFU) #define ADC_ETC_TRIGn_CHAIN_7_6_CSEL6_SHIFT (0U) #define ADC_ETC_TRIGn_CHAIN_7_6_CSEL6(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_CSEL6_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_CSEL6_MASK) @@ -1837,50 +1965,59 @@ typedef struct { #define ADC_ETC_TRIGn_CHAIN_7_6_IE7_MASK (0x60000000U) #define ADC_ETC_TRIGn_CHAIN_7_6_IE7_SHIFT (29U) #define ADC_ETC_TRIGn_CHAIN_7_6_IE7(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_IE7_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_IE7_MASK) +/*! @} */ /* The count of ADC_ETC_TRIGn_CHAIN_7_6 */ #define ADC_ETC_TRIGn_CHAIN_7_6_COUNT (8U) /*! @name TRIGn_RESULT_1_0 - ETC_TRIG Result Data 1/0 Register */ +/*! @{ */ #define ADC_ETC_TRIGn_RESULT_1_0_DATA0_MASK (0xFFFU) #define ADC_ETC_TRIGn_RESULT_1_0_DATA0_SHIFT (0U) #define ADC_ETC_TRIGn_RESULT_1_0_DATA0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_1_0_DATA0_SHIFT)) & ADC_ETC_TRIGn_RESULT_1_0_DATA0_MASK) #define ADC_ETC_TRIGn_RESULT_1_0_DATA1_MASK (0xFFF0000U) #define ADC_ETC_TRIGn_RESULT_1_0_DATA1_SHIFT (16U) #define ADC_ETC_TRIGn_RESULT_1_0_DATA1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_1_0_DATA1_SHIFT)) & ADC_ETC_TRIGn_RESULT_1_0_DATA1_MASK) +/*! @} */ /* The count of ADC_ETC_TRIGn_RESULT_1_0 */ #define ADC_ETC_TRIGn_RESULT_1_0_COUNT (8U) /*! @name TRIGn_RESULT_3_2 - ETC_TRIG Result Data 3/2 Register */ +/*! @{ */ #define ADC_ETC_TRIGn_RESULT_3_2_DATA2_MASK (0xFFFU) #define ADC_ETC_TRIGn_RESULT_3_2_DATA2_SHIFT (0U) #define ADC_ETC_TRIGn_RESULT_3_2_DATA2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_3_2_DATA2_SHIFT)) & ADC_ETC_TRIGn_RESULT_3_2_DATA2_MASK) #define ADC_ETC_TRIGn_RESULT_3_2_DATA3_MASK (0xFFF0000U) #define ADC_ETC_TRIGn_RESULT_3_2_DATA3_SHIFT (16U) #define ADC_ETC_TRIGn_RESULT_3_2_DATA3(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_3_2_DATA3_SHIFT)) & ADC_ETC_TRIGn_RESULT_3_2_DATA3_MASK) +/*! @} */ /* The count of ADC_ETC_TRIGn_RESULT_3_2 */ #define ADC_ETC_TRIGn_RESULT_3_2_COUNT (8U) /*! @name TRIGn_RESULT_5_4 - ETC_TRIG Result Data 5/4 Register */ +/*! @{ */ #define ADC_ETC_TRIGn_RESULT_5_4_DATA4_MASK (0xFFFU) #define ADC_ETC_TRIGn_RESULT_5_4_DATA4_SHIFT (0U) #define ADC_ETC_TRIGn_RESULT_5_4_DATA4(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_5_4_DATA4_SHIFT)) & ADC_ETC_TRIGn_RESULT_5_4_DATA4_MASK) #define ADC_ETC_TRIGn_RESULT_5_4_DATA5_MASK (0xFFF0000U) #define ADC_ETC_TRIGn_RESULT_5_4_DATA5_SHIFT (16U) #define ADC_ETC_TRIGn_RESULT_5_4_DATA5(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_5_4_DATA5_SHIFT)) & ADC_ETC_TRIGn_RESULT_5_4_DATA5_MASK) +/*! @} */ /* The count of ADC_ETC_TRIGn_RESULT_5_4 */ #define ADC_ETC_TRIGn_RESULT_5_4_COUNT (8U) /*! @name TRIGn_RESULT_7_6 - ETC_TRIG Result Data 7/6 Register */ +/*! @{ */ #define ADC_ETC_TRIGn_RESULT_7_6_DATA6_MASK (0xFFFU) #define ADC_ETC_TRIGn_RESULT_7_6_DATA6_SHIFT (0U) #define ADC_ETC_TRIGn_RESULT_7_6_DATA6(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_7_6_DATA6_SHIFT)) & ADC_ETC_TRIGn_RESULT_7_6_DATA6_MASK) #define ADC_ETC_TRIGn_RESULT_7_6_DATA7_MASK (0xFFF0000U) #define ADC_ETC_TRIGn_RESULT_7_6_DATA7_SHIFT (16U) #define ADC_ETC_TRIGn_RESULT_7_6_DATA7(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_7_6_DATA7_SHIFT)) & ADC_ETC_TRIGn_RESULT_7_6_DATA7_MASK) +/*! @} */ /* The count of ADC_ETC_TRIGn_RESULT_7_6 */ #define ADC_ETC_TRIGn_RESULT_7_6_COUNT (8U) @@ -1939,133 +2076,496 @@ typedef struct { */ /*! @name MPR - Master Priviledge Registers */ +/*! @{ */ #define AIPSTZ_MPR_MPROT5_MASK (0xF00U) #define AIPSTZ_MPR_MPROT5_SHIFT (8U) +/*! MPROT5 + * 0bxxx0..Accesses from this master are forced to user-mode (ips_supervisor_access is forced to zero) regardless of the hprot[1] access attribute. + * 0bxxx1..Accesses from this master are not forced to user-mode. The hprot[1] access attribute is used directly to determine ips_supervisor_access. + * 0bxx0x..This master is not trusted for write accesses. + * 0bxx1x..This master is trusted for write accesses. + * 0bx0xx..This master is not trusted for read accesses. + * 0bx1xx..This master is trusted for read accesses. + * 0b1xxx..Write accesses from this master are allowed to be buffered + */ #define AIPSTZ_MPR_MPROT5(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT5_SHIFT)) & AIPSTZ_MPR_MPROT5_MASK) #define AIPSTZ_MPR_MPROT3_MASK (0xF0000U) #define AIPSTZ_MPR_MPROT3_SHIFT (16U) +/*! MPROT3 + * 0bxxx0..Accesses from this master are forced to user-mode (ips_supervisor_access is forced to zero) regardless of the hprot[1] access attribute. + * 0bxxx1..Accesses from this master are not forced to user-mode. The hprot[1] access attribute is used directly to determine ips_supervisor_access. + * 0bxx0x..This master is not trusted for write accesses. + * 0bxx1x..This master is trusted for write accesses. + * 0bx0xx..This master is not trusted for read accesses. + * 0bx1xx..This master is trusted for read accesses. + * 0b1xxx..Write accesses from this master are allowed to be buffered + */ #define AIPSTZ_MPR_MPROT3(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT3_SHIFT)) & AIPSTZ_MPR_MPROT3_MASK) #define AIPSTZ_MPR_MPROT2_MASK (0xF00000U) #define AIPSTZ_MPR_MPROT2_SHIFT (20U) +/*! MPROT2 + * 0bxxx0..Accesses from this master are forced to user-mode (ips_supervisor_access is forced to zero) regardless of the hprot[1] access attribute. + * 0bxxx1..Accesses from this master are not forced to user-mode. The hprot[1] access attribute is used directly to determine ips_supervisor_access. + * 0bxx0x..This master is not trusted for write accesses. + * 0bxx1x..This master is trusted for write accesses. + * 0bx0xx..This master is not trusted for read accesses. + * 0bx1xx..This master is trusted for read accesses. + * 0b1xxx..Write accesses from this master are allowed to be buffered + */ #define AIPSTZ_MPR_MPROT2(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT2_SHIFT)) & AIPSTZ_MPR_MPROT2_MASK) #define AIPSTZ_MPR_MPROT1_MASK (0xF000000U) #define AIPSTZ_MPR_MPROT1_SHIFT (24U) +/*! MPROT1 + * 0bxxx0..Accesses from this master are forced to user-mode (ips_supervisor_access is forced to zero) regardless of the hprot[1] access attribute. + * 0bxxx1..Accesses from this master are not forced to user-mode. The hprot[1] access attribute is used directly to determine ips_supervisor_access. + * 0bxx0x..This master is not trusted for write accesses. + * 0bxx1x..This master is trusted for write accesses. + * 0bx0xx..This master is not trusted for read accesses. + * 0bx1xx..This master is trusted for read accesses. + * 0b1xxx..Write accesses from this master are allowed to be buffered + */ #define AIPSTZ_MPR_MPROT1(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT1_SHIFT)) & AIPSTZ_MPR_MPROT1_MASK) #define AIPSTZ_MPR_MPROT0_MASK (0xF0000000U) #define AIPSTZ_MPR_MPROT0_SHIFT (28U) +/*! MPROT0 + * 0bxxx0..Accesses from this master are forced to user-mode (ips_supervisor_access is forced to zero) regardless of the hprot[1] access attribute. + * 0bxxx1..Accesses from this master are not forced to user-mode. The hprot[1] access attribute is used directly to determine ips_supervisor_access. + * 0bxx0x..This master is not trusted for write accesses. + * 0bxx1x..This master is trusted for write accesses. + * 0bx0xx..This master is not trusted for read accesses. + * 0bx1xx..This master is trusted for read accesses. + * 0b1xxx..Write accesses from this master are allowed to be buffered + */ #define AIPSTZ_MPR_MPROT0(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT0_SHIFT)) & AIPSTZ_MPR_MPROT0_MASK) +/*! @} */ /*! @name OPACR - Off-Platform Peripheral Access Control Registers */ +/*! @{ */ #define AIPSTZ_OPACR_OPAC7_MASK (0xFU) #define AIPSTZ_OPACR_OPAC7_SHIFT (0U) +/*! OPAC7 + * 0bxxx0..Accesses from an untrusted master are allowed. + * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bxx0x..This peripheral allows write accesses. + * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. + * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must be set. If not, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. + */ #define AIPSTZ_OPACR_OPAC7(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC7_SHIFT)) & AIPSTZ_OPACR_OPAC7_MASK) #define AIPSTZ_OPACR_OPAC6_MASK (0xF0U) #define AIPSTZ_OPACR_OPAC6_SHIFT (4U) +/*! OPAC6 + * 0bxxx0..Accesses from an untrusted master are allowed. + * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bxx0x..This peripheral allows write accesses. + * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. + * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must be set. If not, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. + */ #define AIPSTZ_OPACR_OPAC6(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC6_SHIFT)) & AIPSTZ_OPACR_OPAC6_MASK) #define AIPSTZ_OPACR_OPAC5_MASK (0xF00U) #define AIPSTZ_OPACR_OPAC5_SHIFT (8U) +/*! OPAC5 + * 0bxxx0..Accesses from an untrusted master are allowed. + * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bxx0x..This peripheral allows write accesses. + * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. + * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must be set. If not, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. + */ #define AIPSTZ_OPACR_OPAC5(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC5_SHIFT)) & AIPSTZ_OPACR_OPAC5_MASK) #define AIPSTZ_OPACR_OPAC4_MASK (0xF000U) #define AIPSTZ_OPACR_OPAC4_SHIFT (12U) +/*! OPAC4 + * 0bxxx0..Accesses from an untrusted master are allowed. + * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bxx0x..This peripheral allows write accesses. + * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. + * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must be set. If not, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. + */ #define AIPSTZ_OPACR_OPAC4(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC4_SHIFT)) & AIPSTZ_OPACR_OPAC4_MASK) #define AIPSTZ_OPACR_OPAC3_MASK (0xF0000U) #define AIPSTZ_OPACR_OPAC3_SHIFT (16U) +/*! OPAC3 + * 0bxxx0..Accesses from an untrusted master are allowed. + * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bxx0x..This peripheral allows write accesses. + * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. + * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must be set. If not, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. + */ #define AIPSTZ_OPACR_OPAC3(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC3_SHIFT)) & AIPSTZ_OPACR_OPAC3_MASK) #define AIPSTZ_OPACR_OPAC2_MASK (0xF00000U) #define AIPSTZ_OPACR_OPAC2_SHIFT (20U) +/*! OPAC2 + * 0bxxx0..Accesses from an untrusted master are allowed. + * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bxx0x..This peripheral allows write accesses. + * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. + * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must be set. If not, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. + */ #define AIPSTZ_OPACR_OPAC2(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC2_SHIFT)) & AIPSTZ_OPACR_OPAC2_MASK) #define AIPSTZ_OPACR_OPAC1_MASK (0xF000000U) #define AIPSTZ_OPACR_OPAC1_SHIFT (24U) +/*! OPAC1 + * 0bxxx0..Accesses from an untrusted master are allowed. + * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bxx0x..This peripheral allows write accesses. + * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. + * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must be set. If not, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. + */ #define AIPSTZ_OPACR_OPAC1(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC1_SHIFT)) & AIPSTZ_OPACR_OPAC1_MASK) #define AIPSTZ_OPACR_OPAC0_MASK (0xF0000000U) #define AIPSTZ_OPACR_OPAC0_SHIFT (28U) +/*! OPAC0 + * 0bxxx0..Accesses from an untrusted master are allowed. + * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bxx0x..This peripheral allows write accesses. + * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. + * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must be set. If not, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. + */ #define AIPSTZ_OPACR_OPAC0(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC0_SHIFT)) & AIPSTZ_OPACR_OPAC0_MASK) +/*! @} */ /*! @name OPACR1 - Off-Platform Peripheral Access Control Registers */ +/*! @{ */ #define AIPSTZ_OPACR1_OPAC15_MASK (0xFU) #define AIPSTZ_OPACR1_OPAC15_SHIFT (0U) +/*! OPAC15 + * 0bxxx0..Accesses from an untrusted master are allowed. + * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bxx0x..This peripheral allows write accesses. + * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. + * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must be set. If not, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. + */ #define AIPSTZ_OPACR1_OPAC15(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC15_SHIFT)) & AIPSTZ_OPACR1_OPAC15_MASK) #define AIPSTZ_OPACR1_OPAC14_MASK (0xF0U) #define AIPSTZ_OPACR1_OPAC14_SHIFT (4U) +/*! OPAC14 + * 0bxxx0..Accesses from an untrusted master are allowed. + * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bxx0x..This peripheral allows write accesses. + * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. + * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must be set. If not, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. + */ #define AIPSTZ_OPACR1_OPAC14(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC14_SHIFT)) & AIPSTZ_OPACR1_OPAC14_MASK) #define AIPSTZ_OPACR1_OPAC13_MASK (0xF00U) #define AIPSTZ_OPACR1_OPAC13_SHIFT (8U) +/*! OPAC13 + * 0bxxx0..Accesses from an untrusted master are allowed. + * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bxx0x..This peripheral allows write accesses. + * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. + * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must be set. If not, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. + */ #define AIPSTZ_OPACR1_OPAC13(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC13_SHIFT)) & AIPSTZ_OPACR1_OPAC13_MASK) #define AIPSTZ_OPACR1_OPAC12_MASK (0xF000U) #define AIPSTZ_OPACR1_OPAC12_SHIFT (12U) +/*! OPAC12 + * 0bxxx0..Accesses from an untrusted master are allowed. + * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bxx0x..This peripheral allows write accesses. + * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. + * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must be set. If not, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. + */ #define AIPSTZ_OPACR1_OPAC12(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC12_SHIFT)) & AIPSTZ_OPACR1_OPAC12_MASK) #define AIPSTZ_OPACR1_OPAC11_MASK (0xF0000U) #define AIPSTZ_OPACR1_OPAC11_SHIFT (16U) +/*! OPAC11 + * 0bxxx0..Accesses from an untrusted master are allowed. + * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bxx0x..This peripheral allows write accesses. + * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. + * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must be set. If not, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. + */ #define AIPSTZ_OPACR1_OPAC11(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC11_SHIFT)) & AIPSTZ_OPACR1_OPAC11_MASK) #define AIPSTZ_OPACR1_OPAC10_MASK (0xF00000U) #define AIPSTZ_OPACR1_OPAC10_SHIFT (20U) +/*! OPAC10 + * 0bxxx0..Accesses from an untrusted master are allowed. + * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bxx0x..This peripheral allows write accesses. + * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. + * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must be set. If not, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. + */ #define AIPSTZ_OPACR1_OPAC10(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC10_SHIFT)) & AIPSTZ_OPACR1_OPAC10_MASK) #define AIPSTZ_OPACR1_OPAC9_MASK (0xF000000U) #define AIPSTZ_OPACR1_OPAC9_SHIFT (24U) +/*! OPAC9 + * 0bxxx0..Accesses from an untrusted master are allowed. + * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bxx0x..This peripheral allows write accesses. + * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. + * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must be set. If not, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. + */ #define AIPSTZ_OPACR1_OPAC9(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC9_SHIFT)) & AIPSTZ_OPACR1_OPAC9_MASK) #define AIPSTZ_OPACR1_OPAC8_MASK (0xF0000000U) #define AIPSTZ_OPACR1_OPAC8_SHIFT (28U) +/*! OPAC8 + * 0bxxx0..Accesses from an untrusted master are allowed. + * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bxx0x..This peripheral allows write accesses. + * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. + * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must be set. If not, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. + */ #define AIPSTZ_OPACR1_OPAC8(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC8_SHIFT)) & AIPSTZ_OPACR1_OPAC8_MASK) +/*! @} */ /*! @name OPACR2 - Off-Platform Peripheral Access Control Registers */ +/*! @{ */ #define AIPSTZ_OPACR2_OPAC23_MASK (0xFU) #define AIPSTZ_OPACR2_OPAC23_SHIFT (0U) +/*! OPAC23 + * 0bxxx0..Accesses from an untrusted master are allowed. + * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bxx0x..This peripheral allows write accesses. + * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. + * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must be set. If not, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. + */ #define AIPSTZ_OPACR2_OPAC23(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC23_SHIFT)) & AIPSTZ_OPACR2_OPAC23_MASK) #define AIPSTZ_OPACR2_OPAC22_MASK (0xF0U) #define AIPSTZ_OPACR2_OPAC22_SHIFT (4U) +/*! OPAC22 + * 0bxxx0..Accesses from an untrusted master are allowed. + * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bxx0x..This peripheral allows write accesses. + * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. + * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must be set. If not, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. + */ #define AIPSTZ_OPACR2_OPAC22(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC22_SHIFT)) & AIPSTZ_OPACR2_OPAC22_MASK) #define AIPSTZ_OPACR2_OPAC21_MASK (0xF00U) #define AIPSTZ_OPACR2_OPAC21_SHIFT (8U) +/*! OPAC21 + * 0bxxx0..Accesses from an untrusted master are allowed. + * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bxx0x..This peripheral allows write accesses. + * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. + * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must be set. If not, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. + */ #define AIPSTZ_OPACR2_OPAC21(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC21_SHIFT)) & AIPSTZ_OPACR2_OPAC21_MASK) #define AIPSTZ_OPACR2_OPAC20_MASK (0xF000U) #define AIPSTZ_OPACR2_OPAC20_SHIFT (12U) +/*! OPAC20 + * 0bxxx0..Accesses from an untrusted master are allowed. + * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bxx0x..This peripheral allows write accesses. + * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. + * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must be set. If not, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. + */ #define AIPSTZ_OPACR2_OPAC20(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC20_SHIFT)) & AIPSTZ_OPACR2_OPAC20_MASK) #define AIPSTZ_OPACR2_OPAC19_MASK (0xF0000U) #define AIPSTZ_OPACR2_OPAC19_SHIFT (16U) +/*! OPAC19 + * 0bxxx0..Accesses from an untrusted master are allowed. + * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bxx0x..This peripheral allows write accesses. + * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. + * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must be set. If not, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. + */ #define AIPSTZ_OPACR2_OPAC19(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC19_SHIFT)) & AIPSTZ_OPACR2_OPAC19_MASK) #define AIPSTZ_OPACR2_OPAC18_MASK (0xF00000U) #define AIPSTZ_OPACR2_OPAC18_SHIFT (20U) +/*! OPAC18 + * 0bxxx0..Accesses from an untrusted master are allowed. + * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bxx0x..This peripheral allows write accesses. + * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. + * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must be set. If not, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. + */ #define AIPSTZ_OPACR2_OPAC18(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC18_SHIFT)) & AIPSTZ_OPACR2_OPAC18_MASK) #define AIPSTZ_OPACR2_OPAC17_MASK (0xF000000U) #define AIPSTZ_OPACR2_OPAC17_SHIFT (24U) +/*! OPAC17 + * 0bxxx0..Accesses from an untrusted master are allowed. + * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bxx0x..This peripheral allows write accesses. + * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. + * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must be set. If not, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. + */ #define AIPSTZ_OPACR2_OPAC17(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC17_SHIFT)) & AIPSTZ_OPACR2_OPAC17_MASK) #define AIPSTZ_OPACR2_OPAC16_MASK (0xF0000000U) #define AIPSTZ_OPACR2_OPAC16_SHIFT (28U) +/*! OPAC16 + * 0bxxx0..Accesses from an untrusted master are allowed. + * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bxx0x..This peripheral allows write accesses. + * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. + * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must be set. If not, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. + */ #define AIPSTZ_OPACR2_OPAC16(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC16_SHIFT)) & AIPSTZ_OPACR2_OPAC16_MASK) +/*! @} */ /*! @name OPACR3 - Off-Platform Peripheral Access Control Registers */ +/*! @{ */ #define AIPSTZ_OPACR3_OPAC31_MASK (0xFU) #define AIPSTZ_OPACR3_OPAC31_SHIFT (0U) +/*! OPAC31 + * 0bxxx0..Accesses from an untrusted master are allowed. + * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bxx0x..This peripheral allows write accesses. + * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. + * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must be set. If not, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. + */ #define AIPSTZ_OPACR3_OPAC31(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC31_SHIFT)) & AIPSTZ_OPACR3_OPAC31_MASK) #define AIPSTZ_OPACR3_OPAC30_MASK (0xF0U) #define AIPSTZ_OPACR3_OPAC30_SHIFT (4U) +/*! OPAC30 + * 0bxxx0..Accesses from an untrusted master are allowed. + * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bxx0x..This peripheral allows write accesses. + * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. + * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must be set. If not, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. + */ #define AIPSTZ_OPACR3_OPAC30(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC30_SHIFT)) & AIPSTZ_OPACR3_OPAC30_MASK) #define AIPSTZ_OPACR3_OPAC29_MASK (0xF00U) #define AIPSTZ_OPACR3_OPAC29_SHIFT (8U) +/*! OPAC29 + * 0bxxx0..Accesses from an untrusted master are allowed. + * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bxx0x..This peripheral allows write accesses. + * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. + * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must be set. If not, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. + */ #define AIPSTZ_OPACR3_OPAC29(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC29_SHIFT)) & AIPSTZ_OPACR3_OPAC29_MASK) #define AIPSTZ_OPACR3_OPAC28_MASK (0xF000U) #define AIPSTZ_OPACR3_OPAC28_SHIFT (12U) +/*! OPAC28 + * 0bxxx0..Accesses from an untrusted master are allowed. + * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bxx0x..This peripheral allows write accesses. + * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. + * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must be set. If not, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. + */ #define AIPSTZ_OPACR3_OPAC28(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC28_SHIFT)) & AIPSTZ_OPACR3_OPAC28_MASK) #define AIPSTZ_OPACR3_OPAC27_MASK (0xF0000U) #define AIPSTZ_OPACR3_OPAC27_SHIFT (16U) +/*! OPAC27 + * 0bxxx0..Accesses from an untrusted master are allowed. + * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bxx0x..This peripheral allows write accesses. + * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. + * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must be set. If not, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. + */ #define AIPSTZ_OPACR3_OPAC27(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC27_SHIFT)) & AIPSTZ_OPACR3_OPAC27_MASK) #define AIPSTZ_OPACR3_OPAC26_MASK (0xF00000U) #define AIPSTZ_OPACR3_OPAC26_SHIFT (20U) +/*! OPAC26 + * 0bxxx0..Accesses from an untrusted master are allowed. + * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bxx0x..This peripheral allows write accesses. + * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. + * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must be set. If not, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. + */ #define AIPSTZ_OPACR3_OPAC26(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC26_SHIFT)) & AIPSTZ_OPACR3_OPAC26_MASK) #define AIPSTZ_OPACR3_OPAC25_MASK (0xF000000U) #define AIPSTZ_OPACR3_OPAC25_SHIFT (24U) +/*! OPAC25 + * 0bxxx0..Accesses from an untrusted master are allowed. + * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bxx0x..This peripheral allows write accesses. + * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. + * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must be set. If not, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. + */ #define AIPSTZ_OPACR3_OPAC25(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC25_SHIFT)) & AIPSTZ_OPACR3_OPAC25_MASK) #define AIPSTZ_OPACR3_OPAC24_MASK (0xF0000000U) #define AIPSTZ_OPACR3_OPAC24_SHIFT (28U) +/*! OPAC24 + * 0bxxx0..Accesses from an untrusted master are allowed. + * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bxx0x..This peripheral allows write accesses. + * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. + * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must be set. If not, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. + */ #define AIPSTZ_OPACR3_OPAC24(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC24_SHIFT)) & AIPSTZ_OPACR3_OPAC24_MASK) +/*! @} */ /*! @name OPACR4 - Off-Platform Peripheral Access Control Registers */ +/*! @{ */ #define AIPSTZ_OPACR4_OPAC33_MASK (0xF000000U) #define AIPSTZ_OPACR4_OPAC33_SHIFT (24U) +/*! OPAC33 + * 0bxxx0..Accesses from an untrusted master are allowed. + * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bxx0x..This peripheral allows write accesses. + * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. + * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must be set. If not, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. + */ #define AIPSTZ_OPACR4_OPAC33(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR4_OPAC33_SHIFT)) & AIPSTZ_OPACR4_OPAC33_MASK) #define AIPSTZ_OPACR4_OPAC32_MASK (0xF0000000U) #define AIPSTZ_OPACR4_OPAC32_SHIFT (28U) +/*! OPAC32 + * 0bxxx0..Accesses from an untrusted master are allowed. + * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bxx0x..This peripheral allows write accesses. + * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. + * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must be set. If not, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. + */ #define AIPSTZ_OPACR4_OPAC32(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR4_OPAC32_SHIFT)) & AIPSTZ_OPACR4_OPAC32_MASK) +/*! @} */ /*! @@ -2127,59 +2627,159 @@ typedef struct { */ /*! @name BFCRT01 - Boolean Function Term 0 and 1 Configuration Register for EVENTn */ +/*! @{ */ #define AOI_BFCRT01_PT1_DC_MASK (0x3U) #define AOI_BFCRT01_PT1_DC_SHIFT (0U) +/*! PT1_DC - Product term 1, D input configuration + * 0b00..Force the D input in this product term to a logical zero + * 0b01..Pass the D input in this product term + * 0b10..Complement the D input in this product term + * 0b11..Force the D input in this product term to a logical one + */ #define AOI_BFCRT01_PT1_DC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT1_DC_SHIFT)) & AOI_BFCRT01_PT1_DC_MASK) #define AOI_BFCRT01_PT1_CC_MASK (0xCU) #define AOI_BFCRT01_PT1_CC_SHIFT (2U) +/*! PT1_CC - Product term 1, C input configuration + * 0b00..Force the C input in this product term to a logical zero + * 0b01..Pass the C input in this product term + * 0b10..Complement the C input in this product term + * 0b11..Force the C input in this product term to a logical one + */ #define AOI_BFCRT01_PT1_CC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT1_CC_SHIFT)) & AOI_BFCRT01_PT1_CC_MASK) #define AOI_BFCRT01_PT1_BC_MASK (0x30U) #define AOI_BFCRT01_PT1_BC_SHIFT (4U) +/*! PT1_BC - Product term 1, B input configuration + * 0b00..Force the B input in this product term to a logical zero + * 0b01..Pass the B input in this product term + * 0b10..Complement the B input in this product term + * 0b11..Force the B input in this product term to a logical one + */ #define AOI_BFCRT01_PT1_BC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT1_BC_SHIFT)) & AOI_BFCRT01_PT1_BC_MASK) #define AOI_BFCRT01_PT1_AC_MASK (0xC0U) #define AOI_BFCRT01_PT1_AC_SHIFT (6U) +/*! PT1_AC - Product term 1, A input configuration + * 0b00..Force the A input in this product term to a logical zero + * 0b01..Pass the A input in this product term + * 0b10..Complement the A input in this product term + * 0b11..Force the A input in this product term to a logical one + */ #define AOI_BFCRT01_PT1_AC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT1_AC_SHIFT)) & AOI_BFCRT01_PT1_AC_MASK) #define AOI_BFCRT01_PT0_DC_MASK (0x300U) #define AOI_BFCRT01_PT0_DC_SHIFT (8U) +/*! PT0_DC - Product term 0, D input configuration + * 0b00..Force the D input in this product term to a logical zero + * 0b01..Pass the D input in this product term + * 0b10..Complement the D input in this product term + * 0b11..Force the D input in this product term to a logical one + */ #define AOI_BFCRT01_PT0_DC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT0_DC_SHIFT)) & AOI_BFCRT01_PT0_DC_MASK) #define AOI_BFCRT01_PT0_CC_MASK (0xC00U) #define AOI_BFCRT01_PT0_CC_SHIFT (10U) +/*! PT0_CC - Product term 0, C input configuration + * 0b00..Force the C input in this product term to a logical zero + * 0b01..Pass the C input in this product term + * 0b10..Complement the C input in this product term + * 0b11..Force the C input in this product term to a logical one + */ #define AOI_BFCRT01_PT0_CC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT0_CC_SHIFT)) & AOI_BFCRT01_PT0_CC_MASK) #define AOI_BFCRT01_PT0_BC_MASK (0x3000U) #define AOI_BFCRT01_PT0_BC_SHIFT (12U) +/*! PT0_BC - Product term 0, B input configuration + * 0b00..Force the B input in this product term to a logical zero + * 0b01..Pass the B input in this product term + * 0b10..Complement the B input in this product term + * 0b11..Force the B input in this product term to a logical one + */ #define AOI_BFCRT01_PT0_BC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT0_BC_SHIFT)) & AOI_BFCRT01_PT0_BC_MASK) #define AOI_BFCRT01_PT0_AC_MASK (0xC000U) #define AOI_BFCRT01_PT0_AC_SHIFT (14U) +/*! PT0_AC - Product term 0, A input configuration + * 0b00..Force the A input in this product term to a logical zero + * 0b01..Pass the A input in this product term + * 0b10..Complement the A input in this product term + * 0b11..Force the A input in this product term to a logical one + */ #define AOI_BFCRT01_PT0_AC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT0_AC_SHIFT)) & AOI_BFCRT01_PT0_AC_MASK) +/*! @} */ /* The count of AOI_BFCRT01 */ #define AOI_BFCRT01_COUNT (4U) /*! @name BFCRT23 - Boolean Function Term 2 and 3 Configuration Register for EVENTn */ +/*! @{ */ #define AOI_BFCRT23_PT3_DC_MASK (0x3U) #define AOI_BFCRT23_PT3_DC_SHIFT (0U) +/*! PT3_DC - Product term 3, D input configuration + * 0b00..Force the D input in this product term to a logical zero + * 0b01..Pass the D input in this product term + * 0b10..Complement the D input in this product term + * 0b11..Force the D input in this product term to a logical one + */ #define AOI_BFCRT23_PT3_DC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT3_DC_SHIFT)) & AOI_BFCRT23_PT3_DC_MASK) #define AOI_BFCRT23_PT3_CC_MASK (0xCU) #define AOI_BFCRT23_PT3_CC_SHIFT (2U) +/*! PT3_CC - Product term 3, C input configuration + * 0b00..Force the C input in this product term to a logical zero + * 0b01..Pass the C input in this product term + * 0b10..Complement the C input in this product term + * 0b11..Force the C input in this product term to a logical one + */ #define AOI_BFCRT23_PT3_CC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT3_CC_SHIFT)) & AOI_BFCRT23_PT3_CC_MASK) #define AOI_BFCRT23_PT3_BC_MASK (0x30U) #define AOI_BFCRT23_PT3_BC_SHIFT (4U) +/*! PT3_BC - Product term 3, B input configuration + * 0b00..Force the B input in this product term to a logical zero + * 0b01..Pass the B input in this product term + * 0b10..Complement the B input in this product term + * 0b11..Force the B input in this product term to a logical one + */ #define AOI_BFCRT23_PT3_BC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT3_BC_SHIFT)) & AOI_BFCRT23_PT3_BC_MASK) #define AOI_BFCRT23_PT3_AC_MASK (0xC0U) #define AOI_BFCRT23_PT3_AC_SHIFT (6U) +/*! PT3_AC - Product term 3, A input configuration + * 0b00..Force the A input in this product term to a logical zero + * 0b01..Pass the A input in this product term + * 0b10..Complement the A input in this product term + * 0b11..Force the A input in this product term to a logical one + */ #define AOI_BFCRT23_PT3_AC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT3_AC_SHIFT)) & AOI_BFCRT23_PT3_AC_MASK) #define AOI_BFCRT23_PT2_DC_MASK (0x300U) #define AOI_BFCRT23_PT2_DC_SHIFT (8U) +/*! PT2_DC - Product term 2, D input configuration + * 0b00..Force the D input in this product term to a logical zero + * 0b01..Pass the D input in this product term + * 0b10..Complement the D input in this product term + * 0b11..Force the D input in this product term to a logical one + */ #define AOI_BFCRT23_PT2_DC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT2_DC_SHIFT)) & AOI_BFCRT23_PT2_DC_MASK) #define AOI_BFCRT23_PT2_CC_MASK (0xC00U) #define AOI_BFCRT23_PT2_CC_SHIFT (10U) +/*! PT2_CC - Product term 2, C input configuration + * 0b00..Force the C input in this product term to a logical zero + * 0b01..Pass the C input in this product term + * 0b10..Complement the C input in this product term + * 0b11..Force the C input in this product term to a logical one + */ #define AOI_BFCRT23_PT2_CC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT2_CC_SHIFT)) & AOI_BFCRT23_PT2_CC_MASK) #define AOI_BFCRT23_PT2_BC_MASK (0x3000U) #define AOI_BFCRT23_PT2_BC_SHIFT (12U) +/*! PT2_BC - Product term 2, B input configuration + * 0b00..Force the B input in this product term to a logical zero + * 0b01..Pass the B input in this product term + * 0b10..Complement the B input in this product term + * 0b11..Force the B input in this product term to a logical one + */ #define AOI_BFCRT23_PT2_BC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT2_BC_SHIFT)) & AOI_BFCRT23_PT2_BC_MASK) #define AOI_BFCRT23_PT2_AC_MASK (0xC000U) #define AOI_BFCRT23_PT2_AC_SHIFT (14U) +/*! PT2_AC - Product term 2, A input configuration + * 0b00..Force the A input in this product term to a logical zero + * 0b01..Pass the A input in this product term + * 0b10..Complement the A input in this product term + * 0b11..Force the A input in this product term to a logical one + */ #define AOI_BFCRT23_PT2_AC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT2_AC_SHIFT)) & AOI_BFCRT23_PT2_AC_MASK) +/*! @} */ /* The count of AOI_BFCRT23 */ #define AOI_BFCRT23_COUNT (4U) @@ -2250,8 +2850,13 @@ typedef struct { */ /*! @name CTRL - BEE Control Register */ +/*! @{ */ #define BEE_CTRL_BEE_ENABLE_MASK (0x1U) #define BEE_CTRL_BEE_ENABLE_SHIFT (0U) +/*! BEE_ENABLE + * 0b0..Disable BEE + * 0b1..Enable BEE + */ #define BEE_CTRL_BEE_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_BEE_ENABLE_SHIFT)) & BEE_CTRL_BEE_ENABLE_MASK) #define BEE_CTRL_CTRL_CLK_EN_MASK (0x2U) #define BEE_CTRL_CTRL_CLK_EN_SHIFT (1U) @@ -2264,24 +2869,40 @@ typedef struct { #define BEE_CTRL_KEY_VALID(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_KEY_VALID_SHIFT)) & BEE_CTRL_KEY_VALID_MASK) #define BEE_CTRL_KEY_REGION_SEL_MASK (0x20U) #define BEE_CTRL_KEY_REGION_SEL_SHIFT (5U) +/*! KEY_REGION_SEL + * 0b0..Load AES key for region0 + * 0b1..Load AES key for region1 + */ #define BEE_CTRL_KEY_REGION_SEL(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_KEY_REGION_SEL_SHIFT)) & BEE_CTRL_KEY_REGION_SEL_MASK) #define BEE_CTRL_AC_PROT_EN_MASK (0x40U) #define BEE_CTRL_AC_PROT_EN_SHIFT (6U) #define BEE_CTRL_AC_PROT_EN(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_AC_PROT_EN_SHIFT)) & BEE_CTRL_AC_PROT_EN_MASK) #define BEE_CTRL_LITTLE_ENDIAN_MASK (0x80U) #define BEE_CTRL_LITTLE_ENDIAN_SHIFT (7U) +/*! LITTLE_ENDIAN + * 0b0..The input and output data of the AES core is swapped as below: {B15,B14,B13,B12,B11,B10,B9,B8, B7,B6,B5,B4,B3,B2,B1,B0} swap to {B0,B1,B2,B3,B4,B5,B6,B7, B8,B9,B10,B11,B12,B13,B14,B15}, where B0~B15 refers to Byte0 to Byte15. + * 0b1..The input and output data of AES core is not swapped. + */ #define BEE_CTRL_LITTLE_ENDIAN(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_LITTLE_ENDIAN_SHIFT)) & BEE_CTRL_LITTLE_ENDIAN_MASK) #define BEE_CTRL_SECURITY_LEVEL_R0_MASK (0x300U) #define BEE_CTRL_SECURITY_LEVEL_R0_SHIFT (8U) #define BEE_CTRL_SECURITY_LEVEL_R0(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_SECURITY_LEVEL_R0_SHIFT)) & BEE_CTRL_SECURITY_LEVEL_R0_MASK) #define BEE_CTRL_CTRL_AES_MODE_R0_MASK (0x400U) #define BEE_CTRL_CTRL_AES_MODE_R0_SHIFT (10U) +/*! CTRL_AES_MODE_R0 + * 0b0..ECB + * 0b1..CTR + */ #define BEE_CTRL_CTRL_AES_MODE_R0(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_AES_MODE_R0_SHIFT)) & BEE_CTRL_CTRL_AES_MODE_R0_MASK) #define BEE_CTRL_SECURITY_LEVEL_R1_MASK (0x3000U) #define BEE_CTRL_SECURITY_LEVEL_R1_SHIFT (12U) #define BEE_CTRL_SECURITY_LEVEL_R1(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_SECURITY_LEVEL_R1_SHIFT)) & BEE_CTRL_SECURITY_LEVEL_R1_MASK) #define BEE_CTRL_CTRL_AES_MODE_R1_MASK (0x4000U) #define BEE_CTRL_CTRL_AES_MODE_R1_SHIFT (14U) +/*! CTRL_AES_MODE_R1 + * 0b0..ECB + * 0b1..CTR + */ #define BEE_CTRL_CTRL_AES_MODE_R1(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_AES_MODE_R1_SHIFT)) & BEE_CTRL_CTRL_AES_MODE_R1_MASK) #define BEE_CTRL_BEE_ENABLE_LOCK_MASK (0x10000U) #define BEE_CTRL_BEE_ENABLE_LOCK_SHIFT (16U) @@ -2325,100 +2946,135 @@ typedef struct { #define BEE_CTRL_REGION1_KEY_LOCK_MASK (0x80000000U) #define BEE_CTRL_REGION1_KEY_LOCK_SHIFT (31U) #define BEE_CTRL_REGION1_KEY_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_REGION1_KEY_LOCK_SHIFT)) & BEE_CTRL_REGION1_KEY_LOCK_MASK) +/*! @} */ /*! @name ADDR_OFFSET0 - */ +/*! @{ */ #define BEE_ADDR_OFFSET0_ADDR_OFFSET0_MASK (0xFFFFU) #define BEE_ADDR_OFFSET0_ADDR_OFFSET0_SHIFT (0U) #define BEE_ADDR_OFFSET0_ADDR_OFFSET0(x) (((uint32_t)(((uint32_t)(x)) << BEE_ADDR_OFFSET0_ADDR_OFFSET0_SHIFT)) & BEE_ADDR_OFFSET0_ADDR_OFFSET0_MASK) #define BEE_ADDR_OFFSET0_ADDR_OFFSET0_LOCK_MASK (0xFFFF0000U) #define BEE_ADDR_OFFSET0_ADDR_OFFSET0_LOCK_SHIFT (16U) #define BEE_ADDR_OFFSET0_ADDR_OFFSET0_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_ADDR_OFFSET0_ADDR_OFFSET0_LOCK_SHIFT)) & BEE_ADDR_OFFSET0_ADDR_OFFSET0_LOCK_MASK) +/*! @} */ /*! @name ADDR_OFFSET1 - */ -#define BEE_ADDR_OFFSET1_ADDR_OFFSET0_MASK (0xFFFFU) -#define BEE_ADDR_OFFSET1_ADDR_OFFSET0_SHIFT (0U) -#define BEE_ADDR_OFFSET1_ADDR_OFFSET0(x) (((uint32_t)(((uint32_t)(x)) << BEE_ADDR_OFFSET1_ADDR_OFFSET0_SHIFT)) & BEE_ADDR_OFFSET1_ADDR_OFFSET0_MASK) -#define BEE_ADDR_OFFSET1_ADDR_OFFSET0_LOCK_MASK (0xFFFF0000U) -#define BEE_ADDR_OFFSET1_ADDR_OFFSET0_LOCK_SHIFT (16U) -#define BEE_ADDR_OFFSET1_ADDR_OFFSET0_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_ADDR_OFFSET1_ADDR_OFFSET0_LOCK_SHIFT)) & BEE_ADDR_OFFSET1_ADDR_OFFSET0_LOCK_MASK) +/*! @{ */ +#define BEE_ADDR_OFFSET1_ADDR_OFFSET1_MASK (0xFFFFU) +#define BEE_ADDR_OFFSET1_ADDR_OFFSET1_SHIFT (0U) +#define BEE_ADDR_OFFSET1_ADDR_OFFSET1(x) (((uint32_t)(((uint32_t)(x)) << BEE_ADDR_OFFSET1_ADDR_OFFSET1_SHIFT)) & BEE_ADDR_OFFSET1_ADDR_OFFSET1_MASK) +#define BEE_ADDR_OFFSET1_ADDR_OFFSET1_LOCK_MASK (0xFFFF0000U) +#define BEE_ADDR_OFFSET1_ADDR_OFFSET1_LOCK_SHIFT (16U) +#define BEE_ADDR_OFFSET1_ADDR_OFFSET1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_ADDR_OFFSET1_ADDR_OFFSET1_LOCK_SHIFT)) & BEE_ADDR_OFFSET1_ADDR_OFFSET1_LOCK_MASK) +/*! @} */ /*! @name AES_KEY0_W0 - */ +/*! @{ */ #define BEE_AES_KEY0_W0_KEY0_MASK (0xFFFFFFFFU) #define BEE_AES_KEY0_W0_KEY0_SHIFT (0U) #define BEE_AES_KEY0_W0_KEY0(x) (((uint32_t)(((uint32_t)(x)) << BEE_AES_KEY0_W0_KEY0_SHIFT)) & BEE_AES_KEY0_W0_KEY0_MASK) +/*! @} */ /*! @name AES_KEY0_W1 - */ +/*! @{ */ #define BEE_AES_KEY0_W1_KEY1_MASK (0xFFFFFFFFU) #define BEE_AES_KEY0_W1_KEY1_SHIFT (0U) #define BEE_AES_KEY0_W1_KEY1(x) (((uint32_t)(((uint32_t)(x)) << BEE_AES_KEY0_W1_KEY1_SHIFT)) & BEE_AES_KEY0_W1_KEY1_MASK) +/*! @} */ /*! @name AES_KEY0_W2 - */ +/*! @{ */ #define BEE_AES_KEY0_W2_KEY2_MASK (0xFFFFFFFFU) #define BEE_AES_KEY0_W2_KEY2_SHIFT (0U) #define BEE_AES_KEY0_W2_KEY2(x) (((uint32_t)(((uint32_t)(x)) << BEE_AES_KEY0_W2_KEY2_SHIFT)) & BEE_AES_KEY0_W2_KEY2_MASK) +/*! @} */ /*! @name AES_KEY0_W3 - */ +/*! @{ */ #define BEE_AES_KEY0_W3_KEY3_MASK (0xFFFFFFFFU) #define BEE_AES_KEY0_W3_KEY3_SHIFT (0U) #define BEE_AES_KEY0_W3_KEY3(x) (((uint32_t)(((uint32_t)(x)) << BEE_AES_KEY0_W3_KEY3_SHIFT)) & BEE_AES_KEY0_W3_KEY3_MASK) +/*! @} */ /*! @name STATUS - */ +/*! @{ */ #define BEE_STATUS_IRQ_VEC_MASK (0xFFU) #define BEE_STATUS_IRQ_VEC_SHIFT (0U) #define BEE_STATUS_IRQ_VEC(x) (((uint32_t)(((uint32_t)(x)) << BEE_STATUS_IRQ_VEC_SHIFT)) & BEE_STATUS_IRQ_VEC_MASK) #define BEE_STATUS_BEE_IDLE_MASK (0x100U) #define BEE_STATUS_BEE_IDLE_SHIFT (8U) #define BEE_STATUS_BEE_IDLE(x) (((uint32_t)(((uint32_t)(x)) << BEE_STATUS_BEE_IDLE_SHIFT)) & BEE_STATUS_BEE_IDLE_MASK) +/*! @} */ /*! @name CTR_NONCE0_W0 - */ +/*! @{ */ #define BEE_CTR_NONCE0_W0_NONCE00_MASK (0xFFFFFFFFU) #define BEE_CTR_NONCE0_W0_NONCE00_SHIFT (0U) #define BEE_CTR_NONCE0_W0_NONCE00(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE0_W0_NONCE00_SHIFT)) & BEE_CTR_NONCE0_W0_NONCE00_MASK) +/*! @} */ /*! @name CTR_NONCE0_W1 - */ +/*! @{ */ #define BEE_CTR_NONCE0_W1_NONCE01_MASK (0xFFFFFFFFU) #define BEE_CTR_NONCE0_W1_NONCE01_SHIFT (0U) #define BEE_CTR_NONCE0_W1_NONCE01(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE0_W1_NONCE01_SHIFT)) & BEE_CTR_NONCE0_W1_NONCE01_MASK) +/*! @} */ /*! @name CTR_NONCE0_W2 - */ +/*! @{ */ #define BEE_CTR_NONCE0_W2_NONCE02_MASK (0xFFFFFFFFU) #define BEE_CTR_NONCE0_W2_NONCE02_SHIFT (0U) #define BEE_CTR_NONCE0_W2_NONCE02(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE0_W2_NONCE02_SHIFT)) & BEE_CTR_NONCE0_W2_NONCE02_MASK) +/*! @} */ /*! @name CTR_NONCE0_W3 - */ +/*! @{ */ #define BEE_CTR_NONCE0_W3_NONCE03_MASK (0xFFFFFFFFU) #define BEE_CTR_NONCE0_W3_NONCE03_SHIFT (0U) #define BEE_CTR_NONCE0_W3_NONCE03(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE0_W3_NONCE03_SHIFT)) & BEE_CTR_NONCE0_W3_NONCE03_MASK) +/*! @} */ /*! @name CTR_NONCE1_W0 - */ +/*! @{ */ #define BEE_CTR_NONCE1_W0_NONCE10_MASK (0xFFFFFFFFU) #define BEE_CTR_NONCE1_W0_NONCE10_SHIFT (0U) #define BEE_CTR_NONCE1_W0_NONCE10(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE1_W0_NONCE10_SHIFT)) & BEE_CTR_NONCE1_W0_NONCE10_MASK) +/*! @} */ /*! @name CTR_NONCE1_W1 - */ +/*! @{ */ #define BEE_CTR_NONCE1_W1_NONCE11_MASK (0xFFFFFFFFU) #define BEE_CTR_NONCE1_W1_NONCE11_SHIFT (0U) #define BEE_CTR_NONCE1_W1_NONCE11(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE1_W1_NONCE11_SHIFT)) & BEE_CTR_NONCE1_W1_NONCE11_MASK) +/*! @} */ /*! @name CTR_NONCE1_W2 - */ +/*! @{ */ #define BEE_CTR_NONCE1_W2_NONCE12_MASK (0xFFFFFFFFU) #define BEE_CTR_NONCE1_W2_NONCE12_SHIFT (0U) #define BEE_CTR_NONCE1_W2_NONCE12(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE1_W2_NONCE12_SHIFT)) & BEE_CTR_NONCE1_W2_NONCE12_MASK) +/*! @} */ /*! @name CTR_NONCE1_W3 - */ +/*! @{ */ #define BEE_CTR_NONCE1_W3_NONCE13_MASK (0xFFFFFFFFU) #define BEE_CTR_NONCE1_W3_NONCE13_SHIFT (0U) #define BEE_CTR_NONCE1_W3_NONCE13(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE1_W3_NONCE13_SHIFT)) & BEE_CTR_NONCE1_W3_NONCE13_MASK) +/*! @} */ /*! @name REGION1_TOP - */ +/*! @{ */ #define BEE_REGION1_TOP_REGION1_TOP_MASK (0xFFFFFFFFU) #define BEE_REGION1_TOP_REGION1_TOP_SHIFT (0U) #define BEE_REGION1_TOP_REGION1_TOP(x) (((uint32_t)(((uint32_t)(x)) << BEE_REGION1_TOP_REGION1_TOP_SHIFT)) & BEE_REGION1_TOP_REGION1_TOP_MASK) +/*! @} */ /*! @name REGION1_BOT - */ +/*! @{ */ #define BEE_REGION1_BOT_REGION1_BOT_MASK (0xFFFFFFFFU) #define BEE_REGION1_BOT_REGION1_BOT_SHIFT (0U) #define BEE_REGION1_BOT_REGION1_BOT(x) (((uint32_t)(((uint32_t)(x)) << BEE_REGION1_BOT_REGION1_BOT_SHIFT)) & BEE_REGION1_BOT_REGION1_BOT_MASK) +/*! @} */ /*! @@ -2471,16 +3127,19 @@ typedef struct { __I uint32_t CRCR; /**< CRC Register, offset: 0x44 */ __IO uint32_t RXFGMASK; /**< Rx FIFO Global Mask Register, offset: 0x48 */ __I uint32_t RXFIR; /**< Rx FIFO Information Register, offset: 0x4C */ - uint8_t RESERVED_2[48]; + uint8_t RESERVED_2[8]; + __I uint32_t DBG1; /**< Debug 1 register, offset: 0x58 */ + __I uint32_t DBG2; /**< Debug 2 register, offset: 0x5C */ + uint8_t RESERVED_3[32]; struct { /* offset: 0x80, array step: 0x10 */ __IO uint32_t CS; /**< Message Buffer 0 CS Register..Message Buffer 63 CS Register, array offset: 0x80, array step: 0x10 */ __IO uint32_t ID; /**< Message Buffer 0 ID Register..Message Buffer 63 ID Register, array offset: 0x84, array step: 0x10 */ __IO uint32_t WORD0; /**< Message Buffer 0 WORD0 Register..Message Buffer 63 WORD0 Register, array offset: 0x88, array step: 0x10 */ __IO uint32_t WORD1; /**< Message Buffer 0 WORD1 Register..Message Buffer 63 WORD1 Register, array offset: 0x8C, array step: 0x10 */ } MB[64]; - uint8_t RESERVED_3[1024]; + uint8_t RESERVED_4[1024]; __IO uint32_t RXIMR[64]; /**< Rx Individual Mask Registers, array offset: 0x880, array step: 0x4 */ - uint8_t RESERVED_4[96]; + uint8_t RESERVED_5[96]; __IO uint32_t GFWR; /**< Glitch Filter Width Registers, offset: 0x9E0 */ } CAN_Type; @@ -2494,97 +3153,214 @@ typedef struct { */ /*! @name MCR - Module Configuration Register */ +/*! @{ */ #define CAN_MCR_MAXMB_MASK (0x7FU) #define CAN_MCR_MAXMB_SHIFT (0U) #define CAN_MCR_MAXMB(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_MAXMB_SHIFT)) & CAN_MCR_MAXMB_MASK) #define CAN_MCR_IDAM_MASK (0x300U) #define CAN_MCR_IDAM_SHIFT (8U) +/*! IDAM + * 0b00..Format A One full ID (standard or extended) per ID filter Table element. + * 0b01..Format B Two full standard IDs or two partial 14-bit extended IDs per ID filter Table element. + * 0b10..Format C Four partial 8-bit IDs (standard or extended) per ID filter Table element. + * 0b11..Format D All frames rejected. + */ #define CAN_MCR_IDAM(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_IDAM_SHIFT)) & CAN_MCR_IDAM_MASK) #define CAN_MCR_AEN_MASK (0x1000U) #define CAN_MCR_AEN_SHIFT (12U) +/*! AEN + * 0b1..Abort enabled + * 0b0..Abort disabled + */ #define CAN_MCR_AEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_AEN_SHIFT)) & CAN_MCR_AEN_MASK) #define CAN_MCR_LPRIOEN_MASK (0x2000U) #define CAN_MCR_LPRIOEN_SHIFT (13U) +/*! LPRIOEN + * 0b1..Local Priority enabled + * 0b0..Local Priority disabled + */ #define CAN_MCR_LPRIOEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_LPRIOEN_SHIFT)) & CAN_MCR_LPRIOEN_MASK) #define CAN_MCR_IRMQ_MASK (0x10000U) #define CAN_MCR_IRMQ_SHIFT (16U) +/*! IRMQ + * 0b1..Individual Rx masking and queue feature are enabled. + * 0b0..Individual Rx masking and queue feature are disabled.For backward compatibility, the reading of C/S word locks the MB even if it is EMPTY. + */ #define CAN_MCR_IRMQ(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_IRMQ_SHIFT)) & CAN_MCR_IRMQ_MASK) #define CAN_MCR_SRXDIS_MASK (0x20000U) #define CAN_MCR_SRXDIS_SHIFT (17U) +/*! SRXDIS + * 0b1..Self reception disabled + * 0b0..Self reception enabled + */ #define CAN_MCR_SRXDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SRXDIS_SHIFT)) & CAN_MCR_SRXDIS_MASK) #define CAN_MCR_WAKSRC_MASK (0x80000U) #define CAN_MCR_WAKSRC_SHIFT (19U) +/*! WAKSRC + * 0b1..FLEXCAN uses the filtered FLEXCAN_RX input to detect recessive to dominant edges on the CAN bus + * 0b0..FLEXCAN uses the unfiltered FLEXCAN_RX input to detect recessive to dominant edges on the CAN bus. + */ #define CAN_MCR_WAKSRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WAKSRC_SHIFT)) & CAN_MCR_WAKSRC_MASK) #define CAN_MCR_LPMACK_MASK (0x100000U) #define CAN_MCR_LPMACK_SHIFT (20U) +/*! LPMACK + * 0b1..FLEXCAN is either in Disable Mode, or Stop mode + * 0b0..FLEXCAN not in any of the low power modes + */ #define CAN_MCR_LPMACK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_LPMACK_SHIFT)) & CAN_MCR_LPMACK_MASK) #define CAN_MCR_WRNEN_MASK (0x200000U) #define CAN_MCR_WRNEN_SHIFT (21U) +/*! WRNEN + * 0b1..TWRN_INT and RWRN_INT bits are set when the respective error counter transition from <96 to >= 96. + * 0b0..TWRN_INT and RWRN_INT bits are zero, independent of the values in the error counters. + */ #define CAN_MCR_WRNEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WRNEN_SHIFT)) & CAN_MCR_WRNEN_MASK) #define CAN_MCR_SLFWAK_MASK (0x400000U) #define CAN_MCR_SLFWAK_SHIFT (22U) +/*! SLFWAK + * 0b1..FLEXCAN Self Wake Up feature is enabled + * 0b0..FLEXCAN Self Wake Up feature is disabled + */ #define CAN_MCR_SLFWAK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SLFWAK_SHIFT)) & CAN_MCR_SLFWAK_MASK) #define CAN_MCR_SUPV_MASK (0x800000U) #define CAN_MCR_SUPV_SHIFT (23U) +/*! SUPV + * 0b1..FlexCAN is in Supervisor Mode. Affected registers allow only Supervisor access. Unrestricted access behaves as though the access was done to an unimplemented register location + * 0b0..FlexCAN is in User Mode. Affected registers allow both Supervisor and Unrestricted accesses + */ #define CAN_MCR_SUPV(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SUPV_SHIFT)) & CAN_MCR_SUPV_MASK) #define CAN_MCR_FRZACK_MASK (0x1000000U) #define CAN_MCR_FRZACK_SHIFT (24U) +/*! FRZACK + * 0b1..FLEXCAN in Freeze Mode, prescaler stopped + * 0b0..FLEXCAN not in Freeze Mode, prescaler running + */ #define CAN_MCR_FRZACK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FRZACK_SHIFT)) & CAN_MCR_FRZACK_MASK) #define CAN_MCR_SOFTRST_MASK (0x2000000U) #define CAN_MCR_SOFTRST_SHIFT (25U) +/*! SOFTRST + * 0b1..Reset the registers + * 0b0..No reset request + */ #define CAN_MCR_SOFTRST(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SOFTRST_SHIFT)) & CAN_MCR_SOFTRST_MASK) #define CAN_MCR_WAKMSK_MASK (0x4000000U) #define CAN_MCR_WAKMSK_SHIFT (26U) +/*! WAKMSK + * 0b1..Wake Up Interrupt is enabled + * 0b0..Wake Up Interrupt is disabled + */ #define CAN_MCR_WAKMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WAKMSK_SHIFT)) & CAN_MCR_WAKMSK_MASK) #define CAN_MCR_NOTRDY_MASK (0x8000000U) #define CAN_MCR_NOTRDY_SHIFT (27U) +/*! NOTRDY + * 0b1..FLEXCAN module is either in Disable Mode, Stop Mode or Freeze Mode + * 0b0..FLEXCAN module is either in Normal Mode, Listen-Only Mode or Loop-Back Mode + */ #define CAN_MCR_NOTRDY(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_NOTRDY_SHIFT)) & CAN_MCR_NOTRDY_MASK) #define CAN_MCR_HALT_MASK (0x10000000U) #define CAN_MCR_HALT_SHIFT (28U) +/*! HALT + * 0b1..Enters Freeze Mode if the FRZ bit is asserted. + * 0b0..No Freeze Mode request. + */ #define CAN_MCR_HALT(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_HALT_SHIFT)) & CAN_MCR_HALT_MASK) #define CAN_MCR_RFEN_MASK (0x20000000U) #define CAN_MCR_RFEN_SHIFT (29U) +/*! RFEN + * 0b1..FIFO enabled + * 0b0..FIFO not enabled + */ #define CAN_MCR_RFEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_RFEN_SHIFT)) & CAN_MCR_RFEN_MASK) #define CAN_MCR_FRZ_MASK (0x40000000U) #define CAN_MCR_FRZ_SHIFT (30U) +/*! FRZ + * 0b1..Enabled to enter Freeze Mode + * 0b0..Not enabled to enter Freeze Mode + */ #define CAN_MCR_FRZ(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FRZ_SHIFT)) & CAN_MCR_FRZ_MASK) #define CAN_MCR_MDIS_MASK (0x80000000U) #define CAN_MCR_MDIS_SHIFT (31U) +/*! MDIS + * 0b1..Disable the FLEXCAN module + * 0b0..Enable the FLEXCAN module + */ #define CAN_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_MDIS_SHIFT)) & CAN_MCR_MDIS_MASK) +/*! @} */ /*! @name CTRL1 - Control 1 Register */ +/*! @{ */ #define CAN_CTRL1_PROPSEG_MASK (0x7U) #define CAN_CTRL1_PROPSEG_SHIFT (0U) #define CAN_CTRL1_PROPSEG(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PROPSEG_SHIFT)) & CAN_CTRL1_PROPSEG_MASK) #define CAN_CTRL1_LOM_MASK (0x8U) #define CAN_CTRL1_LOM_SHIFT (3U) +/*! LOM + * 0b1..FLEXCAN module operates in Listen Only Mode + * 0b0..Listen Only Mode is deactivated + */ #define CAN_CTRL1_LOM(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LOM_SHIFT)) & CAN_CTRL1_LOM_MASK) #define CAN_CTRL1_LBUF_MASK (0x10U) #define CAN_CTRL1_LBUF_SHIFT (4U) +/*! LBUF + * 0b1..Lowest number buffer is transmitted first + * 0b0..Buffer with highest priority is transmitted first + */ #define CAN_CTRL1_LBUF(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LBUF_SHIFT)) & CAN_CTRL1_LBUF_MASK) #define CAN_CTRL1_TSYN_MASK (0x20U) #define CAN_CTRL1_TSYN_SHIFT (5U) +/*! TSYN + * 0b1..Timer Sync feature enabled + * 0b0..Timer Sync feature disabled + */ #define CAN_CTRL1_TSYN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_TSYN_SHIFT)) & CAN_CTRL1_TSYN_MASK) #define CAN_CTRL1_BOFFREC_MASK (0x40U) #define CAN_CTRL1_BOFFREC_SHIFT (6U) +/*! BOFFREC + * 0b1..Automatic recovering from Bus Off state disabled + * 0b0..Automatic recovering from Bus Off state enabled, according to CAN Spec 2.0 part B + */ #define CAN_CTRL1_BOFFREC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_BOFFREC_SHIFT)) & CAN_CTRL1_BOFFREC_MASK) #define CAN_CTRL1_SMP_MASK (0x80U) #define CAN_CTRL1_SMP_SHIFT (7U) +/*! SMP + * 0b1..Three samples are used to determine the value of the received bit: the regular one (sample point) and 2 preceding samples, a majority rule is used + * 0b0..Just one sample is used to determine the bit value + */ #define CAN_CTRL1_SMP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_SMP_SHIFT)) & CAN_CTRL1_SMP_MASK) #define CAN_CTRL1_RWRNMSK_MASK (0x400U) #define CAN_CTRL1_RWRNMSK_SHIFT (10U) +/*! RWRNMSK + * 0b1..Rx Warning Interrupt enabled + * 0b0..Rx Warning Interrupt disabled + */ #define CAN_CTRL1_RWRNMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_RWRNMSK_SHIFT)) & CAN_CTRL1_RWRNMSK_MASK) #define CAN_CTRL1_TWRNMSK_MASK (0x800U) #define CAN_CTRL1_TWRNMSK_SHIFT (11U) +/*! TWRNMSK + * 0b1..Tx Warning Interrupt enabled + * 0b0..Tx Warning Interrupt disabled + */ #define CAN_CTRL1_TWRNMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_TWRNMSK_SHIFT)) & CAN_CTRL1_TWRNMSK_MASK) #define CAN_CTRL1_LPB_MASK (0x1000U) #define CAN_CTRL1_LPB_SHIFT (12U) +/*! LPB + * 0b1..Loop Back enabled + * 0b0..Loop Back disabled + */ #define CAN_CTRL1_LPB(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LPB_SHIFT)) & CAN_CTRL1_LPB_MASK) #define CAN_CTRL1_ERRMSK_MASK (0x4000U) #define CAN_CTRL1_ERRMSK_SHIFT (14U) +/*! ERRMSK + * 0b1..Error interrupt enabled + * 0b0..Error interrupt disabled + */ #define CAN_CTRL1_ERRMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_ERRMSK_SHIFT)) & CAN_CTRL1_ERRMSK_MASK) #define CAN_CTRL1_BOFFMSK_MASK (0x8000U) #define CAN_CTRL1_BOFFMSK_SHIFT (15U) +/*! BOFFMSK + * 0b1..Bus Off interrupt enabled + * 0b0..Bus Off interrupt disabled + */ #define CAN_CTRL1_BOFFMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_BOFFMSK_SHIFT)) & CAN_CTRL1_BOFFMSK_MASK) #define CAN_CTRL1_PSEG2_MASK (0x70000U) #define CAN_CTRL1_PSEG2_SHIFT (16U) @@ -2598,132 +3374,283 @@ typedef struct { #define CAN_CTRL1_PRESDIV_MASK (0xFF000000U) #define CAN_CTRL1_PRESDIV_SHIFT (24U) #define CAN_CTRL1_PRESDIV(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PRESDIV_SHIFT)) & CAN_CTRL1_PRESDIV_MASK) +/*! @} */ /*! @name TIMER - Free Running Timer Register */ +/*! @{ */ #define CAN_TIMER_TIMER_MASK (0xFFFFU) #define CAN_TIMER_TIMER_SHIFT (0U) #define CAN_TIMER_TIMER(x) (((uint32_t)(((uint32_t)(x)) << CAN_TIMER_TIMER_SHIFT)) & CAN_TIMER_TIMER_MASK) +/*! @} */ /*! @name RXMGMASK - Rx Mailboxes Global Mask Register */ +/*! @{ */ #define CAN_RXMGMASK_MG_MASK (0xFFFFFFFFU) #define CAN_RXMGMASK_MG_SHIFT (0U) +/*! MG + * 0b00000000000000000000000000000001..The corresponding bit in the filter is checked against the one received + * 0b00000000000000000000000000000000..the corresponding bit in the filter is "don't care" + */ #define CAN_RXMGMASK_MG(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXMGMASK_MG_SHIFT)) & CAN_RXMGMASK_MG_MASK) +/*! @} */ /*! @name RX14MASK - Rx Buffer 14 Mask Register */ +/*! @{ */ #define CAN_RX14MASK_RX14M_MASK (0xFFFFFFFFU) #define CAN_RX14MASK_RX14M_SHIFT (0U) +/*! RX14M + * 0b00000000000000000000000000000001..The corresponding bit in the filter is checked + * 0b00000000000000000000000000000000..the corresponding bit in the filter is "don't care" + */ #define CAN_RX14MASK_RX14M(x) (((uint32_t)(((uint32_t)(x)) << CAN_RX14MASK_RX14M_SHIFT)) & CAN_RX14MASK_RX14M_MASK) +/*! @} */ /*! @name RX15MASK - Rx Buffer 15 Mask Register */ +/*! @{ */ #define CAN_RX15MASK_RX15M_MASK (0xFFFFFFFFU) #define CAN_RX15MASK_RX15M_SHIFT (0U) +/*! RX15M + * 0b00000000000000000000000000000001..The corresponding bit in the filter is checked + * 0b00000000000000000000000000000000..the corresponding bit in the filter is "don't care" + */ #define CAN_RX15MASK_RX15M(x) (((uint32_t)(((uint32_t)(x)) << CAN_RX15MASK_RX15M_SHIFT)) & CAN_RX15MASK_RX15M_MASK) +/*! @} */ /*! @name ECR - Error Counter Register */ +/*! @{ */ #define CAN_ECR_TX_ERR_COUNTER_MASK (0xFFU) #define CAN_ECR_TX_ERR_COUNTER_SHIFT (0U) #define CAN_ECR_TX_ERR_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_TX_ERR_COUNTER_SHIFT)) & CAN_ECR_TX_ERR_COUNTER_MASK) #define CAN_ECR_RX_ERR_COUNTER_MASK (0xFF00U) #define CAN_ECR_RX_ERR_COUNTER_SHIFT (8U) #define CAN_ECR_RX_ERR_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_RX_ERR_COUNTER_SHIFT)) & CAN_ECR_RX_ERR_COUNTER_MASK) +/*! @} */ /*! @name ESR1 - Error and Status 1 Register */ +/*! @{ */ #define CAN_ESR1_WAKINT_MASK (0x1U) #define CAN_ESR1_WAKINT_SHIFT (0U) +/*! WAKINT + * 0b1..Indicates a recessive to dominant transition received on the CAN bus when the FLEXCAN module is in Stop Mode + * 0b0..No such occurrence + */ #define CAN_ESR1_WAKINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_WAKINT_SHIFT)) & CAN_ESR1_WAKINT_MASK) #define CAN_ESR1_ERRINT_MASK (0x2U) #define CAN_ESR1_ERRINT_SHIFT (1U) +/*! ERRINT + * 0b1..Indicates setting of any Error Bit in the Error and Status Register + * 0b0..No such occurrence + */ #define CAN_ESR1_ERRINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ERRINT_SHIFT)) & CAN_ESR1_ERRINT_MASK) #define CAN_ESR1_BOFFINT_MASK (0x4U) #define CAN_ESR1_BOFFINT_SHIFT (2U) +/*! BOFFINT + * 0b1..FLEXCAN module entered 'Bus Off' state + * 0b0..No such occurrence + */ #define CAN_ESR1_BOFFINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BOFFINT_SHIFT)) & CAN_ESR1_BOFFINT_MASK) #define CAN_ESR1_RX_MASK (0x8U) #define CAN_ESR1_RX_SHIFT (3U) +/*! RX + * 0b1..FLEXCAN is transmitting a message + * 0b0..FLEXCAN is receiving a message + */ #define CAN_ESR1_RX(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RX_SHIFT)) & CAN_ESR1_RX_MASK) #define CAN_ESR1_FLTCONF_MASK (0x30U) #define CAN_ESR1_FLTCONF_SHIFT (4U) +/*! FLTCONF + * 0b00..Error Active + * 0b01..Error Passive + * 0b1x..Bus off + */ #define CAN_ESR1_FLTCONF(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FLTCONF_SHIFT)) & CAN_ESR1_FLTCONF_MASK) #define CAN_ESR1_TX_MASK (0x40U) #define CAN_ESR1_TX_SHIFT (6U) +/*! TX + * 0b1..FLEXCAN is transmitting a message + * 0b0..FLEXCAN is receiving a message + */ #define CAN_ESR1_TX(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TX_SHIFT)) & CAN_ESR1_TX_MASK) #define CAN_ESR1_IDLE_MASK (0x80U) #define CAN_ESR1_IDLE_SHIFT (7U) +/*! IDLE + * 0b1..CAN bus is now IDLE + * 0b0..No such occurrence + */ #define CAN_ESR1_IDLE(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_IDLE_SHIFT)) & CAN_ESR1_IDLE_MASK) #define CAN_ESR1_RXWRN_MASK (0x100U) #define CAN_ESR1_RXWRN_SHIFT (8U) +/*! RXWRN + * 0b1..Rx_Err_Counter >= 96 + * 0b0..No such occurrence + */ #define CAN_ESR1_RXWRN(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RXWRN_SHIFT)) & CAN_ESR1_RXWRN_MASK) #define CAN_ESR1_TXWRN_MASK (0x200U) #define CAN_ESR1_TXWRN_SHIFT (9U) +/*! TXWRN + * 0b1..TX_Err_Counter >= 96 + * 0b0..No such occurrence + */ #define CAN_ESR1_TXWRN(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TXWRN_SHIFT)) & CAN_ESR1_TXWRN_MASK) #define CAN_ESR1_STFERR_MASK (0x400U) #define CAN_ESR1_STFERR_SHIFT (10U) +/*! STFERR + * 0b1..A Stuffing Error occurred since last read of this register. + * 0b0..No such occurrence. + */ #define CAN_ESR1_STFERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_STFERR_SHIFT)) & CAN_ESR1_STFERR_MASK) #define CAN_ESR1_FRMERR_MASK (0x800U) #define CAN_ESR1_FRMERR_SHIFT (11U) +/*! FRMERR + * 0b1..A Form Error occurred since last read of this register + * 0b0..No such occurrence + */ #define CAN_ESR1_FRMERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FRMERR_SHIFT)) & CAN_ESR1_FRMERR_MASK) #define CAN_ESR1_CRCERR_MASK (0x1000U) #define CAN_ESR1_CRCERR_SHIFT (12U) +/*! CRCERR + * 0b1..A CRC error occurred since last read of this register. + * 0b0..No such occurrence + */ #define CAN_ESR1_CRCERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_CRCERR_SHIFT)) & CAN_ESR1_CRCERR_MASK) #define CAN_ESR1_ACKERR_MASK (0x2000U) #define CAN_ESR1_ACKERR_SHIFT (13U) +/*! ACKERR + * 0b1..An ACK error occurred since last read of this register + * 0b0..No such occurrence + */ #define CAN_ESR1_ACKERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ACKERR_SHIFT)) & CAN_ESR1_ACKERR_MASK) #define CAN_ESR1_BIT0ERR_MASK (0x4000U) #define CAN_ESR1_BIT0ERR_SHIFT (14U) +/*! BIT0ERR + * 0b1..At least one bit sent as dominant is received as recessive + * 0b0..No such occurrence + */ #define CAN_ESR1_BIT0ERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT0ERR_SHIFT)) & CAN_ESR1_BIT0ERR_MASK) #define CAN_ESR1_BIT1ERR_MASK (0x8000U) #define CAN_ESR1_BIT1ERR_SHIFT (15U) +/*! BIT1ERR + * 0b1..At least one bit sent as recessive is received as dominant + * 0b0..No such occurrence + */ #define CAN_ESR1_BIT1ERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT1ERR_SHIFT)) & CAN_ESR1_BIT1ERR_MASK) #define CAN_ESR1_RWRNINT_MASK (0x10000U) #define CAN_ESR1_RWRNINT_SHIFT (16U) +/*! RWRNINT + * 0b1..The Rx error counter transition from < 96 to >= 96 + * 0b0..No such occurrence + */ #define CAN_ESR1_RWRNINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RWRNINT_SHIFT)) & CAN_ESR1_RWRNINT_MASK) #define CAN_ESR1_TWRNINT_MASK (0x20000U) #define CAN_ESR1_TWRNINT_SHIFT (17U) +/*! TWRNINT + * 0b1..The Tx error counter transition from < 96 to >= 96 + * 0b0..No such occurrence + */ #define CAN_ESR1_TWRNINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TWRNINT_SHIFT)) & CAN_ESR1_TWRNINT_MASK) #define CAN_ESR1_SYNCH_MASK (0x40000U) #define CAN_ESR1_SYNCH_SHIFT (18U) +/*! SYNCH + * 0b1..FlexCAN is synchronized to the CAN bus + * 0b0..FlexCAN is not synchronized to the CAN bus + */ #define CAN_ESR1_SYNCH(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_SYNCH_SHIFT)) & CAN_ESR1_SYNCH_MASK) +/*! @} */ /*! @name IMASK2 - Interrupt Masks 2 Register */ +/*! @{ */ #define CAN_IMASK2_BUFHM_MASK (0xFFFFFFFFU) #define CAN_IMASK2_BUFHM_SHIFT (0U) +/*! BUFHM + * 0b00000000000000000000000000000001..The corresponding buffer Interrupt is enabled + * 0b00000000000000000000000000000000..The corresponding buffer Interrupt is disabled + */ #define CAN_IMASK2_BUFHM(x) (((uint32_t)(((uint32_t)(x)) << CAN_IMASK2_BUFHM_SHIFT)) & CAN_IMASK2_BUFHM_MASK) +/*! @} */ /*! @name IMASK1 - Interrupt Masks 1 Register */ +/*! @{ */ #define CAN_IMASK1_BUFLM_MASK (0xFFFFFFFFU) #define CAN_IMASK1_BUFLM_SHIFT (0U) +/*! BUFLM + * 0b00000000000000000000000000000001..The corresponding buffer Interrupt is enabled + * 0b00000000000000000000000000000000..The corresponding buffer Interrupt is disabled + */ #define CAN_IMASK1_BUFLM(x) (((uint32_t)(((uint32_t)(x)) << CAN_IMASK1_BUFLM_SHIFT)) & CAN_IMASK1_BUFLM_MASK) +/*! @} */ /*! @name IFLAG2 - Interrupt Flags 2 Register */ +/*! @{ */ #define CAN_IFLAG2_BUFHI_MASK (0xFFFFFFFFU) #define CAN_IFLAG2_BUFHI_SHIFT (0U) +/*! BUFHI + * 0b00000000000000000000000000000001..The corresponding buffer has successfully completed transmission or reception + * 0b00000000000000000000000000000000..No such occurrence + */ #define CAN_IFLAG2_BUFHI(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG2_BUFHI_SHIFT)) & CAN_IFLAG2_BUFHI_MASK) +/*! @} */ /*! @name IFLAG1 - Interrupt Flags 1 Register */ +/*! @{ */ #define CAN_IFLAG1_BUF4TO0I_MASK (0x1FU) #define CAN_IFLAG1_BUF4TO0I_SHIFT (0U) +/*! BUF4TO0I + * 0b00001..Corresponding MB completed transmission/reception + * 0b00000..No such occurrence + */ #define CAN_IFLAG1_BUF4TO0I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF4TO0I_SHIFT)) & CAN_IFLAG1_BUF4TO0I_MASK) #define CAN_IFLAG1_BUF5I_MASK (0x20U) #define CAN_IFLAG1_BUF5I_SHIFT (5U) +/*! BUF5I + * 0b1..MB5 completed transmission/reception or frames available in the FIFO + * 0b0..No such occurrence + */ #define CAN_IFLAG1_BUF5I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF5I_SHIFT)) & CAN_IFLAG1_BUF5I_MASK) #define CAN_IFLAG1_BUF6I_MASK (0x40U) #define CAN_IFLAG1_BUF6I_SHIFT (6U) +/*! BUF6I + * 0b1..MB6 completed transmission/reception or FIFO almost full + * 0b0..No such occurrence + */ #define CAN_IFLAG1_BUF6I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF6I_SHIFT)) & CAN_IFLAG1_BUF6I_MASK) #define CAN_IFLAG1_BUF7I_MASK (0x80U) #define CAN_IFLAG1_BUF7I_SHIFT (7U) +/*! BUF7I + * 0b1..MB7 completed transmission/reception or FIFO overflow + * 0b0..No such occurrence + */ #define CAN_IFLAG1_BUF7I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF7I_SHIFT)) & CAN_IFLAG1_BUF7I_MASK) #define CAN_IFLAG1_BUF31TO8I_MASK (0xFFFFFF00U) #define CAN_IFLAG1_BUF31TO8I_SHIFT (8U) +/*! BUF31TO8I + * 0b000000000000000000000001..The corresponding MB has successfully completed transmission or reception + * 0b000000000000000000000000..No such occurrence + */ #define CAN_IFLAG1_BUF31TO8I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF31TO8I_SHIFT)) & CAN_IFLAG1_BUF31TO8I_MASK) +/*! @} */ /*! @name CTRL2 - Control 2 Register */ +/*! @{ */ #define CAN_CTRL2_EACEN_MASK (0x10000U) #define CAN_CTRL2_EACEN_SHIFT (16U) +/*! EACEN + * 0b1..Enables the comparison of both Rx Mailbox filter's IDE and RTR bit with their corresponding bits within the incoming frame. Mask bits do apply. + * 0b0..Rx Mailbox filter's IDE bit is always compared and RTR is never compared despite mask bits. + */ #define CAN_CTRL2_EACEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_EACEN_SHIFT)) & CAN_CTRL2_EACEN_MASK) #define CAN_CTRL2_RRS_MASK (0x20000U) #define CAN_CTRL2_RRS_SHIFT (17U) +/*! RRS + * 0b1..Remote Request Frame is stored + * 0b0..Remote Response Frame is generated + */ #define CAN_CTRL2_RRS(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_RRS_SHIFT)) & CAN_CTRL2_RRS_MASK) #define CAN_CTRL2_MRP_MASK (0x40000U) #define CAN_CTRL2_MRP_SHIFT (18U) +/*! MRP + * 0b1..Matching starts from Mailboxes and continues on Rx FIFO + * 0b0..Matching starts from Rx FIFO and continues on Mailboxes + */ #define CAN_CTRL2_MRP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_MRP_SHIFT)) & CAN_CTRL2_MRP_MASK) #define CAN_CTRL2_TASD_MASK (0xF80000U) #define CAN_CTRL2_TASD_SHIFT (19U) @@ -2733,38 +3660,98 @@ typedef struct { #define CAN_CTRL2_RFFN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_RFFN_SHIFT)) & CAN_CTRL2_RFFN_MASK) #define CAN_CTRL2_WRMFRZ_MASK (0x10000000U) #define CAN_CTRL2_WRMFRZ_SHIFT (28U) +/*! WRMFRZ + * 0b1..Enable unrestricted write access to FlexCAN memory + * 0b0..Keep the write access restricted in some regions of FlexCAN memory + */ #define CAN_CTRL2_WRMFRZ(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_WRMFRZ_SHIFT)) & CAN_CTRL2_WRMFRZ_MASK) +/*! @} */ /*! @name ESR2 - Error and Status 2 Register */ +/*! @{ */ #define CAN_ESR2_IMB_MASK (0x2000U) #define CAN_ESR2_IMB_SHIFT (13U) +/*! IMB + * 0b1..If ESR2[VPS] is asserted, there is at least one inactive Mailbox. LPTM content is the number of the first one. + * 0b0..If ESR2[VPS] is asserted, the ESR2[LPTM] is not an inactive Mailbox. + */ #define CAN_ESR2_IMB(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_IMB_SHIFT)) & CAN_ESR2_IMB_MASK) #define CAN_ESR2_VPS_MASK (0x4000U) #define CAN_ESR2_VPS_SHIFT (14U) +/*! VPS + * 0b1..Contents of IMB and LPTM are valid + * 0b0..Contents of IMB and LPTM are invalid + */ #define CAN_ESR2_VPS(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_VPS_SHIFT)) & CAN_ESR2_VPS_MASK) #define CAN_ESR2_LPTM_MASK (0x7F0000U) #define CAN_ESR2_LPTM_SHIFT (16U) #define CAN_ESR2_LPTM(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_LPTM_SHIFT)) & CAN_ESR2_LPTM_MASK) +/*! @} */ /*! @name CRCR - CRC Register */ +/*! @{ */ #define CAN_CRCR_TXCRC_MASK (0x7FFFU) #define CAN_CRCR_TXCRC_SHIFT (0U) #define CAN_CRCR_TXCRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CRCR_TXCRC_SHIFT)) & CAN_CRCR_TXCRC_MASK) #define CAN_CRCR_MBCRC_MASK (0x7F0000U) #define CAN_CRCR_MBCRC_SHIFT (16U) #define CAN_CRCR_MBCRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CRCR_MBCRC_SHIFT)) & CAN_CRCR_MBCRC_MASK) +/*! @} */ /*! @name RXFGMASK - Rx FIFO Global Mask Register */ +/*! @{ */ #define CAN_RXFGMASK_FGM_MASK (0xFFFFFFFFU) #define CAN_RXFGMASK_FGM_SHIFT (0U) +/*! FGM + * 0b00000000000000000000000000000001..The corresponding bit in the filter is checked + * 0b00000000000000000000000000000000..The corresponding bit in the filter is "don't care" + */ #define CAN_RXFGMASK_FGM(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXFGMASK_FGM_SHIFT)) & CAN_RXFGMASK_FGM_MASK) +/*! @} */ /*! @name RXFIR - Rx FIFO Information Register */ +/*! @{ */ #define CAN_RXFIR_IDHIT_MASK (0x1FFU) #define CAN_RXFIR_IDHIT_SHIFT (0U) #define CAN_RXFIR_IDHIT(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXFIR_IDHIT_SHIFT)) & CAN_RXFIR_IDHIT_MASK) +/*! @} */ + +/*! @name DBG1 - Debug 1 register */ +/*! @{ */ +#define CAN_DBG1_CFSM_MASK (0x3FU) +#define CAN_DBG1_CFSM_SHIFT (0U) +#define CAN_DBG1_CFSM(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBG1_CFSM_SHIFT)) & CAN_DBG1_CFSM_MASK) +#define CAN_DBG1_CBN_MASK (0x1F000000U) +#define CAN_DBG1_CBN_SHIFT (24U) +#define CAN_DBG1_CBN(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBG1_CBN_SHIFT)) & CAN_DBG1_CBN_MASK) +/*! @} */ + +/*! @name DBG2 - Debug 2 register */ +/*! @{ */ +#define CAN_DBG2_RMP_MASK (0x7FU) +#define CAN_DBG2_RMP_SHIFT (0U) +#define CAN_DBG2_RMP(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBG2_RMP_SHIFT)) & CAN_DBG2_RMP_MASK) +#define CAN_DBG2_MPP_MASK (0x80U) +#define CAN_DBG2_MPP_SHIFT (7U) +/*! MPP - Matching Process in Progress + * 0b0..No matching process ongoing. + * 0b1..Matching process is in progress. + */ +#define CAN_DBG2_MPP(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBG2_MPP_SHIFT)) & CAN_DBG2_MPP_MASK) +#define CAN_DBG2_TAP_MASK (0x7F00U) +#define CAN_DBG2_TAP_SHIFT (8U) +#define CAN_DBG2_TAP(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBG2_TAP_SHIFT)) & CAN_DBG2_TAP_MASK) +#define CAN_DBG2_APP_MASK (0x8000U) +#define CAN_DBG2_APP_SHIFT (15U) +/*! APP - Arbitration Process in Progress + * 0b0..No matching process ongoing. + * 0b1..Matching process is in progress. + */ +#define CAN_DBG2_APP(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBG2_APP_SHIFT)) & CAN_DBG2_APP_MASK) +/*! @} */ /*! @name CS - Message Buffer 0 CS Register..Message Buffer 63 CS Register */ +/*! @{ */ #define CAN_CS_TIME_STAMP_MASK (0xFFFFU) #define CAN_CS_TIME_STAMP_SHIFT (0U) #define CAN_CS_TIME_STAMP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_TIME_STAMP_SHIFT)) & CAN_CS_TIME_STAMP_MASK) @@ -2783,11 +3770,13 @@ typedef struct { #define CAN_CS_CODE_MASK (0xF000000U) #define CAN_CS_CODE_SHIFT (24U) #define CAN_CS_CODE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_CODE_SHIFT)) & CAN_CS_CODE_MASK) +/*! @} */ /* The count of CAN_CS */ #define CAN_CS_COUNT (64U) /*! @name ID - Message Buffer 0 ID Register..Message Buffer 63 ID Register */ +/*! @{ */ #define CAN_ID_EXT_MASK (0x3FFFFU) #define CAN_ID_EXT_SHIFT (0U) #define CAN_ID_EXT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_EXT_SHIFT)) & CAN_ID_EXT_MASK) @@ -2797,11 +3786,13 @@ typedef struct { #define CAN_ID_PRIO_MASK (0xE0000000U) #define CAN_ID_PRIO_SHIFT (29U) #define CAN_ID_PRIO(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_PRIO_SHIFT)) & CAN_ID_PRIO_MASK) +/*! @} */ /* The count of CAN_ID */ #define CAN_ID_COUNT (64U) /*! @name WORD0 - Message Buffer 0 WORD0 Register..Message Buffer 63 WORD0 Register */ +/*! @{ */ #define CAN_WORD0_DATA_BYTE_3_MASK (0xFFU) #define CAN_WORD0_DATA_BYTE_3_SHIFT (0U) #define CAN_WORD0_DATA_BYTE_3(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_3_SHIFT)) & CAN_WORD0_DATA_BYTE_3_MASK) @@ -2814,11 +3805,13 @@ typedef struct { #define CAN_WORD0_DATA_BYTE_0_MASK (0xFF000000U) #define CAN_WORD0_DATA_BYTE_0_SHIFT (24U) #define CAN_WORD0_DATA_BYTE_0(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_0_SHIFT)) & CAN_WORD0_DATA_BYTE_0_MASK) +/*! @} */ /* The count of CAN_WORD0 */ #define CAN_WORD0_COUNT (64U) /*! @name WORD1 - Message Buffer 0 WORD1 Register..Message Buffer 63 WORD1 Register */ +/*! @{ */ #define CAN_WORD1_DATA_BYTE_7_MASK (0xFFU) #define CAN_WORD1_DATA_BYTE_7_SHIFT (0U) #define CAN_WORD1_DATA_BYTE_7(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_7_SHIFT)) & CAN_WORD1_DATA_BYTE_7_MASK) @@ -2831,22 +3824,31 @@ typedef struct { #define CAN_WORD1_DATA_BYTE_4_MASK (0xFF000000U) #define CAN_WORD1_DATA_BYTE_4_SHIFT (24U) #define CAN_WORD1_DATA_BYTE_4(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_4_SHIFT)) & CAN_WORD1_DATA_BYTE_4_MASK) +/*! @} */ /* The count of CAN_WORD1 */ #define CAN_WORD1_COUNT (64U) /*! @name RXIMR - Rx Individual Mask Registers */ +/*! @{ */ #define CAN_RXIMR_MI_MASK (0xFFFFFFFFU) #define CAN_RXIMR_MI_SHIFT (0U) +/*! MI + * 0b00000000000000000000000000000001..The corresponding bit in the filter is checked + * 0b00000000000000000000000000000000..the corresponding bit in the filter is "don't care" + */ #define CAN_RXIMR_MI(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXIMR_MI_SHIFT)) & CAN_RXIMR_MI_MASK) +/*! @} */ /* The count of CAN_RXIMR */ #define CAN_RXIMR_COUNT (64U) /*! @name GFWR - Glitch Filter Width Registers */ +/*! @{ */ #define CAN_GFWR_GFWR_MASK (0xFFU) #define CAN_GFWR_GFWR_SHIFT (0U) #define CAN_GFWR_GFWR(x) (((uint32_t)(((uint32_t)(x)) << CAN_GFWR_GFWR_SHIFT)) & CAN_GFWR_GFWR_MASK) +/*! @} */ /*! @@ -2944,251 +3946,709 @@ typedef struct { */ /*! @name CCR - CCM Control Register */ +/*! @{ */ #define CCM_CCR_OSCNT_MASK (0xFFU) #define CCM_CCR_OSCNT_SHIFT (0U) +/*! OSCNT + * 0b00000000..count 1 ckil + * 0b11111111..count 256 ckil's + */ #define CCM_CCR_OSCNT(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCR_OSCNT_SHIFT)) & CCM_CCR_OSCNT_MASK) #define CCM_CCR_COSC_EN_MASK (0x1000U) #define CCM_CCR_COSC_EN_SHIFT (12U) +/*! COSC_EN + * 0b0..disable on chip oscillator + * 0b1..enable on chip oscillator + */ #define CCM_CCR_COSC_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCR_COSC_EN_SHIFT)) & CCM_CCR_COSC_EN_MASK) #define CCM_CCR_REG_BYPASS_COUNT_MASK (0x7E00000U) #define CCM_CCR_REG_BYPASS_COUNT_SHIFT (21U) +/*! REG_BYPASS_COUNT + * 0b000000..no delay + * 0b000001..1 CKIL clock period delay + * 0b111111..63 CKIL clock periods delay + */ #define CCM_CCR_REG_BYPASS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCR_REG_BYPASS_COUNT_SHIFT)) & CCM_CCR_REG_BYPASS_COUNT_MASK) #define CCM_CCR_RBC_EN_MASK (0x8000000U) #define CCM_CCR_RBC_EN_SHIFT (27U) +/*! RBC_EN + * 0b1..REG_BYPASS_COUNTER enabled. + * 0b0..REG_BYPASS_COUNTER disabled + */ #define CCM_CCR_RBC_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCR_RBC_EN_SHIFT)) & CCM_CCR_RBC_EN_MASK) +/*! @} */ /*! @name CSR - CCM Status Register */ +/*! @{ */ #define CCM_CSR_REF_EN_B_MASK (0x1U) #define CCM_CSR_REF_EN_B_SHIFT (0U) +/*! REF_EN_B + * 0b0..value of CCM_REF_EN_B is '0' + * 0b1..value of CCM_REF_EN_B is '1' + */ #define CCM_CSR_REF_EN_B(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSR_REF_EN_B_SHIFT)) & CCM_CSR_REF_EN_B_MASK) #define CCM_CSR_CAMP2_READY_MASK (0x8U) #define CCM_CSR_CAMP2_READY_SHIFT (3U) +/*! CAMP2_READY + * 0b0..CAMP2 is not ready. + * 0b1..CAMP2 is ready. + */ #define CCM_CSR_CAMP2_READY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSR_CAMP2_READY_SHIFT)) & CCM_CSR_CAMP2_READY_MASK) #define CCM_CSR_COSC_READY_MASK (0x20U) #define CCM_CSR_COSC_READY_SHIFT (5U) +/*! COSC_READY + * 0b0..on board oscillator is not ready. + * 0b1..on board oscillator is ready. + */ #define CCM_CSR_COSC_READY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSR_COSC_READY_SHIFT)) & CCM_CSR_COSC_READY_MASK) +/*! @} */ /*! @name CCSR - CCM Clock Switcher Register */ +/*! @{ */ #define CCM_CCSR_PLL3_SW_CLK_SEL_MASK (0x1U) #define CCM_CCSR_PLL3_SW_CLK_SEL_SHIFT (0U) +/*! PLL3_SW_CLK_SEL + * 0b0..pll3_main_clk + * 0b1..pll3 bypass clock + */ #define CCM_CCSR_PLL3_SW_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCSR_PLL3_SW_CLK_SEL_SHIFT)) & CCM_CCSR_PLL3_SW_CLK_SEL_MASK) +/*! @} */ /*! @name CACRR - CCM Arm Clock Root Register */ +/*! @{ */ #define CCM_CACRR_ARM_PODF_MASK (0x7U) #define CCM_CACRR_ARM_PODF_SHIFT (0U) +/*! ARM_PODF + * 0b000..divide by 1 + * 0b001..divide by 2 + * 0b010..divide by 3 + * 0b011..divide by 4 + * 0b100..divide by 5 + * 0b101..divide by 6 + * 0b110..divide by 7 + * 0b111..divide by 8 + */ #define CCM_CACRR_ARM_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CACRR_ARM_PODF_SHIFT)) & CCM_CACRR_ARM_PODF_MASK) +/*! @} */ /*! @name CBCDR - CCM Bus Clock Divider Register */ +/*! @{ */ #define CCM_CBCDR_SEMC_CLK_SEL_MASK (0x40U) #define CCM_CBCDR_SEMC_CLK_SEL_SHIFT (6U) +/*! SEMC_CLK_SEL + * 0b0..Periph_clk output will be used as SEMC clock root + * 0b1..SEMC alternative clock will be used as SEMC clock root + */ #define CCM_CBCDR_SEMC_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_SEMC_CLK_SEL_SHIFT)) & CCM_CBCDR_SEMC_CLK_SEL_MASK) #define CCM_CBCDR_SEMC_ALT_CLK_SEL_MASK (0x80U) #define CCM_CBCDR_SEMC_ALT_CLK_SEL_SHIFT (7U) +/*! SEMC_ALT_CLK_SEL + * 0b0..PLL2 PFD2 will be selected as alternative clock for SEMC root clock + * 0b1..PLL3 PFD1 will be selected as alternative clock for SEMC root clock + */ #define CCM_CBCDR_SEMC_ALT_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_SEMC_ALT_CLK_SEL_SHIFT)) & CCM_CBCDR_SEMC_ALT_CLK_SEL_MASK) #define CCM_CBCDR_IPG_PODF_MASK (0x300U) #define CCM_CBCDR_IPG_PODF_SHIFT (8U) +/*! IPG_PODF + * 0b00..divide by 1 + * 0b01..divide by 2 + * 0b10..divide by 3 + * 0b11..divide by 4 + */ #define CCM_CBCDR_IPG_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_IPG_PODF_SHIFT)) & CCM_CBCDR_IPG_PODF_MASK) #define CCM_CBCDR_AHB_PODF_MASK (0x1C00U) #define CCM_CBCDR_AHB_PODF_SHIFT (10U) +/*! AHB_PODF + * 0b000..divide by 1 + * 0b001..divide by 2 + * 0b010..divide by 3 + * 0b011..divide by 4 + * 0b100..divide by 5 + * 0b101..divide by 6 + * 0b110..divide by 7 + * 0b111..divide by 8 + */ #define CCM_CBCDR_AHB_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_AHB_PODF_SHIFT)) & CCM_CBCDR_AHB_PODF_MASK) #define CCM_CBCDR_SEMC_PODF_MASK (0x70000U) #define CCM_CBCDR_SEMC_PODF_SHIFT (16U) +/*! SEMC_PODF + * 0b000..divide by 1 + * 0b001..divide by 2 + * 0b010..divide by 3 + * 0b011..divide by 4 + * 0b100..divide by 5 + * 0b101..divide by 6 + * 0b110..divide by 7 + * 0b111..divide by 8 + */ #define CCM_CBCDR_SEMC_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_SEMC_PODF_SHIFT)) & CCM_CBCDR_SEMC_PODF_MASK) #define CCM_CBCDR_PERIPH_CLK_SEL_MASK (0x2000000U) #define CCM_CBCDR_PERIPH_CLK_SEL_SHIFT (25U) +/*! PERIPH_CLK_SEL + * 0b0..derive clock from pre_periph_clk_sel + * 0b1..derive clock from periph_clk2_clk_divided + */ #define CCM_CBCDR_PERIPH_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_PERIPH_CLK_SEL_SHIFT)) & CCM_CBCDR_PERIPH_CLK_SEL_MASK) #define CCM_CBCDR_PERIPH_CLK2_PODF_MASK (0x38000000U) #define CCM_CBCDR_PERIPH_CLK2_PODF_SHIFT (27U) +/*! PERIPH_CLK2_PODF + * 0b000..divide by 1 + * 0b001..divide by 2 + * 0b010..divide by 3 + * 0b011..divide by 4 + * 0b100..divide by 5 + * 0b101..divide by 6 + * 0b110..divide by 7 + * 0b111..divide by 8 + */ #define CCM_CBCDR_PERIPH_CLK2_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_PERIPH_CLK2_PODF_SHIFT)) & CCM_CBCDR_PERIPH_CLK2_PODF_MASK) +/*! @} */ /*! @name CBCMR - CCM Bus Clock Multiplexer Register */ +/*! @{ */ #define CCM_CBCMR_LPSPI_CLK_SEL_MASK (0x30U) #define CCM_CBCMR_LPSPI_CLK_SEL_SHIFT (4U) +/*! LPSPI_CLK_SEL + * 0b00..derive clock from PLL3 PFD1 clk + * 0b01..derive clock from PLL3 PFD0 + * 0b10..derive clock from PLL2 + * 0b11..derive clock from PLL2 PFD2 + */ #define CCM_CBCMR_LPSPI_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_LPSPI_CLK_SEL_SHIFT)) & CCM_CBCMR_LPSPI_CLK_SEL_MASK) #define CCM_CBCMR_PERIPH_CLK2_SEL_MASK (0x3000U) #define CCM_CBCMR_PERIPH_CLK2_SEL_SHIFT (12U) +/*! PERIPH_CLK2_SEL + * 0b00..derive clock from pll3_sw_clk + * 0b01..derive clock from osc_clk (pll1_ref_clk) + * 0b10..derive clock from pll2_bypass_clk + * 0b11..reserved + */ #define CCM_CBCMR_PERIPH_CLK2_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_PERIPH_CLK2_SEL_SHIFT)) & CCM_CBCMR_PERIPH_CLK2_SEL_MASK) #define CCM_CBCMR_TRACE_CLK_SEL_MASK (0xC000U) #define CCM_CBCMR_TRACE_CLK_SEL_SHIFT (14U) +/*! TRACE_CLK_SEL + * 0b00..derive clock from PLL2 + * 0b01..derive clock from PLL2 PFD2 + * 0b10..derive clock from PLL2 PFD0 + * 0b11..derive clock from PLL2 PFD1 + */ #define CCM_CBCMR_TRACE_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_TRACE_CLK_SEL_SHIFT)) & CCM_CBCMR_TRACE_CLK_SEL_MASK) #define CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK (0xC0000U) #define CCM_CBCMR_PRE_PERIPH_CLK_SEL_SHIFT (18U) +/*! PRE_PERIPH_CLK_SEL + * 0b00..derive clock from PLL2 + * 0b01..derive clock from PLL2 PFD2 + * 0b10..derive clock from PLL2 PFD0 + * 0b11..derive clock from divided PLL1 + */ #define CCM_CBCMR_PRE_PERIPH_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_PRE_PERIPH_CLK_SEL_SHIFT)) & CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK) #define CCM_CBCMR_LCDIF_PODF_MASK (0x3800000U) #define CCM_CBCMR_LCDIF_PODF_SHIFT (23U) +/*! LCDIF_PODF + * 0b000..divide by 1 + * 0b001..divide by 2 + * 0b010..divide by 3 + * 0b011..divide by 4 + * 0b100..divide by 5 + * 0b101..divide by 6 + * 0b110..divide by 7 + * 0b111..divide by 8 + */ #define CCM_CBCMR_LCDIF_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_LCDIF_PODF_SHIFT)) & CCM_CBCMR_LCDIF_PODF_MASK) #define CCM_CBCMR_LPSPI_PODF_MASK (0x1C000000U) #define CCM_CBCMR_LPSPI_PODF_SHIFT (26U) +/*! LPSPI_PODF + * 0b000..divide by 1 + * 0b001..divide by 2 + * 0b010..divide by 3 + * 0b011..divide by 4 + * 0b100..divide by 5 + * 0b101..divide by 6 + * 0b110..divide by 7 + * 0b111..divide by 8 + */ #define CCM_CBCMR_LPSPI_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_LPSPI_PODF_SHIFT)) & CCM_CBCMR_LPSPI_PODF_MASK) +/*! @} */ /*! @name CSCMR1 - CCM Serial Clock Multiplexer Register 1 */ +/*! @{ */ #define CCM_CSCMR1_PERCLK_PODF_MASK (0x3FU) #define CCM_CSCMR1_PERCLK_PODF_SHIFT (0U) +/*! PERCLK_PODF + * 0b000000..divide by 1 + * 0b000001..divide by 2 + * 0b000010..divide by 3 + * 0b000011..divide by 4 + * 0b000100..divide by 5 + * 0b000101..divide by 6 + * 0b000110..divide by 7 + * 0b111111..divide by 64 + */ #define CCM_CSCMR1_PERCLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_PERCLK_PODF_SHIFT)) & CCM_CSCMR1_PERCLK_PODF_MASK) #define CCM_CSCMR1_PERCLK_CLK_SEL_MASK (0x40U) #define CCM_CSCMR1_PERCLK_CLK_SEL_SHIFT (6U) +/*! PERCLK_CLK_SEL + * 0b0..derive clock from ipg clk root + * 0b1..derive clock from osc_clk + */ #define CCM_CSCMR1_PERCLK_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_PERCLK_CLK_SEL_SHIFT)) & CCM_CSCMR1_PERCLK_CLK_SEL_MASK) #define CCM_CSCMR1_SAI1_CLK_SEL_MASK (0xC00U) #define CCM_CSCMR1_SAI1_CLK_SEL_SHIFT (10U) +/*! SAI1_CLK_SEL + * 0b00..derive clock from PLL3 PFD2 + * 0b01..derive clock from PLL5 + * 0b10..derive clock from PLL4 + * 0b11..Reserved + */ #define CCM_CSCMR1_SAI1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_SAI1_CLK_SEL_SHIFT)) & CCM_CSCMR1_SAI1_CLK_SEL_MASK) #define CCM_CSCMR1_SAI2_CLK_SEL_MASK (0x3000U) #define CCM_CSCMR1_SAI2_CLK_SEL_SHIFT (12U) +/*! SAI2_CLK_SEL + * 0b00..derive clock from PLL3 PFD2 + * 0b01..derive clock from PLL5 + * 0b10..derive clock from PLL4 + * 0b11..Reserved + */ #define CCM_CSCMR1_SAI2_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_SAI2_CLK_SEL_SHIFT)) & CCM_CSCMR1_SAI2_CLK_SEL_MASK) #define CCM_CSCMR1_SAI3_CLK_SEL_MASK (0xC000U) #define CCM_CSCMR1_SAI3_CLK_SEL_SHIFT (14U) +/*! SAI3_CLK_SEL + * 0b00..derive clock from PLL3 PFD2 + * 0b01..derive clock from PLL5 + * 0b10..derive clock from PLL4 + * 0b11..Reserved + */ #define CCM_CSCMR1_SAI3_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_SAI3_CLK_SEL_SHIFT)) & CCM_CSCMR1_SAI3_CLK_SEL_MASK) #define CCM_CSCMR1_USDHC1_CLK_SEL_MASK (0x10000U) #define CCM_CSCMR1_USDHC1_CLK_SEL_SHIFT (16U) +/*! USDHC1_CLK_SEL + * 0b0..derive clock from PLL2 PFD2 + * 0b1..derive clock from PLL2 PFD0 + */ #define CCM_CSCMR1_USDHC1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_USDHC1_CLK_SEL_SHIFT)) & CCM_CSCMR1_USDHC1_CLK_SEL_MASK) #define CCM_CSCMR1_USDHC2_CLK_SEL_MASK (0x20000U) #define CCM_CSCMR1_USDHC2_CLK_SEL_SHIFT (17U) +/*! USDHC2_CLK_SEL + * 0b0..derive clock from PLL2 PFD2 + * 0b1..derive clock from PLL2 PFD0 + */ #define CCM_CSCMR1_USDHC2_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_USDHC2_CLK_SEL_SHIFT)) & CCM_CSCMR1_USDHC2_CLK_SEL_MASK) #define CCM_CSCMR1_FLEXSPI_PODF_MASK (0x3800000U) #define CCM_CSCMR1_FLEXSPI_PODF_SHIFT (23U) +/*! FLEXSPI_PODF + * 0b000..divide by 1 + * 0b001..divide by 2 + * 0b010..divide by 3 + * 0b011..divide by 4 + * 0b100..divide by 5 + * 0b101..divide by 6 + * 0b110..divide by 7 + * 0b111..divide by 8 + */ #define CCM_CSCMR1_FLEXSPI_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_FLEXSPI_PODF_SHIFT)) & CCM_CSCMR1_FLEXSPI_PODF_MASK) #define CCM_CSCMR1_FLEXSPI_CLK_SEL_MASK (0x60000000U) #define CCM_CSCMR1_FLEXSPI_CLK_SEL_SHIFT (29U) +/*! FLEXSPI_CLK_SEL + * 0b00..derive clock from semc_clk_root_pre + * 0b01..derive clock from pll3_sw_clk + * 0b10..derive clock from PLL2 PFD2 + * 0b11..derive clock from PLL3 PFD0 + */ #define CCM_CSCMR1_FLEXSPI_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_FLEXSPI_CLK_SEL_SHIFT)) & CCM_CSCMR1_FLEXSPI_CLK_SEL_MASK) +/*! @} */ /*! @name CSCMR2 - CCM Serial Clock Multiplexer Register 2 */ +/*! @{ */ #define CCM_CSCMR2_CAN_CLK_PODF_MASK (0xFCU) #define CCM_CSCMR2_CAN_CLK_PODF_SHIFT (2U) +/*! CAN_CLK_PODF + * 0b000000..divide by 1 + * 0b000111..divide by 8 + * 0b111111..divide by 2^6 + */ #define CCM_CSCMR2_CAN_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR2_CAN_CLK_PODF_SHIFT)) & CCM_CSCMR2_CAN_CLK_PODF_MASK) #define CCM_CSCMR2_CAN_CLK_SEL_MASK (0x300U) #define CCM_CSCMR2_CAN_CLK_SEL_SHIFT (8U) +/*! CAN_CLK_SEL + * 0b00..derive clock from pll3_sw_clk divided clock (60M) + * 0b01..derive clock from osc_clk (24M) + * 0b10..derive clock from pll3_sw_clk divided clock (80M) + * 0b11..Disable FlexCAN clock + */ #define CCM_CSCMR2_CAN_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR2_CAN_CLK_SEL_SHIFT)) & CCM_CSCMR2_CAN_CLK_SEL_MASK) #define CCM_CSCMR2_FLEXIO2_CLK_SEL_MASK (0x180000U) #define CCM_CSCMR2_FLEXIO2_CLK_SEL_SHIFT (19U) +/*! FLEXIO2_CLK_SEL + * 0b00..derive clock from PLL4 divided clock + * 0b01..derive clock from PLL3 PFD2 clock + * 0b10..derive clock from PLL5 clock + * 0b11..derive clock from pll3_sw_clk + */ #define CCM_CSCMR2_FLEXIO2_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR2_FLEXIO2_CLK_SEL_SHIFT)) & CCM_CSCMR2_FLEXIO2_CLK_SEL_MASK) +/*! @} */ /*! @name CSCDR1 - CCM Serial Clock Divider Register 1 */ +/*! @{ */ #define CCM_CSCDR1_UART_CLK_PODF_MASK (0x3FU) #define CCM_CSCDR1_UART_CLK_PODF_SHIFT (0U) +/*! UART_CLK_PODF + * 0b000000..divide by 1 + * 0b111111..divide by 2^6 + */ #define CCM_CSCDR1_UART_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR1_UART_CLK_PODF_SHIFT)) & CCM_CSCDR1_UART_CLK_PODF_MASK) #define CCM_CSCDR1_UART_CLK_SEL_MASK (0x40U) #define CCM_CSCDR1_UART_CLK_SEL_SHIFT (6U) +/*! UART_CLK_SEL + * 0b0..derive clock from pll3_80m + * 0b1..derive clock from osc_clk + */ #define CCM_CSCDR1_UART_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR1_UART_CLK_SEL_SHIFT)) & CCM_CSCDR1_UART_CLK_SEL_MASK) #define CCM_CSCDR1_USDHC1_PODF_MASK (0x3800U) #define CCM_CSCDR1_USDHC1_PODF_SHIFT (11U) +/*! USDHC1_PODF + * 0b000..divide by 1 + * 0b001..divide by 2 + * 0b010..divide by 3 + * 0b011..divide by 4 + * 0b100..divide by 5 + * 0b101..divide by 6 + * 0b110..divide by 7 + * 0b111..divide by 8 + */ #define CCM_CSCDR1_USDHC1_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR1_USDHC1_PODF_SHIFT)) & CCM_CSCDR1_USDHC1_PODF_MASK) #define CCM_CSCDR1_USDHC2_PODF_MASK (0x70000U) #define CCM_CSCDR1_USDHC2_PODF_SHIFT (16U) +/*! USDHC2_PODF + * 0b000..divide by 1 + * 0b001..divide by 2 + * 0b010..divide by 3 + * 0b011..divide by 4 + * 0b100..divide by 5 + * 0b101..divide by 6 + * 0b110..divide by 7 + * 0b111..divide by 8 + */ #define CCM_CSCDR1_USDHC2_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR1_USDHC2_PODF_SHIFT)) & CCM_CSCDR1_USDHC2_PODF_MASK) -#define CCM_CSCDR1_TRACE_PODF_MASK (0xE000000U) +#define CCM_CSCDR1_TRACE_PODF_MASK (0x6000000U) #define CCM_CSCDR1_TRACE_PODF_SHIFT (25U) +/*! TRACE_PODF + * 0b00..divide by 1 + * 0b01..divide by 2 + * 0b10..divide by 3 + * 0b11..divide by 4 + */ #define CCM_CSCDR1_TRACE_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR1_TRACE_PODF_SHIFT)) & CCM_CSCDR1_TRACE_PODF_MASK) +/*! @} */ /*! @name CS1CDR - CCM Clock Divider Register */ +/*! @{ */ #define CCM_CS1CDR_SAI1_CLK_PODF_MASK (0x3FU) #define CCM_CS1CDR_SAI1_CLK_PODF_SHIFT (0U) +/*! SAI1_CLK_PODF + * 0b000000..divide by 1 + * 0b111111..divide by 2^6 + */ #define CCM_CS1CDR_SAI1_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_SAI1_CLK_PODF_SHIFT)) & CCM_CS1CDR_SAI1_CLK_PODF_MASK) #define CCM_CS1CDR_SAI1_CLK_PRED_MASK (0x1C0U) #define CCM_CS1CDR_SAI1_CLK_PRED_SHIFT (6U) +/*! SAI1_CLK_PRED + * 0b000..divide by 1 + * 0b001..divide by 2 + * 0b010..divide by 3 + * 0b011..divide by 4 + * 0b100..divide by 5 + * 0b101..divide by 6 + * 0b110..divide by 7 + * 0b111..divide by 8 + */ #define CCM_CS1CDR_SAI1_CLK_PRED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_SAI1_CLK_PRED_SHIFT)) & CCM_CS1CDR_SAI1_CLK_PRED_MASK) #define CCM_CS1CDR_FLEXIO2_CLK_PRED_MASK (0xE00U) #define CCM_CS1CDR_FLEXIO2_CLK_PRED_SHIFT (9U) +/*! FLEXIO2_CLK_PRED + * 0b000..divide by 1 + * 0b001..divide by 2 + * 0b010..divide by 3 + * 0b011..divide by 4 + * 0b100..divide by 5 + * 0b101..divide by 6 + * 0b110..divide by 7 + * 0b111..divide by 8 + */ #define CCM_CS1CDR_FLEXIO2_CLK_PRED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_FLEXIO2_CLK_PRED_SHIFT)) & CCM_CS1CDR_FLEXIO2_CLK_PRED_MASK) #define CCM_CS1CDR_SAI3_CLK_PODF_MASK (0x3F0000U) #define CCM_CS1CDR_SAI3_CLK_PODF_SHIFT (16U) +/*! SAI3_CLK_PODF + * 0b000000..divide by 1 + * 0b111111..divide by 2^6 + */ #define CCM_CS1CDR_SAI3_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_SAI3_CLK_PODF_SHIFT)) & CCM_CS1CDR_SAI3_CLK_PODF_MASK) #define CCM_CS1CDR_SAI3_CLK_PRED_MASK (0x1C00000U) #define CCM_CS1CDR_SAI3_CLK_PRED_SHIFT (22U) +/*! SAI3_CLK_PRED + * 0b000..divide by 1 + * 0b001..divide by 2 + * 0b010..divide by 3 + * 0b011..divide by 4 + * 0b100..divide by 5 + * 0b101..divide by 6 + * 0b110..divide by 7 + * 0b111..divide by 8 + */ #define CCM_CS1CDR_SAI3_CLK_PRED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_SAI3_CLK_PRED_SHIFT)) & CCM_CS1CDR_SAI3_CLK_PRED_MASK) #define CCM_CS1CDR_FLEXIO2_CLK_PODF_MASK (0xE000000U) #define CCM_CS1CDR_FLEXIO2_CLK_PODF_SHIFT (25U) +/*! FLEXIO2_CLK_PODF + * 0b000..divide by 1 + * 0b001..divide by 2 + * 0b010..divide by 3 + * 0b011..divide by 4 + * 0b100..divide by 5 + * 0b101..divide by 6 + * 0b110..divide by 7 + * 0b111..divide by 8 + */ #define CCM_CS1CDR_FLEXIO2_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_FLEXIO2_CLK_PODF_SHIFT)) & CCM_CS1CDR_FLEXIO2_CLK_PODF_MASK) +/*! @} */ /*! @name CS2CDR - CCM Clock Divider Register */ +/*! @{ */ #define CCM_CS2CDR_SAI2_CLK_PODF_MASK (0x3FU) #define CCM_CS2CDR_SAI2_CLK_PODF_SHIFT (0U) +/*! SAI2_CLK_PODF + * 0b000000..divide by 1 + * 0b111111..divide by 2^6 + */ #define CCM_CS2CDR_SAI2_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS2CDR_SAI2_CLK_PODF_SHIFT)) & CCM_CS2CDR_SAI2_CLK_PODF_MASK) #define CCM_CS2CDR_SAI2_CLK_PRED_MASK (0x1C0U) #define CCM_CS2CDR_SAI2_CLK_PRED_SHIFT (6U) +/*! SAI2_CLK_PRED + * 0b000..divide by 1 + * 0b001..divide by 2 + * 0b010..divide by 3 + * 0b011..divide by 4 + * 0b100..divide by 5 + * 0b101..divide by 6 + * 0b110..divide by 7 + * 0b111..divide by 8 + */ #define CCM_CS2CDR_SAI2_CLK_PRED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS2CDR_SAI2_CLK_PRED_SHIFT)) & CCM_CS2CDR_SAI2_CLK_PRED_MASK) +/*! @} */ /*! @name CDCDR - CCM D1 Clock Divider Register */ +/*! @{ */ #define CCM_CDCDR_FLEXIO1_CLK_SEL_MASK (0x180U) #define CCM_CDCDR_FLEXIO1_CLK_SEL_SHIFT (7U) +/*! FLEXIO1_CLK_SEL + * 0b00..derive clock from PLL4 + * 0b01..derive clock from PLL3 PFD2 + * 0b10..derive clock from PLL5 + * 0b11..derive clock from pll3_sw_clk + */ #define CCM_CDCDR_FLEXIO1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDCDR_FLEXIO1_CLK_SEL_SHIFT)) & CCM_CDCDR_FLEXIO1_CLK_SEL_MASK) #define CCM_CDCDR_FLEXIO1_CLK_PODF_MASK (0xE00U) #define CCM_CDCDR_FLEXIO1_CLK_PODF_SHIFT (9U) +/*! FLEXIO1_CLK_PODF + * 0b000..divide by 1 + * 0b111..divide by 8 + */ #define CCM_CDCDR_FLEXIO1_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDCDR_FLEXIO1_CLK_PODF_SHIFT)) & CCM_CDCDR_FLEXIO1_CLK_PODF_MASK) #define CCM_CDCDR_FLEXIO1_CLK_PRED_MASK (0x7000U) #define CCM_CDCDR_FLEXIO1_CLK_PRED_SHIFT (12U) +/*! FLEXIO1_CLK_PRED + * 0b000..divide by 1 (do not use with high input frequencies) + * 0b001..divide by 2 + * 0b010..divide by 3 + * 0b111..divide by 8 + */ #define CCM_CDCDR_FLEXIO1_CLK_PRED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDCDR_FLEXIO1_CLK_PRED_SHIFT)) & CCM_CDCDR_FLEXIO1_CLK_PRED_MASK) #define CCM_CDCDR_SPDIF0_CLK_SEL_MASK (0x300000U) #define CCM_CDCDR_SPDIF0_CLK_SEL_SHIFT (20U) +/*! SPDIF0_CLK_SEL + * 0b00..derive clock from PLL4 + * 0b01..derive clock from PLL3 PFD2 + * 0b10..derive clock from PLL5 + * 0b11..derive clock from pll3_sw_clk + */ #define CCM_CDCDR_SPDIF0_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDCDR_SPDIF0_CLK_SEL_SHIFT)) & CCM_CDCDR_SPDIF0_CLK_SEL_MASK) #define CCM_CDCDR_SPDIF0_CLK_PODF_MASK (0x1C00000U) #define CCM_CDCDR_SPDIF0_CLK_PODF_SHIFT (22U) +/*! SPDIF0_CLK_PODF + * 0b000..divide by 1 + * 0b111..divide by 8 + */ #define CCM_CDCDR_SPDIF0_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDCDR_SPDIF0_CLK_PODF_SHIFT)) & CCM_CDCDR_SPDIF0_CLK_PODF_MASK) #define CCM_CDCDR_SPDIF0_CLK_PRED_MASK (0xE000000U) #define CCM_CDCDR_SPDIF0_CLK_PRED_SHIFT (25U) +/*! SPDIF0_CLK_PRED + * 0b000..divide by 1 (do not use with high input frequencies) + * 0b001..divide by 2 + * 0b010..divide by 3 + * 0b111..divide by 8 + */ #define CCM_CDCDR_SPDIF0_CLK_PRED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDCDR_SPDIF0_CLK_PRED_SHIFT)) & CCM_CDCDR_SPDIF0_CLK_PRED_MASK) +/*! @} */ /*! @name CSCDR2 - CCM Serial Clock Divider Register 2 */ -#define CCM_CSCDR2_LCDIF_CLK_SEL_MASK (0xE00U) -#define CCM_CSCDR2_LCDIF_CLK_SEL_SHIFT (9U) -#define CCM_CSCDR2_LCDIF_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR2_LCDIF_CLK_SEL_SHIFT)) & CCM_CSCDR2_LCDIF_CLK_SEL_MASK) +/*! @{ */ #define CCM_CSCDR2_LCDIF_PRED_MASK (0x7000U) #define CCM_CSCDR2_LCDIF_PRED_SHIFT (12U) +/*! LCDIF_PRED + * 0b000..divide by 1 + * 0b001..divide by 2 + * 0b010..divide by 3 + * 0b011..divide by 4 + * 0b100..divide by 5 + * 0b101..divide by 6 + * 0b110..divide by 7 + * 0b111..divide by 8 + */ #define CCM_CSCDR2_LCDIF_PRED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR2_LCDIF_PRED_SHIFT)) & CCM_CSCDR2_LCDIF_PRED_MASK) #define CCM_CSCDR2_LCDIF_PRE_CLK_SEL_MASK (0x38000U) #define CCM_CSCDR2_LCDIF_PRE_CLK_SEL_SHIFT (15U) +/*! LCDIF_PRE_CLK_SEL + * 0b000..derive clock from PLL2 + * 0b001..derive clock from PLL3 PFD3 + * 0b010..derive clock from PLL5 + * 0b011..derive clock from PLL2 PFD0 + * 0b100..derive clock from PLL2 PFD1 + * 0b101..derive clock from PLL3 PFD1 + */ #define CCM_CSCDR2_LCDIF_PRE_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR2_LCDIF_PRE_CLK_SEL_SHIFT)) & CCM_CSCDR2_LCDIF_PRE_CLK_SEL_MASK) #define CCM_CSCDR2_LPI2C_CLK_SEL_MASK (0x40000U) #define CCM_CSCDR2_LPI2C_CLK_SEL_SHIFT (18U) +/*! LPI2C_CLK_SEL + * 0b0..derive clock from pll3_60m + * 0b1..derive clock from osc_clk + */ #define CCM_CSCDR2_LPI2C_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR2_LPI2C_CLK_SEL_SHIFT)) & CCM_CSCDR2_LPI2C_CLK_SEL_MASK) #define CCM_CSCDR2_LPI2C_CLK_PODF_MASK (0x1F80000U) #define CCM_CSCDR2_LPI2C_CLK_PODF_SHIFT (19U) +/*! LPI2C_CLK_PODF + * 0b000000..divide by 1 + * 0b111111..divide by 2^6 + */ #define CCM_CSCDR2_LPI2C_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR2_LPI2C_CLK_PODF_SHIFT)) & CCM_CSCDR2_LPI2C_CLK_PODF_MASK) +/*! @} */ /*! @name CSCDR3 - CCM Serial Clock Divider Register 3 */ +/*! @{ */ #define CCM_CSCDR3_CSI_CLK_SEL_MASK (0x600U) #define CCM_CSCDR3_CSI_CLK_SEL_SHIFT (9U) +/*! CSI_CLK_SEL + * 0b00..derive clock from osc_clk (24M) + * 0b01..derive clock from PLL2 PFD2 + * 0b10..derive clock from pll3_120M + * 0b11..derive clock from PLL3 PFD1 + */ #define CCM_CSCDR3_CSI_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR3_CSI_CLK_SEL_SHIFT)) & CCM_CSCDR3_CSI_CLK_SEL_MASK) #define CCM_CSCDR3_CSI_PODF_MASK (0x3800U) #define CCM_CSCDR3_CSI_PODF_SHIFT (11U) +/*! CSI_PODF + * 0b000..divide by 1 + * 0b001..divide by 2 + * 0b010..divide by 3 + * 0b011..divide by 4 + * 0b100..divide by 5 + * 0b101..divide by 6 + * 0b110..divide by 7 + * 0b111..divide by 8 + */ #define CCM_CSCDR3_CSI_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR3_CSI_PODF_SHIFT)) & CCM_CSCDR3_CSI_PODF_MASK) +/*! @} */ /*! @name CDHIPR - CCM Divider Handshake In-Process Register */ +/*! @{ */ #define CCM_CDHIPR_SEMC_PODF_BUSY_MASK (0x1U) #define CCM_CDHIPR_SEMC_PODF_BUSY_SHIFT (0U) +/*! SEMC_PODF_BUSY + * 0b0..divider is not busy and its value represents the actual division. + * 0b1..divider is busy with handshake process with module. The value read in the divider represents the previous value of the division factor, and after the handshake the written value of the semc_podf will be applied. + */ #define CCM_CDHIPR_SEMC_PODF_BUSY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDHIPR_SEMC_PODF_BUSY_SHIFT)) & CCM_CDHIPR_SEMC_PODF_BUSY_MASK) #define CCM_CDHIPR_AHB_PODF_BUSY_MASK (0x2U) #define CCM_CDHIPR_AHB_PODF_BUSY_SHIFT (1U) +/*! AHB_PODF_BUSY + * 0b0..divider is not busy and its value represents the actual division. + * 0b1..divider is busy with handshake process with module. The value read in the divider represents the previous value of the division factor, and after the handshake the written value of the ahb_podf will be applied. + */ #define CCM_CDHIPR_AHB_PODF_BUSY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDHIPR_AHB_PODF_BUSY_SHIFT)) & CCM_CDHIPR_AHB_PODF_BUSY_MASK) #define CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY_MASK (0x8U) #define CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY_SHIFT (3U) +/*! PERIPH2_CLK_SEL_BUSY + * 0b0..mux is not busy and its value represents the actual division. + * 0b1..mux is busy with handshake process with module. The value read in the periph2_clk_sel represents the previous value of select, and after the handshake periph2_clk_sel value will be applied. + */ #define CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY_SHIFT)) & CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY_MASK) #define CCM_CDHIPR_PERIPH_CLK_SEL_BUSY_MASK (0x20U) #define CCM_CDHIPR_PERIPH_CLK_SEL_BUSY_SHIFT (5U) +/*! PERIPH_CLK_SEL_BUSY + * 0b0..mux is not busy and its value represents the actual division. + * 0b1..mux is busy with handshake process with module. The value read in the periph_clk_sel represents the previous value of select, and after the handshake periph_clk_sel value will be applied. + */ #define CCM_CDHIPR_PERIPH_CLK_SEL_BUSY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDHIPR_PERIPH_CLK_SEL_BUSY_SHIFT)) & CCM_CDHIPR_PERIPH_CLK_SEL_BUSY_MASK) #define CCM_CDHIPR_ARM_PODF_BUSY_MASK (0x10000U) #define CCM_CDHIPR_ARM_PODF_BUSY_SHIFT (16U) +/*! ARM_PODF_BUSY + * 0b0..divider is not busy and its value represents the actual division. + * 0b1..divider is busy with handshake process with module. The value read in the divider represents the previous value of the division factor, and after the handshake the written value of the arm_podf will be applied. + */ #define CCM_CDHIPR_ARM_PODF_BUSY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDHIPR_ARM_PODF_BUSY_SHIFT)) & CCM_CDHIPR_ARM_PODF_BUSY_MASK) +/*! @} */ /*! @name CLPCR - CCM Low Power Control Register */ +/*! @{ */ #define CCM_CLPCR_LPM_MASK (0x3U) #define CCM_CLPCR_LPM_SHIFT (0U) +/*! LPM + * 0b00..Remain in run mode + * 0b01..Transfer to wait mode + * 0b10..Transfer to stop mode + * 0b11..Reserved + */ #define CCM_CLPCR_LPM(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_LPM_SHIFT)) & CCM_CLPCR_LPM_MASK) #define CCM_CLPCR_ARM_CLK_DIS_ON_LPM_MASK (0x20U) #define CCM_CLPCR_ARM_CLK_DIS_ON_LPM_SHIFT (5U) +/*! ARM_CLK_DIS_ON_LPM + * 0b0..ARM clock enabled on wait mode. + * 0b1..ARM clock disabled on wait mode. . + */ #define CCM_CLPCR_ARM_CLK_DIS_ON_LPM(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_ARM_CLK_DIS_ON_LPM_SHIFT)) & CCM_CLPCR_ARM_CLK_DIS_ON_LPM_MASK) #define CCM_CLPCR_SBYOS_MASK (0x40U) #define CCM_CLPCR_SBYOS_SHIFT (6U) +/*! SBYOS + * 0b0..On-chip oscillator will not be powered down, after next entrance to STOP mode. (CCM_REF_EN_B will remain asserted - '0' and cosc_pwrdown will remain de asserted - '0') + * 0b1..On-chip oscillator will be powered down, after next entrance to STOP mode. (CCM_REF_EN_B will be deasserted - '1' and cosc_pwrdown will be asserted - '1'). When returning from STOP mode, external oscillator will be enabled again, on-chip oscillator will return to oscillator mode, and after oscnt count, CCM will continue with the exit from the STOP mode process. + */ #define CCM_CLPCR_SBYOS(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_SBYOS_SHIFT)) & CCM_CLPCR_SBYOS_MASK) #define CCM_CLPCR_DIS_REF_OSC_MASK (0x80U) #define CCM_CLPCR_DIS_REF_OSC_SHIFT (7U) +/*! DIS_REF_OSC + * 0b0..external high frequency oscillator will be enabled, i.e. CCM_REF_EN_B = '0'. + * 0b1..external high frequency oscillator will be disabled, i.e. CCM_REF_EN_B = '1' + */ #define CCM_CLPCR_DIS_REF_OSC(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_DIS_REF_OSC_SHIFT)) & CCM_CLPCR_DIS_REF_OSC_MASK) #define CCM_CLPCR_VSTBY_MASK (0x100U) #define CCM_CLPCR_VSTBY_SHIFT (8U) +/*! VSTBY + * 0b0..Voltage will not be changed to standby voltage after next entrance to STOP mode. ( PMIC_STBY_REQ will remain negated - '0') + * 0b1..Voltage will be requested to change to standby voltage after next entrance to stop mode. ( PMIC_STBY_REQ will be asserted - '1'). + */ #define CCM_CLPCR_VSTBY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_VSTBY_SHIFT)) & CCM_CLPCR_VSTBY_MASK) #define CCM_CLPCR_STBY_COUNT_MASK (0x600U) #define CCM_CLPCR_STBY_COUNT_SHIFT (9U) +/*! STBY_COUNT + * 0b00..CCM will wait (1*pmic_delay_scaler)+1 ckil clock cycles + * 0b01..CCM will wait (3*pmic_delay_scaler)+1 ckil clock cycles + * 0b10..CCM will wait (7*pmic_delay_scaler)+1 ckil clock cycles + * 0b11..CCM will wait (15*pmic_delay_scaler)+1 ckil clock cycles + */ #define CCM_CLPCR_STBY_COUNT(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_STBY_COUNT_SHIFT)) & CCM_CLPCR_STBY_COUNT_MASK) #define CCM_CLPCR_COSC_PWRDOWN_MASK (0x800U) #define CCM_CLPCR_COSC_PWRDOWN_SHIFT (11U) +/*! COSC_PWRDOWN + * 0b0..On chip oscillator will not be powered down, i.e. cosc_pwrdown = '0'. + * 0b1..On chip oscillator will be powered down, i.e. cosc_pwrdown = '1'. + */ #define CCM_CLPCR_COSC_PWRDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_COSC_PWRDOWN_SHIFT)) & CCM_CLPCR_COSC_PWRDOWN_MASK) #define CCM_CLPCR_BYPASS_LPM_HS1_MASK (0x80000U) #define CCM_CLPCR_BYPASS_LPM_HS1_SHIFT (19U) @@ -3198,101 +4658,261 @@ typedef struct { #define CCM_CLPCR_BYPASS_LPM_HS0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_BYPASS_LPM_HS0_SHIFT)) & CCM_CLPCR_BYPASS_LPM_HS0_MASK) #define CCM_CLPCR_MASK_CORE0_WFI_MASK (0x400000U) #define CCM_CLPCR_MASK_CORE0_WFI_SHIFT (22U) +/*! MASK_CORE0_WFI + * 0b0..WFI of core0 is not masked + * 0b1..WFI of core0 is masked + */ #define CCM_CLPCR_MASK_CORE0_WFI(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_MASK_CORE0_WFI_SHIFT)) & CCM_CLPCR_MASK_CORE0_WFI_MASK) #define CCM_CLPCR_MASK_SCU_IDLE_MASK (0x4000000U) #define CCM_CLPCR_MASK_SCU_IDLE_SHIFT (26U) +/*! MASK_SCU_IDLE + * 0b1..SCU IDLE is masked + * 0b0..SCU IDLE is not masked + */ #define CCM_CLPCR_MASK_SCU_IDLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_MASK_SCU_IDLE_SHIFT)) & CCM_CLPCR_MASK_SCU_IDLE_MASK) #define CCM_CLPCR_MASK_L2CC_IDLE_MASK (0x8000000U) #define CCM_CLPCR_MASK_L2CC_IDLE_SHIFT (27U) +/*! MASK_L2CC_IDLE + * 0b1..L2CC IDLE is masked + * 0b0..L2CC IDLE is not masked + */ #define CCM_CLPCR_MASK_L2CC_IDLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_MASK_L2CC_IDLE_SHIFT)) & CCM_CLPCR_MASK_L2CC_IDLE_MASK) +/*! @} */ /*! @name CISR - CCM Interrupt Status Register */ +/*! @{ */ #define CCM_CISR_LRF_PLL_MASK (0x1U) #define CCM_CISR_LRF_PLL_SHIFT (0U) +/*! LRF_PLL + * 0b0..interrupt is not generated due to lock ready of all enabled and not bypaseed PLLs + * 0b1..interrupt generated due to lock ready of all enabled and not bypaseed PLLs + */ #define CCM_CISR_LRF_PLL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_LRF_PLL_SHIFT)) & CCM_CISR_LRF_PLL_MASK) #define CCM_CISR_COSC_READY_MASK (0x40U) #define CCM_CISR_COSC_READY_SHIFT (6U) +/*! COSC_READY + * 0b0..interrupt is not generated due to on board oscillator ready + * 0b1..interrupt generated due to on board oscillator ready + */ #define CCM_CISR_COSC_READY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_COSC_READY_SHIFT)) & CCM_CISR_COSC_READY_MASK) #define CCM_CISR_SEMC_PODF_LOADED_MASK (0x20000U) #define CCM_CISR_SEMC_PODF_LOADED_SHIFT (17U) +/*! SEMC_PODF_LOADED + * 0b0..interrupt is not generated due to frequency change of semc_podf + * 0b1..interrupt generated due to frequency change of semc_podf + */ #define CCM_CISR_SEMC_PODF_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_SEMC_PODF_LOADED_SHIFT)) & CCM_CISR_SEMC_PODF_LOADED_MASK) #define CCM_CISR_PERIPH2_CLK_SEL_LOADED_MASK (0x80000U) #define CCM_CISR_PERIPH2_CLK_SEL_LOADED_SHIFT (19U) +/*! PERIPH2_CLK_SEL_LOADED + * 0b0..interrupt is not generated due to frequency change of periph2_clk_sel + * 0b1..interrupt generated due to frequency change of periph2_clk_sel + */ #define CCM_CISR_PERIPH2_CLK_SEL_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_PERIPH2_CLK_SEL_LOADED_SHIFT)) & CCM_CISR_PERIPH2_CLK_SEL_LOADED_MASK) #define CCM_CISR_AHB_PODF_LOADED_MASK (0x100000U) #define CCM_CISR_AHB_PODF_LOADED_SHIFT (20U) +/*! AHB_PODF_LOADED + * 0b0..interrupt is not generated due to frequency change of ahb_podf + * 0b1..interrupt generated due to frequency change of ahb_podf + */ #define CCM_CISR_AHB_PODF_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_AHB_PODF_LOADED_SHIFT)) & CCM_CISR_AHB_PODF_LOADED_MASK) #define CCM_CISR_PERIPH_CLK_SEL_LOADED_MASK (0x400000U) #define CCM_CISR_PERIPH_CLK_SEL_LOADED_SHIFT (22U) +/*! PERIPH_CLK_SEL_LOADED + * 0b0..interrupt is not generated due to update of periph_clk_sel. + * 0b1..interrupt generated due to update of periph_clk_sel. + */ #define CCM_CISR_PERIPH_CLK_SEL_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_PERIPH_CLK_SEL_LOADED_SHIFT)) & CCM_CISR_PERIPH_CLK_SEL_LOADED_MASK) #define CCM_CISR_ARM_PODF_LOADED_MASK (0x4000000U) #define CCM_CISR_ARM_PODF_LOADED_SHIFT (26U) +/*! ARM_PODF_LOADED + * 0b0..interrupt is not generated due to frequency change of arm_podf + * 0b1..interrupt generated due to frequency change of arm_podf + */ #define CCM_CISR_ARM_PODF_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_ARM_PODF_LOADED_SHIFT)) & CCM_CISR_ARM_PODF_LOADED_MASK) +/*! @} */ /*! @name CIMR - CCM Interrupt Mask Register */ +/*! @{ */ #define CCM_CIMR_MASK_LRF_PLL_MASK (0x1U) #define CCM_CIMR_MASK_LRF_PLL_SHIFT (0U) +/*! MASK_LRF_PLL + * 0b0..don't mask interrupt due to lrf of PLLs - interrupt will be created + * 0b1..mask interrupt due to lrf of PLLs + */ #define CCM_CIMR_MASK_LRF_PLL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_MASK_LRF_PLL_SHIFT)) & CCM_CIMR_MASK_LRF_PLL_MASK) #define CCM_CIMR_MASK_COSC_READY_MASK (0x40U) #define CCM_CIMR_MASK_COSC_READY_SHIFT (6U) +/*! MASK_COSC_READY + * 0b0..don't mask interrupt due to on board oscillator ready - interrupt will be created + * 0b1..mask interrupt due to on board oscillator ready + */ #define CCM_CIMR_MASK_COSC_READY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_MASK_COSC_READY_SHIFT)) & CCM_CIMR_MASK_COSC_READY_MASK) #define CCM_CIMR_MASK_SEMC_PODF_LOADED_MASK (0x20000U) #define CCM_CIMR_MASK_SEMC_PODF_LOADED_SHIFT (17U) +/*! MASK_SEMC_PODF_LOADED + * 0b0..don't mask interrupt due to frequency change of semc_podf - interrupt will be created + * 0b1..mask interrupt due to frequency change of semc_podf + */ #define CCM_CIMR_MASK_SEMC_PODF_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_MASK_SEMC_PODF_LOADED_SHIFT)) & CCM_CIMR_MASK_SEMC_PODF_LOADED_MASK) #define CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED_MASK (0x80000U) #define CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED_SHIFT (19U) +/*! MASK_PERIPH2_CLK_SEL_LOADED + * 0b0..don't mask interrupt due to update of periph2_clk_sel - interrupt will be created + * 0b1..mask interrupt due to update of periph2_clk_sel + */ #define CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED_SHIFT)) & CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED_MASK) #define CCM_CIMR_MASK_AHB_PODF_LOADED_MASK (0x100000U) #define CCM_CIMR_MASK_AHB_PODF_LOADED_SHIFT (20U) +/*! MASK_AHB_PODF_LOADED + * 0b0..don't mask interrupt due to frequency change of ahb_podf - interrupt will be created + * 0b1..mask interrupt due to frequency change of ahb_podf + */ #define CCM_CIMR_MASK_AHB_PODF_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_MASK_AHB_PODF_LOADED_SHIFT)) & CCM_CIMR_MASK_AHB_PODF_LOADED_MASK) #define CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED_MASK (0x400000U) #define CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED_SHIFT (22U) +/*! MASK_PERIPH_CLK_SEL_LOADED + * 0b0..don't mask interrupt due to update of periph_clk_sel - interrupt will be created + * 0b1..mask interrupt due to update of periph_clk_sel + */ #define CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED_SHIFT)) & CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED_MASK) #define CCM_CIMR_ARM_PODF_LOADED_MASK (0x4000000U) #define CCM_CIMR_ARM_PODF_LOADED_SHIFT (26U) +/*! ARM_PODF_LOADED + * 0b0..don't mask interrupt due to frequency change of arm_podf - interrupt will be created + * 0b1..mask interrupt due to frequency change of arm_podf + */ #define CCM_CIMR_ARM_PODF_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_ARM_PODF_LOADED_SHIFT)) & CCM_CIMR_ARM_PODF_LOADED_MASK) +/*! @} */ /*! @name CCOSR - CCM Clock Output Source Register */ +/*! @{ */ #define CCM_CCOSR_CLKO1_SEL_MASK (0xFU) #define CCM_CCOSR_CLKO1_SEL_SHIFT (0U) +/*! CLKO1_SEL + * 0b0000..USB1 PLL clock (divided by 2) + * 0b0001..SYS PLL clock (divided by 2) + * 0b0011..VIDEO PLL clock (divided by 2) + * 0b0101..semc_clk_root + * 0b0110..Reserved + * 0b1010..lcdif_pix_clk_root + * 0b1011..ahb_clk_root + * 0b1100..ipg_clk_root + * 0b1101..perclk_root + * 0b1110..ckil_sync_clk_root + * 0b1111..pll4_main_clk + */ #define CCM_CCOSR_CLKO1_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLKO1_SEL_SHIFT)) & CCM_CCOSR_CLKO1_SEL_MASK) #define CCM_CCOSR_CLKO1_DIV_MASK (0x70U) #define CCM_CCOSR_CLKO1_DIV_SHIFT (4U) +/*! CLKO1_DIV + * 0b000..divide by 1 + * 0b001..divide by 2 + * 0b010..divide by 3 + * 0b011..divide by 4 + * 0b100..divide by 5 + * 0b101..divide by 6 + * 0b110..divide by 7 + * 0b111..divide by 8 + */ #define CCM_CCOSR_CLKO1_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLKO1_DIV_SHIFT)) & CCM_CCOSR_CLKO1_DIV_MASK) #define CCM_CCOSR_CLKO1_EN_MASK (0x80U) #define CCM_CCOSR_CLKO1_EN_SHIFT (7U) +/*! CLKO1_EN + * 0b0..CCM_CLKO1 disabled. + * 0b1..CCM_CLKO1 enabled. + */ #define CCM_CCOSR_CLKO1_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLKO1_EN_SHIFT)) & CCM_CCOSR_CLKO1_EN_MASK) #define CCM_CCOSR_CLK_OUT_SEL_MASK (0x100U) #define CCM_CCOSR_CLK_OUT_SEL_SHIFT (8U) +/*! CLK_OUT_SEL + * 0b0..CCM_CLKO1 output drives CCM_CLKO1 clock + * 0b1..CCM_CLKO1 output drives CCM_CLKO2 clock + */ #define CCM_CCOSR_CLK_OUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLK_OUT_SEL_SHIFT)) & CCM_CCOSR_CLK_OUT_SEL_MASK) #define CCM_CCOSR_CLKO2_SEL_MASK (0x1F0000U) #define CCM_CCOSR_CLKO2_SEL_SHIFT (16U) +/*! CLKO2_SEL + * 0b00011..usdhc1_clk_root + * 0b00101..wrck_clk_root + * 0b00110..lpi2c_clk_root + * 0b01011..csi_clk_root + * 0b01110..osc_clk + * 0b10001..usdhc2_clk_root + * 0b10010..sai1_clk_root + * 0b10011..sai2_clk_root + * 0b10100..sai3_clk_root + * 0b10111..can_clk_root + * 0b11011..flexspi_clk_root + * 0b11100..uart_clk_root + * 0b11101..spdif0_clk_root + * 0b11111..Reserved + */ #define CCM_CCOSR_CLKO2_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLKO2_SEL_SHIFT)) & CCM_CCOSR_CLKO2_SEL_MASK) #define CCM_CCOSR_CLKO2_DIV_MASK (0xE00000U) #define CCM_CCOSR_CLKO2_DIV_SHIFT (21U) +/*! CLKO2_DIV + * 0b000..divide by 1 + * 0b001..divide by 2 + * 0b010..divide by 3 + * 0b011..divide by 4 + * 0b100..divide by 5 + * 0b101..divide by 6 + * 0b110..divide by 7 + * 0b111..divide by 8 + */ #define CCM_CCOSR_CLKO2_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLKO2_DIV_SHIFT)) & CCM_CCOSR_CLKO2_DIV_MASK) #define CCM_CCOSR_CLKO2_EN_MASK (0x1000000U) #define CCM_CCOSR_CLKO2_EN_SHIFT (24U) +/*! CLKO2_EN + * 0b0..CCM_CLKO2 disabled. + * 0b1..CCM_CLKO2 enabled. + */ #define CCM_CCOSR_CLKO2_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLKO2_EN_SHIFT)) & CCM_CCOSR_CLKO2_EN_MASK) +/*! @} */ /*! @name CGPR - CCM General Purpose Register */ +/*! @{ */ #define CCM_CGPR_PMIC_DELAY_SCALER_MASK (0x1U) #define CCM_CGPR_PMIC_DELAY_SCALER_SHIFT (0U) +/*! PMIC_DELAY_SCALER + * 0b0..clock is not divided + * 0b1..clock is divided /8 + */ #define CCM_CGPR_PMIC_DELAY_SCALER(x) (((uint32_t)(((uint32_t)(x)) << CCM_CGPR_PMIC_DELAY_SCALER_SHIFT)) & CCM_CGPR_PMIC_DELAY_SCALER_MASK) #define CCM_CGPR_EFUSE_PROG_SUPPLY_GATE_MASK (0x10U) #define CCM_CGPR_EFUSE_PROG_SUPPLY_GATE_SHIFT (4U) +/*! EFUSE_PROG_SUPPLY_GATE + * 0b0..fuse programing supply voltage is gated off to the efuse module + * 0b1..allow fuse programing. + */ #define CCM_CGPR_EFUSE_PROG_SUPPLY_GATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CGPR_EFUSE_PROG_SUPPLY_GATE_SHIFT)) & CCM_CGPR_EFUSE_PROG_SUPPLY_GATE_MASK) #define CCM_CGPR_SYS_MEM_DS_CTRL_MASK (0xC000U) #define CCM_CGPR_SYS_MEM_DS_CTRL_SHIFT (14U) +/*! SYS_MEM_DS_CTRL + * 0b00..Disable memory DS mode always + * 0b01..Enable memory (outside ARM platform) DS mode when system STOP and PLL are disabled + * 0b1x..enable memory (outside ARM platform) DS mode when system is in STOP mode + */ #define CCM_CGPR_SYS_MEM_DS_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CGPR_SYS_MEM_DS_CTRL_SHIFT)) & CCM_CGPR_SYS_MEM_DS_CTRL_MASK) #define CCM_CGPR_FPL_MASK (0x10000U) #define CCM_CGPR_FPL_SHIFT (16U) +/*! FPL - Fast PLL enable. + * 0b0..Engage PLL enable default way. + * 0b1..Engage PLL enable 3 CKIL clocks earlier at exiting low power mode (STOP). Should be used only if 24MHz OSC was active in low power mode. + */ #define CCM_CGPR_FPL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CGPR_FPL_SHIFT)) & CCM_CGPR_FPL_MASK) #define CCM_CGPR_INT_MEM_CLK_LPM_MASK (0x20000U) #define CCM_CGPR_INT_MEM_CLK_LPM_SHIFT (17U) +/*! INT_MEM_CLK_LPM + * 0b0..Disable the clock to the ARM platform memories when entering Low Power Mode + * 0b1..Keep the clocks to the ARM platform memories enabled only if an interrupt is pending when entering Low Power Modes (WAIT and STOP without power gating) + */ #define CCM_CGPR_INT_MEM_CLK_LPM(x) (((uint32_t)(((uint32_t)(x)) << CCM_CGPR_INT_MEM_CLK_LPM_SHIFT)) & CCM_CGPR_INT_MEM_CLK_LPM_MASK) +/*! @} */ /*! @name CCGR0 - CCM Clock Gating Register 0 */ +/*! @{ */ #define CCM_CCGR0_CG0_MASK (0x3U) #define CCM_CCGR0_CG0_SHIFT (0U) #define CCM_CCGR0_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG0_SHIFT)) & CCM_CCGR0_CG0_MASK) @@ -3341,8 +4961,10 @@ typedef struct { #define CCM_CCGR0_CG15_MASK (0xC0000000U) #define CCM_CCGR0_CG15_SHIFT (30U) #define CCM_CCGR0_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG15_SHIFT)) & CCM_CCGR0_CG15_MASK) +/*! @} */ /*! @name CCGR1 - CCM Clock Gating Register 1 */ +/*! @{ */ #define CCM_CCGR1_CG0_MASK (0x3U) #define CCM_CCGR1_CG0_SHIFT (0U) #define CCM_CCGR1_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG0_SHIFT)) & CCM_CCGR1_CG0_MASK) @@ -3391,8 +5013,10 @@ typedef struct { #define CCM_CCGR1_CG15_MASK (0xC0000000U) #define CCM_CCGR1_CG15_SHIFT (30U) #define CCM_CCGR1_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG15_SHIFT)) & CCM_CCGR1_CG15_MASK) +/*! @} */ /*! @name CCGR2 - CCM Clock Gating Register 2 */ +/*! @{ */ #define CCM_CCGR2_CG0_MASK (0x3U) #define CCM_CCGR2_CG0_SHIFT (0U) #define CCM_CCGR2_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG0_SHIFT)) & CCM_CCGR2_CG0_MASK) @@ -3441,8 +5065,10 @@ typedef struct { #define CCM_CCGR2_CG15_MASK (0xC0000000U) #define CCM_CCGR2_CG15_SHIFT (30U) #define CCM_CCGR2_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG15_SHIFT)) & CCM_CCGR2_CG15_MASK) +/*! @} */ /*! @name CCGR3 - CCM Clock Gating Register 3 */ +/*! @{ */ #define CCM_CCGR3_CG0_MASK (0x3U) #define CCM_CCGR3_CG0_SHIFT (0U) #define CCM_CCGR3_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG0_SHIFT)) & CCM_CCGR3_CG0_MASK) @@ -3491,8 +5117,10 @@ typedef struct { #define CCM_CCGR3_CG15_MASK (0xC0000000U) #define CCM_CCGR3_CG15_SHIFT (30U) #define CCM_CCGR3_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG15_SHIFT)) & CCM_CCGR3_CG15_MASK) +/*! @} */ /*! @name CCGR4 - CCM Clock Gating Register 4 */ +/*! @{ */ #define CCM_CCGR4_CG0_MASK (0x3U) #define CCM_CCGR4_CG0_SHIFT (0U) #define CCM_CCGR4_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG0_SHIFT)) & CCM_CCGR4_CG0_MASK) @@ -3541,8 +5169,10 @@ typedef struct { #define CCM_CCGR4_CG15_MASK (0xC0000000U) #define CCM_CCGR4_CG15_SHIFT (30U) #define CCM_CCGR4_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG15_SHIFT)) & CCM_CCGR4_CG15_MASK) +/*! @} */ /*! @name CCGR5 - CCM Clock Gating Register 5 */ +/*! @{ */ #define CCM_CCGR5_CG0_MASK (0x3U) #define CCM_CCGR5_CG0_SHIFT (0U) #define CCM_CCGR5_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG0_SHIFT)) & CCM_CCGR5_CG0_MASK) @@ -3591,8 +5221,10 @@ typedef struct { #define CCM_CCGR5_CG15_MASK (0xC0000000U) #define CCM_CCGR5_CG15_SHIFT (30U) #define CCM_CCGR5_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG15_SHIFT)) & CCM_CCGR5_CG15_MASK) +/*! @} */ /*! @name CCGR6 - CCM Clock Gating Register 6 */ +/*! @{ */ #define CCM_CCGR6_CG0_MASK (0x3U) #define CCM_CCGR6_CG0_SHIFT (0U) #define CCM_CCGR6_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG0_SHIFT)) & CCM_CCGR6_CG0_MASK) @@ -3641,26 +5273,53 @@ typedef struct { #define CCM_CCGR6_CG15_MASK (0xC0000000U) #define CCM_CCGR6_CG15_SHIFT (30U) #define CCM_CCGR6_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG15_SHIFT)) & CCM_CCGR6_CG15_MASK) +/*! @} */ /*! @name CMEOR - CCM Module Enable Overide Register */ +/*! @{ */ #define CCM_CMEOR_MOD_EN_OV_GPT_MASK (0x20U) #define CCM_CMEOR_MOD_EN_OV_GPT_SHIFT (5U) +/*! MOD_EN_OV_GPT + * 0b0..don't override module enable signal + * 0b1..override module enable signal + */ #define CCM_CMEOR_MOD_EN_OV_GPT(x) (((uint32_t)(((uint32_t)(x)) << CCM_CMEOR_MOD_EN_OV_GPT_SHIFT)) & CCM_CMEOR_MOD_EN_OV_GPT_MASK) #define CCM_CMEOR_MOD_EN_OV_PIT_MASK (0x40U) #define CCM_CMEOR_MOD_EN_OV_PIT_SHIFT (6U) +/*! MOD_EN_OV_PIT + * 0b0..don't override module enable signal + * 0b1..override module enable signal + */ #define CCM_CMEOR_MOD_EN_OV_PIT(x) (((uint32_t)(((uint32_t)(x)) << CCM_CMEOR_MOD_EN_OV_PIT_SHIFT)) & CCM_CMEOR_MOD_EN_OV_PIT_MASK) #define CCM_CMEOR_MOD_EN_USDHC_MASK (0x80U) #define CCM_CMEOR_MOD_EN_USDHC_SHIFT (7U) +/*! MOD_EN_USDHC + * 0b0..don't override module enable signal + * 0b1..override module enable signal + */ #define CCM_CMEOR_MOD_EN_USDHC(x) (((uint32_t)(((uint32_t)(x)) << CCM_CMEOR_MOD_EN_USDHC_SHIFT)) & CCM_CMEOR_MOD_EN_USDHC_MASK) #define CCM_CMEOR_MOD_EN_OV_TRNG_MASK (0x200U) #define CCM_CMEOR_MOD_EN_OV_TRNG_SHIFT (9U) +/*! MOD_EN_OV_TRNG + * 0b0..don't override module enable signal + * 0b1..override module enable signal + */ #define CCM_CMEOR_MOD_EN_OV_TRNG(x) (((uint32_t)(((uint32_t)(x)) << CCM_CMEOR_MOD_EN_OV_TRNG_SHIFT)) & CCM_CMEOR_MOD_EN_OV_TRNG_MASK) #define CCM_CMEOR_MOD_EN_OV_CAN2_CPI_MASK (0x10000000U) #define CCM_CMEOR_MOD_EN_OV_CAN2_CPI_SHIFT (28U) +/*! MOD_EN_OV_CAN2_CPI + * 0b0..don't override module enable signal + * 0b1..override module enable signal + */ #define CCM_CMEOR_MOD_EN_OV_CAN2_CPI(x) (((uint32_t)(((uint32_t)(x)) << CCM_CMEOR_MOD_EN_OV_CAN2_CPI_SHIFT)) & CCM_CMEOR_MOD_EN_OV_CAN2_CPI_MASK) #define CCM_CMEOR_MOD_EN_OV_CAN1_CPI_MASK (0x40000000U) #define CCM_CMEOR_MOD_EN_OV_CAN1_CPI_SHIFT (30U) +/*! MOD_EN_OV_CAN1_CPI + * 0b0..don't overide module enable signal + * 0b1..overide module enable signal + */ #define CCM_CMEOR_MOD_EN_OV_CAN1_CPI(x) (((uint32_t)(((uint32_t)(x)) << CCM_CMEOR_MOD_EN_OV_CAN1_CPI_SHIFT)) & CCM_CMEOR_MOD_EN_OV_CAN1_CPI_MASK) +/*! @} */ /*! @@ -3771,6 +5430,7 @@ typedef struct { */ /*! @name PLL_ARM - Analog ARM PLL control Register */ +/*! @{ */ #define CCM_ANALOG_PLL_ARM_DIV_SELECT_MASK (0x7FU) #define CCM_ANALOG_PLL_ARM_DIV_SELECT_SHIFT (0U) #define CCM_ANALOG_PLL_ARM_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ARM_DIV_SELECT_MASK) @@ -3782,6 +5442,12 @@ typedef struct { #define CCM_ANALOG_PLL_ARM_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_ENABLE_SHIFT)) & CCM_ANALOG_PLL_ARM_ENABLE_MASK) #define CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_MASK (0xC000U) #define CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_SHIFT (14U) +/*! BYPASS_CLK_SRC + * 0b00..Select the 24MHz oscillator as source. + * 0b01..Select the CLK1_N / CLK1_P as source. + * 0b10..Reserved1 + * 0b11..Reserved2 + */ #define CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_MASK) #define CCM_ANALOG_PLL_ARM_BYPASS_MASK (0x10000U) #define CCM_ANALOG_PLL_ARM_BYPASS_SHIFT (16U) @@ -3792,8 +5458,10 @@ typedef struct { #define CCM_ANALOG_PLL_ARM_LOCK_MASK (0x80000000U) #define CCM_ANALOG_PLL_ARM_LOCK_SHIFT (31U) #define CCM_ANALOG_PLL_ARM_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_LOCK_SHIFT)) & CCM_ANALOG_PLL_ARM_LOCK_MASK) +/*! @} */ /*! @name PLL_ARM_SET - Analog ARM PLL control Register */ +/*! @{ */ #define CCM_ANALOG_PLL_ARM_SET_DIV_SELECT_MASK (0x7FU) #define CCM_ANALOG_PLL_ARM_SET_DIV_SELECT_SHIFT (0U) #define CCM_ANALOG_PLL_ARM_SET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_SET_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ARM_SET_DIV_SELECT_MASK) @@ -3805,6 +5473,12 @@ typedef struct { #define CCM_ANALOG_PLL_ARM_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_SET_ENABLE_SHIFT)) & CCM_ANALOG_PLL_ARM_SET_ENABLE_MASK) #define CCM_ANALOG_PLL_ARM_SET_BYPASS_CLK_SRC_MASK (0xC000U) #define CCM_ANALOG_PLL_ARM_SET_BYPASS_CLK_SRC_SHIFT (14U) +/*! BYPASS_CLK_SRC + * 0b00..Select the 24MHz oscillator as source. + * 0b01..Select the CLK1_N / CLK1_P as source. + * 0b10..Reserved1 + * 0b11..Reserved2 + */ #define CCM_ANALOG_PLL_ARM_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_SET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ARM_SET_BYPASS_CLK_SRC_MASK) #define CCM_ANALOG_PLL_ARM_SET_BYPASS_MASK (0x10000U) #define CCM_ANALOG_PLL_ARM_SET_BYPASS_SHIFT (16U) @@ -3815,8 +5489,10 @@ typedef struct { #define CCM_ANALOG_PLL_ARM_SET_LOCK_MASK (0x80000000U) #define CCM_ANALOG_PLL_ARM_SET_LOCK_SHIFT (31U) #define CCM_ANALOG_PLL_ARM_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_SET_LOCK_SHIFT)) & CCM_ANALOG_PLL_ARM_SET_LOCK_MASK) +/*! @} */ /*! @name PLL_ARM_CLR - Analog ARM PLL control Register */ +/*! @{ */ #define CCM_ANALOG_PLL_ARM_CLR_DIV_SELECT_MASK (0x7FU) #define CCM_ANALOG_PLL_ARM_CLR_DIV_SELECT_SHIFT (0U) #define CCM_ANALOG_PLL_ARM_CLR_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_CLR_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ARM_CLR_DIV_SELECT_MASK) @@ -3828,6 +5504,12 @@ typedef struct { #define CCM_ANALOG_PLL_ARM_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_CLR_ENABLE_SHIFT)) & CCM_ANALOG_PLL_ARM_CLR_ENABLE_MASK) #define CCM_ANALOG_PLL_ARM_CLR_BYPASS_CLK_SRC_MASK (0xC000U) #define CCM_ANALOG_PLL_ARM_CLR_BYPASS_CLK_SRC_SHIFT (14U) +/*! BYPASS_CLK_SRC + * 0b00..Select the 24MHz oscillator as source. + * 0b01..Select the CLK1_N / CLK1_P as source. + * 0b10..Reserved1 + * 0b11..Reserved2 + */ #define CCM_ANALOG_PLL_ARM_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_CLR_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ARM_CLR_BYPASS_CLK_SRC_MASK) #define CCM_ANALOG_PLL_ARM_CLR_BYPASS_MASK (0x10000U) #define CCM_ANALOG_PLL_ARM_CLR_BYPASS_SHIFT (16U) @@ -3838,8 +5520,10 @@ typedef struct { #define CCM_ANALOG_PLL_ARM_CLR_LOCK_MASK (0x80000000U) #define CCM_ANALOG_PLL_ARM_CLR_LOCK_SHIFT (31U) #define CCM_ANALOG_PLL_ARM_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_CLR_LOCK_SHIFT)) & CCM_ANALOG_PLL_ARM_CLR_LOCK_MASK) +/*! @} */ /*! @name PLL_ARM_TOG - Analog ARM PLL control Register */ +/*! @{ */ #define CCM_ANALOG_PLL_ARM_TOG_DIV_SELECT_MASK (0x7FU) #define CCM_ANALOG_PLL_ARM_TOG_DIV_SELECT_SHIFT (0U) #define CCM_ANALOG_PLL_ARM_TOG_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_TOG_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ARM_TOG_DIV_SELECT_MASK) @@ -3851,6 +5535,12 @@ typedef struct { #define CCM_ANALOG_PLL_ARM_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_TOG_ENABLE_SHIFT)) & CCM_ANALOG_PLL_ARM_TOG_ENABLE_MASK) #define CCM_ANALOG_PLL_ARM_TOG_BYPASS_CLK_SRC_MASK (0xC000U) #define CCM_ANALOG_PLL_ARM_TOG_BYPASS_CLK_SRC_SHIFT (14U) +/*! BYPASS_CLK_SRC + * 0b00..Select the 24MHz oscillator as source. + * 0b01..Select the CLK1_N / CLK1_P as source. + * 0b10..Reserved1 + * 0b11..Reserved2 + */ #define CCM_ANALOG_PLL_ARM_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_TOG_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ARM_TOG_BYPASS_CLK_SRC_MASK) #define CCM_ANALOG_PLL_ARM_TOG_BYPASS_MASK (0x10000U) #define CCM_ANALOG_PLL_ARM_TOG_BYPASS_SHIFT (16U) @@ -3861,13 +5551,19 @@ typedef struct { #define CCM_ANALOG_PLL_ARM_TOG_LOCK_MASK (0x80000000U) #define CCM_ANALOG_PLL_ARM_TOG_LOCK_SHIFT (31U) #define CCM_ANALOG_PLL_ARM_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_TOG_LOCK_SHIFT)) & CCM_ANALOG_PLL_ARM_TOG_LOCK_MASK) +/*! @} */ /*! @name PLL_USB1 - Analog USB1 480MHz PLL Control Register */ -#define CCM_ANALOG_PLL_USB1_DIV_SELECT_MASK (0x3U) -#define CCM_ANALOG_PLL_USB1_DIV_SELECT_SHIFT (0U) +/*! @{ */ +#define CCM_ANALOG_PLL_USB1_DIV_SELECT_MASK (0x2U) +#define CCM_ANALOG_PLL_USB1_DIV_SELECT_SHIFT (1U) #define CCM_ANALOG_PLL_USB1_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB1_DIV_SELECT_MASK) #define CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK (0x40U) #define CCM_ANALOG_PLL_USB1_EN_USB_CLKS_SHIFT (6U) +/*! EN_USB_CLKS + * 0b0..PLL outputs for USBPHYn off. + * 0b1..PLL outputs for USBPHYn on. + */ #define CCM_ANALOG_PLL_USB1_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_EN_USB_CLKS_SHIFT)) & CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK) #define CCM_ANALOG_PLL_USB1_POWER_MASK (0x1000U) #define CCM_ANALOG_PLL_USB1_POWER_SHIFT (12U) @@ -3877,6 +5573,10 @@ typedef struct { #define CCM_ANALOG_PLL_USB1_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB1_ENABLE_MASK) #define CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_MASK (0xC000U) #define CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_SHIFT (14U) +/*! BYPASS_CLK_SRC + * 0b00..Select the 24MHz oscillator as source. + * 0b01..Select the CLK1_N / CLK1_P as source. + */ #define CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_MASK) #define CCM_ANALOG_PLL_USB1_BYPASS_MASK (0x10000U) #define CCM_ANALOG_PLL_USB1_BYPASS_SHIFT (16U) @@ -3884,13 +5584,19 @@ typedef struct { #define CCM_ANALOG_PLL_USB1_LOCK_MASK (0x80000000U) #define CCM_ANALOG_PLL_USB1_LOCK_SHIFT (31U) #define CCM_ANALOG_PLL_USB1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB1_LOCK_MASK) +/*! @} */ /*! @name PLL_USB1_SET - Analog USB1 480MHz PLL Control Register */ -#define CCM_ANALOG_PLL_USB1_SET_DIV_SELECT_MASK (0x3U) -#define CCM_ANALOG_PLL_USB1_SET_DIV_SELECT_SHIFT (0U) +/*! @{ */ +#define CCM_ANALOG_PLL_USB1_SET_DIV_SELECT_MASK (0x2U) +#define CCM_ANALOG_PLL_USB1_SET_DIV_SELECT_SHIFT (1U) #define CCM_ANALOG_PLL_USB1_SET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_DIV_SELECT_MASK) #define CCM_ANALOG_PLL_USB1_SET_EN_USB_CLKS_MASK (0x40U) #define CCM_ANALOG_PLL_USB1_SET_EN_USB_CLKS_SHIFT (6U) +/*! EN_USB_CLKS + * 0b0..PLL outputs for USBPHYn off. + * 0b1..PLL outputs for USBPHYn on. + */ #define CCM_ANALOG_PLL_USB1_SET_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_EN_USB_CLKS_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_EN_USB_CLKS_MASK) #define CCM_ANALOG_PLL_USB1_SET_POWER_MASK (0x1000U) #define CCM_ANALOG_PLL_USB1_SET_POWER_SHIFT (12U) @@ -3900,6 +5606,10 @@ typedef struct { #define CCM_ANALOG_PLL_USB1_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_ENABLE_MASK) #define CCM_ANALOG_PLL_USB1_SET_BYPASS_CLK_SRC_MASK (0xC000U) #define CCM_ANALOG_PLL_USB1_SET_BYPASS_CLK_SRC_SHIFT (14U) +/*! BYPASS_CLK_SRC + * 0b00..Select the 24MHz oscillator as source. + * 0b01..Select the CLK1_N / CLK1_P as source. + */ #define CCM_ANALOG_PLL_USB1_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_BYPASS_CLK_SRC_MASK) #define CCM_ANALOG_PLL_USB1_SET_BYPASS_MASK (0x10000U) #define CCM_ANALOG_PLL_USB1_SET_BYPASS_SHIFT (16U) @@ -3907,13 +5617,19 @@ typedef struct { #define CCM_ANALOG_PLL_USB1_SET_LOCK_MASK (0x80000000U) #define CCM_ANALOG_PLL_USB1_SET_LOCK_SHIFT (31U) #define CCM_ANALOG_PLL_USB1_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_LOCK_MASK) +/*! @} */ /*! @name PLL_USB1_CLR - Analog USB1 480MHz PLL Control Register */ -#define CCM_ANALOG_PLL_USB1_CLR_DIV_SELECT_MASK (0x3U) -#define CCM_ANALOG_PLL_USB1_CLR_DIV_SELECT_SHIFT (0U) +/*! @{ */ +#define CCM_ANALOG_PLL_USB1_CLR_DIV_SELECT_MASK (0x2U) +#define CCM_ANALOG_PLL_USB1_CLR_DIV_SELECT_SHIFT (1U) #define CCM_ANALOG_PLL_USB1_CLR_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_DIV_SELECT_MASK) #define CCM_ANALOG_PLL_USB1_CLR_EN_USB_CLKS_MASK (0x40U) #define CCM_ANALOG_PLL_USB1_CLR_EN_USB_CLKS_SHIFT (6U) +/*! EN_USB_CLKS + * 0b0..PLL outputs for USBPHYn off. + * 0b1..PLL outputs for USBPHYn on. + */ #define CCM_ANALOG_PLL_USB1_CLR_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_EN_USB_CLKS_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_EN_USB_CLKS_MASK) #define CCM_ANALOG_PLL_USB1_CLR_POWER_MASK (0x1000U) #define CCM_ANALOG_PLL_USB1_CLR_POWER_SHIFT (12U) @@ -3923,6 +5639,10 @@ typedef struct { #define CCM_ANALOG_PLL_USB1_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_ENABLE_MASK) #define CCM_ANALOG_PLL_USB1_CLR_BYPASS_CLK_SRC_MASK (0xC000U) #define CCM_ANALOG_PLL_USB1_CLR_BYPASS_CLK_SRC_SHIFT (14U) +/*! BYPASS_CLK_SRC + * 0b00..Select the 24MHz oscillator as source. + * 0b01..Select the CLK1_N / CLK1_P as source. + */ #define CCM_ANALOG_PLL_USB1_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_BYPASS_CLK_SRC_MASK) #define CCM_ANALOG_PLL_USB1_CLR_BYPASS_MASK (0x10000U) #define CCM_ANALOG_PLL_USB1_CLR_BYPASS_SHIFT (16U) @@ -3930,13 +5650,19 @@ typedef struct { #define CCM_ANALOG_PLL_USB1_CLR_LOCK_MASK (0x80000000U) #define CCM_ANALOG_PLL_USB1_CLR_LOCK_SHIFT (31U) #define CCM_ANALOG_PLL_USB1_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_LOCK_MASK) +/*! @} */ /*! @name PLL_USB1_TOG - Analog USB1 480MHz PLL Control Register */ -#define CCM_ANALOG_PLL_USB1_TOG_DIV_SELECT_MASK (0x3U) -#define CCM_ANALOG_PLL_USB1_TOG_DIV_SELECT_SHIFT (0U) +/*! @{ */ +#define CCM_ANALOG_PLL_USB1_TOG_DIV_SELECT_MASK (0x2U) +#define CCM_ANALOG_PLL_USB1_TOG_DIV_SELECT_SHIFT (1U) #define CCM_ANALOG_PLL_USB1_TOG_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_DIV_SELECT_MASK) #define CCM_ANALOG_PLL_USB1_TOG_EN_USB_CLKS_MASK (0x40U) #define CCM_ANALOG_PLL_USB1_TOG_EN_USB_CLKS_SHIFT (6U) +/*! EN_USB_CLKS + * 0b0..PLL outputs for USBPHYn off. + * 0b1..PLL outputs for USBPHYn on. + */ #define CCM_ANALOG_PLL_USB1_TOG_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_EN_USB_CLKS_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_EN_USB_CLKS_MASK) #define CCM_ANALOG_PLL_USB1_TOG_POWER_MASK (0x1000U) #define CCM_ANALOG_PLL_USB1_TOG_POWER_SHIFT (12U) @@ -3946,6 +5672,10 @@ typedef struct { #define CCM_ANALOG_PLL_USB1_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_ENABLE_MASK) #define CCM_ANALOG_PLL_USB1_TOG_BYPASS_CLK_SRC_MASK (0xC000U) #define CCM_ANALOG_PLL_USB1_TOG_BYPASS_CLK_SRC_SHIFT (14U) +/*! BYPASS_CLK_SRC + * 0b00..Select the 24MHz oscillator as source. + * 0b01..Select the CLK1_N / CLK1_P as source. + */ #define CCM_ANALOG_PLL_USB1_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_BYPASS_CLK_SRC_MASK) #define CCM_ANALOG_PLL_USB1_TOG_BYPASS_MASK (0x10000U) #define CCM_ANALOG_PLL_USB1_TOG_BYPASS_SHIFT (16U) @@ -3953,10 +5683,12 @@ typedef struct { #define CCM_ANALOG_PLL_USB1_TOG_LOCK_MASK (0x80000000U) #define CCM_ANALOG_PLL_USB1_TOG_LOCK_SHIFT (31U) #define CCM_ANALOG_PLL_USB1_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_LOCK_MASK) +/*! @} */ /*! @name PLL_USB2 - Analog USB2 480MHz PLL Control Register */ -#define CCM_ANALOG_PLL_USB2_DIV_SELECT_MASK (0x3U) -#define CCM_ANALOG_PLL_USB2_DIV_SELECT_SHIFT (0U) +/*! @{ */ +#define CCM_ANALOG_PLL_USB2_DIV_SELECT_MASK (0x2U) +#define CCM_ANALOG_PLL_USB2_DIV_SELECT_SHIFT (1U) #define CCM_ANALOG_PLL_USB2_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB2_DIV_SELECT_MASK) #define CCM_ANALOG_PLL_USB2_EN_USB_CLKS_MASK (0x40U) #define CCM_ANALOG_PLL_USB2_EN_USB_CLKS_SHIFT (6U) @@ -3969,6 +5701,12 @@ typedef struct { #define CCM_ANALOG_PLL_USB2_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB2_ENABLE_MASK) #define CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC_MASK (0xC000U) #define CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC_SHIFT (14U) +/*! BYPASS_CLK_SRC + * 0b00..Select the 24MHz oscillator as source. + * 0b01..Select the CLK1_N / CLK1_P as source. + * 0b10..Reserved1 + * 0b11..Reserved2 + */ #define CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC_MASK) #define CCM_ANALOG_PLL_USB2_BYPASS_MASK (0x10000U) #define CCM_ANALOG_PLL_USB2_BYPASS_SHIFT (16U) @@ -3976,10 +5714,12 @@ typedef struct { #define CCM_ANALOG_PLL_USB2_LOCK_MASK (0x80000000U) #define CCM_ANALOG_PLL_USB2_LOCK_SHIFT (31U) #define CCM_ANALOG_PLL_USB2_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB2_LOCK_MASK) +/*! @} */ /*! @name PLL_USB2_SET - Analog USB2 480MHz PLL Control Register */ -#define CCM_ANALOG_PLL_USB2_SET_DIV_SELECT_MASK (0x3U) -#define CCM_ANALOG_PLL_USB2_SET_DIV_SELECT_SHIFT (0U) +/*! @{ */ +#define CCM_ANALOG_PLL_USB2_SET_DIV_SELECT_MASK (0x2U) +#define CCM_ANALOG_PLL_USB2_SET_DIV_SELECT_SHIFT (1U) #define CCM_ANALOG_PLL_USB2_SET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_SET_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB2_SET_DIV_SELECT_MASK) #define CCM_ANALOG_PLL_USB2_SET_EN_USB_CLKS_MASK (0x40U) #define CCM_ANALOG_PLL_USB2_SET_EN_USB_CLKS_SHIFT (6U) @@ -3992,6 +5732,12 @@ typedef struct { #define CCM_ANALOG_PLL_USB2_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_SET_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB2_SET_ENABLE_MASK) #define CCM_ANALOG_PLL_USB2_SET_BYPASS_CLK_SRC_MASK (0xC000U) #define CCM_ANALOG_PLL_USB2_SET_BYPASS_CLK_SRC_SHIFT (14U) +/*! BYPASS_CLK_SRC + * 0b00..Select the 24MHz oscillator as source. + * 0b01..Select the CLK1_N / CLK1_P as source. + * 0b10..Reserved1 + * 0b11..Reserved2 + */ #define CCM_ANALOG_PLL_USB2_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_SET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB2_SET_BYPASS_CLK_SRC_MASK) #define CCM_ANALOG_PLL_USB2_SET_BYPASS_MASK (0x10000U) #define CCM_ANALOG_PLL_USB2_SET_BYPASS_SHIFT (16U) @@ -3999,10 +5745,12 @@ typedef struct { #define CCM_ANALOG_PLL_USB2_SET_LOCK_MASK (0x80000000U) #define CCM_ANALOG_PLL_USB2_SET_LOCK_SHIFT (31U) #define CCM_ANALOG_PLL_USB2_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_SET_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB2_SET_LOCK_MASK) +/*! @} */ /*! @name PLL_USB2_CLR - Analog USB2 480MHz PLL Control Register */ -#define CCM_ANALOG_PLL_USB2_CLR_DIV_SELECT_MASK (0x3U) -#define CCM_ANALOG_PLL_USB2_CLR_DIV_SELECT_SHIFT (0U) +/*! @{ */ +#define CCM_ANALOG_PLL_USB2_CLR_DIV_SELECT_MASK (0x2U) +#define CCM_ANALOG_PLL_USB2_CLR_DIV_SELECT_SHIFT (1U) #define CCM_ANALOG_PLL_USB2_CLR_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_CLR_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB2_CLR_DIV_SELECT_MASK) #define CCM_ANALOG_PLL_USB2_CLR_EN_USB_CLKS_MASK (0x40U) #define CCM_ANALOG_PLL_USB2_CLR_EN_USB_CLKS_SHIFT (6U) @@ -4015,6 +5763,12 @@ typedef struct { #define CCM_ANALOG_PLL_USB2_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_CLR_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB2_CLR_ENABLE_MASK) #define CCM_ANALOG_PLL_USB2_CLR_BYPASS_CLK_SRC_MASK (0xC000U) #define CCM_ANALOG_PLL_USB2_CLR_BYPASS_CLK_SRC_SHIFT (14U) +/*! BYPASS_CLK_SRC + * 0b00..Select the 24MHz oscillator as source. + * 0b01..Select the CLK1_N / CLK1_P as source. + * 0b10..Reserved1 + * 0b11..Reserved2 + */ #define CCM_ANALOG_PLL_USB2_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_CLR_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB2_CLR_BYPASS_CLK_SRC_MASK) #define CCM_ANALOG_PLL_USB2_CLR_BYPASS_MASK (0x10000U) #define CCM_ANALOG_PLL_USB2_CLR_BYPASS_SHIFT (16U) @@ -4022,10 +5776,12 @@ typedef struct { #define CCM_ANALOG_PLL_USB2_CLR_LOCK_MASK (0x80000000U) #define CCM_ANALOG_PLL_USB2_CLR_LOCK_SHIFT (31U) #define CCM_ANALOG_PLL_USB2_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_CLR_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB2_CLR_LOCK_MASK) +/*! @} */ /*! @name PLL_USB2_TOG - Analog USB2 480MHz PLL Control Register */ -#define CCM_ANALOG_PLL_USB2_TOG_DIV_SELECT_MASK (0x3U) -#define CCM_ANALOG_PLL_USB2_TOG_DIV_SELECT_SHIFT (0U) +/*! @{ */ +#define CCM_ANALOG_PLL_USB2_TOG_DIV_SELECT_MASK (0x2U) +#define CCM_ANALOG_PLL_USB2_TOG_DIV_SELECT_SHIFT (1U) #define CCM_ANALOG_PLL_USB2_TOG_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_TOG_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB2_TOG_DIV_SELECT_MASK) #define CCM_ANALOG_PLL_USB2_TOG_EN_USB_CLKS_MASK (0x40U) #define CCM_ANALOG_PLL_USB2_TOG_EN_USB_CLKS_SHIFT (6U) @@ -4038,6 +5794,12 @@ typedef struct { #define CCM_ANALOG_PLL_USB2_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_TOG_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB2_TOG_ENABLE_MASK) #define CCM_ANALOG_PLL_USB2_TOG_BYPASS_CLK_SRC_MASK (0xC000U) #define CCM_ANALOG_PLL_USB2_TOG_BYPASS_CLK_SRC_SHIFT (14U) +/*! BYPASS_CLK_SRC + * 0b00..Select the 24MHz oscillator as source. + * 0b01..Select the CLK1_N / CLK1_P as source. + * 0b10..Reserved1 + * 0b11..Reserved2 + */ #define CCM_ANALOG_PLL_USB2_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_TOG_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB2_TOG_BYPASS_CLK_SRC_MASK) #define CCM_ANALOG_PLL_USB2_TOG_BYPASS_MASK (0x10000U) #define CCM_ANALOG_PLL_USB2_TOG_BYPASS_SHIFT (16U) @@ -4045,8 +5807,10 @@ typedef struct { #define CCM_ANALOG_PLL_USB2_TOG_LOCK_MASK (0x80000000U) #define CCM_ANALOG_PLL_USB2_TOG_LOCK_SHIFT (31U) #define CCM_ANALOG_PLL_USB2_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_TOG_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB2_TOG_LOCK_MASK) +/*! @} */ /*! @name PLL_SYS - Analog System PLL Control Register */ +/*! @{ */ #define CCM_ANALOG_PLL_SYS_DIV_SELECT_MASK (0x1U) #define CCM_ANALOG_PLL_SYS_DIV_SELECT_SHIFT (0U) #define CCM_ANALOG_PLL_SYS_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_SYS_DIV_SELECT_MASK) @@ -4058,6 +5822,10 @@ typedef struct { #define CCM_ANALOG_PLL_SYS_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_ENABLE_SHIFT)) & CCM_ANALOG_PLL_SYS_ENABLE_MASK) #define CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_MASK (0xC000U) #define CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_SHIFT (14U) +/*! BYPASS_CLK_SRC + * 0b00..Select the 24MHz oscillator as source. + * 0b01..Select the CLK1_N / CLK1_P as source. + */ #define CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_MASK) #define CCM_ANALOG_PLL_SYS_BYPASS_MASK (0x10000U) #define CCM_ANALOG_PLL_SYS_BYPASS_SHIFT (16U) @@ -4068,8 +5836,10 @@ typedef struct { #define CCM_ANALOG_PLL_SYS_LOCK_MASK (0x80000000U) #define CCM_ANALOG_PLL_SYS_LOCK_SHIFT (31U) #define CCM_ANALOG_PLL_SYS_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_LOCK_SHIFT)) & CCM_ANALOG_PLL_SYS_LOCK_MASK) +/*! @} */ /*! @name PLL_SYS_SET - Analog System PLL Control Register */ +/*! @{ */ #define CCM_ANALOG_PLL_SYS_SET_DIV_SELECT_MASK (0x1U) #define CCM_ANALOG_PLL_SYS_SET_DIV_SELECT_SHIFT (0U) #define CCM_ANALOG_PLL_SYS_SET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SET_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_SYS_SET_DIV_SELECT_MASK) @@ -4081,6 +5851,10 @@ typedef struct { #define CCM_ANALOG_PLL_SYS_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SET_ENABLE_SHIFT)) & CCM_ANALOG_PLL_SYS_SET_ENABLE_MASK) #define CCM_ANALOG_PLL_SYS_SET_BYPASS_CLK_SRC_MASK (0xC000U) #define CCM_ANALOG_PLL_SYS_SET_BYPASS_CLK_SRC_SHIFT (14U) +/*! BYPASS_CLK_SRC + * 0b00..Select the 24MHz oscillator as source. + * 0b01..Select the CLK1_N / CLK1_P as source. + */ #define CCM_ANALOG_PLL_SYS_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_SYS_SET_BYPASS_CLK_SRC_MASK) #define CCM_ANALOG_PLL_SYS_SET_BYPASS_MASK (0x10000U) #define CCM_ANALOG_PLL_SYS_SET_BYPASS_SHIFT (16U) @@ -4091,8 +5865,10 @@ typedef struct { #define CCM_ANALOG_PLL_SYS_SET_LOCK_MASK (0x80000000U) #define CCM_ANALOG_PLL_SYS_SET_LOCK_SHIFT (31U) #define CCM_ANALOG_PLL_SYS_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SET_LOCK_SHIFT)) & CCM_ANALOG_PLL_SYS_SET_LOCK_MASK) +/*! @} */ /*! @name PLL_SYS_CLR - Analog System PLL Control Register */ +/*! @{ */ #define CCM_ANALOG_PLL_SYS_CLR_DIV_SELECT_MASK (0x1U) #define CCM_ANALOG_PLL_SYS_CLR_DIV_SELECT_SHIFT (0U) #define CCM_ANALOG_PLL_SYS_CLR_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_CLR_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_SYS_CLR_DIV_SELECT_MASK) @@ -4104,6 +5880,10 @@ typedef struct { #define CCM_ANALOG_PLL_SYS_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_CLR_ENABLE_SHIFT)) & CCM_ANALOG_PLL_SYS_CLR_ENABLE_MASK) #define CCM_ANALOG_PLL_SYS_CLR_BYPASS_CLK_SRC_MASK (0xC000U) #define CCM_ANALOG_PLL_SYS_CLR_BYPASS_CLK_SRC_SHIFT (14U) +/*! BYPASS_CLK_SRC + * 0b00..Select the 24MHz oscillator as source. + * 0b01..Select the CLK1_N / CLK1_P as source. + */ #define CCM_ANALOG_PLL_SYS_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_CLR_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_SYS_CLR_BYPASS_CLK_SRC_MASK) #define CCM_ANALOG_PLL_SYS_CLR_BYPASS_MASK (0x10000U) #define CCM_ANALOG_PLL_SYS_CLR_BYPASS_SHIFT (16U) @@ -4114,8 +5894,10 @@ typedef struct { #define CCM_ANALOG_PLL_SYS_CLR_LOCK_MASK (0x80000000U) #define CCM_ANALOG_PLL_SYS_CLR_LOCK_SHIFT (31U) #define CCM_ANALOG_PLL_SYS_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_CLR_LOCK_SHIFT)) & CCM_ANALOG_PLL_SYS_CLR_LOCK_MASK) +/*! @} */ /*! @name PLL_SYS_TOG - Analog System PLL Control Register */ +/*! @{ */ #define CCM_ANALOG_PLL_SYS_TOG_DIV_SELECT_MASK (0x1U) #define CCM_ANALOG_PLL_SYS_TOG_DIV_SELECT_SHIFT (0U) #define CCM_ANALOG_PLL_SYS_TOG_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_TOG_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_SYS_TOG_DIV_SELECT_MASK) @@ -4127,6 +5909,10 @@ typedef struct { #define CCM_ANALOG_PLL_SYS_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_TOG_ENABLE_SHIFT)) & CCM_ANALOG_PLL_SYS_TOG_ENABLE_MASK) #define CCM_ANALOG_PLL_SYS_TOG_BYPASS_CLK_SRC_MASK (0xC000U) #define CCM_ANALOG_PLL_SYS_TOG_BYPASS_CLK_SRC_SHIFT (14U) +/*! BYPASS_CLK_SRC + * 0b00..Select the 24MHz oscillator as source. + * 0b01..Select the CLK1_N / CLK1_P as source. + */ #define CCM_ANALOG_PLL_SYS_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_TOG_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_SYS_TOG_BYPASS_CLK_SRC_MASK) #define CCM_ANALOG_PLL_SYS_TOG_BYPASS_MASK (0x10000U) #define CCM_ANALOG_PLL_SYS_TOG_BYPASS_SHIFT (16U) @@ -4137,29 +5923,41 @@ typedef struct { #define CCM_ANALOG_PLL_SYS_TOG_LOCK_MASK (0x80000000U) #define CCM_ANALOG_PLL_SYS_TOG_LOCK_SHIFT (31U) #define CCM_ANALOG_PLL_SYS_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_TOG_LOCK_SHIFT)) & CCM_ANALOG_PLL_SYS_TOG_LOCK_MASK) +/*! @} */ /*! @name PLL_SYS_SS - 528MHz System PLL Spread Spectrum Register */ +/*! @{ */ #define CCM_ANALOG_PLL_SYS_SS_STEP_MASK (0x7FFFU) #define CCM_ANALOG_PLL_SYS_SS_STEP_SHIFT (0U) #define CCM_ANALOG_PLL_SYS_SS_STEP(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SS_STEP_SHIFT)) & CCM_ANALOG_PLL_SYS_SS_STEP_MASK) #define CCM_ANALOG_PLL_SYS_SS_ENABLE_MASK (0x8000U) #define CCM_ANALOG_PLL_SYS_SS_ENABLE_SHIFT (15U) +/*! ENABLE - Enable bit + * 0b0..Spread spectrum modulation disabled + * 0b1..Soread spectrum modulation enabled + */ #define CCM_ANALOG_PLL_SYS_SS_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SS_ENABLE_SHIFT)) & CCM_ANALOG_PLL_SYS_SS_ENABLE_MASK) #define CCM_ANALOG_PLL_SYS_SS_STOP_MASK (0xFFFF0000U) #define CCM_ANALOG_PLL_SYS_SS_STOP_SHIFT (16U) #define CCM_ANALOG_PLL_SYS_SS_STOP(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SS_STOP_SHIFT)) & CCM_ANALOG_PLL_SYS_SS_STOP_MASK) +/*! @} */ /*! @name PLL_SYS_NUM - Numerator of 528MHz System PLL Fractional Loop Divider Register */ +/*! @{ */ #define CCM_ANALOG_PLL_SYS_NUM_A_MASK (0x3FFFFFFFU) #define CCM_ANALOG_PLL_SYS_NUM_A_SHIFT (0U) #define CCM_ANALOG_PLL_SYS_NUM_A(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_NUM_A_SHIFT)) & CCM_ANALOG_PLL_SYS_NUM_A_MASK) +/*! @} */ /*! @name PLL_SYS_DENOM - Denominator of 528MHz System PLL Fractional Loop Divider Register */ +/*! @{ */ #define CCM_ANALOG_PLL_SYS_DENOM_B_MASK (0x3FFFFFFFU) #define CCM_ANALOG_PLL_SYS_DENOM_B_SHIFT (0U) #define CCM_ANALOG_PLL_SYS_DENOM_B(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_DENOM_B_SHIFT)) & CCM_ANALOG_PLL_SYS_DENOM_B_MASK) +/*! @} */ /*! @name PLL_AUDIO - Analog Audio PLL control Register */ +/*! @{ */ #define CCM_ANALOG_PLL_AUDIO_DIV_SELECT_MASK (0x7FU) #define CCM_ANALOG_PLL_AUDIO_DIV_SELECT_SHIFT (0U) #define CCM_ANALOG_PLL_AUDIO_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_DIV_SELECT_MASK) @@ -4171,6 +5969,12 @@ typedef struct { #define CCM_ANALOG_PLL_AUDIO_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_ENABLE_SHIFT)) & CCM_ANALOG_PLL_AUDIO_ENABLE_MASK) #define CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_MASK (0xC000U) #define CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_SHIFT (14U) +/*! BYPASS_CLK_SRC + * 0b00..Select the 24MHz oscillator as source. + * 0b01..Select the CLK1_N / CLK1_P as source. + * 0b10..Reserved1 + * 0b11..Reserved2 + */ #define CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_MASK) #define CCM_ANALOG_PLL_AUDIO_BYPASS_MASK (0x10000U) #define CCM_ANALOG_PLL_AUDIO_BYPASS_SHIFT (16U) @@ -4180,12 +5984,20 @@ typedef struct { #define CCM_ANALOG_PLL_AUDIO_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_AUDIO_PFD_OFFSET_EN_MASK) #define CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_MASK (0x180000U) #define CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_SHIFT (19U) +/*! POST_DIV_SELECT + * 0b00..Divide by 4. + * 0b01..Divide by 2. + * 0b10..Divide by 1. + * 0b11..Reserved + */ #define CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_MASK) #define CCM_ANALOG_PLL_AUDIO_LOCK_MASK (0x80000000U) #define CCM_ANALOG_PLL_AUDIO_LOCK_SHIFT (31U) #define CCM_ANALOG_PLL_AUDIO_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_LOCK_SHIFT)) & CCM_ANALOG_PLL_AUDIO_LOCK_MASK) +/*! @} */ /*! @name PLL_AUDIO_SET - Analog Audio PLL control Register */ +/*! @{ */ #define CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT_MASK (0x7FU) #define CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT_SHIFT (0U) #define CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT_MASK) @@ -4197,6 +6009,12 @@ typedef struct { #define CCM_ANALOG_PLL_AUDIO_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_ENABLE_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_ENABLE_MASK) #define CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC_MASK (0xC000U) #define CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC_SHIFT (14U) +/*! BYPASS_CLK_SRC + * 0b00..Select the 24MHz oscillator as source. + * 0b01..Select the CLK1_N / CLK1_P as source. + * 0b10..Reserved1 + * 0b11..Reserved2 + */ #define CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC_MASK) #define CCM_ANALOG_PLL_AUDIO_SET_BYPASS_MASK (0x10000U) #define CCM_ANALOG_PLL_AUDIO_SET_BYPASS_SHIFT (16U) @@ -4206,12 +6024,20 @@ typedef struct { #define CCM_ANALOG_PLL_AUDIO_SET_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_PFD_OFFSET_EN_MASK) #define CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SELECT_MASK (0x180000U) #define CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SELECT_SHIFT (19U) +/*! POST_DIV_SELECT + * 0b00..Divide by 4. + * 0b01..Divide by 2. + * 0b10..Divide by 1. + * 0b11..Reserved + */ #define CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SELECT_MASK) #define CCM_ANALOG_PLL_AUDIO_SET_LOCK_MASK (0x80000000U) #define CCM_ANALOG_PLL_AUDIO_SET_LOCK_SHIFT (31U) #define CCM_ANALOG_PLL_AUDIO_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_LOCK_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_LOCK_MASK) +/*! @} */ /*! @name PLL_AUDIO_CLR - Analog Audio PLL control Register */ +/*! @{ */ #define CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT_MASK (0x7FU) #define CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT_SHIFT (0U) #define CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT_MASK) @@ -4223,6 +6049,12 @@ typedef struct { #define CCM_ANALOG_PLL_AUDIO_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_ENABLE_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_ENABLE_MASK) #define CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC_MASK (0xC000U) #define CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC_SHIFT (14U) +/*! BYPASS_CLK_SRC + * 0b00..Select the 24MHz oscillator as source. + * 0b01..Select the CLK1_N / CLK1_P as source. + * 0b10..Reserved1 + * 0b11..Reserved2 + */ #define CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC_MASK) #define CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_MASK (0x10000U) #define CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_SHIFT (16U) @@ -4232,12 +6064,20 @@ typedef struct { #define CCM_ANALOG_PLL_AUDIO_CLR_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_PFD_OFFSET_EN_MASK) #define CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SELECT_MASK (0x180000U) #define CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SELECT_SHIFT (19U) +/*! POST_DIV_SELECT + * 0b00..Divide by 4. + * 0b01..Divide by 2. + * 0b10..Divide by 1. + * 0b11..Reserved + */ #define CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SELECT_MASK) #define CCM_ANALOG_PLL_AUDIO_CLR_LOCK_MASK (0x80000000U) #define CCM_ANALOG_PLL_AUDIO_CLR_LOCK_SHIFT (31U) #define CCM_ANALOG_PLL_AUDIO_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_LOCK_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_LOCK_MASK) +/*! @} */ /*! @name PLL_AUDIO_TOG - Analog Audio PLL control Register */ +/*! @{ */ #define CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT_MASK (0x7FU) #define CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT_SHIFT (0U) #define CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT_MASK) @@ -4249,6 +6089,12 @@ typedef struct { #define CCM_ANALOG_PLL_AUDIO_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_ENABLE_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_ENABLE_MASK) #define CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC_MASK (0xC000U) #define CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC_SHIFT (14U) +/*! BYPASS_CLK_SRC + * 0b00..Select the 24MHz oscillator as source. + * 0b01..Select the CLK1_N / CLK1_P as source. + * 0b10..Reserved1 + * 0b11..Reserved2 + */ #define CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC_MASK) #define CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_MASK (0x10000U) #define CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_SHIFT (16U) @@ -4258,22 +6104,34 @@ typedef struct { #define CCM_ANALOG_PLL_AUDIO_TOG_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_PFD_OFFSET_EN_MASK) #define CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SELECT_MASK (0x180000U) #define CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SELECT_SHIFT (19U) +/*! POST_DIV_SELECT + * 0b00..Divide by 4. + * 0b01..Divide by 2. + * 0b10..Divide by 1. + * 0b11..Reserved + */ #define CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SELECT_MASK) #define CCM_ANALOG_PLL_AUDIO_TOG_LOCK_MASK (0x80000000U) #define CCM_ANALOG_PLL_AUDIO_TOG_LOCK_SHIFT (31U) #define CCM_ANALOG_PLL_AUDIO_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_LOCK_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_LOCK_MASK) +/*! @} */ /*! @name PLL_AUDIO_NUM - Numerator of Audio PLL Fractional Loop Divider Register */ +/*! @{ */ #define CCM_ANALOG_PLL_AUDIO_NUM_A_MASK (0x3FFFFFFFU) #define CCM_ANALOG_PLL_AUDIO_NUM_A_SHIFT (0U) #define CCM_ANALOG_PLL_AUDIO_NUM_A(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_NUM_A_SHIFT)) & CCM_ANALOG_PLL_AUDIO_NUM_A_MASK) +/*! @} */ /*! @name PLL_AUDIO_DENOM - Denominator of Audio PLL Fractional Loop Divider Register */ +/*! @{ */ #define CCM_ANALOG_PLL_AUDIO_DENOM_B_MASK (0x3FFFFFFFU) #define CCM_ANALOG_PLL_AUDIO_DENOM_B_SHIFT (0U) #define CCM_ANALOG_PLL_AUDIO_DENOM_B(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_DENOM_B_SHIFT)) & CCM_ANALOG_PLL_AUDIO_DENOM_B_MASK) +/*! @} */ /*! @name PLL_VIDEO - Analog Video PLL control Register */ +/*! @{ */ #define CCM_ANALOG_PLL_VIDEO_DIV_SELECT_MASK (0x7FU) #define CCM_ANALOG_PLL_VIDEO_DIV_SELECT_SHIFT (0U) #define CCM_ANALOG_PLL_VIDEO_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_VIDEO_DIV_SELECT_MASK) @@ -4285,6 +6143,12 @@ typedef struct { #define CCM_ANALOG_PLL_VIDEO_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_ENABLE_SHIFT)) & CCM_ANALOG_PLL_VIDEO_ENABLE_MASK) #define CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_MASK (0xC000U) #define CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_SHIFT (14U) +/*! BYPASS_CLK_SRC + * 0b00..Select the 24MHz oscillator as source. + * 0b01..Select the CLK1_N / CLK1_P as source. + * 0b10..Reserved1 + * 0b11..Reserved2 + */ #define CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_MASK) #define CCM_ANALOG_PLL_VIDEO_BYPASS_MASK (0x10000U) #define CCM_ANALOG_PLL_VIDEO_BYPASS_SHIFT (16U) @@ -4294,12 +6158,20 @@ typedef struct { #define CCM_ANALOG_PLL_VIDEO_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_VIDEO_PFD_OFFSET_EN_MASK) #define CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT_MASK (0x180000U) #define CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT_SHIFT (19U) +/*! POST_DIV_SELECT + * 0b00..Divide by 4. + * 0b01..Divide by 2. + * 0b10..Divide by 1. + * 0b11..Reserved + */ #define CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT_MASK) #define CCM_ANALOG_PLL_VIDEO_LOCK_MASK (0x80000000U) #define CCM_ANALOG_PLL_VIDEO_LOCK_SHIFT (31U) #define CCM_ANALOG_PLL_VIDEO_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_LOCK_SHIFT)) & CCM_ANALOG_PLL_VIDEO_LOCK_MASK) +/*! @} */ /*! @name PLL_VIDEO_SET - Analog Video PLL control Register */ +/*! @{ */ #define CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT_MASK (0x7FU) #define CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT_SHIFT (0U) #define CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT_MASK) @@ -4311,6 +6183,12 @@ typedef struct { #define CCM_ANALOG_PLL_VIDEO_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_SET_ENABLE_SHIFT)) & CCM_ANALOG_PLL_VIDEO_SET_ENABLE_MASK) #define CCM_ANALOG_PLL_VIDEO_SET_BYPASS_CLK_SRC_MASK (0xC000U) #define CCM_ANALOG_PLL_VIDEO_SET_BYPASS_CLK_SRC_SHIFT (14U) +/*! BYPASS_CLK_SRC + * 0b00..Select the 24MHz oscillator as source. + * 0b01..Select the CLK1_N / CLK1_P as source. + * 0b10..Reserved1 + * 0b11..Reserved2 + */ #define CCM_ANALOG_PLL_VIDEO_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_SET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_VIDEO_SET_BYPASS_CLK_SRC_MASK) #define CCM_ANALOG_PLL_VIDEO_SET_BYPASS_MASK (0x10000U) #define CCM_ANALOG_PLL_VIDEO_SET_BYPASS_SHIFT (16U) @@ -4320,12 +6198,20 @@ typedef struct { #define CCM_ANALOG_PLL_VIDEO_SET_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_SET_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_VIDEO_SET_PFD_OFFSET_EN_MASK) #define CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SELECT_MASK (0x180000U) #define CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SELECT_SHIFT (19U) +/*! POST_DIV_SELECT + * 0b00..Divide by 4. + * 0b01..Divide by 2. + * 0b10..Divide by 1. + * 0b11..Reserved + */ #define CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SELECT_MASK) #define CCM_ANALOG_PLL_VIDEO_SET_LOCK_MASK (0x80000000U) #define CCM_ANALOG_PLL_VIDEO_SET_LOCK_SHIFT (31U) #define CCM_ANALOG_PLL_VIDEO_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_SET_LOCK_SHIFT)) & CCM_ANALOG_PLL_VIDEO_SET_LOCK_MASK) +/*! @} */ /*! @name PLL_VIDEO_CLR - Analog Video PLL control Register */ +/*! @{ */ #define CCM_ANALOG_PLL_VIDEO_CLR_DIV_SELECT_MASK (0x7FU) #define CCM_ANALOG_PLL_VIDEO_CLR_DIV_SELECT_SHIFT (0U) #define CCM_ANALOG_PLL_VIDEO_CLR_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_CLR_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_VIDEO_CLR_DIV_SELECT_MASK) @@ -4337,6 +6223,12 @@ typedef struct { #define CCM_ANALOG_PLL_VIDEO_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_CLR_ENABLE_SHIFT)) & CCM_ANALOG_PLL_VIDEO_CLR_ENABLE_MASK) #define CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_CLK_SRC_MASK (0xC000U) #define CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_CLK_SRC_SHIFT (14U) +/*! BYPASS_CLK_SRC + * 0b00..Select the 24MHz oscillator as source. + * 0b01..Select the CLK1_N / CLK1_P as source. + * 0b10..Reserved1 + * 0b11..Reserved2 + */ #define CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_CLK_SRC_MASK) #define CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_MASK (0x10000U) #define CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_SHIFT (16U) @@ -4346,12 +6238,20 @@ typedef struct { #define CCM_ANALOG_PLL_VIDEO_CLR_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_CLR_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_VIDEO_CLR_PFD_OFFSET_EN_MASK) #define CCM_ANALOG_PLL_VIDEO_CLR_POST_DIV_SELECT_MASK (0x180000U) #define CCM_ANALOG_PLL_VIDEO_CLR_POST_DIV_SELECT_SHIFT (19U) +/*! POST_DIV_SELECT + * 0b00..Divide by 4. + * 0b01..Divide by 2. + * 0b10..Divide by 1. + * 0b11..Reserved + */ #define CCM_ANALOG_PLL_VIDEO_CLR_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_CLR_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_VIDEO_CLR_POST_DIV_SELECT_MASK) #define CCM_ANALOG_PLL_VIDEO_CLR_LOCK_MASK (0x80000000U) #define CCM_ANALOG_PLL_VIDEO_CLR_LOCK_SHIFT (31U) #define CCM_ANALOG_PLL_VIDEO_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_CLR_LOCK_SHIFT)) & CCM_ANALOG_PLL_VIDEO_CLR_LOCK_MASK) +/*! @} */ /*! @name PLL_VIDEO_TOG - Analog Video PLL control Register */ +/*! @{ */ #define CCM_ANALOG_PLL_VIDEO_TOG_DIV_SELECT_MASK (0x7FU) #define CCM_ANALOG_PLL_VIDEO_TOG_DIV_SELECT_SHIFT (0U) #define CCM_ANALOG_PLL_VIDEO_TOG_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_TOG_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_VIDEO_TOG_DIV_SELECT_MASK) @@ -4363,6 +6263,12 @@ typedef struct { #define CCM_ANALOG_PLL_VIDEO_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_TOG_ENABLE_SHIFT)) & CCM_ANALOG_PLL_VIDEO_TOG_ENABLE_MASK) #define CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_CLK_SRC_MASK (0xC000U) #define CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_CLK_SRC_SHIFT (14U) +/*! BYPASS_CLK_SRC + * 0b00..Select the 24MHz oscillator as source. + * 0b01..Select the CLK1_N / CLK1_P as source. + * 0b10..Reserved1 + * 0b11..Reserved2 + */ #define CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_CLK_SRC_MASK) #define CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_MASK (0x10000U) #define CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_SHIFT (16U) @@ -4372,36 +6278,51 @@ typedef struct { #define CCM_ANALOG_PLL_VIDEO_TOG_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_TOG_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_VIDEO_TOG_PFD_OFFSET_EN_MASK) #define CCM_ANALOG_PLL_VIDEO_TOG_POST_DIV_SELECT_MASK (0x180000U) #define CCM_ANALOG_PLL_VIDEO_TOG_POST_DIV_SELECT_SHIFT (19U) +/*! POST_DIV_SELECT + * 0b00..Divide by 4. + * 0b01..Divide by 2. + * 0b10..Divide by 1. + * 0b11..Reserved + */ #define CCM_ANALOG_PLL_VIDEO_TOG_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_TOG_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_VIDEO_TOG_POST_DIV_SELECT_MASK) #define CCM_ANALOG_PLL_VIDEO_TOG_LOCK_MASK (0x80000000U) #define CCM_ANALOG_PLL_VIDEO_TOG_LOCK_SHIFT (31U) #define CCM_ANALOG_PLL_VIDEO_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_TOG_LOCK_SHIFT)) & CCM_ANALOG_PLL_VIDEO_TOG_LOCK_MASK) +/*! @} */ /*! @name PLL_VIDEO_NUM - Numerator of Video PLL Fractional Loop Divider Register */ +/*! @{ */ #define CCM_ANALOG_PLL_VIDEO_NUM_A_MASK (0x3FFFFFFFU) #define CCM_ANALOG_PLL_VIDEO_NUM_A_SHIFT (0U) #define CCM_ANALOG_PLL_VIDEO_NUM_A(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_NUM_A_SHIFT)) & CCM_ANALOG_PLL_VIDEO_NUM_A_MASK) +/*! @} */ /*! @name PLL_VIDEO_DENOM - Denominator of Video PLL Fractional Loop Divider Register */ +/*! @{ */ #define CCM_ANALOG_PLL_VIDEO_DENOM_B_MASK (0x3FFFFFFFU) #define CCM_ANALOG_PLL_VIDEO_DENOM_B_SHIFT (0U) #define CCM_ANALOG_PLL_VIDEO_DENOM_B(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_DENOM_B_SHIFT)) & CCM_ANALOG_PLL_VIDEO_DENOM_B_MASK) +/*! @} */ /*! @name PLL_ENET - Analog ENET PLL Control Register */ -#define CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT_MASK (0x3U) -#define CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT_SHIFT (0U) -#define CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT_MASK) -#define CCM_ANALOG_PLL_ENET_ENET1_DIV_SELECT_MASK (0xCU) -#define CCM_ANALOG_PLL_ENET_ENET1_DIV_SELECT_SHIFT (2U) -#define CCM_ANALOG_PLL_ENET_ENET1_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_ENET1_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ENET_ENET1_DIV_SELECT_MASK) +/*! @{ */ +#define CCM_ANALOG_PLL_ENET_DIV_SELECT_MASK (0x3U) +#define CCM_ANALOG_PLL_ENET_DIV_SELECT_SHIFT (0U) +#define CCM_ANALOG_PLL_ENET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ENET_DIV_SELECT_MASK) #define CCM_ANALOG_PLL_ENET_POWERDOWN_MASK (0x1000U) #define CCM_ANALOG_PLL_ENET_POWERDOWN_SHIFT (12U) #define CCM_ANALOG_PLL_ENET_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_ENET_POWERDOWN_MASK) -#define CCM_ANALOG_PLL_ENET_ENET1_125M_EN_MASK (0x2000U) -#define CCM_ANALOG_PLL_ENET_ENET1_125M_EN_SHIFT (13U) -#define CCM_ANALOG_PLL_ENET_ENET1_125M_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_ENET1_125M_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_ENET1_125M_EN_MASK) +#define CCM_ANALOG_PLL_ENET_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_ENET_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_ENET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_ENABLE_SHIFT)) & CCM_ANALOG_PLL_ENET_ENABLE_MASK) #define CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_MASK (0xC000U) #define CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_SHIFT (14U) +/*! BYPASS_CLK_SRC + * 0b00..Select the 24MHz oscillator as source. + * 0b01..Select the CLK1_N / CLK1_P as source. + * 0b10..Reserved1 + * 0b11..Reserved2 + */ #define CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_MASK) #define CCM_ANALOG_PLL_ENET_BYPASS_MASK (0x10000U) #define CCM_ANALOG_PLL_ENET_BYPASS_SHIFT (16U) @@ -4409,34 +6330,33 @@ typedef struct { #define CCM_ANALOG_PLL_ENET_PFD_OFFSET_EN_MASK (0x40000U) #define CCM_ANALOG_PLL_ENET_PFD_OFFSET_EN_SHIFT (18U) #define CCM_ANALOG_PLL_ENET_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_PFD_OFFSET_EN_MASK) -#define CCM_ANALOG_PLL_ENET_ENABLE_125M_MASK (0x80000U) -#define CCM_ANALOG_PLL_ENET_ENABLE_125M_SHIFT (19U) -#define CCM_ANALOG_PLL_ENET_ENABLE_125M(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_ENABLE_125M_SHIFT)) & CCM_ANALOG_PLL_ENET_ENABLE_125M_MASK) -#define CCM_ANALOG_PLL_ENET_ENET2_125M_EN_MASK (0x100000U) -#define CCM_ANALOG_PLL_ENET_ENET2_125M_EN_SHIFT (20U) -#define CCM_ANALOG_PLL_ENET_ENET2_125M_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_ENET2_125M_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_ENET2_125M_EN_MASK) #define CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_MASK (0x200000U) #define CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_SHIFT (21U) #define CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_MASK) #define CCM_ANALOG_PLL_ENET_LOCK_MASK (0x80000000U) #define CCM_ANALOG_PLL_ENET_LOCK_SHIFT (31U) #define CCM_ANALOG_PLL_ENET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_LOCK_SHIFT)) & CCM_ANALOG_PLL_ENET_LOCK_MASK) +/*! @} */ /*! @name PLL_ENET_SET - Analog ENET PLL Control Register */ -#define CCM_ANALOG_PLL_ENET_SET_ENET0_DIV_SELECT_MASK (0x3U) -#define CCM_ANALOG_PLL_ENET_SET_ENET0_DIV_SELECT_SHIFT (0U) -#define CCM_ANALOG_PLL_ENET_SET_ENET0_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_ENET0_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_ENET0_DIV_SELECT_MASK) -#define CCM_ANALOG_PLL_ENET_SET_ENET1_DIV_SELECT_MASK (0xCU) -#define CCM_ANALOG_PLL_ENET_SET_ENET1_DIV_SELECT_SHIFT (2U) -#define CCM_ANALOG_PLL_ENET_SET_ENET1_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_ENET1_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_ENET1_DIV_SELECT_MASK) +/*! @{ */ +#define CCM_ANALOG_PLL_ENET_SET_DIV_SELECT_MASK (0x3U) +#define CCM_ANALOG_PLL_ENET_SET_DIV_SELECT_SHIFT (0U) +#define CCM_ANALOG_PLL_ENET_SET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_DIV_SELECT_MASK) #define CCM_ANALOG_PLL_ENET_SET_POWERDOWN_MASK (0x1000U) #define CCM_ANALOG_PLL_ENET_SET_POWERDOWN_SHIFT (12U) #define CCM_ANALOG_PLL_ENET_SET_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_POWERDOWN_MASK) -#define CCM_ANALOG_PLL_ENET_SET_ENET1_125M_EN_MASK (0x2000U) -#define CCM_ANALOG_PLL_ENET_SET_ENET1_125M_EN_SHIFT (13U) -#define CCM_ANALOG_PLL_ENET_SET_ENET1_125M_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_ENET1_125M_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_ENET1_125M_EN_MASK) +#define CCM_ANALOG_PLL_ENET_SET_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_ENET_SET_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_ENET_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_ENABLE_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_ENABLE_MASK) #define CCM_ANALOG_PLL_ENET_SET_BYPASS_CLK_SRC_MASK (0xC000U) #define CCM_ANALOG_PLL_ENET_SET_BYPASS_CLK_SRC_SHIFT (14U) +/*! BYPASS_CLK_SRC + * 0b00..Select the 24MHz oscillator as source. + * 0b01..Select the CLK1_N / CLK1_P as source. + * 0b10..Reserved1 + * 0b11..Reserved2 + */ #define CCM_ANALOG_PLL_ENET_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_BYPASS_CLK_SRC_MASK) #define CCM_ANALOG_PLL_ENET_SET_BYPASS_MASK (0x10000U) #define CCM_ANALOG_PLL_ENET_SET_BYPASS_SHIFT (16U) @@ -4444,34 +6364,33 @@ typedef struct { #define CCM_ANALOG_PLL_ENET_SET_PFD_OFFSET_EN_MASK (0x40000U) #define CCM_ANALOG_PLL_ENET_SET_PFD_OFFSET_EN_SHIFT (18U) #define CCM_ANALOG_PLL_ENET_SET_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_PFD_OFFSET_EN_MASK) -#define CCM_ANALOG_PLL_ENET_SET_ENABLE_125M_MASK (0x80000U) -#define CCM_ANALOG_PLL_ENET_SET_ENABLE_125M_SHIFT (19U) -#define CCM_ANALOG_PLL_ENET_SET_ENABLE_125M(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_ENABLE_125M_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_ENABLE_125M_MASK) -#define CCM_ANALOG_PLL_ENET_SET_ENET2_125M_EN_MASK (0x100000U) -#define CCM_ANALOG_PLL_ENET_SET_ENET2_125M_EN_SHIFT (20U) -#define CCM_ANALOG_PLL_ENET_SET_ENET2_125M_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_ENET2_125M_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_ENET2_125M_EN_MASK) #define CCM_ANALOG_PLL_ENET_SET_ENET_25M_REF_EN_MASK (0x200000U) #define CCM_ANALOG_PLL_ENET_SET_ENET_25M_REF_EN_SHIFT (21U) #define CCM_ANALOG_PLL_ENET_SET_ENET_25M_REF_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_ENET_25M_REF_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_ENET_25M_REF_EN_MASK) #define CCM_ANALOG_PLL_ENET_SET_LOCK_MASK (0x80000000U) #define CCM_ANALOG_PLL_ENET_SET_LOCK_SHIFT (31U) #define CCM_ANALOG_PLL_ENET_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_LOCK_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_LOCK_MASK) +/*! @} */ /*! @name PLL_ENET_CLR - Analog ENET PLL Control Register */ -#define CCM_ANALOG_PLL_ENET_CLR_ENET0_DIV_SELECT_MASK (0x3U) -#define CCM_ANALOG_PLL_ENET_CLR_ENET0_DIV_SELECT_SHIFT (0U) -#define CCM_ANALOG_PLL_ENET_CLR_ENET0_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_ENET0_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_ENET0_DIV_SELECT_MASK) -#define CCM_ANALOG_PLL_ENET_CLR_ENET1_DIV_SELECT_MASK (0xCU) -#define CCM_ANALOG_PLL_ENET_CLR_ENET1_DIV_SELECT_SHIFT (2U) -#define CCM_ANALOG_PLL_ENET_CLR_ENET1_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_ENET1_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_ENET1_DIV_SELECT_MASK) +/*! @{ */ +#define CCM_ANALOG_PLL_ENET_CLR_DIV_SELECT_MASK (0x3U) +#define CCM_ANALOG_PLL_ENET_CLR_DIV_SELECT_SHIFT (0U) +#define CCM_ANALOG_PLL_ENET_CLR_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_DIV_SELECT_MASK) #define CCM_ANALOG_PLL_ENET_CLR_POWERDOWN_MASK (0x1000U) #define CCM_ANALOG_PLL_ENET_CLR_POWERDOWN_SHIFT (12U) #define CCM_ANALOG_PLL_ENET_CLR_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_POWERDOWN_MASK) -#define CCM_ANALOG_PLL_ENET_CLR_ENET1_125M_EN_MASK (0x2000U) -#define CCM_ANALOG_PLL_ENET_CLR_ENET1_125M_EN_SHIFT (13U) -#define CCM_ANALOG_PLL_ENET_CLR_ENET1_125M_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_ENET1_125M_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_ENET1_125M_EN_MASK) +#define CCM_ANALOG_PLL_ENET_CLR_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_ENET_CLR_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_ENET_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_ENABLE_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_ENABLE_MASK) #define CCM_ANALOG_PLL_ENET_CLR_BYPASS_CLK_SRC_MASK (0xC000U) #define CCM_ANALOG_PLL_ENET_CLR_BYPASS_CLK_SRC_SHIFT (14U) +/*! BYPASS_CLK_SRC + * 0b00..Select the 24MHz oscillator as source. + * 0b01..Select the CLK1_N / CLK1_P as source. + * 0b10..Reserved1 + * 0b11..Reserved2 + */ #define CCM_ANALOG_PLL_ENET_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_BYPASS_CLK_SRC_MASK) #define CCM_ANALOG_PLL_ENET_CLR_BYPASS_MASK (0x10000U) #define CCM_ANALOG_PLL_ENET_CLR_BYPASS_SHIFT (16U) @@ -4479,34 +6398,33 @@ typedef struct { #define CCM_ANALOG_PLL_ENET_CLR_PFD_OFFSET_EN_MASK (0x40000U) #define CCM_ANALOG_PLL_ENET_CLR_PFD_OFFSET_EN_SHIFT (18U) #define CCM_ANALOG_PLL_ENET_CLR_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_PFD_OFFSET_EN_MASK) -#define CCM_ANALOG_PLL_ENET_CLR_ENABLE_125M_MASK (0x80000U) -#define CCM_ANALOG_PLL_ENET_CLR_ENABLE_125M_SHIFT (19U) -#define CCM_ANALOG_PLL_ENET_CLR_ENABLE_125M(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_ENABLE_125M_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_ENABLE_125M_MASK) -#define CCM_ANALOG_PLL_ENET_CLR_ENET2_125M_EN_MASK (0x100000U) -#define CCM_ANALOG_PLL_ENET_CLR_ENET2_125M_EN_SHIFT (20U) -#define CCM_ANALOG_PLL_ENET_CLR_ENET2_125M_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_ENET2_125M_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_ENET2_125M_EN_MASK) #define CCM_ANALOG_PLL_ENET_CLR_ENET_25M_REF_EN_MASK (0x200000U) #define CCM_ANALOG_PLL_ENET_CLR_ENET_25M_REF_EN_SHIFT (21U) #define CCM_ANALOG_PLL_ENET_CLR_ENET_25M_REF_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_ENET_25M_REF_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_ENET_25M_REF_EN_MASK) #define CCM_ANALOG_PLL_ENET_CLR_LOCK_MASK (0x80000000U) #define CCM_ANALOG_PLL_ENET_CLR_LOCK_SHIFT (31U) #define CCM_ANALOG_PLL_ENET_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_LOCK_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_LOCK_MASK) +/*! @} */ /*! @name PLL_ENET_TOG - Analog ENET PLL Control Register */ -#define CCM_ANALOG_PLL_ENET_TOG_ENET0_DIV_SELECT_MASK (0x3U) -#define CCM_ANALOG_PLL_ENET_TOG_ENET0_DIV_SELECT_SHIFT (0U) -#define CCM_ANALOG_PLL_ENET_TOG_ENET0_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_ENET0_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_ENET0_DIV_SELECT_MASK) -#define CCM_ANALOG_PLL_ENET_TOG_ENET1_DIV_SELECT_MASK (0xCU) -#define CCM_ANALOG_PLL_ENET_TOG_ENET1_DIV_SELECT_SHIFT (2U) -#define CCM_ANALOG_PLL_ENET_TOG_ENET1_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_ENET1_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_ENET1_DIV_SELECT_MASK) +/*! @{ */ +#define CCM_ANALOG_PLL_ENET_TOG_DIV_SELECT_MASK (0x3U) +#define CCM_ANALOG_PLL_ENET_TOG_DIV_SELECT_SHIFT (0U) +#define CCM_ANALOG_PLL_ENET_TOG_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_DIV_SELECT_MASK) #define CCM_ANALOG_PLL_ENET_TOG_POWERDOWN_MASK (0x1000U) #define CCM_ANALOG_PLL_ENET_TOG_POWERDOWN_SHIFT (12U) #define CCM_ANALOG_PLL_ENET_TOG_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_POWERDOWN_MASK) -#define CCM_ANALOG_PLL_ENET_TOG_ENET1_125M_EN_MASK (0x2000U) -#define CCM_ANALOG_PLL_ENET_TOG_ENET1_125M_EN_SHIFT (13U) -#define CCM_ANALOG_PLL_ENET_TOG_ENET1_125M_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_ENET1_125M_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_ENET1_125M_EN_MASK) +#define CCM_ANALOG_PLL_ENET_TOG_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_ENET_TOG_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_ENET_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_ENABLE_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_ENABLE_MASK) #define CCM_ANALOG_PLL_ENET_TOG_BYPASS_CLK_SRC_MASK (0xC000U) #define CCM_ANALOG_PLL_ENET_TOG_BYPASS_CLK_SRC_SHIFT (14U) +/*! BYPASS_CLK_SRC + * 0b00..Select the 24MHz oscillator as source. + * 0b01..Select the CLK1_N / CLK1_P as source. + * 0b10..Reserved1 + * 0b11..Reserved2 + */ #define CCM_ANALOG_PLL_ENET_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_BYPASS_CLK_SRC_MASK) #define CCM_ANALOG_PLL_ENET_TOG_BYPASS_MASK (0x10000U) #define CCM_ANALOG_PLL_ENET_TOG_BYPASS_SHIFT (16U) @@ -4514,20 +6432,16 @@ typedef struct { #define CCM_ANALOG_PLL_ENET_TOG_PFD_OFFSET_EN_MASK (0x40000U) #define CCM_ANALOG_PLL_ENET_TOG_PFD_OFFSET_EN_SHIFT (18U) #define CCM_ANALOG_PLL_ENET_TOG_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_PFD_OFFSET_EN_MASK) -#define CCM_ANALOG_PLL_ENET_TOG_ENABLE_125M_MASK (0x80000U) -#define CCM_ANALOG_PLL_ENET_TOG_ENABLE_125M_SHIFT (19U) -#define CCM_ANALOG_PLL_ENET_TOG_ENABLE_125M(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_ENABLE_125M_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_ENABLE_125M_MASK) -#define CCM_ANALOG_PLL_ENET_TOG_ENET2_125M_EN_MASK (0x100000U) -#define CCM_ANALOG_PLL_ENET_TOG_ENET2_125M_EN_SHIFT (20U) -#define CCM_ANALOG_PLL_ENET_TOG_ENET2_125M_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_ENET2_125M_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_ENET2_125M_EN_MASK) #define CCM_ANALOG_PLL_ENET_TOG_ENET_25M_REF_EN_MASK (0x200000U) #define CCM_ANALOG_PLL_ENET_TOG_ENET_25M_REF_EN_SHIFT (21U) #define CCM_ANALOG_PLL_ENET_TOG_ENET_25M_REF_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_ENET_25M_REF_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_ENET_25M_REF_EN_MASK) #define CCM_ANALOG_PLL_ENET_TOG_LOCK_MASK (0x80000000U) #define CCM_ANALOG_PLL_ENET_TOG_LOCK_SHIFT (31U) #define CCM_ANALOG_PLL_ENET_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_LOCK_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_LOCK_MASK) +/*! @} */ /*! @name PFD_480 - 480MHz Clock (PLL3) Phase Fractional Divider Control Register */ +/*! @{ */ #define CCM_ANALOG_PFD_480_PFD0_FRAC_MASK (0x3FU) #define CCM_ANALOG_PFD_480_PFD0_FRAC_SHIFT (0U) #define CCM_ANALOG_PFD_480_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_PFD0_FRAC_MASK) @@ -4564,8 +6478,10 @@ typedef struct { #define CCM_ANALOG_PFD_480_PFD3_CLKGATE_MASK (0x80000000U) #define CCM_ANALOG_PFD_480_PFD3_CLKGATE_SHIFT (31U) #define CCM_ANALOG_PFD_480_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_PFD3_CLKGATE_MASK) +/*! @} */ /*! @name PFD_480_SET - 480MHz Clock (PLL3) Phase Fractional Divider Control Register */ +/*! @{ */ #define CCM_ANALOG_PFD_480_SET_PFD0_FRAC_MASK (0x3FU) #define CCM_ANALOG_PFD_480_SET_PFD0_FRAC_SHIFT (0U) #define CCM_ANALOG_PFD_480_SET_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD0_FRAC_MASK) @@ -4602,8 +6518,10 @@ typedef struct { #define CCM_ANALOG_PFD_480_SET_PFD3_CLKGATE_MASK (0x80000000U) #define CCM_ANALOG_PFD_480_SET_PFD3_CLKGATE_SHIFT (31U) #define CCM_ANALOG_PFD_480_SET_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD3_CLKGATE_MASK) +/*! @} */ /*! @name PFD_480_CLR - 480MHz Clock (PLL3) Phase Fractional Divider Control Register */ +/*! @{ */ #define CCM_ANALOG_PFD_480_CLR_PFD0_FRAC_MASK (0x3FU) #define CCM_ANALOG_PFD_480_CLR_PFD0_FRAC_SHIFT (0U) #define CCM_ANALOG_PFD_480_CLR_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD0_FRAC_MASK) @@ -4640,8 +6558,10 @@ typedef struct { #define CCM_ANALOG_PFD_480_CLR_PFD3_CLKGATE_MASK (0x80000000U) #define CCM_ANALOG_PFD_480_CLR_PFD3_CLKGATE_SHIFT (31U) #define CCM_ANALOG_PFD_480_CLR_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD3_CLKGATE_MASK) +/*! @} */ /*! @name PFD_480_TOG - 480MHz Clock (PLL3) Phase Fractional Divider Control Register */ +/*! @{ */ #define CCM_ANALOG_PFD_480_TOG_PFD0_FRAC_MASK (0x3FU) #define CCM_ANALOG_PFD_480_TOG_PFD0_FRAC_SHIFT (0U) #define CCM_ANALOG_PFD_480_TOG_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD0_FRAC_MASK) @@ -4678,8 +6598,10 @@ typedef struct { #define CCM_ANALOG_PFD_480_TOG_PFD3_CLKGATE_MASK (0x80000000U) #define CCM_ANALOG_PFD_480_TOG_PFD3_CLKGATE_SHIFT (31U) #define CCM_ANALOG_PFD_480_TOG_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD3_CLKGATE_MASK) +/*! @} */ /*! @name PFD_528 - 528MHz Clock (PLL2) Phase Fractional Divider Control Register */ +/*! @{ */ #define CCM_ANALOG_PFD_528_PFD0_FRAC_MASK (0x3FU) #define CCM_ANALOG_PFD_528_PFD0_FRAC_SHIFT (0U) #define CCM_ANALOG_PFD_528_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_PFD0_FRAC_MASK) @@ -4716,8 +6638,10 @@ typedef struct { #define CCM_ANALOG_PFD_528_PFD3_CLKGATE_MASK (0x80000000U) #define CCM_ANALOG_PFD_528_PFD3_CLKGATE_SHIFT (31U) #define CCM_ANALOG_PFD_528_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_PFD3_CLKGATE_MASK) +/*! @} */ /*! @name PFD_528_SET - 528MHz Clock (PLL2) Phase Fractional Divider Control Register */ +/*! @{ */ #define CCM_ANALOG_PFD_528_SET_PFD0_FRAC_MASK (0x3FU) #define CCM_ANALOG_PFD_528_SET_PFD0_FRAC_SHIFT (0U) #define CCM_ANALOG_PFD_528_SET_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD0_FRAC_MASK) @@ -4754,8 +6678,10 @@ typedef struct { #define CCM_ANALOG_PFD_528_SET_PFD3_CLKGATE_MASK (0x80000000U) #define CCM_ANALOG_PFD_528_SET_PFD3_CLKGATE_SHIFT (31U) #define CCM_ANALOG_PFD_528_SET_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD3_CLKGATE_MASK) +/*! @} */ /*! @name PFD_528_CLR - 528MHz Clock (PLL2) Phase Fractional Divider Control Register */ +/*! @{ */ #define CCM_ANALOG_PFD_528_CLR_PFD0_FRAC_MASK (0x3FU) #define CCM_ANALOG_PFD_528_CLR_PFD0_FRAC_SHIFT (0U) #define CCM_ANALOG_PFD_528_CLR_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD0_FRAC_MASK) @@ -4792,8 +6718,10 @@ typedef struct { #define CCM_ANALOG_PFD_528_CLR_PFD3_CLKGATE_MASK (0x80000000U) #define CCM_ANALOG_PFD_528_CLR_PFD3_CLKGATE_SHIFT (31U) #define CCM_ANALOG_PFD_528_CLR_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD3_CLKGATE_MASK) +/*! @} */ /*! @name PFD_528_TOG - 528MHz Clock (PLL2) Phase Fractional Divider Control Register */ +/*! @{ */ #define CCM_ANALOG_PFD_528_TOG_PFD0_FRAC_MASK (0x3FU) #define CCM_ANALOG_PFD_528_TOG_PFD0_FRAC_SHIFT (0U) #define CCM_ANALOG_PFD_528_TOG_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD0_FRAC_MASK) @@ -4830,28 +6758,60 @@ typedef struct { #define CCM_ANALOG_PFD_528_TOG_PFD3_CLKGATE_MASK (0x80000000U) #define CCM_ANALOG_PFD_528_TOG_PFD3_CLKGATE_SHIFT (31U) #define CCM_ANALOG_PFD_528_TOG_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD3_CLKGATE_MASK) +/*! @} */ /*! @name MISC0 - Miscellaneous Register 0 */ +/*! @{ */ #define CCM_ANALOG_MISC0_REFTOP_PWD_MASK (0x1U) #define CCM_ANALOG_MISC0_REFTOP_PWD_SHIFT (0U) #define CCM_ANALOG_MISC0_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_REFTOP_PWD_SHIFT)) & CCM_ANALOG_MISC0_REFTOP_PWD_MASK) #define CCM_ANALOG_MISC0_REFTOP_SELFBIASOFF_MASK (0x8U) #define CCM_ANALOG_MISC0_REFTOP_SELFBIASOFF_SHIFT (3U) +/*! REFTOP_SELFBIASOFF + * 0b0..Uses coarse bias currents for startup + * 0b1..Uses bandgap-based bias currents for best performance. + */ #define CCM_ANALOG_MISC0_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_REFTOP_SELFBIASOFF_SHIFT)) & CCM_ANALOG_MISC0_REFTOP_SELFBIASOFF_MASK) #define CCM_ANALOG_MISC0_REFTOP_VBGADJ_MASK (0x70U) #define CCM_ANALOG_MISC0_REFTOP_VBGADJ_SHIFT (4U) +/*! REFTOP_VBGADJ + * 0b000..Nominal VBG + * 0b001..VBG+0.78% + * 0b010..VBG+1.56% + * 0b011..VBG+2.34% + * 0b100..VBG-0.78% + * 0b101..VBG-1.56% + * 0b110..VBG-2.34% + * 0b111..VBG-3.12% + */ #define CCM_ANALOG_MISC0_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_REFTOP_VBGADJ_SHIFT)) & CCM_ANALOG_MISC0_REFTOP_VBGADJ_MASK) #define CCM_ANALOG_MISC0_REFTOP_VBGUP_MASK (0x80U) #define CCM_ANALOG_MISC0_REFTOP_VBGUP_SHIFT (7U) #define CCM_ANALOG_MISC0_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_REFTOP_VBGUP_SHIFT)) & CCM_ANALOG_MISC0_REFTOP_VBGUP_MASK) #define CCM_ANALOG_MISC0_STOP_MODE_CONFIG_MASK (0xC00U) #define CCM_ANALOG_MISC0_STOP_MODE_CONFIG_SHIFT (10U) +/*! STOP_MODE_CONFIG + * 0b00..All analog except rtc powered down on stop mode assertion. XtalOsc=on, RCOsc=off; + * 0b01..Certain analog functions such as certain regulators left up. XtalOsc=on, RCOsc=off; + * 0b10..XtalOsc=off, RCOsc=on, Old BG=on, New BG=off. + * 0b11..XtalOsc=off, RCOsc=on, Old BG=off, New BG=on. + */ #define CCM_ANALOG_MISC0_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_STOP_MODE_CONFIG_SHIFT)) & CCM_ANALOG_MISC0_STOP_MODE_CONFIG_MASK) #define CCM_ANALOG_MISC0_DISCON_HIGH_SNVS_MASK (0x1000U) #define CCM_ANALOG_MISC0_DISCON_HIGH_SNVS_SHIFT (12U) +/*! DISCON_HIGH_SNVS + * 0b0..Turn on the switch + * 0b1..Turn off the switch + */ #define CCM_ANALOG_MISC0_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_DISCON_HIGH_SNVS_SHIFT)) & CCM_ANALOG_MISC0_DISCON_HIGH_SNVS_MASK) #define CCM_ANALOG_MISC0_OSC_I_MASK (0x6000U) #define CCM_ANALOG_MISC0_OSC_I_SHIFT (13U) +/*! OSC_I + * 0b00..Nominal + * 0b01..Decrease current by 12.5% + * 0b10..Decrease current by 25.0% + * 0b11..Decrease current by 37.5% + */ #define CCM_ANALOG_MISC0_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_OSC_I_SHIFT)) & CCM_ANALOG_MISC0_OSC_I_MASK) #define CCM_ANALOG_MISC0_OSC_XTALOK_MASK (0x8000U) #define CCM_ANALOG_MISC0_OSC_XTALOK_SHIFT (15U) @@ -4861,41 +6821,88 @@ typedef struct { #define CCM_ANALOG_MISC0_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_OSC_XTALOK_EN_SHIFT)) & CCM_ANALOG_MISC0_OSC_XTALOK_EN_MASK) #define CCM_ANALOG_MISC0_CLKGATE_CTRL_MASK (0x2000000U) #define CCM_ANALOG_MISC0_CLKGATE_CTRL_SHIFT (25U) +/*! CLKGATE_CTRL + * 0b0..Allow the logic to automatically gate the clock when the XTAL is powered down. + * 0b1..Prevent the logic from ever gating off the clock. + */ #define CCM_ANALOG_MISC0_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLKGATE_CTRL_SHIFT)) & CCM_ANALOG_MISC0_CLKGATE_CTRL_MASK) #define CCM_ANALOG_MISC0_CLKGATE_DELAY_MASK (0x1C000000U) #define CCM_ANALOG_MISC0_CLKGATE_DELAY_SHIFT (26U) +/*! CLKGATE_DELAY + * 0b000..0.5ms + * 0b001..1.0ms + * 0b010..2.0ms + * 0b011..3.0ms + * 0b100..4.0ms + * 0b101..5.0ms + * 0b110..6.0ms + * 0b111..7.0ms + */ #define CCM_ANALOG_MISC0_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLKGATE_DELAY_SHIFT)) & CCM_ANALOG_MISC0_CLKGATE_DELAY_MASK) #define CCM_ANALOG_MISC0_RTC_XTAL_SOURCE_MASK (0x20000000U) #define CCM_ANALOG_MISC0_RTC_XTAL_SOURCE_SHIFT (29U) +/*! RTC_XTAL_SOURCE + * 0b0..Internal ring oscillator + * 0b1..RTC_XTAL + */ #define CCM_ANALOG_MISC0_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_RTC_XTAL_SOURCE_SHIFT)) & CCM_ANALOG_MISC0_RTC_XTAL_SOURCE_MASK) #define CCM_ANALOG_MISC0_XTAL_24M_PWD_MASK (0x40000000U) #define CCM_ANALOG_MISC0_XTAL_24M_PWD_SHIFT (30U) #define CCM_ANALOG_MISC0_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_XTAL_24M_PWD_SHIFT)) & CCM_ANALOG_MISC0_XTAL_24M_PWD_MASK) -#define CCM_ANALOG_MISC0_VID_PLL_PREDIV_MASK (0x80000000U) -#define CCM_ANALOG_MISC0_VID_PLL_PREDIV_SHIFT (31U) -#define CCM_ANALOG_MISC0_VID_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_VID_PLL_PREDIV_SHIFT)) & CCM_ANALOG_MISC0_VID_PLL_PREDIV_MASK) +/*! @} */ /*! @name MISC0_SET - Miscellaneous Register 0 */ +/*! @{ */ #define CCM_ANALOG_MISC0_SET_REFTOP_PWD_MASK (0x1U) #define CCM_ANALOG_MISC0_SET_REFTOP_PWD_SHIFT (0U) #define CCM_ANALOG_MISC0_SET_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_REFTOP_PWD_SHIFT)) & CCM_ANALOG_MISC0_SET_REFTOP_PWD_MASK) #define CCM_ANALOG_MISC0_SET_REFTOP_SELFBIASOFF_MASK (0x8U) #define CCM_ANALOG_MISC0_SET_REFTOP_SELFBIASOFF_SHIFT (3U) +/*! REFTOP_SELFBIASOFF + * 0b0..Uses coarse bias currents for startup + * 0b1..Uses bandgap-based bias currents for best performance. + */ #define CCM_ANALOG_MISC0_SET_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_REFTOP_SELFBIASOFF_SHIFT)) & CCM_ANALOG_MISC0_SET_REFTOP_SELFBIASOFF_MASK) #define CCM_ANALOG_MISC0_SET_REFTOP_VBGADJ_MASK (0x70U) #define CCM_ANALOG_MISC0_SET_REFTOP_VBGADJ_SHIFT (4U) +/*! REFTOP_VBGADJ + * 0b000..Nominal VBG + * 0b001..VBG+0.78% + * 0b010..VBG+1.56% + * 0b011..VBG+2.34% + * 0b100..VBG-0.78% + * 0b101..VBG-1.56% + * 0b110..VBG-2.34% + * 0b111..VBG-3.12% + */ #define CCM_ANALOG_MISC0_SET_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_REFTOP_VBGADJ_SHIFT)) & CCM_ANALOG_MISC0_SET_REFTOP_VBGADJ_MASK) #define CCM_ANALOG_MISC0_SET_REFTOP_VBGUP_MASK (0x80U) #define CCM_ANALOG_MISC0_SET_REFTOP_VBGUP_SHIFT (7U) #define CCM_ANALOG_MISC0_SET_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_REFTOP_VBGUP_SHIFT)) & CCM_ANALOG_MISC0_SET_REFTOP_VBGUP_MASK) #define CCM_ANALOG_MISC0_SET_STOP_MODE_CONFIG_MASK (0xC00U) #define CCM_ANALOG_MISC0_SET_STOP_MODE_CONFIG_SHIFT (10U) +/*! STOP_MODE_CONFIG + * 0b00..All analog except rtc powered down on stop mode assertion. XtalOsc=on, RCOsc=off; + * 0b01..Certain analog functions such as certain regulators left up. XtalOsc=on, RCOsc=off; + * 0b10..XtalOsc=off, RCOsc=on, Old BG=on, New BG=off. + * 0b11..XtalOsc=off, RCOsc=on, Old BG=off, New BG=on. + */ #define CCM_ANALOG_MISC0_SET_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_STOP_MODE_CONFIG_SHIFT)) & CCM_ANALOG_MISC0_SET_STOP_MODE_CONFIG_MASK) #define CCM_ANALOG_MISC0_SET_DISCON_HIGH_SNVS_MASK (0x1000U) #define CCM_ANALOG_MISC0_SET_DISCON_HIGH_SNVS_SHIFT (12U) +/*! DISCON_HIGH_SNVS + * 0b0..Turn on the switch + * 0b1..Turn off the switch + */ #define CCM_ANALOG_MISC0_SET_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_DISCON_HIGH_SNVS_SHIFT)) & CCM_ANALOG_MISC0_SET_DISCON_HIGH_SNVS_MASK) #define CCM_ANALOG_MISC0_SET_OSC_I_MASK (0x6000U) #define CCM_ANALOG_MISC0_SET_OSC_I_SHIFT (13U) +/*! OSC_I + * 0b00..Nominal + * 0b01..Decrease current by 12.5% + * 0b10..Decrease current by 25.0% + * 0b11..Decrease current by 37.5% + */ #define CCM_ANALOG_MISC0_SET_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_OSC_I_SHIFT)) & CCM_ANALOG_MISC0_SET_OSC_I_MASK) #define CCM_ANALOG_MISC0_SET_OSC_XTALOK_MASK (0x8000U) #define CCM_ANALOG_MISC0_SET_OSC_XTALOK_SHIFT (15U) @@ -4905,41 +6912,88 @@ typedef struct { #define CCM_ANALOG_MISC0_SET_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_OSC_XTALOK_EN_SHIFT)) & CCM_ANALOG_MISC0_SET_OSC_XTALOK_EN_MASK) #define CCM_ANALOG_MISC0_SET_CLKGATE_CTRL_MASK (0x2000000U) #define CCM_ANALOG_MISC0_SET_CLKGATE_CTRL_SHIFT (25U) +/*! CLKGATE_CTRL + * 0b0..Allow the logic to automatically gate the clock when the XTAL is powered down. + * 0b1..Prevent the logic from ever gating off the clock. + */ #define CCM_ANALOG_MISC0_SET_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_CLKGATE_CTRL_SHIFT)) & CCM_ANALOG_MISC0_SET_CLKGATE_CTRL_MASK) #define CCM_ANALOG_MISC0_SET_CLKGATE_DELAY_MASK (0x1C000000U) #define CCM_ANALOG_MISC0_SET_CLKGATE_DELAY_SHIFT (26U) +/*! CLKGATE_DELAY + * 0b000..0.5ms + * 0b001..1.0ms + * 0b010..2.0ms + * 0b011..3.0ms + * 0b100..4.0ms + * 0b101..5.0ms + * 0b110..6.0ms + * 0b111..7.0ms + */ #define CCM_ANALOG_MISC0_SET_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_CLKGATE_DELAY_SHIFT)) & CCM_ANALOG_MISC0_SET_CLKGATE_DELAY_MASK) #define CCM_ANALOG_MISC0_SET_RTC_XTAL_SOURCE_MASK (0x20000000U) #define CCM_ANALOG_MISC0_SET_RTC_XTAL_SOURCE_SHIFT (29U) +/*! RTC_XTAL_SOURCE + * 0b0..Internal ring oscillator + * 0b1..RTC_XTAL + */ #define CCM_ANALOG_MISC0_SET_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_RTC_XTAL_SOURCE_SHIFT)) & CCM_ANALOG_MISC0_SET_RTC_XTAL_SOURCE_MASK) #define CCM_ANALOG_MISC0_SET_XTAL_24M_PWD_MASK (0x40000000U) #define CCM_ANALOG_MISC0_SET_XTAL_24M_PWD_SHIFT (30U) #define CCM_ANALOG_MISC0_SET_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_XTAL_24M_PWD_SHIFT)) & CCM_ANALOG_MISC0_SET_XTAL_24M_PWD_MASK) -#define CCM_ANALOG_MISC0_SET_VID_PLL_PREDIV_MASK (0x80000000U) -#define CCM_ANALOG_MISC0_SET_VID_PLL_PREDIV_SHIFT (31U) -#define CCM_ANALOG_MISC0_SET_VID_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_VID_PLL_PREDIV_SHIFT)) & CCM_ANALOG_MISC0_SET_VID_PLL_PREDIV_MASK) +/*! @} */ /*! @name MISC0_CLR - Miscellaneous Register 0 */ +/*! @{ */ #define CCM_ANALOG_MISC0_CLR_REFTOP_PWD_MASK (0x1U) #define CCM_ANALOG_MISC0_CLR_REFTOP_PWD_SHIFT (0U) #define CCM_ANALOG_MISC0_CLR_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_REFTOP_PWD_SHIFT)) & CCM_ANALOG_MISC0_CLR_REFTOP_PWD_MASK) #define CCM_ANALOG_MISC0_CLR_REFTOP_SELFBIASOFF_MASK (0x8U) #define CCM_ANALOG_MISC0_CLR_REFTOP_SELFBIASOFF_SHIFT (3U) +/*! REFTOP_SELFBIASOFF + * 0b0..Uses coarse bias currents for startup + * 0b1..Uses bandgap-based bias currents for best performance. + */ #define CCM_ANALOG_MISC0_CLR_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_REFTOP_SELFBIASOFF_SHIFT)) & CCM_ANALOG_MISC0_CLR_REFTOP_SELFBIASOFF_MASK) #define CCM_ANALOG_MISC0_CLR_REFTOP_VBGADJ_MASK (0x70U) #define CCM_ANALOG_MISC0_CLR_REFTOP_VBGADJ_SHIFT (4U) +/*! REFTOP_VBGADJ + * 0b000..Nominal VBG + * 0b001..VBG+0.78% + * 0b010..VBG+1.56% + * 0b011..VBG+2.34% + * 0b100..VBG-0.78% + * 0b101..VBG-1.56% + * 0b110..VBG-2.34% + * 0b111..VBG-3.12% + */ #define CCM_ANALOG_MISC0_CLR_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_REFTOP_VBGADJ_SHIFT)) & CCM_ANALOG_MISC0_CLR_REFTOP_VBGADJ_MASK) #define CCM_ANALOG_MISC0_CLR_REFTOP_VBGUP_MASK (0x80U) #define CCM_ANALOG_MISC0_CLR_REFTOP_VBGUP_SHIFT (7U) #define CCM_ANALOG_MISC0_CLR_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_REFTOP_VBGUP_SHIFT)) & CCM_ANALOG_MISC0_CLR_REFTOP_VBGUP_MASK) #define CCM_ANALOG_MISC0_CLR_STOP_MODE_CONFIG_MASK (0xC00U) #define CCM_ANALOG_MISC0_CLR_STOP_MODE_CONFIG_SHIFT (10U) +/*! STOP_MODE_CONFIG + * 0b00..All analog except rtc powered down on stop mode assertion. XtalOsc=on, RCOsc=off; + * 0b01..Certain analog functions such as certain regulators left up. XtalOsc=on, RCOsc=off; + * 0b10..XtalOsc=off, RCOsc=on, Old BG=on, New BG=off. + * 0b11..XtalOsc=off, RCOsc=on, Old BG=off, New BG=on. + */ #define CCM_ANALOG_MISC0_CLR_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_STOP_MODE_CONFIG_SHIFT)) & CCM_ANALOG_MISC0_CLR_STOP_MODE_CONFIG_MASK) #define CCM_ANALOG_MISC0_CLR_DISCON_HIGH_SNVS_MASK (0x1000U) #define CCM_ANALOG_MISC0_CLR_DISCON_HIGH_SNVS_SHIFT (12U) +/*! DISCON_HIGH_SNVS + * 0b0..Turn on the switch + * 0b1..Turn off the switch + */ #define CCM_ANALOG_MISC0_CLR_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_DISCON_HIGH_SNVS_SHIFT)) & CCM_ANALOG_MISC0_CLR_DISCON_HIGH_SNVS_MASK) #define CCM_ANALOG_MISC0_CLR_OSC_I_MASK (0x6000U) #define CCM_ANALOG_MISC0_CLR_OSC_I_SHIFT (13U) +/*! OSC_I + * 0b00..Nominal + * 0b01..Decrease current by 12.5% + * 0b10..Decrease current by 25.0% + * 0b11..Decrease current by 37.5% + */ #define CCM_ANALOG_MISC0_CLR_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_OSC_I_SHIFT)) & CCM_ANALOG_MISC0_CLR_OSC_I_MASK) #define CCM_ANALOG_MISC0_CLR_OSC_XTALOK_MASK (0x8000U) #define CCM_ANALOG_MISC0_CLR_OSC_XTALOK_SHIFT (15U) @@ -4949,41 +7003,88 @@ typedef struct { #define CCM_ANALOG_MISC0_CLR_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_OSC_XTALOK_EN_SHIFT)) & CCM_ANALOG_MISC0_CLR_OSC_XTALOK_EN_MASK) #define CCM_ANALOG_MISC0_CLR_CLKGATE_CTRL_MASK (0x2000000U) #define CCM_ANALOG_MISC0_CLR_CLKGATE_CTRL_SHIFT (25U) +/*! CLKGATE_CTRL + * 0b0..Allow the logic to automatically gate the clock when the XTAL is powered down. + * 0b1..Prevent the logic from ever gating off the clock. + */ #define CCM_ANALOG_MISC0_CLR_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_CLKGATE_CTRL_SHIFT)) & CCM_ANALOG_MISC0_CLR_CLKGATE_CTRL_MASK) #define CCM_ANALOG_MISC0_CLR_CLKGATE_DELAY_MASK (0x1C000000U) #define CCM_ANALOG_MISC0_CLR_CLKGATE_DELAY_SHIFT (26U) +/*! CLKGATE_DELAY + * 0b000..0.5ms + * 0b001..1.0ms + * 0b010..2.0ms + * 0b011..3.0ms + * 0b100..4.0ms + * 0b101..5.0ms + * 0b110..6.0ms + * 0b111..7.0ms + */ #define CCM_ANALOG_MISC0_CLR_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_CLKGATE_DELAY_SHIFT)) & CCM_ANALOG_MISC0_CLR_CLKGATE_DELAY_MASK) #define CCM_ANALOG_MISC0_CLR_RTC_XTAL_SOURCE_MASK (0x20000000U) #define CCM_ANALOG_MISC0_CLR_RTC_XTAL_SOURCE_SHIFT (29U) +/*! RTC_XTAL_SOURCE + * 0b0..Internal ring oscillator + * 0b1..RTC_XTAL + */ #define CCM_ANALOG_MISC0_CLR_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_RTC_XTAL_SOURCE_SHIFT)) & CCM_ANALOG_MISC0_CLR_RTC_XTAL_SOURCE_MASK) #define CCM_ANALOG_MISC0_CLR_XTAL_24M_PWD_MASK (0x40000000U) #define CCM_ANALOG_MISC0_CLR_XTAL_24M_PWD_SHIFT (30U) #define CCM_ANALOG_MISC0_CLR_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_XTAL_24M_PWD_SHIFT)) & CCM_ANALOG_MISC0_CLR_XTAL_24M_PWD_MASK) -#define CCM_ANALOG_MISC0_CLR_VID_PLL_PREDIV_MASK (0x80000000U) -#define CCM_ANALOG_MISC0_CLR_VID_PLL_PREDIV_SHIFT (31U) -#define CCM_ANALOG_MISC0_CLR_VID_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_VID_PLL_PREDIV_SHIFT)) & CCM_ANALOG_MISC0_CLR_VID_PLL_PREDIV_MASK) +/*! @} */ /*! @name MISC0_TOG - Miscellaneous Register 0 */ +/*! @{ */ #define CCM_ANALOG_MISC0_TOG_REFTOP_PWD_MASK (0x1U) #define CCM_ANALOG_MISC0_TOG_REFTOP_PWD_SHIFT (0U) #define CCM_ANALOG_MISC0_TOG_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_REFTOP_PWD_SHIFT)) & CCM_ANALOG_MISC0_TOG_REFTOP_PWD_MASK) #define CCM_ANALOG_MISC0_TOG_REFTOP_SELFBIASOFF_MASK (0x8U) #define CCM_ANALOG_MISC0_TOG_REFTOP_SELFBIASOFF_SHIFT (3U) +/*! REFTOP_SELFBIASOFF + * 0b0..Uses coarse bias currents for startup + * 0b1..Uses bandgap-based bias currents for best performance. + */ #define CCM_ANALOG_MISC0_TOG_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_REFTOP_SELFBIASOFF_SHIFT)) & CCM_ANALOG_MISC0_TOG_REFTOP_SELFBIASOFF_MASK) #define CCM_ANALOG_MISC0_TOG_REFTOP_VBGADJ_MASK (0x70U) #define CCM_ANALOG_MISC0_TOG_REFTOP_VBGADJ_SHIFT (4U) +/*! REFTOP_VBGADJ + * 0b000..Nominal VBG + * 0b001..VBG+0.78% + * 0b010..VBG+1.56% + * 0b011..VBG+2.34% + * 0b100..VBG-0.78% + * 0b101..VBG-1.56% + * 0b110..VBG-2.34% + * 0b111..VBG-3.12% + */ #define CCM_ANALOG_MISC0_TOG_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_REFTOP_VBGADJ_SHIFT)) & CCM_ANALOG_MISC0_TOG_REFTOP_VBGADJ_MASK) #define CCM_ANALOG_MISC0_TOG_REFTOP_VBGUP_MASK (0x80U) #define CCM_ANALOG_MISC0_TOG_REFTOP_VBGUP_SHIFT (7U) #define CCM_ANALOG_MISC0_TOG_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_REFTOP_VBGUP_SHIFT)) & CCM_ANALOG_MISC0_TOG_REFTOP_VBGUP_MASK) #define CCM_ANALOG_MISC0_TOG_STOP_MODE_CONFIG_MASK (0xC00U) #define CCM_ANALOG_MISC0_TOG_STOP_MODE_CONFIG_SHIFT (10U) +/*! STOP_MODE_CONFIG + * 0b00..All analog except rtc powered down on stop mode assertion. XtalOsc=on, RCOsc=off; + * 0b01..Certain analog functions such as certain regulators left up. XtalOsc=on, RCOsc=off; + * 0b10..XtalOsc=off, RCOsc=on, Old BG=on, New BG=off. + * 0b11..XtalOsc=off, RCOsc=on, Old BG=off, New BG=on. + */ #define CCM_ANALOG_MISC0_TOG_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_STOP_MODE_CONFIG_SHIFT)) & CCM_ANALOG_MISC0_TOG_STOP_MODE_CONFIG_MASK) #define CCM_ANALOG_MISC0_TOG_DISCON_HIGH_SNVS_MASK (0x1000U) #define CCM_ANALOG_MISC0_TOG_DISCON_HIGH_SNVS_SHIFT (12U) +/*! DISCON_HIGH_SNVS + * 0b0..Turn on the switch + * 0b1..Turn off the switch + */ #define CCM_ANALOG_MISC0_TOG_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_DISCON_HIGH_SNVS_SHIFT)) & CCM_ANALOG_MISC0_TOG_DISCON_HIGH_SNVS_MASK) #define CCM_ANALOG_MISC0_TOG_OSC_I_MASK (0x6000U) #define CCM_ANALOG_MISC0_TOG_OSC_I_SHIFT (13U) +/*! OSC_I + * 0b00..Nominal + * 0b01..Decrease current by 12.5% + * 0b10..Decrease current by 25.0% + * 0b11..Decrease current by 37.5% + */ #define CCM_ANALOG_MISC0_TOG_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_OSC_I_SHIFT)) & CCM_ANALOG_MISC0_TOG_OSC_I_MASK) #define CCM_ANALOG_MISC0_TOG_OSC_XTALOK_MASK (0x8000U) #define CCM_ANALOG_MISC0_TOG_OSC_XTALOK_SHIFT (15U) @@ -4993,23 +7094,58 @@ typedef struct { #define CCM_ANALOG_MISC0_TOG_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_OSC_XTALOK_EN_SHIFT)) & CCM_ANALOG_MISC0_TOG_OSC_XTALOK_EN_MASK) #define CCM_ANALOG_MISC0_TOG_CLKGATE_CTRL_MASK (0x2000000U) #define CCM_ANALOG_MISC0_TOG_CLKGATE_CTRL_SHIFT (25U) +/*! CLKGATE_CTRL + * 0b0..Allow the logic to automatically gate the clock when the XTAL is powered down. + * 0b1..Prevent the logic from ever gating off the clock. + */ #define CCM_ANALOG_MISC0_TOG_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_CLKGATE_CTRL_SHIFT)) & CCM_ANALOG_MISC0_TOG_CLKGATE_CTRL_MASK) #define CCM_ANALOG_MISC0_TOG_CLKGATE_DELAY_MASK (0x1C000000U) #define CCM_ANALOG_MISC0_TOG_CLKGATE_DELAY_SHIFT (26U) +/*! CLKGATE_DELAY + * 0b000..0.5ms + * 0b001..1.0ms + * 0b010..2.0ms + * 0b011..3.0ms + * 0b100..4.0ms + * 0b101..5.0ms + * 0b110..6.0ms + * 0b111..7.0ms + */ #define CCM_ANALOG_MISC0_TOG_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_CLKGATE_DELAY_SHIFT)) & CCM_ANALOG_MISC0_TOG_CLKGATE_DELAY_MASK) #define CCM_ANALOG_MISC0_TOG_RTC_XTAL_SOURCE_MASK (0x20000000U) #define CCM_ANALOG_MISC0_TOG_RTC_XTAL_SOURCE_SHIFT (29U) +/*! RTC_XTAL_SOURCE + * 0b0..Internal ring oscillator + * 0b1..RTC_XTAL + */ #define CCM_ANALOG_MISC0_TOG_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_RTC_XTAL_SOURCE_SHIFT)) & CCM_ANALOG_MISC0_TOG_RTC_XTAL_SOURCE_MASK) #define CCM_ANALOG_MISC0_TOG_XTAL_24M_PWD_MASK (0x40000000U) #define CCM_ANALOG_MISC0_TOG_XTAL_24M_PWD_SHIFT (30U) #define CCM_ANALOG_MISC0_TOG_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_XTAL_24M_PWD_SHIFT)) & CCM_ANALOG_MISC0_TOG_XTAL_24M_PWD_MASK) -#define CCM_ANALOG_MISC0_TOG_VID_PLL_PREDIV_MASK (0x80000000U) -#define CCM_ANALOG_MISC0_TOG_VID_PLL_PREDIV_SHIFT (31U) -#define CCM_ANALOG_MISC0_TOG_VID_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_VID_PLL_PREDIV_SHIFT)) & CCM_ANALOG_MISC0_TOG_VID_PLL_PREDIV_MASK) +/*! @} */ /*! @name MISC1 - Miscellaneous Register 1 */ +/*! @{ */ #define CCM_ANALOG_MISC1_LVDS1_CLK_SEL_MASK (0x1FU) #define CCM_ANALOG_MISC1_LVDS1_CLK_SEL_SHIFT (0U) +/*! LVDS1_CLK_SEL + * 0b00000..Arm PLL + * 0b00001..System PLL + * 0b00010..ref_pfd4_clk == pll2_pfd0_clk + * 0b00011..ref_pfd5_clk == pll2_pfd1_clk + * 0b00100..ref_pfd6_clk == pll2_pfd2_clk + * 0b00101..ref_pfd7_clk == pll2_pfd3_clk + * 0b00110..Audio PLL + * 0b00111..Video PLL + * 0b01001..ethernet ref clock (ENET_PLL) + * 0b01100..USB1 PLL clock + * 0b01101..USB2 PLL clock + * 0b01110..ref_pfd0_clk == pll3_pfd0_clk + * 0b01111..ref_pfd1_clk == pll3_pfd1_clk + * 0b10000..ref_pfd2_clk == pll3_pfd2_clk + * 0b10001..ref_pfd3_clk == pll3_pfd3_clk + * 0b10010..xtal (24M) + */ #define CCM_ANALOG_MISC1_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_LVDS1_CLK_SEL_SHIFT)) & CCM_ANALOG_MISC1_LVDS1_CLK_SEL_MASK) #define CCM_ANALOG_MISC1_LVDSCLK1_OBEN_MASK (0x400U) #define CCM_ANALOG_MISC1_LVDSCLK1_OBEN_SHIFT (10U) @@ -5038,10 +7174,30 @@ typedef struct { #define CCM_ANALOG_MISC1_IRQ_DIG_BO_MASK (0x80000000U) #define CCM_ANALOG_MISC1_IRQ_DIG_BO_SHIFT (31U) #define CCM_ANALOG_MISC1_IRQ_DIG_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_IRQ_DIG_BO_SHIFT)) & CCM_ANALOG_MISC1_IRQ_DIG_BO_MASK) +/*! @} */ /*! @name MISC1_SET - Miscellaneous Register 1 */ +/*! @{ */ #define CCM_ANALOG_MISC1_SET_LVDS1_CLK_SEL_MASK (0x1FU) #define CCM_ANALOG_MISC1_SET_LVDS1_CLK_SEL_SHIFT (0U) +/*! LVDS1_CLK_SEL + * 0b00000..Arm PLL + * 0b00001..System PLL + * 0b00010..ref_pfd4_clk == pll2_pfd0_clk + * 0b00011..ref_pfd5_clk == pll2_pfd1_clk + * 0b00100..ref_pfd6_clk == pll2_pfd2_clk + * 0b00101..ref_pfd7_clk == pll2_pfd3_clk + * 0b00110..Audio PLL + * 0b00111..Video PLL + * 0b01001..ethernet ref clock (ENET_PLL) + * 0b01100..USB1 PLL clock + * 0b01101..USB2 PLL clock + * 0b01110..ref_pfd0_clk == pll3_pfd0_clk + * 0b01111..ref_pfd1_clk == pll3_pfd1_clk + * 0b10000..ref_pfd2_clk == pll3_pfd2_clk + * 0b10001..ref_pfd3_clk == pll3_pfd3_clk + * 0b10010..xtal (24M) + */ #define CCM_ANALOG_MISC1_SET_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_LVDS1_CLK_SEL_SHIFT)) & CCM_ANALOG_MISC1_SET_LVDS1_CLK_SEL_MASK) #define CCM_ANALOG_MISC1_SET_LVDSCLK1_OBEN_MASK (0x400U) #define CCM_ANALOG_MISC1_SET_LVDSCLK1_OBEN_SHIFT (10U) @@ -5070,10 +7226,30 @@ typedef struct { #define CCM_ANALOG_MISC1_SET_IRQ_DIG_BO_MASK (0x80000000U) #define CCM_ANALOG_MISC1_SET_IRQ_DIG_BO_SHIFT (31U) #define CCM_ANALOG_MISC1_SET_IRQ_DIG_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_IRQ_DIG_BO_SHIFT)) & CCM_ANALOG_MISC1_SET_IRQ_DIG_BO_MASK) +/*! @} */ /*! @name MISC1_CLR - Miscellaneous Register 1 */ +/*! @{ */ #define CCM_ANALOG_MISC1_CLR_LVDS1_CLK_SEL_MASK (0x1FU) #define CCM_ANALOG_MISC1_CLR_LVDS1_CLK_SEL_SHIFT (0U) +/*! LVDS1_CLK_SEL + * 0b00000..Arm PLL + * 0b00001..System PLL + * 0b00010..ref_pfd4_clk == pll2_pfd0_clk + * 0b00011..ref_pfd5_clk == pll2_pfd1_clk + * 0b00100..ref_pfd6_clk == pll2_pfd2_clk + * 0b00101..ref_pfd7_clk == pll2_pfd3_clk + * 0b00110..Audio PLL + * 0b00111..Video PLL + * 0b01001..ethernet ref clock (ENET_PLL) + * 0b01100..USB1 PLL clock + * 0b01101..USB2 PLL clock + * 0b01110..ref_pfd0_clk == pll3_pfd0_clk + * 0b01111..ref_pfd1_clk == pll3_pfd1_clk + * 0b10000..ref_pfd2_clk == pll3_pfd2_clk + * 0b10001..ref_pfd3_clk == pll3_pfd3_clk + * 0b10010..xtal (24M) + */ #define CCM_ANALOG_MISC1_CLR_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_LVDS1_CLK_SEL_SHIFT)) & CCM_ANALOG_MISC1_CLR_LVDS1_CLK_SEL_MASK) #define CCM_ANALOG_MISC1_CLR_LVDSCLK1_OBEN_MASK (0x400U) #define CCM_ANALOG_MISC1_CLR_LVDSCLK1_OBEN_SHIFT (10U) @@ -5102,10 +7278,30 @@ typedef struct { #define CCM_ANALOG_MISC1_CLR_IRQ_DIG_BO_MASK (0x80000000U) #define CCM_ANALOG_MISC1_CLR_IRQ_DIG_BO_SHIFT (31U) #define CCM_ANALOG_MISC1_CLR_IRQ_DIG_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_IRQ_DIG_BO_SHIFT)) & CCM_ANALOG_MISC1_CLR_IRQ_DIG_BO_MASK) +/*! @} */ /*! @name MISC1_TOG - Miscellaneous Register 1 */ +/*! @{ */ #define CCM_ANALOG_MISC1_TOG_LVDS1_CLK_SEL_MASK (0x1FU) #define CCM_ANALOG_MISC1_TOG_LVDS1_CLK_SEL_SHIFT (0U) +/*! LVDS1_CLK_SEL + * 0b00000..Arm PLL + * 0b00001..System PLL + * 0b00010..ref_pfd4_clk == pll2_pfd0_clk + * 0b00011..ref_pfd5_clk == pll2_pfd1_clk + * 0b00100..ref_pfd6_clk == pll2_pfd2_clk + * 0b00101..ref_pfd7_clk == pll2_pfd3_clk + * 0b00110..Audio PLL + * 0b00111..Video PLL + * 0b01001..ethernet ref clock (ENET_PLL) + * 0b01100..USB1 PLL clock + * 0b01101..USB2 PLL clock + * 0b01110..ref_pfd0_clk == pll3_pfd0_clk + * 0b01111..ref_pfd1_clk == pll3_pfd1_clk + * 0b10000..ref_pfd2_clk == pll3_pfd2_clk + * 0b10001..ref_pfd3_clk == pll3_pfd3_clk + * 0b10010..xtal (24M) + */ #define CCM_ANALOG_MISC1_TOG_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_LVDS1_CLK_SEL_SHIFT)) & CCM_ANALOG_MISC1_TOG_LVDS1_CLK_SEL_MASK) #define CCM_ANALOG_MISC1_TOG_LVDSCLK1_OBEN_MASK (0x400U) #define CCM_ANALOG_MISC1_TOG_LVDSCLK1_OBEN_SHIFT (10U) @@ -5134,13 +7330,22 @@ typedef struct { #define CCM_ANALOG_MISC1_TOG_IRQ_DIG_BO_MASK (0x80000000U) #define CCM_ANALOG_MISC1_TOG_IRQ_DIG_BO_SHIFT (31U) #define CCM_ANALOG_MISC1_TOG_IRQ_DIG_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_IRQ_DIG_BO_SHIFT)) & CCM_ANALOG_MISC1_TOG_IRQ_DIG_BO_MASK) +/*! @} */ /*! @name MISC2 - Miscellaneous Register 2 */ +/*! @{ */ #define CCM_ANALOG_MISC2_REG0_BO_OFFSET_MASK (0x7U) #define CCM_ANALOG_MISC2_REG0_BO_OFFSET_SHIFT (0U) +/*! REG0_BO_OFFSET + * 0b100..Brownout offset = 0.100V + * 0b111..Brownout offset = 0.175V + */ #define CCM_ANALOG_MISC2_REG0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG0_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_REG0_BO_OFFSET_MASK) #define CCM_ANALOG_MISC2_REG0_BO_STATUS_MASK (0x8U) #define CCM_ANALOG_MISC2_REG0_BO_STATUS_SHIFT (3U) +/*! REG0_BO_STATUS + * 0b1..Brownout, supply is below target minus brownout offset. + */ #define CCM_ANALOG_MISC2_REG0_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG0_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_REG0_BO_STATUS_MASK) #define CCM_ANALOG_MISC2_REG0_ENABLE_BO_MASK (0x20U) #define CCM_ANALOG_MISC2_REG0_ENABLE_BO_SHIFT (5U) @@ -5150,12 +7355,23 @@ typedef struct { #define CCM_ANALOG_MISC2_REG0_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG0_OK_SHIFT)) & CCM_ANALOG_MISC2_REG0_OK_MASK) #define CCM_ANALOG_MISC2_PLL3_disable_MASK (0x80U) #define CCM_ANALOG_MISC2_PLL3_disable_SHIFT (7U) +/*! PLL3_disable + * 0b0..PLL3 is being used by peripherals and is enabled when SoC is not in any low power mode + * 0b1..PLL3 can be disabled when the SoC is not in any low power mode + */ #define CCM_ANALOG_MISC2_PLL3_disable(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_PLL3_disable_SHIFT)) & CCM_ANALOG_MISC2_PLL3_disable_MASK) #define CCM_ANALOG_MISC2_REG1_BO_OFFSET_MASK (0x700U) #define CCM_ANALOG_MISC2_REG1_BO_OFFSET_SHIFT (8U) +/*! REG1_BO_OFFSET + * 0b100..Brownout offset = 0.100V + * 0b111..Brownout offset = 0.175V + */ #define CCM_ANALOG_MISC2_REG1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG1_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_REG1_BO_OFFSET_MASK) #define CCM_ANALOG_MISC2_REG1_BO_STATUS_MASK (0x800U) #define CCM_ANALOG_MISC2_REG1_BO_STATUS_SHIFT (11U) +/*! REG1_BO_STATUS + * 0b1..Brownout, supply is below target minus brownout offset. + */ #define CCM_ANALOG_MISC2_REG1_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG1_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_REG1_BO_STATUS_MASK) #define CCM_ANALOG_MISC2_REG1_ENABLE_BO_MASK (0x2000U) #define CCM_ANALOG_MISC2_REG1_ENABLE_BO_SHIFT (13U) @@ -5165,9 +7381,17 @@ typedef struct { #define CCM_ANALOG_MISC2_REG1_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG1_OK_SHIFT)) & CCM_ANALOG_MISC2_REG1_OK_MASK) #define CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK (0x8000U) #define CCM_ANALOG_MISC2_AUDIO_DIV_LSB_SHIFT (15U) +/*! AUDIO_DIV_LSB + * 0b0..divide by 1 (Default) + * 0b1..divide by 2 + */ #define CCM_ANALOG_MISC2_AUDIO_DIV_LSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_AUDIO_DIV_LSB_SHIFT)) & CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK) #define CCM_ANALOG_MISC2_REG2_BO_OFFSET_MASK (0x70000U) #define CCM_ANALOG_MISC2_REG2_BO_OFFSET_SHIFT (16U) +/*! REG2_BO_OFFSET + * 0b100..Brownout offset = 0.100V + * 0b111..Brownout offset = 0.175V + */ #define CCM_ANALOG_MISC2_REG2_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG2_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_REG2_BO_OFFSET_MASK) #define CCM_ANALOG_MISC2_REG2_BO_STATUS_MASK (0x80000U) #define CCM_ANALOG_MISC2_REG2_BO_STATUS_SHIFT (19U) @@ -5180,26 +7404,63 @@ typedef struct { #define CCM_ANALOG_MISC2_REG2_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG2_OK_SHIFT)) & CCM_ANALOG_MISC2_REG2_OK_MASK) #define CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK (0x800000U) #define CCM_ANALOG_MISC2_AUDIO_DIV_MSB_SHIFT (23U) +/*! AUDIO_DIV_MSB + * 0b0..divide by 1 (Default) + * 0b1..divide by 2 + */ #define CCM_ANALOG_MISC2_AUDIO_DIV_MSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_AUDIO_DIV_MSB_SHIFT)) & CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK) #define CCM_ANALOG_MISC2_REG0_STEP_TIME_MASK (0x3000000U) #define CCM_ANALOG_MISC2_REG0_STEP_TIME_SHIFT (24U) +/*! REG0_STEP_TIME + * 0b00..64 + * 0b01..128 + * 0b10..256 + * 0b11..512 + */ #define CCM_ANALOG_MISC2_REG0_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG0_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_REG0_STEP_TIME_MASK) #define CCM_ANALOG_MISC2_REG1_STEP_TIME_MASK (0xC000000U) #define CCM_ANALOG_MISC2_REG1_STEP_TIME_SHIFT (26U) +/*! REG1_STEP_TIME + * 0b00..64 + * 0b01..128 + * 0b10..256 + * 0b11..512 + */ #define CCM_ANALOG_MISC2_REG1_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG1_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_REG1_STEP_TIME_MASK) #define CCM_ANALOG_MISC2_REG2_STEP_TIME_MASK (0x30000000U) #define CCM_ANALOG_MISC2_REG2_STEP_TIME_SHIFT (28U) +/*! REG2_STEP_TIME + * 0b00..64 + * 0b01..128 + * 0b10..256 + * 0b11..512 + */ #define CCM_ANALOG_MISC2_REG2_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG2_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_REG2_STEP_TIME_MASK) #define CCM_ANALOG_MISC2_VIDEO_DIV_MASK (0xC0000000U) #define CCM_ANALOG_MISC2_VIDEO_DIV_SHIFT (30U) +/*! VIDEO_DIV + * 0b00..divide by 1 (Default) + * 0b01..divide by 2 + * 0b10..divide by 1 + * 0b11..divide by 4 + */ #define CCM_ANALOG_MISC2_VIDEO_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_VIDEO_DIV_SHIFT)) & CCM_ANALOG_MISC2_VIDEO_DIV_MASK) +/*! @} */ /*! @name MISC2_SET - Miscellaneous Register 2 */ +/*! @{ */ #define CCM_ANALOG_MISC2_SET_REG0_BO_OFFSET_MASK (0x7U) #define CCM_ANALOG_MISC2_SET_REG0_BO_OFFSET_SHIFT (0U) +/*! REG0_BO_OFFSET + * 0b100..Brownout offset = 0.100V + * 0b111..Brownout offset = 0.175V + */ #define CCM_ANALOG_MISC2_SET_REG0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG0_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_SET_REG0_BO_OFFSET_MASK) #define CCM_ANALOG_MISC2_SET_REG0_BO_STATUS_MASK (0x8U) #define CCM_ANALOG_MISC2_SET_REG0_BO_STATUS_SHIFT (3U) +/*! REG0_BO_STATUS + * 0b1..Brownout, supply is below target minus brownout offset. + */ #define CCM_ANALOG_MISC2_SET_REG0_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG0_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_SET_REG0_BO_STATUS_MASK) #define CCM_ANALOG_MISC2_SET_REG0_ENABLE_BO_MASK (0x20U) #define CCM_ANALOG_MISC2_SET_REG0_ENABLE_BO_SHIFT (5U) @@ -5209,12 +7470,23 @@ typedef struct { #define CCM_ANALOG_MISC2_SET_REG0_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG0_OK_SHIFT)) & CCM_ANALOG_MISC2_SET_REG0_OK_MASK) #define CCM_ANALOG_MISC2_SET_PLL3_disable_MASK (0x80U) #define CCM_ANALOG_MISC2_SET_PLL3_disable_SHIFT (7U) +/*! PLL3_disable + * 0b0..PLL3 is being used by peripherals and is enabled when SoC is not in any low power mode + * 0b1..PLL3 can be disabled when the SoC is not in any low power mode + */ #define CCM_ANALOG_MISC2_SET_PLL3_disable(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_PLL3_disable_SHIFT)) & CCM_ANALOG_MISC2_SET_PLL3_disable_MASK) #define CCM_ANALOG_MISC2_SET_REG1_BO_OFFSET_MASK (0x700U) #define CCM_ANALOG_MISC2_SET_REG1_BO_OFFSET_SHIFT (8U) +/*! REG1_BO_OFFSET + * 0b100..Brownout offset = 0.100V + * 0b111..Brownout offset = 0.175V + */ #define CCM_ANALOG_MISC2_SET_REG1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG1_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_SET_REG1_BO_OFFSET_MASK) #define CCM_ANALOG_MISC2_SET_REG1_BO_STATUS_MASK (0x800U) #define CCM_ANALOG_MISC2_SET_REG1_BO_STATUS_SHIFT (11U) +/*! REG1_BO_STATUS + * 0b1..Brownout, supply is below target minus brownout offset. + */ #define CCM_ANALOG_MISC2_SET_REG1_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG1_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_SET_REG1_BO_STATUS_MASK) #define CCM_ANALOG_MISC2_SET_REG1_ENABLE_BO_MASK (0x2000U) #define CCM_ANALOG_MISC2_SET_REG1_ENABLE_BO_SHIFT (13U) @@ -5224,9 +7496,17 @@ typedef struct { #define CCM_ANALOG_MISC2_SET_REG1_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG1_OK_SHIFT)) & CCM_ANALOG_MISC2_SET_REG1_OK_MASK) #define CCM_ANALOG_MISC2_SET_AUDIO_DIV_LSB_MASK (0x8000U) #define CCM_ANALOG_MISC2_SET_AUDIO_DIV_LSB_SHIFT (15U) +/*! AUDIO_DIV_LSB + * 0b0..divide by 1 (Default) + * 0b1..divide by 2 + */ #define CCM_ANALOG_MISC2_SET_AUDIO_DIV_LSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_AUDIO_DIV_LSB_SHIFT)) & CCM_ANALOG_MISC2_SET_AUDIO_DIV_LSB_MASK) #define CCM_ANALOG_MISC2_SET_REG2_BO_OFFSET_MASK (0x70000U) #define CCM_ANALOG_MISC2_SET_REG2_BO_OFFSET_SHIFT (16U) +/*! REG2_BO_OFFSET + * 0b100..Brownout offset = 0.100V + * 0b111..Brownout offset = 0.175V + */ #define CCM_ANALOG_MISC2_SET_REG2_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG2_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_SET_REG2_BO_OFFSET_MASK) #define CCM_ANALOG_MISC2_SET_REG2_BO_STATUS_MASK (0x80000U) #define CCM_ANALOG_MISC2_SET_REG2_BO_STATUS_SHIFT (19U) @@ -5239,26 +7519,63 @@ typedef struct { #define CCM_ANALOG_MISC2_SET_REG2_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG2_OK_SHIFT)) & CCM_ANALOG_MISC2_SET_REG2_OK_MASK) #define CCM_ANALOG_MISC2_SET_AUDIO_DIV_MSB_MASK (0x800000U) #define CCM_ANALOG_MISC2_SET_AUDIO_DIV_MSB_SHIFT (23U) +/*! AUDIO_DIV_MSB + * 0b0..divide by 1 (Default) + * 0b1..divide by 2 + */ #define CCM_ANALOG_MISC2_SET_AUDIO_DIV_MSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_AUDIO_DIV_MSB_SHIFT)) & CCM_ANALOG_MISC2_SET_AUDIO_DIV_MSB_MASK) #define CCM_ANALOG_MISC2_SET_REG0_STEP_TIME_MASK (0x3000000U) #define CCM_ANALOG_MISC2_SET_REG0_STEP_TIME_SHIFT (24U) +/*! REG0_STEP_TIME + * 0b00..64 + * 0b01..128 + * 0b10..256 + * 0b11..512 + */ #define CCM_ANALOG_MISC2_SET_REG0_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG0_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_SET_REG0_STEP_TIME_MASK) #define CCM_ANALOG_MISC2_SET_REG1_STEP_TIME_MASK (0xC000000U) #define CCM_ANALOG_MISC2_SET_REG1_STEP_TIME_SHIFT (26U) +/*! REG1_STEP_TIME + * 0b00..64 + * 0b01..128 + * 0b10..256 + * 0b11..512 + */ #define CCM_ANALOG_MISC2_SET_REG1_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG1_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_SET_REG1_STEP_TIME_MASK) #define CCM_ANALOG_MISC2_SET_REG2_STEP_TIME_MASK (0x30000000U) #define CCM_ANALOG_MISC2_SET_REG2_STEP_TIME_SHIFT (28U) +/*! REG2_STEP_TIME + * 0b00..64 + * 0b01..128 + * 0b10..256 + * 0b11..512 + */ #define CCM_ANALOG_MISC2_SET_REG2_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG2_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_SET_REG2_STEP_TIME_MASK) #define CCM_ANALOG_MISC2_SET_VIDEO_DIV_MASK (0xC0000000U) #define CCM_ANALOG_MISC2_SET_VIDEO_DIV_SHIFT (30U) +/*! VIDEO_DIV + * 0b00..divide by 1 (Default) + * 0b01..divide by 2 + * 0b10..divide by 1 + * 0b11..divide by 4 + */ #define CCM_ANALOG_MISC2_SET_VIDEO_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_VIDEO_DIV_SHIFT)) & CCM_ANALOG_MISC2_SET_VIDEO_DIV_MASK) +/*! @} */ /*! @name MISC2_CLR - Miscellaneous Register 2 */ +/*! @{ */ #define CCM_ANALOG_MISC2_CLR_REG0_BO_OFFSET_MASK (0x7U) #define CCM_ANALOG_MISC2_CLR_REG0_BO_OFFSET_SHIFT (0U) +/*! REG0_BO_OFFSET + * 0b100..Brownout offset = 0.100V + * 0b111..Brownout offset = 0.175V + */ #define CCM_ANALOG_MISC2_CLR_REG0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG0_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG0_BO_OFFSET_MASK) #define CCM_ANALOG_MISC2_CLR_REG0_BO_STATUS_MASK (0x8U) #define CCM_ANALOG_MISC2_CLR_REG0_BO_STATUS_SHIFT (3U) +/*! REG0_BO_STATUS + * 0b1..Brownout, supply is below target minus brownout offset. + */ #define CCM_ANALOG_MISC2_CLR_REG0_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG0_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG0_BO_STATUS_MASK) #define CCM_ANALOG_MISC2_CLR_REG0_ENABLE_BO_MASK (0x20U) #define CCM_ANALOG_MISC2_CLR_REG0_ENABLE_BO_SHIFT (5U) @@ -5268,12 +7585,23 @@ typedef struct { #define CCM_ANALOG_MISC2_CLR_REG0_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG0_OK_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG0_OK_MASK) #define CCM_ANALOG_MISC2_CLR_PLL3_disable_MASK (0x80U) #define CCM_ANALOG_MISC2_CLR_PLL3_disable_SHIFT (7U) +/*! PLL3_disable + * 0b0..PLL3 is being used by peripherals and is enabled when SoC is not in any low power mode + * 0b1..PLL3 can be disabled when the SoC is not in any low power mode + */ #define CCM_ANALOG_MISC2_CLR_PLL3_disable(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_PLL3_disable_SHIFT)) & CCM_ANALOG_MISC2_CLR_PLL3_disable_MASK) #define CCM_ANALOG_MISC2_CLR_REG1_BO_OFFSET_MASK (0x700U) #define CCM_ANALOG_MISC2_CLR_REG1_BO_OFFSET_SHIFT (8U) +/*! REG1_BO_OFFSET + * 0b100..Brownout offset = 0.100V + * 0b111..Brownout offset = 0.175V + */ #define CCM_ANALOG_MISC2_CLR_REG1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG1_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG1_BO_OFFSET_MASK) #define CCM_ANALOG_MISC2_CLR_REG1_BO_STATUS_MASK (0x800U) #define CCM_ANALOG_MISC2_CLR_REG1_BO_STATUS_SHIFT (11U) +/*! REG1_BO_STATUS + * 0b1..Brownout, supply is below target minus brownout offset. + */ #define CCM_ANALOG_MISC2_CLR_REG1_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG1_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG1_BO_STATUS_MASK) #define CCM_ANALOG_MISC2_CLR_REG1_ENABLE_BO_MASK (0x2000U) #define CCM_ANALOG_MISC2_CLR_REG1_ENABLE_BO_SHIFT (13U) @@ -5283,9 +7611,17 @@ typedef struct { #define CCM_ANALOG_MISC2_CLR_REG1_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG1_OK_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG1_OK_MASK) #define CCM_ANALOG_MISC2_CLR_AUDIO_DIV_LSB_MASK (0x8000U) #define CCM_ANALOG_MISC2_CLR_AUDIO_DIV_LSB_SHIFT (15U) +/*! AUDIO_DIV_LSB + * 0b0..divide by 1 (Default) + * 0b1..divide by 2 + */ #define CCM_ANALOG_MISC2_CLR_AUDIO_DIV_LSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_AUDIO_DIV_LSB_SHIFT)) & CCM_ANALOG_MISC2_CLR_AUDIO_DIV_LSB_MASK) #define CCM_ANALOG_MISC2_CLR_REG2_BO_OFFSET_MASK (0x70000U) #define CCM_ANALOG_MISC2_CLR_REG2_BO_OFFSET_SHIFT (16U) +/*! REG2_BO_OFFSET + * 0b100..Brownout offset = 0.100V + * 0b111..Brownout offset = 0.175V + */ #define CCM_ANALOG_MISC2_CLR_REG2_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG2_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG2_BO_OFFSET_MASK) #define CCM_ANALOG_MISC2_CLR_REG2_BO_STATUS_MASK (0x80000U) #define CCM_ANALOG_MISC2_CLR_REG2_BO_STATUS_SHIFT (19U) @@ -5298,26 +7634,63 @@ typedef struct { #define CCM_ANALOG_MISC2_CLR_REG2_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG2_OK_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG2_OK_MASK) #define CCM_ANALOG_MISC2_CLR_AUDIO_DIV_MSB_MASK (0x800000U) #define CCM_ANALOG_MISC2_CLR_AUDIO_DIV_MSB_SHIFT (23U) +/*! AUDIO_DIV_MSB + * 0b0..divide by 1 (Default) + * 0b1..divide by 2 + */ #define CCM_ANALOG_MISC2_CLR_AUDIO_DIV_MSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_AUDIO_DIV_MSB_SHIFT)) & CCM_ANALOG_MISC2_CLR_AUDIO_DIV_MSB_MASK) #define CCM_ANALOG_MISC2_CLR_REG0_STEP_TIME_MASK (0x3000000U) #define CCM_ANALOG_MISC2_CLR_REG0_STEP_TIME_SHIFT (24U) +/*! REG0_STEP_TIME + * 0b00..64 + * 0b01..128 + * 0b10..256 + * 0b11..512 + */ #define CCM_ANALOG_MISC2_CLR_REG0_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG0_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG0_STEP_TIME_MASK) #define CCM_ANALOG_MISC2_CLR_REG1_STEP_TIME_MASK (0xC000000U) #define CCM_ANALOG_MISC2_CLR_REG1_STEP_TIME_SHIFT (26U) +/*! REG1_STEP_TIME + * 0b00..64 + * 0b01..128 + * 0b10..256 + * 0b11..512 + */ #define CCM_ANALOG_MISC2_CLR_REG1_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG1_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG1_STEP_TIME_MASK) #define CCM_ANALOG_MISC2_CLR_REG2_STEP_TIME_MASK (0x30000000U) #define CCM_ANALOG_MISC2_CLR_REG2_STEP_TIME_SHIFT (28U) +/*! REG2_STEP_TIME + * 0b00..64 + * 0b01..128 + * 0b10..256 + * 0b11..512 + */ #define CCM_ANALOG_MISC2_CLR_REG2_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG2_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG2_STEP_TIME_MASK) #define CCM_ANALOG_MISC2_CLR_VIDEO_DIV_MASK (0xC0000000U) #define CCM_ANALOG_MISC2_CLR_VIDEO_DIV_SHIFT (30U) +/*! VIDEO_DIV + * 0b00..divide by 1 (Default) + * 0b01..divide by 2 + * 0b10..divide by 1 + * 0b11..divide by 4 + */ #define CCM_ANALOG_MISC2_CLR_VIDEO_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_VIDEO_DIV_SHIFT)) & CCM_ANALOG_MISC2_CLR_VIDEO_DIV_MASK) +/*! @} */ /*! @name MISC2_TOG - Miscellaneous Register 2 */ +/*! @{ */ #define CCM_ANALOG_MISC2_TOG_REG0_BO_OFFSET_MASK (0x7U) #define CCM_ANALOG_MISC2_TOG_REG0_BO_OFFSET_SHIFT (0U) +/*! REG0_BO_OFFSET + * 0b100..Brownout offset = 0.100V + * 0b111..Brownout offset = 0.175V + */ #define CCM_ANALOG_MISC2_TOG_REG0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG0_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG0_BO_OFFSET_MASK) #define CCM_ANALOG_MISC2_TOG_REG0_BO_STATUS_MASK (0x8U) #define CCM_ANALOG_MISC2_TOG_REG0_BO_STATUS_SHIFT (3U) +/*! REG0_BO_STATUS + * 0b1..Brownout, supply is below target minus brownout offset. + */ #define CCM_ANALOG_MISC2_TOG_REG0_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG0_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG0_BO_STATUS_MASK) #define CCM_ANALOG_MISC2_TOG_REG0_ENABLE_BO_MASK (0x20U) #define CCM_ANALOG_MISC2_TOG_REG0_ENABLE_BO_SHIFT (5U) @@ -5327,12 +7700,23 @@ typedef struct { #define CCM_ANALOG_MISC2_TOG_REG0_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG0_OK_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG0_OK_MASK) #define CCM_ANALOG_MISC2_TOG_PLL3_disable_MASK (0x80U) #define CCM_ANALOG_MISC2_TOG_PLL3_disable_SHIFT (7U) +/*! PLL3_disable + * 0b0..PLL3 is being used by peripherals and is enabled when SoC is not in any low power mode + * 0b1..PLL3 can be disabled when the SoC is not in any low power mode + */ #define CCM_ANALOG_MISC2_TOG_PLL3_disable(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_PLL3_disable_SHIFT)) & CCM_ANALOG_MISC2_TOG_PLL3_disable_MASK) #define CCM_ANALOG_MISC2_TOG_REG1_BO_OFFSET_MASK (0x700U) #define CCM_ANALOG_MISC2_TOG_REG1_BO_OFFSET_SHIFT (8U) +/*! REG1_BO_OFFSET + * 0b100..Brownout offset = 0.100V + * 0b111..Brownout offset = 0.175V + */ #define CCM_ANALOG_MISC2_TOG_REG1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG1_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG1_BO_OFFSET_MASK) #define CCM_ANALOG_MISC2_TOG_REG1_BO_STATUS_MASK (0x800U) #define CCM_ANALOG_MISC2_TOG_REG1_BO_STATUS_SHIFT (11U) +/*! REG1_BO_STATUS + * 0b1..Brownout, supply is below target minus brownout offset. + */ #define CCM_ANALOG_MISC2_TOG_REG1_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG1_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG1_BO_STATUS_MASK) #define CCM_ANALOG_MISC2_TOG_REG1_ENABLE_BO_MASK (0x2000U) #define CCM_ANALOG_MISC2_TOG_REG1_ENABLE_BO_SHIFT (13U) @@ -5342,9 +7726,17 @@ typedef struct { #define CCM_ANALOG_MISC2_TOG_REG1_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG1_OK_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG1_OK_MASK) #define CCM_ANALOG_MISC2_TOG_AUDIO_DIV_LSB_MASK (0x8000U) #define CCM_ANALOG_MISC2_TOG_AUDIO_DIV_LSB_SHIFT (15U) +/*! AUDIO_DIV_LSB + * 0b0..divide by 1 (Default) + * 0b1..divide by 2 + */ #define CCM_ANALOG_MISC2_TOG_AUDIO_DIV_LSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_AUDIO_DIV_LSB_SHIFT)) & CCM_ANALOG_MISC2_TOG_AUDIO_DIV_LSB_MASK) #define CCM_ANALOG_MISC2_TOG_REG2_BO_OFFSET_MASK (0x70000U) #define CCM_ANALOG_MISC2_TOG_REG2_BO_OFFSET_SHIFT (16U) +/*! REG2_BO_OFFSET + * 0b100..Brownout offset = 0.100V + * 0b111..Brownout offset = 0.175V + */ #define CCM_ANALOG_MISC2_TOG_REG2_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG2_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG2_BO_OFFSET_MASK) #define CCM_ANALOG_MISC2_TOG_REG2_BO_STATUS_MASK (0x80000U) #define CCM_ANALOG_MISC2_TOG_REG2_BO_STATUS_SHIFT (19U) @@ -5357,19 +7749,48 @@ typedef struct { #define CCM_ANALOG_MISC2_TOG_REG2_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG2_OK_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG2_OK_MASK) #define CCM_ANALOG_MISC2_TOG_AUDIO_DIV_MSB_MASK (0x800000U) #define CCM_ANALOG_MISC2_TOG_AUDIO_DIV_MSB_SHIFT (23U) +/*! AUDIO_DIV_MSB + * 0b0..divide by 1 (Default) + * 0b1..divide by 2 + */ #define CCM_ANALOG_MISC2_TOG_AUDIO_DIV_MSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_AUDIO_DIV_MSB_SHIFT)) & CCM_ANALOG_MISC2_TOG_AUDIO_DIV_MSB_MASK) #define CCM_ANALOG_MISC2_TOG_REG0_STEP_TIME_MASK (0x3000000U) #define CCM_ANALOG_MISC2_TOG_REG0_STEP_TIME_SHIFT (24U) +/*! REG0_STEP_TIME + * 0b00..64 + * 0b01..128 + * 0b10..256 + * 0b11..512 + */ #define CCM_ANALOG_MISC2_TOG_REG0_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG0_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG0_STEP_TIME_MASK) #define CCM_ANALOG_MISC2_TOG_REG1_STEP_TIME_MASK (0xC000000U) #define CCM_ANALOG_MISC2_TOG_REG1_STEP_TIME_SHIFT (26U) +/*! REG1_STEP_TIME + * 0b00..64 + * 0b01..128 + * 0b10..256 + * 0b11..512 + */ #define CCM_ANALOG_MISC2_TOG_REG1_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG1_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG1_STEP_TIME_MASK) #define CCM_ANALOG_MISC2_TOG_REG2_STEP_TIME_MASK (0x30000000U) #define CCM_ANALOG_MISC2_TOG_REG2_STEP_TIME_SHIFT (28U) +/*! REG2_STEP_TIME + * 0b00..64 + * 0b01..128 + * 0b10..256 + * 0b11..512 + */ #define CCM_ANALOG_MISC2_TOG_REG2_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG2_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG2_STEP_TIME_MASK) #define CCM_ANALOG_MISC2_TOG_VIDEO_DIV_MASK (0xC0000000U) #define CCM_ANALOG_MISC2_TOG_VIDEO_DIV_SHIFT (30U) +/*! VIDEO_DIV + * 0b00..divide by 1 (Default) + * 0b01..divide by 2 + * 0b10..divide by 1 + * 0b11..divide by 4 + */ #define CCM_ANALOG_MISC2_TOG_VIDEO_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_VIDEO_DIV_SHIFT)) & CCM_ANALOG_MISC2_TOG_VIDEO_DIV_MASK) +/*! @} */ /*! @@ -5421,79 +7842,183 @@ typedef struct { */ /*! @name CR0 - CMP Control Register 0 */ +/*! @{ */ #define CMP_CR0_HYSTCTR_MASK (0x3U) #define CMP_CR0_HYSTCTR_SHIFT (0U) +/*! HYSTCTR - Comparator hard block hysteresis control + * 0b00..Level 0 + * 0b01..Level 1 + * 0b10..Level 2 + * 0b11..Level 3 + */ #define CMP_CR0_HYSTCTR(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR0_HYSTCTR_SHIFT)) & CMP_CR0_HYSTCTR_MASK) #define CMP_CR0_FILTER_CNT_MASK (0x70U) #define CMP_CR0_FILTER_CNT_SHIFT (4U) +/*! FILTER_CNT - Filter Sample Count + * 0b000..Filter is disabled. If SE = 1, then COUT is a logic 0. This is not a legal state, and is not recommended. If SE = 0, COUT = COUTA. + * 0b001..One sample must agree. The comparator output is simply sampled. + * 0b010..2 consecutive samples must agree. + * 0b011..3 consecutive samples must agree. + * 0b100..4 consecutive samples must agree. + * 0b101..5 consecutive samples must agree. + * 0b110..6 consecutive samples must agree. + * 0b111..7 consecutive samples must agree. + */ #define CMP_CR0_FILTER_CNT(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR0_FILTER_CNT_SHIFT)) & CMP_CR0_FILTER_CNT_MASK) +/*! @} */ /*! @name CR1 - CMP Control Register 1 */ +/*! @{ */ #define CMP_CR1_EN_MASK (0x1U) #define CMP_CR1_EN_SHIFT (0U) +/*! EN - Comparator Module Enable + * 0b0..Analog Comparator is disabled. + * 0b1..Analog Comparator is enabled. + */ #define CMP_CR1_EN(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_EN_SHIFT)) & CMP_CR1_EN_MASK) #define CMP_CR1_OPE_MASK (0x2U) #define CMP_CR1_OPE_SHIFT (1U) +/*! OPE - Comparator Output Pin Enable + * 0b0..CMPO is not available on the associated CMPO output pin. If the comparator does not own the pin, this field has no effect. + * 0b1..CMPO is available on the associated CMPO output pin. The comparator output (CMPO) is driven out on the associated CMPO output pin if the comparator owns the pin. If the comparator does not own the field, this bit has no effect. + */ #define CMP_CR1_OPE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_OPE_SHIFT)) & CMP_CR1_OPE_MASK) #define CMP_CR1_COS_MASK (0x4U) #define CMP_CR1_COS_SHIFT (2U) +/*! COS - Comparator Output Select + * 0b0..Set the filtered comparator output (CMPO) to equal COUT. + * 0b1..Set the unfiltered comparator output (CMPO) to equal COUTA. + */ #define CMP_CR1_COS(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_COS_SHIFT)) & CMP_CR1_COS_MASK) #define CMP_CR1_INV_MASK (0x8U) #define CMP_CR1_INV_SHIFT (3U) +/*! INV - Comparator INVERT + * 0b0..Does not invert the comparator output. + * 0b1..Inverts the comparator output. + */ #define CMP_CR1_INV(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_INV_SHIFT)) & CMP_CR1_INV_MASK) #define CMP_CR1_PMODE_MASK (0x10U) #define CMP_CR1_PMODE_SHIFT (4U) +/*! PMODE - Power Mode Select + * 0b0..Low-Speed (LS) Comparison mode selected. In this mode, CMP has slower output propagation delay and lower current consumption. + * 0b1..High-Speed (HS) Comparison mode selected. In this mode, CMP has faster output propagation delay and higher current consumption. + */ #define CMP_CR1_PMODE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_PMODE_SHIFT)) & CMP_CR1_PMODE_MASK) #define CMP_CR1_WE_MASK (0x40U) #define CMP_CR1_WE_SHIFT (6U) +/*! WE - Windowing Enable + * 0b0..Windowing mode is not selected. + * 0b1..Windowing mode is selected. + */ #define CMP_CR1_WE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_WE_SHIFT)) & CMP_CR1_WE_MASK) #define CMP_CR1_SE_MASK (0x80U) #define CMP_CR1_SE_SHIFT (7U) +/*! SE - Sample Enable + * 0b0..Sampling mode is not selected. + * 0b1..Sampling mode is selected. + */ #define CMP_CR1_SE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_SE_SHIFT)) & CMP_CR1_SE_MASK) +/*! @} */ /*! @name FPR - CMP Filter Period Register */ +/*! @{ */ #define CMP_FPR_FILT_PER_MASK (0xFFU) #define CMP_FPR_FILT_PER_SHIFT (0U) #define CMP_FPR_FILT_PER(x) (((uint8_t)(((uint8_t)(x)) << CMP_FPR_FILT_PER_SHIFT)) & CMP_FPR_FILT_PER_MASK) +/*! @} */ /*! @name SCR - CMP Status and Control Register */ +/*! @{ */ #define CMP_SCR_COUT_MASK (0x1U) #define CMP_SCR_COUT_SHIFT (0U) #define CMP_SCR_COUT(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_COUT_SHIFT)) & CMP_SCR_COUT_MASK) #define CMP_SCR_CFF_MASK (0x2U) #define CMP_SCR_CFF_SHIFT (1U) +/*! CFF - Analog Comparator Flag Falling + * 0b0..Falling-edge on COUT has not been detected. + * 0b1..Falling-edge on COUT has occurred. + */ #define CMP_SCR_CFF(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFF_SHIFT)) & CMP_SCR_CFF_MASK) #define CMP_SCR_CFR_MASK (0x4U) #define CMP_SCR_CFR_SHIFT (2U) +/*! CFR - Analog Comparator Flag Rising + * 0b0..Rising-edge on COUT has not been detected. + * 0b1..Rising-edge on COUT has occurred. + */ #define CMP_SCR_CFR(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFR_SHIFT)) & CMP_SCR_CFR_MASK) #define CMP_SCR_IEF_MASK (0x8U) #define CMP_SCR_IEF_SHIFT (3U) +/*! IEF - Comparator Interrupt Enable Falling + * 0b0..Interrupt is disabled. + * 0b1..Interrupt is enabled. + */ #define CMP_SCR_IEF(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_IEF_SHIFT)) & CMP_SCR_IEF_MASK) #define CMP_SCR_IER_MASK (0x10U) #define CMP_SCR_IER_SHIFT (4U) +/*! IER - Comparator Interrupt Enable Rising + * 0b0..Interrupt is disabled. + * 0b1..Interrupt is enabled. + */ #define CMP_SCR_IER(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_IER_SHIFT)) & CMP_SCR_IER_MASK) #define CMP_SCR_DMAEN_MASK (0x40U) #define CMP_SCR_DMAEN_SHIFT (6U) +/*! DMAEN - DMA Enable Control + * 0b0..DMA is disabled. + * 0b1..DMA is enabled. + */ #define CMP_SCR_DMAEN(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_DMAEN_SHIFT)) & CMP_SCR_DMAEN_MASK) +/*! @} */ /*! @name DACCR - DAC Control Register */ +/*! @{ */ #define CMP_DACCR_VOSEL_MASK (0x3FU) #define CMP_DACCR_VOSEL_SHIFT (0U) #define CMP_DACCR_VOSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_VOSEL_SHIFT)) & CMP_DACCR_VOSEL_MASK) #define CMP_DACCR_VRSEL_MASK (0x40U) #define CMP_DACCR_VRSEL_SHIFT (6U) +/*! VRSEL - Supply Voltage Reference Source Select + * 0b0..Vin1 is selected as resistor ladder network supply reference. + * 0b1..Vin2 is selected as resistor ladder network supply reference. + */ #define CMP_DACCR_VRSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_VRSEL_SHIFT)) & CMP_DACCR_VRSEL_MASK) #define CMP_DACCR_DACEN_MASK (0x80U) #define CMP_DACCR_DACEN_SHIFT (7U) +/*! DACEN - DAC Enable + * 0b0..DAC is disabled. + * 0b1..DAC is enabled. + */ #define CMP_DACCR_DACEN(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_DACEN_SHIFT)) & CMP_DACCR_DACEN_MASK) +/*! @} */ /*! @name MUXCR - MUX Control Register */ +/*! @{ */ #define CMP_MUXCR_MSEL_MASK (0x7U) #define CMP_MUXCR_MSEL_SHIFT (0U) +/*! MSEL - Minus Input Mux Control + * 0b000..IN0 + * 0b001..IN1 + * 0b010..IN2 + * 0b011..IN3 + * 0b100..IN4 + * 0b101..IN5 + * 0b110..IN6 + * 0b111..IN7 + */ #define CMP_MUXCR_MSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_MSEL_SHIFT)) & CMP_MUXCR_MSEL_MASK) #define CMP_MUXCR_PSEL_MASK (0x38U) #define CMP_MUXCR_PSEL_SHIFT (3U) +/*! PSEL - Plus Input Mux Control + * 0b000..IN0 + * 0b001..IN1 + * 0b010..IN2 + * 0b011..IN3 + * 0b100..IN4 + * 0b101..IN5 + * 0b110..IN6 + * 0b111..IN7 + */ #define CMP_MUXCR_PSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_PSEL_SHIFT)) & CMP_MUXCR_PSEL_MASK) +/*! @} */ /*! @@ -5570,20 +8095,41 @@ typedef struct { */ /*! @name CSICR1 - CSI Control Register 1 */ +/*! @{ */ #define CSI_CSICR1_PIXEL_BIT_MASK (0x1U) #define CSI_CSICR1_PIXEL_BIT_SHIFT (0U) +/*! PIXEL_BIT + * 0b0..8-bit data for each pixel + * 0b1..10-bit data for each pixel + */ #define CSI_CSICR1_PIXEL_BIT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_PIXEL_BIT_SHIFT)) & CSI_CSICR1_PIXEL_BIT_MASK) #define CSI_CSICR1_REDGE_MASK (0x2U) #define CSI_CSICR1_REDGE_SHIFT (1U) +/*! REDGE + * 0b0..Pixel data is latched at the falling edge of CSI_PIXCLK + * 0b1..Pixel data is latched at the rising edge of CSI_PIXCLK + */ #define CSI_CSICR1_REDGE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_REDGE_SHIFT)) & CSI_CSICR1_REDGE_MASK) #define CSI_CSICR1_INV_PCLK_MASK (0x4U) #define CSI_CSICR1_INV_PCLK_SHIFT (2U) +/*! INV_PCLK + * 0b0..CSI_PIXCLK is directly applied to internal circuitry + * 0b1..CSI_PIXCLK is inverted before applied to internal circuitry + */ #define CSI_CSICR1_INV_PCLK(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_INV_PCLK_SHIFT)) & CSI_CSICR1_INV_PCLK_MASK) #define CSI_CSICR1_INV_DATA_MASK (0x8U) #define CSI_CSICR1_INV_DATA_SHIFT (3U) +/*! INV_DATA + * 0b0..CSI_D[7:0] data lines are directly applied to internal circuitry + * 0b1..CSI_D[7:0] data lines are inverted before applied to internal circuitry + */ #define CSI_CSICR1_INV_DATA(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_INV_DATA_SHIFT)) & CSI_CSICR1_INV_DATA_MASK) #define CSI_CSICR1_GCLK_MODE_MASK (0x10U) #define CSI_CSICR1_GCLK_MODE_SHIFT (4U) +/*! GCLK_MODE + * 0b0..Non-gated clock mode. All incoming pixel clocks are valid. HSYNC is ignored. + * 0b1..Gated clock mode. Pixel clock signal is valid only when HSYNC is active. + */ #define CSI_CSICR1_GCLK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_GCLK_MODE_SHIFT)) & CSI_CSICR1_GCLK_MODE_MASK) #define CSI_CSICR1_CLR_RXFIFO_MASK (0x20U) #define CSI_CSICR1_CLR_RXFIFO_SHIFT (5U) @@ -5593,63 +8139,141 @@ typedef struct { #define CSI_CSICR1_CLR_STATFIFO(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_CLR_STATFIFO_SHIFT)) & CSI_CSICR1_CLR_STATFIFO_MASK) #define CSI_CSICR1_PACK_DIR_MASK (0x80U) #define CSI_CSICR1_PACK_DIR_SHIFT (7U) +/*! PACK_DIR + * 0b0..Pack from LSB first. For image data, 0x11, 0x22, 0x33, 0x44, it will appear as 0x44332211 in RX FIFO. For stat data, 0xAAAA, 0xBBBB, it will appear as 0xBBBBAAAA in STAT FIFO. + * 0b1..Pack from MSB first. For image data, 0x11, 0x22, 0x33, 0x44, it will appear as 0x11223344 in RX FIFO. For stat data, 0xAAAA, 0xBBBB, it will appear as 0xAAAABBBB in STAT FIFO. + */ #define CSI_CSICR1_PACK_DIR(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_PACK_DIR_SHIFT)) & CSI_CSICR1_PACK_DIR_MASK) #define CSI_CSICR1_FCC_MASK (0x100U) #define CSI_CSICR1_FCC_SHIFT (8U) +/*! FCC + * 0b0..Asynchronous FIFO clear is selected. + * 0b1..Synchronous FIFO clear is selected. + */ #define CSI_CSICR1_FCC(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_FCC_SHIFT)) & CSI_CSICR1_FCC_MASK) #define CSI_CSICR1_CCIR_EN_MASK (0x400U) #define CSI_CSICR1_CCIR_EN_SHIFT (10U) +/*! CCIR_EN + * 0b0..Traditional interface is selected. Timing interface logic is used to latch data. + * 0b1..CCIR656 interface is selected. + */ #define CSI_CSICR1_CCIR_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_CCIR_EN_SHIFT)) & CSI_CSICR1_CCIR_EN_MASK) #define CSI_CSICR1_HSYNC_POL_MASK (0x800U) #define CSI_CSICR1_HSYNC_POL_SHIFT (11U) +/*! HSYNC_POL + * 0b0..HSYNC is active low + * 0b1..HSYNC is active high + */ #define CSI_CSICR1_HSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_HSYNC_POL_SHIFT)) & CSI_CSICR1_HSYNC_POL_MASK) #define CSI_CSICR1_SOF_INTEN_MASK (0x10000U) #define CSI_CSICR1_SOF_INTEN_SHIFT (16U) +/*! SOF_INTEN + * 0b0..SOF interrupt disable + * 0b1..SOF interrupt enable + */ #define CSI_CSICR1_SOF_INTEN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_SOF_INTEN_SHIFT)) & CSI_CSICR1_SOF_INTEN_MASK) #define CSI_CSICR1_SOF_POL_MASK (0x20000U) #define CSI_CSICR1_SOF_POL_SHIFT (17U) +/*! SOF_POL + * 0b0..SOF interrupt is generated on SOF falling edge + * 0b1..SOF interrupt is generated on SOF rising edge + */ #define CSI_CSICR1_SOF_POL(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_SOF_POL_SHIFT)) & CSI_CSICR1_SOF_POL_MASK) #define CSI_CSICR1_RXFF_INTEN_MASK (0x40000U) #define CSI_CSICR1_RXFF_INTEN_SHIFT (18U) +/*! RXFF_INTEN + * 0b0..RxFIFO full interrupt disable + * 0b1..RxFIFO full interrupt enable + */ #define CSI_CSICR1_RXFF_INTEN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_RXFF_INTEN_SHIFT)) & CSI_CSICR1_RXFF_INTEN_MASK) #define CSI_CSICR1_FB1_DMA_DONE_INTEN_MASK (0x80000U) #define CSI_CSICR1_FB1_DMA_DONE_INTEN_SHIFT (19U) +/*! FB1_DMA_DONE_INTEN + * 0b0..Frame Buffer1 DMA Transfer Done interrupt disable + * 0b1..Frame Buffer1 DMA Transfer Done interrupt enable + */ #define CSI_CSICR1_FB1_DMA_DONE_INTEN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_FB1_DMA_DONE_INTEN_SHIFT)) & CSI_CSICR1_FB1_DMA_DONE_INTEN_MASK) #define CSI_CSICR1_FB2_DMA_DONE_INTEN_MASK (0x100000U) #define CSI_CSICR1_FB2_DMA_DONE_INTEN_SHIFT (20U) +/*! FB2_DMA_DONE_INTEN + * 0b0..Frame Buffer2 DMA Transfer Done interrupt disable + * 0b1..Frame Buffer2 DMA Transfer Done interrupt enable + */ #define CSI_CSICR1_FB2_DMA_DONE_INTEN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_FB2_DMA_DONE_INTEN_SHIFT)) & CSI_CSICR1_FB2_DMA_DONE_INTEN_MASK) #define CSI_CSICR1_STATFF_INTEN_MASK (0x200000U) #define CSI_CSICR1_STATFF_INTEN_SHIFT (21U) +/*! STATFF_INTEN + * 0b0..STATFIFO full interrupt disable + * 0b1..STATFIFO full interrupt enable + */ #define CSI_CSICR1_STATFF_INTEN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_STATFF_INTEN_SHIFT)) & CSI_CSICR1_STATFF_INTEN_MASK) #define CSI_CSICR1_SFF_DMA_DONE_INTEN_MASK (0x400000U) #define CSI_CSICR1_SFF_DMA_DONE_INTEN_SHIFT (22U) +/*! SFF_DMA_DONE_INTEN + * 0b0..STATFIFO DMA Transfer Done interrupt disable + * 0b1..STATFIFO DMA Transfer Done interrupt enable + */ #define CSI_CSICR1_SFF_DMA_DONE_INTEN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_SFF_DMA_DONE_INTEN_SHIFT)) & CSI_CSICR1_SFF_DMA_DONE_INTEN_MASK) #define CSI_CSICR1_RF_OR_INTEN_MASK (0x1000000U) #define CSI_CSICR1_RF_OR_INTEN_SHIFT (24U) +/*! RF_OR_INTEN + * 0b0..RxFIFO overrun interrupt is disabled + * 0b1..RxFIFO overrun interrupt is enabled + */ #define CSI_CSICR1_RF_OR_INTEN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_RF_OR_INTEN_SHIFT)) & CSI_CSICR1_RF_OR_INTEN_MASK) #define CSI_CSICR1_SF_OR_INTEN_MASK (0x2000000U) #define CSI_CSICR1_SF_OR_INTEN_SHIFT (25U) +/*! SF_OR_INTEN + * 0b0..STATFIFO overrun interrupt is disabled + * 0b1..STATFIFO overrun interrupt is enabled + */ #define CSI_CSICR1_SF_OR_INTEN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_SF_OR_INTEN_SHIFT)) & CSI_CSICR1_SF_OR_INTEN_MASK) #define CSI_CSICR1_COF_INT_EN_MASK (0x4000000U) #define CSI_CSICR1_COF_INT_EN_SHIFT (26U) +/*! COF_INT_EN + * 0b0..COF interrupt is disabled + * 0b1..COF interrupt is enabled + */ #define CSI_CSICR1_COF_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_COF_INT_EN_SHIFT)) & CSI_CSICR1_COF_INT_EN_MASK) #define CSI_CSICR1_CCIR_MODE_MASK (0x8000000U) #define CSI_CSICR1_CCIR_MODE_SHIFT (27U) +/*! CCIR_MODE + * 0b0..Progressive mode is selected + * 0b1..Interlace mode is selected + */ #define CSI_CSICR1_CCIR_MODE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_CCIR_MODE_SHIFT)) & CSI_CSICR1_CCIR_MODE_MASK) #define CSI_CSICR1_PrP_IF_EN_MASK (0x10000000U) #define CSI_CSICR1_PrP_IF_EN_SHIFT (28U) +/*! PrP_IF_EN + * 0b0..CSI to PrP bus is disabled + * 0b1..CSI to PrP bus is enabled + */ #define CSI_CSICR1_PrP_IF_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_PrP_IF_EN_SHIFT)) & CSI_CSICR1_PrP_IF_EN_MASK) #define CSI_CSICR1_EOF_INT_EN_MASK (0x20000000U) #define CSI_CSICR1_EOF_INT_EN_SHIFT (29U) +/*! EOF_INT_EN + * 0b0..EOF interrupt is disabled. + * 0b1..EOF interrupt is generated when RX count value is reached. + */ #define CSI_CSICR1_EOF_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_EOF_INT_EN_SHIFT)) & CSI_CSICR1_EOF_INT_EN_MASK) #define CSI_CSICR1_EXT_VSYNC_MASK (0x40000000U) #define CSI_CSICR1_EXT_VSYNC_SHIFT (30U) +/*! EXT_VSYNC + * 0b0..Internal VSYNC mode + * 0b1..External VSYNC mode + */ #define CSI_CSICR1_EXT_VSYNC(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_EXT_VSYNC_SHIFT)) & CSI_CSICR1_EXT_VSYNC_MASK) #define CSI_CSICR1_SWAP16_EN_MASK (0x80000000U) #define CSI_CSICR1_SWAP16_EN_SHIFT (31U) +/*! SWAP16_EN + * 0b0..Disable swapping + * 0b1..Enable swapping + */ #define CSI_CSICR1_SWAP16_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_SWAP16_EN_SHIFT)) & CSI_CSICR1_SWAP16_EN_MASK) +/*! @} */ /*! @name CSICR2 - CSI Control Register 2 */ +/*! @{ */ #define CSI_CSICR2_HSC_MASK (0xFFU) #define CSI_CSICR2_HSC_SHIFT (0U) #define CSI_CSICR2_HSC(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR2_HSC_SHIFT)) & CSI_CSICR2_HSC_MASK) @@ -5658,127 +8282,295 @@ typedef struct { #define CSI_CSICR2_VSC(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR2_VSC_SHIFT)) & CSI_CSICR2_VSC_MASK) #define CSI_CSICR2_LVRM_MASK (0x70000U) #define CSI_CSICR2_LVRM_SHIFT (16U) +/*! LVRM + * 0b000..512 x 384 + * 0b001..448 x 336 + * 0b010..384 x 288 + * 0b011..384 x 256 + * 0b100..320 x 240 + * 0b101..288 x 216 + * 0b110..400 x 300 + */ #define CSI_CSICR2_LVRM(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR2_LVRM_SHIFT)) & CSI_CSICR2_LVRM_MASK) #define CSI_CSICR2_BTS_MASK (0x180000U) #define CSI_CSICR2_BTS_SHIFT (19U) +/*! BTS + * 0b00..GR + * 0b01..RG + * 0b10..BG + * 0b11..GB + */ #define CSI_CSICR2_BTS(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR2_BTS_SHIFT)) & CSI_CSICR2_BTS_MASK) #define CSI_CSICR2_SCE_MASK (0x800000U) #define CSI_CSICR2_SCE_SHIFT (23U) +/*! SCE + * 0b0..Skip count disable + * 0b1..Skip count enable + */ #define CSI_CSICR2_SCE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR2_SCE_SHIFT)) & CSI_CSICR2_SCE_MASK) #define CSI_CSICR2_AFS_MASK (0x3000000U) #define CSI_CSICR2_AFS_SHIFT (24U) +/*! AFS + * 0b00..Abs Diff on consecutive green pixels + * 0b01..Abs Diff on every third green pixels + * 0b1x..Abs Diff on every four green pixels + */ #define CSI_CSICR2_AFS(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR2_AFS_SHIFT)) & CSI_CSICR2_AFS_MASK) #define CSI_CSICR2_DRM_MASK (0x4000000U) #define CSI_CSICR2_DRM_SHIFT (26U) +/*! DRM + * 0b0..Stats grid of 8 x 6 + * 0b1..Stats grid of 8 x 12 + */ #define CSI_CSICR2_DRM(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR2_DRM_SHIFT)) & CSI_CSICR2_DRM_MASK) #define CSI_CSICR2_DMA_BURST_TYPE_SFF_MASK (0x30000000U) #define CSI_CSICR2_DMA_BURST_TYPE_SFF_SHIFT (28U) +/*! DMA_BURST_TYPE_SFF + * 0bx0..INCR8 + * 0b01..INCR4 + * 0b11..INCR16 + */ #define CSI_CSICR2_DMA_BURST_TYPE_SFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR2_DMA_BURST_TYPE_SFF_SHIFT)) & CSI_CSICR2_DMA_BURST_TYPE_SFF_MASK) #define CSI_CSICR2_DMA_BURST_TYPE_RFF_MASK (0xC0000000U) #define CSI_CSICR2_DMA_BURST_TYPE_RFF_SHIFT (30U) +/*! DMA_BURST_TYPE_RFF + * 0bx0..INCR8 + * 0b01..INCR4 + * 0b11..INCR16 + */ #define CSI_CSICR2_DMA_BURST_TYPE_RFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR2_DMA_BURST_TYPE_RFF_SHIFT)) & CSI_CSICR2_DMA_BURST_TYPE_RFF_MASK) +/*! @} */ /*! @name CSICR3 - CSI Control Register 3 */ +/*! @{ */ #define CSI_CSICR3_ECC_AUTO_EN_MASK (0x1U) #define CSI_CSICR3_ECC_AUTO_EN_SHIFT (0U) +/*! ECC_AUTO_EN + * 0b0..Auto Error correction is disabled. + * 0b1..Auto Error correction is enabled. + */ #define CSI_CSICR3_ECC_AUTO_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_ECC_AUTO_EN_SHIFT)) & CSI_CSICR3_ECC_AUTO_EN_MASK) #define CSI_CSICR3_ECC_INT_EN_MASK (0x2U) #define CSI_CSICR3_ECC_INT_EN_SHIFT (1U) +/*! ECC_INT_EN + * 0b0..No interrupt is generated when error is detected. Only the status bit ECC_INT is set. + * 0b1..Interrupt is generated when error is detected. + */ #define CSI_CSICR3_ECC_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_ECC_INT_EN_SHIFT)) & CSI_CSICR3_ECC_INT_EN_MASK) #define CSI_CSICR3_ZERO_PACK_EN_MASK (0x4U) #define CSI_CSICR3_ZERO_PACK_EN_SHIFT (2U) +/*! ZERO_PACK_EN + * 0b0..Zero packing disabled + * 0b1..Zero packing enabled + */ #define CSI_CSICR3_ZERO_PACK_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_ZERO_PACK_EN_SHIFT)) & CSI_CSICR3_ZERO_PACK_EN_MASK) #define CSI_CSICR3_TWO_8BIT_SENSOR_MASK (0x8U) #define CSI_CSICR3_TWO_8BIT_SENSOR_SHIFT (3U) +/*! TWO_8BIT_SENSOR + * 0b0..Only one sensor is connected. + * 0b1..Two 8-bit sensors are connected or one 16-bit sensor is connected. + */ #define CSI_CSICR3_TWO_8BIT_SENSOR(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_TWO_8BIT_SENSOR_SHIFT)) & CSI_CSICR3_TWO_8BIT_SENSOR_MASK) #define CSI_CSICR3_RxFF_LEVEL_MASK (0x70U) #define CSI_CSICR3_RxFF_LEVEL_SHIFT (4U) +/*! RxFF_LEVEL + * 0b000..4 Double words + * 0b001..8 Double words + * 0b010..16 Double words + * 0b011..24 Double words + * 0b100..32 Double words + * 0b101..48 Double words + * 0b110..64 Double words + * 0b111..96 Double words + */ #define CSI_CSICR3_RxFF_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_RxFF_LEVEL_SHIFT)) & CSI_CSICR3_RxFF_LEVEL_MASK) #define CSI_CSICR3_HRESP_ERR_EN_MASK (0x80U) #define CSI_CSICR3_HRESP_ERR_EN_SHIFT (7U) +/*! HRESP_ERR_EN + * 0b0..Disable hresponse error interrupt + * 0b1..Enable hresponse error interrupt + */ #define CSI_CSICR3_HRESP_ERR_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_HRESP_ERR_EN_SHIFT)) & CSI_CSICR3_HRESP_ERR_EN_MASK) #define CSI_CSICR3_STATFF_LEVEL_MASK (0x700U) #define CSI_CSICR3_STATFF_LEVEL_SHIFT (8U) +/*! STATFF_LEVEL + * 0b000..4 Double words + * 0b001..8 Double words + * 0b010..12 Double words + * 0b011..16 Double words + * 0b100..24 Double words + * 0b101..32 Double words + * 0b110..48 Double words + * 0b111..64 Double words + */ #define CSI_CSICR3_STATFF_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_STATFF_LEVEL_SHIFT)) & CSI_CSICR3_STATFF_LEVEL_MASK) #define CSI_CSICR3_DMA_REQ_EN_SFF_MASK (0x800U) #define CSI_CSICR3_DMA_REQ_EN_SFF_SHIFT (11U) +/*! DMA_REQ_EN_SFF + * 0b0..Disable the dma request + * 0b1..Enable the dma request + */ #define CSI_CSICR3_DMA_REQ_EN_SFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_DMA_REQ_EN_SFF_SHIFT)) & CSI_CSICR3_DMA_REQ_EN_SFF_MASK) #define CSI_CSICR3_DMA_REQ_EN_RFF_MASK (0x1000U) #define CSI_CSICR3_DMA_REQ_EN_RFF_SHIFT (12U) +/*! DMA_REQ_EN_RFF + * 0b0..Disable the dma request + * 0b1..Enable the dma request + */ #define CSI_CSICR3_DMA_REQ_EN_RFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_DMA_REQ_EN_RFF_SHIFT)) & CSI_CSICR3_DMA_REQ_EN_RFF_MASK) #define CSI_CSICR3_DMA_REFLASH_SFF_MASK (0x2000U) #define CSI_CSICR3_DMA_REFLASH_SFF_SHIFT (13U) +/*! DMA_REFLASH_SFF + * 0b0..No reflashing + * 0b1..Reflash the embedded DMA controller + */ #define CSI_CSICR3_DMA_REFLASH_SFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_DMA_REFLASH_SFF_SHIFT)) & CSI_CSICR3_DMA_REFLASH_SFF_MASK) #define CSI_CSICR3_DMA_REFLASH_RFF_MASK (0x4000U) #define CSI_CSICR3_DMA_REFLASH_RFF_SHIFT (14U) +/*! DMA_REFLASH_RFF + * 0b0..No reflashing + * 0b1..Reflash the embedded DMA controller + */ #define CSI_CSICR3_DMA_REFLASH_RFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_DMA_REFLASH_RFF_SHIFT)) & CSI_CSICR3_DMA_REFLASH_RFF_MASK) #define CSI_CSICR3_FRMCNT_RST_MASK (0x8000U) #define CSI_CSICR3_FRMCNT_RST_SHIFT (15U) +/*! FRMCNT_RST + * 0b0..Do not reset + * 0b1..Reset frame counter immediately + */ #define CSI_CSICR3_FRMCNT_RST(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_FRMCNT_RST_SHIFT)) & CSI_CSICR3_FRMCNT_RST_MASK) #define CSI_CSICR3_FRMCNT_MASK (0xFFFF0000U) #define CSI_CSICR3_FRMCNT_SHIFT (16U) #define CSI_CSICR3_FRMCNT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_FRMCNT_SHIFT)) & CSI_CSICR3_FRMCNT_MASK) +/*! @} */ /*! @name CSISTATFIFO - CSI Statistic FIFO Register */ +/*! @{ */ #define CSI_CSISTATFIFO_STAT_MASK (0xFFFFFFFFU) #define CSI_CSISTATFIFO_STAT_SHIFT (0U) #define CSI_CSISTATFIFO_STAT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISTATFIFO_STAT_SHIFT)) & CSI_CSISTATFIFO_STAT_MASK) +/*! @} */ /*! @name CSIRFIFO - CSI RX FIFO Register */ +/*! @{ */ #define CSI_CSIRFIFO_IMAGE_MASK (0xFFFFFFFFU) #define CSI_CSIRFIFO_IMAGE_SHIFT (0U) #define CSI_CSIRFIFO_IMAGE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSIRFIFO_IMAGE_SHIFT)) & CSI_CSIRFIFO_IMAGE_MASK) +/*! @} */ /*! @name CSIRXCNT - CSI RX Count Register */ +/*! @{ */ #define CSI_CSIRXCNT_RXCNT_MASK (0x3FFFFFU) #define CSI_CSIRXCNT_RXCNT_SHIFT (0U) #define CSI_CSIRXCNT_RXCNT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSIRXCNT_RXCNT_SHIFT)) & CSI_CSIRXCNT_RXCNT_MASK) +/*! @} */ /*! @name CSISR - CSI Status Register */ +/*! @{ */ #define CSI_CSISR_DRDY_MASK (0x1U) #define CSI_CSISR_DRDY_SHIFT (0U) +/*! DRDY + * 0b0..No data (word) is ready + * 0b1..At least 1 datum (word) is ready in RXFIFO. + */ #define CSI_CSISR_DRDY(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_DRDY_SHIFT)) & CSI_CSISR_DRDY_MASK) #define CSI_CSISR_ECC_INT_MASK (0x2U) #define CSI_CSISR_ECC_INT_SHIFT (1U) +/*! ECC_INT + * 0b0..No error detected + * 0b1..Error is detected in CCIR coding + */ #define CSI_CSISR_ECC_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_ECC_INT_SHIFT)) & CSI_CSISR_ECC_INT_MASK) #define CSI_CSISR_HRESP_ERR_INT_MASK (0x80U) #define CSI_CSISR_HRESP_ERR_INT_SHIFT (7U) +/*! HRESP_ERR_INT + * 0b0..No hresponse error. + * 0b1..Hresponse error is detected. + */ #define CSI_CSISR_HRESP_ERR_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_HRESP_ERR_INT_SHIFT)) & CSI_CSISR_HRESP_ERR_INT_MASK) #define CSI_CSISR_COF_INT_MASK (0x2000U) #define CSI_CSISR_COF_INT_SHIFT (13U) +/*! COF_INT + * 0b0..Video field has no change. + * 0b1..Change of video field is detected. + */ #define CSI_CSISR_COF_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_COF_INT_SHIFT)) & CSI_CSISR_COF_INT_MASK) #define CSI_CSISR_F1_INT_MASK (0x4000U) #define CSI_CSISR_F1_INT_SHIFT (14U) +/*! F1_INT + * 0b0..Field 1 of video is not detected. + * 0b1..Field 1 of video is about to start. + */ #define CSI_CSISR_F1_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_F1_INT_SHIFT)) & CSI_CSISR_F1_INT_MASK) #define CSI_CSISR_F2_INT_MASK (0x8000U) #define CSI_CSISR_F2_INT_SHIFT (15U) +/*! F2_INT + * 0b0..Field 2 of video is not detected + * 0b1..Field 2 of video is about to start + */ #define CSI_CSISR_F2_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_F2_INT_SHIFT)) & CSI_CSISR_F2_INT_MASK) #define CSI_CSISR_SOF_INT_MASK (0x10000U) #define CSI_CSISR_SOF_INT_SHIFT (16U) +/*! SOF_INT + * 0b0..SOF is not detected. + * 0b1..SOF is detected. + */ #define CSI_CSISR_SOF_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_SOF_INT_SHIFT)) & CSI_CSISR_SOF_INT_MASK) #define CSI_CSISR_EOF_INT_MASK (0x20000U) #define CSI_CSISR_EOF_INT_SHIFT (17U) +/*! EOF_INT + * 0b0..EOF is not detected. + * 0b1..EOF is detected. + */ #define CSI_CSISR_EOF_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_EOF_INT_SHIFT)) & CSI_CSISR_EOF_INT_MASK) #define CSI_CSISR_RxFF_INT_MASK (0x40000U) #define CSI_CSISR_RxFF_INT_SHIFT (18U) +/*! RxFF_INT + * 0b0..RxFIFO is not full. + * 0b1..RxFIFO is full. + */ #define CSI_CSISR_RxFF_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_RxFF_INT_SHIFT)) & CSI_CSISR_RxFF_INT_MASK) #define CSI_CSISR_DMA_TSF_DONE_FB1_MASK (0x80000U) #define CSI_CSISR_DMA_TSF_DONE_FB1_SHIFT (19U) +/*! DMA_TSF_DONE_FB1 + * 0b0..DMA transfer is not completed. + * 0b1..DMA transfer is completed. + */ #define CSI_CSISR_DMA_TSF_DONE_FB1(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_DMA_TSF_DONE_FB1_SHIFT)) & CSI_CSISR_DMA_TSF_DONE_FB1_MASK) #define CSI_CSISR_DMA_TSF_DONE_FB2_MASK (0x100000U) #define CSI_CSISR_DMA_TSF_DONE_FB2_SHIFT (20U) +/*! DMA_TSF_DONE_FB2 + * 0b0..DMA transfer is not completed. + * 0b1..DMA transfer is completed. + */ #define CSI_CSISR_DMA_TSF_DONE_FB2(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_DMA_TSF_DONE_FB2_SHIFT)) & CSI_CSISR_DMA_TSF_DONE_FB2_MASK) #define CSI_CSISR_STATFF_INT_MASK (0x200000U) #define CSI_CSISR_STATFF_INT_SHIFT (21U) +/*! STATFF_INT + * 0b0..STATFIFO is not full. + * 0b1..STATFIFO is full. + */ #define CSI_CSISR_STATFF_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_STATFF_INT_SHIFT)) & CSI_CSISR_STATFF_INT_MASK) #define CSI_CSISR_DMA_TSF_DONE_SFF_MASK (0x400000U) #define CSI_CSISR_DMA_TSF_DONE_SFF_SHIFT (22U) +/*! DMA_TSF_DONE_SFF + * 0b0..DMA transfer is not completed. + * 0b1..DMA transfer is completed. + */ #define CSI_CSISR_DMA_TSF_DONE_SFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_DMA_TSF_DONE_SFF_SHIFT)) & CSI_CSISR_DMA_TSF_DONE_SFF_MASK) #define CSI_CSISR_RF_OR_INT_MASK (0x1000000U) #define CSI_CSISR_RF_OR_INT_SHIFT (24U) +/*! RF_OR_INT + * 0b0..RXFIFO has not overflowed. + * 0b1..RXFIFO has overflowed. + */ #define CSI_CSISR_RF_OR_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_RF_OR_INT_SHIFT)) & CSI_CSISR_RF_OR_INT_MASK) #define CSI_CSISR_SF_OR_INT_MASK (0x2000000U) #define CSI_CSISR_SF_OR_INT_SHIFT (25U) +/*! SF_OR_INT + * 0b0..STATFIFO has not overflowed. + * 0b1..STATFIFO has overflowed. + */ #define CSI_CSISR_SF_OR_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_SF_OR_INT_SHIFT)) & CSI_CSISR_SF_OR_INT_MASK) #define CSI_CSISR_DMA_FIELD1_DONE_MASK (0x4000000U) #define CSI_CSISR_DMA_FIELD1_DONE_SHIFT (26U) @@ -5789,46 +8581,64 @@ typedef struct { #define CSI_CSISR_BASEADDR_CHHANGE_ERROR_MASK (0x10000000U) #define CSI_CSISR_BASEADDR_CHHANGE_ERROR_SHIFT (28U) #define CSI_CSISR_BASEADDR_CHHANGE_ERROR(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_BASEADDR_CHHANGE_ERROR_SHIFT)) & CSI_CSISR_BASEADDR_CHHANGE_ERROR_MASK) +/*! @} */ /*! @name CSIDMASA_STATFIFO - CSI DMA Start Address Register - for STATFIFO */ +/*! @{ */ #define CSI_CSIDMASA_STATFIFO_DMA_START_ADDR_SFF_MASK (0xFFFFFFFCU) #define CSI_CSIDMASA_STATFIFO_DMA_START_ADDR_SFF_SHIFT (2U) #define CSI_CSIDMASA_STATFIFO_DMA_START_ADDR_SFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSIDMASA_STATFIFO_DMA_START_ADDR_SFF_SHIFT)) & CSI_CSIDMASA_STATFIFO_DMA_START_ADDR_SFF_MASK) +/*! @} */ /*! @name CSIDMATS_STATFIFO - CSI DMA Transfer Size Register - for STATFIFO */ +/*! @{ */ #define CSI_CSIDMATS_STATFIFO_DMA_TSF_SIZE_SFF_MASK (0xFFFFFFFFU) #define CSI_CSIDMATS_STATFIFO_DMA_TSF_SIZE_SFF_SHIFT (0U) #define CSI_CSIDMATS_STATFIFO_DMA_TSF_SIZE_SFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSIDMATS_STATFIFO_DMA_TSF_SIZE_SFF_SHIFT)) & CSI_CSIDMATS_STATFIFO_DMA_TSF_SIZE_SFF_MASK) +/*! @} */ /*! @name CSIDMASA_FB1 - CSI DMA Start Address Register - for Frame Buffer1 */ +/*! @{ */ #define CSI_CSIDMASA_FB1_DMA_START_ADDR_FB1_MASK (0xFFFFFFFCU) #define CSI_CSIDMASA_FB1_DMA_START_ADDR_FB1_SHIFT (2U) #define CSI_CSIDMASA_FB1_DMA_START_ADDR_FB1(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSIDMASA_FB1_DMA_START_ADDR_FB1_SHIFT)) & CSI_CSIDMASA_FB1_DMA_START_ADDR_FB1_MASK) +/*! @} */ /*! @name CSIDMASA_FB2 - CSI DMA Transfer Size Register - for Frame Buffer2 */ +/*! @{ */ #define CSI_CSIDMASA_FB2_DMA_START_ADDR_FB2_MASK (0xFFFFFFFCU) #define CSI_CSIDMASA_FB2_DMA_START_ADDR_FB2_SHIFT (2U) #define CSI_CSIDMASA_FB2_DMA_START_ADDR_FB2(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSIDMASA_FB2_DMA_START_ADDR_FB2_SHIFT)) & CSI_CSIDMASA_FB2_DMA_START_ADDR_FB2_MASK) +/*! @} */ /*! @name CSIFBUF_PARA - CSI Frame Buffer Parameter Register */ +/*! @{ */ #define CSI_CSIFBUF_PARA_FBUF_STRIDE_MASK (0xFFFFU) #define CSI_CSIFBUF_PARA_FBUF_STRIDE_SHIFT (0U) #define CSI_CSIFBUF_PARA_FBUF_STRIDE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSIFBUF_PARA_FBUF_STRIDE_SHIFT)) & CSI_CSIFBUF_PARA_FBUF_STRIDE_MASK) #define CSI_CSIFBUF_PARA_DEINTERLACE_STRIDE_MASK (0xFFFF0000U) #define CSI_CSIFBUF_PARA_DEINTERLACE_STRIDE_SHIFT (16U) #define CSI_CSIFBUF_PARA_DEINTERLACE_STRIDE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSIFBUF_PARA_DEINTERLACE_STRIDE_SHIFT)) & CSI_CSIFBUF_PARA_DEINTERLACE_STRIDE_MASK) +/*! @} */ /*! @name CSIIMAG_PARA - CSI Image Parameter Register */ +/*! @{ */ #define CSI_CSIIMAG_PARA_IMAGE_HEIGHT_MASK (0xFFFFU) #define CSI_CSIIMAG_PARA_IMAGE_HEIGHT_SHIFT (0U) #define CSI_CSIIMAG_PARA_IMAGE_HEIGHT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSIIMAG_PARA_IMAGE_HEIGHT_SHIFT)) & CSI_CSIIMAG_PARA_IMAGE_HEIGHT_MASK) #define CSI_CSIIMAG_PARA_IMAGE_WIDTH_MASK (0xFFFF0000U) #define CSI_CSIIMAG_PARA_IMAGE_WIDTH_SHIFT (16U) #define CSI_CSIIMAG_PARA_IMAGE_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSIIMAG_PARA_IMAGE_WIDTH_SHIFT)) & CSI_CSIIMAG_PARA_IMAGE_WIDTH_MASK) +/*! @} */ /*! @name CSICR18 - CSI Control Register 18 */ +/*! @{ */ #define CSI_CSICR18_DEINTERLACE_EN_MASK (0x4U) #define CSI_CSICR18_DEINTERLACE_EN_SHIFT (2U) +/*! DEINTERLACE_EN + * 0b0..Deinterlace disabled + * 0b1..Deinterlace enabled + */ #define CSI_CSICR18_DEINTERLACE_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_DEINTERLACE_EN_SHIFT)) & CSI_CSICR18_DEINTERLACE_EN_MASK) #define CSI_CSICR18_PARALLEL24_EN_MASK (0x8U) #define CSI_CSICR18_PARALLEL24_EN_SHIFT (3U) @@ -5838,39 +8648,65 @@ typedef struct { #define CSI_CSICR18_BASEADDR_SWITCH_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_BASEADDR_SWITCH_EN_SHIFT)) & CSI_CSICR18_BASEADDR_SWITCH_EN_MASK) #define CSI_CSICR18_BASEADDR_SWITCH_SEL_MASK (0x20U) #define CSI_CSICR18_BASEADDR_SWITCH_SEL_SHIFT (5U) +/*! BASEADDR_SWITCH_SEL + * 0b0..Switching base address at the edge of the vsync + * 0b1..Switching base address at the edge of the first data of each frame + */ #define CSI_CSICR18_BASEADDR_SWITCH_SEL(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_BASEADDR_SWITCH_SEL_SHIFT)) & CSI_CSICR18_BASEADDR_SWITCH_SEL_MASK) #define CSI_CSICR18_FIELD0_DONE_IE_MASK (0x40U) #define CSI_CSICR18_FIELD0_DONE_IE_SHIFT (6U) +/*! FIELD0_DONE_IE + * 0b0..Interrupt disabled + * 0b1..Interrupt enabled + */ #define CSI_CSICR18_FIELD0_DONE_IE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_FIELD0_DONE_IE_SHIFT)) & CSI_CSICR18_FIELD0_DONE_IE_MASK) #define CSI_CSICR18_DMA_FIELD1_DONE_IE_MASK (0x80U) #define CSI_CSICR18_DMA_FIELD1_DONE_IE_SHIFT (7U) +/*! DMA_FIELD1_DONE_IE + * 0b0..Interrupt disabled + * 0b1..Interrupt enabled + */ #define CSI_CSICR18_DMA_FIELD1_DONE_IE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_DMA_FIELD1_DONE_IE_SHIFT)) & CSI_CSICR18_DMA_FIELD1_DONE_IE_MASK) #define CSI_CSICR18_LAST_DMA_REQ_SEL_MASK (0x100U) #define CSI_CSICR18_LAST_DMA_REQ_SEL_SHIFT (8U) +/*! LAST_DMA_REQ_SEL + * 0b0..fifo_full_level + * 0b1..hburst_length + */ #define CSI_CSICR18_LAST_DMA_REQ_SEL(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_LAST_DMA_REQ_SEL_SHIFT)) & CSI_CSICR18_LAST_DMA_REQ_SEL_MASK) #define CSI_CSICR18_BASEADDR_CHANGE_ERROR_IE_MASK (0x200U) #define CSI_CSICR18_BASEADDR_CHANGE_ERROR_IE_SHIFT (9U) #define CSI_CSICR18_BASEADDR_CHANGE_ERROR_IE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_BASEADDR_CHANGE_ERROR_IE_SHIFT)) & CSI_CSICR18_BASEADDR_CHANGE_ERROR_IE_MASK) #define CSI_CSICR18_RGB888A_FORMAT_SEL_MASK (0x400U) #define CSI_CSICR18_RGB888A_FORMAT_SEL_SHIFT (10U) +/*! RGB888A_FORMAT_SEL + * 0b0..{8'h0, data[23:0]} + * 0b1..{data[23:0], 8'h0} + */ #define CSI_CSICR18_RGB888A_FORMAT_SEL(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_RGB888A_FORMAT_SEL_SHIFT)) & CSI_CSICR18_RGB888A_FORMAT_SEL_MASK) #define CSI_CSICR18_AHB_HPROT_MASK (0xF000U) #define CSI_CSICR18_AHB_HPROT_SHIFT (12U) #define CSI_CSICR18_AHB_HPROT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_AHB_HPROT_SHIFT)) & CSI_CSICR18_AHB_HPROT_MASK) -#define CSI_CSICR18_CSI_LCDIF_BUFFER_LINES_MASK (0x30000U) -#define CSI_CSICR18_CSI_LCDIF_BUFFER_LINES_SHIFT (16U) -#define CSI_CSICR18_CSI_LCDIF_BUFFER_LINES(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_CSI_LCDIF_BUFFER_LINES_SHIFT)) & CSI_CSICR18_CSI_LCDIF_BUFFER_LINES_MASK) #define CSI_CSICR18_MASK_OPTION_MASK (0xC0000U) #define CSI_CSICR18_MASK_OPTION_SHIFT (18U) +/*! MASK_OPTION + * 0b00..Writing to memory from first completely frame, when using this option, the CSI_ENABLE should be 1. + * 0b01..Writing to memory when CSI_ENABLE is 1. + * 0b10..Writing to memory from second completely frame, when using this option, the CSI_ENABLE should be 1. + * 0b11..Writing to memory when data comes in, not matter the CSI_ENABLE is 1 or 0. + */ #define CSI_CSICR18_MASK_OPTION(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_MASK_OPTION_SHIFT)) & CSI_CSICR18_MASK_OPTION_MASK) #define CSI_CSICR18_CSI_ENABLE_MASK (0x80000000U) #define CSI_CSICR18_CSI_ENABLE_SHIFT (31U) #define CSI_CSICR18_CSI_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_CSI_ENABLE_SHIFT)) & CSI_CSICR18_CSI_ENABLE_MASK) +/*! @} */ /*! @name CSICR19 - CSI Control Register 19 */ +/*! @{ */ #define CSI_CSICR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL_MASK (0xFFU) #define CSI_CSICR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL_SHIFT (0U) #define CSI_CSICR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL_SHIFT)) & CSI_CSICR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL_MASK) +/*! @} */ /*! @@ -5925,249 +8761,569 @@ typedef struct { */ /*! @name CSL - Config security level register */ +/*! @{ */ #define CSU_CSL_SUR_S2_MASK (0x1U) #define CSU_CSL_SUR_S2_SHIFT (0U) +/*! SUR_S2 + * 0b0..The secure user read access is disabled for the second slave. + * 0b1..The secure user read access is enabled for the second slave. + */ #define CSU_CSL_SUR_S2(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SUR_S2_SHIFT)) & CSU_CSL_SUR_S2_MASK) #define CSU_CSL_SSR_S2_MASK (0x2U) #define CSU_CSL_SSR_S2_SHIFT (1U) +/*! SSR_S2 + * 0b0..The secure supervisor read access is disabled for the second slave. + * 0b1..The secure supervisor read access is enabled for the second slave. + */ #define CSU_CSL_SSR_S2(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SSR_S2_SHIFT)) & CSU_CSL_SSR_S2_MASK) #define CSU_CSL_NUR_S2_MASK (0x4U) #define CSU_CSL_NUR_S2_SHIFT (2U) +/*! NUR_S2 + * 0b0..The non-secure user read access is disabled for the second slave. + * 0b1..The non-secure user read access is enabled for the second slave. + */ #define CSU_CSL_NUR_S2(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NUR_S2_SHIFT)) & CSU_CSL_NUR_S2_MASK) #define CSU_CSL_NSR_S2_MASK (0x8U) #define CSU_CSL_NSR_S2_SHIFT (3U) +/*! NSR_S2 + * 0b0..The non-secure supervisor read access is disabled for the second slave. + * 0b1..The non-secure supervisor read access is enabled for the second slave. + */ #define CSU_CSL_NSR_S2(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NSR_S2_SHIFT)) & CSU_CSL_NSR_S2_MASK) #define CSU_CSL_SUW_S2_MASK (0x10U) #define CSU_CSL_SUW_S2_SHIFT (4U) +/*! SUW_S2 + * 0b0..The secure user write access is disabled for the second slave. + * 0b1..The secure user write access is enabled for the second slave. + */ #define CSU_CSL_SUW_S2(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SUW_S2_SHIFT)) & CSU_CSL_SUW_S2_MASK) #define CSU_CSL_SSW_S2_MASK (0x20U) #define CSU_CSL_SSW_S2_SHIFT (5U) +/*! SSW_S2 + * 0b0..The secure supervisor write access is disabled for the second slave. + * 0b1..The secure supervisor write access is enabled for the second slave. + */ #define CSU_CSL_SSW_S2(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SSW_S2_SHIFT)) & CSU_CSL_SSW_S2_MASK) #define CSU_CSL_NUW_S2_MASK (0x40U) #define CSU_CSL_NUW_S2_SHIFT (6U) +/*! NUW_S2 + * 0b0..The non-secure user write access is disabled for the second slave. + * 0b1..The non-secure user write access is enabled for the second slave. + */ #define CSU_CSL_NUW_S2(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NUW_S2_SHIFT)) & CSU_CSL_NUW_S2_MASK) #define CSU_CSL_NSW_S2_MASK (0x80U) #define CSU_CSL_NSW_S2_SHIFT (7U) +/*! NSW_S2 + * 0b0..The non-secure supervisor write access is disabled for the second slave. + * 0b1..The non-secure supervisor write access is enabled for the second slave. + */ #define CSU_CSL_NSW_S2(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NSW_S2_SHIFT)) & CSU_CSL_NSW_S2_MASK) #define CSU_CSL_LOCK_S2_MASK (0x100U) #define CSU_CSL_LOCK_S2_SHIFT (8U) +/*! LOCK_S2 + * 0b0..Not locked. Bits 7-0 can be written by the software. + * 0b1..Bits 7-0 are locked and cannot be written by the software + */ #define CSU_CSL_LOCK_S2(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_LOCK_S2_SHIFT)) & CSU_CSL_LOCK_S2_MASK) #define CSU_CSL_SUR_S1_MASK (0x10000U) #define CSU_CSL_SUR_S1_SHIFT (16U) +/*! SUR_S1 + * 0b0..The secure user read access is disabled for the first slave. + * 0b1..The secure user read access is enabled for the first slave. + */ #define CSU_CSL_SUR_S1(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SUR_S1_SHIFT)) & CSU_CSL_SUR_S1_MASK) #define CSU_CSL_SSR_S1_MASK (0x20000U) #define CSU_CSL_SSR_S1_SHIFT (17U) +/*! SSR_S1 + * 0b0..The secure supervisor read access is disabled for the first slave. + * 0b1..The secure supervisor read access is enabled for the first slave. + */ #define CSU_CSL_SSR_S1(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SSR_S1_SHIFT)) & CSU_CSL_SSR_S1_MASK) #define CSU_CSL_NUR_S1_MASK (0x40000U) #define CSU_CSL_NUR_S1_SHIFT (18U) +/*! NUR_S1 + * 0b0..The non-secure user read access is disabled for the first slave. + * 0b1..The non-secure user read access is enabled for the first slave. + */ #define CSU_CSL_NUR_S1(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NUR_S1_SHIFT)) & CSU_CSL_NUR_S1_MASK) #define CSU_CSL_NSR_S1_MASK (0x80000U) #define CSU_CSL_NSR_S1_SHIFT (19U) +/*! NSR_S1 + * 0b0..The non-secure supervisor read access is disabled for the first slave. + * 0b1..The non-secure supervisor read access is enabled for the first slave. + */ #define CSU_CSL_NSR_S1(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NSR_S1_SHIFT)) & CSU_CSL_NSR_S1_MASK) #define CSU_CSL_SUW_S1_MASK (0x100000U) #define CSU_CSL_SUW_S1_SHIFT (20U) +/*! SUW_S1 + * 0b0..The secure user write access is disabled for the first slave. + * 0b1..The secure user write access is enabled for the first slave. + */ #define CSU_CSL_SUW_S1(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SUW_S1_SHIFT)) & CSU_CSL_SUW_S1_MASK) #define CSU_CSL_SSW_S1_MASK (0x200000U) #define CSU_CSL_SSW_S1_SHIFT (21U) +/*! SSW_S1 + * 0b0..The secure supervisor write access is disabled for the first slave. + * 0b1..The secure supervisor write access is enabled for the first slave. + */ #define CSU_CSL_SSW_S1(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SSW_S1_SHIFT)) & CSU_CSL_SSW_S1_MASK) #define CSU_CSL_NUW_S1_MASK (0x400000U) #define CSU_CSL_NUW_S1_SHIFT (22U) +/*! NUW_S1 + * 0b0..The non-secure user write access is disabled for the first slave. + * 0b1..The non-secure user write access is enabled for the first slave. + */ #define CSU_CSL_NUW_S1(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NUW_S1_SHIFT)) & CSU_CSL_NUW_S1_MASK) #define CSU_CSL_NSW_S1_MASK (0x800000U) #define CSU_CSL_NSW_S1_SHIFT (23U) +/*! NSW_S1 + * 0b0..The non-secure supervisor write access is disabled for the first slave. + * 0b1..The non-secure supervisor write access is enabled for the first slave + */ #define CSU_CSL_NSW_S1(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NSW_S1_SHIFT)) & CSU_CSL_NSW_S1_MASK) #define CSU_CSL_LOCK_S1_MASK (0x1000000U) #define CSU_CSL_LOCK_S1_SHIFT (24U) +/*! LOCK_S1 + * 0b0..Not locked. The bits 16-23 can be written by the software. + * 0b1..The bits 16-23 are locked and can't be written by the software. + */ #define CSU_CSL_LOCK_S1(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_LOCK_S1_SHIFT)) & CSU_CSL_LOCK_S1_MASK) +/*! @} */ /* The count of CSU_CSL */ #define CSU_CSL_COUNT (32U) /*! @name HP0 - HP0 register */ +/*! @{ */ #define CSU_HP0_HP_DMA_MASK (0x4U) #define CSU_HP0_HP_DMA_SHIFT (2U) +/*! HP_DMA + * 0b0..The hprot1 input signal value is routed to the csu_hprot1 output for the corresponding master. + * 0b1..The HP register bit is routed to the csu_hprot1 output for the corresponding master. + */ #define CSU_HP0_HP_DMA(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_DMA_SHIFT)) & CSU_HP0_HP_DMA_MASK) #define CSU_HP0_L_DMA_MASK (0x8U) #define CSU_HP0_L_DMA_SHIFT (3U) +/*! L_DMA + * 0b0..No lock-the adjacent (next lower) bit can be written by the software. + * 0b1..Lock-the adjacent (next lower) bit can't be written by the software. + */ #define CSU_HP0_L_DMA(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_DMA_SHIFT)) & CSU_HP0_L_DMA_MASK) #define CSU_HP0_HP_LCDIF_MASK (0x10U) #define CSU_HP0_HP_LCDIF_SHIFT (4U) +/*! HP_LCDIF + * 0b0..The hprot1 input signal value is routed to the csu_hprot1 output for the corresponding master. + * 0b1..The HP register bit is routed to the csu_hprot1 output for the corresponding master. + */ #define CSU_HP0_HP_LCDIF(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_LCDIF_SHIFT)) & CSU_HP0_HP_LCDIF_MASK) #define CSU_HP0_L_LCDIF_MASK (0x20U) #define CSU_HP0_L_LCDIF_SHIFT (5U) +/*! L_LCDIF + * 0b0..No lock-the adjacent (next lower) bit can be written by the software. + * 0b1..Lock-the adjacent (next lower) bit can't be written by the software. + */ #define CSU_HP0_L_LCDIF(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_LCDIF_SHIFT)) & CSU_HP0_L_LCDIF_MASK) #define CSU_HP0_HP_CSI_MASK (0x40U) #define CSU_HP0_HP_CSI_SHIFT (6U) +/*! HP_CSI + * 0b0..The hprot1 input signal value is routed to the csu_hprot1 output for the corresponding master. + * 0b1..The HP register bit is routed to the csu_hprot1 output for the corresponding master. + */ #define CSU_HP0_HP_CSI(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_CSI_SHIFT)) & CSU_HP0_HP_CSI_MASK) #define CSU_HP0_L_CSI_MASK (0x80U) #define CSU_HP0_L_CSI_SHIFT (7U) +/*! L_CSI + * 0b0..No lock-the adjacent (next lower) bit can be written by the software. + * 0b1..Lock-the adjacent (next lower) bit can't be written by the software. + */ #define CSU_HP0_L_CSI(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_CSI_SHIFT)) & CSU_HP0_L_CSI_MASK) #define CSU_HP0_HP_PXP_MASK (0x100U) #define CSU_HP0_HP_PXP_SHIFT (8U) +/*! HP_PXP + * 0b0..The hprot1 input signal value is routed to the csu_hprot1 output for the corresponding master. + * 0b1..The HP register bit is routed to the csu_hprot1 output for the corresponding master. + */ #define CSU_HP0_HP_PXP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_PXP_SHIFT)) & CSU_HP0_HP_PXP_MASK) #define CSU_HP0_L_PXP_MASK (0x200U) #define CSU_HP0_L_PXP_SHIFT (9U) +/*! L_PXP + * 0b0..No lock-the adjacent (next lower) bit can be written by the software. + * 0b1..Lock-the adjacent (next lower) bit can't be written by the software. + */ #define CSU_HP0_L_PXP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_PXP_SHIFT)) & CSU_HP0_L_PXP_MASK) #define CSU_HP0_HP_DCP_MASK (0x400U) #define CSU_HP0_HP_DCP_SHIFT (10U) +/*! HP_DCP + * 0b0..The hprot1 input signal value is routed to the csu_hprot1 output for the corresponding master. + * 0b1..The HP register bit is routed to the csu_hprot1 output for the corresponding master. + */ #define CSU_HP0_HP_DCP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_DCP_SHIFT)) & CSU_HP0_HP_DCP_MASK) #define CSU_HP0_L_DCP_MASK (0x800U) #define CSU_HP0_L_DCP_SHIFT (11U) +/*! L_DCP + * 0b0..No lock-the adjacent (next lower) bit can be written by the software. + * 0b1..Lock-the adjacent (next lower) bit cannot be written by the software. + */ #define CSU_HP0_L_DCP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_DCP_SHIFT)) & CSU_HP0_L_DCP_MASK) #define CSU_HP0_HP_ENET_MASK (0x4000U) #define CSU_HP0_HP_ENET_SHIFT (14U) +/*! HP_ENET + * 0b0..The hprot1 input signal value is routed to the csu_hprot1 output for the corresponding master. + * 0b1..The HP register bit is routed to the csu_hprot1 output for the corresponding master. + */ #define CSU_HP0_HP_ENET(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_ENET_SHIFT)) & CSU_HP0_HP_ENET_MASK) #define CSU_HP0_L_ENET_MASK (0x8000U) #define CSU_HP0_L_ENET_SHIFT (15U) +/*! L_ENET + * 0b0..No lock-the adjacent (next lower) bit can be written by the software. + * 0b1..Lock-the adjacent (next lower) bit can't be written by the software. + */ #define CSU_HP0_L_ENET(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_ENET_SHIFT)) & CSU_HP0_L_ENET_MASK) #define CSU_HP0_HP_USDHC1_MASK (0x10000U) #define CSU_HP0_HP_USDHC1_SHIFT (16U) +/*! HP_USDHC1 + * 0b0..The hprot1 input signal value is routed to the csu_hprot1 output for the corresponding master. + * 0b1..The HP register bit is routed to the csu_hprot1 output for the corresponding master. + */ #define CSU_HP0_HP_USDHC1(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_USDHC1_SHIFT)) & CSU_HP0_HP_USDHC1_MASK) #define CSU_HP0_L_USDHC1_MASK (0x20000U) #define CSU_HP0_L_USDHC1_SHIFT (17U) +/*! L_USDHC1 + * 0b0..No lock-the adjacent (next lower) bit can be written by the software. + * 0b1..Lock-the adjacent (next lower) bit can't be written by the software. + */ #define CSU_HP0_L_USDHC1(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_USDHC1_SHIFT)) & CSU_HP0_L_USDHC1_MASK) #define CSU_HP0_HP_USDHC2_MASK (0x40000U) #define CSU_HP0_HP_USDHC2_SHIFT (18U) +/*! HP_USDHC2 + * 0b0..The hprot1 input signal value is routed to the csu_hprot1 output for the corresponding master. + * 0b1..The HP register bit is routed to the csu_hprot1 output for the corresponding master. + */ #define CSU_HP0_HP_USDHC2(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_USDHC2_SHIFT)) & CSU_HP0_HP_USDHC2_MASK) #define CSU_HP0_L_USDHC2_MASK (0x80000U) #define CSU_HP0_L_USDHC2_SHIFT (19U) +/*! L_USDHC2 + * 0b0..No lock-the adjacent (next lower) bit can be written by the software. + * 0b1..Lock-the adjacent (next lower) bit can't be written by the software. + */ #define CSU_HP0_L_USDHC2(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_USDHC2_SHIFT)) & CSU_HP0_L_USDHC2_MASK) #define CSU_HP0_HP_TPSMP_MASK (0x100000U) #define CSU_HP0_HP_TPSMP_SHIFT (20U) +/*! HP_TPSMP + * 0b0..The hprot1 input signal value is routed to the csu_hprot1 output for the corresponding master. + * 0b1..The HP register bit is routed to the csu_hprot1 output for the corresponding master. + */ #define CSU_HP0_HP_TPSMP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_TPSMP_SHIFT)) & CSU_HP0_HP_TPSMP_MASK) #define CSU_HP0_L_TPSMP_MASK (0x200000U) #define CSU_HP0_L_TPSMP_SHIFT (21U) +/*! L_TPSMP + * 0b0..No lock-the adjacent (next lower) bit can be written by the software. + * 0b1..Lock-the adjacent (next lower) bit can't be written by the software. + */ #define CSU_HP0_L_TPSMP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_TPSMP_SHIFT)) & CSU_HP0_L_TPSMP_MASK) #define CSU_HP0_HP_USB_MASK (0x400000U) #define CSU_HP0_HP_USB_SHIFT (22U) +/*! HP_USB + * 0b0..The hprot1 input signal value is routed to the csu_hprot1 output for the corresponding master. + * 0b1..The HP register bit is routed to the csu_hprot1 output for the corresponding master. + */ #define CSU_HP0_HP_USB(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_USB_SHIFT)) & CSU_HP0_HP_USB_MASK) #define CSU_HP0_L_USB_MASK (0x800000U) #define CSU_HP0_L_USB_SHIFT (23U) +/*! L_USB + * 0b0..No lock-the adjacent (next lower) bit can be written by the software. + * 0b1..Lock-the adjacent (next lower) bit can't be written by the software. + */ #define CSU_HP0_L_USB(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_USB_SHIFT)) & CSU_HP0_L_USB_MASK) +/*! @} */ /*! @name SA - Secure access register */ +/*! @{ */ #define CSU_SA_NSA_DMA_MASK (0x4U) #define CSU_SA_NSA_DMA_SHIFT (2U) +/*! NSA_DMA - Non-secure access policy indicator bit + * 0b0..Secure access for the corresponding type-1 master + * 0b1..Non-secure access for the corresponding type-1 master + */ #define CSU_SA_NSA_DMA(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_DMA_SHIFT)) & CSU_SA_NSA_DMA_MASK) #define CSU_SA_L_DMA_MASK (0x8U) #define CSU_SA_L_DMA_SHIFT (3U) +/*! L_DMA + * 0b0..No lock-the adjacent (next lower) bit can be written by the software. + * 0b1..Lock-the adjacent (next lower) bit can't be written by the software. + */ #define CSU_SA_L_DMA(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_DMA_SHIFT)) & CSU_SA_L_DMA_MASK) #define CSU_SA_NSA_LCDIF_MASK (0x10U) #define CSU_SA_NSA_LCDIF_SHIFT (4U) +/*! NSA_LCDIF - Non-secure access policy indicator bit + * 0b0..Secure access for the corresponding type-1 master + * 0b1..Non-secure access for the corresponding type-1 master + */ #define CSU_SA_NSA_LCDIF(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_LCDIF_SHIFT)) & CSU_SA_NSA_LCDIF_MASK) #define CSU_SA_L_LCDIF_MASK (0x20U) #define CSU_SA_L_LCDIF_SHIFT (5U) +/*! L_LCDIF + * 0b0..No lock-the adjacent (next lower) bit can be written by the software. + * 0b1..Lock-the adjacent (next lower) bit can't be written by the software. + */ #define CSU_SA_L_LCDIF(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_LCDIF_SHIFT)) & CSU_SA_L_LCDIF_MASK) #define CSU_SA_NSA_CSI_MASK (0x40U) #define CSU_SA_NSA_CSI_SHIFT (6U) +/*! NSA_CSI - Non-secure access policy indicator bit + * 0b0..Secure access for the corresponding type-1 master + * 0b1..Non-secure access for the corresponding type-1 master + */ #define CSU_SA_NSA_CSI(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_CSI_SHIFT)) & CSU_SA_NSA_CSI_MASK) #define CSU_SA_L_CSI_MASK (0x80U) #define CSU_SA_L_CSI_SHIFT (7U) +/*! L_CSI + * 0b0..No lock-the adjacent (next lower) bit can be written by the software. + * 0b1..Lock-the adjacent (next lower) bit can't be written by the software. + */ #define CSU_SA_L_CSI(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_CSI_SHIFT)) & CSU_SA_L_CSI_MASK) #define CSU_SA_NSA_PXP_MASK (0x100U) #define CSU_SA_NSA_PXP_SHIFT (8U) +/*! NSA_PXP - Non-Secure Access Policy indicator bit + * 0b0..Secure access for the corresponding type-1 master + * 0b1..Non-secure access for the corresponding type-1 master + */ #define CSU_SA_NSA_PXP(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_PXP_SHIFT)) & CSU_SA_NSA_PXP_MASK) #define CSU_SA_L_PXP_MASK (0x200U) #define CSU_SA_L_PXP_SHIFT (9U) +/*! L_PXP + * 0b0..No lock-the adjacent (next lower) bit can be written by the software. + * 0b1..Lock-the adjacent (next lower) bit can't be written by the software. + */ #define CSU_SA_L_PXP(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_PXP_SHIFT)) & CSU_SA_L_PXP_MASK) #define CSU_SA_NSA_DCP_MASK (0x400U) #define CSU_SA_NSA_DCP_SHIFT (10U) +/*! NSA_DCP - Non-secure access policy indicator bit + * 0b0..Secure access for the corresponding type-1 master + * 0b1..Non-secure access for the corresponding type-1 master + */ #define CSU_SA_NSA_DCP(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_DCP_SHIFT)) & CSU_SA_NSA_DCP_MASK) #define CSU_SA_L_DCP_MASK (0x800U) #define CSU_SA_L_DCP_SHIFT (11U) +/*! L_DCP + * 0b0..No lock-the adjacent (next lower) bit can be written by the software. + * 0b1..Lock-the adjacent (next lower) bit can't be written by the software. + */ #define CSU_SA_L_DCP(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_DCP_SHIFT)) & CSU_SA_L_DCP_MASK) #define CSU_SA_NSA_ENET_MASK (0x4000U) #define CSU_SA_NSA_ENET_SHIFT (14U) +/*! NSA_ENET - Non-secure access policy indicator bit + * 0b0..Secure access for the corresponding type-1 master + * 0b1..Non-secure access for the corresponding type-1 master + */ #define CSU_SA_NSA_ENET(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_ENET_SHIFT)) & CSU_SA_NSA_ENET_MASK) #define CSU_SA_L_ENET_MASK (0x8000U) #define CSU_SA_L_ENET_SHIFT (15U) +/*! L_ENET + * 0b0..No lock-the adjacent (next lower) bit can be written by the software. + * 0b1..Lock-the adjacent (next lower) bit can't be written by the software. + */ #define CSU_SA_L_ENET(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_ENET_SHIFT)) & CSU_SA_L_ENET_MASK) #define CSU_SA_NSA_USDHC1_MASK (0x10000U) #define CSU_SA_NSA_USDHC1_SHIFT (16U) +/*! NSA_USDHC1 - Non-secure access policy indicator bit + * 0b0..Secure access for the corresponding type-1 master + * 0b1..Non-secure access for the corresponding type-1 master + */ #define CSU_SA_NSA_USDHC1(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_USDHC1_SHIFT)) & CSU_SA_NSA_USDHC1_MASK) #define CSU_SA_L_USDHC1_MASK (0x20000U) #define CSU_SA_L_USDHC1_SHIFT (17U) +/*! L_USDHC1 + * 0b0..No lock-the adjacent (next lower) bit can be written by the software. + * 0b1..Lock-the adjacent (next lower) bit can't be written by the software. + */ #define CSU_SA_L_USDHC1(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_USDHC1_SHIFT)) & CSU_SA_L_USDHC1_MASK) #define CSU_SA_NSA_USDHC2_MASK (0x40000U) #define CSU_SA_NSA_USDHC2_SHIFT (18U) +/*! NSA_USDHC2 - Non-secure access policy indicator bit + * 0b0..Secure access for the corresponding type-1 master + * 0b1..Non-secure access for the corresponding type-1 master + */ #define CSU_SA_NSA_USDHC2(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_USDHC2_SHIFT)) & CSU_SA_NSA_USDHC2_MASK) #define CSU_SA_L_USDHC2_MASK (0x80000U) #define CSU_SA_L_USDHC2_SHIFT (19U) +/*! L_USDHC2 + * 0b0..No lock-the adjacent (next lower) bit can be written by the software. + * 0b1..Lock-the adjacent (next lower) bit can't be written by the software. + */ #define CSU_SA_L_USDHC2(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_USDHC2_SHIFT)) & CSU_SA_L_USDHC2_MASK) #define CSU_SA_NSA_TPSMP_MASK (0x100000U) #define CSU_SA_NSA_TPSMP_SHIFT (20U) +/*! NSA_TPSMP - Non-secure access policy indicator bit + * 0b0..Secure access for the corresponding type-1 master + * 0b1..Non-secure access for the corresponding type-1 master + */ #define CSU_SA_NSA_TPSMP(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_TPSMP_SHIFT)) & CSU_SA_NSA_TPSMP_MASK) #define CSU_SA_L_TPSMP_MASK (0x200000U) #define CSU_SA_L_TPSMP_SHIFT (21U) +/*! L_TPSMP + * 0b0..No lock-the adjacent (next lower) bit can be written by the software. + * 0b1..Lock-the adjacent (next lower) bit can't be written by the software. + */ #define CSU_SA_L_TPSMP(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_TPSMP_SHIFT)) & CSU_SA_L_TPSMP_MASK) #define CSU_SA_NSA_USB_MASK (0x400000U) #define CSU_SA_NSA_USB_SHIFT (22U) +/*! NSA_USB - Non-secure access policy indicator bit + * 0b0..Secure access for the corresponding type-1 master + * 0b1..Non-secure access for the corresponding type-1 master + */ #define CSU_SA_NSA_USB(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_USB_SHIFT)) & CSU_SA_NSA_USB_MASK) #define CSU_SA_L_USB_MASK (0x800000U) #define CSU_SA_L_USB_SHIFT (23U) +/*! L_USB + * 0b0..No lock-the adjacent (next lower) bit can be written by the software. + * 0b1..Lock-the adjacent (next lower) bit can't be written by the software. + */ #define CSU_SA_L_USB(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_USB_SHIFT)) & CSU_SA_L_USB_MASK) +/*! @} */ /*! @name HPCONTROL0 - HPCONTROL0 register */ +/*! @{ */ #define CSU_HPCONTROL0_HPC_DMA_MASK (0x4U) #define CSU_HPCONTROL0_HPC_DMA_SHIFT (2U) +/*! HPC_DMA + * 0b0..User mode for the corresponding master + * 0b1..Supervisor mode for the corresponding master + */ #define CSU_HPCONTROL0_HPC_DMA(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_DMA_SHIFT)) & CSU_HPCONTROL0_HPC_DMA_MASK) #define CSU_HPCONTROL0_L_DMA_MASK (0x8U) #define CSU_HPCONTROL0_L_DMA_SHIFT (3U) +/*! L_DMA + * 0b0..No lock-the adjacent (next lower) bit can be written by the software. + * 0b1..Lock-the adjacent (next lower) bit can't be written by the software. + */ #define CSU_HPCONTROL0_L_DMA(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_DMA_SHIFT)) & CSU_HPCONTROL0_L_DMA_MASK) #define CSU_HPCONTROL0_HPC_LCDIF_MASK (0x10U) #define CSU_HPCONTROL0_HPC_LCDIF_SHIFT (4U) +/*! HPC_LCDIF + * 0b0..User mode for the corresponding master + * 0b1..Supervisor mode for the corresponding master + */ #define CSU_HPCONTROL0_HPC_LCDIF(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_LCDIF_SHIFT)) & CSU_HPCONTROL0_HPC_LCDIF_MASK) #define CSU_HPCONTROL0_L_LCDIF_MASK (0x20U) #define CSU_HPCONTROL0_L_LCDIF_SHIFT (5U) +/*! L_LCDIF + * 0b0..No lock-the adjacent (next lower) bit can be written by the software. + * 0b1..Lock-the adjacent (next lower) bit can't be written by the software. + */ #define CSU_HPCONTROL0_L_LCDIF(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_LCDIF_SHIFT)) & CSU_HPCONTROL0_L_LCDIF_MASK) #define CSU_HPCONTROL0_HPC_CSI_MASK (0x40U) #define CSU_HPCONTROL0_HPC_CSI_SHIFT (6U) +/*! HPC_CSI + * 0b0..User mode for the corresponding master + * 0b1..Supervisor mode for the corresponding master + */ #define CSU_HPCONTROL0_HPC_CSI(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_CSI_SHIFT)) & CSU_HPCONTROL0_HPC_CSI_MASK) #define CSU_HPCONTROL0_L_CSI_MASK (0x80U) #define CSU_HPCONTROL0_L_CSI_SHIFT (7U) +/*! L_CSI + * 0b0..No lock-the adjacent (next lower) bit can be written by the software. + * 0b1..Lock-the adjacent (next lower) bit can't be written by the software. + */ #define CSU_HPCONTROL0_L_CSI(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_CSI_SHIFT)) & CSU_HPCONTROL0_L_CSI_MASK) #define CSU_HPCONTROL0_HPC_PXP_MASK (0x100U) #define CSU_HPCONTROL0_HPC_PXP_SHIFT (8U) +/*! HPC_PXP + * 0b0..User mode for the corresponding master + * 0b1..Supervisor mode for the corresponding master + */ #define CSU_HPCONTROL0_HPC_PXP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_PXP_SHIFT)) & CSU_HPCONTROL0_HPC_PXP_MASK) #define CSU_HPCONTROL0_L_PXP_MASK (0x200U) #define CSU_HPCONTROL0_L_PXP_SHIFT (9U) +/*! L_PXP + * 0b0..No lock-the adjacent (next lower) bit can be written by the software. + * 0b1..Lock-the adjacent (next lower) bit can't be written by the software. + */ #define CSU_HPCONTROL0_L_PXP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_PXP_SHIFT)) & CSU_HPCONTROL0_L_PXP_MASK) #define CSU_HPCONTROL0_HPC_DCP_MASK (0x400U) #define CSU_HPCONTROL0_HPC_DCP_SHIFT (10U) +/*! HPC_DCP + * 0b0..User mode for the corresponding master + * 0b1..Supervisor mode for the corresponding master + */ #define CSU_HPCONTROL0_HPC_DCP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_DCP_SHIFT)) & CSU_HPCONTROL0_HPC_DCP_MASK) #define CSU_HPCONTROL0_L_DCP_MASK (0x800U) #define CSU_HPCONTROL0_L_DCP_SHIFT (11U) +/*! L_DCP + * 0b0..No lock-the adjacent (next lower) bit can be written by the software. + * 0b1..Lock-the adjacent (next lower) bit can't be written by the software. + */ #define CSU_HPCONTROL0_L_DCP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_DCP_SHIFT)) & CSU_HPCONTROL0_L_DCP_MASK) #define CSU_HPCONTROL0_HPC_ENET_MASK (0x4000U) #define CSU_HPCONTROL0_HPC_ENET_SHIFT (14U) +/*! HPC_ENET + * 0b0..User mode for the corresponding master + * 0b1..Supervisor mode for the corresponding master + */ #define CSU_HPCONTROL0_HPC_ENET(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_ENET_SHIFT)) & CSU_HPCONTROL0_HPC_ENET_MASK) #define CSU_HPCONTROL0_L_ENET_MASK (0x8000U) #define CSU_HPCONTROL0_L_ENET_SHIFT (15U) +/*! L_ENET + * 0b0..No lock-the adjacent (next lower) bit can be written by the software. + * 0b1..Lock-the adjacent (next lower) bit can't be written by the software. + */ #define CSU_HPCONTROL0_L_ENET(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_ENET_SHIFT)) & CSU_HPCONTROL0_L_ENET_MASK) #define CSU_HPCONTROL0_HPC_USDHC1_MASK (0x10000U) #define CSU_HPCONTROL0_HPC_USDHC1_SHIFT (16U) +/*! HPC_USDHC1 + * 0b0..User mode for the corresponding master + * 0b1..Supervisor mode for the corresponding master + */ #define CSU_HPCONTROL0_HPC_USDHC1(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_USDHC1_SHIFT)) & CSU_HPCONTROL0_HPC_USDHC1_MASK) #define CSU_HPCONTROL0_L_USDHC1_MASK (0x20000U) #define CSU_HPCONTROL0_L_USDHC1_SHIFT (17U) +/*! L_USDHC1 + * 0b0..No lock-the adjacent (next lower) bit can be written by the software. + * 0b1..Lock-the adjacent (next lower) bit can't be written by the software. + */ #define CSU_HPCONTROL0_L_USDHC1(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_USDHC1_SHIFT)) & CSU_HPCONTROL0_L_USDHC1_MASK) #define CSU_HPCONTROL0_HPC_USDHC2_MASK (0x40000U) #define CSU_HPCONTROL0_HPC_USDHC2_SHIFT (18U) +/*! HPC_USDHC2 + * 0b0..User mode for the corresponding master + * 0b1..Supervisor mode for the corresponding master + */ #define CSU_HPCONTROL0_HPC_USDHC2(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_USDHC2_SHIFT)) & CSU_HPCONTROL0_HPC_USDHC2_MASK) #define CSU_HPCONTROL0_L_USDHC2_MASK (0x80000U) #define CSU_HPCONTROL0_L_USDHC2_SHIFT (19U) +/*! L_USDHC2 + * 0b0..No lock-the adjacent (next lower) bit can be written by the software. + * 0b1..Lock-the adjacent (next lower) bit can't be written by the software. + */ #define CSU_HPCONTROL0_L_USDHC2(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_USDHC2_SHIFT)) & CSU_HPCONTROL0_L_USDHC2_MASK) #define CSU_HPCONTROL0_HPC_TPSMP_MASK (0x100000U) #define CSU_HPCONTROL0_HPC_TPSMP_SHIFT (20U) +/*! HPC_TPSMP + * 0b0..User mode for the corresponding master + * 0b1..Supervisor mode for the corresponding master + */ #define CSU_HPCONTROL0_HPC_TPSMP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_TPSMP_SHIFT)) & CSU_HPCONTROL0_HPC_TPSMP_MASK) #define CSU_HPCONTROL0_L_TPSMP_MASK (0x200000U) #define CSU_HPCONTROL0_L_TPSMP_SHIFT (21U) +/*! L_TPSMP + * 0b0..No lock-the adjacent (next lower) bit can be written by the software. + * 0b1..Lock-the adjacent (next lower) bit can't be written by the software. + */ #define CSU_HPCONTROL0_L_TPSMP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_TPSMP_SHIFT)) & CSU_HPCONTROL0_L_TPSMP_MASK) #define CSU_HPCONTROL0_HPC_USB_MASK (0x400000U) #define CSU_HPCONTROL0_HPC_USB_SHIFT (22U) +/*! HPC_USB + * 0b0..User mode for the corresponding master + * 0b1..Supervisor mode for the corresponding master + */ #define CSU_HPCONTROL0_HPC_USB(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_USB_SHIFT)) & CSU_HPCONTROL0_HPC_USB_MASK) #define CSU_HPCONTROL0_L_USB_MASK (0x800000U) #define CSU_HPCONTROL0_L_USB_SHIFT (23U) +/*! L_USB + * 0b0..No lock-the adjacent (next lower) bit can be written by the software. + * 0b1..Lock-the adjacent (next lower) bit can't be written by the software. + */ #define CSU_HPCONTROL0_L_USB(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_USB_SHIFT)) & CSU_HPCONTROL0_L_USB_MASK) +/*! @} */ /*! @@ -6217,6 +9373,7 @@ typedef struct { */ /*! @name REG0 - DCDC Register 0 */ +/*! @{ */ #define DCDC_REG0_PWD_ZCD_MASK (0x1U) #define DCDC_REG0_PWD_ZCD_SHIFT (0U) #define DCDC_REG0_PWD_ZCD(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_ZCD_SHIFT)) & DCDC_REG0_PWD_ZCD_MASK) @@ -6277,8 +9434,10 @@ typedef struct { #define DCDC_REG0_STS_DC_OK_MASK (0x80000000U) #define DCDC_REG0_STS_DC_OK_SHIFT (31U) #define DCDC_REG0_STS_DC_OK(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_STS_DC_OK_SHIFT)) & DCDC_REG0_STS_DC_OK_MASK) +/*! @} */ /*! @name REG1 - DCDC Register 1 */ +/*! @{ */ #define DCDC_REG1_REG_FBK_SEL_MASK (0x180U) #define DCDC_REG1_REG_FBK_SEL_SHIFT (7U) #define DCDC_REG1_REG_FBK_SEL(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_REG_FBK_SEL_SHIFT)) & DCDC_REG1_REG_FBK_SEL_MASK) @@ -6297,8 +9456,10 @@ typedef struct { #define DCDC_REG1_VBG_TRIM_MASK (0x1F000000U) #define DCDC_REG1_VBG_TRIM_SHIFT (24U) #define DCDC_REG1_VBG_TRIM(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_VBG_TRIM_SHIFT)) & DCDC_REG1_VBG_TRIM_MASK) +/*! @} */ /*! @name REG2 - DCDC Register 2 */ +/*! @{ */ #define DCDC_REG2_LOOPCTRL_DC_C_MASK (0x3U) #define DCDC_REG2_LOOPCTRL_DC_C_SHIFT (0U) #define DCDC_REG2_LOOPCTRL_DC_C(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_LOOPCTRL_DC_C_SHIFT)) & DCDC_REG2_LOOPCTRL_DC_C_MASK) @@ -6323,8 +9484,10 @@ typedef struct { #define DCDC_REG2_DCM_SET_CTRL_MASK (0x10000000U) #define DCDC_REG2_DCM_SET_CTRL_SHIFT (28U) #define DCDC_REG2_DCM_SET_CTRL(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_DCM_SET_CTRL_SHIFT)) & DCDC_REG2_DCM_SET_CTRL_MASK) +/*! @} */ /*! @name REG3 - DCDC Register 3 */ +/*! @{ */ #define DCDC_REG3_TRG_MASK (0x1FU) #define DCDC_REG3_TRG_SHIFT (0U) #define DCDC_REG3_TRG(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_TRG_SHIFT)) & DCDC_REG3_TRG_MASK) @@ -6343,6 +9506,7 @@ typedef struct { #define DCDC_REG3_DISABLE_STEP_MASK (0x40000000U) #define DCDC_REG3_DISABLE_STEP_SHIFT (30U) #define DCDC_REG3_DISABLE_STEP(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_DISABLE_STEP_SHIFT)) & DCDC_REG3_DISABLE_STEP_MASK) +/*! @} */ /*! @@ -6459,8 +9623,15 @@ typedef struct { */ /*! @name CTRL - DCP control register 0 */ +/*! @{ */ #define DCP_CTRL_CHANNEL_INTERRUPT_ENABLE_MASK (0xFFU) #define DCP_CTRL_CHANNEL_INTERRUPT_ENABLE_SHIFT (0U) +/*! CHANNEL_INTERRUPT_ENABLE + * 0b00000001..CH0 + * 0b00000010..CH1 + * 0b00000100..CH2 + * 0b00001000..CH3 + */ #define DCP_CTRL_CHANNEL_INTERRUPT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_CHANNEL_INTERRUPT_ENABLE_SHIFT)) & DCP_CTRL_CHANNEL_INTERRUPT_ENABLE_MASK) #define DCP_CTRL_RSVD_CSC_INTERRUPT_ENABLE_MASK (0x100U) #define DCP_CTRL_RSVD_CSC_INTERRUPT_ENABLE_SHIFT (8U) @@ -6476,9 +9647,17 @@ typedef struct { #define DCP_CTRL_GATHER_RESIDUAL_WRITES(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_GATHER_RESIDUAL_WRITES_SHIFT)) & DCP_CTRL_GATHER_RESIDUAL_WRITES_MASK) #define DCP_CTRL_PRESENT_SHA_MASK (0x10000000U) #define DCP_CTRL_PRESENT_SHA_SHIFT (28U) +/*! PRESENT_SHA + * 0b1..Present + * 0b0..Absent + */ #define DCP_CTRL_PRESENT_SHA(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_PRESENT_SHA_SHIFT)) & DCP_CTRL_PRESENT_SHA_MASK) #define DCP_CTRL_PRESENT_CRYPTO_MASK (0x20000000U) #define DCP_CTRL_PRESENT_CRYPTO_SHIFT (29U) +/*! PRESENT_CRYPTO + * 0b1..Present + * 0b0..Absent + */ #define DCP_CTRL_PRESENT_CRYPTO(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_PRESENT_CRYPTO_SHIFT)) & DCP_CTRL_PRESENT_CRYPTO_MASK) #define DCP_CTRL_CLKGATE_MASK (0x40000000U) #define DCP_CTRL_CLKGATE_SHIFT (30U) @@ -6486,8 +9665,10 @@ typedef struct { #define DCP_CTRL_SFTRST_MASK (0x80000000U) #define DCP_CTRL_SFTRST_SHIFT (31U) #define DCP_CTRL_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_SFTRST_SHIFT)) & DCP_CTRL_SFTRST_MASK) +/*! @} */ /*! @name STAT - DCP status register */ +/*! @{ */ #define DCP_STAT_IRQ_MASK (0xFU) #define DCP_STAT_IRQ_SHIFT (0U) #define DCP_STAT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_IRQ_SHIFT)) & DCP_STAT_IRQ_MASK) @@ -6496,20 +9677,47 @@ typedef struct { #define DCP_STAT_RSVD_IRQ(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_RSVD_IRQ_SHIFT)) & DCP_STAT_RSVD_IRQ_MASK) #define DCP_STAT_READY_CHANNELS_MASK (0xFF0000U) #define DCP_STAT_READY_CHANNELS_SHIFT (16U) +/*! READY_CHANNELS + * 0b00000001..CH0 + * 0b00000010..CH1 + * 0b00000100..CH2 + * 0b00001000..CH3 + */ #define DCP_STAT_READY_CHANNELS(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_READY_CHANNELS_SHIFT)) & DCP_STAT_READY_CHANNELS_MASK) #define DCP_STAT_CUR_CHANNEL_MASK (0xF000000U) #define DCP_STAT_CUR_CHANNEL_SHIFT (24U) +/*! CUR_CHANNEL + * 0b0000..None + * 0b0001..CH0 + * 0b0010..CH1 + * 0b0011..CH2 + * 0b0100..CH3 + */ #define DCP_STAT_CUR_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_CUR_CHANNEL_SHIFT)) & DCP_STAT_CUR_CHANNEL_MASK) #define DCP_STAT_OTP_KEY_READY_MASK (0x10000000U) #define DCP_STAT_OTP_KEY_READY_SHIFT (28U) #define DCP_STAT_OTP_KEY_READY(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_OTP_KEY_READY_SHIFT)) & DCP_STAT_OTP_KEY_READY_MASK) +/*! @} */ /*! @name CHANNELCTRL - DCP channel control register */ +/*! @{ */ #define DCP_CHANNELCTRL_ENABLE_CHANNEL_MASK (0xFFU) #define DCP_CHANNELCTRL_ENABLE_CHANNEL_SHIFT (0U) +/*! ENABLE_CHANNEL + * 0b00000001..CH0 + * 0b00000010..CH1 + * 0b00000100..CH2 + * 0b00001000..CH3 + */ #define DCP_CHANNELCTRL_ENABLE_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_ENABLE_CHANNEL_SHIFT)) & DCP_CHANNELCTRL_ENABLE_CHANNEL_MASK) #define DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL_MASK (0xFF00U) #define DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL_SHIFT (8U) +/*! HIGH_PRIORITY_CHANNEL + * 0b00000001..CH0 + * 0b00000010..CH1 + * 0b00000100..CH2 + * 0b00001000..CH3 + */ #define DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL_SHIFT)) & DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL_MASK) #define DCP_CHANNELCTRL_CH0_IRQ_MERGED_MASK (0x10000U) #define DCP_CHANNELCTRL_CH0_IRQ_MERGED_SHIFT (16U) @@ -6517,8 +9725,10 @@ typedef struct { #define DCP_CHANNELCTRL_RSVD_MASK (0xFFFE0000U) #define DCP_CHANNELCTRL_RSVD_SHIFT (17U) #define DCP_CHANNELCTRL_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_RSVD_SHIFT)) & DCP_CHANNELCTRL_RSVD_MASK) +/*! @} */ /*! @name CAPABILITY0 - DCP capability 0 register */ +/*! @{ */ #define DCP_CAPABILITY0_NUM_KEYS_MASK (0xFFU) #define DCP_CAPABILITY0_NUM_KEYS_SHIFT (0U) #define DCP_CAPABILITY0_NUM_KEYS(x) (((uint32_t)(((uint32_t)(x)) << DCP_CAPABILITY0_NUM_KEYS_SHIFT)) & DCP_CAPABILITY0_NUM_KEYS_MASK) @@ -6534,21 +9744,35 @@ typedef struct { #define DCP_CAPABILITY0_DISABLE_DECRYPT_MASK (0x80000000U) #define DCP_CAPABILITY0_DISABLE_DECRYPT_SHIFT (31U) #define DCP_CAPABILITY0_DISABLE_DECRYPT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CAPABILITY0_DISABLE_DECRYPT_SHIFT)) & DCP_CAPABILITY0_DISABLE_DECRYPT_MASK) +/*! @} */ /*! @name CAPABILITY1 - DCP capability 1 register */ +/*! @{ */ #define DCP_CAPABILITY1_CIPHER_ALGORITHMS_MASK (0xFFFFU) #define DCP_CAPABILITY1_CIPHER_ALGORITHMS_SHIFT (0U) +/*! CIPHER_ALGORITHMS + * 0b0000000000000001..AES128 + */ #define DCP_CAPABILITY1_CIPHER_ALGORITHMS(x) (((uint32_t)(((uint32_t)(x)) << DCP_CAPABILITY1_CIPHER_ALGORITHMS_SHIFT)) & DCP_CAPABILITY1_CIPHER_ALGORITHMS_MASK) #define DCP_CAPABILITY1_HASH_ALGORITHMS_MASK (0xFFFF0000U) #define DCP_CAPABILITY1_HASH_ALGORITHMS_SHIFT (16U) +/*! HASH_ALGORITHMS + * 0b0000000000000001..SHA1 + * 0b0000000000000010..CRC32 + * 0b0000000000000100..SHA256 + */ #define DCP_CAPABILITY1_HASH_ALGORITHMS(x) (((uint32_t)(((uint32_t)(x)) << DCP_CAPABILITY1_HASH_ALGORITHMS_SHIFT)) & DCP_CAPABILITY1_HASH_ALGORITHMS_MASK) +/*! @} */ /*! @name CONTEXT - DCP context buffer pointer */ +/*! @{ */ #define DCP_CONTEXT_ADDR_MASK (0xFFFFFFFFU) #define DCP_CONTEXT_ADDR_SHIFT (0U) #define DCP_CONTEXT_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_CONTEXT_ADDR_SHIFT)) & DCP_CONTEXT_ADDR_MASK) +/*! @} */ /*! @name KEY - DCP key index */ +/*! @{ */ #define DCP_KEY_SUBWORD_MASK (0x3U) #define DCP_KEY_SUBWORD_SHIFT (0U) #define DCP_KEY_SUBWORD(x) (((uint32_t)(((uint32_t)(x)) << DCP_KEY_SUBWORD_SHIFT)) & DCP_KEY_SUBWORD_MASK) @@ -6564,18 +9788,24 @@ typedef struct { #define DCP_KEY_RSVD_MASK (0xFFFFFF00U) #define DCP_KEY_RSVD_SHIFT (8U) #define DCP_KEY_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_KEY_RSVD_SHIFT)) & DCP_KEY_RSVD_MASK) +/*! @} */ /*! @name KEYDATA - DCP key data */ +/*! @{ */ #define DCP_KEYDATA_DATA_MASK (0xFFFFFFFFU) #define DCP_KEYDATA_DATA_SHIFT (0U) #define DCP_KEYDATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << DCP_KEYDATA_DATA_SHIFT)) & DCP_KEYDATA_DATA_MASK) +/*! @} */ /*! @name PACKET0 - DCP work packet 0 status register */ +/*! @{ */ #define DCP_PACKET0_ADDR_MASK (0xFFFFFFFFU) #define DCP_PACKET0_ADDR_SHIFT (0U) #define DCP_PACKET0_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET0_ADDR_SHIFT)) & DCP_PACKET0_ADDR_MASK) +/*! @} */ /*! @name PACKET1 - DCP work packet 1 status register */ +/*! @{ */ #define DCP_PACKET1_INTERRUPT_MASK (0x1U) #define DCP_PACKET1_INTERRUPT_SHIFT (0U) #define DCP_PACKET1_INTERRUPT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_INTERRUPT_SHIFT)) & DCP_PACKET1_INTERRUPT_MASK) @@ -6602,6 +9832,10 @@ typedef struct { #define DCP_PACKET1_ENABLE_BLIT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_ENABLE_BLIT_SHIFT)) & DCP_PACKET1_ENABLE_BLIT_MASK) #define DCP_PACKET1_CIPHER_ENCRYPT_MASK (0x100U) #define DCP_PACKET1_CIPHER_ENCRYPT_SHIFT (8U) +/*! CIPHER_ENCRYPT + * 0b1..ENCRYPT + * 0b0..DECRYPT + */ #define DCP_PACKET1_CIPHER_ENCRYPT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_CIPHER_ENCRYPT_SHIFT)) & DCP_PACKET1_CIPHER_ENCRYPT_MASK) #define DCP_PACKET1_CIPHER_INIT_MASK (0x200U) #define DCP_PACKET1_CIPHER_INIT_SHIFT (9U) @@ -6623,6 +9857,10 @@ typedef struct { #define DCP_PACKET1_CHECK_HASH(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_CHECK_HASH_SHIFT)) & DCP_PACKET1_CHECK_HASH_MASK) #define DCP_PACKET1_HASH_OUTPUT_MASK (0x8000U) #define DCP_PACKET1_HASH_OUTPUT_SHIFT (15U) +/*! HASH_OUTPUT + * 0b0..INPUT + * 0b1..OUTPUT + */ #define DCP_PACKET1_HASH_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_HASH_OUTPUT_SHIFT)) & DCP_PACKET1_HASH_OUTPUT_MASK) #define DCP_PACKET1_CONSTANT_FILL_MASK (0x10000U) #define DCP_PACKET1_CONSTANT_FILL_SHIFT (16U) @@ -6651,19 +9889,41 @@ typedef struct { #define DCP_PACKET1_TAG_MASK (0xFF000000U) #define DCP_PACKET1_TAG_SHIFT (24U) #define DCP_PACKET1_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_TAG_SHIFT)) & DCP_PACKET1_TAG_MASK) +/*! @} */ /*! @name PACKET2 - DCP work packet 2 status register */ +/*! @{ */ #define DCP_PACKET2_CIPHER_SELECT_MASK (0xFU) #define DCP_PACKET2_CIPHER_SELECT_SHIFT (0U) +/*! CIPHER_SELECT + * 0b0000..AES128 + */ #define DCP_PACKET2_CIPHER_SELECT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET2_CIPHER_SELECT_SHIFT)) & DCP_PACKET2_CIPHER_SELECT_MASK) #define DCP_PACKET2_CIPHER_MODE_MASK (0xF0U) #define DCP_PACKET2_CIPHER_MODE_SHIFT (4U) +/*! CIPHER_MODE + * 0b0000..ECB + * 0b0001..CBC + */ #define DCP_PACKET2_CIPHER_MODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET2_CIPHER_MODE_SHIFT)) & DCP_PACKET2_CIPHER_MODE_MASK) #define DCP_PACKET2_KEY_SELECT_MASK (0xFF00U) #define DCP_PACKET2_KEY_SELECT_SHIFT (8U) +/*! KEY_SELECT + * 0b00000000..KEY0 + * 0b00000001..KEY1 + * 0b00000010..KEY2 + * 0b00000011..KEY3 + * 0b11111110..UNIQUE_KEY + * 0b11111111..OTP_KEY + */ #define DCP_PACKET2_KEY_SELECT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET2_KEY_SELECT_SHIFT)) & DCP_PACKET2_KEY_SELECT_MASK) #define DCP_PACKET2_HASH_SELECT_MASK (0xF0000U) #define DCP_PACKET2_HASH_SELECT_SHIFT (16U) +/*! HASH_SELECT + * 0b0000..SHA1 + * 0b0001..CRC32 + * 0b0010..SHA256 + */ #define DCP_PACKET2_HASH_SELECT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET2_HASH_SELECT_SHIFT)) & DCP_PACKET2_HASH_SELECT_MASK) #define DCP_PACKET2_RSVD_MASK (0xF00000U) #define DCP_PACKET2_RSVD_SHIFT (20U) @@ -6671,41 +9931,55 @@ typedef struct { #define DCP_PACKET2_CIPHER_CFG_MASK (0xFF000000U) #define DCP_PACKET2_CIPHER_CFG_SHIFT (24U) #define DCP_PACKET2_CIPHER_CFG(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET2_CIPHER_CFG_SHIFT)) & DCP_PACKET2_CIPHER_CFG_MASK) +/*! @} */ /*! @name PACKET3 - DCP work packet 3 status register */ +/*! @{ */ #define DCP_PACKET3_ADDR_MASK (0xFFFFFFFFU) #define DCP_PACKET3_ADDR_SHIFT (0U) #define DCP_PACKET3_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET3_ADDR_SHIFT)) & DCP_PACKET3_ADDR_MASK) +/*! @} */ /*! @name PACKET4 - DCP work packet 4 status register */ +/*! @{ */ #define DCP_PACKET4_ADDR_MASK (0xFFFFFFFFU) #define DCP_PACKET4_ADDR_SHIFT (0U) #define DCP_PACKET4_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET4_ADDR_SHIFT)) & DCP_PACKET4_ADDR_MASK) +/*! @} */ /*! @name PACKET5 - DCP work packet 5 status register */ +/*! @{ */ #define DCP_PACKET5_COUNT_MASK (0xFFFFFFFFU) #define DCP_PACKET5_COUNT_SHIFT (0U) #define DCP_PACKET5_COUNT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET5_COUNT_SHIFT)) & DCP_PACKET5_COUNT_MASK) +/*! @} */ /*! @name PACKET6 - DCP work packet 6 status register */ +/*! @{ */ #define DCP_PACKET6_ADDR_MASK (0xFFFFFFFFU) #define DCP_PACKET6_ADDR_SHIFT (0U) #define DCP_PACKET6_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET6_ADDR_SHIFT)) & DCP_PACKET6_ADDR_MASK) +/*! @} */ /*! @name CH0CMDPTR - DCP channel 0 command pointer address register */ +/*! @{ */ #define DCP_CH0CMDPTR_ADDR_MASK (0xFFFFFFFFU) #define DCP_CH0CMDPTR_ADDR_SHIFT (0U) #define DCP_CH0CMDPTR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0CMDPTR_ADDR_SHIFT)) & DCP_CH0CMDPTR_ADDR_MASK) +/*! @} */ /*! @name CH0SEMA - DCP channel 0 semaphore register */ +/*! @{ */ #define DCP_CH0SEMA_INCREMENT_MASK (0xFFU) #define DCP_CH0SEMA_INCREMENT_SHIFT (0U) #define DCP_CH0SEMA_INCREMENT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0SEMA_INCREMENT_SHIFT)) & DCP_CH0SEMA_INCREMENT_MASK) #define DCP_CH0SEMA_VALUE_MASK (0xFF0000U) #define DCP_CH0SEMA_VALUE_SHIFT (16U) #define DCP_CH0SEMA_VALUE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0SEMA_VALUE_SHIFT)) & DCP_CH0SEMA_VALUE_MASK) +/*! @} */ /*! @name CH0STAT - DCP channel 0 status register */ +/*! @{ */ #define DCP_CH0STAT_RSVD_COMPLETE_MASK (0x1U) #define DCP_CH0STAT_RSVD_COMPLETE_SHIFT (0U) #define DCP_CH0STAT_RSVD_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_RSVD_COMPLETE_SHIFT)) & DCP_CH0STAT_RSVD_COMPLETE_MASK) @@ -6729,33 +10003,48 @@ typedef struct { #define DCP_CH0STAT_ERROR_PAGEFAULT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_ERROR_PAGEFAULT_SHIFT)) & DCP_CH0STAT_ERROR_PAGEFAULT_MASK) #define DCP_CH0STAT_ERROR_CODE_MASK (0xFF0000U) #define DCP_CH0STAT_ERROR_CODE_SHIFT (16U) +/*! ERROR_CODE + * 0b00000001..Error signalled because the next pointer is 0x00000000 + * 0b00000010..Error signalled because the semaphore is non-zero and neither chain bit is set + * 0b00000011..Error signalled because an error is reported reading/writing the context buffer + * 0b00000100..Error signalled because an error is reported reading/writing the payload + * 0b00000101..Error signalled because the control packet specifies an invalid mode select (for instance, blit + hash) + */ #define DCP_CH0STAT_ERROR_CODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_ERROR_CODE_SHIFT)) & DCP_CH0STAT_ERROR_CODE_MASK) #define DCP_CH0STAT_TAG_MASK (0xFF000000U) #define DCP_CH0STAT_TAG_SHIFT (24U) #define DCP_CH0STAT_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_TAG_SHIFT)) & DCP_CH0STAT_TAG_MASK) +/*! @} */ /*! @name CH0OPTS - DCP channel 0 options register */ +/*! @{ */ #define DCP_CH0OPTS_RECOVERY_TIMER_MASK (0xFFFFU) #define DCP_CH0OPTS_RECOVERY_TIMER_SHIFT (0U) #define DCP_CH0OPTS_RECOVERY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0OPTS_RECOVERY_TIMER_SHIFT)) & DCP_CH0OPTS_RECOVERY_TIMER_MASK) #define DCP_CH0OPTS_RSVD_MASK (0xFFFF0000U) #define DCP_CH0OPTS_RSVD_SHIFT (16U) #define DCP_CH0OPTS_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0OPTS_RSVD_SHIFT)) & DCP_CH0OPTS_RSVD_MASK) +/*! @} */ /*! @name CH1CMDPTR - DCP channel 1 command pointer address register */ +/*! @{ */ #define DCP_CH1CMDPTR_ADDR_MASK (0xFFFFFFFFU) #define DCP_CH1CMDPTR_ADDR_SHIFT (0U) #define DCP_CH1CMDPTR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1CMDPTR_ADDR_SHIFT)) & DCP_CH1CMDPTR_ADDR_MASK) +/*! @} */ /*! @name CH1SEMA - DCP channel 1 semaphore register */ +/*! @{ */ #define DCP_CH1SEMA_INCREMENT_MASK (0xFFU) #define DCP_CH1SEMA_INCREMENT_SHIFT (0U) #define DCP_CH1SEMA_INCREMENT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1SEMA_INCREMENT_SHIFT)) & DCP_CH1SEMA_INCREMENT_MASK) #define DCP_CH1SEMA_VALUE_MASK (0xFF0000U) #define DCP_CH1SEMA_VALUE_SHIFT (16U) #define DCP_CH1SEMA_VALUE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1SEMA_VALUE_SHIFT)) & DCP_CH1SEMA_VALUE_MASK) +/*! @} */ /*! @name CH1STAT - DCP channel 1 status register */ +/*! @{ */ #define DCP_CH1STAT_RSVD_COMPLETE_MASK (0x1U) #define DCP_CH1STAT_RSVD_COMPLETE_SHIFT (0U) #define DCP_CH1STAT_RSVD_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_RSVD_COMPLETE_SHIFT)) & DCP_CH1STAT_RSVD_COMPLETE_MASK) @@ -6779,33 +10068,48 @@ typedef struct { #define DCP_CH1STAT_ERROR_PAGEFAULT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_ERROR_PAGEFAULT_SHIFT)) & DCP_CH1STAT_ERROR_PAGEFAULT_MASK) #define DCP_CH1STAT_ERROR_CODE_MASK (0xFF0000U) #define DCP_CH1STAT_ERROR_CODE_SHIFT (16U) +/*! ERROR_CODE + * 0b00000001..Error is signalled because the next pointer is 0x00000000. + * 0b00000010..Error is signalled because the semaphore is of a non-zero value and neither of the chain bits is set. + * 0b00000011..Error is signalled because an error was reported when reading/writing the context buffer. + * 0b00000100..Error is signalled because an error was reported when reading/writing the payload. + * 0b00000101..Error is signalled because the control packet specifies an invalid mode select (for example, blit + hash). + */ #define DCP_CH1STAT_ERROR_CODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_ERROR_CODE_SHIFT)) & DCP_CH1STAT_ERROR_CODE_MASK) #define DCP_CH1STAT_TAG_MASK (0xFF000000U) #define DCP_CH1STAT_TAG_SHIFT (24U) #define DCP_CH1STAT_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_TAG_SHIFT)) & DCP_CH1STAT_TAG_MASK) +/*! @} */ /*! @name CH1OPTS - DCP channel 1 options register */ +/*! @{ */ #define DCP_CH1OPTS_RECOVERY_TIMER_MASK (0xFFFFU) #define DCP_CH1OPTS_RECOVERY_TIMER_SHIFT (0U) #define DCP_CH1OPTS_RECOVERY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1OPTS_RECOVERY_TIMER_SHIFT)) & DCP_CH1OPTS_RECOVERY_TIMER_MASK) #define DCP_CH1OPTS_RSVD_MASK (0xFFFF0000U) #define DCP_CH1OPTS_RSVD_SHIFT (16U) #define DCP_CH1OPTS_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1OPTS_RSVD_SHIFT)) & DCP_CH1OPTS_RSVD_MASK) +/*! @} */ /*! @name CH2CMDPTR - DCP channel 2 command pointer address register */ +/*! @{ */ #define DCP_CH2CMDPTR_ADDR_MASK (0xFFFFFFFFU) #define DCP_CH2CMDPTR_ADDR_SHIFT (0U) #define DCP_CH2CMDPTR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2CMDPTR_ADDR_SHIFT)) & DCP_CH2CMDPTR_ADDR_MASK) +/*! @} */ /*! @name CH2SEMA - DCP channel 2 semaphore register */ +/*! @{ */ #define DCP_CH2SEMA_INCREMENT_MASK (0xFFU) #define DCP_CH2SEMA_INCREMENT_SHIFT (0U) #define DCP_CH2SEMA_INCREMENT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2SEMA_INCREMENT_SHIFT)) & DCP_CH2SEMA_INCREMENT_MASK) #define DCP_CH2SEMA_VALUE_MASK (0xFF0000U) #define DCP_CH2SEMA_VALUE_SHIFT (16U) #define DCP_CH2SEMA_VALUE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2SEMA_VALUE_SHIFT)) & DCP_CH2SEMA_VALUE_MASK) +/*! @} */ /*! @name CH2STAT - DCP channel 2 status register */ +/*! @{ */ #define DCP_CH2STAT_RSVD_COMPLETE_MASK (0x1U) #define DCP_CH2STAT_RSVD_COMPLETE_SHIFT (0U) #define DCP_CH2STAT_RSVD_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_RSVD_COMPLETE_SHIFT)) & DCP_CH2STAT_RSVD_COMPLETE_MASK) @@ -6829,33 +10133,48 @@ typedef struct { #define DCP_CH2STAT_ERROR_PAGEFAULT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_ERROR_PAGEFAULT_SHIFT)) & DCP_CH2STAT_ERROR_PAGEFAULT_MASK) #define DCP_CH2STAT_ERROR_CODE_MASK (0xFF0000U) #define DCP_CH2STAT_ERROR_CODE_SHIFT (16U) +/*! ERROR_CODE + * 0b00000001..Error is signalled because the next pointer is 0x00000000. + * 0b00000010..Error is signalled because the semaphore is of a non-zero value and neither of the chain bits is set. + * 0b00000011..Error is signalled because an error was reported while reading/writing the context buffer. + * 0b00000100..Error is signalled because an error was reported while reading/writing the payload. + * 0b00000101..Error is signalled because the control packet specifies an invalid mode select (for instance, blit + hash). + */ #define DCP_CH2STAT_ERROR_CODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_ERROR_CODE_SHIFT)) & DCP_CH2STAT_ERROR_CODE_MASK) #define DCP_CH2STAT_TAG_MASK (0xFF000000U) #define DCP_CH2STAT_TAG_SHIFT (24U) #define DCP_CH2STAT_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_TAG_SHIFT)) & DCP_CH2STAT_TAG_MASK) +/*! @} */ /*! @name CH2OPTS - DCP channel 2 options register */ +/*! @{ */ #define DCP_CH2OPTS_RECOVERY_TIMER_MASK (0xFFFFU) #define DCP_CH2OPTS_RECOVERY_TIMER_SHIFT (0U) #define DCP_CH2OPTS_RECOVERY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2OPTS_RECOVERY_TIMER_SHIFT)) & DCP_CH2OPTS_RECOVERY_TIMER_MASK) #define DCP_CH2OPTS_RSVD_MASK (0xFFFF0000U) #define DCP_CH2OPTS_RSVD_SHIFT (16U) #define DCP_CH2OPTS_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2OPTS_RSVD_SHIFT)) & DCP_CH2OPTS_RSVD_MASK) +/*! @} */ /*! @name CH3CMDPTR - DCP channel 3 command pointer address register */ +/*! @{ */ #define DCP_CH3CMDPTR_ADDR_MASK (0xFFFFFFFFU) #define DCP_CH3CMDPTR_ADDR_SHIFT (0U) #define DCP_CH3CMDPTR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3CMDPTR_ADDR_SHIFT)) & DCP_CH3CMDPTR_ADDR_MASK) +/*! @} */ /*! @name CH3SEMA - DCP channel 3 semaphore register */ +/*! @{ */ #define DCP_CH3SEMA_INCREMENT_MASK (0xFFU) #define DCP_CH3SEMA_INCREMENT_SHIFT (0U) #define DCP_CH3SEMA_INCREMENT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3SEMA_INCREMENT_SHIFT)) & DCP_CH3SEMA_INCREMENT_MASK) #define DCP_CH3SEMA_VALUE_MASK (0xFF0000U) #define DCP_CH3SEMA_VALUE_SHIFT (16U) #define DCP_CH3SEMA_VALUE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3SEMA_VALUE_SHIFT)) & DCP_CH3SEMA_VALUE_MASK) +/*! @} */ /*! @name CH3STAT - DCP channel 3 status register */ +/*! @{ */ #define DCP_CH3STAT_RSVD_COMPLETE_MASK (0x1U) #define DCP_CH3STAT_RSVD_COMPLETE_SHIFT (0U) #define DCP_CH3STAT_RSVD_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_RSVD_COMPLETE_SHIFT)) & DCP_CH3STAT_RSVD_COMPLETE_MASK) @@ -6879,33 +10198,55 @@ typedef struct { #define DCP_CH3STAT_ERROR_PAGEFAULT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_ERROR_PAGEFAULT_SHIFT)) & DCP_CH3STAT_ERROR_PAGEFAULT_MASK) #define DCP_CH3STAT_ERROR_CODE_MASK (0xFF0000U) #define DCP_CH3STAT_ERROR_CODE_SHIFT (16U) +/*! ERROR_CODE + * 0b00000001..Error is signalled because the next pointer is 0x00000000. + * 0b00000010..Error is signalled because the semaphore is of a non-zero value and neither of the chain bits is set. + * 0b00000011..Error is signalled because an error was reported while reading/writing the context buffer. + * 0b00000100..Error is signalled because an error was reported while reading/writing the payload. + * 0b00000101..Error is signalled because the control packet specifies an invalid mode select (for example, blit + hash). + */ #define DCP_CH3STAT_ERROR_CODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_ERROR_CODE_SHIFT)) & DCP_CH3STAT_ERROR_CODE_MASK) #define DCP_CH3STAT_TAG_MASK (0xFF000000U) #define DCP_CH3STAT_TAG_SHIFT (24U) #define DCP_CH3STAT_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_TAG_SHIFT)) & DCP_CH3STAT_TAG_MASK) +/*! @} */ /*! @name CH3OPTS - DCP channel 3 options register */ +/*! @{ */ #define DCP_CH3OPTS_RECOVERY_TIMER_MASK (0xFFFFU) #define DCP_CH3OPTS_RECOVERY_TIMER_SHIFT (0U) #define DCP_CH3OPTS_RECOVERY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3OPTS_RECOVERY_TIMER_SHIFT)) & DCP_CH3OPTS_RECOVERY_TIMER_MASK) #define DCP_CH3OPTS_RSVD_MASK (0xFFFF0000U) #define DCP_CH3OPTS_RSVD_SHIFT (16U) #define DCP_CH3OPTS_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3OPTS_RSVD_SHIFT)) & DCP_CH3OPTS_RSVD_MASK) +/*! @} */ /*! @name DBGSELECT - DCP debug select register */ +/*! @{ */ #define DCP_DBGSELECT_INDEX_MASK (0xFFU) #define DCP_DBGSELECT_INDEX_SHIFT (0U) +/*! INDEX + * 0b00000001..CONTROL + * 0b00010000..OTPKEY0 + * 0b00010001..OTPKEY1 + * 0b00010010..OTPKEY2 + * 0b00010011..OTPKEY3 + */ #define DCP_DBGSELECT_INDEX(x) (((uint32_t)(((uint32_t)(x)) << DCP_DBGSELECT_INDEX_SHIFT)) & DCP_DBGSELECT_INDEX_MASK) #define DCP_DBGSELECT_RSVD_MASK (0xFFFFFF00U) #define DCP_DBGSELECT_RSVD_SHIFT (8U) #define DCP_DBGSELECT_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_DBGSELECT_RSVD_SHIFT)) & DCP_DBGSELECT_RSVD_MASK) +/*! @} */ /*! @name DBGDATA - DCP debug data register */ +/*! @{ */ #define DCP_DBGDATA_DATA_MASK (0xFFFFFFFFU) #define DCP_DBGDATA_DATA_SHIFT (0U) #define DCP_DBGDATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << DCP_DBGDATA_DATA_SHIFT)) & DCP_DBGDATA_DATA_MASK) +/*! @} */ /*! @name PAGETABLE - DCP page table register */ +/*! @{ */ #define DCP_PAGETABLE_ENABLE_MASK (0x1U) #define DCP_PAGETABLE_ENABLE_SHIFT (0U) #define DCP_PAGETABLE_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DCP_PAGETABLE_ENABLE_SHIFT)) & DCP_PAGETABLE_ENABLE_MASK) @@ -6915,8 +10256,10 @@ typedef struct { #define DCP_PAGETABLE_BASE_MASK (0xFFFFFFFCU) #define DCP_PAGETABLE_BASE_SHIFT (2U) #define DCP_PAGETABLE_BASE(x) (((uint32_t)(((uint32_t)(x)) << DCP_PAGETABLE_BASE_SHIFT)) & DCP_PAGETABLE_BASE_MASK) +/*! @} */ /*! @name VERSION - DCP version register */ +/*! @{ */ #define DCP_VERSION_STEP_MASK (0xFFFFU) #define DCP_VERSION_STEP_SHIFT (0U) #define DCP_VERSION_STEP(x) (((uint32_t)(((uint32_t)(x)) << DCP_VERSION_STEP_SHIFT)) & DCP_VERSION_STEP_MASK) @@ -6926,6 +10269,7 @@ typedef struct { #define DCP_VERSION_MAJOR_MASK (0xFF000000U) #define DCP_VERSION_MAJOR_SHIFT (24U) #define DCP_VERSION_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << DCP_VERSION_MAJOR_SHIFT)) & DCP_VERSION_MAJOR_MASK) +/*! @} */ /*! @@ -7053,26 +10397,55 @@ typedef struct { */ /*! @name CR - Control Register */ +/*! @{ */ #define DMA_CR_EDBG_MASK (0x2U) #define DMA_CR_EDBG_SHIFT (1U) +/*! EDBG - Enable Debug + * 0b0..When in debug mode, the DMA continues to operate. + * 0b1..When in debug mode, the DMA stalls the start of a new channel. Executing channels are allowed to complete. Channel execution resumes when the system exits debug mode or the EDBG bit is cleared. + */ #define DMA_CR_EDBG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_EDBG_SHIFT)) & DMA_CR_EDBG_MASK) #define DMA_CR_ERCA_MASK (0x4U) #define DMA_CR_ERCA_SHIFT (2U) +/*! ERCA - Enable Round Robin Channel Arbitration + * 0b0..Fixed priority arbitration is used for channel selection within each group. + * 0b1..Round robin arbitration is used for channel selection within each group. + */ #define DMA_CR_ERCA(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ERCA_SHIFT)) & DMA_CR_ERCA_MASK) #define DMA_CR_ERGA_MASK (0x8U) #define DMA_CR_ERGA_SHIFT (3U) +/*! ERGA - Enable Round Robin Group Arbitration + * 0b0..Fixed priority arbitration is used for selection among the groups. + * 0b1..Round robin arbitration is used for selection among the groups. + */ #define DMA_CR_ERGA(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ERGA_SHIFT)) & DMA_CR_ERGA_MASK) #define DMA_CR_HOE_MASK (0x10U) #define DMA_CR_HOE_SHIFT (4U) +/*! HOE - Halt On Error + * 0b0..Normal operation + * 0b1..Any error causes the HALT bit to set. Subsequently, all service requests are ignored until the HALT bit is cleared. + */ #define DMA_CR_HOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_HOE_SHIFT)) & DMA_CR_HOE_MASK) #define DMA_CR_HALT_MASK (0x20U) #define DMA_CR_HALT_SHIFT (5U) +/*! HALT - Halt DMA Operations + * 0b0..Normal operation + * 0b1..Stall the start of any new channels. Executing channels are allowed to complete. Channel execution resumes when this bit is cleared. + */ #define DMA_CR_HALT(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_HALT_SHIFT)) & DMA_CR_HALT_MASK) #define DMA_CR_CLM_MASK (0x40U) #define DMA_CR_CLM_SHIFT (6U) +/*! CLM - Continuous Link Mode + * 0b0..A minor loop channel link made to itself goes through channel arbitration before being activated again. + * 0b1..A minor loop channel link made to itself does not go through channel arbitration before being activated again. Upon minor loop completion, the channel activates again if that channel has a minor loop channel link enabled and the link channel is itself. This effectively applies the minor loop offsets and restarts the next minor loop. + */ #define DMA_CR_CLM(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_CLM_SHIFT)) & DMA_CR_CLM_MASK) #define DMA_CR_EMLM_MASK (0x80U) #define DMA_CR_EMLM_SHIFT (7U) +/*! EMLM - Enable Minor Loop Mapping + * 0b0..Disabled. TCDn.word2 is defined as a 32-bit NBYTES field. + * 0b1..Enabled. TCDn.word2 is redefined to include individual enable fields, an offset field, and the NBYTES field. The individual enable fields allow the minor loop offset to be applied to the source address, the destination address, or both. The NBYTES field is reduced when either offset is enabled. + */ #define DMA_CR_EMLM(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_EMLM_SHIFT)) & DMA_CR_EMLM_MASK) #define DMA_CR_GRP0PRI_MASK (0x100U) #define DMA_CR_GRP0PRI_SHIFT (8U) @@ -7082,732 +10455,1656 @@ typedef struct { #define DMA_CR_GRP1PRI(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_GRP1PRI_SHIFT)) & DMA_CR_GRP1PRI_MASK) #define DMA_CR_ECX_MASK (0x10000U) #define DMA_CR_ECX_SHIFT (16U) +/*! ECX - Error Cancel Transfer + * 0b0..Normal operation + * 0b1..Cancel the remaining data transfer in the same fashion as the CX bit. Stop the executing channel and force the minor loop to finish. The cancel takes effect after the last write of the current read/write sequence. The ECX bit clears itself after the cancel is honored. In addition to cancelling the transfer, ECX treats the cancel as an error condition, thus updating the Error Status register (DMAx_ES) and generating an optional error interrupt. + */ #define DMA_CR_ECX(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ECX_SHIFT)) & DMA_CR_ECX_MASK) #define DMA_CR_CX_MASK (0x20000U) #define DMA_CR_CX_SHIFT (17U) +/*! CX - Cancel Transfer + * 0b0..Normal operation + * 0b1..Cancel the remaining data transfer. Stop the executing channel and force the minor loop to finish. The cancel takes effect after the last write of the current read/write sequence. The CX bit clears itself after the cancel has been honored. This cancel retires the channel normally as if the minor loop was completed. + */ #define DMA_CR_CX(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_CX_SHIFT)) & DMA_CR_CX_MASK) #define DMA_CR_ACTIVE_MASK (0x80000000U) #define DMA_CR_ACTIVE_SHIFT (31U) +/*! ACTIVE - DMA Active Status + * 0b0..eDMA is idle. + * 0b1..eDMA is executing a channel. + */ #define DMA_CR_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ACTIVE_SHIFT)) & DMA_CR_ACTIVE_MASK) +/*! @} */ /*! @name ES - Error Status Register */ +/*! @{ */ #define DMA_ES_DBE_MASK (0x1U) #define DMA_ES_DBE_SHIFT (0U) +/*! DBE - Destination Bus Error + * 0b0..No destination bus error + * 0b1..The last recorded error was a bus error on a destination write + */ #define DMA_ES_DBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DBE_SHIFT)) & DMA_ES_DBE_MASK) #define DMA_ES_SBE_MASK (0x2U) #define DMA_ES_SBE_SHIFT (1U) +/*! SBE - Source Bus Error + * 0b0..No source bus error + * 0b1..The last recorded error was a bus error on a source read + */ #define DMA_ES_SBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SBE_SHIFT)) & DMA_ES_SBE_MASK) #define DMA_ES_SGE_MASK (0x4U) #define DMA_ES_SGE_SHIFT (2U) +/*! SGE - Scatter/Gather Configuration Error + * 0b0..No scatter/gather configuration error + * 0b1..The last recorded error was a configuration error detected in the TCDn_DLASTSGA field. This field is checked at the beginning of a scatter/gather operation after major loop completion if TCDn_CSR[ESG] is enabled. TCDn_DLASTSGA is not on a 32 byte boundary. + */ #define DMA_ES_SGE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SGE_SHIFT)) & DMA_ES_SGE_MASK) #define DMA_ES_NCE_MASK (0x8U) #define DMA_ES_NCE_SHIFT (3U) +/*! NCE - NBYTES/CITER Configuration Error + * 0b0..No NBYTES/CITER configuration error + * 0b1..The last recorded error was a configuration error detected in the TCDn_NBYTES or TCDn_CITER fields. TCDn_NBYTES is not a multiple of TCDn_ATTR[SSIZE] and TCDn_ATTR[DSIZE], or TCDn_CITER[CITER] is equal to zero, or TCDn_CITER[ELINK] is not equal to TCDn_BITER[ELINK] + */ #define DMA_ES_NCE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_NCE_SHIFT)) & DMA_ES_NCE_MASK) #define DMA_ES_DOE_MASK (0x10U) #define DMA_ES_DOE_SHIFT (4U) +/*! DOE - Destination Offset Error + * 0b0..No destination offset configuration error + * 0b1..The last recorded error was a configuration error detected in the TCDn_DOFF field. TCDn_DOFF is inconsistent with TCDn_ATTR[DSIZE]. + */ #define DMA_ES_DOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DOE_SHIFT)) & DMA_ES_DOE_MASK) #define DMA_ES_DAE_MASK (0x20U) #define DMA_ES_DAE_SHIFT (5U) +/*! DAE - Destination Address Error + * 0b0..No destination address configuration error + * 0b1..The last recorded error was a configuration error detected in the TCDn_DADDR field. TCDn_DADDR is inconsistent with TCDn_ATTR[DSIZE]. + */ #define DMA_ES_DAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DAE_SHIFT)) & DMA_ES_DAE_MASK) #define DMA_ES_SOE_MASK (0x40U) #define DMA_ES_SOE_SHIFT (6U) +/*! SOE - Source Offset Error + * 0b0..No source offset configuration error + * 0b1..The last recorded error was a configuration error detected in the TCDn_SOFF field. TCDn_SOFF is inconsistent with TCDn_ATTR[SSIZE]. + */ #define DMA_ES_SOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SOE_SHIFT)) & DMA_ES_SOE_MASK) #define DMA_ES_SAE_MASK (0x80U) #define DMA_ES_SAE_SHIFT (7U) +/*! SAE - Source Address Error + * 0b0..No source address configuration error. + * 0b1..The last recorded error was a configuration error detected in the TCDn_SADDR field. TCDn_SADDR is inconsistent with TCDn_ATTR[SSIZE]. + */ #define DMA_ES_SAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SAE_SHIFT)) & DMA_ES_SAE_MASK) #define DMA_ES_ERRCHN_MASK (0x1F00U) #define DMA_ES_ERRCHN_SHIFT (8U) #define DMA_ES_ERRCHN(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_ERRCHN_SHIFT)) & DMA_ES_ERRCHN_MASK) #define DMA_ES_CPE_MASK (0x4000U) #define DMA_ES_CPE_SHIFT (14U) +/*! CPE - Channel Priority Error + * 0b0..No channel priority error + * 0b1..The last recorded error was a configuration error in the channel priorities within a group. Channel priorities within a group are not unique. + */ #define DMA_ES_CPE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_CPE_SHIFT)) & DMA_ES_CPE_MASK) #define DMA_ES_GPE_MASK (0x8000U) #define DMA_ES_GPE_SHIFT (15U) +/*! GPE - Group Priority Error + * 0b0..No group priority error + * 0b1..The last recorded error was a configuration error among the group priorities. All group priorities are not unique. + */ #define DMA_ES_GPE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_GPE_SHIFT)) & DMA_ES_GPE_MASK) #define DMA_ES_ECX_MASK (0x10000U) #define DMA_ES_ECX_SHIFT (16U) +/*! ECX - Transfer Canceled + * 0b0..No canceled transfers + * 0b1..The last recorded entry was a canceled transfer by the error cancel transfer input + */ #define DMA_ES_ECX(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_ECX_SHIFT)) & DMA_ES_ECX_MASK) #define DMA_ES_VLD_MASK (0x80000000U) #define DMA_ES_VLD_SHIFT (31U) +/*! VLD - VLD + * 0b0..No ERR bits are set. + * 0b1..At least one ERR bit is set indicating a valid error exists that has not been cleared. + */ #define DMA_ES_VLD(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_VLD_SHIFT)) & DMA_ES_VLD_MASK) +/*! @} */ /*! @name ERQ - Enable Request Register */ +/*! @{ */ #define DMA_ERQ_ERQ0_MASK (0x1U) #define DMA_ERQ_ERQ0_SHIFT (0U) +/*! ERQ0 - Enable DMA Request 0 + * 0b0..The DMA request signal for the corresponding channel is disabled + * 0b1..The DMA request signal for the corresponding channel is enabled + */ #define DMA_ERQ_ERQ0(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ0_SHIFT)) & DMA_ERQ_ERQ0_MASK) #define DMA_ERQ_ERQ1_MASK (0x2U) #define DMA_ERQ_ERQ1_SHIFT (1U) +/*! ERQ1 - Enable DMA Request 1 + * 0b0..The DMA request signal for the corresponding channel is disabled + * 0b1..The DMA request signal for the corresponding channel is enabled + */ #define DMA_ERQ_ERQ1(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ1_SHIFT)) & DMA_ERQ_ERQ1_MASK) #define DMA_ERQ_ERQ2_MASK (0x4U) #define DMA_ERQ_ERQ2_SHIFT (2U) +/*! ERQ2 - Enable DMA Request 2 + * 0b0..The DMA request signal for the corresponding channel is disabled + * 0b1..The DMA request signal for the corresponding channel is enabled + */ #define DMA_ERQ_ERQ2(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ2_SHIFT)) & DMA_ERQ_ERQ2_MASK) #define DMA_ERQ_ERQ3_MASK (0x8U) #define DMA_ERQ_ERQ3_SHIFT (3U) +/*! ERQ3 - Enable DMA Request 3 + * 0b0..The DMA request signal for the corresponding channel is disabled + * 0b1..The DMA request signal for the corresponding channel is enabled + */ #define DMA_ERQ_ERQ3(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ3_SHIFT)) & DMA_ERQ_ERQ3_MASK) #define DMA_ERQ_ERQ4_MASK (0x10U) #define DMA_ERQ_ERQ4_SHIFT (4U) +/*! ERQ4 - Enable DMA Request 4 + * 0b0..The DMA request signal for the corresponding channel is disabled + * 0b1..The DMA request signal for the corresponding channel is enabled + */ #define DMA_ERQ_ERQ4(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ4_SHIFT)) & DMA_ERQ_ERQ4_MASK) #define DMA_ERQ_ERQ5_MASK (0x20U) #define DMA_ERQ_ERQ5_SHIFT (5U) +/*! ERQ5 - Enable DMA Request 5 + * 0b0..The DMA request signal for the corresponding channel is disabled + * 0b1..The DMA request signal for the corresponding channel is enabled + */ #define DMA_ERQ_ERQ5(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ5_SHIFT)) & DMA_ERQ_ERQ5_MASK) #define DMA_ERQ_ERQ6_MASK (0x40U) #define DMA_ERQ_ERQ6_SHIFT (6U) +/*! ERQ6 - Enable DMA Request 6 + * 0b0..The DMA request signal for the corresponding channel is disabled + * 0b1..The DMA request signal for the corresponding channel is enabled + */ #define DMA_ERQ_ERQ6(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ6_SHIFT)) & DMA_ERQ_ERQ6_MASK) #define DMA_ERQ_ERQ7_MASK (0x80U) #define DMA_ERQ_ERQ7_SHIFT (7U) +/*! ERQ7 - Enable DMA Request 7 + * 0b0..The DMA request signal for the corresponding channel is disabled + * 0b1..The DMA request signal for the corresponding channel is enabled + */ #define DMA_ERQ_ERQ7(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ7_SHIFT)) & DMA_ERQ_ERQ7_MASK) #define DMA_ERQ_ERQ8_MASK (0x100U) #define DMA_ERQ_ERQ8_SHIFT (8U) +/*! ERQ8 - Enable DMA Request 8 + * 0b0..The DMA request signal for the corresponding channel is disabled + * 0b1..The DMA request signal for the corresponding channel is enabled + */ #define DMA_ERQ_ERQ8(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ8_SHIFT)) & DMA_ERQ_ERQ8_MASK) #define DMA_ERQ_ERQ9_MASK (0x200U) #define DMA_ERQ_ERQ9_SHIFT (9U) +/*! ERQ9 - Enable DMA Request 9 + * 0b0..The DMA request signal for the corresponding channel is disabled + * 0b1..The DMA request signal for the corresponding channel is enabled + */ #define DMA_ERQ_ERQ9(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ9_SHIFT)) & DMA_ERQ_ERQ9_MASK) #define DMA_ERQ_ERQ10_MASK (0x400U) #define DMA_ERQ_ERQ10_SHIFT (10U) +/*! ERQ10 - Enable DMA Request 10 + * 0b0..The DMA request signal for the corresponding channel is disabled + * 0b1..The DMA request signal for the corresponding channel is enabled + */ #define DMA_ERQ_ERQ10(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ10_SHIFT)) & DMA_ERQ_ERQ10_MASK) #define DMA_ERQ_ERQ11_MASK (0x800U) #define DMA_ERQ_ERQ11_SHIFT (11U) +/*! ERQ11 - Enable DMA Request 11 + * 0b0..The DMA request signal for the corresponding channel is disabled + * 0b1..The DMA request signal for the corresponding channel is enabled + */ #define DMA_ERQ_ERQ11(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ11_SHIFT)) & DMA_ERQ_ERQ11_MASK) #define DMA_ERQ_ERQ12_MASK (0x1000U) #define DMA_ERQ_ERQ12_SHIFT (12U) +/*! ERQ12 - Enable DMA Request 12 + * 0b0..The DMA request signal for the corresponding channel is disabled + * 0b1..The DMA request signal for the corresponding channel is enabled + */ #define DMA_ERQ_ERQ12(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ12_SHIFT)) & DMA_ERQ_ERQ12_MASK) #define DMA_ERQ_ERQ13_MASK (0x2000U) #define DMA_ERQ_ERQ13_SHIFT (13U) +/*! ERQ13 - Enable DMA Request 13 + * 0b0..The DMA request signal for the corresponding channel is disabled + * 0b1..The DMA request signal for the corresponding channel is enabled + */ #define DMA_ERQ_ERQ13(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ13_SHIFT)) & DMA_ERQ_ERQ13_MASK) #define DMA_ERQ_ERQ14_MASK (0x4000U) #define DMA_ERQ_ERQ14_SHIFT (14U) +/*! ERQ14 - Enable DMA Request 14 + * 0b0..The DMA request signal for the corresponding channel is disabled + * 0b1..The DMA request signal for the corresponding channel is enabled + */ #define DMA_ERQ_ERQ14(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ14_SHIFT)) & DMA_ERQ_ERQ14_MASK) #define DMA_ERQ_ERQ15_MASK (0x8000U) #define DMA_ERQ_ERQ15_SHIFT (15U) +/*! ERQ15 - Enable DMA Request 15 + * 0b0..The DMA request signal for the corresponding channel is disabled + * 0b1..The DMA request signal for the corresponding channel is enabled + */ #define DMA_ERQ_ERQ15(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ15_SHIFT)) & DMA_ERQ_ERQ15_MASK) #define DMA_ERQ_ERQ16_MASK (0x10000U) #define DMA_ERQ_ERQ16_SHIFT (16U) +/*! ERQ16 - Enable DMA Request 16 + * 0b0..The DMA request signal for the corresponding channel is disabled + * 0b1..The DMA request signal for the corresponding channel is enabled + */ #define DMA_ERQ_ERQ16(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ16_SHIFT)) & DMA_ERQ_ERQ16_MASK) #define DMA_ERQ_ERQ17_MASK (0x20000U) #define DMA_ERQ_ERQ17_SHIFT (17U) +/*! ERQ17 - Enable DMA Request 17 + * 0b0..The DMA request signal for the corresponding channel is disabled + * 0b1..The DMA request signal for the corresponding channel is enabled + */ #define DMA_ERQ_ERQ17(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ17_SHIFT)) & DMA_ERQ_ERQ17_MASK) #define DMA_ERQ_ERQ18_MASK (0x40000U) #define DMA_ERQ_ERQ18_SHIFT (18U) +/*! ERQ18 - Enable DMA Request 18 + * 0b0..The DMA request signal for the corresponding channel is disabled + * 0b1..The DMA request signal for the corresponding channel is enabled + */ #define DMA_ERQ_ERQ18(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ18_SHIFT)) & DMA_ERQ_ERQ18_MASK) #define DMA_ERQ_ERQ19_MASK (0x80000U) #define DMA_ERQ_ERQ19_SHIFT (19U) +/*! ERQ19 - Enable DMA Request 19 + * 0b0..The DMA request signal for the corresponding channel is disabled + * 0b1..The DMA request signal for the corresponding channel is enabled + */ #define DMA_ERQ_ERQ19(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ19_SHIFT)) & DMA_ERQ_ERQ19_MASK) #define DMA_ERQ_ERQ20_MASK (0x100000U) #define DMA_ERQ_ERQ20_SHIFT (20U) +/*! ERQ20 - Enable DMA Request 20 + * 0b0..The DMA request signal for the corresponding channel is disabled + * 0b1..The DMA request signal for the corresponding channel is enabled + */ #define DMA_ERQ_ERQ20(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ20_SHIFT)) & DMA_ERQ_ERQ20_MASK) #define DMA_ERQ_ERQ21_MASK (0x200000U) #define DMA_ERQ_ERQ21_SHIFT (21U) +/*! ERQ21 - Enable DMA Request 21 + * 0b0..The DMA request signal for the corresponding channel is disabled + * 0b1..The DMA request signal for the corresponding channel is enabled + */ #define DMA_ERQ_ERQ21(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ21_SHIFT)) & DMA_ERQ_ERQ21_MASK) #define DMA_ERQ_ERQ22_MASK (0x400000U) #define DMA_ERQ_ERQ22_SHIFT (22U) +/*! ERQ22 - Enable DMA Request 22 + * 0b0..The DMA request signal for the corresponding channel is disabled + * 0b1..The DMA request signal for the corresponding channel is enabled + */ #define DMA_ERQ_ERQ22(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ22_SHIFT)) & DMA_ERQ_ERQ22_MASK) #define DMA_ERQ_ERQ23_MASK (0x800000U) #define DMA_ERQ_ERQ23_SHIFT (23U) +/*! ERQ23 - Enable DMA Request 23 + * 0b0..The DMA request signal for the corresponding channel is disabled + * 0b1..The DMA request signal for the corresponding channel is enabled + */ #define DMA_ERQ_ERQ23(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ23_SHIFT)) & DMA_ERQ_ERQ23_MASK) #define DMA_ERQ_ERQ24_MASK (0x1000000U) #define DMA_ERQ_ERQ24_SHIFT (24U) +/*! ERQ24 - Enable DMA Request 24 + * 0b0..The DMA request signal for the corresponding channel is disabled + * 0b1..The DMA request signal for the corresponding channel is enabled + */ #define DMA_ERQ_ERQ24(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ24_SHIFT)) & DMA_ERQ_ERQ24_MASK) #define DMA_ERQ_ERQ25_MASK (0x2000000U) #define DMA_ERQ_ERQ25_SHIFT (25U) +/*! ERQ25 - Enable DMA Request 25 + * 0b0..The DMA request signal for the corresponding channel is disabled + * 0b1..The DMA request signal for the corresponding channel is enabled + */ #define DMA_ERQ_ERQ25(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ25_SHIFT)) & DMA_ERQ_ERQ25_MASK) #define DMA_ERQ_ERQ26_MASK (0x4000000U) #define DMA_ERQ_ERQ26_SHIFT (26U) +/*! ERQ26 - Enable DMA Request 26 + * 0b0..The DMA request signal for the corresponding channel is disabled + * 0b1..The DMA request signal for the corresponding channel is enabled + */ #define DMA_ERQ_ERQ26(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ26_SHIFT)) & DMA_ERQ_ERQ26_MASK) #define DMA_ERQ_ERQ27_MASK (0x8000000U) #define DMA_ERQ_ERQ27_SHIFT (27U) +/*! ERQ27 - Enable DMA Request 27 + * 0b0..The DMA request signal for the corresponding channel is disabled + * 0b1..The DMA request signal for the corresponding channel is enabled + */ #define DMA_ERQ_ERQ27(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ27_SHIFT)) & DMA_ERQ_ERQ27_MASK) #define DMA_ERQ_ERQ28_MASK (0x10000000U) #define DMA_ERQ_ERQ28_SHIFT (28U) +/*! ERQ28 - Enable DMA Request 28 + * 0b0..The DMA request signal for the corresponding channel is disabled + * 0b1..The DMA request signal for the corresponding channel is enabled + */ #define DMA_ERQ_ERQ28(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ28_SHIFT)) & DMA_ERQ_ERQ28_MASK) #define DMA_ERQ_ERQ29_MASK (0x20000000U) #define DMA_ERQ_ERQ29_SHIFT (29U) +/*! ERQ29 - Enable DMA Request 29 + * 0b0..The DMA request signal for the corresponding channel is disabled + * 0b1..The DMA request signal for the corresponding channel is enabled + */ #define DMA_ERQ_ERQ29(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ29_SHIFT)) & DMA_ERQ_ERQ29_MASK) #define DMA_ERQ_ERQ30_MASK (0x40000000U) #define DMA_ERQ_ERQ30_SHIFT (30U) +/*! ERQ30 - Enable DMA Request 30 + * 0b0..The DMA request signal for the corresponding channel is disabled + * 0b1..The DMA request signal for the corresponding channel is enabled + */ #define DMA_ERQ_ERQ30(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ30_SHIFT)) & DMA_ERQ_ERQ30_MASK) #define DMA_ERQ_ERQ31_MASK (0x80000000U) #define DMA_ERQ_ERQ31_SHIFT (31U) +/*! ERQ31 - Enable DMA Request 31 + * 0b0..The DMA request signal for the corresponding channel is disabled + * 0b1..The DMA request signal for the corresponding channel is enabled + */ #define DMA_ERQ_ERQ31(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ31_SHIFT)) & DMA_ERQ_ERQ31_MASK) +/*! @} */ /*! @name EEI - Enable Error Interrupt Register */ +/*! @{ */ #define DMA_EEI_EEI0_MASK (0x1U) #define DMA_EEI_EEI0_SHIFT (0U) +/*! EEI0 - Enable Error Interrupt 0 + * 0b0..The error signal for corresponding channel does not generate an error interrupt + * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request + */ #define DMA_EEI_EEI0(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI0_SHIFT)) & DMA_EEI_EEI0_MASK) #define DMA_EEI_EEI1_MASK (0x2U) #define DMA_EEI_EEI1_SHIFT (1U) +/*! EEI1 - Enable Error Interrupt 1 + * 0b0..The error signal for corresponding channel does not generate an error interrupt + * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request + */ #define DMA_EEI_EEI1(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI1_SHIFT)) & DMA_EEI_EEI1_MASK) #define DMA_EEI_EEI2_MASK (0x4U) #define DMA_EEI_EEI2_SHIFT (2U) +/*! EEI2 - Enable Error Interrupt 2 + * 0b0..The error signal for corresponding channel does not generate an error interrupt + * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request + */ #define DMA_EEI_EEI2(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI2_SHIFT)) & DMA_EEI_EEI2_MASK) #define DMA_EEI_EEI3_MASK (0x8U) #define DMA_EEI_EEI3_SHIFT (3U) +/*! EEI3 - Enable Error Interrupt 3 + * 0b0..The error signal for corresponding channel does not generate an error interrupt + * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request + */ #define DMA_EEI_EEI3(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI3_SHIFT)) & DMA_EEI_EEI3_MASK) #define DMA_EEI_EEI4_MASK (0x10U) #define DMA_EEI_EEI4_SHIFT (4U) +/*! EEI4 - Enable Error Interrupt 4 + * 0b0..The error signal for corresponding channel does not generate an error interrupt + * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request + */ #define DMA_EEI_EEI4(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI4_SHIFT)) & DMA_EEI_EEI4_MASK) #define DMA_EEI_EEI5_MASK (0x20U) #define DMA_EEI_EEI5_SHIFT (5U) +/*! EEI5 - Enable Error Interrupt 5 + * 0b0..The error signal for corresponding channel does not generate an error interrupt + * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request + */ #define DMA_EEI_EEI5(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI5_SHIFT)) & DMA_EEI_EEI5_MASK) #define DMA_EEI_EEI6_MASK (0x40U) #define DMA_EEI_EEI6_SHIFT (6U) +/*! EEI6 - Enable Error Interrupt 6 + * 0b0..The error signal for corresponding channel does not generate an error interrupt + * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request + */ #define DMA_EEI_EEI6(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI6_SHIFT)) & DMA_EEI_EEI6_MASK) #define DMA_EEI_EEI7_MASK (0x80U) #define DMA_EEI_EEI7_SHIFT (7U) +/*! EEI7 - Enable Error Interrupt 7 + * 0b0..The error signal for corresponding channel does not generate an error interrupt + * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request + */ #define DMA_EEI_EEI7(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI7_SHIFT)) & DMA_EEI_EEI7_MASK) #define DMA_EEI_EEI8_MASK (0x100U) #define DMA_EEI_EEI8_SHIFT (8U) +/*! EEI8 - Enable Error Interrupt 8 + * 0b0..The error signal for corresponding channel does not generate an error interrupt + * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request + */ #define DMA_EEI_EEI8(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI8_SHIFT)) & DMA_EEI_EEI8_MASK) #define DMA_EEI_EEI9_MASK (0x200U) #define DMA_EEI_EEI9_SHIFT (9U) +/*! EEI9 - Enable Error Interrupt 9 + * 0b0..The error signal for corresponding channel does not generate an error interrupt + * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request + */ #define DMA_EEI_EEI9(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI9_SHIFT)) & DMA_EEI_EEI9_MASK) #define DMA_EEI_EEI10_MASK (0x400U) #define DMA_EEI_EEI10_SHIFT (10U) +/*! EEI10 - Enable Error Interrupt 10 + * 0b0..The error signal for corresponding channel does not generate an error interrupt + * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request + */ #define DMA_EEI_EEI10(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI10_SHIFT)) & DMA_EEI_EEI10_MASK) #define DMA_EEI_EEI11_MASK (0x800U) #define DMA_EEI_EEI11_SHIFT (11U) +/*! EEI11 - Enable Error Interrupt 11 + * 0b0..The error signal for corresponding channel does not generate an error interrupt + * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request + */ #define DMA_EEI_EEI11(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI11_SHIFT)) & DMA_EEI_EEI11_MASK) #define DMA_EEI_EEI12_MASK (0x1000U) #define DMA_EEI_EEI12_SHIFT (12U) +/*! EEI12 - Enable Error Interrupt 12 + * 0b0..The error signal for corresponding channel does not generate an error interrupt + * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request + */ #define DMA_EEI_EEI12(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI12_SHIFT)) & DMA_EEI_EEI12_MASK) #define DMA_EEI_EEI13_MASK (0x2000U) #define DMA_EEI_EEI13_SHIFT (13U) +/*! EEI13 - Enable Error Interrupt 13 + * 0b0..The error signal for corresponding channel does not generate an error interrupt + * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request + */ #define DMA_EEI_EEI13(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI13_SHIFT)) & DMA_EEI_EEI13_MASK) #define DMA_EEI_EEI14_MASK (0x4000U) #define DMA_EEI_EEI14_SHIFT (14U) +/*! EEI14 - Enable Error Interrupt 14 + * 0b0..The error signal for corresponding channel does not generate an error interrupt + * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request + */ #define DMA_EEI_EEI14(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI14_SHIFT)) & DMA_EEI_EEI14_MASK) #define DMA_EEI_EEI15_MASK (0x8000U) #define DMA_EEI_EEI15_SHIFT (15U) +/*! EEI15 - Enable Error Interrupt 15 + * 0b0..The error signal for corresponding channel does not generate an error interrupt + * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request + */ #define DMA_EEI_EEI15(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI15_SHIFT)) & DMA_EEI_EEI15_MASK) #define DMA_EEI_EEI16_MASK (0x10000U) #define DMA_EEI_EEI16_SHIFT (16U) +/*! EEI16 - Enable Error Interrupt 16 + * 0b0..The error signal for corresponding channel does not generate an error interrupt + * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request + */ #define DMA_EEI_EEI16(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI16_SHIFT)) & DMA_EEI_EEI16_MASK) #define DMA_EEI_EEI17_MASK (0x20000U) #define DMA_EEI_EEI17_SHIFT (17U) +/*! EEI17 - Enable Error Interrupt 17 + * 0b0..The error signal for corresponding channel does not generate an error interrupt + * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request + */ #define DMA_EEI_EEI17(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI17_SHIFT)) & DMA_EEI_EEI17_MASK) #define DMA_EEI_EEI18_MASK (0x40000U) #define DMA_EEI_EEI18_SHIFT (18U) +/*! EEI18 - Enable Error Interrupt 18 + * 0b0..The error signal for corresponding channel does not generate an error interrupt + * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request + */ #define DMA_EEI_EEI18(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI18_SHIFT)) & DMA_EEI_EEI18_MASK) #define DMA_EEI_EEI19_MASK (0x80000U) #define DMA_EEI_EEI19_SHIFT (19U) +/*! EEI19 - Enable Error Interrupt 19 + * 0b0..The error signal for corresponding channel does not generate an error interrupt + * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request + */ #define DMA_EEI_EEI19(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI19_SHIFT)) & DMA_EEI_EEI19_MASK) #define DMA_EEI_EEI20_MASK (0x100000U) #define DMA_EEI_EEI20_SHIFT (20U) +/*! EEI20 - Enable Error Interrupt 20 + * 0b0..The error signal for corresponding channel does not generate an error interrupt + * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request + */ #define DMA_EEI_EEI20(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI20_SHIFT)) & DMA_EEI_EEI20_MASK) #define DMA_EEI_EEI21_MASK (0x200000U) #define DMA_EEI_EEI21_SHIFT (21U) +/*! EEI21 - Enable Error Interrupt 21 + * 0b0..The error signal for corresponding channel does not generate an error interrupt + * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request + */ #define DMA_EEI_EEI21(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI21_SHIFT)) & DMA_EEI_EEI21_MASK) #define DMA_EEI_EEI22_MASK (0x400000U) #define DMA_EEI_EEI22_SHIFT (22U) +/*! EEI22 - Enable Error Interrupt 22 + * 0b0..The error signal for corresponding channel does not generate an error interrupt + * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request + */ #define DMA_EEI_EEI22(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI22_SHIFT)) & DMA_EEI_EEI22_MASK) #define DMA_EEI_EEI23_MASK (0x800000U) #define DMA_EEI_EEI23_SHIFT (23U) +/*! EEI23 - Enable Error Interrupt 23 + * 0b0..The error signal for corresponding channel does not generate an error interrupt + * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request + */ #define DMA_EEI_EEI23(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI23_SHIFT)) & DMA_EEI_EEI23_MASK) #define DMA_EEI_EEI24_MASK (0x1000000U) #define DMA_EEI_EEI24_SHIFT (24U) +/*! EEI24 - Enable Error Interrupt 24 + * 0b0..The error signal for corresponding channel does not generate an error interrupt + * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request + */ #define DMA_EEI_EEI24(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI24_SHIFT)) & DMA_EEI_EEI24_MASK) #define DMA_EEI_EEI25_MASK (0x2000000U) #define DMA_EEI_EEI25_SHIFT (25U) +/*! EEI25 - Enable Error Interrupt 25 + * 0b0..The error signal for corresponding channel does not generate an error interrupt + * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request + */ #define DMA_EEI_EEI25(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI25_SHIFT)) & DMA_EEI_EEI25_MASK) #define DMA_EEI_EEI26_MASK (0x4000000U) #define DMA_EEI_EEI26_SHIFT (26U) +/*! EEI26 - Enable Error Interrupt 26 + * 0b0..The error signal for corresponding channel does not generate an error interrupt + * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request + */ #define DMA_EEI_EEI26(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI26_SHIFT)) & DMA_EEI_EEI26_MASK) #define DMA_EEI_EEI27_MASK (0x8000000U) #define DMA_EEI_EEI27_SHIFT (27U) +/*! EEI27 - Enable Error Interrupt 27 + * 0b0..The error signal for corresponding channel does not generate an error interrupt + * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request + */ #define DMA_EEI_EEI27(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI27_SHIFT)) & DMA_EEI_EEI27_MASK) #define DMA_EEI_EEI28_MASK (0x10000000U) #define DMA_EEI_EEI28_SHIFT (28U) +/*! EEI28 - Enable Error Interrupt 28 + * 0b0..The error signal for corresponding channel does not generate an error interrupt + * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request + */ #define DMA_EEI_EEI28(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI28_SHIFT)) & DMA_EEI_EEI28_MASK) #define DMA_EEI_EEI29_MASK (0x20000000U) #define DMA_EEI_EEI29_SHIFT (29U) +/*! EEI29 - Enable Error Interrupt 29 + * 0b0..The error signal for corresponding channel does not generate an error interrupt + * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request + */ #define DMA_EEI_EEI29(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI29_SHIFT)) & DMA_EEI_EEI29_MASK) #define DMA_EEI_EEI30_MASK (0x40000000U) #define DMA_EEI_EEI30_SHIFT (30U) +/*! EEI30 - Enable Error Interrupt 30 + * 0b0..The error signal for corresponding channel does not generate an error interrupt + * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request + */ #define DMA_EEI_EEI30(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI30_SHIFT)) & DMA_EEI_EEI30_MASK) #define DMA_EEI_EEI31_MASK (0x80000000U) #define DMA_EEI_EEI31_SHIFT (31U) +/*! EEI31 - Enable Error Interrupt 31 + * 0b0..The error signal for corresponding channel does not generate an error interrupt + * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request + */ #define DMA_EEI_EEI31(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI31_SHIFT)) & DMA_EEI_EEI31_MASK) +/*! @} */ /*! @name CEEI - Clear Enable Error Interrupt Register */ +/*! @{ */ #define DMA_CEEI_CEEI_MASK (0x1FU) #define DMA_CEEI_CEEI_SHIFT (0U) #define DMA_CEEI_CEEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_CEEI_SHIFT)) & DMA_CEEI_CEEI_MASK) #define DMA_CEEI_CAEE_MASK (0x40U) #define DMA_CEEI_CAEE_SHIFT (6U) +/*! CAEE - Clear All Enable Error Interrupts + * 0b0..Clear only the EEI bit specified in the CEEI field + * 0b1..Clear all bits in EEI + */ #define DMA_CEEI_CAEE(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_CAEE_SHIFT)) & DMA_CEEI_CAEE_MASK) #define DMA_CEEI_NOP_MASK (0x80U) #define DMA_CEEI_NOP_SHIFT (7U) +/*! NOP - No Op enable + * 0b0..Normal operation + * 0b1..No operation, ignore the other bits in this register + */ #define DMA_CEEI_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_NOP_SHIFT)) & DMA_CEEI_NOP_MASK) +/*! @} */ /*! @name SEEI - Set Enable Error Interrupt Register */ +/*! @{ */ #define DMA_SEEI_SEEI_MASK (0x1FU) #define DMA_SEEI_SEEI_SHIFT (0U) #define DMA_SEEI_SEEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_SEEI_SHIFT)) & DMA_SEEI_SEEI_MASK) #define DMA_SEEI_SAEE_MASK (0x40U) #define DMA_SEEI_SAEE_SHIFT (6U) +/*! SAEE - Sets All Enable Error Interrupts + * 0b0..Set only the EEI bit specified in the SEEI field. + * 0b1..Sets all bits in EEI + */ #define DMA_SEEI_SAEE(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_SAEE_SHIFT)) & DMA_SEEI_SAEE_MASK) #define DMA_SEEI_NOP_MASK (0x80U) #define DMA_SEEI_NOP_SHIFT (7U) +/*! NOP - No Op enable + * 0b0..Normal operation + * 0b1..No operation, ignore the other bits in this register + */ #define DMA_SEEI_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_NOP_SHIFT)) & DMA_SEEI_NOP_MASK) +/*! @} */ /*! @name CERQ - Clear Enable Request Register */ +/*! @{ */ #define DMA_CERQ_CERQ_MASK (0x1FU) #define DMA_CERQ_CERQ_SHIFT (0U) #define DMA_CERQ_CERQ(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_CERQ_SHIFT)) & DMA_CERQ_CERQ_MASK) #define DMA_CERQ_CAER_MASK (0x40U) #define DMA_CERQ_CAER_SHIFT (6U) +/*! CAER - Clear All Enable Requests + * 0b0..Clear only the ERQ bit specified in the CERQ field + * 0b1..Clear all bits in ERQ + */ #define DMA_CERQ_CAER(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_CAER_SHIFT)) & DMA_CERQ_CAER_MASK) #define DMA_CERQ_NOP_MASK (0x80U) #define DMA_CERQ_NOP_SHIFT (7U) +/*! NOP - No Op enable + * 0b0..Normal operation + * 0b1..No operation, ignore the other bits in this register + */ #define DMA_CERQ_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_NOP_SHIFT)) & DMA_CERQ_NOP_MASK) +/*! @} */ /*! @name SERQ - Set Enable Request Register */ +/*! @{ */ #define DMA_SERQ_SERQ_MASK (0x1FU) #define DMA_SERQ_SERQ_SHIFT (0U) #define DMA_SERQ_SERQ(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_SERQ_SHIFT)) & DMA_SERQ_SERQ_MASK) #define DMA_SERQ_SAER_MASK (0x40U) #define DMA_SERQ_SAER_SHIFT (6U) +/*! SAER - Set All Enable Requests + * 0b0..Set only the ERQ bit specified in the SERQ field + * 0b1..Set all bits in ERQ + */ #define DMA_SERQ_SAER(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_SAER_SHIFT)) & DMA_SERQ_SAER_MASK) #define DMA_SERQ_NOP_MASK (0x80U) #define DMA_SERQ_NOP_SHIFT (7U) +/*! NOP - No Op enable + * 0b0..Normal operation + * 0b1..No operation, ignore the other bits in this register + */ #define DMA_SERQ_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_NOP_SHIFT)) & DMA_SERQ_NOP_MASK) +/*! @} */ /*! @name CDNE - Clear DONE Status Bit Register */ +/*! @{ */ #define DMA_CDNE_CDNE_MASK (0x1FU) #define DMA_CDNE_CDNE_SHIFT (0U) #define DMA_CDNE_CDNE(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_CDNE_SHIFT)) & DMA_CDNE_CDNE_MASK) #define DMA_CDNE_CADN_MASK (0x40U) #define DMA_CDNE_CADN_SHIFT (6U) +/*! CADN - Clears All DONE Bits + * 0b0..Clears only the TCDn_CSR[DONE] bit specified in the CDNE field + * 0b1..Clears all bits in TCDn_CSR[DONE] + */ #define DMA_CDNE_CADN(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_CADN_SHIFT)) & DMA_CDNE_CADN_MASK) #define DMA_CDNE_NOP_MASK (0x80U) #define DMA_CDNE_NOP_SHIFT (7U) +/*! NOP - No Op enable + * 0b0..Normal operation + * 0b1..No operation, ignore the other bits in this register + */ #define DMA_CDNE_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_NOP_SHIFT)) & DMA_CDNE_NOP_MASK) +/*! @} */ /*! @name SSRT - Set START Bit Register */ +/*! @{ */ #define DMA_SSRT_SSRT_MASK (0x1FU) #define DMA_SSRT_SSRT_SHIFT (0U) #define DMA_SSRT_SSRT(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_SSRT_SHIFT)) & DMA_SSRT_SSRT_MASK) #define DMA_SSRT_SAST_MASK (0x40U) #define DMA_SSRT_SAST_SHIFT (6U) +/*! SAST - Set All START Bits (activates all channels) + * 0b0..Set only the TCDn_CSR[START] bit specified in the SSRT field + * 0b1..Set all bits in TCDn_CSR[START] + */ #define DMA_SSRT_SAST(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_SAST_SHIFT)) & DMA_SSRT_SAST_MASK) #define DMA_SSRT_NOP_MASK (0x80U) #define DMA_SSRT_NOP_SHIFT (7U) +/*! NOP - No Op enable + * 0b0..Normal operation + * 0b1..No operation, ignore the other bits in this register + */ #define DMA_SSRT_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_NOP_SHIFT)) & DMA_SSRT_NOP_MASK) +/*! @} */ /*! @name CERR - Clear Error Register */ +/*! @{ */ #define DMA_CERR_CERR_MASK (0x1FU) #define DMA_CERR_CERR_SHIFT (0U) #define DMA_CERR_CERR(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_CERR_SHIFT)) & DMA_CERR_CERR_MASK) #define DMA_CERR_CAEI_MASK (0x40U) #define DMA_CERR_CAEI_SHIFT (6U) +/*! CAEI - Clear All Error Indicators + * 0b0..Clear only the ERR bit specified in the CERR field + * 0b1..Clear all bits in ERR + */ #define DMA_CERR_CAEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_CAEI_SHIFT)) & DMA_CERR_CAEI_MASK) #define DMA_CERR_NOP_MASK (0x80U) #define DMA_CERR_NOP_SHIFT (7U) +/*! NOP - No Op enable + * 0b0..Normal operation + * 0b1..No operation, ignore the other bits in this register + */ #define DMA_CERR_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_NOP_SHIFT)) & DMA_CERR_NOP_MASK) +/*! @} */ /*! @name CINT - Clear Interrupt Request Register */ +/*! @{ */ #define DMA_CINT_CINT_MASK (0x1FU) #define DMA_CINT_CINT_SHIFT (0U) #define DMA_CINT_CINT(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_CINT_SHIFT)) & DMA_CINT_CINT_MASK) #define DMA_CINT_CAIR_MASK (0x40U) #define DMA_CINT_CAIR_SHIFT (6U) +/*! CAIR - Clear All Interrupt Requests + * 0b0..Clear only the INT bit specified in the CINT field + * 0b1..Clear all bits in INT + */ #define DMA_CINT_CAIR(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_CAIR_SHIFT)) & DMA_CINT_CAIR_MASK) #define DMA_CINT_NOP_MASK (0x80U) #define DMA_CINT_NOP_SHIFT (7U) +/*! NOP - No Op enable + * 0b0..Normal operation + * 0b1..No operation, ignore the other bits in this register + */ #define DMA_CINT_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_NOP_SHIFT)) & DMA_CINT_NOP_MASK) +/*! @} */ /*! @name INT - Interrupt Request Register */ +/*! @{ */ #define DMA_INT_INT0_MASK (0x1U) #define DMA_INT_INT0_SHIFT (0U) +/*! INT0 - Interrupt Request 0 + * 0b0..The interrupt request for corresponding channel is cleared + * 0b1..The interrupt request for corresponding channel is active + */ #define DMA_INT_INT0(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT0_SHIFT)) & DMA_INT_INT0_MASK) #define DMA_INT_INT1_MASK (0x2U) #define DMA_INT_INT1_SHIFT (1U) +/*! INT1 - Interrupt Request 1 + * 0b0..The interrupt request for corresponding channel is cleared + * 0b1..The interrupt request for corresponding channel is active + */ #define DMA_INT_INT1(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT1_SHIFT)) & DMA_INT_INT1_MASK) #define DMA_INT_INT2_MASK (0x4U) #define DMA_INT_INT2_SHIFT (2U) +/*! INT2 - Interrupt Request 2 + * 0b0..The interrupt request for corresponding channel is cleared + * 0b1..The interrupt request for corresponding channel is active + */ #define DMA_INT_INT2(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT2_SHIFT)) & DMA_INT_INT2_MASK) #define DMA_INT_INT3_MASK (0x8U) #define DMA_INT_INT3_SHIFT (3U) +/*! INT3 - Interrupt Request 3 + * 0b0..The interrupt request for corresponding channel is cleared + * 0b1..The interrupt request for corresponding channel is active + */ #define DMA_INT_INT3(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT3_SHIFT)) & DMA_INT_INT3_MASK) #define DMA_INT_INT4_MASK (0x10U) #define DMA_INT_INT4_SHIFT (4U) +/*! INT4 - Interrupt Request 4 + * 0b0..The interrupt request for corresponding channel is cleared + * 0b1..The interrupt request for corresponding channel is active + */ #define DMA_INT_INT4(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT4_SHIFT)) & DMA_INT_INT4_MASK) #define DMA_INT_INT5_MASK (0x20U) #define DMA_INT_INT5_SHIFT (5U) +/*! INT5 - Interrupt Request 5 + * 0b0..The interrupt request for corresponding channel is cleared + * 0b1..The interrupt request for corresponding channel is active + */ #define DMA_INT_INT5(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT5_SHIFT)) & DMA_INT_INT5_MASK) #define DMA_INT_INT6_MASK (0x40U) #define DMA_INT_INT6_SHIFT (6U) +/*! INT6 - Interrupt Request 6 + * 0b0..The interrupt request for corresponding channel is cleared + * 0b1..The interrupt request for corresponding channel is active + */ #define DMA_INT_INT6(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT6_SHIFT)) & DMA_INT_INT6_MASK) #define DMA_INT_INT7_MASK (0x80U) #define DMA_INT_INT7_SHIFT (7U) +/*! INT7 - Interrupt Request 7 + * 0b0..The interrupt request for corresponding channel is cleared + * 0b1..The interrupt request for corresponding channel is active + */ #define DMA_INT_INT7(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT7_SHIFT)) & DMA_INT_INT7_MASK) #define DMA_INT_INT8_MASK (0x100U) #define DMA_INT_INT8_SHIFT (8U) +/*! INT8 - Interrupt Request 8 + * 0b0..The interrupt request for corresponding channel is cleared + * 0b1..The interrupt request for corresponding channel is active + */ #define DMA_INT_INT8(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT8_SHIFT)) & DMA_INT_INT8_MASK) #define DMA_INT_INT9_MASK (0x200U) #define DMA_INT_INT9_SHIFT (9U) +/*! INT9 - Interrupt Request 9 + * 0b0..The interrupt request for corresponding channel is cleared + * 0b1..The interrupt request for corresponding channel is active + */ #define DMA_INT_INT9(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT9_SHIFT)) & DMA_INT_INT9_MASK) #define DMA_INT_INT10_MASK (0x400U) #define DMA_INT_INT10_SHIFT (10U) +/*! INT10 - Interrupt Request 10 + * 0b0..The interrupt request for corresponding channel is cleared + * 0b1..The interrupt request for corresponding channel is active + */ #define DMA_INT_INT10(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT10_SHIFT)) & DMA_INT_INT10_MASK) #define DMA_INT_INT11_MASK (0x800U) #define DMA_INT_INT11_SHIFT (11U) +/*! INT11 - Interrupt Request 11 + * 0b0..The interrupt request for corresponding channel is cleared + * 0b1..The interrupt request for corresponding channel is active + */ #define DMA_INT_INT11(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT11_SHIFT)) & DMA_INT_INT11_MASK) #define DMA_INT_INT12_MASK (0x1000U) #define DMA_INT_INT12_SHIFT (12U) +/*! INT12 - Interrupt Request 12 + * 0b0..The interrupt request for corresponding channel is cleared + * 0b1..The interrupt request for corresponding channel is active + */ #define DMA_INT_INT12(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT12_SHIFT)) & DMA_INT_INT12_MASK) #define DMA_INT_INT13_MASK (0x2000U) #define DMA_INT_INT13_SHIFT (13U) +/*! INT13 - Interrupt Request 13 + * 0b0..The interrupt request for corresponding channel is cleared + * 0b1..The interrupt request for corresponding channel is active + */ #define DMA_INT_INT13(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT13_SHIFT)) & DMA_INT_INT13_MASK) #define DMA_INT_INT14_MASK (0x4000U) #define DMA_INT_INT14_SHIFT (14U) +/*! INT14 - Interrupt Request 14 + * 0b0..The interrupt request for corresponding channel is cleared + * 0b1..The interrupt request for corresponding channel is active + */ #define DMA_INT_INT14(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT14_SHIFT)) & DMA_INT_INT14_MASK) #define DMA_INT_INT15_MASK (0x8000U) #define DMA_INT_INT15_SHIFT (15U) +/*! INT15 - Interrupt Request 15 + * 0b0..The interrupt request for corresponding channel is cleared + * 0b1..The interrupt request for corresponding channel is active + */ #define DMA_INT_INT15(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT15_SHIFT)) & DMA_INT_INT15_MASK) #define DMA_INT_INT16_MASK (0x10000U) #define DMA_INT_INT16_SHIFT (16U) +/*! INT16 - Interrupt Request 16 + * 0b0..The interrupt request for corresponding channel is cleared + * 0b1..The interrupt request for corresponding channel is active + */ #define DMA_INT_INT16(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT16_SHIFT)) & DMA_INT_INT16_MASK) #define DMA_INT_INT17_MASK (0x20000U) #define DMA_INT_INT17_SHIFT (17U) +/*! INT17 - Interrupt Request 17 + * 0b0..The interrupt request for corresponding channel is cleared + * 0b1..The interrupt request for corresponding channel is active + */ #define DMA_INT_INT17(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT17_SHIFT)) & DMA_INT_INT17_MASK) #define DMA_INT_INT18_MASK (0x40000U) #define DMA_INT_INT18_SHIFT (18U) +/*! INT18 - Interrupt Request 18 + * 0b0..The interrupt request for corresponding channel is cleared + * 0b1..The interrupt request for corresponding channel is active + */ #define DMA_INT_INT18(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT18_SHIFT)) & DMA_INT_INT18_MASK) #define DMA_INT_INT19_MASK (0x80000U) #define DMA_INT_INT19_SHIFT (19U) +/*! INT19 - Interrupt Request 19 + * 0b0..The interrupt request for corresponding channel is cleared + * 0b1..The interrupt request for corresponding channel is active + */ #define DMA_INT_INT19(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT19_SHIFT)) & DMA_INT_INT19_MASK) #define DMA_INT_INT20_MASK (0x100000U) #define DMA_INT_INT20_SHIFT (20U) +/*! INT20 - Interrupt Request 20 + * 0b0..The interrupt request for corresponding channel is cleared + * 0b1..The interrupt request for corresponding channel is active + */ #define DMA_INT_INT20(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT20_SHIFT)) & DMA_INT_INT20_MASK) #define DMA_INT_INT21_MASK (0x200000U) #define DMA_INT_INT21_SHIFT (21U) +/*! INT21 - Interrupt Request 21 + * 0b0..The interrupt request for corresponding channel is cleared + * 0b1..The interrupt request for corresponding channel is active + */ #define DMA_INT_INT21(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT21_SHIFT)) & DMA_INT_INT21_MASK) #define DMA_INT_INT22_MASK (0x400000U) #define DMA_INT_INT22_SHIFT (22U) +/*! INT22 - Interrupt Request 22 + * 0b0..The interrupt request for corresponding channel is cleared + * 0b1..The interrupt request for corresponding channel is active + */ #define DMA_INT_INT22(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT22_SHIFT)) & DMA_INT_INT22_MASK) #define DMA_INT_INT23_MASK (0x800000U) #define DMA_INT_INT23_SHIFT (23U) +/*! INT23 - Interrupt Request 23 + * 0b0..The interrupt request for corresponding channel is cleared + * 0b1..The interrupt request for corresponding channel is active + */ #define DMA_INT_INT23(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT23_SHIFT)) & DMA_INT_INT23_MASK) #define DMA_INT_INT24_MASK (0x1000000U) #define DMA_INT_INT24_SHIFT (24U) +/*! INT24 - Interrupt Request 24 + * 0b0..The interrupt request for corresponding channel is cleared + * 0b1..The interrupt request for corresponding channel is active + */ #define DMA_INT_INT24(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT24_SHIFT)) & DMA_INT_INT24_MASK) #define DMA_INT_INT25_MASK (0x2000000U) #define DMA_INT_INT25_SHIFT (25U) +/*! INT25 - Interrupt Request 25 + * 0b0..The interrupt request for corresponding channel is cleared + * 0b1..The interrupt request for corresponding channel is active + */ #define DMA_INT_INT25(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT25_SHIFT)) & DMA_INT_INT25_MASK) #define DMA_INT_INT26_MASK (0x4000000U) #define DMA_INT_INT26_SHIFT (26U) +/*! INT26 - Interrupt Request 26 + * 0b0..The interrupt request for corresponding channel is cleared + * 0b1..The interrupt request for corresponding channel is active + */ #define DMA_INT_INT26(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT26_SHIFT)) & DMA_INT_INT26_MASK) #define DMA_INT_INT27_MASK (0x8000000U) #define DMA_INT_INT27_SHIFT (27U) +/*! INT27 - Interrupt Request 27 + * 0b0..The interrupt request for corresponding channel is cleared + * 0b1..The interrupt request for corresponding channel is active + */ #define DMA_INT_INT27(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT27_SHIFT)) & DMA_INT_INT27_MASK) #define DMA_INT_INT28_MASK (0x10000000U) #define DMA_INT_INT28_SHIFT (28U) +/*! INT28 - Interrupt Request 28 + * 0b0..The interrupt request for corresponding channel is cleared + * 0b1..The interrupt request for corresponding channel is active + */ #define DMA_INT_INT28(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT28_SHIFT)) & DMA_INT_INT28_MASK) #define DMA_INT_INT29_MASK (0x20000000U) #define DMA_INT_INT29_SHIFT (29U) +/*! INT29 - Interrupt Request 29 + * 0b0..The interrupt request for corresponding channel is cleared + * 0b1..The interrupt request for corresponding channel is active + */ #define DMA_INT_INT29(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT29_SHIFT)) & DMA_INT_INT29_MASK) #define DMA_INT_INT30_MASK (0x40000000U) #define DMA_INT_INT30_SHIFT (30U) +/*! INT30 - Interrupt Request 30 + * 0b0..The interrupt request for corresponding channel is cleared + * 0b1..The interrupt request for corresponding channel is active + */ #define DMA_INT_INT30(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT30_SHIFT)) & DMA_INT_INT30_MASK) #define DMA_INT_INT31_MASK (0x80000000U) #define DMA_INT_INT31_SHIFT (31U) +/*! INT31 - Interrupt Request 31 + * 0b0..The interrupt request for corresponding channel is cleared + * 0b1..The interrupt request for corresponding channel is active + */ #define DMA_INT_INT31(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT31_SHIFT)) & DMA_INT_INT31_MASK) +/*! @} */ /*! @name ERR - Error Register */ +/*! @{ */ #define DMA_ERR_ERR0_MASK (0x1U) #define DMA_ERR_ERR0_SHIFT (0U) +/*! ERR0 - Error In Channel 0 + * 0b0..An error in this channel has not occurred + * 0b1..An error in this channel has occurred + */ #define DMA_ERR_ERR0(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR0_SHIFT)) & DMA_ERR_ERR0_MASK) #define DMA_ERR_ERR1_MASK (0x2U) #define DMA_ERR_ERR1_SHIFT (1U) +/*! ERR1 - Error In Channel 1 + * 0b0..An error in this channel has not occurred + * 0b1..An error in this channel has occurred + */ #define DMA_ERR_ERR1(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR1_SHIFT)) & DMA_ERR_ERR1_MASK) #define DMA_ERR_ERR2_MASK (0x4U) #define DMA_ERR_ERR2_SHIFT (2U) +/*! ERR2 - Error In Channel 2 + * 0b0..An error in this channel has not occurred + * 0b1..An error in this channel has occurred + */ #define DMA_ERR_ERR2(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR2_SHIFT)) & DMA_ERR_ERR2_MASK) #define DMA_ERR_ERR3_MASK (0x8U) #define DMA_ERR_ERR3_SHIFT (3U) +/*! ERR3 - Error In Channel 3 + * 0b0..An error in this channel has not occurred + * 0b1..An error in this channel has occurred + */ #define DMA_ERR_ERR3(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR3_SHIFT)) & DMA_ERR_ERR3_MASK) #define DMA_ERR_ERR4_MASK (0x10U) #define DMA_ERR_ERR4_SHIFT (4U) +/*! ERR4 - Error In Channel 4 + * 0b0..An error in this channel has not occurred + * 0b1..An error in this channel has occurred + */ #define DMA_ERR_ERR4(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR4_SHIFT)) & DMA_ERR_ERR4_MASK) #define DMA_ERR_ERR5_MASK (0x20U) #define DMA_ERR_ERR5_SHIFT (5U) +/*! ERR5 - Error In Channel 5 + * 0b0..An error in this channel has not occurred + * 0b1..An error in this channel has occurred + */ #define DMA_ERR_ERR5(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR5_SHIFT)) & DMA_ERR_ERR5_MASK) #define DMA_ERR_ERR6_MASK (0x40U) #define DMA_ERR_ERR6_SHIFT (6U) +/*! ERR6 - Error In Channel 6 + * 0b0..An error in this channel has not occurred + * 0b1..An error in this channel has occurred + */ #define DMA_ERR_ERR6(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR6_SHIFT)) & DMA_ERR_ERR6_MASK) #define DMA_ERR_ERR7_MASK (0x80U) #define DMA_ERR_ERR7_SHIFT (7U) +/*! ERR7 - Error In Channel 7 + * 0b0..An error in this channel has not occurred + * 0b1..An error in this channel has occurred + */ #define DMA_ERR_ERR7(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR7_SHIFT)) & DMA_ERR_ERR7_MASK) #define DMA_ERR_ERR8_MASK (0x100U) #define DMA_ERR_ERR8_SHIFT (8U) +/*! ERR8 - Error In Channel 8 + * 0b0..An error in this channel has not occurred + * 0b1..An error in this channel has occurred + */ #define DMA_ERR_ERR8(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR8_SHIFT)) & DMA_ERR_ERR8_MASK) #define DMA_ERR_ERR9_MASK (0x200U) #define DMA_ERR_ERR9_SHIFT (9U) +/*! ERR9 - Error In Channel 9 + * 0b0..An error in this channel has not occurred + * 0b1..An error in this channel has occurred + */ #define DMA_ERR_ERR9(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR9_SHIFT)) & DMA_ERR_ERR9_MASK) #define DMA_ERR_ERR10_MASK (0x400U) #define DMA_ERR_ERR10_SHIFT (10U) +/*! ERR10 - Error In Channel 10 + * 0b0..An error in this channel has not occurred + * 0b1..An error in this channel has occurred + */ #define DMA_ERR_ERR10(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR10_SHIFT)) & DMA_ERR_ERR10_MASK) #define DMA_ERR_ERR11_MASK (0x800U) #define DMA_ERR_ERR11_SHIFT (11U) +/*! ERR11 - Error In Channel 11 + * 0b0..An error in this channel has not occurred + * 0b1..An error in this channel has occurred + */ #define DMA_ERR_ERR11(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR11_SHIFT)) & DMA_ERR_ERR11_MASK) #define DMA_ERR_ERR12_MASK (0x1000U) #define DMA_ERR_ERR12_SHIFT (12U) +/*! ERR12 - Error In Channel 12 + * 0b0..An error in this channel has not occurred + * 0b1..An error in this channel has occurred + */ #define DMA_ERR_ERR12(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR12_SHIFT)) & DMA_ERR_ERR12_MASK) #define DMA_ERR_ERR13_MASK (0x2000U) #define DMA_ERR_ERR13_SHIFT (13U) +/*! ERR13 - Error In Channel 13 + * 0b0..An error in this channel has not occurred + * 0b1..An error in this channel has occurred + */ #define DMA_ERR_ERR13(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR13_SHIFT)) & DMA_ERR_ERR13_MASK) #define DMA_ERR_ERR14_MASK (0x4000U) #define DMA_ERR_ERR14_SHIFT (14U) +/*! ERR14 - Error In Channel 14 + * 0b0..An error in this channel has not occurred + * 0b1..An error in this channel has occurred + */ #define DMA_ERR_ERR14(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR14_SHIFT)) & DMA_ERR_ERR14_MASK) #define DMA_ERR_ERR15_MASK (0x8000U) #define DMA_ERR_ERR15_SHIFT (15U) +/*! ERR15 - Error In Channel 15 + * 0b0..An error in this channel has not occurred + * 0b1..An error in this channel has occurred + */ #define DMA_ERR_ERR15(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR15_SHIFT)) & DMA_ERR_ERR15_MASK) #define DMA_ERR_ERR16_MASK (0x10000U) #define DMA_ERR_ERR16_SHIFT (16U) +/*! ERR16 - Error In Channel 16 + * 0b0..An error in this channel has not occurred + * 0b1..An error in this channel has occurred + */ #define DMA_ERR_ERR16(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR16_SHIFT)) & DMA_ERR_ERR16_MASK) #define DMA_ERR_ERR17_MASK (0x20000U) #define DMA_ERR_ERR17_SHIFT (17U) +/*! ERR17 - Error In Channel 17 + * 0b0..An error in this channel has not occurred + * 0b1..An error in this channel has occurred + */ #define DMA_ERR_ERR17(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR17_SHIFT)) & DMA_ERR_ERR17_MASK) #define DMA_ERR_ERR18_MASK (0x40000U) #define DMA_ERR_ERR18_SHIFT (18U) +/*! ERR18 - Error In Channel 18 + * 0b0..An error in this channel has not occurred + * 0b1..An error in this channel has occurred + */ #define DMA_ERR_ERR18(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR18_SHIFT)) & DMA_ERR_ERR18_MASK) #define DMA_ERR_ERR19_MASK (0x80000U) #define DMA_ERR_ERR19_SHIFT (19U) +/*! ERR19 - Error In Channel 19 + * 0b0..An error in this channel has not occurred + * 0b1..An error in this channel has occurred + */ #define DMA_ERR_ERR19(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR19_SHIFT)) & DMA_ERR_ERR19_MASK) #define DMA_ERR_ERR20_MASK (0x100000U) #define DMA_ERR_ERR20_SHIFT (20U) +/*! ERR20 - Error In Channel 20 + * 0b0..An error in this channel has not occurred + * 0b1..An error in this channel has occurred + */ #define DMA_ERR_ERR20(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR20_SHIFT)) & DMA_ERR_ERR20_MASK) #define DMA_ERR_ERR21_MASK (0x200000U) #define DMA_ERR_ERR21_SHIFT (21U) +/*! ERR21 - Error In Channel 21 + * 0b0..An error in this channel has not occurred + * 0b1..An error in this channel has occurred + */ #define DMA_ERR_ERR21(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR21_SHIFT)) & DMA_ERR_ERR21_MASK) #define DMA_ERR_ERR22_MASK (0x400000U) #define DMA_ERR_ERR22_SHIFT (22U) +/*! ERR22 - Error In Channel 22 + * 0b0..An error in this channel has not occurred + * 0b1..An error in this channel has occurred + */ #define DMA_ERR_ERR22(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR22_SHIFT)) & DMA_ERR_ERR22_MASK) #define DMA_ERR_ERR23_MASK (0x800000U) #define DMA_ERR_ERR23_SHIFT (23U) +/*! ERR23 - Error In Channel 23 + * 0b0..An error in this channel has not occurred + * 0b1..An error in this channel has occurred + */ #define DMA_ERR_ERR23(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR23_SHIFT)) & DMA_ERR_ERR23_MASK) #define DMA_ERR_ERR24_MASK (0x1000000U) #define DMA_ERR_ERR24_SHIFT (24U) +/*! ERR24 - Error In Channel 24 + * 0b0..An error in this channel has not occurred + * 0b1..An error in this channel has occurred + */ #define DMA_ERR_ERR24(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR24_SHIFT)) & DMA_ERR_ERR24_MASK) #define DMA_ERR_ERR25_MASK (0x2000000U) #define DMA_ERR_ERR25_SHIFT (25U) +/*! ERR25 - Error In Channel 25 + * 0b0..An error in this channel has not occurred + * 0b1..An error in this channel has occurred + */ #define DMA_ERR_ERR25(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR25_SHIFT)) & DMA_ERR_ERR25_MASK) #define DMA_ERR_ERR26_MASK (0x4000000U) #define DMA_ERR_ERR26_SHIFT (26U) +/*! ERR26 - Error In Channel 26 + * 0b0..An error in this channel has not occurred + * 0b1..An error in this channel has occurred + */ #define DMA_ERR_ERR26(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR26_SHIFT)) & DMA_ERR_ERR26_MASK) #define DMA_ERR_ERR27_MASK (0x8000000U) #define DMA_ERR_ERR27_SHIFT (27U) +/*! ERR27 - Error In Channel 27 + * 0b0..An error in this channel has not occurred + * 0b1..An error in this channel has occurred + */ #define DMA_ERR_ERR27(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR27_SHIFT)) & DMA_ERR_ERR27_MASK) #define DMA_ERR_ERR28_MASK (0x10000000U) #define DMA_ERR_ERR28_SHIFT (28U) +/*! ERR28 - Error In Channel 28 + * 0b0..An error in this channel has not occurred + * 0b1..An error in this channel has occurred + */ #define DMA_ERR_ERR28(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR28_SHIFT)) & DMA_ERR_ERR28_MASK) #define DMA_ERR_ERR29_MASK (0x20000000U) #define DMA_ERR_ERR29_SHIFT (29U) +/*! ERR29 - Error In Channel 29 + * 0b0..An error in this channel has not occurred + * 0b1..An error in this channel has occurred + */ #define DMA_ERR_ERR29(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR29_SHIFT)) & DMA_ERR_ERR29_MASK) #define DMA_ERR_ERR30_MASK (0x40000000U) #define DMA_ERR_ERR30_SHIFT (30U) +/*! ERR30 - Error In Channel 30 + * 0b0..An error in this channel has not occurred + * 0b1..An error in this channel has occurred + */ #define DMA_ERR_ERR30(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR30_SHIFT)) & DMA_ERR_ERR30_MASK) #define DMA_ERR_ERR31_MASK (0x80000000U) #define DMA_ERR_ERR31_SHIFT (31U) +/*! ERR31 - Error In Channel 31 + * 0b0..An error in this channel has not occurred + * 0b1..An error in this channel has occurred + */ #define DMA_ERR_ERR31(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR31_SHIFT)) & DMA_ERR_ERR31_MASK) +/*! @} */ /*! @name HRS - Hardware Request Status Register */ +/*! @{ */ #define DMA_HRS_HRS0_MASK (0x1U) #define DMA_HRS_HRS0_SHIFT (0U) +/*! HRS0 - Hardware Request Status Channel 0 + * 0b0..A hardware service request for channel 0 is not present + * 0b1..A hardware service request for channel 0 is present + */ #define DMA_HRS_HRS0(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS0_SHIFT)) & DMA_HRS_HRS0_MASK) #define DMA_HRS_HRS1_MASK (0x2U) #define DMA_HRS_HRS1_SHIFT (1U) +/*! HRS1 - Hardware Request Status Channel 1 + * 0b0..A hardware service request for channel 1 is not present + * 0b1..A hardware service request for channel 1 is present + */ #define DMA_HRS_HRS1(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS1_SHIFT)) & DMA_HRS_HRS1_MASK) #define DMA_HRS_HRS2_MASK (0x4U) #define DMA_HRS_HRS2_SHIFT (2U) +/*! HRS2 - Hardware Request Status Channel 2 + * 0b0..A hardware service request for channel 2 is not present + * 0b1..A hardware service request for channel 2 is present + */ #define DMA_HRS_HRS2(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS2_SHIFT)) & DMA_HRS_HRS2_MASK) #define DMA_HRS_HRS3_MASK (0x8U) #define DMA_HRS_HRS3_SHIFT (3U) +/*! HRS3 - Hardware Request Status Channel 3 + * 0b0..A hardware service request for channel 3 is not present + * 0b1..A hardware service request for channel 3 is present + */ #define DMA_HRS_HRS3(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS3_SHIFT)) & DMA_HRS_HRS3_MASK) #define DMA_HRS_HRS4_MASK (0x10U) #define DMA_HRS_HRS4_SHIFT (4U) +/*! HRS4 - Hardware Request Status Channel 4 + * 0b0..A hardware service request for channel 4 is not present + * 0b1..A hardware service request for channel 4 is present + */ #define DMA_HRS_HRS4(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS4_SHIFT)) & DMA_HRS_HRS4_MASK) #define DMA_HRS_HRS5_MASK (0x20U) #define DMA_HRS_HRS5_SHIFT (5U) +/*! HRS5 - Hardware Request Status Channel 5 + * 0b0..A hardware service request for channel 5 is not present + * 0b1..A hardware service request for channel 5 is present + */ #define DMA_HRS_HRS5(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS5_SHIFT)) & DMA_HRS_HRS5_MASK) #define DMA_HRS_HRS6_MASK (0x40U) #define DMA_HRS_HRS6_SHIFT (6U) +/*! HRS6 - Hardware Request Status Channel 6 + * 0b0..A hardware service request for channel 6 is not present + * 0b1..A hardware service request for channel 6 is present + */ #define DMA_HRS_HRS6(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS6_SHIFT)) & DMA_HRS_HRS6_MASK) #define DMA_HRS_HRS7_MASK (0x80U) #define DMA_HRS_HRS7_SHIFT (7U) +/*! HRS7 - Hardware Request Status Channel 7 + * 0b0..A hardware service request for channel 7 is not present + * 0b1..A hardware service request for channel 7 is present + */ #define DMA_HRS_HRS7(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS7_SHIFT)) & DMA_HRS_HRS7_MASK) #define DMA_HRS_HRS8_MASK (0x100U) #define DMA_HRS_HRS8_SHIFT (8U) +/*! HRS8 - Hardware Request Status Channel 8 + * 0b0..A hardware service request for channel 8 is not present + * 0b1..A hardware service request for channel 8 is present + */ #define DMA_HRS_HRS8(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS8_SHIFT)) & DMA_HRS_HRS8_MASK) #define DMA_HRS_HRS9_MASK (0x200U) #define DMA_HRS_HRS9_SHIFT (9U) +/*! HRS9 - Hardware Request Status Channel 9 + * 0b0..A hardware service request for channel 9 is not present + * 0b1..A hardware service request for channel 9 is present + */ #define DMA_HRS_HRS9(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS9_SHIFT)) & DMA_HRS_HRS9_MASK) #define DMA_HRS_HRS10_MASK (0x400U) #define DMA_HRS_HRS10_SHIFT (10U) +/*! HRS10 - Hardware Request Status Channel 10 + * 0b0..A hardware service request for channel 10 is not present + * 0b1..A hardware service request for channel 10 is present + */ #define DMA_HRS_HRS10(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS10_SHIFT)) & DMA_HRS_HRS10_MASK) #define DMA_HRS_HRS11_MASK (0x800U) #define DMA_HRS_HRS11_SHIFT (11U) +/*! HRS11 - Hardware Request Status Channel 11 + * 0b0..A hardware service request for channel 11 is not present + * 0b1..A hardware service request for channel 11 is present + */ #define DMA_HRS_HRS11(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS11_SHIFT)) & DMA_HRS_HRS11_MASK) #define DMA_HRS_HRS12_MASK (0x1000U) #define DMA_HRS_HRS12_SHIFT (12U) +/*! HRS12 - Hardware Request Status Channel 12 + * 0b0..A hardware service request for channel 12 is not present + * 0b1..A hardware service request for channel 12 is present + */ #define DMA_HRS_HRS12(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS12_SHIFT)) & DMA_HRS_HRS12_MASK) #define DMA_HRS_HRS13_MASK (0x2000U) #define DMA_HRS_HRS13_SHIFT (13U) +/*! HRS13 - Hardware Request Status Channel 13 + * 0b0..A hardware service request for channel 13 is not present + * 0b1..A hardware service request for channel 13 is present + */ #define DMA_HRS_HRS13(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS13_SHIFT)) & DMA_HRS_HRS13_MASK) #define DMA_HRS_HRS14_MASK (0x4000U) #define DMA_HRS_HRS14_SHIFT (14U) +/*! HRS14 - Hardware Request Status Channel 14 + * 0b0..A hardware service request for channel 14 is not present + * 0b1..A hardware service request for channel 14 is present + */ #define DMA_HRS_HRS14(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS14_SHIFT)) & DMA_HRS_HRS14_MASK) #define DMA_HRS_HRS15_MASK (0x8000U) #define DMA_HRS_HRS15_SHIFT (15U) +/*! HRS15 - Hardware Request Status Channel 15 + * 0b0..A hardware service request for channel 15 is not present + * 0b1..A hardware service request for channel 15 is present + */ #define DMA_HRS_HRS15(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS15_SHIFT)) & DMA_HRS_HRS15_MASK) #define DMA_HRS_HRS16_MASK (0x10000U) #define DMA_HRS_HRS16_SHIFT (16U) +/*! HRS16 - Hardware Request Status Channel 16 + * 0b0..A hardware service request for channel 16 is not present + * 0b1..A hardware service request for channel 16 is present + */ #define DMA_HRS_HRS16(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS16_SHIFT)) & DMA_HRS_HRS16_MASK) #define DMA_HRS_HRS17_MASK (0x20000U) #define DMA_HRS_HRS17_SHIFT (17U) +/*! HRS17 - Hardware Request Status Channel 17 + * 0b0..A hardware service request for channel 17 is not present + * 0b1..A hardware service request for channel 17 is present + */ #define DMA_HRS_HRS17(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS17_SHIFT)) & DMA_HRS_HRS17_MASK) #define DMA_HRS_HRS18_MASK (0x40000U) #define DMA_HRS_HRS18_SHIFT (18U) +/*! HRS18 - Hardware Request Status Channel 18 + * 0b0..A hardware service request for channel 18 is not present + * 0b1..A hardware service request for channel 18 is present + */ #define DMA_HRS_HRS18(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS18_SHIFT)) & DMA_HRS_HRS18_MASK) #define DMA_HRS_HRS19_MASK (0x80000U) #define DMA_HRS_HRS19_SHIFT (19U) +/*! HRS19 - Hardware Request Status Channel 19 + * 0b0..A hardware service request for channel 19 is not present + * 0b1..A hardware service request for channel 19 is present + */ #define DMA_HRS_HRS19(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS19_SHIFT)) & DMA_HRS_HRS19_MASK) #define DMA_HRS_HRS20_MASK (0x100000U) #define DMA_HRS_HRS20_SHIFT (20U) +/*! HRS20 - Hardware Request Status Channel 20 + * 0b0..A hardware service request for channel 20 is not present + * 0b1..A hardware service request for channel 20 is present + */ #define DMA_HRS_HRS20(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS20_SHIFT)) & DMA_HRS_HRS20_MASK) #define DMA_HRS_HRS21_MASK (0x200000U) #define DMA_HRS_HRS21_SHIFT (21U) +/*! HRS21 - Hardware Request Status Channel 21 + * 0b0..A hardware service request for channel 21 is not present + * 0b1..A hardware service request for channel 21 is present + */ #define DMA_HRS_HRS21(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS21_SHIFT)) & DMA_HRS_HRS21_MASK) #define DMA_HRS_HRS22_MASK (0x400000U) #define DMA_HRS_HRS22_SHIFT (22U) +/*! HRS22 - Hardware Request Status Channel 22 + * 0b0..A hardware service request for channel 22 is not present + * 0b1..A hardware service request for channel 22 is present + */ #define DMA_HRS_HRS22(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS22_SHIFT)) & DMA_HRS_HRS22_MASK) #define DMA_HRS_HRS23_MASK (0x800000U) #define DMA_HRS_HRS23_SHIFT (23U) +/*! HRS23 - Hardware Request Status Channel 23 + * 0b0..A hardware service request for channel 23 is not present + * 0b1..A hardware service request for channel 23 is present + */ #define DMA_HRS_HRS23(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS23_SHIFT)) & DMA_HRS_HRS23_MASK) #define DMA_HRS_HRS24_MASK (0x1000000U) #define DMA_HRS_HRS24_SHIFT (24U) +/*! HRS24 - Hardware Request Status Channel 24 + * 0b0..A hardware service request for channel 24 is not present + * 0b1..A hardware service request for channel 24 is present + */ #define DMA_HRS_HRS24(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS24_SHIFT)) & DMA_HRS_HRS24_MASK) #define DMA_HRS_HRS25_MASK (0x2000000U) #define DMA_HRS_HRS25_SHIFT (25U) +/*! HRS25 - Hardware Request Status Channel 25 + * 0b0..A hardware service request for channel 25 is not present + * 0b1..A hardware service request for channel 25 is present + */ #define DMA_HRS_HRS25(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS25_SHIFT)) & DMA_HRS_HRS25_MASK) #define DMA_HRS_HRS26_MASK (0x4000000U) #define DMA_HRS_HRS26_SHIFT (26U) +/*! HRS26 - Hardware Request Status Channel 26 + * 0b0..A hardware service request for channel 26 is not present + * 0b1..A hardware service request for channel 26 is present + */ #define DMA_HRS_HRS26(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS26_SHIFT)) & DMA_HRS_HRS26_MASK) #define DMA_HRS_HRS27_MASK (0x8000000U) #define DMA_HRS_HRS27_SHIFT (27U) +/*! HRS27 - Hardware Request Status Channel 27 + * 0b0..A hardware service request for channel 27 is not present + * 0b1..A hardware service request for channel 27 is present + */ #define DMA_HRS_HRS27(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS27_SHIFT)) & DMA_HRS_HRS27_MASK) #define DMA_HRS_HRS28_MASK (0x10000000U) #define DMA_HRS_HRS28_SHIFT (28U) +/*! HRS28 - Hardware Request Status Channel 28 + * 0b0..A hardware service request for channel 28 is not present + * 0b1..A hardware service request for channel 28 is present + */ #define DMA_HRS_HRS28(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS28_SHIFT)) & DMA_HRS_HRS28_MASK) #define DMA_HRS_HRS29_MASK (0x20000000U) #define DMA_HRS_HRS29_SHIFT (29U) +/*! HRS29 - Hardware Request Status Channel 29 + * 0b0..A hardware service request for channel 29 is not preset + * 0b1..A hardware service request for channel 29 is present + */ #define DMA_HRS_HRS29(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS29_SHIFT)) & DMA_HRS_HRS29_MASK) #define DMA_HRS_HRS30_MASK (0x40000000U) #define DMA_HRS_HRS30_SHIFT (30U) +/*! HRS30 - Hardware Request Status Channel 30 + * 0b0..A hardware service request for channel 30 is not present + * 0b1..A hardware service request for channel 30 is present + */ #define DMA_HRS_HRS30(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS30_SHIFT)) & DMA_HRS_HRS30_MASK) #define DMA_HRS_HRS31_MASK (0x80000000U) #define DMA_HRS_HRS31_SHIFT (31U) +/*! HRS31 - Hardware Request Status Channel 31 + * 0b0..A hardware service request for channel 31 is not present + * 0b1..A hardware service request for channel 31 is present + */ #define DMA_HRS_HRS31(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS31_SHIFT)) & DMA_HRS_HRS31_MASK) +/*! @} */ /*! @name EARS - Enable Asynchronous Request in Stop Register */ +/*! @{ */ #define DMA_EARS_EDREQ_0_MASK (0x1U) #define DMA_EARS_EDREQ_0_SHIFT (0U) +/*! EDREQ_0 - Enable asynchronous DMA request in stop mode for channel 0. + * 0b0..Disable asynchronous DMA request for channel 0. + * 0b1..Enable asynchronous DMA request for channel 0. + */ #define DMA_EARS_EDREQ_0(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_0_SHIFT)) & DMA_EARS_EDREQ_0_MASK) #define DMA_EARS_EDREQ_1_MASK (0x2U) #define DMA_EARS_EDREQ_1_SHIFT (1U) +/*! EDREQ_1 - Enable asynchronous DMA request in stop mode for channel 1. + * 0b0..Disable asynchronous DMA request for channel 1 + * 0b1..Enable asynchronous DMA request for channel 1. + */ #define DMA_EARS_EDREQ_1(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_1_SHIFT)) & DMA_EARS_EDREQ_1_MASK) #define DMA_EARS_EDREQ_2_MASK (0x4U) #define DMA_EARS_EDREQ_2_SHIFT (2U) +/*! EDREQ_2 - Enable asynchronous DMA request in stop mode for channel 2. + * 0b0..Disable asynchronous DMA request for channel 2. + * 0b1..Enable asynchronous DMA request for channel 2. + */ #define DMA_EARS_EDREQ_2(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_2_SHIFT)) & DMA_EARS_EDREQ_2_MASK) #define DMA_EARS_EDREQ_3_MASK (0x8U) #define DMA_EARS_EDREQ_3_SHIFT (3U) +/*! EDREQ_3 - Enable asynchronous DMA request in stop mode for channel 3. + * 0b0..Disable asynchronous DMA request for channel 3. + * 0b1..Enable asynchronous DMA request for channel 3. + */ #define DMA_EARS_EDREQ_3(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_3_SHIFT)) & DMA_EARS_EDREQ_3_MASK) #define DMA_EARS_EDREQ_4_MASK (0x10U) #define DMA_EARS_EDREQ_4_SHIFT (4U) +/*! EDREQ_4 - Enable asynchronous DMA request in stop mode for channel 4 + * 0b0..Disable asynchronous DMA request for channel 4. + * 0b1..Enable asynchronous DMA request for channel 4. + */ #define DMA_EARS_EDREQ_4(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_4_SHIFT)) & DMA_EARS_EDREQ_4_MASK) #define DMA_EARS_EDREQ_5_MASK (0x20U) #define DMA_EARS_EDREQ_5_SHIFT (5U) +/*! EDREQ_5 - Enable asynchronous DMA request in stop mode for channel 5 + * 0b0..Disable asynchronous DMA request for channel 5. + * 0b1..Enable asynchronous DMA request for channel 5. + */ #define DMA_EARS_EDREQ_5(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_5_SHIFT)) & DMA_EARS_EDREQ_5_MASK) #define DMA_EARS_EDREQ_6_MASK (0x40U) #define DMA_EARS_EDREQ_6_SHIFT (6U) +/*! EDREQ_6 - Enable asynchronous DMA request in stop mode for channel 6 + * 0b0..Disable asynchronous DMA request for channel 6. + * 0b1..Enable asynchronous DMA request for channel 6. + */ #define DMA_EARS_EDREQ_6(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_6_SHIFT)) & DMA_EARS_EDREQ_6_MASK) #define DMA_EARS_EDREQ_7_MASK (0x80U) #define DMA_EARS_EDREQ_7_SHIFT (7U) +/*! EDREQ_7 - Enable asynchronous DMA request in stop mode for channel 7 + * 0b0..Disable asynchronous DMA request for channel 7. + * 0b1..Enable asynchronous DMA request for channel 7. + */ #define DMA_EARS_EDREQ_7(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_7_SHIFT)) & DMA_EARS_EDREQ_7_MASK) #define DMA_EARS_EDREQ_8_MASK (0x100U) #define DMA_EARS_EDREQ_8_SHIFT (8U) +/*! EDREQ_8 - Enable asynchronous DMA request in stop mode for channel 8 + * 0b0..Disable asynchronous DMA request for channel 8. + * 0b1..Enable asynchronous DMA request for channel 8. + */ #define DMA_EARS_EDREQ_8(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_8_SHIFT)) & DMA_EARS_EDREQ_8_MASK) #define DMA_EARS_EDREQ_9_MASK (0x200U) #define DMA_EARS_EDREQ_9_SHIFT (9U) +/*! EDREQ_9 - Enable asynchronous DMA request in stop mode for channel 9 + * 0b0..Disable asynchronous DMA request for channel 9. + * 0b1..Enable asynchronous DMA request for channel 9. + */ #define DMA_EARS_EDREQ_9(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_9_SHIFT)) & DMA_EARS_EDREQ_9_MASK) #define DMA_EARS_EDREQ_10_MASK (0x400U) #define DMA_EARS_EDREQ_10_SHIFT (10U) +/*! EDREQ_10 - Enable asynchronous DMA request in stop mode for channel 10 + * 0b0..Disable asynchronous DMA request for channel 10. + * 0b1..Enable asynchronous DMA request for channel 10. + */ #define DMA_EARS_EDREQ_10(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_10_SHIFT)) & DMA_EARS_EDREQ_10_MASK) #define DMA_EARS_EDREQ_11_MASK (0x800U) #define DMA_EARS_EDREQ_11_SHIFT (11U) +/*! EDREQ_11 - Enable asynchronous DMA request in stop mode for channel 11 + * 0b0..Disable asynchronous DMA request for channel 11. + * 0b1..Enable asynchronous DMA request for channel 11. + */ #define DMA_EARS_EDREQ_11(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_11_SHIFT)) & DMA_EARS_EDREQ_11_MASK) #define DMA_EARS_EDREQ_12_MASK (0x1000U) #define DMA_EARS_EDREQ_12_SHIFT (12U) +/*! EDREQ_12 - Enable asynchronous DMA request in stop mode for channel 12 + * 0b0..Disable asynchronous DMA request for channel 12. + * 0b1..Enable asynchronous DMA request for channel 12. + */ #define DMA_EARS_EDREQ_12(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_12_SHIFT)) & DMA_EARS_EDREQ_12_MASK) #define DMA_EARS_EDREQ_13_MASK (0x2000U) #define DMA_EARS_EDREQ_13_SHIFT (13U) +/*! EDREQ_13 - Enable asynchronous DMA request in stop mode for channel 13 + * 0b0..Disable asynchronous DMA request for channel 13. + * 0b1..Enable asynchronous DMA request for channel 13. + */ #define DMA_EARS_EDREQ_13(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_13_SHIFT)) & DMA_EARS_EDREQ_13_MASK) #define DMA_EARS_EDREQ_14_MASK (0x4000U) #define DMA_EARS_EDREQ_14_SHIFT (14U) +/*! EDREQ_14 - Enable asynchronous DMA request in stop mode for channel 14 + * 0b0..Disable asynchronous DMA request for channel 14. + * 0b1..Enable asynchronous DMA request for channel 14. + */ #define DMA_EARS_EDREQ_14(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_14_SHIFT)) & DMA_EARS_EDREQ_14_MASK) #define DMA_EARS_EDREQ_15_MASK (0x8000U) #define DMA_EARS_EDREQ_15_SHIFT (15U) +/*! EDREQ_15 - Enable asynchronous DMA request in stop mode for channel 15 + * 0b0..Disable asynchronous DMA request for channel 15. + * 0b1..Enable asynchronous DMA request for channel 15. + */ #define DMA_EARS_EDREQ_15(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_15_SHIFT)) & DMA_EARS_EDREQ_15_MASK) #define DMA_EARS_EDREQ_16_MASK (0x10000U) #define DMA_EARS_EDREQ_16_SHIFT (16U) +/*! EDREQ_16 - Enable asynchronous DMA request in stop mode for channel 16 + * 0b0..Disable asynchronous DMA request for channel 16 + * 0b1..Enable asynchronous DMA request for channel 16 + */ #define DMA_EARS_EDREQ_16(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_16_SHIFT)) & DMA_EARS_EDREQ_16_MASK) #define DMA_EARS_EDREQ_17_MASK (0x20000U) #define DMA_EARS_EDREQ_17_SHIFT (17U) +/*! EDREQ_17 - Enable asynchronous DMA request in stop mode for channel 17 + * 0b0..Disable asynchronous DMA request for channel 17 + * 0b1..Enable asynchronous DMA request for channel 17 + */ #define DMA_EARS_EDREQ_17(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_17_SHIFT)) & DMA_EARS_EDREQ_17_MASK) #define DMA_EARS_EDREQ_18_MASK (0x40000U) #define DMA_EARS_EDREQ_18_SHIFT (18U) +/*! EDREQ_18 - Enable asynchronous DMA request in stop mode for channel 18 + * 0b0..Disable asynchronous DMA request for channel 18 + * 0b1..Enable asynchronous DMA request for channel 18 + */ #define DMA_EARS_EDREQ_18(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_18_SHIFT)) & DMA_EARS_EDREQ_18_MASK) #define DMA_EARS_EDREQ_19_MASK (0x80000U) #define DMA_EARS_EDREQ_19_SHIFT (19U) +/*! EDREQ_19 - Enable asynchronous DMA request in stop mode for channel 19 + * 0b0..Disable asynchronous DMA request for channel 19 + * 0b1..Enable asynchronous DMA request for channel 19 + */ #define DMA_EARS_EDREQ_19(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_19_SHIFT)) & DMA_EARS_EDREQ_19_MASK) #define DMA_EARS_EDREQ_20_MASK (0x100000U) #define DMA_EARS_EDREQ_20_SHIFT (20U) +/*! EDREQ_20 - Enable asynchronous DMA request in stop mode for channel 20 + * 0b0..Disable asynchronous DMA request for channel 20 + * 0b1..Enable asynchronous DMA request for channel 20 + */ #define DMA_EARS_EDREQ_20(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_20_SHIFT)) & DMA_EARS_EDREQ_20_MASK) #define DMA_EARS_EDREQ_21_MASK (0x200000U) #define DMA_EARS_EDREQ_21_SHIFT (21U) +/*! EDREQ_21 - Enable asynchronous DMA request in stop mode for channel 21 + * 0b0..Disable asynchronous DMA request for channel 21 + * 0b1..Enable asynchronous DMA request for channel 21 + */ #define DMA_EARS_EDREQ_21(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_21_SHIFT)) & DMA_EARS_EDREQ_21_MASK) #define DMA_EARS_EDREQ_22_MASK (0x400000U) #define DMA_EARS_EDREQ_22_SHIFT (22U) +/*! EDREQ_22 - Enable asynchronous DMA request in stop mode for channel 22 + * 0b0..Disable asynchronous DMA request for channel 22 + * 0b1..Enable asynchronous DMA request for channel 22 + */ #define DMA_EARS_EDREQ_22(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_22_SHIFT)) & DMA_EARS_EDREQ_22_MASK) #define DMA_EARS_EDREQ_23_MASK (0x800000U) #define DMA_EARS_EDREQ_23_SHIFT (23U) +/*! EDREQ_23 - Enable asynchronous DMA request in stop mode for channel 23 + * 0b0..Disable asynchronous DMA request for channel 23 + * 0b1..Enable asynchronous DMA request for channel 23 + */ #define DMA_EARS_EDREQ_23(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_23_SHIFT)) & DMA_EARS_EDREQ_23_MASK) #define DMA_EARS_EDREQ_24_MASK (0x1000000U) #define DMA_EARS_EDREQ_24_SHIFT (24U) +/*! EDREQ_24 - Enable asynchronous DMA request in stop mode for channel 24 + * 0b0..Disable asynchronous DMA request for channel 24 + * 0b1..Enable asynchronous DMA request for channel 24 + */ #define DMA_EARS_EDREQ_24(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_24_SHIFT)) & DMA_EARS_EDREQ_24_MASK) #define DMA_EARS_EDREQ_25_MASK (0x2000000U) #define DMA_EARS_EDREQ_25_SHIFT (25U) +/*! EDREQ_25 - Enable asynchronous DMA request in stop mode for channel 25 + * 0b0..Disable asynchronous DMA request for channel 25 + * 0b1..Enable asynchronous DMA request for channel 25 + */ #define DMA_EARS_EDREQ_25(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_25_SHIFT)) & DMA_EARS_EDREQ_25_MASK) #define DMA_EARS_EDREQ_26_MASK (0x4000000U) #define DMA_EARS_EDREQ_26_SHIFT (26U) +/*! EDREQ_26 - Enable asynchronous DMA request in stop mode for channel 26 + * 0b0..Disable asynchronous DMA request for channel 26 + * 0b1..Enable asynchronous DMA request for channel 26 + */ #define DMA_EARS_EDREQ_26(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_26_SHIFT)) & DMA_EARS_EDREQ_26_MASK) #define DMA_EARS_EDREQ_27_MASK (0x8000000U) #define DMA_EARS_EDREQ_27_SHIFT (27U) +/*! EDREQ_27 - Enable asynchronous DMA request in stop mode for channel 27 + * 0b0..Disable asynchronous DMA request for channel 27 + * 0b1..Enable asynchronous DMA request for channel 27 + */ #define DMA_EARS_EDREQ_27(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_27_SHIFT)) & DMA_EARS_EDREQ_27_MASK) #define DMA_EARS_EDREQ_28_MASK (0x10000000U) #define DMA_EARS_EDREQ_28_SHIFT (28U) +/*! EDREQ_28 - Enable asynchronous DMA request in stop mode for channel 28 + * 0b0..Disable asynchronous DMA request for channel 28 + * 0b1..Enable asynchronous DMA request for channel 28 + */ #define DMA_EARS_EDREQ_28(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_28_SHIFT)) & DMA_EARS_EDREQ_28_MASK) #define DMA_EARS_EDREQ_29_MASK (0x20000000U) #define DMA_EARS_EDREQ_29_SHIFT (29U) +/*! EDREQ_29 - Enable asynchronous DMA request in stop mode for channel 29 + * 0b0..Disable asynchronous DMA request for channel 29 + * 0b1..Enable asynchronous DMA request for channel 29 + */ #define DMA_EARS_EDREQ_29(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_29_SHIFT)) & DMA_EARS_EDREQ_29_MASK) #define DMA_EARS_EDREQ_30_MASK (0x40000000U) #define DMA_EARS_EDREQ_30_SHIFT (30U) +/*! EDREQ_30 - Enable asynchronous DMA request in stop mode for channel 30 + * 0b0..Disable asynchronous DMA request for channel 30 + * 0b1..Enable asynchronous DMA request for channel 30 + */ #define DMA_EARS_EDREQ_30(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_30_SHIFT)) & DMA_EARS_EDREQ_30_MASK) #define DMA_EARS_EDREQ_31_MASK (0x80000000U) #define DMA_EARS_EDREQ_31_SHIFT (31U) +/*! EDREQ_31 - Enable asynchronous DMA request in stop mode for channel 31 + * 0b0..Disable asynchronous DMA request for channel 31 + * 0b1..Enable asynchronous DMA request for channel 31 + */ #define DMA_EARS_EDREQ_31(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_31_SHIFT)) & DMA_EARS_EDREQ_31_MASK) +/*! @} */ /*! @name DCHPRI3 - Channel n Priority Register */ +/*! @{ */ #define DMA_DCHPRI3_CHPRI_MASK (0xFU) #define DMA_DCHPRI3_CHPRI_SHIFT (0U) #define DMA_DCHPRI3_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_CHPRI_SHIFT)) & DMA_DCHPRI3_CHPRI_MASK) @@ -7816,12 +12113,22 @@ typedef struct { #define DMA_DCHPRI3_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_GRPPRI_SHIFT)) & DMA_DCHPRI3_GRPPRI_MASK) #define DMA_DCHPRI3_DPA_MASK (0x40U) #define DMA_DCHPRI3_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability. This field resets to 0. + * 0b0..Channel n can suspend a lower priority channel. + * 0b1..Channel n cannot suspend any channel, regardless of channel priority. + */ #define DMA_DCHPRI3_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_DPA_SHIFT)) & DMA_DCHPRI3_DPA_MASK) #define DMA_DCHPRI3_ECP_MASK (0x80U) #define DMA_DCHPRI3_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption. This field resets to 0. + * 0b0..Channel n cannot be suspended by a higher priority channel's service request. + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. + */ #define DMA_DCHPRI3_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_ECP_SHIFT)) & DMA_DCHPRI3_ECP_MASK) +/*! @} */ /*! @name DCHPRI2 - Channel n Priority Register */ +/*! @{ */ #define DMA_DCHPRI2_CHPRI_MASK (0xFU) #define DMA_DCHPRI2_CHPRI_SHIFT (0U) #define DMA_DCHPRI2_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_CHPRI_SHIFT)) & DMA_DCHPRI2_CHPRI_MASK) @@ -7830,12 +12137,22 @@ typedef struct { #define DMA_DCHPRI2_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_GRPPRI_SHIFT)) & DMA_DCHPRI2_GRPPRI_MASK) #define DMA_DCHPRI2_DPA_MASK (0x40U) #define DMA_DCHPRI2_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability. This field resets to 0. + * 0b0..Channel n can suspend a lower priority channel. + * 0b1..Channel n cannot suspend any channel, regardless of channel priority. + */ #define DMA_DCHPRI2_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_DPA_SHIFT)) & DMA_DCHPRI2_DPA_MASK) #define DMA_DCHPRI2_ECP_MASK (0x80U) #define DMA_DCHPRI2_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption. This field resets to 0. + * 0b0..Channel n cannot be suspended by a higher priority channel's service request. + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. + */ #define DMA_DCHPRI2_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_ECP_SHIFT)) & DMA_DCHPRI2_ECP_MASK) +/*! @} */ /*! @name DCHPRI1 - Channel n Priority Register */ +/*! @{ */ #define DMA_DCHPRI1_CHPRI_MASK (0xFU) #define DMA_DCHPRI1_CHPRI_SHIFT (0U) #define DMA_DCHPRI1_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_CHPRI_SHIFT)) & DMA_DCHPRI1_CHPRI_MASK) @@ -7844,12 +12161,22 @@ typedef struct { #define DMA_DCHPRI1_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_GRPPRI_SHIFT)) & DMA_DCHPRI1_GRPPRI_MASK) #define DMA_DCHPRI1_DPA_MASK (0x40U) #define DMA_DCHPRI1_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability. This field resets to 0. + * 0b0..Channel n can suspend a lower priority channel. + * 0b1..Channel n cannot suspend any channel, regardless of channel priority. + */ #define DMA_DCHPRI1_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_DPA_SHIFT)) & DMA_DCHPRI1_DPA_MASK) #define DMA_DCHPRI1_ECP_MASK (0x80U) #define DMA_DCHPRI1_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption. This field resets to 0. + * 0b0..Channel n cannot be suspended by a higher priority channel's service request. + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. + */ #define DMA_DCHPRI1_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_ECP_SHIFT)) & DMA_DCHPRI1_ECP_MASK) +/*! @} */ /*! @name DCHPRI0 - Channel n Priority Register */ +/*! @{ */ #define DMA_DCHPRI0_CHPRI_MASK (0xFU) #define DMA_DCHPRI0_CHPRI_SHIFT (0U) #define DMA_DCHPRI0_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_CHPRI_SHIFT)) & DMA_DCHPRI0_CHPRI_MASK) @@ -7858,12 +12185,22 @@ typedef struct { #define DMA_DCHPRI0_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_GRPPRI_SHIFT)) & DMA_DCHPRI0_GRPPRI_MASK) #define DMA_DCHPRI0_DPA_MASK (0x40U) #define DMA_DCHPRI0_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability. This field resets to 0. + * 0b0..Channel n can suspend a lower priority channel. + * 0b1..Channel n cannot suspend any channel, regardless of channel priority. + */ #define DMA_DCHPRI0_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_DPA_SHIFT)) & DMA_DCHPRI0_DPA_MASK) #define DMA_DCHPRI0_ECP_MASK (0x80U) #define DMA_DCHPRI0_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption. This field resets to 0. + * 0b0..Channel n cannot be suspended by a higher priority channel's service request. + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. + */ #define DMA_DCHPRI0_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_ECP_SHIFT)) & DMA_DCHPRI0_ECP_MASK) +/*! @} */ /*! @name DCHPRI7 - Channel n Priority Register */ +/*! @{ */ #define DMA_DCHPRI7_CHPRI_MASK (0xFU) #define DMA_DCHPRI7_CHPRI_SHIFT (0U) #define DMA_DCHPRI7_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_CHPRI_SHIFT)) & DMA_DCHPRI7_CHPRI_MASK) @@ -7872,12 +12209,22 @@ typedef struct { #define DMA_DCHPRI7_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_GRPPRI_SHIFT)) & DMA_DCHPRI7_GRPPRI_MASK) #define DMA_DCHPRI7_DPA_MASK (0x40U) #define DMA_DCHPRI7_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability. This field resets to 0. + * 0b0..Channel n can suspend a lower priority channel. + * 0b1..Channel n cannot suspend any channel, regardless of channel priority. + */ #define DMA_DCHPRI7_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_DPA_SHIFT)) & DMA_DCHPRI7_DPA_MASK) #define DMA_DCHPRI7_ECP_MASK (0x80U) #define DMA_DCHPRI7_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption. This field resets to 0. + * 0b0..Channel n cannot be suspended by a higher priority channel's service request. + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. + */ #define DMA_DCHPRI7_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_ECP_SHIFT)) & DMA_DCHPRI7_ECP_MASK) +/*! @} */ /*! @name DCHPRI6 - Channel n Priority Register */ +/*! @{ */ #define DMA_DCHPRI6_CHPRI_MASK (0xFU) #define DMA_DCHPRI6_CHPRI_SHIFT (0U) #define DMA_DCHPRI6_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_CHPRI_SHIFT)) & DMA_DCHPRI6_CHPRI_MASK) @@ -7886,12 +12233,22 @@ typedef struct { #define DMA_DCHPRI6_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_GRPPRI_SHIFT)) & DMA_DCHPRI6_GRPPRI_MASK) #define DMA_DCHPRI6_DPA_MASK (0x40U) #define DMA_DCHPRI6_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability. This field resets to 0. + * 0b0..Channel n can suspend a lower priority channel. + * 0b1..Channel n cannot suspend any channel, regardless of channel priority. + */ #define DMA_DCHPRI6_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_DPA_SHIFT)) & DMA_DCHPRI6_DPA_MASK) #define DMA_DCHPRI6_ECP_MASK (0x80U) #define DMA_DCHPRI6_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption. This field resets to 0. + * 0b0..Channel n cannot be suspended by a higher priority channel's service request. + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. + */ #define DMA_DCHPRI6_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_ECP_SHIFT)) & DMA_DCHPRI6_ECP_MASK) +/*! @} */ /*! @name DCHPRI5 - Channel n Priority Register */ +/*! @{ */ #define DMA_DCHPRI5_CHPRI_MASK (0xFU) #define DMA_DCHPRI5_CHPRI_SHIFT (0U) #define DMA_DCHPRI5_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_CHPRI_SHIFT)) & DMA_DCHPRI5_CHPRI_MASK) @@ -7900,12 +12257,22 @@ typedef struct { #define DMA_DCHPRI5_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_GRPPRI_SHIFT)) & DMA_DCHPRI5_GRPPRI_MASK) #define DMA_DCHPRI5_DPA_MASK (0x40U) #define DMA_DCHPRI5_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability. This field resets to 0. + * 0b0..Channel n can suspend a lower priority channel. + * 0b1..Channel n cannot suspend any channel, regardless of channel priority. + */ #define DMA_DCHPRI5_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_DPA_SHIFT)) & DMA_DCHPRI5_DPA_MASK) #define DMA_DCHPRI5_ECP_MASK (0x80U) #define DMA_DCHPRI5_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption. This field resets to 0. + * 0b0..Channel n cannot be suspended by a higher priority channel's service request. + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. + */ #define DMA_DCHPRI5_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_ECP_SHIFT)) & DMA_DCHPRI5_ECP_MASK) +/*! @} */ /*! @name DCHPRI4 - Channel n Priority Register */ +/*! @{ */ #define DMA_DCHPRI4_CHPRI_MASK (0xFU) #define DMA_DCHPRI4_CHPRI_SHIFT (0U) #define DMA_DCHPRI4_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_CHPRI_SHIFT)) & DMA_DCHPRI4_CHPRI_MASK) @@ -7914,12 +12281,22 @@ typedef struct { #define DMA_DCHPRI4_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_GRPPRI_SHIFT)) & DMA_DCHPRI4_GRPPRI_MASK) #define DMA_DCHPRI4_DPA_MASK (0x40U) #define DMA_DCHPRI4_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability. This field resets to 0. + * 0b0..Channel n can suspend a lower priority channel. + * 0b1..Channel n cannot suspend any channel, regardless of channel priority. + */ #define DMA_DCHPRI4_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_DPA_SHIFT)) & DMA_DCHPRI4_DPA_MASK) #define DMA_DCHPRI4_ECP_MASK (0x80U) #define DMA_DCHPRI4_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption. This field resets to 0. + * 0b0..Channel n cannot be suspended by a higher priority channel's service request. + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. + */ #define DMA_DCHPRI4_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_ECP_SHIFT)) & DMA_DCHPRI4_ECP_MASK) +/*! @} */ /*! @name DCHPRI11 - Channel n Priority Register */ +/*! @{ */ #define DMA_DCHPRI11_CHPRI_MASK (0xFU) #define DMA_DCHPRI11_CHPRI_SHIFT (0U) #define DMA_DCHPRI11_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_CHPRI_SHIFT)) & DMA_DCHPRI11_CHPRI_MASK) @@ -7928,12 +12305,22 @@ typedef struct { #define DMA_DCHPRI11_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_GRPPRI_SHIFT)) & DMA_DCHPRI11_GRPPRI_MASK) #define DMA_DCHPRI11_DPA_MASK (0x40U) #define DMA_DCHPRI11_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability. This field resets to 0. + * 0b0..Channel n can suspend a lower priority channel. + * 0b1..Channel n cannot suspend any channel, regardless of channel priority. + */ #define DMA_DCHPRI11_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_DPA_SHIFT)) & DMA_DCHPRI11_DPA_MASK) #define DMA_DCHPRI11_ECP_MASK (0x80U) #define DMA_DCHPRI11_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption. This field resets to 0. + * 0b0..Channel n cannot be suspended by a higher priority channel's service request. + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. + */ #define DMA_DCHPRI11_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_ECP_SHIFT)) & DMA_DCHPRI11_ECP_MASK) +/*! @} */ /*! @name DCHPRI10 - Channel n Priority Register */ +/*! @{ */ #define DMA_DCHPRI10_CHPRI_MASK (0xFU) #define DMA_DCHPRI10_CHPRI_SHIFT (0U) #define DMA_DCHPRI10_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_CHPRI_SHIFT)) & DMA_DCHPRI10_CHPRI_MASK) @@ -7942,12 +12329,22 @@ typedef struct { #define DMA_DCHPRI10_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_GRPPRI_SHIFT)) & DMA_DCHPRI10_GRPPRI_MASK) #define DMA_DCHPRI10_DPA_MASK (0x40U) #define DMA_DCHPRI10_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability. This field resets to 0. + * 0b0..Channel n can suspend a lower priority channel. + * 0b1..Channel n cannot suspend any channel, regardless of channel priority. + */ #define DMA_DCHPRI10_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_DPA_SHIFT)) & DMA_DCHPRI10_DPA_MASK) #define DMA_DCHPRI10_ECP_MASK (0x80U) #define DMA_DCHPRI10_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption. This field resets to 0. + * 0b0..Channel n cannot be suspended by a higher priority channel's service request. + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. + */ #define DMA_DCHPRI10_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_ECP_SHIFT)) & DMA_DCHPRI10_ECP_MASK) +/*! @} */ /*! @name DCHPRI9 - Channel n Priority Register */ +/*! @{ */ #define DMA_DCHPRI9_CHPRI_MASK (0xFU) #define DMA_DCHPRI9_CHPRI_SHIFT (0U) #define DMA_DCHPRI9_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_CHPRI_SHIFT)) & DMA_DCHPRI9_CHPRI_MASK) @@ -7956,12 +12353,22 @@ typedef struct { #define DMA_DCHPRI9_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_GRPPRI_SHIFT)) & DMA_DCHPRI9_GRPPRI_MASK) #define DMA_DCHPRI9_DPA_MASK (0x40U) #define DMA_DCHPRI9_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability. This field resets to 0. + * 0b0..Channel n can suspend a lower priority channel. + * 0b1..Channel n cannot suspend any channel, regardless of channel priority. + */ #define DMA_DCHPRI9_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_DPA_SHIFT)) & DMA_DCHPRI9_DPA_MASK) #define DMA_DCHPRI9_ECP_MASK (0x80U) #define DMA_DCHPRI9_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption. This field resets to 0. + * 0b0..Channel n cannot be suspended by a higher priority channel's service request. + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. + */ #define DMA_DCHPRI9_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_ECP_SHIFT)) & DMA_DCHPRI9_ECP_MASK) +/*! @} */ /*! @name DCHPRI8 - Channel n Priority Register */ +/*! @{ */ #define DMA_DCHPRI8_CHPRI_MASK (0xFU) #define DMA_DCHPRI8_CHPRI_SHIFT (0U) #define DMA_DCHPRI8_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_CHPRI_SHIFT)) & DMA_DCHPRI8_CHPRI_MASK) @@ -7970,12 +12377,22 @@ typedef struct { #define DMA_DCHPRI8_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_GRPPRI_SHIFT)) & DMA_DCHPRI8_GRPPRI_MASK) #define DMA_DCHPRI8_DPA_MASK (0x40U) #define DMA_DCHPRI8_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability. This field resets to 0. + * 0b0..Channel n can suspend a lower priority channel. + * 0b1..Channel n cannot suspend any channel, regardless of channel priority. + */ #define DMA_DCHPRI8_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_DPA_SHIFT)) & DMA_DCHPRI8_DPA_MASK) #define DMA_DCHPRI8_ECP_MASK (0x80U) #define DMA_DCHPRI8_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption. This field resets to 0. + * 0b0..Channel n cannot be suspended by a higher priority channel's service request. + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. + */ #define DMA_DCHPRI8_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_ECP_SHIFT)) & DMA_DCHPRI8_ECP_MASK) +/*! @} */ /*! @name DCHPRI15 - Channel n Priority Register */ +/*! @{ */ #define DMA_DCHPRI15_CHPRI_MASK (0xFU) #define DMA_DCHPRI15_CHPRI_SHIFT (0U) #define DMA_DCHPRI15_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_CHPRI_SHIFT)) & DMA_DCHPRI15_CHPRI_MASK) @@ -7984,12 +12401,22 @@ typedef struct { #define DMA_DCHPRI15_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_GRPPRI_SHIFT)) & DMA_DCHPRI15_GRPPRI_MASK) #define DMA_DCHPRI15_DPA_MASK (0x40U) #define DMA_DCHPRI15_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability. This field resets to 0. + * 0b0..Channel n can suspend a lower priority channel. + * 0b1..Channel n cannot suspend any channel, regardless of channel priority. + */ #define DMA_DCHPRI15_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_DPA_SHIFT)) & DMA_DCHPRI15_DPA_MASK) #define DMA_DCHPRI15_ECP_MASK (0x80U) #define DMA_DCHPRI15_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption. This field resets to 0. + * 0b0..Channel n cannot be suspended by a higher priority channel's service request. + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. + */ #define DMA_DCHPRI15_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_ECP_SHIFT)) & DMA_DCHPRI15_ECP_MASK) +/*! @} */ /*! @name DCHPRI14 - Channel n Priority Register */ +/*! @{ */ #define DMA_DCHPRI14_CHPRI_MASK (0xFU) #define DMA_DCHPRI14_CHPRI_SHIFT (0U) #define DMA_DCHPRI14_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_CHPRI_SHIFT)) & DMA_DCHPRI14_CHPRI_MASK) @@ -7998,12 +12425,22 @@ typedef struct { #define DMA_DCHPRI14_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_GRPPRI_SHIFT)) & DMA_DCHPRI14_GRPPRI_MASK) #define DMA_DCHPRI14_DPA_MASK (0x40U) #define DMA_DCHPRI14_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability. This field resets to 0. + * 0b0..Channel n can suspend a lower priority channel. + * 0b1..Channel n cannot suspend any channel, regardless of channel priority. + */ #define DMA_DCHPRI14_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_DPA_SHIFT)) & DMA_DCHPRI14_DPA_MASK) #define DMA_DCHPRI14_ECP_MASK (0x80U) #define DMA_DCHPRI14_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption. This field resets to 0. + * 0b0..Channel n cannot be suspended by a higher priority channel's service request. + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. + */ #define DMA_DCHPRI14_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_ECP_SHIFT)) & DMA_DCHPRI14_ECP_MASK) +/*! @} */ /*! @name DCHPRI13 - Channel n Priority Register */ +/*! @{ */ #define DMA_DCHPRI13_CHPRI_MASK (0xFU) #define DMA_DCHPRI13_CHPRI_SHIFT (0U) #define DMA_DCHPRI13_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_CHPRI_SHIFT)) & DMA_DCHPRI13_CHPRI_MASK) @@ -8012,12 +12449,22 @@ typedef struct { #define DMA_DCHPRI13_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_GRPPRI_SHIFT)) & DMA_DCHPRI13_GRPPRI_MASK) #define DMA_DCHPRI13_DPA_MASK (0x40U) #define DMA_DCHPRI13_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability. This field resets to 0. + * 0b0..Channel n can suspend a lower priority channel. + * 0b1..Channel n cannot suspend any channel, regardless of channel priority. + */ #define DMA_DCHPRI13_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_DPA_SHIFT)) & DMA_DCHPRI13_DPA_MASK) #define DMA_DCHPRI13_ECP_MASK (0x80U) #define DMA_DCHPRI13_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption. This field resets to 0. + * 0b0..Channel n cannot be suspended by a higher priority channel's service request. + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. + */ #define DMA_DCHPRI13_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_ECP_SHIFT)) & DMA_DCHPRI13_ECP_MASK) +/*! @} */ /*! @name DCHPRI12 - Channel n Priority Register */ +/*! @{ */ #define DMA_DCHPRI12_CHPRI_MASK (0xFU) #define DMA_DCHPRI12_CHPRI_SHIFT (0U) #define DMA_DCHPRI12_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_CHPRI_SHIFT)) & DMA_DCHPRI12_CHPRI_MASK) @@ -8026,12 +12473,22 @@ typedef struct { #define DMA_DCHPRI12_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_GRPPRI_SHIFT)) & DMA_DCHPRI12_GRPPRI_MASK) #define DMA_DCHPRI12_DPA_MASK (0x40U) #define DMA_DCHPRI12_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability. This field resets to 0. + * 0b0..Channel n can suspend a lower priority channel. + * 0b1..Channel n cannot suspend any channel, regardless of channel priority. + */ #define DMA_DCHPRI12_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_DPA_SHIFT)) & DMA_DCHPRI12_DPA_MASK) #define DMA_DCHPRI12_ECP_MASK (0x80U) #define DMA_DCHPRI12_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption. This field resets to 0. + * 0b0..Channel n cannot be suspended by a higher priority channel's service request. + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. + */ #define DMA_DCHPRI12_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_ECP_SHIFT)) & DMA_DCHPRI12_ECP_MASK) +/*! @} */ /*! @name DCHPRI19 - Channel n Priority Register */ +/*! @{ */ #define DMA_DCHPRI19_CHPRI_MASK (0xFU) #define DMA_DCHPRI19_CHPRI_SHIFT (0U) #define DMA_DCHPRI19_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_CHPRI_SHIFT)) & DMA_DCHPRI19_CHPRI_MASK) @@ -8040,12 +12497,22 @@ typedef struct { #define DMA_DCHPRI19_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_GRPPRI_SHIFT)) & DMA_DCHPRI19_GRPPRI_MASK) #define DMA_DCHPRI19_DPA_MASK (0x40U) #define DMA_DCHPRI19_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability. This field resets to 0. + * 0b0..Channel n can suspend a lower priority channel. + * 0b1..Channel n cannot suspend any channel, regardless of channel priority. + */ #define DMA_DCHPRI19_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_DPA_SHIFT)) & DMA_DCHPRI19_DPA_MASK) #define DMA_DCHPRI19_ECP_MASK (0x80U) #define DMA_DCHPRI19_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption. This field resets to 0. + * 0b0..Channel n cannot be suspended by a higher priority channel's service request. + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. + */ #define DMA_DCHPRI19_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_ECP_SHIFT)) & DMA_DCHPRI19_ECP_MASK) +/*! @} */ /*! @name DCHPRI18 - Channel n Priority Register */ +/*! @{ */ #define DMA_DCHPRI18_CHPRI_MASK (0xFU) #define DMA_DCHPRI18_CHPRI_SHIFT (0U) #define DMA_DCHPRI18_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_CHPRI_SHIFT)) & DMA_DCHPRI18_CHPRI_MASK) @@ -8054,12 +12521,22 @@ typedef struct { #define DMA_DCHPRI18_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_GRPPRI_SHIFT)) & DMA_DCHPRI18_GRPPRI_MASK) #define DMA_DCHPRI18_DPA_MASK (0x40U) #define DMA_DCHPRI18_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability. This field resets to 0. + * 0b0..Channel n can suspend a lower priority channel. + * 0b1..Channel n cannot suspend any channel, regardless of channel priority. + */ #define DMA_DCHPRI18_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_DPA_SHIFT)) & DMA_DCHPRI18_DPA_MASK) #define DMA_DCHPRI18_ECP_MASK (0x80U) #define DMA_DCHPRI18_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption. This field resets to 0. + * 0b0..Channel n cannot be suspended by a higher priority channel's service request. + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. + */ #define DMA_DCHPRI18_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_ECP_SHIFT)) & DMA_DCHPRI18_ECP_MASK) +/*! @} */ /*! @name DCHPRI17 - Channel n Priority Register */ +/*! @{ */ #define DMA_DCHPRI17_CHPRI_MASK (0xFU) #define DMA_DCHPRI17_CHPRI_SHIFT (0U) #define DMA_DCHPRI17_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_CHPRI_SHIFT)) & DMA_DCHPRI17_CHPRI_MASK) @@ -8068,12 +12545,22 @@ typedef struct { #define DMA_DCHPRI17_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_GRPPRI_SHIFT)) & DMA_DCHPRI17_GRPPRI_MASK) #define DMA_DCHPRI17_DPA_MASK (0x40U) #define DMA_DCHPRI17_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability. This field resets to 0. + * 0b0..Channel n can suspend a lower priority channel. + * 0b1..Channel n cannot suspend any channel, regardless of channel priority. + */ #define DMA_DCHPRI17_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_DPA_SHIFT)) & DMA_DCHPRI17_DPA_MASK) #define DMA_DCHPRI17_ECP_MASK (0x80U) #define DMA_DCHPRI17_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption. This field resets to 0. + * 0b0..Channel n cannot be suspended by a higher priority channel's service request. + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. + */ #define DMA_DCHPRI17_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_ECP_SHIFT)) & DMA_DCHPRI17_ECP_MASK) +/*! @} */ /*! @name DCHPRI16 - Channel n Priority Register */ +/*! @{ */ #define DMA_DCHPRI16_CHPRI_MASK (0xFU) #define DMA_DCHPRI16_CHPRI_SHIFT (0U) #define DMA_DCHPRI16_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_CHPRI_SHIFT)) & DMA_DCHPRI16_CHPRI_MASK) @@ -8082,12 +12569,22 @@ typedef struct { #define DMA_DCHPRI16_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_GRPPRI_SHIFT)) & DMA_DCHPRI16_GRPPRI_MASK) #define DMA_DCHPRI16_DPA_MASK (0x40U) #define DMA_DCHPRI16_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability. This field resets to 0. + * 0b0..Channel n can suspend a lower priority channel. + * 0b1..Channel n cannot suspend any channel, regardless of channel priority. + */ #define DMA_DCHPRI16_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_DPA_SHIFT)) & DMA_DCHPRI16_DPA_MASK) #define DMA_DCHPRI16_ECP_MASK (0x80U) #define DMA_DCHPRI16_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption. This field resets to 0. + * 0b0..Channel n cannot be suspended by a higher priority channel's service request. + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. + */ #define DMA_DCHPRI16_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_ECP_SHIFT)) & DMA_DCHPRI16_ECP_MASK) +/*! @} */ /*! @name DCHPRI23 - Channel n Priority Register */ +/*! @{ */ #define DMA_DCHPRI23_CHPRI_MASK (0xFU) #define DMA_DCHPRI23_CHPRI_SHIFT (0U) #define DMA_DCHPRI23_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_CHPRI_SHIFT)) & DMA_DCHPRI23_CHPRI_MASK) @@ -8096,12 +12593,22 @@ typedef struct { #define DMA_DCHPRI23_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_GRPPRI_SHIFT)) & DMA_DCHPRI23_GRPPRI_MASK) #define DMA_DCHPRI23_DPA_MASK (0x40U) #define DMA_DCHPRI23_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability. This field resets to 0. + * 0b0..Channel n can suspend a lower priority channel. + * 0b1..Channel n cannot suspend any channel, regardless of channel priority. + */ #define DMA_DCHPRI23_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_DPA_SHIFT)) & DMA_DCHPRI23_DPA_MASK) #define DMA_DCHPRI23_ECP_MASK (0x80U) #define DMA_DCHPRI23_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption. This field resets to 0. + * 0b0..Channel n cannot be suspended by a higher priority channel's service request. + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. + */ #define DMA_DCHPRI23_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_ECP_SHIFT)) & DMA_DCHPRI23_ECP_MASK) +/*! @} */ /*! @name DCHPRI22 - Channel n Priority Register */ +/*! @{ */ #define DMA_DCHPRI22_CHPRI_MASK (0xFU) #define DMA_DCHPRI22_CHPRI_SHIFT (0U) #define DMA_DCHPRI22_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_CHPRI_SHIFT)) & DMA_DCHPRI22_CHPRI_MASK) @@ -8110,12 +12617,22 @@ typedef struct { #define DMA_DCHPRI22_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_GRPPRI_SHIFT)) & DMA_DCHPRI22_GRPPRI_MASK) #define DMA_DCHPRI22_DPA_MASK (0x40U) #define DMA_DCHPRI22_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability. This field resets to 0. + * 0b0..Channel n can suspend a lower priority channel. + * 0b1..Channel n cannot suspend any channel, regardless of channel priority. + */ #define DMA_DCHPRI22_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_DPA_SHIFT)) & DMA_DCHPRI22_DPA_MASK) #define DMA_DCHPRI22_ECP_MASK (0x80U) #define DMA_DCHPRI22_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption. This field resets to 0. + * 0b0..Channel n cannot be suspended by a higher priority channel's service request. + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. + */ #define DMA_DCHPRI22_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_ECP_SHIFT)) & DMA_DCHPRI22_ECP_MASK) +/*! @} */ /*! @name DCHPRI21 - Channel n Priority Register */ +/*! @{ */ #define DMA_DCHPRI21_CHPRI_MASK (0xFU) #define DMA_DCHPRI21_CHPRI_SHIFT (0U) #define DMA_DCHPRI21_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_CHPRI_SHIFT)) & DMA_DCHPRI21_CHPRI_MASK) @@ -8124,12 +12641,22 @@ typedef struct { #define DMA_DCHPRI21_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_GRPPRI_SHIFT)) & DMA_DCHPRI21_GRPPRI_MASK) #define DMA_DCHPRI21_DPA_MASK (0x40U) #define DMA_DCHPRI21_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability. This field resets to 0. + * 0b0..Channel n can suspend a lower priority channel. + * 0b1..Channel n cannot suspend any channel, regardless of channel priority. + */ #define DMA_DCHPRI21_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_DPA_SHIFT)) & DMA_DCHPRI21_DPA_MASK) #define DMA_DCHPRI21_ECP_MASK (0x80U) #define DMA_DCHPRI21_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption. This field resets to 0. + * 0b0..Channel n cannot be suspended by a higher priority channel's service request. + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. + */ #define DMA_DCHPRI21_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_ECP_SHIFT)) & DMA_DCHPRI21_ECP_MASK) +/*! @} */ /*! @name DCHPRI20 - Channel n Priority Register */ +/*! @{ */ #define DMA_DCHPRI20_CHPRI_MASK (0xFU) #define DMA_DCHPRI20_CHPRI_SHIFT (0U) #define DMA_DCHPRI20_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_CHPRI_SHIFT)) & DMA_DCHPRI20_CHPRI_MASK) @@ -8138,12 +12665,22 @@ typedef struct { #define DMA_DCHPRI20_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_GRPPRI_SHIFT)) & DMA_DCHPRI20_GRPPRI_MASK) #define DMA_DCHPRI20_DPA_MASK (0x40U) #define DMA_DCHPRI20_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability. This field resets to 0. + * 0b0..Channel n can suspend a lower priority channel. + * 0b1..Channel n cannot suspend any channel, regardless of channel priority. + */ #define DMA_DCHPRI20_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_DPA_SHIFT)) & DMA_DCHPRI20_DPA_MASK) #define DMA_DCHPRI20_ECP_MASK (0x80U) #define DMA_DCHPRI20_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption. This field resets to 0. + * 0b0..Channel n cannot be suspended by a higher priority channel's service request. + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. + */ #define DMA_DCHPRI20_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_ECP_SHIFT)) & DMA_DCHPRI20_ECP_MASK) +/*! @} */ /*! @name DCHPRI27 - Channel n Priority Register */ +/*! @{ */ #define DMA_DCHPRI27_CHPRI_MASK (0xFU) #define DMA_DCHPRI27_CHPRI_SHIFT (0U) #define DMA_DCHPRI27_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_CHPRI_SHIFT)) & DMA_DCHPRI27_CHPRI_MASK) @@ -8152,12 +12689,22 @@ typedef struct { #define DMA_DCHPRI27_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_GRPPRI_SHIFT)) & DMA_DCHPRI27_GRPPRI_MASK) #define DMA_DCHPRI27_DPA_MASK (0x40U) #define DMA_DCHPRI27_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability. This field resets to 0. + * 0b0..Channel n can suspend a lower priority channel. + * 0b1..Channel n cannot suspend any channel, regardless of channel priority. + */ #define DMA_DCHPRI27_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_DPA_SHIFT)) & DMA_DCHPRI27_DPA_MASK) #define DMA_DCHPRI27_ECP_MASK (0x80U) #define DMA_DCHPRI27_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption. This field resets to 0. + * 0b0..Channel n cannot be suspended by a higher priority channel's service request. + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. + */ #define DMA_DCHPRI27_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_ECP_SHIFT)) & DMA_DCHPRI27_ECP_MASK) +/*! @} */ /*! @name DCHPRI26 - Channel n Priority Register */ +/*! @{ */ #define DMA_DCHPRI26_CHPRI_MASK (0xFU) #define DMA_DCHPRI26_CHPRI_SHIFT (0U) #define DMA_DCHPRI26_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_CHPRI_SHIFT)) & DMA_DCHPRI26_CHPRI_MASK) @@ -8166,12 +12713,22 @@ typedef struct { #define DMA_DCHPRI26_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_GRPPRI_SHIFT)) & DMA_DCHPRI26_GRPPRI_MASK) #define DMA_DCHPRI26_DPA_MASK (0x40U) #define DMA_DCHPRI26_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability. This field resets to 0. + * 0b0..Channel n can suspend a lower priority channel. + * 0b1..Channel n cannot suspend any channel, regardless of channel priority. + */ #define DMA_DCHPRI26_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_DPA_SHIFT)) & DMA_DCHPRI26_DPA_MASK) #define DMA_DCHPRI26_ECP_MASK (0x80U) #define DMA_DCHPRI26_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption. This field resets to 0. + * 0b0..Channel n cannot be suspended by a higher priority channel's service request. + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. + */ #define DMA_DCHPRI26_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_ECP_SHIFT)) & DMA_DCHPRI26_ECP_MASK) +/*! @} */ /*! @name DCHPRI25 - Channel n Priority Register */ +/*! @{ */ #define DMA_DCHPRI25_CHPRI_MASK (0xFU) #define DMA_DCHPRI25_CHPRI_SHIFT (0U) #define DMA_DCHPRI25_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_CHPRI_SHIFT)) & DMA_DCHPRI25_CHPRI_MASK) @@ -8180,12 +12737,22 @@ typedef struct { #define DMA_DCHPRI25_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_GRPPRI_SHIFT)) & DMA_DCHPRI25_GRPPRI_MASK) #define DMA_DCHPRI25_DPA_MASK (0x40U) #define DMA_DCHPRI25_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability. This field resets to 0. + * 0b0..Channel n can suspend a lower priority channel. + * 0b1..Channel n cannot suspend any channel, regardless of channel priority. + */ #define DMA_DCHPRI25_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_DPA_SHIFT)) & DMA_DCHPRI25_DPA_MASK) #define DMA_DCHPRI25_ECP_MASK (0x80U) #define DMA_DCHPRI25_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption. This field resets to 0. + * 0b0..Channel n cannot be suspended by a higher priority channel's service request. + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. + */ #define DMA_DCHPRI25_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_ECP_SHIFT)) & DMA_DCHPRI25_ECP_MASK) +/*! @} */ /*! @name DCHPRI24 - Channel n Priority Register */ +/*! @{ */ #define DMA_DCHPRI24_CHPRI_MASK (0xFU) #define DMA_DCHPRI24_CHPRI_SHIFT (0U) #define DMA_DCHPRI24_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_CHPRI_SHIFT)) & DMA_DCHPRI24_CHPRI_MASK) @@ -8194,12 +12761,22 @@ typedef struct { #define DMA_DCHPRI24_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_GRPPRI_SHIFT)) & DMA_DCHPRI24_GRPPRI_MASK) #define DMA_DCHPRI24_DPA_MASK (0x40U) #define DMA_DCHPRI24_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability. This field resets to 0. + * 0b0..Channel n can suspend a lower priority channel. + * 0b1..Channel n cannot suspend any channel, regardless of channel priority. + */ #define DMA_DCHPRI24_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_DPA_SHIFT)) & DMA_DCHPRI24_DPA_MASK) #define DMA_DCHPRI24_ECP_MASK (0x80U) #define DMA_DCHPRI24_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption. This field resets to 0. + * 0b0..Channel n cannot be suspended by a higher priority channel's service request. + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. + */ #define DMA_DCHPRI24_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_ECP_SHIFT)) & DMA_DCHPRI24_ECP_MASK) +/*! @} */ /*! @name DCHPRI31 - Channel n Priority Register */ +/*! @{ */ #define DMA_DCHPRI31_CHPRI_MASK (0xFU) #define DMA_DCHPRI31_CHPRI_SHIFT (0U) #define DMA_DCHPRI31_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_CHPRI_SHIFT)) & DMA_DCHPRI31_CHPRI_MASK) @@ -8208,12 +12785,22 @@ typedef struct { #define DMA_DCHPRI31_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_GRPPRI_SHIFT)) & DMA_DCHPRI31_GRPPRI_MASK) #define DMA_DCHPRI31_DPA_MASK (0x40U) #define DMA_DCHPRI31_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability. This field resets to 0. + * 0b0..Channel n can suspend a lower priority channel. + * 0b1..Channel n cannot suspend any channel, regardless of channel priority. + */ #define DMA_DCHPRI31_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_DPA_SHIFT)) & DMA_DCHPRI31_DPA_MASK) #define DMA_DCHPRI31_ECP_MASK (0x80U) #define DMA_DCHPRI31_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption. This field resets to 0. + * 0b0..Channel n cannot be suspended by a higher priority channel's service request. + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. + */ #define DMA_DCHPRI31_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_ECP_SHIFT)) & DMA_DCHPRI31_ECP_MASK) +/*! @} */ /*! @name DCHPRI30 - Channel n Priority Register */ +/*! @{ */ #define DMA_DCHPRI30_CHPRI_MASK (0xFU) #define DMA_DCHPRI30_CHPRI_SHIFT (0U) #define DMA_DCHPRI30_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_CHPRI_SHIFT)) & DMA_DCHPRI30_CHPRI_MASK) @@ -8222,12 +12809,22 @@ typedef struct { #define DMA_DCHPRI30_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_GRPPRI_SHIFT)) & DMA_DCHPRI30_GRPPRI_MASK) #define DMA_DCHPRI30_DPA_MASK (0x40U) #define DMA_DCHPRI30_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability. This field resets to 0. + * 0b0..Channel n can suspend a lower priority channel. + * 0b1..Channel n cannot suspend any channel, regardless of channel priority. + */ #define DMA_DCHPRI30_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_DPA_SHIFT)) & DMA_DCHPRI30_DPA_MASK) #define DMA_DCHPRI30_ECP_MASK (0x80U) #define DMA_DCHPRI30_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption. This field resets to 0. + * 0b0..Channel n cannot be suspended by a higher priority channel's service request. + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. + */ #define DMA_DCHPRI30_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_ECP_SHIFT)) & DMA_DCHPRI30_ECP_MASK) +/*! @} */ /*! @name DCHPRI29 - Channel n Priority Register */ +/*! @{ */ #define DMA_DCHPRI29_CHPRI_MASK (0xFU) #define DMA_DCHPRI29_CHPRI_SHIFT (0U) #define DMA_DCHPRI29_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_CHPRI_SHIFT)) & DMA_DCHPRI29_CHPRI_MASK) @@ -8236,12 +12833,22 @@ typedef struct { #define DMA_DCHPRI29_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_GRPPRI_SHIFT)) & DMA_DCHPRI29_GRPPRI_MASK) #define DMA_DCHPRI29_DPA_MASK (0x40U) #define DMA_DCHPRI29_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability. This field resets to 0. + * 0b0..Channel n can suspend a lower priority channel. + * 0b1..Channel n cannot suspend any channel, regardless of channel priority. + */ #define DMA_DCHPRI29_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_DPA_SHIFT)) & DMA_DCHPRI29_DPA_MASK) #define DMA_DCHPRI29_ECP_MASK (0x80U) #define DMA_DCHPRI29_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption. This field resets to 0. + * 0b0..Channel n cannot be suspended by a higher priority channel's service request. + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. + */ #define DMA_DCHPRI29_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_ECP_SHIFT)) & DMA_DCHPRI29_ECP_MASK) +/*! @} */ /*! @name DCHPRI28 - Channel n Priority Register */ +/*! @{ */ #define DMA_DCHPRI28_CHPRI_MASK (0xFU) #define DMA_DCHPRI28_CHPRI_SHIFT (0U) #define DMA_DCHPRI28_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_CHPRI_SHIFT)) & DMA_DCHPRI28_CHPRI_MASK) @@ -8250,28 +12857,42 @@ typedef struct { #define DMA_DCHPRI28_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_GRPPRI_SHIFT)) & DMA_DCHPRI28_GRPPRI_MASK) #define DMA_DCHPRI28_DPA_MASK (0x40U) #define DMA_DCHPRI28_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability. This field resets to 0. + * 0b0..Channel n can suspend a lower priority channel. + * 0b1..Channel n cannot suspend any channel, regardless of channel priority. + */ #define DMA_DCHPRI28_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_DPA_SHIFT)) & DMA_DCHPRI28_DPA_MASK) #define DMA_DCHPRI28_ECP_MASK (0x80U) #define DMA_DCHPRI28_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption. This field resets to 0. + * 0b0..Channel n cannot be suspended by a higher priority channel's service request. + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. + */ #define DMA_DCHPRI28_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_ECP_SHIFT)) & DMA_DCHPRI28_ECP_MASK) +/*! @} */ /*! @name SADDR - TCD Source Address */ +/*! @{ */ #define DMA_SADDR_SADDR_MASK (0xFFFFFFFFU) #define DMA_SADDR_SADDR_SHIFT (0U) #define DMA_SADDR_SADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_SADDR_SADDR_SHIFT)) & DMA_SADDR_SADDR_MASK) +/*! @} */ /* The count of DMA_SADDR */ #define DMA_SADDR_COUNT (32U) /*! @name SOFF - TCD Signed Source Address Offset */ +/*! @{ */ #define DMA_SOFF_SOFF_MASK (0xFFFFU) #define DMA_SOFF_SOFF_SHIFT (0U) #define DMA_SOFF_SOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_SOFF_SOFF_SHIFT)) & DMA_SOFF_SOFF_MASK) +/*! @} */ /* The count of DMA_SOFF */ #define DMA_SOFF_COUNT (32U) /*! @name ATTR - TCD Transfer Attributes */ +/*! @{ */ #define DMA_ATTR_DSIZE_MASK (0x7U) #define DMA_ATTR_DSIZE_SHIFT (0U) #define DMA_ATTR_DSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_DSIZE_SHIFT)) & DMA_ATTR_DSIZE_MASK) @@ -8280,37 +12901,65 @@ typedef struct { #define DMA_ATTR_DMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_DMOD_SHIFT)) & DMA_ATTR_DMOD_MASK) #define DMA_ATTR_SSIZE_MASK (0x700U) #define DMA_ATTR_SSIZE_SHIFT (8U) +/*! SSIZE - Source data transfer size + * 0b000..8-bit + * 0b001..16-bit + * 0b010..32-bit + * 0b011..64-bit + * 0b100..Reserved + * 0b101..32-byte burst (4 beats of 64 bits) + * 0b110..Reserved + * 0b111..Reserved + */ #define DMA_ATTR_SSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_SSIZE_SHIFT)) & DMA_ATTR_SSIZE_MASK) #define DMA_ATTR_SMOD_MASK (0xF800U) #define DMA_ATTR_SMOD_SHIFT (11U) +/*! SMOD - Source Address Modulo + * 0b00000..Source address modulo feature is disabled + * 0b00001-0b11111..This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + */ #define DMA_ATTR_SMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_SMOD_SHIFT)) & DMA_ATTR_SMOD_MASK) +/*! @} */ /* The count of DMA_ATTR */ #define DMA_ATTR_COUNT (32U) /*! @name NBYTES_MLNO - TCD Minor Byte Count (Minor Loop Mapping Disabled) */ +/*! @{ */ #define DMA_NBYTES_MLNO_NBYTES_MASK (0xFFFFFFFFU) #define DMA_NBYTES_MLNO_NBYTES_SHIFT (0U) #define DMA_NBYTES_MLNO_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLNO_NBYTES_SHIFT)) & DMA_NBYTES_MLNO_NBYTES_MASK) +/*! @} */ /* The count of DMA_NBYTES_MLNO */ #define DMA_NBYTES_MLNO_COUNT (32U) /*! @name NBYTES_MLOFFNO - TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) */ +/*! @{ */ #define DMA_NBYTES_MLOFFNO_NBYTES_MASK (0x3FFFFFFFU) #define DMA_NBYTES_MLOFFNO_NBYTES_SHIFT (0U) #define DMA_NBYTES_MLOFFNO_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_NBYTES_SHIFT)) & DMA_NBYTES_MLOFFNO_NBYTES_MASK) #define DMA_NBYTES_MLOFFNO_DMLOE_MASK (0x40000000U) #define DMA_NBYTES_MLOFFNO_DMLOE_SHIFT (30U) +/*! DMLOE - Destination Minor Loop Offset enable + * 0b0..The minor loop offset is not applied to the DADDR + * 0b1..The minor loop offset is applied to the DADDR + */ #define DMA_NBYTES_MLOFFNO_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_DMLOE_SHIFT)) & DMA_NBYTES_MLOFFNO_DMLOE_MASK) #define DMA_NBYTES_MLOFFNO_SMLOE_MASK (0x80000000U) #define DMA_NBYTES_MLOFFNO_SMLOE_SHIFT (31U) +/*! SMLOE - Source Minor Loop Offset Enable + * 0b0..The minor loop offset is not applied to the SADDR + * 0b1..The minor loop offset is applied to the SADDR + */ #define DMA_NBYTES_MLOFFNO_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_SMLOE_SHIFT)) & DMA_NBYTES_MLOFFNO_SMLOE_MASK) +/*! @} */ /* The count of DMA_NBYTES_MLOFFNO */ #define DMA_NBYTES_MLOFFNO_COUNT (32U) /*! @name NBYTES_MLOFFYES - TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) */ +/*! @{ */ #define DMA_NBYTES_MLOFFYES_NBYTES_MASK (0x3FFU) #define DMA_NBYTES_MLOFFYES_NBYTES_SHIFT (0U) #define DMA_NBYTES_MLOFFYES_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_NBYTES_SHIFT)) & DMA_NBYTES_MLOFFYES_NBYTES_MASK) @@ -8319,50 +12968,72 @@ typedef struct { #define DMA_NBYTES_MLOFFYES_MLOFF(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_MLOFF_SHIFT)) & DMA_NBYTES_MLOFFYES_MLOFF_MASK) #define DMA_NBYTES_MLOFFYES_DMLOE_MASK (0x40000000U) #define DMA_NBYTES_MLOFFYES_DMLOE_SHIFT (30U) +/*! DMLOE - Destination Minor Loop Offset enable + * 0b0..The minor loop offset is not applied to the DADDR + * 0b1..The minor loop offset is applied to the DADDR + */ #define DMA_NBYTES_MLOFFYES_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_DMLOE_SHIFT)) & DMA_NBYTES_MLOFFYES_DMLOE_MASK) #define DMA_NBYTES_MLOFFYES_SMLOE_MASK (0x80000000U) #define DMA_NBYTES_MLOFFYES_SMLOE_SHIFT (31U) +/*! SMLOE - Source Minor Loop Offset Enable + * 0b0..The minor loop offset is not applied to the SADDR + * 0b1..The minor loop offset is applied to the SADDR + */ #define DMA_NBYTES_MLOFFYES_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_SMLOE_SHIFT)) & DMA_NBYTES_MLOFFYES_SMLOE_MASK) +/*! @} */ /* The count of DMA_NBYTES_MLOFFYES */ #define DMA_NBYTES_MLOFFYES_COUNT (32U) /*! @name SLAST - TCD Last Source Address Adjustment */ +/*! @{ */ #define DMA_SLAST_SLAST_MASK (0xFFFFFFFFU) #define DMA_SLAST_SLAST_SHIFT (0U) #define DMA_SLAST_SLAST(x) (((uint32_t)(((uint32_t)(x)) << DMA_SLAST_SLAST_SHIFT)) & DMA_SLAST_SLAST_MASK) +/*! @} */ /* The count of DMA_SLAST */ #define DMA_SLAST_COUNT (32U) /*! @name DADDR - TCD Destination Address */ +/*! @{ */ #define DMA_DADDR_DADDR_MASK (0xFFFFFFFFU) #define DMA_DADDR_DADDR_SHIFT (0U) #define DMA_DADDR_DADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_DADDR_DADDR_SHIFT)) & DMA_DADDR_DADDR_MASK) +/*! @} */ /* The count of DMA_DADDR */ #define DMA_DADDR_COUNT (32U) /*! @name DOFF - TCD Signed Destination Address Offset */ +/*! @{ */ #define DMA_DOFF_DOFF_MASK (0xFFFFU) #define DMA_DOFF_DOFF_SHIFT (0U) #define DMA_DOFF_DOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_DOFF_DOFF_SHIFT)) & DMA_DOFF_DOFF_MASK) +/*! @} */ /* The count of DMA_DOFF */ #define DMA_DOFF_COUNT (32U) /*! @name CITER_ELINKNO - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) */ +/*! @{ */ #define DMA_CITER_ELINKNO_CITER_MASK (0x7FFFU) #define DMA_CITER_ELINKNO_CITER_SHIFT (0U) #define DMA_CITER_ELINKNO_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKNO_CITER_SHIFT)) & DMA_CITER_ELINKNO_CITER_MASK) #define DMA_CITER_ELINKNO_ELINK_MASK (0x8000U) #define DMA_CITER_ELINKNO_ELINK_SHIFT (15U) +/*! ELINK - Enable channel-to-channel linking on minor-loop complete + * 0b0..The channel-to-channel linking is disabled + * 0b1..The channel-to-channel linking is enabled + */ #define DMA_CITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKNO_ELINK_SHIFT)) & DMA_CITER_ELINKNO_ELINK_MASK) +/*! @} */ /* The count of DMA_CITER_ELINKNO */ #define DMA_CITER_ELINKNO_COUNT (32U) /*! @name CITER_ELINKYES - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) */ +/*! @{ */ #define DMA_CITER_ELINKYES_CITER_MASK (0x1FFU) #define DMA_CITER_ELINKYES_CITER_SHIFT (0U) #define DMA_CITER_ELINKYES_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_CITER_SHIFT)) & DMA_CITER_ELINKYES_CITER_MASK) @@ -8371,37 +13042,69 @@ typedef struct { #define DMA_CITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_LINKCH_SHIFT)) & DMA_CITER_ELINKYES_LINKCH_MASK) #define DMA_CITER_ELINKYES_ELINK_MASK (0x8000U) #define DMA_CITER_ELINKYES_ELINK_SHIFT (15U) +/*! ELINK - Enable channel-to-channel linking on minor-loop complete + * 0b0..The channel-to-channel linking is disabled + * 0b1..The channel-to-channel linking is enabled + */ #define DMA_CITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_ELINK_SHIFT)) & DMA_CITER_ELINKYES_ELINK_MASK) +/*! @} */ /* The count of DMA_CITER_ELINKYES */ #define DMA_CITER_ELINKYES_COUNT (32U) /*! @name DLAST_SGA - TCD Last Destination Address Adjustment/Scatter Gather Address */ +/*! @{ */ #define DMA_DLAST_SGA_DLASTSGA_MASK (0xFFFFFFFFU) #define DMA_DLAST_SGA_DLASTSGA_SHIFT (0U) #define DMA_DLAST_SGA_DLASTSGA(x) (((uint32_t)(((uint32_t)(x)) << DMA_DLAST_SGA_DLASTSGA_SHIFT)) & DMA_DLAST_SGA_DLASTSGA_MASK) +/*! @} */ /* The count of DMA_DLAST_SGA */ #define DMA_DLAST_SGA_COUNT (32U) /*! @name CSR - TCD Control and Status */ +/*! @{ */ #define DMA_CSR_START_MASK (0x1U) #define DMA_CSR_START_SHIFT (0U) +/*! START - Channel Start + * 0b0..The channel is not explicitly started. + * 0b1..The channel is explicitly started via a software initiated service request. + */ #define DMA_CSR_START(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_START_SHIFT)) & DMA_CSR_START_MASK) #define DMA_CSR_INTMAJOR_MASK (0x2U) #define DMA_CSR_INTMAJOR_SHIFT (1U) +/*! INTMAJOR - Enable an interrupt when major iteration count completes. + * 0b0..The end-of-major loop interrupt is disabled. + * 0b1..The end-of-major loop interrupt is enabled. + */ #define DMA_CSR_INTMAJOR(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_INTMAJOR_SHIFT)) & DMA_CSR_INTMAJOR_MASK) #define DMA_CSR_INTHALF_MASK (0x4U) #define DMA_CSR_INTHALF_SHIFT (2U) +/*! INTHALF - Enable an interrupt when major counter is half complete. + * 0b0..The half-point interrupt is disabled. + * 0b1..The half-point interrupt is enabled. + */ #define DMA_CSR_INTHALF(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_INTHALF_SHIFT)) & DMA_CSR_INTHALF_MASK) #define DMA_CSR_DREQ_MASK (0x8U) #define DMA_CSR_DREQ_SHIFT (3U) +/*! DREQ - Disable Request + * 0b0..The channel's ERQ bit is not affected. + * 0b1..The channel's ERQ bit is cleared when the major loop is complete. + */ #define DMA_CSR_DREQ(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_DREQ_SHIFT)) & DMA_CSR_DREQ_MASK) #define DMA_CSR_ESG_MASK (0x10U) #define DMA_CSR_ESG_SHIFT (4U) +/*! ESG - Enable Scatter/Gather Processing + * 0b0..The current channel's TCD is normal format. + * 0b1..The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. + */ #define DMA_CSR_ESG(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_ESG_SHIFT)) & DMA_CSR_ESG_MASK) #define DMA_CSR_MAJORELINK_MASK (0x20U) #define DMA_CSR_MAJORELINK_SHIFT (5U) +/*! MAJORELINK - Enable channel-to-channel linking on major loop complete + * 0b0..The channel-to-channel linking is disabled. + * 0b1..The channel-to-channel linking is enabled. + */ #define DMA_CSR_MAJORELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_MAJORELINK_SHIFT)) & DMA_CSR_MAJORELINK_MASK) #define DMA_CSR_ACTIVE_MASK (0x40U) #define DMA_CSR_ACTIVE_SHIFT (6U) @@ -8414,23 +13117,37 @@ typedef struct { #define DMA_CSR_MAJORLINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_MAJORLINKCH_SHIFT)) & DMA_CSR_MAJORLINKCH_MASK) #define DMA_CSR_BWC_MASK (0xC000U) #define DMA_CSR_BWC_SHIFT (14U) +/*! BWC - Bandwidth Control + * 0b00..No eDMA engine stalls. + * 0b01..Reserved + * 0b10..eDMA engine stalls for 4 cycles after each R/W. + * 0b11..eDMA engine stalls for 8 cycles after each R/W. + */ #define DMA_CSR_BWC(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_BWC_SHIFT)) & DMA_CSR_BWC_MASK) +/*! @} */ /* The count of DMA_CSR */ #define DMA_CSR_COUNT (32U) /*! @name BITER_ELINKNO - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) */ +/*! @{ */ #define DMA_BITER_ELINKNO_BITER_MASK (0x7FFFU) #define DMA_BITER_ELINKNO_BITER_SHIFT (0U) #define DMA_BITER_ELINKNO_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKNO_BITER_SHIFT)) & DMA_BITER_ELINKNO_BITER_MASK) #define DMA_BITER_ELINKNO_ELINK_MASK (0x8000U) #define DMA_BITER_ELINKNO_ELINK_SHIFT (15U) +/*! ELINK - Enables channel-to-channel linking on minor loop complete + * 0b0..The channel-to-channel linking is disabled + * 0b1..The channel-to-channel linking is enabled + */ #define DMA_BITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKNO_ELINK_SHIFT)) & DMA_BITER_ELINKNO_ELINK_MASK) +/*! @} */ /* The count of DMA_BITER_ELINKNO */ #define DMA_BITER_ELINKNO_COUNT (32U) /*! @name BITER_ELINKYES - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) */ +/*! @{ */ #define DMA_BITER_ELINKYES_BITER_MASK (0x1FFU) #define DMA_BITER_ELINKYES_BITER_SHIFT (0U) #define DMA_BITER_ELINKYES_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_BITER_SHIFT)) & DMA_BITER_ELINKYES_BITER_MASK) @@ -8439,7 +13156,12 @@ typedef struct { #define DMA_BITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_LINKCH_SHIFT)) & DMA_BITER_ELINKYES_LINKCH_MASK) #define DMA_BITER_ELINKYES_ELINK_MASK (0x8000U) #define DMA_BITER_ELINKYES_ELINK_SHIFT (15U) +/*! ELINK - Enables channel-to-channel linking on minor loop complete + * 0b0..The channel-to-channel linking is disabled + * 0b1..The channel-to-channel linking is enabled + */ #define DMA_BITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_ELINK_SHIFT)) & DMA_BITER_ELINKYES_ELINK_MASK) +/*! @} */ /* The count of DMA_BITER_ELINKYES */ #define DMA_BITER_ELINKYES_COUNT (32U) @@ -8479,11 +13201,7 @@ typedef struct { /** DMAMUX - Register Layout Typedef */ typedef struct { - __IO uint32_t CHCFG[32]; /**< - Channel 0 Configuration Register - .. - Channel 31 Configuration Register - , array offset: 0x0, array step: 0x4 */ + __IO uint32_t CHCFG[32]; /**< Channel 0 Configuration Register..Channel 31 Configuration Register, array offset: 0x0, array step: 0x4 */ } DMAMUX_Type; /* ---------------------------------------------------------------------------- @@ -8495,23 +13213,33 @@ typedef struct { * @{ */ -/*! @name CHCFG - - Channel 0 Configuration Register - .. - Channel 31 Configuration Register - */ +/*! @name CHCFG - Channel 0 Configuration Register..Channel 31 Configuration Register */ +/*! @{ */ #define DMAMUX_CHCFG_SOURCE_MASK (0x7FU) #define DMAMUX_CHCFG_SOURCE_SHIFT (0U) #define DMAMUX_CHCFG_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << DMAMUX_CHCFG_SOURCE_SHIFT)) & DMAMUX_CHCFG_SOURCE_MASK) #define DMAMUX_CHCFG_A_ON_MASK (0x20000000U) #define DMAMUX_CHCFG_A_ON_SHIFT (29U) +/*! A_ON - DMA Channel Always Enable + * 0b0..DMA Channel Always ON function is disabled + * 0b1..DMA Channel Always ON function is enabled + */ #define DMAMUX_CHCFG_A_ON(x) (((uint32_t)(((uint32_t)(x)) << DMAMUX_CHCFG_A_ON_SHIFT)) & DMAMUX_CHCFG_A_ON_MASK) #define DMAMUX_CHCFG_TRIG_MASK (0x40000000U) #define DMAMUX_CHCFG_TRIG_SHIFT (30U) +/*! TRIG - DMA Channel Trigger Enable + * 0b0..Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode) + * 0b1..Triggering is enabled. If triggering is enabled and ENBL is set, the DMA_CH_MUX is in Periodic Trigger mode. + */ #define DMAMUX_CHCFG_TRIG(x) (((uint32_t)(((uint32_t)(x)) << DMAMUX_CHCFG_TRIG_SHIFT)) & DMAMUX_CHCFG_TRIG_MASK) #define DMAMUX_CHCFG_ENBL_MASK (0x80000000U) #define DMAMUX_CHCFG_ENBL_SHIFT (31U) +/*! ENBL - DMA Mux Channel Enable + * 0b0..DMA Mux channel is disabled + * 0b1..DMA Mux channel is enabled + */ #define DMAMUX_CHCFG_ENBL(x) (((uint32_t)(((uint32_t)(x)) << DMAMUX_CHCFG_ENBL_SHIFT)) & DMAMUX_CHCFG_ENBL_MASK) +/*! @} */ /* The count of DMAMUX_CHCFG */ #define DMAMUX_CHCFG_COUNT (32U) @@ -8580,119 +13308,210 @@ typedef struct { */ /*! @name CTRL - Control Register */ +/*! @{ */ #define ENC_CTRL_CMPIE_MASK (0x1U) #define ENC_CTRL_CMPIE_SHIFT (0U) +/*! CMPIE - Compare Interrupt Enable + * 0b0..Compare interrupt is disabled + * 0b1..Compare interrupt is enabled + */ #define ENC_CTRL_CMPIE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_CMPIE_SHIFT)) & ENC_CTRL_CMPIE_MASK) #define ENC_CTRL_CMPIRQ_MASK (0x2U) #define ENC_CTRL_CMPIRQ_SHIFT (1U) +/*! CMPIRQ - Compare Interrupt Request + * 0b0..No match has occurred + * 0b1..COMP match has occurred + */ #define ENC_CTRL_CMPIRQ(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_CMPIRQ_SHIFT)) & ENC_CTRL_CMPIRQ_MASK) #define ENC_CTRL_WDE_MASK (0x4U) #define ENC_CTRL_WDE_SHIFT (2U) +/*! WDE - Watchdog Enable + * 0b0..Watchdog timer is disabled + * 0b1..Watchdog timer is enabled + */ #define ENC_CTRL_WDE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_WDE_SHIFT)) & ENC_CTRL_WDE_MASK) #define ENC_CTRL_DIE_MASK (0x8U) #define ENC_CTRL_DIE_SHIFT (3U) +/*! DIE - Watchdog Timeout Interrupt Enable + * 0b0..Watchdog timer interrupt is disabled + * 0b1..Watchdog timer interrupt is enabled + */ #define ENC_CTRL_DIE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_DIE_SHIFT)) & ENC_CTRL_DIE_MASK) #define ENC_CTRL_DIRQ_MASK (0x10U) #define ENC_CTRL_DIRQ_SHIFT (4U) +/*! DIRQ - Watchdog Timeout Interrupt Request + * 0b0..No interrupt has occurred + * 0b1..Watchdog timeout interrupt has occurred + */ #define ENC_CTRL_DIRQ(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_DIRQ_SHIFT)) & ENC_CTRL_DIRQ_MASK) #define ENC_CTRL_XNE_MASK (0x20U) #define ENC_CTRL_XNE_SHIFT (5U) +/*! XNE - Use Negative Edge of INDEX Pulse + * 0b0..Use positive transition edge of INDEX pulse + * 0b1..Use negative transition edge of INDEX pulse + */ #define ENC_CTRL_XNE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_XNE_SHIFT)) & ENC_CTRL_XNE_MASK) #define ENC_CTRL_XIP_MASK (0x40U) #define ENC_CTRL_XIP_SHIFT (6U) +/*! XIP - INDEX Triggered Initialization of Position Counters UPOS and LPOS + * 0b0..No action + * 0b1..INDEX pulse initializes the position counter + */ #define ENC_CTRL_XIP(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_XIP_SHIFT)) & ENC_CTRL_XIP_MASK) #define ENC_CTRL_XIE_MASK (0x80U) #define ENC_CTRL_XIE_SHIFT (7U) +/*! XIE - INDEX Pulse Interrupt Enable + * 0b0..INDEX pulse interrupt is disabled + * 0b1..INDEX pulse interrupt is enabled + */ #define ENC_CTRL_XIE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_XIE_SHIFT)) & ENC_CTRL_XIE_MASK) #define ENC_CTRL_XIRQ_MASK (0x100U) #define ENC_CTRL_XIRQ_SHIFT (8U) +/*! XIRQ - INDEX Pulse Interrupt Request + * 0b0..No interrupt has occurred + * 0b1..INDEX pulse interrupt has occurred + */ #define ENC_CTRL_XIRQ(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_XIRQ_SHIFT)) & ENC_CTRL_XIRQ_MASK) #define ENC_CTRL_PH1_MASK (0x200U) #define ENC_CTRL_PH1_SHIFT (9U) +/*! PH1 - Enable Signal Phase Count Mode + * 0b0..Use standard quadrature decoder where PHASEA and PHASEB represent a two phase quadrature signal. + * 0b1..Bypass the quadrature decoder. A positive transition of the PHASEA input generates a count signal. The PHASEB input and the REV bit control the counter direction. If CTRL[REV] = 0, PHASEB = 0, then count up If CTRL[REV] = 0, PHASEB = 1, then count down If CTRL[REV] = 1, PHASEB = 0, then count down If CTRL[REV] = 1, PHASEB = 1, then count up + */ #define ENC_CTRL_PH1(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_PH1_SHIFT)) & ENC_CTRL_PH1_MASK) #define ENC_CTRL_REV_MASK (0x400U) #define ENC_CTRL_REV_SHIFT (10U) +/*! REV - Enable Reverse Direction Counting + * 0b0..Count normally + * 0b1..Count in the reverse direction + */ #define ENC_CTRL_REV(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_REV_SHIFT)) & ENC_CTRL_REV_MASK) #define ENC_CTRL_SWIP_MASK (0x800U) #define ENC_CTRL_SWIP_SHIFT (11U) +/*! SWIP - Software Triggered Initialization of Position Counters UPOS and LPOS + * 0b0..No action + * 0b1..Initialize position counter + */ #define ENC_CTRL_SWIP(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_SWIP_SHIFT)) & ENC_CTRL_SWIP_MASK) #define ENC_CTRL_HNE_MASK (0x1000U) #define ENC_CTRL_HNE_SHIFT (12U) +/*! HNE - Use Negative Edge of HOME Input + * 0b0..Use positive going edge-to-trigger initialization of position counters UPOS and LPOS + * 0b1..Use negative going edge-to-trigger initialization of position counters UPOS and LPOS + */ #define ENC_CTRL_HNE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_HNE_SHIFT)) & ENC_CTRL_HNE_MASK) #define ENC_CTRL_HIP_MASK (0x2000U) #define ENC_CTRL_HIP_SHIFT (13U) +/*! HIP - Enable HOME to Initialize Position Counters UPOS and LPOS + * 0b0..No action + * 0b1..HOME signal initializes the position counter + */ #define ENC_CTRL_HIP(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_HIP_SHIFT)) & ENC_CTRL_HIP_MASK) #define ENC_CTRL_HIE_MASK (0x4000U) #define ENC_CTRL_HIE_SHIFT (14U) +/*! HIE - HOME Interrupt Enable + * 0b0..Disable HOME interrupts + * 0b1..Enable HOME interrupts + */ #define ENC_CTRL_HIE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_HIE_SHIFT)) & ENC_CTRL_HIE_MASK) #define ENC_CTRL_HIRQ_MASK (0x8000U) #define ENC_CTRL_HIRQ_SHIFT (15U) +/*! HIRQ - HOME Signal Transition Interrupt Request + * 0b0..No interrupt + * 0b1..HOME signal transition interrupt request + */ #define ENC_CTRL_HIRQ(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_HIRQ_SHIFT)) & ENC_CTRL_HIRQ_MASK) +/*! @} */ /*! @name FILT - Input Filter Register */ +/*! @{ */ #define ENC_FILT_FILT_PER_MASK (0xFFU) #define ENC_FILT_FILT_PER_SHIFT (0U) #define ENC_FILT_FILT_PER(x) (((uint16_t)(((uint16_t)(x)) << ENC_FILT_FILT_PER_SHIFT)) & ENC_FILT_FILT_PER_MASK) #define ENC_FILT_FILT_CNT_MASK (0x700U) #define ENC_FILT_FILT_CNT_SHIFT (8U) #define ENC_FILT_FILT_CNT(x) (((uint16_t)(((uint16_t)(x)) << ENC_FILT_FILT_CNT_SHIFT)) & ENC_FILT_FILT_CNT_MASK) +/*! @} */ /*! @name WTR - Watchdog Timeout Register */ +/*! @{ */ #define ENC_WTR_WDOG_MASK (0xFFFFU) #define ENC_WTR_WDOG_SHIFT (0U) #define ENC_WTR_WDOG(x) (((uint16_t)(((uint16_t)(x)) << ENC_WTR_WDOG_SHIFT)) & ENC_WTR_WDOG_MASK) +/*! @} */ /*! @name POSD - Position Difference Counter Register */ +/*! @{ */ #define ENC_POSD_POSD_MASK (0xFFFFU) #define ENC_POSD_POSD_SHIFT (0U) #define ENC_POSD_POSD(x) (((uint16_t)(((uint16_t)(x)) << ENC_POSD_POSD_SHIFT)) & ENC_POSD_POSD_MASK) +/*! @} */ /*! @name POSDH - Position Difference Hold Register */ +/*! @{ */ #define ENC_POSDH_POSDH_MASK (0xFFFFU) #define ENC_POSDH_POSDH_SHIFT (0U) #define ENC_POSDH_POSDH(x) (((uint16_t)(((uint16_t)(x)) << ENC_POSDH_POSDH_SHIFT)) & ENC_POSDH_POSDH_MASK) +/*! @} */ /*! @name REV - Revolution Counter Register */ +/*! @{ */ #define ENC_REV_REV_MASK (0xFFFFU) #define ENC_REV_REV_SHIFT (0U) #define ENC_REV_REV(x) (((uint16_t)(((uint16_t)(x)) << ENC_REV_REV_SHIFT)) & ENC_REV_REV_MASK) +/*! @} */ /*! @name REVH - Revolution Hold Register */ +/*! @{ */ #define ENC_REVH_REVH_MASK (0xFFFFU) #define ENC_REVH_REVH_SHIFT (0U) #define ENC_REVH_REVH(x) (((uint16_t)(((uint16_t)(x)) << ENC_REVH_REVH_SHIFT)) & ENC_REVH_REVH_MASK) +/*! @} */ /*! @name UPOS - Upper Position Counter Register */ +/*! @{ */ #define ENC_UPOS_POS_MASK (0xFFFFU) #define ENC_UPOS_POS_SHIFT (0U) #define ENC_UPOS_POS(x) (((uint16_t)(((uint16_t)(x)) << ENC_UPOS_POS_SHIFT)) & ENC_UPOS_POS_MASK) +/*! @} */ /*! @name LPOS - Lower Position Counter Register */ +/*! @{ */ #define ENC_LPOS_POS_MASK (0xFFFFU) #define ENC_LPOS_POS_SHIFT (0U) #define ENC_LPOS_POS(x) (((uint16_t)(((uint16_t)(x)) << ENC_LPOS_POS_SHIFT)) & ENC_LPOS_POS_MASK) +/*! @} */ /*! @name UPOSH - Upper Position Hold Register */ +/*! @{ */ #define ENC_UPOSH_POSH_MASK (0xFFFFU) #define ENC_UPOSH_POSH_SHIFT (0U) #define ENC_UPOSH_POSH(x) (((uint16_t)(((uint16_t)(x)) << ENC_UPOSH_POSH_SHIFT)) & ENC_UPOSH_POSH_MASK) +/*! @} */ /*! @name LPOSH - Lower Position Hold Register */ +/*! @{ */ #define ENC_LPOSH_POSH_MASK (0xFFFFU) #define ENC_LPOSH_POSH_SHIFT (0U) #define ENC_LPOSH_POSH(x) (((uint16_t)(((uint16_t)(x)) << ENC_LPOSH_POSH_SHIFT)) & ENC_LPOSH_POSH_MASK) +/*! @} */ /*! @name UINIT - Upper Initialization Register */ +/*! @{ */ #define ENC_UINIT_INIT_MASK (0xFFFFU) #define ENC_UINIT_INIT_SHIFT (0U) #define ENC_UINIT_INIT(x) (((uint16_t)(((uint16_t)(x)) << ENC_UINIT_INIT_SHIFT)) & ENC_UINIT_INIT_MASK) +/*! @} */ /*! @name LINIT - Lower Initialization Register */ +/*! @{ */ #define ENC_LINIT_INIT_MASK (0xFFFFU) #define ENC_LINIT_INIT_SHIFT (0U) #define ENC_LINIT_INIT(x) (((uint16_t)(((uint16_t)(x)) << ENC_LINIT_INIT_SHIFT)) & ENC_LINIT_INIT_MASK) +/*! @} */ /*! @name IMR - Input Monitor Register */ +/*! @{ */ #define ENC_IMR_HOME_MASK (0x1U) #define ENC_IMR_HOME_SHIFT (0U) #define ENC_IMR_HOME(x) (((uint16_t)(((uint16_t)(x)) << ENC_IMR_HOME_SHIFT)) & ENC_IMR_HOME_MASK) @@ -8717,8 +13536,10 @@ typedef struct { #define ENC_IMR_FPHA_MASK (0x80U) #define ENC_IMR_FPHA_SHIFT (7U) #define ENC_IMR_FPHA(x) (((uint16_t)(((uint16_t)(x)) << ENC_IMR_FPHA_SHIFT)) & ENC_IMR_FPHA_MASK) +/*! @} */ /*! @name TST - Test Register */ +/*! @{ */ #define ENC_TST_TEST_COUNT_MASK (0xFFU) #define ENC_TST_TEST_COUNT_SHIFT (0U) #define ENC_TST_TEST_COUNT(x) (((uint16_t)(((uint16_t)(x)) << ENC_TST_TEST_COUNT_SHIFT)) & ENC_TST_TEST_COUNT_MASK) @@ -8727,71 +13548,142 @@ typedef struct { #define ENC_TST_TEST_PERIOD(x) (((uint16_t)(((uint16_t)(x)) << ENC_TST_TEST_PERIOD_SHIFT)) & ENC_TST_TEST_PERIOD_MASK) #define ENC_TST_QDN_MASK (0x2000U) #define ENC_TST_QDN_SHIFT (13U) +/*! QDN - Quadrature Decoder Negative Signal + * 0b0..Leaves quadrature decoder signal in a positive direction + * 0b1..Generates a negative quadrature decoder signal + */ #define ENC_TST_QDN(x) (((uint16_t)(((uint16_t)(x)) << ENC_TST_QDN_SHIFT)) & ENC_TST_QDN_MASK) #define ENC_TST_TCE_MASK (0x4000U) #define ENC_TST_TCE_SHIFT (14U) +/*! TCE - Test Counter Enable + * 0b0..Test count is not enabled + * 0b1..Test count is enabled + */ #define ENC_TST_TCE(x) (((uint16_t)(((uint16_t)(x)) << ENC_TST_TCE_SHIFT)) & ENC_TST_TCE_MASK) #define ENC_TST_TEN_MASK (0x8000U) #define ENC_TST_TEN_SHIFT (15U) +/*! TEN - Test Mode Enable + * 0b0..Test module is not enabled + * 0b1..Test module is enabled + */ #define ENC_TST_TEN(x) (((uint16_t)(((uint16_t)(x)) << ENC_TST_TEN_SHIFT)) & ENC_TST_TEN_MASK) +/*! @} */ /*! @name CTRL2 - Control 2 Register */ +/*! @{ */ #define ENC_CTRL2_UPDHLD_MASK (0x1U) #define ENC_CTRL2_UPDHLD_SHIFT (0U) +/*! UPDHLD - Update Hold Registers + * 0b0..Disable updates of hold registers on rising edge of TRIGGER + * 0b1..Enable updates of hold registers on rising edge of TRIGGER + */ #define ENC_CTRL2_UPDHLD(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_UPDHLD_SHIFT)) & ENC_CTRL2_UPDHLD_MASK) #define ENC_CTRL2_UPDPOS_MASK (0x2U) #define ENC_CTRL2_UPDPOS_SHIFT (1U) +/*! UPDPOS - Update Position Registers + * 0b0..No action for POSD, REV, UPOS and LPOS on rising edge of TRIGGER + * 0b1..Clear POSD, REV, UPOS and LPOS on rising edge of TRIGGER + */ #define ENC_CTRL2_UPDPOS(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_UPDPOS_SHIFT)) & ENC_CTRL2_UPDPOS_MASK) #define ENC_CTRL2_MOD_MASK (0x4U) #define ENC_CTRL2_MOD_SHIFT (2U) +/*! MOD - Enable Modulo Counting + * 0b0..Disable modulo counting + * 0b1..Enable modulo counting + */ #define ENC_CTRL2_MOD(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_MOD_SHIFT)) & ENC_CTRL2_MOD_MASK) #define ENC_CTRL2_DIR_MASK (0x8U) #define ENC_CTRL2_DIR_SHIFT (3U) +/*! DIR - Count Direction Flag + * 0b0..Last count was in the down direction + * 0b1..Last count was in the up direction + */ #define ENC_CTRL2_DIR(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_DIR_SHIFT)) & ENC_CTRL2_DIR_MASK) #define ENC_CTRL2_RUIE_MASK (0x10U) #define ENC_CTRL2_RUIE_SHIFT (4U) +/*! RUIE - Roll-under Interrupt Enable + * 0b0..Roll-under interrupt is disabled + * 0b1..Roll-under interrupt is enabled + */ #define ENC_CTRL2_RUIE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_RUIE_SHIFT)) & ENC_CTRL2_RUIE_MASK) #define ENC_CTRL2_RUIRQ_MASK (0x20U) #define ENC_CTRL2_RUIRQ_SHIFT (5U) +/*! RUIRQ - Roll-under Interrupt Request + * 0b0..No roll-under has occurred + * 0b1..Roll-under has occurred + */ #define ENC_CTRL2_RUIRQ(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_RUIRQ_SHIFT)) & ENC_CTRL2_RUIRQ_MASK) #define ENC_CTRL2_ROIE_MASK (0x40U) #define ENC_CTRL2_ROIE_SHIFT (6U) +/*! ROIE - Roll-over Interrupt Enable + * 0b0..Roll-over interrupt is disabled + * 0b1..Roll-over interrupt is enabled + */ #define ENC_CTRL2_ROIE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_ROIE_SHIFT)) & ENC_CTRL2_ROIE_MASK) #define ENC_CTRL2_ROIRQ_MASK (0x80U) #define ENC_CTRL2_ROIRQ_SHIFT (7U) +/*! ROIRQ - Roll-over Interrupt Request + * 0b0..No roll-over has occurred + * 0b1..Roll-over has occurred + */ #define ENC_CTRL2_ROIRQ(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_ROIRQ_SHIFT)) & ENC_CTRL2_ROIRQ_MASK) #define ENC_CTRL2_REVMOD_MASK (0x100U) #define ENC_CTRL2_REVMOD_SHIFT (8U) +/*! REVMOD - Revolution Counter Modulus Enable + * 0b0..Use INDEX pulse to increment/decrement revolution counter (REV). + * 0b1..Use modulus counting roll-over/under to increment/decrement revolution counter (REV). + */ #define ENC_CTRL2_REVMOD(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_REVMOD_SHIFT)) & ENC_CTRL2_REVMOD_MASK) #define ENC_CTRL2_OUTCTL_MASK (0x200U) #define ENC_CTRL2_OUTCTL_SHIFT (9U) +/*! OUTCTL - Output Control + * 0b0..POSMATCH pulses when a match occurs between the position counters (POS) and the compare value (COMP). + * 0b1..POSMATCH pulses when the UPOS, LPOS, REV, or POSD registers are read. + */ #define ENC_CTRL2_OUTCTL(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_OUTCTL_SHIFT)) & ENC_CTRL2_OUTCTL_MASK) #define ENC_CTRL2_SABIE_MASK (0x400U) #define ENC_CTRL2_SABIE_SHIFT (10U) +/*! SABIE - Simultaneous PHASEA and PHASEB Change Interrupt Enable + * 0b0..Simultaneous PHASEA and PHASEB change interrupt disabled. + * 0b1..Simultaneous PHASEA and PHASEB change interrupt enabled. + */ #define ENC_CTRL2_SABIE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_SABIE_SHIFT)) & ENC_CTRL2_SABIE_MASK) #define ENC_CTRL2_SABIRQ_MASK (0x800U) #define ENC_CTRL2_SABIRQ_SHIFT (11U) +/*! SABIRQ - Simultaneous PHASEA and PHASEB Change Interrupt Request + * 0b0..No simultaneous change of PHASEA and PHASEB has occurred. + * 0b1..A simultaneous change of PHASEA and PHASEB has occurred. + */ #define ENC_CTRL2_SABIRQ(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_SABIRQ_SHIFT)) & ENC_CTRL2_SABIRQ_MASK) +/*! @} */ /*! @name UMOD - Upper Modulus Register */ +/*! @{ */ #define ENC_UMOD_MOD_MASK (0xFFFFU) #define ENC_UMOD_MOD_SHIFT (0U) #define ENC_UMOD_MOD(x) (((uint16_t)(((uint16_t)(x)) << ENC_UMOD_MOD_SHIFT)) & ENC_UMOD_MOD_MASK) +/*! @} */ /*! @name LMOD - Lower Modulus Register */ +/*! @{ */ #define ENC_LMOD_MOD_MASK (0xFFFFU) #define ENC_LMOD_MOD_SHIFT (0U) #define ENC_LMOD_MOD(x) (((uint16_t)(((uint16_t)(x)) << ENC_LMOD_MOD_SHIFT)) & ENC_LMOD_MOD_MASK) +/*! @} */ /*! @name UCOMP - Upper Position Compare Register */ +/*! @{ */ #define ENC_UCOMP_COMP_MASK (0xFFFFU) #define ENC_UCOMP_COMP_SHIFT (0U) #define ENC_UCOMP_COMP(x) (((uint16_t)(((uint16_t)(x)) << ENC_UCOMP_COMP_SHIFT)) & ENC_UCOMP_COMP_MASK) +/*! @} */ /*! @name LCOMP - Lower Position Compare Register */ +/*! @{ */ #define ENC_LCOMP_COMP_MASK (0xFFFFU) #define ENC_LCOMP_COMP_SHIFT (0U) #define ENC_LCOMP_COMP(x) (((uint16_t)(((uint16_t)(x)) << ENC_LCOMP_COMP_SHIFT)) & ENC_LCOMP_COMP_MASK) +/*! @} */ /*! @@ -8973,6 +13865,7 @@ typedef struct { */ /*! @name EIR - Interrupt Event Register */ +/*! @{ */ #define ENET_EIR_TS_TIMER_MASK (0x8000U) #define ENET_EIR_TS_TIMER_SHIFT (15U) #define ENET_EIR_TS_TIMER(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TS_TIMER_SHIFT)) & ENET_EIR_TS_TIMER_MASK) @@ -9021,8 +13914,10 @@ typedef struct { #define ENET_EIR_BABR_MASK (0x40000000U) #define ENET_EIR_BABR_SHIFT (30U) #define ENET_EIR_BABR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_BABR_SHIFT)) & ENET_EIR_BABR_MASK) +/*! @} */ /*! @name EIMR - Interrupt Mask Register */ +/*! @{ */ #define ENET_EIMR_TS_TIMER_MASK (0x8000U) #define ENET_EIMR_TS_TIMER_SHIFT (15U) #define ENET_EIMR_TS_TIMER(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TS_TIMER_SHIFT)) & ENET_EIMR_TS_TIMER_MASK) @@ -9058,54 +13953,106 @@ typedef struct { #define ENET_EIMR_RXF(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXF_SHIFT)) & ENET_EIMR_RXF_MASK) #define ENET_EIMR_TXB_MASK (0x4000000U) #define ENET_EIMR_TXB_SHIFT (26U) +/*! TXB - TXB Interrupt Mask + * 0b0..The corresponding interrupt source is masked. + * 0b1..The corresponding interrupt source is not masked. + */ #define ENET_EIMR_TXB(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXB_SHIFT)) & ENET_EIMR_TXB_MASK) #define ENET_EIMR_TXF_MASK (0x8000000U) #define ENET_EIMR_TXF_SHIFT (27U) +/*! TXF - TXF Interrupt Mask + * 0b0..The corresponding interrupt source is masked. + * 0b1..The corresponding interrupt source is not masked. + */ #define ENET_EIMR_TXF(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXF_SHIFT)) & ENET_EIMR_TXF_MASK) #define ENET_EIMR_GRA_MASK (0x10000000U) #define ENET_EIMR_GRA_SHIFT (28U) +/*! GRA - GRA Interrupt Mask + * 0b0..The corresponding interrupt source is masked. + * 0b1..The corresponding interrupt source is not masked. + */ #define ENET_EIMR_GRA(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_GRA_SHIFT)) & ENET_EIMR_GRA_MASK) #define ENET_EIMR_BABT_MASK (0x20000000U) #define ENET_EIMR_BABT_SHIFT (29U) +/*! BABT - BABT Interrupt Mask + * 0b0..The corresponding interrupt source is masked. + * 0b1..The corresponding interrupt source is not masked. + */ #define ENET_EIMR_BABT(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_BABT_SHIFT)) & ENET_EIMR_BABT_MASK) #define ENET_EIMR_BABR_MASK (0x40000000U) #define ENET_EIMR_BABR_SHIFT (30U) +/*! BABR - BABR Interrupt Mask + * 0b0..The corresponding interrupt source is masked. + * 0b1..The corresponding interrupt source is not masked. + */ #define ENET_EIMR_BABR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_BABR_SHIFT)) & ENET_EIMR_BABR_MASK) +/*! @} */ /*! @name RDAR - Receive Descriptor Active Register */ +/*! @{ */ #define ENET_RDAR_RDAR_MASK (0x1000000U) #define ENET_RDAR_RDAR_SHIFT (24U) #define ENET_RDAR_RDAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_RDAR_RDAR_SHIFT)) & ENET_RDAR_RDAR_MASK) +/*! @} */ /*! @name TDAR - Transmit Descriptor Active Register */ +/*! @{ */ #define ENET_TDAR_TDAR_MASK (0x1000000U) #define ENET_TDAR_TDAR_SHIFT (24U) #define ENET_TDAR_TDAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_TDAR_TDAR_SHIFT)) & ENET_TDAR_TDAR_MASK) +/*! @} */ /*! @name ECR - Ethernet Control Register */ +/*! @{ */ #define ENET_ECR_RESET_MASK (0x1U) #define ENET_ECR_RESET_SHIFT (0U) #define ENET_ECR_RESET(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_RESET_SHIFT)) & ENET_ECR_RESET_MASK) #define ENET_ECR_ETHEREN_MASK (0x2U) #define ENET_ECR_ETHEREN_SHIFT (1U) +/*! ETHEREN - Ethernet Enable + * 0b0..Reception immediately stops and transmission stops after a bad CRC is appended to any currently transmitted frame. + * 0b1..MAC is enabled, and reception and transmission are possible. + */ #define ENET_ECR_ETHEREN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_ETHEREN_SHIFT)) & ENET_ECR_ETHEREN_MASK) #define ENET_ECR_MAGICEN_MASK (0x4U) #define ENET_ECR_MAGICEN_SHIFT (2U) +/*! MAGICEN - Magic Packet Detection Enable + * 0b0..Magic detection logic disabled. + * 0b1..The MAC core detects magic packets and asserts EIR[WAKEUP] when a frame is detected. + */ #define ENET_ECR_MAGICEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_MAGICEN_SHIFT)) & ENET_ECR_MAGICEN_MASK) #define ENET_ECR_SLEEP_MASK (0x8U) #define ENET_ECR_SLEEP_SHIFT (3U) +/*! SLEEP - Sleep Mode Enable + * 0b0..Normal operating mode. + * 0b1..Sleep mode. + */ #define ENET_ECR_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_SLEEP_SHIFT)) & ENET_ECR_SLEEP_MASK) #define ENET_ECR_EN1588_MASK (0x10U) #define ENET_ECR_EN1588_SHIFT (4U) +/*! EN1588 - EN1588 Enable + * 0b0..Legacy FEC buffer descriptors and functions enabled. + * 0b1..Enhanced frame time-stamping functions enabled. + */ #define ENET_ECR_EN1588(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_EN1588_SHIFT)) & ENET_ECR_EN1588_MASK) #define ENET_ECR_DBGEN_MASK (0x40U) #define ENET_ECR_DBGEN_SHIFT (6U) +/*! DBGEN - Debug Enable + * 0b0..MAC continues operation in debug mode. + * 0b1..MAC enters hardware freeze mode when the processor is in debug mode. + */ #define ENET_ECR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_DBGEN_SHIFT)) & ENET_ECR_DBGEN_MASK) #define ENET_ECR_DBSWP_MASK (0x100U) #define ENET_ECR_DBSWP_SHIFT (8U) +/*! DBSWP - Descriptor Byte Swapping Enable + * 0b0..The buffer descriptor bytes are not swapped to support big-endian devices. + * 0b1..The buffer descriptor bytes are swapped to support little-endian devices. + */ #define ENET_ECR_DBSWP(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_DBSWP_SHIFT)) & ENET_ECR_DBSWP_MASK) +/*! @} */ /*! @name MMFR - MII Management Frame Register */ +/*! @{ */ #define ENET_MMFR_DATA_MASK (0xFFFFU) #define ENET_MMFR_DATA_SHIFT (0U) #define ENET_MMFR_DATA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_DATA_SHIFT)) & ENET_MMFR_DATA_MASK) @@ -9124,41 +14071,85 @@ typedef struct { #define ENET_MMFR_ST_MASK (0xC0000000U) #define ENET_MMFR_ST_SHIFT (30U) #define ENET_MMFR_ST(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_ST_SHIFT)) & ENET_MMFR_ST_MASK) +/*! @} */ /*! @name MSCR - MII Speed Control Register */ +/*! @{ */ #define ENET_MSCR_MII_SPEED_MASK (0x7EU) #define ENET_MSCR_MII_SPEED_SHIFT (1U) #define ENET_MSCR_MII_SPEED(x) (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_MII_SPEED_SHIFT)) & ENET_MSCR_MII_SPEED_MASK) #define ENET_MSCR_DIS_PRE_MASK (0x80U) #define ENET_MSCR_DIS_PRE_SHIFT (7U) +/*! DIS_PRE - Disable Preamble + * 0b0..Preamble enabled. + * 0b1..Preamble (32 ones) is not prepended to the MII management frame. + */ #define ENET_MSCR_DIS_PRE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_DIS_PRE_SHIFT)) & ENET_MSCR_DIS_PRE_MASK) #define ENET_MSCR_HOLDTIME_MASK (0x700U) #define ENET_MSCR_HOLDTIME_SHIFT (8U) +/*! HOLDTIME - Hold time On MDIO Output + * 0b000..1 internal module clock cycle + * 0b001..2 internal module clock cycles + * 0b010..3 internal module clock cycles + * 0b111..8 internal module clock cycles + */ #define ENET_MSCR_HOLDTIME(x) (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_HOLDTIME_SHIFT)) & ENET_MSCR_HOLDTIME_MASK) +/*! @} */ /*! @name MIBC - MIB Control Register */ +/*! @{ */ #define ENET_MIBC_MIB_CLEAR_MASK (0x20000000U) #define ENET_MIBC_MIB_CLEAR_SHIFT (29U) +/*! MIB_CLEAR - MIB Clear + * 0b0..See note above. + * 0b1..All statistics counters are reset to 0. + */ #define ENET_MIBC_MIB_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_CLEAR_SHIFT)) & ENET_MIBC_MIB_CLEAR_MASK) #define ENET_MIBC_MIB_IDLE_MASK (0x40000000U) #define ENET_MIBC_MIB_IDLE_SHIFT (30U) +/*! MIB_IDLE - MIB Idle + * 0b0..The MIB block is updating MIB counters. + * 0b1..The MIB block is not currently updating any MIB counters. + */ #define ENET_MIBC_MIB_IDLE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_IDLE_SHIFT)) & ENET_MIBC_MIB_IDLE_MASK) #define ENET_MIBC_MIB_DIS_MASK (0x80000000U) #define ENET_MIBC_MIB_DIS_SHIFT (31U) +/*! MIB_DIS - Disable MIB Logic + * 0b0..MIB logic is enabled. + * 0b1..MIB logic is disabled. The MIB logic halts and does not update any MIB counters. + */ #define ENET_MIBC_MIB_DIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_DIS_SHIFT)) & ENET_MIBC_MIB_DIS_MASK) +/*! @} */ /*! @name RCR - Receive Control Register */ +/*! @{ */ #define ENET_RCR_LOOP_MASK (0x1U) #define ENET_RCR_LOOP_SHIFT (0U) +/*! LOOP - Internal Loopback + * 0b0..Loopback disabled. + * 0b1..Transmitted frames are looped back internal to the device and transmit MII output signals are not asserted. DRT must be cleared. + */ #define ENET_RCR_LOOP(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_LOOP_SHIFT)) & ENET_RCR_LOOP_MASK) #define ENET_RCR_DRT_MASK (0x2U) #define ENET_RCR_DRT_SHIFT (1U) +/*! DRT - Disable Receive On Transmit + * 0b0..Receive path operates independently of transmit (i.e., full-duplex mode). Can also be used to monitor transmit activity in half-duplex mode. + * 0b1..Disable reception of frames while transmitting. (Normally used for half-duplex mode.) + */ #define ENET_RCR_DRT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_DRT_SHIFT)) & ENET_RCR_DRT_MASK) #define ENET_RCR_MII_MODE_MASK (0x4U) #define ENET_RCR_MII_MODE_SHIFT (2U) +/*! MII_MODE - Media Independent Interface Mode + * 0b0..Reserved. + * 0b1..MII or RMII mode, as indicated by the RMII_MODE field. + */ #define ENET_RCR_MII_MODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_MII_MODE_SHIFT)) & ENET_RCR_MII_MODE_MASK) #define ENET_RCR_PROM_MASK (0x8U) #define ENET_RCR_PROM_SHIFT (3U) +/*! PROM - Promiscuous Mode + * 0b0..Disabled. + * 0b1..Enabled. + */ #define ENET_RCR_PROM(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PROM_SHIFT)) & ENET_RCR_PROM_MASK) #define ENET_RCR_BC_REJ_MASK (0x10U) #define ENET_RCR_BC_REJ_SHIFT (4U) @@ -9168,33 +14159,63 @@ typedef struct { #define ENET_RCR_FCE(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_FCE_SHIFT)) & ENET_RCR_FCE_MASK) #define ENET_RCR_RMII_MODE_MASK (0x100U) #define ENET_RCR_RMII_MODE_SHIFT (8U) +/*! RMII_MODE - RMII Mode Enable + * 0b0..MAC configured for MII mode. + * 0b1..MAC configured for RMII operation. + */ #define ENET_RCR_RMII_MODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_RMII_MODE_SHIFT)) & ENET_RCR_RMII_MODE_MASK) #define ENET_RCR_RMII_10T_MASK (0x200U) #define ENET_RCR_RMII_10T_SHIFT (9U) +/*! RMII_10T + * 0b0..100-Mbit/s operation. + * 0b1..10-Mbit/s operation. + */ #define ENET_RCR_RMII_10T(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_RMII_10T_SHIFT)) & ENET_RCR_RMII_10T_MASK) #define ENET_RCR_PADEN_MASK (0x1000U) #define ENET_RCR_PADEN_SHIFT (12U) +/*! PADEN - Enable Frame Padding Remove On Receive + * 0b0..No padding is removed on receive by the MAC. + * 0b1..Padding is removed from received frames. + */ #define ENET_RCR_PADEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PADEN_SHIFT)) & ENET_RCR_PADEN_MASK) #define ENET_RCR_PAUFWD_MASK (0x2000U) #define ENET_RCR_PAUFWD_SHIFT (13U) +/*! PAUFWD - Terminate/Forward Pause Frames + * 0b0..Pause frames are terminated and discarded in the MAC. + * 0b1..Pause frames are forwarded to the user application. + */ #define ENET_RCR_PAUFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PAUFWD_SHIFT)) & ENET_RCR_PAUFWD_MASK) #define ENET_RCR_CRCFWD_MASK (0x4000U) #define ENET_RCR_CRCFWD_SHIFT (14U) +/*! CRCFWD - Terminate/Forward Received CRC + * 0b0..The CRC field of received frames is transmitted to the user application. + * 0b1..The CRC field is stripped from the frame. + */ #define ENET_RCR_CRCFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_CRCFWD_SHIFT)) & ENET_RCR_CRCFWD_MASK) #define ENET_RCR_CFEN_MASK (0x8000U) #define ENET_RCR_CFEN_SHIFT (15U) +/*! CFEN - MAC Control Frame Enable + * 0b0..MAC control frames with any opcode other than 0x0001 (pause frame) are accepted and forwarded to the client interface. + * 0b1..MAC control frames with any opcode other than 0x0001 (pause frame) are silently discarded. + */ #define ENET_RCR_CFEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_CFEN_SHIFT)) & ENET_RCR_CFEN_MASK) #define ENET_RCR_MAX_FL_MASK (0x3FFF0000U) #define ENET_RCR_MAX_FL_SHIFT (16U) #define ENET_RCR_MAX_FL(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_MAX_FL_SHIFT)) & ENET_RCR_MAX_FL_MASK) #define ENET_RCR_NLC_MASK (0x40000000U) #define ENET_RCR_NLC_SHIFT (30U) +/*! NLC - Payload Length Check Disable + * 0b0..The payload length check is disabled. + * 0b1..The core checks the frame's payload length with the frame length/type field. Errors are indicated in the EIR[PLR] field. + */ #define ENET_RCR_NLC(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_NLC_SHIFT)) & ENET_RCR_NLC_MASK) #define ENET_RCR_GRS_MASK (0x80000000U) #define ENET_RCR_GRS_SHIFT (31U) #define ENET_RCR_GRS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_GRS_SHIFT)) & ENET_RCR_GRS_MASK) +/*! @} */ /*! @name TCR - Transmit Control Register */ +/*! @{ */ #define ENET_TCR_GTS_MASK (0x1U) #define ENET_TCR_GTS_SHIFT (0U) #define ENET_TCR_GTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_GTS_SHIFT)) & ENET_TCR_GTS_MASK) @@ -9203,42 +14224,68 @@ typedef struct { #define ENET_TCR_FDEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_FDEN_SHIFT)) & ENET_TCR_FDEN_MASK) #define ENET_TCR_TFC_PAUSE_MASK (0x8U) #define ENET_TCR_TFC_PAUSE_SHIFT (3U) +/*! TFC_PAUSE - Transmit Frame Control Pause + * 0b0..No PAUSE frame transmitted. + * 0b1..The MAC stops transmission of data frames after the current transmission is complete. + */ #define ENET_TCR_TFC_PAUSE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_TFC_PAUSE_SHIFT)) & ENET_TCR_TFC_PAUSE_MASK) #define ENET_TCR_RFC_PAUSE_MASK (0x10U) #define ENET_TCR_RFC_PAUSE_SHIFT (4U) #define ENET_TCR_RFC_PAUSE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_RFC_PAUSE_SHIFT)) & ENET_TCR_RFC_PAUSE_MASK) #define ENET_TCR_ADDSEL_MASK (0xE0U) #define ENET_TCR_ADDSEL_SHIFT (5U) +/*! ADDSEL - Source MAC Address Select On Transmit + * 0b000..Node MAC address programmed on PADDR1/2 registers. + * 0b100..Reserved. + * 0b101..Reserved. + * 0b110..Reserved. + */ #define ENET_TCR_ADDSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_ADDSEL_SHIFT)) & ENET_TCR_ADDSEL_MASK) #define ENET_TCR_ADDINS_MASK (0x100U) #define ENET_TCR_ADDINS_SHIFT (8U) +/*! ADDINS - Set MAC Address On Transmit + * 0b0..The source MAC address is not modified by the MAC. + * 0b1..The MAC overwrites the source MAC address with the programmed MAC address according to ADDSEL. + */ #define ENET_TCR_ADDINS(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_ADDINS_SHIFT)) & ENET_TCR_ADDINS_MASK) #define ENET_TCR_CRCFWD_MASK (0x200U) #define ENET_TCR_CRCFWD_SHIFT (9U) +/*! CRCFWD - Forward Frame From Application With CRC + * 0b0..TxBD[TC] controls whether the frame has a CRC from the application. + * 0b1..The transmitter does not append any CRC to transmitted frames, as it is expecting a frame with CRC from the application. + */ #define ENET_TCR_CRCFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_CRCFWD_SHIFT)) & ENET_TCR_CRCFWD_MASK) +/*! @} */ /*! @name PALR - Physical Address Lower Register */ +/*! @{ */ #define ENET_PALR_PADDR1_MASK (0xFFFFFFFFU) #define ENET_PALR_PADDR1_SHIFT (0U) #define ENET_PALR_PADDR1(x) (((uint32_t)(((uint32_t)(x)) << ENET_PALR_PADDR1_SHIFT)) & ENET_PALR_PADDR1_MASK) +/*! @} */ /*! @name PAUR - Physical Address Upper Register */ +/*! @{ */ #define ENET_PAUR_TYPE_MASK (0xFFFFU) #define ENET_PAUR_TYPE_SHIFT (0U) #define ENET_PAUR_TYPE(x) (((uint32_t)(((uint32_t)(x)) << ENET_PAUR_TYPE_SHIFT)) & ENET_PAUR_TYPE_MASK) #define ENET_PAUR_PADDR2_MASK (0xFFFF0000U) #define ENET_PAUR_PADDR2_SHIFT (16U) #define ENET_PAUR_PADDR2(x) (((uint32_t)(((uint32_t)(x)) << ENET_PAUR_PADDR2_SHIFT)) & ENET_PAUR_PADDR2_MASK) +/*! @} */ /*! @name OPD - Opcode/Pause Duration Register */ +/*! @{ */ #define ENET_OPD_PAUSE_DUR_MASK (0xFFFFU) #define ENET_OPD_PAUSE_DUR_SHIFT (0U) #define ENET_OPD_PAUSE_DUR(x) (((uint32_t)(((uint32_t)(x)) << ENET_OPD_PAUSE_DUR_SHIFT)) & ENET_OPD_PAUSE_DUR_MASK) #define ENET_OPD_OPCODE_MASK (0xFFFF0000U) #define ENET_OPD_OPCODE_SHIFT (16U) #define ENET_OPD_OPCODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_OPD_OPCODE_SHIFT)) & ENET_OPD_OPCODE_MASK) +/*! @} */ /*! @name TXIC - Transmit Interrupt Coalescing Register */ +/*! @{ */ #define ENET_TXIC_ICTT_MASK (0xFFFFU) #define ENET_TXIC_ICTT_SHIFT (0U) #define ENET_TXIC_ICTT(x) (((uint32_t)(((uint32_t)(x)) << ENET_TXIC_ICTT_SHIFT)) & ENET_TXIC_ICTT_MASK) @@ -9247,12 +14294,22 @@ typedef struct { #define ENET_TXIC_ICFT(x) (((uint32_t)(((uint32_t)(x)) << ENET_TXIC_ICFT_SHIFT)) & ENET_TXIC_ICFT_MASK) #define ENET_TXIC_ICCS_MASK (0x40000000U) #define ENET_TXIC_ICCS_SHIFT (30U) +/*! ICCS - Interrupt Coalescing Timer Clock Source Select + * 0b0..Use MII/GMII TX clocks. + * 0b1..Use ENET system clock. + */ #define ENET_TXIC_ICCS(x) (((uint32_t)(((uint32_t)(x)) << ENET_TXIC_ICCS_SHIFT)) & ENET_TXIC_ICCS_MASK) #define ENET_TXIC_ICEN_MASK (0x80000000U) #define ENET_TXIC_ICEN_SHIFT (31U) +/*! ICEN - Interrupt Coalescing Enable + * 0b0..Disable Interrupt coalescing. + * 0b1..Enable Interrupt coalescing. + */ #define ENET_TXIC_ICEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_TXIC_ICEN_SHIFT)) & ENET_TXIC_ICEN_MASK) +/*! @} */ /*! @name RXIC - Receive Interrupt Coalescing Register */ +/*! @{ */ #define ENET_RXIC_ICTT_MASK (0xFFFFU) #define ENET_RXIC_ICTT_SHIFT (0U) #define ENET_RXIC_ICTT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RXIC_ICTT_SHIFT)) & ENET_RXIC_ICTT_MASK) @@ -9261,482 +14318,773 @@ typedef struct { #define ENET_RXIC_ICFT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RXIC_ICFT_SHIFT)) & ENET_RXIC_ICFT_MASK) #define ENET_RXIC_ICCS_MASK (0x40000000U) #define ENET_RXIC_ICCS_SHIFT (30U) +/*! ICCS - Interrupt Coalescing Timer Clock Source Select + * 0b0..Use MII/GMII TX clocks. + * 0b1..Use ENET system clock. + */ #define ENET_RXIC_ICCS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RXIC_ICCS_SHIFT)) & ENET_RXIC_ICCS_MASK) #define ENET_RXIC_ICEN_MASK (0x80000000U) #define ENET_RXIC_ICEN_SHIFT (31U) +/*! ICEN - Interrupt Coalescing Enable + * 0b0..Disable Interrupt coalescing. + * 0b1..Enable Interrupt coalescing. + */ #define ENET_RXIC_ICEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_RXIC_ICEN_SHIFT)) & ENET_RXIC_ICEN_MASK) +/*! @} */ /*! @name IAUR - Descriptor Individual Upper Address Register */ +/*! @{ */ #define ENET_IAUR_IADDR1_MASK (0xFFFFFFFFU) #define ENET_IAUR_IADDR1_SHIFT (0U) #define ENET_IAUR_IADDR1(x) (((uint32_t)(((uint32_t)(x)) << ENET_IAUR_IADDR1_SHIFT)) & ENET_IAUR_IADDR1_MASK) +/*! @} */ /*! @name IALR - Descriptor Individual Lower Address Register */ +/*! @{ */ #define ENET_IALR_IADDR2_MASK (0xFFFFFFFFU) #define ENET_IALR_IADDR2_SHIFT (0U) #define ENET_IALR_IADDR2(x) (((uint32_t)(((uint32_t)(x)) << ENET_IALR_IADDR2_SHIFT)) & ENET_IALR_IADDR2_MASK) +/*! @} */ /*! @name GAUR - Descriptor Group Upper Address Register */ +/*! @{ */ #define ENET_GAUR_GADDR1_MASK (0xFFFFFFFFU) #define ENET_GAUR_GADDR1_SHIFT (0U) #define ENET_GAUR_GADDR1(x) (((uint32_t)(((uint32_t)(x)) << ENET_GAUR_GADDR1_SHIFT)) & ENET_GAUR_GADDR1_MASK) +/*! @} */ /*! @name GALR - Descriptor Group Lower Address Register */ +/*! @{ */ #define ENET_GALR_GADDR2_MASK (0xFFFFFFFFU) #define ENET_GALR_GADDR2_SHIFT (0U) #define ENET_GALR_GADDR2(x) (((uint32_t)(((uint32_t)(x)) << ENET_GALR_GADDR2_SHIFT)) & ENET_GALR_GADDR2_MASK) +/*! @} */ /*! @name TFWR - Transmit FIFO Watermark Register */ +/*! @{ */ #define ENET_TFWR_TFWR_MASK (0x3FU) #define ENET_TFWR_TFWR_SHIFT (0U) +/*! TFWR - Transmit FIFO Write + * 0b000000..64 bytes written. + * 0b000001..64 bytes written. + * 0b000010..128 bytes written. + * 0b000011..192 bytes written. + * 0b011111..1984 bytes written. + */ #define ENET_TFWR_TFWR(x) (((uint32_t)(((uint32_t)(x)) << ENET_TFWR_TFWR_SHIFT)) & ENET_TFWR_TFWR_MASK) #define ENET_TFWR_STRFWD_MASK (0x100U) #define ENET_TFWR_STRFWD_SHIFT (8U) +/*! STRFWD - Store And Forward Enable + * 0b0..Reset. The transmission start threshold is programmed in TFWR[TFWR]. + * 0b1..Enabled. + */ #define ENET_TFWR_STRFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_TFWR_STRFWD_SHIFT)) & ENET_TFWR_STRFWD_MASK) +/*! @} */ /*! @name RDSR - Receive Descriptor Ring Start Register */ +/*! @{ */ #define ENET_RDSR_R_DES_START_MASK (0xFFFFFFF8U) #define ENET_RDSR_R_DES_START_SHIFT (3U) #define ENET_RDSR_R_DES_START(x) (((uint32_t)(((uint32_t)(x)) << ENET_RDSR_R_DES_START_SHIFT)) & ENET_RDSR_R_DES_START_MASK) +/*! @} */ /*! @name TDSR - Transmit Buffer Descriptor Ring Start Register */ +/*! @{ */ #define ENET_TDSR_X_DES_START_MASK (0xFFFFFFF8U) #define ENET_TDSR_X_DES_START_SHIFT (3U) #define ENET_TDSR_X_DES_START(x) (((uint32_t)(((uint32_t)(x)) << ENET_TDSR_X_DES_START_SHIFT)) & ENET_TDSR_X_DES_START_MASK) +/*! @} */ /*! @name MRBR - Maximum Receive Buffer Size Register */ +/*! @{ */ #define ENET_MRBR_R_BUF_SIZE_MASK (0x3FF0U) #define ENET_MRBR_R_BUF_SIZE_SHIFT (4U) #define ENET_MRBR_R_BUF_SIZE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MRBR_R_BUF_SIZE_SHIFT)) & ENET_MRBR_R_BUF_SIZE_MASK) +/*! @} */ /*! @name RSFL - Receive FIFO Section Full Threshold */ +/*! @{ */ #define ENET_RSFL_RX_SECTION_FULL_MASK (0xFFU) #define ENET_RSFL_RX_SECTION_FULL_SHIFT (0U) #define ENET_RSFL_RX_SECTION_FULL(x) (((uint32_t)(((uint32_t)(x)) << ENET_RSFL_RX_SECTION_FULL_SHIFT)) & ENET_RSFL_RX_SECTION_FULL_MASK) +/*! @} */ /*! @name RSEM - Receive FIFO Section Empty Threshold */ +/*! @{ */ #define ENET_RSEM_RX_SECTION_EMPTY_MASK (0xFFU) #define ENET_RSEM_RX_SECTION_EMPTY_SHIFT (0U) #define ENET_RSEM_RX_SECTION_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_RSEM_RX_SECTION_EMPTY_SHIFT)) & ENET_RSEM_RX_SECTION_EMPTY_MASK) #define ENET_RSEM_STAT_SECTION_EMPTY_MASK (0x1F0000U) #define ENET_RSEM_STAT_SECTION_EMPTY_SHIFT (16U) #define ENET_RSEM_STAT_SECTION_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_RSEM_STAT_SECTION_EMPTY_SHIFT)) & ENET_RSEM_STAT_SECTION_EMPTY_MASK) +/*! @} */ /*! @name RAEM - Receive FIFO Almost Empty Threshold */ +/*! @{ */ #define ENET_RAEM_RX_ALMOST_EMPTY_MASK (0xFFU) #define ENET_RAEM_RX_ALMOST_EMPTY_SHIFT (0U) #define ENET_RAEM_RX_ALMOST_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_RAEM_RX_ALMOST_EMPTY_SHIFT)) & ENET_RAEM_RX_ALMOST_EMPTY_MASK) +/*! @} */ /*! @name RAFL - Receive FIFO Almost Full Threshold */ +/*! @{ */ #define ENET_RAFL_RX_ALMOST_FULL_MASK (0xFFU) #define ENET_RAFL_RX_ALMOST_FULL_SHIFT (0U) #define ENET_RAFL_RX_ALMOST_FULL(x) (((uint32_t)(((uint32_t)(x)) << ENET_RAFL_RX_ALMOST_FULL_SHIFT)) & ENET_RAFL_RX_ALMOST_FULL_MASK) +/*! @} */ /*! @name TSEM - Transmit FIFO Section Empty Threshold */ +/*! @{ */ #define ENET_TSEM_TX_SECTION_EMPTY_MASK (0xFFU) #define ENET_TSEM_TX_SECTION_EMPTY_SHIFT (0U) #define ENET_TSEM_TX_SECTION_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_TSEM_TX_SECTION_EMPTY_SHIFT)) & ENET_TSEM_TX_SECTION_EMPTY_MASK) +/*! @} */ /*! @name TAEM - Transmit FIFO Almost Empty Threshold */ +/*! @{ */ #define ENET_TAEM_TX_ALMOST_EMPTY_MASK (0xFFU) #define ENET_TAEM_TX_ALMOST_EMPTY_SHIFT (0U) #define ENET_TAEM_TX_ALMOST_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_TAEM_TX_ALMOST_EMPTY_SHIFT)) & ENET_TAEM_TX_ALMOST_EMPTY_MASK) +/*! @} */ /*! @name TAFL - Transmit FIFO Almost Full Threshold */ +/*! @{ */ #define ENET_TAFL_TX_ALMOST_FULL_MASK (0xFFU) #define ENET_TAFL_TX_ALMOST_FULL_SHIFT (0U) #define ENET_TAFL_TX_ALMOST_FULL(x) (((uint32_t)(((uint32_t)(x)) << ENET_TAFL_TX_ALMOST_FULL_SHIFT)) & ENET_TAFL_TX_ALMOST_FULL_MASK) +/*! @} */ /*! @name TIPG - Transmit Inter-Packet Gap */ +/*! @{ */ #define ENET_TIPG_IPG_MASK (0x1FU) #define ENET_TIPG_IPG_SHIFT (0U) #define ENET_TIPG_IPG(x) (((uint32_t)(((uint32_t)(x)) << ENET_TIPG_IPG_SHIFT)) & ENET_TIPG_IPG_MASK) +/*! @} */ /*! @name FTRL - Frame Truncation Length */ +/*! @{ */ #define ENET_FTRL_TRUNC_FL_MASK (0x3FFFU) #define ENET_FTRL_TRUNC_FL_SHIFT (0U) #define ENET_FTRL_TRUNC_FL(x) (((uint32_t)(((uint32_t)(x)) << ENET_FTRL_TRUNC_FL_SHIFT)) & ENET_FTRL_TRUNC_FL_MASK) +/*! @} */ /*! @name TACC - Transmit Accelerator Function Configuration */ +/*! @{ */ #define ENET_TACC_SHIFT16_MASK (0x1U) #define ENET_TACC_SHIFT16_SHIFT (0U) +/*! SHIFT16 - TX FIFO Shift-16 + * 0b0..Disabled. + * 0b1..Indicates to the transmit data FIFO that the written frames contain two additional octets before the frame data. This means the actual frame begins at bit 16 of the first word written into the FIFO. This function allows putting the frame payload on a 32-bit boundary in memory, as the 14-byte Ethernet header is extended to a 16-byte header. + */ #define ENET_TACC_SHIFT16(x) (((uint32_t)(((uint32_t)(x)) << ENET_TACC_SHIFT16_SHIFT)) & ENET_TACC_SHIFT16_MASK) #define ENET_TACC_IPCHK_MASK (0x8U) #define ENET_TACC_IPCHK_SHIFT (3U) +/*! IPCHK + * 0b0..Checksum is not inserted. + * 0b1..If an IP frame is transmitted, the checksum is inserted automatically. The IP header checksum field must be cleared. If a non-IP frame is transmitted the frame is not modified. + */ #define ENET_TACC_IPCHK(x) (((uint32_t)(((uint32_t)(x)) << ENET_TACC_IPCHK_SHIFT)) & ENET_TACC_IPCHK_MASK) #define ENET_TACC_PROCHK_MASK (0x10U) #define ENET_TACC_PROCHK_SHIFT (4U) +/*! PROCHK + * 0b0..Checksum not inserted. + * 0b1..If an IP frame with a known protocol is transmitted, the checksum is inserted automatically into the frame. The checksum field must be cleared. The other frames are not modified. + */ #define ENET_TACC_PROCHK(x) (((uint32_t)(((uint32_t)(x)) << ENET_TACC_PROCHK_SHIFT)) & ENET_TACC_PROCHK_MASK) +/*! @} */ /*! @name RACC - Receive Accelerator Function Configuration */ +/*! @{ */ #define ENET_RACC_PADREM_MASK (0x1U) #define ENET_RACC_PADREM_SHIFT (0U) +/*! PADREM - Enable Padding Removal For Short IP Frames + * 0b0..Padding not removed. + * 0b1..Any bytes following the IP payload section of the frame are removed from the frame. + */ #define ENET_RACC_PADREM(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_PADREM_SHIFT)) & ENET_RACC_PADREM_MASK) #define ENET_RACC_IPDIS_MASK (0x2U) #define ENET_RACC_IPDIS_SHIFT (1U) +/*! IPDIS - Enable Discard Of Frames With Wrong IPv4 Header Checksum + * 0b0..Frames with wrong IPv4 header checksum are not discarded. + * 0b1..If an IPv4 frame is received with a mismatching header checksum, the frame is discarded. IPv6 has no header checksum and is not affected by this setting. Discarding is only available when the RX FIFO operates in store and forward mode (RSFL cleared). + */ #define ENET_RACC_IPDIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_IPDIS_SHIFT)) & ENET_RACC_IPDIS_MASK) #define ENET_RACC_PRODIS_MASK (0x4U) #define ENET_RACC_PRODIS_SHIFT (2U) +/*! PRODIS - Enable Discard Of Frames With Wrong Protocol Checksum + * 0b0..Frames with wrong checksum are not discarded. + * 0b1..If a TCP/IP, UDP/IP, or ICMP/IP frame is received that has a wrong TCP, UDP, or ICMP checksum, the frame is discarded. Discarding is only available when the RX FIFO operates in store and forward mode (RSFL cleared). + */ #define ENET_RACC_PRODIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_PRODIS_SHIFT)) & ENET_RACC_PRODIS_MASK) #define ENET_RACC_LINEDIS_MASK (0x40U) #define ENET_RACC_LINEDIS_SHIFT (6U) +/*! LINEDIS - Enable Discard Of Frames With MAC Layer Errors + * 0b0..Frames with errors are not discarded. + * 0b1..Any frame received with a CRC, length, or PHY error is automatically discarded and not forwarded to the user application interface. + */ #define ENET_RACC_LINEDIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_LINEDIS_SHIFT)) & ENET_RACC_LINEDIS_MASK) #define ENET_RACC_SHIFT16_MASK (0x80U) #define ENET_RACC_SHIFT16_SHIFT (7U) +/*! SHIFT16 - RX FIFO Shift-16 + * 0b0..Disabled. + * 0b1..Instructs the MAC to write two additional bytes in front of each frame received into the RX FIFO. + */ #define ENET_RACC_SHIFT16(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_SHIFT16_SHIFT)) & ENET_RACC_SHIFT16_MASK) +/*! @} */ /*! @name RMON_T_PACKETS - Tx Packet Count Statistic Register */ +/*! @{ */ #define ENET_RMON_T_PACKETS_TXPKTS_MASK (0xFFFFU) #define ENET_RMON_T_PACKETS_TXPKTS_SHIFT (0U) #define ENET_RMON_T_PACKETS_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_PACKETS_TXPKTS_SHIFT)) & ENET_RMON_T_PACKETS_TXPKTS_MASK) +/*! @} */ /*! @name RMON_T_BC_PKT - Tx Broadcast Packets Statistic Register */ +/*! @{ */ #define ENET_RMON_T_BC_PKT_TXPKTS_MASK (0xFFFFU) #define ENET_RMON_T_BC_PKT_TXPKTS_SHIFT (0U) #define ENET_RMON_T_BC_PKT_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_BC_PKT_TXPKTS_SHIFT)) & ENET_RMON_T_BC_PKT_TXPKTS_MASK) +/*! @} */ /*! @name RMON_T_MC_PKT - Tx Multicast Packets Statistic Register */ +/*! @{ */ #define ENET_RMON_T_MC_PKT_TXPKTS_MASK (0xFFFFU) #define ENET_RMON_T_MC_PKT_TXPKTS_SHIFT (0U) #define ENET_RMON_T_MC_PKT_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_MC_PKT_TXPKTS_SHIFT)) & ENET_RMON_T_MC_PKT_TXPKTS_MASK) +/*! @} */ /*! @name RMON_T_CRC_ALIGN - Tx Packets with CRC/Align Error Statistic Register */ +/*! @{ */ #define ENET_RMON_T_CRC_ALIGN_TXPKTS_MASK (0xFFFFU) #define ENET_RMON_T_CRC_ALIGN_TXPKTS_SHIFT (0U) #define ENET_RMON_T_CRC_ALIGN_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_CRC_ALIGN_TXPKTS_SHIFT)) & ENET_RMON_T_CRC_ALIGN_TXPKTS_MASK) +/*! @} */ /*! @name RMON_T_UNDERSIZE - Tx Packets Less Than Bytes and Good CRC Statistic Register */ +/*! @{ */ #define ENET_RMON_T_UNDERSIZE_TXPKTS_MASK (0xFFFFU) #define ENET_RMON_T_UNDERSIZE_TXPKTS_SHIFT (0U) #define ENET_RMON_T_UNDERSIZE_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_UNDERSIZE_TXPKTS_SHIFT)) & ENET_RMON_T_UNDERSIZE_TXPKTS_MASK) +/*! @} */ /*! @name RMON_T_OVERSIZE - Tx Packets GT MAX_FL bytes and Good CRC Statistic Register */ +/*! @{ */ #define ENET_RMON_T_OVERSIZE_TXPKTS_MASK (0xFFFFU) #define ENET_RMON_T_OVERSIZE_TXPKTS_SHIFT (0U) #define ENET_RMON_T_OVERSIZE_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_OVERSIZE_TXPKTS_SHIFT)) & ENET_RMON_T_OVERSIZE_TXPKTS_MASK) +/*! @} */ /*! @name RMON_T_FRAG - Tx Packets Less Than 64 Bytes and Bad CRC Statistic Register */ +/*! @{ */ #define ENET_RMON_T_FRAG_TXPKTS_MASK (0xFFFFU) #define ENET_RMON_T_FRAG_TXPKTS_SHIFT (0U) #define ENET_RMON_T_FRAG_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_FRAG_TXPKTS_SHIFT)) & ENET_RMON_T_FRAG_TXPKTS_MASK) +/*! @} */ /*! @name RMON_T_JAB - Tx Packets Greater Than MAX_FL bytes and Bad CRC Statistic Register */ +/*! @{ */ #define ENET_RMON_T_JAB_TXPKTS_MASK (0xFFFFU) #define ENET_RMON_T_JAB_TXPKTS_SHIFT (0U) #define ENET_RMON_T_JAB_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_JAB_TXPKTS_SHIFT)) & ENET_RMON_T_JAB_TXPKTS_MASK) +/*! @} */ /*! @name RMON_T_COL - Tx Collision Count Statistic Register */ +/*! @{ */ #define ENET_RMON_T_COL_TXPKTS_MASK (0xFFFFU) #define ENET_RMON_T_COL_TXPKTS_SHIFT (0U) #define ENET_RMON_T_COL_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_COL_TXPKTS_SHIFT)) & ENET_RMON_T_COL_TXPKTS_MASK) +/*! @} */ /*! @name RMON_T_P64 - Tx 64-Byte Packets Statistic Register */ +/*! @{ */ #define ENET_RMON_T_P64_TXPKTS_MASK (0xFFFFU) #define ENET_RMON_T_P64_TXPKTS_SHIFT (0U) #define ENET_RMON_T_P64_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P64_TXPKTS_SHIFT)) & ENET_RMON_T_P64_TXPKTS_MASK) +/*! @} */ /*! @name RMON_T_P65TO127 - Tx 65- to 127-byte Packets Statistic Register */ +/*! @{ */ #define ENET_RMON_T_P65TO127_TXPKTS_MASK (0xFFFFU) #define ENET_RMON_T_P65TO127_TXPKTS_SHIFT (0U) #define ENET_RMON_T_P65TO127_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P65TO127_TXPKTS_SHIFT)) & ENET_RMON_T_P65TO127_TXPKTS_MASK) +/*! @} */ /*! @name RMON_T_P128TO255 - Tx 128- to 255-byte Packets Statistic Register */ +/*! @{ */ #define ENET_RMON_T_P128TO255_TXPKTS_MASK (0xFFFFU) #define ENET_RMON_T_P128TO255_TXPKTS_SHIFT (0U) #define ENET_RMON_T_P128TO255_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P128TO255_TXPKTS_SHIFT)) & ENET_RMON_T_P128TO255_TXPKTS_MASK) +/*! @} */ /*! @name RMON_T_P256TO511 - Tx 256- to 511-byte Packets Statistic Register */ +/*! @{ */ #define ENET_RMON_T_P256TO511_TXPKTS_MASK (0xFFFFU) #define ENET_RMON_T_P256TO511_TXPKTS_SHIFT (0U) #define ENET_RMON_T_P256TO511_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P256TO511_TXPKTS_SHIFT)) & ENET_RMON_T_P256TO511_TXPKTS_MASK) +/*! @} */ /*! @name RMON_T_P512TO1023 - Tx 512- to 1023-byte Packets Statistic Register */ +/*! @{ */ #define ENET_RMON_T_P512TO1023_TXPKTS_MASK (0xFFFFU) #define ENET_RMON_T_P512TO1023_TXPKTS_SHIFT (0U) #define ENET_RMON_T_P512TO1023_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P512TO1023_TXPKTS_SHIFT)) & ENET_RMON_T_P512TO1023_TXPKTS_MASK) +/*! @} */ /*! @name RMON_T_P1024TO2047 - Tx 1024- to 2047-byte Packets Statistic Register */ +/*! @{ */ #define ENET_RMON_T_P1024TO2047_TXPKTS_MASK (0xFFFFU) #define ENET_RMON_T_P1024TO2047_TXPKTS_SHIFT (0U) #define ENET_RMON_T_P1024TO2047_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P1024TO2047_TXPKTS_SHIFT)) & ENET_RMON_T_P1024TO2047_TXPKTS_MASK) +/*! @} */ /*! @name RMON_T_P_GTE2048 - Tx Packets Greater Than 2048 Bytes Statistic Register */ +/*! @{ */ #define ENET_RMON_T_P_GTE2048_TXPKTS_MASK (0xFFFFU) #define ENET_RMON_T_P_GTE2048_TXPKTS_SHIFT (0U) #define ENET_RMON_T_P_GTE2048_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P_GTE2048_TXPKTS_SHIFT)) & ENET_RMON_T_P_GTE2048_TXPKTS_MASK) +/*! @} */ /*! @name RMON_T_OCTETS - Tx Octets Statistic Register */ +/*! @{ */ #define ENET_RMON_T_OCTETS_TXOCTS_MASK (0xFFFFFFFFU) #define ENET_RMON_T_OCTETS_TXOCTS_SHIFT (0U) #define ENET_RMON_T_OCTETS_TXOCTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_OCTETS_TXOCTS_SHIFT)) & ENET_RMON_T_OCTETS_TXOCTS_MASK) +/*! @} */ /*! @name IEEE_T_FRAME_OK - Frames Transmitted OK Statistic Register */ +/*! @{ */ #define ENET_IEEE_T_FRAME_OK_COUNT_MASK (0xFFFFU) #define ENET_IEEE_T_FRAME_OK_COUNT_SHIFT (0U) #define ENET_IEEE_T_FRAME_OK_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_FRAME_OK_COUNT_SHIFT)) & ENET_IEEE_T_FRAME_OK_COUNT_MASK) +/*! @} */ /*! @name IEEE_T_1COL - Frames Transmitted with Single Collision Statistic Register */ +/*! @{ */ #define ENET_IEEE_T_1COL_COUNT_MASK (0xFFFFU) #define ENET_IEEE_T_1COL_COUNT_SHIFT (0U) #define ENET_IEEE_T_1COL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_1COL_COUNT_SHIFT)) & ENET_IEEE_T_1COL_COUNT_MASK) +/*! @} */ /*! @name IEEE_T_MCOL - Frames Transmitted with Multiple Collisions Statistic Register */ +/*! @{ */ #define ENET_IEEE_T_MCOL_COUNT_MASK (0xFFFFU) #define ENET_IEEE_T_MCOL_COUNT_SHIFT (0U) #define ENET_IEEE_T_MCOL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_MCOL_COUNT_SHIFT)) & ENET_IEEE_T_MCOL_COUNT_MASK) +/*! @} */ /*! @name IEEE_T_DEF - Frames Transmitted after Deferral Delay Statistic Register */ +/*! @{ */ #define ENET_IEEE_T_DEF_COUNT_MASK (0xFFFFU) #define ENET_IEEE_T_DEF_COUNT_SHIFT (0U) #define ENET_IEEE_T_DEF_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_DEF_COUNT_SHIFT)) & ENET_IEEE_T_DEF_COUNT_MASK) +/*! @} */ /*! @name IEEE_T_LCOL - Frames Transmitted with Late Collision Statistic Register */ +/*! @{ */ #define ENET_IEEE_T_LCOL_COUNT_MASK (0xFFFFU) #define ENET_IEEE_T_LCOL_COUNT_SHIFT (0U) #define ENET_IEEE_T_LCOL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_LCOL_COUNT_SHIFT)) & ENET_IEEE_T_LCOL_COUNT_MASK) +/*! @} */ /*! @name IEEE_T_EXCOL - Frames Transmitted with Excessive Collisions Statistic Register */ +/*! @{ */ #define ENET_IEEE_T_EXCOL_COUNT_MASK (0xFFFFU) #define ENET_IEEE_T_EXCOL_COUNT_SHIFT (0U) #define ENET_IEEE_T_EXCOL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_EXCOL_COUNT_SHIFT)) & ENET_IEEE_T_EXCOL_COUNT_MASK) +/*! @} */ /*! @name IEEE_T_MACERR - Frames Transmitted with Tx FIFO Underrun Statistic Register */ +/*! @{ */ #define ENET_IEEE_T_MACERR_COUNT_MASK (0xFFFFU) #define ENET_IEEE_T_MACERR_COUNT_SHIFT (0U) #define ENET_IEEE_T_MACERR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_MACERR_COUNT_SHIFT)) & ENET_IEEE_T_MACERR_COUNT_MASK) +/*! @} */ /*! @name IEEE_T_CSERR - Frames Transmitted with Carrier Sense Error Statistic Register */ +/*! @{ */ #define ENET_IEEE_T_CSERR_COUNT_MASK (0xFFFFU) #define ENET_IEEE_T_CSERR_COUNT_SHIFT (0U) #define ENET_IEEE_T_CSERR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_CSERR_COUNT_SHIFT)) & ENET_IEEE_T_CSERR_COUNT_MASK) +/*! @} */ /*! @name IEEE_T_SQE - Reserved Statistic Register */ +/*! @{ */ #define ENET_IEEE_T_SQE_COUNT_MASK (0xFFFFU) #define ENET_IEEE_T_SQE_COUNT_SHIFT (0U) #define ENET_IEEE_T_SQE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_SQE_COUNT_SHIFT)) & ENET_IEEE_T_SQE_COUNT_MASK) +/*! @} */ /*! @name IEEE_T_FDXFC - Flow Control Pause Frames Transmitted Statistic Register */ +/*! @{ */ #define ENET_IEEE_T_FDXFC_COUNT_MASK (0xFFFFU) #define ENET_IEEE_T_FDXFC_COUNT_SHIFT (0U) #define ENET_IEEE_T_FDXFC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_FDXFC_COUNT_SHIFT)) & ENET_IEEE_T_FDXFC_COUNT_MASK) +/*! @} */ /*! @name IEEE_T_OCTETS_OK - Octet Count for Frames Transmitted w/o Error Statistic Register */ +/*! @{ */ #define ENET_IEEE_T_OCTETS_OK_COUNT_MASK (0xFFFFFFFFU) #define ENET_IEEE_T_OCTETS_OK_COUNT_SHIFT (0U) #define ENET_IEEE_T_OCTETS_OK_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_OCTETS_OK_COUNT_SHIFT)) & ENET_IEEE_T_OCTETS_OK_COUNT_MASK) +/*! @} */ /*! @name RMON_R_PACKETS - Rx Packet Count Statistic Register */ +/*! @{ */ #define ENET_RMON_R_PACKETS_COUNT_MASK (0xFFFFU) #define ENET_RMON_R_PACKETS_COUNT_SHIFT (0U) #define ENET_RMON_R_PACKETS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_PACKETS_COUNT_SHIFT)) & ENET_RMON_R_PACKETS_COUNT_MASK) +/*! @} */ /*! @name RMON_R_BC_PKT - Rx Broadcast Packets Statistic Register */ +/*! @{ */ #define ENET_RMON_R_BC_PKT_COUNT_MASK (0xFFFFU) #define ENET_RMON_R_BC_PKT_COUNT_SHIFT (0U) #define ENET_RMON_R_BC_PKT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_BC_PKT_COUNT_SHIFT)) & ENET_RMON_R_BC_PKT_COUNT_MASK) +/*! @} */ /*! @name RMON_R_MC_PKT - Rx Multicast Packets Statistic Register */ +/*! @{ */ #define ENET_RMON_R_MC_PKT_COUNT_MASK (0xFFFFU) #define ENET_RMON_R_MC_PKT_COUNT_SHIFT (0U) #define ENET_RMON_R_MC_PKT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_MC_PKT_COUNT_SHIFT)) & ENET_RMON_R_MC_PKT_COUNT_MASK) +/*! @} */ /*! @name RMON_R_CRC_ALIGN - Rx Packets with CRC/Align Error Statistic Register */ +/*! @{ */ #define ENET_RMON_R_CRC_ALIGN_COUNT_MASK (0xFFFFU) #define ENET_RMON_R_CRC_ALIGN_COUNT_SHIFT (0U) #define ENET_RMON_R_CRC_ALIGN_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_CRC_ALIGN_COUNT_SHIFT)) & ENET_RMON_R_CRC_ALIGN_COUNT_MASK) +/*! @} */ /*! @name RMON_R_UNDERSIZE - Rx Packets with Less Than 64 Bytes and Good CRC Statistic Register */ +/*! @{ */ #define ENET_RMON_R_UNDERSIZE_COUNT_MASK (0xFFFFU) #define ENET_RMON_R_UNDERSIZE_COUNT_SHIFT (0U) #define ENET_RMON_R_UNDERSIZE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_UNDERSIZE_COUNT_SHIFT)) & ENET_RMON_R_UNDERSIZE_COUNT_MASK) +/*! @} */ /*! @name RMON_R_OVERSIZE - Rx Packets Greater Than MAX_FL and Good CRC Statistic Register */ +/*! @{ */ #define ENET_RMON_R_OVERSIZE_COUNT_MASK (0xFFFFU) #define ENET_RMON_R_OVERSIZE_COUNT_SHIFT (0U) #define ENET_RMON_R_OVERSIZE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_OVERSIZE_COUNT_SHIFT)) & ENET_RMON_R_OVERSIZE_COUNT_MASK) +/*! @} */ /*! @name RMON_R_FRAG - Rx Packets Less Than 64 Bytes and Bad CRC Statistic Register */ +/*! @{ */ #define ENET_RMON_R_FRAG_COUNT_MASK (0xFFFFU) #define ENET_RMON_R_FRAG_COUNT_SHIFT (0U) #define ENET_RMON_R_FRAG_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_FRAG_COUNT_SHIFT)) & ENET_RMON_R_FRAG_COUNT_MASK) +/*! @} */ /*! @name RMON_R_JAB - Rx Packets Greater Than MAX_FL Bytes and Bad CRC Statistic Register */ +/*! @{ */ #define ENET_RMON_R_JAB_COUNT_MASK (0xFFFFU) #define ENET_RMON_R_JAB_COUNT_SHIFT (0U) #define ENET_RMON_R_JAB_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_JAB_COUNT_SHIFT)) & ENET_RMON_R_JAB_COUNT_MASK) +/*! @} */ /*! @name RMON_R_P64 - Rx 64-Byte Packets Statistic Register */ +/*! @{ */ #define ENET_RMON_R_P64_COUNT_MASK (0xFFFFU) #define ENET_RMON_R_P64_COUNT_SHIFT (0U) #define ENET_RMON_R_P64_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P64_COUNT_SHIFT)) & ENET_RMON_R_P64_COUNT_MASK) +/*! @} */ /*! @name RMON_R_P65TO127 - Rx 65- to 127-Byte Packets Statistic Register */ +/*! @{ */ #define ENET_RMON_R_P65TO127_COUNT_MASK (0xFFFFU) #define ENET_RMON_R_P65TO127_COUNT_SHIFT (0U) #define ENET_RMON_R_P65TO127_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P65TO127_COUNT_SHIFT)) & ENET_RMON_R_P65TO127_COUNT_MASK) +/*! @} */ /*! @name RMON_R_P128TO255 - Rx 128- to 255-Byte Packets Statistic Register */ +/*! @{ */ #define ENET_RMON_R_P128TO255_COUNT_MASK (0xFFFFU) #define ENET_RMON_R_P128TO255_COUNT_SHIFT (0U) #define ENET_RMON_R_P128TO255_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P128TO255_COUNT_SHIFT)) & ENET_RMON_R_P128TO255_COUNT_MASK) +/*! @} */ /*! @name RMON_R_P256TO511 - Rx 256- to 511-Byte Packets Statistic Register */ +/*! @{ */ #define ENET_RMON_R_P256TO511_COUNT_MASK (0xFFFFU) #define ENET_RMON_R_P256TO511_COUNT_SHIFT (0U) #define ENET_RMON_R_P256TO511_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P256TO511_COUNT_SHIFT)) & ENET_RMON_R_P256TO511_COUNT_MASK) +/*! @} */ /*! @name RMON_R_P512TO1023 - Rx 512- to 1023-Byte Packets Statistic Register */ +/*! @{ */ #define ENET_RMON_R_P512TO1023_COUNT_MASK (0xFFFFU) #define ENET_RMON_R_P512TO1023_COUNT_SHIFT (0U) #define ENET_RMON_R_P512TO1023_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P512TO1023_COUNT_SHIFT)) & ENET_RMON_R_P512TO1023_COUNT_MASK) +/*! @} */ /*! @name RMON_R_P1024TO2047 - Rx 1024- to 2047-Byte Packets Statistic Register */ +/*! @{ */ #define ENET_RMON_R_P1024TO2047_COUNT_MASK (0xFFFFU) #define ENET_RMON_R_P1024TO2047_COUNT_SHIFT (0U) #define ENET_RMON_R_P1024TO2047_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P1024TO2047_COUNT_SHIFT)) & ENET_RMON_R_P1024TO2047_COUNT_MASK) +/*! @} */ /*! @name RMON_R_P_GTE2048 - Rx Packets Greater than 2048 Bytes Statistic Register */ +/*! @{ */ #define ENET_RMON_R_P_GTE2048_COUNT_MASK (0xFFFFU) #define ENET_RMON_R_P_GTE2048_COUNT_SHIFT (0U) #define ENET_RMON_R_P_GTE2048_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P_GTE2048_COUNT_SHIFT)) & ENET_RMON_R_P_GTE2048_COUNT_MASK) +/*! @} */ /*! @name RMON_R_OCTETS - Rx Octets Statistic Register */ +/*! @{ */ #define ENET_RMON_R_OCTETS_COUNT_MASK (0xFFFFFFFFU) #define ENET_RMON_R_OCTETS_COUNT_SHIFT (0U) #define ENET_RMON_R_OCTETS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_OCTETS_COUNT_SHIFT)) & ENET_RMON_R_OCTETS_COUNT_MASK) +/*! @} */ /*! @name IEEE_R_DROP - Frames not Counted Correctly Statistic Register */ +/*! @{ */ #define ENET_IEEE_R_DROP_COUNT_MASK (0xFFFFU) #define ENET_IEEE_R_DROP_COUNT_SHIFT (0U) #define ENET_IEEE_R_DROP_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_DROP_COUNT_SHIFT)) & ENET_IEEE_R_DROP_COUNT_MASK) +/*! @} */ /*! @name IEEE_R_FRAME_OK - Frames Received OK Statistic Register */ +/*! @{ */ #define ENET_IEEE_R_FRAME_OK_COUNT_MASK (0xFFFFU) #define ENET_IEEE_R_FRAME_OK_COUNT_SHIFT (0U) #define ENET_IEEE_R_FRAME_OK_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_FRAME_OK_COUNT_SHIFT)) & ENET_IEEE_R_FRAME_OK_COUNT_MASK) +/*! @} */ /*! @name IEEE_R_CRC - Frames Received with CRC Error Statistic Register */ +/*! @{ */ #define ENET_IEEE_R_CRC_COUNT_MASK (0xFFFFU) #define ENET_IEEE_R_CRC_COUNT_SHIFT (0U) #define ENET_IEEE_R_CRC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_CRC_COUNT_SHIFT)) & ENET_IEEE_R_CRC_COUNT_MASK) +/*! @} */ /*! @name IEEE_R_ALIGN - Frames Received with Alignment Error Statistic Register */ +/*! @{ */ #define ENET_IEEE_R_ALIGN_COUNT_MASK (0xFFFFU) #define ENET_IEEE_R_ALIGN_COUNT_SHIFT (0U) #define ENET_IEEE_R_ALIGN_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_ALIGN_COUNT_SHIFT)) & ENET_IEEE_R_ALIGN_COUNT_MASK) +/*! @} */ /*! @name IEEE_R_MACERR - Receive FIFO Overflow Count Statistic Register */ +/*! @{ */ #define ENET_IEEE_R_MACERR_COUNT_MASK (0xFFFFU) #define ENET_IEEE_R_MACERR_COUNT_SHIFT (0U) #define ENET_IEEE_R_MACERR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_MACERR_COUNT_SHIFT)) & ENET_IEEE_R_MACERR_COUNT_MASK) +/*! @} */ /*! @name IEEE_R_FDXFC - Flow Control Pause Frames Received Statistic Register */ +/*! @{ */ #define ENET_IEEE_R_FDXFC_COUNT_MASK (0xFFFFU) #define ENET_IEEE_R_FDXFC_COUNT_SHIFT (0U) #define ENET_IEEE_R_FDXFC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_FDXFC_COUNT_SHIFT)) & ENET_IEEE_R_FDXFC_COUNT_MASK) +/*! @} */ /*! @name IEEE_R_OCTETS_OK - Octet Count for Frames Received without Error Statistic Register */ +/*! @{ */ #define ENET_IEEE_R_OCTETS_OK_COUNT_MASK (0xFFFFFFFFU) #define ENET_IEEE_R_OCTETS_OK_COUNT_SHIFT (0U) #define ENET_IEEE_R_OCTETS_OK_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_OCTETS_OK_COUNT_SHIFT)) & ENET_IEEE_R_OCTETS_OK_COUNT_MASK) +/*! @} */ /*! @name ATCR - Adjustable Timer Control Register */ +/*! @{ */ #define ENET_ATCR_EN_MASK (0x1U) #define ENET_ATCR_EN_SHIFT (0U) +/*! EN - Enable Timer + * 0b0..The timer stops at the current value. + * 0b1..The timer starts incrementing. + */ #define ENET_ATCR_EN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_EN_SHIFT)) & ENET_ATCR_EN_MASK) #define ENET_ATCR_OFFEN_MASK (0x4U) #define ENET_ATCR_OFFEN_SHIFT (2U) +/*! OFFEN - Enable One-Shot Offset Event + * 0b0..Disable. + * 0b1..The timer can be reset to zero when the given offset time is reached (offset event). The field is cleared when the offset event is reached, so no further event occurs until the field is set again. The timer offset value must be set before setting this field. + */ #define ENET_ATCR_OFFEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_OFFEN_SHIFT)) & ENET_ATCR_OFFEN_MASK) #define ENET_ATCR_OFFRST_MASK (0x8U) #define ENET_ATCR_OFFRST_SHIFT (3U) +/*! OFFRST - Reset Timer On Offset Event + * 0b0..The timer is not affected and no action occurs, besides clearing OFFEN, when the offset is reached. + * 0b1..If OFFEN is set, the timer resets to zero when the offset setting is reached. The offset event does not cause a timer interrupt. + */ #define ENET_ATCR_OFFRST(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_OFFRST_SHIFT)) & ENET_ATCR_OFFRST_MASK) #define ENET_ATCR_PEREN_MASK (0x10U) #define ENET_ATCR_PEREN_SHIFT (4U) +/*! PEREN - Enable Periodical Event + * 0b0..Disable. + * 0b1..A period event interrupt can be generated (EIR[TS_TIMER]) and the event signal output is asserted when the timer wraps around according to the periodic setting ATPER. The timer period value must be set before setting this bit. Not all devices contain the event signal output. See the chip configuration details. + */ #define ENET_ATCR_PEREN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_PEREN_SHIFT)) & ENET_ATCR_PEREN_MASK) #define ENET_ATCR_PINPER_MASK (0x80U) #define ENET_ATCR_PINPER_SHIFT (7U) +/*! PINPER + * 0b0..Disable. + * 0b1..Enable. + */ #define ENET_ATCR_PINPER(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_PINPER_SHIFT)) & ENET_ATCR_PINPER_MASK) #define ENET_ATCR_RESTART_MASK (0x200U) #define ENET_ATCR_RESTART_SHIFT (9U) #define ENET_ATCR_RESTART(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_RESTART_SHIFT)) & ENET_ATCR_RESTART_MASK) #define ENET_ATCR_CAPTURE_MASK (0x800U) #define ENET_ATCR_CAPTURE_SHIFT (11U) +/*! CAPTURE - Capture Timer Value + * 0b0..No effect. + * 0b1..The current time is captured and can be read from the ATVR register. + */ #define ENET_ATCR_CAPTURE(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_CAPTURE_SHIFT)) & ENET_ATCR_CAPTURE_MASK) #define ENET_ATCR_SLAVE_MASK (0x2000U) #define ENET_ATCR_SLAVE_SHIFT (13U) +/*! SLAVE - Enable Timer Slave Mode + * 0b0..The timer is active and all configuration fields in this register are relevant. + * 0b1..The internal timer is disabled and the externally provided timer value is used. All other fields, except CAPTURE, in this register have no effect. CAPTURE can still be used to capture the current timer value. + */ #define ENET_ATCR_SLAVE(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_SLAVE_SHIFT)) & ENET_ATCR_SLAVE_MASK) +/*! @} */ /*! @name ATVR - Timer Value Register */ +/*! @{ */ #define ENET_ATVR_ATIME_MASK (0xFFFFFFFFU) #define ENET_ATVR_ATIME_SHIFT (0U) #define ENET_ATVR_ATIME(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATVR_ATIME_SHIFT)) & ENET_ATVR_ATIME_MASK) +/*! @} */ /*! @name ATOFF - Timer Offset Register */ +/*! @{ */ #define ENET_ATOFF_OFFSET_MASK (0xFFFFFFFFU) #define ENET_ATOFF_OFFSET_SHIFT (0U) #define ENET_ATOFF_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATOFF_OFFSET_SHIFT)) & ENET_ATOFF_OFFSET_MASK) +/*! @} */ /*! @name ATPER - Timer Period Register */ +/*! @{ */ #define ENET_ATPER_PERIOD_MASK (0xFFFFFFFFU) #define ENET_ATPER_PERIOD_SHIFT (0U) #define ENET_ATPER_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATPER_PERIOD_SHIFT)) & ENET_ATPER_PERIOD_MASK) +/*! @} */ /*! @name ATCOR - Timer Correction Register */ +/*! @{ */ #define ENET_ATCOR_COR_MASK (0x7FFFFFFFU) #define ENET_ATCOR_COR_SHIFT (0U) #define ENET_ATCOR_COR(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCOR_COR_SHIFT)) & ENET_ATCOR_COR_MASK) +/*! @} */ /*! @name ATINC - Time-Stamping Clock Period Register */ +/*! @{ */ #define ENET_ATINC_INC_MASK (0x7FU) #define ENET_ATINC_INC_SHIFT (0U) #define ENET_ATINC_INC(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATINC_INC_SHIFT)) & ENET_ATINC_INC_MASK) #define ENET_ATINC_INC_CORR_MASK (0x7F00U) #define ENET_ATINC_INC_CORR_SHIFT (8U) #define ENET_ATINC_INC_CORR(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATINC_INC_CORR_SHIFT)) & ENET_ATINC_INC_CORR_MASK) +/*! @} */ /*! @name ATSTMP - Timestamp of Last Transmitted Frame */ +/*! @{ */ #define ENET_ATSTMP_TIMESTAMP_MASK (0xFFFFFFFFU) #define ENET_ATSTMP_TIMESTAMP_SHIFT (0U) #define ENET_ATSTMP_TIMESTAMP(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATSTMP_TIMESTAMP_SHIFT)) & ENET_ATSTMP_TIMESTAMP_MASK) +/*! @} */ /*! @name TGSR - Timer Global Status Register */ +/*! @{ */ #define ENET_TGSR_TF0_MASK (0x1U) #define ENET_TGSR_TF0_SHIFT (0U) +/*! TF0 - Copy Of Timer Flag For Channel 0 + * 0b0..Timer Flag for Channel 0 is clear + * 0b1..Timer Flag for Channel 0 is set + */ #define ENET_TGSR_TF0(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF0_SHIFT)) & ENET_TGSR_TF0_MASK) #define ENET_TGSR_TF1_MASK (0x2U) #define ENET_TGSR_TF1_SHIFT (1U) +/*! TF1 - Copy Of Timer Flag For Channel 1 + * 0b0..Timer Flag for Channel 1 is clear + * 0b1..Timer Flag for Channel 1 is set + */ #define ENET_TGSR_TF1(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF1_SHIFT)) & ENET_TGSR_TF1_MASK) #define ENET_TGSR_TF2_MASK (0x4U) #define ENET_TGSR_TF2_SHIFT (2U) +/*! TF2 - Copy Of Timer Flag For Channel 2 + * 0b0..Timer Flag for Channel 2 is clear + * 0b1..Timer Flag for Channel 2 is set + */ #define ENET_TGSR_TF2(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF2_SHIFT)) & ENET_TGSR_TF2_MASK) #define ENET_TGSR_TF3_MASK (0x8U) #define ENET_TGSR_TF3_SHIFT (3U) +/*! TF3 - Copy Of Timer Flag For Channel 3 + * 0b0..Timer Flag for Channel 3 is clear + * 0b1..Timer Flag for Channel 3 is set + */ #define ENET_TGSR_TF3(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF3_SHIFT)) & ENET_TGSR_TF3_MASK) +/*! @} */ /*! @name TCSR - Timer Control Status Register */ +/*! @{ */ #define ENET_TCSR_TDRE_MASK (0x1U) #define ENET_TCSR_TDRE_SHIFT (0U) +/*! TDRE - Timer DMA Request Enable + * 0b0..DMA request is disabled + * 0b1..DMA request is enabled + */ #define ENET_TCSR_TDRE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TDRE_SHIFT)) & ENET_TCSR_TDRE_MASK) #define ENET_TCSR_TMODE_MASK (0x3CU) #define ENET_TCSR_TMODE_SHIFT (2U) +/*! TMODE - Timer Mode + * 0b0000..Timer Channel is disabled. + * 0b0001..Timer Channel is configured for Input Capture on rising edge. + * 0b0010..Timer Channel is configured for Input Capture on falling edge. + * 0b0011..Timer Channel is configured for Input Capture on both edges. + * 0b0100..Timer Channel is configured for Output Compare - software only. + * 0b0101..Timer Channel is configured for Output Compare - toggle output on compare. + * 0b0110..Timer Channel is configured for Output Compare - clear output on compare. + * 0b0111..Timer Channel is configured for Output Compare - set output on compare. + * 0b1000..Reserved + * 0b1010..Timer Channel is configured for Output Compare - clear output on compare, set output on overflow. + * 0b10x1..Timer Channel is configured for Output Compare - set output on compare, clear output on overflow. + * 0b110x..Reserved + * 0b1110..Timer Channel is configured for Output Compare - pulse output low on compare for 1 to 32 1588-clock cycles as specified by TPWC. + * 0b1111..Timer Channel is configured for Output Compare - pulse output high on compare for 1 to 32 1588-clock cycles as specified by TPWC. + */ #define ENET_TCSR_TMODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TMODE_SHIFT)) & ENET_TCSR_TMODE_MASK) #define ENET_TCSR_TIE_MASK (0x40U) #define ENET_TCSR_TIE_SHIFT (6U) +/*! TIE - Timer Interrupt Enable + * 0b0..Interrupt is disabled + * 0b1..Interrupt is enabled + */ #define ENET_TCSR_TIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TIE_SHIFT)) & ENET_TCSR_TIE_MASK) #define ENET_TCSR_TF_MASK (0x80U) #define ENET_TCSR_TF_SHIFT (7U) +/*! TF - Timer Flag + * 0b0..Input Capture or Output Compare has not occurred. + * 0b1..Input Capture or Output Compare has occurred. + */ #define ENET_TCSR_TF(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TF_SHIFT)) & ENET_TCSR_TF_MASK) #define ENET_TCSR_TPWC_MASK (0xF800U) #define ENET_TCSR_TPWC_SHIFT (11U) +/*! TPWC - Timer PulseWidth Control + * 0b00000..Pulse width is one 1588-clock cycle. + * 0b00001..Pulse width is two 1588-clock cycles. + * 0b00010..Pulse width is three 1588-clock cycles. + * 0b00011..Pulse width is four 1588-clock cycles. + * 0b11111..Pulse width is 32 1588-clock cycles. + */ #define ENET_TCSR_TPWC(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TPWC_SHIFT)) & ENET_TCSR_TPWC_MASK) +/*! @} */ /* The count of ENET_TCSR */ #define ENET_TCSR_COUNT (4U) /*! @name TCCR - Timer Compare Capture Register */ +/*! @{ */ #define ENET_TCCR_TCC_MASK (0xFFFFFFFFU) #define ENET_TCCR_TCC_SHIFT (0U) #define ENET_TCCR_TCC(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCCR_TCC_SHIFT)) & ENET_TCCR_TCC_MASK) +/*! @} */ /* The count of ENET_TCCR */ #define ENET_TCCR_COUNT (4U) @@ -9799,6 +15147,7 @@ typedef struct { */ /*! @name CTRL - Control Register */ +/*! @{ */ #define EWM_CTRL_EWMEN_MASK (0x1U) #define EWM_CTRL_EWMEN_SHIFT (0U) #define EWM_CTRL_EWMEN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_EWMEN_SHIFT)) & EWM_CTRL_EWMEN_MASK) @@ -9811,31 +15160,42 @@ typedef struct { #define EWM_CTRL_INTEN_MASK (0x8U) #define EWM_CTRL_INTEN_SHIFT (3U) #define EWM_CTRL_INTEN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_INTEN_SHIFT)) & EWM_CTRL_INTEN_MASK) +/*! @} */ /*! @name SERV - Service Register */ +/*! @{ */ #define EWM_SERV_SERVICE_MASK (0xFFU) #define EWM_SERV_SERVICE_SHIFT (0U) #define EWM_SERV_SERVICE(x) (((uint8_t)(((uint8_t)(x)) << EWM_SERV_SERVICE_SHIFT)) & EWM_SERV_SERVICE_MASK) +/*! @} */ /*! @name CMPL - Compare Low Register */ +/*! @{ */ #define EWM_CMPL_COMPAREL_MASK (0xFFU) #define EWM_CMPL_COMPAREL_SHIFT (0U) #define EWM_CMPL_COMPAREL(x) (((uint8_t)(((uint8_t)(x)) << EWM_CMPL_COMPAREL_SHIFT)) & EWM_CMPL_COMPAREL_MASK) +/*! @} */ /*! @name CMPH - Compare High Register */ +/*! @{ */ #define EWM_CMPH_COMPAREH_MASK (0xFFU) #define EWM_CMPH_COMPAREH_SHIFT (0U) #define EWM_CMPH_COMPAREH(x) (((uint8_t)(((uint8_t)(x)) << EWM_CMPH_COMPAREH_SHIFT)) & EWM_CMPH_COMPAREH_MASK) +/*! @} */ /*! @name CLKCTRL - Clock Control Register */ +/*! @{ */ #define EWM_CLKCTRL_CLKSEL_MASK (0x3U) #define EWM_CLKCTRL_CLKSEL_SHIFT (0U) #define EWM_CLKCTRL_CLKSEL(x) (((uint8_t)(((uint8_t)(x)) << EWM_CLKCTRL_CLKSEL_SHIFT)) & EWM_CLKCTRL_CLKSEL_MASK) +/*! @} */ /*! @name CLKPRESCALER - Clock Prescaler Register */ +/*! @{ */ #define EWM_CLKPRESCALER_CLK_DIV_MASK (0xFFU) #define EWM_CLKPRESCALER_CLK_DIV_SHIFT (0U) #define EWM_CLKPRESCALER_CLK_DIV(x) (((uint8_t)(((uint8_t)(x)) << EWM_CLKPRESCALER_CLK_DIV_SHIFT)) & EWM_CLKPRESCALER_CLK_DIV_MASK) +/*! @} */ /*! @@ -9922,8 +15282,13 @@ typedef struct { */ /*! @name VERID - Version ID Register */ +/*! @{ */ #define FLEXIO_VERID_FEATURE_MASK (0xFFFFU) #define FLEXIO_VERID_FEATURE_SHIFT (0U) +/*! FEATURE - Feature Specification Number + * 0b0000000000000000..Standard features implemented. + * 0b0000000000000001..Supports state, logic and parallel modes. + */ #define FLEXIO_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_FEATURE_SHIFT)) & FLEXIO_VERID_FEATURE_MASK) #define FLEXIO_VERID_MINOR_MASK (0xFF0000U) #define FLEXIO_VERID_MINOR_SHIFT (16U) @@ -9931,8 +15296,10 @@ typedef struct { #define FLEXIO_VERID_MAJOR_MASK (0xFF000000U) #define FLEXIO_VERID_MAJOR_SHIFT (24U) #define FLEXIO_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_MAJOR_SHIFT)) & FLEXIO_VERID_MAJOR_MASK) +/*! @} */ /*! @name PARAM - Parameter Register */ +/*! @{ */ #define FLEXIO_PARAM_SHIFTER_MASK (0xFFU) #define FLEXIO_PARAM_SHIFTER_SHIFT (0U) #define FLEXIO_PARAM_SHIFTER(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_SHIFTER_SHIFT)) & FLEXIO_PARAM_SHIFTER_MASK) @@ -9945,221 +15312,402 @@ typedef struct { #define FLEXIO_PARAM_TRIGGER_MASK (0xFF000000U) #define FLEXIO_PARAM_TRIGGER_SHIFT (24U) #define FLEXIO_PARAM_TRIGGER(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_TRIGGER_SHIFT)) & FLEXIO_PARAM_TRIGGER_MASK) +/*! @} */ /*! @name CTRL - FlexIO Control Register */ +/*! @{ */ #define FLEXIO_CTRL_FLEXEN_MASK (0x1U) #define FLEXIO_CTRL_FLEXEN_SHIFT (0U) +/*! FLEXEN - FlexIO Enable + * 0b0..FlexIO module is disabled. + * 0b1..FlexIO module is enabled. + */ #define FLEXIO_CTRL_FLEXEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_FLEXEN_SHIFT)) & FLEXIO_CTRL_FLEXEN_MASK) #define FLEXIO_CTRL_SWRST_MASK (0x2U) #define FLEXIO_CTRL_SWRST_SHIFT (1U) +/*! SWRST - Software Reset + * 0b0..Software reset is disabled + * 0b1..Software reset is enabled, all FlexIO registers except the Control Register are reset. + */ #define FLEXIO_CTRL_SWRST(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_SWRST_SHIFT)) & FLEXIO_CTRL_SWRST_MASK) #define FLEXIO_CTRL_FASTACC_MASK (0x4U) #define FLEXIO_CTRL_FASTACC_SHIFT (2U) +/*! FASTACC - Fast Access + * 0b0..Configures for normal register accesses to FlexIO + * 0b1..Configures for fast register accesses to FlexIO + */ #define FLEXIO_CTRL_FASTACC(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_FASTACC_SHIFT)) & FLEXIO_CTRL_FASTACC_MASK) #define FLEXIO_CTRL_DBGE_MASK (0x40000000U) #define FLEXIO_CTRL_DBGE_SHIFT (30U) +/*! DBGE - Debug Enable + * 0b0..FlexIO is disabled in debug modes. + * 0b1..FlexIO is enabled in debug modes + */ #define FLEXIO_CTRL_DBGE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_DBGE_SHIFT)) & FLEXIO_CTRL_DBGE_MASK) #define FLEXIO_CTRL_DOZEN_MASK (0x80000000U) #define FLEXIO_CTRL_DOZEN_SHIFT (31U) +/*! DOZEN - Doze Enable + * 0b0..FlexIO enabled in Doze modes. + * 0b1..FlexIO disabled in Doze modes. + */ #define FLEXIO_CTRL_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_DOZEN_SHIFT)) & FLEXIO_CTRL_DOZEN_MASK) +/*! @} */ /*! @name PIN - Pin State Register */ +/*! @{ */ #define FLEXIO_PIN_PDI_MASK (0xFFFFFFFFU) #define FLEXIO_PIN_PDI_SHIFT (0U) #define FLEXIO_PIN_PDI(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PIN_PDI_SHIFT)) & FLEXIO_PIN_PDI_MASK) +/*! @} */ /*! @name SHIFTSTAT - Shifter Status Register */ +/*! @{ */ #define FLEXIO_SHIFTSTAT_SSF_MASK (0xFU) #define FLEXIO_SHIFTSTAT_SSF_SHIFT (0U) #define FLEXIO_SHIFTSTAT_SSF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSTAT_SSF_SHIFT)) & FLEXIO_SHIFTSTAT_SSF_MASK) +/*! @} */ /*! @name SHIFTERR - Shifter Error Register */ +/*! @{ */ #define FLEXIO_SHIFTERR_SEF_MASK (0xFU) #define FLEXIO_SHIFTERR_SEF_SHIFT (0U) #define FLEXIO_SHIFTERR_SEF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTERR_SEF_SHIFT)) & FLEXIO_SHIFTERR_SEF_MASK) +/*! @} */ /*! @name TIMSTAT - Timer Status Register */ +/*! @{ */ #define FLEXIO_TIMSTAT_TSF_MASK (0xFU) #define FLEXIO_TIMSTAT_TSF_SHIFT (0U) #define FLEXIO_TIMSTAT_TSF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMSTAT_TSF_SHIFT)) & FLEXIO_TIMSTAT_TSF_MASK) +/*! @} */ /*! @name SHIFTSIEN - Shifter Status Interrupt Enable */ +/*! @{ */ #define FLEXIO_SHIFTSIEN_SSIE_MASK (0xFU) #define FLEXIO_SHIFTSIEN_SSIE_SHIFT (0U) #define FLEXIO_SHIFTSIEN_SSIE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSIEN_SSIE_SHIFT)) & FLEXIO_SHIFTSIEN_SSIE_MASK) +/*! @} */ /*! @name SHIFTEIEN - Shifter Error Interrupt Enable */ +/*! @{ */ #define FLEXIO_SHIFTEIEN_SEIE_MASK (0xFU) #define FLEXIO_SHIFTEIEN_SEIE_SHIFT (0U) #define FLEXIO_SHIFTEIEN_SEIE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTEIEN_SEIE_SHIFT)) & FLEXIO_SHIFTEIEN_SEIE_MASK) +/*! @} */ /*! @name TIMIEN - Timer Interrupt Enable Register */ +/*! @{ */ #define FLEXIO_TIMIEN_TEIE_MASK (0xFU) #define FLEXIO_TIMIEN_TEIE_SHIFT (0U) #define FLEXIO_TIMIEN_TEIE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMIEN_TEIE_SHIFT)) & FLEXIO_TIMIEN_TEIE_MASK) +/*! @} */ /*! @name SHIFTSDEN - Shifter Status DMA Enable */ +/*! @{ */ #define FLEXIO_SHIFTSDEN_SSDE_MASK (0xFU) #define FLEXIO_SHIFTSDEN_SSDE_SHIFT (0U) #define FLEXIO_SHIFTSDEN_SSDE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSDEN_SSDE_SHIFT)) & FLEXIO_SHIFTSDEN_SSDE_MASK) +/*! @} */ /*! @name SHIFTSTATE - Shifter State Register */ +/*! @{ */ #define FLEXIO_SHIFTSTATE_STATE_MASK (0x7U) #define FLEXIO_SHIFTSTATE_STATE_SHIFT (0U) #define FLEXIO_SHIFTSTATE_STATE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSTATE_STATE_SHIFT)) & FLEXIO_SHIFTSTATE_STATE_MASK) +/*! @} */ /*! @name SHIFTCTL - Shifter Control N Register */ +/*! @{ */ #define FLEXIO_SHIFTCTL_SMOD_MASK (0x7U) #define FLEXIO_SHIFTCTL_SMOD_SHIFT (0U) +/*! SMOD - Shifter Mode + * 0b000..Disabled. + * 0b001..Receive mode. Captures the current Shifter content into the SHIFTBUF on expiration of the Timer. + * 0b010..Transmit mode. Load SHIFTBUF contents into the Shifter on expiration of the Timer. + * 0b011..Reserved. + * 0b100..Match Store mode. Shifter data is compared to SHIFTBUF content on expiration of the Timer. + * 0b101..Match Continuous mode. Shifter data is continuously compared to SHIFTBUF contents. + * 0b110..State mode. SHIFTBUF contents are used for storing programmable state attributes. + * 0b111..Logic mode. SHIFTBUF contents are used for implementing programmable logic look up table. + */ #define FLEXIO_SHIFTCTL_SMOD(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_SMOD_SHIFT)) & FLEXIO_SHIFTCTL_SMOD_MASK) #define FLEXIO_SHIFTCTL_PINPOL_MASK (0x80U) #define FLEXIO_SHIFTCTL_PINPOL_SHIFT (7U) +/*! PINPOL - Shifter Pin Polarity + * 0b0..Pin is active high + * 0b1..Pin is active low + */ #define FLEXIO_SHIFTCTL_PINPOL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINPOL_SHIFT)) & FLEXIO_SHIFTCTL_PINPOL_MASK) #define FLEXIO_SHIFTCTL_PINSEL_MASK (0x1F00U) #define FLEXIO_SHIFTCTL_PINSEL_SHIFT (8U) #define FLEXIO_SHIFTCTL_PINSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINSEL_SHIFT)) & FLEXIO_SHIFTCTL_PINSEL_MASK) #define FLEXIO_SHIFTCTL_PINCFG_MASK (0x30000U) #define FLEXIO_SHIFTCTL_PINCFG_SHIFT (16U) +/*! PINCFG - Shifter Pin Configuration + * 0b00..Shifter pin output disabled + * 0b01..Shifter pin open drain or bidirectional output enable + * 0b10..Shifter pin bidirectional output data + * 0b11..Shifter pin output + */ #define FLEXIO_SHIFTCTL_PINCFG(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINCFG_SHIFT)) & FLEXIO_SHIFTCTL_PINCFG_MASK) #define FLEXIO_SHIFTCTL_TIMPOL_MASK (0x800000U) #define FLEXIO_SHIFTCTL_TIMPOL_SHIFT (23U) +/*! TIMPOL - Timer Polarity + * 0b0..Shift on posedge of Shift clock + * 0b1..Shift on negedge of Shift clock + */ #define FLEXIO_SHIFTCTL_TIMPOL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_TIMPOL_SHIFT)) & FLEXIO_SHIFTCTL_TIMPOL_MASK) #define FLEXIO_SHIFTCTL_TIMSEL_MASK (0x3000000U) #define FLEXIO_SHIFTCTL_TIMSEL_SHIFT (24U) #define FLEXIO_SHIFTCTL_TIMSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_TIMSEL_SHIFT)) & FLEXIO_SHIFTCTL_TIMSEL_MASK) +/*! @} */ /* The count of FLEXIO_SHIFTCTL */ #define FLEXIO_SHIFTCTL_COUNT (4U) /*! @name SHIFTCFG - Shifter Configuration N Register */ +/*! @{ */ #define FLEXIO_SHIFTCFG_SSTART_MASK (0x3U) #define FLEXIO_SHIFTCFG_SSTART_SHIFT (0U) +/*! SSTART - Shifter Start bit + * 0b00..Start bit disabled for transmitter/receiver/match store, transmitter loads data on enable + * 0b01..Start bit disabled for transmitter/receiver/match store, transmitter loads data on first shift + * 0b10..Transmitter outputs start bit value 0 before loading data on first shift, receiver/match store sets error flag if start bit is not 0 + * 0b11..Transmitter outputs start bit value 1 before loading data on first shift, receiver/match store sets error flag if start bit is not 1 + */ #define FLEXIO_SHIFTCFG_SSTART(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_SSTART_SHIFT)) & FLEXIO_SHIFTCFG_SSTART_MASK) #define FLEXIO_SHIFTCFG_SSTOP_MASK (0x30U) #define FLEXIO_SHIFTCFG_SSTOP_SHIFT (4U) +/*! SSTOP - Shifter Stop bit + * 0b00..Stop bit disabled for transmitter/receiver/match store + * 0b01..Reserved for transmitter/receiver/match store + * 0b10..Transmitter outputs stop bit value 0 on store, receiver/match store sets error flag if stop bit is not 0 + * 0b11..Transmitter outputs stop bit value 1 on store, receiver/match store sets error flag if stop bit is not 1 + */ #define FLEXIO_SHIFTCFG_SSTOP(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_SSTOP_SHIFT)) & FLEXIO_SHIFTCFG_SSTOP_MASK) #define FLEXIO_SHIFTCFG_INSRC_MASK (0x100U) #define FLEXIO_SHIFTCFG_INSRC_SHIFT (8U) +/*! INSRC - Input Source + * 0b0..Pin + * 0b1..Shifter N+1 Output + */ #define FLEXIO_SHIFTCFG_INSRC(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_INSRC_SHIFT)) & FLEXIO_SHIFTCFG_INSRC_MASK) #define FLEXIO_SHIFTCFG_PWIDTH_MASK (0x1F0000U) #define FLEXIO_SHIFTCFG_PWIDTH_SHIFT (16U) #define FLEXIO_SHIFTCFG_PWIDTH(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_PWIDTH_SHIFT)) & FLEXIO_SHIFTCFG_PWIDTH_MASK) +/*! @} */ /* The count of FLEXIO_SHIFTCFG */ #define FLEXIO_SHIFTCFG_COUNT (4U) /*! @name SHIFTBUF - Shifter Buffer N Register */ +/*! @{ */ #define FLEXIO_SHIFTBUF_SHIFTBUF_MASK (0xFFFFFFFFU) #define FLEXIO_SHIFTBUF_SHIFTBUF_SHIFT (0U) #define FLEXIO_SHIFTBUF_SHIFTBUF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUF_SHIFTBUF_SHIFT)) & FLEXIO_SHIFTBUF_SHIFTBUF_MASK) +/*! @} */ /* The count of FLEXIO_SHIFTBUF */ #define FLEXIO_SHIFTBUF_COUNT (4U) /*! @name SHIFTBUFBIS - Shifter Buffer N Bit Swapped Register */ +/*! @{ */ #define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_MASK (0xFFFFFFFFU) #define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_SHIFT (0U) #define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_SHIFT)) & FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_MASK) +/*! @} */ /* The count of FLEXIO_SHIFTBUFBIS */ #define FLEXIO_SHIFTBUFBIS_COUNT (4U) /*! @name SHIFTBUFBYS - Shifter Buffer N Byte Swapped Register */ +/*! @{ */ #define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_MASK (0xFFFFFFFFU) #define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_SHIFT (0U) #define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_SHIFT)) & FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_MASK) +/*! @} */ /* The count of FLEXIO_SHIFTBUFBYS */ #define FLEXIO_SHIFTBUFBYS_COUNT (4U) /*! @name SHIFTBUFBBS - Shifter Buffer N Bit Byte Swapped Register */ +/*! @{ */ #define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_MASK (0xFFFFFFFFU) #define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_SHIFT (0U) #define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_SHIFT)) & FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_MASK) +/*! @} */ /* The count of FLEXIO_SHIFTBUFBBS */ #define FLEXIO_SHIFTBUFBBS_COUNT (4U) /*! @name TIMCTL - Timer Control N Register */ +/*! @{ */ #define FLEXIO_TIMCTL_TIMOD_MASK (0x3U) #define FLEXIO_TIMCTL_TIMOD_SHIFT (0U) +/*! TIMOD - Timer Mode + * 0b00..Timer Disabled. + * 0b01..Dual 8-bit counters baud mode. + * 0b10..Dual 8-bit counters PWM high mode. + * 0b11..Single 16-bit counter mode. + */ #define FLEXIO_TIMCTL_TIMOD(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TIMOD_SHIFT)) & FLEXIO_TIMCTL_TIMOD_MASK) #define FLEXIO_TIMCTL_PINPOL_MASK (0x80U) #define FLEXIO_TIMCTL_PINPOL_SHIFT (7U) +/*! PINPOL - Timer Pin Polarity + * 0b0..Pin is active high + * 0b1..Pin is active low + */ #define FLEXIO_TIMCTL_PINPOL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINPOL_SHIFT)) & FLEXIO_TIMCTL_PINPOL_MASK) #define FLEXIO_TIMCTL_PINSEL_MASK (0x1F00U) #define FLEXIO_TIMCTL_PINSEL_SHIFT (8U) #define FLEXIO_TIMCTL_PINSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINSEL_SHIFT)) & FLEXIO_TIMCTL_PINSEL_MASK) #define FLEXIO_TIMCTL_PINCFG_MASK (0x30000U) #define FLEXIO_TIMCTL_PINCFG_SHIFT (16U) +/*! PINCFG - Timer Pin Configuration + * 0b00..Timer pin output disabled + * 0b01..Timer pin open drain or bidirectional output enable + * 0b10..Timer pin bidirectional output data + * 0b11..Timer pin output + */ #define FLEXIO_TIMCTL_PINCFG(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINCFG_SHIFT)) & FLEXIO_TIMCTL_PINCFG_MASK) #define FLEXIO_TIMCTL_TRGSRC_MASK (0x400000U) #define FLEXIO_TIMCTL_TRGSRC_SHIFT (22U) +/*! TRGSRC - Trigger Source + * 0b0..External trigger selected + * 0b1..Internal trigger selected + */ #define FLEXIO_TIMCTL_TRGSRC(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGSRC_SHIFT)) & FLEXIO_TIMCTL_TRGSRC_MASK) #define FLEXIO_TIMCTL_TRGPOL_MASK (0x800000U) #define FLEXIO_TIMCTL_TRGPOL_SHIFT (23U) +/*! TRGPOL - Trigger Polarity + * 0b0..Trigger active high + * 0b1..Trigger active low + */ #define FLEXIO_TIMCTL_TRGPOL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGPOL_SHIFT)) & FLEXIO_TIMCTL_TRGPOL_MASK) #define FLEXIO_TIMCTL_TRGSEL_MASK (0x3F000000U) #define FLEXIO_TIMCTL_TRGSEL_SHIFT (24U) #define FLEXIO_TIMCTL_TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGSEL_SHIFT)) & FLEXIO_TIMCTL_TRGSEL_MASK) +/*! @} */ /* The count of FLEXIO_TIMCTL */ #define FLEXIO_TIMCTL_COUNT (4U) /*! @name TIMCFG - Timer Configuration N Register */ +/*! @{ */ #define FLEXIO_TIMCFG_TSTART_MASK (0x2U) #define FLEXIO_TIMCFG_TSTART_SHIFT (1U) +/*! TSTART - Timer Start Bit + * 0b0..Start bit disabled + * 0b1..Start bit enabled + */ #define FLEXIO_TIMCFG_TSTART(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TSTART_SHIFT)) & FLEXIO_TIMCFG_TSTART_MASK) #define FLEXIO_TIMCFG_TSTOP_MASK (0x30U) #define FLEXIO_TIMCFG_TSTOP_SHIFT (4U) +/*! TSTOP - Timer Stop Bit + * 0b00..Stop bit disabled + * 0b01..Stop bit is enabled on timer compare + * 0b10..Stop bit is enabled on timer disable + * 0b11..Stop bit is enabled on timer compare and timer disable + */ #define FLEXIO_TIMCFG_TSTOP(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TSTOP_SHIFT)) & FLEXIO_TIMCFG_TSTOP_MASK) #define FLEXIO_TIMCFG_TIMENA_MASK (0x700U) #define FLEXIO_TIMCFG_TIMENA_SHIFT (8U) +/*! TIMENA - Timer Enable + * 0b000..Timer always enabled + * 0b001..Timer enabled on Timer N-1 enable + * 0b010..Timer enabled on Trigger high + * 0b011..Timer enabled on Trigger high and Pin high + * 0b100..Timer enabled on Pin rising edge + * 0b101..Timer enabled on Pin rising edge and Trigger high + * 0b110..Timer enabled on Trigger rising edge + * 0b111..Timer enabled on Trigger rising or falling edge + */ #define FLEXIO_TIMCFG_TIMENA(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMENA_SHIFT)) & FLEXIO_TIMCFG_TIMENA_MASK) #define FLEXIO_TIMCFG_TIMDIS_MASK (0x7000U) #define FLEXIO_TIMCFG_TIMDIS_SHIFT (12U) +/*! TIMDIS - Timer Disable + * 0b000..Timer never disabled + * 0b001..Timer disabled on Timer N-1 disable + * 0b010..Timer disabled on Timer compare (upper 8-bits match and decrement) + * 0b011..Timer disabled on Timer compare (upper 8-bits match and decrement) and Trigger Low + * 0b100..Timer disabled on Pin rising or falling edge + * 0b101..Timer disabled on Pin rising or falling edge provided Trigger is high + * 0b110..Timer disabled on Trigger falling edge + * 0b111..Reserved + */ #define FLEXIO_TIMCFG_TIMDIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMDIS_SHIFT)) & FLEXIO_TIMCFG_TIMDIS_MASK) #define FLEXIO_TIMCFG_TIMRST_MASK (0x70000U) #define FLEXIO_TIMCFG_TIMRST_SHIFT (16U) +/*! TIMRST - Timer Reset + * 0b000..Timer never reset + * 0b001..Reserved + * 0b010..Timer reset on Timer Pin equal to Timer Output + * 0b011..Timer reset on Timer Trigger equal to Timer Output + * 0b100..Timer reset on Timer Pin rising edge + * 0b101..Reserved + * 0b110..Timer reset on Trigger rising edge + * 0b111..Timer reset on Trigger rising or falling edge + */ #define FLEXIO_TIMCFG_TIMRST(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMRST_SHIFT)) & FLEXIO_TIMCFG_TIMRST_MASK) #define FLEXIO_TIMCFG_TIMDEC_MASK (0x300000U) #define FLEXIO_TIMCFG_TIMDEC_SHIFT (20U) +/*! TIMDEC - Timer Decrement + * 0b00..Decrement counter on FlexIO clock, Shift clock equals Timer output. + * 0b01..Decrement counter on Trigger input (both edges), Shift clock equals Timer output. + * 0b10..Decrement counter on Pin input (both edges), Shift clock equals Pin input. + * 0b11..Decrement counter on Trigger input (both edges), Shift clock equals Trigger input. + */ #define FLEXIO_TIMCFG_TIMDEC(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMDEC_SHIFT)) & FLEXIO_TIMCFG_TIMDEC_MASK) #define FLEXIO_TIMCFG_TIMOUT_MASK (0x3000000U) #define FLEXIO_TIMCFG_TIMOUT_SHIFT (24U) +/*! TIMOUT - Timer Output + * 0b00..Timer output is logic one when enabled and is not affected by timer reset + * 0b01..Timer output is logic zero when enabled and is not affected by timer reset + * 0b10..Timer output is logic one when enabled and on timer reset + * 0b11..Timer output is logic zero when enabled and on timer reset + */ #define FLEXIO_TIMCFG_TIMOUT(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMOUT_SHIFT)) & FLEXIO_TIMCFG_TIMOUT_MASK) +/*! @} */ /* The count of FLEXIO_TIMCFG */ #define FLEXIO_TIMCFG_COUNT (4U) /*! @name TIMCMP - Timer Compare N Register */ +/*! @{ */ #define FLEXIO_TIMCMP_CMP_MASK (0xFFFFU) #define FLEXIO_TIMCMP_CMP_SHIFT (0U) #define FLEXIO_TIMCMP_CMP(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCMP_CMP_SHIFT)) & FLEXIO_TIMCMP_CMP_MASK) +/*! @} */ /* The count of FLEXIO_TIMCMP */ #define FLEXIO_TIMCMP_COUNT (4U) /*! @name SHIFTBUFNBS - Shifter Buffer N Nibble Byte Swapped Register */ +/*! @{ */ #define FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_MASK (0xFFFFFFFFU) #define FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_SHIFT (0U) #define FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_SHIFT)) & FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_MASK) +/*! @} */ /* The count of FLEXIO_SHIFTBUFNBS */ #define FLEXIO_SHIFTBUFNBS_COUNT (4U) /*! @name SHIFTBUFHWS - Shifter Buffer N Half Word Swapped Register */ +/*! @{ */ #define FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_MASK (0xFFFFFFFFU) #define FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_SHIFT (0U) #define FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_SHIFT)) & FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_MASK) +/*! @} */ /* The count of FLEXIO_SHIFTBUFHWS */ #define FLEXIO_SHIFTBUFHWS_COUNT (4U) /*! @name SHIFTBUFNIS - Shifter Buffer N Nibble Swapped Register */ +/*! @{ */ #define FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_MASK (0xFFFFFFFFU) #define FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_SHIFT (0U) #define FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_SHIFT)) & FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_MASK) +/*! @} */ /* The count of FLEXIO_SHIFTBUFNIS */ #define FLEXIO_SHIFTBUFNIS_COUNT (4U) @@ -10203,9 +15751,7 @@ typedef struct { /** FLEXRAM - Register Layout Typedef */ typedef struct { __IO uint32_t TCM_CTRL; /**< TCM CRTL Register, offset: 0x0 */ - __IO uint32_t OCRAM_MAGIC_ADDR; /**< OCRAM Magic Address Register, offset: 0x4 */ - __IO uint32_t DTCM_MAGIC_ADDR; /**< DTCM Magic Address Register, offset: 0x8 */ - __IO uint32_t ITCM_MAGIC_ADDR; /**< ITCM Magic Address Register, offset: 0xC */ + uint8_t RESERVED_0[12]; __IO uint32_t INT_STATUS; /**< Interrupt Status Register, offset: 0x10 */ __IO uint32_t INT_STAT_EN; /**< Interrupt Status Enable Register, offset: 0x14 */ __IO uint32_t INT_SIG_EN; /**< Interrupt Enable Register, offset: 0x18 */ @@ -10221,120 +15767,100 @@ typedef struct { */ /*! @name TCM_CTRL - TCM CRTL Register */ +/*! @{ */ #define FLEXRAM_TCM_CTRL_TCM_WWAIT_EN_MASK (0x1U) #define FLEXRAM_TCM_CTRL_TCM_WWAIT_EN_SHIFT (0U) +/*! TCM_WWAIT_EN - TCM Write Wait Mode Enable + * 0b0..TCM write fast mode: Write RAM accesses are expected to be finished in 1-cycle. + * 0b1..TCM write wait mode: Write RAM accesses are expected to be finished in 2-cycles. + */ #define FLEXRAM_TCM_CTRL_TCM_WWAIT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_TCM_CTRL_TCM_WWAIT_EN_SHIFT)) & FLEXRAM_TCM_CTRL_TCM_WWAIT_EN_MASK) #define FLEXRAM_TCM_CTRL_TCM_RWAIT_EN_MASK (0x2U) #define FLEXRAM_TCM_CTRL_TCM_RWAIT_EN_SHIFT (1U) +/*! TCM_RWAIT_EN - TCM Read Wait Mode Enable + * 0b0..TCM read fast mode: Read RAM accesses are expected to be finished in 1-cycle. + * 0b1..TCM read wait mode: Read RAM accesses are expected to be finished in 2-cycles. + */ #define FLEXRAM_TCM_CTRL_TCM_RWAIT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_TCM_CTRL_TCM_RWAIT_EN_SHIFT)) & FLEXRAM_TCM_CTRL_TCM_RWAIT_EN_MASK) #define FLEXRAM_TCM_CTRL_FORCE_CLK_ON_MASK (0x4U) #define FLEXRAM_TCM_CTRL_FORCE_CLK_ON_SHIFT (2U) #define FLEXRAM_TCM_CTRL_FORCE_CLK_ON(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_TCM_CTRL_FORCE_CLK_ON_SHIFT)) & FLEXRAM_TCM_CTRL_FORCE_CLK_ON_MASK) -#define FLEXRAM_TCM_CTRL_Reserved_MASK (0xFFFFFFF8U) -#define FLEXRAM_TCM_CTRL_Reserved_SHIFT (3U) -#define FLEXRAM_TCM_CTRL_Reserved(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_TCM_CTRL_Reserved_SHIFT)) & FLEXRAM_TCM_CTRL_Reserved_MASK) - -/*! @name OCRAM_MAGIC_ADDR - OCRAM Magic Address Register */ -#define FLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_WR_RD_SEL_MASK (0x1U) -#define FLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_WR_RD_SEL_SHIFT (0U) -#define FLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_WR_RD_SEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_WR_RD_SEL_SHIFT)) & FLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_WR_RD_SEL_MASK) -#define FLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_MAGIC_ADDR_MASK (0x1FFFEU) -#define FLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_MAGIC_ADDR_SHIFT (1U) -#define FLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_MAGIC_ADDR(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_MAGIC_ADDR_SHIFT)) & FLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_MAGIC_ADDR_MASK) -#define FLEXRAM_OCRAM_MAGIC_ADDR_Reserved_MASK (0xFFFE0000U) -#define FLEXRAM_OCRAM_MAGIC_ADDR_Reserved_SHIFT (17U) -#define FLEXRAM_OCRAM_MAGIC_ADDR_Reserved(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_OCRAM_MAGIC_ADDR_Reserved_SHIFT)) & FLEXRAM_OCRAM_MAGIC_ADDR_Reserved_MASK) - -/*! @name DTCM_MAGIC_ADDR - DTCM Magic Address Register */ -#define FLEXRAM_DTCM_MAGIC_ADDR_DTCM_WR_RD_SEL_MASK (0x1U) -#define FLEXRAM_DTCM_MAGIC_ADDR_DTCM_WR_RD_SEL_SHIFT (0U) -#define FLEXRAM_DTCM_MAGIC_ADDR_DTCM_WR_RD_SEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_DTCM_MAGIC_ADDR_DTCM_WR_RD_SEL_SHIFT)) & FLEXRAM_DTCM_MAGIC_ADDR_DTCM_WR_RD_SEL_MASK) -#define FLEXRAM_DTCM_MAGIC_ADDR_DTCM_MAGIC_ADDR_MASK (0x1FFFEU) -#define FLEXRAM_DTCM_MAGIC_ADDR_DTCM_MAGIC_ADDR_SHIFT (1U) -#define FLEXRAM_DTCM_MAGIC_ADDR_DTCM_MAGIC_ADDR(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_DTCM_MAGIC_ADDR_DTCM_MAGIC_ADDR_SHIFT)) & FLEXRAM_DTCM_MAGIC_ADDR_DTCM_MAGIC_ADDR_MASK) -#define FLEXRAM_DTCM_MAGIC_ADDR_Reserved_MASK (0xFFFE0000U) -#define FLEXRAM_DTCM_MAGIC_ADDR_Reserved_SHIFT (17U) -#define FLEXRAM_DTCM_MAGIC_ADDR_Reserved(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_DTCM_MAGIC_ADDR_Reserved_SHIFT)) & FLEXRAM_DTCM_MAGIC_ADDR_Reserved_MASK) - -/*! @name ITCM_MAGIC_ADDR - ITCM Magic Address Register */ -#define FLEXRAM_ITCM_MAGIC_ADDR_ITCM_WR_RD_SEL_MASK (0x1U) -#define FLEXRAM_ITCM_MAGIC_ADDR_ITCM_WR_RD_SEL_SHIFT (0U) -#define FLEXRAM_ITCM_MAGIC_ADDR_ITCM_WR_RD_SEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_ITCM_MAGIC_ADDR_ITCM_WR_RD_SEL_SHIFT)) & FLEXRAM_ITCM_MAGIC_ADDR_ITCM_WR_RD_SEL_MASK) -#define FLEXRAM_ITCM_MAGIC_ADDR_ITCM_MAGIC_ADDR_MASK (0x1FFFEU) -#define FLEXRAM_ITCM_MAGIC_ADDR_ITCM_MAGIC_ADDR_SHIFT (1U) -#define FLEXRAM_ITCM_MAGIC_ADDR_ITCM_MAGIC_ADDR(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_ITCM_MAGIC_ADDR_ITCM_MAGIC_ADDR_SHIFT)) & FLEXRAM_ITCM_MAGIC_ADDR_ITCM_MAGIC_ADDR_MASK) -#define FLEXRAM_ITCM_MAGIC_ADDR_Reserved_MASK (0xFFFE0000U) -#define FLEXRAM_ITCM_MAGIC_ADDR_Reserved_SHIFT (17U) -#define FLEXRAM_ITCM_MAGIC_ADDR_Reserved(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_ITCM_MAGIC_ADDR_Reserved_SHIFT)) & FLEXRAM_ITCM_MAGIC_ADDR_Reserved_MASK) +/*! @} */ /*! @name INT_STATUS - Interrupt Status Register */ -#define FLEXRAM_INT_STATUS_ITCM_MAM_STATUS_MASK (0x1U) -#define FLEXRAM_INT_STATUS_ITCM_MAM_STATUS_SHIFT (0U) -#define FLEXRAM_INT_STATUS_ITCM_MAM_STATUS(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_ITCM_MAM_STATUS_SHIFT)) & FLEXRAM_INT_STATUS_ITCM_MAM_STATUS_MASK) -#define FLEXRAM_INT_STATUS_DTCM_MAM_STATUS_MASK (0x2U) -#define FLEXRAM_INT_STATUS_DTCM_MAM_STATUS_SHIFT (1U) -#define FLEXRAM_INT_STATUS_DTCM_MAM_STATUS(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_DTCM_MAM_STATUS_SHIFT)) & FLEXRAM_INT_STATUS_DTCM_MAM_STATUS_MASK) -#define FLEXRAM_INT_STATUS_OCRAM_MAM_STATUS_MASK (0x4U) -#define FLEXRAM_INT_STATUS_OCRAM_MAM_STATUS_SHIFT (2U) -#define FLEXRAM_INT_STATUS_OCRAM_MAM_STATUS(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_OCRAM_MAM_STATUS_SHIFT)) & FLEXRAM_INT_STATUS_OCRAM_MAM_STATUS_MASK) +/*! @{ */ #define FLEXRAM_INT_STATUS_ITCM_ERR_STATUS_MASK (0x8U) #define FLEXRAM_INT_STATUS_ITCM_ERR_STATUS_SHIFT (3U) +/*! ITCM_ERR_STATUS - ITCM Access Error Status + * 0b0..ITCM access error does not happen + * 0b1..ITCM access error happens. + */ #define FLEXRAM_INT_STATUS_ITCM_ERR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_ITCM_ERR_STATUS_SHIFT)) & FLEXRAM_INT_STATUS_ITCM_ERR_STATUS_MASK) #define FLEXRAM_INT_STATUS_DTCM_ERR_STATUS_MASK (0x10U) #define FLEXRAM_INT_STATUS_DTCM_ERR_STATUS_SHIFT (4U) +/*! DTCM_ERR_STATUS - DTCM Access Error Status + * 0b0..DTCM access error does not happen + * 0b1..DTCM access error happens. + */ #define FLEXRAM_INT_STATUS_DTCM_ERR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_DTCM_ERR_STATUS_SHIFT)) & FLEXRAM_INT_STATUS_DTCM_ERR_STATUS_MASK) #define FLEXRAM_INT_STATUS_OCRAM_ERR_STATUS_MASK (0x20U) #define FLEXRAM_INT_STATUS_OCRAM_ERR_STATUS_SHIFT (5U) +/*! OCRAM_ERR_STATUS - OCRAM Access Error Status + * 0b0..OCRAM access error does not happen + * 0b1..OCRAM access error happens. + */ #define FLEXRAM_INT_STATUS_OCRAM_ERR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_OCRAM_ERR_STATUS_SHIFT)) & FLEXRAM_INT_STATUS_OCRAM_ERR_STATUS_MASK) -#define FLEXRAM_INT_STATUS_Reserved_MASK (0xFFFFFFC0U) -#define FLEXRAM_INT_STATUS_Reserved_SHIFT (6U) -#define FLEXRAM_INT_STATUS_Reserved(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_Reserved_SHIFT)) & FLEXRAM_INT_STATUS_Reserved_MASK) +/*! @} */ /*! @name INT_STAT_EN - Interrupt Status Enable Register */ -#define FLEXRAM_INT_STAT_EN_ITCM_MAM_STAT_EN_MASK (0x1U) -#define FLEXRAM_INT_STAT_EN_ITCM_MAM_STAT_EN_SHIFT (0U) -#define FLEXRAM_INT_STAT_EN_ITCM_MAM_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_ITCM_MAM_STAT_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_ITCM_MAM_STAT_EN_MASK) -#define FLEXRAM_INT_STAT_EN_DTCM_MAM_STAT_EN_MASK (0x2U) -#define FLEXRAM_INT_STAT_EN_DTCM_MAM_STAT_EN_SHIFT (1U) -#define FLEXRAM_INT_STAT_EN_DTCM_MAM_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_DTCM_MAM_STAT_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_DTCM_MAM_STAT_EN_MASK) -#define FLEXRAM_INT_STAT_EN_OCRAM_MAM_STAT_EN_MASK (0x4U) -#define FLEXRAM_INT_STAT_EN_OCRAM_MAM_STAT_EN_SHIFT (2U) -#define FLEXRAM_INT_STAT_EN_OCRAM_MAM_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_OCRAM_MAM_STAT_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_OCRAM_MAM_STAT_EN_MASK) +/*! @{ */ #define FLEXRAM_INT_STAT_EN_ITCM_ERR_STAT_EN_MASK (0x8U) #define FLEXRAM_INT_STAT_EN_ITCM_ERR_STAT_EN_SHIFT (3U) +/*! ITCM_ERR_STAT_EN - ITCM Access Error Status Enable + * 0b0..Masked + * 0b1..Enabled + */ #define FLEXRAM_INT_STAT_EN_ITCM_ERR_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_ITCM_ERR_STAT_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_ITCM_ERR_STAT_EN_MASK) #define FLEXRAM_INT_STAT_EN_DTCM_ERR_STAT_EN_MASK (0x10U) #define FLEXRAM_INT_STAT_EN_DTCM_ERR_STAT_EN_SHIFT (4U) +/*! DTCM_ERR_STAT_EN - DTCM Access Error Status Enable + * 0b0..Masked + * 0b1..Enabled + */ #define FLEXRAM_INT_STAT_EN_DTCM_ERR_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_DTCM_ERR_STAT_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_DTCM_ERR_STAT_EN_MASK) #define FLEXRAM_INT_STAT_EN_OCRAM_ERR_STAT_EN_MASK (0x20U) #define FLEXRAM_INT_STAT_EN_OCRAM_ERR_STAT_EN_SHIFT (5U) +/*! OCRAM_ERR_STAT_EN - OCRAM Access Error Status Enable + * 0b0..Masked + * 0b1..Enabled + */ #define FLEXRAM_INT_STAT_EN_OCRAM_ERR_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_OCRAM_ERR_STAT_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_OCRAM_ERR_STAT_EN_MASK) -#define FLEXRAM_INT_STAT_EN_Reserved_MASK (0xFFFFFFC0U) -#define FLEXRAM_INT_STAT_EN_Reserved_SHIFT (6U) -#define FLEXRAM_INT_STAT_EN_Reserved(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_Reserved_SHIFT)) & FLEXRAM_INT_STAT_EN_Reserved_MASK) +/*! @} */ /*! @name INT_SIG_EN - Interrupt Enable Register */ -#define FLEXRAM_INT_SIG_EN_ITCM_MAM_SIG_EN_MASK (0x1U) -#define FLEXRAM_INT_SIG_EN_ITCM_MAM_SIG_EN_SHIFT (0U) -#define FLEXRAM_INT_SIG_EN_ITCM_MAM_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_ITCM_MAM_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_ITCM_MAM_SIG_EN_MASK) -#define FLEXRAM_INT_SIG_EN_DTCM_MAM_SIG_EN_MASK (0x2U) -#define FLEXRAM_INT_SIG_EN_DTCM_MAM_SIG_EN_SHIFT (1U) -#define FLEXRAM_INT_SIG_EN_DTCM_MAM_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_DTCM_MAM_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_DTCM_MAM_SIG_EN_MASK) -#define FLEXRAM_INT_SIG_EN_OCRAM_MAM_SIG_EN_MASK (0x4U) -#define FLEXRAM_INT_SIG_EN_OCRAM_MAM_SIG_EN_SHIFT (2U) -#define FLEXRAM_INT_SIG_EN_OCRAM_MAM_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_OCRAM_MAM_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_OCRAM_MAM_SIG_EN_MASK) +/*! @{ */ #define FLEXRAM_INT_SIG_EN_ITCM_ERR_SIG_EN_MASK (0x8U) #define FLEXRAM_INT_SIG_EN_ITCM_ERR_SIG_EN_SHIFT (3U) +/*! ITCM_ERR_SIG_EN - ITCM Access Error Interrupt Enable + * 0b0..Masked + * 0b1..Enabled + */ #define FLEXRAM_INT_SIG_EN_ITCM_ERR_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_ITCM_ERR_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_ITCM_ERR_SIG_EN_MASK) #define FLEXRAM_INT_SIG_EN_DTCM_ERR_SIG_EN_MASK (0x10U) #define FLEXRAM_INT_SIG_EN_DTCM_ERR_SIG_EN_SHIFT (4U) +/*! DTCM_ERR_SIG_EN - DTCM Access Error Interrupt Enable + * 0b0..Masked + * 0b1..Enabled + */ #define FLEXRAM_INT_SIG_EN_DTCM_ERR_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_DTCM_ERR_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_DTCM_ERR_SIG_EN_MASK) #define FLEXRAM_INT_SIG_EN_OCRAM_ERR_SIG_EN_MASK (0x20U) #define FLEXRAM_INT_SIG_EN_OCRAM_ERR_SIG_EN_SHIFT (5U) +/*! OCRAM_ERR_SIG_EN - OCRAM Access Error Interrupt Enable + * 0b0..Masked + * 0b1..Enabled + */ #define FLEXRAM_INT_SIG_EN_OCRAM_ERR_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_OCRAM_ERR_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_OCRAM_ERR_SIG_EN_MASK) -#define FLEXRAM_INT_SIG_EN_Reserved_MASK (0xFFFFFFC0U) -#define FLEXRAM_INT_SIG_EN_Reserved_SHIFT (6U) -#define FLEXRAM_INT_SIG_EN_Reserved(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_Reserved_SHIFT)) & FLEXRAM_INT_SIG_EN_Reserved_MASK) +/*! @} */ /*! @@ -10417,6 +15943,7 @@ typedef struct { */ /*! @name MCR0 - Module Control Register 0 */ +/*! @{ */ #define FLEXSPI_MCR0_SWRESET_MASK (0x1U) #define FLEXSPI_MCR0_SWRESET_SHIFT (0U) #define FLEXSPI_MCR0_SWRESET(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_SWRESET_SHIFT)) & FLEXSPI_MCR0_SWRESET_MASK) @@ -10425,24 +15952,54 @@ typedef struct { #define FLEXSPI_MCR0_MDIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_MDIS_SHIFT)) & FLEXSPI_MCR0_MDIS_MASK) #define FLEXSPI_MCR0_RXCLKSRC_MASK (0x30U) #define FLEXSPI_MCR0_RXCLKSRC_SHIFT (4U) +/*! RXCLKSRC - Sample Clock source selection for Flash Reading + * 0b00..Dummy Read strobe generated by FlexSPI Controller and loopback internally. + * 0b01..Dummy Read strobe generated by FlexSPI Controller and loopback from DQS pad. + * 0b10..Reserved + * 0b11..Flash provided Read strobe and input from DQS pad + */ #define FLEXSPI_MCR0_RXCLKSRC(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_RXCLKSRC_SHIFT)) & FLEXSPI_MCR0_RXCLKSRC_MASK) #define FLEXSPI_MCR0_ARDFEN_MASK (0x40U) #define FLEXSPI_MCR0_ARDFEN_SHIFT (6U) +/*! ARDFEN - Enable AHB bus Read Access to IP RX FIFO. + * 0b0..IP RX FIFO should be read by IP Bus. AHB Bus read access to IP RX FIFO memory space will get bus error response. + * 0b1..IP RX FIFO should be read by AHB Bus. IP Bus read access to IP RX FIFO memory space will always return data zero but no bus error response. + */ #define FLEXSPI_MCR0_ARDFEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_ARDFEN_SHIFT)) & FLEXSPI_MCR0_ARDFEN_MASK) #define FLEXSPI_MCR0_ATDFEN_MASK (0x80U) #define FLEXSPI_MCR0_ATDFEN_SHIFT (7U) +/*! ATDFEN - Enable AHB bus Write Access to IP TX FIFO. + * 0b0..IP TX FIFO should be written by IP Bus. AHB Bus write access to IP TX FIFO memory space will get bus error response. + * 0b1..IP TX FIFO should be written by AHB Bus. IP Bus write access to IP TX FIFO memory space will be ignored but no bus error response. + */ #define FLEXSPI_MCR0_ATDFEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_ATDFEN_SHIFT)) & FLEXSPI_MCR0_ATDFEN_MASK) #define FLEXSPI_MCR0_HSEN_MASK (0x800U) #define FLEXSPI_MCR0_HSEN_SHIFT (11U) +/*! HSEN - Half Speed Serial Flash access Enable. + * 0b0..Disable divide by 2 of serial flash clock for half speed commands. + * 0b1..Enable divide by 2 of serial flash clock for half speed commands. + */ #define FLEXSPI_MCR0_HSEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_HSEN_SHIFT)) & FLEXSPI_MCR0_HSEN_MASK) #define FLEXSPI_MCR0_DOZEEN_MASK (0x1000U) #define FLEXSPI_MCR0_DOZEEN_SHIFT (12U) +/*! DOZEEN - Doze mode enable bit + * 0b0..Doze mode support disabled. AHB clock and serial clock will not be gated off when there is doze mode request from system. + * 0b1..Doze mode support enabled. AHB clock and serial clock will be gated off when there is doze mode request from system. + */ #define FLEXSPI_MCR0_DOZEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_DOZEEN_SHIFT)) & FLEXSPI_MCR0_DOZEEN_MASK) #define FLEXSPI_MCR0_COMBINATIONEN_MASK (0x2000U) #define FLEXSPI_MCR0_COMBINATIONEN_SHIFT (13U) +/*! COMBINATIONEN - This bit is to support Flash Octal mode access by combining Port A and B Data pins (SIOA[3:0] and SIOB[3:0]). + * 0b0..Disable. + * 0b1..Enable. + */ #define FLEXSPI_MCR0_COMBINATIONEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_COMBINATIONEN_SHIFT)) & FLEXSPI_MCR0_COMBINATIONEN_MASK) #define FLEXSPI_MCR0_SCKFREERUNEN_MASK (0x4000U) #define FLEXSPI_MCR0_SCKFREERUNEN_SHIFT (14U) +/*! SCKFREERUNEN - This bit is used to force SCK output free-running. For FPGA applications, external device may use SCK clock as reference clock to its internal PLL. If SCK free-running is enabled, data sampling with loopback clock from SCK pad is not supported (MCR0[RXCLKSRC]=2). + * 0b0..Disable. + * 0b1..Enable. + */ #define FLEXSPI_MCR0_SCKFREERUNEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_SCKFREERUNEN_SHIFT)) & FLEXSPI_MCR0_SCKFREERUNEN_MASK) #define FLEXSPI_MCR0_IPGRANTWAIT_MASK (0xFF0000U) #define FLEXSPI_MCR0_IPGRANTWAIT_SHIFT (16U) @@ -10450,50 +16007,86 @@ typedef struct { #define FLEXSPI_MCR0_AHBGRANTWAIT_MASK (0xFF000000U) #define FLEXSPI_MCR0_AHBGRANTWAIT_SHIFT (24U) #define FLEXSPI_MCR0_AHBGRANTWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_AHBGRANTWAIT_SHIFT)) & FLEXSPI_MCR0_AHBGRANTWAIT_MASK) +/*! @} */ /*! @name MCR1 - Module Control Register 1 */ +/*! @{ */ #define FLEXSPI_MCR1_AHBBUSWAIT_MASK (0xFFFFU) #define FLEXSPI_MCR1_AHBBUSWAIT_SHIFT (0U) #define FLEXSPI_MCR1_AHBBUSWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR1_AHBBUSWAIT_SHIFT)) & FLEXSPI_MCR1_AHBBUSWAIT_MASK) #define FLEXSPI_MCR1_SEQWAIT_MASK (0xFFFF0000U) #define FLEXSPI_MCR1_SEQWAIT_SHIFT (16U) #define FLEXSPI_MCR1_SEQWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR1_SEQWAIT_SHIFT)) & FLEXSPI_MCR1_SEQWAIT_MASK) +/*! @} */ /*! @name MCR2 - Module Control Register 2 */ +/*! @{ */ #define FLEXSPI_MCR2_CLRAHBBUFOPT_MASK (0x800U) #define FLEXSPI_MCR2_CLRAHBBUFOPT_SHIFT (11U) +/*! CLRAHBBUFOPT - This bit determines whether AHB RX Buffer and AHB TX Buffer will be cleaned automaticaly when FlexSPI returns STOP mode ACK. Software should set this bit if AHB RX Buffer or AHB TX Buffer will be powered off in STOP mode. Otherwise AHB read access after exiting STOP mode may hit AHB RX Buffer or AHB TX Buffer but their data entries are invalid. + * 0b0..AHB RX/TX Buffer will not be cleaned automatically when FlexSPI return Stop mode ACK. + * 0b1..AHB RX/TX Buffer will be cleaned automatically when FlexSPI return Stop mode ACK. + */ #define FLEXSPI_MCR2_CLRAHBBUFOPT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_CLRAHBBUFOPT_SHIFT)) & FLEXSPI_MCR2_CLRAHBBUFOPT_MASK) #define FLEXSPI_MCR2_CLRLEARNPHASE_MASK (0x4000U) #define FLEXSPI_MCR2_CLRLEARNPHASE_SHIFT (14U) #define FLEXSPI_MCR2_CLRLEARNPHASE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_CLRLEARNPHASE_SHIFT)) & FLEXSPI_MCR2_CLRLEARNPHASE_MASK) #define FLEXSPI_MCR2_SAMEDEVICEEN_MASK (0x8000U) #define FLEXSPI_MCR2_SAMEDEVICEEN_SHIFT (15U) +/*! SAMEDEVICEEN - All external devices are same devices (both in types and size) for A1/A2/B1/B2. + * 0b0..In Individual mode, FLSHA1CRx/FLSHA2CRx/FLSHB1CRx/FLSHB2CRx register setting will be applied to Flash A1/A2/B1/B2 seperately. In Parallel mode, FLSHA1CRx register setting will be applied to Flash A1 and B1, FLSHA2CRx register setting will be applied to Flash A2 and B2. FLSHB1CRx/FLSHB2CRx register settings will be ignored. + * 0b1..FLSHA1CR0/FLSHA1CR1/FLSHA1CR2 register settings will be applied to Flash A1/A2/B1/B2. FLSHA2CRx/FLSHB1CRx/FLSHB2CRx will be ignored. + */ #define FLEXSPI_MCR2_SAMEDEVICEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_SAMEDEVICEEN_SHIFT)) & FLEXSPI_MCR2_SAMEDEVICEEN_MASK) #define FLEXSPI_MCR2_SCKBDIFFOPT_MASK (0x80000U) #define FLEXSPI_MCR2_SCKBDIFFOPT_SHIFT (19U) +/*! SCKBDIFFOPT - SCKB pad can be used as SCKA differential clock output (inverted clock to SCKA). In this case, port B flash access is not available. After change the value of this feild, MCR0[SWRESET] should be set. + * 0b1..SCKB pad is used as port A SCK inverted clock output (Differential clock to SCKA). Port B flash access is not available. + * 0b0..SCKB pad is used as port B SCK clock output. Port B flash access is available. + */ #define FLEXSPI_MCR2_SCKBDIFFOPT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_SCKBDIFFOPT_SHIFT)) & FLEXSPI_MCR2_SCKBDIFFOPT_MASK) #define FLEXSPI_MCR2_RESUMEWAIT_MASK (0xFF000000U) #define FLEXSPI_MCR2_RESUMEWAIT_SHIFT (24U) #define FLEXSPI_MCR2_RESUMEWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_RESUMEWAIT_SHIFT)) & FLEXSPI_MCR2_RESUMEWAIT_MASK) +/*! @} */ /*! @name AHBCR - AHB Bus Control Register */ +/*! @{ */ #define FLEXSPI_AHBCR_APAREN_MASK (0x1U) #define FLEXSPI_AHBCR_APAREN_SHIFT (0U) +/*! APAREN - Parallel mode enabled for AHB triggered Command (both read and write) . + * 0b0..Flash will be accessed in Individual mode. + * 0b1..Flash will be accessed in Parallel mode. + */ #define FLEXSPI_AHBCR_APAREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_APAREN_SHIFT)) & FLEXSPI_AHBCR_APAREN_MASK) #define FLEXSPI_AHBCR_CACHABLEEN_MASK (0x8U) #define FLEXSPI_AHBCR_CACHABLEEN_SHIFT (3U) +/*! CACHABLEEN - Enable AHB bus cachable read access support. + * 0b0..Disabled. When there is AHB bus cachable read access, FlexSPI will not check whether it hit AHB TX Buffer. + * 0b1..Enabled. When there is AHB bus cachable read access, FlexSPI will check whether it hit AHB TX Buffer first. + */ #define FLEXSPI_AHBCR_CACHABLEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_CACHABLEEN_SHIFT)) & FLEXSPI_AHBCR_CACHABLEEN_MASK) #define FLEXSPI_AHBCR_BUFFERABLEEN_MASK (0x10U) #define FLEXSPI_AHBCR_BUFFERABLEEN_SHIFT (4U) +/*! BUFFERABLEEN - Enable AHB bus bufferable write access support. This field affects the last beat of AHB write access, refer for more details about AHB bufferable write. + * 0b0..Disabled. For all AHB write access (no matter bufferable or non-bufferable ), FlexSPI will return AHB Bus ready after all data is transmitted to External device and AHB command finished. + * 0b1..Enabled. For AHB bufferable write access, FlexSPI will return AHB Bus ready when the AHB command is granted by arbitrator and will not wait for AHB command finished. + */ #define FLEXSPI_AHBCR_BUFFERABLEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_BUFFERABLEEN_SHIFT)) & FLEXSPI_AHBCR_BUFFERABLEEN_MASK) #define FLEXSPI_AHBCR_PREFETCHEN_MASK (0x20U) #define FLEXSPI_AHBCR_PREFETCHEN_SHIFT (5U) #define FLEXSPI_AHBCR_PREFETCHEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_PREFETCHEN_SHIFT)) & FLEXSPI_AHBCR_PREFETCHEN_MASK) #define FLEXSPI_AHBCR_READADDROPT_MASK (0x40U) #define FLEXSPI_AHBCR_READADDROPT_SHIFT (6U) +/*! READADDROPT - AHB Read Address option bit. This option bit is intend to remove AHB burst start address alignment limitation. + * 0b0..There is AHB read burst start address alignment limitation when flash is accessed in parallel mode or flash is wordaddressable. + * 0b1..There is no AHB read burst start address alignment limitation. FlexSPI will fetch more datas than AHB burst required to meet the alignment requirement. + */ #define FLEXSPI_AHBCR_READADDROPT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_READADDROPT_SHIFT)) & FLEXSPI_AHBCR_READADDROPT_MASK) +/*! @} */ /*! @name INTEN - Interrupt Enable Register */ +/*! @{ */ #define FLEXSPI_INTEN_IPCMDDONEEN_MASK (0x1U) #define FLEXSPI_INTEN_IPCMDDONEEN_SHIFT (0U) #define FLEXSPI_INTEN_IPCMDDONEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPCMDDONEEN_SHIFT)) & FLEXSPI_INTEN_IPCMDDONEEN_MASK) @@ -10527,8 +16120,10 @@ typedef struct { #define FLEXSPI_INTEN_SEQTIMEOUTEN_MASK (0x800U) #define FLEXSPI_INTEN_SEQTIMEOUTEN_SHIFT (11U) #define FLEXSPI_INTEN_SEQTIMEOUTEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_SEQTIMEOUTEN_SHIFT)) & FLEXSPI_INTEN_SEQTIMEOUTEN_MASK) +/*! @} */ /*! @name INTR - Interrupt Register */ +/*! @{ */ #define FLEXSPI_INTR_IPCMDDONE_MASK (0x1U) #define FLEXSPI_INTR_IPCMDDONE_SHIFT (0U) #define FLEXSPI_INTR_IPCMDDONE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPCMDDONE_SHIFT)) & FLEXSPI_INTR_IPCMDDONE_MASK) @@ -10562,21 +16157,27 @@ typedef struct { #define FLEXSPI_INTR_SEQTIMEOUT_MASK (0x800U) #define FLEXSPI_INTR_SEQTIMEOUT_SHIFT (11U) #define FLEXSPI_INTR_SEQTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_SEQTIMEOUT_SHIFT)) & FLEXSPI_INTR_SEQTIMEOUT_MASK) +/*! @} */ /*! @name LUTKEY - LUT Key Register */ +/*! @{ */ #define FLEXSPI_LUTKEY_KEY_MASK (0xFFFFFFFFU) #define FLEXSPI_LUTKEY_KEY_SHIFT (0U) #define FLEXSPI_LUTKEY_KEY(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUTKEY_KEY_SHIFT)) & FLEXSPI_LUTKEY_KEY_MASK) +/*! @} */ /*! @name LUTCR - LUT Control Register */ +/*! @{ */ #define FLEXSPI_LUTCR_LOCK_MASK (0x1U) #define FLEXSPI_LUTCR_LOCK_SHIFT (0U) #define FLEXSPI_LUTCR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUTCR_LOCK_SHIFT)) & FLEXSPI_LUTCR_LOCK_MASK) #define FLEXSPI_LUTCR_UNLOCK_MASK (0x2U) #define FLEXSPI_LUTCR_UNLOCK_SHIFT (1U) #define FLEXSPI_LUTCR_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUTCR_UNLOCK_SHIFT)) & FLEXSPI_LUTCR_UNLOCK_MASK) +/*! @} */ /*! @name AHBRXBUFCR0 - AHB RX Buffer 0 Control Register 0..AHB RX Buffer 3 Control Register 0 */ +/*! @{ */ #define FLEXSPI_AHBRXBUFCR0_BUFSZ_MASK (0xFFU) #define FLEXSPI_AHBRXBUFCR0_BUFSZ_SHIFT (0U) #define FLEXSPI_AHBRXBUFCR0_BUFSZ(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_BUFSZ_SHIFT)) & FLEXSPI_AHBRXBUFCR0_BUFSZ_MASK) @@ -10586,19 +16187,26 @@ typedef struct { #define FLEXSPI_AHBRXBUFCR0_PRIORITY_MASK (0x3000000U) #define FLEXSPI_AHBRXBUFCR0_PRIORITY_SHIFT (24U) #define FLEXSPI_AHBRXBUFCR0_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_PRIORITY_SHIFT)) & FLEXSPI_AHBRXBUFCR0_PRIORITY_MASK) +#define FLEXSPI_AHBRXBUFCR0_PREFETCHEN_MASK (0x80000000U) +#define FLEXSPI_AHBRXBUFCR0_PREFETCHEN_SHIFT (31U) +#define FLEXSPI_AHBRXBUFCR0_PREFETCHEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_PREFETCHEN_SHIFT)) & FLEXSPI_AHBRXBUFCR0_PREFETCHEN_MASK) +/*! @} */ /* The count of FLEXSPI_AHBRXBUFCR0 */ #define FLEXSPI_AHBRXBUFCR0_COUNT (4U) /*! @name FLSHCR0 - Flash A1 Control Register 0..Flash B2 Control Register 0 */ +/*! @{ */ #define FLEXSPI_FLSHCR0_FLSHSZ_MASK (0x7FFFFFU) #define FLEXSPI_FLSHCR0_FLSHSZ_SHIFT (0U) #define FLEXSPI_FLSHCR0_FLSHSZ(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR0_FLSHSZ_SHIFT)) & FLEXSPI_FLSHCR0_FLSHSZ_MASK) +/*! @} */ /* The count of FLEXSPI_FLSHCR0 */ #define FLEXSPI_FLSHCR0_COUNT (4U) /*! @name FLSHCR1 - Flash A1 Control Register 1..Flash B2 Control Register 1 */ +/*! @{ */ #define FLEXSPI_FLSHCR1_TCSS_MASK (0x1FU) #define FLEXSPI_FLSHCR1_TCSS_SHIFT (0U) #define FLEXSPI_FLSHCR1_TCSS(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_TCSS_SHIFT)) & FLEXSPI_FLSHCR1_TCSS_MASK) @@ -10613,15 +16221,21 @@ typedef struct { #define FLEXSPI_FLSHCR1_CAS(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_CAS_SHIFT)) & FLEXSPI_FLSHCR1_CAS_MASK) #define FLEXSPI_FLSHCR1_CSINTERVALUNIT_MASK (0x8000U) #define FLEXSPI_FLSHCR1_CSINTERVALUNIT_SHIFT (15U) +/*! CSINTERVALUNIT - CS interval unit + * 0b0..The CS interval unit is 1 serial clock cycle + * 0b1..The CS interval unit is 256 serial clock cycle + */ #define FLEXSPI_FLSHCR1_CSINTERVALUNIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_CSINTERVALUNIT_SHIFT)) & FLEXSPI_FLSHCR1_CSINTERVALUNIT_MASK) #define FLEXSPI_FLSHCR1_CSINTERVAL_MASK (0xFFFF0000U) #define FLEXSPI_FLSHCR1_CSINTERVAL_SHIFT (16U) #define FLEXSPI_FLSHCR1_CSINTERVAL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_CSINTERVAL_SHIFT)) & FLEXSPI_FLSHCR1_CSINTERVAL_MASK) +/*! @} */ /* The count of FLEXSPI_FLSHCR1 */ #define FLEXSPI_FLSHCR1_COUNT (4U) /*! @name FLSHCR2 - Flash A1 Control Register 2..Flash B2 Control Register 2 */ +/*! @{ */ #define FLEXSPI_FLSHCR2_ARDSEQID_MASK (0xFU) #define FLEXSPI_FLSHCR2_ARDSEQID_SHIFT (0U) #define FLEXSPI_FLSHCR2_ARDSEQID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_ARDSEQID_SHIFT)) & FLEXSPI_FLSHCR2_ARDSEQID_MASK) @@ -10639,31 +16253,59 @@ typedef struct { #define FLEXSPI_FLSHCR2_AWRWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRWAIT_SHIFT)) & FLEXSPI_FLSHCR2_AWRWAIT_MASK) #define FLEXSPI_FLSHCR2_AWRWAITUNIT_MASK (0x70000000U) #define FLEXSPI_FLSHCR2_AWRWAITUNIT_SHIFT (28U) +/*! AWRWAITUNIT - AWRWAIT unit + * 0b000..The AWRWAIT unit is 2 ahb clock cycle + * 0b001..The AWRWAIT unit is 8 ahb clock cycle + * 0b010..The AWRWAIT unit is 32 ahb clock cycle + * 0b011..The AWRWAIT unit is 128 ahb clock cycle + * 0b100..The AWRWAIT unit is 512 ahb clock cycle + * 0b101..The AWRWAIT unit is 2048 ahb clock cycle + * 0b110..The AWRWAIT unit is 8192 ahb clock cycle + * 0b111..The AWRWAIT unit is 32768 ahb clock cycle + */ #define FLEXSPI_FLSHCR2_AWRWAITUNIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRWAITUNIT_SHIFT)) & FLEXSPI_FLSHCR2_AWRWAITUNIT_MASK) #define FLEXSPI_FLSHCR2_CLRINSTRPTR_MASK (0x80000000U) #define FLEXSPI_FLSHCR2_CLRINSTRPTR_SHIFT (31U) #define FLEXSPI_FLSHCR2_CLRINSTRPTR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_CLRINSTRPTR_SHIFT)) & FLEXSPI_FLSHCR2_CLRINSTRPTR_MASK) +/*! @} */ /* The count of FLEXSPI_FLSHCR2 */ #define FLEXSPI_FLSHCR2_COUNT (4U) /*! @name FLSHCR4 - Flash Control Register 4 */ +/*! @{ */ #define FLEXSPI_FLSHCR4_WMOPT1_MASK (0x1U) #define FLEXSPI_FLSHCR4_WMOPT1_SHIFT (0U) +/*! WMOPT1 - Write mask option bit 1. This option bit could be used to remove AHB write burst start address alignment limitation. + * 0b0..DQS pin will be used as Write Mask when writing to external device. There is no limitation on AHB write burst start address alignment when flash is accessed in individual mode. + * 0b1..DQS pin will not be used as Write Mask when writing to external device. There is limitation on AHB write burst start address alignment when flash is accessed in individual mode. + */ #define FLEXSPI_FLSHCR4_WMOPT1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR4_WMOPT1_SHIFT)) & FLEXSPI_FLSHCR4_WMOPT1_MASK) #define FLEXSPI_FLSHCR4_WMENA_MASK (0x4U) #define FLEXSPI_FLSHCR4_WMENA_SHIFT (2U) +/*! WMENA - Write mask enable bit for flash device on port A. When write mask function is needed for memory device on port A, this bit must be set. + * 0b0..Write mask is disabled, DQS(RWDS) pin will be un-driven when writing to external device. + * 0b1..Write mask is enabled, DQS(RWDS) pin will be driven by FlexSPI as write mask output when writing to external device. + */ #define FLEXSPI_FLSHCR4_WMENA(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR4_WMENA_SHIFT)) & FLEXSPI_FLSHCR4_WMENA_MASK) #define FLEXSPI_FLSHCR4_WMENB_MASK (0x8U) #define FLEXSPI_FLSHCR4_WMENB_SHIFT (3U) +/*! WMENB - Write mask enable bit for flash device on port B. When write mask function is needed for memory device on port B, this bit must be set. + * 0b0..Write mask is disabled, DQS(RWDS) pin will be un-driven when writing to external device. + * 0b1..Write mask is enabled, DQS(RWDS) pin will be driven by FlexSPI as write mask output when writing to external device. + */ #define FLEXSPI_FLSHCR4_WMENB(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR4_WMENB_SHIFT)) & FLEXSPI_FLSHCR4_WMENB_MASK) +/*! @} */ /*! @name IPCR0 - IP Control Register 0 */ +/*! @{ */ #define FLEXSPI_IPCR0_SFAR_MASK (0xFFFFFFFFU) #define FLEXSPI_IPCR0_SFAR_SHIFT (0U) #define FLEXSPI_IPCR0_SFAR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR0_SFAR_SHIFT)) & FLEXSPI_IPCR0_SFAR_MASK) +/*! @} */ /*! @name IPCR1 - IP Control Register 1 */ +/*! @{ */ #define FLEXSPI_IPCR1_IDATSZ_MASK (0xFFFFU) #define FLEXSPI_IPCR1_IDATSZ_SHIFT (0U) #define FLEXSPI_IPCR1_IDATSZ(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_IDATSZ_SHIFT)) & FLEXSPI_IPCR1_IDATSZ_MASK) @@ -10675,36 +16317,56 @@ typedef struct { #define FLEXSPI_IPCR1_ISEQNUM(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_ISEQNUM_SHIFT)) & FLEXSPI_IPCR1_ISEQNUM_MASK) #define FLEXSPI_IPCR1_IPAREN_MASK (0x80000000U) #define FLEXSPI_IPCR1_IPAREN_SHIFT (31U) +/*! IPAREN - Parallel mode Enabled for IP command. + * 0b0..Flash will be accessed in Individual mode. + * 0b1..Flash will be accessed in Parallel mode. + */ #define FLEXSPI_IPCR1_IPAREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_IPAREN_SHIFT)) & FLEXSPI_IPCR1_IPAREN_MASK) +/*! @} */ /*! @name IPCMD - IP Command Register */ +/*! @{ */ #define FLEXSPI_IPCMD_TRG_MASK (0x1U) #define FLEXSPI_IPCMD_TRG_SHIFT (0U) #define FLEXSPI_IPCMD_TRG(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCMD_TRG_SHIFT)) & FLEXSPI_IPCMD_TRG_MASK) +/*! @} */ /*! @name IPRXFCR - IP RX FIFO Control Register */ +/*! @{ */ #define FLEXSPI_IPRXFCR_CLRIPRXF_MASK (0x1U) #define FLEXSPI_IPRXFCR_CLRIPRXF_SHIFT (0U) #define FLEXSPI_IPRXFCR_CLRIPRXF(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFCR_CLRIPRXF_SHIFT)) & FLEXSPI_IPRXFCR_CLRIPRXF_MASK) #define FLEXSPI_IPRXFCR_RXDMAEN_MASK (0x2U) #define FLEXSPI_IPRXFCR_RXDMAEN_SHIFT (1U) +/*! RXDMAEN - IP RX FIFO reading by DMA enabled. + * 0b0..IP RX FIFO would be read by processor. + * 0b1..IP RX FIFO would be read by DMA. + */ #define FLEXSPI_IPRXFCR_RXDMAEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFCR_RXDMAEN_SHIFT)) & FLEXSPI_IPRXFCR_RXDMAEN_MASK) #define FLEXSPI_IPRXFCR_RXWMRK_MASK (0x3CU) #define FLEXSPI_IPRXFCR_RXWMRK_SHIFT (2U) #define FLEXSPI_IPRXFCR_RXWMRK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFCR_RXWMRK_SHIFT)) & FLEXSPI_IPRXFCR_RXWMRK_MASK) +/*! @} */ /*! @name IPTXFCR - IP TX FIFO Control Register */ +/*! @{ */ #define FLEXSPI_IPTXFCR_CLRIPTXF_MASK (0x1U) #define FLEXSPI_IPTXFCR_CLRIPTXF_SHIFT (0U) #define FLEXSPI_IPTXFCR_CLRIPTXF(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFCR_CLRIPTXF_SHIFT)) & FLEXSPI_IPTXFCR_CLRIPTXF_MASK) #define FLEXSPI_IPTXFCR_TXDMAEN_MASK (0x2U) #define FLEXSPI_IPTXFCR_TXDMAEN_SHIFT (1U) +/*! TXDMAEN - IP TX FIFO filling by DMA enabled. + * 0b0..IP TX FIFO would be filled by processor. + * 0b1..IP TX FIFO would be filled by DMA. + */ #define FLEXSPI_IPTXFCR_TXDMAEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFCR_TXDMAEN_SHIFT)) & FLEXSPI_IPTXFCR_TXDMAEN_MASK) #define FLEXSPI_IPTXFCR_TXWMRK_MASK (0x3CU) #define FLEXSPI_IPTXFCR_TXWMRK_SHIFT (2U) #define FLEXSPI_IPTXFCR_TXWMRK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFCR_TXWMRK_SHIFT)) & FLEXSPI_IPTXFCR_TXWMRK_MASK) +/*! @} */ /*! @name DLLCR - DLL Control Register 0 */ +/*! @{ */ #define FLEXSPI_DLLCR_DLLEN_MASK (0x1U) #define FLEXSPI_DLLCR_DLLEN_SHIFT (0U) #define FLEXSPI_DLLCR_DLLEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_DLLEN_SHIFT)) & FLEXSPI_DLLCR_DLLEN_MASK) @@ -10720,11 +16382,13 @@ typedef struct { #define FLEXSPI_DLLCR_OVRDVAL_MASK (0x7E00U) #define FLEXSPI_DLLCR_OVRDVAL_SHIFT (9U) #define FLEXSPI_DLLCR_OVRDVAL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_OVRDVAL_SHIFT)) & FLEXSPI_DLLCR_OVRDVAL_MASK) +/*! @} */ /* The count of FLEXSPI_DLLCR */ #define FLEXSPI_DLLCR_COUNT (2U) /*! @name STS0 - Status Register 0 */ +/*! @{ */ #define FLEXSPI_STS0_SEQIDLE_MASK (0x1U) #define FLEXSPI_STS0_SEQIDLE_SHIFT (0U) #define FLEXSPI_STS0_SEQIDLE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS0_SEQIDLE_SHIFT)) & FLEXSPI_STS0_SEQIDLE_MASK) @@ -10733,23 +16397,51 @@ typedef struct { #define FLEXSPI_STS0_ARBIDLE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS0_ARBIDLE_SHIFT)) & FLEXSPI_STS0_ARBIDLE_MASK) #define FLEXSPI_STS0_ARBCMDSRC_MASK (0xCU) #define FLEXSPI_STS0_ARBCMDSRC_SHIFT (2U) +/*! ARBCMDSRC - This status field indicates the trigger source of current command sequence granted by arbitrator. This field value is meaningless when ARB_CTL is not busy (STS0[ARBIDLE]=0x1). + * 0b00..Triggered by AHB read command (triggered by AHB read). + * 0b01..Triggered by AHB write command (triggered by AHB Write). + * 0b10..Triggered by IP command (triggered by setting register bit IPCMD.TRG). + * 0b11..Triggered by suspended command (resumed). + */ #define FLEXSPI_STS0_ARBCMDSRC(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS0_ARBCMDSRC_SHIFT)) & FLEXSPI_STS0_ARBCMDSRC_MASK) +/*! @} */ /*! @name STS1 - Status Register 1 */ +/*! @{ */ #define FLEXSPI_STS1_AHBCMDERRID_MASK (0xFU) #define FLEXSPI_STS1_AHBCMDERRID_SHIFT (0U) #define FLEXSPI_STS1_AHBCMDERRID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_AHBCMDERRID_SHIFT)) & FLEXSPI_STS1_AHBCMDERRID_MASK) #define FLEXSPI_STS1_AHBCMDERRCODE_MASK (0xF00U) #define FLEXSPI_STS1_AHBCMDERRCODE_SHIFT (8U) +/*! AHBCMDERRCODE - Indicates the Error Code when AHB command Error detected. This field will be cleared when INTR[AHBCMDERR] is write-1-clear(w1c). + * 0b0000..No error. + * 0b0010..AHB Write command with JMP_ON_CS instruction used in the sequence. + * 0b0011..There is unknown instruction opcode in the sequence. + * 0b0100..Instruction DUMMY_SDR/DUMMY_RWDS_SDR used in DDR sequence. + * 0b0101..Instruction DUMMY_DDR/DUMMY_RWDS_DDR used in SDR sequence. + * 0b1110..Sequence execution timeout. + */ #define FLEXSPI_STS1_AHBCMDERRCODE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_AHBCMDERRCODE_SHIFT)) & FLEXSPI_STS1_AHBCMDERRCODE_MASK) #define FLEXSPI_STS1_IPCMDERRID_MASK (0xF0000U) #define FLEXSPI_STS1_IPCMDERRID_SHIFT (16U) #define FLEXSPI_STS1_IPCMDERRID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_IPCMDERRID_SHIFT)) & FLEXSPI_STS1_IPCMDERRID_MASK) #define FLEXSPI_STS1_IPCMDERRCODE_MASK (0xF000000U) #define FLEXSPI_STS1_IPCMDERRCODE_SHIFT (24U) +/*! IPCMDERRCODE - Indicates the Error Code when IP command Error detected. This field will be cleared when INTR[IPCMDERR] is write-1-clear(w1c). + * 0b0000..No error. + * 0b0010..IP command with JMP_ON_CS instruction used in the sequence. + * 0b0011..There is unknown instruction opcode in the sequence. + * 0b0100..Instruction DUMMY_SDR/DUMMY_RWDS_SDR used in DDR sequence. + * 0b0101..Instruction DUMMY_DDR/DUMMY_RWDS_DDR used in SDR sequence. + * 0b0110..Flash access start address exceed the whole flash address range (A1/A2/B1/B2). + * 0b1110..Sequence execution timeout. + * 0b1111..Flash boundary crossed. + */ #define FLEXSPI_STS1_IPCMDERRCODE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_IPCMDERRCODE_SHIFT)) & FLEXSPI_STS1_IPCMDERRCODE_MASK) +/*! @} */ /*! @name STS2 - Status Register 2 */ +/*! @{ */ #define FLEXSPI_STS2_ASLVLOCK_MASK (0x1U) #define FLEXSPI_STS2_ASLVLOCK_SHIFT (0U) #define FLEXSPI_STS2_ASLVLOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_ASLVLOCK_SHIFT)) & FLEXSPI_STS2_ASLVLOCK_MASK) @@ -10774,8 +16466,10 @@ typedef struct { #define FLEXSPI_STS2_BREFSEL_MASK (0x3F000000U) #define FLEXSPI_STS2_BREFSEL_SHIFT (24U) #define FLEXSPI_STS2_BREFSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_BREFSEL_SHIFT)) & FLEXSPI_STS2_BREFSEL_MASK) +/*! @} */ /*! @name AHBSPNDSTS - AHB Suspend Status Register */ +/*! @{ */ #define FLEXSPI_AHBSPNDSTS_ACTIVE_MASK (0x1U) #define FLEXSPI_AHBSPNDSTS_ACTIVE_SHIFT (0U) #define FLEXSPI_AHBSPNDSTS_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBSPNDSTS_ACTIVE_SHIFT)) & FLEXSPI_AHBSPNDSTS_ACTIVE_MASK) @@ -10785,40 +16479,50 @@ typedef struct { #define FLEXSPI_AHBSPNDSTS_DATLFT_MASK (0xFFFF0000U) #define FLEXSPI_AHBSPNDSTS_DATLFT_SHIFT (16U) #define FLEXSPI_AHBSPNDSTS_DATLFT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBSPNDSTS_DATLFT_SHIFT)) & FLEXSPI_AHBSPNDSTS_DATLFT_MASK) +/*! @} */ /*! @name IPRXFSTS - IP RX FIFO Status Register */ +/*! @{ */ #define FLEXSPI_IPRXFSTS_FILL_MASK (0xFFU) #define FLEXSPI_IPRXFSTS_FILL_SHIFT (0U) #define FLEXSPI_IPRXFSTS_FILL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFSTS_FILL_SHIFT)) & FLEXSPI_IPRXFSTS_FILL_MASK) #define FLEXSPI_IPRXFSTS_RDCNTR_MASK (0xFFFF0000U) #define FLEXSPI_IPRXFSTS_RDCNTR_SHIFT (16U) #define FLEXSPI_IPRXFSTS_RDCNTR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFSTS_RDCNTR_SHIFT)) & FLEXSPI_IPRXFSTS_RDCNTR_MASK) +/*! @} */ /*! @name IPTXFSTS - IP TX FIFO Status Register */ +/*! @{ */ #define FLEXSPI_IPTXFSTS_FILL_MASK (0xFFU) #define FLEXSPI_IPTXFSTS_FILL_SHIFT (0U) #define FLEXSPI_IPTXFSTS_FILL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFSTS_FILL_SHIFT)) & FLEXSPI_IPTXFSTS_FILL_MASK) #define FLEXSPI_IPTXFSTS_WRCNTR_MASK (0xFFFF0000U) #define FLEXSPI_IPTXFSTS_WRCNTR_SHIFT (16U) #define FLEXSPI_IPTXFSTS_WRCNTR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFSTS_WRCNTR_SHIFT)) & FLEXSPI_IPTXFSTS_WRCNTR_MASK) +/*! @} */ /*! @name RFDR - IP RX FIFO Data Register 0..IP RX FIFO Data Register 31 */ +/*! @{ */ #define FLEXSPI_RFDR_RXDATA_MASK (0xFFFFFFFFU) #define FLEXSPI_RFDR_RXDATA_SHIFT (0U) #define FLEXSPI_RFDR_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_RFDR_RXDATA_SHIFT)) & FLEXSPI_RFDR_RXDATA_MASK) +/*! @} */ /* The count of FLEXSPI_RFDR */ #define FLEXSPI_RFDR_COUNT (32U) /*! @name TFDR - IP TX FIFO Data Register 0..IP TX FIFO Data Register 31 */ +/*! @{ */ #define FLEXSPI_TFDR_TXDATA_MASK (0xFFFFFFFFU) #define FLEXSPI_TFDR_TXDATA_SHIFT (0U) #define FLEXSPI_TFDR_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_TFDR_TXDATA_SHIFT)) & FLEXSPI_TFDR_TXDATA_MASK) +/*! @} */ /* The count of FLEXSPI_TFDR */ #define FLEXSPI_TFDR_COUNT (32U) /*! @name LUT - LUT 0..LUT 63 */ +/*! @{ */ #define FLEXSPI_LUT_OPERAND0_MASK (0xFFU) #define FLEXSPI_LUT_OPERAND0_SHIFT (0U) #define FLEXSPI_LUT_OPERAND0(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPERAND0_SHIFT)) & FLEXSPI_LUT_OPERAND0_MASK) @@ -10837,6 +16541,7 @@ typedef struct { #define FLEXSPI_LUT_OPCODE1_MASK (0xFC000000U) #define FLEXSPI_LUT_OPCODE1_SHIFT (26U) #define FLEXSPI_LUT_OPCODE1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPCODE1_SHIFT)) & FLEXSPI_LUT_OPCODE1_MASK) +/*! @} */ /* The count of FLEXSPI_LUT */ #define FLEXSPI_LUT_COUNT (64U) @@ -10903,17 +16608,32 @@ typedef struct { */ /*! @name CNTR - GPC Interface control register */ +/*! @{ */ #define GPC_CNTR_MEGA_PDN_REQ_MASK (0x4U) #define GPC_CNTR_MEGA_PDN_REQ_SHIFT (2U) +/*! MEGA_PDN_REQ + * 0b0..No Request + * 0b1..Request power down sequence + */ #define GPC_CNTR_MEGA_PDN_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_CNTR_MEGA_PDN_REQ_SHIFT)) & GPC_CNTR_MEGA_PDN_REQ_MASK) #define GPC_CNTR_MEGA_PUP_REQ_MASK (0x8U) #define GPC_CNTR_MEGA_PUP_REQ_SHIFT (3U) +/*! MEGA_PUP_REQ + * 0b0..No Request + * 0b1..Request power up sequence + */ #define GPC_CNTR_MEGA_PUP_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_CNTR_MEGA_PUP_REQ_SHIFT)) & GPC_CNTR_MEGA_PUP_REQ_MASK) #define GPC_CNTR_PDRAM0_PGE_MASK (0x400000U) #define GPC_CNTR_PDRAM0_PGE_SHIFT (22U) +/*! PDRAM0_PGE + * 0b1..FlexRAM PDRAM0 domain (bank1-7) will be power down once when CPU core is power down. + * 0b0..FlexRAM PDRAM0 domain (bank1-7) will keep power on even if CPU core is power down. + */ #define GPC_CNTR_PDRAM0_PGE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CNTR_PDRAM0_PGE_SHIFT)) & GPC_CNTR_PDRAM0_PGE_MASK) +/*! @} */ /*! @name IMR - IRQ masking register 1..IRQ masking register 4 */ +/*! @{ */ #define GPC_IMR_IMR1_MASK (0xFFFFFFFFU) #define GPC_IMR_IMR1_SHIFT (0U) #define GPC_IMR_IMR1(x) (((uint32_t)(((uint32_t)(x)) << GPC_IMR_IMR1_SHIFT)) & GPC_IMR_IMR1_MASK) @@ -10926,11 +16646,13 @@ typedef struct { #define GPC_IMR_IMR4_MASK (0xFFFFFFFFU) #define GPC_IMR_IMR4_SHIFT (0U) #define GPC_IMR_IMR4(x) (((uint32_t)(((uint32_t)(x)) << GPC_IMR_IMR4_SHIFT)) & GPC_IMR_IMR4_MASK) +/*! @} */ /* The count of GPC_IMR */ #define GPC_IMR_COUNT (4U) /*! @name ISR - IRQ status resister 1..IRQ status resister 4 */ +/*! @{ */ #define GPC_ISR_ISR1_MASK (0xFFFFFFFFU) #define GPC_ISR_ISR1_SHIFT (0U) #define GPC_ISR_ISR1(x) (((uint32_t)(((uint32_t)(x)) << GPC_ISR_ISR1_SHIFT)) & GPC_ISR_ISR1_MASK) @@ -10943,19 +16665,24 @@ typedef struct { #define GPC_ISR_ISR4_MASK (0xFFFFFFFFU) #define GPC_ISR_ISR4_SHIFT (0U) #define GPC_ISR_ISR4(x) (((uint32_t)(((uint32_t)(x)) << GPC_ISR_ISR4_SHIFT)) & GPC_ISR_ISR4_MASK) +/*! @} */ /* The count of GPC_ISR */ #define GPC_ISR_COUNT (4U) /*! @name IMR5 - IRQ masking register 5 */ +/*! @{ */ #define GPC_IMR5_IMR5_MASK (0xFFFFFFFFU) #define GPC_IMR5_IMR5_SHIFT (0U) #define GPC_IMR5_IMR5(x) (((uint32_t)(((uint32_t)(x)) << GPC_IMR5_IMR5_SHIFT)) & GPC_IMR5_IMR5_MASK) +/*! @} */ /*! @name ISR5 - IRQ status resister 5 */ +/*! @{ */ #define GPC_ISR5_ISR4_MASK (0xFFFFFFFFU) #define GPC_ISR5_ISR4_SHIFT (0U) #define GPC_ISR5_ISR4(x) (((uint32_t)(((uint32_t)(x)) << GPC_ISR5_ISR4_SHIFT)) & GPC_ISR5_ISR4_MASK) +/*! @} */ /*! @@ -10999,6 +16726,10 @@ typedef struct { __IO uint32_t IMR; /**< GPIO interrupt mask register, offset: 0x14 */ __IO uint32_t ISR; /**< GPIO interrupt status register, offset: 0x18 */ __IO uint32_t EDGE_SEL; /**< GPIO edge select register, offset: 0x1C */ + uint8_t RESERVED_0[100]; + __O uint32_t DR_SET; /**< GPIO data register SET, offset: 0x84 */ + __O uint32_t DR_CLEAR; /**< GPIO data register CLEAR, offset: 0x88 */ + __O uint32_t DR_TOGGLE; /**< GPIO data register TOGGLE, offset: 0x8C */ } GPIO_Type; /* ---------------------------------------------------------------------------- @@ -11011,134 +16742,363 @@ typedef struct { */ /*! @name DR - GPIO data register */ +/*! @{ */ #define GPIO_DR_DR_MASK (0xFFFFFFFFU) #define GPIO_DR_DR_SHIFT (0U) #define GPIO_DR_DR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DR_DR_SHIFT)) & GPIO_DR_DR_MASK) +/*! @} */ /*! @name GDIR - GPIO direction register */ +/*! @{ */ #define GPIO_GDIR_GDIR_MASK (0xFFFFFFFFU) #define GPIO_GDIR_GDIR_SHIFT (0U) #define GPIO_GDIR_GDIR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GDIR_GDIR_SHIFT)) & GPIO_GDIR_GDIR_MASK) +/*! @} */ /*! @name PSR - GPIO pad status register */ +/*! @{ */ #define GPIO_PSR_PSR_MASK (0xFFFFFFFFU) #define GPIO_PSR_PSR_SHIFT (0U) #define GPIO_PSR_PSR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSR_PSR_SHIFT)) & GPIO_PSR_PSR_MASK) +/*! @} */ /*! @name ICR1 - GPIO interrupt configuration register1 */ +/*! @{ */ #define GPIO_ICR1_ICR0_MASK (0x3U) #define GPIO_ICR1_ICR0_SHIFT (0U) +/*! ICR0 - ICR0 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ #define GPIO_ICR1_ICR0(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR0_SHIFT)) & GPIO_ICR1_ICR0_MASK) #define GPIO_ICR1_ICR1_MASK (0xCU) #define GPIO_ICR1_ICR1_SHIFT (2U) +/*! ICR1 - ICR1 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ #define GPIO_ICR1_ICR1(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR1_SHIFT)) & GPIO_ICR1_ICR1_MASK) #define GPIO_ICR1_ICR2_MASK (0x30U) #define GPIO_ICR1_ICR2_SHIFT (4U) +/*! ICR2 - ICR2 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ #define GPIO_ICR1_ICR2(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR2_SHIFT)) & GPIO_ICR1_ICR2_MASK) #define GPIO_ICR1_ICR3_MASK (0xC0U) #define GPIO_ICR1_ICR3_SHIFT (6U) +/*! ICR3 - ICR3 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ #define GPIO_ICR1_ICR3(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR3_SHIFT)) & GPIO_ICR1_ICR3_MASK) #define GPIO_ICR1_ICR4_MASK (0x300U) #define GPIO_ICR1_ICR4_SHIFT (8U) +/*! ICR4 - ICR4 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ #define GPIO_ICR1_ICR4(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR4_SHIFT)) & GPIO_ICR1_ICR4_MASK) #define GPIO_ICR1_ICR5_MASK (0xC00U) #define GPIO_ICR1_ICR5_SHIFT (10U) +/*! ICR5 - ICR5 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ #define GPIO_ICR1_ICR5(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR5_SHIFT)) & GPIO_ICR1_ICR5_MASK) #define GPIO_ICR1_ICR6_MASK (0x3000U) #define GPIO_ICR1_ICR6_SHIFT (12U) +/*! ICR6 - ICR6 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ #define GPIO_ICR1_ICR6(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR6_SHIFT)) & GPIO_ICR1_ICR6_MASK) #define GPIO_ICR1_ICR7_MASK (0xC000U) #define GPIO_ICR1_ICR7_SHIFT (14U) +/*! ICR7 - ICR7 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ #define GPIO_ICR1_ICR7(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR7_SHIFT)) & GPIO_ICR1_ICR7_MASK) #define GPIO_ICR1_ICR8_MASK (0x30000U) #define GPIO_ICR1_ICR8_SHIFT (16U) +/*! ICR8 - ICR8 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ #define GPIO_ICR1_ICR8(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR8_SHIFT)) & GPIO_ICR1_ICR8_MASK) #define GPIO_ICR1_ICR9_MASK (0xC0000U) #define GPIO_ICR1_ICR9_SHIFT (18U) +/*! ICR9 - ICR9 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ #define GPIO_ICR1_ICR9(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR9_SHIFT)) & GPIO_ICR1_ICR9_MASK) #define GPIO_ICR1_ICR10_MASK (0x300000U) #define GPIO_ICR1_ICR10_SHIFT (20U) +/*! ICR10 - ICR10 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ #define GPIO_ICR1_ICR10(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR10_SHIFT)) & GPIO_ICR1_ICR10_MASK) #define GPIO_ICR1_ICR11_MASK (0xC00000U) #define GPIO_ICR1_ICR11_SHIFT (22U) +/*! ICR11 - ICR11 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ #define GPIO_ICR1_ICR11(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR11_SHIFT)) & GPIO_ICR1_ICR11_MASK) #define GPIO_ICR1_ICR12_MASK (0x3000000U) #define GPIO_ICR1_ICR12_SHIFT (24U) +/*! ICR12 - ICR12 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ #define GPIO_ICR1_ICR12(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR12_SHIFT)) & GPIO_ICR1_ICR12_MASK) #define GPIO_ICR1_ICR13_MASK (0xC000000U) #define GPIO_ICR1_ICR13_SHIFT (26U) +/*! ICR13 - ICR13 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ #define GPIO_ICR1_ICR13(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR13_SHIFT)) & GPIO_ICR1_ICR13_MASK) #define GPIO_ICR1_ICR14_MASK (0x30000000U) #define GPIO_ICR1_ICR14_SHIFT (28U) +/*! ICR14 - ICR14 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ #define GPIO_ICR1_ICR14(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR14_SHIFT)) & GPIO_ICR1_ICR14_MASK) #define GPIO_ICR1_ICR15_MASK (0xC0000000U) #define GPIO_ICR1_ICR15_SHIFT (30U) +/*! ICR15 - ICR15 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ #define GPIO_ICR1_ICR15(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR15_SHIFT)) & GPIO_ICR1_ICR15_MASK) +/*! @} */ /*! @name ICR2 - GPIO interrupt configuration register2 */ +/*! @{ */ #define GPIO_ICR2_ICR16_MASK (0x3U) #define GPIO_ICR2_ICR16_SHIFT (0U) +/*! ICR16 - ICR16 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ #define GPIO_ICR2_ICR16(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR16_SHIFT)) & GPIO_ICR2_ICR16_MASK) #define GPIO_ICR2_ICR17_MASK (0xCU) #define GPIO_ICR2_ICR17_SHIFT (2U) +/*! ICR17 - ICR17 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ #define GPIO_ICR2_ICR17(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR17_SHIFT)) & GPIO_ICR2_ICR17_MASK) #define GPIO_ICR2_ICR18_MASK (0x30U) #define GPIO_ICR2_ICR18_SHIFT (4U) +/*! ICR18 - ICR18 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ #define GPIO_ICR2_ICR18(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR18_SHIFT)) & GPIO_ICR2_ICR18_MASK) #define GPIO_ICR2_ICR19_MASK (0xC0U) #define GPIO_ICR2_ICR19_SHIFT (6U) +/*! ICR19 - ICR19 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ #define GPIO_ICR2_ICR19(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR19_SHIFT)) & GPIO_ICR2_ICR19_MASK) #define GPIO_ICR2_ICR20_MASK (0x300U) #define GPIO_ICR2_ICR20_SHIFT (8U) +/*! ICR20 - ICR20 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ #define GPIO_ICR2_ICR20(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR20_SHIFT)) & GPIO_ICR2_ICR20_MASK) #define GPIO_ICR2_ICR21_MASK (0xC00U) #define GPIO_ICR2_ICR21_SHIFT (10U) +/*! ICR21 - ICR21 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ #define GPIO_ICR2_ICR21(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR21_SHIFT)) & GPIO_ICR2_ICR21_MASK) #define GPIO_ICR2_ICR22_MASK (0x3000U) #define GPIO_ICR2_ICR22_SHIFT (12U) +/*! ICR22 - ICR22 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ #define GPIO_ICR2_ICR22(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR22_SHIFT)) & GPIO_ICR2_ICR22_MASK) #define GPIO_ICR2_ICR23_MASK (0xC000U) #define GPIO_ICR2_ICR23_SHIFT (14U) +/*! ICR23 - ICR23 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ #define GPIO_ICR2_ICR23(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR23_SHIFT)) & GPIO_ICR2_ICR23_MASK) #define GPIO_ICR2_ICR24_MASK (0x30000U) #define GPIO_ICR2_ICR24_SHIFT (16U) +/*! ICR24 - ICR24 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ #define GPIO_ICR2_ICR24(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR24_SHIFT)) & GPIO_ICR2_ICR24_MASK) #define GPIO_ICR2_ICR25_MASK (0xC0000U) #define GPIO_ICR2_ICR25_SHIFT (18U) +/*! ICR25 - ICR25 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ #define GPIO_ICR2_ICR25(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR25_SHIFT)) & GPIO_ICR2_ICR25_MASK) #define GPIO_ICR2_ICR26_MASK (0x300000U) #define GPIO_ICR2_ICR26_SHIFT (20U) +/*! ICR26 - ICR26 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ #define GPIO_ICR2_ICR26(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR26_SHIFT)) & GPIO_ICR2_ICR26_MASK) #define GPIO_ICR2_ICR27_MASK (0xC00000U) #define GPIO_ICR2_ICR27_SHIFT (22U) +/*! ICR27 - ICR27 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ #define GPIO_ICR2_ICR27(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR27_SHIFT)) & GPIO_ICR2_ICR27_MASK) #define GPIO_ICR2_ICR28_MASK (0x3000000U) #define GPIO_ICR2_ICR28_SHIFT (24U) +/*! ICR28 - ICR28 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ #define GPIO_ICR2_ICR28(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR28_SHIFT)) & GPIO_ICR2_ICR28_MASK) #define GPIO_ICR2_ICR29_MASK (0xC000000U) #define GPIO_ICR2_ICR29_SHIFT (26U) +/*! ICR29 - ICR29 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ #define GPIO_ICR2_ICR29(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR29_SHIFT)) & GPIO_ICR2_ICR29_MASK) #define GPIO_ICR2_ICR30_MASK (0x30000000U) #define GPIO_ICR2_ICR30_SHIFT (28U) +/*! ICR30 - ICR30 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ #define GPIO_ICR2_ICR30(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR30_SHIFT)) & GPIO_ICR2_ICR30_MASK) #define GPIO_ICR2_ICR31_MASK (0xC0000000U) #define GPIO_ICR2_ICR31_SHIFT (30U) +/*! ICR31 - ICR31 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ #define GPIO_ICR2_ICR31(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR31_SHIFT)) & GPIO_ICR2_ICR31_MASK) +/*! @} */ /*! @name IMR - GPIO interrupt mask register */ +/*! @{ */ #define GPIO_IMR_IMR_MASK (0xFFFFFFFFU) #define GPIO_IMR_IMR_SHIFT (0U) #define GPIO_IMR_IMR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_IMR_IMR_SHIFT)) & GPIO_IMR_IMR_MASK) +/*! @} */ /*! @name ISR - GPIO interrupt status register */ +/*! @{ */ #define GPIO_ISR_ISR_MASK (0xFFFFFFFFU) #define GPIO_ISR_ISR_SHIFT (0U) #define GPIO_ISR_ISR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISR_ISR_SHIFT)) & GPIO_ISR_ISR_MASK) +/*! @} */ /*! @name EDGE_SEL - GPIO edge select register */ +/*! @{ */ #define GPIO_EDGE_SEL_GPIO_EDGE_SEL_MASK (0xFFFFFFFFU) #define GPIO_EDGE_SEL_GPIO_EDGE_SEL_SHIFT (0U) #define GPIO_EDGE_SEL_GPIO_EDGE_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPIO_EDGE_SEL_GPIO_EDGE_SEL_SHIFT)) & GPIO_EDGE_SEL_GPIO_EDGE_SEL_MASK) +/*! @} */ + +/*! @name DR_SET - GPIO data register SET */ +/*! @{ */ +#define GPIO_DR_SET_DR_SET_MASK (0xFFFFFFFFU) +#define GPIO_DR_SET_DR_SET_SHIFT (0U) +#define GPIO_DR_SET_DR_SET(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DR_SET_DR_SET_SHIFT)) & GPIO_DR_SET_DR_SET_MASK) +/*! @} */ + +/*! @name DR_CLEAR - GPIO data register CLEAR */ +/*! @{ */ +#define GPIO_DR_CLEAR_DR_CLEAR_MASK (0xFFFFFFFFU) +#define GPIO_DR_CLEAR_DR_CLEAR_SHIFT (0U) +#define GPIO_DR_CLEAR_DR_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DR_CLEAR_DR_CLEAR_SHIFT)) & GPIO_DR_CLEAR_DR_CLEAR_MASK) +/*! @} */ + +/*! @name DR_TOGGLE - GPIO data register TOGGLE */ +/*! @{ */ +#define GPIO_DR_TOGGLE_DR_TOGGLE_MASK (0xFFFFFFFFU) +#define GPIO_DR_TOGGLE_DR_TOGGLE_SHIFT (0U) +#define GPIO_DR_TOGGLE_DR_TOGGLE(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DR_TOGGLE_DR_TOGGLE_SHIFT)) & GPIO_DR_TOGGLE_DR_TOGGLE_MASK) +/*! @} */ /*! @@ -11173,7 +17133,8 @@ typedef struct { #define GPIO_BASE_PTRS { (GPIO_Type *)0u, GPIO1, GPIO2, GPIO3, GPIO4, GPIO5 } /** Interrupt vectors for the GPIO peripheral type */ #define GPIO_IRQS { NotAvail_IRQn, GPIO1_INT0_IRQn, GPIO1_INT1_IRQn, GPIO1_INT2_IRQn, GPIO1_INT3_IRQn, GPIO1_INT4_IRQn, GPIO1_INT5_IRQn, GPIO1_INT6_IRQn, GPIO1_INT7_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn } -#define GPIO_COMBINED_IRQS { NotAvail_IRQn, GPIO1_Combined_16_31_IRQn, GPIO2_Combined_16_31_IRQn, GPIO2_Combined_0_15_IRQn, GPIO3_Combined_16_31_IRQn, GPIO3_Combined_0_15_IRQn, GPIO4_Combined_16_31_IRQn, GPIO4_Combined_0_15_IRQn, GPIO5_Combined_16_31_IRQn, GPIO5_Combined_0_15_IRQn } +#define GPIO_COMBINED_LOW_IRQS { NotAvail_IRQn, GPIO1_Combined_0_15_IRQn, GPIO2_Combined_0_15_IRQn, GPIO3_Combined_0_15_IRQn, GPIO4_Combined_0_15_IRQn, GPIO5_Combined_0_15_IRQn } +#define GPIO_COMBINED_HIGH_IRQS { NotAvail_IRQn, GPIO1_Combined_16_31_IRQn, GPIO2_Combined_16_31_IRQn, GPIO3_Combined_16_31_IRQn, GPIO4_Combined_16_31_IRQn, GPIO5_Combined_16_31_IRQn } /*! * @} @@ -11210,41 +17171,92 @@ typedef struct { */ /*! @name CR - GPT Control Register */ +/*! @{ */ #define GPT_CR_EN_MASK (0x1U) #define GPT_CR_EN_SHIFT (0U) +/*! EN + * 0b0..GPT is disabled. + * 0b1..GPT is enabled. + */ #define GPT_CR_EN(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_EN_SHIFT)) & GPT_CR_EN_MASK) #define GPT_CR_ENMOD_MASK (0x2U) #define GPT_CR_ENMOD_SHIFT (1U) +/*! ENMOD + * 0b0..GPT counter will retain its value when it is disabled. + * 0b1..GPT counter value is reset to 0 when it is disabled. + */ #define GPT_CR_ENMOD(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_ENMOD_SHIFT)) & GPT_CR_ENMOD_MASK) #define GPT_CR_DBGEN_MASK (0x4U) #define GPT_CR_DBGEN_SHIFT (2U) +/*! DBGEN + * 0b0..GPT is disabled in debug mode. + * 0b1..GPT is enabled in debug mode. + */ #define GPT_CR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_DBGEN_SHIFT)) & GPT_CR_DBGEN_MASK) #define GPT_CR_WAITEN_MASK (0x8U) #define GPT_CR_WAITEN_SHIFT (3U) +/*! WAITEN + * 0b0..GPT is disabled in wait mode. + * 0b1..GPT is enabled in wait mode. + */ #define GPT_CR_WAITEN(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_WAITEN_SHIFT)) & GPT_CR_WAITEN_MASK) #define GPT_CR_DOZEEN_MASK (0x10U) #define GPT_CR_DOZEEN_SHIFT (4U) +/*! DOZEEN + * 0b0..GPT is disabled in doze mode. + * 0b1..GPT is enabled in doze mode. + */ #define GPT_CR_DOZEEN(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_DOZEEN_SHIFT)) & GPT_CR_DOZEEN_MASK) #define GPT_CR_STOPEN_MASK (0x20U) #define GPT_CR_STOPEN_SHIFT (5U) +/*! STOPEN + * 0b0..GPT is disabled in Stop mode. + * 0b1..GPT is enabled in Stop mode. + */ #define GPT_CR_STOPEN(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_STOPEN_SHIFT)) & GPT_CR_STOPEN_MASK) #define GPT_CR_CLKSRC_MASK (0x1C0U) #define GPT_CR_CLKSRC_SHIFT (6U) +/*! CLKSRC + * 0b000..No clock + * 0b001..Peripheral Clock (ipg_clk) + * 0b010..High Frequency Reference Clock (ipg_clk_highfreq) + * 0b011..External Clock + * 0b100..Low Frequency Reference Clock (ipg_clk_32k) + * 0b101..Crystal oscillator as Reference Clock (ipg_clk_24M) + */ #define GPT_CR_CLKSRC(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_CLKSRC_SHIFT)) & GPT_CR_CLKSRC_MASK) #define GPT_CR_FRR_MASK (0x200U) #define GPT_CR_FRR_SHIFT (9U) +/*! FRR + * 0b0..Restart mode + * 0b1..Free-Run mode + */ #define GPT_CR_FRR(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_FRR_SHIFT)) & GPT_CR_FRR_MASK) #define GPT_CR_EN_24M_MASK (0x400U) #define GPT_CR_EN_24M_SHIFT (10U) +/*! EN_24M + * 0b0..24M clock disabled + * 0b1..24M clock enabled + */ #define GPT_CR_EN_24M(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_EN_24M_SHIFT)) & GPT_CR_EN_24M_MASK) #define GPT_CR_SWR_MASK (0x8000U) #define GPT_CR_SWR_SHIFT (15U) +/*! SWR + * 0b0..GPT is not in reset state + * 0b1..GPT is in reset state + */ #define GPT_CR_SWR(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_SWR_SHIFT)) & GPT_CR_SWR_MASK) #define GPT_CR_IM1_MASK (0x30000U) #define GPT_CR_IM1_SHIFT (16U) #define GPT_CR_IM1(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_IM1_SHIFT)) & GPT_CR_IM1_MASK) #define GPT_CR_IM2_MASK (0xC0000U) #define GPT_CR_IM2_SHIFT (18U) +/*! IM2 + * 0b00..capture disabled + * 0b01..capture on rising edge only + * 0b10..capture on falling edge only + * 0b11..capture on both edges + */ #define GPT_CR_IM2(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_IM2_SHIFT)) & GPT_CR_IM2_MASK) #define GPT_CR_OM1_MASK (0x700000U) #define GPT_CR_OM1_SHIFT (20U) @@ -11254,6 +17266,13 @@ typedef struct { #define GPT_CR_OM2(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_OM2_SHIFT)) & GPT_CR_OM2_MASK) #define GPT_CR_OM3_MASK (0x1C000000U) #define GPT_CR_OM3_SHIFT (26U) +/*! OM3 + * 0b000..Output disconnected. No response on pin. + * 0b001..Toggle output pin + * 0b010..Clear output pin + * 0b011..Set output pin + * 0b1xx..Generate an active low pulse (that is one input clock wide) on the output pin. + */ #define GPT_CR_OM3(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_OM3_SHIFT)) & GPT_CR_OM3_MASK) #define GPT_CR_FO1_MASK (0x20000000U) #define GPT_CR_FO1_SHIFT (29U) @@ -11263,17 +17282,35 @@ typedef struct { #define GPT_CR_FO2(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_FO2_SHIFT)) & GPT_CR_FO2_MASK) #define GPT_CR_FO3_MASK (0x80000000U) #define GPT_CR_FO3_SHIFT (31U) +/*! FO3 + * 0b0..Writing a 0 has no effect. + * 0b1..Causes the programmed pin action on the timer Output Compare n pin; the OFn flag is not set. + */ #define GPT_CR_FO3(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_FO3_SHIFT)) & GPT_CR_FO3_MASK) +/*! @} */ /*! @name PR - GPT Prescaler Register */ +/*! @{ */ #define GPT_PR_PRESCALER_MASK (0xFFFU) #define GPT_PR_PRESCALER_SHIFT (0U) +/*! PRESCALER + * 0b000000000000..Divide by 1 + * 0b000000000001..Divide by 2 + * 0b111111111111..Divide by 4096 + */ #define GPT_PR_PRESCALER(x) (((uint32_t)(((uint32_t)(x)) << GPT_PR_PRESCALER_SHIFT)) & GPT_PR_PRESCALER_MASK) #define GPT_PR_PRESCALER24M_MASK (0xF000U) #define GPT_PR_PRESCALER24M_SHIFT (12U) +/*! PRESCALER24M + * 0b0000..Divide by 1 + * 0b0001..Divide by 2 + * 0b1111..Divide by 16 + */ #define GPT_PR_PRESCALER24M(x) (((uint32_t)(((uint32_t)(x)) << GPT_PR_PRESCALER24M_SHIFT)) & GPT_PR_PRESCALER24M_MASK) +/*! @} */ /*! @name SR - GPT Status Register */ +/*! @{ */ #define GPT_SR_OF1_MASK (0x1U) #define GPT_SR_OF1_SHIFT (0U) #define GPT_SR_OF1(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_OF1_SHIFT)) & GPT_SR_OF1_MASK) @@ -11282,18 +17319,32 @@ typedef struct { #define GPT_SR_OF2(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_OF2_SHIFT)) & GPT_SR_OF2_MASK) #define GPT_SR_OF3_MASK (0x4U) #define GPT_SR_OF3_SHIFT (2U) +/*! OF3 + * 0b0..Compare event has not occurred. + * 0b1..Compare event has occurred. + */ #define GPT_SR_OF3(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_OF3_SHIFT)) & GPT_SR_OF3_MASK) #define GPT_SR_IF1_MASK (0x8U) #define GPT_SR_IF1_SHIFT (3U) #define GPT_SR_IF1(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_IF1_SHIFT)) & GPT_SR_IF1_MASK) #define GPT_SR_IF2_MASK (0x10U) #define GPT_SR_IF2_SHIFT (4U) +/*! IF2 + * 0b0..Capture event has not occurred. + * 0b1..Capture event has occurred. + */ #define GPT_SR_IF2(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_IF2_SHIFT)) & GPT_SR_IF2_MASK) #define GPT_SR_ROV_MASK (0x20U) #define GPT_SR_ROV_SHIFT (5U) +/*! ROV + * 0b0..Rollover has not occurred. + * 0b1..Rollover has occurred. + */ #define GPT_SR_ROV(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_ROV_SHIFT)) & GPT_SR_ROV_MASK) +/*! @} */ /*! @name IR - GPT Interrupt Register */ +/*! @{ */ #define GPT_IR_OF1IE_MASK (0x1U) #define GPT_IR_OF1IE_SHIFT (0U) #define GPT_IR_OF1IE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_OF1IE_SHIFT)) & GPT_IR_OF1IE_MASK) @@ -11302,37 +17353,56 @@ typedef struct { #define GPT_IR_OF2IE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_OF2IE_SHIFT)) & GPT_IR_OF2IE_MASK) #define GPT_IR_OF3IE_MASK (0x4U) #define GPT_IR_OF3IE_SHIFT (2U) +/*! OF3IE + * 0b0..Output Compare Channel n interrupt is disabled. + * 0b1..Output Compare Channel n interrupt is enabled. + */ #define GPT_IR_OF3IE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_OF3IE_SHIFT)) & GPT_IR_OF3IE_MASK) #define GPT_IR_IF1IE_MASK (0x8U) #define GPT_IR_IF1IE_SHIFT (3U) #define GPT_IR_IF1IE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_IF1IE_SHIFT)) & GPT_IR_IF1IE_MASK) #define GPT_IR_IF2IE_MASK (0x10U) #define GPT_IR_IF2IE_SHIFT (4U) +/*! IF2IE + * 0b0..IF2IE Input Capture n Interrupt Enable is disabled. + * 0b1..IF2IE Input Capture n Interrupt Enable is enabled. + */ #define GPT_IR_IF2IE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_IF2IE_SHIFT)) & GPT_IR_IF2IE_MASK) #define GPT_IR_ROVIE_MASK (0x20U) #define GPT_IR_ROVIE_SHIFT (5U) +/*! ROVIE + * 0b0..Rollover interrupt is disabled. + * 0b1..Rollover interrupt enabled. + */ #define GPT_IR_ROVIE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_ROVIE_SHIFT)) & GPT_IR_ROVIE_MASK) +/*! @} */ /*! @name OCR - GPT Output Compare Register 1..GPT Output Compare Register 3 */ +/*! @{ */ #define GPT_OCR_COMP_MASK (0xFFFFFFFFU) #define GPT_OCR_COMP_SHIFT (0U) #define GPT_OCR_COMP(x) (((uint32_t)(((uint32_t)(x)) << GPT_OCR_COMP_SHIFT)) & GPT_OCR_COMP_MASK) +/*! @} */ /* The count of GPT_OCR */ #define GPT_OCR_COUNT (3U) /*! @name ICR - GPT Input Capture Register 1..GPT Input Capture Register 2 */ +/*! @{ */ #define GPT_ICR_CAPT_MASK (0xFFFFFFFFU) #define GPT_ICR_CAPT_SHIFT (0U) #define GPT_ICR_CAPT(x) (((uint32_t)(((uint32_t)(x)) << GPT_ICR_CAPT_SHIFT)) & GPT_ICR_CAPT_MASK) +/*! @} */ /* The count of GPT_ICR */ #define GPT_ICR_COUNT (2U) /*! @name CNT - GPT Counter Register */ +/*! @{ */ #define GPT_CNT_COUNT_MASK (0xFFFFFFFFU) #define GPT_CNT_COUNT_SHIFT (0U) #define GPT_CNT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << GPT_CNT_COUNT_SHIFT)) & GPT_CNT_COUNT_MASK) +/*! @} */ /*! @@ -11409,8 +17479,12 @@ typedef struct { */ /*! @name VERID - Version ID Register */ +/*! @{ */ #define I2S_VERID_FEATURE_MASK (0xFFFFU) #define I2S_VERID_FEATURE_SHIFT (0U) +/*! FEATURE - Feature Specification Number + * 0b0000000000000000..Standard feature set. + */ #define I2S_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << I2S_VERID_FEATURE_SHIFT)) & I2S_VERID_FEATURE_MASK) #define I2S_VERID_MINOR_MASK (0xFF0000U) #define I2S_VERID_MINOR_SHIFT (16U) @@ -11418,8 +17492,10 @@ typedef struct { #define I2S_VERID_MAJOR_MASK (0xFF000000U) #define I2S_VERID_MAJOR_SHIFT (24U) #define I2S_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << I2S_VERID_MAJOR_SHIFT)) & I2S_VERID_MAJOR_MASK) +/*! @} */ /*! @name PARAM - Parameter Register */ +/*! @{ */ #define I2S_PARAM_DATALINE_MASK (0xFU) #define I2S_PARAM_DATALINE_SHIFT (0U) #define I2S_PARAM_DATALINE(x) (((uint32_t)(((uint32_t)(x)) << I2S_PARAM_DATALINE_SHIFT)) & I2S_PARAM_DATALINE_MASK) @@ -11429,92 +17505,200 @@ typedef struct { #define I2S_PARAM_FRAME_MASK (0xF0000U) #define I2S_PARAM_FRAME_SHIFT (16U) #define I2S_PARAM_FRAME(x) (((uint32_t)(((uint32_t)(x)) << I2S_PARAM_FRAME_SHIFT)) & I2S_PARAM_FRAME_MASK) +/*! @} */ /*! @name TCSR - SAI Transmit Control Register */ +/*! @{ */ #define I2S_TCSR_FRDE_MASK (0x1U) #define I2S_TCSR_FRDE_SHIFT (0U) +/*! FRDE - FIFO Request DMA Enable + * 0b0..Disables the DMA request. + * 0b1..Enables the DMA request. + */ #define I2S_TCSR_FRDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRDE_SHIFT)) & I2S_TCSR_FRDE_MASK) #define I2S_TCSR_FWDE_MASK (0x2U) #define I2S_TCSR_FWDE_SHIFT (1U) +/*! FWDE - FIFO Warning DMA Enable + * 0b0..Disables the DMA request. + * 0b1..Enables the DMA request. + */ #define I2S_TCSR_FWDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWDE_SHIFT)) & I2S_TCSR_FWDE_MASK) #define I2S_TCSR_FRIE_MASK (0x100U) #define I2S_TCSR_FRIE_SHIFT (8U) +/*! FRIE - FIFO Request Interrupt Enable + * 0b0..Disables the interrupt. + * 0b1..Enables the interrupt. + */ #define I2S_TCSR_FRIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRIE_SHIFT)) & I2S_TCSR_FRIE_MASK) #define I2S_TCSR_FWIE_MASK (0x200U) #define I2S_TCSR_FWIE_SHIFT (9U) +/*! FWIE - FIFO Warning Interrupt Enable + * 0b0..Disables the interrupt. + * 0b1..Enables the interrupt. + */ #define I2S_TCSR_FWIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWIE_SHIFT)) & I2S_TCSR_FWIE_MASK) #define I2S_TCSR_FEIE_MASK (0x400U) #define I2S_TCSR_FEIE_SHIFT (10U) +/*! FEIE - FIFO Error Interrupt Enable + * 0b0..Disables the interrupt. + * 0b1..Enables the interrupt. + */ #define I2S_TCSR_FEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEIE_SHIFT)) & I2S_TCSR_FEIE_MASK) #define I2S_TCSR_SEIE_MASK (0x800U) #define I2S_TCSR_SEIE_SHIFT (11U) +/*! SEIE - Sync Error Interrupt Enable + * 0b0..Disables interrupt. + * 0b1..Enables interrupt. + */ #define I2S_TCSR_SEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEIE_SHIFT)) & I2S_TCSR_SEIE_MASK) #define I2S_TCSR_WSIE_MASK (0x1000U) #define I2S_TCSR_WSIE_SHIFT (12U) +/*! WSIE - Word Start Interrupt Enable + * 0b0..Disables interrupt. + * 0b1..Enables interrupt. + */ #define I2S_TCSR_WSIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSIE_SHIFT)) & I2S_TCSR_WSIE_MASK) #define I2S_TCSR_FRF_MASK (0x10000U) #define I2S_TCSR_FRF_SHIFT (16U) +/*! FRF - FIFO Request Flag + * 0b0..Transmit FIFO watermark has not been reached. + * 0b1..Transmit FIFO watermark has been reached. + */ #define I2S_TCSR_FRF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRF_SHIFT)) & I2S_TCSR_FRF_MASK) #define I2S_TCSR_FWF_MASK (0x20000U) #define I2S_TCSR_FWF_SHIFT (17U) +/*! FWF - FIFO Warning Flag + * 0b0..No enabled transmit FIFO is empty. + * 0b1..Enabled transmit FIFO is empty. + */ #define I2S_TCSR_FWF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWF_SHIFT)) & I2S_TCSR_FWF_MASK) #define I2S_TCSR_FEF_MASK (0x40000U) #define I2S_TCSR_FEF_SHIFT (18U) +/*! FEF - FIFO Error Flag + * 0b0..Transmit underrun not detected. + * 0b1..Transmit underrun detected. + */ #define I2S_TCSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEF_SHIFT)) & I2S_TCSR_FEF_MASK) #define I2S_TCSR_SEF_MASK (0x80000U) #define I2S_TCSR_SEF_SHIFT (19U) +/*! SEF - Sync Error Flag + * 0b0..Sync error not detected. + * 0b1..Frame sync error detected. + */ #define I2S_TCSR_SEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEF_SHIFT)) & I2S_TCSR_SEF_MASK) #define I2S_TCSR_WSF_MASK (0x100000U) #define I2S_TCSR_WSF_SHIFT (20U) +/*! WSF - Word Start Flag + * 0b0..Start of word not detected. + * 0b1..Start of word detected. + */ #define I2S_TCSR_WSF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSF_SHIFT)) & I2S_TCSR_WSF_MASK) #define I2S_TCSR_SR_MASK (0x1000000U) #define I2S_TCSR_SR_SHIFT (24U) +/*! SR - Software Reset + * 0b0..No effect. + * 0b1..Software reset. + */ #define I2S_TCSR_SR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SR_SHIFT)) & I2S_TCSR_SR_MASK) #define I2S_TCSR_FR_MASK (0x2000000U) #define I2S_TCSR_FR_SHIFT (25U) +/*! FR - FIFO Reset + * 0b0..No effect. + * 0b1..FIFO reset. + */ #define I2S_TCSR_FR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FR_SHIFT)) & I2S_TCSR_FR_MASK) #define I2S_TCSR_BCE_MASK (0x10000000U) #define I2S_TCSR_BCE_SHIFT (28U) +/*! BCE - Bit Clock Enable + * 0b0..Transmit bit clock is disabled. + * 0b1..Transmit bit clock is enabled. + */ #define I2S_TCSR_BCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_BCE_SHIFT)) & I2S_TCSR_BCE_MASK) #define I2S_TCSR_DBGE_MASK (0x20000000U) #define I2S_TCSR_DBGE_SHIFT (29U) +/*! DBGE - Debug Enable + * 0b0..Transmitter is disabled in Debug mode, after completing the current frame. + * 0b1..Transmitter is enabled in Debug mode. + */ #define I2S_TCSR_DBGE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_DBGE_SHIFT)) & I2S_TCSR_DBGE_MASK) #define I2S_TCSR_STOPE_MASK (0x40000000U) #define I2S_TCSR_STOPE_SHIFT (30U) +/*! STOPE - Stop Enable + * 0b0..Transmitter disabled in Stop mode. + * 0b1..Transmitter enabled in Stop mode. + */ #define I2S_TCSR_STOPE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_STOPE_SHIFT)) & I2S_TCSR_STOPE_MASK) #define I2S_TCSR_TE_MASK (0x80000000U) #define I2S_TCSR_TE_SHIFT (31U) +/*! TE - Transmitter Enable + * 0b0..Transmitter is disabled. + * 0b1..Transmitter is enabled, or transmitter has been disabled and has not yet reached end of frame. + */ #define I2S_TCSR_TE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_TE_SHIFT)) & I2S_TCSR_TE_MASK) +/*! @} */ /*! @name TCR1 - SAI Transmit Configuration 1 Register */ +/*! @{ */ #define I2S_TCR1_TFW_MASK (0x1FU) #define I2S_TCR1_TFW_SHIFT (0U) #define I2S_TCR1_TFW(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR1_TFW_SHIFT)) & I2S_TCR1_TFW_MASK) +/*! @} */ /*! @name TCR2 - SAI Transmit Configuration 2 Register */ +/*! @{ */ #define I2S_TCR2_DIV_MASK (0xFFU) #define I2S_TCR2_DIV_SHIFT (0U) #define I2S_TCR2_DIV(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_DIV_SHIFT)) & I2S_TCR2_DIV_MASK) #define I2S_TCR2_BCD_MASK (0x1000000U) #define I2S_TCR2_BCD_SHIFT (24U) +/*! BCD - Bit Clock Direction + * 0b0..Bit clock is generated externally in Slave mode. + * 0b1..Bit clock is generated internally in Master mode. + */ #define I2S_TCR2_BCD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCD_SHIFT)) & I2S_TCR2_BCD_MASK) #define I2S_TCR2_BCP_MASK (0x2000000U) #define I2S_TCR2_BCP_SHIFT (25U) +/*! BCP - Bit Clock Polarity + * 0b0..Bit clock is active high with drive outputs on rising edge and sample inputs on falling edge. + * 0b1..Bit clock is active low with drive outputs on falling edge and sample inputs on rising edge. + */ #define I2S_TCR2_BCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCP_SHIFT)) & I2S_TCR2_BCP_MASK) #define I2S_TCR2_MSEL_MASK (0xC000000U) #define I2S_TCR2_MSEL_SHIFT (26U) +/*! MSEL - MCLK Select + * 0b00..Bus Clock selected. + * 0b01..Master Clock (MCLK) 1 option selected. + * 0b10..Master Clock (MCLK) 2 option selected. + * 0b11..Master Clock (MCLK) 3 option selected. + */ #define I2S_TCR2_MSEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_MSEL_SHIFT)) & I2S_TCR2_MSEL_MASK) #define I2S_TCR2_BCI_MASK (0x10000000U) #define I2S_TCR2_BCI_SHIFT (28U) +/*! BCI - Bit Clock Input + * 0b0..No effect. + * 0b1..Internal logic is clocked as if bit clock was externally generated. + */ #define I2S_TCR2_BCI(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCI_SHIFT)) & I2S_TCR2_BCI_MASK) #define I2S_TCR2_BCS_MASK (0x20000000U) #define I2S_TCR2_BCS_SHIFT (29U) +/*! BCS - Bit Clock Swap + * 0b0..Use the normal bit clock source. + * 0b1..Swap the bit clock source. + */ #define I2S_TCR2_BCS(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCS_SHIFT)) & I2S_TCR2_BCS_MASK) #define I2S_TCR2_SYNC_MASK (0xC0000000U) #define I2S_TCR2_SYNC_SHIFT (30U) +/*! SYNC - Synchronous Mode + * 0b00..Asynchronous mode. + * 0b01..Synchronous with receiver. + * 0b10..Reserved. + * 0b11..Reserved. + */ #define I2S_TCR2_SYNC(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_SYNC_SHIFT)) & I2S_TCR2_SYNC_MASK) +/*! @} */ /*! @name TCR3 - SAI Transmit Configuration 3 Register */ +/*! @{ */ #define I2S_TCR3_WDFL_MASK (0x1FU) #define I2S_TCR3_WDFL_SHIFT (0U) #define I2S_TCR3_WDFL(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_WDFL_SHIFT)) & I2S_TCR3_WDFL_MASK) @@ -11524,25 +17708,51 @@ typedef struct { #define I2S_TCR3_CFR_MASK (0xF000000U) #define I2S_TCR3_CFR_SHIFT (24U) #define I2S_TCR3_CFR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_CFR_SHIFT)) & I2S_TCR3_CFR_MASK) +/*! @} */ /*! @name TCR4 - SAI Transmit Configuration 4 Register */ +/*! @{ */ #define I2S_TCR4_FSD_MASK (0x1U) #define I2S_TCR4_FSD_SHIFT (0U) +/*! FSD - Frame Sync Direction + * 0b0..Frame sync is generated externally in Slave mode. + * 0b1..Frame sync is generated internally in Master mode. + */ #define I2S_TCR4_FSD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSD_SHIFT)) & I2S_TCR4_FSD_MASK) #define I2S_TCR4_FSP_MASK (0x2U) #define I2S_TCR4_FSP_SHIFT (1U) +/*! FSP - Frame Sync Polarity + * 0b0..Frame sync is active high. + * 0b1..Frame sync is active low. + */ #define I2S_TCR4_FSP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSP_SHIFT)) & I2S_TCR4_FSP_MASK) #define I2S_TCR4_ONDEM_MASK (0x4U) #define I2S_TCR4_ONDEM_SHIFT (2U) +/*! ONDEM - On Demand Mode + * 0b0..Internal frame sync is generated continuously. + * 0b1..Internal frame sync is generated when the FIFO warning flag is clear. + */ #define I2S_TCR4_ONDEM(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_ONDEM_SHIFT)) & I2S_TCR4_ONDEM_MASK) #define I2S_TCR4_FSE_MASK (0x8U) #define I2S_TCR4_FSE_SHIFT (3U) +/*! FSE - Frame Sync Early + * 0b0..Frame sync asserts with the first bit of the frame. + * 0b1..Frame sync asserts one bit before the first bit of the frame. + */ #define I2S_TCR4_FSE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSE_SHIFT)) & I2S_TCR4_FSE_MASK) #define I2S_TCR4_MF_MASK (0x10U) #define I2S_TCR4_MF_SHIFT (4U) +/*! MF - MSB First + * 0b0..LSB is transmitted first. + * 0b1..MSB is transmitted first. + */ #define I2S_TCR4_MF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_MF_SHIFT)) & I2S_TCR4_MF_MASK) #define I2S_TCR4_CHMOD_MASK (0x20U) #define I2S_TCR4_CHMOD_SHIFT (5U) +/*! CHMOD - Channel Mode + * 0b0..TDM mode, transmit data pins are tri-stated when slots are masked or channels are disabled. + * 0b1..Output mode, transmit data pins are never tri-stated and will output zero when slots are masked or channels are disabled. + */ #define I2S_TCR4_CHMOD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_CHMOD_SHIFT)) & I2S_TCR4_CHMOD_MASK) #define I2S_TCR4_SYWD_MASK (0x1F00U) #define I2S_TCR4_SYWD_SHIFT (8U) @@ -11552,15 +17762,33 @@ typedef struct { #define I2S_TCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FRSZ_SHIFT)) & I2S_TCR4_FRSZ_MASK) #define I2S_TCR4_FPACK_MASK (0x3000000U) #define I2S_TCR4_FPACK_SHIFT (24U) +/*! FPACK - FIFO Packing Mode + * 0b00..FIFO packing is disabled + * 0b01..Reserved + * 0b10..8-bit FIFO packing is enabled + * 0b11..16-bit FIFO packing is enabled + */ #define I2S_TCR4_FPACK(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FPACK_SHIFT)) & I2S_TCR4_FPACK_MASK) #define I2S_TCR4_FCOMB_MASK (0xC000000U) #define I2S_TCR4_FCOMB_SHIFT (26U) +/*! FCOMB - FIFO Combine Mode + * 0b00..FIFO combine mode disabled. + * 0b01..FIFO combine mode enabled on FIFO reads (from transmit shift registers). + * 0b10..FIFO combine mode enabled on FIFO writes (by software). + * 0b11..FIFO combine mode enabled on FIFO reads (from transmit shift registers) and writes (by software). + */ #define I2S_TCR4_FCOMB(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FCOMB_SHIFT)) & I2S_TCR4_FCOMB_MASK) #define I2S_TCR4_FCONT_MASK (0x10000000U) #define I2S_TCR4_FCONT_SHIFT (28U) +/*! FCONT - FIFO Continue on Error + * 0b0..On FIFO error, the SAI will continue from the start of the next frame after the FIFO error flag has been cleared. + * 0b1..On FIFO error, the SAI will continue from the same word that caused the FIFO error to set after the FIFO warning flag has been cleared. + */ #define I2S_TCR4_FCONT(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FCONT_SHIFT)) & I2S_TCR4_FCONT_MASK) +/*! @} */ /*! @name TCR5 - SAI Transmit Configuration 5 Register */ +/*! @{ */ #define I2S_TCR5_FBT_MASK (0x1F00U) #define I2S_TCR5_FBT_SHIFT (8U) #define I2S_TCR5_FBT(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_FBT_SHIFT)) & I2S_TCR5_FBT_MASK) @@ -11570,16 +17798,20 @@ typedef struct { #define I2S_TCR5_WNW_MASK (0x1F000000U) #define I2S_TCR5_WNW_SHIFT (24U) #define I2S_TCR5_WNW(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_WNW_SHIFT)) & I2S_TCR5_WNW_MASK) +/*! @} */ /*! @name TDR - SAI Transmit Data Register */ +/*! @{ */ #define I2S_TDR_TDR_MASK (0xFFFFFFFFU) #define I2S_TDR_TDR_SHIFT (0U) #define I2S_TDR_TDR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TDR_TDR_SHIFT)) & I2S_TDR_TDR_MASK) +/*! @} */ /* The count of I2S_TDR */ #define I2S_TDR_COUNT (4U) /*! @name TFR - SAI Transmit FIFO Register */ +/*! @{ */ #define I2S_TFR_RFP_MASK (0x3FU) #define I2S_TFR_RFP_SHIFT (0U) #define I2S_TFR_RFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TFR_RFP_SHIFT)) & I2S_TFR_RFP_MASK) @@ -11588,101 +17820,219 @@ typedef struct { #define I2S_TFR_WFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TFR_WFP_SHIFT)) & I2S_TFR_WFP_MASK) #define I2S_TFR_WCP_MASK (0x80000000U) #define I2S_TFR_WCP_SHIFT (31U) +/*! WCP - Write Channel Pointer + * 0b0..No effect. + * 0b1..FIFO combine is enabled for FIFO writes and this FIFO will be written on the next FIFO write. + */ #define I2S_TFR_WCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TFR_WCP_SHIFT)) & I2S_TFR_WCP_MASK) +/*! @} */ /* The count of I2S_TFR */ #define I2S_TFR_COUNT (4U) /*! @name TMR - SAI Transmit Mask Register */ +/*! @{ */ #define I2S_TMR_TWM_MASK (0xFFFFFFFFU) #define I2S_TMR_TWM_SHIFT (0U) +/*! TWM - Transmit Word Mask + * 0b00000000000000000000000000000000..Word N is enabled. + * 0b00000000000000000000000000000001..Word N is masked. The transmit data pins are tri-stated or drive zero when masked. + */ #define I2S_TMR_TWM(x) (((uint32_t)(((uint32_t)(x)) << I2S_TMR_TWM_SHIFT)) & I2S_TMR_TWM_MASK) +/*! @} */ /*! @name RCSR - SAI Receive Control Register */ +/*! @{ */ #define I2S_RCSR_FRDE_MASK (0x1U) #define I2S_RCSR_FRDE_SHIFT (0U) +/*! FRDE - FIFO Request DMA Enable + * 0b0..Disables the DMA request. + * 0b1..Enables the DMA request. + */ #define I2S_RCSR_FRDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRDE_SHIFT)) & I2S_RCSR_FRDE_MASK) #define I2S_RCSR_FWDE_MASK (0x2U) #define I2S_RCSR_FWDE_SHIFT (1U) +/*! FWDE - FIFO Warning DMA Enable + * 0b0..Disables the DMA request. + * 0b1..Enables the DMA request. + */ #define I2S_RCSR_FWDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWDE_SHIFT)) & I2S_RCSR_FWDE_MASK) #define I2S_RCSR_FRIE_MASK (0x100U) #define I2S_RCSR_FRIE_SHIFT (8U) +/*! FRIE - FIFO Request Interrupt Enable + * 0b0..Disables the interrupt. + * 0b1..Enables the interrupt. + */ #define I2S_RCSR_FRIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRIE_SHIFT)) & I2S_RCSR_FRIE_MASK) #define I2S_RCSR_FWIE_MASK (0x200U) #define I2S_RCSR_FWIE_SHIFT (9U) +/*! FWIE - FIFO Warning Interrupt Enable + * 0b0..Disables the interrupt. + * 0b1..Enables the interrupt. + */ #define I2S_RCSR_FWIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWIE_SHIFT)) & I2S_RCSR_FWIE_MASK) #define I2S_RCSR_FEIE_MASK (0x400U) #define I2S_RCSR_FEIE_SHIFT (10U) +/*! FEIE - FIFO Error Interrupt Enable + * 0b0..Disables the interrupt. + * 0b1..Enables the interrupt. + */ #define I2S_RCSR_FEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEIE_SHIFT)) & I2S_RCSR_FEIE_MASK) #define I2S_RCSR_SEIE_MASK (0x800U) #define I2S_RCSR_SEIE_SHIFT (11U) +/*! SEIE - Sync Error Interrupt Enable + * 0b0..Disables interrupt. + * 0b1..Enables interrupt. + */ #define I2S_RCSR_SEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEIE_SHIFT)) & I2S_RCSR_SEIE_MASK) #define I2S_RCSR_WSIE_MASK (0x1000U) #define I2S_RCSR_WSIE_SHIFT (12U) +/*! WSIE - Word Start Interrupt Enable + * 0b0..Disables interrupt. + * 0b1..Enables interrupt. + */ #define I2S_RCSR_WSIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSIE_SHIFT)) & I2S_RCSR_WSIE_MASK) #define I2S_RCSR_FRF_MASK (0x10000U) #define I2S_RCSR_FRF_SHIFT (16U) +/*! FRF - FIFO Request Flag + * 0b0..Receive FIFO watermark not reached. + * 0b1..Receive FIFO watermark has been reached. + */ #define I2S_RCSR_FRF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRF_SHIFT)) & I2S_RCSR_FRF_MASK) #define I2S_RCSR_FWF_MASK (0x20000U) #define I2S_RCSR_FWF_SHIFT (17U) +/*! FWF - FIFO Warning Flag + * 0b0..No enabled receive FIFO is full. + * 0b1..Enabled receive FIFO is full. + */ #define I2S_RCSR_FWF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWF_SHIFT)) & I2S_RCSR_FWF_MASK) #define I2S_RCSR_FEF_MASK (0x40000U) #define I2S_RCSR_FEF_SHIFT (18U) +/*! FEF - FIFO Error Flag + * 0b0..Receive overflow not detected. + * 0b1..Receive overflow detected. + */ #define I2S_RCSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEF_SHIFT)) & I2S_RCSR_FEF_MASK) #define I2S_RCSR_SEF_MASK (0x80000U) #define I2S_RCSR_SEF_SHIFT (19U) +/*! SEF - Sync Error Flag + * 0b0..Sync error not detected. + * 0b1..Frame sync error detected. + */ #define I2S_RCSR_SEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEF_SHIFT)) & I2S_RCSR_SEF_MASK) #define I2S_RCSR_WSF_MASK (0x100000U) #define I2S_RCSR_WSF_SHIFT (20U) +/*! WSF - Word Start Flag + * 0b0..Start of word not detected. + * 0b1..Start of word detected. + */ #define I2S_RCSR_WSF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSF_SHIFT)) & I2S_RCSR_WSF_MASK) #define I2S_RCSR_SR_MASK (0x1000000U) #define I2S_RCSR_SR_SHIFT (24U) +/*! SR - Software Reset + * 0b0..No effect. + * 0b1..Software reset. + */ #define I2S_RCSR_SR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SR_SHIFT)) & I2S_RCSR_SR_MASK) #define I2S_RCSR_FR_MASK (0x2000000U) #define I2S_RCSR_FR_SHIFT (25U) +/*! FR - FIFO Reset + * 0b0..No effect. + * 0b1..FIFO reset. + */ #define I2S_RCSR_FR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FR_SHIFT)) & I2S_RCSR_FR_MASK) #define I2S_RCSR_BCE_MASK (0x10000000U) #define I2S_RCSR_BCE_SHIFT (28U) +/*! BCE - Bit Clock Enable + * 0b0..Receive bit clock is disabled. + * 0b1..Receive bit clock is enabled. + */ #define I2S_RCSR_BCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_BCE_SHIFT)) & I2S_RCSR_BCE_MASK) #define I2S_RCSR_DBGE_MASK (0x20000000U) #define I2S_RCSR_DBGE_SHIFT (29U) +/*! DBGE - Debug Enable + * 0b0..Receiver is disabled in Debug mode, after completing the current frame. + * 0b1..Receiver is enabled in Debug mode. + */ #define I2S_RCSR_DBGE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_DBGE_SHIFT)) & I2S_RCSR_DBGE_MASK) #define I2S_RCSR_STOPE_MASK (0x40000000U) #define I2S_RCSR_STOPE_SHIFT (30U) +/*! STOPE - Stop Enable + * 0b0..Receiver disabled in Stop mode. + * 0b1..Receiver enabled in Stop mode. + */ #define I2S_RCSR_STOPE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_STOPE_SHIFT)) & I2S_RCSR_STOPE_MASK) #define I2S_RCSR_RE_MASK (0x80000000U) #define I2S_RCSR_RE_SHIFT (31U) +/*! RE - Receiver Enable + * 0b0..Receiver is disabled. + * 0b1..Receiver is enabled, or receiver has been disabled and has not yet reached end of frame. + */ #define I2S_RCSR_RE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_RE_SHIFT)) & I2S_RCSR_RE_MASK) +/*! @} */ /*! @name RCR1 - SAI Receive Configuration 1 Register */ +/*! @{ */ #define I2S_RCR1_RFW_MASK (0x1FU) #define I2S_RCR1_RFW_SHIFT (0U) #define I2S_RCR1_RFW(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR1_RFW_SHIFT)) & I2S_RCR1_RFW_MASK) +/*! @} */ /*! @name RCR2 - SAI Receive Configuration 2 Register */ +/*! @{ */ #define I2S_RCR2_DIV_MASK (0xFFU) #define I2S_RCR2_DIV_SHIFT (0U) #define I2S_RCR2_DIV(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_DIV_SHIFT)) & I2S_RCR2_DIV_MASK) #define I2S_RCR2_BCD_MASK (0x1000000U) #define I2S_RCR2_BCD_SHIFT (24U) +/*! BCD - Bit Clock Direction + * 0b0..Bit clock is generated externally in Slave mode. + * 0b1..Bit clock is generated internally in Master mode. + */ #define I2S_RCR2_BCD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCD_SHIFT)) & I2S_RCR2_BCD_MASK) #define I2S_RCR2_BCP_MASK (0x2000000U) #define I2S_RCR2_BCP_SHIFT (25U) +/*! BCP - Bit Clock Polarity + * 0b0..Bit Clock is active high with drive outputs on rising edge and sample inputs on falling edge. + * 0b1..Bit Clock is active low with drive outputs on falling edge and sample inputs on rising edge. + */ #define I2S_RCR2_BCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCP_SHIFT)) & I2S_RCR2_BCP_MASK) #define I2S_RCR2_MSEL_MASK (0xC000000U) #define I2S_RCR2_MSEL_SHIFT (26U) +/*! MSEL - MCLK Select + * 0b00..Bus Clock selected. + * 0b01..Master Clock (MCLK) 1 option selected. + * 0b10..Master Clock (MCLK) 2 option selected. + * 0b11..Master Clock (MCLK) 3 option selected. + */ #define I2S_RCR2_MSEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_MSEL_SHIFT)) & I2S_RCR2_MSEL_MASK) #define I2S_RCR2_BCI_MASK (0x10000000U) #define I2S_RCR2_BCI_SHIFT (28U) +/*! BCI - Bit Clock Input + * 0b0..No effect. + * 0b1..Internal logic is clocked as if bit clock was externally generated. + */ #define I2S_RCR2_BCI(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCI_SHIFT)) & I2S_RCR2_BCI_MASK) #define I2S_RCR2_BCS_MASK (0x20000000U) #define I2S_RCR2_BCS_SHIFT (29U) +/*! BCS - Bit Clock Swap + * 0b0..Use the normal bit clock source. + * 0b1..Swap the bit clock source. + */ #define I2S_RCR2_BCS(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCS_SHIFT)) & I2S_RCR2_BCS_MASK) #define I2S_RCR2_SYNC_MASK (0xC0000000U) #define I2S_RCR2_SYNC_SHIFT (30U) +/*! SYNC - Synchronous Mode + * 0b00..Asynchronous mode. + * 0b01..Synchronous with transmitter. + * 0b10..Reserved. + * 0b11..Reserved. + */ #define I2S_RCR2_SYNC(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_SYNC_SHIFT)) & I2S_RCR2_SYNC_MASK) +/*! @} */ /*! @name RCR3 - SAI Receive Configuration 3 Register */ +/*! @{ */ #define I2S_RCR3_WDFL_MASK (0x1FU) #define I2S_RCR3_WDFL_SHIFT (0U) #define I2S_RCR3_WDFL(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_WDFL_SHIFT)) & I2S_RCR3_WDFL_MASK) @@ -11692,22 +18042,44 @@ typedef struct { #define I2S_RCR3_CFR_MASK (0xF000000U) #define I2S_RCR3_CFR_SHIFT (24U) #define I2S_RCR3_CFR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_CFR_SHIFT)) & I2S_RCR3_CFR_MASK) +/*! @} */ /*! @name RCR4 - SAI Receive Configuration 4 Register */ +/*! @{ */ #define I2S_RCR4_FSD_MASK (0x1U) #define I2S_RCR4_FSD_SHIFT (0U) +/*! FSD - Frame Sync Direction + * 0b0..Frame Sync is generated externally in Slave mode. + * 0b1..Frame Sync is generated internally in Master mode. + */ #define I2S_RCR4_FSD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSD_SHIFT)) & I2S_RCR4_FSD_MASK) #define I2S_RCR4_FSP_MASK (0x2U) #define I2S_RCR4_FSP_SHIFT (1U) +/*! FSP - Frame Sync Polarity + * 0b0..Frame sync is active high. + * 0b1..Frame sync is active low. + */ #define I2S_RCR4_FSP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSP_SHIFT)) & I2S_RCR4_FSP_MASK) #define I2S_RCR4_ONDEM_MASK (0x4U) #define I2S_RCR4_ONDEM_SHIFT (2U) +/*! ONDEM - On Demand Mode + * 0b0..Internal frame sync is generated continuously. + * 0b1..Internal frame sync is generated when the FIFO warning flag is clear. + */ #define I2S_RCR4_ONDEM(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_ONDEM_SHIFT)) & I2S_RCR4_ONDEM_MASK) #define I2S_RCR4_FSE_MASK (0x8U) #define I2S_RCR4_FSE_SHIFT (3U) +/*! FSE - Frame Sync Early + * 0b0..Frame sync asserts with the first bit of the frame. + * 0b1..Frame sync asserts one bit before the first bit of the frame. + */ #define I2S_RCR4_FSE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSE_SHIFT)) & I2S_RCR4_FSE_MASK) #define I2S_RCR4_MF_MASK (0x10U) #define I2S_RCR4_MF_SHIFT (4U) +/*! MF - MSB First + * 0b0..LSB is received first. + * 0b1..MSB is received first. + */ #define I2S_RCR4_MF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_MF_SHIFT)) & I2S_RCR4_MF_MASK) #define I2S_RCR4_SYWD_MASK (0x1F00U) #define I2S_RCR4_SYWD_SHIFT (8U) @@ -11717,15 +18089,33 @@ typedef struct { #define I2S_RCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FRSZ_SHIFT)) & I2S_RCR4_FRSZ_MASK) #define I2S_RCR4_FPACK_MASK (0x3000000U) #define I2S_RCR4_FPACK_SHIFT (24U) +/*! FPACK - FIFO Packing Mode + * 0b00..FIFO packing is disabled + * 0b01..Reserved. + * 0b10..8-bit FIFO packing is enabled + * 0b11..16-bit FIFO packing is enabled + */ #define I2S_RCR4_FPACK(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FPACK_SHIFT)) & I2S_RCR4_FPACK_MASK) #define I2S_RCR4_FCOMB_MASK (0xC000000U) #define I2S_RCR4_FCOMB_SHIFT (26U) +/*! FCOMB - FIFO Combine Mode + * 0b00..FIFO combine mode disabled. + * 0b01..FIFO combine mode enabled on FIFO writes (from receive shift registers). + * 0b10..FIFO combine mode enabled on FIFO reads (by software). + * 0b11..FIFO combine mode enabled on FIFO writes (from receive shift registers) and reads (by software). + */ #define I2S_RCR4_FCOMB(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FCOMB_SHIFT)) & I2S_RCR4_FCOMB_MASK) #define I2S_RCR4_FCONT_MASK (0x10000000U) #define I2S_RCR4_FCONT_SHIFT (28U) +/*! FCONT - FIFO Continue on Error + * 0b0..On FIFO error, the SAI will continue from the start of the next frame after the FIFO error flag has been cleared. + * 0b1..On FIFO error, the SAI will continue from the same word that caused the FIFO error to set after the FIFO warning flag has been cleared. + */ #define I2S_RCR4_FCONT(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FCONT_SHIFT)) & I2S_RCR4_FCONT_MASK) +/*! @} */ /*! @name RCR5 - SAI Receive Configuration 5 Register */ +/*! @{ */ #define I2S_RCR5_FBT_MASK (0x1F00U) #define I2S_RCR5_FBT_SHIFT (8U) #define I2S_RCR5_FBT(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_FBT_SHIFT)) & I2S_RCR5_FBT_MASK) @@ -11735,33 +18125,48 @@ typedef struct { #define I2S_RCR5_WNW_MASK (0x1F000000U) #define I2S_RCR5_WNW_SHIFT (24U) #define I2S_RCR5_WNW(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_WNW_SHIFT)) & I2S_RCR5_WNW_MASK) +/*! @} */ /*! @name RDR - SAI Receive Data Register */ +/*! @{ */ #define I2S_RDR_RDR_MASK (0xFFFFFFFFU) #define I2S_RDR_RDR_SHIFT (0U) #define I2S_RDR_RDR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RDR_RDR_SHIFT)) & I2S_RDR_RDR_MASK) +/*! @} */ /* The count of I2S_RDR */ #define I2S_RDR_COUNT (4U) /*! @name RFR - SAI Receive FIFO Register */ +/*! @{ */ #define I2S_RFR_RFP_MASK (0x3FU) #define I2S_RFR_RFP_SHIFT (0U) #define I2S_RFR_RFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RFR_RFP_SHIFT)) & I2S_RFR_RFP_MASK) #define I2S_RFR_RCP_MASK (0x8000U) #define I2S_RFR_RCP_SHIFT (15U) +/*! RCP - Receive Channel Pointer + * 0b0..No effect. + * 0b1..FIFO combine is enabled for FIFO reads and this FIFO will be read on the next FIFO read. + */ #define I2S_RFR_RCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RFR_RCP_SHIFT)) & I2S_RFR_RCP_MASK) #define I2S_RFR_WFP_MASK (0x3F0000U) #define I2S_RFR_WFP_SHIFT (16U) #define I2S_RFR_WFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RFR_WFP_SHIFT)) & I2S_RFR_WFP_MASK) +/*! @} */ /* The count of I2S_RFR */ #define I2S_RFR_COUNT (4U) /*! @name RMR - SAI Receive Mask Register */ +/*! @{ */ #define I2S_RMR_RWM_MASK (0xFFFFFFFFU) #define I2S_RMR_RWM_SHIFT (0U) +/*! RWM - Receive Word Mask + * 0b00000000000000000000000000000000..Word N is enabled. + * 0b00000000000000000000000000000001..Word N is masked. + */ #define I2S_RMR_RWM(x) (((uint32_t)(((uint32_t)(x)) << I2S_RMR_RWM_SHIFT)) & I2S_RMR_RWM_MASK) +/*! @} */ /*! @@ -11822,49 +18227,118 @@ typedef struct { */ /*! @name SW_MUX_CTL_PAD - SW_MUX_CTL_PAD_GPIO_EMC_00 SW MUX Control Register..SW_MUX_CTL_PAD_GPIO_SD_B1_11 SW MUX Control Register */ +/*! @{ */ #define IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_MASK (0x7U) #define IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_SHIFT (0U) +/*! MUX_MODE - MUX Mode Select Field. + * 0b000..Select mux mode: ALT0 mux port: LPI2C4_SCL of instance: lpi2c4 + * 0b001..Select mux mode: ALT1 mux port: CCM_PMIC_READY of instance: ccm + * 0b010..Select mux mode: ALT2 mux port: LPUART1_TX of instance: lpuart1 + * 0b011..Select mux mode: ALT3 mux port: WDOG2_WDOG_B of instance: wdog2 + * 0b100..Select mux mode: ALT4 mux port: FLEXPWM1_PWMX02 of instance: flexpwm1 + * 0b101..Select mux mode: ALT5 mux port: GPIO1_IO12 of instance: gpio1 + * 0b110..Select mux mode: ALT6 mux port: ENET_1588_EVENT1_OUT of instance: enet + * 0b111..Select mux mode: ALT7 mux port: NMI_GLUE_NMI of instance: nmi_glue + */ #define IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_SHIFT)) & IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_MASK) #define IOMUXC_SW_MUX_CTL_PAD_SION_MASK (0x10U) #define IOMUXC_SW_MUX_CTL_PAD_SION_SHIFT (4U) +/*! SION - Software Input On Field. + * 0b1..Force input path of pad GPIO_SD_B1_11 + * 0b0..Input Path is determined by functionality + */ #define IOMUXC_SW_MUX_CTL_PAD_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_MUX_CTL_PAD_SION_SHIFT)) & IOMUXC_SW_MUX_CTL_PAD_SION_MASK) +/*! @} */ /* The count of IOMUXC_SW_MUX_CTL_PAD */ #define IOMUXC_SW_MUX_CTL_PAD_COUNT (124U) /*! @name SW_PAD_CTL_PAD - SW_PAD_CTL_PAD_GPIO_EMC_00 SW PAD Control Register..SW_PAD_CTL_PAD_GPIO_SD_B1_11 SW PAD Control Register */ +/*! @{ */ #define IOMUXC_SW_PAD_CTL_PAD_SRE_MASK (0x1U) #define IOMUXC_SW_PAD_CTL_PAD_SRE_SHIFT (0U) +/*! SRE - Slew Rate Field + * 0b0..Slow Slew Rate + * 0b1..Fast Slew Rate + */ #define IOMUXC_SW_PAD_CTL_PAD_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_SRE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_SRE_MASK) #define IOMUXC_SW_PAD_CTL_PAD_DSE_MASK (0x38U) #define IOMUXC_SW_PAD_CTL_PAD_DSE_SHIFT (3U) +/*! DSE - Drive Strength Field + * 0b000..output driver disabled; + * 0b001..R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + * 0b010..R0/2 + * 0b011..R0/3 + * 0b100..R0/4 + * 0b101..R0/5 + * 0b110..R0/6 + * 0b111..R0/7 + */ #define IOMUXC_SW_PAD_CTL_PAD_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_DSE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_DSE_MASK) #define IOMUXC_SW_PAD_CTL_PAD_SPEED_MASK (0xC0U) #define IOMUXC_SW_PAD_CTL_PAD_SPEED_SHIFT (6U) +/*! SPEED - Speed Field + * 0b00..low(50MHz) + * 0b01..medium(100MHz) + * 0b10..medium(100MHz) + * 0b11..max(200MHz) + */ #define IOMUXC_SW_PAD_CTL_PAD_SPEED(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_SPEED_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_SPEED_MASK) #define IOMUXC_SW_PAD_CTL_PAD_ODE_MASK (0x800U) #define IOMUXC_SW_PAD_CTL_PAD_ODE_SHIFT (11U) +/*! ODE - Open Drain Enable Field + * 0b0..Open Drain Disabled + * 0b1..Open Drain Enabled + */ #define IOMUXC_SW_PAD_CTL_PAD_ODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_ODE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_ODE_MASK) #define IOMUXC_SW_PAD_CTL_PAD_PKE_MASK (0x1000U) #define IOMUXC_SW_PAD_CTL_PAD_PKE_SHIFT (12U) +/*! PKE - Pull / Keep Enable Field + * 0b0..Pull/Keeper Disabled + * 0b1..Pull/Keeper Enabled + */ #define IOMUXC_SW_PAD_CTL_PAD_PKE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_PKE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_PKE_MASK) #define IOMUXC_SW_PAD_CTL_PAD_PUE_MASK (0x2000U) #define IOMUXC_SW_PAD_CTL_PAD_PUE_SHIFT (13U) +/*! PUE - Pull / Keep Select Field + * 0b0..Keeper + * 0b1..Pull + */ #define IOMUXC_SW_PAD_CTL_PAD_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_PUE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_PUE_MASK) #define IOMUXC_SW_PAD_CTL_PAD_PUS_MASK (0xC000U) #define IOMUXC_SW_PAD_CTL_PAD_PUS_SHIFT (14U) +/*! PUS - Pull Up / Down Config. Field + * 0b00..100K Ohm Pull Down + * 0b01..47K Ohm Pull Up + * 0b10..100K Ohm Pull Up + * 0b11..22K Ohm Pull Up + */ #define IOMUXC_SW_PAD_CTL_PAD_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_PUS_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_PUS_MASK) #define IOMUXC_SW_PAD_CTL_PAD_HYS_MASK (0x10000U) #define IOMUXC_SW_PAD_CTL_PAD_HYS_SHIFT (16U) +/*! HYS - Hyst. Enable Field + * 0b0..Hysteresis Disabled + * 0b1..Hysteresis Enabled + */ #define IOMUXC_SW_PAD_CTL_PAD_HYS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_HYS_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_HYS_MASK) +/*! @} */ /* The count of IOMUXC_SW_PAD_CTL_PAD */ #define IOMUXC_SW_PAD_CTL_PAD_COUNT (124U) /*! @name SELECT_INPUT - ANATOP_USB_OTG1_ID_SELECT_INPUT DAISY Register..XBAR1_IN23_SELECT_INPUT DAISY Register */ +/*! @{ */ #define IOMUXC_SELECT_INPUT_DAISY_MASK (0x7U) /* Merged from fields with different position or width, of widths (1, 2, 3), largest definition used */ #define IOMUXC_SELECT_INPUT_DAISY_SHIFT (0U) +/*! DAISY - Selecting Pads Involved in Daisy Chain. + * 0b000..Selecting Pad: GPIO_SD_B1_03 for Mode: ALT6 + * 0b001..Selecting Pad: GPIO_AD_B0_12 for Mode: ALT1 + * 0b010..Selecting Pad: GPIO_AD_B1_01 for Mode: ALT4 + * 0b011..Selecting Pad: GPIO_AD_B1_08 for Mode: ALT3 + * 0b100..Selecting Pad: GPIO_EMC_32 for Mode: ALT3 + */ #define IOMUXC_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SELECT_INPUT_DAISY_SHIFT)) & IOMUXC_SELECT_INPUT_DAISY_MASK) /* Merged from fields with different position or width, of widths (1, 2, 3), largest definition used */ +/*! @} */ /* The count of IOMUXC_SELECT_INPUT */ #define IOMUXC_SELECT_INPUT_COUNT (154U) @@ -11939,542 +18413,1266 @@ typedef struct { */ /*! @name GPR1 - GPR1 General Purpose Register */ +/*! @{ */ #define IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL_MASK (0x7U) #define IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL_SHIFT (0U) +/*! SAI1_MCLK1_SEL + * 0b000..ccm.ssi1_clk_root + * 0b001..ccm.ssi2_clk_root + * 0b010..ccm.ssi3_clk_root + * 0b011..iomux.sai1_ipg_clk_sai_mclk + * 0b100..iomux.sai2_ipg_clk_sai_mclk + * 0b101..iomux.sai3_ipg_clk_sai_mclk + * 0b110..Reserved + * 0b111..Reserved + */ #define IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL_SHIFT)) & IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL_MASK) #define IOMUXC_GPR_GPR1_SAI1_MCLK2_SEL_MASK (0x38U) #define IOMUXC_GPR_GPR1_SAI1_MCLK2_SEL_SHIFT (3U) +/*! SAI1_MCLK2_SEL + * 0b000..ccm.ssi1_clk_root + * 0b001..ccm.ssi2_clk_root + * 0b010..ccm.ssi3_clk_root + * 0b011..iomux.sai1_ipg_clk_sai_mclk + * 0b100..iomux.sai2_ipg_clk_sai_mclk + * 0b101..iomux.sai3_ipg_clk_sai_mclk + * 0b110..Reserved + * 0b111..Reserved + */ #define IOMUXC_GPR_GPR1_SAI1_MCLK2_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI1_MCLK2_SEL_SHIFT)) & IOMUXC_GPR_GPR1_SAI1_MCLK2_SEL_MASK) #define IOMUXC_GPR_GPR1_SAI1_MCLK3_SEL_MASK (0xC0U) #define IOMUXC_GPR_GPR1_SAI1_MCLK3_SEL_SHIFT (6U) +/*! SAI1_MCLK3_SEL + * 0b00..ccm.spdif0_clk_root + * 0b01..iomux.spdif_tx_clk2 + * 0b10..spdif.spdif_srclk + * 0b11..spdif.spdif_outclock + */ #define IOMUXC_GPR_GPR1_SAI1_MCLK3_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI1_MCLK3_SEL_SHIFT)) & IOMUXC_GPR_GPR1_SAI1_MCLK3_SEL_MASK) #define IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL_MASK (0x300U) #define IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL_SHIFT (8U) +/*! SAI2_MCLK3_SEL + * 0b00..ccm.spdif0_clk_root + * 0b01..iomux.spdif_tx_clk2 + * 0b10..spdif.spdif_srclk + * 0b11..spdif.spdif_outclock + */ #define IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL_SHIFT)) & IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL_MASK) #define IOMUXC_GPR_GPR1_SAI3_MCLK3_SEL_MASK (0xC00U) #define IOMUXC_GPR_GPR1_SAI3_MCLK3_SEL_SHIFT (10U) +/*! SAI3_MCLK3_SEL + * 0b00..ccm.spdif0_clk_root + * 0b01..iomux.spdif_tx_clk2 + * 0b10..spdif.spdif_srclk + * 0b11..spdif.spdif_outclock + */ #define IOMUXC_GPR_GPR1_SAI3_MCLK3_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI3_MCLK3_SEL_SHIFT)) & IOMUXC_GPR_GPR1_SAI3_MCLK3_SEL_MASK) #define IOMUXC_GPR_GPR1_GINT_MASK (0x1000U) #define IOMUXC_GPR_GPR1_GINT_SHIFT (12U) +/*! GINT + * 0b0..Global interrupt request is not asserted. + * 0b1..Global interrupt request is asserted. + */ #define IOMUXC_GPR_GPR1_GINT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_GINT_SHIFT)) & IOMUXC_GPR_GPR1_GINT_MASK) #define IOMUXC_GPR_GPR1_ENET1_CLK_SEL_MASK (0x2000U) #define IOMUXC_GPR_GPR1_ENET1_CLK_SEL_SHIFT (13U) +/*! ENET1_CLK_SEL + * 0b0..ENET1 TX reference clock driven by ref_enetpll0. This clock is also output to pins via the IOMUX. ENET_REF_CLK1 function. + * 0b1..Gets ENET1 TX reference clock from the ENET1_TX_CLK pin. In this use case, an external OSC provides the clock for both the external PHY and the internal controller. + */ #define IOMUXC_GPR_GPR1_ENET1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_ENET1_CLK_SEL_SHIFT)) & IOMUXC_GPR_GPR1_ENET1_CLK_SEL_MASK) #define IOMUXC_GPR_GPR1_USB_EXP_MODE_MASK (0x8000U) #define IOMUXC_GPR_GPR1_USB_EXP_MODE_SHIFT (15U) +/*! USB_EXP_MODE + * 0b0..Exposure mode is disabled. + * 0b1..Exposure mode is enabled. + */ #define IOMUXC_GPR_GPR1_USB_EXP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_USB_EXP_MODE_SHIFT)) & IOMUXC_GPR_GPR1_USB_EXP_MODE_MASK) #define IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK (0x20000U) #define IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_SHIFT (17U) +/*! ENET1_TX_CLK_DIR + * 0b0..ENET1_TX_CLK output driver is disabled and ENET_REF_CLK1 is a clock input. + * 0b1..ENET1_TX_CLK output driver is enabled and ENET_REF_CLK1 is an output driven by ref_enetpll0. + */ #define IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_SHIFT)) & IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK) #define IOMUXC_GPR_GPR1_SAI1_MCLK_DIR_MASK (0x80000U) #define IOMUXC_GPR_GPR1_SAI1_MCLK_DIR_SHIFT (19U) +/*! SAI1_MCLK_DIR + * 0b0..sai1.MCLK is input signal + * 0b1..sai1.MCLK is output signal + */ #define IOMUXC_GPR_GPR1_SAI1_MCLK_DIR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI1_MCLK_DIR_SHIFT)) & IOMUXC_GPR_GPR1_SAI1_MCLK_DIR_MASK) #define IOMUXC_GPR_GPR1_SAI2_MCLK_DIR_MASK (0x100000U) #define IOMUXC_GPR_GPR1_SAI2_MCLK_DIR_SHIFT (20U) +/*! SAI2_MCLK_DIR + * 0b0..sai2.MCLK is input signal + * 0b1..sai2.MCLK is output signal + */ #define IOMUXC_GPR_GPR1_SAI2_MCLK_DIR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI2_MCLK_DIR_SHIFT)) & IOMUXC_GPR_GPR1_SAI2_MCLK_DIR_MASK) #define IOMUXC_GPR_GPR1_SAI3_MCLK_DIR_MASK (0x200000U) #define IOMUXC_GPR_GPR1_SAI3_MCLK_DIR_SHIFT (21U) +/*! SAI3_MCLK_DIR + * 0b0..sai3.MCLK is input signal + * 0b1..sai3.MCLK is output signal + */ #define IOMUXC_GPR_GPR1_SAI3_MCLK_DIR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI3_MCLK_DIR_SHIFT)) & IOMUXC_GPR_GPR1_SAI3_MCLK_DIR_MASK) #define IOMUXC_GPR_GPR1_EXC_MON_MASK (0x400000U) #define IOMUXC_GPR_GPR1_EXC_MON_SHIFT (22U) +/*! EXC_MON + * 0b0..OKAY response + * 0b1..SLVError response + */ #define IOMUXC_GPR_GPR1_EXC_MON(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_EXC_MON_SHIFT)) & IOMUXC_GPR_GPR1_EXC_MON_MASK) #define IOMUXC_GPR_GPR1_ENET_IPG_CLK_S_EN_MASK (0x800000U) #define IOMUXC_GPR_GPR1_ENET_IPG_CLK_S_EN_SHIFT (23U) +/*! ENET_IPG_CLK_S_EN + * 0b0..ipg_clk_s is gated when there is no IPS access + * 0b1..ipg_clk_s is always on + */ #define IOMUXC_GPR_GPR1_ENET_IPG_CLK_S_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_ENET_IPG_CLK_S_EN_SHIFT)) & IOMUXC_GPR_GPR1_ENET_IPG_CLK_S_EN_MASK) #define IOMUXC_GPR_GPR1_CM7_FORCE_HCLK_EN_MASK (0x80000000U) #define IOMUXC_GPR_GPR1_CM7_FORCE_HCLK_EN_SHIFT (31U) +/*! CM7_FORCE_HCLK_EN + * 0b0..AHB clock is not running (gated) + * 0b1..AHB clock is running (enabled) + */ #define IOMUXC_GPR_GPR1_CM7_FORCE_HCLK_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_CM7_FORCE_HCLK_EN_SHIFT)) & IOMUXC_GPR_GPR1_CM7_FORCE_HCLK_EN_MASK) +/*! @} */ /*! @name GPR2 - GPR2 General Purpose Register */ +/*! @{ */ #define IOMUXC_GPR_GPR2_L2_MEM_EN_POWERSAVING_MASK (0x1000U) #define IOMUXC_GPR_GPR2_L2_MEM_EN_POWERSAVING_SHIFT (12U) +/*! L2_MEM_EN_POWERSAVING + * 0b0..none memory power saving features enabled, SHUTDOWN/DEEPSLEEP/LIGHTSLEEP will have no effect + * 0b1..memory power saving features enabled, set SHUTDOWN/DEEPSLEEP/LIGHTSLEEP(priority high to low) to enable power saving levels + */ #define IOMUXC_GPR_GPR2_L2_MEM_EN_POWERSAVING(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_L2_MEM_EN_POWERSAVING_SHIFT)) & IOMUXC_GPR_GPR2_L2_MEM_EN_POWERSAVING_MASK) #define IOMUXC_GPR_GPR2_L2_MEM_DEEPSLEEP_MASK (0x4000U) #define IOMUXC_GPR_GPR2_L2_MEM_DEEPSLEEP_SHIFT (14U) +/*! L2_MEM_DEEPSLEEP + * 0b0..no force sleep control supported, memory deep sleep mode only entered when whole system in stop mode + * 0b1..force memory into deep sleep mode + */ #define IOMUXC_GPR_GPR2_L2_MEM_DEEPSLEEP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_L2_MEM_DEEPSLEEP_SHIFT)) & IOMUXC_GPR_GPR2_L2_MEM_DEEPSLEEP_MASK) #define IOMUXC_GPR_GPR2_MQS_CLK_DIV_MASK (0xFF0000U) #define IOMUXC_GPR_GPR2_MQS_CLK_DIV_SHIFT (16U) +/*! MQS_CLK_DIV + * 0b00000000..mclk frequency = hmclk frequency + * 0b00000001..mclk frequency = 1/2 * hmclk frequency + * 0b00000010..mclk frequency = 1/3 * hmclk frequency + * 0b11111111..mclk frequency = 1/256 * hmclk frequency + */ #define IOMUXC_GPR_GPR2_MQS_CLK_DIV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_MQS_CLK_DIV_SHIFT)) & IOMUXC_GPR_GPR2_MQS_CLK_DIV_MASK) #define IOMUXC_GPR_GPR2_MQS_SW_RST_MASK (0x1000000U) #define IOMUXC_GPR_GPR2_MQS_SW_RST_SHIFT (24U) +/*! MQS_SW_RST + * 0b0..Exit software reset for MQS + * 0b1..Enable software reset for MQS + */ #define IOMUXC_GPR_GPR2_MQS_SW_RST(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_MQS_SW_RST_SHIFT)) & IOMUXC_GPR_GPR2_MQS_SW_RST_MASK) #define IOMUXC_GPR_GPR2_MQS_EN_MASK (0x2000000U) #define IOMUXC_GPR_GPR2_MQS_EN_SHIFT (25U) +/*! MQS_EN + * 0b0..Disable MQS + * 0b1..Enable MQS + */ #define IOMUXC_GPR_GPR2_MQS_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_MQS_EN_SHIFT)) & IOMUXC_GPR_GPR2_MQS_EN_MASK) #define IOMUXC_GPR_GPR2_MQS_OVERSAMPLE_MASK (0x4000000U) #define IOMUXC_GPR_GPR2_MQS_OVERSAMPLE_SHIFT (26U) +/*! MQS_OVERSAMPLE + * 0b0..32 + * 0b1..64 + */ #define IOMUXC_GPR_GPR2_MQS_OVERSAMPLE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_MQS_OVERSAMPLE_SHIFT)) & IOMUXC_GPR_GPR2_MQS_OVERSAMPLE_MASK) #define IOMUXC_GPR_GPR2_QTIMER1_TMR_CNTS_FREEZE_MASK (0x10000000U) #define IOMUXC_GPR_GPR2_QTIMER1_TMR_CNTS_FREEZE_SHIFT (28U) +/*! QTIMER1_TMR_CNTS_FREEZE + * 0b0..timer counter work normally + * 0b1..reset counter and ouput flags + */ #define IOMUXC_GPR_GPR2_QTIMER1_TMR_CNTS_FREEZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_QTIMER1_TMR_CNTS_FREEZE_SHIFT)) & IOMUXC_GPR_GPR2_QTIMER1_TMR_CNTS_FREEZE_MASK) #define IOMUXC_GPR_GPR2_QTIMER2_TMR_CNTS_FREEZE_MASK (0x20000000U) #define IOMUXC_GPR_GPR2_QTIMER2_TMR_CNTS_FREEZE_SHIFT (29U) +/*! QTIMER2_TMR_CNTS_FREEZE + * 0b0..timer counter work normally + * 0b1..reset counter and ouput flags + */ #define IOMUXC_GPR_GPR2_QTIMER2_TMR_CNTS_FREEZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_QTIMER2_TMR_CNTS_FREEZE_SHIFT)) & IOMUXC_GPR_GPR2_QTIMER2_TMR_CNTS_FREEZE_MASK) #define IOMUXC_GPR_GPR2_QTIMER3_TMR_CNTS_FREEZE_MASK (0x40000000U) #define IOMUXC_GPR_GPR2_QTIMER3_TMR_CNTS_FREEZE_SHIFT (30U) +/*! QTIMER3_TMR_CNTS_FREEZE + * 0b0..timer counter work normally + * 0b1..reset counter and ouput flags + */ #define IOMUXC_GPR_GPR2_QTIMER3_TMR_CNTS_FREEZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_QTIMER3_TMR_CNTS_FREEZE_SHIFT)) & IOMUXC_GPR_GPR2_QTIMER3_TMR_CNTS_FREEZE_MASK) #define IOMUXC_GPR_GPR2_QTIMER4_TMR_CNTS_FREEZE_MASK (0x80000000U) #define IOMUXC_GPR_GPR2_QTIMER4_TMR_CNTS_FREEZE_SHIFT (31U) +/*! QTIMER4_TMR_CNTS_FREEZE + * 0b0..timer counter work normally + * 0b1..reset counter and ouput flags + */ #define IOMUXC_GPR_GPR2_QTIMER4_TMR_CNTS_FREEZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_QTIMER4_TMR_CNTS_FREEZE_SHIFT)) & IOMUXC_GPR_GPR2_QTIMER4_TMR_CNTS_FREEZE_MASK) +/*! @} */ /*! @name GPR3 - GPR3 General Purpose Register */ +/*! @{ */ #define IOMUXC_GPR_GPR3_OCRAM_CTL_MASK (0xFU) #define IOMUXC_GPR_GPR3_OCRAM_CTL_SHIFT (0U) #define IOMUXC_GPR_GPR3_OCRAM_CTL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR3_OCRAM_CTL_SHIFT)) & IOMUXC_GPR_GPR3_OCRAM_CTL_MASK) #define IOMUXC_GPR_GPR3_DCP_KEY_SEL_MASK (0x10U) #define IOMUXC_GPR_GPR3_DCP_KEY_SEL_SHIFT (4U) +/*! DCP_KEY_SEL + * 0b0..Select [127:0] from snvs/ocotp key as dcp key + * 0b1..Select [255:128] from snvs/ocotp key as dcp key + */ #define IOMUXC_GPR_GPR3_DCP_KEY_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR3_DCP_KEY_SEL_SHIFT)) & IOMUXC_GPR_GPR3_DCP_KEY_SEL_MASK) #define IOMUXC_GPR_GPR3_OCRAM_STATUS_MASK (0xF0000U) #define IOMUXC_GPR_GPR3_OCRAM_STATUS_SHIFT (16U) +/*! OCRAM_STATUS + * 0b0000..read data pipeline configuration valid + * 0b0001..read data pipeline control bit changed + */ #define IOMUXC_GPR_GPR3_OCRAM_STATUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR3_OCRAM_STATUS_SHIFT)) & IOMUXC_GPR_GPR3_OCRAM_STATUS_MASK) +/*! @} */ /*! @name GPR4 - GPR4 General Purpose Register */ +/*! @{ */ #define IOMUXC_GPR_GPR4_EDMA_STOP_REQ_MASK (0x1U) #define IOMUXC_GPR_GPR4_EDMA_STOP_REQ_SHIFT (0U) +/*! EDMA_STOP_REQ + * 0b0..stop request off + * 0b1..stop request on + */ #define IOMUXC_GPR_GPR4_EDMA_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_EDMA_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_EDMA_STOP_REQ_MASK) #define IOMUXC_GPR_GPR4_CAN1_STOP_REQ_MASK (0x2U) #define IOMUXC_GPR_GPR4_CAN1_STOP_REQ_SHIFT (1U) +/*! CAN1_STOP_REQ + * 0b0..stop request off + * 0b1..stop request on + */ #define IOMUXC_GPR_GPR4_CAN1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_CAN1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_CAN1_STOP_REQ_MASK) #define IOMUXC_GPR_GPR4_CAN2_STOP_REQ_MASK (0x4U) #define IOMUXC_GPR_GPR4_CAN2_STOP_REQ_SHIFT (2U) +/*! CAN2_STOP_REQ + * 0b0..stop request off + * 0b1..stop request on + */ #define IOMUXC_GPR_GPR4_CAN2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_CAN2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_CAN2_STOP_REQ_MASK) #define IOMUXC_GPR_GPR4_TRNG_STOP_REQ_MASK (0x8U) #define IOMUXC_GPR_GPR4_TRNG_STOP_REQ_SHIFT (3U) +/*! TRNG_STOP_REQ + * 0b0..stop request off + * 0b1..stop request on + */ #define IOMUXC_GPR_GPR4_TRNG_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_TRNG_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_TRNG_STOP_REQ_MASK) #define IOMUXC_GPR_GPR4_ENET_STOP_REQ_MASK (0x10U) #define IOMUXC_GPR_GPR4_ENET_STOP_REQ_SHIFT (4U) +/*! ENET_STOP_REQ + * 0b0..stop request off + * 0b1..stop request on + */ #define IOMUXC_GPR_GPR4_ENET_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_ENET_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_ENET_STOP_REQ_MASK) #define IOMUXC_GPR_GPR4_SAI1_STOP_REQ_MASK (0x20U) #define IOMUXC_GPR_GPR4_SAI1_STOP_REQ_SHIFT (5U) +/*! SAI1_STOP_REQ + * 0b0..stop request off + * 0b1..stop request on + */ #define IOMUXC_GPR_GPR4_SAI1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SAI1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_SAI1_STOP_REQ_MASK) #define IOMUXC_GPR_GPR4_SAI2_STOP_REQ_MASK (0x40U) #define IOMUXC_GPR_GPR4_SAI2_STOP_REQ_SHIFT (6U) +/*! SAI2_STOP_REQ + * 0b0..stop request off + * 0b1..stop request on + */ #define IOMUXC_GPR_GPR4_SAI2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SAI2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_SAI2_STOP_REQ_MASK) #define IOMUXC_GPR_GPR4_SAI3_STOP_REQ_MASK (0x80U) #define IOMUXC_GPR_GPR4_SAI3_STOP_REQ_SHIFT (7U) +/*! SAI3_STOP_REQ + * 0b0..stop request off + * 0b1..stop request on + */ #define IOMUXC_GPR_GPR4_SAI3_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SAI3_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_SAI3_STOP_REQ_MASK) #define IOMUXC_GPR_GPR4_SEMC_STOP_REQ_MASK (0x200U) #define IOMUXC_GPR_GPR4_SEMC_STOP_REQ_SHIFT (9U) +/*! SEMC_STOP_REQ + * 0b0..stop request off + * 0b1..stop request on + */ #define IOMUXC_GPR_GPR4_SEMC_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SEMC_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_SEMC_STOP_REQ_MASK) #define IOMUXC_GPR_GPR4_PIT_STOP_REQ_MASK (0x400U) #define IOMUXC_GPR_GPR4_PIT_STOP_REQ_SHIFT (10U) +/*! PIT_STOP_REQ + * 0b0..stop request off + * 0b1..stop request on + */ #define IOMUXC_GPR_GPR4_PIT_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_PIT_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_PIT_STOP_REQ_MASK) #define IOMUXC_GPR_GPR4_FLEXSPI_STOP_REQ_MASK (0x800U) #define IOMUXC_GPR_GPR4_FLEXSPI_STOP_REQ_SHIFT (11U) +/*! FLEXSPI_STOP_REQ + * 0b0..stop request off + * 0b1..stop request on + */ #define IOMUXC_GPR_GPR4_FLEXSPI_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_FLEXSPI_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_FLEXSPI_STOP_REQ_MASK) #define IOMUXC_GPR_GPR4_FLEXIO1_STOP_REQ_MASK (0x1000U) #define IOMUXC_GPR_GPR4_FLEXIO1_STOP_REQ_SHIFT (12U) +/*! FLEXIO1_STOP_REQ + * 0b0..stop request off + * 0b1..stop request on + */ #define IOMUXC_GPR_GPR4_FLEXIO1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_FLEXIO1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_FLEXIO1_STOP_REQ_MASK) #define IOMUXC_GPR_GPR4_FLEXIO2_STOP_REQ_MASK (0x2000U) #define IOMUXC_GPR_GPR4_FLEXIO2_STOP_REQ_SHIFT (13U) +/*! FLEXIO2_STOP_REQ + * 0b0..stop request off + * 0b1..stop request on + */ #define IOMUXC_GPR_GPR4_FLEXIO2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_FLEXIO2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_FLEXIO2_STOP_REQ_MASK) #define IOMUXC_GPR_GPR4_EDMA_STOP_ACK_MASK (0x10000U) #define IOMUXC_GPR_GPR4_EDMA_STOP_ACK_SHIFT (16U) +/*! EDMA_STOP_ACK + * 0b0..EDMA stop acknowledge is not asserted + * 0b1..EDMA stop acknowledge is asserted (EDMA is in STOP mode). + */ #define IOMUXC_GPR_GPR4_EDMA_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_EDMA_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_EDMA_STOP_ACK_MASK) #define IOMUXC_GPR_GPR4_CAN1_STOP_ACK_MASK (0x20000U) #define IOMUXC_GPR_GPR4_CAN1_STOP_ACK_SHIFT (17U) +/*! CAN1_STOP_ACK + * 0b0..CAN1 stop acknowledge is not asserted + * 0b1..CAN1 stop acknowledge is asserted + */ #define IOMUXC_GPR_GPR4_CAN1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_CAN1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_CAN1_STOP_ACK_MASK) #define IOMUXC_GPR_GPR4_CAN2_STOP_ACK_MASK (0x40000U) #define IOMUXC_GPR_GPR4_CAN2_STOP_ACK_SHIFT (18U) +/*! CAN2_STOP_ACK + * 0b0..CAN2 stop acknowledge is not asserted + * 0b1..CAN2 stop acknowledge is asserted + */ #define IOMUXC_GPR_GPR4_CAN2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_CAN2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_CAN2_STOP_ACK_MASK) #define IOMUXC_GPR_GPR4_TRNG_STOP_ACK_MASK (0x80000U) #define IOMUXC_GPR_GPR4_TRNG_STOP_ACK_SHIFT (19U) +/*! TRNG_STOP_ACK + * 0b0..TRNG stop acknowledge is not asserted + * 0b1..TRNG stop acknowledge is asserted + */ #define IOMUXC_GPR_GPR4_TRNG_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_TRNG_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_TRNG_STOP_ACK_MASK) #define IOMUXC_GPR_GPR4_ENET_STOP_ACK_MASK (0x100000U) #define IOMUXC_GPR_GPR4_ENET_STOP_ACK_SHIFT (20U) +/*! ENET_STOP_ACK + * 0b0..ENET stop acknowledge is not asserted + * 0b1..ENET stop acknowledge is asserted + */ #define IOMUXC_GPR_GPR4_ENET_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_ENET_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_ENET_STOP_ACK_MASK) #define IOMUXC_GPR_GPR4_SAI1_STOP_ACK_MASK (0x200000U) #define IOMUXC_GPR_GPR4_SAI1_STOP_ACK_SHIFT (21U) +/*! SAI1_STOP_ACK + * 0b0..SAI1 stop acknowledge is not asserted + * 0b1..SAI1 stop acknowledge is asserted + */ #define IOMUXC_GPR_GPR4_SAI1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SAI1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_SAI1_STOP_ACK_MASK) #define IOMUXC_GPR_GPR4_SAI2_STOP_ACK_MASK (0x400000U) #define IOMUXC_GPR_GPR4_SAI2_STOP_ACK_SHIFT (22U) +/*! SAI2_STOP_ACK + * 0b0..SAI2 stop acknowledge is not asserted + * 0b1..SAI2 stop acknowledge is asserted + */ #define IOMUXC_GPR_GPR4_SAI2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SAI2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_SAI2_STOP_ACK_MASK) #define IOMUXC_GPR_GPR4_SAI3_STOP_ACK_MASK (0x800000U) #define IOMUXC_GPR_GPR4_SAI3_STOP_ACK_SHIFT (23U) +/*! SAI3_STOP_ACK + * 0b0..SAI3 stop acknowledge is not asserted + * 0b1..SAI3 stop acknowledge is asserted + */ #define IOMUXC_GPR_GPR4_SAI3_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SAI3_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_SAI3_STOP_ACK_MASK) #define IOMUXC_GPR_GPR4_SEMC_STOP_ACK_MASK (0x2000000U) #define IOMUXC_GPR_GPR4_SEMC_STOP_ACK_SHIFT (25U) +/*! SEMC_STOP_ACK + * 0b0..SEMC stop acknowledge is not asserted + * 0b1..SEMC stop acknowledge is asserted + */ #define IOMUXC_GPR_GPR4_SEMC_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SEMC_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_SEMC_STOP_ACK_MASK) #define IOMUXC_GPR_GPR4_PIT_STOP_ACK_MASK (0x4000000U) #define IOMUXC_GPR_GPR4_PIT_STOP_ACK_SHIFT (26U) +/*! PIT_STOP_ACK + * 0b0..PIT stop acknowledge is not asserted + * 0b1..PIT stop acknowledge is asserted + */ #define IOMUXC_GPR_GPR4_PIT_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_PIT_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_PIT_STOP_ACK_MASK) #define IOMUXC_GPR_GPR4_FLEXSPI_STOP_ACK_MASK (0x8000000U) #define IOMUXC_GPR_GPR4_FLEXSPI_STOP_ACK_SHIFT (27U) +/*! FLEXSPI_STOP_ACK + * 0b0..FLEXSPI stop acknowledge is not asserted + * 0b1..FLEXSPI stop acknowledge is asserted + */ #define IOMUXC_GPR_GPR4_FLEXSPI_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_FLEXSPI_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_FLEXSPI_STOP_ACK_MASK) #define IOMUXC_GPR_GPR4_FLEXIO1_STOP_ACK_MASK (0x10000000U) #define IOMUXC_GPR_GPR4_FLEXIO1_STOP_ACK_SHIFT (28U) +/*! FLEXIO1_STOP_ACK + * 0b0..FLEXIO1 stop acknowledge is not asserted + * 0b1..FLEXIO1 stop acknowledge is asserted + */ #define IOMUXC_GPR_GPR4_FLEXIO1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_FLEXIO1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_FLEXIO1_STOP_ACK_MASK) #define IOMUXC_GPR_GPR4_FLEXIO2_STOP_ACK_MASK (0x20000000U) #define IOMUXC_GPR_GPR4_FLEXIO2_STOP_ACK_SHIFT (29U) +/*! FLEXIO2_STOP_ACK + * 0b0..FLEXIO2 stop acknowledge is not asserted + * 0b1..FLEXIO2 stop acknowledge is asserted (FLEXIO2 is in STOP mode) + */ #define IOMUXC_GPR_GPR4_FLEXIO2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_FLEXIO2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_FLEXIO2_STOP_ACK_MASK) +/*! @} */ /*! @name GPR5 - GPR5 General Purpose Register */ +/*! @{ */ #define IOMUXC_GPR_GPR5_WDOG1_MASK_MASK (0x40U) #define IOMUXC_GPR_GPR5_WDOG1_MASK_SHIFT (6U) +/*! WDOG1_MASK + * 0b0..WDOG1 Timeout behaves normally + * 0b1..WDOG1 Timeout is masked + */ #define IOMUXC_GPR_GPR5_WDOG1_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_WDOG1_MASK_SHIFT)) & IOMUXC_GPR_GPR5_WDOG1_MASK_MASK) #define IOMUXC_GPR_GPR5_WDOG2_MASK_MASK (0x80U) #define IOMUXC_GPR_GPR5_WDOG2_MASK_SHIFT (7U) +/*! WDOG2_MASK + * 0b0..WDOG2 Timeout behaves normally + * 0b1..WDOG2 Timeout is masked + */ #define IOMUXC_GPR_GPR5_WDOG2_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_WDOG2_MASK_SHIFT)) & IOMUXC_GPR_GPR5_WDOG2_MASK_MASK) #define IOMUXC_GPR_GPR5_GPT2_CAPIN1_SEL_MASK (0x800000U) #define IOMUXC_GPR_GPR5_GPT2_CAPIN1_SEL_SHIFT (23U) +/*! GPT2_CAPIN1_SEL + * 0b0..source from pad + * 0b1..source from enet1.ipp_do_mac0_timer[3] + */ #define IOMUXC_GPR_GPR5_GPT2_CAPIN1_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_GPT2_CAPIN1_SEL_SHIFT)) & IOMUXC_GPR_GPR5_GPT2_CAPIN1_SEL_MASK) -#define IOMUXC_GPR_GPR5_GPT2_CAPIN2_SEL_MASK (0x1000000U) -#define IOMUXC_GPR_GPR5_GPT2_CAPIN2_SEL_SHIFT (24U) -#define IOMUXC_GPR_GPR5_GPT2_CAPIN2_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_GPT2_CAPIN2_SEL_SHIFT)) & IOMUXC_GPR_GPR5_GPT2_CAPIN2_SEL_MASK) #define IOMUXC_GPR_GPR5_ENET_EVENT3IN_SEL_MASK (0x2000000U) #define IOMUXC_GPR_GPR5_ENET_EVENT3IN_SEL_SHIFT (25U) +/*! ENET_EVENT3IN_SEL + * 0b0..event3 source input from pad + * 0b1..event3 source input from gpt2.ipp_do_cmpout1 + */ #define IOMUXC_GPR_GPR5_ENET_EVENT3IN_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_ENET_EVENT3IN_SEL_SHIFT)) & IOMUXC_GPR_GPR5_ENET_EVENT3IN_SEL_MASK) #define IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK (0x10000000U) #define IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_SHIFT (28U) +/*! VREF_1M_CLK_GPT1 + * 0b0..GPT1 ipg_clk_highfreq driven by IPG_PERCLK + * 0b1..GPT1 ipg_clk_highfreq driven by anatop 1 MHz clock + */ #define IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_SHIFT)) & IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK) #define IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK (0x20000000U) #define IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_SHIFT (29U) +/*! VREF_1M_CLK_GPT2 + * 0b0..GPT2 ipg_clk_highfreq driven by IPG_PERCLK + * 0b1..GPT2 ipg_clk_highfreq driven by anatop 1 MHz clock + */ #define IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_SHIFT)) & IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK) +/*! @} */ /*! @name GPR6 - GPR6 General Purpose Register */ +/*! @{ */ #define IOMUXC_GPR_GPR6_QTIMER1_TRM0_INPUT_SEL_MASK (0x1U) #define IOMUXC_GPR_GPR6_QTIMER1_TRM0_INPUT_SEL_SHIFT (0U) +/*! QTIMER1_TRM0_INPUT_SEL + * 0b0..input from IOMUX + * 0b1..input from XBAR + */ #define IOMUXC_GPR_GPR6_QTIMER1_TRM0_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER1_TRM0_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER1_TRM0_INPUT_SEL_MASK) #define IOMUXC_GPR_GPR6_QTIMER1_TRM1_INPUT_SEL_MASK (0x2U) #define IOMUXC_GPR_GPR6_QTIMER1_TRM1_INPUT_SEL_SHIFT (1U) +/*! QTIMER1_TRM1_INPUT_SEL + * 0b0..input from IOMUX + * 0b1..input from XBAR + */ #define IOMUXC_GPR_GPR6_QTIMER1_TRM1_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER1_TRM1_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER1_TRM1_INPUT_SEL_MASK) #define IOMUXC_GPR_GPR6_QTIMER1_TRM2_INPUT_SEL_MASK (0x4U) #define IOMUXC_GPR_GPR6_QTIMER1_TRM2_INPUT_SEL_SHIFT (2U) +/*! QTIMER1_TRM2_INPUT_SEL + * 0b0..input from IOMUX + * 0b1..input from XBAR + */ #define IOMUXC_GPR_GPR6_QTIMER1_TRM2_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER1_TRM2_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER1_TRM2_INPUT_SEL_MASK) #define IOMUXC_GPR_GPR6_QTIMER1_TRM3_INPUT_SEL_MASK (0x8U) #define IOMUXC_GPR_GPR6_QTIMER1_TRM3_INPUT_SEL_SHIFT (3U) +/*! QTIMER1_TRM3_INPUT_SEL + * 0b0..input from IOMUX + * 0b1..input from XBAR + */ #define IOMUXC_GPR_GPR6_QTIMER1_TRM3_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER1_TRM3_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER1_TRM3_INPUT_SEL_MASK) #define IOMUXC_GPR_GPR6_QTIMER2_TRM0_INPUT_SEL_MASK (0x10U) #define IOMUXC_GPR_GPR6_QTIMER2_TRM0_INPUT_SEL_SHIFT (4U) +/*! QTIMER2_TRM0_INPUT_SEL + * 0b0..input from IOMUX + * 0b1..input from XBAR + */ #define IOMUXC_GPR_GPR6_QTIMER2_TRM0_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER2_TRM0_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER2_TRM0_INPUT_SEL_MASK) #define IOMUXC_GPR_GPR6_QTIMER2_TRM1_INPUT_SEL_MASK (0x20U) #define IOMUXC_GPR_GPR6_QTIMER2_TRM1_INPUT_SEL_SHIFT (5U) +/*! QTIMER2_TRM1_INPUT_SEL + * 0b0..input from IOMUX + * 0b1..input from XBAR + */ #define IOMUXC_GPR_GPR6_QTIMER2_TRM1_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER2_TRM1_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER2_TRM1_INPUT_SEL_MASK) #define IOMUXC_GPR_GPR6_QTIMER2_TRM2_INPUT_SEL_MASK (0x40U) #define IOMUXC_GPR_GPR6_QTIMER2_TRM2_INPUT_SEL_SHIFT (6U) +/*! QTIMER2_TRM2_INPUT_SEL + * 0b0..input from IOMUX + * 0b1..input from XBAR + */ #define IOMUXC_GPR_GPR6_QTIMER2_TRM2_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER2_TRM2_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER2_TRM2_INPUT_SEL_MASK) #define IOMUXC_GPR_GPR6_QTIMER2_TRM3_INPUT_SEL_MASK (0x80U) #define IOMUXC_GPR_GPR6_QTIMER2_TRM3_INPUT_SEL_SHIFT (7U) +/*! QTIMER2_TRM3_INPUT_SEL + * 0b0..input from IOMUX + * 0b1..input from XBAR + */ #define IOMUXC_GPR_GPR6_QTIMER2_TRM3_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER2_TRM3_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER2_TRM3_INPUT_SEL_MASK) #define IOMUXC_GPR_GPR6_QTIMER3_TRM0_INPUT_SEL_MASK (0x100U) #define IOMUXC_GPR_GPR6_QTIMER3_TRM0_INPUT_SEL_SHIFT (8U) +/*! QTIMER3_TRM0_INPUT_SEL + * 0b0..input from IOMUX + * 0b1..input from XBAR + */ #define IOMUXC_GPR_GPR6_QTIMER3_TRM0_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER3_TRM0_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER3_TRM0_INPUT_SEL_MASK) #define IOMUXC_GPR_GPR6_QTIMER3_TRM1_INPUT_SEL_MASK (0x200U) #define IOMUXC_GPR_GPR6_QTIMER3_TRM1_INPUT_SEL_SHIFT (9U) +/*! QTIMER3_TRM1_INPUT_SEL + * 0b0..input from IOMUX + * 0b1..input from XBAR + */ #define IOMUXC_GPR_GPR6_QTIMER3_TRM1_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER3_TRM1_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER3_TRM1_INPUT_SEL_MASK) #define IOMUXC_GPR_GPR6_QTIMER3_TRM2_INPUT_SEL_MASK (0x400U) #define IOMUXC_GPR_GPR6_QTIMER3_TRM2_INPUT_SEL_SHIFT (10U) +/*! QTIMER3_TRM2_INPUT_SEL + * 0b0..input from IOMUX + * 0b1..input from XBAR + */ #define IOMUXC_GPR_GPR6_QTIMER3_TRM2_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER3_TRM2_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER3_TRM2_INPUT_SEL_MASK) #define IOMUXC_GPR_GPR6_QTIMER3_TRM3_INPUT_SEL_MASK (0x800U) #define IOMUXC_GPR_GPR6_QTIMER3_TRM3_INPUT_SEL_SHIFT (11U) +/*! QTIMER3_TRM3_INPUT_SEL + * 0b0..input from IOMUX + * 0b1..input from XBAR + */ #define IOMUXC_GPR_GPR6_QTIMER3_TRM3_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER3_TRM3_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER3_TRM3_INPUT_SEL_MASK) #define IOMUXC_GPR_GPR6_QTIMER4_TRM0_INPUT_SEL_MASK (0x1000U) #define IOMUXC_GPR_GPR6_QTIMER4_TRM0_INPUT_SEL_SHIFT (12U) +/*! QTIMER4_TRM0_INPUT_SEL + * 0b0..input from IOMUX + * 0b1..input from XBAR + */ #define IOMUXC_GPR_GPR6_QTIMER4_TRM0_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER4_TRM0_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER4_TRM0_INPUT_SEL_MASK) #define IOMUXC_GPR_GPR6_QTIMER4_TRM1_INPUT_SEL_MASK (0x2000U) #define IOMUXC_GPR_GPR6_QTIMER4_TRM1_INPUT_SEL_SHIFT (13U) +/*! QTIMER4_TRM1_INPUT_SEL + * 0b0..input from IOMUX + * 0b1..input from XBAR + */ #define IOMUXC_GPR_GPR6_QTIMER4_TRM1_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER4_TRM1_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER4_TRM1_INPUT_SEL_MASK) #define IOMUXC_GPR_GPR6_QTIMER4_TRM2_INPUT_SEL_MASK (0x4000U) #define IOMUXC_GPR_GPR6_QTIMER4_TRM2_INPUT_SEL_SHIFT (14U) +/*! QTIMER4_TRM2_INPUT_SEL + * 0b0..input from IOMUX + * 0b1..input from XBAR + */ #define IOMUXC_GPR_GPR6_QTIMER4_TRM2_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER4_TRM2_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER4_TRM2_INPUT_SEL_MASK) #define IOMUXC_GPR_GPR6_QTIMER4_TRM3_INPUT_SEL_MASK (0x8000U) #define IOMUXC_GPR_GPR6_QTIMER4_TRM3_INPUT_SEL_SHIFT (15U) +/*! QTIMER4_TRM3_INPUT_SEL + * 0b0..input from IOMUX + * 0b1..input from XBAR + */ #define IOMUXC_GPR_GPR6_QTIMER4_TRM3_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER4_TRM3_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER4_TRM3_INPUT_SEL_MASK) #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_4_MASK (0x10000U) #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_4_SHIFT (16U) +/*! IOMUXC_XBAR_DIR_SEL_4 + * 0b0..XBAR_INOUT as input + * 0b1..XBAR_INOUT as output + */ #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_4_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_4_MASK) #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_5_MASK (0x20000U) #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_5_SHIFT (17U) +/*! IOMUXC_XBAR_DIR_SEL_5 + * 0b0..XBAR_INOUT as input + * 0b1..XBAR_INOUT as output + */ #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_5(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_5_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_5_MASK) #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_6_MASK (0x40000U) #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_6_SHIFT (18U) +/*! IOMUXC_XBAR_DIR_SEL_6 + * 0b0..XBAR_INOUT as input + * 0b1..XBAR_INOUT as output + */ #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_6(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_6_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_6_MASK) #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_7_MASK (0x80000U) #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_7_SHIFT (19U) +/*! IOMUXC_XBAR_DIR_SEL_7 + * 0b0..XBAR_INOUT as input + * 0b1..XBAR_INOUT as output + */ #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_7(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_7_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_7_MASK) #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_8_MASK (0x100000U) #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_8_SHIFT (20U) +/*! IOMUXC_XBAR_DIR_SEL_8 + * 0b0..XBAR_INOUT as input + * 0b1..XBAR_INOUT as output + */ #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_8(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_8_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_8_MASK) #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_9_MASK (0x200000U) #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_9_SHIFT (21U) +/*! IOMUXC_XBAR_DIR_SEL_9 + * 0b0..XBAR_INOUT as input + * 0b1..XBAR_INOUT as output + */ #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_9(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_9_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_9_MASK) #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_10_MASK (0x400000U) #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_10_SHIFT (22U) +/*! IOMUXC_XBAR_DIR_SEL_10 + * 0b0..XBAR_INOUT as input + * 0b1..XBAR_INOUT as output + */ #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_10(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_10_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_10_MASK) #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_11_MASK (0x800000U) #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_11_SHIFT (23U) +/*! IOMUXC_XBAR_DIR_SEL_11 + * 0b0..XBAR_INOUT as input + * 0b1..XBAR_INOUT as output + */ #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_11(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_11_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_11_MASK) #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_12_MASK (0x1000000U) #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_12_SHIFT (24U) +/*! IOMUXC_XBAR_DIR_SEL_12 + * 0b0..XBAR_INOUT as input + * 0b1..XBAR_INOUT as output + */ #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_12(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_12_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_12_MASK) #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_13_MASK (0x2000000U) #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_13_SHIFT (25U) +/*! IOMUXC_XBAR_DIR_SEL_13 + * 0b0..XBAR_INOUT as input + * 0b1..XBAR_INOUT as output + */ #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_13(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_13_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_13_MASK) #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_14_MASK (0x4000000U) #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_14_SHIFT (26U) +/*! IOMUXC_XBAR_DIR_SEL_14 + * 0b0..XBAR_INOUT as input + * 0b1..XBAR_INOUT as output + */ #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_14(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_14_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_14_MASK) #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_15_MASK (0x8000000U) #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_15_SHIFT (27U) +/*! IOMUXC_XBAR_DIR_SEL_15 + * 0b0..XBAR_INOUT as input + * 0b1..XBAR_INOUT as output + */ #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_15(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_15_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_15_MASK) #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_16_MASK (0x10000000U) #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_16_SHIFT (28U) +/*! IOMUXC_XBAR_DIR_SEL_16 + * 0b0..XBAR_INOUT as input + * 0b1..XBAR_INOUT as output + */ #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_16(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_16_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_16_MASK) #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_17_MASK (0x20000000U) #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_17_SHIFT (29U) +/*! IOMUXC_XBAR_DIR_SEL_17 + * 0b0..XBAR_INOUT as input + * 0b1..XBAR_INOUT as output + */ #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_17(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_17_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_17_MASK) #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_18_MASK (0x40000000U) #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_18_SHIFT (30U) +/*! IOMUXC_XBAR_DIR_SEL_18 + * 0b0..XBAR_INOUT as input + * 0b1..XBAR_INOUT as output + */ #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_18_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_18_MASK) #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_19_MASK (0x80000000U) #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_19_SHIFT (31U) +/*! IOMUXC_XBAR_DIR_SEL_19 + * 0b0..XBAR_INOUT as input + * 0b1..XBAR_INOUT as output + */ #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_19(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_19_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_19_MASK) +/*! @} */ /*! @name GPR7 - GPR7 General Purpose Register */ +/*! @{ */ #define IOMUXC_GPR_GPR7_LPI2C1_STOP_REQ_MASK (0x1U) #define IOMUXC_GPR_GPR7_LPI2C1_STOP_REQ_SHIFT (0U) +/*! LPI2C1_STOP_REQ + * 0b0..stop request off + * 0b1..stop request on + */ #define IOMUXC_GPR_GPR7_LPI2C1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPI2C1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPI2C1_STOP_REQ_MASK) #define IOMUXC_GPR_GPR7_LPI2C2_STOP_REQ_MASK (0x2U) #define IOMUXC_GPR_GPR7_LPI2C2_STOP_REQ_SHIFT (1U) +/*! LPI2C2_STOP_REQ + * 0b0..stop request off + * 0b1..stop request on + */ #define IOMUXC_GPR_GPR7_LPI2C2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPI2C2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPI2C2_STOP_REQ_MASK) #define IOMUXC_GPR_GPR7_LPI2C3_STOP_REQ_MASK (0x4U) #define IOMUXC_GPR_GPR7_LPI2C3_STOP_REQ_SHIFT (2U) +/*! LPI2C3_STOP_REQ + * 0b0..stop request off + * 0b1..stop request on + */ #define IOMUXC_GPR_GPR7_LPI2C3_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPI2C3_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPI2C3_STOP_REQ_MASK) #define IOMUXC_GPR_GPR7_LPI2C4_STOP_REQ_MASK (0x8U) #define IOMUXC_GPR_GPR7_LPI2C4_STOP_REQ_SHIFT (3U) +/*! LPI2C4_STOP_REQ + * 0b0..stop request off + * 0b1..stop request on + */ #define IOMUXC_GPR_GPR7_LPI2C4_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPI2C4_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPI2C4_STOP_REQ_MASK) #define IOMUXC_GPR_GPR7_LPSPI1_STOP_REQ_MASK (0x10U) #define IOMUXC_GPR_GPR7_LPSPI1_STOP_REQ_SHIFT (4U) +/*! LPSPI1_STOP_REQ + * 0b0..stop request off + * 0b1..stop request on + */ #define IOMUXC_GPR_GPR7_LPSPI1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPSPI1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPSPI1_STOP_REQ_MASK) #define IOMUXC_GPR_GPR7_LPSPI2_STOP_REQ_MASK (0x20U) #define IOMUXC_GPR_GPR7_LPSPI2_STOP_REQ_SHIFT (5U) +/*! LPSPI2_STOP_REQ + * 0b0..stop request off + * 0b1..stop request on + */ #define IOMUXC_GPR_GPR7_LPSPI2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPSPI2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPSPI2_STOP_REQ_MASK) #define IOMUXC_GPR_GPR7_LPSPI3_STOP_REQ_MASK (0x40U) #define IOMUXC_GPR_GPR7_LPSPI3_STOP_REQ_SHIFT (6U) +/*! LPSPI3_STOP_REQ + * 0b0..stop request off + * 0b1..stop request on + */ #define IOMUXC_GPR_GPR7_LPSPI3_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPSPI3_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPSPI3_STOP_REQ_MASK) #define IOMUXC_GPR_GPR7_LPSPI4_STOP_REQ_MASK (0x80U) #define IOMUXC_GPR_GPR7_LPSPI4_STOP_REQ_SHIFT (7U) +/*! LPSPI4_STOP_REQ + * 0b0..stop request off + * 0b1..stop request on + */ #define IOMUXC_GPR_GPR7_LPSPI4_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPSPI4_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPSPI4_STOP_REQ_MASK) #define IOMUXC_GPR_GPR7_LPUART1_STOP_REQ_MASK (0x100U) #define IOMUXC_GPR_GPR7_LPUART1_STOP_REQ_SHIFT (8U) +/*! LPUART1_STOP_REQ + * 0b0..stop request off + * 0b1..stop request on + */ #define IOMUXC_GPR_GPR7_LPUART1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPUART1_STOP_REQ_MASK) #define IOMUXC_GPR_GPR7_LPUART2_STOP_REQ_MASK (0x200U) #define IOMUXC_GPR_GPR7_LPUART2_STOP_REQ_SHIFT (9U) +/*! LPUART2_STOP_REQ + * 0b0..stop request off + * 0b1..stop request on + */ #define IOMUXC_GPR_GPR7_LPUART2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPUART2_STOP_REQ_MASK) #define IOMUXC_GPR_GPR7_LPUART3_STOP_REQ_MASK (0x400U) #define IOMUXC_GPR_GPR7_LPUART3_STOP_REQ_SHIFT (10U) +/*! LPUART3_STOP_REQ + * 0b0..stop request off + * 0b1..stop request on + */ #define IOMUXC_GPR_GPR7_LPUART3_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART3_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPUART3_STOP_REQ_MASK) #define IOMUXC_GPR_GPR7_LPUART4_STOP_REQ_MASK (0x800U) #define IOMUXC_GPR_GPR7_LPUART4_STOP_REQ_SHIFT (11U) +/*! LPUART4_STOP_REQ + * 0b0..stop request off + * 0b1..stop request on + */ #define IOMUXC_GPR_GPR7_LPUART4_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART4_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPUART4_STOP_REQ_MASK) #define IOMUXC_GPR_GPR7_LPUART5_STOP_REQ_MASK (0x1000U) #define IOMUXC_GPR_GPR7_LPUART5_STOP_REQ_SHIFT (12U) +/*! LPUART5_STOP_REQ + * 0b0..stop request off + * 0b1..stop request on + */ #define IOMUXC_GPR_GPR7_LPUART5_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART5_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPUART5_STOP_REQ_MASK) #define IOMUXC_GPR_GPR7_LPUART6_STOP_REQ_MASK (0x2000U) #define IOMUXC_GPR_GPR7_LPUART6_STOP_REQ_SHIFT (13U) +/*! LPUART6_STOP_REQ + * 0b0..stop request off + * 0b1..stop request on + */ #define IOMUXC_GPR_GPR7_LPUART6_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART6_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPUART6_STOP_REQ_MASK) #define IOMUXC_GPR_GPR7_LPUART7_STOP_REQ_MASK (0x4000U) #define IOMUXC_GPR_GPR7_LPUART7_STOP_REQ_SHIFT (14U) +/*! LPUART7_STOP_REQ + * 0b0..stop request off + * 0b1..stop request on + */ #define IOMUXC_GPR_GPR7_LPUART7_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART7_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPUART7_STOP_REQ_MASK) #define IOMUXC_GPR_GPR7_LPUART8_STOP_REQ_MASK (0x8000U) #define IOMUXC_GPR_GPR7_LPUART8_STOP_REQ_SHIFT (15U) +/*! LPUART8_STOP_REQ + * 0b0..stop request off + * 0b1..stop request on + */ #define IOMUXC_GPR_GPR7_LPUART8_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART8_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPUART8_STOP_REQ_MASK) #define IOMUXC_GPR_GPR7_LPI2C1_STOP_ACK_MASK (0x10000U) #define IOMUXC_GPR_GPR7_LPI2C1_STOP_ACK_SHIFT (16U) +/*! LPI2C1_STOP_ACK + * 0b0..stop acknowledge is not asserted + * 0b1..stop acknowledge is asserted (the module is in Stop mode) + */ #define IOMUXC_GPR_GPR7_LPI2C1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPI2C1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPI2C1_STOP_ACK_MASK) #define IOMUXC_GPR_GPR7_LPI2C2_STOP_ACK_MASK (0x20000U) #define IOMUXC_GPR_GPR7_LPI2C2_STOP_ACK_SHIFT (17U) +/*! LPI2C2_STOP_ACK + * 0b0..stop acknowledge is not asserted + * 0b1..stop acknowledge is asserted + */ #define IOMUXC_GPR_GPR7_LPI2C2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPI2C2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPI2C2_STOP_ACK_MASK) #define IOMUXC_GPR_GPR7_LPI2C3_STOP_ACK_MASK (0x40000U) #define IOMUXC_GPR_GPR7_LPI2C3_STOP_ACK_SHIFT (18U) +/*! LPI2C3_STOP_ACK + * 0b0..stop acknowledge is not asserted + * 0b1..stop acknowledge is asserted + */ #define IOMUXC_GPR_GPR7_LPI2C3_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPI2C3_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPI2C3_STOP_ACK_MASK) #define IOMUXC_GPR_GPR7_LPI2C4_STOP_ACK_MASK (0x80000U) #define IOMUXC_GPR_GPR7_LPI2C4_STOP_ACK_SHIFT (19U) +/*! LPI2C4_STOP_ACK + * 0b0..stop acknowledge is not asserted + * 0b1..stop acknowledge is asserted + */ #define IOMUXC_GPR_GPR7_LPI2C4_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPI2C4_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPI2C4_STOP_ACK_MASK) #define IOMUXC_GPR_GPR7_LPSPI1_STOP_ACK_MASK (0x100000U) #define IOMUXC_GPR_GPR7_LPSPI1_STOP_ACK_SHIFT (20U) +/*! LPSPI1_STOP_ACK + * 0b0..stop acknowledge is not asserted + * 0b1..stop acknowledge is asserted + */ #define IOMUXC_GPR_GPR7_LPSPI1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPSPI1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPSPI1_STOP_ACK_MASK) #define IOMUXC_GPR_GPR7_LPSPI2_STOP_ACK_MASK (0x200000U) #define IOMUXC_GPR_GPR7_LPSPI2_STOP_ACK_SHIFT (21U) +/*! LPSPI2_STOP_ACK + * 0b0..stop acknowledge is not asserted + * 0b1..stop acknowledge is asserted + */ #define IOMUXC_GPR_GPR7_LPSPI2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPSPI2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPSPI2_STOP_ACK_MASK) #define IOMUXC_GPR_GPR7_LPSPI3_STOP_ACK_MASK (0x400000U) #define IOMUXC_GPR_GPR7_LPSPI3_STOP_ACK_SHIFT (22U) +/*! LPSPI3_STOP_ACK + * 0b0..stop acknowledge is not asserted + * 0b1..stop acknowledge is asserted + */ #define IOMUXC_GPR_GPR7_LPSPI3_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPSPI3_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPSPI3_STOP_ACK_MASK) #define IOMUXC_GPR_GPR7_LPSPI4_STOP_ACK_MASK (0x800000U) #define IOMUXC_GPR_GPR7_LPSPI4_STOP_ACK_SHIFT (23U) +/*! LPSPI4_STOP_ACK + * 0b0..stop acknowledge is not asserted + * 0b1..stop acknowledge is asserted + */ #define IOMUXC_GPR_GPR7_LPSPI4_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPSPI4_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPSPI4_STOP_ACK_MASK) #define IOMUXC_GPR_GPR7_LPUART1_STOP_ACK_MASK (0x1000000U) #define IOMUXC_GPR_GPR7_LPUART1_STOP_ACK_SHIFT (24U) +/*! LPUART1_STOP_ACK + * 0b0..stop acknowledge is not asserted + * 0b1..stop acknowledge is asserted + */ #define IOMUXC_GPR_GPR7_LPUART1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPUART1_STOP_ACK_MASK) #define IOMUXC_GPR_GPR7_LPUART2_STOP_ACK_MASK (0x2000000U) #define IOMUXC_GPR_GPR7_LPUART2_STOP_ACK_SHIFT (25U) +/*! LPUART2_STOP_ACK + * 0b0..stop acknowledge is not asserted + * 0b1..stop acknowledge is asserted + */ #define IOMUXC_GPR_GPR7_LPUART2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPUART2_STOP_ACK_MASK) #define IOMUXC_GPR_GPR7_LPUART3_STOP_ACK_MASK (0x4000000U) #define IOMUXC_GPR_GPR7_LPUART3_STOP_ACK_SHIFT (26U) +/*! LPUART3_STOP_ACK + * 0b0..stop acknowledge is not asserted + * 0b1..stop acknowledge is asserted + */ #define IOMUXC_GPR_GPR7_LPUART3_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART3_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPUART3_STOP_ACK_MASK) #define IOMUXC_GPR_GPR7_LPUART4_STOP_ACK_MASK (0x8000000U) #define IOMUXC_GPR_GPR7_LPUART4_STOP_ACK_SHIFT (27U) +/*! LPUART4_STOP_ACK + * 0b0..stop acknowledge is not asserted + * 0b1..stop acknowledge is asserted + */ #define IOMUXC_GPR_GPR7_LPUART4_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART4_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPUART4_STOP_ACK_MASK) #define IOMUXC_GPR_GPR7_LPUART5_STOP_ACK_MASK (0x10000000U) #define IOMUXC_GPR_GPR7_LPUART5_STOP_ACK_SHIFT (28U) +/*! LPUART5_STOP_ACK + * 0b0..stop acknowledge is not asserted + * 0b1..stop acknowledge is asserted + */ #define IOMUXC_GPR_GPR7_LPUART5_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART5_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPUART5_STOP_ACK_MASK) #define IOMUXC_GPR_GPR7_LPUART6_STOP_ACK_MASK (0x20000000U) #define IOMUXC_GPR_GPR7_LPUART6_STOP_ACK_SHIFT (29U) +/*! LPUART6_STOP_ACK + * 0b0..stop acknowledge is not asserted + * 0b1..stop acknowledge is asserted + */ #define IOMUXC_GPR_GPR7_LPUART6_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART6_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPUART6_STOP_ACK_MASK) #define IOMUXC_GPR_GPR7_LPUART7_STOP_ACK_MASK (0x40000000U) #define IOMUXC_GPR_GPR7_LPUART7_STOP_ACK_SHIFT (30U) +/*! LPUART7_STOP_ACK + * 0b0..stop acknowledge is not asserted + * 0b1..stop acknowledge is asserted + */ #define IOMUXC_GPR_GPR7_LPUART7_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART7_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPUART7_STOP_ACK_MASK) #define IOMUXC_GPR_GPR7_LPUART8_STOP_ACK_MASK (0x80000000U) #define IOMUXC_GPR_GPR7_LPUART8_STOP_ACK_SHIFT (31U) +/*! LPUART8_STOP_ACK + * 0b0..stop acknowledge is not asserted + * 0b1..stop acknowledge is asserted (the module is in Stop mode) + */ #define IOMUXC_GPR_GPR7_LPUART8_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART8_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPUART8_STOP_ACK_MASK) +/*! @} */ /*! @name GPR8 - GPR8 General Purpose Register */ +/*! @{ */ #define IOMUXC_GPR_GPR8_LPI2C1_IPG_STOP_MODE_MASK (0x1U) #define IOMUXC_GPR_GPR8_LPI2C1_IPG_STOP_MODE_SHIFT (0U) +/*! LPI2C1_IPG_STOP_MODE + * 0b0..the module is functional in Stop mode + * 0b1..the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted + */ #define IOMUXC_GPR_GPR8_LPI2C1_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPI2C1_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPI2C1_IPG_STOP_MODE_MASK) #define IOMUXC_GPR_GPR8_LPI2C1_IPG_DOZE_MASK (0x2U) #define IOMUXC_GPR_GPR8_LPI2C1_IPG_DOZE_SHIFT (1U) +/*! LPI2C1_IPG_DOZE + * 0b0..not in doze mode + * 0b1..in doze mode + */ #define IOMUXC_GPR_GPR8_LPI2C1_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPI2C1_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPI2C1_IPG_DOZE_MASK) #define IOMUXC_GPR_GPR8_LPI2C2_IPG_STOP_MODE_MASK (0x4U) #define IOMUXC_GPR_GPR8_LPI2C2_IPG_STOP_MODE_SHIFT (2U) +/*! LPI2C2_IPG_STOP_MODE + * 0b0..the module is functional in Stop mode + * 0b1..the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted + */ #define IOMUXC_GPR_GPR8_LPI2C2_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPI2C2_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPI2C2_IPG_STOP_MODE_MASK) #define IOMUXC_GPR_GPR8_LPI2C2_IPG_DOZE_MASK (0x8U) #define IOMUXC_GPR_GPR8_LPI2C2_IPG_DOZE_SHIFT (3U) +/*! LPI2C2_IPG_DOZE + * 0b0..not in doze mode + * 0b1..in doze mode + */ #define IOMUXC_GPR_GPR8_LPI2C2_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPI2C2_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPI2C2_IPG_DOZE_MASK) #define IOMUXC_GPR_GPR8_LPI2C3_IPG_STOP_MODE_MASK (0x10U) #define IOMUXC_GPR_GPR8_LPI2C3_IPG_STOP_MODE_SHIFT (4U) +/*! LPI2C3_IPG_STOP_MODE + * 0b0..the module is functional in Stop mode + * 0b1..the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted + */ #define IOMUXC_GPR_GPR8_LPI2C3_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPI2C3_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPI2C3_IPG_STOP_MODE_MASK) #define IOMUXC_GPR_GPR8_LPI2C3_IPG_DOZE_MASK (0x20U) #define IOMUXC_GPR_GPR8_LPI2C3_IPG_DOZE_SHIFT (5U) +/*! LPI2C3_IPG_DOZE + * 0b0..not in doze mode + * 0b1..in doze mode + */ #define IOMUXC_GPR_GPR8_LPI2C3_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPI2C3_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPI2C3_IPG_DOZE_MASK) #define IOMUXC_GPR_GPR8_LPI2C4_IPG_STOP_MODE_MASK (0x40U) #define IOMUXC_GPR_GPR8_LPI2C4_IPG_STOP_MODE_SHIFT (6U) +/*! LPI2C4_IPG_STOP_MODE + * 0b0..the module is functional in Stop mode + * 0b1..the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted + */ #define IOMUXC_GPR_GPR8_LPI2C4_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPI2C4_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPI2C4_IPG_STOP_MODE_MASK) #define IOMUXC_GPR_GPR8_LPI2C4_IPG_DOZE_MASK (0x80U) #define IOMUXC_GPR_GPR8_LPI2C4_IPG_DOZE_SHIFT (7U) +/*! LPI2C4_IPG_DOZE + * 0b0..not in doze mode + * 0b1..in doze mode + */ #define IOMUXC_GPR_GPR8_LPI2C4_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPI2C4_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPI2C4_IPG_DOZE_MASK) #define IOMUXC_GPR_GPR8_LPSPI1_IPG_STOP_MODE_MASK (0x100U) #define IOMUXC_GPR_GPR8_LPSPI1_IPG_STOP_MODE_SHIFT (8U) +/*! LPSPI1_IPG_STOP_MODE + * 0b0..the module is functional in Stop mode + * 0b1..the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted + */ #define IOMUXC_GPR_GPR8_LPSPI1_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPSPI1_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPSPI1_IPG_STOP_MODE_MASK) #define IOMUXC_GPR_GPR8_LPSPI1_IPG_DOZE_MASK (0x200U) #define IOMUXC_GPR_GPR8_LPSPI1_IPG_DOZE_SHIFT (9U) +/*! LPSPI1_IPG_DOZE + * 0b0..not in doze mode + * 0b1..in doze mode + */ #define IOMUXC_GPR_GPR8_LPSPI1_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPSPI1_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPSPI1_IPG_DOZE_MASK) #define IOMUXC_GPR_GPR8_LPSPI2_IPG_STOP_MODE_MASK (0x400U) #define IOMUXC_GPR_GPR8_LPSPI2_IPG_STOP_MODE_SHIFT (10U) +/*! LPSPI2_IPG_STOP_MODE + * 0b0..the module is functional in Stop mode + * 0b1..the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted + */ #define IOMUXC_GPR_GPR8_LPSPI2_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPSPI2_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPSPI2_IPG_STOP_MODE_MASK) #define IOMUXC_GPR_GPR8_LPSPI2_IPG_DOZE_MASK (0x800U) #define IOMUXC_GPR_GPR8_LPSPI2_IPG_DOZE_SHIFT (11U) +/*! LPSPI2_IPG_DOZE + * 0b0..not in doze mode + * 0b1..in doze mode + */ #define IOMUXC_GPR_GPR8_LPSPI2_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPSPI2_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPSPI2_IPG_DOZE_MASK) #define IOMUXC_GPR_GPR8_LPSPI3_IPG_STOP_MODE_MASK (0x1000U) #define IOMUXC_GPR_GPR8_LPSPI3_IPG_STOP_MODE_SHIFT (12U) +/*! LPSPI3_IPG_STOP_MODE + * 0b0..the module is functional in Stop mode + * 0b1..the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted + */ #define IOMUXC_GPR_GPR8_LPSPI3_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPSPI3_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPSPI3_IPG_STOP_MODE_MASK) #define IOMUXC_GPR_GPR8_LPSPI3_IPG_DOZE_MASK (0x2000U) #define IOMUXC_GPR_GPR8_LPSPI3_IPG_DOZE_SHIFT (13U) +/*! LPSPI3_IPG_DOZE + * 0b0..not in doze mode + * 0b1..in doze mode + */ #define IOMUXC_GPR_GPR8_LPSPI3_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPSPI3_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPSPI3_IPG_DOZE_MASK) #define IOMUXC_GPR_GPR8_LPSPI4_IPG_STOP_MODE_MASK (0x4000U) #define IOMUXC_GPR_GPR8_LPSPI4_IPG_STOP_MODE_SHIFT (14U) +/*! LPSPI4_IPG_STOP_MODE + * 0b0..the module is functional in Stop mode + * 0b1..the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted + */ #define IOMUXC_GPR_GPR8_LPSPI4_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPSPI4_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPSPI4_IPG_STOP_MODE_MASK) #define IOMUXC_GPR_GPR8_LPSPI4_IPG_DOZE_MASK (0x8000U) #define IOMUXC_GPR_GPR8_LPSPI4_IPG_DOZE_SHIFT (15U) +/*! LPSPI4_IPG_DOZE + * 0b0..not in doze mode + * 0b1..in doze mode + */ #define IOMUXC_GPR_GPR8_LPSPI4_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPSPI4_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPSPI4_IPG_DOZE_MASK) #define IOMUXC_GPR_GPR8_LPUART1_IPG_STOP_MODE_MASK (0x10000U) #define IOMUXC_GPR_GPR8_LPUART1_IPG_STOP_MODE_SHIFT (16U) +/*! LPUART1_IPG_STOP_MODE + * 0b0..the module is functional in Stop mode + * 0b1..the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted + */ #define IOMUXC_GPR_GPR8_LPUART1_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART1_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART1_IPG_STOP_MODE_MASK) #define IOMUXC_GPR_GPR8_LPUART1_IPG_DOZE_MASK (0x20000U) #define IOMUXC_GPR_GPR8_LPUART1_IPG_DOZE_SHIFT (17U) +/*! LPUART1_IPG_DOZE + * 0b0..not in doze mode + * 0b1..in doze mode + */ #define IOMUXC_GPR_GPR8_LPUART1_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART1_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART1_IPG_DOZE_MASK) #define IOMUXC_GPR_GPR8_LPUART2_IPG_STOP_MODE_MASK (0x40000U) #define IOMUXC_GPR_GPR8_LPUART2_IPG_STOP_MODE_SHIFT (18U) +/*! LPUART2_IPG_STOP_MODE + * 0b0..the module is functional in Stop mode + * 0b1..the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted + */ #define IOMUXC_GPR_GPR8_LPUART2_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART2_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART2_IPG_STOP_MODE_MASK) #define IOMUXC_GPR_GPR8_LPUART2_IPG_DOZE_MASK (0x80000U) #define IOMUXC_GPR_GPR8_LPUART2_IPG_DOZE_SHIFT (19U) +/*! LPUART2_IPG_DOZE + * 0b0..not in doze mode + * 0b1..in doze mode + */ #define IOMUXC_GPR_GPR8_LPUART2_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART2_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART2_IPG_DOZE_MASK) #define IOMUXC_GPR_GPR8_LPUART3_IPG_STOP_MODE_MASK (0x100000U) #define IOMUXC_GPR_GPR8_LPUART3_IPG_STOP_MODE_SHIFT (20U) +/*! LPUART3_IPG_STOP_MODE + * 0b0..the module is functional in Stop mode + * 0b1..the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted + */ #define IOMUXC_GPR_GPR8_LPUART3_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART3_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART3_IPG_STOP_MODE_MASK) #define IOMUXC_GPR_GPR8_LPUART3_IPG_DOZE_MASK (0x200000U) #define IOMUXC_GPR_GPR8_LPUART3_IPG_DOZE_SHIFT (21U) +/*! LPUART3_IPG_DOZE + * 0b0..not in doze mode + * 0b1..in doze mode + */ #define IOMUXC_GPR_GPR8_LPUART3_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART3_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART3_IPG_DOZE_MASK) #define IOMUXC_GPR_GPR8_LPUART4_IPG_STOP_MODE_MASK (0x400000U) #define IOMUXC_GPR_GPR8_LPUART4_IPG_STOP_MODE_SHIFT (22U) +/*! LPUART4_IPG_STOP_MODE + * 0b0..the module is functional in Stop mode + * 0b1..the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted + */ #define IOMUXC_GPR_GPR8_LPUART4_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART4_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART4_IPG_STOP_MODE_MASK) #define IOMUXC_GPR_GPR8_LPUART4_IPG_DOZE_MASK (0x800000U) #define IOMUXC_GPR_GPR8_LPUART4_IPG_DOZE_SHIFT (23U) +/*! LPUART4_IPG_DOZE + * 0b0..not in doze mode + * 0b1..in doze mode + */ #define IOMUXC_GPR_GPR8_LPUART4_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART4_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART4_IPG_DOZE_MASK) #define IOMUXC_GPR_GPR8_LPUART5_IPG_STOP_MODE_MASK (0x1000000U) #define IOMUXC_GPR_GPR8_LPUART5_IPG_STOP_MODE_SHIFT (24U) +/*! LPUART5_IPG_STOP_MODE + * 0b0..the module is functional in Stop mode + * 0b1..the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted + */ #define IOMUXC_GPR_GPR8_LPUART5_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART5_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART5_IPG_STOP_MODE_MASK) #define IOMUXC_GPR_GPR8_LPUART5_IPG_DOZE_MASK (0x2000000U) #define IOMUXC_GPR_GPR8_LPUART5_IPG_DOZE_SHIFT (25U) +/*! LPUART5_IPG_DOZE + * 0b0..not in doze mode + * 0b1..in doze mode + */ #define IOMUXC_GPR_GPR8_LPUART5_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART5_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART5_IPG_DOZE_MASK) #define IOMUXC_GPR_GPR8_LPUART6_IPG_STOP_MODE_MASK (0x4000000U) #define IOMUXC_GPR_GPR8_LPUART6_IPG_STOP_MODE_SHIFT (26U) +/*! LPUART6_IPG_STOP_MODE + * 0b0..the module is functional in Stop mode + * 0b1..the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted + */ #define IOMUXC_GPR_GPR8_LPUART6_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART6_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART6_IPG_STOP_MODE_MASK) #define IOMUXC_GPR_GPR8_LPUART6_IPG_DOZE_MASK (0x8000000U) #define IOMUXC_GPR_GPR8_LPUART6_IPG_DOZE_SHIFT (27U) +/*! LPUART6_IPG_DOZE + * 0b0..not in doze mode + * 0b1..in doze mode + */ #define IOMUXC_GPR_GPR8_LPUART6_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART6_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART6_IPG_DOZE_MASK) #define IOMUXC_GPR_GPR8_LPUART7_IPG_STOP_MODE_MASK (0x10000000U) #define IOMUXC_GPR_GPR8_LPUART7_IPG_STOP_MODE_SHIFT (28U) +/*! LPUART7_IPG_STOP_MODE + * 0b0..the module is functional in Stop mode + * 0b1..the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted + */ #define IOMUXC_GPR_GPR8_LPUART7_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART7_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART7_IPG_STOP_MODE_MASK) #define IOMUXC_GPR_GPR8_LPUART7_IPG_DOZE_MASK (0x20000000U) #define IOMUXC_GPR_GPR8_LPUART7_IPG_DOZE_SHIFT (29U) +/*! LPUART7_IPG_DOZE + * 0b0..not in doze mode + * 0b1..in doze mode + */ #define IOMUXC_GPR_GPR8_LPUART7_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART7_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART7_IPG_DOZE_MASK) #define IOMUXC_GPR_GPR8_LPUART8_IPG_STOP_MODE_MASK (0x40000000U) #define IOMUXC_GPR_GPR8_LPUART8_IPG_STOP_MODE_SHIFT (30U) +/*! LPUART8_IPG_STOP_MODE + * 0b0..the module is functional in Stop mode + * 0b1..the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted + */ #define IOMUXC_GPR_GPR8_LPUART8_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART8_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART8_IPG_STOP_MODE_MASK) #define IOMUXC_GPR_GPR8_LPUART8_IPG_DOZE_MASK (0x80000000U) #define IOMUXC_GPR_GPR8_LPUART8_IPG_DOZE_SHIFT (31U) +/*! LPUART8_IPG_DOZE + * 0b0..not in doze mode + * 0b1..in doze mode + */ #define IOMUXC_GPR_GPR8_LPUART8_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART8_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART8_IPG_DOZE_MASK) +/*! @} */ /*! @name GPR10 - GPR10 General Purpose Register */ +/*! @{ */ #define IOMUXC_GPR_GPR10_NIDEN_MASK (0x1U) #define IOMUXC_GPR_GPR10_NIDEN_SHIFT (0U) +/*! NIDEN + * 0b0..Debug turned off. + * 0b1..Debug enabled (default). + */ #define IOMUXC_GPR_GPR10_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_NIDEN_SHIFT)) & IOMUXC_GPR_GPR10_NIDEN_MASK) #define IOMUXC_GPR_GPR10_DBG_EN_MASK (0x2U) #define IOMUXC_GPR_GPR10_DBG_EN_SHIFT (1U) +/*! DBG_EN + * 0b0..Debug turned off. + * 0b1..Debug enabled (default). + */ #define IOMUXC_GPR_GPR10_DBG_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_DBG_EN_SHIFT)) & IOMUXC_GPR_GPR10_DBG_EN_MASK) #define IOMUXC_GPR_GPR10_SEC_ERR_RESP_MASK (0x4U) #define IOMUXC_GPR_GPR10_SEC_ERR_RESP_SHIFT (2U) +/*! SEC_ERR_RESP + * 0b0..OKEY response + * 0b1..SLVError (default) + */ #define IOMUXC_GPR_GPR10_SEC_ERR_RESP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_SEC_ERR_RESP_SHIFT)) & IOMUXC_GPR_GPR10_SEC_ERR_RESP_MASK) #define IOMUXC_GPR_GPR10_DCPKEY_OCOTP_OR_KEYMUX_MASK (0x10U) #define IOMUXC_GPR_GPR10_DCPKEY_OCOTP_OR_KEYMUX_SHIFT (4U) +/*! DCPKEY_OCOTP_OR_KEYMUX + * 0b0..Select key from Key MUX (SNVS/OTPMK). + * 0b1..Select key from OCOTP (SW_GP2). + */ #define IOMUXC_GPR_GPR10_DCPKEY_OCOTP_OR_KEYMUX(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_DCPKEY_OCOTP_OR_KEYMUX_SHIFT)) & IOMUXC_GPR_GPR10_DCPKEY_OCOTP_OR_KEYMUX_MASK) #define IOMUXC_GPR_GPR10_OCRAM_TZ_EN_MASK (0x100U) #define IOMUXC_GPR_GPR10_OCRAM_TZ_EN_SHIFT (8U) +/*! OCRAM_TZ_EN + * 0b0..The TrustZone feature is disabled. Entire OCRAM space is available for all access types (secure/non-secure/user/supervisor). + * 0b1..The TrustZone feature is enabled. Access to address in the range specified by [ENDADDR:STARTADDR] follows the execution mode access policy described in CSU chapter. + */ #define IOMUXC_GPR_GPR10_OCRAM_TZ_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_OCRAM_TZ_EN_SHIFT)) & IOMUXC_GPR_GPR10_OCRAM_TZ_EN_MASK) #define IOMUXC_GPR_GPR10_OCRAM_TZ_ADDR_MASK (0xFE00U) #define IOMUXC_GPR_GPR10_OCRAM_TZ_ADDR_SHIFT (9U) #define IOMUXC_GPR_GPR10_OCRAM_TZ_ADDR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_OCRAM_TZ_ADDR_SHIFT)) & IOMUXC_GPR_GPR10_OCRAM_TZ_ADDR_MASK) #define IOMUXC_GPR_GPR10_LOCK_NIDEN_MASK (0x10000U) #define IOMUXC_GPR_GPR10_LOCK_NIDEN_SHIFT (16U) +/*! LOCK_NIDEN + * 0b0..Field is not locked + * 0b1..Field is locked (read access only) + */ #define IOMUXC_GPR_GPR10_LOCK_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_LOCK_NIDEN_SHIFT)) & IOMUXC_GPR_GPR10_LOCK_NIDEN_MASK) #define IOMUXC_GPR_GPR10_LOCK_DBG_EN_MASK (0x20000U) #define IOMUXC_GPR_GPR10_LOCK_DBG_EN_SHIFT (17U) +/*! LOCK_DBG_EN + * 0b0..Field is not locked + * 0b1..Field is locked (read access only) + */ #define IOMUXC_GPR_GPR10_LOCK_DBG_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_LOCK_DBG_EN_SHIFT)) & IOMUXC_GPR_GPR10_LOCK_DBG_EN_MASK) #define IOMUXC_GPR_GPR10_LOCK_SEC_ERR_RESP_MASK (0x40000U) #define IOMUXC_GPR_GPR10_LOCK_SEC_ERR_RESP_SHIFT (18U) +/*! LOCK_SEC_ERR_RESP + * 0b0..Field is not locked + * 0b1..Field is locked (read access only) + */ #define IOMUXC_GPR_GPR10_LOCK_SEC_ERR_RESP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_LOCK_SEC_ERR_RESP_SHIFT)) & IOMUXC_GPR_GPR10_LOCK_SEC_ERR_RESP_MASK) #define IOMUXC_GPR_GPR10_LOCK_DCPKEY_OCOTP_OR_KEYMUX_MASK (0x100000U) #define IOMUXC_GPR_GPR10_LOCK_DCPKEY_OCOTP_OR_KEYMUX_SHIFT (20U) +/*! LOCK_DCPKEY_OCOTP_OR_KEYMUX + * 0b0..Field is not locked + * 0b1..Field is locked (read access only) + */ #define IOMUXC_GPR_GPR10_LOCK_DCPKEY_OCOTP_OR_KEYMUX(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_LOCK_DCPKEY_OCOTP_OR_KEYMUX_SHIFT)) & IOMUXC_GPR_GPR10_LOCK_DCPKEY_OCOTP_OR_KEYMUX_MASK) #define IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_EN_MASK (0x1000000U) #define IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_EN_SHIFT (24U) +/*! LOCK_OCRAM_TZ_EN + * 0b0..Field is not locked + * 0b1..Field is locked (read access only) + */ #define IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_EN_SHIFT)) & IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_EN_MASK) #define IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_ADDR_MASK (0xFE000000U) #define IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_ADDR_SHIFT (25U) +/*! LOCK_OCRAM_TZ_ADDR + * 0b0000000..Field is not locked + * 0b0000001..Field is locked (read access only) + */ #define IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_ADDR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_ADDR_SHIFT)) & IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_ADDR_MASK) +/*! @} */ /*! @name GPR11 - GPR11 General Purpose Register */ +/*! @{ */ #define IOMUXC_GPR_GPR11_M7_APC_AC_R0_CTRL_MASK (0x3U) #define IOMUXC_GPR_GPR11_M7_APC_AC_R0_CTRL_SHIFT (0U) +/*! M7_APC_AC_R0_CTRL + * 0b00..No access protection + * 0b01..M7 debug protection enabled + * 0b10..FlexSPI access protection + * 0b11..Both M7 debug and FlexSPI access are protected + */ #define IOMUXC_GPR_GPR11_M7_APC_AC_R0_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_M7_APC_AC_R0_CTRL_SHIFT)) & IOMUXC_GPR_GPR11_M7_APC_AC_R0_CTRL_MASK) #define IOMUXC_GPR_GPR11_M7_APC_AC_R1_CTRL_MASK (0xCU) #define IOMUXC_GPR_GPR11_M7_APC_AC_R1_CTRL_SHIFT (2U) +/*! M7_APC_AC_R1_CTRL + * 0b00..No access protection + * 0b01..M7 debug protection enabled + * 0b10..FlexSPI access protection + * 0b11..Both M7 debug and FlexSPI access are protected + */ #define IOMUXC_GPR_GPR11_M7_APC_AC_R1_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_M7_APC_AC_R1_CTRL_SHIFT)) & IOMUXC_GPR_GPR11_M7_APC_AC_R1_CTRL_MASK) #define IOMUXC_GPR_GPR11_M7_APC_AC_R2_CTRL_MASK (0x30U) #define IOMUXC_GPR_GPR11_M7_APC_AC_R2_CTRL_SHIFT (4U) +/*! M7_APC_AC_R2_CTRL + * 0b00..No access protection + * 0b01..M7 debug protection enabled + * 0b10..FlexSPI access protection + * 0b11..Both M7 debug and FlexSPI access are protected + */ #define IOMUXC_GPR_GPR11_M7_APC_AC_R2_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_M7_APC_AC_R2_CTRL_SHIFT)) & IOMUXC_GPR_GPR11_M7_APC_AC_R2_CTRL_MASK) #define IOMUXC_GPR_GPR11_M7_APC_AC_R3_CTRL_MASK (0xC0U) #define IOMUXC_GPR_GPR11_M7_APC_AC_R3_CTRL_SHIFT (6U) +/*! M7_APC_AC_R3_CTRL + * 0b00..No access protection + * 0b01..M7 debug protection enabled + * 0b10..FlexSPI access protection + * 0b11..Both M7 debug and FlexSPI access are protected + */ #define IOMUXC_GPR_GPR11_M7_APC_AC_R3_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_M7_APC_AC_R3_CTRL_SHIFT)) & IOMUXC_GPR_GPR11_M7_APC_AC_R3_CTRL_MASK) #define IOMUXC_GPR_GPR11_BEE_DE_RX_EN_MASK (0xF00U) #define IOMUXC_GPR_GPR11_BEE_DE_RX_EN_SHIFT (8U) @@ -12494,164 +19692,338 @@ typedef struct { #define IOMUXC_GPR_GPR11_LOCK_BEE_DE_RX_EN_MASK (0xF000000U) #define IOMUXC_GPR_GPR11_LOCK_BEE_DE_RX_EN_SHIFT (24U) #define IOMUXC_GPR_GPR11_LOCK_BEE_DE_RX_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_LOCK_BEE_DE_RX_EN_SHIFT)) & IOMUXC_GPR_GPR11_LOCK_BEE_DE_RX_EN_MASK) +/*! @} */ /*! @name GPR12 - GPR12 General Purpose Register */ +/*! @{ */ #define IOMUXC_GPR_GPR12_FLEXIO1_IPG_STOP_MODE_MASK (0x1U) #define IOMUXC_GPR_GPR12_FLEXIO1_IPG_STOP_MODE_SHIFT (0U) +/*! FLEXIO1_IPG_STOP_MODE + * 0b0..FlexIO1 is functional in Stop mode. + * 0b1..When this bit is equal to 1'b1 and ipg_stop is asserted, FlexIO1 is not functional in Stop mode. + */ #define IOMUXC_GPR_GPR12_FLEXIO1_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_FLEXIO1_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR12_FLEXIO1_IPG_STOP_MODE_MASK) #define IOMUXC_GPR_GPR12_FLEXIO1_IPG_DOZE_MASK (0x2U) #define IOMUXC_GPR_GPR12_FLEXIO1_IPG_DOZE_SHIFT (1U) +/*! FLEXIO1_IPG_DOZE + * 0b0..FLEXIO1 is not in doze mode + * 0b1..FLEXIO1 is in doze mode + */ #define IOMUXC_GPR_GPR12_FLEXIO1_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_FLEXIO1_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR12_FLEXIO1_IPG_DOZE_MASK) #define IOMUXC_GPR_GPR12_FLEXIO2_IPG_STOP_MODE_MASK (0x4U) #define IOMUXC_GPR_GPR12_FLEXIO2_IPG_STOP_MODE_SHIFT (2U) +/*! FLEXIO2_IPG_STOP_MODE + * 0b0..FlexIO2 is functional in Stop mode. + * 0b1..When this bit is equal to 1'b1 and ipg_stop is asserted, FlexIO2 is not functional in Stop mode. + */ #define IOMUXC_GPR_GPR12_FLEXIO2_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_FLEXIO2_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR12_FLEXIO2_IPG_STOP_MODE_MASK) #define IOMUXC_GPR_GPR12_FLEXIO2_IPG_DOZE_MASK (0x8U) #define IOMUXC_GPR_GPR12_FLEXIO2_IPG_DOZE_SHIFT (3U) +/*! FLEXIO2_IPG_DOZE + * 0b0..FLEXIO2 is not in doze mode + * 0b1..FLEXIO2 is in doze mode + */ #define IOMUXC_GPR_GPR12_FLEXIO2_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_FLEXIO2_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR12_FLEXIO2_IPG_DOZE_MASK) #define IOMUXC_GPR_GPR12_ACMP_IPG_STOP_MODE_MASK (0x10U) #define IOMUXC_GPR_GPR12_ACMP_IPG_STOP_MODE_SHIFT (4U) +/*! ACMP_IPG_STOP_MODE + * 0b0..ACMP is functional in Stop mode. + * 0b1..When this bit is equal to 1'b1 and ipg_stop is asserted, ACMP is not functional in Stop mode. + */ #define IOMUXC_GPR_GPR12_ACMP_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_ACMP_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR12_ACMP_IPG_STOP_MODE_MASK) +/*! @} */ /*! @name GPR13 - GPR13 General Purpose Register */ +/*! @{ */ #define IOMUXC_GPR_GPR13_ARCACHE_USDHC_MASK (0x1U) #define IOMUXC_GPR_GPR13_ARCACHE_USDHC_SHIFT (0U) +/*! ARCACHE_USDHC + * 0b0..Cacheable attribute is off for read transactions. + * 0b1..Cacheable attribute is on for read transactions. + */ #define IOMUXC_GPR_GPR13_ARCACHE_USDHC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR13_ARCACHE_USDHC_SHIFT)) & IOMUXC_GPR_GPR13_ARCACHE_USDHC_MASK) #define IOMUXC_GPR_GPR13_AWCACHE_USDHC_MASK (0x2U) #define IOMUXC_GPR_GPR13_AWCACHE_USDHC_SHIFT (1U) +/*! AWCACHE_USDHC + * 0b0..Cacheable attribute is off for write transactions. + * 0b1..Cacheable attribute is on for write transactions. + */ #define IOMUXC_GPR_GPR13_AWCACHE_USDHC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR13_AWCACHE_USDHC_SHIFT)) & IOMUXC_GPR_GPR13_AWCACHE_USDHC_MASK) #define IOMUXC_GPR_GPR13_CACHE_ENET_MASK (0x80U) #define IOMUXC_GPR_GPR13_CACHE_ENET_SHIFT (7U) +/*! CACHE_ENET + * 0b0..Cacheable attribute is off for read/write transactions. + * 0b1..Cacheable attribute is on for read/write transactions. + */ #define IOMUXC_GPR_GPR13_CACHE_ENET(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR13_CACHE_ENET_SHIFT)) & IOMUXC_GPR_GPR13_CACHE_ENET_MASK) #define IOMUXC_GPR_GPR13_CACHE_USB_MASK (0x2000U) #define IOMUXC_GPR_GPR13_CACHE_USB_SHIFT (13U) +/*! CACHE_USB + * 0b0..Cacheable attribute is off for read/write transactions. + * 0b1..Cacheable attribute is on for read/write transactions. + */ #define IOMUXC_GPR_GPR13_CACHE_USB(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR13_CACHE_USB_SHIFT)) & IOMUXC_GPR_GPR13_CACHE_USB_MASK) +/*! @} */ /*! @name GPR14 - GPR14 General Purpose Register */ +/*! @{ */ #define IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_DN_MASK (0x1U) #define IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_DN_SHIFT (0U) +/*! ACMP1_CMP_IGEN_TRIM_DN + * 0b0..no reduce + * 0b1..reduces + */ #define IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_DN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_DN_SHIFT)) & IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_DN_MASK) #define IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_DN_MASK (0x2U) #define IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_DN_SHIFT (1U) +/*! ACMP2_CMP_IGEN_TRIM_DN + * 0b0..no reduce + * 0b1..reduces + */ #define IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_DN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_DN_SHIFT)) & IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_DN_MASK) #define IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_DN_MASK (0x4U) #define IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_DN_SHIFT (2U) +/*! ACMP3_CMP_IGEN_TRIM_DN + * 0b0..no reduce + * 0b1..reduces + */ #define IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_DN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_DN_SHIFT)) & IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_DN_MASK) #define IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_DN_MASK (0x8U) #define IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_DN_SHIFT (3U) +/*! ACMP4_CMP_IGEN_TRIM_DN + * 0b0..no reduce + * 0b1..reduces + */ #define IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_DN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_DN_SHIFT)) & IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_DN_MASK) #define IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_UP_MASK (0x10U) #define IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_UP_SHIFT (4U) +/*! ACMP1_CMP_IGEN_TRIM_UP + * 0b0..no increase + * 0b1..increases + */ #define IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_UP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_UP_SHIFT)) & IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_UP_MASK) #define IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_UP_MASK (0x20U) #define IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_UP_SHIFT (5U) +/*! ACMP2_CMP_IGEN_TRIM_UP + * 0b0..no increase + * 0b1..increases + */ #define IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_UP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_UP_SHIFT)) & IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_UP_MASK) #define IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_UP_MASK (0x40U) #define IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_UP_SHIFT (6U) +/*! ACMP3_CMP_IGEN_TRIM_UP + * 0b0..no increase + * 0b1..increases + */ #define IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_UP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_UP_SHIFT)) & IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_UP_MASK) #define IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_UP_MASK (0x80U) #define IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_UP_SHIFT (7U) +/*! ACMP4_CMP_IGEN_TRIM_UP + * 0b0..no increase + * 0b1..increases + */ #define IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_UP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_UP_SHIFT)) & IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_UP_MASK) #define IOMUXC_GPR_GPR14_ACMP1_SAMPLE_SYNC_EN_MASK (0x100U) #define IOMUXC_GPR_GPR14_ACMP1_SAMPLE_SYNC_EN_SHIFT (8U) +/*! ACMP1_SAMPLE_SYNC_EN + * 0b0..select XBAR output + * 0b1..select synced sample_lv + */ #define IOMUXC_GPR_GPR14_ACMP1_SAMPLE_SYNC_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP1_SAMPLE_SYNC_EN_SHIFT)) & IOMUXC_GPR_GPR14_ACMP1_SAMPLE_SYNC_EN_MASK) #define IOMUXC_GPR_GPR14_ACMP2_SAMPLE_SYNC_EN_MASK (0x200U) #define IOMUXC_GPR_GPR14_ACMP2_SAMPLE_SYNC_EN_SHIFT (9U) +/*! ACMP2_SAMPLE_SYNC_EN + * 0b0..select XBAR output + * 0b1..select synced sample_lv + */ #define IOMUXC_GPR_GPR14_ACMP2_SAMPLE_SYNC_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP2_SAMPLE_SYNC_EN_SHIFT)) & IOMUXC_GPR_GPR14_ACMP2_SAMPLE_SYNC_EN_MASK) #define IOMUXC_GPR_GPR14_ACMP3_SAMPLE_SYNC_EN_MASK (0x400U) #define IOMUXC_GPR_GPR14_ACMP3_SAMPLE_SYNC_EN_SHIFT (10U) +/*! ACMP3_SAMPLE_SYNC_EN + * 0b0..select XBAR output + * 0b1..select synced sample_lv + */ #define IOMUXC_GPR_GPR14_ACMP3_SAMPLE_SYNC_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP3_SAMPLE_SYNC_EN_SHIFT)) & IOMUXC_GPR_GPR14_ACMP3_SAMPLE_SYNC_EN_MASK) #define IOMUXC_GPR_GPR14_ACMP4_SAMPLE_SYNC_EN_MASK (0x800U) #define IOMUXC_GPR_GPR14_ACMP4_SAMPLE_SYNC_EN_SHIFT (11U) +/*! ACMP4_SAMPLE_SYNC_EN + * 0b0..select XBAR output + * 0b1..select synced sample_lv + */ #define IOMUXC_GPR_GPR14_ACMP4_SAMPLE_SYNC_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP4_SAMPLE_SYNC_EN_SHIFT)) & IOMUXC_GPR_GPR14_ACMP4_SAMPLE_SYNC_EN_MASK) -#define IOMUXC_GPR_GPR14_CM7_MX6RT_CFGITCMSZ_MASK (0xF0000U) -#define IOMUXC_GPR_GPR14_CM7_MX6RT_CFGITCMSZ_SHIFT (16U) -#define IOMUXC_GPR_GPR14_CM7_MX6RT_CFGITCMSZ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_CM7_MX6RT_CFGITCMSZ_SHIFT)) & IOMUXC_GPR_GPR14_CM7_MX6RT_CFGITCMSZ_MASK) -#define IOMUXC_GPR_GPR14_CM7_MX6RT_CFGDTCMSZ_MASK (0xF00000U) -#define IOMUXC_GPR_GPR14_CM7_MX6RT_CFGDTCMSZ_SHIFT (20U) -#define IOMUXC_GPR_GPR14_CM7_MX6RT_CFGDTCMSZ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_CM7_MX6RT_CFGDTCMSZ_SHIFT)) & IOMUXC_GPR_GPR14_CM7_MX6RT_CFGDTCMSZ_MASK) +#define IOMUXC_GPR_GPR14_CM7_CFGITCMSZ_MASK (0xF0000U) +#define IOMUXC_GPR_GPR14_CM7_CFGITCMSZ_SHIFT (16U) +/*! CM7_CFGITCMSZ + * 0b0000..0 KB (No ITCM) + * 0b0011..4 KB + * 0b0100..8 KB + * 0b0101..16 KB + * 0b0110..32 KB + * 0b0111..64 KB + * 0b1000..128 KB + * 0b1001..256 KB + * 0b1010..512 KB + */ +#define IOMUXC_GPR_GPR14_CM7_CFGITCMSZ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_CM7_CFGITCMSZ_SHIFT)) & IOMUXC_GPR_GPR14_CM7_CFGITCMSZ_MASK) +#define IOMUXC_GPR_GPR14_CM7_CFGDTCMSZ_MASK (0xF00000U) +#define IOMUXC_GPR_GPR14_CM7_CFGDTCMSZ_SHIFT (20U) +/*! CM7_CFGDTCMSZ + * 0b0000..0 KB (No DTCM) + * 0b0011..4 KB + * 0b0100..8 KB + * 0b0101..16 KB + * 0b0110..32 KB + * 0b0111..64 KB + * 0b1000..128 KB + * 0b1001..256 KB + * 0b1010..512 KB + */ +#define IOMUXC_GPR_GPR14_CM7_CFGDTCMSZ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_CM7_CFGDTCMSZ_SHIFT)) & IOMUXC_GPR_GPR14_CM7_CFGDTCMSZ_MASK) +/*! @} */ /*! @name GPR16 - GPR16 General Purpose Register */ +/*! @{ */ #define IOMUXC_GPR_GPR16_INIT_ITCM_EN_MASK (0x1U) #define IOMUXC_GPR_GPR16_INIT_ITCM_EN_SHIFT (0U) +/*! INIT_ITCM_EN + * 0b0..ITCM is disabled + * 0b1..ITCM is enabled + */ #define IOMUXC_GPR_GPR16_INIT_ITCM_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR16_INIT_ITCM_EN_SHIFT)) & IOMUXC_GPR_GPR16_INIT_ITCM_EN_MASK) #define IOMUXC_GPR_GPR16_INIT_DTCM_EN_MASK (0x2U) #define IOMUXC_GPR_GPR16_INIT_DTCM_EN_SHIFT (1U) +/*! INIT_DTCM_EN + * 0b0..DTCM is disabled + * 0b1..DTCM is enabled + */ #define IOMUXC_GPR_GPR16_INIT_DTCM_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR16_INIT_DTCM_EN_SHIFT)) & IOMUXC_GPR_GPR16_INIT_DTCM_EN_MASK) #define IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL_MASK (0x4U) #define IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL_SHIFT (2U) +/*! FLEXRAM_BANK_CFG_SEL + * 0b0..use fuse value to config + * 0b1..use FLEXRAM_BANK_CFG to config + */ #define IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL_SHIFT)) & IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL_MASK) -#define IOMUXC_GPR_GPR16_CM7_INIT_VTOR_MASK (0xFFFFFF80U) -#define IOMUXC_GPR_GPR16_CM7_INIT_VTOR_SHIFT (7U) -#define IOMUXC_GPR_GPR16_CM7_INIT_VTOR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR16_CM7_INIT_VTOR_SHIFT)) & IOMUXC_GPR_GPR16_CM7_INIT_VTOR_MASK) +/*! @} */ /*! @name GPR17 - GPR17 General Purpose Register */ +/*! @{ */ #define IOMUXC_GPR_GPR17_FLEXRAM_BANK_CFG_MASK (0xFFFFFFFFU) #define IOMUXC_GPR_GPR17_FLEXRAM_BANK_CFG_SHIFT (0U) #define IOMUXC_GPR_GPR17_FLEXRAM_BANK_CFG(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR17_FLEXRAM_BANK_CFG_SHIFT)) & IOMUXC_GPR_GPR17_FLEXRAM_BANK_CFG_MASK) +/*! @} */ /*! @name GPR18 - GPR18 General Purpose Register */ +/*! @{ */ #define IOMUXC_GPR_GPR18_LOCK_M7_APC_AC_R0_BOT_MASK (0x1U) #define IOMUXC_GPR_GPR18_LOCK_M7_APC_AC_R0_BOT_SHIFT (0U) +/*! LOCK_M7_APC_AC_R0_BOT + * 0b0..Register field [31:1] is not locked + * 0b1..Register field [31:1] is locked (read access only) + */ #define IOMUXC_GPR_GPR18_LOCK_M7_APC_AC_R0_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR18_LOCK_M7_APC_AC_R0_BOT_SHIFT)) & IOMUXC_GPR_GPR18_LOCK_M7_APC_AC_R0_BOT_MASK) #define IOMUXC_GPR_GPR18_M7_APC_AC_R0_BOT_MASK (0xFFFFFFF8U) #define IOMUXC_GPR_GPR18_M7_APC_AC_R0_BOT_SHIFT (3U) #define IOMUXC_GPR_GPR18_M7_APC_AC_R0_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR18_M7_APC_AC_R0_BOT_SHIFT)) & IOMUXC_GPR_GPR18_M7_APC_AC_R0_BOT_MASK) +/*! @} */ /*! @name GPR19 - GPR19 General Purpose Register */ +/*! @{ */ #define IOMUXC_GPR_GPR19_LOCK_M7_APC_AC_R0_TOP_MASK (0x1U) #define IOMUXC_GPR_GPR19_LOCK_M7_APC_AC_R0_TOP_SHIFT (0U) +/*! LOCK_M7_APC_AC_R0_TOP + * 0b0..Register field [31:1] is not locked + * 0b1..Register field [31:1] is locked (read access only) + */ #define IOMUXC_GPR_GPR19_LOCK_M7_APC_AC_R0_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR19_LOCK_M7_APC_AC_R0_TOP_SHIFT)) & IOMUXC_GPR_GPR19_LOCK_M7_APC_AC_R0_TOP_MASK) #define IOMUXC_GPR_GPR19_M7_APC_AC_R0_TOP_MASK (0xFFFFFFF8U) #define IOMUXC_GPR_GPR19_M7_APC_AC_R0_TOP_SHIFT (3U) #define IOMUXC_GPR_GPR19_M7_APC_AC_R0_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR19_M7_APC_AC_R0_TOP_SHIFT)) & IOMUXC_GPR_GPR19_M7_APC_AC_R0_TOP_MASK) +/*! @} */ /*! @name GPR20 - GPR20 General Purpose Register */ +/*! @{ */ #define IOMUXC_GPR_GPR20_LOCK_M7_APC_AC_R1_BOT_MASK (0x1U) #define IOMUXC_GPR_GPR20_LOCK_M7_APC_AC_R1_BOT_SHIFT (0U) +/*! LOCK_M7_APC_AC_R1_BOT + * 0b0..Register field [31:1] is not locked + * 0b1..Register field [31:1] is locked (read access only) + */ #define IOMUXC_GPR_GPR20_LOCK_M7_APC_AC_R1_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_LOCK_M7_APC_AC_R1_BOT_SHIFT)) & IOMUXC_GPR_GPR20_LOCK_M7_APC_AC_R1_BOT_MASK) #define IOMUXC_GPR_GPR20_M7_APC_AC_R1_BOT_MASK (0xFFFFFFF8U) #define IOMUXC_GPR_GPR20_M7_APC_AC_R1_BOT_SHIFT (3U) #define IOMUXC_GPR_GPR20_M7_APC_AC_R1_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_M7_APC_AC_R1_BOT_SHIFT)) & IOMUXC_GPR_GPR20_M7_APC_AC_R1_BOT_MASK) +/*! @} */ /*! @name GPR21 - GPR21 General Purpose Register */ +/*! @{ */ #define IOMUXC_GPR_GPR21_LOCK_M7_APC_AC_R1_TOP_MASK (0x1U) #define IOMUXC_GPR_GPR21_LOCK_M7_APC_AC_R1_TOP_SHIFT (0U) +/*! LOCK_M7_APC_AC_R1_TOP + * 0b0..Register field [31:1] is not locked + * 0b1..Register field [31:1] is locked (read access only) + */ #define IOMUXC_GPR_GPR21_LOCK_M7_APC_AC_R1_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR21_LOCK_M7_APC_AC_R1_TOP_SHIFT)) & IOMUXC_GPR_GPR21_LOCK_M7_APC_AC_R1_TOP_MASK) #define IOMUXC_GPR_GPR21_M7_APC_AC_R1_TOP_MASK (0xFFFFFFF8U) #define IOMUXC_GPR_GPR21_M7_APC_AC_R1_TOP_SHIFT (3U) #define IOMUXC_GPR_GPR21_M7_APC_AC_R1_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR21_M7_APC_AC_R1_TOP_SHIFT)) & IOMUXC_GPR_GPR21_M7_APC_AC_R1_TOP_MASK) +/*! @} */ /*! @name GPR22 - GPR22 General Purpose Register */ +/*! @{ */ #define IOMUXC_GPR_GPR22_LOCK_M7_APC_AC_R2_BOT_MASK (0x1U) #define IOMUXC_GPR_GPR22_LOCK_M7_APC_AC_R2_BOT_SHIFT (0U) +/*! LOCK_M7_APC_AC_R2_BOT + * 0b0..Register field [31:1] is not locked + * 0b1..Register field [31:1] is locked (read access only) + */ #define IOMUXC_GPR_GPR22_LOCK_M7_APC_AC_R2_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR22_LOCK_M7_APC_AC_R2_BOT_SHIFT)) & IOMUXC_GPR_GPR22_LOCK_M7_APC_AC_R2_BOT_MASK) #define IOMUXC_GPR_GPR22_M7_APC_AC_R2_BOT_MASK (0xFFFFFFF8U) #define IOMUXC_GPR_GPR22_M7_APC_AC_R2_BOT_SHIFT (3U) #define IOMUXC_GPR_GPR22_M7_APC_AC_R2_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR22_M7_APC_AC_R2_BOT_SHIFT)) & IOMUXC_GPR_GPR22_M7_APC_AC_R2_BOT_MASK) +/*! @} */ /*! @name GPR23 - GPR23 General Purpose Register */ -#define IOMUXC_GPR_GPR23_LOCK_M7_APC_AC_R1_TOP_MASK (0x1U) -#define IOMUXC_GPR_GPR23_LOCK_M7_APC_AC_R1_TOP_SHIFT (0U) -#define IOMUXC_GPR_GPR23_LOCK_M7_APC_AC_R1_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR23_LOCK_M7_APC_AC_R1_TOP_SHIFT)) & IOMUXC_GPR_GPR23_LOCK_M7_APC_AC_R1_TOP_MASK) +/*! @{ */ +#define IOMUXC_GPR_GPR23_LOCK_M7_APC_AC_R2_TOP_MASK (0x1U) +#define IOMUXC_GPR_GPR23_LOCK_M7_APC_AC_R2_TOP_SHIFT (0U) +/*! LOCK_M7_APC_AC_R2_TOP + * 0b0..Register field [31:1] is not locked + * 0b1..Register field [31:1] is locked (read access only) + */ +#define IOMUXC_GPR_GPR23_LOCK_M7_APC_AC_R2_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR23_LOCK_M7_APC_AC_R2_TOP_SHIFT)) & IOMUXC_GPR_GPR23_LOCK_M7_APC_AC_R2_TOP_MASK) #define IOMUXC_GPR_GPR23_M7_APC_AC_R2_TOP_MASK (0xFFFFFFF8U) #define IOMUXC_GPR_GPR23_M7_APC_AC_R2_TOP_SHIFT (3U) #define IOMUXC_GPR_GPR23_M7_APC_AC_R2_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR23_M7_APC_AC_R2_TOP_SHIFT)) & IOMUXC_GPR_GPR23_M7_APC_AC_R2_TOP_MASK) +/*! @} */ /*! @name GPR24 - GPR24 General Purpose Register */ +/*! @{ */ #define IOMUXC_GPR_GPR24_LOCK_M7_APC_AC_R3_BOT_MASK (0x1U) #define IOMUXC_GPR_GPR24_LOCK_M7_APC_AC_R3_BOT_SHIFT (0U) +/*! LOCK_M7_APC_AC_R3_BOT + * 0b0..Register field [31:1] is not locked + * 0b1..Register field [31:1] is locked (read access only) + */ #define IOMUXC_GPR_GPR24_LOCK_M7_APC_AC_R3_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR24_LOCK_M7_APC_AC_R3_BOT_SHIFT)) & IOMUXC_GPR_GPR24_LOCK_M7_APC_AC_R3_BOT_MASK) -#define IOMUXC_GPR_GPR24_M7_APC_AC_R2_BOT_MASK (0xFFFFFFF8U) -#define IOMUXC_GPR_GPR24_M7_APC_AC_R2_BOT_SHIFT (3U) -#define IOMUXC_GPR_GPR24_M7_APC_AC_R2_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR24_M7_APC_AC_R2_BOT_SHIFT)) & IOMUXC_GPR_GPR24_M7_APC_AC_R2_BOT_MASK) +#define IOMUXC_GPR_GPR24_M7_APC_AC_R3_BOT_MASK (0xFFFFFFF8U) +#define IOMUXC_GPR_GPR24_M7_APC_AC_R3_BOT_SHIFT (3U) +#define IOMUXC_GPR_GPR24_M7_APC_AC_R3_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR24_M7_APC_AC_R3_BOT_SHIFT)) & IOMUXC_GPR_GPR24_M7_APC_AC_R3_BOT_MASK) +/*! @} */ /*! @name GPR25 - GPR25 General Purpose Register */ +/*! @{ */ #define IOMUXC_GPR_GPR25_LOCK_M7_APC_AC_R3_TOP_MASK (0x1U) #define IOMUXC_GPR_GPR25_LOCK_M7_APC_AC_R3_TOP_SHIFT (0U) +/*! LOCK_M7_APC_AC_R3_TOP + * 0b0..Register field [31:1] is not locked + * 0b1..Register field [31:1] is locked (read access only) + */ #define IOMUXC_GPR_GPR25_LOCK_M7_APC_AC_R3_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR25_LOCK_M7_APC_AC_R3_TOP_SHIFT)) & IOMUXC_GPR_GPR25_LOCK_M7_APC_AC_R3_TOP_MASK) #define IOMUXC_GPR_GPR25_M7_APC_AC_R3_TOP_MASK (0xFFFFFFF8U) #define IOMUXC_GPR_GPR25_M7_APC_AC_R3_TOP_SHIFT (3U) #define IOMUXC_GPR_GPR25_M7_APC_AC_R3_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR25_M7_APC_AC_R3_TOP_SHIFT)) & IOMUXC_GPR_GPR25_M7_APC_AC_R3_TOP_MASK) +/*! @} */ /*! @@ -12706,184 +20078,460 @@ typedef struct { */ /*! @name SW_MUX_CTL_PAD_WAKEUP - SW_MUX_CTL_PAD_WAKEUP SW MUX Control Register */ +/*! @{ */ #define IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_MUX_MODE_MASK (0x7U) #define IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_MUX_MODE_SHIFT (0U) +/*! MUX_MODE - MUX Mode Select Field. + * 0b101..Select mux mode: ALT5 mux port: GPIO5_IO00 of instance: gpio5 + * 0b111..Select mux mode: ALT7 mux port: NMI_GLUE_NMI of instance: nmi_glue + */ #define IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_MUX_MODE_MASK) #define IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_SION_MASK (0x10U) #define IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_SION_SHIFT (4U) +/*! SION - Software Input On Field. + * 0b1..Force input path of pad WAKEUP + * 0b0..Input Path is determined by functionality + */ #define IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_SION_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_SION_MASK) +/*! @} */ /*! @name SW_MUX_CTL_PAD_PMIC_ON_REQ - SW_MUX_CTL_PAD_PMIC_ON_REQ SW MUX Control Register */ +/*! @{ */ #define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_MUX_MODE_MASK (0x7U) #define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_MUX_MODE_SHIFT (0U) +/*! MUX_MODE - MUX Mode Select Field. + * 0b000..Select mux mode: ALT0 mux port: SNVS_LP_PMIC_ON_REQ of instance: snvs_lp + * 0b101..Select mux mode: ALT5 mux port: GPIO5_IO01 of instance: gpio5 + */ #define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_MUX_MODE_MASK) #define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_SION_MASK (0x10U) #define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_SION_SHIFT (4U) +/*! SION - Software Input On Field. + * 0b1..Force input path of pad PMIC_ON_REQ + * 0b0..Input Path is determined by functionality + */ #define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_SION_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_SION_MASK) +/*! @} */ /*! @name SW_MUX_CTL_PAD_PMIC_STBY_REQ - SW_MUX_CTL_PAD_PMIC_STBY_REQ SW MUX Control Register */ +/*! @{ */ #define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_MUX_MODE_MASK (0x7U) #define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_MUX_MODE_SHIFT (0U) +/*! MUX_MODE - MUX Mode Select Field. + * 0b000..Select mux mode: ALT0 mux port: CCM_PMIC_VSTBY_REQ of instance: ccm + * 0b101..Select mux mode: ALT5 mux port: GPIO5_IO02 of instance: gpio5 + */ #define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_MUX_MODE_MASK) #define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_SION_MASK (0x10U) #define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_SION_SHIFT (4U) +/*! SION - Software Input On Field. + * 0b1..Force input path of pad PMIC_STBY_REQ + * 0b0..Input Path is determined by functionality + */ #define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_SION_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_SION_MASK) +/*! @} */ /*! @name SW_PAD_CTL_PAD_TEST_MODE - SW_PAD_CTL_PAD_TEST_MODE SW PAD Control Register */ +/*! @{ */ #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SRE_MASK (0x1U) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SRE_SHIFT (0U) +/*! SRE - Slew Rate Field + * 0b0..Slow Slew Rate + * 0b1..Fast Slew Rate + */ #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SRE_MASK) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DSE_MASK (0x38U) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DSE_SHIFT (3U) +/*! DSE - Drive Strength Field + * 0b000..output driver disabled; + * 0b001..R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + * 0b010..R0/2 + * 0b011..R0/3 + * 0b100..R0/4 + * 0b101..R0/5 + * 0b110..R0/6 + * 0b111..R0/7 + */ #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DSE_MASK) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SPEED_MASK (0xC0U) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SPEED_SHIFT (6U) +/*! SPEED - Speed Field + * 0b10..medium(100MHz) + */ #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SPEED(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SPEED_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SPEED_MASK) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_ODE_MASK (0x800U) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_ODE_SHIFT (11U) +/*! ODE - Open Drain Enable Field + * 0b0..Open Drain Disabled + * 0b1..Open Drain Enabled + */ #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_ODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_ODE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_ODE_MASK) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PKE_MASK (0x1000U) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PKE_SHIFT (12U) +/*! PKE - Pull / Keep Enable Field + * 0b0..Pull/Keeper Disabled + * 0b1..Pull/Keeper Enabled + */ #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PKE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PKE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PKE_MASK) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUE_MASK (0x2000U) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUE_SHIFT (13U) +/*! PUE - Pull / Keep Select Field + * 0b0..Keeper + * 0b1..Pull + */ #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUE_MASK) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUS_MASK (0xC000U) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUS_SHIFT (14U) +/*! PUS - Pull Up / Down Config. Field + * 0b00..100K Ohm Pull Down + * 0b01..47K Ohm Pull Up + * 0b10..100K Ohm Pull Up + * 0b11..22K Ohm Pull Up + */ #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUS_MASK) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_HYS_MASK (0x10000U) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_HYS_SHIFT (16U) +/*! HYS - Hyst. Enable Field + * 0b0..Hysteresis Disabled + * 0b1..Hysteresis Enabled + */ #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_HYS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_HYS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_HYS_MASK) +/*! @} */ /*! @name SW_PAD_CTL_PAD_POR_B - SW_PAD_CTL_PAD_POR_B SW PAD Control Register */ +/*! @{ */ #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SRE_MASK (0x1U) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SRE_SHIFT (0U) +/*! SRE - Slew Rate Field + * 0b0..Slow Slew Rate + * 0b1..Fast Slew Rate + */ #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SRE_MASK) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DSE_MASK (0x38U) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DSE_SHIFT (3U) +/*! DSE - Drive Strength Field + * 0b000..output driver disabled; + * 0b001..R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + * 0b010..R0/2 + * 0b011..R0/3 + * 0b100..R0/4 + * 0b101..R0/5 + * 0b110..R0/6 + * 0b111..R0/7 + */ #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DSE_MASK) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SPEED_MASK (0xC0U) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SPEED_SHIFT (6U) +/*! SPEED - Speed Field + * 0b10..medium(100MHz) + */ #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SPEED(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SPEED_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SPEED_MASK) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_ODE_MASK (0x800U) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_ODE_SHIFT (11U) +/*! ODE - Open Drain Enable Field + * 0b0..Open Drain Disabled + * 0b1..Open Drain Enabled + */ #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_ODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_ODE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_ODE_MASK) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PKE_MASK (0x1000U) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PKE_SHIFT (12U) +/*! PKE - Pull / Keep Enable Field + * 0b0..Pull/Keeper Disabled + * 0b1..Pull/Keeper Enabled + */ #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PKE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PKE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PKE_MASK) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUE_MASK (0x2000U) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUE_SHIFT (13U) +/*! PUE - Pull / Keep Select Field + * 0b0..Keeper + * 0b1..Pull + */ #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUE_MASK) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUS_MASK (0xC000U) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUS_SHIFT (14U) +/*! PUS - Pull Up / Down Config. Field + * 0b00..100K Ohm Pull Down + * 0b01..47K Ohm Pull Up + * 0b10..100K Ohm Pull Up + * 0b11..22K Ohm Pull Up + */ #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUS_MASK) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_HYS_MASK (0x10000U) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_HYS_SHIFT (16U) +/*! HYS - Hyst. Enable Field + * 0b0..Hysteresis Disabled + * 0b1..Hysteresis Enabled + */ #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_HYS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_HYS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_HYS_MASK) +/*! @} */ /*! @name SW_PAD_CTL_PAD_ONOFF - SW_PAD_CTL_PAD_ONOFF SW PAD Control Register */ +/*! @{ */ #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SRE_MASK (0x1U) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SRE_SHIFT (0U) +/*! SRE - Slew Rate Field + * 0b0..Slow Slew Rate + * 0b1..Fast Slew Rate + */ #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SRE_MASK) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DSE_MASK (0x38U) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DSE_SHIFT (3U) +/*! DSE - Drive Strength Field + * 0b000..output driver disabled; + * 0b001..R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + * 0b010..R0/2 + * 0b011..R0/3 + * 0b100..R0/4 + * 0b101..R0/5 + * 0b110..R0/6 + * 0b111..R0/7 + */ #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DSE_MASK) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SPEED_MASK (0xC0U) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SPEED_SHIFT (6U) +/*! SPEED - Speed Field + * 0b10..medium(100MHz) + */ #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SPEED(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SPEED_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SPEED_MASK) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_ODE_MASK (0x800U) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_ODE_SHIFT (11U) +/*! ODE - Open Drain Enable Field + * 0b0..Open Drain Disabled + * 0b1..Open Drain Enabled + */ #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_ODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_ODE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_ODE_MASK) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PKE_MASK (0x1000U) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PKE_SHIFT (12U) +/*! PKE - Pull / Keep Enable Field + * 0b0..Pull/Keeper Disabled + * 0b1..Pull/Keeper Enabled + */ #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PKE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PKE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PKE_MASK) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUE_MASK (0x2000U) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUE_SHIFT (13U) +/*! PUE - Pull / Keep Select Field + * 0b0..Keeper + * 0b1..Pull + */ #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUE_MASK) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUS_MASK (0xC000U) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUS_SHIFT (14U) +/*! PUS - Pull Up / Down Config. Field + * 0b00..100K Ohm Pull Down + * 0b01..47K Ohm Pull Up + * 0b10..100K Ohm Pull Up + * 0b11..22K Ohm Pull Up + */ #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUS_MASK) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_HYS_MASK (0x10000U) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_HYS_SHIFT (16U) +/*! HYS - Hyst. Enable Field + * 0b0..Hysteresis Disabled + * 0b1..Hysteresis Enabled + */ #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_HYS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_HYS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_HYS_MASK) +/*! @} */ /*! @name SW_PAD_CTL_PAD_WAKEUP - SW_PAD_CTL_PAD_WAKEUP SW PAD Control Register */ +/*! @{ */ #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SRE_MASK (0x1U) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SRE_SHIFT (0U) +/*! SRE - Slew Rate Field + * 0b0..Slow Slew Rate + * 0b1..Fast Slew Rate + */ #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SRE_MASK) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DSE_MASK (0x38U) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DSE_SHIFT (3U) +/*! DSE - Drive Strength Field + * 0b000..output driver disabled; + * 0b001..R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + * 0b010..R0/2 + * 0b011..R0/3 + * 0b100..R0/4 + * 0b101..R0/5 + * 0b110..R0/6 + * 0b111..R0/7 + */ #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DSE_MASK) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SPEED_MASK (0xC0U) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SPEED_SHIFT (6U) +/*! SPEED - Speed Field + * 0b10..medium(100MHz) + */ #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SPEED(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SPEED_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SPEED_MASK) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_ODE_MASK (0x800U) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_ODE_SHIFT (11U) +/*! ODE - Open Drain Enable Field + * 0b0..Open Drain Disabled + * 0b1..Open Drain Enabled + */ #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_ODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_ODE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_ODE_MASK) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PKE_MASK (0x1000U) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PKE_SHIFT (12U) +/*! PKE - Pull / Keep Enable Field + * 0b0..Pull/Keeper Disabled + * 0b1..Pull/Keeper Enabled + */ #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PKE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PKE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PKE_MASK) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUE_MASK (0x2000U) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUE_SHIFT (13U) +/*! PUE - Pull / Keep Select Field + * 0b0..Keeper + * 0b1..Pull + */ #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUE_MASK) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUS_MASK (0xC000U) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUS_SHIFT (14U) +/*! PUS - Pull Up / Down Config. Field + * 0b00..100K Ohm Pull Down + * 0b01..47K Ohm Pull Up + * 0b10..100K Ohm Pull Up + * 0b11..22K Ohm Pull Up + */ #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUS_MASK) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_HYS_MASK (0x10000U) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_HYS_SHIFT (16U) +/*! HYS - Hyst. Enable Field + * 0b0..Hysteresis Disabled + * 0b1..Hysteresis Enabled + */ #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_HYS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_HYS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_HYS_MASK) +/*! @} */ /*! @name SW_PAD_CTL_PAD_PMIC_ON_REQ - SW_PAD_CTL_PAD_PMIC_ON_REQ SW PAD Control Register */ +/*! @{ */ #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SRE_MASK (0x1U) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SRE_SHIFT (0U) +/*! SRE - Slew Rate Field + * 0b0..Slow Slew Rate + * 0b1..Fast Slew Rate + */ #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SRE_MASK) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DSE_MASK (0x38U) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DSE_SHIFT (3U) +/*! DSE - Drive Strength Field + * 0b000..output driver disabled; + * 0b001..R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + * 0b010..R0/2 + * 0b011..R0/3 + * 0b100..R0/4 + * 0b101..R0/5 + * 0b110..R0/6 + * 0b111..R0/7 + */ #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DSE_MASK) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SPEED_MASK (0xC0U) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SPEED_SHIFT (6U) +/*! SPEED - Speed Field + * 0b10..medium(100MHz) + */ #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SPEED(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SPEED_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SPEED_MASK) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_ODE_MASK (0x800U) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_ODE_SHIFT (11U) +/*! ODE - Open Drain Enable Field + * 0b0..Open Drain Disabled + * 0b1..Open Drain Enabled + */ #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_ODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_ODE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_ODE_MASK) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PKE_MASK (0x1000U) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PKE_SHIFT (12U) +/*! PKE - Pull / Keep Enable Field + * 0b0..Pull/Keeper Disabled + * 0b1..Pull/Keeper Enabled + */ #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PKE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PKE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PKE_MASK) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUE_MASK (0x2000U) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUE_SHIFT (13U) +/*! PUE - Pull / Keep Select Field + * 0b0..Keeper + * 0b1..Pull + */ #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUE_MASK) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUS_MASK (0xC000U) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUS_SHIFT (14U) +/*! PUS - Pull Up / Down Config. Field + * 0b00..100K Ohm Pull Down + * 0b01..47K Ohm Pull Up + * 0b10..100K Ohm Pull Up + * 0b11..22K Ohm Pull Up + */ #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUS_MASK) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_HYS_MASK (0x10000U) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_HYS_SHIFT (16U) +/*! HYS - Hyst. Enable Field + * 0b0..Hysteresis Disabled + * 0b1..Hysteresis Enabled + */ #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_HYS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_HYS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_HYS_MASK) +/*! @} */ /*! @name SW_PAD_CTL_PAD_PMIC_STBY_REQ - SW_PAD_CTL_PAD_PMIC_STBY_REQ SW PAD Control Register */ +/*! @{ */ #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SRE_MASK (0x1U) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SRE_SHIFT (0U) +/*! SRE - Slew Rate Field + * 0b0..Slow Slew Rate + * 0b1..Fast Slew Rate + */ #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SRE_MASK) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DSE_MASK (0x38U) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DSE_SHIFT (3U) +/*! DSE - Drive Strength Field + * 0b000..output driver disabled; + * 0b001..R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + * 0b010..R0/2 + * 0b011..R0/3 + * 0b100..R0/4 + * 0b101..R0/5 + * 0b110..R0/6 + * 0b111..R0/7 + */ #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DSE_MASK) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SPEED_MASK (0xC0U) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SPEED_SHIFT (6U) +/*! SPEED - Speed Field + * 0b10..medium(100MHz) + */ #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SPEED(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SPEED_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SPEED_MASK) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_ODE_MASK (0x800U) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_ODE_SHIFT (11U) +/*! ODE - Open Drain Enable Field + * 0b0..Open Drain Disabled + * 0b1..Open Drain Enabled + */ #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_ODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_ODE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_ODE_MASK) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PKE_MASK (0x1000U) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PKE_SHIFT (12U) +/*! PKE - Pull / Keep Enable Field + * 0b0..Pull/Keeper Disabled + * 0b1..Pull/Keeper Enabled + */ #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PKE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PKE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PKE_MASK) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUE_MASK (0x2000U) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUE_SHIFT (13U) +/*! PUE - Pull / Keep Select Field + * 0b0..Keeper + * 0b1..Pull + */ #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUE_MASK) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUS_MASK (0xC000U) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUS_SHIFT (14U) +/*! PUS - Pull Up / Down Config. Field + * 0b00..100K Ohm Pull Down + * 0b01..47K Ohm Pull Up + * 0b10..100K Ohm Pull Up + * 0b11..22K Ohm Pull Up + */ #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUS_MASK) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_HYS_MASK (0x10000U) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_HYS_SHIFT (16U) +/*! HYS - Hyst. Enable Field + * 0b0..Hysteresis Disabled + * 0b1..Hysteresis Enabled + */ #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_HYS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_HYS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_HYS_MASK) +/*! @} */ /*! @@ -12933,6 +20581,7 @@ typedef struct { */ /*! @name GPR3 - GPR3 General Purpose Register */ +/*! @{ */ #define IOMUXC_SNVS_GPR_GPR3_LPSR_MODE_ENABLE_MASK (0x1U) #define IOMUXC_SNVS_GPR_GPR3_LPSR_MODE_ENABLE_SHIFT (0U) #define IOMUXC_SNVS_GPR_GPR3_LPSR_MODE_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR3_LPSR_MODE_ENABLE_SHIFT)) & IOMUXC_SNVS_GPR_GPR3_LPSR_MODE_ENABLE_MASK) @@ -12942,9 +20591,9 @@ typedef struct { #define IOMUXC_SNVS_GPR_GPR3_POR_PULL_TYPE_MASK (0xCU) #define IOMUXC_SNVS_GPR_GPR3_POR_PULL_TYPE_SHIFT (2U) #define IOMUXC_SNVS_GPR_GPR3_POR_PULL_TYPE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR3_POR_PULL_TYPE_SHIFT)) & IOMUXC_SNVS_GPR_GPR3_POR_PULL_TYPE_MASK) -#define IOMUXC_SNVS_GPR_GPR3_DCDC_LOW_BAT_MASK (0x10000U) -#define IOMUXC_SNVS_GPR_GPR3_DCDC_LOW_BAT_SHIFT (16U) -#define IOMUXC_SNVS_GPR_GPR3_DCDC_LOW_BAT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR3_DCDC_LOW_BAT_SHIFT)) & IOMUXC_SNVS_GPR_GPR3_DCDC_LOW_BAT_MASK) +#define IOMUXC_SNVS_GPR_GPR3_DCDC_IN_LOW_VOL_MASK (0x10000U) +#define IOMUXC_SNVS_GPR_GPR3_DCDC_IN_LOW_VOL_SHIFT (16U) +#define IOMUXC_SNVS_GPR_GPR3_DCDC_IN_LOW_VOL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR3_DCDC_IN_LOW_VOL_SHIFT)) & IOMUXC_SNVS_GPR_GPR3_DCDC_IN_LOW_VOL_MASK) #define IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_CUR_MASK (0x20000U) #define IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_CUR_SHIFT (17U) #define IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_CUR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_CUR_SHIFT)) & IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_CUR_MASK) @@ -12954,6 +20603,7 @@ typedef struct { #define IOMUXC_SNVS_GPR_GPR3_DCDC_STS_DC_OK_MASK (0x80000U) #define IOMUXC_SNVS_GPR_GPR3_DCDC_STS_DC_OK_SHIFT (19U) #define IOMUXC_SNVS_GPR_GPR3_DCDC_STS_DC_OK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR3_DCDC_STS_DC_OK_SHIFT)) & IOMUXC_SNVS_GPR_GPR3_DCDC_STS_DC_OK_MASK) +/*! @} */ /*! @@ -13003,48 +20653,96 @@ typedef struct { */ /*! @name KPCR - Keypad Control Register */ +/*! @{ */ #define KPP_KPCR_KRE_MASK (0xFFU) #define KPP_KPCR_KRE_SHIFT (0U) +/*! KRE + * 0b00000000..Row is not included in the keypad key press detect. + * 0b00000001..Row is included in the keypad key press detect. + */ #define KPP_KPCR_KRE(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPCR_KRE_SHIFT)) & KPP_KPCR_KRE_MASK) #define KPP_KPCR_KCO_MASK (0xFF00U) #define KPP_KPCR_KCO_SHIFT (8U) +/*! KCO + * 0b00000000..Column strobe output is totem pole drive. + * 0b00000001..Column strobe output is open drain. + */ #define KPP_KPCR_KCO(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPCR_KCO_SHIFT)) & KPP_KPCR_KCO_MASK) +/*! @} */ /*! @name KPSR - Keypad Status Register */ +/*! @{ */ #define KPP_KPSR_KPKD_MASK (0x1U) #define KPP_KPSR_KPKD_SHIFT (0U) +/*! KPKD + * 0b0..No key presses detected + * 0b1..A key has been depressed + */ #define KPP_KPSR_KPKD(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KPKD_SHIFT)) & KPP_KPSR_KPKD_MASK) #define KPP_KPSR_KPKR_MASK (0x2U) #define KPP_KPSR_KPKR_SHIFT (1U) +/*! KPKR + * 0b0..No key release detected + * 0b1..All keys have been released + */ #define KPP_KPSR_KPKR(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KPKR_SHIFT)) & KPP_KPSR_KPKR_MASK) #define KPP_KPSR_KDSC_MASK (0x4U) #define KPP_KPSR_KDSC_SHIFT (2U) +/*! KDSC + * 0b0..No effect + * 0b1..Set bits that clear the keypad depress synchronizer chain + */ #define KPP_KPSR_KDSC(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KDSC_SHIFT)) & KPP_KPSR_KDSC_MASK) #define KPP_KPSR_KRSS_MASK (0x8U) #define KPP_KPSR_KRSS_SHIFT (3U) +/*! KRSS + * 0b0..No effect + * 0b1..Set bits which sets keypad release synchronizer chain + */ #define KPP_KPSR_KRSS(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KRSS_SHIFT)) & KPP_KPSR_KRSS_MASK) #define KPP_KPSR_KDIE_MASK (0x100U) #define KPP_KPSR_KDIE_SHIFT (8U) +/*! KDIE + * 0b0..No interrupt request is generated when KPKD is set. + * 0b1..An interrupt request is generated when KPKD is set. + */ #define KPP_KPSR_KDIE(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KDIE_SHIFT)) & KPP_KPSR_KDIE_MASK) #define KPP_KPSR_KRIE_MASK (0x200U) #define KPP_KPSR_KRIE_SHIFT (9U) +/*! KRIE + * 0b0..No interrupt request is generated when KPKR is set. + * 0b1..An interrupt request is generated when KPKR is set. + */ #define KPP_KPSR_KRIE(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KRIE_SHIFT)) & KPP_KPSR_KRIE_MASK) +/*! @} */ /*! @name KDDR - Keypad Data Direction Register */ +/*! @{ */ #define KPP_KDDR_KRDD_MASK (0xFFU) #define KPP_KDDR_KRDD_SHIFT (0U) +/*! KRDD + * 0b00000000..ROWn pin configured as an input. + * 0b00000001..ROWn pin configured as an output. + */ #define KPP_KDDR_KRDD(x) (((uint16_t)(((uint16_t)(x)) << KPP_KDDR_KRDD_SHIFT)) & KPP_KDDR_KRDD_MASK) #define KPP_KDDR_KCDD_MASK (0xFF00U) #define KPP_KDDR_KCDD_SHIFT (8U) +/*! KCDD + * 0b00000000..COLn pin is configured as an input. + * 0b00000001..COLn pin is configured as an output. + */ #define KPP_KDDR_KCDD(x) (((uint16_t)(((uint16_t)(x)) << KPP_KDDR_KCDD_SHIFT)) & KPP_KDDR_KCDD_MASK) +/*! @} */ /*! @name KPDR - Keypad Data Register */ +/*! @{ */ #define KPP_KPDR_KRD_MASK (0xFFU) #define KPP_KPDR_KRD_SHIFT (0U) #define KPP_KPDR_KRD(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPDR_KRD_SHIFT)) & KPP_KPDR_KRD_MASK) #define KPP_KPDR_KCD_MASK (0xFF00U) #define KPP_KPDR_KCD_SHIFT (8U) #define KPP_KPDR_KCD(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPDR_KCD_SHIFT)) & KPP_KPDR_KCD_MASK) +/*! @} */ /*! @@ -13080,35 +20778,35 @@ typedef struct { /** LCDIF - Register Layout Typedef */ typedef struct { - __IO uint32_t CTRL; /**< eLCDIF General Control Register, offset: 0x0 */ - __IO uint32_t CTRL_SET; /**< eLCDIF General Control Register, offset: 0x4 */ - __IO uint32_t CTRL_CLR; /**< eLCDIF General Control Register, offset: 0x8 */ - __IO uint32_t CTRL_TOG; /**< eLCDIF General Control Register, offset: 0xC */ - __IO uint32_t CTRL1; /**< eLCDIF General Control1 Register, offset: 0x10 */ - __IO uint32_t CTRL1_SET; /**< eLCDIF General Control1 Register, offset: 0x14 */ - __IO uint32_t CTRL1_CLR; /**< eLCDIF General Control1 Register, offset: 0x18 */ - __IO uint32_t CTRL1_TOG; /**< eLCDIF General Control1 Register, offset: 0x1C */ - __IO uint32_t CTRL2; /**< eLCDIF General Control2 Register, offset: 0x20 */ - __IO uint32_t CTRL2_SET; /**< eLCDIF General Control2 Register, offset: 0x24 */ - __IO uint32_t CTRL2_CLR; /**< eLCDIF General Control2 Register, offset: 0x28 */ - __IO uint32_t CTRL2_TOG; /**< eLCDIF General Control2 Register, offset: 0x2C */ - __IO uint32_t TRANSFER_COUNT; /**< eLCDIF Horizontal and Vertical Valid Data Count Register, offset: 0x30 */ + __IO uint32_t CTRL; /**< LCDIF General Control Register, offset: 0x0 */ + __IO uint32_t CTRL_SET; /**< LCDIF General Control Register, offset: 0x4 */ + __IO uint32_t CTRL_CLR; /**< LCDIF General Control Register, offset: 0x8 */ + __IO uint32_t CTRL_TOG; /**< LCDIF General Control Register, offset: 0xC */ + __IO uint32_t CTRL1; /**< LCDIF General Control1 Register, offset: 0x10 */ + __IO uint32_t CTRL1_SET; /**< LCDIF General Control1 Register, offset: 0x14 */ + __IO uint32_t CTRL1_CLR; /**< LCDIF General Control1 Register, offset: 0x18 */ + __IO uint32_t CTRL1_TOG; /**< LCDIF General Control1 Register, offset: 0x1C */ + __IO uint32_t CTRL2; /**< LCDIF General Control2 Register, offset: 0x20 */ + __IO uint32_t CTRL2_SET; /**< LCDIF General Control2 Register, offset: 0x24 */ + __IO uint32_t CTRL2_CLR; /**< LCDIF General Control2 Register, offset: 0x28 */ + __IO uint32_t CTRL2_TOG; /**< LCDIF General Control2 Register, offset: 0x2C */ + __IO uint32_t TRANSFER_COUNT; /**< LCDIF Horizontal and Vertical Valid Data Count Register, offset: 0x30 */ uint8_t RESERVED_0[12]; __IO uint32_t CUR_BUF; /**< LCD Interface Current Buffer Address Register, offset: 0x40 */ uint8_t RESERVED_1[12]; __IO uint32_t NEXT_BUF; /**< LCD Interface Next Buffer Address Register, offset: 0x50 */ uint8_t RESERVED_2[28]; - __IO uint32_t VDCTRL0; /**< eLCDIF VSYNC Mode and Dotclk Mode Control Register0, offset: 0x70 */ - __IO uint32_t VDCTRL0_SET; /**< eLCDIF VSYNC Mode and Dotclk Mode Control Register0, offset: 0x74 */ - __IO uint32_t VDCTRL0_CLR; /**< eLCDIF VSYNC Mode and Dotclk Mode Control Register0, offset: 0x78 */ - __IO uint32_t VDCTRL0_TOG; /**< eLCDIF VSYNC Mode and Dotclk Mode Control Register0, offset: 0x7C */ - __IO uint32_t VDCTRL1; /**< eLCDIF VSYNC Mode and Dotclk Mode Control Register1, offset: 0x80 */ + __IO uint32_t VDCTRL0; /**< LCDIF VSYNC Mode and Dotclk Mode Control Register0, offset: 0x70 */ + __IO uint32_t VDCTRL0_SET; /**< LCDIF VSYNC Mode and Dotclk Mode Control Register0, offset: 0x74 */ + __IO uint32_t VDCTRL0_CLR; /**< LCDIF VSYNC Mode and Dotclk Mode Control Register0, offset: 0x78 */ + __IO uint32_t VDCTRL0_TOG; /**< LCDIF VSYNC Mode and Dotclk Mode Control Register0, offset: 0x7C */ + __IO uint32_t VDCTRL1; /**< LCDIF VSYNC Mode and Dotclk Mode Control Register1, offset: 0x80 */ uint8_t RESERVED_3[12]; __IO uint32_t VDCTRL2; /**< LCDIF VSYNC Mode and Dotclk Mode Control Register2, offset: 0x90 */ uint8_t RESERVED_4[12]; - __IO uint32_t VDCTRL3; /**< eLCDIF VSYNC Mode and Dotclk Mode Control Register3, offset: 0xA0 */ + __IO uint32_t VDCTRL3; /**< LCDIF VSYNC Mode and Dotclk Mode Control Register3, offset: 0xA0 */ uint8_t RESERVED_5[12]; - __IO uint32_t VDCTRL4; /**< eLCDIF VSYNC Mode and Dotclk Mode Control Register4, offset: 0xB0 */ + __IO uint32_t VDCTRL4; /**< LCDIF VSYNC Mode and Dotclk Mode Control Register4, offset: 0xB0 */ uint8_t RESERVED_6[220]; __IO uint32_t BM_ERROR_STAT; /**< Bus Master Error Status Register, offset: 0x190 */ uint8_t RESERVED_7[12]; @@ -13116,7 +20814,7 @@ typedef struct { uint8_t RESERVED_8[12]; __I uint32_t STAT; /**< LCD Interface Status Register, offset: 0x1B0 */ uint8_t RESERVED_9[76]; - __IO uint32_t THRES; /**< eLCDIF Threshold Register, offset: 0x200 */ + __IO uint32_t THRES; /**< LCDIF Threshold Register, offset: 0x200 */ uint8_t RESERVED_10[380]; __IO uint32_t PIGEONCTRL0; /**< LCDIF Pigeon Mode Control0 Register, offset: 0x380 */ __IO uint32_t PIGEONCTRL0_SET; /**< LCDIF Pigeon Mode Control0 Register, offset: 0x384 */ @@ -13159,15 +20857,24 @@ typedef struct { * @{ */ -/*! @name CTRL - eLCDIF General Control Register */ +/*! @name CTRL - LCDIF General Control Register */ +/*! @{ */ #define LCDIF_CTRL_RUN_MASK (0x1U) #define LCDIF_CTRL_RUN_SHIFT (0U) #define LCDIF_CTRL_RUN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_RUN_SHIFT)) & LCDIF_CTRL_RUN_MASK) #define LCDIF_CTRL_DATA_FORMAT_24_BIT_MASK (0x2U) #define LCDIF_CTRL_DATA_FORMAT_24_BIT_SHIFT (1U) +/*! DATA_FORMAT_24_BIT + * 0b0..Data input to the block is in 24 bpp format, such that all RGB 888 data is contained in 24 bits. + * 0b1..Data input to the block is actually RGB 18 bpp, but there is 1 color per byte, hence the upper 2 bits in each byte do not contain any useful data, and should be dropped. + */ #define LCDIF_CTRL_DATA_FORMAT_24_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_DATA_FORMAT_24_BIT_SHIFT)) & LCDIF_CTRL_DATA_FORMAT_24_BIT_MASK) #define LCDIF_CTRL_DATA_FORMAT_18_BIT_MASK (0x4U) #define LCDIF_CTRL_DATA_FORMAT_18_BIT_SHIFT (2U) +/*! DATA_FORMAT_18_BIT + * 0b0..Data input to the block is in 18 bpp format, such that lower 18 bits contain RGB 666 and upper 14 bits do not contain any useful data. + * 0b1..Data input to the block is in 18 bpp format, such that upper 18 bits contain RGB 666 and lower 14 bits do not contain any useful data. + */ #define LCDIF_CTRL_DATA_FORMAT_18_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_DATA_FORMAT_18_BIT_SHIFT)) & LCDIF_CTRL_DATA_FORMAT_18_BIT_MASK) #define LCDIF_CTRL_DATA_FORMAT_16_BIT_MASK (0x8U) #define LCDIF_CTRL_DATA_FORMAT_16_BIT_SHIFT (3U) @@ -13183,15 +20890,43 @@ typedef struct { #define LCDIF_CTRL_ENABLE_PXP_HANDSHAKE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_ENABLE_PXP_HANDSHAKE_SHIFT)) & LCDIF_CTRL_ENABLE_PXP_HANDSHAKE_MASK) #define LCDIF_CTRL_WORD_LENGTH_MASK (0x300U) #define LCDIF_CTRL_WORD_LENGTH_SHIFT (8U) +/*! WORD_LENGTH + * 0b00..Input data is 16 bits per pixel. + * 0b01..Input data is 8 bits wide. + * 0b10..Input data is 18 bits per pixel. + * 0b11..Input data is 24 bits per pixel. + */ #define LCDIF_CTRL_WORD_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_WORD_LENGTH_SHIFT)) & LCDIF_CTRL_WORD_LENGTH_MASK) #define LCDIF_CTRL_LCD_DATABUS_WIDTH_MASK (0xC00U) #define LCDIF_CTRL_LCD_DATABUS_WIDTH_SHIFT (10U) +/*! LCD_DATABUS_WIDTH + * 0b00..16-bit data bus mode. + * 0b01..8-bit data bus mode. + * 0b10..18-bit data bus mode. + * 0b11..24-bit data bus mode. + */ #define LCDIF_CTRL_LCD_DATABUS_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_LCD_DATABUS_WIDTH_SHIFT)) & LCDIF_CTRL_LCD_DATABUS_WIDTH_MASK) #define LCDIF_CTRL_CSC_DATA_SWIZZLE_MASK (0x3000U) #define LCDIF_CTRL_CSC_DATA_SWIZZLE_SHIFT (12U) +/*! CSC_DATA_SWIZZLE + * 0b00..No byte swapping.(Little endian) + * 0b00..Little Endian byte ordering (same as NO_SWAP). + * 0b01..Big Endian swap (swap bytes 0,3 and 1,2). + * 0b01..Swizzle all bytes, swap bytes 0,3 and 1,2 (aka Big Endian). + * 0b10..Swap half-words. + * 0b11..Swap bytes within each half-word. + */ #define LCDIF_CTRL_CSC_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CSC_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_CSC_DATA_SWIZZLE_MASK) #define LCDIF_CTRL_INPUT_DATA_SWIZZLE_MASK (0xC000U) #define LCDIF_CTRL_INPUT_DATA_SWIZZLE_SHIFT (14U) +/*! INPUT_DATA_SWIZZLE + * 0b00..No byte swapping.(Little endian) + * 0b00..Little Endian byte ordering (same as NO_SWAP). + * 0b01..Big Endian swap (swap bytes 0,3 and 1,2). + * 0b01..Swizzle all bytes, swap bytes 0,3 and 1,2 (aka Big Endian). + * 0b10..Swap half-words. + * 0b11..Swap bytes within each half-word. + */ #define LCDIF_CTRL_INPUT_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_INPUT_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_INPUT_DATA_SWIZZLE_MASK) #define LCDIF_CTRL_DOTCLK_MODE_MASK (0x20000U) #define LCDIF_CTRL_DOTCLK_MODE_SHIFT (17U) @@ -13204,6 +20939,10 @@ typedef struct { #define LCDIF_CTRL_SHIFT_NUM_BITS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SHIFT_NUM_BITS_SHIFT)) & LCDIF_CTRL_SHIFT_NUM_BITS_MASK) #define LCDIF_CTRL_DATA_SHIFT_DIR_MASK (0x4000000U) #define LCDIF_CTRL_DATA_SHIFT_DIR_SHIFT (26U) +/*! DATA_SHIFT_DIR + * 0b0..Data to be transmitted is shifted LEFT by SHIFT_NUM_BITS bits. + * 0b1..Data to be transmitted is shifted RIGHT by SHIFT_NUM_BITS bits. + */ #define LCDIF_CTRL_DATA_SHIFT_DIR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_DATA_SHIFT_DIR_SHIFT)) & LCDIF_CTRL_DATA_SHIFT_DIR_MASK) #define LCDIF_CTRL_CLKGATE_MASK (0x40000000U) #define LCDIF_CTRL_CLKGATE_SHIFT (30U) @@ -13211,16 +20950,26 @@ typedef struct { #define LCDIF_CTRL_SFTRST_MASK (0x80000000U) #define LCDIF_CTRL_SFTRST_SHIFT (31U) #define LCDIF_CTRL_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SFTRST_SHIFT)) & LCDIF_CTRL_SFTRST_MASK) +/*! @} */ -/*! @name CTRL_SET - eLCDIF General Control Register */ +/*! @name CTRL_SET - LCDIF General Control Register */ +/*! @{ */ #define LCDIF_CTRL_SET_RUN_MASK (0x1U) #define LCDIF_CTRL_SET_RUN_SHIFT (0U) #define LCDIF_CTRL_SET_RUN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_RUN_SHIFT)) & LCDIF_CTRL_SET_RUN_MASK) #define LCDIF_CTRL_SET_DATA_FORMAT_24_BIT_MASK (0x2U) #define LCDIF_CTRL_SET_DATA_FORMAT_24_BIT_SHIFT (1U) +/*! DATA_FORMAT_24_BIT + * 0b0..Data input to the block is in 24 bpp format, such that all RGB 888 data is contained in 24 bits. + * 0b1..Data input to the block is actually RGB 18 bpp, but there is 1 color per byte, hence the upper 2 bits in each byte do not contain any useful data, and should be dropped. + */ #define LCDIF_CTRL_SET_DATA_FORMAT_24_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_DATA_FORMAT_24_BIT_SHIFT)) & LCDIF_CTRL_SET_DATA_FORMAT_24_BIT_MASK) #define LCDIF_CTRL_SET_DATA_FORMAT_18_BIT_MASK (0x4U) #define LCDIF_CTRL_SET_DATA_FORMAT_18_BIT_SHIFT (2U) +/*! DATA_FORMAT_18_BIT + * 0b0..Data input to the block is in 18 bpp format, such that lower 18 bits contain RGB 666 and upper 14 bits do not contain any useful data. + * 0b1..Data input to the block is in 18 bpp format, such that upper 18 bits contain RGB 666 and lower 14 bits do not contain any useful data. + */ #define LCDIF_CTRL_SET_DATA_FORMAT_18_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_DATA_FORMAT_18_BIT_SHIFT)) & LCDIF_CTRL_SET_DATA_FORMAT_18_BIT_MASK) #define LCDIF_CTRL_SET_DATA_FORMAT_16_BIT_MASK (0x8U) #define LCDIF_CTRL_SET_DATA_FORMAT_16_BIT_SHIFT (3U) @@ -13236,15 +20985,43 @@ typedef struct { #define LCDIF_CTRL_SET_ENABLE_PXP_HANDSHAKE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_ENABLE_PXP_HANDSHAKE_SHIFT)) & LCDIF_CTRL_SET_ENABLE_PXP_HANDSHAKE_MASK) #define LCDIF_CTRL_SET_WORD_LENGTH_MASK (0x300U) #define LCDIF_CTRL_SET_WORD_LENGTH_SHIFT (8U) +/*! WORD_LENGTH + * 0b00..Input data is 16 bits per pixel. + * 0b01..Input data is 8 bits wide. + * 0b10..Input data is 18 bits per pixel. + * 0b11..Input data is 24 bits per pixel. + */ #define LCDIF_CTRL_SET_WORD_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_WORD_LENGTH_SHIFT)) & LCDIF_CTRL_SET_WORD_LENGTH_MASK) #define LCDIF_CTRL_SET_LCD_DATABUS_WIDTH_MASK (0xC00U) #define LCDIF_CTRL_SET_LCD_DATABUS_WIDTH_SHIFT (10U) +/*! LCD_DATABUS_WIDTH + * 0b00..16-bit data bus mode. + * 0b01..8-bit data bus mode. + * 0b10..18-bit data bus mode. + * 0b11..24-bit data bus mode. + */ #define LCDIF_CTRL_SET_LCD_DATABUS_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_LCD_DATABUS_WIDTH_SHIFT)) & LCDIF_CTRL_SET_LCD_DATABUS_WIDTH_MASK) #define LCDIF_CTRL_SET_CSC_DATA_SWIZZLE_MASK (0x3000U) #define LCDIF_CTRL_SET_CSC_DATA_SWIZZLE_SHIFT (12U) +/*! CSC_DATA_SWIZZLE + * 0b00..No byte swapping.(Little endian) + * 0b00..Little Endian byte ordering (same as NO_SWAP). + * 0b01..Big Endian swap (swap bytes 0,3 and 1,2). + * 0b01..Swizzle all bytes, swap bytes 0,3 and 1,2 (aka Big Endian). + * 0b10..Swap half-words. + * 0b11..Swap bytes within each half-word. + */ #define LCDIF_CTRL_SET_CSC_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_CSC_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_SET_CSC_DATA_SWIZZLE_MASK) #define LCDIF_CTRL_SET_INPUT_DATA_SWIZZLE_MASK (0xC000U) #define LCDIF_CTRL_SET_INPUT_DATA_SWIZZLE_SHIFT (14U) +/*! INPUT_DATA_SWIZZLE + * 0b00..No byte swapping.(Little endian) + * 0b00..Little Endian byte ordering (same as NO_SWAP). + * 0b01..Big Endian swap (swap bytes 0,3 and 1,2). + * 0b01..Swizzle all bytes, swap bytes 0,3 and 1,2 (aka Big Endian). + * 0b10..Swap half-words. + * 0b11..Swap bytes within each half-word. + */ #define LCDIF_CTRL_SET_INPUT_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_INPUT_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_SET_INPUT_DATA_SWIZZLE_MASK) #define LCDIF_CTRL_SET_DOTCLK_MODE_MASK (0x20000U) #define LCDIF_CTRL_SET_DOTCLK_MODE_SHIFT (17U) @@ -13257,6 +21034,10 @@ typedef struct { #define LCDIF_CTRL_SET_SHIFT_NUM_BITS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_SHIFT_NUM_BITS_SHIFT)) & LCDIF_CTRL_SET_SHIFT_NUM_BITS_MASK) #define LCDIF_CTRL_SET_DATA_SHIFT_DIR_MASK (0x4000000U) #define LCDIF_CTRL_SET_DATA_SHIFT_DIR_SHIFT (26U) +/*! DATA_SHIFT_DIR + * 0b0..Data to be transmitted is shifted LEFT by SHIFT_NUM_BITS bits. + * 0b1..Data to be transmitted is shifted RIGHT by SHIFT_NUM_BITS bits. + */ #define LCDIF_CTRL_SET_DATA_SHIFT_DIR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_DATA_SHIFT_DIR_SHIFT)) & LCDIF_CTRL_SET_DATA_SHIFT_DIR_MASK) #define LCDIF_CTRL_SET_CLKGATE_MASK (0x40000000U) #define LCDIF_CTRL_SET_CLKGATE_SHIFT (30U) @@ -13264,16 +21045,26 @@ typedef struct { #define LCDIF_CTRL_SET_SFTRST_MASK (0x80000000U) #define LCDIF_CTRL_SET_SFTRST_SHIFT (31U) #define LCDIF_CTRL_SET_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_SFTRST_SHIFT)) & LCDIF_CTRL_SET_SFTRST_MASK) +/*! @} */ -/*! @name CTRL_CLR - eLCDIF General Control Register */ +/*! @name CTRL_CLR - LCDIF General Control Register */ +/*! @{ */ #define LCDIF_CTRL_CLR_RUN_MASK (0x1U) #define LCDIF_CTRL_CLR_RUN_SHIFT (0U) #define LCDIF_CTRL_CLR_RUN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_RUN_SHIFT)) & LCDIF_CTRL_CLR_RUN_MASK) #define LCDIF_CTRL_CLR_DATA_FORMAT_24_BIT_MASK (0x2U) #define LCDIF_CTRL_CLR_DATA_FORMAT_24_BIT_SHIFT (1U) +/*! DATA_FORMAT_24_BIT + * 0b0..Data input to the block is in 24 bpp format, such that all RGB 888 data is contained in 24 bits. + * 0b1..Data input to the block is actually RGB 18 bpp, but there is 1 color per byte, hence the upper 2 bits in each byte do not contain any useful data, and should be dropped. + */ #define LCDIF_CTRL_CLR_DATA_FORMAT_24_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_DATA_FORMAT_24_BIT_SHIFT)) & LCDIF_CTRL_CLR_DATA_FORMAT_24_BIT_MASK) #define LCDIF_CTRL_CLR_DATA_FORMAT_18_BIT_MASK (0x4U) #define LCDIF_CTRL_CLR_DATA_FORMAT_18_BIT_SHIFT (2U) +/*! DATA_FORMAT_18_BIT + * 0b0..Data input to the block is in 18 bpp format, such that lower 18 bits contain RGB 666 and upper 14 bits do not contain any useful data. + * 0b1..Data input to the block is in 18 bpp format, such that upper 18 bits contain RGB 666 and lower 14 bits do not contain any useful data. + */ #define LCDIF_CTRL_CLR_DATA_FORMAT_18_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_DATA_FORMAT_18_BIT_SHIFT)) & LCDIF_CTRL_CLR_DATA_FORMAT_18_BIT_MASK) #define LCDIF_CTRL_CLR_DATA_FORMAT_16_BIT_MASK (0x8U) #define LCDIF_CTRL_CLR_DATA_FORMAT_16_BIT_SHIFT (3U) @@ -13289,15 +21080,43 @@ typedef struct { #define LCDIF_CTRL_CLR_ENABLE_PXP_HANDSHAKE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_ENABLE_PXP_HANDSHAKE_SHIFT)) & LCDIF_CTRL_CLR_ENABLE_PXP_HANDSHAKE_MASK) #define LCDIF_CTRL_CLR_WORD_LENGTH_MASK (0x300U) #define LCDIF_CTRL_CLR_WORD_LENGTH_SHIFT (8U) +/*! WORD_LENGTH + * 0b00..Input data is 16 bits per pixel. + * 0b01..Input data is 8 bits wide. + * 0b10..Input data is 18 bits per pixel. + * 0b11..Input data is 24 bits per pixel. + */ #define LCDIF_CTRL_CLR_WORD_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_WORD_LENGTH_SHIFT)) & LCDIF_CTRL_CLR_WORD_LENGTH_MASK) #define LCDIF_CTRL_CLR_LCD_DATABUS_WIDTH_MASK (0xC00U) #define LCDIF_CTRL_CLR_LCD_DATABUS_WIDTH_SHIFT (10U) +/*! LCD_DATABUS_WIDTH + * 0b00..16-bit data bus mode. + * 0b01..8-bit data bus mode. + * 0b10..18-bit data bus mode. + * 0b11..24-bit data bus mode. + */ #define LCDIF_CTRL_CLR_LCD_DATABUS_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_LCD_DATABUS_WIDTH_SHIFT)) & LCDIF_CTRL_CLR_LCD_DATABUS_WIDTH_MASK) #define LCDIF_CTRL_CLR_CSC_DATA_SWIZZLE_MASK (0x3000U) #define LCDIF_CTRL_CLR_CSC_DATA_SWIZZLE_SHIFT (12U) +/*! CSC_DATA_SWIZZLE + * 0b00..No byte swapping.(Little endian) + * 0b00..Little Endian byte ordering (same as NO_SWAP). + * 0b01..Big Endian swap (swap bytes 0,3 and 1,2). + * 0b01..Swizzle all bytes, swap bytes 0,3 and 1,2 (aka Big Endian). + * 0b10..Swap half-words. + * 0b11..Swap bytes within each half-word. + */ #define LCDIF_CTRL_CLR_CSC_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_CSC_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_CLR_CSC_DATA_SWIZZLE_MASK) #define LCDIF_CTRL_CLR_INPUT_DATA_SWIZZLE_MASK (0xC000U) #define LCDIF_CTRL_CLR_INPUT_DATA_SWIZZLE_SHIFT (14U) +/*! INPUT_DATA_SWIZZLE + * 0b00..No byte swapping.(Little endian) + * 0b00..Little Endian byte ordering (same as NO_SWAP). + * 0b01..Big Endian swap (swap bytes 0,3 and 1,2). + * 0b01..Swizzle all bytes, swap bytes 0,3 and 1,2 (aka Big Endian). + * 0b10..Swap half-words. + * 0b11..Swap bytes within each half-word. + */ #define LCDIF_CTRL_CLR_INPUT_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_INPUT_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_CLR_INPUT_DATA_SWIZZLE_MASK) #define LCDIF_CTRL_CLR_DOTCLK_MODE_MASK (0x20000U) #define LCDIF_CTRL_CLR_DOTCLK_MODE_SHIFT (17U) @@ -13310,6 +21129,10 @@ typedef struct { #define LCDIF_CTRL_CLR_SHIFT_NUM_BITS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_SHIFT_NUM_BITS_SHIFT)) & LCDIF_CTRL_CLR_SHIFT_NUM_BITS_MASK) #define LCDIF_CTRL_CLR_DATA_SHIFT_DIR_MASK (0x4000000U) #define LCDIF_CTRL_CLR_DATA_SHIFT_DIR_SHIFT (26U) +/*! DATA_SHIFT_DIR + * 0b0..Data to be transmitted is shifted LEFT by SHIFT_NUM_BITS bits. + * 0b1..Data to be transmitted is shifted RIGHT by SHIFT_NUM_BITS bits. + */ #define LCDIF_CTRL_CLR_DATA_SHIFT_DIR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_DATA_SHIFT_DIR_SHIFT)) & LCDIF_CTRL_CLR_DATA_SHIFT_DIR_MASK) #define LCDIF_CTRL_CLR_CLKGATE_MASK (0x40000000U) #define LCDIF_CTRL_CLR_CLKGATE_SHIFT (30U) @@ -13317,16 +21140,26 @@ typedef struct { #define LCDIF_CTRL_CLR_SFTRST_MASK (0x80000000U) #define LCDIF_CTRL_CLR_SFTRST_SHIFT (31U) #define LCDIF_CTRL_CLR_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_SFTRST_SHIFT)) & LCDIF_CTRL_CLR_SFTRST_MASK) +/*! @} */ -/*! @name CTRL_TOG - eLCDIF General Control Register */ +/*! @name CTRL_TOG - LCDIF General Control Register */ +/*! @{ */ #define LCDIF_CTRL_TOG_RUN_MASK (0x1U) #define LCDIF_CTRL_TOG_RUN_SHIFT (0U) #define LCDIF_CTRL_TOG_RUN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_RUN_SHIFT)) & LCDIF_CTRL_TOG_RUN_MASK) #define LCDIF_CTRL_TOG_DATA_FORMAT_24_BIT_MASK (0x2U) #define LCDIF_CTRL_TOG_DATA_FORMAT_24_BIT_SHIFT (1U) +/*! DATA_FORMAT_24_BIT + * 0b0..Data input to the block is in 24 bpp format, such that all RGB 888 data is contained in 24 bits. + * 0b1..Data input to the block is actually RGB 18 bpp, but there is 1 color per byte, hence the upper 2 bits in each byte do not contain any useful data, and should be dropped. + */ #define LCDIF_CTRL_TOG_DATA_FORMAT_24_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_DATA_FORMAT_24_BIT_SHIFT)) & LCDIF_CTRL_TOG_DATA_FORMAT_24_BIT_MASK) #define LCDIF_CTRL_TOG_DATA_FORMAT_18_BIT_MASK (0x4U) #define LCDIF_CTRL_TOG_DATA_FORMAT_18_BIT_SHIFT (2U) +/*! DATA_FORMAT_18_BIT + * 0b0..Data input to the block is in 18 bpp format, such that lower 18 bits contain RGB 666 and upper 14 bits do not contain any useful data. + * 0b1..Data input to the block is in 18 bpp format, such that upper 18 bits contain RGB 666 and lower 14 bits do not contain any useful data. + */ #define LCDIF_CTRL_TOG_DATA_FORMAT_18_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_DATA_FORMAT_18_BIT_SHIFT)) & LCDIF_CTRL_TOG_DATA_FORMAT_18_BIT_MASK) #define LCDIF_CTRL_TOG_DATA_FORMAT_16_BIT_MASK (0x8U) #define LCDIF_CTRL_TOG_DATA_FORMAT_16_BIT_SHIFT (3U) @@ -13342,15 +21175,43 @@ typedef struct { #define LCDIF_CTRL_TOG_ENABLE_PXP_HANDSHAKE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_ENABLE_PXP_HANDSHAKE_SHIFT)) & LCDIF_CTRL_TOG_ENABLE_PXP_HANDSHAKE_MASK) #define LCDIF_CTRL_TOG_WORD_LENGTH_MASK (0x300U) #define LCDIF_CTRL_TOG_WORD_LENGTH_SHIFT (8U) +/*! WORD_LENGTH + * 0b00..Input data is 16 bits per pixel. + * 0b01..Input data is 8 bits wide. + * 0b10..Input data is 18 bits per pixel. + * 0b11..Input data is 24 bits per pixel. + */ #define LCDIF_CTRL_TOG_WORD_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_WORD_LENGTH_SHIFT)) & LCDIF_CTRL_TOG_WORD_LENGTH_MASK) #define LCDIF_CTRL_TOG_LCD_DATABUS_WIDTH_MASK (0xC00U) #define LCDIF_CTRL_TOG_LCD_DATABUS_WIDTH_SHIFT (10U) +/*! LCD_DATABUS_WIDTH + * 0b00..16-bit data bus mode. + * 0b01..8-bit data bus mode. + * 0b10..18-bit data bus mode. + * 0b11..24-bit data bus mode. + */ #define LCDIF_CTRL_TOG_LCD_DATABUS_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_LCD_DATABUS_WIDTH_SHIFT)) & LCDIF_CTRL_TOG_LCD_DATABUS_WIDTH_MASK) #define LCDIF_CTRL_TOG_CSC_DATA_SWIZZLE_MASK (0x3000U) #define LCDIF_CTRL_TOG_CSC_DATA_SWIZZLE_SHIFT (12U) +/*! CSC_DATA_SWIZZLE + * 0b00..No byte swapping.(Little endian) + * 0b00..Little Endian byte ordering (same as NO_SWAP). + * 0b01..Big Endian swap (swap bytes 0,3 and 1,2). + * 0b01..Swizzle all bytes, swap bytes 0,3 and 1,2 (aka Big Endian). + * 0b10..Swap half-words. + * 0b11..Swap bytes within each half-word. + */ #define LCDIF_CTRL_TOG_CSC_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_CSC_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_TOG_CSC_DATA_SWIZZLE_MASK) #define LCDIF_CTRL_TOG_INPUT_DATA_SWIZZLE_MASK (0xC000U) #define LCDIF_CTRL_TOG_INPUT_DATA_SWIZZLE_SHIFT (14U) +/*! INPUT_DATA_SWIZZLE + * 0b00..No byte swapping.(Little endian) + * 0b00..Little Endian byte ordering (same as NO_SWAP). + * 0b01..Big Endian swap (swap bytes 0,3 and 1,2). + * 0b01..Swizzle all bytes, swap bytes 0,3 and 1,2 (aka Big Endian). + * 0b10..Swap half-words. + * 0b11..Swap bytes within each half-word. + */ #define LCDIF_CTRL_TOG_INPUT_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_INPUT_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_TOG_INPUT_DATA_SWIZZLE_MASK) #define LCDIF_CTRL_TOG_DOTCLK_MODE_MASK (0x20000U) #define LCDIF_CTRL_TOG_DOTCLK_MODE_SHIFT (17U) @@ -13363,6 +21224,10 @@ typedef struct { #define LCDIF_CTRL_TOG_SHIFT_NUM_BITS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_SHIFT_NUM_BITS_SHIFT)) & LCDIF_CTRL_TOG_SHIFT_NUM_BITS_MASK) #define LCDIF_CTRL_TOG_DATA_SHIFT_DIR_MASK (0x4000000U) #define LCDIF_CTRL_TOG_DATA_SHIFT_DIR_SHIFT (26U) +/*! DATA_SHIFT_DIR + * 0b0..Data to be transmitted is shifted LEFT by SHIFT_NUM_BITS bits. + * 0b1..Data to be transmitted is shifted RIGHT by SHIFT_NUM_BITS bits. + */ #define LCDIF_CTRL_TOG_DATA_SHIFT_DIR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_DATA_SHIFT_DIR_SHIFT)) & LCDIF_CTRL_TOG_DATA_SHIFT_DIR_MASK) #define LCDIF_CTRL_TOG_CLKGATE_MASK (0x40000000U) #define LCDIF_CTRL_TOG_CLKGATE_SHIFT (30U) @@ -13370,22 +21235,40 @@ typedef struct { #define LCDIF_CTRL_TOG_SFTRST_MASK (0x80000000U) #define LCDIF_CTRL_TOG_SFTRST_SHIFT (31U) #define LCDIF_CTRL_TOG_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_SFTRST_SHIFT)) & LCDIF_CTRL_TOG_SFTRST_MASK) +/*! @} */ -/*! @name CTRL1 - eLCDIF General Control1 Register */ +/*! @name CTRL1 - LCDIF General Control1 Register */ +/*! @{ */ #define LCDIF_CTRL1_RSRVD0_MASK (0xF8U) #define LCDIF_CTRL1_RSRVD0_SHIFT (3U) #define LCDIF_CTRL1_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_RSRVD0_SHIFT)) & LCDIF_CTRL1_RSRVD0_MASK) #define LCDIF_CTRL1_VSYNC_EDGE_IRQ_MASK (0x100U) #define LCDIF_CTRL1_VSYNC_EDGE_IRQ_SHIFT (8U) +/*! VSYNC_EDGE_IRQ + * 0b0..No Interrupt Request Pending. + * 0b1..Interrupt Request Pending. + */ #define LCDIF_CTRL1_VSYNC_EDGE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_VSYNC_EDGE_IRQ_SHIFT)) & LCDIF_CTRL1_VSYNC_EDGE_IRQ_MASK) #define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_MASK (0x200U) #define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_SHIFT (9U) +/*! CUR_FRAME_DONE_IRQ + * 0b0..No Interrupt Request Pending. + * 0b1..Interrupt Request Pending. + */ #define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_SHIFT)) & LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_MASK) #define LCDIF_CTRL1_UNDERFLOW_IRQ_MASK (0x400U) #define LCDIF_CTRL1_UNDERFLOW_IRQ_SHIFT (10U) +/*! UNDERFLOW_IRQ + * 0b0..No Interrupt Request Pending. + * 0b1..Interrupt Request Pending. + */ #define LCDIF_CTRL1_UNDERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_UNDERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_UNDERFLOW_IRQ_MASK) #define LCDIF_CTRL1_OVERFLOW_IRQ_MASK (0x800U) #define LCDIF_CTRL1_OVERFLOW_IRQ_SHIFT (11U) +/*! OVERFLOW_IRQ + * 0b0..No Interrupt Request Pending. + * 0b1..Interrupt Request Pending. + */ #define LCDIF_CTRL1_OVERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_OVERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_OVERFLOW_IRQ_MASK) #define LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN_MASK (0x1000U) #define LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN_SHIFT (12U) @@ -13419,6 +21302,10 @@ typedef struct { #define LCDIF_CTRL1_RECOVER_ON_UNDERFLOW(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_RECOVER_ON_UNDERFLOW_SHIFT)) & LCDIF_CTRL1_RECOVER_ON_UNDERFLOW_MASK) #define LCDIF_CTRL1_BM_ERROR_IRQ_MASK (0x2000000U) #define LCDIF_CTRL1_BM_ERROR_IRQ_SHIFT (25U) +/*! BM_ERROR_IRQ + * 0b0..No Interrupt Request Pending. + * 0b1..Interrupt Request Pending. + */ #define LCDIF_CTRL1_BM_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_BM_ERROR_IRQ_SHIFT)) & LCDIF_CTRL1_BM_ERROR_IRQ_MASK) #define LCDIF_CTRL1_BM_ERROR_IRQ_EN_MASK (0x4000000U) #define LCDIF_CTRL1_BM_ERROR_IRQ_EN_SHIFT (26U) @@ -13429,22 +21316,40 @@ typedef struct { #define LCDIF_CTRL1_IMAGE_DATA_SELECT_MASK (0x80000000U) #define LCDIF_CTRL1_IMAGE_DATA_SELECT_SHIFT (31U) #define LCDIF_CTRL1_IMAGE_DATA_SELECT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_IMAGE_DATA_SELECT_SHIFT)) & LCDIF_CTRL1_IMAGE_DATA_SELECT_MASK) +/*! @} */ -/*! @name CTRL1_SET - eLCDIF General Control1 Register */ +/*! @name CTRL1_SET - LCDIF General Control1 Register */ +/*! @{ */ #define LCDIF_CTRL1_SET_RSRVD0_MASK (0xF8U) #define LCDIF_CTRL1_SET_RSRVD0_SHIFT (3U) #define LCDIF_CTRL1_SET_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_RSRVD0_SHIFT)) & LCDIF_CTRL1_SET_RSRVD0_MASK) #define LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_MASK (0x100U) #define LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_SHIFT (8U) +/*! VSYNC_EDGE_IRQ + * 0b0..No Interrupt Request Pending. + * 0b1..Interrupt Request Pending. + */ #define LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_SHIFT)) & LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_MASK) #define LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_MASK (0x200U) #define LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_SHIFT (9U) +/*! CUR_FRAME_DONE_IRQ + * 0b0..No Interrupt Request Pending. + * 0b1..Interrupt Request Pending. + */ #define LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_SHIFT)) & LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_MASK) #define LCDIF_CTRL1_SET_UNDERFLOW_IRQ_MASK (0x400U) #define LCDIF_CTRL1_SET_UNDERFLOW_IRQ_SHIFT (10U) +/*! UNDERFLOW_IRQ + * 0b0..No Interrupt Request Pending. + * 0b1..Interrupt Request Pending. + */ #define LCDIF_CTRL1_SET_UNDERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_UNDERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_SET_UNDERFLOW_IRQ_MASK) #define LCDIF_CTRL1_SET_OVERFLOW_IRQ_MASK (0x800U) #define LCDIF_CTRL1_SET_OVERFLOW_IRQ_SHIFT (11U) +/*! OVERFLOW_IRQ + * 0b0..No Interrupt Request Pending. + * 0b1..Interrupt Request Pending. + */ #define LCDIF_CTRL1_SET_OVERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_OVERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_SET_OVERFLOW_IRQ_MASK) #define LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_EN_MASK (0x1000U) #define LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_EN_SHIFT (12U) @@ -13478,6 +21383,10 @@ typedef struct { #define LCDIF_CTRL1_SET_RECOVER_ON_UNDERFLOW(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_RECOVER_ON_UNDERFLOW_SHIFT)) & LCDIF_CTRL1_SET_RECOVER_ON_UNDERFLOW_MASK) #define LCDIF_CTRL1_SET_BM_ERROR_IRQ_MASK (0x2000000U) #define LCDIF_CTRL1_SET_BM_ERROR_IRQ_SHIFT (25U) +/*! BM_ERROR_IRQ + * 0b0..No Interrupt Request Pending. + * 0b1..Interrupt Request Pending. + */ #define LCDIF_CTRL1_SET_BM_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_BM_ERROR_IRQ_SHIFT)) & LCDIF_CTRL1_SET_BM_ERROR_IRQ_MASK) #define LCDIF_CTRL1_SET_BM_ERROR_IRQ_EN_MASK (0x4000000U) #define LCDIF_CTRL1_SET_BM_ERROR_IRQ_EN_SHIFT (26U) @@ -13488,22 +21397,40 @@ typedef struct { #define LCDIF_CTRL1_SET_IMAGE_DATA_SELECT_MASK (0x80000000U) #define LCDIF_CTRL1_SET_IMAGE_DATA_SELECT_SHIFT (31U) #define LCDIF_CTRL1_SET_IMAGE_DATA_SELECT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_IMAGE_DATA_SELECT_SHIFT)) & LCDIF_CTRL1_SET_IMAGE_DATA_SELECT_MASK) +/*! @} */ -/*! @name CTRL1_CLR - eLCDIF General Control1 Register */ +/*! @name CTRL1_CLR - LCDIF General Control1 Register */ +/*! @{ */ #define LCDIF_CTRL1_CLR_RSRVD0_MASK (0xF8U) #define LCDIF_CTRL1_CLR_RSRVD0_SHIFT (3U) #define LCDIF_CTRL1_CLR_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_RSRVD0_SHIFT)) & LCDIF_CTRL1_CLR_RSRVD0_MASK) #define LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_MASK (0x100U) #define LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_SHIFT (8U) +/*! VSYNC_EDGE_IRQ + * 0b0..No Interrupt Request Pending. + * 0b1..Interrupt Request Pending. + */ #define LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_SHIFT)) & LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_MASK) #define LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_MASK (0x200U) #define LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_SHIFT (9U) +/*! CUR_FRAME_DONE_IRQ + * 0b0..No Interrupt Request Pending. + * 0b1..Interrupt Request Pending. + */ #define LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_SHIFT)) & LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_MASK) #define LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_MASK (0x400U) #define LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_SHIFT (10U) +/*! UNDERFLOW_IRQ + * 0b0..No Interrupt Request Pending. + * 0b1..Interrupt Request Pending. + */ #define LCDIF_CTRL1_CLR_UNDERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_MASK) #define LCDIF_CTRL1_CLR_OVERFLOW_IRQ_MASK (0x800U) #define LCDIF_CTRL1_CLR_OVERFLOW_IRQ_SHIFT (11U) +/*! OVERFLOW_IRQ + * 0b0..No Interrupt Request Pending. + * 0b1..Interrupt Request Pending. + */ #define LCDIF_CTRL1_CLR_OVERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_OVERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_CLR_OVERFLOW_IRQ_MASK) #define LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_EN_MASK (0x1000U) #define LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_EN_SHIFT (12U) @@ -13537,6 +21464,10 @@ typedef struct { #define LCDIF_CTRL1_CLR_RECOVER_ON_UNDERFLOW(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_RECOVER_ON_UNDERFLOW_SHIFT)) & LCDIF_CTRL1_CLR_RECOVER_ON_UNDERFLOW_MASK) #define LCDIF_CTRL1_CLR_BM_ERROR_IRQ_MASK (0x2000000U) #define LCDIF_CTRL1_CLR_BM_ERROR_IRQ_SHIFT (25U) +/*! BM_ERROR_IRQ + * 0b0..No Interrupt Request Pending. + * 0b1..Interrupt Request Pending. + */ #define LCDIF_CTRL1_CLR_BM_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_BM_ERROR_IRQ_SHIFT)) & LCDIF_CTRL1_CLR_BM_ERROR_IRQ_MASK) #define LCDIF_CTRL1_CLR_BM_ERROR_IRQ_EN_MASK (0x4000000U) #define LCDIF_CTRL1_CLR_BM_ERROR_IRQ_EN_SHIFT (26U) @@ -13547,22 +21478,40 @@ typedef struct { #define LCDIF_CTRL1_CLR_IMAGE_DATA_SELECT_MASK (0x80000000U) #define LCDIF_CTRL1_CLR_IMAGE_DATA_SELECT_SHIFT (31U) #define LCDIF_CTRL1_CLR_IMAGE_DATA_SELECT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_IMAGE_DATA_SELECT_SHIFT)) & LCDIF_CTRL1_CLR_IMAGE_DATA_SELECT_MASK) +/*! @} */ -/*! @name CTRL1_TOG - eLCDIF General Control1 Register */ +/*! @name CTRL1_TOG - LCDIF General Control1 Register */ +/*! @{ */ #define LCDIF_CTRL1_TOG_RSRVD0_MASK (0xF8U) #define LCDIF_CTRL1_TOG_RSRVD0_SHIFT (3U) #define LCDIF_CTRL1_TOG_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_RSRVD0_SHIFT)) & LCDIF_CTRL1_TOG_RSRVD0_MASK) #define LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_MASK (0x100U) #define LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_SHIFT (8U) +/*! VSYNC_EDGE_IRQ + * 0b0..No Interrupt Request Pending. + * 0b1..Interrupt Request Pending. + */ #define LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_SHIFT)) & LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_MASK) #define LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_MASK (0x200U) #define LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_SHIFT (9U) +/*! CUR_FRAME_DONE_IRQ + * 0b0..No Interrupt Request Pending. + * 0b1..Interrupt Request Pending. + */ #define LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_SHIFT)) & LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_MASK) #define LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_MASK (0x400U) #define LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_SHIFT (10U) +/*! UNDERFLOW_IRQ + * 0b0..No Interrupt Request Pending. + * 0b1..Interrupt Request Pending. + */ #define LCDIF_CTRL1_TOG_UNDERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_MASK) #define LCDIF_CTRL1_TOG_OVERFLOW_IRQ_MASK (0x800U) #define LCDIF_CTRL1_TOG_OVERFLOW_IRQ_SHIFT (11U) +/*! OVERFLOW_IRQ + * 0b0..No Interrupt Request Pending. + * 0b1..Interrupt Request Pending. + */ #define LCDIF_CTRL1_TOG_OVERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_OVERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_TOG_OVERFLOW_IRQ_MASK) #define LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_EN_MASK (0x1000U) #define LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_EN_SHIFT (12U) @@ -13596,6 +21545,10 @@ typedef struct { #define LCDIF_CTRL1_TOG_RECOVER_ON_UNDERFLOW(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_RECOVER_ON_UNDERFLOW_SHIFT)) & LCDIF_CTRL1_TOG_RECOVER_ON_UNDERFLOW_MASK) #define LCDIF_CTRL1_TOG_BM_ERROR_IRQ_MASK (0x2000000U) #define LCDIF_CTRL1_TOG_BM_ERROR_IRQ_SHIFT (25U) +/*! BM_ERROR_IRQ + * 0b0..No Interrupt Request Pending. + * 0b1..Interrupt Request Pending. + */ #define LCDIF_CTRL1_TOG_BM_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_BM_ERROR_IRQ_SHIFT)) & LCDIF_CTRL1_TOG_BM_ERROR_IRQ_MASK) #define LCDIF_CTRL1_TOG_BM_ERROR_IRQ_EN_MASK (0x4000000U) #define LCDIF_CTRL1_TOG_BM_ERROR_IRQ_EN_SHIFT (26U) @@ -13606,19 +21559,37 @@ typedef struct { #define LCDIF_CTRL1_TOG_IMAGE_DATA_SELECT_MASK (0x80000000U) #define LCDIF_CTRL1_TOG_IMAGE_DATA_SELECT_SHIFT (31U) #define LCDIF_CTRL1_TOG_IMAGE_DATA_SELECT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_IMAGE_DATA_SELECT_SHIFT)) & LCDIF_CTRL1_TOG_IMAGE_DATA_SELECT_MASK) +/*! @} */ -/*! @name CTRL2 - eLCDIF General Control2 Register */ +/*! @name CTRL2 - LCDIF General Control2 Register */ +/*! @{ */ #define LCDIF_CTRL2_RSRVD0_MASK (0xFFFU) #define LCDIF_CTRL2_RSRVD0_SHIFT (0U) #define LCDIF_CTRL2_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_RSRVD0_SHIFT)) & LCDIF_CTRL2_RSRVD0_MASK) #define LCDIF_CTRL2_EVEN_LINE_PATTERN_MASK (0x7000U) #define LCDIF_CTRL2_EVEN_LINE_PATTERN_SHIFT (12U) +/*! EVEN_LINE_PATTERN + * 0b000..RGB + * 0b001..RBG + * 0b010..GBR + * 0b011..GRB + * 0b100..BRG + * 0b101..BGR + */ #define LCDIF_CTRL2_EVEN_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_EVEN_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_EVEN_LINE_PATTERN_MASK) #define LCDIF_CTRL2_RSRVD3_MASK (0x8000U) #define LCDIF_CTRL2_RSRVD3_SHIFT (15U) #define LCDIF_CTRL2_RSRVD3(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_RSRVD3_SHIFT)) & LCDIF_CTRL2_RSRVD3_MASK) #define LCDIF_CTRL2_ODD_LINE_PATTERN_MASK (0x70000U) #define LCDIF_CTRL2_ODD_LINE_PATTERN_SHIFT (16U) +/*! ODD_LINE_PATTERN + * 0b000..RGB + * 0b001..RBG + * 0b010..GBR + * 0b011..GRB + * 0b100..BRG + * 0b101..BGR + */ #define LCDIF_CTRL2_ODD_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_ODD_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_ODD_LINE_PATTERN_MASK) #define LCDIF_CTRL2_RSRVD4_MASK (0x80000U) #define LCDIF_CTRL2_RSRVD4_SHIFT (19U) @@ -13628,23 +21599,48 @@ typedef struct { #define LCDIF_CTRL2_BURST_LEN_8(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_BURST_LEN_8_SHIFT)) & LCDIF_CTRL2_BURST_LEN_8_MASK) #define LCDIF_CTRL2_OUTSTANDING_REQS_MASK (0xE00000U) #define LCDIF_CTRL2_OUTSTANDING_REQS_SHIFT (21U) +/*! OUTSTANDING_REQS + * 0b000..REQ_1 + * 0b001..REQ_2 + * 0b010..REQ_4 + * 0b011..REQ_8 + * 0b100..REQ_16 + */ #define LCDIF_CTRL2_OUTSTANDING_REQS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_OUTSTANDING_REQS_SHIFT)) & LCDIF_CTRL2_OUTSTANDING_REQS_MASK) #define LCDIF_CTRL2_RSRVD5_MASK (0xFF000000U) #define LCDIF_CTRL2_RSRVD5_SHIFT (24U) #define LCDIF_CTRL2_RSRVD5(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_RSRVD5_SHIFT)) & LCDIF_CTRL2_RSRVD5_MASK) +/*! @} */ -/*! @name CTRL2_SET - eLCDIF General Control2 Register */ +/*! @name CTRL2_SET - LCDIF General Control2 Register */ +/*! @{ */ #define LCDIF_CTRL2_SET_RSRVD0_MASK (0xFFFU) #define LCDIF_CTRL2_SET_RSRVD0_SHIFT (0U) #define LCDIF_CTRL2_SET_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_RSRVD0_SHIFT)) & LCDIF_CTRL2_SET_RSRVD0_MASK) #define LCDIF_CTRL2_SET_EVEN_LINE_PATTERN_MASK (0x7000U) #define LCDIF_CTRL2_SET_EVEN_LINE_PATTERN_SHIFT (12U) +/*! EVEN_LINE_PATTERN + * 0b000..RGB + * 0b001..RBG + * 0b010..GBR + * 0b011..GRB + * 0b100..BRG + * 0b101..BGR + */ #define LCDIF_CTRL2_SET_EVEN_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_EVEN_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_SET_EVEN_LINE_PATTERN_MASK) #define LCDIF_CTRL2_SET_RSRVD3_MASK (0x8000U) #define LCDIF_CTRL2_SET_RSRVD3_SHIFT (15U) #define LCDIF_CTRL2_SET_RSRVD3(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_RSRVD3_SHIFT)) & LCDIF_CTRL2_SET_RSRVD3_MASK) #define LCDIF_CTRL2_SET_ODD_LINE_PATTERN_MASK (0x70000U) #define LCDIF_CTRL2_SET_ODD_LINE_PATTERN_SHIFT (16U) +/*! ODD_LINE_PATTERN + * 0b000..RGB + * 0b001..RBG + * 0b010..GBR + * 0b011..GRB + * 0b100..BRG + * 0b101..BGR + */ #define LCDIF_CTRL2_SET_ODD_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_ODD_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_SET_ODD_LINE_PATTERN_MASK) #define LCDIF_CTRL2_SET_RSRVD4_MASK (0x80000U) #define LCDIF_CTRL2_SET_RSRVD4_SHIFT (19U) @@ -13654,23 +21650,48 @@ typedef struct { #define LCDIF_CTRL2_SET_BURST_LEN_8(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_BURST_LEN_8_SHIFT)) & LCDIF_CTRL2_SET_BURST_LEN_8_MASK) #define LCDIF_CTRL2_SET_OUTSTANDING_REQS_MASK (0xE00000U) #define LCDIF_CTRL2_SET_OUTSTANDING_REQS_SHIFT (21U) +/*! OUTSTANDING_REQS + * 0b000..REQ_1 + * 0b001..REQ_2 + * 0b010..REQ_4 + * 0b011..REQ_8 + * 0b100..REQ_16 + */ #define LCDIF_CTRL2_SET_OUTSTANDING_REQS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_OUTSTANDING_REQS_SHIFT)) & LCDIF_CTRL2_SET_OUTSTANDING_REQS_MASK) #define LCDIF_CTRL2_SET_RSRVD5_MASK (0xFF000000U) #define LCDIF_CTRL2_SET_RSRVD5_SHIFT (24U) #define LCDIF_CTRL2_SET_RSRVD5(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_RSRVD5_SHIFT)) & LCDIF_CTRL2_SET_RSRVD5_MASK) +/*! @} */ -/*! @name CTRL2_CLR - eLCDIF General Control2 Register */ +/*! @name CTRL2_CLR - LCDIF General Control2 Register */ +/*! @{ */ #define LCDIF_CTRL2_CLR_RSRVD0_MASK (0xFFFU) #define LCDIF_CTRL2_CLR_RSRVD0_SHIFT (0U) #define LCDIF_CTRL2_CLR_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_RSRVD0_SHIFT)) & LCDIF_CTRL2_CLR_RSRVD0_MASK) #define LCDIF_CTRL2_CLR_EVEN_LINE_PATTERN_MASK (0x7000U) #define LCDIF_CTRL2_CLR_EVEN_LINE_PATTERN_SHIFT (12U) +/*! EVEN_LINE_PATTERN + * 0b000..RGB + * 0b001..RBG + * 0b010..GBR + * 0b011..GRB + * 0b100..BRG + * 0b101..BGR + */ #define LCDIF_CTRL2_CLR_EVEN_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_EVEN_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_CLR_EVEN_LINE_PATTERN_MASK) #define LCDIF_CTRL2_CLR_RSRVD3_MASK (0x8000U) #define LCDIF_CTRL2_CLR_RSRVD3_SHIFT (15U) #define LCDIF_CTRL2_CLR_RSRVD3(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_RSRVD3_SHIFT)) & LCDIF_CTRL2_CLR_RSRVD3_MASK) #define LCDIF_CTRL2_CLR_ODD_LINE_PATTERN_MASK (0x70000U) #define LCDIF_CTRL2_CLR_ODD_LINE_PATTERN_SHIFT (16U) +/*! ODD_LINE_PATTERN + * 0b000..RGB + * 0b001..RBG + * 0b010..GBR + * 0b011..GRB + * 0b100..BRG + * 0b101..BGR + */ #define LCDIF_CTRL2_CLR_ODD_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_ODD_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_CLR_ODD_LINE_PATTERN_MASK) #define LCDIF_CTRL2_CLR_RSRVD4_MASK (0x80000U) #define LCDIF_CTRL2_CLR_RSRVD4_SHIFT (19U) @@ -13680,23 +21701,48 @@ typedef struct { #define LCDIF_CTRL2_CLR_BURST_LEN_8(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_BURST_LEN_8_SHIFT)) & LCDIF_CTRL2_CLR_BURST_LEN_8_MASK) #define LCDIF_CTRL2_CLR_OUTSTANDING_REQS_MASK (0xE00000U) #define LCDIF_CTRL2_CLR_OUTSTANDING_REQS_SHIFT (21U) +/*! OUTSTANDING_REQS + * 0b000..REQ_1 + * 0b001..REQ_2 + * 0b010..REQ_4 + * 0b011..REQ_8 + * 0b100..REQ_16 + */ #define LCDIF_CTRL2_CLR_OUTSTANDING_REQS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_OUTSTANDING_REQS_SHIFT)) & LCDIF_CTRL2_CLR_OUTSTANDING_REQS_MASK) #define LCDIF_CTRL2_CLR_RSRVD5_MASK (0xFF000000U) #define LCDIF_CTRL2_CLR_RSRVD5_SHIFT (24U) #define LCDIF_CTRL2_CLR_RSRVD5(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_RSRVD5_SHIFT)) & LCDIF_CTRL2_CLR_RSRVD5_MASK) +/*! @} */ -/*! @name CTRL2_TOG - eLCDIF General Control2 Register */ +/*! @name CTRL2_TOG - LCDIF General Control2 Register */ +/*! @{ */ #define LCDIF_CTRL2_TOG_RSRVD0_MASK (0xFFFU) #define LCDIF_CTRL2_TOG_RSRVD0_SHIFT (0U) #define LCDIF_CTRL2_TOG_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_RSRVD0_SHIFT)) & LCDIF_CTRL2_TOG_RSRVD0_MASK) #define LCDIF_CTRL2_TOG_EVEN_LINE_PATTERN_MASK (0x7000U) #define LCDIF_CTRL2_TOG_EVEN_LINE_PATTERN_SHIFT (12U) +/*! EVEN_LINE_PATTERN + * 0b000..RGB + * 0b001..RBG + * 0b010..GBR + * 0b011..GRB + * 0b100..BRG + * 0b101..BGR + */ #define LCDIF_CTRL2_TOG_EVEN_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_EVEN_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_TOG_EVEN_LINE_PATTERN_MASK) #define LCDIF_CTRL2_TOG_RSRVD3_MASK (0x8000U) #define LCDIF_CTRL2_TOG_RSRVD3_SHIFT (15U) #define LCDIF_CTRL2_TOG_RSRVD3(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_RSRVD3_SHIFT)) & LCDIF_CTRL2_TOG_RSRVD3_MASK) #define LCDIF_CTRL2_TOG_ODD_LINE_PATTERN_MASK (0x70000U) #define LCDIF_CTRL2_TOG_ODD_LINE_PATTERN_SHIFT (16U) +/*! ODD_LINE_PATTERN + * 0b000..RGB + * 0b001..RBG + * 0b010..GBR + * 0b011..GRB + * 0b100..BRG + * 0b101..BGR + */ #define LCDIF_CTRL2_TOG_ODD_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_ODD_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_TOG_ODD_LINE_PATTERN_MASK) #define LCDIF_CTRL2_TOG_RSRVD4_MASK (0x80000U) #define LCDIF_CTRL2_TOG_RSRVD4_SHIFT (19U) @@ -13706,30 +21752,45 @@ typedef struct { #define LCDIF_CTRL2_TOG_BURST_LEN_8(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_BURST_LEN_8_SHIFT)) & LCDIF_CTRL2_TOG_BURST_LEN_8_MASK) #define LCDIF_CTRL2_TOG_OUTSTANDING_REQS_MASK (0xE00000U) #define LCDIF_CTRL2_TOG_OUTSTANDING_REQS_SHIFT (21U) +/*! OUTSTANDING_REQS + * 0b000..REQ_1 + * 0b001..REQ_2 + * 0b010..REQ_4 + * 0b011..REQ_8 + * 0b100..REQ_16 + */ #define LCDIF_CTRL2_TOG_OUTSTANDING_REQS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_OUTSTANDING_REQS_SHIFT)) & LCDIF_CTRL2_TOG_OUTSTANDING_REQS_MASK) #define LCDIF_CTRL2_TOG_RSRVD5_MASK (0xFF000000U) #define LCDIF_CTRL2_TOG_RSRVD5_SHIFT (24U) #define LCDIF_CTRL2_TOG_RSRVD5(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_RSRVD5_SHIFT)) & LCDIF_CTRL2_TOG_RSRVD5_MASK) +/*! @} */ -/*! @name TRANSFER_COUNT - eLCDIF Horizontal and Vertical Valid Data Count Register */ +/*! @name TRANSFER_COUNT - LCDIF Horizontal and Vertical Valid Data Count Register */ +/*! @{ */ #define LCDIF_TRANSFER_COUNT_H_COUNT_MASK (0xFFFFU) #define LCDIF_TRANSFER_COUNT_H_COUNT_SHIFT (0U) #define LCDIF_TRANSFER_COUNT_H_COUNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_TRANSFER_COUNT_H_COUNT_SHIFT)) & LCDIF_TRANSFER_COUNT_H_COUNT_MASK) #define LCDIF_TRANSFER_COUNT_V_COUNT_MASK (0xFFFF0000U) #define LCDIF_TRANSFER_COUNT_V_COUNT_SHIFT (16U) #define LCDIF_TRANSFER_COUNT_V_COUNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_TRANSFER_COUNT_V_COUNT_SHIFT)) & LCDIF_TRANSFER_COUNT_V_COUNT_MASK) +/*! @} */ /*! @name CUR_BUF - LCD Interface Current Buffer Address Register */ +/*! @{ */ #define LCDIF_CUR_BUF_ADDR_MASK (0xFFFFFFFFU) #define LCDIF_CUR_BUF_ADDR_SHIFT (0U) #define LCDIF_CUR_BUF_ADDR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CUR_BUF_ADDR_SHIFT)) & LCDIF_CUR_BUF_ADDR_MASK) +/*! @} */ /*! @name NEXT_BUF - LCD Interface Next Buffer Address Register */ +/*! @{ */ #define LCDIF_NEXT_BUF_ADDR_MASK (0xFFFFFFFFU) #define LCDIF_NEXT_BUF_ADDR_SHIFT (0U) #define LCDIF_NEXT_BUF_ADDR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_NEXT_BUF_ADDR_SHIFT)) & LCDIF_NEXT_BUF_ADDR_MASK) +/*! @} */ -/*! @name VDCTRL0 - eLCDIF VSYNC Mode and Dotclk Mode Control Register0 */ +/*! @name VDCTRL0 - LCDIF VSYNC Mode and Dotclk Mode Control Register0 */ +/*! @{ */ #define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_MASK (0x3FFFFU) #define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_SHIFT (0U) #define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_SHIFT)) & LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_MASK) @@ -13766,8 +21827,10 @@ typedef struct { #define LCDIF_VDCTRL0_RSRVD2_MASK (0xE0000000U) #define LCDIF_VDCTRL0_RSRVD2_SHIFT (29U) #define LCDIF_VDCTRL0_RSRVD2(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_RSRVD2_SHIFT)) & LCDIF_VDCTRL0_RSRVD2_MASK) +/*! @} */ -/*! @name VDCTRL0_SET - eLCDIF VSYNC Mode and Dotclk Mode Control Register0 */ +/*! @name VDCTRL0_SET - LCDIF VSYNC Mode and Dotclk Mode Control Register0 */ +/*! @{ */ #define LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_MASK (0x3FFFFU) #define LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_SHIFT (0U) #define LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_SHIFT)) & LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_MASK) @@ -13804,8 +21867,10 @@ typedef struct { #define LCDIF_VDCTRL0_SET_RSRVD2_MASK (0xE0000000U) #define LCDIF_VDCTRL0_SET_RSRVD2_SHIFT (29U) #define LCDIF_VDCTRL0_SET_RSRVD2(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_RSRVD2_SHIFT)) & LCDIF_VDCTRL0_SET_RSRVD2_MASK) +/*! @} */ -/*! @name VDCTRL0_CLR - eLCDIF VSYNC Mode and Dotclk Mode Control Register0 */ +/*! @name VDCTRL0_CLR - LCDIF VSYNC Mode and Dotclk Mode Control Register0 */ +/*! @{ */ #define LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_MASK (0x3FFFFU) #define LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_SHIFT (0U) #define LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_SHIFT)) & LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_MASK) @@ -13842,8 +21907,10 @@ typedef struct { #define LCDIF_VDCTRL0_CLR_RSRVD2_MASK (0xE0000000U) #define LCDIF_VDCTRL0_CLR_RSRVD2_SHIFT (29U) #define LCDIF_VDCTRL0_CLR_RSRVD2(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_RSRVD2_SHIFT)) & LCDIF_VDCTRL0_CLR_RSRVD2_MASK) +/*! @} */ -/*! @name VDCTRL0_TOG - eLCDIF VSYNC Mode and Dotclk Mode Control Register0 */ +/*! @name VDCTRL0_TOG - LCDIF VSYNC Mode and Dotclk Mode Control Register0 */ +/*! @{ */ #define LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_MASK (0x3FFFFU) #define LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_SHIFT (0U) #define LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_SHIFT)) & LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_MASK) @@ -13880,21 +21947,27 @@ typedef struct { #define LCDIF_VDCTRL0_TOG_RSRVD2_MASK (0xE0000000U) #define LCDIF_VDCTRL0_TOG_RSRVD2_SHIFT (29U) #define LCDIF_VDCTRL0_TOG_RSRVD2(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_RSRVD2_SHIFT)) & LCDIF_VDCTRL0_TOG_RSRVD2_MASK) +/*! @} */ -/*! @name VDCTRL1 - eLCDIF VSYNC Mode and Dotclk Mode Control Register1 */ +/*! @name VDCTRL1 - LCDIF VSYNC Mode and Dotclk Mode Control Register1 */ +/*! @{ */ #define LCDIF_VDCTRL1_VSYNC_PERIOD_MASK (0xFFFFFFFFU) #define LCDIF_VDCTRL1_VSYNC_PERIOD_SHIFT (0U) #define LCDIF_VDCTRL1_VSYNC_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL1_VSYNC_PERIOD_SHIFT)) & LCDIF_VDCTRL1_VSYNC_PERIOD_MASK) +/*! @} */ /*! @name VDCTRL2 - LCDIF VSYNC Mode and Dotclk Mode Control Register2 */ +/*! @{ */ #define LCDIF_VDCTRL2_HSYNC_PERIOD_MASK (0x3FFFFU) #define LCDIF_VDCTRL2_HSYNC_PERIOD_SHIFT (0U) #define LCDIF_VDCTRL2_HSYNC_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL2_HSYNC_PERIOD_SHIFT)) & LCDIF_VDCTRL2_HSYNC_PERIOD_MASK) #define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_MASK (0xFFFC0000U) #define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_SHIFT (18U) #define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_SHIFT)) & LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_MASK) +/*! @} */ -/*! @name VDCTRL3 - eLCDIF VSYNC Mode and Dotclk Mode Control Register3 */ +/*! @name VDCTRL3 - LCDIF VSYNC Mode and Dotclk Mode Control Register3 */ +/*! @{ */ #define LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_MASK (0xFFFFU) #define LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_SHIFT (0U) #define LCDIF_VDCTRL3_VERTICAL_WAIT_CNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_SHIFT)) & LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_MASK) @@ -13910,8 +21983,10 @@ typedef struct { #define LCDIF_VDCTRL3_RSRVD0_MASK (0xC0000000U) #define LCDIF_VDCTRL3_RSRVD0_SHIFT (30U) #define LCDIF_VDCTRL3_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL3_RSRVD0_SHIFT)) & LCDIF_VDCTRL3_RSRVD0_MASK) +/*! @} */ -/*! @name VDCTRL4 - eLCDIF VSYNC Mode and Dotclk Mode Control Register4 */ +/*! @name VDCTRL4 - LCDIF VSYNC Mode and Dotclk Mode Control Register4 */ +/*! @{ */ #define LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_MASK (0x3FFFFU) #define LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_SHIFT (0U) #define LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_SHIFT)) & LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_MASK) @@ -13924,18 +21999,24 @@ typedef struct { #define LCDIF_VDCTRL4_DOTCLK_DLY_SEL_MASK (0xE0000000U) #define LCDIF_VDCTRL4_DOTCLK_DLY_SEL_SHIFT (29U) #define LCDIF_VDCTRL4_DOTCLK_DLY_SEL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL4_DOTCLK_DLY_SEL_SHIFT)) & LCDIF_VDCTRL4_DOTCLK_DLY_SEL_MASK) +/*! @} */ /*! @name BM_ERROR_STAT - Bus Master Error Status Register */ +/*! @{ */ #define LCDIF_BM_ERROR_STAT_ADDR_MASK (0xFFFFFFFFU) #define LCDIF_BM_ERROR_STAT_ADDR_SHIFT (0U) #define LCDIF_BM_ERROR_STAT_ADDR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_BM_ERROR_STAT_ADDR_SHIFT)) & LCDIF_BM_ERROR_STAT_ADDR_MASK) +/*! @} */ /*! @name CRC_STAT - CRC Status Register */ +/*! @{ */ #define LCDIF_CRC_STAT_CRC_VALUE_MASK (0xFFFFFFFFU) #define LCDIF_CRC_STAT_CRC_VALUE_SHIFT (0U) #define LCDIF_CRC_STAT_CRC_VALUE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CRC_STAT_CRC_VALUE_SHIFT)) & LCDIF_CRC_STAT_CRC_VALUE_MASK) +/*! @} */ /*! @name STAT - LCD Interface Status Register */ +/*! @{ */ #define LCDIF_STAT_LFIFO_COUNT_MASK (0x1FFU) #define LCDIF_STAT_LFIFO_COUNT_SHIFT (0U) #define LCDIF_STAT_LFIFO_COUNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_LFIFO_COUNT_SHIFT)) & LCDIF_STAT_LFIFO_COUNT_MASK) @@ -13960,8 +22041,10 @@ typedef struct { #define LCDIF_STAT_PRESENT_MASK (0x80000000U) #define LCDIF_STAT_PRESENT_SHIFT (31U) #define LCDIF_STAT_PRESENT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_PRESENT_SHIFT)) & LCDIF_STAT_PRESENT_MASK) +/*! @} */ -/*! @name THRES - eLCDIF Threshold Register */ +/*! @name THRES - LCDIF Threshold Register */ +/*! @{ */ #define LCDIF_THRES_PANIC_MASK (0x1FFU) #define LCDIF_THRES_PANIC_SHIFT (0U) #define LCDIF_THRES_PANIC(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_THRES_PANIC_SHIFT)) & LCDIF_THRES_PANIC_MASK) @@ -13974,178 +22057,264 @@ typedef struct { #define LCDIF_THRES_RSRVD2_MASK (0xFE000000U) #define LCDIF_THRES_RSRVD2_SHIFT (25U) #define LCDIF_THRES_RSRVD2(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_THRES_RSRVD2_SHIFT)) & LCDIF_THRES_RSRVD2_MASK) +/*! @} */ /*! @name PIGEONCTRL0 - LCDIF Pigeon Mode Control0 Register */ +/*! @{ */ #define LCDIF_PIGEONCTRL0_FD_PERIOD_MASK (0xFFFU) #define LCDIF_PIGEONCTRL0_FD_PERIOD_SHIFT (0U) #define LCDIF_PIGEONCTRL0_FD_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_FD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_FD_PERIOD_MASK) #define LCDIF_PIGEONCTRL0_LD_PERIOD_MASK (0xFFF0000U) #define LCDIF_PIGEONCTRL0_LD_PERIOD_SHIFT (16U) #define LCDIF_PIGEONCTRL0_LD_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_LD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_LD_PERIOD_MASK) +/*! @} */ /*! @name PIGEONCTRL0_SET - LCDIF Pigeon Mode Control0 Register */ +/*! @{ */ #define LCDIF_PIGEONCTRL0_SET_FD_PERIOD_MASK (0xFFFU) #define LCDIF_PIGEONCTRL0_SET_FD_PERIOD_SHIFT (0U) #define LCDIF_PIGEONCTRL0_SET_FD_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_SET_FD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_SET_FD_PERIOD_MASK) #define LCDIF_PIGEONCTRL0_SET_LD_PERIOD_MASK (0xFFF0000U) #define LCDIF_PIGEONCTRL0_SET_LD_PERIOD_SHIFT (16U) #define LCDIF_PIGEONCTRL0_SET_LD_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_SET_LD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_SET_LD_PERIOD_MASK) +/*! @} */ /*! @name PIGEONCTRL0_CLR - LCDIF Pigeon Mode Control0 Register */ +/*! @{ */ #define LCDIF_PIGEONCTRL0_CLR_FD_PERIOD_MASK (0xFFFU) #define LCDIF_PIGEONCTRL0_CLR_FD_PERIOD_SHIFT (0U) #define LCDIF_PIGEONCTRL0_CLR_FD_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_CLR_FD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_CLR_FD_PERIOD_MASK) #define LCDIF_PIGEONCTRL0_CLR_LD_PERIOD_MASK (0xFFF0000U) #define LCDIF_PIGEONCTRL0_CLR_LD_PERIOD_SHIFT (16U) #define LCDIF_PIGEONCTRL0_CLR_LD_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_CLR_LD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_CLR_LD_PERIOD_MASK) +/*! @} */ /*! @name PIGEONCTRL0_TOG - LCDIF Pigeon Mode Control0 Register */ +/*! @{ */ #define LCDIF_PIGEONCTRL0_TOG_FD_PERIOD_MASK (0xFFFU) #define LCDIF_PIGEONCTRL0_TOG_FD_PERIOD_SHIFT (0U) #define LCDIF_PIGEONCTRL0_TOG_FD_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_TOG_FD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_TOG_FD_PERIOD_MASK) #define LCDIF_PIGEONCTRL0_TOG_LD_PERIOD_MASK (0xFFF0000U) #define LCDIF_PIGEONCTRL0_TOG_LD_PERIOD_SHIFT (16U) #define LCDIF_PIGEONCTRL0_TOG_LD_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_TOG_LD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_TOG_LD_PERIOD_MASK) +/*! @} */ /*! @name PIGEONCTRL1 - LCDIF Pigeon Mode Control1 Register */ +/*! @{ */ #define LCDIF_PIGEONCTRL1_FRAME_CNT_PERIOD_MASK (0xFFFU) #define LCDIF_PIGEONCTRL1_FRAME_CNT_PERIOD_SHIFT (0U) #define LCDIF_PIGEONCTRL1_FRAME_CNT_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_FRAME_CNT_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL1_FRAME_CNT_PERIOD_MASK) #define LCDIF_PIGEONCTRL1_FRAME_CNT_CYCLES_MASK (0xFFF0000U) #define LCDIF_PIGEONCTRL1_FRAME_CNT_CYCLES_SHIFT (16U) #define LCDIF_PIGEONCTRL1_FRAME_CNT_CYCLES(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_FRAME_CNT_CYCLES_SHIFT)) & LCDIF_PIGEONCTRL1_FRAME_CNT_CYCLES_MASK) +/*! @} */ /*! @name PIGEONCTRL1_SET - LCDIF Pigeon Mode Control1 Register */ +/*! @{ */ #define LCDIF_PIGEONCTRL1_SET_FRAME_CNT_PERIOD_MASK (0xFFFU) #define LCDIF_PIGEONCTRL1_SET_FRAME_CNT_PERIOD_SHIFT (0U) #define LCDIF_PIGEONCTRL1_SET_FRAME_CNT_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_SET_FRAME_CNT_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL1_SET_FRAME_CNT_PERIOD_MASK) #define LCDIF_PIGEONCTRL1_SET_FRAME_CNT_CYCLES_MASK (0xFFF0000U) #define LCDIF_PIGEONCTRL1_SET_FRAME_CNT_CYCLES_SHIFT (16U) #define LCDIF_PIGEONCTRL1_SET_FRAME_CNT_CYCLES(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_SET_FRAME_CNT_CYCLES_SHIFT)) & LCDIF_PIGEONCTRL1_SET_FRAME_CNT_CYCLES_MASK) +/*! @} */ /*! @name PIGEONCTRL1_CLR - LCDIF Pigeon Mode Control1 Register */ +/*! @{ */ #define LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_PERIOD_MASK (0xFFFU) #define LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_PERIOD_SHIFT (0U) #define LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_PERIOD_MASK) #define LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_CYCLES_MASK (0xFFF0000U) #define LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_CYCLES_SHIFT (16U) #define LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_CYCLES(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_CYCLES_SHIFT)) & LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_CYCLES_MASK) +/*! @} */ /*! @name PIGEONCTRL1_TOG - LCDIF Pigeon Mode Control1 Register */ +/*! @{ */ #define LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_PERIOD_MASK (0xFFFU) #define LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_PERIOD_SHIFT (0U) #define LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_PERIOD_MASK) #define LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_CYCLES_MASK (0xFFF0000U) #define LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_CYCLES_SHIFT (16U) #define LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_CYCLES(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_CYCLES_SHIFT)) & LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_CYCLES_MASK) +/*! @} */ /*! @name PIGEONCTRL2 - LCDIF Pigeon Mode Control2 Register */ +/*! @{ */ #define LCDIF_PIGEONCTRL2_PIGEON_DATA_EN_MASK (0x1U) #define LCDIF_PIGEONCTRL2_PIGEON_DATA_EN_SHIFT (0U) #define LCDIF_PIGEONCTRL2_PIGEON_DATA_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_PIGEON_DATA_EN_SHIFT)) & LCDIF_PIGEONCTRL2_PIGEON_DATA_EN_MASK) #define LCDIF_PIGEONCTRL2_PIGEON_CLK_GATE_MASK (0x2U) #define LCDIF_PIGEONCTRL2_PIGEON_CLK_GATE_SHIFT (1U) #define LCDIF_PIGEONCTRL2_PIGEON_CLK_GATE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_PIGEON_CLK_GATE_SHIFT)) & LCDIF_PIGEONCTRL2_PIGEON_CLK_GATE_MASK) +/*! @} */ /*! @name PIGEONCTRL2_SET - LCDIF Pigeon Mode Control2 Register */ +/*! @{ */ #define LCDIF_PIGEONCTRL2_SET_PIGEON_DATA_EN_MASK (0x1U) #define LCDIF_PIGEONCTRL2_SET_PIGEON_DATA_EN_SHIFT (0U) #define LCDIF_PIGEONCTRL2_SET_PIGEON_DATA_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_SET_PIGEON_DATA_EN_SHIFT)) & LCDIF_PIGEONCTRL2_SET_PIGEON_DATA_EN_MASK) #define LCDIF_PIGEONCTRL2_SET_PIGEON_CLK_GATE_MASK (0x2U) #define LCDIF_PIGEONCTRL2_SET_PIGEON_CLK_GATE_SHIFT (1U) #define LCDIF_PIGEONCTRL2_SET_PIGEON_CLK_GATE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_SET_PIGEON_CLK_GATE_SHIFT)) & LCDIF_PIGEONCTRL2_SET_PIGEON_CLK_GATE_MASK) +/*! @} */ /*! @name PIGEONCTRL2_CLR - LCDIF Pigeon Mode Control2 Register */ +/*! @{ */ #define LCDIF_PIGEONCTRL2_CLR_PIGEON_DATA_EN_MASK (0x1U) #define LCDIF_PIGEONCTRL2_CLR_PIGEON_DATA_EN_SHIFT (0U) #define LCDIF_PIGEONCTRL2_CLR_PIGEON_DATA_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_CLR_PIGEON_DATA_EN_SHIFT)) & LCDIF_PIGEONCTRL2_CLR_PIGEON_DATA_EN_MASK) #define LCDIF_PIGEONCTRL2_CLR_PIGEON_CLK_GATE_MASK (0x2U) #define LCDIF_PIGEONCTRL2_CLR_PIGEON_CLK_GATE_SHIFT (1U) #define LCDIF_PIGEONCTRL2_CLR_PIGEON_CLK_GATE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_CLR_PIGEON_CLK_GATE_SHIFT)) & LCDIF_PIGEONCTRL2_CLR_PIGEON_CLK_GATE_MASK) +/*! @} */ /*! @name PIGEONCTRL2_TOG - LCDIF Pigeon Mode Control2 Register */ +/*! @{ */ #define LCDIF_PIGEONCTRL2_TOG_PIGEON_DATA_EN_MASK (0x1U) #define LCDIF_PIGEONCTRL2_TOG_PIGEON_DATA_EN_SHIFT (0U) #define LCDIF_PIGEONCTRL2_TOG_PIGEON_DATA_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_TOG_PIGEON_DATA_EN_SHIFT)) & LCDIF_PIGEONCTRL2_TOG_PIGEON_DATA_EN_MASK) #define LCDIF_PIGEONCTRL2_TOG_PIGEON_CLK_GATE_MASK (0x2U) #define LCDIF_PIGEONCTRL2_TOG_PIGEON_CLK_GATE_SHIFT (1U) #define LCDIF_PIGEONCTRL2_TOG_PIGEON_CLK_GATE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_TOG_PIGEON_CLK_GATE_SHIFT)) & LCDIF_PIGEONCTRL2_TOG_PIGEON_CLK_GATE_MASK) +/*! @} */ /*! @name PIGEON_0 - Panel Interface Signal Generator Register */ +/*! @{ */ #define LCDIF_PIGEON_0_EN_MASK (0x1U) #define LCDIF_PIGEON_0_EN_SHIFT (0U) #define LCDIF_PIGEON_0_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_0_EN_SHIFT)) & LCDIF_PIGEON_0_EN_MASK) #define LCDIF_PIGEON_0_POL_MASK (0x2U) #define LCDIF_PIGEON_0_POL_SHIFT (1U) +/*! POL + * 0b0..Normal Signal (Active high) + * 0b1..Inverted signal (Active low) + */ #define LCDIF_PIGEON_0_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_0_POL_SHIFT)) & LCDIF_PIGEON_0_POL_MASK) #define LCDIF_PIGEON_0_INC_SEL_MASK (0xCU) #define LCDIF_PIGEON_0_INC_SEL_SHIFT (2U) +/*! INC_SEL + * 0b00..pclk + * 0b01..Line start pulse + * 0b10..Frame start pulse + * 0b11..Use another signal as tick event + */ #define LCDIF_PIGEON_0_INC_SEL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_0_INC_SEL_SHIFT)) & LCDIF_PIGEON_0_INC_SEL_MASK) #define LCDIF_PIGEON_0_OFFSET_MASK (0xF0U) #define LCDIF_PIGEON_0_OFFSET_SHIFT (4U) #define LCDIF_PIGEON_0_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_0_OFFSET_SHIFT)) & LCDIF_PIGEON_0_OFFSET_MASK) #define LCDIF_PIGEON_0_MASK_CNT_SEL_MASK (0xF00U) #define LCDIF_PIGEON_0_MASK_CNT_SEL_SHIFT (8U) +/*! MASK_CNT_SEL + * 0b0000..pclk counter within one hscan state + * 0b0001..pclk cycle within one hscan state + * 0b0010..line counter within one vscan state + * 0b0011..line cycle within one vscan state + * 0b0100..frame counter + * 0b0101..frame cycle + * 0b0110..horizontal counter (pclk counter within one line ) + * 0b0111..vertical counter (line counter within one frame) + */ #define LCDIF_PIGEON_0_MASK_CNT_SEL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_0_MASK_CNT_SEL_SHIFT)) & LCDIF_PIGEON_0_MASK_CNT_SEL_MASK) #define LCDIF_PIGEON_0_MASK_CNT_MASK (0xFFF000U) #define LCDIF_PIGEON_0_MASK_CNT_SHIFT (12U) #define LCDIF_PIGEON_0_MASK_CNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_0_MASK_CNT_SHIFT)) & LCDIF_PIGEON_0_MASK_CNT_MASK) #define LCDIF_PIGEON_0_STATE_MASK_MASK (0xFF000000U) #define LCDIF_PIGEON_0_STATE_MASK_SHIFT (24U) +/*! STATE_MASK + * 0b00000001..FRAME SYNC + * 0b00000010..FRAME BEGIN + * 0b00000100..FRAME DATA + * 0b00001000..FRAME END + * 0b00010000..LINE SYNC + * 0b00100000..LINE BEGIN + * 0b01000000..LINE DATA + * 0b10000000..LINE END + */ #define LCDIF_PIGEON_0_STATE_MASK(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_0_STATE_MASK_SHIFT)) & LCDIF_PIGEON_0_STATE_MASK_MASK) +/*! @} */ /* The count of LCDIF_PIGEON_0 */ #define LCDIF_PIGEON_0_COUNT (12U) /*! @name PIGEON_1 - Panel Interface Signal Generator Register */ +/*! @{ */ #define LCDIF_PIGEON_1_SET_CNT_MASK (0xFFFFU) #define LCDIF_PIGEON_1_SET_CNT_SHIFT (0U) +/*! SET_CNT + * 0b0000000000000000..Start as active + */ #define LCDIF_PIGEON_1_SET_CNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_1_SET_CNT_SHIFT)) & LCDIF_PIGEON_1_SET_CNT_MASK) #define LCDIF_PIGEON_1_CLR_CNT_MASK (0xFFFF0000U) #define LCDIF_PIGEON_1_CLR_CNT_SHIFT (16U) +/*! CLR_CNT + * 0b0000000000000000..Keep active until mask off + */ #define LCDIF_PIGEON_1_CLR_CNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_1_CLR_CNT_SHIFT)) & LCDIF_PIGEON_1_CLR_CNT_MASK) +/*! @} */ /* The count of LCDIF_PIGEON_1 */ #define LCDIF_PIGEON_1_COUNT (12U) /*! @name PIGEON_2 - Panel Interface Signal Generator Register */ +/*! @{ */ #define LCDIF_PIGEON_2_SIG_LOGIC_MASK (0xFU) #define LCDIF_PIGEON_2_SIG_LOGIC_SHIFT (0U) +/*! SIG_LOGIC + * 0b0000..No logic operation + * 0b0001..sigout = sig_another AND this_sig + * 0b0010..sigout = sig_another OR this_sig + * 0b0011..mask = sig_another AND other_masks + */ #define LCDIF_PIGEON_2_SIG_LOGIC(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_2_SIG_LOGIC_SHIFT)) & LCDIF_PIGEON_2_SIG_LOGIC_MASK) #define LCDIF_PIGEON_2_SIG_ANOTHER_MASK (0x1F0U) #define LCDIF_PIGEON_2_SIG_ANOTHER_SHIFT (4U) +/*! SIG_ANOTHER + * 0b00000..Keep active until mask off + */ #define LCDIF_PIGEON_2_SIG_ANOTHER(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_2_SIG_ANOTHER_SHIFT)) & LCDIF_PIGEON_2_SIG_ANOTHER_MASK) #define LCDIF_PIGEON_2_RSVD_MASK (0xFFFFFE00U) #define LCDIF_PIGEON_2_RSVD_SHIFT (9U) #define LCDIF_PIGEON_2_RSVD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_2_RSVD_SHIFT)) & LCDIF_PIGEON_2_RSVD_MASK) +/*! @} */ /* The count of LCDIF_PIGEON_2 */ #define LCDIF_PIGEON_2_COUNT (12U) /*! @name LUT_CTRL - Lookup Table Data Register. */ +/*! @{ */ #define LCDIF_LUT_CTRL_LUT_BYPASS_MASK (0x1U) #define LCDIF_LUT_CTRL_LUT_BYPASS_SHIFT (0U) #define LCDIF_LUT_CTRL_LUT_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_LUT_CTRL_LUT_BYPASS_SHIFT)) & LCDIF_LUT_CTRL_LUT_BYPASS_MASK) +/*! @} */ /*! @name LUT0_ADDR - Lookup Table Control Register. */ +/*! @{ */ #define LCDIF_LUT0_ADDR_ADDR_MASK (0xFFU) #define LCDIF_LUT0_ADDR_ADDR_SHIFT (0U) #define LCDIF_LUT0_ADDR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_LUT0_ADDR_ADDR_SHIFT)) & LCDIF_LUT0_ADDR_ADDR_MASK) +/*! @} */ /*! @name LUT0_DATA - Lookup Table Data Register. */ +/*! @{ */ #define LCDIF_LUT0_DATA_DATA_MASK (0xFFFFFFFFU) #define LCDIF_LUT0_DATA_DATA_SHIFT (0U) #define LCDIF_LUT0_DATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_LUT0_DATA_DATA_SHIFT)) & LCDIF_LUT0_DATA_DATA_MASK) +/*! @} */ /*! @name LUT1_ADDR - Lookup Table Control Register. */ +/*! @{ */ #define LCDIF_LUT1_ADDR_ADDR_MASK (0xFFU) #define LCDIF_LUT1_ADDR_ADDR_SHIFT (0U) #define LCDIF_LUT1_ADDR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_LUT1_ADDR_ADDR_SHIFT)) & LCDIF_LUT1_ADDR_ADDR_MASK) +/*! @} */ /*! @name LUT1_DATA - Lookup Table Data Register. */ +/*! @{ */ #define LCDIF_LUT1_DATA_DATA_MASK (0xFFFFFFFFU) #define LCDIF_LUT1_DATA_DATA_SHIFT (0U) #define LCDIF_LUT1_DATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_LUT1_DATA_DATA_SHIFT)) & LCDIF_LUT1_DATA_DATA_MASK) +/*! @} */ /*! @@ -14233,8 +22402,13 @@ typedef struct { */ /*! @name VERID - Version ID Register */ +/*! @{ */ #define LPI2C_VERID_FEATURE_MASK (0xFFFFU) #define LPI2C_VERID_FEATURE_SHIFT (0U) +/*! FEATURE - Feature Specification Number + * 0b0000000000000010..Master only, with standard feature set + * 0b0000000000000011..Master and slave, with standard feature set + */ #define LPI2C_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_FEATURE_SHIFT)) & LPI2C_VERID_FEATURE_MASK) #define LPI2C_VERID_MINOR_MASK (0xFF0000U) #define LPI2C_VERID_MINOR_SHIFT (16U) @@ -14242,145 +22416,335 @@ typedef struct { #define LPI2C_VERID_MAJOR_MASK (0xFF000000U) #define LPI2C_VERID_MAJOR_SHIFT (24U) #define LPI2C_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_MAJOR_SHIFT)) & LPI2C_VERID_MAJOR_MASK) +/*! @} */ /*! @name PARAM - Parameter Register */ +/*! @{ */ #define LPI2C_PARAM_MTXFIFO_MASK (0xFU) #define LPI2C_PARAM_MTXFIFO_SHIFT (0U) #define LPI2C_PARAM_MTXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_PARAM_MTXFIFO_SHIFT)) & LPI2C_PARAM_MTXFIFO_MASK) #define LPI2C_PARAM_MRXFIFO_MASK (0xF00U) #define LPI2C_PARAM_MRXFIFO_SHIFT (8U) #define LPI2C_PARAM_MRXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_PARAM_MRXFIFO_SHIFT)) & LPI2C_PARAM_MRXFIFO_MASK) +/*! @} */ /*! @name MCR - Master Control Register */ +/*! @{ */ #define LPI2C_MCR_MEN_MASK (0x1U) #define LPI2C_MCR_MEN_SHIFT (0U) +/*! MEN - Master Enable + * 0b0..Master logic is disabled + * 0b1..Master logic is enabled + */ #define LPI2C_MCR_MEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_MEN_SHIFT)) & LPI2C_MCR_MEN_MASK) #define LPI2C_MCR_RST_MASK (0x2U) #define LPI2C_MCR_RST_SHIFT (1U) +/*! RST - Software Reset + * 0b0..Master logic is not reset + * 0b1..Master logic is reset + */ #define LPI2C_MCR_RST(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RST_SHIFT)) & LPI2C_MCR_RST_MASK) #define LPI2C_MCR_DOZEN_MASK (0x4U) #define LPI2C_MCR_DOZEN_SHIFT (2U) +/*! DOZEN - Doze mode enable + * 0b0..Master is enabled in Doze mode + * 0b1..Master is disabled in Doze mode + */ #define LPI2C_MCR_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_DOZEN_SHIFT)) & LPI2C_MCR_DOZEN_MASK) #define LPI2C_MCR_DBGEN_MASK (0x8U) #define LPI2C_MCR_DBGEN_SHIFT (3U) +/*! DBGEN - Debug Enable + * 0b0..Master is disabled in debug mode + * 0b1..Master is enabled in debug mode + */ #define LPI2C_MCR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_DBGEN_SHIFT)) & LPI2C_MCR_DBGEN_MASK) #define LPI2C_MCR_RTF_MASK (0x100U) #define LPI2C_MCR_RTF_SHIFT (8U) +/*! RTF - Reset Transmit FIFO + * 0b0..No effect + * 0b1..Transmit FIFO is reset + */ #define LPI2C_MCR_RTF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RTF_SHIFT)) & LPI2C_MCR_RTF_MASK) #define LPI2C_MCR_RRF_MASK (0x200U) #define LPI2C_MCR_RRF_SHIFT (9U) +/*! RRF - Reset Receive FIFO + * 0b0..No effect + * 0b1..Receive FIFO is reset + */ #define LPI2C_MCR_RRF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RRF_SHIFT)) & LPI2C_MCR_RRF_MASK) +/*! @} */ /*! @name MSR - Master Status Register */ +/*! @{ */ #define LPI2C_MSR_TDF_MASK (0x1U) #define LPI2C_MSR_TDF_SHIFT (0U) +/*! TDF - Transmit Data Flag + * 0b0..Transmit data is not requested + * 0b1..Transmit data is requested + */ #define LPI2C_MSR_TDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_TDF_SHIFT)) & LPI2C_MSR_TDF_MASK) #define LPI2C_MSR_RDF_MASK (0x2U) #define LPI2C_MSR_RDF_SHIFT (1U) +/*! RDF - Receive Data Flag + * 0b0..Receive Data is not ready + * 0b1..Receive data is ready + */ #define LPI2C_MSR_RDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_RDF_SHIFT)) & LPI2C_MSR_RDF_MASK) #define LPI2C_MSR_EPF_MASK (0x100U) #define LPI2C_MSR_EPF_SHIFT (8U) +/*! EPF - End Packet Flag + * 0b0..Master has not generated a STOP or Repeated START condition + * 0b1..Master has generated a STOP or Repeated START condition + */ #define LPI2C_MSR_EPF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_EPF_SHIFT)) & LPI2C_MSR_EPF_MASK) #define LPI2C_MSR_SDF_MASK (0x200U) #define LPI2C_MSR_SDF_SHIFT (9U) +/*! SDF - STOP Detect Flag + * 0b0..Master has not generated a STOP condition + * 0b1..Master has generated a STOP condition + */ #define LPI2C_MSR_SDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_SDF_SHIFT)) & LPI2C_MSR_SDF_MASK) #define LPI2C_MSR_NDF_MASK (0x400U) #define LPI2C_MSR_NDF_SHIFT (10U) +/*! NDF - NACK Detect Flag + * 0b0..Unexpected NACK was not detected + * 0b1..Unexpected NACK was detected + */ #define LPI2C_MSR_NDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_NDF_SHIFT)) & LPI2C_MSR_NDF_MASK) #define LPI2C_MSR_ALF_MASK (0x800U) #define LPI2C_MSR_ALF_SHIFT (11U) +/*! ALF - Arbitration Lost Flag + * 0b0..Master has not lost arbitration + * 0b1..Master has lost arbitration + */ #define LPI2C_MSR_ALF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_ALF_SHIFT)) & LPI2C_MSR_ALF_MASK) #define LPI2C_MSR_FEF_MASK (0x1000U) #define LPI2C_MSR_FEF_SHIFT (12U) +/*! FEF - FIFO Error Flag + * 0b0..No error + * 0b1..Master sending or receiving data without a START condition + */ #define LPI2C_MSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_FEF_SHIFT)) & LPI2C_MSR_FEF_MASK) #define LPI2C_MSR_PLTF_MASK (0x2000U) #define LPI2C_MSR_PLTF_SHIFT (13U) +/*! PLTF - Pin Low Timeout Flag + * 0b0..Pin low timeout has not occurred or is disabled + * 0b1..Pin low timeout has occurred + */ #define LPI2C_MSR_PLTF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_PLTF_SHIFT)) & LPI2C_MSR_PLTF_MASK) #define LPI2C_MSR_DMF_MASK (0x4000U) #define LPI2C_MSR_DMF_SHIFT (14U) +/*! DMF - Data Match Flag + * 0b0..Have not received matching data + * 0b1..Have received matching data + */ #define LPI2C_MSR_DMF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_DMF_SHIFT)) & LPI2C_MSR_DMF_MASK) #define LPI2C_MSR_MBF_MASK (0x1000000U) #define LPI2C_MSR_MBF_SHIFT (24U) +/*! MBF - Master Busy Flag + * 0b0..I2C Master is idle + * 0b1..I2C Master is busy + */ #define LPI2C_MSR_MBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_MBF_SHIFT)) & LPI2C_MSR_MBF_MASK) #define LPI2C_MSR_BBF_MASK (0x2000000U) #define LPI2C_MSR_BBF_SHIFT (25U) +/*! BBF - Bus Busy Flag + * 0b0..I2C Bus is idle + * 0b1..I2C Bus is busy + */ #define LPI2C_MSR_BBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_BBF_SHIFT)) & LPI2C_MSR_BBF_MASK) +/*! @} */ /*! @name MIER - Master Interrupt Enable Register */ +/*! @{ */ #define LPI2C_MIER_TDIE_MASK (0x1U) #define LPI2C_MIER_TDIE_SHIFT (0U) +/*! TDIE - Transmit Data Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ #define LPI2C_MIER_TDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_TDIE_SHIFT)) & LPI2C_MIER_TDIE_MASK) #define LPI2C_MIER_RDIE_MASK (0x2U) #define LPI2C_MIER_RDIE_SHIFT (1U) +/*! RDIE - Receive Data Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ #define LPI2C_MIER_RDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_RDIE_SHIFT)) & LPI2C_MIER_RDIE_MASK) #define LPI2C_MIER_EPIE_MASK (0x100U) #define LPI2C_MIER_EPIE_SHIFT (8U) +/*! EPIE - End Packet Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ #define LPI2C_MIER_EPIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_EPIE_SHIFT)) & LPI2C_MIER_EPIE_MASK) #define LPI2C_MIER_SDIE_MASK (0x200U) #define LPI2C_MIER_SDIE_SHIFT (9U) +/*! SDIE - STOP Detect Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ #define LPI2C_MIER_SDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_SDIE_SHIFT)) & LPI2C_MIER_SDIE_MASK) #define LPI2C_MIER_NDIE_MASK (0x400U) #define LPI2C_MIER_NDIE_SHIFT (10U) +/*! NDIE - NACK Detect Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ #define LPI2C_MIER_NDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_NDIE_SHIFT)) & LPI2C_MIER_NDIE_MASK) #define LPI2C_MIER_ALIE_MASK (0x800U) #define LPI2C_MIER_ALIE_SHIFT (11U) +/*! ALIE - Arbitration Lost Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ #define LPI2C_MIER_ALIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_ALIE_SHIFT)) & LPI2C_MIER_ALIE_MASK) #define LPI2C_MIER_FEIE_MASK (0x1000U) #define LPI2C_MIER_FEIE_SHIFT (12U) +/*! FEIE - FIFO Error Interrupt Enable + * 0b0..Enabled + * 0b1..Disabled + */ #define LPI2C_MIER_FEIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_FEIE_SHIFT)) & LPI2C_MIER_FEIE_MASK) #define LPI2C_MIER_PLTIE_MASK (0x2000U) #define LPI2C_MIER_PLTIE_SHIFT (13U) +/*! PLTIE - Pin Low Timeout Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ #define LPI2C_MIER_PLTIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_PLTIE_SHIFT)) & LPI2C_MIER_PLTIE_MASK) #define LPI2C_MIER_DMIE_MASK (0x4000U) #define LPI2C_MIER_DMIE_SHIFT (14U) +/*! DMIE - Data Match Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ #define LPI2C_MIER_DMIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_DMIE_SHIFT)) & LPI2C_MIER_DMIE_MASK) +/*! @} */ /*! @name MDER - Master DMA Enable Register */ +/*! @{ */ #define LPI2C_MDER_TDDE_MASK (0x1U) #define LPI2C_MDER_TDDE_SHIFT (0U) +/*! TDDE - Transmit Data DMA Enable + * 0b0..DMA request is disabled + * 0b1..DMA request is enabled + */ #define LPI2C_MDER_TDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDER_TDDE_SHIFT)) & LPI2C_MDER_TDDE_MASK) #define LPI2C_MDER_RDDE_MASK (0x2U) #define LPI2C_MDER_RDDE_SHIFT (1U) +/*! RDDE - Receive Data DMA Enable + * 0b0..DMA request is disabled + * 0b1..DMA request is enabled + */ #define LPI2C_MDER_RDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDER_RDDE_SHIFT)) & LPI2C_MDER_RDDE_MASK) +/*! @} */ /*! @name MCFGR0 - Master Configuration Register 0 */ +/*! @{ */ #define LPI2C_MCFGR0_HREN_MASK (0x1U) #define LPI2C_MCFGR0_HREN_SHIFT (0U) +/*! HREN - Host Request Enable + * 0b0..Host request input is disabled + * 0b1..Host request input is enabled + */ #define LPI2C_MCFGR0_HREN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HREN_SHIFT)) & LPI2C_MCFGR0_HREN_MASK) #define LPI2C_MCFGR0_HRPOL_MASK (0x2U) #define LPI2C_MCFGR0_HRPOL_SHIFT (1U) +/*! HRPOL - Host Request Polarity + * 0b0..Active low + * 0b1..Active high + */ #define LPI2C_MCFGR0_HRPOL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HRPOL_SHIFT)) & LPI2C_MCFGR0_HRPOL_MASK) #define LPI2C_MCFGR0_HRSEL_MASK (0x4U) #define LPI2C_MCFGR0_HRSEL_SHIFT (2U) +/*! HRSEL - Host Request Select + * 0b0..Host request input is pin HREQ + * 0b1..Host request input is input trigger + */ #define LPI2C_MCFGR0_HRSEL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HRSEL_SHIFT)) & LPI2C_MCFGR0_HRSEL_MASK) #define LPI2C_MCFGR0_CIRFIFO_MASK (0x100U) #define LPI2C_MCFGR0_CIRFIFO_SHIFT (8U) +/*! CIRFIFO - Circular FIFO Enable + * 0b0..Circular FIFO is disabled + * 0b1..Circular FIFO is enabled + */ #define LPI2C_MCFGR0_CIRFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_CIRFIFO_SHIFT)) & LPI2C_MCFGR0_CIRFIFO_MASK) #define LPI2C_MCFGR0_RDMO_MASK (0x200U) #define LPI2C_MCFGR0_RDMO_SHIFT (9U) +/*! RDMO - Receive Data Match Only + * 0b0..Received data is stored in the receive FIFO + * 0b1..Received data is discarded unless the the Data Match Flag (MSR[DMF]) is set + */ #define LPI2C_MCFGR0_RDMO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_RDMO_SHIFT)) & LPI2C_MCFGR0_RDMO_MASK) +/*! @} */ /*! @name MCFGR1 - Master Configuration Register 1 */ +/*! @{ */ #define LPI2C_MCFGR1_PRESCALE_MASK (0x7U) #define LPI2C_MCFGR1_PRESCALE_SHIFT (0U) +/*! PRESCALE - Prescaler + * 0b000..Divide by 1 + * 0b001..Divide by 2 + * 0b010..Divide by 4 + * 0b011..Divide by 8 + * 0b100..Divide by 16 + * 0b101..Divide by 32 + * 0b110..Divide by 64 + * 0b111..Divide by 128 + */ #define LPI2C_MCFGR1_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_PRESCALE_SHIFT)) & LPI2C_MCFGR1_PRESCALE_MASK) #define LPI2C_MCFGR1_AUTOSTOP_MASK (0x100U) #define LPI2C_MCFGR1_AUTOSTOP_SHIFT (8U) +/*! AUTOSTOP - Automatic STOP Generation + * 0b0..No effect + * 0b1..STOP condition is automatically generated whenever the transmit FIFO is empty and the LPI2C master is busy + */ #define LPI2C_MCFGR1_AUTOSTOP(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_AUTOSTOP_SHIFT)) & LPI2C_MCFGR1_AUTOSTOP_MASK) #define LPI2C_MCFGR1_IGNACK_MASK (0x200U) #define LPI2C_MCFGR1_IGNACK_SHIFT (9U) +/*! IGNACK - IGNACK + * 0b0..LPI2C Master will receive ACK and NACK normally + * 0b1..LPI2C Master will treat a received NACK as if it (NACK) was an ACK + */ #define LPI2C_MCFGR1_IGNACK(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_IGNACK_SHIFT)) & LPI2C_MCFGR1_IGNACK_MASK) #define LPI2C_MCFGR1_TIMECFG_MASK (0x400U) #define LPI2C_MCFGR1_TIMECFG_SHIFT (10U) +/*! TIMECFG - Timeout Configuration + * 0b0..Pin Low Timeout Flag will set if SCL is low for longer than the configured timeout + * 0b1..Pin Low Timeout Flag will set if either SCL or SDA is low for longer than the configured timeout + */ #define LPI2C_MCFGR1_TIMECFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_TIMECFG_SHIFT)) & LPI2C_MCFGR1_TIMECFG_MASK) #define LPI2C_MCFGR1_MATCFG_MASK (0x70000U) #define LPI2C_MCFGR1_MATCFG_SHIFT (16U) +/*! MATCFG - Match Configuration + * 0b000..Match is disabled + * 0b001..Reserved + * 0b010..Match is enabled (1st data word equals MATCH0 OR MATCH1) + * 0b011..Match is enabled (any data word equals MATCH0 OR MATCH1) + * 0b100..Match is enabled (1st data word equals MATCH0 AND 2nd data word equals MATCH1) + * 0b101..Match is enabled (any data word equals MATCH0 AND next data word equals MATCH1) + * 0b110..Match is enabled (1st data word AND MATCH1 equals MATCH0 AND MATCH1) + * 0b111..Match is enabled (any data word AND MATCH1 equals MATCH0 AND MATCH1) + */ #define LPI2C_MCFGR1_MATCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_MATCFG_SHIFT)) & LPI2C_MCFGR1_MATCFG_MASK) #define LPI2C_MCFGR1_PINCFG_MASK (0x7000000U) #define LPI2C_MCFGR1_PINCFG_SHIFT (24U) +/*! PINCFG - Pin Configuration + * 0b000..2-pin open drain mode + * 0b001..2-pin output only mode (ultra-fast mode) + * 0b010..2-pin push-pull mode + * 0b011..4-pin push-pull mode + * 0b100..2-pin open drain mode with separate LPI2C slave + * 0b101..2-pin output only mode (ultra-fast mode) with separate LPI2C slave + * 0b110..2-pin push-pull mode with separate LPI2C slave + * 0b111..4-pin push-pull mode (inverted outputs) + */ #define LPI2C_MCFGR1_PINCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_PINCFG_SHIFT)) & LPI2C_MCFGR1_PINCFG_MASK) +/*! @} */ /*! @name MCFGR2 - Master Configuration Register 2 */ +/*! @{ */ #define LPI2C_MCFGR2_BUSIDLE_MASK (0xFFFU) #define LPI2C_MCFGR2_BUSIDLE_SHIFT (0U) #define LPI2C_MCFGR2_BUSIDLE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_BUSIDLE_SHIFT)) & LPI2C_MCFGR2_BUSIDLE_MASK) @@ -14390,21 +22754,27 @@ typedef struct { #define LPI2C_MCFGR2_FILTSDA_MASK (0xF000000U) #define LPI2C_MCFGR2_FILTSDA_SHIFT (24U) #define LPI2C_MCFGR2_FILTSDA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_FILTSDA_SHIFT)) & LPI2C_MCFGR2_FILTSDA_MASK) +/*! @} */ /*! @name MCFGR3 - Master Configuration Register 3 */ +/*! @{ */ #define LPI2C_MCFGR3_PINLOW_MASK (0xFFF00U) #define LPI2C_MCFGR3_PINLOW_SHIFT (8U) #define LPI2C_MCFGR3_PINLOW(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR3_PINLOW_SHIFT)) & LPI2C_MCFGR3_PINLOW_MASK) +/*! @} */ /*! @name MDMR - Master Data Match Register */ +/*! @{ */ #define LPI2C_MDMR_MATCH0_MASK (0xFFU) #define LPI2C_MDMR_MATCH0_SHIFT (0U) #define LPI2C_MDMR_MATCH0(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDMR_MATCH0_SHIFT)) & LPI2C_MDMR_MATCH0_MASK) #define LPI2C_MDMR_MATCH1_MASK (0xFF0000U) #define LPI2C_MDMR_MATCH1_SHIFT (16U) #define LPI2C_MDMR_MATCH1(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDMR_MATCH1_SHIFT)) & LPI2C_MDMR_MATCH1_MASK) +/*! @} */ /*! @name MCCR0 - Master Clock Configuration Register 0 */ +/*! @{ */ #define LPI2C_MCCR0_CLKLO_MASK (0x3FU) #define LPI2C_MCCR0_CLKLO_SHIFT (0U) #define LPI2C_MCCR0_CLKLO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_CLKLO_SHIFT)) & LPI2C_MCCR0_CLKLO_MASK) @@ -14417,8 +22787,10 @@ typedef struct { #define LPI2C_MCCR0_DATAVD_MASK (0x3F000000U) #define LPI2C_MCCR0_DATAVD_SHIFT (24U) #define LPI2C_MCCR0_DATAVD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_DATAVD_SHIFT)) & LPI2C_MCCR0_DATAVD_MASK) +/*! @} */ /*! @name MCCR1 - Master Clock Configuration Register 1 */ +/*! @{ */ #define LPI2C_MCCR1_CLKLO_MASK (0x3FU) #define LPI2C_MCCR1_CLKLO_SHIFT (0U) #define LPI2C_MCCR1_CLKLO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_CLKLO_SHIFT)) & LPI2C_MCCR1_CLKLO_MASK) @@ -14431,188 +22803,412 @@ typedef struct { #define LPI2C_MCCR1_DATAVD_MASK (0x3F000000U) #define LPI2C_MCCR1_DATAVD_SHIFT (24U) #define LPI2C_MCCR1_DATAVD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_DATAVD_SHIFT)) & LPI2C_MCCR1_DATAVD_MASK) +/*! @} */ /*! @name MFCR - Master FIFO Control Register */ +/*! @{ */ #define LPI2C_MFCR_TXWATER_MASK (0x3U) #define LPI2C_MFCR_TXWATER_SHIFT (0U) #define LPI2C_MFCR_TXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFCR_TXWATER_SHIFT)) & LPI2C_MFCR_TXWATER_MASK) #define LPI2C_MFCR_RXWATER_MASK (0x30000U) #define LPI2C_MFCR_RXWATER_SHIFT (16U) #define LPI2C_MFCR_RXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFCR_RXWATER_SHIFT)) & LPI2C_MFCR_RXWATER_MASK) +/*! @} */ /*! @name MFSR - Master FIFO Status Register */ +/*! @{ */ #define LPI2C_MFSR_TXCOUNT_MASK (0x7U) #define LPI2C_MFSR_TXCOUNT_SHIFT (0U) #define LPI2C_MFSR_TXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFSR_TXCOUNT_SHIFT)) & LPI2C_MFSR_TXCOUNT_MASK) #define LPI2C_MFSR_RXCOUNT_MASK (0x70000U) #define LPI2C_MFSR_RXCOUNT_SHIFT (16U) #define LPI2C_MFSR_RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFSR_RXCOUNT_SHIFT)) & LPI2C_MFSR_RXCOUNT_MASK) +/*! @} */ /*! @name MTDR - Master Transmit Data Register */ +/*! @{ */ #define LPI2C_MTDR_DATA_MASK (0xFFU) #define LPI2C_MTDR_DATA_SHIFT (0U) #define LPI2C_MTDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MTDR_DATA_SHIFT)) & LPI2C_MTDR_DATA_MASK) #define LPI2C_MTDR_CMD_MASK (0x700U) #define LPI2C_MTDR_CMD_SHIFT (8U) +/*! CMD - Command Data + * 0b000..Transmit DATA[7:0] + * 0b001..Receive (DATA[7:0] + 1) bytes + * 0b010..Generate STOP condition + * 0b011..Receive and discard (DATA[7:0] + 1) bytes + * 0b100..Generate (repeated) START and transmit address in DATA[7:0] + * 0b101..Generate (repeated) START and transmit address in DATA[7:0]. This transfer expects a NACK to be returned. + * 0b110..Generate (repeated) START and transmit address in DATA[7:0] using high speed mode + * 0b111..Generate (repeated) START and transmit address in DATA[7:0] using high speed mode. This transfer expects a NACK to be returned. + */ #define LPI2C_MTDR_CMD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MTDR_CMD_SHIFT)) & LPI2C_MTDR_CMD_MASK) +/*! @} */ /*! @name MRDR - Master Receive Data Register */ +/*! @{ */ #define LPI2C_MRDR_DATA_MASK (0xFFU) #define LPI2C_MRDR_DATA_SHIFT (0U) #define LPI2C_MRDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MRDR_DATA_SHIFT)) & LPI2C_MRDR_DATA_MASK) #define LPI2C_MRDR_RXEMPTY_MASK (0x4000U) #define LPI2C_MRDR_RXEMPTY_SHIFT (14U) +/*! RXEMPTY - RX Empty + * 0b0..Receive FIFO is not empty + * 0b1..Receive FIFO is empty + */ #define LPI2C_MRDR_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MRDR_RXEMPTY_SHIFT)) & LPI2C_MRDR_RXEMPTY_MASK) +/*! @} */ /*! @name SCR - Slave Control Register */ +/*! @{ */ #define LPI2C_SCR_SEN_MASK (0x1U) #define LPI2C_SCR_SEN_SHIFT (0U) +/*! SEN - Slave Enable + * 0b0..I2C Slave mode is disabled + * 0b1..I2C Slave mode is enabled + */ #define LPI2C_SCR_SEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_SEN_SHIFT)) & LPI2C_SCR_SEN_MASK) #define LPI2C_SCR_RST_MASK (0x2U) #define LPI2C_SCR_RST_SHIFT (1U) +/*! RST - Software Reset + * 0b0..Slave mode logic is not reset + * 0b1..Slave mode logic is reset + */ #define LPI2C_SCR_RST(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RST_SHIFT)) & LPI2C_SCR_RST_MASK) #define LPI2C_SCR_FILTEN_MASK (0x10U) #define LPI2C_SCR_FILTEN_SHIFT (4U) +/*! FILTEN - Filter Enable + * 0b0..Disable digital filter and output delay counter for slave mode + * 0b1..Enable digital filter and output delay counter for slave mode + */ #define LPI2C_SCR_FILTEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_FILTEN_SHIFT)) & LPI2C_SCR_FILTEN_MASK) #define LPI2C_SCR_FILTDZ_MASK (0x20U) #define LPI2C_SCR_FILTDZ_SHIFT (5U) +/*! FILTDZ - Filter Doze Enable + * 0b0..Filter remains enabled in Doze mode + * 0b1..Filter is disabled in Doze mode + */ #define LPI2C_SCR_FILTDZ(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_FILTDZ_SHIFT)) & LPI2C_SCR_FILTDZ_MASK) #define LPI2C_SCR_RTF_MASK (0x100U) #define LPI2C_SCR_RTF_SHIFT (8U) +/*! RTF - Reset Transmit FIFO + * 0b0..No effect + * 0b1..Transmit Data Register is now empty + */ #define LPI2C_SCR_RTF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RTF_SHIFT)) & LPI2C_SCR_RTF_MASK) #define LPI2C_SCR_RRF_MASK (0x200U) #define LPI2C_SCR_RRF_SHIFT (9U) +/*! RRF - Reset Receive FIFO + * 0b0..No effect + * 0b1..Receive Data Register is now empty + */ #define LPI2C_SCR_RRF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RRF_SHIFT)) & LPI2C_SCR_RRF_MASK) +/*! @} */ /*! @name SSR - Slave Status Register */ +/*! @{ */ #define LPI2C_SSR_TDF_MASK (0x1U) #define LPI2C_SSR_TDF_SHIFT (0U) +/*! TDF - Transmit Data Flag + * 0b0..Transmit data not requested + * 0b1..Transmit data is requested + */ #define LPI2C_SSR_TDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_TDF_SHIFT)) & LPI2C_SSR_TDF_MASK) #define LPI2C_SSR_RDF_MASK (0x2U) #define LPI2C_SSR_RDF_SHIFT (1U) +/*! RDF - Receive Data Flag + * 0b0..Receive data is not ready + * 0b1..Receive data is ready + */ #define LPI2C_SSR_RDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_RDF_SHIFT)) & LPI2C_SSR_RDF_MASK) #define LPI2C_SSR_AVF_MASK (0x4U) #define LPI2C_SSR_AVF_SHIFT (2U) +/*! AVF - Address Valid Flag + * 0b0..Address Status Register is not valid + * 0b1..Address Status Register is valid + */ #define LPI2C_SSR_AVF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AVF_SHIFT)) & LPI2C_SSR_AVF_MASK) #define LPI2C_SSR_TAF_MASK (0x8U) #define LPI2C_SSR_TAF_SHIFT (3U) +/*! TAF - Transmit ACK Flag + * 0b0..Transmit ACK/NACK is not required + * 0b1..Transmit ACK/NACK is required + */ #define LPI2C_SSR_TAF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_TAF_SHIFT)) & LPI2C_SSR_TAF_MASK) #define LPI2C_SSR_RSF_MASK (0x100U) #define LPI2C_SSR_RSF_SHIFT (8U) +/*! RSF - Repeated Start Flag + * 0b0..Slave has not detected a Repeated START condition + * 0b1..Slave has detected a Repeated START condition + */ #define LPI2C_SSR_RSF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_RSF_SHIFT)) & LPI2C_SSR_RSF_MASK) #define LPI2C_SSR_SDF_MASK (0x200U) #define LPI2C_SSR_SDF_SHIFT (9U) +/*! SDF - STOP Detect Flag + * 0b0..Slave has not detected a STOP condition + * 0b1..Slave has detected a STOP condition + */ #define LPI2C_SSR_SDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SDF_SHIFT)) & LPI2C_SSR_SDF_MASK) #define LPI2C_SSR_BEF_MASK (0x400U) #define LPI2C_SSR_BEF_SHIFT (10U) +/*! BEF - Bit Error Flag + * 0b0..Slave has not detected a bit error + * 0b1..Slave has detected a bit error + */ #define LPI2C_SSR_BEF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_BEF_SHIFT)) & LPI2C_SSR_BEF_MASK) #define LPI2C_SSR_FEF_MASK (0x800U) #define LPI2C_SSR_FEF_SHIFT (11U) +/*! FEF - FIFO Error Flag + * 0b0..FIFO underflow or overflow was not detected + * 0b1..FIFO underflow or overflow was detected + */ #define LPI2C_SSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_FEF_SHIFT)) & LPI2C_SSR_FEF_MASK) #define LPI2C_SSR_AM0F_MASK (0x1000U) #define LPI2C_SSR_AM0F_SHIFT (12U) +/*! AM0F - Address Match 0 Flag + * 0b0..Have not received an ADDR0 matching address + * 0b1..Have received an ADDR0 matching address + */ #define LPI2C_SSR_AM0F(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AM0F_SHIFT)) & LPI2C_SSR_AM0F_MASK) #define LPI2C_SSR_AM1F_MASK (0x2000U) #define LPI2C_SSR_AM1F_SHIFT (13U) +/*! AM1F - Address Match 1 Flag + * 0b0..Have not received an ADDR1 or ADDR0/ADDR1 range matching address + * 0b1..Have received an ADDR1 or ADDR0/ADDR1 range matching address + */ #define LPI2C_SSR_AM1F(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AM1F_SHIFT)) & LPI2C_SSR_AM1F_MASK) #define LPI2C_SSR_GCF_MASK (0x4000U) #define LPI2C_SSR_GCF_SHIFT (14U) +/*! GCF - General Call Flag + * 0b0..Slave has not detected the General Call Address or the General Call Address is disabled + * 0b1..Slave has detected the General Call Address + */ #define LPI2C_SSR_GCF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_GCF_SHIFT)) & LPI2C_SSR_GCF_MASK) #define LPI2C_SSR_SARF_MASK (0x8000U) #define LPI2C_SSR_SARF_SHIFT (15U) +/*! SARF - SMBus Alert Response Flag + * 0b0..SMBus Alert Response is disabled or not detected + * 0b1..SMBus Alert Response is enabled and detected + */ #define LPI2C_SSR_SARF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SARF_SHIFT)) & LPI2C_SSR_SARF_MASK) #define LPI2C_SSR_SBF_MASK (0x1000000U) #define LPI2C_SSR_SBF_SHIFT (24U) +/*! SBF - Slave Busy Flag + * 0b0..I2C Slave is idle + * 0b1..I2C Slave is busy + */ #define LPI2C_SSR_SBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SBF_SHIFT)) & LPI2C_SSR_SBF_MASK) #define LPI2C_SSR_BBF_MASK (0x2000000U) #define LPI2C_SSR_BBF_SHIFT (25U) +/*! BBF - Bus Busy Flag + * 0b0..I2C Bus is idle + * 0b1..I2C Bus is busy + */ #define LPI2C_SSR_BBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_BBF_SHIFT)) & LPI2C_SSR_BBF_MASK) +/*! @} */ /*! @name SIER - Slave Interrupt Enable Register */ +/*! @{ */ #define LPI2C_SIER_TDIE_MASK (0x1U) #define LPI2C_SIER_TDIE_SHIFT (0U) +/*! TDIE - Transmit Data Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ #define LPI2C_SIER_TDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_TDIE_SHIFT)) & LPI2C_SIER_TDIE_MASK) #define LPI2C_SIER_RDIE_MASK (0x2U) #define LPI2C_SIER_RDIE_SHIFT (1U) +/*! RDIE - Receive Data Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ #define LPI2C_SIER_RDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_RDIE_SHIFT)) & LPI2C_SIER_RDIE_MASK) #define LPI2C_SIER_AVIE_MASK (0x4U) #define LPI2C_SIER_AVIE_SHIFT (2U) +/*! AVIE - Address Valid Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ #define LPI2C_SIER_AVIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AVIE_SHIFT)) & LPI2C_SIER_AVIE_MASK) #define LPI2C_SIER_TAIE_MASK (0x8U) #define LPI2C_SIER_TAIE_SHIFT (3U) +/*! TAIE - Transmit ACK Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ #define LPI2C_SIER_TAIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_TAIE_SHIFT)) & LPI2C_SIER_TAIE_MASK) #define LPI2C_SIER_RSIE_MASK (0x100U) #define LPI2C_SIER_RSIE_SHIFT (8U) +/*! RSIE - Repeated Start Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ #define LPI2C_SIER_RSIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_RSIE_SHIFT)) & LPI2C_SIER_RSIE_MASK) #define LPI2C_SIER_SDIE_MASK (0x200U) #define LPI2C_SIER_SDIE_SHIFT (9U) +/*! SDIE - STOP Detect Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ #define LPI2C_SIER_SDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_SDIE_SHIFT)) & LPI2C_SIER_SDIE_MASK) #define LPI2C_SIER_BEIE_MASK (0x400U) #define LPI2C_SIER_BEIE_SHIFT (10U) +/*! BEIE - Bit Error Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ #define LPI2C_SIER_BEIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_BEIE_SHIFT)) & LPI2C_SIER_BEIE_MASK) #define LPI2C_SIER_FEIE_MASK (0x800U) #define LPI2C_SIER_FEIE_SHIFT (11U) +/*! FEIE - FIFO Error Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ #define LPI2C_SIER_FEIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_FEIE_SHIFT)) & LPI2C_SIER_FEIE_MASK) #define LPI2C_SIER_AM0IE_MASK (0x1000U) #define LPI2C_SIER_AM0IE_SHIFT (12U) +/*! AM0IE - Address Match 0 Interrupt Enable + * 0b0..Enabled + * 0b1..Disabled + */ #define LPI2C_SIER_AM0IE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AM0IE_SHIFT)) & LPI2C_SIER_AM0IE_MASK) #define LPI2C_SIER_AM1F_MASK (0x2000U) #define LPI2C_SIER_AM1F_SHIFT (13U) +/*! AM1F - Address Match 1 Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ #define LPI2C_SIER_AM1F(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AM1F_SHIFT)) & LPI2C_SIER_AM1F_MASK) #define LPI2C_SIER_GCIE_MASK (0x4000U) #define LPI2C_SIER_GCIE_SHIFT (14U) +/*! GCIE - General Call Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ #define LPI2C_SIER_GCIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_GCIE_SHIFT)) & LPI2C_SIER_GCIE_MASK) #define LPI2C_SIER_SARIE_MASK (0x8000U) #define LPI2C_SIER_SARIE_SHIFT (15U) +/*! SARIE - SMBus Alert Response Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ #define LPI2C_SIER_SARIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_SARIE_SHIFT)) & LPI2C_SIER_SARIE_MASK) +/*! @} */ /*! @name SDER - Slave DMA Enable Register */ +/*! @{ */ #define LPI2C_SDER_TDDE_MASK (0x1U) #define LPI2C_SDER_TDDE_SHIFT (0U) +/*! TDDE - Transmit Data DMA Enable + * 0b0..DMA request is disabled + * 0b1..DMA request is enabled + */ #define LPI2C_SDER_TDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_TDDE_SHIFT)) & LPI2C_SDER_TDDE_MASK) #define LPI2C_SDER_RDDE_MASK (0x2U) #define LPI2C_SDER_RDDE_SHIFT (1U) +/*! RDDE - Receive Data DMA Enable + * 0b0..DMA request is disabled + * 0b1..DMA request is enabled + */ #define LPI2C_SDER_RDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_RDDE_SHIFT)) & LPI2C_SDER_RDDE_MASK) #define LPI2C_SDER_AVDE_MASK (0x4U) #define LPI2C_SDER_AVDE_SHIFT (2U) +/*! AVDE - Address Valid DMA Enable + * 0b0..DMA request is disabled + * 0b1..DMA request is enabled + */ #define LPI2C_SDER_AVDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_AVDE_SHIFT)) & LPI2C_SDER_AVDE_MASK) +/*! @} */ /*! @name SCFGR1 - Slave Configuration Register 1 */ +/*! @{ */ #define LPI2C_SCFGR1_ADRSTALL_MASK (0x1U) #define LPI2C_SCFGR1_ADRSTALL_SHIFT (0U) +/*! ADRSTALL - Address SCL Stall + * 0b0..Clock stretching is disabled + * 0b1..Clock stretching is enabled + */ #define LPI2C_SCFGR1_ADRSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ADRSTALL_SHIFT)) & LPI2C_SCFGR1_ADRSTALL_MASK) #define LPI2C_SCFGR1_RXSTALL_MASK (0x2U) #define LPI2C_SCFGR1_RXSTALL_SHIFT (1U) +/*! RXSTALL - RX SCL Stall + * 0b0..Clock stretching is disabled + * 0b1..Clock stretching is enabled + */ #define LPI2C_SCFGR1_RXSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_RXSTALL_SHIFT)) & LPI2C_SCFGR1_RXSTALL_MASK) #define LPI2C_SCFGR1_TXDSTALL_MASK (0x4U) #define LPI2C_SCFGR1_TXDSTALL_SHIFT (2U) +/*! TXDSTALL - TX Data SCL Stall + * 0b0..Clock stretching is disabled + * 0b1..Clock stretching is enabled + */ #define LPI2C_SCFGR1_TXDSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_TXDSTALL_SHIFT)) & LPI2C_SCFGR1_TXDSTALL_MASK) #define LPI2C_SCFGR1_ACKSTALL_MASK (0x8U) #define LPI2C_SCFGR1_ACKSTALL_SHIFT (3U) +/*! ACKSTALL - ACK SCL Stall + * 0b0..Clock stretching is disabled + * 0b1..Clock stretching is enabled + */ #define LPI2C_SCFGR1_ACKSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ACKSTALL_SHIFT)) & LPI2C_SCFGR1_ACKSTALL_MASK) #define LPI2C_SCFGR1_GCEN_MASK (0x100U) #define LPI2C_SCFGR1_GCEN_SHIFT (8U) +/*! GCEN - General Call Enable + * 0b0..General Call address is disabled + * 0b1..General Call address is enabled + */ #define LPI2C_SCFGR1_GCEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_GCEN_SHIFT)) & LPI2C_SCFGR1_GCEN_MASK) #define LPI2C_SCFGR1_SAEN_MASK (0x200U) #define LPI2C_SCFGR1_SAEN_SHIFT (9U) +/*! SAEN - SMBus Alert Enable + * 0b0..Disables match on SMBus Alert + * 0b1..Enables match on SMBus Alert + */ #define LPI2C_SCFGR1_SAEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_SAEN_SHIFT)) & LPI2C_SCFGR1_SAEN_MASK) #define LPI2C_SCFGR1_TXCFG_MASK (0x400U) #define LPI2C_SCFGR1_TXCFG_SHIFT (10U) +/*! TXCFG - Transmit Flag Configuration + * 0b0..Transmit Data Flag will only assert during a slave-transmit transfer when the Transmit Data register is empty + * 0b1..Transmit Data Flag will assert whenever the Transmit Data register is empty + */ #define LPI2C_SCFGR1_TXCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_TXCFG_SHIFT)) & LPI2C_SCFGR1_TXCFG_MASK) #define LPI2C_SCFGR1_RXCFG_MASK (0x800U) #define LPI2C_SCFGR1_RXCFG_SHIFT (11U) +/*! RXCFG - Receive Data Configuration + * 0b0..Reading the Receive Data register will return received data and clear the Receive Data flag (MSR[RDF]). + * 0b1..Reading the Receive Data register when the Address Valid flag (SSR[AVF])is set, will return the Address Status register and clear the Address Valid flag. Reading the Receive Data register when the Address Valid flag is clear, will return received data and clear the Receive Data flag (MSR[RDF]). + */ #define LPI2C_SCFGR1_RXCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_RXCFG_SHIFT)) & LPI2C_SCFGR1_RXCFG_MASK) #define LPI2C_SCFGR1_IGNACK_MASK (0x1000U) #define LPI2C_SCFGR1_IGNACK_SHIFT (12U) +/*! IGNACK - Ignore NACK + * 0b0..Slave will end transfer when NACK is detected + * 0b1..Slave will not end transfer when NACK detected + */ #define LPI2C_SCFGR1_IGNACK(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_IGNACK_SHIFT)) & LPI2C_SCFGR1_IGNACK_MASK) #define LPI2C_SCFGR1_HSMEN_MASK (0x2000U) #define LPI2C_SCFGR1_HSMEN_SHIFT (13U) +/*! HSMEN - High Speed Mode Enable + * 0b0..Disables detection of HS-mode master code + * 0b1..Enables detection of HS-mode master code + */ #define LPI2C_SCFGR1_HSMEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_HSMEN_SHIFT)) & LPI2C_SCFGR1_HSMEN_MASK) #define LPI2C_SCFGR1_ADDRCFG_MASK (0x70000U) #define LPI2C_SCFGR1_ADDRCFG_SHIFT (16U) +/*! ADDRCFG - Address Configuration + * 0b000..Address match 0 (7-bit) + * 0b001..Address match 0 (10-bit) + * 0b010..Address match 0 (7-bit) or Address match 1 (7-bit) + * 0b011..Address match 0 (10-bit) or Address match 1 (10-bit) + * 0b100..Address match 0 (7-bit) or Address match 1 (10-bit) + * 0b101..Address match 0 (10-bit) or Address match 1 (7-bit) + * 0b110..From Address match 0 (7-bit) to Address match 1 (7-bit) + * 0b111..From Address match 0 (10-bit) to Address match 1 (10-bit) + */ #define LPI2C_SCFGR1_ADDRCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ADDRCFG_SHIFT)) & LPI2C_SCFGR1_ADDRCFG_MASK) +/*! @} */ /*! @name SCFGR2 - Slave Configuration Register 2 */ +/*! @{ */ #define LPI2C_SCFGR2_CLKHOLD_MASK (0xFU) #define LPI2C_SCFGR2_CLKHOLD_SHIFT (0U) #define LPI2C_SCFGR2_CLKHOLD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_CLKHOLD_SHIFT)) & LPI2C_SCFGR2_CLKHOLD_MASK) @@ -14625,43 +23221,70 @@ typedef struct { #define LPI2C_SCFGR2_FILTSDA_MASK (0xF000000U) #define LPI2C_SCFGR2_FILTSDA_SHIFT (24U) #define LPI2C_SCFGR2_FILTSDA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_FILTSDA_SHIFT)) & LPI2C_SCFGR2_FILTSDA_MASK) +/*! @} */ /*! @name SAMR - Slave Address Match Register */ +/*! @{ */ #define LPI2C_SAMR_ADDR0_MASK (0x7FEU) #define LPI2C_SAMR_ADDR0_SHIFT (1U) #define LPI2C_SAMR_ADDR0(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SAMR_ADDR0_SHIFT)) & LPI2C_SAMR_ADDR0_MASK) #define LPI2C_SAMR_ADDR1_MASK (0x7FE0000U) #define LPI2C_SAMR_ADDR1_SHIFT (17U) #define LPI2C_SAMR_ADDR1(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SAMR_ADDR1_SHIFT)) & LPI2C_SAMR_ADDR1_MASK) +/*! @} */ /*! @name SASR - Slave Address Status Register */ +/*! @{ */ #define LPI2C_SASR_RADDR_MASK (0x7FFU) #define LPI2C_SASR_RADDR_SHIFT (0U) #define LPI2C_SASR_RADDR(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SASR_RADDR_SHIFT)) & LPI2C_SASR_RADDR_MASK) #define LPI2C_SASR_ANV_MASK (0x4000U) #define LPI2C_SASR_ANV_SHIFT (14U) +/*! ANV - Address Not Valid + * 0b0..Received Address (RADDR) is valid + * 0b1..Received Address (RADDR) is not valid + */ #define LPI2C_SASR_ANV(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SASR_ANV_SHIFT)) & LPI2C_SASR_ANV_MASK) +/*! @} */ /*! @name STAR - Slave Transmit ACK Register */ +/*! @{ */ #define LPI2C_STAR_TXNACK_MASK (0x1U) #define LPI2C_STAR_TXNACK_SHIFT (0U) +/*! TXNACK - Transmit NACK + * 0b0..Write a Transmit ACK for each received word + * 0b1..Write a Transmit NACK for each received word + */ #define LPI2C_STAR_TXNACK(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_STAR_TXNACK_SHIFT)) & LPI2C_STAR_TXNACK_MASK) +/*! @} */ /*! @name STDR - Slave Transmit Data Register */ +/*! @{ */ #define LPI2C_STDR_DATA_MASK (0xFFU) #define LPI2C_STDR_DATA_SHIFT (0U) #define LPI2C_STDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_STDR_DATA_SHIFT)) & LPI2C_STDR_DATA_MASK) +/*! @} */ /*! @name SRDR - Slave Receive Data Register */ +/*! @{ */ #define LPI2C_SRDR_DATA_MASK (0xFFU) #define LPI2C_SRDR_DATA_SHIFT (0U) #define LPI2C_SRDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_DATA_SHIFT)) & LPI2C_SRDR_DATA_MASK) #define LPI2C_SRDR_RXEMPTY_MASK (0x4000U) #define LPI2C_SRDR_RXEMPTY_SHIFT (14U) +/*! RXEMPTY - RX Empty + * 0b0..The Receive Data Register is not empty + * 0b1..The Receive Data Register is empty + */ #define LPI2C_SRDR_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_RXEMPTY_SHIFT)) & LPI2C_SRDR_RXEMPTY_MASK) #define LPI2C_SRDR_SOF_MASK (0x8000U) #define LPI2C_SRDR_SOF_SHIFT (15U) +/*! SOF - Start Of Frame + * 0b0..Indicates this is not the first data word since a (repeated) START or STOP condition + * 0b1..Indicates this is the first data word since a (repeated) START or STOP condition + */ #define LPI2C_SRDR_SOF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_SOF_SHIFT)) & LPI2C_SRDR_SOF_MASK) +/*! @} */ /*! @@ -14743,8 +23366,12 @@ typedef struct { */ /*! @name VERID - Version ID Register */ +/*! @{ */ #define LPSPI_VERID_FEATURE_MASK (0xFFFFU) #define LPSPI_VERID_FEATURE_SHIFT (0U) +/*! FEATURE - Module Identification Number + * 0b0000000000000100..Standard feature set supporting a 32-bit shift register. + */ #define LPSPI_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_VERID_FEATURE_SHIFT)) & LPSPI_VERID_FEATURE_MASK) #define LPSPI_VERID_MINOR_MASK (0xFF0000U) #define LPSPI_VERID_MINOR_SHIFT (16U) @@ -14752,8 +23379,10 @@ typedef struct { #define LPSPI_VERID_MAJOR_MASK (0xFF000000U) #define LPSPI_VERID_MAJOR_SHIFT (24U) #define LPSPI_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_VERID_MAJOR_SHIFT)) & LPSPI_VERID_MAJOR_MASK) +/*! @} */ /*! @name PARAM - Parameter Register */ +/*! @{ */ #define LPSPI_PARAM_TXFIFO_MASK (0xFFU) #define LPSPI_PARAM_TXFIFO_SHIFT (0U) #define LPSPI_PARAM_TXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_PARAM_TXFIFO_SHIFT)) & LPSPI_PARAM_TXFIFO_MASK) @@ -14763,147 +23392,329 @@ typedef struct { #define LPSPI_PARAM_PCSNUM_MASK (0xFF0000U) #define LPSPI_PARAM_PCSNUM_SHIFT (16U) #define LPSPI_PARAM_PCSNUM(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_PARAM_PCSNUM_SHIFT)) & LPSPI_PARAM_PCSNUM_MASK) +/*! @} */ /*! @name CR - Control Register */ +/*! @{ */ #define LPSPI_CR_MEN_MASK (0x1U) #define LPSPI_CR_MEN_SHIFT (0U) +/*! MEN - Module Enable + * 0b0..Module is disabled + * 0b1..Module is enabled + */ #define LPSPI_CR_MEN(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_MEN_SHIFT)) & LPSPI_CR_MEN_MASK) #define LPSPI_CR_RST_MASK (0x2U) #define LPSPI_CR_RST_SHIFT (1U) +/*! RST - Software Reset + * 0b0..Module is not reset + * 0b1..Module is reset + */ #define LPSPI_CR_RST(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_RST_SHIFT)) & LPSPI_CR_RST_MASK) #define LPSPI_CR_DOZEN_MASK (0x4U) #define LPSPI_CR_DOZEN_SHIFT (2U) +/*! DOZEN - Doze mode enable + * 0b0..Module is enabled in Doze mode + * 0b1..Module is disabled in Doze mode + */ #define LPSPI_CR_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_DOZEN_SHIFT)) & LPSPI_CR_DOZEN_MASK) #define LPSPI_CR_DBGEN_MASK (0x8U) #define LPSPI_CR_DBGEN_SHIFT (3U) +/*! DBGEN - Debug Enable + * 0b0..Module is disabled in debug mode + * 0b1..Module is enabled in debug mode + */ #define LPSPI_CR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_DBGEN_SHIFT)) & LPSPI_CR_DBGEN_MASK) #define LPSPI_CR_RTF_MASK (0x100U) #define LPSPI_CR_RTF_SHIFT (8U) +/*! RTF - Reset Transmit FIFO + * 0b0..No effect + * 0b1..Transmit FIFO is reset + */ #define LPSPI_CR_RTF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_RTF_SHIFT)) & LPSPI_CR_RTF_MASK) #define LPSPI_CR_RRF_MASK (0x200U) #define LPSPI_CR_RRF_SHIFT (9U) +/*! RRF - Reset Receive FIFO + * 0b0..No effect + * 0b1..Receive FIFO is reset + */ #define LPSPI_CR_RRF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_RRF_SHIFT)) & LPSPI_CR_RRF_MASK) +/*! @} */ /*! @name SR - Status Register */ +/*! @{ */ #define LPSPI_SR_TDF_MASK (0x1U) #define LPSPI_SR_TDF_SHIFT (0U) +/*! TDF - Transmit Data Flag + * 0b0..Transmit data not requested + * 0b1..Transmit data is requested + */ #define LPSPI_SR_TDF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_TDF_SHIFT)) & LPSPI_SR_TDF_MASK) #define LPSPI_SR_RDF_MASK (0x2U) #define LPSPI_SR_RDF_SHIFT (1U) +/*! RDF - Receive Data Flag + * 0b0..Receive Data is not ready + * 0b1..Receive data is ready + */ #define LPSPI_SR_RDF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_RDF_SHIFT)) & LPSPI_SR_RDF_MASK) #define LPSPI_SR_WCF_MASK (0x100U) #define LPSPI_SR_WCF_SHIFT (8U) +/*! WCF - Word Complete Flag + * 0b0..Transfer of a received word has not yet completed + * 0b1..Transfer of a received word has completed + */ #define LPSPI_SR_WCF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_WCF_SHIFT)) & LPSPI_SR_WCF_MASK) #define LPSPI_SR_FCF_MASK (0x200U) #define LPSPI_SR_FCF_SHIFT (9U) +/*! FCF - Frame Complete Flag + * 0b0..Frame transfer has not completed + * 0b1..Frame transfer has completed + */ #define LPSPI_SR_FCF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_FCF_SHIFT)) & LPSPI_SR_FCF_MASK) #define LPSPI_SR_TCF_MASK (0x400U) #define LPSPI_SR_TCF_SHIFT (10U) +/*! TCF - Transfer Complete Flag + * 0b0..All transfers have not completed + * 0b1..All transfers have completed + */ #define LPSPI_SR_TCF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_TCF_SHIFT)) & LPSPI_SR_TCF_MASK) #define LPSPI_SR_TEF_MASK (0x800U) #define LPSPI_SR_TEF_SHIFT (11U) +/*! TEF - Transmit Error Flag + * 0b0..Transmit FIFO underrun has not occurred + * 0b1..Transmit FIFO underrun has occurred + */ #define LPSPI_SR_TEF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_TEF_SHIFT)) & LPSPI_SR_TEF_MASK) #define LPSPI_SR_REF_MASK (0x1000U) #define LPSPI_SR_REF_SHIFT (12U) +/*! REF - Receive Error Flag + * 0b0..Receive FIFO has not overflowed + * 0b1..Receive FIFO has overflowed + */ #define LPSPI_SR_REF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_REF_SHIFT)) & LPSPI_SR_REF_MASK) #define LPSPI_SR_DMF_MASK (0x2000U) #define LPSPI_SR_DMF_SHIFT (13U) +/*! DMF - Data Match Flag + * 0b0..Have not received matching data + * 0b1..Have received matching data + */ #define LPSPI_SR_DMF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_DMF_SHIFT)) & LPSPI_SR_DMF_MASK) #define LPSPI_SR_MBF_MASK (0x1000000U) #define LPSPI_SR_MBF_SHIFT (24U) +/*! MBF - Module Busy Flag + * 0b0..LPSPI is idle + * 0b1..LPSPI is busy + */ #define LPSPI_SR_MBF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_MBF_SHIFT)) & LPSPI_SR_MBF_MASK) +/*! @} */ /*! @name IER - Interrupt Enable Register */ +/*! @{ */ #define LPSPI_IER_TDIE_MASK (0x1U) #define LPSPI_IER_TDIE_SHIFT (0U) +/*! TDIE - Transmit Data Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ #define LPSPI_IER_TDIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_TDIE_SHIFT)) & LPSPI_IER_TDIE_MASK) #define LPSPI_IER_RDIE_MASK (0x2U) #define LPSPI_IER_RDIE_SHIFT (1U) +/*! RDIE - Receive Data Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ #define LPSPI_IER_RDIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_RDIE_SHIFT)) & LPSPI_IER_RDIE_MASK) #define LPSPI_IER_WCIE_MASK (0x100U) #define LPSPI_IER_WCIE_SHIFT (8U) +/*! WCIE - Word Complete Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ #define LPSPI_IER_WCIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_WCIE_SHIFT)) & LPSPI_IER_WCIE_MASK) #define LPSPI_IER_FCIE_MASK (0x200U) #define LPSPI_IER_FCIE_SHIFT (9U) +/*! FCIE - Frame Complete Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ #define LPSPI_IER_FCIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_FCIE_SHIFT)) & LPSPI_IER_FCIE_MASK) #define LPSPI_IER_TCIE_MASK (0x400U) #define LPSPI_IER_TCIE_SHIFT (10U) +/*! TCIE - Transfer Complete Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ #define LPSPI_IER_TCIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_TCIE_SHIFT)) & LPSPI_IER_TCIE_MASK) #define LPSPI_IER_TEIE_MASK (0x800U) #define LPSPI_IER_TEIE_SHIFT (11U) +/*! TEIE - Transmit Error Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ #define LPSPI_IER_TEIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_TEIE_SHIFT)) & LPSPI_IER_TEIE_MASK) #define LPSPI_IER_REIE_MASK (0x1000U) #define LPSPI_IER_REIE_SHIFT (12U) +/*! REIE - Receive Error Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ #define LPSPI_IER_REIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_REIE_SHIFT)) & LPSPI_IER_REIE_MASK) #define LPSPI_IER_DMIE_MASK (0x2000U) #define LPSPI_IER_DMIE_SHIFT (13U) +/*! DMIE - Data Match Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ #define LPSPI_IER_DMIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_DMIE_SHIFT)) & LPSPI_IER_DMIE_MASK) +/*! @} */ /*! @name DER - DMA Enable Register */ +/*! @{ */ #define LPSPI_DER_TDDE_MASK (0x1U) #define LPSPI_DER_TDDE_SHIFT (0U) +/*! TDDE - Transmit Data DMA Enable + * 0b0..DMA request is disabled + * 0b1..DMA request is enabled + */ #define LPSPI_DER_TDDE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_DER_TDDE_SHIFT)) & LPSPI_DER_TDDE_MASK) #define LPSPI_DER_RDDE_MASK (0x2U) #define LPSPI_DER_RDDE_SHIFT (1U) +/*! RDDE - Receive Data DMA Enable + * 0b0..DMA request is disabled + * 0b1..DMA request is enabled + */ #define LPSPI_DER_RDDE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_DER_RDDE_SHIFT)) & LPSPI_DER_RDDE_MASK) +/*! @} */ /*! @name CFGR0 - Configuration Register 0 */ +/*! @{ */ #define LPSPI_CFGR0_HREN_MASK (0x1U) #define LPSPI_CFGR0_HREN_SHIFT (0U) +/*! HREN - Host Request Enable + * 0b0..Host request is disabled + * 0b1..Host request is enabled + */ #define LPSPI_CFGR0_HREN(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_HREN_SHIFT)) & LPSPI_CFGR0_HREN_MASK) #define LPSPI_CFGR0_HRPOL_MASK (0x2U) #define LPSPI_CFGR0_HRPOL_SHIFT (1U) +/*! HRPOL - Host Request Polarity + * 0b0..Active low + * 0b1..Active high + */ #define LPSPI_CFGR0_HRPOL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_HRPOL_SHIFT)) & LPSPI_CFGR0_HRPOL_MASK) #define LPSPI_CFGR0_HRSEL_MASK (0x4U) #define LPSPI_CFGR0_HRSEL_SHIFT (2U) +/*! HRSEL - Host Request Select + * 0b0..Host request input is the LPSPI_HREQ pin + * 0b1..Host request input is the input trigger + */ #define LPSPI_CFGR0_HRSEL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_HRSEL_SHIFT)) & LPSPI_CFGR0_HRSEL_MASK) #define LPSPI_CFGR0_CIRFIFO_MASK (0x100U) #define LPSPI_CFGR0_CIRFIFO_SHIFT (8U) +/*! CIRFIFO - Circular FIFO Enable + * 0b0..Circular FIFO is disabled + * 0b1..Circular FIFO is enabled + */ #define LPSPI_CFGR0_CIRFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_CIRFIFO_SHIFT)) & LPSPI_CFGR0_CIRFIFO_MASK) #define LPSPI_CFGR0_RDMO_MASK (0x200U) #define LPSPI_CFGR0_RDMO_SHIFT (9U) +/*! RDMO - Receive Data Match Only + * 0b0..Received data is stored in the receive FIFO as in normal operations + * 0b1..Received data is discarded unless the Data Match Flag (DMF) is set + */ #define LPSPI_CFGR0_RDMO(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_RDMO_SHIFT)) & LPSPI_CFGR0_RDMO_MASK) +/*! @} */ /*! @name CFGR1 - Configuration Register 1 */ +/*! @{ */ #define LPSPI_CFGR1_MASTER_MASK (0x1U) #define LPSPI_CFGR1_MASTER_SHIFT (0U) +/*! MASTER - Master Mode + * 0b0..Slave mode + * 0b1..Master mode + */ #define LPSPI_CFGR1_MASTER(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_MASTER_SHIFT)) & LPSPI_CFGR1_MASTER_MASK) #define LPSPI_CFGR1_SAMPLE_MASK (0x2U) #define LPSPI_CFGR1_SAMPLE_SHIFT (1U) +/*! SAMPLE - Sample Point + * 0b0..Input data is sampled on SCK edge + * 0b1..Input data is sampled on delayed SCK edge + */ #define LPSPI_CFGR1_SAMPLE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_SAMPLE_SHIFT)) & LPSPI_CFGR1_SAMPLE_MASK) #define LPSPI_CFGR1_AUTOPCS_MASK (0x4U) #define LPSPI_CFGR1_AUTOPCS_SHIFT (2U) +/*! AUTOPCS - Automatic PCS + * 0b0..Automatic PCS generation is disabled + * 0b1..Automatic PCS generation is enabled + */ #define LPSPI_CFGR1_AUTOPCS(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_AUTOPCS_SHIFT)) & LPSPI_CFGR1_AUTOPCS_MASK) #define LPSPI_CFGR1_NOSTALL_MASK (0x8U) #define LPSPI_CFGR1_NOSTALL_SHIFT (3U) +/*! NOSTALL - No Stall + * 0b0..Transfers will stall when the transmit FIFO is empty or the receive FIFO is full + * 0b1..Transfers will not stall, allowing transmit FIFO underruns or receive FIFO overruns to occur + */ #define LPSPI_CFGR1_NOSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_NOSTALL_SHIFT)) & LPSPI_CFGR1_NOSTALL_MASK) #define LPSPI_CFGR1_PCSPOL_MASK (0xF00U) #define LPSPI_CFGR1_PCSPOL_SHIFT (8U) +/*! PCSPOL - Peripheral Chip Select Polarity + * 0b0000..The Peripheral Chip Select pin PCSx is active low + * 0b0001..The Peripheral Chip Select pin PCSx is active high + */ #define LPSPI_CFGR1_PCSPOL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PCSPOL_SHIFT)) & LPSPI_CFGR1_PCSPOL_MASK) #define LPSPI_CFGR1_MATCFG_MASK (0x70000U) #define LPSPI_CFGR1_MATCFG_SHIFT (16U) +/*! MATCFG - Match Configuration + * 0b000..Match is disabled + * 0b001..Reserved + * 0b010..010b - Match is enabled, if 1st data word equals MATCH0 OR MATCH1, i.e., (1st data word = MATCH0 + MATCH1) + * 0b011..011b - Match is enabled, if any data word equals MATCH0 OR MATCH1, i.e., (any data word = MATCH0 + MATCH1) + * 0b100..100b - Match is enabled, if 1st data word equals MATCH0 AND 2nd data word equals MATCH1, i.e., [(1st data word = MATCH0) * (2nd data word = MATCH1)] + * 0b101..101b - Match is enabled, if any data word equals MATCH0 AND the next data word equals MATCH1, i.e., [(any data word = MATCH0) * (next data word = MATCH1)] + * 0b110..110b - Match is enabled, if (1st data word AND MATCH1) equals (MATCH0 AND MATCH1), i.e., [(1st data word * MATCH1) = (MATCH0 * MATCH1)] + * 0b111..111b - Match is enabled, if (any data word AND MATCH1) equals (MATCH0 AND MATCH1), i.e., [(any data word * MATCH1) = (MATCH0 * MATCH1)] + */ #define LPSPI_CFGR1_MATCFG(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_MATCFG_SHIFT)) & LPSPI_CFGR1_MATCFG_MASK) #define LPSPI_CFGR1_PINCFG_MASK (0x3000000U) #define LPSPI_CFGR1_PINCFG_SHIFT (24U) +/*! PINCFG - Pin Configuration + * 0b00..SIN is used for input data and SOUT is used for output data + * 0b01..SIN is used for both input and output data + * 0b10..SOUT is used for both input and output data + * 0b11..SOUT is used for input data and SIN is used for output data + */ #define LPSPI_CFGR1_PINCFG(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PINCFG_SHIFT)) & LPSPI_CFGR1_PINCFG_MASK) #define LPSPI_CFGR1_OUTCFG_MASK (0x4000000U) #define LPSPI_CFGR1_OUTCFG_SHIFT (26U) +/*! OUTCFG - Output Config + * 0b0..Output data retains last value when chip select is negated + * 0b1..Output data is tristated when chip select is negated + */ #define LPSPI_CFGR1_OUTCFG(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_OUTCFG_SHIFT)) & LPSPI_CFGR1_OUTCFG_MASK) #define LPSPI_CFGR1_PCSCFG_MASK (0x8000000U) #define LPSPI_CFGR1_PCSCFG_SHIFT (27U) +/*! PCSCFG - Peripheral Chip Select Configuration + * 0b0..PCS[3:2] are enabled + * 0b1..PCS[3:2] are disabled + */ #define LPSPI_CFGR1_PCSCFG(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PCSCFG_SHIFT)) & LPSPI_CFGR1_PCSCFG_MASK) +/*! @} */ /*! @name DMR0 - Data Match Register 0 */ +/*! @{ */ #define LPSPI_DMR0_MATCH0_MASK (0xFFFFFFFFU) #define LPSPI_DMR0_MATCH0_SHIFT (0U) #define LPSPI_DMR0_MATCH0(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_DMR0_MATCH0_SHIFT)) & LPSPI_DMR0_MATCH0_MASK) +/*! @} */ /*! @name DMR1 - Data Match Register 1 */ +/*! @{ */ #define LPSPI_DMR1_MATCH1_MASK (0xFFFFFFFFU) #define LPSPI_DMR1_MATCH1_SHIFT (0U) #define LPSPI_DMR1_MATCH1(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_DMR1_MATCH1_SHIFT)) & LPSPI_DMR1_MATCH1_MASK) +/*! @} */ /*! @name CCR - Clock Configuration Register */ +/*! @{ */ #define LPSPI_CCR_SCKDIV_MASK (0xFFU) #define LPSPI_CCR_SCKDIV_SHIFT (0U) #define LPSPI_CCR_SCKDIV(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_SCKDIV_SHIFT)) & LPSPI_CCR_SCKDIV_MASK) @@ -14916,78 +23727,153 @@ typedef struct { #define LPSPI_CCR_SCKPCS_MASK (0xFF000000U) #define LPSPI_CCR_SCKPCS_SHIFT (24U) #define LPSPI_CCR_SCKPCS(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_SCKPCS_SHIFT)) & LPSPI_CCR_SCKPCS_MASK) +/*! @} */ /*! @name FCR - FIFO Control Register */ +/*! @{ */ #define LPSPI_FCR_TXWATER_MASK (0xFU) #define LPSPI_FCR_TXWATER_SHIFT (0U) #define LPSPI_FCR_TXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_FCR_TXWATER_SHIFT)) & LPSPI_FCR_TXWATER_MASK) #define LPSPI_FCR_RXWATER_MASK (0xF0000U) #define LPSPI_FCR_RXWATER_SHIFT (16U) #define LPSPI_FCR_RXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_FCR_RXWATER_SHIFT)) & LPSPI_FCR_RXWATER_MASK) +/*! @} */ /*! @name FSR - FIFO Status Register */ +/*! @{ */ #define LPSPI_FSR_TXCOUNT_MASK (0x1FU) #define LPSPI_FSR_TXCOUNT_SHIFT (0U) #define LPSPI_FSR_TXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_FSR_TXCOUNT_SHIFT)) & LPSPI_FSR_TXCOUNT_MASK) #define LPSPI_FSR_RXCOUNT_MASK (0x1F0000U) #define LPSPI_FSR_RXCOUNT_SHIFT (16U) #define LPSPI_FSR_RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_FSR_RXCOUNT_SHIFT)) & LPSPI_FSR_RXCOUNT_MASK) +/*! @} */ /*! @name TCR - Transmit Command Register */ +/*! @{ */ #define LPSPI_TCR_FRAMESZ_MASK (0xFFFU) #define LPSPI_TCR_FRAMESZ_SHIFT (0U) #define LPSPI_TCR_FRAMESZ(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_FRAMESZ_SHIFT)) & LPSPI_TCR_FRAMESZ_MASK) #define LPSPI_TCR_WIDTH_MASK (0x30000U) #define LPSPI_TCR_WIDTH_SHIFT (16U) +/*! WIDTH - Transfer Width + * 0b00..1 bit transfer + * 0b01..2 bit transfer + * 0b10..4 bit transfer + * 0b11..Reserved + */ #define LPSPI_TCR_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_WIDTH_SHIFT)) & LPSPI_TCR_WIDTH_MASK) #define LPSPI_TCR_TXMSK_MASK (0x40000U) #define LPSPI_TCR_TXMSK_SHIFT (18U) +/*! TXMSK - Transmit Data Mask + * 0b0..Normal transfer + * 0b1..Mask transmit data + */ #define LPSPI_TCR_TXMSK(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_TXMSK_SHIFT)) & LPSPI_TCR_TXMSK_MASK) #define LPSPI_TCR_RXMSK_MASK (0x80000U) #define LPSPI_TCR_RXMSK_SHIFT (19U) +/*! RXMSK - Receive Data Mask + * 0b0..Normal transfer + * 0b1..Receive data is masked + */ #define LPSPI_TCR_RXMSK(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_RXMSK_SHIFT)) & LPSPI_TCR_RXMSK_MASK) #define LPSPI_TCR_CONTC_MASK (0x100000U) #define LPSPI_TCR_CONTC_SHIFT (20U) +/*! CONTC - Continuing Command + * 0b0..Command word for start of new transfer + * 0b1..Command word for continuing transfer + */ #define LPSPI_TCR_CONTC(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CONTC_SHIFT)) & LPSPI_TCR_CONTC_MASK) #define LPSPI_TCR_CONT_MASK (0x200000U) #define LPSPI_TCR_CONT_SHIFT (21U) +/*! CONT - Continuous Transfer + * 0b0..Continuous transfer is disabled + * 0b1..Continuous transfer is enabled + */ #define LPSPI_TCR_CONT(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CONT_SHIFT)) & LPSPI_TCR_CONT_MASK) #define LPSPI_TCR_BYSW_MASK (0x400000U) #define LPSPI_TCR_BYSW_SHIFT (22U) +/*! BYSW - Byte Swap + * 0b0..Byte swap is disabled + * 0b1..Byte swap is enabled + */ #define LPSPI_TCR_BYSW(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_BYSW_SHIFT)) & LPSPI_TCR_BYSW_MASK) #define LPSPI_TCR_LSBF_MASK (0x800000U) #define LPSPI_TCR_LSBF_SHIFT (23U) +/*! LSBF - LSB First + * 0b0..Data is transferred MSB first + * 0b1..Data is transferred LSB first + */ #define LPSPI_TCR_LSBF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_LSBF_SHIFT)) & LPSPI_TCR_LSBF_MASK) #define LPSPI_TCR_PCS_MASK (0x3000000U) #define LPSPI_TCR_PCS_SHIFT (24U) +/*! PCS - Peripheral Chip Select + * 0b00..Transfer using LPSPI_PCS[0] + * 0b01..Transfer using LPSPI_PCS[1] + * 0b10..Transfer using LPSPI_PCS[2] + * 0b11..Transfer using LPSPI_PCS[3] + */ #define LPSPI_TCR_PCS(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_PCS_SHIFT)) & LPSPI_TCR_PCS_MASK) #define LPSPI_TCR_PRESCALE_MASK (0x38000000U) #define LPSPI_TCR_PRESCALE_SHIFT (27U) +/*! PRESCALE - Prescaler Value + * 0b000..Divide by 1 + * 0b001..Divide by 2 + * 0b010..Divide by 4 + * 0b011..Divide by 8 + * 0b100..Divide by 16 + * 0b101..Divide by 32 + * 0b110..Divide by 64 + * 0b111..Divide by 128 + */ #define LPSPI_TCR_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_PRESCALE_SHIFT)) & LPSPI_TCR_PRESCALE_MASK) #define LPSPI_TCR_CPHA_MASK (0x40000000U) #define LPSPI_TCR_CPHA_SHIFT (30U) +/*! CPHA - Clock Phase + * 0b0..Data is captured on the leading edge of SCK and changed on the following edge of SCK + * 0b1..Data is changed on the leading edge of SCK and captured on the following edge of SCK + */ #define LPSPI_TCR_CPHA(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CPHA_SHIFT)) & LPSPI_TCR_CPHA_MASK) #define LPSPI_TCR_CPOL_MASK (0x80000000U) #define LPSPI_TCR_CPOL_SHIFT (31U) +/*! CPOL - Clock Polarity + * 0b0..The inactive state value of SCK is low + * 0b1..The inactive state value of SCK is high + */ #define LPSPI_TCR_CPOL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CPOL_SHIFT)) & LPSPI_TCR_CPOL_MASK) +/*! @} */ /*! @name TDR - Transmit Data Register */ +/*! @{ */ #define LPSPI_TDR_DATA_MASK (0xFFFFFFFFU) #define LPSPI_TDR_DATA_SHIFT (0U) #define LPSPI_TDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TDR_DATA_SHIFT)) & LPSPI_TDR_DATA_MASK) +/*! @} */ /*! @name RSR - Receive Status Register */ +/*! @{ */ #define LPSPI_RSR_SOF_MASK (0x1U) #define LPSPI_RSR_SOF_SHIFT (0U) +/*! SOF - Start Of Frame + * 0b0..Subsequent data word received after LPSPI_PCS assertion + * 0b1..First data word received after LPSPI_PCS assertion + */ #define LPSPI_RSR_SOF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_RSR_SOF_SHIFT)) & LPSPI_RSR_SOF_MASK) #define LPSPI_RSR_RXEMPTY_MASK (0x2U) #define LPSPI_RSR_RXEMPTY_SHIFT (1U) +/*! RXEMPTY - RX FIFO Empty + * 0b0..RX FIFO is not empty + * 0b1..RX FIFO is empty + */ #define LPSPI_RSR_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_RSR_RXEMPTY_SHIFT)) & LPSPI_RSR_RXEMPTY_MASK) +/*! @} */ /*! @name RDR - Receive Data Register */ +/*! @{ */ #define LPSPI_RDR_DATA_MASK (0xFFFFFFFFU) #define LPSPI_RDR_DATA_SHIFT (0U) #define LPSPI_RDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_RDR_DATA_SHIFT)) & LPSPI_RDR_DATA_MASK) +/*! @} */ /*! @@ -15059,8 +23945,13 @@ typedef struct { */ /*! @name VERID - Version ID Register */ +/*! @{ */ #define LPUART_VERID_FEATURE_MASK (0xFFFFU) #define LPUART_VERID_FEATURE_SHIFT (0U) +/*! FEATURE - Feature Identification Number + * 0b0000000000000001..Standard feature set. + * 0b0000000000000011..Standard feature set with MODEM/IrDA support. + */ #define LPUART_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_VERID_FEATURE_SHIFT)) & LPUART_VERID_FEATURE_MASK) #define LPUART_VERID_MINOR_MASK (0xFF0000U) #define LPUART_VERID_MINOR_SHIFT (16U) @@ -15068,200 +23959,491 @@ typedef struct { #define LPUART_VERID_MAJOR_MASK (0xFF000000U) #define LPUART_VERID_MAJOR_SHIFT (24U) #define LPUART_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_VERID_MAJOR_SHIFT)) & LPUART_VERID_MAJOR_MASK) +/*! @} */ /*! @name PARAM - Parameter Register */ +/*! @{ */ #define LPUART_PARAM_TXFIFO_MASK (0xFFU) #define LPUART_PARAM_TXFIFO_SHIFT (0U) #define LPUART_PARAM_TXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPUART_PARAM_TXFIFO_SHIFT)) & LPUART_PARAM_TXFIFO_MASK) #define LPUART_PARAM_RXFIFO_MASK (0xFF00U) #define LPUART_PARAM_RXFIFO_SHIFT (8U) #define LPUART_PARAM_RXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPUART_PARAM_RXFIFO_SHIFT)) & LPUART_PARAM_RXFIFO_MASK) +/*! @} */ /*! @name GLOBAL - LPUART Global Register */ +/*! @{ */ #define LPUART_GLOBAL_RST_MASK (0x2U) #define LPUART_GLOBAL_RST_SHIFT (1U) +/*! RST - Software Reset + * 0b0..Module is not reset. + * 0b1..Module is reset. + */ #define LPUART_GLOBAL_RST(x) (((uint32_t)(((uint32_t)(x)) << LPUART_GLOBAL_RST_SHIFT)) & LPUART_GLOBAL_RST_MASK) +/*! @} */ /*! @name PINCFG - LPUART Pin Configuration Register */ +/*! @{ */ #define LPUART_PINCFG_TRGSEL_MASK (0x3U) #define LPUART_PINCFG_TRGSEL_SHIFT (0U) +/*! TRGSEL - Trigger Select + * 0b00..Input trigger is disabled. + * 0b01..Input trigger is used instead of RXD pin input. + * 0b10..Input trigger is used instead of CTS_B pin input. + * 0b11..Input trigger is used to modulate the TXD pin output. The TXD pin output (after TXINV configuration) is ANDed with the input trigger. + */ #define LPUART_PINCFG_TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << LPUART_PINCFG_TRGSEL_SHIFT)) & LPUART_PINCFG_TRGSEL_MASK) +/*! @} */ /*! @name BAUD - LPUART Baud Rate Register */ +/*! @{ */ #define LPUART_BAUD_SBR_MASK (0x1FFFU) #define LPUART_BAUD_SBR_SHIFT (0U) #define LPUART_BAUD_SBR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_SBR_SHIFT)) & LPUART_BAUD_SBR_MASK) #define LPUART_BAUD_SBNS_MASK (0x2000U) #define LPUART_BAUD_SBNS_SHIFT (13U) +/*! SBNS - Stop Bit Number Select + * 0b0..One stop bit. + * 0b1..Two stop bits. + */ #define LPUART_BAUD_SBNS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_SBNS_SHIFT)) & LPUART_BAUD_SBNS_MASK) #define LPUART_BAUD_RXEDGIE_MASK (0x4000U) #define LPUART_BAUD_RXEDGIE_SHIFT (14U) +/*! RXEDGIE - RX Input Active Edge Interrupt Enable + * 0b0..Hardware interrupts from STAT[RXEDGIF] are disabled. + * 0b1..Hardware interrupt is requested when STAT[RXEDGIF] flag is 1. + */ #define LPUART_BAUD_RXEDGIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RXEDGIE_SHIFT)) & LPUART_BAUD_RXEDGIE_MASK) #define LPUART_BAUD_LBKDIE_MASK (0x8000U) #define LPUART_BAUD_LBKDIE_SHIFT (15U) +/*! LBKDIE - LIN Break Detect Interrupt Enable + * 0b0..Hardware interrupts from STAT[LBKDIF] flag are disabled (use polling). + * 0b1..Hardware interrupt requested when STAT[LBKDIF] flag is 1. + */ #define LPUART_BAUD_LBKDIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_LBKDIE_SHIFT)) & LPUART_BAUD_LBKDIE_MASK) #define LPUART_BAUD_RESYNCDIS_MASK (0x10000U) #define LPUART_BAUD_RESYNCDIS_SHIFT (16U) +/*! RESYNCDIS - Resynchronization Disable + * 0b0..Resynchronization during received data word is supported + * 0b1..Resynchronization during received data word is disabled + */ #define LPUART_BAUD_RESYNCDIS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RESYNCDIS_SHIFT)) & LPUART_BAUD_RESYNCDIS_MASK) #define LPUART_BAUD_BOTHEDGE_MASK (0x20000U) #define LPUART_BAUD_BOTHEDGE_SHIFT (17U) +/*! BOTHEDGE - Both Edge Sampling + * 0b0..Receiver samples input data using the rising edge of the baud rate clock. + * 0b1..Receiver samples input data using the rising and falling edge of the baud rate clock. + */ #define LPUART_BAUD_BOTHEDGE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_BOTHEDGE_SHIFT)) & LPUART_BAUD_BOTHEDGE_MASK) #define LPUART_BAUD_MATCFG_MASK (0xC0000U) #define LPUART_BAUD_MATCFG_SHIFT (18U) +/*! MATCFG - Match Configuration + * 0b00..Address Match Wakeup + * 0b01..Idle Match Wakeup + * 0b10..Match On and Match Off + * 0b11..Enables RWU on Data Match and Match On/Off for transmitter CTS input + */ #define LPUART_BAUD_MATCFG(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MATCFG_SHIFT)) & LPUART_BAUD_MATCFG_MASK) +#define LPUART_BAUD_RIDMAE_MASK (0x100000U) +#define LPUART_BAUD_RIDMAE_SHIFT (20U) +/*! RIDMAE - Receiver Idle DMA Enable + * 0b0..DMA request disabled. + * 0b1..DMA request enabled. + */ +#define LPUART_BAUD_RIDMAE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RIDMAE_SHIFT)) & LPUART_BAUD_RIDMAE_MASK) #define LPUART_BAUD_RDMAE_MASK (0x200000U) #define LPUART_BAUD_RDMAE_SHIFT (21U) +/*! RDMAE - Receiver Full DMA Enable + * 0b0..DMA request disabled. + * 0b1..DMA request enabled. + */ #define LPUART_BAUD_RDMAE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RDMAE_SHIFT)) & LPUART_BAUD_RDMAE_MASK) #define LPUART_BAUD_TDMAE_MASK (0x800000U) #define LPUART_BAUD_TDMAE_SHIFT (23U) +/*! TDMAE - Transmitter DMA Enable + * 0b0..DMA request disabled. + * 0b1..DMA request enabled. + */ #define LPUART_BAUD_TDMAE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_TDMAE_SHIFT)) & LPUART_BAUD_TDMAE_MASK) #define LPUART_BAUD_OSR_MASK (0x1F000000U) #define LPUART_BAUD_OSR_SHIFT (24U) +/*! OSR - Oversampling Ratio + * 0b00000..Writing 0 to this field will result in an oversampling ratio of 16 + * 0b00001..Reserved + * 0b00010..Reserved + * 0b00011..Oversampling ratio of 4, requires BOTHEDGE to be set. + * 0b00100..Oversampling ratio of 5, requires BOTHEDGE to be set. + * 0b00101..Oversampling ratio of 6, requires BOTHEDGE to be set. + * 0b00110..Oversampling ratio of 7, requires BOTHEDGE to be set. + * 0b00111..Oversampling ratio of 8. + * 0b01000..Oversampling ratio of 9. + * 0b01001..Oversampling ratio of 10. + * 0b01010..Oversampling ratio of 11. + * 0b01011..Oversampling ratio of 12. + * 0b01100..Oversampling ratio of 13. + * 0b01101..Oversampling ratio of 14. + * 0b01110..Oversampling ratio of 15. + * 0b01111..Oversampling ratio of 16. + * 0b10000..Oversampling ratio of 17. + * 0b10001..Oversampling ratio of 18. + * 0b10010..Oversampling ratio of 19. + * 0b10011..Oversampling ratio of 20. + * 0b10100..Oversampling ratio of 21. + * 0b10101..Oversampling ratio of 22. + * 0b10110..Oversampling ratio of 23. + * 0b10111..Oversampling ratio of 24. + * 0b11000..Oversampling ratio of 25. + * 0b11001..Oversampling ratio of 26. + * 0b11010..Oversampling ratio of 27. + * 0b11011..Oversampling ratio of 28. + * 0b11100..Oversampling ratio of 29. + * 0b11101..Oversampling ratio of 30. + * 0b11110..Oversampling ratio of 31. + * 0b11111..Oversampling ratio of 32. + */ #define LPUART_BAUD_OSR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_OSR_SHIFT)) & LPUART_BAUD_OSR_MASK) #define LPUART_BAUD_M10_MASK (0x20000000U) #define LPUART_BAUD_M10_SHIFT (29U) +/*! M10 - 10-bit Mode select + * 0b0..Receiver and transmitter use 7-bit to 9-bit data characters. + * 0b1..Receiver and transmitter use 10-bit data characters. + */ #define LPUART_BAUD_M10(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_M10_SHIFT)) & LPUART_BAUD_M10_MASK) #define LPUART_BAUD_MAEN2_MASK (0x40000000U) #define LPUART_BAUD_MAEN2_SHIFT (30U) +/*! MAEN2 - Match Address Mode Enable 2 + * 0b0..Normal operation. + * 0b1..Enables automatic address matching or data matching mode for MATCH[MA2]. + */ #define LPUART_BAUD_MAEN2(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MAEN2_SHIFT)) & LPUART_BAUD_MAEN2_MASK) #define LPUART_BAUD_MAEN1_MASK (0x80000000U) #define LPUART_BAUD_MAEN1_SHIFT (31U) +/*! MAEN1 - Match Address Mode Enable 1 + * 0b0..Normal operation. + * 0b1..Enables automatic address matching or data matching mode for MATCH[MA1]. + */ #define LPUART_BAUD_MAEN1(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MAEN1_SHIFT)) & LPUART_BAUD_MAEN1_MASK) +/*! @} */ /*! @name STAT - LPUART Status Register */ +/*! @{ */ #define LPUART_STAT_MA2F_MASK (0x4000U) #define LPUART_STAT_MA2F_SHIFT (14U) +/*! MA2F - Match 2 Flag + * 0b0..Received data is not equal to MA2 + * 0b1..Received data is equal to MA2 + */ #define LPUART_STAT_MA2F(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MA2F_SHIFT)) & LPUART_STAT_MA2F_MASK) #define LPUART_STAT_MA1F_MASK (0x8000U) #define LPUART_STAT_MA1F_SHIFT (15U) +/*! MA1F - Match 1 Flag + * 0b0..Received data is not equal to MA1 + * 0b1..Received data is equal to MA1 + */ #define LPUART_STAT_MA1F(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MA1F_SHIFT)) & LPUART_STAT_MA1F_MASK) #define LPUART_STAT_PF_MASK (0x10000U) #define LPUART_STAT_PF_SHIFT (16U) +/*! PF - Parity Error Flag + * 0b0..No parity error. + * 0b1..Parity error. + */ #define LPUART_STAT_PF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_PF_SHIFT)) & LPUART_STAT_PF_MASK) #define LPUART_STAT_FE_MASK (0x20000U) #define LPUART_STAT_FE_SHIFT (17U) +/*! FE - Framing Error Flag + * 0b0..No framing error detected. This does not guarantee the framing is correct. + * 0b1..Framing error. + */ #define LPUART_STAT_FE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_FE_SHIFT)) & LPUART_STAT_FE_MASK) #define LPUART_STAT_NF_MASK (0x40000U) #define LPUART_STAT_NF_SHIFT (18U) +/*! NF - Noise Flag + * 0b0..No noise detected. + * 0b1..Noise detected in the received character in the DATA register. + */ #define LPUART_STAT_NF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_NF_SHIFT)) & LPUART_STAT_NF_MASK) #define LPUART_STAT_OR_MASK (0x80000U) #define LPUART_STAT_OR_SHIFT (19U) +/*! OR - Receiver Overrun Flag + * 0b0..No overrun. + * 0b1..Receive overrun (new LPUART data lost). + */ #define LPUART_STAT_OR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_OR_SHIFT)) & LPUART_STAT_OR_MASK) #define LPUART_STAT_IDLE_MASK (0x100000U) #define LPUART_STAT_IDLE_SHIFT (20U) +/*! IDLE - Idle Line Flag + * 0b0..No idle line detected. + * 0b1..Idle line was detected. + */ #define LPUART_STAT_IDLE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_IDLE_SHIFT)) & LPUART_STAT_IDLE_MASK) #define LPUART_STAT_RDRF_MASK (0x200000U) #define LPUART_STAT_RDRF_SHIFT (21U) +/*! RDRF - Receive Data Register Full Flag + * 0b0..Receive data buffer empty. + * 0b1..Receive data buffer full. + */ #define LPUART_STAT_RDRF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RDRF_SHIFT)) & LPUART_STAT_RDRF_MASK) #define LPUART_STAT_TC_MASK (0x400000U) #define LPUART_STAT_TC_SHIFT (22U) +/*! TC - Transmission Complete Flag + * 0b0..Transmitter active (sending data, a preamble, or a break). + * 0b1..Transmitter idle (transmission activity complete). + */ #define LPUART_STAT_TC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_TC_SHIFT)) & LPUART_STAT_TC_MASK) #define LPUART_STAT_TDRE_MASK (0x800000U) #define LPUART_STAT_TDRE_SHIFT (23U) +/*! TDRE - Transmit Data Register Empty Flag + * 0b0..Transmit data buffer full. + * 0b1..Transmit data buffer empty. + */ #define LPUART_STAT_TDRE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_TDRE_SHIFT)) & LPUART_STAT_TDRE_MASK) #define LPUART_STAT_RAF_MASK (0x1000000U) #define LPUART_STAT_RAF_SHIFT (24U) +/*! RAF - Receiver Active Flag + * 0b0..LPUART receiver idle waiting for a start bit. + * 0b1..LPUART receiver active (RXD input not idle). + */ #define LPUART_STAT_RAF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RAF_SHIFT)) & LPUART_STAT_RAF_MASK) #define LPUART_STAT_LBKDE_MASK (0x2000000U) #define LPUART_STAT_LBKDE_SHIFT (25U) +/*! LBKDE - LIN Break Detection Enable + * 0b0..LIN break detect is disabled, normal break character can be detected. + * 0b1..LIN break detect is enabled. LIN break character is detected at length of 11 bit times (if M = 0) or 12 (if M = 1) or 13 (M10 = 1). + */ #define LPUART_STAT_LBKDE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_LBKDE_SHIFT)) & LPUART_STAT_LBKDE_MASK) #define LPUART_STAT_BRK13_MASK (0x4000000U) #define LPUART_STAT_BRK13_SHIFT (26U) +/*! BRK13 - Break Character Generation Length + * 0b0..Break character is transmitted with length of 9 to 13 bit times. + * 0b1..Break character is transmitted with length of 12 to 15 bit times. + */ #define LPUART_STAT_BRK13(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_BRK13_SHIFT)) & LPUART_STAT_BRK13_MASK) #define LPUART_STAT_RWUID_MASK (0x8000000U) #define LPUART_STAT_RWUID_SHIFT (27U) +/*! RWUID - Receive Wake Up Idle Detect + * 0b0..During receive standby state (RWU = 1), the IDLE bit does not get set upon detection of an idle character. During address match wakeup, the IDLE bit does not set when an address does not match. + * 0b1..During receive standby state (RWU = 1), the IDLE bit gets set upon detection of an idle character. During address match wakeup, the IDLE bit does set when an address does not match. + */ #define LPUART_STAT_RWUID(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RWUID_SHIFT)) & LPUART_STAT_RWUID_MASK) #define LPUART_STAT_RXINV_MASK (0x10000000U) #define LPUART_STAT_RXINV_SHIFT (28U) +/*! RXINV - Receive Data Inversion + * 0b0..Receive data not inverted. + * 0b1..Receive data inverted. + */ #define LPUART_STAT_RXINV(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RXINV_SHIFT)) & LPUART_STAT_RXINV_MASK) #define LPUART_STAT_MSBF_MASK (0x20000000U) #define LPUART_STAT_MSBF_SHIFT (29U) +/*! MSBF - MSB First + * 0b0..LSB (bit0) is the first bit that is transmitted following the start bit. Further, the first bit received after the start bit is identified as bit0. + * 0b1..MSB (bit9, bit8, bit7 or bit6) is the first bit that is transmitted following the start bit depending on the setting of CTRL[M], CTRL[PE] and BAUD[M10]. Further, the first bit received after the start bit is identified as bit9, bit8, bit7 or bit6 depending on the setting of CTRL[M] and CTRL[PE]. + */ #define LPUART_STAT_MSBF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MSBF_SHIFT)) & LPUART_STAT_MSBF_MASK) #define LPUART_STAT_RXEDGIF_MASK (0x40000000U) #define LPUART_STAT_RXEDGIF_SHIFT (30U) +/*! RXEDGIF - RXD Pin Active Edge Interrupt Flag + * 0b0..No active edge on the receive pin has occurred. + * 0b1..An active edge on the receive pin has occurred. + */ #define LPUART_STAT_RXEDGIF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RXEDGIF_SHIFT)) & LPUART_STAT_RXEDGIF_MASK) #define LPUART_STAT_LBKDIF_MASK (0x80000000U) #define LPUART_STAT_LBKDIF_SHIFT (31U) +/*! LBKDIF - LIN Break Detect Interrupt Flag + * 0b0..No LIN break character has been detected. + * 0b1..LIN break character has been detected. + */ #define LPUART_STAT_LBKDIF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_LBKDIF_SHIFT)) & LPUART_STAT_LBKDIF_MASK) +/*! @} */ /*! @name CTRL - LPUART Control Register */ +/*! @{ */ #define LPUART_CTRL_PT_MASK (0x1U) #define LPUART_CTRL_PT_SHIFT (0U) +/*! PT - Parity Type + * 0b0..Even parity. + * 0b1..Odd parity. + */ #define LPUART_CTRL_PT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PT_SHIFT)) & LPUART_CTRL_PT_MASK) #define LPUART_CTRL_PE_MASK (0x2U) #define LPUART_CTRL_PE_SHIFT (1U) +/*! PE - Parity Enable + * 0b0..No hardware parity generation or checking. + * 0b1..Parity enabled. + */ #define LPUART_CTRL_PE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PE_SHIFT)) & LPUART_CTRL_PE_MASK) #define LPUART_CTRL_ILT_MASK (0x4U) #define LPUART_CTRL_ILT_SHIFT (2U) +/*! ILT - Idle Line Type Select + * 0b0..Idle character bit count starts after start bit. + * 0b1..Idle character bit count starts after stop bit. + */ #define LPUART_CTRL_ILT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ILT_SHIFT)) & LPUART_CTRL_ILT_MASK) #define LPUART_CTRL_WAKE_MASK (0x8U) #define LPUART_CTRL_WAKE_SHIFT (3U) +/*! WAKE - Receiver Wakeup Method Select + * 0b0..Configures RWU for idle-line wakeup. + * 0b1..Configures RWU with address-mark wakeup. + */ #define LPUART_CTRL_WAKE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_WAKE_SHIFT)) & LPUART_CTRL_WAKE_MASK) #define LPUART_CTRL_M_MASK (0x10U) #define LPUART_CTRL_M_SHIFT (4U) +/*! M - 9-Bit or 8-Bit Mode Select + * 0b0..Receiver and transmitter use 8-bit data characters. + * 0b1..Receiver and transmitter use 9-bit data characters. + */ #define LPUART_CTRL_M(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_M_SHIFT)) & LPUART_CTRL_M_MASK) #define LPUART_CTRL_RSRC_MASK (0x20U) #define LPUART_CTRL_RSRC_SHIFT (5U) +/*! RSRC - Receiver Source Select + * 0b0..Provided LOOPS is set, RSRC is cleared, selects internal loop back mode and the LPUART does not use the RXD pin. + * 0b1..Single-wire LPUART mode where the TXD pin is connected to the transmitter output and receiver input. + */ #define LPUART_CTRL_RSRC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RSRC_SHIFT)) & LPUART_CTRL_RSRC_MASK) #define LPUART_CTRL_DOZEEN_MASK (0x40U) #define LPUART_CTRL_DOZEEN_SHIFT (6U) +/*! DOZEEN - Doze Enable + * 0b0..LPUART is enabled in Doze mode. + * 0b1..LPUART is disabled in Doze mode. + */ #define LPUART_CTRL_DOZEEN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_DOZEEN_SHIFT)) & LPUART_CTRL_DOZEEN_MASK) #define LPUART_CTRL_LOOPS_MASK (0x80U) #define LPUART_CTRL_LOOPS_SHIFT (7U) +/*! LOOPS - Loop Mode Select + * 0b0..Normal operation - RXD and TXD use separate pins. + * 0b1..Loop mode or single-wire mode where transmitter outputs are internally connected to receiver input (see RSRC bit). + */ #define LPUART_CTRL_LOOPS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_LOOPS_SHIFT)) & LPUART_CTRL_LOOPS_MASK) #define LPUART_CTRL_IDLECFG_MASK (0x700U) #define LPUART_CTRL_IDLECFG_SHIFT (8U) +/*! IDLECFG - Idle Configuration + * 0b000..1 idle character + * 0b001..2 idle characters + * 0b010..4 idle characters + * 0b011..8 idle characters + * 0b100..16 idle characters + * 0b101..32 idle characters + * 0b110..64 idle characters + * 0b111..128 idle characters + */ #define LPUART_CTRL_IDLECFG(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_IDLECFG_SHIFT)) & LPUART_CTRL_IDLECFG_MASK) #define LPUART_CTRL_M7_MASK (0x800U) #define LPUART_CTRL_M7_SHIFT (11U) +/*! M7 - 7-Bit Mode Select + * 0b0..Receiver and transmitter use 8-bit to 10-bit data characters. + * 0b1..Receiver and transmitter use 7-bit data characters. + */ #define LPUART_CTRL_M7(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_M7_SHIFT)) & LPUART_CTRL_M7_MASK) #define LPUART_CTRL_MA2IE_MASK (0x4000U) #define LPUART_CTRL_MA2IE_SHIFT (14U) +/*! MA2IE - Match 2 Interrupt Enable + * 0b0..MA2F interrupt disabled + * 0b1..MA2F interrupt enabled + */ #define LPUART_CTRL_MA2IE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_MA2IE_SHIFT)) & LPUART_CTRL_MA2IE_MASK) #define LPUART_CTRL_MA1IE_MASK (0x8000U) #define LPUART_CTRL_MA1IE_SHIFT (15U) +/*! MA1IE - Match 1 Interrupt Enable + * 0b0..MA1F interrupt disabled + * 0b1..MA1F interrupt enabled + */ #define LPUART_CTRL_MA1IE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_MA1IE_SHIFT)) & LPUART_CTRL_MA1IE_MASK) #define LPUART_CTRL_SBK_MASK (0x10000U) #define LPUART_CTRL_SBK_SHIFT (16U) +/*! SBK - Send Break + * 0b0..Normal transmitter operation. + * 0b1..Queue break character(s) to be sent. + */ #define LPUART_CTRL_SBK(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_SBK_SHIFT)) & LPUART_CTRL_SBK_MASK) #define LPUART_CTRL_RWU_MASK (0x20000U) #define LPUART_CTRL_RWU_SHIFT (17U) +/*! RWU - Receiver Wakeup Control + * 0b0..Normal receiver operation. + * 0b1..LPUART receiver in standby waiting for wakeup condition. + */ #define LPUART_CTRL_RWU(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RWU_SHIFT)) & LPUART_CTRL_RWU_MASK) #define LPUART_CTRL_RE_MASK (0x40000U) #define LPUART_CTRL_RE_SHIFT (18U) +/*! RE - Receiver Enable + * 0b0..Receiver disabled. + * 0b1..Receiver enabled. + */ #define LPUART_CTRL_RE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RE_SHIFT)) & LPUART_CTRL_RE_MASK) #define LPUART_CTRL_TE_MASK (0x80000U) #define LPUART_CTRL_TE_SHIFT (19U) +/*! TE - Transmitter Enable + * 0b0..Transmitter disabled. + * 0b1..Transmitter enabled. + */ #define LPUART_CTRL_TE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TE_SHIFT)) & LPUART_CTRL_TE_MASK) #define LPUART_CTRL_ILIE_MASK (0x100000U) #define LPUART_CTRL_ILIE_SHIFT (20U) +/*! ILIE - Idle Line Interrupt Enable + * 0b0..Hardware interrupts from IDLE disabled; use polling. + * 0b1..Hardware interrupt requested when IDLE flag is 1. + */ #define LPUART_CTRL_ILIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ILIE_SHIFT)) & LPUART_CTRL_ILIE_MASK) #define LPUART_CTRL_RIE_MASK (0x200000U) #define LPUART_CTRL_RIE_SHIFT (21U) +/*! RIE - Receiver Interrupt Enable + * 0b0..Hardware interrupts from RDRF disabled; use polling. + * 0b1..Hardware interrupt requested when RDRF flag is 1. + */ #define LPUART_CTRL_RIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RIE_SHIFT)) & LPUART_CTRL_RIE_MASK) #define LPUART_CTRL_TCIE_MASK (0x400000U) #define LPUART_CTRL_TCIE_SHIFT (22U) +/*! TCIE - Transmission Complete Interrupt Enable for + * 0b0..Hardware interrupts from TC disabled; use polling. + * 0b1..Hardware interrupt requested when TC flag is 1. + */ #define LPUART_CTRL_TCIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TCIE_SHIFT)) & LPUART_CTRL_TCIE_MASK) #define LPUART_CTRL_TIE_MASK (0x800000U) #define LPUART_CTRL_TIE_SHIFT (23U) +/*! TIE - Transmit Interrupt Enable + * 0b0..Hardware interrupts from TDRE disabled; use polling. + * 0b1..Hardware interrupt requested when TDRE flag is 1. + */ #define LPUART_CTRL_TIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TIE_SHIFT)) & LPUART_CTRL_TIE_MASK) #define LPUART_CTRL_PEIE_MASK (0x1000000U) #define LPUART_CTRL_PEIE_SHIFT (24U) +/*! PEIE - Parity Error Interrupt Enable + * 0b0..PF interrupts disabled; use polling). + * 0b1..Hardware interrupt requested when PF is set. + */ #define LPUART_CTRL_PEIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PEIE_SHIFT)) & LPUART_CTRL_PEIE_MASK) #define LPUART_CTRL_FEIE_MASK (0x2000000U) #define LPUART_CTRL_FEIE_SHIFT (25U) +/*! FEIE - Framing Error Interrupt Enable + * 0b0..FE interrupts disabled; use polling. + * 0b1..Hardware interrupt requested when FE is set. + */ #define LPUART_CTRL_FEIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_FEIE_SHIFT)) & LPUART_CTRL_FEIE_MASK) #define LPUART_CTRL_NEIE_MASK (0x4000000U) #define LPUART_CTRL_NEIE_SHIFT (26U) +/*! NEIE - Noise Error Interrupt Enable + * 0b0..NF interrupts disabled; use polling. + * 0b1..Hardware interrupt requested when NF is set. + */ #define LPUART_CTRL_NEIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_NEIE_SHIFT)) & LPUART_CTRL_NEIE_MASK) #define LPUART_CTRL_ORIE_MASK (0x8000000U) #define LPUART_CTRL_ORIE_SHIFT (27U) +/*! ORIE - Overrun Interrupt Enable + * 0b0..OR interrupts disabled; use polling. + * 0b1..Hardware interrupt requested when OR is set. + */ #define LPUART_CTRL_ORIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ORIE_SHIFT)) & LPUART_CTRL_ORIE_MASK) #define LPUART_CTRL_TXINV_MASK (0x10000000U) #define LPUART_CTRL_TXINV_SHIFT (28U) +/*! TXINV - Transmit Data Inversion + * 0b0..Transmit data not inverted. + * 0b1..Transmit data inverted. + */ #define LPUART_CTRL_TXINV(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TXINV_SHIFT)) & LPUART_CTRL_TXINV_MASK) #define LPUART_CTRL_TXDIR_MASK (0x20000000U) #define LPUART_CTRL_TXDIR_SHIFT (29U) +/*! TXDIR - TXD Pin Direction in Single-Wire Mode + * 0b0..TXD pin is an input in single-wire mode. + * 0b1..TXD pin is an output in single-wire mode. + */ #define LPUART_CTRL_TXDIR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TXDIR_SHIFT)) & LPUART_CTRL_TXDIR_MASK) #define LPUART_CTRL_R9T8_MASK (0x40000000U) #define LPUART_CTRL_R9T8_SHIFT (30U) @@ -15269,8 +24451,10 @@ typedef struct { #define LPUART_CTRL_R8T9_MASK (0x80000000U) #define LPUART_CTRL_R8T9_SHIFT (31U) #define LPUART_CTRL_R8T9(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_R8T9_SHIFT)) & LPUART_CTRL_R8T9_MASK) +/*! @} */ /*! @name DATA - LPUART Data Register */ +/*! @{ */ #define LPUART_DATA_R0T0_MASK (0x1U) #define LPUART_DATA_R0T0_SHIFT (0U) #define LPUART_DATA_R0T0(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R0T0_SHIFT)) & LPUART_DATA_R0T0_MASK) @@ -15303,99 +24487,231 @@ typedef struct { #define LPUART_DATA_R9T9(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R9T9_SHIFT)) & LPUART_DATA_R9T9_MASK) #define LPUART_DATA_IDLINE_MASK (0x800U) #define LPUART_DATA_IDLINE_SHIFT (11U) +/*! IDLINE - Idle Line + * 0b0..Receiver was not idle before receiving this character. + * 0b1..Receiver was idle before receiving this character. + */ #define LPUART_DATA_IDLINE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_IDLINE_SHIFT)) & LPUART_DATA_IDLINE_MASK) #define LPUART_DATA_RXEMPT_MASK (0x1000U) #define LPUART_DATA_RXEMPT_SHIFT (12U) +/*! RXEMPT - Receive Buffer Empty + * 0b0..Receive buffer contains valid data. + * 0b1..Receive buffer is empty, data returned on read is not valid. + */ #define LPUART_DATA_RXEMPT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_RXEMPT_SHIFT)) & LPUART_DATA_RXEMPT_MASK) #define LPUART_DATA_FRETSC_MASK (0x2000U) #define LPUART_DATA_FRETSC_SHIFT (13U) +/*! FRETSC - Frame Error / Transmit Special Character + * 0b0..The dataword was received without a frame error on read, or transmit a normal character on write. + * 0b1..The dataword was received with a frame error, or transmit an idle or break character on transmit. + */ #define LPUART_DATA_FRETSC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_FRETSC_SHIFT)) & LPUART_DATA_FRETSC_MASK) #define LPUART_DATA_PARITYE_MASK (0x4000U) #define LPUART_DATA_PARITYE_SHIFT (14U) +/*! PARITYE - PARITYE + * 0b0..The dataword was received without a parity error. + * 0b1..The dataword was received with a parity error. + */ #define LPUART_DATA_PARITYE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_PARITYE_SHIFT)) & LPUART_DATA_PARITYE_MASK) #define LPUART_DATA_NOISY_MASK (0x8000U) #define LPUART_DATA_NOISY_SHIFT (15U) +/*! NOISY - NOISY + * 0b0..The dataword was received without noise. + * 0b1..The data was received with noise. + */ #define LPUART_DATA_NOISY(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_NOISY_SHIFT)) & LPUART_DATA_NOISY_MASK) +/*! @} */ /*! @name MATCH - LPUART Match Address Register */ +/*! @{ */ #define LPUART_MATCH_MA1_MASK (0x3FFU) #define LPUART_MATCH_MA1_SHIFT (0U) #define LPUART_MATCH_MA1(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MATCH_MA1_SHIFT)) & LPUART_MATCH_MA1_MASK) #define LPUART_MATCH_MA2_MASK (0x3FF0000U) #define LPUART_MATCH_MA2_SHIFT (16U) #define LPUART_MATCH_MA2(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MATCH_MA2_SHIFT)) & LPUART_MATCH_MA2_MASK) +/*! @} */ /*! @name MODIR - LPUART Modem IrDA Register */ +/*! @{ */ #define LPUART_MODIR_TXCTSE_MASK (0x1U) #define LPUART_MODIR_TXCTSE_SHIFT (0U) +/*! TXCTSE - Transmitter clear-to-send enable + * 0b0..CTS has no effect on the transmitter. + * 0b1..Enables clear-to-send operation. The transmitter checks the state of CTS each time it is ready to send a character. If CTS is asserted, the character is sent. If CTS is deasserted, the signal TXD remains in the mark state and transmission is delayed until CTS is asserted. Changes in CTS as a character is being sent do not affect its transmission. + */ #define LPUART_MODIR_TXCTSE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSE_SHIFT)) & LPUART_MODIR_TXCTSE_MASK) #define LPUART_MODIR_TXRTSE_MASK (0x2U) #define LPUART_MODIR_TXRTSE_SHIFT (1U) +/*! TXRTSE - Transmitter request-to-send enable + * 0b0..The transmitter has no effect on RTS. + * 0b1..When a character is placed into an empty transmitter data buffer , RTS asserts one bit time before the start bit is transmitted. RTS deasserts one bit time after all characters in the transmitter data buffer and shift register are completely sent, including the last stop bit. + */ #define LPUART_MODIR_TXRTSE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXRTSE_SHIFT)) & LPUART_MODIR_TXRTSE_MASK) #define LPUART_MODIR_TXRTSPOL_MASK (0x4U) #define LPUART_MODIR_TXRTSPOL_SHIFT (2U) +/*! TXRTSPOL - Transmitter request-to-send polarity + * 0b0..Transmitter RTS is active low. + * 0b1..Transmitter RTS is active high. + */ #define LPUART_MODIR_TXRTSPOL(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXRTSPOL_SHIFT)) & LPUART_MODIR_TXRTSPOL_MASK) #define LPUART_MODIR_RXRTSE_MASK (0x8U) #define LPUART_MODIR_RXRTSE_SHIFT (3U) +/*! RXRTSE - Receiver request-to-send enable + * 0b0..The receiver has no effect on RTS. + * 0b1..RTS is deasserted if the receiver data register is full or a start bit has been detected that would cause the receiver data register to become full. RTS is asserted if the receiver data register is not full and has not detected a start bit that would cause the receiver data register to become full. + */ #define LPUART_MODIR_RXRTSE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_RXRTSE_SHIFT)) & LPUART_MODIR_RXRTSE_MASK) #define LPUART_MODIR_TXCTSC_MASK (0x10U) #define LPUART_MODIR_TXCTSC_SHIFT (4U) +/*! TXCTSC - Transmit CTS Configuration + * 0b0..CTS input is sampled at the start of each character. + * 0b1..CTS input is sampled when the transmitter is idle. + */ #define LPUART_MODIR_TXCTSC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSC_SHIFT)) & LPUART_MODIR_TXCTSC_MASK) #define LPUART_MODIR_TXCTSSRC_MASK (0x20U) #define LPUART_MODIR_TXCTSSRC_SHIFT (5U) +/*! TXCTSSRC - Transmit CTS Source + * 0b0..CTS input is the CTS_B pin. + * 0b1..CTS input is the inverted Receiver Match result. + */ #define LPUART_MODIR_TXCTSSRC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSSRC_SHIFT)) & LPUART_MODIR_TXCTSSRC_MASK) #define LPUART_MODIR_RTSWATER_MASK (0x300U) #define LPUART_MODIR_RTSWATER_SHIFT (8U) #define LPUART_MODIR_RTSWATER(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_RTSWATER_SHIFT)) & LPUART_MODIR_RTSWATER_MASK) #define LPUART_MODIR_TNP_MASK (0x30000U) #define LPUART_MODIR_TNP_SHIFT (16U) +/*! TNP - Transmitter narrow pulse + * 0b00..1/OSR. + * 0b01..2/OSR. + * 0b10..3/OSR. + * 0b11..4/OSR. + */ #define LPUART_MODIR_TNP(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TNP_SHIFT)) & LPUART_MODIR_TNP_MASK) #define LPUART_MODIR_IREN_MASK (0x40000U) #define LPUART_MODIR_IREN_SHIFT (18U) +/*! IREN - Infrared enable + * 0b0..IR disabled. + * 0b1..IR enabled. + */ #define LPUART_MODIR_IREN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_IREN_SHIFT)) & LPUART_MODIR_IREN_MASK) +/*! @} */ /*! @name FIFO - LPUART FIFO Register */ +/*! @{ */ #define LPUART_FIFO_RXFIFOSIZE_MASK (0x7U) #define LPUART_FIFO_RXFIFOSIZE_SHIFT (0U) +/*! RXFIFOSIZE - Receive FIFO Buffer Depth + * 0b000..Receive FIFO/Buffer depth = 1 dataword. + * 0b001..Receive FIFO/Buffer depth = 4 datawords. + * 0b010..Receive FIFO/Buffer depth = 8 datawords. + * 0b011..Receive FIFO/Buffer depth = 16 datawords. + * 0b100..Receive FIFO/Buffer depth = 32 datawords. + * 0b101..Receive FIFO/Buffer depth = 64 datawords. + * 0b110..Receive FIFO/Buffer depth = 128 datawords. + * 0b111..Receive FIFO/Buffer depth = 256 datawords. + */ #define LPUART_FIFO_RXFIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXFIFOSIZE_SHIFT)) & LPUART_FIFO_RXFIFOSIZE_MASK) #define LPUART_FIFO_RXFE_MASK (0x8U) #define LPUART_FIFO_RXFE_SHIFT (3U) +/*! RXFE - Receive FIFO Enable + * 0b0..Receive FIFO is not enabled. Buffer is depth 1. + * 0b1..Receive FIFO is enabled. Buffer is depth indicted by RXFIFOSIZE. + */ #define LPUART_FIFO_RXFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXFE_SHIFT)) & LPUART_FIFO_RXFE_MASK) #define LPUART_FIFO_TXFIFOSIZE_MASK (0x70U) #define LPUART_FIFO_TXFIFOSIZE_SHIFT (4U) +/*! TXFIFOSIZE - Transmit FIFO Buffer Depth + * 0b000..Transmit FIFO/Buffer depth = 1 dataword. + * 0b001..Transmit FIFO/Buffer depth = 4 datawords. + * 0b010..Transmit FIFO/Buffer depth = 8 datawords. + * 0b011..Transmit FIFO/Buffer depth = 16 datawords. + * 0b100..Transmit FIFO/Buffer depth = 32 datawords. + * 0b101..Transmit FIFO/Buffer depth = 64 datawords. + * 0b110..Transmit FIFO/Buffer depth = 128 datawords. + * 0b111..Transmit FIFO/Buffer depth = 256 datawords + */ #define LPUART_FIFO_TXFIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXFIFOSIZE_SHIFT)) & LPUART_FIFO_TXFIFOSIZE_MASK) #define LPUART_FIFO_TXFE_MASK (0x80U) #define LPUART_FIFO_TXFE_SHIFT (7U) +/*! TXFE - Transmit FIFO Enable + * 0b0..Transmit FIFO is not enabled. Buffer is depth 1. + * 0b1..Transmit FIFO is enabled. Buffer is depth indicated by TXFIFOSIZE. + */ #define LPUART_FIFO_TXFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXFE_SHIFT)) & LPUART_FIFO_TXFE_MASK) #define LPUART_FIFO_RXUFE_MASK (0x100U) #define LPUART_FIFO_RXUFE_SHIFT (8U) +/*! RXUFE - Receive FIFO Underflow Interrupt Enable + * 0b0..RXUF flag does not generate an interrupt to the host. + * 0b1..RXUF flag generates an interrupt to the host. + */ #define LPUART_FIFO_RXUFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXUFE_SHIFT)) & LPUART_FIFO_RXUFE_MASK) #define LPUART_FIFO_TXOFE_MASK (0x200U) #define LPUART_FIFO_TXOFE_SHIFT (9U) +/*! TXOFE - Transmit FIFO Overflow Interrupt Enable + * 0b0..TXOF flag does not generate an interrupt to the host. + * 0b1..TXOF flag generates an interrupt to the host. + */ #define LPUART_FIFO_TXOFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXOFE_SHIFT)) & LPUART_FIFO_TXOFE_MASK) #define LPUART_FIFO_RXIDEN_MASK (0x1C00U) #define LPUART_FIFO_RXIDEN_SHIFT (10U) +/*! RXIDEN - Receiver Idle Empty Enable + * 0b000..Disable RDRF assertion due to partially filled FIFO when receiver is idle. + * 0b001..Enable RDRF assertion due to partially filled FIFO when receiver is idle for 1 character. + * 0b010..Enable RDRF assertion due to partially filled FIFO when receiver is idle for 2 characters. + * 0b011..Enable RDRF assertion due to partially filled FIFO when receiver is idle for 4 characters. + * 0b100..Enable RDRF assertion due to partially filled FIFO when receiver is idle for 8 characters. + * 0b101..Enable RDRF assertion due to partially filled FIFO when receiver is idle for 16 characters. + * 0b110..Enable RDRF assertion due to partially filled FIFO when receiver is idle for 32 characters. + * 0b111..Enable RDRF assertion due to partially filled FIFO when receiver is idle for 64 characters. + */ #define LPUART_FIFO_RXIDEN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXIDEN_SHIFT)) & LPUART_FIFO_RXIDEN_MASK) #define LPUART_FIFO_RXFLUSH_MASK (0x4000U) #define LPUART_FIFO_RXFLUSH_SHIFT (14U) +/*! RXFLUSH - Receive FIFO/Buffer Flush + * 0b0..No flush operation occurs. + * 0b1..All data in the receive FIFO/buffer is cleared out. + */ #define LPUART_FIFO_RXFLUSH(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXFLUSH_SHIFT)) & LPUART_FIFO_RXFLUSH_MASK) #define LPUART_FIFO_TXFLUSH_MASK (0x8000U) #define LPUART_FIFO_TXFLUSH_SHIFT (15U) +/*! TXFLUSH - Transmit FIFO/Buffer Flush + * 0b0..No flush operation occurs. + * 0b1..All data in the transmit FIFO/Buffer is cleared out. + */ #define LPUART_FIFO_TXFLUSH(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXFLUSH_SHIFT)) & LPUART_FIFO_TXFLUSH_MASK) #define LPUART_FIFO_RXUF_MASK (0x10000U) #define LPUART_FIFO_RXUF_SHIFT (16U) +/*! RXUF - Receiver Buffer Underflow Flag + * 0b0..No receive buffer underflow has occurred since the last time the flag was cleared. + * 0b1..At least one receive buffer underflow has occurred since the last time the flag was cleared. + */ #define LPUART_FIFO_RXUF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXUF_SHIFT)) & LPUART_FIFO_RXUF_MASK) #define LPUART_FIFO_TXOF_MASK (0x20000U) #define LPUART_FIFO_TXOF_SHIFT (17U) +/*! TXOF - Transmitter Buffer Overflow Flag + * 0b0..No transmit buffer overflow has occurred since the last time the flag was cleared. + * 0b1..At least one transmit buffer overflow has occurred since the last time the flag was cleared. + */ #define LPUART_FIFO_TXOF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXOF_SHIFT)) & LPUART_FIFO_TXOF_MASK) #define LPUART_FIFO_RXEMPT_MASK (0x400000U) #define LPUART_FIFO_RXEMPT_SHIFT (22U) +/*! RXEMPT - Receive Buffer/FIFO Empty + * 0b0..Receive buffer is not empty. + * 0b1..Receive buffer is empty. + */ #define LPUART_FIFO_RXEMPT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXEMPT_SHIFT)) & LPUART_FIFO_RXEMPT_MASK) #define LPUART_FIFO_TXEMPT_MASK (0x800000U) #define LPUART_FIFO_TXEMPT_SHIFT (23U) +/*! TXEMPT - Transmit Buffer/FIFO Empty + * 0b0..Transmit buffer is not empty. + * 0b1..Transmit buffer is empty. + */ #define LPUART_FIFO_TXEMPT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXEMPT_SHIFT)) & LPUART_FIFO_TXEMPT_MASK) +/*! @} */ /*! @name WATER - LPUART Watermark Register */ +/*! @{ */ #define LPUART_WATER_TXWATER_MASK (0x3U) #define LPUART_WATER_TXWATER_SHIFT (0U) #define LPUART_WATER_TXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_TXWATER_SHIFT)) & LPUART_WATER_TXWATER_MASK) @@ -15408,6 +24724,7 @@ typedef struct { #define LPUART_WATER_RXCOUNT_MASK (0x7000000U) #define LPUART_WATER_RXCOUNT_SHIFT (24U) #define LPUART_WATER_RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_RXCOUNT_SHIFT)) & LPUART_WATER_RXCOUNT_MASK) +/*! @} */ /*! @@ -15583,6 +24900,7 @@ typedef struct { */ /*! @name CTRL - OTP Controller Control Register */ +/*! @{ */ #define OCOTP_CTRL_ADDR_MASK (0x3FU) #define OCOTP_CTRL_ADDR_SHIFT (0U) #define OCOTP_CTRL_ADDR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_ADDR_SHIFT)) & OCOTP_CTRL_ADDR_MASK) @@ -15598,8 +24916,10 @@ typedef struct { #define OCOTP_CTRL_WR_UNLOCK_MASK (0xFFFF0000U) #define OCOTP_CTRL_WR_UNLOCK_SHIFT (16U) #define OCOTP_CTRL_WR_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_WR_UNLOCK_SHIFT)) & OCOTP_CTRL_WR_UNLOCK_MASK) +/*! @} */ /*! @name CTRL_SET - OTP Controller Control Register */ +/*! @{ */ #define OCOTP_CTRL_SET_ADDR_MASK (0x3FU) #define OCOTP_CTRL_SET_ADDR_SHIFT (0U) #define OCOTP_CTRL_SET_ADDR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_SET_ADDR_SHIFT)) & OCOTP_CTRL_SET_ADDR_MASK) @@ -15615,8 +24935,10 @@ typedef struct { #define OCOTP_CTRL_SET_WR_UNLOCK_MASK (0xFFFF0000U) #define OCOTP_CTRL_SET_WR_UNLOCK_SHIFT (16U) #define OCOTP_CTRL_SET_WR_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_SET_WR_UNLOCK_SHIFT)) & OCOTP_CTRL_SET_WR_UNLOCK_MASK) +/*! @} */ /*! @name CTRL_CLR - OTP Controller Control Register */ +/*! @{ */ #define OCOTP_CTRL_CLR_ADDR_MASK (0x3FU) #define OCOTP_CTRL_CLR_ADDR_SHIFT (0U) #define OCOTP_CTRL_CLR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CLR_ADDR_SHIFT)) & OCOTP_CTRL_CLR_ADDR_MASK) @@ -15632,8 +24954,10 @@ typedef struct { #define OCOTP_CTRL_CLR_WR_UNLOCK_MASK (0xFFFF0000U) #define OCOTP_CTRL_CLR_WR_UNLOCK_SHIFT (16U) #define OCOTP_CTRL_CLR_WR_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CLR_WR_UNLOCK_SHIFT)) & OCOTP_CTRL_CLR_WR_UNLOCK_MASK) +/*! @} */ /*! @name CTRL_TOG - OTP Controller Control Register */ +/*! @{ */ #define OCOTP_CTRL_TOG_ADDR_MASK (0x3FU) #define OCOTP_CTRL_TOG_ADDR_SHIFT (0U) #define OCOTP_CTRL_TOG_ADDR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_TOG_ADDR_SHIFT)) & OCOTP_CTRL_TOG_ADDR_MASK) @@ -15649,8 +24973,10 @@ typedef struct { #define OCOTP_CTRL_TOG_WR_UNLOCK_MASK (0xFFFF0000U) #define OCOTP_CTRL_TOG_WR_UNLOCK_SHIFT (16U) #define OCOTP_CTRL_TOG_WR_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_TOG_WR_UNLOCK_SHIFT)) & OCOTP_CTRL_TOG_WR_UNLOCK_MASK) +/*! @} */ /*! @name TIMING - OTP Controller Timing Register */ +/*! @{ */ #define OCOTP_TIMING_STROBE_PROG_MASK (0xFFFU) #define OCOTP_TIMING_STROBE_PROG_SHIFT (0U) #define OCOTP_TIMING_STROBE_PROG(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_TIMING_STROBE_PROG_SHIFT)) & OCOTP_TIMING_STROBE_PROG_MASK) @@ -15663,23 +24989,31 @@ typedef struct { #define OCOTP_TIMING_WAIT_MASK (0xFC00000U) #define OCOTP_TIMING_WAIT_SHIFT (22U) #define OCOTP_TIMING_WAIT(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_TIMING_WAIT_SHIFT)) & OCOTP_TIMING_WAIT_MASK) +/*! @} */ /*! @name DATA - OTP Controller Write Data Register */ +/*! @{ */ #define OCOTP_DATA_DATA_MASK (0xFFFFFFFFU) #define OCOTP_DATA_DATA_SHIFT (0U) #define OCOTP_DATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_DATA_DATA_SHIFT)) & OCOTP_DATA_DATA_MASK) +/*! @} */ /*! @name READ_CTRL - OTP Controller Write Data Register */ +/*! @{ */ #define OCOTP_READ_CTRL_READ_FUSE_MASK (0x1U) #define OCOTP_READ_CTRL_READ_FUSE_SHIFT (0U) #define OCOTP_READ_CTRL_READ_FUSE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_READ_CTRL_READ_FUSE_SHIFT)) & OCOTP_READ_CTRL_READ_FUSE_MASK) +/*! @} */ /*! @name READ_FUSE_DATA - OTP Controller Read Data Register */ +/*! @{ */ #define OCOTP_READ_FUSE_DATA_DATA_MASK (0xFFFFFFFFU) #define OCOTP_READ_FUSE_DATA_DATA_SHIFT (0U) #define OCOTP_READ_FUSE_DATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_READ_FUSE_DATA_DATA_SHIFT)) & OCOTP_READ_FUSE_DATA_DATA_MASK) +/*! @} */ /*! @name SW_STICKY - Sticky bit Register */ +/*! @{ */ #define OCOTP_SW_STICKY_BLOCK_DTCP_KEY_MASK (0x1U) #define OCOTP_SW_STICKY_BLOCK_DTCP_KEY_SHIFT (0U) #define OCOTP_SW_STICKY_BLOCK_DTCP_KEY(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_STICKY_BLOCK_DTCP_KEY_SHIFT)) & OCOTP_SW_STICKY_BLOCK_DTCP_KEY_MASK) @@ -15695,8 +25029,10 @@ typedef struct { #define OCOTP_SW_STICKY_JTAG_BLOCK_RELEASE_MASK (0x10U) #define OCOTP_SW_STICKY_JTAG_BLOCK_RELEASE_SHIFT (4U) #define OCOTP_SW_STICKY_JTAG_BLOCK_RELEASE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_STICKY_JTAG_BLOCK_RELEASE_SHIFT)) & OCOTP_SW_STICKY_JTAG_BLOCK_RELEASE_MASK) +/*! @} */ /*! @name SCS - Software Controllable Signals Register */ +/*! @{ */ #define OCOTP_SCS_HAB_JDE_MASK (0x1U) #define OCOTP_SCS_HAB_JDE_SHIFT (0U) #define OCOTP_SCS_HAB_JDE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_HAB_JDE_SHIFT)) & OCOTP_SCS_HAB_JDE_MASK) @@ -15706,8 +25042,10 @@ typedef struct { #define OCOTP_SCS_LOCK_MASK (0x80000000U) #define OCOTP_SCS_LOCK_SHIFT (31U) #define OCOTP_SCS_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_LOCK_SHIFT)) & OCOTP_SCS_LOCK_MASK) +/*! @} */ /*! @name SCS_SET - Software Controllable Signals Register */ +/*! @{ */ #define OCOTP_SCS_SET_HAB_JDE_MASK (0x1U) #define OCOTP_SCS_SET_HAB_JDE_SHIFT (0U) #define OCOTP_SCS_SET_HAB_JDE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_SET_HAB_JDE_SHIFT)) & OCOTP_SCS_SET_HAB_JDE_MASK) @@ -15717,8 +25055,10 @@ typedef struct { #define OCOTP_SCS_SET_LOCK_MASK (0x80000000U) #define OCOTP_SCS_SET_LOCK_SHIFT (31U) #define OCOTP_SCS_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_SET_LOCK_SHIFT)) & OCOTP_SCS_SET_LOCK_MASK) +/*! @} */ /*! @name SCS_CLR - Software Controllable Signals Register */ +/*! @{ */ #define OCOTP_SCS_CLR_HAB_JDE_MASK (0x1U) #define OCOTP_SCS_CLR_HAB_JDE_SHIFT (0U) #define OCOTP_SCS_CLR_HAB_JDE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_CLR_HAB_JDE_SHIFT)) & OCOTP_SCS_CLR_HAB_JDE_MASK) @@ -15728,8 +25068,10 @@ typedef struct { #define OCOTP_SCS_CLR_LOCK_MASK (0x80000000U) #define OCOTP_SCS_CLR_LOCK_SHIFT (31U) #define OCOTP_SCS_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_CLR_LOCK_SHIFT)) & OCOTP_SCS_CLR_LOCK_MASK) +/*! @} */ /*! @name SCS_TOG - Software Controllable Signals Register */ +/*! @{ */ #define OCOTP_SCS_TOG_HAB_JDE_MASK (0x1U) #define OCOTP_SCS_TOG_HAB_JDE_SHIFT (0U) #define OCOTP_SCS_TOG_HAB_JDE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_TOG_HAB_JDE_SHIFT)) & OCOTP_SCS_TOG_HAB_JDE_MASK) @@ -15739,8 +25081,10 @@ typedef struct { #define OCOTP_SCS_TOG_LOCK_MASK (0x80000000U) #define OCOTP_SCS_TOG_LOCK_SHIFT (31U) #define OCOTP_SCS_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_TOG_LOCK_SHIFT)) & OCOTP_SCS_TOG_LOCK_MASK) +/*! @} */ /*! @name VERSION - OTP Controller Version Register */ +/*! @{ */ #define OCOTP_VERSION_STEP_MASK (0xFFFFU) #define OCOTP_VERSION_STEP_SHIFT (0U) #define OCOTP_VERSION_STEP(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_VERSION_STEP_SHIFT)) & OCOTP_VERSION_STEP_MASK) @@ -15750,8 +25094,10 @@ typedef struct { #define OCOTP_VERSION_MAJOR_MASK (0xFF000000U) #define OCOTP_VERSION_MAJOR_SHIFT (24U) #define OCOTP_VERSION_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_VERSION_MAJOR_SHIFT)) & OCOTP_VERSION_MAJOR_MASK) +/*! @} */ /*! @name TIMING2 - OTP Controller Timing Register 2 */ +/*! @{ */ #define OCOTP_TIMING2_RELAX_PROG_MASK (0xFFFU) #define OCOTP_TIMING2_RELAX_PROG_SHIFT (0U) #define OCOTP_TIMING2_RELAX_PROG(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_TIMING2_RELAX_PROG_SHIFT)) & OCOTP_TIMING2_RELAX_PROG_MASK) @@ -15761,8 +25107,10 @@ typedef struct { #define OCOTP_TIMING2_RELAX1_MASK (0x1FC00000U) #define OCOTP_TIMING2_RELAX1_SHIFT (22U) #define OCOTP_TIMING2_RELAX1(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_TIMING2_RELAX1_SHIFT)) & OCOTP_TIMING2_RELAX1_MASK) +/*! @} */ /*! @name LOCK - Value of OTP Bank0 Word0 (Lock controls) */ +/*! @{ */ #define OCOTP_LOCK_TESTER_MASK (0x3U) #define OCOTP_LOCK_TESTER_SHIFT (0U) #define OCOTP_LOCK_TESTER(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_TESTER_SHIFT)) & OCOTP_LOCK_TESTER_MASK) @@ -15784,9 +25132,6 @@ typedef struct { #define OCOTP_LOCK_GP2_MASK (0x3000U) #define OCOTP_LOCK_GP2_SHIFT (12U) #define OCOTP_LOCK_GP2(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_GP2_SHIFT)) & OCOTP_LOCK_GP2_MASK) -#define OCOTP_LOCK_SRK_MASK (0x4000U) -#define OCOTP_LOCK_SRK_SHIFT (14U) -#define OCOTP_LOCK_SRK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_SRK_SHIFT)) & OCOTP_LOCK_SRK_MASK) #define OCOTP_LOCK_OTPMK_MSB_MASK (0x8000U) #define OCOTP_LOCK_OTPMK_MSB_SHIFT (15U) #define OCOTP_LOCK_OTPMK_MSB(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_OTPMK_MSB_SHIFT)) & OCOTP_LOCK_OTPMK_MSB_MASK) @@ -15817,196 +25162,273 @@ typedef struct { #define OCOTP_LOCK_FIELD_RETURN_MASK (0xF0000000U) #define OCOTP_LOCK_FIELD_RETURN_SHIFT (28U) #define OCOTP_LOCK_FIELD_RETURN(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_FIELD_RETURN_SHIFT)) & OCOTP_LOCK_FIELD_RETURN_MASK) +/*! @} */ /*! @name CFG0 - Value of OTP Bank0 Word1 (Configuration and Manufacturing Info.) */ +/*! @{ */ #define OCOTP_CFG0_BITS_MASK (0xFFFFFFFFU) #define OCOTP_CFG0_BITS_SHIFT (0U) #define OCOTP_CFG0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CFG0_BITS_SHIFT)) & OCOTP_CFG0_BITS_MASK) +/*! @} */ /*! @name CFG1 - Value of OTP Bank0 Word2 (Configuration and Manufacturing Info.) */ +/*! @{ */ #define OCOTP_CFG1_BITS_MASK (0xFFFFFFFFU) #define OCOTP_CFG1_BITS_SHIFT (0U) #define OCOTP_CFG1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CFG1_BITS_SHIFT)) & OCOTP_CFG1_BITS_MASK) +/*! @} */ /*! @name CFG2 - Value of OTP Bank0 Word3 (Configuration and Manufacturing Info.) */ +/*! @{ */ #define OCOTP_CFG2_BITS_MASK (0xFFFFFFFFU) #define OCOTP_CFG2_BITS_SHIFT (0U) #define OCOTP_CFG2_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CFG2_BITS_SHIFT)) & OCOTP_CFG2_BITS_MASK) +/*! @} */ /*! @name CFG3 - Value of OTP Bank0 Word4 (Configuration and Manufacturing Info.) */ +/*! @{ */ #define OCOTP_CFG3_BITS_MASK (0xFFFFFFFFU) #define OCOTP_CFG3_BITS_SHIFT (0U) #define OCOTP_CFG3_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CFG3_BITS_SHIFT)) & OCOTP_CFG3_BITS_MASK) +/*! @} */ /*! @name CFG4 - Value of OTP Bank0 Word5 (Configuration and Manufacturing Info.) */ +/*! @{ */ #define OCOTP_CFG4_BITS_MASK (0xFFFFFFFFU) #define OCOTP_CFG4_BITS_SHIFT (0U) #define OCOTP_CFG4_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CFG4_BITS_SHIFT)) & OCOTP_CFG4_BITS_MASK) +/*! @} */ /*! @name CFG5 - Value of OTP Bank0 Word6 (Configuration and Manufacturing Info.) */ +/*! @{ */ #define OCOTP_CFG5_BITS_MASK (0xFFFFFFFFU) #define OCOTP_CFG5_BITS_SHIFT (0U) #define OCOTP_CFG5_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CFG5_BITS_SHIFT)) & OCOTP_CFG5_BITS_MASK) +/*! @} */ /*! @name CFG6 - Value of OTP Bank0 Word7 (Configuration and Manufacturing Info.) */ +/*! @{ */ #define OCOTP_CFG6_BITS_MASK (0xFFFFFFFFU) #define OCOTP_CFG6_BITS_SHIFT (0U) #define OCOTP_CFG6_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CFG6_BITS_SHIFT)) & OCOTP_CFG6_BITS_MASK) +/*! @} */ /*! @name MEM0 - Value of OTP Bank1 Word0 (Memory Related Info.) */ +/*! @{ */ #define OCOTP_MEM0_BITS_MASK (0xFFFFFFFFU) #define OCOTP_MEM0_BITS_SHIFT (0U) #define OCOTP_MEM0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MEM0_BITS_SHIFT)) & OCOTP_MEM0_BITS_MASK) +/*! @} */ /*! @name MEM1 - Value of OTP Bank1 Word1 (Memory Related Info.) */ +/*! @{ */ #define OCOTP_MEM1_BITS_MASK (0xFFFFFFFFU) #define OCOTP_MEM1_BITS_SHIFT (0U) #define OCOTP_MEM1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MEM1_BITS_SHIFT)) & OCOTP_MEM1_BITS_MASK) +/*! @} */ /*! @name MEM2 - Value of OTP Bank1 Word2 (Memory Related Info.) */ +/*! @{ */ #define OCOTP_MEM2_BITS_MASK (0xFFFFFFFFU) #define OCOTP_MEM2_BITS_SHIFT (0U) #define OCOTP_MEM2_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MEM2_BITS_SHIFT)) & OCOTP_MEM2_BITS_MASK) +/*! @} */ /*! @name MEM3 - Value of OTP Bank1 Word3 (Memory Related Info.) */ +/*! @{ */ #define OCOTP_MEM3_BITS_MASK (0xFFFFFFFFU) #define OCOTP_MEM3_BITS_SHIFT (0U) #define OCOTP_MEM3_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MEM3_BITS_SHIFT)) & OCOTP_MEM3_BITS_MASK) +/*! @} */ /*! @name MEM4 - Value of OTP Bank1 Word4 (Memory Related Info.) */ +/*! @{ */ #define OCOTP_MEM4_BITS_MASK (0xFFFFFFFFU) #define OCOTP_MEM4_BITS_SHIFT (0U) #define OCOTP_MEM4_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MEM4_BITS_SHIFT)) & OCOTP_MEM4_BITS_MASK) +/*! @} */ /*! @name ANA0 - Value of OTP Bank1 Word5 (Analog Info.) */ +/*! @{ */ #define OCOTP_ANA0_BITS_MASK (0xFFFFFFFFU) #define OCOTP_ANA0_BITS_SHIFT (0U) #define OCOTP_ANA0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_ANA0_BITS_SHIFT)) & OCOTP_ANA0_BITS_MASK) +/*! @} */ /*! @name ANA1 - Value of OTP Bank1 Word6 (Analog Info.) */ +/*! @{ */ #define OCOTP_ANA1_BITS_MASK (0xFFFFFFFFU) #define OCOTP_ANA1_BITS_SHIFT (0U) #define OCOTP_ANA1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_ANA1_BITS_SHIFT)) & OCOTP_ANA1_BITS_MASK) +/*! @} */ /*! @name ANA2 - Value of OTP Bank1 Word7 (Analog Info.) */ +/*! @{ */ #define OCOTP_ANA2_BITS_MASK (0xFFFFFFFFU) #define OCOTP_ANA2_BITS_SHIFT (0U) #define OCOTP_ANA2_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_ANA2_BITS_SHIFT)) & OCOTP_ANA2_BITS_MASK) +/*! @} */ /*! @name SRK0 - Shadow Register for OTP Bank3 Word0 (SRK Hash) */ +/*! @{ */ #define OCOTP_SRK0_BITS_MASK (0xFFFFFFFFU) #define OCOTP_SRK0_BITS_SHIFT (0U) #define OCOTP_SRK0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK0_BITS_SHIFT)) & OCOTP_SRK0_BITS_MASK) +/*! @} */ /*! @name SRK1 - Shadow Register for OTP Bank3 Word1 (SRK Hash) */ +/*! @{ */ #define OCOTP_SRK1_BITS_MASK (0xFFFFFFFFU) #define OCOTP_SRK1_BITS_SHIFT (0U) #define OCOTP_SRK1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK1_BITS_SHIFT)) & OCOTP_SRK1_BITS_MASK) +/*! @} */ /*! @name SRK2 - Shadow Register for OTP Bank3 Word2 (SRK Hash) */ +/*! @{ */ #define OCOTP_SRK2_BITS_MASK (0xFFFFFFFFU) #define OCOTP_SRK2_BITS_SHIFT (0U) #define OCOTP_SRK2_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK2_BITS_SHIFT)) & OCOTP_SRK2_BITS_MASK) +/*! @} */ /*! @name SRK3 - Shadow Register for OTP Bank3 Word3 (SRK Hash) */ +/*! @{ */ #define OCOTP_SRK3_BITS_MASK (0xFFFFFFFFU) #define OCOTP_SRK3_BITS_SHIFT (0U) #define OCOTP_SRK3_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK3_BITS_SHIFT)) & OCOTP_SRK3_BITS_MASK) +/*! @} */ /*! @name SRK4 - Shadow Register for OTP Bank3 Word4 (SRK Hash) */ +/*! @{ */ #define OCOTP_SRK4_BITS_MASK (0xFFFFFFFFU) #define OCOTP_SRK4_BITS_SHIFT (0U) #define OCOTP_SRK4_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK4_BITS_SHIFT)) & OCOTP_SRK4_BITS_MASK) +/*! @} */ /*! @name SRK5 - Shadow Register for OTP Bank3 Word5 (SRK Hash) */ +/*! @{ */ #define OCOTP_SRK5_BITS_MASK (0xFFFFFFFFU) #define OCOTP_SRK5_BITS_SHIFT (0U) #define OCOTP_SRK5_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK5_BITS_SHIFT)) & OCOTP_SRK5_BITS_MASK) +/*! @} */ /*! @name SRK6 - Shadow Register for OTP Bank3 Word6 (SRK Hash) */ +/*! @{ */ #define OCOTP_SRK6_BITS_MASK (0xFFFFFFFFU) #define OCOTP_SRK6_BITS_SHIFT (0U) #define OCOTP_SRK6_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK6_BITS_SHIFT)) & OCOTP_SRK6_BITS_MASK) +/*! @} */ /*! @name SRK7 - Shadow Register for OTP Bank3 Word7 (SRK Hash) */ +/*! @{ */ #define OCOTP_SRK7_BITS_MASK (0xFFFFFFFFU) #define OCOTP_SRK7_BITS_SHIFT (0U) #define OCOTP_SRK7_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK7_BITS_SHIFT)) & OCOTP_SRK7_BITS_MASK) +/*! @} */ /*! @name SJC_RESP0 - Value of OTP Bank4 Word0 (Secure JTAG Response Field) */ +/*! @{ */ #define OCOTP_SJC_RESP0_BITS_MASK (0xFFFFFFFFU) #define OCOTP_SJC_RESP0_BITS_SHIFT (0U) #define OCOTP_SJC_RESP0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SJC_RESP0_BITS_SHIFT)) & OCOTP_SJC_RESP0_BITS_MASK) +/*! @} */ /*! @name SJC_RESP1 - Value of OTP Bank4 Word1 (Secure JTAG Response Field) */ +/*! @{ */ #define OCOTP_SJC_RESP1_BITS_MASK (0xFFFFFFFFU) #define OCOTP_SJC_RESP1_BITS_SHIFT (0U) #define OCOTP_SJC_RESP1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SJC_RESP1_BITS_SHIFT)) & OCOTP_SJC_RESP1_BITS_MASK) +/*! @} */ /*! @name MAC0 - Value of OTP Bank4 Word2 (MAC Address) */ +/*! @{ */ #define OCOTP_MAC0_BITS_MASK (0xFFFFFFFFU) #define OCOTP_MAC0_BITS_SHIFT (0U) #define OCOTP_MAC0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MAC0_BITS_SHIFT)) & OCOTP_MAC0_BITS_MASK) +/*! @} */ /*! @name MAC1 - Value of OTP Bank4 Word3 (MAC Address) */ +/*! @{ */ #define OCOTP_MAC1_BITS_MASK (0xFFFFFFFFU) #define OCOTP_MAC1_BITS_SHIFT (0U) #define OCOTP_MAC1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MAC1_BITS_SHIFT)) & OCOTP_MAC1_BITS_MASK) +/*! @} */ /*! @name GP3 - Value of OTP Bank4 Word4 (MAC Address) */ +/*! @{ */ #define OCOTP_GP3_BITS_MASK (0xFFFFFFFFU) #define OCOTP_GP3_BITS_SHIFT (0U) #define OCOTP_GP3_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_GP3_BITS_SHIFT)) & OCOTP_GP3_BITS_MASK) +/*! @} */ /*! @name GP1 - Value of OTP Bank4 Word6 (General Purpose Customer Defined Info) */ +/*! @{ */ #define OCOTP_GP1_BITS_MASK (0xFFFFFFFFU) #define OCOTP_GP1_BITS_SHIFT (0U) #define OCOTP_GP1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_GP1_BITS_SHIFT)) & OCOTP_GP1_BITS_MASK) +/*! @} */ /*! @name GP2 - Value of OTP Bank4 Word7 (General Purpose Customer Defined Info) */ +/*! @{ */ #define OCOTP_GP2_BITS_MASK (0xFFFFFFFFU) #define OCOTP_GP2_BITS_SHIFT (0U) #define OCOTP_GP2_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_GP2_BITS_SHIFT)) & OCOTP_GP2_BITS_MASK) +/*! @} */ /*! @name SW_GP1 - Value of OTP Bank5 Word0 (SW GP1) */ +/*! @{ */ #define OCOTP_SW_GP1_BITS_MASK (0xFFFFFFFFU) #define OCOTP_SW_GP1_BITS_SHIFT (0U) #define OCOTP_SW_GP1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_GP1_BITS_SHIFT)) & OCOTP_SW_GP1_BITS_MASK) +/*! @} */ /*! @name SW_GP20 - Value of OTP Bank5 Word1 (SW GP2) */ +/*! @{ */ #define OCOTP_SW_GP20_BITS_MASK (0xFFFFFFFFU) #define OCOTP_SW_GP20_BITS_SHIFT (0U) #define OCOTP_SW_GP20_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_GP20_BITS_SHIFT)) & OCOTP_SW_GP20_BITS_MASK) +/*! @} */ /*! @name SW_GP21 - Value of OTP Bank5 Word2 (SW GP2) */ +/*! @{ */ #define OCOTP_SW_GP21_BITS_MASK (0xFFFFFFFFU) #define OCOTP_SW_GP21_BITS_SHIFT (0U) #define OCOTP_SW_GP21_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_GP21_BITS_SHIFT)) & OCOTP_SW_GP21_BITS_MASK) +/*! @} */ /*! @name SW_GP22 - Value of OTP Bank5 Word3 (SW GP2) */ +/*! @{ */ #define OCOTP_SW_GP22_BITS_MASK (0xFFFFFFFFU) #define OCOTP_SW_GP22_BITS_SHIFT (0U) #define OCOTP_SW_GP22_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_GP22_BITS_SHIFT)) & OCOTP_SW_GP22_BITS_MASK) +/*! @} */ /*! @name SW_GP23 - Value of OTP Bank5 Word4 (SW GP2) */ +/*! @{ */ #define OCOTP_SW_GP23_BITS_MASK (0xFFFFFFFFU) #define OCOTP_SW_GP23_BITS_SHIFT (0U) #define OCOTP_SW_GP23_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_GP23_BITS_SHIFT)) & OCOTP_SW_GP23_BITS_MASK) +/*! @} */ /*! @name MISC_CONF0 - Value of OTP Bank5 Word5 (Misc Conf) */ +/*! @{ */ #define OCOTP_MISC_CONF0_BITS_MASK (0xFFFFFFFFU) #define OCOTP_MISC_CONF0_BITS_SHIFT (0U) #define OCOTP_MISC_CONF0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MISC_CONF0_BITS_SHIFT)) & OCOTP_MISC_CONF0_BITS_MASK) +/*! @} */ /*! @name MISC_CONF1 - Value of OTP Bank5 Word6 (Misc Conf) */ +/*! @{ */ #define OCOTP_MISC_CONF1_BITS_MASK (0xFFFFFFFFU) #define OCOTP_MISC_CONF1_BITS_SHIFT (0U) #define OCOTP_MISC_CONF1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MISC_CONF1_BITS_SHIFT)) & OCOTP_MISC_CONF1_BITS_MASK) +/*! @} */ /*! @name SRK_REVOKE - Value of OTP Bank5 Word7 (SRK Revoke) */ +/*! @{ */ #define OCOTP_SRK_REVOKE_BITS_MASK (0xFFFFFFFFU) #define OCOTP_SRK_REVOKE_BITS_SHIFT (0U) #define OCOTP_SRK_REVOKE_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK_REVOKE_BITS_SHIFT)) & OCOTP_SRK_REVOKE_BITS_MASK) +/*! @} */ /*! @@ -16062,56 +25484,88 @@ typedef struct { */ /*! @name MEGA_CTRL - PGC Mega Control Register */ +/*! @{ */ #define PGC_MEGA_CTRL_PCR_MASK (0x1U) #define PGC_MEGA_CTRL_PCR_SHIFT (0U) +/*! PCR + * 0b0..Do not switch off power even if pdn_req is asserted. + * 0b1..Switch off power when pdn_req is asserted. + */ #define PGC_MEGA_CTRL_PCR(x) (((uint32_t)(((uint32_t)(x)) << PGC_MEGA_CTRL_PCR_SHIFT)) & PGC_MEGA_CTRL_PCR_MASK) +/*! @} */ /*! @name MEGA_PUPSCR - PGC Mega Power Up Sequence Control Register */ +/*! @{ */ #define PGC_MEGA_PUPSCR_SW_MASK (0x3FU) #define PGC_MEGA_PUPSCR_SW_SHIFT (0U) #define PGC_MEGA_PUPSCR_SW(x) (((uint32_t)(((uint32_t)(x)) << PGC_MEGA_PUPSCR_SW_SHIFT)) & PGC_MEGA_PUPSCR_SW_MASK) #define PGC_MEGA_PUPSCR_SW2ISO_MASK (0x3F00U) #define PGC_MEGA_PUPSCR_SW2ISO_SHIFT (8U) #define PGC_MEGA_PUPSCR_SW2ISO(x) (((uint32_t)(((uint32_t)(x)) << PGC_MEGA_PUPSCR_SW2ISO_SHIFT)) & PGC_MEGA_PUPSCR_SW2ISO_MASK) +/*! @} */ /*! @name MEGA_PDNSCR - PGC Mega Pull Down Sequence Control Register */ +/*! @{ */ #define PGC_MEGA_PDNSCR_ISO_MASK (0x3FU) #define PGC_MEGA_PDNSCR_ISO_SHIFT (0U) #define PGC_MEGA_PDNSCR_ISO(x) (((uint32_t)(((uint32_t)(x)) << PGC_MEGA_PDNSCR_ISO_SHIFT)) & PGC_MEGA_PDNSCR_ISO_MASK) #define PGC_MEGA_PDNSCR_ISO2SW_MASK (0x3F00U) #define PGC_MEGA_PDNSCR_ISO2SW_SHIFT (8U) #define PGC_MEGA_PDNSCR_ISO2SW(x) (((uint32_t)(((uint32_t)(x)) << PGC_MEGA_PDNSCR_ISO2SW_SHIFT)) & PGC_MEGA_PDNSCR_ISO2SW_MASK) +/*! @} */ /*! @name MEGA_SR - PGC Mega Power Gating Controller Status Register */ +/*! @{ */ #define PGC_MEGA_SR_PSR_MASK (0x1U) #define PGC_MEGA_SR_PSR_SHIFT (0U) +/*! PSR + * 0b0..The target subsystem was not powered down for the previous power-down request. + * 0b1..The target subsystem was powered down for the previous power-down request. + */ #define PGC_MEGA_SR_PSR(x) (((uint32_t)(((uint32_t)(x)) << PGC_MEGA_SR_PSR_SHIFT)) & PGC_MEGA_SR_PSR_MASK) +/*! @} */ /*! @name CPU_CTRL - PGC CPU Control Register */ +/*! @{ */ #define PGC_CPU_CTRL_PCR_MASK (0x1U) #define PGC_CPU_CTRL_PCR_SHIFT (0U) +/*! PCR + * 0b0..Do not switch off power even if pdn_req is asserted. + * 0b1..Switch off power when pdn_req is asserted. + */ #define PGC_CPU_CTRL_PCR(x) (((uint32_t)(((uint32_t)(x)) << PGC_CPU_CTRL_PCR_SHIFT)) & PGC_CPU_CTRL_PCR_MASK) +/*! @} */ /*! @name CPU_PUPSCR - PGC CPU Power Up Sequence Control Register */ +/*! @{ */ #define PGC_CPU_PUPSCR_SW_MASK (0x3FU) #define PGC_CPU_PUPSCR_SW_SHIFT (0U) #define PGC_CPU_PUPSCR_SW(x) (((uint32_t)(((uint32_t)(x)) << PGC_CPU_PUPSCR_SW_SHIFT)) & PGC_CPU_PUPSCR_SW_MASK) #define PGC_CPU_PUPSCR_SW2ISO_MASK (0x3F00U) #define PGC_CPU_PUPSCR_SW2ISO_SHIFT (8U) #define PGC_CPU_PUPSCR_SW2ISO(x) (((uint32_t)(((uint32_t)(x)) << PGC_CPU_PUPSCR_SW2ISO_SHIFT)) & PGC_CPU_PUPSCR_SW2ISO_MASK) +/*! @} */ /*! @name CPU_PDNSCR - PGC CPU Pull Down Sequence Control Register */ +/*! @{ */ #define PGC_CPU_PDNSCR_ISO_MASK (0x3FU) #define PGC_CPU_PDNSCR_ISO_SHIFT (0U) #define PGC_CPU_PDNSCR_ISO(x) (((uint32_t)(((uint32_t)(x)) << PGC_CPU_PDNSCR_ISO_SHIFT)) & PGC_CPU_PDNSCR_ISO_MASK) #define PGC_CPU_PDNSCR_ISO2SW_MASK (0x3F00U) #define PGC_CPU_PDNSCR_ISO2SW_SHIFT (8U) #define PGC_CPU_PDNSCR_ISO2SW(x) (((uint32_t)(((uint32_t)(x)) << PGC_CPU_PDNSCR_ISO2SW_SHIFT)) & PGC_CPU_PDNSCR_ISO2SW_MASK) +/*! @} */ /*! @name CPU_SR - PGC CPU Power Gating Controller Status Register */ +/*! @{ */ #define PGC_CPU_SR_PSR_MASK (0x1U) #define PGC_CPU_SR_PSR_SHIFT (0U) +/*! PSR + * 0b0..The target subsystem was not powered down for the previous power-down request. + * 0b1..The target subsystem was powered down for the previous power-down request. + */ #define PGC_CPU_SR_PSR(x) (((uint32_t)(((uint32_t)(x)) << PGC_CPU_SR_PSR_SHIFT)) & PGC_CPU_SR_PSR_MASK) +/*! @} */ /*! @@ -16168,57 +25622,95 @@ typedef struct { */ /*! @name MCR - PIT Module Control Register */ +/*! @{ */ #define PIT_MCR_FRZ_MASK (0x1U) #define PIT_MCR_FRZ_SHIFT (0U) +/*! FRZ - Freeze + * 0b0..Timers continue to run in Debug mode. + * 0b1..Timers are stopped in Debug mode. + */ #define PIT_MCR_FRZ(x) (((uint32_t)(((uint32_t)(x)) << PIT_MCR_FRZ_SHIFT)) & PIT_MCR_FRZ_MASK) #define PIT_MCR_MDIS_MASK (0x2U) #define PIT_MCR_MDIS_SHIFT (1U) +/*! MDIS - Module Disable - (PIT section) + * 0b0..Clock for standard PIT timers is enabled. + * 0b1..Clock for standard PIT timers is disabled. + */ #define PIT_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << PIT_MCR_MDIS_SHIFT)) & PIT_MCR_MDIS_MASK) +/*! @} */ /*! @name LTMR64H - PIT Upper Lifetime Timer Register */ +/*! @{ */ #define PIT_LTMR64H_LTH_MASK (0xFFFFFFFFU) #define PIT_LTMR64H_LTH_SHIFT (0U) #define PIT_LTMR64H_LTH(x) (((uint32_t)(((uint32_t)(x)) << PIT_LTMR64H_LTH_SHIFT)) & PIT_LTMR64H_LTH_MASK) +/*! @} */ /*! @name LTMR64L - PIT Lower Lifetime Timer Register */ +/*! @{ */ #define PIT_LTMR64L_LTL_MASK (0xFFFFFFFFU) #define PIT_LTMR64L_LTL_SHIFT (0U) #define PIT_LTMR64L_LTL(x) (((uint32_t)(((uint32_t)(x)) << PIT_LTMR64L_LTL_SHIFT)) & PIT_LTMR64L_LTL_MASK) +/*! @} */ /*! @name LDVAL - Timer Load Value Register */ +/*! @{ */ #define PIT_LDVAL_TSV_MASK (0xFFFFFFFFU) #define PIT_LDVAL_TSV_SHIFT (0U) #define PIT_LDVAL_TSV(x) (((uint32_t)(((uint32_t)(x)) << PIT_LDVAL_TSV_SHIFT)) & PIT_LDVAL_TSV_MASK) +/*! @} */ /* The count of PIT_LDVAL */ #define PIT_LDVAL_COUNT (4U) /*! @name CVAL - Current Timer Value Register */ +/*! @{ */ #define PIT_CVAL_TVL_MASK (0xFFFFFFFFU) #define PIT_CVAL_TVL_SHIFT (0U) #define PIT_CVAL_TVL(x) (((uint32_t)(((uint32_t)(x)) << PIT_CVAL_TVL_SHIFT)) & PIT_CVAL_TVL_MASK) +/*! @} */ /* The count of PIT_CVAL */ #define PIT_CVAL_COUNT (4U) /*! @name TCTRL - Timer Control Register */ +/*! @{ */ #define PIT_TCTRL_TEN_MASK (0x1U) #define PIT_TCTRL_TEN_SHIFT (0U) +/*! TEN - Timer Enable + * 0b0..Timer n is disabled. + * 0b1..Timer n is enabled. + */ #define PIT_TCTRL_TEN(x) (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_TEN_SHIFT)) & PIT_TCTRL_TEN_MASK) #define PIT_TCTRL_TIE_MASK (0x2U) #define PIT_TCTRL_TIE_SHIFT (1U) +/*! TIE - Timer Interrupt Enable + * 0b0..Interrupt requests from Timer n are disabled. + * 0b1..Interrupt will be requested whenever TIF is set. + */ #define PIT_TCTRL_TIE(x) (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_TIE_SHIFT)) & PIT_TCTRL_TIE_MASK) #define PIT_TCTRL_CHN_MASK (0x4U) #define PIT_TCTRL_CHN_SHIFT (2U) +/*! CHN - Chain Mode + * 0b0..Timer is not chained. + * 0b1..Timer is chained to previous timer. For example, for Channel 2, if this field is set, Timer 2 is chained to Timer 1. + */ #define PIT_TCTRL_CHN(x) (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_CHN_SHIFT)) & PIT_TCTRL_CHN_MASK) +/*! @} */ /* The count of PIT_TCTRL */ #define PIT_TCTRL_COUNT (4U) /*! @name TFLG - Timer Flag Register */ +/*! @{ */ #define PIT_TFLG_TIF_MASK (0x1U) #define PIT_TFLG_TIF_SHIFT (0U) +/*! TIF - Timer Interrupt Flag + * 0b0..Timeout has not yet occurred. + * 0b1..Timeout has occurred. + */ #define PIT_TFLG_TIF(x) (((uint32_t)(((uint32_t)(x)) << PIT_TFLG_TIF_SHIFT)) & PIT_TFLG_TIF_MASK) +/*! @} */ /* The count of PIT_TFLG */ #define PIT_TFLG_COUNT (4U) @@ -16298,6 +25790,7 @@ typedef struct { */ /*! @name REG_1P1 - Regulator 1P1 Register */ +/*! @{ */ #define PMU_REG_1P1_ENABLE_LINREG_MASK (0x1U) #define PMU_REG_1P1_ENABLE_LINREG_SHIFT (0U) #define PMU_REG_1P1_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_ENABLE_LINREG_SHIFT)) & PMU_REG_1P1_ENABLE_LINREG_MASK) @@ -16315,6 +25808,11 @@ typedef struct { #define PMU_REG_1P1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_BO_OFFSET_SHIFT)) & PMU_REG_1P1_BO_OFFSET_MASK) #define PMU_REG_1P1_OUTPUT_TRG_MASK (0x1F00U) #define PMU_REG_1P1_OUTPUT_TRG_SHIFT (8U) +/*! OUTPUT_TRG + * 0b00100..0.8V + * 0b10000..1.1V + * 0b000x1..1.375V + */ #define PMU_REG_1P1_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_OUTPUT_TRG_SHIFT)) & PMU_REG_1P1_OUTPUT_TRG_MASK) #define PMU_REG_1P1_BO_VDD1P1_MASK (0x10000U) #define PMU_REG_1P1_BO_VDD1P1_SHIFT (16U) @@ -16327,9 +25825,15 @@ typedef struct { #define PMU_REG_1P1_ENABLE_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_ENABLE_WEAK_LINREG_SHIFT)) & PMU_REG_1P1_ENABLE_WEAK_LINREG_MASK) #define PMU_REG_1P1_SELREF_WEAK_LINREG_MASK (0x80000U) #define PMU_REG_1P1_SELREF_WEAK_LINREG_SHIFT (19U) +/*! SELREF_WEAK_LINREG + * 0b0..Weak-linreg output tracks low-power-bandgap voltage + * 0b1..Weak-linreg output tracks VDD_SOC_IN voltage + */ #define PMU_REG_1P1_SELREF_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SELREF_WEAK_LINREG_SHIFT)) & PMU_REG_1P1_SELREF_WEAK_LINREG_MASK) +/*! @} */ /*! @name REG_1P1_SET - Regulator 1P1 Register */ +/*! @{ */ #define PMU_REG_1P1_SET_ENABLE_LINREG_MASK (0x1U) #define PMU_REG_1P1_SET_ENABLE_LINREG_SHIFT (0U) #define PMU_REG_1P1_SET_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_ENABLE_LINREG_SHIFT)) & PMU_REG_1P1_SET_ENABLE_LINREG_MASK) @@ -16347,6 +25851,11 @@ typedef struct { #define PMU_REG_1P1_SET_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_BO_OFFSET_SHIFT)) & PMU_REG_1P1_SET_BO_OFFSET_MASK) #define PMU_REG_1P1_SET_OUTPUT_TRG_MASK (0x1F00U) #define PMU_REG_1P1_SET_OUTPUT_TRG_SHIFT (8U) +/*! OUTPUT_TRG + * 0b00100..0.8V + * 0b10000..1.1V + * 0b000x1..1.375V + */ #define PMU_REG_1P1_SET_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_OUTPUT_TRG_SHIFT)) & PMU_REG_1P1_SET_OUTPUT_TRG_MASK) #define PMU_REG_1P1_SET_BO_VDD1P1_MASK (0x10000U) #define PMU_REG_1P1_SET_BO_VDD1P1_SHIFT (16U) @@ -16359,9 +25868,15 @@ typedef struct { #define PMU_REG_1P1_SET_ENABLE_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_ENABLE_WEAK_LINREG_SHIFT)) & PMU_REG_1P1_SET_ENABLE_WEAK_LINREG_MASK) #define PMU_REG_1P1_SET_SELREF_WEAK_LINREG_MASK (0x80000U) #define PMU_REG_1P1_SET_SELREF_WEAK_LINREG_SHIFT (19U) +/*! SELREF_WEAK_LINREG + * 0b0..Weak-linreg output tracks low-power-bandgap voltage + * 0b1..Weak-linreg output tracks VDD_SOC_IN voltage + */ #define PMU_REG_1P1_SET_SELREF_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_SELREF_WEAK_LINREG_SHIFT)) & PMU_REG_1P1_SET_SELREF_WEAK_LINREG_MASK) +/*! @} */ /*! @name REG_1P1_CLR - Regulator 1P1 Register */ +/*! @{ */ #define PMU_REG_1P1_CLR_ENABLE_LINREG_MASK (0x1U) #define PMU_REG_1P1_CLR_ENABLE_LINREG_SHIFT (0U) #define PMU_REG_1P1_CLR_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_ENABLE_LINREG_SHIFT)) & PMU_REG_1P1_CLR_ENABLE_LINREG_MASK) @@ -16379,6 +25894,11 @@ typedef struct { #define PMU_REG_1P1_CLR_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_BO_OFFSET_SHIFT)) & PMU_REG_1P1_CLR_BO_OFFSET_MASK) #define PMU_REG_1P1_CLR_OUTPUT_TRG_MASK (0x1F00U) #define PMU_REG_1P1_CLR_OUTPUT_TRG_SHIFT (8U) +/*! OUTPUT_TRG + * 0b00100..0.8V + * 0b10000..1.1V + * 0b000x1..1.375V + */ #define PMU_REG_1P1_CLR_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_OUTPUT_TRG_SHIFT)) & PMU_REG_1P1_CLR_OUTPUT_TRG_MASK) #define PMU_REG_1P1_CLR_BO_VDD1P1_MASK (0x10000U) #define PMU_REG_1P1_CLR_BO_VDD1P1_SHIFT (16U) @@ -16391,9 +25911,15 @@ typedef struct { #define PMU_REG_1P1_CLR_ENABLE_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_ENABLE_WEAK_LINREG_SHIFT)) & PMU_REG_1P1_CLR_ENABLE_WEAK_LINREG_MASK) #define PMU_REG_1P1_CLR_SELREF_WEAK_LINREG_MASK (0x80000U) #define PMU_REG_1P1_CLR_SELREF_WEAK_LINREG_SHIFT (19U) +/*! SELREF_WEAK_LINREG + * 0b0..Weak-linreg output tracks low-power-bandgap voltage + * 0b1..Weak-linreg output tracks VDD_SOC_IN voltage + */ #define PMU_REG_1P1_CLR_SELREF_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_SELREF_WEAK_LINREG_SHIFT)) & PMU_REG_1P1_CLR_SELREF_WEAK_LINREG_MASK) +/*! @} */ /*! @name REG_1P1_TOG - Regulator 1P1 Register */ +/*! @{ */ #define PMU_REG_1P1_TOG_ENABLE_LINREG_MASK (0x1U) #define PMU_REG_1P1_TOG_ENABLE_LINREG_SHIFT (0U) #define PMU_REG_1P1_TOG_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_ENABLE_LINREG_SHIFT)) & PMU_REG_1P1_TOG_ENABLE_LINREG_MASK) @@ -16411,6 +25937,11 @@ typedef struct { #define PMU_REG_1P1_TOG_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_BO_OFFSET_SHIFT)) & PMU_REG_1P1_TOG_BO_OFFSET_MASK) #define PMU_REG_1P1_TOG_OUTPUT_TRG_MASK (0x1F00U) #define PMU_REG_1P1_TOG_OUTPUT_TRG_SHIFT (8U) +/*! OUTPUT_TRG + * 0b00100..0.8V + * 0b10000..1.1V + * 0b000x1..1.375V + */ #define PMU_REG_1P1_TOG_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_OUTPUT_TRG_SHIFT)) & PMU_REG_1P1_TOG_OUTPUT_TRG_MASK) #define PMU_REG_1P1_TOG_BO_VDD1P1_MASK (0x10000U) #define PMU_REG_1P1_TOG_BO_VDD1P1_SHIFT (16U) @@ -16423,9 +25954,15 @@ typedef struct { #define PMU_REG_1P1_TOG_ENABLE_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_ENABLE_WEAK_LINREG_SHIFT)) & PMU_REG_1P1_TOG_ENABLE_WEAK_LINREG_MASK) #define PMU_REG_1P1_TOG_SELREF_WEAK_LINREG_MASK (0x80000U) #define PMU_REG_1P1_TOG_SELREF_WEAK_LINREG_SHIFT (19U) +/*! SELREF_WEAK_LINREG + * 0b0..Weak-linreg output tracks low-power-bandgap voltage + * 0b1..Weak-linreg output tracks VDD_SOC_IN voltage + */ #define PMU_REG_1P1_TOG_SELREF_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_SELREF_WEAK_LINREG_SHIFT)) & PMU_REG_1P1_TOG_SELREF_WEAK_LINREG_MASK) +/*! @} */ /*! @name REG_3P0 - Regulator 3P0 Register */ +/*! @{ */ #define PMU_REG_3P0_ENABLE_LINREG_MASK (0x1U) #define PMU_REG_3P0_ENABLE_LINREG_SHIFT (0U) #define PMU_REG_3P0_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_ENABLE_LINREG_SHIFT)) & PMU_REG_3P0_ENABLE_LINREG_MASK) @@ -16440,9 +25977,18 @@ typedef struct { #define PMU_REG_3P0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_BO_OFFSET_SHIFT)) & PMU_REG_3P0_BO_OFFSET_MASK) #define PMU_REG_3P0_VBUS_SEL_MASK (0x80U) #define PMU_REG_3P0_VBUS_SEL_SHIFT (7U) +/*! VBUS_SEL + * 0b1..Utilize VBUS OTG1 power + * 0b0..Utilize VBUS OTG2 power + */ #define PMU_REG_3P0_VBUS_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_VBUS_SEL_SHIFT)) & PMU_REG_3P0_VBUS_SEL_MASK) #define PMU_REG_3P0_OUTPUT_TRG_MASK (0x1F00U) #define PMU_REG_3P0_OUTPUT_TRG_SHIFT (8U) +/*! OUTPUT_TRG + * 0b00000..2.625V + * 0b01111..3.000V + * 0b11111..3.400V + */ #define PMU_REG_3P0_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_OUTPUT_TRG_SHIFT)) & PMU_REG_3P0_OUTPUT_TRG_MASK) #define PMU_REG_3P0_BO_VDD3P0_MASK (0x10000U) #define PMU_REG_3P0_BO_VDD3P0_SHIFT (16U) @@ -16450,8 +25996,10 @@ typedef struct { #define PMU_REG_3P0_OK_VDD3P0_MASK (0x20000U) #define PMU_REG_3P0_OK_VDD3P0_SHIFT (17U) #define PMU_REG_3P0_OK_VDD3P0(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_OK_VDD3P0_SHIFT)) & PMU_REG_3P0_OK_VDD3P0_MASK) +/*! @} */ /*! @name REG_3P0_SET - Regulator 3P0 Register */ +/*! @{ */ #define PMU_REG_3P0_SET_ENABLE_LINREG_MASK (0x1U) #define PMU_REG_3P0_SET_ENABLE_LINREG_SHIFT (0U) #define PMU_REG_3P0_SET_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_SET_ENABLE_LINREG_SHIFT)) & PMU_REG_3P0_SET_ENABLE_LINREG_MASK) @@ -16466,9 +26014,18 @@ typedef struct { #define PMU_REG_3P0_SET_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_SET_BO_OFFSET_SHIFT)) & PMU_REG_3P0_SET_BO_OFFSET_MASK) #define PMU_REG_3P0_SET_VBUS_SEL_MASK (0x80U) #define PMU_REG_3P0_SET_VBUS_SEL_SHIFT (7U) +/*! VBUS_SEL + * 0b1..Utilize VBUS OTG1 power + * 0b0..Utilize VBUS OTG2 power + */ #define PMU_REG_3P0_SET_VBUS_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_SET_VBUS_SEL_SHIFT)) & PMU_REG_3P0_SET_VBUS_SEL_MASK) #define PMU_REG_3P0_SET_OUTPUT_TRG_MASK (0x1F00U) #define PMU_REG_3P0_SET_OUTPUT_TRG_SHIFT (8U) +/*! OUTPUT_TRG + * 0b00000..2.625V + * 0b01111..3.000V + * 0b11111..3.400V + */ #define PMU_REG_3P0_SET_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_SET_OUTPUT_TRG_SHIFT)) & PMU_REG_3P0_SET_OUTPUT_TRG_MASK) #define PMU_REG_3P0_SET_BO_VDD3P0_MASK (0x10000U) #define PMU_REG_3P0_SET_BO_VDD3P0_SHIFT (16U) @@ -16476,8 +26033,10 @@ typedef struct { #define PMU_REG_3P0_SET_OK_VDD3P0_MASK (0x20000U) #define PMU_REG_3P0_SET_OK_VDD3P0_SHIFT (17U) #define PMU_REG_3P0_SET_OK_VDD3P0(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_SET_OK_VDD3P0_SHIFT)) & PMU_REG_3P0_SET_OK_VDD3P0_MASK) +/*! @} */ /*! @name REG_3P0_CLR - Regulator 3P0 Register */ +/*! @{ */ #define PMU_REG_3P0_CLR_ENABLE_LINREG_MASK (0x1U) #define PMU_REG_3P0_CLR_ENABLE_LINREG_SHIFT (0U) #define PMU_REG_3P0_CLR_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_CLR_ENABLE_LINREG_SHIFT)) & PMU_REG_3P0_CLR_ENABLE_LINREG_MASK) @@ -16492,9 +26051,18 @@ typedef struct { #define PMU_REG_3P0_CLR_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_CLR_BO_OFFSET_SHIFT)) & PMU_REG_3P0_CLR_BO_OFFSET_MASK) #define PMU_REG_3P0_CLR_VBUS_SEL_MASK (0x80U) #define PMU_REG_3P0_CLR_VBUS_SEL_SHIFT (7U) +/*! VBUS_SEL + * 0b1..Utilize VBUS OTG1 power + * 0b0..Utilize VBUS OTG2 power + */ #define PMU_REG_3P0_CLR_VBUS_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_CLR_VBUS_SEL_SHIFT)) & PMU_REG_3P0_CLR_VBUS_SEL_MASK) #define PMU_REG_3P0_CLR_OUTPUT_TRG_MASK (0x1F00U) #define PMU_REG_3P0_CLR_OUTPUT_TRG_SHIFT (8U) +/*! OUTPUT_TRG + * 0b00000..2.625V + * 0b01111..3.000V + * 0b11111..3.400V + */ #define PMU_REG_3P0_CLR_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_CLR_OUTPUT_TRG_SHIFT)) & PMU_REG_3P0_CLR_OUTPUT_TRG_MASK) #define PMU_REG_3P0_CLR_BO_VDD3P0_MASK (0x10000U) #define PMU_REG_3P0_CLR_BO_VDD3P0_SHIFT (16U) @@ -16502,8 +26070,10 @@ typedef struct { #define PMU_REG_3P0_CLR_OK_VDD3P0_MASK (0x20000U) #define PMU_REG_3P0_CLR_OK_VDD3P0_SHIFT (17U) #define PMU_REG_3P0_CLR_OK_VDD3P0(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_CLR_OK_VDD3P0_SHIFT)) & PMU_REG_3P0_CLR_OK_VDD3P0_MASK) +/*! @} */ /*! @name REG_3P0_TOG - Regulator 3P0 Register */ +/*! @{ */ #define PMU_REG_3P0_TOG_ENABLE_LINREG_MASK (0x1U) #define PMU_REG_3P0_TOG_ENABLE_LINREG_SHIFT (0U) #define PMU_REG_3P0_TOG_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_TOG_ENABLE_LINREG_SHIFT)) & PMU_REG_3P0_TOG_ENABLE_LINREG_MASK) @@ -16518,9 +26088,18 @@ typedef struct { #define PMU_REG_3P0_TOG_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_TOG_BO_OFFSET_SHIFT)) & PMU_REG_3P0_TOG_BO_OFFSET_MASK) #define PMU_REG_3P0_TOG_VBUS_SEL_MASK (0x80U) #define PMU_REG_3P0_TOG_VBUS_SEL_SHIFT (7U) +/*! VBUS_SEL + * 0b1..Utilize VBUS OTG1 power + * 0b0..Utilize VBUS OTG2 power + */ #define PMU_REG_3P0_TOG_VBUS_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_TOG_VBUS_SEL_SHIFT)) & PMU_REG_3P0_TOG_VBUS_SEL_MASK) #define PMU_REG_3P0_TOG_OUTPUT_TRG_MASK (0x1F00U) #define PMU_REG_3P0_TOG_OUTPUT_TRG_SHIFT (8U) +/*! OUTPUT_TRG + * 0b00000..2.625V + * 0b01111..3.000V + * 0b11111..3.400V + */ #define PMU_REG_3P0_TOG_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_TOG_OUTPUT_TRG_SHIFT)) & PMU_REG_3P0_TOG_OUTPUT_TRG_MASK) #define PMU_REG_3P0_TOG_BO_VDD3P0_MASK (0x10000U) #define PMU_REG_3P0_TOG_BO_VDD3P0_SHIFT (16U) @@ -16528,8 +26107,10 @@ typedef struct { #define PMU_REG_3P0_TOG_OK_VDD3P0_MASK (0x20000U) #define PMU_REG_3P0_TOG_OK_VDD3P0_SHIFT (17U) #define PMU_REG_3P0_TOG_OK_VDD3P0(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_TOG_OK_VDD3P0_SHIFT)) & PMU_REG_3P0_TOG_OK_VDD3P0_MASK) +/*! @} */ /*! @name REG_2P5 - Regulator 2P5 Register */ +/*! @{ */ #define PMU_REG_2P5_ENABLE_LINREG_MASK (0x1U) #define PMU_REG_2P5_ENABLE_LINREG_SHIFT (0U) #define PMU_REG_2P5_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_ENABLE_LINREG_SHIFT)) & PMU_REG_2P5_ENABLE_LINREG_MASK) @@ -16547,6 +26128,11 @@ typedef struct { #define PMU_REG_2P5_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_BO_OFFSET_SHIFT)) & PMU_REG_2P5_BO_OFFSET_MASK) #define PMU_REG_2P5_OUTPUT_TRG_MASK (0x1F00U) #define PMU_REG_2P5_OUTPUT_TRG_SHIFT (8U) +/*! OUTPUT_TRG + * 0b00000..2.10V + * 0b10000..2.50V + * 0b11111..2.875V + */ #define PMU_REG_2P5_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_OUTPUT_TRG_SHIFT)) & PMU_REG_2P5_OUTPUT_TRG_MASK) #define PMU_REG_2P5_BO_VDD2P5_MASK (0x10000U) #define PMU_REG_2P5_BO_VDD2P5_SHIFT (16U) @@ -16557,8 +26143,10 @@ typedef struct { #define PMU_REG_2P5_ENABLE_WEAK_LINREG_MASK (0x40000U) #define PMU_REG_2P5_ENABLE_WEAK_LINREG_SHIFT (18U) #define PMU_REG_2P5_ENABLE_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_ENABLE_WEAK_LINREG_SHIFT)) & PMU_REG_2P5_ENABLE_WEAK_LINREG_MASK) +/*! @} */ /*! @name REG_2P5_SET - Regulator 2P5 Register */ +/*! @{ */ #define PMU_REG_2P5_SET_ENABLE_LINREG_MASK (0x1U) #define PMU_REG_2P5_SET_ENABLE_LINREG_SHIFT (0U) #define PMU_REG_2P5_SET_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_SET_ENABLE_LINREG_SHIFT)) & PMU_REG_2P5_SET_ENABLE_LINREG_MASK) @@ -16576,6 +26164,11 @@ typedef struct { #define PMU_REG_2P5_SET_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_SET_BO_OFFSET_SHIFT)) & PMU_REG_2P5_SET_BO_OFFSET_MASK) #define PMU_REG_2P5_SET_OUTPUT_TRG_MASK (0x1F00U) #define PMU_REG_2P5_SET_OUTPUT_TRG_SHIFT (8U) +/*! OUTPUT_TRG + * 0b00000..2.10V + * 0b10000..2.50V + * 0b11111..2.875V + */ #define PMU_REG_2P5_SET_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_SET_OUTPUT_TRG_SHIFT)) & PMU_REG_2P5_SET_OUTPUT_TRG_MASK) #define PMU_REG_2P5_SET_BO_VDD2P5_MASK (0x10000U) #define PMU_REG_2P5_SET_BO_VDD2P5_SHIFT (16U) @@ -16586,8 +26179,10 @@ typedef struct { #define PMU_REG_2P5_SET_ENABLE_WEAK_LINREG_MASK (0x40000U) #define PMU_REG_2P5_SET_ENABLE_WEAK_LINREG_SHIFT (18U) #define PMU_REG_2P5_SET_ENABLE_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_SET_ENABLE_WEAK_LINREG_SHIFT)) & PMU_REG_2P5_SET_ENABLE_WEAK_LINREG_MASK) +/*! @} */ /*! @name REG_2P5_CLR - Regulator 2P5 Register */ +/*! @{ */ #define PMU_REG_2P5_CLR_ENABLE_LINREG_MASK (0x1U) #define PMU_REG_2P5_CLR_ENABLE_LINREG_SHIFT (0U) #define PMU_REG_2P5_CLR_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_CLR_ENABLE_LINREG_SHIFT)) & PMU_REG_2P5_CLR_ENABLE_LINREG_MASK) @@ -16605,6 +26200,11 @@ typedef struct { #define PMU_REG_2P5_CLR_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_CLR_BO_OFFSET_SHIFT)) & PMU_REG_2P5_CLR_BO_OFFSET_MASK) #define PMU_REG_2P5_CLR_OUTPUT_TRG_MASK (0x1F00U) #define PMU_REG_2P5_CLR_OUTPUT_TRG_SHIFT (8U) +/*! OUTPUT_TRG + * 0b00000..2.10V + * 0b10000..2.50V + * 0b11111..2.875V + */ #define PMU_REG_2P5_CLR_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_CLR_OUTPUT_TRG_SHIFT)) & PMU_REG_2P5_CLR_OUTPUT_TRG_MASK) #define PMU_REG_2P5_CLR_BO_VDD2P5_MASK (0x10000U) #define PMU_REG_2P5_CLR_BO_VDD2P5_SHIFT (16U) @@ -16615,8 +26215,10 @@ typedef struct { #define PMU_REG_2P5_CLR_ENABLE_WEAK_LINREG_MASK (0x40000U) #define PMU_REG_2P5_CLR_ENABLE_WEAK_LINREG_SHIFT (18U) #define PMU_REG_2P5_CLR_ENABLE_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_CLR_ENABLE_WEAK_LINREG_SHIFT)) & PMU_REG_2P5_CLR_ENABLE_WEAK_LINREG_MASK) +/*! @} */ /*! @name REG_2P5_TOG - Regulator 2P5 Register */ +/*! @{ */ #define PMU_REG_2P5_TOG_ENABLE_LINREG_MASK (0x1U) #define PMU_REG_2P5_TOG_ENABLE_LINREG_SHIFT (0U) #define PMU_REG_2P5_TOG_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_TOG_ENABLE_LINREG_SHIFT)) & PMU_REG_2P5_TOG_ENABLE_LINREG_MASK) @@ -16634,6 +26236,11 @@ typedef struct { #define PMU_REG_2P5_TOG_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_TOG_BO_OFFSET_SHIFT)) & PMU_REG_2P5_TOG_BO_OFFSET_MASK) #define PMU_REG_2P5_TOG_OUTPUT_TRG_MASK (0x1F00U) #define PMU_REG_2P5_TOG_OUTPUT_TRG_SHIFT (8U) +/*! OUTPUT_TRG + * 0b00000..2.10V + * 0b10000..2.50V + * 0b11111..2.875V + */ #define PMU_REG_2P5_TOG_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_TOG_OUTPUT_TRG_SHIFT)) & PMU_REG_2P5_TOG_OUTPUT_TRG_MASK) #define PMU_REG_2P5_TOG_BO_VDD2P5_MASK (0x10000U) #define PMU_REG_2P5_TOG_BO_VDD2P5_SHIFT (16U) @@ -16644,84 +26251,520 @@ typedef struct { #define PMU_REG_2P5_TOG_ENABLE_WEAK_LINREG_MASK (0x40000U) #define PMU_REG_2P5_TOG_ENABLE_WEAK_LINREG_SHIFT (18U) #define PMU_REG_2P5_TOG_ENABLE_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_TOG_ENABLE_WEAK_LINREG_SHIFT)) & PMU_REG_2P5_TOG_ENABLE_WEAK_LINREG_MASK) +/*! @} */ /*! @name REG_CORE - Digital Regulator Core Register */ +/*! @{ */ #define PMU_REG_CORE_REG0_TARG_MASK (0x1FU) #define PMU_REG_CORE_REG0_TARG_SHIFT (0U) +/*! REG0_TARG + * 0b00000..Power gated off + * 0b00001..Target core voltage = 0.725V + * 0b00010..Target core voltage = 0.750V + * 0b00011..Target core voltage = 0.775V + * 0b10000..Target core voltage = 1.100V + * 0b11110..Target core voltage = 1.450V + * 0b11111..Power FET switched full on. No regulation. + */ #define PMU_REG_CORE_REG0_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_REG0_TARG_SHIFT)) & PMU_REG_CORE_REG0_TARG_MASK) +#define PMU_REG_CORE_REG0_ADJ_MASK (0x1E0U) +#define PMU_REG_CORE_REG0_ADJ_SHIFT (5U) +/*! REG0_ADJ - This bit field defines the adjustment bits to calibrate the target value of Reg0. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register. + * 0b0000..No adjustment + * 0b0001..+ 0.25% + * 0b0010..+ 0.50% + * 0b0011..+ 0.75% + * 0b0100..+ 1.00% + * 0b0101..+ 1.25% + * 0b0110..+ 1.50% + * 0b0111..+ 1.75% + * 0b1000..- 0.25% + * 0b1001..- 0.50% + * 0b1010..- 0.75% + * 0b1011..- 1.00% + * 0b1100..- 1.25% + * 0b1101..- 1.50% + * 0b1110..- 1.75% + * 0b1111..- 2.00% + */ +#define PMU_REG_CORE_REG0_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_REG0_ADJ_SHIFT)) & PMU_REG_CORE_REG0_ADJ_MASK) +#define PMU_REG_CORE_REG1_TARG_MASK (0x3E00U) +#define PMU_REG_CORE_REG1_TARG_SHIFT (9U) +/*! REG1_TARG - This bit field defines the target voltage for the vpu/gpu power domain. Single bit increments reflect 25mV core voltage steps. Not all steps will make sense to use either because of input supply limitations or load operation. + * 0b00000..Power gated off + * 0b00001..Target core voltage = 0.725V + * 0b00010..Target core voltage = 0.750V + * 0b00011..Target core voltage = 0.775V + * 0b10000..Target core voltage = 1.100V + * 0b11110..Target core voltage = 1.450V + * 0b11111..Power FET switched full on. No regulation. + */ +#define PMU_REG_CORE_REG1_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_REG1_TARG_SHIFT)) & PMU_REG_CORE_REG1_TARG_MASK) +#define PMU_REG_CORE_REG1_ADJ_MASK (0x3C000U) +#define PMU_REG_CORE_REG1_ADJ_SHIFT (14U) +/*! REG1_ADJ - This bit field defines the adjustment bits to calibrate the target value of Reg1. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register. + * 0b0000..No adjustment + * 0b0001..+ 0.25% + * 0b0010..+ 0.50% + * 0b0011..+ 0.75% + * 0b0100..+ 1.00% + * 0b0101..+ 1.25% + * 0b0110..+ 1.50% + * 0b0111..+ 1.75% + * 0b1000..- 0.25% + * 0b1001..- 0.50% + * 0b1010..- 0.75% + * 0b1011..- 1.00% + * 0b1100..- 1.25% + * 0b1101..- 1.50% + * 0b1110..- 1.75% + * 0b1111..- 2.00% + */ +#define PMU_REG_CORE_REG1_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_REG1_ADJ_SHIFT)) & PMU_REG_CORE_REG1_ADJ_MASK) #define PMU_REG_CORE_REG2_TARG_MASK (0x7C0000U) #define PMU_REG_CORE_REG2_TARG_SHIFT (18U) +/*! REG2_TARG + * 0b00000..Power gated off + * 0b00001..Target core voltage = 0.725V + * 0b00010..Target core voltage = 0.750V + * 0b00011..Target core voltage = 0.775V + * 0b10000..Target core voltage = 1.100V + * 0b11110..Target core voltage = 1.450V + * 0b11111..Power FET switched full on. No regulation. + */ #define PMU_REG_CORE_REG2_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_REG2_TARG_SHIFT)) & PMU_REG_CORE_REG2_TARG_MASK) +#define PMU_REG_CORE_REG2_ADJ_MASK (0x7800000U) +#define PMU_REG_CORE_REG2_ADJ_SHIFT (23U) +/*! REG2_ADJ - This bit field defines the adjustment bits to calibrate the target value of Reg2. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register. + * 0b0000..No adjustment + * 0b0001..+ 0.25% + * 0b0010..+ 0.50% + * 0b0011..+ 0.75% + * 0b0100..+ 1.00% + * 0b0101..+ 1.25% + * 0b0110..+ 1.50% + * 0b0111..+ 1.75% + * 0b1000..- 0.25% + * 0b1001..- 0.50% + * 0b1010..- 0.75% + * 0b1011..- 1.00% + * 0b1100..- 1.25% + * 0b1101..- 1.50% + * 0b1110..- 1.75% + * 0b1111..- 2.00% + */ +#define PMU_REG_CORE_REG2_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_REG2_ADJ_SHIFT)) & PMU_REG_CORE_REG2_ADJ_MASK) #define PMU_REG_CORE_RAMP_RATE_MASK (0x18000000U) #define PMU_REG_CORE_RAMP_RATE_SHIFT (27U) +/*! RAMP_RATE + * 0b00..Fast + * 0b01..Medium Fast + * 0b10..Medium Slow + * 0b11..Slow + */ #define PMU_REG_CORE_RAMP_RATE(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_RAMP_RATE_SHIFT)) & PMU_REG_CORE_RAMP_RATE_MASK) #define PMU_REG_CORE_FET_ODRIVE_MASK (0x20000000U) #define PMU_REG_CORE_FET_ODRIVE_SHIFT (29U) #define PMU_REG_CORE_FET_ODRIVE(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_FET_ODRIVE_SHIFT)) & PMU_REG_CORE_FET_ODRIVE_MASK) +/*! @} */ /*! @name REG_CORE_SET - Digital Regulator Core Register */ +/*! @{ */ #define PMU_REG_CORE_SET_REG0_TARG_MASK (0x1FU) #define PMU_REG_CORE_SET_REG0_TARG_SHIFT (0U) +/*! REG0_TARG + * 0b00000..Power gated off + * 0b00001..Target core voltage = 0.725V + * 0b00010..Target core voltage = 0.750V + * 0b00011..Target core voltage = 0.775V + * 0b10000..Target core voltage = 1.100V + * 0b11110..Target core voltage = 1.450V + * 0b11111..Power FET switched full on. No regulation. + */ #define PMU_REG_CORE_SET_REG0_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_SET_REG0_TARG_SHIFT)) & PMU_REG_CORE_SET_REG0_TARG_MASK) +#define PMU_REG_CORE_SET_REG0_ADJ_MASK (0x1E0U) +#define PMU_REG_CORE_SET_REG0_ADJ_SHIFT (5U) +/*! REG0_ADJ - This bit field defines the adjustment bits to calibrate the target value of Reg0. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register. + * 0b0000..No adjustment + * 0b0001..+ 0.25% + * 0b0010..+ 0.50% + * 0b0011..+ 0.75% + * 0b0100..+ 1.00% + * 0b0101..+ 1.25% + * 0b0110..+ 1.50% + * 0b0111..+ 1.75% + * 0b1000..- 0.25% + * 0b1001..- 0.50% + * 0b1010..- 0.75% + * 0b1011..- 1.00% + * 0b1100..- 1.25% + * 0b1101..- 1.50% + * 0b1110..- 1.75% + * 0b1111..- 2.00% + */ +#define PMU_REG_CORE_SET_REG0_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_SET_REG0_ADJ_SHIFT)) & PMU_REG_CORE_SET_REG0_ADJ_MASK) +#define PMU_REG_CORE_SET_REG1_TARG_MASK (0x3E00U) +#define PMU_REG_CORE_SET_REG1_TARG_SHIFT (9U) +/*! REG1_TARG - This bit field defines the target voltage for the vpu/gpu power domain. Single bit increments reflect 25mV core voltage steps. Not all steps will make sense to use either because of input supply limitations or load operation. + * 0b00000..Power gated off + * 0b00001..Target core voltage = 0.725V + * 0b00010..Target core voltage = 0.750V + * 0b00011..Target core voltage = 0.775V + * 0b10000..Target core voltage = 1.100V + * 0b11110..Target core voltage = 1.450V + * 0b11111..Power FET switched full on. No regulation. + */ +#define PMU_REG_CORE_SET_REG1_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_SET_REG1_TARG_SHIFT)) & PMU_REG_CORE_SET_REG1_TARG_MASK) +#define PMU_REG_CORE_SET_REG1_ADJ_MASK (0x3C000U) +#define PMU_REG_CORE_SET_REG1_ADJ_SHIFT (14U) +/*! REG1_ADJ - This bit field defines the adjustment bits to calibrate the target value of Reg1. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register. + * 0b0000..No adjustment + * 0b0001..+ 0.25% + * 0b0010..+ 0.50% + * 0b0011..+ 0.75% + * 0b0100..+ 1.00% + * 0b0101..+ 1.25% + * 0b0110..+ 1.50% + * 0b0111..+ 1.75% + * 0b1000..- 0.25% + * 0b1001..- 0.50% + * 0b1010..- 0.75% + * 0b1011..- 1.00% + * 0b1100..- 1.25% + * 0b1101..- 1.50% + * 0b1110..- 1.75% + * 0b1111..- 2.00% + */ +#define PMU_REG_CORE_SET_REG1_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_SET_REG1_ADJ_SHIFT)) & PMU_REG_CORE_SET_REG1_ADJ_MASK) #define PMU_REG_CORE_SET_REG2_TARG_MASK (0x7C0000U) #define PMU_REG_CORE_SET_REG2_TARG_SHIFT (18U) +/*! REG2_TARG + * 0b00000..Power gated off + * 0b00001..Target core voltage = 0.725V + * 0b00010..Target core voltage = 0.750V + * 0b00011..Target core voltage = 0.775V + * 0b10000..Target core voltage = 1.100V + * 0b11110..Target core voltage = 1.450V + * 0b11111..Power FET switched full on. No regulation. + */ #define PMU_REG_CORE_SET_REG2_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_SET_REG2_TARG_SHIFT)) & PMU_REG_CORE_SET_REG2_TARG_MASK) +#define PMU_REG_CORE_SET_REG2_ADJ_MASK (0x7800000U) +#define PMU_REG_CORE_SET_REG2_ADJ_SHIFT (23U) +/*! REG2_ADJ - This bit field defines the adjustment bits to calibrate the target value of Reg2. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register. + * 0b0000..No adjustment + * 0b0001..+ 0.25% + * 0b0010..+ 0.50% + * 0b0011..+ 0.75% + * 0b0100..+ 1.00% + * 0b0101..+ 1.25% + * 0b0110..+ 1.50% + * 0b0111..+ 1.75% + * 0b1000..- 0.25% + * 0b1001..- 0.50% + * 0b1010..- 0.75% + * 0b1011..- 1.00% + * 0b1100..- 1.25% + * 0b1101..- 1.50% + * 0b1110..- 1.75% + * 0b1111..- 2.00% + */ +#define PMU_REG_CORE_SET_REG2_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_SET_REG2_ADJ_SHIFT)) & PMU_REG_CORE_SET_REG2_ADJ_MASK) #define PMU_REG_CORE_SET_RAMP_RATE_MASK (0x18000000U) #define PMU_REG_CORE_SET_RAMP_RATE_SHIFT (27U) +/*! RAMP_RATE + * 0b00..Fast + * 0b01..Medium Fast + * 0b10..Medium Slow + * 0b11..Slow + */ #define PMU_REG_CORE_SET_RAMP_RATE(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_SET_RAMP_RATE_SHIFT)) & PMU_REG_CORE_SET_RAMP_RATE_MASK) #define PMU_REG_CORE_SET_FET_ODRIVE_MASK (0x20000000U) #define PMU_REG_CORE_SET_FET_ODRIVE_SHIFT (29U) #define PMU_REG_CORE_SET_FET_ODRIVE(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_SET_FET_ODRIVE_SHIFT)) & PMU_REG_CORE_SET_FET_ODRIVE_MASK) +/*! @} */ /*! @name REG_CORE_CLR - Digital Regulator Core Register */ +/*! @{ */ #define PMU_REG_CORE_CLR_REG0_TARG_MASK (0x1FU) #define PMU_REG_CORE_CLR_REG0_TARG_SHIFT (0U) +/*! REG0_TARG + * 0b00000..Power gated off + * 0b00001..Target core voltage = 0.725V + * 0b00010..Target core voltage = 0.750V + * 0b00011..Target core voltage = 0.775V + * 0b10000..Target core voltage = 1.100V + * 0b11110..Target core voltage = 1.450V + * 0b11111..Power FET switched full on. No regulation. + */ #define PMU_REG_CORE_CLR_REG0_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_CLR_REG0_TARG_SHIFT)) & PMU_REG_CORE_CLR_REG0_TARG_MASK) +#define PMU_REG_CORE_CLR_REG0_ADJ_MASK (0x1E0U) +#define PMU_REG_CORE_CLR_REG0_ADJ_SHIFT (5U) +/*! REG0_ADJ - This bit field defines the adjustment bits to calibrate the target value of Reg0. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register. + * 0b0000..No adjustment + * 0b0001..+ 0.25% + * 0b0010..+ 0.50% + * 0b0011..+ 0.75% + * 0b0100..+ 1.00% + * 0b0101..+ 1.25% + * 0b0110..+ 1.50% + * 0b0111..+ 1.75% + * 0b1000..- 0.25% + * 0b1001..- 0.50% + * 0b1010..- 0.75% + * 0b1011..- 1.00% + * 0b1100..- 1.25% + * 0b1101..- 1.50% + * 0b1110..- 1.75% + * 0b1111..- 2.00% + */ +#define PMU_REG_CORE_CLR_REG0_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_CLR_REG0_ADJ_SHIFT)) & PMU_REG_CORE_CLR_REG0_ADJ_MASK) +#define PMU_REG_CORE_CLR_REG1_TARG_MASK (0x3E00U) +#define PMU_REG_CORE_CLR_REG1_TARG_SHIFT (9U) +/*! REG1_TARG - This bit field defines the target voltage for the vpu/gpu power domain. Single bit increments reflect 25mV core voltage steps. Not all steps will make sense to use either because of input supply limitations or load operation. + * 0b00000..Power gated off + * 0b00001..Target core voltage = 0.725V + * 0b00010..Target core voltage = 0.750V + * 0b00011..Target core voltage = 0.775V + * 0b10000..Target core voltage = 1.100V + * 0b11110..Target core voltage = 1.450V + * 0b11111..Power FET switched full on. No regulation. + */ +#define PMU_REG_CORE_CLR_REG1_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_CLR_REG1_TARG_SHIFT)) & PMU_REG_CORE_CLR_REG1_TARG_MASK) +#define PMU_REG_CORE_CLR_REG1_ADJ_MASK (0x3C000U) +#define PMU_REG_CORE_CLR_REG1_ADJ_SHIFT (14U) +/*! REG1_ADJ - This bit field defines the adjustment bits to calibrate the target value of Reg1. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register. + * 0b0000..No adjustment + * 0b0001..+ 0.25% + * 0b0010..+ 0.50% + * 0b0011..+ 0.75% + * 0b0100..+ 1.00% + * 0b0101..+ 1.25% + * 0b0110..+ 1.50% + * 0b0111..+ 1.75% + * 0b1000..- 0.25% + * 0b1001..- 0.50% + * 0b1010..- 0.75% + * 0b1011..- 1.00% + * 0b1100..- 1.25% + * 0b1101..- 1.50% + * 0b1110..- 1.75% + * 0b1111..- 2.00% + */ +#define PMU_REG_CORE_CLR_REG1_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_CLR_REG1_ADJ_SHIFT)) & PMU_REG_CORE_CLR_REG1_ADJ_MASK) #define PMU_REG_CORE_CLR_REG2_TARG_MASK (0x7C0000U) #define PMU_REG_CORE_CLR_REG2_TARG_SHIFT (18U) +/*! REG2_TARG + * 0b00000..Power gated off + * 0b00001..Target core voltage = 0.725V + * 0b00010..Target core voltage = 0.750V + * 0b00011..Target core voltage = 0.775V + * 0b10000..Target core voltage = 1.100V + * 0b11110..Target core voltage = 1.450V + * 0b11111..Power FET switched full on. No regulation. + */ #define PMU_REG_CORE_CLR_REG2_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_CLR_REG2_TARG_SHIFT)) & PMU_REG_CORE_CLR_REG2_TARG_MASK) +#define PMU_REG_CORE_CLR_REG2_ADJ_MASK (0x7800000U) +#define PMU_REG_CORE_CLR_REG2_ADJ_SHIFT (23U) +/*! REG2_ADJ - This bit field defines the adjustment bits to calibrate the target value of Reg2. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register. + * 0b0000..No adjustment + * 0b0001..+ 0.25% + * 0b0010..+ 0.50% + * 0b0011..+ 0.75% + * 0b0100..+ 1.00% + * 0b0101..+ 1.25% + * 0b0110..+ 1.50% + * 0b0111..+ 1.75% + * 0b1000..- 0.25% + * 0b1001..- 0.50% + * 0b1010..- 0.75% + * 0b1011..- 1.00% + * 0b1100..- 1.25% + * 0b1101..- 1.50% + * 0b1110..- 1.75% + * 0b1111..- 2.00% + */ +#define PMU_REG_CORE_CLR_REG2_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_CLR_REG2_ADJ_SHIFT)) & PMU_REG_CORE_CLR_REG2_ADJ_MASK) #define PMU_REG_CORE_CLR_RAMP_RATE_MASK (0x18000000U) #define PMU_REG_CORE_CLR_RAMP_RATE_SHIFT (27U) +/*! RAMP_RATE + * 0b00..Fast + * 0b01..Medium Fast + * 0b10..Medium Slow + * 0b11..Slow + */ #define PMU_REG_CORE_CLR_RAMP_RATE(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_CLR_RAMP_RATE_SHIFT)) & PMU_REG_CORE_CLR_RAMP_RATE_MASK) #define PMU_REG_CORE_CLR_FET_ODRIVE_MASK (0x20000000U) #define PMU_REG_CORE_CLR_FET_ODRIVE_SHIFT (29U) #define PMU_REG_CORE_CLR_FET_ODRIVE(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_CLR_FET_ODRIVE_SHIFT)) & PMU_REG_CORE_CLR_FET_ODRIVE_MASK) +/*! @} */ /*! @name REG_CORE_TOG - Digital Regulator Core Register */ +/*! @{ */ #define PMU_REG_CORE_TOG_REG0_TARG_MASK (0x1FU) #define PMU_REG_CORE_TOG_REG0_TARG_SHIFT (0U) +/*! REG0_TARG + * 0b00000..Power gated off + * 0b00001..Target core voltage = 0.725V + * 0b00010..Target core voltage = 0.750V + * 0b00011..Target core voltage = 0.775V + * 0b10000..Target core voltage = 1.100V + * 0b11110..Target core voltage = 1.450V + * 0b11111..Power FET switched full on. No regulation. + */ #define PMU_REG_CORE_TOG_REG0_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_TOG_REG0_TARG_SHIFT)) & PMU_REG_CORE_TOG_REG0_TARG_MASK) +#define PMU_REG_CORE_TOG_REG0_ADJ_MASK (0x1E0U) +#define PMU_REG_CORE_TOG_REG0_ADJ_SHIFT (5U) +/*! REG0_ADJ - This bit field defines the adjustment bits to calibrate the target value of Reg0. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register. + * 0b0000..No adjustment + * 0b0001..+ 0.25% + * 0b0010..+ 0.50% + * 0b0011..+ 0.75% + * 0b0100..+ 1.00% + * 0b0101..+ 1.25% + * 0b0110..+ 1.50% + * 0b0111..+ 1.75% + * 0b1000..- 0.25% + * 0b1001..- 0.50% + * 0b1010..- 0.75% + * 0b1011..- 1.00% + * 0b1100..- 1.25% + * 0b1101..- 1.50% + * 0b1110..- 1.75% + * 0b1111..- 2.00% + */ +#define PMU_REG_CORE_TOG_REG0_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_TOG_REG0_ADJ_SHIFT)) & PMU_REG_CORE_TOG_REG0_ADJ_MASK) +#define PMU_REG_CORE_TOG_REG1_TARG_MASK (0x3E00U) +#define PMU_REG_CORE_TOG_REG1_TARG_SHIFT (9U) +/*! REG1_TARG - This bit field defines the target voltage for the vpu/gpu power domain. Single bit increments reflect 25mV core voltage steps. Not all steps will make sense to use either because of input supply limitations or load operation. + * 0b00000..Power gated off + * 0b00001..Target core voltage = 0.725V + * 0b00010..Target core voltage = 0.750V + * 0b00011..Target core voltage = 0.775V + * 0b10000..Target core voltage = 1.100V + * 0b11110..Target core voltage = 1.450V + * 0b11111..Power FET switched full on. No regulation. + */ +#define PMU_REG_CORE_TOG_REG1_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_TOG_REG1_TARG_SHIFT)) & PMU_REG_CORE_TOG_REG1_TARG_MASK) +#define PMU_REG_CORE_TOG_REG1_ADJ_MASK (0x3C000U) +#define PMU_REG_CORE_TOG_REG1_ADJ_SHIFT (14U) +/*! REG1_ADJ - This bit field defines the adjustment bits to calibrate the target value of Reg1. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register. + * 0b0000..No adjustment + * 0b0001..+ 0.25% + * 0b0010..+ 0.50% + * 0b0011..+ 0.75% + * 0b0100..+ 1.00% + * 0b0101..+ 1.25% + * 0b0110..+ 1.50% + * 0b0111..+ 1.75% + * 0b1000..- 0.25% + * 0b1001..- 0.50% + * 0b1010..- 0.75% + * 0b1011..- 1.00% + * 0b1100..- 1.25% + * 0b1101..- 1.50% + * 0b1110..- 1.75% + * 0b1111..- 2.00% + */ +#define PMU_REG_CORE_TOG_REG1_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_TOG_REG1_ADJ_SHIFT)) & PMU_REG_CORE_TOG_REG1_ADJ_MASK) #define PMU_REG_CORE_TOG_REG2_TARG_MASK (0x7C0000U) #define PMU_REG_CORE_TOG_REG2_TARG_SHIFT (18U) +/*! REG2_TARG + * 0b00000..Power gated off + * 0b00001..Target core voltage = 0.725V + * 0b00010..Target core voltage = 0.750V + * 0b00011..Target core voltage = 0.775V + * 0b10000..Target core voltage = 1.100V + * 0b11110..Target core voltage = 1.450V + * 0b11111..Power FET switched full on. No regulation. + */ #define PMU_REG_CORE_TOG_REG2_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_TOG_REG2_TARG_SHIFT)) & PMU_REG_CORE_TOG_REG2_TARG_MASK) +#define PMU_REG_CORE_TOG_REG2_ADJ_MASK (0x7800000U) +#define PMU_REG_CORE_TOG_REG2_ADJ_SHIFT (23U) +/*! REG2_ADJ - This bit field defines the adjustment bits to calibrate the target value of Reg2. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register. + * 0b0000..No adjustment + * 0b0001..+ 0.25% + * 0b0010..+ 0.50% + * 0b0011..+ 0.75% + * 0b0100..+ 1.00% + * 0b0101..+ 1.25% + * 0b0110..+ 1.50% + * 0b0111..+ 1.75% + * 0b1000..- 0.25% + * 0b1001..- 0.50% + * 0b1010..- 0.75% + * 0b1011..- 1.00% + * 0b1100..- 1.25% + * 0b1101..- 1.50% + * 0b1110..- 1.75% + * 0b1111..- 2.00% + */ +#define PMU_REG_CORE_TOG_REG2_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_TOG_REG2_ADJ_SHIFT)) & PMU_REG_CORE_TOG_REG2_ADJ_MASK) #define PMU_REG_CORE_TOG_RAMP_RATE_MASK (0x18000000U) #define PMU_REG_CORE_TOG_RAMP_RATE_SHIFT (27U) +/*! RAMP_RATE + * 0b00..Fast + * 0b01..Medium Fast + * 0b10..Medium Slow + * 0b11..Slow + */ #define PMU_REG_CORE_TOG_RAMP_RATE(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_TOG_RAMP_RATE_SHIFT)) & PMU_REG_CORE_TOG_RAMP_RATE_MASK) #define PMU_REG_CORE_TOG_FET_ODRIVE_MASK (0x20000000U) #define PMU_REG_CORE_TOG_FET_ODRIVE_SHIFT (29U) #define PMU_REG_CORE_TOG_FET_ODRIVE(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_TOG_FET_ODRIVE_SHIFT)) & PMU_REG_CORE_TOG_FET_ODRIVE_MASK) +/*! @} */ /*! @name MISC0 - Miscellaneous Register 0 */ +/*! @{ */ #define PMU_MISC0_REFTOP_PWD_MASK (0x1U) #define PMU_MISC0_REFTOP_PWD_SHIFT (0U) #define PMU_MISC0_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_REFTOP_PWD_SHIFT)) & PMU_MISC0_REFTOP_PWD_MASK) #define PMU_MISC0_REFTOP_SELFBIASOFF_MASK (0x8U) #define PMU_MISC0_REFTOP_SELFBIASOFF_SHIFT (3U) +/*! REFTOP_SELFBIASOFF + * 0b0..Uses coarse bias currents for startup + * 0b1..Uses bandgap-based bias currents for best performance. + */ #define PMU_MISC0_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_REFTOP_SELFBIASOFF_SHIFT)) & PMU_MISC0_REFTOP_SELFBIASOFF_MASK) #define PMU_MISC0_REFTOP_VBGADJ_MASK (0x70U) #define PMU_MISC0_REFTOP_VBGADJ_SHIFT (4U) +/*! REFTOP_VBGADJ + * 0b000..Nominal VBG + * 0b001..VBG+0.78% + * 0b010..VBG+1.56% + * 0b011..VBG+2.34% + * 0b100..VBG-0.78% + * 0b101..VBG-1.56% + * 0b110..VBG-2.34% + * 0b111..VBG-3.12% + */ #define PMU_MISC0_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_REFTOP_VBGADJ_SHIFT)) & PMU_MISC0_REFTOP_VBGADJ_MASK) #define PMU_MISC0_REFTOP_VBGUP_MASK (0x80U) #define PMU_MISC0_REFTOP_VBGUP_SHIFT (7U) #define PMU_MISC0_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_REFTOP_VBGUP_SHIFT)) & PMU_MISC0_REFTOP_VBGUP_MASK) #define PMU_MISC0_STOP_MODE_CONFIG_MASK (0xC00U) #define PMU_MISC0_STOP_MODE_CONFIG_SHIFT (10U) +/*! STOP_MODE_CONFIG + * 0b00..SUSPEND (DSM) + * 0b01..Analog regulators are ON. + * 0b10..STOP (lower power) + * 0b11..STOP (very lower power) + */ #define PMU_MISC0_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_STOP_MODE_CONFIG_SHIFT)) & PMU_MISC0_STOP_MODE_CONFIG_MASK) #define PMU_MISC0_DISCON_HIGH_SNVS_MASK (0x1000U) #define PMU_MISC0_DISCON_HIGH_SNVS_SHIFT (12U) +/*! DISCON_HIGH_SNVS + * 0b0..Turn on the switch + * 0b1..Turn off the switch + */ #define PMU_MISC0_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_DISCON_HIGH_SNVS_SHIFT)) & PMU_MISC0_DISCON_HIGH_SNVS_MASK) #define PMU_MISC0_OSC_I_MASK (0x6000U) #define PMU_MISC0_OSC_I_SHIFT (13U) +/*! OSC_I + * 0b00..Nominal + * 0b01..Decrease current by 12.5% + * 0b10..Decrease current by 25.0% + * 0b11..Decrease current by 37.5% + */ #define PMU_MISC0_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_OSC_I_SHIFT)) & PMU_MISC0_OSC_I_MASK) #define PMU_MISC0_OSC_XTALOK_MASK (0x8000U) #define PMU_MISC0_OSC_XTALOK_SHIFT (15U) @@ -16731,41 +26774,95 @@ typedef struct { #define PMU_MISC0_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_OSC_XTALOK_EN_SHIFT)) & PMU_MISC0_OSC_XTALOK_EN_MASK) #define PMU_MISC0_CLKGATE_CTRL_MASK (0x2000000U) #define PMU_MISC0_CLKGATE_CTRL_SHIFT (25U) +/*! CLKGATE_CTRL + * 0b0..Allow the logic to automatically gate the clock when the XTAL is powered down. + * 0b1..Prevent the logic from ever gating off the clock. + */ #define PMU_MISC0_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLKGATE_CTRL_SHIFT)) & PMU_MISC0_CLKGATE_CTRL_MASK) #define PMU_MISC0_CLKGATE_DELAY_MASK (0x1C000000U) #define PMU_MISC0_CLKGATE_DELAY_SHIFT (26U) +/*! CLKGATE_DELAY + * 0b000..0.5ms + * 0b001..1.0ms + * 0b010..2.0ms + * 0b011..3.0ms + * 0b100..4.0ms + * 0b101..5.0ms + * 0b110..6.0ms + * 0b111..7.0ms + */ #define PMU_MISC0_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLKGATE_DELAY_SHIFT)) & PMU_MISC0_CLKGATE_DELAY_MASK) #define PMU_MISC0_RTC_XTAL_SOURCE_MASK (0x20000000U) #define PMU_MISC0_RTC_XTAL_SOURCE_SHIFT (29U) +/*! RTC_XTAL_SOURCE + * 0b0..Internal ring oscillator + * 0b1..RTC_XTAL + */ #define PMU_MISC0_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_RTC_XTAL_SOURCE_SHIFT)) & PMU_MISC0_RTC_XTAL_SOURCE_MASK) #define PMU_MISC0_XTAL_24M_PWD_MASK (0x40000000U) #define PMU_MISC0_XTAL_24M_PWD_SHIFT (30U) #define PMU_MISC0_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_XTAL_24M_PWD_SHIFT)) & PMU_MISC0_XTAL_24M_PWD_MASK) #define PMU_MISC0_VID_PLL_PREDIV_MASK (0x80000000U) #define PMU_MISC0_VID_PLL_PREDIV_SHIFT (31U) +/*! VID_PLL_PREDIV + * 0b0..Divide by 1 + * 0b1..Divide by 2 + */ #define PMU_MISC0_VID_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_VID_PLL_PREDIV_SHIFT)) & PMU_MISC0_VID_PLL_PREDIV_MASK) +/*! @} */ /*! @name MISC0_SET - Miscellaneous Register 0 */ +/*! @{ */ #define PMU_MISC0_SET_REFTOP_PWD_MASK (0x1U) #define PMU_MISC0_SET_REFTOP_PWD_SHIFT (0U) #define PMU_MISC0_SET_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_REFTOP_PWD_SHIFT)) & PMU_MISC0_SET_REFTOP_PWD_MASK) #define PMU_MISC0_SET_REFTOP_SELFBIASOFF_MASK (0x8U) #define PMU_MISC0_SET_REFTOP_SELFBIASOFF_SHIFT (3U) +/*! REFTOP_SELFBIASOFF + * 0b0..Uses coarse bias currents for startup + * 0b1..Uses bandgap-based bias currents for best performance. + */ #define PMU_MISC0_SET_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_REFTOP_SELFBIASOFF_SHIFT)) & PMU_MISC0_SET_REFTOP_SELFBIASOFF_MASK) #define PMU_MISC0_SET_REFTOP_VBGADJ_MASK (0x70U) #define PMU_MISC0_SET_REFTOP_VBGADJ_SHIFT (4U) +/*! REFTOP_VBGADJ + * 0b000..Nominal VBG + * 0b001..VBG+0.78% + * 0b010..VBG+1.56% + * 0b011..VBG+2.34% + * 0b100..VBG-0.78% + * 0b101..VBG-1.56% + * 0b110..VBG-2.34% + * 0b111..VBG-3.12% + */ #define PMU_MISC0_SET_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_REFTOP_VBGADJ_SHIFT)) & PMU_MISC0_SET_REFTOP_VBGADJ_MASK) #define PMU_MISC0_SET_REFTOP_VBGUP_MASK (0x80U) #define PMU_MISC0_SET_REFTOP_VBGUP_SHIFT (7U) #define PMU_MISC0_SET_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_REFTOP_VBGUP_SHIFT)) & PMU_MISC0_SET_REFTOP_VBGUP_MASK) #define PMU_MISC0_SET_STOP_MODE_CONFIG_MASK (0xC00U) #define PMU_MISC0_SET_STOP_MODE_CONFIG_SHIFT (10U) +/*! STOP_MODE_CONFIG + * 0b00..SUSPEND (DSM) + * 0b01..Analog regulators are ON. + * 0b10..STOP (lower power) + * 0b11..STOP (very lower power) + */ #define PMU_MISC0_SET_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_STOP_MODE_CONFIG_SHIFT)) & PMU_MISC0_SET_STOP_MODE_CONFIG_MASK) #define PMU_MISC0_SET_DISCON_HIGH_SNVS_MASK (0x1000U) #define PMU_MISC0_SET_DISCON_HIGH_SNVS_SHIFT (12U) +/*! DISCON_HIGH_SNVS + * 0b0..Turn on the switch + * 0b1..Turn off the switch + */ #define PMU_MISC0_SET_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_DISCON_HIGH_SNVS_SHIFT)) & PMU_MISC0_SET_DISCON_HIGH_SNVS_MASK) #define PMU_MISC0_SET_OSC_I_MASK (0x6000U) #define PMU_MISC0_SET_OSC_I_SHIFT (13U) +/*! OSC_I + * 0b00..Nominal + * 0b01..Decrease current by 12.5% + * 0b10..Decrease current by 25.0% + * 0b11..Decrease current by 37.5% + */ #define PMU_MISC0_SET_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_OSC_I_SHIFT)) & PMU_MISC0_SET_OSC_I_MASK) #define PMU_MISC0_SET_OSC_XTALOK_MASK (0x8000U) #define PMU_MISC0_SET_OSC_XTALOK_SHIFT (15U) @@ -16775,41 +26872,95 @@ typedef struct { #define PMU_MISC0_SET_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_OSC_XTALOK_EN_SHIFT)) & PMU_MISC0_SET_OSC_XTALOK_EN_MASK) #define PMU_MISC0_SET_CLKGATE_CTRL_MASK (0x2000000U) #define PMU_MISC0_SET_CLKGATE_CTRL_SHIFT (25U) +/*! CLKGATE_CTRL + * 0b0..Allow the logic to automatically gate the clock when the XTAL is powered down. + * 0b1..Prevent the logic from ever gating off the clock. + */ #define PMU_MISC0_SET_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_CLKGATE_CTRL_SHIFT)) & PMU_MISC0_SET_CLKGATE_CTRL_MASK) #define PMU_MISC0_SET_CLKGATE_DELAY_MASK (0x1C000000U) #define PMU_MISC0_SET_CLKGATE_DELAY_SHIFT (26U) +/*! CLKGATE_DELAY + * 0b000..0.5ms + * 0b001..1.0ms + * 0b010..2.0ms + * 0b011..3.0ms + * 0b100..4.0ms + * 0b101..5.0ms + * 0b110..6.0ms + * 0b111..7.0ms + */ #define PMU_MISC0_SET_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_CLKGATE_DELAY_SHIFT)) & PMU_MISC0_SET_CLKGATE_DELAY_MASK) #define PMU_MISC0_SET_RTC_XTAL_SOURCE_MASK (0x20000000U) #define PMU_MISC0_SET_RTC_XTAL_SOURCE_SHIFT (29U) +/*! RTC_XTAL_SOURCE + * 0b0..Internal ring oscillator + * 0b1..RTC_XTAL + */ #define PMU_MISC0_SET_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_RTC_XTAL_SOURCE_SHIFT)) & PMU_MISC0_SET_RTC_XTAL_SOURCE_MASK) #define PMU_MISC0_SET_XTAL_24M_PWD_MASK (0x40000000U) #define PMU_MISC0_SET_XTAL_24M_PWD_SHIFT (30U) #define PMU_MISC0_SET_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_XTAL_24M_PWD_SHIFT)) & PMU_MISC0_SET_XTAL_24M_PWD_MASK) #define PMU_MISC0_SET_VID_PLL_PREDIV_MASK (0x80000000U) #define PMU_MISC0_SET_VID_PLL_PREDIV_SHIFT (31U) +/*! VID_PLL_PREDIV + * 0b0..Divide by 1 + * 0b1..Divide by 2 + */ #define PMU_MISC0_SET_VID_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_VID_PLL_PREDIV_SHIFT)) & PMU_MISC0_SET_VID_PLL_PREDIV_MASK) +/*! @} */ /*! @name MISC0_CLR - Miscellaneous Register 0 */ +/*! @{ */ #define PMU_MISC0_CLR_REFTOP_PWD_MASK (0x1U) #define PMU_MISC0_CLR_REFTOP_PWD_SHIFT (0U) #define PMU_MISC0_CLR_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_REFTOP_PWD_SHIFT)) & PMU_MISC0_CLR_REFTOP_PWD_MASK) #define PMU_MISC0_CLR_REFTOP_SELFBIASOFF_MASK (0x8U) #define PMU_MISC0_CLR_REFTOP_SELFBIASOFF_SHIFT (3U) +/*! REFTOP_SELFBIASOFF + * 0b0..Uses coarse bias currents for startup + * 0b1..Uses bandgap-based bias currents for best performance. + */ #define PMU_MISC0_CLR_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_REFTOP_SELFBIASOFF_SHIFT)) & PMU_MISC0_CLR_REFTOP_SELFBIASOFF_MASK) #define PMU_MISC0_CLR_REFTOP_VBGADJ_MASK (0x70U) #define PMU_MISC0_CLR_REFTOP_VBGADJ_SHIFT (4U) +/*! REFTOP_VBGADJ + * 0b000..Nominal VBG + * 0b001..VBG+0.78% + * 0b010..VBG+1.56% + * 0b011..VBG+2.34% + * 0b100..VBG-0.78% + * 0b101..VBG-1.56% + * 0b110..VBG-2.34% + * 0b111..VBG-3.12% + */ #define PMU_MISC0_CLR_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_REFTOP_VBGADJ_SHIFT)) & PMU_MISC0_CLR_REFTOP_VBGADJ_MASK) #define PMU_MISC0_CLR_REFTOP_VBGUP_MASK (0x80U) #define PMU_MISC0_CLR_REFTOP_VBGUP_SHIFT (7U) #define PMU_MISC0_CLR_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_REFTOP_VBGUP_SHIFT)) & PMU_MISC0_CLR_REFTOP_VBGUP_MASK) #define PMU_MISC0_CLR_STOP_MODE_CONFIG_MASK (0xC00U) #define PMU_MISC0_CLR_STOP_MODE_CONFIG_SHIFT (10U) +/*! STOP_MODE_CONFIG + * 0b00..SUSPEND (DSM) + * 0b01..Analog regulators are ON. + * 0b10..STOP (lower power) + * 0b11..STOP (very lower power) + */ #define PMU_MISC0_CLR_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_STOP_MODE_CONFIG_SHIFT)) & PMU_MISC0_CLR_STOP_MODE_CONFIG_MASK) #define PMU_MISC0_CLR_DISCON_HIGH_SNVS_MASK (0x1000U) #define PMU_MISC0_CLR_DISCON_HIGH_SNVS_SHIFT (12U) +/*! DISCON_HIGH_SNVS + * 0b0..Turn on the switch + * 0b1..Turn off the switch + */ #define PMU_MISC0_CLR_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_DISCON_HIGH_SNVS_SHIFT)) & PMU_MISC0_CLR_DISCON_HIGH_SNVS_MASK) #define PMU_MISC0_CLR_OSC_I_MASK (0x6000U) #define PMU_MISC0_CLR_OSC_I_SHIFT (13U) +/*! OSC_I + * 0b00..Nominal + * 0b01..Decrease current by 12.5% + * 0b10..Decrease current by 25.0% + * 0b11..Decrease current by 37.5% + */ #define PMU_MISC0_CLR_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_OSC_I_SHIFT)) & PMU_MISC0_CLR_OSC_I_MASK) #define PMU_MISC0_CLR_OSC_XTALOK_MASK (0x8000U) #define PMU_MISC0_CLR_OSC_XTALOK_SHIFT (15U) @@ -16819,41 +26970,95 @@ typedef struct { #define PMU_MISC0_CLR_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_OSC_XTALOK_EN_SHIFT)) & PMU_MISC0_CLR_OSC_XTALOK_EN_MASK) #define PMU_MISC0_CLR_CLKGATE_CTRL_MASK (0x2000000U) #define PMU_MISC0_CLR_CLKGATE_CTRL_SHIFT (25U) +/*! CLKGATE_CTRL + * 0b0..Allow the logic to automatically gate the clock when the XTAL is powered down. + * 0b1..Prevent the logic from ever gating off the clock. + */ #define PMU_MISC0_CLR_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_CLKGATE_CTRL_SHIFT)) & PMU_MISC0_CLR_CLKGATE_CTRL_MASK) #define PMU_MISC0_CLR_CLKGATE_DELAY_MASK (0x1C000000U) #define PMU_MISC0_CLR_CLKGATE_DELAY_SHIFT (26U) +/*! CLKGATE_DELAY + * 0b000..0.5ms + * 0b001..1.0ms + * 0b010..2.0ms + * 0b011..3.0ms + * 0b100..4.0ms + * 0b101..5.0ms + * 0b110..6.0ms + * 0b111..7.0ms + */ #define PMU_MISC0_CLR_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_CLKGATE_DELAY_SHIFT)) & PMU_MISC0_CLR_CLKGATE_DELAY_MASK) #define PMU_MISC0_CLR_RTC_XTAL_SOURCE_MASK (0x20000000U) #define PMU_MISC0_CLR_RTC_XTAL_SOURCE_SHIFT (29U) +/*! RTC_XTAL_SOURCE + * 0b0..Internal ring oscillator + * 0b1..RTC_XTAL + */ #define PMU_MISC0_CLR_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_RTC_XTAL_SOURCE_SHIFT)) & PMU_MISC0_CLR_RTC_XTAL_SOURCE_MASK) #define PMU_MISC0_CLR_XTAL_24M_PWD_MASK (0x40000000U) #define PMU_MISC0_CLR_XTAL_24M_PWD_SHIFT (30U) #define PMU_MISC0_CLR_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_XTAL_24M_PWD_SHIFT)) & PMU_MISC0_CLR_XTAL_24M_PWD_MASK) #define PMU_MISC0_CLR_VID_PLL_PREDIV_MASK (0x80000000U) #define PMU_MISC0_CLR_VID_PLL_PREDIV_SHIFT (31U) +/*! VID_PLL_PREDIV + * 0b0..Divide by 1 + * 0b1..Divide by 2 + */ #define PMU_MISC0_CLR_VID_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_VID_PLL_PREDIV_SHIFT)) & PMU_MISC0_CLR_VID_PLL_PREDIV_MASK) +/*! @} */ /*! @name MISC0_TOG - Miscellaneous Register 0 */ +/*! @{ */ #define PMU_MISC0_TOG_REFTOP_PWD_MASK (0x1U) #define PMU_MISC0_TOG_REFTOP_PWD_SHIFT (0U) #define PMU_MISC0_TOG_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_REFTOP_PWD_SHIFT)) & PMU_MISC0_TOG_REFTOP_PWD_MASK) #define PMU_MISC0_TOG_REFTOP_SELFBIASOFF_MASK (0x8U) #define PMU_MISC0_TOG_REFTOP_SELFBIASOFF_SHIFT (3U) +/*! REFTOP_SELFBIASOFF + * 0b0..Uses coarse bias currents for startup + * 0b1..Uses bandgap-based bias currents for best performance. + */ #define PMU_MISC0_TOG_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_REFTOP_SELFBIASOFF_SHIFT)) & PMU_MISC0_TOG_REFTOP_SELFBIASOFF_MASK) #define PMU_MISC0_TOG_REFTOP_VBGADJ_MASK (0x70U) #define PMU_MISC0_TOG_REFTOP_VBGADJ_SHIFT (4U) +/*! REFTOP_VBGADJ + * 0b000..Nominal VBG + * 0b001..VBG+0.78% + * 0b010..VBG+1.56% + * 0b011..VBG+2.34% + * 0b100..VBG-0.78% + * 0b101..VBG-1.56% + * 0b110..VBG-2.34% + * 0b111..VBG-3.12% + */ #define PMU_MISC0_TOG_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_REFTOP_VBGADJ_SHIFT)) & PMU_MISC0_TOG_REFTOP_VBGADJ_MASK) #define PMU_MISC0_TOG_REFTOP_VBGUP_MASK (0x80U) #define PMU_MISC0_TOG_REFTOP_VBGUP_SHIFT (7U) #define PMU_MISC0_TOG_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_REFTOP_VBGUP_SHIFT)) & PMU_MISC0_TOG_REFTOP_VBGUP_MASK) #define PMU_MISC0_TOG_STOP_MODE_CONFIG_MASK (0xC00U) #define PMU_MISC0_TOG_STOP_MODE_CONFIG_SHIFT (10U) +/*! STOP_MODE_CONFIG + * 0b00..SUSPEND (DSM) + * 0b01..Analog regulators are ON. + * 0b10..STOP (lower power) + * 0b11..STOP (very lower power) + */ #define PMU_MISC0_TOG_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_STOP_MODE_CONFIG_SHIFT)) & PMU_MISC0_TOG_STOP_MODE_CONFIG_MASK) #define PMU_MISC0_TOG_DISCON_HIGH_SNVS_MASK (0x1000U) #define PMU_MISC0_TOG_DISCON_HIGH_SNVS_SHIFT (12U) +/*! DISCON_HIGH_SNVS + * 0b0..Turn on the switch + * 0b1..Turn off the switch + */ #define PMU_MISC0_TOG_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_DISCON_HIGH_SNVS_SHIFT)) & PMU_MISC0_TOG_DISCON_HIGH_SNVS_MASK) #define PMU_MISC0_TOG_OSC_I_MASK (0x6000U) #define PMU_MISC0_TOG_OSC_I_SHIFT (13U) +/*! OSC_I + * 0b00..Nominal + * 0b01..Decrease current by 12.5% + * 0b10..Decrease current by 25.0% + * 0b11..Decrease current by 37.5% + */ #define PMU_MISC0_TOG_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_OSC_I_SHIFT)) & PMU_MISC0_TOG_OSC_I_MASK) #define PMU_MISC0_TOG_OSC_XTALOK_MASK (0x8000U) #define PMU_MISC0_TOG_OSC_XTALOK_SHIFT (15U) @@ -16863,30 +27068,104 @@ typedef struct { #define PMU_MISC0_TOG_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_OSC_XTALOK_EN_SHIFT)) & PMU_MISC0_TOG_OSC_XTALOK_EN_MASK) #define PMU_MISC0_TOG_CLKGATE_CTRL_MASK (0x2000000U) #define PMU_MISC0_TOG_CLKGATE_CTRL_SHIFT (25U) +/*! CLKGATE_CTRL + * 0b0..Allow the logic to automatically gate the clock when the XTAL is powered down. + * 0b1..Prevent the logic from ever gating off the clock. + */ #define PMU_MISC0_TOG_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_CLKGATE_CTRL_SHIFT)) & PMU_MISC0_TOG_CLKGATE_CTRL_MASK) #define PMU_MISC0_TOG_CLKGATE_DELAY_MASK (0x1C000000U) #define PMU_MISC0_TOG_CLKGATE_DELAY_SHIFT (26U) +/*! CLKGATE_DELAY + * 0b000..0.5ms + * 0b001..1.0ms + * 0b010..2.0ms + * 0b011..3.0ms + * 0b100..4.0ms + * 0b101..5.0ms + * 0b110..6.0ms + * 0b111..7.0ms + */ #define PMU_MISC0_TOG_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_CLKGATE_DELAY_SHIFT)) & PMU_MISC0_TOG_CLKGATE_DELAY_MASK) #define PMU_MISC0_TOG_RTC_XTAL_SOURCE_MASK (0x20000000U) #define PMU_MISC0_TOG_RTC_XTAL_SOURCE_SHIFT (29U) +/*! RTC_XTAL_SOURCE + * 0b0..Internal ring oscillator + * 0b1..RTC_XTAL + */ #define PMU_MISC0_TOG_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_RTC_XTAL_SOURCE_SHIFT)) & PMU_MISC0_TOG_RTC_XTAL_SOURCE_MASK) #define PMU_MISC0_TOG_XTAL_24M_PWD_MASK (0x40000000U) #define PMU_MISC0_TOG_XTAL_24M_PWD_SHIFT (30U) #define PMU_MISC0_TOG_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_XTAL_24M_PWD_SHIFT)) & PMU_MISC0_TOG_XTAL_24M_PWD_MASK) #define PMU_MISC0_TOG_VID_PLL_PREDIV_MASK (0x80000000U) #define PMU_MISC0_TOG_VID_PLL_PREDIV_SHIFT (31U) +/*! VID_PLL_PREDIV + * 0b0..Divide by 1 + * 0b1..Divide by 2 + */ #define PMU_MISC0_TOG_VID_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_VID_PLL_PREDIV_SHIFT)) & PMU_MISC0_TOG_VID_PLL_PREDIV_MASK) +/*! @} */ /*! @name MISC1 - Miscellaneous Register 1 */ +/*! @{ */ #define PMU_MISC1_LVDS1_CLK_SEL_MASK (0x1FU) #define PMU_MISC1_LVDS1_CLK_SEL_SHIFT (0U) +/*! LVDS1_CLK_SEL + * 0b00000..Arm PLL + * 0b00001..System PLL + * 0b00010..ref_pfd4_clk == pll2_pfd0_clk + * 0b00011..ref_pfd5_clk == pll2_pfd1_clk + * 0b00100..ref_pfd6_clk == pll2_pfd2_clk + * 0b00101..ref_pfd7_clk == pll2_pfd3_clk + * 0b00110..Audio PLL + * 0b00111..Video PLL + * 0b01001..ethernet ref clock (ENET_PLL) + * 0b01100..USB1 PLL clock + * 0b01101..USB2 PLL clock + * 0b01110..ref_pfd0_clk == pll3_pfd0_clk + * 0b01111..ref_pfd1_clk == pll3_pfd1_clk + * 0b10000..ref_pfd2_clk == pll3_pfd2_clk + * 0b10001..ref_pfd3_clk == pll3_pfd3_clk + * 0b10010..xtal (24M) + */ #define PMU_MISC1_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_LVDS1_CLK_SEL_SHIFT)) & PMU_MISC1_LVDS1_CLK_SEL_MASK) +#define PMU_MISC1_LVDS2_CLK_SEL_MASK (0x3E0U) +#define PMU_MISC1_LVDS2_CLK_SEL_SHIFT (5U) +/*! LVDS2_CLK_SEL + * 0b00000..Arm PLL + * 0b00001..System PLL + * 0b00010..ref_pfd4_clk == pll2_pfd0_clk + * 0b00011..ref_pfd5_clk == pll2_pfd1_clk + * 0b00100..ref_pfd6_clk == pll2_pfd2_clk + * 0b00101..ref_pfd7_clk == pll2_pfd3_clk + * 0b00110..Audio PLL + * 0b00111..Video PLL + * 0b01000..MLB PLL + * 0b01001..ethernet ref clock (ENET_PLL) + * 0b01010..PCIe ref clock (125M) + * 0b01011..SATA ref clock (100M) + * 0b01100..USB1 PLL clock + * 0b01101..USB2 PLL clock + * 0b01110..ref_pfd0_clk == pll3_pfd0_clk + * 0b01111..ref_pfd1_clk == pll3_pfd1_clk + * 0b10000..ref_pfd2_clk == pll3_pfd2_clk + * 0b10001..ref_pfd3_clk == pll3_pfd3_clk + * 0b10010..xtal (24M) + * 0b10011..LVDS1 (loopback) + * 0b10100..LVDS2 (not useful) + */ +#define PMU_MISC1_LVDS2_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_LVDS2_CLK_SEL_SHIFT)) & PMU_MISC1_LVDS2_CLK_SEL_MASK) #define PMU_MISC1_LVDSCLK1_OBEN_MASK (0x400U) #define PMU_MISC1_LVDSCLK1_OBEN_SHIFT (10U) #define PMU_MISC1_LVDSCLK1_OBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_LVDSCLK1_OBEN_SHIFT)) & PMU_MISC1_LVDSCLK1_OBEN_MASK) +#define PMU_MISC1_LVDSCLK2_OBEN_MASK (0x800U) +#define PMU_MISC1_LVDSCLK2_OBEN_SHIFT (11U) +#define PMU_MISC1_LVDSCLK2_OBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_LVDSCLK2_OBEN_SHIFT)) & PMU_MISC1_LVDSCLK2_OBEN_MASK) #define PMU_MISC1_LVDSCLK1_IBEN_MASK (0x1000U) #define PMU_MISC1_LVDSCLK1_IBEN_SHIFT (12U) #define PMU_MISC1_LVDSCLK1_IBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_LVDSCLK1_IBEN_SHIFT)) & PMU_MISC1_LVDSCLK1_IBEN_MASK) +#define PMU_MISC1_LVDSCLK2_IBEN_MASK (0x2000U) +#define PMU_MISC1_LVDSCLK2_IBEN_SHIFT (13U) +#define PMU_MISC1_LVDSCLK2_IBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_LVDSCLK2_IBEN_SHIFT)) & PMU_MISC1_LVDSCLK2_IBEN_MASK) #define PMU_MISC1_PFD_480_AUTOGATE_EN_MASK (0x10000U) #define PMU_MISC1_PFD_480_AUTOGATE_EN_SHIFT (16U) #define PMU_MISC1_PFD_480_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_PFD_480_AUTOGATE_EN_SHIFT)) & PMU_MISC1_PFD_480_AUTOGATE_EN_MASK) @@ -16908,17 +27187,69 @@ typedef struct { #define PMU_MISC1_IRQ_DIG_BO_MASK (0x80000000U) #define PMU_MISC1_IRQ_DIG_BO_SHIFT (31U) #define PMU_MISC1_IRQ_DIG_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_IRQ_DIG_BO_SHIFT)) & PMU_MISC1_IRQ_DIG_BO_MASK) +/*! @} */ /*! @name MISC1_SET - Miscellaneous Register 1 */ +/*! @{ */ #define PMU_MISC1_SET_LVDS1_CLK_SEL_MASK (0x1FU) #define PMU_MISC1_SET_LVDS1_CLK_SEL_SHIFT (0U) +/*! LVDS1_CLK_SEL + * 0b00000..Arm PLL + * 0b00001..System PLL + * 0b00010..ref_pfd4_clk == pll2_pfd0_clk + * 0b00011..ref_pfd5_clk == pll2_pfd1_clk + * 0b00100..ref_pfd6_clk == pll2_pfd2_clk + * 0b00101..ref_pfd7_clk == pll2_pfd3_clk + * 0b00110..Audio PLL + * 0b00111..Video PLL + * 0b01001..ethernet ref clock (ENET_PLL) + * 0b01100..USB1 PLL clock + * 0b01101..USB2 PLL clock + * 0b01110..ref_pfd0_clk == pll3_pfd0_clk + * 0b01111..ref_pfd1_clk == pll3_pfd1_clk + * 0b10000..ref_pfd2_clk == pll3_pfd2_clk + * 0b10001..ref_pfd3_clk == pll3_pfd3_clk + * 0b10010..xtal (24M) + */ #define PMU_MISC1_SET_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_LVDS1_CLK_SEL_SHIFT)) & PMU_MISC1_SET_LVDS1_CLK_SEL_MASK) +#define PMU_MISC1_SET_LVDS2_CLK_SEL_MASK (0x3E0U) +#define PMU_MISC1_SET_LVDS2_CLK_SEL_SHIFT (5U) +/*! LVDS2_CLK_SEL + * 0b00000..Arm PLL + * 0b00001..System PLL + * 0b00010..ref_pfd4_clk == pll2_pfd0_clk + * 0b00011..ref_pfd5_clk == pll2_pfd1_clk + * 0b00100..ref_pfd6_clk == pll2_pfd2_clk + * 0b00101..ref_pfd7_clk == pll2_pfd3_clk + * 0b00110..Audio PLL + * 0b00111..Video PLL + * 0b01000..MLB PLL + * 0b01001..ethernet ref clock (ENET_PLL) + * 0b01010..PCIe ref clock (125M) + * 0b01011..SATA ref clock (100M) + * 0b01100..USB1 PLL clock + * 0b01101..USB2 PLL clock + * 0b01110..ref_pfd0_clk == pll3_pfd0_clk + * 0b01111..ref_pfd1_clk == pll3_pfd1_clk + * 0b10000..ref_pfd2_clk == pll3_pfd2_clk + * 0b10001..ref_pfd3_clk == pll3_pfd3_clk + * 0b10010..xtal (24M) + * 0b10011..LVDS1 (loopback) + * 0b10100..LVDS2 (not useful) + */ +#define PMU_MISC1_SET_LVDS2_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_LVDS2_CLK_SEL_SHIFT)) & PMU_MISC1_SET_LVDS2_CLK_SEL_MASK) #define PMU_MISC1_SET_LVDSCLK1_OBEN_MASK (0x400U) #define PMU_MISC1_SET_LVDSCLK1_OBEN_SHIFT (10U) #define PMU_MISC1_SET_LVDSCLK1_OBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_LVDSCLK1_OBEN_SHIFT)) & PMU_MISC1_SET_LVDSCLK1_OBEN_MASK) +#define PMU_MISC1_SET_LVDSCLK2_OBEN_MASK (0x800U) +#define PMU_MISC1_SET_LVDSCLK2_OBEN_SHIFT (11U) +#define PMU_MISC1_SET_LVDSCLK2_OBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_LVDSCLK2_OBEN_SHIFT)) & PMU_MISC1_SET_LVDSCLK2_OBEN_MASK) #define PMU_MISC1_SET_LVDSCLK1_IBEN_MASK (0x1000U) #define PMU_MISC1_SET_LVDSCLK1_IBEN_SHIFT (12U) #define PMU_MISC1_SET_LVDSCLK1_IBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_LVDSCLK1_IBEN_SHIFT)) & PMU_MISC1_SET_LVDSCLK1_IBEN_MASK) +#define PMU_MISC1_SET_LVDSCLK2_IBEN_MASK (0x2000U) +#define PMU_MISC1_SET_LVDSCLK2_IBEN_SHIFT (13U) +#define PMU_MISC1_SET_LVDSCLK2_IBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_LVDSCLK2_IBEN_SHIFT)) & PMU_MISC1_SET_LVDSCLK2_IBEN_MASK) #define PMU_MISC1_SET_PFD_480_AUTOGATE_EN_MASK (0x10000U) #define PMU_MISC1_SET_PFD_480_AUTOGATE_EN_SHIFT (16U) #define PMU_MISC1_SET_PFD_480_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_PFD_480_AUTOGATE_EN_SHIFT)) & PMU_MISC1_SET_PFD_480_AUTOGATE_EN_MASK) @@ -16940,17 +27271,69 @@ typedef struct { #define PMU_MISC1_SET_IRQ_DIG_BO_MASK (0x80000000U) #define PMU_MISC1_SET_IRQ_DIG_BO_SHIFT (31U) #define PMU_MISC1_SET_IRQ_DIG_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_IRQ_DIG_BO_SHIFT)) & PMU_MISC1_SET_IRQ_DIG_BO_MASK) +/*! @} */ /*! @name MISC1_CLR - Miscellaneous Register 1 */ +/*! @{ */ #define PMU_MISC1_CLR_LVDS1_CLK_SEL_MASK (0x1FU) #define PMU_MISC1_CLR_LVDS1_CLK_SEL_SHIFT (0U) +/*! LVDS1_CLK_SEL + * 0b00000..Arm PLL + * 0b00001..System PLL + * 0b00010..ref_pfd4_clk == pll2_pfd0_clk + * 0b00011..ref_pfd5_clk == pll2_pfd1_clk + * 0b00100..ref_pfd6_clk == pll2_pfd2_clk + * 0b00101..ref_pfd7_clk == pll2_pfd3_clk + * 0b00110..Audio PLL + * 0b00111..Video PLL + * 0b01001..ethernet ref clock (ENET_PLL) + * 0b01100..USB1 PLL clock + * 0b01101..USB2 PLL clock + * 0b01110..ref_pfd0_clk == pll3_pfd0_clk + * 0b01111..ref_pfd1_clk == pll3_pfd1_clk + * 0b10000..ref_pfd2_clk == pll3_pfd2_clk + * 0b10001..ref_pfd3_clk == pll3_pfd3_clk + * 0b10010..xtal (24M) + */ #define PMU_MISC1_CLR_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_LVDS1_CLK_SEL_SHIFT)) & PMU_MISC1_CLR_LVDS1_CLK_SEL_MASK) +#define PMU_MISC1_CLR_LVDS2_CLK_SEL_MASK (0x3E0U) +#define PMU_MISC1_CLR_LVDS2_CLK_SEL_SHIFT (5U) +/*! LVDS2_CLK_SEL + * 0b00000..Arm PLL + * 0b00001..System PLL + * 0b00010..ref_pfd4_clk == pll2_pfd0_clk + * 0b00011..ref_pfd5_clk == pll2_pfd1_clk + * 0b00100..ref_pfd6_clk == pll2_pfd2_clk + * 0b00101..ref_pfd7_clk == pll2_pfd3_clk + * 0b00110..Audio PLL + * 0b00111..Video PLL + * 0b01000..MLB PLL + * 0b01001..ethernet ref clock (ENET_PLL) + * 0b01010..PCIe ref clock (125M) + * 0b01011..SATA ref clock (100M) + * 0b01100..USB1 PLL clock + * 0b01101..USB2 PLL clock + * 0b01110..ref_pfd0_clk == pll3_pfd0_clk + * 0b01111..ref_pfd1_clk == pll3_pfd1_clk + * 0b10000..ref_pfd2_clk == pll3_pfd2_clk + * 0b10001..ref_pfd3_clk == pll3_pfd3_clk + * 0b10010..xtal (24M) + * 0b10011..LVDS1 (loopback) + * 0b10100..LVDS2 (not useful) + */ +#define PMU_MISC1_CLR_LVDS2_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_LVDS2_CLK_SEL_SHIFT)) & PMU_MISC1_CLR_LVDS2_CLK_SEL_MASK) #define PMU_MISC1_CLR_LVDSCLK1_OBEN_MASK (0x400U) #define PMU_MISC1_CLR_LVDSCLK1_OBEN_SHIFT (10U) #define PMU_MISC1_CLR_LVDSCLK1_OBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_LVDSCLK1_OBEN_SHIFT)) & PMU_MISC1_CLR_LVDSCLK1_OBEN_MASK) +#define PMU_MISC1_CLR_LVDSCLK2_OBEN_MASK (0x800U) +#define PMU_MISC1_CLR_LVDSCLK2_OBEN_SHIFT (11U) +#define PMU_MISC1_CLR_LVDSCLK2_OBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_LVDSCLK2_OBEN_SHIFT)) & PMU_MISC1_CLR_LVDSCLK2_OBEN_MASK) #define PMU_MISC1_CLR_LVDSCLK1_IBEN_MASK (0x1000U) #define PMU_MISC1_CLR_LVDSCLK1_IBEN_SHIFT (12U) #define PMU_MISC1_CLR_LVDSCLK1_IBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_LVDSCLK1_IBEN_SHIFT)) & PMU_MISC1_CLR_LVDSCLK1_IBEN_MASK) +#define PMU_MISC1_CLR_LVDSCLK2_IBEN_MASK (0x2000U) +#define PMU_MISC1_CLR_LVDSCLK2_IBEN_SHIFT (13U) +#define PMU_MISC1_CLR_LVDSCLK2_IBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_LVDSCLK2_IBEN_SHIFT)) & PMU_MISC1_CLR_LVDSCLK2_IBEN_MASK) #define PMU_MISC1_CLR_PFD_480_AUTOGATE_EN_MASK (0x10000U) #define PMU_MISC1_CLR_PFD_480_AUTOGATE_EN_SHIFT (16U) #define PMU_MISC1_CLR_PFD_480_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_PFD_480_AUTOGATE_EN_SHIFT)) & PMU_MISC1_CLR_PFD_480_AUTOGATE_EN_MASK) @@ -16972,17 +27355,69 @@ typedef struct { #define PMU_MISC1_CLR_IRQ_DIG_BO_MASK (0x80000000U) #define PMU_MISC1_CLR_IRQ_DIG_BO_SHIFT (31U) #define PMU_MISC1_CLR_IRQ_DIG_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_IRQ_DIG_BO_SHIFT)) & PMU_MISC1_CLR_IRQ_DIG_BO_MASK) +/*! @} */ /*! @name MISC1_TOG - Miscellaneous Register 1 */ +/*! @{ */ #define PMU_MISC1_TOG_LVDS1_CLK_SEL_MASK (0x1FU) #define PMU_MISC1_TOG_LVDS1_CLK_SEL_SHIFT (0U) +/*! LVDS1_CLK_SEL + * 0b00000..Arm PLL + * 0b00001..System PLL + * 0b00010..ref_pfd4_clk == pll2_pfd0_clk + * 0b00011..ref_pfd5_clk == pll2_pfd1_clk + * 0b00100..ref_pfd6_clk == pll2_pfd2_clk + * 0b00101..ref_pfd7_clk == pll2_pfd3_clk + * 0b00110..Audio PLL + * 0b00111..Video PLL + * 0b01001..ethernet ref clock (ENET_PLL) + * 0b01100..USB1 PLL clock + * 0b01101..USB2 PLL clock + * 0b01110..ref_pfd0_clk == pll3_pfd0_clk + * 0b01111..ref_pfd1_clk == pll3_pfd1_clk + * 0b10000..ref_pfd2_clk == pll3_pfd2_clk + * 0b10001..ref_pfd3_clk == pll3_pfd3_clk + * 0b10010..xtal (24M) + */ #define PMU_MISC1_TOG_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_LVDS1_CLK_SEL_SHIFT)) & PMU_MISC1_TOG_LVDS1_CLK_SEL_MASK) +#define PMU_MISC1_TOG_LVDS2_CLK_SEL_MASK (0x3E0U) +#define PMU_MISC1_TOG_LVDS2_CLK_SEL_SHIFT (5U) +/*! LVDS2_CLK_SEL + * 0b00000..Arm PLL + * 0b00001..System PLL + * 0b00010..ref_pfd4_clk == pll2_pfd0_clk + * 0b00011..ref_pfd5_clk == pll2_pfd1_clk + * 0b00100..ref_pfd6_clk == pll2_pfd2_clk + * 0b00101..ref_pfd7_clk == pll2_pfd3_clk + * 0b00110..Audio PLL + * 0b00111..Video PLL + * 0b01000..MLB PLL + * 0b01001..ethernet ref clock (ENET_PLL) + * 0b01010..PCIe ref clock (125M) + * 0b01011..SATA ref clock (100M) + * 0b01100..USB1 PLL clock + * 0b01101..USB2 PLL clock + * 0b01110..ref_pfd0_clk == pll3_pfd0_clk + * 0b01111..ref_pfd1_clk == pll3_pfd1_clk + * 0b10000..ref_pfd2_clk == pll3_pfd2_clk + * 0b10001..ref_pfd3_clk == pll3_pfd3_clk + * 0b10010..xtal (24M) + * 0b10011..LVDS1 (loopback) + * 0b10100..LVDS2 (not useful) + */ +#define PMU_MISC1_TOG_LVDS2_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_LVDS2_CLK_SEL_SHIFT)) & PMU_MISC1_TOG_LVDS2_CLK_SEL_MASK) #define PMU_MISC1_TOG_LVDSCLK1_OBEN_MASK (0x400U) #define PMU_MISC1_TOG_LVDSCLK1_OBEN_SHIFT (10U) #define PMU_MISC1_TOG_LVDSCLK1_OBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_LVDSCLK1_OBEN_SHIFT)) & PMU_MISC1_TOG_LVDSCLK1_OBEN_MASK) +#define PMU_MISC1_TOG_LVDSCLK2_OBEN_MASK (0x800U) +#define PMU_MISC1_TOG_LVDSCLK2_OBEN_SHIFT (11U) +#define PMU_MISC1_TOG_LVDSCLK2_OBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_LVDSCLK2_OBEN_SHIFT)) & PMU_MISC1_TOG_LVDSCLK2_OBEN_MASK) #define PMU_MISC1_TOG_LVDSCLK1_IBEN_MASK (0x1000U) #define PMU_MISC1_TOG_LVDSCLK1_IBEN_SHIFT (12U) #define PMU_MISC1_TOG_LVDSCLK1_IBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_LVDSCLK1_IBEN_SHIFT)) & PMU_MISC1_TOG_LVDSCLK1_IBEN_MASK) +#define PMU_MISC1_TOG_LVDSCLK2_IBEN_MASK (0x2000U) +#define PMU_MISC1_TOG_LVDSCLK2_IBEN_SHIFT (13U) +#define PMU_MISC1_TOG_LVDSCLK2_IBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_LVDSCLK2_IBEN_SHIFT)) & PMU_MISC1_TOG_LVDSCLK2_IBEN_MASK) #define PMU_MISC1_TOG_PFD_480_AUTOGATE_EN_MASK (0x10000U) #define PMU_MISC1_TOG_PFD_480_AUTOGATE_EN_SHIFT (16U) #define PMU_MISC1_TOG_PFD_480_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_PFD_480_AUTOGATE_EN_SHIFT)) & PMU_MISC1_TOG_PFD_480_AUTOGATE_EN_MASK) @@ -17004,13 +27439,22 @@ typedef struct { #define PMU_MISC1_TOG_IRQ_DIG_BO_MASK (0x80000000U) #define PMU_MISC1_TOG_IRQ_DIG_BO_SHIFT (31U) #define PMU_MISC1_TOG_IRQ_DIG_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_IRQ_DIG_BO_SHIFT)) & PMU_MISC1_TOG_IRQ_DIG_BO_MASK) +/*! @} */ /*! @name MISC2 - Miscellaneous Control Register */ +/*! @{ */ #define PMU_MISC2_REG0_BO_OFFSET_MASK (0x7U) #define PMU_MISC2_REG0_BO_OFFSET_SHIFT (0U) +/*! REG0_BO_OFFSET + * 0b100..Brownout offset = 0.100V + * 0b111..Brownout offset = 0.175V + */ #define PMU_MISC2_REG0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG0_BO_OFFSET_SHIFT)) & PMU_MISC2_REG0_BO_OFFSET_MASK) #define PMU_MISC2_REG0_BO_STATUS_MASK (0x8U) #define PMU_MISC2_REG0_BO_STATUS_SHIFT (3U) +/*! REG0_BO_STATUS + * 0b1..Brownout, supply is below target minus brownout offset. + */ #define PMU_MISC2_REG0_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG0_BO_STATUS_SHIFT)) & PMU_MISC2_REG0_BO_STATUS_MASK) #define PMU_MISC2_REG0_ENABLE_BO_MASK (0x20U) #define PMU_MISC2_REG0_ENABLE_BO_SHIFT (5U) @@ -17018,11 +27462,35 @@ typedef struct { #define PMU_MISC2_PLL3_disable_MASK (0x80U) #define PMU_MISC2_PLL3_disable_SHIFT (7U) #define PMU_MISC2_PLL3_disable(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_PLL3_disable_SHIFT)) & PMU_MISC2_PLL3_disable_MASK) +#define PMU_MISC2_REG1_BO_OFFSET_MASK (0x700U) +#define PMU_MISC2_REG1_BO_OFFSET_SHIFT (8U) +/*! REG1_BO_OFFSET + * 0b100..Brownout offset = 0.100V + * 0b111..Brownout offset = 0.175V + */ +#define PMU_MISC2_REG1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG1_BO_OFFSET_SHIFT)) & PMU_MISC2_REG1_BO_OFFSET_MASK) +#define PMU_MISC2_REG1_BO_STATUS_MASK (0x800U) +#define PMU_MISC2_REG1_BO_STATUS_SHIFT (11U) +/*! REG1_BO_STATUS + * 0b1..Brownout, supply is below target minus brownout offset. + */ +#define PMU_MISC2_REG1_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG1_BO_STATUS_SHIFT)) & PMU_MISC2_REG1_BO_STATUS_MASK) +#define PMU_MISC2_REG1_ENABLE_BO_MASK (0x2000U) +#define PMU_MISC2_REG1_ENABLE_BO_SHIFT (13U) +#define PMU_MISC2_REG1_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG1_ENABLE_BO_SHIFT)) & PMU_MISC2_REG1_ENABLE_BO_MASK) #define PMU_MISC2_AUDIO_DIV_LSB_MASK (0x8000U) #define PMU_MISC2_AUDIO_DIV_LSB_SHIFT (15U) +/*! AUDIO_DIV_LSB + * 0b0..divide by 1 (Default) + * 0b1..divide by 2 + */ #define PMU_MISC2_AUDIO_DIV_LSB(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_AUDIO_DIV_LSB_SHIFT)) & PMU_MISC2_AUDIO_DIV_LSB_MASK) #define PMU_MISC2_REG2_BO_OFFSET_MASK (0x70000U) #define PMU_MISC2_REG2_BO_OFFSET_SHIFT (16U) +/*! REG2_BO_OFFSET + * 0b100..Brownout offset = 0.100V + * 0b111..Brownout offset = 0.175V + */ #define PMU_MISC2_REG2_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG2_BO_OFFSET_SHIFT)) & PMU_MISC2_REG2_BO_OFFSET_MASK) #define PMU_MISC2_REG2_BO_STATUS_MASK (0x80000U) #define PMU_MISC2_REG2_BO_STATUS_SHIFT (19U) @@ -17035,23 +27503,63 @@ typedef struct { #define PMU_MISC2_REG2_OK(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG2_OK_SHIFT)) & PMU_MISC2_REG2_OK_MASK) #define PMU_MISC2_AUDIO_DIV_MSB_MASK (0x800000U) #define PMU_MISC2_AUDIO_DIV_MSB_SHIFT (23U) +/*! AUDIO_DIV_MSB + * 0b0..divide by 1 (Default) + * 0b1..divide by 2 + */ #define PMU_MISC2_AUDIO_DIV_MSB(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_AUDIO_DIV_MSB_SHIFT)) & PMU_MISC2_AUDIO_DIV_MSB_MASK) #define PMU_MISC2_REG0_STEP_TIME_MASK (0x3000000U) #define PMU_MISC2_REG0_STEP_TIME_SHIFT (24U) +/*! REG0_STEP_TIME + * 0b00..64 + * 0b01..128 + * 0b10..256 + * 0b11..512 + */ #define PMU_MISC2_REG0_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG0_STEP_TIME_SHIFT)) & PMU_MISC2_REG0_STEP_TIME_MASK) +#define PMU_MISC2_REG1_STEP_TIME_MASK (0xC000000U) +#define PMU_MISC2_REG1_STEP_TIME_SHIFT (26U) +/*! REG1_STEP_TIME + * 0b00..64 + * 0b01..128 + * 0b10..256 + * 0b11..512 + */ +#define PMU_MISC2_REG1_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG1_STEP_TIME_SHIFT)) & PMU_MISC2_REG1_STEP_TIME_MASK) #define PMU_MISC2_REG2_STEP_TIME_MASK (0x30000000U) #define PMU_MISC2_REG2_STEP_TIME_SHIFT (28U) +/*! REG2_STEP_TIME + * 0b00..64 + * 0b01..128 + * 0b10..256 + * 0b11..512 + */ #define PMU_MISC2_REG2_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG2_STEP_TIME_SHIFT)) & PMU_MISC2_REG2_STEP_TIME_MASK) #define PMU_MISC2_VIDEO_DIV_MASK (0xC0000000U) #define PMU_MISC2_VIDEO_DIV_SHIFT (30U) +/*! VIDEO_DIV + * 0b00..divide by 1 (Default) + * 0b01..divide by 2 + * 0b10..divide by 1 + * 0b11..divide by 4 + */ #define PMU_MISC2_VIDEO_DIV(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_VIDEO_DIV_SHIFT)) & PMU_MISC2_VIDEO_DIV_MASK) +/*! @} */ /*! @name MISC2_SET - Miscellaneous Control Register */ +/*! @{ */ #define PMU_MISC2_SET_REG0_BO_OFFSET_MASK (0x7U) #define PMU_MISC2_SET_REG0_BO_OFFSET_SHIFT (0U) +/*! REG0_BO_OFFSET + * 0b100..Brownout offset = 0.100V + * 0b111..Brownout offset = 0.175V + */ #define PMU_MISC2_SET_REG0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG0_BO_OFFSET_SHIFT)) & PMU_MISC2_SET_REG0_BO_OFFSET_MASK) #define PMU_MISC2_SET_REG0_BO_STATUS_MASK (0x8U) #define PMU_MISC2_SET_REG0_BO_STATUS_SHIFT (3U) +/*! REG0_BO_STATUS + * 0b1..Brownout, supply is below target minus brownout offset. + */ #define PMU_MISC2_SET_REG0_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG0_BO_STATUS_SHIFT)) & PMU_MISC2_SET_REG0_BO_STATUS_MASK) #define PMU_MISC2_SET_REG0_ENABLE_BO_MASK (0x20U) #define PMU_MISC2_SET_REG0_ENABLE_BO_SHIFT (5U) @@ -17059,11 +27567,35 @@ typedef struct { #define PMU_MISC2_SET_PLL3_disable_MASK (0x80U) #define PMU_MISC2_SET_PLL3_disable_SHIFT (7U) #define PMU_MISC2_SET_PLL3_disable(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_PLL3_disable_SHIFT)) & PMU_MISC2_SET_PLL3_disable_MASK) +#define PMU_MISC2_SET_REG1_BO_OFFSET_MASK (0x700U) +#define PMU_MISC2_SET_REG1_BO_OFFSET_SHIFT (8U) +/*! REG1_BO_OFFSET + * 0b100..Brownout offset = 0.100V + * 0b111..Brownout offset = 0.175V + */ +#define PMU_MISC2_SET_REG1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG1_BO_OFFSET_SHIFT)) & PMU_MISC2_SET_REG1_BO_OFFSET_MASK) +#define PMU_MISC2_SET_REG1_BO_STATUS_MASK (0x800U) +#define PMU_MISC2_SET_REG1_BO_STATUS_SHIFT (11U) +/*! REG1_BO_STATUS + * 0b1..Brownout, supply is below target minus brownout offset. + */ +#define PMU_MISC2_SET_REG1_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG1_BO_STATUS_SHIFT)) & PMU_MISC2_SET_REG1_BO_STATUS_MASK) +#define PMU_MISC2_SET_REG1_ENABLE_BO_MASK (0x2000U) +#define PMU_MISC2_SET_REG1_ENABLE_BO_SHIFT (13U) +#define PMU_MISC2_SET_REG1_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG1_ENABLE_BO_SHIFT)) & PMU_MISC2_SET_REG1_ENABLE_BO_MASK) #define PMU_MISC2_SET_AUDIO_DIV_LSB_MASK (0x8000U) #define PMU_MISC2_SET_AUDIO_DIV_LSB_SHIFT (15U) +/*! AUDIO_DIV_LSB + * 0b0..divide by 1 (Default) + * 0b1..divide by 2 + */ #define PMU_MISC2_SET_AUDIO_DIV_LSB(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_AUDIO_DIV_LSB_SHIFT)) & PMU_MISC2_SET_AUDIO_DIV_LSB_MASK) #define PMU_MISC2_SET_REG2_BO_OFFSET_MASK (0x70000U) #define PMU_MISC2_SET_REG2_BO_OFFSET_SHIFT (16U) +/*! REG2_BO_OFFSET + * 0b100..Brownout offset = 0.100V + * 0b111..Brownout offset = 0.175V + */ #define PMU_MISC2_SET_REG2_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG2_BO_OFFSET_SHIFT)) & PMU_MISC2_SET_REG2_BO_OFFSET_MASK) #define PMU_MISC2_SET_REG2_BO_STATUS_MASK (0x80000U) #define PMU_MISC2_SET_REG2_BO_STATUS_SHIFT (19U) @@ -17076,23 +27608,63 @@ typedef struct { #define PMU_MISC2_SET_REG2_OK(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG2_OK_SHIFT)) & PMU_MISC2_SET_REG2_OK_MASK) #define PMU_MISC2_SET_AUDIO_DIV_MSB_MASK (0x800000U) #define PMU_MISC2_SET_AUDIO_DIV_MSB_SHIFT (23U) +/*! AUDIO_DIV_MSB + * 0b0..divide by 1 (Default) + * 0b1..divide by 2 + */ #define PMU_MISC2_SET_AUDIO_DIV_MSB(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_AUDIO_DIV_MSB_SHIFT)) & PMU_MISC2_SET_AUDIO_DIV_MSB_MASK) #define PMU_MISC2_SET_REG0_STEP_TIME_MASK (0x3000000U) #define PMU_MISC2_SET_REG0_STEP_TIME_SHIFT (24U) +/*! REG0_STEP_TIME + * 0b00..64 + * 0b01..128 + * 0b10..256 + * 0b11..512 + */ #define PMU_MISC2_SET_REG0_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG0_STEP_TIME_SHIFT)) & PMU_MISC2_SET_REG0_STEP_TIME_MASK) +#define PMU_MISC2_SET_REG1_STEP_TIME_MASK (0xC000000U) +#define PMU_MISC2_SET_REG1_STEP_TIME_SHIFT (26U) +/*! REG1_STEP_TIME + * 0b00..64 + * 0b01..128 + * 0b10..256 + * 0b11..512 + */ +#define PMU_MISC2_SET_REG1_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG1_STEP_TIME_SHIFT)) & PMU_MISC2_SET_REG1_STEP_TIME_MASK) #define PMU_MISC2_SET_REG2_STEP_TIME_MASK (0x30000000U) #define PMU_MISC2_SET_REG2_STEP_TIME_SHIFT (28U) +/*! REG2_STEP_TIME + * 0b00..64 + * 0b01..128 + * 0b10..256 + * 0b11..512 + */ #define PMU_MISC2_SET_REG2_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG2_STEP_TIME_SHIFT)) & PMU_MISC2_SET_REG2_STEP_TIME_MASK) #define PMU_MISC2_SET_VIDEO_DIV_MASK (0xC0000000U) #define PMU_MISC2_SET_VIDEO_DIV_SHIFT (30U) +/*! VIDEO_DIV + * 0b00..divide by 1 (Default) + * 0b01..divide by 2 + * 0b10..divide by 1 + * 0b11..divide by 4 + */ #define PMU_MISC2_SET_VIDEO_DIV(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_VIDEO_DIV_SHIFT)) & PMU_MISC2_SET_VIDEO_DIV_MASK) +/*! @} */ /*! @name MISC2_CLR - Miscellaneous Control Register */ +/*! @{ */ #define PMU_MISC2_CLR_REG0_BO_OFFSET_MASK (0x7U) #define PMU_MISC2_CLR_REG0_BO_OFFSET_SHIFT (0U) +/*! REG0_BO_OFFSET + * 0b100..Brownout offset = 0.100V + * 0b111..Brownout offset = 0.175V + */ #define PMU_MISC2_CLR_REG0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG0_BO_OFFSET_SHIFT)) & PMU_MISC2_CLR_REG0_BO_OFFSET_MASK) #define PMU_MISC2_CLR_REG0_BO_STATUS_MASK (0x8U) #define PMU_MISC2_CLR_REG0_BO_STATUS_SHIFT (3U) +/*! REG0_BO_STATUS + * 0b1..Brownout, supply is below target minus brownout offset. + */ #define PMU_MISC2_CLR_REG0_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG0_BO_STATUS_SHIFT)) & PMU_MISC2_CLR_REG0_BO_STATUS_MASK) #define PMU_MISC2_CLR_REG0_ENABLE_BO_MASK (0x20U) #define PMU_MISC2_CLR_REG0_ENABLE_BO_SHIFT (5U) @@ -17100,11 +27672,35 @@ typedef struct { #define PMU_MISC2_CLR_PLL3_disable_MASK (0x80U) #define PMU_MISC2_CLR_PLL3_disable_SHIFT (7U) #define PMU_MISC2_CLR_PLL3_disable(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_PLL3_disable_SHIFT)) & PMU_MISC2_CLR_PLL3_disable_MASK) +#define PMU_MISC2_CLR_REG1_BO_OFFSET_MASK (0x700U) +#define PMU_MISC2_CLR_REG1_BO_OFFSET_SHIFT (8U) +/*! REG1_BO_OFFSET + * 0b100..Brownout offset = 0.100V + * 0b111..Brownout offset = 0.175V + */ +#define PMU_MISC2_CLR_REG1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG1_BO_OFFSET_SHIFT)) & PMU_MISC2_CLR_REG1_BO_OFFSET_MASK) +#define PMU_MISC2_CLR_REG1_BO_STATUS_MASK (0x800U) +#define PMU_MISC2_CLR_REG1_BO_STATUS_SHIFT (11U) +/*! REG1_BO_STATUS + * 0b1..Brownout, supply is below target minus brownout offset. + */ +#define PMU_MISC2_CLR_REG1_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG1_BO_STATUS_SHIFT)) & PMU_MISC2_CLR_REG1_BO_STATUS_MASK) +#define PMU_MISC2_CLR_REG1_ENABLE_BO_MASK (0x2000U) +#define PMU_MISC2_CLR_REG1_ENABLE_BO_SHIFT (13U) +#define PMU_MISC2_CLR_REG1_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG1_ENABLE_BO_SHIFT)) & PMU_MISC2_CLR_REG1_ENABLE_BO_MASK) #define PMU_MISC2_CLR_AUDIO_DIV_LSB_MASK (0x8000U) #define PMU_MISC2_CLR_AUDIO_DIV_LSB_SHIFT (15U) +/*! AUDIO_DIV_LSB + * 0b0..divide by 1 (Default) + * 0b1..divide by 2 + */ #define PMU_MISC2_CLR_AUDIO_DIV_LSB(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_AUDIO_DIV_LSB_SHIFT)) & PMU_MISC2_CLR_AUDIO_DIV_LSB_MASK) #define PMU_MISC2_CLR_REG2_BO_OFFSET_MASK (0x70000U) #define PMU_MISC2_CLR_REG2_BO_OFFSET_SHIFT (16U) +/*! REG2_BO_OFFSET + * 0b100..Brownout offset = 0.100V + * 0b111..Brownout offset = 0.175V + */ #define PMU_MISC2_CLR_REG2_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG2_BO_OFFSET_SHIFT)) & PMU_MISC2_CLR_REG2_BO_OFFSET_MASK) #define PMU_MISC2_CLR_REG2_BO_STATUS_MASK (0x80000U) #define PMU_MISC2_CLR_REG2_BO_STATUS_SHIFT (19U) @@ -17117,23 +27713,63 @@ typedef struct { #define PMU_MISC2_CLR_REG2_OK(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG2_OK_SHIFT)) & PMU_MISC2_CLR_REG2_OK_MASK) #define PMU_MISC2_CLR_AUDIO_DIV_MSB_MASK (0x800000U) #define PMU_MISC2_CLR_AUDIO_DIV_MSB_SHIFT (23U) +/*! AUDIO_DIV_MSB + * 0b0..divide by 1 (Default) + * 0b1..divide by 2 + */ #define PMU_MISC2_CLR_AUDIO_DIV_MSB(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_AUDIO_DIV_MSB_SHIFT)) & PMU_MISC2_CLR_AUDIO_DIV_MSB_MASK) #define PMU_MISC2_CLR_REG0_STEP_TIME_MASK (0x3000000U) #define PMU_MISC2_CLR_REG0_STEP_TIME_SHIFT (24U) +/*! REG0_STEP_TIME + * 0b00..64 + * 0b01..128 + * 0b10..256 + * 0b11..512 + */ #define PMU_MISC2_CLR_REG0_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG0_STEP_TIME_SHIFT)) & PMU_MISC2_CLR_REG0_STEP_TIME_MASK) +#define PMU_MISC2_CLR_REG1_STEP_TIME_MASK (0xC000000U) +#define PMU_MISC2_CLR_REG1_STEP_TIME_SHIFT (26U) +/*! REG1_STEP_TIME + * 0b00..64 + * 0b01..128 + * 0b10..256 + * 0b11..512 + */ +#define PMU_MISC2_CLR_REG1_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG1_STEP_TIME_SHIFT)) & PMU_MISC2_CLR_REG1_STEP_TIME_MASK) #define PMU_MISC2_CLR_REG2_STEP_TIME_MASK (0x30000000U) #define PMU_MISC2_CLR_REG2_STEP_TIME_SHIFT (28U) +/*! REG2_STEP_TIME + * 0b00..64 + * 0b01..128 + * 0b10..256 + * 0b11..512 + */ #define PMU_MISC2_CLR_REG2_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG2_STEP_TIME_SHIFT)) & PMU_MISC2_CLR_REG2_STEP_TIME_MASK) #define PMU_MISC2_CLR_VIDEO_DIV_MASK (0xC0000000U) #define PMU_MISC2_CLR_VIDEO_DIV_SHIFT (30U) +/*! VIDEO_DIV + * 0b00..divide by 1 (Default) + * 0b01..divide by 2 + * 0b10..divide by 1 + * 0b11..divide by 4 + */ #define PMU_MISC2_CLR_VIDEO_DIV(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_VIDEO_DIV_SHIFT)) & PMU_MISC2_CLR_VIDEO_DIV_MASK) +/*! @} */ /*! @name MISC2_TOG - Miscellaneous Control Register */ +/*! @{ */ #define PMU_MISC2_TOG_REG0_BO_OFFSET_MASK (0x7U) #define PMU_MISC2_TOG_REG0_BO_OFFSET_SHIFT (0U) +/*! REG0_BO_OFFSET + * 0b100..Brownout offset = 0.100V + * 0b111..Brownout offset = 0.175V + */ #define PMU_MISC2_TOG_REG0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG0_BO_OFFSET_SHIFT)) & PMU_MISC2_TOG_REG0_BO_OFFSET_MASK) #define PMU_MISC2_TOG_REG0_BO_STATUS_MASK (0x8U) #define PMU_MISC2_TOG_REG0_BO_STATUS_SHIFT (3U) +/*! REG0_BO_STATUS + * 0b1..Brownout, supply is below target minus brownout offset. + */ #define PMU_MISC2_TOG_REG0_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG0_BO_STATUS_SHIFT)) & PMU_MISC2_TOG_REG0_BO_STATUS_MASK) #define PMU_MISC2_TOG_REG0_ENABLE_BO_MASK (0x20U) #define PMU_MISC2_TOG_REG0_ENABLE_BO_SHIFT (5U) @@ -17141,11 +27777,35 @@ typedef struct { #define PMU_MISC2_TOG_PLL3_disable_MASK (0x80U) #define PMU_MISC2_TOG_PLL3_disable_SHIFT (7U) #define PMU_MISC2_TOG_PLL3_disable(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_PLL3_disable_SHIFT)) & PMU_MISC2_TOG_PLL3_disable_MASK) +#define PMU_MISC2_TOG_REG1_BO_OFFSET_MASK (0x700U) +#define PMU_MISC2_TOG_REG1_BO_OFFSET_SHIFT (8U) +/*! REG1_BO_OFFSET + * 0b100..Brownout offset = 0.100V + * 0b111..Brownout offset = 0.175V + */ +#define PMU_MISC2_TOG_REG1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG1_BO_OFFSET_SHIFT)) & PMU_MISC2_TOG_REG1_BO_OFFSET_MASK) +#define PMU_MISC2_TOG_REG1_BO_STATUS_MASK (0x800U) +#define PMU_MISC2_TOG_REG1_BO_STATUS_SHIFT (11U) +/*! REG1_BO_STATUS + * 0b1..Brownout, supply is below target minus brownout offset. + */ +#define PMU_MISC2_TOG_REG1_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG1_BO_STATUS_SHIFT)) & PMU_MISC2_TOG_REG1_BO_STATUS_MASK) +#define PMU_MISC2_TOG_REG1_ENABLE_BO_MASK (0x2000U) +#define PMU_MISC2_TOG_REG1_ENABLE_BO_SHIFT (13U) +#define PMU_MISC2_TOG_REG1_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG1_ENABLE_BO_SHIFT)) & PMU_MISC2_TOG_REG1_ENABLE_BO_MASK) #define PMU_MISC2_TOG_AUDIO_DIV_LSB_MASK (0x8000U) #define PMU_MISC2_TOG_AUDIO_DIV_LSB_SHIFT (15U) +/*! AUDIO_DIV_LSB + * 0b0..divide by 1 (Default) + * 0b1..divide by 2 + */ #define PMU_MISC2_TOG_AUDIO_DIV_LSB(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_AUDIO_DIV_LSB_SHIFT)) & PMU_MISC2_TOG_AUDIO_DIV_LSB_MASK) #define PMU_MISC2_TOG_REG2_BO_OFFSET_MASK (0x70000U) #define PMU_MISC2_TOG_REG2_BO_OFFSET_SHIFT (16U) +/*! REG2_BO_OFFSET + * 0b100..Brownout offset = 0.100V + * 0b111..Brownout offset = 0.175V + */ #define PMU_MISC2_TOG_REG2_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG2_BO_OFFSET_SHIFT)) & PMU_MISC2_TOG_REG2_BO_OFFSET_MASK) #define PMU_MISC2_TOG_REG2_BO_STATUS_MASK (0x80000U) #define PMU_MISC2_TOG_REG2_BO_STATUS_SHIFT (19U) @@ -17158,16 +27818,48 @@ typedef struct { #define PMU_MISC2_TOG_REG2_OK(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG2_OK_SHIFT)) & PMU_MISC2_TOG_REG2_OK_MASK) #define PMU_MISC2_TOG_AUDIO_DIV_MSB_MASK (0x800000U) #define PMU_MISC2_TOG_AUDIO_DIV_MSB_SHIFT (23U) +/*! AUDIO_DIV_MSB + * 0b0..divide by 1 (Default) + * 0b1..divide by 2 + */ #define PMU_MISC2_TOG_AUDIO_DIV_MSB(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_AUDIO_DIV_MSB_SHIFT)) & PMU_MISC2_TOG_AUDIO_DIV_MSB_MASK) #define PMU_MISC2_TOG_REG0_STEP_TIME_MASK (0x3000000U) #define PMU_MISC2_TOG_REG0_STEP_TIME_SHIFT (24U) +/*! REG0_STEP_TIME + * 0b00..64 + * 0b01..128 + * 0b10..256 + * 0b11..512 + */ #define PMU_MISC2_TOG_REG0_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG0_STEP_TIME_SHIFT)) & PMU_MISC2_TOG_REG0_STEP_TIME_MASK) +#define PMU_MISC2_TOG_REG1_STEP_TIME_MASK (0xC000000U) +#define PMU_MISC2_TOG_REG1_STEP_TIME_SHIFT (26U) +/*! REG1_STEP_TIME + * 0b00..64 + * 0b01..128 + * 0b10..256 + * 0b11..512 + */ +#define PMU_MISC2_TOG_REG1_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG1_STEP_TIME_SHIFT)) & PMU_MISC2_TOG_REG1_STEP_TIME_MASK) #define PMU_MISC2_TOG_REG2_STEP_TIME_MASK (0x30000000U) #define PMU_MISC2_TOG_REG2_STEP_TIME_SHIFT (28U) +/*! REG2_STEP_TIME + * 0b00..64 + * 0b01..128 + * 0b10..256 + * 0b11..512 + */ #define PMU_MISC2_TOG_REG2_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG2_STEP_TIME_SHIFT)) & PMU_MISC2_TOG_REG2_STEP_TIME_MASK) #define PMU_MISC2_TOG_VIDEO_DIV_MASK (0xC0000000U) #define PMU_MISC2_TOG_VIDEO_DIV_SHIFT (30U) +/*! VIDEO_DIV + * 0b00..divide by 1 (Default) + * 0b01..divide by 2 + * 0b10..divide by 1 + * 0b11..divide by 4 + */ #define PMU_MISC2_TOG_VIDEO_DIV(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_VIDEO_DIV_SHIFT)) & PMU_MISC2_TOG_VIDEO_DIV_MASK) +/*! @} */ /*! @@ -17270,39 +27962,74 @@ typedef struct { */ /*! @name CNT - Counter Register */ +/*! @{ */ #define PWM_CNT_CNT_MASK (0xFFFFU) #define PWM_CNT_CNT_SHIFT (0U) #define PWM_CNT_CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CNT_CNT_SHIFT)) & PWM_CNT_CNT_MASK) +/*! @} */ /* The count of PWM_CNT */ #define PWM_CNT_COUNT (4U) /*! @name INIT - Initial Count Register */ +/*! @{ */ #define PWM_INIT_INIT_MASK (0xFFFFU) #define PWM_INIT_INIT_SHIFT (0U) #define PWM_INIT_INIT(x) (((uint16_t)(((uint16_t)(x)) << PWM_INIT_INIT_SHIFT)) & PWM_INIT_INIT_MASK) +/*! @} */ /* The count of PWM_INIT */ #define PWM_INIT_COUNT (4U) /*! @name CTRL2 - Control 2 Register */ +/*! @{ */ #define PWM_CTRL2_CLK_SEL_MASK (0x3U) #define PWM_CTRL2_CLK_SEL_SHIFT (0U) +/*! CLK_SEL - Clock Source Select + * 0b00..The IPBus clock is used as the clock for the local prescaler and counter. + * 0b01..EXT_CLK is used as the clock for the local prescaler and counter. + * 0b10..Submodule 0's clock (AUX_CLK) is used as the source clock for the local prescaler and counter. This setting should not be used in submodule 0 as it will force the clock to logic 0. + * 0b11..reserved + */ #define PWM_CTRL2_CLK_SEL(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_CLK_SEL_SHIFT)) & PWM_CTRL2_CLK_SEL_MASK) #define PWM_CTRL2_RELOAD_SEL_MASK (0x4U) #define PWM_CTRL2_RELOAD_SEL_SHIFT (2U) +/*! RELOAD_SEL - Reload Source Select + * 0b0..The local RELOAD signal is used to reload registers. + * 0b1..The master RELOAD signal (from submodule 0) is used to reload registers. This setting should not be used in submodule 0 as it will force the RELOAD signal to logic 0. + */ #define PWM_CTRL2_RELOAD_SEL(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_RELOAD_SEL_SHIFT)) & PWM_CTRL2_RELOAD_SEL_MASK) #define PWM_CTRL2_FORCE_SEL_MASK (0x38U) #define PWM_CTRL2_FORCE_SEL_SHIFT (3U) +/*! FORCE_SEL - This read/write bit determines the source of the FORCE OUTPUT signal for this submodule. + * 0b000..The local force signal, CTRL2[FORCE], from this submodule is used to force updates. + * 0b001..The master force signal from submodule 0 is used to force updates. This setting should not be used in submodule 0 as it will hold the FORCE OUTPUT signal to logic 0. + * 0b010..The local reload signal from this submodule is used to force updates without regard to the state of LDOK. + * 0b011..The master reload signal from submodule0 is used to force updates if LDOK is set. This setting should not be used in submodule0 as it will hold the FORCE OUTPUT signal to logic 0. + * 0b100..The local sync signal from this submodule is used to force updates. + * 0b101..The master sync signal from submodule0 is used to force updates. This setting should not be used in submodule0 as it will hold the FORCE OUTPUT signal to logic 0. + * 0b110..The external force signal, EXT_FORCE, from outside the PWM module causes updates. + * 0b111..The external sync signal, EXT_SYNC, from outside the PWM module causes updates. + */ #define PWM_CTRL2_FORCE_SEL(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_FORCE_SEL_SHIFT)) & PWM_CTRL2_FORCE_SEL_MASK) #define PWM_CTRL2_FORCE_MASK (0x40U) #define PWM_CTRL2_FORCE_SHIFT (6U) #define PWM_CTRL2_FORCE(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_FORCE_SHIFT)) & PWM_CTRL2_FORCE_MASK) #define PWM_CTRL2_FRCEN_MASK (0x80U) #define PWM_CTRL2_FRCEN_SHIFT (7U) +/*! FRCEN - FRCEN + * 0b0..Initialization from a FORCE_OUT is disabled. + * 0b1..Initialization from a FORCE_OUT is enabled. + */ #define PWM_CTRL2_FRCEN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_FRCEN_SHIFT)) & PWM_CTRL2_FRCEN_MASK) #define PWM_CTRL2_INIT_SEL_MASK (0x300U) #define PWM_CTRL2_INIT_SEL_SHIFT (8U) +/*! INIT_SEL - Initialization Control Select + * 0b00..Local sync (PWM_X) causes initialization. + * 0b01..Master reload from submodule 0 causes initialization. This setting should not be used in submodule 0 as it will force the INIT signal to logic 0. The submodule counter will only reinitialize when a master reload occurs. + * 0b10..Master sync from submodule 0 causes initialization. This setting should not be used in submodule 0 as it will force the INIT signal to logic 0. + * 0b11..EXT_SYNC causes initialization. + */ #define PWM_CTRL2_INIT_SEL(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_INIT_SEL_SHIFT)) & PWM_CTRL2_INIT_SEL_MASK) #define PWM_CTRL2_PWMX_INIT_MASK (0x400U) #define PWM_CTRL2_PWMX_INIT_SHIFT (10U) @@ -17315,6 +28042,10 @@ typedef struct { #define PWM_CTRL2_PWM23_INIT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_PWM23_INIT_SHIFT)) & PWM_CTRL2_PWM23_INIT_MASK) #define PWM_CTRL2_INDEP_MASK (0x2000U) #define PWM_CTRL2_INDEP_SHIFT (13U) +/*! INDEP - Independent or Complementary Pair Operation + * 0b0..PWM_A and PWM_B form a complementary PWM pair. + * 0b1..PWM_A and PWM_B outputs are independent PWMs. + */ #define PWM_CTRL2_INDEP(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_INDEP_SHIFT)) & PWM_CTRL2_INDEP_MASK) #define PWM_CTRL2_WAITEN_MASK (0x4000U) #define PWM_CTRL2_WAITEN_SHIFT (14U) @@ -17322,171 +28053,301 @@ typedef struct { #define PWM_CTRL2_DBGEN_MASK (0x8000U) #define PWM_CTRL2_DBGEN_SHIFT (15U) #define PWM_CTRL2_DBGEN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_DBGEN_SHIFT)) & PWM_CTRL2_DBGEN_MASK) +/*! @} */ /* The count of PWM_CTRL2 */ #define PWM_CTRL2_COUNT (4U) /*! @name CTRL - Control Register */ +/*! @{ */ #define PWM_CTRL_DBLEN_MASK (0x1U) #define PWM_CTRL_DBLEN_SHIFT (0U) +/*! DBLEN - Double Switching Enable + * 0b0..Double switching disabled. + * 0b1..Double switching enabled. + */ #define PWM_CTRL_DBLEN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_DBLEN_SHIFT)) & PWM_CTRL_DBLEN_MASK) #define PWM_CTRL_DBLX_MASK (0x2U) #define PWM_CTRL_DBLX_SHIFT (1U) +/*! DBLX - PWMX Double Switching Enable + * 0b0..PWMX double pulse disabled. + * 0b1..PWMX double pulse enabled. + */ #define PWM_CTRL_DBLX(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_DBLX_SHIFT)) & PWM_CTRL_DBLX_MASK) #define PWM_CTRL_LDMOD_MASK (0x4U) #define PWM_CTRL_LDMOD_SHIFT (2U) +/*! LDMOD - Load Mode Select + * 0b0..Buffered registers of this submodule are loaded and take effect at the next PWM reload if MCTRL[LDOK] is set. + * 0b1..Buffered registers of this submodule are loaded and take effect immediately upon MCTRL[LDOK] being set. In this case it is not necessary to set CTRL[FULL] or CTRL[HALF]. + */ #define PWM_CTRL_LDMOD(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_LDMOD_SHIFT)) & PWM_CTRL_LDMOD_MASK) #define PWM_CTRL_SPLIT_MASK (0x8U) #define PWM_CTRL_SPLIT_SHIFT (3U) +/*! SPLIT - Split the DBLPWM signal to PWMA and PWMB + * 0b0..DBLPWM is not split. PWMA and PWMB each have double pulses. + * 0b1..DBLPWM is split to PWMA and PWMB. + */ #define PWM_CTRL_SPLIT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_SPLIT_SHIFT)) & PWM_CTRL_SPLIT_MASK) #define PWM_CTRL_PRSC_MASK (0x70U) #define PWM_CTRL_PRSC_SHIFT (4U) +/*! PRSC - Prescaler + * 0b000..PWM clock frequency = fclk + * 0b001..PWM clock frequency = fclk/2 + * 0b010..PWM clock frequency = fclk/4 + * 0b011..PWM clock frequency = fclk/8 + * 0b100..PWM clock frequency = fclk/16 + * 0b101..PWM clock frequency = fclk/32 + * 0b110..PWM clock frequency = fclk/64 + * 0b111..PWM clock frequency = fclk/128 + */ #define PWM_CTRL_PRSC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_PRSC_SHIFT)) & PWM_CTRL_PRSC_MASK) #define PWM_CTRL_COMPMODE_MASK (0x80U) #define PWM_CTRL_COMPMODE_SHIFT (7U) +/*! COMPMODE - Compare Mode + * 0b0..The VAL* registers and the PWM counter are compared using an "equal to" method. This means that PWM edges are only produced when the counter is equal to one of the VAL* register values. This implies that a PWMA output that is high at the end of a period will maintain this state until a match with VAL3 clears the output in the following period. + * 0b1..The VAL* registers and the PWM counter are compared using an "equal to or greater than" method. This means that PWM edges are produced when the counter is equal to or greater than one of the VAL* register values. This implies that a PWMA output that is high at the end of a period could go low at the start of the next period if the starting counter value is greater than (but not necessarily equal to) the new VAL3 value. + */ #define PWM_CTRL_COMPMODE(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_COMPMODE_SHIFT)) & PWM_CTRL_COMPMODE_MASK) #define PWM_CTRL_DT_MASK (0x300U) #define PWM_CTRL_DT_SHIFT (8U) #define PWM_CTRL_DT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_DT_SHIFT)) & PWM_CTRL_DT_MASK) #define PWM_CTRL_FULL_MASK (0x400U) #define PWM_CTRL_FULL_SHIFT (10U) +/*! FULL - Full Cycle Reload + * 0b0..Full-cycle reloads disabled. + * 0b1..Full-cycle reloads enabled. + */ #define PWM_CTRL_FULL(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_FULL_SHIFT)) & PWM_CTRL_FULL_MASK) #define PWM_CTRL_HALF_MASK (0x800U) #define PWM_CTRL_HALF_SHIFT (11U) +/*! HALF - Half Cycle Reload + * 0b0..Half-cycle reloads disabled. + * 0b1..Half-cycle reloads enabled. + */ #define PWM_CTRL_HALF(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_HALF_SHIFT)) & PWM_CTRL_HALF_MASK) #define PWM_CTRL_LDFQ_MASK (0xF000U) #define PWM_CTRL_LDFQ_SHIFT (12U) +/*! LDFQ - Load Frequency + * 0b0000..Every PWM opportunity + * 0b0001..Every 2 PWM opportunities + * 0b0010..Every 3 PWM opportunities + * 0b0011..Every 4 PWM opportunities + * 0b0100..Every 5 PWM opportunities + * 0b0101..Every 6 PWM opportunities + * 0b0110..Every 7 PWM opportunities + * 0b0111..Every 8 PWM opportunities + * 0b1000..Every 9 PWM opportunities + * 0b1001..Every 10 PWM opportunities + * 0b1010..Every 11 PWM opportunities + * 0b1011..Every 12 PWM opportunities + * 0b1100..Every 13 PWM opportunities + * 0b1101..Every 14 PWM opportunities + * 0b1110..Every 15 PWM opportunities + * 0b1111..Every 16 PWM opportunities + */ #define PWM_CTRL_LDFQ(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_LDFQ_SHIFT)) & PWM_CTRL_LDFQ_MASK) +/*! @} */ /* The count of PWM_CTRL */ #define PWM_CTRL_COUNT (4U) /*! @name VAL0 - Value Register 0 */ +/*! @{ */ #define PWM_VAL0_VAL0_MASK (0xFFFFU) #define PWM_VAL0_VAL0_SHIFT (0U) #define PWM_VAL0_VAL0(x) (((uint16_t)(((uint16_t)(x)) << PWM_VAL0_VAL0_SHIFT)) & PWM_VAL0_VAL0_MASK) +/*! @} */ /* The count of PWM_VAL0 */ #define PWM_VAL0_COUNT (4U) /*! @name FRACVAL1 - Fractional Value Register 1 */ +/*! @{ */ #define PWM_FRACVAL1_FRACVAL1_MASK (0xF800U) #define PWM_FRACVAL1_FRACVAL1_SHIFT (11U) #define PWM_FRACVAL1_FRACVAL1(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRACVAL1_FRACVAL1_SHIFT)) & PWM_FRACVAL1_FRACVAL1_MASK) +/*! @} */ /* The count of PWM_FRACVAL1 */ #define PWM_FRACVAL1_COUNT (4U) /*! @name VAL1 - Value Register 1 */ +/*! @{ */ #define PWM_VAL1_VAL1_MASK (0xFFFFU) #define PWM_VAL1_VAL1_SHIFT (0U) #define PWM_VAL1_VAL1(x) (((uint16_t)(((uint16_t)(x)) << PWM_VAL1_VAL1_SHIFT)) & PWM_VAL1_VAL1_MASK) +/*! @} */ /* The count of PWM_VAL1 */ #define PWM_VAL1_COUNT (4U) /*! @name FRACVAL2 - Fractional Value Register 2 */ +/*! @{ */ #define PWM_FRACVAL2_FRACVAL2_MASK (0xF800U) #define PWM_FRACVAL2_FRACVAL2_SHIFT (11U) #define PWM_FRACVAL2_FRACVAL2(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRACVAL2_FRACVAL2_SHIFT)) & PWM_FRACVAL2_FRACVAL2_MASK) +/*! @} */ /* The count of PWM_FRACVAL2 */ #define PWM_FRACVAL2_COUNT (4U) /*! @name VAL2 - Value Register 2 */ +/*! @{ */ #define PWM_VAL2_VAL2_MASK (0xFFFFU) #define PWM_VAL2_VAL2_SHIFT (0U) #define PWM_VAL2_VAL2(x) (((uint16_t)(((uint16_t)(x)) << PWM_VAL2_VAL2_SHIFT)) & PWM_VAL2_VAL2_MASK) +/*! @} */ /* The count of PWM_VAL2 */ #define PWM_VAL2_COUNT (4U) /*! @name FRACVAL3 - Fractional Value Register 3 */ +/*! @{ */ #define PWM_FRACVAL3_FRACVAL3_MASK (0xF800U) #define PWM_FRACVAL3_FRACVAL3_SHIFT (11U) #define PWM_FRACVAL3_FRACVAL3(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRACVAL3_FRACVAL3_SHIFT)) & PWM_FRACVAL3_FRACVAL3_MASK) +/*! @} */ /* The count of PWM_FRACVAL3 */ #define PWM_FRACVAL3_COUNT (4U) /*! @name VAL3 - Value Register 3 */ +/*! @{ */ #define PWM_VAL3_VAL3_MASK (0xFFFFU) #define PWM_VAL3_VAL3_SHIFT (0U) #define PWM_VAL3_VAL3(x) (((uint16_t)(((uint16_t)(x)) << PWM_VAL3_VAL3_SHIFT)) & PWM_VAL3_VAL3_MASK) +/*! @} */ /* The count of PWM_VAL3 */ #define PWM_VAL3_COUNT (4U) /*! @name FRACVAL4 - Fractional Value Register 4 */ +/*! @{ */ #define PWM_FRACVAL4_FRACVAL4_MASK (0xF800U) #define PWM_FRACVAL4_FRACVAL4_SHIFT (11U) #define PWM_FRACVAL4_FRACVAL4(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRACVAL4_FRACVAL4_SHIFT)) & PWM_FRACVAL4_FRACVAL4_MASK) +/*! @} */ /* The count of PWM_FRACVAL4 */ #define PWM_FRACVAL4_COUNT (4U) /*! @name VAL4 - Value Register 4 */ +/*! @{ */ #define PWM_VAL4_VAL4_MASK (0xFFFFU) #define PWM_VAL4_VAL4_SHIFT (0U) #define PWM_VAL4_VAL4(x) (((uint16_t)(((uint16_t)(x)) << PWM_VAL4_VAL4_SHIFT)) & PWM_VAL4_VAL4_MASK) +/*! @} */ /* The count of PWM_VAL4 */ #define PWM_VAL4_COUNT (4U) /*! @name FRACVAL5 - Fractional Value Register 5 */ +/*! @{ */ #define PWM_FRACVAL5_FRACVAL5_MASK (0xF800U) #define PWM_FRACVAL5_FRACVAL5_SHIFT (11U) #define PWM_FRACVAL5_FRACVAL5(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRACVAL5_FRACVAL5_SHIFT)) & PWM_FRACVAL5_FRACVAL5_MASK) +/*! @} */ /* The count of PWM_FRACVAL5 */ #define PWM_FRACVAL5_COUNT (4U) /*! @name VAL5 - Value Register 5 */ +/*! @{ */ #define PWM_VAL5_VAL5_MASK (0xFFFFU) #define PWM_VAL5_VAL5_SHIFT (0U) #define PWM_VAL5_VAL5(x) (((uint16_t)(((uint16_t)(x)) << PWM_VAL5_VAL5_SHIFT)) & PWM_VAL5_VAL5_MASK) +/*! @} */ /* The count of PWM_VAL5 */ #define PWM_VAL5_COUNT (4U) /*! @name FRCTRL - Fractional Control Register */ +/*! @{ */ #define PWM_FRCTRL_FRAC1_EN_MASK (0x2U) #define PWM_FRCTRL_FRAC1_EN_SHIFT (1U) +/*! FRAC1_EN - Fractional Cycle PWM Period Enable + * 0b0..Disable fractional cycle length for the PWM period. + * 0b1..Enable fractional cycle length for the PWM period. + */ #define PWM_FRCTRL_FRAC1_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRCTRL_FRAC1_EN_SHIFT)) & PWM_FRCTRL_FRAC1_EN_MASK) #define PWM_FRCTRL_FRAC23_EN_MASK (0x4U) #define PWM_FRCTRL_FRAC23_EN_SHIFT (2U) +/*! FRAC23_EN - Fractional Cycle Placement Enable for PWM_A + * 0b0..Disable fractional cycle placement for PWM_A. + * 0b1..Enable fractional cycle placement for PWM_A. + */ #define PWM_FRCTRL_FRAC23_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRCTRL_FRAC23_EN_SHIFT)) & PWM_FRCTRL_FRAC23_EN_MASK) #define PWM_FRCTRL_FRAC45_EN_MASK (0x10U) #define PWM_FRCTRL_FRAC45_EN_SHIFT (4U) +/*! FRAC45_EN - Fractional Cycle Placement Enable for PWM_B + * 0b0..Disable fractional cycle placement for PWM_B. + * 0b1..Enable fractional cycle placement for PWM_B. + */ #define PWM_FRCTRL_FRAC45_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRCTRL_FRAC45_EN_SHIFT)) & PWM_FRCTRL_FRAC45_EN_MASK) #define PWM_FRCTRL_FRAC_PU_MASK (0x100U) #define PWM_FRCTRL_FRAC_PU_SHIFT (8U) +/*! FRAC_PU - Fractional Delay Circuit Power Up + * 0b0..Turn off fractional delay logic. + * 0b1..Power up fractional delay logic. + */ #define PWM_FRCTRL_FRAC_PU(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRCTRL_FRAC_PU_SHIFT)) & PWM_FRCTRL_FRAC_PU_MASK) #define PWM_FRCTRL_TEST_MASK (0x8000U) #define PWM_FRCTRL_TEST_SHIFT (15U) #define PWM_FRCTRL_TEST(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRCTRL_TEST_SHIFT)) & PWM_FRCTRL_TEST_MASK) +/*! @} */ /* The count of PWM_FRCTRL */ #define PWM_FRCTRL_COUNT (4U) /*! @name OCTRL - Output Control Register */ +/*! @{ */ #define PWM_OCTRL_PWMXFS_MASK (0x3U) #define PWM_OCTRL_PWMXFS_SHIFT (0U) +/*! PWMXFS - PWM_X Fault State + * 0b00..Output is forced to logic 0 state prior to consideration of output polarity control. + * 0b01..Output is forced to logic 1 state prior to consideration of output polarity control. + * 0b10..Output is tristated. + * 0b11..Output is tristated. + */ #define PWM_OCTRL_PWMXFS(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMXFS_SHIFT)) & PWM_OCTRL_PWMXFS_MASK) #define PWM_OCTRL_PWMBFS_MASK (0xCU) #define PWM_OCTRL_PWMBFS_SHIFT (2U) +/*! PWMBFS - PWM_B Fault State + * 0b00..Output is forced to logic 0 state prior to consideration of output polarity control. + * 0b01..Output is forced to logic 1 state prior to consideration of output polarity control. + * 0b10..Output is tristated. + * 0b11..Output is tristated. + */ #define PWM_OCTRL_PWMBFS(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMBFS_SHIFT)) & PWM_OCTRL_PWMBFS_MASK) #define PWM_OCTRL_PWMAFS_MASK (0x30U) #define PWM_OCTRL_PWMAFS_SHIFT (4U) +/*! PWMAFS - PWM_A Fault State + * 0b00..Output is forced to logic 0 state prior to consideration of output polarity control. + * 0b01..Output is forced to logic 1 state prior to consideration of output polarity control. + * 0b10..Output is tristated. + * 0b11..Output is tristated. + */ #define PWM_OCTRL_PWMAFS(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMAFS_SHIFT)) & PWM_OCTRL_PWMAFS_MASK) #define PWM_OCTRL_POLX_MASK (0x100U) #define PWM_OCTRL_POLX_SHIFT (8U) +/*! POLX - PWM_X Output Polarity + * 0b0..PWM_X output not inverted. A high level on the PWM_X pin represents the "on" or "active" state. + * 0b1..PWM_X output inverted. A low level on the PWM_X pin represents the "on" or "active" state. + */ #define PWM_OCTRL_POLX(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_POLX_SHIFT)) & PWM_OCTRL_POLX_MASK) #define PWM_OCTRL_POLB_MASK (0x200U) #define PWM_OCTRL_POLB_SHIFT (9U) +/*! POLB - PWM_B Output Polarity + * 0b0..PWM_B output not inverted. A high level on the PWM_B pin represents the "on" or "active" state. + * 0b1..PWM_B output inverted. A low level on the PWM_B pin represents the "on" or "active" state. + */ #define PWM_OCTRL_POLB(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_POLB_SHIFT)) & PWM_OCTRL_POLB_MASK) #define PWM_OCTRL_POLA_MASK (0x400U) #define PWM_OCTRL_POLA_SHIFT (10U) +/*! POLA - PWM_A Output Polarity + * 0b0..PWM_A output not inverted. A high level on the PWM_A pin represents the "on" or "active" state. + * 0b1..PWM_A output inverted. A low level on the PWM_A pin represents the "on" or "active" state. + */ #define PWM_OCTRL_POLA(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_POLA_SHIFT)) & PWM_OCTRL_POLA_MASK) #define PWM_OCTRL_PWMX_IN_MASK (0x2000U) #define PWM_OCTRL_PWMX_IN_SHIFT (13U) @@ -17497,13 +28358,19 @@ typedef struct { #define PWM_OCTRL_PWMA_IN_MASK (0x8000U) #define PWM_OCTRL_PWMA_IN_SHIFT (15U) #define PWM_OCTRL_PWMA_IN(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMA_IN_SHIFT)) & PWM_OCTRL_PWMA_IN_MASK) +/*! @} */ /* The count of PWM_OCTRL */ #define PWM_OCTRL_COUNT (4U) /*! @name STS - Status Register */ +/*! @{ */ #define PWM_STS_CMPF_MASK (0x3FU) #define PWM_STS_CMPF_SHIFT (0U) +/*! CMPF - Compare Flags + * 0b000000..No compare event has occurred for a particular VALx value. + * 0b000001..A compare event has occurred for a particular VALx value. + */ #define PWM_STS_CMPF(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_CMPF_SHIFT)) & PWM_STS_CMPF_MASK) #define PWM_STS_CFX0_MASK (0x40U) #define PWM_STS_CFX0_SHIFT (6U) @@ -17525,50 +28392,102 @@ typedef struct { #define PWM_STS_CFA1(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFA1_SHIFT)) & PWM_STS_CFA1_MASK) #define PWM_STS_RF_MASK (0x1000U) #define PWM_STS_RF_SHIFT (12U) +/*! RF - Reload Flag + * 0b0..No new reload cycle since last STS[RF] clearing + * 0b1..New reload cycle since last STS[RF] clearing + */ #define PWM_STS_RF(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_RF_SHIFT)) & PWM_STS_RF_MASK) #define PWM_STS_REF_MASK (0x2000U) #define PWM_STS_REF_SHIFT (13U) +/*! REF - Reload Error Flag + * 0b0..No reload error occurred. + * 0b1..Reload signal occurred with non-coherent data and MCTRL[LDOK] = 0. + */ #define PWM_STS_REF(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_REF_SHIFT)) & PWM_STS_REF_MASK) #define PWM_STS_RUF_MASK (0x4000U) #define PWM_STS_RUF_SHIFT (14U) +/*! RUF - Registers Updated Flag + * 0b0..No register update has occurred since last reload. + * 0b1..At least one of the double buffered registers has been updated since the last reload. + */ #define PWM_STS_RUF(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_RUF_SHIFT)) & PWM_STS_RUF_MASK) +/*! @} */ /* The count of PWM_STS */ #define PWM_STS_COUNT (4U) /*! @name INTEN - Interrupt Enable Register */ +/*! @{ */ #define PWM_INTEN_CMPIE_MASK (0x3FU) #define PWM_INTEN_CMPIE_SHIFT (0U) +/*! CMPIE - Compare Interrupt Enables + * 0b000000..The corresponding STS[CMPF] bit will not cause an interrupt request. + * 0b000001..The corresponding STS[CMPF] bit will cause an interrupt request. + */ #define PWM_INTEN_CMPIE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CMPIE_SHIFT)) & PWM_INTEN_CMPIE_MASK) #define PWM_INTEN_CX0IE_MASK (0x40U) #define PWM_INTEN_CX0IE_SHIFT (6U) +/*! CX0IE - Capture X 0 Interrupt Enable + * 0b0..Interrupt request disabled for STS[CFX0]. + * 0b1..Interrupt request enabled for STS[CFX0]. + */ #define PWM_INTEN_CX0IE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CX0IE_SHIFT)) & PWM_INTEN_CX0IE_MASK) #define PWM_INTEN_CX1IE_MASK (0x80U) #define PWM_INTEN_CX1IE_SHIFT (7U) +/*! CX1IE - Capture X 1 Interrupt Enable + * 0b0..Interrupt request disabled for STS[CFX1]. + * 0b1..Interrupt request enabled for STS[CFX1]. + */ #define PWM_INTEN_CX1IE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CX1IE_SHIFT)) & PWM_INTEN_CX1IE_MASK) #define PWM_INTEN_CB0IE_MASK (0x100U) #define PWM_INTEN_CB0IE_SHIFT (8U) +/*! CB0IE - Capture B 0 Interrupt Enable + * 0b0..Interrupt request disabled for STS[CFB0]. + * 0b1..Interrupt request enabled for STS[CFB0]. + */ #define PWM_INTEN_CB0IE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CB0IE_SHIFT)) & PWM_INTEN_CB0IE_MASK) #define PWM_INTEN_CB1IE_MASK (0x200U) #define PWM_INTEN_CB1IE_SHIFT (9U) +/*! CB1IE - Capture B 1 Interrupt Enable + * 0b0..Interrupt request disabled for STS[CFB1]. + * 0b1..Interrupt request enabled for STS[CFB1]. + */ #define PWM_INTEN_CB1IE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CB1IE_SHIFT)) & PWM_INTEN_CB1IE_MASK) #define PWM_INTEN_CA0IE_MASK (0x400U) #define PWM_INTEN_CA0IE_SHIFT (10U) +/*! CA0IE - Capture A 0 Interrupt Enable + * 0b0..Interrupt request disabled for STS[CFA0]. + * 0b1..Interrupt request enabled for STS[CFA0]. + */ #define PWM_INTEN_CA0IE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CA0IE_SHIFT)) & PWM_INTEN_CA0IE_MASK) #define PWM_INTEN_CA1IE_MASK (0x800U) #define PWM_INTEN_CA1IE_SHIFT (11U) +/*! CA1IE - Capture A 1 Interrupt Enable + * 0b0..Interrupt request disabled for STS[CFA1]. + * 0b1..Interrupt request enabled for STS[CFA1]. + */ #define PWM_INTEN_CA1IE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CA1IE_SHIFT)) & PWM_INTEN_CA1IE_MASK) #define PWM_INTEN_RIE_MASK (0x1000U) #define PWM_INTEN_RIE_SHIFT (12U) +/*! RIE - Reload Interrupt Enable + * 0b0..STS[RF] CPU interrupt requests disabled + * 0b1..STS[RF] CPU interrupt requests enabled + */ #define PWM_INTEN_RIE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_RIE_SHIFT)) & PWM_INTEN_RIE_MASK) #define PWM_INTEN_REIE_MASK (0x2000U) #define PWM_INTEN_REIE_SHIFT (13U) +/*! REIE - Reload Error Interrupt Enable + * 0b0..STS[REF] CPU interrupt requests disabled + * 0b1..STS[REF] CPU interrupt requests enabled + */ #define PWM_INTEN_REIE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_REIE_SHIFT)) & PWM_INTEN_REIE_MASK) +/*! @} */ /* The count of PWM_INTEN */ #define PWM_INTEN_COUNT (4U) /*! @name DMAEN - DMA Enable Register */ +/*! @{ */ #define PWM_DMAEN_CX0DE_MASK (0x1U) #define PWM_DMAEN_CX0DE_SHIFT (0U) #define PWM_DMAEN_CX0DE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CX0DE_SHIFT)) & PWM_DMAEN_CX0DE_MASK) @@ -17589,35 +28508,69 @@ typedef struct { #define PWM_DMAEN_CA1DE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CA1DE_SHIFT)) & PWM_DMAEN_CA1DE_MASK) #define PWM_DMAEN_CAPTDE_MASK (0xC0U) #define PWM_DMAEN_CAPTDE_SHIFT (6U) +/*! CAPTDE - Capture DMA Enable Source Select + * 0b00..Read DMA requests disabled. + * 0b01..Exceeding a FIFO watermark sets the DMA read request. This requires at least one of DMAEN[CA1DE], DMAEN[CA0DE], DMAEN[CB1DE], DMAEN[CB0DE], DMAEN[CX1DE], or DMAEN[CX0DE] to also be set in order to determine to which watermark(s) the DMA request is sensitive. + * 0b10..A local sync (VAL1 matches counter) sets the read DMA request. + * 0b11..A local reload (STS[RF] being set) sets the read DMA request. + */ #define PWM_DMAEN_CAPTDE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CAPTDE_SHIFT)) & PWM_DMAEN_CAPTDE_MASK) #define PWM_DMAEN_FAND_MASK (0x100U) #define PWM_DMAEN_FAND_SHIFT (8U) +/*! FAND - FIFO Watermark AND Control + * 0b0..Selected FIFO watermarks are OR'ed together. + * 0b1..Selected FIFO watermarks are AND'ed together. + */ #define PWM_DMAEN_FAND(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_FAND_SHIFT)) & PWM_DMAEN_FAND_MASK) #define PWM_DMAEN_VALDE_MASK (0x200U) #define PWM_DMAEN_VALDE_SHIFT (9U) +/*! VALDE - Value Registers DMA Enable + * 0b0..DMA write requests disabled + * 0b1..DMA write requests for the VALx and FRACVALx registers enabled + */ #define PWM_DMAEN_VALDE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_VALDE_SHIFT)) & PWM_DMAEN_VALDE_MASK) +/*! @} */ /* The count of PWM_DMAEN */ #define PWM_DMAEN_COUNT (4U) /*! @name TCTRL - Output Trigger Control Register */ +/*! @{ */ #define PWM_TCTRL_OUT_TRIG_EN_MASK (0x3FU) #define PWM_TCTRL_OUT_TRIG_EN_SHIFT (0U) +/*! OUT_TRIG_EN - Output Trigger Enables + * 0b000000..PWM_OUT_TRIGx will not set when the counter value matches the VALx value. + * 0b000001..PWM_OUT_TRIGx will set when the counter value matches the VALx value. + */ #define PWM_TCTRL_OUT_TRIG_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_TCTRL_OUT_TRIG_EN_SHIFT)) & PWM_TCTRL_OUT_TRIG_EN_MASK) #define PWM_TCTRL_TRGFRQ_MASK (0x1000U) #define PWM_TCTRL_TRGFRQ_SHIFT (12U) +/*! TRGFRQ - Trigger frequency + * 0b0..Trigger outputs are generated during every PWM period even if the PWM is not reloaded every period due to CTRL[LDFQ] being non-zero. + * 0b1..Trigger outputs are generated only during the final PWM period prior to a reload opportunity when the PWM is not reloaded every period due to CTRL[LDFQ] being non-zero. + */ #define PWM_TCTRL_TRGFRQ(x) (((uint16_t)(((uint16_t)(x)) << PWM_TCTRL_TRGFRQ_SHIFT)) & PWM_TCTRL_TRGFRQ_MASK) #define PWM_TCTRL_PWBOT1_MASK (0x4000U) #define PWM_TCTRL_PWBOT1_SHIFT (14U) +/*! PWBOT1 - Output Trigger 1 Source Select + * 0b0..Route the PWM_OUT_TRIG1 signal to PWM_OUT_TRIG1 port. + * 0b1..Route the PWMB output to the PWM_OUT_TRIG1 port. + */ #define PWM_TCTRL_PWBOT1(x) (((uint16_t)(((uint16_t)(x)) << PWM_TCTRL_PWBOT1_SHIFT)) & PWM_TCTRL_PWBOT1_MASK) #define PWM_TCTRL_PWAOT0_MASK (0x8000U) #define PWM_TCTRL_PWAOT0_SHIFT (15U) +/*! PWAOT0 - Output Trigger 0 Source Select + * 0b0..Route the PWM_OUT_TRIG0 signal to PWM_OUT_TRIG0 port. + * 0b1..Route the PWMA output to the PWM_OUT_TRIG0 port. + */ #define PWM_TCTRL_PWAOT0(x) (((uint16_t)(((uint16_t)(x)) << PWM_TCTRL_PWAOT0_SHIFT)) & PWM_TCTRL_PWAOT0_MASK) +/*! @} */ /* The count of PWM_TCTRL */ #define PWM_TCTRL_COUNT (4U) /*! @name DISMAP - Fault Disable Mapping Register 0..Fault Disable Mapping Register 1 */ +/*! @{ */ #define PWM_DISMAP_DIS0A_MASK (0xFU) #define PWM_DISMAP_DIS0A_SHIFT (0U) #define PWM_DISMAP_DIS0A(x) (((uint16_t)(((uint16_t)(x)) << PWM_DISMAP_DIS0A_SHIFT)) & PWM_DISMAP_DIS0A_MASK) @@ -17630,12 +28583,13 @@ typedef struct { #define PWM_DISMAP_DIS1B_MASK (0xF0U) #define PWM_DISMAP_DIS1B_SHIFT (4U) #define PWM_DISMAP_DIS1B(x) (((uint16_t)(((uint16_t)(x)) << PWM_DISMAP_DIS1B_SHIFT)) & PWM_DISMAP_DIS1B_MASK) -#define PWM_DISMAP_DIS1X_MASK (0xF00U) -#define PWM_DISMAP_DIS1X_SHIFT (8U) -#define PWM_DISMAP_DIS1X(x) (((uint16_t)(((uint16_t)(x)) << PWM_DISMAP_DIS1X_SHIFT)) & PWM_DISMAP_DIS1X_MASK) #define PWM_DISMAP_DIS0X_MASK (0xF00U) #define PWM_DISMAP_DIS0X_SHIFT (8U) #define PWM_DISMAP_DIS0X(x) (((uint16_t)(((uint16_t)(x)) << PWM_DISMAP_DIS0X_SHIFT)) & PWM_DISMAP_DIS0X_MASK) +#define PWM_DISMAP_DIS1X_MASK (0xF00U) +#define PWM_DISMAP_DIS1X_SHIFT (8U) +#define PWM_DISMAP_DIS1X(x) (((uint16_t)(((uint16_t)(x)) << PWM_DISMAP_DIS1X_SHIFT)) & PWM_DISMAP_DIS1X_MASK) +/*! @} */ /* The count of PWM_DISMAP */ #define PWM_DISMAP_COUNT (4U) @@ -17644,39 +28598,72 @@ typedef struct { #define PWM_DISMAP_COUNT2 (2U) /*! @name DTCNT0 - Deadtime Count Register 0 */ +/*! @{ */ #define PWM_DTCNT0_DTCNT0_MASK (0xFFFFU) #define PWM_DTCNT0_DTCNT0_SHIFT (0U) #define PWM_DTCNT0_DTCNT0(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTCNT0_DTCNT0_SHIFT)) & PWM_DTCNT0_DTCNT0_MASK) +/*! @} */ /* The count of PWM_DTCNT0 */ #define PWM_DTCNT0_COUNT (4U) /*! @name DTCNT1 - Deadtime Count Register 1 */ +/*! @{ */ #define PWM_DTCNT1_DTCNT1_MASK (0xFFFFU) #define PWM_DTCNT1_DTCNT1_SHIFT (0U) #define PWM_DTCNT1_DTCNT1(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTCNT1_DTCNT1_SHIFT)) & PWM_DTCNT1_DTCNT1_MASK) +/*! @} */ /* The count of PWM_DTCNT1 */ #define PWM_DTCNT1_COUNT (4U) /*! @name CAPTCTRLA - Capture Control A Register */ +/*! @{ */ #define PWM_CAPTCTRLA_ARMA_MASK (0x1U) #define PWM_CAPTCTRLA_ARMA_SHIFT (0U) +/*! ARMA - Arm A + * 0b0..Input capture operation is disabled. + * 0b1..Input capture operation as specified by CAPTCTRLA[EDGAx] is enabled. + */ #define PWM_CAPTCTRLA_ARMA(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_ARMA_SHIFT)) & PWM_CAPTCTRLA_ARMA_MASK) #define PWM_CAPTCTRLA_ONESHOTA_MASK (0x2U) #define PWM_CAPTCTRLA_ONESHOTA_SHIFT (1U) +/*! ONESHOTA - One Shot Mode A + * 0b0..Free running mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after CAPTCTRLA[ARMA] is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and capture circuit 0 is re-armed. The process continues indefinitely.If only one of the capture circuits is enabled, then captures continue indefinitely on the enabled capture circuit. + * 0b1..One shot mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after CAPTCTRLA[ARMA] is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and CAPTCTRLA[ARMA] is cleared. No further captures will be performed until CAPTCTRLA[ARMA] is set again.If only one of the capture circuits is enabled, then a single capture will occur on the enabled capture circuit and CAPTCTRLA[ARMA] is then cleared. + */ #define PWM_CAPTCTRLA_ONESHOTA(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_ONESHOTA_SHIFT)) & PWM_CAPTCTRLA_ONESHOTA_MASK) #define PWM_CAPTCTRLA_EDGA0_MASK (0xCU) #define PWM_CAPTCTRLA_EDGA0_SHIFT (2U) +/*! EDGA0 - Edge A 0 + * 0b00..Disabled + * 0b01..Capture falling edges + * 0b10..Capture rising edges + * 0b11..Capture any edge + */ #define PWM_CAPTCTRLA_EDGA0(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_EDGA0_SHIFT)) & PWM_CAPTCTRLA_EDGA0_MASK) #define PWM_CAPTCTRLA_EDGA1_MASK (0x30U) #define PWM_CAPTCTRLA_EDGA1_SHIFT (4U) +/*! EDGA1 - Edge A 1 + * 0b00..Disabled + * 0b01..Capture falling edges + * 0b10..Capture rising edges + * 0b11..Capture any edge + */ #define PWM_CAPTCTRLA_EDGA1(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_EDGA1_SHIFT)) & PWM_CAPTCTRLA_EDGA1_MASK) #define PWM_CAPTCTRLA_INP_SELA_MASK (0x40U) #define PWM_CAPTCTRLA_INP_SELA_SHIFT (6U) +/*! INP_SELA - Input Select A + * 0b0..Raw PWM_A input signal selected as source. + * 0b1..Output of edge counter/compare selected as source. Note that when this bitfield is set to 1, the internal edge counter is enabled and the rising and/or falling edges specified by the CAPTCTRLA[EDGA0] and CAPTCTRLA[EDGA1] fields are ignored. The software must still place a value other than 00 in either or both of the CAPTCTLRA[EDGA0] and/or CAPTCTRLA[EDGA1] fields in order to enable one or both of the capture registers. + */ #define PWM_CAPTCTRLA_INP_SELA(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_INP_SELA_SHIFT)) & PWM_CAPTCTRLA_INP_SELA_MASK) #define PWM_CAPTCTRLA_EDGCNTA_EN_MASK (0x80U) #define PWM_CAPTCTRLA_EDGCNTA_EN_SHIFT (7U) +/*! EDGCNTA_EN - Edge Counter A Enable + * 0b0..Edge counter disabled and held in reset + * 0b1..Edge counter enabled + */ #define PWM_CAPTCTRLA_EDGCNTA_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_EDGCNTA_EN_SHIFT)) & PWM_CAPTCTRLA_EDGCNTA_EN_MASK) #define PWM_CAPTCTRLA_CFAWM_MASK (0x300U) #define PWM_CAPTCTRLA_CFAWM_SHIFT (8U) @@ -17687,39 +28674,71 @@ typedef struct { #define PWM_CAPTCTRLA_CA1CNT_MASK (0xE000U) #define PWM_CAPTCTRLA_CA1CNT_SHIFT (13U) #define PWM_CAPTCTRLA_CA1CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_CA1CNT_SHIFT)) & PWM_CAPTCTRLA_CA1CNT_MASK) +/*! @} */ /* The count of PWM_CAPTCTRLA */ #define PWM_CAPTCTRLA_COUNT (4U) /*! @name CAPTCOMPA - Capture Compare A Register */ +/*! @{ */ #define PWM_CAPTCOMPA_EDGCMPA_MASK (0xFFU) #define PWM_CAPTCOMPA_EDGCMPA_SHIFT (0U) #define PWM_CAPTCOMPA_EDGCMPA(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPA_EDGCMPA_SHIFT)) & PWM_CAPTCOMPA_EDGCMPA_MASK) #define PWM_CAPTCOMPA_EDGCNTA_MASK (0xFF00U) #define PWM_CAPTCOMPA_EDGCNTA_SHIFT (8U) #define PWM_CAPTCOMPA_EDGCNTA(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPA_EDGCNTA_SHIFT)) & PWM_CAPTCOMPA_EDGCNTA_MASK) +/*! @} */ /* The count of PWM_CAPTCOMPA */ #define PWM_CAPTCOMPA_COUNT (4U) /*! @name CAPTCTRLB - Capture Control B Register */ +/*! @{ */ #define PWM_CAPTCTRLB_ARMB_MASK (0x1U) #define PWM_CAPTCTRLB_ARMB_SHIFT (0U) +/*! ARMB - Arm B + * 0b0..Input capture operation is disabled. + * 0b1..Input capture operation as specified by CAPTCTRLB[EDGBx] is enabled. + */ #define PWM_CAPTCTRLB_ARMB(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_ARMB_SHIFT)) & PWM_CAPTCTRLB_ARMB_MASK) #define PWM_CAPTCTRLB_ONESHOTB_MASK (0x2U) #define PWM_CAPTCTRLB_ONESHOTB_SHIFT (1U) +/*! ONESHOTB - One Shot Mode B + * 0b0..Free running mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after CAPTCTRLB[ARMB] is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and capture circuit 0 is re-armed. The process continues indefinitely.If only one of the capture circuits is enabled, then captures continue indefinitely on the enabled capture circuit. + * 0b1..One shot mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after CAPTCTRLB[ARMB] is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and CAPTCTRLB[ARMB] is cleared. No further captures will be performed until CAPTCTRLB[ARMB] is set again.If only one of the capture circuits is enabled, then a single capture will occur on the enabled capture circuit and CAPTCTRLB[ARMB] is then cleared. + */ #define PWM_CAPTCTRLB_ONESHOTB(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_ONESHOTB_SHIFT)) & PWM_CAPTCTRLB_ONESHOTB_MASK) #define PWM_CAPTCTRLB_EDGB0_MASK (0xCU) #define PWM_CAPTCTRLB_EDGB0_SHIFT (2U) +/*! EDGB0 - Edge B 0 + * 0b00..Disabled + * 0b01..Capture falling edges + * 0b10..Capture rising edges + * 0b11..Capture any edge + */ #define PWM_CAPTCTRLB_EDGB0(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_EDGB0_SHIFT)) & PWM_CAPTCTRLB_EDGB0_MASK) #define PWM_CAPTCTRLB_EDGB1_MASK (0x30U) #define PWM_CAPTCTRLB_EDGB1_SHIFT (4U) +/*! EDGB1 - Edge B 1 + * 0b00..Disabled + * 0b01..Capture falling edges + * 0b10..Capture rising edges + * 0b11..Capture any edge + */ #define PWM_CAPTCTRLB_EDGB1(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_EDGB1_SHIFT)) & PWM_CAPTCTRLB_EDGB1_MASK) #define PWM_CAPTCTRLB_INP_SELB_MASK (0x40U) #define PWM_CAPTCTRLB_INP_SELB_SHIFT (6U) +/*! INP_SELB - Input Select B + * 0b0..Raw PWM_B input signal selected as source. + * 0b1..Output of edge counter/compare selected as source. Note that when this bitfield is set to 1, the internal edge counter is enabled and the rising and/or falling edges specified by the CAPTCTRLB[EDGB0] and CAPTCTRLB[EDGB1] fields are ignored. The software must still place a value other than 00 in either or both of the CAPTCTLRB[EDGB0] and/or CAPTCTRLB[EDGB1] fields in order to enable one or both of the capture registers. + */ #define PWM_CAPTCTRLB_INP_SELB(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_INP_SELB_SHIFT)) & PWM_CAPTCTRLB_INP_SELB_MASK) #define PWM_CAPTCTRLB_EDGCNTB_EN_MASK (0x80U) #define PWM_CAPTCTRLB_EDGCNTB_EN_SHIFT (7U) +/*! EDGCNTB_EN - Edge Counter B Enable + * 0b0..Edge counter disabled and held in reset + * 0b1..Edge counter enabled + */ #define PWM_CAPTCTRLB_EDGCNTB_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_EDGCNTB_EN_SHIFT)) & PWM_CAPTCTRLB_EDGCNTB_EN_MASK) #define PWM_CAPTCTRLB_CFBWM_MASK (0x300U) #define PWM_CAPTCTRLB_CFBWM_SHIFT (8U) @@ -17730,39 +28749,71 @@ typedef struct { #define PWM_CAPTCTRLB_CB1CNT_MASK (0xE000U) #define PWM_CAPTCTRLB_CB1CNT_SHIFT (13U) #define PWM_CAPTCTRLB_CB1CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_CB1CNT_SHIFT)) & PWM_CAPTCTRLB_CB1CNT_MASK) +/*! @} */ /* The count of PWM_CAPTCTRLB */ #define PWM_CAPTCTRLB_COUNT (4U) /*! @name CAPTCOMPB - Capture Compare B Register */ +/*! @{ */ #define PWM_CAPTCOMPB_EDGCMPB_MASK (0xFFU) #define PWM_CAPTCOMPB_EDGCMPB_SHIFT (0U) #define PWM_CAPTCOMPB_EDGCMPB(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPB_EDGCMPB_SHIFT)) & PWM_CAPTCOMPB_EDGCMPB_MASK) #define PWM_CAPTCOMPB_EDGCNTB_MASK (0xFF00U) #define PWM_CAPTCOMPB_EDGCNTB_SHIFT (8U) #define PWM_CAPTCOMPB_EDGCNTB(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPB_EDGCNTB_SHIFT)) & PWM_CAPTCOMPB_EDGCNTB_MASK) +/*! @} */ /* The count of PWM_CAPTCOMPB */ #define PWM_CAPTCOMPB_COUNT (4U) /*! @name CAPTCTRLX - Capture Control X Register */ +/*! @{ */ #define PWM_CAPTCTRLX_ARMX_MASK (0x1U) #define PWM_CAPTCTRLX_ARMX_SHIFT (0U) +/*! ARMX - Arm X + * 0b0..Input capture operation is disabled. + * 0b1..Input capture operation as specified by CAPTCTRLX[EDGXx] is enabled. + */ #define PWM_CAPTCTRLX_ARMX(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_ARMX_SHIFT)) & PWM_CAPTCTRLX_ARMX_MASK) #define PWM_CAPTCTRLX_ONESHOTX_MASK (0x2U) #define PWM_CAPTCTRLX_ONESHOTX_SHIFT (1U) +/*! ONESHOTX - One Shot Mode Aux + * 0b0..Free running mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after the ARMX bit is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and capture circuit 0 is re-armed. The process continues indefinitely.If only one of the capture circuits is enabled, then captures continue indefinitely on the enabled capture circuit. + * 0b1..One shot mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after the ARMX bit is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and the ARMX bit is cleared. No further captures will be performed until the ARMX bit is set again.If only one of the capture circuits is enabled, then a single capture will occur on the enabled capture circuit and the ARMX bit is then cleared. + */ #define PWM_CAPTCTRLX_ONESHOTX(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_ONESHOTX_SHIFT)) & PWM_CAPTCTRLX_ONESHOTX_MASK) #define PWM_CAPTCTRLX_EDGX0_MASK (0xCU) #define PWM_CAPTCTRLX_EDGX0_SHIFT (2U) +/*! EDGX0 - Edge X 0 + * 0b00..Disabled + * 0b01..Capture falling edges + * 0b10..Capture rising edges + * 0b11..Capture any edge + */ #define PWM_CAPTCTRLX_EDGX0(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_EDGX0_SHIFT)) & PWM_CAPTCTRLX_EDGX0_MASK) #define PWM_CAPTCTRLX_EDGX1_MASK (0x30U) #define PWM_CAPTCTRLX_EDGX1_SHIFT (4U) +/*! EDGX1 - Edge X 1 + * 0b00..Disabled + * 0b01..Capture falling edges + * 0b10..Capture rising edges + * 0b11..Capture any edge + */ #define PWM_CAPTCTRLX_EDGX1(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_EDGX1_SHIFT)) & PWM_CAPTCTRLX_EDGX1_MASK) #define PWM_CAPTCTRLX_INP_SELX_MASK (0x40U) #define PWM_CAPTCTRLX_INP_SELX_SHIFT (6U) +/*! INP_SELX - Input Select X + * 0b0..Raw PWM_X input signal selected as source. + * 0b1..Output of edge counter/compare selected as source. Note that when this bitfield is set to 1, the internal edge counter is enabled and the rising and/or falling edges specified by the CAPTCTRLX[EDGX0] and CAPTCTRLX[EDGX1] fields are ignored. The software must still place a value other than 00 in either or both of the CAPTCTLRX[EDGX0] and/or CAPTCTRLX[EDGX1] fields in order to enable one or both of the capture registers. + */ #define PWM_CAPTCTRLX_INP_SELX(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_INP_SELX_SHIFT)) & PWM_CAPTCTRLX_INP_SELX_MASK) #define PWM_CAPTCTRLX_EDGCNTX_EN_MASK (0x80U) #define PWM_CAPTCTRLX_EDGCNTX_EN_SHIFT (7U) +/*! EDGCNTX_EN - Edge Counter X Enable + * 0b0..Edge counter disabled and held in reset + * 0b1..Edge counter enabled + */ #define PWM_CAPTCTRLX_EDGCNTX_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_EDGCNTX_EN_SHIFT)) & PWM_CAPTCTRLX_EDGCNTX_EN_MASK) #define PWM_CAPTCTRLX_CFXWM_MASK (0x300U) #define PWM_CAPTCTRLX_CFXWM_SHIFT (8U) @@ -17773,242 +28824,440 @@ typedef struct { #define PWM_CAPTCTRLX_CX1CNT_MASK (0xE000U) #define PWM_CAPTCTRLX_CX1CNT_SHIFT (13U) #define PWM_CAPTCTRLX_CX1CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_CX1CNT_SHIFT)) & PWM_CAPTCTRLX_CX1CNT_MASK) +/*! @} */ /* The count of PWM_CAPTCTRLX */ #define PWM_CAPTCTRLX_COUNT (4U) /*! @name CAPTCOMPX - Capture Compare X Register */ +/*! @{ */ #define PWM_CAPTCOMPX_EDGCMPX_MASK (0xFFU) #define PWM_CAPTCOMPX_EDGCMPX_SHIFT (0U) #define PWM_CAPTCOMPX_EDGCMPX(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPX_EDGCMPX_SHIFT)) & PWM_CAPTCOMPX_EDGCMPX_MASK) #define PWM_CAPTCOMPX_EDGCNTX_MASK (0xFF00U) #define PWM_CAPTCOMPX_EDGCNTX_SHIFT (8U) #define PWM_CAPTCOMPX_EDGCNTX(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPX_EDGCNTX_SHIFT)) & PWM_CAPTCOMPX_EDGCNTX_MASK) +/*! @} */ /* The count of PWM_CAPTCOMPX */ #define PWM_CAPTCOMPX_COUNT (4U) /*! @name CVAL0 - Capture Value 0 Register */ +/*! @{ */ #define PWM_CVAL0_CAPTVAL0_MASK (0xFFFFU) #define PWM_CVAL0_CAPTVAL0_SHIFT (0U) #define PWM_CVAL0_CAPTVAL0(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL0_CAPTVAL0_SHIFT)) & PWM_CVAL0_CAPTVAL0_MASK) +/*! @} */ /* The count of PWM_CVAL0 */ #define PWM_CVAL0_COUNT (4U) /*! @name CVAL0CYC - Capture Value 0 Cycle Register */ +/*! @{ */ #define PWM_CVAL0CYC_CVAL0CYC_MASK (0xFU) #define PWM_CVAL0CYC_CVAL0CYC_SHIFT (0U) #define PWM_CVAL0CYC_CVAL0CYC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL0CYC_CVAL0CYC_SHIFT)) & PWM_CVAL0CYC_CVAL0CYC_MASK) +/*! @} */ /* The count of PWM_CVAL0CYC */ #define PWM_CVAL0CYC_COUNT (4U) /*! @name CVAL1 - Capture Value 1 Register */ +/*! @{ */ #define PWM_CVAL1_CAPTVAL1_MASK (0xFFFFU) #define PWM_CVAL1_CAPTVAL1_SHIFT (0U) #define PWM_CVAL1_CAPTVAL1(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL1_CAPTVAL1_SHIFT)) & PWM_CVAL1_CAPTVAL1_MASK) +/*! @} */ /* The count of PWM_CVAL1 */ #define PWM_CVAL1_COUNT (4U) /*! @name CVAL1CYC - Capture Value 1 Cycle Register */ +/*! @{ */ #define PWM_CVAL1CYC_CVAL1CYC_MASK (0xFU) #define PWM_CVAL1CYC_CVAL1CYC_SHIFT (0U) #define PWM_CVAL1CYC_CVAL1CYC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL1CYC_CVAL1CYC_SHIFT)) & PWM_CVAL1CYC_CVAL1CYC_MASK) +/*! @} */ /* The count of PWM_CVAL1CYC */ #define PWM_CVAL1CYC_COUNT (4U) /*! @name CVAL2 - Capture Value 2 Register */ +/*! @{ */ #define PWM_CVAL2_CAPTVAL2_MASK (0xFFFFU) #define PWM_CVAL2_CAPTVAL2_SHIFT (0U) #define PWM_CVAL2_CAPTVAL2(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL2_CAPTVAL2_SHIFT)) & PWM_CVAL2_CAPTVAL2_MASK) +/*! @} */ /* The count of PWM_CVAL2 */ #define PWM_CVAL2_COUNT (4U) /*! @name CVAL2CYC - Capture Value 2 Cycle Register */ +/*! @{ */ #define PWM_CVAL2CYC_CVAL2CYC_MASK (0xFU) #define PWM_CVAL2CYC_CVAL2CYC_SHIFT (0U) #define PWM_CVAL2CYC_CVAL2CYC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL2CYC_CVAL2CYC_SHIFT)) & PWM_CVAL2CYC_CVAL2CYC_MASK) +/*! @} */ /* The count of PWM_CVAL2CYC */ #define PWM_CVAL2CYC_COUNT (4U) /*! @name CVAL3 - Capture Value 3 Register */ +/*! @{ */ #define PWM_CVAL3_CAPTVAL3_MASK (0xFFFFU) #define PWM_CVAL3_CAPTVAL3_SHIFT (0U) #define PWM_CVAL3_CAPTVAL3(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL3_CAPTVAL3_SHIFT)) & PWM_CVAL3_CAPTVAL3_MASK) +/*! @} */ /* The count of PWM_CVAL3 */ #define PWM_CVAL3_COUNT (4U) /*! @name CVAL3CYC - Capture Value 3 Cycle Register */ +/*! @{ */ #define PWM_CVAL3CYC_CVAL3CYC_MASK (0xFU) #define PWM_CVAL3CYC_CVAL3CYC_SHIFT (0U) #define PWM_CVAL3CYC_CVAL3CYC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL3CYC_CVAL3CYC_SHIFT)) & PWM_CVAL3CYC_CVAL3CYC_MASK) +/*! @} */ /* The count of PWM_CVAL3CYC */ #define PWM_CVAL3CYC_COUNT (4U) /*! @name CVAL4 - Capture Value 4 Register */ +/*! @{ */ #define PWM_CVAL4_CAPTVAL4_MASK (0xFFFFU) #define PWM_CVAL4_CAPTVAL4_SHIFT (0U) #define PWM_CVAL4_CAPTVAL4(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL4_CAPTVAL4_SHIFT)) & PWM_CVAL4_CAPTVAL4_MASK) +/*! @} */ /* The count of PWM_CVAL4 */ #define PWM_CVAL4_COUNT (4U) /*! @name CVAL4CYC - Capture Value 4 Cycle Register */ +/*! @{ */ #define PWM_CVAL4CYC_CVAL4CYC_MASK (0xFU) #define PWM_CVAL4CYC_CVAL4CYC_SHIFT (0U) #define PWM_CVAL4CYC_CVAL4CYC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL4CYC_CVAL4CYC_SHIFT)) & PWM_CVAL4CYC_CVAL4CYC_MASK) +/*! @} */ /* The count of PWM_CVAL4CYC */ #define PWM_CVAL4CYC_COUNT (4U) /*! @name CVAL5 - Capture Value 5 Register */ +/*! @{ */ #define PWM_CVAL5_CAPTVAL5_MASK (0xFFFFU) #define PWM_CVAL5_CAPTVAL5_SHIFT (0U) #define PWM_CVAL5_CAPTVAL5(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL5_CAPTVAL5_SHIFT)) & PWM_CVAL5_CAPTVAL5_MASK) +/*! @} */ /* The count of PWM_CVAL5 */ #define PWM_CVAL5_COUNT (4U) /*! @name CVAL5CYC - Capture Value 5 Cycle Register */ +/*! @{ */ #define PWM_CVAL5CYC_CVAL5CYC_MASK (0xFU) #define PWM_CVAL5CYC_CVAL5CYC_SHIFT (0U) #define PWM_CVAL5CYC_CVAL5CYC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL5CYC_CVAL5CYC_SHIFT)) & PWM_CVAL5CYC_CVAL5CYC_MASK) +/*! @} */ /* The count of PWM_CVAL5CYC */ #define PWM_CVAL5CYC_COUNT (4U) /*! @name OUTEN - Output Enable Register */ +/*! @{ */ #define PWM_OUTEN_PWMX_EN_MASK (0xFU) #define PWM_OUTEN_PWMX_EN_SHIFT (0U) +/*! PWMX_EN - PWM_X Output Enables + * 0b0000..PWM_X output disabled. + * 0b0001..PWM_X output enabled. + */ #define PWM_OUTEN_PWMX_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_OUTEN_PWMX_EN_SHIFT)) & PWM_OUTEN_PWMX_EN_MASK) #define PWM_OUTEN_PWMB_EN_MASK (0xF0U) #define PWM_OUTEN_PWMB_EN_SHIFT (4U) +/*! PWMB_EN - PWM_B Output Enables + * 0b0000..PWM_B output disabled. + * 0b0001..PWM_B output enabled. + */ #define PWM_OUTEN_PWMB_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_OUTEN_PWMB_EN_SHIFT)) & PWM_OUTEN_PWMB_EN_MASK) #define PWM_OUTEN_PWMA_EN_MASK (0xF00U) #define PWM_OUTEN_PWMA_EN_SHIFT (8U) +/*! PWMA_EN - PWM_A Output Enables + * 0b0000..PWM_A output disabled. + * 0b0001..PWM_A output enabled. + */ #define PWM_OUTEN_PWMA_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_OUTEN_PWMA_EN_SHIFT)) & PWM_OUTEN_PWMA_EN_MASK) +/*! @} */ /*! @name MASK - Mask Register */ +/*! @{ */ #define PWM_MASK_MASKX_MASK (0xFU) #define PWM_MASK_MASKX_SHIFT (0U) +/*! MASKX - PWM_X Masks + * 0b0000..PWM_X output normal. + * 0b0001..PWM_X output masked. + */ #define PWM_MASK_MASKX(x) (((uint16_t)(((uint16_t)(x)) << PWM_MASK_MASKX_SHIFT)) & PWM_MASK_MASKX_MASK) #define PWM_MASK_MASKB_MASK (0xF0U) #define PWM_MASK_MASKB_SHIFT (4U) +/*! MASKB - PWM_B Masks + * 0b0000..PWM_B output normal. + * 0b0001..PWM_B output masked. + */ #define PWM_MASK_MASKB(x) (((uint16_t)(((uint16_t)(x)) << PWM_MASK_MASKB_SHIFT)) & PWM_MASK_MASKB_MASK) #define PWM_MASK_MASKA_MASK (0xF00U) #define PWM_MASK_MASKA_SHIFT (8U) +/*! MASKA - PWM_A Masks + * 0b0000..PWM_A output normal. + * 0b0001..PWM_A output masked. + */ #define PWM_MASK_MASKA(x) (((uint16_t)(((uint16_t)(x)) << PWM_MASK_MASKA_SHIFT)) & PWM_MASK_MASKA_MASK) #define PWM_MASK_UPDATE_MASK_MASK (0xF000U) #define PWM_MASK_UPDATE_MASK_SHIFT (12U) +/*! UPDATE_MASK - Update Mask Bits Immediately + * 0b0000..Normal operation. MASK* bits within the corresponding submodule are not updated until a FORCE_OUT event occurs within the submodule. + * 0b0001..Immediate operation. MASK* bits within the corresponding submodule are updated on the following clock edge after setting this bit. + */ #define PWM_MASK_UPDATE_MASK(x) (((uint16_t)(((uint16_t)(x)) << PWM_MASK_UPDATE_MASK_SHIFT)) & PWM_MASK_UPDATE_MASK_MASK) +/*! @} */ /*! @name SWCOUT - Software Controlled Output Register */ +/*! @{ */ #define PWM_SWCOUT_SM0OUT45_MASK (0x1U) #define PWM_SWCOUT_SM0OUT45_SHIFT (0U) +/*! SM0OUT45 - Submodule 0 Software Controlled Output 45 + * 0b0..A logic 0 is supplied to the deadtime generator of submodule 0 instead of PWM45. + * 0b1..A logic 1 is supplied to the deadtime generator of submodule 0 instead of PWM45. + */ #define PWM_SWCOUT_SM0OUT45(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM0OUT45_SHIFT)) & PWM_SWCOUT_SM0OUT45_MASK) #define PWM_SWCOUT_SM0OUT23_MASK (0x2U) #define PWM_SWCOUT_SM0OUT23_SHIFT (1U) +/*! SM0OUT23 - Submodule 0 Software Controlled Output 23 + * 0b0..A logic 0 is supplied to the deadtime generator of submodule 0 instead of PWM23. + * 0b1..A logic 1 is supplied to the deadtime generator of submodule 0 instead of PWM23. + */ #define PWM_SWCOUT_SM0OUT23(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM0OUT23_SHIFT)) & PWM_SWCOUT_SM0OUT23_MASK) #define PWM_SWCOUT_SM1OUT45_MASK (0x4U) #define PWM_SWCOUT_SM1OUT45_SHIFT (2U) +/*! SM1OUT45 - Submodule 1 Software Controlled Output 45 + * 0b0..A logic 0 is supplied to the deadtime generator of submodule 1 instead of PWM45. + * 0b1..A logic 1 is supplied to the deadtime generator of submodule 1 instead of PWM45. + */ #define PWM_SWCOUT_SM1OUT45(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM1OUT45_SHIFT)) & PWM_SWCOUT_SM1OUT45_MASK) #define PWM_SWCOUT_SM1OUT23_MASK (0x8U) #define PWM_SWCOUT_SM1OUT23_SHIFT (3U) +/*! SM1OUT23 - Submodule 1 Software Controlled Output 23 + * 0b0..A logic 0 is supplied to the deadtime generator of submodule 1 instead of PWM23. + * 0b1..A logic 1 is supplied to the deadtime generator of submodule 1 instead of PWM23. + */ #define PWM_SWCOUT_SM1OUT23(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM1OUT23_SHIFT)) & PWM_SWCOUT_SM1OUT23_MASK) #define PWM_SWCOUT_SM2OUT45_MASK (0x10U) #define PWM_SWCOUT_SM2OUT45_SHIFT (4U) +/*! SM2OUT45 - Submodule 2 Software Controlled Output 45 + * 0b0..A logic 0 is supplied to the deadtime generator of submodule 2 instead of PWM45. + * 0b1..A logic 1 is supplied to the deadtime generator of submodule 2 instead of PWM45. + */ #define PWM_SWCOUT_SM2OUT45(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM2OUT45_SHIFT)) & PWM_SWCOUT_SM2OUT45_MASK) #define PWM_SWCOUT_SM2OUT23_MASK (0x20U) #define PWM_SWCOUT_SM2OUT23_SHIFT (5U) +/*! SM2OUT23 - Submodule 2 Software Controlled Output 23 + * 0b0..A logic 0 is supplied to the deadtime generator of submodule 2 instead of PWM23. + * 0b1..A logic 1 is supplied to the deadtime generator of submodule 2 instead of PWM23. + */ #define PWM_SWCOUT_SM2OUT23(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM2OUT23_SHIFT)) & PWM_SWCOUT_SM2OUT23_MASK) #define PWM_SWCOUT_SM3OUT45_MASK (0x40U) #define PWM_SWCOUT_SM3OUT45_SHIFT (6U) +/*! SM3OUT45 - Submodule 3 Software Controlled Output 45 + * 0b0..A logic 0 is supplied to the deadtime generator of submodule 3 instead of PWM45. + * 0b1..A logic 1 is supplied to the deadtime generator of submodule 3 instead of PWM45. + */ #define PWM_SWCOUT_SM3OUT45(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM3OUT45_SHIFT)) & PWM_SWCOUT_SM3OUT45_MASK) #define PWM_SWCOUT_SM3OUT23_MASK (0x80U) #define PWM_SWCOUT_SM3OUT23_SHIFT (7U) +/*! SM3OUT23 - Submodule 3 Software Controlled Output 23 + * 0b0..A logic 0 is supplied to the deadtime generator of submodule 3 instead of PWM23. + * 0b1..A logic 1 is supplied to the deadtime generator of submodule 3 instead of PWM23. + */ #define PWM_SWCOUT_SM3OUT23(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM3OUT23_SHIFT)) & PWM_SWCOUT_SM3OUT23_MASK) +/*! @} */ /*! @name DTSRCSEL - PWM Source Select Register */ +/*! @{ */ #define PWM_DTSRCSEL_SM0SEL45_MASK (0x3U) #define PWM_DTSRCSEL_SM0SEL45_SHIFT (0U) +/*! SM0SEL45 - Submodule 0 PWM45 Control Select + * 0b00..Generated SM0PWM45 signal is used by the deadtime logic. + * 0b01..Inverted generated SM0PWM45 signal is used by the deadtime logic. + * 0b10..SWCOUT[SM0OUT45] is used by the deadtime logic. + * 0b11..PWM0_EXTB signal is used by the deadtime logic. + */ #define PWM_DTSRCSEL_SM0SEL45(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM0SEL45_SHIFT)) & PWM_DTSRCSEL_SM0SEL45_MASK) #define PWM_DTSRCSEL_SM0SEL23_MASK (0xCU) #define PWM_DTSRCSEL_SM0SEL23_SHIFT (2U) +/*! SM0SEL23 - Submodule 0 PWM23 Control Select + * 0b00..Generated SM0PWM23 signal is used by the deadtime logic. + * 0b01..Inverted generated SM0PWM23 signal is used by the deadtime logic. + * 0b10..SWCOUT[SM0OUT23] is used by the deadtime logic. + * 0b11..PWM0_EXTA signal is used by the deadtime logic. + */ #define PWM_DTSRCSEL_SM0SEL23(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM0SEL23_SHIFT)) & PWM_DTSRCSEL_SM0SEL23_MASK) #define PWM_DTSRCSEL_SM1SEL45_MASK (0x30U) #define PWM_DTSRCSEL_SM1SEL45_SHIFT (4U) +/*! SM1SEL45 - Submodule 1 PWM45 Control Select + * 0b00..Generated SM1PWM45 signal is used by the deadtime logic. + * 0b01..Inverted generated SM1PWM45 signal is used by the deadtime logic. + * 0b10..SWCOUT[SM1OUT45] is used by the deadtime logic. + * 0b11..PWM1_EXTB signal is used by the deadtime logic. + */ #define PWM_DTSRCSEL_SM1SEL45(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM1SEL45_SHIFT)) & PWM_DTSRCSEL_SM1SEL45_MASK) #define PWM_DTSRCSEL_SM1SEL23_MASK (0xC0U) #define PWM_DTSRCSEL_SM1SEL23_SHIFT (6U) +/*! SM1SEL23 - Submodule 1 PWM23 Control Select + * 0b00..Generated SM1PWM23 signal is used by the deadtime logic. + * 0b01..Inverted generated SM1PWM23 signal is used by the deadtime logic. + * 0b10..SWCOUT[SM1OUT23] is used by the deadtime logic. + * 0b11..PWM1_EXTA signal is used by the deadtime logic. + */ #define PWM_DTSRCSEL_SM1SEL23(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM1SEL23_SHIFT)) & PWM_DTSRCSEL_SM1SEL23_MASK) #define PWM_DTSRCSEL_SM2SEL45_MASK (0x300U) #define PWM_DTSRCSEL_SM2SEL45_SHIFT (8U) +/*! SM2SEL45 - Submodule 2 PWM45 Control Select + * 0b00..Generated SM2PWM45 signal is used by the deadtime logic. + * 0b01..Inverted generated SM2PWM45 signal is used by the deadtime logic. + * 0b10..SWCOUT[SM2OUT45] is used by the deadtime logic. + * 0b11..PWM2_EXTB signal is used by the deadtime logic. + */ #define PWM_DTSRCSEL_SM2SEL45(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM2SEL45_SHIFT)) & PWM_DTSRCSEL_SM2SEL45_MASK) #define PWM_DTSRCSEL_SM2SEL23_MASK (0xC00U) #define PWM_DTSRCSEL_SM2SEL23_SHIFT (10U) +/*! SM2SEL23 - Submodule 2 PWM23 Control Select + * 0b00..Generated SM2PWM23 signal is used by the deadtime logic. + * 0b01..Inverted generated SM2PWM23 signal is used by the deadtime logic. + * 0b10..SWCOUT[SM2OUT23] is used by the deadtime logic. + * 0b11..PWM2_EXTA signal is used by the deadtime logic. + */ #define PWM_DTSRCSEL_SM2SEL23(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM2SEL23_SHIFT)) & PWM_DTSRCSEL_SM2SEL23_MASK) #define PWM_DTSRCSEL_SM3SEL45_MASK (0x3000U) #define PWM_DTSRCSEL_SM3SEL45_SHIFT (12U) +/*! SM3SEL45 - Submodule 3 PWM45 Control Select + * 0b00..Generated SM3PWM45 signal is used by the deadtime logic. + * 0b01..Inverted generated SM3PWM45 signal is used by the deadtime logic. + * 0b10..SWCOUT[SM3OUT45] is used by the deadtime logic. + * 0b11..PWM3_EXTB signal is used by the deadtime logic. + */ #define PWM_DTSRCSEL_SM3SEL45(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM3SEL45_SHIFT)) & PWM_DTSRCSEL_SM3SEL45_MASK) #define PWM_DTSRCSEL_SM3SEL23_MASK (0xC000U) #define PWM_DTSRCSEL_SM3SEL23_SHIFT (14U) +/*! SM3SEL23 - Submodule 3 PWM23 Control Select + * 0b00..Generated SM3PWM23 signal is used by the deadtime logic. + * 0b01..Inverted generated SM3PWM23 signal is used by the deadtime logic. + * 0b10..SWCOUT[SM3OUT23] is used by the deadtime logic. + * 0b11..PWM3_EXTA signal is used by the deadtime logic. + */ #define PWM_DTSRCSEL_SM3SEL23(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM3SEL23_SHIFT)) & PWM_DTSRCSEL_SM3SEL23_MASK) +/*! @} */ /*! @name MCTRL - Master Control Register */ +/*! @{ */ #define PWM_MCTRL_LDOK_MASK (0xFU) #define PWM_MCTRL_LDOK_SHIFT (0U) +/*! LDOK - Load Okay + * 0b0000..Do not load new values. + * 0b0001..Load prescaler, modulus, and PWM values of the corresponding submodule. + */ #define PWM_MCTRL_LDOK(x) (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL_LDOK_SHIFT)) & PWM_MCTRL_LDOK_MASK) #define PWM_MCTRL_CLDOK_MASK (0xF0U) #define PWM_MCTRL_CLDOK_SHIFT (4U) #define PWM_MCTRL_CLDOK(x) (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL_CLDOK_SHIFT)) & PWM_MCTRL_CLDOK_MASK) #define PWM_MCTRL_RUN_MASK (0xF00U) #define PWM_MCTRL_RUN_SHIFT (8U) +/*! RUN - Run + * 0b0000..PWM generator is disabled in the corresponding submodule. + * 0b0001..PWM generator is enabled in the corresponding submodule. + */ #define PWM_MCTRL_RUN(x) (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL_RUN_SHIFT)) & PWM_MCTRL_RUN_MASK) #define PWM_MCTRL_IPOL_MASK (0xF000U) #define PWM_MCTRL_IPOL_SHIFT (12U) +/*! IPOL - Current Polarity + * 0b0000..PWM23 is used to generate complementary PWM pair in the corresponding submodule. + * 0b0001..PWM45 is used to generate complementary PWM pair in the corresponding submodule. + */ #define PWM_MCTRL_IPOL(x) (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL_IPOL_SHIFT)) & PWM_MCTRL_IPOL_MASK) +/*! @} */ /*! @name MCTRL2 - Master Control 2 Register */ +/*! @{ */ #define PWM_MCTRL2_MONPLL_MASK (0x3U) #define PWM_MCTRL2_MONPLL_SHIFT (0U) +/*! MONPLL - Monitor PLL State + * 0b00..Not locked. Do not monitor PLL operation. Resetting of the fractional delay block in case of PLL losing lock will be controlled by software. + * 0b01..Not locked. Monitor PLL operation to automatically disable the fractional delay block when the PLL encounters problems. + * 0b10..Locked. Do not monitor PLL operation. Resetting of the fractional delay block in case of PLL losing lock will be controlled by software. These bits are write protected until the next reset. + * 0b11..Locked. Monitor PLL operation to automatically disable the fractional delay block when the PLL encounters problems. These bits are write protected until the next reset. + */ #define PWM_MCTRL2_MONPLL(x) (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL2_MONPLL_SHIFT)) & PWM_MCTRL2_MONPLL_MASK) +/*! @} */ /*! @name FCTRL - Fault Control Register */ +/*! @{ */ #define PWM_FCTRL_FIE_MASK (0xFU) #define PWM_FCTRL_FIE_SHIFT (0U) +/*! FIE - Fault Interrupt Enables + * 0b0000..FAULTx CPU interrupt requests disabled. + * 0b0001..FAULTx CPU interrupt requests enabled. + */ #define PWM_FCTRL_FIE(x) (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL_FIE_SHIFT)) & PWM_FCTRL_FIE_MASK) #define PWM_FCTRL_FSAFE_MASK (0xF0U) #define PWM_FCTRL_FSAFE_SHIFT (4U) +/*! FSAFE - Fault Safety Mode + * 0b0000..Normal mode. PWM outputs disabled by this fault are not enabled until FSTS[FFLAGx] is clear at the start of a half cycle or full cycle depending on the state of FSTS[FFULL] without regard to the state of FSTS[FFPINx]. The PWM outputs disabled by this fault input will not be re-enabled until the actual FAULTx input signal de-asserts since the fault input will combinationally disable the PWM outputs (as programmed in DISMAPn). + * 0b0001..Safe mode. PWM outputs disabled by this fault are not enabled until FSTS[FFLAGx] is clear and FSTS[FFPINx] is clear at the start of a half cycle or full cycle depending on the state of FSTS[FFULL]. + */ #define PWM_FCTRL_FSAFE(x) (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL_FSAFE_SHIFT)) & PWM_FCTRL_FSAFE_MASK) #define PWM_FCTRL_FAUTO_MASK (0xF00U) #define PWM_FCTRL_FAUTO_SHIFT (8U) +/*! FAUTO - Automatic Fault Clearing + * 0b0000..Manual fault clearing. PWM outputs disabled by this fault are not enabled until FSTS[FFLAGx] is clear at the start of a half cycle or full cycle depending the state of FSTS[FFULL]. This is further controlled by FCTRL[FSAFE]. + * 0b0001..Automatic fault clearing. PWM outputs disabled by this fault are enabled when FSTS[FFPINx] is clear at the start of a half cycle or full cycle depending on the state of FSTS[FFULL] without regard to the state of FSTS[FFLAGx]. + */ #define PWM_FCTRL_FAUTO(x) (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL_FAUTO_SHIFT)) & PWM_FCTRL_FAUTO_MASK) #define PWM_FCTRL_FLVL_MASK (0xF000U) #define PWM_FCTRL_FLVL_SHIFT (12U) +/*! FLVL - Fault Level + * 0b0000..A logic 0 on the fault input indicates a fault condition. + * 0b0001..A logic 1 on the fault input indicates a fault condition. + */ #define PWM_FCTRL_FLVL(x) (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL_FLVL_SHIFT)) & PWM_FCTRL_FLVL_MASK) +/*! @} */ /*! @name FSTS - Fault Status Register */ +/*! @{ */ #define PWM_FSTS_FFLAG_MASK (0xFU) #define PWM_FSTS_FFLAG_SHIFT (0U) +/*! FFLAG - Fault Flags + * 0b0000..No fault on the FAULTx pin. + * 0b0001..Fault on the FAULTx pin. + */ #define PWM_FSTS_FFLAG(x) (((uint16_t)(((uint16_t)(x)) << PWM_FSTS_FFLAG_SHIFT)) & PWM_FSTS_FFLAG_MASK) #define PWM_FSTS_FFULL_MASK (0xF0U) #define PWM_FSTS_FFULL_SHIFT (4U) +/*! FFULL - Full Cycle + * 0b0000..PWM outputs are not re-enabled at the start of a full cycle + * 0b0001..PWM outputs are re-enabled at the start of a full cycle + */ #define PWM_FSTS_FFULL(x) (((uint16_t)(((uint16_t)(x)) << PWM_FSTS_FFULL_SHIFT)) & PWM_FSTS_FFULL_MASK) #define PWM_FSTS_FFPIN_MASK (0xF00U) #define PWM_FSTS_FFPIN_SHIFT (8U) #define PWM_FSTS_FFPIN(x) (((uint16_t)(((uint16_t)(x)) << PWM_FSTS_FFPIN_SHIFT)) & PWM_FSTS_FFPIN_MASK) #define PWM_FSTS_FHALF_MASK (0xF000U) #define PWM_FSTS_FHALF_SHIFT (12U) +/*! FHALF - Half Cycle Fault Recovery + * 0b0000..PWM outputs are not re-enabled at the start of a half cycle. + * 0b0001..PWM outputs are re-enabled at the start of a half cycle (as defined by VAL0). + */ #define PWM_FSTS_FHALF(x) (((uint16_t)(((uint16_t)(x)) << PWM_FSTS_FHALF_SHIFT)) & PWM_FSTS_FHALF_MASK) +/*! @} */ /*! @name FFILT - Fault Filter Register */ +/*! @{ */ #define PWM_FFILT_FILT_PER_MASK (0xFFU) #define PWM_FFILT_FILT_PER_SHIFT (0U) #define PWM_FFILT_FILT_PER(x) (((uint16_t)(((uint16_t)(x)) << PWM_FFILT_FILT_PER_SHIFT)) & PWM_FFILT_FILT_PER_MASK) @@ -18017,17 +29266,34 @@ typedef struct { #define PWM_FFILT_FILT_CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_FFILT_FILT_CNT_SHIFT)) & PWM_FFILT_FILT_CNT_MASK) #define PWM_FFILT_GSTR_MASK (0x8000U) #define PWM_FFILT_GSTR_SHIFT (15U) +/*! GSTR - Fault Glitch Stretch Enable + * 0b0..Fault input glitch stretching is disabled. + * 0b1..Input fault signals will be stretched to at least 2 IPBus clock cycles. + */ #define PWM_FFILT_GSTR(x) (((uint16_t)(((uint16_t)(x)) << PWM_FFILT_GSTR_SHIFT)) & PWM_FFILT_GSTR_MASK) +/*! @} */ /*! @name FTST - Fault Test Register */ +/*! @{ */ #define PWM_FTST_FTEST_MASK (0x1U) #define PWM_FTST_FTEST_SHIFT (0U) +/*! FTEST - Fault Test + * 0b0..No fault + * 0b1..Cause a simulated fault + */ #define PWM_FTST_FTEST(x) (((uint16_t)(((uint16_t)(x)) << PWM_FTST_FTEST_SHIFT)) & PWM_FTST_FTEST_MASK) +/*! @} */ /*! @name FCTRL2 - Fault Control 2 Register */ +/*! @{ */ #define PWM_FCTRL2_NOCOMB_MASK (0xFU) #define PWM_FCTRL2_NOCOMB_SHIFT (0U) +/*! NOCOMB - No Combinational Path From Fault Input To PWM Output + * 0b0000..There is a combinational link from the fault inputs to the PWM outputs. The fault inputs are combined with the filtered and latched fault signals to disable the PWM outputs. + * 0b0001..The direct combinational path from the fault inputs to the PWM outputs is disabled and the filtered and latched fault signals are used to disable the PWM outputs. + */ #define PWM_FCTRL2_NOCOMB(x) (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL2_NOCOMB_SHIFT)) & PWM_FCTRL2_NOCOMB_MASK) +/*! @} */ /*! @@ -18162,6 +29428,7 @@ typedef struct { */ /*! @name CTRL - Control Register 0 */ +/*! @{ */ #define PXP_CTRL_ENABLE_MASK (0x1U) #define PXP_CTRL_ENABLE_SHIFT (0U) #define PXP_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_ENABLE_SHIFT)) & PXP_CTRL_ENABLE_MASK) @@ -18179,6 +29446,12 @@ typedef struct { #define PXP_CTRL_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_RSVD0_SHIFT)) & PXP_CTRL_RSVD0_MASK) #define PXP_CTRL_ROTATE_MASK (0x300U) #define PXP_CTRL_ROTATE_SHIFT (8U) +/*! ROTATE + * 0b00..ROT_0 + * 0b01..ROT_90 + * 0b10..ROT_180 + * 0b11..ROT_270 + */ #define PXP_CTRL_ROTATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_ROTATE_SHIFT)) & PXP_CTRL_ROTATE_MASK) #define PXP_CTRL_HFLIP_MASK (0x400U) #define PXP_CTRL_HFLIP_SHIFT (10U) @@ -18194,6 +29467,10 @@ typedef struct { #define PXP_CTRL_ROT_POS(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_ROT_POS_SHIFT)) & PXP_CTRL_ROT_POS_MASK) #define PXP_CTRL_BLOCK_SIZE_MASK (0x800000U) #define PXP_CTRL_BLOCK_SIZE_SHIFT (23U) +/*! BLOCK_SIZE + * 0b0..Process 8x8 pixel blocks. + * 0b1..Process 16x16 pixel blocks. + */ #define PXP_CTRL_BLOCK_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_BLOCK_SIZE_SHIFT)) & PXP_CTRL_BLOCK_SIZE_MASK) #define PXP_CTRL_RSVD3_MASK (0xF000000U) #define PXP_CTRL_RSVD3_SHIFT (24U) @@ -18210,8 +29487,10 @@ typedef struct { #define PXP_CTRL_SFTRST_MASK (0x80000000U) #define PXP_CTRL_SFTRST_SHIFT (31U) #define PXP_CTRL_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SFTRST_SHIFT)) & PXP_CTRL_SFTRST_MASK) +/*! @} */ /*! @name CTRL_SET - Control Register 0 */ +/*! @{ */ #define PXP_CTRL_SET_ENABLE_MASK (0x1U) #define PXP_CTRL_SET_ENABLE_SHIFT (0U) #define PXP_CTRL_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_ENABLE_SHIFT)) & PXP_CTRL_SET_ENABLE_MASK) @@ -18229,6 +29508,12 @@ typedef struct { #define PXP_CTRL_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_RSVD0_SHIFT)) & PXP_CTRL_SET_RSVD0_MASK) #define PXP_CTRL_SET_ROTATE_MASK (0x300U) #define PXP_CTRL_SET_ROTATE_SHIFT (8U) +/*! ROTATE + * 0b00..ROT_0 + * 0b01..ROT_90 + * 0b10..ROT_180 + * 0b11..ROT_270 + */ #define PXP_CTRL_SET_ROTATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_ROTATE_SHIFT)) & PXP_CTRL_SET_ROTATE_MASK) #define PXP_CTRL_SET_HFLIP_MASK (0x400U) #define PXP_CTRL_SET_HFLIP_SHIFT (10U) @@ -18244,6 +29529,10 @@ typedef struct { #define PXP_CTRL_SET_ROT_POS(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_ROT_POS_SHIFT)) & PXP_CTRL_SET_ROT_POS_MASK) #define PXP_CTRL_SET_BLOCK_SIZE_MASK (0x800000U) #define PXP_CTRL_SET_BLOCK_SIZE_SHIFT (23U) +/*! BLOCK_SIZE + * 0b0..Process 8x8 pixel blocks. + * 0b1..Process 16x16 pixel blocks. + */ #define PXP_CTRL_SET_BLOCK_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_BLOCK_SIZE_SHIFT)) & PXP_CTRL_SET_BLOCK_SIZE_MASK) #define PXP_CTRL_SET_RSVD3_MASK (0xF000000U) #define PXP_CTRL_SET_RSVD3_SHIFT (24U) @@ -18260,8 +29549,10 @@ typedef struct { #define PXP_CTRL_SET_SFTRST_MASK (0x80000000U) #define PXP_CTRL_SET_SFTRST_SHIFT (31U) #define PXP_CTRL_SET_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_SFTRST_SHIFT)) & PXP_CTRL_SET_SFTRST_MASK) +/*! @} */ /*! @name CTRL_CLR - Control Register 0 */ +/*! @{ */ #define PXP_CTRL_CLR_ENABLE_MASK (0x1U) #define PXP_CTRL_CLR_ENABLE_SHIFT (0U) #define PXP_CTRL_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_ENABLE_SHIFT)) & PXP_CTRL_CLR_ENABLE_MASK) @@ -18279,6 +29570,12 @@ typedef struct { #define PXP_CTRL_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_RSVD0_SHIFT)) & PXP_CTRL_CLR_RSVD0_MASK) #define PXP_CTRL_CLR_ROTATE_MASK (0x300U) #define PXP_CTRL_CLR_ROTATE_SHIFT (8U) +/*! ROTATE + * 0b00..ROT_0 + * 0b01..ROT_90 + * 0b10..ROT_180 + * 0b11..ROT_270 + */ #define PXP_CTRL_CLR_ROTATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_ROTATE_SHIFT)) & PXP_CTRL_CLR_ROTATE_MASK) #define PXP_CTRL_CLR_HFLIP_MASK (0x400U) #define PXP_CTRL_CLR_HFLIP_SHIFT (10U) @@ -18294,6 +29591,10 @@ typedef struct { #define PXP_CTRL_CLR_ROT_POS(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_ROT_POS_SHIFT)) & PXP_CTRL_CLR_ROT_POS_MASK) #define PXP_CTRL_CLR_BLOCK_SIZE_MASK (0x800000U) #define PXP_CTRL_CLR_BLOCK_SIZE_SHIFT (23U) +/*! BLOCK_SIZE + * 0b0..Process 8x8 pixel blocks. + * 0b1..Process 16x16 pixel blocks. + */ #define PXP_CTRL_CLR_BLOCK_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_BLOCK_SIZE_SHIFT)) & PXP_CTRL_CLR_BLOCK_SIZE_MASK) #define PXP_CTRL_CLR_RSVD3_MASK (0xF000000U) #define PXP_CTRL_CLR_RSVD3_SHIFT (24U) @@ -18310,8 +29611,10 @@ typedef struct { #define PXP_CTRL_CLR_SFTRST_MASK (0x80000000U) #define PXP_CTRL_CLR_SFTRST_SHIFT (31U) #define PXP_CTRL_CLR_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_SFTRST_SHIFT)) & PXP_CTRL_CLR_SFTRST_MASK) +/*! @} */ /*! @name CTRL_TOG - Control Register 0 */ +/*! @{ */ #define PXP_CTRL_TOG_ENABLE_MASK (0x1U) #define PXP_CTRL_TOG_ENABLE_SHIFT (0U) #define PXP_CTRL_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_ENABLE_SHIFT)) & PXP_CTRL_TOG_ENABLE_MASK) @@ -18329,6 +29632,12 @@ typedef struct { #define PXP_CTRL_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_RSVD0_SHIFT)) & PXP_CTRL_TOG_RSVD0_MASK) #define PXP_CTRL_TOG_ROTATE_MASK (0x300U) #define PXP_CTRL_TOG_ROTATE_SHIFT (8U) +/*! ROTATE + * 0b00..ROT_0 + * 0b01..ROT_90 + * 0b10..ROT_180 + * 0b11..ROT_270 + */ #define PXP_CTRL_TOG_ROTATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_ROTATE_SHIFT)) & PXP_CTRL_TOG_ROTATE_MASK) #define PXP_CTRL_TOG_HFLIP_MASK (0x400U) #define PXP_CTRL_TOG_HFLIP_SHIFT (10U) @@ -18344,6 +29653,10 @@ typedef struct { #define PXP_CTRL_TOG_ROT_POS(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_ROT_POS_SHIFT)) & PXP_CTRL_TOG_ROT_POS_MASK) #define PXP_CTRL_TOG_BLOCK_SIZE_MASK (0x800000U) #define PXP_CTRL_TOG_BLOCK_SIZE_SHIFT (23U) +/*! BLOCK_SIZE + * 0b0..Process 8x8 pixel blocks. + * 0b1..Process 16x16 pixel blocks. + */ #define PXP_CTRL_TOG_BLOCK_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_BLOCK_SIZE_SHIFT)) & PXP_CTRL_TOG_BLOCK_SIZE_MASK) #define PXP_CTRL_TOG_RSVD3_MASK (0xF000000U) #define PXP_CTRL_TOG_RSVD3_SHIFT (24U) @@ -18360,8 +29673,10 @@ typedef struct { #define PXP_CTRL_TOG_SFTRST_MASK (0x80000000U) #define PXP_CTRL_TOG_SFTRST_SHIFT (31U) #define PXP_CTRL_TOG_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_SFTRST_SHIFT)) & PXP_CTRL_TOG_SFTRST_MASK) +/*! @} */ /*! @name STAT - Status Register */ +/*! @{ */ #define PXP_STAT_IRQ_MASK (0x1U) #define PXP_STAT_IRQ_SHIFT (0U) #define PXP_STAT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_IRQ_SHIFT)) & PXP_STAT_IRQ_MASK) @@ -18389,8 +29704,10 @@ typedef struct { #define PXP_STAT_BLOCKX_MASK (0xFF000000U) #define PXP_STAT_BLOCKX_SHIFT (24U) #define PXP_STAT_BLOCKX(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_BLOCKX_SHIFT)) & PXP_STAT_BLOCKX_MASK) +/*! @} */ /*! @name STAT_SET - Status Register */ +/*! @{ */ #define PXP_STAT_SET_IRQ_MASK (0x1U) #define PXP_STAT_SET_IRQ_SHIFT (0U) #define PXP_STAT_SET_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_IRQ_SHIFT)) & PXP_STAT_SET_IRQ_MASK) @@ -18418,8 +29735,10 @@ typedef struct { #define PXP_STAT_SET_BLOCKX_MASK (0xFF000000U) #define PXP_STAT_SET_BLOCKX_SHIFT (24U) #define PXP_STAT_SET_BLOCKX(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_BLOCKX_SHIFT)) & PXP_STAT_SET_BLOCKX_MASK) +/*! @} */ /*! @name STAT_CLR - Status Register */ +/*! @{ */ #define PXP_STAT_CLR_IRQ_MASK (0x1U) #define PXP_STAT_CLR_IRQ_SHIFT (0U) #define PXP_STAT_CLR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_IRQ_SHIFT)) & PXP_STAT_CLR_IRQ_MASK) @@ -18447,8 +29766,10 @@ typedef struct { #define PXP_STAT_CLR_BLOCKX_MASK (0xFF000000U) #define PXP_STAT_CLR_BLOCKX_SHIFT (24U) #define PXP_STAT_CLR_BLOCKX(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_BLOCKX_SHIFT)) & PXP_STAT_CLR_BLOCKX_MASK) +/*! @} */ /*! @name STAT_TOG - Status Register */ +/*! @{ */ #define PXP_STAT_TOG_IRQ_MASK (0x1U) #define PXP_STAT_TOG_IRQ_SHIFT (0U) #define PXP_STAT_TOG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_IRQ_SHIFT)) & PXP_STAT_TOG_IRQ_MASK) @@ -18476,16 +29797,43 @@ typedef struct { #define PXP_STAT_TOG_BLOCKX_MASK (0xFF000000U) #define PXP_STAT_TOG_BLOCKX_SHIFT (24U) #define PXP_STAT_TOG_BLOCKX(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_BLOCKX_SHIFT)) & PXP_STAT_TOG_BLOCKX_MASK) +/*! @} */ /*! @name OUT_CTRL - Output Buffer Control Register */ +/*! @{ */ #define PXP_OUT_CTRL_FORMAT_MASK (0x1FU) #define PXP_OUT_CTRL_FORMAT_SHIFT (0U) +/*! FORMAT + * 0b00000..32-bit pixels + * 0b00100..32-bit pixels (unpacked 24-bit pixel in 32 bit DWORD.) + * 0b00101..24-bit pixels (packed 24-bit format) + * 0b01000..16-bit pixels + * 0b01001..16-bit pixels + * 0b01100..16-bit pixels + * 0b01101..16-bit pixels + * 0b01110..16-bit pixels + * 0b10000..32-bit pixels (1-plane XYUV unpacked) + * 0b10010..16-bit pixels (1-plane U0,Y0,V0,Y1 interleaved bytes) + * 0b10011..16-bit pixels (1-plane V0,Y0,U0,Y1 interleaved bytes) + * 0b10100..8-bit monochrome pixels (1-plane Y luma output) + * 0b10101..4-bit monochrome pixels (1-plane Y luma, 4 bit truncation) + * 0b11000..16-bit pixels (2-plane UV interleaved bytes) + * 0b11001..16-bit pixels (2-plane UV) + * 0b11010..16-bit pixels (2-plane VU interleaved bytes) + * 0b11011..16-bit pixels (2-plane VU) + */ #define PXP_OUT_CTRL_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_FORMAT_SHIFT)) & PXP_OUT_CTRL_FORMAT_MASK) #define PXP_OUT_CTRL_RSVD0_MASK (0xE0U) #define PXP_OUT_CTRL_RSVD0_SHIFT (5U) #define PXP_OUT_CTRL_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_RSVD0_SHIFT)) & PXP_OUT_CTRL_RSVD0_MASK) #define PXP_OUT_CTRL_INTERLACED_OUTPUT_MASK (0x300U) #define PXP_OUT_CTRL_INTERLACED_OUTPUT_SHIFT (8U) +/*! INTERLACED_OUTPUT + * 0b00..All data written in progressive format to the OUTBUF Pointer. + * 0b01..Interlaced output: only data for field 0 is written to the OUTBUF Pointer. + * 0b10..Interlaced output: only data for field 1 is written to the OUTBUF2 Pointer. + * 0b11..Interlaced output: data for field 0 is written to OUTBUF and data for field 1 is written to OUTBUF2. + */ #define PXP_OUT_CTRL_INTERLACED_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_INTERLACED_OUTPUT_SHIFT)) & PXP_OUT_CTRL_INTERLACED_OUTPUT_MASK) #define PXP_OUT_CTRL_RSVD1_MASK (0x7FFC00U) #define PXP_OUT_CTRL_RSVD1_SHIFT (10U) @@ -18496,16 +29844,43 @@ typedef struct { #define PXP_OUT_CTRL_ALPHA_MASK (0xFF000000U) #define PXP_OUT_CTRL_ALPHA_SHIFT (24U) #define PXP_OUT_CTRL_ALPHA(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_ALPHA_SHIFT)) & PXP_OUT_CTRL_ALPHA_MASK) +/*! @} */ /*! @name OUT_CTRL_SET - Output Buffer Control Register */ +/*! @{ */ #define PXP_OUT_CTRL_SET_FORMAT_MASK (0x1FU) #define PXP_OUT_CTRL_SET_FORMAT_SHIFT (0U) +/*! FORMAT + * 0b00000..32-bit pixels + * 0b00100..32-bit pixels (unpacked 24-bit pixel in 32 bit DWORD.) + * 0b00101..24-bit pixels (packed 24-bit format) + * 0b01000..16-bit pixels + * 0b01001..16-bit pixels + * 0b01100..16-bit pixels + * 0b01101..16-bit pixels + * 0b01110..16-bit pixels + * 0b10000..32-bit pixels (1-plane XYUV unpacked) + * 0b10010..16-bit pixels (1-plane U0,Y0,V0,Y1 interleaved bytes) + * 0b10011..16-bit pixels (1-plane V0,Y0,U0,Y1 interleaved bytes) + * 0b10100..8-bit monochrome pixels (1-plane Y luma output) + * 0b10101..4-bit monochrome pixels (1-plane Y luma, 4 bit truncation) + * 0b11000..16-bit pixels (2-plane UV interleaved bytes) + * 0b11001..16-bit pixels (2-plane UV) + * 0b11010..16-bit pixels (2-plane VU interleaved bytes) + * 0b11011..16-bit pixels (2-plane VU) + */ #define PXP_OUT_CTRL_SET_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_SET_FORMAT_SHIFT)) & PXP_OUT_CTRL_SET_FORMAT_MASK) #define PXP_OUT_CTRL_SET_RSVD0_MASK (0xE0U) #define PXP_OUT_CTRL_SET_RSVD0_SHIFT (5U) #define PXP_OUT_CTRL_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_SET_RSVD0_SHIFT)) & PXP_OUT_CTRL_SET_RSVD0_MASK) #define PXP_OUT_CTRL_SET_INTERLACED_OUTPUT_MASK (0x300U) #define PXP_OUT_CTRL_SET_INTERLACED_OUTPUT_SHIFT (8U) +/*! INTERLACED_OUTPUT + * 0b00..All data written in progressive format to the OUTBUF Pointer. + * 0b01..Interlaced output: only data for field 0 is written to the OUTBUF Pointer. + * 0b10..Interlaced output: only data for field 1 is written to the OUTBUF2 Pointer. + * 0b11..Interlaced output: data for field 0 is written to OUTBUF and data for field 1 is written to OUTBUF2. + */ #define PXP_OUT_CTRL_SET_INTERLACED_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_SET_INTERLACED_OUTPUT_SHIFT)) & PXP_OUT_CTRL_SET_INTERLACED_OUTPUT_MASK) #define PXP_OUT_CTRL_SET_RSVD1_MASK (0x7FFC00U) #define PXP_OUT_CTRL_SET_RSVD1_SHIFT (10U) @@ -18516,16 +29891,43 @@ typedef struct { #define PXP_OUT_CTRL_SET_ALPHA_MASK (0xFF000000U) #define PXP_OUT_CTRL_SET_ALPHA_SHIFT (24U) #define PXP_OUT_CTRL_SET_ALPHA(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_SET_ALPHA_SHIFT)) & PXP_OUT_CTRL_SET_ALPHA_MASK) +/*! @} */ /*! @name OUT_CTRL_CLR - Output Buffer Control Register */ +/*! @{ */ #define PXP_OUT_CTRL_CLR_FORMAT_MASK (0x1FU) #define PXP_OUT_CTRL_CLR_FORMAT_SHIFT (0U) +/*! FORMAT + * 0b00000..32-bit pixels + * 0b00100..32-bit pixels (unpacked 24-bit pixel in 32 bit DWORD.) + * 0b00101..24-bit pixels (packed 24-bit format) + * 0b01000..16-bit pixels + * 0b01001..16-bit pixels + * 0b01100..16-bit pixels + * 0b01101..16-bit pixels + * 0b01110..16-bit pixels + * 0b10000..32-bit pixels (1-plane XYUV unpacked) + * 0b10010..16-bit pixels (1-plane U0,Y0,V0,Y1 interleaved bytes) + * 0b10011..16-bit pixels (1-plane V0,Y0,U0,Y1 interleaved bytes) + * 0b10100..8-bit monochrome pixels (1-plane Y luma output) + * 0b10101..4-bit monochrome pixels (1-plane Y luma, 4 bit truncation) + * 0b11000..16-bit pixels (2-plane UV interleaved bytes) + * 0b11001..16-bit pixels (2-plane UV) + * 0b11010..16-bit pixels (2-plane VU interleaved bytes) + * 0b11011..16-bit pixels (2-plane VU) + */ #define PXP_OUT_CTRL_CLR_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_CLR_FORMAT_SHIFT)) & PXP_OUT_CTRL_CLR_FORMAT_MASK) #define PXP_OUT_CTRL_CLR_RSVD0_MASK (0xE0U) #define PXP_OUT_CTRL_CLR_RSVD0_SHIFT (5U) #define PXP_OUT_CTRL_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_CLR_RSVD0_SHIFT)) & PXP_OUT_CTRL_CLR_RSVD0_MASK) #define PXP_OUT_CTRL_CLR_INTERLACED_OUTPUT_MASK (0x300U) #define PXP_OUT_CTRL_CLR_INTERLACED_OUTPUT_SHIFT (8U) +/*! INTERLACED_OUTPUT + * 0b00..All data written in progressive format to the OUTBUF Pointer. + * 0b01..Interlaced output: only data for field 0 is written to the OUTBUF Pointer. + * 0b10..Interlaced output: only data for field 1 is written to the OUTBUF2 Pointer. + * 0b11..Interlaced output: data for field 0 is written to OUTBUF and data for field 1 is written to OUTBUF2. + */ #define PXP_OUT_CTRL_CLR_INTERLACED_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_CLR_INTERLACED_OUTPUT_SHIFT)) & PXP_OUT_CTRL_CLR_INTERLACED_OUTPUT_MASK) #define PXP_OUT_CTRL_CLR_RSVD1_MASK (0x7FFC00U) #define PXP_OUT_CTRL_CLR_RSVD1_SHIFT (10U) @@ -18536,16 +29938,43 @@ typedef struct { #define PXP_OUT_CTRL_CLR_ALPHA_MASK (0xFF000000U) #define PXP_OUT_CTRL_CLR_ALPHA_SHIFT (24U) #define PXP_OUT_CTRL_CLR_ALPHA(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_CLR_ALPHA_SHIFT)) & PXP_OUT_CTRL_CLR_ALPHA_MASK) +/*! @} */ /*! @name OUT_CTRL_TOG - Output Buffer Control Register */ +/*! @{ */ #define PXP_OUT_CTRL_TOG_FORMAT_MASK (0x1FU) #define PXP_OUT_CTRL_TOG_FORMAT_SHIFT (0U) +/*! FORMAT + * 0b00000..32-bit pixels + * 0b00100..32-bit pixels (unpacked 24-bit pixel in 32 bit DWORD.) + * 0b00101..24-bit pixels (packed 24-bit format) + * 0b01000..16-bit pixels + * 0b01001..16-bit pixels + * 0b01100..16-bit pixels + * 0b01101..16-bit pixels + * 0b01110..16-bit pixels + * 0b10000..32-bit pixels (1-plane XYUV unpacked) + * 0b10010..16-bit pixels (1-plane U0,Y0,V0,Y1 interleaved bytes) + * 0b10011..16-bit pixels (1-plane V0,Y0,U0,Y1 interleaved bytes) + * 0b10100..8-bit monochrome pixels (1-plane Y luma output) + * 0b10101..4-bit monochrome pixels (1-plane Y luma, 4 bit truncation) + * 0b11000..16-bit pixels (2-plane UV interleaved bytes) + * 0b11001..16-bit pixels (2-plane UV) + * 0b11010..16-bit pixels (2-plane VU interleaved bytes) + * 0b11011..16-bit pixels (2-plane VU) + */ #define PXP_OUT_CTRL_TOG_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_TOG_FORMAT_SHIFT)) & PXP_OUT_CTRL_TOG_FORMAT_MASK) #define PXP_OUT_CTRL_TOG_RSVD0_MASK (0xE0U) #define PXP_OUT_CTRL_TOG_RSVD0_SHIFT (5U) #define PXP_OUT_CTRL_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_TOG_RSVD0_SHIFT)) & PXP_OUT_CTRL_TOG_RSVD0_MASK) #define PXP_OUT_CTRL_TOG_INTERLACED_OUTPUT_MASK (0x300U) #define PXP_OUT_CTRL_TOG_INTERLACED_OUTPUT_SHIFT (8U) +/*! INTERLACED_OUTPUT + * 0b00..All data written in progressive format to the OUTBUF Pointer. + * 0b01..Interlaced output: only data for field 0 is written to the OUTBUF Pointer. + * 0b10..Interlaced output: only data for field 1 is written to the OUTBUF2 Pointer. + * 0b11..Interlaced output: data for field 0 is written to OUTBUF and data for field 1 is written to OUTBUF2. + */ #define PXP_OUT_CTRL_TOG_INTERLACED_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_TOG_INTERLACED_OUTPUT_SHIFT)) & PXP_OUT_CTRL_TOG_INTERLACED_OUTPUT_MASK) #define PXP_OUT_CTRL_TOG_RSVD1_MASK (0x7FFC00U) #define PXP_OUT_CTRL_TOG_RSVD1_SHIFT (10U) @@ -18556,26 +29985,34 @@ typedef struct { #define PXP_OUT_CTRL_TOG_ALPHA_MASK (0xFF000000U) #define PXP_OUT_CTRL_TOG_ALPHA_SHIFT (24U) #define PXP_OUT_CTRL_TOG_ALPHA(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_TOG_ALPHA_SHIFT)) & PXP_OUT_CTRL_TOG_ALPHA_MASK) +/*! @} */ /*! @name OUT_BUF - Output Frame Buffer Pointer */ +/*! @{ */ #define PXP_OUT_BUF_ADDR_MASK (0xFFFFFFFFU) #define PXP_OUT_BUF_ADDR_SHIFT (0U) #define PXP_OUT_BUF_ADDR(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_BUF_ADDR_SHIFT)) & PXP_OUT_BUF_ADDR_MASK) +/*! @} */ /*! @name OUT_BUF2 - Output Frame Buffer Pointer #2 */ +/*! @{ */ #define PXP_OUT_BUF2_ADDR_MASK (0xFFFFFFFFU) #define PXP_OUT_BUF2_ADDR_SHIFT (0U) #define PXP_OUT_BUF2_ADDR(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_BUF2_ADDR_SHIFT)) & PXP_OUT_BUF2_ADDR_MASK) +/*! @} */ /*! @name OUT_PITCH - Output Buffer Pitch */ +/*! @{ */ #define PXP_OUT_PITCH_PITCH_MASK (0xFFFFU) #define PXP_OUT_PITCH_PITCH_SHIFT (0U) #define PXP_OUT_PITCH_PITCH(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_PITCH_PITCH_SHIFT)) & PXP_OUT_PITCH_PITCH_MASK) #define PXP_OUT_PITCH_RSVD_MASK (0xFFFF0000U) #define PXP_OUT_PITCH_RSVD_SHIFT (16U) #define PXP_OUT_PITCH_RSVD(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_PITCH_RSVD_SHIFT)) & PXP_OUT_PITCH_RSVD_MASK) +/*! @} */ /*! @name OUT_LRC - Output Surface Lower Right Coordinate */ +/*! @{ */ #define PXP_OUT_LRC_Y_MASK (0x3FFFU) #define PXP_OUT_LRC_Y_SHIFT (0U) #define PXP_OUT_LRC_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_LRC_Y_SHIFT)) & PXP_OUT_LRC_Y_MASK) @@ -18588,8 +30025,10 @@ typedef struct { #define PXP_OUT_LRC_RSVD1_MASK (0xC0000000U) #define PXP_OUT_LRC_RSVD1_SHIFT (30U) #define PXP_OUT_LRC_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_LRC_RSVD1_SHIFT)) & PXP_OUT_LRC_RSVD1_MASK) +/*! @} */ /*! @name OUT_PS_ULC - Processed Surface Upper Left Coordinate */ +/*! @{ */ #define PXP_OUT_PS_ULC_Y_MASK (0x3FFFU) #define PXP_OUT_PS_ULC_Y_SHIFT (0U) #define PXP_OUT_PS_ULC_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_PS_ULC_Y_SHIFT)) & PXP_OUT_PS_ULC_Y_MASK) @@ -18602,8 +30041,10 @@ typedef struct { #define PXP_OUT_PS_ULC_RSVD1_MASK (0xC0000000U) #define PXP_OUT_PS_ULC_RSVD1_SHIFT (30U) #define PXP_OUT_PS_ULC_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_PS_ULC_RSVD1_SHIFT)) & PXP_OUT_PS_ULC_RSVD1_MASK) +/*! @} */ /*! @name OUT_PS_LRC - Processed Surface Lower Right Coordinate */ +/*! @{ */ #define PXP_OUT_PS_LRC_Y_MASK (0x3FFFU) #define PXP_OUT_PS_LRC_Y_SHIFT (0U) #define PXP_OUT_PS_LRC_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_PS_LRC_Y_SHIFT)) & PXP_OUT_PS_LRC_Y_MASK) @@ -18616,8 +30057,10 @@ typedef struct { #define PXP_OUT_PS_LRC_RSVD1_MASK (0xC0000000U) #define PXP_OUT_PS_LRC_RSVD1_SHIFT (30U) #define PXP_OUT_PS_LRC_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_PS_LRC_RSVD1_SHIFT)) & PXP_OUT_PS_LRC_RSVD1_MASK) +/*! @} */ /*! @name OUT_AS_ULC - Alpha Surface Upper Left Coordinate */ +/*! @{ */ #define PXP_OUT_AS_ULC_Y_MASK (0x3FFFU) #define PXP_OUT_AS_ULC_Y_SHIFT (0U) #define PXP_OUT_AS_ULC_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_AS_ULC_Y_SHIFT)) & PXP_OUT_AS_ULC_Y_MASK) @@ -18630,8 +30073,10 @@ typedef struct { #define PXP_OUT_AS_ULC_RSVD1_MASK (0xC0000000U) #define PXP_OUT_AS_ULC_RSVD1_SHIFT (30U) #define PXP_OUT_AS_ULC_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_AS_ULC_RSVD1_SHIFT)) & PXP_OUT_AS_ULC_RSVD1_MASK) +/*! @} */ /*! @name OUT_AS_LRC - Alpha Surface Lower Right Coordinate */ +/*! @{ */ #define PXP_OUT_AS_LRC_Y_MASK (0x3FFFU) #define PXP_OUT_AS_LRC_Y_SHIFT (0U) #define PXP_OUT_AS_LRC_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_AS_LRC_Y_SHIFT)) & PXP_OUT_AS_LRC_Y_MASK) @@ -18644,10 +30089,29 @@ typedef struct { #define PXP_OUT_AS_LRC_RSVD1_MASK (0xC0000000U) #define PXP_OUT_AS_LRC_RSVD1_SHIFT (30U) #define PXP_OUT_AS_LRC_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_AS_LRC_RSVD1_SHIFT)) & PXP_OUT_AS_LRC_RSVD1_MASK) +/*! @} */ /*! @name PS_CTRL - Processed Surface (PS) Control Register */ +/*! @{ */ #define PXP_PS_CTRL_FORMAT_MASK (0x1FU) #define PXP_PS_CTRL_FORMAT_SHIFT (0U) +/*! FORMAT + * 0b00100..32-bit pixels (unpacked 24-bit format) + * 0b01100..16-bit pixels + * 0b01101..16-bit pixels + * 0b01110..16-bit pixels + * 0b10000..32-bit pixels (1-plane XYUV unpacked) + * 0b10010..16-bit pixels (1-plane U0,Y0,V0,Y1 interleaved bytes) + * 0b10011..16-bit pixels (1-plane V0,Y0,U0,Y1 interleaved bytes) + * 0b10100..8-bit monochrome pixels (1-plane Y luma output) + * 0b10101..4-bit monochrome pixels (1-plane Y luma, 4 bit truncation) + * 0b11000..16-bit pixels (2-plane UV interleaved bytes) + * 0b11001..16-bit pixels (2-plane UV) + * 0b11010..16-bit pixels (2-plane VU interleaved bytes) + * 0b11011..16-bit pixels (2-plane VU) + * 0b11110..16-bit pixels (3-plane format) + * 0b11111..16-bit pixels (3-plane format) + */ #define PXP_PS_CTRL_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_FORMAT_SHIFT)) & PXP_PS_CTRL_FORMAT_MASK) #define PXP_PS_CTRL_WB_SWAP_MASK (0x20U) #define PXP_PS_CTRL_WB_SWAP_SHIFT (5U) @@ -18657,17 +30121,48 @@ typedef struct { #define PXP_PS_CTRL_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_RSVD0_SHIFT)) & PXP_PS_CTRL_RSVD0_MASK) #define PXP_PS_CTRL_DECY_MASK (0x300U) #define PXP_PS_CTRL_DECY_SHIFT (8U) +/*! DECY + * 0b00..Disable pre-decimation filter. + * 0b01..Decimate PS by 2. + * 0b10..Decimate PS by 4. + * 0b11..Decimate PS by 8. + */ #define PXP_PS_CTRL_DECY(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_DECY_SHIFT)) & PXP_PS_CTRL_DECY_MASK) #define PXP_PS_CTRL_DECX_MASK (0xC00U) #define PXP_PS_CTRL_DECX_SHIFT (10U) +/*! DECX + * 0b00..Disable pre-decimation filter. + * 0b01..Decimate PS by 2. + * 0b10..Decimate PS by 4. + * 0b11..Decimate PS by 8. + */ #define PXP_PS_CTRL_DECX(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_DECX_SHIFT)) & PXP_PS_CTRL_DECX_MASK) #define PXP_PS_CTRL_RSVD1_MASK (0xFFFFF000U) #define PXP_PS_CTRL_RSVD1_SHIFT (12U) #define PXP_PS_CTRL_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_RSVD1_SHIFT)) & PXP_PS_CTRL_RSVD1_MASK) +/*! @} */ /*! @name PS_CTRL_SET - Processed Surface (PS) Control Register */ +/*! @{ */ #define PXP_PS_CTRL_SET_FORMAT_MASK (0x1FU) #define PXP_PS_CTRL_SET_FORMAT_SHIFT (0U) +/*! FORMAT + * 0b00100..32-bit pixels (unpacked 24-bit format) + * 0b01100..16-bit pixels + * 0b01101..16-bit pixels + * 0b01110..16-bit pixels + * 0b10000..32-bit pixels (1-plane XYUV unpacked) + * 0b10010..16-bit pixels (1-plane U0,Y0,V0,Y1 interleaved bytes) + * 0b10011..16-bit pixels (1-plane V0,Y0,U0,Y1 interleaved bytes) + * 0b10100..8-bit monochrome pixels (1-plane Y luma output) + * 0b10101..4-bit monochrome pixels (1-plane Y luma, 4 bit truncation) + * 0b11000..16-bit pixels (2-plane UV interleaved bytes) + * 0b11001..16-bit pixels (2-plane UV) + * 0b11010..16-bit pixels (2-plane VU interleaved bytes) + * 0b11011..16-bit pixels (2-plane VU) + * 0b11110..16-bit pixels (3-plane format) + * 0b11111..16-bit pixels (3-plane format) + */ #define PXP_PS_CTRL_SET_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_SET_FORMAT_SHIFT)) & PXP_PS_CTRL_SET_FORMAT_MASK) #define PXP_PS_CTRL_SET_WB_SWAP_MASK (0x20U) #define PXP_PS_CTRL_SET_WB_SWAP_SHIFT (5U) @@ -18677,17 +30172,48 @@ typedef struct { #define PXP_PS_CTRL_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_SET_RSVD0_SHIFT)) & PXP_PS_CTRL_SET_RSVD0_MASK) #define PXP_PS_CTRL_SET_DECY_MASK (0x300U) #define PXP_PS_CTRL_SET_DECY_SHIFT (8U) +/*! DECY + * 0b00..Disable pre-decimation filter. + * 0b01..Decimate PS by 2. + * 0b10..Decimate PS by 4. + * 0b11..Decimate PS by 8. + */ #define PXP_PS_CTRL_SET_DECY(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_SET_DECY_SHIFT)) & PXP_PS_CTRL_SET_DECY_MASK) #define PXP_PS_CTRL_SET_DECX_MASK (0xC00U) #define PXP_PS_CTRL_SET_DECX_SHIFT (10U) +/*! DECX + * 0b00..Disable pre-decimation filter. + * 0b01..Decimate PS by 2. + * 0b10..Decimate PS by 4. + * 0b11..Decimate PS by 8. + */ #define PXP_PS_CTRL_SET_DECX(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_SET_DECX_SHIFT)) & PXP_PS_CTRL_SET_DECX_MASK) #define PXP_PS_CTRL_SET_RSVD1_MASK (0xFFFFF000U) #define PXP_PS_CTRL_SET_RSVD1_SHIFT (12U) #define PXP_PS_CTRL_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_SET_RSVD1_SHIFT)) & PXP_PS_CTRL_SET_RSVD1_MASK) +/*! @} */ /*! @name PS_CTRL_CLR - Processed Surface (PS) Control Register */ +/*! @{ */ #define PXP_PS_CTRL_CLR_FORMAT_MASK (0x1FU) #define PXP_PS_CTRL_CLR_FORMAT_SHIFT (0U) +/*! FORMAT + * 0b00100..32-bit pixels (unpacked 24-bit format) + * 0b01100..16-bit pixels + * 0b01101..16-bit pixels + * 0b01110..16-bit pixels + * 0b10000..32-bit pixels (1-plane XYUV unpacked) + * 0b10010..16-bit pixels (1-plane U0,Y0,V0,Y1 interleaved bytes) + * 0b10011..16-bit pixels (1-plane V0,Y0,U0,Y1 interleaved bytes) + * 0b10100..8-bit monochrome pixels (1-plane Y luma output) + * 0b10101..4-bit monochrome pixels (1-plane Y luma, 4 bit truncation) + * 0b11000..16-bit pixels (2-plane UV interleaved bytes) + * 0b11001..16-bit pixels (2-plane UV) + * 0b11010..16-bit pixels (2-plane VU interleaved bytes) + * 0b11011..16-bit pixels (2-plane VU) + * 0b11110..16-bit pixels (3-plane format) + * 0b11111..16-bit pixels (3-plane format) + */ #define PXP_PS_CTRL_CLR_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_CLR_FORMAT_SHIFT)) & PXP_PS_CTRL_CLR_FORMAT_MASK) #define PXP_PS_CTRL_CLR_WB_SWAP_MASK (0x20U) #define PXP_PS_CTRL_CLR_WB_SWAP_SHIFT (5U) @@ -18697,17 +30223,48 @@ typedef struct { #define PXP_PS_CTRL_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_CLR_RSVD0_SHIFT)) & PXP_PS_CTRL_CLR_RSVD0_MASK) #define PXP_PS_CTRL_CLR_DECY_MASK (0x300U) #define PXP_PS_CTRL_CLR_DECY_SHIFT (8U) +/*! DECY + * 0b00..Disable pre-decimation filter. + * 0b01..Decimate PS by 2. + * 0b10..Decimate PS by 4. + * 0b11..Decimate PS by 8. + */ #define PXP_PS_CTRL_CLR_DECY(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_CLR_DECY_SHIFT)) & PXP_PS_CTRL_CLR_DECY_MASK) #define PXP_PS_CTRL_CLR_DECX_MASK (0xC00U) #define PXP_PS_CTRL_CLR_DECX_SHIFT (10U) +/*! DECX + * 0b00..Disable pre-decimation filter. + * 0b01..Decimate PS by 2. + * 0b10..Decimate PS by 4. + * 0b11..Decimate PS by 8. + */ #define PXP_PS_CTRL_CLR_DECX(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_CLR_DECX_SHIFT)) & PXP_PS_CTRL_CLR_DECX_MASK) #define PXP_PS_CTRL_CLR_RSVD1_MASK (0xFFFFF000U) #define PXP_PS_CTRL_CLR_RSVD1_SHIFT (12U) #define PXP_PS_CTRL_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_CLR_RSVD1_SHIFT)) & PXP_PS_CTRL_CLR_RSVD1_MASK) +/*! @} */ /*! @name PS_CTRL_TOG - Processed Surface (PS) Control Register */ +/*! @{ */ #define PXP_PS_CTRL_TOG_FORMAT_MASK (0x1FU) #define PXP_PS_CTRL_TOG_FORMAT_SHIFT (0U) +/*! FORMAT + * 0b00100..32-bit pixels (unpacked 24-bit format) + * 0b01100..16-bit pixels + * 0b01101..16-bit pixels + * 0b01110..16-bit pixels + * 0b10000..32-bit pixels (1-plane XYUV unpacked) + * 0b10010..16-bit pixels (1-plane U0,Y0,V0,Y1 interleaved bytes) + * 0b10011..16-bit pixels (1-plane V0,Y0,U0,Y1 interleaved bytes) + * 0b10100..8-bit monochrome pixels (1-plane Y luma output) + * 0b10101..4-bit monochrome pixels (1-plane Y luma, 4 bit truncation) + * 0b11000..16-bit pixels (2-plane UV interleaved bytes) + * 0b11001..16-bit pixels (2-plane UV) + * 0b11010..16-bit pixels (2-plane VU interleaved bytes) + * 0b11011..16-bit pixels (2-plane VU) + * 0b11110..16-bit pixels (3-plane format) + * 0b11111..16-bit pixels (3-plane format) + */ #define PXP_PS_CTRL_TOG_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_TOG_FORMAT_SHIFT)) & PXP_PS_CTRL_TOG_FORMAT_MASK) #define PXP_PS_CTRL_TOG_WB_SWAP_MASK (0x20U) #define PXP_PS_CTRL_TOG_WB_SWAP_SHIFT (5U) @@ -18717,46 +30274,70 @@ typedef struct { #define PXP_PS_CTRL_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_TOG_RSVD0_SHIFT)) & PXP_PS_CTRL_TOG_RSVD0_MASK) #define PXP_PS_CTRL_TOG_DECY_MASK (0x300U) #define PXP_PS_CTRL_TOG_DECY_SHIFT (8U) +/*! DECY + * 0b00..Disable pre-decimation filter. + * 0b01..Decimate PS by 2. + * 0b10..Decimate PS by 4. + * 0b11..Decimate PS by 8. + */ #define PXP_PS_CTRL_TOG_DECY(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_TOG_DECY_SHIFT)) & PXP_PS_CTRL_TOG_DECY_MASK) #define PXP_PS_CTRL_TOG_DECX_MASK (0xC00U) #define PXP_PS_CTRL_TOG_DECX_SHIFT (10U) +/*! DECX + * 0b00..Disable pre-decimation filter. + * 0b01..Decimate PS by 2. + * 0b10..Decimate PS by 4. + * 0b11..Decimate PS by 8. + */ #define PXP_PS_CTRL_TOG_DECX(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_TOG_DECX_SHIFT)) & PXP_PS_CTRL_TOG_DECX_MASK) #define PXP_PS_CTRL_TOG_RSVD1_MASK (0xFFFFF000U) #define PXP_PS_CTRL_TOG_RSVD1_SHIFT (12U) #define PXP_PS_CTRL_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_TOG_RSVD1_SHIFT)) & PXP_PS_CTRL_TOG_RSVD1_MASK) +/*! @} */ /*! @name PS_BUF - PS Input Buffer Address */ +/*! @{ */ #define PXP_PS_BUF_ADDR_MASK (0xFFFFFFFFU) #define PXP_PS_BUF_ADDR_SHIFT (0U) #define PXP_PS_BUF_ADDR(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_BUF_ADDR_SHIFT)) & PXP_PS_BUF_ADDR_MASK) +/*! @} */ /*! @name PS_UBUF - PS U/Cb or 2 Plane UV Input Buffer Address */ +/*! @{ */ #define PXP_PS_UBUF_ADDR_MASK (0xFFFFFFFFU) #define PXP_PS_UBUF_ADDR_SHIFT (0U) #define PXP_PS_UBUF_ADDR(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_UBUF_ADDR_SHIFT)) & PXP_PS_UBUF_ADDR_MASK) +/*! @} */ /*! @name PS_VBUF - PS V/Cr Input Buffer Address */ +/*! @{ */ #define PXP_PS_VBUF_ADDR_MASK (0xFFFFFFFFU) #define PXP_PS_VBUF_ADDR_SHIFT (0U) #define PXP_PS_VBUF_ADDR(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_VBUF_ADDR_SHIFT)) & PXP_PS_VBUF_ADDR_MASK) +/*! @} */ /*! @name PS_PITCH - Processed Surface Pitch */ +/*! @{ */ #define PXP_PS_PITCH_PITCH_MASK (0xFFFFU) #define PXP_PS_PITCH_PITCH_SHIFT (0U) #define PXP_PS_PITCH_PITCH(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_PITCH_PITCH_SHIFT)) & PXP_PS_PITCH_PITCH_MASK) #define PXP_PS_PITCH_RSVD_MASK (0xFFFF0000U) #define PXP_PS_PITCH_RSVD_SHIFT (16U) #define PXP_PS_PITCH_RSVD(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_PITCH_RSVD_SHIFT)) & PXP_PS_PITCH_RSVD_MASK) +/*! @} */ /*! @name PS_BACKGROUND - PS Background Color */ +/*! @{ */ #define PXP_PS_BACKGROUND_COLOR_MASK (0xFFFFFFU) #define PXP_PS_BACKGROUND_COLOR_SHIFT (0U) #define PXP_PS_BACKGROUND_COLOR(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_BACKGROUND_COLOR_SHIFT)) & PXP_PS_BACKGROUND_COLOR_MASK) #define PXP_PS_BACKGROUND_RSVD_MASK (0xFF000000U) #define PXP_PS_BACKGROUND_RSVD_SHIFT (24U) #define PXP_PS_BACKGROUND_RSVD(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_BACKGROUND_RSVD_SHIFT)) & PXP_PS_BACKGROUND_RSVD_MASK) +/*! @} */ /*! @name PS_SCALE - PS Scale Factor Register */ +/*! @{ */ #define PXP_PS_SCALE_XSCALE_MASK (0x7FFFU) #define PXP_PS_SCALE_XSCALE_SHIFT (0U) #define PXP_PS_SCALE_XSCALE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_SCALE_XSCALE_SHIFT)) & PXP_PS_SCALE_XSCALE_MASK) @@ -18769,8 +30350,10 @@ typedef struct { #define PXP_PS_SCALE_RSVD2_MASK (0x80000000U) #define PXP_PS_SCALE_RSVD2_SHIFT (31U) #define PXP_PS_SCALE_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_SCALE_RSVD2_SHIFT)) & PXP_PS_SCALE_RSVD2_MASK) +/*! @} */ /*! @name PS_OFFSET - PS Scale Offset Register */ +/*! @{ */ #define PXP_PS_OFFSET_XOFFSET_MASK (0xFFFU) #define PXP_PS_OFFSET_XOFFSET_SHIFT (0U) #define PXP_PS_OFFSET_XOFFSET(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_OFFSET_XOFFSET_SHIFT)) & PXP_PS_OFFSET_XOFFSET_MASK) @@ -18783,41 +30366,76 @@ typedef struct { #define PXP_PS_OFFSET_RSVD2_MASK (0xF0000000U) #define PXP_PS_OFFSET_RSVD2_SHIFT (28U) #define PXP_PS_OFFSET_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_OFFSET_RSVD2_SHIFT)) & PXP_PS_OFFSET_RSVD2_MASK) +/*! @} */ /*! @name PS_CLRKEYLOW - PS Color Key Low */ +/*! @{ */ #define PXP_PS_CLRKEYLOW_PIXEL_MASK (0xFFFFFFU) #define PXP_PS_CLRKEYLOW_PIXEL_SHIFT (0U) #define PXP_PS_CLRKEYLOW_PIXEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CLRKEYLOW_PIXEL_SHIFT)) & PXP_PS_CLRKEYLOW_PIXEL_MASK) #define PXP_PS_CLRKEYLOW_RSVD1_MASK (0xFF000000U) #define PXP_PS_CLRKEYLOW_RSVD1_SHIFT (24U) #define PXP_PS_CLRKEYLOW_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CLRKEYLOW_RSVD1_SHIFT)) & PXP_PS_CLRKEYLOW_RSVD1_MASK) +/*! @} */ /*! @name PS_CLRKEYHIGH - PS Color Key High */ +/*! @{ */ #define PXP_PS_CLRKEYHIGH_PIXEL_MASK (0xFFFFFFU) #define PXP_PS_CLRKEYHIGH_PIXEL_SHIFT (0U) #define PXP_PS_CLRKEYHIGH_PIXEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CLRKEYHIGH_PIXEL_SHIFT)) & PXP_PS_CLRKEYHIGH_PIXEL_MASK) #define PXP_PS_CLRKEYHIGH_RSVD1_MASK (0xFF000000U) #define PXP_PS_CLRKEYHIGH_RSVD1_SHIFT (24U) #define PXP_PS_CLRKEYHIGH_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CLRKEYHIGH_RSVD1_SHIFT)) & PXP_PS_CLRKEYHIGH_RSVD1_MASK) +/*! @} */ /*! @name AS_CTRL - Alpha Surface Control */ +/*! @{ */ #define PXP_AS_CTRL_RSVD0_MASK (0x1U) #define PXP_AS_CTRL_RSVD0_SHIFT (0U) #define PXP_AS_CTRL_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CTRL_RSVD0_SHIFT)) & PXP_AS_CTRL_RSVD0_MASK) #define PXP_AS_CTRL_ALPHA_CTRL_MASK (0x6U) #define PXP_AS_CTRL_ALPHA_CTRL_SHIFT (1U) +/*! ALPHA_CTRL + * 0b00..Indicates that the AS pixel alpha value will be used to blend the AS with PS. The ALPHA field is ignored. + * 0b01..Indicates that the value in the ALPHA field should be used instead of the alpha values present in the input pixels. + * 0b10..Indicates that the value in the ALPHA field should be used to scale all pixel alpha values. Each pixel alpha is multiplied by the value in the ALPHA field. + * 0b11..Enable ROPs. The ROP field indicates an operation to be performed on the alpha surface and PS pixels. + */ #define PXP_AS_CTRL_ALPHA_CTRL(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CTRL_ALPHA_CTRL_SHIFT)) & PXP_AS_CTRL_ALPHA_CTRL_MASK) #define PXP_AS_CTRL_ENABLE_COLORKEY_MASK (0x8U) #define PXP_AS_CTRL_ENABLE_COLORKEY_SHIFT (3U) #define PXP_AS_CTRL_ENABLE_COLORKEY(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CTRL_ENABLE_COLORKEY_SHIFT)) & PXP_AS_CTRL_ENABLE_COLORKEY_MASK) #define PXP_AS_CTRL_FORMAT_MASK (0xF0U) #define PXP_AS_CTRL_FORMAT_SHIFT (4U) +/*! FORMAT + * 0b0000..32-bit pixels with alpha + * 0b0100..32-bit pixels without alpha (unpacked 24-bit format) + * 0b1000..16-bit pixels with alpha + * 0b1001..16-bit pixels with alpha + * 0b1100..16-bit pixels without alpha + * 0b1101..16-bit pixels without alpha + * 0b1110..16-bit pixels without alpha + */ #define PXP_AS_CTRL_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CTRL_FORMAT_SHIFT)) & PXP_AS_CTRL_FORMAT_MASK) #define PXP_AS_CTRL_ALPHA_MASK (0xFF00U) #define PXP_AS_CTRL_ALPHA_SHIFT (8U) #define PXP_AS_CTRL_ALPHA(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CTRL_ALPHA_SHIFT)) & PXP_AS_CTRL_ALPHA_MASK) #define PXP_AS_CTRL_ROP_MASK (0xF0000U) #define PXP_AS_CTRL_ROP_SHIFT (16U) +/*! ROP + * 0b0000..AS AND PS + * 0b0001..nAS AND PS + * 0b0010..AS AND nPS + * 0b0011..AS OR PS + * 0b0100..nAS OR PS + * 0b0101..AS OR nPS + * 0b0110..nAS + * 0b0111..nPS + * 0b1000..AS NAND PS + * 0b1001..AS NOR PS + * 0b1010..AS XOR PS + * 0b1011..AS XNOR PS + */ #define PXP_AS_CTRL_ROP(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CTRL_ROP_SHIFT)) & PXP_AS_CTRL_ROP_MASK) #define PXP_AS_CTRL_ALPHA_INVERT_MASK (0x100000U) #define PXP_AS_CTRL_ALPHA_INVERT_SHIFT (20U) @@ -18825,37 +30443,47 @@ typedef struct { #define PXP_AS_CTRL_RSVD1_MASK (0xFFE00000U) #define PXP_AS_CTRL_RSVD1_SHIFT (21U) #define PXP_AS_CTRL_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CTRL_RSVD1_SHIFT)) & PXP_AS_CTRL_RSVD1_MASK) +/*! @} */ /*! @name AS_BUF - Alpha Surface Buffer Pointer */ +/*! @{ */ #define PXP_AS_BUF_ADDR_MASK (0xFFFFFFFFU) #define PXP_AS_BUF_ADDR_SHIFT (0U) #define PXP_AS_BUF_ADDR(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_BUF_ADDR_SHIFT)) & PXP_AS_BUF_ADDR_MASK) +/*! @} */ /*! @name AS_PITCH - Alpha Surface Pitch */ +/*! @{ */ #define PXP_AS_PITCH_PITCH_MASK (0xFFFFU) #define PXP_AS_PITCH_PITCH_SHIFT (0U) #define PXP_AS_PITCH_PITCH(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_PITCH_PITCH_SHIFT)) & PXP_AS_PITCH_PITCH_MASK) #define PXP_AS_PITCH_RSVD_MASK (0xFFFF0000U) #define PXP_AS_PITCH_RSVD_SHIFT (16U) #define PXP_AS_PITCH_RSVD(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_PITCH_RSVD_SHIFT)) & PXP_AS_PITCH_RSVD_MASK) +/*! @} */ /*! @name AS_CLRKEYLOW - Overlay Color Key Low */ +/*! @{ */ #define PXP_AS_CLRKEYLOW_PIXEL_MASK (0xFFFFFFU) #define PXP_AS_CLRKEYLOW_PIXEL_SHIFT (0U) #define PXP_AS_CLRKEYLOW_PIXEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CLRKEYLOW_PIXEL_SHIFT)) & PXP_AS_CLRKEYLOW_PIXEL_MASK) #define PXP_AS_CLRKEYLOW_RSVD1_MASK (0xFF000000U) #define PXP_AS_CLRKEYLOW_RSVD1_SHIFT (24U) #define PXP_AS_CLRKEYLOW_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CLRKEYLOW_RSVD1_SHIFT)) & PXP_AS_CLRKEYLOW_RSVD1_MASK) +/*! @} */ /*! @name AS_CLRKEYHIGH - Overlay Color Key High */ +/*! @{ */ #define PXP_AS_CLRKEYHIGH_PIXEL_MASK (0xFFFFFFU) #define PXP_AS_CLRKEYHIGH_PIXEL_SHIFT (0U) #define PXP_AS_CLRKEYHIGH_PIXEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CLRKEYHIGH_PIXEL_SHIFT)) & PXP_AS_CLRKEYHIGH_PIXEL_MASK) #define PXP_AS_CLRKEYHIGH_RSVD1_MASK (0xFF000000U) #define PXP_AS_CLRKEYHIGH_RSVD1_SHIFT (24U) #define PXP_AS_CLRKEYHIGH_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CLRKEYHIGH_RSVD1_SHIFT)) & PXP_AS_CLRKEYHIGH_RSVD1_MASK) +/*! @} */ /*! @name CSC1_COEF0 - Color Space Conversion Coefficient Register 0 */ +/*! @{ */ #define PXP_CSC1_COEF0_Y_OFFSET_MASK (0x1FFU) #define PXP_CSC1_COEF0_Y_OFFSET_SHIFT (0U) #define PXP_CSC1_COEF0_Y_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF0_Y_OFFSET_SHIFT)) & PXP_CSC1_COEF0_Y_OFFSET_MASK) @@ -18874,8 +30502,10 @@ typedef struct { #define PXP_CSC1_COEF0_YCBCR_MODE_MASK (0x80000000U) #define PXP_CSC1_COEF0_YCBCR_MODE_SHIFT (31U) #define PXP_CSC1_COEF0_YCBCR_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF0_YCBCR_MODE_SHIFT)) & PXP_CSC1_COEF0_YCBCR_MODE_MASK) +/*! @} */ /*! @name CSC1_COEF1 - Color Space Conversion Coefficient Register 1 */ +/*! @{ */ #define PXP_CSC1_COEF1_C4_MASK (0x7FFU) #define PXP_CSC1_COEF1_C4_SHIFT (0U) #define PXP_CSC1_COEF1_C4(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF1_C4_SHIFT)) & PXP_CSC1_COEF1_C4_MASK) @@ -18888,8 +30518,10 @@ typedef struct { #define PXP_CSC1_COEF1_RSVD1_MASK (0xF8000000U) #define PXP_CSC1_COEF1_RSVD1_SHIFT (27U) #define PXP_CSC1_COEF1_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF1_RSVD1_SHIFT)) & PXP_CSC1_COEF1_RSVD1_MASK) +/*! @} */ /*! @name CSC1_COEF2 - Color Space Conversion Coefficient Register 2 */ +/*! @{ */ #define PXP_CSC1_COEF2_C3_MASK (0x7FFU) #define PXP_CSC1_COEF2_C3_SHIFT (0U) #define PXP_CSC1_COEF2_C3(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF2_C3_SHIFT)) & PXP_CSC1_COEF2_C3_MASK) @@ -18902,16 +30534,26 @@ typedef struct { #define PXP_CSC1_COEF2_RSVD1_MASK (0xF8000000U) #define PXP_CSC1_COEF2_RSVD1_SHIFT (27U) #define PXP_CSC1_COEF2_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF2_RSVD1_SHIFT)) & PXP_CSC1_COEF2_RSVD1_MASK) +/*! @} */ /*! @name POWER - PXP Power Control Register */ +/*! @{ */ #define PXP_POWER_ROT_MEM_LP_STATE_MASK (0xE00U) #define PXP_POWER_ROT_MEM_LP_STATE_SHIFT (9U) +/*! ROT_MEM_LP_STATE + * 0b000..Memory is not in low power state. + * 0b001..Light Sleep Mode. Low leakage mode, maintain memory contents. + * 0b010..Deep Sleep Mode. Low leakage mode, maintain memory contents. + * 0b100..Shut Down Mode. Shut Down periphery and core, no memory retention. + */ #define PXP_POWER_ROT_MEM_LP_STATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_POWER_ROT_MEM_LP_STATE_SHIFT)) & PXP_POWER_ROT_MEM_LP_STATE_MASK) #define PXP_POWER_CTRL_MASK (0xFFFFF000U) #define PXP_POWER_CTRL_SHIFT (12U) #define PXP_POWER_CTRL(x) (((uint32_t)(((uint32_t)(x)) << PXP_POWER_CTRL_SHIFT)) & PXP_POWER_CTRL_MASK) +/*! @} */ /*! @name NEXT - Next Frame Pointer */ +/*! @{ */ #define PXP_NEXT_ENABLED_MASK (0x1U) #define PXP_NEXT_ENABLED_SHIFT (0U) #define PXP_NEXT_ENABLED(x) (((uint32_t)(((uint32_t)(x)) << PXP_NEXT_ENABLED_SHIFT)) & PXP_NEXT_ENABLED_MASK) @@ -18921,8 +30563,10 @@ typedef struct { #define PXP_NEXT_POINTER_MASK (0xFFFFFFFCU) #define PXP_NEXT_POINTER_SHIFT (2U) #define PXP_NEXT_POINTER(x) (((uint32_t)(((uint32_t)(x)) << PXP_NEXT_POINTER_SHIFT)) & PXP_NEXT_POINTER_MASK) +/*! @} */ /*! @name PORTER_DUFF_CTRL - PXP Alpha Engine A Control Register. */ +/*! @{ */ #define PXP_PORTER_DUFF_CTRL_POTER_DUFF_ENABLE_MASK (0x1U) #define PXP_PORTER_DUFF_CTRL_POTER_DUFF_ENABLE_SHIFT (0U) #define PXP_PORTER_DUFF_CTRL_POTER_DUFF_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_POTER_DUFF_ENABLE_SHIFT)) & PXP_PORTER_DUFF_CTRL_POTER_DUFF_ENABLE_MASK) @@ -18956,6 +30600,7 @@ typedef struct { #define PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_MASK (0xFF000000U) #define PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_SHIFT (24U) #define PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_SHIFT)) & PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_MASK) +/*! @} */ /*! @@ -19011,44 +30656,79 @@ typedef struct { */ /*! @name ROMPATCHD - ROMC Data Registers */ +/*! @{ */ #define ROMC_ROMPATCHD_DATAX_MASK (0xFFFFFFFFU) #define ROMC_ROMPATCHD_DATAX_SHIFT (0U) #define ROMC_ROMPATCHD_DATAX(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHD_DATAX_SHIFT)) & ROMC_ROMPATCHD_DATAX_MASK) +/*! @} */ /* The count of ROMC_ROMPATCHD */ #define ROMC_ROMPATCHD_COUNT (8U) /*! @name ROMPATCHCNTL - ROMC Control Register */ +/*! @{ */ #define ROMC_ROMPATCHCNTL_DATAFIX_MASK (0xFFU) #define ROMC_ROMPATCHCNTL_DATAFIX_SHIFT (0U) +/*! DATAFIX + * 0b00000000..Address comparator triggers a opcode patch + * 0b00000001..Address comparator triggers a data fix + */ #define ROMC_ROMPATCHCNTL_DATAFIX(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHCNTL_DATAFIX_SHIFT)) & ROMC_ROMPATCHCNTL_DATAFIX_MASK) #define ROMC_ROMPATCHCNTL_DIS_MASK (0x20000000U) #define ROMC_ROMPATCHCNTL_DIS_SHIFT (29U) +/*! DIS + * 0b0..Does not affect any ROMC functions (default) + * 0b1..Disable all ROMC functions: data fixing, and opcode patching + */ #define ROMC_ROMPATCHCNTL_DIS(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHCNTL_DIS_SHIFT)) & ROMC_ROMPATCHCNTL_DIS_MASK) +/*! @} */ /*! @name ROMPATCHENL - ROMC Enable Register Low */ +/*! @{ */ #define ROMC_ROMPATCHENL_ENABLE_MASK (0xFFFFU) #define ROMC_ROMPATCHENL_ENABLE_SHIFT (0U) +/*! ENABLE + * 0b0000000000000000..Address comparator disabled + * 0b0000000000000001..Address comparator enabled, ROMC will trigger a opcode patch or data fix event upon matching of the associated address + */ #define ROMC_ROMPATCHENL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHENL_ENABLE_SHIFT)) & ROMC_ROMPATCHENL_ENABLE_MASK) +/*! @} */ /*! @name ROMPATCHA - ROMC Address Registers */ +/*! @{ */ #define ROMC_ROMPATCHA_THUMBX_MASK (0x1U) #define ROMC_ROMPATCHA_THUMBX_SHIFT (0U) +/*! THUMBX + * 0b0..Arm patch + * 0b1..THUMB patch (ignore if data fix) + */ #define ROMC_ROMPATCHA_THUMBX(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHA_THUMBX_SHIFT)) & ROMC_ROMPATCHA_THUMBX_MASK) #define ROMC_ROMPATCHA_ADDRX_MASK (0x7FFFFEU) #define ROMC_ROMPATCHA_ADDRX_SHIFT (1U) #define ROMC_ROMPATCHA_ADDRX(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHA_ADDRX_SHIFT)) & ROMC_ROMPATCHA_ADDRX_MASK) +/*! @} */ /* The count of ROMC_ROMPATCHA */ #define ROMC_ROMPATCHA_COUNT (16U) /*! @name ROMPATCHSR - ROMC Status Register */ +/*! @{ */ #define ROMC_ROMPATCHSR_SOURCE_MASK (0x3FU) #define ROMC_ROMPATCHSR_SOURCE_SHIFT (0U) +/*! SOURCE + * 0b000000..Address Comparator 0 matched + * 0b000001..Address Comparator 1 matched + * 0b001111..Address Comparator 15 matched + */ #define ROMC_ROMPATCHSR_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHSR_SOURCE_SHIFT)) & ROMC_ROMPATCHSR_SOURCE_MASK) #define ROMC_ROMPATCHSR_SW_MASK (0x20000U) #define ROMC_ROMPATCHSR_SW_SHIFT (17U) +/*! SW + * 0b0..no event or comparator collisions + * 0b1..a collision has occurred + */ #define ROMC_ROMPATCHSR_SW(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHSR_SW_SHIFT)) & ROMC_ROMPATCHSR_SW_MASK) +/*! @} */ /*! @@ -19098,72 +30778,140 @@ typedef struct { */ /*! @name CS - Watchdog Control and Status Register */ +/*! @{ */ #define RTWDOG_CS_STOP_MASK (0x1U) #define RTWDOG_CS_STOP_SHIFT (0U) +/*! STOP - Stop Enable + * 0b0..Watchdog disabled in chip stop mode. + * 0b1..Watchdog enabled in chip stop mode. + */ #define RTWDOG_CS_STOP(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_STOP_SHIFT)) & RTWDOG_CS_STOP_MASK) #define RTWDOG_CS_WAIT_MASK (0x2U) #define RTWDOG_CS_WAIT_SHIFT (1U) +/*! WAIT - Wait Enable + * 0b0..Watchdog disabled in chip wait mode. + * 0b1..Watchdog enabled in chip wait mode. + */ #define RTWDOG_CS_WAIT(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_WAIT_SHIFT)) & RTWDOG_CS_WAIT_MASK) #define RTWDOG_CS_DBG_MASK (0x4U) #define RTWDOG_CS_DBG_SHIFT (2U) +/*! DBG - Debug Enable + * 0b0..Watchdog disabled in chip debug mode. + * 0b1..Watchdog enabled in chip debug mode. + */ #define RTWDOG_CS_DBG(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_DBG_SHIFT)) & RTWDOG_CS_DBG_MASK) #define RTWDOG_CS_TST_MASK (0x18U) #define RTWDOG_CS_TST_SHIFT (3U) +/*! TST - Watchdog Test + * 0b00..Watchdog test mode disabled. + * 0b01..Watchdog user mode enabled. (Watchdog test mode disabled.) After testing the watchdog, software should use this setting to indicate that the watchdog is functioning normally in user mode. + * 0b10..Watchdog test mode enabled, only the low byte is used. CNT[CNTLOW] is compared with TOVAL[TOVALLOW]. + * 0b11..Watchdog test mode enabled, only the high byte is used. CNT[CNTHIGH] is compared with TOVAL[TOVALHIGH]. + */ #define RTWDOG_CS_TST(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_TST_SHIFT)) & RTWDOG_CS_TST_MASK) #define RTWDOG_CS_UPDATE_MASK (0x20U) #define RTWDOG_CS_UPDATE_SHIFT (5U) +/*! UPDATE - Allow updates + * 0b0..Updates not allowed. After the initial configuration, the watchdog cannot be later modified without forcing a reset. + * 0b1..Updates allowed. Software can modify the watchdog configuration registers within 128 bus clocks after performing the unlock write sequence. + */ #define RTWDOG_CS_UPDATE(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_UPDATE_SHIFT)) & RTWDOG_CS_UPDATE_MASK) #define RTWDOG_CS_INT_MASK (0x40U) #define RTWDOG_CS_INT_SHIFT (6U) +/*! INT - Watchdog Interrupt + * 0b0..Watchdog interrupts are disabled. Watchdog resets are not delayed. + * 0b1..Watchdog interrupts are enabled. Watchdog resets are delayed by 128 bus clocks from the interrupt vector fetch. + */ #define RTWDOG_CS_INT(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_INT_SHIFT)) & RTWDOG_CS_INT_MASK) #define RTWDOG_CS_EN_MASK (0x80U) #define RTWDOG_CS_EN_SHIFT (7U) +/*! EN - Watchdog Enable + * 0b0..Watchdog disabled. + * 0b1..Watchdog enabled. + */ #define RTWDOG_CS_EN(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_EN_SHIFT)) & RTWDOG_CS_EN_MASK) #define RTWDOG_CS_CLK_MASK (0x300U) #define RTWDOG_CS_CLK_SHIFT (8U) +/*! CLK - Watchdog Clock + * 0b00..Bus clock + * 0b01..LPO clock + * 0b10..INTCLK (internal clock) + * 0b11..ERCLK (external reference clock) + */ #define RTWDOG_CS_CLK(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_CLK_SHIFT)) & RTWDOG_CS_CLK_MASK) #define RTWDOG_CS_RCS_MASK (0x400U) #define RTWDOG_CS_RCS_SHIFT (10U) +/*! RCS - Reconfiguration Success + * 0b0..Reconfiguring WDOG. + * 0b1..Reconfiguration is successful. + */ #define RTWDOG_CS_RCS(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_RCS_SHIFT)) & RTWDOG_CS_RCS_MASK) #define RTWDOG_CS_ULK_MASK (0x800U) #define RTWDOG_CS_ULK_SHIFT (11U) +/*! ULK - Unlock status + * 0b0..WDOG is locked. + * 0b1..WDOG is unlocked. + */ #define RTWDOG_CS_ULK(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_ULK_SHIFT)) & RTWDOG_CS_ULK_MASK) #define RTWDOG_CS_PRES_MASK (0x1000U) #define RTWDOG_CS_PRES_SHIFT (12U) +/*! PRES - Watchdog prescaler + * 0b0..256 prescaler disabled. + * 0b1..256 prescaler enabled. + */ #define RTWDOG_CS_PRES(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_PRES_SHIFT)) & RTWDOG_CS_PRES_MASK) #define RTWDOG_CS_CMD32EN_MASK (0x2000U) #define RTWDOG_CS_CMD32EN_SHIFT (13U) +/*! CMD32EN - Enables or disables WDOG support for 32-bit (otherwise 16-bit or 8-bit) refresh/unlock command write words + * 0b0..Disables support for 32-bit refresh/unlock command write words. Only 16-bit or 8-bit is supported. + * 0b1..Enables support for 32-bit refresh/unlock command write words. 16-bit or 8-bit is NOT supported. + */ #define RTWDOG_CS_CMD32EN(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_CMD32EN_SHIFT)) & RTWDOG_CS_CMD32EN_MASK) #define RTWDOG_CS_FLG_MASK (0x4000U) #define RTWDOG_CS_FLG_SHIFT (14U) +/*! FLG - Watchdog Interrupt Flag + * 0b0..No interrupt occurred. + * 0b1..An interrupt occurred. + */ #define RTWDOG_CS_FLG(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_FLG_SHIFT)) & RTWDOG_CS_FLG_MASK) #define RTWDOG_CS_WIN_MASK (0x8000U) #define RTWDOG_CS_WIN_SHIFT (15U) +/*! WIN - Watchdog Window + * 0b0..Window mode disabled. + * 0b1..Window mode enabled. + */ #define RTWDOG_CS_WIN(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_WIN_SHIFT)) & RTWDOG_CS_WIN_MASK) +/*! @} */ /*! @name CNT - Watchdog Counter Register */ +/*! @{ */ #define RTWDOG_CNT_CNTLOW_MASK (0xFFU) #define RTWDOG_CNT_CNTLOW_SHIFT (0U) #define RTWDOG_CNT_CNTLOW(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CNT_CNTLOW_SHIFT)) & RTWDOG_CNT_CNTLOW_MASK) #define RTWDOG_CNT_CNTHIGH_MASK (0xFF00U) #define RTWDOG_CNT_CNTHIGH_SHIFT (8U) #define RTWDOG_CNT_CNTHIGH(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CNT_CNTHIGH_SHIFT)) & RTWDOG_CNT_CNTHIGH_MASK) +/*! @} */ /*! @name TOVAL - Watchdog Timeout Value Register */ +/*! @{ */ #define RTWDOG_TOVAL_TOVALLOW_MASK (0xFFU) #define RTWDOG_TOVAL_TOVALLOW_SHIFT (0U) #define RTWDOG_TOVAL_TOVALLOW(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_TOVAL_TOVALLOW_SHIFT)) & RTWDOG_TOVAL_TOVALLOW_MASK) #define RTWDOG_TOVAL_TOVALHIGH_MASK (0xFF00U) #define RTWDOG_TOVAL_TOVALHIGH_SHIFT (8U) #define RTWDOG_TOVAL_TOVALHIGH(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_TOVAL_TOVALHIGH_SHIFT)) & RTWDOG_TOVAL_TOVALHIGH_MASK) +/*! @} */ /*! @name WIN - Watchdog Window Register */ +/*! @{ */ #define RTWDOG_WIN_WINLOW_MASK (0xFFU) #define RTWDOG_WIN_WINLOW_SHIFT (0U) #define RTWDOG_WIN_WINLOW(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_WIN_WINLOW_SHIFT)) & RTWDOG_WIN_WINLOW_MASK) #define RTWDOG_WIN_WINHIGH_MASK (0xFF00U) #define RTWDOG_WIN_WINHIGH_SHIFT (8U) #define RTWDOG_WIN_WINHIGH(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_WIN_WINHIGH_SHIFT)) & RTWDOG_WIN_WINHIGH_MASK) +/*! @} */ /*! @@ -19266,49 +31014,135 @@ typedef struct { */ /*! @name MCR - Module Control Register */ +/*! @{ */ #define SEMC_MCR_SWRST_MASK (0x1U) #define SEMC_MCR_SWRST_SHIFT (0U) #define SEMC_MCR_SWRST(x) (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_SWRST_SHIFT)) & SEMC_MCR_SWRST_MASK) #define SEMC_MCR_MDIS_MASK (0x2U) #define SEMC_MCR_MDIS_SHIFT (1U) +/*! MDIS - Module Disable + * 0b0..Module enabled + * 0b1..Module disabled. + */ #define SEMC_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_MDIS_SHIFT)) & SEMC_MCR_MDIS_MASK) #define SEMC_MCR_DQSMD_MASK (0x4U) #define SEMC_MCR_DQSMD_SHIFT (2U) +/*! DQSMD - DQS (read strobe) mode + * 0b0..Dummy read strobe loopbacked internally + * 0b1..Dummy read strobe loopbacked from DQS pad + */ #define SEMC_MCR_DQSMD(x) (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_DQSMD_SHIFT)) & SEMC_MCR_DQSMD_MASK) #define SEMC_MCR_WPOL0_MASK (0x40U) #define SEMC_MCR_WPOL0_SHIFT (6U) +/*! WPOL0 - WAIT/RDY# polarity for NOR/PSRAM + * 0b0..Low active + * 0b1..High active + */ #define SEMC_MCR_WPOL0(x) (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_WPOL0_SHIFT)) & SEMC_MCR_WPOL0_MASK) #define SEMC_MCR_WPOL1_MASK (0x80U) #define SEMC_MCR_WPOL1_SHIFT (7U) +/*! WPOL1 - WAIT/RDY# polarity for NAND + * 0b0..Low active + * 0b1..High active + */ #define SEMC_MCR_WPOL1(x) (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_WPOL1_SHIFT)) & SEMC_MCR_WPOL1_MASK) #define SEMC_MCR_CTO_MASK (0xFF0000U) #define SEMC_MCR_CTO_SHIFT (16U) #define SEMC_MCR_CTO(x) (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_CTO_SHIFT)) & SEMC_MCR_CTO_MASK) #define SEMC_MCR_BTO_MASK (0x1F000000U) #define SEMC_MCR_BTO_SHIFT (24U) +/*! BTO - Bus timeout cycles + * 0b00000..255*1 + * 0b00001-0b11110..255*2 - 255*2^30 + * 0b11111..255*2^31 + */ #define SEMC_MCR_BTO(x) (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_BTO_SHIFT)) & SEMC_MCR_BTO_MASK) +/*! @} */ /*! @name IOCR - IO Mux Control Register */ +/*! @{ */ #define SEMC_IOCR_MUX_A8_MASK (0x7U) #define SEMC_IOCR_MUX_A8_SHIFT (0U) +/*! MUX_A8 - SEMC_A8 output selection + * 0b000..SDRAM Address bit (A8) + * 0b001..NAND CE# + * 0b010..NOR CE# + * 0b011..PSRAM CE# + * 0b100..DBI CSX + * 0b101..SDRAM Address bit (A8) + * 0b110..SDRAM Address bit (A8) + * 0b111..SDRAM Address bit (A8) + */ #define SEMC_IOCR_MUX_A8(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_A8_SHIFT)) & SEMC_IOCR_MUX_A8_MASK) #define SEMC_IOCR_MUX_CSX0_MASK (0x38U) #define SEMC_IOCR_MUX_CSX0_SHIFT (3U) +/*! MUX_CSX0 - SEMC_CSX0 output selection + * 0b000..NOR/PSRAM Address bit 24 (A24) + * 0b001..SDRAM CS1 + * 0b010..SDRAM CS2 + * 0b011..SDRAM CS3 + * 0b100..NAND CE# + * 0b101..NOR CE# + * 0b110..PSRAM CE# + * 0b111..DBI CSX + */ #define SEMC_IOCR_MUX_CSX0(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_CSX0_SHIFT)) & SEMC_IOCR_MUX_CSX0_MASK) #define SEMC_IOCR_MUX_CSX1_MASK (0x1C0U) #define SEMC_IOCR_MUX_CSX1_SHIFT (6U) +/*! MUX_CSX1 - SEMC_CSX1 output selection + * 0b000..NOR/PSRAM Address bit 25 (A25) + * 0b001..SDRAM CS1 + * 0b010..SDRAM CS2 + * 0b011..SDRAM CS3 + * 0b100..NAND CE# + * 0b101..NOR CE# + * 0b110..PSRAM CE# + * 0b111..DBI CSX + */ #define SEMC_IOCR_MUX_CSX1(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_CSX1_SHIFT)) & SEMC_IOCR_MUX_CSX1_MASK) #define SEMC_IOCR_MUX_CSX2_MASK (0xE00U) #define SEMC_IOCR_MUX_CSX2_SHIFT (9U) +/*! MUX_CSX2 - SEMC_CSX2 output selection + * 0b000..NOR/PSRAM Address bit 26 (A26) + * 0b001..SDRAM CS1 + * 0b010..SDRAM CS2 + * 0b011..SDRAM CS3 + * 0b100..NAND CE# + * 0b101..NOR CE# + * 0b110..PSRAM CE# + * 0b111..DBI CSX + */ #define SEMC_IOCR_MUX_CSX2(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_CSX2_SHIFT)) & SEMC_IOCR_MUX_CSX2_MASK) #define SEMC_IOCR_MUX_CSX3_MASK (0x7000U) #define SEMC_IOCR_MUX_CSX3_SHIFT (12U) +/*! MUX_CSX3 - SEMC_CSX3 output selection + * 0b000..NOR/PSRAM Address bit 27 (A27) + * 0b001..SDRAM CS1 + * 0b010..SDRAM CS2 + * 0b011..SDRAM CS3 + * 0b100..NAND CE# + * 0b101..NOR CE# + * 0b110..PSRAM CE# + * 0b111..DBI CSX + */ #define SEMC_IOCR_MUX_CSX3(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_CSX3_SHIFT)) & SEMC_IOCR_MUX_CSX3_MASK) #define SEMC_IOCR_MUX_RDY_MASK (0x38000U) #define SEMC_IOCR_MUX_RDY_SHIFT (15U) +/*! MUX_RDY - SEMC_RDY function selection + * 0b000..NAND Ready/Wait# input + * 0b001..SDRAM CS1 + * 0b010..SDRAM CS2 + * 0b011..SDRAM CS3 + * 0b100..NOR CE# + * 0b101..PSRAM CE# + * 0b110..DBI CSX + * 0b111..NOR/PSRAM Address bit 27 + */ #define SEMC_IOCR_MUX_RDY(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_RDY_SHIFT)) & SEMC_IOCR_MUX_RDY_MASK) +/*! @} */ /*! @name BMCR0 - Master Bus (AXI) Control Register 0 */ +/*! @{ */ #define SEMC_BMCR0_WQOS_MASK (0xFU) #define SEMC_BMCR0_WQOS_SHIFT (0U) #define SEMC_BMCR0_WQOS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR0_WQOS_SHIFT)) & SEMC_BMCR0_WQOS_MASK) @@ -19321,8 +31155,10 @@ typedef struct { #define SEMC_BMCR0_WRWS_MASK (0xFF0000U) #define SEMC_BMCR0_WRWS_SHIFT (16U) #define SEMC_BMCR0_WRWS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR0_WRWS_SHIFT)) & SEMC_BMCR0_WRWS_MASK) +/*! @} */ /*! @name BMCR1 - Master Bus (AXI) Control Register 1 */ +/*! @{ */ #define SEMC_BMCR1_WQOS_MASK (0xFU) #define SEMC_BMCR1_WQOS_SHIFT (0U) #define SEMC_BMCR1_WQOS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR1_WQOS_SHIFT)) & SEMC_BMCR1_WQOS_MASK) @@ -19338,22 +31174,60 @@ typedef struct { #define SEMC_BMCR1_WBR_MASK (0xFF000000U) #define SEMC_BMCR1_WBR_SHIFT (24U) #define SEMC_BMCR1_WBR(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR1_WBR_SHIFT)) & SEMC_BMCR1_WBR_MASK) +/*! @} */ /*! @name BR - Base Register 0 (For SDRAM CS0 device)..Base Register 8 (For NAND device) */ +/*! @{ */ #define SEMC_BR_VLD_MASK (0x1U) #define SEMC_BR_VLD_SHIFT (0U) #define SEMC_BR_VLD(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BR_VLD_SHIFT)) & SEMC_BR_VLD_MASK) #define SEMC_BR_MS_MASK (0x3EU) #define SEMC_BR_MS_SHIFT (1U) +/*! MS - Memory size + * 0b00000..4KB + * 0b00001..8KB + * 0b00010..16KB + * 0b00011..32KB + * 0b00100..64KB + * 0b00101..128KB + * 0b00110..256KB + * 0b00111..512KB + * 0b01000..1MB + * 0b01001..2MB + * 0b01010..4MB + * 0b01011..8MB + * 0b01100..16MB + * 0b01101..32MB + * 0b01110..64MB + * 0b01111..128MB + * 0b10000..256MB + * 0b10001..512MB + * 0b10010..1GB + * 0b10011..2GB + * 0b10100..4GB + * 0b10101..4GB + * 0b10110..4GB + * 0b10111..4GB + * 0b11000..4GB + * 0b11001..4GB + * 0b11010..4GB + * 0b11011..4GB + * 0b11100..4GB + * 0b11101..4GB + * 0b11110..4GB + * 0b11111..4GB + */ #define SEMC_BR_MS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BR_MS_SHIFT)) & SEMC_BR_MS_MASK) #define SEMC_BR_BA_MASK (0xFFFFF000U) #define SEMC_BR_BA_SHIFT (12U) #define SEMC_BR_BA(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BR_BA_SHIFT)) & SEMC_BR_BA_MASK) +/*! @} */ /* The count of SEMC_BR */ #define SEMC_BR_COUNT (9U) /*! @name INTEN - Interrupt Enable Register */ +/*! @{ */ #define SEMC_INTEN_IPCMDDONEEN_MASK (0x1U) #define SEMC_INTEN_IPCMDDONEEN_SHIFT (0U) #define SEMC_INTEN_IPCMDDONEEN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_IPCMDDONEEN_SHIFT)) & SEMC_INTEN_IPCMDDONEEN_MASK) @@ -19368,12 +31242,22 @@ typedef struct { #define SEMC_INTEN_AXIBUSERREN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_AXIBUSERREN_SHIFT)) & SEMC_INTEN_AXIBUSERREN_MASK) #define SEMC_INTEN_NDPAGEENDEN_MASK (0x10U) #define SEMC_INTEN_NDPAGEENDEN_SHIFT (4U) +/*! NDPAGEENDEN - This bit enable/disable the NDPAGEEND interrupt generation. + * 0b0..Disable + * 0b1..Enable + */ #define SEMC_INTEN_NDPAGEENDEN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_NDPAGEENDEN_SHIFT)) & SEMC_INTEN_NDPAGEENDEN_MASK) #define SEMC_INTEN_NDNOPENDEN_MASK (0x20U) #define SEMC_INTEN_NDNOPENDEN_SHIFT (5U) +/*! NDNOPENDEN - This bit enable/disable the NDNOPEND interrupt generation. + * 0b0..Disable + * 0b1..Enable + */ #define SEMC_INTEN_NDNOPENDEN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_NDNOPENDEN_SHIFT)) & SEMC_INTEN_NDNOPENDEN_MASK) +/*! @} */ /*! @name INTR - Interrupt Enable Register */ +/*! @{ */ #define SEMC_INTR_IPCMDDONE_MASK (0x1U) #define SEMC_INTR_IPCMDDONE_SHIFT (0U) #define SEMC_INTR_IPCMDDONE(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_IPCMDDONE_SHIFT)) & SEMC_INTR_IPCMDDONE_MASK) @@ -19392,22 +31276,52 @@ typedef struct { #define SEMC_INTR_NDNOPEND_MASK (0x20U) #define SEMC_INTR_NDNOPEND_SHIFT (5U) #define SEMC_INTR_NDNOPEND(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_NDNOPEND_SHIFT)) & SEMC_INTR_NDNOPEND_MASK) +/*! @} */ /*! @name SDRAMCR0 - SDRAM control register 0 */ +/*! @{ */ #define SEMC_SDRAMCR0_PS_MASK (0x1U) #define SEMC_SDRAMCR0_PS_SHIFT (0U) +/*! PS - Port Size + * 0b0..8bit + * 0b1..16bit + */ #define SEMC_SDRAMCR0_PS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR0_PS_SHIFT)) & SEMC_SDRAMCR0_PS_MASK) #define SEMC_SDRAMCR0_BL_MASK (0x70U) #define SEMC_SDRAMCR0_BL_SHIFT (4U) +/*! BL - Burst Length + * 0b000..1 + * 0b001..2 + * 0b010..4 + * 0b011..8 + * 0b100..8 + * 0b101..8 + * 0b110..8 + * 0b111..8 + */ #define SEMC_SDRAMCR0_BL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR0_BL_SHIFT)) & SEMC_SDRAMCR0_BL_MASK) #define SEMC_SDRAMCR0_COL_MASK (0x300U) #define SEMC_SDRAMCR0_COL_SHIFT (8U) +/*! COL - Column address bit number + * 0b00..12 bit + * 0b01..11 bit + * 0b10..10 bit + * 0b11..9 bit + */ #define SEMC_SDRAMCR0_COL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR0_COL_SHIFT)) & SEMC_SDRAMCR0_COL_MASK) #define SEMC_SDRAMCR0_CL_MASK (0xC00U) #define SEMC_SDRAMCR0_CL_SHIFT (10U) +/*! CL - CAS Latency + * 0b00..1 + * 0b01..1 + * 0b10..2 + * 0b11..3 + */ #define SEMC_SDRAMCR0_CL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR0_CL_SHIFT)) & SEMC_SDRAMCR0_CL_MASK) +/*! @} */ /*! @name SDRAMCR1 - SDRAM control register 1 */ +/*! @{ */ #define SEMC_SDRAMCR1_PRE2ACT_MASK (0xFU) #define SEMC_SDRAMCR1_PRE2ACT_SHIFT (0U) #define SEMC_SDRAMCR1_PRE2ACT(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR1_PRE2ACT_SHIFT)) & SEMC_SDRAMCR1_PRE2ACT_MASK) @@ -19426,8 +31340,10 @@ typedef struct { #define SEMC_SDRAMCR1_ACT2PRE_MASK (0xF00000U) #define SEMC_SDRAMCR1_ACT2PRE_SHIFT (20U) #define SEMC_SDRAMCR1_ACT2PRE(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR1_ACT2PRE_SHIFT)) & SEMC_SDRAMCR1_ACT2PRE_MASK) +/*! @} */ /*! @name SDRAMCR2 - SDRAM control register 2 */ +/*! @{ */ #define SEMC_SDRAMCR2_SRRC_MASK (0xFFU) #define SEMC_SDRAMCR2_SRRC_SHIFT (0U) #define SEMC_SDRAMCR2_SRRC(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR2_SRRC_SHIFT)) & SEMC_SDRAMCR2_SRRC_MASK) @@ -19439,40 +31355,100 @@ typedef struct { #define SEMC_SDRAMCR2_ACT2ACT(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR2_ACT2ACT_SHIFT)) & SEMC_SDRAMCR2_ACT2ACT_MASK) #define SEMC_SDRAMCR2_ITO_MASK (0xFF000000U) #define SEMC_SDRAMCR2_ITO_SHIFT (24U) +/*! ITO - SDRAM Idle timeout + * 0b00000000..IDLE timeout period is 256*Prescale period. + * 0b00000001-0b11111111..IDLE timeout period is ITO*Prescale period. + */ #define SEMC_SDRAMCR2_ITO(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR2_ITO_SHIFT)) & SEMC_SDRAMCR2_ITO_MASK) +/*! @} */ /*! @name SDRAMCR3 - SDRAM control register 3 */ +/*! @{ */ #define SEMC_SDRAMCR3_REN_MASK (0x1U) #define SEMC_SDRAMCR3_REN_SHIFT (0U) #define SEMC_SDRAMCR3_REN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR3_REN_SHIFT)) & SEMC_SDRAMCR3_REN_MASK) #define SEMC_SDRAMCR3_REBL_MASK (0xEU) #define SEMC_SDRAMCR3_REBL_SHIFT (1U) +/*! REBL - Refresh burst length + * 0b000..1 + * 0b001..2 + * 0b010..3 + * 0b011..4 + * 0b100..5 + * 0b101..6 + * 0b110..7 + * 0b111..8 + */ #define SEMC_SDRAMCR3_REBL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR3_REBL_SHIFT)) & SEMC_SDRAMCR3_REBL_MASK) #define SEMC_SDRAMCR3_PRESCALE_MASK (0xFF00U) #define SEMC_SDRAMCR3_PRESCALE_SHIFT (8U) +/*! PRESCALE - Prescaler timer period + * 0b00000000..256*16 cycle + * 0b00000001-0b11111111..PRESCALE*16 cycle + */ #define SEMC_SDRAMCR3_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR3_PRESCALE_SHIFT)) & SEMC_SDRAMCR3_PRESCALE_MASK) #define SEMC_SDRAMCR3_RT_MASK (0xFF0000U) #define SEMC_SDRAMCR3_RT_SHIFT (16U) +/*! RT - Refresh timer period + * 0b00000000..256*Prescaler period + * 0b00000001-0b11111111..RT*Prescaler period + */ #define SEMC_SDRAMCR3_RT(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR3_RT_SHIFT)) & SEMC_SDRAMCR3_RT_MASK) #define SEMC_SDRAMCR3_UT_MASK (0xFF000000U) #define SEMC_SDRAMCR3_UT_SHIFT (24U) +/*! UT - Refresh urgent threshold + * 0b00000000..256*Prescaler period + * 0b00000001-0b11111111..UT*Prescaler period + */ #define SEMC_SDRAMCR3_UT(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR3_UT_SHIFT)) & SEMC_SDRAMCR3_UT_MASK) +/*! @} */ /*! @name NANDCR0 - NAND control register 0 */ +/*! @{ */ #define SEMC_NANDCR0_PS_MASK (0x1U) #define SEMC_NANDCR0_PS_SHIFT (0U) +/*! PS - Port Size + * 0b0..8bit + * 0b1..16bit + */ #define SEMC_NANDCR0_PS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR0_PS_SHIFT)) & SEMC_NANDCR0_PS_MASK) #define SEMC_NANDCR0_BL_MASK (0x70U) #define SEMC_NANDCR0_BL_SHIFT (4U) +/*! BL - Burst Length + * 0b000..1 + * 0b001..2 + * 0b010..4 + * 0b011..8 + * 0b100..16 + * 0b101..32 + * 0b110..64 + * 0b111..64 + */ #define SEMC_NANDCR0_BL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR0_BL_SHIFT)) & SEMC_NANDCR0_BL_MASK) #define SEMC_NANDCR0_EDO_MASK (0x80U) #define SEMC_NANDCR0_EDO_SHIFT (7U) +/*! EDO - EDO mode enabled + * 0b0..EDO mode disabled + * 0b1..EDO mode enabled + */ #define SEMC_NANDCR0_EDO(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR0_EDO_SHIFT)) & SEMC_NANDCR0_EDO_MASK) #define SEMC_NANDCR0_COL_MASK (0x700U) #define SEMC_NANDCR0_COL_SHIFT (8U) +/*! COL - Column address bit number + * 0b000..16 + * 0b001..15 + * 0b010..14 + * 0b011..13 + * 0b100..12 + * 0b101..11 + * 0b110..10 + * 0b111..9 + */ #define SEMC_NANDCR0_COL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR0_COL_SHIFT)) & SEMC_NANDCR0_COL_MASK) +/*! @} */ /*! @name NANDCR1 - NAND control register 1 */ +/*! @{ */ #define SEMC_NANDCR1_CES_MASK (0xFU) #define SEMC_NANDCR1_CES_SHIFT (0U) #define SEMC_NANDCR1_CES(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_CES_SHIFT)) & SEMC_NANDCR1_CES_MASK) @@ -19497,8 +31473,10 @@ typedef struct { #define SEMC_NANDCR1_CEITV_MASK (0xF0000000U) #define SEMC_NANDCR1_CEITV_SHIFT (28U) #define SEMC_NANDCR1_CEITV(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_CEITV_SHIFT)) & SEMC_NANDCR1_CEITV_MASK) +/*! @} */ /*! @name NANDCR2 - NAND control register 2 */ +/*! @{ */ #define SEMC_NANDCR2_TWHR_MASK (0x3FU) #define SEMC_NANDCR2_TWHR_SHIFT (0U) #define SEMC_NANDCR2_TWHR(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR2_TWHR_SHIFT)) & SEMC_NANDCR2_TWHR_MASK) @@ -19514,8 +31492,10 @@ typedef struct { #define SEMC_NANDCR2_TWB_MASK (0x3F000000U) #define SEMC_NANDCR2_TWB_SHIFT (24U) #define SEMC_NANDCR2_TWB(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR2_TWB_SHIFT)) & SEMC_NANDCR2_TWB_MASK) +/*! @} */ /*! @name NANDCR3 - NAND control register 3 */ +/*! @{ */ #define SEMC_NANDCR3_NDOPT1_MASK (0x1U) #define SEMC_NANDCR3_NDOPT1_SHIFT (0U) #define SEMC_NANDCR3_NDOPT1(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR3_NDOPT1_SHIFT)) & SEMC_NANDCR3_NDOPT1_MASK) @@ -19525,25 +31505,71 @@ typedef struct { #define SEMC_NANDCR3_NDOPT3_MASK (0x4U) #define SEMC_NANDCR3_NDOPT3_SHIFT (2U) #define SEMC_NANDCR3_NDOPT3(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR3_NDOPT3_SHIFT)) & SEMC_NANDCR3_NDOPT3_MASK) +/*! @} */ /*! @name NORCR0 - NOR control register 0 */ +/*! @{ */ #define SEMC_NORCR0_PS_MASK (0x1U) #define SEMC_NORCR0_PS_SHIFT (0U) +/*! PS - Port Size + * 0b0..8bit + * 0b1..16bit + */ #define SEMC_NORCR0_PS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_PS_SHIFT)) & SEMC_NORCR0_PS_MASK) #define SEMC_NORCR0_BL_MASK (0x70U) #define SEMC_NORCR0_BL_SHIFT (4U) +/*! BL - Burst Length + * 0b000..1 + * 0b001..2 + * 0b010..4 + * 0b011..8 + * 0b100..16 + * 0b101..32 + * 0b110..64 + * 0b111..64 + */ #define SEMC_NORCR0_BL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_BL_SHIFT)) & SEMC_NORCR0_BL_MASK) #define SEMC_NORCR0_AM_MASK (0x300U) #define SEMC_NORCR0_AM_SHIFT (8U) +/*! AM - Address Mode + * 0b00..Address/Data MUX mode + * 0b01..Advanced Address/Data MUX mode + * 0b10..Address/Data non-MUX mode + * 0b11..Address/Data non-MUX mode + */ #define SEMC_NORCR0_AM(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_AM_SHIFT)) & SEMC_NORCR0_AM_MASK) #define SEMC_NORCR0_ADVP_MASK (0x400U) #define SEMC_NORCR0_ADVP_SHIFT (10U) +/*! ADVP - ADV# polarity + * 0b0..ADV# is Low Active. In ASYNC mode, device sample address with ADV# rise edge; In SYNC mode, device sample address when ADV# is LOW. + * 0b1..ADV# is High Active. In ASYNC mode, device sample address with ADV# fall edge; In SYNC mode, device sample address when ADV# is HIGH. + */ #define SEMC_NORCR0_ADVP(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_ADVP_SHIFT)) & SEMC_NORCR0_ADVP_MASK) #define SEMC_NORCR0_COL_MASK (0xF000U) #define SEMC_NORCR0_COL_SHIFT (12U) +/*! COL - Column Address bit width + * 0b0000..12 Bits + * 0b0001..11 Bits + * 0b0010..10 Bits + * 0b0011..9 Bits + * 0b0100..8 Bits + * 0b0101..7 Bits + * 0b0110..6 Bits + * 0b0111..5 Bits + * 0b1000..4 Bits + * 0b1001..3 Bits + * 0b1010..2 Bits + * 0b1011..12 Bits + * 0b1100..12 Bits + * 0b1101..12 Bits + * 0b1110..12 Bits + * 0b1111..12 Bits + */ #define SEMC_NORCR0_COL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_COL_SHIFT)) & SEMC_NORCR0_COL_MASK) +/*! @} */ /*! @name NORCR1 - NOR control register 1 */ +/*! @{ */ #define SEMC_NORCR1_CES_MASK (0xFU) #define SEMC_NORCR1_CES_SHIFT (0U) #define SEMC_NORCR1_CES(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_CES_SHIFT)) & SEMC_NORCR1_CES_MASK) @@ -19568,8 +31594,10 @@ typedef struct { #define SEMC_NORCR1_REH_MASK (0xF0000000U) #define SEMC_NORCR1_REH_SHIFT (28U) #define SEMC_NORCR1_REH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_REH_SHIFT)) & SEMC_NORCR1_REH_MASK) +/*! @} */ /*! @name NORCR2 - NOR control register 2 */ +/*! @{ */ #define SEMC_NORCR2_WDS_MASK (0xFU) #define SEMC_NORCR2_WDS_SHIFT (0U) #define SEMC_NORCR2_WDS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_WDS_SHIFT)) & SEMC_NORCR2_WDS_MASK) @@ -19591,25 +31619,71 @@ typedef struct { #define SEMC_NORCR2_CEITV_MASK (0xF000000U) #define SEMC_NORCR2_CEITV_SHIFT (24U) #define SEMC_NORCR2_CEITV(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_CEITV_SHIFT)) & SEMC_NORCR2_CEITV_MASK) +/*! @} */ /*! @name SRAMCR0 - SRAM control register 0 */ +/*! @{ */ #define SEMC_SRAMCR0_PS_MASK (0x1U) #define SEMC_SRAMCR0_PS_SHIFT (0U) +/*! PS - Port Size + * 0b0..8bit + * 0b1..16bit + */ #define SEMC_SRAMCR0_PS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_PS_SHIFT)) & SEMC_SRAMCR0_PS_MASK) #define SEMC_SRAMCR0_BL_MASK (0x70U) #define SEMC_SRAMCR0_BL_SHIFT (4U) +/*! BL - Burst Length + * 0b000..1 + * 0b001..2 + * 0b010..4 + * 0b011..8 + * 0b100..16 + * 0b101..32 + * 0b110..64 + * 0b111..64 + */ #define SEMC_SRAMCR0_BL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_BL_SHIFT)) & SEMC_SRAMCR0_BL_MASK) #define SEMC_SRAMCR0_AM_MASK (0x300U) #define SEMC_SRAMCR0_AM_SHIFT (8U) +/*! AM - Address Mode + * 0b00..Address/Data MUX mode + * 0b01..Advanced Address/Data MUX mode + * 0b10..Address/Data non-MUX mode + * 0b11..Address/Data non-MUX mode + */ #define SEMC_SRAMCR0_AM(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_AM_SHIFT)) & SEMC_SRAMCR0_AM_MASK) #define SEMC_SRAMCR0_ADVP_MASK (0x400U) #define SEMC_SRAMCR0_ADVP_SHIFT (10U) +/*! ADVP - ADV# polarity + * 0b0..ADV# is Low Active. In ASYNC mode, device sample address with ADV# rise edge; In SYNC mode, device sample address when ADV# is LOW. + * 0b1..ADV# is High Active. In ASYNC mode, device sample address with ADV# fall edge; In SYNC mode, device sample address when ADV# is HIGH. + */ #define SEMC_SRAMCR0_ADVP(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_ADVP_SHIFT)) & SEMC_SRAMCR0_ADVP_MASK) #define SEMC_SRAMCR0_COL_MASK (0xF000U) #define SEMC_SRAMCR0_COL_SHIFT (12U) +/*! COL - Column Address bit width + * 0b0000..12 Bits + * 0b0001..11 Bits + * 0b0010..10 Bits + * 0b0011..9 Bits + * 0b0100..8 Bits + * 0b0101..7 Bits + * 0b0110..6 Bits + * 0b0111..5 Bits + * 0b1000..4 Bits + * 0b1001..3 Bits + * 0b1010..2 Bits + * 0b1011..12 Bits + * 0b1100..12 Bits + * 0b1101..12 Bits + * 0b1110..12 Bits + * 0b1111..12 Bits + */ #define SEMC_SRAMCR0_COL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_COL_SHIFT)) & SEMC_SRAMCR0_COL_MASK) +/*! @} */ /*! @name SRAMCR1 - SRAM control register 1 */ +/*! @{ */ #define SEMC_SRAMCR1_CES_MASK (0xFU) #define SEMC_SRAMCR1_CES_SHIFT (0U) #define SEMC_SRAMCR1_CES(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_CES_SHIFT)) & SEMC_SRAMCR1_CES_MASK) @@ -19634,8 +31708,10 @@ typedef struct { #define SEMC_SRAMCR1_REH_MASK (0xF0000000U) #define SEMC_SRAMCR1_REH_SHIFT (28U) #define SEMC_SRAMCR1_REH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_REH_SHIFT)) & SEMC_SRAMCR1_REH_MASK) +/*! @} */ /*! @name SRAMCR2 - SRAM control register 2 */ +/*! @{ */ #define SEMC_SRAMCR2_WDS_MASK (0xFU) #define SEMC_SRAMCR2_WDS_SHIFT (0U) #define SEMC_SRAMCR2_WDS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_WDS_SHIFT)) & SEMC_SRAMCR2_WDS_MASK) @@ -19657,19 +31733,55 @@ typedef struct { #define SEMC_SRAMCR2_CEITV_MASK (0xF000000U) #define SEMC_SRAMCR2_CEITV_SHIFT (24U) #define SEMC_SRAMCR2_CEITV(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_CEITV_SHIFT)) & SEMC_SRAMCR2_CEITV_MASK) +/*! @} */ /*! @name DBICR0 - DBI-B control register 0 */ +/*! @{ */ #define SEMC_DBICR0_PS_MASK (0x1U) #define SEMC_DBICR0_PS_SHIFT (0U) +/*! PS - Port Size + * 0b0..8bit + * 0b1..16bit + */ #define SEMC_DBICR0_PS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR0_PS_SHIFT)) & SEMC_DBICR0_PS_MASK) #define SEMC_DBICR0_BL_MASK (0x70U) #define SEMC_DBICR0_BL_SHIFT (4U) +/*! BL - Burst Length + * 0b000..1 + * 0b001..2 + * 0b010..4 + * 0b011..8 + * 0b100..16 + * 0b101..32 + * 0b110..64 + * 0b111..64 + */ #define SEMC_DBICR0_BL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR0_BL_SHIFT)) & SEMC_DBICR0_BL_MASK) #define SEMC_DBICR0_COL_MASK (0xF000U) #define SEMC_DBICR0_COL_SHIFT (12U) +/*! COL - Column Address bit width + * 0b0000..12 Bits + * 0b0001..11 Bits + * 0b0010..10 Bits + * 0b0011..9 Bits + * 0b0100..8 Bits + * 0b0101..7 Bits + * 0b0110..6 Bits + * 0b0111..5 Bits + * 0b1000..4 Bits + * 0b1001..3 Bits + * 0b1010..2 Bits + * 0b1011..12 Bits + * 0b1100..12 Bits + * 0b1101..12 Bits + * 0b1110..12 Bits + * 0b1111..12 Bits + */ #define SEMC_DBICR0_COL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR0_COL_SHIFT)) & SEMC_DBICR0_COL_MASK) +/*! @} */ /*! @name DBICR1 - DBI-B control register 1 */ +/*! @{ */ #define SEMC_DBICR1_CES_MASK (0xFU) #define SEMC_DBICR1_CES_SHIFT (0U) #define SEMC_DBICR1_CES(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_CES_SHIFT)) & SEMC_DBICR1_CES_MASK) @@ -19691,66 +31803,125 @@ typedef struct { #define SEMC_DBICR1_CEITV_MASK (0xF000000U) #define SEMC_DBICR1_CEITV_SHIFT (24U) #define SEMC_DBICR1_CEITV(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_CEITV_SHIFT)) & SEMC_DBICR1_CEITV_MASK) +#define SEMC_DBICR1_REL2_MASK (0x30000000U) +#define SEMC_DBICR1_REL2_SHIFT (28U) +#define SEMC_DBICR1_REL2(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_REL2_SHIFT)) & SEMC_DBICR1_REL2_MASK) +#define SEMC_DBICR1_REH2_MASK (0xC0000000U) +#define SEMC_DBICR1_REH2_SHIFT (30U) +#define SEMC_DBICR1_REH2(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_REH2_SHIFT)) & SEMC_DBICR1_REH2_MASK) +/*! @} */ /*! @name IPCR0 - IP Command control register 0 */ +/*! @{ */ #define SEMC_IPCR0_SA_MASK (0xFFFFFFFFU) #define SEMC_IPCR0_SA_SHIFT (0U) #define SEMC_IPCR0_SA(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR0_SA_SHIFT)) & SEMC_IPCR0_SA_MASK) +/*! @} */ /*! @name IPCR1 - IP Command control register 1 */ +/*! @{ */ #define SEMC_IPCR1_DATSZ_MASK (0x7U) #define SEMC_IPCR1_DATSZ_SHIFT (0U) +/*! DATSZ - Data Size in Byte + * 0b000..4 + * 0b001..1 + * 0b010..2 + * 0b011..3 + * 0b100..4 + * 0b101..4 + * 0b110..4 + * 0b111..4 + */ #define SEMC_IPCR1_DATSZ(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR1_DATSZ_SHIFT)) & SEMC_IPCR1_DATSZ_MASK) +/*! @} */ /*! @name IPCR2 - IP Command control register 2 */ +/*! @{ */ #define SEMC_IPCR2_BM0_MASK (0x1U) #define SEMC_IPCR2_BM0_SHIFT (0U) +/*! BM0 - Byte Mask for Byte 0 (IPTXD bit 7:0) + * 0b0..Byte Unmasked + * 0b1..Byte Masked + */ #define SEMC_IPCR2_BM0(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR2_BM0_SHIFT)) & SEMC_IPCR2_BM0_MASK) #define SEMC_IPCR2_BM1_MASK (0x2U) #define SEMC_IPCR2_BM1_SHIFT (1U) +/*! BM1 - Byte Mask for Byte 1 (IPTXD bit 15:8) + * 0b0..Byte Unmasked + * 0b1..Byte Masked + */ #define SEMC_IPCR2_BM1(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR2_BM1_SHIFT)) & SEMC_IPCR2_BM1_MASK) #define SEMC_IPCR2_BM2_MASK (0x4U) #define SEMC_IPCR2_BM2_SHIFT (2U) +/*! BM2 - Byte Mask for Byte 2 (IPTXD bit 23:16) + * 0b0..Byte Unmasked + * 0b1..Byte Masked + */ #define SEMC_IPCR2_BM2(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR2_BM2_SHIFT)) & SEMC_IPCR2_BM2_MASK) #define SEMC_IPCR2_BM3_MASK (0x8U) #define SEMC_IPCR2_BM3_SHIFT (3U) +/*! BM3 - Byte Mask for Byte 3 (IPTXD bit 31:24) + * 0b0..Byte Unmasked + * 0b1..Byte Masked + */ #define SEMC_IPCR2_BM3(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR2_BM3_SHIFT)) & SEMC_IPCR2_BM3_MASK) +/*! @} */ /*! @name IPCMD - IP Command register */ +/*! @{ */ #define SEMC_IPCMD_CMD_MASK (0xFFFFU) #define SEMC_IPCMD_CMD_SHIFT (0U) #define SEMC_IPCMD_CMD(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCMD_CMD_SHIFT)) & SEMC_IPCMD_CMD_MASK) #define SEMC_IPCMD_KEY_MASK (0xFFFF0000U) #define SEMC_IPCMD_KEY_SHIFT (16U) #define SEMC_IPCMD_KEY(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCMD_KEY_SHIFT)) & SEMC_IPCMD_KEY_MASK) +/*! @} */ /*! @name IPTXDAT - TX DATA register (for IP Command) */ +/*! @{ */ #define SEMC_IPTXDAT_DAT_MASK (0xFFFFFFFFU) #define SEMC_IPTXDAT_DAT_SHIFT (0U) #define SEMC_IPTXDAT_DAT(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPTXDAT_DAT_SHIFT)) & SEMC_IPTXDAT_DAT_MASK) +/*! @} */ /*! @name IPRXDAT - RX DATA register (for IP Command) */ +/*! @{ */ #define SEMC_IPRXDAT_DAT_MASK (0xFFFFFFFFU) #define SEMC_IPRXDAT_DAT_SHIFT (0U) #define SEMC_IPRXDAT_DAT(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPRXDAT_DAT_SHIFT)) & SEMC_IPRXDAT_DAT_MASK) +/*! @} */ /*! @name STS0 - Status register 0 */ +/*! @{ */ #define SEMC_STS0_IDLE_MASK (0x1U) #define SEMC_STS0_IDLE_SHIFT (0U) #define SEMC_STS0_IDLE(x) (((uint32_t)(((uint32_t)(x)) << SEMC_STS0_IDLE_SHIFT)) & SEMC_STS0_IDLE_MASK) #define SEMC_STS0_NARDY_MASK (0x2U) #define SEMC_STS0_NARDY_SHIFT (1U) +/*! NARDY - Indicating NAND device Ready/WAIT# pin level. + * 0b0..NAND device is not ready + * 0b1..NAND device is ready + */ #define SEMC_STS0_NARDY(x) (((uint32_t)(((uint32_t)(x)) << SEMC_STS0_NARDY_SHIFT)) & SEMC_STS0_NARDY_MASK) +/*! @} */ /*! @name STS2 - Status register 2 */ +/*! @{ */ #define SEMC_STS2_NDWRPEND_MASK (0x8U) #define SEMC_STS2_NDWRPEND_SHIFT (3U) +/*! NDWRPEND - This field indicating whether there is pending AXI command (write) to NAND device. + * 0b0..No pending + * 0b1..Pending + */ #define SEMC_STS2_NDWRPEND(x) (((uint32_t)(((uint32_t)(x)) << SEMC_STS2_NDWRPEND_SHIFT)) & SEMC_STS2_NDWRPEND_MASK) +/*! @} */ /*! @name STS12 - Status register 12 */ +/*! @{ */ #define SEMC_STS12_NDADDR_MASK (0xFFFFFFFFU) #define SEMC_STS12_NDADDR_SHIFT (0U) #define SEMC_STS12_NDADDR(x) (((uint32_t)(((uint32_t)(x)) << SEMC_STS12_NDADDR_SHIFT)) & SEMC_STS12_NDADDR_MASK) +/*! @} */ /*! @@ -19817,8 +31988,8 @@ typedef struct { uint8_t RESERVED_1[4]; __IO uint32_t LPGPR_ALIAS[4]; /**< SNVS_LP General Purpose Registers 0 .. 3, array offset: 0x90, array step: 0x4 */ uint8_t RESERVED_2[96]; - __IO uint32_t LPGPR[4]; /**< SNVS_LP General Purpose Registers 0 .. 3, array offset: 0x100, array step: 0x4 */ - uint8_t RESERVED_3[2792]; + __IO uint32_t LPGPR[8]; /**< SNVS_LP General Purpose Registers 0 .. 7, array offset: 0x100, array step: 0x4 */ + uint8_t RESERVED_3[2776]; __I uint32_t HPVIDR1; /**< SNVS_HP Version ID Register 1, offset: 0xBF8 */ __I uint32_t HPVIDR2; /**< SNVS_HP Version ID Register 2, offset: 0xBFC */ } SNVS_Type; @@ -19833,58 +32004,125 @@ typedef struct { */ /*! @name HPLR - SNVS_HP Lock Register */ +/*! @{ */ #define SNVS_HPLR_ZMK_WSL_MASK (0x1U) #define SNVS_HPLR_ZMK_WSL_SHIFT (0U) +/*! ZMK_WSL + * 0b0..Write access is allowed + * 0b1..Write access is not allowed + */ #define SNVS_HPLR_ZMK_WSL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_ZMK_WSL_SHIFT)) & SNVS_HPLR_ZMK_WSL_MASK) #define SNVS_HPLR_ZMK_RSL_MASK (0x2U) #define SNVS_HPLR_ZMK_RSL_SHIFT (1U) +/*! ZMK_RSL + * 0b0..Read access is allowed (only in software Programming mode) + * 0b1..Read access is not allowed + */ #define SNVS_HPLR_ZMK_RSL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_ZMK_RSL_SHIFT)) & SNVS_HPLR_ZMK_RSL_MASK) #define SNVS_HPLR_SRTC_SL_MASK (0x4U) #define SNVS_HPLR_SRTC_SL_SHIFT (2U) +/*! SRTC_SL + * 0b0..Write access is allowed + * 0b1..Write access is not allowed + */ #define SNVS_HPLR_SRTC_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_SRTC_SL_SHIFT)) & SNVS_HPLR_SRTC_SL_MASK) #define SNVS_HPLR_LPCALB_SL_MASK (0x8U) #define SNVS_HPLR_LPCALB_SL_SHIFT (3U) +/*! LPCALB_SL + * 0b0..Write access is allowed + * 0b1..Write access is not allowed + */ #define SNVS_HPLR_LPCALB_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_LPCALB_SL_SHIFT)) & SNVS_HPLR_LPCALB_SL_MASK) #define SNVS_HPLR_MC_SL_MASK (0x10U) #define SNVS_HPLR_MC_SL_SHIFT (4U) +/*! MC_SL + * 0b0..Write access (increment) is allowed + * 0b1..Write access (increment) is not allowed + */ #define SNVS_HPLR_MC_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_MC_SL_SHIFT)) & SNVS_HPLR_MC_SL_MASK) #define SNVS_HPLR_GPR_SL_MASK (0x20U) #define SNVS_HPLR_GPR_SL_SHIFT (5U) +/*! GPR_SL + * 0b0..Write access is allowed + * 0b1..Write access is not allowed + */ #define SNVS_HPLR_GPR_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_GPR_SL_SHIFT)) & SNVS_HPLR_GPR_SL_MASK) #define SNVS_HPLR_LPSVCR_SL_MASK (0x40U) #define SNVS_HPLR_LPSVCR_SL_SHIFT (6U) +/*! LPSVCR_SL + * 0b0..Write access is allowed + * 0b1..Write access is not allowed + */ #define SNVS_HPLR_LPSVCR_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_LPSVCR_SL_SHIFT)) & SNVS_HPLR_LPSVCR_SL_MASK) #define SNVS_HPLR_LPTDCR_SL_MASK (0x100U) #define SNVS_HPLR_LPTDCR_SL_SHIFT (8U) +/*! LPTDCR_SL + * 0b0..Write access is allowed + * 0b1..Write access is not allowed + */ #define SNVS_HPLR_LPTDCR_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_LPTDCR_SL_SHIFT)) & SNVS_HPLR_LPTDCR_SL_MASK) #define SNVS_HPLR_MKS_SL_MASK (0x200U) #define SNVS_HPLR_MKS_SL_SHIFT (9U) +/*! MKS_SL + * 0b0..Write access is allowed + * 0b1..Write access is not allowed + */ #define SNVS_HPLR_MKS_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_MKS_SL_SHIFT)) & SNVS_HPLR_MKS_SL_MASK) #define SNVS_HPLR_HPSVCR_L_MASK (0x10000U) #define SNVS_HPLR_HPSVCR_L_SHIFT (16U) +/*! HPSVCR_L + * 0b0..Write access is allowed + * 0b1..Write access is not allowed + */ #define SNVS_HPLR_HPSVCR_L(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_HPSVCR_L_SHIFT)) & SNVS_HPLR_HPSVCR_L_MASK) #define SNVS_HPLR_HPSICR_L_MASK (0x20000U) #define SNVS_HPLR_HPSICR_L_SHIFT (17U) +/*! HPSICR_L + * 0b0..Write access is allowed + * 0b1..Write access is not allowed + */ #define SNVS_HPLR_HPSICR_L(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_HPSICR_L_SHIFT)) & SNVS_HPLR_HPSICR_L_MASK) #define SNVS_HPLR_HAC_L_MASK (0x40000U) #define SNVS_HPLR_HAC_L_SHIFT (18U) +/*! HAC_L + * 0b0..Write access is allowed + * 0b1..Write access is not allowed + */ #define SNVS_HPLR_HAC_L(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_HAC_L_SHIFT)) & SNVS_HPLR_HAC_L_MASK) +/*! @} */ /*! @name HPCOMR - SNVS_HP Command Register */ +/*! @{ */ #define SNVS_HPCOMR_SSM_ST_MASK (0x1U) #define SNVS_HPCOMR_SSM_ST_SHIFT (0U) #define SNVS_HPCOMR_SSM_ST(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SSM_ST_SHIFT)) & SNVS_HPCOMR_SSM_ST_MASK) #define SNVS_HPCOMR_SSM_ST_DIS_MASK (0x2U) #define SNVS_HPCOMR_SSM_ST_DIS_SHIFT (1U) +/*! SSM_ST_DIS + * 0b0..Secure to Trusted State transition is enabled + * 0b1..Secure to Trusted State transition is disabled + */ #define SNVS_HPCOMR_SSM_ST_DIS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SSM_ST_DIS_SHIFT)) & SNVS_HPCOMR_SSM_ST_DIS_MASK) #define SNVS_HPCOMR_SSM_SFNS_DIS_MASK (0x4U) #define SNVS_HPCOMR_SSM_SFNS_DIS_SHIFT (2U) +/*! SSM_SFNS_DIS + * 0b0..Soft Fail to Non-Secure State transition is enabled + * 0b1..Soft Fail to Non-Secure State transition is disabled + */ #define SNVS_HPCOMR_SSM_SFNS_DIS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SSM_SFNS_DIS_SHIFT)) & SNVS_HPCOMR_SSM_SFNS_DIS_MASK) #define SNVS_HPCOMR_LP_SWR_MASK (0x10U) #define SNVS_HPCOMR_LP_SWR_SHIFT (4U) +/*! LP_SWR + * 0b0..No Action + * 0b1..Reset LP section + */ #define SNVS_HPCOMR_LP_SWR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_LP_SWR_SHIFT)) & SNVS_HPCOMR_LP_SWR_MASK) #define SNVS_HPCOMR_LP_SWR_DIS_MASK (0x20U) #define SNVS_HPCOMR_LP_SWR_DIS_SHIFT (5U) +/*! LP_SWR_DIS + * 0b0..LP software reset is enabled + * 0b1..LP software reset is disabled + */ #define SNVS_HPCOMR_LP_SWR_DIS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_LP_SWR_DIS_SHIFT)) & SNVS_HPCOMR_LP_SWR_DIS_MASK) #define SNVS_HPCOMR_SW_SV_MASK (0x100U) #define SNVS_HPCOMR_SW_SV_SHIFT (8U) @@ -19897,18 +32135,38 @@ typedef struct { #define SNVS_HPCOMR_SW_LPSV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SW_LPSV_SHIFT)) & SNVS_HPCOMR_SW_LPSV_MASK) #define SNVS_HPCOMR_PROG_ZMK_MASK (0x1000U) #define SNVS_HPCOMR_PROG_ZMK_SHIFT (12U) +/*! PROG_ZMK + * 0b0..No Action + * 0b1..Activate hardware key programming mechanism + */ #define SNVS_HPCOMR_PROG_ZMK(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_PROG_ZMK_SHIFT)) & SNVS_HPCOMR_PROG_ZMK_MASK) #define SNVS_HPCOMR_MKS_EN_MASK (0x2000U) #define SNVS_HPCOMR_MKS_EN_SHIFT (13U) +/*! MKS_EN + * 0b0..OTP master key is selected as an SNVS master key + * 0b1..SNVS master key is selected according to the setting of the MASTER_KEY_SEL field of LPMKCR + */ #define SNVS_HPCOMR_MKS_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_MKS_EN_SHIFT)) & SNVS_HPCOMR_MKS_EN_MASK) #define SNVS_HPCOMR_HAC_EN_MASK (0x10000U) #define SNVS_HPCOMR_HAC_EN_SHIFT (16U) +/*! HAC_EN + * 0b0..High Assurance Counter is disabled + * 0b1..High Assurance Counter is enabled + */ #define SNVS_HPCOMR_HAC_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_HAC_EN_SHIFT)) & SNVS_HPCOMR_HAC_EN_MASK) #define SNVS_HPCOMR_HAC_LOAD_MASK (0x20000U) #define SNVS_HPCOMR_HAC_LOAD_SHIFT (17U) +/*! HAC_LOAD + * 0b0..No Action + * 0b1..Load the HAC + */ #define SNVS_HPCOMR_HAC_LOAD(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_HAC_LOAD_SHIFT)) & SNVS_HPCOMR_HAC_LOAD_MASK) #define SNVS_HPCOMR_HAC_CLEAR_MASK (0x40000U) #define SNVS_HPCOMR_HAC_CLEAR_SHIFT (18U) +/*! HAC_CLEAR + * 0b0..No Action + * 0b1..Clear the HAC + */ #define SNVS_HPCOMR_HAC_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_HAC_CLEAR_SHIFT)) & SNVS_HPCOMR_HAC_CLEAR_MASK) #define SNVS_HPCOMR_HAC_STOP_MASK (0x80000U) #define SNVS_HPCOMR_HAC_STOP_SHIFT (19U) @@ -19916,28 +32174,85 @@ typedef struct { #define SNVS_HPCOMR_NPSWA_EN_MASK (0x80000000U) #define SNVS_HPCOMR_NPSWA_EN_SHIFT (31U) #define SNVS_HPCOMR_NPSWA_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_NPSWA_EN_SHIFT)) & SNVS_HPCOMR_NPSWA_EN_MASK) +/*! @} */ /*! @name HPCR - SNVS_HP Control Register */ +/*! @{ */ #define SNVS_HPCR_RTC_EN_MASK (0x1U) #define SNVS_HPCR_RTC_EN_SHIFT (0U) +/*! RTC_EN + * 0b0..RTC is disabled + * 0b1..RTC is enabled + */ #define SNVS_HPCR_RTC_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_RTC_EN_SHIFT)) & SNVS_HPCR_RTC_EN_MASK) #define SNVS_HPCR_HPTA_EN_MASK (0x2U) #define SNVS_HPCR_HPTA_EN_SHIFT (1U) +/*! HPTA_EN + * 0b0..HP Time Alarm Interrupt is disabled + * 0b1..HP Time Alarm Interrupt is enabled + */ #define SNVS_HPCR_HPTA_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_HPTA_EN_SHIFT)) & SNVS_HPCR_HPTA_EN_MASK) +#define SNVS_HPCR_DIS_PI_MASK (0x4U) +#define SNVS_HPCR_DIS_PI_SHIFT (2U) +/*! DIS_PI + * 0b0..Periodic interrupt will trigger a functional interrupt + * 0b1..Disable periodic interrupt in the function interrupt + */ +#define SNVS_HPCR_DIS_PI(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_DIS_PI_SHIFT)) & SNVS_HPCR_DIS_PI_MASK) #define SNVS_HPCR_PI_EN_MASK (0x8U) #define SNVS_HPCR_PI_EN_SHIFT (3U) +/*! PI_EN + * 0b0..HP Periodic Interrupt is disabled + * 0b1..HP Periodic Interrupt is enabled + */ #define SNVS_HPCR_PI_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_PI_EN_SHIFT)) & SNVS_HPCR_PI_EN_MASK) #define SNVS_HPCR_PI_FREQ_MASK (0xF0U) #define SNVS_HPCR_PI_FREQ_SHIFT (4U) +/*! PI_FREQ + * 0b0000..- bit 0 of the HPRTCLR is selected as a source of the periodic interrupt + * 0b0001..- bit 1 of the HPRTCLR is selected as a source of the periodic interrupt + * 0b0010..- bit 2 of the HPRTCLR is selected as a source of the periodic interrupt + * 0b0011..- bit 3 of the HPRTCLR is selected as a source of the periodic interrupt + * 0b0100..- bit 4 of the HPRTCLR is selected as a source of the periodic interrupt + * 0b0101..- bit 5 of the HPRTCLR is selected as a source of the periodic interrupt + * 0b0110..- bit 6 of the HPRTCLR is selected as a source of the periodic interrupt + * 0b0111..- bit 7 of the HPRTCLR is selected as a source of the periodic interrupt + * 0b1000..- bit 8 of the HPRTCLR is selected as a source of the periodic interrupt + * 0b1001..- bit 9 of the HPRTCLR is selected as a source of the periodic interrupt + * 0b1010..- bit 10 of the HPRTCLR is selected as a source of the periodic interrupt + * 0b1011..- bit 11 of the HPRTCLR is selected as a source of the periodic interrupt + * 0b1100..- bit 12 of the HPRTCLR is selected as a source of the periodic interrupt + * 0b1101..- bit 13 of the HPRTCLR is selected as a source of the periodic interrupt + * 0b1110..- bit 14 of the HPRTCLR is selected as a source of the periodic interrupt + * 0b1111..- bit 15 of the HPRTCLR is selected as a source of the periodic interrupt + */ #define SNVS_HPCR_PI_FREQ(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_PI_FREQ_SHIFT)) & SNVS_HPCR_PI_FREQ_MASK) #define SNVS_HPCR_HPCALB_EN_MASK (0x100U) #define SNVS_HPCR_HPCALB_EN_SHIFT (8U) +/*! HPCALB_EN + * 0b0..HP Timer calibration disabled + * 0b1..HP Timer calibration enabled + */ #define SNVS_HPCR_HPCALB_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_HPCALB_EN_SHIFT)) & SNVS_HPCR_HPCALB_EN_MASK) #define SNVS_HPCR_HPCALB_VAL_MASK (0x7C00U) #define SNVS_HPCR_HPCALB_VAL_SHIFT (10U) +/*! HPCALB_VAL + * 0b00000..+0 counts per each 32768 ticks of the counter + * 0b00001..+1 counts per each 32768 ticks of the counter + * 0b00010..+2 counts per each 32768 ticks of the counter + * 0b01111..+15 counts per each 32768 ticks of the counter + * 0b10000..-16 counts per each 32768 ticks of the counter + * 0b10001..-15 counts per each 32768 ticks of the counter + * 0b11110..-2 counts per each 32768 ticks of the counter + * 0b11111..-1 counts per each 32768 ticks of the counter + */ #define SNVS_HPCR_HPCALB_VAL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_HPCALB_VAL_SHIFT)) & SNVS_HPCR_HPCALB_VAL_MASK) #define SNVS_HPCR_HP_TS_MASK (0x10000U) #define SNVS_HPCR_HP_TS_SHIFT (16U) +/*! HP_TS + * 0b0..No Action + * 0b1..Synchronize the HP Time Counter to the LP Time Counter + */ #define SNVS_HPCR_HP_TS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_HP_TS_SHIFT)) & SNVS_HPCR_HP_TS_MASK) #define SNVS_HPCR_BTN_CONFIG_MASK (0x7000000U) #define SNVS_HPCR_BTN_CONFIG_SHIFT (24U) @@ -19945,59 +32260,131 @@ typedef struct { #define SNVS_HPCR_BTN_MASK_MASK (0x8000000U) #define SNVS_HPCR_BTN_MASK_SHIFT (27U) #define SNVS_HPCR_BTN_MASK(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_BTN_MASK_SHIFT)) & SNVS_HPCR_BTN_MASK_MASK) +/*! @} */ /*! @name HPSICR - SNVS_HP Security Interrupt Control Register */ +/*! @{ */ #define SNVS_HPSICR_SV0_EN_MASK (0x1U) #define SNVS_HPSICR_SV0_EN_SHIFT (0U) +/*! SV0_EN + * 0b0..Security Violation 0 Interrupt is Disabled + * 0b1..Security Violation 0 Interrupt is Enabled + */ #define SNVS_HPSICR_SV0_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_SV0_EN_SHIFT)) & SNVS_HPSICR_SV0_EN_MASK) #define SNVS_HPSICR_SV1_EN_MASK (0x2U) #define SNVS_HPSICR_SV1_EN_SHIFT (1U) +/*! SV1_EN + * 0b0..Security Violation 1 Interrupt is Disabled + * 0b1..Security Violation 1 Interrupt is Enabled + */ #define SNVS_HPSICR_SV1_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_SV1_EN_SHIFT)) & SNVS_HPSICR_SV1_EN_MASK) #define SNVS_HPSICR_SV2_EN_MASK (0x4U) #define SNVS_HPSICR_SV2_EN_SHIFT (2U) +/*! SV2_EN + * 0b0..Security Violation 2 Interrupt is Disabled + * 0b1..Security Violation 2 Interrupt is Enabled + */ #define SNVS_HPSICR_SV2_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_SV2_EN_SHIFT)) & SNVS_HPSICR_SV2_EN_MASK) #define SNVS_HPSICR_SV3_EN_MASK (0x8U) #define SNVS_HPSICR_SV3_EN_SHIFT (3U) +/*! SV3_EN + * 0b0..Security Violation 3 Interrupt is Disabled + * 0b1..Security Violation 3 Interrupt is Enabled + */ #define SNVS_HPSICR_SV3_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_SV3_EN_SHIFT)) & SNVS_HPSICR_SV3_EN_MASK) #define SNVS_HPSICR_SV4_EN_MASK (0x10U) #define SNVS_HPSICR_SV4_EN_SHIFT (4U) +/*! SV4_EN + * 0b0..Security Violation 4 Interrupt is Disabled + * 0b1..Security Violation 4 Interrupt is Enabled + */ #define SNVS_HPSICR_SV4_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_SV4_EN_SHIFT)) & SNVS_HPSICR_SV4_EN_MASK) #define SNVS_HPSICR_SV5_EN_MASK (0x20U) #define SNVS_HPSICR_SV5_EN_SHIFT (5U) +/*! SV5_EN + * 0b0..Security Violation 5 Interrupt is Disabled + * 0b1..Security Violation 5 Interrupt is Enabled + */ #define SNVS_HPSICR_SV5_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_SV5_EN_SHIFT)) & SNVS_HPSICR_SV5_EN_MASK) #define SNVS_HPSICR_LPSVI_EN_MASK (0x80000000U) #define SNVS_HPSICR_LPSVI_EN_SHIFT (31U) +/*! LPSVI_EN + * 0b0..LP Security Violation Interrupt is Disabled + * 0b1..LP Security Violation Interrupt is Enabled + */ #define SNVS_HPSICR_LPSVI_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_LPSVI_EN_SHIFT)) & SNVS_HPSICR_LPSVI_EN_MASK) +/*! @} */ /*! @name HPSVCR - SNVS_HP Security Violation Control Register */ +/*! @{ */ #define SNVS_HPSVCR_SV0_CFG_MASK (0x1U) #define SNVS_HPSVCR_SV0_CFG_SHIFT (0U) +/*! SV0_CFG + * 0b0..Security Violation 0 is a non-fatal violation + * 0b1..Security Violation 0 is a fatal violation + */ #define SNVS_HPSVCR_SV0_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_SV0_CFG_SHIFT)) & SNVS_HPSVCR_SV0_CFG_MASK) #define SNVS_HPSVCR_SV1_CFG_MASK (0x2U) #define SNVS_HPSVCR_SV1_CFG_SHIFT (1U) +/*! SV1_CFG + * 0b0..Security Violation 1 is a non-fatal violation + * 0b1..Security Violation 1 is a fatal violation + */ #define SNVS_HPSVCR_SV1_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_SV1_CFG_SHIFT)) & SNVS_HPSVCR_SV1_CFG_MASK) #define SNVS_HPSVCR_SV2_CFG_MASK (0x4U) #define SNVS_HPSVCR_SV2_CFG_SHIFT (2U) +/*! SV2_CFG + * 0b0..Security Violation 2 is a non-fatal violation + * 0b1..Security Violation 2 is a fatal violation + */ #define SNVS_HPSVCR_SV2_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_SV2_CFG_SHIFT)) & SNVS_HPSVCR_SV2_CFG_MASK) #define SNVS_HPSVCR_SV3_CFG_MASK (0x8U) #define SNVS_HPSVCR_SV3_CFG_SHIFT (3U) +/*! SV3_CFG + * 0b0..Security Violation 3 is a non-fatal violation + * 0b1..Security Violation 3 is a fatal violation + */ #define SNVS_HPSVCR_SV3_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_SV3_CFG_SHIFT)) & SNVS_HPSVCR_SV3_CFG_MASK) #define SNVS_HPSVCR_SV4_CFG_MASK (0x10U) #define SNVS_HPSVCR_SV4_CFG_SHIFT (4U) +/*! SV4_CFG + * 0b0..Security Violation 4 is a non-fatal violation + * 0b1..Security Violation 4 is a fatal violation + */ #define SNVS_HPSVCR_SV4_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_SV4_CFG_SHIFT)) & SNVS_HPSVCR_SV4_CFG_MASK) #define SNVS_HPSVCR_SV5_CFG_MASK (0x60U) #define SNVS_HPSVCR_SV5_CFG_SHIFT (5U) +/*! SV5_CFG + * 0b00..Security Violation 5 is disabled + * 0b01..Security Violation 5 is a non-fatal violation + * 0b1x..Security Violation 5 is a fatal violation + */ #define SNVS_HPSVCR_SV5_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_SV5_CFG_SHIFT)) & SNVS_HPSVCR_SV5_CFG_MASK) #define SNVS_HPSVCR_LPSV_CFG_MASK (0xC0000000U) #define SNVS_HPSVCR_LPSV_CFG_SHIFT (30U) +/*! LPSV_CFG + * 0b00..LP security violation is disabled + * 0b01..LP security violation is a non-fatal violation + * 0b1x..LP security violation is a fatal violation + */ #define SNVS_HPSVCR_LPSV_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_LPSV_CFG_SHIFT)) & SNVS_HPSVCR_LPSV_CFG_MASK) +/*! @} */ /*! @name HPSR - SNVS_HP Status Register */ +/*! @{ */ #define SNVS_HPSR_HPTA_MASK (0x1U) #define SNVS_HPSR_HPTA_SHIFT (0U) +/*! HPTA + * 0b0..No time alarm interrupt occurred. + * 0b1..A time alarm interrupt occurred. + */ #define SNVS_HPSR_HPTA(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_HPTA_SHIFT)) & SNVS_HPSR_HPTA_MASK) #define SNVS_HPSR_PI_MASK (0x2U) #define SNVS_HPSR_PI_SHIFT (1U) +/*! PI + * 0b0..No periodic interrupt occurred. + * 0b1..A periodic interrupt occurred. + */ #define SNVS_HPSR_PI(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_PI_SHIFT)) & SNVS_HPSR_PI_MASK) #define SNVS_HPSR_LPDIS_MASK (0x10U) #define SNVS_HPSR_LPDIS_SHIFT (4U) @@ -20010,41 +32397,88 @@ typedef struct { #define SNVS_HPSR_BI(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_BI_SHIFT)) & SNVS_HPSR_BI_MASK) #define SNVS_HPSR_SSM_STATE_MASK (0xF00U) #define SNVS_HPSR_SSM_STATE_SHIFT (8U) +/*! SSM_STATE + * 0b0000..Init + * 0b0001..Hard Fail + * 0b0011..Soft Fail + * 0b1000..Init Intermediate (transition state between Init and Check - SSM stays in this state only one clock cycle) + * 0b1001..Check + * 0b1011..Non-Secure + * 0b1101..Trusted + * 0b1111..Secure + */ #define SNVS_HPSR_SSM_STATE(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_SSM_STATE_SHIFT)) & SNVS_HPSR_SSM_STATE_MASK) -#define SNVS_HPSR_SYS_SECURITY_CFG_MASK (0x7000U) -#define SNVS_HPSR_SYS_SECURITY_CFG_SHIFT (12U) -#define SNVS_HPSR_SYS_SECURITY_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_SYS_SECURITY_CFG_SHIFT)) & SNVS_HPSR_SYS_SECURITY_CFG_MASK) -#define SNVS_HPSR_SYS_SECURE_BOOT_MASK (0x8000U) -#define SNVS_HPSR_SYS_SECURE_BOOT_SHIFT (15U) -#define SNVS_HPSR_SYS_SECURE_BOOT(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_SYS_SECURE_BOOT_SHIFT)) & SNVS_HPSR_SYS_SECURE_BOOT_MASK) +#define SNVS_HPSR_SECURITY_CONFIG_MASK (0xF000U) +#define SNVS_HPSR_SECURITY_CONFIG_SHIFT (12U) +/*! SECURITY_CONFIG + * 0b0000, 0b1000..FAB configuration + * 0b0001, 0b0010, 0b0011..OPEN configuration + * 0b1010, 0b1001, 0b1011..CLOSED configuration + * 0bx1xx..FIELD RETURN configuration + */ +#define SNVS_HPSR_SECURITY_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_SECURITY_CONFIG_SHIFT)) & SNVS_HPSR_SECURITY_CONFIG_MASK) #define SNVS_HPSR_OTPMK_SYNDROME_MASK (0x1FF0000U) #define SNVS_HPSR_OTPMK_SYNDROME_SHIFT (16U) #define SNVS_HPSR_OTPMK_SYNDROME(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_OTPMK_SYNDROME_SHIFT)) & SNVS_HPSR_OTPMK_SYNDROME_MASK) #define SNVS_HPSR_OTPMK_ZERO_MASK (0x8000000U) #define SNVS_HPSR_OTPMK_ZERO_SHIFT (27U) +/*! OTPMK_ZERO + * 0b0..The OTPMK is not zero. + * 0b1..The OTPMK is zero. + */ #define SNVS_HPSR_OTPMK_ZERO(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_OTPMK_ZERO_SHIFT)) & SNVS_HPSR_OTPMK_ZERO_MASK) #define SNVS_HPSR_ZMK_ZERO_MASK (0x80000000U) #define SNVS_HPSR_ZMK_ZERO_SHIFT (31U) +/*! ZMK_ZERO + * 0b0..The ZMK is not zero. + * 0b1..The ZMK is zero. + */ #define SNVS_HPSR_ZMK_ZERO(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_ZMK_ZERO_SHIFT)) & SNVS_HPSR_ZMK_ZERO_MASK) +/*! @} */ /*! @name HPSVSR - SNVS_HP Security Violation Status Register */ +/*! @{ */ #define SNVS_HPSVSR_SV0_MASK (0x1U) #define SNVS_HPSVSR_SV0_SHIFT (0U) +/*! SV0 + * 0b0..No Security Violation 0 security violation was detected. + * 0b1..Security Violation 0 security violation was detected. + */ #define SNVS_HPSVSR_SV0(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SV0_SHIFT)) & SNVS_HPSVSR_SV0_MASK) #define SNVS_HPSVSR_SV1_MASK (0x2U) #define SNVS_HPSVSR_SV1_SHIFT (1U) +/*! SV1 + * 0b0..No Security Violation 1 security violation was detected. + * 0b1..Security Violation 1 security violation was detected. + */ #define SNVS_HPSVSR_SV1(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SV1_SHIFT)) & SNVS_HPSVSR_SV1_MASK) #define SNVS_HPSVSR_SV2_MASK (0x4U) #define SNVS_HPSVSR_SV2_SHIFT (2U) +/*! SV2 + * 0b0..No Security Violation 2 security violation was detected. + * 0b1..Security Violation 2 security violation was detected. + */ #define SNVS_HPSVSR_SV2(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SV2_SHIFT)) & SNVS_HPSVSR_SV2_MASK) #define SNVS_HPSVSR_SV3_MASK (0x8U) #define SNVS_HPSVSR_SV3_SHIFT (3U) +/*! SV3 + * 0b0..No Security Violation 3 security violation was detected. + * 0b1..Security Violation 3 security violation was detected. + */ #define SNVS_HPSVSR_SV3(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SV3_SHIFT)) & SNVS_HPSVSR_SV3_MASK) #define SNVS_HPSVSR_SV4_MASK (0x10U) #define SNVS_HPSVSR_SV4_SHIFT (4U) +/*! SV4 + * 0b0..No Security Violation 4 security violation was detected. + * 0b1..Security Violation 4 security violation was detected. + */ #define SNVS_HPSVSR_SV4(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SV4_SHIFT)) & SNVS_HPSVSR_SV4_MASK) #define SNVS_HPSVSR_SV5_MASK (0x20U) #define SNVS_HPSVSR_SV5_SHIFT (5U) +/*! SV5 + * 0b0..No Security Violation 5 security violation was detected. + * 0b1..Security Violation 5 security violation was detected. + */ #define SNVS_HPSVSR_SV5(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SV5_SHIFT)) & SNVS_HPSVSR_SV5_MASK) #define SNVS_HPSVSR_SW_SV_MASK (0x2000U) #define SNVS_HPSVSR_SW_SV_SHIFT (13U) @@ -20060,100 +32494,194 @@ typedef struct { #define SNVS_HPSVSR_ZMK_SYNDROME(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_ZMK_SYNDROME_SHIFT)) & SNVS_HPSVSR_ZMK_SYNDROME_MASK) #define SNVS_HPSVSR_ZMK_ECC_FAIL_MASK (0x8000000U) #define SNVS_HPSVSR_ZMK_ECC_FAIL_SHIFT (27U) +/*! ZMK_ECC_FAIL + * 0b0..ZMK ECC Failure was not detected. + * 0b1..ZMK ECC Failure was detected. + */ #define SNVS_HPSVSR_ZMK_ECC_FAIL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_ZMK_ECC_FAIL_SHIFT)) & SNVS_HPSVSR_ZMK_ECC_FAIL_MASK) #define SNVS_HPSVSR_LP_SEC_VIO_MASK (0x80000000U) #define SNVS_HPSVSR_LP_SEC_VIO_SHIFT (31U) #define SNVS_HPSVSR_LP_SEC_VIO(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_LP_SEC_VIO_SHIFT)) & SNVS_HPSVSR_LP_SEC_VIO_MASK) +/*! @} */ /*! @name HPHACIVR - SNVS_HP High Assurance Counter IV Register */ +/*! @{ */ #define SNVS_HPHACIVR_HAC_COUNTER_IV_MASK (0xFFFFFFFFU) #define SNVS_HPHACIVR_HAC_COUNTER_IV_SHIFT (0U) #define SNVS_HPHACIVR_HAC_COUNTER_IV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPHACIVR_HAC_COUNTER_IV_SHIFT)) & SNVS_HPHACIVR_HAC_COUNTER_IV_MASK) +/*! @} */ /*! @name HPHACR - SNVS_HP High Assurance Counter Register */ +/*! @{ */ #define SNVS_HPHACR_HAC_COUNTER_MASK (0xFFFFFFFFU) #define SNVS_HPHACR_HAC_COUNTER_SHIFT (0U) #define SNVS_HPHACR_HAC_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPHACR_HAC_COUNTER_SHIFT)) & SNVS_HPHACR_HAC_COUNTER_MASK) +/*! @} */ /*! @name HPRTCMR - SNVS_HP Real Time Counter MSB Register */ +/*! @{ */ #define SNVS_HPRTCMR_RTC_MASK (0x7FFFU) #define SNVS_HPRTCMR_RTC_SHIFT (0U) #define SNVS_HPRTCMR_RTC(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPRTCMR_RTC_SHIFT)) & SNVS_HPRTCMR_RTC_MASK) +/*! @} */ /*! @name HPRTCLR - SNVS_HP Real Time Counter LSB Register */ +/*! @{ */ #define SNVS_HPRTCLR_RTC_MASK (0xFFFFFFFFU) #define SNVS_HPRTCLR_RTC_SHIFT (0U) #define SNVS_HPRTCLR_RTC(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPRTCLR_RTC_SHIFT)) & SNVS_HPRTCLR_RTC_MASK) +/*! @} */ /*! @name HPTAMR - SNVS_HP Time Alarm MSB Register */ +/*! @{ */ #define SNVS_HPTAMR_HPTA_MS_MASK (0x7FFFU) #define SNVS_HPTAMR_HPTA_MS_SHIFT (0U) #define SNVS_HPTAMR_HPTA_MS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPTAMR_HPTA_MS_SHIFT)) & SNVS_HPTAMR_HPTA_MS_MASK) +/*! @} */ /*! @name HPTALR - SNVS_HP Time Alarm LSB Register */ +/*! @{ */ #define SNVS_HPTALR_HPTA_LS_MASK (0xFFFFFFFFU) #define SNVS_HPTALR_HPTA_LS_SHIFT (0U) #define SNVS_HPTALR_HPTA_LS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPTALR_HPTA_LS_SHIFT)) & SNVS_HPTALR_HPTA_LS_MASK) +/*! @} */ /*! @name LPLR - SNVS_LP Lock Register */ +/*! @{ */ #define SNVS_LPLR_ZMK_WHL_MASK (0x1U) #define SNVS_LPLR_ZMK_WHL_SHIFT (0U) +/*! ZMK_WHL + * 0b0..Write access is allowed. + * 0b1..Write access is not allowed. + */ #define SNVS_LPLR_ZMK_WHL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_ZMK_WHL_SHIFT)) & SNVS_LPLR_ZMK_WHL_MASK) #define SNVS_LPLR_ZMK_RHL_MASK (0x2U) #define SNVS_LPLR_ZMK_RHL_SHIFT (1U) +/*! ZMK_RHL + * 0b0..Read access is allowed (only in software programming mode). + * 0b1..Read access is not allowed. + */ #define SNVS_LPLR_ZMK_RHL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_ZMK_RHL_SHIFT)) & SNVS_LPLR_ZMK_RHL_MASK) #define SNVS_LPLR_SRTC_HL_MASK (0x4U) #define SNVS_LPLR_SRTC_HL_SHIFT (2U) +/*! SRTC_HL + * 0b0..Write access is allowed. + * 0b1..Write access is not allowed. + */ #define SNVS_LPLR_SRTC_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_SRTC_HL_SHIFT)) & SNVS_LPLR_SRTC_HL_MASK) #define SNVS_LPLR_LPCALB_HL_MASK (0x8U) #define SNVS_LPLR_LPCALB_HL_SHIFT (3U) +/*! LPCALB_HL + * 0b0..Write access is allowed. + * 0b1..Write access is not allowed. + */ #define SNVS_LPLR_LPCALB_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_LPCALB_HL_SHIFT)) & SNVS_LPLR_LPCALB_HL_MASK) #define SNVS_LPLR_MC_HL_MASK (0x10U) #define SNVS_LPLR_MC_HL_SHIFT (4U) +/*! MC_HL + * 0b0..Write access (increment) is allowed. + * 0b1..Write access (increment) is not allowed. + */ #define SNVS_LPLR_MC_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_MC_HL_SHIFT)) & SNVS_LPLR_MC_HL_MASK) #define SNVS_LPLR_GPR_HL_MASK (0x20U) #define SNVS_LPLR_GPR_HL_SHIFT (5U) +/*! GPR_HL + * 0b0..Write access is allowed. + * 0b1..Write access is not allowed. + */ #define SNVS_LPLR_GPR_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_GPR_HL_SHIFT)) & SNVS_LPLR_GPR_HL_MASK) #define SNVS_LPLR_LPSVCR_HL_MASK (0x40U) #define SNVS_LPLR_LPSVCR_HL_SHIFT (6U) +/*! LPSVCR_HL + * 0b0..Write access is allowed. + * 0b1..Write access is not allowed. + */ #define SNVS_LPLR_LPSVCR_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_LPSVCR_HL_SHIFT)) & SNVS_LPLR_LPSVCR_HL_MASK) #define SNVS_LPLR_LPTDCR_HL_MASK (0x100U) #define SNVS_LPLR_LPTDCR_HL_SHIFT (8U) +/*! LPTDCR_HL + * 0b0..Write access is allowed. + * 0b1..Write access is not allowed. + */ #define SNVS_LPLR_LPTDCR_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_LPTDCR_HL_SHIFT)) & SNVS_LPLR_LPTDCR_HL_MASK) #define SNVS_LPLR_MKS_HL_MASK (0x200U) #define SNVS_LPLR_MKS_HL_SHIFT (9U) +/*! MKS_HL + * 0b0..Write access is allowed. + * 0b1..Write access is not allowed. + */ #define SNVS_LPLR_MKS_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_MKS_HL_SHIFT)) & SNVS_LPLR_MKS_HL_MASK) +/*! @} */ /*! @name LPCR - SNVS_LP Control Register */ +/*! @{ */ #define SNVS_LPCR_SRTC_ENV_MASK (0x1U) #define SNVS_LPCR_SRTC_ENV_SHIFT (0U) +/*! SRTC_ENV + * 0b0..SRTC is disabled or invalid. + * 0b1..SRTC is enabled and valid. + */ #define SNVS_LPCR_SRTC_ENV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_SRTC_ENV_SHIFT)) & SNVS_LPCR_SRTC_ENV_MASK) #define SNVS_LPCR_LPTA_EN_MASK (0x2U) #define SNVS_LPCR_LPTA_EN_SHIFT (1U) +/*! LPTA_EN + * 0b0..LP time alarm interrupt is disabled. + * 0b1..LP time alarm interrupt is enabled. + */ #define SNVS_LPCR_LPTA_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_LPTA_EN_SHIFT)) & SNVS_LPCR_LPTA_EN_MASK) #define SNVS_LPCR_MC_ENV_MASK (0x4U) #define SNVS_LPCR_MC_ENV_SHIFT (2U) +/*! MC_ENV + * 0b0..MC is disabled or invalid. + * 0b1..MC is enabled and valid. + */ #define SNVS_LPCR_MC_ENV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_MC_ENV_SHIFT)) & SNVS_LPCR_MC_ENV_MASK) #define SNVS_LPCR_LPWUI_EN_MASK (0x8U) #define SNVS_LPCR_LPWUI_EN_SHIFT (3U) #define SNVS_LPCR_LPWUI_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_LPWUI_EN_SHIFT)) & SNVS_LPCR_LPWUI_EN_MASK) #define SNVS_LPCR_SRTC_INV_EN_MASK (0x10U) #define SNVS_LPCR_SRTC_INV_EN_SHIFT (4U) +/*! SRTC_INV_EN + * 0b0..SRTC stays valid in the case of security violation. + * 0b1..SRTC is invalidated in the case of security violation. + */ #define SNVS_LPCR_SRTC_INV_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_SRTC_INV_EN_SHIFT)) & SNVS_LPCR_SRTC_INV_EN_MASK) #define SNVS_LPCR_DP_EN_MASK (0x20U) #define SNVS_LPCR_DP_EN_SHIFT (5U) +/*! DP_EN + * 0b0..Smart PMIC enabled. + * 0b1..Dumb PMIC enabled. + */ #define SNVS_LPCR_DP_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_DP_EN_SHIFT)) & SNVS_LPCR_DP_EN_MASK) #define SNVS_LPCR_TOP_MASK (0x40U) #define SNVS_LPCR_TOP_SHIFT (6U) +/*! TOP + * 0b0..Leave system power on. + * 0b1..Turn off system power. + */ #define SNVS_LPCR_TOP(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_TOP_SHIFT)) & SNVS_LPCR_TOP_MASK) #define SNVS_LPCR_PWR_GLITCH_EN_MASK (0x80U) #define SNVS_LPCR_PWR_GLITCH_EN_SHIFT (7U) #define SNVS_LPCR_PWR_GLITCH_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_PWR_GLITCH_EN_SHIFT)) & SNVS_LPCR_PWR_GLITCH_EN_MASK) #define SNVS_LPCR_LPCALB_EN_MASK (0x100U) #define SNVS_LPCR_LPCALB_EN_SHIFT (8U) +/*! LPCALB_EN + * 0b0..SRTC Time calibration is disabled. + * 0b1..SRTC Time calibration is enabled. + */ #define SNVS_LPCR_LPCALB_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_LPCALB_EN_SHIFT)) & SNVS_LPCR_LPCALB_EN_MASK) #define SNVS_LPCR_LPCALB_VAL_MASK (0x7C00U) #define SNVS_LPCR_LPCALB_VAL_SHIFT (10U) +/*! LPCALB_VAL + * 0b00000..+0 counts per each 32768 ticks of the counter clock + * 0b00001..+1 counts per each 32768 ticks of the counter clock + * 0b00010..+2 counts per each 32768 ticks of the counter clock + * 0b01111..+15 counts per each 32768 ticks of the counter clock + * 0b10000..-16 counts per each 32768 ticks of the counter clock + * 0b10001..-15 counts per each 32768 ticks of the counter clock + * 0b11110..-2 counts per each 32768 ticks of the counter clock + * 0b11111..-1 counts per each 32768 ticks of the counter clock + */ #define SNVS_LPCR_LPCALB_VAL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_LPCALB_VAL_SHIFT)) & SNVS_LPCR_LPCALB_VAL_MASK) #define SNVS_LPCR_BTN_PRESS_TIME_MASK (0x30000U) #define SNVS_LPCR_BTN_PRESS_TIME_SHIFT (16U) @@ -20173,56 +32701,119 @@ typedef struct { #define SNVS_LPCR_GPR_Z_DIS_MASK (0x1000000U) #define SNVS_LPCR_GPR_Z_DIS_SHIFT (24U) #define SNVS_LPCR_GPR_Z_DIS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_GPR_Z_DIS_SHIFT)) & SNVS_LPCR_GPR_Z_DIS_MASK) +/*! @} */ /*! @name LPMKCR - SNVS_LP Master Key Control Register */ +/*! @{ */ #define SNVS_LPMKCR_MASTER_KEY_SEL_MASK (0x3U) #define SNVS_LPMKCR_MASTER_KEY_SEL_SHIFT (0U) +/*! MASTER_KEY_SEL + * 0b0x..Select one time programmable master key. + * 0b10..Select zeroizable master key when MKS_EN bit is set . + * 0b11..Select combined master key when MKS_EN bit is set . + */ #define SNVS_LPMKCR_MASTER_KEY_SEL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPMKCR_MASTER_KEY_SEL_SHIFT)) & SNVS_LPMKCR_MASTER_KEY_SEL_MASK) #define SNVS_LPMKCR_ZMK_HWP_MASK (0x4U) #define SNVS_LPMKCR_ZMK_HWP_SHIFT (2U) +/*! ZMK_HWP + * 0b0..ZMK is in the software programming mode. + * 0b1..ZMK is in the hardware programming mode. + */ #define SNVS_LPMKCR_ZMK_HWP(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPMKCR_ZMK_HWP_SHIFT)) & SNVS_LPMKCR_ZMK_HWP_MASK) #define SNVS_LPMKCR_ZMK_VAL_MASK (0x8U) #define SNVS_LPMKCR_ZMK_VAL_SHIFT (3U) +/*! ZMK_VAL + * 0b0..ZMK is not valid. + * 0b1..ZMK is valid. + */ #define SNVS_LPMKCR_ZMK_VAL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPMKCR_ZMK_VAL_SHIFT)) & SNVS_LPMKCR_ZMK_VAL_MASK) #define SNVS_LPMKCR_ZMK_ECC_EN_MASK (0x10U) #define SNVS_LPMKCR_ZMK_ECC_EN_SHIFT (4U) +/*! ZMK_ECC_EN + * 0b0..ZMK ECC check is disabled. + * 0b1..ZMK ECC check is enabled. + */ #define SNVS_LPMKCR_ZMK_ECC_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPMKCR_ZMK_ECC_EN_SHIFT)) & SNVS_LPMKCR_ZMK_ECC_EN_MASK) #define SNVS_LPMKCR_ZMK_ECC_VALUE_MASK (0xFF80U) #define SNVS_LPMKCR_ZMK_ECC_VALUE_SHIFT (7U) #define SNVS_LPMKCR_ZMK_ECC_VALUE(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPMKCR_ZMK_ECC_VALUE_SHIFT)) & SNVS_LPMKCR_ZMK_ECC_VALUE_MASK) +/*! @} */ /*! @name LPSVCR - SNVS_LP Security Violation Control Register */ +/*! @{ */ #define SNVS_LPSVCR_SV0_EN_MASK (0x1U) #define SNVS_LPSVCR_SV0_EN_SHIFT (0U) +/*! SV0_EN + * 0b0..Security Violation 0 is disabled in the LP domain. + * 0b1..Security Violation 0 is enabled in the LP domain. + */ #define SNVS_LPSVCR_SV0_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_SV0_EN_SHIFT)) & SNVS_LPSVCR_SV0_EN_MASK) #define SNVS_LPSVCR_SV1_EN_MASK (0x2U) #define SNVS_LPSVCR_SV1_EN_SHIFT (1U) +/*! SV1_EN + * 0b0..Security Violation 1 is disabled in the LP domain. + * 0b1..Security Violation 1 is enabled in the LP domain. + */ #define SNVS_LPSVCR_SV1_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_SV1_EN_SHIFT)) & SNVS_LPSVCR_SV1_EN_MASK) #define SNVS_LPSVCR_SV2_EN_MASK (0x4U) #define SNVS_LPSVCR_SV2_EN_SHIFT (2U) +/*! SV2_EN + * 0b0..Security Violation 2 is disabled in the LP domain. + * 0b1..Security Violation 2 is enabled in the LP domain. + */ #define SNVS_LPSVCR_SV2_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_SV2_EN_SHIFT)) & SNVS_LPSVCR_SV2_EN_MASK) #define SNVS_LPSVCR_SV3_EN_MASK (0x8U) #define SNVS_LPSVCR_SV3_EN_SHIFT (3U) +/*! SV3_EN + * 0b0..Security Violation 3 is disabled in the LP domain. + * 0b1..Security Violation 3 is enabled in the LP domain. + */ #define SNVS_LPSVCR_SV3_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_SV3_EN_SHIFT)) & SNVS_LPSVCR_SV3_EN_MASK) #define SNVS_LPSVCR_SV4_EN_MASK (0x10U) #define SNVS_LPSVCR_SV4_EN_SHIFT (4U) +/*! SV4_EN + * 0b0..Security Violation 4 is disabled in the LP domain. + * 0b1..Security Violation 4 is enabled in the LP domain. + */ #define SNVS_LPSVCR_SV4_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_SV4_EN_SHIFT)) & SNVS_LPSVCR_SV4_EN_MASK) #define SNVS_LPSVCR_SV5_EN_MASK (0x20U) #define SNVS_LPSVCR_SV5_EN_SHIFT (5U) +/*! SV5_EN + * 0b0..Security Violation 5 is disabled in the LP domain. + * 0b1..Security Violation 5 is enabled in the LP domain. + */ #define SNVS_LPSVCR_SV5_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_SV5_EN_SHIFT)) & SNVS_LPSVCR_SV5_EN_MASK) +/*! @} */ /*! @name LPTDCR - SNVS_LP Tamper Detectors Configuration Register */ +/*! @{ */ #define SNVS_LPTDCR_SRTCR_EN_MASK (0x2U) #define SNVS_LPTDCR_SRTCR_EN_SHIFT (1U) +/*! SRTCR_EN + * 0b0..SRTC rollover is disabled. + * 0b1..SRTC rollover is enabled. + */ #define SNVS_LPTDCR_SRTCR_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_SRTCR_EN_SHIFT)) & SNVS_LPTDCR_SRTCR_EN_MASK) #define SNVS_LPTDCR_MCR_EN_MASK (0x4U) #define SNVS_LPTDCR_MCR_EN_SHIFT (2U) +/*! MCR_EN + * 0b0..MC rollover is disabled. + * 0b1..MC rollover is enabled. + */ #define SNVS_LPTDCR_MCR_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_MCR_EN_SHIFT)) & SNVS_LPTDCR_MCR_EN_MASK) #define SNVS_LPTDCR_ET1_EN_MASK (0x200U) #define SNVS_LPTDCR_ET1_EN_SHIFT (9U) +/*! ET1_EN + * 0b0..External tamper 1 is disabled. + * 0b1..External tamper 1 is enabled. + */ #define SNVS_LPTDCR_ET1_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_ET1_EN_SHIFT)) & SNVS_LPTDCR_ET1_EN_MASK) #define SNVS_LPTDCR_ET1P_MASK (0x800U) #define SNVS_LPTDCR_ET1P_SHIFT (11U) +/*! ET1P + * 0b0..External tamper 1 is active low. + * 0b1..External tamper 1 is active high. + */ #define SNVS_LPTDCR_ET1P(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_ET1P_SHIFT)) & SNVS_LPTDCR_ET1P_MASK) #define SNVS_LPTDCR_PFD_OBSERV_MASK (0x4000U) #define SNVS_LPTDCR_PFD_OBSERV_SHIFT (14U) @@ -20232,106 +32823,174 @@ typedef struct { #define SNVS_LPTDCR_POR_OBSERV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_POR_OBSERV_SHIFT)) & SNVS_LPTDCR_POR_OBSERV_MASK) #define SNVS_LPTDCR_OSCB_MASK (0x10000000U) #define SNVS_LPTDCR_OSCB_SHIFT (28U) +/*! OSCB + * 0b0..Normal SRTC clock oscillator not bypassed. + * 0b1..Normal SRTC clock oscillator bypassed. Alternate clock can drive the SRTC clock source. + */ #define SNVS_LPTDCR_OSCB(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_OSCB_SHIFT)) & SNVS_LPTDCR_OSCB_MASK) +/*! @} */ /*! @name LPSR - SNVS_LP Status Register */ +/*! @{ */ #define SNVS_LPSR_LPTA_MASK (0x1U) #define SNVS_LPSR_LPTA_SHIFT (0U) +/*! LPTA + * 0b0..No time alarm interrupt occurred. + * 0b1..A time alarm interrupt occurred. + */ #define SNVS_LPSR_LPTA(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_LPTA_SHIFT)) & SNVS_LPSR_LPTA_MASK) #define SNVS_LPSR_SRTCR_MASK (0x2U) #define SNVS_LPSR_SRTCR_SHIFT (1U) +/*! SRTCR + * 0b0..SRTC has not reached its maximum value. + * 0b1..SRTC has reached its maximum value. + */ #define SNVS_LPSR_SRTCR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_SRTCR_SHIFT)) & SNVS_LPSR_SRTCR_MASK) #define SNVS_LPSR_MCR_MASK (0x4U) #define SNVS_LPSR_MCR_SHIFT (2U) +/*! MCR + * 0b0..MC has not reached its maximum value. + * 0b1..MC has reached its maximum value. + */ #define SNVS_LPSR_MCR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_MCR_SHIFT)) & SNVS_LPSR_MCR_MASK) #define SNVS_LPSR_PGD_MASK (0x8U) #define SNVS_LPSR_PGD_SHIFT (3U) #define SNVS_LPSR_PGD(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_PGD_SHIFT)) & SNVS_LPSR_PGD_MASK) #define SNVS_LPSR_ET1D_MASK (0x200U) #define SNVS_LPSR_ET1D_SHIFT (9U) +/*! ET1D + * 0b0..External tampering 1 not detected. + * 0b1..External tampering 1 detected. + */ #define SNVS_LPSR_ET1D(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_ET1D_SHIFT)) & SNVS_LPSR_ET1D_MASK) #define SNVS_LPSR_ESVD_MASK (0x10000U) #define SNVS_LPSR_ESVD_SHIFT (16U) +/*! ESVD + * 0b0..No external security violation. + * 0b1..External security violation is detected. + */ #define SNVS_LPSR_ESVD(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_ESVD_SHIFT)) & SNVS_LPSR_ESVD_MASK) #define SNVS_LPSR_EO_MASK (0x20000U) #define SNVS_LPSR_EO_SHIFT (17U) +/*! EO + * 0b0..Emergency off was not detected. + * 0b1..Emergency off was detected. + */ #define SNVS_LPSR_EO(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_EO_SHIFT)) & SNVS_LPSR_EO_MASK) #define SNVS_LPSR_SPO_MASK (0x40000U) #define SNVS_LPSR_SPO_SHIFT (18U) +/*! SPO + * 0b0..Set Power Off was not detected. + * 0b1..Set Power Off was detected. + */ #define SNVS_LPSR_SPO(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_SPO_SHIFT)) & SNVS_LPSR_SPO_MASK) #define SNVS_LPSR_SED_MASK (0x100000U) #define SNVS_LPSR_SED_SHIFT (20U) +/*! SED + * 0b0..Scan exit was not detected. + * 0b1..Scan exit was detected. + */ #define SNVS_LPSR_SED(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_SED_SHIFT)) & SNVS_LPSR_SED_MASK) #define SNVS_LPSR_LPNS_MASK (0x40000000U) #define SNVS_LPSR_LPNS_SHIFT (30U) +/*! LPNS + * 0b0..LP section was not programmed in the non-secure state. + * 0b1..LP section was programmed in the non-secure state. + */ #define SNVS_LPSR_LPNS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_LPNS_SHIFT)) & SNVS_LPSR_LPNS_MASK) #define SNVS_LPSR_LPS_MASK (0x80000000U) #define SNVS_LPSR_LPS_SHIFT (31U) +/*! LPS + * 0b0..LP section was not programmed in secure or trusted state. + * 0b1..LP section was programmed in secure or trusted state. + */ #define SNVS_LPSR_LPS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_LPS_SHIFT)) & SNVS_LPSR_LPS_MASK) +/*! @} */ /*! @name LPSRTCMR - SNVS_LP Secure Real Time Counter MSB Register */ +/*! @{ */ #define SNVS_LPSRTCMR_SRTC_MASK (0x7FFFU) #define SNVS_LPSRTCMR_SRTC_SHIFT (0U) #define SNVS_LPSRTCMR_SRTC(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSRTCMR_SRTC_SHIFT)) & SNVS_LPSRTCMR_SRTC_MASK) +/*! @} */ /*! @name LPSRTCLR - SNVS_LP Secure Real Time Counter LSB Register */ +/*! @{ */ #define SNVS_LPSRTCLR_SRTC_MASK (0xFFFFFFFFU) #define SNVS_LPSRTCLR_SRTC_SHIFT (0U) #define SNVS_LPSRTCLR_SRTC(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSRTCLR_SRTC_SHIFT)) & SNVS_LPSRTCLR_SRTC_MASK) +/*! @} */ /*! @name LPTAR - SNVS_LP Time Alarm Register */ +/*! @{ */ #define SNVS_LPTAR_LPTA_MASK (0xFFFFFFFFU) #define SNVS_LPTAR_LPTA_SHIFT (0U) #define SNVS_LPTAR_LPTA(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTAR_LPTA_SHIFT)) & SNVS_LPTAR_LPTA_MASK) +/*! @} */ /*! @name LPSMCMR - SNVS_LP Secure Monotonic Counter MSB Register */ +/*! @{ */ #define SNVS_LPSMCMR_MON_COUNTER_MASK (0xFFFFU) #define SNVS_LPSMCMR_MON_COUNTER_SHIFT (0U) #define SNVS_LPSMCMR_MON_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSMCMR_MON_COUNTER_SHIFT)) & SNVS_LPSMCMR_MON_COUNTER_MASK) #define SNVS_LPSMCMR_MC_ERA_BITS_MASK (0xFFFF0000U) #define SNVS_LPSMCMR_MC_ERA_BITS_SHIFT (16U) #define SNVS_LPSMCMR_MC_ERA_BITS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSMCMR_MC_ERA_BITS_SHIFT)) & SNVS_LPSMCMR_MC_ERA_BITS_MASK) +/*! @} */ /*! @name LPSMCLR - SNVS_LP Secure Monotonic Counter LSB Register */ +/*! @{ */ #define SNVS_LPSMCLR_MON_COUNTER_MASK (0xFFFFFFFFU) #define SNVS_LPSMCLR_MON_COUNTER_SHIFT (0U) #define SNVS_LPSMCLR_MON_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSMCLR_MON_COUNTER_SHIFT)) & SNVS_LPSMCLR_MON_COUNTER_MASK) +/*! @} */ /*! @name LPPGDR - SNVS_LP Power Glitch Detector Register */ +/*! @{ */ #define SNVS_LPPGDR_PGD_MASK (0xFFFFFFFFU) #define SNVS_LPPGDR_PGD_SHIFT (0U) #define SNVS_LPPGDR_PGD(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPPGDR_PGD_SHIFT)) & SNVS_LPPGDR_PGD_MASK) +/*! @} */ /*! @name LPGPR0_LEGACY_ALIAS - SNVS_LP General Purpose Register 0 (legacy alias) */ +/*! @{ */ #define SNVS_LPGPR0_LEGACY_ALIAS_GPR_MASK (0xFFFFFFFFU) #define SNVS_LPGPR0_LEGACY_ALIAS_GPR_SHIFT (0U) #define SNVS_LPGPR0_LEGACY_ALIAS_GPR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPGPR0_LEGACY_ALIAS_GPR_SHIFT)) & SNVS_LPGPR0_LEGACY_ALIAS_GPR_MASK) +/*! @} */ /*! @name LPZMKR - SNVS_LP Zeroizable Master Key Register */ +/*! @{ */ #define SNVS_LPZMKR_ZMK_MASK (0xFFFFFFFFU) #define SNVS_LPZMKR_ZMK_SHIFT (0U) #define SNVS_LPZMKR_ZMK(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPZMKR_ZMK_SHIFT)) & SNVS_LPZMKR_ZMK_MASK) +/*! @} */ /* The count of SNVS_LPZMKR */ #define SNVS_LPZMKR_COUNT (8U) /*! @name LPGPR_ALIAS - SNVS_LP General Purpose Registers 0 .. 3 */ +/*! @{ */ #define SNVS_LPGPR_ALIAS_GPR_MASK (0xFFFFFFFFU) #define SNVS_LPGPR_ALIAS_GPR_SHIFT (0U) #define SNVS_LPGPR_ALIAS_GPR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPGPR_ALIAS_GPR_SHIFT)) & SNVS_LPGPR_ALIAS_GPR_MASK) +/*! @} */ /* The count of SNVS_LPGPR_ALIAS */ #define SNVS_LPGPR_ALIAS_COUNT (4U) -/*! @name LPGPR - SNVS_LP General Purpose Registers 0 .. 3 */ +/*! @name LPGPR - SNVS_LP General Purpose Registers 0 .. 7 */ +/*! @{ */ #define SNVS_LPGPR_GPR_MASK (0xFFFFFFFFU) #define SNVS_LPGPR_GPR_SHIFT (0U) #define SNVS_LPGPR_GPR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPGPR_GPR_SHIFT)) & SNVS_LPGPR_GPR_MASK) +/*! @} */ /* The count of SNVS_LPGPR */ -#define SNVS_LPGPR_COUNT (4U) +#define SNVS_LPGPR_COUNT (8U) /*! @name HPVIDR1 - SNVS_HP Version ID Register 1 */ +/*! @{ */ #define SNVS_HPVIDR1_MINOR_REV_MASK (0xFFU) #define SNVS_HPVIDR1_MINOR_REV_SHIFT (0U) #define SNVS_HPVIDR1_MINOR_REV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR1_MINOR_REV_SHIFT)) & SNVS_HPVIDR1_MINOR_REV_MASK) @@ -20341,8 +33000,10 @@ typedef struct { #define SNVS_HPVIDR1_IP_ID_MASK (0xFFFF0000U) #define SNVS_HPVIDR1_IP_ID_SHIFT (16U) #define SNVS_HPVIDR1_IP_ID(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR1_IP_ID_SHIFT)) & SNVS_HPVIDR1_IP_ID_MASK) +/*! @} */ /*! @name HPVIDR2 - SNVS_HP Version ID Register 2 */ +/*! @{ */ #define SNVS_HPVIDR2_CONFIG_OPT_MASK (0xFFU) #define SNVS_HPVIDR2_CONFIG_OPT_SHIFT (0U) #define SNVS_HPVIDR2_CONFIG_OPT(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR2_CONFIG_OPT_SHIFT)) & SNVS_HPVIDR2_CONFIG_OPT_MASK) @@ -20355,6 +33016,7 @@ typedef struct { #define SNVS_HPVIDR2_IP_ERA_MASK (0xFF000000U) #define SNVS_HPVIDR2_IP_ERA_SHIFT (24U) #define SNVS_HPVIDR2_IP_ERA(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR2_IP_ERA_SHIFT)) & SNVS_HPVIDR2_IP_ERA_MASK) +/*! @} */ /*! @@ -20426,14 +33088,30 @@ typedef struct { */ /*! @name SCR - SPDIF Configuration Register */ +/*! @{ */ #define SPDIF_SCR_USRC_SEL_MASK (0x3U) #define SPDIF_SCR_USRC_SEL_SHIFT (0U) +/*! USrc_Sel + * 0b00..No embedded U channel + * 0b01..U channel from SPDIF receive block (CD mode) + * 0b10..Reserved + * 0b11..U channel from on chip transmitter + */ #define SPDIF_SCR_USRC_SEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_USRC_SEL_SHIFT)) & SPDIF_SCR_USRC_SEL_MASK) #define SPDIF_SCR_TXSEL_MASK (0x1CU) #define SPDIF_SCR_TXSEL_SHIFT (2U) +/*! TxSel + * 0b000..Off and output 0 + * 0b001..Feed-through SPDIFIN + * 0b101..Tx Normal operation + */ #define SPDIF_SCR_TXSEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_TXSEL_SHIFT)) & SPDIF_SCR_TXSEL_MASK) #define SPDIF_SCR_VALCTRL_MASK (0x20U) #define SPDIF_SCR_VALCTRL_SHIFT (5U) +/*! ValCtrl + * 0b0..Outgoing Validity always set + * 0b1..Outgoing Validity always clear + */ #define SPDIF_SCR_VALCTRL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_VALCTRL_SHIFT)) & SPDIF_SCR_VALCTRL_MASK) #define SPDIF_SCR_DMA_TX_EN_MASK (0x100U) #define SPDIF_SCR_DMA_TX_EN_SHIFT (8U) @@ -20443,6 +33121,12 @@ typedef struct { #define SPDIF_SCR_DMA_RX_EN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_DMA_RX_EN_SHIFT)) & SPDIF_SCR_DMA_RX_EN_MASK) #define SPDIF_SCR_TXFIFO_CTRL_MASK (0xC00U) #define SPDIF_SCR_TXFIFO_CTRL_SHIFT (10U) +/*! TxFIFO_Ctrl + * 0b00..Send out digital zero on SPDIF Tx + * 0b01..Tx Normal operation + * 0b10..Reset to 1 sample remaining + * 0b11..Reserved + */ #define SPDIF_SCR_TXFIFO_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_TXFIFO_CTRL_SHIFT)) & SPDIF_SCR_TXFIFO_CTRL_MASK) #define SPDIF_SCR_SOFT_RESET_MASK (0x1000U) #define SPDIF_SCR_SOFT_RESET_SHIFT (12U) @@ -20452,43 +33136,102 @@ typedef struct { #define SPDIF_SCR_LOW_POWER(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_LOW_POWER_SHIFT)) & SPDIF_SCR_LOW_POWER_MASK) #define SPDIF_SCR_TXFIFOEMPTY_SEL_MASK (0x18000U) #define SPDIF_SCR_TXFIFOEMPTY_SEL_SHIFT (15U) +/*! TxFIFOEmpty_Sel + * 0b00..Empty interrupt if 0 sample in Tx left and right FIFOs + * 0b01..Empty interrupt if at most 4 sample in Tx left and right FIFOs + * 0b10..Empty interrupt if at most 8 sample in Tx left and right FIFOs + * 0b11..Empty interrupt if at most 12 sample in Tx left and right FIFOs + */ #define SPDIF_SCR_TXFIFOEMPTY_SEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_TXFIFOEMPTY_SEL_SHIFT)) & SPDIF_SCR_TXFIFOEMPTY_SEL_MASK) #define SPDIF_SCR_TXAUTOSYNC_MASK (0x20000U) #define SPDIF_SCR_TXAUTOSYNC_SHIFT (17U) +/*! TxAutoSync + * 0b0..Tx FIFO auto sync off + * 0b1..Tx FIFO auto sync on + */ #define SPDIF_SCR_TXAUTOSYNC(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_TXAUTOSYNC_SHIFT)) & SPDIF_SCR_TXAUTOSYNC_MASK) #define SPDIF_SCR_RXAUTOSYNC_MASK (0x40000U) #define SPDIF_SCR_RXAUTOSYNC_SHIFT (18U) +/*! RxAutoSync + * 0b0..Rx FIFO auto sync off + * 0b1..RxFIFO auto sync on + */ #define SPDIF_SCR_RXAUTOSYNC(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_RXAUTOSYNC_SHIFT)) & SPDIF_SCR_RXAUTOSYNC_MASK) #define SPDIF_SCR_RXFIFOFULL_SEL_MASK (0x180000U) #define SPDIF_SCR_RXFIFOFULL_SEL_SHIFT (19U) +/*! RxFIFOFull_Sel + * 0b00..Full interrupt if at least 1 sample in Rx left and right FIFOs + * 0b01..Full interrupt if at least 4 sample in Rx left and right FIFOs + * 0b10..Full interrupt if at least 8 sample in Rx left and right FIFOs + * 0b11..Full interrupt if at least 16 sample in Rx left and right FIFO + */ #define SPDIF_SCR_RXFIFOFULL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_RXFIFOFULL_SEL_SHIFT)) & SPDIF_SCR_RXFIFOFULL_SEL_MASK) #define SPDIF_SCR_RXFIFO_RST_MASK (0x200000U) #define SPDIF_SCR_RXFIFO_RST_SHIFT (21U) +/*! RxFIFO_Rst + * 0b0..Normal operation + * 0b1..Reset register to 1 sample remaining + */ #define SPDIF_SCR_RXFIFO_RST(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_RXFIFO_RST_SHIFT)) & SPDIF_SCR_RXFIFO_RST_MASK) #define SPDIF_SCR_RXFIFO_OFF_ON_MASK (0x400000U) #define SPDIF_SCR_RXFIFO_OFF_ON_SHIFT (22U) +/*! RxFIFO_Off_On + * 0b0..SPDIF Rx FIFO is on + * 0b1..SPDIF Rx FIFO is off. Does not accept data from interface + */ #define SPDIF_SCR_RXFIFO_OFF_ON(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_RXFIFO_OFF_ON_SHIFT)) & SPDIF_SCR_RXFIFO_OFF_ON_MASK) #define SPDIF_SCR_RXFIFO_CTRL_MASK (0x800000U) #define SPDIF_SCR_RXFIFO_CTRL_SHIFT (23U) +/*! RxFIFO_Ctrl + * 0b0..Normal operation + * 0b1..Always read zero from Rx data register + */ #define SPDIF_SCR_RXFIFO_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_RXFIFO_CTRL_SHIFT)) & SPDIF_SCR_RXFIFO_CTRL_MASK) +/*! @} */ /*! @name SRCD - CDText Control Register */ +/*! @{ */ #define SPDIF_SRCD_USYNCMODE_MASK (0x2U) #define SPDIF_SRCD_USYNCMODE_SHIFT (1U) +/*! USyncMode + * 0b0..Non-CD data + * 0b1..CD user channel subcode + */ #define SPDIF_SRCD_USYNCMODE(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRCD_USYNCMODE_SHIFT)) & SPDIF_SRCD_USYNCMODE_MASK) +/*! @} */ /*! @name SRPC - PhaseConfig Register */ +/*! @{ */ #define SPDIF_SRPC_GAINSEL_MASK (0x38U) #define SPDIF_SRPC_GAINSEL_SHIFT (3U) +/*! GainSel + * 0b000..24*(2**10) + * 0b001..16*(2**10) + * 0b010..12*(2**10) + * 0b011..8*(2**10) + * 0b100..6*(2**10) + * 0b101..4*(2**10) + * 0b110..3*(2**10) + */ #define SPDIF_SRPC_GAINSEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRPC_GAINSEL_SHIFT)) & SPDIF_SRPC_GAINSEL_MASK) #define SPDIF_SRPC_LOCK_MASK (0x40U) #define SPDIF_SRPC_LOCK_SHIFT (6U) #define SPDIF_SRPC_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRPC_LOCK_SHIFT)) & SPDIF_SRPC_LOCK_MASK) #define SPDIF_SRPC_CLKSRC_SEL_MASK (0x780U) #define SPDIF_SRPC_CLKSRC_SEL_SHIFT (7U) +/*! ClkSrc_Sel + * 0b0000..if (DPLL Locked) SPDIF_RxClk else REF_CLK_32K (XTALOSC) + * 0b0001..if (DPLL Locked) SPDIF_RxClk else tx_clk (SPDIF0_CLK_ROOT) + * 0b0011..if (DPLL Locked) SPDIF_RxClk else SPDIF_EXT_CLK + * 0b0101..REF_CLK_32K (XTALOSC) + * 0b0110..tx_clk (SPDIF0_CLK_ROOT) + * 0b1000..SPDIF_EXT_CLK + */ #define SPDIF_SRPC_CLKSRC_SEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRPC_CLKSRC_SEL_SHIFT)) & SPDIF_SRPC_CLKSRC_SEL_MASK) +/*! @} */ /*! @name SIE - InterruptEn Register */ +/*! @{ */ #define SPDIF_SIE_RXFIFOFUL_MASK (0x1U) #define SPDIF_SIE_RXFIFOFUL_SHIFT (0U) #define SPDIF_SIE_RXFIFOFUL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_RXFIFOFUL_SHIFT)) & SPDIF_SIE_RXFIFOFUL_MASK) @@ -20543,8 +33286,10 @@ typedef struct { #define SPDIF_SIE_LOCK_MASK (0x100000U) #define SPDIF_SIE_LOCK_SHIFT (20U) #define SPDIF_SIE_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_LOCK_SHIFT)) & SPDIF_SIE_LOCK_MASK) +/*! @} */ /*! @name SIC - InterruptClear Register */ +/*! @{ */ #define SPDIF_SIC_LOCKLOSS_MASK (0x4U) #define SPDIF_SIC_LOCKLOSS_SHIFT (2U) #define SPDIF_SIC_LOCKLOSS(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_LOCKLOSS_SHIFT)) & SPDIF_SIC_LOCKLOSS_MASK) @@ -20587,8 +33332,10 @@ typedef struct { #define SPDIF_SIC_LOCK_MASK (0x100000U) #define SPDIF_SIC_LOCK_SHIFT (20U) #define SPDIF_SIC_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_LOCK_SHIFT)) & SPDIF_SIC_LOCK_MASK) +/*! @} */ /*! @name SIS - InterruptStat Register */ +/*! @{ */ #define SPDIF_SIS_RXFIFOFUL_MASK (0x1U) #define SPDIF_SIS_RXFIFOFUL_SHIFT (0U) #define SPDIF_SIS_RXFIFOFUL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_RXFIFOFUL_SHIFT)) & SPDIF_SIS_RXFIFOFUL_MASK) @@ -20643,75 +33390,120 @@ typedef struct { #define SPDIF_SIS_LOCK_MASK (0x100000U) #define SPDIF_SIS_LOCK_SHIFT (20U) #define SPDIF_SIS_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_LOCK_SHIFT)) & SPDIF_SIS_LOCK_MASK) +/*! @} */ /*! @name SRL - SPDIFRxLeft Register */ +/*! @{ */ #define SPDIF_SRL_RXDATALEFT_MASK (0xFFFFFFU) #define SPDIF_SRL_RXDATALEFT_SHIFT (0U) #define SPDIF_SRL_RXDATALEFT(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRL_RXDATALEFT_SHIFT)) & SPDIF_SRL_RXDATALEFT_MASK) +/*! @} */ /*! @name SRR - SPDIFRxRight Register */ +/*! @{ */ #define SPDIF_SRR_RXDATARIGHT_MASK (0xFFFFFFU) #define SPDIF_SRR_RXDATARIGHT_SHIFT (0U) #define SPDIF_SRR_RXDATARIGHT(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRR_RXDATARIGHT_SHIFT)) & SPDIF_SRR_RXDATARIGHT_MASK) +/*! @} */ /*! @name SRCSH - SPDIFRxCChannel_h Register */ +/*! @{ */ #define SPDIF_SRCSH_RXCCHANNEL_H_MASK (0xFFFFFFU) #define SPDIF_SRCSH_RXCCHANNEL_H_SHIFT (0U) #define SPDIF_SRCSH_RXCCHANNEL_H(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRCSH_RXCCHANNEL_H_SHIFT)) & SPDIF_SRCSH_RXCCHANNEL_H_MASK) +/*! @} */ /*! @name SRCSL - SPDIFRxCChannel_l Register */ +/*! @{ */ #define SPDIF_SRCSL_RXCCHANNEL_L_MASK (0xFFFFFFU) #define SPDIF_SRCSL_RXCCHANNEL_L_SHIFT (0U) #define SPDIF_SRCSL_RXCCHANNEL_L(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRCSL_RXCCHANNEL_L_SHIFT)) & SPDIF_SRCSL_RXCCHANNEL_L_MASK) +/*! @} */ /*! @name SRU - UchannelRx Register */ +/*! @{ */ #define SPDIF_SRU_RXUCHANNEL_MASK (0xFFFFFFU) #define SPDIF_SRU_RXUCHANNEL_SHIFT (0U) #define SPDIF_SRU_RXUCHANNEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRU_RXUCHANNEL_SHIFT)) & SPDIF_SRU_RXUCHANNEL_MASK) +/*! @} */ /*! @name SRQ - QchannelRx Register */ +/*! @{ */ #define SPDIF_SRQ_RXQCHANNEL_MASK (0xFFFFFFU) #define SPDIF_SRQ_RXQCHANNEL_SHIFT (0U) #define SPDIF_SRQ_RXQCHANNEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRQ_RXQCHANNEL_SHIFT)) & SPDIF_SRQ_RXQCHANNEL_MASK) +/*! @} */ /*! @name STL - SPDIFTxLeft Register */ +/*! @{ */ #define SPDIF_STL_TXDATALEFT_MASK (0xFFFFFFU) #define SPDIF_STL_TXDATALEFT_SHIFT (0U) #define SPDIF_STL_TXDATALEFT(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STL_TXDATALEFT_SHIFT)) & SPDIF_STL_TXDATALEFT_MASK) +/*! @} */ /*! @name STR - SPDIFTxRight Register */ +/*! @{ */ #define SPDIF_STR_TXDATARIGHT_MASK (0xFFFFFFU) #define SPDIF_STR_TXDATARIGHT_SHIFT (0U) #define SPDIF_STR_TXDATARIGHT(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STR_TXDATARIGHT_SHIFT)) & SPDIF_STR_TXDATARIGHT_MASK) +/*! @} */ /*! @name STCSCH - SPDIFTxCChannelCons_h Register */ +/*! @{ */ #define SPDIF_STCSCH_TXCCHANNELCONS_H_MASK (0xFFFFFFU) #define SPDIF_STCSCH_TXCCHANNELCONS_H_SHIFT (0U) #define SPDIF_STCSCH_TXCCHANNELCONS_H(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STCSCH_TXCCHANNELCONS_H_SHIFT)) & SPDIF_STCSCH_TXCCHANNELCONS_H_MASK) +/*! @} */ /*! @name STCSCL - SPDIFTxCChannelCons_l Register */ +/*! @{ */ #define SPDIF_STCSCL_TXCCHANNELCONS_L_MASK (0xFFFFFFU) #define SPDIF_STCSCL_TXCCHANNELCONS_L_SHIFT (0U) #define SPDIF_STCSCL_TXCCHANNELCONS_L(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STCSCL_TXCCHANNELCONS_L_SHIFT)) & SPDIF_STCSCL_TXCCHANNELCONS_L_MASK) +/*! @} */ /*! @name SRFM - FreqMeas Register */ +/*! @{ */ #define SPDIF_SRFM_FREQMEAS_MASK (0xFFFFFFU) #define SPDIF_SRFM_FREQMEAS_SHIFT (0U) #define SPDIF_SRFM_FREQMEAS(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRFM_FREQMEAS_SHIFT)) & SPDIF_SRFM_FREQMEAS_MASK) +/*! @} */ /*! @name STC - SPDIFTxClk Register */ +/*! @{ */ #define SPDIF_STC_TXCLK_DF_MASK (0x7FU) #define SPDIF_STC_TXCLK_DF_SHIFT (0U) +/*! TxClk_DF + * 0b0000000..divider factor is 1 + * 0b0000001..divider factor is 2 + * 0b1111111..divider factor is 128 + */ #define SPDIF_STC_TXCLK_DF(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STC_TXCLK_DF_SHIFT)) & SPDIF_STC_TXCLK_DF_MASK) #define SPDIF_STC_TX_ALL_CLK_EN_MASK (0x80U) #define SPDIF_STC_TX_ALL_CLK_EN_SHIFT (7U) +/*! tx_all_clk_en + * 0b0..disable transfer clock. + * 0b1..enable transfer clock. + */ #define SPDIF_STC_TX_ALL_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STC_TX_ALL_CLK_EN_SHIFT)) & SPDIF_STC_TX_ALL_CLK_EN_MASK) #define SPDIF_STC_TXCLK_SOURCE_MASK (0x700U) #define SPDIF_STC_TXCLK_SOURCE_SHIFT (8U) +/*! TxClk_Source + * 0b000..REF_CLK_32K input (XTALOSC 32 kHz clock) + * 0b001..tx_clk input (from SPDIF0_CLK_ROOT. See CCM.) + * 0b011..SPDIF_EXT_CLK, from pads + * 0b101..ipg_clk input (frequency divided) + */ #define SPDIF_STC_TXCLK_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STC_TXCLK_SOURCE_SHIFT)) & SPDIF_STC_TXCLK_SOURCE_MASK) #define SPDIF_STC_SYSCLK_DF_MASK (0xFF800U) #define SPDIF_STC_SYSCLK_DF_SHIFT (11U) +/*! SYSCLK_DF + * 0b000000000..no clock signal + * 0b000000001..divider factor is 2 + * 0b111111111..divider factor is 512 + */ #define SPDIF_STC_SYSCLK_DF(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STC_SYSCLK_DF_SHIFT)) & SPDIF_STC_SYSCLK_DF_MASK) +/*! @} */ /*! @@ -20765,26 +33557,46 @@ typedef struct { */ /*! @name SCR - SRC Control Register */ -#define SRC_SCR_LOCKUP_RST_MASK (0x10U) -#define SRC_SCR_LOCKUP_RST_SHIFT (4U) -#define SRC_SCR_LOCKUP_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_LOCKUP_RST_SHIFT)) & SRC_SCR_LOCKUP_RST_MASK) +/*! @{ */ #define SRC_SCR_MASK_WDOG_RST_MASK (0x780U) #define SRC_SCR_MASK_WDOG_RST_SHIFT (7U) +/*! mask_wdog_rst + * 0b0101..wdog_rst_b is masked + * 0b1010..wdog_rst_b is not masked (default) + */ #define SRC_SCR_MASK_WDOG_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_MASK_WDOG_RST_SHIFT)) & SRC_SCR_MASK_WDOG_RST_MASK) #define SRC_SCR_CORE0_RST_MASK (0x2000U) #define SRC_SCR_CORE0_RST_SHIFT (13U) +/*! core0_rst + * 0b0..do not assert core0 reset + * 0b1..assert core0 reset + */ #define SRC_SCR_CORE0_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_CORE0_RST_SHIFT)) & SRC_SCR_CORE0_RST_MASK) #define SRC_SCR_CORE0_DBG_RST_MASK (0x20000U) #define SRC_SCR_CORE0_DBG_RST_SHIFT (17U) +/*! core0_dbg_rst + * 0b0..do not assert core0 debug reset + * 0b1..assert core0 debug reset + */ #define SRC_SCR_CORE0_DBG_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_CORE0_DBG_RST_SHIFT)) & SRC_SCR_CORE0_DBG_RST_MASK) #define SRC_SCR_DBG_RST_MSK_PG_MASK (0x2000000U) #define SRC_SCR_DBG_RST_MSK_PG_SHIFT (25U) +/*! dbg_rst_msk_pg + * 0b0..do not mask core debug resets (debug resets will be asserted after power gating event) + * 0b1..mask core debug resets (debug resets won't be asserted after power gating event) + */ #define SRC_SCR_DBG_RST_MSK_PG(x) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_DBG_RST_MSK_PG_SHIFT)) & SRC_SCR_DBG_RST_MSK_PG_MASK) #define SRC_SCR_MASK_WDOG3_RST_MASK (0xF0000000U) #define SRC_SCR_MASK_WDOG3_RST_SHIFT (28U) +/*! mask_wdog3_rst + * 0b0101..wdog3_rst_b is masked + * 0b1010..wdog3_rst_b is not masked + */ #define SRC_SCR_MASK_WDOG3_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_MASK_WDOG3_RST_SHIFT)) & SRC_SCR_MASK_WDOG3_RST_MASK) +/*! @} */ /*! @name SBMR1 - SRC Boot Mode Register 1 */ +/*! @{ */ #define SRC_SBMR1_BOOT_CFG1_MASK (0xFFU) #define SRC_SBMR1_BOOT_CFG1_SHIFT (0U) #define SRC_SBMR1_BOOT_CFG1(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR1_BOOT_CFG1_SHIFT)) & SRC_SBMR1_BOOT_CFG1_MASK) @@ -20797,37 +33609,77 @@ typedef struct { #define SRC_SBMR1_BOOT_CFG4_MASK (0xFF000000U) #define SRC_SBMR1_BOOT_CFG4_SHIFT (24U) #define SRC_SBMR1_BOOT_CFG4(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR1_BOOT_CFG4_SHIFT)) & SRC_SBMR1_BOOT_CFG4_MASK) +/*! @} */ /*! @name SRSR - SRC Reset Status Register */ +/*! @{ */ #define SRC_SRSR_IPP_RESET_B_MASK (0x1U) #define SRC_SRSR_IPP_RESET_B_SHIFT (0U) +/*! ipp_reset_b + * 0b0..Reset is not a result of ipp_reset_b pin. + * 0b1..Reset is a result of ipp_reset_b pin. + */ #define SRC_SRSR_IPP_RESET_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_IPP_RESET_B_SHIFT)) & SRC_SRSR_IPP_RESET_B_MASK) #define SRC_SRSR_LOCKUP_SYSRESETREQ_MASK (0x2U) #define SRC_SRSR_LOCKUP_SYSRESETREQ_SHIFT (1U) +/*! lockup_sysresetreq + * 0b0..Reset is not a result of the mentioned case. + * 0b1..Reset is a result of the mentioned case. + */ #define SRC_SRSR_LOCKUP_SYSRESETREQ(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_LOCKUP_SYSRESETREQ_SHIFT)) & SRC_SRSR_LOCKUP_SYSRESETREQ_MASK) #define SRC_SRSR_CSU_RESET_B_MASK (0x4U) #define SRC_SRSR_CSU_RESET_B_SHIFT (2U) +/*! csu_reset_b + * 0b0..Reset is not a result of the csu_reset_b event. + * 0b1..Reset is a result of the csu_reset_b event. + */ #define SRC_SRSR_CSU_RESET_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_CSU_RESET_B_SHIFT)) & SRC_SRSR_CSU_RESET_B_MASK) #define SRC_SRSR_IPP_USER_RESET_B_MASK (0x8U) #define SRC_SRSR_IPP_USER_RESET_B_SHIFT (3U) +/*! ipp_user_reset_b + * 0b0..Reset is not a result of the ipp_user_reset_b qualified as COLD reset event. + * 0b1..Reset is a result of the ipp_user_reset_b qualified as COLD reset event. + */ #define SRC_SRSR_IPP_USER_RESET_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_IPP_USER_RESET_B_SHIFT)) & SRC_SRSR_IPP_USER_RESET_B_MASK) #define SRC_SRSR_WDOG_RST_B_MASK (0x10U) #define SRC_SRSR_WDOG_RST_B_SHIFT (4U) +/*! wdog_rst_b + * 0b0..Reset is not a result of the watchdog time-out event. + * 0b1..Reset is a result of the watchdog time-out event. + */ #define SRC_SRSR_WDOG_RST_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_WDOG_RST_B_SHIFT)) & SRC_SRSR_WDOG_RST_B_MASK) #define SRC_SRSR_JTAG_RST_B_MASK (0x20U) #define SRC_SRSR_JTAG_RST_B_SHIFT (5U) +/*! jtag_rst_b + * 0b0..Reset is not a result of HIGH-Z reset from JTAG. + * 0b1..Reset is a result of HIGH-Z reset from JTAG. + */ #define SRC_SRSR_JTAG_RST_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_JTAG_RST_B_SHIFT)) & SRC_SRSR_JTAG_RST_B_MASK) #define SRC_SRSR_JTAG_SW_RST_MASK (0x40U) #define SRC_SRSR_JTAG_SW_RST_SHIFT (6U) +/*! jtag_sw_rst + * 0b0..Reset is not a result of software reset from JTAG. + * 0b1..Reset is a result of software reset from JTAG. + */ #define SRC_SRSR_JTAG_SW_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_JTAG_SW_RST_SHIFT)) & SRC_SRSR_JTAG_SW_RST_MASK) #define SRC_SRSR_WDOG3_RST_B_MASK (0x80U) #define SRC_SRSR_WDOG3_RST_B_SHIFT (7U) +/*! wdog3_rst_b + * 0b0..Reset is not a result of the watchdog3 time-out event. + * 0b1..Reset is a result of the watchdog3 time-out event. + */ #define SRC_SRSR_WDOG3_RST_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_WDOG3_RST_B_SHIFT)) & SRC_SRSR_WDOG3_RST_B_MASK) #define SRC_SRSR_TEMPSENSE_RST_B_MASK (0x100U) #define SRC_SRSR_TEMPSENSE_RST_B_SHIFT (8U) +/*! tempsense_rst_b + * 0b0..Reset is not a result of software reset from Temperature Sensor. + * 0b1..Reset is a result of software reset from Temperature Sensor. + */ #define SRC_SRSR_TEMPSENSE_RST_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_TEMPSENSE_RST_B_SHIFT)) & SRC_SRSR_TEMPSENSE_RST_B_MASK) +/*! @} */ /*! @name SBMR2 - SRC Boot Mode Register 2 */ +/*! @{ */ #define SRC_SBMR2_SEC_CONFIG_MASK (0x3U) #define SRC_SBMR2_SEC_CONFIG_SHIFT (0U) #define SRC_SBMR2_SEC_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR2_SEC_CONFIG_SHIFT)) & SRC_SBMR2_SEC_CONFIG_MASK) @@ -20840,14 +33692,17 @@ typedef struct { #define SRC_SBMR2_BMOD_MASK (0x3000000U) #define SRC_SBMR2_BMOD_SHIFT (24U) #define SRC_SBMR2_BMOD(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR2_BMOD_SHIFT)) & SRC_SBMR2_BMOD_MASK) +/*! @} */ /*! @name GPR - SRC General Purpose Register 1..SRC General Purpose Register 10 */ -#define SRC_GPR_PERSISTENT_ENTRY0_MASK (0xFFFFFFFFU) -#define SRC_GPR_PERSISTENT_ENTRY0_SHIFT (0U) -#define SRC_GPR_PERSISTENT_ENTRY0(x) (((uint32_t)(((uint32_t)(x)) << SRC_GPR_PERSISTENT_ENTRY0_SHIFT)) & SRC_GPR_PERSISTENT_ENTRY0_MASK) +/*! @{ */ #define SRC_GPR_PERSISTENT_ARG0_MASK (0xFFFFFFFFU) #define SRC_GPR_PERSISTENT_ARG0_SHIFT (0U) #define SRC_GPR_PERSISTENT_ARG0(x) (((uint32_t)(((uint32_t)(x)) << SRC_GPR_PERSISTENT_ARG0_SHIFT)) & SRC_GPR_PERSISTENT_ARG0_MASK) +#define SRC_GPR_PERSISTENT_ENTRY0_MASK (0xFFFFFFFFU) +#define SRC_GPR_PERSISTENT_ENTRY0_SHIFT (0U) +#define SRC_GPR_PERSISTENT_ENTRY0(x) (((uint32_t)(((uint32_t)(x)) << SRC_GPR_PERSISTENT_ENTRY0_SHIFT)) & SRC_GPR_PERSISTENT_ENTRY0_MASK) +/*! @} */ /* The count of SRC_GPR */ #define SRC_GPR_COUNT (10U) @@ -20938,14 +33793,27 @@ typedef struct { */ /*! @name TEMPSENSE0 - Tempsensor Control Register 0 */ +/*! @{ */ #define TEMPMON_TEMPSENSE0_POWER_DOWN_MASK (0x1U) #define TEMPMON_TEMPSENSE0_POWER_DOWN_SHIFT (0U) +/*! POWER_DOWN + * 0b0..Enable power to the temperature sensor. + * 0b1..Power down the temperature sensor. + */ #define TEMPMON_TEMPSENSE0_POWER_DOWN(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_POWER_DOWN_SHIFT)) & TEMPMON_TEMPSENSE0_POWER_DOWN_MASK) #define TEMPMON_TEMPSENSE0_MEASURE_TEMP_MASK (0x2U) #define TEMPMON_TEMPSENSE0_MEASURE_TEMP_SHIFT (1U) +/*! MEASURE_TEMP + * 0b0..Do not start the measurement process. + * 0b1..Start the measurement process. + */ #define TEMPMON_TEMPSENSE0_MEASURE_TEMP(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_MEASURE_TEMP_SHIFT)) & TEMPMON_TEMPSENSE0_MEASURE_TEMP_MASK) #define TEMPMON_TEMPSENSE0_FINISHED_MASK (0x4U) #define TEMPMON_TEMPSENSE0_FINISHED_SHIFT (2U) +/*! FINISHED + * 0b0..Last measurement is not ready yet. + * 0b1..Last measurement is valid. + */ #define TEMPMON_TEMPSENSE0_FINISHED(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_FINISHED_SHIFT)) & TEMPMON_TEMPSENSE0_FINISHED_MASK) #define TEMPMON_TEMPSENSE0_TEMP_CNT_MASK (0xFFF00U) #define TEMPMON_TEMPSENSE0_TEMP_CNT_SHIFT (8U) @@ -20953,16 +33821,30 @@ typedef struct { #define TEMPMON_TEMPSENSE0_ALARM_VALUE_MASK (0xFFF00000U) #define TEMPMON_TEMPSENSE0_ALARM_VALUE_SHIFT (20U) #define TEMPMON_TEMPSENSE0_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE0_ALARM_VALUE_MASK) +/*! @} */ /*! @name TEMPSENSE0_SET - Tempsensor Control Register 0 */ +/*! @{ */ #define TEMPMON_TEMPSENSE0_SET_POWER_DOWN_MASK (0x1U) #define TEMPMON_TEMPSENSE0_SET_POWER_DOWN_SHIFT (0U) +/*! POWER_DOWN + * 0b0..Enable power to the temperature sensor. + * 0b1..Power down the temperature sensor. + */ #define TEMPMON_TEMPSENSE0_SET_POWER_DOWN(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_SET_POWER_DOWN_SHIFT)) & TEMPMON_TEMPSENSE0_SET_POWER_DOWN_MASK) #define TEMPMON_TEMPSENSE0_SET_MEASURE_TEMP_MASK (0x2U) #define TEMPMON_TEMPSENSE0_SET_MEASURE_TEMP_SHIFT (1U) +/*! MEASURE_TEMP + * 0b0..Do not start the measurement process. + * 0b1..Start the measurement process. + */ #define TEMPMON_TEMPSENSE0_SET_MEASURE_TEMP(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_SET_MEASURE_TEMP_SHIFT)) & TEMPMON_TEMPSENSE0_SET_MEASURE_TEMP_MASK) #define TEMPMON_TEMPSENSE0_SET_FINISHED_MASK (0x4U) #define TEMPMON_TEMPSENSE0_SET_FINISHED_SHIFT (2U) +/*! FINISHED + * 0b0..Last measurement is not ready yet. + * 0b1..Last measurement is valid. + */ #define TEMPMON_TEMPSENSE0_SET_FINISHED(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_SET_FINISHED_SHIFT)) & TEMPMON_TEMPSENSE0_SET_FINISHED_MASK) #define TEMPMON_TEMPSENSE0_SET_TEMP_CNT_MASK (0xFFF00U) #define TEMPMON_TEMPSENSE0_SET_TEMP_CNT_SHIFT (8U) @@ -20970,16 +33852,30 @@ typedef struct { #define TEMPMON_TEMPSENSE0_SET_ALARM_VALUE_MASK (0xFFF00000U) #define TEMPMON_TEMPSENSE0_SET_ALARM_VALUE_SHIFT (20U) #define TEMPMON_TEMPSENSE0_SET_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_SET_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE0_SET_ALARM_VALUE_MASK) +/*! @} */ /*! @name TEMPSENSE0_CLR - Tempsensor Control Register 0 */ +/*! @{ */ #define TEMPMON_TEMPSENSE0_CLR_POWER_DOWN_MASK (0x1U) #define TEMPMON_TEMPSENSE0_CLR_POWER_DOWN_SHIFT (0U) +/*! POWER_DOWN + * 0b0..Enable power to the temperature sensor. + * 0b1..Power down the temperature sensor. + */ #define TEMPMON_TEMPSENSE0_CLR_POWER_DOWN(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_CLR_POWER_DOWN_SHIFT)) & TEMPMON_TEMPSENSE0_CLR_POWER_DOWN_MASK) #define TEMPMON_TEMPSENSE0_CLR_MEASURE_TEMP_MASK (0x2U) #define TEMPMON_TEMPSENSE0_CLR_MEASURE_TEMP_SHIFT (1U) +/*! MEASURE_TEMP + * 0b0..Do not start the measurement process. + * 0b1..Start the measurement process. + */ #define TEMPMON_TEMPSENSE0_CLR_MEASURE_TEMP(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_CLR_MEASURE_TEMP_SHIFT)) & TEMPMON_TEMPSENSE0_CLR_MEASURE_TEMP_MASK) #define TEMPMON_TEMPSENSE0_CLR_FINISHED_MASK (0x4U) #define TEMPMON_TEMPSENSE0_CLR_FINISHED_SHIFT (2U) +/*! FINISHED + * 0b0..Last measurement is not ready yet. + * 0b1..Last measurement is valid. + */ #define TEMPMON_TEMPSENSE0_CLR_FINISHED(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_CLR_FINISHED_SHIFT)) & TEMPMON_TEMPSENSE0_CLR_FINISHED_MASK) #define TEMPMON_TEMPSENSE0_CLR_TEMP_CNT_MASK (0xFFF00U) #define TEMPMON_TEMPSENSE0_CLR_TEMP_CNT_SHIFT (8U) @@ -20987,16 +33883,30 @@ typedef struct { #define TEMPMON_TEMPSENSE0_CLR_ALARM_VALUE_MASK (0xFFF00000U) #define TEMPMON_TEMPSENSE0_CLR_ALARM_VALUE_SHIFT (20U) #define TEMPMON_TEMPSENSE0_CLR_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_CLR_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE0_CLR_ALARM_VALUE_MASK) +/*! @} */ /*! @name TEMPSENSE0_TOG - Tempsensor Control Register 0 */ +/*! @{ */ #define TEMPMON_TEMPSENSE0_TOG_POWER_DOWN_MASK (0x1U) #define TEMPMON_TEMPSENSE0_TOG_POWER_DOWN_SHIFT (0U) +/*! POWER_DOWN + * 0b0..Enable power to the temperature sensor. + * 0b1..Power down the temperature sensor. + */ #define TEMPMON_TEMPSENSE0_TOG_POWER_DOWN(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_TOG_POWER_DOWN_SHIFT)) & TEMPMON_TEMPSENSE0_TOG_POWER_DOWN_MASK) #define TEMPMON_TEMPSENSE0_TOG_MEASURE_TEMP_MASK (0x2U) #define TEMPMON_TEMPSENSE0_TOG_MEASURE_TEMP_SHIFT (1U) +/*! MEASURE_TEMP + * 0b0..Do not start the measurement process. + * 0b1..Start the measurement process. + */ #define TEMPMON_TEMPSENSE0_TOG_MEASURE_TEMP(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_TOG_MEASURE_TEMP_SHIFT)) & TEMPMON_TEMPSENSE0_TOG_MEASURE_TEMP_MASK) #define TEMPMON_TEMPSENSE0_TOG_FINISHED_MASK (0x4U) #define TEMPMON_TEMPSENSE0_TOG_FINISHED_SHIFT (2U) +/*! FINISHED + * 0b0..Last measurement is not ready yet. + * 0b1..Last measurement is valid. + */ #define TEMPMON_TEMPSENSE0_TOG_FINISHED(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_TOG_FINISHED_SHIFT)) & TEMPMON_TEMPSENSE0_TOG_FINISHED_MASK) #define TEMPMON_TEMPSENSE0_TOG_TEMP_CNT_MASK (0xFFF00U) #define TEMPMON_TEMPSENSE0_TOG_TEMP_CNT_SHIFT (8U) @@ -21004,58 +33914,75 @@ typedef struct { #define TEMPMON_TEMPSENSE0_TOG_ALARM_VALUE_MASK (0xFFF00000U) #define TEMPMON_TEMPSENSE0_TOG_ALARM_VALUE_SHIFT (20U) #define TEMPMON_TEMPSENSE0_TOG_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_TOG_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE0_TOG_ALARM_VALUE_MASK) +/*! @} */ /*! @name TEMPSENSE1 - Tempsensor Control Register 1 */ +/*! @{ */ #define TEMPMON_TEMPSENSE1_MEASURE_FREQ_MASK (0xFFFFU) #define TEMPMON_TEMPSENSE1_MEASURE_FREQ_SHIFT (0U) #define TEMPMON_TEMPSENSE1_MEASURE_FREQ(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE1_MEASURE_FREQ_SHIFT)) & TEMPMON_TEMPSENSE1_MEASURE_FREQ_MASK) +/*! @} */ /*! @name TEMPSENSE1_SET - Tempsensor Control Register 1 */ +/*! @{ */ #define TEMPMON_TEMPSENSE1_SET_MEASURE_FREQ_MASK (0xFFFFU) #define TEMPMON_TEMPSENSE1_SET_MEASURE_FREQ_SHIFT (0U) #define TEMPMON_TEMPSENSE1_SET_MEASURE_FREQ(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE1_SET_MEASURE_FREQ_SHIFT)) & TEMPMON_TEMPSENSE1_SET_MEASURE_FREQ_MASK) +/*! @} */ /*! @name TEMPSENSE1_CLR - Tempsensor Control Register 1 */ +/*! @{ */ #define TEMPMON_TEMPSENSE1_CLR_MEASURE_FREQ_MASK (0xFFFFU) #define TEMPMON_TEMPSENSE1_CLR_MEASURE_FREQ_SHIFT (0U) #define TEMPMON_TEMPSENSE1_CLR_MEASURE_FREQ(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE1_CLR_MEASURE_FREQ_SHIFT)) & TEMPMON_TEMPSENSE1_CLR_MEASURE_FREQ_MASK) +/*! @} */ /*! @name TEMPSENSE1_TOG - Tempsensor Control Register 1 */ +/*! @{ */ #define TEMPMON_TEMPSENSE1_TOG_MEASURE_FREQ_MASK (0xFFFFU) #define TEMPMON_TEMPSENSE1_TOG_MEASURE_FREQ_SHIFT (0U) #define TEMPMON_TEMPSENSE1_TOG_MEASURE_FREQ(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE1_TOG_MEASURE_FREQ_SHIFT)) & TEMPMON_TEMPSENSE1_TOG_MEASURE_FREQ_MASK) +/*! @} */ /*! @name TEMPSENSE2 - Tempsensor Control Register 2 */ +/*! @{ */ #define TEMPMON_TEMPSENSE2_LOW_ALARM_VALUE_MASK (0xFFFU) #define TEMPMON_TEMPSENSE2_LOW_ALARM_VALUE_SHIFT (0U) #define TEMPMON_TEMPSENSE2_LOW_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE2_LOW_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE2_LOW_ALARM_VALUE_MASK) #define TEMPMON_TEMPSENSE2_PANIC_ALARM_VALUE_MASK (0xFFF0000U) #define TEMPMON_TEMPSENSE2_PANIC_ALARM_VALUE_SHIFT (16U) #define TEMPMON_TEMPSENSE2_PANIC_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE2_PANIC_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE2_PANIC_ALARM_VALUE_MASK) +/*! @} */ /*! @name TEMPSENSE2_SET - Tempsensor Control Register 2 */ +/*! @{ */ #define TEMPMON_TEMPSENSE2_SET_LOW_ALARM_VALUE_MASK (0xFFFU) #define TEMPMON_TEMPSENSE2_SET_LOW_ALARM_VALUE_SHIFT (0U) #define TEMPMON_TEMPSENSE2_SET_LOW_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE2_SET_LOW_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE2_SET_LOW_ALARM_VALUE_MASK) #define TEMPMON_TEMPSENSE2_SET_PANIC_ALARM_VALUE_MASK (0xFFF0000U) #define TEMPMON_TEMPSENSE2_SET_PANIC_ALARM_VALUE_SHIFT (16U) #define TEMPMON_TEMPSENSE2_SET_PANIC_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE2_SET_PANIC_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE2_SET_PANIC_ALARM_VALUE_MASK) +/*! @} */ /*! @name TEMPSENSE2_CLR - Tempsensor Control Register 2 */ +/*! @{ */ #define TEMPMON_TEMPSENSE2_CLR_LOW_ALARM_VALUE_MASK (0xFFFU) #define TEMPMON_TEMPSENSE2_CLR_LOW_ALARM_VALUE_SHIFT (0U) #define TEMPMON_TEMPSENSE2_CLR_LOW_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE2_CLR_LOW_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE2_CLR_LOW_ALARM_VALUE_MASK) #define TEMPMON_TEMPSENSE2_CLR_PANIC_ALARM_VALUE_MASK (0xFFF0000U) #define TEMPMON_TEMPSENSE2_CLR_PANIC_ALARM_VALUE_SHIFT (16U) #define TEMPMON_TEMPSENSE2_CLR_PANIC_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE2_CLR_PANIC_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE2_CLR_PANIC_ALARM_VALUE_MASK) +/*! @} */ /*! @name TEMPSENSE2_TOG - Tempsensor Control Register 2 */ +/*! @{ */ #define TEMPMON_TEMPSENSE2_TOG_LOW_ALARM_VALUE_MASK (0xFFFU) #define TEMPMON_TEMPSENSE2_TOG_LOW_ALARM_VALUE_SHIFT (0U) #define TEMPMON_TEMPSENSE2_TOG_LOW_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE2_TOG_LOW_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE2_TOG_LOW_ALARM_VALUE_MASK) #define TEMPMON_TEMPSENSE2_TOG_PANIC_ALARM_VALUE_MASK (0xFFF0000U) #define TEMPMON_TEMPSENSE2_TOG_PANIC_ALARM_VALUE_SHIFT (16U) #define TEMPMON_TEMPSENSE2_TOG_PANIC_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE2_TOG_PANIC_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE2_TOG_PANIC_ALARM_VALUE_MASK) +/*! @} */ /*! @@ -21118,88 +34045,171 @@ typedef struct { */ /*! @name COMP1 - Timer Channel Compare Register 1 */ +/*! @{ */ #define TMR_COMP1_COMPARISON_1_MASK (0xFFFFU) #define TMR_COMP1_COMPARISON_1_SHIFT (0U) #define TMR_COMP1_COMPARISON_1(x) (((uint16_t)(((uint16_t)(x)) << TMR_COMP1_COMPARISON_1_SHIFT)) & TMR_COMP1_COMPARISON_1_MASK) +/*! @} */ /* The count of TMR_COMP1 */ #define TMR_COMP1_COUNT (4U) /*! @name COMP2 - Timer Channel Compare Register 2 */ +/*! @{ */ #define TMR_COMP2_COMPARISON_2_MASK (0xFFFFU) #define TMR_COMP2_COMPARISON_2_SHIFT (0U) #define TMR_COMP2_COMPARISON_2(x) (((uint16_t)(((uint16_t)(x)) << TMR_COMP2_COMPARISON_2_SHIFT)) & TMR_COMP2_COMPARISON_2_MASK) +/*! @} */ /* The count of TMR_COMP2 */ #define TMR_COMP2_COUNT (4U) /*! @name CAPT - Timer Channel Capture Register */ +/*! @{ */ #define TMR_CAPT_CAPTURE_MASK (0xFFFFU) #define TMR_CAPT_CAPTURE_SHIFT (0U) #define TMR_CAPT_CAPTURE(x) (((uint16_t)(((uint16_t)(x)) << TMR_CAPT_CAPTURE_SHIFT)) & TMR_CAPT_CAPTURE_MASK) +/*! @} */ /* The count of TMR_CAPT */ #define TMR_CAPT_COUNT (4U) /*! @name LOAD - Timer Channel Load Register */ +/*! @{ */ #define TMR_LOAD_LOAD_MASK (0xFFFFU) #define TMR_LOAD_LOAD_SHIFT (0U) #define TMR_LOAD_LOAD(x) (((uint16_t)(((uint16_t)(x)) << TMR_LOAD_LOAD_SHIFT)) & TMR_LOAD_LOAD_MASK) +/*! @} */ /* The count of TMR_LOAD */ #define TMR_LOAD_COUNT (4U) /*! @name HOLD - Timer Channel Hold Register */ +/*! @{ */ #define TMR_HOLD_HOLD_MASK (0xFFFFU) #define TMR_HOLD_HOLD_SHIFT (0U) #define TMR_HOLD_HOLD(x) (((uint16_t)(((uint16_t)(x)) << TMR_HOLD_HOLD_SHIFT)) & TMR_HOLD_HOLD_MASK) +/*! @} */ /* The count of TMR_HOLD */ #define TMR_HOLD_COUNT (4U) /*! @name CNTR - Timer Channel Counter Register */ +/*! @{ */ #define TMR_CNTR_COUNTER_MASK (0xFFFFU) #define TMR_CNTR_COUNTER_SHIFT (0U) #define TMR_CNTR_COUNTER(x) (((uint16_t)(((uint16_t)(x)) << TMR_CNTR_COUNTER_SHIFT)) & TMR_CNTR_COUNTER_MASK) +/*! @} */ /* The count of TMR_CNTR */ #define TMR_CNTR_COUNT (4U) /*! @name CTRL - Timer Channel Control Register */ +/*! @{ */ #define TMR_CTRL_OUTMODE_MASK (0x7U) #define TMR_CTRL_OUTMODE_SHIFT (0U) +/*! OUTMODE - Output Mode + * 0b000..Asserted while counter is active + * 0b001..Clear OFLAG output on successful compare + * 0b010..Set OFLAG output on successful compare + * 0b011..Toggle OFLAG output on successful compare + * 0b100..Toggle OFLAG output using alternating compare registers + * 0b101..Set on compare, cleared on secondary source input edge + * 0b110..Set on compare, cleared on counter rollover + * 0b111..Enable gated clock output while counter is active + */ #define TMR_CTRL_OUTMODE(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_OUTMODE_SHIFT)) & TMR_CTRL_OUTMODE_MASK) #define TMR_CTRL_COINIT_MASK (0x8U) #define TMR_CTRL_COINIT_SHIFT (3U) +/*! COINIT - Co-Channel Initialization + * 0b0..Co-channel counter/timers cannot force a re-initialization of this counter/timer + * 0b1..Co-channel counter/timers may force a re-initialization of this counter/timer + */ #define TMR_CTRL_COINIT(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_COINIT_SHIFT)) & TMR_CTRL_COINIT_MASK) #define TMR_CTRL_DIR_MASK (0x10U) #define TMR_CTRL_DIR_SHIFT (4U) +/*! DIR - Count Direction + * 0b0..Count up. + * 0b1..Count down. + */ #define TMR_CTRL_DIR(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_DIR_SHIFT)) & TMR_CTRL_DIR_MASK) #define TMR_CTRL_LENGTH_MASK (0x20U) #define TMR_CTRL_LENGTH_SHIFT (5U) +/*! LENGTH - Count Length + * 0b0..Count until roll over at $FFFF and continue from $0000. + * 0b1..Count until compare, then re-initialize. If counting up, a successful compare occurs when the counter reaches a COMP1 value. If counting down, a successful compare occurs when the counter reaches a COMP2 value. When output mode $4 is used, alternating values of COMP1 and COMP2 are used to generate successful comparisons. For example, the counter counts until a COMP1 value is reached, re-initializes, counts until COMP2 value is reached, re-initializes, counts until COMP1 value is reached, and so on. + */ #define TMR_CTRL_LENGTH(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_LENGTH_SHIFT)) & TMR_CTRL_LENGTH_MASK) #define TMR_CTRL_ONCE_MASK (0x40U) #define TMR_CTRL_ONCE_SHIFT (6U) +/*! ONCE - Count Once + * 0b0..Count repeatedly. + * 0b1..Count until compare and then stop. If counting up, a successful compare occurs when the counter reaches a COMP1 value. If counting down, a successful compare occurs when the counter reaches a COMP2 value. When output mode $4 is used, the counter re-initializes after reaching the COMP1 value, continues to count to the COMP2 value, and then stops. + */ #define TMR_CTRL_ONCE(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_ONCE_SHIFT)) & TMR_CTRL_ONCE_MASK) #define TMR_CTRL_SCS_MASK (0x180U) #define TMR_CTRL_SCS_SHIFT (7U) +/*! SCS - Secondary Count Source + * 0b00..Counter 0 input pin + * 0b01..Counter 1 input pin + * 0b10..Counter 2 input pin + * 0b11..Counter 3 input pin + */ #define TMR_CTRL_SCS(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_SCS_SHIFT)) & TMR_CTRL_SCS_MASK) #define TMR_CTRL_PCS_MASK (0x1E00U) #define TMR_CTRL_PCS_SHIFT (9U) +/*! PCS - Primary Count Source + * 0b0000..Counter 0 input pin + * 0b0001..Counter 1 input pin + * 0b0010..Counter 2 input pin + * 0b0011..Counter 3 input pin + * 0b0100..Counter 0 output + * 0b0101..Counter 1 output + * 0b0110..Counter 2 output + * 0b0111..Counter 3 output + * 0b1000..IP bus clock divide by 1 prescaler + * 0b1001..IP bus clock divide by 2 prescaler + * 0b1010..IP bus clock divide by 4 prescaler + * 0b1011..IP bus clock divide by 8 prescaler + * 0b1100..IP bus clock divide by 16 prescaler + * 0b1101..IP bus clock divide by 32 prescaler + * 0b1110..IP bus clock divide by 64 prescaler + * 0b1111..IP bus clock divide by 128 prescaler + */ #define TMR_CTRL_PCS(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_PCS_SHIFT)) & TMR_CTRL_PCS_MASK) #define TMR_CTRL_CM_MASK (0xE000U) #define TMR_CTRL_CM_SHIFT (13U) +/*! CM - Count Mode + * 0b000..No operation + * 0b001..Count rising edges of primary sourceRising edges are counted only when SCTRL[IPS] = 0. Falling edges are counted when SCTRL[IPS] = 1. If the primary count source is IP bus clock divide by 1, only rising edges are counted regardless of the value of SCTRL[IPS]. + * 0b010..Count rising and falling edges of primary sourceIP bus clock divide by 1 cannot be used as a primary count source in edge count mode. + * 0b011..Count rising edges of primary source while secondary input high active + * 0b100..Quadrature count mode, uses primary and secondary sources + * 0b101..Count rising edges of primary source; secondary source specifies directionRising edges are counted only when SCTRL[IPS] = 0. Falling edges are counted when SCTRL[IPS] = 1. + * 0b110..Edge of secondary source triggers primary count until compare + * 0b111..Cascaded counter mode (up/down)The primary count source must be set to one of the counter outputs. + */ #define TMR_CTRL_CM(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_CM_SHIFT)) & TMR_CTRL_CM_MASK) +/*! @} */ /* The count of TMR_CTRL */ #define TMR_CTRL_COUNT (4U) /*! @name SCTRL - Timer Channel Status and Control Register */ +/*! @{ */ #define TMR_SCTRL_OEN_MASK (0x1U) #define TMR_SCTRL_OEN_SHIFT (0U) +/*! OEN - Output Enable + * 0b0..The external pin is configured as an input. + * 0b1..The OFLAG output signal is driven on the external pin. Other timer groups using this external pin as their input see the driven value. The polarity of the signal is determined by OPS. + */ #define TMR_SCTRL_OEN(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_OEN_SHIFT)) & TMR_SCTRL_OEN_MASK) #define TMR_SCTRL_OPS_MASK (0x2U) #define TMR_SCTRL_OPS_SHIFT (1U) +/*! OPS - Output Polarity Select + * 0b0..True polarity. + * 0b1..Inverted polarity. + */ #define TMR_SCTRL_OPS(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_OPS_SHIFT)) & TMR_SCTRL_OPS_MASK) #define TMR_SCTRL_FORCE_MASK (0x4U) #define TMR_SCTRL_FORCE_SHIFT (2U) @@ -21215,6 +34225,12 @@ typedef struct { #define TMR_SCTRL_MSTR(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_MSTR_SHIFT)) & TMR_SCTRL_MSTR_MASK) #define TMR_SCTRL_CAPTURE_MODE_MASK (0xC0U) #define TMR_SCTRL_CAPTURE_MODE_SHIFT (6U) +/*! CAPTURE_MODE - Input Capture Mode + * 0b00..Capture function is disabled + * 0b01..Load capture register on rising edge (when IPS=0) or falling edge (when IPS=1) of input + * 0b10..Load capture register on falling edge (when IPS=0) or rising edge (when IPS=1) of input + * 0b11..Load capture register on both edges of input + */ #define TMR_SCTRL_CAPTURE_MODE(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_CAPTURE_MODE_SHIFT)) & TMR_SCTRL_CAPTURE_MODE_MASK) #define TMR_SCTRL_INPUT_MASK (0x100U) #define TMR_SCTRL_INPUT_SHIFT (8U) @@ -21240,32 +34256,50 @@ typedef struct { #define TMR_SCTRL_TCF_MASK (0x8000U) #define TMR_SCTRL_TCF_SHIFT (15U) #define TMR_SCTRL_TCF(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_TCF_SHIFT)) & TMR_SCTRL_TCF_MASK) +/*! @} */ /* The count of TMR_SCTRL */ #define TMR_SCTRL_COUNT (4U) /*! @name CMPLD1 - Timer Channel Comparator Load Register 1 */ +/*! @{ */ #define TMR_CMPLD1_COMPARATOR_LOAD_1_MASK (0xFFFFU) #define TMR_CMPLD1_COMPARATOR_LOAD_1_SHIFT (0U) #define TMR_CMPLD1_COMPARATOR_LOAD_1(x) (((uint16_t)(((uint16_t)(x)) << TMR_CMPLD1_COMPARATOR_LOAD_1_SHIFT)) & TMR_CMPLD1_COMPARATOR_LOAD_1_MASK) +/*! @} */ /* The count of TMR_CMPLD1 */ #define TMR_CMPLD1_COUNT (4U) /*! @name CMPLD2 - Timer Channel Comparator Load Register 2 */ +/*! @{ */ #define TMR_CMPLD2_COMPARATOR_LOAD_2_MASK (0xFFFFU) #define TMR_CMPLD2_COMPARATOR_LOAD_2_SHIFT (0U) #define TMR_CMPLD2_COMPARATOR_LOAD_2(x) (((uint16_t)(((uint16_t)(x)) << TMR_CMPLD2_COMPARATOR_LOAD_2_SHIFT)) & TMR_CMPLD2_COMPARATOR_LOAD_2_MASK) +/*! @} */ /* The count of TMR_CMPLD2 */ #define TMR_CMPLD2_COUNT (4U) /*! @name CSCTRL - Timer Channel Comparator Status and Control Register */ +/*! @{ */ #define TMR_CSCTRL_CL1_MASK (0x3U) #define TMR_CSCTRL_CL1_SHIFT (0U) +/*! CL1 - Compare Load Control 1 + * 0b00..Never preload + * 0b01..Load upon successful compare with the value in COMP1 + * 0b10..Load upon successful compare with the value in COMP2 + * 0b11..Reserved + */ #define TMR_CSCTRL_CL1(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_CL1_SHIFT)) & TMR_CSCTRL_CL1_MASK) #define TMR_CSCTRL_CL2_MASK (0xCU) #define TMR_CSCTRL_CL2_SHIFT (2U) +/*! CL2 - Compare Load Control 2 + * 0b00..Never preload + * 0b01..Load upon successful compare with the value in COMP1 + * 0b10..Load upon successful compare with the value in COMP2 + * 0b11..Reserved + */ #define TMR_CSCTRL_CL2(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_CL2_SHIFT)) & TMR_CSCTRL_CL2_MASK) #define TMR_CSCTRL_TCF1_MASK (0x10U) #define TMR_CSCTRL_TCF1_SHIFT (4U) @@ -21281,38 +34315,68 @@ typedef struct { #define TMR_CSCTRL_TCF2EN(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_TCF2EN_SHIFT)) & TMR_CSCTRL_TCF2EN_MASK) #define TMR_CSCTRL_UP_MASK (0x200U) #define TMR_CSCTRL_UP_SHIFT (9U) +/*! UP - Counting Direction Indicator + * 0b0..The last count was in the DOWN direction. + * 0b1..The last count was in the UP direction. + */ #define TMR_CSCTRL_UP(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_UP_SHIFT)) & TMR_CSCTRL_UP_MASK) #define TMR_CSCTRL_TCI_MASK (0x400U) #define TMR_CSCTRL_TCI_SHIFT (10U) +/*! TCI - Triggered Count Initialization Control + * 0b0..Stop counter upon receiving a second trigger event while still counting from the first trigger event. + * 0b1..Reload the counter upon receiving a second trigger event while still counting from the first trigger event. + */ #define TMR_CSCTRL_TCI(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_TCI_SHIFT)) & TMR_CSCTRL_TCI_MASK) #define TMR_CSCTRL_ROC_MASK (0x800U) #define TMR_CSCTRL_ROC_SHIFT (11U) +/*! ROC - Reload on Capture + * 0b0..Do not reload the counter on a capture event. + * 0b1..Reload the counter on a capture event. + */ #define TMR_CSCTRL_ROC(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_ROC_SHIFT)) & TMR_CSCTRL_ROC_MASK) #define TMR_CSCTRL_ALT_LOAD_MASK (0x1000U) #define TMR_CSCTRL_ALT_LOAD_SHIFT (12U) +/*! ALT_LOAD - Alternative Load Enable + * 0b0..Counter can be re-initialized only with the LOAD register. + * 0b1..Counter can be re-initialized with the LOAD or CMPLD2 registers depending on count direction. + */ #define TMR_CSCTRL_ALT_LOAD(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_ALT_LOAD_SHIFT)) & TMR_CSCTRL_ALT_LOAD_MASK) #define TMR_CSCTRL_FAULT_MASK (0x2000U) #define TMR_CSCTRL_FAULT_SHIFT (13U) +/*! FAULT - Fault Enable + * 0b0..Fault function disabled. + * 0b1..Fault function enabled. + */ #define TMR_CSCTRL_FAULT(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_FAULT_SHIFT)) & TMR_CSCTRL_FAULT_MASK) #define TMR_CSCTRL_DBG_EN_MASK (0xC000U) #define TMR_CSCTRL_DBG_EN_SHIFT (14U) +/*! DBG_EN - Debug Actions Enable + * 0b00..Continue with normal operation during debug mode. (default) + * 0b01..Halt TMR counter during debug mode. + * 0b10..Force TMR output to logic 0 (prior to consideration of SCTRL[OPS]). + * 0b11..Both halt counter and force output to 0 during debug mode. + */ #define TMR_CSCTRL_DBG_EN(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_DBG_EN_SHIFT)) & TMR_CSCTRL_DBG_EN_MASK) +/*! @} */ /* The count of TMR_CSCTRL */ #define TMR_CSCTRL_COUNT (4U) /*! @name FILT - Timer Channel Input Filter Register */ +/*! @{ */ #define TMR_FILT_FILT_PER_MASK (0xFFU) #define TMR_FILT_FILT_PER_SHIFT (0U) #define TMR_FILT_FILT_PER(x) (((uint16_t)(((uint16_t)(x)) << TMR_FILT_FILT_PER_SHIFT)) & TMR_FILT_FILT_PER_MASK) #define TMR_FILT_FILT_CNT_MASK (0x700U) #define TMR_FILT_FILT_CNT_SHIFT (8U) #define TMR_FILT_FILT_CNT(x) (((uint16_t)(((uint16_t)(x)) << TMR_FILT_FILT_CNT_SHIFT)) & TMR_FILT_FILT_CNT_MASK) +/*! @} */ /* The count of TMR_FILT */ #define TMR_FILT_COUNT (4U) /*! @name DMA - Timer Channel DMA Enable Register */ +/*! @{ */ #define TMR_DMA_IEFDE_MASK (0x1U) #define TMR_DMA_IEFDE_SHIFT (0U) #define TMR_DMA_IEFDE(x) (((uint16_t)(((uint16_t)(x)) << TMR_DMA_IEFDE_SHIFT)) & TMR_DMA_IEFDE_MASK) @@ -21322,14 +34386,21 @@ typedef struct { #define TMR_DMA_CMPLD2DE_MASK (0x4U) #define TMR_DMA_CMPLD2DE_SHIFT (2U) #define TMR_DMA_CMPLD2DE(x) (((uint16_t)(((uint16_t)(x)) << TMR_DMA_CMPLD2DE_SHIFT)) & TMR_DMA_CMPLD2DE_MASK) +/*! @} */ /* The count of TMR_DMA */ #define TMR_DMA_COUNT (4U) /*! @name ENBL - Timer Channel Enable Register */ +/*! @{ */ #define TMR_ENBL_ENBL_MASK (0xFU) #define TMR_ENBL_ENBL_SHIFT (0U) +/*! ENBL - Timer Channel Enable + * 0b0000..Timer channel is disabled. + * 0b0001..Timer channel is enabled. (default) + */ #define TMR_ENBL_ENBL(x) (((uint16_t)(((uint16_t)(x)) << TMR_ENBL_ENBL_SHIFT)) & TMR_ENBL_ENBL_MASK) +/*! @} */ /* The count of TMR_ENBL */ #define TMR_ENBL_COUNT (4U) @@ -21454,11 +34525,24 @@ typedef struct { */ /*! @name MCTL - Miscellaneous Control Register */ +/*! @{ */ #define TRNG_MCTL_SAMP_MODE_MASK (0x3U) #define TRNG_MCTL_SAMP_MODE_SHIFT (0U) +/*! SAMP_MODE + * 0b00..use Von Neumann data into both Entropy shifter and Statistical Checker + * 0b01..use raw data into both Entropy shifter and Statistical Checker + * 0b10..use Von Neumann data into Entropy shifter. Use raw data into Statistical Checker + * 0b11..undefined/reserved. + */ #define TRNG_MCTL_SAMP_MODE(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_SAMP_MODE_SHIFT)) & TRNG_MCTL_SAMP_MODE_MASK) #define TRNG_MCTL_OSC_DIV_MASK (0xCU) #define TRNG_MCTL_OSC_DIV_SHIFT (2U) +/*! OSC_DIV + * 0b00..use ring oscillator with no divide + * 0b01..use ring oscillator divided-by-2 + * 0b10..use ring oscillator divided-by-4 + * 0b11..use ring oscillator divided-by-8 + */ #define TRNG_MCTL_OSC_DIV(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_OSC_DIV_SHIFT)) & TRNG_MCTL_OSC_DIV_MASK) #define TRNG_MCTL_UNUSED4_MASK (0x10U) #define TRNG_MCTL_UNUSED4_SHIFT (4U) @@ -21496,173 +34580,223 @@ typedef struct { #define TRNG_MCTL_PRGM_MASK (0x10000U) #define TRNG_MCTL_PRGM_SHIFT (16U) #define TRNG_MCTL_PRGM(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_PRGM_SHIFT)) & TRNG_MCTL_PRGM_MASK) +/*! @} */ /*! @name SCMISC - Statistical Check Miscellaneous Register */ +/*! @{ */ #define TRNG_SCMISC_LRUN_MAX_MASK (0xFFU) #define TRNG_SCMISC_LRUN_MAX_SHIFT (0U) #define TRNG_SCMISC_LRUN_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCMISC_LRUN_MAX_SHIFT)) & TRNG_SCMISC_LRUN_MAX_MASK) #define TRNG_SCMISC_RTY_CT_MASK (0xF0000U) #define TRNG_SCMISC_RTY_CT_SHIFT (16U) #define TRNG_SCMISC_RTY_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCMISC_RTY_CT_SHIFT)) & TRNG_SCMISC_RTY_CT_MASK) +/*! @} */ /*! @name PKRRNG - Poker Range Register */ +/*! @{ */ #define TRNG_PKRRNG_PKR_RNG_MASK (0xFFFFU) #define TRNG_PKRRNG_PKR_RNG_SHIFT (0U) #define TRNG_PKRRNG_PKR_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRRNG_PKR_RNG_SHIFT)) & TRNG_PKRRNG_PKR_RNG_MASK) +/*! @} */ /*! @name PKRMAX - Poker Maximum Limit Register */ +/*! @{ */ #define TRNG_PKRMAX_PKR_MAX_MASK (0xFFFFFFU) #define TRNG_PKRMAX_PKR_MAX_SHIFT (0U) #define TRNG_PKRMAX_PKR_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRMAX_PKR_MAX_SHIFT)) & TRNG_PKRMAX_PKR_MAX_MASK) +/*! @} */ /*! @name PKRSQ - Poker Square Calculation Result Register */ +/*! @{ */ #define TRNG_PKRSQ_PKR_SQ_MASK (0xFFFFFFU) #define TRNG_PKRSQ_PKR_SQ_SHIFT (0U) #define TRNG_PKRSQ_PKR_SQ(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRSQ_PKR_SQ_SHIFT)) & TRNG_PKRSQ_PKR_SQ_MASK) +/*! @} */ /*! @name SDCTL - Seed Control Register */ +/*! @{ */ #define TRNG_SDCTL_SAMP_SIZE_MASK (0xFFFFU) #define TRNG_SDCTL_SAMP_SIZE_SHIFT (0U) #define TRNG_SDCTL_SAMP_SIZE(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SDCTL_SAMP_SIZE_SHIFT)) & TRNG_SDCTL_SAMP_SIZE_MASK) #define TRNG_SDCTL_ENT_DLY_MASK (0xFFFF0000U) #define TRNG_SDCTL_ENT_DLY_SHIFT (16U) #define TRNG_SDCTL_ENT_DLY(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SDCTL_ENT_DLY_SHIFT)) & TRNG_SDCTL_ENT_DLY_MASK) +/*! @} */ /*! @name SBLIM - Sparse Bit Limit Register */ +/*! @{ */ #define TRNG_SBLIM_SB_LIM_MASK (0x3FFU) #define TRNG_SBLIM_SB_LIM_SHIFT (0U) #define TRNG_SBLIM_SB_LIM(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SBLIM_SB_LIM_SHIFT)) & TRNG_SBLIM_SB_LIM_MASK) +/*! @} */ /*! @name TOTSAM - Total Samples Register */ +/*! @{ */ #define TRNG_TOTSAM_TOT_SAM_MASK (0xFFFFFU) #define TRNG_TOTSAM_TOT_SAM_SHIFT (0U) #define TRNG_TOTSAM_TOT_SAM(x) (((uint32_t)(((uint32_t)(x)) << TRNG_TOTSAM_TOT_SAM_SHIFT)) & TRNG_TOTSAM_TOT_SAM_MASK) +/*! @} */ /*! @name FRQMIN - Frequency Count Minimum Limit Register */ +/*! @{ */ #define TRNG_FRQMIN_FRQ_MIN_MASK (0x3FFFFFU) #define TRNG_FRQMIN_FRQ_MIN_SHIFT (0U) #define TRNG_FRQMIN_FRQ_MIN(x) (((uint32_t)(((uint32_t)(x)) << TRNG_FRQMIN_FRQ_MIN_SHIFT)) & TRNG_FRQMIN_FRQ_MIN_MASK) +/*! @} */ /*! @name FRQCNT - Frequency Count Register */ +/*! @{ */ #define TRNG_FRQCNT_FRQ_CT_MASK (0x3FFFFFU) #define TRNG_FRQCNT_FRQ_CT_SHIFT (0U) #define TRNG_FRQCNT_FRQ_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_FRQCNT_FRQ_CT_SHIFT)) & TRNG_FRQCNT_FRQ_CT_MASK) +/*! @} */ /*! @name FRQMAX - Frequency Count Maximum Limit Register */ +/*! @{ */ #define TRNG_FRQMAX_FRQ_MAX_MASK (0x3FFFFFU) #define TRNG_FRQMAX_FRQ_MAX_SHIFT (0U) #define TRNG_FRQMAX_FRQ_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_FRQMAX_FRQ_MAX_SHIFT)) & TRNG_FRQMAX_FRQ_MAX_MASK) +/*! @} */ /*! @name SCMC - Statistical Check Monobit Count Register */ +/*! @{ */ #define TRNG_SCMC_MONO_CT_MASK (0xFFFFU) #define TRNG_SCMC_MONO_CT_SHIFT (0U) #define TRNG_SCMC_MONO_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCMC_MONO_CT_SHIFT)) & TRNG_SCMC_MONO_CT_MASK) +/*! @} */ /*! @name SCML - Statistical Check Monobit Limit Register */ +/*! @{ */ #define TRNG_SCML_MONO_MAX_MASK (0xFFFFU) #define TRNG_SCML_MONO_MAX_SHIFT (0U) #define TRNG_SCML_MONO_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCML_MONO_MAX_SHIFT)) & TRNG_SCML_MONO_MAX_MASK) #define TRNG_SCML_MONO_RNG_MASK (0xFFFF0000U) #define TRNG_SCML_MONO_RNG_SHIFT (16U) #define TRNG_SCML_MONO_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCML_MONO_RNG_SHIFT)) & TRNG_SCML_MONO_RNG_MASK) +/*! @} */ /*! @name SCR1C - Statistical Check Run Length 1 Count Register */ +/*! @{ */ #define TRNG_SCR1C_R1_0_CT_MASK (0x7FFFU) #define TRNG_SCR1C_R1_0_CT_SHIFT (0U) #define TRNG_SCR1C_R1_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR1C_R1_0_CT_SHIFT)) & TRNG_SCR1C_R1_0_CT_MASK) #define TRNG_SCR1C_R1_1_CT_MASK (0x7FFF0000U) #define TRNG_SCR1C_R1_1_CT_SHIFT (16U) #define TRNG_SCR1C_R1_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR1C_R1_1_CT_SHIFT)) & TRNG_SCR1C_R1_1_CT_MASK) +/*! @} */ /*! @name SCR1L - Statistical Check Run Length 1 Limit Register */ +/*! @{ */ #define TRNG_SCR1L_RUN1_MAX_MASK (0x7FFFU) #define TRNG_SCR1L_RUN1_MAX_SHIFT (0U) #define TRNG_SCR1L_RUN1_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR1L_RUN1_MAX_SHIFT)) & TRNG_SCR1L_RUN1_MAX_MASK) #define TRNG_SCR1L_RUN1_RNG_MASK (0x7FFF0000U) #define TRNG_SCR1L_RUN1_RNG_SHIFT (16U) #define TRNG_SCR1L_RUN1_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR1L_RUN1_RNG_SHIFT)) & TRNG_SCR1L_RUN1_RNG_MASK) +/*! @} */ /*! @name SCR2C - Statistical Check Run Length 2 Count Register */ +/*! @{ */ #define TRNG_SCR2C_R2_0_CT_MASK (0x3FFFU) #define TRNG_SCR2C_R2_0_CT_SHIFT (0U) #define TRNG_SCR2C_R2_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR2C_R2_0_CT_SHIFT)) & TRNG_SCR2C_R2_0_CT_MASK) #define TRNG_SCR2C_R2_1_CT_MASK (0x3FFF0000U) #define TRNG_SCR2C_R2_1_CT_SHIFT (16U) #define TRNG_SCR2C_R2_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR2C_R2_1_CT_SHIFT)) & TRNG_SCR2C_R2_1_CT_MASK) +/*! @} */ /*! @name SCR2L - Statistical Check Run Length 2 Limit Register */ +/*! @{ */ #define TRNG_SCR2L_RUN2_MAX_MASK (0x3FFFU) #define TRNG_SCR2L_RUN2_MAX_SHIFT (0U) #define TRNG_SCR2L_RUN2_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR2L_RUN2_MAX_SHIFT)) & TRNG_SCR2L_RUN2_MAX_MASK) #define TRNG_SCR2L_RUN2_RNG_MASK (0x3FFF0000U) #define TRNG_SCR2L_RUN2_RNG_SHIFT (16U) #define TRNG_SCR2L_RUN2_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR2L_RUN2_RNG_SHIFT)) & TRNG_SCR2L_RUN2_RNG_MASK) +/*! @} */ /*! @name SCR3C - Statistical Check Run Length 3 Count Register */ +/*! @{ */ #define TRNG_SCR3C_R3_0_CT_MASK (0x1FFFU) #define TRNG_SCR3C_R3_0_CT_SHIFT (0U) #define TRNG_SCR3C_R3_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR3C_R3_0_CT_SHIFT)) & TRNG_SCR3C_R3_0_CT_MASK) #define TRNG_SCR3C_R3_1_CT_MASK (0x1FFF0000U) #define TRNG_SCR3C_R3_1_CT_SHIFT (16U) #define TRNG_SCR3C_R3_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR3C_R3_1_CT_SHIFT)) & TRNG_SCR3C_R3_1_CT_MASK) +/*! @} */ /*! @name SCR3L - Statistical Check Run Length 3 Limit Register */ +/*! @{ */ #define TRNG_SCR3L_RUN3_MAX_MASK (0x1FFFU) #define TRNG_SCR3L_RUN3_MAX_SHIFT (0U) #define TRNG_SCR3L_RUN3_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR3L_RUN3_MAX_SHIFT)) & TRNG_SCR3L_RUN3_MAX_MASK) #define TRNG_SCR3L_RUN3_RNG_MASK (0x1FFF0000U) #define TRNG_SCR3L_RUN3_RNG_SHIFT (16U) #define TRNG_SCR3L_RUN3_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR3L_RUN3_RNG_SHIFT)) & TRNG_SCR3L_RUN3_RNG_MASK) +/*! @} */ /*! @name SCR4C - Statistical Check Run Length 4 Count Register */ +/*! @{ */ #define TRNG_SCR4C_R4_0_CT_MASK (0xFFFU) #define TRNG_SCR4C_R4_0_CT_SHIFT (0U) #define TRNG_SCR4C_R4_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR4C_R4_0_CT_SHIFT)) & TRNG_SCR4C_R4_0_CT_MASK) #define TRNG_SCR4C_R4_1_CT_MASK (0xFFF0000U) #define TRNG_SCR4C_R4_1_CT_SHIFT (16U) #define TRNG_SCR4C_R4_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR4C_R4_1_CT_SHIFT)) & TRNG_SCR4C_R4_1_CT_MASK) +/*! @} */ /*! @name SCR4L - Statistical Check Run Length 4 Limit Register */ +/*! @{ */ #define TRNG_SCR4L_RUN4_MAX_MASK (0xFFFU) #define TRNG_SCR4L_RUN4_MAX_SHIFT (0U) #define TRNG_SCR4L_RUN4_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR4L_RUN4_MAX_SHIFT)) & TRNG_SCR4L_RUN4_MAX_MASK) #define TRNG_SCR4L_RUN4_RNG_MASK (0xFFF0000U) #define TRNG_SCR4L_RUN4_RNG_SHIFT (16U) #define TRNG_SCR4L_RUN4_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR4L_RUN4_RNG_SHIFT)) & TRNG_SCR4L_RUN4_RNG_MASK) +/*! @} */ /*! @name SCR5C - Statistical Check Run Length 5 Count Register */ +/*! @{ */ #define TRNG_SCR5C_R5_0_CT_MASK (0x7FFU) #define TRNG_SCR5C_R5_0_CT_SHIFT (0U) #define TRNG_SCR5C_R5_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR5C_R5_0_CT_SHIFT)) & TRNG_SCR5C_R5_0_CT_MASK) #define TRNG_SCR5C_R5_1_CT_MASK (0x7FF0000U) #define TRNG_SCR5C_R5_1_CT_SHIFT (16U) #define TRNG_SCR5C_R5_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR5C_R5_1_CT_SHIFT)) & TRNG_SCR5C_R5_1_CT_MASK) +/*! @} */ /*! @name SCR5L - Statistical Check Run Length 5 Limit Register */ +/*! @{ */ #define TRNG_SCR5L_RUN5_MAX_MASK (0x7FFU) #define TRNG_SCR5L_RUN5_MAX_SHIFT (0U) #define TRNG_SCR5L_RUN5_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR5L_RUN5_MAX_SHIFT)) & TRNG_SCR5L_RUN5_MAX_MASK) #define TRNG_SCR5L_RUN5_RNG_MASK (0x7FF0000U) #define TRNG_SCR5L_RUN5_RNG_SHIFT (16U) #define TRNG_SCR5L_RUN5_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR5L_RUN5_RNG_SHIFT)) & TRNG_SCR5L_RUN5_RNG_MASK) +/*! @} */ /*! @name SCR6PC - Statistical Check Run Length 6+ Count Register */ +/*! @{ */ #define TRNG_SCR6PC_R6P_0_CT_MASK (0x7FFU) #define TRNG_SCR6PC_R6P_0_CT_SHIFT (0U) #define TRNG_SCR6PC_R6P_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR6PC_R6P_0_CT_SHIFT)) & TRNG_SCR6PC_R6P_0_CT_MASK) #define TRNG_SCR6PC_R6P_1_CT_MASK (0x7FF0000U) #define TRNG_SCR6PC_R6P_1_CT_SHIFT (16U) #define TRNG_SCR6PC_R6P_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR6PC_R6P_1_CT_SHIFT)) & TRNG_SCR6PC_R6P_1_CT_MASK) +/*! @} */ /*! @name SCR6PL - Statistical Check Run Length 6+ Limit Register */ +/*! @{ */ #define TRNG_SCR6PL_RUN6P_MAX_MASK (0x7FFU) #define TRNG_SCR6PL_RUN6P_MAX_SHIFT (0U) #define TRNG_SCR6PL_RUN6P_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR6PL_RUN6P_MAX_SHIFT)) & TRNG_SCR6PL_RUN6P_MAX_MASK) #define TRNG_SCR6PL_RUN6P_RNG_MASK (0x7FF0000U) #define TRNG_SCR6PL_RUN6P_RNG_SHIFT (16U) #define TRNG_SCR6PL_RUN6P_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR6PL_RUN6P_RNG_SHIFT)) & TRNG_SCR6PL_RUN6P_RNG_MASK) +/*! @} */ /*! @name STATUS - Status Register */ +/*! @{ */ #define TRNG_STATUS_TF1BR0_MASK (0x1U) #define TRNG_STATUS_TF1BR0_SHIFT (0U) #define TRNG_STATUS_TF1BR0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF1BR0_SHIFT)) & TRNG_STATUS_TF1BR0_MASK) @@ -21714,150 +34848,242 @@ typedef struct { #define TRNG_STATUS_RETRY_CT_MASK (0xF0000U) #define TRNG_STATUS_RETRY_CT_SHIFT (16U) #define TRNG_STATUS_RETRY_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_RETRY_CT_SHIFT)) & TRNG_STATUS_RETRY_CT_MASK) +/*! @} */ /*! @name ENT - Entropy Read Register */ +/*! @{ */ #define TRNG_ENT_ENT_MASK (0xFFFFFFFFU) #define TRNG_ENT_ENT_SHIFT (0U) #define TRNG_ENT_ENT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_ENT_ENT_SHIFT)) & TRNG_ENT_ENT_MASK) +/*! @} */ /* The count of TRNG_ENT */ #define TRNG_ENT_COUNT (16U) /*! @name PKRCNT10 - Statistical Check Poker Count 1 and 0 Register */ +/*! @{ */ #define TRNG_PKRCNT10_PKR_0_CT_MASK (0xFFFFU) #define TRNG_PKRCNT10_PKR_0_CT_SHIFT (0U) #define TRNG_PKRCNT10_PKR_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT10_PKR_0_CT_SHIFT)) & TRNG_PKRCNT10_PKR_0_CT_MASK) #define TRNG_PKRCNT10_PKR_1_CT_MASK (0xFFFF0000U) #define TRNG_PKRCNT10_PKR_1_CT_SHIFT (16U) #define TRNG_PKRCNT10_PKR_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT10_PKR_1_CT_SHIFT)) & TRNG_PKRCNT10_PKR_1_CT_MASK) +/*! @} */ /*! @name PKRCNT32 - Statistical Check Poker Count 3 and 2 Register */ +/*! @{ */ #define TRNG_PKRCNT32_PKR_2_CT_MASK (0xFFFFU) #define TRNG_PKRCNT32_PKR_2_CT_SHIFT (0U) #define TRNG_PKRCNT32_PKR_2_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT32_PKR_2_CT_SHIFT)) & TRNG_PKRCNT32_PKR_2_CT_MASK) #define TRNG_PKRCNT32_PKR_3_CT_MASK (0xFFFF0000U) #define TRNG_PKRCNT32_PKR_3_CT_SHIFT (16U) #define TRNG_PKRCNT32_PKR_3_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT32_PKR_3_CT_SHIFT)) & TRNG_PKRCNT32_PKR_3_CT_MASK) +/*! @} */ /*! @name PKRCNT54 - Statistical Check Poker Count 5 and 4 Register */ +/*! @{ */ #define TRNG_PKRCNT54_PKR_4_CT_MASK (0xFFFFU) #define TRNG_PKRCNT54_PKR_4_CT_SHIFT (0U) #define TRNG_PKRCNT54_PKR_4_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT54_PKR_4_CT_SHIFT)) & TRNG_PKRCNT54_PKR_4_CT_MASK) #define TRNG_PKRCNT54_PKR_5_CT_MASK (0xFFFF0000U) #define TRNG_PKRCNT54_PKR_5_CT_SHIFT (16U) #define TRNG_PKRCNT54_PKR_5_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT54_PKR_5_CT_SHIFT)) & TRNG_PKRCNT54_PKR_5_CT_MASK) +/*! @} */ /*! @name PKRCNT76 - Statistical Check Poker Count 7 and 6 Register */ +/*! @{ */ #define TRNG_PKRCNT76_PKR_6_CT_MASK (0xFFFFU) #define TRNG_PKRCNT76_PKR_6_CT_SHIFT (0U) #define TRNG_PKRCNT76_PKR_6_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT76_PKR_6_CT_SHIFT)) & TRNG_PKRCNT76_PKR_6_CT_MASK) #define TRNG_PKRCNT76_PKR_7_CT_MASK (0xFFFF0000U) #define TRNG_PKRCNT76_PKR_7_CT_SHIFT (16U) #define TRNG_PKRCNT76_PKR_7_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT76_PKR_7_CT_SHIFT)) & TRNG_PKRCNT76_PKR_7_CT_MASK) +/*! @} */ /*! @name PKRCNT98 - Statistical Check Poker Count 9 and 8 Register */ +/*! @{ */ #define TRNG_PKRCNT98_PKR_8_CT_MASK (0xFFFFU) #define TRNG_PKRCNT98_PKR_8_CT_SHIFT (0U) #define TRNG_PKRCNT98_PKR_8_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT98_PKR_8_CT_SHIFT)) & TRNG_PKRCNT98_PKR_8_CT_MASK) #define TRNG_PKRCNT98_PKR_9_CT_MASK (0xFFFF0000U) #define TRNG_PKRCNT98_PKR_9_CT_SHIFT (16U) #define TRNG_PKRCNT98_PKR_9_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT98_PKR_9_CT_SHIFT)) & TRNG_PKRCNT98_PKR_9_CT_MASK) +/*! @} */ /*! @name PKRCNTBA - Statistical Check Poker Count B and A Register */ +/*! @{ */ #define TRNG_PKRCNTBA_PKR_A_CT_MASK (0xFFFFU) #define TRNG_PKRCNTBA_PKR_A_CT_SHIFT (0U) #define TRNG_PKRCNTBA_PKR_A_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTBA_PKR_A_CT_SHIFT)) & TRNG_PKRCNTBA_PKR_A_CT_MASK) #define TRNG_PKRCNTBA_PKR_B_CT_MASK (0xFFFF0000U) #define TRNG_PKRCNTBA_PKR_B_CT_SHIFT (16U) #define TRNG_PKRCNTBA_PKR_B_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTBA_PKR_B_CT_SHIFT)) & TRNG_PKRCNTBA_PKR_B_CT_MASK) +/*! @} */ /*! @name PKRCNTDC - Statistical Check Poker Count D and C Register */ +/*! @{ */ #define TRNG_PKRCNTDC_PKR_C_CT_MASK (0xFFFFU) #define TRNG_PKRCNTDC_PKR_C_CT_SHIFT (0U) #define TRNG_PKRCNTDC_PKR_C_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTDC_PKR_C_CT_SHIFT)) & TRNG_PKRCNTDC_PKR_C_CT_MASK) #define TRNG_PKRCNTDC_PKR_D_CT_MASK (0xFFFF0000U) #define TRNG_PKRCNTDC_PKR_D_CT_SHIFT (16U) #define TRNG_PKRCNTDC_PKR_D_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTDC_PKR_D_CT_SHIFT)) & TRNG_PKRCNTDC_PKR_D_CT_MASK) +/*! @} */ /*! @name PKRCNTFE - Statistical Check Poker Count F and E Register */ +/*! @{ */ #define TRNG_PKRCNTFE_PKR_E_CT_MASK (0xFFFFU) #define TRNG_PKRCNTFE_PKR_E_CT_SHIFT (0U) #define TRNG_PKRCNTFE_PKR_E_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTFE_PKR_E_CT_SHIFT)) & TRNG_PKRCNTFE_PKR_E_CT_MASK) #define TRNG_PKRCNTFE_PKR_F_CT_MASK (0xFFFF0000U) #define TRNG_PKRCNTFE_PKR_F_CT_SHIFT (16U) #define TRNG_PKRCNTFE_PKR_F_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTFE_PKR_F_CT_SHIFT)) & TRNG_PKRCNTFE_PKR_F_CT_MASK) +/*! @} */ /*! @name SEC_CFG - Security Configuration Register */ +/*! @{ */ #define TRNG_SEC_CFG_UNUSED0_MASK (0x1U) #define TRNG_SEC_CFG_UNUSED0_SHIFT (0U) #define TRNG_SEC_CFG_UNUSED0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SEC_CFG_UNUSED0_SHIFT)) & TRNG_SEC_CFG_UNUSED0_MASK) #define TRNG_SEC_CFG_NO_PRGM_MASK (0x2U) #define TRNG_SEC_CFG_NO_PRGM_SHIFT (1U) +/*! NO_PRGM + * 0b0..Programability of registers controlled only by the Miscellaneous Control Register's access mode bit. + * 0b1..Overides Miscellaneous Control Register access mode and prevents TRNG register programming. + */ #define TRNG_SEC_CFG_NO_PRGM(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SEC_CFG_NO_PRGM_SHIFT)) & TRNG_SEC_CFG_NO_PRGM_MASK) #define TRNG_SEC_CFG_UNUSED2_MASK (0x4U) #define TRNG_SEC_CFG_UNUSED2_SHIFT (2U) #define TRNG_SEC_CFG_UNUSED2(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SEC_CFG_UNUSED2_SHIFT)) & TRNG_SEC_CFG_UNUSED2_MASK) +/*! @} */ /*! @name INT_CTRL - Interrupt Control Register */ +/*! @{ */ #define TRNG_INT_CTRL_HW_ERR_MASK (0x1U) #define TRNG_INT_CTRL_HW_ERR_SHIFT (0U) +/*! HW_ERR + * 0b0..Corresponding bit of INT_STATUS register cleared. + * 0b1..Corresponding bit of INT_STATUS register active. + */ #define TRNG_INT_CTRL_HW_ERR(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_CTRL_HW_ERR_SHIFT)) & TRNG_INT_CTRL_HW_ERR_MASK) #define TRNG_INT_CTRL_ENT_VAL_MASK (0x2U) #define TRNG_INT_CTRL_ENT_VAL_SHIFT (1U) +/*! ENT_VAL + * 0b0..Same behavior as bit 0 of this register. + * 0b1..Same behavior as bit 0 of this register. + */ #define TRNG_INT_CTRL_ENT_VAL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_CTRL_ENT_VAL_SHIFT)) & TRNG_INT_CTRL_ENT_VAL_MASK) #define TRNG_INT_CTRL_FRQ_CT_FAIL_MASK (0x4U) #define TRNG_INT_CTRL_FRQ_CT_FAIL_SHIFT (2U) +/*! FRQ_CT_FAIL + * 0b0..Same behavior as bit 0 of this register. + * 0b1..Same behavior as bit 0 of this register. + */ #define TRNG_INT_CTRL_FRQ_CT_FAIL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_CTRL_FRQ_CT_FAIL_SHIFT)) & TRNG_INT_CTRL_FRQ_CT_FAIL_MASK) #define TRNG_INT_CTRL_UNUSED_MASK (0xFFFFFFF8U) #define TRNG_INT_CTRL_UNUSED_SHIFT (3U) #define TRNG_INT_CTRL_UNUSED(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_CTRL_UNUSED_SHIFT)) & TRNG_INT_CTRL_UNUSED_MASK) +/*! @} */ /*! @name INT_MASK - Mask Register */ +/*! @{ */ #define TRNG_INT_MASK_HW_ERR_MASK (0x1U) #define TRNG_INT_MASK_HW_ERR_SHIFT (0U) +/*! HW_ERR + * 0b0..Corresponding interrupt of INT_STATUS is masked. + * 0b1..Corresponding bit of INT_STATUS is active. + */ #define TRNG_INT_MASK_HW_ERR(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_MASK_HW_ERR_SHIFT)) & TRNG_INT_MASK_HW_ERR_MASK) #define TRNG_INT_MASK_ENT_VAL_MASK (0x2U) #define TRNG_INT_MASK_ENT_VAL_SHIFT (1U) +/*! ENT_VAL + * 0b0..Same behavior as bit 0 of this register. + * 0b1..Same behavior as bit 0 of this register. + */ #define TRNG_INT_MASK_ENT_VAL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_MASK_ENT_VAL_SHIFT)) & TRNG_INT_MASK_ENT_VAL_MASK) #define TRNG_INT_MASK_FRQ_CT_FAIL_MASK (0x4U) #define TRNG_INT_MASK_FRQ_CT_FAIL_SHIFT (2U) +/*! FRQ_CT_FAIL + * 0b0..Same behavior as bit 0 of this register. + * 0b1..Same behavior as bit 0 of this register. + */ #define TRNG_INT_MASK_FRQ_CT_FAIL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_MASK_FRQ_CT_FAIL_SHIFT)) & TRNG_INT_MASK_FRQ_CT_FAIL_MASK) +/*! @} */ /*! @name INT_STATUS - Interrupt Status Register */ +/*! @{ */ #define TRNG_INT_STATUS_HW_ERR_MASK (0x1U) #define TRNG_INT_STATUS_HW_ERR_SHIFT (0U) +/*! HW_ERR + * 0b0..no error + * 0b1..error detected. + */ #define TRNG_INT_STATUS_HW_ERR(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_STATUS_HW_ERR_SHIFT)) & TRNG_INT_STATUS_HW_ERR_MASK) #define TRNG_INT_STATUS_ENT_VAL_MASK (0x2U) #define TRNG_INT_STATUS_ENT_VAL_SHIFT (1U) +/*! ENT_VAL + * 0b0..Busy generation entropy. Any value read is invalid. + * 0b1..TRNG can be stopped and entropy is valid if read. + */ #define TRNG_INT_STATUS_ENT_VAL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_STATUS_ENT_VAL_SHIFT)) & TRNG_INT_STATUS_ENT_VAL_MASK) #define TRNG_INT_STATUS_FRQ_CT_FAIL_MASK (0x4U) #define TRNG_INT_STATUS_FRQ_CT_FAIL_SHIFT (2U) +/*! FRQ_CT_FAIL + * 0b0..No hardware nor self test frequency errors. + * 0b1..The frequency counter has detected a failure. + */ #define TRNG_INT_STATUS_FRQ_CT_FAIL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_STATUS_FRQ_CT_FAIL_SHIFT)) & TRNG_INT_STATUS_FRQ_CT_FAIL_MASK) +/*! @} */ /*! @name VID1 - Version ID Register (MS) */ +/*! @{ */ #define TRNG_VID1_MIN_REV_MASK (0xFFU) #define TRNG_VID1_MIN_REV_SHIFT (0U) +/*! MIN_REV + * 0b00000000..Minor revision number for TRNG. + */ #define TRNG_VID1_MIN_REV(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID1_MIN_REV_SHIFT)) & TRNG_VID1_MIN_REV_MASK) #define TRNG_VID1_MAJ_REV_MASK (0xFF00U) #define TRNG_VID1_MAJ_REV_SHIFT (8U) +/*! MAJ_REV + * 0b00000001..Major revision number for TRNG. + */ #define TRNG_VID1_MAJ_REV(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID1_MAJ_REV_SHIFT)) & TRNG_VID1_MAJ_REV_MASK) #define TRNG_VID1_IP_ID_MASK (0xFFFF0000U) #define TRNG_VID1_IP_ID_SHIFT (16U) +/*! IP_ID + * 0b0000000000110000..ID for TRNG. + */ #define TRNG_VID1_IP_ID(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID1_IP_ID_SHIFT)) & TRNG_VID1_IP_ID_MASK) +/*! @} */ /*! @name VID2 - Version ID Register (LS) */ +/*! @{ */ #define TRNG_VID2_CONFIG_OPT_MASK (0xFFU) #define TRNG_VID2_CONFIG_OPT_SHIFT (0U) +/*! CONFIG_OPT + * 0b00000000..TRNG_CONFIG_OPT for TRNG. + */ #define TRNG_VID2_CONFIG_OPT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID2_CONFIG_OPT_SHIFT)) & TRNG_VID2_CONFIG_OPT_MASK) #define TRNG_VID2_ECO_REV_MASK (0xFF00U) #define TRNG_VID2_ECO_REV_SHIFT (8U) +/*! ECO_REV + * 0b00000000..TRNG_ECO_REV for TRNG. + */ #define TRNG_VID2_ECO_REV(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID2_ECO_REV_SHIFT)) & TRNG_VID2_ECO_REV_MASK) #define TRNG_VID2_INTG_OPT_MASK (0xFF0000U) #define TRNG_VID2_INTG_OPT_SHIFT (16U) +/*! INTG_OPT + * 0b00000000..INTG_OPT for TRNG. + */ #define TRNG_VID2_INTG_OPT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID2_INTG_OPT_SHIFT)) & TRNG_VID2_INTG_OPT_MASK) #define TRNG_VID2_ERA_MASK (0xFF000000U) #define TRNG_VID2_ERA_SHIFT (24U) +/*! ERA + * 0b00000000..COMPILE_OPT for TRNG. + */ #define TRNG_VID2_ERA(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID2_ERA_SHIFT)) & TRNG_VID2_ERA_MASK) +/*! @} */ /*! @@ -21893,9 +35119,9 @@ typedef struct { /** TSC - Register Layout Typedef */ typedef struct { - __IO uint32_t BASIC_SETTING; /**< PS Input Buffer Address, offset: 0x0 */ + __IO uint32_t BASIC_SETTING; /**< , offset: 0x0 */ uint8_t RESERVED_0[12]; - __IO uint32_t PS_INPUT_BUFFER_ADDR; /**< PS Input Buffer Address, offset: 0x10 */ + __IO uint32_t PRE_CHARGE_TIME; /**< , offset: 0x10 */ uint8_t RESERVED_1[12]; __IO uint32_t FLOW_CONTROL; /**< Flow Control, offset: 0x20 */ uint8_t RESERVED_2[12]; @@ -21921,87 +35147,166 @@ typedef struct { * @{ */ -/*! @name BASIC_SETTING - PS Input Buffer Address */ +/*! @name BASIC_SETTING - */ +/*! @{ */ #define TSC_BASIC_SETTING_AUTO_MEASURE_MASK (0x1U) #define TSC_BASIC_SETTING_AUTO_MEASURE_SHIFT (0U) +/*! AUTO_MEASURE - Auto Measure + * 0b0..Disable Auto Measure + * 0b1..Auto Measure + */ #define TSC_BASIC_SETTING_AUTO_MEASURE(x) (((uint32_t)(((uint32_t)(x)) << TSC_BASIC_SETTING_AUTO_MEASURE_SHIFT)) & TSC_BASIC_SETTING_AUTO_MEASURE_MASK) #define TSC_BASIC_SETTING_4_5_WIRE_MASK (0x10U) #define TSC_BASIC_SETTING_4_5_WIRE_SHIFT (4U) +/*! 4_5_WIRE - 4/5 Wire detection + * 0b0..4-Wire Detection Mode + * 0b1..5-Wire Detection Mode + */ #define TSC_BASIC_SETTING_4_5_WIRE(x) (((uint32_t)(((uint32_t)(x)) << TSC_BASIC_SETTING_4_5_WIRE_SHIFT)) & TSC_BASIC_SETTING_4_5_WIRE_MASK) #define TSC_BASIC_SETTING_MEASURE_DELAY_TIME_MASK (0xFFFFFF00U) #define TSC_BASIC_SETTING_MEASURE_DELAY_TIME_SHIFT (8U) #define TSC_BASIC_SETTING_MEASURE_DELAY_TIME(x) (((uint32_t)(((uint32_t)(x)) << TSC_BASIC_SETTING_MEASURE_DELAY_TIME_SHIFT)) & TSC_BASIC_SETTING_MEASURE_DELAY_TIME_MASK) +/*! @} */ -/*! @name PS_INPUT_BUFFER_ADDR - PS Input Buffer Address */ -#define TSC_PS_INPUT_BUFFER_ADDR_PRE_CHARGE_TIME_MASK (0xFFFFFFFFU) -#define TSC_PS_INPUT_BUFFER_ADDR_PRE_CHARGE_TIME_SHIFT (0U) -#define TSC_PS_INPUT_BUFFER_ADDR_PRE_CHARGE_TIME(x) (((uint32_t)(((uint32_t)(x)) << TSC_PS_INPUT_BUFFER_ADDR_PRE_CHARGE_TIME_SHIFT)) & TSC_PS_INPUT_BUFFER_ADDR_PRE_CHARGE_TIME_MASK) +/*! @name PRE_CHARGE_TIME - */ +/*! @{ */ +#define TSC_PRE_CHARGE_TIME_PRE_CHARGE_TIME_MASK (0xFFFFFFFFU) +#define TSC_PRE_CHARGE_TIME_PRE_CHARGE_TIME_SHIFT (0U) +#define TSC_PRE_CHARGE_TIME_PRE_CHARGE_TIME(x) (((uint32_t)(((uint32_t)(x)) << TSC_PRE_CHARGE_TIME_PRE_CHARGE_TIME_SHIFT)) & TSC_PRE_CHARGE_TIME_PRE_CHARGE_TIME_MASK) +/*! @} */ /*! @name FLOW_CONTROL - Flow Control */ +/*! @{ */ #define TSC_FLOW_CONTROL_SW_RST_MASK (0x1U) #define TSC_FLOW_CONTROL_SW_RST_SHIFT (0U) #define TSC_FLOW_CONTROL_SW_RST(x) (((uint32_t)(((uint32_t)(x)) << TSC_FLOW_CONTROL_SW_RST_SHIFT)) & TSC_FLOW_CONTROL_SW_RST_MASK) #define TSC_FLOW_CONTROL_START_MEASURE_MASK (0x10U) #define TSC_FLOW_CONTROL_START_MEASURE_SHIFT (4U) +/*! START_MEASURE - Start Measure + * 0b0..Do not start measure for now + * 0b1..Start measure the X/Y coordinate value + */ #define TSC_FLOW_CONTROL_START_MEASURE(x) (((uint32_t)(((uint32_t)(x)) << TSC_FLOW_CONTROL_START_MEASURE_SHIFT)) & TSC_FLOW_CONTROL_START_MEASURE_MASK) #define TSC_FLOW_CONTROL_DROP_MEASURE_MASK (0x100U) #define TSC_FLOW_CONTROL_DROP_MEASURE_SHIFT (8U) +/*! DROP_MEASURE - Drop Measure + * 0b0..Do not drop measure for now + * 0b1..Drop the measure and controller return to idle status + */ #define TSC_FLOW_CONTROL_DROP_MEASURE(x) (((uint32_t)(((uint32_t)(x)) << TSC_FLOW_CONTROL_DROP_MEASURE_SHIFT)) & TSC_FLOW_CONTROL_DROP_MEASURE_MASK) #define TSC_FLOW_CONTROL_START_SENSE_MASK (0x1000U) #define TSC_FLOW_CONTROL_START_SENSE_SHIFT (12U) +/*! START_SENSE - Start Sense + * 0b0..Stay at idle status + * 0b1..Start sense detection and (if auto_measure set to 1) measure after detect a touch + */ #define TSC_FLOW_CONTROL_START_SENSE(x) (((uint32_t)(((uint32_t)(x)) << TSC_FLOW_CONTROL_START_SENSE_SHIFT)) & TSC_FLOW_CONTROL_START_SENSE_MASK) #define TSC_FLOW_CONTROL_DISABLE_MASK (0x10000U) #define TSC_FLOW_CONTROL_DISABLE_SHIFT (16U) +/*! DISABLE + * 0b0..Leave HW state machine control + * 0b1..SW set to idle status + */ #define TSC_FLOW_CONTROL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << TSC_FLOW_CONTROL_DISABLE_SHIFT)) & TSC_FLOW_CONTROL_DISABLE_MASK) +/*! @} */ /*! @name MEASEURE_VALUE - Measure Value */ +/*! @{ */ #define TSC_MEASEURE_VALUE_Y_VALUE_MASK (0xFFFU) #define TSC_MEASEURE_VALUE_Y_VALUE_SHIFT (0U) #define TSC_MEASEURE_VALUE_Y_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TSC_MEASEURE_VALUE_Y_VALUE_SHIFT)) & TSC_MEASEURE_VALUE_Y_VALUE_MASK) #define TSC_MEASEURE_VALUE_X_VALUE_MASK (0xFFF0000U) #define TSC_MEASEURE_VALUE_X_VALUE_SHIFT (16U) #define TSC_MEASEURE_VALUE_X_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TSC_MEASEURE_VALUE_X_VALUE_SHIFT)) & TSC_MEASEURE_VALUE_X_VALUE_MASK) +/*! @} */ /*! @name INT_EN - Interrupt Enable */ +/*! @{ */ #define TSC_INT_EN_MEASURE_INT_EN_MASK (0x1U) #define TSC_INT_EN_MEASURE_INT_EN_SHIFT (0U) +/*! MEASURE_INT_EN - Measure Interrupt Enable + * 0b0..Disable measure interrupt + * 0b1..Enable measure interrupt + */ #define TSC_INT_EN_MEASURE_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << TSC_INT_EN_MEASURE_INT_EN_SHIFT)) & TSC_INT_EN_MEASURE_INT_EN_MASK) #define TSC_INT_EN_DETECT_INT_EN_MASK (0x10U) #define TSC_INT_EN_DETECT_INT_EN_SHIFT (4U) +/*! DETECT_INT_EN - Detect Interrupt Enable + * 0b0..Disable detect interrupt + * 0b1..Enable detect interrupt + */ #define TSC_INT_EN_DETECT_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << TSC_INT_EN_DETECT_INT_EN_SHIFT)) & TSC_INT_EN_DETECT_INT_EN_MASK) #define TSC_INT_EN_IDLE_SW_INT_EN_MASK (0x1000U) #define TSC_INT_EN_IDLE_SW_INT_EN_SHIFT (12U) +/*! IDLE_SW_INT_EN - Idle Software Interrupt Enable + * 0b0..Disable idle software interrupt + * 0b1..Enable idle software interrupt + */ #define TSC_INT_EN_IDLE_SW_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << TSC_INT_EN_IDLE_SW_INT_EN_SHIFT)) & TSC_INT_EN_IDLE_SW_INT_EN_MASK) +/*! @} */ /*! @name INT_SIG_EN - Interrupt Signal Enable */ +/*! @{ */ #define TSC_INT_SIG_EN_MEASURE_SIG_EN_MASK (0x1U) #define TSC_INT_SIG_EN_MEASURE_SIG_EN_SHIFT (0U) #define TSC_INT_SIG_EN_MEASURE_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << TSC_INT_SIG_EN_MEASURE_SIG_EN_SHIFT)) & TSC_INT_SIG_EN_MEASURE_SIG_EN_MASK) #define TSC_INT_SIG_EN_DETECT_SIG_EN_MASK (0x10U) #define TSC_INT_SIG_EN_DETECT_SIG_EN_SHIFT (4U) +/*! DETECT_SIG_EN - Detect Signal Enable + * 0b0..Disable detect signal + * 0b1..Enable detect signal + */ #define TSC_INT_SIG_EN_DETECT_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << TSC_INT_SIG_EN_DETECT_SIG_EN_SHIFT)) & TSC_INT_SIG_EN_DETECT_SIG_EN_MASK) #define TSC_INT_SIG_EN_VALID_SIG_EN_MASK (0x100U) #define TSC_INT_SIG_EN_VALID_SIG_EN_SHIFT (8U) +/*! VALID_SIG_EN - Valid Signal Enable + * 0b0..Disable valid signal + * 0b1..Enable valid signal + */ #define TSC_INT_SIG_EN_VALID_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << TSC_INT_SIG_EN_VALID_SIG_EN_SHIFT)) & TSC_INT_SIG_EN_VALID_SIG_EN_MASK) #define TSC_INT_SIG_EN_IDLE_SW_SIG_EN_MASK (0x1000U) #define TSC_INT_SIG_EN_IDLE_SW_SIG_EN_SHIFT (12U) +/*! IDLE_SW_SIG_EN - Idle Software Signal Enable + * 0b0..Disable idle software signal + * 0b1..Enable idle software signal + */ #define TSC_INT_SIG_EN_IDLE_SW_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << TSC_INT_SIG_EN_IDLE_SW_SIG_EN_SHIFT)) & TSC_INT_SIG_EN_IDLE_SW_SIG_EN_MASK) +/*! @} */ /*! @name INT_STATUS - Intterrupt Status */ +/*! @{ */ #define TSC_INT_STATUS_MEASURE_MASK (0x1U) #define TSC_INT_STATUS_MEASURE_SHIFT (0U) +/*! MEASURE - Measure Signal + * 0b0..Does not exist a measure signal + * 0b1..Exist a measure signal + */ #define TSC_INT_STATUS_MEASURE(x) (((uint32_t)(((uint32_t)(x)) << TSC_INT_STATUS_MEASURE_SHIFT)) & TSC_INT_STATUS_MEASURE_MASK) #define TSC_INT_STATUS_DETECT_MASK (0x10U) #define TSC_INT_STATUS_DETECT_SHIFT (4U) +/*! DETECT - Detect Signal + * 0b0..Does not exist a detect signal + * 0b1..Exist detect signal + */ #define TSC_INT_STATUS_DETECT(x) (((uint32_t)(((uint32_t)(x)) << TSC_INT_STATUS_DETECT_SHIFT)) & TSC_INT_STATUS_DETECT_MASK) #define TSC_INT_STATUS_VALID_MASK (0x100U) #define TSC_INT_STATUS_VALID_SHIFT (8U) +/*! VALID - Valid Signal + * 0b0..There is no touch detected after measurement, indicates that the measured value is not valid + * 0b1..There is touch detection after measurement, indicates that the measure is valid + */ #define TSC_INT_STATUS_VALID(x) (((uint32_t)(((uint32_t)(x)) << TSC_INT_STATUS_VALID_SHIFT)) & TSC_INT_STATUS_VALID_MASK) #define TSC_INT_STATUS_IDLE_SW_MASK (0x1000U) #define TSC_INT_STATUS_IDLE_SW_SHIFT (12U) +/*! IDLE_SW - Idle Software + * 0b0..Haven't return to idle status + * 0b1..Already return to idle status + */ #define TSC_INT_STATUS_IDLE_SW(x) (((uint32_t)(((uint32_t)(x)) << TSC_INT_STATUS_IDLE_SW_SHIFT)) & TSC_INT_STATUS_IDLE_SW_MASK) +/*! @} */ /*! @name DEBUG_MODE - */ +/*! @{ */ #define TSC_DEBUG_MODE_ADC_CONV_VALUE_MASK (0xFFFU) #define TSC_DEBUG_MODE_ADC_CONV_VALUE_SHIFT (0U) #define TSC_DEBUG_MODE_ADC_CONV_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE_ADC_CONV_VALUE_SHIFT)) & TSC_DEBUG_MODE_ADC_CONV_VALUE_MASK) @@ -22013,84 +35318,198 @@ typedef struct { #define TSC_DEBUG_MODE_EXT_HWTS(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE_EXT_HWTS_SHIFT)) & TSC_DEBUG_MODE_EXT_HWTS_MASK) #define TSC_DEBUG_MODE_TRIGGER_MASK (0x1000000U) #define TSC_DEBUG_MODE_TRIGGER_SHIFT (24U) +/*! TRIGGER - Trigger + * 0b0..No hardware trigger signal + * 0b1..Hardware trigger signal, the signal must last at least 1 ips clock period + */ #define TSC_DEBUG_MODE_TRIGGER(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE_TRIGGER_SHIFT)) & TSC_DEBUG_MODE_TRIGGER_MASK) #define TSC_DEBUG_MODE_ADC_COCO_CLEAR_MASK (0x2000000U) #define TSC_DEBUG_MODE_ADC_COCO_CLEAR_SHIFT (25U) +/*! ADC_COCO_CLEAR - ADC Coco Clear + * 0b0..No ADC COCO clear + * 0b1..Set ADC COCO clear + */ #define TSC_DEBUG_MODE_ADC_COCO_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE_ADC_COCO_CLEAR_SHIFT)) & TSC_DEBUG_MODE_ADC_COCO_CLEAR_MASK) #define TSC_DEBUG_MODE_ADC_COCO_CLEAR_DISABLE_MASK (0x4000000U) #define TSC_DEBUG_MODE_ADC_COCO_CLEAR_DISABLE_SHIFT (26U) +/*! ADC_COCO_CLEAR_DISABLE - ADC COCO Clear Disable + * 0b0..Allow TSC hardware generates ADC COCO clear + * 0b1..Prevent TSC from generate ADC COCO clear signal + */ #define TSC_DEBUG_MODE_ADC_COCO_CLEAR_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE_ADC_COCO_CLEAR_DISABLE_SHIFT)) & TSC_DEBUG_MODE_ADC_COCO_CLEAR_DISABLE_MASK) #define TSC_DEBUG_MODE_DEBUG_EN_MASK (0x10000000U) #define TSC_DEBUG_MODE_DEBUG_EN_SHIFT (28U) +/*! DEBUG_EN - Debug Enable + * 0b0..Enable debug mode + * 0b1..Disable debug mode + */ #define TSC_DEBUG_MODE_DEBUG_EN(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE_DEBUG_EN_SHIFT)) & TSC_DEBUG_MODE_DEBUG_EN_MASK) +/*! @} */ /*! @name DEBUG_MODE2 - */ +/*! @{ */ #define TSC_DEBUG_MODE2_XPUL_PULL_DOWN_MASK (0x1U) #define TSC_DEBUG_MODE2_XPUL_PULL_DOWN_SHIFT (0U) +/*! XPUL_PULL_DOWN - XPUL Wire Pull Down Switch + * 0b0..Close the switch + * 0b1..Open up the switch + */ #define TSC_DEBUG_MODE2_XPUL_PULL_DOWN(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_XPUL_PULL_DOWN_SHIFT)) & TSC_DEBUG_MODE2_XPUL_PULL_DOWN_MASK) #define TSC_DEBUG_MODE2_XPUL_PULL_UP_MASK (0x2U) #define TSC_DEBUG_MODE2_XPUL_PULL_UP_SHIFT (1U) +/*! XPUL_PULL_UP - XPUL Wire Pull Up Switch + * 0b0..Close the switch + * 0b1..Open up the switch + */ #define TSC_DEBUG_MODE2_XPUL_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_XPUL_PULL_UP_SHIFT)) & TSC_DEBUG_MODE2_XPUL_PULL_UP_MASK) #define TSC_DEBUG_MODE2_XPUL_200K_PULL_UP_MASK (0x4U) #define TSC_DEBUG_MODE2_XPUL_200K_PULL_UP_SHIFT (2U) +/*! XPUL_200K_PULL_UP - XPUL Wire 200K Pull Up Switch + * 0b0..Close the switch + * 0b1..Open up the switch + */ #define TSC_DEBUG_MODE2_XPUL_200K_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_XPUL_200K_PULL_UP_SHIFT)) & TSC_DEBUG_MODE2_XPUL_200K_PULL_UP_MASK) #define TSC_DEBUG_MODE2_XNUR_PULL_DOWN_MASK (0x8U) #define TSC_DEBUG_MODE2_XNUR_PULL_DOWN_SHIFT (3U) +/*! XNUR_PULL_DOWN - XNUR Wire Pull Down Switch + * 0b0..Close the switch + * 0b1..Open up the switch + */ #define TSC_DEBUG_MODE2_XNUR_PULL_DOWN(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_XNUR_PULL_DOWN_SHIFT)) & TSC_DEBUG_MODE2_XNUR_PULL_DOWN_MASK) #define TSC_DEBUG_MODE2_XNUR_PULL_UP_MASK (0x10U) #define TSC_DEBUG_MODE2_XNUR_PULL_UP_SHIFT (4U) +/*! XNUR_PULL_UP - XNUR Wire Pull Up Switch + * 0b0..Close the switch + * 0b1..Open up the switch + */ #define TSC_DEBUG_MODE2_XNUR_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_XNUR_PULL_UP_SHIFT)) & TSC_DEBUG_MODE2_XNUR_PULL_UP_MASK) #define TSC_DEBUG_MODE2_XNUR_200K_PULL_UP_MASK (0x20U) #define TSC_DEBUG_MODE2_XNUR_200K_PULL_UP_SHIFT (5U) +/*! XNUR_200K_PULL_UP - XNUR Wire 200K Pull Up Switch + * 0b0..Close the switch + * 0b1..Open up the switch + */ #define TSC_DEBUG_MODE2_XNUR_200K_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_XNUR_200K_PULL_UP_SHIFT)) & TSC_DEBUG_MODE2_XNUR_200K_PULL_UP_MASK) #define TSC_DEBUG_MODE2_YPLL_PULL_DOWN_MASK (0x40U) #define TSC_DEBUG_MODE2_YPLL_PULL_DOWN_SHIFT (6U) +/*! YPLL_PULL_DOWN - YPLL Wire Pull Down Switch + * 0b0..Close the switch + * 0b1..Open up the switch + */ #define TSC_DEBUG_MODE2_YPLL_PULL_DOWN(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_YPLL_PULL_DOWN_SHIFT)) & TSC_DEBUG_MODE2_YPLL_PULL_DOWN_MASK) #define TSC_DEBUG_MODE2_YPLL_PULL_UP_MASK (0x80U) #define TSC_DEBUG_MODE2_YPLL_PULL_UP_SHIFT (7U) +/*! YPLL_PULL_UP - YPLL Wire Pull Up Switch + * 0b0..Close the switch + * 0b1..Open the switch + */ #define TSC_DEBUG_MODE2_YPLL_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_YPLL_PULL_UP_SHIFT)) & TSC_DEBUG_MODE2_YPLL_PULL_UP_MASK) #define TSC_DEBUG_MODE2_YPLL_200K_PULL_UP_MASK (0x100U) #define TSC_DEBUG_MODE2_YPLL_200K_PULL_UP_SHIFT (8U) +/*! YPLL_200K_PULL_UP - YPLL Wire 200K Pull Up Switch + * 0b0..Close the switch + * 0b1..Open up the switch + */ #define TSC_DEBUG_MODE2_YPLL_200K_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_YPLL_200K_PULL_UP_SHIFT)) & TSC_DEBUG_MODE2_YPLL_200K_PULL_UP_MASK) #define TSC_DEBUG_MODE2_YNLR_PULL_DOWN_MASK (0x200U) #define TSC_DEBUG_MODE2_YNLR_PULL_DOWN_SHIFT (9U) +/*! YNLR_PULL_DOWN - YNLR Wire Pull Down Switch + * 0b0..Close the switch + * 0b1..Open up the switch + */ #define TSC_DEBUG_MODE2_YNLR_PULL_DOWN(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_YNLR_PULL_DOWN_SHIFT)) & TSC_DEBUG_MODE2_YNLR_PULL_DOWN_MASK) #define TSC_DEBUG_MODE2_YNLR_PULL_UP_MASK (0x400U) #define TSC_DEBUG_MODE2_YNLR_PULL_UP_SHIFT (10U) +/*! YNLR_PULL_UP - YNLR Wire Pull Up Switch + * 0b0..Close the switch + * 0b1..Open up the switch + */ #define TSC_DEBUG_MODE2_YNLR_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_YNLR_PULL_UP_SHIFT)) & TSC_DEBUG_MODE2_YNLR_PULL_UP_MASK) #define TSC_DEBUG_MODE2_YNLR_200K_PULL_UP_MASK (0x800U) #define TSC_DEBUG_MODE2_YNLR_200K_PULL_UP_SHIFT (11U) +/*! YNLR_200K_PULL_UP - YNLR Wire 200K Pull Up Switch + * 0b0..Close the switch + * 0b1..Open up the switch + */ #define TSC_DEBUG_MODE2_YNLR_200K_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_YNLR_200K_PULL_UP_SHIFT)) & TSC_DEBUG_MODE2_YNLR_200K_PULL_UP_MASK) #define TSC_DEBUG_MODE2_WIPER_PULL_DOWN_MASK (0x1000U) #define TSC_DEBUG_MODE2_WIPER_PULL_DOWN_SHIFT (12U) +/*! WIPER_PULL_DOWN - Wiper Wire Pull Down Switch + * 0b0..Close the switch + * 0b1..Open up the switch + */ #define TSC_DEBUG_MODE2_WIPER_PULL_DOWN(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_WIPER_PULL_DOWN_SHIFT)) & TSC_DEBUG_MODE2_WIPER_PULL_DOWN_MASK) #define TSC_DEBUG_MODE2_WIPER_PULL_UP_MASK (0x2000U) #define TSC_DEBUG_MODE2_WIPER_PULL_UP_SHIFT (13U) +/*! WIPER_PULL_UP - Wiper Wire Pull Up Switch + * 0b0..Close the switch + * 0b1..Open up the switch + */ #define TSC_DEBUG_MODE2_WIPER_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_WIPER_PULL_UP_SHIFT)) & TSC_DEBUG_MODE2_WIPER_PULL_UP_MASK) #define TSC_DEBUG_MODE2_WIPER_200K_PULL_UP_MASK (0x4000U) #define TSC_DEBUG_MODE2_WIPER_200K_PULL_UP_SHIFT (14U) +/*! WIPER_200K_PULL_UP - Wiper Wire 200K Pull Up Switch + * 0b0..Close the switch + * 0b1..Open up the switch + */ #define TSC_DEBUG_MODE2_WIPER_200K_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_WIPER_200K_PULL_UP_SHIFT)) & TSC_DEBUG_MODE2_WIPER_200K_PULL_UP_MASK) #define TSC_DEBUG_MODE2_DETECT_FOUR_WIRE_MASK (0x10000U) #define TSC_DEBUG_MODE2_DETECT_FOUR_WIRE_SHIFT (16U) +/*! DETECT_FOUR_WIRE - Detect Four Wire + * 0b0..No detect signal + * 0b1..Yes, there is a detect on the touch screen. + */ #define TSC_DEBUG_MODE2_DETECT_FOUR_WIRE(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_DETECT_FOUR_WIRE_SHIFT)) & TSC_DEBUG_MODE2_DETECT_FOUR_WIRE_MASK) #define TSC_DEBUG_MODE2_DETECT_FIVE_WIRE_MASK (0x20000U) #define TSC_DEBUG_MODE2_DETECT_FIVE_WIRE_SHIFT (17U) +/*! DETECT_FIVE_WIRE - Detect Five Wire + * 0b0..No detect signal + * 0b1..Yes, there is a detect on the touch screen. + */ #define TSC_DEBUG_MODE2_DETECT_FIVE_WIRE(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_DETECT_FIVE_WIRE_SHIFT)) & TSC_DEBUG_MODE2_DETECT_FIVE_WIRE_MASK) #define TSC_DEBUG_MODE2_STATE_MACHINE_MASK (0x700000U) #define TSC_DEBUG_MODE2_STATE_MACHINE_SHIFT (20U) +/*! STATE_MACHINE - State Machine + * 0b000..Idle + * 0b001..Pre-charge + * 0b010..Detect + * 0b011..X-measure + * 0b100..Y-measure + * 0b101..Pre-charge + * 0b110..Detect + */ #define TSC_DEBUG_MODE2_STATE_MACHINE(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_STATE_MACHINE_SHIFT)) & TSC_DEBUG_MODE2_STATE_MACHINE_MASK) #define TSC_DEBUG_MODE2_INTERMEDIATE_MASK (0x800000U) #define TSC_DEBUG_MODE2_INTERMEDIATE_SHIFT (23U) +/*! INTERMEDIATE - Intermediate State + * 0b0..Not in intermedia + * 0b1..Intermedia + */ #define TSC_DEBUG_MODE2_INTERMEDIATE(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_INTERMEDIATE_SHIFT)) & TSC_DEBUG_MODE2_INTERMEDIATE_MASK) #define TSC_DEBUG_MODE2_DETECT_ENABLE_FOUR_WIRE_MASK (0x1000000U) #define TSC_DEBUG_MODE2_DETECT_ENABLE_FOUR_WIRE_SHIFT (24U) +/*! DETECT_ENABLE_FOUR_WIRE - Detect Enable Four Wire + * 0b0..Do not read four wire detect value, read default value from analogue + * 0b1..Read four wire detect status from analogue + */ #define TSC_DEBUG_MODE2_DETECT_ENABLE_FOUR_WIRE(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_DETECT_ENABLE_FOUR_WIRE_SHIFT)) & TSC_DEBUG_MODE2_DETECT_ENABLE_FOUR_WIRE_MASK) #define TSC_DEBUG_MODE2_DETECT_ENABLE_FIVE_WIRE_MASK (0x10000000U) #define TSC_DEBUG_MODE2_DETECT_ENABLE_FIVE_WIRE_SHIFT (28U) +/*! DETECT_ENABLE_FIVE_WIRE - Detect Enable Five Wire + * 0b0..Do not read five wire detect value, read default value from analogue + * 0b1..Read five wire detect status from analogue + */ #define TSC_DEBUG_MODE2_DETECT_ENABLE_FIVE_WIRE(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_DETECT_ENABLE_FIVE_WIRE_SHIFT)) & TSC_DEBUG_MODE2_DETECT_ENABLE_FIVE_WIRE_MASK) #define TSC_DEBUG_MODE2_DE_GLITCH_MASK (0x60000000U) #define TSC_DEBUG_MODE2_DE_GLITCH_SHIFT (29U) +/*! DE_GLITCH + * 0b00..Normal function: 0x1fff ipg clock cycles; Low power mode: 0x9 low power clock cycles + * 0b01..Normal function: 0xfff ipg clock cycles; Low power mode: :0x7 low power clock cycles + * 0b10..Normal function: 0x7ff ipg clock cycles; Low power mode:0x5 low power clock cycles + * 0b11..Normal function: 0x3 ipg clock cycles; Low power mode:0x3 low power clock cycles + */ #define TSC_DEBUG_MODE2_DE_GLITCH(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_DE_GLITCH_SHIFT)) & TSC_DEBUG_MODE2_DE_GLITCH_MASK) +/*! @} */ /*! @@ -22197,6 +35616,7 @@ typedef struct { */ /*! @name ID - Identification register */ +/*! @{ */ #define USB_ID_ID_MASK (0x3FU) #define USB_ID_ID_SHIFT (0U) #define USB_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << USB_ID_ID_SHIFT)) & USB_ID_ID_MASK) @@ -22206,104 +35626,194 @@ typedef struct { #define USB_ID_REVISION_MASK (0xFF0000U) #define USB_ID_REVISION_SHIFT (16U) #define USB_ID_REVISION(x) (((uint32_t)(((uint32_t)(x)) << USB_ID_REVISION_SHIFT)) & USB_ID_REVISION_MASK) +/*! @} */ /*! @name HWGENERAL - Hardware General */ +/*! @{ */ #define USB_HWGENERAL_PHYW_MASK (0x30U) #define USB_HWGENERAL_PHYW_SHIFT (4U) +/*! PHYW + * 0b00..8 bit wide data bus Software non-programmable + * 0b01..16 bit wide data bus Software non-programmable + * 0b10..Reset to 8 bit wide data bus Software programmable + * 0b11..Reset to 16 bit wide data bus Software programmable + */ #define USB_HWGENERAL_PHYW(x) (((uint32_t)(((uint32_t)(x)) << USB_HWGENERAL_PHYW_SHIFT)) & USB_HWGENERAL_PHYW_MASK) #define USB_HWGENERAL_PHYM_MASK (0x1C0U) #define USB_HWGENERAL_PHYM_SHIFT (6U) +/*! PHYM + * 0b000..UTMI/UMTI+ + * 0b001..ULPI DDR + * 0b010..ULPI + * 0b011..Serial Only + * 0b100..Software programmable - reset to UTMI/UTMI+ + * 0b101..Software programmable - reset to ULPI DDR + * 0b110..Software programmable - reset to ULPI + * 0b111..Software programmable - reset to Serial + */ #define USB_HWGENERAL_PHYM(x) (((uint32_t)(((uint32_t)(x)) << USB_HWGENERAL_PHYM_SHIFT)) & USB_HWGENERAL_PHYM_MASK) #define USB_HWGENERAL_SM_MASK (0x600U) #define USB_HWGENERAL_SM_SHIFT (9U) +/*! SM + * 0b00..No Serial Engine, always use parallel signalling. + * 0b01..Serial Engine present, always use serial signalling for FS/LS. + * 0b10..Software programmable - Reset to use parallel signalling for FS/LS + * 0b11..Software programmable - Reset to use serial signalling for FS/LS + */ #define USB_HWGENERAL_SM(x) (((uint32_t)(((uint32_t)(x)) << USB_HWGENERAL_SM_SHIFT)) & USB_HWGENERAL_SM_MASK) +/*! @} */ /*! @name HWHOST - Host Hardware Parameters */ +/*! @{ */ #define USB_HWHOST_HC_MASK (0x1U) #define USB_HWHOST_HC_SHIFT (0U) +/*! HC + * 0b1..Supported + * 0b0..Not supported + */ #define USB_HWHOST_HC(x) (((uint32_t)(((uint32_t)(x)) << USB_HWHOST_HC_SHIFT)) & USB_HWHOST_HC_MASK) #define USB_HWHOST_NPORT_MASK (0xEU) #define USB_HWHOST_NPORT_SHIFT (1U) #define USB_HWHOST_NPORT(x) (((uint32_t)(((uint32_t)(x)) << USB_HWHOST_NPORT_SHIFT)) & USB_HWHOST_NPORT_MASK) +/*! @} */ /*! @name HWDEVICE - Device Hardware Parameters */ +/*! @{ */ #define USB_HWDEVICE_DC_MASK (0x1U) #define USB_HWDEVICE_DC_SHIFT (0U) +/*! DC + * 0b1..Supported + * 0b0..Not supported + */ #define USB_HWDEVICE_DC(x) (((uint32_t)(((uint32_t)(x)) << USB_HWDEVICE_DC_SHIFT)) & USB_HWDEVICE_DC_MASK) #define USB_HWDEVICE_DEVEP_MASK (0x3EU) #define USB_HWDEVICE_DEVEP_SHIFT (1U) #define USB_HWDEVICE_DEVEP(x) (((uint32_t)(((uint32_t)(x)) << USB_HWDEVICE_DEVEP_SHIFT)) & USB_HWDEVICE_DEVEP_MASK) +/*! @} */ /*! @name HWTXBUF - TX Buffer Hardware Parameters */ +/*! @{ */ #define USB_HWTXBUF_TXBURST_MASK (0xFFU) #define USB_HWTXBUF_TXBURST_SHIFT (0U) #define USB_HWTXBUF_TXBURST(x) (((uint32_t)(((uint32_t)(x)) << USB_HWTXBUF_TXBURST_SHIFT)) & USB_HWTXBUF_TXBURST_MASK) #define USB_HWTXBUF_TXCHANADD_MASK (0xFF0000U) #define USB_HWTXBUF_TXCHANADD_SHIFT (16U) #define USB_HWTXBUF_TXCHANADD(x) (((uint32_t)(((uint32_t)(x)) << USB_HWTXBUF_TXCHANADD_SHIFT)) & USB_HWTXBUF_TXCHANADD_MASK) +/*! @} */ /*! @name HWRXBUF - RX Buffer Hardware Parameters */ +/*! @{ */ #define USB_HWRXBUF_RXBURST_MASK (0xFFU) #define USB_HWRXBUF_RXBURST_SHIFT (0U) #define USB_HWRXBUF_RXBURST(x) (((uint32_t)(((uint32_t)(x)) << USB_HWRXBUF_RXBURST_SHIFT)) & USB_HWRXBUF_RXBURST_MASK) #define USB_HWRXBUF_RXADD_MASK (0xFF00U) #define USB_HWRXBUF_RXADD_SHIFT (8U) #define USB_HWRXBUF_RXADD(x) (((uint32_t)(((uint32_t)(x)) << USB_HWRXBUF_RXADD_SHIFT)) & USB_HWRXBUF_RXADD_MASK) +/*! @} */ /*! @name GPTIMER0LD - General Purpose Timer #0 Load */ +/*! @{ */ #define USB_GPTIMER0LD_GPTLD_MASK (0xFFFFFFU) #define USB_GPTIMER0LD_GPTLD_SHIFT (0U) #define USB_GPTIMER0LD_GPTLD(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER0LD_GPTLD_SHIFT)) & USB_GPTIMER0LD_GPTLD_MASK) +/*! @} */ /*! @name GPTIMER0CTRL - General Purpose Timer #0 Controller */ +/*! @{ */ #define USB_GPTIMER0CTRL_GPTCNT_MASK (0xFFFFFFU) #define USB_GPTIMER0CTRL_GPTCNT_SHIFT (0U) #define USB_GPTIMER0CTRL_GPTCNT(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER0CTRL_GPTCNT_SHIFT)) & USB_GPTIMER0CTRL_GPTCNT_MASK) #define USB_GPTIMER0CTRL_GPTMODE_MASK (0x1000000U) #define USB_GPTIMER0CTRL_GPTMODE_SHIFT (24U) +/*! GPTMODE + * 0b0..One Shot Mode + * 0b1..Repeat Mode + */ #define USB_GPTIMER0CTRL_GPTMODE(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER0CTRL_GPTMODE_SHIFT)) & USB_GPTIMER0CTRL_GPTMODE_MASK) #define USB_GPTIMER0CTRL_GPTRST_MASK (0x40000000U) #define USB_GPTIMER0CTRL_GPTRST_SHIFT (30U) +/*! GPTRST + * 0b0..No action + * 0b1..Load counter value from GPTLD bits in n_GPTIMER0LD + */ #define USB_GPTIMER0CTRL_GPTRST(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER0CTRL_GPTRST_SHIFT)) & USB_GPTIMER0CTRL_GPTRST_MASK) #define USB_GPTIMER0CTRL_GPTRUN_MASK (0x80000000U) #define USB_GPTIMER0CTRL_GPTRUN_SHIFT (31U) +/*! GPTRUN + * 0b0..Stop counting + * 0b1..Run + */ #define USB_GPTIMER0CTRL_GPTRUN(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER0CTRL_GPTRUN_SHIFT)) & USB_GPTIMER0CTRL_GPTRUN_MASK) +/*! @} */ /*! @name GPTIMER1LD - General Purpose Timer #1 Load */ +/*! @{ */ #define USB_GPTIMER1LD_GPTLD_MASK (0xFFFFFFU) #define USB_GPTIMER1LD_GPTLD_SHIFT (0U) #define USB_GPTIMER1LD_GPTLD(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER1LD_GPTLD_SHIFT)) & USB_GPTIMER1LD_GPTLD_MASK) +/*! @} */ /*! @name GPTIMER1CTRL - General Purpose Timer #1 Controller */ +/*! @{ */ #define USB_GPTIMER1CTRL_GPTCNT_MASK (0xFFFFFFU) #define USB_GPTIMER1CTRL_GPTCNT_SHIFT (0U) #define USB_GPTIMER1CTRL_GPTCNT(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER1CTRL_GPTCNT_SHIFT)) & USB_GPTIMER1CTRL_GPTCNT_MASK) #define USB_GPTIMER1CTRL_GPTMODE_MASK (0x1000000U) #define USB_GPTIMER1CTRL_GPTMODE_SHIFT (24U) +/*! GPTMODE + * 0b0..One Shot Mode + * 0b1..Repeat Mode + */ #define USB_GPTIMER1CTRL_GPTMODE(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER1CTRL_GPTMODE_SHIFT)) & USB_GPTIMER1CTRL_GPTMODE_MASK) #define USB_GPTIMER1CTRL_GPTRST_MASK (0x40000000U) #define USB_GPTIMER1CTRL_GPTRST_SHIFT (30U) +/*! GPTRST + * 0b0..No action + * 0b1..Load counter value from GPTLD bits in USB_n_GPTIMER0LD + */ #define USB_GPTIMER1CTRL_GPTRST(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER1CTRL_GPTRST_SHIFT)) & USB_GPTIMER1CTRL_GPTRST_MASK) #define USB_GPTIMER1CTRL_GPTRUN_MASK (0x80000000U) #define USB_GPTIMER1CTRL_GPTRUN_SHIFT (31U) +/*! GPTRUN + * 0b0..Stop counting + * 0b1..Run + */ #define USB_GPTIMER1CTRL_GPTRUN(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER1CTRL_GPTRUN_SHIFT)) & USB_GPTIMER1CTRL_GPTRUN_MASK) +/*! @} */ /*! @name SBUSCFG - System Bus Config */ +/*! @{ */ #define USB_SBUSCFG_AHBBRST_MASK (0x7U) #define USB_SBUSCFG_AHBBRST_SHIFT (0U) +/*! AHBBRST + * 0b000..Incremental burst of unspecified length only + * 0b001..INCR4 burst, then single transfer + * 0b010..INCR8 burst, INCR4 burst, then single transfer + * 0b011..INCR16 burst, INCR8 burst, INCR4 burst, then single transfer + * 0b100..Reserved, don't use + * 0b101..INCR4 burst, then incremental burst of unspecified length + * 0b110..INCR8 burst, INCR4 burst, then incremental burst of unspecified length + * 0b111..INCR16 burst, INCR8 burst, INCR4 burst, then incremental burst of unspecified length + */ #define USB_SBUSCFG_AHBBRST(x) (((uint32_t)(((uint32_t)(x)) << USB_SBUSCFG_AHBBRST_SHIFT)) & USB_SBUSCFG_AHBBRST_MASK) +/*! @} */ /*! @name CAPLENGTH - Capability Registers Length */ +/*! @{ */ #define USB_CAPLENGTH_CAPLENGTH_MASK (0xFFU) #define USB_CAPLENGTH_CAPLENGTH_SHIFT (0U) #define USB_CAPLENGTH_CAPLENGTH(x) (((uint8_t)(((uint8_t)(x)) << USB_CAPLENGTH_CAPLENGTH_SHIFT)) & USB_CAPLENGTH_CAPLENGTH_MASK) +/*! @} */ /*! @name HCIVERSION - Host Controller Interface Version */ +/*! @{ */ #define USB_HCIVERSION_HCIVERSION_MASK (0xFFFFU) #define USB_HCIVERSION_HCIVERSION_SHIFT (0U) #define USB_HCIVERSION_HCIVERSION(x) (((uint16_t)(((uint16_t)(x)) << USB_HCIVERSION_HCIVERSION_SHIFT)) & USB_HCIVERSION_HCIVERSION_MASK) +/*! @} */ /*! @name HCSPARAMS - Host Controller Structural Parameters */ +/*! @{ */ #define USB_HCSPARAMS_N_PORTS_MASK (0xFU) #define USB_HCSPARAMS_N_PORTS_SHIFT (0U) #define USB_HCSPARAMS_N_PORTS(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_N_PORTS_SHIFT)) & USB_HCSPARAMS_N_PORTS_MASK) @@ -22315,6 +35825,10 @@ typedef struct { #define USB_HCSPARAMS_N_PCC(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_N_PCC_SHIFT)) & USB_HCSPARAMS_N_PCC_MASK) #define USB_HCSPARAMS_N_CC_MASK (0xF000U) #define USB_HCSPARAMS_N_CC_SHIFT (12U) +/*! N_CC + * 0b0000..There is no internal Companion Controller and port-ownership hand-off is not supported. + * 0b0001..There are internal companion controller(s) and port-ownership hand-offs is supported. + */ #define USB_HCSPARAMS_N_CC(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_N_CC_SHIFT)) & USB_HCSPARAMS_N_CC_MASK) #define USB_HCSPARAMS_PI_MASK (0x10000U) #define USB_HCSPARAMS_PI_SHIFT (16U) @@ -22325,8 +35839,10 @@ typedef struct { #define USB_HCSPARAMS_N_TT_MASK (0xF000000U) #define USB_HCSPARAMS_N_TT_SHIFT (24U) #define USB_HCSPARAMS_N_TT(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_N_TT_SHIFT)) & USB_HCSPARAMS_N_TT_MASK) +/*! @} */ /*! @name HCCPARAMS - Host Controller Capability Parameters */ +/*! @{ */ #define USB_HCCPARAMS_ADC_MASK (0x1U) #define USB_HCCPARAMS_ADC_SHIFT (0U) #define USB_HCCPARAMS_ADC(x) (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS_ADC_SHIFT)) & USB_HCCPARAMS_ADC_MASK) @@ -22342,13 +35858,17 @@ typedef struct { #define USB_HCCPARAMS_EECP_MASK (0xFF00U) #define USB_HCCPARAMS_EECP_SHIFT (8U) #define USB_HCCPARAMS_EECP(x) (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS_EECP_SHIFT)) & USB_HCCPARAMS_EECP_MASK) +/*! @} */ /*! @name DCIVERSION - Device Controller Interface Version */ +/*! @{ */ #define USB_DCIVERSION_DCIVERSION_MASK (0xFFFFU) #define USB_DCIVERSION_DCIVERSION_SHIFT (0U) #define USB_DCIVERSION_DCIVERSION(x) (((uint16_t)(((uint16_t)(x)) << USB_DCIVERSION_DCIVERSION_SHIFT)) & USB_DCIVERSION_DCIVERSION_MASK) +/*! @} */ /*! @name DCCPARAMS - Device Controller Capability Parameters */ +/*! @{ */ #define USB_DCCPARAMS_DEN_MASK (0x1FU) #define USB_DCCPARAMS_DEN_SHIFT (0U) #define USB_DCCPARAMS_DEN(x) (((uint32_t)(((uint32_t)(x)) << USB_DCCPARAMS_DEN_SHIFT)) & USB_DCCPARAMS_DEN_MASK) @@ -22358,8 +35878,10 @@ typedef struct { #define USB_DCCPARAMS_HC_MASK (0x100U) #define USB_DCCPARAMS_HC_SHIFT (8U) #define USB_DCCPARAMS_HC(x) (((uint32_t)(((uint32_t)(x)) << USB_DCCPARAMS_HC_SHIFT)) & USB_DCCPARAMS_HC_MASK) +/*! @} */ /*! @name USBCMD - USB Command Register */ +/*! @{ */ #define USB_USBCMD_RS_MASK (0x1U) #define USB_USBCMD_RS_SHIFT (0U) #define USB_USBCMD_RS(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_RS_SHIFT)) & USB_USBCMD_RS_MASK) @@ -22371,9 +35893,17 @@ typedef struct { #define USB_USBCMD_FS_1(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_FS_1_SHIFT)) & USB_USBCMD_FS_1_MASK) #define USB_USBCMD_PSE_MASK (0x10U) #define USB_USBCMD_PSE_SHIFT (4U) +/*! PSE + * 0b0..Do not process the Periodic Schedule + * 0b1..Use the PERIODICLISTBASE register to access the Periodic Schedule. + */ #define USB_USBCMD_PSE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_PSE_SHIFT)) & USB_USBCMD_PSE_MASK) #define USB_USBCMD_ASE_MASK (0x20U) #define USB_USBCMD_ASE_SHIFT (5U) +/*! ASE + * 0b0..Do not process the Asynchronous Schedule. + * 0b1..Use the ASYNCLISTADDR register to access the Asynchronous Schedule. + */ #define USB_USBCMD_ASE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_ASE_SHIFT)) & USB_USBCMD_ASE_MASK) #define USB_USBCMD_IAA_MASK (0x40U) #define USB_USBCMD_IAA_SHIFT (6U) @@ -22392,12 +35922,28 @@ typedef struct { #define USB_USBCMD_SUTW(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_SUTW_SHIFT)) & USB_USBCMD_SUTW_MASK) #define USB_USBCMD_FS_2_MASK (0x8000U) #define USB_USBCMD_FS_2_SHIFT (15U) +/*! FS_2 + * 0b0..1024 elements (4096 bytes) Default value + * 0b1..512 elements (2048 bytes) + */ #define USB_USBCMD_FS_2(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_FS_2_SHIFT)) & USB_USBCMD_FS_2_MASK) #define USB_USBCMD_ITC_MASK (0xFF0000U) #define USB_USBCMD_ITC_SHIFT (16U) +/*! ITC + * 0b00000000..Immediate (no threshold) + * 0b00000001..1 micro-frame + * 0b00000010..2 micro-frames + * 0b00000100..4 micro-frames + * 0b00001000..8 micro-frames + * 0b00010000..16 micro-frames + * 0b00100000..32 micro-frames + * 0b01000000..64 micro-frames + */ #define USB_USBCMD_ITC(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_ITC_SHIFT)) & USB_USBCMD_ITC_MASK) +/*! @} */ /*! @name USBSTS - USB Status Register */ +/*! @{ */ #define USB_USBSTS_UI_MASK (0x1U) #define USB_USBSTS_UI_SHIFT (0U) #define USB_USBSTS_UI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_UI_SHIFT)) & USB_USBSTS_UI_MASK) @@ -22449,8 +35995,10 @@ typedef struct { #define USB_USBSTS_TI1_MASK (0x2000000U) #define USB_USBSTS_TI1_SHIFT (25U) #define USB_USBSTS_TI1(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_TI1_SHIFT)) & USB_USBSTS_TI1_MASK) +/*! @} */ /*! @name USBINTR - Interrupt Enable Register */ +/*! @{ */ #define USB_USBINTR_UE_MASK (0x1U) #define USB_USBINTR_UE_SHIFT (0U) #define USB_USBINTR_UE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_UE_SHIFT)) & USB_USBINTR_UE_MASK) @@ -22496,44 +36044,68 @@ typedef struct { #define USB_USBINTR_TIE1_MASK (0x2000000U) #define USB_USBINTR_TIE1_SHIFT (25U) #define USB_USBINTR_TIE1(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_TIE1_SHIFT)) & USB_USBINTR_TIE1_MASK) +/*! @} */ /*! @name FRINDEX - USB Frame Index */ +/*! @{ */ #define USB_FRINDEX_FRINDEX_MASK (0x3FFFU) #define USB_FRINDEX_FRINDEX_SHIFT (0U) +/*! FRINDEX + * 0b00000000000000..(1024) 12 + * 0b00000000000001..(512) 11 + * 0b00000000000010..(256) 10 + * 0b00000000000011..(128) 9 + * 0b00000000000100..(64) 8 + * 0b00000000000101..(32) 7 + * 0b00000000000110..(16) 6 + * 0b00000000000111..(8) 5 + */ #define USB_FRINDEX_FRINDEX(x) (((uint32_t)(((uint32_t)(x)) << USB_FRINDEX_FRINDEX_SHIFT)) & USB_FRINDEX_FRINDEX_MASK) +/*! @} */ /*! @name DEVICEADDR - Device Address */ +/*! @{ */ #define USB_DEVICEADDR_USBADRA_MASK (0x1000000U) #define USB_DEVICEADDR_USBADRA_SHIFT (24U) #define USB_DEVICEADDR_USBADRA(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVICEADDR_USBADRA_SHIFT)) & USB_DEVICEADDR_USBADRA_MASK) #define USB_DEVICEADDR_USBADR_MASK (0xFE000000U) #define USB_DEVICEADDR_USBADR_SHIFT (25U) #define USB_DEVICEADDR_USBADR(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVICEADDR_USBADR_SHIFT)) & USB_DEVICEADDR_USBADR_MASK) +/*! @} */ /*! @name PERIODICLISTBASE - Frame List Base Address */ +/*! @{ */ #define USB_PERIODICLISTBASE_BASEADR_MASK (0xFFFFF000U) #define USB_PERIODICLISTBASE_BASEADR_SHIFT (12U) #define USB_PERIODICLISTBASE_BASEADR(x) (((uint32_t)(((uint32_t)(x)) << USB_PERIODICLISTBASE_BASEADR_SHIFT)) & USB_PERIODICLISTBASE_BASEADR_MASK) +/*! @} */ /*! @name ASYNCLISTADDR - Next Asynch. Address */ +/*! @{ */ #define USB_ASYNCLISTADDR_ASYBASE_MASK (0xFFFFFFE0U) #define USB_ASYNCLISTADDR_ASYBASE_SHIFT (5U) #define USB_ASYNCLISTADDR_ASYBASE(x) (((uint32_t)(((uint32_t)(x)) << USB_ASYNCLISTADDR_ASYBASE_SHIFT)) & USB_ASYNCLISTADDR_ASYBASE_MASK) +/*! @} */ /*! @name ENDPTLISTADDR - Endpoint List Address */ +/*! @{ */ #define USB_ENDPTLISTADDR_EPBASE_MASK (0xFFFFF800U) #define USB_ENDPTLISTADDR_EPBASE_SHIFT (11U) #define USB_ENDPTLISTADDR_EPBASE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTLISTADDR_EPBASE_SHIFT)) & USB_ENDPTLISTADDR_EPBASE_MASK) +/*! @} */ /*! @name BURSTSIZE - Programmable Burst Size */ +/*! @{ */ #define USB_BURSTSIZE_RXPBURST_MASK (0xFFU) #define USB_BURSTSIZE_RXPBURST_SHIFT (0U) #define USB_BURSTSIZE_RXPBURST(x) (((uint32_t)(((uint32_t)(x)) << USB_BURSTSIZE_RXPBURST_SHIFT)) & USB_BURSTSIZE_RXPBURST_MASK) #define USB_BURSTSIZE_TXPBURST_MASK (0x1FF00U) #define USB_BURSTSIZE_TXPBURST_SHIFT (8U) #define USB_BURSTSIZE_TXPBURST(x) (((uint32_t)(((uint32_t)(x)) << USB_BURSTSIZE_TXPBURST_SHIFT)) & USB_BURSTSIZE_TXPBURST_MASK) +/*! @} */ /*! @name TXFILLTUNING - TX FIFO Fill Tuning */ +/*! @{ */ #define USB_TXFILLTUNING_TXSCHOH_MASK (0xFFU) #define USB_TXFILLTUNING_TXSCHOH_SHIFT (0U) #define USB_TXFILLTUNING_TXSCHOH(x) (((uint32_t)(((uint32_t)(x)) << USB_TXFILLTUNING_TXSCHOH_SHIFT)) & USB_TXFILLTUNING_TXSCHOH_MASK) @@ -22543,29 +36115,41 @@ typedef struct { #define USB_TXFILLTUNING_TXFIFOTHRES_MASK (0x3F0000U) #define USB_TXFILLTUNING_TXFIFOTHRES_SHIFT (16U) #define USB_TXFILLTUNING_TXFIFOTHRES(x) (((uint32_t)(((uint32_t)(x)) << USB_TXFILLTUNING_TXFIFOTHRES_SHIFT)) & USB_TXFILLTUNING_TXFIFOTHRES_MASK) +/*! @} */ /*! @name ENDPTNAK - Endpoint NAK */ +/*! @{ */ #define USB_ENDPTNAK_EPRN_MASK (0xFFU) #define USB_ENDPTNAK_EPRN_SHIFT (0U) #define USB_ENDPTNAK_EPRN(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTNAK_EPRN_SHIFT)) & USB_ENDPTNAK_EPRN_MASK) #define USB_ENDPTNAK_EPTN_MASK (0xFF0000U) #define USB_ENDPTNAK_EPTN_SHIFT (16U) #define USB_ENDPTNAK_EPTN(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTNAK_EPTN_SHIFT)) & USB_ENDPTNAK_EPTN_MASK) +/*! @} */ /*! @name ENDPTNAKEN - Endpoint NAK Enable */ +/*! @{ */ #define USB_ENDPTNAKEN_EPRNE_MASK (0xFFU) #define USB_ENDPTNAKEN_EPRNE_SHIFT (0U) #define USB_ENDPTNAKEN_EPRNE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTNAKEN_EPRNE_SHIFT)) & USB_ENDPTNAKEN_EPRNE_MASK) #define USB_ENDPTNAKEN_EPTNE_MASK (0xFF0000U) #define USB_ENDPTNAKEN_EPTNE_SHIFT (16U) #define USB_ENDPTNAKEN_EPTNE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTNAKEN_EPTNE_SHIFT)) & USB_ENDPTNAKEN_EPTNE_MASK) +/*! @} */ /*! @name CONFIGFLAG - Configure Flag Register */ +/*! @{ */ #define USB_CONFIGFLAG_CF_MASK (0x1U) #define USB_CONFIGFLAG_CF_SHIFT (0U) +/*! CF + * 0b0..Port routing control logic default-routes each port to an implementation dependent classic host controller. + * 0b1..Port routing control logic default-routes all ports to this host controller. + */ #define USB_CONFIGFLAG_CF(x) (((uint32_t)(((uint32_t)(x)) << USB_CONFIGFLAG_CF_SHIFT)) & USB_CONFIGFLAG_CF_MASK) +/*! @} */ /*! @name PORTSC1 - Port Status & Control */ +/*! @{ */ #define USB_PORTSC1_CCS_MASK (0x1U) #define USB_PORTSC1_CCS_SHIFT (0U) #define USB_PORTSC1_CCS(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_CCS_SHIFT)) & USB_PORTSC1_CCS_MASK) @@ -22580,6 +36164,10 @@ typedef struct { #define USB_PORTSC1_PEC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PEC_SHIFT)) & USB_PORTSC1_PEC_MASK) #define USB_PORTSC1_OCA_MASK (0x10U) #define USB_PORTSC1_OCA_SHIFT (4U) +/*! OCA + * 0b1..This port currently has an over-current condition + * 0b0..This port does not have an over-current condition. + */ #define USB_PORTSC1_OCA(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_OCA_SHIFT)) & USB_PORTSC1_OCA_MASK) #define USB_PORTSC1_OCC_MASK (0x20U) #define USB_PORTSC1_OCC_SHIFT (5U) @@ -22598,6 +36186,12 @@ typedef struct { #define USB_PORTSC1_HSP(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_HSP_SHIFT)) & USB_PORTSC1_HSP_MASK) #define USB_PORTSC1_LS_MASK (0xC00U) #define USB_PORTSC1_LS_SHIFT (10U) +/*! LS + * 0b00..SE0 + * 0b10..J-state + * 0b01..K-state + * 0b11..Undefined + */ #define USB_PORTSC1_LS(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_LS_SHIFT)) & USB_PORTSC1_LS_MASK) #define USB_PORTSC1_PP_MASK (0x1000U) #define USB_PORTSC1_PP_SHIFT (12U) @@ -22607,9 +36201,25 @@ typedef struct { #define USB_PORTSC1_PO(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PO_SHIFT)) & USB_PORTSC1_PO_MASK) #define USB_PORTSC1_PIC_MASK (0xC000U) #define USB_PORTSC1_PIC_SHIFT (14U) +/*! PIC + * 0b00..Port indicators are off + * 0b01..Amber + * 0b10..Green + * 0b11..Undefined + */ #define USB_PORTSC1_PIC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PIC_SHIFT)) & USB_PORTSC1_PIC_MASK) #define USB_PORTSC1_PTC_MASK (0xF0000U) #define USB_PORTSC1_PTC_SHIFT (16U) +/*! PTC + * 0b0000..TEST_MODE_DISABLE + * 0b0001..J_STATE + * 0b0010..K_STATE + * 0b0011..SE0 (host) / NAK (device) + * 0b0100..Packet + * 0b0101..FORCE_ENABLE_HS + * 0b0110..FORCE_ENABLE_FS + * 0b0111..FORCE_ENABLE_LS + */ #define USB_PORTSC1_PTC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PTC_SHIFT)) & USB_PORTSC1_PTC_MASK) #define USB_PORTSC1_WKCN_MASK (0x100000U) #define USB_PORTSC1_WKCN_SHIFT (20U) @@ -22622,18 +36232,36 @@ typedef struct { #define USB_PORTSC1_WKOC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_WKOC_SHIFT)) & USB_PORTSC1_WKOC_MASK) #define USB_PORTSC1_PHCD_MASK (0x800000U) #define USB_PORTSC1_PHCD_SHIFT (23U) +/*! PHCD + * 0b1..Disable PHY clock + * 0b0..Enable PHY clock + */ #define USB_PORTSC1_PHCD(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PHCD_SHIFT)) & USB_PORTSC1_PHCD_MASK) #define USB_PORTSC1_PFSC_MASK (0x1000000U) #define USB_PORTSC1_PFSC_SHIFT (24U) +/*! PFSC + * 0b1..Forced to full speed + * 0b0..Normal operation + */ #define USB_PORTSC1_PFSC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PFSC_SHIFT)) & USB_PORTSC1_PFSC_MASK) #define USB_PORTSC1_PTS_2_MASK (0x2000000U) #define USB_PORTSC1_PTS_2_SHIFT (25U) #define USB_PORTSC1_PTS_2(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PTS_2_SHIFT)) & USB_PORTSC1_PTS_2_MASK) #define USB_PORTSC1_PSPD_MASK (0xC000000U) #define USB_PORTSC1_PSPD_SHIFT (26U) +/*! PSPD + * 0b00..Full Speed + * 0b01..Low Speed + * 0b10..High Speed + * 0b11..Undefined + */ #define USB_PORTSC1_PSPD(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PSPD_SHIFT)) & USB_PORTSC1_PSPD_MASK) #define USB_PORTSC1_PTW_MASK (0x10000000U) #define USB_PORTSC1_PTW_SHIFT (28U) +/*! PTW + * 0b0..Select the 8-bit UTMI interface [60MHz] + * 0b1..Select the 16-bit UTMI interface [30MHz] + */ #define USB_PORTSC1_PTW(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PTW_SHIFT)) & USB_PORTSC1_PTW_MASK) #define USB_PORTSC1_STS_MASK (0x20000000U) #define USB_PORTSC1_STS_SHIFT (29U) @@ -22641,8 +36269,10 @@ typedef struct { #define USB_PORTSC1_PTS_1_MASK (0xC0000000U) #define USB_PORTSC1_PTS_1_SHIFT (30U) #define USB_PORTSC1_PTS_1(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PTS_1_SHIFT)) & USB_PORTSC1_PTS_1_MASK) +/*! @} */ /*! @name OTGSC - On-The-Go Status & control */ +/*! @{ */ #define USB_OTGSC_VD_MASK (0x1U) #define USB_OTGSC_VD_SHIFT (0U) #define USB_OTGSC_VD(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_VD_SHIFT)) & USB_OTGSC_VD_MASK) @@ -22721,59 +36351,87 @@ typedef struct { #define USB_OTGSC_DPIE_MASK (0x40000000U) #define USB_OTGSC_DPIE_SHIFT (30U) #define USB_OTGSC_DPIE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_DPIE_SHIFT)) & USB_OTGSC_DPIE_MASK) +/*! @} */ /*! @name USBMODE - USB Device Mode */ +/*! @{ */ #define USB_USBMODE_CM_MASK (0x3U) #define USB_USBMODE_CM_SHIFT (0U) +/*! CM + * 0b00..Idle [Default for combination host/device] + * 0b01..Reserved + * 0b10..Device Controller [Default for device only controller] + * 0b11..Host Controller [Default for host only controller] + */ #define USB_USBMODE_CM(x) (((uint32_t)(((uint32_t)(x)) << USB_USBMODE_CM_SHIFT)) & USB_USBMODE_CM_MASK) #define USB_USBMODE_ES_MASK (0x4U) #define USB_USBMODE_ES_SHIFT (2U) +/*! ES + * 0b0..Little Endian [Default] + * 0b1..Big Endian + */ #define USB_USBMODE_ES(x) (((uint32_t)(((uint32_t)(x)) << USB_USBMODE_ES_SHIFT)) & USB_USBMODE_ES_MASK) #define USB_USBMODE_SLOM_MASK (0x8U) #define USB_USBMODE_SLOM_SHIFT (3U) +/*! SLOM + * 0b0..Setup Lockouts On (default); + * 0b1..Setup Lockouts Off (DCD requires use of Setup Data Buffer Tripwire in USBCMDUSB Command Register . + */ #define USB_USBMODE_SLOM(x) (((uint32_t)(((uint32_t)(x)) << USB_USBMODE_SLOM_SHIFT)) & USB_USBMODE_SLOM_MASK) #define USB_USBMODE_SDIS_MASK (0x10U) #define USB_USBMODE_SDIS_SHIFT (4U) #define USB_USBMODE_SDIS(x) (((uint32_t)(((uint32_t)(x)) << USB_USBMODE_SDIS_SHIFT)) & USB_USBMODE_SDIS_MASK) +/*! @} */ /*! @name ENDPTSETUPSTAT - Endpoint Setup Status */ +/*! @{ */ #define USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_MASK (0xFFFFU) #define USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_SHIFT (0U) #define USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_SHIFT)) & USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_MASK) +/*! @} */ /*! @name ENDPTPRIME - Endpoint Prime */ +/*! @{ */ #define USB_ENDPTPRIME_PERB_MASK (0xFFU) #define USB_ENDPTPRIME_PERB_SHIFT (0U) #define USB_ENDPTPRIME_PERB(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTPRIME_PERB_SHIFT)) & USB_ENDPTPRIME_PERB_MASK) #define USB_ENDPTPRIME_PETB_MASK (0xFF0000U) #define USB_ENDPTPRIME_PETB_SHIFT (16U) #define USB_ENDPTPRIME_PETB(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTPRIME_PETB_SHIFT)) & USB_ENDPTPRIME_PETB_MASK) +/*! @} */ /*! @name ENDPTFLUSH - Endpoint Flush */ +/*! @{ */ #define USB_ENDPTFLUSH_FERB_MASK (0xFFU) #define USB_ENDPTFLUSH_FERB_SHIFT (0U) #define USB_ENDPTFLUSH_FERB(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTFLUSH_FERB_SHIFT)) & USB_ENDPTFLUSH_FERB_MASK) #define USB_ENDPTFLUSH_FETB_MASK (0xFF0000U) #define USB_ENDPTFLUSH_FETB_SHIFT (16U) #define USB_ENDPTFLUSH_FETB(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTFLUSH_FETB_SHIFT)) & USB_ENDPTFLUSH_FETB_MASK) +/*! @} */ /*! @name ENDPTSTAT - Endpoint Status */ +/*! @{ */ #define USB_ENDPTSTAT_ERBR_MASK (0xFFU) #define USB_ENDPTSTAT_ERBR_SHIFT (0U) #define USB_ENDPTSTAT_ERBR(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTSTAT_ERBR_SHIFT)) & USB_ENDPTSTAT_ERBR_MASK) #define USB_ENDPTSTAT_ETBR_MASK (0xFF0000U) #define USB_ENDPTSTAT_ETBR_SHIFT (16U) #define USB_ENDPTSTAT_ETBR(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTSTAT_ETBR_SHIFT)) & USB_ENDPTSTAT_ETBR_MASK) +/*! @} */ /*! @name ENDPTCOMPLETE - Endpoint Complete */ +/*! @{ */ #define USB_ENDPTCOMPLETE_ERCE_MASK (0xFFU) #define USB_ENDPTCOMPLETE_ERCE_SHIFT (0U) #define USB_ENDPTCOMPLETE_ERCE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCOMPLETE_ERCE_SHIFT)) & USB_ENDPTCOMPLETE_ERCE_MASK) #define USB_ENDPTCOMPLETE_ETCE_MASK (0xFF0000U) #define USB_ENDPTCOMPLETE_ETCE_SHIFT (16U) #define USB_ENDPTCOMPLETE_ETCE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCOMPLETE_ETCE_SHIFT)) & USB_ENDPTCOMPLETE_ETCE_MASK) +/*! @} */ /*! @name ENDPTCTRL0 - Endpoint Control0 */ +/*! @{ */ #define USB_ENDPTCTRL0_RXS_MASK (0x1U) #define USB_ENDPTCTRL0_RXS_SHIFT (0U) #define USB_ENDPTCTRL0_RXS(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_RXS_SHIFT)) & USB_ENDPTCTRL0_RXS_MASK) @@ -22792,8 +36450,10 @@ typedef struct { #define USB_ENDPTCTRL0_TXE_MASK (0x800000U) #define USB_ENDPTCTRL0_TXE_SHIFT (23U) #define USB_ENDPTCTRL0_TXE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_TXE_SHIFT)) & USB_ENDPTCTRL0_TXE_MASK) +/*! @} */ /*! @name ENDPTCTRL - Endpoint Control 1..Endpoint Control 7 */ +/*! @{ */ #define USB_ENDPTCTRL_RXS_MASK (0x1U) #define USB_ENDPTCTRL_RXS_SHIFT (0U) #define USB_ENDPTCTRL_RXS(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXS_SHIFT)) & USB_ENDPTCTRL_RXS_MASK) @@ -22830,6 +36490,7 @@ typedef struct { #define USB_ENDPTCTRL_TXE_MASK (0x800000U) #define USB_ENDPTCTRL_TXE_SHIFT (23U) #define USB_ENDPTCTRL_TXE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXE_SHIFT)) & USB_ENDPTCTRL_TXE_MASK) +/*! @} */ /* The count of USB_ENDPTCTRL */ #define USB_ENDPTCTRL_COUNT (7U) @@ -23459,41 +37120,89 @@ typedef struct { */ /*! @name USB_OTGn_CTRL - USB OTG1 Control Register..USB OTG2 Control Register */ +/*! @{ */ #define USBNC_USB_OTGn_CTRL_OVER_CUR_DIS_MASK (0x80U) #define USBNC_USB_OTGn_CTRL_OVER_CUR_DIS_SHIFT (7U) +/*! OVER_CUR_DIS + * 0b1..Disables overcurrent detection + * 0b0..Enables overcurrent detection + */ #define USBNC_USB_OTGn_CTRL_OVER_CUR_DIS(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_OVER_CUR_DIS_SHIFT)) & USBNC_USB_OTGn_CTRL_OVER_CUR_DIS_MASK) #define USBNC_USB_OTGn_CTRL_OVER_CUR_POL_MASK (0x100U) #define USBNC_USB_OTGn_CTRL_OVER_CUR_POL_SHIFT (8U) +/*! OVER_CUR_POL + * 0b1..Low active (low on this signal represents an overcurrent condition) + * 0b0..High active (high on this signal represents an overcurrent condition) + */ #define USBNC_USB_OTGn_CTRL_OVER_CUR_POL(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_OVER_CUR_POL_SHIFT)) & USBNC_USB_OTGn_CTRL_OVER_CUR_POL_MASK) #define USBNC_USB_OTGn_CTRL_PWR_POL_MASK (0x200U) #define USBNC_USB_OTGn_CTRL_PWR_POL_SHIFT (9U) +/*! PWR_POL + * 0b1..PMIC Power Pin is High active. + * 0b0..PMIC Power Pin is Low active. + */ #define USBNC_USB_OTGn_CTRL_PWR_POL(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_PWR_POL_SHIFT)) & USBNC_USB_OTGn_CTRL_PWR_POL_MASK) #define USBNC_USB_OTGn_CTRL_WIE_MASK (0x400U) #define USBNC_USB_OTGn_CTRL_WIE_SHIFT (10U) +/*! WIE + * 0b1..Interrupt Enabled + * 0b0..Interrupt Disabled + */ #define USBNC_USB_OTGn_CTRL_WIE(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_WIE_SHIFT)) & USBNC_USB_OTGn_CTRL_WIE_MASK) #define USBNC_USB_OTGn_CTRL_WKUP_SW_EN_MASK (0x4000U) #define USBNC_USB_OTGn_CTRL_WKUP_SW_EN_SHIFT (14U) +/*! WKUP_SW_EN + * 0b1..Enable + * 0b0..Disable + */ #define USBNC_USB_OTGn_CTRL_WKUP_SW_EN(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_WKUP_SW_EN_SHIFT)) & USBNC_USB_OTGn_CTRL_WKUP_SW_EN_MASK) #define USBNC_USB_OTGn_CTRL_WKUP_SW_MASK (0x8000U) #define USBNC_USB_OTGn_CTRL_WKUP_SW_SHIFT (15U) +/*! WKUP_SW + * 0b1..Force wake-up + * 0b0..Inactive + */ #define USBNC_USB_OTGn_CTRL_WKUP_SW(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_WKUP_SW_SHIFT)) & USBNC_USB_OTGn_CTRL_WKUP_SW_MASK) #define USBNC_USB_OTGn_CTRL_WKUP_ID_EN_MASK (0x10000U) #define USBNC_USB_OTGn_CTRL_WKUP_ID_EN_SHIFT (16U) +/*! WKUP_ID_EN + * 0b1..Enable + * 0b0..Disable + */ #define USBNC_USB_OTGn_CTRL_WKUP_ID_EN(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_WKUP_ID_EN_SHIFT)) & USBNC_USB_OTGn_CTRL_WKUP_ID_EN_MASK) #define USBNC_USB_OTGn_CTRL_WKUP_VBUS_EN_MASK (0x20000U) #define USBNC_USB_OTGn_CTRL_WKUP_VBUS_EN_SHIFT (17U) +/*! WKUP_VBUS_EN + * 0b1..Enable + * 0b0..Disable + */ #define USBNC_USB_OTGn_CTRL_WKUP_VBUS_EN(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_WKUP_VBUS_EN_SHIFT)) & USBNC_USB_OTGn_CTRL_WKUP_VBUS_EN_MASK) #define USBNC_USB_OTGn_CTRL_WKUP_DPDM_EN_MASK (0x20000000U) #define USBNC_USB_OTGn_CTRL_WKUP_DPDM_EN_SHIFT (29U) +/*! WKUP_DPDM_EN + * 0b1..(Default) DPDM changes wake-up to be enabled, it is for device only. + * 0b0..DPDM changes wake-up to be disabled only when VBUS is 0. + */ #define USBNC_USB_OTGn_CTRL_WKUP_DPDM_EN(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_WKUP_DPDM_EN_SHIFT)) & USBNC_USB_OTGn_CTRL_WKUP_DPDM_EN_MASK) #define USBNC_USB_OTGn_CTRL_WIR_MASK (0x80000000U) #define USBNC_USB_OTGn_CTRL_WIR_SHIFT (31U) +/*! WIR + * 0b1..Wake-up Interrupt Request received + * 0b0..No wake-up interrupt request received + */ #define USBNC_USB_OTGn_CTRL_WIR(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_WIR_SHIFT)) & USBNC_USB_OTGn_CTRL_WIR_MASK) +/*! @} */ /*! @name USB_OTGn_PHY_CTRL_0 - OTG1 UTMI PHY Control 0 Register..OTG2 UTMI PHY Control 0 Register */ +/*! @{ */ #define USBNC_USB_OTGn_PHY_CTRL_0_UTMI_CLK_VLD_MASK (0x80000000U) #define USBNC_USB_OTGn_PHY_CTRL_0_UTMI_CLK_VLD_SHIFT (31U) +/*! UTMI_CLK_VLD + * 0b1..Valid + * 0b0..Invalid + */ #define USBNC_USB_OTGn_PHY_CTRL_0_UTMI_CLK_VLD(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_PHY_CTRL_0_UTMI_CLK_VLD_SHIFT)) & USBNC_USB_OTGn_PHY_CTRL_0_UTMI_CLK_VLD_MASK) +/*! @} */ /*! @@ -23572,6 +37281,7 @@ typedef struct { */ /*! @name PWD - USB PHY Power-Down Register */ +/*! @{ */ #define USBPHY_PWD_RSVD0_MASK (0x3FFU) #define USBPHY_PWD_RSVD0_SHIFT (0U) #define USBPHY_PWD_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RSVD0_SHIFT)) & USBPHY_PWD_RSVD0_MASK) @@ -23602,8 +37312,10 @@ typedef struct { #define USBPHY_PWD_RSVD2_MASK (0xFFE00000U) #define USBPHY_PWD_RSVD2_SHIFT (21U) #define USBPHY_PWD_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RSVD2_SHIFT)) & USBPHY_PWD_RSVD2_MASK) +/*! @} */ /*! @name PWD_SET - USB PHY Power-Down Register */ +/*! @{ */ #define USBPHY_PWD_SET_RSVD0_MASK (0x3FFU) #define USBPHY_PWD_SET_RSVD0_SHIFT (0U) #define USBPHY_PWD_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RSVD0_SHIFT)) & USBPHY_PWD_SET_RSVD0_MASK) @@ -23634,8 +37346,10 @@ typedef struct { #define USBPHY_PWD_SET_RSVD2_MASK (0xFFE00000U) #define USBPHY_PWD_SET_RSVD2_SHIFT (21U) #define USBPHY_PWD_SET_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RSVD2_SHIFT)) & USBPHY_PWD_SET_RSVD2_MASK) +/*! @} */ /*! @name PWD_CLR - USB PHY Power-Down Register */ +/*! @{ */ #define USBPHY_PWD_CLR_RSVD0_MASK (0x3FFU) #define USBPHY_PWD_CLR_RSVD0_SHIFT (0U) #define USBPHY_PWD_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RSVD0_SHIFT)) & USBPHY_PWD_CLR_RSVD0_MASK) @@ -23666,8 +37380,10 @@ typedef struct { #define USBPHY_PWD_CLR_RSVD2_MASK (0xFFE00000U) #define USBPHY_PWD_CLR_RSVD2_SHIFT (21U) #define USBPHY_PWD_CLR_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RSVD2_SHIFT)) & USBPHY_PWD_CLR_RSVD2_MASK) +/*! @} */ /*! @name PWD_TOG - USB PHY Power-Down Register */ +/*! @{ */ #define USBPHY_PWD_TOG_RSVD0_MASK (0x3FFU) #define USBPHY_PWD_TOG_RSVD0_SHIFT (0U) #define USBPHY_PWD_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RSVD0_SHIFT)) & USBPHY_PWD_TOG_RSVD0_MASK) @@ -23698,8 +37414,10 @@ typedef struct { #define USBPHY_PWD_TOG_RSVD2_MASK (0xFFE00000U) #define USBPHY_PWD_TOG_RSVD2_SHIFT (21U) #define USBPHY_PWD_TOG_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RSVD2_SHIFT)) & USBPHY_PWD_TOG_RSVD2_MASK) +/*! @} */ /*! @name TX - USB PHY Transmitter Control Register */ +/*! @{ */ #define USBPHY_TX_D_CAL_MASK (0xFU) #define USBPHY_TX_D_CAL_SHIFT (0U) #define USBPHY_TX_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_D_CAL_SHIFT)) & USBPHY_TX_D_CAL_MASK) @@ -23724,8 +37442,10 @@ typedef struct { #define USBPHY_TX_RSVD5_MASK (0xE0000000U) #define USBPHY_TX_RSVD5_SHIFT (29U) #define USBPHY_TX_RSVD5(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_RSVD5_SHIFT)) & USBPHY_TX_RSVD5_MASK) +/*! @} */ /*! @name TX_SET - USB PHY Transmitter Control Register */ +/*! @{ */ #define USBPHY_TX_SET_D_CAL_MASK (0xFU) #define USBPHY_TX_SET_D_CAL_SHIFT (0U) #define USBPHY_TX_SET_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_D_CAL_SHIFT)) & USBPHY_TX_SET_D_CAL_MASK) @@ -23750,8 +37470,10 @@ typedef struct { #define USBPHY_TX_SET_RSVD5_MASK (0xE0000000U) #define USBPHY_TX_SET_RSVD5_SHIFT (29U) #define USBPHY_TX_SET_RSVD5(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_RSVD5_SHIFT)) & USBPHY_TX_SET_RSVD5_MASK) +/*! @} */ /*! @name TX_CLR - USB PHY Transmitter Control Register */ +/*! @{ */ #define USBPHY_TX_CLR_D_CAL_MASK (0xFU) #define USBPHY_TX_CLR_D_CAL_SHIFT (0U) #define USBPHY_TX_CLR_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_D_CAL_SHIFT)) & USBPHY_TX_CLR_D_CAL_MASK) @@ -23776,8 +37498,10 @@ typedef struct { #define USBPHY_TX_CLR_RSVD5_MASK (0xE0000000U) #define USBPHY_TX_CLR_RSVD5_SHIFT (29U) #define USBPHY_TX_CLR_RSVD5(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_RSVD5_SHIFT)) & USBPHY_TX_CLR_RSVD5_MASK) +/*! @} */ /*! @name TX_TOG - USB PHY Transmitter Control Register */ +/*! @{ */ #define USBPHY_TX_TOG_D_CAL_MASK (0xFU) #define USBPHY_TX_TOG_D_CAL_SHIFT (0U) #define USBPHY_TX_TOG_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_D_CAL_SHIFT)) & USBPHY_TX_TOG_D_CAL_MASK) @@ -23802,8 +37526,10 @@ typedef struct { #define USBPHY_TX_TOG_RSVD5_MASK (0xE0000000U) #define USBPHY_TX_TOG_RSVD5_SHIFT (29U) #define USBPHY_TX_TOG_RSVD5(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_RSVD5_SHIFT)) & USBPHY_TX_TOG_RSVD5_MASK) +/*! @} */ /*! @name RX - USB PHY Receiver Control Register */ +/*! @{ */ #define USBPHY_RX_ENVADJ_MASK (0x7U) #define USBPHY_RX_ENVADJ_SHIFT (0U) #define USBPHY_RX_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_ENVADJ_SHIFT)) & USBPHY_RX_ENVADJ_MASK) @@ -23822,8 +37548,10 @@ typedef struct { #define USBPHY_RX_RSVD2_MASK (0xFF800000U) #define USBPHY_RX_RSVD2_SHIFT (23U) #define USBPHY_RX_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_RSVD2_SHIFT)) & USBPHY_RX_RSVD2_MASK) +/*! @} */ /*! @name RX_SET - USB PHY Receiver Control Register */ +/*! @{ */ #define USBPHY_RX_SET_ENVADJ_MASK (0x7U) #define USBPHY_RX_SET_ENVADJ_SHIFT (0U) #define USBPHY_RX_SET_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_ENVADJ_SHIFT)) & USBPHY_RX_SET_ENVADJ_MASK) @@ -23842,8 +37570,10 @@ typedef struct { #define USBPHY_RX_SET_RSVD2_MASK (0xFF800000U) #define USBPHY_RX_SET_RSVD2_SHIFT (23U) #define USBPHY_RX_SET_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_RSVD2_SHIFT)) & USBPHY_RX_SET_RSVD2_MASK) +/*! @} */ /*! @name RX_CLR - USB PHY Receiver Control Register */ +/*! @{ */ #define USBPHY_RX_CLR_ENVADJ_MASK (0x7U) #define USBPHY_RX_CLR_ENVADJ_SHIFT (0U) #define USBPHY_RX_CLR_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_ENVADJ_SHIFT)) & USBPHY_RX_CLR_ENVADJ_MASK) @@ -23862,8 +37592,10 @@ typedef struct { #define USBPHY_RX_CLR_RSVD2_MASK (0xFF800000U) #define USBPHY_RX_CLR_RSVD2_SHIFT (23U) #define USBPHY_RX_CLR_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_RSVD2_SHIFT)) & USBPHY_RX_CLR_RSVD2_MASK) +/*! @} */ /*! @name RX_TOG - USB PHY Receiver Control Register */ +/*! @{ */ #define USBPHY_RX_TOG_ENVADJ_MASK (0x7U) #define USBPHY_RX_TOG_ENVADJ_SHIFT (0U) #define USBPHY_RX_TOG_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_ENVADJ_SHIFT)) & USBPHY_RX_TOG_ENVADJ_MASK) @@ -23882,8 +37614,10 @@ typedef struct { #define USBPHY_RX_TOG_RSVD2_MASK (0xFF800000U) #define USBPHY_RX_TOG_RSVD2_SHIFT (23U) #define USBPHY_RX_TOG_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_RSVD2_SHIFT)) & USBPHY_RX_TOG_RSVD2_MASK) +/*! @} */ /*! @name CTRL - USB PHY General Control Register */ +/*! @{ */ #define USBPHY_CTRL_ENOTG_ID_CHG_IRQ_MASK (0x1U) #define USBPHY_CTRL_ENOTG_ID_CHG_IRQ_SHIFT (0U) #define USBPHY_CTRL_ENOTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENOTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_ENOTG_ID_CHG_IRQ_MASK) @@ -23977,8 +37711,10 @@ typedef struct { #define USBPHY_CTRL_SFTRST_MASK (0x80000000U) #define USBPHY_CTRL_SFTRST_SHIFT (31U) #define USBPHY_CTRL_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SFTRST_SHIFT)) & USBPHY_CTRL_SFTRST_MASK) +/*! @} */ /*! @name CTRL_SET - USB PHY General Control Register */ +/*! @{ */ #define USBPHY_CTRL_SET_ENOTG_ID_CHG_IRQ_MASK (0x1U) #define USBPHY_CTRL_SET_ENOTG_ID_CHG_IRQ_SHIFT (0U) #define USBPHY_CTRL_SET_ENOTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENOTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_SET_ENOTG_ID_CHG_IRQ_MASK) @@ -24072,8 +37808,10 @@ typedef struct { #define USBPHY_CTRL_SET_SFTRST_MASK (0x80000000U) #define USBPHY_CTRL_SET_SFTRST_SHIFT (31U) #define USBPHY_CTRL_SET_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_SFTRST_SHIFT)) & USBPHY_CTRL_SET_SFTRST_MASK) +/*! @} */ /*! @name CTRL_CLR - USB PHY General Control Register */ +/*! @{ */ #define USBPHY_CTRL_CLR_ENOTG_ID_CHG_IRQ_MASK (0x1U) #define USBPHY_CTRL_CLR_ENOTG_ID_CHG_IRQ_SHIFT (0U) #define USBPHY_CTRL_CLR_ENOTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENOTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_CLR_ENOTG_ID_CHG_IRQ_MASK) @@ -24167,8 +37905,10 @@ typedef struct { #define USBPHY_CTRL_CLR_SFTRST_MASK (0x80000000U) #define USBPHY_CTRL_CLR_SFTRST_SHIFT (31U) #define USBPHY_CTRL_CLR_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_SFTRST_SHIFT)) & USBPHY_CTRL_CLR_SFTRST_MASK) +/*! @} */ /*! @name CTRL_TOG - USB PHY General Control Register */ +/*! @{ */ #define USBPHY_CTRL_TOG_ENOTG_ID_CHG_IRQ_MASK (0x1U) #define USBPHY_CTRL_TOG_ENOTG_ID_CHG_IRQ_SHIFT (0U) #define USBPHY_CTRL_TOG_ENOTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENOTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_TOG_ENOTG_ID_CHG_IRQ_MASK) @@ -24262,8 +38002,10 @@ typedef struct { #define USBPHY_CTRL_TOG_SFTRST_MASK (0x80000000U) #define USBPHY_CTRL_TOG_SFTRST_SHIFT (31U) #define USBPHY_CTRL_TOG_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_SFTRST_SHIFT)) & USBPHY_CTRL_TOG_SFTRST_MASK) +/*! @} */ /*! @name STATUS - USB PHY Status Register */ +/*! @{ */ #define USBPHY_STATUS_RSVD0_MASK (0x7U) #define USBPHY_STATUS_RSVD0_SHIFT (0U) #define USBPHY_STATUS_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_RSVD0_SHIFT)) & USBPHY_STATUS_RSVD0_MASK) @@ -24291,8 +38033,10 @@ typedef struct { #define USBPHY_STATUS_RSVD4_MASK (0xFFFFF800U) #define USBPHY_STATUS_RSVD4_SHIFT (11U) #define USBPHY_STATUS_RSVD4(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_RSVD4_SHIFT)) & USBPHY_STATUS_RSVD4_MASK) +/*! @} */ /*! @name DEBUG - USB PHY Debug Register */ +/*! @{ */ #define USBPHY_DEBUG_OTGIDPIOLOCK_MASK (0x1U) #define USBPHY_DEBUG_OTGIDPIOLOCK_SHIFT (0U) #define USBPHY_DEBUG_OTGIDPIOLOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG_OTGIDPIOLOCK_MASK) @@ -24338,8 +38082,10 @@ typedef struct { #define USBPHY_DEBUG_RSVD3_MASK (0x80000000U) #define USBPHY_DEBUG_RSVD3_SHIFT (31U) #define USBPHY_DEBUG_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_RSVD3_SHIFT)) & USBPHY_DEBUG_RSVD3_MASK) +/*! @} */ /*! @name DEBUG_SET - USB PHY Debug Register */ +/*! @{ */ #define USBPHY_DEBUG_SET_OTGIDPIOLOCK_MASK (0x1U) #define USBPHY_DEBUG_SET_OTGIDPIOLOCK_SHIFT (0U) #define USBPHY_DEBUG_SET_OTGIDPIOLOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG_SET_OTGIDPIOLOCK_MASK) @@ -24385,8 +38131,10 @@ typedef struct { #define USBPHY_DEBUG_SET_RSVD3_MASK (0x80000000U) #define USBPHY_DEBUG_SET_RSVD3_SHIFT (31U) #define USBPHY_DEBUG_SET_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_RSVD3_SHIFT)) & USBPHY_DEBUG_SET_RSVD3_MASK) +/*! @} */ /*! @name DEBUG_CLR - USB PHY Debug Register */ +/*! @{ */ #define USBPHY_DEBUG_CLR_OTGIDPIOLOCK_MASK (0x1U) #define USBPHY_DEBUG_CLR_OTGIDPIOLOCK_SHIFT (0U) #define USBPHY_DEBUG_CLR_OTGIDPIOLOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG_CLR_OTGIDPIOLOCK_MASK) @@ -24432,8 +38180,10 @@ typedef struct { #define USBPHY_DEBUG_CLR_RSVD3_MASK (0x80000000U) #define USBPHY_DEBUG_CLR_RSVD3_SHIFT (31U) #define USBPHY_DEBUG_CLR_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_RSVD3_SHIFT)) & USBPHY_DEBUG_CLR_RSVD3_MASK) +/*! @} */ /*! @name DEBUG_TOG - USB PHY Debug Register */ +/*! @{ */ #define USBPHY_DEBUG_TOG_OTGIDPIOLOCK_MASK (0x1U) #define USBPHY_DEBUG_TOG_OTGIDPIOLOCK_SHIFT (0U) #define USBPHY_DEBUG_TOG_OTGIDPIOLOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG_TOG_OTGIDPIOLOCK_MASK) @@ -24479,8 +38229,10 @@ typedef struct { #define USBPHY_DEBUG_TOG_RSVD3_MASK (0x80000000U) #define USBPHY_DEBUG_TOG_RSVD3_SHIFT (31U) #define USBPHY_DEBUG_TOG_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_RSVD3_SHIFT)) & USBPHY_DEBUG_TOG_RSVD3_MASK) +/*! @} */ /*! @name DEBUG0_STATUS - UTMI Debug Status Register 0 */ +/*! @{ */ #define USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT_MASK (0xFFFFU) #define USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT_SHIFT (0U) #define USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT_SHIFT)) & USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT_MASK) @@ -24490,8 +38242,10 @@ typedef struct { #define USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_MASK (0xFC000000U) #define USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_SHIFT (26U) #define USBPHY_DEBUG0_STATUS_SQUELCH_COUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_SHIFT)) & USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_MASK) +/*! @} */ /*! @name DEBUG1 - UTMI Debug Status Register 1 */ +/*! @{ */ #define USBPHY_DEBUG1_RSVD0_MASK (0x1FFFU) #define USBPHY_DEBUG1_RSVD0_SHIFT (0U) #define USBPHY_DEBUG1_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_RSVD0_SHIFT)) & USBPHY_DEBUG1_RSVD0_MASK) @@ -24501,8 +38255,10 @@ typedef struct { #define USBPHY_DEBUG1_RSVD1_MASK (0xFFFF8000U) #define USBPHY_DEBUG1_RSVD1_SHIFT (15U) #define USBPHY_DEBUG1_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_RSVD1_SHIFT)) & USBPHY_DEBUG1_RSVD1_MASK) +/*! @} */ /*! @name DEBUG1_SET - UTMI Debug Status Register 1 */ +/*! @{ */ #define USBPHY_DEBUG1_SET_RSVD0_MASK (0x1FFFU) #define USBPHY_DEBUG1_SET_RSVD0_SHIFT (0U) #define USBPHY_DEBUG1_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_SET_RSVD0_SHIFT)) & USBPHY_DEBUG1_SET_RSVD0_MASK) @@ -24512,8 +38268,10 @@ typedef struct { #define USBPHY_DEBUG1_SET_RSVD1_MASK (0xFFFF8000U) #define USBPHY_DEBUG1_SET_RSVD1_SHIFT (15U) #define USBPHY_DEBUG1_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_SET_RSVD1_SHIFT)) & USBPHY_DEBUG1_SET_RSVD1_MASK) +/*! @} */ /*! @name DEBUG1_CLR - UTMI Debug Status Register 1 */ +/*! @{ */ #define USBPHY_DEBUG1_CLR_RSVD0_MASK (0x1FFFU) #define USBPHY_DEBUG1_CLR_RSVD0_SHIFT (0U) #define USBPHY_DEBUG1_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_CLR_RSVD0_SHIFT)) & USBPHY_DEBUG1_CLR_RSVD0_MASK) @@ -24523,8 +38281,10 @@ typedef struct { #define USBPHY_DEBUG1_CLR_RSVD1_MASK (0xFFFF8000U) #define USBPHY_DEBUG1_CLR_RSVD1_SHIFT (15U) #define USBPHY_DEBUG1_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_CLR_RSVD1_SHIFT)) & USBPHY_DEBUG1_CLR_RSVD1_MASK) +/*! @} */ /*! @name DEBUG1_TOG - UTMI Debug Status Register 1 */ +/*! @{ */ #define USBPHY_DEBUG1_TOG_RSVD0_MASK (0x1FFFU) #define USBPHY_DEBUG1_TOG_RSVD0_SHIFT (0U) #define USBPHY_DEBUG1_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_TOG_RSVD0_SHIFT)) & USBPHY_DEBUG1_TOG_RSVD0_MASK) @@ -24534,8 +38294,10 @@ typedef struct { #define USBPHY_DEBUG1_TOG_RSVD1_MASK (0xFFFF8000U) #define USBPHY_DEBUG1_TOG_RSVD1_SHIFT (15U) #define USBPHY_DEBUG1_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_TOG_RSVD1_SHIFT)) & USBPHY_DEBUG1_TOG_RSVD1_MASK) +/*! @} */ /*! @name VERSION - UTMI RTL Version */ +/*! @{ */ #define USBPHY_VERSION_STEP_MASK (0xFFFFU) #define USBPHY_VERSION_STEP_SHIFT (0U) #define USBPHY_VERSION_STEP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_VERSION_STEP_SHIFT)) & USBPHY_VERSION_STEP_MASK) @@ -24545,6 +38307,7 @@ typedef struct { #define USBPHY_VERSION_MAJOR_MASK (0xFF000000U) #define USBPHY_VERSION_MAJOR_SHIFT (24U) #define USBPHY_VERSION_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_VERSION_MAJOR_SHIFT)) & USBPHY_VERSION_MAJOR_MASK) +/*! @} */ /*! @@ -24624,8 +38387,19 @@ typedef struct { */ /*! @name VBUS_DETECT - USB VBUS Detect Register */ +/*! @{ */ #define USB_ANALOG_VBUS_DETECT_VBUSVALID_THRESH_MASK (0x7U) #define USB_ANALOG_VBUS_DETECT_VBUSVALID_THRESH_SHIFT (0U) +/*! VBUSVALID_THRESH + * 0b000..4.0V + * 0b001..4.1V + * 0b010..4.2V + * 0b011..4.3V + * 0b100..4.4V (default) + * 0b101..4.5V + * 0b110..4.6V + * 0b111..4.7V + */ #define USB_ANALOG_VBUS_DETECT_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_VBUSVALID_THRESH_SHIFT)) & USB_ANALOG_VBUS_DETECT_VBUSVALID_THRESH_MASK) #define USB_ANALOG_VBUS_DETECT_VBUSVALID_PWRUP_CMPS_MASK (0x100000U) #define USB_ANALOG_VBUS_DETECT_VBUSVALID_PWRUP_CMPS_SHIFT (20U) @@ -24636,13 +38410,25 @@ typedef struct { #define USB_ANALOG_VBUS_DETECT_CHARGE_VBUS_MASK (0x8000000U) #define USB_ANALOG_VBUS_DETECT_CHARGE_VBUS_SHIFT (27U) #define USB_ANALOG_VBUS_DETECT_CHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_CHARGE_VBUS_SHIFT)) & USB_ANALOG_VBUS_DETECT_CHARGE_VBUS_MASK) +/*! @} */ /* The count of USB_ANALOG_VBUS_DETECT */ #define USB_ANALOG_VBUS_DETECT_COUNT (2U) /*! @name VBUS_DETECT_SET - USB VBUS Detect Register */ +/*! @{ */ #define USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_THRESH_MASK (0x7U) #define USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_THRESH_SHIFT (0U) +/*! VBUSVALID_THRESH + * 0b000..4.0V + * 0b001..4.1V + * 0b010..4.2V + * 0b011..4.3V + * 0b100..4.4V (default) + * 0b101..4.5V + * 0b110..4.6V + * 0b111..4.7V + */ #define USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_THRESH_SHIFT)) & USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_THRESH_MASK) #define USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_PWRUP_CMPS_MASK (0x100000U) #define USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_PWRUP_CMPS_SHIFT (20U) @@ -24653,13 +38439,25 @@ typedef struct { #define USB_ANALOG_VBUS_DETECT_SET_CHARGE_VBUS_MASK (0x8000000U) #define USB_ANALOG_VBUS_DETECT_SET_CHARGE_VBUS_SHIFT (27U) #define USB_ANALOG_VBUS_DETECT_SET_CHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_SET_CHARGE_VBUS_SHIFT)) & USB_ANALOG_VBUS_DETECT_SET_CHARGE_VBUS_MASK) +/*! @} */ /* The count of USB_ANALOG_VBUS_DETECT_SET */ #define USB_ANALOG_VBUS_DETECT_SET_COUNT (2U) /*! @name VBUS_DETECT_CLR - USB VBUS Detect Register */ +/*! @{ */ #define USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_THRESH_MASK (0x7U) #define USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_THRESH_SHIFT (0U) +/*! VBUSVALID_THRESH + * 0b000..4.0V + * 0b001..4.1V + * 0b010..4.2V + * 0b011..4.3V + * 0b100..4.4V (default) + * 0b101..4.5V + * 0b110..4.6V + * 0b111..4.7V + */ #define USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_THRESH_SHIFT)) & USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_THRESH_MASK) #define USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_PWRUP_CMPS_MASK (0x100000U) #define USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_PWRUP_CMPS_SHIFT (20U) @@ -24670,13 +38468,25 @@ typedef struct { #define USB_ANALOG_VBUS_DETECT_CLR_CHARGE_VBUS_MASK (0x8000000U) #define USB_ANALOG_VBUS_DETECT_CLR_CHARGE_VBUS_SHIFT (27U) #define USB_ANALOG_VBUS_DETECT_CLR_CHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_CLR_CHARGE_VBUS_SHIFT)) & USB_ANALOG_VBUS_DETECT_CLR_CHARGE_VBUS_MASK) +/*! @} */ /* The count of USB_ANALOG_VBUS_DETECT_CLR */ #define USB_ANALOG_VBUS_DETECT_CLR_COUNT (2U) /*! @name VBUS_DETECT_TOG - USB VBUS Detect Register */ +/*! @{ */ #define USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_THRESH_MASK (0x7U) #define USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_THRESH_SHIFT (0U) +/*! VBUSVALID_THRESH + * 0b000..4.0V + * 0b001..4.1V + * 0b010..4.2V + * 0b011..4.3V + * 0b100..4.4V (default) + * 0b101..4.5V + * 0b110..4.6V + * 0b111..4.7V + */ #define USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_THRESH_SHIFT)) & USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_THRESH_MASK) #define USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_PWRUP_CMPS_MASK (0x100000U) #define USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_PWRUP_CMPS_SHIFT (20U) @@ -24687,67 +38497,125 @@ typedef struct { #define USB_ANALOG_VBUS_DETECT_TOG_CHARGE_VBUS_MASK (0x8000000U) #define USB_ANALOG_VBUS_DETECT_TOG_CHARGE_VBUS_SHIFT (27U) #define USB_ANALOG_VBUS_DETECT_TOG_CHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_TOG_CHARGE_VBUS_SHIFT)) & USB_ANALOG_VBUS_DETECT_TOG_CHARGE_VBUS_MASK) +/*! @} */ /* The count of USB_ANALOG_VBUS_DETECT_TOG */ #define USB_ANALOG_VBUS_DETECT_TOG_COUNT (2U) /*! @name CHRG_DETECT - USB Charger Detect Register */ +/*! @{ */ #define USB_ANALOG_CHRG_DETECT_CHK_CONTACT_MASK (0x40000U) #define USB_ANALOG_CHRG_DETECT_CHK_CONTACT_SHIFT (18U) +/*! CHK_CONTACT - Check the contact of USB plug + * 0b0..Do not check the contact of USB plug. + * 0b1..Check whether the USB plug has been in contact with each other + */ #define USB_ANALOG_CHRG_DETECT_CHK_CONTACT(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_CHK_CONTACT_SHIFT)) & USB_ANALOG_CHRG_DETECT_CHK_CONTACT_MASK) #define USB_ANALOG_CHRG_DETECT_CHK_CHRG_B_MASK (0x80000U) #define USB_ANALOG_CHRG_DETECT_CHK_CHRG_B_SHIFT (19U) +/*! CHK_CHRG_B - Check the charger connection + * 0b0..Check whether a charger (either a dedicated charger or a host charger) is connected to USB port. + * 0b1..Do not check whether a charger is connected to the USB port. + */ #define USB_ANALOG_CHRG_DETECT_CHK_CHRG_B(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_CHK_CHRG_B_SHIFT)) & USB_ANALOG_CHRG_DETECT_CHK_CHRG_B_MASK) #define USB_ANALOG_CHRG_DETECT_EN_B_MASK (0x100000U) #define USB_ANALOG_CHRG_DETECT_EN_B_SHIFT (20U) +/*! EN_B + * 0b0..Enable the charger detector. + * 0b1..Disable the charger detector. + */ #define USB_ANALOG_CHRG_DETECT_EN_B(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_EN_B_SHIFT)) & USB_ANALOG_CHRG_DETECT_EN_B_MASK) +/*! @} */ /* The count of USB_ANALOG_CHRG_DETECT */ #define USB_ANALOG_CHRG_DETECT_COUNT (2U) /*! @name CHRG_DETECT_SET - USB Charger Detect Register */ +/*! @{ */ #define USB_ANALOG_CHRG_DETECT_SET_CHK_CONTACT_MASK (0x40000U) #define USB_ANALOG_CHRG_DETECT_SET_CHK_CONTACT_SHIFT (18U) +/*! CHK_CONTACT - Check the contact of USB plug + * 0b0..Do not check the contact of USB plug. + * 0b1..Check whether the USB plug has been in contact with each other + */ #define USB_ANALOG_CHRG_DETECT_SET_CHK_CONTACT(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_SET_CHK_CONTACT_SHIFT)) & USB_ANALOG_CHRG_DETECT_SET_CHK_CONTACT_MASK) #define USB_ANALOG_CHRG_DETECT_SET_CHK_CHRG_B_MASK (0x80000U) #define USB_ANALOG_CHRG_DETECT_SET_CHK_CHRG_B_SHIFT (19U) +/*! CHK_CHRG_B - Check the charger connection + * 0b0..Check whether a charger (either a dedicated charger or a host charger) is connected to USB port. + * 0b1..Do not check whether a charger is connected to the USB port. + */ #define USB_ANALOG_CHRG_DETECT_SET_CHK_CHRG_B(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_SET_CHK_CHRG_B_SHIFT)) & USB_ANALOG_CHRG_DETECT_SET_CHK_CHRG_B_MASK) #define USB_ANALOG_CHRG_DETECT_SET_EN_B_MASK (0x100000U) #define USB_ANALOG_CHRG_DETECT_SET_EN_B_SHIFT (20U) +/*! EN_B + * 0b0..Enable the charger detector. + * 0b1..Disable the charger detector. + */ #define USB_ANALOG_CHRG_DETECT_SET_EN_B(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_SET_EN_B_SHIFT)) & USB_ANALOG_CHRG_DETECT_SET_EN_B_MASK) +/*! @} */ /* The count of USB_ANALOG_CHRG_DETECT_SET */ #define USB_ANALOG_CHRG_DETECT_SET_COUNT (2U) /*! @name CHRG_DETECT_CLR - USB Charger Detect Register */ +/*! @{ */ #define USB_ANALOG_CHRG_DETECT_CLR_CHK_CONTACT_MASK (0x40000U) #define USB_ANALOG_CHRG_DETECT_CLR_CHK_CONTACT_SHIFT (18U) +/*! CHK_CONTACT - Check the contact of USB plug + * 0b0..Do not check the contact of USB plug. + * 0b1..Check whether the USB plug has been in contact with each other + */ #define USB_ANALOG_CHRG_DETECT_CLR_CHK_CONTACT(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_CLR_CHK_CONTACT_SHIFT)) & USB_ANALOG_CHRG_DETECT_CLR_CHK_CONTACT_MASK) #define USB_ANALOG_CHRG_DETECT_CLR_CHK_CHRG_B_MASK (0x80000U) #define USB_ANALOG_CHRG_DETECT_CLR_CHK_CHRG_B_SHIFT (19U) +/*! CHK_CHRG_B - Check the charger connection + * 0b0..Check whether a charger (either a dedicated charger or a host charger) is connected to USB port. + * 0b1..Do not check whether a charger is connected to the USB port. + */ #define USB_ANALOG_CHRG_DETECT_CLR_CHK_CHRG_B(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_CLR_CHK_CHRG_B_SHIFT)) & USB_ANALOG_CHRG_DETECT_CLR_CHK_CHRG_B_MASK) #define USB_ANALOG_CHRG_DETECT_CLR_EN_B_MASK (0x100000U) #define USB_ANALOG_CHRG_DETECT_CLR_EN_B_SHIFT (20U) +/*! EN_B + * 0b0..Enable the charger detector. + * 0b1..Disable the charger detector. + */ #define USB_ANALOG_CHRG_DETECT_CLR_EN_B(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_CLR_EN_B_SHIFT)) & USB_ANALOG_CHRG_DETECT_CLR_EN_B_MASK) +/*! @} */ /* The count of USB_ANALOG_CHRG_DETECT_CLR */ #define USB_ANALOG_CHRG_DETECT_CLR_COUNT (2U) /*! @name CHRG_DETECT_TOG - USB Charger Detect Register */ +/*! @{ */ #define USB_ANALOG_CHRG_DETECT_TOG_CHK_CONTACT_MASK (0x40000U) #define USB_ANALOG_CHRG_DETECT_TOG_CHK_CONTACT_SHIFT (18U) +/*! CHK_CONTACT - Check the contact of USB plug + * 0b0..Do not check the contact of USB plug. + * 0b1..Check whether the USB plug has been in contact with each other + */ #define USB_ANALOG_CHRG_DETECT_TOG_CHK_CONTACT(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_TOG_CHK_CONTACT_SHIFT)) & USB_ANALOG_CHRG_DETECT_TOG_CHK_CONTACT_MASK) #define USB_ANALOG_CHRG_DETECT_TOG_CHK_CHRG_B_MASK (0x80000U) #define USB_ANALOG_CHRG_DETECT_TOG_CHK_CHRG_B_SHIFT (19U) +/*! CHK_CHRG_B - Check the charger connection + * 0b0..Check whether a charger (either a dedicated charger or a host charger) is connected to USB port. + * 0b1..Do not check whether a charger is connected to the USB port. + */ #define USB_ANALOG_CHRG_DETECT_TOG_CHK_CHRG_B(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_TOG_CHK_CHRG_B_SHIFT)) & USB_ANALOG_CHRG_DETECT_TOG_CHK_CHRG_B_MASK) #define USB_ANALOG_CHRG_DETECT_TOG_EN_B_MASK (0x100000U) #define USB_ANALOG_CHRG_DETECT_TOG_EN_B_SHIFT (20U) +/*! EN_B + * 0b0..Enable the charger detector. + * 0b1..Disable the charger detector. + */ #define USB_ANALOG_CHRG_DETECT_TOG_EN_B(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_TOG_EN_B_SHIFT)) & USB_ANALOG_CHRG_DETECT_TOG_EN_B_MASK) +/*! @} */ /* The count of USB_ANALOG_CHRG_DETECT_TOG */ #define USB_ANALOG_CHRG_DETECT_TOG_COUNT (2U) /*! @name VBUS_DETECT_STAT - USB VBUS Detect Status Register */ +/*! @{ */ #define USB_ANALOG_VBUS_DETECT_STAT_SESSEND_MASK (0x1U) #define USB_ANALOG_VBUS_DETECT_STAT_SESSEND_SHIFT (0U) #define USB_ANALOG_VBUS_DETECT_STAT_SESSEND(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_STAT_SESSEND_SHIFT)) & USB_ANALOG_VBUS_DETECT_STAT_SESSEND_MASK) @@ -24760,16 +38628,26 @@ typedef struct { #define USB_ANALOG_VBUS_DETECT_STAT_VBUS_VALID_MASK (0x8U) #define USB_ANALOG_VBUS_DETECT_STAT_VBUS_VALID_SHIFT (3U) #define USB_ANALOG_VBUS_DETECT_STAT_VBUS_VALID(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_STAT_VBUS_VALID_SHIFT)) & USB_ANALOG_VBUS_DETECT_STAT_VBUS_VALID_MASK) +/*! @} */ /* The count of USB_ANALOG_VBUS_DETECT_STAT */ #define USB_ANALOG_VBUS_DETECT_STAT_COUNT (2U) /*! @name CHRG_DETECT_STAT - USB Charger Detect Status Register */ +/*! @{ */ #define USB_ANALOG_CHRG_DETECT_STAT_PLUG_CONTACT_MASK (0x1U) #define USB_ANALOG_CHRG_DETECT_STAT_PLUG_CONTACT_SHIFT (0U) +/*! PLUG_CONTACT + * 0b0..The USB plug has not made contact. + * 0b1..The USB plug has made good contact. + */ #define USB_ANALOG_CHRG_DETECT_STAT_PLUG_CONTACT(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_STAT_PLUG_CONTACT_SHIFT)) & USB_ANALOG_CHRG_DETECT_STAT_PLUG_CONTACT_MASK) #define USB_ANALOG_CHRG_DETECT_STAT_CHRG_DETECTED_MASK (0x2U) #define USB_ANALOG_CHRG_DETECT_STAT_CHRG_DETECTED_SHIFT (1U) +/*! CHRG_DETECTED + * 0b0..The USB port is not connected to a charger. + * 0b1..A charger (either a dedicated charger or a host charger) is connected to the USB port. + */ #define USB_ANALOG_CHRG_DETECT_STAT_CHRG_DETECTED(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_STAT_CHRG_DETECTED_SHIFT)) & USB_ANALOG_CHRG_DETECT_STAT_CHRG_DETECTED_MASK) #define USB_ANALOG_CHRG_DETECT_STAT_DM_STATE_MASK (0x4U) #define USB_ANALOG_CHRG_DETECT_STAT_DM_STATE_SHIFT (2U) @@ -24777,11 +38655,13 @@ typedef struct { #define USB_ANALOG_CHRG_DETECT_STAT_DP_STATE_MASK (0x8U) #define USB_ANALOG_CHRG_DETECT_STAT_DP_STATE_SHIFT (3U) #define USB_ANALOG_CHRG_DETECT_STAT_DP_STATE(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_STAT_DP_STATE_SHIFT)) & USB_ANALOG_CHRG_DETECT_STAT_DP_STATE_MASK) +/*! @} */ /* The count of USB_ANALOG_CHRG_DETECT_STAT */ #define USB_ANALOG_CHRG_DETECT_STAT_COUNT (2U) /*! @name MISC - USB Misc Register */ +/*! @{ */ #define USB_ANALOG_MISC_HS_USE_EXTERNAL_R_MASK (0x1U) #define USB_ANALOG_MISC_HS_USE_EXTERNAL_R_SHIFT (0U) #define USB_ANALOG_MISC_HS_USE_EXTERNAL_R(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_HS_USE_EXTERNAL_R_SHIFT)) & USB_ANALOG_MISC_HS_USE_EXTERNAL_R_MASK) @@ -24791,11 +38671,13 @@ typedef struct { #define USB_ANALOG_MISC_EN_CLK_UTMI_MASK (0x40000000U) #define USB_ANALOG_MISC_EN_CLK_UTMI_SHIFT (30U) #define USB_ANALOG_MISC_EN_CLK_UTMI(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_EN_CLK_UTMI_SHIFT)) & USB_ANALOG_MISC_EN_CLK_UTMI_MASK) +/*! @} */ /* The count of USB_ANALOG_MISC */ #define USB_ANALOG_MISC_COUNT (2U) /*! @name MISC_SET - USB Misc Register */ +/*! @{ */ #define USB_ANALOG_MISC_SET_HS_USE_EXTERNAL_R_MASK (0x1U) #define USB_ANALOG_MISC_SET_HS_USE_EXTERNAL_R_SHIFT (0U) #define USB_ANALOG_MISC_SET_HS_USE_EXTERNAL_R(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_SET_HS_USE_EXTERNAL_R_SHIFT)) & USB_ANALOG_MISC_SET_HS_USE_EXTERNAL_R_MASK) @@ -24805,11 +38687,13 @@ typedef struct { #define USB_ANALOG_MISC_SET_EN_CLK_UTMI_MASK (0x40000000U) #define USB_ANALOG_MISC_SET_EN_CLK_UTMI_SHIFT (30U) #define USB_ANALOG_MISC_SET_EN_CLK_UTMI(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_SET_EN_CLK_UTMI_SHIFT)) & USB_ANALOG_MISC_SET_EN_CLK_UTMI_MASK) +/*! @} */ /* The count of USB_ANALOG_MISC_SET */ #define USB_ANALOG_MISC_SET_COUNT (2U) /*! @name MISC_CLR - USB Misc Register */ +/*! @{ */ #define USB_ANALOG_MISC_CLR_HS_USE_EXTERNAL_R_MASK (0x1U) #define USB_ANALOG_MISC_CLR_HS_USE_EXTERNAL_R_SHIFT (0U) #define USB_ANALOG_MISC_CLR_HS_USE_EXTERNAL_R(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_CLR_HS_USE_EXTERNAL_R_SHIFT)) & USB_ANALOG_MISC_CLR_HS_USE_EXTERNAL_R_MASK) @@ -24819,11 +38703,13 @@ typedef struct { #define USB_ANALOG_MISC_CLR_EN_CLK_UTMI_MASK (0x40000000U) #define USB_ANALOG_MISC_CLR_EN_CLK_UTMI_SHIFT (30U) #define USB_ANALOG_MISC_CLR_EN_CLK_UTMI(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_CLR_EN_CLK_UTMI_SHIFT)) & USB_ANALOG_MISC_CLR_EN_CLK_UTMI_MASK) +/*! @} */ /* The count of USB_ANALOG_MISC_CLR */ #define USB_ANALOG_MISC_CLR_COUNT (2U) /*! @name MISC_TOG - USB Misc Register */ +/*! @{ */ #define USB_ANALOG_MISC_TOG_HS_USE_EXTERNAL_R_MASK (0x1U) #define USB_ANALOG_MISC_TOG_HS_USE_EXTERNAL_R_SHIFT (0U) #define USB_ANALOG_MISC_TOG_HS_USE_EXTERNAL_R(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_TOG_HS_USE_EXTERNAL_R_SHIFT)) & USB_ANALOG_MISC_TOG_HS_USE_EXTERNAL_R_MASK) @@ -24833,20 +38719,20 @@ typedef struct { #define USB_ANALOG_MISC_TOG_EN_CLK_UTMI_MASK (0x40000000U) #define USB_ANALOG_MISC_TOG_EN_CLK_UTMI_SHIFT (30U) #define USB_ANALOG_MISC_TOG_EN_CLK_UTMI(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_TOG_EN_CLK_UTMI_SHIFT)) & USB_ANALOG_MISC_TOG_EN_CLK_UTMI_MASK) +/*! @} */ /* The count of USB_ANALOG_MISC_TOG */ #define USB_ANALOG_MISC_TOG_COUNT (2U) /*! @name DIGPROG - Chip Silicon Version */ -#define USB_ANALOG_DIGPROG_MINOR_MASK (0xFFU) -#define USB_ANALOG_DIGPROG_MINOR_SHIFT (0U) -#define USB_ANALOG_DIGPROG_MINOR(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_DIGPROG_MINOR_SHIFT)) & USB_ANALOG_DIGPROG_MINOR_MASK) -#define USB_ANALOG_DIGPROG_MAJOR_LOWER_MASK (0xFF00U) -#define USB_ANALOG_DIGPROG_MAJOR_LOWER_SHIFT (8U) -#define USB_ANALOG_DIGPROG_MAJOR_LOWER(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_DIGPROG_MAJOR_LOWER_SHIFT)) & USB_ANALOG_DIGPROG_MAJOR_LOWER_MASK) -#define USB_ANALOG_DIGPROG_MAJOR_UPPER_MASK (0xFF0000U) -#define USB_ANALOG_DIGPROG_MAJOR_UPPER_SHIFT (16U) -#define USB_ANALOG_DIGPROG_MAJOR_UPPER(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_DIGPROG_MAJOR_UPPER_SHIFT)) & USB_ANALOG_DIGPROG_MAJOR_UPPER_MASK) +/*! @{ */ +#define USB_ANALOG_DIGPROG_SILICON_REVISION_MASK (0xFFFFFFFFU) +#define USB_ANALOG_DIGPROG_SILICON_REVISION_SHIFT (0U) +/*! SILICON_REVISION + * 0b00000000011010100000000000000001..Silicon revision 1.1 + */ +#define USB_ANALOG_DIGPROG_SILICON_REVISION(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_DIGPROG_SILICON_REVISION_SHIFT)) & USB_ANALOG_DIGPROG_SILICON_REVISION_MASK) +/*! @} */ /*! @@ -24924,201 +38810,439 @@ typedef struct { */ /*! @name DS_ADDR - DMA System Address */ +/*! @{ */ #define USDHC_DS_ADDR_DS_ADDR_MASK (0xFFFFFFFFU) #define USDHC_DS_ADDR_DS_ADDR_SHIFT (0U) #define USDHC_DS_ADDR_DS_ADDR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DS_ADDR_DS_ADDR_SHIFT)) & USDHC_DS_ADDR_DS_ADDR_MASK) +/*! @} */ /*! @name BLK_ATT - Block Attributes */ +/*! @{ */ #define USDHC_BLK_ATT_BLKSIZE_MASK (0x1FFFU) #define USDHC_BLK_ATT_BLKSIZE_SHIFT (0U) +/*! BLKSIZE - Block Size + * 0b1000000000000..4096 Bytes + * 0b0100000000000..2048 Bytes + * 0b0001000000000..512 Bytes + * 0b0000111111111..511 Bytes + * 0b0000000000100..4 Bytes + * 0b0000000000011..3 Bytes + * 0b0000000000010..2 Bytes + * 0b0000000000001..1 Byte + * 0b0000000000000..No data transfer + */ #define USDHC_BLK_ATT_BLKSIZE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_BLK_ATT_BLKSIZE_SHIFT)) & USDHC_BLK_ATT_BLKSIZE_MASK) #define USDHC_BLK_ATT_BLKCNT_MASK (0xFFFF0000U) #define USDHC_BLK_ATT_BLKCNT_SHIFT (16U) +/*! BLKCNT - Block Count + * 0b1111111111111111..65535 blocks + * 0b0000000000000010..2 blocks + * 0b0000000000000001..1 block + * 0b0000000000000000..Stop Count + */ #define USDHC_BLK_ATT_BLKCNT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_BLK_ATT_BLKCNT_SHIFT)) & USDHC_BLK_ATT_BLKCNT_MASK) +/*! @} */ /*! @name CMD_ARG - Command Argument */ +/*! @{ */ #define USDHC_CMD_ARG_CMDARG_MASK (0xFFFFFFFFU) #define USDHC_CMD_ARG_CMDARG_SHIFT (0U) #define USDHC_CMD_ARG_CMDARG(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_ARG_CMDARG_SHIFT)) & USDHC_CMD_ARG_CMDARG_MASK) +/*! @} */ /*! @name CMD_XFR_TYP - Command Transfer Type */ +/*! @{ */ #define USDHC_CMD_XFR_TYP_RSPTYP_MASK (0x30000U) #define USDHC_CMD_XFR_TYP_RSPTYP_SHIFT (16U) +/*! RSPTYP - Response Type Select + * 0b00..No Response + * 0b01..Response Length 136 + * 0b10..Response Length 48 + * 0b11..Response Length 48, check Busy after response + */ #define USDHC_CMD_XFR_TYP_RSPTYP(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_RSPTYP_SHIFT)) & USDHC_CMD_XFR_TYP_RSPTYP_MASK) #define USDHC_CMD_XFR_TYP_CCCEN_MASK (0x80000U) #define USDHC_CMD_XFR_TYP_CCCEN_SHIFT (19U) +/*! CCCEN - Command CRC Check Enable + * 0b1..Enable + * 0b0..Disable + */ #define USDHC_CMD_XFR_TYP_CCCEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CCCEN_SHIFT)) & USDHC_CMD_XFR_TYP_CCCEN_MASK) #define USDHC_CMD_XFR_TYP_CICEN_MASK (0x100000U) #define USDHC_CMD_XFR_TYP_CICEN_SHIFT (20U) +/*! CICEN - Command Index Check Enable + * 0b1..Enable + * 0b0..Disable + */ #define USDHC_CMD_XFR_TYP_CICEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CICEN_SHIFT)) & USDHC_CMD_XFR_TYP_CICEN_MASK) #define USDHC_CMD_XFR_TYP_DPSEL_MASK (0x200000U) #define USDHC_CMD_XFR_TYP_DPSEL_SHIFT (21U) +/*! DPSEL - Data Present Select + * 0b1..Data Present + * 0b0..No Data Present + */ #define USDHC_CMD_XFR_TYP_DPSEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_DPSEL_SHIFT)) & USDHC_CMD_XFR_TYP_DPSEL_MASK) #define USDHC_CMD_XFR_TYP_CMDTYP_MASK (0xC00000U) #define USDHC_CMD_XFR_TYP_CMDTYP_SHIFT (22U) +/*! CMDTYP - Command Type + * 0b11..Abort CMD12, CMD52 for writing I/O Abort in CCCR + * 0b10..Resume CMD52 for writing Function Select in CCCR + * 0b01..Suspend CMD52 for writing Bus Suspend in CCCR + * 0b00..Normal Other commands + */ #define USDHC_CMD_XFR_TYP_CMDTYP(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CMDTYP_SHIFT)) & USDHC_CMD_XFR_TYP_CMDTYP_MASK) #define USDHC_CMD_XFR_TYP_CMDINX_MASK (0x3F000000U) #define USDHC_CMD_XFR_TYP_CMDINX_SHIFT (24U) #define USDHC_CMD_XFR_TYP_CMDINX(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CMDINX_SHIFT)) & USDHC_CMD_XFR_TYP_CMDINX_MASK) +/*! @} */ /*! @name CMD_RSP0 - Command Response0 */ +/*! @{ */ #define USDHC_CMD_RSP0_CMDRSP0_MASK (0xFFFFFFFFU) #define USDHC_CMD_RSP0_CMDRSP0_SHIFT (0U) #define USDHC_CMD_RSP0_CMDRSP0(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP0_CMDRSP0_SHIFT)) & USDHC_CMD_RSP0_CMDRSP0_MASK) +/*! @} */ /*! @name CMD_RSP1 - Command Response1 */ +/*! @{ */ #define USDHC_CMD_RSP1_CMDRSP1_MASK (0xFFFFFFFFU) #define USDHC_CMD_RSP1_CMDRSP1_SHIFT (0U) #define USDHC_CMD_RSP1_CMDRSP1(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP1_CMDRSP1_SHIFT)) & USDHC_CMD_RSP1_CMDRSP1_MASK) +/*! @} */ /*! @name CMD_RSP2 - Command Response2 */ +/*! @{ */ #define USDHC_CMD_RSP2_CMDRSP2_MASK (0xFFFFFFFFU) #define USDHC_CMD_RSP2_CMDRSP2_SHIFT (0U) #define USDHC_CMD_RSP2_CMDRSP2(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP2_CMDRSP2_SHIFT)) & USDHC_CMD_RSP2_CMDRSP2_MASK) +/*! @} */ /*! @name CMD_RSP3 - Command Response3 */ +/*! @{ */ #define USDHC_CMD_RSP3_CMDRSP3_MASK (0xFFFFFFFFU) #define USDHC_CMD_RSP3_CMDRSP3_SHIFT (0U) #define USDHC_CMD_RSP3_CMDRSP3(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP3_CMDRSP3_SHIFT)) & USDHC_CMD_RSP3_CMDRSP3_MASK) +/*! @} */ /*! @name DATA_BUFF_ACC_PORT - Data Buffer Access Port */ +/*! @{ */ #define USDHC_DATA_BUFF_ACC_PORT_DATCONT_MASK (0xFFFFFFFFU) #define USDHC_DATA_BUFF_ACC_PORT_DATCONT_SHIFT (0U) #define USDHC_DATA_BUFF_ACC_PORT_DATCONT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DATA_BUFF_ACC_PORT_DATCONT_SHIFT)) & USDHC_DATA_BUFF_ACC_PORT_DATCONT_MASK) +/*! @} */ /*! @name PRES_STATE - Present State */ +/*! @{ */ #define USDHC_PRES_STATE_CIHB_MASK (0x1U) #define USDHC_PRES_STATE_CIHB_SHIFT (0U) +/*! CIHB - Command Inhibit (CMD) + * 0b1..Cannot issue command + * 0b0..Can issue command using only CMD line + */ #define USDHC_PRES_STATE_CIHB(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CIHB_SHIFT)) & USDHC_PRES_STATE_CIHB_MASK) #define USDHC_PRES_STATE_CDIHB_MASK (0x2U) #define USDHC_PRES_STATE_CDIHB_SHIFT (1U) +/*! CDIHB - Command Inhibit (DATA) + * 0b1..Cannot issue command which uses the DATA line + * 0b0..Can issue command which uses the DATA line + */ #define USDHC_PRES_STATE_CDIHB(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CDIHB_SHIFT)) & USDHC_PRES_STATE_CDIHB_MASK) #define USDHC_PRES_STATE_DLA_MASK (0x4U) #define USDHC_PRES_STATE_DLA_SHIFT (2U) +/*! DLA - Data Line Active + * 0b1..DATA Line Active + * 0b0..DATA Line Inactive + */ #define USDHC_PRES_STATE_DLA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_DLA_SHIFT)) & USDHC_PRES_STATE_DLA_MASK) #define USDHC_PRES_STATE_SDSTB_MASK (0x8U) #define USDHC_PRES_STATE_SDSTB_SHIFT (3U) +/*! SDSTB - SD Clock Stable + * 0b1..Clock is stable. + * 0b0..Clock is changing frequency and not stable. + */ #define USDHC_PRES_STATE_SDSTB(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_SDSTB_SHIFT)) & USDHC_PRES_STATE_SDSTB_MASK) #define USDHC_PRES_STATE_IPGOFF_MASK (0x10U) #define USDHC_PRES_STATE_IPGOFF_SHIFT (4U) +/*! IPGOFF - IPG_CLK Gated Off Internally + * 0b1..IPG_CLK is gated off. + * 0b0..IPG_CLK is active. + */ #define USDHC_PRES_STATE_IPGOFF(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_IPGOFF_SHIFT)) & USDHC_PRES_STATE_IPGOFF_MASK) #define USDHC_PRES_STATE_HCKOFF_MASK (0x20U) #define USDHC_PRES_STATE_HCKOFF_SHIFT (5U) +/*! HCKOFF - HCLK Gated Off Internally + * 0b1..HCLK is gated off. + * 0b0..HCLK is active. + */ #define USDHC_PRES_STATE_HCKOFF(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_HCKOFF_SHIFT)) & USDHC_PRES_STATE_HCKOFF_MASK) #define USDHC_PRES_STATE_PEROFF_MASK (0x40U) #define USDHC_PRES_STATE_PEROFF_SHIFT (6U) +/*! PEROFF - IPG_PERCLK Gated Off Internally + * 0b1..IPG_PERCLK is gated off. + * 0b0..IPG_PERCLK is active. + */ #define USDHC_PRES_STATE_PEROFF(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_PEROFF_SHIFT)) & USDHC_PRES_STATE_PEROFF_MASK) #define USDHC_PRES_STATE_SDOFF_MASK (0x80U) #define USDHC_PRES_STATE_SDOFF_SHIFT (7U) +/*! SDOFF - SD Clock Gated Off Internally + * 0b1..SD Clock is gated off. + * 0b0..SD Clock is active. + */ #define USDHC_PRES_STATE_SDOFF(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_SDOFF_SHIFT)) & USDHC_PRES_STATE_SDOFF_MASK) #define USDHC_PRES_STATE_WTA_MASK (0x100U) #define USDHC_PRES_STATE_WTA_SHIFT (8U) +/*! WTA - Write Transfer Active + * 0b1..Transferring data + * 0b0..No valid data + */ #define USDHC_PRES_STATE_WTA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_WTA_SHIFT)) & USDHC_PRES_STATE_WTA_MASK) #define USDHC_PRES_STATE_RTA_MASK (0x200U) #define USDHC_PRES_STATE_RTA_SHIFT (9U) +/*! RTA - Read Transfer Active + * 0b1..Transferring data + * 0b0..No valid data + */ #define USDHC_PRES_STATE_RTA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_RTA_SHIFT)) & USDHC_PRES_STATE_RTA_MASK) #define USDHC_PRES_STATE_BWEN_MASK (0x400U) #define USDHC_PRES_STATE_BWEN_SHIFT (10U) +/*! BWEN - Buffer Write Enable + * 0b1..Write enable + * 0b0..Write disable + */ #define USDHC_PRES_STATE_BWEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_BWEN_SHIFT)) & USDHC_PRES_STATE_BWEN_MASK) #define USDHC_PRES_STATE_BREN_MASK (0x800U) #define USDHC_PRES_STATE_BREN_SHIFT (11U) +/*! BREN - Buffer Read Enable + * 0b1..Read enable + * 0b0..Read disable + */ #define USDHC_PRES_STATE_BREN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_BREN_SHIFT)) & USDHC_PRES_STATE_BREN_MASK) #define USDHC_PRES_STATE_RTR_MASK (0x1000U) #define USDHC_PRES_STATE_RTR_SHIFT (12U) +/*! RTR - Re-Tuning Request (only for SD3.0 SDR104 mode and EMMC HS200 mode) + * 0b1..Sampling clock needs re-tuning + * 0b0..Fixed or well tuned sampling clock + */ #define USDHC_PRES_STATE_RTR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_RTR_SHIFT)) & USDHC_PRES_STATE_RTR_MASK) #define USDHC_PRES_STATE_TSCD_MASK (0x8000U) #define USDHC_PRES_STATE_TSCD_SHIFT (15U) +/*! TSCD - Tape Select Change Done + * 0b1..Delay cell select change is finished. + * 0b0..Delay cell select change is not finished. + */ #define USDHC_PRES_STATE_TSCD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_TSCD_SHIFT)) & USDHC_PRES_STATE_TSCD_MASK) #define USDHC_PRES_STATE_CINST_MASK (0x10000U) #define USDHC_PRES_STATE_CINST_SHIFT (16U) +/*! CINST - Card Inserted + * 0b1..Card Inserted + * 0b0..Power on Reset or No Card + */ #define USDHC_PRES_STATE_CINST(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CINST_SHIFT)) & USDHC_PRES_STATE_CINST_MASK) #define USDHC_PRES_STATE_CDPL_MASK (0x40000U) #define USDHC_PRES_STATE_CDPL_SHIFT (18U) +/*! CDPL - Card Detect Pin Level + * 0b1..Card present (CD_B = 0) + * 0b0..No card present (CD_B = 1) + */ #define USDHC_PRES_STATE_CDPL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CDPL_SHIFT)) & USDHC_PRES_STATE_CDPL_MASK) #define USDHC_PRES_STATE_WPSPL_MASK (0x80000U) #define USDHC_PRES_STATE_WPSPL_SHIFT (19U) +/*! WPSPL - Write Protect Switch Pin Level + * 0b1..Write enabled (WP = 0) + * 0b0..Write protected (WP = 1) + */ #define USDHC_PRES_STATE_WPSPL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_WPSPL_SHIFT)) & USDHC_PRES_STATE_WPSPL_MASK) #define USDHC_PRES_STATE_CLSL_MASK (0x800000U) #define USDHC_PRES_STATE_CLSL_SHIFT (23U) #define USDHC_PRES_STATE_CLSL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CLSL_SHIFT)) & USDHC_PRES_STATE_CLSL_MASK) #define USDHC_PRES_STATE_DLSL_MASK (0xFF000000U) #define USDHC_PRES_STATE_DLSL_SHIFT (24U) +/*! DLSL - DATA[7:0] Line Signal Level + * 0b00000111..Data 7 line signal level + * 0b00000110..Data 6 line signal level + * 0b00000101..Data 5 line signal level + * 0b00000100..Data 4 line signal level + * 0b00000011..Data 3 line signal level + * 0b00000010..Data 2 line signal level + * 0b00000001..Data 1 line signal level + * 0b00000000..Data 0 line signal level + */ #define USDHC_PRES_STATE_DLSL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_DLSL_SHIFT)) & USDHC_PRES_STATE_DLSL_MASK) +/*! @} */ /*! @name PROT_CTRL - Protocol Control */ +/*! @{ */ #define USDHC_PROT_CTRL_LCTL_MASK (0x1U) #define USDHC_PROT_CTRL_LCTL_SHIFT (0U) +/*! LCTL - LED Control + * 0b1..LED on + * 0b0..LED off + */ #define USDHC_PROT_CTRL_LCTL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_LCTL_SHIFT)) & USDHC_PROT_CTRL_LCTL_MASK) #define USDHC_PROT_CTRL_DTW_MASK (0x6U) #define USDHC_PROT_CTRL_DTW_SHIFT (1U) +/*! DTW - Data Transfer Width + * 0b10..8-bit mode + * 0b01..4-bit mode + * 0b00..1-bit mode + * 0b11..Reserved + */ #define USDHC_PROT_CTRL_DTW(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_DTW_SHIFT)) & USDHC_PROT_CTRL_DTW_MASK) #define USDHC_PROT_CTRL_D3CD_MASK (0x8U) #define USDHC_PROT_CTRL_D3CD_SHIFT (3U) +/*! D3CD - DATA3 as Card Detection Pin + * 0b1..DATA3 as Card Detection Pin + * 0b0..DATA3 does not monitor Card Insertion + */ #define USDHC_PROT_CTRL_D3CD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_D3CD_SHIFT)) & USDHC_PROT_CTRL_D3CD_MASK) #define USDHC_PROT_CTRL_EMODE_MASK (0x30U) #define USDHC_PROT_CTRL_EMODE_SHIFT (4U) +/*! EMODE - Endian Mode + * 0b00..Big Endian Mode + * 0b01..Half Word Big Endian Mode + * 0b10..Little Endian Mode + * 0b11..Reserved + */ #define USDHC_PROT_CTRL_EMODE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_EMODE_SHIFT)) & USDHC_PROT_CTRL_EMODE_MASK) #define USDHC_PROT_CTRL_CDTL_MASK (0x40U) #define USDHC_PROT_CTRL_CDTL_SHIFT (6U) +/*! CDTL - Card Detect Test Level + * 0b1..Card Detect Test Level is 1, card inserted + * 0b0..Card Detect Test Level is 0, no card inserted + */ #define USDHC_PROT_CTRL_CDTL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_CDTL_SHIFT)) & USDHC_PROT_CTRL_CDTL_MASK) #define USDHC_PROT_CTRL_CDSS_MASK (0x80U) #define USDHC_PROT_CTRL_CDSS_SHIFT (7U) +/*! CDSS - Card Detect Signal Selection + * 0b1..Card Detection Test Level is selected (for test purpose). + * 0b0..Card Detection Level is selected (for normal purpose). + */ #define USDHC_PROT_CTRL_CDSS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_CDSS_SHIFT)) & USDHC_PROT_CTRL_CDSS_MASK) #define USDHC_PROT_CTRL_DMASEL_MASK (0x300U) #define USDHC_PROT_CTRL_DMASEL_SHIFT (8U) +/*! DMASEL - DMA Select + * 0b00..No DMA or Simple DMA is selected + * 0b01..ADMA1 is selected + * 0b10..ADMA2 is selected + * 0b11..reserved + */ #define USDHC_PROT_CTRL_DMASEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_DMASEL_SHIFT)) & USDHC_PROT_CTRL_DMASEL_MASK) #define USDHC_PROT_CTRL_SABGREQ_MASK (0x10000U) #define USDHC_PROT_CTRL_SABGREQ_SHIFT (16U) +/*! SABGREQ - Stop At Block Gap Request + * 0b1..Stop + * 0b0..Transfer + */ #define USDHC_PROT_CTRL_SABGREQ(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_SABGREQ_SHIFT)) & USDHC_PROT_CTRL_SABGREQ_MASK) #define USDHC_PROT_CTRL_CREQ_MASK (0x20000U) #define USDHC_PROT_CTRL_CREQ_SHIFT (17U) +/*! CREQ - Continue Request + * 0b1..Restart + * 0b0..No effect + */ #define USDHC_PROT_CTRL_CREQ(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_CREQ_SHIFT)) & USDHC_PROT_CTRL_CREQ_MASK) #define USDHC_PROT_CTRL_RWCTL_MASK (0x40000U) #define USDHC_PROT_CTRL_RWCTL_SHIFT (18U) +/*! RWCTL - Read Wait Control + * 0b1..Enable Read Wait Control, and assert Read Wait without stopping SD Clock at block gap when SABGREQ bit is set + * 0b0..Disable Read Wait Control, and stop SD Clock at block gap when SABGREQ bit is set + */ #define USDHC_PROT_CTRL_RWCTL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_RWCTL_SHIFT)) & USDHC_PROT_CTRL_RWCTL_MASK) #define USDHC_PROT_CTRL_IABG_MASK (0x80000U) #define USDHC_PROT_CTRL_IABG_SHIFT (19U) +/*! IABG - Interrupt At Block Gap + * 0b1..Enabled + * 0b0..Disabled + */ #define USDHC_PROT_CTRL_IABG(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_IABG_SHIFT)) & USDHC_PROT_CTRL_IABG_MASK) #define USDHC_PROT_CTRL_RD_DONE_NO_8CLK_MASK (0x100000U) #define USDHC_PROT_CTRL_RD_DONE_NO_8CLK_SHIFT (20U) #define USDHC_PROT_CTRL_RD_DONE_NO_8CLK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_RD_DONE_NO_8CLK_SHIFT)) & USDHC_PROT_CTRL_RD_DONE_NO_8CLK_MASK) #define USDHC_PROT_CTRL_WECINT_MASK (0x1000000U) #define USDHC_PROT_CTRL_WECINT_SHIFT (24U) +/*! WECINT - Wakeup Event Enable On Card Interrupt + * 0b1..Enable + * 0b0..Disable + */ #define USDHC_PROT_CTRL_WECINT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_WECINT_SHIFT)) & USDHC_PROT_CTRL_WECINT_MASK) #define USDHC_PROT_CTRL_WECINS_MASK (0x2000000U) #define USDHC_PROT_CTRL_WECINS_SHIFT (25U) +/*! WECINS - Wakeup Event Enable On SD Card Insertion + * 0b1..Enable + * 0b0..Disable + */ #define USDHC_PROT_CTRL_WECINS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_WECINS_SHIFT)) & USDHC_PROT_CTRL_WECINS_MASK) #define USDHC_PROT_CTRL_WECRM_MASK (0x4000000U) #define USDHC_PROT_CTRL_WECRM_SHIFT (26U) +/*! WECRM - Wakeup Event Enable On SD Card Removal + * 0b1..Enable + * 0b0..Disable + */ #define USDHC_PROT_CTRL_WECRM(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_WECRM_SHIFT)) & USDHC_PROT_CTRL_WECRM_MASK) #define USDHC_PROT_CTRL_BURST_LEN_EN_MASK (0x38000000U) #define USDHC_PROT_CTRL_BURST_LEN_EN_SHIFT (27U) +/*! BURST_LEN_EN - BURST length enable for INCR, INCR4 / INCR8 / INCR16, INCR4-WRAP / INCR8-WRAP / INCR16-WRAP + * 0bxx1..Burst length is enabled for INCR + * 0bx1x..Burst length is enabled for INCR4 / INCR8 / INCR16 + * 0b1xx..Burst length is enabled for INCR4-WRAP / INCR8-WRAP / INCR16-WRAP + */ #define USDHC_PROT_CTRL_BURST_LEN_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_BURST_LEN_EN_SHIFT)) & USDHC_PROT_CTRL_BURST_LEN_EN_MASK) #define USDHC_PROT_CTRL_NON_EXACT_BLK_RD_MASK (0x40000000U) #define USDHC_PROT_CTRL_NON_EXACT_BLK_RD_SHIFT (30U) +/*! NON_EXACT_BLK_RD - NON_EXACT_BLK_RD + * 0b1..The block read is non-exact block read. Host driver needs to issue abort command to terminate this multi-block read. + * 0b0..The block read is exact block read. Host driver doesn't need to issue abort command to terminate this multi-block read. + */ #define USDHC_PROT_CTRL_NON_EXACT_BLK_RD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_NON_EXACT_BLK_RD_SHIFT)) & USDHC_PROT_CTRL_NON_EXACT_BLK_RD_MASK) +/*! @} */ /*! @name SYS_CTRL - System Control */ +/*! @{ */ #define USDHC_SYS_CTRL_DVS_MASK (0xF0U) #define USDHC_SYS_CTRL_DVS_SHIFT (4U) +/*! DVS - Divisor + * 0b0000..Divide-by-1 + * 0b0001..Divide-by-2 + * 0b1110..Divide-by-15 + * 0b1111..Divide-by-16 + */ #define USDHC_SYS_CTRL_DVS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_DVS_SHIFT)) & USDHC_SYS_CTRL_DVS_MASK) #define USDHC_SYS_CTRL_SDCLKFS_MASK (0xFF00U) #define USDHC_SYS_CTRL_SDCLKFS_SHIFT (8U) #define USDHC_SYS_CTRL_SDCLKFS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_SDCLKFS_SHIFT)) & USDHC_SYS_CTRL_SDCLKFS_MASK) #define USDHC_SYS_CTRL_DTOCV_MASK (0xF0000U) #define USDHC_SYS_CTRL_DTOCV_SHIFT (16U) +/*! DTOCV - Data Timeout Counter Value + * 0b1111..SDCLK x 2 29 + * 0b1110..SDCLK x 2 28 + * 0b1101..SDCLK x 2 27 + * 0b0001..SDCLK x 2 15 + * 0b0000..SDCLK x 2 14 + */ #define USDHC_SYS_CTRL_DTOCV(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_DTOCV_SHIFT)) & USDHC_SYS_CTRL_DTOCV_MASK) #define USDHC_SYS_CTRL_IPP_RST_N_MASK (0x800000U) #define USDHC_SYS_CTRL_IPP_RST_N_SHIFT (23U) #define USDHC_SYS_CTRL_IPP_RST_N(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_IPP_RST_N_SHIFT)) & USDHC_SYS_CTRL_IPP_RST_N_MASK) #define USDHC_SYS_CTRL_RSTA_MASK (0x1000000U) #define USDHC_SYS_CTRL_RSTA_SHIFT (24U) +/*! RSTA - Software Reset For ALL + * 0b1..Reset + * 0b0..No Reset + */ #define USDHC_SYS_CTRL_RSTA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTA_SHIFT)) & USDHC_SYS_CTRL_RSTA_MASK) #define USDHC_SYS_CTRL_RSTC_MASK (0x2000000U) #define USDHC_SYS_CTRL_RSTC_SHIFT (25U) +/*! RSTC - Software Reset For CMD Line + * 0b1..Reset + * 0b0..No Reset + */ #define USDHC_SYS_CTRL_RSTC(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTC_SHIFT)) & USDHC_SYS_CTRL_RSTC_MASK) #define USDHC_SYS_CTRL_RSTD_MASK (0x4000000U) #define USDHC_SYS_CTRL_RSTD_SHIFT (26U) +/*! RSTD - Software Reset For DATA Line + * 0b1..Reset + * 0b0..No Reset + */ #define USDHC_SYS_CTRL_RSTD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTD_SHIFT)) & USDHC_SYS_CTRL_RSTD_MASK) #define USDHC_SYS_CTRL_INITA_MASK (0x8000000U) #define USDHC_SYS_CTRL_INITA_SHIFT (27U) @@ -25126,229 +39250,511 @@ typedef struct { #define USDHC_SYS_CTRL_RSTT_MASK (0x10000000U) #define USDHC_SYS_CTRL_RSTT_SHIFT (28U) #define USDHC_SYS_CTRL_RSTT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTT_SHIFT)) & USDHC_SYS_CTRL_RSTT_MASK) +/*! @} */ /*! @name INT_STATUS - Interrupt Status */ +/*! @{ */ #define USDHC_INT_STATUS_CC_MASK (0x1U) #define USDHC_INT_STATUS_CC_SHIFT (0U) +/*! CC - Command Complete + * 0b1..Command complete + * 0b0..Command not complete + */ #define USDHC_INT_STATUS_CC(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CC_SHIFT)) & USDHC_INT_STATUS_CC_MASK) #define USDHC_INT_STATUS_TC_MASK (0x2U) #define USDHC_INT_STATUS_TC_SHIFT (1U) +/*! TC - Transfer Complete + * 0b1..Transfer complete + * 0b0..Transfer not complete + */ #define USDHC_INT_STATUS_TC(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_TC_SHIFT)) & USDHC_INT_STATUS_TC_MASK) #define USDHC_INT_STATUS_BGE_MASK (0x4U) #define USDHC_INT_STATUS_BGE_SHIFT (2U) +/*! BGE - Block Gap Event + * 0b1..Transaction stopped at block gap + * 0b0..No block gap event + */ #define USDHC_INT_STATUS_BGE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_BGE_SHIFT)) & USDHC_INT_STATUS_BGE_MASK) #define USDHC_INT_STATUS_DINT_MASK (0x8U) #define USDHC_INT_STATUS_DINT_SHIFT (3U) +/*! DINT - DMA Interrupt + * 0b1..DMA Interrupt is generated + * 0b0..No DMA Interrupt + */ #define USDHC_INT_STATUS_DINT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DINT_SHIFT)) & USDHC_INT_STATUS_DINT_MASK) #define USDHC_INT_STATUS_BWR_MASK (0x10U) #define USDHC_INT_STATUS_BWR_SHIFT (4U) +/*! BWR - Buffer Write Ready + * 0b1..Ready to write buffer: + * 0b0..Not ready to write buffer + */ #define USDHC_INT_STATUS_BWR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_BWR_SHIFT)) & USDHC_INT_STATUS_BWR_MASK) #define USDHC_INT_STATUS_BRR_MASK (0x20U) #define USDHC_INT_STATUS_BRR_SHIFT (5U) +/*! BRR - Buffer Read Ready + * 0b1..Ready to read buffer + * 0b0..Not ready to read buffer + */ #define USDHC_INT_STATUS_BRR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_BRR_SHIFT)) & USDHC_INT_STATUS_BRR_MASK) #define USDHC_INT_STATUS_CINS_MASK (0x40U) #define USDHC_INT_STATUS_CINS_SHIFT (6U) +/*! CINS - Card Insertion + * 0b1..Card inserted + * 0b0..Card state unstable or removed + */ #define USDHC_INT_STATUS_CINS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CINS_SHIFT)) & USDHC_INT_STATUS_CINS_MASK) #define USDHC_INT_STATUS_CRM_MASK (0x80U) #define USDHC_INT_STATUS_CRM_SHIFT (7U) +/*! CRM - Card Removal + * 0b1..Card removed + * 0b0..Card state unstable or inserted + */ #define USDHC_INT_STATUS_CRM(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CRM_SHIFT)) & USDHC_INT_STATUS_CRM_MASK) #define USDHC_INT_STATUS_CINT_MASK (0x100U) #define USDHC_INT_STATUS_CINT_SHIFT (8U) +/*! CINT - Card Interrupt + * 0b1..Generate Card Interrupt + * 0b0..No Card Interrupt + */ #define USDHC_INT_STATUS_CINT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CINT_SHIFT)) & USDHC_INT_STATUS_CINT_MASK) #define USDHC_INT_STATUS_RTE_MASK (0x1000U) #define USDHC_INT_STATUS_RTE_SHIFT (12U) +/*! RTE - Re-Tuning Event: (only for SD3.0 SDR104 mode and EMMC HS200 mode) + * 0b1..Re-Tuning should be performed + * 0b0..Re-Tuning is not required + */ #define USDHC_INT_STATUS_RTE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_RTE_SHIFT)) & USDHC_INT_STATUS_RTE_MASK) #define USDHC_INT_STATUS_TP_MASK (0x4000U) #define USDHC_INT_STATUS_TP_SHIFT (14U) #define USDHC_INT_STATUS_TP(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_TP_SHIFT)) & USDHC_INT_STATUS_TP_MASK) #define USDHC_INT_STATUS_CTOE_MASK (0x10000U) #define USDHC_INT_STATUS_CTOE_SHIFT (16U) +/*! CTOE - Command Timeout Error + * 0b1..Time out + * 0b0..No Error + */ #define USDHC_INT_STATUS_CTOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CTOE_SHIFT)) & USDHC_INT_STATUS_CTOE_MASK) #define USDHC_INT_STATUS_CCE_MASK (0x20000U) #define USDHC_INT_STATUS_CCE_SHIFT (17U) +/*! CCE - Command CRC Error + * 0b1..CRC Error Generated. + * 0b0..No Error + */ #define USDHC_INT_STATUS_CCE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CCE_SHIFT)) & USDHC_INT_STATUS_CCE_MASK) #define USDHC_INT_STATUS_CEBE_MASK (0x40000U) #define USDHC_INT_STATUS_CEBE_SHIFT (18U) +/*! CEBE - Command End Bit Error + * 0b1..End Bit Error Generated + * 0b0..No Error + */ #define USDHC_INT_STATUS_CEBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CEBE_SHIFT)) & USDHC_INT_STATUS_CEBE_MASK) #define USDHC_INT_STATUS_CIE_MASK (0x80000U) #define USDHC_INT_STATUS_CIE_SHIFT (19U) +/*! CIE - Command Index Error + * 0b1..Error + * 0b0..No Error + */ #define USDHC_INT_STATUS_CIE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CIE_SHIFT)) & USDHC_INT_STATUS_CIE_MASK) #define USDHC_INT_STATUS_DTOE_MASK (0x100000U) #define USDHC_INT_STATUS_DTOE_SHIFT (20U) +/*! DTOE - Data Timeout Error + * 0b1..Time out + * 0b0..No Error + */ #define USDHC_INT_STATUS_DTOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DTOE_SHIFT)) & USDHC_INT_STATUS_DTOE_MASK) #define USDHC_INT_STATUS_DCE_MASK (0x200000U) #define USDHC_INT_STATUS_DCE_SHIFT (21U) +/*! DCE - Data CRC Error + * 0b1..Error + * 0b0..No Error + */ #define USDHC_INT_STATUS_DCE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DCE_SHIFT)) & USDHC_INT_STATUS_DCE_MASK) #define USDHC_INT_STATUS_DEBE_MASK (0x400000U) #define USDHC_INT_STATUS_DEBE_SHIFT (22U) +/*! DEBE - Data End Bit Error + * 0b1..Error + * 0b0..No Error + */ #define USDHC_INT_STATUS_DEBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DEBE_SHIFT)) & USDHC_INT_STATUS_DEBE_MASK) #define USDHC_INT_STATUS_AC12E_MASK (0x1000000U) #define USDHC_INT_STATUS_AC12E_SHIFT (24U) +/*! AC12E - Auto CMD12 Error + * 0b1..Error + * 0b0..No Error + */ #define USDHC_INT_STATUS_AC12E(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_AC12E_SHIFT)) & USDHC_INT_STATUS_AC12E_MASK) #define USDHC_INT_STATUS_TNE_MASK (0x4000000U) #define USDHC_INT_STATUS_TNE_SHIFT (26U) #define USDHC_INT_STATUS_TNE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_TNE_SHIFT)) & USDHC_INT_STATUS_TNE_MASK) #define USDHC_INT_STATUS_DMAE_MASK (0x10000000U) #define USDHC_INT_STATUS_DMAE_SHIFT (28U) +/*! DMAE - DMA Error + * 0b1..Error + * 0b0..No Error + */ #define USDHC_INT_STATUS_DMAE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DMAE_SHIFT)) & USDHC_INT_STATUS_DMAE_MASK) +/*! @} */ /*! @name INT_STATUS_EN - Interrupt Status Enable */ +/*! @{ */ #define USDHC_INT_STATUS_EN_CCSEN_MASK (0x1U) #define USDHC_INT_STATUS_EN_CCSEN_SHIFT (0U) +/*! CCSEN - Command Complete Status Enable + * 0b1..Enabled + * 0b0..Masked + */ #define USDHC_INT_STATUS_EN_CCSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CCSEN_SHIFT)) & USDHC_INT_STATUS_EN_CCSEN_MASK) #define USDHC_INT_STATUS_EN_TCSEN_MASK (0x2U) #define USDHC_INT_STATUS_EN_TCSEN_SHIFT (1U) +/*! TCSEN - Transfer Complete Status Enable + * 0b1..Enabled + * 0b0..Masked + */ #define USDHC_INT_STATUS_EN_TCSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_TCSEN_SHIFT)) & USDHC_INT_STATUS_EN_TCSEN_MASK) #define USDHC_INT_STATUS_EN_BGESEN_MASK (0x4U) #define USDHC_INT_STATUS_EN_BGESEN_SHIFT (2U) +/*! BGESEN - Block Gap Event Status Enable + * 0b1..Enabled + * 0b0..Masked + */ #define USDHC_INT_STATUS_EN_BGESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_BGESEN_SHIFT)) & USDHC_INT_STATUS_EN_BGESEN_MASK) #define USDHC_INT_STATUS_EN_DINTSEN_MASK (0x8U) #define USDHC_INT_STATUS_EN_DINTSEN_SHIFT (3U) +/*! DINTSEN - DMA Interrupt Status Enable + * 0b1..Enabled + * 0b0..Masked + */ #define USDHC_INT_STATUS_EN_DINTSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DINTSEN_SHIFT)) & USDHC_INT_STATUS_EN_DINTSEN_MASK) #define USDHC_INT_STATUS_EN_BWRSEN_MASK (0x10U) #define USDHC_INT_STATUS_EN_BWRSEN_SHIFT (4U) +/*! BWRSEN - Buffer Write Ready Status Enable + * 0b1..Enabled + * 0b0..Masked + */ #define USDHC_INT_STATUS_EN_BWRSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_BWRSEN_SHIFT)) & USDHC_INT_STATUS_EN_BWRSEN_MASK) #define USDHC_INT_STATUS_EN_BRRSEN_MASK (0x20U) #define USDHC_INT_STATUS_EN_BRRSEN_SHIFT (5U) +/*! BRRSEN - Buffer Read Ready Status Enable + * 0b1..Enabled + * 0b0..Masked + */ #define USDHC_INT_STATUS_EN_BRRSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_BRRSEN_SHIFT)) & USDHC_INT_STATUS_EN_BRRSEN_MASK) #define USDHC_INT_STATUS_EN_CINSSEN_MASK (0x40U) #define USDHC_INT_STATUS_EN_CINSSEN_SHIFT (6U) +/*! CINSSEN - Card Insertion Status Enable + * 0b1..Enabled + * 0b0..Masked + */ #define USDHC_INT_STATUS_EN_CINSSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CINSSEN_SHIFT)) & USDHC_INT_STATUS_EN_CINSSEN_MASK) #define USDHC_INT_STATUS_EN_CRMSEN_MASK (0x80U) #define USDHC_INT_STATUS_EN_CRMSEN_SHIFT (7U) +/*! CRMSEN - Card Removal Status Enable + * 0b1..Enabled + * 0b0..Masked + */ #define USDHC_INT_STATUS_EN_CRMSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CRMSEN_SHIFT)) & USDHC_INT_STATUS_EN_CRMSEN_MASK) #define USDHC_INT_STATUS_EN_CINTSEN_MASK (0x100U) #define USDHC_INT_STATUS_EN_CINTSEN_SHIFT (8U) +/*! CINTSEN - Card Interrupt Status Enable + * 0b1..Enabled + * 0b0..Masked + */ #define USDHC_INT_STATUS_EN_CINTSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CINTSEN_SHIFT)) & USDHC_INT_STATUS_EN_CINTSEN_MASK) #define USDHC_INT_STATUS_EN_RTESEN_MASK (0x1000U) #define USDHC_INT_STATUS_EN_RTESEN_SHIFT (12U) +/*! RTESEN - Re-Tuning Event Status Enable + * 0b1..Enabled + * 0b0..Masked + */ #define USDHC_INT_STATUS_EN_RTESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_RTESEN_SHIFT)) & USDHC_INT_STATUS_EN_RTESEN_MASK) #define USDHC_INT_STATUS_EN_TPSEN_MASK (0x4000U) #define USDHC_INT_STATUS_EN_TPSEN_SHIFT (14U) +/*! TPSEN - Tuning Pass Status Enable + * 0b1..Enabled + * 0b0..Masked + */ #define USDHC_INT_STATUS_EN_TPSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_TPSEN_SHIFT)) & USDHC_INT_STATUS_EN_TPSEN_MASK) #define USDHC_INT_STATUS_EN_CTOESEN_MASK (0x10000U) #define USDHC_INT_STATUS_EN_CTOESEN_SHIFT (16U) +/*! CTOESEN - Command Timeout Error Status Enable + * 0b1..Enabled + * 0b0..Masked + */ #define USDHC_INT_STATUS_EN_CTOESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CTOESEN_SHIFT)) & USDHC_INT_STATUS_EN_CTOESEN_MASK) #define USDHC_INT_STATUS_EN_CCESEN_MASK (0x20000U) #define USDHC_INT_STATUS_EN_CCESEN_SHIFT (17U) +/*! CCESEN - Command CRC Error Status Enable + * 0b1..Enabled + * 0b0..Masked + */ #define USDHC_INT_STATUS_EN_CCESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CCESEN_SHIFT)) & USDHC_INT_STATUS_EN_CCESEN_MASK) #define USDHC_INT_STATUS_EN_CEBESEN_MASK (0x40000U) #define USDHC_INT_STATUS_EN_CEBESEN_SHIFT (18U) +/*! CEBESEN - Command End Bit Error Status Enable + * 0b1..Enabled + * 0b0..Masked + */ #define USDHC_INT_STATUS_EN_CEBESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CEBESEN_SHIFT)) & USDHC_INT_STATUS_EN_CEBESEN_MASK) #define USDHC_INT_STATUS_EN_CIESEN_MASK (0x80000U) #define USDHC_INT_STATUS_EN_CIESEN_SHIFT (19U) +/*! CIESEN - Command Index Error Status Enable + * 0b1..Enabled + * 0b0..Masked + */ #define USDHC_INT_STATUS_EN_CIESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CIESEN_SHIFT)) & USDHC_INT_STATUS_EN_CIESEN_MASK) #define USDHC_INT_STATUS_EN_DTOESEN_MASK (0x100000U) #define USDHC_INT_STATUS_EN_DTOESEN_SHIFT (20U) +/*! DTOESEN - Data Timeout Error Status Enable + * 0b1..Enabled + * 0b0..Masked + */ #define USDHC_INT_STATUS_EN_DTOESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DTOESEN_SHIFT)) & USDHC_INT_STATUS_EN_DTOESEN_MASK) #define USDHC_INT_STATUS_EN_DCESEN_MASK (0x200000U) #define USDHC_INT_STATUS_EN_DCESEN_SHIFT (21U) +/*! DCESEN - Data CRC Error Status Enable + * 0b1..Enabled + * 0b0..Masked + */ #define USDHC_INT_STATUS_EN_DCESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DCESEN_SHIFT)) & USDHC_INT_STATUS_EN_DCESEN_MASK) #define USDHC_INT_STATUS_EN_DEBESEN_MASK (0x400000U) #define USDHC_INT_STATUS_EN_DEBESEN_SHIFT (22U) +/*! DEBESEN - Data End Bit Error Status Enable + * 0b1..Enabled + * 0b0..Masked + */ #define USDHC_INT_STATUS_EN_DEBESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DEBESEN_SHIFT)) & USDHC_INT_STATUS_EN_DEBESEN_MASK) #define USDHC_INT_STATUS_EN_AC12ESEN_MASK (0x1000000U) #define USDHC_INT_STATUS_EN_AC12ESEN_SHIFT (24U) +/*! AC12ESEN - Auto CMD12 Error Status Enable + * 0b1..Enabled + * 0b0..Masked + */ #define USDHC_INT_STATUS_EN_AC12ESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_AC12ESEN_SHIFT)) & USDHC_INT_STATUS_EN_AC12ESEN_MASK) #define USDHC_INT_STATUS_EN_TNESEN_MASK (0x4000000U) #define USDHC_INT_STATUS_EN_TNESEN_SHIFT (26U) +/*! TNESEN - Tuning Error Status Enable + * 0b1..Enabled + * 0b0..Masked + */ #define USDHC_INT_STATUS_EN_TNESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_TNESEN_SHIFT)) & USDHC_INT_STATUS_EN_TNESEN_MASK) #define USDHC_INT_STATUS_EN_DMAESEN_MASK (0x10000000U) #define USDHC_INT_STATUS_EN_DMAESEN_SHIFT (28U) +/*! DMAESEN - DMA Error Status Enable + * 0b1..Enabled + * 0b0..Masked + */ #define USDHC_INT_STATUS_EN_DMAESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DMAESEN_SHIFT)) & USDHC_INT_STATUS_EN_DMAESEN_MASK) +/*! @} */ /*! @name INT_SIGNAL_EN - Interrupt Signal Enable */ +/*! @{ */ #define USDHC_INT_SIGNAL_EN_CCIEN_MASK (0x1U) #define USDHC_INT_SIGNAL_EN_CCIEN_SHIFT (0U) +/*! CCIEN - Command Complete Interrupt Enable + * 0b1..Enabled + * 0b0..Masked + */ #define USDHC_INT_SIGNAL_EN_CCIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CCIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CCIEN_MASK) #define USDHC_INT_SIGNAL_EN_TCIEN_MASK (0x2U) #define USDHC_INT_SIGNAL_EN_TCIEN_SHIFT (1U) +/*! TCIEN - Transfer Complete Interrupt Enable + * 0b1..Enabled + * 0b0..Masked + */ #define USDHC_INT_SIGNAL_EN_TCIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_TCIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_TCIEN_MASK) #define USDHC_INT_SIGNAL_EN_BGEIEN_MASK (0x4U) #define USDHC_INT_SIGNAL_EN_BGEIEN_SHIFT (2U) +/*! BGEIEN - Block Gap Event Interrupt Enable + * 0b1..Enabled + * 0b0..Masked + */ #define USDHC_INT_SIGNAL_EN_BGEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_BGEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_BGEIEN_MASK) #define USDHC_INT_SIGNAL_EN_DINTIEN_MASK (0x8U) #define USDHC_INT_SIGNAL_EN_DINTIEN_SHIFT (3U) +/*! DINTIEN - DMA Interrupt Enable + * 0b1..Enabled + * 0b0..Masked + */ #define USDHC_INT_SIGNAL_EN_DINTIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DINTIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DINTIEN_MASK) #define USDHC_INT_SIGNAL_EN_BWRIEN_MASK (0x10U) #define USDHC_INT_SIGNAL_EN_BWRIEN_SHIFT (4U) +/*! BWRIEN - Buffer Write Ready Interrupt Enable + * 0b1..Enabled + * 0b0..Masked + */ #define USDHC_INT_SIGNAL_EN_BWRIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_BWRIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_BWRIEN_MASK) #define USDHC_INT_SIGNAL_EN_BRRIEN_MASK (0x20U) #define USDHC_INT_SIGNAL_EN_BRRIEN_SHIFT (5U) +/*! BRRIEN - Buffer Read Ready Interrupt Enable + * 0b1..Enabled + * 0b0..Masked + */ #define USDHC_INT_SIGNAL_EN_BRRIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_BRRIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_BRRIEN_MASK) #define USDHC_INT_SIGNAL_EN_CINSIEN_MASK (0x40U) #define USDHC_INT_SIGNAL_EN_CINSIEN_SHIFT (6U) +/*! CINSIEN - Card Insertion Interrupt Enable + * 0b1..Enabled + * 0b0..Masked + */ #define USDHC_INT_SIGNAL_EN_CINSIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CINSIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CINSIEN_MASK) #define USDHC_INT_SIGNAL_EN_CRMIEN_MASK (0x80U) #define USDHC_INT_SIGNAL_EN_CRMIEN_SHIFT (7U) +/*! CRMIEN - Card Removal Interrupt Enable + * 0b1..Enabled + * 0b0..Masked + */ #define USDHC_INT_SIGNAL_EN_CRMIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CRMIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CRMIEN_MASK) #define USDHC_INT_SIGNAL_EN_CINTIEN_MASK (0x100U) #define USDHC_INT_SIGNAL_EN_CINTIEN_SHIFT (8U) +/*! CINTIEN - Card Interrupt Interrupt Enable + * 0b1..Enabled + * 0b0..Masked + */ #define USDHC_INT_SIGNAL_EN_CINTIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CINTIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CINTIEN_MASK) #define USDHC_INT_SIGNAL_EN_RTEIEN_MASK (0x1000U) #define USDHC_INT_SIGNAL_EN_RTEIEN_SHIFT (12U) +/*! RTEIEN - Re-Tuning Event Interrupt Enable + * 0b1..Enabled + * 0b0..Masked + */ #define USDHC_INT_SIGNAL_EN_RTEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_RTEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_RTEIEN_MASK) #define USDHC_INT_SIGNAL_EN_TPIEN_MASK (0x4000U) #define USDHC_INT_SIGNAL_EN_TPIEN_SHIFT (14U) +/*! TPIEN - Tuning Pass Interrupt Enable + * 0b1..Enabled + * 0b0..Masked + */ #define USDHC_INT_SIGNAL_EN_TPIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_TPIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_TPIEN_MASK) #define USDHC_INT_SIGNAL_EN_CTOEIEN_MASK (0x10000U) #define USDHC_INT_SIGNAL_EN_CTOEIEN_SHIFT (16U) +/*! CTOEIEN - Command Timeout Error Interrupt Enable + * 0b1..Enabled + * 0b0..Masked + */ #define USDHC_INT_SIGNAL_EN_CTOEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CTOEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CTOEIEN_MASK) #define USDHC_INT_SIGNAL_EN_CCEIEN_MASK (0x20000U) #define USDHC_INT_SIGNAL_EN_CCEIEN_SHIFT (17U) +/*! CCEIEN - Command CRC Error Interrupt Enable + * 0b1..Enabled + * 0b0..Masked + */ #define USDHC_INT_SIGNAL_EN_CCEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CCEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CCEIEN_MASK) #define USDHC_INT_SIGNAL_EN_CEBEIEN_MASK (0x40000U) #define USDHC_INT_SIGNAL_EN_CEBEIEN_SHIFT (18U) +/*! CEBEIEN - Command End Bit Error Interrupt Enable + * 0b1..Enabled + * 0b0..Masked + */ #define USDHC_INT_SIGNAL_EN_CEBEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CEBEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CEBEIEN_MASK) #define USDHC_INT_SIGNAL_EN_CIEIEN_MASK (0x80000U) #define USDHC_INT_SIGNAL_EN_CIEIEN_SHIFT (19U) +/*! CIEIEN - Command Index Error Interrupt Enable + * 0b1..Enabled + * 0b0..Masked + */ #define USDHC_INT_SIGNAL_EN_CIEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CIEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CIEIEN_MASK) #define USDHC_INT_SIGNAL_EN_DTOEIEN_MASK (0x100000U) #define USDHC_INT_SIGNAL_EN_DTOEIEN_SHIFT (20U) +/*! DTOEIEN - Data Timeout Error Interrupt Enable + * 0b1..Enabled + * 0b0..Masked + */ #define USDHC_INT_SIGNAL_EN_DTOEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DTOEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DTOEIEN_MASK) #define USDHC_INT_SIGNAL_EN_DCEIEN_MASK (0x200000U) #define USDHC_INT_SIGNAL_EN_DCEIEN_SHIFT (21U) +/*! DCEIEN - Data CRC Error Interrupt Enable + * 0b1..Enabled + * 0b0..Masked + */ #define USDHC_INT_SIGNAL_EN_DCEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DCEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DCEIEN_MASK) #define USDHC_INT_SIGNAL_EN_DEBEIEN_MASK (0x400000U) #define USDHC_INT_SIGNAL_EN_DEBEIEN_SHIFT (22U) +/*! DEBEIEN - Data End Bit Error Interrupt Enable + * 0b1..Enabled + * 0b0..Masked + */ #define USDHC_INT_SIGNAL_EN_DEBEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DEBEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DEBEIEN_MASK) #define USDHC_INT_SIGNAL_EN_AC12EIEN_MASK (0x1000000U) #define USDHC_INT_SIGNAL_EN_AC12EIEN_SHIFT (24U) +/*! AC12EIEN - Auto CMD12 Error Interrupt Enable + * 0b1..Enabled + * 0b0..Masked + */ #define USDHC_INT_SIGNAL_EN_AC12EIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_AC12EIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_AC12EIEN_MASK) #define USDHC_INT_SIGNAL_EN_TNEIEN_MASK (0x4000000U) #define USDHC_INT_SIGNAL_EN_TNEIEN_SHIFT (26U) +/*! TNEIEN - Tuning Error Interrupt Enable + * 0b1..Enabled + * 0b0..Masked + */ #define USDHC_INT_SIGNAL_EN_TNEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_TNEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_TNEIEN_MASK) #define USDHC_INT_SIGNAL_EN_DMAEIEN_MASK (0x10000000U) #define USDHC_INT_SIGNAL_EN_DMAEIEN_SHIFT (28U) +/*! DMAEIEN - DMA Error Interrupt Enable + * 0b1..Enable + * 0b0..Masked + */ #define USDHC_INT_SIGNAL_EN_DMAEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DMAEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DMAEIEN_MASK) +/*! @} */ /*! @name AUTOCMD12_ERR_STATUS - Auto CMD12 Error Status */ +/*! @{ */ #define USDHC_AUTOCMD12_ERR_STATUS_AC12NE_MASK (0x1U) #define USDHC_AUTOCMD12_ERR_STATUS_AC12NE_SHIFT (0U) +/*! AC12NE - Auto CMD12 Not Executed + * 0b1..Not executed + * 0b0..Executed + */ #define USDHC_AUTOCMD12_ERR_STATUS_AC12NE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12NE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12NE_MASK) #define USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_MASK (0x2U) #define USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_SHIFT (1U) +/*! AC12TOE - Auto CMD12 / 23 Timeout Error + * 0b1..Time out + * 0b0..No error + */ #define USDHC_AUTOCMD12_ERR_STATUS_AC12TOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_MASK) #define USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_MASK (0x4U) #define USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_SHIFT (2U) +/*! AC12EBE - Auto CMD12 / 23 End Bit Error + * 0b1..End Bit Error Generated + * 0b0..No error + */ #define USDHC_AUTOCMD12_ERR_STATUS_AC12EBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_MASK) #define USDHC_AUTOCMD12_ERR_STATUS_AC12CE_MASK (0x8U) #define USDHC_AUTOCMD12_ERR_STATUS_AC12CE_SHIFT (3U) +/*! AC12CE - Auto CMD12 / 23 CRC Error + * 0b1..CRC Error Met in Auto CMD12/23 Response + * 0b0..No CRC error + */ #define USDHC_AUTOCMD12_ERR_STATUS_AC12CE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12CE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12CE_MASK) #define USDHC_AUTOCMD12_ERR_STATUS_AC12IE_MASK (0x10U) #define USDHC_AUTOCMD12_ERR_STATUS_AC12IE_SHIFT (4U) +/*! AC12IE - Auto CMD12 / 23 Index Error + * 0b1..Error, the CMD index in response is not CMD12/23 + * 0b0..No error + */ #define USDHC_AUTOCMD12_ERR_STATUS_AC12IE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12IE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12IE_MASK) #define USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_MASK (0x80U) #define USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_SHIFT (7U) +/*! CNIBAC12E - Command Not Issued By Auto CMD12 Error + * 0b1..Not Issued + * 0b0..No error + */ #define USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_MASK) #define USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_MASK (0x400000U) #define USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_SHIFT (22U) #define USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_MASK) #define USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_MASK (0x800000U) #define USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_SHIFT (23U) +/*! SMP_CLK_SEL - Sample Clock Select + * 0b1..Tuned clock is used to sample data + * 0b0..Fixed clock is used to sample data + */ #define USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_MASK) +/*! @} */ /*! @name HOST_CTRL_CAP - Host Controller Capabilities */ +/*! @{ */ #define USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_MASK (0x1U) #define USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_SHIFT (0U) #define USDHC_HOST_CTRL_CAP_SDR50_SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_SHIFT)) & USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_MASK) @@ -25363,36 +39769,82 @@ typedef struct { #define USDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING_SHIFT)) & USDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING_MASK) #define USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_MASK (0x2000U) #define USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_SHIFT (13U) +/*! USE_TUNING_SDR50 - Use Tuning for SDR50 + * 0b1..SDR50 requires tuning + * 0b0..SDR does not require tuning + */ #define USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_SHIFT)) & USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_MASK) #define USDHC_HOST_CTRL_CAP_RETUNING_MODE_MASK (0xC000U) #define USDHC_HOST_CTRL_CAP_RETUNING_MODE_SHIFT (14U) +/*! RETUNING_MODE - Retuning Mode + * 0b00..Mode 1 + * 0b01..Mode 2 + * 0b10..Mode 3 + * 0b11..Reserved + */ #define USDHC_HOST_CTRL_CAP_RETUNING_MODE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_RETUNING_MODE_SHIFT)) & USDHC_HOST_CTRL_CAP_RETUNING_MODE_MASK) #define USDHC_HOST_CTRL_CAP_MBL_MASK (0x70000U) #define USDHC_HOST_CTRL_CAP_MBL_SHIFT (16U) +/*! MBL - Max Block Length + * 0b000..512 bytes + * 0b001..1024 bytes + * 0b010..2048 bytes + * 0b011..4096 bytes + */ #define USDHC_HOST_CTRL_CAP_MBL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_MBL_SHIFT)) & USDHC_HOST_CTRL_CAP_MBL_MASK) #define USDHC_HOST_CTRL_CAP_ADMAS_MASK (0x100000U) #define USDHC_HOST_CTRL_CAP_ADMAS_SHIFT (20U) +/*! ADMAS - ADMA Support + * 0b1..Advanced DMA Supported + * 0b0..Advanced DMA Not supported + */ #define USDHC_HOST_CTRL_CAP_ADMAS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_ADMAS_SHIFT)) & USDHC_HOST_CTRL_CAP_ADMAS_MASK) #define USDHC_HOST_CTRL_CAP_HSS_MASK (0x200000U) #define USDHC_HOST_CTRL_CAP_HSS_SHIFT (21U) +/*! HSS - High Speed Support + * 0b1..High Speed Supported + * 0b0..High Speed Not Supported + */ #define USDHC_HOST_CTRL_CAP_HSS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_HSS_SHIFT)) & USDHC_HOST_CTRL_CAP_HSS_MASK) #define USDHC_HOST_CTRL_CAP_DMAS_MASK (0x400000U) #define USDHC_HOST_CTRL_CAP_DMAS_SHIFT (22U) +/*! DMAS - DMA Support + * 0b1..DMA Supported + * 0b0..DMA not supported + */ #define USDHC_HOST_CTRL_CAP_DMAS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_DMAS_SHIFT)) & USDHC_HOST_CTRL_CAP_DMAS_MASK) #define USDHC_HOST_CTRL_CAP_SRS_MASK (0x800000U) #define USDHC_HOST_CTRL_CAP_SRS_SHIFT (23U) +/*! SRS - Suspend / Resume Support + * 0b1..Supported + * 0b0..Not supported + */ #define USDHC_HOST_CTRL_CAP_SRS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_SRS_SHIFT)) & USDHC_HOST_CTRL_CAP_SRS_MASK) #define USDHC_HOST_CTRL_CAP_VS33_MASK (0x1000000U) #define USDHC_HOST_CTRL_CAP_VS33_SHIFT (24U) +/*! VS33 - Voltage Support 3.3V + * 0b1..3.3V supported + * 0b0..3.3V not supported + */ #define USDHC_HOST_CTRL_CAP_VS33(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_VS33_SHIFT)) & USDHC_HOST_CTRL_CAP_VS33_MASK) #define USDHC_HOST_CTRL_CAP_VS30_MASK (0x2000000U) #define USDHC_HOST_CTRL_CAP_VS30_SHIFT (25U) +/*! VS30 - Voltage Support 3.0 V + * 0b1..3.0V supported + * 0b0..3.0V not supported + */ #define USDHC_HOST_CTRL_CAP_VS30(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_VS30_SHIFT)) & USDHC_HOST_CTRL_CAP_VS30_MASK) #define USDHC_HOST_CTRL_CAP_VS18_MASK (0x4000000U) #define USDHC_HOST_CTRL_CAP_VS18_SHIFT (26U) +/*! VS18 - Voltage Support 1.8 V + * 0b1..1.8V supported + * 0b0..1.8V not supported + */ #define USDHC_HOST_CTRL_CAP_VS18(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_VS18_SHIFT)) & USDHC_HOST_CTRL_CAP_VS18_MASK) +/*! @} */ /*! @name WTMK_LVL - Watermark Level */ +/*! @{ */ #define USDHC_WTMK_LVL_RD_WML_MASK (0xFFU) #define USDHC_WTMK_LVL_RD_WML_SHIFT (0U) #define USDHC_WTMK_LVL_RD_WML(x) (((uint32_t)(((uint32_t)(x)) << USDHC_WTMK_LVL_RD_WML_SHIFT)) & USDHC_WTMK_LVL_RD_WML_MASK) @@ -25405,25 +39857,47 @@ typedef struct { #define USDHC_WTMK_LVL_WR_BRST_LEN_MASK (0x1F000000U) #define USDHC_WTMK_LVL_WR_BRST_LEN_SHIFT (24U) #define USDHC_WTMK_LVL_WR_BRST_LEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_WTMK_LVL_WR_BRST_LEN_SHIFT)) & USDHC_WTMK_LVL_WR_BRST_LEN_MASK) +/*! @} */ /*! @name MIX_CTRL - Mixer Control */ +/*! @{ */ #define USDHC_MIX_CTRL_DMAEN_MASK (0x1U) #define USDHC_MIX_CTRL_DMAEN_SHIFT (0U) +/*! DMAEN - DMA Enable + * 0b1..Enable + * 0b0..Disable + */ #define USDHC_MIX_CTRL_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_DMAEN_SHIFT)) & USDHC_MIX_CTRL_DMAEN_MASK) #define USDHC_MIX_CTRL_BCEN_MASK (0x2U) #define USDHC_MIX_CTRL_BCEN_SHIFT (1U) +/*! BCEN - Block Count Enable + * 0b1..Enable + * 0b0..Disable + */ #define USDHC_MIX_CTRL_BCEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_BCEN_SHIFT)) & USDHC_MIX_CTRL_BCEN_MASK) #define USDHC_MIX_CTRL_AC12EN_MASK (0x4U) #define USDHC_MIX_CTRL_AC12EN_SHIFT (2U) +/*! AC12EN - Auto CMD12 Enable + * 0b1..Enable + * 0b0..Disable + */ #define USDHC_MIX_CTRL_AC12EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_AC12EN_SHIFT)) & USDHC_MIX_CTRL_AC12EN_MASK) #define USDHC_MIX_CTRL_DDR_EN_MASK (0x8U) #define USDHC_MIX_CTRL_DDR_EN_SHIFT (3U) #define USDHC_MIX_CTRL_DDR_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_DDR_EN_SHIFT)) & USDHC_MIX_CTRL_DDR_EN_MASK) #define USDHC_MIX_CTRL_DTDSEL_MASK (0x10U) #define USDHC_MIX_CTRL_DTDSEL_SHIFT (4U) +/*! DTDSEL - Data Transfer Direction Select + * 0b1..Read (Card to Host) + * 0b0..Write (Host to Card) + */ #define USDHC_MIX_CTRL_DTDSEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_DTDSEL_SHIFT)) & USDHC_MIX_CTRL_DTDSEL_MASK) #define USDHC_MIX_CTRL_MSBSEL_MASK (0x20U) #define USDHC_MIX_CTRL_MSBSEL_SHIFT (5U) +/*! MSBSEL - Multi / Single Block Select + * 0b1..Multiple Blocks + * 0b0..Single Block + */ #define USDHC_MIX_CTRL_MSBSEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_MSBSEL_SHIFT)) & USDHC_MIX_CTRL_MSBSEL_MASK) #define USDHC_MIX_CTRL_NIBBLE_POS_MASK (0x40U) #define USDHC_MIX_CTRL_NIBBLE_POS_SHIFT (6U) @@ -25433,18 +39907,36 @@ typedef struct { #define USDHC_MIX_CTRL_AC23EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_AC23EN_SHIFT)) & USDHC_MIX_CTRL_AC23EN_MASK) #define USDHC_MIX_CTRL_EXE_TUNE_MASK (0x400000U) #define USDHC_MIX_CTRL_EXE_TUNE_SHIFT (22U) +/*! EXE_TUNE - Execute Tuning: (Only used for SD3.0, SDR104 mode and EMMC HS200 mode) + * 0b1..Execute Tuning + * 0b0..Not Tuned or Tuning Completed + */ #define USDHC_MIX_CTRL_EXE_TUNE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_EXE_TUNE_SHIFT)) & USDHC_MIX_CTRL_EXE_TUNE_MASK) #define USDHC_MIX_CTRL_SMP_CLK_SEL_MASK (0x800000U) #define USDHC_MIX_CTRL_SMP_CLK_SEL_SHIFT (23U) +/*! SMP_CLK_SEL - SMP_CLK_SEL + * 0b1..Tuned clock is used to sample data / cmd + * 0b0..Fixed clock is used to sample data / cmd + */ #define USDHC_MIX_CTRL_SMP_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_SMP_CLK_SEL_SHIFT)) & USDHC_MIX_CTRL_SMP_CLK_SEL_MASK) #define USDHC_MIX_CTRL_AUTO_TUNE_EN_MASK (0x1000000U) #define USDHC_MIX_CTRL_AUTO_TUNE_EN_SHIFT (24U) +/*! AUTO_TUNE_EN - Auto Tuning Enable (Only used for SD3.0, SDR104 mode and and EMMC HS200 mode) + * 0b1..Enable auto tuning + * 0b0..Disable auto tuning + */ #define USDHC_MIX_CTRL_AUTO_TUNE_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_AUTO_TUNE_EN_SHIFT)) & USDHC_MIX_CTRL_AUTO_TUNE_EN_MASK) #define USDHC_MIX_CTRL_FBCLK_SEL_MASK (0x2000000U) #define USDHC_MIX_CTRL_FBCLK_SEL_SHIFT (25U) +/*! FBCLK_SEL - Feedback Clock Source Selection (Only used for SD3.0, SDR104 mode and EMMC HS200 mode) + * 0b1..Feedback clock comes from the ipp_card_clk_out + * 0b0..Feedback clock comes from the loopback CLK + */ #define USDHC_MIX_CTRL_FBCLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_FBCLK_SEL_SHIFT)) & USDHC_MIX_CTRL_FBCLK_SEL_MASK) +/*! @} */ /*! @name FORCE_EVENT - Force Event */ +/*! @{ */ #define USDHC_FORCE_EVENT_FEVTAC12NE_MASK (0x1U) #define USDHC_FORCE_EVENT_FEVTAC12NE_SHIFT (0U) #define USDHC_FORCE_EVENT_FEVTAC12NE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12NE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12NE_MASK) @@ -25496,24 +39988,38 @@ typedef struct { #define USDHC_FORCE_EVENT_FEVTCINT_MASK (0x80000000U) #define USDHC_FORCE_EVENT_FEVTCINT_SHIFT (31U) #define USDHC_FORCE_EVENT_FEVTCINT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCINT_SHIFT)) & USDHC_FORCE_EVENT_FEVTCINT_MASK) +/*! @} */ /*! @name ADMA_ERR_STATUS - ADMA Error Status Register */ +/*! @{ */ #define USDHC_ADMA_ERR_STATUS_ADMAES_MASK (0x3U) #define USDHC_ADMA_ERR_STATUS_ADMAES_SHIFT (0U) #define USDHC_ADMA_ERR_STATUS_ADMAES(x) (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_ERR_STATUS_ADMAES_SHIFT)) & USDHC_ADMA_ERR_STATUS_ADMAES_MASK) #define USDHC_ADMA_ERR_STATUS_ADMALME_MASK (0x4U) #define USDHC_ADMA_ERR_STATUS_ADMALME_SHIFT (2U) +/*! ADMALME - ADMA Length Mismatch Error + * 0b1..Error + * 0b0..No Error + */ #define USDHC_ADMA_ERR_STATUS_ADMALME(x) (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_ERR_STATUS_ADMALME_SHIFT)) & USDHC_ADMA_ERR_STATUS_ADMALME_MASK) #define USDHC_ADMA_ERR_STATUS_ADMADCE_MASK (0x8U) #define USDHC_ADMA_ERR_STATUS_ADMADCE_SHIFT (3U) +/*! ADMADCE - ADMA Descriptor Error + * 0b1..Error + * 0b0..No Error + */ #define USDHC_ADMA_ERR_STATUS_ADMADCE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_ERR_STATUS_ADMADCE_SHIFT)) & USDHC_ADMA_ERR_STATUS_ADMADCE_MASK) +/*! @} */ /*! @name ADMA_SYS_ADDR - ADMA System Address */ +/*! @{ */ #define USDHC_ADMA_SYS_ADDR_ADS_ADDR_MASK (0xFFFFFFFCU) #define USDHC_ADMA_SYS_ADDR_ADS_ADDR_SHIFT (2U) #define USDHC_ADMA_SYS_ADDR_ADS_ADDR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_SYS_ADDR_ADS_ADDR_SHIFT)) & USDHC_ADMA_SYS_ADDR_ADS_ADDR_MASK) +/*! @} */ /*! @name DLL_CTRL - DLL (Delay Line) Control */ +/*! @{ */ #define USDHC_DLL_CTRL_DLL_CTRL_ENABLE_MASK (0x1U) #define USDHC_DLL_CTRL_DLL_CTRL_ENABLE_SHIFT (0U) #define USDHC_DLL_CTRL_DLL_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_ENABLE_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_ENABLE_MASK) @@ -25544,8 +40050,10 @@ typedef struct { #define USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_MASK (0xF0000000U) #define USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_SHIFT (28U) #define USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_MASK) +/*! @} */ /*! @name DLL_STATUS - DLL Status */ +/*! @{ */ #define USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_MASK (0x1U) #define USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_SHIFT (0U) #define USDHC_DLL_STATUS_DLL_STS_SLV_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_MASK) @@ -25558,8 +40066,10 @@ typedef struct { #define USDHC_DLL_STATUS_DLL_STS_REF_SEL_MASK (0xFE00U) #define USDHC_DLL_STATUS_DLL_STS_REF_SEL_SHIFT (9U) #define USDHC_DLL_STATUS_DLL_STS_REF_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_REF_SEL_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_REF_SEL_MASK) +/*! @} */ /*! @name CLK_TUNE_CTRL_STATUS - CLK Tuning Control and Status */ +/*! @{ */ #define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_MASK (0xFU) #define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_SHIFT (0U) #define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_MASK) @@ -25584,53 +40094,115 @@ typedef struct { #define USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_MASK (0x80000000U) #define USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_SHIFT (31U) #define USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_MASK) +/*! @} */ /*! @name VEND_SPEC - Vendor Specific Register */ +/*! @{ */ #define USDHC_VEND_SPEC_VSELECT_MASK (0x2U) #define USDHC_VEND_SPEC_VSELECT_SHIFT (1U) +/*! VSELECT - Voltage Selection + * 0b1..Change the voltage to low voltage range, around 1.8 V + * 0b0..Change the voltage to high voltage range, around 3.0 V + */ #define USDHC_VEND_SPEC_VSELECT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_VSELECT_SHIFT)) & USDHC_VEND_SPEC_VSELECT_MASK) #define USDHC_VEND_SPEC_CONFLICT_CHK_EN_MASK (0x4U) #define USDHC_VEND_SPEC_CONFLICT_CHK_EN_SHIFT (2U) +/*! CONFLICT_CHK_EN - Conflict check enable. + * 0b0..Conflict check disable + * 0b1..Conflict check enable + */ #define USDHC_VEND_SPEC_CONFLICT_CHK_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_CONFLICT_CHK_EN_SHIFT)) & USDHC_VEND_SPEC_CONFLICT_CHK_EN_MASK) #define USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_MASK (0x8U) #define USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_SHIFT (3U) +/*! AC12_WR_CHKBUSY_EN - AC12_WR_CHKBUSY_EN + * 0b0..Do not check busy after auto CMD12 for write data packet + * 0b1..Check busy after auto CMD12 for write data packet + */ #define USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_SHIFT)) & USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_MASK) #define USDHC_VEND_SPEC_FRC_SDCLK_ON_MASK (0x100U) #define USDHC_VEND_SPEC_FRC_SDCLK_ON_SHIFT (8U) +/*! FRC_SDCLK_ON - FRC_SDCLK_ON + * 0b0..CLK active or inactive is fully controlled by the hardware. + * 0b1..Force CLK active. + */ #define USDHC_VEND_SPEC_FRC_SDCLK_ON(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_FRC_SDCLK_ON_SHIFT)) & USDHC_VEND_SPEC_FRC_SDCLK_ON_MASK) #define USDHC_VEND_SPEC_CRC_CHK_DIS_MASK (0x8000U) #define USDHC_VEND_SPEC_CRC_CHK_DIS_SHIFT (15U) +/*! CRC_CHK_DIS - CRC Check Disable + * 0b0..Check CRC16 for every read data packet and check CRC bits for every write data packet + * 0b1..Ignore CRC16 check for every read data packet and ignore CRC bits check for every write data packet + */ #define USDHC_VEND_SPEC_CRC_CHK_DIS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_CRC_CHK_DIS_SHIFT)) & USDHC_VEND_SPEC_CRC_CHK_DIS_MASK) #define USDHC_VEND_SPEC_CMD_BYTE_EN_MASK (0x80000000U) #define USDHC_VEND_SPEC_CMD_BYTE_EN_SHIFT (31U) +/*! CMD_BYTE_EN - CMD_BYTE_EN + * 0b0..Disable + * 0b1..Enable + */ #define USDHC_VEND_SPEC_CMD_BYTE_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_CMD_BYTE_EN_SHIFT)) & USDHC_VEND_SPEC_CMD_BYTE_EN_MASK) +/*! @} */ /*! @name MMC_BOOT - MMC Boot Register */ +/*! @{ */ #define USDHC_MMC_BOOT_DTOCV_ACK_MASK (0xFU) #define USDHC_MMC_BOOT_DTOCV_ACK_SHIFT (0U) +/*! DTOCV_ACK - DTOCV_ACK + * 0b0000..SDCLK x 2^14 + * 0b0001..SDCLK x 2^15 + * 0b0010..SDCLK x 2^16 + * 0b0011..SDCLK x 2^17 + * 0b0100..SDCLK x 2^18 + * 0b0101..SDCLK x 2^19 + * 0b0110..SDCLK x 2^20 + * 0b0111..SDCLK x 2^21 + * 0b1110..SDCLK x 2^28 + * 0b1111..SDCLK x 2^29 + */ #define USDHC_MMC_BOOT_DTOCV_ACK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_DTOCV_ACK_SHIFT)) & USDHC_MMC_BOOT_DTOCV_ACK_MASK) #define USDHC_MMC_BOOT_BOOT_ACK_MASK (0x10U) #define USDHC_MMC_BOOT_BOOT_ACK_SHIFT (4U) +/*! BOOT_ACK - BOOT_ACK + * 0b0..No ack + * 0b1..Ack + */ #define USDHC_MMC_BOOT_BOOT_ACK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_ACK_SHIFT)) & USDHC_MMC_BOOT_BOOT_ACK_MASK) #define USDHC_MMC_BOOT_BOOT_MODE_MASK (0x20U) #define USDHC_MMC_BOOT_BOOT_MODE_SHIFT (5U) +/*! BOOT_MODE - BOOT_MODE + * 0b0..Normal boot + * 0b1..Alternative boot + */ #define USDHC_MMC_BOOT_BOOT_MODE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_MODE_SHIFT)) & USDHC_MMC_BOOT_BOOT_MODE_MASK) #define USDHC_MMC_BOOT_BOOT_EN_MASK (0x40U) #define USDHC_MMC_BOOT_BOOT_EN_SHIFT (6U) +/*! BOOT_EN - BOOT_EN + * 0b0..Fast boot disable + * 0b1..Fast boot enable + */ #define USDHC_MMC_BOOT_BOOT_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_EN_SHIFT)) & USDHC_MMC_BOOT_BOOT_EN_MASK) #define USDHC_MMC_BOOT_AUTO_SABG_EN_MASK (0x80U) #define USDHC_MMC_BOOT_AUTO_SABG_EN_SHIFT (7U) #define USDHC_MMC_BOOT_AUTO_SABG_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_AUTO_SABG_EN_SHIFT)) & USDHC_MMC_BOOT_AUTO_SABG_EN_MASK) #define USDHC_MMC_BOOT_DISABLE_TIME_OUT_MASK (0x100U) #define USDHC_MMC_BOOT_DISABLE_TIME_OUT_SHIFT (8U) +/*! DISABLE_TIME_OUT - Disable Time Out + * 0b0..Enable time out + * 0b1..Disable time out + */ #define USDHC_MMC_BOOT_DISABLE_TIME_OUT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_DISABLE_TIME_OUT_SHIFT)) & USDHC_MMC_BOOT_DISABLE_TIME_OUT_MASK) #define USDHC_MMC_BOOT_BOOT_BLK_CNT_MASK (0xFFFF0000U) #define USDHC_MMC_BOOT_BOOT_BLK_CNT_SHIFT (16U) #define USDHC_MMC_BOOT_BOOT_BLK_CNT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_BLK_CNT_SHIFT)) & USDHC_MMC_BOOT_BOOT_BLK_CNT_MASK) +/*! @} */ /*! @name VEND_SPEC2 - Vendor Specific 2 Register */ +/*! @{ */ #define USDHC_VEND_SPEC2_CARD_INT_D3_TEST_MASK (0x8U) #define USDHC_VEND_SPEC2_CARD_INT_D3_TEST_SHIFT (3U) +/*! CARD_INT_D3_TEST - Card Interrupt Detection Test + * 0b0..Check the card interrupt only when DATA3 is high. + * 0b1..Check the card interrupt by ignoring the status of DATA3. + */ #define USDHC_VEND_SPEC2_CARD_INT_D3_TEST(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_CARD_INT_D3_TEST_SHIFT)) & USDHC_VEND_SPEC2_CARD_INT_D3_TEST_MASK) #define USDHC_VEND_SPEC2_TUNING_8bit_EN_MASK (0x10U) #define USDHC_VEND_SPEC2_TUNING_8bit_EN_SHIFT (4U) @@ -25640,15 +40212,28 @@ typedef struct { #define USDHC_VEND_SPEC2_TUNING_1bit_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_TUNING_1bit_EN_SHIFT)) & USDHC_VEND_SPEC2_TUNING_1bit_EN_MASK) #define USDHC_VEND_SPEC2_TUNING_CMD_EN_MASK (0x40U) #define USDHC_VEND_SPEC2_TUNING_CMD_EN_SHIFT (6U) +/*! TUNING_CMD_EN - TUNING_CMD_EN + * 0b0..Auto tuning circuit does not check the CMD line. + * 0b1..Auto tuning circuit checks the CMD line. + */ #define USDHC_VEND_SPEC2_TUNING_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_TUNING_CMD_EN_SHIFT)) & USDHC_VEND_SPEC2_TUNING_CMD_EN_MASK) #define USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_MASK (0x1000U) #define USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_SHIFT (12U) +/*! ACMD23_ARGU2_EN - Argument2 register enable for ACMD23 + * 0b1..Argument2 register enable for ACMD23 sharing with SDMA system address register. Default is enable. + * 0b0..Disable + */ #define USDHC_VEND_SPEC2_ACMD23_ARGU2_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_SHIFT)) & USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_MASK) -#define USDHC_VEND_SPEC2_AHB_RST_MASK (0x4000U) -#define USDHC_VEND_SPEC2_AHB_RST_SHIFT (14U) -#define USDHC_VEND_SPEC2_AHB_RST(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_AHB_RST_SHIFT)) & USDHC_VEND_SPEC2_AHB_RST_MASK) +#define USDHC_VEND_SPEC2_PART_DLL_DEBUG_MASK (0x2000U) +#define USDHC_VEND_SPEC2_PART_DLL_DEBUG_SHIFT (13U) +#define USDHC_VEND_SPEC2_PART_DLL_DEBUG(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_PART_DLL_DEBUG_SHIFT)) & USDHC_VEND_SPEC2_PART_DLL_DEBUG_MASK) +#define USDHC_VEND_SPEC2_BUS_RST_MASK (0x4000U) +#define USDHC_VEND_SPEC2_BUS_RST_SHIFT (14U) +#define USDHC_VEND_SPEC2_BUS_RST(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_BUS_RST_SHIFT)) & USDHC_VEND_SPEC2_BUS_RST_MASK) +/*! @} */ /*! @name TUNING_CTRL - Tuning Control Register */ +/*! @{ */ #define USDHC_TUNING_CTRL_TUNING_START_TAP_MASK (0xFFU) #define USDHC_TUNING_CTRL_TUNING_START_TAP_SHIFT (0U) #define USDHC_TUNING_CTRL_TUNING_START_TAP(x) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_START_TAP_SHIFT)) & USDHC_TUNING_CTRL_TUNING_START_TAP_MASK) @@ -25664,6 +40249,7 @@ typedef struct { #define USDHC_TUNING_CTRL_STD_TUNING_EN_MASK (0x1000000U) #define USDHC_TUNING_CTRL_STD_TUNING_EN_SHIFT (24U) #define USDHC_TUNING_CTRL_STD_TUNING_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_STD_TUNING_EN_SHIFT)) & USDHC_TUNING_CTRL_STD_TUNING_EN_MASK) +/*! @} */ /*! @@ -25720,65 +40306,148 @@ typedef struct { */ /*! @name WCR - Watchdog Control Register */ +/*! @{ */ #define WDOG_WCR_WDZST_MASK (0x1U) #define WDOG_WCR_WDZST_SHIFT (0U) +/*! WDZST - WDZST + * 0b0..Continue timer operation (Default). + * 0b1..Suspend the watchdog timer. + */ #define WDOG_WCR_WDZST(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDZST_SHIFT)) & WDOG_WCR_WDZST_MASK) #define WDOG_WCR_WDBG_MASK (0x2U) #define WDOG_WCR_WDBG_SHIFT (1U) +/*! WDBG - WDBG + * 0b0..Continue WDOG timer operation (Default). + * 0b1..Suspend the watchdog timer. + */ #define WDOG_WCR_WDBG(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDBG_SHIFT)) & WDOG_WCR_WDBG_MASK) #define WDOG_WCR_WDE_MASK (0x4U) #define WDOG_WCR_WDE_SHIFT (2U) +/*! WDE - WDE + * 0b0..Disable the Watchdog (Default). + * 0b1..Enable the Watchdog. + */ #define WDOG_WCR_WDE(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDE_SHIFT)) & WDOG_WCR_WDE_MASK) #define WDOG_WCR_WDT_MASK (0x8U) #define WDOG_WCR_WDT_SHIFT (3U) +/*! WDT - WDT + * 0b0..No effect on WDOG_B (Default). + * 0b1..Assert WDOG_B upon a Watchdog Time-out event. + */ #define WDOG_WCR_WDT(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDT_SHIFT)) & WDOG_WCR_WDT_MASK) #define WDOG_WCR_SRS_MASK (0x10U) #define WDOG_WCR_SRS_SHIFT (4U) +/*! SRS - SRS + * 0b0..Assert system reset signal. + * 0b1..No effect on the system (Default). + */ #define WDOG_WCR_SRS(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_SRS_SHIFT)) & WDOG_WCR_SRS_MASK) #define WDOG_WCR_WDA_MASK (0x20U) #define WDOG_WCR_WDA_SHIFT (5U) +/*! WDA - WDA + * 0b0..Assert WDOG_B output. + * 0b1..No effect on system (Default). + */ #define WDOG_WCR_WDA(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDA_SHIFT)) & WDOG_WCR_WDA_MASK) #define WDOG_WCR_SRE_MASK (0x40U) #define WDOG_WCR_SRE_SHIFT (6U) +/*! SRE - software reset extension, an option way to generate software reset + * 0b0..using original way to generate software reset (default) + * 0b1..using new way to generate software reset. + */ #define WDOG_WCR_SRE(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_SRE_SHIFT)) & WDOG_WCR_SRE_MASK) #define WDOG_WCR_WDW_MASK (0x80U) #define WDOG_WCR_WDW_SHIFT (7U) +/*! WDW - WDW + * 0b0..Continue WDOG timer operation (Default). + * 0b1..Suspend WDOG timer operation. + */ #define WDOG_WCR_WDW(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDW_SHIFT)) & WDOG_WCR_WDW_MASK) #define WDOG_WCR_WT_MASK (0xFF00U) #define WDOG_WCR_WT_SHIFT (8U) +/*! WT - WT + * 0b00000000..- 0.5 Seconds (Default). + * 0b00000001..- 1.0 Seconds. + * 0b00000010..- 1.5 Seconds. + * 0b00000011..- 2.0 Seconds. + * 0b11111111..- 128 Seconds. + */ #define WDOG_WCR_WT(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WT_SHIFT)) & WDOG_WCR_WT_MASK) +/*! @} */ /*! @name WSR - Watchdog Service Register */ +/*! @{ */ #define WDOG_WSR_WSR_MASK (0xFFFFU) #define WDOG_WSR_WSR_SHIFT (0U) +/*! WSR - WSR + * 0b0101010101010101..Write to the Watchdog Service Register (WDOG_WSR). + * 0b1010101010101010..Write to the Watchdog Service Register (WDOG_WSR). + */ #define WDOG_WSR_WSR(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WSR_WSR_SHIFT)) & WDOG_WSR_WSR_MASK) +/*! @} */ /*! @name WRSR - Watchdog Reset Status Register */ +/*! @{ */ #define WDOG_WRSR_SFTW_MASK (0x1U) #define WDOG_WRSR_SFTW_SHIFT (0U) +/*! SFTW - SFTW + * 0b0..Reset is not the result of a software reset. + * 0b1..Reset is the result of a software reset. + */ #define WDOG_WRSR_SFTW(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WRSR_SFTW_SHIFT)) & WDOG_WRSR_SFTW_MASK) #define WDOG_WRSR_TOUT_MASK (0x2U) #define WDOG_WRSR_TOUT_SHIFT (1U) +/*! TOUT - TOUT + * 0b0..Reset is not the result of a WDOG timeout. + * 0b1..Reset is the result of a WDOG timeout. + */ #define WDOG_WRSR_TOUT(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WRSR_TOUT_SHIFT)) & WDOG_WRSR_TOUT_MASK) #define WDOG_WRSR_POR_MASK (0x10U) #define WDOG_WRSR_POR_SHIFT (4U) +/*! POR - POR + * 0b0..Reset is not the result of a power on reset. + * 0b1..Reset is the result of a power on reset. + */ #define WDOG_WRSR_POR(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WRSR_POR_SHIFT)) & WDOG_WRSR_POR_MASK) +/*! @} */ /*! @name WICR - Watchdog Interrupt Control Register */ +/*! @{ */ #define WDOG_WICR_WICT_MASK (0xFFU) #define WDOG_WICR_WICT_SHIFT (0U) +/*! WICT - WICT + * 0b00000000..WICT[7:0] = Time duration between interrupt and time-out is 0 seconds. + * 0b00000001..WICT[7:0] = Time duration between interrupt and time-out is 0.5 seconds. + * 0b00000100..WICT[7:0] = Time duration between interrupt and time-out is 2 seconds (Default). + * 0b11111111..WICT[7:0] = Time duration between interrupt and time-out is 127.5 seconds. + */ #define WDOG_WICR_WICT(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WICR_WICT_SHIFT)) & WDOG_WICR_WICT_MASK) #define WDOG_WICR_WTIS_MASK (0x4000U) #define WDOG_WICR_WTIS_SHIFT (14U) +/*! WTIS - WTIS + * 0b0..No interrupt has occurred (Default). + * 0b1..Interrupt has occurred + */ #define WDOG_WICR_WTIS(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WICR_WTIS_SHIFT)) & WDOG_WICR_WTIS_MASK) #define WDOG_WICR_WIE_MASK (0x8000U) #define WDOG_WICR_WIE_SHIFT (15U) +/*! WIE - WIE + * 0b0..Disable Interrupt (Default). + * 0b1..Enable Interrupt. + */ #define WDOG_WICR_WIE(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WICR_WIE_SHIFT)) & WDOG_WICR_WIE_MASK) +/*! @} */ /*! @name WMCR - Watchdog Miscellaneous Control Register */ +/*! @{ */ #define WDOG_WMCR_PDE_MASK (0x1U) #define WDOG_WMCR_PDE_SHIFT (0U) +/*! PDE - PDE + * 0b0..Power Down Counter of WDOG is disabled. + * 0b1..Power Down Counter of WDOG is enabled (Default). + */ #define WDOG_WMCR_PDE(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WMCR_PDE_SHIFT)) & WDOG_WMCR_PDE_MASK) +/*! @} */ /*! @@ -25898,584 +40567,792 @@ typedef struct { */ /*! @name SEL0 - Crossbar A Select Register 0 */ +/*! @{ */ #define XBARA_SEL0_SEL0_MASK (0x7FU) #define XBARA_SEL0_SEL0_SHIFT (0U) #define XBARA_SEL0_SEL0(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL0_SEL0_SHIFT)) & XBARA_SEL0_SEL0_MASK) #define XBARA_SEL0_SEL1_MASK (0x7F00U) #define XBARA_SEL0_SEL1_SHIFT (8U) #define XBARA_SEL0_SEL1(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL0_SEL1_SHIFT)) & XBARA_SEL0_SEL1_MASK) +/*! @} */ /*! @name SEL1 - Crossbar A Select Register 1 */ +/*! @{ */ #define XBARA_SEL1_SEL2_MASK (0x7FU) #define XBARA_SEL1_SEL2_SHIFT (0U) #define XBARA_SEL1_SEL2(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL1_SEL2_SHIFT)) & XBARA_SEL1_SEL2_MASK) #define XBARA_SEL1_SEL3_MASK (0x7F00U) #define XBARA_SEL1_SEL3_SHIFT (8U) #define XBARA_SEL1_SEL3(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL1_SEL3_SHIFT)) & XBARA_SEL1_SEL3_MASK) +/*! @} */ /*! @name SEL2 - Crossbar A Select Register 2 */ +/*! @{ */ #define XBARA_SEL2_SEL4_MASK (0x7FU) #define XBARA_SEL2_SEL4_SHIFT (0U) #define XBARA_SEL2_SEL4(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL2_SEL4_SHIFT)) & XBARA_SEL2_SEL4_MASK) #define XBARA_SEL2_SEL5_MASK (0x7F00U) #define XBARA_SEL2_SEL5_SHIFT (8U) #define XBARA_SEL2_SEL5(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL2_SEL5_SHIFT)) & XBARA_SEL2_SEL5_MASK) +/*! @} */ /*! @name SEL3 - Crossbar A Select Register 3 */ +/*! @{ */ #define XBARA_SEL3_SEL6_MASK (0x7FU) #define XBARA_SEL3_SEL6_SHIFT (0U) #define XBARA_SEL3_SEL6(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL3_SEL6_SHIFT)) & XBARA_SEL3_SEL6_MASK) #define XBARA_SEL3_SEL7_MASK (0x7F00U) #define XBARA_SEL3_SEL7_SHIFT (8U) #define XBARA_SEL3_SEL7(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL3_SEL7_SHIFT)) & XBARA_SEL3_SEL7_MASK) +/*! @} */ /*! @name SEL4 - Crossbar A Select Register 4 */ +/*! @{ */ #define XBARA_SEL4_SEL8_MASK (0x7FU) #define XBARA_SEL4_SEL8_SHIFT (0U) #define XBARA_SEL4_SEL8(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL4_SEL8_SHIFT)) & XBARA_SEL4_SEL8_MASK) #define XBARA_SEL4_SEL9_MASK (0x7F00U) #define XBARA_SEL4_SEL9_SHIFT (8U) #define XBARA_SEL4_SEL9(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL4_SEL9_SHIFT)) & XBARA_SEL4_SEL9_MASK) +/*! @} */ /*! @name SEL5 - Crossbar A Select Register 5 */ +/*! @{ */ #define XBARA_SEL5_SEL10_MASK (0x7FU) #define XBARA_SEL5_SEL10_SHIFT (0U) #define XBARA_SEL5_SEL10(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL5_SEL10_SHIFT)) & XBARA_SEL5_SEL10_MASK) #define XBARA_SEL5_SEL11_MASK (0x7F00U) #define XBARA_SEL5_SEL11_SHIFT (8U) #define XBARA_SEL5_SEL11(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL5_SEL11_SHIFT)) & XBARA_SEL5_SEL11_MASK) +/*! @} */ /*! @name SEL6 - Crossbar A Select Register 6 */ +/*! @{ */ #define XBARA_SEL6_SEL12_MASK (0x7FU) #define XBARA_SEL6_SEL12_SHIFT (0U) #define XBARA_SEL6_SEL12(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL6_SEL12_SHIFT)) & XBARA_SEL6_SEL12_MASK) #define XBARA_SEL6_SEL13_MASK (0x7F00U) #define XBARA_SEL6_SEL13_SHIFT (8U) #define XBARA_SEL6_SEL13(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL6_SEL13_SHIFT)) & XBARA_SEL6_SEL13_MASK) +/*! @} */ /*! @name SEL7 - Crossbar A Select Register 7 */ +/*! @{ */ #define XBARA_SEL7_SEL14_MASK (0x7FU) #define XBARA_SEL7_SEL14_SHIFT (0U) #define XBARA_SEL7_SEL14(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL7_SEL14_SHIFT)) & XBARA_SEL7_SEL14_MASK) #define XBARA_SEL7_SEL15_MASK (0x7F00U) #define XBARA_SEL7_SEL15_SHIFT (8U) #define XBARA_SEL7_SEL15(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL7_SEL15_SHIFT)) & XBARA_SEL7_SEL15_MASK) +/*! @} */ /*! @name SEL8 - Crossbar A Select Register 8 */ +/*! @{ */ #define XBARA_SEL8_SEL16_MASK (0x7FU) #define XBARA_SEL8_SEL16_SHIFT (0U) #define XBARA_SEL8_SEL16(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL8_SEL16_SHIFT)) & XBARA_SEL8_SEL16_MASK) #define XBARA_SEL8_SEL17_MASK (0x7F00U) #define XBARA_SEL8_SEL17_SHIFT (8U) #define XBARA_SEL8_SEL17(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL8_SEL17_SHIFT)) & XBARA_SEL8_SEL17_MASK) +/*! @} */ /*! @name SEL9 - Crossbar A Select Register 9 */ +/*! @{ */ #define XBARA_SEL9_SEL18_MASK (0x7FU) #define XBARA_SEL9_SEL18_SHIFT (0U) #define XBARA_SEL9_SEL18(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL9_SEL18_SHIFT)) & XBARA_SEL9_SEL18_MASK) #define XBARA_SEL9_SEL19_MASK (0x7F00U) #define XBARA_SEL9_SEL19_SHIFT (8U) #define XBARA_SEL9_SEL19(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL9_SEL19_SHIFT)) & XBARA_SEL9_SEL19_MASK) +/*! @} */ /*! @name SEL10 - Crossbar A Select Register 10 */ +/*! @{ */ #define XBARA_SEL10_SEL20_MASK (0x7FU) #define XBARA_SEL10_SEL20_SHIFT (0U) #define XBARA_SEL10_SEL20(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL10_SEL20_SHIFT)) & XBARA_SEL10_SEL20_MASK) #define XBARA_SEL10_SEL21_MASK (0x7F00U) #define XBARA_SEL10_SEL21_SHIFT (8U) #define XBARA_SEL10_SEL21(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL10_SEL21_SHIFT)) & XBARA_SEL10_SEL21_MASK) +/*! @} */ /*! @name SEL11 - Crossbar A Select Register 11 */ +/*! @{ */ #define XBARA_SEL11_SEL22_MASK (0x7FU) #define XBARA_SEL11_SEL22_SHIFT (0U) #define XBARA_SEL11_SEL22(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL11_SEL22_SHIFT)) & XBARA_SEL11_SEL22_MASK) #define XBARA_SEL11_SEL23_MASK (0x7F00U) #define XBARA_SEL11_SEL23_SHIFT (8U) #define XBARA_SEL11_SEL23(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL11_SEL23_SHIFT)) & XBARA_SEL11_SEL23_MASK) +/*! @} */ /*! @name SEL12 - Crossbar A Select Register 12 */ +/*! @{ */ #define XBARA_SEL12_SEL24_MASK (0x7FU) #define XBARA_SEL12_SEL24_SHIFT (0U) #define XBARA_SEL12_SEL24(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL12_SEL24_SHIFT)) & XBARA_SEL12_SEL24_MASK) #define XBARA_SEL12_SEL25_MASK (0x7F00U) #define XBARA_SEL12_SEL25_SHIFT (8U) #define XBARA_SEL12_SEL25(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL12_SEL25_SHIFT)) & XBARA_SEL12_SEL25_MASK) +/*! @} */ /*! @name SEL13 - Crossbar A Select Register 13 */ +/*! @{ */ #define XBARA_SEL13_SEL26_MASK (0x7FU) #define XBARA_SEL13_SEL26_SHIFT (0U) #define XBARA_SEL13_SEL26(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL13_SEL26_SHIFT)) & XBARA_SEL13_SEL26_MASK) #define XBARA_SEL13_SEL27_MASK (0x7F00U) #define XBARA_SEL13_SEL27_SHIFT (8U) #define XBARA_SEL13_SEL27(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL13_SEL27_SHIFT)) & XBARA_SEL13_SEL27_MASK) +/*! @} */ /*! @name SEL14 - Crossbar A Select Register 14 */ +/*! @{ */ #define XBARA_SEL14_SEL28_MASK (0x7FU) #define XBARA_SEL14_SEL28_SHIFT (0U) #define XBARA_SEL14_SEL28(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL14_SEL28_SHIFT)) & XBARA_SEL14_SEL28_MASK) #define XBARA_SEL14_SEL29_MASK (0x7F00U) #define XBARA_SEL14_SEL29_SHIFT (8U) #define XBARA_SEL14_SEL29(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL14_SEL29_SHIFT)) & XBARA_SEL14_SEL29_MASK) +/*! @} */ /*! @name SEL15 - Crossbar A Select Register 15 */ +/*! @{ */ #define XBARA_SEL15_SEL30_MASK (0x7FU) #define XBARA_SEL15_SEL30_SHIFT (0U) #define XBARA_SEL15_SEL30(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL15_SEL30_SHIFT)) & XBARA_SEL15_SEL30_MASK) #define XBARA_SEL15_SEL31_MASK (0x7F00U) #define XBARA_SEL15_SEL31_SHIFT (8U) #define XBARA_SEL15_SEL31(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL15_SEL31_SHIFT)) & XBARA_SEL15_SEL31_MASK) +/*! @} */ /*! @name SEL16 - Crossbar A Select Register 16 */ +/*! @{ */ #define XBARA_SEL16_SEL32_MASK (0x7FU) #define XBARA_SEL16_SEL32_SHIFT (0U) #define XBARA_SEL16_SEL32(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL16_SEL32_SHIFT)) & XBARA_SEL16_SEL32_MASK) #define XBARA_SEL16_SEL33_MASK (0x7F00U) #define XBARA_SEL16_SEL33_SHIFT (8U) #define XBARA_SEL16_SEL33(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL16_SEL33_SHIFT)) & XBARA_SEL16_SEL33_MASK) +/*! @} */ /*! @name SEL17 - Crossbar A Select Register 17 */ +/*! @{ */ #define XBARA_SEL17_SEL34_MASK (0x7FU) #define XBARA_SEL17_SEL34_SHIFT (0U) #define XBARA_SEL17_SEL34(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL17_SEL34_SHIFT)) & XBARA_SEL17_SEL34_MASK) #define XBARA_SEL17_SEL35_MASK (0x7F00U) #define XBARA_SEL17_SEL35_SHIFT (8U) #define XBARA_SEL17_SEL35(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL17_SEL35_SHIFT)) & XBARA_SEL17_SEL35_MASK) +/*! @} */ /*! @name SEL18 - Crossbar A Select Register 18 */ +/*! @{ */ #define XBARA_SEL18_SEL36_MASK (0x7FU) #define XBARA_SEL18_SEL36_SHIFT (0U) #define XBARA_SEL18_SEL36(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL18_SEL36_SHIFT)) & XBARA_SEL18_SEL36_MASK) #define XBARA_SEL18_SEL37_MASK (0x7F00U) #define XBARA_SEL18_SEL37_SHIFT (8U) #define XBARA_SEL18_SEL37(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL18_SEL37_SHIFT)) & XBARA_SEL18_SEL37_MASK) +/*! @} */ /*! @name SEL19 - Crossbar A Select Register 19 */ +/*! @{ */ #define XBARA_SEL19_SEL38_MASK (0x7FU) #define XBARA_SEL19_SEL38_SHIFT (0U) #define XBARA_SEL19_SEL38(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL19_SEL38_SHIFT)) & XBARA_SEL19_SEL38_MASK) #define XBARA_SEL19_SEL39_MASK (0x7F00U) #define XBARA_SEL19_SEL39_SHIFT (8U) #define XBARA_SEL19_SEL39(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL19_SEL39_SHIFT)) & XBARA_SEL19_SEL39_MASK) +/*! @} */ /*! @name SEL20 - Crossbar A Select Register 20 */ +/*! @{ */ #define XBARA_SEL20_SEL40_MASK (0x7FU) #define XBARA_SEL20_SEL40_SHIFT (0U) #define XBARA_SEL20_SEL40(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL20_SEL40_SHIFT)) & XBARA_SEL20_SEL40_MASK) #define XBARA_SEL20_SEL41_MASK (0x7F00U) #define XBARA_SEL20_SEL41_SHIFT (8U) #define XBARA_SEL20_SEL41(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL20_SEL41_SHIFT)) & XBARA_SEL20_SEL41_MASK) +/*! @} */ /*! @name SEL21 - Crossbar A Select Register 21 */ +/*! @{ */ #define XBARA_SEL21_SEL42_MASK (0x7FU) #define XBARA_SEL21_SEL42_SHIFT (0U) #define XBARA_SEL21_SEL42(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL21_SEL42_SHIFT)) & XBARA_SEL21_SEL42_MASK) #define XBARA_SEL21_SEL43_MASK (0x7F00U) #define XBARA_SEL21_SEL43_SHIFT (8U) #define XBARA_SEL21_SEL43(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL21_SEL43_SHIFT)) & XBARA_SEL21_SEL43_MASK) +/*! @} */ /*! @name SEL22 - Crossbar A Select Register 22 */ +/*! @{ */ #define XBARA_SEL22_SEL44_MASK (0x7FU) #define XBARA_SEL22_SEL44_SHIFT (0U) #define XBARA_SEL22_SEL44(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL22_SEL44_SHIFT)) & XBARA_SEL22_SEL44_MASK) #define XBARA_SEL22_SEL45_MASK (0x7F00U) #define XBARA_SEL22_SEL45_SHIFT (8U) #define XBARA_SEL22_SEL45(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL22_SEL45_SHIFT)) & XBARA_SEL22_SEL45_MASK) +/*! @} */ /*! @name SEL23 - Crossbar A Select Register 23 */ +/*! @{ */ #define XBARA_SEL23_SEL46_MASK (0x7FU) #define XBARA_SEL23_SEL46_SHIFT (0U) #define XBARA_SEL23_SEL46(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL23_SEL46_SHIFT)) & XBARA_SEL23_SEL46_MASK) #define XBARA_SEL23_SEL47_MASK (0x7F00U) #define XBARA_SEL23_SEL47_SHIFT (8U) #define XBARA_SEL23_SEL47(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL23_SEL47_SHIFT)) & XBARA_SEL23_SEL47_MASK) +/*! @} */ /*! @name SEL24 - Crossbar A Select Register 24 */ +/*! @{ */ #define XBARA_SEL24_SEL48_MASK (0x7FU) #define XBARA_SEL24_SEL48_SHIFT (0U) #define XBARA_SEL24_SEL48(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL24_SEL48_SHIFT)) & XBARA_SEL24_SEL48_MASK) #define XBARA_SEL24_SEL49_MASK (0x7F00U) #define XBARA_SEL24_SEL49_SHIFT (8U) #define XBARA_SEL24_SEL49(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL24_SEL49_SHIFT)) & XBARA_SEL24_SEL49_MASK) +/*! @} */ /*! @name SEL25 - Crossbar A Select Register 25 */ +/*! @{ */ #define XBARA_SEL25_SEL50_MASK (0x7FU) #define XBARA_SEL25_SEL50_SHIFT (0U) #define XBARA_SEL25_SEL50(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL25_SEL50_SHIFT)) & XBARA_SEL25_SEL50_MASK) #define XBARA_SEL25_SEL51_MASK (0x7F00U) #define XBARA_SEL25_SEL51_SHIFT (8U) #define XBARA_SEL25_SEL51(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL25_SEL51_SHIFT)) & XBARA_SEL25_SEL51_MASK) +/*! @} */ /*! @name SEL26 - Crossbar A Select Register 26 */ +/*! @{ */ #define XBARA_SEL26_SEL52_MASK (0x7FU) #define XBARA_SEL26_SEL52_SHIFT (0U) #define XBARA_SEL26_SEL52(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL26_SEL52_SHIFT)) & XBARA_SEL26_SEL52_MASK) #define XBARA_SEL26_SEL53_MASK (0x7F00U) #define XBARA_SEL26_SEL53_SHIFT (8U) #define XBARA_SEL26_SEL53(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL26_SEL53_SHIFT)) & XBARA_SEL26_SEL53_MASK) +/*! @} */ /*! @name SEL27 - Crossbar A Select Register 27 */ +/*! @{ */ #define XBARA_SEL27_SEL54_MASK (0x7FU) #define XBARA_SEL27_SEL54_SHIFT (0U) #define XBARA_SEL27_SEL54(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL27_SEL54_SHIFT)) & XBARA_SEL27_SEL54_MASK) #define XBARA_SEL27_SEL55_MASK (0x7F00U) #define XBARA_SEL27_SEL55_SHIFT (8U) #define XBARA_SEL27_SEL55(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL27_SEL55_SHIFT)) & XBARA_SEL27_SEL55_MASK) +/*! @} */ /*! @name SEL28 - Crossbar A Select Register 28 */ +/*! @{ */ #define XBARA_SEL28_SEL56_MASK (0x7FU) #define XBARA_SEL28_SEL56_SHIFT (0U) #define XBARA_SEL28_SEL56(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL28_SEL56_SHIFT)) & XBARA_SEL28_SEL56_MASK) #define XBARA_SEL28_SEL57_MASK (0x7F00U) #define XBARA_SEL28_SEL57_SHIFT (8U) #define XBARA_SEL28_SEL57(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL28_SEL57_SHIFT)) & XBARA_SEL28_SEL57_MASK) +/*! @} */ /*! @name SEL29 - Crossbar A Select Register 29 */ +/*! @{ */ #define XBARA_SEL29_SEL58_MASK (0x7FU) #define XBARA_SEL29_SEL58_SHIFT (0U) #define XBARA_SEL29_SEL58(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL29_SEL58_SHIFT)) & XBARA_SEL29_SEL58_MASK) #define XBARA_SEL29_SEL59_MASK (0x7F00U) #define XBARA_SEL29_SEL59_SHIFT (8U) #define XBARA_SEL29_SEL59(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL29_SEL59_SHIFT)) & XBARA_SEL29_SEL59_MASK) +/*! @} */ /*! @name SEL30 - Crossbar A Select Register 30 */ +/*! @{ */ #define XBARA_SEL30_SEL60_MASK (0x7FU) #define XBARA_SEL30_SEL60_SHIFT (0U) #define XBARA_SEL30_SEL60(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL30_SEL60_SHIFT)) & XBARA_SEL30_SEL60_MASK) #define XBARA_SEL30_SEL61_MASK (0x7F00U) #define XBARA_SEL30_SEL61_SHIFT (8U) #define XBARA_SEL30_SEL61(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL30_SEL61_SHIFT)) & XBARA_SEL30_SEL61_MASK) +/*! @} */ /*! @name SEL31 - Crossbar A Select Register 31 */ +/*! @{ */ #define XBARA_SEL31_SEL62_MASK (0x7FU) #define XBARA_SEL31_SEL62_SHIFT (0U) #define XBARA_SEL31_SEL62(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL31_SEL62_SHIFT)) & XBARA_SEL31_SEL62_MASK) #define XBARA_SEL31_SEL63_MASK (0x7F00U) #define XBARA_SEL31_SEL63_SHIFT (8U) #define XBARA_SEL31_SEL63(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL31_SEL63_SHIFT)) & XBARA_SEL31_SEL63_MASK) +/*! @} */ /*! @name SEL32 - Crossbar A Select Register 32 */ +/*! @{ */ #define XBARA_SEL32_SEL64_MASK (0x7FU) #define XBARA_SEL32_SEL64_SHIFT (0U) #define XBARA_SEL32_SEL64(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL32_SEL64_SHIFT)) & XBARA_SEL32_SEL64_MASK) #define XBARA_SEL32_SEL65_MASK (0x7F00U) #define XBARA_SEL32_SEL65_SHIFT (8U) #define XBARA_SEL32_SEL65(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL32_SEL65_SHIFT)) & XBARA_SEL32_SEL65_MASK) +/*! @} */ /*! @name SEL33 - Crossbar A Select Register 33 */ +/*! @{ */ #define XBARA_SEL33_SEL66_MASK (0x7FU) #define XBARA_SEL33_SEL66_SHIFT (0U) #define XBARA_SEL33_SEL66(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL33_SEL66_SHIFT)) & XBARA_SEL33_SEL66_MASK) #define XBARA_SEL33_SEL67_MASK (0x7F00U) #define XBARA_SEL33_SEL67_SHIFT (8U) #define XBARA_SEL33_SEL67(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL33_SEL67_SHIFT)) & XBARA_SEL33_SEL67_MASK) +/*! @} */ /*! @name SEL34 - Crossbar A Select Register 34 */ +/*! @{ */ #define XBARA_SEL34_SEL68_MASK (0x7FU) #define XBARA_SEL34_SEL68_SHIFT (0U) #define XBARA_SEL34_SEL68(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL34_SEL68_SHIFT)) & XBARA_SEL34_SEL68_MASK) #define XBARA_SEL34_SEL69_MASK (0x7F00U) #define XBARA_SEL34_SEL69_SHIFT (8U) #define XBARA_SEL34_SEL69(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL34_SEL69_SHIFT)) & XBARA_SEL34_SEL69_MASK) +/*! @} */ /*! @name SEL35 - Crossbar A Select Register 35 */ +/*! @{ */ #define XBARA_SEL35_SEL70_MASK (0x7FU) #define XBARA_SEL35_SEL70_SHIFT (0U) #define XBARA_SEL35_SEL70(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL35_SEL70_SHIFT)) & XBARA_SEL35_SEL70_MASK) #define XBARA_SEL35_SEL71_MASK (0x7F00U) #define XBARA_SEL35_SEL71_SHIFT (8U) #define XBARA_SEL35_SEL71(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL35_SEL71_SHIFT)) & XBARA_SEL35_SEL71_MASK) +/*! @} */ /*! @name SEL36 - Crossbar A Select Register 36 */ +/*! @{ */ #define XBARA_SEL36_SEL72_MASK (0x7FU) #define XBARA_SEL36_SEL72_SHIFT (0U) #define XBARA_SEL36_SEL72(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL36_SEL72_SHIFT)) & XBARA_SEL36_SEL72_MASK) #define XBARA_SEL36_SEL73_MASK (0x7F00U) #define XBARA_SEL36_SEL73_SHIFT (8U) #define XBARA_SEL36_SEL73(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL36_SEL73_SHIFT)) & XBARA_SEL36_SEL73_MASK) +/*! @} */ /*! @name SEL37 - Crossbar A Select Register 37 */ +/*! @{ */ #define XBARA_SEL37_SEL74_MASK (0x7FU) #define XBARA_SEL37_SEL74_SHIFT (0U) #define XBARA_SEL37_SEL74(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL37_SEL74_SHIFT)) & XBARA_SEL37_SEL74_MASK) #define XBARA_SEL37_SEL75_MASK (0x7F00U) #define XBARA_SEL37_SEL75_SHIFT (8U) #define XBARA_SEL37_SEL75(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL37_SEL75_SHIFT)) & XBARA_SEL37_SEL75_MASK) +/*! @} */ /*! @name SEL38 - Crossbar A Select Register 38 */ +/*! @{ */ #define XBARA_SEL38_SEL76_MASK (0x7FU) #define XBARA_SEL38_SEL76_SHIFT (0U) #define XBARA_SEL38_SEL76(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL38_SEL76_SHIFT)) & XBARA_SEL38_SEL76_MASK) #define XBARA_SEL38_SEL77_MASK (0x7F00U) #define XBARA_SEL38_SEL77_SHIFT (8U) #define XBARA_SEL38_SEL77(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL38_SEL77_SHIFT)) & XBARA_SEL38_SEL77_MASK) +/*! @} */ /*! @name SEL39 - Crossbar A Select Register 39 */ +/*! @{ */ #define XBARA_SEL39_SEL78_MASK (0x7FU) #define XBARA_SEL39_SEL78_SHIFT (0U) #define XBARA_SEL39_SEL78(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL39_SEL78_SHIFT)) & XBARA_SEL39_SEL78_MASK) #define XBARA_SEL39_SEL79_MASK (0x7F00U) #define XBARA_SEL39_SEL79_SHIFT (8U) #define XBARA_SEL39_SEL79(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL39_SEL79_SHIFT)) & XBARA_SEL39_SEL79_MASK) +/*! @} */ /*! @name SEL40 - Crossbar A Select Register 40 */ +/*! @{ */ #define XBARA_SEL40_SEL80_MASK (0x7FU) #define XBARA_SEL40_SEL80_SHIFT (0U) #define XBARA_SEL40_SEL80(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL40_SEL80_SHIFT)) & XBARA_SEL40_SEL80_MASK) #define XBARA_SEL40_SEL81_MASK (0x7F00U) #define XBARA_SEL40_SEL81_SHIFT (8U) #define XBARA_SEL40_SEL81(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL40_SEL81_SHIFT)) & XBARA_SEL40_SEL81_MASK) +/*! @} */ /*! @name SEL41 - Crossbar A Select Register 41 */ +/*! @{ */ #define XBARA_SEL41_SEL82_MASK (0x7FU) #define XBARA_SEL41_SEL82_SHIFT (0U) #define XBARA_SEL41_SEL82(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL41_SEL82_SHIFT)) & XBARA_SEL41_SEL82_MASK) #define XBARA_SEL41_SEL83_MASK (0x7F00U) #define XBARA_SEL41_SEL83_SHIFT (8U) #define XBARA_SEL41_SEL83(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL41_SEL83_SHIFT)) & XBARA_SEL41_SEL83_MASK) +/*! @} */ /*! @name SEL42 - Crossbar A Select Register 42 */ +/*! @{ */ #define XBARA_SEL42_SEL84_MASK (0x7FU) #define XBARA_SEL42_SEL84_SHIFT (0U) #define XBARA_SEL42_SEL84(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL42_SEL84_SHIFT)) & XBARA_SEL42_SEL84_MASK) #define XBARA_SEL42_SEL85_MASK (0x7F00U) #define XBARA_SEL42_SEL85_SHIFT (8U) #define XBARA_SEL42_SEL85(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL42_SEL85_SHIFT)) & XBARA_SEL42_SEL85_MASK) +/*! @} */ /*! @name SEL43 - Crossbar A Select Register 43 */ +/*! @{ */ #define XBARA_SEL43_SEL86_MASK (0x7FU) #define XBARA_SEL43_SEL86_SHIFT (0U) #define XBARA_SEL43_SEL86(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL43_SEL86_SHIFT)) & XBARA_SEL43_SEL86_MASK) #define XBARA_SEL43_SEL87_MASK (0x7F00U) #define XBARA_SEL43_SEL87_SHIFT (8U) #define XBARA_SEL43_SEL87(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL43_SEL87_SHIFT)) & XBARA_SEL43_SEL87_MASK) +/*! @} */ /*! @name SEL44 - Crossbar A Select Register 44 */ +/*! @{ */ #define XBARA_SEL44_SEL88_MASK (0x7FU) #define XBARA_SEL44_SEL88_SHIFT (0U) #define XBARA_SEL44_SEL88(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL44_SEL88_SHIFT)) & XBARA_SEL44_SEL88_MASK) #define XBARA_SEL44_SEL89_MASK (0x7F00U) #define XBARA_SEL44_SEL89_SHIFT (8U) #define XBARA_SEL44_SEL89(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL44_SEL89_SHIFT)) & XBARA_SEL44_SEL89_MASK) +/*! @} */ /*! @name SEL45 - Crossbar A Select Register 45 */ +/*! @{ */ #define XBARA_SEL45_SEL90_MASK (0x7FU) #define XBARA_SEL45_SEL90_SHIFT (0U) #define XBARA_SEL45_SEL90(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL45_SEL90_SHIFT)) & XBARA_SEL45_SEL90_MASK) #define XBARA_SEL45_SEL91_MASK (0x7F00U) #define XBARA_SEL45_SEL91_SHIFT (8U) #define XBARA_SEL45_SEL91(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL45_SEL91_SHIFT)) & XBARA_SEL45_SEL91_MASK) +/*! @} */ /*! @name SEL46 - Crossbar A Select Register 46 */ +/*! @{ */ #define XBARA_SEL46_SEL92_MASK (0x7FU) #define XBARA_SEL46_SEL92_SHIFT (0U) #define XBARA_SEL46_SEL92(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL46_SEL92_SHIFT)) & XBARA_SEL46_SEL92_MASK) #define XBARA_SEL46_SEL93_MASK (0x7F00U) #define XBARA_SEL46_SEL93_SHIFT (8U) #define XBARA_SEL46_SEL93(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL46_SEL93_SHIFT)) & XBARA_SEL46_SEL93_MASK) +/*! @} */ /*! @name SEL47 - Crossbar A Select Register 47 */ +/*! @{ */ #define XBARA_SEL47_SEL94_MASK (0x7FU) #define XBARA_SEL47_SEL94_SHIFT (0U) #define XBARA_SEL47_SEL94(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL47_SEL94_SHIFT)) & XBARA_SEL47_SEL94_MASK) #define XBARA_SEL47_SEL95_MASK (0x7F00U) #define XBARA_SEL47_SEL95_SHIFT (8U) #define XBARA_SEL47_SEL95(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL47_SEL95_SHIFT)) & XBARA_SEL47_SEL95_MASK) +/*! @} */ /*! @name SEL48 - Crossbar A Select Register 48 */ +/*! @{ */ #define XBARA_SEL48_SEL96_MASK (0x7FU) #define XBARA_SEL48_SEL96_SHIFT (0U) #define XBARA_SEL48_SEL96(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL48_SEL96_SHIFT)) & XBARA_SEL48_SEL96_MASK) #define XBARA_SEL48_SEL97_MASK (0x7F00U) #define XBARA_SEL48_SEL97_SHIFT (8U) #define XBARA_SEL48_SEL97(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL48_SEL97_SHIFT)) & XBARA_SEL48_SEL97_MASK) +/*! @} */ /*! @name SEL49 - Crossbar A Select Register 49 */ +/*! @{ */ #define XBARA_SEL49_SEL98_MASK (0x7FU) #define XBARA_SEL49_SEL98_SHIFT (0U) #define XBARA_SEL49_SEL98(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL49_SEL98_SHIFT)) & XBARA_SEL49_SEL98_MASK) #define XBARA_SEL49_SEL99_MASK (0x7F00U) #define XBARA_SEL49_SEL99_SHIFT (8U) #define XBARA_SEL49_SEL99(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL49_SEL99_SHIFT)) & XBARA_SEL49_SEL99_MASK) +/*! @} */ /*! @name SEL50 - Crossbar A Select Register 50 */ +/*! @{ */ #define XBARA_SEL50_SEL100_MASK (0x7FU) #define XBARA_SEL50_SEL100_SHIFT (0U) #define XBARA_SEL50_SEL100(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL50_SEL100_SHIFT)) & XBARA_SEL50_SEL100_MASK) #define XBARA_SEL50_SEL101_MASK (0x7F00U) #define XBARA_SEL50_SEL101_SHIFT (8U) #define XBARA_SEL50_SEL101(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL50_SEL101_SHIFT)) & XBARA_SEL50_SEL101_MASK) +/*! @} */ /*! @name SEL51 - Crossbar A Select Register 51 */ +/*! @{ */ #define XBARA_SEL51_SEL102_MASK (0x7FU) #define XBARA_SEL51_SEL102_SHIFT (0U) #define XBARA_SEL51_SEL102(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL51_SEL102_SHIFT)) & XBARA_SEL51_SEL102_MASK) #define XBARA_SEL51_SEL103_MASK (0x7F00U) #define XBARA_SEL51_SEL103_SHIFT (8U) #define XBARA_SEL51_SEL103(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL51_SEL103_SHIFT)) & XBARA_SEL51_SEL103_MASK) +/*! @} */ /*! @name SEL52 - Crossbar A Select Register 52 */ +/*! @{ */ #define XBARA_SEL52_SEL104_MASK (0x7FU) #define XBARA_SEL52_SEL104_SHIFT (0U) #define XBARA_SEL52_SEL104(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL52_SEL104_SHIFT)) & XBARA_SEL52_SEL104_MASK) #define XBARA_SEL52_SEL105_MASK (0x7F00U) #define XBARA_SEL52_SEL105_SHIFT (8U) #define XBARA_SEL52_SEL105(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL52_SEL105_SHIFT)) & XBARA_SEL52_SEL105_MASK) +/*! @} */ /*! @name SEL53 - Crossbar A Select Register 53 */ +/*! @{ */ #define XBARA_SEL53_SEL106_MASK (0x7FU) #define XBARA_SEL53_SEL106_SHIFT (0U) #define XBARA_SEL53_SEL106(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL53_SEL106_SHIFT)) & XBARA_SEL53_SEL106_MASK) #define XBARA_SEL53_SEL107_MASK (0x7F00U) #define XBARA_SEL53_SEL107_SHIFT (8U) #define XBARA_SEL53_SEL107(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL53_SEL107_SHIFT)) & XBARA_SEL53_SEL107_MASK) +/*! @} */ /*! @name SEL54 - Crossbar A Select Register 54 */ +/*! @{ */ #define XBARA_SEL54_SEL108_MASK (0x7FU) #define XBARA_SEL54_SEL108_SHIFT (0U) #define XBARA_SEL54_SEL108(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL54_SEL108_SHIFT)) & XBARA_SEL54_SEL108_MASK) #define XBARA_SEL54_SEL109_MASK (0x7F00U) #define XBARA_SEL54_SEL109_SHIFT (8U) #define XBARA_SEL54_SEL109(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL54_SEL109_SHIFT)) & XBARA_SEL54_SEL109_MASK) +/*! @} */ /*! @name SEL55 - Crossbar A Select Register 55 */ +/*! @{ */ #define XBARA_SEL55_SEL110_MASK (0x7FU) #define XBARA_SEL55_SEL110_SHIFT (0U) #define XBARA_SEL55_SEL110(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL55_SEL110_SHIFT)) & XBARA_SEL55_SEL110_MASK) #define XBARA_SEL55_SEL111_MASK (0x7F00U) #define XBARA_SEL55_SEL111_SHIFT (8U) #define XBARA_SEL55_SEL111(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL55_SEL111_SHIFT)) & XBARA_SEL55_SEL111_MASK) +/*! @} */ /*! @name SEL56 - Crossbar A Select Register 56 */ +/*! @{ */ #define XBARA_SEL56_SEL112_MASK (0x7FU) #define XBARA_SEL56_SEL112_SHIFT (0U) #define XBARA_SEL56_SEL112(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL56_SEL112_SHIFT)) & XBARA_SEL56_SEL112_MASK) #define XBARA_SEL56_SEL113_MASK (0x7F00U) #define XBARA_SEL56_SEL113_SHIFT (8U) #define XBARA_SEL56_SEL113(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL56_SEL113_SHIFT)) & XBARA_SEL56_SEL113_MASK) +/*! @} */ /*! @name SEL57 - Crossbar A Select Register 57 */ +/*! @{ */ #define XBARA_SEL57_SEL114_MASK (0x7FU) #define XBARA_SEL57_SEL114_SHIFT (0U) #define XBARA_SEL57_SEL114(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL57_SEL114_SHIFT)) & XBARA_SEL57_SEL114_MASK) #define XBARA_SEL57_SEL115_MASK (0x7F00U) #define XBARA_SEL57_SEL115_SHIFT (8U) #define XBARA_SEL57_SEL115(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL57_SEL115_SHIFT)) & XBARA_SEL57_SEL115_MASK) +/*! @} */ /*! @name SEL58 - Crossbar A Select Register 58 */ +/*! @{ */ #define XBARA_SEL58_SEL116_MASK (0x7FU) #define XBARA_SEL58_SEL116_SHIFT (0U) #define XBARA_SEL58_SEL116(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL58_SEL116_SHIFT)) & XBARA_SEL58_SEL116_MASK) #define XBARA_SEL58_SEL117_MASK (0x7F00U) #define XBARA_SEL58_SEL117_SHIFT (8U) #define XBARA_SEL58_SEL117(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL58_SEL117_SHIFT)) & XBARA_SEL58_SEL117_MASK) +/*! @} */ /*! @name SEL59 - Crossbar A Select Register 59 */ +/*! @{ */ #define XBARA_SEL59_SEL118_MASK (0x7FU) #define XBARA_SEL59_SEL118_SHIFT (0U) #define XBARA_SEL59_SEL118(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL59_SEL118_SHIFT)) & XBARA_SEL59_SEL118_MASK) #define XBARA_SEL59_SEL119_MASK (0x7F00U) #define XBARA_SEL59_SEL119_SHIFT (8U) #define XBARA_SEL59_SEL119(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL59_SEL119_SHIFT)) & XBARA_SEL59_SEL119_MASK) +/*! @} */ /*! @name SEL60 - Crossbar A Select Register 60 */ +/*! @{ */ #define XBARA_SEL60_SEL120_MASK (0x7FU) #define XBARA_SEL60_SEL120_SHIFT (0U) #define XBARA_SEL60_SEL120(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL60_SEL120_SHIFT)) & XBARA_SEL60_SEL120_MASK) #define XBARA_SEL60_SEL121_MASK (0x7F00U) #define XBARA_SEL60_SEL121_SHIFT (8U) #define XBARA_SEL60_SEL121(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL60_SEL121_SHIFT)) & XBARA_SEL60_SEL121_MASK) +/*! @} */ /*! @name SEL61 - Crossbar A Select Register 61 */ +/*! @{ */ #define XBARA_SEL61_SEL122_MASK (0x7FU) #define XBARA_SEL61_SEL122_SHIFT (0U) #define XBARA_SEL61_SEL122(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL61_SEL122_SHIFT)) & XBARA_SEL61_SEL122_MASK) #define XBARA_SEL61_SEL123_MASK (0x7F00U) #define XBARA_SEL61_SEL123_SHIFT (8U) #define XBARA_SEL61_SEL123(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL61_SEL123_SHIFT)) & XBARA_SEL61_SEL123_MASK) +/*! @} */ /*! @name SEL62 - Crossbar A Select Register 62 */ +/*! @{ */ #define XBARA_SEL62_SEL124_MASK (0x7FU) #define XBARA_SEL62_SEL124_SHIFT (0U) #define XBARA_SEL62_SEL124(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL62_SEL124_SHIFT)) & XBARA_SEL62_SEL124_MASK) #define XBARA_SEL62_SEL125_MASK (0x7F00U) #define XBARA_SEL62_SEL125_SHIFT (8U) #define XBARA_SEL62_SEL125(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL62_SEL125_SHIFT)) & XBARA_SEL62_SEL125_MASK) +/*! @} */ /*! @name SEL63 - Crossbar A Select Register 63 */ +/*! @{ */ #define XBARA_SEL63_SEL126_MASK (0x7FU) #define XBARA_SEL63_SEL126_SHIFT (0U) #define XBARA_SEL63_SEL126(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL63_SEL126_SHIFT)) & XBARA_SEL63_SEL126_MASK) #define XBARA_SEL63_SEL127_MASK (0x7F00U) #define XBARA_SEL63_SEL127_SHIFT (8U) #define XBARA_SEL63_SEL127(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL63_SEL127_SHIFT)) & XBARA_SEL63_SEL127_MASK) +/*! @} */ /*! @name SEL64 - Crossbar A Select Register 64 */ +/*! @{ */ #define XBARA_SEL64_SEL128_MASK (0x7FU) #define XBARA_SEL64_SEL128_SHIFT (0U) #define XBARA_SEL64_SEL128(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL64_SEL128_SHIFT)) & XBARA_SEL64_SEL128_MASK) #define XBARA_SEL64_SEL129_MASK (0x7F00U) #define XBARA_SEL64_SEL129_SHIFT (8U) #define XBARA_SEL64_SEL129(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL64_SEL129_SHIFT)) & XBARA_SEL64_SEL129_MASK) +/*! @} */ /*! @name SEL65 - Crossbar A Select Register 65 */ +/*! @{ */ #define XBARA_SEL65_SEL130_MASK (0x7FU) #define XBARA_SEL65_SEL130_SHIFT (0U) #define XBARA_SEL65_SEL130(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL65_SEL130_SHIFT)) & XBARA_SEL65_SEL130_MASK) #define XBARA_SEL65_SEL131_MASK (0x7F00U) #define XBARA_SEL65_SEL131_SHIFT (8U) #define XBARA_SEL65_SEL131(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL65_SEL131_SHIFT)) & XBARA_SEL65_SEL131_MASK) +/*! @} */ /*! @name CTRL0 - Crossbar A Control Register 0 */ +/*! @{ */ #define XBARA_CTRL0_DEN0_MASK (0x1U) #define XBARA_CTRL0_DEN0_SHIFT (0U) +/*! DEN0 - DMA Enable for XBAR_OUT0 + * 0b0..DMA disabled + * 0b1..DMA enabled + */ #define XBARA_CTRL0_DEN0(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_DEN0_SHIFT)) & XBARA_CTRL0_DEN0_MASK) #define XBARA_CTRL0_IEN0_MASK (0x2U) #define XBARA_CTRL0_IEN0_SHIFT (1U) +/*! IEN0 - Interrupt Enable for XBAR_OUT0 + * 0b0..Interrupt disabled + * 0b1..Interrupt enabled + */ #define XBARA_CTRL0_IEN0(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_IEN0_SHIFT)) & XBARA_CTRL0_IEN0_MASK) #define XBARA_CTRL0_EDGE0_MASK (0xCU) #define XBARA_CTRL0_EDGE0_SHIFT (2U) +/*! EDGE0 - Active edge for edge detection on XBAR_OUT0 + * 0b00..STS0 never asserts + * 0b01..STS0 asserts on rising edges of XBAR_OUT0 + * 0b10..STS0 asserts on falling edges of XBAR_OUT0 + * 0b11..STS0 asserts on rising and falling edges of XBAR_OUT0 + */ #define XBARA_CTRL0_EDGE0(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_EDGE0_SHIFT)) & XBARA_CTRL0_EDGE0_MASK) #define XBARA_CTRL0_STS0_MASK (0x10U) #define XBARA_CTRL0_STS0_SHIFT (4U) +/*! STS0 - Edge detection status for XBAR_OUT0 + * 0b0..Active edge not yet detected on XBAR_OUT0 + * 0b1..Active edge detected on XBAR_OUT0 + */ #define XBARA_CTRL0_STS0(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_STS0_SHIFT)) & XBARA_CTRL0_STS0_MASK) #define XBARA_CTRL0_DEN1_MASK (0x100U) #define XBARA_CTRL0_DEN1_SHIFT (8U) +/*! DEN1 - DMA Enable for XBAR_OUT1 + * 0b0..DMA disabled + * 0b1..DMA enabled + */ #define XBARA_CTRL0_DEN1(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_DEN1_SHIFT)) & XBARA_CTRL0_DEN1_MASK) #define XBARA_CTRL0_IEN1_MASK (0x200U) #define XBARA_CTRL0_IEN1_SHIFT (9U) +/*! IEN1 - Interrupt Enable for XBAR_OUT1 + * 0b0..Interrupt disabled + * 0b1..Interrupt enabled + */ #define XBARA_CTRL0_IEN1(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_IEN1_SHIFT)) & XBARA_CTRL0_IEN1_MASK) #define XBARA_CTRL0_EDGE1_MASK (0xC00U) #define XBARA_CTRL0_EDGE1_SHIFT (10U) +/*! EDGE1 - Active edge for edge detection on XBAR_OUT1 + * 0b00..STS1 never asserts + * 0b01..STS1 asserts on rising edges of XBAR_OUT1 + * 0b10..STS1 asserts on falling edges of XBAR_OUT1 + * 0b11..STS1 asserts on rising and falling edges of XBAR_OUT1 + */ #define XBARA_CTRL0_EDGE1(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_EDGE1_SHIFT)) & XBARA_CTRL0_EDGE1_MASK) #define XBARA_CTRL0_STS1_MASK (0x1000U) #define XBARA_CTRL0_STS1_SHIFT (12U) +/*! STS1 - Edge detection status for XBAR_OUT1 + * 0b0..Active edge not yet detected on XBAR_OUT1 + * 0b1..Active edge detected on XBAR_OUT1 + */ #define XBARA_CTRL0_STS1(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_STS1_SHIFT)) & XBARA_CTRL0_STS1_MASK) +/*! @} */ /*! @name CTRL1 - Crossbar A Control Register 1 */ +/*! @{ */ #define XBARA_CTRL1_DEN2_MASK (0x1U) #define XBARA_CTRL1_DEN2_SHIFT (0U) +/*! DEN2 - DMA Enable for XBAR_OUT2 + * 0b0..DMA disabled + * 0b1..DMA enabled + */ #define XBARA_CTRL1_DEN2(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_DEN2_SHIFT)) & XBARA_CTRL1_DEN2_MASK) #define XBARA_CTRL1_IEN2_MASK (0x2U) #define XBARA_CTRL1_IEN2_SHIFT (1U) +/*! IEN2 - Interrupt Enable for XBAR_OUT2 + * 0b0..Interrupt disabled + * 0b1..Interrupt enabled + */ #define XBARA_CTRL1_IEN2(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_IEN2_SHIFT)) & XBARA_CTRL1_IEN2_MASK) #define XBARA_CTRL1_EDGE2_MASK (0xCU) #define XBARA_CTRL1_EDGE2_SHIFT (2U) +/*! EDGE2 - Active edge for edge detection on XBAR_OUT2 + * 0b00..STS2 never asserts + * 0b01..STS2 asserts on rising edges of XBAR_OUT2 + * 0b10..STS2 asserts on falling edges of XBAR_OUT2 + * 0b11..STS2 asserts on rising and falling edges of XBAR_OUT2 + */ #define XBARA_CTRL1_EDGE2(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_EDGE2_SHIFT)) & XBARA_CTRL1_EDGE2_MASK) #define XBARA_CTRL1_STS2_MASK (0x10U) #define XBARA_CTRL1_STS2_SHIFT (4U) +/*! STS2 - Edge detection status for XBAR_OUT2 + * 0b0..Active edge not yet detected on XBAR_OUT2 + * 0b1..Active edge detected on XBAR_OUT2 + */ #define XBARA_CTRL1_STS2(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_STS2_SHIFT)) & XBARA_CTRL1_STS2_MASK) #define XBARA_CTRL1_DEN3_MASK (0x100U) #define XBARA_CTRL1_DEN3_SHIFT (8U) +/*! DEN3 - DMA Enable for XBAR_OUT3 + * 0b0..DMA disabled + * 0b1..DMA enabled + */ #define XBARA_CTRL1_DEN3(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_DEN3_SHIFT)) & XBARA_CTRL1_DEN3_MASK) #define XBARA_CTRL1_IEN3_MASK (0x200U) #define XBARA_CTRL1_IEN3_SHIFT (9U) +/*! IEN3 - Interrupt Enable for XBAR_OUT3 + * 0b0..Interrupt disabled + * 0b1..Interrupt enabled + */ #define XBARA_CTRL1_IEN3(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_IEN3_SHIFT)) & XBARA_CTRL1_IEN3_MASK) #define XBARA_CTRL1_EDGE3_MASK (0xC00U) #define XBARA_CTRL1_EDGE3_SHIFT (10U) +/*! EDGE3 - Active edge for edge detection on XBAR_OUT3 + * 0b00..STS3 never asserts + * 0b01..STS3 asserts on rising edges of XBAR_OUT3 + * 0b10..STS3 asserts on falling edges of XBAR_OUT3 + * 0b11..STS3 asserts on rising and falling edges of XBAR_OUT3 + */ #define XBARA_CTRL1_EDGE3(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_EDGE3_SHIFT)) & XBARA_CTRL1_EDGE3_MASK) #define XBARA_CTRL1_STS3_MASK (0x1000U) #define XBARA_CTRL1_STS3_SHIFT (12U) +/*! STS3 - Edge detection status for XBAR_OUT3 + * 0b0..Active edge not yet detected on XBAR_OUT3 + * 0b1..Active edge detected on XBAR_OUT3 + */ #define XBARA_CTRL1_STS3(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_STS3_SHIFT)) & XBARA_CTRL1_STS3_MASK) +/*! @} */ /*! @@ -26529,68 +41406,84 @@ typedef struct { */ /*! @name SEL0 - Crossbar B Select Register 0 */ +/*! @{ */ #define XBARB_SEL0_SEL0_MASK (0x3FU) #define XBARB_SEL0_SEL0_SHIFT (0U) #define XBARB_SEL0_SEL0(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL0_SEL0_SHIFT)) & XBARB_SEL0_SEL0_MASK) #define XBARB_SEL0_SEL1_MASK (0x3F00U) #define XBARB_SEL0_SEL1_SHIFT (8U) #define XBARB_SEL0_SEL1(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL0_SEL1_SHIFT)) & XBARB_SEL0_SEL1_MASK) +/*! @} */ /*! @name SEL1 - Crossbar B Select Register 1 */ +/*! @{ */ #define XBARB_SEL1_SEL2_MASK (0x3FU) #define XBARB_SEL1_SEL2_SHIFT (0U) #define XBARB_SEL1_SEL2(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL1_SEL2_SHIFT)) & XBARB_SEL1_SEL2_MASK) #define XBARB_SEL1_SEL3_MASK (0x3F00U) #define XBARB_SEL1_SEL3_SHIFT (8U) #define XBARB_SEL1_SEL3(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL1_SEL3_SHIFT)) & XBARB_SEL1_SEL3_MASK) +/*! @} */ /*! @name SEL2 - Crossbar B Select Register 2 */ +/*! @{ */ #define XBARB_SEL2_SEL4_MASK (0x3FU) #define XBARB_SEL2_SEL4_SHIFT (0U) #define XBARB_SEL2_SEL4(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL2_SEL4_SHIFT)) & XBARB_SEL2_SEL4_MASK) #define XBARB_SEL2_SEL5_MASK (0x3F00U) #define XBARB_SEL2_SEL5_SHIFT (8U) #define XBARB_SEL2_SEL5(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL2_SEL5_SHIFT)) & XBARB_SEL2_SEL5_MASK) +/*! @} */ /*! @name SEL3 - Crossbar B Select Register 3 */ +/*! @{ */ #define XBARB_SEL3_SEL6_MASK (0x3FU) #define XBARB_SEL3_SEL6_SHIFT (0U) #define XBARB_SEL3_SEL6(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL3_SEL6_SHIFT)) & XBARB_SEL3_SEL6_MASK) #define XBARB_SEL3_SEL7_MASK (0x3F00U) #define XBARB_SEL3_SEL7_SHIFT (8U) #define XBARB_SEL3_SEL7(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL3_SEL7_SHIFT)) & XBARB_SEL3_SEL7_MASK) +/*! @} */ /*! @name SEL4 - Crossbar B Select Register 4 */ +/*! @{ */ #define XBARB_SEL4_SEL8_MASK (0x3FU) #define XBARB_SEL4_SEL8_SHIFT (0U) #define XBARB_SEL4_SEL8(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL4_SEL8_SHIFT)) & XBARB_SEL4_SEL8_MASK) #define XBARB_SEL4_SEL9_MASK (0x3F00U) #define XBARB_SEL4_SEL9_SHIFT (8U) #define XBARB_SEL4_SEL9(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL4_SEL9_SHIFT)) & XBARB_SEL4_SEL9_MASK) +/*! @} */ /*! @name SEL5 - Crossbar B Select Register 5 */ +/*! @{ */ #define XBARB_SEL5_SEL10_MASK (0x3FU) #define XBARB_SEL5_SEL10_SHIFT (0U) #define XBARB_SEL5_SEL10(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL5_SEL10_SHIFT)) & XBARB_SEL5_SEL10_MASK) #define XBARB_SEL5_SEL11_MASK (0x3F00U) #define XBARB_SEL5_SEL11_SHIFT (8U) #define XBARB_SEL5_SEL11(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL5_SEL11_SHIFT)) & XBARB_SEL5_SEL11_MASK) +/*! @} */ /*! @name SEL6 - Crossbar B Select Register 6 */ +/*! @{ */ #define XBARB_SEL6_SEL12_MASK (0x3FU) #define XBARB_SEL6_SEL12_SHIFT (0U) #define XBARB_SEL6_SEL12(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL6_SEL12_SHIFT)) & XBARB_SEL6_SEL12_MASK) #define XBARB_SEL6_SEL13_MASK (0x3F00U) #define XBARB_SEL6_SEL13_SHIFT (8U) #define XBARB_SEL6_SEL13(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL6_SEL13_SHIFT)) & XBARB_SEL6_SEL13_MASK) +/*! @} */ /*! @name SEL7 - Crossbar B Select Register 7 */ +/*! @{ */ #define XBARB_SEL7_SEL14_MASK (0x3FU) #define XBARB_SEL7_SEL14_SHIFT (0U) #define XBARB_SEL7_SEL14(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL7_SEL14_SHIFT)) & XBARB_SEL7_SEL14_MASK) #define XBARB_SEL7_SEL15_MASK (0x3F00U) #define XBARB_SEL7_SEL15_SHIFT (8U) #define XBARB_SEL7_SEL15(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL7_SEL15_SHIFT)) & XBARB_SEL7_SEL15_MASK) +/*! @} */ /*! @@ -26663,26 +41556,57 @@ typedef struct { */ /*! @name MISC0 - Miscellaneous Register 0 */ +/*! @{ */ #define XTALOSC24M_MISC0_REFTOP_PWD_MASK (0x1U) #define XTALOSC24M_MISC0_REFTOP_PWD_SHIFT (0U) #define XTALOSC24M_MISC0_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_REFTOP_PWD_SHIFT)) & XTALOSC24M_MISC0_REFTOP_PWD_MASK) #define XTALOSC24M_MISC0_REFTOP_SELFBIASOFF_MASK (0x8U) #define XTALOSC24M_MISC0_REFTOP_SELFBIASOFF_SHIFT (3U) +/*! REFTOP_SELFBIASOFF + * 0b0..Uses coarse bias currents for startup + * 0b1..Uses bandgap-based bias currents for best performance. + */ #define XTALOSC24M_MISC0_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_REFTOP_SELFBIASOFF_SHIFT)) & XTALOSC24M_MISC0_REFTOP_SELFBIASOFF_MASK) #define XTALOSC24M_MISC0_REFTOP_VBGADJ_MASK (0x70U) #define XTALOSC24M_MISC0_REFTOP_VBGADJ_SHIFT (4U) +/*! REFTOP_VBGADJ + * 0b000..Nominal VBG + * 0b001..VBG+0.78% + * 0b010..VBG+1.56% + * 0b011..VBG+2.34% + * 0b100..VBG-0.78% + * 0b101..VBG-1.56% + * 0b110..VBG-2.34% + * 0b111..VBG-3.12% + */ #define XTALOSC24M_MISC0_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_REFTOP_VBGADJ_SHIFT)) & XTALOSC24M_MISC0_REFTOP_VBGADJ_MASK) #define XTALOSC24M_MISC0_REFTOP_VBGUP_MASK (0x80U) #define XTALOSC24M_MISC0_REFTOP_VBGUP_SHIFT (7U) #define XTALOSC24M_MISC0_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_REFTOP_VBGUP_SHIFT)) & XTALOSC24M_MISC0_REFTOP_VBGUP_MASK) #define XTALOSC24M_MISC0_STOP_MODE_CONFIG_MASK (0xC00U) #define XTALOSC24M_MISC0_STOP_MODE_CONFIG_SHIFT (10U) +/*! STOP_MODE_CONFIG + * 0b00..All analog except rtc powered down on stop mode assertion. XtalOsc=on, RCOsc=off; + * 0b01..Certain analog functions such as certain regulators left up. XtalOsc=on, RCOsc=off; + * 0b10..XtalOsc=off, RCOsc=on, Old BG=on, New BG=off. + * 0b11..XtalOsc=off, RCOsc=on, Old BG=off, New BG=on. + */ #define XTALOSC24M_MISC0_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_STOP_MODE_CONFIG_SHIFT)) & XTALOSC24M_MISC0_STOP_MODE_CONFIG_MASK) #define XTALOSC24M_MISC0_DISCON_HIGH_SNVS_MASK (0x1000U) #define XTALOSC24M_MISC0_DISCON_HIGH_SNVS_SHIFT (12U) +/*! DISCON_HIGH_SNVS + * 0b0..Turn on the switch + * 0b1..Turn off the switch + */ #define XTALOSC24M_MISC0_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_DISCON_HIGH_SNVS_SHIFT)) & XTALOSC24M_MISC0_DISCON_HIGH_SNVS_MASK) #define XTALOSC24M_MISC0_OSC_I_MASK (0x6000U) #define XTALOSC24M_MISC0_OSC_I_SHIFT (13U) +/*! OSC_I + * 0b00..Nominal + * 0b01..Decrease current by 12.5% + * 0b10..Decrease current by 25.0% + * 0b11..Decrease current by 37.5% + */ #define XTALOSC24M_MISC0_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_OSC_I_SHIFT)) & XTALOSC24M_MISC0_OSC_I_MASK) #define XTALOSC24M_MISC0_OSC_XTALOK_MASK (0x8000U) #define XTALOSC24M_MISC0_OSC_XTALOK_SHIFT (15U) @@ -26692,41 +41616,95 @@ typedef struct { #define XTALOSC24M_MISC0_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_OSC_XTALOK_EN_SHIFT)) & XTALOSC24M_MISC0_OSC_XTALOK_EN_MASK) #define XTALOSC24M_MISC0_CLKGATE_CTRL_MASK (0x2000000U) #define XTALOSC24M_MISC0_CLKGATE_CTRL_SHIFT (25U) +/*! CLKGATE_CTRL + * 0b0..Allow the logic to automatically gate the clock when the XTAL is powered down. + * 0b1..Prevent the logic from ever gating off the clock. + */ #define XTALOSC24M_MISC0_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLKGATE_CTRL_SHIFT)) & XTALOSC24M_MISC0_CLKGATE_CTRL_MASK) #define XTALOSC24M_MISC0_CLKGATE_DELAY_MASK (0x1C000000U) #define XTALOSC24M_MISC0_CLKGATE_DELAY_SHIFT (26U) +/*! CLKGATE_DELAY + * 0b000..0.5ms + * 0b001..1.0ms + * 0b010..2.0ms + * 0b011..3.0ms + * 0b100..4.0ms + * 0b101..5.0ms + * 0b110..6.0ms + * 0b111..7.0ms + */ #define XTALOSC24M_MISC0_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLKGATE_DELAY_SHIFT)) & XTALOSC24M_MISC0_CLKGATE_DELAY_MASK) #define XTALOSC24M_MISC0_RTC_XTAL_SOURCE_MASK (0x20000000U) #define XTALOSC24M_MISC0_RTC_XTAL_SOURCE_SHIFT (29U) +/*! RTC_XTAL_SOURCE + * 0b0..Internal ring oscillator + * 0b1..RTC_XTAL + */ #define XTALOSC24M_MISC0_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_RTC_XTAL_SOURCE_SHIFT)) & XTALOSC24M_MISC0_RTC_XTAL_SOURCE_MASK) #define XTALOSC24M_MISC0_XTAL_24M_PWD_MASK (0x40000000U) #define XTALOSC24M_MISC0_XTAL_24M_PWD_SHIFT (30U) #define XTALOSC24M_MISC0_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_XTAL_24M_PWD_SHIFT)) & XTALOSC24M_MISC0_XTAL_24M_PWD_MASK) #define XTALOSC24M_MISC0_VID_PLL_PREDIV_MASK (0x80000000U) #define XTALOSC24M_MISC0_VID_PLL_PREDIV_SHIFT (31U) +/*! VID_PLL_PREDIV + * 0b0..Divide by 1 + * 0b1..Divide by 2 + */ #define XTALOSC24M_MISC0_VID_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_VID_PLL_PREDIV_SHIFT)) & XTALOSC24M_MISC0_VID_PLL_PREDIV_MASK) +/*! @} */ /*! @name MISC0_SET - Miscellaneous Register 0 */ +/*! @{ */ #define XTALOSC24M_MISC0_SET_REFTOP_PWD_MASK (0x1U) #define XTALOSC24M_MISC0_SET_REFTOP_PWD_SHIFT (0U) #define XTALOSC24M_MISC0_SET_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_REFTOP_PWD_SHIFT)) & XTALOSC24M_MISC0_SET_REFTOP_PWD_MASK) #define XTALOSC24M_MISC0_SET_REFTOP_SELFBIASOFF_MASK (0x8U) #define XTALOSC24M_MISC0_SET_REFTOP_SELFBIASOFF_SHIFT (3U) +/*! REFTOP_SELFBIASOFF + * 0b0..Uses coarse bias currents for startup + * 0b1..Uses bandgap-based bias currents for best performance. + */ #define XTALOSC24M_MISC0_SET_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_REFTOP_SELFBIASOFF_SHIFT)) & XTALOSC24M_MISC0_SET_REFTOP_SELFBIASOFF_MASK) #define XTALOSC24M_MISC0_SET_REFTOP_VBGADJ_MASK (0x70U) #define XTALOSC24M_MISC0_SET_REFTOP_VBGADJ_SHIFT (4U) +/*! REFTOP_VBGADJ + * 0b000..Nominal VBG + * 0b001..VBG+0.78% + * 0b010..VBG+1.56% + * 0b011..VBG+2.34% + * 0b100..VBG-0.78% + * 0b101..VBG-1.56% + * 0b110..VBG-2.34% + * 0b111..VBG-3.12% + */ #define XTALOSC24M_MISC0_SET_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_REFTOP_VBGADJ_SHIFT)) & XTALOSC24M_MISC0_SET_REFTOP_VBGADJ_MASK) #define XTALOSC24M_MISC0_SET_REFTOP_VBGUP_MASK (0x80U) #define XTALOSC24M_MISC0_SET_REFTOP_VBGUP_SHIFT (7U) #define XTALOSC24M_MISC0_SET_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_REFTOP_VBGUP_SHIFT)) & XTALOSC24M_MISC0_SET_REFTOP_VBGUP_MASK) #define XTALOSC24M_MISC0_SET_STOP_MODE_CONFIG_MASK (0xC00U) #define XTALOSC24M_MISC0_SET_STOP_MODE_CONFIG_SHIFT (10U) +/*! STOP_MODE_CONFIG + * 0b00..All analog except rtc powered down on stop mode assertion. XtalOsc=on, RCOsc=off; + * 0b01..Certain analog functions such as certain regulators left up. XtalOsc=on, RCOsc=off; + * 0b10..XtalOsc=off, RCOsc=on, Old BG=on, New BG=off. + * 0b11..XtalOsc=off, RCOsc=on, Old BG=off, New BG=on. + */ #define XTALOSC24M_MISC0_SET_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_STOP_MODE_CONFIG_SHIFT)) & XTALOSC24M_MISC0_SET_STOP_MODE_CONFIG_MASK) #define XTALOSC24M_MISC0_SET_DISCON_HIGH_SNVS_MASK (0x1000U) #define XTALOSC24M_MISC0_SET_DISCON_HIGH_SNVS_SHIFT (12U) +/*! DISCON_HIGH_SNVS + * 0b0..Turn on the switch + * 0b1..Turn off the switch + */ #define XTALOSC24M_MISC0_SET_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_DISCON_HIGH_SNVS_SHIFT)) & XTALOSC24M_MISC0_SET_DISCON_HIGH_SNVS_MASK) #define XTALOSC24M_MISC0_SET_OSC_I_MASK (0x6000U) #define XTALOSC24M_MISC0_SET_OSC_I_SHIFT (13U) +/*! OSC_I + * 0b00..Nominal + * 0b01..Decrease current by 12.5% + * 0b10..Decrease current by 25.0% + * 0b11..Decrease current by 37.5% + */ #define XTALOSC24M_MISC0_SET_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_OSC_I_SHIFT)) & XTALOSC24M_MISC0_SET_OSC_I_MASK) #define XTALOSC24M_MISC0_SET_OSC_XTALOK_MASK (0x8000U) #define XTALOSC24M_MISC0_SET_OSC_XTALOK_SHIFT (15U) @@ -26736,41 +41714,95 @@ typedef struct { #define XTALOSC24M_MISC0_SET_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_OSC_XTALOK_EN_SHIFT)) & XTALOSC24M_MISC0_SET_OSC_XTALOK_EN_MASK) #define XTALOSC24M_MISC0_SET_CLKGATE_CTRL_MASK (0x2000000U) #define XTALOSC24M_MISC0_SET_CLKGATE_CTRL_SHIFT (25U) +/*! CLKGATE_CTRL + * 0b0..Allow the logic to automatically gate the clock when the XTAL is powered down. + * 0b1..Prevent the logic from ever gating off the clock. + */ #define XTALOSC24M_MISC0_SET_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_CLKGATE_CTRL_SHIFT)) & XTALOSC24M_MISC0_SET_CLKGATE_CTRL_MASK) #define XTALOSC24M_MISC0_SET_CLKGATE_DELAY_MASK (0x1C000000U) #define XTALOSC24M_MISC0_SET_CLKGATE_DELAY_SHIFT (26U) +/*! CLKGATE_DELAY + * 0b000..0.5ms + * 0b001..1.0ms + * 0b010..2.0ms + * 0b011..3.0ms + * 0b100..4.0ms + * 0b101..5.0ms + * 0b110..6.0ms + * 0b111..7.0ms + */ #define XTALOSC24M_MISC0_SET_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_CLKGATE_DELAY_SHIFT)) & XTALOSC24M_MISC0_SET_CLKGATE_DELAY_MASK) #define XTALOSC24M_MISC0_SET_RTC_XTAL_SOURCE_MASK (0x20000000U) #define XTALOSC24M_MISC0_SET_RTC_XTAL_SOURCE_SHIFT (29U) +/*! RTC_XTAL_SOURCE + * 0b0..Internal ring oscillator + * 0b1..RTC_XTAL + */ #define XTALOSC24M_MISC0_SET_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_RTC_XTAL_SOURCE_SHIFT)) & XTALOSC24M_MISC0_SET_RTC_XTAL_SOURCE_MASK) #define XTALOSC24M_MISC0_SET_XTAL_24M_PWD_MASK (0x40000000U) #define XTALOSC24M_MISC0_SET_XTAL_24M_PWD_SHIFT (30U) #define XTALOSC24M_MISC0_SET_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_XTAL_24M_PWD_SHIFT)) & XTALOSC24M_MISC0_SET_XTAL_24M_PWD_MASK) #define XTALOSC24M_MISC0_SET_VID_PLL_PREDIV_MASK (0x80000000U) #define XTALOSC24M_MISC0_SET_VID_PLL_PREDIV_SHIFT (31U) +/*! VID_PLL_PREDIV + * 0b0..Divide by 1 + * 0b1..Divide by 2 + */ #define XTALOSC24M_MISC0_SET_VID_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_VID_PLL_PREDIV_SHIFT)) & XTALOSC24M_MISC0_SET_VID_PLL_PREDIV_MASK) +/*! @} */ /*! @name MISC0_CLR - Miscellaneous Register 0 */ +/*! @{ */ #define XTALOSC24M_MISC0_CLR_REFTOP_PWD_MASK (0x1U) #define XTALOSC24M_MISC0_CLR_REFTOP_PWD_SHIFT (0U) #define XTALOSC24M_MISC0_CLR_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_REFTOP_PWD_SHIFT)) & XTALOSC24M_MISC0_CLR_REFTOP_PWD_MASK) #define XTALOSC24M_MISC0_CLR_REFTOP_SELFBIASOFF_MASK (0x8U) #define XTALOSC24M_MISC0_CLR_REFTOP_SELFBIASOFF_SHIFT (3U) +/*! REFTOP_SELFBIASOFF + * 0b0..Uses coarse bias currents for startup + * 0b1..Uses bandgap-based bias currents for best performance. + */ #define XTALOSC24M_MISC0_CLR_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_REFTOP_SELFBIASOFF_SHIFT)) & XTALOSC24M_MISC0_CLR_REFTOP_SELFBIASOFF_MASK) #define XTALOSC24M_MISC0_CLR_REFTOP_VBGADJ_MASK (0x70U) #define XTALOSC24M_MISC0_CLR_REFTOP_VBGADJ_SHIFT (4U) +/*! REFTOP_VBGADJ + * 0b000..Nominal VBG + * 0b001..VBG+0.78% + * 0b010..VBG+1.56% + * 0b011..VBG+2.34% + * 0b100..VBG-0.78% + * 0b101..VBG-1.56% + * 0b110..VBG-2.34% + * 0b111..VBG-3.12% + */ #define XTALOSC24M_MISC0_CLR_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_REFTOP_VBGADJ_SHIFT)) & XTALOSC24M_MISC0_CLR_REFTOP_VBGADJ_MASK) #define XTALOSC24M_MISC0_CLR_REFTOP_VBGUP_MASK (0x80U) #define XTALOSC24M_MISC0_CLR_REFTOP_VBGUP_SHIFT (7U) #define XTALOSC24M_MISC0_CLR_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_REFTOP_VBGUP_SHIFT)) & XTALOSC24M_MISC0_CLR_REFTOP_VBGUP_MASK) #define XTALOSC24M_MISC0_CLR_STOP_MODE_CONFIG_MASK (0xC00U) #define XTALOSC24M_MISC0_CLR_STOP_MODE_CONFIG_SHIFT (10U) +/*! STOP_MODE_CONFIG + * 0b00..All analog except rtc powered down on stop mode assertion. XtalOsc=on, RCOsc=off; + * 0b01..Certain analog functions such as certain regulators left up. XtalOsc=on, RCOsc=off; + * 0b10..XtalOsc=off, RCOsc=on, Old BG=on, New BG=off. + * 0b11..XtalOsc=off, RCOsc=on, Old BG=off, New BG=on. + */ #define XTALOSC24M_MISC0_CLR_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_STOP_MODE_CONFIG_SHIFT)) & XTALOSC24M_MISC0_CLR_STOP_MODE_CONFIG_MASK) #define XTALOSC24M_MISC0_CLR_DISCON_HIGH_SNVS_MASK (0x1000U) #define XTALOSC24M_MISC0_CLR_DISCON_HIGH_SNVS_SHIFT (12U) +/*! DISCON_HIGH_SNVS + * 0b0..Turn on the switch + * 0b1..Turn off the switch + */ #define XTALOSC24M_MISC0_CLR_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_DISCON_HIGH_SNVS_SHIFT)) & XTALOSC24M_MISC0_CLR_DISCON_HIGH_SNVS_MASK) #define XTALOSC24M_MISC0_CLR_OSC_I_MASK (0x6000U) #define XTALOSC24M_MISC0_CLR_OSC_I_SHIFT (13U) +/*! OSC_I + * 0b00..Nominal + * 0b01..Decrease current by 12.5% + * 0b10..Decrease current by 25.0% + * 0b11..Decrease current by 37.5% + */ #define XTALOSC24M_MISC0_CLR_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_OSC_I_SHIFT)) & XTALOSC24M_MISC0_CLR_OSC_I_MASK) #define XTALOSC24M_MISC0_CLR_OSC_XTALOK_MASK (0x8000U) #define XTALOSC24M_MISC0_CLR_OSC_XTALOK_SHIFT (15U) @@ -26780,41 +41812,95 @@ typedef struct { #define XTALOSC24M_MISC0_CLR_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_OSC_XTALOK_EN_SHIFT)) & XTALOSC24M_MISC0_CLR_OSC_XTALOK_EN_MASK) #define XTALOSC24M_MISC0_CLR_CLKGATE_CTRL_MASK (0x2000000U) #define XTALOSC24M_MISC0_CLR_CLKGATE_CTRL_SHIFT (25U) +/*! CLKGATE_CTRL + * 0b0..Allow the logic to automatically gate the clock when the XTAL is powered down. + * 0b1..Prevent the logic from ever gating off the clock. + */ #define XTALOSC24M_MISC0_CLR_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_CLKGATE_CTRL_SHIFT)) & XTALOSC24M_MISC0_CLR_CLKGATE_CTRL_MASK) #define XTALOSC24M_MISC0_CLR_CLKGATE_DELAY_MASK (0x1C000000U) #define XTALOSC24M_MISC0_CLR_CLKGATE_DELAY_SHIFT (26U) +/*! CLKGATE_DELAY + * 0b000..0.5ms + * 0b001..1.0ms + * 0b010..2.0ms + * 0b011..3.0ms + * 0b100..4.0ms + * 0b101..5.0ms + * 0b110..6.0ms + * 0b111..7.0ms + */ #define XTALOSC24M_MISC0_CLR_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_CLKGATE_DELAY_SHIFT)) & XTALOSC24M_MISC0_CLR_CLKGATE_DELAY_MASK) #define XTALOSC24M_MISC0_CLR_RTC_XTAL_SOURCE_MASK (0x20000000U) #define XTALOSC24M_MISC0_CLR_RTC_XTAL_SOURCE_SHIFT (29U) +/*! RTC_XTAL_SOURCE + * 0b0..Internal ring oscillator + * 0b1..RTC_XTAL + */ #define XTALOSC24M_MISC0_CLR_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_RTC_XTAL_SOURCE_SHIFT)) & XTALOSC24M_MISC0_CLR_RTC_XTAL_SOURCE_MASK) #define XTALOSC24M_MISC0_CLR_XTAL_24M_PWD_MASK (0x40000000U) #define XTALOSC24M_MISC0_CLR_XTAL_24M_PWD_SHIFT (30U) #define XTALOSC24M_MISC0_CLR_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_XTAL_24M_PWD_SHIFT)) & XTALOSC24M_MISC0_CLR_XTAL_24M_PWD_MASK) #define XTALOSC24M_MISC0_CLR_VID_PLL_PREDIV_MASK (0x80000000U) #define XTALOSC24M_MISC0_CLR_VID_PLL_PREDIV_SHIFT (31U) +/*! VID_PLL_PREDIV + * 0b0..Divide by 1 + * 0b1..Divide by 2 + */ #define XTALOSC24M_MISC0_CLR_VID_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_VID_PLL_PREDIV_SHIFT)) & XTALOSC24M_MISC0_CLR_VID_PLL_PREDIV_MASK) +/*! @} */ /*! @name MISC0_TOG - Miscellaneous Register 0 */ +/*! @{ */ #define XTALOSC24M_MISC0_TOG_REFTOP_PWD_MASK (0x1U) #define XTALOSC24M_MISC0_TOG_REFTOP_PWD_SHIFT (0U) #define XTALOSC24M_MISC0_TOG_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_REFTOP_PWD_SHIFT)) & XTALOSC24M_MISC0_TOG_REFTOP_PWD_MASK) #define XTALOSC24M_MISC0_TOG_REFTOP_SELFBIASOFF_MASK (0x8U) #define XTALOSC24M_MISC0_TOG_REFTOP_SELFBIASOFF_SHIFT (3U) +/*! REFTOP_SELFBIASOFF + * 0b0..Uses coarse bias currents for startup + * 0b1..Uses bandgap-based bias currents for best performance. + */ #define XTALOSC24M_MISC0_TOG_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_REFTOP_SELFBIASOFF_SHIFT)) & XTALOSC24M_MISC0_TOG_REFTOP_SELFBIASOFF_MASK) #define XTALOSC24M_MISC0_TOG_REFTOP_VBGADJ_MASK (0x70U) #define XTALOSC24M_MISC0_TOG_REFTOP_VBGADJ_SHIFT (4U) +/*! REFTOP_VBGADJ + * 0b000..Nominal VBG + * 0b001..VBG+0.78% + * 0b010..VBG+1.56% + * 0b011..VBG+2.34% + * 0b100..VBG-0.78% + * 0b101..VBG-1.56% + * 0b110..VBG-2.34% + * 0b111..VBG-3.12% + */ #define XTALOSC24M_MISC0_TOG_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_REFTOP_VBGADJ_SHIFT)) & XTALOSC24M_MISC0_TOG_REFTOP_VBGADJ_MASK) #define XTALOSC24M_MISC0_TOG_REFTOP_VBGUP_MASK (0x80U) #define XTALOSC24M_MISC0_TOG_REFTOP_VBGUP_SHIFT (7U) #define XTALOSC24M_MISC0_TOG_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_REFTOP_VBGUP_SHIFT)) & XTALOSC24M_MISC0_TOG_REFTOP_VBGUP_MASK) #define XTALOSC24M_MISC0_TOG_STOP_MODE_CONFIG_MASK (0xC00U) #define XTALOSC24M_MISC0_TOG_STOP_MODE_CONFIG_SHIFT (10U) +/*! STOP_MODE_CONFIG + * 0b00..All analog except rtc powered down on stop mode assertion. XtalOsc=on, RCOsc=off; + * 0b01..Certain analog functions such as certain regulators left up. XtalOsc=on, RCOsc=off; + * 0b10..XtalOsc=off, RCOsc=on, Old BG=on, New BG=off. + * 0b11..XtalOsc=off, RCOsc=on, Old BG=off, New BG=on. + */ #define XTALOSC24M_MISC0_TOG_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_STOP_MODE_CONFIG_SHIFT)) & XTALOSC24M_MISC0_TOG_STOP_MODE_CONFIG_MASK) #define XTALOSC24M_MISC0_TOG_DISCON_HIGH_SNVS_MASK (0x1000U) #define XTALOSC24M_MISC0_TOG_DISCON_HIGH_SNVS_SHIFT (12U) +/*! DISCON_HIGH_SNVS + * 0b0..Turn on the switch + * 0b1..Turn off the switch + */ #define XTALOSC24M_MISC0_TOG_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_DISCON_HIGH_SNVS_SHIFT)) & XTALOSC24M_MISC0_TOG_DISCON_HIGH_SNVS_MASK) #define XTALOSC24M_MISC0_TOG_OSC_I_MASK (0x6000U) #define XTALOSC24M_MISC0_TOG_OSC_I_SHIFT (13U) +/*! OSC_I + * 0b00..Nominal + * 0b01..Decrease current by 12.5% + * 0b10..Decrease current by 25.0% + * 0b11..Decrease current by 37.5% + */ #define XTALOSC24M_MISC0_TOG_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_OSC_I_SHIFT)) & XTALOSC24M_MISC0_TOG_OSC_I_MASK) #define XTALOSC24M_MISC0_TOG_OSC_XTALOK_MASK (0x8000U) #define XTALOSC24M_MISC0_TOG_OSC_XTALOK_SHIFT (15U) @@ -26824,32 +41910,65 @@ typedef struct { #define XTALOSC24M_MISC0_TOG_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_OSC_XTALOK_EN_SHIFT)) & XTALOSC24M_MISC0_TOG_OSC_XTALOK_EN_MASK) #define XTALOSC24M_MISC0_TOG_CLKGATE_CTRL_MASK (0x2000000U) #define XTALOSC24M_MISC0_TOG_CLKGATE_CTRL_SHIFT (25U) +/*! CLKGATE_CTRL + * 0b0..Allow the logic to automatically gate the clock when the XTAL is powered down. + * 0b1..Prevent the logic from ever gating off the clock. + */ #define XTALOSC24M_MISC0_TOG_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_CLKGATE_CTRL_SHIFT)) & XTALOSC24M_MISC0_TOG_CLKGATE_CTRL_MASK) #define XTALOSC24M_MISC0_TOG_CLKGATE_DELAY_MASK (0x1C000000U) #define XTALOSC24M_MISC0_TOG_CLKGATE_DELAY_SHIFT (26U) +/*! CLKGATE_DELAY + * 0b000..0.5ms + * 0b001..1.0ms + * 0b010..2.0ms + * 0b011..3.0ms + * 0b100..4.0ms + * 0b101..5.0ms + * 0b110..6.0ms + * 0b111..7.0ms + */ #define XTALOSC24M_MISC0_TOG_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_CLKGATE_DELAY_SHIFT)) & XTALOSC24M_MISC0_TOG_CLKGATE_DELAY_MASK) #define XTALOSC24M_MISC0_TOG_RTC_XTAL_SOURCE_MASK (0x20000000U) #define XTALOSC24M_MISC0_TOG_RTC_XTAL_SOURCE_SHIFT (29U) +/*! RTC_XTAL_SOURCE + * 0b0..Internal ring oscillator + * 0b1..RTC_XTAL + */ #define XTALOSC24M_MISC0_TOG_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_RTC_XTAL_SOURCE_SHIFT)) & XTALOSC24M_MISC0_TOG_RTC_XTAL_SOURCE_MASK) #define XTALOSC24M_MISC0_TOG_XTAL_24M_PWD_MASK (0x40000000U) #define XTALOSC24M_MISC0_TOG_XTAL_24M_PWD_SHIFT (30U) #define XTALOSC24M_MISC0_TOG_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_XTAL_24M_PWD_SHIFT)) & XTALOSC24M_MISC0_TOG_XTAL_24M_PWD_MASK) #define XTALOSC24M_MISC0_TOG_VID_PLL_PREDIV_MASK (0x80000000U) #define XTALOSC24M_MISC0_TOG_VID_PLL_PREDIV_SHIFT (31U) +/*! VID_PLL_PREDIV + * 0b0..Divide by 1 + * 0b1..Divide by 2 + */ #define XTALOSC24M_MISC0_TOG_VID_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_VID_PLL_PREDIV_SHIFT)) & XTALOSC24M_MISC0_TOG_VID_PLL_PREDIV_MASK) +/*! @} */ /*! @name LOWPWR_CTRL - XTAL OSC (LP) Control Register */ +/*! @{ */ #define XTALOSC24M_LOWPWR_CTRL_RC_OSC_EN_MASK (0x1U) #define XTALOSC24M_LOWPWR_CTRL_RC_OSC_EN_SHIFT (0U) +/*! RC_OSC_EN + * 0b0..Use XTAL OSC to source the 24MHz clock + * 0b1..Use RC OSC + */ #define XTALOSC24M_LOWPWR_CTRL_RC_OSC_EN(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_RC_OSC_EN_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_RC_OSC_EN_MASK) -#define XTALOSC24M_LOWPWR_CTRL_RC_OSC_PROG_MASK (0xEU) -#define XTALOSC24M_LOWPWR_CTRL_RC_OSC_PROG_SHIFT (1U) -#define XTALOSC24M_LOWPWR_CTRL_RC_OSC_PROG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_RC_OSC_PROG_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_RC_OSC_PROG_MASK) #define XTALOSC24M_LOWPWR_CTRL_OSC_SEL_MASK (0x10U) #define XTALOSC24M_LOWPWR_CTRL_OSC_SEL_SHIFT (4U) +/*! OSC_SEL + * 0b0..XTAL OSC + * 0b1..RC OSC + */ #define XTALOSC24M_LOWPWR_CTRL_OSC_SEL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_OSC_SEL_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_OSC_SEL_MASK) #define XTALOSC24M_LOWPWR_CTRL_LPBG_SEL_MASK (0x20U) #define XTALOSC24M_LOWPWR_CTRL_LPBG_SEL_SHIFT (5U) +/*! LPBG_SEL + * 0b0..Normal power bandgap + * 0b1..Low power bandgap + */ #define XTALOSC24M_LOWPWR_CTRL_LPBG_SEL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_LPBG_SEL_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_LPBG_SEL_MASK) #define XTALOSC24M_LOWPWR_CTRL_LPBG_TEST_MASK (0x40U) #define XTALOSC24M_LOWPWR_CTRL_LPBG_TEST_SHIFT (6U) @@ -26874,26 +41993,50 @@ typedef struct { #define XTALOSC24M_LOWPWR_CTRL_RCOSC_CG_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_RCOSC_CG_OVERRIDE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_RCOSC_CG_OVERRIDE_MASK) #define XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_DELAY_MASK (0xC000U) #define XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_DELAY_SHIFT (14U) +/*! XTALOSC_PWRUP_DELAY + * 0b00..0.25ms + * 0b01..0.5ms + * 0b10..1ms + * 0b11..2ms + */ #define XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_DELAY(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_DELAY_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_DELAY_MASK) #define XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_STAT_MASK (0x10000U) #define XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_STAT_SHIFT (16U) +/*! XTALOSC_PWRUP_STAT + * 0b0..Not stable + * 0b1..Stable and ready to use + */ #define XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_STAT(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_STAT_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_STAT_MASK) #define XTALOSC24M_LOWPWR_CTRL_MIX_PWRGATE_MASK (0x20000U) #define XTALOSC24M_LOWPWR_CTRL_MIX_PWRGATE_SHIFT (17U) #define XTALOSC24M_LOWPWR_CTRL_MIX_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_MIX_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_MIX_PWRGATE_MASK) +#define XTALOSC24M_LOWPWR_CTRL_GPU_PWRGATE_MASK (0x40000U) +#define XTALOSC24M_LOWPWR_CTRL_GPU_PWRGATE_SHIFT (18U) +#define XTALOSC24M_LOWPWR_CTRL_GPU_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_GPU_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_GPU_PWRGATE_MASK) +/*! @} */ /*! @name LOWPWR_CTRL_SET - XTAL OSC (LP) Control Register */ +/*! @{ */ #define XTALOSC24M_LOWPWR_CTRL_SET_RC_OSC_EN_MASK (0x1U) #define XTALOSC24M_LOWPWR_CTRL_SET_RC_OSC_EN_SHIFT (0U) +/*! RC_OSC_EN + * 0b0..Use XTAL OSC to source the 24MHz clock + * 0b1..Use RC OSC + */ #define XTALOSC24M_LOWPWR_CTRL_SET_RC_OSC_EN(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_RC_OSC_EN_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_RC_OSC_EN_MASK) -#define XTALOSC24M_LOWPWR_CTRL_SET_RC_OSC_PROG_MASK (0xEU) -#define XTALOSC24M_LOWPWR_CTRL_SET_RC_OSC_PROG_SHIFT (1U) -#define XTALOSC24M_LOWPWR_CTRL_SET_RC_OSC_PROG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_RC_OSC_PROG_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_RC_OSC_PROG_MASK) #define XTALOSC24M_LOWPWR_CTRL_SET_OSC_SEL_MASK (0x10U) #define XTALOSC24M_LOWPWR_CTRL_SET_OSC_SEL_SHIFT (4U) +/*! OSC_SEL + * 0b0..XTAL OSC + * 0b1..RC OSC + */ #define XTALOSC24M_LOWPWR_CTRL_SET_OSC_SEL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_OSC_SEL_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_OSC_SEL_MASK) #define XTALOSC24M_LOWPWR_CTRL_SET_LPBG_SEL_MASK (0x20U) #define XTALOSC24M_LOWPWR_CTRL_SET_LPBG_SEL_SHIFT (5U) +/*! LPBG_SEL + * 0b0..Normal power bandgap + * 0b1..Low power bandgap + */ #define XTALOSC24M_LOWPWR_CTRL_SET_LPBG_SEL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_LPBG_SEL_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_LPBG_SEL_MASK) #define XTALOSC24M_LOWPWR_CTRL_SET_LPBG_TEST_MASK (0x40U) #define XTALOSC24M_LOWPWR_CTRL_SET_LPBG_TEST_SHIFT (6U) @@ -26918,26 +42061,50 @@ typedef struct { #define XTALOSC24M_LOWPWR_CTRL_SET_RCOSC_CG_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_RCOSC_CG_OVERRIDE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_RCOSC_CG_OVERRIDE_MASK) #define XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_DELAY_MASK (0xC000U) #define XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_DELAY_SHIFT (14U) +/*! XTALOSC_PWRUP_DELAY + * 0b00..0.25ms + * 0b01..0.5ms + * 0b10..1ms + * 0b11..2ms + */ #define XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_DELAY(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_DELAY_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_DELAY_MASK) #define XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_STAT_MASK (0x10000U) #define XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_STAT_SHIFT (16U) +/*! XTALOSC_PWRUP_STAT + * 0b0..Not stable + * 0b1..Stable and ready to use + */ #define XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_STAT(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_STAT_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_STAT_MASK) #define XTALOSC24M_LOWPWR_CTRL_SET_MIX_PWRGATE_MASK (0x20000U) #define XTALOSC24M_LOWPWR_CTRL_SET_MIX_PWRGATE_SHIFT (17U) #define XTALOSC24M_LOWPWR_CTRL_SET_MIX_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_MIX_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_MIX_PWRGATE_MASK) +#define XTALOSC24M_LOWPWR_CTRL_SET_GPU_PWRGATE_MASK (0x40000U) +#define XTALOSC24M_LOWPWR_CTRL_SET_GPU_PWRGATE_SHIFT (18U) +#define XTALOSC24M_LOWPWR_CTRL_SET_GPU_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_GPU_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_GPU_PWRGATE_MASK) +/*! @} */ /*! @name LOWPWR_CTRL_CLR - XTAL OSC (LP) Control Register */ +/*! @{ */ #define XTALOSC24M_LOWPWR_CTRL_CLR_RC_OSC_EN_MASK (0x1U) #define XTALOSC24M_LOWPWR_CTRL_CLR_RC_OSC_EN_SHIFT (0U) +/*! RC_OSC_EN + * 0b0..Use XTAL OSC to source the 24MHz clock + * 0b1..Use RC OSC + */ #define XTALOSC24M_LOWPWR_CTRL_CLR_RC_OSC_EN(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_RC_OSC_EN_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_RC_OSC_EN_MASK) -#define XTALOSC24M_LOWPWR_CTRL_CLR_RC_OSC_PROG_MASK (0xEU) -#define XTALOSC24M_LOWPWR_CTRL_CLR_RC_OSC_PROG_SHIFT (1U) -#define XTALOSC24M_LOWPWR_CTRL_CLR_RC_OSC_PROG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_RC_OSC_PROG_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_RC_OSC_PROG_MASK) #define XTALOSC24M_LOWPWR_CTRL_CLR_OSC_SEL_MASK (0x10U) #define XTALOSC24M_LOWPWR_CTRL_CLR_OSC_SEL_SHIFT (4U) +/*! OSC_SEL + * 0b0..XTAL OSC + * 0b1..RC OSC + */ #define XTALOSC24M_LOWPWR_CTRL_CLR_OSC_SEL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_OSC_SEL_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_OSC_SEL_MASK) #define XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_SEL_MASK (0x20U) #define XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_SEL_SHIFT (5U) +/*! LPBG_SEL + * 0b0..Normal power bandgap + * 0b1..Low power bandgap + */ #define XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_SEL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_SEL_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_SEL_MASK) #define XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_TEST_MASK (0x40U) #define XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_TEST_SHIFT (6U) @@ -26962,26 +42129,50 @@ typedef struct { #define XTALOSC24M_LOWPWR_CTRL_CLR_RCOSC_CG_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_RCOSC_CG_OVERRIDE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_RCOSC_CG_OVERRIDE_MASK) #define XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_DELAY_MASK (0xC000U) #define XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_DELAY_SHIFT (14U) +/*! XTALOSC_PWRUP_DELAY + * 0b00..0.25ms + * 0b01..0.5ms + * 0b10..1ms + * 0b11..2ms + */ #define XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_DELAY(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_DELAY_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_DELAY_MASK) #define XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_STAT_MASK (0x10000U) #define XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_STAT_SHIFT (16U) +/*! XTALOSC_PWRUP_STAT + * 0b0..Not stable + * 0b1..Stable and ready to use + */ #define XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_STAT(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_STAT_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_STAT_MASK) #define XTALOSC24M_LOWPWR_CTRL_CLR_MIX_PWRGATE_MASK (0x20000U) #define XTALOSC24M_LOWPWR_CTRL_CLR_MIX_PWRGATE_SHIFT (17U) #define XTALOSC24M_LOWPWR_CTRL_CLR_MIX_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_MIX_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_MIX_PWRGATE_MASK) +#define XTALOSC24M_LOWPWR_CTRL_CLR_GPU_PWRGATE_MASK (0x40000U) +#define XTALOSC24M_LOWPWR_CTRL_CLR_GPU_PWRGATE_SHIFT (18U) +#define XTALOSC24M_LOWPWR_CTRL_CLR_GPU_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_GPU_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_GPU_PWRGATE_MASK) +/*! @} */ /*! @name LOWPWR_CTRL_TOG - XTAL OSC (LP) Control Register */ +/*! @{ */ #define XTALOSC24M_LOWPWR_CTRL_TOG_RC_OSC_EN_MASK (0x1U) #define XTALOSC24M_LOWPWR_CTRL_TOG_RC_OSC_EN_SHIFT (0U) +/*! RC_OSC_EN + * 0b0..Use XTAL OSC to source the 24MHz clock + * 0b1..Use RC OSC + */ #define XTALOSC24M_LOWPWR_CTRL_TOG_RC_OSC_EN(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_RC_OSC_EN_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_RC_OSC_EN_MASK) -#define XTALOSC24M_LOWPWR_CTRL_TOG_RC_OSC_PROG_MASK (0xEU) -#define XTALOSC24M_LOWPWR_CTRL_TOG_RC_OSC_PROG_SHIFT (1U) -#define XTALOSC24M_LOWPWR_CTRL_TOG_RC_OSC_PROG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_RC_OSC_PROG_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_RC_OSC_PROG_MASK) #define XTALOSC24M_LOWPWR_CTRL_TOG_OSC_SEL_MASK (0x10U) #define XTALOSC24M_LOWPWR_CTRL_TOG_OSC_SEL_SHIFT (4U) +/*! OSC_SEL + * 0b0..XTAL OSC + * 0b1..RC OSC + */ #define XTALOSC24M_LOWPWR_CTRL_TOG_OSC_SEL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_OSC_SEL_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_OSC_SEL_MASK) #define XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_SEL_MASK (0x20U) #define XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_SEL_SHIFT (5U) +/*! LPBG_SEL + * 0b0..Normal power bandgap + * 0b1..Low power bandgap + */ #define XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_SEL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_SEL_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_SEL_MASK) #define XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_TEST_MASK (0x40U) #define XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_TEST_SHIFT (6U) @@ -27006,15 +42197,30 @@ typedef struct { #define XTALOSC24M_LOWPWR_CTRL_TOG_RCOSC_CG_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_RCOSC_CG_OVERRIDE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_RCOSC_CG_OVERRIDE_MASK) #define XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_DELAY_MASK (0xC000U) #define XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_DELAY_SHIFT (14U) +/*! XTALOSC_PWRUP_DELAY + * 0b00..0.25ms + * 0b01..0.5ms + * 0b10..1ms + * 0b11..2ms + */ #define XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_DELAY(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_DELAY_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_DELAY_MASK) #define XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_STAT_MASK (0x10000U) #define XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_STAT_SHIFT (16U) +/*! XTALOSC_PWRUP_STAT + * 0b0..Not stable + * 0b1..Stable and ready to use + */ #define XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_STAT(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_STAT_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_STAT_MASK) #define XTALOSC24M_LOWPWR_CTRL_TOG_MIX_PWRGATE_MASK (0x20000U) #define XTALOSC24M_LOWPWR_CTRL_TOG_MIX_PWRGATE_SHIFT (17U) #define XTALOSC24M_LOWPWR_CTRL_TOG_MIX_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_MIX_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_MIX_PWRGATE_MASK) +#define XTALOSC24M_LOWPWR_CTRL_TOG_GPU_PWRGATE_MASK (0x40000U) +#define XTALOSC24M_LOWPWR_CTRL_TOG_GPU_PWRGATE_SHIFT (18U) +#define XTALOSC24M_LOWPWR_CTRL_TOG_GPU_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_GPU_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_GPU_PWRGATE_MASK) +/*! @} */ /*! @name OSC_CONFIG0 - XTAL OSC Configuration 0 Register */ +/*! @{ */ #define XTALOSC24M_OSC_CONFIG0_START_MASK (0x1U) #define XTALOSC24M_OSC_CONFIG0_START_SHIFT (0U) #define XTALOSC24M_OSC_CONFIG0_START(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_START_SHIFT)) & XTALOSC24M_OSC_CONFIG0_START_MASK) @@ -27039,8 +42245,10 @@ typedef struct { #define XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_CUR_MASK (0xFF000000U) #define XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_CUR_SHIFT (24U) #define XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_CUR(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_CUR_SHIFT)) & XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_CUR_MASK) +/*! @} */ /*! @name OSC_CONFIG0_SET - XTAL OSC Configuration 0 Register */ +/*! @{ */ #define XTALOSC24M_OSC_CONFIG0_SET_START_MASK (0x1U) #define XTALOSC24M_OSC_CONFIG0_SET_START_SHIFT (0U) #define XTALOSC24M_OSC_CONFIG0_SET_START(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_SET_START_SHIFT)) & XTALOSC24M_OSC_CONFIG0_SET_START_MASK) @@ -27065,8 +42273,10 @@ typedef struct { #define XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_CUR_MASK (0xFF000000U) #define XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_CUR_SHIFT (24U) #define XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_CUR(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_CUR_SHIFT)) & XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_CUR_MASK) +/*! @} */ /*! @name OSC_CONFIG0_CLR - XTAL OSC Configuration 0 Register */ +/*! @{ */ #define XTALOSC24M_OSC_CONFIG0_CLR_START_MASK (0x1U) #define XTALOSC24M_OSC_CONFIG0_CLR_START_SHIFT (0U) #define XTALOSC24M_OSC_CONFIG0_CLR_START(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_CLR_START_SHIFT)) & XTALOSC24M_OSC_CONFIG0_CLR_START_MASK) @@ -27091,8 +42301,10 @@ typedef struct { #define XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_CUR_MASK (0xFF000000U) #define XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_CUR_SHIFT (24U) #define XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_CUR(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_CUR_SHIFT)) & XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_CUR_MASK) +/*! @} */ /*! @name OSC_CONFIG0_TOG - XTAL OSC Configuration 0 Register */ +/*! @{ */ #define XTALOSC24M_OSC_CONFIG0_TOG_START_MASK (0x1U) #define XTALOSC24M_OSC_CONFIG0_TOG_START_SHIFT (0U) #define XTALOSC24M_OSC_CONFIG0_TOG_START(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_TOG_START_SHIFT)) & XTALOSC24M_OSC_CONFIG0_TOG_START_MASK) @@ -27117,40 +42329,50 @@ typedef struct { #define XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_CUR_MASK (0xFF000000U) #define XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_CUR_SHIFT (24U) #define XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_CUR(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_CUR_SHIFT)) & XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_CUR_MASK) +/*! @} */ /*! @name OSC_CONFIG1 - XTAL OSC Configuration 1 Register */ +/*! @{ */ #define XTALOSC24M_OSC_CONFIG1_COUNT_RC_TRG_MASK (0xFFFU) #define XTALOSC24M_OSC_CONFIG1_COUNT_RC_TRG_SHIFT (0U) #define XTALOSC24M_OSC_CONFIG1_COUNT_RC_TRG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG1_COUNT_RC_TRG_SHIFT)) & XTALOSC24M_OSC_CONFIG1_COUNT_RC_TRG_MASK) #define XTALOSC24M_OSC_CONFIG1_COUNT_RC_CUR_MASK (0xFFF00000U) #define XTALOSC24M_OSC_CONFIG1_COUNT_RC_CUR_SHIFT (20U) #define XTALOSC24M_OSC_CONFIG1_COUNT_RC_CUR(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG1_COUNT_RC_CUR_SHIFT)) & XTALOSC24M_OSC_CONFIG1_COUNT_RC_CUR_MASK) +/*! @} */ /*! @name OSC_CONFIG1_SET - XTAL OSC Configuration 1 Register */ +/*! @{ */ #define XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_TRG_MASK (0xFFFU) #define XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_TRG_SHIFT (0U) #define XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_TRG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_TRG_SHIFT)) & XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_TRG_MASK) #define XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_CUR_MASK (0xFFF00000U) #define XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_CUR_SHIFT (20U) #define XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_CUR(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_CUR_SHIFT)) & XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_CUR_MASK) +/*! @} */ /*! @name OSC_CONFIG1_CLR - XTAL OSC Configuration 1 Register */ +/*! @{ */ #define XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_TRG_MASK (0xFFFU) #define XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_TRG_SHIFT (0U) #define XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_TRG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_TRG_SHIFT)) & XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_TRG_MASK) #define XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_CUR_MASK (0xFFF00000U) #define XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_CUR_SHIFT (20U) #define XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_CUR(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_CUR_SHIFT)) & XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_CUR_MASK) +/*! @} */ /*! @name OSC_CONFIG1_TOG - XTAL OSC Configuration 1 Register */ +/*! @{ */ #define XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_TRG_MASK (0xFFFU) #define XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_TRG_SHIFT (0U) #define XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_TRG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_TRG_SHIFT)) & XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_TRG_MASK) #define XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_CUR_MASK (0xFFF00000U) #define XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_CUR_SHIFT (20U) #define XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_CUR(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_CUR_SHIFT)) & XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_CUR_MASK) +/*! @} */ /*! @name OSC_CONFIG2 - XTAL OSC Configuration 2 Register */ +/*! @{ */ #define XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG_MASK (0xFFFU) #define XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG_SHIFT (0U) #define XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG_SHIFT)) & XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG_MASK) @@ -27163,8 +42385,10 @@ typedef struct { #define XTALOSC24M_OSC_CONFIG2_CLK_1M_ERR_FL_MASK (0x80000000U) #define XTALOSC24M_OSC_CONFIG2_CLK_1M_ERR_FL_SHIFT (31U) #define XTALOSC24M_OSC_CONFIG2_CLK_1M_ERR_FL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_CLK_1M_ERR_FL_SHIFT)) & XTALOSC24M_OSC_CONFIG2_CLK_1M_ERR_FL_MASK) +/*! @} */ /*! @name OSC_CONFIG2_SET - XTAL OSC Configuration 2 Register */ +/*! @{ */ #define XTALOSC24M_OSC_CONFIG2_SET_COUNT_1M_TRG_MASK (0xFFFU) #define XTALOSC24M_OSC_CONFIG2_SET_COUNT_1M_TRG_SHIFT (0U) #define XTALOSC24M_OSC_CONFIG2_SET_COUNT_1M_TRG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_SET_COUNT_1M_TRG_SHIFT)) & XTALOSC24M_OSC_CONFIG2_SET_COUNT_1M_TRG_MASK) @@ -27177,8 +42401,10 @@ typedef struct { #define XTALOSC24M_OSC_CONFIG2_SET_CLK_1M_ERR_FL_MASK (0x80000000U) #define XTALOSC24M_OSC_CONFIG2_SET_CLK_1M_ERR_FL_SHIFT (31U) #define XTALOSC24M_OSC_CONFIG2_SET_CLK_1M_ERR_FL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_SET_CLK_1M_ERR_FL_SHIFT)) & XTALOSC24M_OSC_CONFIG2_SET_CLK_1M_ERR_FL_MASK) +/*! @} */ /*! @name OSC_CONFIG2_CLR - XTAL OSC Configuration 2 Register */ +/*! @{ */ #define XTALOSC24M_OSC_CONFIG2_CLR_COUNT_1M_TRG_MASK (0xFFFU) #define XTALOSC24M_OSC_CONFIG2_CLR_COUNT_1M_TRG_SHIFT (0U) #define XTALOSC24M_OSC_CONFIG2_CLR_COUNT_1M_TRG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_CLR_COUNT_1M_TRG_SHIFT)) & XTALOSC24M_OSC_CONFIG2_CLR_COUNT_1M_TRG_MASK) @@ -27191,8 +42417,10 @@ typedef struct { #define XTALOSC24M_OSC_CONFIG2_CLR_CLK_1M_ERR_FL_MASK (0x80000000U) #define XTALOSC24M_OSC_CONFIG2_CLR_CLK_1M_ERR_FL_SHIFT (31U) #define XTALOSC24M_OSC_CONFIG2_CLR_CLK_1M_ERR_FL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_CLR_CLK_1M_ERR_FL_SHIFT)) & XTALOSC24M_OSC_CONFIG2_CLR_CLK_1M_ERR_FL_MASK) +/*! @} */ /*! @name OSC_CONFIG2_TOG - XTAL OSC Configuration 2 Register */ +/*! @{ */ #define XTALOSC24M_OSC_CONFIG2_TOG_COUNT_1M_TRG_MASK (0xFFFU) #define XTALOSC24M_OSC_CONFIG2_TOG_COUNT_1M_TRG_SHIFT (0U) #define XTALOSC24M_OSC_CONFIG2_TOG_COUNT_1M_TRG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_TOG_COUNT_1M_TRG_SHIFT)) & XTALOSC24M_OSC_CONFIG2_TOG_COUNT_1M_TRG_MASK) @@ -27205,6 +42433,7 @@ typedef struct { #define XTALOSC24M_OSC_CONFIG2_TOG_CLK_1M_ERR_FL_MASK (0x80000000U) #define XTALOSC24M_OSC_CONFIG2_TOG_CLK_1M_ERR_FL_SHIFT (31U) #define XTALOSC24M_OSC_CONFIG2_TOG_CLK_1M_ERR_FL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_TOG_CLK_1M_ERR_FL_SHIFT)) & XTALOSC24M_OSC_CONFIG2_TOG_CLK_1M_ERR_FL_MASK) +/*! @} */ /*! @@ -27232,7 +42461,11 @@ typedef struct { */ #if defined(__ARMCC_VERSION) - #pragma pop + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop + #else + #pragma pop + #endif #elif defined(__CWCC__) #pragma pop #elif defined(__GNUC__) diff --git a/ext/hal/nxp/mcux/devices/MIMXRT1052/MIMXRT1052.xml b/ext/hal/nxp/mcux/devices/MIMXRT1052/MIMXRT1052.xml index 5f995799a23..882738e3790 100644 --- a/ext/hal/nxp/mcux/devices/MIMXRT1052/MIMXRT1052.xml +++ b/ext/hal/nxp/mcux/devices/MIMXRT1052/MIMXRT1052.xml @@ -3,32 +3,12 @@ nxp.com MIMXRT1052 1.0 - MIMXRT1052DVL6A + MIMXRT1052DVL6B -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: +Copyright 2016-2018 NXP +All rights reserved. -1. Redistributions of source code must retain the above copyright notice, this list - of conditions and the following disclaimer. - -2. Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. - -3. Neither the name of the copyright holder nor the names of its - contributors may be used to endorse or promote products derived from this - software without specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +SPDX-License-Identifier: BSD-3-Clause CM7 @@ -2154,22 +2134,22 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. read-write - DCDC_LOW_BAT - DCDC low battery detect + DCDC_IN_LOW_VOL + DCDC_IN low voltage detect. 16 1 read-only DCDC_OVER_CUR - DCDC over current alert + DCDC output over current alert 17 1 read-only DCDC_OVER_VOL - DCDC over voltage alert + DCDC output over voltage alert 18 1 read-only @@ -3588,17 +3568,17 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. SAI1_MCLK1_SEL_3 - iomux.sai1_ipg_clk_sai_mclk[2] + iomux.sai1_ipg_clk_sai_mclk 0x3 SAI1_MCLK1_SEL_4 - iomux.sai2_ipg_clk_sai_mclk[2] + iomux.sai2_ipg_clk_sai_mclk 0x4 SAI1_MCLK1_SEL_5 - iomux.sai3_ipg_clk_sai_mclk[2] + iomux.sai3_ipg_clk_sai_mclk 0x5 @@ -3627,17 +3607,17 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. SAI1_MCLK2_SEL_3 - iomux.sai1_ipg_clk_sai_mclk[2] + iomux.sai1_ipg_clk_sai_mclk 0x3 SAI1_MCLK2_SEL_4 - iomux.sai2_ipg_clk_sai_mclk[2] + iomux.sai2_ipg_clk_sai_mclk 0x4 SAI1_MCLK2_SEL_5 - iomux.sai3_ipg_clk_sai_mclk[2] + iomux.sai3_ipg_clk_sai_mclk 0x5 @@ -3731,7 +3711,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. GINT - Global interrupt "0" bit (connected to ARM M7 IRQ#0 and GPC) + Global interrupt bit (connected to ARM M7 IRQ#41 and GPC) 12 1 read-write @@ -3757,7 +3737,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ENET1_CLK_SEL_0 - ENET1 TX reference clock driven by ref_enetpll. This clock is also output to pins via the IOMUX. ENET_REF_CLK1 function. + ENET1 TX reference clock driven by ref_enetpll0. This clock is also output to pins via the IOMUX. ENET_REF_CLK1 function. 0 @@ -3788,76 +3768,76 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ENET1_TX_CLK_DIR - ENET1_TX_CLK data direction control when anatop. ENET_REF_CLK1 is selected (ALT1) + ENET1_TX_CLK data direction control when ENET_REF_CLK1 ALT is selected. 17 1 read-write ENET1_TX_CLK_DIR_0 - ENET1_TX_CLK output driver is disabled when configured for ALT1 + ENET1_TX_CLK output driver is disabled and ENET_REF_CLK1 is a clock input. 0 ENET1_TX_CLK_DIR_1 - ENET1_TX_CLK output driver is enabled when configured for ALT1 + ENET1_TX_CLK output driver is enabled and ENET_REF_CLK1 is an output driven by ref_enetpll0. 0x1 SAI1_MCLK_DIR - LCD_DATA00 data direction control when sai1.MCLK is selected (ALT8) + sai1.MCLK signal direction control 19 1 read-write SAI1_MCLK_DIR_0 - LCD_DATA00 output driver is disabled when configured for ALT8 + sai1.MCLK is input signal 0 SAI1_MCLK_DIR_1 - LCD_DATA00 output driver is enabled when configured for ALT8 + sai1.MCLK is output signal 0x1 SAI2_MCLK_DIR - SD1_CLK data direction control when sai2.MCLK is selected (ALT2) + sai2.MCLK signal direction control 20 1 read-write SAI2_MCLK_DIR_0 - SD1_CLK output driver is disabled when configured for ALT2 + sai2.MCLK is input signal 0 SAI2_MCLK_DIR_1 - SD1_CLK output driver is enabled when configured for ALT2 + sai2.MCLK is output signal 0x1 SAI3_MCLK_DIR - LCD_CLK data direction control when sai3.MCLK is selected (ALT3) + sai3.MCLK signal direction control 21 1 read-write SAI3_MCLK_DIR_0 - LCD_CLK output driver is disabled when configured for ALT3 + sai3.MCLK is input signal 0 SAI3_MCLK_DIR_1 - LCD_CLK output driver is enabled when configured for ALT3 + sai3.MCLK is output signal 0x1 @@ -3876,7 +3856,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. EXC_MON_1 - SLVError response (default) + SLVError response 0x1 @@ -3932,7 +3912,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. L2_MEM_EN_POWERSAVING - enable power saving features on L2 memory + enable power saving features on memory 12 1 read-write @@ -4138,7 +4118,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0xC 32 read-write - 0xFF0 + 0xFFF0 0xFFFFFFFF @@ -4510,12 +4490,12 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. TRNG_STOP_ACK_0 - ENET1 stop acknowledge is not asserted + TRNG stop acknowledge is not asserted 0 TRNG_STOP_ACK_1 - ENET1 stop acknowledge is asserted + TRNG stop acknowledge is asserted 0x1 @@ -4529,12 +4509,12 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ENET_STOP_ACK_0 - ENET2 stop acknowledge is not asserted + ENET stop acknowledge is not asserted 0 ENET_STOP_ACK_1 - ENET2 stop acknowledge is asserted + ENET stop acknowledge is asserted 0x1 @@ -4759,25 +4739,6 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - - GPT2_CAPIN2_SEL - GPT2 input capture channel 2 source select - 24 - 1 - read-write - - - GPT2_CAPIN2_SEL_0 - source from pad - 0 - - - GPT2_CAPIN2_SEL_1 - source from enet2.ipp_do_mac0_timer[3] - 0x1 - - - ENET_EVENT3IN_SEL ENET input timer event3 source select @@ -7298,7 +7259,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0x38 32 read-write - 0 + 0xAA0000 0xFFFFFFFF @@ -7530,108 +7491,108 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - CM7_MX6RT_CFGITCMSZ + CM7_CFGITCMSZ ITCM total size configuration 16 4 read-write - CM7_MX6RT_CFGITCMSZ_0 + CM7_CFGITCMSZ_0 0 KB (No ITCM) 0 - CM7_MX6RT_CFGITCMSZ_3 + CM7_CFGITCMSZ_3 4 KB 0x3 - CM7_MX6RT_CFGITCMSZ_4 + CM7_CFGITCMSZ_4 8 KB 0x4 - CM7_MX6RT_CFGITCMSZ_5 + CM7_CFGITCMSZ_5 16 KB 0x5 - CM7_MX6RT_CFGITCMSZ_6 + CM7_CFGITCMSZ_6 32 KB 0x6 - CM7_MX6RT_CFGITCMSZ_7 + CM7_CFGITCMSZ_7 64 KB 0x7 - CM7_MX6RT_CFGITCMSZ_8 + CM7_CFGITCMSZ_8 128 KB 0x8 - CM7_MX6RT_CFGITCMSZ_9 + CM7_CFGITCMSZ_9 256 KB 0x9 - CM7_MX6RT_CFGITCMSZ_10 + CM7_CFGITCMSZ_10 512 KB 0xA - CM7_MX6RT_CFGDTCMSZ + CM7_CFGDTCMSZ DTCM total size configuration 20 4 read-write - CM7_MX6RT_CFGDTCMSZ_0 + CM7_CFGDTCMSZ_0 0 KB (No DTCM) 0 - CM7_MX6RT_CFGDTCMSZ_3 + CM7_CFGDTCMSZ_3 4 KB 0x3 - CM7_MX6RT_CFGDTCMSZ_4 + CM7_CFGDTCMSZ_4 8 KB 0x4 - CM7_MX6RT_CFGDTCMSZ_5 + CM7_CFGDTCMSZ_5 16 KB 0x5 - CM7_MX6RT_CFGDTCMSZ_6 + CM7_CFGDTCMSZ_6 32 KB 0x6 - CM7_MX6RT_CFGDTCMSZ_7 + CM7_CFGDTCMSZ_7 64 KB 0x7 - CM7_MX6RT_CFGDTCMSZ_8 + CM7_CFGDTCMSZ_8 128 KB 0x8 - CM7_MX6RT_CFGDTCMSZ_9 + CM7_CFGDTCMSZ_9 256 KB 0x9 - CM7_MX6RT_CFGDTCMSZ_10 + CM7_CFGDTCMSZ_10 512 KB 0xA @@ -7714,13 +7675,6 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - - CM7_INIT_VTOR - Vector table offset register out of reset - 7 - 25 - read-write - @@ -7936,19 +7890,19 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0xFFFFFFFF - LOCK_M7_APC_AC_R1_TOP + LOCK_M7_APC_AC_R2_TOP lock M7_APC_AC_R2_TOP field for changes 0 1 read-write - LOCK_M7_APC_AC_R1_TOP_0 + LOCK_M7_APC_AC_R2_TOP_0 Register field [31:1] is not locked 0 - LOCK_M7_APC_AC_R1_TOP_1 + LOCK_M7_APC_AC_R2_TOP_1 Register field [31:1] is locked (read access only) 0x1 @@ -7992,7 +7946,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - M7_APC_AC_R2_BOT + M7_APC_AC_R3_BOT APC end address of memory region-3 3 29 @@ -8108,145 +8062,6 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 1 read-write - - Reserved - Reserved - 3 - 29 - read-only - - - - - OCRAM_MAGIC_ADDR - OCRAM Magic Address Register - 0x4 - 32 - read-write - 0 - 0xFFFFFFFF - - - OCRAM_WR_RD_SEL - OCRAM Write Read Select - 0 - 1 - read-write - - - OCRAM_WR_RD_SEL_0 - When OCRAM read access hits magic address, it will generate interrupt. - 0 - - - OCRAM_WR_RD_SEL_1 - When OCRAM write access hits magic address, it will generate interrupt. - 0x1 - - - - - OCRAM_MAGIC_ADDR - OCRAM Magic Address - 1 - 16 - read-write - - - Reserved - Reserved - 17 - 15 - read-only - - - - - DTCM_MAGIC_ADDR - DTCM Magic Address Register - 0x8 - 32 - read-write - 0 - 0xFFFFFFFF - - - DTCM_WR_RD_SEL - DTCM Write Read Select - 0 - 1 - read-write - - - DTCM_WR_RD_SEL_0 - When DTCM read access hits magic address, it will generate interrupt. - 0 - - - DTCM_WR_RD_SEL_1 - When DTCM write access hits magic address, it will generate interrupt. - 0x1 - - - - - DTCM_MAGIC_ADDR - DTCM Magic Address - 1 - 16 - read-write - - - Reserved - Reserved - 17 - 15 - read-only - - - - - ITCM_MAGIC_ADDR - ITCM Magic Address Register - 0xC - 32 - read-write - 0 - 0xFFFFFFFF - - - ITCM_WR_RD_SEL - ITCM Write Read Select - 0 - 1 - read-write - - - ITCM_WR_RD_SEL_0 - When ITCM read access hits magic address, it will generate interrupt. - 0 - - - ITCM_WR_RD_SEL_1 - When ITCM write access hits magic address, it will generate interrupt. - 0x1 - - - - - ITCM_MAGIC_ADDR - ITCM Magic Address - 1 - 16 - read-write - - - Reserved - Reserved - 17 - 15 - read-only - @@ -8258,66 +8073,6 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 0xFFFFFFFF - - ITCM_MAM_STATUS - ITCM Magic Address Match Status - 0 - 1 - read-write - oneToClear - - - ITCM_MAM_STATUS_0 - ITCM did not access magic address. - 0 - - - ITCM_MAM_STATUS_1 - ITCM accessed magic address. - 0x1 - - - - - DTCM_MAM_STATUS - DTCM Magic Address Match Status - 1 - 1 - read-write - oneToClear - - - DTCM_MAM_STATUS_0 - DTCM did not access magic address. - 0 - - - DTCM_MAM_STATUS_1 - DTCM accessed magic address. - 0x1 - - - - - OCRAM_MAM_STATUS - OCRAM Magic Address Match Status - 2 - 1 - read-write - oneToClear - - - OCRAM_MAM_STATUS_0 - OCRAM did not access magic address. - 0 - - - OCRAM_MAM_STATUS_1 - OCRAM accessed magic address. - 0x1 - - - ITCM_ERR_STATUS ITCM Access Error Status @@ -8378,13 +8133,6 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - - Reserved - Reserved - 6 - 26 - read-only - @@ -8396,63 +8144,6 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 0xFFFFFFFF - - ITCM_MAM_STAT_EN - ITCM Magic Address Match Status Enable - 0 - 1 - read-write - - - ITCM_MAM_STAT_EN_0 - Masked - 0 - - - ITCM_MAM_STAT_EN_1 - Enabled - 0x1 - - - - - DTCM_MAM_STAT_EN - DTCM Magic Address Match Status Enable - 1 - 1 - read-write - - - DTCM_MAM_STAT_EN_0 - Masked - 0 - - - DTCM_MAM_STAT_EN_1 - Enabled - 0x1 - - - - - OCRAM_MAM_STAT_EN - OCRAM Magic Address Match Status Enable - 2 - 1 - read-write - - - OCRAM_MAM_STAT_EN_0 - Masked - 0 - - - OCRAM_MAM_STAT_EN_1 - Enabled - 0x1 - - - ITCM_ERR_STAT_EN ITCM Access Error Status Enable @@ -8510,13 +8201,6 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - - Reserved - Reserved - 6 - 26 - read-only - @@ -8528,63 +8212,6 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 0xFFFFFFFF - - ITCM_MAM_SIG_EN - ITCM Magic Address Match Interrupt Enable - 0 - 1 - read-write - - - ITCM_MAM_SIG_EN_0 - Masked - 0 - - - ITCM_MAM_SIG_EN_1 - Enabled - 0x1 - - - - - DTCM_MAM_SIG_EN - DTCM Magic Address Match Interrupt Enable - 1 - 1 - read-write - - - DTCM_MAM_SIG_EN_0 - Masked - 0 - - - DTCM_MAM_SIG_EN_1 - Enabled - 0x1 - - - - - OCRAM_MAM_SIG_EN - OCRAM Magic Address Match Interrupt Enable - 2 - 1 - read-write - - - OCRAM_MAM_SIG_EN_0 - Masked - 0 - - - OCRAM_MAM_SIG_EN_1 - Enabled - 0x1 - - - ITCM_ERR_SIG_EN ITCM Access Error Interrupt Enable @@ -8642,13 +8269,6 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - - Reserved - Reserved - 6 - 26 - read-only - @@ -12149,7 +11769,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. LP_SWR - LP Software Reset When set to 1, the registers in the SNVS_LP section are reset + LP Software Reset When set to 1, most registers in the SNVS_LP section are reset, but the following registers are not reset by an LP software reset: Secure Real Time Counter Time Alarm Register This bit cannot be set when the LP_SWR_DIS bit is set 4 1 write-only @@ -12364,6 +11984,25 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + + DIS_PI + Disable periodic interrupt in the functional interrupt + 2 + 1 + read-write + + + DIS_PI_0 + Periodic interrupt will trigger a functional interrupt + 0 + + + DIS_PI_1 + Disable periodic interrupt in the function interrupt + 0x1 + + + PI_EN HP Periodic Interrupt Enable The periodic interrupt can be generated only if the HP Real Time Counter is enabled @@ -12879,7 +12518,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0x14 32 read-write - 0x8000B000 + 0x80003000 0xFFFFFFFF @@ -12994,41 +12633,59 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - SYS_SECURITY_CFG - System Security Configuration This field indicates the security configuration of SNVS, defined as follows: + SECURITY_CONFIG + Security Configuration This field reflects the settings of the sys_secure_boot input and the three security configuration inputs to SNVS 12 - 3 + 4 read-only - SYS_SECURITY_CFG_0 - Fab Configuration - the default configuration of newly fabricated chips + FAB_CONFIG + FAB configuration 0 - SYS_SECURITY_CFG_1 - Open Configuration - the configuration after NXP-programmable fuses have been blown + OPEN_CONFIG + OPEN configuration 0x1 - SYS_SECURITY_CFG_3 - Closed Configuration - the configuration after OEM-programmable fuses have been blown + OPEN_CONFIG + OPEN configuration + 0x2 + + + OPEN_CONFIG + OPEN configuration 0x3 - SYS_SECURITY_CFG_7 - Field Return Configuration - the configuration of chips that are returned to NXP for analysis - 0x7 + FIELD_RETURN_CONFIG + FIELD RETURN configuration + #x1xx + + + FAB_CONFIG + FAB configuration + 0x8 + + + CLOSED_CONFIG + CLOSED configuration + 0x9 + + + CLOSED_CONFIG + CLOSED configuration + 0xA + + + CLOSED_CONFIG + CLOSED configuration + 0xB - - SYS_SECURE_BOOT - System Secure Boot If SYS_SECURE_BOOT is 1, the chip boots from internal ROM. - 15 - 1 - read-only - OTPMK_SYNDROME One Time Programmable Master Key Syndrome In the case of a single-bit error, the eight lower bits of this value indicate the bit number of error location @@ -13558,7 +13215,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0x38 32 read-write - 0 + 0x20 0xFFFFFFFF @@ -14434,7 +14091,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. MC_ERA_BITS - Monotonic Counter Era Bits These bits are inputs to the module and typically connect to fuses. + Monotonic Counter Era Bits These bits are inputs to the module and typically connect to fuses 16 16 read-only @@ -14536,10 +14193,10 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - 4 + 8 0x4 LPGPR[%s] - SNVS_LP General Purpose Registers 0 .. 3 + SNVS_LP General Purpose Registers 0 .. 7 0x100 32 read-write @@ -14940,8 +14597,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. DIV_SELECT This field controls the PLL loop divider. 0 - Fout=Fref*20; 1 - Fout=Fref*22. - 0 - 2 + 1 + 1 read-write @@ -14994,16 +14651,6 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. Select the CLK1_N / CLK1_P as source. 0x1 - - GPANAIO - GPANAIO - 0x2 - - - CHRG_DET_B - CHRG_DET_B - 0x3 - @@ -15034,8 +14681,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. DIV_SELECT This field controls the PLL loop divider. 0 - Fout=Fref*20; 1 - Fout=Fref*22. - 0 - 2 + 1 + 1 read-write @@ -15088,16 +14735,6 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. Select the CLK1_N / CLK1_P as source. 0x1 - - GPANAIO - GPANAIO - 0x2 - - - CHRG_DET_B - CHRG_DET_B - 0x3 - @@ -15128,8 +14765,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. DIV_SELECT This field controls the PLL loop divider. 0 - Fout=Fref*20; 1 - Fout=Fref*22. - 0 - 2 + 1 + 1 read-write @@ -15182,16 +14819,6 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. Select the CLK1_N / CLK1_P as source. 0x1 - - GPANAIO - GPANAIO - 0x2 - - - CHRG_DET_B - CHRG_DET_B - 0x3 - @@ -15222,8 +14849,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. DIV_SELECT This field controls the PLL loop divider. 0 - Fout=Fref*20; 1 - Fout=Fref*22. - 0 - 2 + 1 + 1 read-write @@ -15276,16 +14903,6 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. Select the CLK1_N / CLK1_P as source. 0x1 - - GPANAIO - GPANAIO - 0x2 - - - CHRG_DET_B - CHRG_DET_B - 0x3 - @@ -15316,8 +14933,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. DIV_SELECT This field controls the PLL loop divider. 0 - Fout=Fref*20; 1 - Fout=Fref*22. - 0 - 2 + 1 + 1 read-write @@ -15388,8 +15005,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. DIV_SELECT This field controls the PLL loop divider. 0 - Fout=Fref*20; 1 - Fout=Fref*22. - 0 - 2 + 1 + 1 read-write @@ -15460,8 +15077,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. DIV_SELECT This field controls the PLL loop divider. 0 - Fout=Fref*20; 1 - Fout=Fref*22. - 0 - 2 + 1 + 1 read-write @@ -15532,8 +15149,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. DIV_SELECT This field controls the PLL loop divider. 0 - Fout=Fref*20; 1 - Fout=Fref*22. - 0 - 2 + 1 + 1 read-write @@ -15639,16 +15256,6 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. Select the CLK1_N / CLK1_P as source. 0x1 - - GPANAIO - GPANAIO - 0x2 - - - CHRG_DET_B - CHRG_DET_B - 0x3 - @@ -15721,16 +15328,6 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. Select the CLK1_N / CLK1_P as source. 0x1 - - GPANAIO - GPANAIO - 0x2 - - - CHRG_DET_B - CHRG_DET_B - 0x3 - @@ -15803,16 +15400,6 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. Select the CLK1_N / CLK1_P as source. 0x1 - - GPANAIO - GPANAIO - 0x2 - - - CHRG_DET_B - CHRG_DET_B - 0x3 - @@ -15885,16 +15472,6 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. Select the CLK1_N / CLK1_P as source. 0x1 - - GPANAIO - GPANAIO - 0x2 - - - CHRG_DET_B - CHRG_DET_B - 0x3 - @@ -16850,62 +16427,11 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0xFFFFFFFF - ENET0_DIV_SELECT - Controls the frequency of the ethernet0 reference clock. + DIV_SELECT + Controls the frequency of the ethernet reference clock 0 2 read-write - - - ENET0_DIV_SELECT_0 - 25MHz - 0 - - - ENET0_DIV_SELECT_1 - 50MHz - 0x1 - - - ENET0_DIV_SELECT_2 - 100MHz (not 50% duty cycle) - 0x2 - - - ENET0_DIV_SELECT_3 - 125MHz - 0x3 - - - - - ENET1_DIV_SELECT - Controls the frequency of the ethernet1 reference clock. - 2 - 2 - read-write - - - ENET1_DIV_SELECT_0 - 25MHz - 0 - - - ENET1_DIV_SELECT_1 - 50MHz - 0x1 - - - ENET1_DIV_SELECT_2 - 100MHz (not 50% duty cycle) - 0x2 - - - ENET1_DIV_SELECT_3 - 125MHz - 0x3 - - POWERDOWN @@ -16915,8 +16441,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. read-write - ENET1_125M_EN - Enable the PLL providing the ENET1 125 MHz reference clock. + ENABLE + Enable the ethernet clock output. 13 1 read-write @@ -16954,20 +16480,6 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 1 read-write - - ENABLE_125M - Enables an offset in the phase frequency detector. - 19 - 1 - read-write - - - ENET2_125M_EN - Enable the PLL providing the ENET2 125 MHz reference clock - 20 - 1 - read-write - ENET_25M_REF_EN Enable the PLL providing ENET 25 MHz reference clock @@ -16994,62 +16506,11 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0xFFFFFFFF - ENET0_DIV_SELECT - Controls the frequency of the ethernet0 reference clock. + DIV_SELECT + Controls the frequency of the ethernet reference clock 0 2 read-write - - - ENET0_DIV_SELECT_0 - 25MHz - 0 - - - ENET0_DIV_SELECT_1 - 50MHz - 0x1 - - - ENET0_DIV_SELECT_2 - 100MHz (not 50% duty cycle) - 0x2 - - - ENET0_DIV_SELECT_3 - 125MHz - 0x3 - - - - - ENET1_DIV_SELECT - Controls the frequency of the ethernet1 reference clock. - 2 - 2 - read-write - - - ENET1_DIV_SELECT_0 - 25MHz - 0 - - - ENET1_DIV_SELECT_1 - 50MHz - 0x1 - - - ENET1_DIV_SELECT_2 - 100MHz (not 50% duty cycle) - 0x2 - - - ENET1_DIV_SELECT_3 - 125MHz - 0x3 - - POWERDOWN @@ -17059,8 +16520,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. read-write - ENET1_125M_EN - Enable the PLL providing the ENET1 125 MHz reference clock. + ENABLE + Enable the ethernet clock output. 13 1 read-write @@ -17098,20 +16559,6 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 1 read-write - - ENABLE_125M - Enables an offset in the phase frequency detector. - 19 - 1 - read-write - - - ENET2_125M_EN - Enable the PLL providing the ENET2 125 MHz reference clock - 20 - 1 - read-write - ENET_25M_REF_EN Enable the PLL providing ENET 25 MHz reference clock @@ -17138,62 +16585,11 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0xFFFFFFFF - ENET0_DIV_SELECT - Controls the frequency of the ethernet0 reference clock. + DIV_SELECT + Controls the frequency of the ethernet reference clock 0 2 read-write - - - ENET0_DIV_SELECT_0 - 25MHz - 0 - - - ENET0_DIV_SELECT_1 - 50MHz - 0x1 - - - ENET0_DIV_SELECT_2 - 100MHz (not 50% duty cycle) - 0x2 - - - ENET0_DIV_SELECT_3 - 125MHz - 0x3 - - - - - ENET1_DIV_SELECT - Controls the frequency of the ethernet1 reference clock. - 2 - 2 - read-write - - - ENET1_DIV_SELECT_0 - 25MHz - 0 - - - ENET1_DIV_SELECT_1 - 50MHz - 0x1 - - - ENET1_DIV_SELECT_2 - 100MHz (not 50% duty cycle) - 0x2 - - - ENET1_DIV_SELECT_3 - 125MHz - 0x3 - - POWERDOWN @@ -17203,8 +16599,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. read-write - ENET1_125M_EN - Enable the PLL providing the ENET1 125 MHz reference clock. + ENABLE + Enable the ethernet clock output. 13 1 read-write @@ -17242,20 +16638,6 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 1 read-write - - ENABLE_125M - Enables an offset in the phase frequency detector. - 19 - 1 - read-write - - - ENET2_125M_EN - Enable the PLL providing the ENET2 125 MHz reference clock - 20 - 1 - read-write - ENET_25M_REF_EN Enable the PLL providing ENET 25 MHz reference clock @@ -17282,62 +16664,11 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0xFFFFFFFF - ENET0_DIV_SELECT - Controls the frequency of the ethernet0 reference clock. + DIV_SELECT + Controls the frequency of the ethernet reference clock 0 2 read-write - - - ENET0_DIV_SELECT_0 - 25MHz - 0 - - - ENET0_DIV_SELECT_1 - 50MHz - 0x1 - - - ENET0_DIV_SELECT_2 - 100MHz (not 50% duty cycle) - 0x2 - - - ENET0_DIV_SELECT_3 - 125MHz - 0x3 - - - - - ENET1_DIV_SELECT - Controls the frequency of the ethernet1 reference clock. - 2 - 2 - read-write - - - ENET1_DIV_SELECT_0 - 25MHz - 0 - - - ENET1_DIV_SELECT_1 - 50MHz - 0x1 - - - ENET1_DIV_SELECT_2 - 100MHz (not 50% duty cycle) - 0x2 - - - ENET1_DIV_SELECT_3 - 125MHz - 0x3 - - POWERDOWN @@ -17347,8 +16678,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. read-write - ENET1_125M_EN - Enable the PLL providing the ENET1 125 MHz reference clock. + ENABLE + Enable the ethernet clock output. 13 1 read-write @@ -17386,20 +16717,6 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 1 read-write - - ENABLE_125M - Enables an offset in the phase frequency detector. - 19 - 1 - read-write - - - ENET2_125M_EN - Enable the PLL providing the ENET2 125 MHz reference clock - 20 - 1 - read-write - ENET_25M_REF_EN Enable the PLL providing ENET 25 MHz reference clock @@ -18452,25 +17769,6 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 1 read-write - - VID_PLL_PREDIV - Predivider for the source clock of the PLL's. - 31 - 1 - read-write - - - VID_PLL_PREDIV_0 - Divide by 1 - 0 - - - VID_PLL_PREDIV_1 - Divide by 2 - 0x1 - - - @@ -18749,25 +18047,6 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 1 read-write - - VID_PLL_PREDIV - Predivider for the source clock of the PLL's. - 31 - 1 - read-write - - - VID_PLL_PREDIV_0 - Divide by 1 - 0 - - - VID_PLL_PREDIV_1 - Divide by 2 - 0x1 - - - @@ -19046,25 +18325,6 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 1 read-write - - VID_PLL_PREDIV - Predivider for the source clock of the PLL's. - 31 - 1 - read-write - - - VID_PLL_PREDIV_0 - Divide by 1 - 0 - - - VID_PLL_PREDIV_1 - Divide by 2 - 0x1 - - - @@ -19343,25 +18603,6 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 1 read-write - - VID_PLL_PREDIV - Predivider for the source clock of the PLL's. - 31 - 1 - read-write - - - VID_PLL_PREDIV_0 - Divide by 1 - 0 - - - VID_PLL_PREDIV_1 - Divide by 2 - 0x1 - - - @@ -21322,6 +20563,10 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0x180 registers + + PMU_EVENT + 61 + REG_1P1 @@ -21421,7 +20666,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. SELREF_WEAK_LINREG_1 - Weak-linreg output tracks VDD_SOC_CAP voltage + Weak-linreg output tracks VDD_SOC_IN voltage 0x1 @@ -21526,7 +20771,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. SELREF_WEAK_LINREG_1 - Weak-linreg output tracks VDD_SOC_CAP voltage + Weak-linreg output tracks VDD_SOC_IN voltage 0x1 @@ -21631,7 +20876,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. SELREF_WEAK_LINREG_1 - Weak-linreg output tracks VDD_SOC_CAP voltage + Weak-linreg output tracks VDD_SOC_IN voltage 0x1 @@ -21736,7 +20981,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. SELREF_WEAK_LINREG_1 - Weak-linreg output tracks VDD_SOC_CAP voltage + Weak-linreg output tracks VDD_SOC_IN voltage 0x1 @@ -22544,6 +21789,228 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + + REG0_ADJ + This bit field defines the adjustment bits to calibrate the target value of Reg0. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register. + 5 + 4 + read-write + + + REG0_ADJ_0 + No adjustment + 0 + + + REG0_ADJ_1 + + 0.25% + 0x1 + + + REG0_ADJ_2 + + 0.50% + 0x2 + + + REG0_ADJ_3 + + 0.75% + 0x3 + + + REG0_ADJ_4 + + 1.00% + 0x4 + + + REG0_ADJ_5 + + 1.25% + 0x5 + + + REG0_ADJ_6 + + 1.50% + 0x6 + + + REG0_ADJ_7 + + 1.75% + 0x7 + + + REG0_ADJ_8 + - 0.25% + 0x8 + + + REG0_ADJ_9 + - 0.50% + 0x9 + + + REG0_ADJ_10 + - 0.75% + 0xA + + + REG0_ADJ_11 + - 1.00% + 0xB + + + REG0_ADJ_12 + - 1.25% + 0xC + + + REG0_ADJ_13 + - 1.50% + 0xD + + + REG0_ADJ_14 + - 1.75% + 0xE + + + REG0_ADJ_15 + - 2.00% + 0xF + + + + + REG1_TARG + This bit field defines the target voltage for the vpu/gpu power domain. Single bit increments reflect 25mV core voltage steps. Not all steps will make sense to use either because of input supply limitations or load operation. + 9 + 5 + read-write + + + REG1_TARG_0 + Power gated off + 0 + + + REG1_TARG_1 + Target core voltage = 0.725V + 0x1 + + + REG1_TARG_2 + Target core voltage = 0.750V + 0x2 + + + REG1_TARG_3 + Target core voltage = 0.775V + 0x3 + + + REG1_TARG_16 + Target core voltage = 1.100V + 0x10 + + + REG1_TARG_30 + Target core voltage = 1.450V + 0x1E + + + REG1_TARG_31 + Power FET switched full on. No regulation. + 0x1F + + + + + REG1_ADJ + This bit field defines the adjustment bits to calibrate the target value of Reg1. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register. + 14 + 4 + read-write + + + REG1_ADJ_0 + No adjustment + 0 + + + REG1_ADJ_1 + + 0.25% + 0x1 + + + REG1_ADJ_2 + + 0.50% + 0x2 + + + REG1_ADJ_3 + + 0.75% + 0x3 + + + REG1_ADJ_4 + + 1.00% + 0x4 + + + REG1_ADJ_5 + + 1.25% + 0x5 + + + REG1_ADJ_6 + + 1.50% + 0x6 + + + REG1_ADJ_7 + + 1.75% + 0x7 + + + REG1_ADJ_8 + - 0.25% + 0x8 + + + REG1_ADJ_9 + - 0.50% + 0x9 + + + REG1_ADJ_10 + - 0.75% + 0xA + + + REG1_ADJ_11 + - 1.00% + 0xB + + + REG1_ADJ_12 + - 1.25% + 0xC + + + REG1_ADJ_13 + - 1.50% + 0xD + + + REG1_ADJ_14 + - 1.75% + 0xE + + + REG1_ADJ_15 + - 2.00% + 0xF + + + REG2_TARG This field defines the target voltage for the SOC power domain @@ -22588,6 +22055,95 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + + REG2_ADJ + This bit field defines the adjustment bits to calibrate the target value of Reg2. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register. + 23 + 4 + read-write + + + REG2_ADJ_0 + No adjustment + 0 + + + REG2_ADJ_1 + + 0.25% + 0x1 + + + REG2_ADJ_2 + + 0.50% + 0x2 + + + REG2_ADJ_3 + + 0.75% + 0x3 + + + REG2_ADJ_4 + + 1.00% + 0x4 + + + REG2_ADJ_5 + + 1.25% + 0x5 + + + REG2_ADJ_6 + + 1.50% + 0x6 + + + REG2_ADJ_7 + + 1.75% + 0x7 + + + REG2_ADJ_8 + - 0.25% + 0x8 + + + REG2_ADJ_9 + - 0.50% + 0x9 + + + REG2_ADJ_10 + - 0.75% + 0xA + + + REG2_ADJ_11 + - 1.00% + 0xB + + + REG2_ADJ_12 + - 1.25% + 0xC + + + REG2_ADJ_13 + - 1.50% + 0xD + + + REG2_ADJ_14 + - 1.75% + 0xE + + + REG2_ADJ_15 + - 2.00% + 0xF + + + RAMP_RATE Regulator voltage ramp rate. @@ -22679,6 +22235,228 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + + REG0_ADJ + This bit field defines the adjustment bits to calibrate the target value of Reg0. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register. + 5 + 4 + read-write + + + REG0_ADJ_0 + No adjustment + 0 + + + REG0_ADJ_1 + + 0.25% + 0x1 + + + REG0_ADJ_2 + + 0.50% + 0x2 + + + REG0_ADJ_3 + + 0.75% + 0x3 + + + REG0_ADJ_4 + + 1.00% + 0x4 + + + REG0_ADJ_5 + + 1.25% + 0x5 + + + REG0_ADJ_6 + + 1.50% + 0x6 + + + REG0_ADJ_7 + + 1.75% + 0x7 + + + REG0_ADJ_8 + - 0.25% + 0x8 + + + REG0_ADJ_9 + - 0.50% + 0x9 + + + REG0_ADJ_10 + - 0.75% + 0xA + + + REG0_ADJ_11 + - 1.00% + 0xB + + + REG0_ADJ_12 + - 1.25% + 0xC + + + REG0_ADJ_13 + - 1.50% + 0xD + + + REG0_ADJ_14 + - 1.75% + 0xE + + + REG0_ADJ_15 + - 2.00% + 0xF + + + + + REG1_TARG + This bit field defines the target voltage for the vpu/gpu power domain. Single bit increments reflect 25mV core voltage steps. Not all steps will make sense to use either because of input supply limitations or load operation. + 9 + 5 + read-write + + + REG1_TARG_0 + Power gated off + 0 + + + REG1_TARG_1 + Target core voltage = 0.725V + 0x1 + + + REG1_TARG_2 + Target core voltage = 0.750V + 0x2 + + + REG1_TARG_3 + Target core voltage = 0.775V + 0x3 + + + REG1_TARG_16 + Target core voltage = 1.100V + 0x10 + + + REG1_TARG_30 + Target core voltage = 1.450V + 0x1E + + + REG1_TARG_31 + Power FET switched full on. No regulation. + 0x1F + + + + + REG1_ADJ + This bit field defines the adjustment bits to calibrate the target value of Reg1. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register. + 14 + 4 + read-write + + + REG1_ADJ_0 + No adjustment + 0 + + + REG1_ADJ_1 + + 0.25% + 0x1 + + + REG1_ADJ_2 + + 0.50% + 0x2 + + + REG1_ADJ_3 + + 0.75% + 0x3 + + + REG1_ADJ_4 + + 1.00% + 0x4 + + + REG1_ADJ_5 + + 1.25% + 0x5 + + + REG1_ADJ_6 + + 1.50% + 0x6 + + + REG1_ADJ_7 + + 1.75% + 0x7 + + + REG1_ADJ_8 + - 0.25% + 0x8 + + + REG1_ADJ_9 + - 0.50% + 0x9 + + + REG1_ADJ_10 + - 0.75% + 0xA + + + REG1_ADJ_11 + - 1.00% + 0xB + + + REG1_ADJ_12 + - 1.25% + 0xC + + + REG1_ADJ_13 + - 1.50% + 0xD + + + REG1_ADJ_14 + - 1.75% + 0xE + + + REG1_ADJ_15 + - 2.00% + 0xF + + + REG2_TARG This field defines the target voltage for the SOC power domain @@ -22723,6 +22501,95 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + + REG2_ADJ + This bit field defines the adjustment bits to calibrate the target value of Reg2. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register. + 23 + 4 + read-write + + + REG2_ADJ_0 + No adjustment + 0 + + + REG2_ADJ_1 + + 0.25% + 0x1 + + + REG2_ADJ_2 + + 0.50% + 0x2 + + + REG2_ADJ_3 + + 0.75% + 0x3 + + + REG2_ADJ_4 + + 1.00% + 0x4 + + + REG2_ADJ_5 + + 1.25% + 0x5 + + + REG2_ADJ_6 + + 1.50% + 0x6 + + + REG2_ADJ_7 + + 1.75% + 0x7 + + + REG2_ADJ_8 + - 0.25% + 0x8 + + + REG2_ADJ_9 + - 0.50% + 0x9 + + + REG2_ADJ_10 + - 0.75% + 0xA + + + REG2_ADJ_11 + - 1.00% + 0xB + + + REG2_ADJ_12 + - 1.25% + 0xC + + + REG2_ADJ_13 + - 1.50% + 0xD + + + REG2_ADJ_14 + - 1.75% + 0xE + + + REG2_ADJ_15 + - 2.00% + 0xF + + + RAMP_RATE Regulator voltage ramp rate. @@ -22814,6 +22681,228 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + + REG0_ADJ + This bit field defines the adjustment bits to calibrate the target value of Reg0. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register. + 5 + 4 + read-write + + + REG0_ADJ_0 + No adjustment + 0 + + + REG0_ADJ_1 + + 0.25% + 0x1 + + + REG0_ADJ_2 + + 0.50% + 0x2 + + + REG0_ADJ_3 + + 0.75% + 0x3 + + + REG0_ADJ_4 + + 1.00% + 0x4 + + + REG0_ADJ_5 + + 1.25% + 0x5 + + + REG0_ADJ_6 + + 1.50% + 0x6 + + + REG0_ADJ_7 + + 1.75% + 0x7 + + + REG0_ADJ_8 + - 0.25% + 0x8 + + + REG0_ADJ_9 + - 0.50% + 0x9 + + + REG0_ADJ_10 + - 0.75% + 0xA + + + REG0_ADJ_11 + - 1.00% + 0xB + + + REG0_ADJ_12 + - 1.25% + 0xC + + + REG0_ADJ_13 + - 1.50% + 0xD + + + REG0_ADJ_14 + - 1.75% + 0xE + + + REG0_ADJ_15 + - 2.00% + 0xF + + + + + REG1_TARG + This bit field defines the target voltage for the vpu/gpu power domain. Single bit increments reflect 25mV core voltage steps. Not all steps will make sense to use either because of input supply limitations or load operation. + 9 + 5 + read-write + + + REG1_TARG_0 + Power gated off + 0 + + + REG1_TARG_1 + Target core voltage = 0.725V + 0x1 + + + REG1_TARG_2 + Target core voltage = 0.750V + 0x2 + + + REG1_TARG_3 + Target core voltage = 0.775V + 0x3 + + + REG1_TARG_16 + Target core voltage = 1.100V + 0x10 + + + REG1_TARG_30 + Target core voltage = 1.450V + 0x1E + + + REG1_TARG_31 + Power FET switched full on. No regulation. + 0x1F + + + + + REG1_ADJ + This bit field defines the adjustment bits to calibrate the target value of Reg1. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register. + 14 + 4 + read-write + + + REG1_ADJ_0 + No adjustment + 0 + + + REG1_ADJ_1 + + 0.25% + 0x1 + + + REG1_ADJ_2 + + 0.50% + 0x2 + + + REG1_ADJ_3 + + 0.75% + 0x3 + + + REG1_ADJ_4 + + 1.00% + 0x4 + + + REG1_ADJ_5 + + 1.25% + 0x5 + + + REG1_ADJ_6 + + 1.50% + 0x6 + + + REG1_ADJ_7 + + 1.75% + 0x7 + + + REG1_ADJ_8 + - 0.25% + 0x8 + + + REG1_ADJ_9 + - 0.50% + 0x9 + + + REG1_ADJ_10 + - 0.75% + 0xA + + + REG1_ADJ_11 + - 1.00% + 0xB + + + REG1_ADJ_12 + - 1.25% + 0xC + + + REG1_ADJ_13 + - 1.50% + 0xD + + + REG1_ADJ_14 + - 1.75% + 0xE + + + REG1_ADJ_15 + - 2.00% + 0xF + + + REG2_TARG This field defines the target voltage for the SOC power domain @@ -22858,6 +22947,95 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + + REG2_ADJ + This bit field defines the adjustment bits to calibrate the target value of Reg2. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register. + 23 + 4 + read-write + + + REG2_ADJ_0 + No adjustment + 0 + + + REG2_ADJ_1 + + 0.25% + 0x1 + + + REG2_ADJ_2 + + 0.50% + 0x2 + + + REG2_ADJ_3 + + 0.75% + 0x3 + + + REG2_ADJ_4 + + 1.00% + 0x4 + + + REG2_ADJ_5 + + 1.25% + 0x5 + + + REG2_ADJ_6 + + 1.50% + 0x6 + + + REG2_ADJ_7 + + 1.75% + 0x7 + + + REG2_ADJ_8 + - 0.25% + 0x8 + + + REG2_ADJ_9 + - 0.50% + 0x9 + + + REG2_ADJ_10 + - 0.75% + 0xA + + + REG2_ADJ_11 + - 1.00% + 0xB + + + REG2_ADJ_12 + - 1.25% + 0xC + + + REG2_ADJ_13 + - 1.50% + 0xD + + + REG2_ADJ_14 + - 1.75% + 0xE + + + REG2_ADJ_15 + - 2.00% + 0xF + + + RAMP_RATE Regulator voltage ramp rate. @@ -22949,6 +23127,228 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + + REG0_ADJ + This bit field defines the adjustment bits to calibrate the target value of Reg0. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register. + 5 + 4 + read-write + + + REG0_ADJ_0 + No adjustment + 0 + + + REG0_ADJ_1 + + 0.25% + 0x1 + + + REG0_ADJ_2 + + 0.50% + 0x2 + + + REG0_ADJ_3 + + 0.75% + 0x3 + + + REG0_ADJ_4 + + 1.00% + 0x4 + + + REG0_ADJ_5 + + 1.25% + 0x5 + + + REG0_ADJ_6 + + 1.50% + 0x6 + + + REG0_ADJ_7 + + 1.75% + 0x7 + + + REG0_ADJ_8 + - 0.25% + 0x8 + + + REG0_ADJ_9 + - 0.50% + 0x9 + + + REG0_ADJ_10 + - 0.75% + 0xA + + + REG0_ADJ_11 + - 1.00% + 0xB + + + REG0_ADJ_12 + - 1.25% + 0xC + + + REG0_ADJ_13 + - 1.50% + 0xD + + + REG0_ADJ_14 + - 1.75% + 0xE + + + REG0_ADJ_15 + - 2.00% + 0xF + + + + + REG1_TARG + This bit field defines the target voltage for the vpu/gpu power domain. Single bit increments reflect 25mV core voltage steps. Not all steps will make sense to use either because of input supply limitations or load operation. + 9 + 5 + read-write + + + REG1_TARG_0 + Power gated off + 0 + + + REG1_TARG_1 + Target core voltage = 0.725V + 0x1 + + + REG1_TARG_2 + Target core voltage = 0.750V + 0x2 + + + REG1_TARG_3 + Target core voltage = 0.775V + 0x3 + + + REG1_TARG_16 + Target core voltage = 1.100V + 0x10 + + + REG1_TARG_30 + Target core voltage = 1.450V + 0x1E + + + REG1_TARG_31 + Power FET switched full on. No regulation. + 0x1F + + + + + REG1_ADJ + This bit field defines the adjustment bits to calibrate the target value of Reg1. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register. + 14 + 4 + read-write + + + REG1_ADJ_0 + No adjustment + 0 + + + REG1_ADJ_1 + + 0.25% + 0x1 + + + REG1_ADJ_2 + + 0.50% + 0x2 + + + REG1_ADJ_3 + + 0.75% + 0x3 + + + REG1_ADJ_4 + + 1.00% + 0x4 + + + REG1_ADJ_5 + + 1.25% + 0x5 + + + REG1_ADJ_6 + + 1.50% + 0x6 + + + REG1_ADJ_7 + + 1.75% + 0x7 + + + REG1_ADJ_8 + - 0.25% + 0x8 + + + REG1_ADJ_9 + - 0.50% + 0x9 + + + REG1_ADJ_10 + - 0.75% + 0xA + + + REG1_ADJ_11 + - 1.00% + 0xB + + + REG1_ADJ_12 + - 1.25% + 0xC + + + REG1_ADJ_13 + - 1.50% + 0xD + + + REG1_ADJ_14 + - 1.75% + 0xE + + + REG1_ADJ_15 + - 2.00% + 0xF + + + REG2_TARG This field defines the target voltage for the SOC power domain @@ -22993,6 +23393,95 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + + REG2_ADJ + This bit field defines the adjustment bits to calibrate the target value of Reg2. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register. + 23 + 4 + read-write + + + REG2_ADJ_0 + No adjustment + 0 + + + REG2_ADJ_1 + + 0.25% + 0x1 + + + REG2_ADJ_2 + + 0.50% + 0x2 + + + REG2_ADJ_3 + + 0.75% + 0x3 + + + REG2_ADJ_4 + + 1.00% + 0x4 + + + REG2_ADJ_5 + + 1.25% + 0x5 + + + REG2_ADJ_6 + + 1.50% + 0x6 + + + REG2_ADJ_7 + + 1.75% + 0x7 + + + REG2_ADJ_8 + - 0.25% + 0x8 + + + REG2_ADJ_9 + - 0.50% + 0x9 + + + REG2_ADJ_10 + - 0.75% + 0xA + + + REG2_ADJ_11 + - 1.00% + 0xB + + + REG2_ADJ_12 + - 1.25% + 0xC + + + REG2_ADJ_13 + - 1.50% + 0xD + + + REG2_ADJ_14 + - 1.75% + 0xE + + + REG2_ADJ_15 + - 2.00% + 0xF + + + RAMP_RATE Regulator voltage ramp rate. @@ -24317,6 +24806,120 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + + LVDS2_CLK_SEL + This field selects the clk to be routed to anaclk2/2b.Not related to PMU. + 5 + 5 + read-write + + + ARM_PLL + Arm PLL + 0 + + + SYS_PLL + System PLL + 0x1 + + + PFD4 + ref_pfd4_clk == pll2_pfd0_clk + 0x2 + + + PFD5 + ref_pfd5_clk == pll2_pfd1_clk + 0x3 + + + PFD6 + ref_pfd6_clk == pll2_pfd2_clk + 0x4 + + + PFD7 + ref_pfd7_clk == pll2_pfd3_clk + 0x5 + + + AUDIO_PLL + Audio PLL + 0x6 + + + VIDEO_PLL + Video PLL + 0x7 + + + MLB_PLL + MLB PLL + 0x8 + + + ETHERNET_REF + ethernet ref clock (ENET_PLL) + 0x9 + + + PCIE_REF + PCIe ref clock (125M) + 0xA + + + SATA_REF + SATA ref clock (100M) + 0xB + + + USB1_PLL + USB1 PLL clock + 0xC + + + USB2_PLL + USB2 PLL clock + 0xD + + + PFD0 + ref_pfd0_clk == pll3_pfd0_clk + 0xE + + + PFD1 + ref_pfd1_clk == pll3_pfd1_clk + 0xF + + + PFD2 + ref_pfd2_clk == pll3_pfd2_clk + 0x10 + + + PFD3 + ref_pfd3_clk == pll3_pfd3_clk + 0x11 + + + XTAL + xtal (24M) + 0x12 + + + LVDS1 + LVDS1 (loopback) + 0x13 + + + LVDS2 + LVDS2 (not useful) + 0x14 + + + LVDSCLK1_OBEN This enables the LVDS output buffer for anaclk1/1b @@ -24324,6 +24927,13 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 1 read-write + + LVDSCLK2_OBEN + This enables the LVDS output buffer for anaclk2/2b + 11 + 1 + read-write + LVDSCLK1_IBEN This enables the LVDS input buffer for anaclk1/1b @@ -24331,6 +24941,13 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 1 read-write + + LVDSCLK2_IBEN + This enables the LVDS input buffer for anaclk2/2b + 13 + 1 + read-write + PFD_480_AUTOGATE_EN This enables a feature that will clkgate (reset) all PFD_480 clocks anytime the USB1_PLL_480 is unlocked or powered off @@ -24485,6 +25102,120 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + + LVDS2_CLK_SEL + This field selects the clk to be routed to anaclk2/2b.Not related to PMU. + 5 + 5 + read-write + + + ARM_PLL + Arm PLL + 0 + + + SYS_PLL + System PLL + 0x1 + + + PFD4 + ref_pfd4_clk == pll2_pfd0_clk + 0x2 + + + PFD5 + ref_pfd5_clk == pll2_pfd1_clk + 0x3 + + + PFD6 + ref_pfd6_clk == pll2_pfd2_clk + 0x4 + + + PFD7 + ref_pfd7_clk == pll2_pfd3_clk + 0x5 + + + AUDIO_PLL + Audio PLL + 0x6 + + + VIDEO_PLL + Video PLL + 0x7 + + + MLB_PLL + MLB PLL + 0x8 + + + ETHERNET_REF + ethernet ref clock (ENET_PLL) + 0x9 + + + PCIE_REF + PCIe ref clock (125M) + 0xA + + + SATA_REF + SATA ref clock (100M) + 0xB + + + USB1_PLL + USB1 PLL clock + 0xC + + + USB2_PLL + USB2 PLL clock + 0xD + + + PFD0 + ref_pfd0_clk == pll3_pfd0_clk + 0xE + + + PFD1 + ref_pfd1_clk == pll3_pfd1_clk + 0xF + + + PFD2 + ref_pfd2_clk == pll3_pfd2_clk + 0x10 + + + PFD3 + ref_pfd3_clk == pll3_pfd3_clk + 0x11 + + + XTAL + xtal (24M) + 0x12 + + + LVDS1 + LVDS1 (loopback) + 0x13 + + + LVDS2 + LVDS2 (not useful) + 0x14 + + + LVDSCLK1_OBEN This enables the LVDS output buffer for anaclk1/1b @@ -24492,6 +25223,13 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 1 read-write + + LVDSCLK2_OBEN + This enables the LVDS output buffer for anaclk2/2b + 11 + 1 + read-write + LVDSCLK1_IBEN This enables the LVDS input buffer for anaclk1/1b @@ -24499,6 +25237,13 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 1 read-write + + LVDSCLK2_IBEN + This enables the LVDS input buffer for anaclk2/2b + 13 + 1 + read-write + PFD_480_AUTOGATE_EN This enables a feature that will clkgate (reset) all PFD_480 clocks anytime the USB1_PLL_480 is unlocked or powered off @@ -24653,6 +25398,120 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + + LVDS2_CLK_SEL + This field selects the clk to be routed to anaclk2/2b.Not related to PMU. + 5 + 5 + read-write + + + ARM_PLL + Arm PLL + 0 + + + SYS_PLL + System PLL + 0x1 + + + PFD4 + ref_pfd4_clk == pll2_pfd0_clk + 0x2 + + + PFD5 + ref_pfd5_clk == pll2_pfd1_clk + 0x3 + + + PFD6 + ref_pfd6_clk == pll2_pfd2_clk + 0x4 + + + PFD7 + ref_pfd7_clk == pll2_pfd3_clk + 0x5 + + + AUDIO_PLL + Audio PLL + 0x6 + + + VIDEO_PLL + Video PLL + 0x7 + + + MLB_PLL + MLB PLL + 0x8 + + + ETHERNET_REF + ethernet ref clock (ENET_PLL) + 0x9 + + + PCIE_REF + PCIe ref clock (125M) + 0xA + + + SATA_REF + SATA ref clock (100M) + 0xB + + + USB1_PLL + USB1 PLL clock + 0xC + + + USB2_PLL + USB2 PLL clock + 0xD + + + PFD0 + ref_pfd0_clk == pll3_pfd0_clk + 0xE + + + PFD1 + ref_pfd1_clk == pll3_pfd1_clk + 0xF + + + PFD2 + ref_pfd2_clk == pll3_pfd2_clk + 0x10 + + + PFD3 + ref_pfd3_clk == pll3_pfd3_clk + 0x11 + + + XTAL + xtal (24M) + 0x12 + + + LVDS1 + LVDS1 (loopback) + 0x13 + + + LVDS2 + LVDS2 (not useful) + 0x14 + + + LVDSCLK1_OBEN This enables the LVDS output buffer for anaclk1/1b @@ -24660,6 +25519,13 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 1 read-write + + LVDSCLK2_OBEN + This enables the LVDS output buffer for anaclk2/2b + 11 + 1 + read-write + LVDSCLK1_IBEN This enables the LVDS input buffer for anaclk1/1b @@ -24667,6 +25533,13 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 1 read-write + + LVDSCLK2_IBEN + This enables the LVDS input buffer for anaclk2/2b + 13 + 1 + read-write + PFD_480_AUTOGATE_EN This enables a feature that will clkgate (reset) all PFD_480 clocks anytime the USB1_PLL_480 is unlocked or powered off @@ -24821,6 +25694,120 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + + LVDS2_CLK_SEL + This field selects the clk to be routed to anaclk2/2b.Not related to PMU. + 5 + 5 + read-write + + + ARM_PLL + Arm PLL + 0 + + + SYS_PLL + System PLL + 0x1 + + + PFD4 + ref_pfd4_clk == pll2_pfd0_clk + 0x2 + + + PFD5 + ref_pfd5_clk == pll2_pfd1_clk + 0x3 + + + PFD6 + ref_pfd6_clk == pll2_pfd2_clk + 0x4 + + + PFD7 + ref_pfd7_clk == pll2_pfd3_clk + 0x5 + + + AUDIO_PLL + Audio PLL + 0x6 + + + VIDEO_PLL + Video PLL + 0x7 + + + MLB_PLL + MLB PLL + 0x8 + + + ETHERNET_REF + ethernet ref clock (ENET_PLL) + 0x9 + + + PCIE_REF + PCIe ref clock (125M) + 0xA + + + SATA_REF + SATA ref clock (100M) + 0xB + + + USB1_PLL + USB1 PLL clock + 0xC + + + USB2_PLL + USB2 PLL clock + 0xD + + + PFD0 + ref_pfd0_clk == pll3_pfd0_clk + 0xE + + + PFD1 + ref_pfd1_clk == pll3_pfd1_clk + 0xF + + + PFD2 + ref_pfd2_clk == pll3_pfd2_clk + 0x10 + + + PFD3 + ref_pfd3_clk == pll3_pfd3_clk + 0x11 + + + XTAL + xtal (24M) + 0x12 + + + LVDS1 + LVDS1 (loopback) + 0x13 + + + LVDS2 + LVDS2 (not useful) + 0x14 + + + LVDSCLK1_OBEN This enables the LVDS output buffer for anaclk1/1b @@ -24828,6 +25815,13 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 1 read-write + + LVDSCLK2_OBEN + This enables the LVDS output buffer for anaclk2/2b + 11 + 1 + read-write + LVDSCLK1_IBEN This enables the LVDS input buffer for anaclk1/1b @@ -24835,6 +25829,13 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 1 read-write + + LVDSCLK2_IBEN + This enables the LVDS input buffer for anaclk2/2b + 13 + 1 + read-write + PFD_480_AUTOGATE_EN This enables a feature that will clkgate (reset) all PFD_480 clocks anytime the USB1_PLL_480 is unlocked or powered off @@ -24947,6 +25948,46 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 1 read-write + + REG1_BO_OFFSET + This field defines the brown out voltage offset for the xPU power domain + 8 + 3 + read-only + + + REG1_BO_OFFSET_4 + Brownout offset = 0.100V + 0x4 + + + REG1_BO_OFFSET_7 + Brownout offset = 0.175V + 0x7 + + + + + REG1_BO_STATUS + Reg1 brownout status bit. + 11 + 1 + read-only + + + REG1_BO_STATUS_1 + Brownout, supply is below target minus brownout offset. + 0x1 + + + + + REG1_ENABLE_BO + Enables the brownout detection. + 13 + 1 + read-write + AUDIO_DIV_LSB LSB of Post-divider for Audio PLL @@ -25054,6 +26095,35 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + + REG1_STEP_TIME + Number of clock periods (24MHz clock). + 26 + 2 + read-write + + + 64_CLOCKS + 64 + 0 + + + 128_CLOCKS + 128 + 0x1 + + + 256_CLOCKS + 256 + 0x2 + + + 512_CLOCKS + 512 + 0x3 + + + REG2_STEP_TIME Number of clock periods (24MHz clock). @@ -25170,6 +26240,46 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 1 read-write + + REG1_BO_OFFSET + This field defines the brown out voltage offset for the xPU power domain + 8 + 3 + read-only + + + REG1_BO_OFFSET_4 + Brownout offset = 0.100V + 0x4 + + + REG1_BO_OFFSET_7 + Brownout offset = 0.175V + 0x7 + + + + + REG1_BO_STATUS + Reg1 brownout status bit. + 11 + 1 + read-only + + + REG1_BO_STATUS_1 + Brownout, supply is below target minus brownout offset. + 0x1 + + + + + REG1_ENABLE_BO + Enables the brownout detection. + 13 + 1 + read-write + AUDIO_DIV_LSB LSB of Post-divider for Audio PLL @@ -25277,6 +26387,35 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + + REG1_STEP_TIME + Number of clock periods (24MHz clock). + 26 + 2 + read-write + + + 64_CLOCKS + 64 + 0 + + + 128_CLOCKS + 128 + 0x1 + + + 256_CLOCKS + 256 + 0x2 + + + 512_CLOCKS + 512 + 0x3 + + + REG2_STEP_TIME Number of clock periods (24MHz clock). @@ -25393,6 +26532,46 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 1 read-write + + REG1_BO_OFFSET + This field defines the brown out voltage offset for the xPU power domain + 8 + 3 + read-only + + + REG1_BO_OFFSET_4 + Brownout offset = 0.100V + 0x4 + + + REG1_BO_OFFSET_7 + Brownout offset = 0.175V + 0x7 + + + + + REG1_BO_STATUS + Reg1 brownout status bit. + 11 + 1 + read-only + + + REG1_BO_STATUS_1 + Brownout, supply is below target minus brownout offset. + 0x1 + + + + + REG1_ENABLE_BO + Enables the brownout detection. + 13 + 1 + read-write + AUDIO_DIV_LSB LSB of Post-divider for Audio PLL @@ -25500,6 +26679,35 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + + REG1_STEP_TIME + Number of clock periods (24MHz clock). + 26 + 2 + read-write + + + 64_CLOCKS + 64 + 0 + + + 128_CLOCKS + 128 + 0x1 + + + 256_CLOCKS + 256 + 0x2 + + + 512_CLOCKS + 512 + 0x3 + + + REG2_STEP_TIME Number of clock periods (24MHz clock). @@ -25616,6 +26824,46 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 1 read-write + + REG1_BO_OFFSET + This field defines the brown out voltage offset for the xPU power domain + 8 + 3 + read-only + + + REG1_BO_OFFSET_4 + Brownout offset = 0.100V + 0x4 + + + REG1_BO_OFFSET_7 + Brownout offset = 0.175V + 0x7 + + + + + REG1_BO_STATUS + Reg1 brownout status bit. + 11 + 1 + read-only + + + REG1_BO_STATUS_1 + Brownout, supply is below target minus brownout offset. + 0x1 + + + + + REG1_ENABLE_BO + Enables the brownout detection. + 13 + 1 + read-write + AUDIO_DIV_LSB LSB of Post-divider for Audio PLL @@ -25723,6 +26971,35 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + + REG1_STEP_TIME + Number of clock periods (24MHz clock). + 26 + 2 + read-write + + + 64_CLOCKS + 64 + 0 + + + 128_CLOCKS + 128 + 0x1 + + + 256_CLOCKS + 256 + 0x2 + + + 512_CLOCKS + 512 + 0x3 + + + REG2_STEP_TIME Number of clock periods (24MHz clock). @@ -25797,6 +27074,14 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0x2A0 registers + + TEMP_LOW_HIGH + 63 + + + TEMP_PANIC + 64 + TEMPSENSE0 @@ -27971,64 +29256,23 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0x260 32 read-only - 0x640000 + 0x6A0001 0xFFFFFFFF - MINOR - MINOR lower byte - Read-only value representing a minor silicon revision. + SILICON_REVISION + Chip silicon revision 0 - 8 + 32 read-only - MINOR_0 - silicon revision x.0 - 0 - - - MINOR_1 - silicon revision x.1 - 0x1 - - - MINOR_2 - silicon revision x.2 - 0x2 - - - MINOR_3 - silicon revision x.3 - 0x3 + SILICON_REVISION_6946817 + Silicon revision 1.1 + 0x6A0001 - - MAJOR_LOWER - MAJOR lower byte - Read-only value representing a major silicon revision. - 8 - 8 - read-only - - - MAJOR_LOWER_0 - silicon revision 1.x - 0 - - - MAJOR_LOWER_1 - silicon revision 2.x - 0x1 - - - - - MAJOR_UPPER - MAJOR upper byte-Read-only value representing the chip type. - 16 - 8 - read-only - @@ -29240,7 +30484,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0x270 32 read-write - 0x4009 + 0x4001 0xFFFFFFFF @@ -29262,13 +30506,6 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - - RC_OSC_PROG - RC osc. tuning values. - 1 - 3 - read-write - OSC_SEL Select the source for the 24MHz clock. @@ -29411,6 +30648,13 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 1 read-write + + GPU_PWRGATE + GPU power gate control. Used as software mask. Set to zero to force ungated. + 18 + 1 + read-write + @@ -29419,7 +30663,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0x274 32 read-write - 0x4009 + 0x4001 0xFFFFFFFF @@ -29441,13 +30685,6 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - - RC_OSC_PROG - RC osc. tuning values. - 1 - 3 - read-write - OSC_SEL Select the source for the 24MHz clock. @@ -29590,6 +30827,13 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 1 read-write + + GPU_PWRGATE + GPU power gate control. Used as software mask. Set to zero to force ungated. + 18 + 1 + read-write + @@ -29598,7 +30842,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0x278 32 read-write - 0x4009 + 0x4001 0xFFFFFFFF @@ -29620,13 +30864,6 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - - RC_OSC_PROG - RC osc. tuning values. - 1 - 3 - read-write - OSC_SEL Select the source for the 24MHz clock. @@ -29769,6 +31006,13 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 1 read-write + + GPU_PWRGATE + GPU power gate control. Used as software mask. Set to zero to force ungated. + 18 + 1 + read-write + @@ -29777,7 +31021,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0x27C 32 read-write - 0x4009 + 0x4001 0xFFFFFFFF @@ -29799,13 +31043,6 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - - RC_OSC_PROG - RC osc. tuning values. - 1 - 3 - read-write - OSC_SEL Select the source for the 24MHz clock. @@ -29948,6 +31185,13 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 1 read-write + + GPU_PWRGATE + GPU power gate control. Used as software mask. Set to zero to force ungated. + 18 + 1 + read-write + @@ -30329,7 +31573,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. COUNT_1M_TRG - The target count used to tune the RC OSC frequency + The target count used to tune the 1MHz clock frequency 0 12 read-write @@ -30343,14 +31587,14 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. MUX_1M - Mux the corrected or uncorrected 1MHz clock to the output. + Mux the corrected or uncorrected 1MHz clock to the output 17 1 read-write CLK_1M_ERR_FL - Flag indicates that the count_1m count wasn't reached within 1 32KHz period + Flag indicates that the count_1m count wasn't reached within 1 32kHz period 31 1 read-write @@ -30368,7 +31612,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. COUNT_1M_TRG - The target count used to tune the RC OSC frequency + The target count used to tune the 1MHz clock frequency 0 12 read-write @@ -30382,14 +31626,14 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. MUX_1M - Mux the corrected or uncorrected 1MHz clock to the output. + Mux the corrected or uncorrected 1MHz clock to the output 17 1 read-write CLK_1M_ERR_FL - Flag indicates that the count_1m count wasn't reached within 1 32KHz period + Flag indicates that the count_1m count wasn't reached within 1 32kHz period 31 1 read-write @@ -30407,7 +31651,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. COUNT_1M_TRG - The target count used to tune the RC OSC frequency + The target count used to tune the 1MHz clock frequency 0 12 read-write @@ -30421,14 +31665,14 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. MUX_1M - Mux the corrected or uncorrected 1MHz clock to the output. + Mux the corrected or uncorrected 1MHz clock to the output 17 1 read-write CLK_1M_ERR_FL - Flag indicates that the count_1m count wasn't reached within 1 32KHz period + Flag indicates that the count_1m count wasn't reached within 1 32kHz period 31 1 read-write @@ -30446,7 +31690,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. COUNT_1M_TRG - The target count used to tune the RC OSC frequency + The target count used to tune the 1MHz clock frequency 0 12 read-write @@ -30460,14 +31704,14 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. MUX_1M - Mux the corrected or uncorrected 1MHz clock to the output. + Mux the corrected or uncorrected 1MHz clock to the output 17 1 read-write CLK_1M_ERR_FL - Flag indicates that the count_1m count wasn't reached within 1 32KHz period + Flag indicates that the count_1m count wasn't reached within 1 32kHz period 31 1 read-write @@ -32913,7 +34157,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0x80 32 read-only - 0x4020000 + 0x4030000 0xFFFFFFFF @@ -34522,7 +35766,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. BASIC_SETTING - PS Input Buffer Address + no description available 0 32 read-write @@ -34577,8 +35821,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - PS_INPUT_BUFFER_ADDR - PS Input Buffer Address + PRE_CHARGE_TIME + no description available 0x10 32 read-write @@ -34587,22 +35831,10 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. PRE_CHARGE_TIME - Auto Measure + Before detection, the top screen needs some time before being pulled up to a high voltage. 0 32 read-write - - - PRE_CHARGE_TIME_0 - Disable Auto Measure - 0 - - - PRE_CHARGE_TIME_1 - Auto Measure - 0x1 - - @@ -34743,9 +35975,14 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. MEASURE_INT_EN_0 - Disable measure + Disable measure interrupt 0 + + MEASURE_INT_EN_1 + Enable measure interrupt + 0x1 + @@ -40291,10 +41528,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - 32 - 0x1 - 3,2,1,0,7,6,5,4,11,10,9,8,15,14,13,12,19,18,17,16,23,22,21,20,27,26,25,24,31,30,29,28 - DCHPRI%s + DCHPRI3 Channel n Priority Register 0x100 8 @@ -40356,6 +41590,1959 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + + DCHPRI2 + Channel n Priority Register + 0x101 + 8 + read-write + 0x2 + 0xFF + + + CHPRI + Channel n Arbitration Priority + 0 + 4 + read-write + + + GRPPRI + Channel n Current Group Priority + 4 + 2 + read-only + + + DPA + Disable Preempt Ability. This field resets to 0. + 6 + 1 + read-write + + + DPA_0 + Channel n can suspend a lower priority channel. + 0 + + + DPA_1 + Channel n cannot suspend any channel, regardless of channel priority. + 0x1 + + + + + ECP + Enable Channel Preemption. This field resets to 0. + 7 + 1 + read-write + + + ECP_0 + Channel n cannot be suspended by a higher priority channel's service request. + 0 + + + ECP_1 + Channel n can be temporarily suspended by the service request of a higher priority channel. + 0x1 + + + + + + + DCHPRI1 + Channel n Priority Register + 0x102 + 8 + read-write + 0x1 + 0xFF + + + CHPRI + Channel n Arbitration Priority + 0 + 4 + read-write + + + GRPPRI + Channel n Current Group Priority + 4 + 2 + read-only + + + DPA + Disable Preempt Ability. This field resets to 0. + 6 + 1 + read-write + + + DPA_0 + Channel n can suspend a lower priority channel. + 0 + + + DPA_1 + Channel n cannot suspend any channel, regardless of channel priority. + 0x1 + + + + + ECP + Enable Channel Preemption. This field resets to 0. + 7 + 1 + read-write + + + ECP_0 + Channel n cannot be suspended by a higher priority channel's service request. + 0 + + + ECP_1 + Channel n can be temporarily suspended by the service request of a higher priority channel. + 0x1 + + + + + + + DCHPRI0 + Channel n Priority Register + 0x103 + 8 + read-write + 0 + 0xFF + + + CHPRI + Channel n Arbitration Priority + 0 + 4 + read-write + + + GRPPRI + Channel n Current Group Priority + 4 + 2 + read-only + + + DPA + Disable Preempt Ability. This field resets to 0. + 6 + 1 + read-write + + + DPA_0 + Channel n can suspend a lower priority channel. + 0 + + + DPA_1 + Channel n cannot suspend any channel, regardless of channel priority. + 0x1 + + + + + ECP + Enable Channel Preemption. This field resets to 0. + 7 + 1 + read-write + + + ECP_0 + Channel n cannot be suspended by a higher priority channel's service request. + 0 + + + ECP_1 + Channel n can be temporarily suspended by the service request of a higher priority channel. + 0x1 + + + + + + + DCHPRI7 + Channel n Priority Register + 0x104 + 8 + read-write + 0x7 + 0xFF + + + CHPRI + Channel n Arbitration Priority + 0 + 4 + read-write + + + GRPPRI + Channel n Current Group Priority + 4 + 2 + read-only + + + DPA + Disable Preempt Ability. This field resets to 0. + 6 + 1 + read-write + + + DPA_0 + Channel n can suspend a lower priority channel. + 0 + + + DPA_1 + Channel n cannot suspend any channel, regardless of channel priority. + 0x1 + + + + + ECP + Enable Channel Preemption. This field resets to 0. + 7 + 1 + read-write + + + ECP_0 + Channel n cannot be suspended by a higher priority channel's service request. + 0 + + + ECP_1 + Channel n can be temporarily suspended by the service request of a higher priority channel. + 0x1 + + + + + + + DCHPRI6 + Channel n Priority Register + 0x105 + 8 + read-write + 0x6 + 0xFF + + + CHPRI + Channel n Arbitration Priority + 0 + 4 + read-write + + + GRPPRI + Channel n Current Group Priority + 4 + 2 + read-only + + + DPA + Disable Preempt Ability. This field resets to 0. + 6 + 1 + read-write + + + DPA_0 + Channel n can suspend a lower priority channel. + 0 + + + DPA_1 + Channel n cannot suspend any channel, regardless of channel priority. + 0x1 + + + + + ECP + Enable Channel Preemption. This field resets to 0. + 7 + 1 + read-write + + + ECP_0 + Channel n cannot be suspended by a higher priority channel's service request. + 0 + + + ECP_1 + Channel n can be temporarily suspended by the service request of a higher priority channel. + 0x1 + + + + + + + DCHPRI5 + Channel n Priority Register + 0x106 + 8 + read-write + 0x5 + 0xFF + + + CHPRI + Channel n Arbitration Priority + 0 + 4 + read-write + + + GRPPRI + Channel n Current Group Priority + 4 + 2 + read-only + + + DPA + Disable Preempt Ability. This field resets to 0. + 6 + 1 + read-write + + + DPA_0 + Channel n can suspend a lower priority channel. + 0 + + + DPA_1 + Channel n cannot suspend any channel, regardless of channel priority. + 0x1 + + + + + ECP + Enable Channel Preemption. This field resets to 0. + 7 + 1 + read-write + + + ECP_0 + Channel n cannot be suspended by a higher priority channel's service request. + 0 + + + ECP_1 + Channel n can be temporarily suspended by the service request of a higher priority channel. + 0x1 + + + + + + + DCHPRI4 + Channel n Priority Register + 0x107 + 8 + read-write + 0x4 + 0xFF + + + CHPRI + Channel n Arbitration Priority + 0 + 4 + read-write + + + GRPPRI + Channel n Current Group Priority + 4 + 2 + read-only + + + DPA + Disable Preempt Ability. This field resets to 0. + 6 + 1 + read-write + + + DPA_0 + Channel n can suspend a lower priority channel. + 0 + + + DPA_1 + Channel n cannot suspend any channel, regardless of channel priority. + 0x1 + + + + + ECP + Enable Channel Preemption. This field resets to 0. + 7 + 1 + read-write + + + ECP_0 + Channel n cannot be suspended by a higher priority channel's service request. + 0 + + + ECP_1 + Channel n can be temporarily suspended by the service request of a higher priority channel. + 0x1 + + + + + + + DCHPRI11 + Channel n Priority Register + 0x108 + 8 + read-write + 0xB + 0xFF + + + CHPRI + Channel n Arbitration Priority + 0 + 4 + read-write + + + GRPPRI + Channel n Current Group Priority + 4 + 2 + read-only + + + DPA + Disable Preempt Ability. This field resets to 0. + 6 + 1 + read-write + + + DPA_0 + Channel n can suspend a lower priority channel. + 0 + + + DPA_1 + Channel n cannot suspend any channel, regardless of channel priority. + 0x1 + + + + + ECP + Enable Channel Preemption. This field resets to 0. + 7 + 1 + read-write + + + ECP_0 + Channel n cannot be suspended by a higher priority channel's service request. + 0 + + + ECP_1 + Channel n can be temporarily suspended by the service request of a higher priority channel. + 0x1 + + + + + + + DCHPRI10 + Channel n Priority Register + 0x109 + 8 + read-write + 0xA + 0xFF + + + CHPRI + Channel n Arbitration Priority + 0 + 4 + read-write + + + GRPPRI + Channel n Current Group Priority + 4 + 2 + read-only + + + DPA + Disable Preempt Ability. This field resets to 0. + 6 + 1 + read-write + + + DPA_0 + Channel n can suspend a lower priority channel. + 0 + + + DPA_1 + Channel n cannot suspend any channel, regardless of channel priority. + 0x1 + + + + + ECP + Enable Channel Preemption. This field resets to 0. + 7 + 1 + read-write + + + ECP_0 + Channel n cannot be suspended by a higher priority channel's service request. + 0 + + + ECP_1 + Channel n can be temporarily suspended by the service request of a higher priority channel. + 0x1 + + + + + + + DCHPRI9 + Channel n Priority Register + 0x10A + 8 + read-write + 0x9 + 0xFF + + + CHPRI + Channel n Arbitration Priority + 0 + 4 + read-write + + + GRPPRI + Channel n Current Group Priority + 4 + 2 + read-only + + + DPA + Disable Preempt Ability. This field resets to 0. + 6 + 1 + read-write + + + DPA_0 + Channel n can suspend a lower priority channel. + 0 + + + DPA_1 + Channel n cannot suspend any channel, regardless of channel priority. + 0x1 + + + + + ECP + Enable Channel Preemption. This field resets to 0. + 7 + 1 + read-write + + + ECP_0 + Channel n cannot be suspended by a higher priority channel's service request. + 0 + + + ECP_1 + Channel n can be temporarily suspended by the service request of a higher priority channel. + 0x1 + + + + + + + DCHPRI8 + Channel n Priority Register + 0x10B + 8 + read-write + 0x8 + 0xFF + + + CHPRI + Channel n Arbitration Priority + 0 + 4 + read-write + + + GRPPRI + Channel n Current Group Priority + 4 + 2 + read-only + + + DPA + Disable Preempt Ability. This field resets to 0. + 6 + 1 + read-write + + + DPA_0 + Channel n can suspend a lower priority channel. + 0 + + + DPA_1 + Channel n cannot suspend any channel, regardless of channel priority. + 0x1 + + + + + ECP + Enable Channel Preemption. This field resets to 0. + 7 + 1 + read-write + + + ECP_0 + Channel n cannot be suspended by a higher priority channel's service request. + 0 + + + ECP_1 + Channel n can be temporarily suspended by the service request of a higher priority channel. + 0x1 + + + + + + + DCHPRI15 + Channel n Priority Register + 0x10C + 8 + read-write + 0xF + 0xFF + + + CHPRI + Channel n Arbitration Priority + 0 + 4 + read-write + + + GRPPRI + Channel n Current Group Priority + 4 + 2 + read-only + + + DPA + Disable Preempt Ability. This field resets to 0. + 6 + 1 + read-write + + + DPA_0 + Channel n can suspend a lower priority channel. + 0 + + + DPA_1 + Channel n cannot suspend any channel, regardless of channel priority. + 0x1 + + + + + ECP + Enable Channel Preemption. This field resets to 0. + 7 + 1 + read-write + + + ECP_0 + Channel n cannot be suspended by a higher priority channel's service request. + 0 + + + ECP_1 + Channel n can be temporarily suspended by the service request of a higher priority channel. + 0x1 + + + + + + + DCHPRI14 + Channel n Priority Register + 0x10D + 8 + read-write + 0xE + 0xFF + + + CHPRI + Channel n Arbitration Priority + 0 + 4 + read-write + + + GRPPRI + Channel n Current Group Priority + 4 + 2 + read-only + + + DPA + Disable Preempt Ability. This field resets to 0. + 6 + 1 + read-write + + + DPA_0 + Channel n can suspend a lower priority channel. + 0 + + + DPA_1 + Channel n cannot suspend any channel, regardless of channel priority. + 0x1 + + + + + ECP + Enable Channel Preemption. This field resets to 0. + 7 + 1 + read-write + + + ECP_0 + Channel n cannot be suspended by a higher priority channel's service request. + 0 + + + ECP_1 + Channel n can be temporarily suspended by the service request of a higher priority channel. + 0x1 + + + + + + + DCHPRI13 + Channel n Priority Register + 0x10E + 8 + read-write + 0xD + 0xFF + + + CHPRI + Channel n Arbitration Priority + 0 + 4 + read-write + + + GRPPRI + Channel n Current Group Priority + 4 + 2 + read-only + + + DPA + Disable Preempt Ability. This field resets to 0. + 6 + 1 + read-write + + + DPA_0 + Channel n can suspend a lower priority channel. + 0 + + + DPA_1 + Channel n cannot suspend any channel, regardless of channel priority. + 0x1 + + + + + ECP + Enable Channel Preemption. This field resets to 0. + 7 + 1 + read-write + + + ECP_0 + Channel n cannot be suspended by a higher priority channel's service request. + 0 + + + ECP_1 + Channel n can be temporarily suspended by the service request of a higher priority channel. + 0x1 + + + + + + + DCHPRI12 + Channel n Priority Register + 0x10F + 8 + read-write + 0xC + 0xFF + + + CHPRI + Channel n Arbitration Priority + 0 + 4 + read-write + + + GRPPRI + Channel n Current Group Priority + 4 + 2 + read-only + + + DPA + Disable Preempt Ability. This field resets to 0. + 6 + 1 + read-write + + + DPA_0 + Channel n can suspend a lower priority channel. + 0 + + + DPA_1 + Channel n cannot suspend any channel, regardless of channel priority. + 0x1 + + + + + ECP + Enable Channel Preemption. This field resets to 0. + 7 + 1 + read-write + + + ECP_0 + Channel n cannot be suspended by a higher priority channel's service request. + 0 + + + ECP_1 + Channel n can be temporarily suspended by the service request of a higher priority channel. + 0x1 + + + + + + + DCHPRI19 + Channel n Priority Register + 0x110 + 8 + read-write + 0x13 + 0xFF + + + CHPRI + Channel n Arbitration Priority + 0 + 4 + read-write + + + GRPPRI + Channel n Current Group Priority + 4 + 2 + read-only + + + DPA + Disable Preempt Ability. This field resets to 0. + 6 + 1 + read-write + + + DPA_0 + Channel n can suspend a lower priority channel. + 0 + + + DPA_1 + Channel n cannot suspend any channel, regardless of channel priority. + 0x1 + + + + + ECP + Enable Channel Preemption. This field resets to 0. + 7 + 1 + read-write + + + ECP_0 + Channel n cannot be suspended by a higher priority channel's service request. + 0 + + + ECP_1 + Channel n can be temporarily suspended by the service request of a higher priority channel. + 0x1 + + + + + + + DCHPRI18 + Channel n Priority Register + 0x111 + 8 + read-write + 0x12 + 0xFF + + + CHPRI + Channel n Arbitration Priority + 0 + 4 + read-write + + + GRPPRI + Channel n Current Group Priority + 4 + 2 + read-only + + + DPA + Disable Preempt Ability. This field resets to 0. + 6 + 1 + read-write + + + DPA_0 + Channel n can suspend a lower priority channel. + 0 + + + DPA_1 + Channel n cannot suspend any channel, regardless of channel priority. + 0x1 + + + + + ECP + Enable Channel Preemption. This field resets to 0. + 7 + 1 + read-write + + + ECP_0 + Channel n cannot be suspended by a higher priority channel's service request. + 0 + + + ECP_1 + Channel n can be temporarily suspended by the service request of a higher priority channel. + 0x1 + + + + + + + DCHPRI17 + Channel n Priority Register + 0x112 + 8 + read-write + 0x11 + 0xFF + + + CHPRI + Channel n Arbitration Priority + 0 + 4 + read-write + + + GRPPRI + Channel n Current Group Priority + 4 + 2 + read-only + + + DPA + Disable Preempt Ability. This field resets to 0. + 6 + 1 + read-write + + + DPA_0 + Channel n can suspend a lower priority channel. + 0 + + + DPA_1 + Channel n cannot suspend any channel, regardless of channel priority. + 0x1 + + + + + ECP + Enable Channel Preemption. This field resets to 0. + 7 + 1 + read-write + + + ECP_0 + Channel n cannot be suspended by a higher priority channel's service request. + 0 + + + ECP_1 + Channel n can be temporarily suspended by the service request of a higher priority channel. + 0x1 + + + + + + + DCHPRI16 + Channel n Priority Register + 0x113 + 8 + read-write + 0x10 + 0xFF + + + CHPRI + Channel n Arbitration Priority + 0 + 4 + read-write + + + GRPPRI + Channel n Current Group Priority + 4 + 2 + read-only + + + DPA + Disable Preempt Ability. This field resets to 0. + 6 + 1 + read-write + + + DPA_0 + Channel n can suspend a lower priority channel. + 0 + + + DPA_1 + Channel n cannot suspend any channel, regardless of channel priority. + 0x1 + + + + + ECP + Enable Channel Preemption. This field resets to 0. + 7 + 1 + read-write + + + ECP_0 + Channel n cannot be suspended by a higher priority channel's service request. + 0 + + + ECP_1 + Channel n can be temporarily suspended by the service request of a higher priority channel. + 0x1 + + + + + + + DCHPRI23 + Channel n Priority Register + 0x114 + 8 + read-write + 0x17 + 0xFF + + + CHPRI + Channel n Arbitration Priority + 0 + 4 + read-write + + + GRPPRI + Channel n Current Group Priority + 4 + 2 + read-only + + + DPA + Disable Preempt Ability. This field resets to 0. + 6 + 1 + read-write + + + DPA_0 + Channel n can suspend a lower priority channel. + 0 + + + DPA_1 + Channel n cannot suspend any channel, regardless of channel priority. + 0x1 + + + + + ECP + Enable Channel Preemption. This field resets to 0. + 7 + 1 + read-write + + + ECP_0 + Channel n cannot be suspended by a higher priority channel's service request. + 0 + + + ECP_1 + Channel n can be temporarily suspended by the service request of a higher priority channel. + 0x1 + + + + + + + DCHPRI22 + Channel n Priority Register + 0x115 + 8 + read-write + 0x16 + 0xFF + + + CHPRI + Channel n Arbitration Priority + 0 + 4 + read-write + + + GRPPRI + Channel n Current Group Priority + 4 + 2 + read-only + + + DPA + Disable Preempt Ability. This field resets to 0. + 6 + 1 + read-write + + + DPA_0 + Channel n can suspend a lower priority channel. + 0 + + + DPA_1 + Channel n cannot suspend any channel, regardless of channel priority. + 0x1 + + + + + ECP + Enable Channel Preemption. This field resets to 0. + 7 + 1 + read-write + + + ECP_0 + Channel n cannot be suspended by a higher priority channel's service request. + 0 + + + ECP_1 + Channel n can be temporarily suspended by the service request of a higher priority channel. + 0x1 + + + + + + + DCHPRI21 + Channel n Priority Register + 0x116 + 8 + read-write + 0x15 + 0xFF + + + CHPRI + Channel n Arbitration Priority + 0 + 4 + read-write + + + GRPPRI + Channel n Current Group Priority + 4 + 2 + read-only + + + DPA + Disable Preempt Ability. This field resets to 0. + 6 + 1 + read-write + + + DPA_0 + Channel n can suspend a lower priority channel. + 0 + + + DPA_1 + Channel n cannot suspend any channel, regardless of channel priority. + 0x1 + + + + + ECP + Enable Channel Preemption. This field resets to 0. + 7 + 1 + read-write + + + ECP_0 + Channel n cannot be suspended by a higher priority channel's service request. + 0 + + + ECP_1 + Channel n can be temporarily suspended by the service request of a higher priority channel. + 0x1 + + + + + + + DCHPRI20 + Channel n Priority Register + 0x117 + 8 + read-write + 0x14 + 0xFF + + + CHPRI + Channel n Arbitration Priority + 0 + 4 + read-write + + + GRPPRI + Channel n Current Group Priority + 4 + 2 + read-only + + + DPA + Disable Preempt Ability. This field resets to 0. + 6 + 1 + read-write + + + DPA_0 + Channel n can suspend a lower priority channel. + 0 + + + DPA_1 + Channel n cannot suspend any channel, regardless of channel priority. + 0x1 + + + + + ECP + Enable Channel Preemption. This field resets to 0. + 7 + 1 + read-write + + + ECP_0 + Channel n cannot be suspended by a higher priority channel's service request. + 0 + + + ECP_1 + Channel n can be temporarily suspended by the service request of a higher priority channel. + 0x1 + + + + + + + DCHPRI27 + Channel n Priority Register + 0x118 + 8 + read-write + 0x1B + 0xFF + + + CHPRI + Channel n Arbitration Priority + 0 + 4 + read-write + + + GRPPRI + Channel n Current Group Priority + 4 + 2 + read-only + + + DPA + Disable Preempt Ability. This field resets to 0. + 6 + 1 + read-write + + + DPA_0 + Channel n can suspend a lower priority channel. + 0 + + + DPA_1 + Channel n cannot suspend any channel, regardless of channel priority. + 0x1 + + + + + ECP + Enable Channel Preemption. This field resets to 0. + 7 + 1 + read-write + + + ECP_0 + Channel n cannot be suspended by a higher priority channel's service request. + 0 + + + ECP_1 + Channel n can be temporarily suspended by the service request of a higher priority channel. + 0x1 + + + + + + + DCHPRI26 + Channel n Priority Register + 0x119 + 8 + read-write + 0x1A + 0xFF + + + CHPRI + Channel n Arbitration Priority + 0 + 4 + read-write + + + GRPPRI + Channel n Current Group Priority + 4 + 2 + read-only + + + DPA + Disable Preempt Ability. This field resets to 0. + 6 + 1 + read-write + + + DPA_0 + Channel n can suspend a lower priority channel. + 0 + + + DPA_1 + Channel n cannot suspend any channel, regardless of channel priority. + 0x1 + + + + + ECP + Enable Channel Preemption. This field resets to 0. + 7 + 1 + read-write + + + ECP_0 + Channel n cannot be suspended by a higher priority channel's service request. + 0 + + + ECP_1 + Channel n can be temporarily suspended by the service request of a higher priority channel. + 0x1 + + + + + + + DCHPRI25 + Channel n Priority Register + 0x11A + 8 + read-write + 0x19 + 0xFF + + + CHPRI + Channel n Arbitration Priority + 0 + 4 + read-write + + + GRPPRI + Channel n Current Group Priority + 4 + 2 + read-only + + + DPA + Disable Preempt Ability. This field resets to 0. + 6 + 1 + read-write + + + DPA_0 + Channel n can suspend a lower priority channel. + 0 + + + DPA_1 + Channel n cannot suspend any channel, regardless of channel priority. + 0x1 + + + + + ECP + Enable Channel Preemption. This field resets to 0. + 7 + 1 + read-write + + + ECP_0 + Channel n cannot be suspended by a higher priority channel's service request. + 0 + + + ECP_1 + Channel n can be temporarily suspended by the service request of a higher priority channel. + 0x1 + + + + + + + DCHPRI24 + Channel n Priority Register + 0x11B + 8 + read-write + 0x18 + 0xFF + + + CHPRI + Channel n Arbitration Priority + 0 + 4 + read-write + + + GRPPRI + Channel n Current Group Priority + 4 + 2 + read-only + + + DPA + Disable Preempt Ability. This field resets to 0. + 6 + 1 + read-write + + + DPA_0 + Channel n can suspend a lower priority channel. + 0 + + + DPA_1 + Channel n cannot suspend any channel, regardless of channel priority. + 0x1 + + + + + ECP + Enable Channel Preemption. This field resets to 0. + 7 + 1 + read-write + + + ECP_0 + Channel n cannot be suspended by a higher priority channel's service request. + 0 + + + ECP_1 + Channel n can be temporarily suspended by the service request of a higher priority channel. + 0x1 + + + + + + + DCHPRI31 + Channel n Priority Register + 0x11C + 8 + read-write + 0x1F + 0xFF + + + CHPRI + Channel n Arbitration Priority + 0 + 4 + read-write + + + GRPPRI + Channel n Current Group Priority + 4 + 2 + read-only + + + DPA + Disable Preempt Ability. This field resets to 0. + 6 + 1 + read-write + + + DPA_0 + Channel n can suspend a lower priority channel. + 0 + + + DPA_1 + Channel n cannot suspend any channel, regardless of channel priority. + 0x1 + + + + + ECP + Enable Channel Preemption. This field resets to 0. + 7 + 1 + read-write + + + ECP_0 + Channel n cannot be suspended by a higher priority channel's service request. + 0 + + + ECP_1 + Channel n can be temporarily suspended by the service request of a higher priority channel. + 0x1 + + + + + + + DCHPRI30 + Channel n Priority Register + 0x11D + 8 + read-write + 0x1E + 0xFF + + + CHPRI + Channel n Arbitration Priority + 0 + 4 + read-write + + + GRPPRI + Channel n Current Group Priority + 4 + 2 + read-only + + + DPA + Disable Preempt Ability. This field resets to 0. + 6 + 1 + read-write + + + DPA_0 + Channel n can suspend a lower priority channel. + 0 + + + DPA_1 + Channel n cannot suspend any channel, regardless of channel priority. + 0x1 + + + + + ECP + Enable Channel Preemption. This field resets to 0. + 7 + 1 + read-write + + + ECP_0 + Channel n cannot be suspended by a higher priority channel's service request. + 0 + + + ECP_1 + Channel n can be temporarily suspended by the service request of a higher priority channel. + 0x1 + + + + + + + DCHPRI29 + Channel n Priority Register + 0x11E + 8 + read-write + 0x1D + 0xFF + + + CHPRI + Channel n Arbitration Priority + 0 + 4 + read-write + + + GRPPRI + Channel n Current Group Priority + 4 + 2 + read-only + + + DPA + Disable Preempt Ability. This field resets to 0. + 6 + 1 + read-write + + + DPA_0 + Channel n can suspend a lower priority channel. + 0 + + + DPA_1 + Channel n cannot suspend any channel, regardless of channel priority. + 0x1 + + + + + ECP + Enable Channel Preemption. This field resets to 0. + 7 + 1 + read-write + + + ECP_0 + Channel n cannot be suspended by a higher priority channel's service request. + 0 + + + ECP_1 + Channel n can be temporarily suspended by the service request of a higher priority channel. + 0x1 + + + + + + + DCHPRI28 + Channel n Priority Register + 0x11F + 8 + read-write + 0x1C + 0xFF + + + CHPRI + Channel n Arbitration Priority + 0 + 4 + read-write + + + GRPPRI + Channel n Current Group Priority + 4 + 2 + read-only + + + DPA + Disable Preempt Ability. This field resets to 0. + 6 + 1 + read-write + + + DPA_0 + Channel n can suspend a lower priority channel. + 0 + + + DPA_1 + Channel n cannot suspend any channel, regardless of channel priority. + 0x1 + + + + + ECP + Enable Channel Preemption. This field resets to 0. + 7 + 1 + read-write + + + ECP_0 + Channel n cannot be suspended by a higher priority channel's service request. + 0 + + + ECP_1 + Channel n can be temporarily suspended by the service request of a higher priority channel. + 0x1 + + + + + TCD0_SADDR TCD Source Address @@ -63467,28 +66654,9 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 32 read-write - 0x500 + 0xA0480520 0xFFFFFFFF - - lockup_rst - lockup reset enable bit - 4 - 1 - read-write - - - lockup_rst_0 - disabled - 0 - - - lockup_rst_1 - enabled - 0x1 - - - mask_wdog_rst Mask wdog_rst_b source @@ -63990,7 +67158,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 32 read-write - 0x401167F + 0x401107F 0xFFFFFFFF @@ -64180,7 +67348,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0x10 32 read-write - 0 + 0x1 0xFFFFFFFF @@ -64240,7 +67408,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0x14 32 read-write - 0xB8600 + 0xA8300 0xFFFFFFFF @@ -64283,7 +67451,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. IPG_PODF - Divider for ipg podf + Divider for ipg podf. 8 2 read-write @@ -64484,7 +67652,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0x18 32 read-write - 0x2DA28324 + 0x2DAE8324 0xFFFFFFFF @@ -64704,7 +67872,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0x1C 32 read-write - 0x4900080 + 0x4900000 0xFFFFFFFF @@ -64971,12 +68139,12 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0x20 32 read-write - 0x3192C06 + 0x13192F06 0xFFFFFFFF CAN_CLK_PODF - Divider for can clock podf. + Divider for CAN clock podf. 2 6 read-write @@ -65000,7 +68168,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. CAN_CLK_SEL - Selector for FlexCAN clock multiplexer + Selector for CAN clock multiplexer 8 2 read-write @@ -65020,6 +68188,11 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. derive clock from pll3_sw_clk divided clock (80M) 0x2 + + CAN_CLK_SEL_3 + Disable FlexCAN clock + 0x3 + @@ -65059,7 +68232,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0x24 32 read-write - 0x490B00 + 0x6490B00 0xFFFFFFFF @@ -65202,7 +68375,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. TRACE_PODF Divider for trace clock. Divider should be updated when output clock is gated. 25 - 3 + 2 read-write @@ -65225,26 +68398,6 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. divide by 4 0x3 - - TRACE_PODF_4 - divide by 5 - 0x4 - - - TRACE_PODF_5 - divide by 6 - 0x5 - - - TRACE_PODF_6 - divide by 7 - 0x6 - - - TRACE_PODF_7 - divide by 8 - 0x7 - @@ -65500,7 +68653,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0x2C 32 read-write - 0x336C1 + 0x7336C1 0xFFFFFFFF @@ -65744,43 +68897,9 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0x38 32 read-write - 0x29B48 + 0x29150 0xFFFFFFFF - - LCDIF_CLK_SEL - Selector for LCDIF root clock multiplexer - 9 - 3 - read-write - - - LCDIF_CLK_SEL_0 - derive clock from divided pre-muxed LCDIF clock - 0 - - - LCDIF_CLK_SEL_1 - derive clock from ipp_di0_clk - 0x1 - - - LCDIF_CLK_SEL_2 - derive clock from ipp_di1_clk - 0x2 - - - LCDIF_CLK_SEL_3 - derive clock from ldb_di0_clk - 0x3 - - - LCDIF_CLK_SEL_4 - derive clock from ldb_di1_clk - 0x4 - - - LCDIF_PRED Pre-divider for lcdif clock. Divider should be updated when output clock is gated. @@ -65915,7 +69034,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0x3C 32 read-write - 0x14841 + 0x30841 0xFFFFFFFF @@ -66645,16 +69764,26 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 4 read-write + + CLKO1_SEL_0 + USB1 PLL clock (divided by 2) + 0 + + + CLKO1_SEL_1 + SYS PLL clock (divided by 2) + 0x1 + + + CLKO1_SEL_3 + VIDEO PLL clock (divided by 2) + 0x3 + CLKO1_SEL_5 semc_clk_root 0x5 - - CLKO1_SEL_6 - enc_clk_root - 0x6 - CLKO1_SEL_10 lcdif_pix_clk_root @@ -66798,7 +69927,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. CLKO2_SEL_11 - csi_core + csi_clk_root 0xB @@ -67061,14 +70190,14 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. CG3 - Reserved + flexspi_exsc clock (flexspi_exsc_clk_enable) 6 2 read-write CG4 - Reserved + sim_m or sim_main register access clock (sim_m_mainclk_r_enable) 8 2 read-write @@ -67226,21 +70355,21 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. CG9 - Reserved + semc_exsc clock (semc_exsc_clk_enable) 18 2 read-write CG10 - gpt bus clock (gpt_clk_enable) + gpt1 bus clock (gpt_clk_enable) 20 2 read-write CG11 - gpt serial clock (gpt_serial_clk_enable) + gpt1 serial clock (gpt_serial_clk_enable) 22 2 read-write @@ -67268,7 +70397,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. CG15 - gpio5 clock (gpio5_clk_enable) + Reserved 30 2 read-write @@ -67286,7 +70415,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. CG0 - Reserved + ocram_exsc clock (ocram_exsc_clk_enable) 0 2 read-write @@ -67444,7 +70573,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. CG5 - LCDIF pix clock (LCDIF_pix_clk_enable) + lcdif pix clock (lcdif_pix_clk_enable) 10 2 read-write @@ -67532,7 +70661,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. CG0 - Reserved + sim_m7 register access clock (sim_m7_mainclk_r_enable) 0 2 read-write @@ -67813,7 +70942,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. CG5 - flexspi clocks (flexspi_clk_enable) + flexspi clocks (flexspi_clk_enable) sim_ems_clk_enable must also be cleared, when flexspi_clk_enable is cleared 10 2 read-write @@ -67876,14 +71005,14 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. CG14 - timer2 clocks (timer4_clk_enable) + timer2 clocks (timer2_clk_enable) 28 2 read-write CG15 - timer3 clocks (timer4_clk_enable) + timer3 clocks (timer3_clk_enable) 30 2 read-write @@ -68152,14 +71281,14 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. THUMBX - THUMB Comparator Select - Indicates that this address will trigger a THUMB opcode patch or an ARM opcode patch + THUMB Comparator Select - Indicates that this address will trigger a THUMB opcode patch or an Arm opcode patch 0 1 read-write THUMBX_0 - ARM patch + Arm patch 0 @@ -68434,12 +71563,12 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. RXEDGIE_0 - Hardware interrupts from LPUART_STAT[RXEDGIF] disabled. + Hardware interrupts from STAT[RXEDGIF] are disabled. 0 RXEDGIE_1 - Hardware interrupt requested when LPUART_STAT[RXEDGIF] flag is 1. + Hardware interrupt is requested when STAT[RXEDGIF] flag is 1. 0x1 @@ -68453,12 +71582,12 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. LBKDIE_0 - Hardware interrupts from LPUART_STAT[LBKDIF] disabled (use polling). + Hardware interrupts from STAT[LBKDIF] flag are disabled (use polling). 0 LBKDIE_1 - Hardware interrupt requested when LPUART_STAT[LBKDIF] flag is 1. + Hardware interrupt requested when STAT[LBKDIF] flag is 1. 0x1 @@ -68530,6 +71659,25 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + + RIDMAE + Receiver Idle DMA Enable + 20 + 1 + read-write + + + RIDMAE_0 + DMA request disabled. + 0 + + + RIDMAE_1 + DMA request enabled. + 0x1 + + + RDMAE Receiver Full DMA Enable @@ -68890,7 +72038,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. NF_1 - Noise detected in the received character in LPUART_DATA. + Noise detected in the received character in the DATA register. 0x1 @@ -70089,7 +73237,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. RXFIFOSIZE - Receive FIFO. Buffer Depth + Receive FIFO Buffer Depth 0 3 read-only @@ -70145,7 +73293,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. RXFE_0 - Receive FIFO is not enabled. Buffer is depth 1. (Legacy support) + Receive FIFO is not enabled. Buffer is depth 1. 0 @@ -70157,7 +73305,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. TXFIFOSIZE - Transmit FIFO. Buffer Depth + Transmit FIFO Buffer Depth 4 3 read-only @@ -70213,7 +73361,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. TXFE_0 - Transmit FIFO is not enabled. Buffer is depth 1. (Legacy support). + Transmit FIFO is not enabled. Buffer is depth 1. 0 @@ -71523,12 +74671,12 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. TIMDIS_2 - Timer disabled on Timer compare + Timer disabled on Timer compare (upper 8-bits match and decrement) 0x2 TIMDIS_3 - Timer disabled on Timer compare and Trigger Low + Timer disabled on Timer compare (upper 8-bits match and decrement) and Trigger Low 0x3 @@ -71752,7 +74900,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0x401B8000 0 - 0x20 + 0x90 registers @@ -72855,6 +76003,60 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + + DR_SET + GPIO data register SET + 0x84 + 32 + write-only + 0 + 0xFFFFFFFF + + + DR_SET + DR_SET + 0 + 32 + write-only + + + + + DR_CLEAR + GPIO data register CLEAR + 0x88 + 32 + write-only + 0 + 0xFFFFFFFF + + + DR_CLEAR + DR_CLEAR + 0 + 32 + write-only + + + + + DR_TOGGLE + GPIO data register TOGGLE + 0x8C + 32 + write-only + 0 + 0xFFFFFFFF + + + DR_TOGGLE + DR_TOGGLE + 0 + 32 + write-only + + + @@ -72864,7 +76066,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0x400C0000 0 - 0x20 + 0x90 registers @@ -72883,7 +76085,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0x401BC000 0 - 0x20 + 0x90 registers @@ -72902,7 +76104,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0x401C0000 0 - 0x20 + 0x90 registers @@ -72921,7 +76123,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0x401C4000 0 - 0x20 + 0x90 registers @@ -73282,7 +76484,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. FRZ - The FRZ bit specifies the FLEXCAN behavior when the HALT bit in the MCR Register is set or when Debug Mode is requested at ARM level + The FRZ bit specifies the FLEXCAN behavior when the HALT bit in the MCR Register is set or when Debug Mode is requested at Arm level 30 1 read-write @@ -73700,7 +76902,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. WAKINT - When FLEXCAN is Stop Mode and a recessive to dominant transition is detected on the CAN bus and if the WAK_MSK bit in the MCR Register is set, an interrupt is generated to the ARM + When FLEXCAN is Stop Mode and a recessive to dominant transition is detected on the CAN bus and if the WAK_MSK bit in the MCR Register is set, an interrupt is generated to the Arm 0 1 read-write @@ -74473,6 +77675,94 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + + DBG1 + Debug 1 register + 0x58 + 32 + read-only + 0x10000 + 0xFFFFFFFF + + + CFSM + CAN Finite State Machine + 0 + 6 + read-only + + + CBN + CAN Bit Number + 24 + 5 + read-only + + + + + DBG2 + Debug 2 register + 0x5C + 32 + read-only + 0 + 0xFFFFFFFF + + + RMP + Rx Matching Pointer + 0 + 7 + read-only + + + MPP + Matching Process in Progress + 7 + 1 + read-only + + + MPP_0 + No matching process ongoing. + 0 + + + MPP_1 + Matching process is in progress. + 0x1 + + + + + TAP + Tx Arbitration Pointer + 8 + 7 + read-only + + + APP + Arbitration Process in Progress + 15 + 1 + read-only + + + APP_0 + No matching process ongoing. + 0 + + + APP_1 + Matching process is in progress. + 0x1 + + + + + CS0 Message Buffer 0 CS Register @@ -86783,6 +90073,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 6 read-write + oneToSet BUSY @@ -86790,6 +90081,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 8 1 read-only + oneToSet ERROR @@ -86797,6 +90089,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 9 1 read-write + oneToSet RELOAD_SHADOWS @@ -86804,6 +90097,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 10 1 read-write + oneToSet WR_UNLOCK @@ -86811,6 +90105,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 16 16 read-write + oneToSet @@ -86829,6 +90124,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 6 read-write + oneToClear BUSY @@ -86836,6 +90132,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 8 1 read-only + oneToClear ERROR @@ -86843,6 +90140,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 9 1 read-write + oneToClear RELOAD_SHADOWS @@ -86850,6 +90148,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 10 1 read-write + oneToClear WR_UNLOCK @@ -86857,6 +90156,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 16 16 read-write + oneToClear @@ -86875,6 +90175,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 6 read-write + oneToToggle BUSY @@ -86882,6 +90183,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 8 1 read-only + oneToToggle ERROR @@ -86889,6 +90191,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 9 1 read-write + oneToToggle RELOAD_SHADOWS @@ -86896,6 +90199,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 10 1 read-write + oneToToggle WR_UNLOCK @@ -86903,6 +90207,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 16 16 read-write + oneToToggle @@ -87092,6 +90397,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 1 read-write + oneToSet SPARE @@ -87099,6 +90405,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 1 30 read-write + oneToSet LOCK @@ -87106,6 +90413,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 1 read-write + oneToSet @@ -87124,6 +90432,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 1 read-write + oneToClear SPARE @@ -87131,6 +90440,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 1 30 read-write + oneToClear LOCK @@ -87138,6 +90448,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 1 read-write + oneToClear @@ -87156,6 +90467,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 1 read-write + oneToToggle SPARE @@ -87163,6 +90475,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 1 30 read-write + oneToToggle LOCK @@ -87170,6 +90483,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 1 read-write + oneToToggle @@ -87295,13 +90609,6 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2 read-only - - SRK - Status of shadow register and OTP write lock for srk region - 14 - 1 - read-only - OTPMK_MSB Status of shadow register read and write, OTP read and write lock for otpmk region (MSB) @@ -88118,11 +91425,6 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. Select mux mode: ALT5 mux port: GPIO4_IO00 of instance: gpio4 0x5 - - ALT7 - Select mux mode: ALT7 mux port: JTAG_DONE of instance: JTAG - 0x7 - @@ -88192,11 +91494,6 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. Select mux mode: ALT5 mux port: GPIO4_IO01 of instance: gpio4 0x5 - - ALT7 - Select mux mode: ALT7 mux port: JTAG_DE_B of instance: JTAG - 0x7 - @@ -88266,11 +91563,6 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. Select mux mode: ALT5 mux port: GPIO4_IO02 of instance: gpio4 0x5 - - ALT7 - Select mux mode: ALT7 mux port: JTAG_FAIL of instance: JTAG - 0x7 - @@ -88340,11 +91632,6 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. Select mux mode: ALT5 mux port: GPIO4_IO03 of instance: gpio4 0x5 - - ALT7 - Select mux mode: ALT7 mux port: JTAG_ACTIVE of instance: JTAG - 0x7 - @@ -92034,6 +95321,11 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. Select mux mode: ALT6 mux port: ENET_1588_EVENT1_OUT of instance: enet 0x6 + + ALT7 + Select mux mode: ALT7 mux port: NMI_GLUE_NMI of instance: nmi_glue + 0x7 + @@ -93880,6 +97172,11 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. Select mux mode: ALT2 mux port: LPI2C2_SCL of instance: lpi2c2 0x2 + + ALT3 + Select mux mode: ALT3 mux port: ARM_CM7_TRACE00 of instance: cm7_mx6rt + 0x3 + ALT4 Select mux mode: ALT4 mux port: FLEXIO2_FLEXIO04 of instance: flexio2 @@ -93949,6 +97246,11 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. Select mux mode: ALT2 mux port: LPI2C2_SDA of instance: lpi2c2 0x2 + + ALT3 + Select mux mode: ALT3 mux port: ARM_CM7_TRACE01 of instance: cm7_mx6rt + 0x3 + ALT4 Select mux mode: ALT4 mux port: FLEXIO2_FLEXIO05 of instance: flexio2 @@ -94018,6 +97320,11 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. Select mux mode: ALT2 mux port: FLEXPWM2_PWMA00 of instance: flexpwm2 0x2 + + ALT3 + Select mux mode: ALT3 mux port: ARM_CM7_TRACE02 of instance: cm7_mx6rt + 0x3 + ALT4 Select mux mode: ALT4 mux port: FLEXIO2_FLEXIO06 of instance: flexio2 @@ -94087,6 +97394,11 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. Select mux mode: ALT2 mux port: FLEXPWM2_PWMB00 of instance: flexpwm2 0x2 + + ALT3 + Select mux mode: ALT3 mux port: ARM_CM7_TRACE03 of instance: cm7_mx6rt + 0x3 + ALT4 Select mux mode: ALT4 mux port: FLEXIO2_FLEXIO07 of instance: flexio2 @@ -94447,6 +97759,11 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. Select mux mode: ALT1 mux port: XBAR1_INOUT10 of instance: xbar1 0x1 + + ALT2 + Select mux mode: ALT2 mux port: ARM_CM7_TRACE_CLK of instance: cm7_mx6rt + 0x2 + ALT3 Select mux mode: ALT3 mux port: SAI1_TX_DATA01 of instance: sai1 @@ -94516,6 +97833,11 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. Select mux mode: ALT1 mux port: XBAR1_INOUT11 of instance: xbar1 0x1 + + ALT2 + Select mux mode: ALT2 mux port: ARM_CM7_TRACE_SWO of instance: cm7_mx6rt + 0x2 + ALT3 Select mux mode: ALT3 mux port: SAI1_MCLK of instance: sai1 @@ -95049,11 +98371,6 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. Select mux mode: ALT5 mux port: GPIO2_IO20 of instance: gpio2 0x5 - - ALT6 - Select mux mode: ALT6 mux port: CSU_CSU_ALARM_AUT02 of instance: csu - 0x6 - @@ -95123,11 +98440,6 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. Select mux mode: ALT5 mux port: GPIO2_IO21 of instance: gpio2 0x5 - - ALT6 - Select mux mode: ALT6 mux port: CSU_CSU_ALARM_AUT01 of instance: csu - 0x6 - @@ -95197,11 +98509,6 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. Select mux mode: ALT5 mux port: GPIO2_IO22 of instance: gpio2 0x5 - - ALT6 - Select mux mode: ALT6 mux port: CSU_CSU_ALARM_AUT00 of instance: csu - 0x6 - @@ -95271,11 +98578,6 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. Select mux mode: ALT5 mux port: GPIO2_IO23 of instance: gpio2 0x5 - - ALT6 - Select mux mode: ALT6 mux port: CSU_CSU_INT_DEB of instance: csu - 0x6 - @@ -96435,11 +99737,6 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. Select mux mode: ALT5 mux port: GPIO3_IO01 of instance: gpio3 0x5 - - ALT6 - Select mux mode: ALT6 mux port: CCM_DI0_EXT_CLK of instance: ccm - 0x6 - @@ -96869,11 +100166,6 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. Select mux mode: ALT5 mux port: GPIO3_IO07 of instance: gpio3 0x5 - - ALT6 - Select mux mode: ALT6 mux port: CCM_REF_EN_B of instance: ccm - 0x6 - @@ -97086,11 +100378,6 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. Select mux mode: ALT5 mux port: GPIO3_IO10 of instance: gpio3 0x5 - - ALT6 - Select mux mode: ALT6 mux port: SRC_SYSTEM_RESET of instance: src - 0x6 - @@ -97160,11 +100447,6 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. Select mux mode: ALT5 mux port: GPIO3_IO11 of instance: gpio3 0x5 - - ALT6 - Select mux mode: ALT6 mux port: SRC_EARLY_RESET of instance: src - 0x6 - @@ -97229,8 +100511,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -97442,8 +100724,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -97655,8 +100937,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -97868,8 +101150,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -98081,8 +101363,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -98294,8 +101576,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -98507,8 +101789,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -98720,8 +102002,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -98933,8 +102215,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -99146,8 +102428,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -99359,8 +102641,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -99572,8 +102854,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -99785,8 +103067,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -99998,8 +103280,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -100211,8 +103493,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -100424,8 +103706,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -100637,8 +103919,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -100850,8 +104132,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -101063,8 +104345,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -101276,8 +104558,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -101489,8 +104771,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -101702,8 +104984,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -101915,8 +105197,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -102128,8 +105410,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -102341,8 +105623,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -102554,8 +105836,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -102767,8 +106049,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -102980,8 +106262,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -103193,8 +106475,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -103406,8 +106688,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -103619,8 +106901,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -103832,8 +107114,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -104045,8 +107327,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -104258,8 +107540,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -104471,8 +107753,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -104684,8 +107966,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -104897,8 +108179,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -105110,8 +108392,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -105323,8 +108605,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -105536,8 +108818,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -105749,8 +109031,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -105962,8 +109244,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -106175,8 +109457,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -106388,8 +109670,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -106601,8 +109883,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -106814,8 +110096,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -107027,8 +110309,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -107240,8 +110522,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -107453,8 +110735,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -107666,8 +110948,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -107879,8 +111161,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -108092,8 +111374,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -108305,8 +111587,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -108518,8 +111800,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -108731,8 +112013,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -108944,8 +112226,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -109157,8 +112439,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -109370,8 +112652,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -109583,8 +112865,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -109796,8 +113078,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -110009,8 +113291,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -110222,8 +113504,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -110435,8 +113717,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -110648,8 +113930,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -110861,8 +114143,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -111074,8 +114356,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -111287,8 +114569,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -111500,8 +114782,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -111713,8 +114995,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -111926,8 +115208,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -112139,8 +115421,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -112352,8 +115634,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -112565,8 +115847,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -112778,8 +116060,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -112991,8 +116273,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -113204,8 +116486,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -113417,8 +116699,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -113630,8 +116912,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -113843,8 +117125,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -114056,8 +117338,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -114269,8 +117551,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -114482,8 +117764,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -114695,8 +117977,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -114908,8 +118190,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -115121,8 +118403,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -115334,8 +118616,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -115547,8 +118829,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -115760,8 +119042,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -115973,8 +119255,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -116186,8 +119468,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -116399,8 +119681,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -116612,8 +119894,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -116825,8 +120107,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -117038,8 +120320,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -117251,8 +120533,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -117464,8 +120746,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -117677,8 +120959,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -117890,8 +121172,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -118103,8 +121385,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -118316,8 +121598,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -118529,8 +121811,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -118742,8 +122024,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -118955,8 +122237,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -119168,8 +122450,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -119381,8 +122663,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -119594,8 +122876,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -119807,8 +123089,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -120020,8 +123302,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -120233,8 +123515,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -120446,8 +123728,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -120659,8 +123941,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -120872,8 +124154,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -121085,8 +124367,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -121298,8 +124580,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -121511,8 +124793,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -121724,8 +125006,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -121937,8 +125219,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -122150,8 +125432,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -122363,8 +125645,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -122576,8 +125858,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -122789,8 +126071,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -123002,8 +126284,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -123215,8 +126497,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -123428,8 +126710,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0 - DSE_1_R0_260_Ohm_3_3V_150_Ohm_1_8V_240_Ohm_for_DDR - R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 @@ -126557,12 +129839,12 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. read-write - SELECT_GPIO_AD_B0_12_ALT7 + GPIO_AD_B0_12_ALT7 Selecting Pad: GPIO_AD_B0_12 for Mode: ALT7 0 - SELECT_WAKEUP_ALT7 + WAKEUP_ALT7 Selecting Pad: WAKEUP for Mode: ALT7 0x1 @@ -129339,10 +132621,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - 4 - 0x4 - 0,1,2,3 - AHBRXBUFCR0%s + AHBRXBUF0CR0 AHB RX Buffer 0 Control Register 0 0x20 32 @@ -129371,13 +132650,134 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2 read-write + + PREFETCHEN + AHB Read Prefetch Enable for current AHB RX Buffer corresponding Master. + 31 + 1 + read-write + - 4 - 0x4 - A1,A2,B1,B2 - FLSHCR0%s + AHBRXBUF1CR0 + AHB RX Buffer 1 Control Register 0 + 0x24 + 32 + read-write + 0x80010020 + 0xFFFFFFFF + + + BUFSZ + AHB RX Buffer Size in 64 bits.Refer AHB RX Buffer Management for more details. + 0 + 8 + read-write + + + MSTRID + This AHB RX Buffer is assigned according to AHB Master with ID (MSTR_ID). Please refer to for AHB RX Buffer allocation. + 16 + 4 + read-write + + + PRIORITY + This priority for AHB Master Read which this AHB RX Buffer is assigned. Refer for more details. + 24 + 2 + read-write + + + PREFETCHEN + AHB Read Prefetch Enable for current AHB RX Buffer corresponding Master. + 31 + 1 + read-write + + + + + AHBRXBUF2CR0 + AHB RX Buffer 2 Control Register 0 + 0x28 + 32 + read-write + 0x80020020 + 0xFFFFFFFF + + + BUFSZ + AHB RX Buffer Size in 64 bits.Refer AHB RX Buffer Management for more details. + 0 + 8 + read-write + + + MSTRID + This AHB RX Buffer is assigned according to AHB Master with ID (MSTR_ID). Please refer to for AHB RX Buffer allocation. + 16 + 4 + read-write + + + PRIORITY + This priority for AHB Master Read which this AHB RX Buffer is assigned. Refer for more details. + 24 + 2 + read-write + + + PREFETCHEN + AHB Read Prefetch Enable for current AHB RX Buffer corresponding Master. + 31 + 1 + read-write + + + + + AHBRXBUF3CR0 + AHB RX Buffer 3 Control Register 0 + 0x2C + 32 + read-write + 0x80030020 + 0xFFFFFFFF + + + BUFSZ + AHB RX Buffer Size in 64 bits.Refer AHB RX Buffer Management for more details. + 0 + 8 + read-write + + + MSTRID + This AHB RX Buffer is assigned according to AHB Master with ID (MSTR_ID). Please refer to for AHB RX Buffer allocation. + 16 + 4 + read-write + + + PRIORITY + This priority for AHB Master Read which this AHB RX Buffer is assigned. Refer for more details. + 24 + 2 + read-write + + + PREFETCHEN + AHB Read Prefetch Enable for current AHB RX Buffer corresponding Master. + 31 + 1 + read-write + + + + + FLSHA1CR0 Flash A1 Control Register 0 0x60 32 @@ -129394,6 +132794,60 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + + FLSHA2CR0 + Flash A2 Control Register 0 + 0x64 + 32 + read-write + 0x10000 + 0xFFFFFFFF + + + FLSHSZ + Flash Size in KByte. + 0 + 23 + read-write + + + + + FLSHB1CR0 + Flash B1 Control Register 0 + 0x68 + 32 + read-write + 0x10000 + 0xFFFFFFFF + + + FLSHSZ + Flash Size in KByte. + 0 + 23 + read-write + + + + + FLSHB2CR0 + Flash B2 Control Register 0 + 0x6C + 32 + read-write + 0x10000 + 0xFFFFFFFF + + + FLSHSZ + Flash Size in KByte. + 0 + 23 + read-write + + + 4 0x4 @@ -133627,7 +137081,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. LCDIF - eLCDIF Register Reference Index + LCDIF Register Reference Index LCDIF LCDIF_ 0x402B8000 @@ -133643,7 +137097,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. CTRL - eLCDIF General Control Register + LCDIF General Control Register 0 32 read-write @@ -133652,7 +137106,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. RUN - When this bit is set by software, the eLCDIF will begin transferring data between the SoC and the display + When this bit is set by software, the LCDIF will begin transferring data between the SoC and the display 0 1 read-write @@ -133704,14 +137158,14 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. MASTER - Set this bit to make the eLCDIF act as a bus master + Set this bit to make the LCDIF act as a bus master 5 1 read-write ENABLE_PXP_HANDSHAKE - If this bit is set and LCDIF_MASTER bit is set, the eLCDIF will act as bus master and the handshake mechanism between eLCDIF and PXP will be turned on + If this bit is set and LCDIF_MASTER bit is set, the LCDIF will act as bus master and the handshake mechanism between LCDIF and PXP will be turned on 6 1 read-write @@ -133841,7 +137295,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. BYPASS_COUNT - When this bit is 0, it means that eLCDIF will stop the block operation and turn off the RUN bit after the amount of data indicated by the LCDIF_TRANSFER_COUNT register has been transferred out + When this bit is 0, it means that LCDIF will stop the block operation and turn off the RUN bit after the amount of data indicated by the LCDIF_TRANSFER_COUNT register has been transferred out 19 1 read-write @@ -133881,7 +137335,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. SFTRST - This bit must be set to zero to enable normal operation of the eLCDIF + This bit must be set to zero to enable normal operation of the LCDIF 31 1 read-write @@ -133890,7 +137344,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. CTRL_SET - eLCDIF General Control Register + LCDIF General Control Register 0x4 32 read-write @@ -133899,7 +137353,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. RUN - When this bit is set by software, the eLCDIF will begin transferring data between the SoC and the display + When this bit is set by software, the LCDIF will begin transferring data between the SoC and the display 0 1 read-write @@ -133951,14 +137405,14 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. MASTER - Set this bit to make the eLCDIF act as a bus master + Set this bit to make the LCDIF act as a bus master 5 1 read-write ENABLE_PXP_HANDSHAKE - If this bit is set and LCDIF_MASTER bit is set, the eLCDIF will act as bus master and the handshake mechanism between eLCDIF and PXP will be turned on + If this bit is set and LCDIF_MASTER bit is set, the LCDIF will act as bus master and the handshake mechanism between LCDIF and PXP will be turned on 6 1 read-write @@ -134088,7 +137542,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. BYPASS_COUNT - When this bit is 0, it means that eLCDIF will stop the block operation and turn off the RUN bit after the amount of data indicated by the LCDIF_TRANSFER_COUNT register has been transferred out + When this bit is 0, it means that LCDIF will stop the block operation and turn off the RUN bit after the amount of data indicated by the LCDIF_TRANSFER_COUNT register has been transferred out 19 1 read-write @@ -134128,7 +137582,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. SFTRST - This bit must be set to zero to enable normal operation of the eLCDIF + This bit must be set to zero to enable normal operation of the LCDIF 31 1 read-write @@ -134137,7 +137591,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. CTRL_CLR - eLCDIF General Control Register + LCDIF General Control Register 0x8 32 read-write @@ -134146,7 +137600,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. RUN - When this bit is set by software, the eLCDIF will begin transferring data between the SoC and the display + When this bit is set by software, the LCDIF will begin transferring data between the SoC and the display 0 1 read-write @@ -134198,14 +137652,14 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. MASTER - Set this bit to make the eLCDIF act as a bus master + Set this bit to make the LCDIF act as a bus master 5 1 read-write ENABLE_PXP_HANDSHAKE - If this bit is set and LCDIF_MASTER bit is set, the eLCDIF will act as bus master and the handshake mechanism between eLCDIF and PXP will be turned on + If this bit is set and LCDIF_MASTER bit is set, the LCDIF will act as bus master and the handshake mechanism between LCDIF and PXP will be turned on 6 1 read-write @@ -134335,7 +137789,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. BYPASS_COUNT - When this bit is 0, it means that eLCDIF will stop the block operation and turn off the RUN bit after the amount of data indicated by the LCDIF_TRANSFER_COUNT register has been transferred out + When this bit is 0, it means that LCDIF will stop the block operation and turn off the RUN bit after the amount of data indicated by the LCDIF_TRANSFER_COUNT register has been transferred out 19 1 read-write @@ -134375,7 +137829,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. SFTRST - This bit must be set to zero to enable normal operation of the eLCDIF + This bit must be set to zero to enable normal operation of the LCDIF 31 1 read-write @@ -134384,7 +137838,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. CTRL_TOG - eLCDIF General Control Register + LCDIF General Control Register 0xC 32 read-write @@ -134393,7 +137847,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. RUN - When this bit is set by software, the eLCDIF will begin transferring data between the SoC and the display + When this bit is set by software, the LCDIF will begin transferring data between the SoC and the display 0 1 read-write @@ -134445,14 +137899,14 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. MASTER - Set this bit to make the eLCDIF act as a bus master + Set this bit to make the LCDIF act as a bus master 5 1 read-write ENABLE_PXP_HANDSHAKE - If this bit is set and LCDIF_MASTER bit is set, the eLCDIF will act as bus master and the handshake mechanism between eLCDIF and PXP will be turned on + If this bit is set and LCDIF_MASTER bit is set, the LCDIF will act as bus master and the handshake mechanism between LCDIF and PXP will be turned on 6 1 read-write @@ -134582,7 +138036,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. BYPASS_COUNT - When this bit is 0, it means that eLCDIF will stop the block operation and turn off the RUN bit after the amount of data indicated by the LCDIF_TRANSFER_COUNT register has been transferred out + When this bit is 0, it means that LCDIF will stop the block operation and turn off the RUN bit after the amount of data indicated by the LCDIF_TRANSFER_COUNT register has been transferred out 19 1 read-write @@ -134622,7 +138076,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. SFTRST - This bit must be set to zero to enable normal operation of the eLCDIF + This bit must be set to zero to enable normal operation of the LCDIF 31 1 read-write @@ -134631,7 +138085,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. CTRL1 - eLCDIF General Control1 Register + LCDIF General Control1 Register 0x10 32 read-write @@ -134640,7 +138094,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. VSYNC_EDGE_IRQ - This bit is set to indicate that an interrupt is requested by the eLCDIF block + This bit is set to indicate that an interrupt is requested by the LCDIF block 8 1 read-write @@ -134659,7 +138113,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. CUR_FRAME_DONE_IRQ - This bit is set to indicate that an interrupt is requested by the eLCDIF block + This bit is set to indicate that an interrupt is requested by the LCDIF block 9 1 read-write @@ -134678,7 +138132,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. UNDERFLOW_IRQ - This bit is set to indicate that an interrupt is requested by the eLCDIF block + This bit is set to indicate that an interrupt is requested by the LCDIF block 10 1 read-write @@ -134697,7 +138151,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. OVERFLOW_IRQ - This bit is set to indicate that an interrupt is requested by the eLCDIF block + This bit is set to indicate that an interrupt is requested by the LCDIF block 11 1 read-write @@ -134751,7 +138205,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. IRQ_ON_ALTERNATE_FIELDS - If this bit is set, the eLCDIF block will assert the cur_frame_done interrupt only on alternate fields, otherwise it will issue the interrupt on both odd and even field + If this bit is set, the LCDIF block will assert the cur_frame_done interrupt only on alternate fields, otherwise it will issue the interrupt on both odd and even field 20 1 read-write @@ -134772,21 +138226,21 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. INTERLACE_FIELDS - Set this bit if it is required that the eLCDIF block fetches odd lines in one field and even lines in the other field + Set this bit if it is required that the LCDIF block fetches odd lines in one field and even lines in the other field 23 1 read-write RECOVER_ON_UNDERFLOW - Set this bit to enable the eLCDIF block to recover in the next field/frame if there was an underflow in the current field/frame + Set this bit to enable the LCDIF block to recover in the next field/frame if there was an underflow in the current field/frame 24 1 read-write BM_ERROR_IRQ - This bit is set to indicate that an interrupt is requested by the eLCDIF block + This bit is set to indicate that an interrupt is requested by the LCDIF block 25 1 read-write @@ -134805,7 +138259,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. BM_ERROR_IRQ_EN - This bit is set to enable bus master error interrupt in the eLCDIF master mode. + This bit is set to enable bus master error interrupt in the LCDIF master mode. 26 1 read-write @@ -134828,7 +138282,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. CTRL1_SET - eLCDIF General Control1 Register + LCDIF General Control1 Register 0x14 32 read-write @@ -134837,7 +138291,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. VSYNC_EDGE_IRQ - This bit is set to indicate that an interrupt is requested by the eLCDIF block + This bit is set to indicate that an interrupt is requested by the LCDIF block 8 1 read-write @@ -134856,7 +138310,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. CUR_FRAME_DONE_IRQ - This bit is set to indicate that an interrupt is requested by the eLCDIF block + This bit is set to indicate that an interrupt is requested by the LCDIF block 9 1 read-write @@ -134875,7 +138329,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. UNDERFLOW_IRQ - This bit is set to indicate that an interrupt is requested by the eLCDIF block + This bit is set to indicate that an interrupt is requested by the LCDIF block 10 1 read-write @@ -134894,7 +138348,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. OVERFLOW_IRQ - This bit is set to indicate that an interrupt is requested by the eLCDIF block + This bit is set to indicate that an interrupt is requested by the LCDIF block 11 1 read-write @@ -134948,7 +138402,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. IRQ_ON_ALTERNATE_FIELDS - If this bit is set, the eLCDIF block will assert the cur_frame_done interrupt only on alternate fields, otherwise it will issue the interrupt on both odd and even field + If this bit is set, the LCDIF block will assert the cur_frame_done interrupt only on alternate fields, otherwise it will issue the interrupt on both odd and even field 20 1 read-write @@ -134969,21 +138423,21 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. INTERLACE_FIELDS - Set this bit if it is required that the eLCDIF block fetches odd lines in one field and even lines in the other field + Set this bit if it is required that the LCDIF block fetches odd lines in one field and even lines in the other field 23 1 read-write RECOVER_ON_UNDERFLOW - Set this bit to enable the eLCDIF block to recover in the next field/frame if there was an underflow in the current field/frame + Set this bit to enable the LCDIF block to recover in the next field/frame if there was an underflow in the current field/frame 24 1 read-write BM_ERROR_IRQ - This bit is set to indicate that an interrupt is requested by the eLCDIF block + This bit is set to indicate that an interrupt is requested by the LCDIF block 25 1 read-write @@ -135002,7 +138456,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. BM_ERROR_IRQ_EN - This bit is set to enable bus master error interrupt in the eLCDIF master mode. + This bit is set to enable bus master error interrupt in the LCDIF master mode. 26 1 read-write @@ -135025,7 +138479,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. CTRL1_CLR - eLCDIF General Control1 Register + LCDIF General Control1 Register 0x18 32 read-write @@ -135034,7 +138488,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. VSYNC_EDGE_IRQ - This bit is set to indicate that an interrupt is requested by the eLCDIF block + This bit is set to indicate that an interrupt is requested by the LCDIF block 8 1 read-write @@ -135053,7 +138507,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. CUR_FRAME_DONE_IRQ - This bit is set to indicate that an interrupt is requested by the eLCDIF block + This bit is set to indicate that an interrupt is requested by the LCDIF block 9 1 read-write @@ -135072,7 +138526,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. UNDERFLOW_IRQ - This bit is set to indicate that an interrupt is requested by the eLCDIF block + This bit is set to indicate that an interrupt is requested by the LCDIF block 10 1 read-write @@ -135091,7 +138545,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. OVERFLOW_IRQ - This bit is set to indicate that an interrupt is requested by the eLCDIF block + This bit is set to indicate that an interrupt is requested by the LCDIF block 11 1 read-write @@ -135145,7 +138599,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. IRQ_ON_ALTERNATE_FIELDS - If this bit is set, the eLCDIF block will assert the cur_frame_done interrupt only on alternate fields, otherwise it will issue the interrupt on both odd and even field + If this bit is set, the LCDIF block will assert the cur_frame_done interrupt only on alternate fields, otherwise it will issue the interrupt on both odd and even field 20 1 read-write @@ -135166,21 +138620,21 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. INTERLACE_FIELDS - Set this bit if it is required that the eLCDIF block fetches odd lines in one field and even lines in the other field + Set this bit if it is required that the LCDIF block fetches odd lines in one field and even lines in the other field 23 1 read-write RECOVER_ON_UNDERFLOW - Set this bit to enable the eLCDIF block to recover in the next field/frame if there was an underflow in the current field/frame + Set this bit to enable the LCDIF block to recover in the next field/frame if there was an underflow in the current field/frame 24 1 read-write BM_ERROR_IRQ - This bit is set to indicate that an interrupt is requested by the eLCDIF block + This bit is set to indicate that an interrupt is requested by the LCDIF block 25 1 read-write @@ -135199,7 +138653,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. BM_ERROR_IRQ_EN - This bit is set to enable bus master error interrupt in the eLCDIF master mode. + This bit is set to enable bus master error interrupt in the LCDIF master mode. 26 1 read-write @@ -135222,7 +138676,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. CTRL1_TOG - eLCDIF General Control1 Register + LCDIF General Control1 Register 0x1C 32 read-write @@ -135231,7 +138685,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. VSYNC_EDGE_IRQ - This bit is set to indicate that an interrupt is requested by the eLCDIF block + This bit is set to indicate that an interrupt is requested by the LCDIF block 8 1 read-write @@ -135250,7 +138704,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. CUR_FRAME_DONE_IRQ - This bit is set to indicate that an interrupt is requested by the eLCDIF block + This bit is set to indicate that an interrupt is requested by the LCDIF block 9 1 read-write @@ -135269,7 +138723,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. UNDERFLOW_IRQ - This bit is set to indicate that an interrupt is requested by the eLCDIF block + This bit is set to indicate that an interrupt is requested by the LCDIF block 10 1 read-write @@ -135288,7 +138742,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. OVERFLOW_IRQ - This bit is set to indicate that an interrupt is requested by the eLCDIF block + This bit is set to indicate that an interrupt is requested by the LCDIF block 11 1 read-write @@ -135342,7 +138796,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. IRQ_ON_ALTERNATE_FIELDS - If this bit is set, the eLCDIF block will assert the cur_frame_done interrupt only on alternate fields, otherwise it will issue the interrupt on both odd and even field + If this bit is set, the LCDIF block will assert the cur_frame_done interrupt only on alternate fields, otherwise it will issue the interrupt on both odd and even field 20 1 read-write @@ -135363,21 +138817,21 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. INTERLACE_FIELDS - Set this bit if it is required that the eLCDIF block fetches odd lines in one field and even lines in the other field + Set this bit if it is required that the LCDIF block fetches odd lines in one field and even lines in the other field 23 1 read-write RECOVER_ON_UNDERFLOW - Set this bit to enable the eLCDIF block to recover in the next field/frame if there was an underflow in the current field/frame + Set this bit to enable the LCDIF block to recover in the next field/frame if there was an underflow in the current field/frame 24 1 read-write BM_ERROR_IRQ - This bit is set to indicate that an interrupt is requested by the eLCDIF block + This bit is set to indicate that an interrupt is requested by the LCDIF block 25 1 read-write @@ -135396,7 +138850,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. BM_ERROR_IRQ_EN - This bit is set to enable bus master error interrupt in the eLCDIF master mode. + This bit is set to enable bus master error interrupt in the LCDIF master mode. 26 1 read-write @@ -135419,7 +138873,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. CTRL2 - eLCDIF General Control2 Register + LCDIF General Control2 Register 0x20 32 read-write @@ -135506,14 +138960,14 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. BURST_LEN_8 - By default, when the eLCDIF is in the bus master mode, it will issue AXI bursts of length 16 (except when in packed 24 bpp mode, it will issue bursts of length 15) + By default, when the LCDIF is in the bus master mode, it will issue AXI bursts of length 16 (except when in packed 24 bpp mode, it will issue bursts of length 15) 20 1 read-write OUTSTANDING_REQS - This bitfield indicates the maximum number of outstanding transactions that eLCDIF should request when it is acting as a bus master + This bitfield indicates the maximum number of outstanding transactions that LCDIF should request when it is acting as a bus master 21 3 read-write @@ -135549,7 +139003,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. CTRL2_SET - eLCDIF General Control2 Register + LCDIF General Control2 Register 0x24 32 read-write @@ -135636,14 +139090,14 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. BURST_LEN_8 - By default, when the eLCDIF is in the bus master mode, it will issue AXI bursts of length 16 (except when in packed 24 bpp mode, it will issue bursts of length 15) + By default, when the LCDIF is in the bus master mode, it will issue AXI bursts of length 16 (except when in packed 24 bpp mode, it will issue bursts of length 15) 20 1 read-write OUTSTANDING_REQS - This bitfield indicates the maximum number of outstanding transactions that eLCDIF should request when it is acting as a bus master + This bitfield indicates the maximum number of outstanding transactions that LCDIF should request when it is acting as a bus master 21 3 read-write @@ -135679,7 +139133,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. CTRL2_CLR - eLCDIF General Control2 Register + LCDIF General Control2 Register 0x28 32 read-write @@ -135766,14 +139220,14 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. BURST_LEN_8 - By default, when the eLCDIF is in the bus master mode, it will issue AXI bursts of length 16 (except when in packed 24 bpp mode, it will issue bursts of length 15) + By default, when the LCDIF is in the bus master mode, it will issue AXI bursts of length 16 (except when in packed 24 bpp mode, it will issue bursts of length 15) 20 1 read-write OUTSTANDING_REQS - This bitfield indicates the maximum number of outstanding transactions that eLCDIF should request when it is acting as a bus master + This bitfield indicates the maximum number of outstanding transactions that LCDIF should request when it is acting as a bus master 21 3 read-write @@ -135809,7 +139263,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. CTRL2_TOG - eLCDIF General Control2 Register + LCDIF General Control2 Register 0x2C 32 read-write @@ -135896,14 +139350,14 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. BURST_LEN_8 - By default, when the eLCDIF is in the bus master mode, it will issue AXI bursts of length 16 (except when in packed 24 bpp mode, it will issue bursts of length 15) + By default, when the LCDIF is in the bus master mode, it will issue AXI bursts of length 16 (except when in packed 24 bpp mode, it will issue bursts of length 15) 20 1 read-write OUTSTANDING_REQS - This bitfield indicates the maximum number of outstanding transactions that eLCDIF should request when it is acting as a bus master + This bitfield indicates the maximum number of outstanding transactions that LCDIF should request when it is acting as a bus master 21 3 read-write @@ -135939,7 +139393,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. TRANSFER_COUNT - eLCDIF Horizontal and Vertical Valid Data Count Register + LCDIF Horizontal and Vertical Valid Data Count Register 0x30 32 read-write @@ -135973,7 +139427,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ADDR - Address of the current frame being transmitted by eLCDIF. + Address of the current frame being transmitted by LCDIF. 0 32 read-write @@ -135991,7 +139445,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ADDR - Address of the next frame that will be transmitted by eLCDIF. + Address of the next frame that will be transmitted by LCDIF. 0 32 read-write @@ -136000,7 +139454,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. VDCTRL0 - eLCDIF VSYNC Mode and Dotclk Mode Control Register0 + LCDIF VSYNC Mode and Dotclk Mode Control Register0 0x70 32 read-write @@ -136081,7 +139535,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. VDCTRL0_SET - eLCDIF VSYNC Mode and Dotclk Mode Control Register0 + LCDIF VSYNC Mode and Dotclk Mode Control Register0 0x74 32 read-write @@ -136162,7 +139616,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. VDCTRL0_CLR - eLCDIF VSYNC Mode and Dotclk Mode Control Register0 + LCDIF VSYNC Mode and Dotclk Mode Control Register0 0x78 32 read-write @@ -136243,7 +139697,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. VDCTRL0_TOG - eLCDIF VSYNC Mode and Dotclk Mode Control Register0 + LCDIF VSYNC Mode and Dotclk Mode Control Register0 0x7C 32 read-write @@ -136324,7 +139778,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. VDCTRL1 - eLCDIF VSYNC Mode and Dotclk Mode Control Register1 + LCDIF VSYNC Mode and Dotclk Mode Control Register1 0x80 32 read-write @@ -136367,7 +139821,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. VDCTRL3 - eLCDIF VSYNC Mode and Dotclk Mode Control Register3 + LCDIF VSYNC Mode and Dotclk Mode Control Register3 0xA0 32 read-write @@ -136397,7 +139851,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. MUX_SYNC_SIGNALS - When this bit is set, the eLCDIF block will internally mux HSYNC with LCD_D14, DOTCLK with LCD_D13 and ENABLE with LCD_D12, otherwise these signals will go out on separate pins + When this bit is set, the LCDIF block will internally mux HSYNC with LCD_D14, DOTCLK with LCD_D13 and ENABLE with LCD_D12, otherwise these signals will go out on separate pins 29 1 read-write @@ -136406,7 +139860,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. VDCTRL4 - eLCDIF VSYNC Mode and Dotclk Mode Control Register4 + LCDIF VSYNC Mode and Dotclk Mode Control Register4 0xB0 32 read-write @@ -136518,14 +139972,14 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. DMA_REQ - Reflects the current state of the DMA Request line for the eLCDIF + Reflects the current state of the DMA Request line for the LCDIF 30 1 read-only PRESENT - 0: eLCDIF not present on this product 1: eLCDIF is present. + 0: LCDIF not present on this product 1: LCDIF is present. 31 1 read-only @@ -136534,7 +139988,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. THRES - eLCDIF Threshold Register + LCDIF Threshold Register 0x200 32 read-write @@ -140120,7 +143574,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. LUT_BYPASS - This bit controls whether the pixels entering the CSC2 unit get converted or not + Setting this bit will bypass the LUT memory resource completely 0 1 read-write @@ -141000,42 +144454,42 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. RxFF_LEVEL_0 - 4 Words + 4 Double words 0 RxFF_LEVEL_1 - 8 Words + 8 Double words 0x1 RxFF_LEVEL_2 - 16 Words + 16 Double words 0x2 RxFF_LEVEL_3 - 24 Words + 24 Double words 0x3 RxFF_LEVEL_4 - 32 Words + 32 Double words 0x4 RxFF_LEVEL_5 - 48 Words + 48 Double words 0x5 RxFF_LEVEL_6 - 64 Words + 64 Double words 0x6 RxFF_LEVEL_7 - 96 Words + 96 Double words 0x7 @@ -141068,42 +144522,42 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. STATFF_LEVEL_0 - 4 Words + 4 Double words 0 STATFF_LEVEL_1 - 8 Words + 8 Double words 0x1 STATFF_LEVEL_2 - 12 Words + 12 Double words 0x2 STATFF_LEVEL_3 - 16 Words + 16 Double words 0x3 STATFF_LEVEL_4 - 24 Words + 24 Double words 0x4 STATFF_LEVEL_5 - 32 Words + 32 Double words 0x5 STATFF_LEVEL_6 - 48 Words + 48 Double words 0x6 STATFF_LEVEL_7 - 64 Words + 64 Double words 0x7 @@ -141856,35 +145310,6 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 4 read-write - - CSI_LCDIF_BUFFER_LINES - The number of lines are used in handshake mode with LCDIF. - 16 - 2 - read-write - - - CSI_LCDIF_BUFFER_LINES_0 - 4 lines - 0 - - - CSI_LCDIF_BUFFER_LINES_1 - 8 lines - 0x1 - - - CSI_LCDIF_BUFFER_LINES_2 - 16 lines - 0x2 - - - CSI_LCDIF_BUFFER_LINES_3 - 16 lines - 0x3 - - - MASK_OPTION These bits used to choose the method to mask the CSI input. @@ -143040,7 +146465,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0x2C 32 read-write - 0x8080800F + 0x80800F 0xFFFFFFFF @@ -145267,7 +148692,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0x60 32 read-write - 0x200 + 0 0xFFFFFFFF @@ -145348,7 +148773,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0x64 32 read-only - 0 + 0x200 0xFFFFFFFF @@ -145814,8 +149239,15 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - AHB_RST - AHB BUS reset + PART_DLL_DEBUG + debug for part dll + 13 + 1 + read-write + + + BUS_RST + BUS reset 14 1 read-write @@ -150484,7 +153916,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0x164 32 read-write - 0xA0000 + 0 0xFFFFFFFF @@ -152363,7 +155795,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. MDIS_1 - Master disabled. + Module disabled. 0x1 @@ -153864,7 +157296,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0x24 32 read-write - 0x9000001E + 0x90000018 0xFFFFFFFF @@ -154058,7 +157490,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0x28 32 read-write - 0x9800001C + 0x98000018 0xFFFFFFFF @@ -154677,7 +158109,6 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 4 1 read-write - oneToClear NDPAGEENDEN_0 @@ -154697,7 +158128,6 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 5 1 read-write - oneToClear NDNOPENDEN_0 @@ -156500,14 +159930,14 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. REL - RDX Low Time + RDX Low Time bit [3:0] 16 4 read-write REH - RDX High Time + RDX High Time bit [3:0] 20 4 read-write @@ -156519,6 +159949,20 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 4 read-write + + REL2 + RDX Low Time bit [5:4] + 28 + 2 + read-write + + + REH2 + RDX High Time bit [5:4] + 30 + 2 + read-write + @@ -161684,12 +165128,12 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. RST_0 - Master logic is not reset + Module is not reset 0 RST_1 - Master logic is reset + Module is reset 0x1 @@ -163102,9 +166546,16 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 8 read-write + + DMA_MODE_SEL + 1'b0: Trig DMA_REQ with latched signal, REQ will be cleared when ACK and source request cleared + 29 + 1 + read-write + TSC_BYPASS - 1'b1: TSC is bypassed; 1'b0: TSC not bypassed; + 1'b1: TSC is bypassed to ADC2. 1'b0: TSC not bypassed. To use ADC2, this bit should be cleared. 30 1 read-write @@ -163576,7 +167027,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. HWTS0 - CHAIN0 HWTS ADC hardware trigger selection + CHAIN0 HWTS ADC hardware trigger selection. For more information, see the ADC chapter. 4 8 read-write @@ -163604,7 +167055,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. HWTS1 - CHAIN1 HWTS ADC hardware trigger selection + CHAIN1 HWTS ADC hardware trigger selection. For more information, see the ADC chapter. 20 8 read-write @@ -181692,7 +185143,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. AC_PROT_EN - Enable access permission control + Enable access permission control When AC_PROT_EN is asserted, all encrypted regions are limited to be ARM core access only 6 1 read-write @@ -181879,7 +185330,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ADDR_OFFSET0 - Address offset used to remap received address to output address of memory region0 + Signed offset for BEE region 0 0 16 read-write @@ -181903,14 +185354,14 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0xFFFFFFFF - ADDR_OFFSET0 - Address offset used to remap received address to output address of memory region1 + ADDR_OFFSET1 + Signed offset for BEE region 1 0 16 read-write - ADDR_OFFSET0_LOCK + ADDR_OFFSET1_LOCK Lock bits for addr_offset1 16 16 @@ -182001,7 +185452,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. IRQ_VEC - bit 7: Protected region-3 access violation bit 6: Protected region-2 access violation bit 5: Protected region-1 access violation bit 4: Protected region-0 access violation bit 3: Region-1 read channel security violation bit 2: Read channel illegal access detected bit 1: Region-0 Read channel security violation bit 0: Disable abort + bit 7: Protected region-3 access violation bit 6: Protected region-2 access violation bit 5: Protected region-1 access violation bit 4: Protected region-0 access violation bit 3: Region-1 read channel security violation bit 2: Read channel illegal access detected bit 1: Region-0 read channel security violation bit 0: Disable abort 0 8 read-write @@ -182009,7 +185460,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. BEE_IDLE - Lock bits for addr_offset1 + 1'b1: BEE is idle; 1'b0: BEE is active 8 1 read-only @@ -189476,19 +192927,19 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 60 - ANATOP_EVENT0 + PMU_EVENT 61 - ANATOP_EVENT1 + Reserved78 62 - ANATOP_TAMP_LOW_HIGH + TEMP_LOW_HIGH 63 - ANATOP_TEMP_PANIC + TEMP_PANIC 64 @@ -189835,38 +193286,6 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. PWM4_FAULT 151 - - Reserved168 - 152 - - - Reserved169 - 153 - - - Reserved170 - 154 - - - Reserved171 - 155 - - - Reserved172 - 156 - - - Reserved173 - 157 - - - SJC_ARM_DEBUG - 158 - - - NMI_WAKEUP - 159 - NVICISER0 @@ -191447,7 +194866,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. PRI61 - Priority of the INT_ANATOP_EVENT0 interrupt 61 + Priority of the INT_PMU_EVENT interrupt 61 4 4 read-write @@ -191465,7 +194884,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. PRI62 - Priority of the INT_ANATOP_EVENT1 interrupt 62 + Priority of the INT_Reserved78 interrupt 62 4 4 read-write @@ -191483,7 +194902,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. PRI63 - Priority of the INT_ANATOP_TAMP_LOW_HIGH interrupt 63 + Priority of the INT_TEMP_LOW_HIGH interrupt 63 4 4 read-write @@ -191501,7 +194920,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. PRI64 - Priority of the INT_ANATOP_TEMP_PANIC interrupt 64 + Priority of the INT_TEMP_PANIC interrupt 64 4 4 read-write @@ -193074,150 +196493,6 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - - NVICIP152 - Interrupt Priority Register 152 - 0x398 - 8 - read-write - 0 - 0xFF - - - PRI152 - Priority of the INT_Reserved168 interrupt 152 - 4 - 4 - read-write - - - - - NVICIP153 - Interrupt Priority Register 153 - 0x399 - 8 - read-write - 0 - 0xFF - - - PRI153 - Priority of the INT_Reserved169 interrupt 153 - 4 - 4 - read-write - - - - - NVICIP154 - Interrupt Priority Register 154 - 0x39A - 8 - read-write - 0 - 0xFF - - - PRI154 - Priority of the INT_Reserved170 interrupt 154 - 4 - 4 - read-write - - - - - NVICIP155 - Interrupt Priority Register 155 - 0x39B - 8 - read-write - 0 - 0xFF - - - PRI155 - Priority of the INT_Reserved171 interrupt 155 - 4 - 4 - read-write - - - - - NVICIP156 - Interrupt Priority Register 156 - 0x39C - 8 - read-write - 0 - 0xFF - - - PRI156 - Priority of the INT_Reserved172 interrupt 156 - 4 - 4 - read-write - - - - - NVICIP157 - Interrupt Priority Register 157 - 0x39D - 8 - read-write - 0 - 0xFF - - - PRI157 - Priority of the INT_Reserved173 interrupt 157 - 4 - 4 - read-write - - - - - NVICIP158 - Interrupt Priority Register 158 - 0x39E - 8 - read-write - 0 - 0xFF - - - PRI158 - Priority of the INT_SJC_ARM_DEBUG interrupt 158 - 4 - 4 - read-write - - - - - NVICIP159 - Interrupt Priority Register 159 - 0x39F - 8 - read-write - 0 - 0xFF - - - PRI159 - Priority of the INT_NMI_WAKEUP interrupt 159 - 4 - 4 - read-write - - - NVICSTIR Software Trigger Interrupt Register diff --git a/ext/hal/nxp/mcux/devices/MIMXRT1052/MIMXRT1052_features.h b/ext/hal/nxp/mcux/devices/MIMXRT1052/MIMXRT1052_features.h index 9d00377b19b..7ccb7401570 100644 --- a/ext/hal/nxp/mcux/devices/MIMXRT1052/MIMXRT1052_features.h +++ b/ext/hal/nxp/mcux/devices/MIMXRT1052/MIMXRT1052_features.h @@ -1,37 +1,16 @@ /* ** ################################################################### -** Version: rev. 0.1, 2017-01-10 -** Build: b171017 +** Version: rev. 1.1, 2018-11-16 +** Build: b181120 ** ** Abstract: ** Chip specific module features. ** ** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2017 NXP -** Redistribution and use in source and binary forms, with or without modification, -** are permitted provided that the following conditions are met: +** Copyright 2016-2018 NXP +** All rights reserved. ** -** 1. Redistributions of source code must retain the above copyright notice, this list -** of conditions and the following disclaimer. -** -** 2. Redistributions in binary form must reproduce the above copyright notice, this -** list of conditions and the following disclaimer in the documentation and/or -** other materials provided with the distribution. -** -** 3. Neither the name of the copyright holder nor the names of its -** contributors may be used to endorse or promote products derived from this -** software without specific prior written permission. -** -** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** SPDX-License-Identifier: BSD-3-Clause ** ** http: www.nxp.com ** mail: support@nxp.com @@ -39,6 +18,12 @@ ** Revisions: ** - rev. 0.1 (2017-01-10) ** Initial version. +** - rev. 1.0 (2018-09-21) +** Update interrupt vector table and dma request source. +** Update register BEE_ADDR_OFFSET1's bitfield name to ADDR_OFFSET1. +** Split GPIO_COMBINED_IRQS to GPIO_COMBINED_LOW_IRQS and GPIO_COMBINED_HIGH_IRQS. +** - rev. 1.1 (2018-11-16) +** Update feature files to align with IMXRT1050RM Rev.1. ** ** ################################################################### */ @@ -48,532 +33,110 @@ /* SOC module features */ -/* @brief ACMP availability on the SoC. */ -#define FSL_FEATURE_SOC_ACMP_COUNT (0) /* @brief ADC availability on the SoC. */ #define FSL_FEATURE_SOC_ADC_COUNT (2) -/* @brief ADC12 availability on the SoC. */ -#define FSL_FEATURE_SOC_ADC12_COUNT (0) -/* @brief ADC16 availability on the SoC. */ -#define FSL_FEATURE_SOC_ADC16_COUNT (0) -/* @brief ADC_5HC availability on the SoC. */ -#define FSL_FEATURE_SOC_ADC_5HC_COUNT (0) -/* @brief AES availability on the SoC. */ -#define FSL_FEATURE_SOC_AES_COUNT (0) -/* @brief AFE availability on the SoC. */ -#define FSL_FEATURE_SOC_AFE_COUNT (0) -/* @brief AGC availability on the SoC. */ -#define FSL_FEATURE_SOC_AGC_COUNT (0) -/* @brief AIPS availability on the SoC. */ -#define FSL_FEATURE_SOC_AIPS_COUNT (0) /* @brief AIPSTZ availability on the SoC. */ #define FSL_FEATURE_SOC_AIPSTZ_COUNT (4) -/* @brief ANATOP availability on the SoC. */ -#define FSL_FEATURE_SOC_ANATOP_COUNT (0) /* @brief AOI availability on the SoC. */ #define FSL_FEATURE_SOC_AOI_COUNT (2) -/* @brief APBH availability on the SoC. */ -#define FSL_FEATURE_SOC_APBH_COUNT (0) -/* @brief ASMC availability on the SoC. */ -#define FSL_FEATURE_SOC_ASMC_COUNT (0) -/* @brief ASRC availability on the SoC. */ -#define FSL_FEATURE_SOC_ASRC_COUNT (0) -/* @brief ASYNC_SYSCON availability on the SoC. */ -#define FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT (0) -/* @brief ATX availability on the SoC. */ -#define FSL_FEATURE_SOC_ATX_COUNT (0) -/* @brief AXBS availability on the SoC. */ -#define FSL_FEATURE_SOC_AXBS_COUNT (0) -/* @brief BCH availability on the SoC. */ -#define FSL_FEATURE_SOC_BCH_COUNT (0) -/* @brief BLEDP availability on the SoC. */ -#define FSL_FEATURE_SOC_BLEDP_COUNT (0) -/* @brief BOD availability on the SoC. */ -#define FSL_FEATURE_SOC_BOD_COUNT (0) -/* @brief CAAM availability on the SoC. */ -#define FSL_FEATURE_SOC_CAAM_COUNT (0) -/* @brief CADC availability on the SoC. */ -#define FSL_FEATURE_SOC_CADC_COUNT (0) -/* @brief CALIB availability on the SoC. */ -#define FSL_FEATURE_SOC_CALIB_COUNT (0) -/* @brief CAN availability on the SoC. */ -#define FSL_FEATURE_SOC_CAN_COUNT (0) -/* @brief CAU availability on the SoC. */ -#define FSL_FEATURE_SOC_CAU_COUNT (0) -/* @brief CAU3 availability on the SoC. */ -#define FSL_FEATURE_SOC_CAU3_COUNT (0) /* @brief CCM availability on the SoC. */ #define FSL_FEATURE_SOC_CCM_COUNT (1) /* @brief CCM_ANALOG availability on the SoC. */ #define FSL_FEATURE_SOC_CCM_ANALOG_COUNT (1) -/* @brief CHRG availability on the SoC. */ -#define FSL_FEATURE_SOC_CHRG_COUNT (0) -/* @brief CLKCTL0 availability on the SoC. */ -#define FSL_FEATURE_SOC_CLKCTL0_COUNT (0) -/* @brief CLKCTL1 availability on the SoC. */ -#define FSL_FEATURE_SOC_CLKCTL1_COUNT (0) /* @brief CMP availability on the SoC. */ #define FSL_FEATURE_SOC_CMP_COUNT (4) -/* @brief CMT availability on the SoC. */ -#define FSL_FEATURE_SOC_CMT_COUNT (0) -/* @brief CNC availability on the SoC. */ -#define FSL_FEATURE_SOC_CNC_COUNT (0) -/* @brief COP availability on the SoC. */ -#define FSL_FEATURE_SOC_COP_COUNT (0) -/* @brief CRC availability on the SoC. */ -#define FSL_FEATURE_SOC_CRC_COUNT (0) -/* @brief CS availability on the SoC. */ -#define FSL_FEATURE_SOC_CS_COUNT (0) /* @brief CSI availability on the SoC. */ #define FSL_FEATURE_SOC_CSI_COUNT (1) -/* @brief CT32B availability on the SoC. */ -#define FSL_FEATURE_SOC_CT32B_COUNT (0) -/* @brief CTI availability on the SoC. */ -#define FSL_FEATURE_SOC_CTI_COUNT (0) -/* @brief CTIMER availability on the SoC. */ -#define FSL_FEATURE_SOC_CTIMER_COUNT (0) -/* @brief DAC availability on the SoC. */ -#define FSL_FEATURE_SOC_DAC_COUNT (0) -/* @brief DAC32 availability on the SoC. */ -#define FSL_FEATURE_SOC_DAC32_COUNT (0) /* @brief DCDC availability on the SoC. */ #define FSL_FEATURE_SOC_DCDC_COUNT (1) /* @brief DCP availability on the SoC. */ #define FSL_FEATURE_SOC_DCP_COUNT (1) -/* @brief DDR availability on the SoC. */ -#define FSL_FEATURE_SOC_DDR_COUNT (0) -/* @brief DDRC availability on the SoC. */ -#define FSL_FEATURE_SOC_DDRC_COUNT (0) -/* @brief DDRC_MP availability on the SoC. */ -#define FSL_FEATURE_SOC_DDRC_MP_COUNT (0) -/* @brief DDR_PHY availability on the SoC. */ -#define FSL_FEATURE_SOC_DDR_PHY_COUNT (0) -/* @brief DMA availability on the SoC. */ -#define FSL_FEATURE_SOC_DMA_COUNT (0) /* @brief DMAMUX availability on the SoC. */ #define FSL_FEATURE_SOC_DMAMUX_COUNT (1) -/* @brief DMIC availability on the SoC. */ -#define FSL_FEATURE_SOC_DMIC_COUNT (0) -/* @brief DRY availability on the SoC. */ -#define FSL_FEATURE_SOC_DRY_COUNT (0) -/* @brief DSPI availability on the SoC. */ -#define FSL_FEATURE_SOC_DSPI_COUNT (0) -/* @brief ECSPI availability on the SoC. */ -#define FSL_FEATURE_SOC_ECSPI_COUNT (0) /* @brief EDMA availability on the SoC. */ #define FSL_FEATURE_SOC_EDMA_COUNT (1) -/* @brief EEPROM availability on the SoC. */ -#define FSL_FEATURE_SOC_EEPROM_COUNT (0) -/* @brief EIM availability on the SoC. */ -#define FSL_FEATURE_SOC_EIM_COUNT (0) -/* @brief EMC availability on the SoC. */ -#define FSL_FEATURE_SOC_EMC_COUNT (0) -/* @brief EMVSIM availability on the SoC. */ -#define FSL_FEATURE_SOC_EMVSIM_COUNT (0) /* @brief ENC availability on the SoC. */ #define FSL_FEATURE_SOC_ENC_COUNT (4) /* @brief ENET availability on the SoC. */ #define FSL_FEATURE_SOC_ENET_COUNT (1) -/* @brief EPDC availability on the SoC. */ -#define FSL_FEATURE_SOC_EPDC_COUNT (0) -/* @brief EPIT availability on the SoC. */ -#define FSL_FEATURE_SOC_EPIT_COUNT (0) -/* @brief ESAI availability on the SoC. */ -#define FSL_FEATURE_SOC_ESAI_COUNT (0) /* @brief EWM availability on the SoC. */ #define FSL_FEATURE_SOC_EWM_COUNT (1) -/* @brief FB availability on the SoC. */ -#define FSL_FEATURE_SOC_FB_COUNT (0) -/* @brief FGPIO availability on the SoC. */ -#define FSL_FEATURE_SOC_FGPIO_COUNT (0) -/* @brief FLASH availability on the SoC. */ -#define FSL_FEATURE_SOC_FLASH_COUNT (0) /* @brief FLEXCAN availability on the SoC. */ #define FSL_FEATURE_SOC_FLEXCAN_COUNT (2) -/* @brief FLEXCOMM availability on the SoC. */ -#define FSL_FEATURE_SOC_FLEXCOMM_COUNT (0) /* @brief FLEXIO availability on the SoC. */ #define FSL_FEATURE_SOC_FLEXIO_COUNT (2) /* @brief FLEXRAM availability on the SoC. */ #define FSL_FEATURE_SOC_FLEXRAM_COUNT (1) /* @brief FLEXSPI availability on the SoC. */ #define FSL_FEATURE_SOC_FLEXSPI_COUNT (1) -/* @brief FMC availability on the SoC. */ -#define FSL_FEATURE_SOC_FMC_COUNT (0) -/* @brief FREQME availability on the SoC. */ -#define FSL_FEATURE_SOC_FREQME_COUNT (0) -/* @brief FSKDT availability on the SoC. */ -#define FSL_FEATURE_SOC_FSKDT_COUNT (0) -/* @brief FSP availability on the SoC. */ -#define FSL_FEATURE_SOC_FSP_COUNT (0) -/* @brief FTFA availability on the SoC. */ -#define FSL_FEATURE_SOC_FTFA_COUNT (0) -/* @brief FTFE availability on the SoC. */ -#define FSL_FEATURE_SOC_FTFE_COUNT (0) -/* @brief FTFL availability on the SoC. */ -#define FSL_FEATURE_SOC_FTFL_COUNT (0) -/* @brief FTM availability on the SoC. */ -#define FSL_FEATURE_SOC_FTM_COUNT (0) -/* @brief FTMRA availability on the SoC. */ -#define FSL_FEATURE_SOC_FTMRA_COUNT (0) -/* @brief FTMRE availability on the SoC. */ -#define FSL_FEATURE_SOC_FTMRE_COUNT (0) -/* @brief FTMRH availability on the SoC. */ -#define FSL_FEATURE_SOC_FTMRH_COUNT (0) -/* @brief GINT availability on the SoC. */ -#define FSL_FEATURE_SOC_GINT_COUNT (0) /* @brief GPC availability on the SoC. */ #define FSL_FEATURE_SOC_GPC_COUNT (1) -/* @brief GPC_PGC availability on the SoC. */ -#define FSL_FEATURE_SOC_GPC_PGC_COUNT (0) -/* @brief GPIO availability on the SoC. */ -#define FSL_FEATURE_SOC_GPIO_COUNT (0) -/* @brief GPMI availability on the SoC. */ -#define FSL_FEATURE_SOC_GPMI_COUNT (0) /* @brief GPT availability on the SoC. */ #define FSL_FEATURE_SOC_GPT_COUNT (2) -/* @brief HASH availability on the SoC. */ -#define FSL_FEATURE_SOC_HASH_COUNT (0) -/* @brief HSADC availability on the SoC. */ -#define FSL_FEATURE_SOC_HSADC_COUNT (0) -/* @brief I2C availability on the SoC. */ -#define FSL_FEATURE_SOC_I2C_COUNT (0) /* @brief I2S availability on the SoC. */ #define FSL_FEATURE_SOC_I2S_COUNT (3) -/* @brief ICS availability on the SoC. */ -#define FSL_FEATURE_SOC_ICS_COUNT (0) -/* @brief IEE availability on the SoC. */ -#define FSL_FEATURE_SOC_IEE_COUNT (0) -/* @brief IEER availability on the SoC. */ -#define FSL_FEATURE_SOC_IEER_COUNT (0) /* @brief IGPIO availability on the SoC. */ #define FSL_FEATURE_SOC_IGPIO_COUNT (5) -/* @brief II2C availability on the SoC. */ -#define FSL_FEATURE_SOC_II2C_COUNT (0) -/* @brief INPUTMUX availability on the SoC. */ -#define FSL_FEATURE_SOC_INPUTMUX_COUNT (0) -/* @brief INTMUX availability on the SoC. */ -#define FSL_FEATURE_SOC_INTMUX_COUNT (0) -/* @brief IOCON availability on the SoC. */ -#define FSL_FEATURE_SOC_IOCON_COUNT (0) /* @brief IOMUXC availability on the SoC. */ #define FSL_FEATURE_SOC_IOMUXC_COUNT (1) /* @brief IOMUXC_GPR availability on the SoC. */ #define FSL_FEATURE_SOC_IOMUXC_GPR_COUNT (1) -/* @brief IOMUXC_LPSR availability on the SoC. */ -#define FSL_FEATURE_SOC_IOMUXC_LPSR_COUNT (0) -/* @brief IOMUXC_LPSR_GPR availability on the SoC. */ -#define FSL_FEATURE_SOC_IOMUXC_LPSR_GPR_COUNT (0) /* @brief IOMUXC_SNVS availability on the SoC. */ #define FSL_FEATURE_SOC_IOMUXC_SNVS_COUNT (1) -/* @brief IOPCTL availability on the SoC. */ -#define FSL_FEATURE_SOC_IOPCTL_COUNT (0) -/* @brief IPWM availability on the SoC. */ -#define FSL_FEATURE_SOC_IPWM_COUNT (0) -/* @brief IRQ availability on the SoC. */ -#define FSL_FEATURE_SOC_IRQ_COUNT (0) -/* @brief IUART availability on the SoC. */ -#define FSL_FEATURE_SOC_IUART_COUNT (0) -/* @brief KBI availability on the SoC. */ -#define FSL_FEATURE_SOC_KBI_COUNT (0) /* @brief KPP availability on the SoC. */ #define FSL_FEATURE_SOC_KPP_COUNT (1) -/* @brief L2CACHEC availability on the SoC. */ -#define FSL_FEATURE_SOC_L2CACHEC_COUNT (0) -/* @brief LCD availability on the SoC. */ -#define FSL_FEATURE_SOC_LCD_COUNT (0) -/* @brief LCDC availability on the SoC. */ -#define FSL_FEATURE_SOC_LCDC_COUNT (0) /* @brief LCDIF availability on the SoC. */ #define FSL_FEATURE_SOC_LCDIF_COUNT (1) -/* @brief LDO availability on the SoC. */ -#define FSL_FEATURE_SOC_LDO_COUNT (0) -/* @brief LLWU availability on the SoC. */ -#define FSL_FEATURE_SOC_LLWU_COUNT (0) -/* @brief LMEM availability on the SoC. */ -#define FSL_FEATURE_SOC_LMEM_COUNT (0) -/* @brief LPADC availability on the SoC. */ -#define FSL_FEATURE_SOC_LPADC_COUNT (0) -/* @brief LPCMP availability on the SoC. */ -#define FSL_FEATURE_SOC_LPCMP_COUNT (0) -/* @brief LPDAC availability on the SoC. */ -#define FSL_FEATURE_SOC_LPDAC_COUNT (0) /* @brief LPI2C availability on the SoC. */ #define FSL_FEATURE_SOC_LPI2C_COUNT (4) -/* @brief LPIT availability on the SoC. */ -#define FSL_FEATURE_SOC_LPIT_COUNT (0) -/* @brief LPSCI availability on the SoC. */ -#define FSL_FEATURE_SOC_LPSCI_COUNT (0) /* @brief LPSPI availability on the SoC. */ #define FSL_FEATURE_SOC_LPSPI_COUNT (4) -/* @brief LPTMR availability on the SoC. */ -#define FSL_FEATURE_SOC_LPTMR_COUNT (0) -/* @brief LPTPM availability on the SoC. */ -#define FSL_FEATURE_SOC_LPTPM_COUNT (0) /* @brief LPUART availability on the SoC. */ #define FSL_FEATURE_SOC_LPUART_COUNT (8) -/* @brief LTC availability on the SoC. */ -#define FSL_FEATURE_SOC_LTC_COUNT (0) -/* @brief MAILBOX availability on the SoC. */ -#define FSL_FEATURE_SOC_MAILBOX_COUNT (0) -/* @brief MC availability on the SoC. */ -#define FSL_FEATURE_SOC_MC_COUNT (0) -/* @brief MCG availability on the SoC. */ -#define FSL_FEATURE_SOC_MCG_COUNT (0) -/* @brief MCGLITE availability on the SoC. */ -#define FSL_FEATURE_SOC_MCGLITE_COUNT (0) -/* @brief MCM availability on the SoC. */ -#define FSL_FEATURE_SOC_MCM_COUNT (0) -/* @brief MIPI_CSI2 availability on the SoC. */ -#define FSL_FEATURE_SOC_MIPI_CSI2_COUNT (0) -/* @brief MIPI_CSI2RX availability on the SoC. */ -#define FSL_FEATURE_SOC_MIPI_CSI2RX_COUNT (0) -/* @brief MIPI_DSI availability on the SoC. */ -#define FSL_FEATURE_SOC_MIPI_DSI_COUNT (0) -/* @brief MIPI_DSI_HOST availability on the SoC. */ -#define FSL_FEATURE_SOC_MIPI_DSI_HOST_COUNT (0) -/* @brief MMAU availability on the SoC. */ -#define FSL_FEATURE_SOC_MMAU_COUNT (0) -/* @brief MMCAU availability on the SoC. */ -#define FSL_FEATURE_SOC_MMCAU_COUNT (0) -/* @brief MMDC availability on the SoC. */ -#define FSL_FEATURE_SOC_MMDC_COUNT (0) -/* @brief MMDVSQ availability on the SoC. */ -#define FSL_FEATURE_SOC_MMDVSQ_COUNT (0) -/* @brief MPU availability on the SoC. */ -#define FSL_FEATURE_SOC_MPU_COUNT (0) -/* @brief MRT availability on the SoC. */ -#define FSL_FEATURE_SOC_MRT_COUNT (0) -/* @brief MSCAN availability on the SoC. */ -#define FSL_FEATURE_SOC_MSCAN_COUNT (0) -/* @brief MSCM availability on the SoC. */ -#define FSL_FEATURE_SOC_MSCM_COUNT (0) -/* @brief MTB availability on the SoC. */ -#define FSL_FEATURE_SOC_MTB_COUNT (0) -/* @brief MTBDWT availability on the SoC. */ -#define FSL_FEATURE_SOC_MTBDWT_COUNT (0) -/* @brief MU availability on the SoC. */ -#define FSL_FEATURE_SOC_MU_COUNT (0) -/* @brief NFC availability on the SoC. */ -#define FSL_FEATURE_SOC_NFC_COUNT (0) /* @brief OCOTP availability on the SoC. */ #define FSL_FEATURE_SOC_OCOTP_COUNT (1) -/* @brief OPAMP availability on the SoC. */ -#define FSL_FEATURE_SOC_OPAMP_COUNT (0) -/* @brief OTPC availability on the SoC. */ -#define FSL_FEATURE_SOC_OTPC_COUNT (0) -/* @brief OSC availability on the SoC. */ -#define FSL_FEATURE_SOC_OSC_COUNT (0) -/* @brief OSC32 availability on the SoC. */ -#define FSL_FEATURE_SOC_OSC32_COUNT (0) -/* @brief OTFAD availability on the SoC. */ -#define FSL_FEATURE_SOC_OTFAD_COUNT (0) -/* @brief PCC availability on the SoC. */ -#define FSL_FEATURE_SOC_PCC_COUNT (0) -/* @brief PCIE_PHY_CMN availability on the SoC. */ -#define FSL_FEATURE_SOC_PCIE_PHY_CMN_COUNT (0) -/* @brief PCIE_PHY_TRSV availability on the SoC. */ -#define FSL_FEATURE_SOC_PCIE_PHY_TRSV_COUNT (0) -/* @brief PDB availability on the SoC. */ -#define FSL_FEATURE_SOC_PDB_COUNT (0) -/* @brief PGA availability on the SoC. */ -#define FSL_FEATURE_SOC_PGA_COUNT (0) -/* @brief PIMCTL availability on the SoC. */ -#define FSL_FEATURE_SOC_PIMCTL_COUNT (0) -/* @brief PINT availability on the SoC. */ -#define FSL_FEATURE_SOC_PINT_COUNT (0) /* @brief PIT availability on the SoC. */ #define FSL_FEATURE_SOC_PIT_COUNT (1) -/* @brief PMC availability on the SoC. */ -#define FSL_FEATURE_SOC_PMC_COUNT (0) /* @brief PMU availability on the SoC. */ #define FSL_FEATURE_SOC_PMU_COUNT (1) -/* @brief POWERQUAD availability on the SoC. */ -#define FSL_FEATURE_SOC_POWERQUAD_COUNT (0) -/* @brief PORT availability on the SoC. */ -#define FSL_FEATURE_SOC_PORT_COUNT (0) -/* @brief PROP availability on the SoC. */ -#define FSL_FEATURE_SOC_PROP_COUNT (0) /* @brief PWM availability on the SoC. */ #define FSL_FEATURE_SOC_PWM_COUNT (4) -/* @brief PWT availability on the SoC. */ -#define FSL_FEATURE_SOC_PWT_COUNT (0) /* @brief PXP availability on the SoC. */ #define FSL_FEATURE_SOC_PXP_COUNT (1) -/* @brief QDDKEY availability on the SoC. */ -#define FSL_FEATURE_SOC_QDDKEY_COUNT (0) -/* @brief QDEC availability on the SoC. */ -#define FSL_FEATURE_SOC_QDEC_COUNT (0) -/* @brief QuadSPI availability on the SoC. */ -#define FSL_FEATURE_SOC_QuadSPI_COUNT (0) -/* @brief RCM availability on the SoC. */ -#define FSL_FEATURE_SOC_RCM_COUNT (0) -/* @brief RDC availability on the SoC. */ -#define FSL_FEATURE_SOC_RDC_COUNT (0) -/* @brief RDC_SEMAPHORE availability on the SoC. */ -#define FSL_FEATURE_SOC_RDC_SEMAPHORE_COUNT (0) -/* @brief RFSYS availability on the SoC. */ -#define FSL_FEATURE_SOC_RFSYS_COUNT (0) -/* @brief RFVBAT availability on the SoC. */ -#define FSL_FEATURE_SOC_RFVBAT_COUNT (0) -/* @brief RIT availability on the SoC. */ -#define FSL_FEATURE_SOC_RIT_COUNT (0) -/* @brief RNG availability on the SoC. */ -#define FSL_FEATURE_SOC_RNG_COUNT (0) -/* @brief RNGB availability on the SoC. */ -#define FSL_FEATURE_SOC_RNGB_COUNT (0) -/* @brief ROM availability on the SoC. */ -#define FSL_FEATURE_SOC_ROM_COUNT (0) /* @brief ROMC availability on the SoC. */ #define FSL_FEATURE_SOC_ROMC_COUNT (1) -/* @brief RSIM availability on the SoC. */ -#define FSL_FEATURE_SOC_RSIM_COUNT (0) -/* @brief RSTCTL0 availability on the SoC. */ -#define FSL_FEATURE_SOC_RSTCTL0_COUNT (0) -/* @brief RSTCTL1 availability on the SoC. */ -#define FSL_FEATURE_SOC_RSTCTL1_COUNT (0) -/* @brief RTC availability on the SoC. */ -#define FSL_FEATURE_SOC_RTC_COUNT (0) -/* @brief SCG availability on the SoC. */ -#define FSL_FEATURE_SOC_SCG_COUNT (0) -/* @brief SCI availability on the SoC. */ -#define FSL_FEATURE_SOC_SCI_COUNT (0) -/* @brief SCT availability on the SoC. */ -#define FSL_FEATURE_SOC_SCT_COUNT (0) -/* @brief SDHC availability on the SoC. */ -#define FSL_FEATURE_SOC_SDHC_COUNT (0) -/* @brief SDIF availability on the SoC. */ -#define FSL_FEATURE_SOC_SDIF_COUNT (0) -/* @brief SDIO availability on the SoC. */ -#define FSL_FEATURE_SOC_SDIO_COUNT (0) -/* @brief SDMA availability on the SoC. */ -#define FSL_FEATURE_SOC_SDMA_COUNT (0) -/* @brief SDMAARM availability on the SoC. */ -#define FSL_FEATURE_SOC_SDMAARM_COUNT (0) -/* @brief SDMABP availability on the SoC. */ -#define FSL_FEATURE_SOC_SDMABP_COUNT (0) -/* @brief SDMACORE availability on the SoC. */ -#define FSL_FEATURE_SOC_SDMACORE_COUNT (0) -/* @brief SDMCORE availability on the SoC. */ -#define FSL_FEATURE_SOC_SDMCORE_COUNT (0) -/* @brief SDRAM availability on the SoC. */ -#define FSL_FEATURE_SOC_SDRAM_COUNT (0) -/* @brief SEMA4 availability on the SoC. */ -#define FSL_FEATURE_SOC_SEMA4_COUNT (0) -/* @brief SEMA42 availability on the SoC. */ -#define FSL_FEATURE_SOC_SEMA42_COUNT (0) /* @brief SEMC availability on the SoC. */ #define FSL_FEATURE_SOC_SEMC_COUNT (1) -/* @brief SHA availability on the SoC. */ -#define FSL_FEATURE_SOC_SHA_COUNT (0) -/* @brief SIM availability on the SoC. */ -#define FSL_FEATURE_SOC_SIM_COUNT (0) -/* @brief SJC availability on the SoC. */ -#define FSL_FEATURE_SOC_SJC_COUNT (0) -/* @brief SLCD availability on the SoC. */ -#define FSL_FEATURE_SOC_SLCD_COUNT (0) -/* @brief SMARTCARD availability on the SoC. */ -#define FSL_FEATURE_SOC_SMARTCARD_COUNT (0) -/* @brief SMC availability on the SoC. */ -#define FSL_FEATURE_SOC_SMC_COUNT (0) /* @brief SNVS availability on the SoC. */ #define FSL_FEATURE_SOC_SNVS_COUNT (1) -/* @brief SPBA availability on the SoC. */ -#define FSL_FEATURE_SOC_SPBA_COUNT (0) /* @brief SPDIF availability on the SoC. */ #define FSL_FEATURE_SOC_SPDIF_COUNT (1) -/* @brief SPI availability on the SoC. */ -#define FSL_FEATURE_SOC_SPI_COUNT (0) -/* @brief SPIFI availability on the SoC. */ -#define FSL_FEATURE_SOC_SPIFI_COUNT (0) -/* @brief SPM availability on the SoC. */ -#define FSL_FEATURE_SOC_SPM_COUNT (0) /* @brief SRC availability on the SoC. */ #define FSL_FEATURE_SOC_SRC_COUNT (1) -/* @brief SYSCON availability on the SoC. */ -#define FSL_FEATURE_SOC_SYSCON_COUNT (0) -/* @brief SYSCTL0 availability on the SoC. */ -#define FSL_FEATURE_SOC_SYSCTL0_COUNT (0) -/* @brief SYSCTL1 availability on the SoC. */ -#define FSL_FEATURE_SOC_SYSCTL1_COUNT (0) /* @brief TEMPMON availability on the SoC. */ #define FSL_FEATURE_SOC_TEMPMON_COUNT (1) /* @brief TMR availability on the SoC. */ #define FSL_FEATURE_SOC_TMR_COUNT (4) -/* @brief TPM availability on the SoC. */ -#define FSL_FEATURE_SOC_TPM_COUNT (0) -/* @brief TRGMUX availability on the SoC. */ -#define FSL_FEATURE_SOC_TRGMUX_COUNT (0) -/* @brief TRIAMP availability on the SoC. */ -#define FSL_FEATURE_SOC_TRIAMP_COUNT (0) /* @brief TRNG availability on the SoC. */ #define FSL_FEATURE_SOC_TRNG_COUNT (1) /* @brief TSC availability on the SoC. */ #define FSL_FEATURE_SOC_TSC_COUNT (1) -/* @brief TSI availability on the SoC. */ -#define FSL_FEATURE_SOC_TSI_COUNT (0) -/* @brief TSTMR availability on the SoC. */ -#define FSL_FEATURE_SOC_TSTMR_COUNT (0) -/* @brief UART availability on the SoC. */ -#define FSL_FEATURE_SOC_UART_COUNT (0) -/* @brief USART availability on the SoC. */ -#define FSL_FEATURE_SOC_USART_COUNT (0) -/* @brief USB availability on the SoC. */ -#define FSL_FEATURE_SOC_USB_COUNT (0) /* @brief USBHS availability on the SoC. */ #define FSL_FEATURE_SOC_USBHS_COUNT (2) -/* @brief USBDCD availability on the SoC. */ -#define FSL_FEATURE_SOC_USBDCD_COUNT (0) -/* @brief USBFSH availability on the SoC. */ -#define FSL_FEATURE_SOC_USBFSH_COUNT (0) -/* @brief USBHSD availability on the SoC. */ -#define FSL_FEATURE_SOC_USBHSD_COUNT (0) -/* @brief USBHSDCD availability on the SoC. */ -#define FSL_FEATURE_SOC_USBHSDCD_COUNT (0) -/* @brief USBHSH availability on the SoC. */ -#define FSL_FEATURE_SOC_USBHSH_COUNT (0) /* @brief USBNC availability on the SoC. */ #define FSL_FEATURE_SOC_USBNC_COUNT (2) /* @brief USBPHY availability on the SoC. */ #define FSL_FEATURE_SOC_USBPHY_COUNT (2) -/* @brief USB_HSIC availability on the SoC. */ -#define FSL_FEATURE_SOC_USB_HSIC_COUNT (0) -/* @brief USB_OTG availability on the SoC. */ -#define FSL_FEATURE_SOC_USB_OTG_COUNT (0) -/* @brief USBVREG availability on the SoC. */ -#define FSL_FEATURE_SOC_USBVREG_COUNT (0) /* @brief USDHC availability on the SoC. */ #define FSL_FEATURE_SOC_USDHC_COUNT (2) -/* @brief UTICK availability on the SoC. */ -#define FSL_FEATURE_SOC_UTICK_COUNT (0) -/* @brief VIU availability on the SoC. */ -#define FSL_FEATURE_SOC_VIU_COUNT (0) -/* @brief VREF availability on the SoC. */ -#define FSL_FEATURE_SOC_VREF_COUNT (0) -/* @brief VFIFO availability on the SoC. */ -#define FSL_FEATURE_SOC_VFIFO_COUNT (0) /* @brief WDOG availability on the SoC. */ #define FSL_FEATURE_SOC_WDOG_COUNT (2) -/* @brief WKPU availability on the SoC. */ -#define FSL_FEATURE_SOC_WKPU_COUNT (0) -/* @brief WWDT availability on the SoC. */ -#define FSL_FEATURE_SOC_WWDT_COUNT (0) -/* @brief XBAR availability on the SoC. */ -#define FSL_FEATURE_SOC_XBAR_COUNT (0) /* @brief XBARA availability on the SoC. */ #define FSL_FEATURE_SOC_XBARA_COUNT (1) /* @brief XBARB availability on the SoC. */ #define FSL_FEATURE_SOC_XBARB_COUNT (2) -/* @brief XCVR availability on the SoC. */ -#define FSL_FEATURE_SOC_XCVR_COUNT (0) -/* @brief XRDC availability on the SoC. */ -#define FSL_FEATURE_SOC_XRDC_COUNT (0) -/* @brief XTALOSC availability on the SoC. */ -#define FSL_FEATURE_SOC_XTALOSC_COUNT (0) /* @brief XTALOSC24M availability on the SoC. */ #define FSL_FEATURE_SOC_XTALOSC24M_COUNT (1) -/* @brief ZLL availability on the SoC. */ -#define FSL_FEATURE_SOC_ZLL_COUNT (0) /* ADC module features */ @@ -582,6 +145,11 @@ /* @brief Remove ALT Clock selection feature. */ #define FSL_FEATURE_ADC_SUPPORT_ALTCLK_REMOVE (1) +/* ADC_ETC module features */ + +/* @brief Has DMA model control(bit field CTRL[DMA_MODE_SEL]). */ +#define FSL_FEATURE_ADC_ETC_HAS_CTRL_DMA_MODE_SEL (1) + /* AOI module features */ /* @brief Maximum value of input mux. */ @@ -595,20 +163,34 @@ #define FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(x) (64) /* @brief Has doze mode support (register bit field MCR[DOZE]). */ #define FSL_FEATURE_FLEXCAN_HAS_DOZE_MODE_SUPPORT (0) +/* @brief Insatnce has doze mode support (register bit field MCR[DOZE]). */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_DOZE_MODE_SUPPORTn(x) (0) /* @brief Has a glitch filter on the receive pin (register bit field MCR[WAKSRC]). */ #define FSL_FEATURE_FLEXCAN_HAS_GLITCH_FILTER (1) /* @brief Has extended interrupt mask and flag register (register IMASK2, IFLAG2). */ #define FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER (1) -/* @brief Has extended bit timing register (register CBT). */ -#define FSL_FEATURE_FLEXCAN_HAS_EXTENDED_TIMING_REGISTER (0) +/* @brief Instance has extended bit timing register (register CBT). */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_EXTENDED_TIMING_REGISTERn(x) (0) /* @brief Has a receive FIFO DMA feature (register bit field MCR[DMA]). */ #define FSL_FEATURE_FLEXCAN_HAS_RX_FIFO_DMA (0) +/* @brief Instance has a receive FIFO DMA feature (register bit field MCR[DMA]). */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_RX_FIFO_DMAn(x) (0) /* @brief Remove CAN Engine Clock Source Selection from unsupported part. */ #define FSL_FEATURE_FLEXCAN_SUPPORT_ENGINE_CLK_SEL_REMOVE (1) +/* @brief Instance remove CAN Engine Clock Source Selection from unsupported part. */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_SUPPORT_ENGINE_CLK_SEL_REMOVEn(x) (1) /* @brief Is affected by errata with ID 5641 (Module does not transmit a message that is enabled to be transmitted at a specific moment during the arbitration process). */ #define FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641 (0) +/* @brief Is affected by errata with ID 5829 (FlexCAN: FlexCAN does not transmit a message that is enabled to be transmitted in a specific moment during the arbitration process). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_5829 (1) +/* @brief Is affected by errata with ID 6032 (FlexCAN: A frame with wrong ID or payload is transmitted into the CAN bus when the Message Buffer under transmission is either aborted or deactivated while the CAN bus is in the Bus Idle state). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_6032 (1) +/* @brief Is affected by errata with ID 9595 (FlexCAN: Corrupt frame possible if the Freeze Mode or the Low-Power Mode are entered during a Bus-Off state). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_9595 (1) /* @brief Has CAN with Flexible Data rate (CAN FD) protocol. */ #define FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE (0) +/* @brief CAN instance support Flexible Data rate (CAN FD) protocol. */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_FLEXIBLE_DATA_RATEn(x) (0) /* @brief Has extra MB interrupt or common one. */ #define FSL_FEATURE_FLEXCAN_HAS_EXTRA_MB_INT (1) @@ -666,10 +248,40 @@ /* @brief Has Additional 1588 Timer Channel Interrupt. */ #define FSL_FEATURE_ENET_HAS_ADD_1588_TIMER_CHN_INT (0) +/* EWM module features */ + +/* @brief Has clock select (register CLKCTRL). */ +#define FSL_FEATURE_EWM_HAS_CLOCK_SELECT (1) +/* @brief Has clock prescaler (register CLKPRESCALER). */ +#define FSL_FEATURE_EWM_HAS_PRESCALER (1) + +/* FLEXIO module features */ + +/* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */ +#define FSL_FEATURE_FLEXIO_HAS_SHIFTER_STATUS (1) +/* @brief Has Pin Data Input Register (FLEXIO_PIN) */ +#define FSL_FEATURE_FLEXIO_HAS_PIN_STATUS (1) +/* @brief Has Shifter Buffer N Nibble Byte Swapped Register (FLEXIO_SHIFTBUFNBSn) */ +#define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_BYTE_SWAP (1) +/* @brief Has Shifter Buffer N Half Word Swapped Register (FLEXIO_SHIFTBUFHWSn) */ +#define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_HALF_WORD_SWAP (1) +/* @brief Has Shifter Buffer N Nibble Swapped Register (FLEXIO_SHIFTBUFNISn) */ +#define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_SWAP (1) +/* @brief Supports Shifter State Mode (FLEXIO_SHIFTCTLn[SMOD]) */ +#define FSL_FEATURE_FLEXIO_HAS_STATE_MODE (1) +/* @brief Supports Shifter Logic Mode (FLEXIO_SHIFTCTLn[SMOD]) */ +#define FSL_FEATURE_FLEXIO_HAS_LOGIC_MODE (1) +/* @brief Supports paralle width (FLEXIO_SHIFTCFGn[PWIDTH]) */ +#define FSL_FEATURE_FLEXIO_HAS_PARALLEL_WIDTH (1) +/* @brief Reset value of the FLEXIO_VERID register */ +#define FSL_FEATURE_FLEXIO_VERID_RESET_VALUE (0x1010001) +/* @brief Reset value of the FLEXIO_PARAM register */ +#define FSL_FEATURE_FLEXIO_PARAM_RESET_VALUE (0x2200404) + /* FLEXRAM module features */ /* @brief Bank size */ -#define FSL_FEATURE_FLEXRAM_INTERNAL_RAM_BANK_SIZE (32 * 1024) +#define FSL_FEATURE_FLEXRAM_INTERNAL_RAM_BANK_SIZE (32768) /* @brief Total Bank numbers */ #define FSL_FEATURE_FLEXRAM_INTERNAL_RAM_TOTAL_BANK_NUMBERS (16) @@ -697,6 +309,15 @@ /* @brief Supports IRQ 0-31. */ #define FSL_FEATURE_GPC_HAS_IRQ_0_31 (1) +/* IGPIO module features */ + +/* @brief Has data register set DR_SET. */ +#define FSL_FEATURE_IGPIO_HAS_DR_SET (1) +/* @brief Has data register clear DR_CLEAR. */ +#define FSL_FEATURE_IGPIO_HAS_DR_CLEAR (1) +/* @brief Has data register toggle DR_TOGGLE. */ +#define FSL_FEATURE_IGPIO_HAS_DR_TOGGLE (1) + /* LCDIF module features */ /* @brief LCDIF does not support alpha support. */ @@ -796,7 +417,7 @@ /* @brief Lowest interrupt request number. */ #define FSL_FEATURE_INTERRUPT_IRQ_MIN (-14) /* @brief Highest interrupt request number. */ -#define FSL_FEATURE_INTERRUPT_IRQ_MAX (159) +#define FSL_FEATURE_INTERRUPT_IRQ_MAX (151) /* OCOTP module features */ @@ -885,8 +506,19 @@ #define FSL_FEATURE_SAI_INT_SOURCE_NUM (2) /* @brief Has register of MCR. */ #define FSL_FEATURE_SAI_HAS_MCR (0) +/* @brief Has bit field MICS of the MCR register. */ +#define FSL_FEATURE_SAI_HAS_NO_MCR_MICS (1) /* @brief Has register of MDR */ #define FSL_FEATURE_SAI_HAS_MDR (0) +/* @brief Has support the BCLK bypass mode when BCLK = MCLK. */ +#define FSL_FEATURE_SAI_HAS_BCLK_BYPASS (0) + +/* SEMC module features */ + +/* @brief Has WDH time in NOR controller (register bit field NORCR2[WDH]). */ +#define FSL_FEATURE_SEMC_HAS_NOR_WDH_TIME (1) +/* @brief Has WDS time in NOR controller (register bit field NORCR2[WDS]).) */ +#define FSL_FEATURE_SEMC_HAS_NOR_WDS_TIME (1) /* SNVS module features */ @@ -912,7 +544,7 @@ /* @brief There is CORE0_RST bit in SCR register. */ #define FSL_FEATURE_SRC_HAS_SCR_CORE0_RST (1) /* @brief There is LOCKUP_RST bit in SCR register. */ -#define FSL_FEATURE_SRC_HAS_SCR_LOCKUP_RST (1) +#define FSL_FEATURE_SRC_HAS_SCR_LOCKUP_RST (0) /* @brief There is SWRC bit in SCR register. */ #define FSL_FEATURE_SRC_HAS_SCR_SWRC (0) /* @brief There is EIM_RST bit in SCR register. */ diff --git a/ext/hal/nxp/mcux/devices/MIMXRT1052/fsl_clock.c b/ext/hal/nxp/mcux/devices/MIMXRT1052/fsl_clock.c index 342f0aba924..e12179b96fb 100644 --- a/ext/hal/nxp/mcux/devices/MIMXRT1052/fsl_clock.c +++ b/ext/hal/nxp/mcux/devices/MIMXRT1052/fsl_clock.c @@ -1,55 +1,72 @@ /* * Copyright 2017 NXP + * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * SPDX-License-Identifier: BSD-3-Clause */ -#include "fsl_common.h" #include "fsl_clock.h" - +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.clock" +#endif /******************************************************************************* * Definitions ******************************************************************************/ +/* To make full use of CM7 hardware FPU, use double instead of uint64_t in clock driver to +achieve better performance, it is depend on the IDE Floating point settings, if double precision is selected +in IDE, clock_64b_t will switch to double type automatically. only support IAR and MDK here */ +#if __FPU_USED + +#if ((defined(__ICCARM__)) || (defined(__GNUC__))) + +#if (__ARMVFP__ >= __ARMFPV5__) && \ + (__ARM_FP == 0xE) /*0xe implies support for half, single and double precision operations*/ +typedef double clock_64b_t; +#else +typedef uint64_t clock_64b_t; +#endif + +#elif defined(__CC_ARM) || defined(__ARMCC_VERSION) + +#if defined __TARGET_FPU_FPV5_D16 +typedef double clock_64b_t; +#else +typedef uint64_t clock_64b_t; +#endif + +#else +typedef uint64_t clock_64b_t; +#endif + +#else +typedef uint64_t clock_64b_t; +#endif /******************************************************************************* * Variables ******************************************************************************/ /* External XTAL (OSC) clock frequency. */ -uint32_t g_xtalFreq; +volatile uint32_t g_xtalFreq; /* External RTC XTAL clock frequency. */ -uint32_t g_rtcXtalFreq; +volatile uint32_t g_rtcXtalFreq; /******************************************************************************* * Prototypes ******************************************************************************/ +/*! + * @brief Get the periph clock frequency. + * + * @return Periph clock frequency in Hz. + */ +static uint32_t CLOCK_GetPeriphClkFreq(void); + /******************************************************************************* * Code ******************************************************************************/ + static uint32_t CLOCK_GetPeriphClkFreq(void) { uint32_t freq; @@ -70,6 +87,9 @@ static uint32_t CLOCK_GetPeriphClkFreq(void) break; case CCM_CBCMR_PERIPH_CLK2_SEL(2U): + freq = CLOCK_GetPllFreq(kCLOCK_PllSys); + break; + case CCM_CBCMR_PERIPH_CLK2_SEL(3U): default: freq = 0U; @@ -100,7 +120,8 @@ static uint32_t CLOCK_GetPeriphClkFreq(void) /* PLL1 divided(/2) ---> Pre_Periph_clk ---> Periph_clk */ case CCM_CBCMR_PRE_PERIPH_CLK_SEL(3U): - freq = CLOCK_GetPllFreq(kCLOCK_PllArm) / (((CCM->CACRR & CCM_CACRR_ARM_PODF_MASK) >> CCM_CACRR_ARM_PODF_SHIFT) + 1U); + freq = CLOCK_GetPllFreq(kCLOCK_PllArm) / + (((CCM->CACRR & CCM_CACRR_ARM_PODF_MASK) >> CCM_CACRR_ARM_PODF_SHIFT) + 1U); break; default: @@ -112,6 +133,20 @@ static uint32_t CLOCK_GetPeriphClkFreq(void) return freq; } +/*! + * brief Initialize the external 24MHz clock. + * + * This function supports two modes: + * 1. Use external crystal oscillator. + * 2. Bypass the external crystal oscillator, using input source clock directly. + * + * After this function, please call ref CLOCK_SetXtal0Freq to inform clock driver + * the external clock frequency. + * + * param bypassXtalOsc Pass in true to bypass the external crystal oscillator. + * note This device does not support bypass external crystal oscillator, so + * the input parameter should always be false. + */ void CLOCK_InitExternalClk(bool bypassXtalOsc) { /* This device does not support bypass XTAL OSC. */ @@ -128,11 +163,26 @@ void CLOCK_InitExternalClk(bool bypassXtalOsc) CCM_ANALOG->MISC0_CLR = CCM_ANALOG_MISC0_OSC_XTALOK_EN_MASK; } +/*! + * brief Deinitialize the external 24MHz clock. + * + * This function disables the external 24MHz clock. + * + * After this function, please call ref CLOCK_SetXtal0Freq to set external clock + * frequency to 0. + */ void CLOCK_DeinitExternalClk(void) { CCM_ANALOG->MISC0_SET = CCM_ANALOG_MISC0_XTAL_24M_PWD_MASK; /* Power down */ } +/*! + * brief Switch the OSC. + * + * This function switches the OSC source for SoC. + * + * param osc OSC source to switch to. + */ void CLOCK_SwitchOsc(clock_osc_t osc) { if (osc == kCLOCK_RcOsc) @@ -141,16 +191,110 @@ void CLOCK_SwitchOsc(clock_osc_t osc) XTALOSC24M->LOWPWR_CTRL_CLR = XTALOSC24M_LOWPWR_CTRL_CLR_OSC_SEL_MASK; } +/*! + * brief Initialize the RC oscillator 24MHz clock. + */ void CLOCK_InitRcOsc24M(void) { XTALOSC24M->LOWPWR_CTRL |= XTALOSC24M_LOWPWR_CTRL_RC_OSC_EN_MASK; } +/*! + * brief Power down the RCOSC 24M clock. + */ void CLOCK_DeinitRcOsc24M(void) { XTALOSC24M->LOWPWR_CTRL &= ~XTALOSC24M_LOWPWR_CTRL_RC_OSC_EN_MASK; } +/*! + * brief Gets the AHB clock frequency. + * + * return The AHB clock frequency value in hertz. + */ +uint32_t CLOCK_GetAhbFreq(void) +{ + return CLOCK_GetPeriphClkFreq() / (((CCM->CBCDR & CCM_CBCDR_AHB_PODF_MASK) >> CCM_CBCDR_AHB_PODF_SHIFT) + 1U); +} + +/*! + * brief Gets the SEMC clock frequency. + * + * return The SEMC clock frequency value in hertz. + */ +uint32_t CLOCK_GetSemcFreq(void) +{ + uint32_t freq; + + /* SEMC alternative clock ---> SEMC Clock */ + if (CCM->CBCDR & CCM_CBCDR_SEMC_CLK_SEL_MASK) + { + /* PLL3 PFD1 ---> SEMC alternative clock ---> SEMC Clock */ + if (CCM->CBCDR & CCM_CBCDR_SEMC_ALT_CLK_SEL_MASK) + { + freq = CLOCK_GetUsb1PfdFreq(kCLOCK_Pfd1); + } + /* PLL2 PFD2 ---> SEMC alternative clock ---> SEMC Clock */ + else + { + freq = CLOCK_GetSysPfdFreq(kCLOCK_Pfd2); + } + } + /* Periph_clk ---> SEMC Clock */ + else + { + freq = CLOCK_GetPeriphClkFreq(); + } + + freq /= (((CCM->CBCDR & CCM_CBCDR_SEMC_PODF_MASK) >> CCM_CBCDR_SEMC_PODF_SHIFT) + 1U); + + return freq; +} + +/*! + * brief Gets the IPG clock frequency. + * + * return The IPG clock frequency value in hertz. + */ +uint32_t CLOCK_GetIpgFreq(void) +{ + return CLOCK_GetAhbFreq() / (((CCM->CBCDR & CCM_CBCDR_IPG_PODF_MASK) >> CCM_CBCDR_IPG_PODF_SHIFT) + 1U); +} + +/*! + * brief Gets the PER clock frequency. + * + * return The PER clock frequency value in hertz. + */ +uint32_t CLOCK_GetPerClkFreq(void) +{ + uint32_t freq; + + /* Osc_clk ---> PER Clock*/ + if (CCM->CSCMR1 & CCM_CSCMR1_PERCLK_CLK_SEL_MASK) + { + freq = CLOCK_GetOscFreq(); + } + /* Periph_clk ---> AHB Clock ---> IPG Clock ---> PER Clock */ + else + { + freq = CLOCK_GetFreq(kCLOCK_IpgClk); + } + + freq /= (((CCM->CSCMR1 & CCM_CSCMR1_PERCLK_PODF_MASK) >> CCM_CSCMR1_PERCLK_PODF_SHIFT) + 1U); + + return freq; +} + +/*! + * brief Gets the clock frequency for a specific clock name. + * + * This function checks the current clock configurations and then calculates + * the clock frequency for a specific clock name defined in clock_name_t. + * + * param clockName Clock names defined in clock_name_t + * return Clock frequency value in hertz + */ uint32_t CLOCK_GetFreq(clock_name_t name) { uint32_t freq; @@ -158,40 +302,20 @@ uint32_t CLOCK_GetFreq(clock_name_t name) switch (name) { case kCLOCK_CpuClk: - /* Periph_clk ---> AHB Clock */ case kCLOCK_AhbClk: - /* Periph_clk ---> AHB Clock */ - freq = CLOCK_GetPeriphClkFreq() / (((CCM->CBCDR & CCM_CBCDR_AHB_PODF_MASK) >> CCM_CBCDR_AHB_PODF_SHIFT) + 1U); + freq = CLOCK_GetAhbFreq(); break; case kCLOCK_SemcClk: - /* SEMC alternative clock ---> SEMC Clock */ - if (CCM->CBCDR & CCM_CBCDR_SEMC_CLK_SEL_MASK) - { - /* PLL3 PFD1 ---> SEMC alternative clock ---> SEMC Clock */ - if (CCM->CBCDR & CCM_CBCDR_SEMC_ALT_CLK_SEL_MASK) - { - freq = CLOCK_GetUsb1PfdFreq(kCLOCK_Pfd1); - } - /* PLL2 PFD2 ---> SEMC alternative clock ---> SEMC Clock */ - else - { - freq = CLOCK_GetSysPfdFreq(kCLOCK_Pfd2); - } - } - /* Periph_clk ---> SEMC Clock */ - else - { - freq = CLOCK_GetPeriphClkFreq(); - } - - freq /= (((CCM->CBCDR & CCM_CBCDR_SEMC_PODF_MASK) >> CCM_CBCDR_SEMC_PODF_SHIFT) + 1U); + freq = CLOCK_GetSemcFreq(); break; case kCLOCK_IpgClk: - /* Periph_clk ---> AHB Clock ---> IPG Clock */ - freq = CLOCK_GetPeriphClkFreq() / (((CCM->CBCDR & CCM_CBCDR_AHB_PODF_MASK) >> CCM_CBCDR_AHB_PODF_SHIFT) + 1U); - freq /= (((CCM->CBCDR & CCM_CBCDR_IPG_PODF_MASK) >> CCM_CBCDR_IPG_PODF_SHIFT) + 1U); + freq = CLOCK_GetIpgFreq(); + break; + + case kCLOCK_PerClk: + freq = CLOCK_GetPerClkFreq(); break; case kCLOCK_OscClk: @@ -237,13 +361,10 @@ uint32_t CLOCK_GetFreq(clock_name_t name) freq = CLOCK_GetSysPfdFreq(kCLOCK_Pfd3); break; case kCLOCK_EnetPll0Clk: - freq = CLOCK_GetPllFreq(kCLOCK_PllEnet0); + freq = CLOCK_GetPllFreq(kCLOCK_PllEnet); break; case kCLOCK_EnetPll1Clk: - freq = CLOCK_GetPllFreq(kCLOCK_PllEnet1); - break; - case kCLOCK_EnetPll2Clk: - freq = CLOCK_GetPllFreq(kCLOCK_PllEnet2); + freq = CLOCK_GetPllFreq(kCLOCK_PllEnet25M); break; case kCLOCK_AudioPllClk: freq = CLOCK_GetPllFreq(kCLOCK_PllAudio); @@ -259,75 +380,252 @@ uint32_t CLOCK_GetFreq(clock_name_t name) return freq; } +/*! brief Enable USB HS clock. + * + * This function only enables the access to USB HS prepheral, upper layer + * should first call the ref CLOCK_EnableUsbhs0PhyPllClock to enable the PHY + * clock to use USB HS. + * + * param src USB HS does not care about the clock source, here must be ref kCLOCK_UsbSrcUnused. + * param freq USB HS does not care about the clock source, so this parameter is ignored. + * retval true The clock is set successfully. + * retval false The clock source is invalid to get proper USB HS clock. + */ +bool CLOCK_EnableUsbhs0Clock(clock_usb_src_t src, uint32_t freq) +{ + CCM->CCGR6 |= CCM_CCGR6_CG0_MASK; + USB1->USBCMD |= USBHS_USBCMD_RST_MASK; + for (volatile uint32_t i = 0; i < 400000; + i++) /* Add a delay between RST and RS so make sure there is a DP pullup sequence*/ + { + __ASM("nop"); + } + PMU->REG_3P0 = (PMU->REG_3P0 & (~PMU_REG_3P0_OUTPUT_TRG_MASK)) | + (PMU_REG_3P0_OUTPUT_TRG(0x17) | PMU_REG_3P0_ENABLE_LINREG_MASK); + return true; +} + +/*! brief Enable USB HS clock. + * + * This function only enables the access to USB HS prepheral, upper layer + * should first call the ref CLOCK_EnableUsbhs0PhyPllClock to enable the PHY + * clock to use USB HS. + * + * param src USB HS does not care about the clock source, here must be ref kCLOCK_UsbSrcUnused. + * param freq USB HS does not care about the clock source, so this parameter is ignored. + * retval true The clock is set successfully. + * retval false The clock source is invalid to get proper USB HS clock. + */ +bool CLOCK_EnableUsbhs1Clock(clock_usb_src_t src, uint32_t freq) +{ + CCM->CCGR6 |= CCM_CCGR6_CG0_MASK; + USB2->USBCMD |= USBHS_USBCMD_RST_MASK; + for (volatile uint32_t i = 0; i < 400000; + i++) /* Add a delay between RST and RS so make sure there is a DP pullup sequence*/ + { + __ASM("nop"); + } + PMU->REG_3P0 = (PMU->REG_3P0 & (~PMU_REG_3P0_OUTPUT_TRG_MASK)) | + (PMU_REG_3P0_OUTPUT_TRG(0x17) | PMU_REG_3P0_ENABLE_LINREG_MASK); + return true; +} + +/*! brief Enable USB HS PHY PLL clock. + * + * This function enables the internal 480MHz USB PHY PLL clock. + * + * param src USB HS PHY PLL clock source. + * param freq The frequency specified by src. + * retval true The clock is set successfully. + * retval false The clock source is invalid to get proper USB HS clock. + */ +bool CLOCK_EnableUsbhs0PhyPllClock(clock_usb_phy_src_t src, uint32_t freq) +{ + const clock_usb_pll_config_t g_ccmConfigUsbPll = {.loopDivider = 0U}; + if (CCM_ANALOG->PLL_USB1 & CCM_ANALOG_PLL_USB1_ENABLE_MASK) + { + CCM_ANALOG->PLL_USB1 |= CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK; + } + else + { + CLOCK_InitUsb1Pll(&g_ccmConfigUsbPll); + } + USBPHY1->CTRL &= ~USBPHY_CTRL_SFTRST_MASK; /* release PHY from reset */ + USBPHY1->CTRL &= ~USBPHY_CTRL_CLKGATE_MASK; + + USBPHY1->PWD = 0; + USBPHY1->CTRL |= USBPHY_CTRL_ENAUTOCLR_PHY_PWD_MASK | USBPHY_CTRL_ENAUTOCLR_CLKGATE_MASK | + USBPHY_CTRL_ENUTMILEVEL2_MASK | USBPHY_CTRL_ENUTMILEVEL3_MASK; + return true; +} + +/*! brief Disable USB HS PHY PLL clock. + * + * This function disables USB HS PHY PLL clock. + */ +void CLOCK_DisableUsbhs0PhyPllClock(void) +{ + CCM_ANALOG->PLL_USB1 &= ~CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK; + USBPHY1->CTRL |= USBPHY_CTRL_CLKGATE_MASK; /* Set to 1U to gate clocks */ +} + +/*! + * brief Initialize the ARM PLL. + * + * This function initialize the ARM PLL with specific settings + * + * param config configuration to set to PLL. + */ void CLOCK_InitArmPll(const clock_arm_pll_config_t *config) { - CCM_ANALOG->PLL_ARM = CCM_ANALOG_PLL_ARM_ENABLE_MASK | - CCM_ANALOG_PLL_ARM_DIV_SELECT(config->loopDivider); + /* Bypass PLL first */ + CCM_ANALOG->PLL_ARM = (CCM_ANALOG->PLL_ARM & (~CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_MASK)) | + CCM_ANALOG_PLL_ARM_BYPASS_MASK | CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC(config->src); + + CCM_ANALOG->PLL_ARM = + (CCM_ANALOG->PLL_ARM & (~(CCM_ANALOG_PLL_ARM_DIV_SELECT_MASK | CCM_ANALOG_PLL_ARM_POWERDOWN_MASK))) | + CCM_ANALOG_PLL_ARM_ENABLE_MASK | CCM_ANALOG_PLL_ARM_DIV_SELECT(config->loopDivider); while ((CCM_ANALOG->PLL_ARM & CCM_ANALOG_PLL_ARM_LOCK_MASK) == 0) { } + + /* Disable Bypass */ + CCM_ANALOG->PLL_ARM &= ~CCM_ANALOG_PLL_ARM_BYPASS_MASK; } +/*! + * brief De-initialize the ARM PLL. + */ void CLOCK_DeinitArmPll(void) { CCM_ANALOG->PLL_ARM = CCM_ANALOG_PLL_ARM_POWERDOWN_MASK; } +/*! + * brief Initialize the System PLL. + * + * This function initializes the System PLL with specific settings + * + * param config Configuration to set to PLL. + */ void CLOCK_InitSysPll(const clock_sys_pll_config_t *config) { - CCM_ANALOG->PLL_SYS = CCM_ANALOG_PLL_SYS_ENABLE_MASK | - CCM_ANALOG_PLL_SYS_DIV_SELECT(config->loopDivider); + /* Bypass PLL first */ + CCM_ANALOG->PLL_SYS = (CCM_ANALOG->PLL_SYS & (~CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_MASK)) | + CCM_ANALOG_PLL_SYS_BYPASS_MASK | CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC(config->src); + + CCM_ANALOG->PLL_SYS = + (CCM_ANALOG->PLL_SYS & (~(CCM_ANALOG_PLL_SYS_DIV_SELECT_MASK | CCM_ANALOG_PLL_SYS_POWERDOWN_MASK))) | + CCM_ANALOG_PLL_SYS_ENABLE_MASK | CCM_ANALOG_PLL_SYS_DIV_SELECT(config->loopDivider); + + /* Initialize the fractional mode */ + CCM_ANALOG->PLL_SYS_NUM = CCM_ANALOG_PLL_SYS_NUM_A(config->numerator); + CCM_ANALOG->PLL_SYS_DENOM = CCM_ANALOG_PLL_SYS_DENOM_B(config->denominator); + + /* Initialize the spread spectrum mode */ + CCM_ANALOG->PLL_SYS_SS = CCM_ANALOG_PLL_SYS_SS_STEP(config->ss_step) | + CCM_ANALOG_PLL_SYS_SS_ENABLE(config->ss_enable) | + CCM_ANALOG_PLL_SYS_SS_STOP(config->ss_stop); while ((CCM_ANALOG->PLL_SYS & CCM_ANALOG_PLL_SYS_LOCK_MASK) == 0) { } + + /* Disable Bypass */ + CCM_ANALOG->PLL_SYS &= ~CCM_ANALOG_PLL_SYS_BYPASS_MASK; } +/*! + * brief De-initialize the System PLL. + */ void CLOCK_DeinitSysPll(void) { CCM_ANALOG->PLL_SYS = CCM_ANALOG_PLL_SYS_POWERDOWN_MASK; } +/*! + * brief Initialize the USB1 PLL. + * + * This function initializes the USB1 PLL with specific settings + * + * param config Configuration to set to PLL. + */ void CLOCK_InitUsb1Pll(const clock_usb_pll_config_t *config) { - CCM_ANALOG->PLL_USB1 = CCM_ANALOG_PLL_USB1_ENABLE_MASK | - CCM_ANALOG_PLL_USB1_POWER_MASK | - CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK | - CCM_ANALOG_PLL_USB1_DIV_SELECT(config->loopDivider); + /* Bypass PLL first */ + CCM_ANALOG->PLL_USB1 = (CCM_ANALOG->PLL_USB1 & (~CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_MASK)) | + CCM_ANALOG_PLL_USB1_BYPASS_MASK | CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC(config->src); + + CCM_ANALOG->PLL_USB1 = (CCM_ANALOG->PLL_USB1 & (~CCM_ANALOG_PLL_USB1_DIV_SELECT_MASK)) | + CCM_ANALOG_PLL_USB1_ENABLE_MASK | CCM_ANALOG_PLL_USB1_POWER_MASK | + CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK | CCM_ANALOG_PLL_USB1_DIV_SELECT(config->loopDivider); while ((CCM_ANALOG->PLL_USB1 & CCM_ANALOG_PLL_USB1_LOCK_MASK) == 0) { } + + /* Disable Bypass */ + CCM_ANALOG->PLL_USB1 &= ~CCM_ANALOG_PLL_USB1_BYPASS_MASK; } +/*! + * brief Deinitialize the USB1 PLL. + */ void CLOCK_DeinitUsb1Pll(void) { CCM_ANALOG->PLL_USB1 = 0U; } +/*! + * brief Initialize the USB2 PLL. + * + * This function initializes the USB2 PLL with specific settings + * + * param config Configuration to set to PLL. + */ void CLOCK_InitUsb2Pll(const clock_usb_pll_config_t *config) { - CCM_ANALOG->PLL_USB2 = CCM_ANALOG_PLL_USB2_ENABLE_MASK | - CCM_ANALOG_PLL_USB2_POWER_MASK | - CCM_ANALOG_PLL_USB2_EN_USB_CLKS_MASK | - CCM_ANALOG_PLL_USB2_DIV_SELECT(config->loopDivider); + /* Bypass PLL first */ + CCM_ANALOG->PLL_USB2 = (CCM_ANALOG->PLL_USB2 & (~CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC_MASK)) | + CCM_ANALOG_PLL_USB2_BYPASS_MASK | CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC(config->src); + + CCM_ANALOG->PLL_USB2 = (CCM_ANALOG->PLL_USB2 & (~CCM_ANALOG_PLL_USB2_DIV_SELECT_MASK)) | + CCM_ANALOG_PLL_USB2_ENABLE_MASK | CCM_ANALOG_PLL_USB2_POWER_MASK | + CCM_ANALOG_PLL_USB2_EN_USB_CLKS_MASK | CCM_ANALOG_PLL_USB2_DIV_SELECT(config->loopDivider); while ((CCM_ANALOG->PLL_USB2 & CCM_ANALOG_PLL_USB2_LOCK_MASK) == 0) { } + + /* Disable Bypass */ + CCM_ANALOG->PLL_USB2 &= ~CCM_ANALOG_PLL_USB2_BYPASS_MASK; } +/*! + * brief Deinitialize the USB2 PLL. + */ void CLOCK_DeinitUsb2Pll(void) { CCM_ANALOG->PLL_USB2 = 0U; } +/*! + * brief Initializes the Audio PLL. + * + * This function initializes the Audio PLL with specific settings + * + * param config Configuration to set to PLL. + */ void CLOCK_InitAudioPll(const clock_audio_pll_config_t *config) { uint32_t pllAudio; uint32_t misc2 = 0; + /* Bypass PLL first */ + CCM_ANALOG->PLL_AUDIO = (CCM_ANALOG->PLL_AUDIO & (~CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_MASK)) | + CCM_ANALOG_PLL_AUDIO_BYPASS_MASK | CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC(config->src); + CCM_ANALOG->PLL_AUDIO_NUM = CCM_ANALOG_PLL_AUDIO_NUM_A(config->numerator); CCM_ANALOG->PLL_AUDIO_DENOM = CCM_ANALOG_PLL_AUDIO_DENOM_B(config->denominator); @@ -348,7 +646,9 @@ void CLOCK_InitAudioPll(const clock_audio_pll_config_t *config) * | 16 | 0 | 3 | * ------------------------------------------------------------------------ */ - pllAudio = CCM_ANALOG_PLL_AUDIO_ENABLE_MASK | CCM_ANALOG_PLL_AUDIO_DIV_SELECT(config->loopDivider); + pllAudio = + (CCM_ANALOG->PLL_AUDIO & (~(CCM_ANALOG_PLL_AUDIO_DIV_SELECT_MASK | CCM_ANALOG_PLL_AUDIO_POWERDOWN_MASK))) | + CCM_ANALOG_PLL_AUDIO_ENABLE_MASK | CCM_ANALOG_PLL_AUDIO_DIV_SELECT(config->loopDivider); switch (config->postDivider) { @@ -376,26 +676,43 @@ void CLOCK_InitAudioPll(const clock_audio_pll_config_t *config) break; } - CCM_ANALOG->MISC2 = (CCM_ANALOG->MISC2 & ~(CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK | CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK)) - | misc2; + CCM_ANALOG->MISC2 = + (CCM_ANALOG->MISC2 & ~(CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK | CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK)) | misc2; CCM_ANALOG->PLL_AUDIO = pllAudio; while ((CCM_ANALOG->PLL_AUDIO & CCM_ANALOG_PLL_AUDIO_LOCK_MASK) == 0) { } + + /* Disable Bypass */ + CCM_ANALOG->PLL_AUDIO &= ~CCM_ANALOG_PLL_AUDIO_BYPASS_MASK; } +/*! + * brief De-initialize the Audio PLL. + */ void CLOCK_DeinitAudioPll(void) { CCM_ANALOG->PLL_AUDIO = CCM_ANALOG_PLL_AUDIO_POWERDOWN_MASK; } +/*! + * brief Initialize the video PLL. + * + * This function configures the Video PLL with specific settings + * + * param config configuration to set to PLL. + */ void CLOCK_InitVideoPll(const clock_video_pll_config_t *config) { uint32_t pllVideo; uint32_t misc2 = 0; + /* Bypass PLL first */ + CCM_ANALOG->PLL_VIDEO = (CCM_ANALOG->PLL_VIDEO & (~CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_MASK)) | + CCM_ANALOG_PLL_VIDEO_BYPASS_MASK | CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC(config->src); + CCM_ANALOG->PLL_VIDEO_NUM = CCM_ANALOG_PLL_VIDEO_NUM_A(config->numerator); CCM_ANALOG->PLL_VIDEO_DENOM = CCM_ANALOG_PLL_VIDEO_DENOM_B(config->denominator); @@ -416,7 +733,9 @@ void CLOCK_InitVideoPll(const clock_video_pll_config_t *config) * | 16 | 0 | 3 | * ------------------------------------------------------------------------ */ - pllVideo = CCM_ANALOG_PLL_VIDEO_ENABLE_MASK | CCM_ANALOG_PLL_VIDEO_DIV_SELECT(config->loopDivider); + pllVideo = + (CCM_ANALOG->PLL_VIDEO & (~(CCM_ANALOG_PLL_VIDEO_DIV_SELECT_MASK | CCM_ANALOG_PLL_VIDEO_POWERDOWN_MASK))) | + CCM_ANALOG_PLL_VIDEO_ENABLE_MASK | CCM_ANALOG_PLL_VIDEO_DIV_SELECT(config->loopDivider); switch (config->postDivider) { @@ -451,71 +770,113 @@ void CLOCK_InitVideoPll(const clock_video_pll_config_t *config) while ((CCM_ANALOG->PLL_VIDEO & CCM_ANALOG_PLL_VIDEO_LOCK_MASK) == 0) { } + + /* Disable Bypass */ + CCM_ANALOG->PLL_VIDEO &= ~CCM_ANALOG_PLL_VIDEO_BYPASS_MASK; } +/*! + * brief De-initialize the Video PLL. + */ void CLOCK_DeinitVideoPll(void) { CCM_ANALOG->PLL_VIDEO = CCM_ANALOG_PLL_VIDEO_POWERDOWN_MASK; } +/*! + * brief Initialize the ENET PLL. + * + * This function initializes the ENET PLL with specific settings. + * + * param config Configuration to set to PLL. + */ void CLOCK_InitEnetPll(const clock_enet_pll_config_t *config) { - uint32_t enet_pll = CCM_ANALOG_PLL_ENET_ENET1_DIV_SELECT(config->loopDivider1) | - CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT(config->loopDivider0); + uint32_t enet_pll = CCM_ANALOG_PLL_ENET_DIV_SELECT(config->loopDivider); - if (config->enableClkOutput0) + CCM_ANALOG->PLL_ENET = (CCM_ANALOG->PLL_ENET & (~CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_MASK)) | + CCM_ANALOG_PLL_ENET_BYPASS_MASK | CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC(config->src); + + if (config->enableClkOutput) { - enet_pll |= CCM_ANALOG_PLL_ENET_ENET1_125M_EN_MASK; + enet_pll |= CCM_ANALOG_PLL_ENET_ENABLE_MASK; } - if (config->enableClkOutput1) - { - enet_pll |= CCM_ANALOG_PLL_ENET_ENET2_125M_EN_MASK; - } - - if (config->enableClkOutput2) + if (config->enableClkOutput25M) { enet_pll |= CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_MASK; } - CCM_ANALOG->PLL_ENET = enet_pll; + CCM_ANALOG->PLL_ENET = + (CCM_ANALOG->PLL_ENET & (~(CCM_ANALOG_PLL_ENET_DIV_SELECT_MASK | CCM_ANALOG_PLL_ENET_POWERDOWN_MASK))) | + enet_pll; /* Wait for stable */ while ((CCM_ANALOG->PLL_ENET & CCM_ANALOG_PLL_ENET_LOCK_MASK) == 0) { } + + /* Disable Bypass */ + CCM_ANALOG->PLL_ENET &= ~CCM_ANALOG_PLL_ENET_BYPASS_MASK; } +/*! + * brief Deinitialize the ENET PLL. + * + * This function disables the ENET PLL. + */ void CLOCK_DeinitEnetPll(void) { CCM_ANALOG->PLL_ENET = CCM_ANALOG_PLL_ENET_POWERDOWN_MASK; } +/*! + * brief Get current PLL output frequency. + * + * This function get current output frequency of specific PLL + * + * param pll pll name to get frequency. + * return The PLL output frequency in hertz. + */ uint32_t CLOCK_GetPllFreq(clock_pll_t pll) { uint32_t freq; uint32_t divSelect; - uint64_t freqTmp; + clock_64b_t freqTmp; const uint32_t enetRefClkFreq[] = { - 25000000U, /* 25M */ - 50000000U, /* 50M */ + 25000000U, /* 25M */ + 50000000U, /* 50M */ 100000000U, /* 100M */ - 125000000U /* 125M */ + 125000000U /* 125M */ }; + /* check if PLL is enabled */ + if (!CLOCK_IsPllEnabled(CCM_ANALOG, pll)) + { + return 0U; + } + + /* get pll reference clock */ + freq = CLOCK_GetPllBypassRefClk(CCM_ANALOG, pll); + + /* check if pll is bypassed */ + if (CLOCK_IsPllBypassed(CCM_ANALOG, pll)) + { + return freq; + } + switch (pll) { case kCLOCK_PllArm: - freq = ((CLOCK_GetOscFreq() * ((CCM_ANALOG->PLL_ARM & CCM_ANALOG_PLL_ARM_DIV_SELECT_MASK) >> - CCM_ANALOG_PLL_ARM_DIV_SELECT_SHIFT)) >> 1U); + freq = ((freq * ((CCM_ANALOG->PLL_ARM & CCM_ANALOG_PLL_ARM_DIV_SELECT_MASK) >> + CCM_ANALOG_PLL_ARM_DIV_SELECT_SHIFT)) >> + 1U); break; - case kCLOCK_PllSys: - freq = CLOCK_GetOscFreq(); - /* PLL output frequency = Fref * (DIV_SELECT + NUM/DENOM). */ - freqTmp = ((uint64_t)freq * ((uint64_t)(CCM_ANALOG->PLL_SYS_NUM))) / ((uint64_t)(CCM_ANALOG->PLL_SYS_DENOM)); + freqTmp = ((clock_64b_t)freq * ((clock_64b_t)(CCM_ANALOG->PLL_SYS_NUM))) / + ((clock_64b_t)(CCM_ANALOG->PLL_SYS_DENOM)); if (CCM_ANALOG->PLL_SYS & CCM_ANALOG_PLL_SYS_DIV_SELECT_MASK) { @@ -530,16 +891,16 @@ uint32_t CLOCK_GetPllFreq(clock_pll_t pll) break; case kCLOCK_PllUsb1: - freq = (CLOCK_GetOscFreq() * ((CCM_ANALOG->PLL_USB1 & CCM_ANALOG_PLL_USB1_DIV_SELECT_MASK) ? 22U : 20U)); + freq = (freq * ((CCM_ANALOG->PLL_USB1 & CCM_ANALOG_PLL_USB1_DIV_SELECT_MASK) ? 22U : 20U)); break; case kCLOCK_PllAudio: - freq = CLOCK_GetOscFreq(); - /* PLL output frequency = Fref * (DIV_SELECT + NUM/DENOM). */ - divSelect = (CCM_ANALOG->PLL_AUDIO & CCM_ANALOG_PLL_AUDIO_DIV_SELECT_MASK) >> CCM_ANALOG_PLL_AUDIO_DIV_SELECT_SHIFT; + divSelect = + (CCM_ANALOG->PLL_AUDIO & CCM_ANALOG_PLL_AUDIO_DIV_SELECT_MASK) >> CCM_ANALOG_PLL_AUDIO_DIV_SELECT_SHIFT; - freqTmp = ((uint64_t)freq * ((uint64_t)(CCM_ANALOG->PLL_AUDIO_NUM))) / ((uint64_t)(CCM_ANALOG->PLL_AUDIO_DENOM)); + freqTmp = ((clock_64b_t)freq * ((clock_64b_t)(CCM_ANALOG->PLL_AUDIO_NUM))) / + ((clock_64b_t)(CCM_ANALOG->PLL_AUDIO_DENOM)); freq = freq * divSelect + (uint32_t)freqTmp; @@ -589,12 +950,12 @@ uint32_t CLOCK_GetPllFreq(clock_pll_t pll) break; case kCLOCK_PllVideo: - freq = CLOCK_GetOscFreq(); - /* PLL output frequency = Fref * (DIV_SELECT + NUM/DENOM). */ - divSelect = (CCM_ANALOG->PLL_VIDEO & CCM_ANALOG_PLL_VIDEO_DIV_SELECT_MASK) >> CCM_ANALOG_PLL_VIDEO_DIV_SELECT_SHIFT; + divSelect = + (CCM_ANALOG->PLL_VIDEO & CCM_ANALOG_PLL_VIDEO_DIV_SELECT_MASK) >> CCM_ANALOG_PLL_VIDEO_DIV_SELECT_SHIFT; - freqTmp = ((uint64_t)freq * ((uint64_t)(CCM_ANALOG->PLL_VIDEO_NUM))) / ((uint64_t)(CCM_ANALOG->PLL_VIDEO_DENOM)); + freqTmp = ((clock_64b_t)freq * ((clock_64b_t)(CCM_ANALOG->PLL_VIDEO_NUM))) / + ((clock_64b_t)(CCM_ANALOG->PLL_VIDEO_DENOM)); freq = freq * divSelect + (uint32_t)freqTmp; @@ -642,28 +1003,20 @@ uint32_t CLOCK_GetPllFreq(clock_pll_t pll) break; } break; - - case kCLOCK_PllEnet0: - divSelect = (CCM_ANALOG->PLL_ENET & CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT_MASK) - >> CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT_SHIFT; + case kCLOCK_PllEnet: + divSelect = + (CCM_ANALOG->PLL_ENET & CCM_ANALOG_PLL_ENET_DIV_SELECT_MASK) >> CCM_ANALOG_PLL_ENET_DIV_SELECT_SHIFT; freq = enetRefClkFreq[divSelect]; break; - case kCLOCK_PllEnet1: - divSelect = (CCM_ANALOG->PLL_ENET & CCM_ANALOG_PLL_ENET_ENET1_DIV_SELECT_MASK) - >> CCM_ANALOG_PLL_ENET_ENET1_DIV_SELECT_SHIFT; - freq = enetRefClkFreq[divSelect]; - break; - - case kCLOCK_PllEnet2: - /* ref_enetpll2 if fixed at 25MHz. */ + case kCLOCK_PllEnet25M: + /* ref_enetpll1 if fixed at 25MHz. */ freq = 25000000UL; break; case kCLOCK_PllUsb2: - freq = (CLOCK_GetOscFreq() * ((CCM_ANALOG->PLL_USB2 & CCM_ANALOG_PLL_USB2_DIV_SELECT_MASK) ? 22U : 20U)); + freq = (freq * ((CCM_ANALOG->PLL_USB2 & CCM_ANALOG_PLL_USB2_DIV_SELECT_MASK) ? 22U : 20U)); break; - default: freq = 0U; break; @@ -672,12 +1025,23 @@ uint32_t CLOCK_GetPllFreq(clock_pll_t pll) return freq; } +/*! + * brief Initialize the System PLL PFD. + * + * This function initializes the System PLL PFD. During new value setting, + * the clock output is disabled to prevent glitch. + * + * param pfd Which PFD clock to enable. + * param pfdFrac The PFD FRAC value. + * note It is recommended that PFD settings are kept between 12-35. + */ void CLOCK_InitSysPfd(clock_pfd_t pfd, uint8_t pfdFrac) { uint32_t pfdIndex = (uint32_t)pfd; uint32_t pfd528; - pfd528 = CCM_ANALOG->PFD_528 & ~((CCM_ANALOG_PFD_528_PFD0_CLKGATE_MASK | CCM_ANALOG_PFD_528_PFD0_FRAC_MASK) << (8 * pfdIndex)); + pfd528 = CCM_ANALOG->PFD_528 & + ~((CCM_ANALOG_PFD_528_PFD0_CLKGATE_MASK | CCM_ANALOG_PFD_528_PFD0_FRAC_MASK) << (8 * pfdIndex)); /* Disable the clock output first. */ CCM_ANALOG->PFD_528 = pfd528 | (CCM_ANALOG_PFD_528_PFD0_CLKGATE_MASK << (8 * pfdIndex)); @@ -686,17 +1050,35 @@ void CLOCK_InitSysPfd(clock_pfd_t pfd, uint8_t pfdFrac) CCM_ANALOG->PFD_528 = pfd528 | (CCM_ANALOG_PFD_528_PFD0_FRAC(pfdFrac) << (8 * pfdIndex)); } +/*! + * brief De-initialize the System PLL PFD. + * + * This function disables the System PLL PFD. + * + * param pfd Which PFD clock to disable. + */ void CLOCK_DeinitSysPfd(clock_pfd_t pfd) { CCM_ANALOG->PFD_528 |= CCM_ANALOG_PFD_528_PFD0_CLKGATE_MASK << (8 * pfd); } +/*! + * brief Initialize the USB1 PLL PFD. + * + * This function initializes the USB1 PLL PFD. During new value setting, + * the clock output is disabled to prevent glitch. + * + * param pfd Which PFD clock to enable. + * param pfdFrac The PFD FRAC value. + * note It is recommended that PFD settings are kept between 12-35. + */ void CLOCK_InitUsb1Pfd(clock_pfd_t pfd, uint8_t pfdFrac) { uint32_t pfdIndex = (uint32_t)pfd; uint32_t pfd480; - pfd480 = CCM_ANALOG->PFD_480 & ~((CCM_ANALOG_PFD_480_PFD0_CLKGATE_MASK | CCM_ANALOG_PFD_480_PFD0_FRAC_MASK) << (8 * pfdIndex)); + pfd480 = CCM_ANALOG->PFD_480 & + ~((CCM_ANALOG_PFD_480_PFD0_CLKGATE_MASK | CCM_ANALOG_PFD_480_PFD0_FRAC_MASK) << (8 * pfdIndex)); /* Disable the clock output first. */ CCM_ANALOG->PFD_480 = pfd480 | (CCM_ANALOG_PFD_480_PFD0_CLKGATE_MASK << (8 * pfdIndex)); @@ -705,11 +1087,26 @@ void CLOCK_InitUsb1Pfd(clock_pfd_t pfd, uint8_t pfdFrac) CCM_ANALOG->PFD_480 = pfd480 | (CCM_ANALOG_PFD_480_PFD0_FRAC(pfdFrac) << (8 * pfdIndex)); } +/*! + * brief De-initialize the USB1 PLL PFD. + * + * This function disables the USB1 PLL PFD. + * + * param pfd Which PFD clock to disable. + */ void CLOCK_DeinitUsb1Pfd(clock_pfd_t pfd) { CCM_ANALOG->PFD_480 |= CCM_ANALOG_PFD_480_PFD0_CLKGATE_MASK << (8 * pfd); } +/*! + * brief Get current System PLL PFD output frequency. + * + * This function get current output frequency of specific System PLL PFD + * + * param pfd pfd name to get frequency. + * return The PFD output frequency in hertz. + */ uint32_t CLOCK_GetSysPfdFreq(clock_pfd_t pfd) { uint32_t freq = CLOCK_GetPllFreq(kCLOCK_PllSys); @@ -741,6 +1138,14 @@ uint32_t CLOCK_GetSysPfdFreq(clock_pfd_t pfd) return freq; } +/*! + * brief Get current USB1 PLL PFD output frequency. + * + * This function get current output frequency of specific USB1 PLL PFD + * + * param pfd pfd name to get frequency. + * return The PFD output frequency in hertz. + */ uint32_t CLOCK_GetUsb1PfdFreq(clock_pfd_t pfd) { uint32_t freq = CLOCK_GetPllFreq(kCLOCK_PllUsb1); @@ -765,78 +1170,42 @@ uint32_t CLOCK_GetUsb1PfdFreq(clock_pfd_t pfd) default: freq = 0U; - break; + break; } freq *= 18U; return freq; } -bool CLOCK_EnableUsbhs0Clock(clock_usb_src_t src, uint32_t freq) -{ - CCM->CCGR6 |= CCM_CCGR6_CG0_MASK ; - USB1->USBCMD |= USBHS_USBCMD_RST_MASK; - for (volatile uint32_t i = 0; i < 400000; i++) /* Add a delay between RST and RS so make sure there is a DP pullup sequence*/ - { - __ASM("nop"); - } - PMU->REG_3P0 = (PMU->REG_3P0 & (~PMU_REG_3P0_OUTPUT_TRG_MASK)) | (PMU_REG_3P0_OUTPUT_TRG(0x17) | PMU_REG_3P0_ENABLE_LINREG_MASK); - return true; -} - - -bool CLOCK_EnableUsbhs1Clock(clock_usb_src_t src, uint32_t freq) -{ - CCM->CCGR6 |= CCM_CCGR6_CG0_MASK ; - USB2->USBCMD |= USBHS_USBCMD_RST_MASK; - for (volatile uint32_t i = 0; i < 400000; i++) /* Add a delay between RST and RS so make sure there is a DP pullup sequence*/ - { - __ASM("nop"); - } - PMU->REG_3P0 = (PMU->REG_3P0 & (~PMU_REG_3P0_OUTPUT_TRG_MASK)) | (PMU_REG_3P0_OUTPUT_TRG(0x17) | PMU_REG_3P0_ENABLE_LINREG_MASK); - return true; -} - - -bool CLOCK_EnableUsbhs0PhyPllClock(clock_usb_phy_src_t src, uint32_t freq) -{ - const clock_usb_pll_config_t g_ccmConfigUsbPll = {.loopDivider = 0U}; - CLOCK_InitUsb1Pll(&g_ccmConfigUsbPll); - USBPHY1->CTRL &= ~USBPHY_CTRL_SFTRST_MASK; /* release PHY from reset */ - USBPHY1->CTRL &= ~USBPHY_CTRL_CLKGATE_MASK; - - USBPHY1->PWD = 0; - USBPHY1->CTRL |= - USBPHY_CTRL_ENAUTOCLR_PHY_PWD_MASK | - USBPHY_CTRL_ENAUTOCLR_CLKGATE_MASK | - USBPHY_CTRL_ENUTMILEVEL2_MASK | - USBPHY_CTRL_ENUTMILEVEL3_MASK; - return true; -} +/*! brief Enable USB HS PHY PLL clock. + * + * This function enables the internal 480MHz USB PHY PLL clock. + * + * param src USB HS PHY PLL clock source. + * param freq The frequency specified by src. + * retval true The clock is set successfully. + * retval false The clock source is invalid to get proper USB HS clock. + */ bool CLOCK_EnableUsbhs1PhyPllClock(clock_usb_phy_src_t src, uint32_t freq) { - const clock_usb_pll_config_t g_ccmConfigUsbPll = {.loopDivider = 0U}; + const clock_usb_pll_config_t g_ccmConfigUsbPll = {.loopDivider = 0U}; CLOCK_InitUsb2Pll(&g_ccmConfigUsbPll); - USBPHY2->CTRL &= ~USBPHY_CTRL_SFTRST_MASK; /* release PHY from reset */ + USBPHY2->CTRL &= ~USBPHY_CTRL_SFTRST_MASK; /* release PHY from reset */ USBPHY2->CTRL &= ~USBPHY_CTRL_CLKGATE_MASK; - USBPHY2->PWD = 0; - USBPHY2->CTRL |= - USBPHY_CTRL_ENAUTOCLR_PHY_PWD_MASK | - USBPHY_CTRL_ENAUTOCLR_CLKGATE_MASK | - USBPHY_CTRL_ENUTMILEVEL2_MASK | - USBPHY_CTRL_ENUTMILEVEL3_MASK; + USBPHY2->PWD = 0; + USBPHY2->CTRL |= USBPHY_CTRL_ENAUTOCLR_PHY_PWD_MASK | USBPHY_CTRL_ENAUTOCLR_CLKGATE_MASK | + USBPHY_CTRL_ENUTMILEVEL2_MASK | USBPHY_CTRL_ENUTMILEVEL3_MASK; return true; } -void CLOCK_DisableUsbhs0PhyPllClock(void) -{ - CLOCK_DeinitUsb1Pll(); - USBPHY1->CTRL |= USBPHY_CTRL_CLKGATE_MASK; /* Set to 1U to gate clocks */ -} +/*! brief Disable USB HS PHY PLL clock. + * + * This function disables USB HS PHY PLL clock. + */ void CLOCK_DisableUsbhs1PhyPllClock(void) { - CLOCK_DeinitUsb2Pll(); - USBPHY2->CTRL |= USBPHY_CTRL_CLKGATE_MASK; /* Set to 1U to gate clocks */ + CCM_ANALOG->PLL_USB2 &= ~CCM_ANALOG_PLL_USB2_EN_USB_CLKS_MASK; + USBPHY2->CTRL |= USBPHY_CTRL_CLKGATE_MASK; /* Set to 1U to gate clocks */ } diff --git a/ext/hal/nxp/mcux/devices/MIMXRT1052/fsl_clock.h b/ext/hal/nxp/mcux/devices/MIMXRT1052/fsl_clock.h index 57b7df7ed12..a562eda0a23 100644 --- a/ext/hal/nxp/mcux/devices/MIMXRT1052/fsl_clock.h +++ b/ext/hal/nxp/mcux/devices/MIMXRT1052/fsl_clock.h @@ -1,55 +1,23 @@ /* * Copyright 2017 NXP + * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * SPDX-License-Identifier: BSD-3-Clause */ #ifndef _FSL_CLOCK_H_ #define _FSL_CLOCK_H_ -#include "fsl_device_registers.h" -#include -#include -#include +#include "fsl_common.h" -/*! - * @addtogroup clock - * @{ - */ +/*! @addtogroup clock */ +/*! @{ */ + +/*! @file */ /******************************************************************************* - * Definitions + * Configurations ******************************************************************************/ -#define CCM_TUPLE(reg, shift, mask, busyShift) ((((uint32_t)(&((CCM_Type *)0U)->reg)) & 0xFFU) | ((shift) << 8U) | ((((mask) >> (shift)) & 0x1FFFU) << 13U) | ((busyShift) << 26U)) -#define CCM_TUPLE_REG(base, tuple) (*((volatile uint32_t *)(((uint32_t)(base)) + ((tuple) & 0xFFU)))) -#define CCM_TUPLE_SHIFT(tuple) (((tuple) >> 8U) & 0x1FU) -#define CCM_TUPLE_MASK(tuple) ((uint32_t)((((tuple) >> 13U) & 0x1FFFU) << ((((tuple) >> 8U) & 0x1FU)))) -#define CCM_TUPLE_BUSY_SHIFT(tuple) (((tuple) >> 26U) & 0x3FU) - -#define CCM_NO_BUSY_WAIT (0x20U) /*! @brief Configure whether driver controls clock * @@ -65,12 +33,44 @@ #define FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL 0 #endif +/******************************************************************************* + * Definitions + ******************************************************************************/ + /*! @name Driver version */ /*@{*/ -/*! @brief CLOCK driver version 2.1.0. */ -#define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 1, 0)) -/*@}*/ +/*! @brief CLOCK driver version 2.1.5. */ +#define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 1, 5)) +/* analog pll definition */ +#define CCM_ANALOG_PLL_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_BYPASS_CLK_SRC_SHIFT (14U) + +/*@}*/ +#define CCM_TUPLE(reg, shift, mask, busyShift) \ + (int)((((uint32_t)(&((CCM_Type *)0U)->reg)) & 0xFFU) | ((shift) << 8U) | \ + ((((mask) >> (shift)) & 0x1FFFU) << 13U) | ((busyShift) << 26U)) +#define CCM_TUPLE_REG(base, tuple) (*((volatile uint32_t *)(((uint32_t)(base)) + ((tuple)&0xFFU)))) +#define CCM_TUPLE_SHIFT(tuple) (((tuple) >> 8U) & 0x1FU) +#define CCM_TUPLE_MASK(tuple) ((uint32_t)((((tuple) >> 13U) & 0x1FFFU) << ((((tuple) >> 8U) & 0x1FU)))) +#define CCM_TUPLE_BUSY_SHIFT(tuple) (((tuple) >> 26U) & 0x3FU) + +#define CCM_NO_BUSY_WAIT (0x20U) + +/*! + * @brief CCM ANALOG tuple macros to map corresponding registers and bit fields. + */ +#define CCM_ANALOG_TUPLE(reg, shift) ((((uint32_t)(&((CCM_ANALOG_Type *)0U)->reg) & 0xFFFU) << 16U) | (shift)) +#define CCM_ANALOG_TUPLE_SHIFT(tuple) (((uint32_t)tuple) & 0x1FU) +#define CCM_ANALOG_TUPLE_REG_OFF(base, tuple, off) \ + (*((volatile uint32_t *)((uint32_t)base + (((uint32_t)tuple >> 16U) & 0xFFFU) + off))) +#define CCM_ANALOG_TUPLE_REG(base, tuple) CCM_ANALOG_TUPLE_REG_OFF(base, tuple, 0U) + +/*! + * @brief clock1PN frequency. + */ +#define CLKPN_FREQ 0U /*! @brief External XTAL (24M OSC/SYSOSC) clock frequency. * @@ -82,323 +82,318 @@ * CLOCK_SetXtalFreq(240000000); // Set the XTAL value to clock driver. * @endcode */ -extern uint32_t g_xtalFreq; +extern volatile uint32_t g_xtalFreq; /*! @brief External RTC XTAL (32K OSC) clock frequency. * * The RTC XTAL (32K OSC) clock frequency in Hz, when the clock is setup, use the * function CLOCK_SetRtcXtalFreq to set the value in to clock driver. */ -extern uint32_t g_rtcXtalFreq; +extern volatile uint32_t g_rtcXtalFreq; /* For compatible with other platforms */ #define CLOCK_SetXtal0Freq CLOCK_SetXtalFreq #define CLOCK_SetXtal32Freq CLOCK_SetRtcXtalFreq - /*! @brief Clock ip name array for ADC. */ -#define ADC_CLOCKS \ - { \ - kCLOCK_IpInvalid, kCLOCK_Adc1 \ - } - -/*! @brief Clock ip name array for ADC_5HC. */ -#define ADC_5HC_CLOCKS \ - { \ - kCLOCK_Adc_5hc \ +/*! @brief Clock ip name array for ADC. */ +#define ADC_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_Adc1, kCLOCK_Adc2 \ } /*! @brief Clock ip name array for AOI. */ -#define AOI_CLOCKS \ - { \ - kCLOCK_IpInvalid, kCLOCK_Aoi1, kCLOCK_Aoi2 \ +#define AOI_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_Aoi1, kCLOCK_Aoi2 \ } /*! @brief Clock ip name array for BEE. */ -#define BEE_CLOCKS \ - { \ - kCLOCK_Bee \ - } +#define BEE_CLOCKS \ + { \ + kCLOCK_Bee \ + } /*! @brief Clock ip name array for CMP. */ -#define CMP_CLOCKS \ - { \ - kCLOCK_IpInvalid, kCLOCK_Acmp1, kCLOCK_Acmp2, \ - kCLOCK_Acmp3, kCLOCK_Acmp4 \ +#define CMP_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_Acmp1, kCLOCK_Acmp2, kCLOCK_Acmp3, kCLOCK_Acmp4 \ } /*! @brief Clock ip name array for CSI. */ -#define CSI_CLOCKS \ - { \ - kCLOCK_Csi \ +#define CSI_CLOCKS \ + { \ + kCLOCK_Csi \ } /*! @brief Clock ip name array for DCDC. */ -#define DCDC_CLOCKS \ - { \ - kCLOCK_Dcdc \ +#define DCDC_CLOCKS \ + { \ + kCLOCK_Dcdc \ } /*! @brief Clock ip name array for DCP. */ -#define DCP_CLOCKS \ - { \ - kCLOCK_Dcp \ +#define DCP_CLOCKS \ + { \ + kCLOCK_Dcp \ } /*! @brief Clock ip name array for DMAMUX_CLOCKS. */ -#define DMAMUX_CLOCKS \ - { \ - kCLOCK_Dma \ - } +#define DMAMUX_CLOCKS \ + { \ + kCLOCK_Dma \ + } /*! @brief Clock ip name array for DMA. */ -#define EDMA_CLOCKS \ - { \ - kCLOCK_Dma \ - } +#define EDMA_CLOCKS \ + { \ + kCLOCK_Dma \ + } /*! @brief Clock ip name array for ENC. */ -#define ENC_CLOCKS \ - { \ - kCLOCK_IpInvalid, kCLOCK_Enc1, kCLOCK_Enc2, \ - kCLOCK_Enc3, kCLOCK_Enc4 \ +#define ENC_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_Enc1, kCLOCK_Enc2, kCLOCK_Enc3, kCLOCK_Enc4 \ } /*! @brief Clock ip name array for ENET. */ -#define ENET_CLOCKS \ - { \ - kCLOCK_Enet \ +#define ENET_CLOCKS \ + { \ + kCLOCK_Enet \ } /*! @brief Clock ip name array for EWM. */ -#define EWM_CLOCKS \ - { \ - kCLOCK_Ewm0 \ - } +#define EWM_CLOCKS \ + { \ + kCLOCK_Ewm0 \ + } /*! @brief Clock ip name array for FLEXCAN. */ -#define FLEXCAN_CLOCKS \ - { \ - kCLOCK_IpInvalid, kCLOCK_Can1, kCLOCK_Can2 \ +#define FLEXCAN_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_Can1, kCLOCK_Can2 \ } - + /*! @brief Clock ip name array for FLEXCAN Peripheral clock. */ -#define FLEXCAN_PERIPH_CLOCKS \ - { \ - kCLOCK_IpInvalid, kCLOCK_Can1S, kCLOCK_Can2S \ - } +#define FLEXCAN_PERIPH_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_Can1S, kCLOCK_Can2S \ + } /*! @brief Clock ip name array for FLEXIO. */ -#define FLEXIO_CLOCKS \ - { \ - kCLOCK_IpInvalid, kCLOCK_Flexio1, kCLOCK_Flexio2 \ +#define FLEXIO_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_Flexio1, kCLOCK_Flexio2 \ } /*! @brief Clock ip name array for FLEXRAM. */ -#define FLEXRAM_CLOCKS \ - { \ - kCLOCK_FlexRam \ - } +#define FLEXRAM_CLOCKS \ + { \ + kCLOCK_FlexRam \ + } /*! @brief Clock ip name array for FLEXSPI. */ -#define FLEXSPI_CLOCKS \ - { \ - kCLOCK_FlexSpi \ - } +#define FLEXSPI_CLOCKS \ + { \ + kCLOCK_FlexSpi \ + } + +/*! @brief Clock ip name array for FLEXSPI EXSC. */ +#define FLEXSPI_EXSC_CLOCKS \ + { \ + kCLOCK_FlexSpiExsc \ + } /*! @brief Clock ip name array for GPIO. */ -#define GPIO_CLOCKS \ - { \ - kCLOCK_IpInvalid, kCLOCK_Gpio1, kCLOCK_Gpio2, \ - kCLOCK_Gpio3, kCLOCK_Gpio4, kCLOCK_Gpio5 \ +#define GPIO_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_Gpio1, kCLOCK_Gpio2, kCLOCK_Gpio3, kCLOCK_Gpio4, kCLOCK_Gpio5 \ } /*! @brief Clock ip name array for GPT. */ -#define GPT_CLOCKS \ - { \ - kCLOCK_IpInvalid, kCLOCK_Gpt1, kCLOCK_Gpt2 \ +#define GPT_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_Gpt1, kCLOCK_Gpt2 \ } /*! @brief Clock ip name array for KPP. */ -#define KPP_CLOCKS \ - { \ - kCLOCK_Kpp \ - } - +#define KPP_CLOCKS \ + { \ + kCLOCK_Kpp \ + } + /*! @brief Clock ip name array for LCDIF. */ -#define LCDIF_CLOCKS \ - { \ - kCLOCK_Lcd \ +#define LCDIF_CLOCKS \ + { \ + kCLOCK_Lcd \ } /*! @brief Clock ip name array for LCDIF PIXEL. */ -#define LCDIF_PERIPH_CLOCKS \ - { \ - kCLOCK_LcdPixel \ +#define LCDIF_PERIPH_CLOCKS \ + { \ + kCLOCK_LcdPixel \ } /*! @brief Clock ip name array for LPI2C. */ -#define LPI2C_CLOCKS \ - { \ - kCLOCK_IpInvalid, kCLOCK_Lpi2c1, kCLOCK_Lpi2c2, \ - kCLOCK_Lpi2c3, kCLOCK_Lpi2c4 \ - } +#define LPI2C_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_Lpi2c1, kCLOCK_Lpi2c2, kCLOCK_Lpi2c3, kCLOCK_Lpi2c4 \ + } /*! @brief Clock ip name array for LPSPI. */ -#define LPSPI_CLOCKS \ - { \ - kCLOCK_IpInvalid, kCLOCK_Lpspi1, kCLOCK_Lpspi2, \ - kCLOCK_Lpspi3, kCLOCK_Lpspi4 \ - } +#define LPSPI_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_Lpspi1, kCLOCK_Lpspi2, kCLOCK_Lpspi3, kCLOCK_Lpspi4 \ + } /*! @brief Clock ip name array for LPUART. */ -#define LPUART_CLOCKS \ - { \ - kCLOCK_IpInvalid, kCLOCK_Lpuart1, kCLOCK_Lpuart2, \ - kCLOCK_Lpuart3, kCLOCK_Lpuart4, kCLOCK_Lpuart5, \ - kCLOCK_Lpuart6, kCLOCK_Lpuart7, kCLOCK_Lpuart8 \ - } +#define LPUART_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_Lpuart1, kCLOCK_Lpuart2, kCLOCK_Lpuart3, kCLOCK_Lpuart4, kCLOCK_Lpuart5, \ + kCLOCK_Lpuart6, kCLOCK_Lpuart7, kCLOCK_Lpuart8 \ + } + +/*! @brief Clock ip name array for MQS. */ +#define MQS_CLOCKS \ + { \ + kCLOCK_Mqs \ + } + +/*! @brief Clock ip name array for OCRAM EXSC. */ +#define OCRAM_EXSC_CLOCKS \ + { \ + kCLOCK_OcramExsc \ + } /*! @brief Clock ip name array for PIT. */ -#define PIT_CLOCKS \ - { \ - kCLOCK_Pit \ +#define PIT_CLOCKS \ + { \ + kCLOCK_Pit \ } /*! @brief Clock ip name array for PWM. */ -#define PWM_CLOCKS \ - { \ - { \ - kCLOCK_IpInvalid, kCLOCK_IpInvalid, kCLOCK_IpInvalid, \ - kCLOCK_IpInvalid \ - } \ - , \ - { \ - kCLOCK_Pwm1, kCLOCK_Pwm1,kCLOCK_Pwm1, kCLOCK_Pwm1 \ - } \ - , \ - { \ - kCLOCK_Pwm2, kCLOCK_Pwm2,kCLOCK_Pwm2, kCLOCK_Pwm2 \ - } \ - , \ - { \ - kCLOCK_Pwm3, kCLOCK_Pwm3,kCLOCK_Pwm3, kCLOCK_Pwm3 \ - } \ - , \ - { \ - kCLOCK_Pwm4, kCLOCK_Pwm4,kCLOCK_Pwm4, kCLOCK_Pwm4 \ - } \ - } +#define PWM_CLOCKS \ + { \ + { \ + kCLOCK_IpInvalid, kCLOCK_IpInvalid, kCLOCK_IpInvalid, kCLOCK_IpInvalid \ + } \ + , {kCLOCK_Pwm1, kCLOCK_Pwm1, kCLOCK_Pwm1, kCLOCK_Pwm1}, {kCLOCK_Pwm2, kCLOCK_Pwm2, kCLOCK_Pwm2, kCLOCK_Pwm2}, \ + {kCLOCK_Pwm3, kCLOCK_Pwm3, kCLOCK_Pwm3, kCLOCK_Pwm3}, \ + { \ + kCLOCK_Pwm4, kCLOCK_Pwm4, kCLOCK_Pwm4, kCLOCK_Pwm4 \ + } \ + } /*! @brief Clock ip name array for PXP. */ -#define PXP_CLOCKS \ - { \ - kCLOCK_Pxp \ +#define PXP_CLOCKS \ + { \ + kCLOCK_Pxp \ } /*! @brief Clock ip name array for RTWDOG. */ -#define RTWDOG_CLOCKS \ - { \ - kCLOCK_Wdog3 \ - } +#define RTWDOG_CLOCKS \ + { \ + kCLOCK_Wdog3 \ + } /*! @brief Clock ip name array for SAI. */ -#define SAI_CLOCKS \ - { \ - kCLOCK_IpInvalid, kCLOCK_Sai1, kCLOCK_Sai2, \ - kCLOCK_Sai3 \ +#define SAI_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_Sai1, kCLOCK_Sai2, kCLOCK_Sai3 \ } /*! @brief Clock ip name array for SEMC. */ -#define SEMC_CLOCKS \ - { \ - kCLOCK_Semc \ +#define SEMC_CLOCKS \ + { \ + kCLOCK_Semc \ } +/*! @brief Clock ip name array for SEMC EXSC. */ +#define SEMC_EXSC_CLOCKS \ + { \ + kCLOCK_SemcExsc \ + } /*! @brief Clock ip name array for QTIMER. */ -#define TMR_CLOCKS \ - { \ - kCLOCK_IpInvalid, kCLOCK_Timer1, kCLOCK_Timer2, \ - kCLOCK_Timer3, kCLOCK_Timer4 \ +#define TMR_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_Timer1, kCLOCK_Timer2, kCLOCK_Timer3, kCLOCK_Timer4 \ } /*! @brief Clock ip name array for TRNG. */ -#define TRNG_CLOCKS \ - { \ - kCLOCK_Trng \ +#define TRNG_CLOCKS \ + { \ + kCLOCK_Trng \ } /*! @brief Clock ip name array for TSC. */ -#define TSC_CLOCKS \ - { \ - kCLOCK_Tsc \ - } - -/*! @brief Clock ip name array for WDOG. */ -#define WDOG_CLOCKS \ - { \ - kCLOCK_IpInvalid, kCLOCK_Wdog1, kCLOCK_Wdog2 \ +#define TSC_CLOCKS \ + { \ + kCLOCK_Tsc \ } +/*! @brief Clock ip name array for WDOG. */ +#define WDOG_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_Wdog1, kCLOCK_Wdog2 \ + } /*! @brief Clock ip name array for USDHC. */ -#define USDHC_CLOCKS \ - { \ - kCLOCK_IpInvalid, kCLOCK_Usdhc1, kCLOCK_Usdhc2 \ +#define USDHC_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_Usdhc1, kCLOCK_Usdhc2 \ } - + /*! @brief Clock ip name array for SPDIF. */ -#define SPDIF_CLOCKS \ - { \ - kCLOCK_Spdif \ +#define SPDIF_CLOCKS \ + { \ + kCLOCK_Spdif \ } - + /*! @brief Clock ip name array for XBARA. */ -#define XBARA_CLOCKS \ - { \ - kCLOCK_Xbar1 \ - } +#define XBARA_CLOCKS \ + { \ + kCLOCK_Xbar1 \ + } /*! @brief Clock ip name array for XBARB. */ -#define XBARB_CLOCKS \ - { \ - kCLOCK_IpInvalid, kCLOCK_IpInvalid, kCLOCK_Xbar2, \ - kCLOCK_Xbar3 \ - } +#define XBARB_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_IpInvalid, kCLOCK_Xbar2, kCLOCK_Xbar3 \ + } /*! @brief Clock name used to get clock frequency. */ typedef enum _clock_name { - kCLOCK_CpuClk = 0x0U, /*!< CPU clock */ - kCLOCK_AhbClk = 0x1U, /*!< AHB clock */ - kCLOCK_SemcClk = 0x2U, /*!< SEMC clock */ - kCLOCK_IpgClk = 0x3U, /*!< IPG clock */ + kCLOCK_CpuClk = 0x0U, /*!< CPU clock */ + kCLOCK_AhbClk = 0x1U, /*!< AHB clock */ + kCLOCK_SemcClk = 0x2U, /*!< SEMC clock */ + kCLOCK_IpgClk = 0x3U, /*!< IPG clock */ + kCLOCK_PerClk = 0x4U, /*!< PER clock */ - kCLOCK_OscClk = 0x4U, /*!< OSC clock selected by PMU_LOWPWR_CTRL[OSC_SEL]. */ - kCLOCK_RtcClk = 0x5U, /*!< RTC clock. (RTCCLK) */ + kCLOCK_OscClk = 0x5U, /*!< OSC clock selected by PMU_LOWPWR_CTRL[OSC_SEL]. */ + kCLOCK_RtcClk = 0x6U, /*!< RTC clock. (RTCCLK) */ - kCLOCK_ArmPllClk = 0x6U, /*!< ARMPLLCLK. */ + kCLOCK_ArmPllClk = 0x7U, /*!< ARMPLLCLK. */ - kCLOCK_Usb1PllClk = 0x7U, /*!< USB1PLLCLK. */ - kCLOCK_Usb1PllPfd0Clk = 0x8U, /*!< USB1PLLPDF0CLK. */ - kCLOCK_Usb1PllPfd1Clk = 0x9U, /*!< USB1PLLPFD1CLK. */ - kCLOCK_Usb1PllPfd2Clk = 0xAU, /*!< USB1PLLPFD2CLK. */ - kCLOCK_Usb1PllPfd3Clk = 0xBU, /*!< USB1PLLPFD3CLK. */ + kCLOCK_Usb1PllClk = 0x8U, /*!< USB1PLLCLK. */ + kCLOCK_Usb1PllPfd0Clk = 0x9U, /*!< USB1PLLPDF0CLK. */ + kCLOCK_Usb1PllPfd1Clk = 0xAU, /*!< USB1PLLPFD1CLK. */ + kCLOCK_Usb1PllPfd2Clk = 0xBU, /*!< USB1PLLPFD2CLK. */ + kCLOCK_Usb1PllPfd3Clk = 0xCU, /*!< USB1PLLPFD3CLK. */ - kCLOCK_Usb2PllClk = 0xCU, /*!< USB2PLLCLK. */ + kCLOCK_Usb2PllClk = 0xDU, /*!< USB2PLLCLK. */ - kCLOCK_SysPllClk = 0xDU, /*!< SYSPLLCLK. */ - kCLOCK_SysPllPfd0Clk = 0xEU, /*!< SYSPLLPDF0CLK. */ - kCLOCK_SysPllPfd1Clk = 0xFU, /*!< SYSPLLPFD1CLK. */ - kCLOCK_SysPllPfd2Clk = 0x10U, /*!< SYSPLLPFD2CLK. */ - kCLOCK_SysPllPfd3Clk = 0x11U, /*!< SYSPLLPFD3CLK. */ + kCLOCK_SysPllClk = 0xEU, /*!< SYSPLLCLK. */ + kCLOCK_SysPllPfd0Clk = 0xFU, /*!< SYSPLLPDF0CLK. */ + kCLOCK_SysPllPfd1Clk = 0x10U, /*!< SYSPLLPFD1CLK. */ + kCLOCK_SysPllPfd2Clk = 0x11U, /*!< SYSPLLPFD2CLK. */ + kCLOCK_SysPllPfd3Clk = 0x12U, /*!< SYSPLLPFD3CLK. */ - kCLOCK_EnetPll0Clk = 0x12U, /*!< Enet PLLCLK ref_enetpll0. */ - kCLOCK_EnetPll1Clk = 0x13U, /*!< Enet PLLCLK ref_enetpll1. */ - kCLOCK_EnetPll2Clk = 0x14U, /*!< Enet PLLCLK ref_enetpll2. */ + kCLOCK_EnetPll0Clk = 0x13U, /*!< Enet PLLCLK ref_enetpll0. */ + kCLOCK_EnetPll1Clk = 0x14U, /*!< Enet PLLCLK ref_enetpll1. */ - kCLOCK_AudioPllClk = 0x15U, /*!< Audio PLLCLK. */ - kCLOCK_VideoPllClk = 0x16U, /*!< Video PLLCLK. */ + kCLOCK_AudioPllClk = 0x15U, /*!< Audio PLLCLK. */ + kCLOCK_VideoPllClk = 0x16U, /*!< Video PLLCLK. */ } clock_name_t; #define kCLOCK_CoreSysClk kCLOCK_CpuClk /*!< For compatible with other platforms without CCM. */ @@ -412,156 +407,155 @@ typedef enum _clock_ip_name kCLOCK_IpInvalid = -1, /* CCM CCGR0 */ - kCLOCK_Aips_tz1 = (0U << 8U) | CCM_CCGR0_CG0_SHIFT, /*!< CCGR0, CG0 */ - kCLOCK_Aips_tz2 = (0U << 8U) | CCM_CCGR0_CG1_SHIFT, /*!< CCGR0, CG1 */ - /*!< CCGR0, CG2, Reserved */ - /*!< CCGR0, CG3, Reserved */ - /*!< CCGR0, CG4, Reserved */ - kCLOCK_Dcp = (0U << 8U) | CCM_CCGR0_CG5_SHIFT, /*!< CCGR0, CG5 */ - kCLOCK_Lpuart3 = (0U << 8U) | CCM_CCGR0_CG6_SHIFT, /*!< CCGR0, CG6 */ - kCLOCK_Can1 = (0U << 8U) | CCM_CCGR0_CG7_SHIFT, /*!< CCGR0, CG7 */ - kCLOCK_Can1S = (0U << 8U) | CCM_CCGR0_CG8_SHIFT, /*!< CCGR0, CG8 */ - kCLOCK_Can2 = (0U << 8U) | CCM_CCGR0_CG9_SHIFT, /*!< CCGR0, CG9 */ - kCLOCK_Can2S = (0U << 8U) | CCM_CCGR0_CG10_SHIFT, /*!< CCGR0, CG10 */ - kCLOCK_Trace = (0U << 8U) | CCM_CCGR0_CG11_SHIFT, /*!< CCGR0, CG11 */ - kCLOCK_Gpt2 = (0U << 8U) | CCM_CCGR0_CG12_SHIFT, /*!< CCGR0, CG12 */ - kCLOCK_Gpt2S = (0U << 8U) | CCM_CCGR0_CG13_SHIFT, /*!< CCGR0, CG13 */ - kCLOCK_Lpuart2 = (0U << 8U) | CCM_CCGR0_CG14_SHIFT, /*!< CCGR0, CG14 */ - kCLOCK_Gpio2 = (0U << 8U) | CCM_CCGR0_CG15_SHIFT, /*!< CCGR0, CG15 */ + kCLOCK_Aips_tz1 = (0U << 8U) | CCM_CCGR0_CG0_SHIFT, /*!< CCGR0, CG0 */ + kCLOCK_Aips_tz2 = (0U << 8U) | CCM_CCGR0_CG1_SHIFT, /*!< CCGR0, CG1 */ + kCLOCK_Mqs = (0U << 8U) | CCM_CCGR0_CG2_SHIFT, /*!< CCGR0, CG2 */ + kCLOCK_FlexSpiExsc = (0U << 8U) | CCM_CCGR0_CG3_SHIFT, /*!< CCGR0, CG3 */ + kCLOCK_Sim_M_Main = (0U << 8U) | CCM_CCGR0_CG4_SHIFT, /*!< CCGR0, CG4 */ + kCLOCK_Dcp = (0U << 8U) | CCM_CCGR0_CG5_SHIFT, /*!< CCGR0, CG5 */ + kCLOCK_Lpuart3 = (0U << 8U) | CCM_CCGR0_CG6_SHIFT, /*!< CCGR0, CG6 */ + kCLOCK_Can1 = (0U << 8U) | CCM_CCGR0_CG7_SHIFT, /*!< CCGR0, CG7 */ + kCLOCK_Can1S = (0U << 8U) | CCM_CCGR0_CG8_SHIFT, /*!< CCGR0, CG8 */ + kCLOCK_Can2 = (0U << 8U) | CCM_CCGR0_CG9_SHIFT, /*!< CCGR0, CG9 */ + kCLOCK_Can2S = (0U << 8U) | CCM_CCGR0_CG10_SHIFT, /*!< CCGR0, CG10 */ + kCLOCK_Trace = (0U << 8U) | CCM_CCGR0_CG11_SHIFT, /*!< CCGR0, CG11 */ + kCLOCK_Gpt2 = (0U << 8U) | CCM_CCGR0_CG12_SHIFT, /*!< CCGR0, CG12 */ + kCLOCK_Gpt2S = (0U << 8U) | CCM_CCGR0_CG13_SHIFT, /*!< CCGR0, CG13 */ + kCLOCK_Lpuart2 = (0U << 8U) | CCM_CCGR0_CG14_SHIFT, /*!< CCGR0, CG14 */ + kCLOCK_Gpio2 = (0U << 8U) | CCM_CCGR0_CG15_SHIFT, /*!< CCGR0, CG15 */ /* CCM CCGR1 */ - kCLOCK_Lpspi1 = (1U << 8U) | CCM_CCGR1_CG0_SHIFT, /*!< CCGR1, CG0 */ - kCLOCK_Lpspi2 = (1U << 8U) | CCM_CCGR1_CG1_SHIFT, /*!< CCGR1, CG1 */ - kCLOCK_Lpspi3 = (1U << 8U) | CCM_CCGR1_CG2_SHIFT, /*!< CCGR1, CG2 */ - kCLOCK_Lpspi4 = (1U << 8U) | CCM_CCGR1_CG3_SHIFT, /*!< CCGR1, CG3 */ - kCLOCK_Adc_5hc = (1U << 8U) | CCM_CCGR1_CG4_SHIFT, /*!< CCGR1, CG4 */ - kCLOCK_Enet = (1U << 8U) | CCM_CCGR1_CG5_SHIFT, /*!< CCGR1, CG5 */ - kCLOCK_Pit = (1U << 8U) | CCM_CCGR1_CG6_SHIFT, /*!< CCGR1, CG6 */ - kCLOCK_Aoi2 = (1U << 8U) | CCM_CCGR1_CG7_SHIFT, /*!< CCGR1, CG7 */ - kCLOCK_Adc1 = (1U << 8U) | CCM_CCGR1_CG8_SHIFT, /*!< CCGR1, CG8 */ - /*!< CCGR1, CG9, Reserved */ - kCLOCK_Gpt1 = (1U << 8U) | CCM_CCGR1_CG10_SHIFT, /*!< CCGR1, CG10 */ - kCLOCK_Gpt1S = (1U << 8U) | CCM_CCGR1_CG11_SHIFT, /*!< CCGR1, CG11 */ - kCLOCK_Lpuart4 = (1U << 8U) | CCM_CCGR1_CG12_SHIFT, /*!< CCGR1, CG12 */ - kCLOCK_Gpio1 = (1U << 8U) | CCM_CCGR1_CG13_SHIFT, /*!< CCGR1, CG13 */ - kCLOCK_Csu = (1U << 8U) | CCM_CCGR1_CG14_SHIFT, /*!< CCGR1, CG14 */ - kCLOCK_Gpio5 = (1U << 8U) | CCM_CCGR1_CG15_SHIFT, /*!< CCGR1, CG15 */ + kCLOCK_Lpspi1 = (1U << 8U) | CCM_CCGR1_CG0_SHIFT, /*!< CCGR1, CG0 */ + kCLOCK_Lpspi2 = (1U << 8U) | CCM_CCGR1_CG1_SHIFT, /*!< CCGR1, CG1 */ + kCLOCK_Lpspi3 = (1U << 8U) | CCM_CCGR1_CG2_SHIFT, /*!< CCGR1, CG2 */ + kCLOCK_Lpspi4 = (1U << 8U) | CCM_CCGR1_CG3_SHIFT, /*!< CCGR1, CG3 */ + kCLOCK_Adc2 = (1U << 8U) | CCM_CCGR1_CG4_SHIFT, /*!< CCGR1, CG4 */ + kCLOCK_Enet = (1U << 8U) | CCM_CCGR1_CG5_SHIFT, /*!< CCGR1, CG5 */ + kCLOCK_Pit = (1U << 8U) | CCM_CCGR1_CG6_SHIFT, /*!< CCGR1, CG6 */ + kCLOCK_Aoi2 = (1U << 8U) | CCM_CCGR1_CG7_SHIFT, /*!< CCGR1, CG7 */ + kCLOCK_Adc1 = (1U << 8U) | CCM_CCGR1_CG8_SHIFT, /*!< CCGR1, CG8 */ + kCLOCK_SemcExsc = (1U << 8U) | CCM_CCGR1_CG9_SHIFT, /*!< CCGR1, CG9 */ + kCLOCK_Gpt1 = (1U << 8U) | CCM_CCGR1_CG10_SHIFT, /*!< CCGR1, CG10 */ + kCLOCK_Gpt1S = (1U << 8U) | CCM_CCGR1_CG11_SHIFT, /*!< CCGR1, CG11 */ + kCLOCK_Lpuart4 = (1U << 8U) | CCM_CCGR1_CG12_SHIFT, /*!< CCGR1, CG12 */ + kCLOCK_Gpio1 = (1U << 8U) | CCM_CCGR1_CG13_SHIFT, /*!< CCGR1, CG13 */ + kCLOCK_Csu = (1U << 8U) | CCM_CCGR1_CG14_SHIFT, /*!< CCGR1, CG14 */ + kCLOCK_Gpio5 = (1U << 8U) | CCM_CCGR1_CG15_SHIFT, /*!< CCGR1, CG15 */ /* CCM CCGR2 */ - /*!< CCGR2, CG0, Reserved */ - kCLOCK_Csi = (2U << 8U) | CCM_CCGR2_CG1_SHIFT, /*!< CCGR2, CG1 */ - kCLOCK_IomuxcSnvs = (2U << 8U) | CCM_CCGR2_CG2_SHIFT, /*!< CCGR2, CG2 */ - kCLOCK_Lpi2c1 = (2U << 8U) | CCM_CCGR2_CG3_SHIFT, /*!< CCGR2, CG3 */ - kCLOCK_Lpi2c2 = (2U << 8U) | CCM_CCGR2_CG4_SHIFT, /*!< CCGR2, CG4 */ - kCLOCK_Lpi2c3 = (2U << 8U) | CCM_CCGR2_CG5_SHIFT, /*!< CCGR2, CG5 */ - kCLOCK_Ocotp = (2U << 8U) | CCM_CCGR2_CG6_SHIFT, /*!< CCGR2, CG6 */ - kCLOCK_Xbar3 = (2U << 8U) | CCM_CCGR2_CG7_SHIFT, /*!< CCGR2, CG7 */ - kCLOCK_Ipmux1 = (2U << 8U) | CCM_CCGR2_CG8_SHIFT, /*!< CCGR2, CG8 */ - kCLOCK_Ipmux2 = (2U << 8U) | CCM_CCGR2_CG9_SHIFT, /*!< CCGR2, CG9 */ - kCLOCK_Ipmux3 = (2U << 8U) | CCM_CCGR2_CG10_SHIFT, /*!< CCGR2, CG10 */ - kCLOCK_Xbar1 = (2U << 8U) | CCM_CCGR2_CG11_SHIFT, /*!< CCGR2, CG11 */ - kCLOCK_Xbar2 = (2U << 8U) | CCM_CCGR2_CG12_SHIFT, /*!< CCGR2, CG12 */ - kCLOCK_Gpio3 = (2U << 8U) | CCM_CCGR2_CG13_SHIFT, /*!< CCGR2, CG13 */ - kCLOCK_Lcd = (2U << 8U) | CCM_CCGR2_CG14_SHIFT, /*!< CCGR2, CG14 */ - kCLOCK_Pxp = (2U << 8U) | CCM_CCGR2_CG15_SHIFT, /*!< CCGR2, CG15 */ + kCLOCK_OcramExsc = (2U << 8U) | CCM_CCGR2_CG0_SHIFT, /*!< CCGR2, CG0 */ + kCLOCK_Csi = (2U << 8U) | CCM_CCGR2_CG1_SHIFT, /*!< CCGR2, CG1 */ + kCLOCK_IomuxcSnvs = (2U << 8U) | CCM_CCGR2_CG2_SHIFT, /*!< CCGR2, CG2 */ + kCLOCK_Lpi2c1 = (2U << 8U) | CCM_CCGR2_CG3_SHIFT, /*!< CCGR2, CG3 */ + kCLOCK_Lpi2c2 = (2U << 8U) | CCM_CCGR2_CG4_SHIFT, /*!< CCGR2, CG4 */ + kCLOCK_Lpi2c3 = (2U << 8U) | CCM_CCGR2_CG5_SHIFT, /*!< CCGR2, CG5 */ + kCLOCK_Ocotp = (2U << 8U) | CCM_CCGR2_CG6_SHIFT, /*!< CCGR2, CG6 */ + kCLOCK_Xbar3 = (2U << 8U) | CCM_CCGR2_CG7_SHIFT, /*!< CCGR2, CG7 */ + kCLOCK_Ipmux1 = (2U << 8U) | CCM_CCGR2_CG8_SHIFT, /*!< CCGR2, CG8 */ + kCLOCK_Ipmux2 = (2U << 8U) | CCM_CCGR2_CG9_SHIFT, /*!< CCGR2, CG9 */ + kCLOCK_Ipmux3 = (2U << 8U) | CCM_CCGR2_CG10_SHIFT, /*!< CCGR2, CG10 */ + kCLOCK_Xbar1 = (2U << 8U) | CCM_CCGR2_CG11_SHIFT, /*!< CCGR2, CG11 */ + kCLOCK_Xbar2 = (2U << 8U) | CCM_CCGR2_CG12_SHIFT, /*!< CCGR2, CG12 */ + kCLOCK_Gpio3 = (2U << 8U) | CCM_CCGR2_CG13_SHIFT, /*!< CCGR2, CG13 */ + kCLOCK_Lcd = (2U << 8U) | CCM_CCGR2_CG14_SHIFT, /*!< CCGR2, CG14 */ + kCLOCK_Pxp = (2U << 8U) | CCM_CCGR2_CG15_SHIFT, /*!< CCGR2, CG15 */ /* CCM CCGR3 */ - kCLOCK_Flexio2 = (3U << 8U) | CCM_CCGR3_CG0_SHIFT, /*!< CCGR3, CG0 */ - kCLOCK_Lpuart5 = (3U << 8U) | CCM_CCGR3_CG1_SHIFT, /*!< CCGR3, CG1 */ - kCLOCK_Semc = (3U << 8U) | CCM_CCGR3_CG2_SHIFT, /*!< CCGR3, CG2 */ - kCLOCK_Lpuart6 = (3U << 8U) | CCM_CCGR3_CG3_SHIFT, /*!< CCGR3, CG3 */ - kCLOCK_Aoi1 = (3U << 8U) | CCM_CCGR3_CG4_SHIFT, /*!< CCGR3, CG4 */ - kCLOCK_LcdPixel = (3U << 8U) | CCM_CCGR3_CG5_SHIFT, /*!< CCGR3, CG5 */ - kCLOCK_Gpio4 = (3U << 8U) | CCM_CCGR3_CG6_SHIFT, /*!< CCGR3, CG6 */ - kCLOCK_Ewm0 = (3U << 8U) | CCM_CCGR3_CG7_SHIFT, /*!< CCGR3, CG7 */ - kCLOCK_Wdog1 = (3U << 8U) | CCM_CCGR3_CG8_SHIFT, /*!< CCGR3, CG8 */ - kCLOCK_FlexRam = (3U << 8U) | CCM_CCGR3_CG9_SHIFT, /*!< CCGR3, CG9 */ - kCLOCK_Acmp1 = (3U << 8U) | CCM_CCGR3_CG10_SHIFT, /*!< CCGR3, CG10 */ - kCLOCK_Acmp2 = (3U << 8U) | CCM_CCGR3_CG11_SHIFT, /*!< CCGR3, CG11 */ - kCLOCK_Acmp3 = (3U << 8U) | CCM_CCGR3_CG12_SHIFT, /*!< CCGR3, CG12 */ - kCLOCK_Acmp4 = (3U << 8U) | CCM_CCGR3_CG13_SHIFT, /*!< CCGR3, CG13 */ - kCLOCK_Ocram = (3U << 8U) | CCM_CCGR3_CG14_SHIFT, /*!< CCGR3, CG14 */ - kCLOCK_IomuxcSnvsGpr = (3U << 8U) | CCM_CCGR3_CG15_SHIFT, /*!< CCGR3, CG15 */ + kCLOCK_Flexio2 = (3U << 8U) | CCM_CCGR3_CG0_SHIFT, /*!< CCGR3, CG0 */ + kCLOCK_Lpuart5 = (3U << 8U) | CCM_CCGR3_CG1_SHIFT, /*!< CCGR3, CG1 */ + kCLOCK_Semc = (3U << 8U) | CCM_CCGR3_CG2_SHIFT, /*!< CCGR3, CG2 */ + kCLOCK_Lpuart6 = (3U << 8U) | CCM_CCGR3_CG3_SHIFT, /*!< CCGR3, CG3 */ + kCLOCK_Aoi1 = (3U << 8U) | CCM_CCGR3_CG4_SHIFT, /*!< CCGR3, CG4 */ + kCLOCK_LcdPixel = (3U << 8U) | CCM_CCGR3_CG5_SHIFT, /*!< CCGR3, CG5 */ + kCLOCK_Gpio4 = (3U << 8U) | CCM_CCGR3_CG6_SHIFT, /*!< CCGR3, CG6 */ + kCLOCK_Ewm0 = (3U << 8U) | CCM_CCGR3_CG7_SHIFT, /*!< CCGR3, CG7 */ + kCLOCK_Wdog1 = (3U << 8U) | CCM_CCGR3_CG8_SHIFT, /*!< CCGR3, CG8 */ + kCLOCK_FlexRam = (3U << 8U) | CCM_CCGR3_CG9_SHIFT, /*!< CCGR3, CG9 */ + kCLOCK_Acmp1 = (3U << 8U) | CCM_CCGR3_CG10_SHIFT, /*!< CCGR3, CG10 */ + kCLOCK_Acmp2 = (3U << 8U) | CCM_CCGR3_CG11_SHIFT, /*!< CCGR3, CG11 */ + kCLOCK_Acmp3 = (3U << 8U) | CCM_CCGR3_CG12_SHIFT, /*!< CCGR3, CG12 */ + kCLOCK_Acmp4 = (3U << 8U) | CCM_CCGR3_CG13_SHIFT, /*!< CCGR3, CG13 */ + kCLOCK_Ocram = (3U << 8U) | CCM_CCGR3_CG14_SHIFT, /*!< CCGR3, CG14 */ + kCLOCK_IomuxcSnvsGpr = (3U << 8U) | CCM_CCGR3_CG15_SHIFT, /*!< CCGR3, CG15 */ /* CCM CCGR4 */ - kCLOCK_Iomuxc = (4U << 8U) | CCM_CCGR4_CG1_SHIFT, /*!< CCGR4, CG1 */ - kCLOCK_IomuxcGpr = (4U << 8U) | CCM_CCGR4_CG2_SHIFT, /*!< CCGR4, CG2 */ - kCLOCK_Bee = (4U << 8U) | CCM_CCGR4_CG3_SHIFT, /*!< CCGR4, CG3 */ - kCLOCK_SimM7 = (4U << 8U) | CCM_CCGR4_CG4_SHIFT, /*!< CCGR4, CG4 */ - kCLOCK_Tsc = (4U << 8U) | CCM_CCGR4_CG5_SHIFT, /*!< CCGR4, CG5 */ - kCLOCK_SimM = (4U << 8U) | CCM_CCGR4_CG6_SHIFT, /*!< CCGR4, CG6 */ - kCLOCK_SimEms = (4U << 8U) | CCM_CCGR4_CG7_SHIFT, /*!< CCGR4, CG7 */ - kCLOCK_Pwm1 = (4U << 8U) | CCM_CCGR4_CG8_SHIFT, /*!< CCGR4, CG8 */ - kCLOCK_Pwm2 = (4U << 8U) | CCM_CCGR4_CG9_SHIFT, /*!< CCGR4, CG9 */ - kCLOCK_Pwm3 = (4U << 8U) | CCM_CCGR4_CG10_SHIFT, /*!< CCGR4, CG10 */ - kCLOCK_Pwm4 = (4U << 8U) | CCM_CCGR4_CG11_SHIFT, /*!< CCGR4, CG11 */ - kCLOCK_Enc1 = (4U << 8U) | CCM_CCGR4_CG12_SHIFT, /*!< CCGR4, CG12 */ - kCLOCK_Enc2 = (4U << 8U) | CCM_CCGR4_CG13_SHIFT, /*!< CCGR4, CG13 */ - kCLOCK_Enc3 = (4U << 8U) | CCM_CCGR4_CG14_SHIFT, /*!< CCGR4, CG14 */ - kCLOCK_Enc4 = (4U << 8U) | CCM_CCGR4_CG15_SHIFT, /*!< CCGR4, CG15 */ + kCLOCK_Iomuxc = (4U << 8U) | CCM_CCGR4_CG1_SHIFT, /*!< CCGR4, CG1 */ + kCLOCK_IomuxcGpr = (4U << 8U) | CCM_CCGR4_CG2_SHIFT, /*!< CCGR4, CG2 */ + kCLOCK_Bee = (4U << 8U) | CCM_CCGR4_CG3_SHIFT, /*!< CCGR4, CG3 */ + kCLOCK_SimM7 = (4U << 8U) | CCM_CCGR4_CG4_SHIFT, /*!< CCGR4, CG4 */ + kCLOCK_Tsc = (4U << 8U) | CCM_CCGR4_CG5_SHIFT, /*!< CCGR4, CG5 */ + kCLOCK_SimM = (4U << 8U) | CCM_CCGR4_CG6_SHIFT, /*!< CCGR4, CG6 */ + kCLOCK_SimEms = (4U << 8U) | CCM_CCGR4_CG7_SHIFT, /*!< CCGR4, CG7 */ + kCLOCK_Pwm1 = (4U << 8U) | CCM_CCGR4_CG8_SHIFT, /*!< CCGR4, CG8 */ + kCLOCK_Pwm2 = (4U << 8U) | CCM_CCGR4_CG9_SHIFT, /*!< CCGR4, CG9 */ + kCLOCK_Pwm3 = (4U << 8U) | CCM_CCGR4_CG10_SHIFT, /*!< CCGR4, CG10 */ + kCLOCK_Pwm4 = (4U << 8U) | CCM_CCGR4_CG11_SHIFT, /*!< CCGR4, CG11 */ + kCLOCK_Enc1 = (4U << 8U) | CCM_CCGR4_CG12_SHIFT, /*!< CCGR4, CG12 */ + kCLOCK_Enc2 = (4U << 8U) | CCM_CCGR4_CG13_SHIFT, /*!< CCGR4, CG13 */ + kCLOCK_Enc3 = (4U << 8U) | CCM_CCGR4_CG14_SHIFT, /*!< CCGR4, CG14 */ + kCLOCK_Enc4 = (4U << 8U) | CCM_CCGR4_CG15_SHIFT, /*!< CCGR4, CG15 */ /* CCM CCGR5 */ - kCLOCK_Rom = (5U << 8U) | CCM_CCGR5_CG0_SHIFT, /*!< CCGR5, CG0 */ - kCLOCK_Flexio1 = (5U << 8U) | CCM_CCGR5_CG1_SHIFT, /*!< CCGR5, CG1 */ - kCLOCK_Wdog3 = (5U << 8U) | CCM_CCGR5_CG2_SHIFT, /*!< CCGR5, CG2 */ - kCLOCK_Dma = (5U << 8U) | CCM_CCGR5_CG3_SHIFT, /*!< CCGR5, CG3 */ - kCLOCK_Kpp = (5U << 8U) | CCM_CCGR5_CG4_SHIFT, /*!< CCGR5, CG4 */ - kCLOCK_Wdog2 = (5U << 8U) | CCM_CCGR5_CG5_SHIFT, /*!< CCGR5, CG5 */ - kCLOCK_Aips_tz4 = (5U << 8U) | CCM_CCGR5_CG6_SHIFT, /*!< CCGR5, CG6 */ - kCLOCK_Spdif = (5U << 8U) | CCM_CCGR5_CG7_SHIFT, /*!< CCGR5, CG7 */ - kCLOCK_SimMain = (5U << 8U) | CCM_CCGR5_CG8_SHIFT, /*!< CCGR5, CG8 */ - kCLOCK_Sai1 = (5U << 8U) | CCM_CCGR5_CG9_SHIFT, /*!< CCGR5, CG9 */ - kCLOCK_Sai2 = (5U << 8U) | CCM_CCGR5_CG10_SHIFT, /*!< CCGR5, CG10 */ - kCLOCK_Sai3 = (5U << 8U) | CCM_CCGR5_CG11_SHIFT, /*!< CCGR5, CG11 */ - kCLOCK_Lpuart1 = (5U << 8U) | CCM_CCGR5_CG12_SHIFT, /*!< CCGR5, CG12 */ - kCLOCK_Lpuart7 = (5U << 8U) | CCM_CCGR5_CG13_SHIFT, /*!< CCGR5, CG13 */ - kCLOCK_SnvsHp = (5U << 8U) | CCM_CCGR5_CG14_SHIFT, /*!< CCGR5, CG14 */ - kCLOCK_SnvsLp = (5U << 8U) | CCM_CCGR5_CG15_SHIFT, /*!< CCGR5, CG15 */ + kCLOCK_Rom = (5U << 8U) | CCM_CCGR5_CG0_SHIFT, /*!< CCGR5, CG0 */ + kCLOCK_Flexio1 = (5U << 8U) | CCM_CCGR5_CG1_SHIFT, /*!< CCGR5, CG1 */ + kCLOCK_Wdog3 = (5U << 8U) | CCM_CCGR5_CG2_SHIFT, /*!< CCGR5, CG2 */ + kCLOCK_Dma = (5U << 8U) | CCM_CCGR5_CG3_SHIFT, /*!< CCGR5, CG3 */ + kCLOCK_Kpp = (5U << 8U) | CCM_CCGR5_CG4_SHIFT, /*!< CCGR5, CG4 */ + kCLOCK_Wdog2 = (5U << 8U) | CCM_CCGR5_CG5_SHIFT, /*!< CCGR5, CG5 */ + kCLOCK_Aips_tz4 = (5U << 8U) | CCM_CCGR5_CG6_SHIFT, /*!< CCGR5, CG6 */ + kCLOCK_Spdif = (5U << 8U) | CCM_CCGR5_CG7_SHIFT, /*!< CCGR5, CG7 */ + kCLOCK_SimMain = (5U << 8U) | CCM_CCGR5_CG8_SHIFT, /*!< CCGR5, CG8 */ + kCLOCK_Sai1 = (5U << 8U) | CCM_CCGR5_CG9_SHIFT, /*!< CCGR5, CG9 */ + kCLOCK_Sai2 = (5U << 8U) | CCM_CCGR5_CG10_SHIFT, /*!< CCGR5, CG10 */ + kCLOCK_Sai3 = (5U << 8U) | CCM_CCGR5_CG11_SHIFT, /*!< CCGR5, CG11 */ + kCLOCK_Lpuart1 = (5U << 8U) | CCM_CCGR5_CG12_SHIFT, /*!< CCGR5, CG12 */ + kCLOCK_Lpuart7 = (5U << 8U) | CCM_CCGR5_CG13_SHIFT, /*!< CCGR5, CG13 */ + kCLOCK_SnvsHp = (5U << 8U) | CCM_CCGR5_CG14_SHIFT, /*!< CCGR5, CG14 */ + kCLOCK_SnvsLp = (5U << 8U) | CCM_CCGR5_CG15_SHIFT, /*!< CCGR5, CG15 */ /* CCM CCGR6 */ - kCLOCK_UsbOh3 = (6U << 8U) | CCM_CCGR6_CG0_SHIFT, /*!< CCGR6, CG0 */ - kCLOCK_Usdhc1 = (6U << 8U) | CCM_CCGR6_CG1_SHIFT, /*!< CCGR6, CG1 */ - kCLOCK_Usdhc2 = (6U << 8U) | CCM_CCGR6_CG2_SHIFT, /*!< CCGR6, CG2 */ - kCLOCK_Dcdc = (6U << 8U) | CCM_CCGR6_CG3_SHIFT, /*!< CCGR6, CG3 */ - kCLOCK_Ipmux4 = (6U << 8U) | CCM_CCGR6_CG4_SHIFT, /*!< CCGR6, CG4 */ - kCLOCK_FlexSpi = (6U << 8U) | CCM_CCGR6_CG5_SHIFT, /*!< CCGR6, CG5 */ - kCLOCK_Trng = (6U << 8U) | CCM_CCGR6_CG6_SHIFT, /*!< CCGR6, CG6 */ - kCLOCK_Lpuart8 = (6U << 8U) | CCM_CCGR6_CG7_SHIFT, /*!< CCGR6, CG7 */ - kCLOCK_Timer4 = (6U << 8U) | CCM_CCGR6_CG8_SHIFT, /*!< CCGR6, CG8 */ - kCLOCK_Aips_tz3 = (6U << 8U) | CCM_CCGR6_CG9_SHIFT, /*!< CCGR6, CG9 */ - kCLOCK_SimPer = (6U << 8U) | CCM_CCGR6_CG10_SHIFT, /*!< CCGR6, CG10 */ - kCLOCK_Anadig = (6U << 8U) | CCM_CCGR6_CG11_SHIFT, /*!< CCGR6, CG11 */ - kCLOCK_Lpi2c4 = (6U << 8U) | CCM_CCGR6_CG12_SHIFT, /*!< CCGR6, CG12 */ - kCLOCK_Timer1 = (6U << 8U) | CCM_CCGR6_CG13_SHIFT, /*!< CCGR6, CG13 */ - kCLOCK_Timer2 = (6U << 8U) | CCM_CCGR6_CG14_SHIFT, /*!< CCGR6, CG14 */ - kCLOCK_Timer3 = (6U << 8U) | CCM_CCGR6_CG15_SHIFT, /*!< CCGR6, CG15 */ + kCLOCK_UsbOh3 = (6U << 8U) | CCM_CCGR6_CG0_SHIFT, /*!< CCGR6, CG0 */ + kCLOCK_Usdhc1 = (6U << 8U) | CCM_CCGR6_CG1_SHIFT, /*!< CCGR6, CG1 */ + kCLOCK_Usdhc2 = (6U << 8U) | CCM_CCGR6_CG2_SHIFT, /*!< CCGR6, CG2 */ + kCLOCK_Dcdc = (6U << 8U) | CCM_CCGR6_CG3_SHIFT, /*!< CCGR6, CG3 */ + kCLOCK_Ipmux4 = (6U << 8U) | CCM_CCGR6_CG4_SHIFT, /*!< CCGR6, CG4 */ + kCLOCK_FlexSpi = (6U << 8U) | CCM_CCGR6_CG5_SHIFT, /*!< CCGR6, CG5 */ + kCLOCK_Trng = (6U << 8U) | CCM_CCGR6_CG6_SHIFT, /*!< CCGR6, CG6 */ + kCLOCK_Lpuart8 = (6U << 8U) | CCM_CCGR6_CG7_SHIFT, /*!< CCGR6, CG7 */ + kCLOCK_Timer4 = (6U << 8U) | CCM_CCGR6_CG8_SHIFT, /*!< CCGR6, CG8 */ + kCLOCK_Aips_tz3 = (6U << 8U) | CCM_CCGR6_CG9_SHIFT, /*!< CCGR6, CG9 */ + kCLOCK_SimPer = (6U << 8U) | CCM_CCGR6_CG10_SHIFT, /*!< CCGR6, CG10 */ + kCLOCK_Anadig = (6U << 8U) | CCM_CCGR6_CG11_SHIFT, /*!< CCGR6, CG11 */ + kCLOCK_Lpi2c4 = (6U << 8U) | CCM_CCGR6_CG12_SHIFT, /*!< CCGR6, CG12 */ + kCLOCK_Timer1 = (6U << 8U) | CCM_CCGR6_CG13_SHIFT, /*!< CCGR6, CG13 */ + kCLOCK_Timer2 = (6U << 8U) | CCM_CCGR6_CG14_SHIFT, /*!< CCGR6, CG14 */ + kCLOCK_Timer3 = (6U << 8U) | CCM_CCGR6_CG15_SHIFT, /*!< CCGR6, CG15 */ } clock_ip_name_t; /*! @brief OSC 24M sorce select */ typedef enum _clock_osc { - kCLOCK_RcOsc = 0U, /*!< On chip OSC. */ - kCLOCK_XtalOsc = 1U, /*!< 24M Xtal OSC */ + kCLOCK_RcOsc = 0U, /*!< On chip OSC. */ + kCLOCK_XtalOsc = 1U, /*!< 24M Xtal OSC */ } clock_osc_t; /*! @brief Clock gate value */ typedef enum _clock_gate_value { - kCLOCK_ClockNotNeeded = 0U, /*!< Clock is off during all modes. */ - kCLOCK_ClockNeededRun = 1U, /*!< Clock is on in run mode, but off in WAIT and STOP modes */ - kCLOCK_ClockNeededRunWait = 3U, /*!< Clock is on during all modes, except STOP mode */ + kCLOCK_ClockNotNeeded = 0U, /*!< Clock is off during all modes. */ + kCLOCK_ClockNeededRun = 1U, /*!< Clock is on in run mode, but off in WAIT and STOP modes */ + kCLOCK_ClockNeededRunWait = 3U, /*!< Clock is on during all modes, except STOP mode */ } clock_gate_value_t; /*! @brief System clock mode */ typedef enum _clock_mode_t { - kCLOCK_ModeRun = 0U, /*!< Remain in run mode. */ - kCLOCK_ModeWait = 1U, /*!< Transfer to wait mode. */ - kCLOCK_ModeStop = 2U, /*!< Transfer to stop mode. */ + kCLOCK_ModeRun = 0U, /*!< Remain in run mode. */ + kCLOCK_ModeWait = 1U, /*!< Transfer to wait mode. */ + kCLOCK_ModeStop = 2U, /*!< Transfer to stop mode. */ } clock_mode_t; - /*! * @brief MUX control names for clock mux setting. * @@ -572,41 +566,86 @@ typedef enum _clock_mode_t */ typedef enum _clock_mux { - kCLOCK_Pll3SwMux = CCM_TUPLE(CCSR, CCM_CCSR_PLL3_SW_CLK_SEL_SHIFT, CCM_CCSR_PLL3_SW_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), /*!< pll3_sw_clk mux name */ + kCLOCK_Pll3SwMux = CCM_TUPLE(CCSR, + CCM_CCSR_PLL3_SW_CLK_SEL_SHIFT, + CCM_CCSR_PLL3_SW_CLK_SEL_MASK, + CCM_NO_BUSY_WAIT), /*!< pll3_sw_clk mux name */ - kCLOCK_PeriphMux = CCM_TUPLE(CBCDR, CCM_CBCDR_PERIPH_CLK_SEL_SHIFT, CCM_CBCDR_PERIPH_CLK_SEL_MASK, CCM_CDHIPR_PERIPH_CLK_SEL_BUSY_SHIFT), /*!< periph mux name */ - kCLOCK_SemcAltMux = CCM_TUPLE(CBCDR, CCM_CBCDR_SEMC_ALT_CLK_SEL_SHIFT, CCM_CBCDR_SEMC_ALT_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), /*!< semc mux name */ - kCLOCK_SemcMux = CCM_TUPLE(CBCDR, CCM_CBCDR_SEMC_CLK_SEL_SHIFT, CCM_CBCDR_SEMC_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), /*!< semc mux name */ - - kCLOCK_PrePeriphMux = CCM_TUPLE(CBCMR, CCM_CBCMR_PRE_PERIPH_CLK_SEL_SHIFT, CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), /*!< pre-periph mux name */ - kCLOCK_TraceMux = CCM_TUPLE(CBCMR, CCM_CBCMR_TRACE_CLK_SEL_SHIFT, CCM_CBCMR_TRACE_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), /*!< trace mux name */ - kCLOCK_PeriphClk2Mux = CCM_TUPLE(CBCMR, CCM_CBCMR_PERIPH_CLK2_SEL_SHIFT, CCM_CBCMR_PERIPH_CLK2_SEL_MASK, CCM_NO_BUSY_WAIT), /*!< periph clock2 mux name */ - kCLOCK_LpspiMux = CCM_TUPLE(CBCMR, CCM_CBCMR_LPSPI_CLK_SEL_SHIFT, CCM_CBCMR_LPSPI_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), /*!< lpspi mux name */ + kCLOCK_PeriphMux = CCM_TUPLE(CBCDR, + CCM_CBCDR_PERIPH_CLK_SEL_SHIFT, + CCM_CBCDR_PERIPH_CLK_SEL_MASK, + CCM_CDHIPR_PERIPH_CLK_SEL_BUSY_SHIFT), /*!< periph mux name */ + kCLOCK_SemcAltMux = CCM_TUPLE(CBCDR, + CCM_CBCDR_SEMC_ALT_CLK_SEL_SHIFT, + CCM_CBCDR_SEMC_ALT_CLK_SEL_MASK, + CCM_NO_BUSY_WAIT), /*!< semc mux name */ + kCLOCK_SemcMux = CCM_TUPLE( + CBCDR, CCM_CBCDR_SEMC_CLK_SEL_SHIFT, CCM_CBCDR_SEMC_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), /*!< semc mux name */ - kCLOCK_FlexspiMux = CCM_TUPLE(CSCMR1, CCM_CSCMR1_FLEXSPI_CLK_SEL_SHIFT, CCM_CSCMR1_FLEXSPI_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), /*!< flexspi mux name */ - kCLOCK_Usdhc2Mux = CCM_TUPLE(CSCMR1, CCM_CSCMR1_USDHC2_CLK_SEL_SHIFT, CCM_CSCMR1_USDHC2_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), /*!< usdhc2 mux name */ - kCLOCK_Usdhc1Mux = CCM_TUPLE(CSCMR1, CCM_CSCMR1_USDHC1_CLK_SEL_SHIFT, CCM_CSCMR1_USDHC1_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), /*!< usdhc1 mux name */ - kCLOCK_Sai3Mux = CCM_TUPLE(CSCMR1, CCM_CSCMR1_SAI3_CLK_SEL_SHIFT, CCM_CSCMR1_SAI3_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), /*!< sai3 mux name */ - kCLOCK_Sai2Mux = CCM_TUPLE(CSCMR1, CCM_CSCMR1_SAI2_CLK_SEL_SHIFT, CCM_CSCMR1_SAI2_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), /*!< sai2 mux name */ - kCLOCK_Sai1Mux = CCM_TUPLE(CSCMR1, CCM_CSCMR1_SAI1_CLK_SEL_SHIFT, CCM_CSCMR1_SAI1_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), /*!< sai1 mux name */ - kCLOCK_PerclkMux = CCM_TUPLE(CSCMR1, CCM_CSCMR1_PERCLK_CLK_SEL_SHIFT, CCM_CSCMR1_PERCLK_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), /*!< perclk mux name */ + kCLOCK_PrePeriphMux = CCM_TUPLE(CBCMR, + CCM_CBCMR_PRE_PERIPH_CLK_SEL_SHIFT, + CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK, + CCM_NO_BUSY_WAIT), /*!< pre-periph mux name */ + kCLOCK_TraceMux = CCM_TUPLE( + CBCMR, CCM_CBCMR_TRACE_CLK_SEL_SHIFT, CCM_CBCMR_TRACE_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), /*!< trace mux name */ + kCLOCK_PeriphClk2Mux = CCM_TUPLE(CBCMR, + CCM_CBCMR_PERIPH_CLK2_SEL_SHIFT, + CCM_CBCMR_PERIPH_CLK2_SEL_MASK, + CCM_NO_BUSY_WAIT), /*!< periph clock2 mux name */ + kCLOCK_LpspiMux = CCM_TUPLE( + CBCMR, CCM_CBCMR_LPSPI_CLK_SEL_SHIFT, CCM_CBCMR_LPSPI_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), /*!< lpspi mux name */ - kCLOCK_Flexio2Mux = CCM_TUPLE(CSCMR2, CCM_CSCMR2_FLEXIO2_CLK_SEL_SHIFT, CCM_CSCMR2_FLEXIO2_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), /*!< flexio2 mux name */ - kCLOCK_CanMux = CCM_TUPLE(CSCMR2, CCM_CSCMR2_CAN_CLK_SEL_SHIFT, CCM_CSCMR2_CAN_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), /*!< can mux name */ + kCLOCK_FlexspiMux = CCM_TUPLE(CSCMR1, + CCM_CSCMR1_FLEXSPI_CLK_SEL_SHIFT, + CCM_CSCMR1_FLEXSPI_CLK_SEL_MASK, + CCM_NO_BUSY_WAIT), /*!< flexspi mux name */ + kCLOCK_Usdhc2Mux = CCM_TUPLE(CSCMR1, + CCM_CSCMR1_USDHC2_CLK_SEL_SHIFT, + CCM_CSCMR1_USDHC2_CLK_SEL_MASK, + CCM_NO_BUSY_WAIT), /*!< usdhc2 mux name */ + kCLOCK_Usdhc1Mux = CCM_TUPLE(CSCMR1, + CCM_CSCMR1_USDHC1_CLK_SEL_SHIFT, + CCM_CSCMR1_USDHC1_CLK_SEL_MASK, + CCM_NO_BUSY_WAIT), /*!< usdhc1 mux name */ + kCLOCK_Sai3Mux = CCM_TUPLE( + CSCMR1, CCM_CSCMR1_SAI3_CLK_SEL_SHIFT, CCM_CSCMR1_SAI3_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), /*!< sai3 mux name */ + kCLOCK_Sai2Mux = CCM_TUPLE( + CSCMR1, CCM_CSCMR1_SAI2_CLK_SEL_SHIFT, CCM_CSCMR1_SAI2_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), /*!< sai2 mux name */ + kCLOCK_Sai1Mux = CCM_TUPLE( + CSCMR1, CCM_CSCMR1_SAI1_CLK_SEL_SHIFT, CCM_CSCMR1_SAI1_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), /*!< sai1 mux name */ + kCLOCK_PerclkMux = CCM_TUPLE(CSCMR1, + CCM_CSCMR1_PERCLK_CLK_SEL_SHIFT, + CCM_CSCMR1_PERCLK_CLK_SEL_MASK, + CCM_NO_BUSY_WAIT), /*!< perclk mux name */ - kCLOCK_UartMux = CCM_TUPLE(CSCDR1, CCM_CSCDR1_UART_CLK_SEL_SHIFT, CCM_CSCDR1_UART_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), /*!< uart mux name */ - - kCLOCK_SpdifMux = CCM_TUPLE(CDCDR, CCM_CDCDR_SPDIF0_CLK_SEL_SHIFT, CCM_CDCDR_SPDIF0_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), /*!< spdif mux name */ - kCLOCK_Flexio1Mux = CCM_TUPLE(CDCDR, CCM_CDCDR_FLEXIO1_CLK_SEL_SHIFT, CCM_CDCDR_FLEXIO1_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), /*!< flexio1 mux name */ + kCLOCK_Flexio2Mux = CCM_TUPLE(CSCMR2, + CCM_CSCMR2_FLEXIO2_CLK_SEL_SHIFT, + CCM_CSCMR2_FLEXIO2_CLK_SEL_MASK, + CCM_NO_BUSY_WAIT), /*!< flexio2 mux name */ + kCLOCK_CanMux = CCM_TUPLE( + CSCMR2, CCM_CSCMR2_CAN_CLK_SEL_SHIFT, CCM_CSCMR2_CAN_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), /*!< can mux name */ - kCLOCK_Lpi2cMux = CCM_TUPLE(CSCDR2, CCM_CSCDR2_LPI2C_CLK_SEL_SHIFT, CCM_CSCDR2_LPI2C_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), /*!< lpi2c mux name */ - kCLOCK_Lcdif1PreMux = CCM_TUPLE(CSCDR2, CCM_CSCDR2_LCDIF_PRE_CLK_SEL_SHIFT, CCM_CSCDR2_LCDIF_PRE_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), /*!< lcdif1 pre mux name */ - kCLOCK_Lcdif1Mux = CCM_TUPLE(CSCDR2, CCM_CSCDR2_LCDIF_CLK_SEL_SHIFT, CCM_CSCDR2_LCDIF_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), /*!< lcdif1 mux name */ + kCLOCK_UartMux = CCM_TUPLE( + CSCDR1, CCM_CSCDR1_UART_CLK_SEL_SHIFT, CCM_CSCDR1_UART_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), /*!< uart mux name */ - kCLOCK_CsiMux = CCM_TUPLE(CSCDR3, CCM_CSCDR3_CSI_CLK_SEL_SHIFT, CCM_CSCDR3_CSI_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), /*!< csi mux name */ + kCLOCK_SpdifMux = CCM_TUPLE( + CDCDR, CCM_CDCDR_SPDIF0_CLK_SEL_SHIFT, CCM_CDCDR_SPDIF0_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), /*!< spdif mux name */ + kCLOCK_Flexio1Mux = CCM_TUPLE(CDCDR, + CCM_CDCDR_FLEXIO1_CLK_SEL_SHIFT, + CCM_CDCDR_FLEXIO1_CLK_SEL_MASK, + CCM_NO_BUSY_WAIT), /*!< flexio1 mux name */ + + kCLOCK_Lpi2cMux = CCM_TUPLE( + CSCDR2, CCM_CSCDR2_LPI2C_CLK_SEL_SHIFT, CCM_CSCDR2_LPI2C_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), /*!< lpi2c mux name */ + kCLOCK_LcdifPreMux = CCM_TUPLE(CSCDR2, + CCM_CSCDR2_LCDIF_PRE_CLK_SEL_SHIFT, + CCM_CSCDR2_LCDIF_PRE_CLK_SEL_MASK, + CCM_NO_BUSY_WAIT), /*!< lcdif pre mux name */ + + kCLOCK_CsiMux = CCM_TUPLE( + CSCDR3, CCM_CSCDR3_CSI_CLK_SEL_SHIFT, CCM_CSCDR3_CSI_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), /*!< csi mux name */ } clock_mux_t; - /*! * @brief DIV control names for clock div setting. * @@ -617,146 +656,215 @@ typedef enum _clock_mux */ typedef enum _clock_div { - kCLOCK_ArmDiv = CCM_TUPLE(CACRR, CCM_CACRR_ARM_PODF_SHIFT, CCM_CACRR_ARM_PODF_MASK, CCM_CDHIPR_ARM_PODF_BUSY_SHIFT), /*!< core div name */ + kCLOCK_ArmDiv = CCM_TUPLE( + CACRR, CCM_CACRR_ARM_PODF_SHIFT, CCM_CACRR_ARM_PODF_MASK, CCM_CDHIPR_ARM_PODF_BUSY_SHIFT), /*!< core div name */ - kCLOCK_PeriphClk2Div = CCM_TUPLE(CBCDR, CCM_CBCDR_PERIPH_CLK2_PODF_SHIFT, CCM_CBCDR_PERIPH_CLK2_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< periph clock2 div name */ - kCLOCK_SemcDiv = CCM_TUPLE(CBCDR, CCM_CBCDR_SEMC_PODF_SHIFT, CCM_CBCDR_SEMC_PODF_MASK, CCM_CDHIPR_SEMC_PODF_BUSY_SHIFT), /*!< semc div name */ - kCLOCK_AhbDiv = CCM_TUPLE(CBCDR, CCM_CBCDR_AHB_PODF_SHIFT, CCM_CBCDR_AHB_PODF_MASK, CCM_CDHIPR_AHB_PODF_BUSY_SHIFT), /*!< ahb div name */ - kCLOCK_IpgDiv = CCM_TUPLE(CBCDR, CCM_CBCDR_IPG_PODF_SHIFT, CCM_CBCDR_IPG_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< ipg div name */ + kCLOCK_PeriphClk2Div = CCM_TUPLE(CBCDR, + CCM_CBCDR_PERIPH_CLK2_PODF_SHIFT, + CCM_CBCDR_PERIPH_CLK2_PODF_MASK, + CCM_NO_BUSY_WAIT), /*!< periph clock2 div name */ + kCLOCK_SemcDiv = CCM_TUPLE(CBCDR, + CCM_CBCDR_SEMC_PODF_SHIFT, + CCM_CBCDR_SEMC_PODF_MASK, + CCM_CDHIPR_SEMC_PODF_BUSY_SHIFT), /*!< semc div name */ + kCLOCK_AhbDiv = CCM_TUPLE( + CBCDR, CCM_CBCDR_AHB_PODF_SHIFT, CCM_CBCDR_AHB_PODF_MASK, CCM_CDHIPR_AHB_PODF_BUSY_SHIFT), /*!< ahb div name */ + kCLOCK_IpgDiv = + CCM_TUPLE(CBCDR, CCM_CBCDR_IPG_PODF_SHIFT, CCM_CBCDR_IPG_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< ipg div name */ - kCLOCK_LpspiDiv = CCM_TUPLE(CBCMR, CCM_CBCMR_LPSPI_PODF_SHIFT, CCM_CBCMR_LPSPI_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< lpspi div name */ - kCLOCK_Lcdif1Div = CCM_TUPLE(CBCMR, CCM_CBCMR_LCDIF_PODF_SHIFT, CCM_CBCMR_LCDIF_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< lcdif1 div name */ + kCLOCK_LpspiDiv = CCM_TUPLE( + CBCMR, CCM_CBCMR_LPSPI_PODF_SHIFT, CCM_CBCMR_LPSPI_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< lpspi div name */ + kCLOCK_LcdifDiv = CCM_TUPLE( + CBCMR, CCM_CBCMR_LCDIF_PODF_SHIFT, CCM_CBCMR_LCDIF_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< lcdif div name */ - kCLOCK_FlexspiDiv = CCM_TUPLE(CSCMR1, CCM_CSCMR1_FLEXSPI_PODF_SHIFT, CCM_CSCMR1_FLEXSPI_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< flexspi div name */ - kCLOCK_PerclkDiv = CCM_TUPLE(CSCMR1, CCM_CSCMR1_PERCLK_PODF_SHIFT, CCM_CSCMR1_PERCLK_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< perclk div name */ + kCLOCK_FlexspiDiv = CCM_TUPLE( + CSCMR1, CCM_CSCMR1_FLEXSPI_PODF_SHIFT, CCM_CSCMR1_FLEXSPI_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< flexspi div name */ + kCLOCK_PerclkDiv = CCM_TUPLE( + CSCMR1, CCM_CSCMR1_PERCLK_PODF_SHIFT, CCM_CSCMR1_PERCLK_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< perclk div name */ - kCLOCK_CanDiv = CCM_TUPLE(CSCMR2, CCM_CSCMR2_CAN_CLK_PODF_SHIFT, CCM_CSCMR2_CAN_CLK_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< can div name */ + kCLOCK_CanDiv = CCM_TUPLE( + CSCMR2, CCM_CSCMR2_CAN_CLK_PODF_SHIFT, CCM_CSCMR2_CAN_CLK_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< can div name */ - kCLOCK_TraceDiv = CCM_TUPLE(CSCDR1, CCM_CSCDR1_TRACE_PODF_SHIFT, CCM_CSCDR1_TRACE_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< trace div name */ - kCLOCK_Usdhc2Div = CCM_TUPLE(CSCDR1, CCM_CSCDR1_USDHC2_PODF_SHIFT, CCM_CSCDR1_USDHC2_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< usdhc2 div name */ - kCLOCK_Usdhc1Div = CCM_TUPLE(CSCDR1, CCM_CSCDR1_USDHC1_PODF_SHIFT, CCM_CSCDR1_USDHC1_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< usdhc1 div name */ - kCLOCK_UartDiv = CCM_TUPLE(CSCDR1, CCM_CSCDR1_UART_CLK_PODF_SHIFT, CCM_CSCDR1_UART_CLK_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< uart div name */ + kCLOCK_TraceDiv = CCM_TUPLE( + CSCDR1, CCM_CSCDR1_TRACE_PODF_SHIFT, CCM_CSCDR1_TRACE_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< trace div name */ + kCLOCK_Usdhc2Div = CCM_TUPLE( + CSCDR1, CCM_CSCDR1_USDHC2_PODF_SHIFT, CCM_CSCDR1_USDHC2_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< usdhc2 div name */ + kCLOCK_Usdhc1Div = CCM_TUPLE( + CSCDR1, CCM_CSCDR1_USDHC1_PODF_SHIFT, CCM_CSCDR1_USDHC1_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< usdhc1 div name */ + kCLOCK_UartDiv = CCM_TUPLE( + CSCDR1, CCM_CSCDR1_UART_CLK_PODF_SHIFT, CCM_CSCDR1_UART_CLK_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< uart div name */ - kCLOCK_Flexio2Div = CCM_TUPLE(CS1CDR, CCM_CS1CDR_FLEXIO2_CLK_PODF_SHIFT, CCM_CS1CDR_FLEXIO2_CLK_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< flexio2 pre div name */ - kCLOCK_Sai3PreDiv = CCM_TUPLE(CS1CDR, CCM_CS1CDR_SAI3_CLK_PRED_SHIFT, CCM_CS1CDR_SAI3_CLK_PRED_MASK, CCM_NO_BUSY_WAIT), /*!< sai3 pre div name */ - kCLOCK_Sai3Div = CCM_TUPLE(CS1CDR, CCM_CS1CDR_SAI3_CLK_PODF_SHIFT, CCM_CS1CDR_SAI3_CLK_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< sai3 div name */ - kCLOCK_Flexio2PreDiv = CCM_TUPLE(CS1CDR, CCM_CS1CDR_FLEXIO2_CLK_PRED_SHIFT, CCM_CS1CDR_FLEXIO2_CLK_PRED_MASK, CCM_NO_BUSY_WAIT), /*!< sai3 pre div name */ - kCLOCK_Sai1PreDiv = CCM_TUPLE(CS1CDR, CCM_CS1CDR_SAI1_CLK_PRED_SHIFT, CCM_CS1CDR_SAI1_CLK_PRED_MASK, CCM_NO_BUSY_WAIT), /*!< sai1 pre div name */ - kCLOCK_Sai1Div = CCM_TUPLE(CS1CDR, CCM_CS1CDR_SAI1_CLK_PODF_SHIFT, CCM_CS1CDR_SAI1_CLK_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< sai1 div name */ + kCLOCK_Flexio2Div = CCM_TUPLE(CS1CDR, + CCM_CS1CDR_FLEXIO2_CLK_PODF_SHIFT, + CCM_CS1CDR_FLEXIO2_CLK_PODF_MASK, + CCM_NO_BUSY_WAIT), /*!< flexio2 pre div name */ + kCLOCK_Sai3PreDiv = CCM_TUPLE(CS1CDR, + CCM_CS1CDR_SAI3_CLK_PRED_SHIFT, + CCM_CS1CDR_SAI3_CLK_PRED_MASK, + CCM_NO_BUSY_WAIT), /*!< sai3 pre div name */ + kCLOCK_Sai3Div = CCM_TUPLE( + CS1CDR, CCM_CS1CDR_SAI3_CLK_PODF_SHIFT, CCM_CS1CDR_SAI3_CLK_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< sai3 div name */ + kCLOCK_Flexio2PreDiv = CCM_TUPLE(CS1CDR, + CCM_CS1CDR_FLEXIO2_CLK_PRED_SHIFT, + CCM_CS1CDR_FLEXIO2_CLK_PRED_MASK, + CCM_NO_BUSY_WAIT), /*!< sai3 pre div name */ + kCLOCK_Sai1PreDiv = CCM_TUPLE(CS1CDR, + CCM_CS1CDR_SAI1_CLK_PRED_SHIFT, + CCM_CS1CDR_SAI1_CLK_PRED_MASK, + CCM_NO_BUSY_WAIT), /*!< sai1 pre div name */ + kCLOCK_Sai1Div = CCM_TUPLE( + CS1CDR, CCM_CS1CDR_SAI1_CLK_PODF_SHIFT, CCM_CS1CDR_SAI1_CLK_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< sai1 div name */ - kCLOCK_Sai2PreDiv = CCM_TUPLE(CS2CDR, CCM_CS2CDR_SAI2_CLK_PRED_SHIFT, CCM_CS2CDR_SAI2_CLK_PRED_MASK, CCM_NO_BUSY_WAIT), /*!< sai2 pre div name */ - kCLOCK_Sai2Div = CCM_TUPLE(CS2CDR, CCM_CS2CDR_SAI2_CLK_PODF_SHIFT, CCM_CS2CDR_SAI2_CLK_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< sai2 div name */ + kCLOCK_Sai2PreDiv = CCM_TUPLE(CS2CDR, + CCM_CS2CDR_SAI2_CLK_PRED_SHIFT, + CCM_CS2CDR_SAI2_CLK_PRED_MASK, + CCM_NO_BUSY_WAIT), /*!< sai2 pre div name */ + kCLOCK_Sai2Div = CCM_TUPLE( + CS2CDR, CCM_CS2CDR_SAI2_CLK_PODF_SHIFT, CCM_CS2CDR_SAI2_CLK_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< sai2 div name */ - kCLOCK_Spdif0PreDiv = CCM_TUPLE(CDCDR, CCM_CDCDR_SPDIF0_CLK_PRED_SHIFT, CCM_CDCDR_SPDIF0_CLK_PRED_MASK, CCM_NO_BUSY_WAIT), /*!< spdif pre div name */ - kCLOCK_Spdif0Div = CCM_TUPLE(CDCDR, CCM_CDCDR_SPDIF0_CLK_PODF_SHIFT, CCM_CDCDR_SPDIF0_CLK_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< spdif div name */ - kCLOCK_Flexio1PreDiv = CCM_TUPLE(CDCDR, CCM_CDCDR_FLEXIO1_CLK_PRED_SHIFT, CCM_CDCDR_FLEXIO1_CLK_PRED_MASK, CCM_NO_BUSY_WAIT), /*!< flexio1 pre div name */ - kCLOCK_Flexio1Div = CCM_TUPLE(CDCDR, CCM_CDCDR_FLEXIO1_CLK_PODF_SHIFT, CCM_CDCDR_FLEXIO1_CLK_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< flexio1 div name */ + kCLOCK_Spdif0PreDiv = CCM_TUPLE(CDCDR, + CCM_CDCDR_SPDIF0_CLK_PRED_SHIFT, + CCM_CDCDR_SPDIF0_CLK_PRED_MASK, + CCM_NO_BUSY_WAIT), /*!< spdif pre div name */ + kCLOCK_Spdif0Div = CCM_TUPLE(CDCDR, + CCM_CDCDR_SPDIF0_CLK_PODF_SHIFT, + CCM_CDCDR_SPDIF0_CLK_PODF_MASK, + CCM_NO_BUSY_WAIT), /*!< spdif div name */ + kCLOCK_Flexio1PreDiv = CCM_TUPLE(CDCDR, + CCM_CDCDR_FLEXIO1_CLK_PRED_SHIFT, + CCM_CDCDR_FLEXIO1_CLK_PRED_MASK, + CCM_NO_BUSY_WAIT), /*!< flexio1 pre div name */ + kCLOCK_Flexio1Div = CCM_TUPLE(CDCDR, + CCM_CDCDR_FLEXIO1_CLK_PODF_SHIFT, + CCM_CDCDR_FLEXIO1_CLK_PODF_MASK, + CCM_NO_BUSY_WAIT), /*!< flexio1 div name */ - kCLOCK_Lpi2cDiv = CCM_TUPLE(CSCDR2, CCM_CSCDR2_LPI2C_CLK_PODF_SHIFT, CCM_CSCDR2_LPI2C_CLK_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< lpi2c div name */ - kCLOCK_Lcdif1PreDiv = CCM_TUPLE(CSCDR2, CCM_CSCDR2_LCDIF_PRED_SHIFT, CCM_CSCDR2_LCDIF_PRED_MASK, CCM_NO_BUSY_WAIT), /*!< lcdif1 pre div name */ + kCLOCK_Lpi2cDiv = CCM_TUPLE(CSCDR2, + CCM_CSCDR2_LPI2C_CLK_PODF_SHIFT, + CCM_CSCDR2_LPI2C_CLK_PODF_MASK, + CCM_NO_BUSY_WAIT), /*!< lpi2c div name */ + kCLOCK_LcdifPreDiv = CCM_TUPLE( + CSCDR2, CCM_CSCDR2_LCDIF_PRED_SHIFT, CCM_CSCDR2_LCDIF_PRED_MASK, CCM_NO_BUSY_WAIT), /*!< lcdif pre div name */ - kCLOCK_CsiDiv = CCM_TUPLE(CSCDR3, CCM_CSCDR3_CSI_PODF_SHIFT, CCM_CSCDR3_CSI_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< csi div name */ + kCLOCK_CsiDiv = + CCM_TUPLE(CSCDR3, CCM_CSCDR3_CSI_PODF_SHIFT, CCM_CSCDR3_CSI_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< csi div name */ } clock_div_t; - -/*! @brief PLL configuration for ARM */ -typedef struct _clock_arm_pll_config -{ - uint32_t loopDivider; /*!< PLL loop divider. Valid range for divider value: 54-108. Fout=Fin*loopDivider/2. */ -} clock_arm_pll_config_t; - -/*! @brief PLL configuration for USB */ -typedef struct _clock_usb_pll_config -{ - uint8_t loopDivider; /*!< PLL loop divider. - 0 - Fout=Fref*20; - 1 - Fout=Fref*22 */ -} clock_usb_pll_config_t; - - -/*! @brief PLL configuration for System */ -typedef struct _clock_sys_pll_config -{ - uint8_t loopDivider; /*!< PLL loop divider. Intended to be 1 (528M). - 0 - Fout=Fref*20; - 1 - Fout=Fref*22 */ - uint32_t numerator; /*!< 30 bit numerator of fractional loop divider.*/ - uint32_t denominator; /*!< 30 bit denominator of fractional loop divider */ -} clock_sys_pll_config_t; - -/*! @brief PLL configuration for AUDIO and VIDEO */ -typedef struct _clock_audio_pll_config -{ - uint8_t loopDivider; /*!< PLL loop divider. Valid range for DIV_SELECT divider value: 27~54. */ - uint8_t postDivider; /*!< Divider after the PLL, should only be 1, 2, 4, 8, 16. */ - uint32_t numerator; /*!< 30 bit numerator of fractional loop divider.*/ - uint32_t denominator; /*!< 30 bit denominator of fractional loop divider */ -} clock_audio_pll_config_t; - -/*! @brief PLL configuration for AUDIO and VIDEO */ -typedef struct _clock_video_pll_config -{ - uint8_t loopDivider; /*!< PLL loop divider. Valid range for DIV_SELECT divider value: 27~54. */ - uint8_t postDivider; /*!< Divider after the PLL, should only be 1, 2, 4, 8, 16. */ - uint32_t numerator; /*!< 30 bit numerator of fractional loop divider.*/ - uint32_t denominator; /*!< 30 bit denominator of fractional loop divider */ -} clock_video_pll_config_t; - -/*! @brief PLL configuration for ENET */ -typedef struct _clock_enet_pll_config -{ - bool enableClkOutput0; /*!< Power on and enable PLL clock output for ENET0 (ref_enetpll0). */ - bool enableClkOutput1; /*!< Power on and enable PLL clock output for ENET1 (ref_enetpll1). */ - bool enableClkOutput2; /*!< Power on and enable PLL clock output for ENET2 (ref_enetpll2). */ - uint8_t loopDivider0; /*!< Controls the frequency of the ENET0 reference clock. - b00 25MHz - b01 50MHz - b10 100MHz (not 50% duty cycle) - b11 125MHz */ - uint8_t loopDivider1; /*!< Controls the frequency of the ENET1 reference clock. - b00 25MHz - b01 50MHz - b10 100MHz (not 50% duty cycle) - b11 125MHz */ -} clock_enet_pll_config_t; - -/*! @brief PLL name */ -typedef enum _clock_pll -{ - kCLOCK_PllArm = 0U, /*!< PLL ARM */ - kCLOCK_PllSys = 1U, /*!< PLL SYS */ - kCLOCK_PllUsb1 = 2U, /*!< PLL USB1 */ - kCLOCK_PllAudio = 3U, /*!< PLL Audio */ - kCLOCK_PllVideo = 4U, /*!< PLL Video */ - kCLOCK_PllEnet0 = 5U, /*!< PLL Enet0 */ - kCLOCK_PllEnet1 = 6U, /*!< PLL Enet1 */ - kCLOCK_PllEnet2 = 7U, /*!< PLL Enet2 */ - kCLOCK_PllUsb2 = 8U, /*!< PLL USB2 */ -} clock_pll_t; - -/*! @brief PLL PFD name */ -typedef enum _clock_pfd -{ - kCLOCK_Pfd0 = 0U, /*!< PLL PFD0 */ - kCLOCK_Pfd1 = 1U, /*!< PLL PFD1 */ - kCLOCK_Pfd2 = 2U, /*!< PLL PFD2 */ - kCLOCK_Pfd3 = 3U, /*!< PLL PFD3 */ -} clock_pfd_t; - /*! @brief USB clock source definition. */ typedef enum _clock_usb_src { - kCLOCK_Usb480M = 0, /*!< Use 480M. */ - kCLOCK_UsbSrcUnused = 0xFFFFFFFFU, /*!< Used when the function does not - care the clock source. */ + kCLOCK_Usb480M = 0, /*!< Use 480M. */ + kCLOCK_UsbSrcUnused = (int)0xFFFFFFFFU, /*!< Used when the function does not + care the clock source. */ } clock_usb_src_t; /*! @brief Source of the USB HS PHY. */ typedef enum _clock_usb_phy_src { - kCLOCK_Usbphy480M = 0, /*!< Use 480M. */ + kCLOCK_Usbphy480M = 0, /*!< Use 480M. */ } clock_usb_phy_src_t; +/*!@brief PLL clock source, bypass cloco source also */ +enum _clock_pll_clk_src +{ + kCLOCK_PllClkSrc24M = 0U, /*!< Pll clock source 24M */ + kCLOCK_PllSrcClkPN = 1U, /*!< Pll clock source CLK1_P and CLK1_N */ +}; + +/*! @brief PLL configuration for ARM */ +typedef struct _clock_arm_pll_config +{ + uint32_t loopDivider; /*!< PLL loop divider. Valid range for divider value: 54-108. Fout=Fin*loopDivider/2. */ + uint8_t src; /*!< Pll clock source, reference _clock_pll_clk_src */ +} clock_arm_pll_config_t; + +/*! @brief PLL configuration for USB */ +typedef struct _clock_usb_pll_config +{ + uint8_t loopDivider; /*!< PLL loop divider. + 0 - Fout=Fref*20; + 1 - Fout=Fref*22 */ + uint8_t src; /*!< Pll clock source, reference _clock_pll_clk_src */ + +} clock_usb_pll_config_t; + +/*! @brief PLL configuration for System */ +typedef struct _clock_sys_pll_config +{ + uint8_t loopDivider; /*!< PLL loop divider. Intended to be 1 (528M). + 0 - Fout=Fref*20; + 1 - Fout=Fref*22 */ + uint32_t numerator; /*!< 30 bit numerator of fractional loop divider.*/ + uint32_t denominator; /*!< 30 bit denominator of fractional loop divider */ + uint8_t src; /*!< Pll clock source, reference _clock_pll_clk_src */ + uint16_t ss_stop; /*!< Stop value to get frequency change. */ + uint8_t ss_enable; /*!< Enable spread spectrum modulation */ + uint16_t ss_step; /*!< Step value to get frequency change step. */ + +} clock_sys_pll_config_t; + +/*! @brief PLL configuration for AUDIO and VIDEO */ +typedef struct _clock_audio_pll_config +{ + uint8_t loopDivider; /*!< PLL loop divider. Valid range for DIV_SELECT divider value: 27~54. */ + uint8_t postDivider; /*!< Divider after the PLL, should only be 1, 2, 4, 8, 16. */ + uint32_t numerator; /*!< 30 bit numerator of fractional loop divider.*/ + uint32_t denominator; /*!< 30 bit denominator of fractional loop divider */ + uint8_t src; /*!< Pll clock source, reference _clock_pll_clk_src */ +} clock_audio_pll_config_t; + +/*! @brief PLL configuration for AUDIO and VIDEO */ +typedef struct _clock_video_pll_config +{ + uint8_t loopDivider; /*!< PLL loop divider. Valid range for DIV_SELECT divider value: 27~54. */ + uint8_t postDivider; /*!< Divider after the PLL, should only be 1, 2, 4, 8, 16. */ + uint32_t numerator; /*!< 30 bit numerator of fractional loop divider.*/ + uint32_t denominator; /*!< 30 bit denominator of fractional loop divider */ + uint8_t src; /*!< Pll clock source, reference _clock_pll_clk_src */ + +} clock_video_pll_config_t; + +/*! @brief PLL configuration for ENET */ +typedef struct _clock_enet_pll_config +{ + bool enableClkOutput; /*!< Power on and enable PLL clock output for ENET0 (ref_enetpll0). */ + + bool enableClkOutput25M; /*!< Power on and enable PLL clock output for ENET1 (ref_enetpll1). */ + uint8_t loopDivider; /*!< Controls the frequency of the ENET0 reference clock. + b00 25MHz + b01 50MHz + b10 100MHz (not 50% duty cycle) + b11 125MHz */ + uint8_t src; /*!< Pll clock source, reference _clock_pll_clk_src */ + +} clock_enet_pll_config_t; + +/*! @brief PLL name */ +typedef enum _clock_pll +{ + kCLOCK_PllArm = CCM_ANALOG_TUPLE(PLL_ARM, CCM_ANALOG_PLL_ARM_ENABLE_SHIFT), /*!< PLL ARM */ + kCLOCK_PllSys = CCM_ANALOG_TUPLE(PLL_SYS, CCM_ANALOG_PLL_SYS_ENABLE_SHIFT), /*!< PLL SYS */ + kCLOCK_PllUsb1 = CCM_ANALOG_TUPLE(PLL_USB1, CCM_ANALOG_PLL_USB1_ENABLE_SHIFT), /*!< PLL USB1 */ + kCLOCK_PllAudio = CCM_ANALOG_TUPLE(PLL_AUDIO, CCM_ANALOG_PLL_AUDIO_ENABLE_SHIFT), /*!< PLL Audio */ + kCLOCK_PllVideo = CCM_ANALOG_TUPLE(PLL_VIDEO, CCM_ANALOG_PLL_VIDEO_ENABLE_SHIFT), /*!< PLL Video */ + + kCLOCK_PllEnet = CCM_ANALOG_TUPLE(PLL_ENET, CCM_ANALOG_PLL_ENET_ENABLE_SHIFT), /*!< PLL Enet0 */ + + kCLOCK_PllEnet25M = CCM_ANALOG_TUPLE(PLL_ENET, CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_SHIFT), /*!< PLL Enet1 */ + + kCLOCK_PllUsb2 = CCM_ANALOG_TUPLE(PLL_USB2, CCM_ANALOG_PLL_USB2_ENABLE_SHIFT), /*!< PLL USB2 */ + +} clock_pll_t; + +/*! @brief PLL PFD name */ +typedef enum _clock_pfd +{ + kCLOCK_Pfd0 = 0U, /*!< PLL PFD0 */ + kCLOCK_Pfd1 = 1U, /*!< PLL PFD1 */ + kCLOCK_Pfd2 = 2U, /*!< PLL PFD2 */ + kCLOCK_Pfd3 = 3U, /*!< PLL PFD3 */ +} clock_pfd_t; + /******************************************************************************* * API ******************************************************************************/ @@ -814,7 +922,7 @@ static inline void CLOCK_SetDiv(clock_div_t divider, uint32_t value) busyShift = CCM_TUPLE_BUSY_SHIFT(divider); CCM_TUPLE_REG(CCM, divider) = (CCM_TUPLE_REG(CCM, divider) & (~CCM_TUPLE_MASK(divider))) | - (((uint32_t)((value) << CCM_TUPLE_SHIFT(divider))) & CCM_TUPLE_MASK(divider)); + (((uint32_t)((value) << CCM_TUPLE_SHIFT(divider))) & CCM_TUPLE_MASK(divider)); assert(busyShift <= CCM_NO_BUSY_WAIT); @@ -835,10 +943,7 @@ static inline void CLOCK_SetDiv(clock_div_t divider, uint32_t value) */ static inline uint32_t CLOCK_GetDiv(clock_div_t divider) { - uint32_t value; - - value = (CCM_TUPLE_REG(CCM, divider) & CCM_TUPLE_MASK(divider)) >> CCM_TUPLE_SHIFT(divider); - return value; + return ((CCM_TUPLE_REG(CCM, divider) & CCM_TUPLE_MASK(divider)) >> CCM_TUPLE_SHIFT(divider)); } /*! @@ -853,7 +958,7 @@ static inline void CLOCK_ControlGate(clock_ip_name_t name, clock_gate_value_t va uint32_t shift = ((uint32_t)name) & 0x1FU; volatile uint32_t *reg; - assert (index <= 6); + assert(index <= 6); reg = ((volatile uint32_t *)&CCM->CCGR0) + index; *reg = ((*reg) & ~(3U << shift)) | (((uint32_t)value) << shift); @@ -888,7 +993,50 @@ static inline void CLOCK_SetMode(clock_mode_t mode) { CCM->CLPCR = (CCM->CLPCR & ~CCM_CLPCR_LPM_MASK) | CCM_CLPCR_LPM((uint32_t)mode); } - + +/*! + * @brief Gets the OSC clock frequency. + * + * This function will return the external XTAL OSC frequency if it is selected as the source of OSC, + * otherwise internal 24MHz RC OSC frequency will be returned. + * + * @param osc OSC type to get frequency. + * + * @return Clock frequency; If the clock is invalid, returns 0. + */ +static inline uint32_t CLOCK_GetOscFreq(void) +{ + return (XTALOSC24M->LOWPWR_CTRL & XTALOSC24M_LOWPWR_CTRL_OSC_SEL_MASK) ? 24000000UL : g_xtalFreq; +} + +/*! + * @brief Gets the AHB clock frequency. + * + * @return The AHB clock frequency value in hertz. + */ +uint32_t CLOCK_GetAhbFreq(void); + +/*! + * @brief Gets the SEMC clock frequency. + * + * @return The SEMC clock frequency value in hertz. + */ +uint32_t CLOCK_GetSemcFreq(void); + +/*! + * @brief Gets the IPG clock frequency. + * + * @return The IPG clock frequency value in hertz. + */ +uint32_t CLOCK_GetIpgFreq(void); + +/*! + * @brief Gets the PER clock frequency. + * + * @return The PER clock frequency value in hertz. + */ +uint32_t CLOCK_GetPerClkFreq(void); + /*! * @brief Gets the clock frequency for a specific clock name. * @@ -950,21 +1098,6 @@ void CLOCK_DeinitExternalClk(void); */ void CLOCK_SwitchOsc(clock_osc_t osc); -/*! - * @brief Gets the OSC clock frequency. - * - * This function will return the external XTAL OSC frequency if it is selected as the source of OSC, - * otherwise internal 24MHz RC OSC frequency will be returned. - * - * @param osc OSC type to get frequency. - * - * @return Clock frequency; If the clock is invalid, returns 0. - */ -static inline uint32_t CLOCK_GetOscFreq(void) -{ - return (XTALOSC24M->LOWPWR_CTRL & XTALOSC24M_LOWPWR_CTRL_OSC_SEL_MASK) ? 24000000UL : g_xtalFreq; -} - /*! * @brief Gets the RTC clock frequency. * @@ -995,7 +1128,6 @@ static inline void CLOCK_SetRtcXtalFreq(uint32_t freq) g_rtcXtalFreq = freq; } - /*! * @brief Initialize the RC oscillator 24MHz clock. */ @@ -1007,10 +1139,121 @@ void CLOCK_InitRcOsc24M(void); void CLOCK_DeinitRcOsc24M(void); /* @} */ +/*! @brief Enable USB HS clock. + * + * This function only enables the access to USB HS prepheral, upper layer + * should first call the @ref CLOCK_EnableUsbhs0PhyPllClock to enable the PHY + * clock to use USB HS. + * + * @param src USB HS does not care about the clock source, here must be @ref kCLOCK_UsbSrcUnused. + * @param freq USB HS does not care about the clock source, so this parameter is ignored. + * @retval true The clock is set successfully. + * @retval false The clock source is invalid to get proper USB HS clock. + */ +bool CLOCK_EnableUsbhs0Clock(clock_usb_src_t src, uint32_t freq); + +/*! @brief Enable USB HS clock. + * + * This function only enables the access to USB HS prepheral, upper layer + * should first call the @ref CLOCK_EnableUsbhs0PhyPllClock to enable the PHY + * clock to use USB HS. + * + * @param src USB HS does not care about the clock source, here must be @ref kCLOCK_UsbSrcUnused. + * @param freq USB HS does not care about the clock source, so this parameter is ignored. + * @retval true The clock is set successfully. + * @retval false The clock source is invalid to get proper USB HS clock. + */ +bool CLOCK_EnableUsbhs1Clock(clock_usb_src_t src, uint32_t freq); + +/*! @brief Disable USB HS PHY PLL clock. + * + * This function disables USB HS PHY PLL clock. + */ +void CLOCK_DisableUsbhs1PhyPllClock(void); + +/* @} */ + /*! * @name PLL/PFD operations * @{ */ +/*! + * @brief PLL bypass setting + * + * @param base CCM_ANALOG base pointer. + * @param pll PLL control name (see @ref ccm_analog_pll_control_t enumeration) + * @param bypass Bypass the PLL. + * - true: Bypass the PLL. + * - false:Not bypass the PLL. + */ +static inline void CLOCK_SetPllBypass(CCM_ANALOG_Type *base, clock_pll_t pll, bool bypass) +{ + if (bypass) + { + CCM_ANALOG_TUPLE_REG_OFF(base, pll, 4U) = 1U << CCM_ANALOG_PLL_BYPASS_SHIFT; + } + else + { + CCM_ANALOG_TUPLE_REG_OFF(base, pll, 8U) = 1U << CCM_ANALOG_PLL_BYPASS_SHIFT; + } +} + +/*! + * @brief Check if PLL is bypassed + * + * @param base CCM_ANALOG base pointer. + * @param pll PLL control name (see @ref ccm_analog_pll_control_t enumeration) + * @return PLL bypass status. + * - true: The PLL is bypassed. + * - false: The PLL is not bypassed. + */ +static inline bool CLOCK_IsPllBypassed(CCM_ANALOG_Type *base, clock_pll_t pll) +{ + return (bool)(CCM_ANALOG_TUPLE_REG(base, pll) & (1U << CCM_ANALOG_PLL_BYPASS_SHIFT)); +} + +/*! + * @brief Check if PLL is enabled + * + * @param base CCM_ANALOG base pointer. + * @param pll PLL control name (see @ref ccm_analog_pll_control_t enumeration) + * @return PLL bypass status. + * - true: The PLL is enabled. + * - false: The PLL is not enabled. + */ +static inline bool CLOCK_IsPllEnabled(CCM_ANALOG_Type *base, clock_pll_t pll) +{ + return (bool)(CCM_ANALOG_TUPLE_REG(base, pll) & (1U << CCM_ANALOG_TUPLE_SHIFT(pll))); +} + +/*! + * @brief PLL bypass clock source setting. + * Note: change the bypass clock source also change the pll reference clock source. + * + * @param base CCM_ANALOG base pointer. + * @param pll PLL control name (see @ref ccm_analog_pll_control_t enumeration) + * @param src Bypass clock source, reference _clock_pll_bypass_clk_src. + */ +static inline void CLOCK_SetPllBypassRefClkSrc(CCM_ANALOG_Type *base, clock_pll_t pll, uint32_t src) +{ + CCM_ANALOG_TUPLE_REG(base, pll) |= (CCM_ANALOG_TUPLE_REG(base, pll) & (~CCM_ANALOG_PLL_BYPASS_CLK_SRC_MASK)) | src; +} + +/*! + * @brief Get PLL bypass clock value, it is PLL reference clock actually. + * If CLOCK1_P,CLOCK1_N is choose as the pll bypass clock source, please implement the CLKPN_FREQ define, otherwise 0 + * will be returned. + * @param base CCM_ANALOG base pointer. + * @param pll PLL control name (see @ref ccm_analog_pll_control_t enumeration) + * @retval bypass reference clock frequency value. + */ +static inline uint32_t CLOCK_GetPllBypassRefClk(CCM_ANALOG_Type *base, clock_pll_t pll) +{ + return (((CCM_ANALOG_TUPLE_REG(base, pll) & CCM_ANALOG_PLL_BYPASS_CLK_SRC_MASK) >> + CCM_ANALOG_PLL_BYPASS_CLK_SRC_SHIFT) == kCLOCK_PllClkSrc24M) ? + CLOCK_GetOscFreq() : + CLKPN_FREQ; +} /*! * @brief Initialize the ARM PLL. @@ -1095,7 +1338,6 @@ void CLOCK_InitVideoPll(const clock_video_pll_config_t *config); * @brief De-initialize the Video PLL. */ void CLOCK_DeinitVideoPll(void); - /*! * @brief Initialize the ENET PLL. * @@ -1184,20 +1426,6 @@ uint32_t CLOCK_GetSysPfdFreq(clock_pfd_t pfd); */ uint32_t CLOCK_GetUsb1PfdFreq(clock_pfd_t pfd); -/*! @brief Enable USB HS clock. - * - * This function only enables the access to USB HS prepheral, upper layer - * should first call the @ref CLOCK_EnableUsbhs0PhyPllClock to enable the PHY - * clock to use USB HS. - * - * @param src USB HS does not care about the clock source, here must be @ref kCLOCK_UsbSrcUnused. - * @param freq USB HS does not care about the clock source, so this parameter is ignored. - * @retval true The clock is set successfully. - * @retval false The clock source is invalid to get proper USB HS clock. - */ -bool CLOCK_EnableUsbhs0Clock(clock_usb_src_t src, uint32_t freq); - - /*! @brief Enable USB HS PHY PLL clock. * * This function enables the internal 480MHz USB PHY PLL clock. @@ -1215,20 +1443,6 @@ bool CLOCK_EnableUsbhs0PhyPllClock(clock_usb_phy_src_t src, uint32_t freq); */ void CLOCK_DisableUsbhs0PhyPllClock(void); -/*! @brief Enable USB HS clock. - * - * This function only enables the access to USB HS prepheral, upper layer - * should first call the @ref CLOCK_EnableUsbhs0PhyPllClock to enable the PHY - * clock to use USB HS. - * - * @param src USB HS does not care about the clock source, here must be @ref kCLOCK_UsbSrcUnused. - * @param freq USB HS does not care about the clock source, so this parameter is ignored. - * @retval true The clock is set successfully. - * @retval false The clock source is invalid to get proper USB HS clock. - */ -bool CLOCK_EnableUsbhs1Clock(clock_usb_src_t src, uint32_t freq); - - /*! @brief Enable USB HS PHY PLL clock. * * This function enables the internal 480MHz USB PHY PLL clock. @@ -1248,7 +1462,6 @@ void CLOCK_DisableUsbhs1PhyPllClock(void); /* @} */ - #if defined(__cplusplus) } #endif /* __cplusplus */ diff --git a/ext/hal/nxp/mcux/devices/MIMXRT1052/fsl_device_registers.h b/ext/hal/nxp/mcux/devices/MIMXRT1052/fsl_device_registers.h index e569bbeba9b..54caf43ca6c 100644 --- a/ext/hal/nxp/mcux/devices/MIMXRT1052/fsl_device_registers.h +++ b/ext/hal/nxp/mcux/devices/MIMXRT1052/fsl_device_registers.h @@ -1,30 +1,9 @@ /* * Copyright 2014-2016 Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * Copyright 2016-2018 NXP + * All rights reserved. * - * 1. Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * 3. Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * SPDX-License-Identifier: BSD-3-Clause * */ @@ -36,7 +15,8 @@ * * The CPU macro should be declared in the project or makefile. */ -#if (defined(CPU_MIMXRT1052CVL5A) || defined(CPU_MIMXRT1052DVL6A)) +#if (defined(CPU_MIMXRT1052CVJ5B) || defined(CPU_MIMXRT1052CVL5B) || defined(CPU_MIMXRT1052DVJ6B) || \ + defined(CPU_MIMXRT1052DVL6B)) #define MIMXRT1052_SERIES diff --git a/ext/hal/nxp/mcux/devices/MIMXRT1052/fsl_iomuxc.h b/ext/hal/nxp/mcux/devices/MIMXRT1052/fsl_iomuxc.h index ff5f9d9dd77..d6f335592b2 100644 --- a/ext/hal/nxp/mcux/devices/MIMXRT1052/fsl_iomuxc.h +++ b/ext/hal/nxp/mcux/devices/MIMXRT1052/fsl_iomuxc.h @@ -1,31 +1,9 @@ /* - * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016 Freescale Semiconductor, Inc. + * Copyright 2016-2018 NXP * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of Freescale Semiconductor, Inc. nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * SPDX-License-Identifier: BSD-3-Clause */ #ifndef _FSL_IOMUXC_H_ @@ -43,6 +21,10 @@ /******************************************************************************* * Definitions ******************************************************************************/ +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.iomuxc" +#endif /*! @name Driver version */ /*@{*/ @@ -54,7 +36,7 @@ /*@{*/ /*! @brief The pin function ID is a tuple of */ #define IOMUXC_SNVS_WAKEUP_GPIO5_IO00 0x400A8000U, 0x5U, 0, 0, 0x400A8018U -#define IOMUXC_SNVS_WAKEUP_NMI_GLUE_NMI 0x400A8000U, 0x7U, 0, 0, 0x400A8018U +#define IOMUXC_SNVS_WAKEUP_NMI_GLUE_NMI 0x400A8000U, 0x7U, 0x401F8568U, 0x1U, 0x400A8018U #define IOMUXC_SNVS_PMIC_ON_REQ_SNVS_LP_PMIC_ON_REQ 0x400A8004U, 0x0U, 0, 0, 0x400A801CU #define IOMUXC_SNVS_PMIC_ON_REQ_GPIO5_IO01 0x400A8004U, 0x5U, 0, 0, 0x400A801CU @@ -74,7 +56,6 @@ #define IOMUXC_GPIO_EMC_00_XBAR1_XBAR_IN02 0x401F8014U, 0x3U, 0x401F860CU, 0x0U, 0x401F8204U #define IOMUXC_GPIO_EMC_00_FLEXIO1_FLEXIO00 0x401F8014U, 0x4U, 0, 0, 0x401F8204U #define IOMUXC_GPIO_EMC_00_GPIO4_IO00 0x401F8014U, 0x5U, 0, 0, 0x401F8204U -#define IOMUXC_GPIO_EMC_00_JTAG_DONE 0x401F8014U, 0x7U, 0, 0, 0x401F8204U #define IOMUXC_GPIO_EMC_01_SEMC_DATA01 0x401F8018U, 0x0U, 0, 0, 0x401F8208U #define IOMUXC_GPIO_EMC_01_FLEXPWM4_PWMB00 0x401F8018U, 0x1U, 0, 0, 0x401F8208U @@ -82,7 +63,6 @@ #define IOMUXC_GPIO_EMC_01_XBAR1_IN03 0x401F8018U, 0x3U, 0x401F8610U, 0x0U, 0x401F8208U #define IOMUXC_GPIO_EMC_01_FLEXIO1_FLEXIO01 0x401F8018U, 0x4U, 0, 0, 0x401F8208U #define IOMUXC_GPIO_EMC_01_GPIO4_IO01 0x401F8018U, 0x5U, 0, 0, 0x401F8208U -#define IOMUXC_GPIO_EMC_01_JTAG_DE_B 0x401F8018U, 0x7U, 0, 0, 0x401F8208U #define IOMUXC_GPIO_EMC_02_SEMC_DATA02 0x401F801CU, 0x0U, 0, 0, 0x401F820CU #define IOMUXC_GPIO_EMC_02_FLEXPWM4_PWMA01 0x401F801CU, 0x1U, 0x401F8498U, 0x0U, 0x401F820CU @@ -90,7 +70,6 @@ #define IOMUXC_GPIO_EMC_02_XBAR1_INOUT04 0x401F801CU, 0x3U, 0x401F8614U, 0x0U, 0x401F820CU #define IOMUXC_GPIO_EMC_02_FLEXIO1_FLEXIO02 0x401F801CU, 0x4U, 0, 0, 0x401F820CU #define IOMUXC_GPIO_EMC_02_GPIO4_IO02 0x401F801CU, 0x5U, 0, 0, 0x401F820CU -#define IOMUXC_GPIO_EMC_02_JTAG_FAIL 0x401F801CU, 0x7U, 0, 0, 0x401F820CU #define IOMUXC_GPIO_EMC_03_SEMC_DATA03 0x401F8020U, 0x0U, 0, 0, 0x401F8210U #define IOMUXC_GPIO_EMC_03_FLEXPWM4_PWMB01 0x401F8020U, 0x1U, 0, 0, 0x401F8210U @@ -98,7 +77,6 @@ #define IOMUXC_GPIO_EMC_03_XBAR1_INOUT05 0x401F8020U, 0x3U, 0x401F8618U, 0x0U, 0x401F8210U #define IOMUXC_GPIO_EMC_03_FLEXIO1_FLEXIO03 0x401F8020U, 0x4U, 0, 0, 0x401F8210U #define IOMUXC_GPIO_EMC_03_GPIO4_IO03 0x401F8020U, 0x5U, 0, 0, 0x401F8210U -#define IOMUXC_GPIO_EMC_03_JTAG_ACTIVE 0x401F8020U, 0x7U, 0, 0, 0x401F8210U #define IOMUXC_GPIO_EMC_04_SEMC_DATA04 0x401F8024U, 0x0U, 0, 0, 0x401F8214U #define IOMUXC_GPIO_EMC_04_FLEXPWM4_PWMA02 0x401F8024U, 0x1U, 0x401F849CU, 0x0U, 0x401F8214U @@ -490,6 +468,7 @@ #define IOMUXC_GPIO_AD_B0_12_FLEXPWM1_PWMX02 0x401F80ECU, 0x4U, 0, 0, 0x401F82DCU #define IOMUXC_GPIO_AD_B0_12_GPIO1_IO12 0x401F80ECU, 0x5U, 0, 0, 0x401F82DCU #define IOMUXC_GPIO_AD_B0_12_ENET_1588_EVENT1_OUT 0x401F80ECU, 0x6U, 0, 0, 0x401F82DCU +#define IOMUXC_GPIO_AD_B0_12_NMI_GLUE_NMI 0x401F80ECU, 0x7U, 0x401F8568U, 0x0U, 0x401F82DCU #define IOMUXC_GPIO_AD_B0_13_LPI2C4_SDA 0x401F80F0U, 0x0U, 0x401F84E8U, 0x1U, 0x401F82E0U #define IOMUXC_GPIO_AD_B0_13_GPT1_CLK 0x401F80F0U, 0x1U, 0, 0, 0x401F82E0U @@ -696,6 +675,7 @@ #define IOMUXC_GPIO_B0_04_LCD_DATA00 0x401F814CU, 0x0U, 0, 0, 0x401F833CU #define IOMUXC_GPIO_B0_04_QTIMER2_TIMER1 0x401F814CU, 0x1U, 0x401F8570U, 0x1U, 0x401F833CU #define IOMUXC_GPIO_B0_04_LPI2C2_SCL 0x401F814CU, 0x2U, 0x401F84D4U, 0x1U, 0x401F833CU +#define IOMUXC_GPIO_B0_04_ARM_CM7_TRACE00 0x401F814CU, 0x3U, 0, 0, 0x401F833CU #define IOMUXC_GPIO_B0_04_FLEXIO2_FLEXIO04 0x401F814CU, 0x4U, 0, 0, 0x401F833CU #define IOMUXC_GPIO_B0_04_GPIO2_IO04 0x401F814CU, 0x5U, 0, 0, 0x401F833CU #define IOMUXC_GPIO_B0_04_SRC_BOOT_CFG00 0x401F814CU, 0x6U, 0, 0, 0x401F833CU @@ -703,6 +683,7 @@ #define IOMUXC_GPIO_B0_05_LCD_DATA01 0x401F8150U, 0x0U, 0, 0, 0x401F8340U #define IOMUXC_GPIO_B0_05_QTIMER2_TIMER2 0x401F8150U, 0x1U, 0x401F8574U, 0x1U, 0x401F8340U #define IOMUXC_GPIO_B0_05_LPI2C2_SDA 0x401F8150U, 0x2U, 0x401F84D8U, 0x1U, 0x401F8340U +#define IOMUXC_GPIO_B0_05_ARM_CM7_TRACE01 0x401F8150U, 0x3U, 0, 0, 0x401F8340U #define IOMUXC_GPIO_B0_05_FLEXIO2_FLEXIO05 0x401F8150U, 0x4U, 0, 0, 0x401F8340U #define IOMUXC_GPIO_B0_05_GPIO2_IO05 0x401F8150U, 0x5U, 0, 0, 0x401F8340U #define IOMUXC_GPIO_B0_05_SRC_BOOT_CFG01 0x401F8150U, 0x6U, 0, 0, 0x401F8340U @@ -710,6 +691,7 @@ #define IOMUXC_GPIO_B0_06_LCD_DATA02 0x401F8154U, 0x0U, 0, 0, 0x401F8344U #define IOMUXC_GPIO_B0_06_QTIMER3_TIMER0 0x401F8154U, 0x1U, 0x401F857CU, 0x2U, 0x401F8344U #define IOMUXC_GPIO_B0_06_FLEXPWM2_PWMA00 0x401F8154U, 0x2U, 0x401F8478U, 0x1U, 0x401F8344U +#define IOMUXC_GPIO_B0_06_ARM_CM7_TRACE02 0x401F8154U, 0x3U, 0, 0, 0x401F8344U #define IOMUXC_GPIO_B0_06_FLEXIO2_FLEXIO06 0x401F8154U, 0x4U, 0, 0, 0x401F8344U #define IOMUXC_GPIO_B0_06_GPIO2_IO06 0x401F8154U, 0x5U, 0, 0, 0x401F8344U #define IOMUXC_GPIO_B0_06_SRC_BOOT_CFG02 0x401F8154U, 0x6U, 0, 0, 0x401F8344U @@ -717,6 +699,7 @@ #define IOMUXC_GPIO_B0_07_LCD_DATA03 0x401F8158U, 0x0U, 0, 0, 0x401F8348U #define IOMUXC_GPIO_B0_07_QTIMER3_TIMER1 0x401F8158U, 0x1U, 0x401F8580U, 0x2U, 0x401F8348U #define IOMUXC_GPIO_B0_07_FLEXPWM2_PWMB00 0x401F8158U, 0x2U, 0x401F8488U, 0x1U, 0x401F8348U +#define IOMUXC_GPIO_B0_07_ARM_CM7_TRACE03 0x401F8158U, 0x3U, 0, 0, 0x401F8348U #define IOMUXC_GPIO_B0_07_FLEXIO2_FLEXIO07 0x401F8158U, 0x4U, 0, 0, 0x401F8348U #define IOMUXC_GPIO_B0_07_GPIO2_IO07 0x401F8158U, 0x5U, 0, 0, 0x401F8348U #define IOMUXC_GPIO_B0_07_SRC_BOOT_CFG03 0x401F8158U, 0x6U, 0, 0, 0x401F8348U @@ -755,6 +738,7 @@ #define IOMUXC_GPIO_B0_12_LCD_DATA08 0x401F816CU, 0x0U, 0, 0, 0x401F835CU #define IOMUXC_GPIO_B0_12_XBAR1_INOUT10 0x401F816CU, 0x1U, 0, 0, 0x401F835CU +#define IOMUXC_GPIO_B0_12_ARM_CM7_TRACE_CLK 0x401F816CU, 0x2U, 0, 0, 0x401F835CU #define IOMUXC_GPIO_B0_12_SAI1_TX_DATA01 0x401F816CU, 0x3U, 0x401F85A0U, 0x1U, 0x401F835CU #define IOMUXC_GPIO_B0_12_FLEXIO2_FLEXIO12 0x401F816CU, 0x4U, 0, 0, 0x401F835CU #define IOMUXC_GPIO_B0_12_GPIO2_IO12 0x401F816CU, 0x5U, 0, 0, 0x401F835CU @@ -762,6 +746,7 @@ #define IOMUXC_GPIO_B0_13_LCD_DATA09 0x401F8170U, 0x0U, 0, 0, 0x401F8360U #define IOMUXC_GPIO_B0_13_XBAR1_INOUT11 0x401F8170U, 0x1U, 0, 0, 0x401F8360U +#define IOMUXC_GPIO_B0_13_ARM_CM7_TRACE_SWO 0x401F8170U, 0x2U, 0, 0, 0x401F8360U #define IOMUXC_GPIO_B0_13_SAI1_MCLK 0x401F8170U, 0x3U, 0x401F858CU, 0x2U, 0x401F8360U #define IOMUXC_GPIO_B0_13_FLEXIO2_FLEXIO13 0x401F8170U, 0x4U, 0, 0, 0x401F8360U #define IOMUXC_GPIO_B0_13_GPIO2_IO13 0x401F8170U, 0x5U, 0, 0, 0x401F8360U @@ -821,7 +806,6 @@ #define IOMUXC_GPIO_B1_04_ENET_RX_DATA00 0x401F818CU, 0x3U, 0x401F8434U, 0x1U, 0x401F837CU #define IOMUXC_GPIO_B1_04_FLEXIO2_FLEXIO20 0x401F818CU, 0x4U, 0, 0, 0x401F837CU #define IOMUXC_GPIO_B1_04_GPIO2_IO20 0x401F818CU, 0x5U, 0, 0, 0x401F837CU -#define IOMUXC_GPIO_B1_04_CSU_CSU_ALARM_AUT02 0x401F818CU, 0x6U, 0, 0, 0x401F837CU #define IOMUXC_GPIO_B1_05_LCD_DATA17 0x401F8190U, 0x0U, 0, 0, 0x401F8380U #define IOMUXC_GPIO_B1_05_LPSPI4_SDI 0x401F8190U, 0x1U, 0x401F8524U, 0x1U, 0x401F8380U @@ -829,7 +813,6 @@ #define IOMUXC_GPIO_B1_05_ENET_RX_DATA01 0x401F8190U, 0x3U, 0x401F8438U, 0x1U, 0x401F8380U #define IOMUXC_GPIO_B1_05_FLEXIO2_FLEXIO21 0x401F8190U, 0x4U, 0, 0, 0x401F8380U #define IOMUXC_GPIO_B1_05_GPIO2_IO21 0x401F8190U, 0x5U, 0, 0, 0x401F8380U -#define IOMUXC_GPIO_B1_05_CSU_CSU_ALARM_AUT01 0x401F8190U, 0x6U, 0, 0, 0x401F8380U #define IOMUXC_GPIO_B1_06_LCD_DATA18 0x401F8194U, 0x0U, 0, 0, 0x401F8384U #define IOMUXC_GPIO_B1_06_LPSPI4_SDO 0x401F8194U, 0x1U, 0x401F8528U, 0x1U, 0x401F8384U @@ -837,7 +820,6 @@ #define IOMUXC_GPIO_B1_06_ENET_RX_EN 0x401F8194U, 0x3U, 0x401F843CU, 0x1U, 0x401F8384U #define IOMUXC_GPIO_B1_06_FLEXIO2_FLEXIO22 0x401F8194U, 0x4U, 0, 0, 0x401F8384U #define IOMUXC_GPIO_B1_06_GPIO2_IO22 0x401F8194U, 0x5U, 0, 0, 0x401F8384U -#define IOMUXC_GPIO_B1_06_CSU_CSU_ALARM_AUT00 0x401F8194U, 0x6U, 0, 0, 0x401F8384U #define IOMUXC_GPIO_B1_07_LCD_DATA19 0x401F8198U, 0x0U, 0, 0, 0x401F8388U #define IOMUXC_GPIO_B1_07_LPSPI4_SCK 0x401F8198U, 0x1U, 0x401F8520U, 0x1U, 0x401F8388U @@ -845,7 +827,6 @@ #define IOMUXC_GPIO_B1_07_ENET_TX_DATA00 0x401F8198U, 0x3U, 0, 0, 0x401F8388U #define IOMUXC_GPIO_B1_07_FLEXIO2_FLEXIO23 0x401F8198U, 0x4U, 0, 0, 0x401F8388U #define IOMUXC_GPIO_B1_07_GPIO2_IO23 0x401F8198U, 0x5U, 0, 0, 0x401F8388U -#define IOMUXC_GPIO_B1_07_CSU_CSU_INT_DEB 0x401F8198U, 0x6U, 0, 0, 0x401F8388U #define IOMUXC_GPIO_B1_08_LCD_DATA20 0x401F819CU, 0x0U, 0, 0, 0x401F838CU #define IOMUXC_GPIO_B1_08_QTIMER1_TIMER3 0x401F819CU, 0x1U, 0, 0, 0x401F838CU @@ -969,7 +950,6 @@ #define IOMUXC_GPIO_SD_B1_01_SAI1_TX_DATA02 0x401F81D8U, 0x3U, 0x401F859CU, 0x0U, 0x401F83C8U #define IOMUXC_GPIO_SD_B1_01_LPUART4_RX 0x401F81D8U, 0x4U, 0x401F8540U, 0x0U, 0x401F83C8U #define IOMUXC_GPIO_SD_B1_01_GPIO3_IO01 0x401F81D8U, 0x5U, 0, 0, 0x401F83C8U -#define IOMUXC_GPIO_SD_B1_01_CCM_DI0_EXT_CLK 0x401F81D8U, 0x6U, 0, 0, 0x401F83C8U #define IOMUXC_GPIO_SD_B1_02_USDHC2_DATA1 0x401F81DCU, 0x0U, 0x401F85ECU, 0x0U, 0x401F83CCU #define IOMUXC_GPIO_SD_B1_02_FLEXSPIB_DATA01 0x401F81DCU, 0x1U, 0x401F84BCU, 0x0U, 0x401F83CCU @@ -1015,7 +995,6 @@ #define IOMUXC_GPIO_SD_B1_07_SAI1_TX_DATA00 0x401F81F0U, 0x3U, 0, 0, 0x401F83E0U #define IOMUXC_GPIO_SD_B1_07_LPSPI2_SCK 0x401F81F0U, 0x4U, 0x401F8500U, 0x0U, 0x401F83E0U #define IOMUXC_GPIO_SD_B1_07_GPIO3_IO07 0x401F81F0U, 0x5U, 0, 0, 0x401F83E0U -#define IOMUXC_GPIO_SD_B1_07_CCM_REF_EN_B 0x401F81F0U, 0x6U, 0, 0, 0x401F83E0U #define IOMUXC_GPIO_SD_B1_08_USDHC2_DATA4 0x401F81F4U, 0x0U, 0x401F85F8U, 0x0U, 0x401F83E4U #define IOMUXC_GPIO_SD_B1_08_FLEXSPIA_DATA00 0x401F81F4U, 0x1U, 0x401F84A8U, 0x0U, 0x401F83E4U @@ -1038,7 +1017,6 @@ #define IOMUXC_GPIO_SD_B1_10_LPI2C2_SDA 0x401F81FCU, 0x3U, 0x401F84D8U, 0x0U, 0x401F83ECU #define IOMUXC_GPIO_SD_B1_10_LPSPI2_PCS2 0x401F81FCU, 0x4U, 0, 0, 0x401F83ECU #define IOMUXC_GPIO_SD_B1_10_GPIO3_IO10 0x401F81FCU, 0x5U, 0, 0, 0x401F83ECU -#define IOMUXC_GPIO_SD_B1_10_SRC_SYSTEM_RESET 0x401F81FCU, 0x6U, 0, 0, 0x401F83ECU #define IOMUXC_GPIO_SD_B1_11_USDHC2_DATA7 0x401F8200U, 0x0U, 0x401F8604U, 0x0U, 0x401F83F0U #define IOMUXC_GPIO_SD_B1_11_FLEXSPIA_DATA03 0x401F8200U, 0x1U, 0x401F84B4U, 0x0U, 0x401F83F0U @@ -1046,7 +1024,6 @@ #define IOMUXC_GPIO_SD_B1_11_LPI2C2_SCL 0x401F8200U, 0x3U, 0x401F84D4U, 0x0U, 0x401F83F0U #define IOMUXC_GPIO_SD_B1_11_LPSPI2_PCS3 0x401F8200U, 0x4U, 0, 0, 0x401F83F0U #define IOMUXC_GPIO_SD_B1_11_GPIO3_IO11 0x401F8200U, 0x5U, 0, 0, 0x401F83F0U -#define IOMUXC_GPIO_SD_B1_11_SRC_EARLY_RESET 0x401F8200U, 0x6U, 0, 0, 0x401F83F0U #define IOMUXC_GPR_SAIMCLK_LOWBITMASK (0x7U) #define IOMUXC_GPR_SAIMCLK_HIGHBITMASK (0x3U) @@ -1062,16 +1039,16 @@ typedef enum _iomuxc_gpr_mode kIOMUXC_GPR_SAI3MClkOutputDir = IOMUXC_GPR_GPR1_SAI3_MCLK_DIR_MASK, kIOMUXC_GPR_ExcMonitorSlavErrResponse = IOMUXC_GPR_GPR1_EXC_MON_MASK, kIOMUXC_GPR_ENETIpgClkOn = IOMUXC_GPR_GPR1_ENET_IPG_CLK_S_EN_MASK, - kIOMUXC_GPR_AHBClockEnable = IOMUXC_GPR_GPR1_CM7_FORCE_HCLK_EN_MASK, -} iomuxc_gpr_mode_t; + kIOMUXC_GPR_AHBClockEnable = (int)IOMUXC_GPR_GPR1_CM7_FORCE_HCLK_EN_MASK, +} iomuxc_gpr_mode_t; typedef enum _iomuxc_gpr_saimclk { kIOMUXC_GPR_SAI1MClk1Sel = IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL_SHIFT, kIOMUXC_GPR_SAI1MClk2Sel = IOMUXC_GPR_GPR1_SAI1_MCLK2_SEL_SHIFT, - kIOMUXC_GPR_SAI1MClk3Sel = IOMUXC_GPR_GPR1_SAI1_MCLK3_SEL_SHIFT, - kIOMUXC_GPR_SAI2MClk3Sel = IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL_SHIFT, - kIOMUXC_GPR_SAI3MClk3Sel = IOMUXC_GPR_GPR1_SAI3_MCLK3_SEL_SHIFT, + kIOMUXC_GPR_SAI1MClk3Sel = IOMUXC_GPR_GPR1_SAI1_MCLK3_SEL_SHIFT, + kIOMUXC_GPR_SAI2MClk3Sel = IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL_SHIFT, + kIOMUXC_GPR_SAI3MClk3Sel = IOMUXC_GPR_GPR1_SAI3_MCLK3_SEL_SHIFT, } iomuxc_gpr_saimclk_t; typedef enum _iomuxc_mqs_pwm_oversample_rate @@ -1164,11 +1141,13 @@ static inline void IOMUXC_SetPinConfig(uint32_t muxRegister, */ static inline void IOMUXC_EnableMode(IOMUXC_GPR_Type *base, uint32_t mode, bool enable) { - uint32_t gpr = base->GPR1 & 0xFFF; + mode &= ~(IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL_MASK | IOMUXC_GPR_GPR1_SAI1_MCLK2_SEL_MASK | + IOMUXC_GPR_GPR1_SAI1_MCLK3_SEL_MASK | IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL_MASK | + IOMUXC_GPR_GPR1_SAI3_MCLK3_SEL_MASK); if (enable) { - base->GPR1 = mode | gpr; + base->GPR1 |= mode; } else { @@ -1190,17 +1169,17 @@ static inline void IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR_Type *base, iomuxc_gp if (mclk > kIOMUXC_GPR_SAI1MClk2Sel) { gpr = base->GPR1 & ~(IOMUXC_GPR_SAIMCLK_HIGHBITMASK << mclk); - base->GPR1 = ((clkSrc & IOMUXC_GPR_SAIMCLK_HIGHBITMASK) << mclk) | gpr; + base->GPR1 = ((clkSrc & IOMUXC_GPR_SAIMCLK_HIGHBITMASK) << mclk) | gpr; } else { gpr = base->GPR1 & ~(IOMUXC_GPR_SAIMCLK_LOWBITMASK << mclk); - base->GPR1 = ((clkSrc & IOMUXC_GPR_SAIMCLK_LOWBITMASK) << mclk) | gpr; + base->GPR1 = ((clkSrc & IOMUXC_GPR_SAIMCLK_LOWBITMASK) << mclk) | gpr; } } /*! - * @brief Enters or exit MQS software reset. + * @brief Enters or exit MQS software reset. * * @param base The IOMUXC GPR base address. * @param enable Enter or exit MQS software reset. @@ -1209,17 +1188,16 @@ static inline void IOMUXC_MQSEnterSoftwareReset(IOMUXC_GPR_Type *base, bool enab { if (enable) { - base->GPR2 |= IOMUXC_GPR_GPR2_MQS_SW_RST_MASK; + base->GPR2 |= IOMUXC_GPR_GPR2_MQS_SW_RST_MASK; } else { - base->GPR2 &= ~IOMUXC_GPR_GPR2_MQS_SW_RST_MASK; + base->GPR2 &= ~IOMUXC_GPR_GPR2_MQS_SW_RST_MASK; } } - /*! - * @brief Enables or disables MQS. + * @brief Enables or disables MQS. * * @param base The IOMUXC GPR base address. * @param enable Enable or disable the MQS. @@ -1228,16 +1206,16 @@ static inline void IOMUXC_MQSEnable(IOMUXC_GPR_Type *base, bool enable) { if (enable) { - base->GPR2 |= IOMUXC_GPR_GPR2_MQS_EN_MASK; + base->GPR2 |= IOMUXC_GPR_GPR2_MQS_EN_MASK; } else { - base->GPR2 &= ~IOMUXC_GPR_GPR2_MQS_EN_MASK; + base->GPR2 &= ~IOMUXC_GPR_GPR2_MQS_EN_MASK; } } /*! - * @brief Configure MQS PWM oversampling rate compared with mclk and divider ratio control for mclk from hmclk. + * @brief Configure MQS PWM oversampling rate compared with mclk and divider ratio control for mclk from hmclk. * * @param base The IOMUXC GPR base address. * @param rate The MQS PWM oversampling rate, refer to "iomuxc_mqs_pwm_oversample_rate_t". @@ -1247,7 +1225,7 @@ static inline void IOMUXC_MQSEnable(IOMUXC_GPR_Type *base, bool enable) static inline void IOMUXC_MQSConfig(IOMUXC_GPR_Type *base, iomuxc_mqs_pwm_oversample_rate_t rate, uint8_t divider) { uint32_t gpr = base->GPR2 & ~(IOMUXC_GPR_GPR2_MQS_OVERSAMPLE_MASK | IOMUXC_GPR_GPR2_MQS_CLK_DIV_MASK); - + base->GPR2 = gpr | IOMUXC_GPR_GPR2_MQS_OVERSAMPLE(rate) | IOMUXC_GPR_GPR2_MQS_CLK_DIV(divider); } @@ -1260,4 +1238,3 @@ static inline void IOMUXC_MQSConfig(IOMUXC_GPR_Type *base, iomuxc_mqs_pwm_oversa /*! @}*/ #endif /* _FSL_IOMUXC_H_ */ - diff --git a/ext/hal/nxp/mcux/devices/MIMXRT1052/system_MIMXRT1052.c b/ext/hal/nxp/mcux/devices/MIMXRT1052/system_MIMXRT1052.c index f505e8ec9da..e5b034d158e 100644 --- a/ext/hal/nxp/mcux/devices/MIMXRT1052/system_MIMXRT1052.c +++ b/ext/hal/nxp/mcux/devices/MIMXRT1052/system_MIMXRT1052.c @@ -1,17 +1,19 @@ /* ** ################################################################### -** Processors: MIMXRT1052CVL5A -** MIMXRT1052DVL6A +** Processors: MIMXRT1052CVJ5B +** MIMXRT1052CVL5B +** MIMXRT1052DVJ6B +** MIMXRT1052DVL6B ** -** Compilers: Keil ARM C/C++ Compiler -** Freescale C/C++ for Embedded ARM +** Compilers: Freescale C/C++ for Embedded ARM ** GNU C Compiler ** IAR ANSI C/C++ Compiler for ARM +** Keil ARM C/C++ Compiler ** MCUXpresso Compiler ** -** Reference manual: IMXRT1050RM Rev.C, 08/2017 -** Version: rev. 0.1, 2017-01-10 -** Build: b170927 +** Reference manual: IMXRT1050RM Rev.2.1, 12/2018 +** Version: rev. 1.2, 2018-11-27 +** Build: b181205 ** ** Abstract: ** Provides a system configuration function and a global variable that @@ -19,31 +21,10 @@ ** the oscillator (PLL) that is part of the microcontroller device. ** ** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2017 NXP -** Redistribution and use in source and binary forms, with or without modification, -** are permitted provided that the following conditions are met: +** Copyright 2016-2018 NXP +** All rights reserved. ** -** 1. Redistributions of source code must retain the above copyright notice, this list -** of conditions and the following disclaimer. -** -** 2. Redistributions in binary form must reproduce the above copyright notice, this -** list of conditions and the following disclaimer in the documentation and/or -** other materials provided with the distribution. -** -** 3. Neither the name of the copyright holder nor the names of its -** contributors may be used to endorse or promote products derived from this -** software without specific prior written permission. -** -** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** SPDX-License-Identifier: BSD-3-Clause ** ** http: www.nxp.com ** mail: support@nxp.com @@ -51,14 +32,22 @@ ** Revisions: ** - rev. 0.1 (2017-01-10) ** Initial version. +** - rev. 1.0 (2018-09-21) +** Update interrupt vector table and dma request source. +** Update register BEE_ADDR_OFFSET1's bitfield name to ADDR_OFFSET1. +** Split GPIO_COMBINED_IRQS to GPIO_COMBINED_LOW_IRQS and GPIO_COMBINED_HIGH_IRQS. +** - rev. 1.1 (2018-11-16) +** Update header files to align with IMXRT1050RM Rev.1. +** - rev. 1.2 (2018-11-27) +** Update header files to align with IMXRT1050RM Rev.2.1. ** ** ################################################################### */ /*! * @file MIMXRT1052 - * @version 0.1 - * @date 2017-01-10 + * @version 1.2 + * @date 2018-11-27 * @brief Device specific configuration file for MIMXRT1052 (implementation file) * * Provides a system configuration function and a global variable that contains @@ -86,6 +75,15 @@ void SystemInit (void) { SCB->CPACR |= ((3UL << 10*2) | (3UL << 11*2)); /* set CP10, CP11 Full Access */ #endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */ +#if defined(__MCUXPRESSO) + extern uint32_t g_pfnVectors[]; // Vector table defined in startup code + SCB->VTOR = (uint32_t)g_pfnVectors; +#endif + +/* Disable Watchdog Power Down Counter */ +WDOG1->WMCR &= ~WDOG_WMCR_PDE_MASK; +WDOG2->WMCR &= ~WDOG_WMCR_PDE_MASK; + /* Watchdog disable */ #if (DISABLE_WDOG) @@ -110,12 +108,17 @@ void SystemInit (void) { /* Enable instruction and data caches */ #if defined(__ICACHE_PRESENT) && __ICACHE_PRESENT - SCB_EnableICache(); + if (SCB_CCR_IC_Msk != (SCB_CCR_IC_Msk & SCB->CCR)) { + SCB_EnableICache(); + } #endif #if defined(__DCACHE_PRESENT) && __DCACHE_PRESENT - SCB_EnableDCache(); + if (SCB_CCR_DC_Msk != (SCB_CCR_DC_Msk & SCB->CCR)) { + SCB_EnableDCache(); + } #endif + SystemInitHook(); } /* ---------------------------------------------------------------------------- @@ -135,15 +138,26 @@ void SystemCoreClockUpdate (void) { { /* Pll3_sw_clk ---> Periph_clk2_clk ---> Periph_clk */ case CCM_CBCMR_PERIPH_CLK2_SEL(0U): - freq = (24000000UL * ((CCM_ANALOG->PLL_USB1 & CCM_ANALOG_PLL_USB1_DIV_SELECT_MASK) ? 22U : 20U)); + if(CCM_ANALOG->PLL_USB1 & CCM_ANALOG_PLL_USB1_BYPASS_MASK) + { + freq = (((CCM_ANALOG->PLL_USB1 & CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_MASK) >> CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_SHIFT) == 0U) ? + CPU_XTAL_CLK_HZ : CPU_CLK1_HZ; + } + else + { + freq = (CPU_XTAL_CLK_HZ * ((CCM_ANALOG->PLL_USB1 & CCM_ANALOG_PLL_USB1_DIV_SELECT_MASK) ? 22U : 20U)); + } break; /* Osc_clk ---> Periph_clk2_clk ---> Periph_clk */ case CCM_CBCMR_PERIPH_CLK2_SEL(1U): - freq = 24000000UL; + freq = CPU_XTAL_CLK_HZ; break; case CCM_CBCMR_PERIPH_CLK2_SEL(2U): + freq = (((CCM_ANALOG->PLL_SYS & CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_MASK) >> CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_SHIFT) == 0U) ? + CPU_XTAL_CLK_HZ : CPU_CLK1_HZ; + case CCM_CBCMR_PERIPH_CLK2_SEL(3U): default: freq = 0U; @@ -155,11 +169,29 @@ void SystemCoreClockUpdate (void) { /* Pre_Periph_clk ---> Periph_clk */ else { - PLL1MainClock = ((24000000UL * ((CCM_ANALOG->PLL_ARM & CCM_ANALOG_PLL_ARM_DIV_SELECT_MASK) >> - CCM_ANALOG_PLL_ARM_DIV_SELECT_SHIFT)) >> 1U); + /* check if pll is bypassed */ + if(CCM_ANALOG->PLL_ARM & CCM_ANALOG_PLL_ARM_BYPASS_MASK) + { + PLL1MainClock = (((CCM_ANALOG->PLL_ARM & CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_MASK) >> CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_SHIFT) == 0U) ? + CPU_XTAL_CLK_HZ : CPU_CLK1_HZ; + } + else + { + PLL1MainClock = ((CPU_XTAL_CLK_HZ * ((CCM_ANALOG->PLL_ARM & CCM_ANALOG_PLL_ARM_DIV_SELECT_MASK) >> + CCM_ANALOG_PLL_ARM_DIV_SELECT_SHIFT)) >> 1U); + } - PLL2MainClock = (24000000UL * ((CCM_ANALOG->PLL_SYS & CCM_ANALOG_PLL_SYS_DIV_SELECT_MASK) ? 22U : 20U)); - PLL2MainClock += ((uint64_t)24000000UL * ((uint64_t)(CCM_ANALOG->PLL_SYS_NUM))) / ((uint64_t)(CCM_ANALOG->PLL_SYS_DENOM)); + /* check if pll is bypassed */ + if(CCM_ANALOG->PLL_SYS & CCM_ANALOG_PLL_SYS_BYPASS_MASK) + { + PLL2MainClock = (((CCM_ANALOG->PLL_SYS & CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_MASK) >> CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_SHIFT) == 0U) ? + CPU_XTAL_CLK_HZ : CPU_CLK1_HZ; + } + else + { + PLL2MainClock = (CPU_XTAL_CLK_HZ * ((CCM_ANALOG->PLL_SYS & CCM_ANALOG_PLL_SYS_DIV_SELECT_MASK) ? 22U : 20U)); + } + PLL2MainClock += ((uint64_t)CPU_XTAL_CLK_HZ * ((uint64_t)(CCM_ANALOG->PLL_SYS_NUM))) / ((uint64_t)(CCM_ANALOG->PLL_SYS_DENOM)); switch (CCM->CBCMR & CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK) @@ -193,3 +225,11 @@ void SystemCoreClockUpdate (void) { SystemCoreClock = (freq / (((CCM->CBCDR & CCM_CBCDR_AHB_PODF_MASK) >> CCM_CBCDR_AHB_PODF_SHIFT) + 1U)); } + +/* ---------------------------------------------------------------------------- + -- SystemInitHook() + ---------------------------------------------------------------------------- */ + +__attribute__ ((weak)) void SystemInitHook (void) { + /* Void implementation of the weak function. */ +} diff --git a/ext/hal/nxp/mcux/devices/MIMXRT1052/system_MIMXRT1052.h b/ext/hal/nxp/mcux/devices/MIMXRT1052/system_MIMXRT1052.h index 2a559acf31a..74941f9fbda 100644 --- a/ext/hal/nxp/mcux/devices/MIMXRT1052/system_MIMXRT1052.h +++ b/ext/hal/nxp/mcux/devices/MIMXRT1052/system_MIMXRT1052.h @@ -1,17 +1,19 @@ /* ** ################################################################### -** Processors: MIMXRT1052CVL5A -** MIMXRT1052DVL6A +** Processors: MIMXRT1052CVJ5B +** MIMXRT1052CVL5B +** MIMXRT1052DVJ6B +** MIMXRT1052DVL6B ** -** Compilers: Keil ARM C/C++ Compiler -** Freescale C/C++ for Embedded ARM +** Compilers: Freescale C/C++ for Embedded ARM ** GNU C Compiler ** IAR ANSI C/C++ Compiler for ARM +** Keil ARM C/C++ Compiler ** MCUXpresso Compiler ** -** Reference manual: IMXRT1050RM Rev.C, 08/2017 -** Version: rev. 0.1, 2017-01-10 -** Build: b170927 +** Reference manual: IMXRT1050RM Rev.2.1, 12/2018 +** Version: rev. 1.2, 2018-11-27 +** Build: b181205 ** ** Abstract: ** Provides a system configuration function and a global variable that @@ -19,31 +21,10 @@ ** the oscillator (PLL) that is part of the microcontroller device. ** ** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2017 NXP -** Redistribution and use in source and binary forms, with or without modification, -** are permitted provided that the following conditions are met: +** Copyright 2016-2018 NXP +** All rights reserved. ** -** 1. Redistributions of source code must retain the above copyright notice, this list -** of conditions and the following disclaimer. -** -** 2. Redistributions in binary form must reproduce the above copyright notice, this -** list of conditions and the following disclaimer in the documentation and/or -** other materials provided with the distribution. -** -** 3. Neither the name of the copyright holder nor the names of its -** contributors may be used to endorse or promote products derived from this -** software without specific prior written permission. -** -** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** SPDX-License-Identifier: BSD-3-Clause ** ** http: www.nxp.com ** mail: support@nxp.com @@ -51,14 +32,22 @@ ** Revisions: ** - rev. 0.1 (2017-01-10) ** Initial version. +** - rev. 1.0 (2018-09-21) +** Update interrupt vector table and dma request source. +** Update register BEE_ADDR_OFFSET1's bitfield name to ADDR_OFFSET1. +** Split GPIO_COMBINED_IRQS to GPIO_COMBINED_LOW_IRQS and GPIO_COMBINED_HIGH_IRQS. +** - rev. 1.1 (2018-11-16) +** Update header files to align with IMXRT1050RM Rev.1. +** - rev. 1.2 (2018-11-27) +** Update header files to align with IMXRT1050RM Rev.2.1. ** ** ################################################################### */ /*! * @file MIMXRT1052 - * @version 0.1 - * @date 2017-01-10 + * @version 1.2 + * @date 2018-11-27 * @brief Device specific configuration file for MIMXRT1052 (header file) * * Provides a system configuration function and a global variable that contains @@ -84,6 +73,9 @@ extern "C" { #define CPU_XTAL_CLK_HZ 24000000UL /* Value of the external crystal or oscillator clock frequency in Hz */ +#define CPU_CLK1_HZ 0UL /* Value of the CLK1 (select the CLK1_N/CLK1_P as source) frequency in Hz */ + /* If CLOCK1_P,CLOCK1_N is choose as the pll bypass clock source, please implement the CLKPN_FREQ define, otherwise 0 will be returned. */ + #define DEFAULT_SYSTEM_CLOCK 528000000UL /* Default System clock value */ @@ -116,6 +108,18 @@ void SystemInit (void); */ void SystemCoreClockUpdate (void); +/** + * @brief SystemInit function hook. + * + * This weak function allows to call specific initialization code during the + * SystemInit() execution.This can be used when an application specific code needs + * to be called as close to the reset entry as possible (for example the Multicore + * Manager MCMGR_EarlyInit() function call). + * NOTE: No global r/w variables can be used in this hook function because the + * initialization of these variables happens after this function. + */ +void SystemInitHook (void); + #ifdef __cplusplus } #endif diff --git a/ext/hal/nxp/mcux/devices/MIMXRT1061/MIMXRT1061.h b/ext/hal/nxp/mcux/devices/MIMXRT1061/MIMXRT1061.h index be24f8dd3e3..88938b4ce11 100644 --- a/ext/hal/nxp/mcux/devices/MIMXRT1061/MIMXRT1061.h +++ b/ext/hal/nxp/mcux/devices/MIMXRT1061/MIMXRT1061.h @@ -4,21 +4,22 @@ ** MIMXRT1061CVL5A ** MIMXRT1061DVL6A ** -** Compilers: Keil ARM C/C++ Compiler -** Freescale C/C++ for Embedded ARM +** Compilers: Freescale C/C++ for Embedded ARM ** GNU C Compiler ** IAR ANSI C/C++ Compiler for ARM +** Keil ARM C/C++ Compiler ** MCUXpresso Compiler ** -** Reference manual: IMXRT1060RM Rev. 0, 08/2018 -** Version: rev. 0.1, 2017-01-10 -** Build: b180819 +** Reference manual: IMXRT1060RM Rev.1, 12/2018 +** Version: rev. 1.1, 2018-11-27 +** Build: b181127 ** ** Abstract: ** CMSIS Peripheral Access Layer for MIMXRT1061 ** ** Copyright 1997-2016 Freescale Semiconductor, Inc. ** Copyright 2016-2018 NXP +** All rights reserved. ** ** SPDX-License-Identifier: BSD-3-Clause ** @@ -28,14 +29,18 @@ ** Revisions: ** - rev. 0.1 (2017-01-10) ** Initial version. +** - rev. 1.0 (2018-11-16) +** Update header files to align with IMXRT1060RM Rev.0. +** - rev. 1.1 (2018-11-27) +** Update header files to align with IMXRT1060RM Rev.1. ** ** ################################################################### */ /*! * @file MIMXRT1061.h - * @version 0.1 - * @date 2017-01-10 + * @version 1.1 + * @date 2018-11-27 * @brief CMSIS Peripheral Access Layer for MIMXRT1061 * * CMSIS Peripheral Access Layer for MIMXRT1061 @@ -46,7 +51,7 @@ /** Memory map major version (memory maps with equal major version number are * compatible) */ -#define MCU_MEM_MAP_VERSION 0x0000U +#define MCU_MEM_MAP_VERSION 0x0100U /** Memory map minor version */ #define MCU_MEM_MAP_VERSION_MINOR 0x0001U @@ -297,8 +302,8 @@ typedef enum IRQn { */ typedef enum _dma_request_source { - kDmaRequestMuxFlexIO1Request0Request1 = 0|0x100U, /**< FlexIO1 */ - kDmaRequestMuxFlexIO2Request0Request1 = 1|0x100U, /**< FlexIO2 */ + kDmaRequestMuxFlexIO1Request0Request1 = 0|0x100U, /**< FlexIO1 Request0 and Request1 */ + kDmaRequestMuxFlexIO2Request0Request1 = 1|0x100U, /**< FlexIO2 Request0 and Request1 */ kDmaRequestMuxLPUART1Tx = 2|0x100U, /**< LPUART1 Transmit */ kDmaRequestMuxLPUART1Rx = 3|0x100U, /**< LPUART1 Receive */ kDmaRequestMuxLPUART3Tx = 4|0x100U, /**< LPUART3 Transmit */ @@ -356,8 +361,8 @@ typedef enum _dma_request_source kDmaRequestMuxQTIMER3CaptTimer3Cmpld1Timer3Cmpld2Timer2 = 59|0x100U, /**< QTIMER3 capture timer 3, cmpld1 in timer 3 or cmpld2 in timer 2 */ kDmaRequestMuxFlexSPI2Rx = 60|0x100U, /**< FlexSPI2 Receive */ kDmaRequestMuxFlexSPI2Tx = 61|0x100U, /**< FlexSPI2 Transmit */ - kDmaRequestMuxFlexIO1Request2Request3 = 64|0x100U, /**< FlexIO1 */ - kDmaRequestMuxFlexIO2Request2Request3 = 65|0x100U, /**< FlexIO2 */ + kDmaRequestMuxFlexIO1Request2Request3 = 64|0x100U, /**< FlexIO1 Request2 and Request3 */ + kDmaRequestMuxFlexIO2Request2Request3 = 65|0x100U, /**< FlexIO2 Request2 and Request3 */ kDmaRequestMuxLPUART2Tx = 66|0x100U, /**< LPUART2 Transmit */ kDmaRequestMuxLPUART2Rx = 67|0x100U, /**< LPUART2 Receive */ kDmaRequestMuxLPUART4Tx = 68|0x100U, /**< LPUART4 Transmit */ @@ -3250,7 +3255,10 @@ typedef struct { __IO uint32_t RXFGMASK; /**< Rx FIFO Global Mask Register..Legacy Rx FIFO Global Mask register, offset: 0x48 */ __I uint32_t RXFIR; /**< Rx FIFO Information Register..Legacy Rx FIFO Information Register, offset: 0x4C */ __IO uint32_t CBT; /**< CAN Bit Timing Register, offset: 0x50 */ - uint8_t RESERVED_2[44]; + uint8_t RESERVED_2[4]; + __I uint32_t DBG1; /**< Debug 1 register, offset: 0x58 */ + __I uint32_t DBG2; /**< Debug 2 register, offset: 0x5C */ + uint8_t RESERVED_3[32]; union { /* offset: 0x80 */ struct { /* offset: 0x80, array step: 0x18 */ __IO uint32_t CS; /**< Message Buffer 0 CS Register..Message Buffer 41 CS Register, array offset: 0x80, array step: 0x18 */ @@ -3279,11 +3287,11 @@ typedef struct { __IO uint32_t WORD1; /**< Message Buffer 0 WORD1 Register..Message Buffer 63 WORD1 Register, array offset: 0x8C, array step: 0x10 */ } MB[64]; }; - uint8_t RESERVED_3[1024]; + uint8_t RESERVED_4[1024]; __IO uint32_t RXIMR[64]; /**< Rx Individual Mask Registers, array offset: 0x880, array step: 0x4 */ - uint8_t RESERVED_4[96]; + uint8_t RESERVED_5[96]; __IO uint32_t GFWR; /**< Glitch Filter Width Registers, offset: 0x9E0 */ - uint8_t RESERVED_5[524]; + uint8_t RESERVED_6[524]; __IO uint32_t EPRS; /**< Enhanced CAN Bit Timing Prescalers, offset: 0xBF0 */ __IO uint32_t ENCBT; /**< Enhanced Nominal CAN Bit Timing, offset: 0xBF4 */ __IO uint32_t EDCBT; /**< Enhanced Data Phase CAN bit Timing, offset: 0xBF8 */ @@ -3294,9 +3302,9 @@ typedef struct { __IO uint32_t ERFCR; /**< Enhanced Rx FIFO Control Register, offset: 0xC0C */ __IO uint32_t ERFIER; /**< Enhanced Rx FIFO Interrupt Enable register, offset: 0xC10 */ __IO uint32_t ERFSR; /**< Enhanced Rx FIFO Status Register, offset: 0xC14 */ - uint8_t RESERVED_6[24]; + uint8_t RESERVED_7[24]; __I uint32_t HR_TIME_STAMP[64]; /**< High Resolution Time Stamp, array offset: 0xC30, array step: 0x4 */ - uint8_t RESERVED_7[8912]; + uint8_t RESERVED_8[8912]; __IO uint32_t ERFFEL[128]; /**< Enhanced Rx FIFO Filter Element, array offset: 0x3000, array step: 0x4 */ } CAN_Type; @@ -3375,15 +3383,15 @@ typedef struct { #define CAN_MCR_WAKSRC_MASK (0x80000U) #define CAN_MCR_WAKSRC_SHIFT (19U) /*! WAKSRC - Wake Up Source - * 0b0..FlexCAN uses the unfiltered Rx input to detect recessive to dominant edges on the CAN bus. - * 0b1..FlexCAN uses the filtered Rx input to detect recessive to dominant edges on the CAN bus. + * 0b1..FLEXCAN uses the filtered FLEXCAN_RX input to detect recessive to dominant edges on the CAN bus + * 0b0..FLEXCAN uses the unfiltered FLEXCAN_RX input to detect recessive to dominant edges on the CAN bus. */ #define CAN_MCR_WAKSRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WAKSRC_SHIFT)) & CAN_MCR_WAKSRC_MASK) #define CAN_MCR_LPMACK_MASK (0x100000U) #define CAN_MCR_LPMACK_SHIFT (20U) /*! LPMACK - Low-Power Mode Acknowledge - * 0b0..FlexCAN is not in a low-power mode. - * 0b1..FlexCAN is in a low-power mode. + * 0b1..FLEXCAN is either in Disable Mode, or Stop mode + * 0b0..FLEXCAN not in any of the low power modes */ #define CAN_MCR_LPMACK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_LPMACK_SHIFT)) & CAN_MCR_LPMACK_MASK) #define CAN_MCR_WRNEN_MASK (0x200000U) @@ -3402,6 +3410,10 @@ typedef struct { #define CAN_MCR_SLFWAK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SLFWAK_SHIFT)) & CAN_MCR_SLFWAK_MASK) #define CAN_MCR_SUPV_MASK (0x800000U) #define CAN_MCR_SUPV_SHIFT (23U) +/*! SUPV - Supervisor Mode + * 0b1..FlexCAN is in Supervisor Mode. Affected registers allow only Supervisor access. Unrestricted access behaves as though the access was done to an unimplemented register location + * 0b0..FlexCAN is in User Mode. Affected registers allow both Supervisor and Unrestricted accesses + */ #define CAN_MCR_SUPV(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SUPV_SHIFT)) & CAN_MCR_SUPV_MASK) #define CAN_MCR_FRZACK_MASK (0x1000000U) #define CAN_MCR_FRZACK_SHIFT (24U) @@ -3427,7 +3439,8 @@ typedef struct { #define CAN_MCR_NOTRDY_MASK (0x8000000U) #define CAN_MCR_NOTRDY_SHIFT (27U) /*! NOTRDY - FlexCAN Not Ready - * 0b0..FlexCAN module is either in Normal mode, Listen-Only mode or Loop-Back mode. + * 0b1..FLEXCAN module is either in Disable Mode, Stop Mode or Freeze Mode + * 0b0..FLEXCAN module is either in Normal Mode, Listen-Only Mode or Loop-Back Mode */ #define CAN_MCR_NOTRDY(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_NOTRDY_SHIFT)) & CAN_MCR_NOTRDY_MASK) #define CAN_MCR_HALT_MASK (0x10000000U) @@ -3482,15 +3495,15 @@ typedef struct { #define CAN_CTRL1_TSYN_MASK (0x20U) #define CAN_CTRL1_TSYN_SHIFT (5U) /*! TSYN - Timer Sync - * 0b0..Timer Sync feature disabled * 0b1..Timer Sync feature enabled + * 0b0..Timer Sync feature disabled */ #define CAN_CTRL1_TSYN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_TSYN_SHIFT)) & CAN_CTRL1_TSYN_MASK) #define CAN_CTRL1_BOFFREC_MASK (0x40U) #define CAN_CTRL1_BOFFREC_SHIFT (6U) /*! BOFFREC - Bus Off Recovery - * 0b0..Automatic recovering from Bus Off state enabled. - * 0b1..Automatic recovering from Bus Off state disabled. + * 0b1..Automatic recovering from Bus Off state disabled + * 0b0..Automatic recovering from Bus Off state enabled, according to CAN Spec 2.0 part B */ #define CAN_CTRL1_BOFFREC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_BOFFREC_SHIFT)) & CAN_CTRL1_BOFFREC_MASK) #define CAN_CTRL1_SMP_MASK (0x80U) @@ -3567,6 +3580,10 @@ typedef struct { /*! @{ */ #define CAN_RXMGMASK_MG_MASK (0xFFFFFFFFU) #define CAN_RXMGMASK_MG_SHIFT (0U) +/*! MG - Rx Mailboxes Global Mask Bits + * 0b00000000000000000000000000000001..The corresponding bit in the filter is checked against the one received + * 0b00000000000000000000000000000000..the corresponding bit in the filter is "don't care" + */ #define CAN_RXMGMASK_MG(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXMGMASK_MG_SHIFT)) & CAN_RXMGMASK_MG_MASK) /*! @} */ @@ -3574,6 +3591,10 @@ typedef struct { /*! @{ */ #define CAN_RX14MASK_RX14M_MASK (0xFFFFFFFFU) #define CAN_RX14MASK_RX14M_SHIFT (0U) +/*! RX14M - Rx Buffer 14 Mask Bits + * 0b00000000000000000000000000000001..The corresponding bit in the filter is checked + * 0b00000000000000000000000000000000..the corresponding bit in the filter is "don't care" + */ #define CAN_RX14MASK_RX14M(x) (((uint32_t)(((uint32_t)(x)) << CAN_RX14MASK_RX14M_SHIFT)) & CAN_RX14MASK_RX14M_MASK) /*! @} */ @@ -3581,6 +3602,10 @@ typedef struct { /*! @{ */ #define CAN_RX15MASK_RX15M_MASK (0xFFFFFFFFU) #define CAN_RX15MASK_RX15M_SHIFT (0U) +/*! RX15M - Rx Buffer 15 Mask Bits + * 0b00000000000000000000000000000001..The corresponding bit in the filter is checked + * 0b00000000000000000000000000000000..the corresponding bit in the filter is "don't care" + */ #define CAN_RX15MASK_RX15M(x) (((uint32_t)(((uint32_t)(x)) << CAN_RX15MASK_RX15M_SHIFT)) & CAN_RX15MASK_RX15M_MASK) /*! @} */ @@ -3611,8 +3636,8 @@ typedef struct { #define CAN_ESR1_WAKINT_MASK (0x1U) #define CAN_ESR1_WAKINT_SHIFT (0U) /*! WAKINT - Wake-Up Interrupt - * 0b0..No such occurrence. - * 0b1..Indicates a recessive to dominant transition was received on the CAN bus. + * 0b1..Indicates a recessive to dominant transition received on the CAN bus when the FLEXCAN module is in Stop Mode + * 0b0..No such occurrence */ #define CAN_ESR1_WAKINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_WAKINT_SHIFT)) & CAN_ESR1_WAKINT_MASK) #define CAN_ESR1_ERRINT_MASK (0x2U) @@ -3641,7 +3666,7 @@ typedef struct { /*! FLTCONF - Fault Confinement State * 0b00..Error Active * 0b01..Error Passive - * 0b1x..Bus Off + * 0b1x..Bus off */ #define CAN_ESR1_FLTCONF(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FLTCONF_SHIFT)) & CAN_ESR1_FLTCONF_MASK) #define CAN_ESR1_TX_MASK (0x40U) @@ -3744,8 +3769,7 @@ typedef struct { #define CAN_ESR1_BOFFDONEINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BOFFDONEINT_SHIFT)) & CAN_ESR1_BOFFDONEINT_MASK) #define CAN_ESR1_ERRINT_FAST_MASK (0x100000U) #define CAN_ESR1_ERRINT_FAST_SHIFT (20U) -/*! ERRINT_FAST - Error Interrupt for errors detected in the Data Phase of CAN FD - frames with the BRS bit set +/*! ERRINT_FAST - Error Interrupt for errors detected in the Data Phase of CAN FD frames with the BRS bit set * 0b0..No such occurrence. * 0b1..Indicates setting of any Error Bit detected in the Data Phase of CAN FD frames with the BRS bit set. */ @@ -3759,40 +3783,35 @@ typedef struct { #define CAN_ESR1_ERROVR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ERROVR_SHIFT)) & CAN_ESR1_ERROVR_MASK) #define CAN_ESR1_STFERR_FAST_MASK (0x4000000U) #define CAN_ESR1_STFERR_FAST_SHIFT (26U) -/*! STFERR_FAST - Stuffing Error in the Data Phase of CAN FD frames with the BRS bit - set +/*! STFERR_FAST - Stuffing Error in the Data Phase of CAN FD frames with the BRS bit set * 0b0..No such occurrence. * 0b1..A Stuffing Error occurred since last read of this register. */ #define CAN_ESR1_STFERR_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_STFERR_FAST_SHIFT)) & CAN_ESR1_STFERR_FAST_MASK) #define CAN_ESR1_FRMERR_FAST_MASK (0x8000000U) #define CAN_ESR1_FRMERR_FAST_SHIFT (27U) -/*! FRMERR_FAST - Form Error in the Data Phase of CAN FD frames with the BRS bit - set +/*! FRMERR_FAST - Form Error in the Data Phase of CAN FD frames with the BRS bit set * 0b0..No such occurrence. * 0b1..A Form Error occurred since last read of this register. */ #define CAN_ESR1_FRMERR_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FRMERR_FAST_SHIFT)) & CAN_ESR1_FRMERR_FAST_MASK) #define CAN_ESR1_CRCERR_FAST_MASK (0x10000000U) #define CAN_ESR1_CRCERR_FAST_SHIFT (28U) -/*! CRCERR_FAST - Cyclic Redundancy Check Error in the CRC field of CAN FD frames with - the BRS bit set +/*! CRCERR_FAST - Cyclic Redundancy Check Error in the CRC field of CAN FD frames with the BRS bit set * 0b0..No such occurrence. * 0b1..A CRC error occurred since last read of this register. */ #define CAN_ESR1_CRCERR_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_CRCERR_FAST_SHIFT)) & CAN_ESR1_CRCERR_FAST_MASK) #define CAN_ESR1_BIT0ERR_FAST_MASK (0x40000000U) #define CAN_ESR1_BIT0ERR_FAST_SHIFT (30U) -/*! BIT0ERR_FAST - Bit0 Error in the Data Phase of CAN FD frames with the BRS bit - set +/*! BIT0ERR_FAST - Bit0 Error in the Data Phase of CAN FD frames with the BRS bit set * 0b0..No such occurrence. * 0b1..At least one bit sent as dominant is received as recessive. */ #define CAN_ESR1_BIT0ERR_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT0ERR_FAST_SHIFT)) & CAN_ESR1_BIT0ERR_FAST_MASK) #define CAN_ESR1_BIT1ERR_FAST_MASK (0x80000000U) #define CAN_ESR1_BIT1ERR_FAST_SHIFT (31U) -/*! BIT1ERR_FAST - Bit1 Error in the Data Phase of CAN FD frames with the BRS bit - set +/*! BIT1ERR_FAST - Bit1 Error in the Data Phase of CAN FD frames with the BRS bit set * 0b0..No such occurrence. * 0b1..At least one bit sent as recessive is received as dominant. */ @@ -3845,8 +3864,7 @@ typedef struct { /*! @{ */ #define CAN_IFLAG1_BUF0I_MASK (0x1U) #define CAN_IFLAG1_BUF0I_SHIFT (0U) -/*! BUF0I - Buffer MB0 Interrupt Or Clear Legacy - FIFO bit +/*! BUF0I - Buffer MB0 Interrupt Or Clear Legacy FIFO bit * 0b0..The corresponding buffer has no occurrence of successfully completed transmission or reception when CAN_MCR[RFEN]=0. * 0b1..The corresponding buffer has successfully completed transmission or reception when CAN_MCR[RFEN]=0. */ @@ -3863,29 +3881,31 @@ typedef struct { #define CAN_IFLAG1_BUF4TO1I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF4TO1I_SHIFT)) & CAN_IFLAG1_BUF4TO1I_MASK) #define CAN_IFLAG1_BUF5I_MASK (0x20U) #define CAN_IFLAG1_BUF5I_SHIFT (5U) -/*! BUF5I - Buffer MB5 Interrupt Or "Frames available in Legacy Rx FIFO" +/*! BUF5I - Buffer MB5 Interrupt Or "Frames available in Legacy Rx FIFO" * 0b0..No occurrence of MB5 completing transmission/reception when CAN_MCR[RFEN]=0, or of frame(s) available in the Legacy FIFO, when CAN_MCR[RFEN]=1 * 0b1..MB5 completed transmission/reception when CAN_MCR[RFEN]=0, or frame(s) available in the Legacy Rx FIFO when CAN_MCR[RFEN]=1. It generates a DMA request in case of CAN_MCR[RFEN] and CAN_MCR[DMA] are enabled. */ #define CAN_IFLAG1_BUF5I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF5I_SHIFT)) & CAN_IFLAG1_BUF5I_MASK) #define CAN_IFLAG1_BUF6I_MASK (0x40U) #define CAN_IFLAG1_BUF6I_SHIFT (6U) -/*! BUF6I - Buffer MB6 Interrupt Or "Legacy Rx - FIFO Warning" +/*! BUF6I - Buffer MB6 Interrupt Or "Legacy Rx FIFO Warning" * 0b0..No occurrence of MB6 completing transmission/reception when CAN_MCR[RFEN]=0, or of Legacy Rx FIFO almost full when CAN_MCR[RFEN]=1 * 0b1..MB6 completed transmission/reception when CAN_MCR[RFEN]=0, or Legacy Rx FIFO almost full when CAN_MCR[RFEN]=1 */ #define CAN_IFLAG1_BUF6I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF6I_SHIFT)) & CAN_IFLAG1_BUF6I_MASK) #define CAN_IFLAG1_BUF7I_MASK (0x80U) #define CAN_IFLAG1_BUF7I_SHIFT (7U) -/*! BUF7I - Buffer MB7 Interrupt Or "Legacy Rx - FIFO Overflow" +/*! BUF7I - Buffer MB7 Interrupt Or "Legacy Rx FIFO Overflow" * 0b0..No occurrence of MB7 completing transmission/reception when CAN_MCR[RFEN]=0, or of Legacy Rx FIFO overflow when CAN_MCR[RFEN]=1 * 0b1..MB7 completed transmission/reception when CAN_MCR[RFEN]=0, or Legacy Rx FIFO overflow when CAN_MCR[RFEN]=1 */ #define CAN_IFLAG1_BUF7I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF7I_SHIFT)) & CAN_IFLAG1_BUF7I_MASK) #define CAN_IFLAG1_BUF31TO8I_MASK (0xFFFFFF00U) #define CAN_IFLAG1_BUF31TO8I_SHIFT (8U) +/*! BUF31TO8I - Buffer MBi Interrupt + * 0b000000000000000000000001..The corresponding MB has successfully completed transmission or reception + * 0b000000000000000000000000..No such occurrence + */ #define CAN_IFLAG1_BUF31TO8I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF31TO8I_SHIFT)) & CAN_IFLAG1_BUF31TO8I_MASK) /*! @} */ @@ -3893,7 +3913,7 @@ typedef struct { /*! @{ */ #define CAN_CTRL2_TSTAMPCAP_MASK (0xC0U) #define CAN_CTRL2_TSTAMPCAP_SHIFT (6U) -/*! TSTAMPCAP - Time Stamp Capture Point +/*! TSTAMPCAP - Time Stamp Capture Point * 0b00..The high resolution time stamp capture is disabled * 0b01..The high resolution time stamp is captured in the end of the CAN frame * 0b10..The high resolution time stamp is captured in the start of the CAN frame @@ -3902,7 +3922,7 @@ typedef struct { #define CAN_CTRL2_TSTAMPCAP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_TSTAMPCAP_SHIFT)) & CAN_CTRL2_TSTAMPCAP_MASK) #define CAN_CTRL2_MBTSBASE_MASK (0x300U) #define CAN_CTRL2_MBTSBASE_SHIFT (8U) -/*! MBTSBASE - Message Buffer Time Stamp Base +/*! MBTSBASE - Message Buffer Time Stamp Base * 0b00..Message Buffer Time Stamp base is CAN_TIMER * 0b01..Message Buffer Time Stamp base is lower 16-bits of high resolution timer * 0b10..Message Buffer Time Stamp base is upper 16-bits of high resolution timerT @@ -3925,7 +3945,7 @@ typedef struct { #define CAN_CTRL2_ISOCANFDEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_ISOCANFDEN_SHIFT)) & CAN_CTRL2_ISOCANFDEN_MASK) #define CAN_CTRL2_BTE_MASK (0x2000U) #define CAN_CTRL2_BTE_SHIFT (13U) -/*! BTE - Bit Timing Expansion enable +/*! BTE - Bit Timing Expansion enable * 0b0..CAN Bit timing expansion is disabled. * 0b1..CAN bit timing expansion is enabled. */ @@ -3946,8 +3966,7 @@ typedef struct { #define CAN_CTRL2_TIMER_SRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_TIMER_SRC_SHIFT)) & CAN_CTRL2_TIMER_SRC_MASK) #define CAN_CTRL2_EACEN_MASK (0x10000U) #define CAN_CTRL2_EACEN_SHIFT (16U) -/*! EACEN - Entire Frame Arbitration Field Comparison Enable For Rx - Mailboxes +/*! EACEN - Entire Frame Arbitration Field Comparison Enable For Rx Mailboxes * 0b0..Rx Mailbox filter's IDE bit is always compared and RTR is never compared despite mask bits. * 0b1..Enables the comparison of both Rx Mailbox filter's IDE and RTR bit with their corresponding bits within the incoming frame. Mask bits do apply. */ @@ -3988,8 +4007,7 @@ typedef struct { #define CAN_CTRL2_BOFFDONEMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_BOFFDONEMSK_SHIFT)) & CAN_CTRL2_BOFFDONEMSK_MASK) #define CAN_CTRL2_ERRMSK_FAST_MASK (0x80000000U) #define CAN_CTRL2_ERRMSK_FAST_SHIFT (31U) -/*! ERRMSK_FAST - Error Interrupt Mask for errors detected in the Data Phase of fast - CAN FD frames +/*! ERRMSK_FAST - Error Interrupt Mask for errors detected in the Data Phase of fast CAN FD frames * 0b0..ERRINT_FAST Error interrupt disabled. * 0b1..ERRINT_FAST Error interrupt enabled. */ @@ -4031,6 +4049,10 @@ typedef struct { /*! @{ */ #define CAN_RXFGMASK_FGM_MASK (0xFFFFFFFFU) #define CAN_RXFGMASK_FGM_SHIFT (0U) +/*! FGM - Legacy Rx FIFO Global Mask Bits + * 0b00000000000000000000000000000001..The corresponding bit in the filter is checked + * 0b00000000000000000000000000000000..The corresponding bit in the filter is "don't care" + */ #define CAN_RXFGMASK_FGM(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXFGMASK_FGM_SHIFT)) & CAN_RXFGMASK_FGM_MASK) /*! @} */ @@ -4067,6 +4089,40 @@ typedef struct { #define CAN_CBT_BTF(x) (((uint32_t)(((uint32_t)(x)) << CAN_CBT_BTF_SHIFT)) & CAN_CBT_BTF_MASK) /*! @} */ +/*! @name DBG1 - Debug 1 register */ +/*! @{ */ +#define CAN_DBG1_CFSM_MASK (0x3FU) +#define CAN_DBG1_CFSM_SHIFT (0U) +#define CAN_DBG1_CFSM(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBG1_CFSM_SHIFT)) & CAN_DBG1_CFSM_MASK) +#define CAN_DBG1_CBN_MASK (0x1F000000U) +#define CAN_DBG1_CBN_SHIFT (24U) +#define CAN_DBG1_CBN(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBG1_CBN_SHIFT)) & CAN_DBG1_CBN_MASK) +/*! @} */ + +/*! @name DBG2 - Debug 2 register */ +/*! @{ */ +#define CAN_DBG2_RMP_MASK (0x7FU) +#define CAN_DBG2_RMP_SHIFT (0U) +#define CAN_DBG2_RMP(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBG2_RMP_SHIFT)) & CAN_DBG2_RMP_MASK) +#define CAN_DBG2_MPP_MASK (0x80U) +#define CAN_DBG2_MPP_SHIFT (7U) +/*! MPP - Matching Process in Progress + * 0b0..No matching process ongoing. + * 0b1..Matching process is in progress. + */ +#define CAN_DBG2_MPP(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBG2_MPP_SHIFT)) & CAN_DBG2_MPP_MASK) +#define CAN_DBG2_TAP_MASK (0x7F00U) +#define CAN_DBG2_TAP_SHIFT (8U) +#define CAN_DBG2_TAP(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBG2_TAP_SHIFT)) & CAN_DBG2_TAP_MASK) +#define CAN_DBG2_APP_MASK (0x8000U) +#define CAN_DBG2_APP_SHIFT (15U) +/*! APP - Arbitration Process in Progress + * 0b0..No matching process ongoing. + * 0b1..Matching process is in progress. + */ +#define CAN_DBG2_APP(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBG2_APP_SHIFT)) & CAN_DBG2_APP_MASK) +/*! @} */ + /* The count of CAN_CS */ #define CAN_CS_COUNT_MB16B (42U) @@ -4403,6 +4459,10 @@ typedef struct { /*! @{ */ #define CAN_RXIMR_MI_MASK (0xFFFFFFFFU) #define CAN_RXIMR_MI_SHIFT (0U) +/*! MI - Individual Mask Bits + * 0b00000000000000000000000000000001..The corresponding bit in the filter is checked + * 0b00000000000000000000000000000000..the corresponding bit in the filter is "don't care" + */ #define CAN_RXIMR_MI(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXIMR_MI_SHIFT)) & CAN_RXIMR_MI_MASK) /*! @} */ @@ -4462,7 +4522,7 @@ typedef struct { #define CAN_ETDC_ETDCOFF(x) (((uint32_t)(((uint32_t)(x)) << CAN_ETDC_ETDCOFF_SHIFT)) & CAN_ETDC_ETDCOFF_MASK) #define CAN_ETDC_TDMDIS_MASK (0x80000000U) #define CAN_ETDC_TDMDIS_SHIFT (31U) -/*! TDMDIS - Transceiver Delay Measurement Disable +/*! TDMDIS - Transceiver Delay Measurement Disable * 0b0..TDC measurement is enabled * 0b1..TDC measurement is disabled */ @@ -4563,7 +4623,7 @@ typedef struct { #define CAN_ERFCR_DMALW(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFCR_DMALW_SHIFT)) & CAN_ERFCR_DMALW_MASK) #define CAN_ERFCR_ERFEN_MASK (0x80000000U) #define CAN_ERFCR_ERFEN_SHIFT (31U) -/*! ERFEN - Enhanced Rx FIFO enable +/*! ERFEN - Enhanced Rx FIFO enable * 0b0..Enhanced Rx FIFO is disabled * 0b1..Enhanced Rx FIFO is enabled */ @@ -4574,28 +4634,28 @@ typedef struct { /*! @{ */ #define CAN_ERFIER_ERFDAIE_MASK (0x10000000U) #define CAN_ERFIER_ERFDAIE_SHIFT (28U) -/*! ERFDAIE - Enhanced Rx FIFO Data Available Interrupt Enable +/*! ERFDAIE - Enhanced Rx FIFO Data Available Interrupt Enable * 0b0..Enhanced Rx FIFO Data Available Interrupt is disabled * 0b1..Enhanced Rx FIFO Data Available Interrupt is enabled */ #define CAN_ERFIER_ERFDAIE(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFIER_ERFDAIE_SHIFT)) & CAN_ERFIER_ERFDAIE_MASK) #define CAN_ERFIER_ERFWMIIE_MASK (0x20000000U) #define CAN_ERFIER_ERFWMIIE_SHIFT (29U) -/*! ERFWMIIE - Enhanced Rx FIFO Watermark Indication Interrupt Enable +/*! ERFWMIIE - Enhanced Rx FIFO Watermark Indication Interrupt Enable * 0b0..Enhanced Rx FIFO Watermark Interrupt is disabled * 0b1..Enhanced Rx FIFO Watermark Interrupt is enabled */ #define CAN_ERFIER_ERFWMIIE(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFIER_ERFWMIIE_SHIFT)) & CAN_ERFIER_ERFWMIIE_MASK) #define CAN_ERFIER_ERFOVFIE_MASK (0x40000000U) #define CAN_ERFIER_ERFOVFIE_SHIFT (30U) -/*! ERFOVFIE - Enhanced Rx FIFO Overflow Interrupt Enable +/*! ERFOVFIE - Enhanced Rx FIFO Overflow Interrupt Enable * 0b0..Enhanced Rx FIFO Overflow is disabled * 0b1..Enhanced Rx FIFO Overflow is enabled */ #define CAN_ERFIER_ERFOVFIE(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFIER_ERFOVFIE_SHIFT)) & CAN_ERFIER_ERFOVFIE_MASK) #define CAN_ERFIER_ERFUFWIE_MASK (0x80000000U) #define CAN_ERFIER_ERFUFWIE_SHIFT (31U) -/*! ERFUFWIE - Enhanced Rx FIFO Underflow Interrupt Enable +/*! ERFUFWIE - Enhanced Rx FIFO Underflow Interrupt Enable * 0b0..Enhanced Rx FIFO Underflow interrupt is disabled * 0b1..Enhanced Rx FIFO Underflow interrupt is enabled */ @@ -4609,49 +4669,49 @@ typedef struct { #define CAN_ERFSR_ERFEL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFSR_ERFEL_SHIFT)) & CAN_ERFSR_ERFEL_MASK) #define CAN_ERFSR_ERFF_MASK (0x10000U) #define CAN_ERFSR_ERFF_SHIFT (16U) -/*! ERFF - Enhanced Rx FIFO full +/*! ERFF - Enhanced Rx FIFO full * 0b0..Enhanced Rx FIFO is not full * 0b1..Enhanced Rx FIFO is full */ #define CAN_ERFSR_ERFF(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFSR_ERFF_SHIFT)) & CAN_ERFSR_ERFF_MASK) #define CAN_ERFSR_ERFE_MASK (0x20000U) #define CAN_ERFSR_ERFE_SHIFT (17U) -/*! ERFE - Enhanced Rx FIFO empty +/*! ERFE - Enhanced Rx FIFO empty * 0b0..Enhanced Rx FIFO is not empty * 0b1..Enhanced Rx FIFO is empty */ #define CAN_ERFSR_ERFE(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFSR_ERFE_SHIFT)) & CAN_ERFSR_ERFE_MASK) #define CAN_ERFSR_ERFCLR_MASK (0x8000000U) #define CAN_ERFSR_ERFCLR_SHIFT (27U) -/*! ERFCLR - Enhanced Rx FIFO Clear +/*! ERFCLR - Enhanced Rx FIFO Clear * 0b0..No effect * 0b1..Clear Enhanced Rx FIFO content */ #define CAN_ERFSR_ERFCLR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFSR_ERFCLR_SHIFT)) & CAN_ERFSR_ERFCLR_MASK) #define CAN_ERFSR_ERFDA_MASK (0x10000000U) #define CAN_ERFSR_ERFDA_SHIFT (28U) -/*! ERFDA - Enhanced Rx FIFO Data Available +/*! ERFDA - Enhanced Rx FIFO Data Available * 0b0..No such occurrence * 0b1..There is at least one message stored in Enhanced Rx FIFO */ #define CAN_ERFSR_ERFDA(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFSR_ERFDA_SHIFT)) & CAN_ERFSR_ERFDA_MASK) #define CAN_ERFSR_ERFWMI_MASK (0x20000000U) #define CAN_ERFSR_ERFWMI_SHIFT (29U) -/*! ERFWMI - Enhanced Rx FIFO Watermark Indication +/*! ERFWMI - Enhanced Rx FIFO Watermark Indication * 0b0..No such occurrence * 0b1..The number of messages in FIFO is greater than the watermark */ #define CAN_ERFSR_ERFWMI(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFSR_ERFWMI_SHIFT)) & CAN_ERFSR_ERFWMI_MASK) #define CAN_ERFSR_ERFOVF_MASK (0x40000000U) #define CAN_ERFSR_ERFOVF_SHIFT (30U) -/*! ERFOVF - Enhanced Rx FIFO Overflow +/*! ERFOVF - Enhanced Rx FIFO Overflow * 0b0..No such occurrence * 0b1..Enhanced Rx FIFO overflow */ #define CAN_ERFSR_ERFOVF(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFSR_ERFOVF_SHIFT)) & CAN_ERFSR_ERFOVF_MASK) #define CAN_ERFSR_ERFUFW_MASK (0x80000000U) #define CAN_ERFSR_ERFUFW_SHIFT (31U) -/*! ERFUFW - Enhanced Rx FIFO Underflow +/*! ERFUFW - Enhanced Rx FIFO Underflow * 0b0..No such occurrence * 0b1..Enhanced Rx FIFO underflow */ @@ -4709,7 +4769,6 @@ typedef struct { #define CAN_Bus_Off_IRQS { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn, CAN3_IRQn } #define CAN_ORed_Message_buffer_IRQS { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn, CAN3_IRQn } - /*! * @} */ /* end of group CAN_Peripheral_Access_Layer */ @@ -10602,9 +10661,17 @@ typedef struct { /*! @{ */ #define DMA_CR_EDBG_MASK (0x2U) #define DMA_CR_EDBG_SHIFT (1U) +/*! EDBG - Enable Debug + * 0b0..When in debug mode, the DMA continues to operate. + * 0b1..When in debug mode, the DMA stalls the start of a new channel. Executing channels are allowed to complete. Channel execution resumes when the system exits debug mode or the EDBG bit is cleared. + */ #define DMA_CR_EDBG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_EDBG_SHIFT)) & DMA_CR_EDBG_MASK) #define DMA_CR_ERCA_MASK (0x4U) #define DMA_CR_ERCA_SHIFT (2U) +/*! ERCA - Enable Round Robin Channel Arbitration + * 0b0..Fixed priority arbitration is used for channel selection within each group. + * 0b1..Round robin arbitration is used for channel selection within each group. + */ #define DMA_CR_ERCA(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ERCA_SHIFT)) & DMA_CR_ERCA_MASK) #define DMA_CR_ERGA_MASK (0x8U) #define DMA_CR_ERGA_SHIFT (3U) @@ -10697,6 +10764,7 @@ typedef struct { #define DMA_ES_NCE_SHIFT (3U) /*! NCE - NBYTES/CITER Configuration Error * 0b0..No NBYTES/CITER configuration error + * 0b1..The last recorded error was a configuration error detected in the TCDn_NBYTES or TCDn_CITER fields. TCDn_NBYTES is not a multiple of TCDn_ATTR[SSIZE] and TCDn_ATTR[DSIZE], or TCDn_CITER[CITER] is equal to zero, or TCDn_CITER[ELINK] is not equal to TCDn_BITER[ELINK] */ #define DMA_ES_NCE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_NCE_SHIFT)) & DMA_ES_NCE_MASK) #define DMA_ES_DOE_MASK (0x10U) @@ -10734,6 +10802,7 @@ typedef struct { #define DMA_ES_CPE_SHIFT (14U) /*! CPE - Channel Priority Error * 0b0..No channel priority error + * 0b1..The last recorded error was a configuration error in the channel priorities within a group. Channel priorities within a group are not unique. */ #define DMA_ES_CPE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_CPE_SHIFT)) & DMA_ES_CPE_MASK) #define DMA_ES_GPE_MASK (0x8000U) @@ -11222,6 +11291,10 @@ typedef struct { #define DMA_CEEI_CEEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_CEEI_SHIFT)) & DMA_CEEI_CEEI_MASK) #define DMA_CEEI_CAEE_MASK (0x40U) #define DMA_CEEI_CAEE_SHIFT (6U) +/*! CAEE - Clear All Enable Error Interrupts + * 0b0..Clear only the EEI bit specified in the CEEI field + * 0b1..Clear all bits in EEI + */ #define DMA_CEEI_CAEE(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_CAEE_SHIFT)) & DMA_CEEI_CAEE_MASK) #define DMA_CEEI_NOP_MASK (0x80U) #define DMA_CEEI_NOP_SHIFT (7U) @@ -11239,6 +11312,10 @@ typedef struct { #define DMA_SEEI_SEEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_SEEI_SHIFT)) & DMA_SEEI_SEEI_MASK) #define DMA_SEEI_SAEE_MASK (0x40U) #define DMA_SEEI_SAEE_SHIFT (6U) +/*! SAEE - Sets All Enable Error Interrupts + * 0b0..Set only the EEI bit specified in the SEEI field. + * 0b1..Sets all bits in EEI + */ #define DMA_SEEI_SAEE(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_SAEE_SHIFT)) & DMA_SEEI_SAEE_MASK) #define DMA_SEEI_NOP_MASK (0x80U) #define DMA_SEEI_NOP_SHIFT (7U) @@ -11256,6 +11333,10 @@ typedef struct { #define DMA_CERQ_CERQ(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_CERQ_SHIFT)) & DMA_CERQ_CERQ_MASK) #define DMA_CERQ_CAER_MASK (0x40U) #define DMA_CERQ_CAER_SHIFT (6U) +/*! CAER - Clear All Enable Requests + * 0b0..Clear only the ERQ bit specified in the CERQ field + * 0b1..Clear all bits in ERQ + */ #define DMA_CERQ_CAER(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_CAER_SHIFT)) & DMA_CERQ_CAER_MASK) #define DMA_CERQ_NOP_MASK (0x80U) #define DMA_CERQ_NOP_SHIFT (7U) @@ -11273,6 +11354,10 @@ typedef struct { #define DMA_SERQ_SERQ(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_SERQ_SHIFT)) & DMA_SERQ_SERQ_MASK) #define DMA_SERQ_SAER_MASK (0x40U) #define DMA_SERQ_SAER_SHIFT (6U) +/*! SAER - Set All Enable Requests + * 0b0..Set only the ERQ bit specified in the SERQ field + * 0b1..Set all bits in ERQ + */ #define DMA_SERQ_SAER(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_SAER_SHIFT)) & DMA_SERQ_SAER_MASK) #define DMA_SERQ_NOP_MASK (0x80U) #define DMA_SERQ_NOP_SHIFT (7U) @@ -11332,6 +11417,10 @@ typedef struct { #define DMA_CERR_CERR(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_CERR_SHIFT)) & DMA_CERR_CERR_MASK) #define DMA_CERR_CAEI_MASK (0x40U) #define DMA_CERR_CAEI_SHIFT (6U) +/*! CAEI - Clear All Error Indicators + * 0b0..Clear only the ERR bit specified in the CERR field + * 0b1..Clear all bits in ERR + */ #define DMA_CERR_CAEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_CAEI_SHIFT)) & DMA_CERR_CAEI_MASK) #define DMA_CERR_NOP_MASK (0x80U) #define DMA_CERR_NOP_SHIFT (7U) @@ -11349,6 +11438,10 @@ typedef struct { #define DMA_CINT_CINT(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_CINT_SHIFT)) & DMA_CINT_CINT_MASK) #define DMA_CINT_CAIR_MASK (0x40U) #define DMA_CINT_CAIR_SHIFT (6U) +/*! CAIR - Clear All Interrupt Requests + * 0b0..Clear only the INT bit specified in the CINT field + * 0b1..Clear all bits in INT + */ #define DMA_CINT_CAIR(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_CAIR_SHIFT)) & DMA_CINT_CAIR_MASK) #define DMA_CINT_NOP_MASK (0x80U) #define DMA_CINT_NOP_SHIFT (7U) @@ -12047,256 +12140,224 @@ typedef struct { /*! @{ */ #define DMA_EARS_EDREQ_0_MASK (0x1U) #define DMA_EARS_EDREQ_0_SHIFT (0U) -/*! EDREQ_0 - Enable asynchronous DMA request in stop mode for channel - 0. +/*! EDREQ_0 - Enable asynchronous DMA request in stop mode for channel 0. * 0b0..Disable asynchronous DMA request for channel 0. * 0b1..Enable asynchronous DMA request for channel 0. */ #define DMA_EARS_EDREQ_0(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_0_SHIFT)) & DMA_EARS_EDREQ_0_MASK) #define DMA_EARS_EDREQ_1_MASK (0x2U) #define DMA_EARS_EDREQ_1_SHIFT (1U) -/*! EDREQ_1 - Enable asynchronous DMA request in stop mode for channel - 1. +/*! EDREQ_1 - Enable asynchronous DMA request in stop mode for channel 1. * 0b0..Disable asynchronous DMA request for channel 1 * 0b1..Enable asynchronous DMA request for channel 1. */ #define DMA_EARS_EDREQ_1(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_1_SHIFT)) & DMA_EARS_EDREQ_1_MASK) #define DMA_EARS_EDREQ_2_MASK (0x4U) #define DMA_EARS_EDREQ_2_SHIFT (2U) -/*! EDREQ_2 - Enable asynchronous DMA request in stop mode for channel - 2. +/*! EDREQ_2 - Enable asynchronous DMA request in stop mode for channel 2. * 0b0..Disable asynchronous DMA request for channel 2. * 0b1..Enable asynchronous DMA request for channel 2. */ #define DMA_EARS_EDREQ_2(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_2_SHIFT)) & DMA_EARS_EDREQ_2_MASK) #define DMA_EARS_EDREQ_3_MASK (0x8U) #define DMA_EARS_EDREQ_3_SHIFT (3U) -/*! EDREQ_3 - Enable asynchronous DMA request in stop mode for channel - 3. +/*! EDREQ_3 - Enable asynchronous DMA request in stop mode for channel 3. * 0b0..Disable asynchronous DMA request for channel 3. * 0b1..Enable asynchronous DMA request for channel 3. */ #define DMA_EARS_EDREQ_3(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_3_SHIFT)) & DMA_EARS_EDREQ_3_MASK) #define DMA_EARS_EDREQ_4_MASK (0x10U) #define DMA_EARS_EDREQ_4_SHIFT (4U) -/*! EDREQ_4 - Enable asynchronous DMA request in stop mode for channel - 4 +/*! EDREQ_4 - Enable asynchronous DMA request in stop mode for channel 4 * 0b0..Disable asynchronous DMA request for channel 4. * 0b1..Enable asynchronous DMA request for channel 4. */ #define DMA_EARS_EDREQ_4(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_4_SHIFT)) & DMA_EARS_EDREQ_4_MASK) #define DMA_EARS_EDREQ_5_MASK (0x20U) #define DMA_EARS_EDREQ_5_SHIFT (5U) -/*! EDREQ_5 - Enable asynchronous DMA request in stop mode for channel - 5 +/*! EDREQ_5 - Enable asynchronous DMA request in stop mode for channel 5 * 0b0..Disable asynchronous DMA request for channel 5. * 0b1..Enable asynchronous DMA request for channel 5. */ #define DMA_EARS_EDREQ_5(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_5_SHIFT)) & DMA_EARS_EDREQ_5_MASK) #define DMA_EARS_EDREQ_6_MASK (0x40U) #define DMA_EARS_EDREQ_6_SHIFT (6U) -/*! EDREQ_6 - Enable asynchronous DMA request in stop mode for channel - 6 +/*! EDREQ_6 - Enable asynchronous DMA request in stop mode for channel 6 * 0b0..Disable asynchronous DMA request for channel 6. * 0b1..Enable asynchronous DMA request for channel 6. */ #define DMA_EARS_EDREQ_6(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_6_SHIFT)) & DMA_EARS_EDREQ_6_MASK) #define DMA_EARS_EDREQ_7_MASK (0x80U) #define DMA_EARS_EDREQ_7_SHIFT (7U) -/*! EDREQ_7 - Enable asynchronous DMA request in stop mode for channel - 7 +/*! EDREQ_7 - Enable asynchronous DMA request in stop mode for channel 7 * 0b0..Disable asynchronous DMA request for channel 7. * 0b1..Enable asynchronous DMA request for channel 7. */ #define DMA_EARS_EDREQ_7(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_7_SHIFT)) & DMA_EARS_EDREQ_7_MASK) #define DMA_EARS_EDREQ_8_MASK (0x100U) #define DMA_EARS_EDREQ_8_SHIFT (8U) -/*! EDREQ_8 - Enable asynchronous DMA request in stop mode for channel - 8 +/*! EDREQ_8 - Enable asynchronous DMA request in stop mode for channel 8 * 0b0..Disable asynchronous DMA request for channel 8. * 0b1..Enable asynchronous DMA request for channel 8. */ #define DMA_EARS_EDREQ_8(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_8_SHIFT)) & DMA_EARS_EDREQ_8_MASK) #define DMA_EARS_EDREQ_9_MASK (0x200U) #define DMA_EARS_EDREQ_9_SHIFT (9U) -/*! EDREQ_9 - Enable asynchronous DMA request in stop mode for channel - 9 +/*! EDREQ_9 - Enable asynchronous DMA request in stop mode for channel 9 * 0b0..Disable asynchronous DMA request for channel 9. * 0b1..Enable asynchronous DMA request for channel 9. */ #define DMA_EARS_EDREQ_9(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_9_SHIFT)) & DMA_EARS_EDREQ_9_MASK) #define DMA_EARS_EDREQ_10_MASK (0x400U) #define DMA_EARS_EDREQ_10_SHIFT (10U) -/*! EDREQ_10 - Enable asynchronous DMA request in stop mode for channel - 10 +/*! EDREQ_10 - Enable asynchronous DMA request in stop mode for channel 10 * 0b0..Disable asynchronous DMA request for channel 10. * 0b1..Enable asynchronous DMA request for channel 10. */ #define DMA_EARS_EDREQ_10(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_10_SHIFT)) & DMA_EARS_EDREQ_10_MASK) #define DMA_EARS_EDREQ_11_MASK (0x800U) #define DMA_EARS_EDREQ_11_SHIFT (11U) -/*! EDREQ_11 - Enable asynchronous DMA request in stop mode for channel - 11 +/*! EDREQ_11 - Enable asynchronous DMA request in stop mode for channel 11 * 0b0..Disable asynchronous DMA request for channel 11. * 0b1..Enable asynchronous DMA request for channel 11. */ #define DMA_EARS_EDREQ_11(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_11_SHIFT)) & DMA_EARS_EDREQ_11_MASK) #define DMA_EARS_EDREQ_12_MASK (0x1000U) #define DMA_EARS_EDREQ_12_SHIFT (12U) -/*! EDREQ_12 - Enable asynchronous DMA request in stop mode for channel - 12 +/*! EDREQ_12 - Enable asynchronous DMA request in stop mode for channel 12 * 0b0..Disable asynchronous DMA request for channel 12. * 0b1..Enable asynchronous DMA request for channel 12. */ #define DMA_EARS_EDREQ_12(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_12_SHIFT)) & DMA_EARS_EDREQ_12_MASK) #define DMA_EARS_EDREQ_13_MASK (0x2000U) #define DMA_EARS_EDREQ_13_SHIFT (13U) -/*! EDREQ_13 - Enable asynchronous DMA request in stop mode for channel - 13 +/*! EDREQ_13 - Enable asynchronous DMA request in stop mode for channel 13 * 0b0..Disable asynchronous DMA request for channel 13. * 0b1..Enable asynchronous DMA request for channel 13. */ #define DMA_EARS_EDREQ_13(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_13_SHIFT)) & DMA_EARS_EDREQ_13_MASK) #define DMA_EARS_EDREQ_14_MASK (0x4000U) #define DMA_EARS_EDREQ_14_SHIFT (14U) -/*! EDREQ_14 - Enable asynchronous DMA request in stop mode for channel - 14 +/*! EDREQ_14 - Enable asynchronous DMA request in stop mode for channel 14 * 0b0..Disable asynchronous DMA request for channel 14. * 0b1..Enable asynchronous DMA request for channel 14. */ #define DMA_EARS_EDREQ_14(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_14_SHIFT)) & DMA_EARS_EDREQ_14_MASK) #define DMA_EARS_EDREQ_15_MASK (0x8000U) #define DMA_EARS_EDREQ_15_SHIFT (15U) -/*! EDREQ_15 - Enable asynchronous DMA request in stop mode for channel - 15 +/*! EDREQ_15 - Enable asynchronous DMA request in stop mode for channel 15 * 0b0..Disable asynchronous DMA request for channel 15. * 0b1..Enable asynchronous DMA request for channel 15. */ #define DMA_EARS_EDREQ_15(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_15_SHIFT)) & DMA_EARS_EDREQ_15_MASK) #define DMA_EARS_EDREQ_16_MASK (0x10000U) #define DMA_EARS_EDREQ_16_SHIFT (16U) -/*! EDREQ_16 - Enable asynchronous DMA request in stop mode for channel - 16 +/*! EDREQ_16 - Enable asynchronous DMA request in stop mode for channel 16 * 0b0..Disable asynchronous DMA request for channel 16 * 0b1..Enable asynchronous DMA request for channel 16 */ #define DMA_EARS_EDREQ_16(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_16_SHIFT)) & DMA_EARS_EDREQ_16_MASK) #define DMA_EARS_EDREQ_17_MASK (0x20000U) #define DMA_EARS_EDREQ_17_SHIFT (17U) -/*! EDREQ_17 - Enable asynchronous DMA request in stop mode for channel - 17 +/*! EDREQ_17 - Enable asynchronous DMA request in stop mode for channel 17 * 0b0..Disable asynchronous DMA request for channel 17 * 0b1..Enable asynchronous DMA request for channel 17 */ #define DMA_EARS_EDREQ_17(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_17_SHIFT)) & DMA_EARS_EDREQ_17_MASK) #define DMA_EARS_EDREQ_18_MASK (0x40000U) #define DMA_EARS_EDREQ_18_SHIFT (18U) -/*! EDREQ_18 - Enable asynchronous DMA request in stop mode for channel - 18 +/*! EDREQ_18 - Enable asynchronous DMA request in stop mode for channel 18 * 0b0..Disable asynchronous DMA request for channel 18 * 0b1..Enable asynchronous DMA request for channel 18 */ #define DMA_EARS_EDREQ_18(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_18_SHIFT)) & DMA_EARS_EDREQ_18_MASK) #define DMA_EARS_EDREQ_19_MASK (0x80000U) #define DMA_EARS_EDREQ_19_SHIFT (19U) -/*! EDREQ_19 - Enable asynchronous DMA request in stop mode for channel - 19 +/*! EDREQ_19 - Enable asynchronous DMA request in stop mode for channel 19 * 0b0..Disable asynchronous DMA request for channel 19 * 0b1..Enable asynchronous DMA request for channel 19 */ #define DMA_EARS_EDREQ_19(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_19_SHIFT)) & DMA_EARS_EDREQ_19_MASK) #define DMA_EARS_EDREQ_20_MASK (0x100000U) #define DMA_EARS_EDREQ_20_SHIFT (20U) -/*! EDREQ_20 - Enable asynchronous DMA request in stop mode for channel - 20 +/*! EDREQ_20 - Enable asynchronous DMA request in stop mode for channel 20 * 0b0..Disable asynchronous DMA request for channel 20 * 0b1..Enable asynchronous DMA request for channel 20 */ #define DMA_EARS_EDREQ_20(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_20_SHIFT)) & DMA_EARS_EDREQ_20_MASK) #define DMA_EARS_EDREQ_21_MASK (0x200000U) #define DMA_EARS_EDREQ_21_SHIFT (21U) -/*! EDREQ_21 - Enable asynchronous DMA request in stop mode for channel - 21 +/*! EDREQ_21 - Enable asynchronous DMA request in stop mode for channel 21 * 0b0..Disable asynchronous DMA request for channel 21 * 0b1..Enable asynchronous DMA request for channel 21 */ #define DMA_EARS_EDREQ_21(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_21_SHIFT)) & DMA_EARS_EDREQ_21_MASK) #define DMA_EARS_EDREQ_22_MASK (0x400000U) #define DMA_EARS_EDREQ_22_SHIFT (22U) -/*! EDREQ_22 - Enable asynchronous DMA request in stop mode for channel - 22 +/*! EDREQ_22 - Enable asynchronous DMA request in stop mode for channel 22 * 0b0..Disable asynchronous DMA request for channel 22 * 0b1..Enable asynchronous DMA request for channel 22 */ #define DMA_EARS_EDREQ_22(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_22_SHIFT)) & DMA_EARS_EDREQ_22_MASK) #define DMA_EARS_EDREQ_23_MASK (0x800000U) #define DMA_EARS_EDREQ_23_SHIFT (23U) -/*! EDREQ_23 - Enable asynchronous DMA request in stop mode for channel - 23 +/*! EDREQ_23 - Enable asynchronous DMA request in stop mode for channel 23 * 0b0..Disable asynchronous DMA request for channel 23 * 0b1..Enable asynchronous DMA request for channel 23 */ #define DMA_EARS_EDREQ_23(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_23_SHIFT)) & DMA_EARS_EDREQ_23_MASK) #define DMA_EARS_EDREQ_24_MASK (0x1000000U) #define DMA_EARS_EDREQ_24_SHIFT (24U) -/*! EDREQ_24 - Enable asynchronous DMA request in stop mode for channel - 24 +/*! EDREQ_24 - Enable asynchronous DMA request in stop mode for channel 24 * 0b0..Disable asynchronous DMA request for channel 24 * 0b1..Enable asynchronous DMA request for channel 24 */ #define DMA_EARS_EDREQ_24(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_24_SHIFT)) & DMA_EARS_EDREQ_24_MASK) #define DMA_EARS_EDREQ_25_MASK (0x2000000U) #define DMA_EARS_EDREQ_25_SHIFT (25U) -/*! EDREQ_25 - Enable asynchronous DMA request in stop mode for channel - 25 +/*! EDREQ_25 - Enable asynchronous DMA request in stop mode for channel 25 * 0b0..Disable asynchronous DMA request for channel 25 * 0b1..Enable asynchronous DMA request for channel 25 */ #define DMA_EARS_EDREQ_25(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_25_SHIFT)) & DMA_EARS_EDREQ_25_MASK) #define DMA_EARS_EDREQ_26_MASK (0x4000000U) #define DMA_EARS_EDREQ_26_SHIFT (26U) -/*! EDREQ_26 - Enable asynchronous DMA request in stop mode for channel - 26 +/*! EDREQ_26 - Enable asynchronous DMA request in stop mode for channel 26 * 0b0..Disable asynchronous DMA request for channel 26 * 0b1..Enable asynchronous DMA request for channel 26 */ #define DMA_EARS_EDREQ_26(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_26_SHIFT)) & DMA_EARS_EDREQ_26_MASK) #define DMA_EARS_EDREQ_27_MASK (0x8000000U) #define DMA_EARS_EDREQ_27_SHIFT (27U) -/*! EDREQ_27 - Enable asynchronous DMA request in stop mode for channel - 27 +/*! EDREQ_27 - Enable asynchronous DMA request in stop mode for channel 27 * 0b0..Disable asynchronous DMA request for channel 27 * 0b1..Enable asynchronous DMA request for channel 27 */ #define DMA_EARS_EDREQ_27(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_27_SHIFT)) & DMA_EARS_EDREQ_27_MASK) #define DMA_EARS_EDREQ_28_MASK (0x10000000U) #define DMA_EARS_EDREQ_28_SHIFT (28U) -/*! EDREQ_28 - Enable asynchronous DMA request in stop mode for channel - 28 +/*! EDREQ_28 - Enable asynchronous DMA request in stop mode for channel 28 * 0b0..Disable asynchronous DMA request for channel 28 * 0b1..Enable asynchronous DMA request for channel 28 */ #define DMA_EARS_EDREQ_28(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_28_SHIFT)) & DMA_EARS_EDREQ_28_MASK) #define DMA_EARS_EDREQ_29_MASK (0x20000000U) #define DMA_EARS_EDREQ_29_SHIFT (29U) -/*! EDREQ_29 - Enable asynchronous DMA request in stop mode for channel - 29 +/*! EDREQ_29 - Enable asynchronous DMA request in stop mode for channel 29 * 0b0..Disable asynchronous DMA request for channel 29 * 0b1..Enable asynchronous DMA request for channel 29 */ #define DMA_EARS_EDREQ_29(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_29_SHIFT)) & DMA_EARS_EDREQ_29_MASK) #define DMA_EARS_EDREQ_30_MASK (0x40000000U) #define DMA_EARS_EDREQ_30_SHIFT (30U) -/*! EDREQ_30 - Enable asynchronous DMA request in stop mode for channel - 30 +/*! EDREQ_30 - Enable asynchronous DMA request in stop mode for channel 30 * 0b0..Disable asynchronous DMA request for channel 30 * 0b1..Enable asynchronous DMA request for channel 30 */ #define DMA_EARS_EDREQ_30(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_30_SHIFT)) & DMA_EARS_EDREQ_30_MASK) #define DMA_EARS_EDREQ_31_MASK (0x80000000U) #define DMA_EARS_EDREQ_31_SHIFT (31U) -/*! EDREQ_31 - Enable asynchronous DMA request in stop mode for channel - 31 +/*! EDREQ_31 - Enable asynchronous DMA request in stop mode for channel 31 * 0b0..Disable asynchronous DMA request for channel 31 * 0b1..Enable asynchronous DMA request for channel 31 */ @@ -12313,16 +12374,14 @@ typedef struct { #define DMA_DCHPRI3_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_GRPPRI_SHIFT)) & DMA_DCHPRI3_GRPPRI_MASK) #define DMA_DCHPRI3_DPA_MASK (0x40U) #define DMA_DCHPRI3_DPA_SHIFT (6U) -/*! DPA - Disable Preempt Ability. This field resets to - 0. +/*! DPA - Disable Preempt Ability. This field resets to 0. * 0b0..Channel n can suspend a lower priority channel. * 0b1..Channel n cannot suspend any channel, regardless of channel priority. */ #define DMA_DCHPRI3_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_DPA_SHIFT)) & DMA_DCHPRI3_DPA_MASK) #define DMA_DCHPRI3_ECP_MASK (0x80U) #define DMA_DCHPRI3_ECP_SHIFT (7U) -/*! ECP - Enable Channel Preemption. This field resets to - 0. +/*! ECP - Enable Channel Preemption. This field resets to 0. * 0b0..Channel n cannot be suspended by a higher priority channel's service request. * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. */ @@ -12339,16 +12398,14 @@ typedef struct { #define DMA_DCHPRI2_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_GRPPRI_SHIFT)) & DMA_DCHPRI2_GRPPRI_MASK) #define DMA_DCHPRI2_DPA_MASK (0x40U) #define DMA_DCHPRI2_DPA_SHIFT (6U) -/*! DPA - Disable Preempt Ability. This field resets to - 0. +/*! DPA - Disable Preempt Ability. This field resets to 0. * 0b0..Channel n can suspend a lower priority channel. * 0b1..Channel n cannot suspend any channel, regardless of channel priority. */ #define DMA_DCHPRI2_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_DPA_SHIFT)) & DMA_DCHPRI2_DPA_MASK) #define DMA_DCHPRI2_ECP_MASK (0x80U) #define DMA_DCHPRI2_ECP_SHIFT (7U) -/*! ECP - Enable Channel Preemption. This field resets to - 0. +/*! ECP - Enable Channel Preemption. This field resets to 0. * 0b0..Channel n cannot be suspended by a higher priority channel's service request. * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. */ @@ -12365,16 +12422,14 @@ typedef struct { #define DMA_DCHPRI1_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_GRPPRI_SHIFT)) & DMA_DCHPRI1_GRPPRI_MASK) #define DMA_DCHPRI1_DPA_MASK (0x40U) #define DMA_DCHPRI1_DPA_SHIFT (6U) -/*! DPA - Disable Preempt Ability. This field resets to - 0. +/*! DPA - Disable Preempt Ability. This field resets to 0. * 0b0..Channel n can suspend a lower priority channel. * 0b1..Channel n cannot suspend any channel, regardless of channel priority. */ #define DMA_DCHPRI1_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_DPA_SHIFT)) & DMA_DCHPRI1_DPA_MASK) #define DMA_DCHPRI1_ECP_MASK (0x80U) #define DMA_DCHPRI1_ECP_SHIFT (7U) -/*! ECP - Enable Channel Preemption. This field resets to - 0. +/*! ECP - Enable Channel Preemption. This field resets to 0. * 0b0..Channel n cannot be suspended by a higher priority channel's service request. * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. */ @@ -12391,16 +12446,14 @@ typedef struct { #define DMA_DCHPRI0_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_GRPPRI_SHIFT)) & DMA_DCHPRI0_GRPPRI_MASK) #define DMA_DCHPRI0_DPA_MASK (0x40U) #define DMA_DCHPRI0_DPA_SHIFT (6U) -/*! DPA - Disable Preempt Ability. This field resets to - 0. +/*! DPA - Disable Preempt Ability. This field resets to 0. * 0b0..Channel n can suspend a lower priority channel. * 0b1..Channel n cannot suspend any channel, regardless of channel priority. */ #define DMA_DCHPRI0_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_DPA_SHIFT)) & DMA_DCHPRI0_DPA_MASK) #define DMA_DCHPRI0_ECP_MASK (0x80U) #define DMA_DCHPRI0_ECP_SHIFT (7U) -/*! ECP - Enable Channel Preemption. This field resets to - 0. +/*! ECP - Enable Channel Preemption. This field resets to 0. * 0b0..Channel n cannot be suspended by a higher priority channel's service request. * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. */ @@ -12417,16 +12470,14 @@ typedef struct { #define DMA_DCHPRI7_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_GRPPRI_SHIFT)) & DMA_DCHPRI7_GRPPRI_MASK) #define DMA_DCHPRI7_DPA_MASK (0x40U) #define DMA_DCHPRI7_DPA_SHIFT (6U) -/*! DPA - Disable Preempt Ability. This field resets to - 0. +/*! DPA - Disable Preempt Ability. This field resets to 0. * 0b0..Channel n can suspend a lower priority channel. * 0b1..Channel n cannot suspend any channel, regardless of channel priority. */ #define DMA_DCHPRI7_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_DPA_SHIFT)) & DMA_DCHPRI7_DPA_MASK) #define DMA_DCHPRI7_ECP_MASK (0x80U) #define DMA_DCHPRI7_ECP_SHIFT (7U) -/*! ECP - Enable Channel Preemption. This field resets to - 0. +/*! ECP - Enable Channel Preemption. This field resets to 0. * 0b0..Channel n cannot be suspended by a higher priority channel's service request. * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. */ @@ -12443,16 +12494,14 @@ typedef struct { #define DMA_DCHPRI6_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_GRPPRI_SHIFT)) & DMA_DCHPRI6_GRPPRI_MASK) #define DMA_DCHPRI6_DPA_MASK (0x40U) #define DMA_DCHPRI6_DPA_SHIFT (6U) -/*! DPA - Disable Preempt Ability. This field resets to - 0. +/*! DPA - Disable Preempt Ability. This field resets to 0. * 0b0..Channel n can suspend a lower priority channel. * 0b1..Channel n cannot suspend any channel, regardless of channel priority. */ #define DMA_DCHPRI6_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_DPA_SHIFT)) & DMA_DCHPRI6_DPA_MASK) #define DMA_DCHPRI6_ECP_MASK (0x80U) #define DMA_DCHPRI6_ECP_SHIFT (7U) -/*! ECP - Enable Channel Preemption. This field resets to - 0. +/*! ECP - Enable Channel Preemption. This field resets to 0. * 0b0..Channel n cannot be suspended by a higher priority channel's service request. * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. */ @@ -12469,16 +12518,14 @@ typedef struct { #define DMA_DCHPRI5_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_GRPPRI_SHIFT)) & DMA_DCHPRI5_GRPPRI_MASK) #define DMA_DCHPRI5_DPA_MASK (0x40U) #define DMA_DCHPRI5_DPA_SHIFT (6U) -/*! DPA - Disable Preempt Ability. This field resets to - 0. +/*! DPA - Disable Preempt Ability. This field resets to 0. * 0b0..Channel n can suspend a lower priority channel. * 0b1..Channel n cannot suspend any channel, regardless of channel priority. */ #define DMA_DCHPRI5_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_DPA_SHIFT)) & DMA_DCHPRI5_DPA_MASK) #define DMA_DCHPRI5_ECP_MASK (0x80U) #define DMA_DCHPRI5_ECP_SHIFT (7U) -/*! ECP - Enable Channel Preemption. This field resets to - 0. +/*! ECP - Enable Channel Preemption. This field resets to 0. * 0b0..Channel n cannot be suspended by a higher priority channel's service request. * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. */ @@ -12495,16 +12542,14 @@ typedef struct { #define DMA_DCHPRI4_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_GRPPRI_SHIFT)) & DMA_DCHPRI4_GRPPRI_MASK) #define DMA_DCHPRI4_DPA_MASK (0x40U) #define DMA_DCHPRI4_DPA_SHIFT (6U) -/*! DPA - Disable Preempt Ability. This field resets to - 0. +/*! DPA - Disable Preempt Ability. This field resets to 0. * 0b0..Channel n can suspend a lower priority channel. * 0b1..Channel n cannot suspend any channel, regardless of channel priority. */ #define DMA_DCHPRI4_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_DPA_SHIFT)) & DMA_DCHPRI4_DPA_MASK) #define DMA_DCHPRI4_ECP_MASK (0x80U) #define DMA_DCHPRI4_ECP_SHIFT (7U) -/*! ECP - Enable Channel Preemption. This field resets to - 0. +/*! ECP - Enable Channel Preemption. This field resets to 0. * 0b0..Channel n cannot be suspended by a higher priority channel's service request. * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. */ @@ -12521,16 +12566,14 @@ typedef struct { #define DMA_DCHPRI11_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_GRPPRI_SHIFT)) & DMA_DCHPRI11_GRPPRI_MASK) #define DMA_DCHPRI11_DPA_MASK (0x40U) #define DMA_DCHPRI11_DPA_SHIFT (6U) -/*! DPA - Disable Preempt Ability. This field resets to - 0. +/*! DPA - Disable Preempt Ability. This field resets to 0. * 0b0..Channel n can suspend a lower priority channel. * 0b1..Channel n cannot suspend any channel, regardless of channel priority. */ #define DMA_DCHPRI11_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_DPA_SHIFT)) & DMA_DCHPRI11_DPA_MASK) #define DMA_DCHPRI11_ECP_MASK (0x80U) #define DMA_DCHPRI11_ECP_SHIFT (7U) -/*! ECP - Enable Channel Preemption. This field resets to - 0. +/*! ECP - Enable Channel Preemption. This field resets to 0. * 0b0..Channel n cannot be suspended by a higher priority channel's service request. * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. */ @@ -12547,16 +12590,14 @@ typedef struct { #define DMA_DCHPRI10_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_GRPPRI_SHIFT)) & DMA_DCHPRI10_GRPPRI_MASK) #define DMA_DCHPRI10_DPA_MASK (0x40U) #define DMA_DCHPRI10_DPA_SHIFT (6U) -/*! DPA - Disable Preempt Ability. This field resets to - 0. +/*! DPA - Disable Preempt Ability. This field resets to 0. * 0b0..Channel n can suspend a lower priority channel. * 0b1..Channel n cannot suspend any channel, regardless of channel priority. */ #define DMA_DCHPRI10_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_DPA_SHIFT)) & DMA_DCHPRI10_DPA_MASK) #define DMA_DCHPRI10_ECP_MASK (0x80U) #define DMA_DCHPRI10_ECP_SHIFT (7U) -/*! ECP - Enable Channel Preemption. This field resets to - 0. +/*! ECP - Enable Channel Preemption. This field resets to 0. * 0b0..Channel n cannot be suspended by a higher priority channel's service request. * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. */ @@ -12573,16 +12614,14 @@ typedef struct { #define DMA_DCHPRI9_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_GRPPRI_SHIFT)) & DMA_DCHPRI9_GRPPRI_MASK) #define DMA_DCHPRI9_DPA_MASK (0x40U) #define DMA_DCHPRI9_DPA_SHIFT (6U) -/*! DPA - Disable Preempt Ability. This field resets to - 0. +/*! DPA - Disable Preempt Ability. This field resets to 0. * 0b0..Channel n can suspend a lower priority channel. * 0b1..Channel n cannot suspend any channel, regardless of channel priority. */ #define DMA_DCHPRI9_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_DPA_SHIFT)) & DMA_DCHPRI9_DPA_MASK) #define DMA_DCHPRI9_ECP_MASK (0x80U) #define DMA_DCHPRI9_ECP_SHIFT (7U) -/*! ECP - Enable Channel Preemption. This field resets to - 0. +/*! ECP - Enable Channel Preemption. This field resets to 0. * 0b0..Channel n cannot be suspended by a higher priority channel's service request. * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. */ @@ -12599,16 +12638,14 @@ typedef struct { #define DMA_DCHPRI8_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_GRPPRI_SHIFT)) & DMA_DCHPRI8_GRPPRI_MASK) #define DMA_DCHPRI8_DPA_MASK (0x40U) #define DMA_DCHPRI8_DPA_SHIFT (6U) -/*! DPA - Disable Preempt Ability. This field resets to - 0. +/*! DPA - Disable Preempt Ability. This field resets to 0. * 0b0..Channel n can suspend a lower priority channel. * 0b1..Channel n cannot suspend any channel, regardless of channel priority. */ #define DMA_DCHPRI8_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_DPA_SHIFT)) & DMA_DCHPRI8_DPA_MASK) #define DMA_DCHPRI8_ECP_MASK (0x80U) #define DMA_DCHPRI8_ECP_SHIFT (7U) -/*! ECP - Enable Channel Preemption. This field resets to - 0. +/*! ECP - Enable Channel Preemption. This field resets to 0. * 0b0..Channel n cannot be suspended by a higher priority channel's service request. * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. */ @@ -12625,16 +12662,14 @@ typedef struct { #define DMA_DCHPRI15_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_GRPPRI_SHIFT)) & DMA_DCHPRI15_GRPPRI_MASK) #define DMA_DCHPRI15_DPA_MASK (0x40U) #define DMA_DCHPRI15_DPA_SHIFT (6U) -/*! DPA - Disable Preempt Ability. This field resets to - 0. +/*! DPA - Disable Preempt Ability. This field resets to 0. * 0b0..Channel n can suspend a lower priority channel. * 0b1..Channel n cannot suspend any channel, regardless of channel priority. */ #define DMA_DCHPRI15_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_DPA_SHIFT)) & DMA_DCHPRI15_DPA_MASK) #define DMA_DCHPRI15_ECP_MASK (0x80U) #define DMA_DCHPRI15_ECP_SHIFT (7U) -/*! ECP - Enable Channel Preemption. This field resets to - 0. +/*! ECP - Enable Channel Preemption. This field resets to 0. * 0b0..Channel n cannot be suspended by a higher priority channel's service request. * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. */ @@ -12651,16 +12686,14 @@ typedef struct { #define DMA_DCHPRI14_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_GRPPRI_SHIFT)) & DMA_DCHPRI14_GRPPRI_MASK) #define DMA_DCHPRI14_DPA_MASK (0x40U) #define DMA_DCHPRI14_DPA_SHIFT (6U) -/*! DPA - Disable Preempt Ability. This field resets to - 0. +/*! DPA - Disable Preempt Ability. This field resets to 0. * 0b0..Channel n can suspend a lower priority channel. * 0b1..Channel n cannot suspend any channel, regardless of channel priority. */ #define DMA_DCHPRI14_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_DPA_SHIFT)) & DMA_DCHPRI14_DPA_MASK) #define DMA_DCHPRI14_ECP_MASK (0x80U) #define DMA_DCHPRI14_ECP_SHIFT (7U) -/*! ECP - Enable Channel Preemption. This field resets to - 0. +/*! ECP - Enable Channel Preemption. This field resets to 0. * 0b0..Channel n cannot be suspended by a higher priority channel's service request. * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. */ @@ -12677,16 +12710,14 @@ typedef struct { #define DMA_DCHPRI13_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_GRPPRI_SHIFT)) & DMA_DCHPRI13_GRPPRI_MASK) #define DMA_DCHPRI13_DPA_MASK (0x40U) #define DMA_DCHPRI13_DPA_SHIFT (6U) -/*! DPA - Disable Preempt Ability. This field resets to - 0. +/*! DPA - Disable Preempt Ability. This field resets to 0. * 0b0..Channel n can suspend a lower priority channel. * 0b1..Channel n cannot suspend any channel, regardless of channel priority. */ #define DMA_DCHPRI13_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_DPA_SHIFT)) & DMA_DCHPRI13_DPA_MASK) #define DMA_DCHPRI13_ECP_MASK (0x80U) #define DMA_DCHPRI13_ECP_SHIFT (7U) -/*! ECP - Enable Channel Preemption. This field resets to - 0. +/*! ECP - Enable Channel Preemption. This field resets to 0. * 0b0..Channel n cannot be suspended by a higher priority channel's service request. * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. */ @@ -12703,16 +12734,14 @@ typedef struct { #define DMA_DCHPRI12_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_GRPPRI_SHIFT)) & DMA_DCHPRI12_GRPPRI_MASK) #define DMA_DCHPRI12_DPA_MASK (0x40U) #define DMA_DCHPRI12_DPA_SHIFT (6U) -/*! DPA - Disable Preempt Ability. This field resets to - 0. +/*! DPA - Disable Preempt Ability. This field resets to 0. * 0b0..Channel n can suspend a lower priority channel. * 0b1..Channel n cannot suspend any channel, regardless of channel priority. */ #define DMA_DCHPRI12_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_DPA_SHIFT)) & DMA_DCHPRI12_DPA_MASK) #define DMA_DCHPRI12_ECP_MASK (0x80U) #define DMA_DCHPRI12_ECP_SHIFT (7U) -/*! ECP - Enable Channel Preemption. This field resets to - 0. +/*! ECP - Enable Channel Preemption. This field resets to 0. * 0b0..Channel n cannot be suspended by a higher priority channel's service request. * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. */ @@ -12729,16 +12758,14 @@ typedef struct { #define DMA_DCHPRI19_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_GRPPRI_SHIFT)) & DMA_DCHPRI19_GRPPRI_MASK) #define DMA_DCHPRI19_DPA_MASK (0x40U) #define DMA_DCHPRI19_DPA_SHIFT (6U) -/*! DPA - Disable Preempt Ability. This field resets to - 0. +/*! DPA - Disable Preempt Ability. This field resets to 0. * 0b0..Channel n can suspend a lower priority channel. * 0b1..Channel n cannot suspend any channel, regardless of channel priority. */ #define DMA_DCHPRI19_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_DPA_SHIFT)) & DMA_DCHPRI19_DPA_MASK) #define DMA_DCHPRI19_ECP_MASK (0x80U) #define DMA_DCHPRI19_ECP_SHIFT (7U) -/*! ECP - Enable Channel Preemption. This field resets to - 0. +/*! ECP - Enable Channel Preemption. This field resets to 0. * 0b0..Channel n cannot be suspended by a higher priority channel's service request. * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. */ @@ -12755,16 +12782,14 @@ typedef struct { #define DMA_DCHPRI18_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_GRPPRI_SHIFT)) & DMA_DCHPRI18_GRPPRI_MASK) #define DMA_DCHPRI18_DPA_MASK (0x40U) #define DMA_DCHPRI18_DPA_SHIFT (6U) -/*! DPA - Disable Preempt Ability. This field resets to - 0. +/*! DPA - Disable Preempt Ability. This field resets to 0. * 0b0..Channel n can suspend a lower priority channel. * 0b1..Channel n cannot suspend any channel, regardless of channel priority. */ #define DMA_DCHPRI18_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_DPA_SHIFT)) & DMA_DCHPRI18_DPA_MASK) #define DMA_DCHPRI18_ECP_MASK (0x80U) #define DMA_DCHPRI18_ECP_SHIFT (7U) -/*! ECP - Enable Channel Preemption. This field resets to - 0. +/*! ECP - Enable Channel Preemption. This field resets to 0. * 0b0..Channel n cannot be suspended by a higher priority channel's service request. * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. */ @@ -12781,16 +12806,14 @@ typedef struct { #define DMA_DCHPRI17_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_GRPPRI_SHIFT)) & DMA_DCHPRI17_GRPPRI_MASK) #define DMA_DCHPRI17_DPA_MASK (0x40U) #define DMA_DCHPRI17_DPA_SHIFT (6U) -/*! DPA - Disable Preempt Ability. This field resets to - 0. +/*! DPA - Disable Preempt Ability. This field resets to 0. * 0b0..Channel n can suspend a lower priority channel. * 0b1..Channel n cannot suspend any channel, regardless of channel priority. */ #define DMA_DCHPRI17_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_DPA_SHIFT)) & DMA_DCHPRI17_DPA_MASK) #define DMA_DCHPRI17_ECP_MASK (0x80U) #define DMA_DCHPRI17_ECP_SHIFT (7U) -/*! ECP - Enable Channel Preemption. This field resets to - 0. +/*! ECP - Enable Channel Preemption. This field resets to 0. * 0b0..Channel n cannot be suspended by a higher priority channel's service request. * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. */ @@ -12807,16 +12830,14 @@ typedef struct { #define DMA_DCHPRI16_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_GRPPRI_SHIFT)) & DMA_DCHPRI16_GRPPRI_MASK) #define DMA_DCHPRI16_DPA_MASK (0x40U) #define DMA_DCHPRI16_DPA_SHIFT (6U) -/*! DPA - Disable Preempt Ability. This field resets to - 0. +/*! DPA - Disable Preempt Ability. This field resets to 0. * 0b0..Channel n can suspend a lower priority channel. * 0b1..Channel n cannot suspend any channel, regardless of channel priority. */ #define DMA_DCHPRI16_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_DPA_SHIFT)) & DMA_DCHPRI16_DPA_MASK) #define DMA_DCHPRI16_ECP_MASK (0x80U) #define DMA_DCHPRI16_ECP_SHIFT (7U) -/*! ECP - Enable Channel Preemption. This field resets to - 0. +/*! ECP - Enable Channel Preemption. This field resets to 0. * 0b0..Channel n cannot be suspended by a higher priority channel's service request. * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. */ @@ -12833,16 +12854,14 @@ typedef struct { #define DMA_DCHPRI23_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_GRPPRI_SHIFT)) & DMA_DCHPRI23_GRPPRI_MASK) #define DMA_DCHPRI23_DPA_MASK (0x40U) #define DMA_DCHPRI23_DPA_SHIFT (6U) -/*! DPA - Disable Preempt Ability. This field resets to - 0. +/*! DPA - Disable Preempt Ability. This field resets to 0. * 0b0..Channel n can suspend a lower priority channel. * 0b1..Channel n cannot suspend any channel, regardless of channel priority. */ #define DMA_DCHPRI23_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_DPA_SHIFT)) & DMA_DCHPRI23_DPA_MASK) #define DMA_DCHPRI23_ECP_MASK (0x80U) #define DMA_DCHPRI23_ECP_SHIFT (7U) -/*! ECP - Enable Channel Preemption. This field resets to - 0. +/*! ECP - Enable Channel Preemption. This field resets to 0. * 0b0..Channel n cannot be suspended by a higher priority channel's service request. * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. */ @@ -12859,16 +12878,14 @@ typedef struct { #define DMA_DCHPRI22_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_GRPPRI_SHIFT)) & DMA_DCHPRI22_GRPPRI_MASK) #define DMA_DCHPRI22_DPA_MASK (0x40U) #define DMA_DCHPRI22_DPA_SHIFT (6U) -/*! DPA - Disable Preempt Ability. This field resets to - 0. +/*! DPA - Disable Preempt Ability. This field resets to 0. * 0b0..Channel n can suspend a lower priority channel. * 0b1..Channel n cannot suspend any channel, regardless of channel priority. */ #define DMA_DCHPRI22_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_DPA_SHIFT)) & DMA_DCHPRI22_DPA_MASK) #define DMA_DCHPRI22_ECP_MASK (0x80U) #define DMA_DCHPRI22_ECP_SHIFT (7U) -/*! ECP - Enable Channel Preemption. This field resets to - 0. +/*! ECP - Enable Channel Preemption. This field resets to 0. * 0b0..Channel n cannot be suspended by a higher priority channel's service request. * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. */ @@ -12885,16 +12902,14 @@ typedef struct { #define DMA_DCHPRI21_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_GRPPRI_SHIFT)) & DMA_DCHPRI21_GRPPRI_MASK) #define DMA_DCHPRI21_DPA_MASK (0x40U) #define DMA_DCHPRI21_DPA_SHIFT (6U) -/*! DPA - Disable Preempt Ability. This field resets to - 0. +/*! DPA - Disable Preempt Ability. This field resets to 0. * 0b0..Channel n can suspend a lower priority channel. * 0b1..Channel n cannot suspend any channel, regardless of channel priority. */ #define DMA_DCHPRI21_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_DPA_SHIFT)) & DMA_DCHPRI21_DPA_MASK) #define DMA_DCHPRI21_ECP_MASK (0x80U) #define DMA_DCHPRI21_ECP_SHIFT (7U) -/*! ECP - Enable Channel Preemption. This field resets to - 0. +/*! ECP - Enable Channel Preemption. This field resets to 0. * 0b0..Channel n cannot be suspended by a higher priority channel's service request. * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. */ @@ -12911,16 +12926,14 @@ typedef struct { #define DMA_DCHPRI20_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_GRPPRI_SHIFT)) & DMA_DCHPRI20_GRPPRI_MASK) #define DMA_DCHPRI20_DPA_MASK (0x40U) #define DMA_DCHPRI20_DPA_SHIFT (6U) -/*! DPA - Disable Preempt Ability. This field resets to - 0. +/*! DPA - Disable Preempt Ability. This field resets to 0. * 0b0..Channel n can suspend a lower priority channel. * 0b1..Channel n cannot suspend any channel, regardless of channel priority. */ #define DMA_DCHPRI20_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_DPA_SHIFT)) & DMA_DCHPRI20_DPA_MASK) #define DMA_DCHPRI20_ECP_MASK (0x80U) #define DMA_DCHPRI20_ECP_SHIFT (7U) -/*! ECP - Enable Channel Preemption. This field resets to - 0. +/*! ECP - Enable Channel Preemption. This field resets to 0. * 0b0..Channel n cannot be suspended by a higher priority channel's service request. * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. */ @@ -12937,16 +12950,14 @@ typedef struct { #define DMA_DCHPRI27_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_GRPPRI_SHIFT)) & DMA_DCHPRI27_GRPPRI_MASK) #define DMA_DCHPRI27_DPA_MASK (0x40U) #define DMA_DCHPRI27_DPA_SHIFT (6U) -/*! DPA - Disable Preempt Ability. This field resets to - 0. +/*! DPA - Disable Preempt Ability. This field resets to 0. * 0b0..Channel n can suspend a lower priority channel. * 0b1..Channel n cannot suspend any channel, regardless of channel priority. */ #define DMA_DCHPRI27_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_DPA_SHIFT)) & DMA_DCHPRI27_DPA_MASK) #define DMA_DCHPRI27_ECP_MASK (0x80U) #define DMA_DCHPRI27_ECP_SHIFT (7U) -/*! ECP - Enable Channel Preemption. This field resets to - 0. +/*! ECP - Enable Channel Preemption. This field resets to 0. * 0b0..Channel n cannot be suspended by a higher priority channel's service request. * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. */ @@ -12963,16 +12974,14 @@ typedef struct { #define DMA_DCHPRI26_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_GRPPRI_SHIFT)) & DMA_DCHPRI26_GRPPRI_MASK) #define DMA_DCHPRI26_DPA_MASK (0x40U) #define DMA_DCHPRI26_DPA_SHIFT (6U) -/*! DPA - Disable Preempt Ability. This field resets to - 0. +/*! DPA - Disable Preempt Ability. This field resets to 0. * 0b0..Channel n can suspend a lower priority channel. * 0b1..Channel n cannot suspend any channel, regardless of channel priority. */ #define DMA_DCHPRI26_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_DPA_SHIFT)) & DMA_DCHPRI26_DPA_MASK) #define DMA_DCHPRI26_ECP_MASK (0x80U) #define DMA_DCHPRI26_ECP_SHIFT (7U) -/*! ECP - Enable Channel Preemption. This field resets to - 0. +/*! ECP - Enable Channel Preemption. This field resets to 0. * 0b0..Channel n cannot be suspended by a higher priority channel's service request. * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. */ @@ -12989,16 +12998,14 @@ typedef struct { #define DMA_DCHPRI25_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_GRPPRI_SHIFT)) & DMA_DCHPRI25_GRPPRI_MASK) #define DMA_DCHPRI25_DPA_MASK (0x40U) #define DMA_DCHPRI25_DPA_SHIFT (6U) -/*! DPA - Disable Preempt Ability. This field resets to - 0. +/*! DPA - Disable Preempt Ability. This field resets to 0. * 0b0..Channel n can suspend a lower priority channel. * 0b1..Channel n cannot suspend any channel, regardless of channel priority. */ #define DMA_DCHPRI25_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_DPA_SHIFT)) & DMA_DCHPRI25_DPA_MASK) #define DMA_DCHPRI25_ECP_MASK (0x80U) #define DMA_DCHPRI25_ECP_SHIFT (7U) -/*! ECP - Enable Channel Preemption. This field resets to - 0. +/*! ECP - Enable Channel Preemption. This field resets to 0. * 0b0..Channel n cannot be suspended by a higher priority channel's service request. * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. */ @@ -13015,16 +13022,14 @@ typedef struct { #define DMA_DCHPRI24_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_GRPPRI_SHIFT)) & DMA_DCHPRI24_GRPPRI_MASK) #define DMA_DCHPRI24_DPA_MASK (0x40U) #define DMA_DCHPRI24_DPA_SHIFT (6U) -/*! DPA - Disable Preempt Ability. This field resets to - 0. +/*! DPA - Disable Preempt Ability. This field resets to 0. * 0b0..Channel n can suspend a lower priority channel. * 0b1..Channel n cannot suspend any channel, regardless of channel priority. */ #define DMA_DCHPRI24_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_DPA_SHIFT)) & DMA_DCHPRI24_DPA_MASK) #define DMA_DCHPRI24_ECP_MASK (0x80U) #define DMA_DCHPRI24_ECP_SHIFT (7U) -/*! ECP - Enable Channel Preemption. This field resets to - 0. +/*! ECP - Enable Channel Preemption. This field resets to 0. * 0b0..Channel n cannot be suspended by a higher priority channel's service request. * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. */ @@ -13041,16 +13046,14 @@ typedef struct { #define DMA_DCHPRI31_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_GRPPRI_SHIFT)) & DMA_DCHPRI31_GRPPRI_MASK) #define DMA_DCHPRI31_DPA_MASK (0x40U) #define DMA_DCHPRI31_DPA_SHIFT (6U) -/*! DPA - Disable Preempt Ability. This field resets to - 0. +/*! DPA - Disable Preempt Ability. This field resets to 0. * 0b0..Channel n can suspend a lower priority channel. * 0b1..Channel n cannot suspend any channel, regardless of channel priority. */ #define DMA_DCHPRI31_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_DPA_SHIFT)) & DMA_DCHPRI31_DPA_MASK) #define DMA_DCHPRI31_ECP_MASK (0x80U) #define DMA_DCHPRI31_ECP_SHIFT (7U) -/*! ECP - Enable Channel Preemption. This field resets to - 0. +/*! ECP - Enable Channel Preemption. This field resets to 0. * 0b0..Channel n cannot be suspended by a higher priority channel's service request. * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. */ @@ -13067,16 +13070,14 @@ typedef struct { #define DMA_DCHPRI30_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_GRPPRI_SHIFT)) & DMA_DCHPRI30_GRPPRI_MASK) #define DMA_DCHPRI30_DPA_MASK (0x40U) #define DMA_DCHPRI30_DPA_SHIFT (6U) -/*! DPA - Disable Preempt Ability. This field resets to - 0. +/*! DPA - Disable Preempt Ability. This field resets to 0. * 0b0..Channel n can suspend a lower priority channel. * 0b1..Channel n cannot suspend any channel, regardless of channel priority. */ #define DMA_DCHPRI30_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_DPA_SHIFT)) & DMA_DCHPRI30_DPA_MASK) #define DMA_DCHPRI30_ECP_MASK (0x80U) #define DMA_DCHPRI30_ECP_SHIFT (7U) -/*! ECP - Enable Channel Preemption. This field resets to - 0. +/*! ECP - Enable Channel Preemption. This field resets to 0. * 0b0..Channel n cannot be suspended by a higher priority channel's service request. * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. */ @@ -13093,16 +13094,14 @@ typedef struct { #define DMA_DCHPRI29_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_GRPPRI_SHIFT)) & DMA_DCHPRI29_GRPPRI_MASK) #define DMA_DCHPRI29_DPA_MASK (0x40U) #define DMA_DCHPRI29_DPA_SHIFT (6U) -/*! DPA - Disable Preempt Ability. This field resets to - 0. +/*! DPA - Disable Preempt Ability. This field resets to 0. * 0b0..Channel n can suspend a lower priority channel. * 0b1..Channel n cannot suspend any channel, regardless of channel priority. */ #define DMA_DCHPRI29_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_DPA_SHIFT)) & DMA_DCHPRI29_DPA_MASK) #define DMA_DCHPRI29_ECP_MASK (0x80U) #define DMA_DCHPRI29_ECP_SHIFT (7U) -/*! ECP - Enable Channel Preemption. This field resets to - 0. +/*! ECP - Enable Channel Preemption. This field resets to 0. * 0b0..Channel n cannot be suspended by a higher priority channel's service request. * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. */ @@ -13119,16 +13118,14 @@ typedef struct { #define DMA_DCHPRI28_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_GRPPRI_SHIFT)) & DMA_DCHPRI28_GRPPRI_MASK) #define DMA_DCHPRI28_DPA_MASK (0x40U) #define DMA_DCHPRI28_DPA_SHIFT (6U) -/*! DPA - Disable Preempt Ability. This field resets to - 0. +/*! DPA - Disable Preempt Ability. This field resets to 0. * 0b0..Channel n can suspend a lower priority channel. * 0b1..Channel n cannot suspend any channel, regardless of channel priority. */ #define DMA_DCHPRI28_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_DPA_SHIFT)) & DMA_DCHPRI28_DPA_MASK) #define DMA_DCHPRI28_ECP_MASK (0x80U) #define DMA_DCHPRI28_ECP_SHIFT (7U) -/*! ECP - Enable Channel Preemption. This field resets to - 0. +/*! ECP - Enable Channel Preemption. This field resets to 0. * 0b0..Channel n cannot be suspended by a higher priority channel's service request. * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. */ @@ -13169,6 +13166,9 @@ typedef struct { * 0b000..8-bit * 0b001..16-bit * 0b010..32-bit + * 0b011..64-bit + * 0b100..Reserved + * 0b101..32-byte burst (4 beats of 64 bits) * 0b110..Reserved * 0b111..Reserved */ @@ -13283,8 +13283,7 @@ typedef struct { #define DMA_CITER_ELINKNO_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKNO_CITER_SHIFT)) & DMA_CITER_ELINKNO_CITER_MASK) #define DMA_CITER_ELINKNO_ELINK_MASK (0x8000U) #define DMA_CITER_ELINKNO_ELINK_SHIFT (15U) -/*! ELINK - Enable channel-to-channel linking on minor-loop - complete +/*! ELINK - Enable channel-to-channel linking on minor-loop complete * 0b0..The channel-to-channel linking is disabled * 0b1..The channel-to-channel linking is enabled */ @@ -13304,8 +13303,7 @@ typedef struct { #define DMA_CITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_LINKCH_SHIFT)) & DMA_CITER_ELINKYES_LINKCH_MASK) #define DMA_CITER_ELINKYES_ELINK_MASK (0x8000U) #define DMA_CITER_ELINKYES_ELINK_SHIFT (15U) -/*! ELINK - Enable channel-to-channel linking on minor-loop - complete +/*! ELINK - Enable channel-to-channel linking on minor-loop complete * 0b0..The channel-to-channel linking is disabled * 0b1..The channel-to-channel linking is enabled */ @@ -13336,22 +13334,24 @@ typedef struct { #define DMA_CSR_START(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_START_SHIFT)) & DMA_CSR_START_MASK) #define DMA_CSR_INTMAJOR_MASK (0x2U) #define DMA_CSR_INTMAJOR_SHIFT (1U) -/*! INTMAJOR - Enable an interrupt when major iteration count - completes. +/*! INTMAJOR - Enable an interrupt when major iteration count completes. * 0b0..The end-of-major loop interrupt is disabled. * 0b1..The end-of-major loop interrupt is enabled. */ #define DMA_CSR_INTMAJOR(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_INTMAJOR_SHIFT)) & DMA_CSR_INTMAJOR_MASK) #define DMA_CSR_INTHALF_MASK (0x4U) #define DMA_CSR_INTHALF_SHIFT (2U) -/*! INTHALF - Enable an interrupt when major counter is half - complete. +/*! INTHALF - Enable an interrupt when major counter is half complete. * 0b0..The half-point interrupt is disabled. * 0b1..The half-point interrupt is enabled. */ #define DMA_CSR_INTHALF(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_INTHALF_SHIFT)) & DMA_CSR_INTHALF_MASK) #define DMA_CSR_DREQ_MASK (0x8U) #define DMA_CSR_DREQ_SHIFT (3U) +/*! DREQ - Disable Request + * 0b0..The channel's ERQ bit is not affected. + * 0b1..The channel's ERQ bit is cleared when the major loop is complete. + */ #define DMA_CSR_DREQ(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_DREQ_SHIFT)) & DMA_CSR_DREQ_MASK) #define DMA_CSR_ESG_MASK (0x10U) #define DMA_CSR_ESG_SHIFT (4U) @@ -13362,8 +13362,7 @@ typedef struct { #define DMA_CSR_ESG(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_ESG_SHIFT)) & DMA_CSR_ESG_MASK) #define DMA_CSR_MAJORELINK_MASK (0x20U) #define DMA_CSR_MAJORELINK_SHIFT (5U) -/*! MAJORELINK - Enable channel-to-channel linking on major loop - complete +/*! MAJORELINK - Enable channel-to-channel linking on major loop complete * 0b0..The channel-to-channel linking is disabled. * 0b1..The channel-to-channel linking is enabled. */ @@ -13398,8 +13397,7 @@ typedef struct { #define DMA_BITER_ELINKNO_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKNO_BITER_SHIFT)) & DMA_BITER_ELINKNO_BITER_MASK) #define DMA_BITER_ELINKNO_ELINK_MASK (0x8000U) #define DMA_BITER_ELINKNO_ELINK_SHIFT (15U) -/*! ELINK - Enables channel-to-channel linking on minor loop - complete +/*! ELINK - Enables channel-to-channel linking on minor loop complete * 0b0..The channel-to-channel linking is disabled * 0b1..The channel-to-channel linking is enabled */ @@ -13419,8 +13417,7 @@ typedef struct { #define DMA_BITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_LINKCH_SHIFT)) & DMA_BITER_ELINKYES_LINKCH_MASK) #define DMA_BITER_ELINKYES_ELINK_MASK (0x8000U) #define DMA_BITER_ELINKYES_ELINK_SHIFT (15U) -/*! ELINK - Enables channel-to-channel linking on minor loop - complete +/*! ELINK - Enables channel-to-channel linking on minor loop complete * 0b0..The channel-to-channel linking is disabled * 0b1..The channel-to-channel linking is enabled */ @@ -13484,9 +13481,7 @@ typedef struct { #define DMAMUX_CHCFG_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << DMAMUX_CHCFG_SOURCE_SHIFT)) & DMAMUX_CHCFG_SOURCE_MASK) #define DMAMUX_CHCFG_A_ON_MASK (0x20000000U) #define DMAMUX_CHCFG_A_ON_SHIFT (29U) -/*! A_ON - - DMA Channel Always Enable - +/*! A_ON - DMA Channel Always Enable * 0b0..DMA Channel Always ON function is disabled * 0b1..DMA Channel Always ON function is enabled */ @@ -13500,9 +13495,7 @@ typedef struct { #define DMAMUX_CHCFG_TRIG(x) (((uint32_t)(((uint32_t)(x)) << DMAMUX_CHCFG_TRIG_SHIFT)) & DMAMUX_CHCFG_TRIG_MASK) #define DMAMUX_CHCFG_ENBL_MASK (0x80000000U) #define DMAMUX_CHCFG_ENBL_SHIFT (31U) -/*! ENBL - - DMA Mux Channel Enable - +/*! ENBL - DMA Mux Channel Enable * 0b0..DMA Mux channel is disabled * 0b1..DMA Mux channel is enabled */ @@ -15699,6 +15692,8 @@ typedef struct { * 0b011..Reserved. * 0b100..Match Store mode. Shifter data is compared to SHIFTBUF content on expiration of the Timer. * 0b101..Match Continuous mode. Shifter data is continuously compared to SHIFTBUF contents. + * 0b110..State mode. SHIFTBUF contents are used for storing programmable state attributes. + * 0b111..Logic mode. SHIFTBUF contents are used for implementing programmable logic look up table. */ #define FLEXIO_SHIFTCTL_SMOD(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_SMOD_SHIFT)) & FLEXIO_SHIFTCTL_SMOD_MASK) #define FLEXIO_SHIFTCTL_PINPOL_MASK (0x80U) @@ -16025,9 +16020,7 @@ typedef struct { /** FLEXRAM - Register Layout Typedef */ typedef struct { __IO uint32_t TCM_CTRL; /**< TCM CRTL Register, offset: 0x0 */ - __IO uint32_t OCRAM_MAGIC_ADDR; /**< OCRAM Magic Address Register, offset: 0x4 */ - __IO uint32_t DTCM_MAGIC_ADDR; /**< DTCM Magic Address Register, offset: 0x8 */ - __IO uint32_t ITCM_MAGIC_ADDR; /**< ITCM Magic Address Register, offset: 0xC */ + uint8_t RESERVED_0[12]; __IO uint32_t INT_STATUS; /**< Interrupt Status Register, offset: 0x10 */ __IO uint32_t INT_STAT_EN; /**< Interrupt Status Enable Register, offset: 0x14 */ __IO uint32_t INT_SIG_EN; /**< Interrupt Enable Register, offset: 0x18 */ @@ -16061,85 +16054,10 @@ typedef struct { #define FLEXRAM_TCM_CTRL_FORCE_CLK_ON_MASK (0x4U) #define FLEXRAM_TCM_CTRL_FORCE_CLK_ON_SHIFT (2U) #define FLEXRAM_TCM_CTRL_FORCE_CLK_ON(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_TCM_CTRL_FORCE_CLK_ON_SHIFT)) & FLEXRAM_TCM_CTRL_FORCE_CLK_ON_MASK) -#define FLEXRAM_TCM_CTRL_Reserved_MASK (0xFFFFFFF8U) -#define FLEXRAM_TCM_CTRL_Reserved_SHIFT (3U) -#define FLEXRAM_TCM_CTRL_Reserved(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_TCM_CTRL_Reserved_SHIFT)) & FLEXRAM_TCM_CTRL_Reserved_MASK) -/*! @} */ - -/*! @name OCRAM_MAGIC_ADDR - OCRAM Magic Address Register */ -/*! @{ */ -#define FLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_WR_RD_SEL_MASK (0x1U) -#define FLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_WR_RD_SEL_SHIFT (0U) -/*! OCRAM_WR_RD_SEL - OCRAM Write Read Select - * 0b0..When OCRAM read access hits magic address, it will generate interrupt. - * 0b1..When OCRAM write access hits magic address, it will generate interrupt. - */ -#define FLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_WR_RD_SEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_WR_RD_SEL_SHIFT)) & FLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_WR_RD_SEL_MASK) -#define FLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_MAGIC_ADDR_MASK (0x1FFFEU) -#define FLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_MAGIC_ADDR_SHIFT (1U) -#define FLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_MAGIC_ADDR(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_MAGIC_ADDR_SHIFT)) & FLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_MAGIC_ADDR_MASK) -#define FLEXRAM_OCRAM_MAGIC_ADDR_Reserved_MASK (0xFFFE0000U) -#define FLEXRAM_OCRAM_MAGIC_ADDR_Reserved_SHIFT (17U) -#define FLEXRAM_OCRAM_MAGIC_ADDR_Reserved(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_OCRAM_MAGIC_ADDR_Reserved_SHIFT)) & FLEXRAM_OCRAM_MAGIC_ADDR_Reserved_MASK) -/*! @} */ - -/*! @name DTCM_MAGIC_ADDR - DTCM Magic Address Register */ -/*! @{ */ -#define FLEXRAM_DTCM_MAGIC_ADDR_DTCM_WR_RD_SEL_MASK (0x1U) -#define FLEXRAM_DTCM_MAGIC_ADDR_DTCM_WR_RD_SEL_SHIFT (0U) -/*! DTCM_WR_RD_SEL - DTCM Write Read Select - * 0b0..When DTCM read access hits magic address, it will generate interrupt. - * 0b1..When DTCM write access hits magic address, it will generate interrupt. - */ -#define FLEXRAM_DTCM_MAGIC_ADDR_DTCM_WR_RD_SEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_DTCM_MAGIC_ADDR_DTCM_WR_RD_SEL_SHIFT)) & FLEXRAM_DTCM_MAGIC_ADDR_DTCM_WR_RD_SEL_MASK) -#define FLEXRAM_DTCM_MAGIC_ADDR_DTCM_MAGIC_ADDR_MASK (0x1FFFEU) -#define FLEXRAM_DTCM_MAGIC_ADDR_DTCM_MAGIC_ADDR_SHIFT (1U) -#define FLEXRAM_DTCM_MAGIC_ADDR_DTCM_MAGIC_ADDR(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_DTCM_MAGIC_ADDR_DTCM_MAGIC_ADDR_SHIFT)) & FLEXRAM_DTCM_MAGIC_ADDR_DTCM_MAGIC_ADDR_MASK) -#define FLEXRAM_DTCM_MAGIC_ADDR_Reserved_MASK (0xFFFE0000U) -#define FLEXRAM_DTCM_MAGIC_ADDR_Reserved_SHIFT (17U) -#define FLEXRAM_DTCM_MAGIC_ADDR_Reserved(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_DTCM_MAGIC_ADDR_Reserved_SHIFT)) & FLEXRAM_DTCM_MAGIC_ADDR_Reserved_MASK) -/*! @} */ - -/*! @name ITCM_MAGIC_ADDR - ITCM Magic Address Register */ -/*! @{ */ -#define FLEXRAM_ITCM_MAGIC_ADDR_ITCM_WR_RD_SEL_MASK (0x1U) -#define FLEXRAM_ITCM_MAGIC_ADDR_ITCM_WR_RD_SEL_SHIFT (0U) -/*! ITCM_WR_RD_SEL - ITCM Write Read Select - * 0b0..When ITCM read access hits magic address, it will generate interrupt. - * 0b1..When ITCM write access hits magic address, it will generate interrupt. - */ -#define FLEXRAM_ITCM_MAGIC_ADDR_ITCM_WR_RD_SEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_ITCM_MAGIC_ADDR_ITCM_WR_RD_SEL_SHIFT)) & FLEXRAM_ITCM_MAGIC_ADDR_ITCM_WR_RD_SEL_MASK) -#define FLEXRAM_ITCM_MAGIC_ADDR_ITCM_MAGIC_ADDR_MASK (0x1FFFEU) -#define FLEXRAM_ITCM_MAGIC_ADDR_ITCM_MAGIC_ADDR_SHIFT (1U) -#define FLEXRAM_ITCM_MAGIC_ADDR_ITCM_MAGIC_ADDR(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_ITCM_MAGIC_ADDR_ITCM_MAGIC_ADDR_SHIFT)) & FLEXRAM_ITCM_MAGIC_ADDR_ITCM_MAGIC_ADDR_MASK) -#define FLEXRAM_ITCM_MAGIC_ADDR_Reserved_MASK (0xFFFE0000U) -#define FLEXRAM_ITCM_MAGIC_ADDR_Reserved_SHIFT (17U) -#define FLEXRAM_ITCM_MAGIC_ADDR_Reserved(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_ITCM_MAGIC_ADDR_Reserved_SHIFT)) & FLEXRAM_ITCM_MAGIC_ADDR_Reserved_MASK) /*! @} */ /*! @name INT_STATUS - Interrupt Status Register */ /*! @{ */ -#define FLEXRAM_INT_STATUS_ITCM_MAM_STATUS_MASK (0x1U) -#define FLEXRAM_INT_STATUS_ITCM_MAM_STATUS_SHIFT (0U) -/*! ITCM_MAM_STATUS - ITCM Magic Address Match Status - * 0b0..ITCM did not access magic address. - * 0b1..ITCM accessed magic address. - */ -#define FLEXRAM_INT_STATUS_ITCM_MAM_STATUS(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_ITCM_MAM_STATUS_SHIFT)) & FLEXRAM_INT_STATUS_ITCM_MAM_STATUS_MASK) -#define FLEXRAM_INT_STATUS_DTCM_MAM_STATUS_MASK (0x2U) -#define FLEXRAM_INT_STATUS_DTCM_MAM_STATUS_SHIFT (1U) -/*! DTCM_MAM_STATUS - DTCM Magic Address Match Status - * 0b0..DTCM did not access magic address. - * 0b1..DTCM accessed magic address. - */ -#define FLEXRAM_INT_STATUS_DTCM_MAM_STATUS(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_DTCM_MAM_STATUS_SHIFT)) & FLEXRAM_INT_STATUS_DTCM_MAM_STATUS_MASK) -#define FLEXRAM_INT_STATUS_OCRAM_MAM_STATUS_MASK (0x4U) -#define FLEXRAM_INT_STATUS_OCRAM_MAM_STATUS_SHIFT (2U) -/*! OCRAM_MAM_STATUS - OCRAM Magic Address Match Status - * 0b0..OCRAM did not access magic address. - * 0b1..OCRAM accessed magic address. - */ -#define FLEXRAM_INT_STATUS_OCRAM_MAM_STATUS(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_OCRAM_MAM_STATUS_SHIFT)) & FLEXRAM_INT_STATUS_OCRAM_MAM_STATUS_MASK) #define FLEXRAM_INT_STATUS_ITCM_ERR_STATUS_MASK (0x8U) #define FLEXRAM_INT_STATUS_ITCM_ERR_STATUS_SHIFT (3U) /*! ITCM_ERR_STATUS - ITCM Access Error Status @@ -16161,34 +16079,10 @@ typedef struct { * 0b1..OCRAM access error happens. */ #define FLEXRAM_INT_STATUS_OCRAM_ERR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_OCRAM_ERR_STATUS_SHIFT)) & FLEXRAM_INT_STATUS_OCRAM_ERR_STATUS_MASK) -#define FLEXRAM_INT_STATUS_Reserved_MASK (0xFFFFFFC0U) -#define FLEXRAM_INT_STATUS_Reserved_SHIFT (6U) -#define FLEXRAM_INT_STATUS_Reserved(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_Reserved_SHIFT)) & FLEXRAM_INT_STATUS_Reserved_MASK) /*! @} */ /*! @name INT_STAT_EN - Interrupt Status Enable Register */ /*! @{ */ -#define FLEXRAM_INT_STAT_EN_ITCM_MAM_STAT_EN_MASK (0x1U) -#define FLEXRAM_INT_STAT_EN_ITCM_MAM_STAT_EN_SHIFT (0U) -/*! ITCM_MAM_STAT_EN - ITCM Magic Address Match Status Enable - * 0b0..Masked - * 0b1..Enabled - */ -#define FLEXRAM_INT_STAT_EN_ITCM_MAM_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_ITCM_MAM_STAT_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_ITCM_MAM_STAT_EN_MASK) -#define FLEXRAM_INT_STAT_EN_DTCM_MAM_STAT_EN_MASK (0x2U) -#define FLEXRAM_INT_STAT_EN_DTCM_MAM_STAT_EN_SHIFT (1U) -/*! DTCM_MAM_STAT_EN - DTCM Magic Address Match Status Enable - * 0b0..Masked - * 0b1..Enabled - */ -#define FLEXRAM_INT_STAT_EN_DTCM_MAM_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_DTCM_MAM_STAT_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_DTCM_MAM_STAT_EN_MASK) -#define FLEXRAM_INT_STAT_EN_OCRAM_MAM_STAT_EN_MASK (0x4U) -#define FLEXRAM_INT_STAT_EN_OCRAM_MAM_STAT_EN_SHIFT (2U) -/*! OCRAM_MAM_STAT_EN - OCRAM Magic Address Match Status Enable - * 0b0..Masked - * 0b1..Enabled - */ -#define FLEXRAM_INT_STAT_EN_OCRAM_MAM_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_OCRAM_MAM_STAT_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_OCRAM_MAM_STAT_EN_MASK) #define FLEXRAM_INT_STAT_EN_ITCM_ERR_STAT_EN_MASK (0x8U) #define FLEXRAM_INT_STAT_EN_ITCM_ERR_STAT_EN_SHIFT (3U) /*! ITCM_ERR_STAT_EN - ITCM Access Error Status Enable @@ -16210,34 +16104,10 @@ typedef struct { * 0b1..Enabled */ #define FLEXRAM_INT_STAT_EN_OCRAM_ERR_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_OCRAM_ERR_STAT_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_OCRAM_ERR_STAT_EN_MASK) -#define FLEXRAM_INT_STAT_EN_Reserved_MASK (0xFFFFFFC0U) -#define FLEXRAM_INT_STAT_EN_Reserved_SHIFT (6U) -#define FLEXRAM_INT_STAT_EN_Reserved(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_Reserved_SHIFT)) & FLEXRAM_INT_STAT_EN_Reserved_MASK) /*! @} */ /*! @name INT_SIG_EN - Interrupt Enable Register */ /*! @{ */ -#define FLEXRAM_INT_SIG_EN_ITCM_MAM_SIG_EN_MASK (0x1U) -#define FLEXRAM_INT_SIG_EN_ITCM_MAM_SIG_EN_SHIFT (0U) -/*! ITCM_MAM_SIG_EN - ITCM Magic Address Match Interrupt Enable - * 0b0..Masked - * 0b1..Enabled - */ -#define FLEXRAM_INT_SIG_EN_ITCM_MAM_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_ITCM_MAM_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_ITCM_MAM_SIG_EN_MASK) -#define FLEXRAM_INT_SIG_EN_DTCM_MAM_SIG_EN_MASK (0x2U) -#define FLEXRAM_INT_SIG_EN_DTCM_MAM_SIG_EN_SHIFT (1U) -/*! DTCM_MAM_SIG_EN - DTCM Magic Address Match Interrupt Enable - * 0b0..Masked - * 0b1..Enabled - */ -#define FLEXRAM_INT_SIG_EN_DTCM_MAM_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_DTCM_MAM_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_DTCM_MAM_SIG_EN_MASK) -#define FLEXRAM_INT_SIG_EN_OCRAM_MAM_SIG_EN_MASK (0x4U) -#define FLEXRAM_INT_SIG_EN_OCRAM_MAM_SIG_EN_SHIFT (2U) -/*! OCRAM_MAM_SIG_EN - OCRAM Magic Address Match Interrupt Enable - * 0b0..Masked - * 0b1..Enabled - */ -#define FLEXRAM_INT_SIG_EN_OCRAM_MAM_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_OCRAM_MAM_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_OCRAM_MAM_SIG_EN_MASK) #define FLEXRAM_INT_SIG_EN_ITCM_ERR_SIG_EN_MASK (0x8U) #define FLEXRAM_INT_SIG_EN_ITCM_ERR_SIG_EN_SHIFT (3U) /*! ITCM_ERR_SIG_EN - ITCM Access Error Interrupt Enable @@ -16259,9 +16129,6 @@ typedef struct { * 0b1..Enabled */ #define FLEXRAM_INT_SIG_EN_OCRAM_ERR_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_OCRAM_ERR_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_OCRAM_ERR_SIG_EN_MASK) -#define FLEXRAM_INT_SIG_EN_Reserved_MASK (0xFFFFFFC0U) -#define FLEXRAM_INT_SIG_EN_Reserved_SHIFT (6U) -#define FLEXRAM_INT_SIG_EN_Reserved(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_Reserved_SHIFT)) & FLEXRAM_INT_SIG_EN_Reserved_MASK) /*! @} */ @@ -16355,7 +16222,6 @@ typedef struct { #define FLEXSPI_MCR0_RXCLKSRC_MASK (0x30U) #define FLEXSPI_MCR0_RXCLKSRC_SHIFT (4U) /*! RXCLKSRC - Sample Clock source selection for Flash Reading - * 0b00..Dummy Read strobe generated by FlexSPI Controller and loopback internally. * 0b01..Dummy Read strobe generated by FlexSPI Controller and loopback from DQS pad. * 0b10..Reserved @@ -16399,10 +16265,7 @@ typedef struct { #define FLEXSPI_MCR0_COMBINATIONEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_COMBINATIONEN_SHIFT)) & FLEXSPI_MCR0_COMBINATIONEN_MASK) #define FLEXSPI_MCR0_SCKFREERUNEN_MASK (0x4000U) #define FLEXSPI_MCR0_SCKFREERUNEN_SHIFT (14U) -/*! SCKFREERUNEN - This bit is used to force SCK output free-running. For FPGA applications, external device may use SCK clock - as reference clock to its internal PLL. If SCK free-running is enabled, data sampling with loopback clock from SCK pad is not supported (MCR0[RXCLKSRC]=2). - - +/*! SCKFREERUNEN - This bit is used to force SCK output free-running. For FPGA applications, external device may use SCK clock as reference clock to its internal PLL. If SCK free-running is enabled, data sampling with loopback clock from SCK pad is not supported (MCR0[RXCLKSRC]=2). * 0b0..Disable. * 0b1..Enable. */ @@ -16446,8 +16309,7 @@ typedef struct { #define FLEXSPI_MCR2_SAMEDEVICEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_SAMEDEVICEEN_SHIFT)) & FLEXSPI_MCR2_SAMEDEVICEEN_MASK) #define FLEXSPI_MCR2_SCKBDIFFOPT_MASK (0x80000U) #define FLEXSPI_MCR2_SCKBDIFFOPT_SHIFT (19U) -/*! SCKBDIFFOPT - SCKB pad can be used as SCKA differential clock output (inverted clock to SCKA). In this case, port B flash access is not available. - After change the value of this feild, MCR0[SWRESET] should be set. +/*! SCKBDIFFOPT - SCKB pad can be used as SCKA differential clock output (inverted clock to SCKA). In this case, port B flash access is not available. After change the value of this feild, MCR0[SWRESET] should be set. * 0b1..SCKB pad is used as port A SCK inverted clock output (Differential clock to SCKA). Port B flash access is not available. * 0b0..SCKB pad is used as port B SCK clock output. Port B flash access is available. */ @@ -16475,7 +16337,7 @@ typedef struct { #define FLEXSPI_AHBCR_CACHABLEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_CACHABLEEN_SHIFT)) & FLEXSPI_AHBCR_CACHABLEEN_MASK) #define FLEXSPI_AHBCR_BUFFERABLEEN_MASK (0x10U) #define FLEXSPI_AHBCR_BUFFERABLEEN_SHIFT (4U) -/*! BUFFERABLEEN - Enable AHB bus bufferable write access support. This field affects the last beat of AHB write access, refer for more details about AHB bufferable write. +/*! BUFFERABLEEN - Enable AHB bus bufferable write access support. This field affects the last beat of AHB write access, refer for more details about AHB bufferable write. * 0b0..Disabled. For all AHB write access (no matter bufferable or non-bufferable ), FlexSPI will return AHB Bus ready after all data is transmitted to External device and AHB command finished. * 0b1..Enabled. For AHB bufferable write access, FlexSPI will return AHB Bus ready when the AHB command is granted by arbitrator and will not wait for AHB command finished. */ @@ -16804,9 +16666,7 @@ typedef struct { #define FLEXSPI_STS0_ARBIDLE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS0_ARBIDLE_SHIFT)) & FLEXSPI_STS0_ARBIDLE_MASK) #define FLEXSPI_STS0_ARBCMDSRC_MASK (0xCU) #define FLEXSPI_STS0_ARBCMDSRC_SHIFT (2U) -/*! ARBCMDSRC - This status field indicates the trigger source of current command sequence granted by arbitrator. - This field value is meaningless when ARB_CTL is not busy (STS0[ARBIDLE]=0x1). - +/*! ARBCMDSRC - This status field indicates the trigger source of current command sequence granted by arbitrator. This field value is meaningless when ARB_CTL is not busy (STS0[ARBIDLE]=0x1). * 0b00..Triggered by AHB read command (triggered by AHB read). * 0b01..Triggered by AHB write command (triggered by AHB Write). * 0b10..Triggered by IP command (triggered by setting register bit IPCMD.TRG). @@ -16823,7 +16683,6 @@ typedef struct { #define FLEXSPI_STS1_AHBCMDERRCODE_MASK (0xF00U) #define FLEXSPI_STS1_AHBCMDERRCODE_SHIFT (8U) /*! AHBCMDERRCODE - Indicates the Error Code when AHB command Error detected. This field will be cleared when INTR[AHBCMDERR] is write-1-clear(w1c). - * 0b0000..No error. * 0b0010..AHB Write command with JMP_ON_CS instruction used in the sequence. * 0b0011..There is unknown instruction opcode in the sequence. @@ -18672,19 +18531,22 @@ typedef struct { #define IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_MASK (0xFU) /* Merged from fields with different position or width, of widths (3, 4), largest definition used */ #define IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_SHIFT (0U) /*! MUX_MODE - MUX Mode Select Field. - * 0b0000..Select mux mode: ALT0 mux port: SEMC_ADDR00 of instance: semc - * 0b0001..Select mux mode: ALT1 mux port: FLEXPWM2_PWMB01 of instance: flexpwm2 - * 0b0010..Select mux mode: ALT2 mux port: SAI2_RX_SYNC of instance: sai2 - * 0b0011..Select mux mode: ALT3 mux port: FLEXCAN2_TX of instance: flexcan2 - * 0b0100..Select mux mode: ALT4 mux port: FLEXIO1_FLEXIO09 of instance: flexio1 - * 0b0101..Select mux mode: ALT5 mux port: GPIO4_IO09 of instance: gpio4 - * 0b1000..Select mux mode: ALT8 mux port: FLEXSPI2_B_SS1_B of instance: flexspi2 + * 0b0000..Select mux mode: ALT0 mux port: USB_OTG1_PWR of instance: usb + * 0b0001..Select mux mode: ALT1 mux port: QTIMER3_TIMER1 of instance: qtimer3 + * 0b0010..Select mux mode: ALT2 mux port: LPUART2_RTS_B of instance: lpuart2 + * 0b0011..Select mux mode: ALT3 mux port: LPI2C1_SDA of instance: lpi2c1 + * 0b0100..Select mux mode: ALT4 mux port: CCM_PMIC_READY of instance: ccm + * 0b0101..Select mux mode: ALT5 mux port: GPIO1_IO17 of instance: gpio1 + * 0b0110..Select mux mode: ALT6 mux port: USDHC1_VSELECT of instance: usdhc1 + * 0b0111..Select mux mode: ALT7 mux port: KPP_COL07 of instance: kpp + * 0b1000..Select mux mode: ALT8 mux port: ENET2_1588_EVENT0_IN of instance: enet2 + * 0b1001..Select mux mode: ALT9 mux port: FLEXIO3_FLEXIO01 of instance: flexio3 */ #define IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_SHIFT)) & IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_MASK) /* Merged from fields with different position or width, of widths (3, 4), largest definition used */ #define IOMUXC_SW_MUX_CTL_PAD_SION_MASK (0x10U) #define IOMUXC_SW_MUX_CTL_PAD_SION_SHIFT (4U) /*! SION - Software Input On Field. - * 0b1..Force input path of pad GPIO_EMC_00 + * 0b1..Force input path of pad GPIO_SD_B1_11 * 0b0..Input Path is determined by functionality */ #define IOMUXC_SW_MUX_CTL_PAD_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_MUX_CTL_PAD_SION_SHIFT)) & IOMUXC_SW_MUX_CTL_PAD_SION_MASK) @@ -18788,13 +18650,13 @@ typedef struct { #define IOMUXC_SW_MUX_CTL_PAD_1_MUX_MODE_MASK (0x7U) #define IOMUXC_SW_MUX_CTL_PAD_1_MUX_MODE_SHIFT (0U) /*! MUX_MODE - MUX Mode Select Field. - * 0b000..Select mux mode: ALT0 mux port: FLEXSPI2_B_SCLK of instance: flexspi2 + * 0b000..Select mux mode: ALT0 mux port: FLEXSPI2_B_DATA03 of instance: flexspi2 */ #define IOMUXC_SW_MUX_CTL_PAD_1_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_MUX_CTL_PAD_1_MUX_MODE_SHIFT)) & IOMUXC_SW_MUX_CTL_PAD_1_MUX_MODE_MASK) #define IOMUXC_SW_MUX_CTL_PAD_1_SION_MASK (0x10U) #define IOMUXC_SW_MUX_CTL_PAD_1_SION_SHIFT (4U) /*! SION - Software Input On Field. - * 0b1..Force input path of pad GPIO_SPI_B0_00 + * 0b1..Force input path of pad GPIO_SPI_B1_07 * 0b0..Input Path is determined by functionality */ #define IOMUXC_SW_MUX_CTL_PAD_1_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_MUX_CTL_PAD_1_SION_SHIFT)) & IOMUXC_SW_MUX_CTL_PAD_1_SION_MASK) @@ -18881,9 +18743,10 @@ typedef struct { #define IOMUXC_SELECT_INPUT_1_DAISY_MASK (0x3U) /* Merged from fields with different position or width, of widths (1, 2), largest definition used */ #define IOMUXC_SELECT_INPUT_1_DAISY_SHIFT (0U) /*! DAISY - Selecting Pads Involved in Daisy Chain. - * 0b00..Selecting Pad: GPIO_EMC_33 for Mode: ALT9 - * 0b01..Selecting Pad: GPIO_SD_B0_01 for Mode: ALT9 - * 0b10..Selecting Pad: GPIO_B0_15 for Mode: ALT9 + * 0b00..Selecting Pad: GPIO_SD_B0_00 for Mode: ALT9 + * 0b01..Selecting Pad: GPIO_EMC_39 for Mode: ALT9 + * 0b10..Selecting Pad: GPIO_AD_B0_09 for Mode: ALT9 + * 0b11..Selecting Pad: GPIO_B1_13 for Mode: ALT8 */ #define IOMUXC_SELECT_INPUT_1_DAISY(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SELECT_INPUT_1_DAISY_SHIFT)) & IOMUXC_SELECT_INPUT_1_DAISY_MASK) /* Merged from fields with different position or width, of widths (1, 2), largest definition used */ /*! @} */ @@ -20616,9 +20479,6 @@ typedef struct { * 0b1..use FLEXRAM_BANK_CFG to config */ #define IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL_SHIFT)) & IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL_MASK) -#define IOMUXC_GPR_GPR16_CM7_INIT_VTOR_MASK (0xFFFFFF80U) -#define IOMUXC_GPR_GPR16_CM7_INIT_VTOR_SHIFT (7U) -#define IOMUXC_GPR_GPR16_CM7_INIT_VTOR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR16_CM7_INIT_VTOR_SHIFT)) & IOMUXC_GPR_GPR16_CM7_INIT_VTOR_MASK) /*! @} */ /*! @name GPR17 - GPR17 General Purpose Register */ @@ -23275,6 +23135,7 @@ typedef struct { * 0b00..Address Match Wakeup * 0b01..Idle Match Wakeup * 0b10..Match On and Match Off + * 0b11..Enables RWU on Data Match and Match On/Off for transmitter CTS input */ #define LPUART_BAUD_MATCFG(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MATCFG_SHIFT)) & LPUART_BAUD_MATCFG_MASK) #define LPUART_BAUD_RIDMAE_MASK (0x100000U) @@ -23792,6 +23653,7 @@ typedef struct { #define LPUART_MODIR_RXRTSE_SHIFT (3U) /*! RXRTSE - Receiver request-to-send enable * 0b0..The receiver has no effect on RTS. + * 0b1..RTS is deasserted if the receiver data register is full or a start bit has been detected that would cause the receiver data register to become full. RTS is asserted if the receiver data register is not full and has not detected a start bit that would cause the receiver data register to become full. */ #define LPUART_MODIR_RXRTSE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_RXRTSE_SHIFT)) & LPUART_MODIR_RXRTSE_MASK) #define LPUART_MODIR_TXCTSC_MASK (0x10U) @@ -24072,11 +23934,11 @@ typedef struct { uint8_t RESERVED_20[12]; __IO uint32_t MEM4; /**< Value of OTP Bank1 Word4 (Memory Related Info.), offset: 0x4C0 */ uint8_t RESERVED_21[12]; - __IO uint32_t ANA0; /**< Value of OTP Bank1 Word5 (Analog Info.), offset: 0x4D0 */ + __IO uint32_t ANA0; /**< Value of OTP Bank1 Word5 (Memory Related Info.), offset: 0x4D0 */ uint8_t RESERVED_22[12]; - __IO uint32_t ANA1; /**< Value of OTP Bank1 Word6 (Analog Info.), offset: 0x4E0 */ + __IO uint32_t ANA1; /**< Value of OTP Bank1 Word6 (General Purpose Customer Defined Info.), offset: 0x4E0 */ uint8_t RESERVED_23[12]; - __IO uint32_t ANA2; /**< Value of OTP Bank1 Word7 (Analog Info.), offset: 0x4F0 */ + __IO uint32_t ANA2; /**< Value of OTP Bank1 Word7 (General Purpose Customer Defined Info.), offset: 0x4F0 */ uint8_t RESERVED_24[12]; __IO uint32_t OTPMK0; /**< Value of OTP Bank2 Word0 (OTPMK Key), offset: 0x500 */ uint8_t RESERVED_25[12]; @@ -24118,7 +23980,7 @@ typedef struct { uint8_t RESERVED_43[12]; __IO uint32_t MAC1; /**< Value of OTP Bank4 Word3 (MAC Address), offset: 0x630 */ uint8_t RESERVED_44[12]; - __IO uint32_t MAC2; /**< Value of OTP Bank4 Word4 (MAC Address), offset: 0x640 */ + __IO uint32_t MAC2; /**< Value of OTP Bank4 Word4 (MAC2 Address), offset: 0x640 */ uint8_t RESERVED_45[12]; __IO uint32_t OTPMK_CRC32; /**< Value of OTP Bank4 Word5 (CRC Key), offset: 0x650 */ uint8_t RESERVED_46[12]; @@ -24509,9 +24371,6 @@ typedef struct { #define OCOTP_LOCK_GP2_MASK (0x3000U) #define OCOTP_LOCK_GP2_SHIFT (12U) #define OCOTP_LOCK_GP2(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_GP2_SHIFT)) & OCOTP_LOCK_GP2_MASK) -#define OCOTP_LOCK_SRK_MASK (0x4000U) -#define OCOTP_LOCK_SRK_SHIFT (14U) -#define OCOTP_LOCK_SRK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_SRK_SHIFT)) & OCOTP_LOCK_SRK_MASK) #define OCOTP_LOCK_ROM_PATCH_MASK (0x8000U) #define OCOTP_LOCK_ROM_PATCH_SHIFT (15U) #define OCOTP_LOCK_ROM_PATCH(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_ROM_PATCH_SHIFT)) & OCOTP_LOCK_ROM_PATCH_MASK) @@ -24631,21 +24490,21 @@ typedef struct { #define OCOTP_MEM4_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MEM4_BITS_SHIFT)) & OCOTP_MEM4_BITS_MASK) /*! @} */ -/*! @name ANA0 - Value of OTP Bank1 Word5 (Analog Info.) */ +/*! @name ANA0 - Value of OTP Bank1 Word5 (Memory Related Info.) */ /*! @{ */ #define OCOTP_ANA0_BITS_MASK (0xFFFFFFFFU) #define OCOTP_ANA0_BITS_SHIFT (0U) #define OCOTP_ANA0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_ANA0_BITS_SHIFT)) & OCOTP_ANA0_BITS_MASK) /*! @} */ -/*! @name ANA1 - Value of OTP Bank1 Word6 (Analog Info.) */ +/*! @name ANA1 - Value of OTP Bank1 Word6 (General Purpose Customer Defined Info.) */ /*! @{ */ #define OCOTP_ANA1_BITS_MASK (0xFFFFFFFFU) #define OCOTP_ANA1_BITS_SHIFT (0U) #define OCOTP_ANA1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_ANA1_BITS_SHIFT)) & OCOTP_ANA1_BITS_MASK) /*! @} */ -/*! @name ANA2 - Value of OTP Bank1 Word7 (Analog Info.) */ +/*! @name ANA2 - Value of OTP Bank1 Word7 (General Purpose Customer Defined Info.) */ /*! @{ */ #define OCOTP_ANA2_BITS_MASK (0xFFFFFFFFU) #define OCOTP_ANA2_BITS_SHIFT (0U) @@ -24792,7 +24651,7 @@ typedef struct { #define OCOTP_MAC1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MAC1_BITS_SHIFT)) & OCOTP_MAC1_BITS_MASK) /*! @} */ -/*! @name MAC2 - Value of OTP Bank4 Word4 (MAC Address) */ +/*! @name MAC2 - Value of OTP Bank4 Word4 (MAC2 Address) */ /*! @{ */ #define OCOTP_MAC2_BITS_MASK (0xFFFFFFFFU) #define OCOTP_MAC2_BITS_SHIFT (0U) @@ -27648,6 +27507,16 @@ typedef struct { #define PWM_CTRL_SPLIT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_SPLIT_SHIFT)) & PWM_CTRL_SPLIT_MASK) #define PWM_CTRL_PRSC_MASK (0x70U) #define PWM_CTRL_PRSC_SHIFT (4U) +/*! PRSC - Prescaler + * 0b000..PWM clock frequency = fclk + * 0b001..PWM clock frequency = fclk/2 + * 0b010..PWM clock frequency = fclk/4 + * 0b011..PWM clock frequency = fclk/8 + * 0b100..PWM clock frequency = fclk/16 + * 0b101..PWM clock frequency = fclk/32 + * 0b110..PWM clock frequency = fclk/64 + * 0b111..PWM clock frequency = fclk/128 + */ #define PWM_CTRL_PRSC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_PRSC_SHIFT)) & PWM_CTRL_PRSC_MASK) #define PWM_CTRL_COMPMODE_MASK (0x80U) #define PWM_CTRL_COMPMODE_SHIFT (7U) @@ -28074,6 +27943,7 @@ typedef struct { #define PWM_DMAEN_VALDE_SHIFT (9U) /*! VALDE - Value Registers DMA Enable * 0b0..DMA write requests disabled + * 0b1..DMA write requests for the VALx and FRACVALx registers enabled */ #define PWM_DMAEN_VALDE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_VALDE_SHIFT)) & PWM_DMAEN_VALDE_MASK) /*! @} */ @@ -28175,6 +28045,10 @@ typedef struct { #define PWM_CAPTCTRLA_ARMA(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_ARMA_SHIFT)) & PWM_CAPTCTRLA_ARMA_MASK) #define PWM_CAPTCTRLA_ONESHOTA_MASK (0x2U) #define PWM_CAPTCTRLA_ONESHOTA_SHIFT (1U) +/*! ONESHOTA - One Shot Mode A + * 0b0..Free running mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after CAPTCTRLA[ARMA] is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and capture circuit 0 is re-armed. The process continues indefinitely.If only one of the capture circuits is enabled, then captures continue indefinitely on the enabled capture circuit. + * 0b1..One shot mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after CAPTCTRLA[ARMA] is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and CAPTCTRLA[ARMA] is cleared. No further captures will be performed until CAPTCTRLA[ARMA] is set again.If only one of the capture circuits is enabled, then a single capture will occur on the enabled capture circuit and CAPTCTRLA[ARMA] is then cleared. + */ #define PWM_CAPTCTRLA_ONESHOTA(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_ONESHOTA_SHIFT)) & PWM_CAPTCTRLA_ONESHOTA_MASK) #define PWM_CAPTCTRLA_EDGA0_MASK (0xCU) #define PWM_CAPTCTRLA_EDGA0_SHIFT (2U) @@ -28198,6 +28072,7 @@ typedef struct { #define PWM_CAPTCTRLA_INP_SELA_SHIFT (6U) /*! INP_SELA - Input Select A * 0b0..Raw PWM_A input signal selected as source. + * 0b1..Output of edge counter/compare selected as source. Note that when this bitfield is set to 1, the internal edge counter is enabled and the rising and/or falling edges specified by the CAPTCTRLA[EDGA0] and CAPTCTRLA[EDGA1] fields are ignored. The software must still place a value other than 00 in either or both of the CAPTCTLRA[EDGA0] and/or CAPTCTRLA[EDGA1] fields in order to enable one or both of the capture registers. */ #define PWM_CAPTCTRLA_INP_SELA(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_INP_SELA_SHIFT)) & PWM_CAPTCTRLA_INP_SELA_MASK) #define PWM_CAPTCTRLA_EDGCNTA_EN_MASK (0x80U) @@ -28245,6 +28120,10 @@ typedef struct { #define PWM_CAPTCTRLB_ARMB(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_ARMB_SHIFT)) & PWM_CAPTCTRLB_ARMB_MASK) #define PWM_CAPTCTRLB_ONESHOTB_MASK (0x2U) #define PWM_CAPTCTRLB_ONESHOTB_SHIFT (1U) +/*! ONESHOTB - One Shot Mode B + * 0b0..Free running mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after CAPTCTRLB[ARMB] is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and capture circuit 0 is re-armed. The process continues indefinitely.If only one of the capture circuits is enabled, then captures continue indefinitely on the enabled capture circuit. + * 0b1..One shot mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after CAPTCTRLB[ARMB] is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and CAPTCTRLB[ARMB] is cleared. No further captures will be performed until CAPTCTRLB[ARMB] is set again.If only one of the capture circuits is enabled, then a single capture will occur on the enabled capture circuit and CAPTCTRLB[ARMB] is then cleared. + */ #define PWM_CAPTCTRLB_ONESHOTB(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_ONESHOTB_SHIFT)) & PWM_CAPTCTRLB_ONESHOTB_MASK) #define PWM_CAPTCTRLB_EDGB0_MASK (0xCU) #define PWM_CAPTCTRLB_EDGB0_SHIFT (2U) @@ -28268,6 +28147,7 @@ typedef struct { #define PWM_CAPTCTRLB_INP_SELB_SHIFT (6U) /*! INP_SELB - Input Select B * 0b0..Raw PWM_B input signal selected as source. + * 0b1..Output of edge counter/compare selected as source. Note that when this bitfield is set to 1, the internal edge counter is enabled and the rising and/or falling edges specified by the CAPTCTRLB[EDGB0] and CAPTCTRLB[EDGB1] fields are ignored. The software must still place a value other than 00 in either or both of the CAPTCTLRB[EDGB0] and/or CAPTCTRLB[EDGB1] fields in order to enable one or both of the capture registers. */ #define PWM_CAPTCTRLB_INP_SELB(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_INP_SELB_SHIFT)) & PWM_CAPTCTRLB_INP_SELB_MASK) #define PWM_CAPTCTRLB_EDGCNTB_EN_MASK (0x80U) @@ -28315,6 +28195,10 @@ typedef struct { #define PWM_CAPTCTRLX_ARMX(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_ARMX_SHIFT)) & PWM_CAPTCTRLX_ARMX_MASK) #define PWM_CAPTCTRLX_ONESHOTX_MASK (0x2U) #define PWM_CAPTCTRLX_ONESHOTX_SHIFT (1U) +/*! ONESHOTX - One Shot Mode Aux + * 0b0..Free running mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after the ARMX bit is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and capture circuit 0 is re-armed. The process continues indefinitely.If only one of the capture circuits is enabled, then captures continue indefinitely on the enabled capture circuit. + * 0b1..One shot mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after the ARMX bit is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and the ARMX bit is cleared. No further captures will be performed until the ARMX bit is set again.If only one of the capture circuits is enabled, then a single capture will occur on the enabled capture circuit and the ARMX bit is then cleared. + */ #define PWM_CAPTCTRLX_ONESHOTX(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_ONESHOTX_SHIFT)) & PWM_CAPTCTRLX_ONESHOTX_MASK) #define PWM_CAPTCTRLX_EDGX0_MASK (0xCU) #define PWM_CAPTCTRLX_EDGX0_SHIFT (2U) @@ -28338,6 +28222,7 @@ typedef struct { #define PWM_CAPTCTRLX_INP_SELX_SHIFT (6U) /*! INP_SELX - Input Select X * 0b0..Raw PWM_X input signal selected as source. + * 0b1..Output of edge counter/compare selected as source. Note that when this bitfield is set to 1, the internal edge counter is enabled and the rising and/or falling edges specified by the CAPTCTRLX[EDGX0] and CAPTCTRLX[EDGX1] fields are ignored. The software must still place a value other than 00 in either or both of the CAPTCTLRX[EDGX0] and/or CAPTCTRLX[EDGX1] fields in order to enable one or both of the capture registers. */ #define PWM_CAPTCTRLX_INP_SELX(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_INP_SELX_SHIFT)) & PWM_CAPTCTRLX_INP_SELX_MASK) #define PWM_CAPTCTRLX_EDGCNTX_EN_MASK (0x80U) @@ -29261,7 +29146,7 @@ typedef struct { #define SEMC_MCR_SWRST(x) (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_SWRST_SHIFT)) & SEMC_MCR_SWRST_MASK) #define SEMC_MCR_MDIS_MASK (0x2U) #define SEMC_MCR_MDIS_SHIFT (1U) -/*! MDIS - Module Disable +/*! MDIS - Module Disable * 0b0..Module enabled * 0b1..Module disabled. */ @@ -29570,14 +29455,14 @@ typedef struct { /*! @{ */ #define SEMC_SDRAMCR0_PS_MASK (0x1U) #define SEMC_SDRAMCR0_PS_SHIFT (0U) -/*! PS - Port Size +/*! PS - Port Size * 0b0..8bit * 0b1..16bit */ #define SEMC_SDRAMCR0_PS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR0_PS_SHIFT)) & SEMC_SDRAMCR0_PS_MASK) #define SEMC_SDRAMCR0_BL_MASK (0x70U) #define SEMC_SDRAMCR0_BL_SHIFT (4U) -/*! BL - Burst Length +/*! BL - Burst Length * 0b000..1 * 0b001..2 * 0b010..4 @@ -29597,7 +29482,7 @@ typedef struct { #define SEMC_SDRAMCR0_COL8(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR0_COL8_SHIFT)) & SEMC_SDRAMCR0_COL8_MASK) #define SEMC_SDRAMCR0_COL_MASK (0x300U) #define SEMC_SDRAMCR0_COL_SHIFT (8U) -/*! COL - Column address bit number +/*! COL - Column address bit number * 0b00..12 bit * 0b01..11 bit * 0b10..10 bit @@ -29606,7 +29491,7 @@ typedef struct { #define SEMC_SDRAMCR0_COL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR0_COL_SHIFT)) & SEMC_SDRAMCR0_COL_MASK) #define SEMC_SDRAMCR0_CL_MASK (0xC00U) #define SEMC_SDRAMCR0_CL_SHIFT (10U) -/*! CL - CAS Latency +/*! CL - CAS Latency * 0b00..1 * 0b01..1 * 0b10..2 @@ -29684,14 +29569,14 @@ typedef struct { #define SEMC_SDRAMCR3_REBL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR3_REBL_SHIFT)) & SEMC_SDRAMCR3_REBL_MASK) #define SEMC_SDRAMCR3_PRESCALE_MASK (0xFF00U) #define SEMC_SDRAMCR3_PRESCALE_SHIFT (8U) -/*! PRESCALE - Prescaler timer period +/*! PRESCALE - Prescaler timer period * 0b00000000..256*16 cycle * 0b00000001-0b11111111..PRESCALE*16 cycle */ #define SEMC_SDRAMCR3_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR3_PRESCALE_SHIFT)) & SEMC_SDRAMCR3_PRESCALE_MASK) #define SEMC_SDRAMCR3_RT_MASK (0xFF0000U) #define SEMC_SDRAMCR3_RT_SHIFT (16U) -/*! RT - Refresh timer period +/*! RT - Refresh timer period * 0b00000000..256*Prescaler period * 0b00000001-0b11111111..RT*Prescaler period */ @@ -29709,7 +29594,7 @@ typedef struct { /*! @{ */ #define SEMC_NANDCR0_PS_MASK (0x1U) #define SEMC_NANDCR0_PS_SHIFT (0U) -/*! PS - Port Size +/*! PS - Port Size * 0b0..8bit * 0b1..16bit */ @@ -29723,7 +29608,7 @@ typedef struct { #define SEMC_NANDCR0_SYNCEN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR0_SYNCEN_SHIFT)) & SEMC_NANDCR0_SYNCEN_MASK) #define SEMC_NANDCR0_BL_MASK (0x70U) #define SEMC_NANDCR0_BL_SHIFT (4U) -/*! BL - Burst Length +/*! BL - Burst Length * 0b000..1 * 0b001..2 * 0b010..4 @@ -29743,7 +29628,7 @@ typedef struct { #define SEMC_NANDCR0_EDO(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR0_EDO_SHIFT)) & SEMC_NANDCR0_EDO_MASK) #define SEMC_NANDCR0_COL_MASK (0x700U) #define SEMC_NANDCR0_COL_SHIFT (8U) -/*! COL - Column address bit number +/*! COL - Column address bit number * 0b000..16 * 0b001..15 * 0b010..14 @@ -29835,7 +29720,7 @@ typedef struct { /*! @{ */ #define SEMC_NORCR0_PS_MASK (0x1U) #define SEMC_NORCR0_PS_SHIFT (0U) -/*! PS - Port Size +/*! PS - Port Size * 0b0..8bit * 0b1..16bit */ @@ -29849,7 +29734,7 @@ typedef struct { #define SEMC_NORCR0_SYNCEN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_SYNCEN_SHIFT)) & SEMC_NORCR0_SYNCEN_MASK) #define SEMC_NORCR0_BL_MASK (0x70U) #define SEMC_NORCR0_BL_SHIFT (4U) -/*! BL - Burst Length +/*! BL - Burst Length * 0b000..1 * 0b001..2 * 0b010..4 @@ -29862,7 +29747,7 @@ typedef struct { #define SEMC_NORCR0_BL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_BL_SHIFT)) & SEMC_NORCR0_BL_MASK) #define SEMC_NORCR0_AM_MASK (0x300U) #define SEMC_NORCR0_AM_SHIFT (8U) -/*! AM - Address Mode +/*! AM - Address Mode * 0b00..Address/Data MUX mode * 0b01..Advanced Address/Data MUX mode * 0b10..Address/Data non-MUX mode @@ -29871,21 +29756,21 @@ typedef struct { #define SEMC_NORCR0_AM(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_AM_SHIFT)) & SEMC_NORCR0_AM_MASK) #define SEMC_NORCR0_ADVP_MASK (0x400U) #define SEMC_NORCR0_ADVP_SHIFT (10U) -/*! ADVP - ADV# polarity +/*! ADVP - ADV# polarity * 0b0..ADV# is Low Active. In ASYNC mode, device sample address with ADV# rise edge; In SYNC mode, device sample address when ADV# is LOW. * 0b1..ADV# is High Active. In ASYNC mode, device sample address with ADV# fall edge; In SYNC mode, device sample address when ADV# is HIGH. */ #define SEMC_NORCR0_ADVP(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_ADVP_SHIFT)) & SEMC_NORCR0_ADVP_MASK) #define SEMC_NORCR0_ADVH_MASK (0x800U) #define SEMC_NORCR0_ADVH_SHIFT (11U) -/*! ADVH - ADV# level control during address hold state +/*! ADVH - ADV# level control during address hold state * 0b0..ADV# is high during address hold state. * 0b1..ADV# is low during address hold state. */ #define SEMC_NORCR0_ADVH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_ADVH_SHIFT)) & SEMC_NORCR0_ADVH_MASK) #define SEMC_NORCR0_COL_MASK (0xF000U) #define SEMC_NORCR0_COL_SHIFT (12U) -/*! COL - Column Address bit width +/*! COL - Column Address bit width * 0b0000..12 Bits * 0b0001..11 Bits * 0b0010..10 Bits @@ -29970,7 +29855,7 @@ typedef struct { /*! @{ */ #define SEMC_SRAMCR0_PS_MASK (0x1U) #define SEMC_SRAMCR0_PS_SHIFT (0U) -/*! PS - Port Size +/*! PS - Port Size * 0b0..8bit * 0b1..16bit */ @@ -29984,7 +29869,7 @@ typedef struct { #define SEMC_SRAMCR0_SYNCEN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_SYNCEN_SHIFT)) & SEMC_SRAMCR0_SYNCEN_MASK) #define SEMC_SRAMCR0_BL_MASK (0x70U) #define SEMC_SRAMCR0_BL_SHIFT (4U) -/*! BL - Burst Length +/*! BL - Burst Length * 0b000..1 * 0b001..2 * 0b010..4 @@ -29997,7 +29882,7 @@ typedef struct { #define SEMC_SRAMCR0_BL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_BL_SHIFT)) & SEMC_SRAMCR0_BL_MASK) #define SEMC_SRAMCR0_AM_MASK (0x300U) #define SEMC_SRAMCR0_AM_SHIFT (8U) -/*! AM - Address Mode +/*! AM - Address Mode * 0b00..Address/Data MUX mode * 0b01..Advanced Address/Data MUX mode * 0b10..Address/Data non-MUX mode @@ -30006,21 +29891,21 @@ typedef struct { #define SEMC_SRAMCR0_AM(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_AM_SHIFT)) & SEMC_SRAMCR0_AM_MASK) #define SEMC_SRAMCR0_ADVP_MASK (0x400U) #define SEMC_SRAMCR0_ADVP_SHIFT (10U) -/*! ADVP - ADV# polarity +/*! ADVP - ADV# polarity * 0b0..ADV# is Low Active. In ASYNC mode, device sample address with ADV# rise edge; In SYNC mode, device sample address when ADV# is LOW. * 0b1..ADV# is High Active. In ASYNC mode, device sample address with ADV# fall edge; In SYNC mode, device sample address when ADV# is HIGH. */ #define SEMC_SRAMCR0_ADVP(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_ADVP_SHIFT)) & SEMC_SRAMCR0_ADVP_MASK) #define SEMC_SRAMCR0_ADVH_MASK (0x800U) #define SEMC_SRAMCR0_ADVH_SHIFT (11U) -/*! ADVH - ADV# level control during address hold state +/*! ADVH - ADV# level control during address hold state * 0b0..ADV# is high during address hold state. * 0b1..ADV# is low during address hold state. */ #define SEMC_SRAMCR0_ADVH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_ADVH_SHIFT)) & SEMC_SRAMCR0_ADVH_MASK) #define SEMC_SRAMCR0_COL_MASK (0xF000U) #define SEMC_SRAMCR0_COL_SHIFT (12U) -/*! COL - Column Address bit width +/*! COL - Column Address bit width * 0b0000..12 Bits * 0b0001..11 Bits * 0b0010..10 Bits @@ -30101,14 +29986,14 @@ typedef struct { /*! @{ */ #define SEMC_DBICR0_PS_MASK (0x1U) #define SEMC_DBICR0_PS_SHIFT (0U) -/*! PS - Port Size +/*! PS - Port Size * 0b0..8bit * 0b1..16bit */ #define SEMC_DBICR0_PS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR0_PS_SHIFT)) & SEMC_DBICR0_PS_MASK) #define SEMC_DBICR0_BL_MASK (0x70U) #define SEMC_DBICR0_BL_SHIFT (4U) -/*! BL - Burst Length +/*! BL - Burst Length * 0b000..1 * 0b001..2 * 0b010..4 @@ -30121,7 +30006,7 @@ typedef struct { #define SEMC_DBICR0_BL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR0_BL_SHIFT)) & SEMC_DBICR0_BL_MASK) #define SEMC_DBICR0_COL_MASK (0xF000U) #define SEMC_DBICR0_COL_SHIFT (12U) -/*! COL - Column Address bit width +/*! COL - Column Address bit width * 0b0000..12 Bits * 0b0001..11 Bits * 0b0010..10 Bits @@ -30178,7 +30063,7 @@ typedef struct { /*! @{ */ #define SEMC_IPCR1_DATSZ_MASK (0x7U) #define SEMC_IPCR1_DATSZ_SHIFT (0U) -/*! DATSZ - Data Size in Byte +/*! DATSZ - Data Size in Byte * 0b000..4 * 0b001..1 * 0b010..2 @@ -30517,6 +30402,10 @@ typedef struct { #define SNVS_HPCOMR_PROG_ZMK(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_PROG_ZMK_SHIFT)) & SNVS_HPCOMR_PROG_ZMK_MASK) #define SNVS_HPCOMR_MKS_EN_MASK (0x2000U) #define SNVS_HPCOMR_MKS_EN_SHIFT (13U) +/*! MKS_EN + * 0b0..OTP master key is selected as an SNVS master key + * 0b1..SNVS master key is selected according to the setting of the MASTER_KEY_SEL field of LPMKCR + */ #define SNVS_HPCOMR_MKS_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_MKS_EN_SHIFT)) & SNVS_HPCOMR_MKS_EN_MASK) #define SNVS_HPCOMR_HAC_EN_MASK (0x10000U) #define SNVS_HPCOMR_HAC_EN_SHIFT (16U) @@ -31080,6 +30969,8 @@ typedef struct { #define SNVS_LPMKCR_MASTER_KEY_SEL_SHIFT (0U) /*! MASTER_KEY_SEL * 0b0x..Select one time programmable master key. + * 0b10..Select zeroizable master key when MKS_EN bit is set . + * 0b11..Select combined master key when MKS_EN bit is set . */ #define SNVS_LPMKCR_MASTER_KEY_SEL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPMKCR_MASTER_KEY_SEL_SHIFT)) & SNVS_LPMKCR_MASTER_KEY_SEL_MASK) #define SNVS_LPMKCR_ZMK_HWP_MASK (0x4U) @@ -37584,6 +37475,13 @@ typedef struct { #define USDHC_SYS_CTRL_SDCLKFS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_SDCLKFS_SHIFT)) & USDHC_SYS_CTRL_SDCLKFS_MASK) #define USDHC_SYS_CTRL_DTOCV_MASK (0xF0000U) #define USDHC_SYS_CTRL_DTOCV_SHIFT (16U) +/*! DTOCV - Data Timeout Counter Value + * 0b1111..SDCLK x 2 29 + * 0b1110..SDCLK x 2 28 + * 0b1101..SDCLK x 2 27 + * 0b0001..SDCLK x 2 15 + * 0b0000..SDCLK x 2 14 + */ #define USDHC_SYS_CTRL_DTOCV(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_DTOCV_SHIFT)) & USDHC_SYS_CTRL_DTOCV_MASK) #define USDHC_SYS_CTRL_IPP_RST_N_MASK (0x800000U) #define USDHC_SYS_CTRL_IPP_RST_N_SHIFT (23U) @@ -38695,6 +38593,10 @@ typedef struct { #define WDOG_WCR_WDE(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDE_SHIFT)) & WDOG_WCR_WDE_MASK) #define WDOG_WCR_WDT_MASK (0x8U) #define WDOG_WCR_WDT_SHIFT (3U) +/*! WDT - WDT + * 0b0..No effect on WDOG_B (Default). + * 0b1..Assert WDOG_B upon a Watchdog Time-out event. + */ #define WDOG_WCR_WDT(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDT_SHIFT)) & WDOG_WCR_WDT_MASK) #define WDOG_WCR_SRS_MASK (0x10U) #define WDOG_WCR_SRS_SHIFT (4U) @@ -38706,6 +38608,7 @@ typedef struct { #define WDOG_WCR_WDA_MASK (0x20U) #define WDOG_WCR_WDA_SHIFT (5U) /*! WDA - WDA + * 0b0..Assert WDOG_B output. * 0b1..No effect on system (Default). */ #define WDOG_WCR_WDA(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDA_SHIFT)) & WDOG_WCR_WDA_MASK) diff --git a/ext/hal/nxp/mcux/devices/MIMXRT1061/MIMXRT1061.xml b/ext/hal/nxp/mcux/devices/MIMXRT1061/MIMXRT1061.xml index 185164cd818..6cca5a09522 100644 --- a/ext/hal/nxp/mcux/devices/MIMXRT1061/MIMXRT1061.xml +++ b/ext/hal/nxp/mcux/devices/MIMXRT1061/MIMXRT1061.xml @@ -6,6 +6,7 @@ MIMXRT1061DVL6A Copyright 2016-2018 NXP +All rights reserved. SPDX-License-Identifier: BSD-3-Clause @@ -8097,13 +8098,6 @@ SPDX-License-Identifier: BSD-3-Clause - - CM7_INIT_VTOR - Vector table offset register out of reset - 7 - 25 - read-write - @@ -8729,145 +8723,6 @@ SPDX-License-Identifier: BSD-3-Clause 1 read-write - - Reserved - Reserved - 3 - 29 - read-only - - - - - OCRAM_MAGIC_ADDR - OCRAM Magic Address Register - 0x4 - 32 - read-write - 0 - 0xFFFFFFFF - - - OCRAM_WR_RD_SEL - OCRAM Write Read Select - 0 - 1 - read-write - - - OCRAM_WR_RD_SEL_0 - When OCRAM read access hits magic address, it will generate interrupt. - 0 - - - OCRAM_WR_RD_SEL_1 - When OCRAM write access hits magic address, it will generate interrupt. - 0x1 - - - - - OCRAM_MAGIC_ADDR - OCRAM Magic Address - 1 - 16 - read-write - - - Reserved - Reserved - 17 - 15 - read-only - - - - - DTCM_MAGIC_ADDR - DTCM Magic Address Register - 0x8 - 32 - read-write - 0 - 0xFFFFFFFF - - - DTCM_WR_RD_SEL - DTCM Write Read Select - 0 - 1 - read-write - - - DTCM_WR_RD_SEL_0 - When DTCM read access hits magic address, it will generate interrupt. - 0 - - - DTCM_WR_RD_SEL_1 - When DTCM write access hits magic address, it will generate interrupt. - 0x1 - - - - - DTCM_MAGIC_ADDR - DTCM Magic Address - 1 - 16 - read-write - - - Reserved - Reserved - 17 - 15 - read-only - - - - - ITCM_MAGIC_ADDR - ITCM Magic Address Register - 0xC - 32 - read-write - 0 - 0xFFFFFFFF - - - ITCM_WR_RD_SEL - ITCM Write Read Select - 0 - 1 - read-write - - - ITCM_WR_RD_SEL_0 - When ITCM read access hits magic address, it will generate interrupt. - 0 - - - ITCM_WR_RD_SEL_1 - When ITCM write access hits magic address, it will generate interrupt. - 0x1 - - - - - ITCM_MAGIC_ADDR - ITCM Magic Address - 1 - 16 - read-write - - - Reserved - Reserved - 17 - 15 - read-only - @@ -8879,66 +8734,6 @@ SPDX-License-Identifier: BSD-3-Clause 0 0xFFFFFFFF - - ITCM_MAM_STATUS - ITCM Magic Address Match Status - 0 - 1 - read-write - oneToClear - - - ITCM_MAM_STATUS_0 - ITCM did not access magic address. - 0 - - - ITCM_MAM_STATUS_1 - ITCM accessed magic address. - 0x1 - - - - - DTCM_MAM_STATUS - DTCM Magic Address Match Status - 1 - 1 - read-write - oneToClear - - - DTCM_MAM_STATUS_0 - DTCM did not access magic address. - 0 - - - DTCM_MAM_STATUS_1 - DTCM accessed magic address. - 0x1 - - - - - OCRAM_MAM_STATUS - OCRAM Magic Address Match Status - 2 - 1 - read-write - oneToClear - - - OCRAM_MAM_STATUS_0 - OCRAM did not access magic address. - 0 - - - OCRAM_MAM_STATUS_1 - OCRAM accessed magic address. - 0x1 - - - ITCM_ERR_STATUS ITCM Access Error Status @@ -8999,13 +8794,6 @@ SPDX-License-Identifier: BSD-3-Clause - - Reserved - Reserved - 6 - 26 - read-only - @@ -9017,63 +8805,6 @@ SPDX-License-Identifier: BSD-3-Clause 0 0xFFFFFFFF - - ITCM_MAM_STAT_EN - ITCM Magic Address Match Status Enable - 0 - 1 - read-write - - - ITCM_MAM_STAT_EN_0 - Masked - 0 - - - ITCM_MAM_STAT_EN_1 - Enabled - 0x1 - - - - - DTCM_MAM_STAT_EN - DTCM Magic Address Match Status Enable - 1 - 1 - read-write - - - DTCM_MAM_STAT_EN_0 - Masked - 0 - - - DTCM_MAM_STAT_EN_1 - Enabled - 0x1 - - - - - OCRAM_MAM_STAT_EN - OCRAM Magic Address Match Status Enable - 2 - 1 - read-write - - - OCRAM_MAM_STAT_EN_0 - Masked - 0 - - - OCRAM_MAM_STAT_EN_1 - Enabled - 0x1 - - - ITCM_ERR_STAT_EN ITCM Access Error Status Enable @@ -9131,13 +8862,6 @@ SPDX-License-Identifier: BSD-3-Clause - - Reserved - Reserved - 6 - 26 - read-only - @@ -9149,63 +8873,6 @@ SPDX-License-Identifier: BSD-3-Clause 0 0xFFFFFFFF - - ITCM_MAM_SIG_EN - ITCM Magic Address Match Interrupt Enable - 0 - 1 - read-write - - - ITCM_MAM_SIG_EN_0 - Masked - 0 - - - ITCM_MAM_SIG_EN_1 - Enabled - 0x1 - - - - - DTCM_MAM_SIG_EN - DTCM Magic Address Match Interrupt Enable - 1 - 1 - read-write - - - DTCM_MAM_SIG_EN_0 - Masked - 0 - - - DTCM_MAM_SIG_EN_1 - Enabled - 0x1 - - - - - OCRAM_MAM_SIG_EN - OCRAM Magic Address Match Interrupt Enable - 2 - 1 - read-write - - - OCRAM_MAM_SIG_EN_0 - Masked - 0 - - - OCRAM_MAM_SIG_EN_1 - Enabled - 0x1 - - - ITCM_ERR_SIG_EN ITCM Access Error Interrupt Enable @@ -9263,13 +8930,6 @@ SPDX-License-Identifier: BSD-3-Clause - - Reserved - Reserved - 6 - 26 - read-only - @@ -78935,6 +78595,94 @@ SPDX-License-Identifier: BSD-3-Clause + + DBG1 + Debug 1 register + 0x58 + 32 + read-only + 0x10000 + 0xFFFFFFFF + + + CFSM + CAN Finite State Machine + 0 + 6 + read-only + + + CBN + CAN Bit Number + 24 + 5 + read-only + + + + + DBG2 + Debug 2 register + 0x5C + 32 + read-only + 0 + 0xFFFFFFFF + + + RMP + Rx Matching Pointer + 0 + 7 + read-only + + + MPP + Matching Process in Progress + 7 + 1 + read-only + + + MPP_0 + No matching process ongoing. + 0 + + + MPP_1 + Matching process is in progress. + 0x1 + + + + + TAP + Tx Arbitration Pointer + 8 + 7 + read-only + + + APP + Arbitration Process in Progress + 15 + 1 + read-only + + + APP_0 + No matching process ongoing. + 0 + + + APP_1 + Matching process is in progress. + 0x1 + + + + + 64 0x4 @@ -140288,13 +140036,6 @@ SPDX-License-Identifier: BSD-3-Clause 2 read-only - - SRK - SRK - 14 - 1 - read-only - ROM_PATCH ROM_PATCH @@ -140592,7 +140333,7 @@ SPDX-License-Identifier: BSD-3-Clause ANA0 - Value of OTP Bank1 Word5 (Analog Info.) + Value of OTP Bank1 Word5 (Memory Related Info.) 0x4D0 32 read-write @@ -140610,7 +140351,7 @@ SPDX-License-Identifier: BSD-3-Clause ANA1 - Value of OTP Bank1 Word6 (Analog Info.) + Value of OTP Bank1 Word6 (General Purpose Customer Defined Info.) 0x4E0 32 read-write @@ -140628,7 +140369,7 @@ SPDX-License-Identifier: BSD-3-Clause ANA2 - Value of OTP Bank1 Word7 (Analog Info.) + Value of OTP Bank1 Word7 (General Purpose Customer Defined Info.) 0x4F0 32 read-write @@ -141006,7 +140747,7 @@ SPDX-License-Identifier: BSD-3-Clause MAC2 - Value of OTP Bank4 Word4 (MAC Address) + Value of OTP Bank4 Word4 (MAC2 Address) 0x640 32 read-write diff --git a/ext/hal/nxp/mcux/devices/MIMXRT1061/MIMXRT1061_features.h b/ext/hal/nxp/mcux/devices/MIMXRT1061/MIMXRT1061_features.h index 65b26f84bf6..91ea5b01b36 100644 --- a/ext/hal/nxp/mcux/devices/MIMXRT1061/MIMXRT1061_features.h +++ b/ext/hal/nxp/mcux/devices/MIMXRT1061/MIMXRT1061_features.h @@ -1,13 +1,14 @@ /* ** ################################################################### -** Version: rev. 0.1, 2017-01-10 -** Build: b180806 +** Version: rev. 1.0, 2018-11-16 +** Build: b181120 ** ** Abstract: ** Chip specific module features. ** ** Copyright 2016 Freescale Semiconductor, Inc. ** Copyright 2016-2018 NXP +** All rights reserved. ** ** SPDX-License-Identifier: BSD-3-Clause ** @@ -17,6 +18,8 @@ ** Revisions: ** - rev. 0.1 (2017-01-10) ** Initial version. +** - rev. 1.0 (2018-11-16) +** Update feature files to align with IMXRT1060RM Rev.0. ** ** ################################################################### */ @@ -67,7 +70,7 @@ /* @brief I2S availability on the SoC. */ #define FSL_FEATURE_SOC_I2S_COUNT (3) /* @brief IGPIO availability on the SoC. */ -#define FSL_FEATURE_SOC_IGPIO_COUNT (10) +#define FSL_FEATURE_SOC_IGPIO_COUNT (9) /* @brief IOMUXC availability on the SoC. */ #define FSL_FEATURE_SOC_IOMUXC_COUNT (1) /* @brief IOMUXC_GPR availability on the SoC. */ @@ -180,6 +183,12 @@ ((x) == CAN3 ? (0) : (-1)))) /* @brief Is affected by errata with ID 5641 (Module does not transmit a message that is enabled to be transmitted at a specific moment during the arbitration process). */ #define FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641 (0) +/* @brief Is affected by errata with ID 5829 (FlexCAN: FlexCAN does not transmit a message that is enabled to be transmitted in a specific moment during the arbitration process). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_5829 (1) +/* @brief Is affected by errata with ID 6032 (FlexCAN: A frame with wrong ID or payload is transmitted into the CAN bus when the Message Buffer under transmission is either aborted or deactivated while the CAN bus is in the Bus Idle state). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_6032 (1) +/* @brief Is affected by errata with ID 9595 (FlexCAN: Corrupt frame possible if the Freeze Mode or the Low-Power Mode are entered during a Bus-Off state). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_9595 (1) /* @brief Has CAN with Flexible Data rate (CAN FD) protocol. */ #define FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE (1) /* @brief CAN instance support Flexible Data rate (CAN FD) protocol. */ @@ -277,7 +286,7 @@ /* FLEXRAM module features */ /* @brief Bank size */ -#define FSL_FEATURE_FLEXRAM_INTERNAL_RAM_BANK_SIZE (32 * 1024) +#define FSL_FEATURE_FLEXRAM_INTERNAL_RAM_BANK_SIZE (32768) /* @brief Total Bank numbers */ #define FSL_FEATURE_FLEXRAM_INTERNAL_RAM_TOTAL_BANK_NUMBERS (16) diff --git a/ext/hal/nxp/mcux/devices/MIMXRT1061/fsl_clock.c b/ext/hal/nxp/mcux/devices/MIMXRT1061/fsl_clock.c index 40ba8e2cf17..3a0f5de829d 100644 --- a/ext/hal/nxp/mcux/devices/MIMXRT1061/fsl_clock.c +++ b/ext/hal/nxp/mcux/devices/MIMXRT1061/fsl_clock.c @@ -14,20 +14,21 @@ /******************************************************************************* * Definitions ******************************************************************************/ -/* To make full use of CM7 hardware FPU, use double instead of uint64_t in clock driver to +/* To make full use of CM7 hardware FPU, use double instead of uint64_t in clock driver to achieve better performance, it is depend on the IDE Floating point settings, if double precision is selected in IDE, clock_64b_t will switch to double type automatically. only support IAR and MDK here */ #if __FPU_USED #if ((defined(__ICCARM__)) || (defined(__GNUC__))) -#if (__ARMVFP__ >= __ARMFPV5__) && (__ARM_FP == 0xE) /*0xe implies support for half, single and double precision operations*/ +#if (__ARMVFP__ >= __ARMFPV5__) && \ + (__ARM_FP == 0xE) /*0xe implies support for half, single and double precision operations*/ typedef double clock_64b_t; #else typedef uint64_t clock_64b_t; #endif -#elif defined(__CC_ARM) +#elif defined(__CC_ARM) || defined(__ARMCC_VERSION) #if defined __TARGET_FPU_FPV5_D16 typedef double clock_64b_t; @@ -447,7 +448,7 @@ bool CLOCK_EnableUsbhs0PhyPllClock(clock_usb_phy_src_t src, uint32_t freq) const clock_usb_pll_config_t g_ccmConfigUsbPll = {.loopDivider = 0U}; if (CCM_ANALOG->PLL_USB1 & CCM_ANALOG_PLL_USB1_ENABLE_MASK) { - CCM_ANALOG->PLL_USB1 |= CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK; + CCM_ANALOG->PLL_USB1 |= CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK; } else { @@ -468,7 +469,7 @@ bool CLOCK_EnableUsbhs0PhyPllClock(clock_usb_phy_src_t src, uint32_t freq) */ void CLOCK_DisableUsbhs0PhyPllClock(void) { - CCM_ANALOG->PLL_USB1 &= ~CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK; + CCM_ANALOG->PLL_USB1 &= ~CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK; USBPHY1->CTRL |= USBPHY_CTRL_CLKGATE_MASK; /* Set to 1U to gate clocks */ } @@ -522,6 +523,15 @@ void CLOCK_InitSysPll(const clock_sys_pll_config_t *config) (CCM_ANALOG->PLL_SYS & (~(CCM_ANALOG_PLL_SYS_DIV_SELECT_MASK | CCM_ANALOG_PLL_SYS_POWERDOWN_MASK))) | CCM_ANALOG_PLL_SYS_ENABLE_MASK | CCM_ANALOG_PLL_SYS_DIV_SELECT(config->loopDivider); + /* Initialize the fractional mode */ + CCM_ANALOG->PLL_SYS_NUM = CCM_ANALOG_PLL_SYS_NUM_A(config->numerator); + CCM_ANALOG->PLL_SYS_DENOM = CCM_ANALOG_PLL_SYS_DENOM_B(config->denominator); + + /* Initialize the spread spectrum mode */ + CCM_ANALOG->PLL_SYS_SS = CCM_ANALOG_PLL_SYS_SS_STEP(config->ss_step) | + CCM_ANALOG_PLL_SYS_SS_ENABLE(config->ss_enable) | + CCM_ANALOG_PLL_SYS_SS_STOP(config->ss_stop); + while ((CCM_ANALOG->PLL_SYS & CCM_ANALOG_PLL_SYS_LOCK_MASK) == 0) { } @@ -809,7 +819,8 @@ void CLOCK_InitEnetPll(const clock_enet_pll_config_t *config) CCM_ANALOG->PLL_ENET = (CCM_ANALOG->PLL_ENET & (~(CCM_ANALOG_PLL_ENET_DIV_SELECT_MASK | CCM_ANALOG_PLL_ENET_ENET2_DIV_SELECT_MASK | - CCM_ANALOG_PLL_ENET_POWERDOWN_MASK))) | enet_pll; + CCM_ANALOG_PLL_ENET_POWERDOWN_MASK))) | + enet_pll; /* Wait for stable */ while ((CCM_ANALOG->PLL_ENET & CCM_ANALOG_PLL_ENET_LOCK_MASK) == 0) @@ -875,8 +886,8 @@ uint32_t CLOCK_GetPllFreq(clock_pll_t pll) break; case kCLOCK_PllSys: /* PLL output frequency = Fref * (DIV_SELECT + NUM/DENOM). */ - freqTmp = - ((clock_64b_t)freq * ((clock_64b_t)(CCM_ANALOG->PLL_SYS_NUM))) / ((clock_64b_t)(CCM_ANALOG->PLL_SYS_DENOM)); + freqTmp = ((clock_64b_t)freq * ((clock_64b_t)(CCM_ANALOG->PLL_SYS_NUM))) / + ((clock_64b_t)(CCM_ANALOG->PLL_SYS_DENOM)); if (CCM_ANALOG->PLL_SYS & CCM_ANALOG_PLL_SYS_DIV_SELECT_MASK) { @@ -899,8 +910,8 @@ uint32_t CLOCK_GetPllFreq(clock_pll_t pll) divSelect = (CCM_ANALOG->PLL_AUDIO & CCM_ANALOG_PLL_AUDIO_DIV_SELECT_MASK) >> CCM_ANALOG_PLL_AUDIO_DIV_SELECT_SHIFT; - freqTmp = - ((clock_64b_t)freq * ((clock_64b_t)(CCM_ANALOG->PLL_AUDIO_NUM))) / ((clock_64b_t)(CCM_ANALOG->PLL_AUDIO_DENOM)); + freqTmp = ((clock_64b_t)freq * ((clock_64b_t)(CCM_ANALOG->PLL_AUDIO_NUM))) / + ((clock_64b_t)(CCM_ANALOG->PLL_AUDIO_DENOM)); freq = freq * divSelect + (uint32_t)freqTmp; @@ -954,8 +965,8 @@ uint32_t CLOCK_GetPllFreq(clock_pll_t pll) divSelect = (CCM_ANALOG->PLL_VIDEO & CCM_ANALOG_PLL_VIDEO_DIV_SELECT_MASK) >> CCM_ANALOG_PLL_VIDEO_DIV_SELECT_SHIFT; - freqTmp = - ((clock_64b_t)freq * ((clock_64b_t)(CCM_ANALOG->PLL_VIDEO_NUM))) / ((clock_64b_t)(CCM_ANALOG->PLL_VIDEO_DENOM)); + freqTmp = ((clock_64b_t)freq * ((clock_64b_t)(CCM_ANALOG->PLL_VIDEO_NUM))) / + ((clock_64b_t)(CCM_ANALOG->PLL_VIDEO_DENOM)); freq = freq * divSelect + (uint32_t)freqTmp; @@ -1212,6 +1223,6 @@ bool CLOCK_EnableUsbhs1PhyPllClock(clock_usb_phy_src_t src, uint32_t freq) */ void CLOCK_DisableUsbhs1PhyPllClock(void) { - CCM_ANALOG->PLL_USB2 &= ~CCM_ANALOG_PLL_USB2_EN_USB_CLKS_MASK; + CCM_ANALOG->PLL_USB2 &= ~CCM_ANALOG_PLL_USB2_EN_USB_CLKS_MASK; USBPHY2->CTRL |= USBPHY_CTRL_CLKGATE_MASK; /* Set to 1U to gate clocks */ } diff --git a/ext/hal/nxp/mcux/devices/MIMXRT1061/fsl_clock.h b/ext/hal/nxp/mcux/devices/MIMXRT1061/fsl_clock.h index f59bd27b47b..85af6a62bf3 100644 --- a/ext/hal/nxp/mcux/devices/MIMXRT1061/fsl_clock.h +++ b/ext/hal/nxp/mcux/devices/MIMXRT1061/fsl_clock.h @@ -39,8 +39,8 @@ /*! @name Driver version */ /*@{*/ -/*! @brief CLOCK driver version 2.1.5. */ -#define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 1, 5)) +/*! @brief CLOCK driver version 2.1.6. */ +#define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 1, 6)) /* analog pll definition */ #define CCM_ANALOG_PLL_BYPASS_SHIFT (16U) @@ -156,8 +156,8 @@ extern volatile uint32_t g_rtcXtalFreq; } /*! @brief Clock ip name array for ENET. */ -#define ENET_CLOCKS \ - { \ +#define ENET_CLOCKS \ + { \ kCLOCK_Enet, kCLOCK_IpInvalid, kCLOCK_Enet2 \ } @@ -168,20 +168,20 @@ extern volatile uint32_t g_rtcXtalFreq; } /*! @brief Clock ip name array for FLEXCAN. */ -#define FLEXCAN_CLOCKS \ - { \ +#define FLEXCAN_CLOCKS \ + { \ kCLOCK_IpInvalid, kCLOCK_Can1, kCLOCK_Can2, kCLOCK_Can3 \ } /*! @brief Clock ip name array for FLEXCAN Peripheral clock. */ -#define FLEXCAN_PERIPH_CLOCKS \ - { \ +#define FLEXCAN_PERIPH_CLOCKS \ + { \ kCLOCK_IpInvalid, kCLOCK_Can1S, kCLOCK_Can2S, kCLOCK_Can3S \ } /*! @brief Clock ip name array for FLEXIO. */ -#define FLEXIO_CLOCKS \ - { \ +#define FLEXIO_CLOCKS \ + { \ kCLOCK_IpInvalid, kCLOCK_Flexio1, kCLOCK_Flexio2, kCLOCK_Flexio3 \ } @@ -192,8 +192,8 @@ extern volatile uint32_t g_rtcXtalFreq; } /*! @brief Clock ip name array for FLEXSPI. */ -#define FLEXSPI_CLOCKS \ - { \ +#define FLEXSPI_CLOCKS \ + { \ kCLOCK_FlexSpi, kCLOCK_IpInvalid, kCLOCK_FlexSpi2 \ } @@ -533,14 +533,14 @@ typedef enum _clock_ip_name kCLOCK_Timer3 = (6U << 8U) | CCM_CCGR6_CG15_SHIFT, /*!< CCGR6, CG15 */ /* CCM CCGR7 */ - kCLOCK_Enet2 = (7U << 8U) | CCM_CCGR7_CG0_SHIFT, /*!< CCGR7, CG0 */ - kCLOCK_FlexSpi2 = (7U << 8U) | CCM_CCGR7_CG1_SHIFT, /*!< CCGR7, CG1 */ - kCLOCK_Axbs_l = (7U << 8U) | CCM_CCGR7_CG2_SHIFT, /*!< CCGR7, CG2 */ - kCLOCK_Can3 = (7U << 8U) | CCM_CCGR7_CG3_SHIFT, /*!< CCGR7, CG3 */ - kCLOCK_Can3S = (7U << 8U) | CCM_CCGR7_CG4_SHIFT, /*!< CCGR7, CG4 */ - kCLOCK_Aips_lite = (7U << 8U) | CCM_CCGR7_CG5_SHIFT,/*!< CCGR7, CG5 */ - kCLOCK_Flexio3 = (7U << 8U) | CCM_CCGR7_CG6_SHIFT, /*!< CCGR7, CG6 */ - + kCLOCK_Enet2 = (7U << 8U) | CCM_CCGR7_CG0_SHIFT, /*!< CCGR7, CG0 */ + kCLOCK_FlexSpi2 = (7U << 8U) | CCM_CCGR7_CG1_SHIFT, /*!< CCGR7, CG1 */ + kCLOCK_Axbs_l = (7U << 8U) | CCM_CCGR7_CG2_SHIFT, /*!< CCGR7, CG2 */ + kCLOCK_Can3 = (7U << 8U) | CCM_CCGR7_CG3_SHIFT, /*!< CCGR7, CG3 */ + kCLOCK_Can3S = (7U << 8U) | CCM_CCGR7_CG4_SHIFT, /*!< CCGR7, CG4 */ + kCLOCK_Aips_lite = (7U << 8U) | CCM_CCGR7_CG5_SHIFT, /*!< CCGR7, CG5 */ + kCLOCK_Flexio3 = (7U << 8U) | CCM_CCGR7_CG6_SHIFT, /*!< CCGR7, CG6 */ + } clock_ip_name_t; /*! @brief OSC 24M sorce select */ @@ -603,9 +603,9 @@ typedef enum _clock_mux CCM_CBCMR_PERIPH_CLK2_SEL_MASK, CCM_NO_BUSY_WAIT), /*!< periph clock2 mux name */ kCLOCK_Flexspi2Mux = CCM_TUPLE(CBCMR, - CCM_CBCMR_FLEXSPI2_CLK_SEL_SHIFT, - CCM_CBCMR_FLEXSPI2_CLK_SEL_MASK, - CCM_NO_BUSY_WAIT), /*!< flexspi2 mux name */ + CCM_CBCMR_FLEXSPI2_CLK_SEL_SHIFT, + CCM_CBCMR_FLEXSPI2_CLK_SEL_MASK, + CCM_NO_BUSY_WAIT), /*!< flexspi2 mux name */ kCLOCK_LpspiMux = CCM_TUPLE( CBCMR, CCM_CBCMR_LPSPI_CLK_SEL_SHIFT, CCM_CBCMR_LPSPI_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), /*!< lpspi mux name */ @@ -813,7 +813,9 @@ typedef struct _clock_sys_pll_config uint32_t numerator; /*!< 30 bit numerator of fractional loop divider.*/ uint32_t denominator; /*!< 30 bit denominator of fractional loop divider */ uint8_t src; /*!< Pll clock source, reference _clock_pll_clk_src */ - + uint16_t ss_stop; /*!< Stop value to get frequency change. */ + uint8_t ss_enable; /*!< Enable spread spectrum modulation */ + uint16_t ss_step; /*!< Step value to get frequency change step. */ } clock_sys_pll_config_t; /*! @brief PLL configuration for AUDIO and VIDEO */ @@ -841,20 +843,19 @@ typedef struct _clock_video_pll_config typedef struct _clock_enet_pll_config { bool enableClkOutput; /*!< Power on and enable PLL clock output for ENET0 (ref_enetpll0). */ - bool enableClkOutput1; /*!< Power on and enable PLL clock output for ENET1 (ref_enetpll1). */ bool enableClkOutput25M; /*!< Power on and enable PLL clock output for ENET2 (ref_enetpll2). */ uint8_t loopDivider; /*!< Controls the frequency of the ENET0 reference clock. b00 25MHz b01 50MHz b10 100MHz (not 50% duty cycle) b11 125MHz */ - uint8_t loopDivider1; /*!< Controls the frequency of the ENET1 reference clock. + uint8_t src; /*!< Pll clock source, reference _clock_pll_clk_src */ + bool enableClkOutput1; /*!< Power on and enable PLL clock output for ENET1 (ref_enetpll1). */ + uint8_t loopDivider1; /*!< Controls the frequency of the ENET1 reference clock. b00 25MHz b01 50MHz b10 100MHz (not 50% duty cycle) b11 125MHz */ - uint8_t src; /*!< Pll clock source, reference _clock_pll_clk_src */ - } clock_enet_pll_config_t; /*! @brief PLL name */ @@ -1157,7 +1158,6 @@ void CLOCK_InitRcOsc24M(void); void CLOCK_DeinitRcOsc24M(void); /* @} */ - /*! @brief Enable USB HS clock. * * This function only enables the access to USB HS prepheral, upper layer diff --git a/ext/hal/nxp/mcux/devices/MIMXRT1061/fsl_iomuxc.h b/ext/hal/nxp/mcux/devices/MIMXRT1061/fsl_iomuxc.h index e4cad1d0883..5c4a5c28fa2 100644 --- a/ext/hal/nxp/mcux/devices/MIMXRT1061/fsl_iomuxc.h +++ b/ext/hal/nxp/mcux/devices/MIMXRT1061/fsl_iomuxc.h @@ -27,8 +27,8 @@ /*! @name Driver version */ /*@{*/ -/*! @brief IOMUXC driver version 2.0.0. */ -#define FSL_IOMUXC_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) +/*! @brief IOMUXC driver version 2.0.1. */ +#define FSL_IOMUXC_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) /*@}*/ /*! @name Pin function ID */ @@ -1206,8 +1206,10 @@ typedef enum _iomuxc_gpr_mode { kIOMUXC_GPR_GlobalInterruptRequest = IOMUXC_GPR_GPR1_GINT_MASK, kIOMUXC_GPR_ENET1RefClkMode = IOMUXC_GPR_GPR1_ENET1_CLK_SEL_MASK, + kIOMUXC_GPR_ENET2RefClkMode = IOMUXC_GPR_GPR1_ENET2_CLK_SEL_MASK, kIOMUXC_GPR_USBExposureMode = IOMUXC_GPR_GPR1_USB_EXP_MODE_MASK, kIOMUXC_GPR_ENET1TxClkOutputDir = IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK, + kIOMUXC_GPR_ENET2TxClkOutputDir = IOMUXC_GPR_GPR1_ENET2_TX_CLK_DIR_MASK, kIOMUXC_GPR_SAI1MClkOutputDir = IOMUXC_GPR_GPR1_SAI1_MCLK_DIR_MASK, kIOMUXC_GPR_SAI2MClkOutputDir = IOMUXC_GPR_GPR1_SAI2_MCLK_DIR_MASK, kIOMUXC_GPR_SAI3MClkOutputDir = IOMUXC_GPR_GPR1_SAI3_MCLK_DIR_MASK, diff --git a/ext/hal/nxp/mcux/devices/MIMXRT1062/MIMXRT1062.h b/ext/hal/nxp/mcux/devices/MIMXRT1062/MIMXRT1062.h index 1222a52d7ee..228c60c4d0a 100644 --- a/ext/hal/nxp/mcux/devices/MIMXRT1062/MIMXRT1062.h +++ b/ext/hal/nxp/mcux/devices/MIMXRT1062/MIMXRT1062.h @@ -5,21 +5,22 @@ ** MIMXRT1062DVJ6A ** MIMXRT1062DVL6A ** -** Compilers: Keil ARM C/C++ Compiler -** Freescale C/C++ for Embedded ARM +** Compilers: Freescale C/C++ for Embedded ARM ** GNU C Compiler ** IAR ANSI C/C++ Compiler for ARM +** Keil ARM C/C++ Compiler ** MCUXpresso Compiler ** -** Reference manual: IMXRT1060RM Rev. 0, 08/2018 -** Version: rev. 0.1, 2017-01-10 -** Build: b180819 +** Reference manual: IMXRT1060RM Rev.1, 12/2018 +** Version: rev. 1.1, 2018-11-27 +** Build: b181127 ** ** Abstract: ** CMSIS Peripheral Access Layer for MIMXRT1062 ** ** Copyright 1997-2016 Freescale Semiconductor, Inc. ** Copyright 2016-2018 NXP +** All rights reserved. ** ** SPDX-License-Identifier: BSD-3-Clause ** @@ -29,14 +30,18 @@ ** Revisions: ** - rev. 0.1 (2017-01-10) ** Initial version. +** - rev. 1.0 (2018-11-16) +** Update header files to align with IMXRT1060RM Rev.0. +** - rev. 1.1 (2018-11-27) +** Update header files to align with IMXRT1060RM Rev.1. ** ** ################################################################### */ /*! * @file MIMXRT1062.h - * @version 0.1 - * @date 2017-01-10 + * @version 1.1 + * @date 2018-11-27 * @brief CMSIS Peripheral Access Layer for MIMXRT1062 * * CMSIS Peripheral Access Layer for MIMXRT1062 @@ -47,7 +52,7 @@ /** Memory map major version (memory maps with equal major version number are * compatible) */ -#define MCU_MEM_MAP_VERSION 0x0000U +#define MCU_MEM_MAP_VERSION 0x0100U /** Memory map minor version */ #define MCU_MEM_MAP_VERSION_MINOR 0x0001U @@ -298,8 +303,8 @@ typedef enum IRQn { */ typedef enum _dma_request_source { - kDmaRequestMuxFlexIO1Request0Request1 = 0|0x100U, /**< FlexIO1 */ - kDmaRequestMuxFlexIO2Request0Request1 = 1|0x100U, /**< FlexIO2 */ + kDmaRequestMuxFlexIO1Request0Request1 = 0|0x100U, /**< FlexIO1 Request0 and Request1 */ + kDmaRequestMuxFlexIO2Request0Request1 = 1|0x100U, /**< FlexIO2 Request0 and Request1 */ kDmaRequestMuxLPUART1Tx = 2|0x100U, /**< LPUART1 Transmit */ kDmaRequestMuxLPUART1Rx = 3|0x100U, /**< LPUART1 Receive */ kDmaRequestMuxLPUART3Tx = 4|0x100U, /**< LPUART3 Transmit */ @@ -358,8 +363,8 @@ typedef enum _dma_request_source kDmaRequestMuxQTIMER3CaptTimer3Cmpld1Timer3Cmpld2Timer2 = 59|0x100U, /**< QTIMER3 capture timer 3, cmpld1 in timer 3 or cmpld2 in timer 2 */ kDmaRequestMuxFlexSPI2Rx = 60|0x100U, /**< FlexSPI2 Receive */ kDmaRequestMuxFlexSPI2Tx = 61|0x100U, /**< FlexSPI2 Transmit */ - kDmaRequestMuxFlexIO1Request2Request3 = 64|0x100U, /**< FlexIO1 */ - kDmaRequestMuxFlexIO2Request2Request3 = 65|0x100U, /**< FlexIO2 */ + kDmaRequestMuxFlexIO1Request2Request3 = 64|0x100U, /**< FlexIO1 Request2 and Request3 */ + kDmaRequestMuxFlexIO2Request2Request3 = 65|0x100U, /**< FlexIO2 Request2 and Request3 */ kDmaRequestMuxLPUART2Tx = 66|0x100U, /**< LPUART2 Transmit */ kDmaRequestMuxLPUART2Rx = 67|0x100U, /**< LPUART2 Receive */ kDmaRequestMuxLPUART4Tx = 68|0x100U, /**< LPUART4 Transmit */ @@ -3254,7 +3259,10 @@ typedef struct { __IO uint32_t RXFGMASK; /**< Rx FIFO Global Mask Register..Legacy Rx FIFO Global Mask register, offset: 0x48 */ __I uint32_t RXFIR; /**< Rx FIFO Information Register..Legacy Rx FIFO Information Register, offset: 0x4C */ __IO uint32_t CBT; /**< CAN Bit Timing Register, offset: 0x50 */ - uint8_t RESERVED_2[44]; + uint8_t RESERVED_2[4]; + __I uint32_t DBG1; /**< Debug 1 register, offset: 0x58 */ + __I uint32_t DBG2; /**< Debug 2 register, offset: 0x5C */ + uint8_t RESERVED_3[32]; union { /* offset: 0x80 */ struct { /* offset: 0x80, array step: 0x18 */ __IO uint32_t CS; /**< Message Buffer 0 CS Register..Message Buffer 41 CS Register, array offset: 0x80, array step: 0x18 */ @@ -3283,11 +3291,11 @@ typedef struct { __IO uint32_t WORD1; /**< Message Buffer 0 WORD1 Register..Message Buffer 63 WORD1 Register, array offset: 0x8C, array step: 0x10 */ } MB[64]; }; - uint8_t RESERVED_3[1024]; + uint8_t RESERVED_4[1024]; __IO uint32_t RXIMR[64]; /**< Rx Individual Mask Registers, array offset: 0x880, array step: 0x4 */ - uint8_t RESERVED_4[96]; + uint8_t RESERVED_5[96]; __IO uint32_t GFWR; /**< Glitch Filter Width Registers, offset: 0x9E0 */ - uint8_t RESERVED_5[524]; + uint8_t RESERVED_6[524]; __IO uint32_t EPRS; /**< Enhanced CAN Bit Timing Prescalers, offset: 0xBF0 */ __IO uint32_t ENCBT; /**< Enhanced Nominal CAN Bit Timing, offset: 0xBF4 */ __IO uint32_t EDCBT; /**< Enhanced Data Phase CAN bit Timing, offset: 0xBF8 */ @@ -3298,9 +3306,9 @@ typedef struct { __IO uint32_t ERFCR; /**< Enhanced Rx FIFO Control Register, offset: 0xC0C */ __IO uint32_t ERFIER; /**< Enhanced Rx FIFO Interrupt Enable register, offset: 0xC10 */ __IO uint32_t ERFSR; /**< Enhanced Rx FIFO Status Register, offset: 0xC14 */ - uint8_t RESERVED_6[24]; + uint8_t RESERVED_7[24]; __I uint32_t HR_TIME_STAMP[64]; /**< High Resolution Time Stamp, array offset: 0xC30, array step: 0x4 */ - uint8_t RESERVED_7[8912]; + uint8_t RESERVED_8[8912]; __IO uint32_t ERFFEL[128]; /**< Enhanced Rx FIFO Filter Element, array offset: 0x3000, array step: 0x4 */ } CAN_Type; @@ -3379,15 +3387,15 @@ typedef struct { #define CAN_MCR_WAKSRC_MASK (0x80000U) #define CAN_MCR_WAKSRC_SHIFT (19U) /*! WAKSRC - Wake Up Source - * 0b0..FlexCAN uses the unfiltered Rx input to detect recessive to dominant edges on the CAN bus. - * 0b1..FlexCAN uses the filtered Rx input to detect recessive to dominant edges on the CAN bus. + * 0b1..FLEXCAN uses the filtered FLEXCAN_RX input to detect recessive to dominant edges on the CAN bus + * 0b0..FLEXCAN uses the unfiltered FLEXCAN_RX input to detect recessive to dominant edges on the CAN bus. */ #define CAN_MCR_WAKSRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WAKSRC_SHIFT)) & CAN_MCR_WAKSRC_MASK) #define CAN_MCR_LPMACK_MASK (0x100000U) #define CAN_MCR_LPMACK_SHIFT (20U) /*! LPMACK - Low-Power Mode Acknowledge - * 0b0..FlexCAN is not in a low-power mode. - * 0b1..FlexCAN is in a low-power mode. + * 0b1..FLEXCAN is either in Disable Mode, or Stop mode + * 0b0..FLEXCAN not in any of the low power modes */ #define CAN_MCR_LPMACK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_LPMACK_SHIFT)) & CAN_MCR_LPMACK_MASK) #define CAN_MCR_WRNEN_MASK (0x200000U) @@ -3406,6 +3414,10 @@ typedef struct { #define CAN_MCR_SLFWAK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SLFWAK_SHIFT)) & CAN_MCR_SLFWAK_MASK) #define CAN_MCR_SUPV_MASK (0x800000U) #define CAN_MCR_SUPV_SHIFT (23U) +/*! SUPV - Supervisor Mode + * 0b1..FlexCAN is in Supervisor Mode. Affected registers allow only Supervisor access. Unrestricted access behaves as though the access was done to an unimplemented register location + * 0b0..FlexCAN is in User Mode. Affected registers allow both Supervisor and Unrestricted accesses + */ #define CAN_MCR_SUPV(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SUPV_SHIFT)) & CAN_MCR_SUPV_MASK) #define CAN_MCR_FRZACK_MASK (0x1000000U) #define CAN_MCR_FRZACK_SHIFT (24U) @@ -3431,7 +3443,8 @@ typedef struct { #define CAN_MCR_NOTRDY_MASK (0x8000000U) #define CAN_MCR_NOTRDY_SHIFT (27U) /*! NOTRDY - FlexCAN Not Ready - * 0b0..FlexCAN module is either in Normal mode, Listen-Only mode or Loop-Back mode. + * 0b1..FLEXCAN module is either in Disable Mode, Stop Mode or Freeze Mode + * 0b0..FLEXCAN module is either in Normal Mode, Listen-Only Mode or Loop-Back Mode */ #define CAN_MCR_NOTRDY(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_NOTRDY_SHIFT)) & CAN_MCR_NOTRDY_MASK) #define CAN_MCR_HALT_MASK (0x10000000U) @@ -3486,15 +3499,15 @@ typedef struct { #define CAN_CTRL1_TSYN_MASK (0x20U) #define CAN_CTRL1_TSYN_SHIFT (5U) /*! TSYN - Timer Sync - * 0b0..Timer Sync feature disabled * 0b1..Timer Sync feature enabled + * 0b0..Timer Sync feature disabled */ #define CAN_CTRL1_TSYN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_TSYN_SHIFT)) & CAN_CTRL1_TSYN_MASK) #define CAN_CTRL1_BOFFREC_MASK (0x40U) #define CAN_CTRL1_BOFFREC_SHIFT (6U) /*! BOFFREC - Bus Off Recovery - * 0b0..Automatic recovering from Bus Off state enabled. - * 0b1..Automatic recovering from Bus Off state disabled. + * 0b1..Automatic recovering from Bus Off state disabled + * 0b0..Automatic recovering from Bus Off state enabled, according to CAN Spec 2.0 part B */ #define CAN_CTRL1_BOFFREC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_BOFFREC_SHIFT)) & CAN_CTRL1_BOFFREC_MASK) #define CAN_CTRL1_SMP_MASK (0x80U) @@ -3571,6 +3584,10 @@ typedef struct { /*! @{ */ #define CAN_RXMGMASK_MG_MASK (0xFFFFFFFFU) #define CAN_RXMGMASK_MG_SHIFT (0U) +/*! MG - Rx Mailboxes Global Mask Bits + * 0b00000000000000000000000000000001..The corresponding bit in the filter is checked against the one received + * 0b00000000000000000000000000000000..the corresponding bit in the filter is "don't care" + */ #define CAN_RXMGMASK_MG(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXMGMASK_MG_SHIFT)) & CAN_RXMGMASK_MG_MASK) /*! @} */ @@ -3578,6 +3595,10 @@ typedef struct { /*! @{ */ #define CAN_RX14MASK_RX14M_MASK (0xFFFFFFFFU) #define CAN_RX14MASK_RX14M_SHIFT (0U) +/*! RX14M - Rx Buffer 14 Mask Bits + * 0b00000000000000000000000000000001..The corresponding bit in the filter is checked + * 0b00000000000000000000000000000000..the corresponding bit in the filter is "don't care" + */ #define CAN_RX14MASK_RX14M(x) (((uint32_t)(((uint32_t)(x)) << CAN_RX14MASK_RX14M_SHIFT)) & CAN_RX14MASK_RX14M_MASK) /*! @} */ @@ -3585,6 +3606,10 @@ typedef struct { /*! @{ */ #define CAN_RX15MASK_RX15M_MASK (0xFFFFFFFFU) #define CAN_RX15MASK_RX15M_SHIFT (0U) +/*! RX15M - Rx Buffer 15 Mask Bits + * 0b00000000000000000000000000000001..The corresponding bit in the filter is checked + * 0b00000000000000000000000000000000..the corresponding bit in the filter is "don't care" + */ #define CAN_RX15MASK_RX15M(x) (((uint32_t)(((uint32_t)(x)) << CAN_RX15MASK_RX15M_SHIFT)) & CAN_RX15MASK_RX15M_MASK) /*! @} */ @@ -3615,8 +3640,8 @@ typedef struct { #define CAN_ESR1_WAKINT_MASK (0x1U) #define CAN_ESR1_WAKINT_SHIFT (0U) /*! WAKINT - Wake-Up Interrupt - * 0b0..No such occurrence. - * 0b1..Indicates a recessive to dominant transition was received on the CAN bus. + * 0b1..Indicates a recessive to dominant transition received on the CAN bus when the FLEXCAN module is in Stop Mode + * 0b0..No such occurrence */ #define CAN_ESR1_WAKINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_WAKINT_SHIFT)) & CAN_ESR1_WAKINT_MASK) #define CAN_ESR1_ERRINT_MASK (0x2U) @@ -3645,7 +3670,7 @@ typedef struct { /*! FLTCONF - Fault Confinement State * 0b00..Error Active * 0b01..Error Passive - * 0b1x..Bus Off + * 0b1x..Bus off */ #define CAN_ESR1_FLTCONF(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FLTCONF_SHIFT)) & CAN_ESR1_FLTCONF_MASK) #define CAN_ESR1_TX_MASK (0x40U) @@ -3748,8 +3773,7 @@ typedef struct { #define CAN_ESR1_BOFFDONEINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BOFFDONEINT_SHIFT)) & CAN_ESR1_BOFFDONEINT_MASK) #define CAN_ESR1_ERRINT_FAST_MASK (0x100000U) #define CAN_ESR1_ERRINT_FAST_SHIFT (20U) -/*! ERRINT_FAST - Error Interrupt for errors detected in the Data Phase of CAN FD - frames with the BRS bit set +/*! ERRINT_FAST - Error Interrupt for errors detected in the Data Phase of CAN FD frames with the BRS bit set * 0b0..No such occurrence. * 0b1..Indicates setting of any Error Bit detected in the Data Phase of CAN FD frames with the BRS bit set. */ @@ -3763,40 +3787,35 @@ typedef struct { #define CAN_ESR1_ERROVR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ERROVR_SHIFT)) & CAN_ESR1_ERROVR_MASK) #define CAN_ESR1_STFERR_FAST_MASK (0x4000000U) #define CAN_ESR1_STFERR_FAST_SHIFT (26U) -/*! STFERR_FAST - Stuffing Error in the Data Phase of CAN FD frames with the BRS bit - set +/*! STFERR_FAST - Stuffing Error in the Data Phase of CAN FD frames with the BRS bit set * 0b0..No such occurrence. * 0b1..A Stuffing Error occurred since last read of this register. */ #define CAN_ESR1_STFERR_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_STFERR_FAST_SHIFT)) & CAN_ESR1_STFERR_FAST_MASK) #define CAN_ESR1_FRMERR_FAST_MASK (0x8000000U) #define CAN_ESR1_FRMERR_FAST_SHIFT (27U) -/*! FRMERR_FAST - Form Error in the Data Phase of CAN FD frames with the BRS bit - set +/*! FRMERR_FAST - Form Error in the Data Phase of CAN FD frames with the BRS bit set * 0b0..No such occurrence. * 0b1..A Form Error occurred since last read of this register. */ #define CAN_ESR1_FRMERR_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FRMERR_FAST_SHIFT)) & CAN_ESR1_FRMERR_FAST_MASK) #define CAN_ESR1_CRCERR_FAST_MASK (0x10000000U) #define CAN_ESR1_CRCERR_FAST_SHIFT (28U) -/*! CRCERR_FAST - Cyclic Redundancy Check Error in the CRC field of CAN FD frames with - the BRS bit set +/*! CRCERR_FAST - Cyclic Redundancy Check Error in the CRC field of CAN FD frames with the BRS bit set * 0b0..No such occurrence. * 0b1..A CRC error occurred since last read of this register. */ #define CAN_ESR1_CRCERR_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_CRCERR_FAST_SHIFT)) & CAN_ESR1_CRCERR_FAST_MASK) #define CAN_ESR1_BIT0ERR_FAST_MASK (0x40000000U) #define CAN_ESR1_BIT0ERR_FAST_SHIFT (30U) -/*! BIT0ERR_FAST - Bit0 Error in the Data Phase of CAN FD frames with the BRS bit - set +/*! BIT0ERR_FAST - Bit0 Error in the Data Phase of CAN FD frames with the BRS bit set * 0b0..No such occurrence. * 0b1..At least one bit sent as dominant is received as recessive. */ #define CAN_ESR1_BIT0ERR_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT0ERR_FAST_SHIFT)) & CAN_ESR1_BIT0ERR_FAST_MASK) #define CAN_ESR1_BIT1ERR_FAST_MASK (0x80000000U) #define CAN_ESR1_BIT1ERR_FAST_SHIFT (31U) -/*! BIT1ERR_FAST - Bit1 Error in the Data Phase of CAN FD frames with the BRS bit - set +/*! BIT1ERR_FAST - Bit1 Error in the Data Phase of CAN FD frames with the BRS bit set * 0b0..No such occurrence. * 0b1..At least one bit sent as recessive is received as dominant. */ @@ -3849,8 +3868,7 @@ typedef struct { /*! @{ */ #define CAN_IFLAG1_BUF0I_MASK (0x1U) #define CAN_IFLAG1_BUF0I_SHIFT (0U) -/*! BUF0I - Buffer MB0 Interrupt Or Clear Legacy - FIFO bit +/*! BUF0I - Buffer MB0 Interrupt Or Clear Legacy FIFO bit * 0b0..The corresponding buffer has no occurrence of successfully completed transmission or reception when CAN_MCR[RFEN]=0. * 0b1..The corresponding buffer has successfully completed transmission or reception when CAN_MCR[RFEN]=0. */ @@ -3867,29 +3885,31 @@ typedef struct { #define CAN_IFLAG1_BUF4TO1I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF4TO1I_SHIFT)) & CAN_IFLAG1_BUF4TO1I_MASK) #define CAN_IFLAG1_BUF5I_MASK (0x20U) #define CAN_IFLAG1_BUF5I_SHIFT (5U) -/*! BUF5I - Buffer MB5 Interrupt Or "Frames available in Legacy Rx FIFO" +/*! BUF5I - Buffer MB5 Interrupt Or "Frames available in Legacy Rx FIFO" * 0b0..No occurrence of MB5 completing transmission/reception when CAN_MCR[RFEN]=0, or of frame(s) available in the Legacy FIFO, when CAN_MCR[RFEN]=1 * 0b1..MB5 completed transmission/reception when CAN_MCR[RFEN]=0, or frame(s) available in the Legacy Rx FIFO when CAN_MCR[RFEN]=1. It generates a DMA request in case of CAN_MCR[RFEN] and CAN_MCR[DMA] are enabled. */ #define CAN_IFLAG1_BUF5I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF5I_SHIFT)) & CAN_IFLAG1_BUF5I_MASK) #define CAN_IFLAG1_BUF6I_MASK (0x40U) #define CAN_IFLAG1_BUF6I_SHIFT (6U) -/*! BUF6I - Buffer MB6 Interrupt Or "Legacy Rx - FIFO Warning" +/*! BUF6I - Buffer MB6 Interrupt Or "Legacy Rx FIFO Warning" * 0b0..No occurrence of MB6 completing transmission/reception when CAN_MCR[RFEN]=0, or of Legacy Rx FIFO almost full when CAN_MCR[RFEN]=1 * 0b1..MB6 completed transmission/reception when CAN_MCR[RFEN]=0, or Legacy Rx FIFO almost full when CAN_MCR[RFEN]=1 */ #define CAN_IFLAG1_BUF6I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF6I_SHIFT)) & CAN_IFLAG1_BUF6I_MASK) #define CAN_IFLAG1_BUF7I_MASK (0x80U) #define CAN_IFLAG1_BUF7I_SHIFT (7U) -/*! BUF7I - Buffer MB7 Interrupt Or "Legacy Rx - FIFO Overflow" +/*! BUF7I - Buffer MB7 Interrupt Or "Legacy Rx FIFO Overflow" * 0b0..No occurrence of MB7 completing transmission/reception when CAN_MCR[RFEN]=0, or of Legacy Rx FIFO overflow when CAN_MCR[RFEN]=1 * 0b1..MB7 completed transmission/reception when CAN_MCR[RFEN]=0, or Legacy Rx FIFO overflow when CAN_MCR[RFEN]=1 */ #define CAN_IFLAG1_BUF7I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF7I_SHIFT)) & CAN_IFLAG1_BUF7I_MASK) #define CAN_IFLAG1_BUF31TO8I_MASK (0xFFFFFF00U) #define CAN_IFLAG1_BUF31TO8I_SHIFT (8U) +/*! BUF31TO8I - Buffer MBi Interrupt + * 0b000000000000000000000001..The corresponding MB has successfully completed transmission or reception + * 0b000000000000000000000000..No such occurrence + */ #define CAN_IFLAG1_BUF31TO8I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF31TO8I_SHIFT)) & CAN_IFLAG1_BUF31TO8I_MASK) /*! @} */ @@ -3897,7 +3917,7 @@ typedef struct { /*! @{ */ #define CAN_CTRL2_TSTAMPCAP_MASK (0xC0U) #define CAN_CTRL2_TSTAMPCAP_SHIFT (6U) -/*! TSTAMPCAP - Time Stamp Capture Point +/*! TSTAMPCAP - Time Stamp Capture Point * 0b00..The high resolution time stamp capture is disabled * 0b01..The high resolution time stamp is captured in the end of the CAN frame * 0b10..The high resolution time stamp is captured in the start of the CAN frame @@ -3906,7 +3926,7 @@ typedef struct { #define CAN_CTRL2_TSTAMPCAP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_TSTAMPCAP_SHIFT)) & CAN_CTRL2_TSTAMPCAP_MASK) #define CAN_CTRL2_MBTSBASE_MASK (0x300U) #define CAN_CTRL2_MBTSBASE_SHIFT (8U) -/*! MBTSBASE - Message Buffer Time Stamp Base +/*! MBTSBASE - Message Buffer Time Stamp Base * 0b00..Message Buffer Time Stamp base is CAN_TIMER * 0b01..Message Buffer Time Stamp base is lower 16-bits of high resolution timer * 0b10..Message Buffer Time Stamp base is upper 16-bits of high resolution timerT @@ -3929,7 +3949,7 @@ typedef struct { #define CAN_CTRL2_ISOCANFDEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_ISOCANFDEN_SHIFT)) & CAN_CTRL2_ISOCANFDEN_MASK) #define CAN_CTRL2_BTE_MASK (0x2000U) #define CAN_CTRL2_BTE_SHIFT (13U) -/*! BTE - Bit Timing Expansion enable +/*! BTE - Bit Timing Expansion enable * 0b0..CAN Bit timing expansion is disabled. * 0b1..CAN bit timing expansion is enabled. */ @@ -3950,8 +3970,7 @@ typedef struct { #define CAN_CTRL2_TIMER_SRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_TIMER_SRC_SHIFT)) & CAN_CTRL2_TIMER_SRC_MASK) #define CAN_CTRL2_EACEN_MASK (0x10000U) #define CAN_CTRL2_EACEN_SHIFT (16U) -/*! EACEN - Entire Frame Arbitration Field Comparison Enable For Rx - Mailboxes +/*! EACEN - Entire Frame Arbitration Field Comparison Enable For Rx Mailboxes * 0b0..Rx Mailbox filter's IDE bit is always compared and RTR is never compared despite mask bits. * 0b1..Enables the comparison of both Rx Mailbox filter's IDE and RTR bit with their corresponding bits within the incoming frame. Mask bits do apply. */ @@ -3992,8 +4011,7 @@ typedef struct { #define CAN_CTRL2_BOFFDONEMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_BOFFDONEMSK_SHIFT)) & CAN_CTRL2_BOFFDONEMSK_MASK) #define CAN_CTRL2_ERRMSK_FAST_MASK (0x80000000U) #define CAN_CTRL2_ERRMSK_FAST_SHIFT (31U) -/*! ERRMSK_FAST - Error Interrupt Mask for errors detected in the Data Phase of fast - CAN FD frames +/*! ERRMSK_FAST - Error Interrupt Mask for errors detected in the Data Phase of fast CAN FD frames * 0b0..ERRINT_FAST Error interrupt disabled. * 0b1..ERRINT_FAST Error interrupt enabled. */ @@ -4035,6 +4053,10 @@ typedef struct { /*! @{ */ #define CAN_RXFGMASK_FGM_MASK (0xFFFFFFFFU) #define CAN_RXFGMASK_FGM_SHIFT (0U) +/*! FGM - Legacy Rx FIFO Global Mask Bits + * 0b00000000000000000000000000000001..The corresponding bit in the filter is checked + * 0b00000000000000000000000000000000..The corresponding bit in the filter is "don't care" + */ #define CAN_RXFGMASK_FGM(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXFGMASK_FGM_SHIFT)) & CAN_RXFGMASK_FGM_MASK) /*! @} */ @@ -4071,6 +4093,40 @@ typedef struct { #define CAN_CBT_BTF(x) (((uint32_t)(((uint32_t)(x)) << CAN_CBT_BTF_SHIFT)) & CAN_CBT_BTF_MASK) /*! @} */ +/*! @name DBG1 - Debug 1 register */ +/*! @{ */ +#define CAN_DBG1_CFSM_MASK (0x3FU) +#define CAN_DBG1_CFSM_SHIFT (0U) +#define CAN_DBG1_CFSM(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBG1_CFSM_SHIFT)) & CAN_DBG1_CFSM_MASK) +#define CAN_DBG1_CBN_MASK (0x1F000000U) +#define CAN_DBG1_CBN_SHIFT (24U) +#define CAN_DBG1_CBN(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBG1_CBN_SHIFT)) & CAN_DBG1_CBN_MASK) +/*! @} */ + +/*! @name DBG2 - Debug 2 register */ +/*! @{ */ +#define CAN_DBG2_RMP_MASK (0x7FU) +#define CAN_DBG2_RMP_SHIFT (0U) +#define CAN_DBG2_RMP(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBG2_RMP_SHIFT)) & CAN_DBG2_RMP_MASK) +#define CAN_DBG2_MPP_MASK (0x80U) +#define CAN_DBG2_MPP_SHIFT (7U) +/*! MPP - Matching Process in Progress + * 0b0..No matching process ongoing. + * 0b1..Matching process is in progress. + */ +#define CAN_DBG2_MPP(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBG2_MPP_SHIFT)) & CAN_DBG2_MPP_MASK) +#define CAN_DBG2_TAP_MASK (0x7F00U) +#define CAN_DBG2_TAP_SHIFT (8U) +#define CAN_DBG2_TAP(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBG2_TAP_SHIFT)) & CAN_DBG2_TAP_MASK) +#define CAN_DBG2_APP_MASK (0x8000U) +#define CAN_DBG2_APP_SHIFT (15U) +/*! APP - Arbitration Process in Progress + * 0b0..No matching process ongoing. + * 0b1..Matching process is in progress. + */ +#define CAN_DBG2_APP(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBG2_APP_SHIFT)) & CAN_DBG2_APP_MASK) +/*! @} */ + /* The count of CAN_CS */ #define CAN_CS_COUNT_MB16B (42U) @@ -4407,6 +4463,10 @@ typedef struct { /*! @{ */ #define CAN_RXIMR_MI_MASK (0xFFFFFFFFU) #define CAN_RXIMR_MI_SHIFT (0U) +/*! MI - Individual Mask Bits + * 0b00000000000000000000000000000001..The corresponding bit in the filter is checked + * 0b00000000000000000000000000000000..the corresponding bit in the filter is "don't care" + */ #define CAN_RXIMR_MI(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXIMR_MI_SHIFT)) & CAN_RXIMR_MI_MASK) /*! @} */ @@ -4466,7 +4526,7 @@ typedef struct { #define CAN_ETDC_ETDCOFF(x) (((uint32_t)(((uint32_t)(x)) << CAN_ETDC_ETDCOFF_SHIFT)) & CAN_ETDC_ETDCOFF_MASK) #define CAN_ETDC_TDMDIS_MASK (0x80000000U) #define CAN_ETDC_TDMDIS_SHIFT (31U) -/*! TDMDIS - Transceiver Delay Measurement Disable +/*! TDMDIS - Transceiver Delay Measurement Disable * 0b0..TDC measurement is enabled * 0b1..TDC measurement is disabled */ @@ -4567,7 +4627,7 @@ typedef struct { #define CAN_ERFCR_DMALW(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFCR_DMALW_SHIFT)) & CAN_ERFCR_DMALW_MASK) #define CAN_ERFCR_ERFEN_MASK (0x80000000U) #define CAN_ERFCR_ERFEN_SHIFT (31U) -/*! ERFEN - Enhanced Rx FIFO enable +/*! ERFEN - Enhanced Rx FIFO enable * 0b0..Enhanced Rx FIFO is disabled * 0b1..Enhanced Rx FIFO is enabled */ @@ -4578,28 +4638,28 @@ typedef struct { /*! @{ */ #define CAN_ERFIER_ERFDAIE_MASK (0x10000000U) #define CAN_ERFIER_ERFDAIE_SHIFT (28U) -/*! ERFDAIE - Enhanced Rx FIFO Data Available Interrupt Enable +/*! ERFDAIE - Enhanced Rx FIFO Data Available Interrupt Enable * 0b0..Enhanced Rx FIFO Data Available Interrupt is disabled * 0b1..Enhanced Rx FIFO Data Available Interrupt is enabled */ #define CAN_ERFIER_ERFDAIE(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFIER_ERFDAIE_SHIFT)) & CAN_ERFIER_ERFDAIE_MASK) #define CAN_ERFIER_ERFWMIIE_MASK (0x20000000U) #define CAN_ERFIER_ERFWMIIE_SHIFT (29U) -/*! ERFWMIIE - Enhanced Rx FIFO Watermark Indication Interrupt Enable +/*! ERFWMIIE - Enhanced Rx FIFO Watermark Indication Interrupt Enable * 0b0..Enhanced Rx FIFO Watermark Interrupt is disabled * 0b1..Enhanced Rx FIFO Watermark Interrupt is enabled */ #define CAN_ERFIER_ERFWMIIE(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFIER_ERFWMIIE_SHIFT)) & CAN_ERFIER_ERFWMIIE_MASK) #define CAN_ERFIER_ERFOVFIE_MASK (0x40000000U) #define CAN_ERFIER_ERFOVFIE_SHIFT (30U) -/*! ERFOVFIE - Enhanced Rx FIFO Overflow Interrupt Enable +/*! ERFOVFIE - Enhanced Rx FIFO Overflow Interrupt Enable * 0b0..Enhanced Rx FIFO Overflow is disabled * 0b1..Enhanced Rx FIFO Overflow is enabled */ #define CAN_ERFIER_ERFOVFIE(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFIER_ERFOVFIE_SHIFT)) & CAN_ERFIER_ERFOVFIE_MASK) #define CAN_ERFIER_ERFUFWIE_MASK (0x80000000U) #define CAN_ERFIER_ERFUFWIE_SHIFT (31U) -/*! ERFUFWIE - Enhanced Rx FIFO Underflow Interrupt Enable +/*! ERFUFWIE - Enhanced Rx FIFO Underflow Interrupt Enable * 0b0..Enhanced Rx FIFO Underflow interrupt is disabled * 0b1..Enhanced Rx FIFO Underflow interrupt is enabled */ @@ -4613,49 +4673,49 @@ typedef struct { #define CAN_ERFSR_ERFEL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFSR_ERFEL_SHIFT)) & CAN_ERFSR_ERFEL_MASK) #define CAN_ERFSR_ERFF_MASK (0x10000U) #define CAN_ERFSR_ERFF_SHIFT (16U) -/*! ERFF - Enhanced Rx FIFO full +/*! ERFF - Enhanced Rx FIFO full * 0b0..Enhanced Rx FIFO is not full * 0b1..Enhanced Rx FIFO is full */ #define CAN_ERFSR_ERFF(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFSR_ERFF_SHIFT)) & CAN_ERFSR_ERFF_MASK) #define CAN_ERFSR_ERFE_MASK (0x20000U) #define CAN_ERFSR_ERFE_SHIFT (17U) -/*! ERFE - Enhanced Rx FIFO empty +/*! ERFE - Enhanced Rx FIFO empty * 0b0..Enhanced Rx FIFO is not empty * 0b1..Enhanced Rx FIFO is empty */ #define CAN_ERFSR_ERFE(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFSR_ERFE_SHIFT)) & CAN_ERFSR_ERFE_MASK) #define CAN_ERFSR_ERFCLR_MASK (0x8000000U) #define CAN_ERFSR_ERFCLR_SHIFT (27U) -/*! ERFCLR - Enhanced Rx FIFO Clear +/*! ERFCLR - Enhanced Rx FIFO Clear * 0b0..No effect * 0b1..Clear Enhanced Rx FIFO content */ #define CAN_ERFSR_ERFCLR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFSR_ERFCLR_SHIFT)) & CAN_ERFSR_ERFCLR_MASK) #define CAN_ERFSR_ERFDA_MASK (0x10000000U) #define CAN_ERFSR_ERFDA_SHIFT (28U) -/*! ERFDA - Enhanced Rx FIFO Data Available +/*! ERFDA - Enhanced Rx FIFO Data Available * 0b0..No such occurrence * 0b1..There is at least one message stored in Enhanced Rx FIFO */ #define CAN_ERFSR_ERFDA(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFSR_ERFDA_SHIFT)) & CAN_ERFSR_ERFDA_MASK) #define CAN_ERFSR_ERFWMI_MASK (0x20000000U) #define CAN_ERFSR_ERFWMI_SHIFT (29U) -/*! ERFWMI - Enhanced Rx FIFO Watermark Indication +/*! ERFWMI - Enhanced Rx FIFO Watermark Indication * 0b0..No such occurrence * 0b1..The number of messages in FIFO is greater than the watermark */ #define CAN_ERFSR_ERFWMI(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFSR_ERFWMI_SHIFT)) & CAN_ERFSR_ERFWMI_MASK) #define CAN_ERFSR_ERFOVF_MASK (0x40000000U) #define CAN_ERFSR_ERFOVF_SHIFT (30U) -/*! ERFOVF - Enhanced Rx FIFO Overflow +/*! ERFOVF - Enhanced Rx FIFO Overflow * 0b0..No such occurrence * 0b1..Enhanced Rx FIFO overflow */ #define CAN_ERFSR_ERFOVF(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFSR_ERFOVF_SHIFT)) & CAN_ERFSR_ERFOVF_MASK) #define CAN_ERFSR_ERFUFW_MASK (0x80000000U) #define CAN_ERFSR_ERFUFW_SHIFT (31U) -/*! ERFUFW - Enhanced Rx FIFO Underflow +/*! ERFUFW - Enhanced Rx FIFO Underflow * 0b0..No such occurrence * 0b1..Enhanced Rx FIFO underflow */ @@ -4713,7 +4773,6 @@ typedef struct { #define CAN_Bus_Off_IRQS { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn, CAN3_IRQn } #define CAN_ORed_Message_buffer_IRQS { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn, CAN3_IRQn } - /*! * @} */ /* end of group CAN_Peripheral_Access_Layer */ @@ -11282,9 +11341,17 @@ typedef struct { /*! @{ */ #define DMA_CR_EDBG_MASK (0x2U) #define DMA_CR_EDBG_SHIFT (1U) +/*! EDBG - Enable Debug + * 0b0..When in debug mode, the DMA continues to operate. + * 0b1..When in debug mode, the DMA stalls the start of a new channel. Executing channels are allowed to complete. Channel execution resumes when the system exits debug mode or the EDBG bit is cleared. + */ #define DMA_CR_EDBG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_EDBG_SHIFT)) & DMA_CR_EDBG_MASK) #define DMA_CR_ERCA_MASK (0x4U) #define DMA_CR_ERCA_SHIFT (2U) +/*! ERCA - Enable Round Robin Channel Arbitration + * 0b0..Fixed priority arbitration is used for channel selection within each group. + * 0b1..Round robin arbitration is used for channel selection within each group. + */ #define DMA_CR_ERCA(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ERCA_SHIFT)) & DMA_CR_ERCA_MASK) #define DMA_CR_ERGA_MASK (0x8U) #define DMA_CR_ERGA_SHIFT (3U) @@ -11377,6 +11444,7 @@ typedef struct { #define DMA_ES_NCE_SHIFT (3U) /*! NCE - NBYTES/CITER Configuration Error * 0b0..No NBYTES/CITER configuration error + * 0b1..The last recorded error was a configuration error detected in the TCDn_NBYTES or TCDn_CITER fields. TCDn_NBYTES is not a multiple of TCDn_ATTR[SSIZE] and TCDn_ATTR[DSIZE], or TCDn_CITER[CITER] is equal to zero, or TCDn_CITER[ELINK] is not equal to TCDn_BITER[ELINK] */ #define DMA_ES_NCE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_NCE_SHIFT)) & DMA_ES_NCE_MASK) #define DMA_ES_DOE_MASK (0x10U) @@ -11414,6 +11482,7 @@ typedef struct { #define DMA_ES_CPE_SHIFT (14U) /*! CPE - Channel Priority Error * 0b0..No channel priority error + * 0b1..The last recorded error was a configuration error in the channel priorities within a group. Channel priorities within a group are not unique. */ #define DMA_ES_CPE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_CPE_SHIFT)) & DMA_ES_CPE_MASK) #define DMA_ES_GPE_MASK (0x8000U) @@ -11902,6 +11971,10 @@ typedef struct { #define DMA_CEEI_CEEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_CEEI_SHIFT)) & DMA_CEEI_CEEI_MASK) #define DMA_CEEI_CAEE_MASK (0x40U) #define DMA_CEEI_CAEE_SHIFT (6U) +/*! CAEE - Clear All Enable Error Interrupts + * 0b0..Clear only the EEI bit specified in the CEEI field + * 0b1..Clear all bits in EEI + */ #define DMA_CEEI_CAEE(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_CAEE_SHIFT)) & DMA_CEEI_CAEE_MASK) #define DMA_CEEI_NOP_MASK (0x80U) #define DMA_CEEI_NOP_SHIFT (7U) @@ -11919,6 +11992,10 @@ typedef struct { #define DMA_SEEI_SEEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_SEEI_SHIFT)) & DMA_SEEI_SEEI_MASK) #define DMA_SEEI_SAEE_MASK (0x40U) #define DMA_SEEI_SAEE_SHIFT (6U) +/*! SAEE - Sets All Enable Error Interrupts + * 0b0..Set only the EEI bit specified in the SEEI field. + * 0b1..Sets all bits in EEI + */ #define DMA_SEEI_SAEE(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_SAEE_SHIFT)) & DMA_SEEI_SAEE_MASK) #define DMA_SEEI_NOP_MASK (0x80U) #define DMA_SEEI_NOP_SHIFT (7U) @@ -11936,6 +12013,10 @@ typedef struct { #define DMA_CERQ_CERQ(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_CERQ_SHIFT)) & DMA_CERQ_CERQ_MASK) #define DMA_CERQ_CAER_MASK (0x40U) #define DMA_CERQ_CAER_SHIFT (6U) +/*! CAER - Clear All Enable Requests + * 0b0..Clear only the ERQ bit specified in the CERQ field + * 0b1..Clear all bits in ERQ + */ #define DMA_CERQ_CAER(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_CAER_SHIFT)) & DMA_CERQ_CAER_MASK) #define DMA_CERQ_NOP_MASK (0x80U) #define DMA_CERQ_NOP_SHIFT (7U) @@ -11953,6 +12034,10 @@ typedef struct { #define DMA_SERQ_SERQ(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_SERQ_SHIFT)) & DMA_SERQ_SERQ_MASK) #define DMA_SERQ_SAER_MASK (0x40U) #define DMA_SERQ_SAER_SHIFT (6U) +/*! SAER - Set All Enable Requests + * 0b0..Set only the ERQ bit specified in the SERQ field + * 0b1..Set all bits in ERQ + */ #define DMA_SERQ_SAER(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_SAER_SHIFT)) & DMA_SERQ_SAER_MASK) #define DMA_SERQ_NOP_MASK (0x80U) #define DMA_SERQ_NOP_SHIFT (7U) @@ -12012,6 +12097,10 @@ typedef struct { #define DMA_CERR_CERR(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_CERR_SHIFT)) & DMA_CERR_CERR_MASK) #define DMA_CERR_CAEI_MASK (0x40U) #define DMA_CERR_CAEI_SHIFT (6U) +/*! CAEI - Clear All Error Indicators + * 0b0..Clear only the ERR bit specified in the CERR field + * 0b1..Clear all bits in ERR + */ #define DMA_CERR_CAEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_CAEI_SHIFT)) & DMA_CERR_CAEI_MASK) #define DMA_CERR_NOP_MASK (0x80U) #define DMA_CERR_NOP_SHIFT (7U) @@ -12029,6 +12118,10 @@ typedef struct { #define DMA_CINT_CINT(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_CINT_SHIFT)) & DMA_CINT_CINT_MASK) #define DMA_CINT_CAIR_MASK (0x40U) #define DMA_CINT_CAIR_SHIFT (6U) +/*! CAIR - Clear All Interrupt Requests + * 0b0..Clear only the INT bit specified in the CINT field + * 0b1..Clear all bits in INT + */ #define DMA_CINT_CAIR(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_CAIR_SHIFT)) & DMA_CINT_CAIR_MASK) #define DMA_CINT_NOP_MASK (0x80U) #define DMA_CINT_NOP_SHIFT (7U) @@ -12727,256 +12820,224 @@ typedef struct { /*! @{ */ #define DMA_EARS_EDREQ_0_MASK (0x1U) #define DMA_EARS_EDREQ_0_SHIFT (0U) -/*! EDREQ_0 - Enable asynchronous DMA request in stop mode for channel - 0. +/*! EDREQ_0 - Enable asynchronous DMA request in stop mode for channel 0. * 0b0..Disable asynchronous DMA request for channel 0. * 0b1..Enable asynchronous DMA request for channel 0. */ #define DMA_EARS_EDREQ_0(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_0_SHIFT)) & DMA_EARS_EDREQ_0_MASK) #define DMA_EARS_EDREQ_1_MASK (0x2U) #define DMA_EARS_EDREQ_1_SHIFT (1U) -/*! EDREQ_1 - Enable asynchronous DMA request in stop mode for channel - 1. +/*! EDREQ_1 - Enable asynchronous DMA request in stop mode for channel 1. * 0b0..Disable asynchronous DMA request for channel 1 * 0b1..Enable asynchronous DMA request for channel 1. */ #define DMA_EARS_EDREQ_1(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_1_SHIFT)) & DMA_EARS_EDREQ_1_MASK) #define DMA_EARS_EDREQ_2_MASK (0x4U) #define DMA_EARS_EDREQ_2_SHIFT (2U) -/*! EDREQ_2 - Enable asynchronous DMA request in stop mode for channel - 2. +/*! EDREQ_2 - Enable asynchronous DMA request in stop mode for channel 2. * 0b0..Disable asynchronous DMA request for channel 2. * 0b1..Enable asynchronous DMA request for channel 2. */ #define DMA_EARS_EDREQ_2(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_2_SHIFT)) & DMA_EARS_EDREQ_2_MASK) #define DMA_EARS_EDREQ_3_MASK (0x8U) #define DMA_EARS_EDREQ_3_SHIFT (3U) -/*! EDREQ_3 - Enable asynchronous DMA request in stop mode for channel - 3. +/*! EDREQ_3 - Enable asynchronous DMA request in stop mode for channel 3. * 0b0..Disable asynchronous DMA request for channel 3. * 0b1..Enable asynchronous DMA request for channel 3. */ #define DMA_EARS_EDREQ_3(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_3_SHIFT)) & DMA_EARS_EDREQ_3_MASK) #define DMA_EARS_EDREQ_4_MASK (0x10U) #define DMA_EARS_EDREQ_4_SHIFT (4U) -/*! EDREQ_4 - Enable asynchronous DMA request in stop mode for channel - 4 +/*! EDREQ_4 - Enable asynchronous DMA request in stop mode for channel 4 * 0b0..Disable asynchronous DMA request for channel 4. * 0b1..Enable asynchronous DMA request for channel 4. */ #define DMA_EARS_EDREQ_4(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_4_SHIFT)) & DMA_EARS_EDREQ_4_MASK) #define DMA_EARS_EDREQ_5_MASK (0x20U) #define DMA_EARS_EDREQ_5_SHIFT (5U) -/*! EDREQ_5 - Enable asynchronous DMA request in stop mode for channel - 5 +/*! EDREQ_5 - Enable asynchronous DMA request in stop mode for channel 5 * 0b0..Disable asynchronous DMA request for channel 5. * 0b1..Enable asynchronous DMA request for channel 5. */ #define DMA_EARS_EDREQ_5(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_5_SHIFT)) & DMA_EARS_EDREQ_5_MASK) #define DMA_EARS_EDREQ_6_MASK (0x40U) #define DMA_EARS_EDREQ_6_SHIFT (6U) -/*! EDREQ_6 - Enable asynchronous DMA request in stop mode for channel - 6 +/*! EDREQ_6 - Enable asynchronous DMA request in stop mode for channel 6 * 0b0..Disable asynchronous DMA request for channel 6. * 0b1..Enable asynchronous DMA request for channel 6. */ #define DMA_EARS_EDREQ_6(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_6_SHIFT)) & DMA_EARS_EDREQ_6_MASK) #define DMA_EARS_EDREQ_7_MASK (0x80U) #define DMA_EARS_EDREQ_7_SHIFT (7U) -/*! EDREQ_7 - Enable asynchronous DMA request in stop mode for channel - 7 +/*! EDREQ_7 - Enable asynchronous DMA request in stop mode for channel 7 * 0b0..Disable asynchronous DMA request for channel 7. * 0b1..Enable asynchronous DMA request for channel 7. */ #define DMA_EARS_EDREQ_7(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_7_SHIFT)) & DMA_EARS_EDREQ_7_MASK) #define DMA_EARS_EDREQ_8_MASK (0x100U) #define DMA_EARS_EDREQ_8_SHIFT (8U) -/*! EDREQ_8 - Enable asynchronous DMA request in stop mode for channel - 8 +/*! EDREQ_8 - Enable asynchronous DMA request in stop mode for channel 8 * 0b0..Disable asynchronous DMA request for channel 8. * 0b1..Enable asynchronous DMA request for channel 8. */ #define DMA_EARS_EDREQ_8(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_8_SHIFT)) & DMA_EARS_EDREQ_8_MASK) #define DMA_EARS_EDREQ_9_MASK (0x200U) #define DMA_EARS_EDREQ_9_SHIFT (9U) -/*! EDREQ_9 - Enable asynchronous DMA request in stop mode for channel - 9 +/*! EDREQ_9 - Enable asynchronous DMA request in stop mode for channel 9 * 0b0..Disable asynchronous DMA request for channel 9. * 0b1..Enable asynchronous DMA request for channel 9. */ #define DMA_EARS_EDREQ_9(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_9_SHIFT)) & DMA_EARS_EDREQ_9_MASK) #define DMA_EARS_EDREQ_10_MASK (0x400U) #define DMA_EARS_EDREQ_10_SHIFT (10U) -/*! EDREQ_10 - Enable asynchronous DMA request in stop mode for channel - 10 +/*! EDREQ_10 - Enable asynchronous DMA request in stop mode for channel 10 * 0b0..Disable asynchronous DMA request for channel 10. * 0b1..Enable asynchronous DMA request for channel 10. */ #define DMA_EARS_EDREQ_10(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_10_SHIFT)) & DMA_EARS_EDREQ_10_MASK) #define DMA_EARS_EDREQ_11_MASK (0x800U) #define DMA_EARS_EDREQ_11_SHIFT (11U) -/*! EDREQ_11 - Enable asynchronous DMA request in stop mode for channel - 11 +/*! EDREQ_11 - Enable asynchronous DMA request in stop mode for channel 11 * 0b0..Disable asynchronous DMA request for channel 11. * 0b1..Enable asynchronous DMA request for channel 11. */ #define DMA_EARS_EDREQ_11(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_11_SHIFT)) & DMA_EARS_EDREQ_11_MASK) #define DMA_EARS_EDREQ_12_MASK (0x1000U) #define DMA_EARS_EDREQ_12_SHIFT (12U) -/*! EDREQ_12 - Enable asynchronous DMA request in stop mode for channel - 12 +/*! EDREQ_12 - Enable asynchronous DMA request in stop mode for channel 12 * 0b0..Disable asynchronous DMA request for channel 12. * 0b1..Enable asynchronous DMA request for channel 12. */ #define DMA_EARS_EDREQ_12(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_12_SHIFT)) & DMA_EARS_EDREQ_12_MASK) #define DMA_EARS_EDREQ_13_MASK (0x2000U) #define DMA_EARS_EDREQ_13_SHIFT (13U) -/*! EDREQ_13 - Enable asynchronous DMA request in stop mode for channel - 13 +/*! EDREQ_13 - Enable asynchronous DMA request in stop mode for channel 13 * 0b0..Disable asynchronous DMA request for channel 13. * 0b1..Enable asynchronous DMA request for channel 13. */ #define DMA_EARS_EDREQ_13(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_13_SHIFT)) & DMA_EARS_EDREQ_13_MASK) #define DMA_EARS_EDREQ_14_MASK (0x4000U) #define DMA_EARS_EDREQ_14_SHIFT (14U) -/*! EDREQ_14 - Enable asynchronous DMA request in stop mode for channel - 14 +/*! EDREQ_14 - Enable asynchronous DMA request in stop mode for channel 14 * 0b0..Disable asynchronous DMA request for channel 14. * 0b1..Enable asynchronous DMA request for channel 14. */ #define DMA_EARS_EDREQ_14(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_14_SHIFT)) & DMA_EARS_EDREQ_14_MASK) #define DMA_EARS_EDREQ_15_MASK (0x8000U) #define DMA_EARS_EDREQ_15_SHIFT (15U) -/*! EDREQ_15 - Enable asynchronous DMA request in stop mode for channel - 15 +/*! EDREQ_15 - Enable asynchronous DMA request in stop mode for channel 15 * 0b0..Disable asynchronous DMA request for channel 15. * 0b1..Enable asynchronous DMA request for channel 15. */ #define DMA_EARS_EDREQ_15(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_15_SHIFT)) & DMA_EARS_EDREQ_15_MASK) #define DMA_EARS_EDREQ_16_MASK (0x10000U) #define DMA_EARS_EDREQ_16_SHIFT (16U) -/*! EDREQ_16 - Enable asynchronous DMA request in stop mode for channel - 16 +/*! EDREQ_16 - Enable asynchronous DMA request in stop mode for channel 16 * 0b0..Disable asynchronous DMA request for channel 16 * 0b1..Enable asynchronous DMA request for channel 16 */ #define DMA_EARS_EDREQ_16(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_16_SHIFT)) & DMA_EARS_EDREQ_16_MASK) #define DMA_EARS_EDREQ_17_MASK (0x20000U) #define DMA_EARS_EDREQ_17_SHIFT (17U) -/*! EDREQ_17 - Enable asynchronous DMA request in stop mode for channel - 17 +/*! EDREQ_17 - Enable asynchronous DMA request in stop mode for channel 17 * 0b0..Disable asynchronous DMA request for channel 17 * 0b1..Enable asynchronous DMA request for channel 17 */ #define DMA_EARS_EDREQ_17(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_17_SHIFT)) & DMA_EARS_EDREQ_17_MASK) #define DMA_EARS_EDREQ_18_MASK (0x40000U) #define DMA_EARS_EDREQ_18_SHIFT (18U) -/*! EDREQ_18 - Enable asynchronous DMA request in stop mode for channel - 18 +/*! EDREQ_18 - Enable asynchronous DMA request in stop mode for channel 18 * 0b0..Disable asynchronous DMA request for channel 18 * 0b1..Enable asynchronous DMA request for channel 18 */ #define DMA_EARS_EDREQ_18(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_18_SHIFT)) & DMA_EARS_EDREQ_18_MASK) #define DMA_EARS_EDREQ_19_MASK (0x80000U) #define DMA_EARS_EDREQ_19_SHIFT (19U) -/*! EDREQ_19 - Enable asynchronous DMA request in stop mode for channel - 19 +/*! EDREQ_19 - Enable asynchronous DMA request in stop mode for channel 19 * 0b0..Disable asynchronous DMA request for channel 19 * 0b1..Enable asynchronous DMA request for channel 19 */ #define DMA_EARS_EDREQ_19(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_19_SHIFT)) & DMA_EARS_EDREQ_19_MASK) #define DMA_EARS_EDREQ_20_MASK (0x100000U) #define DMA_EARS_EDREQ_20_SHIFT (20U) -/*! EDREQ_20 - Enable asynchronous DMA request in stop mode for channel - 20 +/*! EDREQ_20 - Enable asynchronous DMA request in stop mode for channel 20 * 0b0..Disable asynchronous DMA request for channel 20 * 0b1..Enable asynchronous DMA request for channel 20 */ #define DMA_EARS_EDREQ_20(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_20_SHIFT)) & DMA_EARS_EDREQ_20_MASK) #define DMA_EARS_EDREQ_21_MASK (0x200000U) #define DMA_EARS_EDREQ_21_SHIFT (21U) -/*! EDREQ_21 - Enable asynchronous DMA request in stop mode for channel - 21 +/*! EDREQ_21 - Enable asynchronous DMA request in stop mode for channel 21 * 0b0..Disable asynchronous DMA request for channel 21 * 0b1..Enable asynchronous DMA request for channel 21 */ #define DMA_EARS_EDREQ_21(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_21_SHIFT)) & DMA_EARS_EDREQ_21_MASK) #define DMA_EARS_EDREQ_22_MASK (0x400000U) #define DMA_EARS_EDREQ_22_SHIFT (22U) -/*! EDREQ_22 - Enable asynchronous DMA request in stop mode for channel - 22 +/*! EDREQ_22 - Enable asynchronous DMA request in stop mode for channel 22 * 0b0..Disable asynchronous DMA request for channel 22 * 0b1..Enable asynchronous DMA request for channel 22 */ #define DMA_EARS_EDREQ_22(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_22_SHIFT)) & DMA_EARS_EDREQ_22_MASK) #define DMA_EARS_EDREQ_23_MASK (0x800000U) #define DMA_EARS_EDREQ_23_SHIFT (23U) -/*! EDREQ_23 - Enable asynchronous DMA request in stop mode for channel - 23 +/*! EDREQ_23 - Enable asynchronous DMA request in stop mode for channel 23 * 0b0..Disable asynchronous DMA request for channel 23 * 0b1..Enable asynchronous DMA request for channel 23 */ #define DMA_EARS_EDREQ_23(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_23_SHIFT)) & DMA_EARS_EDREQ_23_MASK) #define DMA_EARS_EDREQ_24_MASK (0x1000000U) #define DMA_EARS_EDREQ_24_SHIFT (24U) -/*! EDREQ_24 - Enable asynchronous DMA request in stop mode for channel - 24 +/*! EDREQ_24 - Enable asynchronous DMA request in stop mode for channel 24 * 0b0..Disable asynchronous DMA request for channel 24 * 0b1..Enable asynchronous DMA request for channel 24 */ #define DMA_EARS_EDREQ_24(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_24_SHIFT)) & DMA_EARS_EDREQ_24_MASK) #define DMA_EARS_EDREQ_25_MASK (0x2000000U) #define DMA_EARS_EDREQ_25_SHIFT (25U) -/*! EDREQ_25 - Enable asynchronous DMA request in stop mode for channel - 25 +/*! EDREQ_25 - Enable asynchronous DMA request in stop mode for channel 25 * 0b0..Disable asynchronous DMA request for channel 25 * 0b1..Enable asynchronous DMA request for channel 25 */ #define DMA_EARS_EDREQ_25(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_25_SHIFT)) & DMA_EARS_EDREQ_25_MASK) #define DMA_EARS_EDREQ_26_MASK (0x4000000U) #define DMA_EARS_EDREQ_26_SHIFT (26U) -/*! EDREQ_26 - Enable asynchronous DMA request in stop mode for channel - 26 +/*! EDREQ_26 - Enable asynchronous DMA request in stop mode for channel 26 * 0b0..Disable asynchronous DMA request for channel 26 * 0b1..Enable asynchronous DMA request for channel 26 */ #define DMA_EARS_EDREQ_26(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_26_SHIFT)) & DMA_EARS_EDREQ_26_MASK) #define DMA_EARS_EDREQ_27_MASK (0x8000000U) #define DMA_EARS_EDREQ_27_SHIFT (27U) -/*! EDREQ_27 - Enable asynchronous DMA request in stop mode for channel - 27 +/*! EDREQ_27 - Enable asynchronous DMA request in stop mode for channel 27 * 0b0..Disable asynchronous DMA request for channel 27 * 0b1..Enable asynchronous DMA request for channel 27 */ #define DMA_EARS_EDREQ_27(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_27_SHIFT)) & DMA_EARS_EDREQ_27_MASK) #define DMA_EARS_EDREQ_28_MASK (0x10000000U) #define DMA_EARS_EDREQ_28_SHIFT (28U) -/*! EDREQ_28 - Enable asynchronous DMA request in stop mode for channel - 28 +/*! EDREQ_28 - Enable asynchronous DMA request in stop mode for channel 28 * 0b0..Disable asynchronous DMA request for channel 28 * 0b1..Enable asynchronous DMA request for channel 28 */ #define DMA_EARS_EDREQ_28(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_28_SHIFT)) & DMA_EARS_EDREQ_28_MASK) #define DMA_EARS_EDREQ_29_MASK (0x20000000U) #define DMA_EARS_EDREQ_29_SHIFT (29U) -/*! EDREQ_29 - Enable asynchronous DMA request in stop mode for channel - 29 +/*! EDREQ_29 - Enable asynchronous DMA request in stop mode for channel 29 * 0b0..Disable asynchronous DMA request for channel 29 * 0b1..Enable asynchronous DMA request for channel 29 */ #define DMA_EARS_EDREQ_29(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_29_SHIFT)) & DMA_EARS_EDREQ_29_MASK) #define DMA_EARS_EDREQ_30_MASK (0x40000000U) #define DMA_EARS_EDREQ_30_SHIFT (30U) -/*! EDREQ_30 - Enable asynchronous DMA request in stop mode for channel - 30 +/*! EDREQ_30 - Enable asynchronous DMA request in stop mode for channel 30 * 0b0..Disable asynchronous DMA request for channel 30 * 0b1..Enable asynchronous DMA request for channel 30 */ #define DMA_EARS_EDREQ_30(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_30_SHIFT)) & DMA_EARS_EDREQ_30_MASK) #define DMA_EARS_EDREQ_31_MASK (0x80000000U) #define DMA_EARS_EDREQ_31_SHIFT (31U) -/*! EDREQ_31 - Enable asynchronous DMA request in stop mode for channel - 31 +/*! EDREQ_31 - Enable asynchronous DMA request in stop mode for channel 31 * 0b0..Disable asynchronous DMA request for channel 31 * 0b1..Enable asynchronous DMA request for channel 31 */ @@ -12993,16 +13054,14 @@ typedef struct { #define DMA_DCHPRI3_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_GRPPRI_SHIFT)) & DMA_DCHPRI3_GRPPRI_MASK) #define DMA_DCHPRI3_DPA_MASK (0x40U) #define DMA_DCHPRI3_DPA_SHIFT (6U) -/*! DPA - Disable Preempt Ability. This field resets to - 0. +/*! DPA - Disable Preempt Ability. This field resets to 0. * 0b0..Channel n can suspend a lower priority channel. * 0b1..Channel n cannot suspend any channel, regardless of channel priority. */ #define DMA_DCHPRI3_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_DPA_SHIFT)) & DMA_DCHPRI3_DPA_MASK) #define DMA_DCHPRI3_ECP_MASK (0x80U) #define DMA_DCHPRI3_ECP_SHIFT (7U) -/*! ECP - Enable Channel Preemption. This field resets to - 0. +/*! ECP - Enable Channel Preemption. This field resets to 0. * 0b0..Channel n cannot be suspended by a higher priority channel's service request. * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. */ @@ -13019,16 +13078,14 @@ typedef struct { #define DMA_DCHPRI2_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_GRPPRI_SHIFT)) & DMA_DCHPRI2_GRPPRI_MASK) #define DMA_DCHPRI2_DPA_MASK (0x40U) #define DMA_DCHPRI2_DPA_SHIFT (6U) -/*! DPA - Disable Preempt Ability. This field resets to - 0. +/*! DPA - Disable Preempt Ability. This field resets to 0. * 0b0..Channel n can suspend a lower priority channel. * 0b1..Channel n cannot suspend any channel, regardless of channel priority. */ #define DMA_DCHPRI2_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_DPA_SHIFT)) & DMA_DCHPRI2_DPA_MASK) #define DMA_DCHPRI2_ECP_MASK (0x80U) #define DMA_DCHPRI2_ECP_SHIFT (7U) -/*! ECP - Enable Channel Preemption. This field resets to - 0. +/*! ECP - Enable Channel Preemption. This field resets to 0. * 0b0..Channel n cannot be suspended by a higher priority channel's service request. * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. */ @@ -13045,16 +13102,14 @@ typedef struct { #define DMA_DCHPRI1_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_GRPPRI_SHIFT)) & DMA_DCHPRI1_GRPPRI_MASK) #define DMA_DCHPRI1_DPA_MASK (0x40U) #define DMA_DCHPRI1_DPA_SHIFT (6U) -/*! DPA - Disable Preempt Ability. This field resets to - 0. +/*! DPA - Disable Preempt Ability. This field resets to 0. * 0b0..Channel n can suspend a lower priority channel. * 0b1..Channel n cannot suspend any channel, regardless of channel priority. */ #define DMA_DCHPRI1_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_DPA_SHIFT)) & DMA_DCHPRI1_DPA_MASK) #define DMA_DCHPRI1_ECP_MASK (0x80U) #define DMA_DCHPRI1_ECP_SHIFT (7U) -/*! ECP - Enable Channel Preemption. This field resets to - 0. +/*! ECP - Enable Channel Preemption. This field resets to 0. * 0b0..Channel n cannot be suspended by a higher priority channel's service request. * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. */ @@ -13071,16 +13126,14 @@ typedef struct { #define DMA_DCHPRI0_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_GRPPRI_SHIFT)) & DMA_DCHPRI0_GRPPRI_MASK) #define DMA_DCHPRI0_DPA_MASK (0x40U) #define DMA_DCHPRI0_DPA_SHIFT (6U) -/*! DPA - Disable Preempt Ability. This field resets to - 0. +/*! DPA - Disable Preempt Ability. This field resets to 0. * 0b0..Channel n can suspend a lower priority channel. * 0b1..Channel n cannot suspend any channel, regardless of channel priority. */ #define DMA_DCHPRI0_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_DPA_SHIFT)) & DMA_DCHPRI0_DPA_MASK) #define DMA_DCHPRI0_ECP_MASK (0x80U) #define DMA_DCHPRI0_ECP_SHIFT (7U) -/*! ECP - Enable Channel Preemption. This field resets to - 0. +/*! ECP - Enable Channel Preemption. This field resets to 0. * 0b0..Channel n cannot be suspended by a higher priority channel's service request. * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. */ @@ -13097,16 +13150,14 @@ typedef struct { #define DMA_DCHPRI7_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_GRPPRI_SHIFT)) & DMA_DCHPRI7_GRPPRI_MASK) #define DMA_DCHPRI7_DPA_MASK (0x40U) #define DMA_DCHPRI7_DPA_SHIFT (6U) -/*! DPA - Disable Preempt Ability. This field resets to - 0. +/*! DPA - Disable Preempt Ability. This field resets to 0. * 0b0..Channel n can suspend a lower priority channel. * 0b1..Channel n cannot suspend any channel, regardless of channel priority. */ #define DMA_DCHPRI7_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_DPA_SHIFT)) & DMA_DCHPRI7_DPA_MASK) #define DMA_DCHPRI7_ECP_MASK (0x80U) #define DMA_DCHPRI7_ECP_SHIFT (7U) -/*! ECP - Enable Channel Preemption. This field resets to - 0. +/*! ECP - Enable Channel Preemption. This field resets to 0. * 0b0..Channel n cannot be suspended by a higher priority channel's service request. * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. */ @@ -13123,16 +13174,14 @@ typedef struct { #define DMA_DCHPRI6_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_GRPPRI_SHIFT)) & DMA_DCHPRI6_GRPPRI_MASK) #define DMA_DCHPRI6_DPA_MASK (0x40U) #define DMA_DCHPRI6_DPA_SHIFT (6U) -/*! DPA - Disable Preempt Ability. This field resets to - 0. +/*! DPA - Disable Preempt Ability. This field resets to 0. * 0b0..Channel n can suspend a lower priority channel. * 0b1..Channel n cannot suspend any channel, regardless of channel priority. */ #define DMA_DCHPRI6_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_DPA_SHIFT)) & DMA_DCHPRI6_DPA_MASK) #define DMA_DCHPRI6_ECP_MASK (0x80U) #define DMA_DCHPRI6_ECP_SHIFT (7U) -/*! ECP - Enable Channel Preemption. This field resets to - 0. +/*! ECP - Enable Channel Preemption. This field resets to 0. * 0b0..Channel n cannot be suspended by a higher priority channel's service request. * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. */ @@ -13149,16 +13198,14 @@ typedef struct { #define DMA_DCHPRI5_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_GRPPRI_SHIFT)) & DMA_DCHPRI5_GRPPRI_MASK) #define DMA_DCHPRI5_DPA_MASK (0x40U) #define DMA_DCHPRI5_DPA_SHIFT (6U) -/*! DPA - Disable Preempt Ability. This field resets to - 0. +/*! DPA - Disable Preempt Ability. This field resets to 0. * 0b0..Channel n can suspend a lower priority channel. * 0b1..Channel n cannot suspend any channel, regardless of channel priority. */ #define DMA_DCHPRI5_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_DPA_SHIFT)) & DMA_DCHPRI5_DPA_MASK) #define DMA_DCHPRI5_ECP_MASK (0x80U) #define DMA_DCHPRI5_ECP_SHIFT (7U) -/*! ECP - Enable Channel Preemption. This field resets to - 0. +/*! ECP - Enable Channel Preemption. This field resets to 0. * 0b0..Channel n cannot be suspended by a higher priority channel's service request. * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. */ @@ -13175,16 +13222,14 @@ typedef struct { #define DMA_DCHPRI4_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_GRPPRI_SHIFT)) & DMA_DCHPRI4_GRPPRI_MASK) #define DMA_DCHPRI4_DPA_MASK (0x40U) #define DMA_DCHPRI4_DPA_SHIFT (6U) -/*! DPA - Disable Preempt Ability. This field resets to - 0. +/*! DPA - Disable Preempt Ability. This field resets to 0. * 0b0..Channel n can suspend a lower priority channel. * 0b1..Channel n cannot suspend any channel, regardless of channel priority. */ #define DMA_DCHPRI4_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_DPA_SHIFT)) & DMA_DCHPRI4_DPA_MASK) #define DMA_DCHPRI4_ECP_MASK (0x80U) #define DMA_DCHPRI4_ECP_SHIFT (7U) -/*! ECP - Enable Channel Preemption. This field resets to - 0. +/*! ECP - Enable Channel Preemption. This field resets to 0. * 0b0..Channel n cannot be suspended by a higher priority channel's service request. * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. */ @@ -13201,16 +13246,14 @@ typedef struct { #define DMA_DCHPRI11_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_GRPPRI_SHIFT)) & DMA_DCHPRI11_GRPPRI_MASK) #define DMA_DCHPRI11_DPA_MASK (0x40U) #define DMA_DCHPRI11_DPA_SHIFT (6U) -/*! DPA - Disable Preempt Ability. This field resets to - 0. +/*! DPA - Disable Preempt Ability. This field resets to 0. * 0b0..Channel n can suspend a lower priority channel. * 0b1..Channel n cannot suspend any channel, regardless of channel priority. */ #define DMA_DCHPRI11_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_DPA_SHIFT)) & DMA_DCHPRI11_DPA_MASK) #define DMA_DCHPRI11_ECP_MASK (0x80U) #define DMA_DCHPRI11_ECP_SHIFT (7U) -/*! ECP - Enable Channel Preemption. This field resets to - 0. +/*! ECP - Enable Channel Preemption. This field resets to 0. * 0b0..Channel n cannot be suspended by a higher priority channel's service request. * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. */ @@ -13227,16 +13270,14 @@ typedef struct { #define DMA_DCHPRI10_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_GRPPRI_SHIFT)) & DMA_DCHPRI10_GRPPRI_MASK) #define DMA_DCHPRI10_DPA_MASK (0x40U) #define DMA_DCHPRI10_DPA_SHIFT (6U) -/*! DPA - Disable Preempt Ability. This field resets to - 0. +/*! DPA - Disable Preempt Ability. This field resets to 0. * 0b0..Channel n can suspend a lower priority channel. * 0b1..Channel n cannot suspend any channel, regardless of channel priority. */ #define DMA_DCHPRI10_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_DPA_SHIFT)) & DMA_DCHPRI10_DPA_MASK) #define DMA_DCHPRI10_ECP_MASK (0x80U) #define DMA_DCHPRI10_ECP_SHIFT (7U) -/*! ECP - Enable Channel Preemption. This field resets to - 0. +/*! ECP - Enable Channel Preemption. This field resets to 0. * 0b0..Channel n cannot be suspended by a higher priority channel's service request. * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. */ @@ -13253,16 +13294,14 @@ typedef struct { #define DMA_DCHPRI9_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_GRPPRI_SHIFT)) & DMA_DCHPRI9_GRPPRI_MASK) #define DMA_DCHPRI9_DPA_MASK (0x40U) #define DMA_DCHPRI9_DPA_SHIFT (6U) -/*! DPA - Disable Preempt Ability. This field resets to - 0. +/*! DPA - Disable Preempt Ability. This field resets to 0. * 0b0..Channel n can suspend a lower priority channel. * 0b1..Channel n cannot suspend any channel, regardless of channel priority. */ #define DMA_DCHPRI9_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_DPA_SHIFT)) & DMA_DCHPRI9_DPA_MASK) #define DMA_DCHPRI9_ECP_MASK (0x80U) #define DMA_DCHPRI9_ECP_SHIFT (7U) -/*! ECP - Enable Channel Preemption. This field resets to - 0. +/*! ECP - Enable Channel Preemption. This field resets to 0. * 0b0..Channel n cannot be suspended by a higher priority channel's service request. * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. */ @@ -13279,16 +13318,14 @@ typedef struct { #define DMA_DCHPRI8_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_GRPPRI_SHIFT)) & DMA_DCHPRI8_GRPPRI_MASK) #define DMA_DCHPRI8_DPA_MASK (0x40U) #define DMA_DCHPRI8_DPA_SHIFT (6U) -/*! DPA - Disable Preempt Ability. This field resets to - 0. +/*! DPA - Disable Preempt Ability. This field resets to 0. * 0b0..Channel n can suspend a lower priority channel. * 0b1..Channel n cannot suspend any channel, regardless of channel priority. */ #define DMA_DCHPRI8_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_DPA_SHIFT)) & DMA_DCHPRI8_DPA_MASK) #define DMA_DCHPRI8_ECP_MASK (0x80U) #define DMA_DCHPRI8_ECP_SHIFT (7U) -/*! ECP - Enable Channel Preemption. This field resets to - 0. +/*! ECP - Enable Channel Preemption. This field resets to 0. * 0b0..Channel n cannot be suspended by a higher priority channel's service request. * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. */ @@ -13305,16 +13342,14 @@ typedef struct { #define DMA_DCHPRI15_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_GRPPRI_SHIFT)) & DMA_DCHPRI15_GRPPRI_MASK) #define DMA_DCHPRI15_DPA_MASK (0x40U) #define DMA_DCHPRI15_DPA_SHIFT (6U) -/*! DPA - Disable Preempt Ability. This field resets to - 0. +/*! DPA - Disable Preempt Ability. This field resets to 0. * 0b0..Channel n can suspend a lower priority channel. * 0b1..Channel n cannot suspend any channel, regardless of channel priority. */ #define DMA_DCHPRI15_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_DPA_SHIFT)) & DMA_DCHPRI15_DPA_MASK) #define DMA_DCHPRI15_ECP_MASK (0x80U) #define DMA_DCHPRI15_ECP_SHIFT (7U) -/*! ECP - Enable Channel Preemption. This field resets to - 0. +/*! ECP - Enable Channel Preemption. This field resets to 0. * 0b0..Channel n cannot be suspended by a higher priority channel's service request. * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. */ @@ -13331,16 +13366,14 @@ typedef struct { #define DMA_DCHPRI14_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_GRPPRI_SHIFT)) & DMA_DCHPRI14_GRPPRI_MASK) #define DMA_DCHPRI14_DPA_MASK (0x40U) #define DMA_DCHPRI14_DPA_SHIFT (6U) -/*! DPA - Disable Preempt Ability. This field resets to - 0. +/*! DPA - Disable Preempt Ability. This field resets to 0. * 0b0..Channel n can suspend a lower priority channel. * 0b1..Channel n cannot suspend any channel, regardless of channel priority. */ #define DMA_DCHPRI14_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_DPA_SHIFT)) & DMA_DCHPRI14_DPA_MASK) #define DMA_DCHPRI14_ECP_MASK (0x80U) #define DMA_DCHPRI14_ECP_SHIFT (7U) -/*! ECP - Enable Channel Preemption. This field resets to - 0. +/*! ECP - Enable Channel Preemption. This field resets to 0. * 0b0..Channel n cannot be suspended by a higher priority channel's service request. * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. */ @@ -13357,16 +13390,14 @@ typedef struct { #define DMA_DCHPRI13_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_GRPPRI_SHIFT)) & DMA_DCHPRI13_GRPPRI_MASK) #define DMA_DCHPRI13_DPA_MASK (0x40U) #define DMA_DCHPRI13_DPA_SHIFT (6U) -/*! DPA - Disable Preempt Ability. This field resets to - 0. +/*! DPA - Disable Preempt Ability. This field resets to 0. * 0b0..Channel n can suspend a lower priority channel. * 0b1..Channel n cannot suspend any channel, regardless of channel priority. */ #define DMA_DCHPRI13_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_DPA_SHIFT)) & DMA_DCHPRI13_DPA_MASK) #define DMA_DCHPRI13_ECP_MASK (0x80U) #define DMA_DCHPRI13_ECP_SHIFT (7U) -/*! ECP - Enable Channel Preemption. This field resets to - 0. +/*! ECP - Enable Channel Preemption. This field resets to 0. * 0b0..Channel n cannot be suspended by a higher priority channel's service request. * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. */ @@ -13383,16 +13414,14 @@ typedef struct { #define DMA_DCHPRI12_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_GRPPRI_SHIFT)) & DMA_DCHPRI12_GRPPRI_MASK) #define DMA_DCHPRI12_DPA_MASK (0x40U) #define DMA_DCHPRI12_DPA_SHIFT (6U) -/*! DPA - Disable Preempt Ability. This field resets to - 0. +/*! DPA - Disable Preempt Ability. This field resets to 0. * 0b0..Channel n can suspend a lower priority channel. * 0b1..Channel n cannot suspend any channel, regardless of channel priority. */ #define DMA_DCHPRI12_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_DPA_SHIFT)) & DMA_DCHPRI12_DPA_MASK) #define DMA_DCHPRI12_ECP_MASK (0x80U) #define DMA_DCHPRI12_ECP_SHIFT (7U) -/*! ECP - Enable Channel Preemption. This field resets to - 0. +/*! ECP - Enable Channel Preemption. This field resets to 0. * 0b0..Channel n cannot be suspended by a higher priority channel's service request. * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. */ @@ -13409,16 +13438,14 @@ typedef struct { #define DMA_DCHPRI19_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_GRPPRI_SHIFT)) & DMA_DCHPRI19_GRPPRI_MASK) #define DMA_DCHPRI19_DPA_MASK (0x40U) #define DMA_DCHPRI19_DPA_SHIFT (6U) -/*! DPA - Disable Preempt Ability. This field resets to - 0. +/*! DPA - Disable Preempt Ability. This field resets to 0. * 0b0..Channel n can suspend a lower priority channel. * 0b1..Channel n cannot suspend any channel, regardless of channel priority. */ #define DMA_DCHPRI19_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_DPA_SHIFT)) & DMA_DCHPRI19_DPA_MASK) #define DMA_DCHPRI19_ECP_MASK (0x80U) #define DMA_DCHPRI19_ECP_SHIFT (7U) -/*! ECP - Enable Channel Preemption. This field resets to - 0. +/*! ECP - Enable Channel Preemption. This field resets to 0. * 0b0..Channel n cannot be suspended by a higher priority channel's service request. * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. */ @@ -13435,16 +13462,14 @@ typedef struct { #define DMA_DCHPRI18_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_GRPPRI_SHIFT)) & DMA_DCHPRI18_GRPPRI_MASK) #define DMA_DCHPRI18_DPA_MASK (0x40U) #define DMA_DCHPRI18_DPA_SHIFT (6U) -/*! DPA - Disable Preempt Ability. This field resets to - 0. +/*! DPA - Disable Preempt Ability. This field resets to 0. * 0b0..Channel n can suspend a lower priority channel. * 0b1..Channel n cannot suspend any channel, regardless of channel priority. */ #define DMA_DCHPRI18_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_DPA_SHIFT)) & DMA_DCHPRI18_DPA_MASK) #define DMA_DCHPRI18_ECP_MASK (0x80U) #define DMA_DCHPRI18_ECP_SHIFT (7U) -/*! ECP - Enable Channel Preemption. This field resets to - 0. +/*! ECP - Enable Channel Preemption. This field resets to 0. * 0b0..Channel n cannot be suspended by a higher priority channel's service request. * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. */ @@ -13461,16 +13486,14 @@ typedef struct { #define DMA_DCHPRI17_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_GRPPRI_SHIFT)) & DMA_DCHPRI17_GRPPRI_MASK) #define DMA_DCHPRI17_DPA_MASK (0x40U) #define DMA_DCHPRI17_DPA_SHIFT (6U) -/*! DPA - Disable Preempt Ability. This field resets to - 0. +/*! DPA - Disable Preempt Ability. This field resets to 0. * 0b0..Channel n can suspend a lower priority channel. * 0b1..Channel n cannot suspend any channel, regardless of channel priority. */ #define DMA_DCHPRI17_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_DPA_SHIFT)) & DMA_DCHPRI17_DPA_MASK) #define DMA_DCHPRI17_ECP_MASK (0x80U) #define DMA_DCHPRI17_ECP_SHIFT (7U) -/*! ECP - Enable Channel Preemption. This field resets to - 0. +/*! ECP - Enable Channel Preemption. This field resets to 0. * 0b0..Channel n cannot be suspended by a higher priority channel's service request. * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. */ @@ -13487,16 +13510,14 @@ typedef struct { #define DMA_DCHPRI16_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_GRPPRI_SHIFT)) & DMA_DCHPRI16_GRPPRI_MASK) #define DMA_DCHPRI16_DPA_MASK (0x40U) #define DMA_DCHPRI16_DPA_SHIFT (6U) -/*! DPA - Disable Preempt Ability. This field resets to - 0. +/*! DPA - Disable Preempt Ability. This field resets to 0. * 0b0..Channel n can suspend a lower priority channel. * 0b1..Channel n cannot suspend any channel, regardless of channel priority. */ #define DMA_DCHPRI16_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_DPA_SHIFT)) & DMA_DCHPRI16_DPA_MASK) #define DMA_DCHPRI16_ECP_MASK (0x80U) #define DMA_DCHPRI16_ECP_SHIFT (7U) -/*! ECP - Enable Channel Preemption. This field resets to - 0. +/*! ECP - Enable Channel Preemption. This field resets to 0. * 0b0..Channel n cannot be suspended by a higher priority channel's service request. * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. */ @@ -13513,16 +13534,14 @@ typedef struct { #define DMA_DCHPRI23_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_GRPPRI_SHIFT)) & DMA_DCHPRI23_GRPPRI_MASK) #define DMA_DCHPRI23_DPA_MASK (0x40U) #define DMA_DCHPRI23_DPA_SHIFT (6U) -/*! DPA - Disable Preempt Ability. This field resets to - 0. +/*! DPA - Disable Preempt Ability. This field resets to 0. * 0b0..Channel n can suspend a lower priority channel. * 0b1..Channel n cannot suspend any channel, regardless of channel priority. */ #define DMA_DCHPRI23_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_DPA_SHIFT)) & DMA_DCHPRI23_DPA_MASK) #define DMA_DCHPRI23_ECP_MASK (0x80U) #define DMA_DCHPRI23_ECP_SHIFT (7U) -/*! ECP - Enable Channel Preemption. This field resets to - 0. +/*! ECP - Enable Channel Preemption. This field resets to 0. * 0b0..Channel n cannot be suspended by a higher priority channel's service request. * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. */ @@ -13539,16 +13558,14 @@ typedef struct { #define DMA_DCHPRI22_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_GRPPRI_SHIFT)) & DMA_DCHPRI22_GRPPRI_MASK) #define DMA_DCHPRI22_DPA_MASK (0x40U) #define DMA_DCHPRI22_DPA_SHIFT (6U) -/*! DPA - Disable Preempt Ability. This field resets to - 0. +/*! DPA - Disable Preempt Ability. This field resets to 0. * 0b0..Channel n can suspend a lower priority channel. * 0b1..Channel n cannot suspend any channel, regardless of channel priority. */ #define DMA_DCHPRI22_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_DPA_SHIFT)) & DMA_DCHPRI22_DPA_MASK) #define DMA_DCHPRI22_ECP_MASK (0x80U) #define DMA_DCHPRI22_ECP_SHIFT (7U) -/*! ECP - Enable Channel Preemption. This field resets to - 0. +/*! ECP - Enable Channel Preemption. This field resets to 0. * 0b0..Channel n cannot be suspended by a higher priority channel's service request. * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. */ @@ -13565,16 +13582,14 @@ typedef struct { #define DMA_DCHPRI21_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_GRPPRI_SHIFT)) & DMA_DCHPRI21_GRPPRI_MASK) #define DMA_DCHPRI21_DPA_MASK (0x40U) #define DMA_DCHPRI21_DPA_SHIFT (6U) -/*! DPA - Disable Preempt Ability. This field resets to - 0. +/*! DPA - Disable Preempt Ability. This field resets to 0. * 0b0..Channel n can suspend a lower priority channel. * 0b1..Channel n cannot suspend any channel, regardless of channel priority. */ #define DMA_DCHPRI21_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_DPA_SHIFT)) & DMA_DCHPRI21_DPA_MASK) #define DMA_DCHPRI21_ECP_MASK (0x80U) #define DMA_DCHPRI21_ECP_SHIFT (7U) -/*! ECP - Enable Channel Preemption. This field resets to - 0. +/*! ECP - Enable Channel Preemption. This field resets to 0. * 0b0..Channel n cannot be suspended by a higher priority channel's service request. * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. */ @@ -13591,16 +13606,14 @@ typedef struct { #define DMA_DCHPRI20_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_GRPPRI_SHIFT)) & DMA_DCHPRI20_GRPPRI_MASK) #define DMA_DCHPRI20_DPA_MASK (0x40U) #define DMA_DCHPRI20_DPA_SHIFT (6U) -/*! DPA - Disable Preempt Ability. This field resets to - 0. +/*! DPA - Disable Preempt Ability. This field resets to 0. * 0b0..Channel n can suspend a lower priority channel. * 0b1..Channel n cannot suspend any channel, regardless of channel priority. */ #define DMA_DCHPRI20_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_DPA_SHIFT)) & DMA_DCHPRI20_DPA_MASK) #define DMA_DCHPRI20_ECP_MASK (0x80U) #define DMA_DCHPRI20_ECP_SHIFT (7U) -/*! ECP - Enable Channel Preemption. This field resets to - 0. +/*! ECP - Enable Channel Preemption. This field resets to 0. * 0b0..Channel n cannot be suspended by a higher priority channel's service request. * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. */ @@ -13617,16 +13630,14 @@ typedef struct { #define DMA_DCHPRI27_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_GRPPRI_SHIFT)) & DMA_DCHPRI27_GRPPRI_MASK) #define DMA_DCHPRI27_DPA_MASK (0x40U) #define DMA_DCHPRI27_DPA_SHIFT (6U) -/*! DPA - Disable Preempt Ability. This field resets to - 0. +/*! DPA - Disable Preempt Ability. This field resets to 0. * 0b0..Channel n can suspend a lower priority channel. * 0b1..Channel n cannot suspend any channel, regardless of channel priority. */ #define DMA_DCHPRI27_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_DPA_SHIFT)) & DMA_DCHPRI27_DPA_MASK) #define DMA_DCHPRI27_ECP_MASK (0x80U) #define DMA_DCHPRI27_ECP_SHIFT (7U) -/*! ECP - Enable Channel Preemption. This field resets to - 0. +/*! ECP - Enable Channel Preemption. This field resets to 0. * 0b0..Channel n cannot be suspended by a higher priority channel's service request. * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. */ @@ -13643,16 +13654,14 @@ typedef struct { #define DMA_DCHPRI26_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_GRPPRI_SHIFT)) & DMA_DCHPRI26_GRPPRI_MASK) #define DMA_DCHPRI26_DPA_MASK (0x40U) #define DMA_DCHPRI26_DPA_SHIFT (6U) -/*! DPA - Disable Preempt Ability. This field resets to - 0. +/*! DPA - Disable Preempt Ability. This field resets to 0. * 0b0..Channel n can suspend a lower priority channel. * 0b1..Channel n cannot suspend any channel, regardless of channel priority. */ #define DMA_DCHPRI26_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_DPA_SHIFT)) & DMA_DCHPRI26_DPA_MASK) #define DMA_DCHPRI26_ECP_MASK (0x80U) #define DMA_DCHPRI26_ECP_SHIFT (7U) -/*! ECP - Enable Channel Preemption. This field resets to - 0. +/*! ECP - Enable Channel Preemption. This field resets to 0. * 0b0..Channel n cannot be suspended by a higher priority channel's service request. * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. */ @@ -13669,16 +13678,14 @@ typedef struct { #define DMA_DCHPRI25_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_GRPPRI_SHIFT)) & DMA_DCHPRI25_GRPPRI_MASK) #define DMA_DCHPRI25_DPA_MASK (0x40U) #define DMA_DCHPRI25_DPA_SHIFT (6U) -/*! DPA - Disable Preempt Ability. This field resets to - 0. +/*! DPA - Disable Preempt Ability. This field resets to 0. * 0b0..Channel n can suspend a lower priority channel. * 0b1..Channel n cannot suspend any channel, regardless of channel priority. */ #define DMA_DCHPRI25_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_DPA_SHIFT)) & DMA_DCHPRI25_DPA_MASK) #define DMA_DCHPRI25_ECP_MASK (0x80U) #define DMA_DCHPRI25_ECP_SHIFT (7U) -/*! ECP - Enable Channel Preemption. This field resets to - 0. +/*! ECP - Enable Channel Preemption. This field resets to 0. * 0b0..Channel n cannot be suspended by a higher priority channel's service request. * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. */ @@ -13695,16 +13702,14 @@ typedef struct { #define DMA_DCHPRI24_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_GRPPRI_SHIFT)) & DMA_DCHPRI24_GRPPRI_MASK) #define DMA_DCHPRI24_DPA_MASK (0x40U) #define DMA_DCHPRI24_DPA_SHIFT (6U) -/*! DPA - Disable Preempt Ability. This field resets to - 0. +/*! DPA - Disable Preempt Ability. This field resets to 0. * 0b0..Channel n can suspend a lower priority channel. * 0b1..Channel n cannot suspend any channel, regardless of channel priority. */ #define DMA_DCHPRI24_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_DPA_SHIFT)) & DMA_DCHPRI24_DPA_MASK) #define DMA_DCHPRI24_ECP_MASK (0x80U) #define DMA_DCHPRI24_ECP_SHIFT (7U) -/*! ECP - Enable Channel Preemption. This field resets to - 0. +/*! ECP - Enable Channel Preemption. This field resets to 0. * 0b0..Channel n cannot be suspended by a higher priority channel's service request. * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. */ @@ -13721,16 +13726,14 @@ typedef struct { #define DMA_DCHPRI31_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_GRPPRI_SHIFT)) & DMA_DCHPRI31_GRPPRI_MASK) #define DMA_DCHPRI31_DPA_MASK (0x40U) #define DMA_DCHPRI31_DPA_SHIFT (6U) -/*! DPA - Disable Preempt Ability. This field resets to - 0. +/*! DPA - Disable Preempt Ability. This field resets to 0. * 0b0..Channel n can suspend a lower priority channel. * 0b1..Channel n cannot suspend any channel, regardless of channel priority. */ #define DMA_DCHPRI31_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_DPA_SHIFT)) & DMA_DCHPRI31_DPA_MASK) #define DMA_DCHPRI31_ECP_MASK (0x80U) #define DMA_DCHPRI31_ECP_SHIFT (7U) -/*! ECP - Enable Channel Preemption. This field resets to - 0. +/*! ECP - Enable Channel Preemption. This field resets to 0. * 0b0..Channel n cannot be suspended by a higher priority channel's service request. * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. */ @@ -13747,16 +13750,14 @@ typedef struct { #define DMA_DCHPRI30_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_GRPPRI_SHIFT)) & DMA_DCHPRI30_GRPPRI_MASK) #define DMA_DCHPRI30_DPA_MASK (0x40U) #define DMA_DCHPRI30_DPA_SHIFT (6U) -/*! DPA - Disable Preempt Ability. This field resets to - 0. +/*! DPA - Disable Preempt Ability. This field resets to 0. * 0b0..Channel n can suspend a lower priority channel. * 0b1..Channel n cannot suspend any channel, regardless of channel priority. */ #define DMA_DCHPRI30_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_DPA_SHIFT)) & DMA_DCHPRI30_DPA_MASK) #define DMA_DCHPRI30_ECP_MASK (0x80U) #define DMA_DCHPRI30_ECP_SHIFT (7U) -/*! ECP - Enable Channel Preemption. This field resets to - 0. +/*! ECP - Enable Channel Preemption. This field resets to 0. * 0b0..Channel n cannot be suspended by a higher priority channel's service request. * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. */ @@ -13773,16 +13774,14 @@ typedef struct { #define DMA_DCHPRI29_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_GRPPRI_SHIFT)) & DMA_DCHPRI29_GRPPRI_MASK) #define DMA_DCHPRI29_DPA_MASK (0x40U) #define DMA_DCHPRI29_DPA_SHIFT (6U) -/*! DPA - Disable Preempt Ability. This field resets to - 0. +/*! DPA - Disable Preempt Ability. This field resets to 0. * 0b0..Channel n can suspend a lower priority channel. * 0b1..Channel n cannot suspend any channel, regardless of channel priority. */ #define DMA_DCHPRI29_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_DPA_SHIFT)) & DMA_DCHPRI29_DPA_MASK) #define DMA_DCHPRI29_ECP_MASK (0x80U) #define DMA_DCHPRI29_ECP_SHIFT (7U) -/*! ECP - Enable Channel Preemption. This field resets to - 0. +/*! ECP - Enable Channel Preemption. This field resets to 0. * 0b0..Channel n cannot be suspended by a higher priority channel's service request. * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. */ @@ -13799,16 +13798,14 @@ typedef struct { #define DMA_DCHPRI28_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_GRPPRI_SHIFT)) & DMA_DCHPRI28_GRPPRI_MASK) #define DMA_DCHPRI28_DPA_MASK (0x40U) #define DMA_DCHPRI28_DPA_SHIFT (6U) -/*! DPA - Disable Preempt Ability. This field resets to - 0. +/*! DPA - Disable Preempt Ability. This field resets to 0. * 0b0..Channel n can suspend a lower priority channel. * 0b1..Channel n cannot suspend any channel, regardless of channel priority. */ #define DMA_DCHPRI28_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_DPA_SHIFT)) & DMA_DCHPRI28_DPA_MASK) #define DMA_DCHPRI28_ECP_MASK (0x80U) #define DMA_DCHPRI28_ECP_SHIFT (7U) -/*! ECP - Enable Channel Preemption. This field resets to - 0. +/*! ECP - Enable Channel Preemption. This field resets to 0. * 0b0..Channel n cannot be suspended by a higher priority channel's service request. * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. */ @@ -13849,6 +13846,9 @@ typedef struct { * 0b000..8-bit * 0b001..16-bit * 0b010..32-bit + * 0b011..64-bit + * 0b100..Reserved + * 0b101..32-byte burst (4 beats of 64 bits) * 0b110..Reserved * 0b111..Reserved */ @@ -13963,8 +13963,7 @@ typedef struct { #define DMA_CITER_ELINKNO_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKNO_CITER_SHIFT)) & DMA_CITER_ELINKNO_CITER_MASK) #define DMA_CITER_ELINKNO_ELINK_MASK (0x8000U) #define DMA_CITER_ELINKNO_ELINK_SHIFT (15U) -/*! ELINK - Enable channel-to-channel linking on minor-loop - complete +/*! ELINK - Enable channel-to-channel linking on minor-loop complete * 0b0..The channel-to-channel linking is disabled * 0b1..The channel-to-channel linking is enabled */ @@ -13984,8 +13983,7 @@ typedef struct { #define DMA_CITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_LINKCH_SHIFT)) & DMA_CITER_ELINKYES_LINKCH_MASK) #define DMA_CITER_ELINKYES_ELINK_MASK (0x8000U) #define DMA_CITER_ELINKYES_ELINK_SHIFT (15U) -/*! ELINK - Enable channel-to-channel linking on minor-loop - complete +/*! ELINK - Enable channel-to-channel linking on minor-loop complete * 0b0..The channel-to-channel linking is disabled * 0b1..The channel-to-channel linking is enabled */ @@ -14016,22 +14014,24 @@ typedef struct { #define DMA_CSR_START(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_START_SHIFT)) & DMA_CSR_START_MASK) #define DMA_CSR_INTMAJOR_MASK (0x2U) #define DMA_CSR_INTMAJOR_SHIFT (1U) -/*! INTMAJOR - Enable an interrupt when major iteration count - completes. +/*! INTMAJOR - Enable an interrupt when major iteration count completes. * 0b0..The end-of-major loop interrupt is disabled. * 0b1..The end-of-major loop interrupt is enabled. */ #define DMA_CSR_INTMAJOR(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_INTMAJOR_SHIFT)) & DMA_CSR_INTMAJOR_MASK) #define DMA_CSR_INTHALF_MASK (0x4U) #define DMA_CSR_INTHALF_SHIFT (2U) -/*! INTHALF - Enable an interrupt when major counter is half - complete. +/*! INTHALF - Enable an interrupt when major counter is half complete. * 0b0..The half-point interrupt is disabled. * 0b1..The half-point interrupt is enabled. */ #define DMA_CSR_INTHALF(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_INTHALF_SHIFT)) & DMA_CSR_INTHALF_MASK) #define DMA_CSR_DREQ_MASK (0x8U) #define DMA_CSR_DREQ_SHIFT (3U) +/*! DREQ - Disable Request + * 0b0..The channel's ERQ bit is not affected. + * 0b1..The channel's ERQ bit is cleared when the major loop is complete. + */ #define DMA_CSR_DREQ(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_DREQ_SHIFT)) & DMA_CSR_DREQ_MASK) #define DMA_CSR_ESG_MASK (0x10U) #define DMA_CSR_ESG_SHIFT (4U) @@ -14042,8 +14042,7 @@ typedef struct { #define DMA_CSR_ESG(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_ESG_SHIFT)) & DMA_CSR_ESG_MASK) #define DMA_CSR_MAJORELINK_MASK (0x20U) #define DMA_CSR_MAJORELINK_SHIFT (5U) -/*! MAJORELINK - Enable channel-to-channel linking on major loop - complete +/*! MAJORELINK - Enable channel-to-channel linking on major loop complete * 0b0..The channel-to-channel linking is disabled. * 0b1..The channel-to-channel linking is enabled. */ @@ -14078,8 +14077,7 @@ typedef struct { #define DMA_BITER_ELINKNO_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKNO_BITER_SHIFT)) & DMA_BITER_ELINKNO_BITER_MASK) #define DMA_BITER_ELINKNO_ELINK_MASK (0x8000U) #define DMA_BITER_ELINKNO_ELINK_SHIFT (15U) -/*! ELINK - Enables channel-to-channel linking on minor loop - complete +/*! ELINK - Enables channel-to-channel linking on minor loop complete * 0b0..The channel-to-channel linking is disabled * 0b1..The channel-to-channel linking is enabled */ @@ -14099,8 +14097,7 @@ typedef struct { #define DMA_BITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_LINKCH_SHIFT)) & DMA_BITER_ELINKYES_LINKCH_MASK) #define DMA_BITER_ELINKYES_ELINK_MASK (0x8000U) #define DMA_BITER_ELINKYES_ELINK_SHIFT (15U) -/*! ELINK - Enables channel-to-channel linking on minor loop - complete +/*! ELINK - Enables channel-to-channel linking on minor loop complete * 0b0..The channel-to-channel linking is disabled * 0b1..The channel-to-channel linking is enabled */ @@ -14164,9 +14161,7 @@ typedef struct { #define DMAMUX_CHCFG_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << DMAMUX_CHCFG_SOURCE_SHIFT)) & DMAMUX_CHCFG_SOURCE_MASK) #define DMAMUX_CHCFG_A_ON_MASK (0x20000000U) #define DMAMUX_CHCFG_A_ON_SHIFT (29U) -/*! A_ON - - DMA Channel Always Enable - +/*! A_ON - DMA Channel Always Enable * 0b0..DMA Channel Always ON function is disabled * 0b1..DMA Channel Always ON function is enabled */ @@ -14180,9 +14175,7 @@ typedef struct { #define DMAMUX_CHCFG_TRIG(x) (((uint32_t)(((uint32_t)(x)) << DMAMUX_CHCFG_TRIG_SHIFT)) & DMAMUX_CHCFG_TRIG_MASK) #define DMAMUX_CHCFG_ENBL_MASK (0x80000000U) #define DMAMUX_CHCFG_ENBL_SHIFT (31U) -/*! ENBL - - DMA Mux Channel Enable - +/*! ENBL - DMA Mux Channel Enable * 0b0..DMA Mux channel is disabled * 0b1..DMA Mux channel is enabled */ @@ -16379,6 +16372,8 @@ typedef struct { * 0b011..Reserved. * 0b100..Match Store mode. Shifter data is compared to SHIFTBUF content on expiration of the Timer. * 0b101..Match Continuous mode. Shifter data is continuously compared to SHIFTBUF contents. + * 0b110..State mode. SHIFTBUF contents are used for storing programmable state attributes. + * 0b111..Logic mode. SHIFTBUF contents are used for implementing programmable logic look up table. */ #define FLEXIO_SHIFTCTL_SMOD(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_SMOD_SHIFT)) & FLEXIO_SHIFTCTL_SMOD_MASK) #define FLEXIO_SHIFTCTL_PINPOL_MASK (0x80U) @@ -16705,9 +16700,7 @@ typedef struct { /** FLEXRAM - Register Layout Typedef */ typedef struct { __IO uint32_t TCM_CTRL; /**< TCM CRTL Register, offset: 0x0 */ - __IO uint32_t OCRAM_MAGIC_ADDR; /**< OCRAM Magic Address Register, offset: 0x4 */ - __IO uint32_t DTCM_MAGIC_ADDR; /**< DTCM Magic Address Register, offset: 0x8 */ - __IO uint32_t ITCM_MAGIC_ADDR; /**< ITCM Magic Address Register, offset: 0xC */ + uint8_t RESERVED_0[12]; __IO uint32_t INT_STATUS; /**< Interrupt Status Register, offset: 0x10 */ __IO uint32_t INT_STAT_EN; /**< Interrupt Status Enable Register, offset: 0x14 */ __IO uint32_t INT_SIG_EN; /**< Interrupt Enable Register, offset: 0x18 */ @@ -16741,85 +16734,10 @@ typedef struct { #define FLEXRAM_TCM_CTRL_FORCE_CLK_ON_MASK (0x4U) #define FLEXRAM_TCM_CTRL_FORCE_CLK_ON_SHIFT (2U) #define FLEXRAM_TCM_CTRL_FORCE_CLK_ON(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_TCM_CTRL_FORCE_CLK_ON_SHIFT)) & FLEXRAM_TCM_CTRL_FORCE_CLK_ON_MASK) -#define FLEXRAM_TCM_CTRL_Reserved_MASK (0xFFFFFFF8U) -#define FLEXRAM_TCM_CTRL_Reserved_SHIFT (3U) -#define FLEXRAM_TCM_CTRL_Reserved(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_TCM_CTRL_Reserved_SHIFT)) & FLEXRAM_TCM_CTRL_Reserved_MASK) -/*! @} */ - -/*! @name OCRAM_MAGIC_ADDR - OCRAM Magic Address Register */ -/*! @{ */ -#define FLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_WR_RD_SEL_MASK (0x1U) -#define FLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_WR_RD_SEL_SHIFT (0U) -/*! OCRAM_WR_RD_SEL - OCRAM Write Read Select - * 0b0..When OCRAM read access hits magic address, it will generate interrupt. - * 0b1..When OCRAM write access hits magic address, it will generate interrupt. - */ -#define FLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_WR_RD_SEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_WR_RD_SEL_SHIFT)) & FLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_WR_RD_SEL_MASK) -#define FLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_MAGIC_ADDR_MASK (0x1FFFEU) -#define FLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_MAGIC_ADDR_SHIFT (1U) -#define FLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_MAGIC_ADDR(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_MAGIC_ADDR_SHIFT)) & FLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_MAGIC_ADDR_MASK) -#define FLEXRAM_OCRAM_MAGIC_ADDR_Reserved_MASK (0xFFFE0000U) -#define FLEXRAM_OCRAM_MAGIC_ADDR_Reserved_SHIFT (17U) -#define FLEXRAM_OCRAM_MAGIC_ADDR_Reserved(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_OCRAM_MAGIC_ADDR_Reserved_SHIFT)) & FLEXRAM_OCRAM_MAGIC_ADDR_Reserved_MASK) -/*! @} */ - -/*! @name DTCM_MAGIC_ADDR - DTCM Magic Address Register */ -/*! @{ */ -#define FLEXRAM_DTCM_MAGIC_ADDR_DTCM_WR_RD_SEL_MASK (0x1U) -#define FLEXRAM_DTCM_MAGIC_ADDR_DTCM_WR_RD_SEL_SHIFT (0U) -/*! DTCM_WR_RD_SEL - DTCM Write Read Select - * 0b0..When DTCM read access hits magic address, it will generate interrupt. - * 0b1..When DTCM write access hits magic address, it will generate interrupt. - */ -#define FLEXRAM_DTCM_MAGIC_ADDR_DTCM_WR_RD_SEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_DTCM_MAGIC_ADDR_DTCM_WR_RD_SEL_SHIFT)) & FLEXRAM_DTCM_MAGIC_ADDR_DTCM_WR_RD_SEL_MASK) -#define FLEXRAM_DTCM_MAGIC_ADDR_DTCM_MAGIC_ADDR_MASK (0x1FFFEU) -#define FLEXRAM_DTCM_MAGIC_ADDR_DTCM_MAGIC_ADDR_SHIFT (1U) -#define FLEXRAM_DTCM_MAGIC_ADDR_DTCM_MAGIC_ADDR(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_DTCM_MAGIC_ADDR_DTCM_MAGIC_ADDR_SHIFT)) & FLEXRAM_DTCM_MAGIC_ADDR_DTCM_MAGIC_ADDR_MASK) -#define FLEXRAM_DTCM_MAGIC_ADDR_Reserved_MASK (0xFFFE0000U) -#define FLEXRAM_DTCM_MAGIC_ADDR_Reserved_SHIFT (17U) -#define FLEXRAM_DTCM_MAGIC_ADDR_Reserved(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_DTCM_MAGIC_ADDR_Reserved_SHIFT)) & FLEXRAM_DTCM_MAGIC_ADDR_Reserved_MASK) -/*! @} */ - -/*! @name ITCM_MAGIC_ADDR - ITCM Magic Address Register */ -/*! @{ */ -#define FLEXRAM_ITCM_MAGIC_ADDR_ITCM_WR_RD_SEL_MASK (0x1U) -#define FLEXRAM_ITCM_MAGIC_ADDR_ITCM_WR_RD_SEL_SHIFT (0U) -/*! ITCM_WR_RD_SEL - ITCM Write Read Select - * 0b0..When ITCM read access hits magic address, it will generate interrupt. - * 0b1..When ITCM write access hits magic address, it will generate interrupt. - */ -#define FLEXRAM_ITCM_MAGIC_ADDR_ITCM_WR_RD_SEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_ITCM_MAGIC_ADDR_ITCM_WR_RD_SEL_SHIFT)) & FLEXRAM_ITCM_MAGIC_ADDR_ITCM_WR_RD_SEL_MASK) -#define FLEXRAM_ITCM_MAGIC_ADDR_ITCM_MAGIC_ADDR_MASK (0x1FFFEU) -#define FLEXRAM_ITCM_MAGIC_ADDR_ITCM_MAGIC_ADDR_SHIFT (1U) -#define FLEXRAM_ITCM_MAGIC_ADDR_ITCM_MAGIC_ADDR(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_ITCM_MAGIC_ADDR_ITCM_MAGIC_ADDR_SHIFT)) & FLEXRAM_ITCM_MAGIC_ADDR_ITCM_MAGIC_ADDR_MASK) -#define FLEXRAM_ITCM_MAGIC_ADDR_Reserved_MASK (0xFFFE0000U) -#define FLEXRAM_ITCM_MAGIC_ADDR_Reserved_SHIFT (17U) -#define FLEXRAM_ITCM_MAGIC_ADDR_Reserved(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_ITCM_MAGIC_ADDR_Reserved_SHIFT)) & FLEXRAM_ITCM_MAGIC_ADDR_Reserved_MASK) /*! @} */ /*! @name INT_STATUS - Interrupt Status Register */ /*! @{ */ -#define FLEXRAM_INT_STATUS_ITCM_MAM_STATUS_MASK (0x1U) -#define FLEXRAM_INT_STATUS_ITCM_MAM_STATUS_SHIFT (0U) -/*! ITCM_MAM_STATUS - ITCM Magic Address Match Status - * 0b0..ITCM did not access magic address. - * 0b1..ITCM accessed magic address. - */ -#define FLEXRAM_INT_STATUS_ITCM_MAM_STATUS(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_ITCM_MAM_STATUS_SHIFT)) & FLEXRAM_INT_STATUS_ITCM_MAM_STATUS_MASK) -#define FLEXRAM_INT_STATUS_DTCM_MAM_STATUS_MASK (0x2U) -#define FLEXRAM_INT_STATUS_DTCM_MAM_STATUS_SHIFT (1U) -/*! DTCM_MAM_STATUS - DTCM Magic Address Match Status - * 0b0..DTCM did not access magic address. - * 0b1..DTCM accessed magic address. - */ -#define FLEXRAM_INT_STATUS_DTCM_MAM_STATUS(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_DTCM_MAM_STATUS_SHIFT)) & FLEXRAM_INT_STATUS_DTCM_MAM_STATUS_MASK) -#define FLEXRAM_INT_STATUS_OCRAM_MAM_STATUS_MASK (0x4U) -#define FLEXRAM_INT_STATUS_OCRAM_MAM_STATUS_SHIFT (2U) -/*! OCRAM_MAM_STATUS - OCRAM Magic Address Match Status - * 0b0..OCRAM did not access magic address. - * 0b1..OCRAM accessed magic address. - */ -#define FLEXRAM_INT_STATUS_OCRAM_MAM_STATUS(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_OCRAM_MAM_STATUS_SHIFT)) & FLEXRAM_INT_STATUS_OCRAM_MAM_STATUS_MASK) #define FLEXRAM_INT_STATUS_ITCM_ERR_STATUS_MASK (0x8U) #define FLEXRAM_INT_STATUS_ITCM_ERR_STATUS_SHIFT (3U) /*! ITCM_ERR_STATUS - ITCM Access Error Status @@ -16841,34 +16759,10 @@ typedef struct { * 0b1..OCRAM access error happens. */ #define FLEXRAM_INT_STATUS_OCRAM_ERR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_OCRAM_ERR_STATUS_SHIFT)) & FLEXRAM_INT_STATUS_OCRAM_ERR_STATUS_MASK) -#define FLEXRAM_INT_STATUS_Reserved_MASK (0xFFFFFFC0U) -#define FLEXRAM_INT_STATUS_Reserved_SHIFT (6U) -#define FLEXRAM_INT_STATUS_Reserved(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_Reserved_SHIFT)) & FLEXRAM_INT_STATUS_Reserved_MASK) /*! @} */ /*! @name INT_STAT_EN - Interrupt Status Enable Register */ /*! @{ */ -#define FLEXRAM_INT_STAT_EN_ITCM_MAM_STAT_EN_MASK (0x1U) -#define FLEXRAM_INT_STAT_EN_ITCM_MAM_STAT_EN_SHIFT (0U) -/*! ITCM_MAM_STAT_EN - ITCM Magic Address Match Status Enable - * 0b0..Masked - * 0b1..Enabled - */ -#define FLEXRAM_INT_STAT_EN_ITCM_MAM_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_ITCM_MAM_STAT_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_ITCM_MAM_STAT_EN_MASK) -#define FLEXRAM_INT_STAT_EN_DTCM_MAM_STAT_EN_MASK (0x2U) -#define FLEXRAM_INT_STAT_EN_DTCM_MAM_STAT_EN_SHIFT (1U) -/*! DTCM_MAM_STAT_EN - DTCM Magic Address Match Status Enable - * 0b0..Masked - * 0b1..Enabled - */ -#define FLEXRAM_INT_STAT_EN_DTCM_MAM_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_DTCM_MAM_STAT_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_DTCM_MAM_STAT_EN_MASK) -#define FLEXRAM_INT_STAT_EN_OCRAM_MAM_STAT_EN_MASK (0x4U) -#define FLEXRAM_INT_STAT_EN_OCRAM_MAM_STAT_EN_SHIFT (2U) -/*! OCRAM_MAM_STAT_EN - OCRAM Magic Address Match Status Enable - * 0b0..Masked - * 0b1..Enabled - */ -#define FLEXRAM_INT_STAT_EN_OCRAM_MAM_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_OCRAM_MAM_STAT_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_OCRAM_MAM_STAT_EN_MASK) #define FLEXRAM_INT_STAT_EN_ITCM_ERR_STAT_EN_MASK (0x8U) #define FLEXRAM_INT_STAT_EN_ITCM_ERR_STAT_EN_SHIFT (3U) /*! ITCM_ERR_STAT_EN - ITCM Access Error Status Enable @@ -16890,34 +16784,10 @@ typedef struct { * 0b1..Enabled */ #define FLEXRAM_INT_STAT_EN_OCRAM_ERR_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_OCRAM_ERR_STAT_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_OCRAM_ERR_STAT_EN_MASK) -#define FLEXRAM_INT_STAT_EN_Reserved_MASK (0xFFFFFFC0U) -#define FLEXRAM_INT_STAT_EN_Reserved_SHIFT (6U) -#define FLEXRAM_INT_STAT_EN_Reserved(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_Reserved_SHIFT)) & FLEXRAM_INT_STAT_EN_Reserved_MASK) /*! @} */ /*! @name INT_SIG_EN - Interrupt Enable Register */ /*! @{ */ -#define FLEXRAM_INT_SIG_EN_ITCM_MAM_SIG_EN_MASK (0x1U) -#define FLEXRAM_INT_SIG_EN_ITCM_MAM_SIG_EN_SHIFT (0U) -/*! ITCM_MAM_SIG_EN - ITCM Magic Address Match Interrupt Enable - * 0b0..Masked - * 0b1..Enabled - */ -#define FLEXRAM_INT_SIG_EN_ITCM_MAM_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_ITCM_MAM_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_ITCM_MAM_SIG_EN_MASK) -#define FLEXRAM_INT_SIG_EN_DTCM_MAM_SIG_EN_MASK (0x2U) -#define FLEXRAM_INT_SIG_EN_DTCM_MAM_SIG_EN_SHIFT (1U) -/*! DTCM_MAM_SIG_EN - DTCM Magic Address Match Interrupt Enable - * 0b0..Masked - * 0b1..Enabled - */ -#define FLEXRAM_INT_SIG_EN_DTCM_MAM_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_DTCM_MAM_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_DTCM_MAM_SIG_EN_MASK) -#define FLEXRAM_INT_SIG_EN_OCRAM_MAM_SIG_EN_MASK (0x4U) -#define FLEXRAM_INT_SIG_EN_OCRAM_MAM_SIG_EN_SHIFT (2U) -/*! OCRAM_MAM_SIG_EN - OCRAM Magic Address Match Interrupt Enable - * 0b0..Masked - * 0b1..Enabled - */ -#define FLEXRAM_INT_SIG_EN_OCRAM_MAM_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_OCRAM_MAM_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_OCRAM_MAM_SIG_EN_MASK) #define FLEXRAM_INT_SIG_EN_ITCM_ERR_SIG_EN_MASK (0x8U) #define FLEXRAM_INT_SIG_EN_ITCM_ERR_SIG_EN_SHIFT (3U) /*! ITCM_ERR_SIG_EN - ITCM Access Error Interrupt Enable @@ -16939,9 +16809,6 @@ typedef struct { * 0b1..Enabled */ #define FLEXRAM_INT_SIG_EN_OCRAM_ERR_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_OCRAM_ERR_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_OCRAM_ERR_SIG_EN_MASK) -#define FLEXRAM_INT_SIG_EN_Reserved_MASK (0xFFFFFFC0U) -#define FLEXRAM_INT_SIG_EN_Reserved_SHIFT (6U) -#define FLEXRAM_INT_SIG_EN_Reserved(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_Reserved_SHIFT)) & FLEXRAM_INT_SIG_EN_Reserved_MASK) /*! @} */ @@ -17035,7 +16902,6 @@ typedef struct { #define FLEXSPI_MCR0_RXCLKSRC_MASK (0x30U) #define FLEXSPI_MCR0_RXCLKSRC_SHIFT (4U) /*! RXCLKSRC - Sample Clock source selection for Flash Reading - * 0b00..Dummy Read strobe generated by FlexSPI Controller and loopback internally. * 0b01..Dummy Read strobe generated by FlexSPI Controller and loopback from DQS pad. * 0b10..Reserved @@ -17079,10 +16945,7 @@ typedef struct { #define FLEXSPI_MCR0_COMBINATIONEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_COMBINATIONEN_SHIFT)) & FLEXSPI_MCR0_COMBINATIONEN_MASK) #define FLEXSPI_MCR0_SCKFREERUNEN_MASK (0x4000U) #define FLEXSPI_MCR0_SCKFREERUNEN_SHIFT (14U) -/*! SCKFREERUNEN - This bit is used to force SCK output free-running. For FPGA applications, external device may use SCK clock - as reference clock to its internal PLL. If SCK free-running is enabled, data sampling with loopback clock from SCK pad is not supported (MCR0[RXCLKSRC]=2). - - +/*! SCKFREERUNEN - This bit is used to force SCK output free-running. For FPGA applications, external device may use SCK clock as reference clock to its internal PLL. If SCK free-running is enabled, data sampling with loopback clock from SCK pad is not supported (MCR0[RXCLKSRC]=2). * 0b0..Disable. * 0b1..Enable. */ @@ -17126,8 +16989,7 @@ typedef struct { #define FLEXSPI_MCR2_SAMEDEVICEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_SAMEDEVICEEN_SHIFT)) & FLEXSPI_MCR2_SAMEDEVICEEN_MASK) #define FLEXSPI_MCR2_SCKBDIFFOPT_MASK (0x80000U) #define FLEXSPI_MCR2_SCKBDIFFOPT_SHIFT (19U) -/*! SCKBDIFFOPT - SCKB pad can be used as SCKA differential clock output (inverted clock to SCKA). In this case, port B flash access is not available. - After change the value of this feild, MCR0[SWRESET] should be set. +/*! SCKBDIFFOPT - SCKB pad can be used as SCKA differential clock output (inverted clock to SCKA). In this case, port B flash access is not available. After change the value of this feild, MCR0[SWRESET] should be set. * 0b1..SCKB pad is used as port A SCK inverted clock output (Differential clock to SCKA). Port B flash access is not available. * 0b0..SCKB pad is used as port B SCK clock output. Port B flash access is available. */ @@ -17155,7 +17017,7 @@ typedef struct { #define FLEXSPI_AHBCR_CACHABLEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_CACHABLEEN_SHIFT)) & FLEXSPI_AHBCR_CACHABLEEN_MASK) #define FLEXSPI_AHBCR_BUFFERABLEEN_MASK (0x10U) #define FLEXSPI_AHBCR_BUFFERABLEEN_SHIFT (4U) -/*! BUFFERABLEEN - Enable AHB bus bufferable write access support. This field affects the last beat of AHB write access, refer for more details about AHB bufferable write. +/*! BUFFERABLEEN - Enable AHB bus bufferable write access support. This field affects the last beat of AHB write access, refer for more details about AHB bufferable write. * 0b0..Disabled. For all AHB write access (no matter bufferable or non-bufferable ), FlexSPI will return AHB Bus ready after all data is transmitted to External device and AHB command finished. * 0b1..Enabled. For AHB bufferable write access, FlexSPI will return AHB Bus ready when the AHB command is granted by arbitrator and will not wait for AHB command finished. */ @@ -17484,9 +17346,7 @@ typedef struct { #define FLEXSPI_STS0_ARBIDLE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS0_ARBIDLE_SHIFT)) & FLEXSPI_STS0_ARBIDLE_MASK) #define FLEXSPI_STS0_ARBCMDSRC_MASK (0xCU) #define FLEXSPI_STS0_ARBCMDSRC_SHIFT (2U) -/*! ARBCMDSRC - This status field indicates the trigger source of current command sequence granted by arbitrator. - This field value is meaningless when ARB_CTL is not busy (STS0[ARBIDLE]=0x1). - +/*! ARBCMDSRC - This status field indicates the trigger source of current command sequence granted by arbitrator. This field value is meaningless when ARB_CTL is not busy (STS0[ARBIDLE]=0x1). * 0b00..Triggered by AHB read command (triggered by AHB read). * 0b01..Triggered by AHB write command (triggered by AHB Write). * 0b10..Triggered by IP command (triggered by setting register bit IPCMD.TRG). @@ -17503,7 +17363,6 @@ typedef struct { #define FLEXSPI_STS1_AHBCMDERRCODE_MASK (0xF00U) #define FLEXSPI_STS1_AHBCMDERRCODE_SHIFT (8U) /*! AHBCMDERRCODE - Indicates the Error Code when AHB command Error detected. This field will be cleared when INTR[AHBCMDERR] is write-1-clear(w1c). - * 0b0000..No error. * 0b0010..AHB Write command with JMP_ON_CS instruction used in the sequence. * 0b0011..There is unknown instruction opcode in the sequence. @@ -19352,19 +19211,22 @@ typedef struct { #define IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_MASK (0xFU) /* Merged from fields with different position or width, of widths (3, 4), largest definition used */ #define IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_SHIFT (0U) /*! MUX_MODE - MUX Mode Select Field. - * 0b0000..Select mux mode: ALT0 mux port: SEMC_ADDR00 of instance: semc - * 0b0001..Select mux mode: ALT1 mux port: FLEXPWM2_PWMB01 of instance: flexpwm2 - * 0b0010..Select mux mode: ALT2 mux port: SAI2_RX_SYNC of instance: sai2 - * 0b0011..Select mux mode: ALT3 mux port: FLEXCAN2_TX of instance: flexcan2 - * 0b0100..Select mux mode: ALT4 mux port: FLEXIO1_FLEXIO09 of instance: flexio1 - * 0b0101..Select mux mode: ALT5 mux port: GPIO4_IO09 of instance: gpio4 - * 0b1000..Select mux mode: ALT8 mux port: FLEXSPI2_B_SS1_B of instance: flexspi2 + * 0b0000..Select mux mode: ALT0 mux port: USB_OTG1_PWR of instance: usb + * 0b0001..Select mux mode: ALT1 mux port: QTIMER3_TIMER1 of instance: qtimer3 + * 0b0010..Select mux mode: ALT2 mux port: LPUART2_RTS_B of instance: lpuart2 + * 0b0011..Select mux mode: ALT3 mux port: LPI2C1_SDA of instance: lpi2c1 + * 0b0100..Select mux mode: ALT4 mux port: CCM_PMIC_READY of instance: ccm + * 0b0101..Select mux mode: ALT5 mux port: GPIO1_IO17 of instance: gpio1 + * 0b0110..Select mux mode: ALT6 mux port: USDHC1_VSELECT of instance: usdhc1 + * 0b0111..Select mux mode: ALT7 mux port: KPP_COL07 of instance: kpp + * 0b1000..Select mux mode: ALT8 mux port: ENET2_1588_EVENT0_IN of instance: enet2 + * 0b1001..Select mux mode: ALT9 mux port: FLEXIO3_FLEXIO01 of instance: flexio3 */ #define IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_SHIFT)) & IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_MASK) /* Merged from fields with different position or width, of widths (3, 4), largest definition used */ #define IOMUXC_SW_MUX_CTL_PAD_SION_MASK (0x10U) #define IOMUXC_SW_MUX_CTL_PAD_SION_SHIFT (4U) /*! SION - Software Input On Field. - * 0b1..Force input path of pad GPIO_EMC_00 + * 0b1..Force input path of pad GPIO_SD_B1_11 * 0b0..Input Path is determined by functionality */ #define IOMUXC_SW_MUX_CTL_PAD_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_MUX_CTL_PAD_SION_SHIFT)) & IOMUXC_SW_MUX_CTL_PAD_SION_MASK) @@ -19468,13 +19330,13 @@ typedef struct { #define IOMUXC_SW_MUX_CTL_PAD_1_MUX_MODE_MASK (0x7U) #define IOMUXC_SW_MUX_CTL_PAD_1_MUX_MODE_SHIFT (0U) /*! MUX_MODE - MUX Mode Select Field. - * 0b000..Select mux mode: ALT0 mux port: FLEXSPI2_B_SCLK of instance: flexspi2 + * 0b000..Select mux mode: ALT0 mux port: FLEXSPI2_B_DATA03 of instance: flexspi2 */ #define IOMUXC_SW_MUX_CTL_PAD_1_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_MUX_CTL_PAD_1_MUX_MODE_SHIFT)) & IOMUXC_SW_MUX_CTL_PAD_1_MUX_MODE_MASK) #define IOMUXC_SW_MUX_CTL_PAD_1_SION_MASK (0x10U) #define IOMUXC_SW_MUX_CTL_PAD_1_SION_SHIFT (4U) /*! SION - Software Input On Field. - * 0b1..Force input path of pad GPIO_SPI_B0_00 + * 0b1..Force input path of pad GPIO_SPI_B1_07 * 0b0..Input Path is determined by functionality */ #define IOMUXC_SW_MUX_CTL_PAD_1_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_MUX_CTL_PAD_1_SION_SHIFT)) & IOMUXC_SW_MUX_CTL_PAD_1_SION_MASK) @@ -19561,9 +19423,10 @@ typedef struct { #define IOMUXC_SELECT_INPUT_1_DAISY_MASK (0x3U) /* Merged from fields with different position or width, of widths (1, 2), largest definition used */ #define IOMUXC_SELECT_INPUT_1_DAISY_SHIFT (0U) /*! DAISY - Selecting Pads Involved in Daisy Chain. - * 0b00..Selecting Pad: GPIO_EMC_33 for Mode: ALT9 - * 0b01..Selecting Pad: GPIO_SD_B0_01 for Mode: ALT9 - * 0b10..Selecting Pad: GPIO_B0_15 for Mode: ALT9 + * 0b00..Selecting Pad: GPIO_SD_B0_00 for Mode: ALT9 + * 0b01..Selecting Pad: GPIO_EMC_39 for Mode: ALT9 + * 0b10..Selecting Pad: GPIO_AD_B0_09 for Mode: ALT9 + * 0b11..Selecting Pad: GPIO_B1_13 for Mode: ALT8 */ #define IOMUXC_SELECT_INPUT_1_DAISY(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SELECT_INPUT_1_DAISY_SHIFT)) & IOMUXC_SELECT_INPUT_1_DAISY_MASK) /* Merged from fields with different position or width, of widths (1, 2), largest definition used */ /*! @} */ @@ -21296,9 +21159,6 @@ typedef struct { * 0b1..use FLEXRAM_BANK_CFG to config */ #define IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL_SHIFT)) & IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL_MASK) -#define IOMUXC_GPR_GPR16_CM7_INIT_VTOR_MASK (0xFFFFFF80U) -#define IOMUXC_GPR_GPR16_CM7_INIT_VTOR_SHIFT (7U) -#define IOMUXC_GPR_GPR16_CM7_INIT_VTOR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR16_CM7_INIT_VTOR_SHIFT)) & IOMUXC_GPR_GPR16_CM7_INIT_VTOR_MASK) /*! @} */ /*! @name GPR17 - GPR17 General Purpose Register */ @@ -25509,6 +25369,7 @@ typedef struct { * 0b00..Address Match Wakeup * 0b01..Idle Match Wakeup * 0b10..Match On and Match Off + * 0b11..Enables RWU on Data Match and Match On/Off for transmitter CTS input */ #define LPUART_BAUD_MATCFG(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MATCFG_SHIFT)) & LPUART_BAUD_MATCFG_MASK) #define LPUART_BAUD_RIDMAE_MASK (0x100000U) @@ -26026,6 +25887,7 @@ typedef struct { #define LPUART_MODIR_RXRTSE_SHIFT (3U) /*! RXRTSE - Receiver request-to-send enable * 0b0..The receiver has no effect on RTS. + * 0b1..RTS is deasserted if the receiver data register is full or a start bit has been detected that would cause the receiver data register to become full. RTS is asserted if the receiver data register is not full and has not detected a start bit that would cause the receiver data register to become full. */ #define LPUART_MODIR_RXRTSE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_RXRTSE_SHIFT)) & LPUART_MODIR_RXRTSE_MASK) #define LPUART_MODIR_TXCTSC_MASK (0x10U) @@ -26306,11 +26168,11 @@ typedef struct { uint8_t RESERVED_20[12]; __IO uint32_t MEM4; /**< Value of OTP Bank1 Word4 (Memory Related Info.), offset: 0x4C0 */ uint8_t RESERVED_21[12]; - __IO uint32_t ANA0; /**< Value of OTP Bank1 Word5 (Analog Info.), offset: 0x4D0 */ + __IO uint32_t ANA0; /**< Value of OTP Bank1 Word5 (Memory Related Info.), offset: 0x4D0 */ uint8_t RESERVED_22[12]; - __IO uint32_t ANA1; /**< Value of OTP Bank1 Word6 (Analog Info.), offset: 0x4E0 */ + __IO uint32_t ANA1; /**< Value of OTP Bank1 Word6 (General Purpose Customer Defined Info.), offset: 0x4E0 */ uint8_t RESERVED_23[12]; - __IO uint32_t ANA2; /**< Value of OTP Bank1 Word7 (Analog Info.), offset: 0x4F0 */ + __IO uint32_t ANA2; /**< Value of OTP Bank1 Word7 (General Purpose Customer Defined Info.), offset: 0x4F0 */ uint8_t RESERVED_24[12]; __IO uint32_t OTPMK0; /**< Value of OTP Bank2 Word0 (OTPMK Key), offset: 0x500 */ uint8_t RESERVED_25[12]; @@ -26352,7 +26214,7 @@ typedef struct { uint8_t RESERVED_43[12]; __IO uint32_t MAC1; /**< Value of OTP Bank4 Word3 (MAC Address), offset: 0x630 */ uint8_t RESERVED_44[12]; - __IO uint32_t MAC2; /**< Value of OTP Bank4 Word4 (MAC Address), offset: 0x640 */ + __IO uint32_t MAC2; /**< Value of OTP Bank4 Word4 (MAC2 Address), offset: 0x640 */ uint8_t RESERVED_45[12]; __IO uint32_t OTPMK_CRC32; /**< Value of OTP Bank4 Word5 (CRC Key), offset: 0x650 */ uint8_t RESERVED_46[12]; @@ -26743,9 +26605,6 @@ typedef struct { #define OCOTP_LOCK_GP2_MASK (0x3000U) #define OCOTP_LOCK_GP2_SHIFT (12U) #define OCOTP_LOCK_GP2(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_GP2_SHIFT)) & OCOTP_LOCK_GP2_MASK) -#define OCOTP_LOCK_SRK_MASK (0x4000U) -#define OCOTP_LOCK_SRK_SHIFT (14U) -#define OCOTP_LOCK_SRK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_SRK_SHIFT)) & OCOTP_LOCK_SRK_MASK) #define OCOTP_LOCK_ROM_PATCH_MASK (0x8000U) #define OCOTP_LOCK_ROM_PATCH_SHIFT (15U) #define OCOTP_LOCK_ROM_PATCH(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_ROM_PATCH_SHIFT)) & OCOTP_LOCK_ROM_PATCH_MASK) @@ -26865,21 +26724,21 @@ typedef struct { #define OCOTP_MEM4_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MEM4_BITS_SHIFT)) & OCOTP_MEM4_BITS_MASK) /*! @} */ -/*! @name ANA0 - Value of OTP Bank1 Word5 (Analog Info.) */ +/*! @name ANA0 - Value of OTP Bank1 Word5 (Memory Related Info.) */ /*! @{ */ #define OCOTP_ANA0_BITS_MASK (0xFFFFFFFFU) #define OCOTP_ANA0_BITS_SHIFT (0U) #define OCOTP_ANA0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_ANA0_BITS_SHIFT)) & OCOTP_ANA0_BITS_MASK) /*! @} */ -/*! @name ANA1 - Value of OTP Bank1 Word6 (Analog Info.) */ +/*! @name ANA1 - Value of OTP Bank1 Word6 (General Purpose Customer Defined Info.) */ /*! @{ */ #define OCOTP_ANA1_BITS_MASK (0xFFFFFFFFU) #define OCOTP_ANA1_BITS_SHIFT (0U) #define OCOTP_ANA1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_ANA1_BITS_SHIFT)) & OCOTP_ANA1_BITS_MASK) /*! @} */ -/*! @name ANA2 - Value of OTP Bank1 Word7 (Analog Info.) */ +/*! @name ANA2 - Value of OTP Bank1 Word7 (General Purpose Customer Defined Info.) */ /*! @{ */ #define OCOTP_ANA2_BITS_MASK (0xFFFFFFFFU) #define OCOTP_ANA2_BITS_SHIFT (0U) @@ -27026,7 +26885,7 @@ typedef struct { #define OCOTP_MAC1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MAC1_BITS_SHIFT)) & OCOTP_MAC1_BITS_MASK) /*! @} */ -/*! @name MAC2 - Value of OTP Bank4 Word4 (MAC Address) */ +/*! @name MAC2 - Value of OTP Bank4 Word4 (MAC2 Address) */ /*! @{ */ #define OCOTP_MAC2_BITS_MASK (0xFFFFFFFFU) #define OCOTP_MAC2_BITS_SHIFT (0U) @@ -29882,6 +29741,16 @@ typedef struct { #define PWM_CTRL_SPLIT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_SPLIT_SHIFT)) & PWM_CTRL_SPLIT_MASK) #define PWM_CTRL_PRSC_MASK (0x70U) #define PWM_CTRL_PRSC_SHIFT (4U) +/*! PRSC - Prescaler + * 0b000..PWM clock frequency = fclk + * 0b001..PWM clock frequency = fclk/2 + * 0b010..PWM clock frequency = fclk/4 + * 0b011..PWM clock frequency = fclk/8 + * 0b100..PWM clock frequency = fclk/16 + * 0b101..PWM clock frequency = fclk/32 + * 0b110..PWM clock frequency = fclk/64 + * 0b111..PWM clock frequency = fclk/128 + */ #define PWM_CTRL_PRSC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_PRSC_SHIFT)) & PWM_CTRL_PRSC_MASK) #define PWM_CTRL_COMPMODE_MASK (0x80U) #define PWM_CTRL_COMPMODE_SHIFT (7U) @@ -30308,6 +30177,7 @@ typedef struct { #define PWM_DMAEN_VALDE_SHIFT (9U) /*! VALDE - Value Registers DMA Enable * 0b0..DMA write requests disabled + * 0b1..DMA write requests for the VALx and FRACVALx registers enabled */ #define PWM_DMAEN_VALDE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_VALDE_SHIFT)) & PWM_DMAEN_VALDE_MASK) /*! @} */ @@ -30409,6 +30279,10 @@ typedef struct { #define PWM_CAPTCTRLA_ARMA(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_ARMA_SHIFT)) & PWM_CAPTCTRLA_ARMA_MASK) #define PWM_CAPTCTRLA_ONESHOTA_MASK (0x2U) #define PWM_CAPTCTRLA_ONESHOTA_SHIFT (1U) +/*! ONESHOTA - One Shot Mode A + * 0b0..Free running mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after CAPTCTRLA[ARMA] is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and capture circuit 0 is re-armed. The process continues indefinitely.If only one of the capture circuits is enabled, then captures continue indefinitely on the enabled capture circuit. + * 0b1..One shot mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after CAPTCTRLA[ARMA] is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and CAPTCTRLA[ARMA] is cleared. No further captures will be performed until CAPTCTRLA[ARMA] is set again.If only one of the capture circuits is enabled, then a single capture will occur on the enabled capture circuit and CAPTCTRLA[ARMA] is then cleared. + */ #define PWM_CAPTCTRLA_ONESHOTA(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_ONESHOTA_SHIFT)) & PWM_CAPTCTRLA_ONESHOTA_MASK) #define PWM_CAPTCTRLA_EDGA0_MASK (0xCU) #define PWM_CAPTCTRLA_EDGA0_SHIFT (2U) @@ -30432,6 +30306,7 @@ typedef struct { #define PWM_CAPTCTRLA_INP_SELA_SHIFT (6U) /*! INP_SELA - Input Select A * 0b0..Raw PWM_A input signal selected as source. + * 0b1..Output of edge counter/compare selected as source. Note that when this bitfield is set to 1, the internal edge counter is enabled and the rising and/or falling edges specified by the CAPTCTRLA[EDGA0] and CAPTCTRLA[EDGA1] fields are ignored. The software must still place a value other than 00 in either or both of the CAPTCTLRA[EDGA0] and/or CAPTCTRLA[EDGA1] fields in order to enable one or both of the capture registers. */ #define PWM_CAPTCTRLA_INP_SELA(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_INP_SELA_SHIFT)) & PWM_CAPTCTRLA_INP_SELA_MASK) #define PWM_CAPTCTRLA_EDGCNTA_EN_MASK (0x80U) @@ -30479,6 +30354,10 @@ typedef struct { #define PWM_CAPTCTRLB_ARMB(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_ARMB_SHIFT)) & PWM_CAPTCTRLB_ARMB_MASK) #define PWM_CAPTCTRLB_ONESHOTB_MASK (0x2U) #define PWM_CAPTCTRLB_ONESHOTB_SHIFT (1U) +/*! ONESHOTB - One Shot Mode B + * 0b0..Free running mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after CAPTCTRLB[ARMB] is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and capture circuit 0 is re-armed. The process continues indefinitely.If only one of the capture circuits is enabled, then captures continue indefinitely on the enabled capture circuit. + * 0b1..One shot mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after CAPTCTRLB[ARMB] is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and CAPTCTRLB[ARMB] is cleared. No further captures will be performed until CAPTCTRLB[ARMB] is set again.If only one of the capture circuits is enabled, then a single capture will occur on the enabled capture circuit and CAPTCTRLB[ARMB] is then cleared. + */ #define PWM_CAPTCTRLB_ONESHOTB(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_ONESHOTB_SHIFT)) & PWM_CAPTCTRLB_ONESHOTB_MASK) #define PWM_CAPTCTRLB_EDGB0_MASK (0xCU) #define PWM_CAPTCTRLB_EDGB0_SHIFT (2U) @@ -30502,6 +30381,7 @@ typedef struct { #define PWM_CAPTCTRLB_INP_SELB_SHIFT (6U) /*! INP_SELB - Input Select B * 0b0..Raw PWM_B input signal selected as source. + * 0b1..Output of edge counter/compare selected as source. Note that when this bitfield is set to 1, the internal edge counter is enabled and the rising and/or falling edges specified by the CAPTCTRLB[EDGB0] and CAPTCTRLB[EDGB1] fields are ignored. The software must still place a value other than 00 in either or both of the CAPTCTLRB[EDGB0] and/or CAPTCTRLB[EDGB1] fields in order to enable one or both of the capture registers. */ #define PWM_CAPTCTRLB_INP_SELB(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_INP_SELB_SHIFT)) & PWM_CAPTCTRLB_INP_SELB_MASK) #define PWM_CAPTCTRLB_EDGCNTB_EN_MASK (0x80U) @@ -30549,6 +30429,10 @@ typedef struct { #define PWM_CAPTCTRLX_ARMX(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_ARMX_SHIFT)) & PWM_CAPTCTRLX_ARMX_MASK) #define PWM_CAPTCTRLX_ONESHOTX_MASK (0x2U) #define PWM_CAPTCTRLX_ONESHOTX_SHIFT (1U) +/*! ONESHOTX - One Shot Mode Aux + * 0b0..Free running mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after the ARMX bit is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and capture circuit 0 is re-armed. The process continues indefinitely.If only one of the capture circuits is enabled, then captures continue indefinitely on the enabled capture circuit. + * 0b1..One shot mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after the ARMX bit is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and the ARMX bit is cleared. No further captures will be performed until the ARMX bit is set again.If only one of the capture circuits is enabled, then a single capture will occur on the enabled capture circuit and the ARMX bit is then cleared. + */ #define PWM_CAPTCTRLX_ONESHOTX(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_ONESHOTX_SHIFT)) & PWM_CAPTCTRLX_ONESHOTX_MASK) #define PWM_CAPTCTRLX_EDGX0_MASK (0xCU) #define PWM_CAPTCTRLX_EDGX0_SHIFT (2U) @@ -30572,6 +30456,7 @@ typedef struct { #define PWM_CAPTCTRLX_INP_SELX_SHIFT (6U) /*! INP_SELX - Input Select X * 0b0..Raw PWM_X input signal selected as source. + * 0b1..Output of edge counter/compare selected as source. Note that when this bitfield is set to 1, the internal edge counter is enabled and the rising and/or falling edges specified by the CAPTCTRLX[EDGX0] and CAPTCTRLX[EDGX1] fields are ignored. The software must still place a value other than 00 in either or both of the CAPTCTLRX[EDGX0] and/or CAPTCTRLX[EDGX1] fields in order to enable one or both of the capture registers. */ #define PWM_CAPTCTRLX_INP_SELX(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_INP_SELX_SHIFT)) & PWM_CAPTCTRLX_INP_SELX_MASK) #define PWM_CAPTCTRLX_EDGCNTX_EN_MASK (0x80U) @@ -32786,7 +32671,7 @@ typedef struct { #define SEMC_MCR_SWRST(x) (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_SWRST_SHIFT)) & SEMC_MCR_SWRST_MASK) #define SEMC_MCR_MDIS_MASK (0x2U) #define SEMC_MCR_MDIS_SHIFT (1U) -/*! MDIS - Module Disable +/*! MDIS - Module Disable * 0b0..Module enabled * 0b1..Module disabled. */ @@ -33095,14 +32980,14 @@ typedef struct { /*! @{ */ #define SEMC_SDRAMCR0_PS_MASK (0x1U) #define SEMC_SDRAMCR0_PS_SHIFT (0U) -/*! PS - Port Size +/*! PS - Port Size * 0b0..8bit * 0b1..16bit */ #define SEMC_SDRAMCR0_PS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR0_PS_SHIFT)) & SEMC_SDRAMCR0_PS_MASK) #define SEMC_SDRAMCR0_BL_MASK (0x70U) #define SEMC_SDRAMCR0_BL_SHIFT (4U) -/*! BL - Burst Length +/*! BL - Burst Length * 0b000..1 * 0b001..2 * 0b010..4 @@ -33122,7 +33007,7 @@ typedef struct { #define SEMC_SDRAMCR0_COL8(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR0_COL8_SHIFT)) & SEMC_SDRAMCR0_COL8_MASK) #define SEMC_SDRAMCR0_COL_MASK (0x300U) #define SEMC_SDRAMCR0_COL_SHIFT (8U) -/*! COL - Column address bit number +/*! COL - Column address bit number * 0b00..12 bit * 0b01..11 bit * 0b10..10 bit @@ -33131,7 +33016,7 @@ typedef struct { #define SEMC_SDRAMCR0_COL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR0_COL_SHIFT)) & SEMC_SDRAMCR0_COL_MASK) #define SEMC_SDRAMCR0_CL_MASK (0xC00U) #define SEMC_SDRAMCR0_CL_SHIFT (10U) -/*! CL - CAS Latency +/*! CL - CAS Latency * 0b00..1 * 0b01..1 * 0b10..2 @@ -33209,14 +33094,14 @@ typedef struct { #define SEMC_SDRAMCR3_REBL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR3_REBL_SHIFT)) & SEMC_SDRAMCR3_REBL_MASK) #define SEMC_SDRAMCR3_PRESCALE_MASK (0xFF00U) #define SEMC_SDRAMCR3_PRESCALE_SHIFT (8U) -/*! PRESCALE - Prescaler timer period +/*! PRESCALE - Prescaler timer period * 0b00000000..256*16 cycle * 0b00000001-0b11111111..PRESCALE*16 cycle */ #define SEMC_SDRAMCR3_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR3_PRESCALE_SHIFT)) & SEMC_SDRAMCR3_PRESCALE_MASK) #define SEMC_SDRAMCR3_RT_MASK (0xFF0000U) #define SEMC_SDRAMCR3_RT_SHIFT (16U) -/*! RT - Refresh timer period +/*! RT - Refresh timer period * 0b00000000..256*Prescaler period * 0b00000001-0b11111111..RT*Prescaler period */ @@ -33234,7 +33119,7 @@ typedef struct { /*! @{ */ #define SEMC_NANDCR0_PS_MASK (0x1U) #define SEMC_NANDCR0_PS_SHIFT (0U) -/*! PS - Port Size +/*! PS - Port Size * 0b0..8bit * 0b1..16bit */ @@ -33248,7 +33133,7 @@ typedef struct { #define SEMC_NANDCR0_SYNCEN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR0_SYNCEN_SHIFT)) & SEMC_NANDCR0_SYNCEN_MASK) #define SEMC_NANDCR0_BL_MASK (0x70U) #define SEMC_NANDCR0_BL_SHIFT (4U) -/*! BL - Burst Length +/*! BL - Burst Length * 0b000..1 * 0b001..2 * 0b010..4 @@ -33268,7 +33153,7 @@ typedef struct { #define SEMC_NANDCR0_EDO(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR0_EDO_SHIFT)) & SEMC_NANDCR0_EDO_MASK) #define SEMC_NANDCR0_COL_MASK (0x700U) #define SEMC_NANDCR0_COL_SHIFT (8U) -/*! COL - Column address bit number +/*! COL - Column address bit number * 0b000..16 * 0b001..15 * 0b010..14 @@ -33360,7 +33245,7 @@ typedef struct { /*! @{ */ #define SEMC_NORCR0_PS_MASK (0x1U) #define SEMC_NORCR0_PS_SHIFT (0U) -/*! PS - Port Size +/*! PS - Port Size * 0b0..8bit * 0b1..16bit */ @@ -33374,7 +33259,7 @@ typedef struct { #define SEMC_NORCR0_SYNCEN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_SYNCEN_SHIFT)) & SEMC_NORCR0_SYNCEN_MASK) #define SEMC_NORCR0_BL_MASK (0x70U) #define SEMC_NORCR0_BL_SHIFT (4U) -/*! BL - Burst Length +/*! BL - Burst Length * 0b000..1 * 0b001..2 * 0b010..4 @@ -33387,7 +33272,7 @@ typedef struct { #define SEMC_NORCR0_BL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_BL_SHIFT)) & SEMC_NORCR0_BL_MASK) #define SEMC_NORCR0_AM_MASK (0x300U) #define SEMC_NORCR0_AM_SHIFT (8U) -/*! AM - Address Mode +/*! AM - Address Mode * 0b00..Address/Data MUX mode * 0b01..Advanced Address/Data MUX mode * 0b10..Address/Data non-MUX mode @@ -33396,21 +33281,21 @@ typedef struct { #define SEMC_NORCR0_AM(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_AM_SHIFT)) & SEMC_NORCR0_AM_MASK) #define SEMC_NORCR0_ADVP_MASK (0x400U) #define SEMC_NORCR0_ADVP_SHIFT (10U) -/*! ADVP - ADV# polarity +/*! ADVP - ADV# polarity * 0b0..ADV# is Low Active. In ASYNC mode, device sample address with ADV# rise edge; In SYNC mode, device sample address when ADV# is LOW. * 0b1..ADV# is High Active. In ASYNC mode, device sample address with ADV# fall edge; In SYNC mode, device sample address when ADV# is HIGH. */ #define SEMC_NORCR0_ADVP(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_ADVP_SHIFT)) & SEMC_NORCR0_ADVP_MASK) #define SEMC_NORCR0_ADVH_MASK (0x800U) #define SEMC_NORCR0_ADVH_SHIFT (11U) -/*! ADVH - ADV# level control during address hold state +/*! ADVH - ADV# level control during address hold state * 0b0..ADV# is high during address hold state. * 0b1..ADV# is low during address hold state. */ #define SEMC_NORCR0_ADVH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_ADVH_SHIFT)) & SEMC_NORCR0_ADVH_MASK) #define SEMC_NORCR0_COL_MASK (0xF000U) #define SEMC_NORCR0_COL_SHIFT (12U) -/*! COL - Column Address bit width +/*! COL - Column Address bit width * 0b0000..12 Bits * 0b0001..11 Bits * 0b0010..10 Bits @@ -33495,7 +33380,7 @@ typedef struct { /*! @{ */ #define SEMC_SRAMCR0_PS_MASK (0x1U) #define SEMC_SRAMCR0_PS_SHIFT (0U) -/*! PS - Port Size +/*! PS - Port Size * 0b0..8bit * 0b1..16bit */ @@ -33509,7 +33394,7 @@ typedef struct { #define SEMC_SRAMCR0_SYNCEN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_SYNCEN_SHIFT)) & SEMC_SRAMCR0_SYNCEN_MASK) #define SEMC_SRAMCR0_BL_MASK (0x70U) #define SEMC_SRAMCR0_BL_SHIFT (4U) -/*! BL - Burst Length +/*! BL - Burst Length * 0b000..1 * 0b001..2 * 0b010..4 @@ -33522,7 +33407,7 @@ typedef struct { #define SEMC_SRAMCR0_BL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_BL_SHIFT)) & SEMC_SRAMCR0_BL_MASK) #define SEMC_SRAMCR0_AM_MASK (0x300U) #define SEMC_SRAMCR0_AM_SHIFT (8U) -/*! AM - Address Mode +/*! AM - Address Mode * 0b00..Address/Data MUX mode * 0b01..Advanced Address/Data MUX mode * 0b10..Address/Data non-MUX mode @@ -33531,21 +33416,21 @@ typedef struct { #define SEMC_SRAMCR0_AM(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_AM_SHIFT)) & SEMC_SRAMCR0_AM_MASK) #define SEMC_SRAMCR0_ADVP_MASK (0x400U) #define SEMC_SRAMCR0_ADVP_SHIFT (10U) -/*! ADVP - ADV# polarity +/*! ADVP - ADV# polarity * 0b0..ADV# is Low Active. In ASYNC mode, device sample address with ADV# rise edge; In SYNC mode, device sample address when ADV# is LOW. * 0b1..ADV# is High Active. In ASYNC mode, device sample address with ADV# fall edge; In SYNC mode, device sample address when ADV# is HIGH. */ #define SEMC_SRAMCR0_ADVP(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_ADVP_SHIFT)) & SEMC_SRAMCR0_ADVP_MASK) #define SEMC_SRAMCR0_ADVH_MASK (0x800U) #define SEMC_SRAMCR0_ADVH_SHIFT (11U) -/*! ADVH - ADV# level control during address hold state +/*! ADVH - ADV# level control during address hold state * 0b0..ADV# is high during address hold state. * 0b1..ADV# is low during address hold state. */ #define SEMC_SRAMCR0_ADVH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_ADVH_SHIFT)) & SEMC_SRAMCR0_ADVH_MASK) #define SEMC_SRAMCR0_COL_MASK (0xF000U) #define SEMC_SRAMCR0_COL_SHIFT (12U) -/*! COL - Column Address bit width +/*! COL - Column Address bit width * 0b0000..12 Bits * 0b0001..11 Bits * 0b0010..10 Bits @@ -33626,14 +33511,14 @@ typedef struct { /*! @{ */ #define SEMC_DBICR0_PS_MASK (0x1U) #define SEMC_DBICR0_PS_SHIFT (0U) -/*! PS - Port Size +/*! PS - Port Size * 0b0..8bit * 0b1..16bit */ #define SEMC_DBICR0_PS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR0_PS_SHIFT)) & SEMC_DBICR0_PS_MASK) #define SEMC_DBICR0_BL_MASK (0x70U) #define SEMC_DBICR0_BL_SHIFT (4U) -/*! BL - Burst Length +/*! BL - Burst Length * 0b000..1 * 0b001..2 * 0b010..4 @@ -33646,7 +33531,7 @@ typedef struct { #define SEMC_DBICR0_BL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR0_BL_SHIFT)) & SEMC_DBICR0_BL_MASK) #define SEMC_DBICR0_COL_MASK (0xF000U) #define SEMC_DBICR0_COL_SHIFT (12U) -/*! COL - Column Address bit width +/*! COL - Column Address bit width * 0b0000..12 Bits * 0b0001..11 Bits * 0b0010..10 Bits @@ -33703,7 +33588,7 @@ typedef struct { /*! @{ */ #define SEMC_IPCR1_DATSZ_MASK (0x7U) #define SEMC_IPCR1_DATSZ_SHIFT (0U) -/*! DATSZ - Data Size in Byte +/*! DATSZ - Data Size in Byte * 0b000..4 * 0b001..1 * 0b010..2 @@ -34042,6 +33927,10 @@ typedef struct { #define SNVS_HPCOMR_PROG_ZMK(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_PROG_ZMK_SHIFT)) & SNVS_HPCOMR_PROG_ZMK_MASK) #define SNVS_HPCOMR_MKS_EN_MASK (0x2000U) #define SNVS_HPCOMR_MKS_EN_SHIFT (13U) +/*! MKS_EN + * 0b0..OTP master key is selected as an SNVS master key + * 0b1..SNVS master key is selected according to the setting of the MASTER_KEY_SEL field of LPMKCR + */ #define SNVS_HPCOMR_MKS_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_MKS_EN_SHIFT)) & SNVS_HPCOMR_MKS_EN_MASK) #define SNVS_HPCOMR_HAC_EN_MASK (0x10000U) #define SNVS_HPCOMR_HAC_EN_SHIFT (16U) @@ -34605,6 +34494,8 @@ typedef struct { #define SNVS_LPMKCR_MASTER_KEY_SEL_SHIFT (0U) /*! MASTER_KEY_SEL * 0b0x..Select one time programmable master key. + * 0b10..Select zeroizable master key when MKS_EN bit is set . + * 0b11..Select combined master key when MKS_EN bit is set . */ #define SNVS_LPMKCR_MASTER_KEY_SEL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPMKCR_MASTER_KEY_SEL_SHIFT)) & SNVS_LPMKCR_MASTER_KEY_SEL_MASK) #define SNVS_LPMKCR_ZMK_HWP_MASK (0x4U) @@ -41109,6 +41000,13 @@ typedef struct { #define USDHC_SYS_CTRL_SDCLKFS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_SDCLKFS_SHIFT)) & USDHC_SYS_CTRL_SDCLKFS_MASK) #define USDHC_SYS_CTRL_DTOCV_MASK (0xF0000U) #define USDHC_SYS_CTRL_DTOCV_SHIFT (16U) +/*! DTOCV - Data Timeout Counter Value + * 0b1111..SDCLK x 2 29 + * 0b1110..SDCLK x 2 28 + * 0b1101..SDCLK x 2 27 + * 0b0001..SDCLK x 2 15 + * 0b0000..SDCLK x 2 14 + */ #define USDHC_SYS_CTRL_DTOCV(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_DTOCV_SHIFT)) & USDHC_SYS_CTRL_DTOCV_MASK) #define USDHC_SYS_CTRL_IPP_RST_N_MASK (0x800000U) #define USDHC_SYS_CTRL_IPP_RST_N_SHIFT (23U) @@ -42220,6 +42118,10 @@ typedef struct { #define WDOG_WCR_WDE(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDE_SHIFT)) & WDOG_WCR_WDE_MASK) #define WDOG_WCR_WDT_MASK (0x8U) #define WDOG_WCR_WDT_SHIFT (3U) +/*! WDT - WDT + * 0b0..No effect on WDOG_B (Default). + * 0b1..Assert WDOG_B upon a Watchdog Time-out event. + */ #define WDOG_WCR_WDT(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDT_SHIFT)) & WDOG_WCR_WDT_MASK) #define WDOG_WCR_SRS_MASK (0x10U) #define WDOG_WCR_SRS_SHIFT (4U) @@ -42231,6 +42133,7 @@ typedef struct { #define WDOG_WCR_WDA_MASK (0x20U) #define WDOG_WCR_WDA_SHIFT (5U) /*! WDA - WDA + * 0b0..Assert WDOG_B output. * 0b1..No effect on system (Default). */ #define WDOG_WCR_WDA(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDA_SHIFT)) & WDOG_WCR_WDA_MASK) diff --git a/ext/hal/nxp/mcux/devices/MIMXRT1062/MIMXRT1062.xml b/ext/hal/nxp/mcux/devices/MIMXRT1062/MIMXRT1062.xml index 4dfa0e4b017..5a2efbc9a14 100644 --- a/ext/hal/nxp/mcux/devices/MIMXRT1062/MIMXRT1062.xml +++ b/ext/hal/nxp/mcux/devices/MIMXRT1062/MIMXRT1062.xml @@ -6,6 +6,7 @@ MIMXRT1062DVL6A Copyright 2016-2018 NXP +All rights reserved. SPDX-License-Identifier: BSD-3-Clause @@ -8097,13 +8098,6 @@ SPDX-License-Identifier: BSD-3-Clause - - CM7_INIT_VTOR - Vector table offset register out of reset - 7 - 25 - read-write - @@ -8729,145 +8723,6 @@ SPDX-License-Identifier: BSD-3-Clause 1 read-write - - Reserved - Reserved - 3 - 29 - read-only - - - - - OCRAM_MAGIC_ADDR - OCRAM Magic Address Register - 0x4 - 32 - read-write - 0 - 0xFFFFFFFF - - - OCRAM_WR_RD_SEL - OCRAM Write Read Select - 0 - 1 - read-write - - - OCRAM_WR_RD_SEL_0 - When OCRAM read access hits magic address, it will generate interrupt. - 0 - - - OCRAM_WR_RD_SEL_1 - When OCRAM write access hits magic address, it will generate interrupt. - 0x1 - - - - - OCRAM_MAGIC_ADDR - OCRAM Magic Address - 1 - 16 - read-write - - - Reserved - Reserved - 17 - 15 - read-only - - - - - DTCM_MAGIC_ADDR - DTCM Magic Address Register - 0x8 - 32 - read-write - 0 - 0xFFFFFFFF - - - DTCM_WR_RD_SEL - DTCM Write Read Select - 0 - 1 - read-write - - - DTCM_WR_RD_SEL_0 - When DTCM read access hits magic address, it will generate interrupt. - 0 - - - DTCM_WR_RD_SEL_1 - When DTCM write access hits magic address, it will generate interrupt. - 0x1 - - - - - DTCM_MAGIC_ADDR - DTCM Magic Address - 1 - 16 - read-write - - - Reserved - Reserved - 17 - 15 - read-only - - - - - ITCM_MAGIC_ADDR - ITCM Magic Address Register - 0xC - 32 - read-write - 0 - 0xFFFFFFFF - - - ITCM_WR_RD_SEL - ITCM Write Read Select - 0 - 1 - read-write - - - ITCM_WR_RD_SEL_0 - When ITCM read access hits magic address, it will generate interrupt. - 0 - - - ITCM_WR_RD_SEL_1 - When ITCM write access hits magic address, it will generate interrupt. - 0x1 - - - - - ITCM_MAGIC_ADDR - ITCM Magic Address - 1 - 16 - read-write - - - Reserved - Reserved - 17 - 15 - read-only - @@ -8879,66 +8734,6 @@ SPDX-License-Identifier: BSD-3-Clause 0 0xFFFFFFFF - - ITCM_MAM_STATUS - ITCM Magic Address Match Status - 0 - 1 - read-write - oneToClear - - - ITCM_MAM_STATUS_0 - ITCM did not access magic address. - 0 - - - ITCM_MAM_STATUS_1 - ITCM accessed magic address. - 0x1 - - - - - DTCM_MAM_STATUS - DTCM Magic Address Match Status - 1 - 1 - read-write - oneToClear - - - DTCM_MAM_STATUS_0 - DTCM did not access magic address. - 0 - - - DTCM_MAM_STATUS_1 - DTCM accessed magic address. - 0x1 - - - - - OCRAM_MAM_STATUS - OCRAM Magic Address Match Status - 2 - 1 - read-write - oneToClear - - - OCRAM_MAM_STATUS_0 - OCRAM did not access magic address. - 0 - - - OCRAM_MAM_STATUS_1 - OCRAM accessed magic address. - 0x1 - - - ITCM_ERR_STATUS ITCM Access Error Status @@ -8999,13 +8794,6 @@ SPDX-License-Identifier: BSD-3-Clause - - Reserved - Reserved - 6 - 26 - read-only - @@ -9017,63 +8805,6 @@ SPDX-License-Identifier: BSD-3-Clause 0 0xFFFFFFFF - - ITCM_MAM_STAT_EN - ITCM Magic Address Match Status Enable - 0 - 1 - read-write - - - ITCM_MAM_STAT_EN_0 - Masked - 0 - - - ITCM_MAM_STAT_EN_1 - Enabled - 0x1 - - - - - DTCM_MAM_STAT_EN - DTCM Magic Address Match Status Enable - 1 - 1 - read-write - - - DTCM_MAM_STAT_EN_0 - Masked - 0 - - - DTCM_MAM_STAT_EN_1 - Enabled - 0x1 - - - - - OCRAM_MAM_STAT_EN - OCRAM Magic Address Match Status Enable - 2 - 1 - read-write - - - OCRAM_MAM_STAT_EN_0 - Masked - 0 - - - OCRAM_MAM_STAT_EN_1 - Enabled - 0x1 - - - ITCM_ERR_STAT_EN ITCM Access Error Status Enable @@ -9131,13 +8862,6 @@ SPDX-License-Identifier: BSD-3-Clause - - Reserved - Reserved - 6 - 26 - read-only - @@ -9149,63 +8873,6 @@ SPDX-License-Identifier: BSD-3-Clause 0 0xFFFFFFFF - - ITCM_MAM_SIG_EN - ITCM Magic Address Match Interrupt Enable - 0 - 1 - read-write - - - ITCM_MAM_SIG_EN_0 - Masked - 0 - - - ITCM_MAM_SIG_EN_1 - Enabled - 0x1 - - - - - DTCM_MAM_SIG_EN - DTCM Magic Address Match Interrupt Enable - 1 - 1 - read-write - - - DTCM_MAM_SIG_EN_0 - Masked - 0 - - - DTCM_MAM_SIG_EN_1 - Enabled - 0x1 - - - - - OCRAM_MAM_SIG_EN - OCRAM Magic Address Match Interrupt Enable - 2 - 1 - read-write - - - OCRAM_MAM_SIG_EN_0 - Masked - 0 - - - OCRAM_MAM_SIG_EN_1 - Enabled - 0x1 - - - ITCM_ERR_SIG_EN ITCM Access Error Interrupt Enable @@ -9263,13 +8930,6 @@ SPDX-License-Identifier: BSD-3-Clause - - Reserved - Reserved - 6 - 26 - read-only - @@ -78935,6 +78595,94 @@ SPDX-License-Identifier: BSD-3-Clause + + DBG1 + Debug 1 register + 0x58 + 32 + read-only + 0x10000 + 0xFFFFFFFF + + + CFSM + CAN Finite State Machine + 0 + 6 + read-only + + + CBN + CAN Bit Number + 24 + 5 + read-only + + + + + DBG2 + Debug 2 register + 0x5C + 32 + read-only + 0 + 0xFFFFFFFF + + + RMP + Rx Matching Pointer + 0 + 7 + read-only + + + MPP + Matching Process in Progress + 7 + 1 + read-only + + + MPP_0 + No matching process ongoing. + 0 + + + MPP_1 + Matching process is in progress. + 0x1 + + + + + TAP + Tx Arbitration Pointer + 8 + 7 + read-only + + + APP + Arbitration Process in Progress + 15 + 1 + read-only + + + APP_0 + No matching process ongoing. + 0 + + + APP_1 + Matching process is in progress. + 0x1 + + + + + 64 0x4 @@ -140288,13 +140036,6 @@ SPDX-License-Identifier: BSD-3-Clause 2 read-only - - SRK - SRK - 14 - 1 - read-only - ROM_PATCH ROM_PATCH @@ -140592,7 +140333,7 @@ SPDX-License-Identifier: BSD-3-Clause ANA0 - Value of OTP Bank1 Word5 (Analog Info.) + Value of OTP Bank1 Word5 (Memory Related Info.) 0x4D0 32 read-write @@ -140610,7 +140351,7 @@ SPDX-License-Identifier: BSD-3-Clause ANA1 - Value of OTP Bank1 Word6 (Analog Info.) + Value of OTP Bank1 Word6 (General Purpose Customer Defined Info.) 0x4E0 32 read-write @@ -140628,7 +140369,7 @@ SPDX-License-Identifier: BSD-3-Clause ANA2 - Value of OTP Bank1 Word7 (Analog Info.) + Value of OTP Bank1 Word7 (General Purpose Customer Defined Info.) 0x4F0 32 read-write @@ -141006,7 +140747,7 @@ SPDX-License-Identifier: BSD-3-Clause MAC2 - Value of OTP Bank4 Word4 (MAC Address) + Value of OTP Bank4 Word4 (MAC2 Address) 0x640 32 read-write diff --git a/ext/hal/nxp/mcux/devices/MIMXRT1062/MIMXRT1062_features.h b/ext/hal/nxp/mcux/devices/MIMXRT1062/MIMXRT1062_features.h index 9c92c971c96..bb9a2c779b2 100644 --- a/ext/hal/nxp/mcux/devices/MIMXRT1062/MIMXRT1062_features.h +++ b/ext/hal/nxp/mcux/devices/MIMXRT1062/MIMXRT1062_features.h @@ -1,13 +1,14 @@ /* ** ################################################################### -** Version: rev. 0.1, 2017-01-10 -** Build: b180806 +** Version: rev. 1.0, 2018-11-16 +** Build: b181120 ** ** Abstract: ** Chip specific module features. ** ** Copyright 2016 Freescale Semiconductor, Inc. ** Copyright 2016-2018 NXP +** All rights reserved. ** ** SPDX-License-Identifier: BSD-3-Clause ** @@ -17,6 +18,8 @@ ** Revisions: ** - rev. 0.1 (2017-01-10) ** Initial version. +** - rev. 1.0 (2018-11-16) +** Update feature files to align with IMXRT1060RM Rev.0. ** ** ################################################################### */ @@ -69,7 +72,7 @@ /* @brief I2S availability on the SoC. */ #define FSL_FEATURE_SOC_I2S_COUNT (3) /* @brief IGPIO availability on the SoC. */ -#define FSL_FEATURE_SOC_IGPIO_COUNT (10) +#define FSL_FEATURE_SOC_IGPIO_COUNT (9) /* @brief IOMUXC availability on the SoC. */ #define FSL_FEATURE_SOC_IOMUXC_COUNT (1) /* @brief IOMUXC_GPR availability on the SoC. */ @@ -186,6 +189,12 @@ ((x) == CAN3 ? (0) : (-1)))) /* @brief Is affected by errata with ID 5641 (Module does not transmit a message that is enabled to be transmitted at a specific moment during the arbitration process). */ #define FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641 (0) +/* @brief Is affected by errata with ID 5829 (FlexCAN: FlexCAN does not transmit a message that is enabled to be transmitted in a specific moment during the arbitration process). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_5829 (1) +/* @brief Is affected by errata with ID 6032 (FlexCAN: A frame with wrong ID or payload is transmitted into the CAN bus when the Message Buffer under transmission is either aborted or deactivated while the CAN bus is in the Bus Idle state). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_6032 (1) +/* @brief Is affected by errata with ID 9595 (FlexCAN: Corrupt frame possible if the Freeze Mode or the Low-Power Mode are entered during a Bus-Off state). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_9595 (1) /* @brief Has CAN with Flexible Data rate (CAN FD) protocol. */ #define FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE (1) /* @brief CAN instance support Flexible Data rate (CAN FD) protocol. */ @@ -283,7 +292,7 @@ /* FLEXRAM module features */ /* @brief Bank size */ -#define FSL_FEATURE_FLEXRAM_INTERNAL_RAM_BANK_SIZE (32 * 1024) +#define FSL_FEATURE_FLEXRAM_INTERNAL_RAM_BANK_SIZE (32768) /* @brief Total Bank numbers */ #define FSL_FEATURE_FLEXRAM_INTERNAL_RAM_TOTAL_BANK_NUMBERS (16) diff --git a/ext/hal/nxp/mcux/devices/MIMXRT1062/fsl_clock.c b/ext/hal/nxp/mcux/devices/MIMXRT1062/fsl_clock.c index 40ba8e2cf17..3a0f5de829d 100644 --- a/ext/hal/nxp/mcux/devices/MIMXRT1062/fsl_clock.c +++ b/ext/hal/nxp/mcux/devices/MIMXRT1062/fsl_clock.c @@ -14,20 +14,21 @@ /******************************************************************************* * Definitions ******************************************************************************/ -/* To make full use of CM7 hardware FPU, use double instead of uint64_t in clock driver to +/* To make full use of CM7 hardware FPU, use double instead of uint64_t in clock driver to achieve better performance, it is depend on the IDE Floating point settings, if double precision is selected in IDE, clock_64b_t will switch to double type automatically. only support IAR and MDK here */ #if __FPU_USED #if ((defined(__ICCARM__)) || (defined(__GNUC__))) -#if (__ARMVFP__ >= __ARMFPV5__) && (__ARM_FP == 0xE) /*0xe implies support for half, single and double precision operations*/ +#if (__ARMVFP__ >= __ARMFPV5__) && \ + (__ARM_FP == 0xE) /*0xe implies support for half, single and double precision operations*/ typedef double clock_64b_t; #else typedef uint64_t clock_64b_t; #endif -#elif defined(__CC_ARM) +#elif defined(__CC_ARM) || defined(__ARMCC_VERSION) #if defined __TARGET_FPU_FPV5_D16 typedef double clock_64b_t; @@ -447,7 +448,7 @@ bool CLOCK_EnableUsbhs0PhyPllClock(clock_usb_phy_src_t src, uint32_t freq) const clock_usb_pll_config_t g_ccmConfigUsbPll = {.loopDivider = 0U}; if (CCM_ANALOG->PLL_USB1 & CCM_ANALOG_PLL_USB1_ENABLE_MASK) { - CCM_ANALOG->PLL_USB1 |= CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK; + CCM_ANALOG->PLL_USB1 |= CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK; } else { @@ -468,7 +469,7 @@ bool CLOCK_EnableUsbhs0PhyPllClock(clock_usb_phy_src_t src, uint32_t freq) */ void CLOCK_DisableUsbhs0PhyPllClock(void) { - CCM_ANALOG->PLL_USB1 &= ~CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK; + CCM_ANALOG->PLL_USB1 &= ~CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK; USBPHY1->CTRL |= USBPHY_CTRL_CLKGATE_MASK; /* Set to 1U to gate clocks */ } @@ -522,6 +523,15 @@ void CLOCK_InitSysPll(const clock_sys_pll_config_t *config) (CCM_ANALOG->PLL_SYS & (~(CCM_ANALOG_PLL_SYS_DIV_SELECT_MASK | CCM_ANALOG_PLL_SYS_POWERDOWN_MASK))) | CCM_ANALOG_PLL_SYS_ENABLE_MASK | CCM_ANALOG_PLL_SYS_DIV_SELECT(config->loopDivider); + /* Initialize the fractional mode */ + CCM_ANALOG->PLL_SYS_NUM = CCM_ANALOG_PLL_SYS_NUM_A(config->numerator); + CCM_ANALOG->PLL_SYS_DENOM = CCM_ANALOG_PLL_SYS_DENOM_B(config->denominator); + + /* Initialize the spread spectrum mode */ + CCM_ANALOG->PLL_SYS_SS = CCM_ANALOG_PLL_SYS_SS_STEP(config->ss_step) | + CCM_ANALOG_PLL_SYS_SS_ENABLE(config->ss_enable) | + CCM_ANALOG_PLL_SYS_SS_STOP(config->ss_stop); + while ((CCM_ANALOG->PLL_SYS & CCM_ANALOG_PLL_SYS_LOCK_MASK) == 0) { } @@ -809,7 +819,8 @@ void CLOCK_InitEnetPll(const clock_enet_pll_config_t *config) CCM_ANALOG->PLL_ENET = (CCM_ANALOG->PLL_ENET & (~(CCM_ANALOG_PLL_ENET_DIV_SELECT_MASK | CCM_ANALOG_PLL_ENET_ENET2_DIV_SELECT_MASK | - CCM_ANALOG_PLL_ENET_POWERDOWN_MASK))) | enet_pll; + CCM_ANALOG_PLL_ENET_POWERDOWN_MASK))) | + enet_pll; /* Wait for stable */ while ((CCM_ANALOG->PLL_ENET & CCM_ANALOG_PLL_ENET_LOCK_MASK) == 0) @@ -875,8 +886,8 @@ uint32_t CLOCK_GetPllFreq(clock_pll_t pll) break; case kCLOCK_PllSys: /* PLL output frequency = Fref * (DIV_SELECT + NUM/DENOM). */ - freqTmp = - ((clock_64b_t)freq * ((clock_64b_t)(CCM_ANALOG->PLL_SYS_NUM))) / ((clock_64b_t)(CCM_ANALOG->PLL_SYS_DENOM)); + freqTmp = ((clock_64b_t)freq * ((clock_64b_t)(CCM_ANALOG->PLL_SYS_NUM))) / + ((clock_64b_t)(CCM_ANALOG->PLL_SYS_DENOM)); if (CCM_ANALOG->PLL_SYS & CCM_ANALOG_PLL_SYS_DIV_SELECT_MASK) { @@ -899,8 +910,8 @@ uint32_t CLOCK_GetPllFreq(clock_pll_t pll) divSelect = (CCM_ANALOG->PLL_AUDIO & CCM_ANALOG_PLL_AUDIO_DIV_SELECT_MASK) >> CCM_ANALOG_PLL_AUDIO_DIV_SELECT_SHIFT; - freqTmp = - ((clock_64b_t)freq * ((clock_64b_t)(CCM_ANALOG->PLL_AUDIO_NUM))) / ((clock_64b_t)(CCM_ANALOG->PLL_AUDIO_DENOM)); + freqTmp = ((clock_64b_t)freq * ((clock_64b_t)(CCM_ANALOG->PLL_AUDIO_NUM))) / + ((clock_64b_t)(CCM_ANALOG->PLL_AUDIO_DENOM)); freq = freq * divSelect + (uint32_t)freqTmp; @@ -954,8 +965,8 @@ uint32_t CLOCK_GetPllFreq(clock_pll_t pll) divSelect = (CCM_ANALOG->PLL_VIDEO & CCM_ANALOG_PLL_VIDEO_DIV_SELECT_MASK) >> CCM_ANALOG_PLL_VIDEO_DIV_SELECT_SHIFT; - freqTmp = - ((clock_64b_t)freq * ((clock_64b_t)(CCM_ANALOG->PLL_VIDEO_NUM))) / ((clock_64b_t)(CCM_ANALOG->PLL_VIDEO_DENOM)); + freqTmp = ((clock_64b_t)freq * ((clock_64b_t)(CCM_ANALOG->PLL_VIDEO_NUM))) / + ((clock_64b_t)(CCM_ANALOG->PLL_VIDEO_DENOM)); freq = freq * divSelect + (uint32_t)freqTmp; @@ -1212,6 +1223,6 @@ bool CLOCK_EnableUsbhs1PhyPllClock(clock_usb_phy_src_t src, uint32_t freq) */ void CLOCK_DisableUsbhs1PhyPllClock(void) { - CCM_ANALOG->PLL_USB2 &= ~CCM_ANALOG_PLL_USB2_EN_USB_CLKS_MASK; + CCM_ANALOG->PLL_USB2 &= ~CCM_ANALOG_PLL_USB2_EN_USB_CLKS_MASK; USBPHY2->CTRL |= USBPHY_CTRL_CLKGATE_MASK; /* Set to 1U to gate clocks */ } diff --git a/ext/hal/nxp/mcux/devices/MIMXRT1062/fsl_clock.h b/ext/hal/nxp/mcux/devices/MIMXRT1062/fsl_clock.h index dda0e8407b8..997bbd9c4e4 100644 --- a/ext/hal/nxp/mcux/devices/MIMXRT1062/fsl_clock.h +++ b/ext/hal/nxp/mcux/devices/MIMXRT1062/fsl_clock.h @@ -39,8 +39,8 @@ /*! @name Driver version */ /*@{*/ -/*! @brief CLOCK driver version 2.1.5. */ -#define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 1, 5)) +/*! @brief CLOCK driver version 2.1.6. */ +#define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 1, 6)) /* analog pll definition */ #define CCM_ANALOG_PLL_BYPASS_SHIFT (16U) @@ -48,9 +48,9 @@ #define CCM_ANALOG_PLL_BYPASS_CLK_SRC_SHIFT (14U) /*@}*/ -#define CCM_TUPLE(reg, shift, mask, busyShift) \ - ((((uint32_t)(&((CCM_Type *)0U)->reg)) & 0xFFU) | ((shift) << 8U) | ((((mask) >> (shift)) & 0x1FFFU) << 13U) | \ - ((busyShift) << 26U)) +#define CCM_TUPLE(reg, shift, mask, busyShift) \ + (int)((((uint32_t)(&((CCM_Type *)0U)->reg)) & 0xFFU) | ((shift) << 8U) | \ + ((((mask) >> (shift)) & 0x1FFFU) << 13U) | ((busyShift) << 26U)) #define CCM_TUPLE_REG(base, tuple) (*((volatile uint32_t *)(((uint32_t)(base)) + ((tuple)&0xFFU)))) #define CCM_TUPLE_SHIFT(tuple) (((tuple) >> 8U) & 0x1FU) #define CCM_TUPLE_MASK(tuple) ((uint32_t)((((tuple) >> 13U) & 0x1FFFU) << ((((tuple) >> 8U) & 0x1FU)))) @@ -769,8 +769,8 @@ typedef enum _clock_div /*! @brief USB clock source definition. */ typedef enum _clock_usb_src { - kCLOCK_Usb480M = 0, /*!< Use 480M. */ - kCLOCK_UsbSrcUnused = 0xFFFFFFFFU, /*!< Used when the function does not + kCLOCK_Usb480M = 0, /*!< Use 480M. */ + kCLOCK_UsbSrcUnused = (int)0xFFFFFFFFU, /*!< Used when the function does not care the clock source. */ } clock_usb_src_t; @@ -813,7 +813,9 @@ typedef struct _clock_sys_pll_config uint32_t numerator; /*!< 30 bit numerator of fractional loop divider.*/ uint32_t denominator; /*!< 30 bit denominator of fractional loop divider */ uint8_t src; /*!< Pll clock source, reference _clock_pll_clk_src */ - + uint16_t ss_stop; /*!< Stop value to get frequency change. */ + uint8_t ss_enable; /*!< Enable spread spectrum modulation */ + uint16_t ss_step; /*!< Step value to get frequency change step. */ } clock_sys_pll_config_t; /*! @brief PLL configuration for AUDIO and VIDEO */ diff --git a/ext/hal/nxp/mcux/devices/MIMXRT1062/fsl_iomuxc.h b/ext/hal/nxp/mcux/devices/MIMXRT1062/fsl_iomuxc.h index e4cad1d0883..1811f9b0759 100644 --- a/ext/hal/nxp/mcux/devices/MIMXRT1062/fsl_iomuxc.h +++ b/ext/hal/nxp/mcux/devices/MIMXRT1062/fsl_iomuxc.h @@ -1,7 +1,7 @@ /* * Copyright 2016 Freescale Semiconductor, Inc. * Copyright 2016-2018 NXP - * + * * SPDX-License-Identifier: BSD-3-Clause */ @@ -27,8 +27,8 @@ /*! @name Driver version */ /*@{*/ -/*! @brief IOMUXC driver version 2.0.0. */ -#define FSL_IOMUXC_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) +/*! @brief IOMUXC driver version 2.0.1. */ +#define FSL_IOMUXC_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) /*@}*/ /*! @name Pin function ID */ @@ -1206,23 +1206,25 @@ typedef enum _iomuxc_gpr_mode { kIOMUXC_GPR_GlobalInterruptRequest = IOMUXC_GPR_GPR1_GINT_MASK, kIOMUXC_GPR_ENET1RefClkMode = IOMUXC_GPR_GPR1_ENET1_CLK_SEL_MASK, + kIOMUXC_GPR_ENET2RefClkMode = IOMUXC_GPR_GPR1_ENET2_CLK_SEL_MASK, kIOMUXC_GPR_USBExposureMode = IOMUXC_GPR_GPR1_USB_EXP_MODE_MASK, kIOMUXC_GPR_ENET1TxClkOutputDir = IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK, + kIOMUXC_GPR_ENET2TxClkOutputDir = IOMUXC_GPR_GPR1_ENET2_TX_CLK_DIR_MASK, kIOMUXC_GPR_SAI1MClkOutputDir = IOMUXC_GPR_GPR1_SAI1_MCLK_DIR_MASK, kIOMUXC_GPR_SAI2MClkOutputDir = IOMUXC_GPR_GPR1_SAI2_MCLK_DIR_MASK, kIOMUXC_GPR_SAI3MClkOutputDir = IOMUXC_GPR_GPR1_SAI3_MCLK_DIR_MASK, kIOMUXC_GPR_ExcMonitorSlavErrResponse = IOMUXC_GPR_GPR1_EXC_MON_MASK, kIOMUXC_GPR_ENETIpgClkOn = IOMUXC_GPR_GPR1_ENET_IPG_CLK_S_EN_MASK, - kIOMUXC_GPR_AHBClockEnable = IOMUXC_GPR_GPR1_CM7_FORCE_HCLK_EN_MASK, -} iomuxc_gpr_mode_t; + kIOMUXC_GPR_AHBClockEnable = (int)IOMUXC_GPR_GPR1_CM7_FORCE_HCLK_EN_MASK, +} iomuxc_gpr_mode_t; typedef enum _iomuxc_gpr_saimclk { kIOMUXC_GPR_SAI1MClk1Sel = IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL_SHIFT, kIOMUXC_GPR_SAI1MClk2Sel = IOMUXC_GPR_GPR1_SAI1_MCLK2_SEL_SHIFT, - kIOMUXC_GPR_SAI1MClk3Sel = IOMUXC_GPR_GPR1_SAI1_MCLK3_SEL_SHIFT, - kIOMUXC_GPR_SAI2MClk3Sel = IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL_SHIFT, - kIOMUXC_GPR_SAI3MClk3Sel = IOMUXC_GPR_GPR1_SAI3_MCLK3_SEL_SHIFT, + kIOMUXC_GPR_SAI1MClk3Sel = IOMUXC_GPR_GPR1_SAI1_MCLK3_SEL_SHIFT, + kIOMUXC_GPR_SAI2MClk3Sel = IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL_SHIFT, + kIOMUXC_GPR_SAI3MClk3Sel = IOMUXC_GPR_GPR1_SAI3_MCLK3_SEL_SHIFT, } iomuxc_gpr_saimclk_t; typedef enum _iomuxc_mqs_pwm_oversample_rate @@ -1315,11 +1317,9 @@ static inline void IOMUXC_SetPinConfig(uint32_t muxRegister, */ static inline void IOMUXC_EnableMode(IOMUXC_GPR_Type *base, uint32_t mode, bool enable) { - mode &= ~(IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL_MASK - | IOMUXC_GPR_GPR1_SAI1_MCLK2_SEL_MASK - | IOMUXC_GPR_GPR1_SAI1_MCLK3_SEL_MASK - | IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL_MASK - | IOMUXC_GPR_GPR1_SAI3_MCLK3_SEL_MASK); + mode &= ~(IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL_MASK | IOMUXC_GPR_GPR1_SAI1_MCLK2_SEL_MASK | + IOMUXC_GPR_GPR1_SAI1_MCLK3_SEL_MASK | IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL_MASK | + IOMUXC_GPR_GPR1_SAI3_MCLK3_SEL_MASK); if (enable) { @@ -1345,17 +1345,17 @@ static inline void IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR_Type *base, iomuxc_gp if (mclk > kIOMUXC_GPR_SAI1MClk2Sel) { gpr = base->GPR1 & ~(IOMUXC_GPR_SAIMCLK_HIGHBITMASK << mclk); - base->GPR1 = ((clkSrc & IOMUXC_GPR_SAIMCLK_HIGHBITMASK) << mclk) | gpr; + base->GPR1 = ((clkSrc & IOMUXC_GPR_SAIMCLK_HIGHBITMASK) << mclk) | gpr; } else { gpr = base->GPR1 & ~(IOMUXC_GPR_SAIMCLK_LOWBITMASK << mclk); - base->GPR1 = ((clkSrc & IOMUXC_GPR_SAIMCLK_LOWBITMASK) << mclk) | gpr; + base->GPR1 = ((clkSrc & IOMUXC_GPR_SAIMCLK_LOWBITMASK) << mclk) | gpr; } } /*! - * @brief Enters or exit MQS software reset. + * @brief Enters or exit MQS software reset. * * @param base The IOMUXC GPR base address. * @param enable Enter or exit MQS software reset. @@ -1364,17 +1364,16 @@ static inline void IOMUXC_MQSEnterSoftwareReset(IOMUXC_GPR_Type *base, bool enab { if (enable) { - base->GPR2 |= IOMUXC_GPR_GPR2_MQS_SW_RST_MASK; + base->GPR2 |= IOMUXC_GPR_GPR2_MQS_SW_RST_MASK; } else { - base->GPR2 &= ~IOMUXC_GPR_GPR2_MQS_SW_RST_MASK; + base->GPR2 &= ~IOMUXC_GPR_GPR2_MQS_SW_RST_MASK; } } - /*! - * @brief Enables or disables MQS. + * @brief Enables or disables MQS. * * @param base The IOMUXC GPR base address. * @param enable Enable or disable the MQS. @@ -1383,16 +1382,16 @@ static inline void IOMUXC_MQSEnable(IOMUXC_GPR_Type *base, bool enable) { if (enable) { - base->GPR2 |= IOMUXC_GPR_GPR2_MQS_EN_MASK; + base->GPR2 |= IOMUXC_GPR_GPR2_MQS_EN_MASK; } else { - base->GPR2 &= ~IOMUXC_GPR_GPR2_MQS_EN_MASK; + base->GPR2 &= ~IOMUXC_GPR_GPR2_MQS_EN_MASK; } } /*! - * @brief Configure MQS PWM oversampling rate compared with mclk and divider ratio control for mclk from hmclk. + * @brief Configure MQS PWM oversampling rate compared with mclk and divider ratio control for mclk from hmclk. * * @param base The IOMUXC GPR base address. * @param rate The MQS PWM oversampling rate, refer to "iomuxc_mqs_pwm_oversample_rate_t". @@ -1402,7 +1401,7 @@ static inline void IOMUXC_MQSEnable(IOMUXC_GPR_Type *base, bool enable) static inline void IOMUXC_MQSConfig(IOMUXC_GPR_Type *base, iomuxc_mqs_pwm_oversample_rate_t rate, uint8_t divider) { uint32_t gpr = base->GPR2 & ~(IOMUXC_GPR_GPR2_MQS_OVERSAMPLE_MASK | IOMUXC_GPR_GPR2_MQS_CLK_DIV_MASK); - + base->GPR2 = gpr | IOMUXC_GPR_GPR2_MQS_OVERSAMPLE(rate) | IOMUXC_GPR_GPR2_MQS_CLK_DIV(divider); } @@ -1415,4 +1414,3 @@ static inline void IOMUXC_MQSConfig(IOMUXC_GPR_Type *base, iomuxc_mqs_pwm_oversa /*! @}*/ #endif /* _FSL_IOMUXC_H_ */ - diff --git a/ext/hal/nxp/mcux/devices/MK64F12/MK64F12.h b/ext/hal/nxp/mcux/devices/MK64F12/MK64F12.h index 44cb790a096..0756881fc82 100644 --- a/ext/hal/nxp/mcux/devices/MK64F12/MK64F12.h +++ b/ext/hal/nxp/mcux/devices/MK64F12/MK64F12.h @@ -18,37 +18,15 @@ ** ** Reference manual: K64P144M120SF5RM, Rev.2, January 2014 ** Version: rev. 2.9, 2016-03-21 -** Build: b170112 +** Build: b180801 ** ** Abstract: ** CMSIS Peripheral Access Layer for MK64F12 ** -** Copyright (c) 1997 - 2016 Freescale Semiconductor, Inc. -** Copyright 2016 - 2017 NXP -** Redistribution and use in source and binary forms, with or without modification, -** are permitted provided that the following conditions are met: +** Copyright 1997-2016 Freescale Semiconductor, Inc. +** Copyright 2016-2018 NXP ** -** o Redistributions of source code must retain the above copyright notice, this list -** of conditions and the following disclaimer. -** -** o Redistributions in binary form must reproduce the above copyright notice, this -** list of conditions and the following disclaimer in the documentation and/or -** other materials provided with the distribution. -** -** o Neither the name of the copyright holder nor the names of its -** contributors may be used to endorse or promote products derived from this -** software without specific prior written permission. -** -** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** SPDX-License-Identifier: BSD-3-Clause ** ** http: www.nxp.com ** mail: support@nxp.com @@ -410,8 +388,12 @@ typedef enum _dma_request_source */ #if defined(__ARMCC_VERSION) - #pragma push - #pragma anon_unions + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #else + #pragma push + #pragma anon_unions + #endif #elif defined(__CWCC__) #pragma push #pragma cpp_extensions on @@ -472,195 +454,383 @@ typedef struct { */ /*! @name SC1 - ADC Status and Control Registers 1 */ +/*! @{ */ #define ADC_SC1_ADCH_MASK (0x1FU) #define ADC_SC1_ADCH_SHIFT (0U) +/*! ADCH - Input channel select + * 0b00000..When DIFF=0, DADP0 is selected as input; when DIFF=1, DAD0 is selected as input. + * 0b00001..When DIFF=0, DADP1 is selected as input; when DIFF=1, DAD1 is selected as input. + * 0b00010..When DIFF=0, DADP2 is selected as input; when DIFF=1, DAD2 is selected as input. + * 0b00011..When DIFF=0, DADP3 is selected as input; when DIFF=1, DAD3 is selected as input. + * 0b00100..When DIFF=0, AD4 is selected as input; when DIFF=1, it is reserved. + * 0b00101..When DIFF=0, AD5 is selected as input; when DIFF=1, it is reserved. + * 0b00110..When DIFF=0, AD6 is selected as input; when DIFF=1, it is reserved. + * 0b00111..When DIFF=0, AD7 is selected as input; when DIFF=1, it is reserved. + * 0b01000..When DIFF=0, AD8 is selected as input; when DIFF=1, it is reserved. + * 0b01001..When DIFF=0, AD9 is selected as input; when DIFF=1, it is reserved. + * 0b01010..When DIFF=0, AD10 is selected as input; when DIFF=1, it is reserved. + * 0b01011..When DIFF=0, AD11 is selected as input; when DIFF=1, it is reserved. + * 0b01100..When DIFF=0, AD12 is selected as input; when DIFF=1, it is reserved. + * 0b01101..When DIFF=0, AD13 is selected as input; when DIFF=1, it is reserved. + * 0b01110..When DIFF=0, AD14 is selected as input; when DIFF=1, it is reserved. + * 0b01111..When DIFF=0, AD15 is selected as input; when DIFF=1, it is reserved. + * 0b10000..When DIFF=0, AD16 is selected as input; when DIFF=1, it is reserved. + * 0b10001..When DIFF=0, AD17 is selected as input; when DIFF=1, it is reserved. + * 0b10010..When DIFF=0, AD18 is selected as input; when DIFF=1, it is reserved. + * 0b10011..When DIFF=0, AD19 is selected as input; when DIFF=1, it is reserved. + * 0b10100..When DIFF=0, AD20 is selected as input; when DIFF=1, it is reserved. + * 0b10101..When DIFF=0, AD21 is selected as input; when DIFF=1, it is reserved. + * 0b10110..When DIFF=0, AD22 is selected as input; when DIFF=1, it is reserved. + * 0b10111..When DIFF=0, AD23 is selected as input; when DIFF=1, it is reserved. + * 0b11000..Reserved. + * 0b11001..Reserved. + * 0b11010..When DIFF=0, Temp Sensor (single-ended) is selected as input; when DIFF=1, Temp Sensor (differential) is selected as input. + * 0b11011..When DIFF=0, Bandgap (single-ended) is selected as input; when DIFF=1, Bandgap (differential) is selected as input. + * 0b11100..Reserved. + * 0b11101..When DIFF=0,VREFSH is selected as input; when DIFF=1, -VREFSH (differential) is selected as input. Voltage reference selected is determined by SC2[REFSEL]. + * 0b11110..When DIFF=0,VREFSL is selected as input; when DIFF=1, it is reserved. Voltage reference selected is determined by SC2[REFSEL]. + * 0b11111..Module is disabled. + */ #define ADC_SC1_ADCH(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_ADCH_SHIFT)) & ADC_SC1_ADCH_MASK) #define ADC_SC1_DIFF_MASK (0x20U) #define ADC_SC1_DIFF_SHIFT (5U) +/*! DIFF - Differential Mode Enable + * 0b0..Single-ended conversions and input channels are selected. + * 0b1..Differential conversions and input channels are selected. + */ #define ADC_SC1_DIFF(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_DIFF_SHIFT)) & ADC_SC1_DIFF_MASK) #define ADC_SC1_AIEN_MASK (0x40U) #define ADC_SC1_AIEN_SHIFT (6U) +/*! AIEN - Interrupt Enable + * 0b0..Conversion complete interrupt is disabled. + * 0b1..Conversion complete interrupt is enabled. + */ #define ADC_SC1_AIEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_AIEN_SHIFT)) & ADC_SC1_AIEN_MASK) #define ADC_SC1_COCO_MASK (0x80U) #define ADC_SC1_COCO_SHIFT (7U) +/*! COCO - Conversion Complete Flag + * 0b0..Conversion is not completed. + * 0b1..Conversion is completed. + */ #define ADC_SC1_COCO(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_COCO_SHIFT)) & ADC_SC1_COCO_MASK) +/*! @} */ /* The count of ADC_SC1 */ #define ADC_SC1_COUNT (2U) /*! @name CFG1 - ADC Configuration Register 1 */ +/*! @{ */ #define ADC_CFG1_ADICLK_MASK (0x3U) #define ADC_CFG1_ADICLK_SHIFT (0U) +/*! ADICLK - Input Clock Select + * 0b00..Bus clock + * 0b01..Alternate clock 2 (ALTCLK2) + * 0b10..Alternate clock (ALTCLK) + * 0b11..Asynchronous clock (ADACK) + */ #define ADC_CFG1_ADICLK(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADICLK_SHIFT)) & ADC_CFG1_ADICLK_MASK) #define ADC_CFG1_MODE_MASK (0xCU) #define ADC_CFG1_MODE_SHIFT (2U) +/*! MODE - Conversion mode selection + * 0b00..When DIFF=0:It is single-ended 8-bit conversion; when DIFF=1, it is differential 9-bit conversion with 2's complement output. + * 0b01..When DIFF=0:It is single-ended 12-bit conversion ; when DIFF=1, it is differential 13-bit conversion with 2's complement output. + * 0b10..When DIFF=0:It is single-ended 10-bit conversion. ; when DIFF=1, it is differential 11-bit conversion with 2's complement output + * 0b11..When DIFF=0:It is single-ended 16-bit conversion..; when DIFF=1, it is differential 16-bit conversion with 2's complement output + */ #define ADC_CFG1_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_MODE_SHIFT)) & ADC_CFG1_MODE_MASK) #define ADC_CFG1_ADLSMP_MASK (0x10U) #define ADC_CFG1_ADLSMP_SHIFT (4U) +/*! ADLSMP - Sample Time Configuration + * 0b0..Short sample time. + * 0b1..Long sample time. + */ #define ADC_CFG1_ADLSMP(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADLSMP_SHIFT)) & ADC_CFG1_ADLSMP_MASK) #define ADC_CFG1_ADIV_MASK (0x60U) #define ADC_CFG1_ADIV_SHIFT (5U) +/*! ADIV - Clock Divide Select + * 0b00..The divide ratio is 1 and the clock rate is input clock. + * 0b01..The divide ratio is 2 and the clock rate is (input clock)/2. + * 0b10..The divide ratio is 4 and the clock rate is (input clock)/4. + * 0b11..The divide ratio is 8 and the clock rate is (input clock)/8. + */ #define ADC_CFG1_ADIV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADIV_SHIFT)) & ADC_CFG1_ADIV_MASK) #define ADC_CFG1_ADLPC_MASK (0x80U) #define ADC_CFG1_ADLPC_SHIFT (7U) +/*! ADLPC - Low-Power Configuration + * 0b0..Normal power configuration. + * 0b1..Low-power configuration. The power is reduced at the expense of maximum clock speed. + */ #define ADC_CFG1_ADLPC(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADLPC_SHIFT)) & ADC_CFG1_ADLPC_MASK) +/*! @} */ /*! @name CFG2 - ADC Configuration Register 2 */ +/*! @{ */ #define ADC_CFG2_ADLSTS_MASK (0x3U) #define ADC_CFG2_ADLSTS_SHIFT (0U) +/*! ADLSTS - Long Sample Time Select + * 0b00..Default longest sample time; 20 extra ADCK cycles; 24 ADCK cycles total. + * 0b01..12 extra ADCK cycles; 16 ADCK cycles total sample time. + * 0b10..6 extra ADCK cycles; 10 ADCK cycles total sample time. + * 0b11..2 extra ADCK cycles; 6 ADCK cycles total sample time. + */ #define ADC_CFG2_ADLSTS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_ADLSTS_SHIFT)) & ADC_CFG2_ADLSTS_MASK) #define ADC_CFG2_ADHSC_MASK (0x4U) #define ADC_CFG2_ADHSC_SHIFT (2U) +/*! ADHSC - High-Speed Configuration + * 0b0..Normal conversion sequence selected. + * 0b1..High-speed conversion sequence selected with 2 additional ADCK cycles to total conversion time. + */ #define ADC_CFG2_ADHSC(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_ADHSC_SHIFT)) & ADC_CFG2_ADHSC_MASK) #define ADC_CFG2_ADACKEN_MASK (0x8U) #define ADC_CFG2_ADACKEN_SHIFT (3U) +/*! ADACKEN - Asynchronous Clock Output Enable + * 0b0..Asynchronous clock output disabled; Asynchronous clock is enabled only if selected by ADICLK and a conversion is active. + * 0b1..Asynchronous clock and clock output is enabled regardless of the state of the ADC. + */ #define ADC_CFG2_ADACKEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_ADACKEN_SHIFT)) & ADC_CFG2_ADACKEN_MASK) #define ADC_CFG2_MUXSEL_MASK (0x10U) #define ADC_CFG2_MUXSEL_SHIFT (4U) +/*! MUXSEL - ADC Mux Select + * 0b0..ADxxa channels are selected. + * 0b1..ADxxb channels are selected. + */ #define ADC_CFG2_MUXSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_MUXSEL_SHIFT)) & ADC_CFG2_MUXSEL_MASK) +/*! @} */ /*! @name R - ADC Data Result Register */ +/*! @{ */ #define ADC_R_D_MASK (0xFFFFU) #define ADC_R_D_SHIFT (0U) #define ADC_R_D(x) (((uint32_t)(((uint32_t)(x)) << ADC_R_D_SHIFT)) & ADC_R_D_MASK) +/*! @} */ /* The count of ADC_R */ #define ADC_R_COUNT (2U) /*! @name CV1 - Compare Value Registers */ +/*! @{ */ #define ADC_CV1_CV_MASK (0xFFFFU) #define ADC_CV1_CV_SHIFT (0U) #define ADC_CV1_CV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV1_CV_SHIFT)) & ADC_CV1_CV_MASK) +/*! @} */ /*! @name CV2 - Compare Value Registers */ +/*! @{ */ #define ADC_CV2_CV_MASK (0xFFFFU) #define ADC_CV2_CV_SHIFT (0U) #define ADC_CV2_CV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV2_CV_SHIFT)) & ADC_CV2_CV_MASK) +/*! @} */ /*! @name SC2 - Status and Control Register 2 */ +/*! @{ */ #define ADC_SC2_REFSEL_MASK (0x3U) #define ADC_SC2_REFSEL_SHIFT (0U) +/*! REFSEL - Voltage Reference Selection + * 0b00..Default voltage reference pin pair, that is, external pins VREFH and VREFL + * 0b01..Alternate reference pair, that is, VALTH and VALTL . This pair may be additional external pins or internal sources depending on the MCU configuration. See the chip configuration information for details specific to this MCU + * 0b10..Reserved + * 0b11..Reserved + */ #define ADC_SC2_REFSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_REFSEL_SHIFT)) & ADC_SC2_REFSEL_MASK) #define ADC_SC2_DMAEN_MASK (0x4U) #define ADC_SC2_DMAEN_SHIFT (2U) +/*! DMAEN - DMA Enable + * 0b0..DMA is disabled. + * 0b1..DMA is enabled and will assert the ADC DMA request during an ADC conversion complete event noted when any of the SC1n[COCO] flags is asserted. + */ #define ADC_SC2_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_DMAEN_SHIFT)) & ADC_SC2_DMAEN_MASK) #define ADC_SC2_ACREN_MASK (0x8U) #define ADC_SC2_ACREN_SHIFT (3U) +/*! ACREN - Compare Function Range Enable + * 0b0..Range function disabled. Only CV1 is compared. + * 0b1..Range function enabled. Both CV1 and CV2 are compared. + */ #define ADC_SC2_ACREN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACREN_SHIFT)) & ADC_SC2_ACREN_MASK) #define ADC_SC2_ACFGT_MASK (0x10U) #define ADC_SC2_ACFGT_SHIFT (4U) +/*! ACFGT - Compare Function Greater Than Enable + * 0b0..Configures less than threshold, outside range not inclusive and inside range not inclusive; functionality based on the values placed in CV1 and CV2. + * 0b1..Configures greater than or equal to threshold, outside and inside ranges inclusive; functionality based on the values placed in CV1 and CV2. + */ #define ADC_SC2_ACFGT(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACFGT_SHIFT)) & ADC_SC2_ACFGT_MASK) #define ADC_SC2_ACFE_MASK (0x20U) #define ADC_SC2_ACFE_SHIFT (5U) +/*! ACFE - Compare Function Enable + * 0b0..Compare function disabled. + * 0b1..Compare function enabled. + */ #define ADC_SC2_ACFE(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACFE_SHIFT)) & ADC_SC2_ACFE_MASK) #define ADC_SC2_ADTRG_MASK (0x40U) #define ADC_SC2_ADTRG_SHIFT (6U) +/*! ADTRG - Conversion Trigger Select + * 0b0..Software trigger selected. + * 0b1..Hardware trigger selected. + */ #define ADC_SC2_ADTRG(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ADTRG_SHIFT)) & ADC_SC2_ADTRG_MASK) #define ADC_SC2_ADACT_MASK (0x80U) #define ADC_SC2_ADACT_SHIFT (7U) +/*! ADACT - Conversion Active + * 0b0..Conversion not in progress. + * 0b1..Conversion in progress. + */ #define ADC_SC2_ADACT(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ADACT_SHIFT)) & ADC_SC2_ADACT_MASK) +/*! @} */ /*! @name SC3 - Status and Control Register 3 */ +/*! @{ */ #define ADC_SC3_AVGS_MASK (0x3U) #define ADC_SC3_AVGS_SHIFT (0U) +/*! AVGS - Hardware Average Select + * 0b00..4 samples averaged. + * 0b01..8 samples averaged. + * 0b10..16 samples averaged. + * 0b11..32 samples averaged. + */ #define ADC_SC3_AVGS(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_AVGS_SHIFT)) & ADC_SC3_AVGS_MASK) #define ADC_SC3_AVGE_MASK (0x4U) #define ADC_SC3_AVGE_SHIFT (2U) +/*! AVGE - Hardware Average Enable + * 0b0..Hardware average function disabled. + * 0b1..Hardware average function enabled. + */ #define ADC_SC3_AVGE(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_AVGE_SHIFT)) & ADC_SC3_AVGE_MASK) #define ADC_SC3_ADCO_MASK (0x8U) #define ADC_SC3_ADCO_SHIFT (3U) +/*! ADCO - Continuous Conversion Enable + * 0b0..One conversion or one set of conversions if the hardware average function is enabled, that is, AVGE=1, after initiating a conversion. + * 0b1..Continuous conversions or sets of conversions if the hardware average function is enabled, that is, AVGE=1, after initiating a conversion. + */ #define ADC_SC3_ADCO(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_ADCO_SHIFT)) & ADC_SC3_ADCO_MASK) #define ADC_SC3_CALF_MASK (0x40U) #define ADC_SC3_CALF_SHIFT (6U) +/*! CALF - Calibration Failed Flag + * 0b0..Calibration completed normally. + * 0b1..Calibration failed. ADC accuracy specifications are not guaranteed. + */ #define ADC_SC3_CALF(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_CALF_SHIFT)) & ADC_SC3_CALF_MASK) #define ADC_SC3_CAL_MASK (0x80U) #define ADC_SC3_CAL_SHIFT (7U) #define ADC_SC3_CAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_CAL_SHIFT)) & ADC_SC3_CAL_MASK) +/*! @} */ /*! @name OFS - ADC Offset Correction Register */ +/*! @{ */ #define ADC_OFS_OFS_MASK (0xFFFFU) #define ADC_OFS_OFS_SHIFT (0U) #define ADC_OFS_OFS(x) (((uint32_t)(((uint32_t)(x)) << ADC_OFS_OFS_SHIFT)) & ADC_OFS_OFS_MASK) +/*! @} */ /*! @name PG - ADC Plus-Side Gain Register */ +/*! @{ */ #define ADC_PG_PG_MASK (0xFFFFU) #define ADC_PG_PG_SHIFT (0U) #define ADC_PG_PG(x) (((uint32_t)(((uint32_t)(x)) << ADC_PG_PG_SHIFT)) & ADC_PG_PG_MASK) +/*! @} */ /*! @name MG - ADC Minus-Side Gain Register */ +/*! @{ */ #define ADC_MG_MG_MASK (0xFFFFU) #define ADC_MG_MG_SHIFT (0U) #define ADC_MG_MG(x) (((uint32_t)(((uint32_t)(x)) << ADC_MG_MG_SHIFT)) & ADC_MG_MG_MASK) +/*! @} */ /*! @name CLPD - ADC Plus-Side General Calibration Value Register */ +/*! @{ */ #define ADC_CLPD_CLPD_MASK (0x3FU) #define ADC_CLPD_CLPD_SHIFT (0U) #define ADC_CLPD_CLPD(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLPD_CLPD_SHIFT)) & ADC_CLPD_CLPD_MASK) +/*! @} */ /*! @name CLPS - ADC Plus-Side General Calibration Value Register */ +/*! @{ */ #define ADC_CLPS_CLPS_MASK (0x3FU) #define ADC_CLPS_CLPS_SHIFT (0U) #define ADC_CLPS_CLPS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLPS_CLPS_SHIFT)) & ADC_CLPS_CLPS_MASK) +/*! @} */ /*! @name CLP4 - ADC Plus-Side General Calibration Value Register */ +/*! @{ */ #define ADC_CLP4_CLP4_MASK (0x3FFU) #define ADC_CLP4_CLP4_SHIFT (0U) #define ADC_CLP4_CLP4(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP4_CLP4_SHIFT)) & ADC_CLP4_CLP4_MASK) +/*! @} */ /*! @name CLP3 - ADC Plus-Side General Calibration Value Register */ +/*! @{ */ #define ADC_CLP3_CLP3_MASK (0x1FFU) #define ADC_CLP3_CLP3_SHIFT (0U) #define ADC_CLP3_CLP3(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP3_CLP3_SHIFT)) & ADC_CLP3_CLP3_MASK) +/*! @} */ /*! @name CLP2 - ADC Plus-Side General Calibration Value Register */ +/*! @{ */ #define ADC_CLP2_CLP2_MASK (0xFFU) #define ADC_CLP2_CLP2_SHIFT (0U) #define ADC_CLP2_CLP2(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP2_CLP2_SHIFT)) & ADC_CLP2_CLP2_MASK) +/*! @} */ /*! @name CLP1 - ADC Plus-Side General Calibration Value Register */ +/*! @{ */ #define ADC_CLP1_CLP1_MASK (0x7FU) #define ADC_CLP1_CLP1_SHIFT (0U) #define ADC_CLP1_CLP1(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP1_CLP1_SHIFT)) & ADC_CLP1_CLP1_MASK) +/*! @} */ /*! @name CLP0 - ADC Plus-Side General Calibration Value Register */ +/*! @{ */ #define ADC_CLP0_CLP0_MASK (0x3FU) #define ADC_CLP0_CLP0_SHIFT (0U) #define ADC_CLP0_CLP0(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP0_CLP0_SHIFT)) & ADC_CLP0_CLP0_MASK) +/*! @} */ /*! @name CLMD - ADC Minus-Side General Calibration Value Register */ +/*! @{ */ #define ADC_CLMD_CLMD_MASK (0x3FU) #define ADC_CLMD_CLMD_SHIFT (0U) #define ADC_CLMD_CLMD(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLMD_CLMD_SHIFT)) & ADC_CLMD_CLMD_MASK) +/*! @} */ /*! @name CLMS - ADC Minus-Side General Calibration Value Register */ +/*! @{ */ #define ADC_CLMS_CLMS_MASK (0x3FU) #define ADC_CLMS_CLMS_SHIFT (0U) #define ADC_CLMS_CLMS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLMS_CLMS_SHIFT)) & ADC_CLMS_CLMS_MASK) +/*! @} */ /*! @name CLM4 - ADC Minus-Side General Calibration Value Register */ +/*! @{ */ #define ADC_CLM4_CLM4_MASK (0x3FFU) #define ADC_CLM4_CLM4_SHIFT (0U) #define ADC_CLM4_CLM4(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM4_CLM4_SHIFT)) & ADC_CLM4_CLM4_MASK) +/*! @} */ /*! @name CLM3 - ADC Minus-Side General Calibration Value Register */ +/*! @{ */ #define ADC_CLM3_CLM3_MASK (0x1FFU) #define ADC_CLM3_CLM3_SHIFT (0U) #define ADC_CLM3_CLM3(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM3_CLM3_SHIFT)) & ADC_CLM3_CLM3_MASK) +/*! @} */ /*! @name CLM2 - ADC Minus-Side General Calibration Value Register */ +/*! @{ */ #define ADC_CLM2_CLM2_MASK (0xFFU) #define ADC_CLM2_CLM2_SHIFT (0U) #define ADC_CLM2_CLM2(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM2_CLM2_SHIFT)) & ADC_CLM2_CLM2_MASK) +/*! @} */ /*! @name CLM1 - ADC Minus-Side General Calibration Value Register */ +/*! @{ */ #define ADC_CLM1_CLM1_MASK (0x7FU) #define ADC_CLM1_CLM1_SHIFT (0U) #define ADC_CLM1_CLM1(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM1_CLM1_SHIFT)) & ADC_CLM1_CLM1_MASK) +/*! @} */ /*! @name CLM0 - ADC Minus-Side General Calibration Value Register */ +/*! @{ */ #define ADC_CLM0_CLM0_MASK (0x3FU) #define ADC_CLM0_CLM0_SHIFT (0U) #define ADC_CLM0_CLM0(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM0_CLM0_SHIFT)) & ADC_CLM0_CLM0_MASK) +/*! @} */ /*! @@ -733,1264 +903,2932 @@ typedef struct { */ /*! @name MPRA - Master Privilege Register A */ +/*! @{ */ #define AIPS_MPRA_MPL5_MASK (0x100U) #define AIPS_MPRA_MPL5_SHIFT (8U) +/*! MPL5 - Master 5 Privilege Level + * 0b0..Accesses from this master are forced to user-mode. + * 0b1..Accesses from this master are not forced to user-mode. + */ #define AIPS_MPRA_MPL5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL5_SHIFT)) & AIPS_MPRA_MPL5_MASK) #define AIPS_MPRA_MTW5_MASK (0x200U) #define AIPS_MPRA_MTW5_SHIFT (9U) +/*! MTW5 - Master 5 Trusted For Writes + * 0b0..This master is not trusted for write accesses. + * 0b1..This master is trusted for write accesses. + */ #define AIPS_MPRA_MTW5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW5_SHIFT)) & AIPS_MPRA_MTW5_MASK) #define AIPS_MPRA_MTR5_MASK (0x400U) #define AIPS_MPRA_MTR5_SHIFT (10U) +/*! MTR5 - Master 5 Trusted For Read + * 0b0..This master is not trusted for read accesses. + * 0b1..This master is trusted for read accesses. + */ #define AIPS_MPRA_MTR5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR5_SHIFT)) & AIPS_MPRA_MTR5_MASK) #define AIPS_MPRA_MPL4_MASK (0x1000U) #define AIPS_MPRA_MPL4_SHIFT (12U) +/*! MPL4 - Master 4 Privilege Level + * 0b0..Accesses from this master are forced to user-mode. + * 0b1..Accesses from this master are not forced to user-mode. + */ #define AIPS_MPRA_MPL4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL4_SHIFT)) & AIPS_MPRA_MPL4_MASK) #define AIPS_MPRA_MTW4_MASK (0x2000U) #define AIPS_MPRA_MTW4_SHIFT (13U) +/*! MTW4 - Master 4 Trusted For Writes + * 0b0..This master is not trusted for write accesses. + * 0b1..This master is trusted for write accesses. + */ #define AIPS_MPRA_MTW4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW4_SHIFT)) & AIPS_MPRA_MTW4_MASK) #define AIPS_MPRA_MTR4_MASK (0x4000U) #define AIPS_MPRA_MTR4_SHIFT (14U) +/*! MTR4 - Master 4 Trusted For Read + * 0b0..This master is not trusted for read accesses. + * 0b1..This master is trusted for read accesses. + */ #define AIPS_MPRA_MTR4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR4_SHIFT)) & AIPS_MPRA_MTR4_MASK) #define AIPS_MPRA_MPL3_MASK (0x10000U) #define AIPS_MPRA_MPL3_SHIFT (16U) +/*! MPL3 - Master 3 Privilege Level + * 0b0..Accesses from this master are forced to user-mode. + * 0b1..Accesses from this master are not forced to user-mode. + */ #define AIPS_MPRA_MPL3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL3_SHIFT)) & AIPS_MPRA_MPL3_MASK) #define AIPS_MPRA_MTW3_MASK (0x20000U) #define AIPS_MPRA_MTW3_SHIFT (17U) +/*! MTW3 - Master 3 Trusted For Writes + * 0b0..This master is not trusted for write accesses. + * 0b1..This master is trusted for write accesses. + */ #define AIPS_MPRA_MTW3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW3_SHIFT)) & AIPS_MPRA_MTW3_MASK) #define AIPS_MPRA_MTR3_MASK (0x40000U) #define AIPS_MPRA_MTR3_SHIFT (18U) +/*! MTR3 - Master 3 Trusted For Read + * 0b0..This master is not trusted for read accesses. + * 0b1..This master is trusted for read accesses. + */ #define AIPS_MPRA_MTR3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR3_SHIFT)) & AIPS_MPRA_MTR3_MASK) #define AIPS_MPRA_MPL2_MASK (0x100000U) #define AIPS_MPRA_MPL2_SHIFT (20U) +/*! MPL2 - Master 2 Privilege Level + * 0b0..Accesses from this master are forced to user-mode. + * 0b1..Accesses from this master are not forced to user-mode. + */ #define AIPS_MPRA_MPL2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL2_SHIFT)) & AIPS_MPRA_MPL2_MASK) #define AIPS_MPRA_MTW2_MASK (0x200000U) #define AIPS_MPRA_MTW2_SHIFT (21U) +/*! MTW2 - Master 2 Trusted For Writes + * 0b0..This master is not trusted for write accesses. + * 0b1..This master is trusted for write accesses. + */ #define AIPS_MPRA_MTW2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW2_SHIFT)) & AIPS_MPRA_MTW2_MASK) #define AIPS_MPRA_MTR2_MASK (0x400000U) #define AIPS_MPRA_MTR2_SHIFT (22U) +/*! MTR2 - Master 2 Trusted For Read + * 0b0..This master is not trusted for read accesses. + * 0b1..This master is trusted for read accesses. + */ #define AIPS_MPRA_MTR2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR2_SHIFT)) & AIPS_MPRA_MTR2_MASK) #define AIPS_MPRA_MPL1_MASK (0x1000000U) #define AIPS_MPRA_MPL1_SHIFT (24U) +/*! MPL1 - Master 1 Privilege Level + * 0b0..Accesses from this master are forced to user-mode. + * 0b1..Accesses from this master are not forced to user-mode. + */ #define AIPS_MPRA_MPL1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL1_SHIFT)) & AIPS_MPRA_MPL1_MASK) #define AIPS_MPRA_MTW1_MASK (0x2000000U) #define AIPS_MPRA_MTW1_SHIFT (25U) +/*! MTW1 - Master 1 Trusted for Writes + * 0b0..This master is not trusted for write accesses. + * 0b1..This master is trusted for write accesses. + */ #define AIPS_MPRA_MTW1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW1_SHIFT)) & AIPS_MPRA_MTW1_MASK) #define AIPS_MPRA_MTR1_MASK (0x4000000U) #define AIPS_MPRA_MTR1_SHIFT (26U) +/*! MTR1 - Master 1 Trusted for Read + * 0b0..This master is not trusted for read accesses. + * 0b1..This master is trusted for read accesses. + */ #define AIPS_MPRA_MTR1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR1_SHIFT)) & AIPS_MPRA_MTR1_MASK) #define AIPS_MPRA_MPL0_MASK (0x10000000U) #define AIPS_MPRA_MPL0_SHIFT (28U) +/*! MPL0 - Master 0 Privilege Level + * 0b0..Accesses from this master are forced to user-mode. + * 0b1..Accesses from this master are not forced to user-mode. + */ #define AIPS_MPRA_MPL0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL0_SHIFT)) & AIPS_MPRA_MPL0_MASK) #define AIPS_MPRA_MTW0_MASK (0x20000000U) #define AIPS_MPRA_MTW0_SHIFT (29U) +/*! MTW0 - Master 0 Trusted For Writes + * 0b0..This master is not trusted for write accesses. + * 0b1..This master is trusted for write accesses. + */ #define AIPS_MPRA_MTW0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW0_SHIFT)) & AIPS_MPRA_MTW0_MASK) #define AIPS_MPRA_MTR0_MASK (0x40000000U) #define AIPS_MPRA_MTR0_SHIFT (30U) +/*! MTR0 - Master 0 Trusted For Read + * 0b0..This master is not trusted for read accesses. + * 0b1..This master is trusted for read accesses. + */ #define AIPS_MPRA_MTR0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR0_SHIFT)) & AIPS_MPRA_MTR0_MASK) +/*! @} */ /*! @name PACRA - Peripheral Access Control Register */ +/*! @{ */ #define AIPS_PACRA_TP7_MASK (0x1U) #define AIPS_PACRA_TP7_SHIFT (0U) +/*! TP7 - Trusted Protect + * 0b0..Accesses from an untrusted master are allowed. + * 0b1..Accesses from an untrusted master are not allowed. + */ #define AIPS_PACRA_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP7_SHIFT)) & AIPS_PACRA_TP7_MASK) #define AIPS_PACRA_WP7_MASK (0x2U) #define AIPS_PACRA_WP7_SHIFT (1U) +/*! WP7 - Write Protect + * 0b0..This peripheral allows write accesses. + * 0b1..This peripheral is write protected. + */ #define AIPS_PACRA_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP7_SHIFT)) & AIPS_PACRA_WP7_MASK) #define AIPS_PACRA_SP7_MASK (0x4U) #define AIPS_PACRA_SP7_SHIFT (2U) +/*! SP7 - Supervisor Protect + * 0b0..This peripheral does not require supervisor privilege level for accesses. + * 0b1..This peripheral requires supervisor privilege level for accesses. + */ #define AIPS_PACRA_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP7_SHIFT)) & AIPS_PACRA_SP7_MASK) #define AIPS_PACRA_TP6_MASK (0x10U) #define AIPS_PACRA_TP6_SHIFT (4U) +/*! TP6 - Trusted Protect + * 0b0..Accesses from an untrusted master are allowed. + * 0b1..Accesses from an untrusted master are not allowed. + */ #define AIPS_PACRA_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP6_SHIFT)) & AIPS_PACRA_TP6_MASK) #define AIPS_PACRA_WP6_MASK (0x20U) #define AIPS_PACRA_WP6_SHIFT (5U) +/*! WP6 - Write Protect + * 0b0..This peripheral allows write accesses. + * 0b1..This peripheral is write protected. + */ #define AIPS_PACRA_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP6_SHIFT)) & AIPS_PACRA_WP6_MASK) #define AIPS_PACRA_SP6_MASK (0x40U) #define AIPS_PACRA_SP6_SHIFT (6U) +/*! SP6 - Supervisor Protect + * 0b0..This peripheral does not require supervisor privilege level for accesses. + * 0b1..This peripheral requires supervisor privilege level for accesses. + */ #define AIPS_PACRA_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP6_SHIFT)) & AIPS_PACRA_SP6_MASK) #define AIPS_PACRA_TP5_MASK (0x100U) #define AIPS_PACRA_TP5_SHIFT (8U) +/*! TP5 - Trusted Protect + * 0b0..Accesses from an untrusted master are allowed. + * 0b1..Accesses from an untrusted master are not allowed. + */ #define AIPS_PACRA_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP5_SHIFT)) & AIPS_PACRA_TP5_MASK) #define AIPS_PACRA_WP5_MASK (0x200U) #define AIPS_PACRA_WP5_SHIFT (9U) +/*! WP5 - Write Protect + * 0b0..This peripheral allows write accesses. + * 0b1..This peripheral is write protected. + */ #define AIPS_PACRA_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP5_SHIFT)) & AIPS_PACRA_WP5_MASK) #define AIPS_PACRA_SP5_MASK (0x400U) #define AIPS_PACRA_SP5_SHIFT (10U) +/*! SP5 - Supervisor Protect + * 0b0..This peripheral does not require supervisor privilege level for accesses. + * 0b1..This peripheral requires supervisor privilege level for accesses. + */ #define AIPS_PACRA_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP5_SHIFT)) & AIPS_PACRA_SP5_MASK) #define AIPS_PACRA_TP4_MASK (0x1000U) #define AIPS_PACRA_TP4_SHIFT (12U) +/*! TP4 - Trusted Protect + * 0b0..Accesses from an untrusted master are allowed. + * 0b1..Accesses from an untrusted master are not allowed. + */ #define AIPS_PACRA_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP4_SHIFT)) & AIPS_PACRA_TP4_MASK) #define AIPS_PACRA_WP4_MASK (0x2000U) #define AIPS_PACRA_WP4_SHIFT (13U) +/*! WP4 - Write Protect + * 0b0..This peripheral allows write accesses. + * 0b1..This peripheral is write protected. + */ #define AIPS_PACRA_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP4_SHIFT)) & AIPS_PACRA_WP4_MASK) #define AIPS_PACRA_SP4_MASK (0x4000U) #define AIPS_PACRA_SP4_SHIFT (14U) +/*! SP4 - Supervisor Protect + * 0b0..This peripheral does not require supervisor privilege level for accesses. + * 0b1..This peripheral requires supervisor privilege level for accesses. + */ #define AIPS_PACRA_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP4_SHIFT)) & AIPS_PACRA_SP4_MASK) #define AIPS_PACRA_TP3_MASK (0x10000U) #define AIPS_PACRA_TP3_SHIFT (16U) +/*! TP3 - Trusted Protect + * 0b0..Accesses from an untrusted master are allowed. + * 0b1..Accesses from an untrusted master are not allowed. + */ #define AIPS_PACRA_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP3_SHIFT)) & AIPS_PACRA_TP3_MASK) #define AIPS_PACRA_WP3_MASK (0x20000U) #define AIPS_PACRA_WP3_SHIFT (17U) +/*! WP3 - Write Protect + * 0b0..This peripheral allows write accesses. + * 0b1..This peripheral is write protected. + */ #define AIPS_PACRA_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP3_SHIFT)) & AIPS_PACRA_WP3_MASK) #define AIPS_PACRA_SP3_MASK (0x40000U) #define AIPS_PACRA_SP3_SHIFT (18U) +/*! SP3 - Supervisor Protect + * 0b0..This peripheral does not require supervisor privilege level for accesses. + * 0b1..This peripheral requires supervisor privilege level for accesses. + */ #define AIPS_PACRA_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP3_SHIFT)) & AIPS_PACRA_SP3_MASK) #define AIPS_PACRA_TP2_MASK (0x100000U) #define AIPS_PACRA_TP2_SHIFT (20U) +/*! TP2 - Trusted Protect + * 0b0..Accesses from an untrusted master are allowed. + * 0b1..Accesses from an untrusted master are not allowed. + */ #define AIPS_PACRA_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP2_SHIFT)) & AIPS_PACRA_TP2_MASK) #define AIPS_PACRA_WP2_MASK (0x200000U) #define AIPS_PACRA_WP2_SHIFT (21U) +/*! WP2 - Write Protect + * 0b0..This peripheral allows write accesses. + * 0b1..This peripheral is write protected. + */ #define AIPS_PACRA_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP2_SHIFT)) & AIPS_PACRA_WP2_MASK) #define AIPS_PACRA_SP2_MASK (0x400000U) #define AIPS_PACRA_SP2_SHIFT (22U) +/*! SP2 - Supervisor Protect + * 0b0..This peripheral does not require supervisor privilege level for accesses. + * 0b1..This peripheral requires supervisor privilege level for accesses. + */ #define AIPS_PACRA_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP2_SHIFT)) & AIPS_PACRA_SP2_MASK) #define AIPS_PACRA_TP1_MASK (0x1000000U) #define AIPS_PACRA_TP1_SHIFT (24U) +/*! TP1 - Trusted Protect + * 0b0..Accesses from an untrusted master are allowed. + * 0b1..Accesses from an untrusted master are not allowed. + */ #define AIPS_PACRA_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP1_SHIFT)) & AIPS_PACRA_TP1_MASK) #define AIPS_PACRA_WP1_MASK (0x2000000U) #define AIPS_PACRA_WP1_SHIFT (25U) +/*! WP1 - Write Protect + * 0b0..This peripheral allows write accesses. + * 0b1..This peripheral is write protected. + */ #define AIPS_PACRA_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP1_SHIFT)) & AIPS_PACRA_WP1_MASK) #define AIPS_PACRA_SP1_MASK (0x4000000U) #define AIPS_PACRA_SP1_SHIFT (26U) +/*! SP1 - Supervisor Protect + * 0b0..This peripheral does not require supervisor privilege level for accesses. + * 0b1..This peripheral requires supervisor privilege level for accesses. + */ #define AIPS_PACRA_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP1_SHIFT)) & AIPS_PACRA_SP1_MASK) #define AIPS_PACRA_TP0_MASK (0x10000000U) #define AIPS_PACRA_TP0_SHIFT (28U) +/*! TP0 - Trusted Protect + * 0b0..Accesses from an untrusted master are allowed. + * 0b1..Accesses from an untrusted master are not allowed. + */ #define AIPS_PACRA_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP0_SHIFT)) & AIPS_PACRA_TP0_MASK) #define AIPS_PACRA_WP0_MASK (0x20000000U) #define AIPS_PACRA_WP0_SHIFT (29U) +/*! WP0 - Write Protect + * 0b0..This peripheral allows write accesses. + * 0b1..This peripheral is write protected. + */ #define AIPS_PACRA_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP0_SHIFT)) & AIPS_PACRA_WP0_MASK) #define AIPS_PACRA_SP0_MASK (0x40000000U) #define AIPS_PACRA_SP0_SHIFT (30U) +/*! SP0 - Supervisor Protect + * 0b0..This peripheral does not require supervisor privilege level for accesses. + * 0b1..This peripheral requires supervisor privilege level for accesses. + */ #define AIPS_PACRA_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP0_SHIFT)) & AIPS_PACRA_SP0_MASK) +/*! @} */ /*! @name PACRB - Peripheral Access Control Register */ +/*! @{ */ #define AIPS_PACRB_TP7_MASK (0x1U) #define AIPS_PACRB_TP7_SHIFT (0U) +/*! TP7 - Trusted Protect + * 0b0..Accesses from an untrusted master are allowed. + * 0b1..Accesses from an untrusted master are not allowed. + */ #define AIPS_PACRB_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP7_SHIFT)) & AIPS_PACRB_TP7_MASK) #define AIPS_PACRB_WP7_MASK (0x2U) #define AIPS_PACRB_WP7_SHIFT (1U) +/*! WP7 - Write Protect + * 0b0..This peripheral allows write accesses. + * 0b1..This peripheral is write protected. + */ #define AIPS_PACRB_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP7_SHIFT)) & AIPS_PACRB_WP7_MASK) #define AIPS_PACRB_SP7_MASK (0x4U) #define AIPS_PACRB_SP7_SHIFT (2U) +/*! SP7 - Supervisor Protect + * 0b0..This peripheral does not require supervisor privilege level for accesses. + * 0b1..This peripheral requires supervisor privilege level for accesses. + */ #define AIPS_PACRB_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP7_SHIFT)) & AIPS_PACRB_SP7_MASK) #define AIPS_PACRB_TP6_MASK (0x10U) #define AIPS_PACRB_TP6_SHIFT (4U) +/*! TP6 - Trusted Protect + * 0b0..Accesses from an untrusted master are allowed. + * 0b1..Accesses from an untrusted master are not allowed. + */ #define AIPS_PACRB_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP6_SHIFT)) & AIPS_PACRB_TP6_MASK) #define AIPS_PACRB_WP6_MASK (0x20U) #define AIPS_PACRB_WP6_SHIFT (5U) +/*! WP6 - Write Protect + * 0b0..This peripheral allows write accesses. + * 0b1..This peripheral is write protected. + */ #define AIPS_PACRB_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP6_SHIFT)) & AIPS_PACRB_WP6_MASK) #define AIPS_PACRB_SP6_MASK (0x40U) #define AIPS_PACRB_SP6_SHIFT (6U) +/*! SP6 - Supervisor Protect + * 0b0..This peripheral does not require supervisor privilege level for accesses. + * 0b1..This peripheral requires supervisor privilege level for accesses. + */ #define AIPS_PACRB_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP6_SHIFT)) & AIPS_PACRB_SP6_MASK) #define AIPS_PACRB_TP5_MASK (0x100U) #define AIPS_PACRB_TP5_SHIFT (8U) +/*! TP5 - Trusted Protect + * 0b0..Accesses from an untrusted master are allowed. + * 0b1..Accesses from an untrusted master are not allowed. + */ #define AIPS_PACRB_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP5_SHIFT)) & AIPS_PACRB_TP5_MASK) #define AIPS_PACRB_WP5_MASK (0x200U) #define AIPS_PACRB_WP5_SHIFT (9U) +/*! WP5 - Write Protect + * 0b0..This peripheral allows write accesses. + * 0b1..This peripheral is write protected. + */ #define AIPS_PACRB_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP5_SHIFT)) & AIPS_PACRB_WP5_MASK) #define AIPS_PACRB_SP5_MASK (0x400U) #define AIPS_PACRB_SP5_SHIFT (10U) +/*! SP5 - Supervisor Protect + * 0b0..This peripheral does not require supervisor privilege level for accesses. + * 0b1..This peripheral requires supervisor privilege level for accesses. + */ #define AIPS_PACRB_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP5_SHIFT)) & AIPS_PACRB_SP5_MASK) #define AIPS_PACRB_TP4_MASK (0x1000U) #define AIPS_PACRB_TP4_SHIFT (12U) +/*! TP4 - Trusted Protect + * 0b0..Accesses from an untrusted master are allowed. + * 0b1..Accesses from an untrusted master are not allowed. + */ #define AIPS_PACRB_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP4_SHIFT)) & AIPS_PACRB_TP4_MASK) #define AIPS_PACRB_WP4_MASK (0x2000U) #define AIPS_PACRB_WP4_SHIFT (13U) +/*! WP4 - Write Protect + * 0b0..This peripheral allows write accesses. + * 0b1..This peripheral is write protected. + */ #define AIPS_PACRB_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP4_SHIFT)) & AIPS_PACRB_WP4_MASK) #define AIPS_PACRB_SP4_MASK (0x4000U) #define AIPS_PACRB_SP4_SHIFT (14U) +/*! SP4 - Supervisor Protect + * 0b0..This peripheral does not require supervisor privilege level for accesses. + * 0b1..This peripheral requires supervisor privilege level for accesses. + */ #define AIPS_PACRB_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP4_SHIFT)) & AIPS_PACRB_SP4_MASK) #define AIPS_PACRB_TP3_MASK (0x10000U) #define AIPS_PACRB_TP3_SHIFT (16U) +/*! TP3 - Trusted Protect + * 0b0..Accesses from an untrusted master are allowed. + * 0b1..Accesses from an untrusted master are not allowed. + */ #define AIPS_PACRB_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP3_SHIFT)) & AIPS_PACRB_TP3_MASK) #define AIPS_PACRB_WP3_MASK (0x20000U) #define AIPS_PACRB_WP3_SHIFT (17U) +/*! WP3 - Write Protect + * 0b0..This peripheral allows write accesses. + * 0b1..This peripheral is write protected. + */ #define AIPS_PACRB_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP3_SHIFT)) & AIPS_PACRB_WP3_MASK) #define AIPS_PACRB_SP3_MASK (0x40000U) #define AIPS_PACRB_SP3_SHIFT (18U) +/*! SP3 - Supervisor Protect + * 0b0..This peripheral does not require supervisor privilege level for accesses. + * 0b1..This peripheral requires supervisor privilege level for accesses. + */ #define AIPS_PACRB_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP3_SHIFT)) & AIPS_PACRB_SP3_MASK) #define AIPS_PACRB_TP2_MASK (0x100000U) #define AIPS_PACRB_TP2_SHIFT (20U) +/*! TP2 - Trusted Protect + * 0b0..Accesses from an untrusted master are allowed. + * 0b1..Accesses from an untrusted master are not allowed. + */ #define AIPS_PACRB_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP2_SHIFT)) & AIPS_PACRB_TP2_MASK) #define AIPS_PACRB_WP2_MASK (0x200000U) #define AIPS_PACRB_WP2_SHIFT (21U) +/*! WP2 - Write Protect + * 0b0..This peripheral allows write accesses. + * 0b1..This peripheral is write protected. + */ #define AIPS_PACRB_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP2_SHIFT)) & AIPS_PACRB_WP2_MASK) #define AIPS_PACRB_SP2_MASK (0x400000U) #define AIPS_PACRB_SP2_SHIFT (22U) +/*! SP2 - Supervisor Protect + * 0b0..This peripheral does not require supervisor privilege level for accesses. + * 0b1..This peripheral requires supervisor privilege level for accesses. + */ #define AIPS_PACRB_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP2_SHIFT)) & AIPS_PACRB_SP2_MASK) #define AIPS_PACRB_TP1_MASK (0x1000000U) #define AIPS_PACRB_TP1_SHIFT (24U) +/*! TP1 - Trusted Protect + * 0b0..Accesses from an untrusted master are allowed. + * 0b1..Accesses from an untrusted master are not allowed. + */ #define AIPS_PACRB_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP1_SHIFT)) & AIPS_PACRB_TP1_MASK) #define AIPS_PACRB_WP1_MASK (0x2000000U) #define AIPS_PACRB_WP1_SHIFT (25U) +/*! WP1 - Write Protect + * 0b0..This peripheral allows write accesses. + * 0b1..This peripheral is write protected. + */ #define AIPS_PACRB_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP1_SHIFT)) & AIPS_PACRB_WP1_MASK) #define AIPS_PACRB_SP1_MASK (0x4000000U) #define AIPS_PACRB_SP1_SHIFT (26U) +/*! SP1 - Supervisor Protect + * 0b0..This peripheral does not require supervisor privilege level for accesses. + * 0b1..This peripheral requires supervisor privilege level for accesses. + */ #define AIPS_PACRB_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP1_SHIFT)) & AIPS_PACRB_SP1_MASK) #define AIPS_PACRB_TP0_MASK (0x10000000U) #define AIPS_PACRB_TP0_SHIFT (28U) +/*! TP0 - Trusted Protect + * 0b0..Accesses from an untrusted master are allowed. + * 0b1..Accesses from an untrusted master are not allowed. + */ #define AIPS_PACRB_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP0_SHIFT)) & AIPS_PACRB_TP0_MASK) #define AIPS_PACRB_WP0_MASK (0x20000000U) #define AIPS_PACRB_WP0_SHIFT (29U) +/*! WP0 - Write Protect + * 0b0..This peripheral allows write accesses. + * 0b1..This peripheral is write protected. + */ #define AIPS_PACRB_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP0_SHIFT)) & AIPS_PACRB_WP0_MASK) #define AIPS_PACRB_SP0_MASK (0x40000000U) #define AIPS_PACRB_SP0_SHIFT (30U) +/*! SP0 - Supervisor Protect + * 0b0..This peripheral does not require supervisor privilege level for accesses. + * 0b1..This peripheral requires supervisor privilege level for accesses. + */ #define AIPS_PACRB_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP0_SHIFT)) & AIPS_PACRB_SP0_MASK) +/*! @} */ /*! @name PACRC - Peripheral Access Control Register */ +/*! @{ */ #define AIPS_PACRC_TP7_MASK (0x1U) #define AIPS_PACRC_TP7_SHIFT (0U) +/*! TP7 - Trusted Protect + * 0b0..Accesses from an untrusted master are allowed. + * 0b1..Accesses from an untrusted master are not allowed. + */ #define AIPS_PACRC_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP7_SHIFT)) & AIPS_PACRC_TP7_MASK) #define AIPS_PACRC_WP7_MASK (0x2U) #define AIPS_PACRC_WP7_SHIFT (1U) +/*! WP7 - Write Protect + * 0b0..This peripheral allows write accesses. + * 0b1..This peripheral is write protected. + */ #define AIPS_PACRC_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP7_SHIFT)) & AIPS_PACRC_WP7_MASK) #define AIPS_PACRC_SP7_MASK (0x4U) #define AIPS_PACRC_SP7_SHIFT (2U) +/*! SP7 - Supervisor Protect + * 0b0..This peripheral does not require supervisor privilege level for accesses. + * 0b1..This peripheral requires supervisor privilege level for accesses. + */ #define AIPS_PACRC_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP7_SHIFT)) & AIPS_PACRC_SP7_MASK) #define AIPS_PACRC_TP6_MASK (0x10U) #define AIPS_PACRC_TP6_SHIFT (4U) +/*! TP6 - Trusted Protect + * 0b0..Accesses from an untrusted master are allowed. + * 0b1..Accesses from an untrusted master are not allowed. + */ #define AIPS_PACRC_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP6_SHIFT)) & AIPS_PACRC_TP6_MASK) #define AIPS_PACRC_WP6_MASK (0x20U) #define AIPS_PACRC_WP6_SHIFT (5U) +/*! WP6 - Write Protect + * 0b0..This peripheral allows write accesses. + * 0b1..This peripheral is write protected. + */ #define AIPS_PACRC_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP6_SHIFT)) & AIPS_PACRC_WP6_MASK) #define AIPS_PACRC_SP6_MASK (0x40U) #define AIPS_PACRC_SP6_SHIFT (6U) +/*! SP6 - Supervisor Protect + * 0b0..This peripheral does not require supervisor privilege level for accesses. + * 0b1..This peripheral requires supervisor privilege level for accesses. + */ #define AIPS_PACRC_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP6_SHIFT)) & AIPS_PACRC_SP6_MASK) #define AIPS_PACRC_TP5_MASK (0x100U) #define AIPS_PACRC_TP5_SHIFT (8U) +/*! TP5 - Trusted Protect + * 0b0..Accesses from an untrusted master are allowed. + * 0b1..Accesses from an untrusted master are not allowed. + */ #define AIPS_PACRC_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP5_SHIFT)) & AIPS_PACRC_TP5_MASK) #define AIPS_PACRC_WP5_MASK (0x200U) #define AIPS_PACRC_WP5_SHIFT (9U) +/*! WP5 - Write Protect + * 0b0..This peripheral allows write accesses. + * 0b1..This peripheral is write protected. + */ #define AIPS_PACRC_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP5_SHIFT)) & AIPS_PACRC_WP5_MASK) #define AIPS_PACRC_SP5_MASK (0x400U) #define AIPS_PACRC_SP5_SHIFT (10U) +/*! SP5 - Supervisor Protect + * 0b0..This peripheral does not require supervisor privilege level for accesses. + * 0b1..This peripheral requires supervisor privilege level for accesses. + */ #define AIPS_PACRC_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP5_SHIFT)) & AIPS_PACRC_SP5_MASK) #define AIPS_PACRC_TP4_MASK (0x1000U) #define AIPS_PACRC_TP4_SHIFT (12U) +/*! TP4 - Trusted Protect + * 0b0..Accesses from an untrusted master are allowed. + * 0b1..Accesses from an untrusted master are not allowed. + */ #define AIPS_PACRC_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP4_SHIFT)) & AIPS_PACRC_TP4_MASK) #define AIPS_PACRC_WP4_MASK (0x2000U) #define AIPS_PACRC_WP4_SHIFT (13U) +/*! WP4 - Write Protect + * 0b0..This peripheral allows write accesses. + * 0b1..This peripheral is write protected. + */ #define AIPS_PACRC_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP4_SHIFT)) & AIPS_PACRC_WP4_MASK) #define AIPS_PACRC_SP4_MASK (0x4000U) #define AIPS_PACRC_SP4_SHIFT (14U) +/*! SP4 - Supervisor Protect + * 0b0..This peripheral does not require supervisor privilege level for accesses. + * 0b1..This peripheral requires supervisor privilege level for accesses. + */ #define AIPS_PACRC_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP4_SHIFT)) & AIPS_PACRC_SP4_MASK) #define AIPS_PACRC_TP3_MASK (0x10000U) #define AIPS_PACRC_TP3_SHIFT (16U) +/*! TP3 - Trusted Protect + * 0b0..Accesses from an untrusted master are allowed. + * 0b1..Accesses from an untrusted master are not allowed. + */ #define AIPS_PACRC_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP3_SHIFT)) & AIPS_PACRC_TP3_MASK) #define AIPS_PACRC_WP3_MASK (0x20000U) #define AIPS_PACRC_WP3_SHIFT (17U) +/*! WP3 - Write Protect + * 0b0..This peripheral allows write accesses. + * 0b1..This peripheral is write protected. + */ #define AIPS_PACRC_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP3_SHIFT)) & AIPS_PACRC_WP3_MASK) #define AIPS_PACRC_SP3_MASK (0x40000U) #define AIPS_PACRC_SP3_SHIFT (18U) +/*! SP3 - Supervisor Protect + * 0b0..This peripheral does not require supervisor privilege level for accesses. + * 0b1..This peripheral requires supervisor privilege level for accesses. + */ #define AIPS_PACRC_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP3_SHIFT)) & AIPS_PACRC_SP3_MASK) #define AIPS_PACRC_TP2_MASK (0x100000U) #define AIPS_PACRC_TP2_SHIFT (20U) +/*! TP2 - Trusted Protect + * 0b0..Accesses from an untrusted master are allowed. + * 0b1..Accesses from an untrusted master are not allowed. + */ #define AIPS_PACRC_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP2_SHIFT)) & AIPS_PACRC_TP2_MASK) #define AIPS_PACRC_WP2_MASK (0x200000U) #define AIPS_PACRC_WP2_SHIFT (21U) +/*! WP2 - Write Protect + * 0b0..This peripheral allows write accesses. + * 0b1..This peripheral is write protected. + */ #define AIPS_PACRC_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP2_SHIFT)) & AIPS_PACRC_WP2_MASK) #define AIPS_PACRC_SP2_MASK (0x400000U) #define AIPS_PACRC_SP2_SHIFT (22U) +/*! SP2 - Supervisor Protect + * 0b0..This peripheral does not require supervisor privilege level for accesses. + * 0b1..This peripheral requires supervisor privilege level for accesses. + */ #define AIPS_PACRC_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP2_SHIFT)) & AIPS_PACRC_SP2_MASK) #define AIPS_PACRC_TP1_MASK (0x1000000U) #define AIPS_PACRC_TP1_SHIFT (24U) +/*! TP1 - Trusted Protect + * 0b0..Accesses from an untrusted master are allowed. + * 0b1..Accesses from an untrusted master are not allowed. + */ #define AIPS_PACRC_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP1_SHIFT)) & AIPS_PACRC_TP1_MASK) #define AIPS_PACRC_WP1_MASK (0x2000000U) #define AIPS_PACRC_WP1_SHIFT (25U) +/*! WP1 - Write Protect + * 0b0..This peripheral allows write accesses. + * 0b1..This peripheral is write protected. + */ #define AIPS_PACRC_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP1_SHIFT)) & AIPS_PACRC_WP1_MASK) #define AIPS_PACRC_SP1_MASK (0x4000000U) #define AIPS_PACRC_SP1_SHIFT (26U) +/*! SP1 - Supervisor Protect + * 0b0..This peripheral does not require supervisor privilege level for accesses. + * 0b1..This peripheral requires supervisor privilege level for accesses. + */ #define AIPS_PACRC_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP1_SHIFT)) & AIPS_PACRC_SP1_MASK) #define AIPS_PACRC_TP0_MASK (0x10000000U) #define AIPS_PACRC_TP0_SHIFT (28U) +/*! TP0 - Trusted Protect + * 0b0..Accesses from an untrusted master are allowed. + * 0b1..Accesses from an untrusted master are not allowed. + */ #define AIPS_PACRC_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP0_SHIFT)) & AIPS_PACRC_TP0_MASK) #define AIPS_PACRC_WP0_MASK (0x20000000U) #define AIPS_PACRC_WP0_SHIFT (29U) +/*! WP0 - Write Protect + * 0b0..This peripheral allows write accesses. + * 0b1..This peripheral is write protected. + */ #define AIPS_PACRC_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP0_SHIFT)) & AIPS_PACRC_WP0_MASK) #define AIPS_PACRC_SP0_MASK (0x40000000U) #define AIPS_PACRC_SP0_SHIFT (30U) +/*! SP0 - Supervisor Protect + * 0b0..This peripheral does not require supervisor privilege level for accesses. + * 0b1..This peripheral requires supervisor privilege level for accesses. + */ #define AIPS_PACRC_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP0_SHIFT)) & AIPS_PACRC_SP0_MASK) +/*! @} */ /*! @name PACRD - Peripheral Access Control Register */ +/*! @{ */ #define AIPS_PACRD_TP7_MASK (0x1U) #define AIPS_PACRD_TP7_SHIFT (0U) +/*! TP7 - Trusted Protect + * 0b0..Accesses from an untrusted master are allowed. + * 0b1..Accesses from an untrusted master are not allowed. + */ #define AIPS_PACRD_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP7_SHIFT)) & AIPS_PACRD_TP7_MASK) #define AIPS_PACRD_WP7_MASK (0x2U) #define AIPS_PACRD_WP7_SHIFT (1U) +/*! WP7 - Write Protect + * 0b0..This peripheral allows write accesses. + * 0b1..This peripheral is write protected. + */ #define AIPS_PACRD_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP7_SHIFT)) & AIPS_PACRD_WP7_MASK) #define AIPS_PACRD_SP7_MASK (0x4U) #define AIPS_PACRD_SP7_SHIFT (2U) +/*! SP7 - Supervisor Protect + * 0b0..This peripheral does not require supervisor privilege level for accesses. + * 0b1..This peripheral requires supervisor privilege level for accesses. + */ #define AIPS_PACRD_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP7_SHIFT)) & AIPS_PACRD_SP7_MASK) #define AIPS_PACRD_TP6_MASK (0x10U) #define AIPS_PACRD_TP6_SHIFT (4U) +/*! TP6 - Trusted Protect + * 0b0..Accesses from an untrusted master are allowed. + * 0b1..Accesses from an untrusted master are not allowed. + */ #define AIPS_PACRD_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP6_SHIFT)) & AIPS_PACRD_TP6_MASK) #define AIPS_PACRD_WP6_MASK (0x20U) #define AIPS_PACRD_WP6_SHIFT (5U) +/*! WP6 - Write Protect + * 0b0..This peripheral allows write accesses. + * 0b1..This peripheral is write protected. + */ #define AIPS_PACRD_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP6_SHIFT)) & AIPS_PACRD_WP6_MASK) #define AIPS_PACRD_SP6_MASK (0x40U) #define AIPS_PACRD_SP6_SHIFT (6U) +/*! SP6 - Supervisor Protect + * 0b0..This peripheral does not require supervisor privilege level for accesses. + * 0b1..This peripheral requires supervisor privilege level for accesses. + */ #define AIPS_PACRD_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP6_SHIFT)) & AIPS_PACRD_SP6_MASK) #define AIPS_PACRD_TP5_MASK (0x100U) #define AIPS_PACRD_TP5_SHIFT (8U) +/*! TP5 - Trusted Protect + * 0b0..Accesses from an untrusted master are allowed. + * 0b1..Accesses from an untrusted master are not allowed. + */ #define AIPS_PACRD_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP5_SHIFT)) & AIPS_PACRD_TP5_MASK) #define AIPS_PACRD_WP5_MASK (0x200U) #define AIPS_PACRD_WP5_SHIFT (9U) +/*! WP5 - Write Protect + * 0b0..This peripheral allows write accesses. + * 0b1..This peripheral is write protected. + */ #define AIPS_PACRD_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP5_SHIFT)) & AIPS_PACRD_WP5_MASK) #define AIPS_PACRD_SP5_MASK (0x400U) #define AIPS_PACRD_SP5_SHIFT (10U) +/*! SP5 - Supervisor Protect + * 0b0..This peripheral does not require supervisor privilege level for accesses. + * 0b1..This peripheral requires supervisor privilege level for accesses. + */ #define AIPS_PACRD_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP5_SHIFT)) & AIPS_PACRD_SP5_MASK) #define AIPS_PACRD_TP4_MASK (0x1000U) #define AIPS_PACRD_TP4_SHIFT (12U) +/*! TP4 - Trusted Protect + * 0b0..Accesses from an untrusted master are allowed. + * 0b1..Accesses from an untrusted master are not allowed. + */ #define AIPS_PACRD_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP4_SHIFT)) & AIPS_PACRD_TP4_MASK) #define AIPS_PACRD_WP4_MASK (0x2000U) #define AIPS_PACRD_WP4_SHIFT (13U) +/*! WP4 - Write Protect + * 0b0..This peripheral allows write accesses. + * 0b1..This peripheral is write protected. + */ #define AIPS_PACRD_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP4_SHIFT)) & AIPS_PACRD_WP4_MASK) #define AIPS_PACRD_SP4_MASK (0x4000U) #define AIPS_PACRD_SP4_SHIFT (14U) +/*! SP4 - Supervisor Protect + * 0b0..This peripheral does not require supervisor privilege level for accesses. + * 0b1..This peripheral requires supervisor privilege level for accesses. + */ #define AIPS_PACRD_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP4_SHIFT)) & AIPS_PACRD_SP4_MASK) #define AIPS_PACRD_TP3_MASK (0x10000U) #define AIPS_PACRD_TP3_SHIFT (16U) +/*! TP3 - Trusted Protect + * 0b0..Accesses from an untrusted master are allowed. + * 0b1..Accesses from an untrusted master are not allowed. + */ #define AIPS_PACRD_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP3_SHIFT)) & AIPS_PACRD_TP3_MASK) #define AIPS_PACRD_WP3_MASK (0x20000U) #define AIPS_PACRD_WP3_SHIFT (17U) +/*! WP3 - Write Protect + * 0b0..This peripheral allows write accesses. + * 0b1..This peripheral is write protected. + */ #define AIPS_PACRD_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP3_SHIFT)) & AIPS_PACRD_WP3_MASK) #define AIPS_PACRD_SP3_MASK (0x40000U) #define AIPS_PACRD_SP3_SHIFT (18U) +/*! SP3 - Supervisor Protect + * 0b0..This peripheral does not require supervisor privilege level for accesses. + * 0b1..This peripheral requires supervisor privilege level for accesses. + */ #define AIPS_PACRD_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP3_SHIFT)) & AIPS_PACRD_SP3_MASK) #define AIPS_PACRD_TP2_MASK (0x100000U) #define AIPS_PACRD_TP2_SHIFT (20U) +/*! TP2 - Trusted Protect + * 0b0..Accesses from an untrusted master are allowed. + * 0b1..Accesses from an untrusted master are not allowed. + */ #define AIPS_PACRD_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP2_SHIFT)) & AIPS_PACRD_TP2_MASK) #define AIPS_PACRD_WP2_MASK (0x200000U) #define AIPS_PACRD_WP2_SHIFT (21U) +/*! WP2 - Write Protect + * 0b0..This peripheral allows write accesses. + * 0b1..This peripheral is write protected. + */ #define AIPS_PACRD_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP2_SHIFT)) & AIPS_PACRD_WP2_MASK) #define AIPS_PACRD_SP2_MASK (0x400000U) #define AIPS_PACRD_SP2_SHIFT (22U) +/*! SP2 - Supervisor Protect + * 0b0..This peripheral does not require supervisor privilege level for accesses. + * 0b1..This peripheral requires supervisor privilege level for accesses. + */ #define AIPS_PACRD_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP2_SHIFT)) & AIPS_PACRD_SP2_MASK) #define AIPS_PACRD_TP1_MASK (0x1000000U) #define AIPS_PACRD_TP1_SHIFT (24U) +/*! TP1 - Trusted Protect + * 0b0..Accesses from an untrusted master are allowed. + * 0b1..Accesses from an untrusted master are not allowed. + */ #define AIPS_PACRD_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP1_SHIFT)) & AIPS_PACRD_TP1_MASK) #define AIPS_PACRD_WP1_MASK (0x2000000U) #define AIPS_PACRD_WP1_SHIFT (25U) +/*! WP1 - Write Protect + * 0b0..This peripheral allows write accesses. + * 0b1..This peripheral is write protected. + */ #define AIPS_PACRD_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP1_SHIFT)) & AIPS_PACRD_WP1_MASK) #define AIPS_PACRD_SP1_MASK (0x4000000U) #define AIPS_PACRD_SP1_SHIFT (26U) +/*! SP1 - Supervisor Protect + * 0b0..This peripheral does not require supervisor privilege level for accesses. + * 0b1..This peripheral requires supervisor privilege level for accesses. + */ #define AIPS_PACRD_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP1_SHIFT)) & AIPS_PACRD_SP1_MASK) #define AIPS_PACRD_TP0_MASK (0x10000000U) #define AIPS_PACRD_TP0_SHIFT (28U) +/*! TP0 - Trusted Protect + * 0b0..Accesses from an untrusted master are allowed. + * 0b1..Accesses from an untrusted master are not allowed. + */ #define AIPS_PACRD_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP0_SHIFT)) & AIPS_PACRD_TP0_MASK) #define AIPS_PACRD_WP0_MASK (0x20000000U) #define AIPS_PACRD_WP0_SHIFT (29U) +/*! WP0 - Write Protect + * 0b0..This peripheral allows write accesses. + * 0b1..This peripheral is write protected. + */ #define AIPS_PACRD_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP0_SHIFT)) & AIPS_PACRD_WP0_MASK) #define AIPS_PACRD_SP0_MASK (0x40000000U) #define AIPS_PACRD_SP0_SHIFT (30U) +/*! SP0 - Supervisor Protect + * 0b0..This peripheral does not require supervisor privilege level for accesses. + * 0b1..This peripheral requires supervisor privilege level for accesses. + */ #define AIPS_PACRD_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP0_SHIFT)) & AIPS_PACRD_SP0_MASK) +/*! @} */ /*! @name PACRE - Peripheral Access Control Register */ +/*! @{ */ #define AIPS_PACRE_TP7_MASK (0x1U) #define AIPS_PACRE_TP7_SHIFT (0U) +/*! TP7 - Trusted Protect + * 0b0..Accesses from an untrusted master are allowed. + * 0b1..Accesses from an untrusted master are not allowed. + */ #define AIPS_PACRE_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP7_SHIFT)) & AIPS_PACRE_TP7_MASK) #define AIPS_PACRE_WP7_MASK (0x2U) #define AIPS_PACRE_WP7_SHIFT (1U) +/*! WP7 - Write Protect + * 0b0..This peripheral allows write accesses. + * 0b1..This peripheral is write protected. + */ #define AIPS_PACRE_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP7_SHIFT)) & AIPS_PACRE_WP7_MASK) #define AIPS_PACRE_SP7_MASK (0x4U) #define AIPS_PACRE_SP7_SHIFT (2U) +/*! SP7 - Supervisor Protect + * 0b0..This peripheral does not require supervisor privilege level for accesses. + * 0b1..This peripheral requires supervisor privilege level for accesses. + */ #define AIPS_PACRE_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP7_SHIFT)) & AIPS_PACRE_SP7_MASK) #define AIPS_PACRE_TP6_MASK (0x10U) #define AIPS_PACRE_TP6_SHIFT (4U) +/*! TP6 - Trusted Protect + * 0b0..Accesses from an untrusted master are allowed. + * 0b1..Accesses from an untrusted master are not allowed. + */ #define AIPS_PACRE_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP6_SHIFT)) & AIPS_PACRE_TP6_MASK) #define AIPS_PACRE_WP6_MASK (0x20U) #define AIPS_PACRE_WP6_SHIFT (5U) +/*! WP6 - Write Protect + * 0b0..This peripheral allows write accesses. + * 0b1..This peripheral is write protected. + */ #define AIPS_PACRE_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP6_SHIFT)) & AIPS_PACRE_WP6_MASK) #define AIPS_PACRE_SP6_MASK (0x40U) #define AIPS_PACRE_SP6_SHIFT (6U) +/*! SP6 - Supervisor Protect + * 0b0..This peripheral does not require supervisor privilege level for accesses. + * 0b1..This peripheral requires supervisor privilege level for accesses. + */ #define AIPS_PACRE_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP6_SHIFT)) & AIPS_PACRE_SP6_MASK) #define AIPS_PACRE_TP5_MASK (0x100U) #define AIPS_PACRE_TP5_SHIFT (8U) +/*! TP5 - Trusted Protect + * 0b0..Accesses from an untrusted master are allowed. + * 0b1..Accesses from an untrusted master are not allowed. + */ #define AIPS_PACRE_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP5_SHIFT)) & AIPS_PACRE_TP5_MASK) #define AIPS_PACRE_WP5_MASK (0x200U) #define AIPS_PACRE_WP5_SHIFT (9U) +/*! WP5 - Write Protect + * 0b0..This peripheral allows write accesses. + * 0b1..This peripheral is write protected. + */ #define AIPS_PACRE_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP5_SHIFT)) & AIPS_PACRE_WP5_MASK) #define AIPS_PACRE_SP5_MASK (0x400U) #define AIPS_PACRE_SP5_SHIFT (10U) +/*! SP5 - Supervisor Protect + * 0b0..This peripheral does not require supervisor privilege level for accesses. + * 0b1..This peripheral requires supervisor privilege level for accesses. + */ #define AIPS_PACRE_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP5_SHIFT)) & AIPS_PACRE_SP5_MASK) #define AIPS_PACRE_TP4_MASK (0x1000U) #define AIPS_PACRE_TP4_SHIFT (12U) +/*! TP4 - Trusted Protect + * 0b0..Accesses from an untrusted master are allowed. + * 0b1..Accesses from an untrusted master are not allowed. + */ #define AIPS_PACRE_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP4_SHIFT)) & AIPS_PACRE_TP4_MASK) #define AIPS_PACRE_WP4_MASK (0x2000U) #define AIPS_PACRE_WP4_SHIFT (13U) +/*! WP4 - Write Protect + * 0b0..This peripheral allows write accesses. + * 0b1..This peripheral is write protected. + */ #define AIPS_PACRE_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP4_SHIFT)) & AIPS_PACRE_WP4_MASK) #define AIPS_PACRE_SP4_MASK (0x4000U) #define AIPS_PACRE_SP4_SHIFT (14U) +/*! SP4 - Supervisor Protect + * 0b0..This peripheral does not require supervisor privilege level for accesses. + * 0b1..This peripheral requires supervisor privilege level for accesses. + */ #define AIPS_PACRE_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP4_SHIFT)) & AIPS_PACRE_SP4_MASK) #define AIPS_PACRE_TP3_MASK (0x10000U) #define AIPS_PACRE_TP3_SHIFT (16U) +/*! TP3 - Trusted Protect + * 0b0..Accesses from an untrusted master are allowed. + * 0b1..Accesses from an untrusted master are not allowed. + */ #define AIPS_PACRE_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP3_SHIFT)) & AIPS_PACRE_TP3_MASK) #define AIPS_PACRE_WP3_MASK (0x20000U) #define AIPS_PACRE_WP3_SHIFT (17U) +/*! WP3 - Write Protect + * 0b0..This peripheral allows write accesses. + * 0b1..This peripheral is write protected. + */ #define AIPS_PACRE_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP3_SHIFT)) & AIPS_PACRE_WP3_MASK) #define AIPS_PACRE_SP3_MASK (0x40000U) #define AIPS_PACRE_SP3_SHIFT (18U) +/*! SP3 - Supervisor Protect + * 0b0..This peripheral does not require supervisor privilege level for accesses. + * 0b1..This peripheral requires supervisor privilege level for accesses. + */ #define AIPS_PACRE_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP3_SHIFT)) & AIPS_PACRE_SP3_MASK) #define AIPS_PACRE_TP2_MASK (0x100000U) #define AIPS_PACRE_TP2_SHIFT (20U) +/*! TP2 - Trusted Protect + * 0b0..Accesses from an untrusted master are allowed. + * 0b1..Accesses from an untrusted master are not allowed. + */ #define AIPS_PACRE_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP2_SHIFT)) & AIPS_PACRE_TP2_MASK) #define AIPS_PACRE_WP2_MASK (0x200000U) #define AIPS_PACRE_WP2_SHIFT (21U) +/*! WP2 - Write Protect + * 0b0..This peripheral allows write accesses. + * 0b1..This peripheral is write protected. + */ #define AIPS_PACRE_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP2_SHIFT)) & AIPS_PACRE_WP2_MASK) #define AIPS_PACRE_SP2_MASK (0x400000U) #define AIPS_PACRE_SP2_SHIFT (22U) +/*! SP2 - Supervisor Protect + * 0b0..This peripheral does not require supervisor privilege level for accesses. + * 0b1..This peripheral requires supervisor privilege level for accesses. + */ #define AIPS_PACRE_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP2_SHIFT)) & AIPS_PACRE_SP2_MASK) #define AIPS_PACRE_TP1_MASK (0x1000000U) #define AIPS_PACRE_TP1_SHIFT (24U) +/*! TP1 - Trusted Protect + * 0b0..Accesses from an untrusted master are allowed. + * 0b1..Accesses from an untrusted master are not allowed. + */ #define AIPS_PACRE_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP1_SHIFT)) & AIPS_PACRE_TP1_MASK) #define AIPS_PACRE_WP1_MASK (0x2000000U) #define AIPS_PACRE_WP1_SHIFT (25U) +/*! WP1 - Write Protect + * 0b0..This peripheral allows write accesses. + * 0b1..This peripheral is write protected. + */ #define AIPS_PACRE_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP1_SHIFT)) & AIPS_PACRE_WP1_MASK) #define AIPS_PACRE_SP1_MASK (0x4000000U) #define AIPS_PACRE_SP1_SHIFT (26U) +/*! SP1 - Supervisor Protect + * 0b0..This peripheral does not require supervisor privilege level for accesses. + * 0b1..This peripheral requires supervisor privilege level for accesses. + */ #define AIPS_PACRE_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP1_SHIFT)) & AIPS_PACRE_SP1_MASK) #define AIPS_PACRE_TP0_MASK (0x10000000U) #define AIPS_PACRE_TP0_SHIFT (28U) +/*! TP0 - Trusted Protect + * 0b0..Accesses from an untrusted master are allowed. + * 0b1..Accesses from an untrusted master are not allowed. + */ #define AIPS_PACRE_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP0_SHIFT)) & AIPS_PACRE_TP0_MASK) #define AIPS_PACRE_WP0_MASK (0x20000000U) #define AIPS_PACRE_WP0_SHIFT (29U) +/*! WP0 - Write Protect + * 0b0..This peripheral allows write accesses. + * 0b1..This peripheral is write protected. + */ #define AIPS_PACRE_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP0_SHIFT)) & AIPS_PACRE_WP0_MASK) #define AIPS_PACRE_SP0_MASK (0x40000000U) #define AIPS_PACRE_SP0_SHIFT (30U) +/*! SP0 - Supervisor Protect + * 0b0..This peripheral does not require supervisor privilege level for accesses. + * 0b1..This peripheral requires supervisor privilege level for accesses. + */ #define AIPS_PACRE_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP0_SHIFT)) & AIPS_PACRE_SP0_MASK) +/*! @} */ /*! @name PACRF - Peripheral Access Control Register */ +/*! @{ */ #define AIPS_PACRF_TP7_MASK (0x1U) #define AIPS_PACRF_TP7_SHIFT (0U) +/*! TP7 - Trusted Protect + * 0b0..Accesses from an untrusted master are allowed. + * 0b1..Accesses from an untrusted master are not allowed. + */ #define AIPS_PACRF_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP7_SHIFT)) & AIPS_PACRF_TP7_MASK) #define AIPS_PACRF_WP7_MASK (0x2U) #define AIPS_PACRF_WP7_SHIFT (1U) +/*! WP7 - Write Protect + * 0b0..This peripheral allows write accesses. + * 0b1..This peripheral is write protected. + */ #define AIPS_PACRF_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP7_SHIFT)) & AIPS_PACRF_WP7_MASK) #define AIPS_PACRF_SP7_MASK (0x4U) #define AIPS_PACRF_SP7_SHIFT (2U) +/*! SP7 - Supervisor Protect + * 0b0..This peripheral does not require supervisor privilege level for accesses. + * 0b1..This peripheral requires supervisor privilege level for accesses. + */ #define AIPS_PACRF_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP7_SHIFT)) & AIPS_PACRF_SP7_MASK) #define AIPS_PACRF_TP6_MASK (0x10U) #define AIPS_PACRF_TP6_SHIFT (4U) +/*! TP6 - Trusted Protect + * 0b0..Accesses from an untrusted master are allowed. + * 0b1..Accesses from an untrusted master are not allowed. + */ #define AIPS_PACRF_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP6_SHIFT)) & AIPS_PACRF_TP6_MASK) #define AIPS_PACRF_WP6_MASK (0x20U) #define AIPS_PACRF_WP6_SHIFT (5U) +/*! WP6 - Write Protect + * 0b0..This peripheral allows write accesses. + * 0b1..This peripheral is write protected. + */ #define AIPS_PACRF_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP6_SHIFT)) & AIPS_PACRF_WP6_MASK) #define AIPS_PACRF_SP6_MASK (0x40U) #define AIPS_PACRF_SP6_SHIFT (6U) +/*! SP6 - Supervisor Protect + * 0b0..This peripheral does not require supervisor privilege level for accesses. + * 0b1..This peripheral requires supervisor privilege level for accesses. + */ #define AIPS_PACRF_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP6_SHIFT)) & AIPS_PACRF_SP6_MASK) #define AIPS_PACRF_TP5_MASK (0x100U) #define AIPS_PACRF_TP5_SHIFT (8U) +/*! TP5 - Trusted Protect + * 0b0..Accesses from an untrusted master are allowed. + * 0b1..Accesses from an untrusted master are not allowed. + */ #define AIPS_PACRF_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP5_SHIFT)) & AIPS_PACRF_TP5_MASK) #define AIPS_PACRF_WP5_MASK (0x200U) #define AIPS_PACRF_WP5_SHIFT (9U) +/*! WP5 - Write Protect + * 0b0..This peripheral allows write accesses. + * 0b1..This peripheral is write protected. + */ #define AIPS_PACRF_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP5_SHIFT)) & AIPS_PACRF_WP5_MASK) #define AIPS_PACRF_SP5_MASK (0x400U) #define AIPS_PACRF_SP5_SHIFT (10U) +/*! SP5 - Supervisor Protect + * 0b0..This peripheral does not require supervisor privilege level for accesses. + * 0b1..This peripheral requires supervisor privilege level for accesses. + */ #define AIPS_PACRF_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP5_SHIFT)) & AIPS_PACRF_SP5_MASK) #define AIPS_PACRF_TP4_MASK (0x1000U) #define AIPS_PACRF_TP4_SHIFT (12U) +/*! TP4 - Trusted Protect + * 0b0..Accesses from an untrusted master are allowed. + * 0b1..Accesses from an untrusted master are not allowed. + */ #define AIPS_PACRF_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP4_SHIFT)) & AIPS_PACRF_TP4_MASK) #define AIPS_PACRF_WP4_MASK (0x2000U) #define AIPS_PACRF_WP4_SHIFT (13U) +/*! WP4 - Write Protect + * 0b0..This peripheral allows write accesses. + * 0b1..This peripheral is write protected. + */ #define AIPS_PACRF_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP4_SHIFT)) & AIPS_PACRF_WP4_MASK) #define AIPS_PACRF_SP4_MASK (0x4000U) #define AIPS_PACRF_SP4_SHIFT (14U) +/*! SP4 - Supervisor Protect + * 0b0..This peripheral does not require supervisor privilege level for accesses. + * 0b1..This peripheral requires supervisor privilege level for accesses. + */ #define AIPS_PACRF_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP4_SHIFT)) & AIPS_PACRF_SP4_MASK) #define AIPS_PACRF_TP3_MASK (0x10000U) #define AIPS_PACRF_TP3_SHIFT (16U) +/*! TP3 - Trusted Protect + * 0b0..Accesses from an untrusted master are allowed. + * 0b1..Accesses from an untrusted master are not allowed. + */ #define AIPS_PACRF_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP3_SHIFT)) & AIPS_PACRF_TP3_MASK) #define AIPS_PACRF_WP3_MASK (0x20000U) #define AIPS_PACRF_WP3_SHIFT (17U) +/*! WP3 - Write Protect + * 0b0..This peripheral allows write accesses. + * 0b1..This peripheral is write protected. + */ #define AIPS_PACRF_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP3_SHIFT)) & AIPS_PACRF_WP3_MASK) #define AIPS_PACRF_SP3_MASK (0x40000U) #define AIPS_PACRF_SP3_SHIFT (18U) +/*! SP3 - Supervisor Protect + * 0b0..This peripheral does not require supervisor privilege level for accesses. + * 0b1..This peripheral requires supervisor privilege level for accesses. + */ #define AIPS_PACRF_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP3_SHIFT)) & AIPS_PACRF_SP3_MASK) #define AIPS_PACRF_TP2_MASK (0x100000U) #define AIPS_PACRF_TP2_SHIFT (20U) +/*! TP2 - Trusted Protect + * 0b0..Accesses from an untrusted master are allowed. + * 0b1..Accesses from an untrusted master are not allowed. + */ #define AIPS_PACRF_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP2_SHIFT)) & AIPS_PACRF_TP2_MASK) #define AIPS_PACRF_WP2_MASK (0x200000U) #define AIPS_PACRF_WP2_SHIFT (21U) +/*! WP2 - Write Protect + * 0b0..This peripheral allows write accesses. + * 0b1..This peripheral is write protected. + */ #define AIPS_PACRF_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP2_SHIFT)) & AIPS_PACRF_WP2_MASK) #define AIPS_PACRF_SP2_MASK (0x400000U) #define AIPS_PACRF_SP2_SHIFT (22U) +/*! SP2 - Supervisor Protect + * 0b0..This peripheral does not require supervisor privilege level for accesses. + * 0b1..This peripheral requires supervisor privilege level for accesses. + */ #define AIPS_PACRF_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP2_SHIFT)) & AIPS_PACRF_SP2_MASK) #define AIPS_PACRF_TP1_MASK (0x1000000U) #define AIPS_PACRF_TP1_SHIFT (24U) +/*! TP1 - Trusted Protect + * 0b0..Accesses from an untrusted master are allowed. + * 0b1..Accesses from an untrusted master are not allowed. + */ #define AIPS_PACRF_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP1_SHIFT)) & AIPS_PACRF_TP1_MASK) #define AIPS_PACRF_WP1_MASK (0x2000000U) #define AIPS_PACRF_WP1_SHIFT (25U) +/*! WP1 - Write Protect + * 0b0..This peripheral allows write accesses. + * 0b1..This peripheral is write protected. + */ #define AIPS_PACRF_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP1_SHIFT)) & AIPS_PACRF_WP1_MASK) #define AIPS_PACRF_SP1_MASK (0x4000000U) #define AIPS_PACRF_SP1_SHIFT (26U) +/*! SP1 - Supervisor Protect + * 0b0..This peripheral does not require supervisor privilege level for accesses. + * 0b1..This peripheral requires supervisor privilege level for accesses. + */ #define AIPS_PACRF_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP1_SHIFT)) & AIPS_PACRF_SP1_MASK) #define AIPS_PACRF_TP0_MASK (0x10000000U) #define AIPS_PACRF_TP0_SHIFT (28U) +/*! TP0 - Trusted Protect + * 0b0..Accesses from an untrusted master are allowed. + * 0b1..Accesses from an untrusted master are not allowed. + */ #define AIPS_PACRF_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP0_SHIFT)) & AIPS_PACRF_TP0_MASK) #define AIPS_PACRF_WP0_MASK (0x20000000U) #define AIPS_PACRF_WP0_SHIFT (29U) +/*! WP0 - Write Protect + * 0b0..This peripheral allows write accesses. + * 0b1..This peripheral is write protected. + */ #define AIPS_PACRF_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP0_SHIFT)) & AIPS_PACRF_WP0_MASK) #define AIPS_PACRF_SP0_MASK (0x40000000U) #define AIPS_PACRF_SP0_SHIFT (30U) +/*! SP0 - Supervisor Protect + * 0b0..This peripheral does not require supervisor privilege level for accesses. + * 0b1..This peripheral requires supervisor privilege level for accesses. + */ #define AIPS_PACRF_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP0_SHIFT)) & AIPS_PACRF_SP0_MASK) +/*! @} */ /*! @name PACRG - Peripheral Access Control Register */ +/*! @{ */ #define AIPS_PACRG_TP7_MASK (0x1U) #define AIPS_PACRG_TP7_SHIFT (0U) +/*! TP7 - Trusted Protect + * 0b0..Accesses from an untrusted master are allowed. + * 0b1..Accesses from an untrusted master are not allowed. + */ #define AIPS_PACRG_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP7_SHIFT)) & AIPS_PACRG_TP7_MASK) #define AIPS_PACRG_WP7_MASK (0x2U) #define AIPS_PACRG_WP7_SHIFT (1U) +/*! WP7 - Write Protect + * 0b0..This peripheral allows write accesses. + * 0b1..This peripheral is write protected. + */ #define AIPS_PACRG_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP7_SHIFT)) & AIPS_PACRG_WP7_MASK) #define AIPS_PACRG_SP7_MASK (0x4U) #define AIPS_PACRG_SP7_SHIFT (2U) +/*! SP7 - Supervisor Protect + * 0b0..This peripheral does not require supervisor privilege level for accesses. + * 0b1..This peripheral requires supervisor privilege level for accesses. + */ #define AIPS_PACRG_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP7_SHIFT)) & AIPS_PACRG_SP7_MASK) #define AIPS_PACRG_TP6_MASK (0x10U) #define AIPS_PACRG_TP6_SHIFT (4U) +/*! TP6 - Trusted Protect + * 0b0..Accesses from an untrusted master are allowed. + * 0b1..Accesses from an untrusted master are not allowed. + */ #define AIPS_PACRG_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP6_SHIFT)) & AIPS_PACRG_TP6_MASK) #define AIPS_PACRG_WP6_MASK (0x20U) #define AIPS_PACRG_WP6_SHIFT (5U) +/*! WP6 - Write Protect + * 0b0..This peripheral allows write accesses. + * 0b1..This peripheral is write protected. + */ #define AIPS_PACRG_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP6_SHIFT)) & AIPS_PACRG_WP6_MASK) #define AIPS_PACRG_SP6_MASK (0x40U) #define AIPS_PACRG_SP6_SHIFT (6U) +/*! SP6 - Supervisor Protect + * 0b0..This peripheral does not require supervisor privilege level for accesses. + * 0b1..This peripheral requires supervisor privilege level for accesses. + */ #define AIPS_PACRG_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP6_SHIFT)) & AIPS_PACRG_SP6_MASK) #define AIPS_PACRG_TP5_MASK (0x100U) #define AIPS_PACRG_TP5_SHIFT (8U) +/*! TP5 - Trusted Protect + * 0b0..Accesses from an untrusted master are allowed. + * 0b1..Accesses from an untrusted master are not allowed. + */ #define AIPS_PACRG_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP5_SHIFT)) & AIPS_PACRG_TP5_MASK) #define AIPS_PACRG_WP5_MASK (0x200U) #define AIPS_PACRG_WP5_SHIFT (9U) +/*! WP5 - Write Protect + * 0b0..This peripheral allows write accesses. + * 0b1..This peripheral is write protected. + */ #define AIPS_PACRG_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP5_SHIFT)) & AIPS_PACRG_WP5_MASK) #define AIPS_PACRG_SP5_MASK (0x400U) #define AIPS_PACRG_SP5_SHIFT (10U) +/*! SP5 - Supervisor Protect + * 0b0..This peripheral does not require supervisor privilege level for accesses. + * 0b1..This peripheral requires supervisor privilege level for accesses. + */ #define AIPS_PACRG_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP5_SHIFT)) & AIPS_PACRG_SP5_MASK) #define AIPS_PACRG_TP4_MASK (0x1000U) #define AIPS_PACRG_TP4_SHIFT (12U) +/*! TP4 - Trusted Protect + * 0b0..Accesses from an untrusted master are allowed. + * 0b1..Accesses from an untrusted master are not allowed. + */ #define AIPS_PACRG_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP4_SHIFT)) & AIPS_PACRG_TP4_MASK) #define AIPS_PACRG_WP4_MASK (0x2000U) #define AIPS_PACRG_WP4_SHIFT (13U) +/*! WP4 - Write Protect + * 0b0..This peripheral allows write accesses. + * 0b1..This peripheral is write protected. + */ #define AIPS_PACRG_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP4_SHIFT)) & AIPS_PACRG_WP4_MASK) #define AIPS_PACRG_SP4_MASK (0x4000U) #define AIPS_PACRG_SP4_SHIFT (14U) +/*! SP4 - Supervisor Protect + * 0b0..This peripheral does not require supervisor privilege level for accesses. + * 0b1..This peripheral requires supervisor privilege level for accesses. + */ #define AIPS_PACRG_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP4_SHIFT)) & AIPS_PACRG_SP4_MASK) #define AIPS_PACRG_TP3_MASK (0x10000U) #define AIPS_PACRG_TP3_SHIFT (16U) +/*! TP3 - Trusted Protect + * 0b0..Accesses from an untrusted master are allowed. + * 0b1..Accesses from an untrusted master are not allowed. + */ #define AIPS_PACRG_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP3_SHIFT)) & AIPS_PACRG_TP3_MASK) #define AIPS_PACRG_WP3_MASK (0x20000U) #define AIPS_PACRG_WP3_SHIFT (17U) +/*! WP3 - Write Protect + * 0b0..This peripheral allows write accesses. + * 0b1..This peripheral is write protected. + */ #define AIPS_PACRG_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP3_SHIFT)) & AIPS_PACRG_WP3_MASK) #define AIPS_PACRG_SP3_MASK (0x40000U) #define AIPS_PACRG_SP3_SHIFT (18U) +/*! SP3 - Supervisor Protect + * 0b0..This peripheral does not require supervisor privilege level for accesses. + * 0b1..This peripheral requires supervisor privilege level for accesses. + */ #define AIPS_PACRG_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP3_SHIFT)) & AIPS_PACRG_SP3_MASK) #define AIPS_PACRG_TP2_MASK (0x100000U) #define AIPS_PACRG_TP2_SHIFT (20U) +/*! TP2 - Trusted Protect + * 0b0..Accesses from an untrusted master are allowed. + * 0b1..Accesses from an untrusted master are not allowed. + */ #define AIPS_PACRG_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP2_SHIFT)) & AIPS_PACRG_TP2_MASK) #define AIPS_PACRG_WP2_MASK (0x200000U) #define AIPS_PACRG_WP2_SHIFT (21U) +/*! WP2 - Write Protect + * 0b0..This peripheral allows write accesses. + * 0b1..This peripheral is write protected. + */ #define AIPS_PACRG_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP2_SHIFT)) & AIPS_PACRG_WP2_MASK) #define AIPS_PACRG_SP2_MASK (0x400000U) #define AIPS_PACRG_SP2_SHIFT (22U) +/*! SP2 - Supervisor Protect + * 0b0..This peripheral does not require supervisor privilege level for accesses. + * 0b1..This peripheral requires supervisor privilege level for accesses. + */ #define AIPS_PACRG_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP2_SHIFT)) & AIPS_PACRG_SP2_MASK) #define AIPS_PACRG_TP1_MASK (0x1000000U) #define AIPS_PACRG_TP1_SHIFT (24U) +/*! TP1 - Trusted Protect + * 0b0..Accesses from an untrusted master are allowed. + * 0b1..Accesses from an untrusted master are not allowed. + */ #define AIPS_PACRG_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP1_SHIFT)) & AIPS_PACRG_TP1_MASK) #define AIPS_PACRG_WP1_MASK (0x2000000U) #define AIPS_PACRG_WP1_SHIFT (25U) +/*! WP1 - Write Protect + * 0b0..This peripheral allows write accesses. + * 0b1..This peripheral is write protected. + */ #define AIPS_PACRG_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP1_SHIFT)) & AIPS_PACRG_WP1_MASK) #define AIPS_PACRG_SP1_MASK (0x4000000U) #define AIPS_PACRG_SP1_SHIFT (26U) +/*! SP1 - Supervisor Protect + * 0b0..This peripheral does not require supervisor privilege level for accesses. + * 0b1..This peripheral requires supervisor privilege level for accesses. + */ #define AIPS_PACRG_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP1_SHIFT)) & AIPS_PACRG_SP1_MASK) #define AIPS_PACRG_TP0_MASK (0x10000000U) #define AIPS_PACRG_TP0_SHIFT (28U) +/*! TP0 - Trusted Protect + * 0b0..Accesses from an untrusted master are allowed. + * 0b1..Accesses from an untrusted master are not allowed. + */ #define AIPS_PACRG_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP0_SHIFT)) & AIPS_PACRG_TP0_MASK) #define AIPS_PACRG_WP0_MASK (0x20000000U) #define AIPS_PACRG_WP0_SHIFT (29U) +/*! WP0 - Write Protect + * 0b0..This peripheral allows write accesses. + * 0b1..This peripheral is write protected. + */ #define AIPS_PACRG_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP0_SHIFT)) & AIPS_PACRG_WP0_MASK) #define AIPS_PACRG_SP0_MASK (0x40000000U) #define AIPS_PACRG_SP0_SHIFT (30U) +/*! SP0 - Supervisor Protect + * 0b0..This peripheral does not require supervisor privilege level for accesses. + * 0b1..This peripheral requires supervisor privilege level for accesses. + */ #define AIPS_PACRG_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP0_SHIFT)) & AIPS_PACRG_SP0_MASK) +/*! @} */ /*! @name PACRH - Peripheral Access Control Register */ +/*! @{ */ #define AIPS_PACRH_TP7_MASK (0x1U) #define AIPS_PACRH_TP7_SHIFT (0U) +/*! TP7 - Trusted Protect + * 0b0..Accesses from an untrusted master are allowed. + * 0b1..Accesses from an untrusted master are not allowed. + */ #define AIPS_PACRH_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP7_SHIFT)) & AIPS_PACRH_TP7_MASK) #define AIPS_PACRH_WP7_MASK (0x2U) #define AIPS_PACRH_WP7_SHIFT (1U) +/*! WP7 - Write Protect + * 0b0..This peripheral allows write accesses. + * 0b1..This peripheral is write protected. + */ #define AIPS_PACRH_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP7_SHIFT)) & AIPS_PACRH_WP7_MASK) #define AIPS_PACRH_SP7_MASK (0x4U) #define AIPS_PACRH_SP7_SHIFT (2U) +/*! SP7 - Supervisor Protect + * 0b0..This peripheral does not require supervisor privilege level for accesses. + * 0b1..This peripheral requires supervisor privilege level for accesses. + */ #define AIPS_PACRH_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP7_SHIFT)) & AIPS_PACRH_SP7_MASK) #define AIPS_PACRH_TP6_MASK (0x10U) #define AIPS_PACRH_TP6_SHIFT (4U) +/*! TP6 - Trusted Protect + * 0b0..Accesses from an untrusted master are allowed. + * 0b1..Accesses from an untrusted master are not allowed. + */ #define AIPS_PACRH_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP6_SHIFT)) & AIPS_PACRH_TP6_MASK) #define AIPS_PACRH_WP6_MASK (0x20U) #define AIPS_PACRH_WP6_SHIFT (5U) +/*! WP6 - Write Protect + * 0b0..This peripheral allows write accesses. + * 0b1..This peripheral is write protected. + */ #define AIPS_PACRH_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP6_SHIFT)) & AIPS_PACRH_WP6_MASK) #define AIPS_PACRH_SP6_MASK (0x40U) #define AIPS_PACRH_SP6_SHIFT (6U) +/*! SP6 - Supervisor Protect + * 0b0..This peripheral does not require supervisor privilege level for accesses. + * 0b1..This peripheral requires supervisor privilege level for accesses. + */ #define AIPS_PACRH_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP6_SHIFT)) & AIPS_PACRH_SP6_MASK) #define AIPS_PACRH_TP5_MASK (0x100U) #define AIPS_PACRH_TP5_SHIFT (8U) +/*! TP5 - Trusted Protect + * 0b0..Accesses from an untrusted master are allowed. + * 0b1..Accesses from an untrusted master are not allowed. + */ #define AIPS_PACRH_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP5_SHIFT)) & AIPS_PACRH_TP5_MASK) #define AIPS_PACRH_WP5_MASK (0x200U) #define AIPS_PACRH_WP5_SHIFT (9U) +/*! WP5 - Write Protect + * 0b0..This peripheral allows write accesses. + * 0b1..This peripheral is write protected. + */ #define AIPS_PACRH_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP5_SHIFT)) & AIPS_PACRH_WP5_MASK) #define AIPS_PACRH_SP5_MASK (0x400U) #define AIPS_PACRH_SP5_SHIFT (10U) +/*! SP5 - Supervisor Protect + * 0b0..This peripheral does not require supervisor privilege level for accesses. + * 0b1..This peripheral requires supervisor privilege level for accesses. + */ #define AIPS_PACRH_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP5_SHIFT)) & AIPS_PACRH_SP5_MASK) #define AIPS_PACRH_TP4_MASK (0x1000U) #define AIPS_PACRH_TP4_SHIFT (12U) +/*! TP4 - Trusted Protect + * 0b0..Accesses from an untrusted master are allowed. + * 0b1..Accesses from an untrusted master are not allowed. + */ #define AIPS_PACRH_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP4_SHIFT)) & AIPS_PACRH_TP4_MASK) #define AIPS_PACRH_WP4_MASK (0x2000U) #define AIPS_PACRH_WP4_SHIFT (13U) +/*! WP4 - Write Protect + * 0b0..This peripheral allows write accesses. + * 0b1..This peripheral is write protected. + */ #define AIPS_PACRH_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP4_SHIFT)) & AIPS_PACRH_WP4_MASK) #define AIPS_PACRH_SP4_MASK (0x4000U) #define AIPS_PACRH_SP4_SHIFT (14U) +/*! SP4 - Supervisor Protect + * 0b0..This peripheral does not require supervisor privilege level for accesses. + * 0b1..This peripheral requires supervisor privilege level for accesses. + */ #define AIPS_PACRH_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP4_SHIFT)) & AIPS_PACRH_SP4_MASK) #define AIPS_PACRH_TP3_MASK (0x10000U) #define AIPS_PACRH_TP3_SHIFT (16U) +/*! TP3 - Trusted Protect + * 0b0..Accesses from an untrusted master are allowed. + * 0b1..Accesses from an untrusted master are not allowed. + */ #define AIPS_PACRH_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP3_SHIFT)) & AIPS_PACRH_TP3_MASK) #define AIPS_PACRH_WP3_MASK (0x20000U) #define AIPS_PACRH_WP3_SHIFT (17U) +/*! WP3 - Write Protect + * 0b0..This peripheral allows write accesses. + * 0b1..This peripheral is write protected. + */ #define AIPS_PACRH_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP3_SHIFT)) & AIPS_PACRH_WP3_MASK) #define AIPS_PACRH_SP3_MASK (0x40000U) #define AIPS_PACRH_SP3_SHIFT (18U) +/*! SP3 - Supervisor Protect + * 0b0..This peripheral does not require supervisor privilege level for accesses. + * 0b1..This peripheral requires supervisor privilege level for accesses. + */ #define AIPS_PACRH_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP3_SHIFT)) & AIPS_PACRH_SP3_MASK) #define AIPS_PACRH_TP2_MASK (0x100000U) #define AIPS_PACRH_TP2_SHIFT (20U) +/*! TP2 - Trusted Protect + * 0b0..Accesses from an untrusted master are allowed. + * 0b1..Accesses from an untrusted master are not allowed. + */ #define AIPS_PACRH_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP2_SHIFT)) & AIPS_PACRH_TP2_MASK) #define AIPS_PACRH_WP2_MASK (0x200000U) #define AIPS_PACRH_WP2_SHIFT (21U) +/*! WP2 - Write Protect + * 0b0..This peripheral allows write accesses. + * 0b1..This peripheral is write protected. + */ #define AIPS_PACRH_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP2_SHIFT)) & AIPS_PACRH_WP2_MASK) #define AIPS_PACRH_SP2_MASK (0x400000U) #define AIPS_PACRH_SP2_SHIFT (22U) +/*! SP2 - Supervisor Protect + * 0b0..This peripheral does not require supervisor privilege level for accesses. + * 0b1..This peripheral requires supervisor privilege level for accesses. + */ #define AIPS_PACRH_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP2_SHIFT)) & AIPS_PACRH_SP2_MASK) #define AIPS_PACRH_TP1_MASK (0x1000000U) #define AIPS_PACRH_TP1_SHIFT (24U) +/*! TP1 - Trusted Protect + * 0b0..Accesses from an untrusted master are allowed. + * 0b1..Accesses from an untrusted master are not allowed. + */ #define AIPS_PACRH_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP1_SHIFT)) & AIPS_PACRH_TP1_MASK) #define AIPS_PACRH_WP1_MASK (0x2000000U) #define AIPS_PACRH_WP1_SHIFT (25U) +/*! WP1 - Write Protect + * 0b0..This peripheral allows write accesses. + * 0b1..This peripheral is write protected. + */ #define AIPS_PACRH_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP1_SHIFT)) & AIPS_PACRH_WP1_MASK) #define AIPS_PACRH_SP1_MASK (0x4000000U) #define AIPS_PACRH_SP1_SHIFT (26U) +/*! SP1 - Supervisor Protect + * 0b0..This peripheral does not require supervisor privilege level for accesses. + * 0b1..This peripheral requires supervisor privilege level for accesses. + */ #define AIPS_PACRH_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP1_SHIFT)) & AIPS_PACRH_SP1_MASK) #define AIPS_PACRH_TP0_MASK (0x10000000U) #define AIPS_PACRH_TP0_SHIFT (28U) +/*! TP0 - Trusted Protect + * 0b0..Accesses from an untrusted master are allowed. + * 0b1..Accesses from an untrusted master are not allowed. + */ #define AIPS_PACRH_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP0_SHIFT)) & AIPS_PACRH_TP0_MASK) #define AIPS_PACRH_WP0_MASK (0x20000000U) #define AIPS_PACRH_WP0_SHIFT (29U) +/*! WP0 - Write Protect + * 0b0..This peripheral allows write accesses. + * 0b1..This peripheral is write protected. + */ #define AIPS_PACRH_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP0_SHIFT)) & AIPS_PACRH_WP0_MASK) #define AIPS_PACRH_SP0_MASK (0x40000000U) #define AIPS_PACRH_SP0_SHIFT (30U) +/*! SP0 - Supervisor Protect + * 0b0..This peripheral does not require supervisor privilege level for accesses. + * 0b1..This peripheral requires supervisor privilege level for accesses. + */ #define AIPS_PACRH_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP0_SHIFT)) & AIPS_PACRH_SP0_MASK) +/*! @} */ /*! @name PACRI - Peripheral Access Control Register */ +/*! @{ */ #define AIPS_PACRI_TP7_MASK (0x1U) #define AIPS_PACRI_TP7_SHIFT (0U) +/*! TP7 - Trusted Protect + * 0b0..Accesses from an untrusted master are allowed. + * 0b1..Accesses from an untrusted master are not allowed. + */ #define AIPS_PACRI_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP7_SHIFT)) & AIPS_PACRI_TP7_MASK) #define AIPS_PACRI_WP7_MASK (0x2U) #define AIPS_PACRI_WP7_SHIFT (1U) +/*! WP7 - Write Protect + * 0b0..This peripheral allows write accesses. + * 0b1..This peripheral is write protected. + */ #define AIPS_PACRI_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP7_SHIFT)) & AIPS_PACRI_WP7_MASK) #define AIPS_PACRI_SP7_MASK (0x4U) #define AIPS_PACRI_SP7_SHIFT (2U) +/*! SP7 - Supervisor Protect + * 0b0..This peripheral does not require supervisor privilege level for accesses. + * 0b1..This peripheral requires supervisor privilege level for accesses. + */ #define AIPS_PACRI_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP7_SHIFT)) & AIPS_PACRI_SP7_MASK) #define AIPS_PACRI_TP6_MASK (0x10U) #define AIPS_PACRI_TP6_SHIFT (4U) +/*! TP6 - Trusted Protect + * 0b0..Accesses from an untrusted master are allowed. + * 0b1..Accesses from an untrusted master are not allowed. + */ #define AIPS_PACRI_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP6_SHIFT)) & AIPS_PACRI_TP6_MASK) #define AIPS_PACRI_WP6_MASK (0x20U) #define AIPS_PACRI_WP6_SHIFT (5U) +/*! WP6 - Write Protect + * 0b0..This peripheral allows write accesses. + * 0b1..This peripheral is write protected. + */ #define AIPS_PACRI_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP6_SHIFT)) & AIPS_PACRI_WP6_MASK) #define AIPS_PACRI_SP6_MASK (0x40U) #define AIPS_PACRI_SP6_SHIFT (6U) +/*! SP6 - Supervisor Protect + * 0b0..This peripheral does not require supervisor privilege level for accesses. + * 0b1..This peripheral requires supervisor privilege level for accesses. + */ #define AIPS_PACRI_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP6_SHIFT)) & AIPS_PACRI_SP6_MASK) #define AIPS_PACRI_TP5_MASK (0x100U) #define AIPS_PACRI_TP5_SHIFT (8U) +/*! TP5 - Trusted Protect + * 0b0..Accesses from an untrusted master are allowed. + * 0b1..Accesses from an untrusted master are not allowed. + */ #define AIPS_PACRI_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP5_SHIFT)) & AIPS_PACRI_TP5_MASK) #define AIPS_PACRI_WP5_MASK (0x200U) #define AIPS_PACRI_WP5_SHIFT (9U) +/*! WP5 - Write Protect + * 0b0..This peripheral allows write accesses. + * 0b1..This peripheral is write protected. + */ #define AIPS_PACRI_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP5_SHIFT)) & AIPS_PACRI_WP5_MASK) #define AIPS_PACRI_SP5_MASK (0x400U) #define AIPS_PACRI_SP5_SHIFT (10U) +/*! SP5 - Supervisor Protect + * 0b0..This peripheral does not require supervisor privilege level for accesses. + * 0b1..This peripheral requires supervisor privilege level for accesses. + */ #define AIPS_PACRI_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP5_SHIFT)) & AIPS_PACRI_SP5_MASK) #define AIPS_PACRI_TP4_MASK (0x1000U) #define AIPS_PACRI_TP4_SHIFT (12U) +/*! TP4 - Trusted Protect + * 0b0..Accesses from an untrusted master are allowed. + * 0b1..Accesses from an untrusted master are not allowed. + */ #define AIPS_PACRI_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP4_SHIFT)) & AIPS_PACRI_TP4_MASK) #define AIPS_PACRI_WP4_MASK (0x2000U) #define AIPS_PACRI_WP4_SHIFT (13U) +/*! WP4 - Write Protect + * 0b0..This peripheral allows write accesses. + * 0b1..This peripheral is write protected. + */ #define AIPS_PACRI_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP4_SHIFT)) & AIPS_PACRI_WP4_MASK) #define AIPS_PACRI_SP4_MASK (0x4000U) #define AIPS_PACRI_SP4_SHIFT (14U) +/*! SP4 - Supervisor Protect + * 0b0..This peripheral does not require supervisor privilege level for accesses. + * 0b1..This peripheral requires supervisor privilege level for accesses. + */ #define AIPS_PACRI_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP4_SHIFT)) & AIPS_PACRI_SP4_MASK) #define AIPS_PACRI_TP3_MASK (0x10000U) #define AIPS_PACRI_TP3_SHIFT (16U) +/*! TP3 - Trusted Protect + * 0b0..Accesses from an untrusted master are allowed. + * 0b1..Accesses from an untrusted master are not allowed. + */ #define AIPS_PACRI_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP3_SHIFT)) & AIPS_PACRI_TP3_MASK) #define AIPS_PACRI_WP3_MASK (0x20000U) #define AIPS_PACRI_WP3_SHIFT (17U) +/*! WP3 - Write Protect + * 0b0..This peripheral allows write accesses. + * 0b1..This peripheral is write protected. + */ #define AIPS_PACRI_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP3_SHIFT)) & AIPS_PACRI_WP3_MASK) #define AIPS_PACRI_SP3_MASK (0x40000U) #define AIPS_PACRI_SP3_SHIFT (18U) +/*! SP3 - Supervisor Protect + * 0b0..This peripheral does not require supervisor privilege level for accesses. + * 0b1..This peripheral requires supervisor privilege level for accesses. + */ #define AIPS_PACRI_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP3_SHIFT)) & AIPS_PACRI_SP3_MASK) #define AIPS_PACRI_TP2_MASK (0x100000U) #define AIPS_PACRI_TP2_SHIFT (20U) +/*! TP2 - Trusted Protect + * 0b0..Accesses from an untrusted master are allowed. + * 0b1..Accesses from an untrusted master are not allowed. + */ #define AIPS_PACRI_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP2_SHIFT)) & AIPS_PACRI_TP2_MASK) #define AIPS_PACRI_WP2_MASK (0x200000U) #define AIPS_PACRI_WP2_SHIFT (21U) +/*! WP2 - Write Protect + * 0b0..This peripheral allows write accesses. + * 0b1..This peripheral is write protected. + */ #define AIPS_PACRI_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP2_SHIFT)) & AIPS_PACRI_WP2_MASK) #define AIPS_PACRI_SP2_MASK (0x400000U) #define AIPS_PACRI_SP2_SHIFT (22U) +/*! SP2 - Supervisor Protect + * 0b0..This peripheral does not require supervisor privilege level for accesses. + * 0b1..This peripheral requires supervisor privilege level for accesses. + */ #define AIPS_PACRI_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP2_SHIFT)) & AIPS_PACRI_SP2_MASK) #define AIPS_PACRI_TP1_MASK (0x1000000U) #define AIPS_PACRI_TP1_SHIFT (24U) +/*! TP1 - Trusted Protect + * 0b0..Accesses from an untrusted master are allowed. + * 0b1..Accesses from an untrusted master are not allowed. + */ #define AIPS_PACRI_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP1_SHIFT)) & AIPS_PACRI_TP1_MASK) #define AIPS_PACRI_WP1_MASK (0x2000000U) #define AIPS_PACRI_WP1_SHIFT (25U) +/*! WP1 - Write Protect + * 0b0..This peripheral allows write accesses. + * 0b1..This peripheral is write protected. + */ #define AIPS_PACRI_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP1_SHIFT)) & AIPS_PACRI_WP1_MASK) #define AIPS_PACRI_SP1_MASK (0x4000000U) #define AIPS_PACRI_SP1_SHIFT (26U) +/*! SP1 - Supervisor Protect + * 0b0..This peripheral does not require supervisor privilege level for accesses. + * 0b1..This peripheral requires supervisor privilege level for accesses. + */ #define AIPS_PACRI_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP1_SHIFT)) & AIPS_PACRI_SP1_MASK) #define AIPS_PACRI_TP0_MASK (0x10000000U) #define AIPS_PACRI_TP0_SHIFT (28U) +/*! TP0 - Trusted Protect + * 0b0..Accesses from an untrusted master are allowed. + * 0b1..Accesses from an untrusted master are not allowed. + */ #define AIPS_PACRI_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP0_SHIFT)) & AIPS_PACRI_TP0_MASK) #define AIPS_PACRI_WP0_MASK (0x20000000U) #define AIPS_PACRI_WP0_SHIFT (29U) +/*! WP0 - Write Protect + * 0b0..This peripheral allows write accesses. + * 0b1..This peripheral is write protected. + */ #define AIPS_PACRI_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP0_SHIFT)) & AIPS_PACRI_WP0_MASK) #define AIPS_PACRI_SP0_MASK (0x40000000U) #define AIPS_PACRI_SP0_SHIFT (30U) +/*! SP0 - Supervisor Protect + * 0b0..This peripheral does not require supervisor privilege level for accesses. + * 0b1..This peripheral requires supervisor privilege level for accesses. + */ #define AIPS_PACRI_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP0_SHIFT)) & AIPS_PACRI_SP0_MASK) +/*! @} */ /*! @name PACRJ - Peripheral Access Control Register */ +/*! @{ */ #define AIPS_PACRJ_TP7_MASK (0x1U) #define AIPS_PACRJ_TP7_SHIFT (0U) +/*! TP7 - Trusted Protect + * 0b0..Accesses from an untrusted master are allowed. + * 0b1..Accesses from an untrusted master are not allowed. + */ #define AIPS_PACRJ_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP7_SHIFT)) & AIPS_PACRJ_TP7_MASK) #define AIPS_PACRJ_WP7_MASK (0x2U) #define AIPS_PACRJ_WP7_SHIFT (1U) +/*! WP7 - Write Protect + * 0b0..This peripheral allows write accesses. + * 0b1..This peripheral is write protected. + */ #define AIPS_PACRJ_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP7_SHIFT)) & AIPS_PACRJ_WP7_MASK) #define AIPS_PACRJ_SP7_MASK (0x4U) #define AIPS_PACRJ_SP7_SHIFT (2U) +/*! SP7 - Supervisor Protect + * 0b0..This peripheral does not require supervisor privilege level for accesses. + * 0b1..This peripheral requires supervisor privilege level for accesses. + */ #define AIPS_PACRJ_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP7_SHIFT)) & AIPS_PACRJ_SP7_MASK) #define AIPS_PACRJ_TP6_MASK (0x10U) #define AIPS_PACRJ_TP6_SHIFT (4U) +/*! TP6 - Trusted Protect + * 0b0..Accesses from an untrusted master are allowed. + * 0b1..Accesses from an untrusted master are not allowed. + */ #define AIPS_PACRJ_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP6_SHIFT)) & AIPS_PACRJ_TP6_MASK) #define AIPS_PACRJ_WP6_MASK (0x20U) #define AIPS_PACRJ_WP6_SHIFT (5U) +/*! WP6 - Write Protect + * 0b0..This peripheral allows write accesses. + * 0b1..This peripheral is write protected. + */ #define AIPS_PACRJ_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP6_SHIFT)) & AIPS_PACRJ_WP6_MASK) #define AIPS_PACRJ_SP6_MASK (0x40U) #define AIPS_PACRJ_SP6_SHIFT (6U) +/*! SP6 - Supervisor Protect + * 0b0..This peripheral does not require supervisor privilege level for accesses. + * 0b1..This peripheral requires supervisor privilege level for accesses. + */ #define AIPS_PACRJ_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP6_SHIFT)) & AIPS_PACRJ_SP6_MASK) #define AIPS_PACRJ_TP5_MASK (0x100U) #define AIPS_PACRJ_TP5_SHIFT (8U) +/*! TP5 - Trusted Protect + * 0b0..Accesses from an untrusted master are allowed. + * 0b1..Accesses from an untrusted master are not allowed. + */ #define AIPS_PACRJ_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP5_SHIFT)) & AIPS_PACRJ_TP5_MASK) #define AIPS_PACRJ_WP5_MASK (0x200U) #define AIPS_PACRJ_WP5_SHIFT (9U) +/*! WP5 - Write Protect + * 0b0..This peripheral allows write accesses. + * 0b1..This peripheral is write protected. + */ #define AIPS_PACRJ_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP5_SHIFT)) & AIPS_PACRJ_WP5_MASK) #define AIPS_PACRJ_SP5_MASK (0x400U) #define AIPS_PACRJ_SP5_SHIFT (10U) +/*! SP5 - Supervisor Protect + * 0b0..This peripheral does not require supervisor privilege level for accesses. + * 0b1..This peripheral requires supervisor privilege level for accesses. + */ #define AIPS_PACRJ_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP5_SHIFT)) & AIPS_PACRJ_SP5_MASK) #define AIPS_PACRJ_TP4_MASK (0x1000U) #define AIPS_PACRJ_TP4_SHIFT (12U) +/*! TP4 - Trusted Protect + * 0b0..Accesses from an untrusted master are allowed. + * 0b1..Accesses from an untrusted master are not allowed. + */ #define AIPS_PACRJ_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP4_SHIFT)) & AIPS_PACRJ_TP4_MASK) #define AIPS_PACRJ_WP4_MASK (0x2000U) #define AIPS_PACRJ_WP4_SHIFT (13U) +/*! WP4 - Write Protect + * 0b0..This peripheral allows write accesses. + * 0b1..This peripheral is write protected. + */ #define AIPS_PACRJ_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP4_SHIFT)) & AIPS_PACRJ_WP4_MASK) #define AIPS_PACRJ_SP4_MASK (0x4000U) #define AIPS_PACRJ_SP4_SHIFT (14U) +/*! SP4 - Supervisor Protect + * 0b0..This peripheral does not require supervisor privilege level for accesses. + * 0b1..This peripheral requires supervisor privilege level for accesses. + */ #define AIPS_PACRJ_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP4_SHIFT)) & AIPS_PACRJ_SP4_MASK) #define AIPS_PACRJ_TP3_MASK (0x10000U) #define AIPS_PACRJ_TP3_SHIFT (16U) +/*! TP3 - Trusted Protect + * 0b0..Accesses from an untrusted master are allowed. + * 0b1..Accesses from an untrusted master are not allowed. + */ #define AIPS_PACRJ_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP3_SHIFT)) & AIPS_PACRJ_TP3_MASK) #define AIPS_PACRJ_WP3_MASK (0x20000U) #define AIPS_PACRJ_WP3_SHIFT (17U) +/*! WP3 - Write Protect + * 0b0..This peripheral allows write accesses. + * 0b1..This peripheral is write protected. + */ #define AIPS_PACRJ_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP3_SHIFT)) & AIPS_PACRJ_WP3_MASK) #define AIPS_PACRJ_SP3_MASK (0x40000U) #define AIPS_PACRJ_SP3_SHIFT (18U) +/*! SP3 - Supervisor Protect + * 0b0..This peripheral does not require supervisor privilege level for accesses. + * 0b1..This peripheral requires supervisor privilege level for accesses. + */ #define AIPS_PACRJ_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP3_SHIFT)) & AIPS_PACRJ_SP3_MASK) #define AIPS_PACRJ_TP2_MASK (0x100000U) #define AIPS_PACRJ_TP2_SHIFT (20U) +/*! TP2 - Trusted Protect + * 0b0..Accesses from an untrusted master are allowed. + * 0b1..Accesses from an untrusted master are not allowed. + */ #define AIPS_PACRJ_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP2_SHIFT)) & AIPS_PACRJ_TP2_MASK) #define AIPS_PACRJ_WP2_MASK (0x200000U) #define AIPS_PACRJ_WP2_SHIFT (21U) +/*! WP2 - Write Protect + * 0b0..This peripheral allows write accesses. + * 0b1..This peripheral is write protected. + */ #define AIPS_PACRJ_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP2_SHIFT)) & AIPS_PACRJ_WP2_MASK) #define AIPS_PACRJ_SP2_MASK (0x400000U) #define AIPS_PACRJ_SP2_SHIFT (22U) +/*! SP2 - Supervisor Protect + * 0b0..This peripheral does not require supervisor privilege level for accesses. + * 0b1..This peripheral requires supervisor privilege level for accesses. + */ #define AIPS_PACRJ_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP2_SHIFT)) & AIPS_PACRJ_SP2_MASK) #define AIPS_PACRJ_TP1_MASK (0x1000000U) #define AIPS_PACRJ_TP1_SHIFT (24U) +/*! TP1 - Trusted Protect + * 0b0..Accesses from an untrusted master are allowed. + * 0b1..Accesses from an untrusted master are not allowed. + */ #define AIPS_PACRJ_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP1_SHIFT)) & AIPS_PACRJ_TP1_MASK) #define AIPS_PACRJ_WP1_MASK (0x2000000U) #define AIPS_PACRJ_WP1_SHIFT (25U) +/*! WP1 - Write Protect + * 0b0..This peripheral allows write accesses. + * 0b1..This peripheral is write protected. + */ #define AIPS_PACRJ_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP1_SHIFT)) & AIPS_PACRJ_WP1_MASK) #define AIPS_PACRJ_SP1_MASK (0x4000000U) #define AIPS_PACRJ_SP1_SHIFT (26U) +/*! SP1 - Supervisor Protect + * 0b0..This peripheral does not require supervisor privilege level for accesses. + * 0b1..This peripheral requires supervisor privilege level for accesses. + */ #define AIPS_PACRJ_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP1_SHIFT)) & AIPS_PACRJ_SP1_MASK) #define AIPS_PACRJ_TP0_MASK (0x10000000U) #define AIPS_PACRJ_TP0_SHIFT (28U) +/*! TP0 - Trusted Protect + * 0b0..Accesses from an untrusted master are allowed. + * 0b1..Accesses from an untrusted master are not allowed. + */ #define AIPS_PACRJ_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP0_SHIFT)) & AIPS_PACRJ_TP0_MASK) #define AIPS_PACRJ_WP0_MASK (0x20000000U) #define AIPS_PACRJ_WP0_SHIFT (29U) +/*! WP0 - Write Protect + * 0b0..This peripheral allows write accesses. + * 0b1..This peripheral is write protected. + */ #define AIPS_PACRJ_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP0_SHIFT)) & AIPS_PACRJ_WP0_MASK) #define AIPS_PACRJ_SP0_MASK (0x40000000U) #define AIPS_PACRJ_SP0_SHIFT (30U) +/*! SP0 - Supervisor Protect + * 0b0..This peripheral does not require supervisor privilege level for accesses. + * 0b1..This peripheral requires supervisor privilege level for accesses. + */ #define AIPS_PACRJ_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP0_SHIFT)) & AIPS_PACRJ_SP0_MASK) +/*! @} */ /*! @name PACRK - Peripheral Access Control Register */ +/*! @{ */ #define AIPS_PACRK_TP7_MASK (0x1U) #define AIPS_PACRK_TP7_SHIFT (0U) +/*! TP7 - Trusted Protect + * 0b0..Accesses from an untrusted master are allowed. + * 0b1..Accesses from an untrusted master are not allowed. + */ #define AIPS_PACRK_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP7_SHIFT)) & AIPS_PACRK_TP7_MASK) #define AIPS_PACRK_WP7_MASK (0x2U) #define AIPS_PACRK_WP7_SHIFT (1U) +/*! WP7 - Write Protect + * 0b0..This peripheral allows write accesses. + * 0b1..This peripheral is write protected. + */ #define AIPS_PACRK_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP7_SHIFT)) & AIPS_PACRK_WP7_MASK) #define AIPS_PACRK_SP7_MASK (0x4U) #define AIPS_PACRK_SP7_SHIFT (2U) +/*! SP7 - Supervisor Protect + * 0b0..This peripheral does not require supervisor privilege level for accesses. + * 0b1..This peripheral requires supervisor privilege level for accesses. + */ #define AIPS_PACRK_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP7_SHIFT)) & AIPS_PACRK_SP7_MASK) #define AIPS_PACRK_TP6_MASK (0x10U) #define AIPS_PACRK_TP6_SHIFT (4U) +/*! TP6 - Trusted Protect + * 0b0..Accesses from an untrusted master are allowed. + * 0b1..Accesses from an untrusted master are not allowed. + */ #define AIPS_PACRK_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP6_SHIFT)) & AIPS_PACRK_TP6_MASK) #define AIPS_PACRK_WP6_MASK (0x20U) #define AIPS_PACRK_WP6_SHIFT (5U) +/*! WP6 - Write Protect + * 0b0..This peripheral allows write accesses. + * 0b1..This peripheral is write protected. + */ #define AIPS_PACRK_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP6_SHIFT)) & AIPS_PACRK_WP6_MASK) #define AIPS_PACRK_SP6_MASK (0x40U) #define AIPS_PACRK_SP6_SHIFT (6U) +/*! SP6 - Supervisor Protect + * 0b0..This peripheral does not require supervisor privilege level for accesses. + * 0b1..This peripheral requires supervisor privilege level for accesses. + */ #define AIPS_PACRK_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP6_SHIFT)) & AIPS_PACRK_SP6_MASK) #define AIPS_PACRK_TP5_MASK (0x100U) #define AIPS_PACRK_TP5_SHIFT (8U) +/*! TP5 - Trusted Protect + * 0b0..Accesses from an untrusted master are allowed. + * 0b1..Accesses from an untrusted master are not allowed. + */ #define AIPS_PACRK_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP5_SHIFT)) & AIPS_PACRK_TP5_MASK) #define AIPS_PACRK_WP5_MASK (0x200U) #define AIPS_PACRK_WP5_SHIFT (9U) +/*! WP5 - Write Protect + * 0b0..This peripheral allows write accesses. + * 0b1..This peripheral is write protected. + */ #define AIPS_PACRK_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP5_SHIFT)) & AIPS_PACRK_WP5_MASK) #define AIPS_PACRK_SP5_MASK (0x400U) #define AIPS_PACRK_SP5_SHIFT (10U) +/*! SP5 - Supervisor Protect + * 0b0..This peripheral does not require supervisor privilege level for accesses. + * 0b1..This peripheral requires supervisor privilege level for accesses. + */ #define AIPS_PACRK_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP5_SHIFT)) & AIPS_PACRK_SP5_MASK) #define AIPS_PACRK_TP4_MASK (0x1000U) #define AIPS_PACRK_TP4_SHIFT (12U) +/*! TP4 - Trusted Protect + * 0b0..Accesses from an untrusted master are allowed. + * 0b1..Accesses from an untrusted master are not allowed. + */ #define AIPS_PACRK_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP4_SHIFT)) & AIPS_PACRK_TP4_MASK) #define AIPS_PACRK_WP4_MASK (0x2000U) #define AIPS_PACRK_WP4_SHIFT (13U) +/*! WP4 - Write Protect + * 0b0..This peripheral allows write accesses. + * 0b1..This peripheral is write protected. + */ #define AIPS_PACRK_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP4_SHIFT)) & AIPS_PACRK_WP4_MASK) #define AIPS_PACRK_SP4_MASK (0x4000U) #define AIPS_PACRK_SP4_SHIFT (14U) +/*! SP4 - Supervisor Protect + * 0b0..This peripheral does not require supervisor privilege level for accesses. + * 0b1..This peripheral requires supervisor privilege level for accesses. + */ #define AIPS_PACRK_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP4_SHIFT)) & AIPS_PACRK_SP4_MASK) #define AIPS_PACRK_TP3_MASK (0x10000U) #define AIPS_PACRK_TP3_SHIFT (16U) +/*! TP3 - Trusted Protect + * 0b0..Accesses from an untrusted master are allowed. + * 0b1..Accesses from an untrusted master are not allowed. + */ #define AIPS_PACRK_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP3_SHIFT)) & AIPS_PACRK_TP3_MASK) #define AIPS_PACRK_WP3_MASK (0x20000U) #define AIPS_PACRK_WP3_SHIFT (17U) +/*! WP3 - Write Protect + * 0b0..This peripheral allows write accesses. + * 0b1..This peripheral is write protected. + */ #define AIPS_PACRK_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP3_SHIFT)) & AIPS_PACRK_WP3_MASK) #define AIPS_PACRK_SP3_MASK (0x40000U) #define AIPS_PACRK_SP3_SHIFT (18U) +/*! SP3 - Supervisor Protect + * 0b0..This peripheral does not require supervisor privilege level for accesses. + * 0b1..This peripheral requires supervisor privilege level for accesses. + */ #define AIPS_PACRK_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP3_SHIFT)) & AIPS_PACRK_SP3_MASK) #define AIPS_PACRK_TP2_MASK (0x100000U) #define AIPS_PACRK_TP2_SHIFT (20U) +/*! TP2 - Trusted Protect + * 0b0..Accesses from an untrusted master are allowed. + * 0b1..Accesses from an untrusted master are not allowed. + */ #define AIPS_PACRK_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP2_SHIFT)) & AIPS_PACRK_TP2_MASK) #define AIPS_PACRK_WP2_MASK (0x200000U) #define AIPS_PACRK_WP2_SHIFT (21U) +/*! WP2 - Write Protect + * 0b0..This peripheral allows write accesses. + * 0b1..This peripheral is write protected. + */ #define AIPS_PACRK_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP2_SHIFT)) & AIPS_PACRK_WP2_MASK) #define AIPS_PACRK_SP2_MASK (0x400000U) #define AIPS_PACRK_SP2_SHIFT (22U) +/*! SP2 - Supervisor Protect + * 0b0..This peripheral does not require supervisor privilege level for accesses. + * 0b1..This peripheral requires supervisor privilege level for accesses. + */ #define AIPS_PACRK_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP2_SHIFT)) & AIPS_PACRK_SP2_MASK) #define AIPS_PACRK_TP1_MASK (0x1000000U) #define AIPS_PACRK_TP1_SHIFT (24U) +/*! TP1 - Trusted Protect + * 0b0..Accesses from an untrusted master are allowed. + * 0b1..Accesses from an untrusted master are not allowed. + */ #define AIPS_PACRK_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP1_SHIFT)) & AIPS_PACRK_TP1_MASK) #define AIPS_PACRK_WP1_MASK (0x2000000U) #define AIPS_PACRK_WP1_SHIFT (25U) +/*! WP1 - Write Protect + * 0b0..This peripheral allows write accesses. + * 0b1..This peripheral is write protected. + */ #define AIPS_PACRK_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP1_SHIFT)) & AIPS_PACRK_WP1_MASK) #define AIPS_PACRK_SP1_MASK (0x4000000U) #define AIPS_PACRK_SP1_SHIFT (26U) +/*! SP1 - Supervisor Protect + * 0b0..This peripheral does not require supervisor privilege level for accesses. + * 0b1..This peripheral requires supervisor privilege level for accesses. + */ #define AIPS_PACRK_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP1_SHIFT)) & AIPS_PACRK_SP1_MASK) #define AIPS_PACRK_TP0_MASK (0x10000000U) #define AIPS_PACRK_TP0_SHIFT (28U) +/*! TP0 - Trusted Protect + * 0b0..Accesses from an untrusted master are allowed. + * 0b1..Accesses from an untrusted master are not allowed. + */ #define AIPS_PACRK_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP0_SHIFT)) & AIPS_PACRK_TP0_MASK) #define AIPS_PACRK_WP0_MASK (0x20000000U) #define AIPS_PACRK_WP0_SHIFT (29U) +/*! WP0 - Write Protect + * 0b0..This peripheral allows write accesses. + * 0b1..This peripheral is write protected. + */ #define AIPS_PACRK_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP0_SHIFT)) & AIPS_PACRK_WP0_MASK) #define AIPS_PACRK_SP0_MASK (0x40000000U) #define AIPS_PACRK_SP0_SHIFT (30U) +/*! SP0 - Supervisor Protect + * 0b0..This peripheral does not require supervisor privilege level for accesses. + * 0b1..This peripheral requires supervisor privilege level for accesses. + */ #define AIPS_PACRK_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP0_SHIFT)) & AIPS_PACRK_SP0_MASK) +/*! @} */ /*! @name PACRL - Peripheral Access Control Register */ +/*! @{ */ #define AIPS_PACRL_TP7_MASK (0x1U) #define AIPS_PACRL_TP7_SHIFT (0U) +/*! TP7 - Trusted Protect + * 0b0..Accesses from an untrusted master are allowed. + * 0b1..Accesses from an untrusted master are not allowed. + */ #define AIPS_PACRL_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP7_SHIFT)) & AIPS_PACRL_TP7_MASK) #define AIPS_PACRL_WP7_MASK (0x2U) #define AIPS_PACRL_WP7_SHIFT (1U) +/*! WP7 - Write Protect + * 0b0..This peripheral allows write accesses. + * 0b1..This peripheral is write protected. + */ #define AIPS_PACRL_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP7_SHIFT)) & AIPS_PACRL_WP7_MASK) #define AIPS_PACRL_SP7_MASK (0x4U) #define AIPS_PACRL_SP7_SHIFT (2U) +/*! SP7 - Supervisor Protect + * 0b0..This peripheral does not require supervisor privilege level for accesses. + * 0b1..This peripheral requires supervisor privilege level for accesses. + */ #define AIPS_PACRL_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP7_SHIFT)) & AIPS_PACRL_SP7_MASK) #define AIPS_PACRL_TP6_MASK (0x10U) #define AIPS_PACRL_TP6_SHIFT (4U) +/*! TP6 - Trusted Protect + * 0b0..Accesses from an untrusted master are allowed. + * 0b1..Accesses from an untrusted master are not allowed. + */ #define AIPS_PACRL_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP6_SHIFT)) & AIPS_PACRL_TP6_MASK) #define AIPS_PACRL_WP6_MASK (0x20U) #define AIPS_PACRL_WP6_SHIFT (5U) +/*! WP6 - Write Protect + * 0b0..This peripheral allows write accesses. + * 0b1..This peripheral is write protected. + */ #define AIPS_PACRL_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP6_SHIFT)) & AIPS_PACRL_WP6_MASK) #define AIPS_PACRL_SP6_MASK (0x40U) #define AIPS_PACRL_SP6_SHIFT (6U) +/*! SP6 - Supervisor Protect + * 0b0..This peripheral does not require supervisor privilege level for accesses. + * 0b1..This peripheral requires supervisor privilege level for accesses. + */ #define AIPS_PACRL_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP6_SHIFT)) & AIPS_PACRL_SP6_MASK) #define AIPS_PACRL_TP5_MASK (0x100U) #define AIPS_PACRL_TP5_SHIFT (8U) +/*! TP5 - Trusted Protect + * 0b0..Accesses from an untrusted master are allowed. + * 0b1..Accesses from an untrusted master are not allowed. + */ #define AIPS_PACRL_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP5_SHIFT)) & AIPS_PACRL_TP5_MASK) #define AIPS_PACRL_WP5_MASK (0x200U) #define AIPS_PACRL_WP5_SHIFT (9U) +/*! WP5 - Write Protect + * 0b0..This peripheral allows write accesses. + * 0b1..This peripheral is write protected. + */ #define AIPS_PACRL_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP5_SHIFT)) & AIPS_PACRL_WP5_MASK) #define AIPS_PACRL_SP5_MASK (0x400U) #define AIPS_PACRL_SP5_SHIFT (10U) +/*! SP5 - Supervisor Protect + * 0b0..This peripheral does not require supervisor privilege level for accesses. + * 0b1..This peripheral requires supervisor privilege level for accesses. + */ #define AIPS_PACRL_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP5_SHIFT)) & AIPS_PACRL_SP5_MASK) #define AIPS_PACRL_TP4_MASK (0x1000U) #define AIPS_PACRL_TP4_SHIFT (12U) +/*! TP4 - Trusted Protect + * 0b0..Accesses from an untrusted master are allowed. + * 0b1..Accesses from an untrusted master are not allowed. + */ #define AIPS_PACRL_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP4_SHIFT)) & AIPS_PACRL_TP4_MASK) #define AIPS_PACRL_WP4_MASK (0x2000U) #define AIPS_PACRL_WP4_SHIFT (13U) +/*! WP4 - Write Protect + * 0b0..This peripheral allows write accesses. + * 0b1..This peripheral is write protected. + */ #define AIPS_PACRL_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP4_SHIFT)) & AIPS_PACRL_WP4_MASK) #define AIPS_PACRL_SP4_MASK (0x4000U) #define AIPS_PACRL_SP4_SHIFT (14U) +/*! SP4 - Supervisor Protect + * 0b0..This peripheral does not require supervisor privilege level for accesses. + * 0b1..This peripheral requires supervisor privilege level for accesses. + */ #define AIPS_PACRL_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP4_SHIFT)) & AIPS_PACRL_SP4_MASK) #define AIPS_PACRL_TP3_MASK (0x10000U) #define AIPS_PACRL_TP3_SHIFT (16U) +/*! TP3 - Trusted Protect + * 0b0..Accesses from an untrusted master are allowed. + * 0b1..Accesses from an untrusted master are not allowed. + */ #define AIPS_PACRL_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP3_SHIFT)) & AIPS_PACRL_TP3_MASK) #define AIPS_PACRL_WP3_MASK (0x20000U) #define AIPS_PACRL_WP3_SHIFT (17U) +/*! WP3 - Write Protect + * 0b0..This peripheral allows write accesses. + * 0b1..This peripheral is write protected. + */ #define AIPS_PACRL_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP3_SHIFT)) & AIPS_PACRL_WP3_MASK) #define AIPS_PACRL_SP3_MASK (0x40000U) #define AIPS_PACRL_SP3_SHIFT (18U) +/*! SP3 - Supervisor Protect + * 0b0..This peripheral does not require supervisor privilege level for accesses. + * 0b1..This peripheral requires supervisor privilege level for accesses. + */ #define AIPS_PACRL_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP3_SHIFT)) & AIPS_PACRL_SP3_MASK) #define AIPS_PACRL_TP2_MASK (0x100000U) #define AIPS_PACRL_TP2_SHIFT (20U) +/*! TP2 - Trusted Protect + * 0b0..Accesses from an untrusted master are allowed. + * 0b1..Accesses from an untrusted master are not allowed. + */ #define AIPS_PACRL_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP2_SHIFT)) & AIPS_PACRL_TP2_MASK) #define AIPS_PACRL_WP2_MASK (0x200000U) #define AIPS_PACRL_WP2_SHIFT (21U) +/*! WP2 - Write Protect + * 0b0..This peripheral allows write accesses. + * 0b1..This peripheral is write protected. + */ #define AIPS_PACRL_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP2_SHIFT)) & AIPS_PACRL_WP2_MASK) #define AIPS_PACRL_SP2_MASK (0x400000U) #define AIPS_PACRL_SP2_SHIFT (22U) +/*! SP2 - Supervisor Protect + * 0b0..This peripheral does not require supervisor privilege level for accesses. + * 0b1..This peripheral requires supervisor privilege level for accesses. + */ #define AIPS_PACRL_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP2_SHIFT)) & AIPS_PACRL_SP2_MASK) #define AIPS_PACRL_TP1_MASK (0x1000000U) #define AIPS_PACRL_TP1_SHIFT (24U) +/*! TP1 - Trusted Protect + * 0b0..Accesses from an untrusted master are allowed. + * 0b1..Accesses from an untrusted master are not allowed. + */ #define AIPS_PACRL_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP1_SHIFT)) & AIPS_PACRL_TP1_MASK) #define AIPS_PACRL_WP1_MASK (0x2000000U) #define AIPS_PACRL_WP1_SHIFT (25U) +/*! WP1 - Write Protect + * 0b0..This peripheral allows write accesses. + * 0b1..This peripheral is write protected. + */ #define AIPS_PACRL_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP1_SHIFT)) & AIPS_PACRL_WP1_MASK) #define AIPS_PACRL_SP1_MASK (0x4000000U) #define AIPS_PACRL_SP1_SHIFT (26U) +/*! SP1 - Supervisor Protect + * 0b0..This peripheral does not require supervisor privilege level for accesses. + * 0b1..This peripheral requires supervisor privilege level for accesses. + */ #define AIPS_PACRL_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP1_SHIFT)) & AIPS_PACRL_SP1_MASK) #define AIPS_PACRL_TP0_MASK (0x10000000U) #define AIPS_PACRL_TP0_SHIFT (28U) +/*! TP0 - Trusted Protect + * 0b0..Accesses from an untrusted master are allowed. + * 0b1..Accesses from an untrusted master are not allowed. + */ #define AIPS_PACRL_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP0_SHIFT)) & AIPS_PACRL_TP0_MASK) #define AIPS_PACRL_WP0_MASK (0x20000000U) #define AIPS_PACRL_WP0_SHIFT (29U) +/*! WP0 - Write Protect + * 0b0..This peripheral allows write accesses. + * 0b1..This peripheral is write protected. + */ #define AIPS_PACRL_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP0_SHIFT)) & AIPS_PACRL_WP0_MASK) #define AIPS_PACRL_SP0_MASK (0x40000000U) #define AIPS_PACRL_SP0_SHIFT (30U) +/*! SP0 - Supervisor Protect + * 0b0..This peripheral does not require supervisor privilege level for accesses. + * 0b1..This peripheral requires supervisor privilege level for accesses. + */ #define AIPS_PACRL_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP0_SHIFT)) & AIPS_PACRL_SP0_MASK) +/*! @} */ /*! @name PACRM - Peripheral Access Control Register */ +/*! @{ */ #define AIPS_PACRM_TP7_MASK (0x1U) #define AIPS_PACRM_TP7_SHIFT (0U) +/*! TP7 - Trusted Protect + * 0b0..Accesses from an untrusted master are allowed. + * 0b1..Accesses from an untrusted master are not allowed. + */ #define AIPS_PACRM_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP7_SHIFT)) & AIPS_PACRM_TP7_MASK) #define AIPS_PACRM_WP7_MASK (0x2U) #define AIPS_PACRM_WP7_SHIFT (1U) +/*! WP7 - Write Protect + * 0b0..This peripheral allows write accesses. + * 0b1..This peripheral is write protected. + */ #define AIPS_PACRM_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP7_SHIFT)) & AIPS_PACRM_WP7_MASK) #define AIPS_PACRM_SP7_MASK (0x4U) #define AIPS_PACRM_SP7_SHIFT (2U) +/*! SP7 - Supervisor Protect + * 0b0..This peripheral does not require supervisor privilege level for accesses. + * 0b1..This peripheral requires supervisor privilege level for accesses. + */ #define AIPS_PACRM_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP7_SHIFT)) & AIPS_PACRM_SP7_MASK) #define AIPS_PACRM_TP6_MASK (0x10U) #define AIPS_PACRM_TP6_SHIFT (4U) +/*! TP6 - Trusted Protect + * 0b0..Accesses from an untrusted master are allowed. + * 0b1..Accesses from an untrusted master are not allowed. + */ #define AIPS_PACRM_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP6_SHIFT)) & AIPS_PACRM_TP6_MASK) #define AIPS_PACRM_WP6_MASK (0x20U) #define AIPS_PACRM_WP6_SHIFT (5U) +/*! WP6 - Write Protect + * 0b0..This peripheral allows write accesses. + * 0b1..This peripheral is write protected. + */ #define AIPS_PACRM_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP6_SHIFT)) & AIPS_PACRM_WP6_MASK) #define AIPS_PACRM_SP6_MASK (0x40U) #define AIPS_PACRM_SP6_SHIFT (6U) +/*! SP6 - Supervisor Protect + * 0b0..This peripheral does not require supervisor privilege level for accesses. + * 0b1..This peripheral requires supervisor privilege level for accesses. + */ #define AIPS_PACRM_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP6_SHIFT)) & AIPS_PACRM_SP6_MASK) #define AIPS_PACRM_TP5_MASK (0x100U) #define AIPS_PACRM_TP5_SHIFT (8U) +/*! TP5 - Trusted Protect + * 0b0..Accesses from an untrusted master are allowed. + * 0b1..Accesses from an untrusted master are not allowed. + */ #define AIPS_PACRM_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP5_SHIFT)) & AIPS_PACRM_TP5_MASK) #define AIPS_PACRM_WP5_MASK (0x200U) #define AIPS_PACRM_WP5_SHIFT (9U) +/*! WP5 - Write Protect + * 0b0..This peripheral allows write accesses. + * 0b1..This peripheral is write protected. + */ #define AIPS_PACRM_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP5_SHIFT)) & AIPS_PACRM_WP5_MASK) #define AIPS_PACRM_SP5_MASK (0x400U) #define AIPS_PACRM_SP5_SHIFT (10U) +/*! SP5 - Supervisor Protect + * 0b0..This peripheral does not require supervisor privilege level for accesses. + * 0b1..This peripheral requires supervisor privilege level for accesses. + */ #define AIPS_PACRM_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP5_SHIFT)) & AIPS_PACRM_SP5_MASK) #define AIPS_PACRM_TP4_MASK (0x1000U) #define AIPS_PACRM_TP4_SHIFT (12U) +/*! TP4 - Trusted Protect + * 0b0..Accesses from an untrusted master are allowed. + * 0b1..Accesses from an untrusted master are not allowed. + */ #define AIPS_PACRM_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP4_SHIFT)) & AIPS_PACRM_TP4_MASK) #define AIPS_PACRM_WP4_MASK (0x2000U) #define AIPS_PACRM_WP4_SHIFT (13U) +/*! WP4 - Write Protect + * 0b0..This peripheral allows write accesses. + * 0b1..This peripheral is write protected. + */ #define AIPS_PACRM_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP4_SHIFT)) & AIPS_PACRM_WP4_MASK) #define AIPS_PACRM_SP4_MASK (0x4000U) #define AIPS_PACRM_SP4_SHIFT (14U) +/*! SP4 - Supervisor Protect + * 0b0..This peripheral does not require supervisor privilege level for accesses. + * 0b1..This peripheral requires supervisor privilege level for accesses. + */ #define AIPS_PACRM_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP4_SHIFT)) & AIPS_PACRM_SP4_MASK) #define AIPS_PACRM_TP3_MASK (0x10000U) #define AIPS_PACRM_TP3_SHIFT (16U) +/*! TP3 - Trusted Protect + * 0b0..Accesses from an untrusted master are allowed. + * 0b1..Accesses from an untrusted master are not allowed. + */ #define AIPS_PACRM_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP3_SHIFT)) & AIPS_PACRM_TP3_MASK) #define AIPS_PACRM_WP3_MASK (0x20000U) #define AIPS_PACRM_WP3_SHIFT (17U) +/*! WP3 - Write Protect + * 0b0..This peripheral allows write accesses. + * 0b1..This peripheral is write protected. + */ #define AIPS_PACRM_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP3_SHIFT)) & AIPS_PACRM_WP3_MASK) #define AIPS_PACRM_SP3_MASK (0x40000U) #define AIPS_PACRM_SP3_SHIFT (18U) +/*! SP3 - Supervisor Protect + * 0b0..This peripheral does not require supervisor privilege level for accesses. + * 0b1..This peripheral requires supervisor privilege level for accesses. + */ #define AIPS_PACRM_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP3_SHIFT)) & AIPS_PACRM_SP3_MASK) #define AIPS_PACRM_TP2_MASK (0x100000U) #define AIPS_PACRM_TP2_SHIFT (20U) +/*! TP2 - Trusted Protect + * 0b0..Accesses from an untrusted master are allowed. + * 0b1..Accesses from an untrusted master are not allowed. + */ #define AIPS_PACRM_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP2_SHIFT)) & AIPS_PACRM_TP2_MASK) #define AIPS_PACRM_WP2_MASK (0x200000U) #define AIPS_PACRM_WP2_SHIFT (21U) +/*! WP2 - Write Protect + * 0b0..This peripheral allows write accesses. + * 0b1..This peripheral is write protected. + */ #define AIPS_PACRM_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP2_SHIFT)) & AIPS_PACRM_WP2_MASK) #define AIPS_PACRM_SP2_MASK (0x400000U) #define AIPS_PACRM_SP2_SHIFT (22U) +/*! SP2 - Supervisor Protect + * 0b0..This peripheral does not require supervisor privilege level for accesses. + * 0b1..This peripheral requires supervisor privilege level for accesses. + */ #define AIPS_PACRM_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP2_SHIFT)) & AIPS_PACRM_SP2_MASK) #define AIPS_PACRM_TP1_MASK (0x1000000U) #define AIPS_PACRM_TP1_SHIFT (24U) +/*! TP1 - Trusted Protect + * 0b0..Accesses from an untrusted master are allowed. + * 0b1..Accesses from an untrusted master are not allowed. + */ #define AIPS_PACRM_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP1_SHIFT)) & AIPS_PACRM_TP1_MASK) #define AIPS_PACRM_WP1_MASK (0x2000000U) #define AIPS_PACRM_WP1_SHIFT (25U) +/*! WP1 - Write Protect + * 0b0..This peripheral allows write accesses. + * 0b1..This peripheral is write protected. + */ #define AIPS_PACRM_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP1_SHIFT)) & AIPS_PACRM_WP1_MASK) #define AIPS_PACRM_SP1_MASK (0x4000000U) #define AIPS_PACRM_SP1_SHIFT (26U) +/*! SP1 - Supervisor Protect + * 0b0..This peripheral does not require supervisor privilege level for accesses. + * 0b1..This peripheral requires supervisor privilege level for accesses. + */ #define AIPS_PACRM_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP1_SHIFT)) & AIPS_PACRM_SP1_MASK) #define AIPS_PACRM_TP0_MASK (0x10000000U) #define AIPS_PACRM_TP0_SHIFT (28U) +/*! TP0 - Trusted Protect + * 0b0..Accesses from an untrusted master are allowed. + * 0b1..Accesses from an untrusted master are not allowed. + */ #define AIPS_PACRM_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP0_SHIFT)) & AIPS_PACRM_TP0_MASK) #define AIPS_PACRM_WP0_MASK (0x20000000U) #define AIPS_PACRM_WP0_SHIFT (29U) +/*! WP0 - Write Protect + * 0b0..This peripheral allows write accesses. + * 0b1..This peripheral is write protected. + */ #define AIPS_PACRM_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP0_SHIFT)) & AIPS_PACRM_WP0_MASK) #define AIPS_PACRM_SP0_MASK (0x40000000U) #define AIPS_PACRM_SP0_SHIFT (30U) +/*! SP0 - Supervisor Protect + * 0b0..This peripheral does not require supervisor privilege level for accesses. + * 0b1..This peripheral requires supervisor privilege level for accesses. + */ #define AIPS_PACRM_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP0_SHIFT)) & AIPS_PACRM_SP0_MASK) +/*! @} */ /*! @name PACRN - Peripheral Access Control Register */ +/*! @{ */ #define AIPS_PACRN_TP7_MASK (0x1U) #define AIPS_PACRN_TP7_SHIFT (0U) +/*! TP7 - Trusted Protect + * 0b0..Accesses from an untrusted master are allowed. + * 0b1..Accesses from an untrusted master are not allowed. + */ #define AIPS_PACRN_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP7_SHIFT)) & AIPS_PACRN_TP7_MASK) #define AIPS_PACRN_WP7_MASK (0x2U) #define AIPS_PACRN_WP7_SHIFT (1U) +/*! WP7 - Write Protect + * 0b0..This peripheral allows write accesses. + * 0b1..This peripheral is write protected. + */ #define AIPS_PACRN_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP7_SHIFT)) & AIPS_PACRN_WP7_MASK) #define AIPS_PACRN_SP7_MASK (0x4U) #define AIPS_PACRN_SP7_SHIFT (2U) +/*! SP7 - Supervisor Protect + * 0b0..This peripheral does not require supervisor privilege level for accesses. + * 0b1..This peripheral requires supervisor privilege level for accesses. + */ #define AIPS_PACRN_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP7_SHIFT)) & AIPS_PACRN_SP7_MASK) #define AIPS_PACRN_TP6_MASK (0x10U) #define AIPS_PACRN_TP6_SHIFT (4U) +/*! TP6 - Trusted Protect + * 0b0..Accesses from an untrusted master are allowed. + * 0b1..Accesses from an untrusted master are not allowed. + */ #define AIPS_PACRN_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP6_SHIFT)) & AIPS_PACRN_TP6_MASK) #define AIPS_PACRN_WP6_MASK (0x20U) #define AIPS_PACRN_WP6_SHIFT (5U) +/*! WP6 - Write Protect + * 0b0..This peripheral allows write accesses. + * 0b1..This peripheral is write protected. + */ #define AIPS_PACRN_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP6_SHIFT)) & AIPS_PACRN_WP6_MASK) #define AIPS_PACRN_SP6_MASK (0x40U) #define AIPS_PACRN_SP6_SHIFT (6U) +/*! SP6 - Supervisor Protect + * 0b0..This peripheral does not require supervisor privilege level for accesses. + * 0b1..This peripheral requires supervisor privilege level for accesses. + */ #define AIPS_PACRN_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP6_SHIFT)) & AIPS_PACRN_SP6_MASK) #define AIPS_PACRN_TP5_MASK (0x100U) #define AIPS_PACRN_TP5_SHIFT (8U) +/*! TP5 - Trusted Protect + * 0b0..Accesses from an untrusted master are allowed. + * 0b1..Accesses from an untrusted master are not allowed. + */ #define AIPS_PACRN_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP5_SHIFT)) & AIPS_PACRN_TP5_MASK) #define AIPS_PACRN_WP5_MASK (0x200U) #define AIPS_PACRN_WP5_SHIFT (9U) +/*! WP5 - Write Protect + * 0b0..This peripheral allows write accesses. + * 0b1..This peripheral is write protected. + */ #define AIPS_PACRN_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP5_SHIFT)) & AIPS_PACRN_WP5_MASK) #define AIPS_PACRN_SP5_MASK (0x400U) #define AIPS_PACRN_SP5_SHIFT (10U) +/*! SP5 - Supervisor Protect + * 0b0..This peripheral does not require supervisor privilege level for accesses. + * 0b1..This peripheral requires supervisor privilege level for accesses. + */ #define AIPS_PACRN_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP5_SHIFT)) & AIPS_PACRN_SP5_MASK) #define AIPS_PACRN_TP4_MASK (0x1000U) #define AIPS_PACRN_TP4_SHIFT (12U) +/*! TP4 - Trusted Protect + * 0b0..Accesses from an untrusted master are allowed. + * 0b1..Accesses from an untrusted master are not allowed. + */ #define AIPS_PACRN_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP4_SHIFT)) & AIPS_PACRN_TP4_MASK) #define AIPS_PACRN_WP4_MASK (0x2000U) #define AIPS_PACRN_WP4_SHIFT (13U) +/*! WP4 - Write Protect + * 0b0..This peripheral allows write accesses. + * 0b1..This peripheral is write protected. + */ #define AIPS_PACRN_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP4_SHIFT)) & AIPS_PACRN_WP4_MASK) #define AIPS_PACRN_SP4_MASK (0x4000U) #define AIPS_PACRN_SP4_SHIFT (14U) +/*! SP4 - Supervisor Protect + * 0b0..This peripheral does not require supervisor privilege level for accesses. + * 0b1..This peripheral requires supervisor privilege level for accesses. + */ #define AIPS_PACRN_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP4_SHIFT)) & AIPS_PACRN_SP4_MASK) #define AIPS_PACRN_TP3_MASK (0x10000U) #define AIPS_PACRN_TP3_SHIFT (16U) +/*! TP3 - Trusted Protect + * 0b0..Accesses from an untrusted master are allowed. + * 0b1..Accesses from an untrusted master are not allowed. + */ #define AIPS_PACRN_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP3_SHIFT)) & AIPS_PACRN_TP3_MASK) #define AIPS_PACRN_WP3_MASK (0x20000U) #define AIPS_PACRN_WP3_SHIFT (17U) +/*! WP3 - Write Protect + * 0b0..This peripheral allows write accesses. + * 0b1..This peripheral is write protected. + */ #define AIPS_PACRN_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP3_SHIFT)) & AIPS_PACRN_WP3_MASK) #define AIPS_PACRN_SP3_MASK (0x40000U) #define AIPS_PACRN_SP3_SHIFT (18U) +/*! SP3 - Supervisor Protect + * 0b0..This peripheral does not require supervisor privilege level for accesses. + * 0b1..This peripheral requires supervisor privilege level for accesses. + */ #define AIPS_PACRN_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP3_SHIFT)) & AIPS_PACRN_SP3_MASK) #define AIPS_PACRN_TP2_MASK (0x100000U) #define AIPS_PACRN_TP2_SHIFT (20U) +/*! TP2 - Trusted Protect + * 0b0..Accesses from an untrusted master are allowed. + * 0b1..Accesses from an untrusted master are not allowed. + */ #define AIPS_PACRN_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP2_SHIFT)) & AIPS_PACRN_TP2_MASK) #define AIPS_PACRN_WP2_MASK (0x200000U) #define AIPS_PACRN_WP2_SHIFT (21U) +/*! WP2 - Write Protect + * 0b0..This peripheral allows write accesses. + * 0b1..This peripheral is write protected. + */ #define AIPS_PACRN_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP2_SHIFT)) & AIPS_PACRN_WP2_MASK) #define AIPS_PACRN_SP2_MASK (0x400000U) #define AIPS_PACRN_SP2_SHIFT (22U) +/*! SP2 - Supervisor Protect + * 0b0..This peripheral does not require supervisor privilege level for accesses. + * 0b1..This peripheral requires supervisor privilege level for accesses. + */ #define AIPS_PACRN_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP2_SHIFT)) & AIPS_PACRN_SP2_MASK) #define AIPS_PACRN_TP1_MASK (0x1000000U) #define AIPS_PACRN_TP1_SHIFT (24U) +/*! TP1 - Trusted Protect + * 0b0..Accesses from an untrusted master are allowed. + * 0b1..Accesses from an untrusted master are not allowed. + */ #define AIPS_PACRN_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP1_SHIFT)) & AIPS_PACRN_TP1_MASK) #define AIPS_PACRN_WP1_MASK (0x2000000U) #define AIPS_PACRN_WP1_SHIFT (25U) +/*! WP1 - Write Protect + * 0b0..This peripheral allows write accesses. + * 0b1..This peripheral is write protected. + */ #define AIPS_PACRN_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP1_SHIFT)) & AIPS_PACRN_WP1_MASK) #define AIPS_PACRN_SP1_MASK (0x4000000U) #define AIPS_PACRN_SP1_SHIFT (26U) +/*! SP1 - Supervisor Protect + * 0b0..This peripheral does not require supervisor privilege level for accesses. + * 0b1..This peripheral requires supervisor privilege level for accesses. + */ #define AIPS_PACRN_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP1_SHIFT)) & AIPS_PACRN_SP1_MASK) #define AIPS_PACRN_TP0_MASK (0x10000000U) #define AIPS_PACRN_TP0_SHIFT (28U) +/*! TP0 - Trusted Protect + * 0b0..Accesses from an untrusted master are allowed. + * 0b1..Accesses from an untrusted master are not allowed. + */ #define AIPS_PACRN_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP0_SHIFT)) & AIPS_PACRN_TP0_MASK) #define AIPS_PACRN_WP0_MASK (0x20000000U) #define AIPS_PACRN_WP0_SHIFT (29U) +/*! WP0 - Write Protect + * 0b0..This peripheral allows write accesses. + * 0b1..This peripheral is write protected. + */ #define AIPS_PACRN_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP0_SHIFT)) & AIPS_PACRN_WP0_MASK) #define AIPS_PACRN_SP0_MASK (0x40000000U) #define AIPS_PACRN_SP0_SHIFT (30U) +/*! SP0 - Supervisor Protect + * 0b0..This peripheral does not require supervisor privilege level for accesses. + * 0b1..This peripheral requires supervisor privilege level for accesses. + */ #define AIPS_PACRN_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP0_SHIFT)) & AIPS_PACRN_SP0_MASK) +/*! @} */ /*! @name PACRO - Peripheral Access Control Register */ +/*! @{ */ #define AIPS_PACRO_TP7_MASK (0x1U) #define AIPS_PACRO_TP7_SHIFT (0U) +/*! TP7 - Trusted Protect + * 0b0..Accesses from an untrusted master are allowed. + * 0b1..Accesses from an untrusted master are not allowed. + */ #define AIPS_PACRO_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP7_SHIFT)) & AIPS_PACRO_TP7_MASK) #define AIPS_PACRO_WP7_MASK (0x2U) #define AIPS_PACRO_WP7_SHIFT (1U) +/*! WP7 - Write Protect + * 0b0..This peripheral allows write accesses. + * 0b1..This peripheral is write protected. + */ #define AIPS_PACRO_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP7_SHIFT)) & AIPS_PACRO_WP7_MASK) #define AIPS_PACRO_SP7_MASK (0x4U) #define AIPS_PACRO_SP7_SHIFT (2U) +/*! SP7 - Supervisor Protect + * 0b0..This peripheral does not require supervisor privilege level for accesses. + * 0b1..This peripheral requires supervisor privilege level for accesses. + */ #define AIPS_PACRO_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP7_SHIFT)) & AIPS_PACRO_SP7_MASK) #define AIPS_PACRO_TP6_MASK (0x10U) #define AIPS_PACRO_TP6_SHIFT (4U) +/*! TP6 - Trusted Protect + * 0b0..Accesses from an untrusted master are allowed. + * 0b1..Accesses from an untrusted master are not allowed. + */ #define AIPS_PACRO_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP6_SHIFT)) & AIPS_PACRO_TP6_MASK) #define AIPS_PACRO_WP6_MASK (0x20U) #define AIPS_PACRO_WP6_SHIFT (5U) +/*! WP6 - Write Protect + * 0b0..This peripheral allows write accesses. + * 0b1..This peripheral is write protected. + */ #define AIPS_PACRO_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP6_SHIFT)) & AIPS_PACRO_WP6_MASK) #define AIPS_PACRO_SP6_MASK (0x40U) #define AIPS_PACRO_SP6_SHIFT (6U) +/*! SP6 - Supervisor Protect + * 0b0..This peripheral does not require supervisor privilege level for accesses. + * 0b1..This peripheral requires supervisor privilege level for accesses. + */ #define AIPS_PACRO_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP6_SHIFT)) & AIPS_PACRO_SP6_MASK) #define AIPS_PACRO_TP5_MASK (0x100U) #define AIPS_PACRO_TP5_SHIFT (8U) +/*! TP5 - Trusted Protect + * 0b0..Accesses from an untrusted master are allowed. + * 0b1..Accesses from an untrusted master are not allowed. + */ #define AIPS_PACRO_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP5_SHIFT)) & AIPS_PACRO_TP5_MASK) #define AIPS_PACRO_WP5_MASK (0x200U) #define AIPS_PACRO_WP5_SHIFT (9U) +/*! WP5 - Write Protect + * 0b0..This peripheral allows write accesses. + * 0b1..This peripheral is write protected. + */ #define AIPS_PACRO_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP5_SHIFT)) & AIPS_PACRO_WP5_MASK) #define AIPS_PACRO_SP5_MASK (0x400U) #define AIPS_PACRO_SP5_SHIFT (10U) +/*! SP5 - Supervisor Protect + * 0b0..This peripheral does not require supervisor privilege level for accesses. + * 0b1..This peripheral requires supervisor privilege level for accesses. + */ #define AIPS_PACRO_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP5_SHIFT)) & AIPS_PACRO_SP5_MASK) #define AIPS_PACRO_TP4_MASK (0x1000U) #define AIPS_PACRO_TP4_SHIFT (12U) +/*! TP4 - Trusted Protect + * 0b0..Accesses from an untrusted master are allowed. + * 0b1..Accesses from an untrusted master are not allowed. + */ #define AIPS_PACRO_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP4_SHIFT)) & AIPS_PACRO_TP4_MASK) #define AIPS_PACRO_WP4_MASK (0x2000U) #define AIPS_PACRO_WP4_SHIFT (13U) +/*! WP4 - Write Protect + * 0b0..This peripheral allows write accesses. + * 0b1..This peripheral is write protected. + */ #define AIPS_PACRO_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP4_SHIFT)) & AIPS_PACRO_WP4_MASK) #define AIPS_PACRO_SP4_MASK (0x4000U) #define AIPS_PACRO_SP4_SHIFT (14U) +/*! SP4 - Supervisor Protect + * 0b0..This peripheral does not require supervisor privilege level for accesses. + * 0b1..This peripheral requires supervisor privilege level for accesses. + */ #define AIPS_PACRO_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP4_SHIFT)) & AIPS_PACRO_SP4_MASK) #define AIPS_PACRO_TP3_MASK (0x10000U) #define AIPS_PACRO_TP3_SHIFT (16U) +/*! TP3 - Trusted Protect + * 0b0..Accesses from an untrusted master are allowed. + * 0b1..Accesses from an untrusted master are not allowed. + */ #define AIPS_PACRO_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP3_SHIFT)) & AIPS_PACRO_TP3_MASK) #define AIPS_PACRO_WP3_MASK (0x20000U) #define AIPS_PACRO_WP3_SHIFT (17U) +/*! WP3 - Write Protect + * 0b0..This peripheral allows write accesses. + * 0b1..This peripheral is write protected. + */ #define AIPS_PACRO_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP3_SHIFT)) & AIPS_PACRO_WP3_MASK) #define AIPS_PACRO_SP3_MASK (0x40000U) #define AIPS_PACRO_SP3_SHIFT (18U) +/*! SP3 - Supervisor Protect + * 0b0..This peripheral does not require supervisor privilege level for accesses. + * 0b1..This peripheral requires supervisor privilege level for accesses. + */ #define AIPS_PACRO_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP3_SHIFT)) & AIPS_PACRO_SP3_MASK) #define AIPS_PACRO_TP2_MASK (0x100000U) #define AIPS_PACRO_TP2_SHIFT (20U) +/*! TP2 - Trusted Protect + * 0b0..Accesses from an untrusted master are allowed. + * 0b1..Accesses from an untrusted master are not allowed. + */ #define AIPS_PACRO_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP2_SHIFT)) & AIPS_PACRO_TP2_MASK) #define AIPS_PACRO_WP2_MASK (0x200000U) #define AIPS_PACRO_WP2_SHIFT (21U) +/*! WP2 - Write Protect + * 0b0..This peripheral allows write accesses. + * 0b1..This peripheral is write protected. + */ #define AIPS_PACRO_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP2_SHIFT)) & AIPS_PACRO_WP2_MASK) #define AIPS_PACRO_SP2_MASK (0x400000U) #define AIPS_PACRO_SP2_SHIFT (22U) +/*! SP2 - Supervisor Protect + * 0b0..This peripheral does not require supervisor privilege level for accesses. + * 0b1..This peripheral requires supervisor privilege level for accesses. + */ #define AIPS_PACRO_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP2_SHIFT)) & AIPS_PACRO_SP2_MASK) #define AIPS_PACRO_TP1_MASK (0x1000000U) #define AIPS_PACRO_TP1_SHIFT (24U) +/*! TP1 - Trusted Protect + * 0b0..Accesses from an untrusted master are allowed. + * 0b1..Accesses from an untrusted master are not allowed. + */ #define AIPS_PACRO_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP1_SHIFT)) & AIPS_PACRO_TP1_MASK) #define AIPS_PACRO_WP1_MASK (0x2000000U) #define AIPS_PACRO_WP1_SHIFT (25U) +/*! WP1 - Write Protect + * 0b0..This peripheral allows write accesses. + * 0b1..This peripheral is write protected. + */ #define AIPS_PACRO_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP1_SHIFT)) & AIPS_PACRO_WP1_MASK) #define AIPS_PACRO_SP1_MASK (0x4000000U) #define AIPS_PACRO_SP1_SHIFT (26U) +/*! SP1 - Supervisor Protect + * 0b0..This peripheral does not require supervisor privilege level for accesses. + * 0b1..This peripheral requires supervisor privilege level for accesses. + */ #define AIPS_PACRO_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP1_SHIFT)) & AIPS_PACRO_SP1_MASK) #define AIPS_PACRO_TP0_MASK (0x10000000U) #define AIPS_PACRO_TP0_SHIFT (28U) +/*! TP0 - Trusted Protect + * 0b0..Accesses from an untrusted master are allowed. + * 0b1..Accesses from an untrusted master are not allowed. + */ #define AIPS_PACRO_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP0_SHIFT)) & AIPS_PACRO_TP0_MASK) #define AIPS_PACRO_WP0_MASK (0x20000000U) #define AIPS_PACRO_WP0_SHIFT (29U) +/*! WP0 - Write Protect + * 0b0..This peripheral allows write accesses. + * 0b1..This peripheral is write protected. + */ #define AIPS_PACRO_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP0_SHIFT)) & AIPS_PACRO_WP0_MASK) #define AIPS_PACRO_SP0_MASK (0x40000000U) #define AIPS_PACRO_SP0_SHIFT (30U) +/*! SP0 - Supervisor Protect + * 0b0..This peripheral does not require supervisor privilege level for accesses. + * 0b1..This peripheral requires supervisor privilege level for accesses. + */ #define AIPS_PACRO_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP0_SHIFT)) & AIPS_PACRO_SP0_MASK) +/*! @} */ /*! @name PACRP - Peripheral Access Control Register */ +/*! @{ */ #define AIPS_PACRP_TP7_MASK (0x1U) #define AIPS_PACRP_TP7_SHIFT (0U) +/*! TP7 - Trusted Protect + * 0b0..Accesses from an untrusted master are allowed. + * 0b1..Accesses from an untrusted master are not allowed. + */ #define AIPS_PACRP_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP7_SHIFT)) & AIPS_PACRP_TP7_MASK) #define AIPS_PACRP_WP7_MASK (0x2U) #define AIPS_PACRP_WP7_SHIFT (1U) +/*! WP7 - Write Protect + * 0b0..This peripheral allows write accesses. + * 0b1..This peripheral is write protected. + */ #define AIPS_PACRP_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP7_SHIFT)) & AIPS_PACRP_WP7_MASK) #define AIPS_PACRP_SP7_MASK (0x4U) #define AIPS_PACRP_SP7_SHIFT (2U) +/*! SP7 - Supervisor Protect + * 0b0..This peripheral does not require supervisor privilege level for accesses. + * 0b1..This peripheral requires supervisor privilege level for accesses. + */ #define AIPS_PACRP_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP7_SHIFT)) & AIPS_PACRP_SP7_MASK) #define AIPS_PACRP_TP6_MASK (0x10U) #define AIPS_PACRP_TP6_SHIFT (4U) +/*! TP6 - Trusted Protect + * 0b0..Accesses from an untrusted master are allowed. + * 0b1..Accesses from an untrusted master are not allowed. + */ #define AIPS_PACRP_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP6_SHIFT)) & AIPS_PACRP_TP6_MASK) #define AIPS_PACRP_WP6_MASK (0x20U) #define AIPS_PACRP_WP6_SHIFT (5U) +/*! WP6 - Write Protect + * 0b0..This peripheral allows write accesses. + * 0b1..This peripheral is write protected. + */ #define AIPS_PACRP_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP6_SHIFT)) & AIPS_PACRP_WP6_MASK) #define AIPS_PACRP_SP6_MASK (0x40U) #define AIPS_PACRP_SP6_SHIFT (6U) +/*! SP6 - Supervisor Protect + * 0b0..This peripheral does not require supervisor privilege level for accesses. + * 0b1..This peripheral requires supervisor privilege level for accesses. + */ #define AIPS_PACRP_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP6_SHIFT)) & AIPS_PACRP_SP6_MASK) #define AIPS_PACRP_TP5_MASK (0x100U) #define AIPS_PACRP_TP5_SHIFT (8U) +/*! TP5 - Trusted Protect + * 0b0..Accesses from an untrusted master are allowed. + * 0b1..Accesses from an untrusted master are not allowed. + */ #define AIPS_PACRP_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP5_SHIFT)) & AIPS_PACRP_TP5_MASK) #define AIPS_PACRP_WP5_MASK (0x200U) #define AIPS_PACRP_WP5_SHIFT (9U) +/*! WP5 - Write Protect + * 0b0..This peripheral allows write accesses. + * 0b1..This peripheral is write protected. + */ #define AIPS_PACRP_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP5_SHIFT)) & AIPS_PACRP_WP5_MASK) #define AIPS_PACRP_SP5_MASK (0x400U) #define AIPS_PACRP_SP5_SHIFT (10U) +/*! SP5 - Supervisor Protect + * 0b0..This peripheral does not require supervisor privilege level for accesses. + * 0b1..This peripheral requires supervisor privilege level for accesses. + */ #define AIPS_PACRP_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP5_SHIFT)) & AIPS_PACRP_SP5_MASK) #define AIPS_PACRP_TP4_MASK (0x1000U) #define AIPS_PACRP_TP4_SHIFT (12U) +/*! TP4 - Trusted Protect + * 0b0..Accesses from an untrusted master are allowed. + * 0b1..Accesses from an untrusted master are not allowed. + */ #define AIPS_PACRP_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP4_SHIFT)) & AIPS_PACRP_TP4_MASK) #define AIPS_PACRP_WP4_MASK (0x2000U) #define AIPS_PACRP_WP4_SHIFT (13U) +/*! WP4 - Write Protect + * 0b0..This peripheral allows write accesses. + * 0b1..This peripheral is write protected. + */ #define AIPS_PACRP_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP4_SHIFT)) & AIPS_PACRP_WP4_MASK) #define AIPS_PACRP_SP4_MASK (0x4000U) #define AIPS_PACRP_SP4_SHIFT (14U) +/*! SP4 - Supervisor Protect + * 0b0..This peripheral does not require supervisor privilege level for accesses. + * 0b1..This peripheral requires supervisor privilege level for accesses. + */ #define AIPS_PACRP_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP4_SHIFT)) & AIPS_PACRP_SP4_MASK) #define AIPS_PACRP_TP3_MASK (0x10000U) #define AIPS_PACRP_TP3_SHIFT (16U) +/*! TP3 - Trusted Protect + * 0b0..Accesses from an untrusted master are allowed. + * 0b1..Accesses from an untrusted master are not allowed. + */ #define AIPS_PACRP_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP3_SHIFT)) & AIPS_PACRP_TP3_MASK) #define AIPS_PACRP_WP3_MASK (0x20000U) #define AIPS_PACRP_WP3_SHIFT (17U) +/*! WP3 - Write Protect + * 0b0..This peripheral allows write accesses. + * 0b1..This peripheral is write protected. + */ #define AIPS_PACRP_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP3_SHIFT)) & AIPS_PACRP_WP3_MASK) #define AIPS_PACRP_SP3_MASK (0x40000U) #define AIPS_PACRP_SP3_SHIFT (18U) +/*! SP3 - Supervisor Protect + * 0b0..This peripheral does not require supervisor privilege level for accesses. + * 0b1..This peripheral requires supervisor privilege level for accesses. + */ #define AIPS_PACRP_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP3_SHIFT)) & AIPS_PACRP_SP3_MASK) #define AIPS_PACRP_TP2_MASK (0x100000U) #define AIPS_PACRP_TP2_SHIFT (20U) +/*! TP2 - Trusted Protect + * 0b0..Accesses from an untrusted master are allowed. + * 0b1..Accesses from an untrusted master are not allowed. + */ #define AIPS_PACRP_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP2_SHIFT)) & AIPS_PACRP_TP2_MASK) #define AIPS_PACRP_WP2_MASK (0x200000U) #define AIPS_PACRP_WP2_SHIFT (21U) +/*! WP2 - Write Protect + * 0b0..This peripheral allows write accesses. + * 0b1..This peripheral is write protected. + */ #define AIPS_PACRP_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP2_SHIFT)) & AIPS_PACRP_WP2_MASK) #define AIPS_PACRP_SP2_MASK (0x400000U) #define AIPS_PACRP_SP2_SHIFT (22U) +/*! SP2 - Supervisor Protect + * 0b0..This peripheral does not require supervisor privilege level for accesses. + * 0b1..This peripheral requires supervisor privilege level for accesses. + */ #define AIPS_PACRP_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP2_SHIFT)) & AIPS_PACRP_SP2_MASK) #define AIPS_PACRP_TP1_MASK (0x1000000U) #define AIPS_PACRP_TP1_SHIFT (24U) +/*! TP1 - Trusted Protect + * 0b0..Accesses from an untrusted master are allowed. + * 0b1..Accesses from an untrusted master are not allowed. + */ #define AIPS_PACRP_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP1_SHIFT)) & AIPS_PACRP_TP1_MASK) #define AIPS_PACRP_WP1_MASK (0x2000000U) #define AIPS_PACRP_WP1_SHIFT (25U) +/*! WP1 - Write Protect + * 0b0..This peripheral allows write accesses. + * 0b1..This peripheral is write protected. + */ #define AIPS_PACRP_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP1_SHIFT)) & AIPS_PACRP_WP1_MASK) #define AIPS_PACRP_SP1_MASK (0x4000000U) #define AIPS_PACRP_SP1_SHIFT (26U) +/*! SP1 - Supervisor Protect + * 0b0..This peripheral does not require supervisor privilege level for accesses. + * 0b1..This peripheral requires supervisor privilege level for accesses. + */ #define AIPS_PACRP_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP1_SHIFT)) & AIPS_PACRP_SP1_MASK) #define AIPS_PACRP_TP0_MASK (0x10000000U) #define AIPS_PACRP_TP0_SHIFT (28U) +/*! TP0 - Trusted Protect + * 0b0..Accesses from an untrusted master are allowed. + * 0b1..Accesses from an untrusted master are not allowed. + */ #define AIPS_PACRP_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP0_SHIFT)) & AIPS_PACRP_TP0_MASK) #define AIPS_PACRP_WP0_MASK (0x20000000U) #define AIPS_PACRP_WP0_SHIFT (29U) +/*! WP0 - Write Protect + * 0b0..This peripheral allows write accesses. + * 0b1..This peripheral is write protected. + */ #define AIPS_PACRP_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP0_SHIFT)) & AIPS_PACRP_WP0_MASK) #define AIPS_PACRP_SP0_MASK (0x40000000U) #define AIPS_PACRP_SP0_SHIFT (30U) +/*! SP0 - Supervisor Protect + * 0b0..This peripheral does not require supervisor privilege level for accesses. + * 0b1..This peripheral requires supervisor privilege level for accesses. + */ #define AIPS_PACRP_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP0_SHIFT)) & AIPS_PACRP_SP0_MASK) +/*! @} */ /*! @name PACRU - Peripheral Access Control Register */ +/*! @{ */ #define AIPS_PACRU_TP1_MASK (0x1000000U) #define AIPS_PACRU_TP1_SHIFT (24U) +/*! TP1 - Trusted Protect + * 0b0..Accesses from an untrusted master are allowed. + * 0b1..Accesses from an untrusted master are not allowed. + */ #define AIPS_PACRU_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRU_TP1_SHIFT)) & AIPS_PACRU_TP1_MASK) #define AIPS_PACRU_WP1_MASK (0x2000000U) #define AIPS_PACRU_WP1_SHIFT (25U) +/*! WP1 - Write Protect + * 0b0..This peripheral allows write accesses. + * 0b1..This peripheral is write protected. + */ #define AIPS_PACRU_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRU_WP1_SHIFT)) & AIPS_PACRU_WP1_MASK) #define AIPS_PACRU_SP1_MASK (0x4000000U) #define AIPS_PACRU_SP1_SHIFT (26U) +/*! SP1 - Supervisor Protect + * 0b0..This peripheral does not require supervisor privilege level for accesses. + * 0b1..This peripheral requires supervisor privilege level for accesses. + */ #define AIPS_PACRU_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRU_SP1_SHIFT)) & AIPS_PACRU_SP1_MASK) #define AIPS_PACRU_TP0_MASK (0x10000000U) #define AIPS_PACRU_TP0_SHIFT (28U) +/*! TP0 - Trusted Protect + * 0b0..Accesses from an untrusted master are allowed. + * 0b1..Accesses from an untrusted master are not allowed. + */ #define AIPS_PACRU_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRU_TP0_SHIFT)) & AIPS_PACRU_TP0_MASK) #define AIPS_PACRU_WP0_MASK (0x20000000U) #define AIPS_PACRU_WP0_SHIFT (29U) +/*! WP0 - Write Protect + * 0b0..This peripheral allows write accesses. + * 0b1..This peripheral is write protected. + */ #define AIPS_PACRU_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRU_WP0_SHIFT)) & AIPS_PACRU_WP0_MASK) #define AIPS_PACRU_SP0_MASK (0x40000000U) #define AIPS_PACRU_SP0_SHIFT (30U) +/*! SP0 - Supervisor Protect + * 0b0..This peripheral does not require supervisor privilege level for accesses. + * 0b1..This peripheral requires supervisor privilege level for accesses. + */ #define AIPS_PACRU_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRU_SP0_SHIFT)) & AIPS_PACRU_SP0_MASK) +/*! @} */ /*! @@ -2058,77 +3896,243 @@ typedef struct { */ /*! @name PRS - Priority Registers Slave */ +/*! @{ */ #define AXBS_PRS_M0_MASK (0x7U) #define AXBS_PRS_M0_SHIFT (0U) +/*! M0 - Master 0 Priority. Sets the arbitration priority for this port on the associated slave port. + * 0b000..This master has level 1, or highest, priority when accessing the slave port. + * 0b001..This master has level 2 priority when accessing the slave port. + * 0b010..This master has level 3 priority when accessing the slave port. + * 0b011..This master has level 4 priority when accessing the slave port. + * 0b100..This master has level 5 priority when accessing the slave port. + * 0b101..This master has level 6 priority when accessing the slave port. + * 0b110..This master has level 7 priority when accessing the slave port. + * 0b111..This master has level 8, or lowest, priority when accessing the slave port. + */ #define AXBS_PRS_M0(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M0_SHIFT)) & AXBS_PRS_M0_MASK) #define AXBS_PRS_M1_MASK (0x70U) #define AXBS_PRS_M1_SHIFT (4U) +/*! M1 - Master 1 Priority. Sets the arbitration priority for this port on the associated slave port. + * 0b000..This master has level 1, or highest, priority when accessing the slave port. + * 0b001..This master has level 2 priority when accessing the slave port. + * 0b010..This master has level 3 priority when accessing the slave port. + * 0b011..This master has level 4 priority when accessing the slave port. + * 0b100..This master has level 5 priority when accessing the slave port. + * 0b101..This master has level 6 priority when accessing the slave port. + * 0b110..This master has level 7 priority when accessing the slave port. + * 0b111..This master has level 8, or lowest, priority when accessing the slave port. + */ #define AXBS_PRS_M1(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M1_SHIFT)) & AXBS_PRS_M1_MASK) #define AXBS_PRS_M2_MASK (0x700U) #define AXBS_PRS_M2_SHIFT (8U) +/*! M2 - Master 2 Priority. Sets the arbitration priority for this port on the associated slave port. + * 0b000..This master has level 1, or highest, priority when accessing the slave port. + * 0b001..This master has level 2 priority when accessing the slave port. + * 0b010..This master has level 3 priority when accessing the slave port. + * 0b011..This master has level 4 priority when accessing the slave port. + * 0b100..This master has level 5 priority when accessing the slave port. + * 0b101..This master has level 6 priority when accessing the slave port. + * 0b110..This master has level 7 priority when accessing the slave port. + * 0b111..This master has level 8, or lowest, priority when accessing the slave port. + */ #define AXBS_PRS_M2(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M2_SHIFT)) & AXBS_PRS_M2_MASK) #define AXBS_PRS_M3_MASK (0x7000U) #define AXBS_PRS_M3_SHIFT (12U) +/*! M3 - Master 3 Priority. Sets the arbitration priority for this port on the associated slave port. + * 0b000..This master has level 1, or highest, priority when accessing the slave port. + * 0b001..This master has level 2 priority when accessing the slave port. + * 0b010..This master has level 3 priority when accessing the slave port. + * 0b011..This master has level 4 priority when accessing the slave port. + * 0b100..This master has level 5 priority when accessing the slave port. + * 0b101..This master has level 6 priority when accessing the slave port. + * 0b110..This master has level 7 priority when accessing the slave port. + * 0b111..This master has level 8, or lowest, priority when accessing the slave port. + */ #define AXBS_PRS_M3(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M3_SHIFT)) & AXBS_PRS_M3_MASK) #define AXBS_PRS_M4_MASK (0x70000U) #define AXBS_PRS_M4_SHIFT (16U) +/*! M4 - Master 4 Priority. Sets the arbitration priority for this port on the associated slave port. + * 0b000..This master has level 1, or highest, priority when accessing the slave port. + * 0b001..This master has level 2 priority when accessing the slave port. + * 0b010..This master has level 3 priority when accessing the slave port. + * 0b011..This master has level 4 priority when accessing the slave port. + * 0b100..This master has level 5 priority when accessing the slave port. + * 0b101..This master has level 6 priority when accessing the slave port. + * 0b110..This master has level 7 priority when accessing the slave port. + * 0b111..This master has level 8, or lowest, priority when accessing the slave port. + */ #define AXBS_PRS_M4(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M4_SHIFT)) & AXBS_PRS_M4_MASK) #define AXBS_PRS_M5_MASK (0x700000U) #define AXBS_PRS_M5_SHIFT (20U) +/*! M5 - Master 5 Priority. Sets the arbitration priority for this port on the associated slave port. + * 0b000..This master has level 1, or highest, priority when accessing the slave port. + * 0b001..This master has level 2 priority when accessing the slave port. + * 0b010..This master has level 3 priority when accessing the slave port. + * 0b011..This master has level 4 priority when accessing the slave port. + * 0b100..This master has level 5 priority when accessing the slave port. + * 0b101..This master has level 6 priority when accessing the slave port. + * 0b110..This master has level 7 priority when accessing the slave port. + * 0b111..This master has level 8, or lowest, priority when accessing the slave port. + */ #define AXBS_PRS_M5(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M5_SHIFT)) & AXBS_PRS_M5_MASK) +/*! @} */ /* The count of AXBS_PRS */ #define AXBS_PRS_COUNT (5U) /*! @name CRS - Control Register */ +/*! @{ */ #define AXBS_CRS_PARK_MASK (0x7U) #define AXBS_CRS_PARK_SHIFT (0U) +/*! PARK - Park + * 0b000..Park on master port M0 + * 0b001..Park on master port M1 + * 0b010..Park on master port M2 + * 0b011..Park on master port M3 + * 0b100..Park on master port M4 + * 0b101..Park on master port M5 + * 0b110..Park on master port M6 + * 0b111..Park on master port M7 + */ #define AXBS_CRS_PARK(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_PARK_SHIFT)) & AXBS_CRS_PARK_MASK) #define AXBS_CRS_PCTL_MASK (0x30U) #define AXBS_CRS_PCTL_SHIFT (4U) +/*! PCTL - Parking Control + * 0b00..When no master makes a request, the arbiter parks the slave port on the master port defined by the PARK field + * 0b01..When no master makes a request, the arbiter parks the slave port on the last master to be in control of the slave port + * 0b10..When no master makes a request, the slave port is not parked on a master and the arbiter drives all outputs to a constant safe state + * 0b11..Reserved + */ #define AXBS_CRS_PCTL(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_PCTL_SHIFT)) & AXBS_CRS_PCTL_MASK) #define AXBS_CRS_ARB_MASK (0x300U) #define AXBS_CRS_ARB_SHIFT (8U) +/*! ARB - Arbitration Mode + * 0b00..Fixed priority + * 0b01..Round-robin, or rotating, priority + * 0b10..Reserved + * 0b11..Reserved + */ #define AXBS_CRS_ARB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_ARB_SHIFT)) & AXBS_CRS_ARB_MASK) #define AXBS_CRS_HLP_MASK (0x40000000U) #define AXBS_CRS_HLP_SHIFT (30U) +/*! HLP - Halt Low Priority + * 0b0..The low power mode request has the highest priority for arbitration on this slave port + * 0b1..The low power mode request has the lowest initial priority for arbitration on this slave port + */ #define AXBS_CRS_HLP(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_HLP_SHIFT)) & AXBS_CRS_HLP_MASK) #define AXBS_CRS_RO_MASK (0x80000000U) #define AXBS_CRS_RO_SHIFT (31U) +/*! RO - Read Only + * 0b0..The slave port's registers are writeable + * 0b1..The slave port's registers are read-only and cannot be written. Attempted writes have no effect on the registers and result in a bus error response. + */ #define AXBS_CRS_RO(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_RO_SHIFT)) & AXBS_CRS_RO_MASK) +/*! @} */ /* The count of AXBS_CRS */ #define AXBS_CRS_COUNT (5U) /*! @name MGPCR0 - Master General Purpose Control Register */ +/*! @{ */ #define AXBS_MGPCR0_AULB_MASK (0x7U) #define AXBS_MGPCR0_AULB_SHIFT (0U) +/*! AULB - Arbitrates On Undefined Length Bursts + * 0b000..No arbitration is allowed during an undefined length burst + * 0b001..Arbitration is allowed at any time during an undefined length burst + * 0b010..Arbitration is allowed after four beats of an undefined length burst + * 0b011..Arbitration is allowed after eight beats of an undefined length burst + * 0b100..Arbitration is allowed after 16 beats of an undefined length burst + * 0b101..Reserved + * 0b110..Reserved + * 0b111..Reserved + */ #define AXBS_MGPCR0_AULB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR0_AULB_SHIFT)) & AXBS_MGPCR0_AULB_MASK) +/*! @} */ /*! @name MGPCR1 - Master General Purpose Control Register */ +/*! @{ */ #define AXBS_MGPCR1_AULB_MASK (0x7U) #define AXBS_MGPCR1_AULB_SHIFT (0U) +/*! AULB - Arbitrates On Undefined Length Bursts + * 0b000..No arbitration is allowed during an undefined length burst + * 0b001..Arbitration is allowed at any time during an undefined length burst + * 0b010..Arbitration is allowed after four beats of an undefined length burst + * 0b011..Arbitration is allowed after eight beats of an undefined length burst + * 0b100..Arbitration is allowed after 16 beats of an undefined length burst + * 0b101..Reserved + * 0b110..Reserved + * 0b111..Reserved + */ #define AXBS_MGPCR1_AULB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR1_AULB_SHIFT)) & AXBS_MGPCR1_AULB_MASK) +/*! @} */ /*! @name MGPCR2 - Master General Purpose Control Register */ +/*! @{ */ #define AXBS_MGPCR2_AULB_MASK (0x7U) #define AXBS_MGPCR2_AULB_SHIFT (0U) +/*! AULB - Arbitrates On Undefined Length Bursts + * 0b000..No arbitration is allowed during an undefined length burst + * 0b001..Arbitration is allowed at any time during an undefined length burst + * 0b010..Arbitration is allowed after four beats of an undefined length burst + * 0b011..Arbitration is allowed after eight beats of an undefined length burst + * 0b100..Arbitration is allowed after 16 beats of an undefined length burst + * 0b101..Reserved + * 0b110..Reserved + * 0b111..Reserved + */ #define AXBS_MGPCR2_AULB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR2_AULB_SHIFT)) & AXBS_MGPCR2_AULB_MASK) +/*! @} */ /*! @name MGPCR3 - Master General Purpose Control Register */ +/*! @{ */ #define AXBS_MGPCR3_AULB_MASK (0x7U) #define AXBS_MGPCR3_AULB_SHIFT (0U) +/*! AULB - Arbitrates On Undefined Length Bursts + * 0b000..No arbitration is allowed during an undefined length burst + * 0b001..Arbitration is allowed at any time during an undefined length burst + * 0b010..Arbitration is allowed after four beats of an undefined length burst + * 0b011..Arbitration is allowed after eight beats of an undefined length burst + * 0b100..Arbitration is allowed after 16 beats of an undefined length burst + * 0b101..Reserved + * 0b110..Reserved + * 0b111..Reserved + */ #define AXBS_MGPCR3_AULB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR3_AULB_SHIFT)) & AXBS_MGPCR3_AULB_MASK) +/*! @} */ /*! @name MGPCR4 - Master General Purpose Control Register */ +/*! @{ */ #define AXBS_MGPCR4_AULB_MASK (0x7U) #define AXBS_MGPCR4_AULB_SHIFT (0U) +/*! AULB - Arbitrates On Undefined Length Bursts + * 0b000..No arbitration is allowed during an undefined length burst + * 0b001..Arbitration is allowed at any time during an undefined length burst + * 0b010..Arbitration is allowed after four beats of an undefined length burst + * 0b011..Arbitration is allowed after eight beats of an undefined length burst + * 0b100..Arbitration is allowed after 16 beats of an undefined length burst + * 0b101..Reserved + * 0b110..Reserved + * 0b111..Reserved + */ #define AXBS_MGPCR4_AULB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR4_AULB_SHIFT)) & AXBS_MGPCR4_AULB_MASK) +/*! @} */ /*! @name MGPCR5 - Master General Purpose Control Register */ +/*! @{ */ #define AXBS_MGPCR5_AULB_MASK (0x7U) #define AXBS_MGPCR5_AULB_SHIFT (0U) +/*! AULB - Arbitrates On Undefined Length Bursts + * 0b000..No arbitration is allowed during an undefined length burst + * 0b001..Arbitration is allowed at any time during an undefined length burst + * 0b010..Arbitration is allowed after four beats of an undefined length burst + * 0b011..Arbitration is allowed after eight beats of an undefined length burst + * 0b100..Arbitration is allowed after 16 beats of an undefined length burst + * 0b101..Reserved + * 0b110..Reserved + * 0b111..Reserved + */ #define AXBS_MGPCR5_AULB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR5_AULB_SHIFT)) & AXBS_MGPCR5_AULB_MASK) +/*! @} */ /*! @@ -2202,100 +4206,221 @@ typedef struct { */ /*! @name MCR - Module Configuration Register */ +/*! @{ */ #define CAN_MCR_MAXMB_MASK (0x7FU) #define CAN_MCR_MAXMB_SHIFT (0U) #define CAN_MCR_MAXMB(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_MAXMB_SHIFT)) & CAN_MCR_MAXMB_MASK) #define CAN_MCR_IDAM_MASK (0x300U) #define CAN_MCR_IDAM_SHIFT (8U) +/*! IDAM - ID Acceptance Mode + * 0b00..Format A: One full ID (standard and extended) per ID Filter Table element. + * 0b01..Format B: Two full standard IDs or two partial 14-bit (standard and extended) IDs per ID Filter Table element. + * 0b10..Format C: Four partial 8-bit Standard IDs per ID Filter Table element. + * 0b11..Format D: All frames rejected. + */ #define CAN_MCR_IDAM(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_IDAM_SHIFT)) & CAN_MCR_IDAM_MASK) #define CAN_MCR_AEN_MASK (0x1000U) #define CAN_MCR_AEN_SHIFT (12U) +/*! AEN - Abort Enable + * 0b0..Abort disabled. + * 0b1..Abort enabled. + */ #define CAN_MCR_AEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_AEN_SHIFT)) & CAN_MCR_AEN_MASK) #define CAN_MCR_LPRIOEN_MASK (0x2000U) #define CAN_MCR_LPRIOEN_SHIFT (13U) +/*! LPRIOEN - Local Priority Enable + * 0b0..Local Priority disabled. + * 0b1..Local Priority enabled. + */ #define CAN_MCR_LPRIOEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_LPRIOEN_SHIFT)) & CAN_MCR_LPRIOEN_MASK) #define CAN_MCR_IRMQ_MASK (0x10000U) #define CAN_MCR_IRMQ_SHIFT (16U) +/*! IRMQ - Individual Rx Masking And Queue Enable + * 0b0..Individual Rx masking and queue feature are disabled. For backward compatibility with legacy applications, the reading of C/S word locks the MB even if it is EMPTY. + * 0b1..Individual Rx masking and queue feature are enabled. + */ #define CAN_MCR_IRMQ(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_IRMQ_SHIFT)) & CAN_MCR_IRMQ_MASK) #define CAN_MCR_SRXDIS_MASK (0x20000U) #define CAN_MCR_SRXDIS_SHIFT (17U) +/*! SRXDIS - Self Reception Disable + * 0b0..Self reception enabled. + * 0b1..Self reception disabled. + */ #define CAN_MCR_SRXDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SRXDIS_SHIFT)) & CAN_MCR_SRXDIS_MASK) #define CAN_MCR_WAKSRC_MASK (0x80000U) #define CAN_MCR_WAKSRC_SHIFT (19U) +/*! WAKSRC - Wake Up Source + * 0b0..FlexCAN uses the unfiltered Rx input to detect recessive to dominant edges on the CAN bus. + * 0b1..FlexCAN uses the filtered Rx input to detect recessive to dominant edges on the CAN bus. + */ #define CAN_MCR_WAKSRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WAKSRC_SHIFT)) & CAN_MCR_WAKSRC_MASK) #define CAN_MCR_LPMACK_MASK (0x100000U) #define CAN_MCR_LPMACK_SHIFT (20U) +/*! LPMACK - Low-Power Mode Acknowledge + * 0b0..FlexCAN is not in a low-power mode. + * 0b1..FlexCAN is in a low-power mode. + */ #define CAN_MCR_LPMACK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_LPMACK_SHIFT)) & CAN_MCR_LPMACK_MASK) #define CAN_MCR_WRNEN_MASK (0x200000U) #define CAN_MCR_WRNEN_SHIFT (21U) +/*! WRNEN - Warning Interrupt Enable + * 0b0..TWRNINT and RWRNINT bits are zero, independent of the values in the error counters. + * 0b1..TWRNINT and RWRNINT bits are set when the respective error counter transitions from less than 96 to greater than or equal to 96. + */ #define CAN_MCR_WRNEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WRNEN_SHIFT)) & CAN_MCR_WRNEN_MASK) #define CAN_MCR_SLFWAK_MASK (0x400000U) #define CAN_MCR_SLFWAK_SHIFT (22U) +/*! SLFWAK - Self Wake Up + * 0b0..FlexCAN Self Wake Up feature is disabled. + * 0b1..FlexCAN Self Wake Up feature is enabled. + */ #define CAN_MCR_SLFWAK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SLFWAK_SHIFT)) & CAN_MCR_SLFWAK_MASK) #define CAN_MCR_SUPV_MASK (0x800000U) #define CAN_MCR_SUPV_SHIFT (23U) +/*! SUPV - Supervisor Mode + * 0b0..FlexCAN is in User mode. Affected registers allow both Supervisor and Unrestricted accesses . + * 0b1..FlexCAN is in Supervisor mode. Affected registers allow only Supervisor access. Unrestricted access behaves as though the access was done to an unimplemented register location . + */ #define CAN_MCR_SUPV(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SUPV_SHIFT)) & CAN_MCR_SUPV_MASK) #define CAN_MCR_FRZACK_MASK (0x1000000U) #define CAN_MCR_FRZACK_SHIFT (24U) +/*! FRZACK - Freeze Mode Acknowledge + * 0b0..FlexCAN not in Freeze mode, prescaler running. + * 0b1..FlexCAN in Freeze mode, prescaler stopped. + */ #define CAN_MCR_FRZACK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FRZACK_SHIFT)) & CAN_MCR_FRZACK_MASK) #define CAN_MCR_SOFTRST_MASK (0x2000000U) #define CAN_MCR_SOFTRST_SHIFT (25U) +/*! SOFTRST - Soft Reset + * 0b0..No reset request. + * 0b1..Resets the registers affected by soft reset. + */ #define CAN_MCR_SOFTRST(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SOFTRST_SHIFT)) & CAN_MCR_SOFTRST_MASK) #define CAN_MCR_WAKMSK_MASK (0x4000000U) #define CAN_MCR_WAKMSK_SHIFT (26U) +/*! WAKMSK - Wake Up Interrupt Mask + * 0b0..Wake Up Interrupt is disabled. + * 0b1..Wake Up Interrupt is enabled. + */ #define CAN_MCR_WAKMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WAKMSK_SHIFT)) & CAN_MCR_WAKMSK_MASK) #define CAN_MCR_NOTRDY_MASK (0x8000000U) #define CAN_MCR_NOTRDY_SHIFT (27U) +/*! NOTRDY - FlexCAN Not Ready + * 0b0..FlexCAN module is either in Normal mode, Listen-Only mode or Loop-Back mode. + * 0b1..FlexCAN module is either in Disable mode , Stop mode or Freeze mode. + */ #define CAN_MCR_NOTRDY(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_NOTRDY_SHIFT)) & CAN_MCR_NOTRDY_MASK) #define CAN_MCR_HALT_MASK (0x10000000U) #define CAN_MCR_HALT_SHIFT (28U) +/*! HALT - Halt FlexCAN + * 0b0..No Freeze mode request. + * 0b1..Enters Freeze mode if the FRZ bit is asserted. + */ #define CAN_MCR_HALT(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_HALT_SHIFT)) & CAN_MCR_HALT_MASK) #define CAN_MCR_RFEN_MASK (0x20000000U) #define CAN_MCR_RFEN_SHIFT (29U) +/*! RFEN - Rx FIFO Enable + * 0b0..Rx FIFO not enabled. + * 0b1..Rx FIFO enabled. + */ #define CAN_MCR_RFEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_RFEN_SHIFT)) & CAN_MCR_RFEN_MASK) #define CAN_MCR_FRZ_MASK (0x40000000U) #define CAN_MCR_FRZ_SHIFT (30U) +/*! FRZ - Freeze Enable + * 0b0..Not enabled to enter Freeze mode. + * 0b1..Enabled to enter Freeze mode. + */ #define CAN_MCR_FRZ(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FRZ_SHIFT)) & CAN_MCR_FRZ_MASK) #define CAN_MCR_MDIS_MASK (0x80000000U) #define CAN_MCR_MDIS_SHIFT (31U) +/*! MDIS - Module Disable + * 0b0..Enable the FlexCAN module. + * 0b1..Disable the FlexCAN module. + */ #define CAN_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_MDIS_SHIFT)) & CAN_MCR_MDIS_MASK) +/*! @} */ /*! @name CTRL1 - Control 1 register */ +/*! @{ */ #define CAN_CTRL1_PROPSEG_MASK (0x7U) #define CAN_CTRL1_PROPSEG_SHIFT (0U) #define CAN_CTRL1_PROPSEG(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PROPSEG_SHIFT)) & CAN_CTRL1_PROPSEG_MASK) #define CAN_CTRL1_LOM_MASK (0x8U) #define CAN_CTRL1_LOM_SHIFT (3U) +/*! LOM - Listen-Only Mode + * 0b0..Listen-Only mode is deactivated. + * 0b1..FlexCAN module operates in Listen-Only mode. + */ #define CAN_CTRL1_LOM(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LOM_SHIFT)) & CAN_CTRL1_LOM_MASK) #define CAN_CTRL1_LBUF_MASK (0x10U) #define CAN_CTRL1_LBUF_SHIFT (4U) +/*! LBUF - Lowest Buffer Transmitted First + * 0b0..Buffer with highest priority is transmitted first. + * 0b1..Lowest number buffer is transmitted first. + */ #define CAN_CTRL1_LBUF(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LBUF_SHIFT)) & CAN_CTRL1_LBUF_MASK) #define CAN_CTRL1_TSYN_MASK (0x20U) #define CAN_CTRL1_TSYN_SHIFT (5U) +/*! TSYN - Timer Sync + * 0b0..Timer Sync feature disabled + * 0b1..Timer Sync feature enabled + */ #define CAN_CTRL1_TSYN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_TSYN_SHIFT)) & CAN_CTRL1_TSYN_MASK) #define CAN_CTRL1_BOFFREC_MASK (0x40U) #define CAN_CTRL1_BOFFREC_SHIFT (6U) +/*! BOFFREC - Bus Off Recovery + * 0b0..Automatic recovering from Bus Off state enabled, according to CAN Spec 2.0 part B. + * 0b1..Automatic recovering from Bus Off state disabled. + */ #define CAN_CTRL1_BOFFREC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_BOFFREC_SHIFT)) & CAN_CTRL1_BOFFREC_MASK) #define CAN_CTRL1_SMP_MASK (0x80U) #define CAN_CTRL1_SMP_SHIFT (7U) +/*! SMP - CAN Bit Sampling + * 0b0..Just one sample is used to determine the bit value. + * 0b1..Three samples are used to determine the value of the received bit: the regular one (sample point) and 2 preceding samples; a majority rule is used. + */ #define CAN_CTRL1_SMP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_SMP_SHIFT)) & CAN_CTRL1_SMP_MASK) #define CAN_CTRL1_RWRNMSK_MASK (0x400U) #define CAN_CTRL1_RWRNMSK_SHIFT (10U) +/*! RWRNMSK - Rx Warning Interrupt Mask + * 0b0..Rx Warning Interrupt disabled. + * 0b1..Rx Warning Interrupt enabled. + */ #define CAN_CTRL1_RWRNMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_RWRNMSK_SHIFT)) & CAN_CTRL1_RWRNMSK_MASK) #define CAN_CTRL1_TWRNMSK_MASK (0x800U) #define CAN_CTRL1_TWRNMSK_SHIFT (11U) +/*! TWRNMSK - Tx Warning Interrupt Mask + * 0b0..Tx Warning Interrupt disabled. + * 0b1..Tx Warning Interrupt enabled. + */ #define CAN_CTRL1_TWRNMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_TWRNMSK_SHIFT)) & CAN_CTRL1_TWRNMSK_MASK) #define CAN_CTRL1_LPB_MASK (0x1000U) #define CAN_CTRL1_LPB_SHIFT (12U) +/*! LPB - Loop Back Mode + * 0b0..Loop Back disabled. + * 0b1..Loop Back enabled. + */ #define CAN_CTRL1_LPB(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LPB_SHIFT)) & CAN_CTRL1_LPB_MASK) #define CAN_CTRL1_CLKSRC_MASK (0x2000U) #define CAN_CTRL1_CLKSRC_SHIFT (13U) +/*! CLKSRC - CAN Engine Clock Source + * 0b0..The CAN engine clock source is the oscillator clock. Under this condition, the oscillator clock frequency must be lower than the bus clock. + * 0b1..The CAN engine clock source is the peripheral clock. + */ #define CAN_CTRL1_CLKSRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_CLKSRC_SHIFT)) & CAN_CTRL1_CLKSRC_MASK) #define CAN_CTRL1_ERRMSK_MASK (0x4000U) #define CAN_CTRL1_ERRMSK_SHIFT (14U) +/*! ERRMSK - Error Mask + * 0b0..Error interrupt disabled. + * 0b1..Error interrupt enabled. + */ #define CAN_CTRL1_ERRMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_ERRMSK_SHIFT)) & CAN_CTRL1_ERRMSK_MASK) #define CAN_CTRL1_BOFFMSK_MASK (0x8000U) #define CAN_CTRL1_BOFFMSK_SHIFT (15U) +/*! BOFFMSK - Bus Off Mask + * 0b0..Bus Off interrupt disabled. + * 0b1..Bus Off interrupt enabled. + */ #define CAN_CTRL1_BOFFMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_BOFFMSK_SHIFT)) & CAN_CTRL1_BOFFMSK_MASK) #define CAN_CTRL1_PSEG2_MASK (0x70000U) #define CAN_CTRL1_PSEG2_SHIFT (16U) @@ -2309,125 +4434,268 @@ typedef struct { #define CAN_CTRL1_PRESDIV_MASK (0xFF000000U) #define CAN_CTRL1_PRESDIV_SHIFT (24U) #define CAN_CTRL1_PRESDIV(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PRESDIV_SHIFT)) & CAN_CTRL1_PRESDIV_MASK) +/*! @} */ /*! @name TIMER - Free Running Timer */ +/*! @{ */ #define CAN_TIMER_TIMER_MASK (0xFFFFU) #define CAN_TIMER_TIMER_SHIFT (0U) #define CAN_TIMER_TIMER(x) (((uint32_t)(((uint32_t)(x)) << CAN_TIMER_TIMER_SHIFT)) & CAN_TIMER_TIMER_MASK) +/*! @} */ /*! @name RXMGMASK - Rx Mailboxes Global Mask Register */ +/*! @{ */ #define CAN_RXMGMASK_MG_MASK (0xFFFFFFFFU) #define CAN_RXMGMASK_MG_SHIFT (0U) +/*! MG - Rx Mailboxes Global Mask Bits + * 0b00000000000000000000000000000000..The corresponding bit in the filter is "don't care." + * 0b00000000000000000000000000000001..The corresponding bit in the filter is checked. + */ #define CAN_RXMGMASK_MG(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXMGMASK_MG_SHIFT)) & CAN_RXMGMASK_MG_MASK) +/*! @} */ /*! @name RX14MASK - Rx 14 Mask register */ +/*! @{ */ #define CAN_RX14MASK_RX14M_MASK (0xFFFFFFFFU) #define CAN_RX14MASK_RX14M_SHIFT (0U) +/*! RX14M - Rx Buffer 14 Mask Bits + * 0b00000000000000000000000000000000..The corresponding bit in the filter is "don't care." + * 0b00000000000000000000000000000001..The corresponding bit in the filter is checked. + */ #define CAN_RX14MASK_RX14M(x) (((uint32_t)(((uint32_t)(x)) << CAN_RX14MASK_RX14M_SHIFT)) & CAN_RX14MASK_RX14M_MASK) +/*! @} */ /*! @name RX15MASK - Rx 15 Mask register */ +/*! @{ */ #define CAN_RX15MASK_RX15M_MASK (0xFFFFFFFFU) #define CAN_RX15MASK_RX15M_SHIFT (0U) +/*! RX15M - Rx Buffer 15 Mask Bits + * 0b00000000000000000000000000000000..The corresponding bit in the filter is "don't care." + * 0b00000000000000000000000000000001..The corresponding bit in the filter is checked. + */ #define CAN_RX15MASK_RX15M(x) (((uint32_t)(((uint32_t)(x)) << CAN_RX15MASK_RX15M_SHIFT)) & CAN_RX15MASK_RX15M_MASK) +/*! @} */ /*! @name ECR - Error Counter */ +/*! @{ */ #define CAN_ECR_TXERRCNT_MASK (0xFFU) #define CAN_ECR_TXERRCNT_SHIFT (0U) #define CAN_ECR_TXERRCNT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_TXERRCNT_SHIFT)) & CAN_ECR_TXERRCNT_MASK) #define CAN_ECR_RXERRCNT_MASK (0xFF00U) #define CAN_ECR_RXERRCNT_SHIFT (8U) #define CAN_ECR_RXERRCNT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_RXERRCNT_SHIFT)) & CAN_ECR_RXERRCNT_MASK) +/*! @} */ /*! @name ESR1 - Error and Status 1 register */ +/*! @{ */ #define CAN_ESR1_WAKINT_MASK (0x1U) #define CAN_ESR1_WAKINT_SHIFT (0U) +/*! WAKINT - Wake-Up Interrupt + * 0b0..No such occurrence. + * 0b1..Indicates a recessive to dominant transition was received on the CAN bus. + */ #define CAN_ESR1_WAKINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_WAKINT_SHIFT)) & CAN_ESR1_WAKINT_MASK) #define CAN_ESR1_ERRINT_MASK (0x2U) #define CAN_ESR1_ERRINT_SHIFT (1U) +/*! ERRINT - Error Interrupt + * 0b0..No such occurrence. + * 0b1..Indicates setting of any Error Bit in the Error and Status Register. + */ #define CAN_ESR1_ERRINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ERRINT_SHIFT)) & CAN_ESR1_ERRINT_MASK) #define CAN_ESR1_BOFFINT_MASK (0x4U) #define CAN_ESR1_BOFFINT_SHIFT (2U) +/*! BOFFINT - Bus Off Interrupt + * 0b0..No such occurrence. + * 0b1..FlexCAN module entered Bus Off state. + */ #define CAN_ESR1_BOFFINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BOFFINT_SHIFT)) & CAN_ESR1_BOFFINT_MASK) #define CAN_ESR1_RX_MASK (0x8U) #define CAN_ESR1_RX_SHIFT (3U) +/*! RX - FlexCAN In Reception + * 0b0..FlexCAN is not receiving a message. + * 0b1..FlexCAN is receiving a message. + */ #define CAN_ESR1_RX(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RX_SHIFT)) & CAN_ESR1_RX_MASK) #define CAN_ESR1_FLTCONF_MASK (0x30U) #define CAN_ESR1_FLTCONF_SHIFT (4U) +/*! FLTCONF - Fault Confinement State + * 0b00..Error Active + * 0b01..Error Passive + * 0b1x..Bus Off + */ #define CAN_ESR1_FLTCONF(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FLTCONF_SHIFT)) & CAN_ESR1_FLTCONF_MASK) #define CAN_ESR1_TX_MASK (0x40U) #define CAN_ESR1_TX_SHIFT (6U) +/*! TX - FlexCAN In Transmission + * 0b0..FlexCAN is not transmitting a message. + * 0b1..FlexCAN is transmitting a message. + */ #define CAN_ESR1_TX(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TX_SHIFT)) & CAN_ESR1_TX_MASK) #define CAN_ESR1_IDLE_MASK (0x80U) #define CAN_ESR1_IDLE_SHIFT (7U) +/*! IDLE + * 0b0..No such occurrence. + * 0b1..CAN bus is now IDLE. + */ #define CAN_ESR1_IDLE(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_IDLE_SHIFT)) & CAN_ESR1_IDLE_MASK) #define CAN_ESR1_RXWRN_MASK (0x100U) #define CAN_ESR1_RXWRN_SHIFT (8U) +/*! RXWRN - Rx Error Warning + * 0b0..No such occurrence. + * 0b1..RXERRCNT is greater than or equal to 96. + */ #define CAN_ESR1_RXWRN(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RXWRN_SHIFT)) & CAN_ESR1_RXWRN_MASK) #define CAN_ESR1_TXWRN_MASK (0x200U) #define CAN_ESR1_TXWRN_SHIFT (9U) +/*! TXWRN - TX Error Warning + * 0b0..No such occurrence. + * 0b1..TXERRCNT is greater than or equal to 96. + */ #define CAN_ESR1_TXWRN(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TXWRN_SHIFT)) & CAN_ESR1_TXWRN_MASK) #define CAN_ESR1_STFERR_MASK (0x400U) #define CAN_ESR1_STFERR_SHIFT (10U) +/*! STFERR - Stuffing Error + * 0b0..No such occurrence. + * 0b1..A Stuffing Error occurred since last read of this register. + */ #define CAN_ESR1_STFERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_STFERR_SHIFT)) & CAN_ESR1_STFERR_MASK) #define CAN_ESR1_FRMERR_MASK (0x800U) #define CAN_ESR1_FRMERR_SHIFT (11U) +/*! FRMERR - Form Error + * 0b0..No such occurrence. + * 0b1..A Form Error occurred since last read of this register. + */ #define CAN_ESR1_FRMERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FRMERR_SHIFT)) & CAN_ESR1_FRMERR_MASK) #define CAN_ESR1_CRCERR_MASK (0x1000U) #define CAN_ESR1_CRCERR_SHIFT (12U) +/*! CRCERR - Cyclic Redundancy Check Error + * 0b0..No such occurrence. + * 0b1..A CRC error occurred since last read of this register. + */ #define CAN_ESR1_CRCERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_CRCERR_SHIFT)) & CAN_ESR1_CRCERR_MASK) #define CAN_ESR1_ACKERR_MASK (0x2000U) #define CAN_ESR1_ACKERR_SHIFT (13U) +/*! ACKERR - Acknowledge Error + * 0b0..No such occurrence. + * 0b1..An ACK error occurred since last read of this register. + */ #define CAN_ESR1_ACKERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ACKERR_SHIFT)) & CAN_ESR1_ACKERR_MASK) #define CAN_ESR1_BIT0ERR_MASK (0x4000U) #define CAN_ESR1_BIT0ERR_SHIFT (14U) +/*! BIT0ERR - Bit0 Error + * 0b0..No such occurrence. + * 0b1..At least one bit sent as dominant is received as recessive. + */ #define CAN_ESR1_BIT0ERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT0ERR_SHIFT)) & CAN_ESR1_BIT0ERR_MASK) #define CAN_ESR1_BIT1ERR_MASK (0x8000U) #define CAN_ESR1_BIT1ERR_SHIFT (15U) +/*! BIT1ERR - Bit1 Error + * 0b0..No such occurrence. + * 0b1..At least one bit sent as recessive is received as dominant. + */ #define CAN_ESR1_BIT1ERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT1ERR_SHIFT)) & CAN_ESR1_BIT1ERR_MASK) #define CAN_ESR1_RWRNINT_MASK (0x10000U) #define CAN_ESR1_RWRNINT_SHIFT (16U) +/*! RWRNINT - Rx Warning Interrupt Flag + * 0b0..No such occurrence. + * 0b1..The Rx error counter transitioned from less than 96 to greater than or equal to 96. + */ #define CAN_ESR1_RWRNINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RWRNINT_SHIFT)) & CAN_ESR1_RWRNINT_MASK) #define CAN_ESR1_TWRNINT_MASK (0x20000U) #define CAN_ESR1_TWRNINT_SHIFT (17U) +/*! TWRNINT - Tx Warning Interrupt Flag + * 0b0..No such occurrence. + * 0b1..The Tx error counter transitioned from less than 96 to greater than or equal to 96. + */ #define CAN_ESR1_TWRNINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TWRNINT_SHIFT)) & CAN_ESR1_TWRNINT_MASK) #define CAN_ESR1_SYNCH_MASK (0x40000U) #define CAN_ESR1_SYNCH_SHIFT (18U) +/*! SYNCH - CAN Synchronization Status + * 0b0..FlexCAN is not synchronized to the CAN bus. + * 0b1..FlexCAN is synchronized to the CAN bus. + */ #define CAN_ESR1_SYNCH(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_SYNCH_SHIFT)) & CAN_ESR1_SYNCH_MASK) +/*! @} */ /*! @name IMASK1 - Interrupt Masks 1 register */ +/*! @{ */ #define CAN_IMASK1_BUFLM_MASK (0xFFFFFFFFU) #define CAN_IMASK1_BUFLM_SHIFT (0U) +/*! BUFLM - Buffer MB i Mask + * 0b00000000000000000000000000000000..The corresponding buffer Interrupt is disabled. + * 0b00000000000000000000000000000001..The corresponding buffer Interrupt is enabled. + */ #define CAN_IMASK1_BUFLM(x) (((uint32_t)(((uint32_t)(x)) << CAN_IMASK1_BUFLM_SHIFT)) & CAN_IMASK1_BUFLM_MASK) +/*! @} */ /*! @name IFLAG1 - Interrupt Flags 1 register */ +/*! @{ */ #define CAN_IFLAG1_BUF0I_MASK (0x1U) #define CAN_IFLAG1_BUF0I_SHIFT (0U) +/*! BUF0I - Buffer MB0 Interrupt Or "reserved" + * 0b0..The corresponding buffer has no occurrence of successfully completed transmission or reception when MCR[RFEN]=0. + * 0b1..The corresponding buffer has successfully completed transmission or reception when MCR[RFEN]=0. + */ #define CAN_IFLAG1_BUF0I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF0I_SHIFT)) & CAN_IFLAG1_BUF0I_MASK) #define CAN_IFLAG1_BUF4TO1I_MASK (0x1EU) #define CAN_IFLAG1_BUF4TO1I_SHIFT (1U) +/*! BUF4TO1I - Buffer MB i Interrupt Or "reserved" + * 0b0000..The corresponding buffer has no occurrence of successfully completed transmission or reception when MCR[RFEN]=0. + * 0b0001..The corresponding buffer has successfully completed transmission or reception when MCR[RFEN]=0. + */ #define CAN_IFLAG1_BUF4TO1I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF4TO1I_SHIFT)) & CAN_IFLAG1_BUF4TO1I_MASK) #define CAN_IFLAG1_BUF5I_MASK (0x20U) #define CAN_IFLAG1_BUF5I_SHIFT (5U) +/*! BUF5I - Buffer MB5 Interrupt Or "Frames available in Rx FIFO" + * 0b0..No occurrence of MB5 completing transmission/reception when MCR[RFEN]=0, or of frame(s) available in the FIFO, when MCR[RFEN]=1 + * 0b1..MB5 completed transmission/reception when MCR[RFEN]=0, or frame(s) available in the Rx FIFO when MCR[RFEN]=1 + */ #define CAN_IFLAG1_BUF5I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF5I_SHIFT)) & CAN_IFLAG1_BUF5I_MASK) #define CAN_IFLAG1_BUF6I_MASK (0x40U) #define CAN_IFLAG1_BUF6I_SHIFT (6U) +/*! BUF6I - Buffer MB6 Interrupt Or "Rx FIFO Warning" + * 0b0..No occurrence of MB6 completing transmission/reception when MCR[RFEN]=0, or of Rx FIFO almost full when MCR[RFEN]=1 + * 0b1..MB6 completed transmission/reception when MCR[RFEN]=0, or Rx FIFO almost full when MCR[RFEN]=1 + */ #define CAN_IFLAG1_BUF6I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF6I_SHIFT)) & CAN_IFLAG1_BUF6I_MASK) #define CAN_IFLAG1_BUF7I_MASK (0x80U) #define CAN_IFLAG1_BUF7I_SHIFT (7U) +/*! BUF7I - Buffer MB7 Interrupt Or "Rx FIFO Overflow" + * 0b0..No occurrence of MB7 completing transmission/reception when MCR[RFEN]=0, or of Rx FIFO overflow when MCR[RFEN]=1 + * 0b1..MB7 completed transmission/reception when MCR[RFEN]=0, or Rx FIFO overflow when MCR[RFEN]=1 + */ #define CAN_IFLAG1_BUF7I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF7I_SHIFT)) & CAN_IFLAG1_BUF7I_MASK) #define CAN_IFLAG1_BUF31TO8I_MASK (0xFFFFFF00U) #define CAN_IFLAG1_BUF31TO8I_SHIFT (8U) +/*! BUF31TO8I - Buffer MBi Interrupt + * 0b000000000000000000000000..The corresponding buffer has no occurrence of successfully completed transmission or reception. + * 0b000000000000000000000001..The corresponding buffer has successfully completed transmission or reception. + */ #define CAN_IFLAG1_BUF31TO8I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF31TO8I_SHIFT)) & CAN_IFLAG1_BUF31TO8I_MASK) +/*! @} */ /*! @name CTRL2 - Control 2 register */ +/*! @{ */ #define CAN_CTRL2_EACEN_MASK (0x10000U) #define CAN_CTRL2_EACEN_SHIFT (16U) +/*! EACEN - Entire Frame Arbitration Field Comparison Enable For Rx Mailboxes + * 0b0..Rx Mailbox filter's IDE bit is always compared and RTR is never compared despite mask bits. + * 0b1..Enables the comparison of both Rx Mailbox filter's IDE and RTR bit with their corresponding bits within the incoming frame. Mask bits do apply. + */ #define CAN_CTRL2_EACEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_EACEN_SHIFT)) & CAN_CTRL2_EACEN_MASK) #define CAN_CTRL2_RRS_MASK (0x20000U) #define CAN_CTRL2_RRS_SHIFT (17U) +/*! RRS - Remote Request Storing + * 0b0..Remote Response Frame is generated. + * 0b1..Remote Request Frame is stored. + */ #define CAN_CTRL2_RRS(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_RRS_SHIFT)) & CAN_CTRL2_RRS_MASK) #define CAN_CTRL2_MRP_MASK (0x40000U) #define CAN_CTRL2_MRP_SHIFT (18U) +/*! MRP - Mailboxes Reception Priority + * 0b0..Matching starts from Rx FIFO and continues on Mailboxes. + * 0b1..Matching starts from Mailboxes and continues on Rx FIFO. + */ #define CAN_CTRL2_MRP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_MRP_SHIFT)) & CAN_CTRL2_MRP_MASK) #define CAN_CTRL2_TASD_MASK (0xF80000U) #define CAN_CTRL2_TASD_SHIFT (19U) @@ -2437,38 +4705,64 @@ typedef struct { #define CAN_CTRL2_RFFN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_RFFN_SHIFT)) & CAN_CTRL2_RFFN_MASK) #define CAN_CTRL2_WRMFRZ_MASK (0x10000000U) #define CAN_CTRL2_WRMFRZ_SHIFT (28U) +/*! WRMFRZ - Write-Access To Memory In Freeze Mode + * 0b0..Maintain the write access restrictions. + * 0b1..Enable unrestricted write access to FlexCAN memory. + */ #define CAN_CTRL2_WRMFRZ(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_WRMFRZ_SHIFT)) & CAN_CTRL2_WRMFRZ_MASK) +/*! @} */ /*! @name ESR2 - Error and Status 2 register */ +/*! @{ */ #define CAN_ESR2_IMB_MASK (0x2000U) #define CAN_ESR2_IMB_SHIFT (13U) +/*! IMB - Inactive Mailbox + * 0b0..If ESR2[VPS] is asserted, the ESR2[LPTM] is not an inactive Mailbox. + * 0b1..If ESR2[VPS] is asserted, there is at least one inactive Mailbox. LPTM content is the number of the first one. + */ #define CAN_ESR2_IMB(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_IMB_SHIFT)) & CAN_ESR2_IMB_MASK) #define CAN_ESR2_VPS_MASK (0x4000U) #define CAN_ESR2_VPS_SHIFT (14U) +/*! VPS - Valid Priority Status + * 0b0..Contents of IMB and LPTM are invalid. + * 0b1..Contents of IMB and LPTM are valid. + */ #define CAN_ESR2_VPS(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_VPS_SHIFT)) & CAN_ESR2_VPS_MASK) #define CAN_ESR2_LPTM_MASK (0x7F0000U) #define CAN_ESR2_LPTM_SHIFT (16U) #define CAN_ESR2_LPTM(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_LPTM_SHIFT)) & CAN_ESR2_LPTM_MASK) +/*! @} */ /*! @name CRCR - CRC Register */ +/*! @{ */ #define CAN_CRCR_TXCRC_MASK (0x7FFFU) #define CAN_CRCR_TXCRC_SHIFT (0U) #define CAN_CRCR_TXCRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CRCR_TXCRC_SHIFT)) & CAN_CRCR_TXCRC_MASK) #define CAN_CRCR_MBCRC_MASK (0x7F0000U) #define CAN_CRCR_MBCRC_SHIFT (16U) #define CAN_CRCR_MBCRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CRCR_MBCRC_SHIFT)) & CAN_CRCR_MBCRC_MASK) +/*! @} */ /*! @name RXFGMASK - Rx FIFO Global Mask register */ +/*! @{ */ #define CAN_RXFGMASK_FGM_MASK (0xFFFFFFFFU) #define CAN_RXFGMASK_FGM_SHIFT (0U) +/*! FGM - Rx FIFO Global Mask Bits + * 0b00000000000000000000000000000000..The corresponding bit in the filter is "don't care." + * 0b00000000000000000000000000000001..The corresponding bit in the filter is checked. + */ #define CAN_RXFGMASK_FGM(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXFGMASK_FGM_SHIFT)) & CAN_RXFGMASK_FGM_MASK) +/*! @} */ /*! @name RXFIR - Rx FIFO Information Register */ +/*! @{ */ #define CAN_RXFIR_IDHIT_MASK (0x1FFU) #define CAN_RXFIR_IDHIT_SHIFT (0U) #define CAN_RXFIR_IDHIT(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXFIR_IDHIT_SHIFT)) & CAN_RXFIR_IDHIT_MASK) +/*! @} */ /*! @name CS - Message Buffer 0 CS Register..Message Buffer 15 CS Register */ +/*! @{ */ #define CAN_CS_TIME_STAMP_MASK (0xFFFFU) #define CAN_CS_TIME_STAMP_SHIFT (0U) #define CAN_CS_TIME_STAMP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_TIME_STAMP_SHIFT)) & CAN_CS_TIME_STAMP_MASK) @@ -2487,11 +4781,13 @@ typedef struct { #define CAN_CS_CODE_MASK (0xF000000U) #define CAN_CS_CODE_SHIFT (24U) #define CAN_CS_CODE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_CODE_SHIFT)) & CAN_CS_CODE_MASK) +/*! @} */ /* The count of CAN_CS */ #define CAN_CS_COUNT (16U) /*! @name ID - Message Buffer 0 ID Register..Message Buffer 15 ID Register */ +/*! @{ */ #define CAN_ID_EXT_MASK (0x3FFFFU) #define CAN_ID_EXT_SHIFT (0U) #define CAN_ID_EXT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_EXT_SHIFT)) & CAN_ID_EXT_MASK) @@ -2501,11 +4797,13 @@ typedef struct { #define CAN_ID_PRIO_MASK (0xE0000000U) #define CAN_ID_PRIO_SHIFT (29U) #define CAN_ID_PRIO(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_PRIO_SHIFT)) & CAN_ID_PRIO_MASK) +/*! @} */ /* The count of CAN_ID */ #define CAN_ID_COUNT (16U) /*! @name WORD0 - Message Buffer 0 WORD0 Register..Message Buffer 15 WORD0 Register */ +/*! @{ */ #define CAN_WORD0_DATA_BYTE_3_MASK (0xFFU) #define CAN_WORD0_DATA_BYTE_3_SHIFT (0U) #define CAN_WORD0_DATA_BYTE_3(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_3_SHIFT)) & CAN_WORD0_DATA_BYTE_3_MASK) @@ -2518,11 +4816,13 @@ typedef struct { #define CAN_WORD0_DATA_BYTE_0_MASK (0xFF000000U) #define CAN_WORD0_DATA_BYTE_0_SHIFT (24U) #define CAN_WORD0_DATA_BYTE_0(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_0_SHIFT)) & CAN_WORD0_DATA_BYTE_0_MASK) +/*! @} */ /* The count of CAN_WORD0 */ #define CAN_WORD0_COUNT (16U) /*! @name WORD1 - Message Buffer 0 WORD1 Register..Message Buffer 15 WORD1 Register */ +/*! @{ */ #define CAN_WORD1_DATA_BYTE_7_MASK (0xFFU) #define CAN_WORD1_DATA_BYTE_7_SHIFT (0U) #define CAN_WORD1_DATA_BYTE_7(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_7_SHIFT)) & CAN_WORD1_DATA_BYTE_7_MASK) @@ -2535,14 +4835,21 @@ typedef struct { #define CAN_WORD1_DATA_BYTE_4_MASK (0xFF000000U) #define CAN_WORD1_DATA_BYTE_4_SHIFT (24U) #define CAN_WORD1_DATA_BYTE_4(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_4_SHIFT)) & CAN_WORD1_DATA_BYTE_4_MASK) +/*! @} */ /* The count of CAN_WORD1 */ #define CAN_WORD1_COUNT (16U) /*! @name RXIMR - Rx Individual Mask Registers */ +/*! @{ */ #define CAN_RXIMR_MI_MASK (0xFFFFFFFFU) #define CAN_RXIMR_MI_SHIFT (0U) +/*! MI - Individual Mask Bits + * 0b00000000000000000000000000000000..The corresponding bit in the filter is "don't care." + * 0b00000000000000000000000000000001..The corresponding bit in the filter is checked. + */ #define CAN_RXIMR_MI(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXIMR_MI_SHIFT)) & CAN_RXIMR_MI_MASK) +/*! @} */ /* The count of CAN_RXIMR */ #define CAN_RXIMR_COUNT (16U) @@ -2631,6 +4938,7 @@ typedef struct { */ /*! @name DIRECT - Direct access register 0..Direct access register 15 */ +/*! @{ */ #define CAU_DIRECT_CAU_DIRECT0_MASK (0xFFFFFFFFU) #define CAU_DIRECT_CAU_DIRECT0_SHIFT (0U) #define CAU_DIRECT_CAU_DIRECT0(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT0_SHIFT)) & CAU_DIRECT_CAU_DIRECT0_MASK) @@ -2679,27 +4987,45 @@ typedef struct { #define CAU_DIRECT_CAU_DIRECT15_MASK (0xFFFFFFFFU) #define CAU_DIRECT_CAU_DIRECT15_SHIFT (0U) #define CAU_DIRECT_CAU_DIRECT15(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT15_SHIFT)) & CAU_DIRECT_CAU_DIRECT15_MASK) +/*! @} */ /* The count of CAU_DIRECT */ #define CAU_DIRECT_COUNT (16U) /*! @name LDR_CASR - Status register - Load Register command */ +/*! @{ */ #define CAU_LDR_CASR_IC_MASK (0x1U) #define CAU_LDR_CASR_IC_SHIFT (0U) +/*! IC + * 0b0..No illegal commands issued + * 0b1..Illegal command issued + */ #define CAU_LDR_CASR_IC(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CASR_IC_SHIFT)) & CAU_LDR_CASR_IC_MASK) #define CAU_LDR_CASR_DPE_MASK (0x2U) #define CAU_LDR_CASR_DPE_SHIFT (1U) +/*! DPE + * 0b0..No error detected + * 0b1..DES key parity error detected + */ #define CAU_LDR_CASR_DPE(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CASR_DPE_SHIFT)) & CAU_LDR_CASR_DPE_MASK) #define CAU_LDR_CASR_VER_MASK (0xF0000000U) #define CAU_LDR_CASR_VER_SHIFT (28U) +/*! VER - CAU version + * 0b0001..Initial CAU version + * 0b0010..Second version, added support for SHA-256 algorithm.(This is the value on this device) + */ #define CAU_LDR_CASR_VER(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CASR_VER_SHIFT)) & CAU_LDR_CASR_VER_MASK) +/*! @} */ /*! @name LDR_CAA - Accumulator register - Load Register command */ +/*! @{ */ #define CAU_LDR_CAA_ACC_MASK (0xFFFFFFFFU) #define CAU_LDR_CAA_ACC_SHIFT (0U) #define CAU_LDR_CAA_ACC(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CAA_ACC_SHIFT)) & CAU_LDR_CAA_ACC_MASK) +/*! @} */ /*! @name LDR_CA - General Purpose Register 0 - Load Register command..General Purpose Register 8 - Load Register command */ +/*! @{ */ #define CAU_LDR_CA_CA0_MASK (0xFFFFFFFFU) #define CAU_LDR_CA_CA0_SHIFT (0U) #define CAU_LDR_CA_CA0(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA0_SHIFT)) & CAU_LDR_CA_CA0_MASK) @@ -2727,27 +5053,45 @@ typedef struct { #define CAU_LDR_CA_CA8_MASK (0xFFFFFFFFU) #define CAU_LDR_CA_CA8_SHIFT (0U) #define CAU_LDR_CA_CA8(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA8_SHIFT)) & CAU_LDR_CA_CA8_MASK) +/*! @} */ /* The count of CAU_LDR_CA */ #define CAU_LDR_CA_COUNT (9U) /*! @name STR_CASR - Status register - Store Register command */ +/*! @{ */ #define CAU_STR_CASR_IC_MASK (0x1U) #define CAU_STR_CASR_IC_SHIFT (0U) +/*! IC + * 0b0..No illegal commands issued + * 0b1..Illegal command issued + */ #define CAU_STR_CASR_IC(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CASR_IC_SHIFT)) & CAU_STR_CASR_IC_MASK) #define CAU_STR_CASR_DPE_MASK (0x2U) #define CAU_STR_CASR_DPE_SHIFT (1U) +/*! DPE + * 0b0..No error detected + * 0b1..DES key parity error detected + */ #define CAU_STR_CASR_DPE(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CASR_DPE_SHIFT)) & CAU_STR_CASR_DPE_MASK) #define CAU_STR_CASR_VER_MASK (0xF0000000U) #define CAU_STR_CASR_VER_SHIFT (28U) +/*! VER - CAU version + * 0b0001..Initial CAU version + * 0b0010..Second version, added support for SHA-256 algorithm.(This is the value on this device) + */ #define CAU_STR_CASR_VER(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CASR_VER_SHIFT)) & CAU_STR_CASR_VER_MASK) +/*! @} */ /*! @name STR_CAA - Accumulator register - Store Register command */ +/*! @{ */ #define CAU_STR_CAA_ACC_MASK (0xFFFFFFFFU) #define CAU_STR_CAA_ACC_SHIFT (0U) #define CAU_STR_CAA_ACC(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CAA_ACC_SHIFT)) & CAU_STR_CAA_ACC_MASK) +/*! @} */ /*! @name STR_CA - General Purpose Register 0 - Store Register command..General Purpose Register 8 - Store Register command */ +/*! @{ */ #define CAU_STR_CA_CA0_MASK (0xFFFFFFFFU) #define CAU_STR_CA_CA0_SHIFT (0U) #define CAU_STR_CA_CA0(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA0_SHIFT)) & CAU_STR_CA_CA0_MASK) @@ -2775,27 +5119,45 @@ typedef struct { #define CAU_STR_CA_CA8_MASK (0xFFFFFFFFU) #define CAU_STR_CA_CA8_SHIFT (0U) #define CAU_STR_CA_CA8(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA8_SHIFT)) & CAU_STR_CA_CA8_MASK) +/*! @} */ /* The count of CAU_STR_CA */ #define CAU_STR_CA_COUNT (9U) /*! @name ADR_CASR - Status register - Add Register command */ +/*! @{ */ #define CAU_ADR_CASR_IC_MASK (0x1U) #define CAU_ADR_CASR_IC_SHIFT (0U) +/*! IC + * 0b0..No illegal commands issued + * 0b1..Illegal command issued + */ #define CAU_ADR_CASR_IC(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CASR_IC_SHIFT)) & CAU_ADR_CASR_IC_MASK) #define CAU_ADR_CASR_DPE_MASK (0x2U) #define CAU_ADR_CASR_DPE_SHIFT (1U) +/*! DPE + * 0b0..No error detected + * 0b1..DES key parity error detected + */ #define CAU_ADR_CASR_DPE(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CASR_DPE_SHIFT)) & CAU_ADR_CASR_DPE_MASK) #define CAU_ADR_CASR_VER_MASK (0xF0000000U) #define CAU_ADR_CASR_VER_SHIFT (28U) +/*! VER - CAU version + * 0b0001..Initial CAU version + * 0b0010..Second version, added support for SHA-256 algorithm.(This is the value on this device) + */ #define CAU_ADR_CASR_VER(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CASR_VER_SHIFT)) & CAU_ADR_CASR_VER_MASK) +/*! @} */ /*! @name ADR_CAA - Accumulator register - Add to register command */ +/*! @{ */ #define CAU_ADR_CAA_ACC_MASK (0xFFFFFFFFU) #define CAU_ADR_CAA_ACC_SHIFT (0U) #define CAU_ADR_CAA_ACC(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CAA_ACC_SHIFT)) & CAU_ADR_CAA_ACC_MASK) +/*! @} */ /*! @name ADR_CA - General Purpose Register 0 - Add to register command..General Purpose Register 8 - Add to register command */ +/*! @{ */ #define CAU_ADR_CA_CA0_MASK (0xFFFFFFFFU) #define CAU_ADR_CA_CA0_SHIFT (0U) #define CAU_ADR_CA_CA0(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA0_SHIFT)) & CAU_ADR_CA_CA0_MASK) @@ -2823,27 +5185,45 @@ typedef struct { #define CAU_ADR_CA_CA8_MASK (0xFFFFFFFFU) #define CAU_ADR_CA_CA8_SHIFT (0U) #define CAU_ADR_CA_CA8(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA8_SHIFT)) & CAU_ADR_CA_CA8_MASK) +/*! @} */ /* The count of CAU_ADR_CA */ #define CAU_ADR_CA_COUNT (9U) /*! @name RADR_CASR - Status register - Reverse and Add to Register command */ +/*! @{ */ #define CAU_RADR_CASR_IC_MASK (0x1U) #define CAU_RADR_CASR_IC_SHIFT (0U) +/*! IC + * 0b0..No illegal commands issued + * 0b1..Illegal command issued + */ #define CAU_RADR_CASR_IC(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CASR_IC_SHIFT)) & CAU_RADR_CASR_IC_MASK) #define CAU_RADR_CASR_DPE_MASK (0x2U) #define CAU_RADR_CASR_DPE_SHIFT (1U) +/*! DPE + * 0b0..No error detected + * 0b1..DES key parity error detected + */ #define CAU_RADR_CASR_DPE(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CASR_DPE_SHIFT)) & CAU_RADR_CASR_DPE_MASK) #define CAU_RADR_CASR_VER_MASK (0xF0000000U) #define CAU_RADR_CASR_VER_SHIFT (28U) +/*! VER - CAU version + * 0b0001..Initial CAU version + * 0b0010..Second version, added support for SHA-256 algorithm.(This is the value on this device) + */ #define CAU_RADR_CASR_VER(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CASR_VER_SHIFT)) & CAU_RADR_CASR_VER_MASK) +/*! @} */ /*! @name RADR_CAA - Accumulator register - Reverse and Add to Register command */ +/*! @{ */ #define CAU_RADR_CAA_ACC_MASK (0xFFFFFFFFU) #define CAU_RADR_CAA_ACC_SHIFT (0U) #define CAU_RADR_CAA_ACC(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CAA_ACC_SHIFT)) & CAU_RADR_CAA_ACC_MASK) +/*! @} */ /*! @name RADR_CA - General Purpose Register 0 - Reverse and Add to Register command..General Purpose Register 8 - Reverse and Add to Register command */ +/*! @{ */ #define CAU_RADR_CA_CA0_MASK (0xFFFFFFFFU) #define CAU_RADR_CA_CA0_SHIFT (0U) #define CAU_RADR_CA_CA0(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA0_SHIFT)) & CAU_RADR_CA_CA0_MASK) @@ -2871,27 +5251,45 @@ typedef struct { #define CAU_RADR_CA_CA8_MASK (0xFFFFFFFFU) #define CAU_RADR_CA_CA8_SHIFT (0U) #define CAU_RADR_CA_CA8(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA8_SHIFT)) & CAU_RADR_CA_CA8_MASK) +/*! @} */ /* The count of CAU_RADR_CA */ #define CAU_RADR_CA_COUNT (9U) /*! @name XOR_CASR - Status register - Exclusive Or command */ +/*! @{ */ #define CAU_XOR_CASR_IC_MASK (0x1U) #define CAU_XOR_CASR_IC_SHIFT (0U) +/*! IC + * 0b0..No illegal commands issued + * 0b1..Illegal command issued + */ #define CAU_XOR_CASR_IC(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CASR_IC_SHIFT)) & CAU_XOR_CASR_IC_MASK) #define CAU_XOR_CASR_DPE_MASK (0x2U) #define CAU_XOR_CASR_DPE_SHIFT (1U) +/*! DPE + * 0b0..No error detected + * 0b1..DES key parity error detected + */ #define CAU_XOR_CASR_DPE(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CASR_DPE_SHIFT)) & CAU_XOR_CASR_DPE_MASK) #define CAU_XOR_CASR_VER_MASK (0xF0000000U) #define CAU_XOR_CASR_VER_SHIFT (28U) +/*! VER - CAU version + * 0b0001..Initial CAU version + * 0b0010..Second version, added support for SHA-256 algorithm.(This is the value on this device) + */ #define CAU_XOR_CASR_VER(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CASR_VER_SHIFT)) & CAU_XOR_CASR_VER_MASK) +/*! @} */ /*! @name XOR_CAA - Accumulator register - Exclusive Or command */ +/*! @{ */ #define CAU_XOR_CAA_ACC_MASK (0xFFFFFFFFU) #define CAU_XOR_CAA_ACC_SHIFT (0U) #define CAU_XOR_CAA_ACC(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CAA_ACC_SHIFT)) & CAU_XOR_CAA_ACC_MASK) +/*! @} */ /*! @name XOR_CA - General Purpose Register 0 - Exclusive Or command..General Purpose Register 8 - Exclusive Or command */ +/*! @{ */ #define CAU_XOR_CA_CA0_MASK (0xFFFFFFFFU) #define CAU_XOR_CA_CA0_SHIFT (0U) #define CAU_XOR_CA_CA0(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA0_SHIFT)) & CAU_XOR_CA_CA0_MASK) @@ -2919,27 +5317,45 @@ typedef struct { #define CAU_XOR_CA_CA8_MASK (0xFFFFFFFFU) #define CAU_XOR_CA_CA8_SHIFT (0U) #define CAU_XOR_CA_CA8(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA8_SHIFT)) & CAU_XOR_CA_CA8_MASK) +/*! @} */ /* The count of CAU_XOR_CA */ #define CAU_XOR_CA_COUNT (9U) /*! @name ROTL_CASR - Status register - Rotate Left command */ +/*! @{ */ #define CAU_ROTL_CASR_IC_MASK (0x1U) #define CAU_ROTL_CASR_IC_SHIFT (0U) +/*! IC + * 0b0..No illegal commands issued + * 0b1..Illegal command issued + */ #define CAU_ROTL_CASR_IC(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CASR_IC_SHIFT)) & CAU_ROTL_CASR_IC_MASK) #define CAU_ROTL_CASR_DPE_MASK (0x2U) #define CAU_ROTL_CASR_DPE_SHIFT (1U) +/*! DPE + * 0b0..No error detected + * 0b1..DES key parity error detected + */ #define CAU_ROTL_CASR_DPE(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CASR_DPE_SHIFT)) & CAU_ROTL_CASR_DPE_MASK) #define CAU_ROTL_CASR_VER_MASK (0xF0000000U) #define CAU_ROTL_CASR_VER_SHIFT (28U) +/*! VER - CAU version + * 0b0001..Initial CAU version + * 0b0010..Second version, added support for SHA-256 algorithm.(This is the value on this device) + */ #define CAU_ROTL_CASR_VER(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CASR_VER_SHIFT)) & CAU_ROTL_CASR_VER_MASK) +/*! @} */ /*! @name ROTL_CAA - Accumulator register - Rotate Left command */ +/*! @{ */ #define CAU_ROTL_CAA_ACC_MASK (0xFFFFFFFFU) #define CAU_ROTL_CAA_ACC_SHIFT (0U) #define CAU_ROTL_CAA_ACC(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CAA_ACC_SHIFT)) & CAU_ROTL_CAA_ACC_MASK) +/*! @} */ /*! @name ROTL_CA - General Purpose Register 0 - Rotate Left command..General Purpose Register 8 - Rotate Left command */ +/*! @{ */ #define CAU_ROTL_CA_CA0_MASK (0xFFFFFFFFU) #define CAU_ROTL_CA_CA0_SHIFT (0U) #define CAU_ROTL_CA_CA0(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA0_SHIFT)) & CAU_ROTL_CA_CA0_MASK) @@ -2967,27 +5383,45 @@ typedef struct { #define CAU_ROTL_CA_CA8_MASK (0xFFFFFFFFU) #define CAU_ROTL_CA_CA8_SHIFT (0U) #define CAU_ROTL_CA_CA8(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA8_SHIFT)) & CAU_ROTL_CA_CA8_MASK) +/*! @} */ /* The count of CAU_ROTL_CA */ #define CAU_ROTL_CA_COUNT (9U) /*! @name AESC_CASR - Status register - AES Column Operation command */ +/*! @{ */ #define CAU_AESC_CASR_IC_MASK (0x1U) #define CAU_AESC_CASR_IC_SHIFT (0U) +/*! IC + * 0b0..No illegal commands issued + * 0b1..Illegal command issued + */ #define CAU_AESC_CASR_IC(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CASR_IC_SHIFT)) & CAU_AESC_CASR_IC_MASK) #define CAU_AESC_CASR_DPE_MASK (0x2U) #define CAU_AESC_CASR_DPE_SHIFT (1U) +/*! DPE + * 0b0..No error detected + * 0b1..DES key parity error detected + */ #define CAU_AESC_CASR_DPE(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CASR_DPE_SHIFT)) & CAU_AESC_CASR_DPE_MASK) #define CAU_AESC_CASR_VER_MASK (0xF0000000U) #define CAU_AESC_CASR_VER_SHIFT (28U) +/*! VER - CAU version + * 0b0001..Initial CAU version + * 0b0010..Second version, added support for SHA-256 algorithm.(This is the value on this device) + */ #define CAU_AESC_CASR_VER(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CASR_VER_SHIFT)) & CAU_AESC_CASR_VER_MASK) +/*! @} */ /*! @name AESC_CAA - Accumulator register - AES Column Operation command */ +/*! @{ */ #define CAU_AESC_CAA_ACC_MASK (0xFFFFFFFFU) #define CAU_AESC_CAA_ACC_SHIFT (0U) #define CAU_AESC_CAA_ACC(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CAA_ACC_SHIFT)) & CAU_AESC_CAA_ACC_MASK) +/*! @} */ /*! @name AESC_CA - General Purpose Register 0 - AES Column Operation command..General Purpose Register 8 - AES Column Operation command */ +/*! @{ */ #define CAU_AESC_CA_CA0_MASK (0xFFFFFFFFU) #define CAU_AESC_CA_CA0_SHIFT (0U) #define CAU_AESC_CA_CA0(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA0_SHIFT)) & CAU_AESC_CA_CA0_MASK) @@ -3015,27 +5449,45 @@ typedef struct { #define CAU_AESC_CA_CA8_MASK (0xFFFFFFFFU) #define CAU_AESC_CA_CA8_SHIFT (0U) #define CAU_AESC_CA_CA8(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA8_SHIFT)) & CAU_AESC_CA_CA8_MASK) +/*! @} */ /* The count of CAU_AESC_CA */ #define CAU_AESC_CA_COUNT (9U) /*! @name AESIC_CASR - Status register - AES Inverse Column Operation command */ +/*! @{ */ #define CAU_AESIC_CASR_IC_MASK (0x1U) #define CAU_AESIC_CASR_IC_SHIFT (0U) +/*! IC + * 0b0..No illegal commands issued + * 0b1..Illegal command issued + */ #define CAU_AESIC_CASR_IC(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CASR_IC_SHIFT)) & CAU_AESIC_CASR_IC_MASK) #define CAU_AESIC_CASR_DPE_MASK (0x2U) #define CAU_AESIC_CASR_DPE_SHIFT (1U) +/*! DPE + * 0b0..No error detected + * 0b1..DES key parity error detected + */ #define CAU_AESIC_CASR_DPE(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CASR_DPE_SHIFT)) & CAU_AESIC_CASR_DPE_MASK) #define CAU_AESIC_CASR_VER_MASK (0xF0000000U) #define CAU_AESIC_CASR_VER_SHIFT (28U) +/*! VER - CAU version + * 0b0001..Initial CAU version + * 0b0010..Second version, added support for SHA-256 algorithm.(This is the value on this device) + */ #define CAU_AESIC_CASR_VER(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CASR_VER_SHIFT)) & CAU_AESIC_CASR_VER_MASK) +/*! @} */ /*! @name AESIC_CAA - Accumulator register - AES Inverse Column Operation command */ +/*! @{ */ #define CAU_AESIC_CAA_ACC_MASK (0xFFFFFFFFU) #define CAU_AESIC_CAA_ACC_SHIFT (0U) #define CAU_AESIC_CAA_ACC(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CAA_ACC_SHIFT)) & CAU_AESIC_CAA_ACC_MASK) +/*! @} */ /*! @name AESIC_CA - General Purpose Register 0 - AES Inverse Column Operation command..General Purpose Register 8 - AES Inverse Column Operation command */ +/*! @{ */ #define CAU_AESIC_CA_CA0_MASK (0xFFFFFFFFU) #define CAU_AESIC_CA_CA0_SHIFT (0U) #define CAU_AESIC_CA_CA0(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA0_SHIFT)) & CAU_AESIC_CA_CA0_MASK) @@ -3063,6 +5515,7 @@ typedef struct { #define CAU_AESIC_CA_CA8_MASK (0xFFFFFFFFU) #define CAU_AESIC_CA_CA8_SHIFT (0U) #define CAU_AESIC_CA_CA8(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA8_SHIFT)) & CAU_AESIC_CA_CA8_MASK) +/*! @} */ /* The count of CAU_AESIC_CA */ #define CAU_AESIC_CA_COUNT (9U) @@ -3117,82 +5570,190 @@ typedef struct { */ /*! @name CR0 - CMP Control Register 0 */ +/*! @{ */ #define CMP_CR0_HYSTCTR_MASK (0x3U) #define CMP_CR0_HYSTCTR_SHIFT (0U) +/*! HYSTCTR - Comparator hard block hysteresis control + * 0b00..Level 0 + * 0b01..Level 1 + * 0b10..Level 2 + * 0b11..Level 3 + */ #define CMP_CR0_HYSTCTR(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR0_HYSTCTR_SHIFT)) & CMP_CR0_HYSTCTR_MASK) #define CMP_CR0_FILTER_CNT_MASK (0x70U) #define CMP_CR0_FILTER_CNT_SHIFT (4U) +/*! FILTER_CNT - Filter Sample Count + * 0b000..Filter is disabled. If SE = 1, then COUT is a logic 0. This is not a legal state, and is not recommended. If SE = 0, COUT = COUTA. + * 0b001..One sample must agree. The comparator output is simply sampled. + * 0b010..2 consecutive samples must agree. + * 0b011..3 consecutive samples must agree. + * 0b100..4 consecutive samples must agree. + * 0b101..5 consecutive samples must agree. + * 0b110..6 consecutive samples must agree. + * 0b111..7 consecutive samples must agree. + */ #define CMP_CR0_FILTER_CNT(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR0_FILTER_CNT_SHIFT)) & CMP_CR0_FILTER_CNT_MASK) +/*! @} */ /*! @name CR1 - CMP Control Register 1 */ +/*! @{ */ #define CMP_CR1_EN_MASK (0x1U) #define CMP_CR1_EN_SHIFT (0U) +/*! EN - Comparator Module Enable + * 0b0..Analog Comparator is disabled. + * 0b1..Analog Comparator is enabled. + */ #define CMP_CR1_EN(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_EN_SHIFT)) & CMP_CR1_EN_MASK) #define CMP_CR1_OPE_MASK (0x2U) #define CMP_CR1_OPE_SHIFT (1U) +/*! OPE - Comparator Output Pin Enable + * 0b0..CMPO is not available on the associated CMPO output pin. If the comparator does not own the pin, this field has no effect. + * 0b1..CMPO is available on the associated CMPO output pin. The comparator output (CMPO) is driven out on the associated CMPO output pin if the comparator owns the pin. If the comparator does not own the field, this bit has no effect. + */ #define CMP_CR1_OPE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_OPE_SHIFT)) & CMP_CR1_OPE_MASK) #define CMP_CR1_COS_MASK (0x4U) #define CMP_CR1_COS_SHIFT (2U) +/*! COS - Comparator Output Select + * 0b0..Set the filtered comparator output (CMPO) to equal COUT. + * 0b1..Set the unfiltered comparator output (CMPO) to equal COUTA. + */ #define CMP_CR1_COS(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_COS_SHIFT)) & CMP_CR1_COS_MASK) #define CMP_CR1_INV_MASK (0x8U) #define CMP_CR1_INV_SHIFT (3U) +/*! INV - Comparator INVERT + * 0b0..Does not invert the comparator output. + * 0b1..Inverts the comparator output. + */ #define CMP_CR1_INV(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_INV_SHIFT)) & CMP_CR1_INV_MASK) #define CMP_CR1_PMODE_MASK (0x10U) #define CMP_CR1_PMODE_SHIFT (4U) +/*! PMODE - Power Mode Select + * 0b0..Low-Speed (LS) Comparison mode selected. In this mode, CMP has slower output propagation delay and lower current consumption. + * 0b1..High-Speed (HS) Comparison mode selected. In this mode, CMP has faster output propagation delay and higher current consumption. + */ #define CMP_CR1_PMODE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_PMODE_SHIFT)) & CMP_CR1_PMODE_MASK) #define CMP_CR1_WE_MASK (0x40U) #define CMP_CR1_WE_SHIFT (6U) +/*! WE - Windowing Enable + * 0b0..Windowing mode is not selected. + * 0b1..Windowing mode is selected. + */ #define CMP_CR1_WE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_WE_SHIFT)) & CMP_CR1_WE_MASK) #define CMP_CR1_SE_MASK (0x80U) #define CMP_CR1_SE_SHIFT (7U) +/*! SE - Sample Enable + * 0b0..Sampling mode is not selected. + * 0b1..Sampling mode is selected. + */ #define CMP_CR1_SE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_SE_SHIFT)) & CMP_CR1_SE_MASK) +/*! @} */ /*! @name FPR - CMP Filter Period Register */ +/*! @{ */ #define CMP_FPR_FILT_PER_MASK (0xFFU) #define CMP_FPR_FILT_PER_SHIFT (0U) #define CMP_FPR_FILT_PER(x) (((uint8_t)(((uint8_t)(x)) << CMP_FPR_FILT_PER_SHIFT)) & CMP_FPR_FILT_PER_MASK) +/*! @} */ /*! @name SCR - CMP Status and Control Register */ +/*! @{ */ #define CMP_SCR_COUT_MASK (0x1U) #define CMP_SCR_COUT_SHIFT (0U) #define CMP_SCR_COUT(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_COUT_SHIFT)) & CMP_SCR_COUT_MASK) #define CMP_SCR_CFF_MASK (0x2U) #define CMP_SCR_CFF_SHIFT (1U) +/*! CFF - Analog Comparator Flag Falling + * 0b0..Falling-edge on COUT has not been detected. + * 0b1..Falling-edge on COUT has occurred. + */ #define CMP_SCR_CFF(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFF_SHIFT)) & CMP_SCR_CFF_MASK) #define CMP_SCR_CFR_MASK (0x4U) #define CMP_SCR_CFR_SHIFT (2U) +/*! CFR - Analog Comparator Flag Rising + * 0b0..Rising-edge on COUT has not been detected. + * 0b1..Rising-edge on COUT has occurred. + */ #define CMP_SCR_CFR(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFR_SHIFT)) & CMP_SCR_CFR_MASK) #define CMP_SCR_IEF_MASK (0x8U) #define CMP_SCR_IEF_SHIFT (3U) +/*! IEF - Comparator Interrupt Enable Falling + * 0b0..Interrupt is disabled. + * 0b1..Interrupt is enabled. + */ #define CMP_SCR_IEF(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_IEF_SHIFT)) & CMP_SCR_IEF_MASK) #define CMP_SCR_IER_MASK (0x10U) #define CMP_SCR_IER_SHIFT (4U) +/*! IER - Comparator Interrupt Enable Rising + * 0b0..Interrupt is disabled. + * 0b1..Interrupt is enabled. + */ #define CMP_SCR_IER(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_IER_SHIFT)) & CMP_SCR_IER_MASK) #define CMP_SCR_DMAEN_MASK (0x40U) #define CMP_SCR_DMAEN_SHIFT (6U) +/*! DMAEN - DMA Enable Control + * 0b0..DMA is disabled. + * 0b1..DMA is enabled. + */ #define CMP_SCR_DMAEN(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_DMAEN_SHIFT)) & CMP_SCR_DMAEN_MASK) +/*! @} */ /*! @name DACCR - DAC Control Register */ +/*! @{ */ #define CMP_DACCR_VOSEL_MASK (0x3FU) #define CMP_DACCR_VOSEL_SHIFT (0U) #define CMP_DACCR_VOSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_VOSEL_SHIFT)) & CMP_DACCR_VOSEL_MASK) #define CMP_DACCR_VRSEL_MASK (0x40U) #define CMP_DACCR_VRSEL_SHIFT (6U) +/*! VRSEL - Supply Voltage Reference Source Select + * 0b0..V is selected as resistor ladder network supply reference V. in1 in + * 0b1..V is selected as resistor ladder network supply reference V. in2 in + */ #define CMP_DACCR_VRSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_VRSEL_SHIFT)) & CMP_DACCR_VRSEL_MASK) #define CMP_DACCR_DACEN_MASK (0x80U) #define CMP_DACCR_DACEN_SHIFT (7U) +/*! DACEN - DAC Enable + * 0b0..DAC is disabled. + * 0b1..DAC is enabled. + */ #define CMP_DACCR_DACEN(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_DACEN_SHIFT)) & CMP_DACCR_DACEN_MASK) +/*! @} */ /*! @name MUXCR - MUX Control Register */ +/*! @{ */ #define CMP_MUXCR_MSEL_MASK (0x7U) #define CMP_MUXCR_MSEL_SHIFT (0U) +/*! MSEL - Minus Input Mux Control + * 0b000..IN0 + * 0b001..IN1 + * 0b010..IN2 + * 0b011..IN3 + * 0b100..IN4 + * 0b101..IN5 + * 0b110..IN6 + * 0b111..IN7 + */ #define CMP_MUXCR_MSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_MSEL_SHIFT)) & CMP_MUXCR_MSEL_MASK) #define CMP_MUXCR_PSEL_MASK (0x38U) #define CMP_MUXCR_PSEL_SHIFT (3U) +/*! PSEL - Plus Input Mux Control + * 0b000..IN0 + * 0b001..IN1 + * 0b010..IN2 + * 0b011..IN3 + * 0b100..IN4 + * 0b101..IN5 + * 0b110..IN6 + * 0b111..IN7 + */ #define CMP_MUXCR_PSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_PSEL_SHIFT)) & CMP_MUXCR_PSEL_MASK) #define CMP_MUXCR_PSTM_MASK (0x80U) #define CMP_MUXCR_PSTM_SHIFT (7U) +/*! PSTM - Pass Through Mode Enable + * 0b0..Pass Through Mode is disabled. + * 0b1..Pass Through Mode is enabled. + */ #define CMP_MUXCR_PSTM(x) (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_PSTM_SHIFT)) & CMP_MUXCR_PSTM_MASK) +/*! @} */ /*! @@ -3260,88 +5821,172 @@ typedef struct { */ /*! @name CGH1 - CMT Carrier Generator High Data Register 1 */ +/*! @{ */ #define CMT_CGH1_PH_MASK (0xFFU) #define CMT_CGH1_PH_SHIFT (0U) #define CMT_CGH1_PH(x) (((uint8_t)(((uint8_t)(x)) << CMT_CGH1_PH_SHIFT)) & CMT_CGH1_PH_MASK) +/*! @} */ /*! @name CGL1 - CMT Carrier Generator Low Data Register 1 */ +/*! @{ */ #define CMT_CGL1_PL_MASK (0xFFU) #define CMT_CGL1_PL_SHIFT (0U) #define CMT_CGL1_PL(x) (((uint8_t)(((uint8_t)(x)) << CMT_CGL1_PL_SHIFT)) & CMT_CGL1_PL_MASK) +/*! @} */ /*! @name CGH2 - CMT Carrier Generator High Data Register 2 */ +/*! @{ */ #define CMT_CGH2_SH_MASK (0xFFU) #define CMT_CGH2_SH_SHIFT (0U) #define CMT_CGH2_SH(x) (((uint8_t)(((uint8_t)(x)) << CMT_CGH2_SH_SHIFT)) & CMT_CGH2_SH_MASK) +/*! @} */ /*! @name CGL2 - CMT Carrier Generator Low Data Register 2 */ +/*! @{ */ #define CMT_CGL2_SL_MASK (0xFFU) #define CMT_CGL2_SL_SHIFT (0U) #define CMT_CGL2_SL(x) (((uint8_t)(((uint8_t)(x)) << CMT_CGL2_SL_SHIFT)) & CMT_CGL2_SL_MASK) +/*! @} */ /*! @name OC - CMT Output Control Register */ +/*! @{ */ #define CMT_OC_IROPEN_MASK (0x20U) #define CMT_OC_IROPEN_SHIFT (5U) +/*! IROPEN - IRO Pin Enable + * 0b0..The IRO signal is disabled. + * 0b1..The IRO signal is enabled as output. + */ #define CMT_OC_IROPEN(x) (((uint8_t)(((uint8_t)(x)) << CMT_OC_IROPEN_SHIFT)) & CMT_OC_IROPEN_MASK) #define CMT_OC_CMTPOL_MASK (0x40U) #define CMT_OC_CMTPOL_SHIFT (6U) +/*! CMTPOL - CMT Output Polarity + * 0b0..The IRO signal is active-low. + * 0b1..The IRO signal is active-high. + */ #define CMT_OC_CMTPOL(x) (((uint8_t)(((uint8_t)(x)) << CMT_OC_CMTPOL_SHIFT)) & CMT_OC_CMTPOL_MASK) #define CMT_OC_IROL_MASK (0x80U) #define CMT_OC_IROL_SHIFT (7U) #define CMT_OC_IROL(x) (((uint8_t)(((uint8_t)(x)) << CMT_OC_IROL_SHIFT)) & CMT_OC_IROL_MASK) +/*! @} */ /*! @name MSC - CMT Modulator Status and Control Register */ +/*! @{ */ #define CMT_MSC_MCGEN_MASK (0x1U) #define CMT_MSC_MCGEN_SHIFT (0U) +/*! MCGEN - Modulator and Carrier Generator Enable + * 0b0..Modulator and carrier generator disabled + * 0b1..Modulator and carrier generator enabled + */ #define CMT_MSC_MCGEN(x) (((uint8_t)(((uint8_t)(x)) << CMT_MSC_MCGEN_SHIFT)) & CMT_MSC_MCGEN_MASK) #define CMT_MSC_EOCIE_MASK (0x2U) #define CMT_MSC_EOCIE_SHIFT (1U) +/*! EOCIE - End of Cycle Interrupt Enable + * 0b0..CPU interrupt is disabled. + * 0b1..CPU interrupt is enabled. + */ #define CMT_MSC_EOCIE(x) (((uint8_t)(((uint8_t)(x)) << CMT_MSC_EOCIE_SHIFT)) & CMT_MSC_EOCIE_MASK) #define CMT_MSC_FSK_MASK (0x4U) #define CMT_MSC_FSK_SHIFT (2U) +/*! FSK - FSK Mode Select + * 0b0..The CMT operates in Time or Baseband mode. + * 0b1..The CMT operates in FSK mode. + */ #define CMT_MSC_FSK(x) (((uint8_t)(((uint8_t)(x)) << CMT_MSC_FSK_SHIFT)) & CMT_MSC_FSK_MASK) #define CMT_MSC_BASE_MASK (0x8U) #define CMT_MSC_BASE_SHIFT (3U) +/*! BASE - Baseband Enable + * 0b0..Baseband mode is disabled. + * 0b1..Baseband mode is enabled. + */ #define CMT_MSC_BASE(x) (((uint8_t)(((uint8_t)(x)) << CMT_MSC_BASE_SHIFT)) & CMT_MSC_BASE_MASK) #define CMT_MSC_EXSPC_MASK (0x10U) #define CMT_MSC_EXSPC_SHIFT (4U) +/*! EXSPC - Extended Space Enable + * 0b0..Extended space is disabled. + * 0b1..Extended space is enabled. + */ #define CMT_MSC_EXSPC(x) (((uint8_t)(((uint8_t)(x)) << CMT_MSC_EXSPC_SHIFT)) & CMT_MSC_EXSPC_MASK) #define CMT_MSC_CMTDIV_MASK (0x60U) #define CMT_MSC_CMTDIV_SHIFT (5U) +/*! CMTDIV - CMT Clock Divide Prescaler + * 0b00..IF * 1 + * 0b01..IF * 2 + * 0b10..IF * 4 + * 0b11..IF * 8 + */ #define CMT_MSC_CMTDIV(x) (((uint8_t)(((uint8_t)(x)) << CMT_MSC_CMTDIV_SHIFT)) & CMT_MSC_CMTDIV_MASK) #define CMT_MSC_EOCF_MASK (0x80U) #define CMT_MSC_EOCF_SHIFT (7U) +/*! EOCF - End Of Cycle Status Flag + * 0b0..End of modulation cycle has not occured since the flag last cleared. + * 0b1..End of modulator cycle has occurred. + */ #define CMT_MSC_EOCF(x) (((uint8_t)(((uint8_t)(x)) << CMT_MSC_EOCF_SHIFT)) & CMT_MSC_EOCF_MASK) +/*! @} */ /*! @name CMD1 - CMT Modulator Data Register Mark High */ +/*! @{ */ #define CMT_CMD1_MB_MASK (0xFFU) #define CMT_CMD1_MB_SHIFT (0U) #define CMT_CMD1_MB(x) (((uint8_t)(((uint8_t)(x)) << CMT_CMD1_MB_SHIFT)) & CMT_CMD1_MB_MASK) +/*! @} */ /*! @name CMD2 - CMT Modulator Data Register Mark Low */ +/*! @{ */ #define CMT_CMD2_MB_MASK (0xFFU) #define CMT_CMD2_MB_SHIFT (0U) #define CMT_CMD2_MB(x) (((uint8_t)(((uint8_t)(x)) << CMT_CMD2_MB_SHIFT)) & CMT_CMD2_MB_MASK) +/*! @} */ /*! @name CMD3 - CMT Modulator Data Register Space High */ +/*! @{ */ #define CMT_CMD3_SB_MASK (0xFFU) #define CMT_CMD3_SB_SHIFT (0U) #define CMT_CMD3_SB(x) (((uint8_t)(((uint8_t)(x)) << CMT_CMD3_SB_SHIFT)) & CMT_CMD3_SB_MASK) +/*! @} */ /*! @name CMD4 - CMT Modulator Data Register Space Low */ +/*! @{ */ #define CMT_CMD4_SB_MASK (0xFFU) #define CMT_CMD4_SB_SHIFT (0U) #define CMT_CMD4_SB(x) (((uint8_t)(((uint8_t)(x)) << CMT_CMD4_SB_SHIFT)) & CMT_CMD4_SB_MASK) +/*! @} */ /*! @name PPS - CMT Primary Prescaler Register */ +/*! @{ */ #define CMT_PPS_PPSDIV_MASK (0xFU) #define CMT_PPS_PPSDIV_SHIFT (0U) +/*! PPSDIV - Primary Prescaler Divider + * 0b0000..Bus clock * 1 + * 0b0001..Bus clock * 2 + * 0b0010..Bus clock * 3 + * 0b0011..Bus clock * 4 + * 0b0100..Bus clock * 5 + * 0b0101..Bus clock * 6 + * 0b0110..Bus clock * 7 + * 0b0111..Bus clock * 8 + * 0b1000..Bus clock * 9 + * 0b1001..Bus clock * 10 + * 0b1010..Bus clock * 11 + * 0b1011..Bus clock * 12 + * 0b1100..Bus clock * 13 + * 0b1101..Bus clock * 14 + * 0b1110..Bus clock * 15 + * 0b1111..Bus clock * 16 + */ #define CMT_PPS_PPSDIV(x) (((uint8_t)(((uint8_t)(x)) << CMT_PPS_PPSDIV_SHIFT)) & CMT_PPS_PPSDIV_MASK) +/*! @} */ /*! @name DMA - CMT Direct Memory Access Register */ +/*! @{ */ #define CMT_DMA_DMA_MASK (0x1U) #define CMT_DMA_DMA_SHIFT (0U) +/*! DMA - DMA Enable + * 0b0..DMA transfer request and done are disabled. + * 0b1..DMA transfer request and done are enabled. + */ #define CMT_DMA_DMA(x) (((uint8_t)(((uint8_t)(x)) << CMT_DMA_DMA_SHIFT)) & CMT_DMA_DMA_MASK) +/*! @} */ /*! @@ -3422,16 +6067,21 @@ typedef struct { */ /*! @name DATAL - CRC_DATAL register. */ +/*! @{ */ #define CRC_DATAL_DATAL_MASK (0xFFFFU) #define CRC_DATAL_DATAL_SHIFT (0U) #define CRC_DATAL_DATAL(x) (((uint16_t)(((uint16_t)(x)) << CRC_DATAL_DATAL_SHIFT)) & CRC_DATAL_DATAL_MASK) +/*! @} */ /*! @name DATAH - CRC_DATAH register. */ +/*! @{ */ #define CRC_DATAH_DATAH_MASK (0xFFFFU) #define CRC_DATAH_DATAH_SHIFT (0U) #define CRC_DATAH_DATAH(x) (((uint16_t)(((uint16_t)(x)) << CRC_DATAH_DATAH_SHIFT)) & CRC_DATAH_DATAH_MASK) +/*! @} */ /*! @name DATA - CRC Data register */ +/*! @{ */ #define CRC_DATA_LL_MASK (0xFFU) #define CRC_DATA_LL_SHIFT (0U) #define CRC_DATA_LL(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_LL_SHIFT)) & CRC_DATA_LL_MASK) @@ -3444,98 +6094,173 @@ typedef struct { #define CRC_DATA_HU_MASK (0xFF000000U) #define CRC_DATA_HU_SHIFT (24U) #define CRC_DATA_HU(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_HU_SHIFT)) & CRC_DATA_HU_MASK) +/*! @} */ /*! @name DATALL - CRC_DATALL register. */ +/*! @{ */ #define CRC_DATALL_DATALL_MASK (0xFFU) #define CRC_DATALL_DATALL_SHIFT (0U) #define CRC_DATALL_DATALL(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATALL_DATALL_SHIFT)) & CRC_DATALL_DATALL_MASK) +/*! @} */ /*! @name DATALU - CRC_DATALU register. */ +/*! @{ */ #define CRC_DATALU_DATALU_MASK (0xFFU) #define CRC_DATALU_DATALU_SHIFT (0U) #define CRC_DATALU_DATALU(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATALU_DATALU_SHIFT)) & CRC_DATALU_DATALU_MASK) +/*! @} */ /*! @name DATAHL - CRC_DATAHL register. */ +/*! @{ */ #define CRC_DATAHL_DATAHL_MASK (0xFFU) #define CRC_DATAHL_DATAHL_SHIFT (0U) #define CRC_DATAHL_DATAHL(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATAHL_DATAHL_SHIFT)) & CRC_DATAHL_DATAHL_MASK) +/*! @} */ /*! @name DATAHU - CRC_DATAHU register. */ +/*! @{ */ #define CRC_DATAHU_DATAHU_MASK (0xFFU) #define CRC_DATAHU_DATAHU_SHIFT (0U) #define CRC_DATAHU_DATAHU(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATAHU_DATAHU_SHIFT)) & CRC_DATAHU_DATAHU_MASK) +/*! @} */ /*! @name GPOLYL - CRC_GPOLYL register. */ +/*! @{ */ #define CRC_GPOLYL_GPOLYL_MASK (0xFFFFU) #define CRC_GPOLYL_GPOLYL_SHIFT (0U) #define CRC_GPOLYL_GPOLYL(x) (((uint16_t)(((uint16_t)(x)) << CRC_GPOLYL_GPOLYL_SHIFT)) & CRC_GPOLYL_GPOLYL_MASK) +/*! @} */ /*! @name GPOLYH - CRC_GPOLYH register. */ +/*! @{ */ #define CRC_GPOLYH_GPOLYH_MASK (0xFFFFU) #define CRC_GPOLYH_GPOLYH_SHIFT (0U) #define CRC_GPOLYH_GPOLYH(x) (((uint16_t)(((uint16_t)(x)) << CRC_GPOLYH_GPOLYH_SHIFT)) & CRC_GPOLYH_GPOLYH_MASK) +/*! @} */ /*! @name GPOLY - CRC Polynomial register */ +/*! @{ */ #define CRC_GPOLY_LOW_MASK (0xFFFFU) #define CRC_GPOLY_LOW_SHIFT (0U) #define CRC_GPOLY_LOW(x) (((uint32_t)(((uint32_t)(x)) << CRC_GPOLY_LOW_SHIFT)) & CRC_GPOLY_LOW_MASK) #define CRC_GPOLY_HIGH_MASK (0xFFFF0000U) #define CRC_GPOLY_HIGH_SHIFT (16U) #define CRC_GPOLY_HIGH(x) (((uint32_t)(((uint32_t)(x)) << CRC_GPOLY_HIGH_SHIFT)) & CRC_GPOLY_HIGH_MASK) +/*! @} */ /*! @name GPOLYLL - CRC_GPOLYLL register. */ +/*! @{ */ #define CRC_GPOLYLL_GPOLYLL_MASK (0xFFU) #define CRC_GPOLYLL_GPOLYLL_SHIFT (0U) #define CRC_GPOLYLL_GPOLYLL(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYLL_GPOLYLL_SHIFT)) & CRC_GPOLYLL_GPOLYLL_MASK) +/*! @} */ /*! @name GPOLYLU - CRC_GPOLYLU register. */ +/*! @{ */ #define CRC_GPOLYLU_GPOLYLU_MASK (0xFFU) #define CRC_GPOLYLU_GPOLYLU_SHIFT (0U) #define CRC_GPOLYLU_GPOLYLU(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYLU_GPOLYLU_SHIFT)) & CRC_GPOLYLU_GPOLYLU_MASK) +/*! @} */ /*! @name GPOLYHL - CRC_GPOLYHL register. */ +/*! @{ */ #define CRC_GPOLYHL_GPOLYHL_MASK (0xFFU) #define CRC_GPOLYHL_GPOLYHL_SHIFT (0U) #define CRC_GPOLYHL_GPOLYHL(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYHL_GPOLYHL_SHIFT)) & CRC_GPOLYHL_GPOLYHL_MASK) +/*! @} */ /*! @name GPOLYHU - CRC_GPOLYHU register. */ +/*! @{ */ #define CRC_GPOLYHU_GPOLYHU_MASK (0xFFU) #define CRC_GPOLYHU_GPOLYHU_SHIFT (0U) #define CRC_GPOLYHU_GPOLYHU(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYHU_GPOLYHU_SHIFT)) & CRC_GPOLYHU_GPOLYHU_MASK) +/*! @} */ /*! @name CTRL - CRC Control register */ +/*! @{ */ #define CRC_CTRL_TCRC_MASK (0x1000000U) #define CRC_CTRL_TCRC_SHIFT (24U) +/*! TCRC + * 0b0..16-bit CRC protocol. + * 0b1..32-bit CRC protocol. + */ #define CRC_CTRL_TCRC(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TCRC_SHIFT)) & CRC_CTRL_TCRC_MASK) #define CRC_CTRL_WAS_MASK (0x2000000U) #define CRC_CTRL_WAS_SHIFT (25U) +/*! WAS - Write CRC Data Register As Seed + * 0b0..Writes to the CRC data register are data values. + * 0b1..Writes to the CRC data register are seed values. + */ #define CRC_CTRL_WAS(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_WAS_SHIFT)) & CRC_CTRL_WAS_MASK) #define CRC_CTRL_FXOR_MASK (0x4000000U) #define CRC_CTRL_FXOR_SHIFT (26U) +/*! FXOR - Complement Read Of CRC Data Register + * 0b0..No XOR on reading. + * 0b1..Invert or complement the read value of the CRC Data register. + */ #define CRC_CTRL_FXOR(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_FXOR_SHIFT)) & CRC_CTRL_FXOR_MASK) #define CRC_CTRL_TOTR_MASK (0x30000000U) #define CRC_CTRL_TOTR_SHIFT (28U) +/*! TOTR - Type Of Transpose For Read + * 0b00..No transposition. + * 0b01..Bits in bytes are transposed; bytes are not transposed. + * 0b10..Both bits in bytes and bytes are transposed. + * 0b11..Only bytes are transposed; no bits in a byte are transposed. + */ #define CRC_CTRL_TOTR(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TOTR_SHIFT)) & CRC_CTRL_TOTR_MASK) #define CRC_CTRL_TOT_MASK (0xC0000000U) #define CRC_CTRL_TOT_SHIFT (30U) +/*! TOT - Type Of Transpose For Writes + * 0b00..No transposition. + * 0b01..Bits in bytes are transposed; bytes are not transposed. + * 0b10..Both bits in bytes and bytes are transposed. + * 0b11..Only bytes are transposed; no bits in a byte are transposed. + */ #define CRC_CTRL_TOT(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TOT_SHIFT)) & CRC_CTRL_TOT_MASK) +/*! @} */ /*! @name CTRLHU - CRC_CTRLHU register. */ +/*! @{ */ #define CRC_CTRLHU_TCRC_MASK (0x1U) #define CRC_CTRLHU_TCRC_SHIFT (0U) +/*! TCRC + * 0b0..16-bit CRC protocol. + * 0b1..32-bit CRC protocol. + */ #define CRC_CTRLHU_TCRC(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TCRC_SHIFT)) & CRC_CTRLHU_TCRC_MASK) #define CRC_CTRLHU_WAS_MASK (0x2U) #define CRC_CTRLHU_WAS_SHIFT (1U) +/*! WAS + * 0b0..Writes to CRC data register are data values. + * 0b1..Writes to CRC data reguster are seed values. + */ #define CRC_CTRLHU_WAS(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_WAS_SHIFT)) & CRC_CTRLHU_WAS_MASK) #define CRC_CTRLHU_FXOR_MASK (0x4U) #define CRC_CTRLHU_FXOR_SHIFT (2U) +/*! FXOR + * 0b0..No XOR on reading. + * 0b1..Invert or complement the read value of CRC data register. + */ #define CRC_CTRLHU_FXOR(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_FXOR_SHIFT)) & CRC_CTRLHU_FXOR_MASK) #define CRC_CTRLHU_TOTR_MASK (0x30U) #define CRC_CTRLHU_TOTR_SHIFT (4U) +/*! TOTR + * 0b00..No Transposition. + * 0b01..Bits in bytes are transposed, bytes are not transposed. + * 0b10..Both bits in bytes and bytes are transposed. + * 0b11..Only bytes are transposed; no bits in a byte are transposed. + */ #define CRC_CTRLHU_TOTR(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TOTR_SHIFT)) & CRC_CTRLHU_TOTR_MASK) #define CRC_CTRLHU_TOT_MASK (0xC0U) #define CRC_CTRLHU_TOT_SHIFT (6U) +/*! TOT + * 0b00..No Transposition. + * 0b01..Bits in bytes are transposed, bytes are not transposed. + * 0b10..Both bits in bytes and bytes are transposed. + * 0b11..Only bytes are transposed; no bits in a byte are transposed. + */ #define CRC_CTRLHU_TOT(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TOT_SHIFT)) & CRC_CTRLHU_TOT_MASK) +/*! @} */ /*! @@ -3589,79 +6314,155 @@ typedef struct { */ /*! @name DATL - DAC Data Low Register */ +/*! @{ */ #define DAC_DATL_DATA0_MASK (0xFFU) #define DAC_DATL_DATA0_SHIFT (0U) #define DAC_DATL_DATA0(x) (((uint8_t)(((uint8_t)(x)) << DAC_DATL_DATA0_SHIFT)) & DAC_DATL_DATA0_MASK) +/*! @} */ /* The count of DAC_DATL */ #define DAC_DATL_COUNT (16U) /*! @name DATH - DAC Data High Register */ +/*! @{ */ #define DAC_DATH_DATA1_MASK (0xFU) #define DAC_DATH_DATA1_SHIFT (0U) #define DAC_DATH_DATA1(x) (((uint8_t)(((uint8_t)(x)) << DAC_DATH_DATA1_SHIFT)) & DAC_DATH_DATA1_MASK) +/*! @} */ /* The count of DAC_DATH */ #define DAC_DATH_COUNT (16U) /*! @name SR - DAC Status Register */ +/*! @{ */ #define DAC_SR_DACBFRPBF_MASK (0x1U) #define DAC_SR_DACBFRPBF_SHIFT (0U) +/*! DACBFRPBF - DAC Buffer Read Pointer Bottom Position Flag + * 0b0..The DAC buffer read pointer is not equal to C2[DACBFUP]. + * 0b1..The DAC buffer read pointer is equal to C2[DACBFUP]. + */ #define DAC_SR_DACBFRPBF(x) (((uint8_t)(((uint8_t)(x)) << DAC_SR_DACBFRPBF_SHIFT)) & DAC_SR_DACBFRPBF_MASK) #define DAC_SR_DACBFRPTF_MASK (0x2U) #define DAC_SR_DACBFRPTF_SHIFT (1U) +/*! DACBFRPTF - DAC Buffer Read Pointer Top Position Flag + * 0b0..The DAC buffer read pointer is not zero. + * 0b1..The DAC buffer read pointer is zero. + */ #define DAC_SR_DACBFRPTF(x) (((uint8_t)(((uint8_t)(x)) << DAC_SR_DACBFRPTF_SHIFT)) & DAC_SR_DACBFRPTF_MASK) #define DAC_SR_DACBFWMF_MASK (0x4U) #define DAC_SR_DACBFWMF_SHIFT (2U) +/*! DACBFWMF - DAC Buffer Watermark Flag + * 0b0..The DAC buffer read pointer has not reached the watermark level. + * 0b1..The DAC buffer read pointer has reached the watermark level. + */ #define DAC_SR_DACBFWMF(x) (((uint8_t)(((uint8_t)(x)) << DAC_SR_DACBFWMF_SHIFT)) & DAC_SR_DACBFWMF_MASK) +/*! @} */ /*! @name C0 - DAC Control Register */ +/*! @{ */ #define DAC_C0_DACBBIEN_MASK (0x1U) #define DAC_C0_DACBBIEN_SHIFT (0U) +/*! DACBBIEN - DAC Buffer Read Pointer Bottom Flag Interrupt Enable + * 0b0..The DAC buffer read pointer bottom flag interrupt is disabled. + * 0b1..The DAC buffer read pointer bottom flag interrupt is enabled. + */ #define DAC_C0_DACBBIEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACBBIEN_SHIFT)) & DAC_C0_DACBBIEN_MASK) #define DAC_C0_DACBTIEN_MASK (0x2U) #define DAC_C0_DACBTIEN_SHIFT (1U) +/*! DACBTIEN - DAC Buffer Read Pointer Top Flag Interrupt Enable + * 0b0..The DAC buffer read pointer top flag interrupt is disabled. + * 0b1..The DAC buffer read pointer top flag interrupt is enabled. + */ #define DAC_C0_DACBTIEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACBTIEN_SHIFT)) & DAC_C0_DACBTIEN_MASK) #define DAC_C0_DACBWIEN_MASK (0x4U) #define DAC_C0_DACBWIEN_SHIFT (2U) +/*! DACBWIEN - DAC Buffer Watermark Interrupt Enable + * 0b0..The DAC buffer watermark interrupt is disabled. + * 0b1..The DAC buffer watermark interrupt is enabled. + */ #define DAC_C0_DACBWIEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACBWIEN_SHIFT)) & DAC_C0_DACBWIEN_MASK) #define DAC_C0_LPEN_MASK (0x8U) #define DAC_C0_LPEN_SHIFT (3U) +/*! LPEN - DAC Low Power Control + * 0b0..High-Power mode + * 0b1..Low-Power mode + */ #define DAC_C0_LPEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_LPEN_SHIFT)) & DAC_C0_LPEN_MASK) #define DAC_C0_DACSWTRG_MASK (0x10U) #define DAC_C0_DACSWTRG_SHIFT (4U) +/*! DACSWTRG - DAC Software Trigger + * 0b0..The DAC soft trigger is not valid. + * 0b1..The DAC soft trigger is valid. + */ #define DAC_C0_DACSWTRG(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACSWTRG_SHIFT)) & DAC_C0_DACSWTRG_MASK) #define DAC_C0_DACTRGSEL_MASK (0x20U) #define DAC_C0_DACTRGSEL_SHIFT (5U) +/*! DACTRGSEL - DAC Trigger Select + * 0b0..The DAC hardware trigger is selected. + * 0b1..The DAC software trigger is selected. + */ #define DAC_C0_DACTRGSEL(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACTRGSEL_SHIFT)) & DAC_C0_DACTRGSEL_MASK) #define DAC_C0_DACRFS_MASK (0x40U) #define DAC_C0_DACRFS_SHIFT (6U) +/*! DACRFS - DAC Reference Select + * 0b0..The DAC selects DACREF_1 as the reference voltage. + * 0b1..The DAC selects DACREF_2 as the reference voltage. + */ #define DAC_C0_DACRFS(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACRFS_SHIFT)) & DAC_C0_DACRFS_MASK) #define DAC_C0_DACEN_MASK (0x80U) #define DAC_C0_DACEN_SHIFT (7U) +/*! DACEN - DAC Enable + * 0b0..The DAC system is disabled. + * 0b1..The DAC system is enabled. + */ #define DAC_C0_DACEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACEN_SHIFT)) & DAC_C0_DACEN_MASK) +/*! @} */ /*! @name C1 - DAC Control Register 1 */ +/*! @{ */ #define DAC_C1_DACBFEN_MASK (0x1U) #define DAC_C1_DACBFEN_SHIFT (0U) +/*! DACBFEN - DAC Buffer Enable + * 0b0..Buffer read pointer is disabled. The converted data is always the first word of the buffer. + * 0b1..Buffer read pointer is enabled. The converted data is the word that the read pointer points to. It means converted data can be from any word of the buffer. + */ #define DAC_C1_DACBFEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C1_DACBFEN_SHIFT)) & DAC_C1_DACBFEN_MASK) #define DAC_C1_DACBFMD_MASK (0x6U) #define DAC_C1_DACBFMD_SHIFT (1U) +/*! DACBFMD - DAC Buffer Work Mode Select + * 0b00..Normal mode + * 0b01..Swing mode + * 0b10..One-Time Scan mode + * 0b11..Reserved + */ #define DAC_C1_DACBFMD(x) (((uint8_t)(((uint8_t)(x)) << DAC_C1_DACBFMD_SHIFT)) & DAC_C1_DACBFMD_MASK) #define DAC_C1_DACBFWM_MASK (0x18U) #define DAC_C1_DACBFWM_SHIFT (3U) +/*! DACBFWM - DAC Buffer Watermark Select + * 0b00..1 word + * 0b01..2 words + * 0b10..3 words + * 0b11..4 words + */ #define DAC_C1_DACBFWM(x) (((uint8_t)(((uint8_t)(x)) << DAC_C1_DACBFWM_SHIFT)) & DAC_C1_DACBFWM_MASK) #define DAC_C1_DMAEN_MASK (0x80U) #define DAC_C1_DMAEN_SHIFT (7U) +/*! DMAEN - DMA Enable Select + * 0b0..DMA is disabled. + * 0b1..DMA is enabled. When DMA is enabled, the DMA request will be generated by original interrupts. The interrupts will not be presented on this module at the same time. + */ #define DAC_C1_DMAEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C1_DMAEN_SHIFT)) & DAC_C1_DMAEN_MASK) +/*! @} */ /*! @name C2 - DAC Control Register 2 */ +/*! @{ */ #define DAC_C2_DACBFUP_MASK (0xFU) #define DAC_C2_DACBFUP_SHIFT (0U) #define DAC_C2_DACBFUP(x) (((uint8_t)(((uint8_t)(x)) << DAC_C2_DACBFUP_SHIFT)) & DAC_C2_DACBFUP_MASK) #define DAC_C2_DACBFRP_MASK (0xF0U) #define DAC_C2_DACBFRP_SHIFT (4U) #define DAC_C2_DACBFRP(x) (((uint8_t)(((uint8_t)(x)) << DAC_C2_DACBFRP_SHIFT)) & DAC_C2_DACBFRP_MASK) +/*! @} */ /*! @@ -3774,600 +6575,1255 @@ typedef struct { */ /*! @name CR - Control Register */ +/*! @{ */ #define DMA_CR_EDBG_MASK (0x2U) #define DMA_CR_EDBG_SHIFT (1U) +/*! EDBG - Enable Debug + * 0b0..When in debug mode, the DMA continues to operate. + * 0b1..When in debug mode, the DMA stalls the start of a new channel. Executing channels are allowed to complete. Channel execution resumes when the system exits debug mode or the EDBG bit is cleared. + */ #define DMA_CR_EDBG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_EDBG_SHIFT)) & DMA_CR_EDBG_MASK) #define DMA_CR_ERCA_MASK (0x4U) #define DMA_CR_ERCA_SHIFT (2U) +/*! ERCA - Enable Round Robin Channel Arbitration + * 0b0..Fixed priority arbitration is used for channel selection . + * 0b1..Round robin arbitration is used for channel selection . + */ #define DMA_CR_ERCA(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ERCA_SHIFT)) & DMA_CR_ERCA_MASK) #define DMA_CR_HOE_MASK (0x10U) #define DMA_CR_HOE_SHIFT (4U) +/*! HOE - Halt On Error + * 0b0..Normal operation + * 0b1..Any error causes the HALT bit to set. Subsequently, all service requests are ignored until the HALT bit is cleared. + */ #define DMA_CR_HOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_HOE_SHIFT)) & DMA_CR_HOE_MASK) #define DMA_CR_HALT_MASK (0x20U) #define DMA_CR_HALT_SHIFT (5U) +/*! HALT - Halt DMA Operations + * 0b0..Normal operation + * 0b1..Stall the start of any new channels. Executing channels are allowed to complete. Channel execution resumes when this bit is cleared. + */ #define DMA_CR_HALT(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_HALT_SHIFT)) & DMA_CR_HALT_MASK) #define DMA_CR_CLM_MASK (0x40U) #define DMA_CR_CLM_SHIFT (6U) +/*! CLM - Continuous Link Mode + * 0b0..A minor loop channel link made to itself goes through channel arbitration before being activated again. + * 0b1..A minor loop channel link made to itself does not go through channel arbitration before being activated again. Upon minor loop completion, the channel activates again if that channel has a minor loop channel link enabled and the link channel is itself. This effectively applies the minor loop offsets and restarts the next minor loop. + */ #define DMA_CR_CLM(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_CLM_SHIFT)) & DMA_CR_CLM_MASK) #define DMA_CR_EMLM_MASK (0x80U) #define DMA_CR_EMLM_SHIFT (7U) +/*! EMLM - Enable Minor Loop Mapping + * 0b0..Disabled. TCDn.word2 is defined as a 32-bit NBYTES field. + * 0b1..Enabled. TCDn.word2 is redefined to include individual enable fields, an offset field, and the NBYTES field. The individual enable fields allow the minor loop offset to be applied to the source address, the destination address, or both. The NBYTES field is reduced when either offset is enabled. + */ #define DMA_CR_EMLM(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_EMLM_SHIFT)) & DMA_CR_EMLM_MASK) #define DMA_CR_ECX_MASK (0x10000U) #define DMA_CR_ECX_SHIFT (16U) +/*! ECX - Error Cancel Transfer + * 0b0..Normal operation + * 0b1..Cancel the remaining data transfer in the same fashion as the CX bit. Stop the executing channel and force the minor loop to finish. The cancel takes effect after the last write of the current read/write sequence. The ECX bit clears itself after the cancel is honored. In addition to cancelling the transfer, ECX treats the cancel as an error condition, thus updating the Error Status register (DMAx_ES) and generating an optional error interrupt. + */ #define DMA_CR_ECX(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ECX_SHIFT)) & DMA_CR_ECX_MASK) #define DMA_CR_CX_MASK (0x20000U) #define DMA_CR_CX_SHIFT (17U) +/*! CX - Cancel Transfer + * 0b0..Normal operation + * 0b1..Cancel the remaining data transfer. Stop the executing channel and force the minor loop to finish. The cancel takes effect after the last write of the current read/write sequence. The CX bit clears itself after the cancel has been honored. This cancel retires the channel normally as if the minor loop was completed. + */ #define DMA_CR_CX(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_CX_SHIFT)) & DMA_CR_CX_MASK) +/*! @} */ /*! @name ES - Error Status Register */ +/*! @{ */ #define DMA_ES_DBE_MASK (0x1U) #define DMA_ES_DBE_SHIFT (0U) +/*! DBE - Destination Bus Error + * 0b0..No destination bus error + * 0b1..The last recorded error was a bus error on a destination write + */ #define DMA_ES_DBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DBE_SHIFT)) & DMA_ES_DBE_MASK) #define DMA_ES_SBE_MASK (0x2U) #define DMA_ES_SBE_SHIFT (1U) +/*! SBE - Source Bus Error + * 0b0..No source bus error + * 0b1..The last recorded error was a bus error on a source read + */ #define DMA_ES_SBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SBE_SHIFT)) & DMA_ES_SBE_MASK) #define DMA_ES_SGE_MASK (0x4U) #define DMA_ES_SGE_SHIFT (2U) +/*! SGE - Scatter/Gather Configuration Error + * 0b0..No scatter/gather configuration error + * 0b1..The last recorded error was a configuration error detected in the TCDn_DLASTSGA field. This field is checked at the beginning of a scatter/gather operation after major loop completion if TCDn_CSR[ESG] is enabled. TCDn_DLASTSGA is not on a 32 byte boundary. + */ #define DMA_ES_SGE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SGE_SHIFT)) & DMA_ES_SGE_MASK) #define DMA_ES_NCE_MASK (0x8U) #define DMA_ES_NCE_SHIFT (3U) +/*! NCE - NBYTES/CITER Configuration Error + * 0b0..No NBYTES/CITER configuration error + * 0b1..The last recorded error was a configuration error detected in the TCDn_NBYTES or TCDn_CITER fields. TCDn_NBYTES is not a multiple of TCDn_ATTR[SSIZE] and TCDn_ATTR[DSIZE], or TCDn_CITER[CITER] is equal to zero, or TCDn_CITER[ELINK] is not equal to TCDn_BITER[ELINK] + */ #define DMA_ES_NCE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_NCE_SHIFT)) & DMA_ES_NCE_MASK) #define DMA_ES_DOE_MASK (0x10U) #define DMA_ES_DOE_SHIFT (4U) +/*! DOE - Destination Offset Error + * 0b0..No destination offset configuration error + * 0b1..The last recorded error was a configuration error detected in the TCDn_DOFF field. TCDn_DOFF is inconsistent with TCDn_ATTR[DSIZE]. + */ #define DMA_ES_DOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DOE_SHIFT)) & DMA_ES_DOE_MASK) #define DMA_ES_DAE_MASK (0x20U) #define DMA_ES_DAE_SHIFT (5U) +/*! DAE - Destination Address Error + * 0b0..No destination address configuration error + * 0b1..The last recorded error was a configuration error detected in the TCDn_DADDR field. TCDn_DADDR is inconsistent with TCDn_ATTR[DSIZE]. + */ #define DMA_ES_DAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DAE_SHIFT)) & DMA_ES_DAE_MASK) #define DMA_ES_SOE_MASK (0x40U) #define DMA_ES_SOE_SHIFT (6U) +/*! SOE - Source Offset Error + * 0b0..No source offset configuration error + * 0b1..The last recorded error was a configuration error detected in the TCDn_SOFF field. TCDn_SOFF is inconsistent with TCDn_ATTR[SSIZE]. + */ #define DMA_ES_SOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SOE_SHIFT)) & DMA_ES_SOE_MASK) #define DMA_ES_SAE_MASK (0x80U) #define DMA_ES_SAE_SHIFT (7U) +/*! SAE - Source Address Error + * 0b0..No source address configuration error. + * 0b1..The last recorded error was a configuration error detected in the TCDn_SADDR field. TCDn_SADDR is inconsistent with TCDn_ATTR[SSIZE]. + */ #define DMA_ES_SAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SAE_SHIFT)) & DMA_ES_SAE_MASK) #define DMA_ES_ERRCHN_MASK (0xF00U) #define DMA_ES_ERRCHN_SHIFT (8U) #define DMA_ES_ERRCHN(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_ERRCHN_SHIFT)) & DMA_ES_ERRCHN_MASK) #define DMA_ES_CPE_MASK (0x4000U) #define DMA_ES_CPE_SHIFT (14U) +/*! CPE - Channel Priority Error + * 0b0..No channel priority error + * 0b1..The last recorded error was a configuration error in the channel priorities . Channel priorities are not unique. + */ #define DMA_ES_CPE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_CPE_SHIFT)) & DMA_ES_CPE_MASK) #define DMA_ES_ECX_MASK (0x10000U) #define DMA_ES_ECX_SHIFT (16U) +/*! ECX - Transfer Canceled + * 0b0..No canceled transfers + * 0b1..The last recorded entry was a canceled transfer by the error cancel transfer input + */ #define DMA_ES_ECX(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_ECX_SHIFT)) & DMA_ES_ECX_MASK) #define DMA_ES_VLD_MASK (0x80000000U) #define DMA_ES_VLD_SHIFT (31U) +/*! VLD + * 0b0..No ERR bits are set + * 0b1..At least one ERR bit is set indicating a valid error exists that has not been cleared + */ #define DMA_ES_VLD(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_VLD_SHIFT)) & DMA_ES_VLD_MASK) +/*! @} */ /*! @name ERQ - Enable Request Register */ +/*! @{ */ #define DMA_ERQ_ERQ0_MASK (0x1U) #define DMA_ERQ_ERQ0_SHIFT (0U) +/*! ERQ0 - Enable DMA Request 0 + * 0b0..The DMA request signal for the corresponding channel is disabled + * 0b1..The DMA request signal for the corresponding channel is enabled + */ #define DMA_ERQ_ERQ0(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ0_SHIFT)) & DMA_ERQ_ERQ0_MASK) #define DMA_ERQ_ERQ1_MASK (0x2U) #define DMA_ERQ_ERQ1_SHIFT (1U) +/*! ERQ1 - Enable DMA Request 1 + * 0b0..The DMA request signal for the corresponding channel is disabled + * 0b1..The DMA request signal for the corresponding channel is enabled + */ #define DMA_ERQ_ERQ1(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ1_SHIFT)) & DMA_ERQ_ERQ1_MASK) #define DMA_ERQ_ERQ2_MASK (0x4U) #define DMA_ERQ_ERQ2_SHIFT (2U) +/*! ERQ2 - Enable DMA Request 2 + * 0b0..The DMA request signal for the corresponding channel is disabled + * 0b1..The DMA request signal for the corresponding channel is enabled + */ #define DMA_ERQ_ERQ2(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ2_SHIFT)) & DMA_ERQ_ERQ2_MASK) #define DMA_ERQ_ERQ3_MASK (0x8U) #define DMA_ERQ_ERQ3_SHIFT (3U) +/*! ERQ3 - Enable DMA Request 3 + * 0b0..The DMA request signal for the corresponding channel is disabled + * 0b1..The DMA request signal for the corresponding channel is enabled + */ #define DMA_ERQ_ERQ3(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ3_SHIFT)) & DMA_ERQ_ERQ3_MASK) #define DMA_ERQ_ERQ4_MASK (0x10U) #define DMA_ERQ_ERQ4_SHIFT (4U) +/*! ERQ4 - Enable DMA Request 4 + * 0b0..The DMA request signal for the corresponding channel is disabled + * 0b1..The DMA request signal for the corresponding channel is enabled + */ #define DMA_ERQ_ERQ4(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ4_SHIFT)) & DMA_ERQ_ERQ4_MASK) #define DMA_ERQ_ERQ5_MASK (0x20U) #define DMA_ERQ_ERQ5_SHIFT (5U) +/*! ERQ5 - Enable DMA Request 5 + * 0b0..The DMA request signal for the corresponding channel is disabled + * 0b1..The DMA request signal for the corresponding channel is enabled + */ #define DMA_ERQ_ERQ5(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ5_SHIFT)) & DMA_ERQ_ERQ5_MASK) #define DMA_ERQ_ERQ6_MASK (0x40U) #define DMA_ERQ_ERQ6_SHIFT (6U) +/*! ERQ6 - Enable DMA Request 6 + * 0b0..The DMA request signal for the corresponding channel is disabled + * 0b1..The DMA request signal for the corresponding channel is enabled + */ #define DMA_ERQ_ERQ6(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ6_SHIFT)) & DMA_ERQ_ERQ6_MASK) #define DMA_ERQ_ERQ7_MASK (0x80U) #define DMA_ERQ_ERQ7_SHIFT (7U) +/*! ERQ7 - Enable DMA Request 7 + * 0b0..The DMA request signal for the corresponding channel is disabled + * 0b1..The DMA request signal for the corresponding channel is enabled + */ #define DMA_ERQ_ERQ7(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ7_SHIFT)) & DMA_ERQ_ERQ7_MASK) #define DMA_ERQ_ERQ8_MASK (0x100U) #define DMA_ERQ_ERQ8_SHIFT (8U) +/*! ERQ8 - Enable DMA Request 8 + * 0b0..The DMA request signal for the corresponding channel is disabled + * 0b1..The DMA request signal for the corresponding channel is enabled + */ #define DMA_ERQ_ERQ8(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ8_SHIFT)) & DMA_ERQ_ERQ8_MASK) #define DMA_ERQ_ERQ9_MASK (0x200U) #define DMA_ERQ_ERQ9_SHIFT (9U) +/*! ERQ9 - Enable DMA Request 9 + * 0b0..The DMA request signal for the corresponding channel is disabled + * 0b1..The DMA request signal for the corresponding channel is enabled + */ #define DMA_ERQ_ERQ9(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ9_SHIFT)) & DMA_ERQ_ERQ9_MASK) #define DMA_ERQ_ERQ10_MASK (0x400U) #define DMA_ERQ_ERQ10_SHIFT (10U) +/*! ERQ10 - Enable DMA Request 10 + * 0b0..The DMA request signal for the corresponding channel is disabled + * 0b1..The DMA request signal for the corresponding channel is enabled + */ #define DMA_ERQ_ERQ10(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ10_SHIFT)) & DMA_ERQ_ERQ10_MASK) #define DMA_ERQ_ERQ11_MASK (0x800U) #define DMA_ERQ_ERQ11_SHIFT (11U) +/*! ERQ11 - Enable DMA Request 11 + * 0b0..The DMA request signal for the corresponding channel is disabled + * 0b1..The DMA request signal for the corresponding channel is enabled + */ #define DMA_ERQ_ERQ11(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ11_SHIFT)) & DMA_ERQ_ERQ11_MASK) #define DMA_ERQ_ERQ12_MASK (0x1000U) #define DMA_ERQ_ERQ12_SHIFT (12U) +/*! ERQ12 - Enable DMA Request 12 + * 0b0..The DMA request signal for the corresponding channel is disabled + * 0b1..The DMA request signal for the corresponding channel is enabled + */ #define DMA_ERQ_ERQ12(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ12_SHIFT)) & DMA_ERQ_ERQ12_MASK) #define DMA_ERQ_ERQ13_MASK (0x2000U) #define DMA_ERQ_ERQ13_SHIFT (13U) +/*! ERQ13 - Enable DMA Request 13 + * 0b0..The DMA request signal for the corresponding channel is disabled + * 0b1..The DMA request signal for the corresponding channel is enabled + */ #define DMA_ERQ_ERQ13(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ13_SHIFT)) & DMA_ERQ_ERQ13_MASK) #define DMA_ERQ_ERQ14_MASK (0x4000U) #define DMA_ERQ_ERQ14_SHIFT (14U) +/*! ERQ14 - Enable DMA Request 14 + * 0b0..The DMA request signal for the corresponding channel is disabled + * 0b1..The DMA request signal for the corresponding channel is enabled + */ #define DMA_ERQ_ERQ14(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ14_SHIFT)) & DMA_ERQ_ERQ14_MASK) #define DMA_ERQ_ERQ15_MASK (0x8000U) #define DMA_ERQ_ERQ15_SHIFT (15U) +/*! ERQ15 - Enable DMA Request 15 + * 0b0..The DMA request signal for the corresponding channel is disabled + * 0b1..The DMA request signal for the corresponding channel is enabled + */ #define DMA_ERQ_ERQ15(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ15_SHIFT)) & DMA_ERQ_ERQ15_MASK) +/*! @} */ /*! @name EEI - Enable Error Interrupt Register */ +/*! @{ */ #define DMA_EEI_EEI0_MASK (0x1U) #define DMA_EEI_EEI0_SHIFT (0U) +/*! EEI0 - Enable Error Interrupt 0 + * 0b0..The error signal for corresponding channel does not generate an error interrupt + * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request + */ #define DMA_EEI_EEI0(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI0_SHIFT)) & DMA_EEI_EEI0_MASK) #define DMA_EEI_EEI1_MASK (0x2U) #define DMA_EEI_EEI1_SHIFT (1U) +/*! EEI1 - Enable Error Interrupt 1 + * 0b0..The error signal for corresponding channel does not generate an error interrupt + * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request + */ #define DMA_EEI_EEI1(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI1_SHIFT)) & DMA_EEI_EEI1_MASK) #define DMA_EEI_EEI2_MASK (0x4U) #define DMA_EEI_EEI2_SHIFT (2U) +/*! EEI2 - Enable Error Interrupt 2 + * 0b0..The error signal for corresponding channel does not generate an error interrupt + * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request + */ #define DMA_EEI_EEI2(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI2_SHIFT)) & DMA_EEI_EEI2_MASK) #define DMA_EEI_EEI3_MASK (0x8U) #define DMA_EEI_EEI3_SHIFT (3U) +/*! EEI3 - Enable Error Interrupt 3 + * 0b0..The error signal for corresponding channel does not generate an error interrupt + * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request + */ #define DMA_EEI_EEI3(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI3_SHIFT)) & DMA_EEI_EEI3_MASK) #define DMA_EEI_EEI4_MASK (0x10U) #define DMA_EEI_EEI4_SHIFT (4U) +/*! EEI4 - Enable Error Interrupt 4 + * 0b0..The error signal for corresponding channel does not generate an error interrupt + * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request + */ #define DMA_EEI_EEI4(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI4_SHIFT)) & DMA_EEI_EEI4_MASK) #define DMA_EEI_EEI5_MASK (0x20U) #define DMA_EEI_EEI5_SHIFT (5U) +/*! EEI5 - Enable Error Interrupt 5 + * 0b0..The error signal for corresponding channel does not generate an error interrupt + * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request + */ #define DMA_EEI_EEI5(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI5_SHIFT)) & DMA_EEI_EEI5_MASK) #define DMA_EEI_EEI6_MASK (0x40U) #define DMA_EEI_EEI6_SHIFT (6U) +/*! EEI6 - Enable Error Interrupt 6 + * 0b0..The error signal for corresponding channel does not generate an error interrupt + * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request + */ #define DMA_EEI_EEI6(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI6_SHIFT)) & DMA_EEI_EEI6_MASK) #define DMA_EEI_EEI7_MASK (0x80U) #define DMA_EEI_EEI7_SHIFT (7U) +/*! EEI7 - Enable Error Interrupt 7 + * 0b0..The error signal for corresponding channel does not generate an error interrupt + * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request + */ #define DMA_EEI_EEI7(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI7_SHIFT)) & DMA_EEI_EEI7_MASK) #define DMA_EEI_EEI8_MASK (0x100U) #define DMA_EEI_EEI8_SHIFT (8U) +/*! EEI8 - Enable Error Interrupt 8 + * 0b0..The error signal for corresponding channel does not generate an error interrupt + * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request + */ #define DMA_EEI_EEI8(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI8_SHIFT)) & DMA_EEI_EEI8_MASK) #define DMA_EEI_EEI9_MASK (0x200U) #define DMA_EEI_EEI9_SHIFT (9U) +/*! EEI9 - Enable Error Interrupt 9 + * 0b0..The error signal for corresponding channel does not generate an error interrupt + * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request + */ #define DMA_EEI_EEI9(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI9_SHIFT)) & DMA_EEI_EEI9_MASK) #define DMA_EEI_EEI10_MASK (0x400U) #define DMA_EEI_EEI10_SHIFT (10U) +/*! EEI10 - Enable Error Interrupt 10 + * 0b0..The error signal for corresponding channel does not generate an error interrupt + * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request + */ #define DMA_EEI_EEI10(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI10_SHIFT)) & DMA_EEI_EEI10_MASK) #define DMA_EEI_EEI11_MASK (0x800U) #define DMA_EEI_EEI11_SHIFT (11U) +/*! EEI11 - Enable Error Interrupt 11 + * 0b0..The error signal for corresponding channel does not generate an error interrupt + * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request + */ #define DMA_EEI_EEI11(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI11_SHIFT)) & DMA_EEI_EEI11_MASK) #define DMA_EEI_EEI12_MASK (0x1000U) #define DMA_EEI_EEI12_SHIFT (12U) +/*! EEI12 - Enable Error Interrupt 12 + * 0b0..The error signal for corresponding channel does not generate an error interrupt + * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request + */ #define DMA_EEI_EEI12(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI12_SHIFT)) & DMA_EEI_EEI12_MASK) #define DMA_EEI_EEI13_MASK (0x2000U) #define DMA_EEI_EEI13_SHIFT (13U) +/*! EEI13 - Enable Error Interrupt 13 + * 0b0..The error signal for corresponding channel does not generate an error interrupt + * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request + */ #define DMA_EEI_EEI13(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI13_SHIFT)) & DMA_EEI_EEI13_MASK) #define DMA_EEI_EEI14_MASK (0x4000U) #define DMA_EEI_EEI14_SHIFT (14U) +/*! EEI14 - Enable Error Interrupt 14 + * 0b0..The error signal for corresponding channel does not generate an error interrupt + * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request + */ #define DMA_EEI_EEI14(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI14_SHIFT)) & DMA_EEI_EEI14_MASK) #define DMA_EEI_EEI15_MASK (0x8000U) #define DMA_EEI_EEI15_SHIFT (15U) +/*! EEI15 - Enable Error Interrupt 15 + * 0b0..The error signal for corresponding channel does not generate an error interrupt + * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request + */ #define DMA_EEI_EEI15(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI15_SHIFT)) & DMA_EEI_EEI15_MASK) +/*! @} */ /*! @name CEEI - Clear Enable Error Interrupt Register */ +/*! @{ */ #define DMA_CEEI_CEEI_MASK (0xFU) #define DMA_CEEI_CEEI_SHIFT (0U) #define DMA_CEEI_CEEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_CEEI_SHIFT)) & DMA_CEEI_CEEI_MASK) #define DMA_CEEI_CAEE_MASK (0x40U) #define DMA_CEEI_CAEE_SHIFT (6U) +/*! CAEE - Clear All Enable Error Interrupts + * 0b0..Clear only the EEI bit specified in the CEEI field + * 0b1..Clear all bits in EEI + */ #define DMA_CEEI_CAEE(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_CAEE_SHIFT)) & DMA_CEEI_CAEE_MASK) #define DMA_CEEI_NOP_MASK (0x80U) #define DMA_CEEI_NOP_SHIFT (7U) +/*! NOP - No Op enable + * 0b0..Normal operation + * 0b1..No operation, ignore the other bits in this register + */ #define DMA_CEEI_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_NOP_SHIFT)) & DMA_CEEI_NOP_MASK) +/*! @} */ /*! @name SEEI - Set Enable Error Interrupt Register */ +/*! @{ */ #define DMA_SEEI_SEEI_MASK (0xFU) #define DMA_SEEI_SEEI_SHIFT (0U) #define DMA_SEEI_SEEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_SEEI_SHIFT)) & DMA_SEEI_SEEI_MASK) #define DMA_SEEI_SAEE_MASK (0x40U) #define DMA_SEEI_SAEE_SHIFT (6U) +/*! SAEE - Sets All Enable Error Interrupts + * 0b0..Set only the EEI bit specified in the SEEI field. + * 0b1..Sets all bits in EEI + */ #define DMA_SEEI_SAEE(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_SAEE_SHIFT)) & DMA_SEEI_SAEE_MASK) #define DMA_SEEI_NOP_MASK (0x80U) #define DMA_SEEI_NOP_SHIFT (7U) +/*! NOP - No Op enable + * 0b0..Normal operation + * 0b1..No operation, ignore the other bits in this register + */ #define DMA_SEEI_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_NOP_SHIFT)) & DMA_SEEI_NOP_MASK) +/*! @} */ /*! @name CERQ - Clear Enable Request Register */ +/*! @{ */ #define DMA_CERQ_CERQ_MASK (0xFU) #define DMA_CERQ_CERQ_SHIFT (0U) #define DMA_CERQ_CERQ(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_CERQ_SHIFT)) & DMA_CERQ_CERQ_MASK) #define DMA_CERQ_CAER_MASK (0x40U) #define DMA_CERQ_CAER_SHIFT (6U) +/*! CAER - Clear All Enable Requests + * 0b0..Clear only the ERQ bit specified in the CERQ field + * 0b1..Clear all bits in ERQ + */ #define DMA_CERQ_CAER(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_CAER_SHIFT)) & DMA_CERQ_CAER_MASK) #define DMA_CERQ_NOP_MASK (0x80U) #define DMA_CERQ_NOP_SHIFT (7U) +/*! NOP - No Op enable + * 0b0..Normal operation + * 0b1..No operation, ignore the other bits in this register + */ #define DMA_CERQ_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_NOP_SHIFT)) & DMA_CERQ_NOP_MASK) +/*! @} */ /*! @name SERQ - Set Enable Request Register */ +/*! @{ */ #define DMA_SERQ_SERQ_MASK (0xFU) #define DMA_SERQ_SERQ_SHIFT (0U) #define DMA_SERQ_SERQ(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_SERQ_SHIFT)) & DMA_SERQ_SERQ_MASK) #define DMA_SERQ_SAER_MASK (0x40U) #define DMA_SERQ_SAER_SHIFT (6U) +/*! SAER - Set All Enable Requests + * 0b0..Set only the ERQ bit specified in the SERQ field + * 0b1..Set all bits in ERQ + */ #define DMA_SERQ_SAER(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_SAER_SHIFT)) & DMA_SERQ_SAER_MASK) #define DMA_SERQ_NOP_MASK (0x80U) #define DMA_SERQ_NOP_SHIFT (7U) +/*! NOP - No Op enable + * 0b0..Normal operation + * 0b1..No operation, ignore the other bits in this register + */ #define DMA_SERQ_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_NOP_SHIFT)) & DMA_SERQ_NOP_MASK) +/*! @} */ /*! @name CDNE - Clear DONE Status Bit Register */ +/*! @{ */ #define DMA_CDNE_CDNE_MASK (0xFU) #define DMA_CDNE_CDNE_SHIFT (0U) #define DMA_CDNE_CDNE(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_CDNE_SHIFT)) & DMA_CDNE_CDNE_MASK) #define DMA_CDNE_CADN_MASK (0x40U) #define DMA_CDNE_CADN_SHIFT (6U) +/*! CADN - Clears All DONE Bits + * 0b0..Clears only the TCDn_CSR[DONE] bit specified in the CDNE field + * 0b1..Clears all bits in TCDn_CSR[DONE] + */ #define DMA_CDNE_CADN(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_CADN_SHIFT)) & DMA_CDNE_CADN_MASK) #define DMA_CDNE_NOP_MASK (0x80U) #define DMA_CDNE_NOP_SHIFT (7U) +/*! NOP - No Op enable + * 0b0..Normal operation + * 0b1..No operation, ignore the other bits in this register + */ #define DMA_CDNE_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_NOP_SHIFT)) & DMA_CDNE_NOP_MASK) +/*! @} */ /*! @name SSRT - Set START Bit Register */ +/*! @{ */ #define DMA_SSRT_SSRT_MASK (0xFU) #define DMA_SSRT_SSRT_SHIFT (0U) #define DMA_SSRT_SSRT(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_SSRT_SHIFT)) & DMA_SSRT_SSRT_MASK) #define DMA_SSRT_SAST_MASK (0x40U) #define DMA_SSRT_SAST_SHIFT (6U) +/*! SAST - Set All START Bits (activates all channels) + * 0b0..Set only the TCDn_CSR[START] bit specified in the SSRT field + * 0b1..Set all bits in TCDn_CSR[START] + */ #define DMA_SSRT_SAST(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_SAST_SHIFT)) & DMA_SSRT_SAST_MASK) #define DMA_SSRT_NOP_MASK (0x80U) #define DMA_SSRT_NOP_SHIFT (7U) +/*! NOP - No Op enable + * 0b0..Normal operation + * 0b1..No operation, ignore the other bits in this register + */ #define DMA_SSRT_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_NOP_SHIFT)) & DMA_SSRT_NOP_MASK) +/*! @} */ /*! @name CERR - Clear Error Register */ +/*! @{ */ #define DMA_CERR_CERR_MASK (0xFU) #define DMA_CERR_CERR_SHIFT (0U) #define DMA_CERR_CERR(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_CERR_SHIFT)) & DMA_CERR_CERR_MASK) #define DMA_CERR_CAEI_MASK (0x40U) #define DMA_CERR_CAEI_SHIFT (6U) +/*! CAEI - Clear All Error Indicators + * 0b0..Clear only the ERR bit specified in the CERR field + * 0b1..Clear all bits in ERR + */ #define DMA_CERR_CAEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_CAEI_SHIFT)) & DMA_CERR_CAEI_MASK) #define DMA_CERR_NOP_MASK (0x80U) #define DMA_CERR_NOP_SHIFT (7U) +/*! NOP - No Op enable + * 0b0..Normal operation + * 0b1..No operation, ignore the other bits in this register + */ #define DMA_CERR_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_NOP_SHIFT)) & DMA_CERR_NOP_MASK) +/*! @} */ /*! @name CINT - Clear Interrupt Request Register */ +/*! @{ */ #define DMA_CINT_CINT_MASK (0xFU) #define DMA_CINT_CINT_SHIFT (0U) #define DMA_CINT_CINT(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_CINT_SHIFT)) & DMA_CINT_CINT_MASK) #define DMA_CINT_CAIR_MASK (0x40U) #define DMA_CINT_CAIR_SHIFT (6U) +/*! CAIR - Clear All Interrupt Requests + * 0b0..Clear only the INT bit specified in the CINT field + * 0b1..Clear all bits in INT + */ #define DMA_CINT_CAIR(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_CAIR_SHIFT)) & DMA_CINT_CAIR_MASK) #define DMA_CINT_NOP_MASK (0x80U) #define DMA_CINT_NOP_SHIFT (7U) +/*! NOP - No Op enable + * 0b0..Normal operation + * 0b1..No operation, ignore the other bits in this register + */ #define DMA_CINT_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_NOP_SHIFT)) & DMA_CINT_NOP_MASK) +/*! @} */ /*! @name INT - Interrupt Request Register */ +/*! @{ */ #define DMA_INT_INT0_MASK (0x1U) #define DMA_INT_INT0_SHIFT (0U) +/*! INT0 - Interrupt Request 0 + * 0b0..The interrupt request for corresponding channel is cleared + * 0b1..The interrupt request for corresponding channel is active + */ #define DMA_INT_INT0(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT0_SHIFT)) & DMA_INT_INT0_MASK) #define DMA_INT_INT1_MASK (0x2U) #define DMA_INT_INT1_SHIFT (1U) +/*! INT1 - Interrupt Request 1 + * 0b0..The interrupt request for corresponding channel is cleared + * 0b1..The interrupt request for corresponding channel is active + */ #define DMA_INT_INT1(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT1_SHIFT)) & DMA_INT_INT1_MASK) #define DMA_INT_INT2_MASK (0x4U) #define DMA_INT_INT2_SHIFT (2U) +/*! INT2 - Interrupt Request 2 + * 0b0..The interrupt request for corresponding channel is cleared + * 0b1..The interrupt request for corresponding channel is active + */ #define DMA_INT_INT2(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT2_SHIFT)) & DMA_INT_INT2_MASK) #define DMA_INT_INT3_MASK (0x8U) #define DMA_INT_INT3_SHIFT (3U) +/*! INT3 - Interrupt Request 3 + * 0b0..The interrupt request for corresponding channel is cleared + * 0b1..The interrupt request for corresponding channel is active + */ #define DMA_INT_INT3(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT3_SHIFT)) & DMA_INT_INT3_MASK) #define DMA_INT_INT4_MASK (0x10U) #define DMA_INT_INT4_SHIFT (4U) +/*! INT4 - Interrupt Request 4 + * 0b0..The interrupt request for corresponding channel is cleared + * 0b1..The interrupt request for corresponding channel is active + */ #define DMA_INT_INT4(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT4_SHIFT)) & DMA_INT_INT4_MASK) #define DMA_INT_INT5_MASK (0x20U) #define DMA_INT_INT5_SHIFT (5U) +/*! INT5 - Interrupt Request 5 + * 0b0..The interrupt request for corresponding channel is cleared + * 0b1..The interrupt request for corresponding channel is active + */ #define DMA_INT_INT5(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT5_SHIFT)) & DMA_INT_INT5_MASK) #define DMA_INT_INT6_MASK (0x40U) #define DMA_INT_INT6_SHIFT (6U) +/*! INT6 - Interrupt Request 6 + * 0b0..The interrupt request for corresponding channel is cleared + * 0b1..The interrupt request for corresponding channel is active + */ #define DMA_INT_INT6(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT6_SHIFT)) & DMA_INT_INT6_MASK) #define DMA_INT_INT7_MASK (0x80U) #define DMA_INT_INT7_SHIFT (7U) +/*! INT7 - Interrupt Request 7 + * 0b0..The interrupt request for corresponding channel is cleared + * 0b1..The interrupt request for corresponding channel is active + */ #define DMA_INT_INT7(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT7_SHIFT)) & DMA_INT_INT7_MASK) #define DMA_INT_INT8_MASK (0x100U) #define DMA_INT_INT8_SHIFT (8U) +/*! INT8 - Interrupt Request 8 + * 0b0..The interrupt request for corresponding channel is cleared + * 0b1..The interrupt request for corresponding channel is active + */ #define DMA_INT_INT8(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT8_SHIFT)) & DMA_INT_INT8_MASK) #define DMA_INT_INT9_MASK (0x200U) #define DMA_INT_INT9_SHIFT (9U) +/*! INT9 - Interrupt Request 9 + * 0b0..The interrupt request for corresponding channel is cleared + * 0b1..The interrupt request for corresponding channel is active + */ #define DMA_INT_INT9(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT9_SHIFT)) & DMA_INT_INT9_MASK) #define DMA_INT_INT10_MASK (0x400U) #define DMA_INT_INT10_SHIFT (10U) +/*! INT10 - Interrupt Request 10 + * 0b0..The interrupt request for corresponding channel is cleared + * 0b1..The interrupt request for corresponding channel is active + */ #define DMA_INT_INT10(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT10_SHIFT)) & DMA_INT_INT10_MASK) #define DMA_INT_INT11_MASK (0x800U) #define DMA_INT_INT11_SHIFT (11U) +/*! INT11 - Interrupt Request 11 + * 0b0..The interrupt request for corresponding channel is cleared + * 0b1..The interrupt request for corresponding channel is active + */ #define DMA_INT_INT11(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT11_SHIFT)) & DMA_INT_INT11_MASK) #define DMA_INT_INT12_MASK (0x1000U) #define DMA_INT_INT12_SHIFT (12U) +/*! INT12 - Interrupt Request 12 + * 0b0..The interrupt request for corresponding channel is cleared + * 0b1..The interrupt request for corresponding channel is active + */ #define DMA_INT_INT12(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT12_SHIFT)) & DMA_INT_INT12_MASK) #define DMA_INT_INT13_MASK (0x2000U) #define DMA_INT_INT13_SHIFT (13U) +/*! INT13 - Interrupt Request 13 + * 0b0..The interrupt request for corresponding channel is cleared + * 0b1..The interrupt request for corresponding channel is active + */ #define DMA_INT_INT13(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT13_SHIFT)) & DMA_INT_INT13_MASK) #define DMA_INT_INT14_MASK (0x4000U) #define DMA_INT_INT14_SHIFT (14U) +/*! INT14 - Interrupt Request 14 + * 0b0..The interrupt request for corresponding channel is cleared + * 0b1..The interrupt request for corresponding channel is active + */ #define DMA_INT_INT14(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT14_SHIFT)) & DMA_INT_INT14_MASK) #define DMA_INT_INT15_MASK (0x8000U) #define DMA_INT_INT15_SHIFT (15U) +/*! INT15 - Interrupt Request 15 + * 0b0..The interrupt request for corresponding channel is cleared + * 0b1..The interrupt request for corresponding channel is active + */ #define DMA_INT_INT15(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT15_SHIFT)) & DMA_INT_INT15_MASK) +/*! @} */ /*! @name ERR - Error Register */ +/*! @{ */ #define DMA_ERR_ERR0_MASK (0x1U) #define DMA_ERR_ERR0_SHIFT (0U) +/*! ERR0 - Error In Channel 0 + * 0b0..An error in the corresponding channel has not occurred + * 0b1..An error in the corresponding channel has occurred + */ #define DMA_ERR_ERR0(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR0_SHIFT)) & DMA_ERR_ERR0_MASK) #define DMA_ERR_ERR1_MASK (0x2U) #define DMA_ERR_ERR1_SHIFT (1U) +/*! ERR1 - Error In Channel 1 + * 0b0..An error in the corresponding channel has not occurred + * 0b1..An error in the corresponding channel has occurred + */ #define DMA_ERR_ERR1(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR1_SHIFT)) & DMA_ERR_ERR1_MASK) #define DMA_ERR_ERR2_MASK (0x4U) #define DMA_ERR_ERR2_SHIFT (2U) +/*! ERR2 - Error In Channel 2 + * 0b0..An error in the corresponding channel has not occurred + * 0b1..An error in the corresponding channel has occurred + */ #define DMA_ERR_ERR2(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR2_SHIFT)) & DMA_ERR_ERR2_MASK) #define DMA_ERR_ERR3_MASK (0x8U) #define DMA_ERR_ERR3_SHIFT (3U) +/*! ERR3 - Error In Channel 3 + * 0b0..An error in the corresponding channel has not occurred + * 0b1..An error in the corresponding channel has occurred + */ #define DMA_ERR_ERR3(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR3_SHIFT)) & DMA_ERR_ERR3_MASK) #define DMA_ERR_ERR4_MASK (0x10U) #define DMA_ERR_ERR4_SHIFT (4U) +/*! ERR4 - Error In Channel 4 + * 0b0..An error in the corresponding channel has not occurred + * 0b1..An error in the corresponding channel has occurred + */ #define DMA_ERR_ERR4(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR4_SHIFT)) & DMA_ERR_ERR4_MASK) #define DMA_ERR_ERR5_MASK (0x20U) #define DMA_ERR_ERR5_SHIFT (5U) +/*! ERR5 - Error In Channel 5 + * 0b0..An error in the corresponding channel has not occurred + * 0b1..An error in the corresponding channel has occurred + */ #define DMA_ERR_ERR5(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR5_SHIFT)) & DMA_ERR_ERR5_MASK) #define DMA_ERR_ERR6_MASK (0x40U) #define DMA_ERR_ERR6_SHIFT (6U) +/*! ERR6 - Error In Channel 6 + * 0b0..An error in the corresponding channel has not occurred + * 0b1..An error in the corresponding channel has occurred + */ #define DMA_ERR_ERR6(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR6_SHIFT)) & DMA_ERR_ERR6_MASK) #define DMA_ERR_ERR7_MASK (0x80U) #define DMA_ERR_ERR7_SHIFT (7U) +/*! ERR7 - Error In Channel 7 + * 0b0..An error in the corresponding channel has not occurred + * 0b1..An error in the corresponding channel has occurred + */ #define DMA_ERR_ERR7(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR7_SHIFT)) & DMA_ERR_ERR7_MASK) #define DMA_ERR_ERR8_MASK (0x100U) #define DMA_ERR_ERR8_SHIFT (8U) +/*! ERR8 - Error In Channel 8 + * 0b0..An error in the corresponding channel has not occurred + * 0b1..An error in the corresponding channel has occurred + */ #define DMA_ERR_ERR8(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR8_SHIFT)) & DMA_ERR_ERR8_MASK) #define DMA_ERR_ERR9_MASK (0x200U) #define DMA_ERR_ERR9_SHIFT (9U) +/*! ERR9 - Error In Channel 9 + * 0b0..An error in the corresponding channel has not occurred + * 0b1..An error in the corresponding channel has occurred + */ #define DMA_ERR_ERR9(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR9_SHIFT)) & DMA_ERR_ERR9_MASK) #define DMA_ERR_ERR10_MASK (0x400U) #define DMA_ERR_ERR10_SHIFT (10U) +/*! ERR10 - Error In Channel 10 + * 0b0..An error in the corresponding channel has not occurred + * 0b1..An error in the corresponding channel has occurred + */ #define DMA_ERR_ERR10(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR10_SHIFT)) & DMA_ERR_ERR10_MASK) #define DMA_ERR_ERR11_MASK (0x800U) #define DMA_ERR_ERR11_SHIFT (11U) +/*! ERR11 - Error In Channel 11 + * 0b0..An error in the corresponding channel has not occurred + * 0b1..An error in the corresponding channel has occurred + */ #define DMA_ERR_ERR11(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR11_SHIFT)) & DMA_ERR_ERR11_MASK) #define DMA_ERR_ERR12_MASK (0x1000U) #define DMA_ERR_ERR12_SHIFT (12U) +/*! ERR12 - Error In Channel 12 + * 0b0..An error in the corresponding channel has not occurred + * 0b1..An error in the corresponding channel has occurred + */ #define DMA_ERR_ERR12(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR12_SHIFT)) & DMA_ERR_ERR12_MASK) #define DMA_ERR_ERR13_MASK (0x2000U) #define DMA_ERR_ERR13_SHIFT (13U) +/*! ERR13 - Error In Channel 13 + * 0b0..An error in the corresponding channel has not occurred + * 0b1..An error in the corresponding channel has occurred + */ #define DMA_ERR_ERR13(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR13_SHIFT)) & DMA_ERR_ERR13_MASK) #define DMA_ERR_ERR14_MASK (0x4000U) #define DMA_ERR_ERR14_SHIFT (14U) +/*! ERR14 - Error In Channel 14 + * 0b0..An error in the corresponding channel has not occurred + * 0b1..An error in the corresponding channel has occurred + */ #define DMA_ERR_ERR14(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR14_SHIFT)) & DMA_ERR_ERR14_MASK) #define DMA_ERR_ERR15_MASK (0x8000U) #define DMA_ERR_ERR15_SHIFT (15U) +/*! ERR15 - Error In Channel 15 + * 0b0..An error in the corresponding channel has not occurred + * 0b1..An error in the corresponding channel has occurred + */ #define DMA_ERR_ERR15(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR15_SHIFT)) & DMA_ERR_ERR15_MASK) +/*! @} */ /*! @name HRS - Hardware Request Status Register */ +/*! @{ */ #define DMA_HRS_HRS0_MASK (0x1U) #define DMA_HRS_HRS0_SHIFT (0U) +/*! HRS0 - Hardware Request Status Channel 0 + * 0b0..A hardware service request for channel 0 is not present + * 0b1..A hardware service request for channel 0 is present + */ #define DMA_HRS_HRS0(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS0_SHIFT)) & DMA_HRS_HRS0_MASK) #define DMA_HRS_HRS1_MASK (0x2U) #define DMA_HRS_HRS1_SHIFT (1U) +/*! HRS1 - Hardware Request Status Channel 1 + * 0b0..A hardware service request for channel 1 is not present + * 0b1..A hardware service request for channel 1 is present + */ #define DMA_HRS_HRS1(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS1_SHIFT)) & DMA_HRS_HRS1_MASK) #define DMA_HRS_HRS2_MASK (0x4U) #define DMA_HRS_HRS2_SHIFT (2U) +/*! HRS2 - Hardware Request Status Channel 2 + * 0b0..A hardware service request for channel 2 is not present + * 0b1..A hardware service request for channel 2 is present + */ #define DMA_HRS_HRS2(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS2_SHIFT)) & DMA_HRS_HRS2_MASK) #define DMA_HRS_HRS3_MASK (0x8U) #define DMA_HRS_HRS3_SHIFT (3U) +/*! HRS3 - Hardware Request Status Channel 3 + * 0b0..A hardware service request for channel 3 is not present + * 0b1..A hardware service request for channel 3 is present + */ #define DMA_HRS_HRS3(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS3_SHIFT)) & DMA_HRS_HRS3_MASK) #define DMA_HRS_HRS4_MASK (0x10U) #define DMA_HRS_HRS4_SHIFT (4U) +/*! HRS4 - Hardware Request Status Channel 4 + * 0b0..A hardware service request for channel 4 is not present + * 0b1..A hardware service request for channel 4 is present + */ #define DMA_HRS_HRS4(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS4_SHIFT)) & DMA_HRS_HRS4_MASK) #define DMA_HRS_HRS5_MASK (0x20U) #define DMA_HRS_HRS5_SHIFT (5U) +/*! HRS5 - Hardware Request Status Channel 5 + * 0b0..A hardware service request for channel 5 is not present + * 0b1..A hardware service request for channel 5 is present + */ #define DMA_HRS_HRS5(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS5_SHIFT)) & DMA_HRS_HRS5_MASK) #define DMA_HRS_HRS6_MASK (0x40U) #define DMA_HRS_HRS6_SHIFT (6U) +/*! HRS6 - Hardware Request Status Channel 6 + * 0b0..A hardware service request for channel 6 is not present + * 0b1..A hardware service request for channel 6 is present + */ #define DMA_HRS_HRS6(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS6_SHIFT)) & DMA_HRS_HRS6_MASK) #define DMA_HRS_HRS7_MASK (0x80U) #define DMA_HRS_HRS7_SHIFT (7U) +/*! HRS7 - Hardware Request Status Channel 7 + * 0b0..A hardware service request for channel 7 is not present + * 0b1..A hardware service request for channel 7 is present + */ #define DMA_HRS_HRS7(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS7_SHIFT)) & DMA_HRS_HRS7_MASK) #define DMA_HRS_HRS8_MASK (0x100U) #define DMA_HRS_HRS8_SHIFT (8U) +/*! HRS8 - Hardware Request Status Channel 8 + * 0b0..A hardware service request for channel 8 is not present + * 0b1..A hardware service request for channel 8 is present + */ #define DMA_HRS_HRS8(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS8_SHIFT)) & DMA_HRS_HRS8_MASK) #define DMA_HRS_HRS9_MASK (0x200U) #define DMA_HRS_HRS9_SHIFT (9U) +/*! HRS9 - Hardware Request Status Channel 9 + * 0b0..A hardware service request for channel 9 is not present + * 0b1..A hardware service request for channel 9 is present + */ #define DMA_HRS_HRS9(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS9_SHIFT)) & DMA_HRS_HRS9_MASK) #define DMA_HRS_HRS10_MASK (0x400U) #define DMA_HRS_HRS10_SHIFT (10U) +/*! HRS10 - Hardware Request Status Channel 10 + * 0b0..A hardware service request for channel 10 is not present + * 0b1..A hardware service request for channel 10 is present + */ #define DMA_HRS_HRS10(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS10_SHIFT)) & DMA_HRS_HRS10_MASK) #define DMA_HRS_HRS11_MASK (0x800U) #define DMA_HRS_HRS11_SHIFT (11U) +/*! HRS11 - Hardware Request Status Channel 11 + * 0b0..A hardware service request for channel 11 is not present + * 0b1..A hardware service request for channel 11 is present + */ #define DMA_HRS_HRS11(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS11_SHIFT)) & DMA_HRS_HRS11_MASK) #define DMA_HRS_HRS12_MASK (0x1000U) #define DMA_HRS_HRS12_SHIFT (12U) +/*! HRS12 - Hardware Request Status Channel 12 + * 0b0..A hardware service request for channel 12 is not present + * 0b1..A hardware service request for channel 12 is present + */ #define DMA_HRS_HRS12(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS12_SHIFT)) & DMA_HRS_HRS12_MASK) #define DMA_HRS_HRS13_MASK (0x2000U) #define DMA_HRS_HRS13_SHIFT (13U) +/*! HRS13 - Hardware Request Status Channel 13 + * 0b0..A hardware service request for channel 13 is not present + * 0b1..A hardware service request for channel 13 is present + */ #define DMA_HRS_HRS13(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS13_SHIFT)) & DMA_HRS_HRS13_MASK) #define DMA_HRS_HRS14_MASK (0x4000U) #define DMA_HRS_HRS14_SHIFT (14U) +/*! HRS14 - Hardware Request Status Channel 14 + * 0b0..A hardware service request for channel 14 is not present + * 0b1..A hardware service request for channel 14 is present + */ #define DMA_HRS_HRS14(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS14_SHIFT)) & DMA_HRS_HRS14_MASK) #define DMA_HRS_HRS15_MASK (0x8000U) #define DMA_HRS_HRS15_SHIFT (15U) +/*! HRS15 - Hardware Request Status Channel 15 + * 0b0..A hardware service request for channel 15 is not present + * 0b1..A hardware service request for channel 15 is present + */ #define DMA_HRS_HRS15(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS15_SHIFT)) & DMA_HRS_HRS15_MASK) +/*! @} */ /*! @name DCHPRI3 - Channel n Priority Register */ +/*! @{ */ #define DMA_DCHPRI3_CHPRI_MASK (0xFU) #define DMA_DCHPRI3_CHPRI_SHIFT (0U) #define DMA_DCHPRI3_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_CHPRI_SHIFT)) & DMA_DCHPRI3_CHPRI_MASK) #define DMA_DCHPRI3_DPA_MASK (0x40U) #define DMA_DCHPRI3_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability + * 0b0..Channel n can suspend a lower priority channel + * 0b1..Channel n cannot suspend any channel, regardless of channel priority + */ #define DMA_DCHPRI3_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_DPA_SHIFT)) & DMA_DCHPRI3_DPA_MASK) #define DMA_DCHPRI3_ECP_MASK (0x80U) #define DMA_DCHPRI3_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption + * 0b0..Channel n cannot be suspended by a higher priority channel's service request + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel + */ #define DMA_DCHPRI3_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_ECP_SHIFT)) & DMA_DCHPRI3_ECP_MASK) +/*! @} */ /*! @name DCHPRI2 - Channel n Priority Register */ +/*! @{ */ #define DMA_DCHPRI2_CHPRI_MASK (0xFU) #define DMA_DCHPRI2_CHPRI_SHIFT (0U) #define DMA_DCHPRI2_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_CHPRI_SHIFT)) & DMA_DCHPRI2_CHPRI_MASK) #define DMA_DCHPRI2_DPA_MASK (0x40U) #define DMA_DCHPRI2_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability + * 0b0..Channel n can suspend a lower priority channel + * 0b1..Channel n cannot suspend any channel, regardless of channel priority + */ #define DMA_DCHPRI2_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_DPA_SHIFT)) & DMA_DCHPRI2_DPA_MASK) #define DMA_DCHPRI2_ECP_MASK (0x80U) #define DMA_DCHPRI2_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption + * 0b0..Channel n cannot be suspended by a higher priority channel's service request + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel + */ #define DMA_DCHPRI2_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_ECP_SHIFT)) & DMA_DCHPRI2_ECP_MASK) +/*! @} */ /*! @name DCHPRI1 - Channel n Priority Register */ +/*! @{ */ #define DMA_DCHPRI1_CHPRI_MASK (0xFU) #define DMA_DCHPRI1_CHPRI_SHIFT (0U) #define DMA_DCHPRI1_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_CHPRI_SHIFT)) & DMA_DCHPRI1_CHPRI_MASK) #define DMA_DCHPRI1_DPA_MASK (0x40U) #define DMA_DCHPRI1_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability + * 0b0..Channel n can suspend a lower priority channel + * 0b1..Channel n cannot suspend any channel, regardless of channel priority + */ #define DMA_DCHPRI1_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_DPA_SHIFT)) & DMA_DCHPRI1_DPA_MASK) #define DMA_DCHPRI1_ECP_MASK (0x80U) #define DMA_DCHPRI1_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption + * 0b0..Channel n cannot be suspended by a higher priority channel's service request + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel + */ #define DMA_DCHPRI1_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_ECP_SHIFT)) & DMA_DCHPRI1_ECP_MASK) +/*! @} */ /*! @name DCHPRI0 - Channel n Priority Register */ +/*! @{ */ #define DMA_DCHPRI0_CHPRI_MASK (0xFU) #define DMA_DCHPRI0_CHPRI_SHIFT (0U) #define DMA_DCHPRI0_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_CHPRI_SHIFT)) & DMA_DCHPRI0_CHPRI_MASK) #define DMA_DCHPRI0_DPA_MASK (0x40U) #define DMA_DCHPRI0_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability + * 0b0..Channel n can suspend a lower priority channel + * 0b1..Channel n cannot suspend any channel, regardless of channel priority + */ #define DMA_DCHPRI0_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_DPA_SHIFT)) & DMA_DCHPRI0_DPA_MASK) #define DMA_DCHPRI0_ECP_MASK (0x80U) #define DMA_DCHPRI0_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption + * 0b0..Channel n cannot be suspended by a higher priority channel's service request + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel + */ #define DMA_DCHPRI0_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_ECP_SHIFT)) & DMA_DCHPRI0_ECP_MASK) +/*! @} */ /*! @name DCHPRI7 - Channel n Priority Register */ +/*! @{ */ #define DMA_DCHPRI7_CHPRI_MASK (0xFU) #define DMA_DCHPRI7_CHPRI_SHIFT (0U) #define DMA_DCHPRI7_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_CHPRI_SHIFT)) & DMA_DCHPRI7_CHPRI_MASK) #define DMA_DCHPRI7_DPA_MASK (0x40U) #define DMA_DCHPRI7_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability + * 0b0..Channel n can suspend a lower priority channel + * 0b1..Channel n cannot suspend any channel, regardless of channel priority + */ #define DMA_DCHPRI7_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_DPA_SHIFT)) & DMA_DCHPRI7_DPA_MASK) #define DMA_DCHPRI7_ECP_MASK (0x80U) #define DMA_DCHPRI7_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption + * 0b0..Channel n cannot be suspended by a higher priority channel's service request + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel + */ #define DMA_DCHPRI7_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_ECP_SHIFT)) & DMA_DCHPRI7_ECP_MASK) +/*! @} */ /*! @name DCHPRI6 - Channel n Priority Register */ +/*! @{ */ #define DMA_DCHPRI6_CHPRI_MASK (0xFU) #define DMA_DCHPRI6_CHPRI_SHIFT (0U) #define DMA_DCHPRI6_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_CHPRI_SHIFT)) & DMA_DCHPRI6_CHPRI_MASK) #define DMA_DCHPRI6_DPA_MASK (0x40U) #define DMA_DCHPRI6_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability + * 0b0..Channel n can suspend a lower priority channel + * 0b1..Channel n cannot suspend any channel, regardless of channel priority + */ #define DMA_DCHPRI6_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_DPA_SHIFT)) & DMA_DCHPRI6_DPA_MASK) #define DMA_DCHPRI6_ECP_MASK (0x80U) #define DMA_DCHPRI6_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption + * 0b0..Channel n cannot be suspended by a higher priority channel's service request + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel + */ #define DMA_DCHPRI6_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_ECP_SHIFT)) & DMA_DCHPRI6_ECP_MASK) +/*! @} */ /*! @name DCHPRI5 - Channel n Priority Register */ +/*! @{ */ #define DMA_DCHPRI5_CHPRI_MASK (0xFU) #define DMA_DCHPRI5_CHPRI_SHIFT (0U) #define DMA_DCHPRI5_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_CHPRI_SHIFT)) & DMA_DCHPRI5_CHPRI_MASK) #define DMA_DCHPRI5_DPA_MASK (0x40U) #define DMA_DCHPRI5_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability + * 0b0..Channel n can suspend a lower priority channel + * 0b1..Channel n cannot suspend any channel, regardless of channel priority + */ #define DMA_DCHPRI5_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_DPA_SHIFT)) & DMA_DCHPRI5_DPA_MASK) #define DMA_DCHPRI5_ECP_MASK (0x80U) #define DMA_DCHPRI5_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption + * 0b0..Channel n cannot be suspended by a higher priority channel's service request + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel + */ #define DMA_DCHPRI5_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_ECP_SHIFT)) & DMA_DCHPRI5_ECP_MASK) +/*! @} */ /*! @name DCHPRI4 - Channel n Priority Register */ +/*! @{ */ #define DMA_DCHPRI4_CHPRI_MASK (0xFU) #define DMA_DCHPRI4_CHPRI_SHIFT (0U) #define DMA_DCHPRI4_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_CHPRI_SHIFT)) & DMA_DCHPRI4_CHPRI_MASK) #define DMA_DCHPRI4_DPA_MASK (0x40U) #define DMA_DCHPRI4_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability + * 0b0..Channel n can suspend a lower priority channel + * 0b1..Channel n cannot suspend any channel, regardless of channel priority + */ #define DMA_DCHPRI4_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_DPA_SHIFT)) & DMA_DCHPRI4_DPA_MASK) #define DMA_DCHPRI4_ECP_MASK (0x80U) #define DMA_DCHPRI4_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption + * 0b0..Channel n cannot be suspended by a higher priority channel's service request + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel + */ #define DMA_DCHPRI4_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_ECP_SHIFT)) & DMA_DCHPRI4_ECP_MASK) +/*! @} */ /*! @name DCHPRI11 - Channel n Priority Register */ +/*! @{ */ #define DMA_DCHPRI11_CHPRI_MASK (0xFU) #define DMA_DCHPRI11_CHPRI_SHIFT (0U) #define DMA_DCHPRI11_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_CHPRI_SHIFT)) & DMA_DCHPRI11_CHPRI_MASK) #define DMA_DCHPRI11_DPA_MASK (0x40U) #define DMA_DCHPRI11_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability + * 0b0..Channel n can suspend a lower priority channel + * 0b1..Channel n cannot suspend any channel, regardless of channel priority + */ #define DMA_DCHPRI11_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_DPA_SHIFT)) & DMA_DCHPRI11_DPA_MASK) #define DMA_DCHPRI11_ECP_MASK (0x80U) #define DMA_DCHPRI11_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption + * 0b0..Channel n cannot be suspended by a higher priority channel's service request + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel + */ #define DMA_DCHPRI11_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_ECP_SHIFT)) & DMA_DCHPRI11_ECP_MASK) +/*! @} */ /*! @name DCHPRI10 - Channel n Priority Register */ +/*! @{ */ #define DMA_DCHPRI10_CHPRI_MASK (0xFU) #define DMA_DCHPRI10_CHPRI_SHIFT (0U) #define DMA_DCHPRI10_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_CHPRI_SHIFT)) & DMA_DCHPRI10_CHPRI_MASK) #define DMA_DCHPRI10_DPA_MASK (0x40U) #define DMA_DCHPRI10_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability + * 0b0..Channel n can suspend a lower priority channel + * 0b1..Channel n cannot suspend any channel, regardless of channel priority + */ #define DMA_DCHPRI10_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_DPA_SHIFT)) & DMA_DCHPRI10_DPA_MASK) #define DMA_DCHPRI10_ECP_MASK (0x80U) #define DMA_DCHPRI10_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption + * 0b0..Channel n cannot be suspended by a higher priority channel's service request + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel + */ #define DMA_DCHPRI10_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_ECP_SHIFT)) & DMA_DCHPRI10_ECP_MASK) +/*! @} */ /*! @name DCHPRI9 - Channel n Priority Register */ +/*! @{ */ #define DMA_DCHPRI9_CHPRI_MASK (0xFU) #define DMA_DCHPRI9_CHPRI_SHIFT (0U) #define DMA_DCHPRI9_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_CHPRI_SHIFT)) & DMA_DCHPRI9_CHPRI_MASK) #define DMA_DCHPRI9_DPA_MASK (0x40U) #define DMA_DCHPRI9_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability + * 0b0..Channel n can suspend a lower priority channel + * 0b1..Channel n cannot suspend any channel, regardless of channel priority + */ #define DMA_DCHPRI9_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_DPA_SHIFT)) & DMA_DCHPRI9_DPA_MASK) #define DMA_DCHPRI9_ECP_MASK (0x80U) #define DMA_DCHPRI9_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption + * 0b0..Channel n cannot be suspended by a higher priority channel's service request + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel + */ #define DMA_DCHPRI9_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_ECP_SHIFT)) & DMA_DCHPRI9_ECP_MASK) +/*! @} */ /*! @name DCHPRI8 - Channel n Priority Register */ +/*! @{ */ #define DMA_DCHPRI8_CHPRI_MASK (0xFU) #define DMA_DCHPRI8_CHPRI_SHIFT (0U) #define DMA_DCHPRI8_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_CHPRI_SHIFT)) & DMA_DCHPRI8_CHPRI_MASK) #define DMA_DCHPRI8_DPA_MASK (0x40U) #define DMA_DCHPRI8_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability + * 0b0..Channel n can suspend a lower priority channel + * 0b1..Channel n cannot suspend any channel, regardless of channel priority + */ #define DMA_DCHPRI8_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_DPA_SHIFT)) & DMA_DCHPRI8_DPA_MASK) #define DMA_DCHPRI8_ECP_MASK (0x80U) #define DMA_DCHPRI8_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption + * 0b0..Channel n cannot be suspended by a higher priority channel's service request + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel + */ #define DMA_DCHPRI8_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_ECP_SHIFT)) & DMA_DCHPRI8_ECP_MASK) +/*! @} */ /*! @name DCHPRI15 - Channel n Priority Register */ +/*! @{ */ #define DMA_DCHPRI15_CHPRI_MASK (0xFU) #define DMA_DCHPRI15_CHPRI_SHIFT (0U) #define DMA_DCHPRI15_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_CHPRI_SHIFT)) & DMA_DCHPRI15_CHPRI_MASK) #define DMA_DCHPRI15_DPA_MASK (0x40U) #define DMA_DCHPRI15_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability + * 0b0..Channel n can suspend a lower priority channel + * 0b1..Channel n cannot suspend any channel, regardless of channel priority + */ #define DMA_DCHPRI15_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_DPA_SHIFT)) & DMA_DCHPRI15_DPA_MASK) #define DMA_DCHPRI15_ECP_MASK (0x80U) #define DMA_DCHPRI15_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption + * 0b0..Channel n cannot be suspended by a higher priority channel's service request + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel + */ #define DMA_DCHPRI15_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_ECP_SHIFT)) & DMA_DCHPRI15_ECP_MASK) +/*! @} */ /*! @name DCHPRI14 - Channel n Priority Register */ +/*! @{ */ #define DMA_DCHPRI14_CHPRI_MASK (0xFU) #define DMA_DCHPRI14_CHPRI_SHIFT (0U) #define DMA_DCHPRI14_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_CHPRI_SHIFT)) & DMA_DCHPRI14_CHPRI_MASK) #define DMA_DCHPRI14_DPA_MASK (0x40U) #define DMA_DCHPRI14_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability + * 0b0..Channel n can suspend a lower priority channel + * 0b1..Channel n cannot suspend any channel, regardless of channel priority + */ #define DMA_DCHPRI14_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_DPA_SHIFT)) & DMA_DCHPRI14_DPA_MASK) #define DMA_DCHPRI14_ECP_MASK (0x80U) #define DMA_DCHPRI14_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption + * 0b0..Channel n cannot be suspended by a higher priority channel's service request + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel + */ #define DMA_DCHPRI14_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_ECP_SHIFT)) & DMA_DCHPRI14_ECP_MASK) +/*! @} */ /*! @name DCHPRI13 - Channel n Priority Register */ +/*! @{ */ #define DMA_DCHPRI13_CHPRI_MASK (0xFU) #define DMA_DCHPRI13_CHPRI_SHIFT (0U) #define DMA_DCHPRI13_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_CHPRI_SHIFT)) & DMA_DCHPRI13_CHPRI_MASK) #define DMA_DCHPRI13_DPA_MASK (0x40U) #define DMA_DCHPRI13_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability + * 0b0..Channel n can suspend a lower priority channel + * 0b1..Channel n cannot suspend any channel, regardless of channel priority + */ #define DMA_DCHPRI13_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_DPA_SHIFT)) & DMA_DCHPRI13_DPA_MASK) #define DMA_DCHPRI13_ECP_MASK (0x80U) #define DMA_DCHPRI13_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption + * 0b0..Channel n cannot be suspended by a higher priority channel's service request + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel + */ #define DMA_DCHPRI13_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_ECP_SHIFT)) & DMA_DCHPRI13_ECP_MASK) +/*! @} */ /*! @name DCHPRI12 - Channel n Priority Register */ +/*! @{ */ #define DMA_DCHPRI12_CHPRI_MASK (0xFU) #define DMA_DCHPRI12_CHPRI_SHIFT (0U) #define DMA_DCHPRI12_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_CHPRI_SHIFT)) & DMA_DCHPRI12_CHPRI_MASK) #define DMA_DCHPRI12_DPA_MASK (0x40U) #define DMA_DCHPRI12_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability + * 0b0..Channel n can suspend a lower priority channel + * 0b1..Channel n cannot suspend any channel, regardless of channel priority + */ #define DMA_DCHPRI12_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_DPA_SHIFT)) & DMA_DCHPRI12_DPA_MASK) #define DMA_DCHPRI12_ECP_MASK (0x80U) #define DMA_DCHPRI12_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption + * 0b0..Channel n cannot be suspended by a higher priority channel's service request + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel + */ #define DMA_DCHPRI12_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_ECP_SHIFT)) & DMA_DCHPRI12_ECP_MASK) +/*! @} */ /*! @name SADDR - TCD Source Address */ +/*! @{ */ #define DMA_SADDR_SADDR_MASK (0xFFFFFFFFU) #define DMA_SADDR_SADDR_SHIFT (0U) #define DMA_SADDR_SADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_SADDR_SADDR_SHIFT)) & DMA_SADDR_SADDR_MASK) +/*! @} */ /* The count of DMA_SADDR */ #define DMA_SADDR_COUNT (16U) /*! @name SOFF - TCD Signed Source Address Offset */ +/*! @{ */ #define DMA_SOFF_SOFF_MASK (0xFFFFU) #define DMA_SOFF_SOFF_SHIFT (0U) #define DMA_SOFF_SOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_SOFF_SOFF_SHIFT)) & DMA_SOFF_SOFF_MASK) +/*! @} */ /* The count of DMA_SOFF */ #define DMA_SOFF_COUNT (16U) /*! @name ATTR - TCD Transfer Attributes */ +/*! @{ */ #define DMA_ATTR_DSIZE_MASK (0x7U) #define DMA_ATTR_DSIZE_SHIFT (0U) #define DMA_ATTR_DSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_DSIZE_SHIFT)) & DMA_ATTR_DSIZE_MASK) @@ -4376,37 +7832,64 @@ typedef struct { #define DMA_ATTR_DMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_DMOD_SHIFT)) & DMA_ATTR_DMOD_MASK) #define DMA_ATTR_SSIZE_MASK (0x700U) #define DMA_ATTR_SSIZE_SHIFT (8U) +/*! SSIZE - Source data transfer size + * 0b000..8-bit + * 0b001..16-bit + * 0b010..32-bit + * 0b011..Reserved + * 0b100..16-byte + * 0b101..32-byte + * 0b110..Reserved + * 0b111..Reserved + */ #define DMA_ATTR_SSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_SSIZE_SHIFT)) & DMA_ATTR_SSIZE_MASK) #define DMA_ATTR_SMOD_MASK (0xF800U) #define DMA_ATTR_SMOD_SHIFT (11U) +/*! SMOD - Source Address Modulo. + * 0b00000..Source address modulo feature is disabled + */ #define DMA_ATTR_SMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_SMOD_SHIFT)) & DMA_ATTR_SMOD_MASK) +/*! @} */ /* The count of DMA_ATTR */ #define DMA_ATTR_COUNT (16U) /*! @name NBYTES_MLNO - TCD Minor Byte Count (Minor Loop Disabled) */ +/*! @{ */ #define DMA_NBYTES_MLNO_NBYTES_MASK (0xFFFFFFFFU) #define DMA_NBYTES_MLNO_NBYTES_SHIFT (0U) #define DMA_NBYTES_MLNO_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLNO_NBYTES_SHIFT)) & DMA_NBYTES_MLNO_NBYTES_MASK) +/*! @} */ /* The count of DMA_NBYTES_MLNO */ #define DMA_NBYTES_MLNO_COUNT (16U) /*! @name NBYTES_MLOFFNO - TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled) */ +/*! @{ */ #define DMA_NBYTES_MLOFFNO_NBYTES_MASK (0x3FFFFFFFU) #define DMA_NBYTES_MLOFFNO_NBYTES_SHIFT (0U) #define DMA_NBYTES_MLOFFNO_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_NBYTES_SHIFT)) & DMA_NBYTES_MLOFFNO_NBYTES_MASK) #define DMA_NBYTES_MLOFFNO_DMLOE_MASK (0x40000000U) #define DMA_NBYTES_MLOFFNO_DMLOE_SHIFT (30U) +/*! DMLOE - Destination Minor Loop Offset enable + * 0b0..The minor loop offset is not applied to the DADDR + * 0b1..The minor loop offset is applied to the DADDR + */ #define DMA_NBYTES_MLOFFNO_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_DMLOE_SHIFT)) & DMA_NBYTES_MLOFFNO_DMLOE_MASK) #define DMA_NBYTES_MLOFFNO_SMLOE_MASK (0x80000000U) #define DMA_NBYTES_MLOFFNO_SMLOE_SHIFT (31U) +/*! SMLOE - Source Minor Loop Offset Enable + * 0b0..The minor loop offset is not applied to the SADDR + * 0b1..The minor loop offset is applied to the SADDR + */ #define DMA_NBYTES_MLOFFNO_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_SMLOE_SHIFT)) & DMA_NBYTES_MLOFFNO_SMLOE_MASK) +/*! @} */ /* The count of DMA_NBYTES_MLOFFNO */ #define DMA_NBYTES_MLOFFNO_COUNT (16U) /*! @name NBYTES_MLOFFYES - TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled) */ +/*! @{ */ #define DMA_NBYTES_MLOFFYES_NBYTES_MASK (0x3FFU) #define DMA_NBYTES_MLOFFYES_NBYTES_SHIFT (0U) #define DMA_NBYTES_MLOFFYES_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_NBYTES_SHIFT)) & DMA_NBYTES_MLOFFYES_NBYTES_MASK) @@ -4415,50 +7898,72 @@ typedef struct { #define DMA_NBYTES_MLOFFYES_MLOFF(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_MLOFF_SHIFT)) & DMA_NBYTES_MLOFFYES_MLOFF_MASK) #define DMA_NBYTES_MLOFFYES_DMLOE_MASK (0x40000000U) #define DMA_NBYTES_MLOFFYES_DMLOE_SHIFT (30U) +/*! DMLOE - Destination Minor Loop Offset enable + * 0b0..The minor loop offset is not applied to the DADDR + * 0b1..The minor loop offset is applied to the DADDR + */ #define DMA_NBYTES_MLOFFYES_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_DMLOE_SHIFT)) & DMA_NBYTES_MLOFFYES_DMLOE_MASK) #define DMA_NBYTES_MLOFFYES_SMLOE_MASK (0x80000000U) #define DMA_NBYTES_MLOFFYES_SMLOE_SHIFT (31U) +/*! SMLOE - Source Minor Loop Offset Enable + * 0b0..The minor loop offset is not applied to the SADDR + * 0b1..The minor loop offset is applied to the SADDR + */ #define DMA_NBYTES_MLOFFYES_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_SMLOE_SHIFT)) & DMA_NBYTES_MLOFFYES_SMLOE_MASK) +/*! @} */ /* The count of DMA_NBYTES_MLOFFYES */ #define DMA_NBYTES_MLOFFYES_COUNT (16U) /*! @name SLAST - TCD Last Source Address Adjustment */ +/*! @{ */ #define DMA_SLAST_SLAST_MASK (0xFFFFFFFFU) #define DMA_SLAST_SLAST_SHIFT (0U) #define DMA_SLAST_SLAST(x) (((uint32_t)(((uint32_t)(x)) << DMA_SLAST_SLAST_SHIFT)) & DMA_SLAST_SLAST_MASK) +/*! @} */ /* The count of DMA_SLAST */ #define DMA_SLAST_COUNT (16U) /*! @name DADDR - TCD Destination Address */ +/*! @{ */ #define DMA_DADDR_DADDR_MASK (0xFFFFFFFFU) #define DMA_DADDR_DADDR_SHIFT (0U) #define DMA_DADDR_DADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_DADDR_DADDR_SHIFT)) & DMA_DADDR_DADDR_MASK) +/*! @} */ /* The count of DMA_DADDR */ #define DMA_DADDR_COUNT (16U) /*! @name DOFF - TCD Signed Destination Address Offset */ +/*! @{ */ #define DMA_DOFF_DOFF_MASK (0xFFFFU) #define DMA_DOFF_DOFF_SHIFT (0U) #define DMA_DOFF_DOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_DOFF_DOFF_SHIFT)) & DMA_DOFF_DOFF_MASK) +/*! @} */ /* The count of DMA_DOFF */ #define DMA_DOFF_COUNT (16U) /*! @name CITER_ELINKNO - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) */ +/*! @{ */ #define DMA_CITER_ELINKNO_CITER_MASK (0x7FFFU) #define DMA_CITER_ELINKNO_CITER_SHIFT (0U) #define DMA_CITER_ELINKNO_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKNO_CITER_SHIFT)) & DMA_CITER_ELINKNO_CITER_MASK) #define DMA_CITER_ELINKNO_ELINK_MASK (0x8000U) #define DMA_CITER_ELINKNO_ELINK_SHIFT (15U) +/*! ELINK - Enable channel-to-channel linking on minor-loop complete + * 0b0..The channel-to-channel linking is disabled + * 0b1..The channel-to-channel linking is enabled + */ #define DMA_CITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKNO_ELINK_SHIFT)) & DMA_CITER_ELINKNO_ELINK_MASK) +/*! @} */ /* The count of DMA_CITER_ELINKNO */ #define DMA_CITER_ELINKNO_COUNT (16U) /*! @name CITER_ELINKYES - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) */ +/*! @{ */ #define DMA_CITER_ELINKYES_CITER_MASK (0x1FFU) #define DMA_CITER_ELINKYES_CITER_SHIFT (0U) #define DMA_CITER_ELINKYES_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_CITER_SHIFT)) & DMA_CITER_ELINKYES_CITER_MASK) @@ -4467,37 +7972,69 @@ typedef struct { #define DMA_CITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_LINKCH_SHIFT)) & DMA_CITER_ELINKYES_LINKCH_MASK) #define DMA_CITER_ELINKYES_ELINK_MASK (0x8000U) #define DMA_CITER_ELINKYES_ELINK_SHIFT (15U) +/*! ELINK - Enable channel-to-channel linking on minor-loop complete + * 0b0..The channel-to-channel linking is disabled + * 0b1..The channel-to-channel linking is enabled + */ #define DMA_CITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_ELINK_SHIFT)) & DMA_CITER_ELINKYES_ELINK_MASK) +/*! @} */ /* The count of DMA_CITER_ELINKYES */ #define DMA_CITER_ELINKYES_COUNT (16U) /*! @name DLAST_SGA - TCD Last Destination Address Adjustment/Scatter Gather Address */ +/*! @{ */ #define DMA_DLAST_SGA_DLASTSGA_MASK (0xFFFFFFFFU) #define DMA_DLAST_SGA_DLASTSGA_SHIFT (0U) #define DMA_DLAST_SGA_DLASTSGA(x) (((uint32_t)(((uint32_t)(x)) << DMA_DLAST_SGA_DLASTSGA_SHIFT)) & DMA_DLAST_SGA_DLASTSGA_MASK) +/*! @} */ /* The count of DMA_DLAST_SGA */ #define DMA_DLAST_SGA_COUNT (16U) /*! @name CSR - TCD Control and Status */ +/*! @{ */ #define DMA_CSR_START_MASK (0x1U) #define DMA_CSR_START_SHIFT (0U) +/*! START - Channel Start + * 0b0..The channel is not explicitly started + * 0b1..The channel is explicitly started via a software initiated service request + */ #define DMA_CSR_START(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_START_SHIFT)) & DMA_CSR_START_MASK) #define DMA_CSR_INTMAJOR_MASK (0x2U) #define DMA_CSR_INTMAJOR_SHIFT (1U) +/*! INTMAJOR - Enable an interrupt when major iteration count completes + * 0b0..The end-of-major loop interrupt is disabled + * 0b1..The end-of-major loop interrupt is enabled + */ #define DMA_CSR_INTMAJOR(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_INTMAJOR_SHIFT)) & DMA_CSR_INTMAJOR_MASK) #define DMA_CSR_INTHALF_MASK (0x4U) #define DMA_CSR_INTHALF_SHIFT (2U) +/*! INTHALF - Enable an interrupt when major counter is half complete. + * 0b0..The half-point interrupt is disabled + * 0b1..The half-point interrupt is enabled + */ #define DMA_CSR_INTHALF(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_INTHALF_SHIFT)) & DMA_CSR_INTHALF_MASK) #define DMA_CSR_DREQ_MASK (0x8U) #define DMA_CSR_DREQ_SHIFT (3U) +/*! DREQ - Disable Request + * 0b0..The channel's ERQ bit is not affected + * 0b1..The channel's ERQ bit is cleared when the major loop is complete + */ #define DMA_CSR_DREQ(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_DREQ_SHIFT)) & DMA_CSR_DREQ_MASK) #define DMA_CSR_ESG_MASK (0x10U) #define DMA_CSR_ESG_SHIFT (4U) +/*! ESG - Enable Scatter/Gather Processing + * 0b0..The current channel's TCD is normal format. + * 0b1..The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. + */ #define DMA_CSR_ESG(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_ESG_SHIFT)) & DMA_CSR_ESG_MASK) #define DMA_CSR_MAJORELINK_MASK (0x20U) #define DMA_CSR_MAJORELINK_SHIFT (5U) +/*! MAJORELINK - Enable channel-to-channel linking on major loop complete + * 0b0..The channel-to-channel linking is disabled + * 0b1..The channel-to-channel linking is enabled + */ #define DMA_CSR_MAJORELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_MAJORELINK_SHIFT)) & DMA_CSR_MAJORELINK_MASK) #define DMA_CSR_ACTIVE_MASK (0x40U) #define DMA_CSR_ACTIVE_SHIFT (6U) @@ -4510,23 +8047,37 @@ typedef struct { #define DMA_CSR_MAJORLINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_MAJORLINKCH_SHIFT)) & DMA_CSR_MAJORLINKCH_MASK) #define DMA_CSR_BWC_MASK (0xC000U) #define DMA_CSR_BWC_SHIFT (14U) +/*! BWC - Bandwidth Control + * 0b00..No eDMA engine stalls + * 0b01..Reserved + * 0b10..eDMA engine stalls for 4 cycles after each r/w + * 0b11..eDMA engine stalls for 8 cycles after each r/w + */ #define DMA_CSR_BWC(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_BWC_SHIFT)) & DMA_CSR_BWC_MASK) +/*! @} */ /* The count of DMA_CSR */ #define DMA_CSR_COUNT (16U) /*! @name BITER_ELINKNO - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) */ +/*! @{ */ #define DMA_BITER_ELINKNO_BITER_MASK (0x7FFFU) #define DMA_BITER_ELINKNO_BITER_SHIFT (0U) #define DMA_BITER_ELINKNO_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKNO_BITER_SHIFT)) & DMA_BITER_ELINKNO_BITER_MASK) #define DMA_BITER_ELINKNO_ELINK_MASK (0x8000U) #define DMA_BITER_ELINKNO_ELINK_SHIFT (15U) +/*! ELINK - Enables channel-to-channel linking on minor loop complete + * 0b0..The channel-to-channel linking is disabled + * 0b1..The channel-to-channel linking is enabled + */ #define DMA_BITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKNO_ELINK_SHIFT)) & DMA_BITER_ELINKNO_ELINK_MASK) +/*! @} */ /* The count of DMA_BITER_ELINKNO */ #define DMA_BITER_ELINKNO_COUNT (16U) /*! @name BITER_ELINKYES - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) */ +/*! @{ */ #define DMA_BITER_ELINKYES_BITER_MASK (0x1FFU) #define DMA_BITER_ELINKYES_BITER_SHIFT (0U) #define DMA_BITER_ELINKYES_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_BITER_SHIFT)) & DMA_BITER_ELINKYES_BITER_MASK) @@ -4535,7 +8086,12 @@ typedef struct { #define DMA_BITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_LINKCH_SHIFT)) & DMA_BITER_ELINKYES_LINKCH_MASK) #define DMA_BITER_ELINKYES_ELINK_MASK (0x8000U) #define DMA_BITER_ELINKYES_ELINK_SHIFT (15U) +/*! ELINK - Enables channel-to-channel linking on minor loop complete + * 0b0..The channel-to-channel linking is disabled + * 0b1..The channel-to-channel linking is enabled + */ #define DMA_BITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_ELINK_SHIFT)) & DMA_BITER_ELINKYES_ELINK_MASK) +/*! @} */ /* The count of DMA_BITER_ELINKYES */ #define DMA_BITER_ELINKYES_COUNT (16U) @@ -4588,15 +8144,90 @@ typedef struct { */ /*! @name CHCFG - Channel Configuration register */ +/*! @{ */ #define DMAMUX_CHCFG_SOURCE_MASK (0x3FU) #define DMAMUX_CHCFG_SOURCE_SHIFT (0U) +/*! SOURCE - DMA Channel Source (Slot) + * 0b000000..Disable_Signal + * 0b000010..UART0_Rx_Signal + * 0b000011..UART0_Tx_Signal + * 0b000100..UART1_Rx_Signal + * 0b000101..UART1_Tx_Signal + * 0b000110..UART2_Rx_Signal + * 0b000111..UART2_Tx_Signal + * 0b001000..UART3_Rx_Signal + * 0b001001..UART3_Tx_Signal + * 0b001010..UART4_Signal + * 0b001011..UART5_Signal + * 0b001100..I2S0_Rx_Signal + * 0b001101..I2S0_Tx_Signal + * 0b001110..SPI0_Rx_Signal + * 0b001111..SPI0_Tx_Signal + * 0b010000..SPI1_Signal + * 0b010001..SPI2_Signal + * 0b010010..I2C0_Signal + * 0b010011..I2C1_I2C2_Signal + * 0b010100..FTM0_Channel0_Signal + * 0b010101..FTM0_Channel1_Signal + * 0b010110..FTM0_Channel2_Signal + * 0b010111..FTM0_Channel3_Signal + * 0b011000..FTM0_Channel4_Signal + * 0b011001..FTM0_Channel5_Signal + * 0b011010..FTM0_Channel6_Signal + * 0b011011..FTM0_Channel7_Signal + * 0b011100..FTM1_Channel0_Signal + * 0b011101..FTM1_Channel1_Signal + * 0b011110..FTM2_Channel0_Signal + * 0b011111..FTM2_Channel1_Signal + * 0b100000..FTM3_Channel0_Signal + * 0b100001..FTM3_Channel1_Signal + * 0b100010..FTM3_Channel2_Signal + * 0b100011..FTM3_Channel3_Signal + * 0b100100..FTM3_Channel4_Signal + * 0b100101..FTM3_Channel5_Signal + * 0b100110..FTM3_Channel6_Signal + * 0b100111..FTM3_Channel7_Signal + * 0b101000..ADC0_Signal + * 0b101001..ADC1_Signal + * 0b101010..CMP0_Signal + * 0b101011..CMP1_Signal + * 0b101100..CMP2_Signal + * 0b101101..DAC0_Signal + * 0b101110..DAC1_Signal + * 0b101111..CMT_Signal + * 0b110000..PDB_Signal + * 0b110001..PortA_Signal + * 0b110010..PortB_Signal + * 0b110011..PortC_Signal + * 0b110100..PortD_Signal + * 0b110101..PortE_Signal + * 0b110110..IEEE1588Timer0_Signal + * 0b110111..IEEE1588Timer1_Signal + * 0b111000..IEEE1588Timer2_Signal + * 0b111001..IEEE1588Timer3_Signal + * 0b111010..AlwaysOn58_Signal + * 0b111011..AlwaysOn59_Signal + * 0b111100..AlwaysOn60_Signal + * 0b111101..AlwaysOn61_Signal + * 0b111110..AlwaysOn62_Signal + * 0b111111..AlwaysOn63_Signal + */ #define DMAMUX_CHCFG_SOURCE(x) (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_SOURCE_SHIFT)) & DMAMUX_CHCFG_SOURCE_MASK) #define DMAMUX_CHCFG_TRIG_MASK (0x40U) #define DMAMUX_CHCFG_TRIG_SHIFT (6U) +/*! TRIG - DMA Channel Trigger Enable + * 0b0..Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode) + * 0b1..Triggering is enabled. If triggering is enabled and ENBL is set, the DMAMUX is in Periodic Trigger mode. + */ #define DMAMUX_CHCFG_TRIG(x) (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_TRIG_SHIFT)) & DMAMUX_CHCFG_TRIG_MASK) #define DMAMUX_CHCFG_ENBL_MASK (0x80U) #define DMAMUX_CHCFG_ENBL_SHIFT (7U) +/*! ENBL - DMA Channel Enable + * 0b0..DMA channel is disabled. This mode is primarily used during configuration of the DMAMux. The DMA has separate channel enables/disables, which should be used to disable or reconfigure a DMA channel. + * 0b1..DMA channel is enabled + */ #define DMAMUX_CHCFG_ENBL(x) (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_ENBL_SHIFT)) & DMAMUX_CHCFG_ENBL_MASK) +/*! @} */ /* The count of DMAMUX_CHCFG */ #define DMAMUX_CHCFG_COUNT (16U) @@ -4759,6 +8390,7 @@ typedef struct { */ /*! @name EIR - Interrupt Event Register */ +/*! @{ */ #define ENET_EIR_TS_TIMER_MASK (0x8000U) #define ENET_EIR_TS_TIMER_SHIFT (15U) #define ENET_EIR_TS_TIMER(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TS_TIMER_SHIFT)) & ENET_EIR_TS_TIMER_MASK) @@ -4807,8 +8439,10 @@ typedef struct { #define ENET_EIR_BABR_MASK (0x40000000U) #define ENET_EIR_BABR_SHIFT (30U) #define ENET_EIR_BABR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_BABR_SHIFT)) & ENET_EIR_BABR_MASK) +/*! @} */ /*! @name EIMR - Interrupt Mask Register */ +/*! @{ */ #define ENET_EIMR_TS_TIMER_MASK (0x8000U) #define ENET_EIMR_TS_TIMER_SHIFT (15U) #define ENET_EIMR_TS_TIMER(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TS_TIMER_SHIFT)) & ENET_EIMR_TS_TIMER_MASK) @@ -4844,57 +8478,109 @@ typedef struct { #define ENET_EIMR_RXF(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXF_SHIFT)) & ENET_EIMR_RXF_MASK) #define ENET_EIMR_TXB_MASK (0x4000000U) #define ENET_EIMR_TXB_SHIFT (26U) +/*! TXB - TXB Interrupt Mask + * 0b0..The corresponding interrupt source is masked. + * 0b1..The corresponding interrupt source is not masked. + */ #define ENET_EIMR_TXB(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXB_SHIFT)) & ENET_EIMR_TXB_MASK) #define ENET_EIMR_TXF_MASK (0x8000000U) #define ENET_EIMR_TXF_SHIFT (27U) +/*! TXF - TXF Interrupt Mask + * 0b0..The corresponding interrupt source is masked. + * 0b1..The corresponding interrupt source is not masked. + */ #define ENET_EIMR_TXF(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXF_SHIFT)) & ENET_EIMR_TXF_MASK) #define ENET_EIMR_GRA_MASK (0x10000000U) #define ENET_EIMR_GRA_SHIFT (28U) +/*! GRA - GRA Interrupt Mask + * 0b0..The corresponding interrupt source is masked. + * 0b1..The corresponding interrupt source is not masked. + */ #define ENET_EIMR_GRA(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_GRA_SHIFT)) & ENET_EIMR_GRA_MASK) #define ENET_EIMR_BABT_MASK (0x20000000U) #define ENET_EIMR_BABT_SHIFT (29U) +/*! BABT - BABT Interrupt Mask + * 0b0..The corresponding interrupt source is masked. + * 0b1..The corresponding interrupt source is not masked. + */ #define ENET_EIMR_BABT(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_BABT_SHIFT)) & ENET_EIMR_BABT_MASK) #define ENET_EIMR_BABR_MASK (0x40000000U) #define ENET_EIMR_BABR_SHIFT (30U) +/*! BABR - BABR Interrupt Mask + * 0b0..The corresponding interrupt source is masked. + * 0b1..The corresponding interrupt source is not masked. + */ #define ENET_EIMR_BABR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_BABR_SHIFT)) & ENET_EIMR_BABR_MASK) +/*! @} */ /*! @name RDAR - Receive Descriptor Active Register */ +/*! @{ */ #define ENET_RDAR_RDAR_MASK (0x1000000U) #define ENET_RDAR_RDAR_SHIFT (24U) #define ENET_RDAR_RDAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_RDAR_RDAR_SHIFT)) & ENET_RDAR_RDAR_MASK) +/*! @} */ /*! @name TDAR - Transmit Descriptor Active Register */ +/*! @{ */ #define ENET_TDAR_TDAR_MASK (0x1000000U) #define ENET_TDAR_TDAR_SHIFT (24U) #define ENET_TDAR_TDAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_TDAR_TDAR_SHIFT)) & ENET_TDAR_TDAR_MASK) +/*! @} */ /*! @name ECR - Ethernet Control Register */ +/*! @{ */ #define ENET_ECR_RESET_MASK (0x1U) #define ENET_ECR_RESET_SHIFT (0U) #define ENET_ECR_RESET(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_RESET_SHIFT)) & ENET_ECR_RESET_MASK) #define ENET_ECR_ETHEREN_MASK (0x2U) #define ENET_ECR_ETHEREN_SHIFT (1U) +/*! ETHEREN - Ethernet Enable + * 0b0..Reception immediately stops and transmission stops after a bad CRC is appended to any currently transmitted frame. + * 0b1..MAC is enabled, and reception and transmission are possible. + */ #define ENET_ECR_ETHEREN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_ETHEREN_SHIFT)) & ENET_ECR_ETHEREN_MASK) #define ENET_ECR_MAGICEN_MASK (0x4U) #define ENET_ECR_MAGICEN_SHIFT (2U) +/*! MAGICEN - Magic Packet Detection Enable + * 0b0..Magic detection logic disabled. + * 0b1..The MAC core detects magic packets and asserts EIR[WAKEUP] when a frame is detected. + */ #define ENET_ECR_MAGICEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_MAGICEN_SHIFT)) & ENET_ECR_MAGICEN_MASK) #define ENET_ECR_SLEEP_MASK (0x8U) #define ENET_ECR_SLEEP_SHIFT (3U) +/*! SLEEP - Sleep Mode Enable + * 0b0..Normal operating mode. + * 0b1..Sleep mode. + */ #define ENET_ECR_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_SLEEP_SHIFT)) & ENET_ECR_SLEEP_MASK) #define ENET_ECR_EN1588_MASK (0x10U) #define ENET_ECR_EN1588_SHIFT (4U) +/*! EN1588 - EN1588 Enable + * 0b0..Legacy FEC buffer descriptors and functions enabled. + * 0b1..Enhanced frame time-stamping functions enabled. + */ #define ENET_ECR_EN1588(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_EN1588_SHIFT)) & ENET_ECR_EN1588_MASK) #define ENET_ECR_DBGEN_MASK (0x40U) #define ENET_ECR_DBGEN_SHIFT (6U) +/*! DBGEN - Debug Enable + * 0b0..MAC continues operation in debug mode. + * 0b1..MAC enters hardware freeze mode when the processor is in debug mode. + */ #define ENET_ECR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_DBGEN_SHIFT)) & ENET_ECR_DBGEN_MASK) #define ENET_ECR_STOPEN_MASK (0x80U) #define ENET_ECR_STOPEN_SHIFT (7U) #define ENET_ECR_STOPEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_STOPEN_SHIFT)) & ENET_ECR_STOPEN_MASK) #define ENET_ECR_DBSWP_MASK (0x100U) #define ENET_ECR_DBSWP_SHIFT (8U) +/*! DBSWP - Descriptor Byte Swapping Enable + * 0b0..The buffer descriptor bytes are not swapped to support big-endian devices. + * 0b1..The buffer descriptor bytes are swapped to support little-endian devices. + */ #define ENET_ECR_DBSWP(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_DBSWP_SHIFT)) & ENET_ECR_DBSWP_MASK) +/*! @} */ /*! @name MMFR - MII Management Frame Register */ +/*! @{ */ #define ENET_MMFR_DATA_MASK (0xFFFFU) #define ENET_MMFR_DATA_SHIFT (0U) #define ENET_MMFR_DATA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_DATA_SHIFT)) & ENET_MMFR_DATA_MASK) @@ -4909,23 +8595,43 @@ typedef struct { #define ENET_MMFR_PA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_PA_SHIFT)) & ENET_MMFR_PA_MASK) #define ENET_MMFR_OP_MASK (0x30000000U) #define ENET_MMFR_OP_SHIFT (28U) +/*! OP - Operation Code + * 0b00..Write frame operation, but not MII compliant. + * 0b01..Write frame operation for a valid MII management frame. + * 0b10..Read frame operation for a valid MII management frame. + * 0b11..Read frame operation, but not MII compliant. + */ #define ENET_MMFR_OP(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_OP_SHIFT)) & ENET_MMFR_OP_MASK) #define ENET_MMFR_ST_MASK (0xC0000000U) #define ENET_MMFR_ST_SHIFT (30U) #define ENET_MMFR_ST(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_ST_SHIFT)) & ENET_MMFR_ST_MASK) +/*! @} */ /*! @name MSCR - MII Speed Control Register */ +/*! @{ */ #define ENET_MSCR_MII_SPEED_MASK (0x7EU) #define ENET_MSCR_MII_SPEED_SHIFT (1U) #define ENET_MSCR_MII_SPEED(x) (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_MII_SPEED_SHIFT)) & ENET_MSCR_MII_SPEED_MASK) #define ENET_MSCR_DIS_PRE_MASK (0x80U) #define ENET_MSCR_DIS_PRE_SHIFT (7U) +/*! DIS_PRE - Disable Preamble + * 0b0..Preamble enabled. + * 0b1..Preamble (32 ones) is not prepended to the MII management frame. + */ #define ENET_MSCR_DIS_PRE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_DIS_PRE_SHIFT)) & ENET_MSCR_DIS_PRE_MASK) #define ENET_MSCR_HOLDTIME_MASK (0x700U) #define ENET_MSCR_HOLDTIME_SHIFT (8U) +/*! HOLDTIME - Hold time On MDIO Output + * 0b000..1 internal module clock cycle + * 0b001..2 internal module clock cycles + * 0b010..3 internal module clock cycles + * 0b111..8 internal module clock cycles + */ #define ENET_MSCR_HOLDTIME(x) (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_HOLDTIME_SHIFT)) & ENET_MSCR_HOLDTIME_MASK) +/*! @} */ /*! @name MIBC - MIB Control Register */ +/*! @{ */ #define ENET_MIBC_MIB_CLEAR_MASK (0x20000000U) #define ENET_MIBC_MIB_CLEAR_SHIFT (29U) #define ENET_MIBC_MIB_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_CLEAR_SHIFT)) & ENET_MIBC_MIB_CLEAR_MASK) @@ -4935,19 +8641,37 @@ typedef struct { #define ENET_MIBC_MIB_DIS_MASK (0x80000000U) #define ENET_MIBC_MIB_DIS_SHIFT (31U) #define ENET_MIBC_MIB_DIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_DIS_SHIFT)) & ENET_MIBC_MIB_DIS_MASK) +/*! @} */ /*! @name RCR - Receive Control Register */ +/*! @{ */ #define ENET_RCR_LOOP_MASK (0x1U) #define ENET_RCR_LOOP_SHIFT (0U) +/*! LOOP - Internal Loopback + * 0b0..Loopback disabled. + * 0b1..Transmitted frames are looped back internal to the device and transmit MII output signals are not asserted. DRT must be cleared. + */ #define ENET_RCR_LOOP(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_LOOP_SHIFT)) & ENET_RCR_LOOP_MASK) #define ENET_RCR_DRT_MASK (0x2U) #define ENET_RCR_DRT_SHIFT (1U) +/*! DRT - Disable Receive On Transmit + * 0b0..Receive path operates independently of transmit. Used for full-duplex or to monitor transmit activity in half-duplex mode. + * 0b1..Disable reception of frames while transmitting. Normally used for half-duplex mode. + */ #define ENET_RCR_DRT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_DRT_SHIFT)) & ENET_RCR_DRT_MASK) #define ENET_RCR_MII_MODE_MASK (0x4U) #define ENET_RCR_MII_MODE_SHIFT (2U) +/*! MII_MODE - Media Independent Interface Mode + * 0b0..Reserved. + * 0b1..MII or RMII mode, as indicated by the RMII_MODE field. + */ #define ENET_RCR_MII_MODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_MII_MODE_SHIFT)) & ENET_RCR_MII_MODE_MASK) #define ENET_RCR_PROM_MASK (0x8U) #define ENET_RCR_PROM_SHIFT (3U) +/*! PROM - Promiscuous Mode + * 0b0..Disabled. + * 0b1..Enabled. + */ #define ENET_RCR_PROM(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PROM_SHIFT)) & ENET_RCR_PROM_MASK) #define ENET_RCR_BC_REJ_MASK (0x10U) #define ENET_RCR_BC_REJ_SHIFT (4U) @@ -4957,33 +8681,63 @@ typedef struct { #define ENET_RCR_FCE(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_FCE_SHIFT)) & ENET_RCR_FCE_MASK) #define ENET_RCR_RMII_MODE_MASK (0x100U) #define ENET_RCR_RMII_MODE_SHIFT (8U) +/*! RMII_MODE - RMII Mode Enable + * 0b0..MAC configured for MII mode. + * 0b1..MAC configured for RMII operation. + */ #define ENET_RCR_RMII_MODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_RMII_MODE_SHIFT)) & ENET_RCR_RMII_MODE_MASK) #define ENET_RCR_RMII_10T_MASK (0x200U) #define ENET_RCR_RMII_10T_SHIFT (9U) +/*! RMII_10T + * 0b0..100 Mbps operation. + * 0b1..10 Mbps operation. + */ #define ENET_RCR_RMII_10T(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_RMII_10T_SHIFT)) & ENET_RCR_RMII_10T_MASK) #define ENET_RCR_PADEN_MASK (0x1000U) #define ENET_RCR_PADEN_SHIFT (12U) +/*! PADEN - Enable Frame Padding Remove On Receive + * 0b0..No padding is removed on receive by the MAC. + * 0b1..Padding is removed from received frames. + */ #define ENET_RCR_PADEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PADEN_SHIFT)) & ENET_RCR_PADEN_MASK) #define ENET_RCR_PAUFWD_MASK (0x2000U) #define ENET_RCR_PAUFWD_SHIFT (13U) +/*! PAUFWD - Terminate/Forward Pause Frames + * 0b0..Pause frames are terminated and discarded in the MAC. + * 0b1..Pause frames are forwarded to the user application. + */ #define ENET_RCR_PAUFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PAUFWD_SHIFT)) & ENET_RCR_PAUFWD_MASK) #define ENET_RCR_CRCFWD_MASK (0x4000U) #define ENET_RCR_CRCFWD_SHIFT (14U) +/*! CRCFWD - Terminate/Forward Received CRC + * 0b0..The CRC field of received frames is transmitted to the user application. + * 0b1..The CRC field is stripped from the frame. + */ #define ENET_RCR_CRCFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_CRCFWD_SHIFT)) & ENET_RCR_CRCFWD_MASK) #define ENET_RCR_CFEN_MASK (0x8000U) #define ENET_RCR_CFEN_SHIFT (15U) +/*! CFEN - MAC Control Frame Enable + * 0b0..MAC control frames with any opcode other than 0x0001 (pause frame) are accepted and forwarded to the client interface. + * 0b1..MAC control frames with any opcode other than 0x0001 (pause frame) are silently discarded. + */ #define ENET_RCR_CFEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_CFEN_SHIFT)) & ENET_RCR_CFEN_MASK) #define ENET_RCR_MAX_FL_MASK (0x3FFF0000U) #define ENET_RCR_MAX_FL_SHIFT (16U) #define ENET_RCR_MAX_FL(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_MAX_FL_SHIFT)) & ENET_RCR_MAX_FL_MASK) #define ENET_RCR_NLC_MASK (0x40000000U) #define ENET_RCR_NLC_SHIFT (30U) +/*! NLC - Payload Length Check Disable + * 0b0..The payload length check is disabled. + * 0b1..The core checks the frame's payload length with the frame length/type field. Errors are indicated in the EIR[PLC] field. + */ #define ENET_RCR_NLC(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_NLC_SHIFT)) & ENET_RCR_NLC_MASK) #define ENET_RCR_GRS_MASK (0x80000000U) #define ENET_RCR_GRS_SHIFT (31U) #define ENET_RCR_GRS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_GRS_SHIFT)) & ENET_RCR_GRS_MASK) +/*! @} */ /*! @name TCR - Transmit Control Register */ +/*! @{ */ #define ENET_TCR_GTS_MASK (0x1U) #define ENET_TCR_GTS_SHIFT (0U) #define ENET_TCR_GTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_GTS_SHIFT)) & ENET_TCR_GTS_MASK) @@ -4992,504 +8746,803 @@ typedef struct { #define ENET_TCR_FDEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_FDEN_SHIFT)) & ENET_TCR_FDEN_MASK) #define ENET_TCR_TFC_PAUSE_MASK (0x8U) #define ENET_TCR_TFC_PAUSE_SHIFT (3U) +/*! TFC_PAUSE - Transmit Frame Control Pause + * 0b0..No PAUSE frame transmitted. + * 0b1..The MAC stops transmission of data frames after the current transmission is complete. + */ #define ENET_TCR_TFC_PAUSE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_TFC_PAUSE_SHIFT)) & ENET_TCR_TFC_PAUSE_MASK) #define ENET_TCR_RFC_PAUSE_MASK (0x10U) #define ENET_TCR_RFC_PAUSE_SHIFT (4U) #define ENET_TCR_RFC_PAUSE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_RFC_PAUSE_SHIFT)) & ENET_TCR_RFC_PAUSE_MASK) #define ENET_TCR_ADDSEL_MASK (0xE0U) #define ENET_TCR_ADDSEL_SHIFT (5U) +/*! ADDSEL - Source MAC Address Select On Transmit + * 0b000..Node MAC address programmed on PADDR1/2 registers. + * 0b100..Reserved. + * 0b101..Reserved. + * 0b110..Reserved. + */ #define ENET_TCR_ADDSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_ADDSEL_SHIFT)) & ENET_TCR_ADDSEL_MASK) #define ENET_TCR_ADDINS_MASK (0x100U) #define ENET_TCR_ADDINS_SHIFT (8U) +/*! ADDINS - Set MAC Address On Transmit + * 0b0..The source MAC address is not modified by the MAC. + * 0b1..The MAC overwrites the source MAC address with the programmed MAC address according to ADDSEL. + */ #define ENET_TCR_ADDINS(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_ADDINS_SHIFT)) & ENET_TCR_ADDINS_MASK) #define ENET_TCR_CRCFWD_MASK (0x200U) #define ENET_TCR_CRCFWD_SHIFT (9U) +/*! CRCFWD - Forward Frame From Application With CRC + * 0b0..TxBD[TC] controls whether the frame has a CRC from the application. + * 0b1..The transmitter does not append any CRC to transmitted frames, as it is expecting a frame with CRC from the application. + */ #define ENET_TCR_CRCFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_CRCFWD_SHIFT)) & ENET_TCR_CRCFWD_MASK) +/*! @} */ /*! @name PALR - Physical Address Lower Register */ +/*! @{ */ #define ENET_PALR_PADDR1_MASK (0xFFFFFFFFU) #define ENET_PALR_PADDR1_SHIFT (0U) #define ENET_PALR_PADDR1(x) (((uint32_t)(((uint32_t)(x)) << ENET_PALR_PADDR1_SHIFT)) & ENET_PALR_PADDR1_MASK) +/*! @} */ /*! @name PAUR - Physical Address Upper Register */ +/*! @{ */ #define ENET_PAUR_TYPE_MASK (0xFFFFU) #define ENET_PAUR_TYPE_SHIFT (0U) #define ENET_PAUR_TYPE(x) (((uint32_t)(((uint32_t)(x)) << ENET_PAUR_TYPE_SHIFT)) & ENET_PAUR_TYPE_MASK) #define ENET_PAUR_PADDR2_MASK (0xFFFF0000U) #define ENET_PAUR_PADDR2_SHIFT (16U) #define ENET_PAUR_PADDR2(x) (((uint32_t)(((uint32_t)(x)) << ENET_PAUR_PADDR2_SHIFT)) & ENET_PAUR_PADDR2_MASK) +/*! @} */ /*! @name OPD - Opcode/Pause Duration Register */ +/*! @{ */ #define ENET_OPD_PAUSE_DUR_MASK (0xFFFFU) #define ENET_OPD_PAUSE_DUR_SHIFT (0U) #define ENET_OPD_PAUSE_DUR(x) (((uint32_t)(((uint32_t)(x)) << ENET_OPD_PAUSE_DUR_SHIFT)) & ENET_OPD_PAUSE_DUR_MASK) #define ENET_OPD_OPCODE_MASK (0xFFFF0000U) #define ENET_OPD_OPCODE_SHIFT (16U) #define ENET_OPD_OPCODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_OPD_OPCODE_SHIFT)) & ENET_OPD_OPCODE_MASK) +/*! @} */ /*! @name IAUR - Descriptor Individual Upper Address Register */ +/*! @{ */ #define ENET_IAUR_IADDR1_MASK (0xFFFFFFFFU) #define ENET_IAUR_IADDR1_SHIFT (0U) #define ENET_IAUR_IADDR1(x) (((uint32_t)(((uint32_t)(x)) << ENET_IAUR_IADDR1_SHIFT)) & ENET_IAUR_IADDR1_MASK) +/*! @} */ /*! @name IALR - Descriptor Individual Lower Address Register */ +/*! @{ */ #define ENET_IALR_IADDR2_MASK (0xFFFFFFFFU) #define ENET_IALR_IADDR2_SHIFT (0U) #define ENET_IALR_IADDR2(x) (((uint32_t)(((uint32_t)(x)) << ENET_IALR_IADDR2_SHIFT)) & ENET_IALR_IADDR2_MASK) +/*! @} */ /*! @name GAUR - Descriptor Group Upper Address Register */ +/*! @{ */ #define ENET_GAUR_GADDR1_MASK (0xFFFFFFFFU) #define ENET_GAUR_GADDR1_SHIFT (0U) #define ENET_GAUR_GADDR1(x) (((uint32_t)(((uint32_t)(x)) << ENET_GAUR_GADDR1_SHIFT)) & ENET_GAUR_GADDR1_MASK) +/*! @} */ /*! @name GALR - Descriptor Group Lower Address Register */ +/*! @{ */ #define ENET_GALR_GADDR2_MASK (0xFFFFFFFFU) #define ENET_GALR_GADDR2_SHIFT (0U) #define ENET_GALR_GADDR2(x) (((uint32_t)(((uint32_t)(x)) << ENET_GALR_GADDR2_SHIFT)) & ENET_GALR_GADDR2_MASK) +/*! @} */ /*! @name TFWR - Transmit FIFO Watermark Register */ +/*! @{ */ #define ENET_TFWR_TFWR_MASK (0x3FU) #define ENET_TFWR_TFWR_SHIFT (0U) +/*! TFWR - Transmit FIFO Write + * 0b000000..64 bytes written. + * 0b000001..64 bytes written. + * 0b000010..128 bytes written. + * 0b000011..192 bytes written. + * 0b111110..3968 bytes written. + * 0b111111..4032 bytes written. + */ #define ENET_TFWR_TFWR(x) (((uint32_t)(((uint32_t)(x)) << ENET_TFWR_TFWR_SHIFT)) & ENET_TFWR_TFWR_MASK) #define ENET_TFWR_STRFWD_MASK (0x100U) #define ENET_TFWR_STRFWD_SHIFT (8U) +/*! STRFWD - Store And Forward Enable + * 0b0..Reset. The transmission start threshold is programmed in TFWR[TFWR]. + * 0b1..Enabled. + */ #define ENET_TFWR_STRFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_TFWR_STRFWD_SHIFT)) & ENET_TFWR_STRFWD_MASK) +/*! @} */ /*! @name RDSR - Receive Descriptor Ring Start Register */ +/*! @{ */ #define ENET_RDSR_R_DES_START_MASK (0xFFFFFFF8U) #define ENET_RDSR_R_DES_START_SHIFT (3U) #define ENET_RDSR_R_DES_START(x) (((uint32_t)(((uint32_t)(x)) << ENET_RDSR_R_DES_START_SHIFT)) & ENET_RDSR_R_DES_START_MASK) +/*! @} */ /*! @name TDSR - Transmit Buffer Descriptor Ring Start Register */ +/*! @{ */ #define ENET_TDSR_X_DES_START_MASK (0xFFFFFFF8U) #define ENET_TDSR_X_DES_START_SHIFT (3U) #define ENET_TDSR_X_DES_START(x) (((uint32_t)(((uint32_t)(x)) << ENET_TDSR_X_DES_START_SHIFT)) & ENET_TDSR_X_DES_START_MASK) +/*! @} */ /*! @name MRBR - Maximum Receive Buffer Size Register */ +/*! @{ */ #define ENET_MRBR_R_BUF_SIZE_MASK (0x3FF0U) #define ENET_MRBR_R_BUF_SIZE_SHIFT (4U) #define ENET_MRBR_R_BUF_SIZE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MRBR_R_BUF_SIZE_SHIFT)) & ENET_MRBR_R_BUF_SIZE_MASK) +/*! @} */ /*! @name RSFL - Receive FIFO Section Full Threshold */ +/*! @{ */ #define ENET_RSFL_RX_SECTION_FULL_MASK (0xFFU) #define ENET_RSFL_RX_SECTION_FULL_SHIFT (0U) #define ENET_RSFL_RX_SECTION_FULL(x) (((uint32_t)(((uint32_t)(x)) << ENET_RSFL_RX_SECTION_FULL_SHIFT)) & ENET_RSFL_RX_SECTION_FULL_MASK) +/*! @} */ /*! @name RSEM - Receive FIFO Section Empty Threshold */ +/*! @{ */ #define ENET_RSEM_RX_SECTION_EMPTY_MASK (0xFFU) #define ENET_RSEM_RX_SECTION_EMPTY_SHIFT (0U) #define ENET_RSEM_RX_SECTION_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_RSEM_RX_SECTION_EMPTY_SHIFT)) & ENET_RSEM_RX_SECTION_EMPTY_MASK) #define ENET_RSEM_STAT_SECTION_EMPTY_MASK (0x1F0000U) #define ENET_RSEM_STAT_SECTION_EMPTY_SHIFT (16U) #define ENET_RSEM_STAT_SECTION_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_RSEM_STAT_SECTION_EMPTY_SHIFT)) & ENET_RSEM_STAT_SECTION_EMPTY_MASK) +/*! @} */ /*! @name RAEM - Receive FIFO Almost Empty Threshold */ +/*! @{ */ #define ENET_RAEM_RX_ALMOST_EMPTY_MASK (0xFFU) #define ENET_RAEM_RX_ALMOST_EMPTY_SHIFT (0U) #define ENET_RAEM_RX_ALMOST_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_RAEM_RX_ALMOST_EMPTY_SHIFT)) & ENET_RAEM_RX_ALMOST_EMPTY_MASK) +/*! @} */ /*! @name RAFL - Receive FIFO Almost Full Threshold */ +/*! @{ */ #define ENET_RAFL_RX_ALMOST_FULL_MASK (0xFFU) #define ENET_RAFL_RX_ALMOST_FULL_SHIFT (0U) #define ENET_RAFL_RX_ALMOST_FULL(x) (((uint32_t)(((uint32_t)(x)) << ENET_RAFL_RX_ALMOST_FULL_SHIFT)) & ENET_RAFL_RX_ALMOST_FULL_MASK) +/*! @} */ /*! @name TSEM - Transmit FIFO Section Empty Threshold */ +/*! @{ */ #define ENET_TSEM_TX_SECTION_EMPTY_MASK (0xFFU) #define ENET_TSEM_TX_SECTION_EMPTY_SHIFT (0U) #define ENET_TSEM_TX_SECTION_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_TSEM_TX_SECTION_EMPTY_SHIFT)) & ENET_TSEM_TX_SECTION_EMPTY_MASK) +/*! @} */ /*! @name TAEM - Transmit FIFO Almost Empty Threshold */ +/*! @{ */ #define ENET_TAEM_TX_ALMOST_EMPTY_MASK (0xFFU) #define ENET_TAEM_TX_ALMOST_EMPTY_SHIFT (0U) #define ENET_TAEM_TX_ALMOST_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_TAEM_TX_ALMOST_EMPTY_SHIFT)) & ENET_TAEM_TX_ALMOST_EMPTY_MASK) +/*! @} */ /*! @name TAFL - Transmit FIFO Almost Full Threshold */ +/*! @{ */ #define ENET_TAFL_TX_ALMOST_FULL_MASK (0xFFU) #define ENET_TAFL_TX_ALMOST_FULL_SHIFT (0U) #define ENET_TAFL_TX_ALMOST_FULL(x) (((uint32_t)(((uint32_t)(x)) << ENET_TAFL_TX_ALMOST_FULL_SHIFT)) & ENET_TAFL_TX_ALMOST_FULL_MASK) +/*! @} */ /*! @name TIPG - Transmit Inter-Packet Gap */ +/*! @{ */ #define ENET_TIPG_IPG_MASK (0x1FU) #define ENET_TIPG_IPG_SHIFT (0U) #define ENET_TIPG_IPG(x) (((uint32_t)(((uint32_t)(x)) << ENET_TIPG_IPG_SHIFT)) & ENET_TIPG_IPG_MASK) +/*! @} */ /*! @name FTRL - Frame Truncation Length */ +/*! @{ */ #define ENET_FTRL_TRUNC_FL_MASK (0x3FFFU) #define ENET_FTRL_TRUNC_FL_SHIFT (0U) #define ENET_FTRL_TRUNC_FL(x) (((uint32_t)(((uint32_t)(x)) << ENET_FTRL_TRUNC_FL_SHIFT)) & ENET_FTRL_TRUNC_FL_MASK) +/*! @} */ /*! @name TACC - Transmit Accelerator Function Configuration */ +/*! @{ */ #define ENET_TACC_SHIFT16_MASK (0x1U) #define ENET_TACC_SHIFT16_SHIFT (0U) +/*! SHIFT16 - TX FIFO Shift-16 + * 0b0..Disabled. + * 0b1..Indicates to the transmit data FIFO that the written frames contain two additional octets before the frame data. This means the actual frame begins at bit 16 of the first word written into the FIFO. This function allows putting the frame payload on a 32-bit boundary in memory, as the 14-byte Ethernet header is extended to a 16-byte header. + */ #define ENET_TACC_SHIFT16(x) (((uint32_t)(((uint32_t)(x)) << ENET_TACC_SHIFT16_SHIFT)) & ENET_TACC_SHIFT16_MASK) #define ENET_TACC_IPCHK_MASK (0x8U) #define ENET_TACC_IPCHK_SHIFT (3U) +/*! IPCHK + * 0b0..Checksum is not inserted. + * 0b1..If an IP frame is transmitted, the checksum is inserted automatically. The IP header checksum field must be cleared. If a non-IP frame is transmitted the frame is not modified. + */ #define ENET_TACC_IPCHK(x) (((uint32_t)(((uint32_t)(x)) << ENET_TACC_IPCHK_SHIFT)) & ENET_TACC_IPCHK_MASK) #define ENET_TACC_PROCHK_MASK (0x10U) #define ENET_TACC_PROCHK_SHIFT (4U) +/*! PROCHK + * 0b0..Checksum not inserted. + * 0b1..If an IP frame with a known protocol is transmitted, the checksum is inserted automatically into the frame. The checksum field must be cleared. The other frames are not modified. + */ #define ENET_TACC_PROCHK(x) (((uint32_t)(((uint32_t)(x)) << ENET_TACC_PROCHK_SHIFT)) & ENET_TACC_PROCHK_MASK) +/*! @} */ /*! @name RACC - Receive Accelerator Function Configuration */ +/*! @{ */ #define ENET_RACC_PADREM_MASK (0x1U) #define ENET_RACC_PADREM_SHIFT (0U) +/*! PADREM - Enable Padding Removal For Short IP Frames + * 0b0..Padding not removed. + * 0b1..Any bytes following the IP payload section of the frame are removed from the frame. + */ #define ENET_RACC_PADREM(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_PADREM_SHIFT)) & ENET_RACC_PADREM_MASK) #define ENET_RACC_IPDIS_MASK (0x2U) #define ENET_RACC_IPDIS_SHIFT (1U) +/*! IPDIS - Enable Discard Of Frames With Wrong IPv4 Header Checksum + * 0b0..Frames with wrong IPv4 header checksum are not discarded. + * 0b1..If an IPv4 frame is received with a mismatching header checksum, the frame is discarded. IPv6 has no header checksum and is not affected by this setting. Discarding is only available when the RX FIFO operates in store and forward mode (RSFL cleared). + */ #define ENET_RACC_IPDIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_IPDIS_SHIFT)) & ENET_RACC_IPDIS_MASK) #define ENET_RACC_PRODIS_MASK (0x4U) #define ENET_RACC_PRODIS_SHIFT (2U) +/*! PRODIS - Enable Discard Of Frames With Wrong Protocol Checksum + * 0b0..Frames with wrong checksum are not discarded. + * 0b1..If a TCP/IP, UDP/IP, or ICMP/IP frame is received that has a wrong TCP, UDP, or ICMP checksum, the frame is discarded. Discarding is only available when the RX FIFO operates in store and forward mode (RSFL cleared). + */ #define ENET_RACC_PRODIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_PRODIS_SHIFT)) & ENET_RACC_PRODIS_MASK) #define ENET_RACC_LINEDIS_MASK (0x40U) #define ENET_RACC_LINEDIS_SHIFT (6U) +/*! LINEDIS - Enable Discard Of Frames With MAC Layer Errors + * 0b0..Frames with errors are not discarded. + * 0b1..Any frame received with a CRC, length, or PHY error is automatically discarded and not forwarded to the user application interface. + */ #define ENET_RACC_LINEDIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_LINEDIS_SHIFT)) & ENET_RACC_LINEDIS_MASK) #define ENET_RACC_SHIFT16_MASK (0x80U) #define ENET_RACC_SHIFT16_SHIFT (7U) +/*! SHIFT16 - RX FIFO Shift-16 + * 0b0..Disabled. + * 0b1..Instructs the MAC to write two additional bytes in front of each frame received into the RX FIFO. + */ #define ENET_RACC_SHIFT16(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_SHIFT16_SHIFT)) & ENET_RACC_SHIFT16_MASK) +/*! @} */ /*! @name RMON_T_PACKETS - Tx Packet Count Statistic Register */ +/*! @{ */ #define ENET_RMON_T_PACKETS_TXPKTS_MASK (0xFFFFU) #define ENET_RMON_T_PACKETS_TXPKTS_SHIFT (0U) #define ENET_RMON_T_PACKETS_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_PACKETS_TXPKTS_SHIFT)) & ENET_RMON_T_PACKETS_TXPKTS_MASK) +/*! @} */ /*! @name RMON_T_BC_PKT - Tx Broadcast Packets Statistic Register */ +/*! @{ */ #define ENET_RMON_T_BC_PKT_TXPKTS_MASK (0xFFFFU) #define ENET_RMON_T_BC_PKT_TXPKTS_SHIFT (0U) #define ENET_RMON_T_BC_PKT_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_BC_PKT_TXPKTS_SHIFT)) & ENET_RMON_T_BC_PKT_TXPKTS_MASK) +/*! @} */ /*! @name RMON_T_MC_PKT - Tx Multicast Packets Statistic Register */ +/*! @{ */ #define ENET_RMON_T_MC_PKT_TXPKTS_MASK (0xFFFFU) #define ENET_RMON_T_MC_PKT_TXPKTS_SHIFT (0U) #define ENET_RMON_T_MC_PKT_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_MC_PKT_TXPKTS_SHIFT)) & ENET_RMON_T_MC_PKT_TXPKTS_MASK) +/*! @} */ /*! @name RMON_T_CRC_ALIGN - Tx Packets with CRC/Align Error Statistic Register */ +/*! @{ */ #define ENET_RMON_T_CRC_ALIGN_TXPKTS_MASK (0xFFFFU) #define ENET_RMON_T_CRC_ALIGN_TXPKTS_SHIFT (0U) #define ENET_RMON_T_CRC_ALIGN_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_CRC_ALIGN_TXPKTS_SHIFT)) & ENET_RMON_T_CRC_ALIGN_TXPKTS_MASK) +/*! @} */ /*! @name RMON_T_UNDERSIZE - Tx Packets Less Than Bytes and Good CRC Statistic Register */ +/*! @{ */ #define ENET_RMON_T_UNDERSIZE_TXPKTS_MASK (0xFFFFU) #define ENET_RMON_T_UNDERSIZE_TXPKTS_SHIFT (0U) #define ENET_RMON_T_UNDERSIZE_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_UNDERSIZE_TXPKTS_SHIFT)) & ENET_RMON_T_UNDERSIZE_TXPKTS_MASK) +/*! @} */ /*! @name RMON_T_OVERSIZE - Tx Packets GT MAX_FL bytes and Good CRC Statistic Register */ +/*! @{ */ #define ENET_RMON_T_OVERSIZE_TXPKTS_MASK (0xFFFFU) #define ENET_RMON_T_OVERSIZE_TXPKTS_SHIFT (0U) #define ENET_RMON_T_OVERSIZE_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_OVERSIZE_TXPKTS_SHIFT)) & ENET_RMON_T_OVERSIZE_TXPKTS_MASK) +/*! @} */ /*! @name RMON_T_FRAG - Tx Packets Less Than 64 Bytes and Bad CRC Statistic Register */ +/*! @{ */ #define ENET_RMON_T_FRAG_TXPKTS_MASK (0xFFFFU) #define ENET_RMON_T_FRAG_TXPKTS_SHIFT (0U) #define ENET_RMON_T_FRAG_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_FRAG_TXPKTS_SHIFT)) & ENET_RMON_T_FRAG_TXPKTS_MASK) +/*! @} */ /*! @name RMON_T_JAB - Tx Packets Greater Than MAX_FL bytes and Bad CRC Statistic Register */ +/*! @{ */ #define ENET_RMON_T_JAB_TXPKTS_MASK (0xFFFFU) #define ENET_RMON_T_JAB_TXPKTS_SHIFT (0U) #define ENET_RMON_T_JAB_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_JAB_TXPKTS_SHIFT)) & ENET_RMON_T_JAB_TXPKTS_MASK) +/*! @} */ /*! @name RMON_T_COL - Tx Collision Count Statistic Register */ +/*! @{ */ #define ENET_RMON_T_COL_TXPKTS_MASK (0xFFFFU) #define ENET_RMON_T_COL_TXPKTS_SHIFT (0U) #define ENET_RMON_T_COL_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_COL_TXPKTS_SHIFT)) & ENET_RMON_T_COL_TXPKTS_MASK) +/*! @} */ /*! @name RMON_T_P64 - Tx 64-Byte Packets Statistic Register */ +/*! @{ */ #define ENET_RMON_T_P64_TXPKTS_MASK (0xFFFFU) #define ENET_RMON_T_P64_TXPKTS_SHIFT (0U) #define ENET_RMON_T_P64_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P64_TXPKTS_SHIFT)) & ENET_RMON_T_P64_TXPKTS_MASK) +/*! @} */ /*! @name RMON_T_P65TO127 - Tx 65- to 127-byte Packets Statistic Register */ +/*! @{ */ #define ENET_RMON_T_P65TO127_TXPKTS_MASK (0xFFFFU) #define ENET_RMON_T_P65TO127_TXPKTS_SHIFT (0U) #define ENET_RMON_T_P65TO127_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P65TO127_TXPKTS_SHIFT)) & ENET_RMON_T_P65TO127_TXPKTS_MASK) +/*! @} */ /*! @name RMON_T_P128TO255 - Tx 128- to 255-byte Packets Statistic Register */ +/*! @{ */ #define ENET_RMON_T_P128TO255_TXPKTS_MASK (0xFFFFU) #define ENET_RMON_T_P128TO255_TXPKTS_SHIFT (0U) #define ENET_RMON_T_P128TO255_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P128TO255_TXPKTS_SHIFT)) & ENET_RMON_T_P128TO255_TXPKTS_MASK) +/*! @} */ /*! @name RMON_T_P256TO511 - Tx 256- to 511-byte Packets Statistic Register */ +/*! @{ */ #define ENET_RMON_T_P256TO511_TXPKTS_MASK (0xFFFFU) #define ENET_RMON_T_P256TO511_TXPKTS_SHIFT (0U) #define ENET_RMON_T_P256TO511_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P256TO511_TXPKTS_SHIFT)) & ENET_RMON_T_P256TO511_TXPKTS_MASK) +/*! @} */ /*! @name RMON_T_P512TO1023 - Tx 512- to 1023-byte Packets Statistic Register */ +/*! @{ */ #define ENET_RMON_T_P512TO1023_TXPKTS_MASK (0xFFFFU) #define ENET_RMON_T_P512TO1023_TXPKTS_SHIFT (0U) #define ENET_RMON_T_P512TO1023_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P512TO1023_TXPKTS_SHIFT)) & ENET_RMON_T_P512TO1023_TXPKTS_MASK) +/*! @} */ /*! @name RMON_T_P1024TO2047 - Tx 1024- to 2047-byte Packets Statistic Register */ +/*! @{ */ #define ENET_RMON_T_P1024TO2047_TXPKTS_MASK (0xFFFFU) #define ENET_RMON_T_P1024TO2047_TXPKTS_SHIFT (0U) #define ENET_RMON_T_P1024TO2047_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P1024TO2047_TXPKTS_SHIFT)) & ENET_RMON_T_P1024TO2047_TXPKTS_MASK) +/*! @} */ /*! @name RMON_T_P_GTE2048 - Tx Packets Greater Than 2048 Bytes Statistic Register */ +/*! @{ */ #define ENET_RMON_T_P_GTE2048_TXPKTS_MASK (0xFFFFU) #define ENET_RMON_T_P_GTE2048_TXPKTS_SHIFT (0U) #define ENET_RMON_T_P_GTE2048_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P_GTE2048_TXPKTS_SHIFT)) & ENET_RMON_T_P_GTE2048_TXPKTS_MASK) +/*! @} */ /*! @name RMON_T_OCTETS - Tx Octets Statistic Register */ +/*! @{ */ #define ENET_RMON_T_OCTETS_TXOCTS_MASK (0xFFFFFFFFU) #define ENET_RMON_T_OCTETS_TXOCTS_SHIFT (0U) #define ENET_RMON_T_OCTETS_TXOCTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_OCTETS_TXOCTS_SHIFT)) & ENET_RMON_T_OCTETS_TXOCTS_MASK) +/*! @} */ /*! @name IEEE_T_FRAME_OK - Frames Transmitted OK Statistic Register */ +/*! @{ */ #define ENET_IEEE_T_FRAME_OK_COUNT_MASK (0xFFFFU) #define ENET_IEEE_T_FRAME_OK_COUNT_SHIFT (0U) #define ENET_IEEE_T_FRAME_OK_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_FRAME_OK_COUNT_SHIFT)) & ENET_IEEE_T_FRAME_OK_COUNT_MASK) +/*! @} */ /*! @name IEEE_T_1COL - Frames Transmitted with Single Collision Statistic Register */ +/*! @{ */ #define ENET_IEEE_T_1COL_COUNT_MASK (0xFFFFU) #define ENET_IEEE_T_1COL_COUNT_SHIFT (0U) #define ENET_IEEE_T_1COL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_1COL_COUNT_SHIFT)) & ENET_IEEE_T_1COL_COUNT_MASK) +/*! @} */ /*! @name IEEE_T_MCOL - Frames Transmitted with Multiple Collisions Statistic Register */ +/*! @{ */ #define ENET_IEEE_T_MCOL_COUNT_MASK (0xFFFFU) #define ENET_IEEE_T_MCOL_COUNT_SHIFT (0U) #define ENET_IEEE_T_MCOL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_MCOL_COUNT_SHIFT)) & ENET_IEEE_T_MCOL_COUNT_MASK) +/*! @} */ /*! @name IEEE_T_DEF - Frames Transmitted after Deferral Delay Statistic Register */ +/*! @{ */ #define ENET_IEEE_T_DEF_COUNT_MASK (0xFFFFU) #define ENET_IEEE_T_DEF_COUNT_SHIFT (0U) #define ENET_IEEE_T_DEF_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_DEF_COUNT_SHIFT)) & ENET_IEEE_T_DEF_COUNT_MASK) +/*! @} */ /*! @name IEEE_T_LCOL - Frames Transmitted with Late Collision Statistic Register */ +/*! @{ */ #define ENET_IEEE_T_LCOL_COUNT_MASK (0xFFFFU) #define ENET_IEEE_T_LCOL_COUNT_SHIFT (0U) #define ENET_IEEE_T_LCOL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_LCOL_COUNT_SHIFT)) & ENET_IEEE_T_LCOL_COUNT_MASK) +/*! @} */ /*! @name IEEE_T_EXCOL - Frames Transmitted with Excessive Collisions Statistic Register */ +/*! @{ */ #define ENET_IEEE_T_EXCOL_COUNT_MASK (0xFFFFU) #define ENET_IEEE_T_EXCOL_COUNT_SHIFT (0U) #define ENET_IEEE_T_EXCOL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_EXCOL_COUNT_SHIFT)) & ENET_IEEE_T_EXCOL_COUNT_MASK) +/*! @} */ /*! @name IEEE_T_MACERR - Frames Transmitted with Tx FIFO Underrun Statistic Register */ +/*! @{ */ #define ENET_IEEE_T_MACERR_COUNT_MASK (0xFFFFU) #define ENET_IEEE_T_MACERR_COUNT_SHIFT (0U) #define ENET_IEEE_T_MACERR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_MACERR_COUNT_SHIFT)) & ENET_IEEE_T_MACERR_COUNT_MASK) +/*! @} */ /*! @name IEEE_T_CSERR - Frames Transmitted with Carrier Sense Error Statistic Register */ +/*! @{ */ #define ENET_IEEE_T_CSERR_COUNT_MASK (0xFFFFU) #define ENET_IEEE_T_CSERR_COUNT_SHIFT (0U) #define ENET_IEEE_T_CSERR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_CSERR_COUNT_SHIFT)) & ENET_IEEE_T_CSERR_COUNT_MASK) +/*! @} */ /*! @name IEEE_T_FDXFC - Flow Control Pause Frames Transmitted Statistic Register */ +/*! @{ */ #define ENET_IEEE_T_FDXFC_COUNT_MASK (0xFFFFU) #define ENET_IEEE_T_FDXFC_COUNT_SHIFT (0U) #define ENET_IEEE_T_FDXFC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_FDXFC_COUNT_SHIFT)) & ENET_IEEE_T_FDXFC_COUNT_MASK) +/*! @} */ /*! @name IEEE_T_OCTETS_OK - Octet Count for Frames Transmitted w/o Error Statistic Register */ +/*! @{ */ #define ENET_IEEE_T_OCTETS_OK_COUNT_MASK (0xFFFFFFFFU) #define ENET_IEEE_T_OCTETS_OK_COUNT_SHIFT (0U) #define ENET_IEEE_T_OCTETS_OK_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_OCTETS_OK_COUNT_SHIFT)) & ENET_IEEE_T_OCTETS_OK_COUNT_MASK) +/*! @} */ /*! @name RMON_R_PACKETS - Rx Packet Count Statistic Register */ +/*! @{ */ #define ENET_RMON_R_PACKETS_COUNT_MASK (0xFFFFU) #define ENET_RMON_R_PACKETS_COUNT_SHIFT (0U) #define ENET_RMON_R_PACKETS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_PACKETS_COUNT_SHIFT)) & ENET_RMON_R_PACKETS_COUNT_MASK) +/*! @} */ /*! @name RMON_R_BC_PKT - Rx Broadcast Packets Statistic Register */ +/*! @{ */ #define ENET_RMON_R_BC_PKT_COUNT_MASK (0xFFFFU) #define ENET_RMON_R_BC_PKT_COUNT_SHIFT (0U) #define ENET_RMON_R_BC_PKT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_BC_PKT_COUNT_SHIFT)) & ENET_RMON_R_BC_PKT_COUNT_MASK) +/*! @} */ /*! @name RMON_R_MC_PKT - Rx Multicast Packets Statistic Register */ +/*! @{ */ #define ENET_RMON_R_MC_PKT_COUNT_MASK (0xFFFFU) #define ENET_RMON_R_MC_PKT_COUNT_SHIFT (0U) #define ENET_RMON_R_MC_PKT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_MC_PKT_COUNT_SHIFT)) & ENET_RMON_R_MC_PKT_COUNT_MASK) +/*! @} */ /*! @name RMON_R_CRC_ALIGN - Rx Packets with CRC/Align Error Statistic Register */ +/*! @{ */ #define ENET_RMON_R_CRC_ALIGN_COUNT_MASK (0xFFFFU) #define ENET_RMON_R_CRC_ALIGN_COUNT_SHIFT (0U) #define ENET_RMON_R_CRC_ALIGN_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_CRC_ALIGN_COUNT_SHIFT)) & ENET_RMON_R_CRC_ALIGN_COUNT_MASK) +/*! @} */ /*! @name RMON_R_UNDERSIZE - Rx Packets with Less Than 64 Bytes and Good CRC Statistic Register */ +/*! @{ */ #define ENET_RMON_R_UNDERSIZE_COUNT_MASK (0xFFFFU) #define ENET_RMON_R_UNDERSIZE_COUNT_SHIFT (0U) #define ENET_RMON_R_UNDERSIZE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_UNDERSIZE_COUNT_SHIFT)) & ENET_RMON_R_UNDERSIZE_COUNT_MASK) +/*! @} */ /*! @name RMON_R_OVERSIZE - Rx Packets Greater Than MAX_FL and Good CRC Statistic Register */ +/*! @{ */ #define ENET_RMON_R_OVERSIZE_COUNT_MASK (0xFFFFU) #define ENET_RMON_R_OVERSIZE_COUNT_SHIFT (0U) #define ENET_RMON_R_OVERSIZE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_OVERSIZE_COUNT_SHIFT)) & ENET_RMON_R_OVERSIZE_COUNT_MASK) +/*! @} */ /*! @name RMON_R_FRAG - Rx Packets Less Than 64 Bytes and Bad CRC Statistic Register */ +/*! @{ */ #define ENET_RMON_R_FRAG_COUNT_MASK (0xFFFFU) #define ENET_RMON_R_FRAG_COUNT_SHIFT (0U) #define ENET_RMON_R_FRAG_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_FRAG_COUNT_SHIFT)) & ENET_RMON_R_FRAG_COUNT_MASK) +/*! @} */ /*! @name RMON_R_JAB - Rx Packets Greater Than MAX_FL Bytes and Bad CRC Statistic Register */ +/*! @{ */ #define ENET_RMON_R_JAB_COUNT_MASK (0xFFFFU) #define ENET_RMON_R_JAB_COUNT_SHIFT (0U) #define ENET_RMON_R_JAB_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_JAB_COUNT_SHIFT)) & ENET_RMON_R_JAB_COUNT_MASK) +/*! @} */ /*! @name RMON_R_P64 - Rx 64-Byte Packets Statistic Register */ +/*! @{ */ #define ENET_RMON_R_P64_COUNT_MASK (0xFFFFU) #define ENET_RMON_R_P64_COUNT_SHIFT (0U) #define ENET_RMON_R_P64_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P64_COUNT_SHIFT)) & ENET_RMON_R_P64_COUNT_MASK) +/*! @} */ /*! @name RMON_R_P65TO127 - Rx 65- to 127-Byte Packets Statistic Register */ +/*! @{ */ #define ENET_RMON_R_P65TO127_COUNT_MASK (0xFFFFU) #define ENET_RMON_R_P65TO127_COUNT_SHIFT (0U) #define ENET_RMON_R_P65TO127_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P65TO127_COUNT_SHIFT)) & ENET_RMON_R_P65TO127_COUNT_MASK) +/*! @} */ /*! @name RMON_R_P128TO255 - Rx 128- to 255-Byte Packets Statistic Register */ +/*! @{ */ #define ENET_RMON_R_P128TO255_COUNT_MASK (0xFFFFU) #define ENET_RMON_R_P128TO255_COUNT_SHIFT (0U) #define ENET_RMON_R_P128TO255_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P128TO255_COUNT_SHIFT)) & ENET_RMON_R_P128TO255_COUNT_MASK) +/*! @} */ /*! @name RMON_R_P256TO511 - Rx 256- to 511-Byte Packets Statistic Register */ +/*! @{ */ #define ENET_RMON_R_P256TO511_COUNT_MASK (0xFFFFU) #define ENET_RMON_R_P256TO511_COUNT_SHIFT (0U) #define ENET_RMON_R_P256TO511_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P256TO511_COUNT_SHIFT)) & ENET_RMON_R_P256TO511_COUNT_MASK) +/*! @} */ /*! @name RMON_R_P512TO1023 - Rx 512- to 1023-Byte Packets Statistic Register */ +/*! @{ */ #define ENET_RMON_R_P512TO1023_COUNT_MASK (0xFFFFU) #define ENET_RMON_R_P512TO1023_COUNT_SHIFT (0U) #define ENET_RMON_R_P512TO1023_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P512TO1023_COUNT_SHIFT)) & ENET_RMON_R_P512TO1023_COUNT_MASK) +/*! @} */ /*! @name RMON_R_P1024TO2047 - Rx 1024- to 2047-Byte Packets Statistic Register */ +/*! @{ */ #define ENET_RMON_R_P1024TO2047_COUNT_MASK (0xFFFFU) #define ENET_RMON_R_P1024TO2047_COUNT_SHIFT (0U) #define ENET_RMON_R_P1024TO2047_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P1024TO2047_COUNT_SHIFT)) & ENET_RMON_R_P1024TO2047_COUNT_MASK) +/*! @} */ /*! @name RMON_R_P_GTE2048 - Rx Packets Greater than 2048 Bytes Statistic Register */ +/*! @{ */ #define ENET_RMON_R_P_GTE2048_COUNT_MASK (0xFFFFU) #define ENET_RMON_R_P_GTE2048_COUNT_SHIFT (0U) #define ENET_RMON_R_P_GTE2048_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P_GTE2048_COUNT_SHIFT)) & ENET_RMON_R_P_GTE2048_COUNT_MASK) +/*! @} */ /*! @name RMON_R_OCTETS - Rx Octets Statistic Register */ +/*! @{ */ #define ENET_RMON_R_OCTETS_COUNT_MASK (0xFFFFFFFFU) #define ENET_RMON_R_OCTETS_COUNT_SHIFT (0U) #define ENET_RMON_R_OCTETS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_OCTETS_COUNT_SHIFT)) & ENET_RMON_R_OCTETS_COUNT_MASK) +/*! @} */ /*! @name IEEE_R_DROP - Frames not Counted Correctly Statistic Register */ +/*! @{ */ #define ENET_IEEE_R_DROP_COUNT_MASK (0xFFFFU) #define ENET_IEEE_R_DROP_COUNT_SHIFT (0U) #define ENET_IEEE_R_DROP_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_DROP_COUNT_SHIFT)) & ENET_IEEE_R_DROP_COUNT_MASK) +/*! @} */ /*! @name IEEE_R_FRAME_OK - Frames Received OK Statistic Register */ +/*! @{ */ #define ENET_IEEE_R_FRAME_OK_COUNT_MASK (0xFFFFU) #define ENET_IEEE_R_FRAME_OK_COUNT_SHIFT (0U) #define ENET_IEEE_R_FRAME_OK_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_FRAME_OK_COUNT_SHIFT)) & ENET_IEEE_R_FRAME_OK_COUNT_MASK) +/*! @} */ /*! @name IEEE_R_CRC - Frames Received with CRC Error Statistic Register */ +/*! @{ */ #define ENET_IEEE_R_CRC_COUNT_MASK (0xFFFFU) #define ENET_IEEE_R_CRC_COUNT_SHIFT (0U) #define ENET_IEEE_R_CRC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_CRC_COUNT_SHIFT)) & ENET_IEEE_R_CRC_COUNT_MASK) +/*! @} */ /*! @name IEEE_R_ALIGN - Frames Received with Alignment Error Statistic Register */ +/*! @{ */ #define ENET_IEEE_R_ALIGN_COUNT_MASK (0xFFFFU) #define ENET_IEEE_R_ALIGN_COUNT_SHIFT (0U) #define ENET_IEEE_R_ALIGN_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_ALIGN_COUNT_SHIFT)) & ENET_IEEE_R_ALIGN_COUNT_MASK) +/*! @} */ /*! @name IEEE_R_MACERR - Receive FIFO Overflow Count Statistic Register */ +/*! @{ */ #define ENET_IEEE_R_MACERR_COUNT_MASK (0xFFFFU) #define ENET_IEEE_R_MACERR_COUNT_SHIFT (0U) #define ENET_IEEE_R_MACERR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_MACERR_COUNT_SHIFT)) & ENET_IEEE_R_MACERR_COUNT_MASK) +/*! @} */ /*! @name IEEE_R_FDXFC - Flow Control Pause Frames Received Statistic Register */ +/*! @{ */ #define ENET_IEEE_R_FDXFC_COUNT_MASK (0xFFFFU) #define ENET_IEEE_R_FDXFC_COUNT_SHIFT (0U) #define ENET_IEEE_R_FDXFC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_FDXFC_COUNT_SHIFT)) & ENET_IEEE_R_FDXFC_COUNT_MASK) +/*! @} */ /*! @name IEEE_R_OCTETS_OK - Octet Count for Frames Received without Error Statistic Register */ +/*! @{ */ #define ENET_IEEE_R_OCTETS_OK_COUNT_MASK (0xFFFFFFFFU) #define ENET_IEEE_R_OCTETS_OK_COUNT_SHIFT (0U) #define ENET_IEEE_R_OCTETS_OK_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_OCTETS_OK_COUNT_SHIFT)) & ENET_IEEE_R_OCTETS_OK_COUNT_MASK) +/*! @} */ /*! @name ATCR - Adjustable Timer Control Register */ +/*! @{ */ #define ENET_ATCR_EN_MASK (0x1U) #define ENET_ATCR_EN_SHIFT (0U) +/*! EN - Enable Timer + * 0b0..The timer stops at the current value. + * 0b1..The timer starts incrementing. + */ #define ENET_ATCR_EN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_EN_SHIFT)) & ENET_ATCR_EN_MASK) #define ENET_ATCR_OFFEN_MASK (0x4U) #define ENET_ATCR_OFFEN_SHIFT (2U) +/*! OFFEN - Enable One-Shot Offset Event + * 0b0..Disable. + * 0b1..The timer can be reset to zero when the given offset time is reached (offset event). The field is cleared when the offset event is reached, so no further event occurs until the field is set again. The timer offset value must be set before setting this field. + */ #define ENET_ATCR_OFFEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_OFFEN_SHIFT)) & ENET_ATCR_OFFEN_MASK) #define ENET_ATCR_OFFRST_MASK (0x8U) #define ENET_ATCR_OFFRST_SHIFT (3U) +/*! OFFRST - Reset Timer On Offset Event + * 0b0..The timer is not affected and no action occurs, besides clearing OFFEN, when the offset is reached. + * 0b1..If OFFEN is set, the timer resets to zero when the offset setting is reached. The offset event does not cause a timer interrupt. + */ #define ENET_ATCR_OFFRST(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_OFFRST_SHIFT)) & ENET_ATCR_OFFRST_MASK) #define ENET_ATCR_PEREN_MASK (0x10U) #define ENET_ATCR_PEREN_SHIFT (4U) +/*! PEREN - Enable Periodical Event + * 0b0..Disable. + * 0b1..A period event interrupt can be generated (EIR[TS_TIMER]) and the event signal output is asserted when the timer wraps around according to the periodic setting ATPER. The timer period value must be set before setting this bit. Not all devices contain the event signal output. See the chip configuration details. + */ #define ENET_ATCR_PEREN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_PEREN_SHIFT)) & ENET_ATCR_PEREN_MASK) #define ENET_ATCR_PINPER_MASK (0x80U) #define ENET_ATCR_PINPER_SHIFT (7U) +/*! PINPER + * 0b0..Disable. + * 0b1..Enable. + */ #define ENET_ATCR_PINPER(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_PINPER_SHIFT)) & ENET_ATCR_PINPER_MASK) #define ENET_ATCR_RESTART_MASK (0x200U) #define ENET_ATCR_RESTART_SHIFT (9U) #define ENET_ATCR_RESTART(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_RESTART_SHIFT)) & ENET_ATCR_RESTART_MASK) #define ENET_ATCR_CAPTURE_MASK (0x800U) #define ENET_ATCR_CAPTURE_SHIFT (11U) +/*! CAPTURE - Capture Timer Value + * 0b0..No effect. + * 0b1..The current time is captured and can be read from the ATVR register. + */ #define ENET_ATCR_CAPTURE(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_CAPTURE_SHIFT)) & ENET_ATCR_CAPTURE_MASK) #define ENET_ATCR_SLAVE_MASK (0x2000U) #define ENET_ATCR_SLAVE_SHIFT (13U) +/*! SLAVE - Enable Timer Slave Mode + * 0b0..The timer is active and all configuration fields in this register are relevant. + * 0b1..The internal timer is disabled and the externally provided timer value is used. All other fields, except CAPTURE, in this register have no effect. CAPTURE can still be used to capture the current timer value. + */ #define ENET_ATCR_SLAVE(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_SLAVE_SHIFT)) & ENET_ATCR_SLAVE_MASK) +/*! @} */ /*! @name ATVR - Timer Value Register */ +/*! @{ */ #define ENET_ATVR_ATIME_MASK (0xFFFFFFFFU) #define ENET_ATVR_ATIME_SHIFT (0U) #define ENET_ATVR_ATIME(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATVR_ATIME_SHIFT)) & ENET_ATVR_ATIME_MASK) +/*! @} */ /*! @name ATOFF - Timer Offset Register */ +/*! @{ */ #define ENET_ATOFF_OFFSET_MASK (0xFFFFFFFFU) #define ENET_ATOFF_OFFSET_SHIFT (0U) #define ENET_ATOFF_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATOFF_OFFSET_SHIFT)) & ENET_ATOFF_OFFSET_MASK) +/*! @} */ /*! @name ATPER - Timer Period Register */ +/*! @{ */ #define ENET_ATPER_PERIOD_MASK (0xFFFFFFFFU) #define ENET_ATPER_PERIOD_SHIFT (0U) #define ENET_ATPER_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATPER_PERIOD_SHIFT)) & ENET_ATPER_PERIOD_MASK) +/*! @} */ /*! @name ATCOR - Timer Correction Register */ +/*! @{ */ #define ENET_ATCOR_COR_MASK (0x7FFFFFFFU) #define ENET_ATCOR_COR_SHIFT (0U) #define ENET_ATCOR_COR(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCOR_COR_SHIFT)) & ENET_ATCOR_COR_MASK) +/*! @} */ /*! @name ATINC - Time-Stamping Clock Period Register */ +/*! @{ */ #define ENET_ATINC_INC_MASK (0x7FU) #define ENET_ATINC_INC_SHIFT (0U) #define ENET_ATINC_INC(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATINC_INC_SHIFT)) & ENET_ATINC_INC_MASK) #define ENET_ATINC_INC_CORR_MASK (0x7F00U) #define ENET_ATINC_INC_CORR_SHIFT (8U) #define ENET_ATINC_INC_CORR(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATINC_INC_CORR_SHIFT)) & ENET_ATINC_INC_CORR_MASK) +/*! @} */ /*! @name ATSTMP - Timestamp of Last Transmitted Frame */ +/*! @{ */ #define ENET_ATSTMP_TIMESTAMP_MASK (0xFFFFFFFFU) #define ENET_ATSTMP_TIMESTAMP_SHIFT (0U) #define ENET_ATSTMP_TIMESTAMP(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATSTMP_TIMESTAMP_SHIFT)) & ENET_ATSTMP_TIMESTAMP_MASK) +/*! @} */ /*! @name TGSR - Timer Global Status Register */ +/*! @{ */ #define ENET_TGSR_TF0_MASK (0x1U) #define ENET_TGSR_TF0_SHIFT (0U) +/*! TF0 - Copy Of Timer Flag For Channel 0 + * 0b0..Timer Flag for Channel 0 is clear + * 0b1..Timer Flag for Channel 0 is set + */ #define ENET_TGSR_TF0(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF0_SHIFT)) & ENET_TGSR_TF0_MASK) #define ENET_TGSR_TF1_MASK (0x2U) #define ENET_TGSR_TF1_SHIFT (1U) +/*! TF1 - Copy Of Timer Flag For Channel 1 + * 0b0..Timer Flag for Channel 1 is clear + * 0b1..Timer Flag for Channel 1 is set + */ #define ENET_TGSR_TF1(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF1_SHIFT)) & ENET_TGSR_TF1_MASK) #define ENET_TGSR_TF2_MASK (0x4U) #define ENET_TGSR_TF2_SHIFT (2U) +/*! TF2 - Copy Of Timer Flag For Channel 2 + * 0b0..Timer Flag for Channel 2 is clear + * 0b1..Timer Flag for Channel 2 is set + */ #define ENET_TGSR_TF2(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF2_SHIFT)) & ENET_TGSR_TF2_MASK) #define ENET_TGSR_TF3_MASK (0x8U) #define ENET_TGSR_TF3_SHIFT (3U) +/*! TF3 - Copy Of Timer Flag For Channel 3 + * 0b0..Timer Flag for Channel 3 is clear + * 0b1..Timer Flag for Channel 3 is set + */ #define ENET_TGSR_TF3(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF3_SHIFT)) & ENET_TGSR_TF3_MASK) +/*! @} */ /*! @name TCSR - Timer Control Status Register */ +/*! @{ */ #define ENET_TCSR_TDRE_MASK (0x1U) #define ENET_TCSR_TDRE_SHIFT (0U) +/*! TDRE - Timer DMA Request Enable + * 0b0..DMA request is disabled + * 0b1..DMA request is enabled + */ #define ENET_TCSR_TDRE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TDRE_SHIFT)) & ENET_TCSR_TDRE_MASK) #define ENET_TCSR_TMODE_MASK (0x3CU) #define ENET_TCSR_TMODE_SHIFT (2U) +/*! TMODE - Timer Mode + * 0b0000..Timer Channel is disabled. + * 0b0001..Timer Channel is configured for Input Capture on rising edge + * 0b0010..Timer Channel is configured for Input Capture on falling edge + * 0b0011..Timer Channel is configured for Input Capture on both edges + * 0b0100..Timer Channel is configured for Output Compare - software only + * 0b0101..Timer Channel is configured for Output Compare - toggle output on compare + * 0b0110..Timer Channel is configured for Output Compare - clear output on compare + * 0b0111..Timer Channel is configured for Output Compare - set output on compare + * 0b1000..Reserved + * 0b1010..Timer Channel is configured for Output Compare - clear output on compare, set output on overflow + * 0b10x1..Timer Channel is configured for Output Compare - set output on compare, clear output on overflow + * 0b1100..Reserved + * 0b1110..Timer Channel is configured for Output Compare - pulse output low on compare for one 1588 clock cycle + * 0b1111..Timer Channel is configured for Output Compare - pulse output high on compare for one 1588 clock cycle + */ #define ENET_TCSR_TMODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TMODE_SHIFT)) & ENET_TCSR_TMODE_MASK) #define ENET_TCSR_TIE_MASK (0x40U) #define ENET_TCSR_TIE_SHIFT (6U) +/*! TIE - Timer Interrupt Enable + * 0b0..Interrupt is disabled + * 0b1..Interrupt is enabled + */ #define ENET_TCSR_TIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TIE_SHIFT)) & ENET_TCSR_TIE_MASK) #define ENET_TCSR_TF_MASK (0x80U) #define ENET_TCSR_TF_SHIFT (7U) +/*! TF - Timer Flag + * 0b0..Input Capture or Output Compare has not occurred + * 0b1..Input Capture or Output Compare has occurred + */ #define ENET_TCSR_TF(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TF_SHIFT)) & ENET_TCSR_TF_MASK) +/*! @} */ /* The count of ENET_TCSR */ #define ENET_TCSR_COUNT (4U) /*! @name TCCR - Timer Compare Capture Register */ +/*! @{ */ #define ENET_TCCR_TCC_MASK (0xFFFFFFFFU) #define ENET_TCCR_TCC_SHIFT (0U) #define ENET_TCCR_TCC(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCCR_TCC_SHIFT)) & ENET_TCCR_TCC_MASK) +/*! @} */ /* The count of ENET_TCCR */ #define ENET_TCCR_COUNT (4U) @@ -5550,6 +9603,7 @@ typedef struct { */ /*! @name CTRL - Control Register */ +/*! @{ */ #define EWM_CTRL_EWMEN_MASK (0x1U) #define EWM_CTRL_EWMEN_SHIFT (0U) #define EWM_CTRL_EWMEN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_EWMEN_SHIFT)) & EWM_CTRL_EWMEN_MASK) @@ -5562,21 +9616,28 @@ typedef struct { #define EWM_CTRL_INTEN_MASK (0x8U) #define EWM_CTRL_INTEN_SHIFT (3U) #define EWM_CTRL_INTEN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_INTEN_SHIFT)) & EWM_CTRL_INTEN_MASK) +/*! @} */ /*! @name SERV - Service Register */ +/*! @{ */ #define EWM_SERV_SERVICE_MASK (0xFFU) #define EWM_SERV_SERVICE_SHIFT (0U) #define EWM_SERV_SERVICE(x) (((uint8_t)(((uint8_t)(x)) << EWM_SERV_SERVICE_SHIFT)) & EWM_SERV_SERVICE_MASK) +/*! @} */ /*! @name CMPL - Compare Low Register */ +/*! @{ */ #define EWM_CMPL_COMPAREL_MASK (0xFFU) #define EWM_CMPL_COMPAREL_SHIFT (0U) #define EWM_CMPL_COMPAREL(x) (((uint8_t)(((uint8_t)(x)) << EWM_CMPL_COMPAREL_SHIFT)) & EWM_CMPL_COMPAREL_MASK) +/*! @} */ /*! @name CMPH - Compare High Register */ +/*! @{ */ #define EWM_CMPH_COMPAREH_MASK (0xFFU) #define EWM_CMPH_COMPAREH_SHIFT (0U) #define EWM_CMPH_COMPAREH(x) (((uint8_t)(((uint8_t)(x)) << EWM_CMPH_COMPAREH_SHIFT)) & EWM_CMPH_COMPAREH_MASK) +/*! @} */ /*! @@ -5631,87 +9692,183 @@ typedef struct { */ /*! @name CSAR - Chip Select Address Register */ +/*! @{ */ #define FB_CSAR_BA_MASK (0xFFFF0000U) #define FB_CSAR_BA_SHIFT (16U) #define FB_CSAR_BA(x) (((uint32_t)(((uint32_t)(x)) << FB_CSAR_BA_SHIFT)) & FB_CSAR_BA_MASK) +/*! @} */ /* The count of FB_CSAR */ #define FB_CSAR_COUNT (6U) /*! @name CSMR - Chip Select Mask Register */ +/*! @{ */ #define FB_CSMR_V_MASK (0x1U) #define FB_CSMR_V_SHIFT (0U) +/*! V - Valid + * 0b0..Chip-select is invalid. + * 0b1..Chip-select is valid. + */ #define FB_CSMR_V(x) (((uint32_t)(((uint32_t)(x)) << FB_CSMR_V_SHIFT)) & FB_CSMR_V_MASK) #define FB_CSMR_WP_MASK (0x100U) #define FB_CSMR_WP_SHIFT (8U) +/*! WP - Write Protect + * 0b0..Write accesses are allowed. + * 0b1..Write accesses are not allowed. Attempting to write to the range of addresses for which the WP bit is set results in a bus error termination of the internal cycle and no external cycle. + */ #define FB_CSMR_WP(x) (((uint32_t)(((uint32_t)(x)) << FB_CSMR_WP_SHIFT)) & FB_CSMR_WP_MASK) #define FB_CSMR_BAM_MASK (0xFFFF0000U) #define FB_CSMR_BAM_SHIFT (16U) +/*! BAM - Base Address Mask + * 0b0000000000000000..The corresponding address bit in CSAR is used in the chip-select decode. + * 0b0000000000000001..The corresponding address bit in CSAR is a don't care in the chip-select decode. + */ #define FB_CSMR_BAM(x) (((uint32_t)(((uint32_t)(x)) << FB_CSMR_BAM_SHIFT)) & FB_CSMR_BAM_MASK) +/*! @} */ /* The count of FB_CSMR */ #define FB_CSMR_COUNT (6U) /*! @name CSCR - Chip Select Control Register */ +/*! @{ */ #define FB_CSCR_BSTW_MASK (0x8U) #define FB_CSCR_BSTW_SHIFT (3U) +/*! BSTW - Burst-Write Enable + * 0b0..Disabled. Data exceeding the specified port size is broken into individual, port-sized, non-burst writes. For example, a 32-bit write to an 8-bit port takes four byte writes. + * 0b1..Enabled. Enables burst write of data larger than the specified port size, including 32-bit writes to 8- and 16-bit ports, 16-bit writes to 8-bit ports, and line writes to 8-, 16-, and 32-bit ports. + */ #define FB_CSCR_BSTW(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_BSTW_SHIFT)) & FB_CSCR_BSTW_MASK) #define FB_CSCR_BSTR_MASK (0x10U) #define FB_CSCR_BSTR_SHIFT (4U) +/*! BSTR - Burst-Read Enable + * 0b0..Disabled. Data exceeding the specified port size is broken into individual, port-sized, non-burst reads. For example, a 32-bit read from an 8-bit port is broken into four 8-bit reads. + * 0b1..Enabled. Enables data burst reads larger than the specified port size, including 32-bit reads from 8- and 16-bit ports, 16-bit reads from 8-bit ports, and line reads from 8-, 16-, and 32-bit ports. + */ #define FB_CSCR_BSTR(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_BSTR_SHIFT)) & FB_CSCR_BSTR_MASK) #define FB_CSCR_BEM_MASK (0x20U) #define FB_CSCR_BEM_SHIFT (5U) +/*! BEM - Byte-Enable Mode + * 0b0..FB_BE is asserted for data write only. + * 0b1..FB_BE is asserted for data read and write accesses. + */ #define FB_CSCR_BEM(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_BEM_SHIFT)) & FB_CSCR_BEM_MASK) #define FB_CSCR_PS_MASK (0xC0U) #define FB_CSCR_PS_SHIFT (6U) +/*! PS - Port Size + * 0b00..32-bit port size. Valid data is sampled and driven on FB_D[31:0]. + * 0b01..8-bit port size. Valid data is sampled and driven on FB_D[31:24] when BLS is 0b, or FB_D[7:0] when BLS is 1b. + * 0b1x..16-bit port size. Valid data is sampled and driven on FB_D[31:16] when BLS is 0b, or FB_D[15:0] when BLS is 1b. + */ #define FB_CSCR_PS(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_PS_SHIFT)) & FB_CSCR_PS_MASK) #define FB_CSCR_AA_MASK (0x100U) #define FB_CSCR_AA_SHIFT (8U) +/*! AA - Auto-Acknowledge Enable + * 0b0..Disabled. No internal transfer acknowledge is asserted and the cycle is terminated externally. + * 0b1..Enabled. Internal transfer acknowledge is asserted as specified by WS. + */ #define FB_CSCR_AA(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_AA_SHIFT)) & FB_CSCR_AA_MASK) #define FB_CSCR_BLS_MASK (0x200U) #define FB_CSCR_BLS_SHIFT (9U) +/*! BLS - Byte-Lane Shift + * 0b0..Not shifted. Data is left-aligned on FB_AD. + * 0b1..Shifted. Data is right-aligned on FB_AD. + */ #define FB_CSCR_BLS(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_BLS_SHIFT)) & FB_CSCR_BLS_MASK) #define FB_CSCR_WS_MASK (0xFC00U) #define FB_CSCR_WS_SHIFT (10U) #define FB_CSCR_WS(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_WS_SHIFT)) & FB_CSCR_WS_MASK) #define FB_CSCR_WRAH_MASK (0x30000U) #define FB_CSCR_WRAH_SHIFT (16U) +/*! WRAH - Write Address Hold or Deselect + * 0b00..1 cycle (default for all but FB_CS0 ) + * 0b01..2 cycles + * 0b10..3 cycles + * 0b11..4 cycles (default for FB_CS0 ) + */ #define FB_CSCR_WRAH(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_WRAH_SHIFT)) & FB_CSCR_WRAH_MASK) #define FB_CSCR_RDAH_MASK (0xC0000U) #define FB_CSCR_RDAH_SHIFT (18U) +/*! RDAH - Read Address Hold or Deselect + * 0b00..When AA is 0b, 1 cycle. When AA is 1b, 0 cycles. + * 0b01..When AA is 0b, 2 cycles. When AA is 1b, 1 cycle. + * 0b10..When AA is 0b, 3 cycles. When AA is 1b, 2 cycles. + * 0b11..When AA is 0b, 4 cycles. When AA is 1b, 3 cycles. + */ #define FB_CSCR_RDAH(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_RDAH_SHIFT)) & FB_CSCR_RDAH_MASK) #define FB_CSCR_ASET_MASK (0x300000U) #define FB_CSCR_ASET_SHIFT (20U) +/*! ASET - Address Setup + * 0b00..Assert FB_CSn on the first rising clock edge after the address is asserted (default for all but FB_CS0 ). + * 0b01..Assert FB_CSn on the second rising clock edge after the address is asserted. + * 0b10..Assert FB_CSn on the third rising clock edge after the address is asserted. + * 0b11..Assert FB_CSn on the fourth rising clock edge after the address is asserted (default for FB_CS0 ). + */ #define FB_CSCR_ASET(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_ASET_SHIFT)) & FB_CSCR_ASET_MASK) #define FB_CSCR_EXTS_MASK (0x400000U) #define FB_CSCR_EXTS_SHIFT (22U) +/*! EXTS + * 0b0..Disabled. FB_TS /FB_ALE asserts for one bus clock cycle. + * 0b1..Enabled. FB_TS /FB_ALE remains asserted until the first positive clock edge after FB_CSn asserts. + */ #define FB_CSCR_EXTS(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_EXTS_SHIFT)) & FB_CSCR_EXTS_MASK) #define FB_CSCR_SWSEN_MASK (0x800000U) #define FB_CSCR_SWSEN_SHIFT (23U) +/*! SWSEN - Secondary Wait State Enable + * 0b0..Disabled. A number of wait states (specified by WS) are inserted before an internal transfer acknowledge is generated for all transfers. + * 0b1..Enabled. A number of wait states (specified by SWS) are inserted before an internal transfer acknowledge is generated for burst transfer secondary terminations. + */ #define FB_CSCR_SWSEN(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_SWSEN_SHIFT)) & FB_CSCR_SWSEN_MASK) #define FB_CSCR_SWS_MASK (0xFC000000U) #define FB_CSCR_SWS_SHIFT (26U) #define FB_CSCR_SWS(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_SWS_SHIFT)) & FB_CSCR_SWS_MASK) +/*! @} */ /* The count of FB_CSCR */ #define FB_CSCR_COUNT (6U) /*! @name CSPMCR - Chip Select port Multiplexing Control Register */ +/*! @{ */ #define FB_CSPMCR_GROUP5_MASK (0xF000U) #define FB_CSPMCR_GROUP5_SHIFT (12U) +/*! GROUP5 - FlexBus Signal Group 5 Multiplex control + * 0b0000..FB_TA + * 0b0001..FB_CS3 . You must also write 1b to CSCR[AA]. + * 0b0010..FB_BE_7_0 . You must also write 1b to CSCR[AA]. + */ #define FB_CSPMCR_GROUP5(x) (((uint32_t)(((uint32_t)(x)) << FB_CSPMCR_GROUP5_SHIFT)) & FB_CSPMCR_GROUP5_MASK) #define FB_CSPMCR_GROUP4_MASK (0xF0000U) #define FB_CSPMCR_GROUP4_SHIFT (16U) +/*! GROUP4 - FlexBus Signal Group 4 Multiplex control + * 0b0000..FB_TBST + * 0b0001..FB_CS2 + * 0b0010..FB_BE_15_8 + */ #define FB_CSPMCR_GROUP4(x) (((uint32_t)(((uint32_t)(x)) << FB_CSPMCR_GROUP4_SHIFT)) & FB_CSPMCR_GROUP4_MASK) #define FB_CSPMCR_GROUP3_MASK (0xF00000U) #define FB_CSPMCR_GROUP3_SHIFT (20U) +/*! GROUP3 - FlexBus Signal Group 3 Multiplex control + * 0b0000..FB_CS5 + * 0b0001..FB_TSIZ1 + * 0b0010..FB_BE_23_16 + */ #define FB_CSPMCR_GROUP3(x) (((uint32_t)(((uint32_t)(x)) << FB_CSPMCR_GROUP3_SHIFT)) & FB_CSPMCR_GROUP3_MASK) #define FB_CSPMCR_GROUP2_MASK (0xF000000U) #define FB_CSPMCR_GROUP2_SHIFT (24U) +/*! GROUP2 - FlexBus Signal Group 2 Multiplex control + * 0b0000..FB_CS4 + * 0b0001..FB_TSIZ0 + * 0b0010..FB_BE_31_24 + */ #define FB_CSPMCR_GROUP2(x) (((uint32_t)(((uint32_t)(x)) << FB_CSPMCR_GROUP2_SHIFT)) & FB_CSPMCR_GROUP2_MASK) #define FB_CSPMCR_GROUP1_MASK (0xF0000000U) #define FB_CSPMCR_GROUP1_SHIFT (28U) +/*! GROUP1 - FlexBus Signal Group 1 Multiplex control + * 0b0000..FB_ALE + * 0b0001..FB_CS1 + * 0b0010..FB_TS + */ #define FB_CSPMCR_GROUP1(x) (((uint32_t)(((uint32_t)(x)) << FB_CSPMCR_GROUP1_SHIFT)) & FB_CSPMCR_GROUP1_MASK) +/*! @} */ /*! @@ -5770,161 +9927,328 @@ typedef struct { */ /*! @name PFAPR - Flash Access Protection Register */ +/*! @{ */ #define FMC_PFAPR_M0AP_MASK (0x3U) #define FMC_PFAPR_M0AP_SHIFT (0U) +/*! M0AP - Master 0 Access Protection + * 0b00..No access may be performed by this master + * 0b01..Only read accesses may be performed by this master + * 0b10..Only write accesses may be performed by this master + * 0b11..Both read and write accesses may be performed by this master + */ #define FMC_PFAPR_M0AP(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M0AP_SHIFT)) & FMC_PFAPR_M0AP_MASK) #define FMC_PFAPR_M1AP_MASK (0xCU) #define FMC_PFAPR_M1AP_SHIFT (2U) +/*! M1AP - Master 1 Access Protection + * 0b00..No access may be performed by this master + * 0b01..Only read accesses may be performed by this master + * 0b10..Only write accesses may be performed by this master + * 0b11..Both read and write accesses may be performed by this master + */ #define FMC_PFAPR_M1AP(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M1AP_SHIFT)) & FMC_PFAPR_M1AP_MASK) #define FMC_PFAPR_M2AP_MASK (0x30U) #define FMC_PFAPR_M2AP_SHIFT (4U) +/*! M2AP - Master 2 Access Protection + * 0b00..No access may be performed by this master + * 0b01..Only read accesses may be performed by this master + * 0b10..Only write accesses may be performed by this master + * 0b11..Both read and write accesses may be performed by this master + */ #define FMC_PFAPR_M2AP(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M2AP_SHIFT)) & FMC_PFAPR_M2AP_MASK) #define FMC_PFAPR_M3AP_MASK (0xC0U) #define FMC_PFAPR_M3AP_SHIFT (6U) +/*! M3AP - Master 3 Access Protection + * 0b00..No access may be performed by this master + * 0b01..Only read accesses may be performed by this master + * 0b10..Only write accesses may be performed by this master + * 0b11..Both read and write accesses may be performed by this master + */ #define FMC_PFAPR_M3AP(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M3AP_SHIFT)) & FMC_PFAPR_M3AP_MASK) #define FMC_PFAPR_M4AP_MASK (0x300U) #define FMC_PFAPR_M4AP_SHIFT (8U) +/*! M4AP - Master 4 Access Protection + * 0b00..No access may be performed by this master + * 0b01..Only read accesses may be performed by this master + * 0b10..Only write accesses may be performed by this master + * 0b11..Both read and write accesses may be performed by this master + */ #define FMC_PFAPR_M4AP(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M4AP_SHIFT)) & FMC_PFAPR_M4AP_MASK) #define FMC_PFAPR_M5AP_MASK (0xC00U) #define FMC_PFAPR_M5AP_SHIFT (10U) +/*! M5AP - Master 5 Access Protection + * 0b00..No access may be performed by this master + * 0b01..Only read accesses may be performed by this master + * 0b10..Only write accesses may be performed by this master + * 0b11..Both read and write accesses may be performed by this master + */ #define FMC_PFAPR_M5AP(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M5AP_SHIFT)) & FMC_PFAPR_M5AP_MASK) #define FMC_PFAPR_M6AP_MASK (0x3000U) #define FMC_PFAPR_M6AP_SHIFT (12U) +/*! M6AP - Master 6 Access Protection + * 0b00..No access may be performed by this master + * 0b01..Only read accesses may be performed by this master + * 0b10..Only write accesses may be performed by this master + * 0b11..Both read and write accesses may be performed by this master + */ #define FMC_PFAPR_M6AP(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M6AP_SHIFT)) & FMC_PFAPR_M6AP_MASK) #define FMC_PFAPR_M7AP_MASK (0xC000U) #define FMC_PFAPR_M7AP_SHIFT (14U) +/*! M7AP - Master 7 Access Protection + * 0b00..No access may be performed by this master. + * 0b01..Only read accesses may be performed by this master. + * 0b10..Only write accesses may be performed by this master. + * 0b11..Both read and write accesses may be performed by this master. + */ #define FMC_PFAPR_M7AP(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M7AP_SHIFT)) & FMC_PFAPR_M7AP_MASK) #define FMC_PFAPR_M0PFD_MASK (0x10000U) #define FMC_PFAPR_M0PFD_SHIFT (16U) +/*! M0PFD - Master 0 Prefetch Disable + * 0b0..Prefetching for this master is enabled. + * 0b1..Prefetching for this master is disabled. + */ #define FMC_PFAPR_M0PFD(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M0PFD_SHIFT)) & FMC_PFAPR_M0PFD_MASK) #define FMC_PFAPR_M1PFD_MASK (0x20000U) #define FMC_PFAPR_M1PFD_SHIFT (17U) +/*! M1PFD - Master 1 Prefetch Disable + * 0b0..Prefetching for this master is enabled. + * 0b1..Prefetching for this master is disabled. + */ #define FMC_PFAPR_M1PFD(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M1PFD_SHIFT)) & FMC_PFAPR_M1PFD_MASK) #define FMC_PFAPR_M2PFD_MASK (0x40000U) #define FMC_PFAPR_M2PFD_SHIFT (18U) +/*! M2PFD - Master 2 Prefetch Disable + * 0b0..Prefetching for this master is enabled. + * 0b1..Prefetching for this master is disabled. + */ #define FMC_PFAPR_M2PFD(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M2PFD_SHIFT)) & FMC_PFAPR_M2PFD_MASK) #define FMC_PFAPR_M3PFD_MASK (0x80000U) #define FMC_PFAPR_M3PFD_SHIFT (19U) +/*! M3PFD - Master 3 Prefetch Disable + * 0b0..Prefetching for this master is enabled. + * 0b1..Prefetching for this master is disabled. + */ #define FMC_PFAPR_M3PFD(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M3PFD_SHIFT)) & FMC_PFAPR_M3PFD_MASK) #define FMC_PFAPR_M4PFD_MASK (0x100000U) #define FMC_PFAPR_M4PFD_SHIFT (20U) +/*! M4PFD - Master 4 Prefetch Disable + * 0b0..Prefetching for this master is enabled. + * 0b1..Prefetching for this master is disabled. + */ #define FMC_PFAPR_M4PFD(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M4PFD_SHIFT)) & FMC_PFAPR_M4PFD_MASK) #define FMC_PFAPR_M5PFD_MASK (0x200000U) #define FMC_PFAPR_M5PFD_SHIFT (21U) +/*! M5PFD - Master 5 Prefetch Disable + * 0b0..Prefetching for this master is enabled. + * 0b1..Prefetching for this master is disabled. + */ #define FMC_PFAPR_M5PFD(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M5PFD_SHIFT)) & FMC_PFAPR_M5PFD_MASK) #define FMC_PFAPR_M6PFD_MASK (0x400000U) #define FMC_PFAPR_M6PFD_SHIFT (22U) +/*! M6PFD - Master 6 Prefetch Disable + * 0b0..Prefetching for this master is enabled. + * 0b1..Prefetching for this master is disabled. + */ #define FMC_PFAPR_M6PFD(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M6PFD_SHIFT)) & FMC_PFAPR_M6PFD_MASK) #define FMC_PFAPR_M7PFD_MASK (0x800000U) #define FMC_PFAPR_M7PFD_SHIFT (23U) +/*! M7PFD - Master 7 Prefetch Disable + * 0b0..Prefetching for this master is enabled. + * 0b1..Prefetching for this master is disabled. + */ #define FMC_PFAPR_M7PFD(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M7PFD_SHIFT)) & FMC_PFAPR_M7PFD_MASK) +/*! @} */ /*! @name PFB0CR - Flash Bank 0 Control Register */ +/*! @{ */ #define FMC_PFB0CR_B0SEBE_MASK (0x1U) #define FMC_PFB0CR_B0SEBE_SHIFT (0U) +/*! B0SEBE - Bank 0 Single Entry Buffer Enable + * 0b0..Single entry buffer is disabled. + * 0b1..Single entry buffer is enabled. + */ #define FMC_PFB0CR_B0SEBE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_B0SEBE_SHIFT)) & FMC_PFB0CR_B0SEBE_MASK) #define FMC_PFB0CR_B0IPE_MASK (0x2U) #define FMC_PFB0CR_B0IPE_SHIFT (1U) +/*! B0IPE - Bank 0 Instruction Prefetch Enable + * 0b0..Do not prefetch in response to instruction fetches. + * 0b1..Enable prefetches in response to instruction fetches. + */ #define FMC_PFB0CR_B0IPE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_B0IPE_SHIFT)) & FMC_PFB0CR_B0IPE_MASK) #define FMC_PFB0CR_B0DPE_MASK (0x4U) #define FMC_PFB0CR_B0DPE_SHIFT (2U) +/*! B0DPE - Bank 0 Data Prefetch Enable + * 0b0..Do not prefetch in response to data references. + * 0b1..Enable prefetches in response to data references. + */ #define FMC_PFB0CR_B0DPE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_B0DPE_SHIFT)) & FMC_PFB0CR_B0DPE_MASK) #define FMC_PFB0CR_B0ICE_MASK (0x8U) #define FMC_PFB0CR_B0ICE_SHIFT (3U) +/*! B0ICE - Bank 0 Instruction Cache Enable + * 0b0..Do not cache instruction fetches. + * 0b1..Cache instruction fetches. + */ #define FMC_PFB0CR_B0ICE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_B0ICE_SHIFT)) & FMC_PFB0CR_B0ICE_MASK) #define FMC_PFB0CR_B0DCE_MASK (0x10U) #define FMC_PFB0CR_B0DCE_SHIFT (4U) +/*! B0DCE - Bank 0 Data Cache Enable + * 0b0..Do not cache data references. + * 0b1..Cache data references. + */ #define FMC_PFB0CR_B0DCE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_B0DCE_SHIFT)) & FMC_PFB0CR_B0DCE_MASK) #define FMC_PFB0CR_CRC_MASK (0xE0U) #define FMC_PFB0CR_CRC_SHIFT (5U) +/*! CRC - Cache Replacement Control + * 0b000..LRU replacement algorithm per set across all four ways + * 0b001..Reserved + * 0b010..Independent LRU with ways [0-1] for ifetches, [2-3] for data + * 0b011..Independent LRU with ways [0-2] for ifetches, [3] for data + * 0b1xx..Reserved + */ #define FMC_PFB0CR_CRC(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_CRC_SHIFT)) & FMC_PFB0CR_CRC_MASK) #define FMC_PFB0CR_B0MW_MASK (0x60000U) #define FMC_PFB0CR_B0MW_SHIFT (17U) +/*! B0MW - Bank 0 Memory Width + * 0b00..32 bits + * 0b01..64 bits + * 0b10..128 bits + * 0b11..Reserved + */ #define FMC_PFB0CR_B0MW(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_B0MW_SHIFT)) & FMC_PFB0CR_B0MW_MASK) #define FMC_PFB0CR_S_B_INV_MASK (0x80000U) #define FMC_PFB0CR_S_B_INV_SHIFT (19U) +/*! S_B_INV - Invalidate Prefetch Speculation Buffer + * 0b0..Speculation buffer and single entry buffer are not affected. + * 0b1..Invalidate (clear) speculation buffer and single entry buffer. + */ #define FMC_PFB0CR_S_B_INV(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_S_B_INV_SHIFT)) & FMC_PFB0CR_S_B_INV_MASK) #define FMC_PFB0CR_CINV_WAY_MASK (0xF00000U) #define FMC_PFB0CR_CINV_WAY_SHIFT (20U) +/*! CINV_WAY - Cache Invalidate Way x + * 0b0000..No cache way invalidation for the corresponding cache + * 0b0001..Invalidate cache way for the corresponding cache: clear the tag, data, and vld bits of ways selected + */ #define FMC_PFB0CR_CINV_WAY(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_CINV_WAY_SHIFT)) & FMC_PFB0CR_CINV_WAY_MASK) #define FMC_PFB0CR_CLCK_WAY_MASK (0xF000000U) #define FMC_PFB0CR_CLCK_WAY_SHIFT (24U) +/*! CLCK_WAY - Cache Lock Way x + * 0b0000..Cache way is unlocked and may be displaced + * 0b0001..Cache way is locked and its contents are not displaced + */ #define FMC_PFB0CR_CLCK_WAY(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_CLCK_WAY_SHIFT)) & FMC_PFB0CR_CLCK_WAY_MASK) #define FMC_PFB0CR_B0RWSC_MASK (0xF0000000U) #define FMC_PFB0CR_B0RWSC_SHIFT (28U) #define FMC_PFB0CR_B0RWSC(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_B0RWSC_SHIFT)) & FMC_PFB0CR_B0RWSC_MASK) +/*! @} */ /*! @name PFB1CR - Flash Bank 1 Control Register */ +/*! @{ */ #define FMC_PFB1CR_B1SEBE_MASK (0x1U) #define FMC_PFB1CR_B1SEBE_SHIFT (0U) +/*! B1SEBE - Bank 1 Single Entry Buffer Enable + * 0b0..Single entry buffer is disabled. + * 0b1..Single entry buffer is enabled. + */ #define FMC_PFB1CR_B1SEBE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB1CR_B1SEBE_SHIFT)) & FMC_PFB1CR_B1SEBE_MASK) #define FMC_PFB1CR_B1IPE_MASK (0x2U) #define FMC_PFB1CR_B1IPE_SHIFT (1U) +/*! B1IPE - Bank 1 Instruction Prefetch Enable + * 0b0..Do not prefetch in response to instruction fetches. + * 0b1..Enable prefetches in response to instruction fetches. + */ #define FMC_PFB1CR_B1IPE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB1CR_B1IPE_SHIFT)) & FMC_PFB1CR_B1IPE_MASK) #define FMC_PFB1CR_B1DPE_MASK (0x4U) #define FMC_PFB1CR_B1DPE_SHIFT (2U) +/*! B1DPE - Bank 1 Data Prefetch Enable + * 0b0..Do not prefetch in response to data references. + * 0b1..Enable prefetches in response to data references. + */ #define FMC_PFB1CR_B1DPE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB1CR_B1DPE_SHIFT)) & FMC_PFB1CR_B1DPE_MASK) #define FMC_PFB1CR_B1ICE_MASK (0x8U) #define FMC_PFB1CR_B1ICE_SHIFT (3U) +/*! B1ICE - Bank 1 Instruction Cache Enable + * 0b0..Do not cache instruction fetches. + * 0b1..Cache instruction fetches. + */ #define FMC_PFB1CR_B1ICE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB1CR_B1ICE_SHIFT)) & FMC_PFB1CR_B1ICE_MASK) #define FMC_PFB1CR_B1DCE_MASK (0x10U) #define FMC_PFB1CR_B1DCE_SHIFT (4U) +/*! B1DCE - Bank 1 Data Cache Enable + * 0b0..Do not cache data references. + * 0b1..Cache data references. + */ #define FMC_PFB1CR_B1DCE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB1CR_B1DCE_SHIFT)) & FMC_PFB1CR_B1DCE_MASK) #define FMC_PFB1CR_B1MW_MASK (0x60000U) #define FMC_PFB1CR_B1MW_SHIFT (17U) +/*! B1MW - Bank 1 Memory Width + * 0b00..32 bits + * 0b01..64 bits + * 0b10..128 bits + * 0b11..Reserved + */ #define FMC_PFB1CR_B1MW(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB1CR_B1MW_SHIFT)) & FMC_PFB1CR_B1MW_MASK) #define FMC_PFB1CR_B1RWSC_MASK (0xF0000000U) #define FMC_PFB1CR_B1RWSC_SHIFT (28U) #define FMC_PFB1CR_B1RWSC(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB1CR_B1RWSC_SHIFT)) & FMC_PFB1CR_B1RWSC_MASK) +/*! @} */ /*! @name TAGVDW0S - Cache Tag Storage */ +/*! @{ */ #define FMC_TAGVDW0S_valid_MASK (0x1U) #define FMC_TAGVDW0S_valid_SHIFT (0U) #define FMC_TAGVDW0S_valid(x) (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW0S_valid_SHIFT)) & FMC_TAGVDW0S_valid_MASK) #define FMC_TAGVDW0S_tag_MASK (0x7FFE0U) #define FMC_TAGVDW0S_tag_SHIFT (5U) #define FMC_TAGVDW0S_tag(x) (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW0S_tag_SHIFT)) & FMC_TAGVDW0S_tag_MASK) +/*! @} */ /* The count of FMC_TAGVDW0S */ #define FMC_TAGVDW0S_COUNT (4U) /*! @name TAGVDW1S - Cache Tag Storage */ +/*! @{ */ #define FMC_TAGVDW1S_valid_MASK (0x1U) #define FMC_TAGVDW1S_valid_SHIFT (0U) #define FMC_TAGVDW1S_valid(x) (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW1S_valid_SHIFT)) & FMC_TAGVDW1S_valid_MASK) #define FMC_TAGVDW1S_tag_MASK (0x7FFE0U) #define FMC_TAGVDW1S_tag_SHIFT (5U) #define FMC_TAGVDW1S_tag(x) (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW1S_tag_SHIFT)) & FMC_TAGVDW1S_tag_MASK) +/*! @} */ /* The count of FMC_TAGVDW1S */ #define FMC_TAGVDW1S_COUNT (4U) /*! @name TAGVDW2S - Cache Tag Storage */ +/*! @{ */ #define FMC_TAGVDW2S_valid_MASK (0x1U) #define FMC_TAGVDW2S_valid_SHIFT (0U) #define FMC_TAGVDW2S_valid(x) (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW2S_valid_SHIFT)) & FMC_TAGVDW2S_valid_MASK) #define FMC_TAGVDW2S_tag_MASK (0x7FFE0U) #define FMC_TAGVDW2S_tag_SHIFT (5U) #define FMC_TAGVDW2S_tag(x) (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW2S_tag_SHIFT)) & FMC_TAGVDW2S_tag_MASK) +/*! @} */ /* The count of FMC_TAGVDW2S */ #define FMC_TAGVDW2S_COUNT (4U) /*! @name TAGVDW3S - Cache Tag Storage */ +/*! @{ */ #define FMC_TAGVDW3S_valid_MASK (0x1U) #define FMC_TAGVDW3S_valid_SHIFT (0U) #define FMC_TAGVDW3S_valid(x) (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW3S_valid_SHIFT)) & FMC_TAGVDW3S_valid_MASK) #define FMC_TAGVDW3S_tag_MASK (0x7FFE0U) #define FMC_TAGVDW3S_tag_SHIFT (5U) #define FMC_TAGVDW3S_tag(x) (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW3S_tag_SHIFT)) & FMC_TAGVDW3S_tag_MASK) +/*! @} */ /* The count of FMC_TAGVDW3S */ #define FMC_TAGVDW3S_COUNT (4U) /*! @name DATA_U - Cache Data Storage (upper word) */ +/*! @{ */ #define FMC_DATA_U_data_MASK (0xFFFFFFFFU) #define FMC_DATA_U_data_SHIFT (0U) #define FMC_DATA_U_data(x) (((uint32_t)(((uint32_t)(x)) << FMC_DATA_U_data_SHIFT)) & FMC_DATA_U_data_MASK) +/*! @} */ /* The count of FMC_DATA_U */ #define FMC_DATA_U_COUNT (4U) @@ -5933,9 +10257,11 @@ typedef struct { #define FMC_DATA_U_COUNT2 (4U) /*! @name DATA_L - Cache Data Storage (lower word) */ +/*! @{ */ #define FMC_DATA_L_data_MASK (0xFFFFFFFFU) #define FMC_DATA_L_data_SHIFT (0U) #define FMC_DATA_L_data(x) (((uint32_t)(((uint32_t)(x)) << FMC_DATA_L_data_SHIFT)) & FMC_DATA_L_data_MASK) +/*! @} */ /* The count of FMC_DATA_L */ #define FMC_DATA_L_COUNT (4U) @@ -6010,156 +10336,296 @@ typedef struct { */ /*! @name FSTAT - Flash Status Register */ +/*! @{ */ #define FTFE_FSTAT_MGSTAT0_MASK (0x1U) #define FTFE_FSTAT_MGSTAT0_SHIFT (0U) #define FTFE_FSTAT_MGSTAT0(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FSTAT_MGSTAT0_SHIFT)) & FTFE_FSTAT_MGSTAT0_MASK) #define FTFE_FSTAT_FPVIOL_MASK (0x10U) #define FTFE_FSTAT_FPVIOL_SHIFT (4U) +/*! FPVIOL - Flash Protection Violation Flag + * 0b0..No protection violation detected + * 0b1..Protection violation detected + */ #define FTFE_FSTAT_FPVIOL(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FSTAT_FPVIOL_SHIFT)) & FTFE_FSTAT_FPVIOL_MASK) #define FTFE_FSTAT_ACCERR_MASK (0x20U) #define FTFE_FSTAT_ACCERR_SHIFT (5U) +/*! ACCERR - Flash Access Error Flag + * 0b0..No access error detected + * 0b1..Access error detected + */ #define FTFE_FSTAT_ACCERR(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FSTAT_ACCERR_SHIFT)) & FTFE_FSTAT_ACCERR_MASK) #define FTFE_FSTAT_RDCOLERR_MASK (0x40U) #define FTFE_FSTAT_RDCOLERR_SHIFT (6U) +/*! RDCOLERR - FTFE Read Collision Error Flag + * 0b0..No collision error detected + * 0b1..Collision error detected + */ #define FTFE_FSTAT_RDCOLERR(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FSTAT_RDCOLERR_SHIFT)) & FTFE_FSTAT_RDCOLERR_MASK) #define FTFE_FSTAT_CCIF_MASK (0x80U) #define FTFE_FSTAT_CCIF_SHIFT (7U) +/*! CCIF - Command Complete Interrupt Flag + * 0b0..FTFE command or EEPROM file system operation in progress + * 0b1..FTFE command or EEPROM file system operation has completed + */ #define FTFE_FSTAT_CCIF(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FSTAT_CCIF_SHIFT)) & FTFE_FSTAT_CCIF_MASK) +/*! @} */ /*! @name FCNFG - Flash Configuration Register */ +/*! @{ */ #define FTFE_FCNFG_EEERDY_MASK (0x1U) #define FTFE_FCNFG_EEERDY_SHIFT (0U) +/*! EEERDY + * 0b0..For devices with FlexNVM: FlexRAM is not available for EEPROM operation. + * 0b1..For devices with FlexNVM: FlexRAM is available for EEPROM operations where: reads from the FlexRAM return data previously written to the FlexRAM in EEPROM mode and writes launch an EEPROM operation to store the written data in the FlexRAM and EEPROM backup. + */ #define FTFE_FCNFG_EEERDY(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_EEERDY_SHIFT)) & FTFE_FCNFG_EEERDY_MASK) #define FTFE_FCNFG_RAMRDY_MASK (0x2U) #define FTFE_FCNFG_RAMRDY_SHIFT (1U) +/*! RAMRDY - RAM Ready + * 0b0..For devices with FlexNVM: FlexRAM is not available for traditional RAM access. For devices without FlexNVM: Programming acceleration RAM is not available. + * 0b1..For devices with FlexNVM: FlexRAM is available as traditional RAM only; writes to the FlexRAM do not trigger EEPROM operations. For devices without FlexNVM: Programming acceleration RAM is available. + */ #define FTFE_FCNFG_RAMRDY(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_RAMRDY_SHIFT)) & FTFE_FCNFG_RAMRDY_MASK) #define FTFE_FCNFG_PFLSH_MASK (0x4U) #define FTFE_FCNFG_PFLSH_SHIFT (2U) +/*! PFLSH - FTFE configuration + * 0b0..For devices with FlexNVM: FTFE configuration supports two program flash blocks and two FlexNVM blocks For devices with program flash only: Reserved + * 0b1..For devices with FlexNVM: Reserved For devices with program flash only: FTFE configuration supports four program flash blocks + */ #define FTFE_FCNFG_PFLSH(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_PFLSH_SHIFT)) & FTFE_FCNFG_PFLSH_MASK) #define FTFE_FCNFG_SWAP_MASK (0x8U) #define FTFE_FCNFG_SWAP_SHIFT (3U) +/*! SWAP - Swap + * 0b0..For devices with FlexNVM: Program flash 0 block is located at relative address 0x0000 For devices with program flash only: Program flash 0 block is located at relative address 0x0000 + * 0b1..For devices with FlexNVM: Reserved For devices with program flash only: Program flash 1 block is located at relative address 0x0000 + */ #define FTFE_FCNFG_SWAP(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_SWAP_SHIFT)) & FTFE_FCNFG_SWAP_MASK) #define FTFE_FCNFG_ERSSUSP_MASK (0x10U) #define FTFE_FCNFG_ERSSUSP_SHIFT (4U) +/*! ERSSUSP - Erase Suspend + * 0b0..No suspend requested + * 0b1..Suspend the current Erase Flash Sector command execution. + */ #define FTFE_FCNFG_ERSSUSP(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_ERSSUSP_SHIFT)) & FTFE_FCNFG_ERSSUSP_MASK) #define FTFE_FCNFG_ERSAREQ_MASK (0x20U) #define FTFE_FCNFG_ERSAREQ_SHIFT (5U) +/*! ERSAREQ - Erase All Request + * 0b0..No request or request complete + * 0b1..Request to: run the Erase All Blocks command, verify the erased state, program the security byte in the Flash Configuration Field to the unsecure state, and release MCU security by setting the FSEC[SEC] field to the unsecure state. + */ #define FTFE_FCNFG_ERSAREQ(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_ERSAREQ_SHIFT)) & FTFE_FCNFG_ERSAREQ_MASK) #define FTFE_FCNFG_RDCOLLIE_MASK (0x40U) #define FTFE_FCNFG_RDCOLLIE_SHIFT (6U) +/*! RDCOLLIE - Read Collision Error Interrupt Enable + * 0b0..Read collision error interrupt disabled + * 0b1..Read collision error interrupt enabled. An interrupt request is generated whenever an FTFE read collision error is detected (see the description of FSTAT[RDCOLERR]). + */ #define FTFE_FCNFG_RDCOLLIE(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_RDCOLLIE_SHIFT)) & FTFE_FCNFG_RDCOLLIE_MASK) #define FTFE_FCNFG_CCIE_MASK (0x80U) #define FTFE_FCNFG_CCIE_SHIFT (7U) +/*! CCIE - Command Complete Interrupt Enable + * 0b0..Command complete interrupt disabled + * 0b1..Command complete interrupt enabled. An interrupt request is generated whenever the FSTAT[CCIF] flag is set. + */ #define FTFE_FCNFG_CCIE(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_CCIE_SHIFT)) & FTFE_FCNFG_CCIE_MASK) +/*! @} */ /*! @name FSEC - Flash Security Register */ +/*! @{ */ #define FTFE_FSEC_SEC_MASK (0x3U) #define FTFE_FSEC_SEC_SHIFT (0U) +/*! SEC - Flash Security + * 0b00..MCU security status is secure + * 0b01..MCU security status is secure + * 0b10..MCU security status is unsecure (The standard shipping condition of the FTFE is unsecure.) + * 0b11..MCU security status is secure + */ #define FTFE_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FSEC_SEC_SHIFT)) & FTFE_FSEC_SEC_MASK) #define FTFE_FSEC_FSLACC_MASK (0xCU) #define FTFE_FSEC_FSLACC_SHIFT (2U) +/*! FSLACC - Freescale Failure Analysis Access Code + * 0b00..Freescale factory access granted + * 0b01..Freescale factory access denied + * 0b10..Freescale factory access denied + * 0b11..Freescale factory access granted + */ #define FTFE_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FSEC_FSLACC_SHIFT)) & FTFE_FSEC_FSLACC_MASK) #define FTFE_FSEC_MEEN_MASK (0x30U) #define FTFE_FSEC_MEEN_SHIFT (4U) +/*! MEEN - Mass Erase Enable Bits + * 0b00..Mass erase is enabled + * 0b01..Mass erase is enabled + * 0b10..Mass erase is disabled + * 0b11..Mass erase is enabled + */ #define FTFE_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FSEC_MEEN_SHIFT)) & FTFE_FSEC_MEEN_MASK) #define FTFE_FSEC_KEYEN_MASK (0xC0U) #define FTFE_FSEC_KEYEN_SHIFT (6U) +/*! KEYEN - Backdoor Key Security Enable + * 0b00..Backdoor key access disabled + * 0b01..Backdoor key access disabled (preferred KEYEN state to disable backdoor key access) + * 0b10..Backdoor key access enabled + * 0b11..Backdoor key access disabled + */ #define FTFE_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FSEC_KEYEN_SHIFT)) & FTFE_FSEC_KEYEN_MASK) +/*! @} */ /*! @name FOPT - Flash Option Register */ +/*! @{ */ #define FTFE_FOPT_OPT_MASK (0xFFU) #define FTFE_FOPT_OPT_SHIFT (0U) #define FTFE_FOPT_OPT(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FOPT_OPT_SHIFT)) & FTFE_FOPT_OPT_MASK) +/*! @} */ /*! @name FCCOB3 - Flash Common Command Object Registers */ +/*! @{ */ #define FTFE_FCCOB3_CCOBn_MASK (0xFFU) #define FTFE_FCCOB3_CCOBn_SHIFT (0U) #define FTFE_FCCOB3_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB3_CCOBn_SHIFT)) & FTFE_FCCOB3_CCOBn_MASK) +/*! @} */ /*! @name FCCOB2 - Flash Common Command Object Registers */ +/*! @{ */ #define FTFE_FCCOB2_CCOBn_MASK (0xFFU) #define FTFE_FCCOB2_CCOBn_SHIFT (0U) #define FTFE_FCCOB2_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB2_CCOBn_SHIFT)) & FTFE_FCCOB2_CCOBn_MASK) +/*! @} */ /*! @name FCCOB1 - Flash Common Command Object Registers */ +/*! @{ */ #define FTFE_FCCOB1_CCOBn_MASK (0xFFU) #define FTFE_FCCOB1_CCOBn_SHIFT (0U) #define FTFE_FCCOB1_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB1_CCOBn_SHIFT)) & FTFE_FCCOB1_CCOBn_MASK) +/*! @} */ /*! @name FCCOB0 - Flash Common Command Object Registers */ +/*! @{ */ #define FTFE_FCCOB0_CCOBn_MASK (0xFFU) #define FTFE_FCCOB0_CCOBn_SHIFT (0U) #define FTFE_FCCOB0_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB0_CCOBn_SHIFT)) & FTFE_FCCOB0_CCOBn_MASK) +/*! @} */ /*! @name FCCOB7 - Flash Common Command Object Registers */ +/*! @{ */ #define FTFE_FCCOB7_CCOBn_MASK (0xFFU) #define FTFE_FCCOB7_CCOBn_SHIFT (0U) #define FTFE_FCCOB7_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB7_CCOBn_SHIFT)) & FTFE_FCCOB7_CCOBn_MASK) +/*! @} */ /*! @name FCCOB6 - Flash Common Command Object Registers */ +/*! @{ */ #define FTFE_FCCOB6_CCOBn_MASK (0xFFU) #define FTFE_FCCOB6_CCOBn_SHIFT (0U) #define FTFE_FCCOB6_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB6_CCOBn_SHIFT)) & FTFE_FCCOB6_CCOBn_MASK) +/*! @} */ /*! @name FCCOB5 - Flash Common Command Object Registers */ +/*! @{ */ #define FTFE_FCCOB5_CCOBn_MASK (0xFFU) #define FTFE_FCCOB5_CCOBn_SHIFT (0U) #define FTFE_FCCOB5_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB5_CCOBn_SHIFT)) & FTFE_FCCOB5_CCOBn_MASK) +/*! @} */ /*! @name FCCOB4 - Flash Common Command Object Registers */ +/*! @{ */ #define FTFE_FCCOB4_CCOBn_MASK (0xFFU) #define FTFE_FCCOB4_CCOBn_SHIFT (0U) #define FTFE_FCCOB4_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB4_CCOBn_SHIFT)) & FTFE_FCCOB4_CCOBn_MASK) +/*! @} */ /*! @name FCCOBB - Flash Common Command Object Registers */ +/*! @{ */ #define FTFE_FCCOBB_CCOBn_MASK (0xFFU) #define FTFE_FCCOBB_CCOBn_SHIFT (0U) #define FTFE_FCCOBB_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOBB_CCOBn_SHIFT)) & FTFE_FCCOBB_CCOBn_MASK) +/*! @} */ /*! @name FCCOBA - Flash Common Command Object Registers */ +/*! @{ */ #define FTFE_FCCOBA_CCOBn_MASK (0xFFU) #define FTFE_FCCOBA_CCOBn_SHIFT (0U) #define FTFE_FCCOBA_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOBA_CCOBn_SHIFT)) & FTFE_FCCOBA_CCOBn_MASK) +/*! @} */ /*! @name FCCOB9 - Flash Common Command Object Registers */ +/*! @{ */ #define FTFE_FCCOB9_CCOBn_MASK (0xFFU) #define FTFE_FCCOB9_CCOBn_SHIFT (0U) #define FTFE_FCCOB9_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB9_CCOBn_SHIFT)) & FTFE_FCCOB9_CCOBn_MASK) +/*! @} */ /*! @name FCCOB8 - Flash Common Command Object Registers */ +/*! @{ */ #define FTFE_FCCOB8_CCOBn_MASK (0xFFU) #define FTFE_FCCOB8_CCOBn_SHIFT (0U) #define FTFE_FCCOB8_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB8_CCOBn_SHIFT)) & FTFE_FCCOB8_CCOBn_MASK) +/*! @} */ /*! @name FPROT3 - Program Flash Protection Registers */ +/*! @{ */ #define FTFE_FPROT3_PROT_MASK (0xFFU) #define FTFE_FPROT3_PROT_SHIFT (0U) +/*! PROT - Program Flash Region Protect + * 0b00000000..Program flash region is protected. + * 0b00000001..Program flash region is not protected + */ #define FTFE_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FPROT3_PROT_SHIFT)) & FTFE_FPROT3_PROT_MASK) +/*! @} */ /*! @name FPROT2 - Program Flash Protection Registers */ +/*! @{ */ #define FTFE_FPROT2_PROT_MASK (0xFFU) #define FTFE_FPROT2_PROT_SHIFT (0U) +/*! PROT - Program Flash Region Protect + * 0b00000000..Program flash region is protected. + * 0b00000001..Program flash region is not protected + */ #define FTFE_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FPROT2_PROT_SHIFT)) & FTFE_FPROT2_PROT_MASK) +/*! @} */ /*! @name FPROT1 - Program Flash Protection Registers */ +/*! @{ */ #define FTFE_FPROT1_PROT_MASK (0xFFU) #define FTFE_FPROT1_PROT_SHIFT (0U) +/*! PROT - Program Flash Region Protect + * 0b00000000..Program flash region is protected. + * 0b00000001..Program flash region is not protected + */ #define FTFE_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FPROT1_PROT_SHIFT)) & FTFE_FPROT1_PROT_MASK) +/*! @} */ /*! @name FPROT0 - Program Flash Protection Registers */ +/*! @{ */ #define FTFE_FPROT0_PROT_MASK (0xFFU) #define FTFE_FPROT0_PROT_SHIFT (0U) +/*! PROT - Program Flash Region Protect + * 0b00000000..Program flash region is protected. + * 0b00000001..Program flash region is not protected + */ #define FTFE_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FPROT0_PROT_SHIFT)) & FTFE_FPROT0_PROT_MASK) +/*! @} */ /*! @name FEPROT - EEPROM Protection Register */ +/*! @{ */ #define FTFE_FEPROT_EPROT_MASK (0xFFU) #define FTFE_FEPROT_EPROT_SHIFT (0U) +/*! EPROT - EEPROM Region Protect + * 0b00000000..For devices with program flash only: Reserved For devices with FlexNVM: EEPROM region is protected + * 0b00000001..For devices with program flash only: Reserved For devices with FlexNVM: EEPROM region is not protected + */ #define FTFE_FEPROT_EPROT(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FEPROT_EPROT_SHIFT)) & FTFE_FEPROT_EPROT_MASK) +/*! @} */ /*! @name FDPROT - Data Flash Protection Register */ +/*! @{ */ #define FTFE_FDPROT_DPROT_MASK (0xFFU) #define FTFE_FDPROT_DPROT_SHIFT (0U) +/*! DPROT - Data Flash Region Protect + * 0b00000000..Data Flash region is protected + * 0b00000001..Data Flash region is not protected + */ #define FTFE_FDPROT_DPROT(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FDPROT_DPROT_SHIFT)) & FTFE_FDPROT_DPROT_MASK) +/*! @} */ /*! @@ -6235,35 +10701,74 @@ typedef struct { */ /*! @name SC - Status And Control */ +/*! @{ */ #define FTM_SC_PS_MASK (0x7U) #define FTM_SC_PS_SHIFT (0U) +/*! PS - Prescale Factor Selection + * 0b000..Divide by 1 + * 0b001..Divide by 2 + * 0b010..Divide by 4 + * 0b011..Divide by 8 + * 0b100..Divide by 16 + * 0b101..Divide by 32 + * 0b110..Divide by 64 + * 0b111..Divide by 128 + */ #define FTM_SC_PS(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_PS_SHIFT)) & FTM_SC_PS_MASK) #define FTM_SC_CLKS_MASK (0x18U) #define FTM_SC_CLKS_SHIFT (3U) +/*! CLKS - Clock Source Selection + * 0b00..No clock selected. This in effect disables the FTM counter. + * 0b01..System clock + * 0b10..Fixed frequency clock + * 0b11..External clock + */ #define FTM_SC_CLKS(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_CLKS_SHIFT)) & FTM_SC_CLKS_MASK) #define FTM_SC_CPWMS_MASK (0x20U) #define FTM_SC_CPWMS_SHIFT (5U) +/*! CPWMS - Center-Aligned PWM Select + * 0b0..FTM counter operates in Up Counting mode. + * 0b1..FTM counter operates in Up-Down Counting mode. + */ #define FTM_SC_CPWMS(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_CPWMS_SHIFT)) & FTM_SC_CPWMS_MASK) #define FTM_SC_TOIE_MASK (0x40U) #define FTM_SC_TOIE_SHIFT (6U) +/*! TOIE - Timer Overflow Interrupt Enable + * 0b0..Disable TOF interrupts. Use software polling. + * 0b1..Enable TOF interrupts. An interrupt is generated when TOF equals one. + */ #define FTM_SC_TOIE(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_TOIE_SHIFT)) & FTM_SC_TOIE_MASK) #define FTM_SC_TOF_MASK (0x80U) #define FTM_SC_TOF_SHIFT (7U) +/*! TOF - Timer Overflow Flag + * 0b0..FTM counter has not overflowed. + * 0b1..FTM counter has overflowed. + */ #define FTM_SC_TOF(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_TOF_SHIFT)) & FTM_SC_TOF_MASK) +/*! @} */ /*! @name CNT - Counter */ +/*! @{ */ #define FTM_CNT_COUNT_MASK (0xFFFFU) #define FTM_CNT_COUNT_SHIFT (0U) #define FTM_CNT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << FTM_CNT_COUNT_SHIFT)) & FTM_CNT_COUNT_MASK) +/*! @} */ /*! @name MOD - Modulo */ +/*! @{ */ #define FTM_MOD_MOD_MASK (0xFFFFU) #define FTM_MOD_MOD_SHIFT (0U) #define FTM_MOD_MOD(x) (((uint32_t)(((uint32_t)(x)) << FTM_MOD_MOD_SHIFT)) & FTM_MOD_MOD_MASK) +/*! @} */ /*! @name CnSC - Channel (n) Status And Control */ +/*! @{ */ #define FTM_CnSC_DMA_MASK (0x1U) #define FTM_CnSC_DMA_SHIFT (0U) +/*! DMA - DMA Enable + * 0b0..Disable DMA transfers. + * 0b1..Enable DMA transfers. + */ #define FTM_CnSC_DMA(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_DMA_SHIFT)) & FTM_CnSC_DMA_MASK) #define FTM_CnSC_ELSA_MASK (0x4U) #define FTM_CnSC_ELSA_SHIFT (2U) @@ -6279,324 +10784,721 @@ typedef struct { #define FTM_CnSC_MSB(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_MSB_SHIFT)) & FTM_CnSC_MSB_MASK) #define FTM_CnSC_CHIE_MASK (0x40U) #define FTM_CnSC_CHIE_SHIFT (6U) +/*! CHIE - Channel Interrupt Enable + * 0b0..Disable channel interrupts. Use software polling. + * 0b1..Enable channel interrupts. + */ #define FTM_CnSC_CHIE(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_CHIE_SHIFT)) & FTM_CnSC_CHIE_MASK) #define FTM_CnSC_CHF_MASK (0x80U) #define FTM_CnSC_CHF_SHIFT (7U) +/*! CHF - Channel Flag + * 0b0..No channel event has occurred. + * 0b1..A channel event has occurred. + */ #define FTM_CnSC_CHF(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_CHF_SHIFT)) & FTM_CnSC_CHF_MASK) +/*! @} */ /* The count of FTM_CnSC */ #define FTM_CnSC_COUNT (8U) /*! @name CnV - Channel (n) Value */ +/*! @{ */ #define FTM_CnV_VAL_MASK (0xFFFFU) #define FTM_CnV_VAL_SHIFT (0U) #define FTM_CnV_VAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnV_VAL_SHIFT)) & FTM_CnV_VAL_MASK) +/*! @} */ /* The count of FTM_CnV */ #define FTM_CnV_COUNT (8U) /*! @name CNTIN - Counter Initial Value */ +/*! @{ */ #define FTM_CNTIN_INIT_MASK (0xFFFFU) #define FTM_CNTIN_INIT_SHIFT (0U) #define FTM_CNTIN_INIT(x) (((uint32_t)(((uint32_t)(x)) << FTM_CNTIN_INIT_SHIFT)) & FTM_CNTIN_INIT_MASK) +/*! @} */ /*! @name STATUS - Capture And Compare Status */ +/*! @{ */ #define FTM_STATUS_CH0F_MASK (0x1U) #define FTM_STATUS_CH0F_SHIFT (0U) +/*! CH0F - Channel 0 Flag + * 0b0..No channel event has occurred. + * 0b1..A channel event has occurred. + */ #define FTM_STATUS_CH0F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH0F_SHIFT)) & FTM_STATUS_CH0F_MASK) #define FTM_STATUS_CH1F_MASK (0x2U) #define FTM_STATUS_CH1F_SHIFT (1U) +/*! CH1F - Channel 1 Flag + * 0b0..No channel event has occurred. + * 0b1..A channel event has occurred. + */ #define FTM_STATUS_CH1F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH1F_SHIFT)) & FTM_STATUS_CH1F_MASK) #define FTM_STATUS_CH2F_MASK (0x4U) #define FTM_STATUS_CH2F_SHIFT (2U) +/*! CH2F - Channel 2 Flag + * 0b0..No channel event has occurred. + * 0b1..A channel event has occurred. + */ #define FTM_STATUS_CH2F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH2F_SHIFT)) & FTM_STATUS_CH2F_MASK) #define FTM_STATUS_CH3F_MASK (0x8U) #define FTM_STATUS_CH3F_SHIFT (3U) +/*! CH3F - Channel 3 Flag + * 0b0..No channel event has occurred. + * 0b1..A channel event has occurred. + */ #define FTM_STATUS_CH3F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH3F_SHIFT)) & FTM_STATUS_CH3F_MASK) #define FTM_STATUS_CH4F_MASK (0x10U) #define FTM_STATUS_CH4F_SHIFT (4U) +/*! CH4F - Channel 4 Flag + * 0b0..No channel event has occurred. + * 0b1..A channel event has occurred. + */ #define FTM_STATUS_CH4F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH4F_SHIFT)) & FTM_STATUS_CH4F_MASK) #define FTM_STATUS_CH5F_MASK (0x20U) #define FTM_STATUS_CH5F_SHIFT (5U) +/*! CH5F - Channel 5 Flag + * 0b0..No channel event has occurred. + * 0b1..A channel event has occurred. + */ #define FTM_STATUS_CH5F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH5F_SHIFT)) & FTM_STATUS_CH5F_MASK) #define FTM_STATUS_CH6F_MASK (0x40U) #define FTM_STATUS_CH6F_SHIFT (6U) +/*! CH6F - Channel 6 Flag + * 0b0..No channel event has occurred. + * 0b1..A channel event has occurred. + */ #define FTM_STATUS_CH6F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH6F_SHIFT)) & FTM_STATUS_CH6F_MASK) #define FTM_STATUS_CH7F_MASK (0x80U) #define FTM_STATUS_CH7F_SHIFT (7U) +/*! CH7F - Channel 7 Flag + * 0b0..No channel event has occurred. + * 0b1..A channel event has occurred. + */ #define FTM_STATUS_CH7F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH7F_SHIFT)) & FTM_STATUS_CH7F_MASK) +/*! @} */ /*! @name MODE - Features Mode Selection */ +/*! @{ */ #define FTM_MODE_FTMEN_MASK (0x1U) #define FTM_MODE_FTMEN_SHIFT (0U) +/*! FTMEN - FTM Enable + * 0b0..Only the TPM-compatible registers (first set of registers) can be used without any restriction. Do not use the FTM-specific registers. + * 0b1..All registers including the FTM-specific registers (second set of registers) are available for use with no restrictions. + */ #define FTM_MODE_FTMEN(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_FTMEN_SHIFT)) & FTM_MODE_FTMEN_MASK) #define FTM_MODE_INIT_MASK (0x2U) #define FTM_MODE_INIT_SHIFT (1U) #define FTM_MODE_INIT(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_INIT_SHIFT)) & FTM_MODE_INIT_MASK) #define FTM_MODE_WPDIS_MASK (0x4U) #define FTM_MODE_WPDIS_SHIFT (2U) +/*! WPDIS - Write Protection Disable + * 0b0..Write protection is enabled. + * 0b1..Write protection is disabled. + */ #define FTM_MODE_WPDIS(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_WPDIS_SHIFT)) & FTM_MODE_WPDIS_MASK) #define FTM_MODE_PWMSYNC_MASK (0x8U) #define FTM_MODE_PWMSYNC_SHIFT (3U) +/*! PWMSYNC - PWM Synchronization Mode + * 0b0..No restrictions. Software and hardware triggers can be used by MOD, CnV, OUTMASK, and FTM counter synchronization. + * 0b1..Software trigger can only be used by MOD and CnV synchronization, and hardware triggers can only be used by OUTMASK and FTM counter synchronization. + */ #define FTM_MODE_PWMSYNC(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_PWMSYNC_SHIFT)) & FTM_MODE_PWMSYNC_MASK) #define FTM_MODE_CAPTEST_MASK (0x10U) #define FTM_MODE_CAPTEST_SHIFT (4U) +/*! CAPTEST - Capture Test Mode Enable + * 0b0..Capture test mode is disabled. + * 0b1..Capture test mode is enabled. + */ #define FTM_MODE_CAPTEST(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_CAPTEST_SHIFT)) & FTM_MODE_CAPTEST_MASK) #define FTM_MODE_FAULTM_MASK (0x60U) #define FTM_MODE_FAULTM_SHIFT (5U) +/*! FAULTM - Fault Control Mode + * 0b00..Fault control is disabled for all channels. + * 0b01..Fault control is enabled for even channels only (channels 0, 2, 4, and 6), and the selected mode is the manual fault clearing. + * 0b10..Fault control is enabled for all channels, and the selected mode is the manual fault clearing. + * 0b11..Fault control is enabled for all channels, and the selected mode is the automatic fault clearing. + */ #define FTM_MODE_FAULTM(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_FAULTM_SHIFT)) & FTM_MODE_FAULTM_MASK) #define FTM_MODE_FAULTIE_MASK (0x80U) #define FTM_MODE_FAULTIE_SHIFT (7U) +/*! FAULTIE - Fault Interrupt Enable + * 0b0..Fault control interrupt is disabled. + * 0b1..Fault control interrupt is enabled. + */ #define FTM_MODE_FAULTIE(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_FAULTIE_SHIFT)) & FTM_MODE_FAULTIE_MASK) +/*! @} */ /*! @name SYNC - Synchronization */ +/*! @{ */ #define FTM_SYNC_CNTMIN_MASK (0x1U) #define FTM_SYNC_CNTMIN_SHIFT (0U) +/*! CNTMIN - Minimum Loading Point Enable + * 0b0..The minimum loading point is disabled. + * 0b1..The minimum loading point is enabled. + */ #define FTM_SYNC_CNTMIN(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_CNTMIN_SHIFT)) & FTM_SYNC_CNTMIN_MASK) #define FTM_SYNC_CNTMAX_MASK (0x2U) #define FTM_SYNC_CNTMAX_SHIFT (1U) +/*! CNTMAX - Maximum Loading Point Enable + * 0b0..The maximum loading point is disabled. + * 0b1..The maximum loading point is enabled. + */ #define FTM_SYNC_CNTMAX(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_CNTMAX_SHIFT)) & FTM_SYNC_CNTMAX_MASK) #define FTM_SYNC_REINIT_MASK (0x4U) #define FTM_SYNC_REINIT_SHIFT (2U) +/*! REINIT - FTM Counter Reinitialization By Synchronization (FTM counter synchronization) + * 0b0..FTM counter continues to count normally. + * 0b1..FTM counter is updated with its initial value when the selected trigger is detected. + */ #define FTM_SYNC_REINIT(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_REINIT_SHIFT)) & FTM_SYNC_REINIT_MASK) #define FTM_SYNC_SYNCHOM_MASK (0x8U) #define FTM_SYNC_SYNCHOM_SHIFT (3U) +/*! SYNCHOM - Output Mask Synchronization + * 0b0..OUTMASK register is updated with the value of its buffer in all rising edges of the system clock. + * 0b1..OUTMASK register is updated with the value of its buffer only by the PWM synchronization. + */ #define FTM_SYNC_SYNCHOM(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_SYNCHOM_SHIFT)) & FTM_SYNC_SYNCHOM_MASK) #define FTM_SYNC_TRIG0_MASK (0x10U) #define FTM_SYNC_TRIG0_SHIFT (4U) +/*! TRIG0 - PWM Synchronization Hardware Trigger 0 + * 0b0..Trigger is disabled. + * 0b1..Trigger is enabled. + */ #define FTM_SYNC_TRIG0(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_TRIG0_SHIFT)) & FTM_SYNC_TRIG0_MASK) #define FTM_SYNC_TRIG1_MASK (0x20U) #define FTM_SYNC_TRIG1_SHIFT (5U) +/*! TRIG1 - PWM Synchronization Hardware Trigger 1 + * 0b0..Trigger is disabled. + * 0b1..Trigger is enabled. + */ #define FTM_SYNC_TRIG1(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_TRIG1_SHIFT)) & FTM_SYNC_TRIG1_MASK) #define FTM_SYNC_TRIG2_MASK (0x40U) #define FTM_SYNC_TRIG2_SHIFT (6U) +/*! TRIG2 - PWM Synchronization Hardware Trigger 2 + * 0b0..Trigger is disabled. + * 0b1..Trigger is enabled. + */ #define FTM_SYNC_TRIG2(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_TRIG2_SHIFT)) & FTM_SYNC_TRIG2_MASK) #define FTM_SYNC_SWSYNC_MASK (0x80U) #define FTM_SYNC_SWSYNC_SHIFT (7U) +/*! SWSYNC - PWM Synchronization Software Trigger + * 0b0..Software trigger is not selected. + * 0b1..Software trigger is selected. + */ #define FTM_SYNC_SWSYNC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_SWSYNC_SHIFT)) & FTM_SYNC_SWSYNC_MASK) +/*! @} */ /*! @name OUTINIT - Initial State For Channels Output */ +/*! @{ */ #define FTM_OUTINIT_CH0OI_MASK (0x1U) #define FTM_OUTINIT_CH0OI_SHIFT (0U) +/*! CH0OI - Channel 0 Output Initialization Value + * 0b0..The initialization value is 0. + * 0b1..The initialization value is 1. + */ #define FTM_OUTINIT_CH0OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH0OI_SHIFT)) & FTM_OUTINIT_CH0OI_MASK) #define FTM_OUTINIT_CH1OI_MASK (0x2U) #define FTM_OUTINIT_CH1OI_SHIFT (1U) +/*! CH1OI - Channel 1 Output Initialization Value + * 0b0..The initialization value is 0. + * 0b1..The initialization value is 1. + */ #define FTM_OUTINIT_CH1OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH1OI_SHIFT)) & FTM_OUTINIT_CH1OI_MASK) #define FTM_OUTINIT_CH2OI_MASK (0x4U) #define FTM_OUTINIT_CH2OI_SHIFT (2U) +/*! CH2OI - Channel 2 Output Initialization Value + * 0b0..The initialization value is 0. + * 0b1..The initialization value is 1. + */ #define FTM_OUTINIT_CH2OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH2OI_SHIFT)) & FTM_OUTINIT_CH2OI_MASK) #define FTM_OUTINIT_CH3OI_MASK (0x8U) #define FTM_OUTINIT_CH3OI_SHIFT (3U) +/*! CH3OI - Channel 3 Output Initialization Value + * 0b0..The initialization value is 0. + * 0b1..The initialization value is 1. + */ #define FTM_OUTINIT_CH3OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH3OI_SHIFT)) & FTM_OUTINIT_CH3OI_MASK) #define FTM_OUTINIT_CH4OI_MASK (0x10U) #define FTM_OUTINIT_CH4OI_SHIFT (4U) +/*! CH4OI - Channel 4 Output Initialization Value + * 0b0..The initialization value is 0. + * 0b1..The initialization value is 1. + */ #define FTM_OUTINIT_CH4OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH4OI_SHIFT)) & FTM_OUTINIT_CH4OI_MASK) #define FTM_OUTINIT_CH5OI_MASK (0x20U) #define FTM_OUTINIT_CH5OI_SHIFT (5U) +/*! CH5OI - Channel 5 Output Initialization Value + * 0b0..The initialization value is 0. + * 0b1..The initialization value is 1. + */ #define FTM_OUTINIT_CH5OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH5OI_SHIFT)) & FTM_OUTINIT_CH5OI_MASK) #define FTM_OUTINIT_CH6OI_MASK (0x40U) #define FTM_OUTINIT_CH6OI_SHIFT (6U) +/*! CH6OI - Channel 6 Output Initialization Value + * 0b0..The initialization value is 0. + * 0b1..The initialization value is 1. + */ #define FTM_OUTINIT_CH6OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH6OI_SHIFT)) & FTM_OUTINIT_CH6OI_MASK) #define FTM_OUTINIT_CH7OI_MASK (0x80U) #define FTM_OUTINIT_CH7OI_SHIFT (7U) +/*! CH7OI - Channel 7 Output Initialization Value + * 0b0..The initialization value is 0. + * 0b1..The initialization value is 1. + */ #define FTM_OUTINIT_CH7OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH7OI_SHIFT)) & FTM_OUTINIT_CH7OI_MASK) +/*! @} */ /*! @name OUTMASK - Output Mask */ +/*! @{ */ #define FTM_OUTMASK_CH0OM_MASK (0x1U) #define FTM_OUTMASK_CH0OM_SHIFT (0U) +/*! CH0OM - Channel 0 Output Mask + * 0b0..Channel output is not masked. It continues to operate normally. + * 0b1..Channel output is masked. It is forced to its inactive state. + */ #define FTM_OUTMASK_CH0OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH0OM_SHIFT)) & FTM_OUTMASK_CH0OM_MASK) #define FTM_OUTMASK_CH1OM_MASK (0x2U) #define FTM_OUTMASK_CH1OM_SHIFT (1U) +/*! CH1OM - Channel 1 Output Mask + * 0b0..Channel output is not masked. It continues to operate normally. + * 0b1..Channel output is masked. It is forced to its inactive state. + */ #define FTM_OUTMASK_CH1OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH1OM_SHIFT)) & FTM_OUTMASK_CH1OM_MASK) #define FTM_OUTMASK_CH2OM_MASK (0x4U) #define FTM_OUTMASK_CH2OM_SHIFT (2U) +/*! CH2OM - Channel 2 Output Mask + * 0b0..Channel output is not masked. It continues to operate normally. + * 0b1..Channel output is masked. It is forced to its inactive state. + */ #define FTM_OUTMASK_CH2OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH2OM_SHIFT)) & FTM_OUTMASK_CH2OM_MASK) #define FTM_OUTMASK_CH3OM_MASK (0x8U) #define FTM_OUTMASK_CH3OM_SHIFT (3U) +/*! CH3OM - Channel 3 Output Mask + * 0b0..Channel output is not masked. It continues to operate normally. + * 0b1..Channel output is masked. It is forced to its inactive state. + */ #define FTM_OUTMASK_CH3OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH3OM_SHIFT)) & FTM_OUTMASK_CH3OM_MASK) #define FTM_OUTMASK_CH4OM_MASK (0x10U) #define FTM_OUTMASK_CH4OM_SHIFT (4U) +/*! CH4OM - Channel 4 Output Mask + * 0b0..Channel output is not masked. It continues to operate normally. + * 0b1..Channel output is masked. It is forced to its inactive state. + */ #define FTM_OUTMASK_CH4OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH4OM_SHIFT)) & FTM_OUTMASK_CH4OM_MASK) #define FTM_OUTMASK_CH5OM_MASK (0x20U) #define FTM_OUTMASK_CH5OM_SHIFT (5U) +/*! CH5OM - Channel 5 Output Mask + * 0b0..Channel output is not masked. It continues to operate normally. + * 0b1..Channel output is masked. It is forced to its inactive state. + */ #define FTM_OUTMASK_CH5OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH5OM_SHIFT)) & FTM_OUTMASK_CH5OM_MASK) #define FTM_OUTMASK_CH6OM_MASK (0x40U) #define FTM_OUTMASK_CH6OM_SHIFT (6U) +/*! CH6OM - Channel 6 Output Mask + * 0b0..Channel output is not masked. It continues to operate normally. + * 0b1..Channel output is masked. It is forced to its inactive state. + */ #define FTM_OUTMASK_CH6OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH6OM_SHIFT)) & FTM_OUTMASK_CH6OM_MASK) #define FTM_OUTMASK_CH7OM_MASK (0x80U) #define FTM_OUTMASK_CH7OM_SHIFT (7U) +/*! CH7OM - Channel 7 Output Mask + * 0b0..Channel output is not masked. It continues to operate normally. + * 0b1..Channel output is masked. It is forced to its inactive state. + */ #define FTM_OUTMASK_CH7OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH7OM_SHIFT)) & FTM_OUTMASK_CH7OM_MASK) +/*! @} */ /*! @name COMBINE - Function For Linked Channels */ +/*! @{ */ #define FTM_COMBINE_COMBINE0_MASK (0x1U) #define FTM_COMBINE_COMBINE0_SHIFT (0U) +/*! COMBINE0 - Combine Channels For n = 0 + * 0b0..Channels (n) and (n+1) are independent. + * 0b1..Channels (n) and (n+1) are combined. + */ #define FTM_COMBINE_COMBINE0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMBINE0_SHIFT)) & FTM_COMBINE_COMBINE0_MASK) #define FTM_COMBINE_COMP0_MASK (0x2U) #define FTM_COMBINE_COMP0_SHIFT (1U) +/*! COMP0 - Complement Of Channel (n) For n = 0 + * 0b0..The channel (n+1) output is the same as the channel (n) output. + * 0b1..The channel (n+1) output is the complement of the channel (n) output. + */ #define FTM_COMBINE_COMP0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMP0_SHIFT)) & FTM_COMBINE_COMP0_MASK) #define FTM_COMBINE_DECAPEN0_MASK (0x4U) #define FTM_COMBINE_DECAPEN0_SHIFT (2U) +/*! DECAPEN0 - Dual Edge Capture Mode Enable For n = 0 + * 0b0..The Dual Edge Capture mode in this pair of channels is disabled. + * 0b1..The Dual Edge Capture mode in this pair of channels is enabled. + */ #define FTM_COMBINE_DECAPEN0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAPEN0_SHIFT)) & FTM_COMBINE_DECAPEN0_MASK) #define FTM_COMBINE_DECAP0_MASK (0x8U) #define FTM_COMBINE_DECAP0_SHIFT (3U) +/*! DECAP0 - Dual Edge Capture Mode Captures For n = 0 + * 0b0..The dual edge captures are inactive. + * 0b1..The dual edge captures are active. + */ #define FTM_COMBINE_DECAP0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAP0_SHIFT)) & FTM_COMBINE_DECAP0_MASK) #define FTM_COMBINE_DTEN0_MASK (0x10U) #define FTM_COMBINE_DTEN0_SHIFT (4U) +/*! DTEN0 - Deadtime Enable For n = 0 + * 0b0..The deadtime insertion in this pair of channels is disabled. + * 0b1..The deadtime insertion in this pair of channels is enabled. + */ #define FTM_COMBINE_DTEN0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DTEN0_SHIFT)) & FTM_COMBINE_DTEN0_MASK) #define FTM_COMBINE_SYNCEN0_MASK (0x20U) #define FTM_COMBINE_SYNCEN0_SHIFT (5U) +/*! SYNCEN0 - Synchronization Enable For n = 0 + * 0b0..The PWM synchronization in this pair of channels is disabled. + * 0b1..The PWM synchronization in this pair of channels is enabled. + */ #define FTM_COMBINE_SYNCEN0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_SYNCEN0_SHIFT)) & FTM_COMBINE_SYNCEN0_MASK) #define FTM_COMBINE_FAULTEN0_MASK (0x40U) #define FTM_COMBINE_FAULTEN0_SHIFT (6U) +/*! FAULTEN0 - Fault Control Enable For n = 0 + * 0b0..The fault control in this pair of channels is disabled. + * 0b1..The fault control in this pair of channels is enabled. + */ #define FTM_COMBINE_FAULTEN0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_FAULTEN0_SHIFT)) & FTM_COMBINE_FAULTEN0_MASK) #define FTM_COMBINE_COMBINE1_MASK (0x100U) #define FTM_COMBINE_COMBINE1_SHIFT (8U) +/*! COMBINE1 - Combine Channels For n = 2 + * 0b0..Channels (n) and (n+1) are independent. + * 0b1..Channels (n) and (n+1) are combined. + */ #define FTM_COMBINE_COMBINE1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMBINE1_SHIFT)) & FTM_COMBINE_COMBINE1_MASK) #define FTM_COMBINE_COMP1_MASK (0x200U) #define FTM_COMBINE_COMP1_SHIFT (9U) +/*! COMP1 - Complement Of Channel (n) For n = 2 + * 0b0..The channel (n+1) output is the same as the channel (n) output. + * 0b1..The channel (n+1) output is the complement of the channel (n) output. + */ #define FTM_COMBINE_COMP1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMP1_SHIFT)) & FTM_COMBINE_COMP1_MASK) #define FTM_COMBINE_DECAPEN1_MASK (0x400U) #define FTM_COMBINE_DECAPEN1_SHIFT (10U) +/*! DECAPEN1 - Dual Edge Capture Mode Enable For n = 2 + * 0b0..The Dual Edge Capture mode in this pair of channels is disabled. + * 0b1..The Dual Edge Capture mode in this pair of channels is enabled. + */ #define FTM_COMBINE_DECAPEN1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAPEN1_SHIFT)) & FTM_COMBINE_DECAPEN1_MASK) #define FTM_COMBINE_DECAP1_MASK (0x800U) #define FTM_COMBINE_DECAP1_SHIFT (11U) +/*! DECAP1 - Dual Edge Capture Mode Captures For n = 2 + * 0b0..The dual edge captures are inactive. + * 0b1..The dual edge captures are active. + */ #define FTM_COMBINE_DECAP1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAP1_SHIFT)) & FTM_COMBINE_DECAP1_MASK) #define FTM_COMBINE_DTEN1_MASK (0x1000U) #define FTM_COMBINE_DTEN1_SHIFT (12U) +/*! DTEN1 - Deadtime Enable For n = 2 + * 0b0..The deadtime insertion in this pair of channels is disabled. + * 0b1..The deadtime insertion in this pair of channels is enabled. + */ #define FTM_COMBINE_DTEN1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DTEN1_SHIFT)) & FTM_COMBINE_DTEN1_MASK) #define FTM_COMBINE_SYNCEN1_MASK (0x2000U) #define FTM_COMBINE_SYNCEN1_SHIFT (13U) +/*! SYNCEN1 - Synchronization Enable For n = 2 + * 0b0..The PWM synchronization in this pair of channels is disabled. + * 0b1..The PWM synchronization in this pair of channels is enabled. + */ #define FTM_COMBINE_SYNCEN1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_SYNCEN1_SHIFT)) & FTM_COMBINE_SYNCEN1_MASK) #define FTM_COMBINE_FAULTEN1_MASK (0x4000U) #define FTM_COMBINE_FAULTEN1_SHIFT (14U) +/*! FAULTEN1 - Fault Control Enable For n = 2 + * 0b0..The fault control in this pair of channels is disabled. + * 0b1..The fault control in this pair of channels is enabled. + */ #define FTM_COMBINE_FAULTEN1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_FAULTEN1_SHIFT)) & FTM_COMBINE_FAULTEN1_MASK) #define FTM_COMBINE_COMBINE2_MASK (0x10000U) #define FTM_COMBINE_COMBINE2_SHIFT (16U) +/*! COMBINE2 - Combine Channels For n = 4 + * 0b0..Channels (n) and (n+1) are independent. + * 0b1..Channels (n) and (n+1) are combined. + */ #define FTM_COMBINE_COMBINE2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMBINE2_SHIFT)) & FTM_COMBINE_COMBINE2_MASK) #define FTM_COMBINE_COMP2_MASK (0x20000U) #define FTM_COMBINE_COMP2_SHIFT (17U) +/*! COMP2 - Complement Of Channel (n) For n = 4 + * 0b0..The channel (n+1) output is the same as the channel (n) output. + * 0b1..The channel (n+1) output is the complement of the channel (n) output. + */ #define FTM_COMBINE_COMP2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMP2_SHIFT)) & FTM_COMBINE_COMP2_MASK) #define FTM_COMBINE_DECAPEN2_MASK (0x40000U) #define FTM_COMBINE_DECAPEN2_SHIFT (18U) +/*! DECAPEN2 - Dual Edge Capture Mode Enable For n = 4 + * 0b0..The Dual Edge Capture mode in this pair of channels is disabled. + * 0b1..The Dual Edge Capture mode in this pair of channels is enabled. + */ #define FTM_COMBINE_DECAPEN2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAPEN2_SHIFT)) & FTM_COMBINE_DECAPEN2_MASK) #define FTM_COMBINE_DECAP2_MASK (0x80000U) #define FTM_COMBINE_DECAP2_SHIFT (19U) +/*! DECAP2 - Dual Edge Capture Mode Captures For n = 4 + * 0b0..The dual edge captures are inactive. + * 0b1..The dual edge captures are active. + */ #define FTM_COMBINE_DECAP2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAP2_SHIFT)) & FTM_COMBINE_DECAP2_MASK) #define FTM_COMBINE_DTEN2_MASK (0x100000U) #define FTM_COMBINE_DTEN2_SHIFT (20U) +/*! DTEN2 - Deadtime Enable For n = 4 + * 0b0..The deadtime insertion in this pair of channels is disabled. + * 0b1..The deadtime insertion in this pair of channels is enabled. + */ #define FTM_COMBINE_DTEN2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DTEN2_SHIFT)) & FTM_COMBINE_DTEN2_MASK) #define FTM_COMBINE_SYNCEN2_MASK (0x200000U) #define FTM_COMBINE_SYNCEN2_SHIFT (21U) +/*! SYNCEN2 - Synchronization Enable For n = 4 + * 0b0..The PWM synchronization in this pair of channels is disabled. + * 0b1..The PWM synchronization in this pair of channels is enabled. + */ #define FTM_COMBINE_SYNCEN2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_SYNCEN2_SHIFT)) & FTM_COMBINE_SYNCEN2_MASK) #define FTM_COMBINE_FAULTEN2_MASK (0x400000U) #define FTM_COMBINE_FAULTEN2_SHIFT (22U) +/*! FAULTEN2 - Fault Control Enable For n = 4 + * 0b0..The fault control in this pair of channels is disabled. + * 0b1..The fault control in this pair of channels is enabled. + */ #define FTM_COMBINE_FAULTEN2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_FAULTEN2_SHIFT)) & FTM_COMBINE_FAULTEN2_MASK) #define FTM_COMBINE_COMBINE3_MASK (0x1000000U) #define FTM_COMBINE_COMBINE3_SHIFT (24U) +/*! COMBINE3 - Combine Channels For n = 6 + * 0b0..Channels (n) and (n+1) are independent. + * 0b1..Channels (n) and (n+1) are combined. + */ #define FTM_COMBINE_COMBINE3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMBINE3_SHIFT)) & FTM_COMBINE_COMBINE3_MASK) #define FTM_COMBINE_COMP3_MASK (0x2000000U) #define FTM_COMBINE_COMP3_SHIFT (25U) +/*! COMP3 - Complement Of Channel (n) for n = 6 + * 0b0..The channel (n+1) output is the same as the channel (n) output. + * 0b1..The channel (n+1) output is the complement of the channel (n) output. + */ #define FTM_COMBINE_COMP3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMP3_SHIFT)) & FTM_COMBINE_COMP3_MASK) #define FTM_COMBINE_DECAPEN3_MASK (0x4000000U) #define FTM_COMBINE_DECAPEN3_SHIFT (26U) +/*! DECAPEN3 - Dual Edge Capture Mode Enable For n = 6 + * 0b0..The Dual Edge Capture mode in this pair of channels is disabled. + * 0b1..The Dual Edge Capture mode in this pair of channels is enabled. + */ #define FTM_COMBINE_DECAPEN3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAPEN3_SHIFT)) & FTM_COMBINE_DECAPEN3_MASK) #define FTM_COMBINE_DECAP3_MASK (0x8000000U) #define FTM_COMBINE_DECAP3_SHIFT (27U) +/*! DECAP3 - Dual Edge Capture Mode Captures For n = 6 + * 0b0..The dual edge captures are inactive. + * 0b1..The dual edge captures are active. + */ #define FTM_COMBINE_DECAP3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAP3_SHIFT)) & FTM_COMBINE_DECAP3_MASK) #define FTM_COMBINE_DTEN3_MASK (0x10000000U) #define FTM_COMBINE_DTEN3_SHIFT (28U) +/*! DTEN3 - Deadtime Enable For n = 6 + * 0b0..The deadtime insertion in this pair of channels is disabled. + * 0b1..The deadtime insertion in this pair of channels is enabled. + */ #define FTM_COMBINE_DTEN3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DTEN3_SHIFT)) & FTM_COMBINE_DTEN3_MASK) #define FTM_COMBINE_SYNCEN3_MASK (0x20000000U) #define FTM_COMBINE_SYNCEN3_SHIFT (29U) +/*! SYNCEN3 - Synchronization Enable For n = 6 + * 0b0..The PWM synchronization in this pair of channels is disabled. + * 0b1..The PWM synchronization in this pair of channels is enabled. + */ #define FTM_COMBINE_SYNCEN3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_SYNCEN3_SHIFT)) & FTM_COMBINE_SYNCEN3_MASK) #define FTM_COMBINE_FAULTEN3_MASK (0x40000000U) #define FTM_COMBINE_FAULTEN3_SHIFT (30U) +/*! FAULTEN3 - Fault Control Enable For n = 6 + * 0b0..The fault control in this pair of channels is disabled. + * 0b1..The fault control in this pair of channels is enabled. + */ #define FTM_COMBINE_FAULTEN3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_FAULTEN3_SHIFT)) & FTM_COMBINE_FAULTEN3_MASK) +/*! @} */ /*! @name DEADTIME - Deadtime Insertion Control */ +/*! @{ */ #define FTM_DEADTIME_DTVAL_MASK (0x3FU) #define FTM_DEADTIME_DTVAL_SHIFT (0U) #define FTM_DEADTIME_DTVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_DEADTIME_DTVAL_SHIFT)) & FTM_DEADTIME_DTVAL_MASK) #define FTM_DEADTIME_DTPS_MASK (0xC0U) #define FTM_DEADTIME_DTPS_SHIFT (6U) +/*! DTPS - Deadtime Prescaler Value + * 0b0x..Divide the system clock by 1. + * 0b10..Divide the system clock by 4. + * 0b11..Divide the system clock by 16. + */ #define FTM_DEADTIME_DTPS(x) (((uint32_t)(((uint32_t)(x)) << FTM_DEADTIME_DTPS_SHIFT)) & FTM_DEADTIME_DTPS_MASK) +/*! @} */ /*! @name EXTTRIG - FTM External Trigger */ +/*! @{ */ #define FTM_EXTTRIG_CH2TRIG_MASK (0x1U) #define FTM_EXTTRIG_CH2TRIG_SHIFT (0U) +/*! CH2TRIG - Channel 2 Trigger Enable + * 0b0..The generation of the channel trigger is disabled. + * 0b1..The generation of the channel trigger is enabled. + */ #define FTM_EXTTRIG_CH2TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH2TRIG_SHIFT)) & FTM_EXTTRIG_CH2TRIG_MASK) #define FTM_EXTTRIG_CH3TRIG_MASK (0x2U) #define FTM_EXTTRIG_CH3TRIG_SHIFT (1U) +/*! CH3TRIG - Channel 3 Trigger Enable + * 0b0..The generation of the channel trigger is disabled. + * 0b1..The generation of the channel trigger is enabled. + */ #define FTM_EXTTRIG_CH3TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH3TRIG_SHIFT)) & FTM_EXTTRIG_CH3TRIG_MASK) #define FTM_EXTTRIG_CH4TRIG_MASK (0x4U) #define FTM_EXTTRIG_CH4TRIG_SHIFT (2U) +/*! CH4TRIG - Channel 4 Trigger Enable + * 0b0..The generation of the channel trigger is disabled. + * 0b1..The generation of the channel trigger is enabled. + */ #define FTM_EXTTRIG_CH4TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH4TRIG_SHIFT)) & FTM_EXTTRIG_CH4TRIG_MASK) #define FTM_EXTTRIG_CH5TRIG_MASK (0x8U) #define FTM_EXTTRIG_CH5TRIG_SHIFT (3U) +/*! CH5TRIG - Channel 5 Trigger Enable + * 0b0..The generation of the channel trigger is disabled. + * 0b1..The generation of the channel trigger is enabled. + */ #define FTM_EXTTRIG_CH5TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH5TRIG_SHIFT)) & FTM_EXTTRIG_CH5TRIG_MASK) #define FTM_EXTTRIG_CH0TRIG_MASK (0x10U) #define FTM_EXTTRIG_CH0TRIG_SHIFT (4U) +/*! CH0TRIG - Channel 0 Trigger Enable + * 0b0..The generation of the channel trigger is disabled. + * 0b1..The generation of the channel trigger is enabled. + */ #define FTM_EXTTRIG_CH0TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH0TRIG_SHIFT)) & FTM_EXTTRIG_CH0TRIG_MASK) #define FTM_EXTTRIG_CH1TRIG_MASK (0x20U) #define FTM_EXTTRIG_CH1TRIG_SHIFT (5U) +/*! CH1TRIG - Channel 1 Trigger Enable + * 0b0..The generation of the channel trigger is disabled. + * 0b1..The generation of the channel trigger is enabled. + */ #define FTM_EXTTRIG_CH1TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH1TRIG_SHIFT)) & FTM_EXTTRIG_CH1TRIG_MASK) #define FTM_EXTTRIG_INITTRIGEN_MASK (0x40U) #define FTM_EXTTRIG_INITTRIGEN_SHIFT (6U) +/*! INITTRIGEN - Initialization Trigger Enable + * 0b0..The generation of initialization trigger is disabled. + * 0b1..The generation of initialization trigger is enabled. + */ #define FTM_EXTTRIG_INITTRIGEN(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_INITTRIGEN_SHIFT)) & FTM_EXTTRIG_INITTRIGEN_MASK) #define FTM_EXTTRIG_TRIGF_MASK (0x80U) #define FTM_EXTTRIG_TRIGF_SHIFT (7U) +/*! TRIGF - Channel Trigger Flag + * 0b0..No channel trigger was generated. + * 0b1..A channel trigger was generated. + */ #define FTM_EXTTRIG_TRIGF(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_TRIGF_SHIFT)) & FTM_EXTTRIG_TRIGF_MASK) +/*! @} */ /*! @name POL - Channels Polarity */ +/*! @{ */ #define FTM_POL_POL0_MASK (0x1U) #define FTM_POL_POL0_SHIFT (0U) +/*! POL0 - Channel 0 Polarity + * 0b0..The channel polarity is active high. + * 0b1..The channel polarity is active low. + */ #define FTM_POL_POL0(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL0_SHIFT)) & FTM_POL_POL0_MASK) #define FTM_POL_POL1_MASK (0x2U) #define FTM_POL_POL1_SHIFT (1U) +/*! POL1 - Channel 1 Polarity + * 0b0..The channel polarity is active high. + * 0b1..The channel polarity is active low. + */ #define FTM_POL_POL1(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL1_SHIFT)) & FTM_POL_POL1_MASK) #define FTM_POL_POL2_MASK (0x4U) #define FTM_POL_POL2_SHIFT (2U) +/*! POL2 - Channel 2 Polarity + * 0b0..The channel polarity is active high. + * 0b1..The channel polarity is active low. + */ #define FTM_POL_POL2(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL2_SHIFT)) & FTM_POL_POL2_MASK) #define FTM_POL_POL3_MASK (0x8U) #define FTM_POL_POL3_SHIFT (3U) +/*! POL3 - Channel 3 Polarity + * 0b0..The channel polarity is active high. + * 0b1..The channel polarity is active low. + */ #define FTM_POL_POL3(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL3_SHIFT)) & FTM_POL_POL3_MASK) #define FTM_POL_POL4_MASK (0x10U) #define FTM_POL_POL4_SHIFT (4U) +/*! POL4 - Channel 4 Polarity + * 0b0..The channel polarity is active high. + * 0b1..The channel polarity is active low. + */ #define FTM_POL_POL4(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL4_SHIFT)) & FTM_POL_POL4_MASK) #define FTM_POL_POL5_MASK (0x20U) #define FTM_POL_POL5_SHIFT (5U) +/*! POL5 - Channel 5 Polarity + * 0b0..The channel polarity is active high. + * 0b1..The channel polarity is active low. + */ #define FTM_POL_POL5(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL5_SHIFT)) & FTM_POL_POL5_MASK) #define FTM_POL_POL6_MASK (0x40U) #define FTM_POL_POL6_SHIFT (6U) +/*! POL6 - Channel 6 Polarity + * 0b0..The channel polarity is active high. + * 0b1..The channel polarity is active low. + */ #define FTM_POL_POL6(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL6_SHIFT)) & FTM_POL_POL6_MASK) #define FTM_POL_POL7_MASK (0x80U) #define FTM_POL_POL7_SHIFT (7U) +/*! POL7 - Channel 7 Polarity + * 0b0..The channel polarity is active high. + * 0b1..The channel polarity is active low. + */ #define FTM_POL_POL7(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL7_SHIFT)) & FTM_POL_POL7_MASK) +/*! @} */ /*! @name FMS - Fault Mode Status */ +/*! @{ */ #define FTM_FMS_FAULTF0_MASK (0x1U) #define FTM_FMS_FAULTF0_SHIFT (0U) +/*! FAULTF0 - Fault Detection Flag 0 + * 0b0..No fault condition was detected at the fault input. + * 0b1..A fault condition was detected at the fault input. + */ #define FTM_FMS_FAULTF0(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF0_SHIFT)) & FTM_FMS_FAULTF0_MASK) #define FTM_FMS_FAULTF1_MASK (0x2U) #define FTM_FMS_FAULTF1_SHIFT (1U) +/*! FAULTF1 - Fault Detection Flag 1 + * 0b0..No fault condition was detected at the fault input. + * 0b1..A fault condition was detected at the fault input. + */ #define FTM_FMS_FAULTF1(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF1_SHIFT)) & FTM_FMS_FAULTF1_MASK) #define FTM_FMS_FAULTF2_MASK (0x4U) #define FTM_FMS_FAULTF2_SHIFT (2U) +/*! FAULTF2 - Fault Detection Flag 2 + * 0b0..No fault condition was detected at the fault input. + * 0b1..A fault condition was detected at the fault input. + */ #define FTM_FMS_FAULTF2(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF2_SHIFT)) & FTM_FMS_FAULTF2_MASK) #define FTM_FMS_FAULTF3_MASK (0x8U) #define FTM_FMS_FAULTF3_SHIFT (3U) +/*! FAULTF3 - Fault Detection Flag 3 + * 0b0..No fault condition was detected at the fault input. + * 0b1..A fault condition was detected at the fault input. + */ #define FTM_FMS_FAULTF3(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF3_SHIFT)) & FTM_FMS_FAULTF3_MASK) #define FTM_FMS_FAULTIN_MASK (0x20U) #define FTM_FMS_FAULTIN_SHIFT (5U) +/*! FAULTIN - Fault Inputs + * 0b0..The logic OR of the enabled fault inputs is 0. + * 0b1..The logic OR of the enabled fault inputs is 1. + */ #define FTM_FMS_FAULTIN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTIN_SHIFT)) & FTM_FMS_FAULTIN_MASK) #define FTM_FMS_WPEN_MASK (0x40U) #define FTM_FMS_WPEN_SHIFT (6U) +/*! WPEN - Write Protection Enable + * 0b0..Write protection is disabled. Write protected bits can be written. + * 0b1..Write protection is enabled. Write protected bits cannot be written. + */ #define FTM_FMS_WPEN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_WPEN_SHIFT)) & FTM_FMS_WPEN_MASK) #define FTM_FMS_FAULTF_MASK (0x80U) #define FTM_FMS_FAULTF_SHIFT (7U) +/*! FAULTF - Fault Detection Flag + * 0b0..No fault condition was detected. + * 0b1..A fault condition was detected. + */ #define FTM_FMS_FAULTF(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF_SHIFT)) & FTM_FMS_FAULTF_MASK) +/*! @} */ /*! @name FILTER - Input Capture Filter Control */ +/*! @{ */ #define FTM_FILTER_CH0FVAL_MASK (0xFU) #define FTM_FILTER_CH0FVAL_SHIFT (0U) #define FTM_FILTER_CH0FVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FILTER_CH0FVAL_SHIFT)) & FTM_FILTER_CH0FVAL_MASK) @@ -6609,63 +11511,133 @@ typedef struct { #define FTM_FILTER_CH3FVAL_MASK (0xF000U) #define FTM_FILTER_CH3FVAL_SHIFT (12U) #define FTM_FILTER_CH3FVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FILTER_CH3FVAL_SHIFT)) & FTM_FILTER_CH3FVAL_MASK) +/*! @} */ /*! @name FLTCTRL - Fault Control */ +/*! @{ */ #define FTM_FLTCTRL_FAULT0EN_MASK (0x1U) #define FTM_FLTCTRL_FAULT0EN_SHIFT (0U) +/*! FAULT0EN - Fault Input 0 Enable + * 0b0..Fault input is disabled. + * 0b1..Fault input is enabled. + */ #define FTM_FLTCTRL_FAULT0EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FAULT0EN_SHIFT)) & FTM_FLTCTRL_FAULT0EN_MASK) #define FTM_FLTCTRL_FAULT1EN_MASK (0x2U) #define FTM_FLTCTRL_FAULT1EN_SHIFT (1U) +/*! FAULT1EN - Fault Input 1 Enable + * 0b0..Fault input is disabled. + * 0b1..Fault input is enabled. + */ #define FTM_FLTCTRL_FAULT1EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FAULT1EN_SHIFT)) & FTM_FLTCTRL_FAULT1EN_MASK) #define FTM_FLTCTRL_FAULT2EN_MASK (0x4U) #define FTM_FLTCTRL_FAULT2EN_SHIFT (2U) +/*! FAULT2EN - Fault Input 2 Enable + * 0b0..Fault input is disabled. + * 0b1..Fault input is enabled. + */ #define FTM_FLTCTRL_FAULT2EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FAULT2EN_SHIFT)) & FTM_FLTCTRL_FAULT2EN_MASK) #define FTM_FLTCTRL_FAULT3EN_MASK (0x8U) #define FTM_FLTCTRL_FAULT3EN_SHIFT (3U) +/*! FAULT3EN - Fault Input 3 Enable + * 0b0..Fault input is disabled. + * 0b1..Fault input is enabled. + */ #define FTM_FLTCTRL_FAULT3EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FAULT3EN_SHIFT)) & FTM_FLTCTRL_FAULT3EN_MASK) #define FTM_FLTCTRL_FFLTR0EN_MASK (0x10U) #define FTM_FLTCTRL_FFLTR0EN_SHIFT (4U) +/*! FFLTR0EN - Fault Input 0 Filter Enable + * 0b0..Fault input filter is disabled. + * 0b1..Fault input filter is enabled. + */ #define FTM_FLTCTRL_FFLTR0EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFLTR0EN_SHIFT)) & FTM_FLTCTRL_FFLTR0EN_MASK) #define FTM_FLTCTRL_FFLTR1EN_MASK (0x20U) #define FTM_FLTCTRL_FFLTR1EN_SHIFT (5U) +/*! FFLTR1EN - Fault Input 1 Filter Enable + * 0b0..Fault input filter is disabled. + * 0b1..Fault input filter is enabled. + */ #define FTM_FLTCTRL_FFLTR1EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFLTR1EN_SHIFT)) & FTM_FLTCTRL_FFLTR1EN_MASK) #define FTM_FLTCTRL_FFLTR2EN_MASK (0x40U) #define FTM_FLTCTRL_FFLTR2EN_SHIFT (6U) +/*! FFLTR2EN - Fault Input 2 Filter Enable + * 0b0..Fault input filter is disabled. + * 0b1..Fault input filter is enabled. + */ #define FTM_FLTCTRL_FFLTR2EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFLTR2EN_SHIFT)) & FTM_FLTCTRL_FFLTR2EN_MASK) #define FTM_FLTCTRL_FFLTR3EN_MASK (0x80U) #define FTM_FLTCTRL_FFLTR3EN_SHIFT (7U) +/*! FFLTR3EN - Fault Input 3 Filter Enable + * 0b0..Fault input filter is disabled. + * 0b1..Fault input filter is enabled. + */ #define FTM_FLTCTRL_FFLTR3EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFLTR3EN_SHIFT)) & FTM_FLTCTRL_FFLTR3EN_MASK) #define FTM_FLTCTRL_FFVAL_MASK (0xF00U) #define FTM_FLTCTRL_FFVAL_SHIFT (8U) #define FTM_FLTCTRL_FFVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFVAL_SHIFT)) & FTM_FLTCTRL_FFVAL_MASK) +/*! @} */ /*! @name QDCTRL - Quadrature Decoder Control And Status */ +/*! @{ */ #define FTM_QDCTRL_QUADEN_MASK (0x1U) #define FTM_QDCTRL_QUADEN_SHIFT (0U) +/*! QUADEN - Quadrature Decoder Mode Enable + * 0b0..Quadrature Decoder mode is disabled. + * 0b1..Quadrature Decoder mode is enabled. + */ #define FTM_QDCTRL_QUADEN(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_QUADEN_SHIFT)) & FTM_QDCTRL_QUADEN_MASK) #define FTM_QDCTRL_TOFDIR_MASK (0x2U) #define FTM_QDCTRL_TOFDIR_SHIFT (1U) +/*! TOFDIR - Timer Overflow Direction In Quadrature Decoder Mode + * 0b0..TOF bit was set on the bottom of counting. There was an FTM counter decrement and FTM counter changes from its minimum value (CNTIN register) to its maximum value (MOD register). + * 0b1..TOF bit was set on the top of counting. There was an FTM counter increment and FTM counter changes from its maximum value (MOD register) to its minimum value (CNTIN register). + */ #define FTM_QDCTRL_TOFDIR(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_TOFDIR_SHIFT)) & FTM_QDCTRL_TOFDIR_MASK) #define FTM_QDCTRL_QUADIR_MASK (0x4U) #define FTM_QDCTRL_QUADIR_SHIFT (2U) +/*! QUADIR - FTM Counter Direction In Quadrature Decoder Mode + * 0b0..Counting direction is decreasing (FTM counter decrement). + * 0b1..Counting direction is increasing (FTM counter increment). + */ #define FTM_QDCTRL_QUADIR(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_QUADIR_SHIFT)) & FTM_QDCTRL_QUADIR_MASK) #define FTM_QDCTRL_QUADMODE_MASK (0x8U) #define FTM_QDCTRL_QUADMODE_SHIFT (3U) +/*! QUADMODE - Quadrature Decoder Mode + * 0b0..Phase A and phase B encoding mode. + * 0b1..Count and direction encoding mode. + */ #define FTM_QDCTRL_QUADMODE(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_QUADMODE_SHIFT)) & FTM_QDCTRL_QUADMODE_MASK) #define FTM_QDCTRL_PHBPOL_MASK (0x10U) #define FTM_QDCTRL_PHBPOL_SHIFT (4U) +/*! PHBPOL - Phase B Input Polarity + * 0b0..Normal polarity. Phase B input signal is not inverted before identifying the rising and falling edges of this signal. + * 0b1..Inverted polarity. Phase B input signal is inverted before identifying the rising and falling edges of this signal. + */ #define FTM_QDCTRL_PHBPOL(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHBPOL_SHIFT)) & FTM_QDCTRL_PHBPOL_MASK) #define FTM_QDCTRL_PHAPOL_MASK (0x20U) #define FTM_QDCTRL_PHAPOL_SHIFT (5U) +/*! PHAPOL - Phase A Input Polarity + * 0b0..Normal polarity. Phase A input signal is not inverted before identifying the rising and falling edges of this signal. + * 0b1..Inverted polarity. Phase A input signal is inverted before identifying the rising and falling edges of this signal. + */ #define FTM_QDCTRL_PHAPOL(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHAPOL_SHIFT)) & FTM_QDCTRL_PHAPOL_MASK) #define FTM_QDCTRL_PHBFLTREN_MASK (0x40U) #define FTM_QDCTRL_PHBFLTREN_SHIFT (6U) +/*! PHBFLTREN - Phase B Input Filter Enable + * 0b0..Phase B input filter is disabled. + * 0b1..Phase B input filter is enabled. + */ #define FTM_QDCTRL_PHBFLTREN(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHBFLTREN_SHIFT)) & FTM_QDCTRL_PHBFLTREN_MASK) #define FTM_QDCTRL_PHAFLTREN_MASK (0x80U) #define FTM_QDCTRL_PHAFLTREN_SHIFT (7U) +/*! PHAFLTREN - Phase A Input Filter Enable + * 0b0..Phase A input filter is disabled. + * 0b1..Phase A input filter is enabled. + */ #define FTM_QDCTRL_PHAFLTREN(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHAFLTREN_SHIFT)) & FTM_QDCTRL_PHAFLTREN_MASK) +/*! @} */ /*! @name CONF - Configuration */ +/*! @{ */ #define FTM_CONF_NUMTOF_MASK (0x1FU) #define FTM_CONF_NUMTOF_SHIFT (0U) #define FTM_CONF_NUMTOF(x) (((uint32_t)(((uint32_t)(x)) << FTM_CONF_NUMTOF_SHIFT)) & FTM_CONF_NUMTOF_MASK) @@ -6674,164 +11646,375 @@ typedef struct { #define FTM_CONF_BDMMODE(x) (((uint32_t)(((uint32_t)(x)) << FTM_CONF_BDMMODE_SHIFT)) & FTM_CONF_BDMMODE_MASK) #define FTM_CONF_GTBEEN_MASK (0x200U) #define FTM_CONF_GTBEEN_SHIFT (9U) +/*! GTBEEN - Global Time Base Enable + * 0b0..Use of an external global time base is disabled. + * 0b1..Use of an external global time base is enabled. + */ #define FTM_CONF_GTBEEN(x) (((uint32_t)(((uint32_t)(x)) << FTM_CONF_GTBEEN_SHIFT)) & FTM_CONF_GTBEEN_MASK) #define FTM_CONF_GTBEOUT_MASK (0x400U) #define FTM_CONF_GTBEOUT_SHIFT (10U) +/*! GTBEOUT - Global Time Base Output + * 0b0..A global time base signal generation is disabled. + * 0b1..A global time base signal generation is enabled. + */ #define FTM_CONF_GTBEOUT(x) (((uint32_t)(((uint32_t)(x)) << FTM_CONF_GTBEOUT_SHIFT)) & FTM_CONF_GTBEOUT_MASK) +/*! @} */ /*! @name FLTPOL - FTM Fault Input Polarity */ +/*! @{ */ #define FTM_FLTPOL_FLT0POL_MASK (0x1U) #define FTM_FLTPOL_FLT0POL_SHIFT (0U) +/*! FLT0POL - Fault Input 0 Polarity + * 0b0..The fault input polarity is active high. A 1 at the fault input indicates a fault. + * 0b1..The fault input polarity is active low. A 0 at the fault input indicates a fault. + */ #define FTM_FLTPOL_FLT0POL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTPOL_FLT0POL_SHIFT)) & FTM_FLTPOL_FLT0POL_MASK) #define FTM_FLTPOL_FLT1POL_MASK (0x2U) #define FTM_FLTPOL_FLT1POL_SHIFT (1U) +/*! FLT1POL - Fault Input 1 Polarity + * 0b0..The fault input polarity is active high. A 1 at the fault input indicates a fault. + * 0b1..The fault input polarity is active low. A 0 at the fault input indicates a fault. + */ #define FTM_FLTPOL_FLT1POL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTPOL_FLT1POL_SHIFT)) & FTM_FLTPOL_FLT1POL_MASK) #define FTM_FLTPOL_FLT2POL_MASK (0x4U) #define FTM_FLTPOL_FLT2POL_SHIFT (2U) +/*! FLT2POL - Fault Input 2 Polarity + * 0b0..The fault input polarity is active high. A 1 at the fault input indicates a fault. + * 0b1..The fault input polarity is active low. A 0 at the fault input indicates a fault. + */ #define FTM_FLTPOL_FLT2POL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTPOL_FLT2POL_SHIFT)) & FTM_FLTPOL_FLT2POL_MASK) #define FTM_FLTPOL_FLT3POL_MASK (0x8U) #define FTM_FLTPOL_FLT3POL_SHIFT (3U) +/*! FLT3POL - Fault Input 3 Polarity + * 0b0..The fault input polarity is active high. A 1 at the fault input indicates a fault. + * 0b1..The fault input polarity is active low. A 0 at the fault input indicates a fault. + */ #define FTM_FLTPOL_FLT3POL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTPOL_FLT3POL_SHIFT)) & FTM_FLTPOL_FLT3POL_MASK) +/*! @} */ /*! @name SYNCONF - Synchronization Configuration */ +/*! @{ */ #define FTM_SYNCONF_HWTRIGMODE_MASK (0x1U) #define FTM_SYNCONF_HWTRIGMODE_SHIFT (0U) +/*! HWTRIGMODE - Hardware Trigger Mode + * 0b0..FTM clears the TRIGj bit when the hardware trigger j is detected, where j = 0, 1,2. + * 0b1..FTM does not clear the TRIGj bit when the hardware trigger j is detected, where j = 0, 1,2. + */ #define FTM_SYNCONF_HWTRIGMODE(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWTRIGMODE_SHIFT)) & FTM_SYNCONF_HWTRIGMODE_MASK) #define FTM_SYNCONF_CNTINC_MASK (0x4U) #define FTM_SYNCONF_CNTINC_SHIFT (2U) +/*! CNTINC - CNTIN Register Synchronization + * 0b0..CNTIN register is updated with its buffer value at all rising edges of system clock. + * 0b1..CNTIN register is updated with its buffer value by the PWM synchronization. + */ #define FTM_SYNCONF_CNTINC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_CNTINC_SHIFT)) & FTM_SYNCONF_CNTINC_MASK) #define FTM_SYNCONF_INVC_MASK (0x10U) #define FTM_SYNCONF_INVC_SHIFT (4U) +/*! INVC - INVCTRL Register Synchronization + * 0b0..INVCTRL register is updated with its buffer value at all rising edges of system clock. + * 0b1..INVCTRL register is updated with its buffer value by the PWM synchronization. + */ #define FTM_SYNCONF_INVC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_INVC_SHIFT)) & FTM_SYNCONF_INVC_MASK) #define FTM_SYNCONF_SWOC_MASK (0x20U) #define FTM_SYNCONF_SWOC_SHIFT (5U) +/*! SWOC - SWOCTRL Register Synchronization + * 0b0..SWOCTRL register is updated with its buffer value at all rising edges of system clock. + * 0b1..SWOCTRL register is updated with its buffer value by the PWM synchronization. + */ #define FTM_SYNCONF_SWOC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWOC_SHIFT)) & FTM_SYNCONF_SWOC_MASK) #define FTM_SYNCONF_SYNCMODE_MASK (0x80U) #define FTM_SYNCONF_SYNCMODE_SHIFT (7U) +/*! SYNCMODE - Synchronization Mode + * 0b0..Legacy PWM synchronization is selected. + * 0b1..Enhanced PWM synchronization is selected. + */ #define FTM_SYNCONF_SYNCMODE(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SYNCMODE_SHIFT)) & FTM_SYNCONF_SYNCMODE_MASK) #define FTM_SYNCONF_SWRSTCNT_MASK (0x100U) #define FTM_SYNCONF_SWRSTCNT_SHIFT (8U) +/*! SWRSTCNT + * 0b0..The software trigger does not activate the FTM counter synchronization. + * 0b1..The software trigger activates the FTM counter synchronization. + */ #define FTM_SYNCONF_SWRSTCNT(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWRSTCNT_SHIFT)) & FTM_SYNCONF_SWRSTCNT_MASK) #define FTM_SYNCONF_SWWRBUF_MASK (0x200U) #define FTM_SYNCONF_SWWRBUF_SHIFT (9U) +/*! SWWRBUF + * 0b0..The software trigger does not activate MOD, CNTIN, and CV registers synchronization. + * 0b1..The software trigger activates MOD, CNTIN, and CV registers synchronization. + */ #define FTM_SYNCONF_SWWRBUF(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWWRBUF_SHIFT)) & FTM_SYNCONF_SWWRBUF_MASK) #define FTM_SYNCONF_SWOM_MASK (0x400U) #define FTM_SYNCONF_SWOM_SHIFT (10U) +/*! SWOM + * 0b0..The software trigger does not activate the OUTMASK register synchronization. + * 0b1..The software trigger activates the OUTMASK register synchronization. + */ #define FTM_SYNCONF_SWOM(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWOM_SHIFT)) & FTM_SYNCONF_SWOM_MASK) #define FTM_SYNCONF_SWINVC_MASK (0x800U) #define FTM_SYNCONF_SWINVC_SHIFT (11U) +/*! SWINVC + * 0b0..The software trigger does not activate the INVCTRL register synchronization. + * 0b1..The software trigger activates the INVCTRL register synchronization. + */ #define FTM_SYNCONF_SWINVC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWINVC_SHIFT)) & FTM_SYNCONF_SWINVC_MASK) #define FTM_SYNCONF_SWSOC_MASK (0x1000U) #define FTM_SYNCONF_SWSOC_SHIFT (12U) +/*! SWSOC + * 0b0..The software trigger does not activate the SWOCTRL register synchronization. + * 0b1..The software trigger activates the SWOCTRL register synchronization. + */ #define FTM_SYNCONF_SWSOC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWSOC_SHIFT)) & FTM_SYNCONF_SWSOC_MASK) #define FTM_SYNCONF_HWRSTCNT_MASK (0x10000U) #define FTM_SYNCONF_HWRSTCNT_SHIFT (16U) +/*! HWRSTCNT + * 0b0..A hardware trigger does not activate the FTM counter synchronization. + * 0b1..A hardware trigger activates the FTM counter synchronization. + */ #define FTM_SYNCONF_HWRSTCNT(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWRSTCNT_SHIFT)) & FTM_SYNCONF_HWRSTCNT_MASK) #define FTM_SYNCONF_HWWRBUF_MASK (0x20000U) #define FTM_SYNCONF_HWWRBUF_SHIFT (17U) +/*! HWWRBUF + * 0b0..A hardware trigger does not activate MOD, CNTIN, and CV registers synchronization. + * 0b1..A hardware trigger activates MOD, CNTIN, and CV registers synchronization. + */ #define FTM_SYNCONF_HWWRBUF(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWWRBUF_SHIFT)) & FTM_SYNCONF_HWWRBUF_MASK) #define FTM_SYNCONF_HWOM_MASK (0x40000U) #define FTM_SYNCONF_HWOM_SHIFT (18U) +/*! HWOM + * 0b0..A hardware trigger does not activate the OUTMASK register synchronization. + * 0b1..A hardware trigger activates the OUTMASK register synchronization. + */ #define FTM_SYNCONF_HWOM(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWOM_SHIFT)) & FTM_SYNCONF_HWOM_MASK) #define FTM_SYNCONF_HWINVC_MASK (0x80000U) #define FTM_SYNCONF_HWINVC_SHIFT (19U) +/*! HWINVC + * 0b0..A hardware trigger does not activate the INVCTRL register synchronization. + * 0b1..A hardware trigger activates the INVCTRL register synchronization. + */ #define FTM_SYNCONF_HWINVC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWINVC_SHIFT)) & FTM_SYNCONF_HWINVC_MASK) #define FTM_SYNCONF_HWSOC_MASK (0x100000U) #define FTM_SYNCONF_HWSOC_SHIFT (20U) +/*! HWSOC + * 0b0..A hardware trigger does not activate the SWOCTRL register synchronization. + * 0b1..A hardware trigger activates the SWOCTRL register synchronization. + */ #define FTM_SYNCONF_HWSOC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWSOC_SHIFT)) & FTM_SYNCONF_HWSOC_MASK) +/*! @} */ /*! @name INVCTRL - FTM Inverting Control */ +/*! @{ */ #define FTM_INVCTRL_INV0EN_MASK (0x1U) #define FTM_INVCTRL_INV0EN_SHIFT (0U) +/*! INV0EN - Pair Channels 0 Inverting Enable + * 0b0..Inverting is disabled. + * 0b1..Inverting is enabled. + */ #define FTM_INVCTRL_INV0EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_INVCTRL_INV0EN_SHIFT)) & FTM_INVCTRL_INV0EN_MASK) #define FTM_INVCTRL_INV1EN_MASK (0x2U) #define FTM_INVCTRL_INV1EN_SHIFT (1U) +/*! INV1EN - Pair Channels 1 Inverting Enable + * 0b0..Inverting is disabled. + * 0b1..Inverting is enabled. + */ #define FTM_INVCTRL_INV1EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_INVCTRL_INV1EN_SHIFT)) & FTM_INVCTRL_INV1EN_MASK) #define FTM_INVCTRL_INV2EN_MASK (0x4U) #define FTM_INVCTRL_INV2EN_SHIFT (2U) +/*! INV2EN - Pair Channels 2 Inverting Enable + * 0b0..Inverting is disabled. + * 0b1..Inverting is enabled. + */ #define FTM_INVCTRL_INV2EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_INVCTRL_INV2EN_SHIFT)) & FTM_INVCTRL_INV2EN_MASK) #define FTM_INVCTRL_INV3EN_MASK (0x8U) #define FTM_INVCTRL_INV3EN_SHIFT (3U) +/*! INV3EN - Pair Channels 3 Inverting Enable + * 0b0..Inverting is disabled. + * 0b1..Inverting is enabled. + */ #define FTM_INVCTRL_INV3EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_INVCTRL_INV3EN_SHIFT)) & FTM_INVCTRL_INV3EN_MASK) +/*! @} */ /*! @name SWOCTRL - FTM Software Output Control */ +/*! @{ */ #define FTM_SWOCTRL_CH0OC_MASK (0x1U) #define FTM_SWOCTRL_CH0OC_SHIFT (0U) +/*! CH0OC - Channel 0 Software Output Control Enable + * 0b0..The channel output is not affected by software output control. + * 0b1..The channel output is affected by software output control. + */ #define FTM_SWOCTRL_CH0OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH0OC_SHIFT)) & FTM_SWOCTRL_CH0OC_MASK) #define FTM_SWOCTRL_CH1OC_MASK (0x2U) #define FTM_SWOCTRL_CH1OC_SHIFT (1U) +/*! CH1OC - Channel 1 Software Output Control Enable + * 0b0..The channel output is not affected by software output control. + * 0b1..The channel output is affected by software output control. + */ #define FTM_SWOCTRL_CH1OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH1OC_SHIFT)) & FTM_SWOCTRL_CH1OC_MASK) #define FTM_SWOCTRL_CH2OC_MASK (0x4U) #define FTM_SWOCTRL_CH2OC_SHIFT (2U) +/*! CH2OC - Channel 2 Software Output Control Enable + * 0b0..The channel output is not affected by software output control. + * 0b1..The channel output is affected by software output control. + */ #define FTM_SWOCTRL_CH2OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH2OC_SHIFT)) & FTM_SWOCTRL_CH2OC_MASK) #define FTM_SWOCTRL_CH3OC_MASK (0x8U) #define FTM_SWOCTRL_CH3OC_SHIFT (3U) +/*! CH3OC - Channel 3 Software Output Control Enable + * 0b0..The channel output is not affected by software output control. + * 0b1..The channel output is affected by software output control. + */ #define FTM_SWOCTRL_CH3OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH3OC_SHIFT)) & FTM_SWOCTRL_CH3OC_MASK) #define FTM_SWOCTRL_CH4OC_MASK (0x10U) #define FTM_SWOCTRL_CH4OC_SHIFT (4U) +/*! CH4OC - Channel 4 Software Output Control Enable + * 0b0..The channel output is not affected by software output control. + * 0b1..The channel output is affected by software output control. + */ #define FTM_SWOCTRL_CH4OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH4OC_SHIFT)) & FTM_SWOCTRL_CH4OC_MASK) #define FTM_SWOCTRL_CH5OC_MASK (0x20U) #define FTM_SWOCTRL_CH5OC_SHIFT (5U) +/*! CH5OC - Channel 5 Software Output Control Enable + * 0b0..The channel output is not affected by software output control. + * 0b1..The channel output is affected by software output control. + */ #define FTM_SWOCTRL_CH5OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH5OC_SHIFT)) & FTM_SWOCTRL_CH5OC_MASK) #define FTM_SWOCTRL_CH6OC_MASK (0x40U) #define FTM_SWOCTRL_CH6OC_SHIFT (6U) +/*! CH6OC - Channel 6 Software Output Control Enable + * 0b0..The channel output is not affected by software output control. + * 0b1..The channel output is affected by software output control. + */ #define FTM_SWOCTRL_CH6OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH6OC_SHIFT)) & FTM_SWOCTRL_CH6OC_MASK) #define FTM_SWOCTRL_CH7OC_MASK (0x80U) #define FTM_SWOCTRL_CH7OC_SHIFT (7U) +/*! CH7OC - Channel 7 Software Output Control Enable + * 0b0..The channel output is not affected by software output control. + * 0b1..The channel output is affected by software output control. + */ #define FTM_SWOCTRL_CH7OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH7OC_SHIFT)) & FTM_SWOCTRL_CH7OC_MASK) #define FTM_SWOCTRL_CH0OCV_MASK (0x100U) #define FTM_SWOCTRL_CH0OCV_SHIFT (8U) +/*! CH0OCV - Channel 0 Software Output Control Value + * 0b0..The software output control forces 0 to the channel output. + * 0b1..The software output control forces 1 to the channel output. + */ #define FTM_SWOCTRL_CH0OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH0OCV_SHIFT)) & FTM_SWOCTRL_CH0OCV_MASK) #define FTM_SWOCTRL_CH1OCV_MASK (0x200U) #define FTM_SWOCTRL_CH1OCV_SHIFT (9U) +/*! CH1OCV - Channel 1 Software Output Control Value + * 0b0..The software output control forces 0 to the channel output. + * 0b1..The software output control forces 1 to the channel output. + */ #define FTM_SWOCTRL_CH1OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH1OCV_SHIFT)) & FTM_SWOCTRL_CH1OCV_MASK) #define FTM_SWOCTRL_CH2OCV_MASK (0x400U) #define FTM_SWOCTRL_CH2OCV_SHIFT (10U) +/*! CH2OCV - Channel 2 Software Output Control Value + * 0b0..The software output control forces 0 to the channel output. + * 0b1..The software output control forces 1 to the channel output. + */ #define FTM_SWOCTRL_CH2OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH2OCV_SHIFT)) & FTM_SWOCTRL_CH2OCV_MASK) #define FTM_SWOCTRL_CH3OCV_MASK (0x800U) #define FTM_SWOCTRL_CH3OCV_SHIFT (11U) +/*! CH3OCV - Channel 3 Software Output Control Value + * 0b0..The software output control forces 0 to the channel output. + * 0b1..The software output control forces 1 to the channel output. + */ #define FTM_SWOCTRL_CH3OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH3OCV_SHIFT)) & FTM_SWOCTRL_CH3OCV_MASK) #define FTM_SWOCTRL_CH4OCV_MASK (0x1000U) #define FTM_SWOCTRL_CH4OCV_SHIFT (12U) +/*! CH4OCV - Channel 4 Software Output Control Value + * 0b0..The software output control forces 0 to the channel output. + * 0b1..The software output control forces 1 to the channel output. + */ #define FTM_SWOCTRL_CH4OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH4OCV_SHIFT)) & FTM_SWOCTRL_CH4OCV_MASK) #define FTM_SWOCTRL_CH5OCV_MASK (0x2000U) #define FTM_SWOCTRL_CH5OCV_SHIFT (13U) +/*! CH5OCV - Channel 5 Software Output Control Value + * 0b0..The software output control forces 0 to the channel output. + * 0b1..The software output control forces 1 to the channel output. + */ #define FTM_SWOCTRL_CH5OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH5OCV_SHIFT)) & FTM_SWOCTRL_CH5OCV_MASK) #define FTM_SWOCTRL_CH6OCV_MASK (0x4000U) #define FTM_SWOCTRL_CH6OCV_SHIFT (14U) +/*! CH6OCV - Channel 6 Software Output Control Value + * 0b0..The software output control forces 0 to the channel output. + * 0b1..The software output control forces 1 to the channel output. + */ #define FTM_SWOCTRL_CH6OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH6OCV_SHIFT)) & FTM_SWOCTRL_CH6OCV_MASK) #define FTM_SWOCTRL_CH7OCV_MASK (0x8000U) #define FTM_SWOCTRL_CH7OCV_SHIFT (15U) +/*! CH7OCV - Channel 7 Software Output Control Value + * 0b0..The software output control forces 0 to the channel output. + * 0b1..The software output control forces 1 to the channel output. + */ #define FTM_SWOCTRL_CH7OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH7OCV_SHIFT)) & FTM_SWOCTRL_CH7OCV_MASK) +/*! @} */ /*! @name PWMLOAD - FTM PWM Load */ +/*! @{ */ #define FTM_PWMLOAD_CH0SEL_MASK (0x1U) #define FTM_PWMLOAD_CH0SEL_SHIFT (0U) +/*! CH0SEL - Channel 0 Select + * 0b0..Do not include the channel in the matching process. + * 0b1..Include the channel in the matching process. + */ #define FTM_PWMLOAD_CH0SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH0SEL_SHIFT)) & FTM_PWMLOAD_CH0SEL_MASK) #define FTM_PWMLOAD_CH1SEL_MASK (0x2U) #define FTM_PWMLOAD_CH1SEL_SHIFT (1U) +/*! CH1SEL - Channel 1 Select + * 0b0..Do not include the channel in the matching process. + * 0b1..Include the channel in the matching process. + */ #define FTM_PWMLOAD_CH1SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH1SEL_SHIFT)) & FTM_PWMLOAD_CH1SEL_MASK) #define FTM_PWMLOAD_CH2SEL_MASK (0x4U) #define FTM_PWMLOAD_CH2SEL_SHIFT (2U) +/*! CH2SEL - Channel 2 Select + * 0b0..Do not include the channel in the matching process. + * 0b1..Include the channel in the matching process. + */ #define FTM_PWMLOAD_CH2SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH2SEL_SHIFT)) & FTM_PWMLOAD_CH2SEL_MASK) #define FTM_PWMLOAD_CH3SEL_MASK (0x8U) #define FTM_PWMLOAD_CH3SEL_SHIFT (3U) +/*! CH3SEL - Channel 3 Select + * 0b0..Do not include the channel in the matching process. + * 0b1..Include the channel in the matching process. + */ #define FTM_PWMLOAD_CH3SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH3SEL_SHIFT)) & FTM_PWMLOAD_CH3SEL_MASK) #define FTM_PWMLOAD_CH4SEL_MASK (0x10U) #define FTM_PWMLOAD_CH4SEL_SHIFT (4U) +/*! CH4SEL - Channel 4 Select + * 0b0..Do not include the channel in the matching process. + * 0b1..Include the channel in the matching process. + */ #define FTM_PWMLOAD_CH4SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH4SEL_SHIFT)) & FTM_PWMLOAD_CH4SEL_MASK) #define FTM_PWMLOAD_CH5SEL_MASK (0x20U) #define FTM_PWMLOAD_CH5SEL_SHIFT (5U) +/*! CH5SEL - Channel 5 Select + * 0b0..Do not include the channel in the matching process. + * 0b1..Include the channel in the matching process. + */ #define FTM_PWMLOAD_CH5SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH5SEL_SHIFT)) & FTM_PWMLOAD_CH5SEL_MASK) #define FTM_PWMLOAD_CH6SEL_MASK (0x40U) #define FTM_PWMLOAD_CH6SEL_SHIFT (6U) +/*! CH6SEL - Channel 6 Select + * 0b0..Do not include the channel in the matching process. + * 0b1..Include the channel in the matching process. + */ #define FTM_PWMLOAD_CH6SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH6SEL_SHIFT)) & FTM_PWMLOAD_CH6SEL_MASK) #define FTM_PWMLOAD_CH7SEL_MASK (0x80U) #define FTM_PWMLOAD_CH7SEL_SHIFT (7U) +/*! CH7SEL - Channel 7 Select + * 0b0..Do not include the channel in the matching process. + * 0b1..Include the channel in the matching process. + */ #define FTM_PWMLOAD_CH7SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH7SEL_SHIFT)) & FTM_PWMLOAD_CH7SEL_MASK) #define FTM_PWMLOAD_LDOK_MASK (0x200U) #define FTM_PWMLOAD_LDOK_SHIFT (9U) +/*! LDOK - Load Enable + * 0b0..Loading updated values is disabled. + * 0b1..Loading updated values is enabled. + */ #define FTM_PWMLOAD_LDOK(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_LDOK_SHIFT)) & FTM_PWMLOAD_LDOK_MASK) +/*! @} */ /*! @@ -6897,34 +12080,70 @@ typedef struct { */ /*! @name PDOR - Port Data Output Register */ +/*! @{ */ #define GPIO_PDOR_PDO_MASK (0xFFFFFFFFU) #define GPIO_PDOR_PDO_SHIFT (0U) +/*! PDO - Port Data Output + * 0b00000000000000000000000000000000..Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + * 0b00000000000000000000000000000001..Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + */ #define GPIO_PDOR_PDO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO_SHIFT)) & GPIO_PDOR_PDO_MASK) +/*! @} */ /*! @name PSOR - Port Set Output Register */ +/*! @{ */ #define GPIO_PSOR_PTSO_MASK (0xFFFFFFFFU) #define GPIO_PSOR_PTSO_SHIFT (0U) +/*! PTSO - Port Set Output + * 0b00000000000000000000000000000000..Corresponding bit in PDORn does not change. + * 0b00000000000000000000000000000001..Corresponding bit in PDORn is set to logic 1. + */ #define GPIO_PSOR_PTSO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO_SHIFT)) & GPIO_PSOR_PTSO_MASK) +/*! @} */ /*! @name PCOR - Port Clear Output Register */ +/*! @{ */ #define GPIO_PCOR_PTCO_MASK (0xFFFFFFFFU) #define GPIO_PCOR_PTCO_SHIFT (0U) +/*! PTCO - Port Clear Output + * 0b00000000000000000000000000000000..Corresponding bit in PDORn does not change. + * 0b00000000000000000000000000000001..Corresponding bit in PDORn is cleared to logic 0. + */ #define GPIO_PCOR_PTCO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO_SHIFT)) & GPIO_PCOR_PTCO_MASK) +/*! @} */ /*! @name PTOR - Port Toggle Output Register */ +/*! @{ */ #define GPIO_PTOR_PTTO_MASK (0xFFFFFFFFU) #define GPIO_PTOR_PTTO_SHIFT (0U) +/*! PTTO - Port Toggle Output + * 0b00000000000000000000000000000000..Corresponding bit in PDORn does not change. + * 0b00000000000000000000000000000001..Corresponding bit in PDORn is set to the inverse of its existing logic state. + */ #define GPIO_PTOR_PTTO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO_SHIFT)) & GPIO_PTOR_PTTO_MASK) +/*! @} */ /*! @name PDIR - Port Data Input Register */ +/*! @{ */ #define GPIO_PDIR_PDI_MASK (0xFFFFFFFFU) #define GPIO_PDIR_PDI_SHIFT (0U) +/*! PDI - Port Data Input + * 0b00000000000000000000000000000000..Pin logic level is logic 0, or is not configured for use by digital function. + * 0b00000000000000000000000000000001..Pin logic level is logic 1. + */ #define GPIO_PDIR_PDI(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI_SHIFT)) & GPIO_PDIR_PDI_MASK) +/*! @} */ /*! @name PDDR - Port Data Direction Register */ +/*! @{ */ #define GPIO_PDDR_PDD_MASK (0xFFFFFFFFU) #define GPIO_PDDR_PDD_SHIFT (0U) +/*! PDD - Port Data Direction + * 0b00000000000000000000000000000000..Pin is configured as general-purpose input, for the GPIO function. + * 0b00000000000000000000000000000001..Pin is configured as general-purpose output, for the GPIO function. + */ #define GPIO_PDDR_PDD(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD_SHIFT)) & GPIO_PDDR_PDD_MASK) +/*! @} */ /*! @@ -6998,157 +12217,318 @@ typedef struct { */ /*! @name A1 - I2C Address Register 1 */ +/*! @{ */ #define I2C_A1_AD_MASK (0xFEU) #define I2C_A1_AD_SHIFT (1U) #define I2C_A1_AD(x) (((uint8_t)(((uint8_t)(x)) << I2C_A1_AD_SHIFT)) & I2C_A1_AD_MASK) +/*! @} */ /*! @name F - I2C Frequency Divider register */ +/*! @{ */ #define I2C_F_ICR_MASK (0x3FU) #define I2C_F_ICR_SHIFT (0U) #define I2C_F_ICR(x) (((uint8_t)(((uint8_t)(x)) << I2C_F_ICR_SHIFT)) & I2C_F_ICR_MASK) #define I2C_F_MULT_MASK (0xC0U) #define I2C_F_MULT_SHIFT (6U) +/*! MULT - Multiplier Factor + * 0b00..mul = 1 + * 0b01..mul = 2 + * 0b10..mul = 4 + * 0b11..Reserved + */ #define I2C_F_MULT(x) (((uint8_t)(((uint8_t)(x)) << I2C_F_MULT_SHIFT)) & I2C_F_MULT_MASK) +/*! @} */ /*! @name C1 - I2C Control Register 1 */ +/*! @{ */ #define I2C_C1_DMAEN_MASK (0x1U) #define I2C_C1_DMAEN_SHIFT (0U) +/*! DMAEN - DMA Enable + * 0b0..All DMA signalling disabled. + * 0b1..DMA transfer is enabled. While SMB[FACK] = 0, the following conditions trigger the DMA request: a data byte is received, and either address or data is transmitted. (ACK/NACK is automatic) the first byte received matches the A1 register or is a general call address. If any address matching occurs, S[IAAS] and S[TCF] are set. If the direction of transfer is known from master to slave, then it is not required to check S[SRW]. With this assumption, DMA can also be used in this case. In other cases, if the master reads data from the slave, then it is required to rewrite the C1 register operation. With this assumption, DMA cannot be used. When FACK = 1, an address or a data byte is transmitted. + */ #define I2C_C1_DMAEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_DMAEN_SHIFT)) & I2C_C1_DMAEN_MASK) #define I2C_C1_WUEN_MASK (0x2U) #define I2C_C1_WUEN_SHIFT (1U) +/*! WUEN - Wakeup Enable + * 0b0..Normal operation. No interrupt generated when address matching in low power mode. + * 0b1..Enables the wakeup function in low power mode. + */ #define I2C_C1_WUEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_WUEN_SHIFT)) & I2C_C1_WUEN_MASK) #define I2C_C1_RSTA_MASK (0x4U) #define I2C_C1_RSTA_SHIFT (2U) #define I2C_C1_RSTA(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_RSTA_SHIFT)) & I2C_C1_RSTA_MASK) #define I2C_C1_TXAK_MASK (0x8U) #define I2C_C1_TXAK_SHIFT (3U) +/*! TXAK - Transmit Acknowledge Enable + * 0b0..An acknowledge signal is sent to the bus on the following receiving byte (if FACK is cleared) or the current receiving byte (if FACK is set). + * 0b1..No acknowledge signal is sent to the bus on the following receiving data byte (if FACK is cleared) or the current receiving data byte (if FACK is set). + */ #define I2C_C1_TXAK(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_TXAK_SHIFT)) & I2C_C1_TXAK_MASK) #define I2C_C1_TX_MASK (0x10U) #define I2C_C1_TX_SHIFT (4U) +/*! TX - Transmit Mode Select + * 0b0..Receive + * 0b1..Transmit + */ #define I2C_C1_TX(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_TX_SHIFT)) & I2C_C1_TX_MASK) #define I2C_C1_MST_MASK (0x20U) #define I2C_C1_MST_SHIFT (5U) +/*! MST - Master Mode Select + * 0b0..Slave mode + * 0b1..Master mode + */ #define I2C_C1_MST(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_MST_SHIFT)) & I2C_C1_MST_MASK) #define I2C_C1_IICIE_MASK (0x40U) #define I2C_C1_IICIE_SHIFT (6U) +/*! IICIE - I2C Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ #define I2C_C1_IICIE(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_IICIE_SHIFT)) & I2C_C1_IICIE_MASK) #define I2C_C1_IICEN_MASK (0x80U) #define I2C_C1_IICEN_SHIFT (7U) +/*! IICEN - I2C Enable + * 0b0..Disabled + * 0b1..Enabled + */ #define I2C_C1_IICEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_IICEN_SHIFT)) & I2C_C1_IICEN_MASK) +/*! @} */ /*! @name S - I2C Status register */ +/*! @{ */ #define I2C_S_RXAK_MASK (0x1U) #define I2C_S_RXAK_SHIFT (0U) +/*! RXAK - Receive Acknowledge + * 0b0..Acknowledge signal was received after the completion of one byte of data transmission on the bus + * 0b1..No acknowledge signal detected + */ #define I2C_S_RXAK(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_RXAK_SHIFT)) & I2C_S_RXAK_MASK) #define I2C_S_IICIF_MASK (0x2U) #define I2C_S_IICIF_SHIFT (1U) +/*! IICIF - Interrupt Flag + * 0b0..No interrupt pending + * 0b1..Interrupt pending + */ #define I2C_S_IICIF(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_IICIF_SHIFT)) & I2C_S_IICIF_MASK) #define I2C_S_SRW_MASK (0x4U) #define I2C_S_SRW_SHIFT (2U) +/*! SRW - Slave Read/Write + * 0b0..Slave receive, master writing to slave + * 0b1..Slave transmit, master reading from slave + */ #define I2C_S_SRW(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_SRW_SHIFT)) & I2C_S_SRW_MASK) #define I2C_S_RAM_MASK (0x8U) #define I2C_S_RAM_SHIFT (3U) +/*! RAM - Range Address Match + * 0b0..Not addressed + * 0b1..Addressed as a slave + */ #define I2C_S_RAM(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_RAM_SHIFT)) & I2C_S_RAM_MASK) #define I2C_S_ARBL_MASK (0x10U) #define I2C_S_ARBL_SHIFT (4U) +/*! ARBL - Arbitration Lost + * 0b0..Standard bus operation. + * 0b1..Loss of arbitration. + */ #define I2C_S_ARBL(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_ARBL_SHIFT)) & I2C_S_ARBL_MASK) #define I2C_S_BUSY_MASK (0x20U) #define I2C_S_BUSY_SHIFT (5U) +/*! BUSY - Bus Busy + * 0b0..Bus is idle + * 0b1..Bus is busy + */ #define I2C_S_BUSY(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_BUSY_SHIFT)) & I2C_S_BUSY_MASK) #define I2C_S_IAAS_MASK (0x40U) #define I2C_S_IAAS_SHIFT (6U) +/*! IAAS - Addressed As A Slave + * 0b0..Not addressed + * 0b1..Addressed as a slave + */ #define I2C_S_IAAS(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_IAAS_SHIFT)) & I2C_S_IAAS_MASK) #define I2C_S_TCF_MASK (0x80U) #define I2C_S_TCF_SHIFT (7U) +/*! TCF - Transfer Complete Flag + * 0b0..Transfer in progress + * 0b1..Transfer complete + */ #define I2C_S_TCF(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_TCF_SHIFT)) & I2C_S_TCF_MASK) +/*! @} */ /*! @name D - I2C Data I/O register */ +/*! @{ */ #define I2C_D_DATA_MASK (0xFFU) #define I2C_D_DATA_SHIFT (0U) #define I2C_D_DATA(x) (((uint8_t)(((uint8_t)(x)) << I2C_D_DATA_SHIFT)) & I2C_D_DATA_MASK) +/*! @} */ /*! @name C2 - I2C Control Register 2 */ +/*! @{ */ #define I2C_C2_AD_MASK (0x7U) #define I2C_C2_AD_SHIFT (0U) #define I2C_C2_AD(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_AD_SHIFT)) & I2C_C2_AD_MASK) #define I2C_C2_RMEN_MASK (0x8U) #define I2C_C2_RMEN_SHIFT (3U) +/*! RMEN - Range Address Matching Enable + * 0b0..Range mode disabled. No address matching occurs for an address within the range of values of the A1 and RA registers. + * 0b1..Range mode enabled. Address matching occurs when a slave receives an address within the range of values of the A1 and RA registers. + */ #define I2C_C2_RMEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_RMEN_SHIFT)) & I2C_C2_RMEN_MASK) #define I2C_C2_SBRC_MASK (0x10U) #define I2C_C2_SBRC_SHIFT (4U) +/*! SBRC - Slave Baud Rate Control + * 0b0..The slave baud rate follows the master baud rate and clock stretching may occur + * 0b1..Slave baud rate is independent of the master baud rate + */ #define I2C_C2_SBRC(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_SBRC_SHIFT)) & I2C_C2_SBRC_MASK) #define I2C_C2_HDRS_MASK (0x20U) #define I2C_C2_HDRS_SHIFT (5U) +/*! HDRS - High Drive Select + * 0b0..Normal drive mode + * 0b1..High drive mode + */ #define I2C_C2_HDRS(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_HDRS_SHIFT)) & I2C_C2_HDRS_MASK) #define I2C_C2_ADEXT_MASK (0x40U) #define I2C_C2_ADEXT_SHIFT (6U) +/*! ADEXT - Address Extension + * 0b0..7-bit address scheme + * 0b1..10-bit address scheme + */ #define I2C_C2_ADEXT(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_ADEXT_SHIFT)) & I2C_C2_ADEXT_MASK) #define I2C_C2_GCAEN_MASK (0x80U) #define I2C_C2_GCAEN_SHIFT (7U) +/*! GCAEN - General Call Address Enable + * 0b0..Disabled + * 0b1..Enabled + */ #define I2C_C2_GCAEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_GCAEN_SHIFT)) & I2C_C2_GCAEN_MASK) +/*! @} */ /*! @name FLT - I2C Programmable Input Glitch Filter register */ +/*! @{ */ #define I2C_FLT_FLT_MASK (0xFU) #define I2C_FLT_FLT_SHIFT (0U) +/*! FLT - I2C Programmable Filter Factor + * 0b0000..No filter/bypass + */ #define I2C_FLT_FLT(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_FLT_SHIFT)) & I2C_FLT_FLT_MASK) #define I2C_FLT_STARTF_MASK (0x10U) #define I2C_FLT_STARTF_SHIFT (4U) +/*! STARTF - I2C Bus Start Detect Flag + * 0b0..No start happens on I2C bus + * 0b1..Start detected on I2C bus + */ #define I2C_FLT_STARTF(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_STARTF_SHIFT)) & I2C_FLT_STARTF_MASK) #define I2C_FLT_SSIE_MASK (0x20U) #define I2C_FLT_SSIE_SHIFT (5U) +/*! SSIE - I2C Bus Stop or Start Interrupt Enable + * 0b0..Stop or start detection interrupt is disabled + * 0b1..Stop or start detection interrupt is enabled + */ #define I2C_FLT_SSIE(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_SSIE_SHIFT)) & I2C_FLT_SSIE_MASK) #define I2C_FLT_STOPF_MASK (0x40U) #define I2C_FLT_STOPF_SHIFT (6U) +/*! STOPF - I2C Bus Stop Detect Flag + * 0b0..No stop happens on I2C bus + * 0b1..Stop detected on I2C bus + */ #define I2C_FLT_STOPF(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_STOPF_SHIFT)) & I2C_FLT_STOPF_MASK) #define I2C_FLT_SHEN_MASK (0x80U) #define I2C_FLT_SHEN_SHIFT (7U) +/*! SHEN - Stop Hold Enable + * 0b0..Stop holdoff is disabled. The MCU's entry to stop mode is not gated. + * 0b1..Stop holdoff is enabled. + */ #define I2C_FLT_SHEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_SHEN_SHIFT)) & I2C_FLT_SHEN_MASK) +/*! @} */ /*! @name RA - I2C Range Address register */ +/*! @{ */ #define I2C_RA_RAD_MASK (0xFEU) #define I2C_RA_RAD_SHIFT (1U) #define I2C_RA_RAD(x) (((uint8_t)(((uint8_t)(x)) << I2C_RA_RAD_SHIFT)) & I2C_RA_RAD_MASK) +/*! @} */ /*! @name SMB - I2C SMBus Control and Status register */ +/*! @{ */ #define I2C_SMB_SHTF2IE_MASK (0x1U) #define I2C_SMB_SHTF2IE_SHIFT (0U) +/*! SHTF2IE - SHTF2 Interrupt Enable + * 0b0..SHTF2 interrupt is disabled + * 0b1..SHTF2 interrupt is enabled + */ #define I2C_SMB_SHTF2IE(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SHTF2IE_SHIFT)) & I2C_SMB_SHTF2IE_MASK) #define I2C_SMB_SHTF2_MASK (0x2U) #define I2C_SMB_SHTF2_SHIFT (1U) +/*! SHTF2 - SCL High Timeout Flag 2 + * 0b0..No SCL high and SDA low timeout occurs + * 0b1..SCL high and SDA low timeout occurs + */ #define I2C_SMB_SHTF2(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SHTF2_SHIFT)) & I2C_SMB_SHTF2_MASK) #define I2C_SMB_SHTF1_MASK (0x4U) #define I2C_SMB_SHTF1_SHIFT (2U) +/*! SHTF1 - SCL High Timeout Flag 1 + * 0b0..No SCL high and SDA high timeout occurs + * 0b1..SCL high and SDA high timeout occurs + */ #define I2C_SMB_SHTF1(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SHTF1_SHIFT)) & I2C_SMB_SHTF1_MASK) #define I2C_SMB_SLTF_MASK (0x8U) #define I2C_SMB_SLTF_SHIFT (3U) +/*! SLTF - SCL Low Timeout Flag + * 0b0..No low timeout occurs + * 0b1..Low timeout occurs + */ #define I2C_SMB_SLTF(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SLTF_SHIFT)) & I2C_SMB_SLTF_MASK) #define I2C_SMB_TCKSEL_MASK (0x10U) #define I2C_SMB_TCKSEL_SHIFT (4U) +/*! TCKSEL - Timeout Counter Clock Select + * 0b0..Timeout counter counts at the frequency of the I2C module clock / 64 + * 0b1..Timeout counter counts at the frequency of the I2C module clock + */ #define I2C_SMB_TCKSEL(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_TCKSEL_SHIFT)) & I2C_SMB_TCKSEL_MASK) #define I2C_SMB_SIICAEN_MASK (0x20U) #define I2C_SMB_SIICAEN_SHIFT (5U) +/*! SIICAEN - Second I2C Address Enable + * 0b0..I2C address register 2 matching is disabled + * 0b1..I2C address register 2 matching is enabled + */ #define I2C_SMB_SIICAEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SIICAEN_SHIFT)) & I2C_SMB_SIICAEN_MASK) #define I2C_SMB_ALERTEN_MASK (0x40U) #define I2C_SMB_ALERTEN_SHIFT (6U) +/*! ALERTEN - SMBus Alert Response Address Enable + * 0b0..SMBus alert response address matching is disabled + * 0b1..SMBus alert response address matching is enabled + */ #define I2C_SMB_ALERTEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_ALERTEN_SHIFT)) & I2C_SMB_ALERTEN_MASK) #define I2C_SMB_FACK_MASK (0x80U) #define I2C_SMB_FACK_SHIFT (7U) +/*! FACK - Fast NACK/ACK Enable + * 0b0..An ACK or NACK is sent on the following receiving data byte + * 0b1..Writing 0 to TXAK after receiving a data byte generates an ACK. Writing 1 to TXAK after receiving a data byte generates a NACK. + */ #define I2C_SMB_FACK(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_FACK_SHIFT)) & I2C_SMB_FACK_MASK) +/*! @} */ /*! @name A2 - I2C Address Register 2 */ +/*! @{ */ #define I2C_A2_SAD_MASK (0xFEU) #define I2C_A2_SAD_SHIFT (1U) #define I2C_A2_SAD(x) (((uint8_t)(((uint8_t)(x)) << I2C_A2_SAD_SHIFT)) & I2C_A2_SAD_MASK) +/*! @} */ /*! @name SLTH - I2C SCL Low Timeout Register High */ +/*! @{ */ #define I2C_SLTH_SSLT_MASK (0xFFU) #define I2C_SLTH_SSLT_SHIFT (0U) #define I2C_SLTH_SSLT(x) (((uint8_t)(((uint8_t)(x)) << I2C_SLTH_SSLT_SHIFT)) & I2C_SLTH_SSLT_MASK) +/*! @} */ /*! @name SLTL - I2C SCL Low Timeout Register Low */ +/*! @{ */ #define I2C_SLTL_SSLT_MASK (0xFFU) #define I2C_SLTL_SSLT_SHIFT (0U) #define I2C_SLTL_SSLT(x) (((uint8_t)(((uint8_t)(x)) << I2C_SLTL_SSLT_SHIFT)) & I2C_SLTL_SSLT_MASK) +/*! @} */ /*! @@ -7232,109 +12612,238 @@ typedef struct { */ /*! @name TCSR - SAI Transmit Control Register */ +/*! @{ */ #define I2S_TCSR_FRDE_MASK (0x1U) #define I2S_TCSR_FRDE_SHIFT (0U) +/*! FRDE - FIFO Request DMA Enable + * 0b0..Disables the DMA request. + * 0b1..Enables the DMA request. + */ #define I2S_TCSR_FRDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRDE_SHIFT)) & I2S_TCSR_FRDE_MASK) #define I2S_TCSR_FWDE_MASK (0x2U) #define I2S_TCSR_FWDE_SHIFT (1U) +/*! FWDE - FIFO Warning DMA Enable + * 0b0..Disables the DMA request. + * 0b1..Enables the DMA request. + */ #define I2S_TCSR_FWDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWDE_SHIFT)) & I2S_TCSR_FWDE_MASK) #define I2S_TCSR_FRIE_MASK (0x100U) #define I2S_TCSR_FRIE_SHIFT (8U) +/*! FRIE - FIFO Request Interrupt Enable + * 0b0..Disables the interrupt. + * 0b1..Enables the interrupt. + */ #define I2S_TCSR_FRIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRIE_SHIFT)) & I2S_TCSR_FRIE_MASK) #define I2S_TCSR_FWIE_MASK (0x200U) #define I2S_TCSR_FWIE_SHIFT (9U) +/*! FWIE - FIFO Warning Interrupt Enable + * 0b0..Disables the interrupt. + * 0b1..Enables the interrupt. + */ #define I2S_TCSR_FWIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWIE_SHIFT)) & I2S_TCSR_FWIE_MASK) #define I2S_TCSR_FEIE_MASK (0x400U) #define I2S_TCSR_FEIE_SHIFT (10U) +/*! FEIE - FIFO Error Interrupt Enable + * 0b0..Disables the interrupt. + * 0b1..Enables the interrupt. + */ #define I2S_TCSR_FEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEIE_SHIFT)) & I2S_TCSR_FEIE_MASK) #define I2S_TCSR_SEIE_MASK (0x800U) #define I2S_TCSR_SEIE_SHIFT (11U) +/*! SEIE - Sync Error Interrupt Enable + * 0b0..Disables interrupt. + * 0b1..Enables interrupt. + */ #define I2S_TCSR_SEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEIE_SHIFT)) & I2S_TCSR_SEIE_MASK) #define I2S_TCSR_WSIE_MASK (0x1000U) #define I2S_TCSR_WSIE_SHIFT (12U) +/*! WSIE - Word Start Interrupt Enable + * 0b0..Disables interrupt. + * 0b1..Enables interrupt. + */ #define I2S_TCSR_WSIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSIE_SHIFT)) & I2S_TCSR_WSIE_MASK) #define I2S_TCSR_FRF_MASK (0x10000U) #define I2S_TCSR_FRF_SHIFT (16U) +/*! FRF - FIFO Request Flag + * 0b0..Transmit FIFO watermark has not been reached. + * 0b1..Transmit FIFO watermark has been reached. + */ #define I2S_TCSR_FRF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRF_SHIFT)) & I2S_TCSR_FRF_MASK) #define I2S_TCSR_FWF_MASK (0x20000U) #define I2S_TCSR_FWF_SHIFT (17U) +/*! FWF - FIFO Warning Flag + * 0b0..No enabled transmit FIFO is empty. + * 0b1..Enabled transmit FIFO is empty. + */ #define I2S_TCSR_FWF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWF_SHIFT)) & I2S_TCSR_FWF_MASK) #define I2S_TCSR_FEF_MASK (0x40000U) #define I2S_TCSR_FEF_SHIFT (18U) +/*! FEF - FIFO Error Flag + * 0b0..Transmit underrun not detected. + * 0b1..Transmit underrun detected. + */ #define I2S_TCSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEF_SHIFT)) & I2S_TCSR_FEF_MASK) #define I2S_TCSR_SEF_MASK (0x80000U) #define I2S_TCSR_SEF_SHIFT (19U) +/*! SEF - Sync Error Flag + * 0b0..Sync error not detected. + * 0b1..Frame sync error detected. + */ #define I2S_TCSR_SEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEF_SHIFT)) & I2S_TCSR_SEF_MASK) #define I2S_TCSR_WSF_MASK (0x100000U) #define I2S_TCSR_WSF_SHIFT (20U) +/*! WSF - Word Start Flag + * 0b0..Start of word not detected. + * 0b1..Start of word detected. + */ #define I2S_TCSR_WSF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSF_SHIFT)) & I2S_TCSR_WSF_MASK) #define I2S_TCSR_SR_MASK (0x1000000U) #define I2S_TCSR_SR_SHIFT (24U) +/*! SR - Software Reset + * 0b0..No effect. + * 0b1..Software reset. + */ #define I2S_TCSR_SR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SR_SHIFT)) & I2S_TCSR_SR_MASK) #define I2S_TCSR_FR_MASK (0x2000000U) #define I2S_TCSR_FR_SHIFT (25U) +/*! FR - FIFO Reset + * 0b0..No effect. + * 0b1..FIFO reset. + */ #define I2S_TCSR_FR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FR_SHIFT)) & I2S_TCSR_FR_MASK) #define I2S_TCSR_BCE_MASK (0x10000000U) #define I2S_TCSR_BCE_SHIFT (28U) +/*! BCE - Bit Clock Enable + * 0b0..Transmit bit clock is disabled. + * 0b1..Transmit bit clock is enabled. + */ #define I2S_TCSR_BCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_BCE_SHIFT)) & I2S_TCSR_BCE_MASK) #define I2S_TCSR_DBGE_MASK (0x20000000U) #define I2S_TCSR_DBGE_SHIFT (29U) +/*! DBGE - Debug Enable + * 0b0..Transmitter is disabled in Debug mode, after completing the current frame. + * 0b1..Transmitter is enabled in Debug mode. + */ #define I2S_TCSR_DBGE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_DBGE_SHIFT)) & I2S_TCSR_DBGE_MASK) #define I2S_TCSR_STOPE_MASK (0x40000000U) #define I2S_TCSR_STOPE_SHIFT (30U) +/*! STOPE - Stop Enable + * 0b0..Transmitter disabled in Stop mode. + * 0b1..Transmitter enabled in Stop mode. + */ #define I2S_TCSR_STOPE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_STOPE_SHIFT)) & I2S_TCSR_STOPE_MASK) #define I2S_TCSR_TE_MASK (0x80000000U) #define I2S_TCSR_TE_SHIFT (31U) +/*! TE - Transmitter Enable + * 0b0..Transmitter is disabled. + * 0b1..Transmitter is enabled, or transmitter has been disabled and has not yet reached end of frame. + */ #define I2S_TCSR_TE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_TE_SHIFT)) & I2S_TCSR_TE_MASK) +/*! @} */ /*! @name TCR1 - SAI Transmit Configuration 1 Register */ +/*! @{ */ #define I2S_TCR1_TFW_MASK (0x7U) #define I2S_TCR1_TFW_SHIFT (0U) #define I2S_TCR1_TFW(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR1_TFW_SHIFT)) & I2S_TCR1_TFW_MASK) +/*! @} */ /*! @name TCR2 - SAI Transmit Configuration 2 Register */ +/*! @{ */ #define I2S_TCR2_DIV_MASK (0xFFU) #define I2S_TCR2_DIV_SHIFT (0U) #define I2S_TCR2_DIV(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_DIV_SHIFT)) & I2S_TCR2_DIV_MASK) #define I2S_TCR2_BCD_MASK (0x1000000U) #define I2S_TCR2_BCD_SHIFT (24U) +/*! BCD - Bit Clock Direction + * 0b0..Bit clock is generated externally in Slave mode. + * 0b1..Bit clock is generated internally in Master mode. + */ #define I2S_TCR2_BCD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCD_SHIFT)) & I2S_TCR2_BCD_MASK) #define I2S_TCR2_BCP_MASK (0x2000000U) #define I2S_TCR2_BCP_SHIFT (25U) +/*! BCP - Bit Clock Polarity + * 0b0..Bit clock is active high with drive outputs on rising edge and sample inputs on falling edge. + * 0b1..Bit clock is active low with drive outputs on falling edge and sample inputs on rising edge. + */ #define I2S_TCR2_BCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCP_SHIFT)) & I2S_TCR2_BCP_MASK) #define I2S_TCR2_MSEL_MASK (0xC000000U) #define I2S_TCR2_MSEL_SHIFT (26U) +/*! MSEL - MCLK Select + * 0b00..Bus Clock selected. + * 0b01..Master Clock (MCLK) 1 option selected. + * 0b10..Master Clock (MCLK) 2 option selected. + * 0b11..Master Clock (MCLK) 3 option selected. + */ #define I2S_TCR2_MSEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_MSEL_SHIFT)) & I2S_TCR2_MSEL_MASK) #define I2S_TCR2_BCI_MASK (0x10000000U) #define I2S_TCR2_BCI_SHIFT (28U) +/*! BCI - Bit Clock Input + * 0b0..No effect. + * 0b1..Internal logic is clocked as if bit clock was externally generated. + */ #define I2S_TCR2_BCI(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCI_SHIFT)) & I2S_TCR2_BCI_MASK) #define I2S_TCR2_BCS_MASK (0x20000000U) #define I2S_TCR2_BCS_SHIFT (29U) +/*! BCS - Bit Clock Swap + * 0b0..Use the normal bit clock source. + * 0b1..Swap the bit clock source. + */ #define I2S_TCR2_BCS(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCS_SHIFT)) & I2S_TCR2_BCS_MASK) #define I2S_TCR2_SYNC_MASK (0xC0000000U) #define I2S_TCR2_SYNC_SHIFT (30U) +/*! SYNC - Synchronous Mode + * 0b00..Asynchronous mode. + * 0b01..Synchronous with receiver. + * 0b10..Synchronous with another SAI transmitter. + * 0b11..Synchronous with another SAI receiver. + */ #define I2S_TCR2_SYNC(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_SYNC_SHIFT)) & I2S_TCR2_SYNC_MASK) +/*! @} */ /*! @name TCR3 - SAI Transmit Configuration 3 Register */ +/*! @{ */ #define I2S_TCR3_WDFL_MASK (0x1FU) #define I2S_TCR3_WDFL_SHIFT (0U) #define I2S_TCR3_WDFL(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_WDFL_SHIFT)) & I2S_TCR3_WDFL_MASK) #define I2S_TCR3_TCE_MASK (0x30000U) #define I2S_TCR3_TCE_SHIFT (16U) +/*! TCE - Transmit Channel Enable + * 0b00..Transmit data channel N is disabled. + * 0b01..Transmit data channel N is enabled. + */ #define I2S_TCR3_TCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_TCE_SHIFT)) & I2S_TCR3_TCE_MASK) +/*! @} */ /*! @name TCR4 - SAI Transmit Configuration 4 Register */ +/*! @{ */ #define I2S_TCR4_FSD_MASK (0x1U) #define I2S_TCR4_FSD_SHIFT (0U) +/*! FSD - Frame Sync Direction + * 0b0..Frame sync is generated externally in Slave mode. + * 0b1..Frame sync is generated internally in Master mode. + */ #define I2S_TCR4_FSD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSD_SHIFT)) & I2S_TCR4_FSD_MASK) #define I2S_TCR4_FSP_MASK (0x2U) #define I2S_TCR4_FSP_SHIFT (1U) +/*! FSP - Frame Sync Polarity + * 0b0..Frame sync is active high. + * 0b1..Frame sync is active low. + */ #define I2S_TCR4_FSP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSP_SHIFT)) & I2S_TCR4_FSP_MASK) #define I2S_TCR4_FSE_MASK (0x8U) #define I2S_TCR4_FSE_SHIFT (3U) +/*! FSE - Frame Sync Early + * 0b0..Frame sync asserts with the first bit of the frame. + * 0b1..Frame sync asserts one bit before the first bit of the frame. + */ #define I2S_TCR4_FSE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSE_SHIFT)) & I2S_TCR4_FSE_MASK) #define I2S_TCR4_MF_MASK (0x10U) #define I2S_TCR4_MF_SHIFT (4U) +/*! MF - MSB First + * 0b0..LSB is transmitted first. + * 0b1..MSB is transmitted first. + */ #define I2S_TCR4_MF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_MF_SHIFT)) & I2S_TCR4_MF_MASK) #define I2S_TCR4_SYWD_MASK (0x1F00U) #define I2S_TCR4_SYWD_SHIFT (8U) @@ -7342,8 +12851,10 @@ typedef struct { #define I2S_TCR4_FRSZ_MASK (0x1F0000U) #define I2S_TCR4_FRSZ_SHIFT (16U) #define I2S_TCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FRSZ_SHIFT)) & I2S_TCR4_FRSZ_MASK) +/*! @} */ /*! @name TCR5 - SAI Transmit Configuration 5 Register */ +/*! @{ */ #define I2S_TCR5_FBT_MASK (0x1F00U) #define I2S_TCR5_FBT_SHIFT (8U) #define I2S_TCR5_FBT(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_FBT_SHIFT)) & I2S_TCR5_FBT_MASK) @@ -7353,135 +12864,275 @@ typedef struct { #define I2S_TCR5_WNW_MASK (0x1F000000U) #define I2S_TCR5_WNW_SHIFT (24U) #define I2S_TCR5_WNW(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_WNW_SHIFT)) & I2S_TCR5_WNW_MASK) +/*! @} */ /*! @name TDR - SAI Transmit Data Register */ +/*! @{ */ #define I2S_TDR_TDR_MASK (0xFFFFFFFFU) #define I2S_TDR_TDR_SHIFT (0U) #define I2S_TDR_TDR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TDR_TDR_SHIFT)) & I2S_TDR_TDR_MASK) +/*! @} */ /* The count of I2S_TDR */ #define I2S_TDR_COUNT (2U) /*! @name TFR - SAI Transmit FIFO Register */ +/*! @{ */ #define I2S_TFR_RFP_MASK (0xFU) #define I2S_TFR_RFP_SHIFT (0U) #define I2S_TFR_RFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TFR_RFP_SHIFT)) & I2S_TFR_RFP_MASK) #define I2S_TFR_WFP_MASK (0xF0000U) #define I2S_TFR_WFP_SHIFT (16U) #define I2S_TFR_WFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TFR_WFP_SHIFT)) & I2S_TFR_WFP_MASK) +/*! @} */ /* The count of I2S_TFR */ #define I2S_TFR_COUNT (2U) /*! @name TMR - SAI Transmit Mask Register */ +/*! @{ */ #define I2S_TMR_TWM_MASK (0xFFFFFFFFU) #define I2S_TMR_TWM_SHIFT (0U) +/*! TWM - Transmit Word Mask + * 0b00000000000000000000000000000000..Word N is enabled. + * 0b00000000000000000000000000000001..Word N is masked. The transmit data pins are tri-stated when masked. + */ #define I2S_TMR_TWM(x) (((uint32_t)(((uint32_t)(x)) << I2S_TMR_TWM_SHIFT)) & I2S_TMR_TWM_MASK) +/*! @} */ /*! @name RCSR - SAI Receive Control Register */ +/*! @{ */ #define I2S_RCSR_FRDE_MASK (0x1U) #define I2S_RCSR_FRDE_SHIFT (0U) +/*! FRDE - FIFO Request DMA Enable + * 0b0..Disables the DMA request. + * 0b1..Enables the DMA request. + */ #define I2S_RCSR_FRDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRDE_SHIFT)) & I2S_RCSR_FRDE_MASK) #define I2S_RCSR_FWDE_MASK (0x2U) #define I2S_RCSR_FWDE_SHIFT (1U) +/*! FWDE - FIFO Warning DMA Enable + * 0b0..Disables the DMA request. + * 0b1..Enables the DMA request. + */ #define I2S_RCSR_FWDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWDE_SHIFT)) & I2S_RCSR_FWDE_MASK) #define I2S_RCSR_FRIE_MASK (0x100U) #define I2S_RCSR_FRIE_SHIFT (8U) +/*! FRIE - FIFO Request Interrupt Enable + * 0b0..Disables the interrupt. + * 0b1..Enables the interrupt. + */ #define I2S_RCSR_FRIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRIE_SHIFT)) & I2S_RCSR_FRIE_MASK) #define I2S_RCSR_FWIE_MASK (0x200U) #define I2S_RCSR_FWIE_SHIFT (9U) +/*! FWIE - FIFO Warning Interrupt Enable + * 0b0..Disables the interrupt. + * 0b1..Enables the interrupt. + */ #define I2S_RCSR_FWIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWIE_SHIFT)) & I2S_RCSR_FWIE_MASK) #define I2S_RCSR_FEIE_MASK (0x400U) #define I2S_RCSR_FEIE_SHIFT (10U) +/*! FEIE - FIFO Error Interrupt Enable + * 0b0..Disables the interrupt. + * 0b1..Enables the interrupt. + */ #define I2S_RCSR_FEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEIE_SHIFT)) & I2S_RCSR_FEIE_MASK) #define I2S_RCSR_SEIE_MASK (0x800U) #define I2S_RCSR_SEIE_SHIFT (11U) +/*! SEIE - Sync Error Interrupt Enable + * 0b0..Disables interrupt. + * 0b1..Enables interrupt. + */ #define I2S_RCSR_SEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEIE_SHIFT)) & I2S_RCSR_SEIE_MASK) #define I2S_RCSR_WSIE_MASK (0x1000U) #define I2S_RCSR_WSIE_SHIFT (12U) +/*! WSIE - Word Start Interrupt Enable + * 0b0..Disables interrupt. + * 0b1..Enables interrupt. + */ #define I2S_RCSR_WSIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSIE_SHIFT)) & I2S_RCSR_WSIE_MASK) #define I2S_RCSR_FRF_MASK (0x10000U) #define I2S_RCSR_FRF_SHIFT (16U) +/*! FRF - FIFO Request Flag + * 0b0..Receive FIFO watermark not reached. + * 0b1..Receive FIFO watermark has been reached. + */ #define I2S_RCSR_FRF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRF_SHIFT)) & I2S_RCSR_FRF_MASK) #define I2S_RCSR_FWF_MASK (0x20000U) #define I2S_RCSR_FWF_SHIFT (17U) +/*! FWF - FIFO Warning Flag + * 0b0..No enabled receive FIFO is full. + * 0b1..Enabled receive FIFO is full. + */ #define I2S_RCSR_FWF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWF_SHIFT)) & I2S_RCSR_FWF_MASK) #define I2S_RCSR_FEF_MASK (0x40000U) #define I2S_RCSR_FEF_SHIFT (18U) +/*! FEF - FIFO Error Flag + * 0b0..Receive overflow not detected. + * 0b1..Receive overflow detected. + */ #define I2S_RCSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEF_SHIFT)) & I2S_RCSR_FEF_MASK) #define I2S_RCSR_SEF_MASK (0x80000U) #define I2S_RCSR_SEF_SHIFT (19U) +/*! SEF - Sync Error Flag + * 0b0..Sync error not detected. + * 0b1..Frame sync error detected. + */ #define I2S_RCSR_SEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEF_SHIFT)) & I2S_RCSR_SEF_MASK) #define I2S_RCSR_WSF_MASK (0x100000U) #define I2S_RCSR_WSF_SHIFT (20U) +/*! WSF - Word Start Flag + * 0b0..Start of word not detected. + * 0b1..Start of word detected. + */ #define I2S_RCSR_WSF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSF_SHIFT)) & I2S_RCSR_WSF_MASK) #define I2S_RCSR_SR_MASK (0x1000000U) #define I2S_RCSR_SR_SHIFT (24U) +/*! SR - Software Reset + * 0b0..No effect. + * 0b1..Software reset. + */ #define I2S_RCSR_SR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SR_SHIFT)) & I2S_RCSR_SR_MASK) #define I2S_RCSR_FR_MASK (0x2000000U) #define I2S_RCSR_FR_SHIFT (25U) +/*! FR - FIFO Reset + * 0b0..No effect. + * 0b1..FIFO reset. + */ #define I2S_RCSR_FR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FR_SHIFT)) & I2S_RCSR_FR_MASK) #define I2S_RCSR_BCE_MASK (0x10000000U) #define I2S_RCSR_BCE_SHIFT (28U) +/*! BCE - Bit Clock Enable + * 0b0..Receive bit clock is disabled. + * 0b1..Receive bit clock is enabled. + */ #define I2S_RCSR_BCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_BCE_SHIFT)) & I2S_RCSR_BCE_MASK) #define I2S_RCSR_DBGE_MASK (0x20000000U) #define I2S_RCSR_DBGE_SHIFT (29U) +/*! DBGE - Debug Enable + * 0b0..Receiver is disabled in Debug mode, after completing the current frame. + * 0b1..Receiver is enabled in Debug mode. + */ #define I2S_RCSR_DBGE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_DBGE_SHIFT)) & I2S_RCSR_DBGE_MASK) #define I2S_RCSR_STOPE_MASK (0x40000000U) #define I2S_RCSR_STOPE_SHIFT (30U) +/*! STOPE - Stop Enable + * 0b0..Receiver disabled in Stop mode. + * 0b1..Receiver enabled in Stop mode. + */ #define I2S_RCSR_STOPE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_STOPE_SHIFT)) & I2S_RCSR_STOPE_MASK) #define I2S_RCSR_RE_MASK (0x80000000U) #define I2S_RCSR_RE_SHIFT (31U) +/*! RE - Receiver Enable + * 0b0..Receiver is disabled. + * 0b1..Receiver is enabled, or receiver has been disabled and has not yet reached end of frame. + */ #define I2S_RCSR_RE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_RE_SHIFT)) & I2S_RCSR_RE_MASK) +/*! @} */ /*! @name RCR1 - SAI Receive Configuration 1 Register */ +/*! @{ */ #define I2S_RCR1_RFW_MASK (0x7U) #define I2S_RCR1_RFW_SHIFT (0U) #define I2S_RCR1_RFW(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR1_RFW_SHIFT)) & I2S_RCR1_RFW_MASK) +/*! @} */ /*! @name RCR2 - SAI Receive Configuration 2 Register */ +/*! @{ */ #define I2S_RCR2_DIV_MASK (0xFFU) #define I2S_RCR2_DIV_SHIFT (0U) #define I2S_RCR2_DIV(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_DIV_SHIFT)) & I2S_RCR2_DIV_MASK) #define I2S_RCR2_BCD_MASK (0x1000000U) #define I2S_RCR2_BCD_SHIFT (24U) +/*! BCD - Bit Clock Direction + * 0b0..Bit clock is generated externally in Slave mode. + * 0b1..Bit clock is generated internally in Master mode. + */ #define I2S_RCR2_BCD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCD_SHIFT)) & I2S_RCR2_BCD_MASK) #define I2S_RCR2_BCP_MASK (0x2000000U) #define I2S_RCR2_BCP_SHIFT (25U) +/*! BCP - Bit Clock Polarity + * 0b0..Bit Clock is active high with drive outputs on rising edge and sample inputs on falling edge. + * 0b1..Bit Clock is active low with drive outputs on falling edge and sample inputs on rising edge. + */ #define I2S_RCR2_BCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCP_SHIFT)) & I2S_RCR2_BCP_MASK) #define I2S_RCR2_MSEL_MASK (0xC000000U) #define I2S_RCR2_MSEL_SHIFT (26U) +/*! MSEL - MCLK Select + * 0b00..Bus Clock selected. + * 0b01..Master Clock (MCLK) 1 option selected. + * 0b10..Master Clock (MCLK) 2 option selected. + * 0b11..Master Clock (MCLK) 3 option selected. + */ #define I2S_RCR2_MSEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_MSEL_SHIFT)) & I2S_RCR2_MSEL_MASK) #define I2S_RCR2_BCI_MASK (0x10000000U) #define I2S_RCR2_BCI_SHIFT (28U) +/*! BCI - Bit Clock Input + * 0b0..No effect. + * 0b1..Internal logic is clocked as if bit clock was externally generated. + */ #define I2S_RCR2_BCI(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCI_SHIFT)) & I2S_RCR2_BCI_MASK) #define I2S_RCR2_BCS_MASK (0x20000000U) #define I2S_RCR2_BCS_SHIFT (29U) +/*! BCS - Bit Clock Swap + * 0b0..Use the normal bit clock source. + * 0b1..Swap the bit clock source. + */ #define I2S_RCR2_BCS(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCS_SHIFT)) & I2S_RCR2_BCS_MASK) #define I2S_RCR2_SYNC_MASK (0xC0000000U) #define I2S_RCR2_SYNC_SHIFT (30U) +/*! SYNC - Synchronous Mode + * 0b00..Asynchronous mode. + * 0b01..Synchronous with transmitter. + * 0b10..Synchronous with another SAI receiver. + * 0b11..Synchronous with another SAI transmitter. + */ #define I2S_RCR2_SYNC(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_SYNC_SHIFT)) & I2S_RCR2_SYNC_MASK) +/*! @} */ /*! @name RCR3 - SAI Receive Configuration 3 Register */ +/*! @{ */ #define I2S_RCR3_WDFL_MASK (0x1FU) #define I2S_RCR3_WDFL_SHIFT (0U) #define I2S_RCR3_WDFL(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_WDFL_SHIFT)) & I2S_RCR3_WDFL_MASK) #define I2S_RCR3_RCE_MASK (0x30000U) #define I2S_RCR3_RCE_SHIFT (16U) +/*! RCE - Receive Channel Enable + * 0b00..Receive data channel N is disabled. + * 0b01..Receive data channel N is enabled. + */ #define I2S_RCR3_RCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_RCE_SHIFT)) & I2S_RCR3_RCE_MASK) +/*! @} */ /*! @name RCR4 - SAI Receive Configuration 4 Register */ +/*! @{ */ #define I2S_RCR4_FSD_MASK (0x1U) #define I2S_RCR4_FSD_SHIFT (0U) +/*! FSD - Frame Sync Direction + * 0b0..Frame Sync is generated externally in Slave mode. + * 0b1..Frame Sync is generated internally in Master mode. + */ #define I2S_RCR4_FSD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSD_SHIFT)) & I2S_RCR4_FSD_MASK) #define I2S_RCR4_FSP_MASK (0x2U) #define I2S_RCR4_FSP_SHIFT (1U) +/*! FSP - Frame Sync Polarity + * 0b0..Frame sync is active high. + * 0b1..Frame sync is active low. + */ #define I2S_RCR4_FSP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSP_SHIFT)) & I2S_RCR4_FSP_MASK) #define I2S_RCR4_FSE_MASK (0x8U) #define I2S_RCR4_FSE_SHIFT (3U) +/*! FSE - Frame Sync Early + * 0b0..Frame sync asserts with the first bit of the frame. + * 0b1..Frame sync asserts one bit before the first bit of the frame. + */ #define I2S_RCR4_FSE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSE_SHIFT)) & I2S_RCR4_FSE_MASK) #define I2S_RCR4_MF_MASK (0x10U) #define I2S_RCR4_MF_SHIFT (4U) +/*! MF - MSB First + * 0b0..LSB is received first. + * 0b1..MSB is received first. + */ #define I2S_RCR4_MF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_MF_SHIFT)) & I2S_RCR4_MF_MASK) #define I2S_RCR4_SYWD_MASK (0x1F00U) #define I2S_RCR4_SYWD_SHIFT (8U) @@ -7489,8 +13140,10 @@ typedef struct { #define I2S_RCR4_FRSZ_MASK (0x1F0000U) #define I2S_RCR4_FRSZ_SHIFT (16U) #define I2S_RCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FRSZ_SHIFT)) & I2S_RCR4_FRSZ_MASK) +/*! @} */ /*! @name RCR5 - SAI Receive Configuration 5 Register */ +/*! @{ */ #define I2S_RCR5_FBT_MASK (0x1F00U) #define I2S_RCR5_FBT_SHIFT (8U) #define I2S_RCR5_FBT(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_FBT_SHIFT)) & I2S_RCR5_FBT_MASK) @@ -7500,49 +13153,78 @@ typedef struct { #define I2S_RCR5_WNW_MASK (0x1F000000U) #define I2S_RCR5_WNW_SHIFT (24U) #define I2S_RCR5_WNW(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_WNW_SHIFT)) & I2S_RCR5_WNW_MASK) +/*! @} */ /*! @name RDR - SAI Receive Data Register */ +/*! @{ */ #define I2S_RDR_RDR_MASK (0xFFFFFFFFU) #define I2S_RDR_RDR_SHIFT (0U) #define I2S_RDR_RDR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RDR_RDR_SHIFT)) & I2S_RDR_RDR_MASK) +/*! @} */ /* The count of I2S_RDR */ #define I2S_RDR_COUNT (2U) /*! @name RFR - SAI Receive FIFO Register */ +/*! @{ */ #define I2S_RFR_RFP_MASK (0xFU) #define I2S_RFR_RFP_SHIFT (0U) #define I2S_RFR_RFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RFR_RFP_SHIFT)) & I2S_RFR_RFP_MASK) #define I2S_RFR_WFP_MASK (0xF0000U) #define I2S_RFR_WFP_SHIFT (16U) #define I2S_RFR_WFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RFR_WFP_SHIFT)) & I2S_RFR_WFP_MASK) +/*! @} */ /* The count of I2S_RFR */ #define I2S_RFR_COUNT (2U) /*! @name RMR - SAI Receive Mask Register */ +/*! @{ */ #define I2S_RMR_RWM_MASK (0xFFFFFFFFU) #define I2S_RMR_RWM_SHIFT (0U) +/*! RWM - Receive Word Mask + * 0b00000000000000000000000000000000..Word N is enabled. + * 0b00000000000000000000000000000001..Word N is masked. + */ #define I2S_RMR_RWM(x) (((uint32_t)(((uint32_t)(x)) << I2S_RMR_RWM_SHIFT)) & I2S_RMR_RWM_MASK) +/*! @} */ /*! @name MCR - SAI MCLK Control Register */ +/*! @{ */ #define I2S_MCR_MICS_MASK (0x3000000U) #define I2S_MCR_MICS_SHIFT (24U) +/*! MICS - MCLK Input Clock Select + * 0b00..MCLK divider input clock 0 selected. + * 0b01..MCLK divider input clock 1 selected. + * 0b10..MCLK divider input clock 2 selected. + * 0b11..MCLK divider input clock 3 selected. + */ #define I2S_MCR_MICS(x) (((uint32_t)(((uint32_t)(x)) << I2S_MCR_MICS_SHIFT)) & I2S_MCR_MICS_MASK) #define I2S_MCR_MOE_MASK (0x40000000U) #define I2S_MCR_MOE_SHIFT (30U) +/*! MOE - MCLK Output Enable + * 0b0..MCLK signal pin is configured as an input that bypasses the MCLK divider. + * 0b1..MCLK signal pin is configured as an output from the MCLK divider and the MCLK divider is enabled. + */ #define I2S_MCR_MOE(x) (((uint32_t)(((uint32_t)(x)) << I2S_MCR_MOE_SHIFT)) & I2S_MCR_MOE_MASK) #define I2S_MCR_DUF_MASK (0x80000000U) #define I2S_MCR_DUF_SHIFT (31U) +/*! DUF - Divider Update Flag + * 0b0..MCLK divider ratio is not being updated currently. + * 0b1..MCLK divider ratio is updating on-the-fly. Further updates to the MCLK divider ratio are blocked while this flag remains set. + */ #define I2S_MCR_DUF(x) (((uint32_t)(((uint32_t)(x)) << I2S_MCR_DUF_SHIFT)) & I2S_MCR_DUF_MASK) +/*! @} */ /*! @name MDR - SAI MCLK Divide Register */ +/*! @{ */ #define I2S_MDR_DIVIDE_MASK (0xFFFU) #define I2S_MDR_DIVIDE_SHIFT (0U) #define I2S_MDR_DIVIDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_MDR_DIVIDE_SHIFT)) & I2S_MDR_DIVIDE_MASK) #define I2S_MDR_FRACT_MASK (0xFF000U) #define I2S_MDR_FRACT_SHIFT (12U) #define I2S_MDR_FRACT(x) (((uint32_t)(((uint32_t)(x)) << I2S_MDR_FRACT_SHIFT)) & I2S_MDR_FRACT_MASK) +/*! @} */ /*! @@ -7602,194 +13284,476 @@ typedef struct { */ /*! @name PE1 - LLWU Pin Enable 1 register */ +/*! @{ */ #define LLWU_PE1_WUPE0_MASK (0x3U) #define LLWU_PE1_WUPE0_SHIFT (0U) +/*! WUPE0 - Wakeup Pin Enable For LLWU_P0 + * 0b00..External input pin disabled as wakeup input + * 0b01..External input pin enabled with rising edge detection + * 0b10..External input pin enabled with falling edge detection + * 0b11..External input pin enabled with any change detection + */ #define LLWU_PE1_WUPE0(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE0_SHIFT)) & LLWU_PE1_WUPE0_MASK) #define LLWU_PE1_WUPE1_MASK (0xCU) #define LLWU_PE1_WUPE1_SHIFT (2U) +/*! WUPE1 - Wakeup Pin Enable For LLWU_P1 + * 0b00..External input pin disabled as wakeup input + * 0b01..External input pin enabled with rising edge detection + * 0b10..External input pin enabled with falling edge detection + * 0b11..External input pin enabled with any change detection + */ #define LLWU_PE1_WUPE1(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE1_SHIFT)) & LLWU_PE1_WUPE1_MASK) #define LLWU_PE1_WUPE2_MASK (0x30U) #define LLWU_PE1_WUPE2_SHIFT (4U) +/*! WUPE2 - Wakeup Pin Enable For LLWU_P2 + * 0b00..External input pin disabled as wakeup input + * 0b01..External input pin enabled with rising edge detection + * 0b10..External input pin enabled with falling edge detection + * 0b11..External input pin enabled with any change detection + */ #define LLWU_PE1_WUPE2(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE2_SHIFT)) & LLWU_PE1_WUPE2_MASK) #define LLWU_PE1_WUPE3_MASK (0xC0U) #define LLWU_PE1_WUPE3_SHIFT (6U) +/*! WUPE3 - Wakeup Pin Enable For LLWU_P3 + * 0b00..External input pin disabled as wakeup input + * 0b01..External input pin enabled with rising edge detection + * 0b10..External input pin enabled with falling edge detection + * 0b11..External input pin enabled with any change detection + */ #define LLWU_PE1_WUPE3(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE3_SHIFT)) & LLWU_PE1_WUPE3_MASK) +/*! @} */ /*! @name PE2 - LLWU Pin Enable 2 register */ +/*! @{ */ #define LLWU_PE2_WUPE4_MASK (0x3U) #define LLWU_PE2_WUPE4_SHIFT (0U) +/*! WUPE4 - Wakeup Pin Enable For LLWU_P4 + * 0b00..External input pin disabled as wakeup input + * 0b01..External input pin enabled with rising edge detection + * 0b10..External input pin enabled with falling edge detection + * 0b11..External input pin enabled with any change detection + */ #define LLWU_PE2_WUPE4(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE4_SHIFT)) & LLWU_PE2_WUPE4_MASK) #define LLWU_PE2_WUPE5_MASK (0xCU) #define LLWU_PE2_WUPE5_SHIFT (2U) +/*! WUPE5 - Wakeup Pin Enable For LLWU_P5 + * 0b00..External input pin disabled as wakeup input + * 0b01..External input pin enabled with rising edge detection + * 0b10..External input pin enabled with falling edge detection + * 0b11..External input pin enabled with any change detection + */ #define LLWU_PE2_WUPE5(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE5_SHIFT)) & LLWU_PE2_WUPE5_MASK) #define LLWU_PE2_WUPE6_MASK (0x30U) #define LLWU_PE2_WUPE6_SHIFT (4U) +/*! WUPE6 - Wakeup Pin Enable For LLWU_P6 + * 0b00..External input pin disabled as wakeup input + * 0b01..External input pin enabled with rising edge detection + * 0b10..External input pin enabled with falling edge detection + * 0b11..External input pin enabled with any change detection + */ #define LLWU_PE2_WUPE6(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE6_SHIFT)) & LLWU_PE2_WUPE6_MASK) #define LLWU_PE2_WUPE7_MASK (0xC0U) #define LLWU_PE2_WUPE7_SHIFT (6U) +/*! WUPE7 - Wakeup Pin Enable For LLWU_P7 + * 0b00..External input pin disabled as wakeup input + * 0b01..External input pin enabled with rising edge detection + * 0b10..External input pin enabled with falling edge detection + * 0b11..External input pin enabled with any change detection + */ #define LLWU_PE2_WUPE7(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE7_SHIFT)) & LLWU_PE2_WUPE7_MASK) +/*! @} */ /*! @name PE3 - LLWU Pin Enable 3 register */ +/*! @{ */ #define LLWU_PE3_WUPE8_MASK (0x3U) #define LLWU_PE3_WUPE8_SHIFT (0U) +/*! WUPE8 - Wakeup Pin Enable For LLWU_P8 + * 0b00..External input pin disabled as wakeup input + * 0b01..External input pin enabled with rising edge detection + * 0b10..External input pin enabled with falling edge detection + * 0b11..External input pin enabled with any change detection + */ #define LLWU_PE3_WUPE8(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE3_WUPE8_SHIFT)) & LLWU_PE3_WUPE8_MASK) #define LLWU_PE3_WUPE9_MASK (0xCU) #define LLWU_PE3_WUPE9_SHIFT (2U) +/*! WUPE9 - Wakeup Pin Enable For LLWU_P9 + * 0b00..External input pin disabled as wakeup input + * 0b01..External input pin enabled with rising edge detection + * 0b10..External input pin enabled with falling edge detection + * 0b11..External input pin enabled with any change detection + */ #define LLWU_PE3_WUPE9(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE3_WUPE9_SHIFT)) & LLWU_PE3_WUPE9_MASK) #define LLWU_PE3_WUPE10_MASK (0x30U) #define LLWU_PE3_WUPE10_SHIFT (4U) +/*! WUPE10 - Wakeup Pin Enable For LLWU_P10 + * 0b00..External input pin disabled as wakeup input + * 0b01..External input pin enabled with rising edge detection + * 0b10..External input pin enabled with falling edge detection + * 0b11..External input pin enabled with any change detection + */ #define LLWU_PE3_WUPE10(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE3_WUPE10_SHIFT)) & LLWU_PE3_WUPE10_MASK) #define LLWU_PE3_WUPE11_MASK (0xC0U) #define LLWU_PE3_WUPE11_SHIFT (6U) +/*! WUPE11 - Wakeup Pin Enable For LLWU_P11 + * 0b00..External input pin disabled as wakeup input + * 0b01..External input pin enabled with rising edge detection + * 0b10..External input pin enabled with falling edge detection + * 0b11..External input pin enabled with any change detection + */ #define LLWU_PE3_WUPE11(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE3_WUPE11_SHIFT)) & LLWU_PE3_WUPE11_MASK) +/*! @} */ /*! @name PE4 - LLWU Pin Enable 4 register */ +/*! @{ */ #define LLWU_PE4_WUPE12_MASK (0x3U) #define LLWU_PE4_WUPE12_SHIFT (0U) +/*! WUPE12 - Wakeup Pin Enable For LLWU_P12 + * 0b00..External input pin disabled as wakeup input + * 0b01..External input pin enabled with rising edge detection + * 0b10..External input pin enabled with falling edge detection + * 0b11..External input pin enabled with any change detection + */ #define LLWU_PE4_WUPE12(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE4_WUPE12_SHIFT)) & LLWU_PE4_WUPE12_MASK) #define LLWU_PE4_WUPE13_MASK (0xCU) #define LLWU_PE4_WUPE13_SHIFT (2U) +/*! WUPE13 - Wakeup Pin Enable For LLWU_P13 + * 0b00..External input pin disabled as wakeup input + * 0b01..External input pin enabled with rising edge detection + * 0b10..External input pin enabled with falling edge detection + * 0b11..External input pin enabled with any change detection + */ #define LLWU_PE4_WUPE13(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE4_WUPE13_SHIFT)) & LLWU_PE4_WUPE13_MASK) #define LLWU_PE4_WUPE14_MASK (0x30U) #define LLWU_PE4_WUPE14_SHIFT (4U) +/*! WUPE14 - Wakeup Pin Enable For LLWU_P14 + * 0b00..External input pin disabled as wakeup input + * 0b01..External input pin enabled with rising edge detection + * 0b10..External input pin enabled with falling edge detection + * 0b11..External input pin enabled with any change detection + */ #define LLWU_PE4_WUPE14(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE4_WUPE14_SHIFT)) & LLWU_PE4_WUPE14_MASK) #define LLWU_PE4_WUPE15_MASK (0xC0U) #define LLWU_PE4_WUPE15_SHIFT (6U) +/*! WUPE15 - Wakeup Pin Enable For LLWU_P15 + * 0b00..External input pin disabled as wakeup input + * 0b01..External input pin enabled with rising edge detection + * 0b10..External input pin enabled with falling edge detection + * 0b11..External input pin enabled with any change detection + */ #define LLWU_PE4_WUPE15(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE4_WUPE15_SHIFT)) & LLWU_PE4_WUPE15_MASK) +/*! @} */ /*! @name ME - LLWU Module Enable register */ +/*! @{ */ #define LLWU_ME_WUME0_MASK (0x1U) #define LLWU_ME_WUME0_SHIFT (0U) +/*! WUME0 - Wakeup Module Enable For Module 0 + * 0b0..Internal module flag not used as wakeup source + * 0b1..Internal module flag used as wakeup source + */ #define LLWU_ME_WUME0(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME0_SHIFT)) & LLWU_ME_WUME0_MASK) #define LLWU_ME_WUME1_MASK (0x2U) #define LLWU_ME_WUME1_SHIFT (1U) +/*! WUME1 - Wakeup Module Enable for Module 1 + * 0b0..Internal module flag not used as wakeup source + * 0b1..Internal module flag used as wakeup source + */ #define LLWU_ME_WUME1(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME1_SHIFT)) & LLWU_ME_WUME1_MASK) #define LLWU_ME_WUME2_MASK (0x4U) #define LLWU_ME_WUME2_SHIFT (2U) +/*! WUME2 - Wakeup Module Enable For Module 2 + * 0b0..Internal module flag not used as wakeup source + * 0b1..Internal module flag used as wakeup source + */ #define LLWU_ME_WUME2(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME2_SHIFT)) & LLWU_ME_WUME2_MASK) #define LLWU_ME_WUME3_MASK (0x8U) #define LLWU_ME_WUME3_SHIFT (3U) +/*! WUME3 - Wakeup Module Enable For Module 3 + * 0b0..Internal module flag not used as wakeup source + * 0b1..Internal module flag used as wakeup source + */ #define LLWU_ME_WUME3(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME3_SHIFT)) & LLWU_ME_WUME3_MASK) #define LLWU_ME_WUME4_MASK (0x10U) #define LLWU_ME_WUME4_SHIFT (4U) +/*! WUME4 - Wakeup Module Enable For Module 4 + * 0b0..Internal module flag not used as wakeup source + * 0b1..Internal module flag used as wakeup source + */ #define LLWU_ME_WUME4(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME4_SHIFT)) & LLWU_ME_WUME4_MASK) #define LLWU_ME_WUME5_MASK (0x20U) #define LLWU_ME_WUME5_SHIFT (5U) +/*! WUME5 - Wakeup Module Enable For Module 5 + * 0b0..Internal module flag not used as wakeup source + * 0b1..Internal module flag used as wakeup source + */ #define LLWU_ME_WUME5(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME5_SHIFT)) & LLWU_ME_WUME5_MASK) #define LLWU_ME_WUME6_MASK (0x40U) #define LLWU_ME_WUME6_SHIFT (6U) +/*! WUME6 - Wakeup Module Enable For Module 6 + * 0b0..Internal module flag not used as wakeup source + * 0b1..Internal module flag used as wakeup source + */ #define LLWU_ME_WUME6(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME6_SHIFT)) & LLWU_ME_WUME6_MASK) #define LLWU_ME_WUME7_MASK (0x80U) #define LLWU_ME_WUME7_SHIFT (7U) +/*! WUME7 - Wakeup Module Enable For Module 7 + * 0b0..Internal module flag not used as wakeup source + * 0b1..Internal module flag used as wakeup source + */ #define LLWU_ME_WUME7(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME7_SHIFT)) & LLWU_ME_WUME7_MASK) +/*! @} */ /*! @name F1 - LLWU Flag 1 register */ +/*! @{ */ #define LLWU_F1_WUF0_MASK (0x1U) #define LLWU_F1_WUF0_SHIFT (0U) +/*! WUF0 - Wakeup Flag For LLWU_P0 + * 0b0..LLWU_P0 input was not a wakeup source + * 0b1..LLWU_P0 input was a wakeup source + */ #define LLWU_F1_WUF0(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF0_SHIFT)) & LLWU_F1_WUF0_MASK) #define LLWU_F1_WUF1_MASK (0x2U) #define LLWU_F1_WUF1_SHIFT (1U) +/*! WUF1 - Wakeup Flag For LLWU_P1 + * 0b0..LLWU_P1 input was not a wakeup source + * 0b1..LLWU_P1 input was a wakeup source + */ #define LLWU_F1_WUF1(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF1_SHIFT)) & LLWU_F1_WUF1_MASK) #define LLWU_F1_WUF2_MASK (0x4U) #define LLWU_F1_WUF2_SHIFT (2U) +/*! WUF2 - Wakeup Flag For LLWU_P2 + * 0b0..LLWU_P2 input was not a wakeup source + * 0b1..LLWU_P2 input was a wakeup source + */ #define LLWU_F1_WUF2(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF2_SHIFT)) & LLWU_F1_WUF2_MASK) #define LLWU_F1_WUF3_MASK (0x8U) #define LLWU_F1_WUF3_SHIFT (3U) +/*! WUF3 - Wakeup Flag For LLWU_P3 + * 0b0..LLWU_P3 input was not a wake-up source + * 0b1..LLWU_P3 input was a wake-up source + */ #define LLWU_F1_WUF3(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF3_SHIFT)) & LLWU_F1_WUF3_MASK) #define LLWU_F1_WUF4_MASK (0x10U) #define LLWU_F1_WUF4_SHIFT (4U) +/*! WUF4 - Wakeup Flag For LLWU_P4 + * 0b0..LLWU_P4 input was not a wakeup source + * 0b1..LLWU_P4 input was a wakeup source + */ #define LLWU_F1_WUF4(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF4_SHIFT)) & LLWU_F1_WUF4_MASK) #define LLWU_F1_WUF5_MASK (0x20U) #define LLWU_F1_WUF5_SHIFT (5U) +/*! WUF5 - Wakeup Flag For LLWU_P5 + * 0b0..LLWU_P5 input was not a wakeup source + * 0b1..LLWU_P5 input was a wakeup source + */ #define LLWU_F1_WUF5(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF5_SHIFT)) & LLWU_F1_WUF5_MASK) #define LLWU_F1_WUF6_MASK (0x40U) #define LLWU_F1_WUF6_SHIFT (6U) +/*! WUF6 - Wakeup Flag For LLWU_P6 + * 0b0..LLWU_P6 input was not a wakeup source + * 0b1..LLWU_P6 input was a wakeup source + */ #define LLWU_F1_WUF6(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF6_SHIFT)) & LLWU_F1_WUF6_MASK) #define LLWU_F1_WUF7_MASK (0x80U) #define LLWU_F1_WUF7_SHIFT (7U) +/*! WUF7 - Wakeup Flag For LLWU_P7 + * 0b0..LLWU_P7 input was not a wakeup source + * 0b1..LLWU_P7 input was a wakeup source + */ #define LLWU_F1_WUF7(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF7_SHIFT)) & LLWU_F1_WUF7_MASK) +/*! @} */ /*! @name F2 - LLWU Flag 2 register */ +/*! @{ */ #define LLWU_F2_WUF8_MASK (0x1U) #define LLWU_F2_WUF8_SHIFT (0U) +/*! WUF8 - Wakeup Flag For LLWU_P8 + * 0b0..LLWU_P8 input was not a wakeup source + * 0b1..LLWU_P8 input was a wakeup source + */ #define LLWU_F2_WUF8(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF8_SHIFT)) & LLWU_F2_WUF8_MASK) #define LLWU_F2_WUF9_MASK (0x2U) #define LLWU_F2_WUF9_SHIFT (1U) +/*! WUF9 - Wakeup Flag For LLWU_P9 + * 0b0..LLWU_P9 input was not a wakeup source + * 0b1..LLWU_P9 input was a wakeup source + */ #define LLWU_F2_WUF9(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF9_SHIFT)) & LLWU_F2_WUF9_MASK) #define LLWU_F2_WUF10_MASK (0x4U) #define LLWU_F2_WUF10_SHIFT (2U) +/*! WUF10 - Wakeup Flag For LLWU_P10 + * 0b0..LLWU_P10 input was not a wakeup source + * 0b1..LLWU_P10 input was a wakeup source + */ #define LLWU_F2_WUF10(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF10_SHIFT)) & LLWU_F2_WUF10_MASK) #define LLWU_F2_WUF11_MASK (0x8U) #define LLWU_F2_WUF11_SHIFT (3U) +/*! WUF11 - Wakeup Flag For LLWU_P11 + * 0b0..LLWU_P11 input was not a wakeup source + * 0b1..LLWU_P11 input was a wakeup source + */ #define LLWU_F2_WUF11(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF11_SHIFT)) & LLWU_F2_WUF11_MASK) #define LLWU_F2_WUF12_MASK (0x10U) #define LLWU_F2_WUF12_SHIFT (4U) +/*! WUF12 - Wakeup Flag For LLWU_P12 + * 0b0..LLWU_P12 input was not a wakeup source + * 0b1..LLWU_P12 input was a wakeup source + */ #define LLWU_F2_WUF12(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF12_SHIFT)) & LLWU_F2_WUF12_MASK) #define LLWU_F2_WUF13_MASK (0x20U) #define LLWU_F2_WUF13_SHIFT (5U) +/*! WUF13 - Wakeup Flag For LLWU_P13 + * 0b0..LLWU_P13 input was not a wakeup source + * 0b1..LLWU_P13 input was a wakeup source + */ #define LLWU_F2_WUF13(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF13_SHIFT)) & LLWU_F2_WUF13_MASK) #define LLWU_F2_WUF14_MASK (0x40U) #define LLWU_F2_WUF14_SHIFT (6U) +/*! WUF14 - Wakeup Flag For LLWU_P14 + * 0b0..LLWU_P14 input was not a wakeup source + * 0b1..LLWU_P14 input was a wakeup source + */ #define LLWU_F2_WUF14(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF14_SHIFT)) & LLWU_F2_WUF14_MASK) #define LLWU_F2_WUF15_MASK (0x80U) #define LLWU_F2_WUF15_SHIFT (7U) +/*! WUF15 - Wakeup Flag For LLWU_P15 + * 0b0..LLWU_P15 input was not a wakeup source + * 0b1..LLWU_P15 input was a wakeup source + */ #define LLWU_F2_WUF15(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF15_SHIFT)) & LLWU_F2_WUF15_MASK) +/*! @} */ /*! @name F3 - LLWU Flag 3 register */ +/*! @{ */ #define LLWU_F3_MWUF0_MASK (0x1U) #define LLWU_F3_MWUF0_SHIFT (0U) +/*! MWUF0 - Wakeup flag For module 0 + * 0b0..Module 0 input was not a wakeup source + * 0b1..Module 0 input was a wakeup source + */ #define LLWU_F3_MWUF0(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF0_SHIFT)) & LLWU_F3_MWUF0_MASK) #define LLWU_F3_MWUF1_MASK (0x2U) #define LLWU_F3_MWUF1_SHIFT (1U) +/*! MWUF1 - Wakeup flag For module 1 + * 0b0..Module 1 input was not a wakeup source + * 0b1..Module 1 input was a wakeup source + */ #define LLWU_F3_MWUF1(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF1_SHIFT)) & LLWU_F3_MWUF1_MASK) #define LLWU_F3_MWUF2_MASK (0x4U) #define LLWU_F3_MWUF2_SHIFT (2U) +/*! MWUF2 - Wakeup flag For module 2 + * 0b0..Module 2 input was not a wakeup source + * 0b1..Module 2 input was a wakeup source + */ #define LLWU_F3_MWUF2(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF2_SHIFT)) & LLWU_F3_MWUF2_MASK) #define LLWU_F3_MWUF3_MASK (0x8U) #define LLWU_F3_MWUF3_SHIFT (3U) +/*! MWUF3 - Wakeup flag For module 3 + * 0b0..Module 3 input was not a wakeup source + * 0b1..Module 3 input was a wakeup source + */ #define LLWU_F3_MWUF3(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF3_SHIFT)) & LLWU_F3_MWUF3_MASK) #define LLWU_F3_MWUF4_MASK (0x10U) #define LLWU_F3_MWUF4_SHIFT (4U) +/*! MWUF4 - Wakeup flag For module 4 + * 0b0..Module 4 input was not a wakeup source + * 0b1..Module 4 input was a wakeup source + */ #define LLWU_F3_MWUF4(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF4_SHIFT)) & LLWU_F3_MWUF4_MASK) #define LLWU_F3_MWUF5_MASK (0x20U) #define LLWU_F3_MWUF5_SHIFT (5U) +/*! MWUF5 - Wakeup flag For module 5 + * 0b0..Module 5 input was not a wakeup source + * 0b1..Module 5 input was a wakeup source + */ #define LLWU_F3_MWUF5(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF5_SHIFT)) & LLWU_F3_MWUF5_MASK) #define LLWU_F3_MWUF6_MASK (0x40U) #define LLWU_F3_MWUF6_SHIFT (6U) +/*! MWUF6 - Wakeup flag For module 6 + * 0b0..Module 6 input was not a wakeup source + * 0b1..Module 6 input was a wakeup source + */ #define LLWU_F3_MWUF6(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF6_SHIFT)) & LLWU_F3_MWUF6_MASK) #define LLWU_F3_MWUF7_MASK (0x80U) #define LLWU_F3_MWUF7_SHIFT (7U) +/*! MWUF7 - Wakeup flag For module 7 + * 0b0..Module 7 input was not a wakeup source + * 0b1..Module 7 input was a wakeup source + */ #define LLWU_F3_MWUF7(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF7_SHIFT)) & LLWU_F3_MWUF7_MASK) +/*! @} */ /*! @name FILT1 - LLWU Pin Filter 1 register */ +/*! @{ */ #define LLWU_FILT1_FILTSEL_MASK (0xFU) #define LLWU_FILT1_FILTSEL_SHIFT (0U) +/*! FILTSEL - Filter Pin Select + * 0b0000..Select LLWU_P0 for filter + * 0b1111..Select LLWU_P15 for filter + */ #define LLWU_FILT1_FILTSEL(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT1_FILTSEL_SHIFT)) & LLWU_FILT1_FILTSEL_MASK) #define LLWU_FILT1_FILTE_MASK (0x60U) #define LLWU_FILT1_FILTE_SHIFT (5U) +/*! FILTE - Digital Filter On External Pin + * 0b00..Filter disabled + * 0b01..Filter posedge detect enabled + * 0b10..Filter negedge detect enabled + * 0b11..Filter any edge detect enabled + */ #define LLWU_FILT1_FILTE(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT1_FILTE_SHIFT)) & LLWU_FILT1_FILTE_MASK) #define LLWU_FILT1_FILTF_MASK (0x80U) #define LLWU_FILT1_FILTF_SHIFT (7U) +/*! FILTF - Filter Detect Flag + * 0b0..Pin Filter 1 was not a wakeup source + * 0b1..Pin Filter 1 was a wakeup source + */ #define LLWU_FILT1_FILTF(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT1_FILTF_SHIFT)) & LLWU_FILT1_FILTF_MASK) +/*! @} */ /*! @name FILT2 - LLWU Pin Filter 2 register */ +/*! @{ */ #define LLWU_FILT2_FILTSEL_MASK (0xFU) #define LLWU_FILT2_FILTSEL_SHIFT (0U) +/*! FILTSEL - Filter Pin Select + * 0b0000..Select LLWU_P0 for filter + * 0b1111..Select LLWU_P15 for filter + */ #define LLWU_FILT2_FILTSEL(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT2_FILTSEL_SHIFT)) & LLWU_FILT2_FILTSEL_MASK) #define LLWU_FILT2_FILTE_MASK (0x60U) #define LLWU_FILT2_FILTE_SHIFT (5U) +/*! FILTE - Digital Filter On External Pin + * 0b00..Filter disabled + * 0b01..Filter posedge detect enabled + * 0b10..Filter negedge detect enabled + * 0b11..Filter any edge detect enabled + */ #define LLWU_FILT2_FILTE(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT2_FILTE_SHIFT)) & LLWU_FILT2_FILTE_MASK) #define LLWU_FILT2_FILTF_MASK (0x80U) #define LLWU_FILT2_FILTF_SHIFT (7U) +/*! FILTF - Filter Detect Flag + * 0b0..Pin Filter 2 was not a wakeup source + * 0b1..Pin Filter 2 was a wakeup source + */ #define LLWU_FILT2_FILTF(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT2_FILTF_SHIFT)) & LLWU_FILT2_FILTF_MASK) +/*! @} */ /*! @name RST - LLWU Reset Enable register */ +/*! @{ */ #define LLWU_RST_RSTFILT_MASK (0x1U) #define LLWU_RST_RSTFILT_SHIFT (0U) +/*! RSTFILT - Digital Filter On RESET Pin + * 0b0..Filter not enabled + * 0b1..Filter enabled + */ #define LLWU_RST_RSTFILT(x) (((uint8_t)(((uint8_t)(x)) << LLWU_RST_RSTFILT_SHIFT)) & LLWU_RST_RSTFILT_MASK) #define LLWU_RST_LLRSTE_MASK (0x2U) #define LLWU_RST_LLRSTE_SHIFT (1U) +/*! LLRSTE - Low-Leakage Mode RESET Enable + * 0b0..RESET pin not enabled as a leakage mode exit source + * 0b1..RESET pin enabled as a low leakage mode exit source + */ #define LLWU_RST_LLRSTE(x) (((uint8_t)(((uint8_t)(x)) << LLWU_RST_LLRSTE_SHIFT)) & LLWU_RST_LLRSTE_MASK) +/*! @} */ /*! @@ -7841,48 +13805,114 @@ typedef struct { */ /*! @name CSR - Low Power Timer Control Status Register */ +/*! @{ */ #define LPTMR_CSR_TEN_MASK (0x1U) #define LPTMR_CSR_TEN_SHIFT (0U) +/*! TEN - Timer Enable + * 0b0..LPTMR is disabled and internal logic is reset. + * 0b1..LPTMR is enabled. + */ #define LPTMR_CSR_TEN(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TEN_SHIFT)) & LPTMR_CSR_TEN_MASK) #define LPTMR_CSR_TMS_MASK (0x2U) #define LPTMR_CSR_TMS_SHIFT (1U) +/*! TMS - Timer Mode Select + * 0b0..Time Counter mode. + * 0b1..Pulse Counter mode. + */ #define LPTMR_CSR_TMS(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TMS_SHIFT)) & LPTMR_CSR_TMS_MASK) #define LPTMR_CSR_TFC_MASK (0x4U) #define LPTMR_CSR_TFC_SHIFT (2U) +/*! TFC - Timer Free-Running Counter + * 0b0..CNR is reset whenever TCF is set. + * 0b1..CNR is reset on overflow. + */ #define LPTMR_CSR_TFC(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TFC_SHIFT)) & LPTMR_CSR_TFC_MASK) #define LPTMR_CSR_TPP_MASK (0x8U) #define LPTMR_CSR_TPP_SHIFT (3U) +/*! TPP - Timer Pin Polarity + * 0b0..Pulse Counter input source is active-high, and the CNR will increment on the rising-edge. + * 0b1..Pulse Counter input source is active-low, and the CNR will increment on the falling-edge. + */ #define LPTMR_CSR_TPP(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TPP_SHIFT)) & LPTMR_CSR_TPP_MASK) #define LPTMR_CSR_TPS_MASK (0x30U) #define LPTMR_CSR_TPS_SHIFT (4U) +/*! TPS - Timer Pin Select + * 0b00..Pulse counter input 0 is selected. + * 0b01..Pulse counter input 1 is selected. + * 0b10..Pulse counter input 2 is selected. + * 0b11..Pulse counter input 3 is selected. + */ #define LPTMR_CSR_TPS(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TPS_SHIFT)) & LPTMR_CSR_TPS_MASK) #define LPTMR_CSR_TIE_MASK (0x40U) #define LPTMR_CSR_TIE_SHIFT (6U) +/*! TIE - Timer Interrupt Enable + * 0b0..Timer interrupt disabled. + * 0b1..Timer interrupt enabled. + */ #define LPTMR_CSR_TIE(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TIE_SHIFT)) & LPTMR_CSR_TIE_MASK) #define LPTMR_CSR_TCF_MASK (0x80U) #define LPTMR_CSR_TCF_SHIFT (7U) +/*! TCF - Timer Compare Flag + * 0b0..The value of CNR is not equal to CMR and increments. + * 0b1..The value of CNR is equal to CMR and increments. + */ #define LPTMR_CSR_TCF(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TCF_SHIFT)) & LPTMR_CSR_TCF_MASK) +/*! @} */ /*! @name PSR - Low Power Timer Prescale Register */ +/*! @{ */ #define LPTMR_PSR_PCS_MASK (0x3U) #define LPTMR_PSR_PCS_SHIFT (0U) +/*! PCS - Prescaler Clock Select + * 0b00..Prescaler/glitch filter clock 0 selected. + * 0b01..Prescaler/glitch filter clock 1 selected. + * 0b10..Prescaler/glitch filter clock 2 selected. + * 0b11..Prescaler/glitch filter clock 3 selected. + */ #define LPTMR_PSR_PCS(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PCS_SHIFT)) & LPTMR_PSR_PCS_MASK) #define LPTMR_PSR_PBYP_MASK (0x4U) #define LPTMR_PSR_PBYP_SHIFT (2U) +/*! PBYP - Prescaler Bypass + * 0b0..Prescaler/glitch filter is enabled. + * 0b1..Prescaler/glitch filter is bypassed. + */ #define LPTMR_PSR_PBYP(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PBYP_SHIFT)) & LPTMR_PSR_PBYP_MASK) #define LPTMR_PSR_PRESCALE_MASK (0x78U) #define LPTMR_PSR_PRESCALE_SHIFT (3U) +/*! PRESCALE - Prescale Value + * 0b0000..Prescaler divides the prescaler clock by 2; glitch filter does not support this configuration. + * 0b0001..Prescaler divides the prescaler clock by 4; glitch filter recognizes change on input pin after 2 rising clock edges. + * 0b0010..Prescaler divides the prescaler clock by 8; glitch filter recognizes change on input pin after 4 rising clock edges. + * 0b0011..Prescaler divides the prescaler clock by 16; glitch filter recognizes change on input pin after 8 rising clock edges. + * 0b0100..Prescaler divides the prescaler clock by 32; glitch filter recognizes change on input pin after 16 rising clock edges. + * 0b0101..Prescaler divides the prescaler clock by 64; glitch filter recognizes change on input pin after 32 rising clock edges. + * 0b0110..Prescaler divides the prescaler clock by 128; glitch filter recognizes change on input pin after 64 rising clock edges. + * 0b0111..Prescaler divides the prescaler clock by 256; glitch filter recognizes change on input pin after 128 rising clock edges. + * 0b1000..Prescaler divides the prescaler clock by 512; glitch filter recognizes change on input pin after 256 rising clock edges. + * 0b1001..Prescaler divides the prescaler clock by 1024; glitch filter recognizes change on input pin after 512 rising clock edges. + * 0b1010..Prescaler divides the prescaler clock by 2048; glitch filter recognizes change on input pin after 1024 rising clock edges. + * 0b1011..Prescaler divides the prescaler clock by 4096; glitch filter recognizes change on input pin after 2048 rising clock edges. + * 0b1100..Prescaler divides the prescaler clock by 8192; glitch filter recognizes change on input pin after 4096 rising clock edges. + * 0b1101..Prescaler divides the prescaler clock by 16,384; glitch filter recognizes change on input pin after 8192 rising clock edges. + * 0b1110..Prescaler divides the prescaler clock by 32,768; glitch filter recognizes change on input pin after 16,384 rising clock edges. + * 0b1111..Prescaler divides the prescaler clock by 65,536; glitch filter recognizes change on input pin after 32,768 rising clock edges. + */ #define LPTMR_PSR_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PRESCALE_SHIFT)) & LPTMR_PSR_PRESCALE_MASK) +/*! @} */ /*! @name CMR - Low Power Timer Compare Register */ +/*! @{ */ #define LPTMR_CMR_COMPARE_MASK (0xFFFFU) #define LPTMR_CMR_COMPARE_SHIFT (0U) #define LPTMR_CMR_COMPARE(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CMR_COMPARE_SHIFT)) & LPTMR_CMR_COMPARE_MASK) +/*! @} */ /*! @name CNR - Low Power Timer Counter Register */ +/*! @{ */ #define LPTMR_CNR_COUNTER_MASK (0xFFFFU) #define LPTMR_CNR_COUNTER_SHIFT (0U) #define LPTMR_CNR_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CNR_COUNTER_SHIFT)) & LPTMR_CNR_COUNTER_MASK) +/*! @} */ /*! @@ -7944,51 +13974,111 @@ typedef struct { */ /*! @name C1 - MCG Control 1 Register */ +/*! @{ */ #define MCG_C1_IREFSTEN_MASK (0x1U) #define MCG_C1_IREFSTEN_SHIFT (0U) +/*! IREFSTEN - Internal Reference Stop Enable + * 0b0..Internal reference clock is disabled in Stop mode. + * 0b1..Internal reference clock is enabled in Stop mode if IRCLKEN is set or if MCG is in FEI, FBI, or BLPI modes before entering Stop mode. + */ #define MCG_C1_IREFSTEN(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_IREFSTEN_SHIFT)) & MCG_C1_IREFSTEN_MASK) #define MCG_C1_IRCLKEN_MASK (0x2U) #define MCG_C1_IRCLKEN_SHIFT (1U) +/*! IRCLKEN - Internal Reference Clock Enable + * 0b0..MCGIRCLK inactive. + * 0b1..MCGIRCLK active. + */ #define MCG_C1_IRCLKEN(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_IRCLKEN_SHIFT)) & MCG_C1_IRCLKEN_MASK) #define MCG_C1_IREFS_MASK (0x4U) #define MCG_C1_IREFS_SHIFT (2U) +/*! IREFS - Internal Reference Select + * 0b0..External reference clock is selected. + * 0b1..The slow internal reference clock is selected. + */ #define MCG_C1_IREFS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_IREFS_SHIFT)) & MCG_C1_IREFS_MASK) #define MCG_C1_FRDIV_MASK (0x38U) #define MCG_C1_FRDIV_SHIFT (3U) +/*! FRDIV - FLL External Reference Divider + * 0b000..If RANGE = 0 or OSCSEL=1 , Divide Factor is 1; for all other RANGE values, Divide Factor is 32. + * 0b001..If RANGE = 0 or OSCSEL=1 , Divide Factor is 2; for all other RANGE values, Divide Factor is 64. + * 0b010..If RANGE = 0 or OSCSEL=1 , Divide Factor is 4; for all other RANGE values, Divide Factor is 128. + * 0b011..If RANGE = 0 or OSCSEL=1 , Divide Factor is 8; for all other RANGE values, Divide Factor is 256. + * 0b100..If RANGE = 0 or OSCSEL=1 , Divide Factor is 16; for all other RANGE values, Divide Factor is 512. + * 0b101..If RANGE = 0 or OSCSEL=1 , Divide Factor is 32; for all other RANGE values, Divide Factor is 1024. + * 0b110..If RANGE = 0 or OSCSEL=1 , Divide Factor is 64; for all other RANGE values, Divide Factor is 1280 . + * 0b111..If RANGE = 0 or OSCSEL=1 , Divide Factor is 128; for all other RANGE values, Divide Factor is 1536 . + */ #define MCG_C1_FRDIV(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_FRDIV_SHIFT)) & MCG_C1_FRDIV_MASK) #define MCG_C1_CLKS_MASK (0xC0U) #define MCG_C1_CLKS_SHIFT (6U) +/*! CLKS - Clock Source Select + * 0b00..Encoding 0 - Output of FLL or PLL is selected (depends on PLLS control bit). + * 0b01..Encoding 1 - Internal reference clock is selected. + * 0b10..Encoding 2 - External reference clock is selected. + * 0b11..Encoding 3 - Reserved. + */ #define MCG_C1_CLKS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_CLKS_SHIFT)) & MCG_C1_CLKS_MASK) +/*! @} */ /*! @name C2 - MCG Control 2 Register */ +/*! @{ */ #define MCG_C2_IRCS_MASK (0x1U) #define MCG_C2_IRCS_SHIFT (0U) +/*! IRCS - Internal Reference Clock Select + * 0b0..Slow internal reference clock selected. + * 0b1..Fast internal reference clock selected. + */ #define MCG_C2_IRCS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_IRCS_SHIFT)) & MCG_C2_IRCS_MASK) #define MCG_C2_LP_MASK (0x2U) #define MCG_C2_LP_SHIFT (1U) +/*! LP - Low Power Select + * 0b0..FLL or PLL is not disabled in bypass modes. + * 0b1..FLL or PLL is disabled in bypass modes (lower power) + */ #define MCG_C2_LP(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_LP_SHIFT)) & MCG_C2_LP_MASK) #define MCG_C2_EREFS_MASK (0x4U) #define MCG_C2_EREFS_SHIFT (2U) +/*! EREFS - External Reference Select + * 0b0..External reference clock requested. + * 0b1..Oscillator requested. + */ #define MCG_C2_EREFS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_EREFS_SHIFT)) & MCG_C2_EREFS_MASK) #define MCG_C2_HGO_MASK (0x8U) #define MCG_C2_HGO_SHIFT (3U) +/*! HGO - High Gain Oscillator Select + * 0b0..Configure crystal oscillator for low-power operation. + * 0b1..Configure crystal oscillator for high-gain operation. + */ #define MCG_C2_HGO(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_HGO_SHIFT)) & MCG_C2_HGO_MASK) #define MCG_C2_RANGE_MASK (0x30U) #define MCG_C2_RANGE_SHIFT (4U) +/*! RANGE - Frequency Range Select + * 0b00..Encoding 0 - Low frequency range selected for the crystal oscillator . + * 0b01..Encoding 1 - High frequency range selected for the crystal oscillator . + * 0b1x..Encoding 2 - Very high frequency range selected for the crystal oscillator . + */ #define MCG_C2_RANGE(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_RANGE_SHIFT)) & MCG_C2_RANGE_MASK) #define MCG_C2_FCFTRIM_MASK (0x40U) #define MCG_C2_FCFTRIM_SHIFT (6U) #define MCG_C2_FCFTRIM(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_FCFTRIM_SHIFT)) & MCG_C2_FCFTRIM_MASK) #define MCG_C2_LOCRE0_MASK (0x80U) #define MCG_C2_LOCRE0_SHIFT (7U) +/*! LOCRE0 - Loss of Clock Reset Enable + * 0b0..Interrupt request is generated on a loss of OSC0 external reference clock. + * 0b1..Generate a reset request on a loss of OSC0 external reference clock. + */ #define MCG_C2_LOCRE0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_LOCRE0_SHIFT)) & MCG_C2_LOCRE0_MASK) +/*! @} */ /*! @name C3 - MCG Control 3 Register */ +/*! @{ */ #define MCG_C3_SCTRIM_MASK (0xFFU) #define MCG_C3_SCTRIM_SHIFT (0U) #define MCG_C3_SCTRIM(x) (((uint8_t)(((uint8_t)(x)) << MCG_C3_SCTRIM_SHIFT)) & MCG_C3_SCTRIM_MASK) +/*! @} */ /*! @name C4 - MCG Control 4 Register */ +/*! @{ */ #define MCG_C4_SCFTRIM_MASK (0x1U) #define MCG_C4_SCFTRIM_SHIFT (0U) #define MCG_C4_SCFTRIM(x) (((uint8_t)(((uint8_t)(x)) << MCG_C4_SCFTRIM_SHIFT)) & MCG_C4_SCFTRIM_MASK) @@ -7997,107 +14087,300 @@ typedef struct { #define MCG_C4_FCTRIM(x) (((uint8_t)(((uint8_t)(x)) << MCG_C4_FCTRIM_SHIFT)) & MCG_C4_FCTRIM_MASK) #define MCG_C4_DRST_DRS_MASK (0x60U) #define MCG_C4_DRST_DRS_SHIFT (5U) +/*! DRST_DRS - DCO Range Select + * 0b00..Encoding 0 - Low range (reset default). + * 0b01..Encoding 1 - Mid range. + * 0b10..Encoding 2 - Mid-high range. + * 0b11..Encoding 3 - High range. + */ #define MCG_C4_DRST_DRS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C4_DRST_DRS_SHIFT)) & MCG_C4_DRST_DRS_MASK) #define MCG_C4_DMX32_MASK (0x80U) #define MCG_C4_DMX32_SHIFT (7U) +/*! DMX32 - DCO Maximum Frequency with 32.768 kHz Reference + * 0b0..DCO has a default range of 25%. + * 0b1..DCO is fine-tuned for maximum frequency with 32.768 kHz reference. + */ #define MCG_C4_DMX32(x) (((uint8_t)(((uint8_t)(x)) << MCG_C4_DMX32_SHIFT)) & MCG_C4_DMX32_MASK) +/*! @} */ /*! @name C5 - MCG Control 5 Register */ +/*! @{ */ #define MCG_C5_PRDIV0_MASK (0x1FU) #define MCG_C5_PRDIV0_SHIFT (0U) +/*! PRDIV0 - PLL External Reference Divider + * 0b00000..Divide Factor is 1 + * 0b00001..Divide Factor is 2 + * 0b00010..Divide Factor is 3 + * 0b00011..Divide Factor is 4 + * 0b00100..Divide Factor is 5 + * 0b00101..Divide Factor is 6 + * 0b00110..Divide Factor is 7 + * 0b00111..Divide Factor is 8 + * 0b01000..Divide Factor is 9 + * 0b01001..Divide Factor is 10 + * 0b01010..Divide Factor is 11 + * 0b01011..Divide Factor is 12 + * 0b01100..Divide Factor is 13 + * 0b01101..Divide Factor is 14 + * 0b01110..Divide Factor is 15 + * 0b01111..Divide Factor is 16 + * 0b10000..Divide Factor is 17 + * 0b10001..Divide Factor is 18 + * 0b10010..Divide Factor is 19 + * 0b10011..Divide Factor is 20 + * 0b10100..Divide Factor is 21 + * 0b10101..Divide Factor is 22 + * 0b10110..Divide Factor is 23 + * 0b10111..Divide Factor is 24 + * 0b11000..Divide Factor is 25 + * 0b11001..Divide Factor is 26 + * 0b11010..Divide Factor is 27 + * 0b11011..Divide Factor is 28 + * 0b11100..Divide Factor is 29 + * 0b11101..Divide Factor is 30 + * 0b11110..Divide Factor is 31 + * 0b11111..Divide Factor is 32 + */ #define MCG_C5_PRDIV0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C5_PRDIV0_SHIFT)) & MCG_C5_PRDIV0_MASK) #define MCG_C5_PLLSTEN0_MASK (0x20U) #define MCG_C5_PLLSTEN0_SHIFT (5U) +/*! PLLSTEN0 - PLL Stop Enable + * 0b0..MCGPLLCLK is disabled in any of the Stop modes. + * 0b1..MCGPLLCLK is enabled if system is in Normal Stop mode. + */ #define MCG_C5_PLLSTEN0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C5_PLLSTEN0_SHIFT)) & MCG_C5_PLLSTEN0_MASK) #define MCG_C5_PLLCLKEN0_MASK (0x40U) #define MCG_C5_PLLCLKEN0_SHIFT (6U) +/*! PLLCLKEN0 - PLL Clock Enable + * 0b0..MCGPLLCLK is inactive. + * 0b1..MCGPLLCLK is active. + */ #define MCG_C5_PLLCLKEN0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C5_PLLCLKEN0_SHIFT)) & MCG_C5_PLLCLKEN0_MASK) +/*! @} */ /*! @name C6 - MCG Control 6 Register */ +/*! @{ */ #define MCG_C6_VDIV0_MASK (0x1FU) #define MCG_C6_VDIV0_SHIFT (0U) +/*! VDIV0 - VCO 0 Divider + * 0b00000..Multiply Factor is 24 + * 0b00001..Multiply Factor is 25 + * 0b00010..Multiply Factor is 26 + * 0b00011..Multiply Factor is 27 + * 0b00100..Multiply Factor is 28 + * 0b00101..Multiply Factor is 29 + * 0b00110..Multiply Factor is 30 + * 0b00111..Multiply Factor is 31 + * 0b01000..Multiply Factor is 32 + * 0b01001..Multiply Factor is 33 + * 0b01010..Multiply Factor is 34 + * 0b01011..Multiply Factor is 35 + * 0b01100..Multiply Factor is 36 + * 0b01101..Multiply Factor is 37 + * 0b01110..Multiply Factor is 38 + * 0b01111..Multiply Factor is 39 + * 0b10000..Multiply Factor is 40 + * 0b10001..Multiply Factor is 41 + * 0b10010..Multiply Factor is 42 + * 0b10011..Multiply Factor is 43 + * 0b10100..Multiply Factor is 44 + * 0b10101..Multiply Factor is 45 + * 0b10110..Multiply Factor is 46 + * 0b10111..Multiply Factor is 47 + * 0b11000..Multiply Factor is 48 + * 0b11001..Multiply Factor is 49 + * 0b11010..Multiply Factor is 50 + * 0b11011..Multiply Factor is 51 + * 0b11100..Multiply Factor is 52 + * 0b11101..Multiply Factor is 53 + * 0b11110..Multiply Factor is 54 + * 0b11111..Multiply Factor is 55 + */ #define MCG_C6_VDIV0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C6_VDIV0_SHIFT)) & MCG_C6_VDIV0_MASK) #define MCG_C6_CME0_MASK (0x20U) #define MCG_C6_CME0_SHIFT (5U) +/*! CME0 - Clock Monitor Enable + * 0b0..External clock monitor is disabled for OSC0. + * 0b1..External clock monitor is enabled for OSC0. + */ #define MCG_C6_CME0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C6_CME0_SHIFT)) & MCG_C6_CME0_MASK) #define MCG_C6_PLLS_MASK (0x40U) #define MCG_C6_PLLS_SHIFT (6U) +/*! PLLS - PLL Select + * 0b0..FLL is selected. + * 0b1..PLL is selected (PRDIV 0 need to be programmed to the correct divider to generate a PLL reference clock in the range of 2-4 MHz prior to setting the PLLS bit). + */ #define MCG_C6_PLLS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C6_PLLS_SHIFT)) & MCG_C6_PLLS_MASK) #define MCG_C6_LOLIE0_MASK (0x80U) #define MCG_C6_LOLIE0_SHIFT (7U) +/*! LOLIE0 - Loss of Lock Interrrupt Enable + * 0b0..No interrupt request is generated on loss of lock. + * 0b1..Generate an interrupt request on loss of lock. + */ #define MCG_C6_LOLIE0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C6_LOLIE0_SHIFT)) & MCG_C6_LOLIE0_MASK) +/*! @} */ /*! @name S - MCG Status Register */ +/*! @{ */ #define MCG_S_IRCST_MASK (0x1U) #define MCG_S_IRCST_SHIFT (0U) +/*! IRCST - Internal Reference Clock Status + * 0b0..Source of internal reference clock is the slow clock (32 kHz IRC). + * 0b1..Source of internal reference clock is the fast clock (4 MHz IRC). + */ #define MCG_S_IRCST(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_IRCST_SHIFT)) & MCG_S_IRCST_MASK) #define MCG_S_OSCINIT0_MASK (0x2U) #define MCG_S_OSCINIT0_SHIFT (1U) #define MCG_S_OSCINIT0(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_OSCINIT0_SHIFT)) & MCG_S_OSCINIT0_MASK) #define MCG_S_CLKST_MASK (0xCU) #define MCG_S_CLKST_SHIFT (2U) +/*! CLKST - Clock Mode Status + * 0b00..Encoding 0 - Output of the FLL is selected (reset default). + * 0b01..Encoding 1 - Internal reference clock is selected. + * 0b10..Encoding 2 - External reference clock is selected. + * 0b11..Encoding 3 - Output of the PLL is selected. + */ #define MCG_S_CLKST(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_CLKST_SHIFT)) & MCG_S_CLKST_MASK) #define MCG_S_IREFST_MASK (0x10U) #define MCG_S_IREFST_SHIFT (4U) +/*! IREFST - Internal Reference Status + * 0b0..Source of FLL reference clock is the external reference clock. + * 0b1..Source of FLL reference clock is the internal reference clock. + */ #define MCG_S_IREFST(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_IREFST_SHIFT)) & MCG_S_IREFST_MASK) #define MCG_S_PLLST_MASK (0x20U) #define MCG_S_PLLST_SHIFT (5U) +/*! PLLST - PLL Select Status + * 0b0..Source of PLLS clock is FLL clock. + * 0b1..Source of PLLS clock is PLL output clock. + */ #define MCG_S_PLLST(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_PLLST_SHIFT)) & MCG_S_PLLST_MASK) #define MCG_S_LOCK0_MASK (0x40U) #define MCG_S_LOCK0_SHIFT (6U) +/*! LOCK0 - Lock Status + * 0b0..PLL is currently unlocked. + * 0b1..PLL is currently locked. + */ #define MCG_S_LOCK0(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_LOCK0_SHIFT)) & MCG_S_LOCK0_MASK) #define MCG_S_LOLS0_MASK (0x80U) #define MCG_S_LOLS0_SHIFT (7U) +/*! LOLS0 - Loss of Lock Status + * 0b0..PLL has not lost lock since LOLS 0 was last cleared. + * 0b1..PLL has lost lock since LOLS 0 was last cleared. + */ #define MCG_S_LOLS0(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_LOLS0_SHIFT)) & MCG_S_LOLS0_MASK) +/*! @} */ /*! @name SC - MCG Status and Control Register */ +/*! @{ */ #define MCG_SC_LOCS0_MASK (0x1U) #define MCG_SC_LOCS0_SHIFT (0U) +/*! LOCS0 - OSC0 Loss of Clock Status + * 0b0..Loss of OSC0 has not occurred. + * 0b1..Loss of OSC0 has occurred. + */ #define MCG_SC_LOCS0(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_LOCS0_SHIFT)) & MCG_SC_LOCS0_MASK) #define MCG_SC_FCRDIV_MASK (0xEU) #define MCG_SC_FCRDIV_SHIFT (1U) +/*! FCRDIV - Fast Clock Internal Reference Divider + * 0b000..Divide Factor is 1 + * 0b001..Divide Factor is 2. + * 0b010..Divide Factor is 4. + * 0b011..Divide Factor is 8. + * 0b100..Divide Factor is 16 + * 0b101..Divide Factor is 32 + * 0b110..Divide Factor is 64 + * 0b111..Divide Factor is 128. + */ #define MCG_SC_FCRDIV(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_FCRDIV_SHIFT)) & MCG_SC_FCRDIV_MASK) #define MCG_SC_FLTPRSRV_MASK (0x10U) #define MCG_SC_FLTPRSRV_SHIFT (4U) +/*! FLTPRSRV - FLL Filter Preserve Enable + * 0b0..FLL filter and FLL frequency will reset on changes to currect clock mode. + * 0b1..Fll filter and FLL frequency retain their previous values during new clock mode change. + */ #define MCG_SC_FLTPRSRV(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_FLTPRSRV_SHIFT)) & MCG_SC_FLTPRSRV_MASK) #define MCG_SC_ATMF_MASK (0x20U) #define MCG_SC_ATMF_SHIFT (5U) +/*! ATMF - Automatic Trim Machine Fail Flag + * 0b0..Automatic Trim Machine completed normally. + * 0b1..Automatic Trim Machine failed. + */ #define MCG_SC_ATMF(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_ATMF_SHIFT)) & MCG_SC_ATMF_MASK) #define MCG_SC_ATMS_MASK (0x40U) #define MCG_SC_ATMS_SHIFT (6U) +/*! ATMS - Automatic Trim Machine Select + * 0b0..32 kHz Internal Reference Clock selected. + * 0b1..4 MHz Internal Reference Clock selected. + */ #define MCG_SC_ATMS(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_ATMS_SHIFT)) & MCG_SC_ATMS_MASK) #define MCG_SC_ATME_MASK (0x80U) #define MCG_SC_ATME_SHIFT (7U) +/*! ATME - Automatic Trim Machine Enable + * 0b0..Auto Trim Machine disabled. + * 0b1..Auto Trim Machine enabled. + */ #define MCG_SC_ATME(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_ATME_SHIFT)) & MCG_SC_ATME_MASK) +/*! @} */ /*! @name ATCVH - MCG Auto Trim Compare Value High Register */ +/*! @{ */ #define MCG_ATCVH_ATCVH_MASK (0xFFU) #define MCG_ATCVH_ATCVH_SHIFT (0U) #define MCG_ATCVH_ATCVH(x) (((uint8_t)(((uint8_t)(x)) << MCG_ATCVH_ATCVH_SHIFT)) & MCG_ATCVH_ATCVH_MASK) +/*! @} */ /*! @name ATCVL - MCG Auto Trim Compare Value Low Register */ +/*! @{ */ #define MCG_ATCVL_ATCVL_MASK (0xFFU) #define MCG_ATCVL_ATCVL_SHIFT (0U) #define MCG_ATCVL_ATCVL(x) (((uint8_t)(((uint8_t)(x)) << MCG_ATCVL_ATCVL_SHIFT)) & MCG_ATCVL_ATCVL_MASK) +/*! @} */ /*! @name C7 - MCG Control 7 Register */ +/*! @{ */ #define MCG_C7_OSCSEL_MASK (0x3U) #define MCG_C7_OSCSEL_SHIFT (0U) +/*! OSCSEL - MCG OSC Clock Select + * 0b00..Selects Oscillator (OSCCLK0). + * 0b01..Selects 32 kHz RTC Oscillator. + * 0b10..Selects Oscillator (OSCCLK1). + * 0b11..RESERVED + */ #define MCG_C7_OSCSEL(x) (((uint8_t)(((uint8_t)(x)) << MCG_C7_OSCSEL_SHIFT)) & MCG_C7_OSCSEL_MASK) +/*! @} */ /*! @name C8 - MCG Control 8 Register */ +/*! @{ */ #define MCG_C8_LOCS1_MASK (0x1U) #define MCG_C8_LOCS1_SHIFT (0U) +/*! LOCS1 - RTC Loss of Clock Status + * 0b0..Loss of RTC has not occur. + * 0b1..Loss of RTC has occur + */ #define MCG_C8_LOCS1(x) (((uint8_t)(((uint8_t)(x)) << MCG_C8_LOCS1_SHIFT)) & MCG_C8_LOCS1_MASK) #define MCG_C8_CME1_MASK (0x20U) #define MCG_C8_CME1_SHIFT (5U) +/*! CME1 - Clock Monitor Enable1 + * 0b0..External clock monitor is disabled for RTC clock. + * 0b1..External clock monitor is enabled for RTC clock. + */ #define MCG_C8_CME1(x) (((uint8_t)(((uint8_t)(x)) << MCG_C8_CME1_SHIFT)) & MCG_C8_CME1_MASK) #define MCG_C8_LOLRE_MASK (0x40U) #define MCG_C8_LOLRE_SHIFT (6U) +/*! LOLRE - PLL Loss of Lock Reset Enable + * 0b0..Interrupt request is generated on a PLL loss of lock indication. The PLL loss of lock interrupt enable bit must also be set to generate the interrupt request. + * 0b1..Generate a reset request on a PLL loss of lock indication. + */ #define MCG_C8_LOLRE(x) (((uint8_t)(((uint8_t)(x)) << MCG_C8_LOLRE_SHIFT)) & MCG_C8_LOLRE_MASK) #define MCG_C8_LOCRE1_MASK (0x80U) #define MCG_C8_LOCRE1_SHIFT (7U) +/*! LOCRE1 - Loss of Clock Reset Enable + * 0b0..Interrupt request is generated on a loss of RTC external reference clock. + * 0b1..Generate a reset request on a loss of RTC external reference clock + */ #define MCG_C8_LOCRE1(x) (((uint8_t)(((uint8_t)(x)) << MCG_C8_LOCRE1_SHIFT)) & MCG_C8_LOCRE1_MASK) +/*! @} */ /*! @@ -8153,107 +14436,225 @@ typedef struct { */ /*! @name PLASC - Crossbar Switch (AXBS) Slave Configuration */ +/*! @{ */ #define MCM_PLASC_ASC_MASK (0xFFU) #define MCM_PLASC_ASC_SHIFT (0U) +/*! ASC - Each bit in the ASC field indicates whether there is a corresponding connection to the crossbar switch's slave input port. + * 0b00000000..A bus slave connection to AXBS input port n is absent + * 0b00000001..A bus slave connection to AXBS input port n is present + */ #define MCM_PLASC_ASC(x) (((uint16_t)(((uint16_t)(x)) << MCM_PLASC_ASC_SHIFT)) & MCM_PLASC_ASC_MASK) +/*! @} */ /*! @name PLAMC - Crossbar Switch (AXBS) Master Configuration */ +/*! @{ */ #define MCM_PLAMC_AMC_MASK (0xFFU) #define MCM_PLAMC_AMC_SHIFT (0U) +/*! AMC - Each bit in the AMC field indicates whether there is a corresponding connection to the AXBS master input port. + * 0b00000000..A bus master connection to AXBS input port n is absent + * 0b00000001..A bus master connection to AXBS input port n is present + */ #define MCM_PLAMC_AMC(x) (((uint16_t)(((uint16_t)(x)) << MCM_PLAMC_AMC_SHIFT)) & MCM_PLAMC_AMC_MASK) +/*! @} */ /*! @name CR - Control Register */ +/*! @{ */ #define MCM_CR_SRAMUAP_MASK (0x3000000U) #define MCM_CR_SRAMUAP_SHIFT (24U) +/*! SRAMUAP - SRAM_U arbitration priority + * 0b00..Round robin + * 0b01..Special round robin (favors SRAM backoor accesses over the processor) + * 0b10..Fixed priority. Processor has highest, backdoor has lowest + * 0b11..Fixed priority. Backdoor has highest, processor has lowest + */ #define MCM_CR_SRAMUAP(x) (((uint32_t)(((uint32_t)(x)) << MCM_CR_SRAMUAP_SHIFT)) & MCM_CR_SRAMUAP_MASK) #define MCM_CR_SRAMUWP_MASK (0x4000000U) #define MCM_CR_SRAMUWP_SHIFT (26U) #define MCM_CR_SRAMUWP(x) (((uint32_t)(((uint32_t)(x)) << MCM_CR_SRAMUWP_SHIFT)) & MCM_CR_SRAMUWP_MASK) #define MCM_CR_SRAMLAP_MASK (0x30000000U) #define MCM_CR_SRAMLAP_SHIFT (28U) +/*! SRAMLAP - SRAM_L arbitration priority + * 0b00..Round robin + * 0b01..Special round robin (favors SRAM backoor accesses over the processor) + * 0b10..Fixed priority. Processor has highest, backdoor has lowest + * 0b11..Fixed priority. Backdoor has highest, processor has lowest + */ #define MCM_CR_SRAMLAP(x) (((uint32_t)(((uint32_t)(x)) << MCM_CR_SRAMLAP_SHIFT)) & MCM_CR_SRAMLAP_MASK) #define MCM_CR_SRAMLWP_MASK (0x40000000U) #define MCM_CR_SRAMLWP_SHIFT (30U) #define MCM_CR_SRAMLWP(x) (((uint32_t)(((uint32_t)(x)) << MCM_CR_SRAMLWP_SHIFT)) & MCM_CR_SRAMLWP_MASK) +/*! @} */ /*! @name ISCR - Interrupt Status Register */ +/*! @{ */ #define MCM_ISCR_IRQ_MASK (0x2U) #define MCM_ISCR_IRQ_SHIFT (1U) +/*! IRQ - Normal Interrupt Pending + * 0b0..No pending interrupt + * 0b1..Due to the ETB counter expiring, a normal interrupt is pending + */ #define MCM_ISCR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_IRQ_SHIFT)) & MCM_ISCR_IRQ_MASK) #define MCM_ISCR_NMI_MASK (0x4U) #define MCM_ISCR_NMI_SHIFT (2U) +/*! NMI - Non-maskable Interrupt Pending + * 0b0..No pending NMI + * 0b1..Due to the ETB counter expiring, an NMI is pending + */ #define MCM_ISCR_NMI(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_NMI_SHIFT)) & MCM_ISCR_NMI_MASK) #define MCM_ISCR_DHREQ_MASK (0x8U) #define MCM_ISCR_DHREQ_SHIFT (3U) +/*! DHREQ - Debug Halt Request Indicator + * 0b0..No debug halt request + * 0b1..Debug halt request initiated + */ #define MCM_ISCR_DHREQ(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_DHREQ_SHIFT)) & MCM_ISCR_DHREQ_MASK) #define MCM_ISCR_FIOC_MASK (0x100U) #define MCM_ISCR_FIOC_SHIFT (8U) +/*! FIOC - FPU invalid operation interrupt status + * 0b0..No interrupt + * 0b1..Interrupt occurred + */ #define MCM_ISCR_FIOC(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIOC_SHIFT)) & MCM_ISCR_FIOC_MASK) #define MCM_ISCR_FDZC_MASK (0x200U) #define MCM_ISCR_FDZC_SHIFT (9U) +/*! FDZC - FPU divide-by-zero interrupt status + * 0b0..No interrupt + * 0b1..Interrupt occurred + */ #define MCM_ISCR_FDZC(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FDZC_SHIFT)) & MCM_ISCR_FDZC_MASK) #define MCM_ISCR_FOFC_MASK (0x400U) #define MCM_ISCR_FOFC_SHIFT (10U) +/*! FOFC - FPU overflow interrupt status + * 0b0..No interrupt + * 0b1..Interrupt occurred + */ #define MCM_ISCR_FOFC(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FOFC_SHIFT)) & MCM_ISCR_FOFC_MASK) #define MCM_ISCR_FUFC_MASK (0x800U) #define MCM_ISCR_FUFC_SHIFT (11U) +/*! FUFC - FPU underflow interrupt status + * 0b0..No interrupt + * 0b1..Interrupt occurred + */ #define MCM_ISCR_FUFC(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FUFC_SHIFT)) & MCM_ISCR_FUFC_MASK) #define MCM_ISCR_FIXC_MASK (0x1000U) #define MCM_ISCR_FIXC_SHIFT (12U) +/*! FIXC - FPU inexact interrupt status + * 0b0..No interrupt + * 0b1..Interrupt occurred + */ #define MCM_ISCR_FIXC(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIXC_SHIFT)) & MCM_ISCR_FIXC_MASK) #define MCM_ISCR_FIDC_MASK (0x8000U) #define MCM_ISCR_FIDC_SHIFT (15U) +/*! FIDC - FPU input denormal interrupt status + * 0b0..No interrupt + * 0b1..Interrupt occurred + */ #define MCM_ISCR_FIDC(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIDC_SHIFT)) & MCM_ISCR_FIDC_MASK) #define MCM_ISCR_FIOCE_MASK (0x1000000U) #define MCM_ISCR_FIOCE_SHIFT (24U) +/*! FIOCE - FPU invalid operation interrupt enable + * 0b0..Disable interrupt + * 0b1..Enable interrupt + */ #define MCM_ISCR_FIOCE(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIOCE_SHIFT)) & MCM_ISCR_FIOCE_MASK) #define MCM_ISCR_FDZCE_MASK (0x2000000U) #define MCM_ISCR_FDZCE_SHIFT (25U) +/*! FDZCE - FPU divide-by-zero interrupt enable + * 0b0..Disable interrupt + * 0b1..Enable interrupt + */ #define MCM_ISCR_FDZCE(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FDZCE_SHIFT)) & MCM_ISCR_FDZCE_MASK) #define MCM_ISCR_FOFCE_MASK (0x4000000U) #define MCM_ISCR_FOFCE_SHIFT (26U) +/*! FOFCE - FPU overflow interrupt enable + * 0b0..Disable interrupt + * 0b1..Enable interrupt + */ #define MCM_ISCR_FOFCE(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FOFCE_SHIFT)) & MCM_ISCR_FOFCE_MASK) #define MCM_ISCR_FUFCE_MASK (0x8000000U) #define MCM_ISCR_FUFCE_SHIFT (27U) +/*! FUFCE - FPU underflow interrupt enable + * 0b0..Disable interrupt + * 0b1..Enable interrupt + */ #define MCM_ISCR_FUFCE(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FUFCE_SHIFT)) & MCM_ISCR_FUFCE_MASK) #define MCM_ISCR_FIXCE_MASK (0x10000000U) #define MCM_ISCR_FIXCE_SHIFT (28U) +/*! FIXCE - FPU inexact interrupt enable + * 0b0..Disable interrupt + * 0b1..Enable interrupt + */ #define MCM_ISCR_FIXCE(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIXCE_SHIFT)) & MCM_ISCR_FIXCE_MASK) #define MCM_ISCR_FIDCE_MASK (0x80000000U) #define MCM_ISCR_FIDCE_SHIFT (31U) +/*! FIDCE - FPU input denormal interrupt enable + * 0b0..Disable interrupt + * 0b1..Enable interrupt + */ #define MCM_ISCR_FIDCE(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIDCE_SHIFT)) & MCM_ISCR_FIDCE_MASK) +/*! @} */ /*! @name ETBCC - ETB Counter Control register */ +/*! @{ */ #define MCM_ETBCC_CNTEN_MASK (0x1U) #define MCM_ETBCC_CNTEN_SHIFT (0U) +/*! CNTEN - Counter Enable + * 0b0..ETB counter disabled + * 0b1..ETB counter enabled + */ #define MCM_ETBCC_CNTEN(x) (((uint32_t)(((uint32_t)(x)) << MCM_ETBCC_CNTEN_SHIFT)) & MCM_ETBCC_CNTEN_MASK) #define MCM_ETBCC_RSPT_MASK (0x6U) #define MCM_ETBCC_RSPT_SHIFT (1U) +/*! RSPT - Response Type + * 0b00..No response when the ETB count expires + * 0b01..Generate a normal interrupt when the ETB count expires + * 0b10..Generate an NMI when the ETB count expires + * 0b11..Generate a debug halt when the ETB count expires + */ #define MCM_ETBCC_RSPT(x) (((uint32_t)(((uint32_t)(x)) << MCM_ETBCC_RSPT_SHIFT)) & MCM_ETBCC_RSPT_MASK) #define MCM_ETBCC_RLRQ_MASK (0x8U) #define MCM_ETBCC_RLRQ_SHIFT (3U) +/*! RLRQ - Reload Request + * 0b0..No effect + * 0b1..Clears pending debug halt, NMI, or IRQ interrupt requests + */ #define MCM_ETBCC_RLRQ(x) (((uint32_t)(((uint32_t)(x)) << MCM_ETBCC_RLRQ_SHIFT)) & MCM_ETBCC_RLRQ_MASK) #define MCM_ETBCC_ETDIS_MASK (0x10U) #define MCM_ETBCC_ETDIS_SHIFT (4U) +/*! ETDIS - ETM-To-TPIU Disable + * 0b0..ETM-to-TPIU trace path enabled + * 0b1..ETM-to-TPIU trace path disabled + */ #define MCM_ETBCC_ETDIS(x) (((uint32_t)(((uint32_t)(x)) << MCM_ETBCC_ETDIS_SHIFT)) & MCM_ETBCC_ETDIS_MASK) #define MCM_ETBCC_ITDIS_MASK (0x20U) #define MCM_ETBCC_ITDIS_SHIFT (5U) +/*! ITDIS - ITM-To-TPIU Disable + * 0b0..ITM-to-TPIU trace path enabled + * 0b1..ITM-to-TPIU trace path disabled + */ #define MCM_ETBCC_ITDIS(x) (((uint32_t)(((uint32_t)(x)) << MCM_ETBCC_ITDIS_SHIFT)) & MCM_ETBCC_ITDIS_MASK) +/*! @} */ /*! @name ETBRL - ETB Reload register */ +/*! @{ */ #define MCM_ETBRL_RELOAD_MASK (0x7FFU) #define MCM_ETBRL_RELOAD_SHIFT (0U) #define MCM_ETBRL_RELOAD(x) (((uint32_t)(((uint32_t)(x)) << MCM_ETBRL_RELOAD_SHIFT)) & MCM_ETBRL_RELOAD_MASK) +/*! @} */ /*! @name ETBCNT - ETB Counter Value register */ +/*! @{ */ #define MCM_ETBCNT_COUNTER_MASK (0x7FFU) #define MCM_ETBCNT_COUNTER_SHIFT (0U) #define MCM_ETBCNT_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << MCM_ETBCNT_COUNTER_SHIFT)) & MCM_ETBCNT_COUNTER_MASK) +/*! @} */ /*! @name PID - Process ID register */ +/*! @{ */ #define MCM_PID_PID_MASK (0xFFU) #define MCM_PID_PID_SHIFT (0U) #define MCM_PID_PID(x) (((uint32_t)(((uint32_t)(x)) << MCM_PID_PID_SHIFT)) & MCM_PID_PID_MASK) +/*! @} */ /*! @@ -8317,96 +14718,152 @@ typedef struct { */ /*! @name BACKKEY3 - Backdoor Comparison Key 3. */ +/*! @{ */ #define NV_BACKKEY3_KEY_MASK (0xFFU) #define NV_BACKKEY3_KEY_SHIFT (0U) #define NV_BACKKEY3_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY3_KEY_SHIFT)) & NV_BACKKEY3_KEY_MASK) +/*! @} */ /*! @name BACKKEY2 - Backdoor Comparison Key 2. */ +/*! @{ */ #define NV_BACKKEY2_KEY_MASK (0xFFU) #define NV_BACKKEY2_KEY_SHIFT (0U) #define NV_BACKKEY2_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY2_KEY_SHIFT)) & NV_BACKKEY2_KEY_MASK) +/*! @} */ /*! @name BACKKEY1 - Backdoor Comparison Key 1. */ +/*! @{ */ #define NV_BACKKEY1_KEY_MASK (0xFFU) #define NV_BACKKEY1_KEY_SHIFT (0U) #define NV_BACKKEY1_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY1_KEY_SHIFT)) & NV_BACKKEY1_KEY_MASK) +/*! @} */ /*! @name BACKKEY0 - Backdoor Comparison Key 0. */ +/*! @{ */ #define NV_BACKKEY0_KEY_MASK (0xFFU) #define NV_BACKKEY0_KEY_SHIFT (0U) #define NV_BACKKEY0_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY0_KEY_SHIFT)) & NV_BACKKEY0_KEY_MASK) +/*! @} */ /*! @name BACKKEY7 - Backdoor Comparison Key 7. */ +/*! @{ */ #define NV_BACKKEY7_KEY_MASK (0xFFU) #define NV_BACKKEY7_KEY_SHIFT (0U) #define NV_BACKKEY7_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY7_KEY_SHIFT)) & NV_BACKKEY7_KEY_MASK) +/*! @} */ /*! @name BACKKEY6 - Backdoor Comparison Key 6. */ +/*! @{ */ #define NV_BACKKEY6_KEY_MASK (0xFFU) #define NV_BACKKEY6_KEY_SHIFT (0U) #define NV_BACKKEY6_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY6_KEY_SHIFT)) & NV_BACKKEY6_KEY_MASK) +/*! @} */ /*! @name BACKKEY5 - Backdoor Comparison Key 5. */ +/*! @{ */ #define NV_BACKKEY5_KEY_MASK (0xFFU) #define NV_BACKKEY5_KEY_SHIFT (0U) #define NV_BACKKEY5_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY5_KEY_SHIFT)) & NV_BACKKEY5_KEY_MASK) +/*! @} */ /*! @name BACKKEY4 - Backdoor Comparison Key 4. */ +/*! @{ */ #define NV_BACKKEY4_KEY_MASK (0xFFU) #define NV_BACKKEY4_KEY_SHIFT (0U) #define NV_BACKKEY4_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY4_KEY_SHIFT)) & NV_BACKKEY4_KEY_MASK) +/*! @} */ /*! @name FPROT3 - Non-volatile P-Flash Protection 1 - Low Register */ +/*! @{ */ #define NV_FPROT3_PROT_MASK (0xFFU) #define NV_FPROT3_PROT_SHIFT (0U) #define NV_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FPROT3_PROT_SHIFT)) & NV_FPROT3_PROT_MASK) +/*! @} */ /*! @name FPROT2 - Non-volatile P-Flash Protection 1 - High Register */ +/*! @{ */ #define NV_FPROT2_PROT_MASK (0xFFU) #define NV_FPROT2_PROT_SHIFT (0U) #define NV_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FPROT2_PROT_SHIFT)) & NV_FPROT2_PROT_MASK) +/*! @} */ /*! @name FPROT1 - Non-volatile P-Flash Protection 0 - Low Register */ +/*! @{ */ #define NV_FPROT1_PROT_MASK (0xFFU) #define NV_FPROT1_PROT_SHIFT (0U) #define NV_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FPROT1_PROT_SHIFT)) & NV_FPROT1_PROT_MASK) +/*! @} */ /*! @name FPROT0 - Non-volatile P-Flash Protection 0 - High Register */ +/*! @{ */ #define NV_FPROT0_PROT_MASK (0xFFU) #define NV_FPROT0_PROT_SHIFT (0U) #define NV_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FPROT0_PROT_SHIFT)) & NV_FPROT0_PROT_MASK) +/*! @} */ /*! @name FSEC - Non-volatile Flash Security Register */ +/*! @{ */ #define NV_FSEC_SEC_MASK (0x3U) #define NV_FSEC_SEC_SHIFT (0U) +/*! SEC - Flash Security + * 0b10..MCU security status is unsecure + * 0b11..MCU security status is secure + */ #define NV_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x)) << NV_FSEC_SEC_SHIFT)) & NV_FSEC_SEC_MASK) #define NV_FSEC_FSLACC_MASK (0xCU) #define NV_FSEC_FSLACC_SHIFT (2U) +/*! FSLACC - Freescale Failure Analysis Access Code + * 0b10..Freescale factory access denied + * 0b11..Freescale factory access granted + */ #define NV_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x)) << NV_FSEC_FSLACC_SHIFT)) & NV_FSEC_FSLACC_MASK) #define NV_FSEC_MEEN_MASK (0x30U) #define NV_FSEC_MEEN_SHIFT (4U) +/*! MEEN + * 0b10..Mass erase is disabled + * 0b11..Mass erase is enabled + */ #define NV_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x)) << NV_FSEC_MEEN_SHIFT)) & NV_FSEC_MEEN_MASK) #define NV_FSEC_KEYEN_MASK (0xC0U) #define NV_FSEC_KEYEN_SHIFT (6U) +/*! KEYEN - Backdoor Key Security Enable + * 0b10..Backdoor key access enabled + * 0b11..Backdoor key access disabled + */ #define NV_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x)) << NV_FSEC_KEYEN_SHIFT)) & NV_FSEC_KEYEN_MASK) +/*! @} */ /*! @name FOPT - Non-volatile Flash Option Register */ +/*! @{ */ #define NV_FOPT_LPBOOT_MASK (0x1U) #define NV_FOPT_LPBOOT_SHIFT (0U) +/*! LPBOOT + * 0b0..Low-power boot + * 0b1..Normal boot + */ #define NV_FOPT_LPBOOT(x) (((uint8_t)(((uint8_t)(x)) << NV_FOPT_LPBOOT_SHIFT)) & NV_FOPT_LPBOOT_MASK) #define NV_FOPT_EZPORT_DIS_MASK (0x2U) #define NV_FOPT_EZPORT_DIS_SHIFT (1U) +/*! EZPORT_DIS + * 0b0..EzPort operation is disabled + * 0b1..EzPort operation is enabled + */ #define NV_FOPT_EZPORT_DIS(x) (((uint8_t)(((uint8_t)(x)) << NV_FOPT_EZPORT_DIS_SHIFT)) & NV_FOPT_EZPORT_DIS_MASK) +/*! @} */ /*! @name FEPROT - Non-volatile EERAM Protection Register */ +/*! @{ */ #define NV_FEPROT_EPROT_MASK (0xFFU) #define NV_FEPROT_EPROT_SHIFT (0U) #define NV_FEPROT_EPROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FEPROT_EPROT_SHIFT)) & NV_FEPROT_EPROT_MASK) +/*! @} */ /*! @name FDPROT - Non-volatile D-Flash Protection Register */ +/*! @{ */ #define NV_FDPROT_DPROT_MASK (0xFFU) #define NV_FDPROT_DPROT_SHIFT (0U) #define NV_FDPROT_DPROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FDPROT_DPROT_SHIFT)) & NV_FDPROT_DPROT_MASK) +/*! @} */ /*! @@ -8453,24 +14910,50 @@ typedef struct { */ /*! @name CR - OSC Control Register */ +/*! @{ */ #define OSC_CR_SC16P_MASK (0x1U) #define OSC_CR_SC16P_SHIFT (0U) +/*! SC16P - Oscillator 16 pF Capacitor Load Configure + * 0b0..Disable the selection. + * 0b1..Add 16 pF capacitor to the oscillator load. + */ #define OSC_CR_SC16P(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_SC16P_SHIFT)) & OSC_CR_SC16P_MASK) #define OSC_CR_SC8P_MASK (0x2U) #define OSC_CR_SC8P_SHIFT (1U) +/*! SC8P - Oscillator 8 pF Capacitor Load Configure + * 0b0..Disable the selection. + * 0b1..Add 8 pF capacitor to the oscillator load. + */ #define OSC_CR_SC8P(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_SC8P_SHIFT)) & OSC_CR_SC8P_MASK) #define OSC_CR_SC4P_MASK (0x4U) #define OSC_CR_SC4P_SHIFT (2U) +/*! SC4P - Oscillator 4 pF Capacitor Load Configure + * 0b0..Disable the selection. + * 0b1..Add 4 pF capacitor to the oscillator load. + */ #define OSC_CR_SC4P(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_SC4P_SHIFT)) & OSC_CR_SC4P_MASK) #define OSC_CR_SC2P_MASK (0x8U) #define OSC_CR_SC2P_SHIFT (3U) +/*! SC2P - Oscillator 2 pF Capacitor Load Configure + * 0b0..Disable the selection. + * 0b1..Add 2 pF capacitor to the oscillator load. + */ #define OSC_CR_SC2P(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_SC2P_SHIFT)) & OSC_CR_SC2P_MASK) #define OSC_CR_EREFSTEN_MASK (0x20U) #define OSC_CR_EREFSTEN_SHIFT (5U) +/*! EREFSTEN - External Reference Stop Enable + * 0b0..External reference clock is disabled in Stop mode. + * 0b1..External reference clock stays enabled in Stop mode if ERCLKEN is set before entering Stop mode. + */ #define OSC_CR_EREFSTEN(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_EREFSTEN_SHIFT)) & OSC_CR_EREFSTEN_MASK) #define OSC_CR_ERCLKEN_MASK (0x80U) #define OSC_CR_ERCLKEN_SHIFT (7U) +/*! ERCLKEN - External Reference Enable + * 0b0..External reference clock is inactive. + * 0b1..External reference clock is enabled. + */ #define OSC_CR_ERCLKEN(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_ERCLKEN_SHIFT)) & OSC_CR_ERCLKEN_MASK) +/*! @} */ /*! @@ -8534,87 +15017,177 @@ typedef struct { */ /*! @name SC - Status and Control register */ +/*! @{ */ #define PDB_SC_LDOK_MASK (0x1U) #define PDB_SC_LDOK_SHIFT (0U) #define PDB_SC_LDOK(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_LDOK_SHIFT)) & PDB_SC_LDOK_MASK) #define PDB_SC_CONT_MASK (0x2U) #define PDB_SC_CONT_SHIFT (1U) +/*! CONT - Continuous Mode Enable + * 0b0..PDB operation in One-Shot mode + * 0b1..PDB operation in Continuous mode + */ #define PDB_SC_CONT(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_CONT_SHIFT)) & PDB_SC_CONT_MASK) #define PDB_SC_MULT_MASK (0xCU) #define PDB_SC_MULT_SHIFT (2U) +/*! MULT - Multiplication Factor Select for Prescaler + * 0b00..Multiplication factor is 1. + * 0b01..Multiplication factor is 10. + * 0b10..Multiplication factor is 20. + * 0b11..Multiplication factor is 40. + */ #define PDB_SC_MULT(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_MULT_SHIFT)) & PDB_SC_MULT_MASK) #define PDB_SC_PDBIE_MASK (0x20U) #define PDB_SC_PDBIE_SHIFT (5U) +/*! PDBIE - PDB Interrupt Enable + * 0b0..PDB interrupt disabled. + * 0b1..PDB interrupt enabled. + */ #define PDB_SC_PDBIE(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_PDBIE_SHIFT)) & PDB_SC_PDBIE_MASK) #define PDB_SC_PDBIF_MASK (0x40U) #define PDB_SC_PDBIF_SHIFT (6U) #define PDB_SC_PDBIF(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_PDBIF_SHIFT)) & PDB_SC_PDBIF_MASK) #define PDB_SC_PDBEN_MASK (0x80U) #define PDB_SC_PDBEN_SHIFT (7U) +/*! PDBEN - PDB Enable + * 0b0..PDB disabled. Counter is off. + * 0b1..PDB enabled. + */ #define PDB_SC_PDBEN(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_PDBEN_SHIFT)) & PDB_SC_PDBEN_MASK) #define PDB_SC_TRGSEL_MASK (0xF00U) #define PDB_SC_TRGSEL_SHIFT (8U) +/*! TRGSEL - Trigger Input Source Select + * 0b0000..Trigger-In 0 is selected. + * 0b0001..Trigger-In 1 is selected. + * 0b0010..Trigger-In 2 is selected. + * 0b0011..Trigger-In 3 is selected. + * 0b0100..Trigger-In 4 is selected. + * 0b0101..Trigger-In 5 is selected. + * 0b0110..Trigger-In 6 is selected. + * 0b0111..Trigger-In 7 is selected. + * 0b1000..Trigger-In 8 is selected. + * 0b1001..Trigger-In 9 is selected. + * 0b1010..Trigger-In 10 is selected. + * 0b1011..Trigger-In 11 is selected. + * 0b1100..Trigger-In 12 is selected. + * 0b1101..Trigger-In 13 is selected. + * 0b1110..Trigger-In 14 is selected. + * 0b1111..Software trigger is selected. + */ #define PDB_SC_TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_TRGSEL_SHIFT)) & PDB_SC_TRGSEL_MASK) #define PDB_SC_PRESCALER_MASK (0x7000U) #define PDB_SC_PRESCALER_SHIFT (12U) +/*! PRESCALER - Prescaler Divider Select + * 0b000..Counting uses the peripheral clock divided by multiplication factor selected by MULT. + * 0b001..Counting uses the peripheral clock divided by twice of the multiplication factor selected by MULT. + * 0b010..Counting uses the peripheral clock divided by four times of the multiplication factor selected by MULT. + * 0b011..Counting uses the peripheral clock divided by eight times of the multiplication factor selected by MULT. + * 0b100..Counting uses the peripheral clock divided by 16 times of the multiplication factor selected by MULT. + * 0b101..Counting uses the peripheral clock divided by 32 times of the multiplication factor selected by MULT. + * 0b110..Counting uses the peripheral clock divided by 64 times of the multiplication factor selected by MULT. + * 0b111..Counting uses the peripheral clock divided by 128 times of the multiplication factor selected by MULT. + */ #define PDB_SC_PRESCALER(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_PRESCALER_SHIFT)) & PDB_SC_PRESCALER_MASK) #define PDB_SC_DMAEN_MASK (0x8000U) #define PDB_SC_DMAEN_SHIFT (15U) +/*! DMAEN - DMA Enable + * 0b0..DMA disabled. + * 0b1..DMA enabled. + */ #define PDB_SC_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_DMAEN_SHIFT)) & PDB_SC_DMAEN_MASK) #define PDB_SC_SWTRIG_MASK (0x10000U) #define PDB_SC_SWTRIG_SHIFT (16U) #define PDB_SC_SWTRIG(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_SWTRIG_SHIFT)) & PDB_SC_SWTRIG_MASK) #define PDB_SC_PDBEIE_MASK (0x20000U) #define PDB_SC_PDBEIE_SHIFT (17U) +/*! PDBEIE - PDB Sequence Error Interrupt Enable + * 0b0..PDB sequence error interrupt disabled. + * 0b1..PDB sequence error interrupt enabled. + */ #define PDB_SC_PDBEIE(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_PDBEIE_SHIFT)) & PDB_SC_PDBEIE_MASK) #define PDB_SC_LDMOD_MASK (0xC0000U) #define PDB_SC_LDMOD_SHIFT (18U) +/*! LDMOD - Load Mode Select + * 0b00..The internal registers are loaded with the values from their buffers immediately after 1 is written to LDOK. + * 0b01..The internal registers are loaded with the values from their buffers when the PDB counter reaches the MOD register value after 1 is written to LDOK. + * 0b10..The internal registers are loaded with the values from their buffers when a trigger input event is detected after 1 is written to LDOK. + * 0b11..The internal registers are loaded with the values from their buffers when either the PDB counter reaches the MOD register value or a trigger input event is detected, after 1 is written to LDOK. + */ #define PDB_SC_LDMOD(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_LDMOD_SHIFT)) & PDB_SC_LDMOD_MASK) +/*! @} */ /*! @name MOD - Modulus register */ +/*! @{ */ #define PDB_MOD_MOD_MASK (0xFFFFU) #define PDB_MOD_MOD_SHIFT (0U) #define PDB_MOD_MOD(x) (((uint32_t)(((uint32_t)(x)) << PDB_MOD_MOD_SHIFT)) & PDB_MOD_MOD_MASK) +/*! @} */ /*! @name CNT - Counter register */ +/*! @{ */ #define PDB_CNT_CNT_MASK (0xFFFFU) #define PDB_CNT_CNT_SHIFT (0U) #define PDB_CNT_CNT(x) (((uint32_t)(((uint32_t)(x)) << PDB_CNT_CNT_SHIFT)) & PDB_CNT_CNT_MASK) +/*! @} */ /*! @name IDLY - Interrupt Delay register */ +/*! @{ */ #define PDB_IDLY_IDLY_MASK (0xFFFFU) #define PDB_IDLY_IDLY_SHIFT (0U) #define PDB_IDLY_IDLY(x) (((uint32_t)(((uint32_t)(x)) << PDB_IDLY_IDLY_SHIFT)) & PDB_IDLY_IDLY_MASK) +/*! @} */ /*! @name C1 - Channel n Control register 1 */ +/*! @{ */ #define PDB_C1_EN_MASK (0xFFU) #define PDB_C1_EN_SHIFT (0U) +/*! EN - PDB Channel Pre-Trigger Enable + * 0b00000000..PDB channel's corresponding pre-trigger disabled. + * 0b00000001..PDB channel's corresponding pre-trigger enabled. + */ #define PDB_C1_EN(x) (((uint32_t)(((uint32_t)(x)) << PDB_C1_EN_SHIFT)) & PDB_C1_EN_MASK) #define PDB_C1_TOS_MASK (0xFF00U) #define PDB_C1_TOS_SHIFT (8U) +/*! TOS - PDB Channel Pre-Trigger Output Select + * 0b00000000..PDB channel's corresponding pre-trigger is in bypassed mode. The pre-trigger asserts one peripheral clock cycle after a rising edge is detected on selected trigger input source or software trigger is selected and SWTRIG is written with 1. + * 0b00000001..PDB channel's corresponding pre-trigger asserts when the counter reaches the channel delay register and one peripheral clock cycle after a rising edge is detected on selected trigger input source or software trigger is selected and SETRIG is written with 1. + */ #define PDB_C1_TOS(x) (((uint32_t)(((uint32_t)(x)) << PDB_C1_TOS_SHIFT)) & PDB_C1_TOS_MASK) #define PDB_C1_BB_MASK (0xFF0000U) #define PDB_C1_BB_SHIFT (16U) +/*! BB - PDB Channel Pre-Trigger Back-to-Back Operation Enable + * 0b00000000..PDB channel's corresponding pre-trigger back-to-back operation disabled. + * 0b00000001..PDB channel's corresponding pre-trigger back-to-back operation enabled. + */ #define PDB_C1_BB(x) (((uint32_t)(((uint32_t)(x)) << PDB_C1_BB_SHIFT)) & PDB_C1_BB_MASK) +/*! @} */ /* The count of PDB_C1 */ #define PDB_C1_COUNT (2U) /*! @name S - Channel n Status register */ +/*! @{ */ #define PDB_S_ERR_MASK (0xFFU) #define PDB_S_ERR_SHIFT (0U) +/*! ERR - PDB Channel Sequence Error Flags + * 0b00000000..Sequence error not detected on PDB channel's corresponding pre-trigger. + * 0b00000001..Sequence error detected on PDB channel's corresponding pre-trigger. ADCn block can be triggered for a conversion by one pre-trigger from PDB channel n. When one conversion, which is triggered by one of the pre-triggers from PDB channel n, is in progress, new trigger from PDB channel's corresponding pre-trigger m cannot be accepted by ADCn, and ERR[m] is set. Writing 0's to clear the sequence error flags. + */ #define PDB_S_ERR(x) (((uint32_t)(((uint32_t)(x)) << PDB_S_ERR_SHIFT)) & PDB_S_ERR_MASK) #define PDB_S_CF_MASK (0xFF0000U) #define PDB_S_CF_SHIFT (16U) #define PDB_S_CF(x) (((uint32_t)(((uint32_t)(x)) << PDB_S_CF_SHIFT)) & PDB_S_CF_MASK) +/*! @} */ /* The count of PDB_S */ #define PDB_S_COUNT (2U) /*! @name DLY - Channel n Delay 0 register..Channel n Delay 1 register */ +/*! @{ */ #define PDB_DLY_DLY_MASK (0xFFFFU) #define PDB_DLY_DLY_SHIFT (0U) #define PDB_DLY_DLY(x) (((uint32_t)(((uint32_t)(x)) << PDB_DLY_DLY_SHIFT)) & PDB_DLY_DLY_MASK) +/*! @} */ /* The count of PDB_DLY */ #define PDB_DLY_COUNT (2U) @@ -8623,36 +15196,56 @@ typedef struct { #define PDB_DLY_COUNT2 (2U) /*! @name INTC - DAC Interval Trigger n Control register */ +/*! @{ */ #define PDB_INTC_TOE_MASK (0x1U) #define PDB_INTC_TOE_SHIFT (0U) +/*! TOE - DAC Interval Trigger Enable + * 0b0..DAC interval trigger disabled. + * 0b1..DAC interval trigger enabled. + */ #define PDB_INTC_TOE(x) (((uint32_t)(((uint32_t)(x)) << PDB_INTC_TOE_SHIFT)) & PDB_INTC_TOE_MASK) #define PDB_INTC_EXT_MASK (0x2U) #define PDB_INTC_EXT_SHIFT (1U) +/*! EXT - DAC External Trigger Input Enable + * 0b0..DAC external trigger input disabled. DAC interval counter is reset and counting starts when a rising edge is detected on selected trigger input source or software trigger is selected and SWTRIG is written with 1. + * 0b1..DAC external trigger input enabled. DAC interval counter is bypassed and DAC external trigger input triggers the DAC interval trigger. + */ #define PDB_INTC_EXT(x) (((uint32_t)(((uint32_t)(x)) << PDB_INTC_EXT_SHIFT)) & PDB_INTC_EXT_MASK) +/*! @} */ /* The count of PDB_INTC */ #define PDB_INTC_COUNT (2U) /*! @name INT - DAC Interval n register */ +/*! @{ */ #define PDB_INT_INT_MASK (0xFFFFU) #define PDB_INT_INT_SHIFT (0U) #define PDB_INT_INT(x) (((uint32_t)(((uint32_t)(x)) << PDB_INT_INT_SHIFT)) & PDB_INT_INT_MASK) +/*! @} */ /* The count of PDB_INT */ #define PDB_INT_COUNT (2U) /*! @name POEN - Pulse-Out n Enable register */ +/*! @{ */ #define PDB_POEN_POEN_MASK (0xFFU) #define PDB_POEN_POEN_SHIFT (0U) +/*! POEN - PDB Pulse-Out Enable + * 0b00000000..PDB Pulse-Out disabled + * 0b00000001..PDB Pulse-Out enabled + */ #define PDB_POEN_POEN(x) (((uint32_t)(((uint32_t)(x)) << PDB_POEN_POEN_SHIFT)) & PDB_POEN_POEN_MASK) +/*! @} */ /*! @name PODLY - Pulse-Out n Delay register */ +/*! @{ */ #define PDB_PODLY_DLY2_MASK (0xFFFFU) #define PDB_PODLY_DLY2_SHIFT (0U) #define PDB_PODLY_DLY2(x) (((uint32_t)(((uint32_t)(x)) << PDB_PODLY_DLY2_SHIFT)) & PDB_PODLY_DLY2_MASK) #define PDB_PODLY_DLY1_MASK (0xFFFF0000U) #define PDB_PODLY_DLY1_SHIFT (16U) #define PDB_PODLY_DLY1(x) (((uint32_t)(((uint32_t)(x)) << PDB_PODLY_DLY1_SHIFT)) & PDB_PODLY_DLY1_MASK) +/*! @} */ /* The count of PDB_PODLY */ #define PDB_PODLY_COUNT (3U) @@ -8711,47 +15304,81 @@ typedef struct { */ /*! @name MCR - PIT Module Control Register */ +/*! @{ */ #define PIT_MCR_FRZ_MASK (0x1U) #define PIT_MCR_FRZ_SHIFT (0U) +/*! FRZ - Freeze + * 0b0..Timers continue to run in Debug mode. + * 0b1..Timers are stopped in Debug mode. + */ #define PIT_MCR_FRZ(x) (((uint32_t)(((uint32_t)(x)) << PIT_MCR_FRZ_SHIFT)) & PIT_MCR_FRZ_MASK) #define PIT_MCR_MDIS_MASK (0x2U) #define PIT_MCR_MDIS_SHIFT (1U) +/*! MDIS - Module Disable - (PIT section) + * 0b0..Clock for standard PIT timers is enabled. + * 0b1..Clock for standard PIT timers is disabled. + */ #define PIT_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << PIT_MCR_MDIS_SHIFT)) & PIT_MCR_MDIS_MASK) +/*! @} */ /*! @name LDVAL - Timer Load Value Register */ +/*! @{ */ #define PIT_LDVAL_TSV_MASK (0xFFFFFFFFU) #define PIT_LDVAL_TSV_SHIFT (0U) #define PIT_LDVAL_TSV(x) (((uint32_t)(((uint32_t)(x)) << PIT_LDVAL_TSV_SHIFT)) & PIT_LDVAL_TSV_MASK) +/*! @} */ /* The count of PIT_LDVAL */ #define PIT_LDVAL_COUNT (4U) /*! @name CVAL - Current Timer Value Register */ +/*! @{ */ #define PIT_CVAL_TVL_MASK (0xFFFFFFFFU) #define PIT_CVAL_TVL_SHIFT (0U) #define PIT_CVAL_TVL(x) (((uint32_t)(((uint32_t)(x)) << PIT_CVAL_TVL_SHIFT)) & PIT_CVAL_TVL_MASK) +/*! @} */ /* The count of PIT_CVAL */ #define PIT_CVAL_COUNT (4U) /*! @name TCTRL - Timer Control Register */ +/*! @{ */ #define PIT_TCTRL_TEN_MASK (0x1U) #define PIT_TCTRL_TEN_SHIFT (0U) +/*! TEN - Timer Enable + * 0b0..Timer n is disabled. + * 0b1..Timer n is enabled. + */ #define PIT_TCTRL_TEN(x) (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_TEN_SHIFT)) & PIT_TCTRL_TEN_MASK) #define PIT_TCTRL_TIE_MASK (0x2U) #define PIT_TCTRL_TIE_SHIFT (1U) +/*! TIE - Timer Interrupt Enable + * 0b0..Interrupt requests from Timer n are disabled. + * 0b1..Interrupt will be requested whenever TIF is set. + */ #define PIT_TCTRL_TIE(x) (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_TIE_SHIFT)) & PIT_TCTRL_TIE_MASK) #define PIT_TCTRL_CHN_MASK (0x4U) #define PIT_TCTRL_CHN_SHIFT (2U) +/*! CHN - Chain Mode + * 0b0..Timer is not chained. + * 0b1..Timer is chained to previous timer. For example, for Channel 2, if this field is set, Timer 2 is chained to Timer 1. + */ #define PIT_TCTRL_CHN(x) (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_CHN_SHIFT)) & PIT_TCTRL_CHN_MASK) +/*! @} */ /* The count of PIT_TCTRL */ #define PIT_TCTRL_COUNT (4U) /*! @name TFLG - Timer Flag Register */ +/*! @{ */ #define PIT_TFLG_TIF_MASK (0x1U) #define PIT_TFLG_TIF_SHIFT (0U) +/*! TIF - Timer Interrupt Flag + * 0b0..Timeout has not yet occurred. + * 0b1..Timeout has occurred. + */ #define PIT_TFLG_TIF(x) (((uint32_t)(((uint32_t)(x)) << PIT_TFLG_TIF_SHIFT)) & PIT_TFLG_TIF_MASK) +/*! @} */ /* The count of PIT_TFLG */ #define PIT_TFLG_COUNT (4U) @@ -8805,49 +15432,103 @@ typedef struct { */ /*! @name LVDSC1 - Low Voltage Detect Status And Control 1 register */ +/*! @{ */ #define PMC_LVDSC1_LVDV_MASK (0x3U) #define PMC_LVDSC1_LVDV_SHIFT (0U) +/*! LVDV - Low-Voltage Detect Voltage Select + * 0b00..Low trip point selected (V LVD = V LVDL ) + * 0b01..High trip point selected (V LVD = V LVDH ) + * 0b10..Reserved + * 0b11..Reserved + */ #define PMC_LVDSC1_LVDV(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDV_SHIFT)) & PMC_LVDSC1_LVDV_MASK) #define PMC_LVDSC1_LVDRE_MASK (0x10U) #define PMC_LVDSC1_LVDRE_SHIFT (4U) +/*! LVDRE - Low-Voltage Detect Reset Enable + * 0b0..LVDF does not generate hardware resets + * 0b1..Force an MCU reset when LVDF = 1 + */ #define PMC_LVDSC1_LVDRE(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDRE_SHIFT)) & PMC_LVDSC1_LVDRE_MASK) #define PMC_LVDSC1_LVDIE_MASK (0x20U) #define PMC_LVDSC1_LVDIE_SHIFT (5U) +/*! LVDIE - Low-Voltage Detect Interrupt Enable + * 0b0..Hardware interrupt disabled (use polling) + * 0b1..Request a hardware interrupt when LVDF = 1 + */ #define PMC_LVDSC1_LVDIE(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDIE_SHIFT)) & PMC_LVDSC1_LVDIE_MASK) #define PMC_LVDSC1_LVDACK_MASK (0x40U) #define PMC_LVDSC1_LVDACK_SHIFT (6U) #define PMC_LVDSC1_LVDACK(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDACK_SHIFT)) & PMC_LVDSC1_LVDACK_MASK) #define PMC_LVDSC1_LVDF_MASK (0x80U) #define PMC_LVDSC1_LVDF_SHIFT (7U) +/*! LVDF - Low-Voltage Detect Flag + * 0b0..Low-voltage event not detected + * 0b1..Low-voltage event detected + */ #define PMC_LVDSC1_LVDF(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDF_SHIFT)) & PMC_LVDSC1_LVDF_MASK) +/*! @} */ /*! @name LVDSC2 - Low Voltage Detect Status And Control 2 register */ +/*! @{ */ #define PMC_LVDSC2_LVWV_MASK (0x3U) #define PMC_LVDSC2_LVWV_SHIFT (0U) +/*! LVWV - Low-Voltage Warning Voltage Select + * 0b00..Low trip point selected (VLVW = VLVW1) + * 0b01..Mid 1 trip point selected (VLVW = VLVW2) + * 0b10..Mid 2 trip point selected (VLVW = VLVW3) + * 0b11..High trip point selected (VLVW = VLVW4) + */ #define PMC_LVDSC2_LVWV(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWV_SHIFT)) & PMC_LVDSC2_LVWV_MASK) #define PMC_LVDSC2_LVWIE_MASK (0x20U) #define PMC_LVDSC2_LVWIE_SHIFT (5U) +/*! LVWIE - Low-Voltage Warning Interrupt Enable + * 0b0..Hardware interrupt disabled (use polling) + * 0b1..Request a hardware interrupt when LVWF = 1 + */ #define PMC_LVDSC2_LVWIE(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWIE_SHIFT)) & PMC_LVDSC2_LVWIE_MASK) #define PMC_LVDSC2_LVWACK_MASK (0x40U) #define PMC_LVDSC2_LVWACK_SHIFT (6U) #define PMC_LVDSC2_LVWACK(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWACK_SHIFT)) & PMC_LVDSC2_LVWACK_MASK) #define PMC_LVDSC2_LVWF_MASK (0x80U) #define PMC_LVDSC2_LVWF_SHIFT (7U) +/*! LVWF - Low-Voltage Warning Flag + * 0b0..Low-voltage warning event not detected + * 0b1..Low-voltage warning event detected + */ #define PMC_LVDSC2_LVWF(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWF_SHIFT)) & PMC_LVDSC2_LVWF_MASK) +/*! @} */ /*! @name REGSC - Regulator Status And Control register */ +/*! @{ */ #define PMC_REGSC_BGBE_MASK (0x1U) #define PMC_REGSC_BGBE_SHIFT (0U) +/*! BGBE - Bandgap Buffer Enable + * 0b0..Bandgap buffer not enabled + * 0b1..Bandgap buffer enabled + */ #define PMC_REGSC_BGBE(x) (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_BGBE_SHIFT)) & PMC_REGSC_BGBE_MASK) #define PMC_REGSC_REGONS_MASK (0x4U) #define PMC_REGSC_REGONS_SHIFT (2U) +/*! REGONS - Regulator In Run Regulation Status + * 0b0..Regulator is in stop regulation or in transition to/from it + * 0b1..Regulator is in run regulation + */ #define PMC_REGSC_REGONS(x) (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_REGONS_SHIFT)) & PMC_REGSC_REGONS_MASK) #define PMC_REGSC_ACKISO_MASK (0x8U) #define PMC_REGSC_ACKISO_SHIFT (3U) +/*! ACKISO - Acknowledge Isolation + * 0b0..Peripherals and I/O pads are in normal run state. + * 0b1..Certain peripherals and I/O pads are in an isolated and latched state. + */ #define PMC_REGSC_ACKISO(x) (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_ACKISO_SHIFT)) & PMC_REGSC_ACKISO_MASK) #define PMC_REGSC_BGEN_MASK (0x10U) #define PMC_REGSC_BGEN_SHIFT (4U) +/*! BGEN - Bandgap Enable In VLPx Operation + * 0b0..Bandgap voltage reference is disabled in VLPx , LLS , and VLLSx modes. + * 0b1..Bandgap voltage reference is enabled in VLPx , LLS , and VLLSx modes. + */ #define PMC_REGSC_BGEN(x) (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_BGEN_SHIFT)) & PMC_REGSC_BGEN_MASK) +/*! @} */ /*! @@ -8904,75 +15585,162 @@ typedef struct { */ /*! @name PCR - Pin Control Register n */ +/*! @{ */ #define PORT_PCR_PS_MASK (0x1U) #define PORT_PCR_PS_SHIFT (0U) +/*! PS - Pull Select + * 0b0..Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. + * 0b1..Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. + */ #define PORT_PCR_PS(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PS_SHIFT)) & PORT_PCR_PS_MASK) #define PORT_PCR_PE_MASK (0x2U) #define PORT_PCR_PE_SHIFT (1U) +/*! PE - Pull Enable + * 0b0..Internal pullup or pulldown resistor is not enabled on the corresponding pin. + * 0b1..Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. + */ #define PORT_PCR_PE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PE_SHIFT)) & PORT_PCR_PE_MASK) #define PORT_PCR_SRE_MASK (0x4U) #define PORT_PCR_SRE_SHIFT (2U) +/*! SRE - Slew Rate Enable + * 0b0..Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. + * 0b1..Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. + */ #define PORT_PCR_SRE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_SRE_SHIFT)) & PORT_PCR_SRE_MASK) #define PORT_PCR_PFE_MASK (0x10U) #define PORT_PCR_PFE_SHIFT (4U) +/*! PFE - Passive Filter Enable + * 0b0..Passive input filter is disabled on the corresponding pin. + * 0b1..Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. + */ #define PORT_PCR_PFE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PFE_SHIFT)) & PORT_PCR_PFE_MASK) #define PORT_PCR_ODE_MASK (0x20U) #define PORT_PCR_ODE_SHIFT (5U) +/*! ODE - Open Drain Enable + * 0b0..Open drain output is disabled on the corresponding pin. + * 0b1..Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. + */ #define PORT_PCR_ODE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_ODE_SHIFT)) & PORT_PCR_ODE_MASK) #define PORT_PCR_DSE_MASK (0x40U) #define PORT_PCR_DSE_SHIFT (6U) +/*! DSE - Drive Strength Enable + * 0b0..Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. + * 0b1..High drive strength is configured on the corresponding pin, if pin is configured as a digital output. + */ #define PORT_PCR_DSE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_DSE_SHIFT)) & PORT_PCR_DSE_MASK) #define PORT_PCR_MUX_MASK (0x700U) #define PORT_PCR_MUX_SHIFT (8U) +/*! MUX - Pin Mux Control + * 0b000..Pin disabled (analog). + * 0b001..Alternative 1 (GPIO). + * 0b010..Alternative 2 (chip-specific). + * 0b011..Alternative 3 (chip-specific). + * 0b100..Alternative 4 (chip-specific). + * 0b101..Alternative 5 (chip-specific). + * 0b110..Alternative 6 (chip-specific). + * 0b111..Alternative 7 (chip-specific). + */ #define PORT_PCR_MUX(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_MUX_SHIFT)) & PORT_PCR_MUX_MASK) #define PORT_PCR_LK_MASK (0x8000U) #define PORT_PCR_LK_SHIFT (15U) +/*! LK - Lock Register + * 0b0..Pin Control Register fields [15:0] are not locked. + * 0b1..Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. + */ #define PORT_PCR_LK(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_LK_SHIFT)) & PORT_PCR_LK_MASK) #define PORT_PCR_IRQC_MASK (0xF0000U) #define PORT_PCR_IRQC_SHIFT (16U) +/*! IRQC - Interrupt Configuration + * 0b0000..Interrupt/DMA request disabled. + * 0b0001..DMA request on rising edge. + * 0b0010..DMA request on falling edge. + * 0b0011..DMA request on either edge. + * 0b1000..Interrupt when logic 0. + * 0b1001..Interrupt on rising-edge. + * 0b1010..Interrupt on falling-edge. + * 0b1011..Interrupt on either edge. + * 0b1100..Interrupt when logic 1. + */ #define PORT_PCR_IRQC(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_IRQC_SHIFT)) & PORT_PCR_IRQC_MASK) #define PORT_PCR_ISF_MASK (0x1000000U) #define PORT_PCR_ISF_SHIFT (24U) +/*! ISF - Interrupt Status Flag + * 0b0..Configured interrupt is not detected. + * 0b1..Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. + */ #define PORT_PCR_ISF(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_ISF_SHIFT)) & PORT_PCR_ISF_MASK) +/*! @} */ /* The count of PORT_PCR */ #define PORT_PCR_COUNT (32U) /*! @name GPCLR - Global Pin Control Low Register */ +/*! @{ */ #define PORT_GPCLR_GPWD_MASK (0xFFFFU) #define PORT_GPCLR_GPWD_SHIFT (0U) #define PORT_GPCLR_GPWD(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWD_SHIFT)) & PORT_GPCLR_GPWD_MASK) #define PORT_GPCLR_GPWE_MASK (0xFFFF0000U) #define PORT_GPCLR_GPWE_SHIFT (16U) +/*! GPWE - Global Pin Write Enable + * 0b0000000000000000..Corresponding Pin Control Register is not updated with the value in GPWD. + * 0b0000000000000001..Corresponding Pin Control Register is updated with the value in GPWD. + */ #define PORT_GPCLR_GPWE(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE_SHIFT)) & PORT_GPCLR_GPWE_MASK) +/*! @} */ /*! @name GPCHR - Global Pin Control High Register */ +/*! @{ */ #define PORT_GPCHR_GPWD_MASK (0xFFFFU) #define PORT_GPCHR_GPWD_SHIFT (0U) #define PORT_GPCHR_GPWD(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWD_SHIFT)) & PORT_GPCHR_GPWD_MASK) #define PORT_GPCHR_GPWE_MASK (0xFFFF0000U) #define PORT_GPCHR_GPWE_SHIFT (16U) +/*! GPWE - Global Pin Write Enable + * 0b0000000000000000..Corresponding Pin Control Register is not updated with the value in GPWD. + * 0b0000000000000001..Corresponding Pin Control Register is updated with the value in GPWD. + */ #define PORT_GPCHR_GPWE(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE_SHIFT)) & PORT_GPCHR_GPWE_MASK) +/*! @} */ /*! @name ISFR - Interrupt Status Flag Register */ +/*! @{ */ #define PORT_ISFR_ISF_MASK (0xFFFFFFFFU) #define PORT_ISFR_ISF_SHIFT (0U) +/*! ISF - Interrupt Status Flag + * 0b00000000000000000000000000000000..Configured interrupt is not detected. + * 0b00000000000000000000000000000001..Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. + */ #define PORT_ISFR_ISF(x) (((uint32_t)(((uint32_t)(x)) << PORT_ISFR_ISF_SHIFT)) & PORT_ISFR_ISF_MASK) +/*! @} */ /*! @name DFER - Digital Filter Enable Register */ +/*! @{ */ #define PORT_DFER_DFE_MASK (0xFFFFFFFFU) #define PORT_DFER_DFE_SHIFT (0U) +/*! DFE - Digital Filter Enable + * 0b00000000000000000000000000000000..Digital filter is disabled on the corresponding pin and output of the digital filter is reset to zero. + * 0b00000000000000000000000000000001..Digital filter is enabled on the corresponding pin, if the pin is configured as a digital input. + */ #define PORT_DFER_DFE(x) (((uint32_t)(((uint32_t)(x)) << PORT_DFER_DFE_SHIFT)) & PORT_DFER_DFE_MASK) +/*! @} */ /*! @name DFCR - Digital Filter Clock Register */ +/*! @{ */ #define PORT_DFCR_CS_MASK (0x1U) #define PORT_DFCR_CS_SHIFT (0U) +/*! CS - Clock Source + * 0b0..Digital filters are clocked by the bus clock. + * 0b1..Digital filters are clocked by the 1 kHz LPO clock. + */ #define PORT_DFCR_CS(x) (((uint32_t)(((uint32_t)(x)) << PORT_DFCR_CS_SHIFT)) & PORT_DFCR_CS_MASK) +/*! @} */ /*! @name DFWR - Digital Filter Width Register */ +/*! @{ */ #define PORT_DFWR_FILT_MASK (0x1FU) #define PORT_DFWR_FILT_SHIFT (0U) #define PORT_DFWR_FILT(x) (((uint32_t)(((uint32_t)(x)) << PORT_DFWR_FILT_SHIFT)) & PORT_DFWR_FILT_MASK) +/*! @} */ /*! @@ -9043,65 +15811,175 @@ typedef struct { */ /*! @name SRS0 - System Reset Status Register 0 */ +/*! @{ */ #define RCM_SRS0_WAKEUP_MASK (0x1U) #define RCM_SRS0_WAKEUP_SHIFT (0U) +/*! WAKEUP - Low Leakage Wakeup Reset + * 0b0..Reset not caused by LLWU module wakeup source + * 0b1..Reset caused by LLWU module wakeup source + */ #define RCM_SRS0_WAKEUP(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_WAKEUP_SHIFT)) & RCM_SRS0_WAKEUP_MASK) #define RCM_SRS0_LVD_MASK (0x2U) #define RCM_SRS0_LVD_SHIFT (1U) +/*! LVD - Low-Voltage Detect Reset + * 0b0..Reset not caused by LVD trip or POR + * 0b1..Reset caused by LVD trip or POR + */ #define RCM_SRS0_LVD(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_LVD_SHIFT)) & RCM_SRS0_LVD_MASK) #define RCM_SRS0_LOC_MASK (0x4U) #define RCM_SRS0_LOC_SHIFT (2U) +/*! LOC - Loss-of-Clock Reset + * 0b0..Reset not caused by a loss of external clock. + * 0b1..Reset caused by a loss of external clock. + */ #define RCM_SRS0_LOC(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_LOC_SHIFT)) & RCM_SRS0_LOC_MASK) #define RCM_SRS0_LOL_MASK (0x8U) #define RCM_SRS0_LOL_SHIFT (3U) +/*! LOL - Loss-of-Lock Reset + * 0b0..Reset not caused by a loss of lock in the PLL + * 0b1..Reset caused by a loss of lock in the PLL + */ #define RCM_SRS0_LOL(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_LOL_SHIFT)) & RCM_SRS0_LOL_MASK) #define RCM_SRS0_WDOG_MASK (0x20U) #define RCM_SRS0_WDOG_SHIFT (5U) +/*! WDOG - Watchdog + * 0b0..Reset not caused by watchdog timeout + * 0b1..Reset caused by watchdog timeout + */ #define RCM_SRS0_WDOG(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_WDOG_SHIFT)) & RCM_SRS0_WDOG_MASK) #define RCM_SRS0_PIN_MASK (0x40U) #define RCM_SRS0_PIN_SHIFT (6U) +/*! PIN - External Reset Pin + * 0b0..Reset not caused by external reset pin + * 0b1..Reset caused by external reset pin + */ #define RCM_SRS0_PIN(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_PIN_SHIFT)) & RCM_SRS0_PIN_MASK) #define RCM_SRS0_POR_MASK (0x80U) #define RCM_SRS0_POR_SHIFT (7U) +/*! POR - Power-On Reset + * 0b0..Reset not caused by POR + * 0b1..Reset caused by POR + */ #define RCM_SRS0_POR(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_POR_SHIFT)) & RCM_SRS0_POR_MASK) +/*! @} */ /*! @name SRS1 - System Reset Status Register 1 */ +/*! @{ */ #define RCM_SRS1_JTAG_MASK (0x1U) #define RCM_SRS1_JTAG_SHIFT (0U) +/*! JTAG - JTAG Generated Reset + * 0b0..Reset not caused by JTAG + * 0b1..Reset caused by JTAG + */ #define RCM_SRS1_JTAG(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_JTAG_SHIFT)) & RCM_SRS1_JTAG_MASK) #define RCM_SRS1_LOCKUP_MASK (0x2U) #define RCM_SRS1_LOCKUP_SHIFT (1U) +/*! LOCKUP - Core Lockup + * 0b0..Reset not caused by core LOCKUP event + * 0b1..Reset caused by core LOCKUP event + */ #define RCM_SRS1_LOCKUP(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_LOCKUP_SHIFT)) & RCM_SRS1_LOCKUP_MASK) #define RCM_SRS1_SW_MASK (0x4U) #define RCM_SRS1_SW_SHIFT (2U) +/*! SW - Software + * 0b0..Reset not caused by software setting of SYSRESETREQ bit + * 0b1..Reset caused by software setting of SYSRESETREQ bit + */ #define RCM_SRS1_SW(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_SW_SHIFT)) & RCM_SRS1_SW_MASK) #define RCM_SRS1_MDM_AP_MASK (0x8U) #define RCM_SRS1_MDM_AP_SHIFT (3U) +/*! MDM_AP - MDM-AP System Reset Request + * 0b0..Reset not caused by host debugger system setting of the System Reset Request bit + * 0b1..Reset caused by host debugger system setting of the System Reset Request bit + */ #define RCM_SRS1_MDM_AP(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_MDM_AP_SHIFT)) & RCM_SRS1_MDM_AP_MASK) #define RCM_SRS1_EZPT_MASK (0x10U) #define RCM_SRS1_EZPT_SHIFT (4U) +/*! EZPT - EzPort Reset + * 0b0..Reset not caused by EzPort receiving the RESET command while the device is in EzPort mode + * 0b1..Reset caused by EzPort receiving the RESET command while the device is in EzPort mode + */ #define RCM_SRS1_EZPT(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_EZPT_SHIFT)) & RCM_SRS1_EZPT_MASK) #define RCM_SRS1_SACKERR_MASK (0x20U) #define RCM_SRS1_SACKERR_SHIFT (5U) +/*! SACKERR - Stop Mode Acknowledge Error Reset + * 0b0..Reset not caused by peripheral failure to acknowledge attempt to enter stop mode + * 0b1..Reset caused by peripheral failure to acknowledge attempt to enter stop mode + */ #define RCM_SRS1_SACKERR(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_SACKERR_SHIFT)) & RCM_SRS1_SACKERR_MASK) +/*! @} */ /*! @name RPFC - Reset Pin Filter Control register */ +/*! @{ */ #define RCM_RPFC_RSTFLTSRW_MASK (0x3U) #define RCM_RPFC_RSTFLTSRW_SHIFT (0U) +/*! RSTFLTSRW - Reset Pin Filter Select in Run and Wait Modes + * 0b00..All filtering disabled + * 0b01..Bus clock filter enabled for normal operation + * 0b10..LPO clock filter enabled for normal operation + * 0b11..Reserved + */ #define RCM_RPFC_RSTFLTSRW(x) (((uint8_t)(((uint8_t)(x)) << RCM_RPFC_RSTFLTSRW_SHIFT)) & RCM_RPFC_RSTFLTSRW_MASK) #define RCM_RPFC_RSTFLTSS_MASK (0x4U) #define RCM_RPFC_RSTFLTSS_SHIFT (2U) +/*! RSTFLTSS - Reset Pin Filter Select in Stop Mode + * 0b0..All filtering disabled + * 0b1..LPO clock filter enabled + */ #define RCM_RPFC_RSTFLTSS(x) (((uint8_t)(((uint8_t)(x)) << RCM_RPFC_RSTFLTSS_SHIFT)) & RCM_RPFC_RSTFLTSS_MASK) +/*! @} */ /*! @name RPFW - Reset Pin Filter Width register */ +/*! @{ */ #define RCM_RPFW_RSTFLTSEL_MASK (0x1FU) #define RCM_RPFW_RSTFLTSEL_SHIFT (0U) +/*! RSTFLTSEL - Reset Pin Filter Bus Clock Select + * 0b00000..Bus clock filter count is 1 + * 0b00001..Bus clock filter count is 2 + * 0b00010..Bus clock filter count is 3 + * 0b00011..Bus clock filter count is 4 + * 0b00100..Bus clock filter count is 5 + * 0b00101..Bus clock filter count is 6 + * 0b00110..Bus clock filter count is 7 + * 0b00111..Bus clock filter count is 8 + * 0b01000..Bus clock filter count is 9 + * 0b01001..Bus clock filter count is 10 + * 0b01010..Bus clock filter count is 11 + * 0b01011..Bus clock filter count is 12 + * 0b01100..Bus clock filter count is 13 + * 0b01101..Bus clock filter count is 14 + * 0b01110..Bus clock filter count is 15 + * 0b01111..Bus clock filter count is 16 + * 0b10000..Bus clock filter count is 17 + * 0b10001..Bus clock filter count is 18 + * 0b10010..Bus clock filter count is 19 + * 0b10011..Bus clock filter count is 20 + * 0b10100..Bus clock filter count is 21 + * 0b10101..Bus clock filter count is 22 + * 0b10110..Bus clock filter count is 23 + * 0b10111..Bus clock filter count is 24 + * 0b11000..Bus clock filter count is 25 + * 0b11001..Bus clock filter count is 26 + * 0b11010..Bus clock filter count is 27 + * 0b11011..Bus clock filter count is 28 + * 0b11100..Bus clock filter count is 29 + * 0b11101..Bus clock filter count is 30 + * 0b11110..Bus clock filter count is 31 + * 0b11111..Bus clock filter count is 32 + */ #define RCM_RPFW_RSTFLTSEL(x) (((uint8_t)(((uint8_t)(x)) << RCM_RPFW_RSTFLTSEL_SHIFT)) & RCM_RPFW_RSTFLTSEL_MASK) +/*! @} */ /*! @name MR - Mode Register */ +/*! @{ */ #define RCM_MR_EZP_MS_MASK (0x2U) #define RCM_MR_EZP_MS_SHIFT (1U) +/*! EZP_MS - EZP_MS_B pin state + * 0b0..Pin deasserted (logic 1) + * 0b1..Pin asserted (logic 0) + */ #define RCM_MR_EZP_MS(x) (((uint8_t)(((uint8_t)(x)) << RCM_MR_EZP_MS_SHIFT)) & RCM_MR_EZP_MS_MASK) +/*! @} */ /*! @@ -9148,6 +16026,7 @@ typedef struct { */ /*! @name REG - Register file register */ +/*! @{ */ #define RFSYS_REG_LL_MASK (0xFFU) #define RFSYS_REG_LL_SHIFT (0U) #define RFSYS_REG_LL(x) (((uint32_t)(((uint32_t)(x)) << RFSYS_REG_LL_SHIFT)) & RFSYS_REG_LL_MASK) @@ -9160,6 +16039,7 @@ typedef struct { #define RFSYS_REG_HH_MASK (0xFF000000U) #define RFSYS_REG_HH_SHIFT (24U) #define RFSYS_REG_HH(x) (((uint32_t)(((uint32_t)(x)) << RFSYS_REG_HH_SHIFT)) & RFSYS_REG_HH_MASK) +/*! @} */ /* The count of RFSYS_REG */ #define RFSYS_REG_COUNT (8U) @@ -9209,6 +16089,7 @@ typedef struct { */ /*! @name REG - VBAT register file register */ +/*! @{ */ #define RFVBAT_REG_LL_MASK (0xFFU) #define RFVBAT_REG_LL_SHIFT (0U) #define RFVBAT_REG_LL(x) (((uint32_t)(((uint32_t)(x)) << RFVBAT_REG_LL_SHIFT)) & RFVBAT_REG_LL_MASK) @@ -9221,6 +16102,7 @@ typedef struct { #define RFVBAT_REG_HH_MASK (0xFF000000U) #define RFVBAT_REG_HH_SHIFT (24U) #define RFVBAT_REG_HH(x) (((uint32_t)(((uint32_t)(x)) << RFVBAT_REG_HH_SHIFT)) & RFVBAT_REG_HH_MASK) +/*! @} */ /* The count of RFVBAT_REG */ #define RFVBAT_REG_COUNT (8U) @@ -9273,54 +16155,112 @@ typedef struct { */ /*! @name CR - RNGA Control Register */ +/*! @{ */ #define RNG_CR_GO_MASK (0x1U) #define RNG_CR_GO_SHIFT (0U) +/*! GO - Go + * 0b0..Disabled + * 0b1..Enabled + */ #define RNG_CR_GO(x) (((uint32_t)(((uint32_t)(x)) << RNG_CR_GO_SHIFT)) & RNG_CR_GO_MASK) #define RNG_CR_HA_MASK (0x2U) #define RNG_CR_HA_SHIFT (1U) +/*! HA - High Assurance + * 0b0..Disabled + * 0b1..Enabled + */ #define RNG_CR_HA(x) (((uint32_t)(((uint32_t)(x)) << RNG_CR_HA_SHIFT)) & RNG_CR_HA_MASK) #define RNG_CR_INTM_MASK (0x4U) #define RNG_CR_INTM_SHIFT (2U) +/*! INTM - Interrupt Mask + * 0b0..Not masked + * 0b1..Masked + */ #define RNG_CR_INTM(x) (((uint32_t)(((uint32_t)(x)) << RNG_CR_INTM_SHIFT)) & RNG_CR_INTM_MASK) #define RNG_CR_CLRI_MASK (0x8U) #define RNG_CR_CLRI_SHIFT (3U) +/*! CLRI - Clear Interrupt + * 0b0..Do not clear the interrupt. + * 0b1..Clear the interrupt. When you write 1 to this field, RNGA then resets the error-interrupt indicator (SR[ERRI]). This bit always reads as 0. + */ #define RNG_CR_CLRI(x) (((uint32_t)(((uint32_t)(x)) << RNG_CR_CLRI_SHIFT)) & RNG_CR_CLRI_MASK) #define RNG_CR_SLP_MASK (0x10U) #define RNG_CR_SLP_SHIFT (4U) +/*! SLP - Sleep + * 0b0..Normal mode + * 0b1..Sleep (low-power) mode + */ #define RNG_CR_SLP(x) (((uint32_t)(((uint32_t)(x)) << RNG_CR_SLP_SHIFT)) & RNG_CR_SLP_MASK) +/*! @} */ /*! @name SR - RNGA Status Register */ +/*! @{ */ #define RNG_SR_SECV_MASK (0x1U) #define RNG_SR_SECV_SHIFT (0U) +/*! SECV - Security Violation + * 0b0..No security violation + * 0b1..Security violation + */ #define RNG_SR_SECV(x) (((uint32_t)(((uint32_t)(x)) << RNG_SR_SECV_SHIFT)) & RNG_SR_SECV_MASK) #define RNG_SR_LRS_MASK (0x2U) #define RNG_SR_LRS_SHIFT (1U) +/*! LRS - Last Read Status + * 0b0..No underflow + * 0b1..Underflow + */ #define RNG_SR_LRS(x) (((uint32_t)(((uint32_t)(x)) << RNG_SR_LRS_SHIFT)) & RNG_SR_LRS_MASK) #define RNG_SR_ORU_MASK (0x4U) #define RNG_SR_ORU_SHIFT (2U) +/*! ORU - Output Register Underflow + * 0b0..No underflow + * 0b1..Underflow + */ #define RNG_SR_ORU(x) (((uint32_t)(((uint32_t)(x)) << RNG_SR_ORU_SHIFT)) & RNG_SR_ORU_MASK) #define RNG_SR_ERRI_MASK (0x8U) #define RNG_SR_ERRI_SHIFT (3U) +/*! ERRI - Error Interrupt + * 0b0..No underflow + * 0b1..Underflow + */ #define RNG_SR_ERRI(x) (((uint32_t)(((uint32_t)(x)) << RNG_SR_ERRI_SHIFT)) & RNG_SR_ERRI_MASK) #define RNG_SR_SLP_MASK (0x10U) #define RNG_SR_SLP_SHIFT (4U) +/*! SLP - Sleep + * 0b0..Normal mode + * 0b1..Sleep (low-power) mode + */ #define RNG_SR_SLP(x) (((uint32_t)(((uint32_t)(x)) << RNG_SR_SLP_SHIFT)) & RNG_SR_SLP_MASK) #define RNG_SR_OREG_LVL_MASK (0xFF00U) #define RNG_SR_OREG_LVL_SHIFT (8U) +/*! OREG_LVL - Output Register Level + * 0b00000000..No words (empty) + * 0b00000001..One word (valid) + */ #define RNG_SR_OREG_LVL(x) (((uint32_t)(((uint32_t)(x)) << RNG_SR_OREG_LVL_SHIFT)) & RNG_SR_OREG_LVL_MASK) #define RNG_SR_OREG_SIZE_MASK (0xFF0000U) #define RNG_SR_OREG_SIZE_SHIFT (16U) +/*! OREG_SIZE - Output Register Size + * 0b00000001..One word (this value is fixed) + */ #define RNG_SR_OREG_SIZE(x) (((uint32_t)(((uint32_t)(x)) << RNG_SR_OREG_SIZE_SHIFT)) & RNG_SR_OREG_SIZE_MASK) +/*! @} */ /*! @name ER - RNGA Entropy Register */ +/*! @{ */ #define RNG_ER_EXT_ENT_MASK (0xFFFFFFFFU) #define RNG_ER_EXT_ENT_SHIFT (0U) #define RNG_ER_EXT_ENT(x) (((uint32_t)(((uint32_t)(x)) << RNG_ER_EXT_ENT_SHIFT)) & RNG_ER_EXT_ENT_MASK) +/*! @} */ /*! @name OR - RNGA Output Register */ +/*! @{ */ #define RNG_OR_RANDOUT_MASK (0xFFFFFFFFU) #define RNG_OR_RANDOUT_SHIFT (0U) +/*! RANDOUT - Random Output + * 0b00000000000000000000000000000000..Invalid data (if you read this field when it is 0 and SR[OREG_LVL] is 0, RNGA then writes 1 to SR[ERRI], SR[ORU], and SR[LRS]; when the error interrupt is not masked (CR[INTM]=0), RNGA also asserts an error interrupt request to the interrupt controller). + */ #define RNG_OR_RANDOUT(x) (((uint32_t)(((uint32_t)(x)) << RNG_OR_RANDOUT_SHIFT)) & RNG_OR_RANDOUT_MASK) +/*! @} */ /*! @@ -9379,23 +16319,37 @@ typedef struct { */ /*! @name TSR - RTC Time Seconds Register */ +/*! @{ */ #define RTC_TSR_TSR_MASK (0xFFFFFFFFU) #define RTC_TSR_TSR_SHIFT (0U) #define RTC_TSR_TSR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TSR_TSR_SHIFT)) & RTC_TSR_TSR_MASK) +/*! @} */ /*! @name TPR - RTC Time Prescaler Register */ +/*! @{ */ #define RTC_TPR_TPR_MASK (0xFFFFU) #define RTC_TPR_TPR_SHIFT (0U) #define RTC_TPR_TPR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TPR_TPR_SHIFT)) & RTC_TPR_TPR_MASK) +/*! @} */ /*! @name TAR - RTC Time Alarm Register */ +/*! @{ */ #define RTC_TAR_TAR_MASK (0xFFFFFFFFU) #define RTC_TAR_TAR_SHIFT (0U) #define RTC_TAR_TAR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TAR_TAR_SHIFT)) & RTC_TAR_TAR_MASK) +/*! @} */ /*! @name TCR - RTC Time Compensation Register */ +/*! @{ */ #define RTC_TCR_TCR_MASK (0xFFU) #define RTC_TCR_TCR_SHIFT (0U) +/*! TCR - Time Compensation Register + * 0b10000000..Time Prescaler Register overflows every 32896 clock cycles. + * 0b11111111..Time Prescaler Register overflows every 32769 clock cycles. + * 0b00000000..Time Prescaler Register overflows every 32768 clock cycles. + * 0b00000001..Time Prescaler Register overflows every 32767 clock cycles. + * 0b01111111..Time Prescaler Register overflows every 32641 clock cycles. + */ #define RTC_TCR_TCR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TCR_TCR_SHIFT)) & RTC_TCR_TCR_MASK) #define RTC_TCR_CIR_MASK (0xFF00U) #define RTC_TCR_CIR_SHIFT (8U) @@ -9406,138 +16360,311 @@ typedef struct { #define RTC_TCR_CIC_MASK (0xFF000000U) #define RTC_TCR_CIC_SHIFT (24U) #define RTC_TCR_CIC(x) (((uint32_t)(((uint32_t)(x)) << RTC_TCR_CIC_SHIFT)) & RTC_TCR_CIC_MASK) +/*! @} */ /*! @name CR - RTC Control Register */ +/*! @{ */ #define RTC_CR_SWR_MASK (0x1U) #define RTC_CR_SWR_SHIFT (0U) +/*! SWR - Software Reset + * 0b0..No effect. + * 0b1..Resets all RTC registers except for the SWR bit and the RTC_WAR and RTC_RAR registers . The SWR bit is cleared by VBAT POR and by software explicitly clearing it. + */ #define RTC_CR_SWR(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SWR_SHIFT)) & RTC_CR_SWR_MASK) #define RTC_CR_WPE_MASK (0x2U) #define RTC_CR_WPE_SHIFT (1U) +/*! WPE - Wakeup Pin Enable + * 0b0..Wakeup pin is disabled. + * 0b1..Wakeup pin is enabled and wakeup pin asserts if the RTC interrupt asserts or the wakeup pin is turned on. + */ #define RTC_CR_WPE(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_WPE_SHIFT)) & RTC_CR_WPE_MASK) #define RTC_CR_SUP_MASK (0x4U) #define RTC_CR_SUP_SHIFT (2U) +/*! SUP - Supervisor Access + * 0b0..Non-supervisor mode write accesses are not supported and generate a bus error. + * 0b1..Non-supervisor mode write accesses are supported. + */ #define RTC_CR_SUP(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SUP_SHIFT)) & RTC_CR_SUP_MASK) #define RTC_CR_UM_MASK (0x8U) #define RTC_CR_UM_SHIFT (3U) +/*! UM - Update Mode + * 0b0..Registers cannot be written when locked. + * 0b1..Registers can be written when locked under limited conditions. + */ #define RTC_CR_UM(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_UM_SHIFT)) & RTC_CR_UM_MASK) #define RTC_CR_WPS_MASK (0x10U) #define RTC_CR_WPS_SHIFT (4U) +/*! WPS - Wakeup Pin Select + * 0b0..Wakeup pin asserts (active low, open drain) if the RTC interrupt asserts or the wakeup pin is turned on. + * 0b1..Wakeup pin instead outputs the RTC 32kHz clock, provided the wakeup pin is turned on and the 32kHz clock is output to other peripherals. + */ #define RTC_CR_WPS(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_WPS_SHIFT)) & RTC_CR_WPS_MASK) #define RTC_CR_OSCE_MASK (0x100U) #define RTC_CR_OSCE_SHIFT (8U) +/*! OSCE - Oscillator Enable + * 0b0..32.768 kHz oscillator is disabled. + * 0b1..32.768 kHz oscillator is enabled. After setting this bit, wait the oscillator startup time before enabling the time counter to allow the 32.768 kHz clock time to stabilize. + */ #define RTC_CR_OSCE(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_OSCE_SHIFT)) & RTC_CR_OSCE_MASK) #define RTC_CR_CLKO_MASK (0x200U) #define RTC_CR_CLKO_SHIFT (9U) +/*! CLKO - Clock Output + * 0b0..The 32 kHz clock is output to other peripherals. + * 0b1..The 32 kHz clock is not output to other peripherals. + */ #define RTC_CR_CLKO(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_CLKO_SHIFT)) & RTC_CR_CLKO_MASK) #define RTC_CR_SC16P_MASK (0x400U) #define RTC_CR_SC16P_SHIFT (10U) +/*! SC16P - Oscillator 16pF Load Configure + * 0b0..Disable the load. + * 0b1..Enable the additional load. + */ #define RTC_CR_SC16P(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC16P_SHIFT)) & RTC_CR_SC16P_MASK) #define RTC_CR_SC8P_MASK (0x800U) #define RTC_CR_SC8P_SHIFT (11U) +/*! SC8P - Oscillator 8pF Load Configure + * 0b0..Disable the load. + * 0b1..Enable the additional load. + */ #define RTC_CR_SC8P(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC8P_SHIFT)) & RTC_CR_SC8P_MASK) #define RTC_CR_SC4P_MASK (0x1000U) #define RTC_CR_SC4P_SHIFT (12U) +/*! SC4P - Oscillator 4pF Load Configure + * 0b0..Disable the load. + * 0b1..Enable the additional load. + */ #define RTC_CR_SC4P(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC4P_SHIFT)) & RTC_CR_SC4P_MASK) #define RTC_CR_SC2P_MASK (0x2000U) #define RTC_CR_SC2P_SHIFT (13U) +/*! SC2P - Oscillator 2pF Load Configure + * 0b0..Disable the load. + * 0b1..Enable the additional load. + */ #define RTC_CR_SC2P(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC2P_SHIFT)) & RTC_CR_SC2P_MASK) +/*! @} */ /*! @name SR - RTC Status Register */ +/*! @{ */ #define RTC_SR_TIF_MASK (0x1U) #define RTC_SR_TIF_SHIFT (0U) +/*! TIF - Time Invalid Flag + * 0b0..Time is valid. + * 0b1..Time is invalid and time counter is read as zero. + */ #define RTC_SR_TIF(x) (((uint32_t)(((uint32_t)(x)) << RTC_SR_TIF_SHIFT)) & RTC_SR_TIF_MASK) #define RTC_SR_TOF_MASK (0x2U) #define RTC_SR_TOF_SHIFT (1U) +/*! TOF - Time Overflow Flag + * 0b0..Time overflow has not occurred. + * 0b1..Time overflow has occurred and time counter is read as zero. + */ #define RTC_SR_TOF(x) (((uint32_t)(((uint32_t)(x)) << RTC_SR_TOF_SHIFT)) & RTC_SR_TOF_MASK) #define RTC_SR_TAF_MASK (0x4U) #define RTC_SR_TAF_SHIFT (2U) +/*! TAF - Time Alarm Flag + * 0b0..Time alarm has not occurred. + * 0b1..Time alarm has occurred. + */ #define RTC_SR_TAF(x) (((uint32_t)(((uint32_t)(x)) << RTC_SR_TAF_SHIFT)) & RTC_SR_TAF_MASK) #define RTC_SR_TCE_MASK (0x10U) #define RTC_SR_TCE_SHIFT (4U) +/*! TCE - Time Counter Enable + * 0b0..Time counter is disabled. + * 0b1..Time counter is enabled. + */ #define RTC_SR_TCE(x) (((uint32_t)(((uint32_t)(x)) << RTC_SR_TCE_SHIFT)) & RTC_SR_TCE_MASK) +/*! @} */ /*! @name LR - RTC Lock Register */ +/*! @{ */ #define RTC_LR_TCL_MASK (0x8U) #define RTC_LR_TCL_SHIFT (3U) +/*! TCL - Time Compensation Lock + * 0b0..Time Compensation Register is locked and writes are ignored. + * 0b1..Time Compensation Register is not locked and writes complete as normal. + */ #define RTC_LR_TCL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_TCL_SHIFT)) & RTC_LR_TCL_MASK) #define RTC_LR_CRL_MASK (0x10U) #define RTC_LR_CRL_SHIFT (4U) +/*! CRL - Control Register Lock + * 0b0..Control Register is locked and writes are ignored. + * 0b1..Control Register is not locked and writes complete as normal. + */ #define RTC_LR_CRL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_CRL_SHIFT)) & RTC_LR_CRL_MASK) #define RTC_LR_SRL_MASK (0x20U) #define RTC_LR_SRL_SHIFT (5U) +/*! SRL - Status Register Lock + * 0b0..Status Register is locked and writes are ignored. + * 0b1..Status Register is not locked and writes complete as normal. + */ #define RTC_LR_SRL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_SRL_SHIFT)) & RTC_LR_SRL_MASK) #define RTC_LR_LRL_MASK (0x40U) #define RTC_LR_LRL_SHIFT (6U) +/*! LRL - Lock Register Lock + * 0b0..Lock Register is locked and writes are ignored. + * 0b1..Lock Register is not locked and writes complete as normal. + */ #define RTC_LR_LRL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_LRL_SHIFT)) & RTC_LR_LRL_MASK) +/*! @} */ /*! @name IER - RTC Interrupt Enable Register */ +/*! @{ */ #define RTC_IER_TIIE_MASK (0x1U) #define RTC_IER_TIIE_SHIFT (0U) +/*! TIIE - Time Invalid Interrupt Enable + * 0b0..Time invalid flag does not generate an interrupt. + * 0b1..Time invalid flag does generate an interrupt. + */ #define RTC_IER_TIIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_TIIE_SHIFT)) & RTC_IER_TIIE_MASK) #define RTC_IER_TOIE_MASK (0x2U) #define RTC_IER_TOIE_SHIFT (1U) +/*! TOIE - Time Overflow Interrupt Enable + * 0b0..Time overflow flag does not generate an interrupt. + * 0b1..Time overflow flag does generate an interrupt. + */ #define RTC_IER_TOIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_TOIE_SHIFT)) & RTC_IER_TOIE_MASK) #define RTC_IER_TAIE_MASK (0x4U) #define RTC_IER_TAIE_SHIFT (2U) +/*! TAIE - Time Alarm Interrupt Enable + * 0b0..Time alarm flag does not generate an interrupt. + * 0b1..Time alarm flag does generate an interrupt. + */ #define RTC_IER_TAIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_TAIE_SHIFT)) & RTC_IER_TAIE_MASK) #define RTC_IER_TSIE_MASK (0x10U) #define RTC_IER_TSIE_SHIFT (4U) +/*! TSIE - Time Seconds Interrupt Enable + * 0b0..Seconds interrupt is disabled. + * 0b1..Seconds interrupt is enabled. + */ #define RTC_IER_TSIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_TSIE_SHIFT)) & RTC_IER_TSIE_MASK) #define RTC_IER_WPON_MASK (0x80U) #define RTC_IER_WPON_SHIFT (7U) +/*! WPON - Wakeup Pin On + * 0b0..No effect. + * 0b1..If the wakeup pin is enabled, then the wakeup pin will assert. + */ #define RTC_IER_WPON(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_WPON_SHIFT)) & RTC_IER_WPON_MASK) +/*! @} */ /*! @name WAR - RTC Write Access Register */ +/*! @{ */ #define RTC_WAR_TSRW_MASK (0x1U) #define RTC_WAR_TSRW_SHIFT (0U) +/*! TSRW - Time Seconds Register Write + * 0b0..Writes to the Time Seconds Register are ignored. + * 0b1..Writes to the Time Seconds Register complete as normal. + */ #define RTC_WAR_TSRW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_TSRW_SHIFT)) & RTC_WAR_TSRW_MASK) #define RTC_WAR_TPRW_MASK (0x2U) #define RTC_WAR_TPRW_SHIFT (1U) +/*! TPRW - Time Prescaler Register Write + * 0b0..Writes to the Time Prescaler Register are ignored. + * 0b1..Writes to the Time Prescaler Register complete as normal. + */ #define RTC_WAR_TPRW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_TPRW_SHIFT)) & RTC_WAR_TPRW_MASK) #define RTC_WAR_TARW_MASK (0x4U) #define RTC_WAR_TARW_SHIFT (2U) +/*! TARW - Time Alarm Register Write + * 0b0..Writes to the Time Alarm Register are ignored. + * 0b1..Writes to the Time Alarm Register complete as normal. + */ #define RTC_WAR_TARW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_TARW_SHIFT)) & RTC_WAR_TARW_MASK) #define RTC_WAR_TCRW_MASK (0x8U) #define RTC_WAR_TCRW_SHIFT (3U) +/*! TCRW - Time Compensation Register Write + * 0b0..Writes to the Time Compensation Register are ignored. + * 0b1..Writes to the Time Compensation Register complete as normal. + */ #define RTC_WAR_TCRW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_TCRW_SHIFT)) & RTC_WAR_TCRW_MASK) #define RTC_WAR_CRW_MASK (0x10U) #define RTC_WAR_CRW_SHIFT (4U) +/*! CRW - Control Register Write + * 0b0..Writes to the Control Register are ignored. + * 0b1..Writes to the Control Register complete as normal. + */ #define RTC_WAR_CRW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_CRW_SHIFT)) & RTC_WAR_CRW_MASK) #define RTC_WAR_SRW_MASK (0x20U) #define RTC_WAR_SRW_SHIFT (5U) +/*! SRW - Status Register Write + * 0b0..Writes to the Status Register are ignored. + * 0b1..Writes to the Status Register complete as normal. + */ #define RTC_WAR_SRW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_SRW_SHIFT)) & RTC_WAR_SRW_MASK) #define RTC_WAR_LRW_MASK (0x40U) #define RTC_WAR_LRW_SHIFT (6U) +/*! LRW - Lock Register Write + * 0b0..Writes to the Lock Register are ignored. + * 0b1..Writes to the Lock Register complete as normal. + */ #define RTC_WAR_LRW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_LRW_SHIFT)) & RTC_WAR_LRW_MASK) #define RTC_WAR_IERW_MASK (0x80U) #define RTC_WAR_IERW_SHIFT (7U) +/*! IERW - Interrupt Enable Register Write + * 0b0..Writes to the Interupt Enable Register are ignored. + * 0b1..Writes to the Interrupt Enable Register complete as normal. + */ #define RTC_WAR_IERW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_IERW_SHIFT)) & RTC_WAR_IERW_MASK) +/*! @} */ /*! @name RAR - RTC Read Access Register */ +/*! @{ */ #define RTC_RAR_TSRR_MASK (0x1U) #define RTC_RAR_TSRR_SHIFT (0U) +/*! TSRR - Time Seconds Register Read + * 0b0..Reads to the Time Seconds Register are ignored. + * 0b1..Reads to the Time Seconds Register complete as normal. + */ #define RTC_RAR_TSRR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_TSRR_SHIFT)) & RTC_RAR_TSRR_MASK) #define RTC_RAR_TPRR_MASK (0x2U) #define RTC_RAR_TPRR_SHIFT (1U) +/*! TPRR - Time Prescaler Register Read + * 0b0..Reads to the Time Pprescaler Register are ignored. + * 0b1..Reads to the Time Prescaler Register complete as normal. + */ #define RTC_RAR_TPRR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_TPRR_SHIFT)) & RTC_RAR_TPRR_MASK) #define RTC_RAR_TARR_MASK (0x4U) #define RTC_RAR_TARR_SHIFT (2U) +/*! TARR - Time Alarm Register Read + * 0b0..Reads to the Time Alarm Register are ignored. + * 0b1..Reads to the Time Alarm Register complete as normal. + */ #define RTC_RAR_TARR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_TARR_SHIFT)) & RTC_RAR_TARR_MASK) #define RTC_RAR_TCRR_MASK (0x8U) #define RTC_RAR_TCRR_SHIFT (3U) +/*! TCRR - Time Compensation Register Read + * 0b0..Reads to the Time Compensation Register are ignored. + * 0b1..Reads to the Time Compensation Register complete as normal. + */ #define RTC_RAR_TCRR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_TCRR_SHIFT)) & RTC_RAR_TCRR_MASK) #define RTC_RAR_CRR_MASK (0x10U) #define RTC_RAR_CRR_SHIFT (4U) +/*! CRR - Control Register Read + * 0b0..Reads to the Control Register are ignored. + * 0b1..Reads to the Control Register complete as normal. + */ #define RTC_RAR_CRR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_CRR_SHIFT)) & RTC_RAR_CRR_MASK) #define RTC_RAR_SRR_MASK (0x20U) #define RTC_RAR_SRR_SHIFT (5U) +/*! SRR - Status Register Read + * 0b0..Reads to the Status Register are ignored. + * 0b1..Reads to the Status Register complete as normal. + */ #define RTC_RAR_SRR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_SRR_SHIFT)) & RTC_RAR_SRR_MASK) #define RTC_RAR_LRR_MASK (0x40U) #define RTC_RAR_LRR_SHIFT (6U) +/*! LRR - Lock Register Read + * 0b0..Reads to the Lock Register are ignored. + * 0b1..Reads to the Lock Register complete as normal. + */ #define RTC_RAR_LRR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_LRR_SHIFT)) & RTC_RAR_LRR_MASK) #define RTC_RAR_IERR_MASK (0x80U) #define RTC_RAR_IERR_SHIFT (7U) +/*! IERR - Interrupt Enable Register Read + * 0b0..Reads to the Interrupt Enable Register are ignored. + * 0b1..Reads to the Interrupt Enable Register complete as normal. + */ #define RTC_RAR_IERR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_IERR_SHIFT)) & RTC_RAR_IERR_MASK) +/*! @} */ /*! @@ -9610,59 +16737,129 @@ typedef struct { */ /*! @name DSADDR - DMA System Address register */ +/*! @{ */ #define SDHC_DSADDR_DSADDR_MASK (0xFFFFFFFCU) #define SDHC_DSADDR_DSADDR_SHIFT (2U) #define SDHC_DSADDR_DSADDR(x) (((uint32_t)(((uint32_t)(x)) << SDHC_DSADDR_DSADDR_SHIFT)) & SDHC_DSADDR_DSADDR_MASK) +/*! @} */ /*! @name BLKATTR - Block Attributes register */ +/*! @{ */ #define SDHC_BLKATTR_BLKSIZE_MASK (0x1FFFU) #define SDHC_BLKATTR_BLKSIZE_SHIFT (0U) +/*! BLKSIZE - Transfer Block Size + * 0b0000000000000..No data transfer. + * 0b0000000000001..1 Byte + * 0b0000000000010..2 Bytes + * 0b0000000000011..3 Bytes + * 0b0000000000100..4 Bytes + * 0b0000111111111..511 Bytes + * 0b0001000000000..512 Bytes + * 0b0100000000000..2048 Bytes + * 0b1000000000000..4096 Bytes + */ #define SDHC_BLKATTR_BLKSIZE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_BLKATTR_BLKSIZE_SHIFT)) & SDHC_BLKATTR_BLKSIZE_MASK) #define SDHC_BLKATTR_BLKCNT_MASK (0xFFFF0000U) #define SDHC_BLKATTR_BLKCNT_SHIFT (16U) +/*! BLKCNT - Blocks Count For Current Transfer + * 0b0000000000000000..Stop count. + * 0b0000000000000001..1 block + * 0b0000000000000010..2 blocks + * 0b1111111111111111..65535 blocks + */ #define SDHC_BLKATTR_BLKCNT(x) (((uint32_t)(((uint32_t)(x)) << SDHC_BLKATTR_BLKCNT_SHIFT)) & SDHC_BLKATTR_BLKCNT_MASK) +/*! @} */ /*! @name CMDARG - Command Argument register */ +/*! @{ */ #define SDHC_CMDARG_CMDARG_MASK (0xFFFFFFFFU) #define SDHC_CMDARG_CMDARG_SHIFT (0U) #define SDHC_CMDARG_CMDARG(x) (((uint32_t)(((uint32_t)(x)) << SDHC_CMDARG_CMDARG_SHIFT)) & SDHC_CMDARG_CMDARG_MASK) +/*! @} */ /*! @name XFERTYP - Transfer Type register */ +/*! @{ */ #define SDHC_XFERTYP_DMAEN_MASK (0x1U) #define SDHC_XFERTYP_DMAEN_SHIFT (0U) +/*! DMAEN - DMA Enable + * 0b0..Disable + * 0b1..Enable + */ #define SDHC_XFERTYP_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_DMAEN_SHIFT)) & SDHC_XFERTYP_DMAEN_MASK) #define SDHC_XFERTYP_BCEN_MASK (0x2U) #define SDHC_XFERTYP_BCEN_SHIFT (1U) +/*! BCEN - Block Count Enable + * 0b0..Disable + * 0b1..Enable + */ #define SDHC_XFERTYP_BCEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_BCEN_SHIFT)) & SDHC_XFERTYP_BCEN_MASK) #define SDHC_XFERTYP_AC12EN_MASK (0x4U) #define SDHC_XFERTYP_AC12EN_SHIFT (2U) +/*! AC12EN - Auto CMD12 Enable + * 0b0..Disable + * 0b1..Enable + */ #define SDHC_XFERTYP_AC12EN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_AC12EN_SHIFT)) & SDHC_XFERTYP_AC12EN_MASK) #define SDHC_XFERTYP_DTDSEL_MASK (0x10U) #define SDHC_XFERTYP_DTDSEL_SHIFT (4U) +/*! DTDSEL - Data Transfer Direction Select + * 0b0..Write host to card. + * 0b1..Read card to host. + */ #define SDHC_XFERTYP_DTDSEL(x) (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_DTDSEL_SHIFT)) & SDHC_XFERTYP_DTDSEL_MASK) #define SDHC_XFERTYP_MSBSEL_MASK (0x20U) #define SDHC_XFERTYP_MSBSEL_SHIFT (5U) +/*! MSBSEL - Multi/Single Block Select + * 0b0..Single block. + * 0b1..Multiple blocks. + */ #define SDHC_XFERTYP_MSBSEL(x) (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_MSBSEL_SHIFT)) & SDHC_XFERTYP_MSBSEL_MASK) #define SDHC_XFERTYP_RSPTYP_MASK (0x30000U) #define SDHC_XFERTYP_RSPTYP_SHIFT (16U) +/*! RSPTYP - Response Type Select + * 0b00..No response. + * 0b01..Response length 136. + * 0b10..Response length 48. + * 0b11..Response length 48, check busy after response. + */ #define SDHC_XFERTYP_RSPTYP(x) (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_RSPTYP_SHIFT)) & SDHC_XFERTYP_RSPTYP_MASK) #define SDHC_XFERTYP_CCCEN_MASK (0x80000U) #define SDHC_XFERTYP_CCCEN_SHIFT (19U) +/*! CCCEN - Command CRC Check Enable + * 0b0..Disable + * 0b1..Enable + */ #define SDHC_XFERTYP_CCCEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_CCCEN_SHIFT)) & SDHC_XFERTYP_CCCEN_MASK) #define SDHC_XFERTYP_CICEN_MASK (0x100000U) #define SDHC_XFERTYP_CICEN_SHIFT (20U) +/*! CICEN - Command Index Check Enable + * 0b0..Disable + * 0b1..Enable + */ #define SDHC_XFERTYP_CICEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_CICEN_SHIFT)) & SDHC_XFERTYP_CICEN_MASK) #define SDHC_XFERTYP_DPSEL_MASK (0x200000U) #define SDHC_XFERTYP_DPSEL_SHIFT (21U) +/*! DPSEL - Data Present Select + * 0b0..No data present. + * 0b1..Data present. + */ #define SDHC_XFERTYP_DPSEL(x) (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_DPSEL_SHIFT)) & SDHC_XFERTYP_DPSEL_MASK) #define SDHC_XFERTYP_CMDTYP_MASK (0xC00000U) #define SDHC_XFERTYP_CMDTYP_SHIFT (22U) +/*! CMDTYP - Command Type + * 0b00..Normal other commands. + * 0b01..Suspend CMD52 for writing bus suspend in CCCR. + * 0b10..Resume CMD52 for writing function select in CCCR. + * 0b11..Abort CMD12, CMD52 for writing I/O abort in CCCR. + */ #define SDHC_XFERTYP_CMDTYP(x) (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_CMDTYP_SHIFT)) & SDHC_XFERTYP_CMDTYP_MASK) #define SDHC_XFERTYP_CMDINX_MASK (0x3F000000U) #define SDHC_XFERTYP_CMDINX_SHIFT (24U) #define SDHC_XFERTYP_CMDINX(x) (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_CMDINX_SHIFT)) & SDHC_XFERTYP_CMDINX_MASK) +/*! @} */ /*! @name CMDRSP - Command Response 0..Command Response 3 */ +/*! @{ */ #define SDHC_CMDRSP_CMDRSP0_MASK (0xFFFFFFFFU) #define SDHC_CMDRSP_CMDRSP0_SHIFT (0U) #define SDHC_CMDRSP_CMDRSP0(x) (((uint32_t)(((uint32_t)(x)) << SDHC_CMDRSP_CMDRSP0_SHIFT)) & SDHC_CMDRSP_CMDRSP0_MASK) @@ -9675,54 +16872,110 @@ typedef struct { #define SDHC_CMDRSP_CMDRSP3_MASK (0xFFFFFFFFU) #define SDHC_CMDRSP_CMDRSP3_SHIFT (0U) #define SDHC_CMDRSP_CMDRSP3(x) (((uint32_t)(((uint32_t)(x)) << SDHC_CMDRSP_CMDRSP3_SHIFT)) & SDHC_CMDRSP_CMDRSP3_MASK) +/*! @} */ /* The count of SDHC_CMDRSP */ #define SDHC_CMDRSP_COUNT (4U) /*! @name DATPORT - Buffer Data Port register */ +/*! @{ */ #define SDHC_DATPORT_DATCONT_MASK (0xFFFFFFFFU) #define SDHC_DATPORT_DATCONT_SHIFT (0U) #define SDHC_DATPORT_DATCONT(x) (((uint32_t)(((uint32_t)(x)) << SDHC_DATPORT_DATCONT_SHIFT)) & SDHC_DATPORT_DATCONT_MASK) +/*! @} */ /*! @name PRSSTAT - Present State register */ +/*! @{ */ #define SDHC_PRSSTAT_CIHB_MASK (0x1U) #define SDHC_PRSSTAT_CIHB_SHIFT (0U) +/*! CIHB - Command Inhibit (CMD) + * 0b0..Can issue command using only CMD line. + * 0b1..Cannot issue command. + */ #define SDHC_PRSSTAT_CIHB(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_CIHB_SHIFT)) & SDHC_PRSSTAT_CIHB_MASK) #define SDHC_PRSSTAT_CDIHB_MASK (0x2U) #define SDHC_PRSSTAT_CDIHB_SHIFT (1U) +/*! CDIHB - Command Inhibit (DAT) + * 0b0..Can issue command which uses the DAT line. + * 0b1..Cannot issue command which uses the DAT line. + */ #define SDHC_PRSSTAT_CDIHB(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_CDIHB_SHIFT)) & SDHC_PRSSTAT_CDIHB_MASK) #define SDHC_PRSSTAT_DLA_MASK (0x4U) #define SDHC_PRSSTAT_DLA_SHIFT (2U) +/*! DLA - Data Line Active + * 0b0..DAT line inactive. + * 0b1..DAT line active. + */ #define SDHC_PRSSTAT_DLA(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_DLA_SHIFT)) & SDHC_PRSSTAT_DLA_MASK) #define SDHC_PRSSTAT_SDSTB_MASK (0x8U) #define SDHC_PRSSTAT_SDSTB_SHIFT (3U) +/*! SDSTB - SD Clock Stable + * 0b0..Clock is changing frequency and not stable. + * 0b1..Clock is stable. + */ #define SDHC_PRSSTAT_SDSTB(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_SDSTB_SHIFT)) & SDHC_PRSSTAT_SDSTB_MASK) #define SDHC_PRSSTAT_IPGOFF_MASK (0x10U) #define SDHC_PRSSTAT_IPGOFF_SHIFT (4U) +/*! IPGOFF - Bus Clock Gated Off Internally + * 0b0..Bus clock is active. + * 0b1..Bus clock is gated off. + */ #define SDHC_PRSSTAT_IPGOFF(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_IPGOFF_SHIFT)) & SDHC_PRSSTAT_IPGOFF_MASK) #define SDHC_PRSSTAT_HCKOFF_MASK (0x20U) #define SDHC_PRSSTAT_HCKOFF_SHIFT (5U) +/*! HCKOFF - System Clock Gated Off Internally + * 0b0..System clock is active. + * 0b1..System clock is gated off. + */ #define SDHC_PRSSTAT_HCKOFF(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_HCKOFF_SHIFT)) & SDHC_PRSSTAT_HCKOFF_MASK) #define SDHC_PRSSTAT_PEROFF_MASK (0x40U) #define SDHC_PRSSTAT_PEROFF_SHIFT (6U) +/*! PEROFF - SDHC clock Gated Off Internally + * 0b0..SDHC clock is active. + * 0b1..SDHC clock is gated off. + */ #define SDHC_PRSSTAT_PEROFF(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_PEROFF_SHIFT)) & SDHC_PRSSTAT_PEROFF_MASK) #define SDHC_PRSSTAT_SDOFF_MASK (0x80U) #define SDHC_PRSSTAT_SDOFF_SHIFT (7U) +/*! SDOFF - SD Clock Gated Off Internally + * 0b0..SD clock is active. + * 0b1..SD clock is gated off. + */ #define SDHC_PRSSTAT_SDOFF(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_SDOFF_SHIFT)) & SDHC_PRSSTAT_SDOFF_MASK) #define SDHC_PRSSTAT_WTA_MASK (0x100U) #define SDHC_PRSSTAT_WTA_SHIFT (8U) +/*! WTA - Write Transfer Active + * 0b0..No valid data. + * 0b1..Transferring data. + */ #define SDHC_PRSSTAT_WTA(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_WTA_SHIFT)) & SDHC_PRSSTAT_WTA_MASK) #define SDHC_PRSSTAT_RTA_MASK (0x200U) #define SDHC_PRSSTAT_RTA_SHIFT (9U) +/*! RTA - Read Transfer Active + * 0b0..No valid data. + * 0b1..Transferring data. + */ #define SDHC_PRSSTAT_RTA(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_RTA_SHIFT)) & SDHC_PRSSTAT_RTA_MASK) #define SDHC_PRSSTAT_BWEN_MASK (0x400U) #define SDHC_PRSSTAT_BWEN_SHIFT (10U) +/*! BWEN - Buffer Write Enable + * 0b0..Write disable, the buffer can hold valid data less than the write watermark level. + * 0b1..Write enable, the buffer can hold valid data greater than the write watermark level. + */ #define SDHC_PRSSTAT_BWEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_BWEN_SHIFT)) & SDHC_PRSSTAT_BWEN_MASK) #define SDHC_PRSSTAT_BREN_MASK (0x800U) #define SDHC_PRSSTAT_BREN_SHIFT (11U) +/*! BREN - Buffer Read Enable + * 0b0..Read disable, valid data less than the watermark level exist in the buffer. + * 0b1..Read enable, valid data greater than the watermark level exist in the buffer. + */ #define SDHC_PRSSTAT_BREN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_BREN_SHIFT)) & SDHC_PRSSTAT_BREN_MASK) #define SDHC_PRSSTAT_CINS_MASK (0x10000U) #define SDHC_PRSSTAT_CINS_SHIFT (16U) +/*! CINS - Card Inserted + * 0b0..Power on reset or no card. + * 0b1..Card inserted. + */ #define SDHC_PRSSTAT_CINS(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_CINS_SHIFT)) & SDHC_PRSSTAT_CINS_MASK) #define SDHC_PRSSTAT_CLSL_MASK (0x800000U) #define SDHC_PRSSTAT_CLSL_SHIFT (23U) @@ -9730,303 +16983,695 @@ typedef struct { #define SDHC_PRSSTAT_DLSL_MASK (0xFF000000U) #define SDHC_PRSSTAT_DLSL_SHIFT (24U) #define SDHC_PRSSTAT_DLSL(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_DLSL_SHIFT)) & SDHC_PRSSTAT_DLSL_MASK) +/*! @} */ /*! @name PROCTL - Protocol Control register */ +/*! @{ */ #define SDHC_PROCTL_LCTL_MASK (0x1U) #define SDHC_PROCTL_LCTL_SHIFT (0U) +/*! LCTL - LED Control + * 0b0..LED off. + * 0b1..LED on. + */ #define SDHC_PROCTL_LCTL(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_LCTL_SHIFT)) & SDHC_PROCTL_LCTL_MASK) #define SDHC_PROCTL_DTW_MASK (0x6U) #define SDHC_PROCTL_DTW_SHIFT (1U) +/*! DTW - Data Transfer Width + * 0b00..1-bit mode + * 0b01..4-bit mode + * 0b10..8-bit mode + * 0b11..Reserved + */ #define SDHC_PROCTL_DTW(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_DTW_SHIFT)) & SDHC_PROCTL_DTW_MASK) #define SDHC_PROCTL_D3CD_MASK (0x8U) #define SDHC_PROCTL_D3CD_SHIFT (3U) +/*! D3CD - DAT3 As Card Detection Pin + * 0b0..DAT3 does not monitor card Insertion. + * 0b1..DAT3 as card detection pin. + */ #define SDHC_PROCTL_D3CD(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_D3CD_SHIFT)) & SDHC_PROCTL_D3CD_MASK) #define SDHC_PROCTL_EMODE_MASK (0x30U) #define SDHC_PROCTL_EMODE_SHIFT (4U) +/*! EMODE - Endian Mode + * 0b00..Big endian mode + * 0b01..Half word big endian mode + * 0b10..Little endian mode + * 0b11..Reserved + */ #define SDHC_PROCTL_EMODE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_EMODE_SHIFT)) & SDHC_PROCTL_EMODE_MASK) #define SDHC_PROCTL_CDTL_MASK (0x40U) #define SDHC_PROCTL_CDTL_SHIFT (6U) +/*! CDTL - Card Detect Test Level + * 0b0..Card detect test level is 0, no card inserted. + * 0b1..Card detect test level is 1, card inserted. + */ #define SDHC_PROCTL_CDTL(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_CDTL_SHIFT)) & SDHC_PROCTL_CDTL_MASK) #define SDHC_PROCTL_CDSS_MASK (0x80U) #define SDHC_PROCTL_CDSS_SHIFT (7U) +/*! CDSS - Card Detect Signal Selection + * 0b0..Card detection level is selected for normal purpose. + * 0b1..Card detection test level is selected for test purpose. + */ #define SDHC_PROCTL_CDSS(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_CDSS_SHIFT)) & SDHC_PROCTL_CDSS_MASK) #define SDHC_PROCTL_DMAS_MASK (0x300U) #define SDHC_PROCTL_DMAS_SHIFT (8U) +/*! DMAS - DMA Select + * 0b00..No DMA or simple DMA is selected. + * 0b01..ADMA1 is selected. + * 0b10..ADMA2 is selected. + * 0b11..Reserved + */ #define SDHC_PROCTL_DMAS(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_DMAS_SHIFT)) & SDHC_PROCTL_DMAS_MASK) #define SDHC_PROCTL_SABGREQ_MASK (0x10000U) #define SDHC_PROCTL_SABGREQ_SHIFT (16U) +/*! SABGREQ - Stop At Block Gap Request + * 0b0..Transfer + * 0b1..Stop + */ #define SDHC_PROCTL_SABGREQ(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_SABGREQ_SHIFT)) & SDHC_PROCTL_SABGREQ_MASK) #define SDHC_PROCTL_CREQ_MASK (0x20000U) #define SDHC_PROCTL_CREQ_SHIFT (17U) +/*! CREQ - Continue Request + * 0b0..No effect. + * 0b1..Restart + */ #define SDHC_PROCTL_CREQ(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_CREQ_SHIFT)) & SDHC_PROCTL_CREQ_MASK) #define SDHC_PROCTL_RWCTL_MASK (0x40000U) #define SDHC_PROCTL_RWCTL_SHIFT (18U) +/*! RWCTL - Read Wait Control + * 0b0..Disable read wait control, and stop SD clock at block gap when SABGREQ is set. + * 0b1..Enable read wait control, and assert read wait without stopping SD clock at block gap when SABGREQ bit is set. + */ #define SDHC_PROCTL_RWCTL(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_RWCTL_SHIFT)) & SDHC_PROCTL_RWCTL_MASK) #define SDHC_PROCTL_IABG_MASK (0x80000U) #define SDHC_PROCTL_IABG_SHIFT (19U) +/*! IABG - Interrupt At Block Gap + * 0b0..Disabled + * 0b1..Enabled + */ #define SDHC_PROCTL_IABG(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_IABG_SHIFT)) & SDHC_PROCTL_IABG_MASK) #define SDHC_PROCTL_WECINT_MASK (0x1000000U) #define SDHC_PROCTL_WECINT_SHIFT (24U) +/*! WECINT - Wakeup Event Enable On Card Interrupt + * 0b0..Disabled + * 0b1..Enabled + */ #define SDHC_PROCTL_WECINT(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_WECINT_SHIFT)) & SDHC_PROCTL_WECINT_MASK) #define SDHC_PROCTL_WECINS_MASK (0x2000000U) #define SDHC_PROCTL_WECINS_SHIFT (25U) +/*! WECINS - Wakeup Event Enable On SD Card Insertion + * 0b0..Disabled + * 0b1..Enabled + */ #define SDHC_PROCTL_WECINS(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_WECINS_SHIFT)) & SDHC_PROCTL_WECINS_MASK) #define SDHC_PROCTL_WECRM_MASK (0x4000000U) #define SDHC_PROCTL_WECRM_SHIFT (26U) +/*! WECRM - Wakeup Event Enable On SD Card Removal + * 0b0..Disabled + * 0b1..Enabled + */ #define SDHC_PROCTL_WECRM(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_WECRM_SHIFT)) & SDHC_PROCTL_WECRM_MASK) +/*! @} */ /*! @name SYSCTL - System Control register */ +/*! @{ */ #define SDHC_SYSCTL_IPGEN_MASK (0x1U) #define SDHC_SYSCTL_IPGEN_SHIFT (0U) +/*! IPGEN - IPG Clock Enable + * 0b0..Bus clock will be internally gated off. + * 0b1..Bus clock will not be automatically gated off. + */ #define SDHC_SYSCTL_IPGEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_IPGEN_SHIFT)) & SDHC_SYSCTL_IPGEN_MASK) #define SDHC_SYSCTL_HCKEN_MASK (0x2U) #define SDHC_SYSCTL_HCKEN_SHIFT (1U) +/*! HCKEN - System Clock Enable + * 0b0..System clock will be internally gated off. + * 0b1..System clock will not be automatically gated off. + */ #define SDHC_SYSCTL_HCKEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_HCKEN_SHIFT)) & SDHC_SYSCTL_HCKEN_MASK) #define SDHC_SYSCTL_PEREN_MASK (0x4U) #define SDHC_SYSCTL_PEREN_SHIFT (2U) +/*! PEREN - Peripheral Clock Enable + * 0b0..SDHC clock will be internally gated off. + * 0b1..SDHC clock will not be automatically gated off. + */ #define SDHC_SYSCTL_PEREN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_PEREN_SHIFT)) & SDHC_SYSCTL_PEREN_MASK) #define SDHC_SYSCTL_SDCLKEN_MASK (0x8U) #define SDHC_SYSCTL_SDCLKEN_SHIFT (3U) #define SDHC_SYSCTL_SDCLKEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_SDCLKEN_SHIFT)) & SDHC_SYSCTL_SDCLKEN_MASK) #define SDHC_SYSCTL_DVS_MASK (0xF0U) #define SDHC_SYSCTL_DVS_SHIFT (4U) +/*! DVS - Divisor + * 0b0000..Divisor by 1. + * 0b0001..Divisor by 2. + * 0b1110..Divisor by 15. + * 0b1111..Divisor by 16. + */ #define SDHC_SYSCTL_DVS(x) (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_DVS_SHIFT)) & SDHC_SYSCTL_DVS_MASK) #define SDHC_SYSCTL_SDCLKFS_MASK (0xFF00U) #define SDHC_SYSCTL_SDCLKFS_SHIFT (8U) +/*! SDCLKFS - SDCLK Frequency Select + * 0b00000001..Base clock divided by 2. + * 0b00000010..Base clock divided by 4. + * 0b00000100..Base clock divided by 8. + * 0b00001000..Base clock divided by 16. + * 0b00010000..Base clock divided by 32. + * 0b00100000..Base clock divided by 64. + * 0b01000000..Base clock divided by 128. + * 0b10000000..Base clock divided by 256. + */ #define SDHC_SYSCTL_SDCLKFS(x) (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_SDCLKFS_SHIFT)) & SDHC_SYSCTL_SDCLKFS_MASK) #define SDHC_SYSCTL_DTOCV_MASK (0xF0000U) #define SDHC_SYSCTL_DTOCV_SHIFT (16U) +/*! DTOCV - Data Timeout Counter Value + * 0b0000..SDCLK x 2 13 + * 0b0001..SDCLK x 2 14 + * 0b1110..SDCLK x 2 27 + * 0b1111..Reserved + */ #define SDHC_SYSCTL_DTOCV(x) (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_DTOCV_SHIFT)) & SDHC_SYSCTL_DTOCV_MASK) #define SDHC_SYSCTL_RSTA_MASK (0x1000000U) #define SDHC_SYSCTL_RSTA_SHIFT (24U) +/*! RSTA - Software Reset For ALL + * 0b0..No reset. + * 0b1..Reset. + */ #define SDHC_SYSCTL_RSTA(x) (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_RSTA_SHIFT)) & SDHC_SYSCTL_RSTA_MASK) #define SDHC_SYSCTL_RSTC_MASK (0x2000000U) #define SDHC_SYSCTL_RSTC_SHIFT (25U) +/*! RSTC - Software Reset For CMD Line + * 0b0..No reset. + * 0b1..Reset. + */ #define SDHC_SYSCTL_RSTC(x) (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_RSTC_SHIFT)) & SDHC_SYSCTL_RSTC_MASK) #define SDHC_SYSCTL_RSTD_MASK (0x4000000U) #define SDHC_SYSCTL_RSTD_SHIFT (26U) +/*! RSTD - Software Reset For DAT Line + * 0b0..No reset. + * 0b1..Reset. + */ #define SDHC_SYSCTL_RSTD(x) (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_RSTD_SHIFT)) & SDHC_SYSCTL_RSTD_MASK) #define SDHC_SYSCTL_INITA_MASK (0x8000000U) #define SDHC_SYSCTL_INITA_SHIFT (27U) #define SDHC_SYSCTL_INITA(x) (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_INITA_SHIFT)) & SDHC_SYSCTL_INITA_MASK) +/*! @} */ /*! @name IRQSTAT - Interrupt Status register */ +/*! @{ */ #define SDHC_IRQSTAT_CC_MASK (0x1U) #define SDHC_IRQSTAT_CC_SHIFT (0U) +/*! CC - Command Complete + * 0b0..Command not complete. + * 0b1..Command complete. + */ #define SDHC_IRQSTAT_CC(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CC_SHIFT)) & SDHC_IRQSTAT_CC_MASK) #define SDHC_IRQSTAT_TC_MASK (0x2U) #define SDHC_IRQSTAT_TC_SHIFT (1U) +/*! TC - Transfer Complete + * 0b0..Transfer not complete. + * 0b1..Transfer complete. + */ #define SDHC_IRQSTAT_TC(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_TC_SHIFT)) & SDHC_IRQSTAT_TC_MASK) #define SDHC_IRQSTAT_BGE_MASK (0x4U) #define SDHC_IRQSTAT_BGE_SHIFT (2U) +/*! BGE - Block Gap Event + * 0b0..No block gap event. + * 0b1..Transaction stopped at block gap. + */ #define SDHC_IRQSTAT_BGE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_BGE_SHIFT)) & SDHC_IRQSTAT_BGE_MASK) #define SDHC_IRQSTAT_DINT_MASK (0x8U) #define SDHC_IRQSTAT_DINT_SHIFT (3U) +/*! DINT - DMA Interrupt + * 0b0..No DMA Interrupt. + * 0b1..DMA Interrupt is generated. + */ #define SDHC_IRQSTAT_DINT(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_DINT_SHIFT)) & SDHC_IRQSTAT_DINT_MASK) #define SDHC_IRQSTAT_BWR_MASK (0x10U) #define SDHC_IRQSTAT_BWR_SHIFT (4U) +/*! BWR - Buffer Write Ready + * 0b0..Not ready to write buffer. + * 0b1..Ready to write buffer. + */ #define SDHC_IRQSTAT_BWR(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_BWR_SHIFT)) & SDHC_IRQSTAT_BWR_MASK) #define SDHC_IRQSTAT_BRR_MASK (0x20U) #define SDHC_IRQSTAT_BRR_SHIFT (5U) +/*! BRR - Buffer Read Ready + * 0b0..Not ready to read buffer. + * 0b1..Ready to read buffer. + */ #define SDHC_IRQSTAT_BRR(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_BRR_SHIFT)) & SDHC_IRQSTAT_BRR_MASK) #define SDHC_IRQSTAT_CINS_MASK (0x40U) #define SDHC_IRQSTAT_CINS_SHIFT (6U) +/*! CINS - Card Insertion + * 0b0..Card state unstable or removed. + * 0b1..Card inserted. + */ #define SDHC_IRQSTAT_CINS(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CINS_SHIFT)) & SDHC_IRQSTAT_CINS_MASK) #define SDHC_IRQSTAT_CRM_MASK (0x80U) #define SDHC_IRQSTAT_CRM_SHIFT (7U) +/*! CRM - Card Removal + * 0b0..Card state unstable or inserted. + * 0b1..Card removed. + */ #define SDHC_IRQSTAT_CRM(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CRM_SHIFT)) & SDHC_IRQSTAT_CRM_MASK) #define SDHC_IRQSTAT_CINT_MASK (0x100U) #define SDHC_IRQSTAT_CINT_SHIFT (8U) +/*! CINT - Card Interrupt + * 0b0..No Card Interrupt. + * 0b1..Generate Card Interrupt. + */ #define SDHC_IRQSTAT_CINT(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CINT_SHIFT)) & SDHC_IRQSTAT_CINT_MASK) #define SDHC_IRQSTAT_CTOE_MASK (0x10000U) #define SDHC_IRQSTAT_CTOE_SHIFT (16U) +/*! CTOE - Command Timeout Error + * 0b0..No error. + * 0b1..Time out. + */ #define SDHC_IRQSTAT_CTOE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CTOE_SHIFT)) & SDHC_IRQSTAT_CTOE_MASK) #define SDHC_IRQSTAT_CCE_MASK (0x20000U) #define SDHC_IRQSTAT_CCE_SHIFT (17U) +/*! CCE - Command CRC Error + * 0b0..No error. + * 0b1..CRC Error generated. + */ #define SDHC_IRQSTAT_CCE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CCE_SHIFT)) & SDHC_IRQSTAT_CCE_MASK) #define SDHC_IRQSTAT_CEBE_MASK (0x40000U) #define SDHC_IRQSTAT_CEBE_SHIFT (18U) +/*! CEBE - Command End Bit Error + * 0b0..No error. + * 0b1..End Bit Error generated. + */ #define SDHC_IRQSTAT_CEBE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CEBE_SHIFT)) & SDHC_IRQSTAT_CEBE_MASK) #define SDHC_IRQSTAT_CIE_MASK (0x80000U) #define SDHC_IRQSTAT_CIE_SHIFT (19U) +/*! CIE - Command Index Error + * 0b0..No error. + * 0b1..Error. + */ #define SDHC_IRQSTAT_CIE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CIE_SHIFT)) & SDHC_IRQSTAT_CIE_MASK) #define SDHC_IRQSTAT_DTOE_MASK (0x100000U) #define SDHC_IRQSTAT_DTOE_SHIFT (20U) +/*! DTOE - Data Timeout Error + * 0b0..No error. + * 0b1..Time out. + */ #define SDHC_IRQSTAT_DTOE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_DTOE_SHIFT)) & SDHC_IRQSTAT_DTOE_MASK) #define SDHC_IRQSTAT_DCE_MASK (0x200000U) #define SDHC_IRQSTAT_DCE_SHIFT (21U) +/*! DCE - Data CRC Error + * 0b0..No error. + * 0b1..Error. + */ #define SDHC_IRQSTAT_DCE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_DCE_SHIFT)) & SDHC_IRQSTAT_DCE_MASK) #define SDHC_IRQSTAT_DEBE_MASK (0x400000U) #define SDHC_IRQSTAT_DEBE_SHIFT (22U) +/*! DEBE - Data End Bit Error + * 0b0..No error. + * 0b1..Error. + */ #define SDHC_IRQSTAT_DEBE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_DEBE_SHIFT)) & SDHC_IRQSTAT_DEBE_MASK) #define SDHC_IRQSTAT_AC12E_MASK (0x1000000U) #define SDHC_IRQSTAT_AC12E_SHIFT (24U) +/*! AC12E - Auto CMD12 Error + * 0b0..No error. + * 0b1..Error. + */ #define SDHC_IRQSTAT_AC12E(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_AC12E_SHIFT)) & SDHC_IRQSTAT_AC12E_MASK) #define SDHC_IRQSTAT_DMAE_MASK (0x10000000U) #define SDHC_IRQSTAT_DMAE_SHIFT (28U) +/*! DMAE - DMA Error + * 0b0..No error. + * 0b1..Error. + */ #define SDHC_IRQSTAT_DMAE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_DMAE_SHIFT)) & SDHC_IRQSTAT_DMAE_MASK) +/*! @} */ /*! @name IRQSTATEN - Interrupt Status Enable register */ +/*! @{ */ #define SDHC_IRQSTATEN_CCSEN_MASK (0x1U) #define SDHC_IRQSTATEN_CCSEN_SHIFT (0U) +/*! CCSEN - Command Complete Status Enable + * 0b0..Masked + * 0b1..Enabled + */ #define SDHC_IRQSTATEN_CCSEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CCSEN_SHIFT)) & SDHC_IRQSTATEN_CCSEN_MASK) #define SDHC_IRQSTATEN_TCSEN_MASK (0x2U) #define SDHC_IRQSTATEN_TCSEN_SHIFT (1U) +/*! TCSEN - Transfer Complete Status Enable + * 0b0..Masked + * 0b1..Enabled + */ #define SDHC_IRQSTATEN_TCSEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_TCSEN_SHIFT)) & SDHC_IRQSTATEN_TCSEN_MASK) #define SDHC_IRQSTATEN_BGESEN_MASK (0x4U) #define SDHC_IRQSTATEN_BGESEN_SHIFT (2U) +/*! BGESEN - Block Gap Event Status Enable + * 0b0..Masked + * 0b1..Enabled + */ #define SDHC_IRQSTATEN_BGESEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_BGESEN_SHIFT)) & SDHC_IRQSTATEN_BGESEN_MASK) #define SDHC_IRQSTATEN_DINTSEN_MASK (0x8U) #define SDHC_IRQSTATEN_DINTSEN_SHIFT (3U) +/*! DINTSEN - DMA Interrupt Status Enable + * 0b0..Masked + * 0b1..Enabled + */ #define SDHC_IRQSTATEN_DINTSEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_DINTSEN_SHIFT)) & SDHC_IRQSTATEN_DINTSEN_MASK) #define SDHC_IRQSTATEN_BWRSEN_MASK (0x10U) #define SDHC_IRQSTATEN_BWRSEN_SHIFT (4U) +/*! BWRSEN - Buffer Write Ready Status Enable + * 0b0..Masked + * 0b1..Enabled + */ #define SDHC_IRQSTATEN_BWRSEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_BWRSEN_SHIFT)) & SDHC_IRQSTATEN_BWRSEN_MASK) #define SDHC_IRQSTATEN_BRRSEN_MASK (0x20U) #define SDHC_IRQSTATEN_BRRSEN_SHIFT (5U) +/*! BRRSEN - Buffer Read Ready Status Enable + * 0b0..Masked + * 0b1..Enabled + */ #define SDHC_IRQSTATEN_BRRSEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_BRRSEN_SHIFT)) & SDHC_IRQSTATEN_BRRSEN_MASK) #define SDHC_IRQSTATEN_CINSEN_MASK (0x40U) #define SDHC_IRQSTATEN_CINSEN_SHIFT (6U) +/*! CINSEN - Card Insertion Status Enable + * 0b0..Masked + * 0b1..Enabled + */ #define SDHC_IRQSTATEN_CINSEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CINSEN_SHIFT)) & SDHC_IRQSTATEN_CINSEN_MASK) #define SDHC_IRQSTATEN_CRMSEN_MASK (0x80U) #define SDHC_IRQSTATEN_CRMSEN_SHIFT (7U) +/*! CRMSEN - Card Removal Status Enable + * 0b0..Masked + * 0b1..Enabled + */ #define SDHC_IRQSTATEN_CRMSEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CRMSEN_SHIFT)) & SDHC_IRQSTATEN_CRMSEN_MASK) #define SDHC_IRQSTATEN_CINTSEN_MASK (0x100U) #define SDHC_IRQSTATEN_CINTSEN_SHIFT (8U) +/*! CINTSEN - Card Interrupt Status Enable + * 0b0..Masked + * 0b1..Enabled + */ #define SDHC_IRQSTATEN_CINTSEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CINTSEN_SHIFT)) & SDHC_IRQSTATEN_CINTSEN_MASK) #define SDHC_IRQSTATEN_CTOESEN_MASK (0x10000U) #define SDHC_IRQSTATEN_CTOESEN_SHIFT (16U) +/*! CTOESEN - Command Timeout Error Status Enable + * 0b0..Masked + * 0b1..Enabled + */ #define SDHC_IRQSTATEN_CTOESEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CTOESEN_SHIFT)) & SDHC_IRQSTATEN_CTOESEN_MASK) #define SDHC_IRQSTATEN_CCESEN_MASK (0x20000U) #define SDHC_IRQSTATEN_CCESEN_SHIFT (17U) +/*! CCESEN - Command CRC Error Status Enable + * 0b0..Masked + * 0b1..Enabled + */ #define SDHC_IRQSTATEN_CCESEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CCESEN_SHIFT)) & SDHC_IRQSTATEN_CCESEN_MASK) #define SDHC_IRQSTATEN_CEBESEN_MASK (0x40000U) #define SDHC_IRQSTATEN_CEBESEN_SHIFT (18U) +/*! CEBESEN - Command End Bit Error Status Enable + * 0b0..Masked + * 0b1..Enabled + */ #define SDHC_IRQSTATEN_CEBESEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CEBESEN_SHIFT)) & SDHC_IRQSTATEN_CEBESEN_MASK) #define SDHC_IRQSTATEN_CIESEN_MASK (0x80000U) #define SDHC_IRQSTATEN_CIESEN_SHIFT (19U) +/*! CIESEN - Command Index Error Status Enable + * 0b0..Masked + * 0b1..Enabled + */ #define SDHC_IRQSTATEN_CIESEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CIESEN_SHIFT)) & SDHC_IRQSTATEN_CIESEN_MASK) #define SDHC_IRQSTATEN_DTOESEN_MASK (0x100000U) #define SDHC_IRQSTATEN_DTOESEN_SHIFT (20U) +/*! DTOESEN - Data Timeout Error Status Enable + * 0b0..Masked + * 0b1..Enabled + */ #define SDHC_IRQSTATEN_DTOESEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_DTOESEN_SHIFT)) & SDHC_IRQSTATEN_DTOESEN_MASK) #define SDHC_IRQSTATEN_DCESEN_MASK (0x200000U) #define SDHC_IRQSTATEN_DCESEN_SHIFT (21U) +/*! DCESEN - Data CRC Error Status Enable + * 0b0..Masked + * 0b1..Enabled + */ #define SDHC_IRQSTATEN_DCESEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_DCESEN_SHIFT)) & SDHC_IRQSTATEN_DCESEN_MASK) #define SDHC_IRQSTATEN_DEBESEN_MASK (0x400000U) #define SDHC_IRQSTATEN_DEBESEN_SHIFT (22U) +/*! DEBESEN - Data End Bit Error Status Enable + * 0b0..Masked + * 0b1..Enabled + */ #define SDHC_IRQSTATEN_DEBESEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_DEBESEN_SHIFT)) & SDHC_IRQSTATEN_DEBESEN_MASK) #define SDHC_IRQSTATEN_AC12ESEN_MASK (0x1000000U) #define SDHC_IRQSTATEN_AC12ESEN_SHIFT (24U) +/*! AC12ESEN - Auto CMD12 Error Status Enable + * 0b0..Masked + * 0b1..Enabled + */ #define SDHC_IRQSTATEN_AC12ESEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_AC12ESEN_SHIFT)) & SDHC_IRQSTATEN_AC12ESEN_MASK) #define SDHC_IRQSTATEN_DMAESEN_MASK (0x10000000U) #define SDHC_IRQSTATEN_DMAESEN_SHIFT (28U) +/*! DMAESEN - DMA Error Status Enable + * 0b0..Masked + * 0b1..Enabled + */ #define SDHC_IRQSTATEN_DMAESEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_DMAESEN_SHIFT)) & SDHC_IRQSTATEN_DMAESEN_MASK) +/*! @} */ /*! @name IRQSIGEN - Interrupt Signal Enable register */ +/*! @{ */ #define SDHC_IRQSIGEN_CCIEN_MASK (0x1U) #define SDHC_IRQSIGEN_CCIEN_SHIFT (0U) +/*! CCIEN - Command Complete Interrupt Enable + * 0b0..Masked + * 0b1..Enabled + */ #define SDHC_IRQSIGEN_CCIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CCIEN_SHIFT)) & SDHC_IRQSIGEN_CCIEN_MASK) #define SDHC_IRQSIGEN_TCIEN_MASK (0x2U) #define SDHC_IRQSIGEN_TCIEN_SHIFT (1U) +/*! TCIEN - Transfer Complete Interrupt Enable + * 0b0..Masked + * 0b1..Enabled + */ #define SDHC_IRQSIGEN_TCIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_TCIEN_SHIFT)) & SDHC_IRQSIGEN_TCIEN_MASK) #define SDHC_IRQSIGEN_BGEIEN_MASK (0x4U) #define SDHC_IRQSIGEN_BGEIEN_SHIFT (2U) +/*! BGEIEN - Block Gap Event Interrupt Enable + * 0b0..Masked + * 0b1..Enabled + */ #define SDHC_IRQSIGEN_BGEIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_BGEIEN_SHIFT)) & SDHC_IRQSIGEN_BGEIEN_MASK) #define SDHC_IRQSIGEN_DINTIEN_MASK (0x8U) #define SDHC_IRQSIGEN_DINTIEN_SHIFT (3U) +/*! DINTIEN - DMA Interrupt Enable + * 0b0..Masked + * 0b1..Enabled + */ #define SDHC_IRQSIGEN_DINTIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_DINTIEN_SHIFT)) & SDHC_IRQSIGEN_DINTIEN_MASK) #define SDHC_IRQSIGEN_BWRIEN_MASK (0x10U) #define SDHC_IRQSIGEN_BWRIEN_SHIFT (4U) +/*! BWRIEN - Buffer Write Ready Interrupt Enable + * 0b0..Masked + * 0b1..Enabled + */ #define SDHC_IRQSIGEN_BWRIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_BWRIEN_SHIFT)) & SDHC_IRQSIGEN_BWRIEN_MASK) #define SDHC_IRQSIGEN_BRRIEN_MASK (0x20U) #define SDHC_IRQSIGEN_BRRIEN_SHIFT (5U) +/*! BRRIEN - Buffer Read Ready Interrupt Enable + * 0b0..Masked + * 0b1..Enabled + */ #define SDHC_IRQSIGEN_BRRIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_BRRIEN_SHIFT)) & SDHC_IRQSIGEN_BRRIEN_MASK) #define SDHC_IRQSIGEN_CINSIEN_MASK (0x40U) #define SDHC_IRQSIGEN_CINSIEN_SHIFT (6U) +/*! CINSIEN - Card Insertion Interrupt Enable + * 0b0..Masked + * 0b1..Enabled + */ #define SDHC_IRQSIGEN_CINSIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CINSIEN_SHIFT)) & SDHC_IRQSIGEN_CINSIEN_MASK) #define SDHC_IRQSIGEN_CRMIEN_MASK (0x80U) #define SDHC_IRQSIGEN_CRMIEN_SHIFT (7U) +/*! CRMIEN - Card Removal Interrupt Enable + * 0b0..Masked + * 0b1..Enabled + */ #define SDHC_IRQSIGEN_CRMIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CRMIEN_SHIFT)) & SDHC_IRQSIGEN_CRMIEN_MASK) #define SDHC_IRQSIGEN_CINTIEN_MASK (0x100U) #define SDHC_IRQSIGEN_CINTIEN_SHIFT (8U) +/*! CINTIEN - Card Interrupt Enable + * 0b0..Masked + * 0b1..Enabled + */ #define SDHC_IRQSIGEN_CINTIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CINTIEN_SHIFT)) & SDHC_IRQSIGEN_CINTIEN_MASK) #define SDHC_IRQSIGEN_CTOEIEN_MASK (0x10000U) #define SDHC_IRQSIGEN_CTOEIEN_SHIFT (16U) +/*! CTOEIEN - Command Timeout Error Interrupt Enable + * 0b0..Masked + * 0b1..Enabled + */ #define SDHC_IRQSIGEN_CTOEIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CTOEIEN_SHIFT)) & SDHC_IRQSIGEN_CTOEIEN_MASK) #define SDHC_IRQSIGEN_CCEIEN_MASK (0x20000U) #define SDHC_IRQSIGEN_CCEIEN_SHIFT (17U) +/*! CCEIEN - Command CRC Error Interrupt Enable + * 0b0..Masked + * 0b1..Enabled + */ #define SDHC_IRQSIGEN_CCEIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CCEIEN_SHIFT)) & SDHC_IRQSIGEN_CCEIEN_MASK) #define SDHC_IRQSIGEN_CEBEIEN_MASK (0x40000U) #define SDHC_IRQSIGEN_CEBEIEN_SHIFT (18U) +/*! CEBEIEN - Command End Bit Error Interrupt Enable + * 0b0..Masked + * 0b1..Enabled + */ #define SDHC_IRQSIGEN_CEBEIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CEBEIEN_SHIFT)) & SDHC_IRQSIGEN_CEBEIEN_MASK) #define SDHC_IRQSIGEN_CIEIEN_MASK (0x80000U) #define SDHC_IRQSIGEN_CIEIEN_SHIFT (19U) +/*! CIEIEN - Command Index Error Interrupt Enable + * 0b0..Masked + * 0b1..Enabled + */ #define SDHC_IRQSIGEN_CIEIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CIEIEN_SHIFT)) & SDHC_IRQSIGEN_CIEIEN_MASK) #define SDHC_IRQSIGEN_DTOEIEN_MASK (0x100000U) #define SDHC_IRQSIGEN_DTOEIEN_SHIFT (20U) +/*! DTOEIEN - Data Timeout Error Interrupt Enable + * 0b0..Masked + * 0b1..Enabled + */ #define SDHC_IRQSIGEN_DTOEIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_DTOEIEN_SHIFT)) & SDHC_IRQSIGEN_DTOEIEN_MASK) #define SDHC_IRQSIGEN_DCEIEN_MASK (0x200000U) #define SDHC_IRQSIGEN_DCEIEN_SHIFT (21U) +/*! DCEIEN - Data CRC Error Interrupt Enable + * 0b0..Masked + * 0b1..Enabled + */ #define SDHC_IRQSIGEN_DCEIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_DCEIEN_SHIFT)) & SDHC_IRQSIGEN_DCEIEN_MASK) #define SDHC_IRQSIGEN_DEBEIEN_MASK (0x400000U) #define SDHC_IRQSIGEN_DEBEIEN_SHIFT (22U) +/*! DEBEIEN - Data End Bit Error Interrupt Enable + * 0b0..Masked + * 0b1..Enabled + */ #define SDHC_IRQSIGEN_DEBEIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_DEBEIEN_SHIFT)) & SDHC_IRQSIGEN_DEBEIEN_MASK) #define SDHC_IRQSIGEN_AC12EIEN_MASK (0x1000000U) #define SDHC_IRQSIGEN_AC12EIEN_SHIFT (24U) +/*! AC12EIEN - Auto CMD12 Error Interrupt Enable + * 0b0..Masked + * 0b1..Enabled + */ #define SDHC_IRQSIGEN_AC12EIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_AC12EIEN_SHIFT)) & SDHC_IRQSIGEN_AC12EIEN_MASK) #define SDHC_IRQSIGEN_DMAEIEN_MASK (0x10000000U) #define SDHC_IRQSIGEN_DMAEIEN_SHIFT (28U) +/*! DMAEIEN - DMA Error Interrupt Enable + * 0b0..Masked + * 0b1..Enabled + */ #define SDHC_IRQSIGEN_DMAEIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_DMAEIEN_SHIFT)) & SDHC_IRQSIGEN_DMAEIEN_MASK) +/*! @} */ /*! @name AC12ERR - Auto CMD12 Error Status Register */ +/*! @{ */ #define SDHC_AC12ERR_AC12NE_MASK (0x1U) #define SDHC_AC12ERR_AC12NE_SHIFT (0U) +/*! AC12NE - Auto CMD12 Not Executed + * 0b0..Executed. + * 0b1..Not executed. + */ #define SDHC_AC12ERR_AC12NE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_AC12ERR_AC12NE_SHIFT)) & SDHC_AC12ERR_AC12NE_MASK) #define SDHC_AC12ERR_AC12TOE_MASK (0x2U) #define SDHC_AC12ERR_AC12TOE_SHIFT (1U) +/*! AC12TOE - Auto CMD12 Timeout Error + * 0b0..No error. + * 0b1..Time out. + */ #define SDHC_AC12ERR_AC12TOE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_AC12ERR_AC12TOE_SHIFT)) & SDHC_AC12ERR_AC12TOE_MASK) #define SDHC_AC12ERR_AC12EBE_MASK (0x4U) #define SDHC_AC12ERR_AC12EBE_SHIFT (2U) +/*! AC12EBE - Auto CMD12 End Bit Error + * 0b0..No error. + * 0b1..End bit error generated. + */ #define SDHC_AC12ERR_AC12EBE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_AC12ERR_AC12EBE_SHIFT)) & SDHC_AC12ERR_AC12EBE_MASK) #define SDHC_AC12ERR_AC12CE_MASK (0x8U) #define SDHC_AC12ERR_AC12CE_SHIFT (3U) +/*! AC12CE - Auto CMD12 CRC Error + * 0b0..No CRC error. + * 0b1..CRC error met in Auto CMD12 response. + */ #define SDHC_AC12ERR_AC12CE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_AC12ERR_AC12CE_SHIFT)) & SDHC_AC12ERR_AC12CE_MASK) #define SDHC_AC12ERR_AC12IE_MASK (0x10U) #define SDHC_AC12ERR_AC12IE_SHIFT (4U) +/*! AC12IE - Auto CMD12 Index Error + * 0b0..No error. + * 0b1..Error, the CMD index in response is not CMD12. + */ #define SDHC_AC12ERR_AC12IE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_AC12ERR_AC12IE_SHIFT)) & SDHC_AC12ERR_AC12IE_MASK) #define SDHC_AC12ERR_CNIBAC12E_MASK (0x80U) #define SDHC_AC12ERR_CNIBAC12E_SHIFT (7U) +/*! CNIBAC12E - Command Not Issued By Auto CMD12 Error + * 0b0..No error. + * 0b1..Not issued. + */ #define SDHC_AC12ERR_CNIBAC12E(x) (((uint32_t)(((uint32_t)(x)) << SDHC_AC12ERR_CNIBAC12E_SHIFT)) & SDHC_AC12ERR_CNIBAC12E_MASK) +/*! @} */ /*! @name HTCAPBLT - Host Controller Capabilities */ +/*! @{ */ #define SDHC_HTCAPBLT_MBL_MASK (0x70000U) #define SDHC_HTCAPBLT_MBL_SHIFT (16U) +/*! MBL - Max Block Length + * 0b000..512 bytes + * 0b001..1024 bytes + * 0b010..2048 bytes + * 0b011..4096 bytes + */ #define SDHC_HTCAPBLT_MBL(x) (((uint32_t)(((uint32_t)(x)) << SDHC_HTCAPBLT_MBL_SHIFT)) & SDHC_HTCAPBLT_MBL_MASK) #define SDHC_HTCAPBLT_ADMAS_MASK (0x100000U) #define SDHC_HTCAPBLT_ADMAS_SHIFT (20U) +/*! ADMAS - ADMA Support + * 0b0..Advanced DMA not supported. + * 0b1..Advanced DMA supported. + */ #define SDHC_HTCAPBLT_ADMAS(x) (((uint32_t)(((uint32_t)(x)) << SDHC_HTCAPBLT_ADMAS_SHIFT)) & SDHC_HTCAPBLT_ADMAS_MASK) #define SDHC_HTCAPBLT_HSS_MASK (0x200000U) #define SDHC_HTCAPBLT_HSS_SHIFT (21U) +/*! HSS - High Speed Support + * 0b0..High speed not supported. + * 0b1..High speed supported. + */ #define SDHC_HTCAPBLT_HSS(x) (((uint32_t)(((uint32_t)(x)) << SDHC_HTCAPBLT_HSS_SHIFT)) & SDHC_HTCAPBLT_HSS_MASK) #define SDHC_HTCAPBLT_DMAS_MASK (0x400000U) #define SDHC_HTCAPBLT_DMAS_SHIFT (22U) +/*! DMAS - DMA Support + * 0b0..DMA not supported. + * 0b1..DMA supported. + */ #define SDHC_HTCAPBLT_DMAS(x) (((uint32_t)(((uint32_t)(x)) << SDHC_HTCAPBLT_DMAS_SHIFT)) & SDHC_HTCAPBLT_DMAS_MASK) #define SDHC_HTCAPBLT_SRS_MASK (0x800000U) #define SDHC_HTCAPBLT_SRS_SHIFT (23U) +/*! SRS - Suspend/Resume Support + * 0b0..Not supported. + * 0b1..Supported. + */ #define SDHC_HTCAPBLT_SRS(x) (((uint32_t)(((uint32_t)(x)) << SDHC_HTCAPBLT_SRS_SHIFT)) & SDHC_HTCAPBLT_SRS_MASK) #define SDHC_HTCAPBLT_VS33_MASK (0x1000000U) #define SDHC_HTCAPBLT_VS33_SHIFT (24U) +/*! VS33 - Voltage Support 3.3 V + * 0b0..3.3 V not supported. + * 0b1..3.3 V supported. + */ #define SDHC_HTCAPBLT_VS33(x) (((uint32_t)(((uint32_t)(x)) << SDHC_HTCAPBLT_VS33_SHIFT)) & SDHC_HTCAPBLT_VS33_MASK) +/*! @} */ /*! @name WML - Watermark Level Register */ +/*! @{ */ #define SDHC_WML_RDWML_MASK (0xFFU) #define SDHC_WML_RDWML_SHIFT (0U) #define SDHC_WML_RDWML(x) (((uint32_t)(((uint32_t)(x)) << SDHC_WML_RDWML_SHIFT)) & SDHC_WML_RDWML_MASK) #define SDHC_WML_WRWML_MASK (0xFF0000U) #define SDHC_WML_WRWML_SHIFT (16U) #define SDHC_WML_WRWML(x) (((uint32_t)(((uint32_t)(x)) << SDHC_WML_WRWML_SHIFT)) & SDHC_WML_WRWML_MASK) +/*! @} */ /*! @name FEVT - Force Event register */ +/*! @{ */ #define SDHC_FEVT_AC12NE_MASK (0x1U) #define SDHC_FEVT_AC12NE_SHIFT (0U) #define SDHC_FEVT_AC12NE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_AC12NE_SHIFT)) & SDHC_FEVT_AC12NE_MASK) @@ -10075,46 +17720,94 @@ typedef struct { #define SDHC_FEVT_CINT_MASK (0x80000000U) #define SDHC_FEVT_CINT_SHIFT (31U) #define SDHC_FEVT_CINT(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_CINT_SHIFT)) & SDHC_FEVT_CINT_MASK) +/*! @} */ /*! @name ADMAES - ADMA Error Status register */ +/*! @{ */ #define SDHC_ADMAES_ADMAES_MASK (0x3U) #define SDHC_ADMAES_ADMAES_SHIFT (0U) #define SDHC_ADMAES_ADMAES(x) (((uint32_t)(((uint32_t)(x)) << SDHC_ADMAES_ADMAES_SHIFT)) & SDHC_ADMAES_ADMAES_MASK) #define SDHC_ADMAES_ADMALME_MASK (0x4U) #define SDHC_ADMAES_ADMALME_SHIFT (2U) +/*! ADMALME - ADMA Length Mismatch Error + * 0b0..No error. + * 0b1..Error. + */ #define SDHC_ADMAES_ADMALME(x) (((uint32_t)(((uint32_t)(x)) << SDHC_ADMAES_ADMALME_SHIFT)) & SDHC_ADMAES_ADMALME_MASK) #define SDHC_ADMAES_ADMADCE_MASK (0x8U) #define SDHC_ADMAES_ADMADCE_SHIFT (3U) +/*! ADMADCE - ADMA Descriptor Error + * 0b0..No error. + * 0b1..Error. + */ #define SDHC_ADMAES_ADMADCE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_ADMAES_ADMADCE_SHIFT)) & SDHC_ADMAES_ADMADCE_MASK) +/*! @} */ /*! @name ADSADDR - ADMA System Addressregister */ +/*! @{ */ #define SDHC_ADSADDR_ADSADDR_MASK (0xFFFFFFFCU) #define SDHC_ADSADDR_ADSADDR_SHIFT (2U) #define SDHC_ADSADDR_ADSADDR(x) (((uint32_t)(((uint32_t)(x)) << SDHC_ADSADDR_ADSADDR_SHIFT)) & SDHC_ADSADDR_ADSADDR_MASK) +/*! @} */ /*! @name VENDOR - Vendor Specific register */ +/*! @{ */ #define SDHC_VENDOR_EXTDMAEN_MASK (0x1U) #define SDHC_VENDOR_EXTDMAEN_SHIFT (0U) +/*! EXTDMAEN - External DMA Request Enable + * 0b0..In any scenario, SDHC does not send out the external DMA request. + * 0b1..When internal DMA is not active, the external DMA request will be sent out. + */ #define SDHC_VENDOR_EXTDMAEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_VENDOR_EXTDMAEN_SHIFT)) & SDHC_VENDOR_EXTDMAEN_MASK) #define SDHC_VENDOR_EXBLKNU_MASK (0x2U) #define SDHC_VENDOR_EXBLKNU_SHIFT (1U) +/*! EXBLKNU - Exact Block Number Block Read Enable For SDIO CMD53 + * 0b0..None exact block read. + * 0b1..Exact block read for SDIO CMD53. + */ #define SDHC_VENDOR_EXBLKNU(x) (((uint32_t)(((uint32_t)(x)) << SDHC_VENDOR_EXBLKNU_SHIFT)) & SDHC_VENDOR_EXBLKNU_MASK) #define SDHC_VENDOR_INTSTVAL_MASK (0xFF0000U) #define SDHC_VENDOR_INTSTVAL_SHIFT (16U) #define SDHC_VENDOR_INTSTVAL(x) (((uint32_t)(((uint32_t)(x)) << SDHC_VENDOR_INTSTVAL_SHIFT)) & SDHC_VENDOR_INTSTVAL_MASK) +/*! @} */ /*! @name MMCBOOT - MMC Boot register */ +/*! @{ */ #define SDHC_MMCBOOT_DTOCVACK_MASK (0xFU) #define SDHC_MMCBOOT_DTOCVACK_SHIFT (0U) +/*! DTOCVACK - Boot ACK Time Out Counter Value + * 0b0000..SDCLK x 2^8 + * 0b0001..SDCLK x 2^9 + * 0b0010..SDCLK x 2^10 + * 0b0011..SDCLK x 2^11 + * 0b0100..SDCLK x 2^12 + * 0b0101..SDCLK x 2^13 + * 0b0110..SDCLK x 2^14 + * 0b0111..SDCLK x 2^15 + * 0b1110..SDCLK x 2^22 + * 0b1111..Reserved + */ #define SDHC_MMCBOOT_DTOCVACK(x) (((uint32_t)(((uint32_t)(x)) << SDHC_MMCBOOT_DTOCVACK_SHIFT)) & SDHC_MMCBOOT_DTOCVACK_MASK) #define SDHC_MMCBOOT_BOOTACK_MASK (0x10U) #define SDHC_MMCBOOT_BOOTACK_SHIFT (4U) +/*! BOOTACK - Boot Ack Mode Select + * 0b0..No ack. + * 0b1..Ack. + */ #define SDHC_MMCBOOT_BOOTACK(x) (((uint32_t)(((uint32_t)(x)) << SDHC_MMCBOOT_BOOTACK_SHIFT)) & SDHC_MMCBOOT_BOOTACK_MASK) #define SDHC_MMCBOOT_BOOTMODE_MASK (0x20U) #define SDHC_MMCBOOT_BOOTMODE_SHIFT (5U) +/*! BOOTMODE - Boot Mode Select + * 0b0..Normal boot. + * 0b1..Alternative boot. + */ #define SDHC_MMCBOOT_BOOTMODE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_MMCBOOT_BOOTMODE_SHIFT)) & SDHC_MMCBOOT_BOOTMODE_MASK) #define SDHC_MMCBOOT_BOOTEN_MASK (0x40U) #define SDHC_MMCBOOT_BOOTEN_SHIFT (6U) +/*! BOOTEN - Boot Mode Enable + * 0b0..Fast boot disable. + * 0b1..Fast boot enable. + */ #define SDHC_MMCBOOT_BOOTEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_MMCBOOT_BOOTEN_SHIFT)) & SDHC_MMCBOOT_BOOTEN_MASK) #define SDHC_MMCBOOT_AUTOSABGEN_MASK (0x80U) #define SDHC_MMCBOOT_AUTOSABGEN_SHIFT (7U) @@ -10122,14 +17815,26 @@ typedef struct { #define SDHC_MMCBOOT_BOOTBLKCNT_MASK (0xFFFF0000U) #define SDHC_MMCBOOT_BOOTBLKCNT_SHIFT (16U) #define SDHC_MMCBOOT_BOOTBLKCNT(x) (((uint32_t)(((uint32_t)(x)) << SDHC_MMCBOOT_BOOTBLKCNT_SHIFT)) & SDHC_MMCBOOT_BOOTBLKCNT_MASK) +/*! @} */ /*! @name HOSTVER - Host Controller Version */ +/*! @{ */ #define SDHC_HOSTVER_SVN_MASK (0xFFU) #define SDHC_HOSTVER_SVN_SHIFT (0U) +/*! SVN - Specification Version Number + * 0b00000001..SD host specification version 2.0, supports test event register and ADMA. + */ #define SDHC_HOSTVER_SVN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_HOSTVER_SVN_SHIFT)) & SDHC_HOSTVER_SVN_MASK) #define SDHC_HOSTVER_VVN_MASK (0xFF00U) #define SDHC_HOSTVER_VVN_SHIFT (8U) +/*! VVN - Vendor Version Number + * 0b00000000..Freescale SDHC version 1.0 + * 0b00010000..Freescale SDHC version 2.0 + * 0b00010001..Freescale SDHC version 2.1 + * 0b00010010..Freescale SDHC version 2.2 + */ #define SDHC_HOSTVER_VVN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_HOSTVER_VVN_SHIFT)) & SDHC_HOSTVER_VVN_MASK) +/*! @} */ /*! @@ -10203,155 +17908,435 @@ typedef struct { */ /*! @name SOPT1 - System Options Register 1 */ +/*! @{ */ #define SIM_SOPT1_RAMSIZE_MASK (0xF000U) #define SIM_SOPT1_RAMSIZE_SHIFT (12U) +/*! RAMSIZE - RAM size + * 0b0001..8 KB + * 0b0011..16 KB + * 0b0100..24 KB + * 0b0101..32 KB + * 0b0110..48 KB + * 0b0111..64 KB + * 0b1000..96 KB + * 0b1001..128 KB + * 0b1011..256 KB + */ #define SIM_SOPT1_RAMSIZE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_RAMSIZE_SHIFT)) & SIM_SOPT1_RAMSIZE_MASK) #define SIM_SOPT1_OSC32KSEL_MASK (0xC0000U) #define SIM_SOPT1_OSC32KSEL_SHIFT (18U) +/*! OSC32KSEL - 32K oscillator clock select + * 0b00..System oscillator (OSC32KCLK) + * 0b01..Reserved + * 0b10..RTC 32.768kHz oscillator + * 0b11..LPO 1 kHz + */ #define SIM_SOPT1_OSC32KSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_OSC32KSEL_SHIFT)) & SIM_SOPT1_OSC32KSEL_MASK) #define SIM_SOPT1_USBVSTBY_MASK (0x20000000U) #define SIM_SOPT1_USBVSTBY_SHIFT (29U) +/*! USBVSTBY - USB voltage regulator in standby mode during VLPR and VLPW modes + * 0b0..USB voltage regulator not in standby during VLPR and VLPW modes. + * 0b1..USB voltage regulator in standby during VLPR and VLPW modes. + */ #define SIM_SOPT1_USBVSTBY(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_USBVSTBY_SHIFT)) & SIM_SOPT1_USBVSTBY_MASK) #define SIM_SOPT1_USBSSTBY_MASK (0x40000000U) #define SIM_SOPT1_USBSSTBY_SHIFT (30U) +/*! USBSSTBY - USB voltage regulator in standby mode during Stop, VLPS, LLS and VLLS modes. + * 0b0..USB voltage regulator not in standby during Stop, VLPS, LLS and VLLS modes. + * 0b1..USB voltage regulator in standby during Stop, VLPS, LLS and VLLS modes. + */ #define SIM_SOPT1_USBSSTBY(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_USBSSTBY_SHIFT)) & SIM_SOPT1_USBSSTBY_MASK) #define SIM_SOPT1_USBREGEN_MASK (0x80000000U) #define SIM_SOPT1_USBREGEN_SHIFT (31U) +/*! USBREGEN - USB voltage regulator enable + * 0b0..USB voltage regulator is disabled. + * 0b1..USB voltage regulator is enabled. + */ #define SIM_SOPT1_USBREGEN(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_USBREGEN_SHIFT)) & SIM_SOPT1_USBREGEN_MASK) +/*! @} */ /*! @name SOPT1CFG - SOPT1 Configuration Register */ +/*! @{ */ #define SIM_SOPT1CFG_URWE_MASK (0x1000000U) #define SIM_SOPT1CFG_URWE_SHIFT (24U) +/*! URWE - USB voltage regulator enable write enable + * 0b0..SOPT1 USBREGEN cannot be written. + * 0b1..SOPT1 USBREGEN can be written. + */ #define SIM_SOPT1CFG_URWE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1CFG_URWE_SHIFT)) & SIM_SOPT1CFG_URWE_MASK) #define SIM_SOPT1CFG_UVSWE_MASK (0x2000000U) #define SIM_SOPT1CFG_UVSWE_SHIFT (25U) +/*! UVSWE - USB voltage regulator VLP standby write enable + * 0b0..SOPT1 USBVSTBY cannot be written. + * 0b1..SOPT1 USBVSTBY can be written. + */ #define SIM_SOPT1CFG_UVSWE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1CFG_UVSWE_SHIFT)) & SIM_SOPT1CFG_UVSWE_MASK) #define SIM_SOPT1CFG_USSWE_MASK (0x4000000U) #define SIM_SOPT1CFG_USSWE_SHIFT (26U) +/*! USSWE - USB voltage regulator stop standby write enable + * 0b0..SOPT1 USBSSTBY cannot be written. + * 0b1..SOPT1 USBSSTBY can be written. + */ #define SIM_SOPT1CFG_USSWE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1CFG_USSWE_SHIFT)) & SIM_SOPT1CFG_USSWE_MASK) +/*! @} */ /*! @name SOPT2 - System Options Register 2 */ +/*! @{ */ #define SIM_SOPT2_RTCCLKOUTSEL_MASK (0x10U) #define SIM_SOPT2_RTCCLKOUTSEL_SHIFT (4U) +/*! RTCCLKOUTSEL - RTC clock out select + * 0b0..RTC 1 Hz clock is output on the RTC_CLKOUT pin. + * 0b1..RTC 32.768kHz clock is output on the RTC_CLKOUT pin. + */ #define SIM_SOPT2_RTCCLKOUTSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_RTCCLKOUTSEL_SHIFT)) & SIM_SOPT2_RTCCLKOUTSEL_MASK) #define SIM_SOPT2_CLKOUTSEL_MASK (0xE0U) #define SIM_SOPT2_CLKOUTSEL_SHIFT (5U) +/*! CLKOUTSEL - CLKOUT select + * 0b000..FlexBus CLKOUT + * 0b001..Reserved + * 0b010..Flash clock + * 0b011..LPO clock (1 kHz) + * 0b100..MCGIRCLK + * 0b101..RTC 32.768kHz clock + * 0b110..OSCERCLK0 + * 0b111..IRC 48 MHz clock + */ #define SIM_SOPT2_CLKOUTSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_CLKOUTSEL_SHIFT)) & SIM_SOPT2_CLKOUTSEL_MASK) #define SIM_SOPT2_FBSL_MASK (0x300U) #define SIM_SOPT2_FBSL_SHIFT (8U) +/*! FBSL - FlexBus security level + * 0b00..All off-chip accesses (instruction and data) via the FlexBus are disallowed. + * 0b01..All off-chip accesses (instruction and data) via the FlexBus are disallowed. + * 0b10..Off-chip instruction accesses are disallowed. Data accesses are allowed. + * 0b11..Off-chip instruction accesses and data accesses are allowed. + */ #define SIM_SOPT2_FBSL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_FBSL_SHIFT)) & SIM_SOPT2_FBSL_MASK) #define SIM_SOPT2_PTD7PAD_MASK (0x800U) #define SIM_SOPT2_PTD7PAD_SHIFT (11U) +/*! PTD7PAD - PTD7 pad drive strength + * 0b0..Single-pad drive strength for PTD7. + * 0b1..Double pad drive strength for PTD7. + */ #define SIM_SOPT2_PTD7PAD(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_PTD7PAD_SHIFT)) & SIM_SOPT2_PTD7PAD_MASK) #define SIM_SOPT2_TRACECLKSEL_MASK (0x1000U) #define SIM_SOPT2_TRACECLKSEL_SHIFT (12U) +/*! TRACECLKSEL - Debug trace clock select + * 0b0..MCGOUTCLK + * 0b1..Core/system clock + */ #define SIM_SOPT2_TRACECLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_TRACECLKSEL_SHIFT)) & SIM_SOPT2_TRACECLKSEL_MASK) #define SIM_SOPT2_PLLFLLSEL_MASK (0x30000U) #define SIM_SOPT2_PLLFLLSEL_SHIFT (16U) +/*! PLLFLLSEL - PLL/FLL clock select + * 0b00..MCGFLLCLK clock + * 0b01..MCGPLLCLK clock + * 0b10..Reserved + * 0b11..IRC48 MHz clock + */ #define SIM_SOPT2_PLLFLLSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_PLLFLLSEL_SHIFT)) & SIM_SOPT2_PLLFLLSEL_MASK) #define SIM_SOPT2_USBSRC_MASK (0x40000U) #define SIM_SOPT2_USBSRC_SHIFT (18U) +/*! USBSRC - USB clock source select + * 0b0..External bypass clock (USB_CLKIN). + * 0b1..MCGFLLCLK , or MCGPLLCLK , or IRC48M clock as selected by SOPT2[PLLFLLSEL], and then divided by the USB fractional divider as configured by SIM_CLKDIV2[USBFRAC, USBDIV]. + */ #define SIM_SOPT2_USBSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_USBSRC_SHIFT)) & SIM_SOPT2_USBSRC_MASK) #define SIM_SOPT2_RMIISRC_MASK (0x80000U) #define SIM_SOPT2_RMIISRC_SHIFT (19U) +/*! RMIISRC - RMII clock source select + * 0b0..EXTAL clock + * 0b1..External bypass clock (ENET_1588_CLKIN). + */ #define SIM_SOPT2_RMIISRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_RMIISRC_SHIFT)) & SIM_SOPT2_RMIISRC_MASK) #define SIM_SOPT2_TIMESRC_MASK (0x300000U) #define SIM_SOPT2_TIMESRC_SHIFT (20U) +/*! TIMESRC - IEEE 1588 timestamp clock source select + * 0b00..Core/system clock. + * 0b01..MCGFLLCLK , or MCGPLLCLK , or IRC48M clock as selected by SOPT2[PLLFLLSEL]. + * 0b10..OSCERCLK clock + * 0b11..External bypass clock (ENET_1588_CLKIN). + */ #define SIM_SOPT2_TIMESRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_TIMESRC_SHIFT)) & SIM_SOPT2_TIMESRC_MASK) #define SIM_SOPT2_SDHCSRC_MASK (0x30000000U) #define SIM_SOPT2_SDHCSRC_SHIFT (28U) +/*! SDHCSRC - SDHC clock source select + * 0b00..Core/system clock. + * 0b01..MCGFLLCLK, or MCGPLLCLK , or IRC48M clock as selected by SOPT2[PLLFLLSEL]. + * 0b10..OSCERCLK clock + * 0b11..External bypass clock (SDHC0_CLKIN) + */ #define SIM_SOPT2_SDHCSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_SDHCSRC_SHIFT)) & SIM_SOPT2_SDHCSRC_MASK) +/*! @} */ /*! @name SOPT4 - System Options Register 4 */ +/*! @{ */ #define SIM_SOPT4_FTM0FLT0_MASK (0x1U) #define SIM_SOPT4_FTM0FLT0_SHIFT (0U) +/*! FTM0FLT0 - FTM0 Fault 0 Select + * 0b0..FTM0_FLT0 pin + * 0b1..CMP0 out + */ #define SIM_SOPT4_FTM0FLT0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0FLT0_SHIFT)) & SIM_SOPT4_FTM0FLT0_MASK) #define SIM_SOPT4_FTM0FLT1_MASK (0x2U) #define SIM_SOPT4_FTM0FLT1_SHIFT (1U) +/*! FTM0FLT1 - FTM0 Fault 1 Select + * 0b0..FTM0_FLT1 pin + * 0b1..CMP1 out + */ #define SIM_SOPT4_FTM0FLT1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0FLT1_SHIFT)) & SIM_SOPT4_FTM0FLT1_MASK) #define SIM_SOPT4_FTM0FLT2_MASK (0x4U) #define SIM_SOPT4_FTM0FLT2_SHIFT (2U) +/*! FTM0FLT2 - FTM0 Fault 2 Select + * 0b0..FTM0_FLT2 pin + * 0b1..CMP2 out + */ #define SIM_SOPT4_FTM0FLT2(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0FLT2_SHIFT)) & SIM_SOPT4_FTM0FLT2_MASK) #define SIM_SOPT4_FTM1FLT0_MASK (0x10U) #define SIM_SOPT4_FTM1FLT0_SHIFT (4U) +/*! FTM1FLT0 - FTM1 Fault 0 Select + * 0b0..FTM1_FLT0 pin + * 0b1..CMP0 out + */ #define SIM_SOPT4_FTM1FLT0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM1FLT0_SHIFT)) & SIM_SOPT4_FTM1FLT0_MASK) #define SIM_SOPT4_FTM2FLT0_MASK (0x100U) #define SIM_SOPT4_FTM2FLT0_SHIFT (8U) +/*! FTM2FLT0 - FTM2 Fault 0 Select + * 0b0..FTM2_FLT0 pin + * 0b1..CMP0 out + */ #define SIM_SOPT4_FTM2FLT0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM2FLT0_SHIFT)) & SIM_SOPT4_FTM2FLT0_MASK) #define SIM_SOPT4_FTM3FLT0_MASK (0x1000U) #define SIM_SOPT4_FTM3FLT0_SHIFT (12U) +/*! FTM3FLT0 - FTM3 Fault 0 Select + * 0b0..FTM3_FLT0 pin + * 0b1..CMP0 out + */ #define SIM_SOPT4_FTM3FLT0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM3FLT0_SHIFT)) & SIM_SOPT4_FTM3FLT0_MASK) #define SIM_SOPT4_FTM1CH0SRC_MASK (0xC0000U) #define SIM_SOPT4_FTM1CH0SRC_SHIFT (18U) +/*! FTM1CH0SRC - FTM1 channel 0 input capture source select + * 0b00..FTM1_CH0 signal + * 0b01..CMP0 output + * 0b10..CMP1 output + * 0b11..USB start of frame pulse + */ #define SIM_SOPT4_FTM1CH0SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM1CH0SRC_SHIFT)) & SIM_SOPT4_FTM1CH0SRC_MASK) #define SIM_SOPT4_FTM2CH0SRC_MASK (0x300000U) #define SIM_SOPT4_FTM2CH0SRC_SHIFT (20U) +/*! FTM2CH0SRC - FTM2 channel 0 input capture source select + * 0b00..FTM2_CH0 signal + * 0b01..CMP0 output + * 0b10..CMP1 output + * 0b11..Reserved + */ #define SIM_SOPT4_FTM2CH0SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM2CH0SRC_SHIFT)) & SIM_SOPT4_FTM2CH0SRC_MASK) #define SIM_SOPT4_FTM0CLKSEL_MASK (0x1000000U) #define SIM_SOPT4_FTM0CLKSEL_SHIFT (24U) +/*! FTM0CLKSEL - FlexTimer 0 External Clock Pin Select + * 0b0..FTM_CLK0 pin + * 0b1..FTM_CLK1 pin + */ #define SIM_SOPT4_FTM0CLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0CLKSEL_SHIFT)) & SIM_SOPT4_FTM0CLKSEL_MASK) #define SIM_SOPT4_FTM1CLKSEL_MASK (0x2000000U) #define SIM_SOPT4_FTM1CLKSEL_SHIFT (25U) +/*! FTM1CLKSEL - FTM1 External Clock Pin Select + * 0b0..FTM_CLK0 pin + * 0b1..FTM_CLK1 pin + */ #define SIM_SOPT4_FTM1CLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM1CLKSEL_SHIFT)) & SIM_SOPT4_FTM1CLKSEL_MASK) #define SIM_SOPT4_FTM2CLKSEL_MASK (0x4000000U) #define SIM_SOPT4_FTM2CLKSEL_SHIFT (26U) +/*! FTM2CLKSEL - FlexTimer 2 External Clock Pin Select + * 0b0..FTM2 external clock driven by FTM_CLK0 pin. + * 0b1..FTM2 external clock driven by FTM_CLK1 pin. + */ #define SIM_SOPT4_FTM2CLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM2CLKSEL_SHIFT)) & SIM_SOPT4_FTM2CLKSEL_MASK) #define SIM_SOPT4_FTM3CLKSEL_MASK (0x8000000U) #define SIM_SOPT4_FTM3CLKSEL_SHIFT (27U) +/*! FTM3CLKSEL - FlexTimer 3 External Clock Pin Select + * 0b0..FTM3 external clock driven by FTM_CLK0 pin. + * 0b1..FTM3 external clock driven by FTM_CLK1 pin. + */ #define SIM_SOPT4_FTM3CLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM3CLKSEL_SHIFT)) & SIM_SOPT4_FTM3CLKSEL_MASK) #define SIM_SOPT4_FTM0TRG0SRC_MASK (0x10000000U) #define SIM_SOPT4_FTM0TRG0SRC_SHIFT (28U) +/*! FTM0TRG0SRC - FlexTimer 0 Hardware Trigger 0 Source Select + * 0b0..HSCMP0 output drives FTM0 hardware trigger 0 + * 0b1..FTM1 channel match drives FTM0 hardware trigger 0 + */ #define SIM_SOPT4_FTM0TRG0SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0TRG0SRC_SHIFT)) & SIM_SOPT4_FTM0TRG0SRC_MASK) #define SIM_SOPT4_FTM0TRG1SRC_MASK (0x20000000U) #define SIM_SOPT4_FTM0TRG1SRC_SHIFT (29U) +/*! FTM0TRG1SRC - FlexTimer 0 Hardware Trigger 1 Source Select + * 0b0..PDB output trigger 1 drives FTM0 hardware trigger 1 + * 0b1..FTM2 channel match drives FTM0 hardware trigger 1 + */ #define SIM_SOPT4_FTM0TRG1SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0TRG1SRC_SHIFT)) & SIM_SOPT4_FTM0TRG1SRC_MASK) #define SIM_SOPT4_FTM3TRG0SRC_MASK (0x40000000U) #define SIM_SOPT4_FTM3TRG0SRC_SHIFT (30U) +/*! FTM3TRG0SRC - FlexTimer 3 Hardware Trigger 0 Source Select + * 0b0..Reserved + * 0b1..FTM1 channel match drives FTM3 hardware trigger 0 + */ #define SIM_SOPT4_FTM3TRG0SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM3TRG0SRC_SHIFT)) & SIM_SOPT4_FTM3TRG0SRC_MASK) #define SIM_SOPT4_FTM3TRG1SRC_MASK (0x80000000U) #define SIM_SOPT4_FTM3TRG1SRC_SHIFT (31U) +/*! FTM3TRG1SRC - FlexTimer 3 Hardware Trigger 1 Source Select + * 0b0..Reserved + * 0b1..FTM2 channel match drives FTM3 hardware trigger 1 + */ #define SIM_SOPT4_FTM3TRG1SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM3TRG1SRC_SHIFT)) & SIM_SOPT4_FTM3TRG1SRC_MASK) +/*! @} */ /*! @name SOPT5 - System Options Register 5 */ +/*! @{ */ #define SIM_SOPT5_UART0TXSRC_MASK (0x3U) #define SIM_SOPT5_UART0TXSRC_SHIFT (0U) +/*! UART0TXSRC - UART 0 transmit data source select + * 0b00..UART0_TX pin + * 0b01..UART0_TX pin modulated with FTM1 channel 0 output + * 0b10..UART0_TX pin modulated with FTM2 channel 0 output + * 0b11..Reserved + */ #define SIM_SOPT5_UART0TXSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART0TXSRC_SHIFT)) & SIM_SOPT5_UART0TXSRC_MASK) #define SIM_SOPT5_UART0RXSRC_MASK (0xCU) #define SIM_SOPT5_UART0RXSRC_SHIFT (2U) +/*! UART0RXSRC - UART 0 receive data source select + * 0b00..UART0_RX pin + * 0b01..CMP0 + * 0b10..CMP1 + * 0b11..Reserved + */ #define SIM_SOPT5_UART0RXSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART0RXSRC_SHIFT)) & SIM_SOPT5_UART0RXSRC_MASK) #define SIM_SOPT5_UART1TXSRC_MASK (0x30U) #define SIM_SOPT5_UART1TXSRC_SHIFT (4U) +/*! UART1TXSRC - UART 1 transmit data source select + * 0b00..UART1_TX pin + * 0b01..UART1_TX pin modulated with FTM1 channel 0 output + * 0b10..UART1_TX pin modulated with FTM2 channel 0 output + * 0b11..Reserved + */ #define SIM_SOPT5_UART1TXSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART1TXSRC_SHIFT)) & SIM_SOPT5_UART1TXSRC_MASK) #define SIM_SOPT5_UART1RXSRC_MASK (0xC0U) #define SIM_SOPT5_UART1RXSRC_SHIFT (6U) +/*! UART1RXSRC - UART 1 receive data source select + * 0b00..UART1_RX pin + * 0b01..CMP0 + * 0b10..CMP1 + * 0b11..Reserved + */ #define SIM_SOPT5_UART1RXSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART1RXSRC_SHIFT)) & SIM_SOPT5_UART1RXSRC_MASK) +/*! @} */ /*! @name SOPT7 - System Options Register 7 */ +/*! @{ */ #define SIM_SOPT7_ADC0TRGSEL_MASK (0xFU) #define SIM_SOPT7_ADC0TRGSEL_SHIFT (0U) +/*! ADC0TRGSEL - ADC0 trigger select + * 0b0000..PDB external trigger pin input (PDB0_EXTRG) + * 0b0001..High speed comparator 0 output + * 0b0010..High speed comparator 1 output + * 0b0011..High speed comparator 2 output + * 0b0100..PIT trigger 0 + * 0b0101..PIT trigger 1 + * 0b0110..PIT trigger 2 + * 0b0111..PIT trigger 3 + * 0b1000..FTM0 trigger + * 0b1001..FTM1 trigger + * 0b1010..FTM2 trigger + * 0b1011..FTM3 trigger + * 0b1100..RTC alarm + * 0b1101..RTC seconds + * 0b1110..Low-power timer (LPTMR) trigger + * 0b1111..Reserved + */ #define SIM_SOPT7_ADC0TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC0TRGSEL_SHIFT)) & SIM_SOPT7_ADC0TRGSEL_MASK) #define SIM_SOPT7_ADC0PRETRGSEL_MASK (0x10U) #define SIM_SOPT7_ADC0PRETRGSEL_SHIFT (4U) +/*! ADC0PRETRGSEL - ADC0 pretrigger select + * 0b0..Pre-trigger A + * 0b1..Pre-trigger B + */ #define SIM_SOPT7_ADC0PRETRGSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC0PRETRGSEL_SHIFT)) & SIM_SOPT7_ADC0PRETRGSEL_MASK) #define SIM_SOPT7_ADC0ALTTRGEN_MASK (0x80U) #define SIM_SOPT7_ADC0ALTTRGEN_SHIFT (7U) +/*! ADC0ALTTRGEN - ADC0 alternate trigger enable + * 0b0..PDB trigger selected for ADC0. + * 0b1..Alternate trigger selected for ADC0. + */ #define SIM_SOPT7_ADC0ALTTRGEN(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC0ALTTRGEN_SHIFT)) & SIM_SOPT7_ADC0ALTTRGEN_MASK) #define SIM_SOPT7_ADC1TRGSEL_MASK (0xF00U) #define SIM_SOPT7_ADC1TRGSEL_SHIFT (8U) +/*! ADC1TRGSEL - ADC1 trigger select + * 0b0000..PDB external trigger pin input (PDB0_EXTRG) + * 0b0001..High speed comparator 0 output + * 0b0010..High speed comparator 1 output + * 0b0011..High speed comparator 2 output + * 0b0100..PIT trigger 0 + * 0b0101..PIT trigger 1 + * 0b0110..PIT trigger 2 + * 0b0111..PIT trigger 3 + * 0b1000..FTM0 trigger + * 0b1001..FTM1 trigger + * 0b1010..FTM2 trigger + * 0b1011..FTM3 trigger + * 0b1100..RTC alarm + * 0b1101..RTC seconds + * 0b1110..Low-power timer (LPTMR) trigger + * 0b1111..Reserved + */ #define SIM_SOPT7_ADC1TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC1TRGSEL_SHIFT)) & SIM_SOPT7_ADC1TRGSEL_MASK) #define SIM_SOPT7_ADC1PRETRGSEL_MASK (0x1000U) #define SIM_SOPT7_ADC1PRETRGSEL_SHIFT (12U) +/*! ADC1PRETRGSEL - ADC1 pre-trigger select + * 0b0..Pre-trigger A selected for ADC1. + * 0b1..Pre-trigger B selected for ADC1. + */ #define SIM_SOPT7_ADC1PRETRGSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC1PRETRGSEL_SHIFT)) & SIM_SOPT7_ADC1PRETRGSEL_MASK) #define SIM_SOPT7_ADC1ALTTRGEN_MASK (0x8000U) #define SIM_SOPT7_ADC1ALTTRGEN_SHIFT (15U) +/*! ADC1ALTTRGEN - ADC1 alternate trigger enable + * 0b0..PDB trigger selected for ADC1 + * 0b1..Alternate trigger selected for ADC1 as defined by ADC1TRGSEL. + */ #define SIM_SOPT7_ADC1ALTTRGEN(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC1ALTTRGEN_SHIFT)) & SIM_SOPT7_ADC1ALTTRGEN_MASK) +/*! @} */ /*! @name SDID - System Device Identification Register */ +/*! @{ */ #define SIM_SDID_PINID_MASK (0xFU) #define SIM_SDID_PINID_SHIFT (0U) +/*! PINID - Pincount identification + * 0b0000..Reserved + * 0b0001..Reserved + * 0b0010..32-pin + * 0b0011..Reserved + * 0b0100..48-pin + * 0b0101..64-pin + * 0b0110..80-pin + * 0b0111..81-pin or 121-pin + * 0b1000..100-pin + * 0b1001..121-pin + * 0b1010..144-pin + * 0b1011..Custom pinout (WLCSP) + * 0b1100..169-pin + * 0b1101..Reserved + * 0b1110..256-pin + * 0b1111..Reserved + */ #define SIM_SDID_PINID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_PINID_SHIFT)) & SIM_SDID_PINID_MASK) #define SIM_SDID_FAMID_MASK (0x70U) #define SIM_SDID_FAMID_SHIFT (4U) +/*! FAMID - Kinetis family identification + * 0b000..K1x Family (without tamper) + * 0b001..K2x Family (without tamper) + * 0b010..K3x Family or K1x/K6x Family (with tamper) + * 0b011..K4x Family or K2x Family (with tamper) + * 0b100..K6x Family (without tamper) + * 0b101..K7x Family + * 0b110..Reserved + * 0b111..Reserved + */ #define SIM_SDID_FAMID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_FAMID_SHIFT)) & SIM_SDID_FAMID_MASK) #define SIM_SDID_DIEID_MASK (0xF80U) #define SIM_SDID_DIEID_SHIFT (7U) @@ -10361,247 +18346,608 @@ typedef struct { #define SIM_SDID_REVID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_REVID_SHIFT)) & SIM_SDID_REVID_MASK) #define SIM_SDID_SERIESID_MASK (0xF00000U) #define SIM_SDID_SERIESID_SHIFT (20U) +/*! SERIESID - Kinetis Series ID + * 0b0000..Kinetis K series + * 0b0001..Kinetis L series + * 0b0101..Kinetis W series + * 0b0110..Kinetis V series + */ #define SIM_SDID_SERIESID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_SERIESID_SHIFT)) & SIM_SDID_SERIESID_MASK) #define SIM_SDID_SUBFAMID_MASK (0xF000000U) #define SIM_SDID_SUBFAMID_SHIFT (24U) +/*! SUBFAMID - Kinetis Sub-Family ID + * 0b0000..Kx0 Subfamily + * 0b0001..Kx1 Subfamily (tamper detect) + * 0b0010..Kx2 Subfamily + * 0b0011..Kx3 Subfamily (tamper detect) + * 0b0100..Kx4 Subfamily + * 0b0101..Kx5 Subfamily (tamper detect) + * 0b0110..Kx6 Subfamily + */ #define SIM_SDID_SUBFAMID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_SUBFAMID_SHIFT)) & SIM_SDID_SUBFAMID_MASK) #define SIM_SDID_FAMILYID_MASK (0xF0000000U) #define SIM_SDID_FAMILYID_SHIFT (28U) +/*! FAMILYID - Kinetis Family ID + * 0b0001..K1x Family + * 0b0010..K2x Family + * 0b0011..K3x Family + * 0b0100..K4x Family + * 0b0110..K6x Family + * 0b0111..K7x Family + */ #define SIM_SDID_FAMILYID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_FAMILYID_SHIFT)) & SIM_SDID_FAMILYID_MASK) +/*! @} */ /*! @name SCGC1 - System Clock Gating Control Register 1 */ +/*! @{ */ #define SIM_SCGC1_I2C2_MASK (0x40U) #define SIM_SCGC1_I2C2_SHIFT (6U) +/*! I2C2 - I2C2 Clock Gate Control + * 0b0..Clock disabled + * 0b1..Clock enabled + */ #define SIM_SCGC1_I2C2(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC1_I2C2_SHIFT)) & SIM_SCGC1_I2C2_MASK) #define SIM_SCGC1_UART4_MASK (0x400U) #define SIM_SCGC1_UART4_SHIFT (10U) +/*! UART4 - UART4 Clock Gate Control + * 0b0..Clock disabled + * 0b1..Clock enabled + */ #define SIM_SCGC1_UART4(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC1_UART4_SHIFT)) & SIM_SCGC1_UART4_MASK) #define SIM_SCGC1_UART5_MASK (0x800U) #define SIM_SCGC1_UART5_SHIFT (11U) +/*! UART5 - UART5 Clock Gate Control + * 0b0..Clock disabled + * 0b1..Clock enabled + */ #define SIM_SCGC1_UART5(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC1_UART5_SHIFT)) & SIM_SCGC1_UART5_MASK) +/*! @} */ /*! @name SCGC2 - System Clock Gating Control Register 2 */ +/*! @{ */ #define SIM_SCGC2_ENET_MASK (0x1U) #define SIM_SCGC2_ENET_SHIFT (0U) +/*! ENET - ENET Clock Gate Control + * 0b0..Clock disabled + * 0b1..Clock enabled + */ #define SIM_SCGC2_ENET(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC2_ENET_SHIFT)) & SIM_SCGC2_ENET_MASK) #define SIM_SCGC2_DAC0_MASK (0x1000U) #define SIM_SCGC2_DAC0_SHIFT (12U) +/*! DAC0 - DAC0 Clock Gate Control + * 0b0..Clock disabled + * 0b1..Clock enabled + */ #define SIM_SCGC2_DAC0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC2_DAC0_SHIFT)) & SIM_SCGC2_DAC0_MASK) #define SIM_SCGC2_DAC1_MASK (0x2000U) #define SIM_SCGC2_DAC1_SHIFT (13U) +/*! DAC1 - DAC1 Clock Gate Control + * 0b0..Clock disabled + * 0b1..Clock enabled + */ #define SIM_SCGC2_DAC1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC2_DAC1_SHIFT)) & SIM_SCGC2_DAC1_MASK) +/*! @} */ /*! @name SCGC3 - System Clock Gating Control Register 3 */ +/*! @{ */ #define SIM_SCGC3_RNGA_MASK (0x1U) #define SIM_SCGC3_RNGA_SHIFT (0U) +/*! RNGA - RNGA Clock Gate Control + * 0b0..Clock disabled + * 0b1..Clock enabled + */ #define SIM_SCGC3_RNGA(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_RNGA_SHIFT)) & SIM_SCGC3_RNGA_MASK) #define SIM_SCGC3_SPI2_MASK (0x1000U) #define SIM_SCGC3_SPI2_SHIFT (12U) +/*! SPI2 - SPI2 Clock Gate Control + * 0b0..Clock disabled + * 0b1..Clock enabled + */ #define SIM_SCGC3_SPI2(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_SPI2_SHIFT)) & SIM_SCGC3_SPI2_MASK) #define SIM_SCGC3_SDHC_MASK (0x20000U) #define SIM_SCGC3_SDHC_SHIFT (17U) +/*! SDHC - SDHC Clock Gate Control + * 0b0..Clock disabled + * 0b1..Clock enabled + */ #define SIM_SCGC3_SDHC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_SDHC_SHIFT)) & SIM_SCGC3_SDHC_MASK) #define SIM_SCGC3_FTM2_MASK (0x1000000U) #define SIM_SCGC3_FTM2_SHIFT (24U) +/*! FTM2 - FTM2 Clock Gate Control + * 0b0..Clock disabled + * 0b1..Clock enabled + */ #define SIM_SCGC3_FTM2(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_FTM2_SHIFT)) & SIM_SCGC3_FTM2_MASK) #define SIM_SCGC3_FTM3_MASK (0x2000000U) #define SIM_SCGC3_FTM3_SHIFT (25U) +/*! FTM3 - FTM3 Clock Gate Control + * 0b0..Clock disabled + * 0b1..Clock enabled + */ #define SIM_SCGC3_FTM3(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_FTM3_SHIFT)) & SIM_SCGC3_FTM3_MASK) #define SIM_SCGC3_ADC1_MASK (0x8000000U) #define SIM_SCGC3_ADC1_SHIFT (27U) +/*! ADC1 - ADC1 Clock Gate Control + * 0b0..Clock disabled + * 0b1..Clock enabled + */ #define SIM_SCGC3_ADC1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_ADC1_SHIFT)) & SIM_SCGC3_ADC1_MASK) +/*! @} */ /*! @name SCGC4 - System Clock Gating Control Register 4 */ +/*! @{ */ #define SIM_SCGC4_EWM_MASK (0x2U) #define SIM_SCGC4_EWM_SHIFT (1U) +/*! EWM - EWM Clock Gate Control + * 0b0..Clock disabled + * 0b1..Clock enabled + */ #define SIM_SCGC4_EWM(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_EWM_SHIFT)) & SIM_SCGC4_EWM_MASK) #define SIM_SCGC4_CMT_MASK (0x4U) #define SIM_SCGC4_CMT_SHIFT (2U) +/*! CMT - CMT Clock Gate Control + * 0b0..Clock disabled + * 0b1..Clock enabled + */ #define SIM_SCGC4_CMT(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_CMT_SHIFT)) & SIM_SCGC4_CMT_MASK) #define SIM_SCGC4_I2C0_MASK (0x40U) #define SIM_SCGC4_I2C0_SHIFT (6U) +/*! I2C0 - I2C0 Clock Gate Control + * 0b0..Clock disabled + * 0b1..Clock enabled + */ #define SIM_SCGC4_I2C0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_I2C0_SHIFT)) & SIM_SCGC4_I2C0_MASK) #define SIM_SCGC4_I2C1_MASK (0x80U) #define SIM_SCGC4_I2C1_SHIFT (7U) +/*! I2C1 - I2C1 Clock Gate Control + * 0b0..Clock disabled + * 0b1..Clock enabled + */ #define SIM_SCGC4_I2C1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_I2C1_SHIFT)) & SIM_SCGC4_I2C1_MASK) #define SIM_SCGC4_UART0_MASK (0x400U) #define SIM_SCGC4_UART0_SHIFT (10U) +/*! UART0 - UART0 Clock Gate Control + * 0b0..Clock disabled + * 0b1..Clock enabled + */ #define SIM_SCGC4_UART0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_UART0_SHIFT)) & SIM_SCGC4_UART0_MASK) #define SIM_SCGC4_UART1_MASK (0x800U) #define SIM_SCGC4_UART1_SHIFT (11U) +/*! UART1 - UART1 Clock Gate Control + * 0b0..Clock disabled + * 0b1..Clock enabled + */ #define SIM_SCGC4_UART1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_UART1_SHIFT)) & SIM_SCGC4_UART1_MASK) #define SIM_SCGC4_UART2_MASK (0x1000U) #define SIM_SCGC4_UART2_SHIFT (12U) +/*! UART2 - UART2 Clock Gate Control + * 0b0..Clock disabled + * 0b1..Clock enabled + */ #define SIM_SCGC4_UART2(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_UART2_SHIFT)) & SIM_SCGC4_UART2_MASK) #define SIM_SCGC4_UART3_MASK (0x2000U) #define SIM_SCGC4_UART3_SHIFT (13U) +/*! UART3 - UART3 Clock Gate Control + * 0b0..Clock disabled + * 0b1..Clock enabled + */ #define SIM_SCGC4_UART3(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_UART3_SHIFT)) & SIM_SCGC4_UART3_MASK) #define SIM_SCGC4_USBOTG_MASK (0x40000U) #define SIM_SCGC4_USBOTG_SHIFT (18U) +/*! USBOTG - USB Clock Gate Control + * 0b0..Clock disabled + * 0b1..Clock enabled + */ #define SIM_SCGC4_USBOTG(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_USBOTG_SHIFT)) & SIM_SCGC4_USBOTG_MASK) #define SIM_SCGC4_CMP_MASK (0x80000U) #define SIM_SCGC4_CMP_SHIFT (19U) +/*! CMP - Comparator Clock Gate Control + * 0b0..Clock disabled + * 0b1..Clock enabled + */ #define SIM_SCGC4_CMP(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_CMP_SHIFT)) & SIM_SCGC4_CMP_MASK) #define SIM_SCGC4_VREF_MASK (0x100000U) #define SIM_SCGC4_VREF_SHIFT (20U) +/*! VREF - VREF Clock Gate Control + * 0b0..Clock disabled + * 0b1..Clock enabled + */ #define SIM_SCGC4_VREF(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_VREF_SHIFT)) & SIM_SCGC4_VREF_MASK) +/*! @} */ /*! @name SCGC5 - System Clock Gating Control Register 5 */ +/*! @{ */ #define SIM_SCGC5_LPTMR_MASK (0x1U) #define SIM_SCGC5_LPTMR_SHIFT (0U) +/*! LPTMR - Low Power Timer Access Control + * 0b0..Access disabled + * 0b1..Access enabled + */ #define SIM_SCGC5_LPTMR(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_LPTMR_SHIFT)) & SIM_SCGC5_LPTMR_MASK) #define SIM_SCGC5_PORTA_MASK (0x200U) #define SIM_SCGC5_PORTA_SHIFT (9U) +/*! PORTA - Port A Clock Gate Control + * 0b0..Clock disabled + * 0b1..Clock enabled + */ #define SIM_SCGC5_PORTA(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTA_SHIFT)) & SIM_SCGC5_PORTA_MASK) #define SIM_SCGC5_PORTB_MASK (0x400U) #define SIM_SCGC5_PORTB_SHIFT (10U) +/*! PORTB - Port B Clock Gate Control + * 0b0..Clock disabled + * 0b1..Clock enabled + */ #define SIM_SCGC5_PORTB(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTB_SHIFT)) & SIM_SCGC5_PORTB_MASK) #define SIM_SCGC5_PORTC_MASK (0x800U) #define SIM_SCGC5_PORTC_SHIFT (11U) +/*! PORTC - Port C Clock Gate Control + * 0b0..Clock disabled + * 0b1..Clock enabled + */ #define SIM_SCGC5_PORTC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTC_SHIFT)) & SIM_SCGC5_PORTC_MASK) #define SIM_SCGC5_PORTD_MASK (0x1000U) #define SIM_SCGC5_PORTD_SHIFT (12U) +/*! PORTD - Port D Clock Gate Control + * 0b0..Clock disabled + * 0b1..Clock enabled + */ #define SIM_SCGC5_PORTD(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTD_SHIFT)) & SIM_SCGC5_PORTD_MASK) #define SIM_SCGC5_PORTE_MASK (0x2000U) #define SIM_SCGC5_PORTE_SHIFT (13U) +/*! PORTE - Port E Clock Gate Control + * 0b0..Clock disabled + * 0b1..Clock enabled + */ #define SIM_SCGC5_PORTE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTE_SHIFT)) & SIM_SCGC5_PORTE_MASK) +/*! @} */ /*! @name SCGC6 - System Clock Gating Control Register 6 */ +/*! @{ */ #define SIM_SCGC6_FTF_MASK (0x1U) #define SIM_SCGC6_FTF_SHIFT (0U) +/*! FTF - Flash Memory Clock Gate Control + * 0b0..Clock disabled + * 0b1..Clock enabled + */ #define SIM_SCGC6_FTF(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FTF_SHIFT)) & SIM_SCGC6_FTF_MASK) #define SIM_SCGC6_DMAMUX_MASK (0x2U) #define SIM_SCGC6_DMAMUX_SHIFT (1U) +/*! DMAMUX - DMA Mux Clock Gate Control + * 0b0..Clock disabled + * 0b1..Clock enabled + */ #define SIM_SCGC6_DMAMUX(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_DMAMUX_SHIFT)) & SIM_SCGC6_DMAMUX_MASK) #define SIM_SCGC6_FLEXCAN0_MASK (0x10U) #define SIM_SCGC6_FLEXCAN0_SHIFT (4U) +/*! FLEXCAN0 - FlexCAN0 Clock Gate Control + * 0b0..Clock disabled + * 0b1..Clock enabled + */ #define SIM_SCGC6_FLEXCAN0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FLEXCAN0_SHIFT)) & SIM_SCGC6_FLEXCAN0_MASK) #define SIM_SCGC6_RNGA_MASK (0x200U) #define SIM_SCGC6_RNGA_SHIFT (9U) #define SIM_SCGC6_RNGA(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_RNGA_SHIFT)) & SIM_SCGC6_RNGA_MASK) #define SIM_SCGC6_SPI0_MASK (0x1000U) #define SIM_SCGC6_SPI0_SHIFT (12U) +/*! SPI0 - SPI0 Clock Gate Control + * 0b0..Clock disabled + * 0b1..Clock enabled + */ #define SIM_SCGC6_SPI0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_SPI0_SHIFT)) & SIM_SCGC6_SPI0_MASK) #define SIM_SCGC6_SPI1_MASK (0x2000U) #define SIM_SCGC6_SPI1_SHIFT (13U) +/*! SPI1 - SPI1 Clock Gate Control + * 0b0..Clock disabled + * 0b1..Clock enabled + */ #define SIM_SCGC6_SPI1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_SPI1_SHIFT)) & SIM_SCGC6_SPI1_MASK) #define SIM_SCGC6_I2S_MASK (0x8000U) #define SIM_SCGC6_I2S_SHIFT (15U) +/*! I2S - I2S Clock Gate Control + * 0b0..Clock disabled + * 0b1..Clock enabled + */ #define SIM_SCGC6_I2S(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_I2S_SHIFT)) & SIM_SCGC6_I2S_MASK) #define SIM_SCGC6_CRC_MASK (0x40000U) #define SIM_SCGC6_CRC_SHIFT (18U) +/*! CRC - CRC Clock Gate Control + * 0b0..Clock disabled + * 0b1..Clock enabled + */ #define SIM_SCGC6_CRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_CRC_SHIFT)) & SIM_SCGC6_CRC_MASK) #define SIM_SCGC6_USBDCD_MASK (0x200000U) #define SIM_SCGC6_USBDCD_SHIFT (21U) +/*! USBDCD - USB DCD Clock Gate Control + * 0b0..Clock disabled + * 0b1..Clock enabled + */ #define SIM_SCGC6_USBDCD(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_USBDCD_SHIFT)) & SIM_SCGC6_USBDCD_MASK) #define SIM_SCGC6_PDB_MASK (0x400000U) #define SIM_SCGC6_PDB_SHIFT (22U) +/*! PDB - PDB Clock Gate Control + * 0b0..Clock disabled + * 0b1..Clock enabled + */ #define SIM_SCGC6_PDB(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_PDB_SHIFT)) & SIM_SCGC6_PDB_MASK) #define SIM_SCGC6_PIT_MASK (0x800000U) #define SIM_SCGC6_PIT_SHIFT (23U) +/*! PIT - PIT Clock Gate Control + * 0b0..Clock disabled + * 0b1..Clock enabled + */ #define SIM_SCGC6_PIT(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_PIT_SHIFT)) & SIM_SCGC6_PIT_MASK) #define SIM_SCGC6_FTM0_MASK (0x1000000U) #define SIM_SCGC6_FTM0_SHIFT (24U) +/*! FTM0 - FTM0 Clock Gate Control + * 0b0..Clock disabled + * 0b1..Clock enabled + */ #define SIM_SCGC6_FTM0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FTM0_SHIFT)) & SIM_SCGC6_FTM0_MASK) #define SIM_SCGC6_FTM1_MASK (0x2000000U) #define SIM_SCGC6_FTM1_SHIFT (25U) +/*! FTM1 - FTM1 Clock Gate Control + * 0b0..Clock disabled + * 0b1..Clock enabled + */ #define SIM_SCGC6_FTM1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FTM1_SHIFT)) & SIM_SCGC6_FTM1_MASK) #define SIM_SCGC6_FTM2_MASK (0x4000000U) #define SIM_SCGC6_FTM2_SHIFT (26U) +/*! FTM2 - FTM2 Clock Gate Control + * 0b0..Clock disabled + * 0b1..Clock enabled + */ #define SIM_SCGC6_FTM2(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FTM2_SHIFT)) & SIM_SCGC6_FTM2_MASK) #define SIM_SCGC6_ADC0_MASK (0x8000000U) #define SIM_SCGC6_ADC0_SHIFT (27U) +/*! ADC0 - ADC0 Clock Gate Control + * 0b0..Clock disabled + * 0b1..Clock enabled + */ #define SIM_SCGC6_ADC0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_ADC0_SHIFT)) & SIM_SCGC6_ADC0_MASK) #define SIM_SCGC6_RTC_MASK (0x20000000U) #define SIM_SCGC6_RTC_SHIFT (29U) +/*! RTC - RTC Access Control + * 0b0..Access and interrupts disabled + * 0b1..Access and interrupts enabled + */ #define SIM_SCGC6_RTC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_RTC_SHIFT)) & SIM_SCGC6_RTC_MASK) #define SIM_SCGC6_DAC0_MASK (0x80000000U) #define SIM_SCGC6_DAC0_SHIFT (31U) +/*! DAC0 - DAC0 Clock Gate Control + * 0b0..Clock disabled + * 0b1..Clock enabled + */ #define SIM_SCGC6_DAC0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_DAC0_SHIFT)) & SIM_SCGC6_DAC0_MASK) +/*! @} */ /*! @name SCGC7 - System Clock Gating Control Register 7 */ +/*! @{ */ #define SIM_SCGC7_FLEXBUS_MASK (0x1U) #define SIM_SCGC7_FLEXBUS_SHIFT (0U) +/*! FLEXBUS - FlexBus Clock Gate Control + * 0b0..Clock disabled + * 0b1..Clock enabled + */ #define SIM_SCGC7_FLEXBUS(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC7_FLEXBUS_SHIFT)) & SIM_SCGC7_FLEXBUS_MASK) #define SIM_SCGC7_DMA_MASK (0x2U) #define SIM_SCGC7_DMA_SHIFT (1U) +/*! DMA - DMA Clock Gate Control + * 0b0..Clock disabled + * 0b1..Clock enabled + */ #define SIM_SCGC7_DMA(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC7_DMA_SHIFT)) & SIM_SCGC7_DMA_MASK) #define SIM_SCGC7_MPU_MASK (0x4U) #define SIM_SCGC7_MPU_SHIFT (2U) +/*! MPU - MPU Clock Gate Control + * 0b0..Clock disabled + * 0b1..Clock enabled + */ #define SIM_SCGC7_MPU(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC7_MPU_SHIFT)) & SIM_SCGC7_MPU_MASK) +/*! @} */ /*! @name CLKDIV1 - System Clock Divider Register 1 */ +/*! @{ */ #define SIM_CLKDIV1_OUTDIV4_MASK (0xF0000U) #define SIM_CLKDIV1_OUTDIV4_SHIFT (16U) +/*! OUTDIV4 - Clock 4 output divider value + * 0b0000..Divide-by-1. + * 0b0001..Divide-by-2. + * 0b0010..Divide-by-3. + * 0b0011..Divide-by-4. + * 0b0100..Divide-by-5. + * 0b0101..Divide-by-6. + * 0b0110..Divide-by-7. + * 0b0111..Divide-by-8. + * 0b1000..Divide-by-9. + * 0b1001..Divide-by-10. + * 0b1010..Divide-by-11. + * 0b1011..Divide-by-12. + * 0b1100..Divide-by-13. + * 0b1101..Divide-by-14. + * 0b1110..Divide-by-15. + * 0b1111..Divide-by-16. + */ #define SIM_CLKDIV1_OUTDIV4(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV1_OUTDIV4_SHIFT)) & SIM_CLKDIV1_OUTDIV4_MASK) #define SIM_CLKDIV1_OUTDIV3_MASK (0xF00000U) #define SIM_CLKDIV1_OUTDIV3_SHIFT (20U) +/*! OUTDIV3 - Clock 3 output divider value + * 0b0000..Divide-by-1. + * 0b0001..Divide-by-2. + * 0b0010..Divide-by-3. + * 0b0011..Divide-by-4. + * 0b0100..Divide-by-5. + * 0b0101..Divide-by-6. + * 0b0110..Divide-by-7. + * 0b0111..Divide-by-8. + * 0b1000..Divide-by-9. + * 0b1001..Divide-by-10. + * 0b1010..Divide-by-11. + * 0b1011..Divide-by-12. + * 0b1100..Divide-by-13. + * 0b1101..Divide-by-14. + * 0b1110..Divide-by-15. + * 0b1111..Divide-by-16. + */ #define SIM_CLKDIV1_OUTDIV3(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV1_OUTDIV3_SHIFT)) & SIM_CLKDIV1_OUTDIV3_MASK) #define SIM_CLKDIV1_OUTDIV2_MASK (0xF000000U) #define SIM_CLKDIV1_OUTDIV2_SHIFT (24U) +/*! OUTDIV2 - Clock 2 output divider value + * 0b0000..Divide-by-1. + * 0b0001..Divide-by-2. + * 0b0010..Divide-by-3. + * 0b0011..Divide-by-4. + * 0b0100..Divide-by-5. + * 0b0101..Divide-by-6. + * 0b0110..Divide-by-7. + * 0b0111..Divide-by-8. + * 0b1000..Divide-by-9. + * 0b1001..Divide-by-10. + * 0b1010..Divide-by-11. + * 0b1011..Divide-by-12. + * 0b1100..Divide-by-13. + * 0b1101..Divide-by-14. + * 0b1110..Divide-by-15. + * 0b1111..Divide-by-16. + */ #define SIM_CLKDIV1_OUTDIV2(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV1_OUTDIV2_SHIFT)) & SIM_CLKDIV1_OUTDIV2_MASK) #define SIM_CLKDIV1_OUTDIV1_MASK (0xF0000000U) #define SIM_CLKDIV1_OUTDIV1_SHIFT (28U) +/*! OUTDIV1 - Clock 1 output divider value + * 0b0000..Divide-by-1. + * 0b0001..Divide-by-2. + * 0b0010..Divide-by-3. + * 0b0011..Divide-by-4. + * 0b0100..Divide-by-5. + * 0b0101..Divide-by-6. + * 0b0110..Divide-by-7. + * 0b0111..Divide-by-8. + * 0b1000..Divide-by-9. + * 0b1001..Divide-by-10. + * 0b1010..Divide-by-11. + * 0b1011..Divide-by-12. + * 0b1100..Divide-by-13. + * 0b1101..Divide-by-14. + * 0b1110..Divide-by-15. + * 0b1111..Divide-by-16. + */ #define SIM_CLKDIV1_OUTDIV1(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV1_OUTDIV1_SHIFT)) & SIM_CLKDIV1_OUTDIV1_MASK) +/*! @} */ /*! @name CLKDIV2 - System Clock Divider Register 2 */ +/*! @{ */ #define SIM_CLKDIV2_USBFRAC_MASK (0x1U) #define SIM_CLKDIV2_USBFRAC_SHIFT (0U) #define SIM_CLKDIV2_USBFRAC(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV2_USBFRAC_SHIFT)) & SIM_CLKDIV2_USBFRAC_MASK) #define SIM_CLKDIV2_USBDIV_MASK (0xEU) #define SIM_CLKDIV2_USBDIV_SHIFT (1U) #define SIM_CLKDIV2_USBDIV(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV2_USBDIV_SHIFT)) & SIM_CLKDIV2_USBDIV_MASK) +/*! @} */ /*! @name FCFG1 - Flash Configuration Register 1 */ +/*! @{ */ #define SIM_FCFG1_FLASHDIS_MASK (0x1U) #define SIM_FCFG1_FLASHDIS_SHIFT (0U) +/*! FLASHDIS - Flash Disable + * 0b0..Flash is enabled + * 0b1..Flash is disabled + */ #define SIM_FCFG1_FLASHDIS(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_FLASHDIS_SHIFT)) & SIM_FCFG1_FLASHDIS_MASK) #define SIM_FCFG1_FLASHDOZE_MASK (0x2U) #define SIM_FCFG1_FLASHDOZE_SHIFT (1U) +/*! FLASHDOZE - Flash Doze + * 0b0..Flash remains enabled during Wait mode + * 0b1..Flash is disabled for the duration of Wait mode + */ #define SIM_FCFG1_FLASHDOZE(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_FLASHDOZE_SHIFT)) & SIM_FCFG1_FLASHDOZE_MASK) #define SIM_FCFG1_DEPART_MASK (0xF00U) #define SIM_FCFG1_DEPART_SHIFT (8U) #define SIM_FCFG1_DEPART(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_DEPART_SHIFT)) & SIM_FCFG1_DEPART_MASK) #define SIM_FCFG1_EESIZE_MASK (0xF0000U) #define SIM_FCFG1_EESIZE_SHIFT (16U) +/*! EESIZE - EEPROM size + * 0b0000..16 KB + * 0b0001..8 KB + * 0b0010..4 KB + * 0b0011..2 KB + * 0b0100..1 KB + * 0b0101..512 Bytes + * 0b0110..256 Bytes + * 0b0111..128 Bytes + * 0b1000..64 Bytes + * 0b1001..32 Bytes + * 0b1111..0 Bytes + */ #define SIM_FCFG1_EESIZE(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_EESIZE_SHIFT)) & SIM_FCFG1_EESIZE_MASK) #define SIM_FCFG1_PFSIZE_MASK (0xF000000U) #define SIM_FCFG1_PFSIZE_SHIFT (24U) +/*! PFSIZE - Program flash size + * 0b0011..32 KB of program flash memory + * 0b0101..64 KB of program flash memory + * 0b0111..128 KB of program flash memory + * 0b1001..256 KB of program flash memory + * 0b1011..512 KB of program flash memory + * 0b1101..1024 KB of program flash memory + * 0b1111..1024 KB of program flash memory + */ #define SIM_FCFG1_PFSIZE(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_PFSIZE_SHIFT)) & SIM_FCFG1_PFSIZE_MASK) #define SIM_FCFG1_NVMSIZE_MASK (0xF0000000U) #define SIM_FCFG1_NVMSIZE_SHIFT (28U) +/*! NVMSIZE - FlexNVM size + * 0b0000..0 KB of FlexNVM + * 0b0011..32 KB of FlexNVM + * 0b0101..64 KB of FlexNVM + * 0b0111..128 KB of FlexNVM + * 0b1001..256 KB of FlexNVM + * 0b1011..512 KB of FlexNVM + * 0b1111..512 KB of FlexNVM + */ #define SIM_FCFG1_NVMSIZE(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_NVMSIZE_SHIFT)) & SIM_FCFG1_NVMSIZE_MASK) +/*! @} */ /*! @name FCFG2 - Flash Configuration Register 2 */ +/*! @{ */ #define SIM_FCFG2_MAXADDR1_MASK (0x7F0000U) #define SIM_FCFG2_MAXADDR1_SHIFT (16U) #define SIM_FCFG2_MAXADDR1(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG2_MAXADDR1_SHIFT)) & SIM_FCFG2_MAXADDR1_MASK) #define SIM_FCFG2_PFLSH_MASK (0x800000U) #define SIM_FCFG2_PFLSH_SHIFT (23U) +/*! PFLSH - Program flash only + * 0b0..Device supports FlexNVM + * 0b1..Program Flash only, device does not support FlexNVM + */ #define SIM_FCFG2_PFLSH(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG2_PFLSH_SHIFT)) & SIM_FCFG2_PFLSH_MASK) #define SIM_FCFG2_MAXADDR0_MASK (0x7F000000U) #define SIM_FCFG2_MAXADDR0_SHIFT (24U) #define SIM_FCFG2_MAXADDR0(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG2_MAXADDR0_SHIFT)) & SIM_FCFG2_MAXADDR0_MASK) +/*! @} */ /*! @name UIDH - Unique Identification Register High */ +/*! @{ */ #define SIM_UIDH_UID_MASK (0xFFFFFFFFU) #define SIM_UIDH_UID_SHIFT (0U) #define SIM_UIDH_UID(x) (((uint32_t)(((uint32_t)(x)) << SIM_UIDH_UID_SHIFT)) & SIM_UIDH_UID_MASK) +/*! @} */ /*! @name UIDMH - Unique Identification Register Mid-High */ +/*! @{ */ #define SIM_UIDMH_UID_MASK (0xFFFFFFFFU) #define SIM_UIDMH_UID_SHIFT (0U) #define SIM_UIDMH_UID(x) (((uint32_t)(((uint32_t)(x)) << SIM_UIDMH_UID_SHIFT)) & SIM_UIDMH_UID_MASK) +/*! @} */ /*! @name UIDML - Unique Identification Register Mid Low */ +/*! @{ */ #define SIM_UIDML_UID_MASK (0xFFFFFFFFU) #define SIM_UIDML_UID_SHIFT (0U) #define SIM_UIDML_UID(x) (((uint32_t)(((uint32_t)(x)) << SIM_UIDML_UID_SHIFT)) & SIM_UIDML_UID_MASK) +/*! @} */ /*! @name UIDL - Unique Identification Register Low */ +/*! @{ */ #define SIM_UIDL_UID_MASK (0xFFFFFFFFU) #define SIM_UIDL_UID_SHIFT (0U) #define SIM_UIDL_UID(x) (((uint32_t)(((uint32_t)(x)) << SIM_UIDL_UID_SHIFT)) & SIM_UIDL_UID_MASK) +/*! @} */ /*! @@ -10651,42 +18997,100 @@ typedef struct { */ /*! @name PMPROT - Power Mode Protection register */ +/*! @{ */ #define SMC_PMPROT_AVLLS_MASK (0x2U) #define SMC_PMPROT_AVLLS_SHIFT (1U) +/*! AVLLS - Allow Very-Low-Leakage Stop Mode + * 0b0..Any VLLSx mode is not allowed + * 0b1..Any VLLSx mode is allowed + */ #define SMC_PMPROT_AVLLS(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMPROT_AVLLS_SHIFT)) & SMC_PMPROT_AVLLS_MASK) #define SMC_PMPROT_ALLS_MASK (0x8U) #define SMC_PMPROT_ALLS_SHIFT (3U) +/*! ALLS - Allow Low-Leakage Stop Mode + * 0b0..LLS is not allowed + * 0b1..LLS is allowed + */ #define SMC_PMPROT_ALLS(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMPROT_ALLS_SHIFT)) & SMC_PMPROT_ALLS_MASK) #define SMC_PMPROT_AVLP_MASK (0x20U) #define SMC_PMPROT_AVLP_SHIFT (5U) +/*! AVLP - Allow Very-Low-Power Modes + * 0b0..VLPR, VLPW, and VLPS are not allowed. + * 0b1..VLPR, VLPW, and VLPS are allowed. + */ #define SMC_PMPROT_AVLP(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMPROT_AVLP_SHIFT)) & SMC_PMPROT_AVLP_MASK) +/*! @} */ /*! @name PMCTRL - Power Mode Control register */ +/*! @{ */ #define SMC_PMCTRL_STOPM_MASK (0x7U) #define SMC_PMCTRL_STOPM_SHIFT (0U) +/*! STOPM - Stop Mode Control + * 0b000..Normal Stop (STOP) + * 0b001..Reserved + * 0b010..Very-Low-Power Stop (VLPS) + * 0b011..Low-Leakage Stop (LLS) + * 0b100..Very-Low-Leakage Stop (VLLSx) + * 0b101..Reserved + * 0b110..Reseved + * 0b111..Reserved + */ #define SMC_PMCTRL_STOPM(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMCTRL_STOPM_SHIFT)) & SMC_PMCTRL_STOPM_MASK) #define SMC_PMCTRL_STOPA_MASK (0x8U) #define SMC_PMCTRL_STOPA_SHIFT (3U) +/*! STOPA - Stop Aborted + * 0b0..The previous stop mode entry was successsful. + * 0b1..The previous stop mode entry was aborted. + */ #define SMC_PMCTRL_STOPA(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMCTRL_STOPA_SHIFT)) & SMC_PMCTRL_STOPA_MASK) #define SMC_PMCTRL_RUNM_MASK (0x60U) #define SMC_PMCTRL_RUNM_SHIFT (5U) +/*! RUNM - Run Mode Control + * 0b00..Normal Run mode (RUN) + * 0b01..Reserved + * 0b10..Very-Low-Power Run mode (VLPR) + * 0b11..Reserved + */ #define SMC_PMCTRL_RUNM(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMCTRL_RUNM_SHIFT)) & SMC_PMCTRL_RUNM_MASK) #define SMC_PMCTRL_LPWUI_MASK (0x80U) #define SMC_PMCTRL_LPWUI_SHIFT (7U) +/*! LPWUI - Low-Power Wake Up On Interrupt + * 0b0..The system remains in a VLP mode on an interrupt + * 0b1..The system exits to Normal RUN mode on an interrupt + */ #define SMC_PMCTRL_LPWUI(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMCTRL_LPWUI_SHIFT)) & SMC_PMCTRL_LPWUI_MASK) +/*! @} */ /*! @name VLLSCTRL - VLLS Control register */ +/*! @{ */ #define SMC_VLLSCTRL_VLLSM_MASK (0x7U) #define SMC_VLLSCTRL_VLLSM_SHIFT (0U) +/*! VLLSM - VLLS Mode Control + * 0b000..VLLS0 + * 0b001..VLLS1 + * 0b010..VLLS2 + * 0b011..VLLS3 + * 0b100..Reserved + * 0b101..Reserved + * 0b110..Reserved + * 0b111..Reserved + */ #define SMC_VLLSCTRL_VLLSM(x) (((uint8_t)(((uint8_t)(x)) << SMC_VLLSCTRL_VLLSM_SHIFT)) & SMC_VLLSCTRL_VLLSM_MASK) #define SMC_VLLSCTRL_PORPO_MASK (0x20U) #define SMC_VLLSCTRL_PORPO_SHIFT (5U) +/*! PORPO - POR Power Option + * 0b0..POR detect circuit is enabled in VLLS0. + * 0b1..POR detect circuit is disabled in VLLS0. + */ #define SMC_VLLSCTRL_PORPO(x) (((uint8_t)(((uint8_t)(x)) << SMC_VLLSCTRL_PORPO_SHIFT)) & SMC_VLLSCTRL_PORPO_MASK) +/*! @} */ /*! @name PMSTAT - Power Mode Status register */ +/*! @{ */ #define SMC_PMSTAT_PMSTAT_MASK (0x7FU) #define SMC_PMSTAT_PMSTAT_SHIFT (0U) #define SMC_PMSTAT_PMSTAT(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMSTAT_PMSTAT_SHIFT)) & SMC_PMSTAT_PMSTAT_MASK) +/*! @} */ /*! @@ -10756,61 +19160,134 @@ typedef struct { */ /*! @name MCR - Module Configuration Register */ +/*! @{ */ #define SPI_MCR_HALT_MASK (0x1U) #define SPI_MCR_HALT_SHIFT (0U) +/*! HALT - Halt + * 0b0..Start transfers. + * 0b1..Stop transfers. + */ #define SPI_MCR_HALT(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_HALT_SHIFT)) & SPI_MCR_HALT_MASK) #define SPI_MCR_SMPL_PT_MASK (0x300U) #define SPI_MCR_SMPL_PT_SHIFT (8U) +/*! SMPL_PT - Sample Point + * 0b00..0 protocol clock cycles between SCK edge and SIN sample + * 0b01..1 protocol clock cycle between SCK edge and SIN sample + * 0b10..2 protocol clock cycles between SCK edge and SIN sample + * 0b11..Reserved + */ #define SPI_MCR_SMPL_PT(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_SMPL_PT_SHIFT)) & SPI_MCR_SMPL_PT_MASK) #define SPI_MCR_CLR_RXF_MASK (0x400U) #define SPI_MCR_CLR_RXF_SHIFT (10U) +/*! CLR_RXF + * 0b0..Do not clear the RX FIFO counter. + * 0b1..Clear the RX FIFO counter. + */ #define SPI_MCR_CLR_RXF(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_CLR_RXF_SHIFT)) & SPI_MCR_CLR_RXF_MASK) #define SPI_MCR_CLR_TXF_MASK (0x800U) #define SPI_MCR_CLR_TXF_SHIFT (11U) +/*! CLR_TXF - Clear TX FIFO + * 0b0..Do not clear the TX FIFO counter. + * 0b1..Clear the TX FIFO counter. + */ #define SPI_MCR_CLR_TXF(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_CLR_TXF_SHIFT)) & SPI_MCR_CLR_TXF_MASK) #define SPI_MCR_DIS_RXF_MASK (0x1000U) #define SPI_MCR_DIS_RXF_SHIFT (12U) +/*! DIS_RXF - Disable Receive FIFO + * 0b0..RX FIFO is enabled. + * 0b1..RX FIFO is disabled. + */ #define SPI_MCR_DIS_RXF(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_DIS_RXF_SHIFT)) & SPI_MCR_DIS_RXF_MASK) #define SPI_MCR_DIS_TXF_MASK (0x2000U) #define SPI_MCR_DIS_TXF_SHIFT (13U) +/*! DIS_TXF - Disable Transmit FIFO + * 0b0..TX FIFO is enabled. + * 0b1..TX FIFO is disabled. + */ #define SPI_MCR_DIS_TXF(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_DIS_TXF_SHIFT)) & SPI_MCR_DIS_TXF_MASK) #define SPI_MCR_MDIS_MASK (0x4000U) #define SPI_MCR_MDIS_SHIFT (14U) +/*! MDIS - Module Disable + * 0b0..Enables the module clocks. + * 0b1..Allows external logic to disable the module clocks. + */ #define SPI_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_MDIS_SHIFT)) & SPI_MCR_MDIS_MASK) #define SPI_MCR_DOZE_MASK (0x8000U) #define SPI_MCR_DOZE_SHIFT (15U) +/*! DOZE - Doze Enable + * 0b0..Doze mode has no effect on the module. + * 0b1..Doze mode disables the module. + */ #define SPI_MCR_DOZE(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_DOZE_SHIFT)) & SPI_MCR_DOZE_MASK) #define SPI_MCR_PCSIS_MASK (0x3F0000U) #define SPI_MCR_PCSIS_SHIFT (16U) +/*! PCSIS - Peripheral Chip Select x Inactive State + * 0b000000..The inactive state of PCSx is low. + * 0b000001..The inactive state of PCSx is high. + */ #define SPI_MCR_PCSIS(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_PCSIS_SHIFT)) & SPI_MCR_PCSIS_MASK) #define SPI_MCR_ROOE_MASK (0x1000000U) #define SPI_MCR_ROOE_SHIFT (24U) +/*! ROOE - Receive FIFO Overflow Overwrite Enable + * 0b0..Incoming data is ignored. + * 0b1..Incoming data is shifted into the shift register. + */ #define SPI_MCR_ROOE(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_ROOE_SHIFT)) & SPI_MCR_ROOE_MASK) #define SPI_MCR_PCSSE_MASK (0x2000000U) #define SPI_MCR_PCSSE_SHIFT (25U) +/*! PCSSE - Peripheral Chip Select Strobe Enable + * 0b0..PCS5/ PCSS is used as the Peripheral Chip Select[5] signal. + * 0b1..PCS5/ PCSS is used as an active-low PCS Strobe signal. + */ #define SPI_MCR_PCSSE(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_PCSSE_SHIFT)) & SPI_MCR_PCSSE_MASK) #define SPI_MCR_MTFE_MASK (0x4000000U) #define SPI_MCR_MTFE_SHIFT (26U) +/*! MTFE - Modified Timing Format Enable + * 0b0..Modified SPI transfer format disabled. + * 0b1..Modified SPI transfer format enabled. + */ #define SPI_MCR_MTFE(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_MTFE_SHIFT)) & SPI_MCR_MTFE_MASK) #define SPI_MCR_FRZ_MASK (0x8000000U) #define SPI_MCR_FRZ_SHIFT (27U) +/*! FRZ - Freeze + * 0b0..Do not halt serial transfers in Debug mode. + * 0b1..Halt serial transfers in Debug mode. + */ #define SPI_MCR_FRZ(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_FRZ_SHIFT)) & SPI_MCR_FRZ_MASK) #define SPI_MCR_DCONF_MASK (0x30000000U) #define SPI_MCR_DCONF_SHIFT (28U) +/*! DCONF - SPI Configuration. + * 0b00..SPI + * 0b01..Reserved + * 0b10..Reserved + * 0b11..Reserved + */ #define SPI_MCR_DCONF(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_DCONF_SHIFT)) & SPI_MCR_DCONF_MASK) #define SPI_MCR_CONT_SCKE_MASK (0x40000000U) #define SPI_MCR_CONT_SCKE_SHIFT (30U) +/*! CONT_SCKE - Continuous SCK Enable + * 0b0..Continuous SCK disabled. + * 0b1..Continuous SCK enabled. + */ #define SPI_MCR_CONT_SCKE(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_CONT_SCKE_SHIFT)) & SPI_MCR_CONT_SCKE_MASK) #define SPI_MCR_MSTR_MASK (0x80000000U) #define SPI_MCR_MSTR_SHIFT (31U) +/*! MSTR - Master/Slave Mode Select + * 0b0..Enables Slave mode + * 0b1..Enables Master mode + */ #define SPI_MCR_MSTR(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_MSTR_SHIFT)) & SPI_MCR_MSTR_MASK) +/*! @} */ /*! @name TCR - Transfer Count Register */ +/*! @{ */ #define SPI_TCR_SPI_TCNT_MASK (0xFFFF0000U) #define SPI_TCR_SPI_TCNT_SHIFT (16U) #define SPI_TCR_SPI_TCNT(x) (((uint32_t)(((uint32_t)(x)) << SPI_TCR_SPI_TCNT_SHIFT)) & SPI_TCR_SPI_TCNT_MASK) +/*! @} */ /*! @name CTAR - Clock and Transfer Attributes Register (In Master Mode) */ +/*! @{ */ #define SPI_CTAR_BR_MASK (0xFU) #define SPI_CTAR_BR_SHIFT (0U) #define SPI_CTAR_BR(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_BR_SHIFT)) & SPI_CTAR_BR_MASK) @@ -10825,50 +19302,102 @@ typedef struct { #define SPI_CTAR_CSSCK(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_CSSCK_SHIFT)) & SPI_CTAR_CSSCK_MASK) #define SPI_CTAR_PBR_MASK (0x30000U) #define SPI_CTAR_PBR_SHIFT (16U) +/*! PBR - Baud Rate Prescaler + * 0b00..Baud Rate Prescaler value is 2. + * 0b01..Baud Rate Prescaler value is 3. + * 0b10..Baud Rate Prescaler value is 5. + * 0b11..Baud Rate Prescaler value is 7. + */ #define SPI_CTAR_PBR(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_PBR_SHIFT)) & SPI_CTAR_PBR_MASK) #define SPI_CTAR_PDT_MASK (0xC0000U) #define SPI_CTAR_PDT_SHIFT (18U) +/*! PDT - Delay after Transfer Prescaler + * 0b00..Delay after Transfer Prescaler value is 1. + * 0b01..Delay after Transfer Prescaler value is 3. + * 0b10..Delay after Transfer Prescaler value is 5. + * 0b11..Delay after Transfer Prescaler value is 7. + */ #define SPI_CTAR_PDT(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_PDT_SHIFT)) & SPI_CTAR_PDT_MASK) #define SPI_CTAR_PASC_MASK (0x300000U) #define SPI_CTAR_PASC_SHIFT (20U) +/*! PASC - After SCK Delay Prescaler + * 0b00..Delay after Transfer Prescaler value is 1. + * 0b01..Delay after Transfer Prescaler value is 3. + * 0b10..Delay after Transfer Prescaler value is 5. + * 0b11..Delay after Transfer Prescaler value is 7. + */ #define SPI_CTAR_PASC(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_PASC_SHIFT)) & SPI_CTAR_PASC_MASK) #define SPI_CTAR_PCSSCK_MASK (0xC00000U) #define SPI_CTAR_PCSSCK_SHIFT (22U) +/*! PCSSCK - PCS to SCK Delay Prescaler + * 0b00..PCS to SCK Prescaler value is 1. + * 0b01..PCS to SCK Prescaler value is 3. + * 0b10..PCS to SCK Prescaler value is 5. + * 0b11..PCS to SCK Prescaler value is 7. + */ #define SPI_CTAR_PCSSCK(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_PCSSCK_SHIFT)) & SPI_CTAR_PCSSCK_MASK) #define SPI_CTAR_LSBFE_MASK (0x1000000U) #define SPI_CTAR_LSBFE_SHIFT (24U) +/*! LSBFE - LSB First + * 0b0..Data is transferred MSB first. + * 0b1..Data is transferred LSB first. + */ #define SPI_CTAR_LSBFE(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_LSBFE_SHIFT)) & SPI_CTAR_LSBFE_MASK) #define SPI_CTAR_CPHA_MASK (0x2000000U) #define SPI_CTAR_CPHA_SHIFT (25U) +/*! CPHA - Clock Phase + * 0b0..Data is captured on the leading edge of SCK and changed on the following edge. + * 0b1..Data is changed on the leading edge of SCK and captured on the following edge. + */ #define SPI_CTAR_CPHA(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_CPHA_SHIFT)) & SPI_CTAR_CPHA_MASK) #define SPI_CTAR_CPOL_MASK (0x4000000U) #define SPI_CTAR_CPOL_SHIFT (26U) +/*! CPOL - Clock Polarity + * 0b0..The inactive state value of SCK is low. + * 0b1..The inactive state value of SCK is high. + */ #define SPI_CTAR_CPOL(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_CPOL_SHIFT)) & SPI_CTAR_CPOL_MASK) #define SPI_CTAR_FMSZ_MASK (0x78000000U) #define SPI_CTAR_FMSZ_SHIFT (27U) #define SPI_CTAR_FMSZ(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_FMSZ_SHIFT)) & SPI_CTAR_FMSZ_MASK) #define SPI_CTAR_DBR_MASK (0x80000000U) #define SPI_CTAR_DBR_SHIFT (31U) +/*! DBR - Double Baud Rate + * 0b0..The baud rate is computed normally with a 50/50 duty cycle. + * 0b1..The baud rate is doubled with the duty cycle depending on the Baud Rate Prescaler. + */ #define SPI_CTAR_DBR(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_DBR_SHIFT)) & SPI_CTAR_DBR_MASK) +/*! @} */ /* The count of SPI_CTAR */ #define SPI_CTAR_COUNT (2U) /*! @name CTAR_SLAVE - Clock and Transfer Attributes Register (In Slave Mode) */ +/*! @{ */ #define SPI_CTAR_SLAVE_CPHA_MASK (0x2000000U) #define SPI_CTAR_SLAVE_CPHA_SHIFT (25U) +/*! CPHA - Clock Phase + * 0b0..Data is captured on the leading edge of SCK and changed on the following edge. + * 0b1..Data is changed on the leading edge of SCK and captured on the following edge. + */ #define SPI_CTAR_SLAVE_CPHA(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_SLAVE_CPHA_SHIFT)) & SPI_CTAR_SLAVE_CPHA_MASK) #define SPI_CTAR_SLAVE_CPOL_MASK (0x4000000U) #define SPI_CTAR_SLAVE_CPOL_SHIFT (26U) +/*! CPOL - Clock Polarity + * 0b0..The inactive state value of SCK is low. + * 0b1..The inactive state value of SCK is high. + */ #define SPI_CTAR_SLAVE_CPOL(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_SLAVE_CPOL_SHIFT)) & SPI_CTAR_SLAVE_CPOL_MASK) #define SPI_CTAR_SLAVE_FMSZ_MASK (0xF8000000U) #define SPI_CTAR_SLAVE_FMSZ_SHIFT (27U) #define SPI_CTAR_SLAVE_FMSZ(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_SLAVE_FMSZ_SHIFT)) & SPI_CTAR_SLAVE_FMSZ_MASK) +/*! @} */ /* The count of SPI_CTAR_SLAVE */ #define SPI_CTAR_SLAVE_COUNT (1U) /*! @name SR - Status Register */ +/*! @{ */ #define SPI_SR_POPNXTPTR_MASK (0xFU) #define SPI_SR_POPNXTPTR_SHIFT (0U) #define SPI_SR_POPNXTPTR(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_POPNXTPTR_SHIFT)) & SPI_SR_POPNXTPTR_MASK) @@ -10883,133 +19412,244 @@ typedef struct { #define SPI_SR_TXCTR(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_TXCTR_SHIFT)) & SPI_SR_TXCTR_MASK) #define SPI_SR_RFDF_MASK (0x20000U) #define SPI_SR_RFDF_SHIFT (17U) +/*! RFDF - Receive FIFO Drain Flag + * 0b0..RX FIFO is empty. + * 0b1..RX FIFO is not empty. + */ #define SPI_SR_RFDF(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_RFDF_SHIFT)) & SPI_SR_RFDF_MASK) #define SPI_SR_RFOF_MASK (0x80000U) #define SPI_SR_RFOF_SHIFT (19U) +/*! RFOF - Receive FIFO Overflow Flag + * 0b0..No Rx FIFO overflow. + * 0b1..Rx FIFO overflow has occurred. + */ #define SPI_SR_RFOF(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_RFOF_SHIFT)) & SPI_SR_RFOF_MASK) #define SPI_SR_TFFF_MASK (0x2000000U) #define SPI_SR_TFFF_SHIFT (25U) +/*! TFFF - Transmit FIFO Fill Flag + * 0b0..TX FIFO is full. + * 0b1..TX FIFO is not full. + */ #define SPI_SR_TFFF(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_TFFF_SHIFT)) & SPI_SR_TFFF_MASK) #define SPI_SR_TFUF_MASK (0x8000000U) #define SPI_SR_TFUF_SHIFT (27U) +/*! TFUF - Transmit FIFO Underflow Flag + * 0b0..No TX FIFO underflow. + * 0b1..TX FIFO underflow has occurred. + */ #define SPI_SR_TFUF(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_TFUF_SHIFT)) & SPI_SR_TFUF_MASK) #define SPI_SR_EOQF_MASK (0x10000000U) #define SPI_SR_EOQF_SHIFT (28U) +/*! EOQF - End of Queue Flag + * 0b0..EOQ is not set in the executing command. + * 0b1..EOQ is set in the executing SPI command. + */ #define SPI_SR_EOQF(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_EOQF_SHIFT)) & SPI_SR_EOQF_MASK) #define SPI_SR_TXRXS_MASK (0x40000000U) #define SPI_SR_TXRXS_SHIFT (30U) +/*! TXRXS - TX and RX Status + * 0b0..Transmit and receive operations are disabled (The module is in Stopped state). + * 0b1..Transmit and receive operations are enabled (The module is in Running state). + */ #define SPI_SR_TXRXS(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_TXRXS_SHIFT)) & SPI_SR_TXRXS_MASK) #define SPI_SR_TCF_MASK (0x80000000U) #define SPI_SR_TCF_SHIFT (31U) +/*! TCF - Transfer Complete Flag + * 0b0..Transfer not complete. + * 0b1..Transfer complete. + */ #define SPI_SR_TCF(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_TCF_SHIFT)) & SPI_SR_TCF_MASK) +/*! @} */ /*! @name RSER - DMA/Interrupt Request Select and Enable Register */ +/*! @{ */ #define SPI_RSER_RFDF_DIRS_MASK (0x10000U) #define SPI_RSER_RFDF_DIRS_SHIFT (16U) +/*! RFDF_DIRS - Receive FIFO Drain DMA or Interrupt Request Select + * 0b0..Interrupt request. + * 0b1..DMA request. + */ #define SPI_RSER_RFDF_DIRS(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_RFDF_DIRS_SHIFT)) & SPI_RSER_RFDF_DIRS_MASK) #define SPI_RSER_RFDF_RE_MASK (0x20000U) #define SPI_RSER_RFDF_RE_SHIFT (17U) +/*! RFDF_RE - Receive FIFO Drain Request Enable + * 0b0..RFDF interrupt or DMA requests are disabled. + * 0b1..RFDF interrupt or DMA requests are enabled. + */ #define SPI_RSER_RFDF_RE(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_RFDF_RE_SHIFT)) & SPI_RSER_RFDF_RE_MASK) #define SPI_RSER_RFOF_RE_MASK (0x80000U) #define SPI_RSER_RFOF_RE_SHIFT (19U) +/*! RFOF_RE - Receive FIFO Overflow Request Enable + * 0b0..RFOF interrupt requests are disabled. + * 0b1..RFOF interrupt requests are enabled. + */ #define SPI_RSER_RFOF_RE(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_RFOF_RE_SHIFT)) & SPI_RSER_RFOF_RE_MASK) #define SPI_RSER_TFFF_DIRS_MASK (0x1000000U) #define SPI_RSER_TFFF_DIRS_SHIFT (24U) +/*! TFFF_DIRS - Transmit FIFO Fill DMA or Interrupt Request Select + * 0b0..TFFF flag generates interrupt requests. + * 0b1..TFFF flag generates DMA requests. + */ #define SPI_RSER_TFFF_DIRS(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_TFFF_DIRS_SHIFT)) & SPI_RSER_TFFF_DIRS_MASK) #define SPI_RSER_TFFF_RE_MASK (0x2000000U) #define SPI_RSER_TFFF_RE_SHIFT (25U) +/*! TFFF_RE - Transmit FIFO Fill Request Enable + * 0b0..TFFF interrupts or DMA requests are disabled. + * 0b1..TFFF interrupts or DMA requests are enabled. + */ #define SPI_RSER_TFFF_RE(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_TFFF_RE_SHIFT)) & SPI_RSER_TFFF_RE_MASK) #define SPI_RSER_TFUF_RE_MASK (0x8000000U) #define SPI_RSER_TFUF_RE_SHIFT (27U) +/*! TFUF_RE - Transmit FIFO Underflow Request Enable + * 0b0..TFUF interrupt requests are disabled. + * 0b1..TFUF interrupt requests are enabled. + */ #define SPI_RSER_TFUF_RE(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_TFUF_RE_SHIFT)) & SPI_RSER_TFUF_RE_MASK) #define SPI_RSER_EOQF_RE_MASK (0x10000000U) #define SPI_RSER_EOQF_RE_SHIFT (28U) +/*! EOQF_RE - Finished Request Enable + * 0b0..EOQF interrupt requests are disabled. + * 0b1..EOQF interrupt requests are enabled. + */ #define SPI_RSER_EOQF_RE(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_EOQF_RE_SHIFT)) & SPI_RSER_EOQF_RE_MASK) #define SPI_RSER_TCF_RE_MASK (0x80000000U) #define SPI_RSER_TCF_RE_SHIFT (31U) +/*! TCF_RE - Transmission Complete Request Enable + * 0b0..TCF interrupt requests are disabled. + * 0b1..TCF interrupt requests are enabled. + */ #define SPI_RSER_TCF_RE(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_TCF_RE_SHIFT)) & SPI_RSER_TCF_RE_MASK) +/*! @} */ /*! @name PUSHR - PUSH TX FIFO Register In Master Mode */ +/*! @{ */ #define SPI_PUSHR_TXDATA_MASK (0xFFFFU) #define SPI_PUSHR_TXDATA_SHIFT (0U) #define SPI_PUSHR_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_TXDATA_SHIFT)) & SPI_PUSHR_TXDATA_MASK) #define SPI_PUSHR_PCS_MASK (0x3F0000U) #define SPI_PUSHR_PCS_SHIFT (16U) +/*! PCS + * 0b000000..Negate the PCS[x] signal. + * 0b000001..Assert the PCS[x] signal. + */ #define SPI_PUSHR_PCS(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_PCS_SHIFT)) & SPI_PUSHR_PCS_MASK) #define SPI_PUSHR_CTCNT_MASK (0x4000000U) #define SPI_PUSHR_CTCNT_SHIFT (26U) +/*! CTCNT - Clear Transfer Counter + * 0b0..Do not clear the TCR[TCNT] field. + * 0b1..Clear the TCR[TCNT] field. + */ #define SPI_PUSHR_CTCNT(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_CTCNT_SHIFT)) & SPI_PUSHR_CTCNT_MASK) #define SPI_PUSHR_EOQ_MASK (0x8000000U) #define SPI_PUSHR_EOQ_SHIFT (27U) +/*! EOQ - End Of Queue + * 0b0..The SPI data is not the last data to transfer. + * 0b1..The SPI data is the last data to transfer. + */ #define SPI_PUSHR_EOQ(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_EOQ_SHIFT)) & SPI_PUSHR_EOQ_MASK) #define SPI_PUSHR_CTAS_MASK (0x70000000U) #define SPI_PUSHR_CTAS_SHIFT (28U) +/*! CTAS - Clock and Transfer Attributes Select + * 0b000..CTAR0 + * 0b001..CTAR1 + * 0b010..Reserved + * 0b011..Reserved + * 0b100..Reserved + * 0b101..Reserved + * 0b110..Reserved + * 0b111..Reserved + */ #define SPI_PUSHR_CTAS(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_CTAS_SHIFT)) & SPI_PUSHR_CTAS_MASK) #define SPI_PUSHR_CONT_MASK (0x80000000U) #define SPI_PUSHR_CONT_SHIFT (31U) +/*! CONT - Continuous Peripheral Chip Select Enable + * 0b0..Return PCSn signals to their inactive state between transfers. + * 0b1..Keep PCSn signals asserted between transfers. + */ #define SPI_PUSHR_CONT(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_CONT_SHIFT)) & SPI_PUSHR_CONT_MASK) +/*! @} */ /*! @name PUSHR_SLAVE - PUSH TX FIFO Register In Slave Mode */ +/*! @{ */ #define SPI_PUSHR_SLAVE_TXDATA_MASK (0xFFFFFFFFU) #define SPI_PUSHR_SLAVE_TXDATA_SHIFT (0U) #define SPI_PUSHR_SLAVE_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_SLAVE_TXDATA_SHIFT)) & SPI_PUSHR_SLAVE_TXDATA_MASK) +/*! @} */ /*! @name POPR - POP RX FIFO Register */ +/*! @{ */ #define SPI_POPR_RXDATA_MASK (0xFFFFFFFFU) #define SPI_POPR_RXDATA_SHIFT (0U) #define SPI_POPR_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_POPR_RXDATA_SHIFT)) & SPI_POPR_RXDATA_MASK) +/*! @} */ /*! @name TXFR0 - Transmit FIFO Registers */ +/*! @{ */ #define SPI_TXFR0_TXDATA_MASK (0xFFFFU) #define SPI_TXFR0_TXDATA_SHIFT (0U) #define SPI_TXFR0_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR0_TXDATA_SHIFT)) & SPI_TXFR0_TXDATA_MASK) #define SPI_TXFR0_TXCMD_TXDATA_MASK (0xFFFF0000U) #define SPI_TXFR0_TXCMD_TXDATA_SHIFT (16U) #define SPI_TXFR0_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR0_TXCMD_TXDATA_SHIFT)) & SPI_TXFR0_TXCMD_TXDATA_MASK) +/*! @} */ /*! @name TXFR1 - Transmit FIFO Registers */ +/*! @{ */ #define SPI_TXFR1_TXDATA_MASK (0xFFFFU) #define SPI_TXFR1_TXDATA_SHIFT (0U) #define SPI_TXFR1_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR1_TXDATA_SHIFT)) & SPI_TXFR1_TXDATA_MASK) #define SPI_TXFR1_TXCMD_TXDATA_MASK (0xFFFF0000U) #define SPI_TXFR1_TXCMD_TXDATA_SHIFT (16U) #define SPI_TXFR1_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR1_TXCMD_TXDATA_SHIFT)) & SPI_TXFR1_TXCMD_TXDATA_MASK) +/*! @} */ /*! @name TXFR2 - Transmit FIFO Registers */ +/*! @{ */ #define SPI_TXFR2_TXDATA_MASK (0xFFFFU) #define SPI_TXFR2_TXDATA_SHIFT (0U) #define SPI_TXFR2_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR2_TXDATA_SHIFT)) & SPI_TXFR2_TXDATA_MASK) #define SPI_TXFR2_TXCMD_TXDATA_MASK (0xFFFF0000U) #define SPI_TXFR2_TXCMD_TXDATA_SHIFT (16U) #define SPI_TXFR2_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR2_TXCMD_TXDATA_SHIFT)) & SPI_TXFR2_TXCMD_TXDATA_MASK) +/*! @} */ /*! @name TXFR3 - Transmit FIFO Registers */ +/*! @{ */ #define SPI_TXFR3_TXDATA_MASK (0xFFFFU) #define SPI_TXFR3_TXDATA_SHIFT (0U) #define SPI_TXFR3_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR3_TXDATA_SHIFT)) & SPI_TXFR3_TXDATA_MASK) #define SPI_TXFR3_TXCMD_TXDATA_MASK (0xFFFF0000U) #define SPI_TXFR3_TXCMD_TXDATA_SHIFT (16U) #define SPI_TXFR3_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR3_TXCMD_TXDATA_SHIFT)) & SPI_TXFR3_TXCMD_TXDATA_MASK) +/*! @} */ /*! @name RXFR0 - Receive FIFO Registers */ +/*! @{ */ #define SPI_RXFR0_RXDATA_MASK (0xFFFFFFFFU) #define SPI_RXFR0_RXDATA_SHIFT (0U) #define SPI_RXFR0_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_RXFR0_RXDATA_SHIFT)) & SPI_RXFR0_RXDATA_MASK) +/*! @} */ /*! @name RXFR1 - Receive FIFO Registers */ +/*! @{ */ #define SPI_RXFR1_RXDATA_MASK (0xFFFFFFFFU) #define SPI_RXFR1_RXDATA_SHIFT (0U) #define SPI_RXFR1_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_RXFR1_RXDATA_SHIFT)) & SPI_RXFR1_RXDATA_MASK) +/*! @} */ /*! @name RXFR2 - Receive FIFO Registers */ +/*! @{ */ #define SPI_RXFR2_RXDATA_MASK (0xFFFFFFFFU) #define SPI_RXFR2_RXDATA_SHIFT (0U) #define SPI_RXFR2_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_RXFR2_RXDATA_SHIFT)) & SPI_RXFR2_RXDATA_MASK) +/*! @} */ /*! @name RXFR3 - Receive FIFO Registers */ +/*! @{ */ #define SPI_RXFR3_RXDATA_MASK (0xFFFFFFFFU) #define SPI_RXFR3_RXDATA_SHIFT (0U) #define SPI_RXFR3_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_RXFR3_RXDATA_SHIFT)) & SPI_RXFR3_RXDATA_MASK) +/*! @} */ /*! @@ -11075,11 +19715,21 @@ typedef struct { */ /*! @name CESR - Control/Error Status Register */ +/*! @{ */ #define SYSMPU_CESR_VLD_MASK (0x1U) #define SYSMPU_CESR_VLD_SHIFT (0U) +/*! VLD - Valid + * 0b0..MPU is disabled. All accesses from all bus masters are allowed. + * 0b1..MPU is enabled + */ #define SYSMPU_CESR_VLD(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_CESR_VLD_SHIFT)) & SYSMPU_CESR_VLD_MASK) #define SYSMPU_CESR_NRGD_MASK (0xF00U) #define SYSMPU_CESR_NRGD_SHIFT (8U) +/*! NRGD - Number Of Region Descriptors + * 0b0000..8 region descriptors + * 0b0001..12 region descriptors + * 0b0010..16 region descriptors + */ #define SYSMPU_CESR_NRGD(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_CESR_NRGD_SHIFT)) & SYSMPU_CESR_NRGD_MASK) #define SYSMPU_CESR_NSP_MASK (0xF000U) #define SYSMPU_CESR_NSP_SHIFT (12U) @@ -11089,22 +19739,40 @@ typedef struct { #define SYSMPU_CESR_HRL(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_CESR_HRL_SHIFT)) & SYSMPU_CESR_HRL_MASK) #define SYSMPU_CESR_SPERR_MASK (0xF8000000U) #define SYSMPU_CESR_SPERR_SHIFT (27U) +/*! SPERR - Slave Port n Error + * 0b00000..No error has occurred for slave port n. + * 0b00001..An error has occurred for slave port n. + */ #define SYSMPU_CESR_SPERR(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_CESR_SPERR_SHIFT)) & SYSMPU_CESR_SPERR_MASK) +/*! @} */ /*! @name EAR - Error Address Register, slave port n */ +/*! @{ */ #define SYSMPU_EAR_EADDR_MASK (0xFFFFFFFFU) #define SYSMPU_EAR_EADDR_SHIFT (0U) #define SYSMPU_EAR_EADDR(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_EAR_EADDR_SHIFT)) & SYSMPU_EAR_EADDR_MASK) +/*! @} */ /* The count of SYSMPU_EAR */ #define SYSMPU_EAR_COUNT (5U) /*! @name EDR - Error Detail Register, slave port n */ +/*! @{ */ #define SYSMPU_EDR_ERW_MASK (0x1U) #define SYSMPU_EDR_ERW_SHIFT (0U) +/*! ERW - Error Read/Write + * 0b0..Read + * 0b1..Write + */ #define SYSMPU_EDR_ERW(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_EDR_ERW_SHIFT)) & SYSMPU_EDR_ERW_MASK) #define SYSMPU_EDR_EATTR_MASK (0xEU) #define SYSMPU_EDR_EATTR_SHIFT (1U) +/*! EATTR - Error Attributes + * 0b000..User mode, instruction access + * 0b001..User mode, data access + * 0b010..Supervisor mode, instruction access + * 0b011..Supervisor mode, data access + */ #define SYSMPU_EDR_EATTR(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_EDR_EATTR_SHIFT)) & SYSMPU_EDR_EATTR_MASK) #define SYSMPU_EDR_EMN_MASK (0xF0U) #define SYSMPU_EDR_EMN_SHIFT (4U) @@ -11115,26 +19783,32 @@ typedef struct { #define SYSMPU_EDR_EACD_MASK (0xFFFF0000U) #define SYSMPU_EDR_EACD_SHIFT (16U) #define SYSMPU_EDR_EACD(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_EDR_EACD_SHIFT)) & SYSMPU_EDR_EACD_MASK) +/*! @} */ /* The count of SYSMPU_EDR */ #define SYSMPU_EDR_COUNT (5U) /*! @name WORD - Region Descriptor n, Word 0..Region Descriptor n, Word 3 */ -#define SYSMPU_WORD_VLD_MASK (0x1U) -#define SYSMPU_WORD_VLD_SHIFT (0U) -#define SYSMPU_WORD_VLD(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_VLD_SHIFT)) & SYSMPU_WORD_VLD_MASK) +/*! @{ */ #define SYSMPU_WORD_M0UM_MASK (0x7U) #define SYSMPU_WORD_M0UM_SHIFT (0U) #define SYSMPU_WORD_M0UM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M0UM_SHIFT)) & SYSMPU_WORD_M0UM_MASK) +#define SYSMPU_WORD_VLD_MASK (0x1U) +#define SYSMPU_WORD_VLD_SHIFT (0U) +/*! VLD - Valid + * 0b0..Region descriptor is invalid + * 0b1..Region descriptor is valid + */ +#define SYSMPU_WORD_VLD(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_VLD_SHIFT)) & SYSMPU_WORD_VLD_MASK) #define SYSMPU_WORD_M0SM_MASK (0x18U) #define SYSMPU_WORD_M0SM_SHIFT (3U) #define SYSMPU_WORD_M0SM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M0SM_SHIFT)) & SYSMPU_WORD_M0SM_MASK) -#define SYSMPU_WORD_M0PE_MASK (0x20U) -#define SYSMPU_WORD_M0PE_SHIFT (5U) -#define SYSMPU_WORD_M0PE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M0PE_SHIFT)) & SYSMPU_WORD_M0PE_MASK) #define SYSMPU_WORD_ENDADDR_MASK (0xFFFFFFE0U) #define SYSMPU_WORD_ENDADDR_SHIFT (5U) #define SYSMPU_WORD_ENDADDR(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_ENDADDR_SHIFT)) & SYSMPU_WORD_ENDADDR_MASK) +#define SYSMPU_WORD_M0PE_MASK (0x20U) +#define SYSMPU_WORD_M0PE_SHIFT (5U) +#define SYSMPU_WORD_M0PE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M0PE_SHIFT)) & SYSMPU_WORD_M0PE_MASK) #define SYSMPU_WORD_SRTADDR_MASK (0xFFFFFFE0U) #define SYSMPU_WORD_SRTADDR_SHIFT (5U) #define SYSMPU_WORD_SRTADDR(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_SRTADDR_SHIFT)) & SYSMPU_WORD_SRTADDR_MASK) @@ -11161,40 +19835,87 @@ typedef struct { #define SYSMPU_WORD_M2PE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M2PE_SHIFT)) & SYSMPU_WORD_M2PE_MASK) #define SYSMPU_WORD_M3UM_MASK (0x1C0000U) #define SYSMPU_WORD_M3UM_SHIFT (18U) +/*! M3UM - Bus Master 3 User Mode Access Control + * 0b000..An attempted access of that mode may be terminated with an access error (if not allowed by another descriptor) and the access not performed. + * 0b001..Allows the given access type to occur + */ #define SYSMPU_WORD_M3UM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M3UM_SHIFT)) & SYSMPU_WORD_M3UM_MASK) #define SYSMPU_WORD_M3SM_MASK (0x600000U) #define SYSMPU_WORD_M3SM_SHIFT (21U) +/*! M3SM - Bus Master 3 Supervisor Mode Access Control + * 0b00..r/w/x; read, write and execute allowed + * 0b01..r/x; read and execute allowed, but no write + * 0b10..r/w; read and write allowed, but no execute + * 0b11..Same as User mode defined in M3UM + */ #define SYSMPU_WORD_M3SM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M3SM_SHIFT)) & SYSMPU_WORD_M3SM_MASK) #define SYSMPU_WORD_M3PE_MASK (0x800000U) #define SYSMPU_WORD_M3PE_SHIFT (23U) +/*! M3PE - Bus Master 3 Process Identifier Enable + * 0b0..Do not include the process identifier in the evaluation + * 0b1..Include the process identifier and mask (RGDn_WORD3) in the region hit evaluation + */ #define SYSMPU_WORD_M3PE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M3PE_SHIFT)) & SYSMPU_WORD_M3PE_MASK) +#define SYSMPU_WORD_M4WE_MASK (0x1000000U) +#define SYSMPU_WORD_M4WE_SHIFT (24U) +/*! M4WE - Bus Master 4 Write Enable + * 0b0..Bus master 4 writes terminate with an access error and the write is not performed + * 0b1..Bus master 4 writes allowed + */ +#define SYSMPU_WORD_M4WE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M4WE_SHIFT)) & SYSMPU_WORD_M4WE_MASK) #define SYSMPU_WORD_PID_MASK (0xFF000000U) #define SYSMPU_WORD_PID_SHIFT (24U) #define SYSMPU_WORD_PID(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_PID_SHIFT)) & SYSMPU_WORD_PID_MASK) -#define SYSMPU_WORD_M4WE_MASK (0x1000000U) -#define SYSMPU_WORD_M4WE_SHIFT (24U) -#define SYSMPU_WORD_M4WE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M4WE_SHIFT)) & SYSMPU_WORD_M4WE_MASK) #define SYSMPU_WORD_M4RE_MASK (0x2000000U) #define SYSMPU_WORD_M4RE_SHIFT (25U) +/*! M4RE - Bus Master 4 Read Enable + * 0b0..Bus master 4 reads terminate with an access error and the read is not performed + * 0b1..Bus master 4 reads allowed + */ #define SYSMPU_WORD_M4RE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M4RE_SHIFT)) & SYSMPU_WORD_M4RE_MASK) #define SYSMPU_WORD_M5WE_MASK (0x4000000U) #define SYSMPU_WORD_M5WE_SHIFT (26U) +/*! M5WE - Bus Master 5 Write Enable + * 0b0..Bus master 5 writes terminate with an access error and the write is not performed + * 0b1..Bus master 5 writes allowed + */ #define SYSMPU_WORD_M5WE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M5WE_SHIFT)) & SYSMPU_WORD_M5WE_MASK) #define SYSMPU_WORD_M5RE_MASK (0x8000000U) #define SYSMPU_WORD_M5RE_SHIFT (27U) +/*! M5RE - Bus Master 5 Read Enable + * 0b0..Bus master 5 reads terminate with an access error and the read is not performed + * 0b1..Bus master 5 reads allowed + */ #define SYSMPU_WORD_M5RE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M5RE_SHIFT)) & SYSMPU_WORD_M5RE_MASK) #define SYSMPU_WORD_M6WE_MASK (0x10000000U) #define SYSMPU_WORD_M6WE_SHIFT (28U) +/*! M6WE - Bus Master 6 Write Enable + * 0b0..Bus master 6 writes terminate with an access error and the write is not performed + * 0b1..Bus master 6 writes allowed + */ #define SYSMPU_WORD_M6WE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M6WE_SHIFT)) & SYSMPU_WORD_M6WE_MASK) #define SYSMPU_WORD_M6RE_MASK (0x20000000U) #define SYSMPU_WORD_M6RE_SHIFT (29U) +/*! M6RE - Bus Master 6 Read Enable + * 0b0..Bus master 6 reads terminate with an access error and the read is not performed + * 0b1..Bus master 6 reads allowed + */ #define SYSMPU_WORD_M6RE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M6RE_SHIFT)) & SYSMPU_WORD_M6RE_MASK) #define SYSMPU_WORD_M7WE_MASK (0x40000000U) #define SYSMPU_WORD_M7WE_SHIFT (30U) +/*! M7WE - Bus Master 7 Write Enable + * 0b0..Bus master 7 writes terminate with an access error and the write is not performed + * 0b1..Bus master 7 writes allowed + */ #define SYSMPU_WORD_M7WE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M7WE_SHIFT)) & SYSMPU_WORD_M7WE_MASK) #define SYSMPU_WORD_M7RE_MASK (0x80000000U) #define SYSMPU_WORD_M7RE_SHIFT (31U) +/*! M7RE - Bus Master 7 Read Enable + * 0b0..Bus master 7 reads terminate with an access error and the read is not performed + * 0b1..Bus master 7 reads allowed + */ #define SYSMPU_WORD_M7RE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M7RE_SHIFT)) & SYSMPU_WORD_M7RE_MASK) +/*! @} */ /* The count of SYSMPU_WORD */ #define SYSMPU_WORD_COUNT (12U) @@ -11203,6 +19924,7 @@ typedef struct { #define SYSMPU_WORD_COUNT2 (4U) /*! @name RGDAAC - Region Descriptor Alternate Access Control n */ +/*! @{ */ #define SYSMPU_RGDAAC_M0UM_MASK (0x7U) #define SYSMPU_RGDAAC_M0UM_SHIFT (0U) #define SYSMPU_RGDAAC_M0UM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M0UM_SHIFT)) & SYSMPU_RGDAAC_M0UM_MASK) @@ -11232,37 +19954,84 @@ typedef struct { #define SYSMPU_RGDAAC_M2PE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M2PE_SHIFT)) & SYSMPU_RGDAAC_M2PE_MASK) #define SYSMPU_RGDAAC_M3UM_MASK (0x1C0000U) #define SYSMPU_RGDAAC_M3UM_SHIFT (18U) +/*! M3UM - Bus Master 3 User Mode Access Control + * 0b000..An attempted access of that mode may be terminated with an access error (if not allowed by another descriptor) and the access not performed. + * 0b001..Allows the given access type to occur + */ #define SYSMPU_RGDAAC_M3UM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M3UM_SHIFT)) & SYSMPU_RGDAAC_M3UM_MASK) #define SYSMPU_RGDAAC_M3SM_MASK (0x600000U) #define SYSMPU_RGDAAC_M3SM_SHIFT (21U) +/*! M3SM - Bus Master 3 Supervisor Mode Access Control + * 0b00..r/w/x; read, write and execute allowed + * 0b01..r/x; read and execute allowed, but no write + * 0b10..r/w; read and write allowed, but no execute + * 0b11..Same as User mode defined in M3UM + */ #define SYSMPU_RGDAAC_M3SM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M3SM_SHIFT)) & SYSMPU_RGDAAC_M3SM_MASK) #define SYSMPU_RGDAAC_M3PE_MASK (0x800000U) #define SYSMPU_RGDAAC_M3PE_SHIFT (23U) +/*! M3PE - Bus Master 3 Process Identifier Enable + * 0b0..Do not include the process identifier in the evaluation + * 0b1..Include the process identifier and mask (RGDn.RGDAAC) in the region hit evaluation + */ #define SYSMPU_RGDAAC_M3PE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M3PE_SHIFT)) & SYSMPU_RGDAAC_M3PE_MASK) #define SYSMPU_RGDAAC_M4WE_MASK (0x1000000U) #define SYSMPU_RGDAAC_M4WE_SHIFT (24U) +/*! M4WE - Bus Master 4 Write Enable + * 0b0..Bus master 4 writes terminate with an access error and the write is not performed + * 0b1..Bus master 4 writes allowed + */ #define SYSMPU_RGDAAC_M4WE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M4WE_SHIFT)) & SYSMPU_RGDAAC_M4WE_MASK) #define SYSMPU_RGDAAC_M4RE_MASK (0x2000000U) #define SYSMPU_RGDAAC_M4RE_SHIFT (25U) +/*! M4RE - Bus Master 4 Read Enable + * 0b0..Bus master 4 reads terminate with an access error and the read is not performed + * 0b1..Bus master 4 reads allowed + */ #define SYSMPU_RGDAAC_M4RE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M4RE_SHIFT)) & SYSMPU_RGDAAC_M4RE_MASK) #define SYSMPU_RGDAAC_M5WE_MASK (0x4000000U) #define SYSMPU_RGDAAC_M5WE_SHIFT (26U) +/*! M5WE - Bus Master 5 Write Enable + * 0b0..Bus master 5 writes terminate with an access error and the write is not performed + * 0b1..Bus master 5 writes allowed + */ #define SYSMPU_RGDAAC_M5WE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M5WE_SHIFT)) & SYSMPU_RGDAAC_M5WE_MASK) #define SYSMPU_RGDAAC_M5RE_MASK (0x8000000U) #define SYSMPU_RGDAAC_M5RE_SHIFT (27U) +/*! M5RE - Bus Master 5 Read Enable + * 0b0..Bus master 5 reads terminate with an access error and the read is not performed + * 0b1..Bus master 5 reads allowed + */ #define SYSMPU_RGDAAC_M5RE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M5RE_SHIFT)) & SYSMPU_RGDAAC_M5RE_MASK) #define SYSMPU_RGDAAC_M6WE_MASK (0x10000000U) #define SYSMPU_RGDAAC_M6WE_SHIFT (28U) +/*! M6WE - Bus Master 6 Write Enable + * 0b0..Bus master 6 writes terminate with an access error and the write is not performed + * 0b1..Bus master 6 writes allowed + */ #define SYSMPU_RGDAAC_M6WE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M6WE_SHIFT)) & SYSMPU_RGDAAC_M6WE_MASK) #define SYSMPU_RGDAAC_M6RE_MASK (0x20000000U) #define SYSMPU_RGDAAC_M6RE_SHIFT (29U) +/*! M6RE - Bus Master 6 Read Enable + * 0b0..Bus master 6 reads terminate with an access error and the read is not performed + * 0b1..Bus master 6 reads allowed + */ #define SYSMPU_RGDAAC_M6RE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M6RE_SHIFT)) & SYSMPU_RGDAAC_M6RE_MASK) #define SYSMPU_RGDAAC_M7WE_MASK (0x40000000U) #define SYSMPU_RGDAAC_M7WE_SHIFT (30U) +/*! M7WE - Bus Master 7 Write Enable + * 0b0..Bus master 7 writes terminate with an access error and the write is not performed + * 0b1..Bus master 7 writes allowed + */ #define SYSMPU_RGDAAC_M7WE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M7WE_SHIFT)) & SYSMPU_RGDAAC_M7WE_MASK) #define SYSMPU_RGDAAC_M7RE_MASK (0x80000000U) #define SYSMPU_RGDAAC_M7RE_SHIFT (31U) +/*! M7RE - Bus Master 7 Read Enable + * 0b0..Bus master 7 reads terminate with an access error and the read is not performed + * 0b1..Bus master 7 reads allowed + */ #define SYSMPU_RGDAAC_M7RE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M7RE_SHIFT)) & SYSMPU_RGDAAC_M7RE_MASK) +/*! @} */ /* The count of SYSMPU_RGDAAC */ #define SYSMPU_RGDAAC_COUNT (12U) @@ -11346,146 +20115,323 @@ typedef struct { */ /*! @name BDH - UART Baud Rate Registers: High */ +/*! @{ */ #define UART_BDH_SBR_MASK (0x1FU) #define UART_BDH_SBR_SHIFT (0U) #define UART_BDH_SBR(x) (((uint8_t)(((uint8_t)(x)) << UART_BDH_SBR_SHIFT)) & UART_BDH_SBR_MASK) #define UART_BDH_SBNS_MASK (0x20U) #define UART_BDH_SBNS_SHIFT (5U) +/*! SBNS - Stop Bit Number Select + * 0b0..Data frame consists of a single stop bit. + * 0b1..Data frame consists of two stop bits. + */ #define UART_BDH_SBNS(x) (((uint8_t)(((uint8_t)(x)) << UART_BDH_SBNS_SHIFT)) & UART_BDH_SBNS_MASK) #define UART_BDH_RXEDGIE_MASK (0x40U) #define UART_BDH_RXEDGIE_SHIFT (6U) +/*! RXEDGIE - RxD Input Active Edge Interrupt Enable + * 0b0..Hardware interrupts from RXEDGIF disabled using polling. + * 0b1..RXEDGIF interrupt request enabled. + */ #define UART_BDH_RXEDGIE(x) (((uint8_t)(((uint8_t)(x)) << UART_BDH_RXEDGIE_SHIFT)) & UART_BDH_RXEDGIE_MASK) #define UART_BDH_LBKDIE_MASK (0x80U) #define UART_BDH_LBKDIE_SHIFT (7U) +/*! LBKDIE - LIN Break Detect Interrupt or DMA Request Enable + * 0b0..LBKDIF interrupt and DMA transfer requests disabled. + * 0b1..LBKDIF interrupt or DMA transfer requests enabled. + */ #define UART_BDH_LBKDIE(x) (((uint8_t)(((uint8_t)(x)) << UART_BDH_LBKDIE_SHIFT)) & UART_BDH_LBKDIE_MASK) +/*! @} */ /*! @name BDL - UART Baud Rate Registers: Low */ +/*! @{ */ #define UART_BDL_SBR_MASK (0xFFU) #define UART_BDL_SBR_SHIFT (0U) #define UART_BDL_SBR(x) (((uint8_t)(((uint8_t)(x)) << UART_BDL_SBR_SHIFT)) & UART_BDL_SBR_MASK) +/*! @} */ /*! @name C1 - UART Control Register 1 */ +/*! @{ */ #define UART_C1_PT_MASK (0x1U) #define UART_C1_PT_SHIFT (0U) +/*! PT - Parity Type + * 0b0..Even parity. + * 0b1..Odd parity. + */ #define UART_C1_PT(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_PT_SHIFT)) & UART_C1_PT_MASK) #define UART_C1_PE_MASK (0x2U) #define UART_C1_PE_SHIFT (1U) +/*! PE - Parity Enable + * 0b0..Parity function disabled. + * 0b1..Parity function enabled. + */ #define UART_C1_PE(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_PE_SHIFT)) & UART_C1_PE_MASK) #define UART_C1_ILT_MASK (0x4U) #define UART_C1_ILT_SHIFT (2U) +/*! ILT - Idle Line Type Select + * 0b0..Idle character bit count starts after start bit. + * 0b1..Idle character bit count starts after stop bit. + */ #define UART_C1_ILT(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_ILT_SHIFT)) & UART_C1_ILT_MASK) #define UART_C1_WAKE_MASK (0x8U) #define UART_C1_WAKE_SHIFT (3U) +/*! WAKE - Receiver Wakeup Method Select + * 0b0..Idle line wakeup. + * 0b1..Address mark wakeup. + */ #define UART_C1_WAKE(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_WAKE_SHIFT)) & UART_C1_WAKE_MASK) #define UART_C1_M_MASK (0x10U) #define UART_C1_M_SHIFT (4U) +/*! M - 9-bit or 8-bit Mode Select + * 0b0..Normal-start + 8 data bits (MSB/LSB first as determined by MSBF) + stop. + * 0b1..Use-start + 9 data bits (MSB/LSB first as determined by MSBF) + stop. + */ #define UART_C1_M(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_M_SHIFT)) & UART_C1_M_MASK) #define UART_C1_RSRC_MASK (0x20U) #define UART_C1_RSRC_SHIFT (5U) +/*! RSRC - Receiver Source Select + * 0b0..Selects internal loop back mode. The receiver input is internally connected to transmitter output. + * 0b1..Single wire UART mode where the receiver input is connected to the transmit pin input signal. + */ #define UART_C1_RSRC(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_RSRC_SHIFT)) & UART_C1_RSRC_MASK) #define UART_C1_UARTSWAI_MASK (0x40U) #define UART_C1_UARTSWAI_SHIFT (6U) +/*! UARTSWAI - UART Stops in Wait Mode + * 0b0..UART clock continues to run in Wait mode. + * 0b1..UART clock freezes while CPU is in Wait mode. + */ #define UART_C1_UARTSWAI(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_UARTSWAI_SHIFT)) & UART_C1_UARTSWAI_MASK) #define UART_C1_LOOPS_MASK (0x80U) #define UART_C1_LOOPS_SHIFT (7U) +/*! LOOPS - Loop Mode Select + * 0b0..Normal operation. + * 0b1..Loop mode where transmitter output is internally connected to receiver input. The receiver input is determined by RSRC. + */ #define UART_C1_LOOPS(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_LOOPS_SHIFT)) & UART_C1_LOOPS_MASK) +/*! @} */ /*! @name C2 - UART Control Register 2 */ +/*! @{ */ #define UART_C2_SBK_MASK (0x1U) #define UART_C2_SBK_SHIFT (0U) +/*! SBK - Send Break + * 0b0..Normal transmitter operation. + * 0b1..Queue break characters to be sent. + */ #define UART_C2_SBK(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_SBK_SHIFT)) & UART_C2_SBK_MASK) #define UART_C2_RWU_MASK (0x2U) #define UART_C2_RWU_SHIFT (1U) +/*! RWU - Receiver Wakeup Control + * 0b0..Normal operation. + * 0b1..RWU enables the wakeup function and inhibits further receiver interrupt requests. Normally, hardware wakes the receiver by automatically clearing RWU. + */ #define UART_C2_RWU(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_RWU_SHIFT)) & UART_C2_RWU_MASK) #define UART_C2_RE_MASK (0x4U) #define UART_C2_RE_SHIFT (2U) +/*! RE - Receiver Enable + * 0b0..Receiver off. + * 0b1..Receiver on. + */ #define UART_C2_RE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_RE_SHIFT)) & UART_C2_RE_MASK) #define UART_C2_TE_MASK (0x8U) #define UART_C2_TE_SHIFT (3U) +/*! TE - Transmitter Enable + * 0b0..Transmitter off. + * 0b1..Transmitter on. + */ #define UART_C2_TE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_TE_SHIFT)) & UART_C2_TE_MASK) #define UART_C2_ILIE_MASK (0x10U) #define UART_C2_ILIE_SHIFT (4U) +/*! ILIE - Idle Line Interrupt DMA Transfer Enable + * 0b0..IDLE interrupt requests disabled. and DMA transfer + * 0b1..IDLE interrupt requests enabled. or DMA transfer + */ #define UART_C2_ILIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_ILIE_SHIFT)) & UART_C2_ILIE_MASK) #define UART_C2_RIE_MASK (0x20U) #define UART_C2_RIE_SHIFT (5U) +/*! RIE - Receiver Full Interrupt or DMA Transfer Enable + * 0b0..RDRF interrupt and DMA transfer requests disabled. + * 0b1..RDRF interrupt or DMA transfer requests enabled. + */ #define UART_C2_RIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_RIE_SHIFT)) & UART_C2_RIE_MASK) #define UART_C2_TCIE_MASK (0x40U) #define UART_C2_TCIE_SHIFT (6U) +/*! TCIE - Transmission Complete Interrupt or DMA Transfer Enable + * 0b0..TC interrupt and DMA transfer requests disabled. + * 0b1..TC interrupt or DMA transfer requests enabled. + */ #define UART_C2_TCIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_TCIE_SHIFT)) & UART_C2_TCIE_MASK) #define UART_C2_TIE_MASK (0x80U) #define UART_C2_TIE_SHIFT (7U) +/*! TIE - Transmitter Interrupt or DMA Transfer Enable. + * 0b0..TDRE interrupt and DMA transfer requests disabled. + * 0b1..TDRE interrupt or DMA transfer requests enabled. + */ #define UART_C2_TIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_TIE_SHIFT)) & UART_C2_TIE_MASK) +/*! @} */ /*! @name S1 - UART Status Register 1 */ +/*! @{ */ #define UART_S1_PF_MASK (0x1U) #define UART_S1_PF_SHIFT (0U) +/*! PF - Parity Error Flag + * 0b0..No parity error detected since the last time this flag was cleared. If the receive buffer has a depth greater than 1, then there may be data in the receive buffer what was received with a parity error. + * 0b1..At least one dataword was received with a parity error since the last time this flag was cleared. + */ #define UART_S1_PF(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_PF_SHIFT)) & UART_S1_PF_MASK) #define UART_S1_FE_MASK (0x2U) #define UART_S1_FE_SHIFT (1U) +/*! FE - Framing Error Flag + * 0b0..No framing error detected. + * 0b1..Framing error. + */ #define UART_S1_FE(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_FE_SHIFT)) & UART_S1_FE_MASK) #define UART_S1_NF_MASK (0x4U) #define UART_S1_NF_SHIFT (2U) +/*! NF - Noise Flag + * 0b0..No noise detected since the last time this flag was cleared. If the receive buffer has a depth greater than 1 then there may be data in the receiver buffer that was received with noise. + * 0b1..At least one dataword was received with noise detected since the last time the flag was cleared. + */ #define UART_S1_NF(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_NF_SHIFT)) & UART_S1_NF_MASK) #define UART_S1_OR_MASK (0x8U) #define UART_S1_OR_SHIFT (3U) +/*! OR - Receiver Overrun Flag + * 0b0..No overrun has occurred since the last time the flag was cleared. + * 0b1..Overrun has occurred or the overrun flag has not been cleared since the last overrun occured. + */ #define UART_S1_OR(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_OR_SHIFT)) & UART_S1_OR_MASK) #define UART_S1_IDLE_MASK (0x10U) #define UART_S1_IDLE_SHIFT (4U) +/*! IDLE - Idle Line Flag + * 0b0..Receiver input is either active now or has never become active since the IDLE flag was last cleared. + * 0b1..Receiver input has become idle or the flag has not been cleared since it last asserted. + */ #define UART_S1_IDLE(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_IDLE_SHIFT)) & UART_S1_IDLE_MASK) #define UART_S1_RDRF_MASK (0x20U) #define UART_S1_RDRF_SHIFT (5U) +/*! RDRF - Receive Data Register Full Flag + * 0b0..The number of datawords in the receive buffer is less than the number indicated by RXWATER. + * 0b1..The number of datawords in the receive buffer is equal to or greater than the number indicated by RXWATER at some point in time since this flag was last cleared. + */ #define UART_S1_RDRF(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_RDRF_SHIFT)) & UART_S1_RDRF_MASK) #define UART_S1_TC_MASK (0x40U) #define UART_S1_TC_SHIFT (6U) +/*! TC - Transmit Complete Flag + * 0b0..Transmitter active (sending data, a preamble, or a break). + * 0b1..Transmitter idle (transmission activity complete). + */ #define UART_S1_TC(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_TC_SHIFT)) & UART_S1_TC_MASK) #define UART_S1_TDRE_MASK (0x80U) #define UART_S1_TDRE_SHIFT (7U) +/*! TDRE - Transmit Data Register Empty Flag + * 0b0..The amount of data in the transmit buffer is greater than the value indicated by TWFIFO[TXWATER]. + * 0b1..The amount of data in the transmit buffer is less than or equal to the value indicated by TWFIFO[TXWATER] at some point in time since the flag has been cleared. + */ #define UART_S1_TDRE(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_TDRE_SHIFT)) & UART_S1_TDRE_MASK) +/*! @} */ /*! @name S2 - UART Status Register 2 */ +/*! @{ */ #define UART_S2_RAF_MASK (0x1U) #define UART_S2_RAF_SHIFT (0U) +/*! RAF - Receiver Active Flag + * 0b0..UART receiver idle/inactive waiting for a start bit. + * 0b1..UART receiver active, RxD input not idle. + */ #define UART_S2_RAF(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_RAF_SHIFT)) & UART_S2_RAF_MASK) #define UART_S2_LBKDE_MASK (0x2U) #define UART_S2_LBKDE_SHIFT (1U) +/*! LBKDE - LIN Break Detection Enable + * 0b0..Break character detection is disabled. + * 0b1..Break character is detected at length of 11 bit times if C1[M] = 0 or 12 bits time if C1[M] = 1. + */ #define UART_S2_LBKDE(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_LBKDE_SHIFT)) & UART_S2_LBKDE_MASK) #define UART_S2_BRK13_MASK (0x4U) #define UART_S2_BRK13_SHIFT (2U) +/*! BRK13 - Break Transmit Character Length + * 0b0..Break character is 10, 11, or 12 bits long. + * 0b1..Break character is 13 or 14 bits long. + */ #define UART_S2_BRK13(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_BRK13_SHIFT)) & UART_S2_BRK13_MASK) #define UART_S2_RWUID_MASK (0x8U) #define UART_S2_RWUID_SHIFT (3U) +/*! RWUID - Receive Wakeup Idle Detect + * 0b0..S1[IDLE] is not set upon detection of an idle character. + * 0b1..S1[IDLE] is set upon detection of an idle character. + */ #define UART_S2_RWUID(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_RWUID_SHIFT)) & UART_S2_RWUID_MASK) #define UART_S2_RXINV_MASK (0x10U) #define UART_S2_RXINV_SHIFT (4U) +/*! RXINV - Receive Data Inversion + * 0b0..Receive data is not inverted. + * 0b1..Receive data is inverted. + */ #define UART_S2_RXINV(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_RXINV_SHIFT)) & UART_S2_RXINV_MASK) #define UART_S2_MSBF_MASK (0x20U) #define UART_S2_MSBF_SHIFT (5U) +/*! MSBF - Most Significant Bit First + * 0b0..LSB (bit0) is the first bit that is transmitted following the start bit. Further, the first bit received after the start bit is identified as bit0. + * 0b1..MSB (bit8, bit7 or bit6) is the first bit that is transmitted following the start bit, depending on the setting of C1[M] and C1[PE]. Further, the first bit received after the start bit is identified as bit8, bit7, or bit6, depending on the setting of C1[M] and C1[PE]. + */ #define UART_S2_MSBF(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_MSBF_SHIFT)) & UART_S2_MSBF_MASK) #define UART_S2_RXEDGIF_MASK (0x40U) #define UART_S2_RXEDGIF_SHIFT (6U) +/*! RXEDGIF - RxD Pin Active Edge Interrupt Flag + * 0b0..No active edge on the receive pin has occurred. + * 0b1..An active edge on the receive pin has occurred. + */ #define UART_S2_RXEDGIF(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_RXEDGIF_SHIFT)) & UART_S2_RXEDGIF_MASK) #define UART_S2_LBKDIF_MASK (0x80U) #define UART_S2_LBKDIF_SHIFT (7U) +/*! LBKDIF - LIN Break Detect Interrupt Flag + * 0b0..No LIN break character detected. + * 0b1..LIN break character detected. + */ #define UART_S2_LBKDIF(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_LBKDIF_SHIFT)) & UART_S2_LBKDIF_MASK) +/*! @} */ /*! @name C3 - UART Control Register 3 */ +/*! @{ */ #define UART_C3_PEIE_MASK (0x1U) #define UART_C3_PEIE_SHIFT (0U) +/*! PEIE - Parity Error Interrupt Enable + * 0b0..PF interrupt requests are disabled. + * 0b1..PF interrupt requests are enabled. + */ #define UART_C3_PEIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_PEIE_SHIFT)) & UART_C3_PEIE_MASK) #define UART_C3_FEIE_MASK (0x2U) #define UART_C3_FEIE_SHIFT (1U) +/*! FEIE - Framing Error Interrupt Enable + * 0b0..FE interrupt requests are disabled. + * 0b1..FE interrupt requests are enabled. + */ #define UART_C3_FEIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_FEIE_SHIFT)) & UART_C3_FEIE_MASK) #define UART_C3_NEIE_MASK (0x4U) #define UART_C3_NEIE_SHIFT (2U) +/*! NEIE - Noise Error Interrupt Enable + * 0b0..NF interrupt requests are disabled. + * 0b1..NF interrupt requests are enabled. + */ #define UART_C3_NEIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_NEIE_SHIFT)) & UART_C3_NEIE_MASK) #define UART_C3_ORIE_MASK (0x8U) #define UART_C3_ORIE_SHIFT (3U) +/*! ORIE - Overrun Error Interrupt Enable + * 0b0..OR interrupts are disabled. + * 0b1..OR interrupt requests are enabled. + */ #define UART_C3_ORIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_ORIE_SHIFT)) & UART_C3_ORIE_MASK) #define UART_C3_TXINV_MASK (0x10U) #define UART_C3_TXINV_SHIFT (4U) +/*! TXINV - Transmit Data Inversion. + * 0b0..Transmit data is not inverted. + * 0b1..Transmit data is inverted. + */ #define UART_C3_TXINV(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_TXINV_SHIFT)) & UART_C3_TXINV_MASK) #define UART_C3_TXDIR_MASK (0x20U) #define UART_C3_TXDIR_SHIFT (5U) +/*! TXDIR - Transmitter Pin Data Direction in Single-Wire mode + * 0b0..TXD pin is an input in single wire mode. + * 0b1..TXD pin is an output in single wire mode. + */ #define UART_C3_TXDIR(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_TXDIR_SHIFT)) & UART_C3_TXDIR_MASK) #define UART_C3_T8_MASK (0x40U) #define UART_C3_T8_SHIFT (6U) @@ -11493,249 +20439,512 @@ typedef struct { #define UART_C3_R8_MASK (0x80U) #define UART_C3_R8_SHIFT (7U) #define UART_C3_R8(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_R8_SHIFT)) & UART_C3_R8_MASK) +/*! @} */ /*! @name D - UART Data Register */ +/*! @{ */ #define UART_D_RT_MASK (0xFFU) #define UART_D_RT_SHIFT (0U) #define UART_D_RT(x) (((uint8_t)(((uint8_t)(x)) << UART_D_RT_SHIFT)) & UART_D_RT_MASK) +/*! @} */ /*! @name MA1 - UART Match Address Registers 1 */ +/*! @{ */ #define UART_MA1_MA_MASK (0xFFU) #define UART_MA1_MA_SHIFT (0U) #define UART_MA1_MA(x) (((uint8_t)(((uint8_t)(x)) << UART_MA1_MA_SHIFT)) & UART_MA1_MA_MASK) +/*! @} */ /*! @name MA2 - UART Match Address Registers 2 */ +/*! @{ */ #define UART_MA2_MA_MASK (0xFFU) #define UART_MA2_MA_SHIFT (0U) #define UART_MA2_MA(x) (((uint8_t)(((uint8_t)(x)) << UART_MA2_MA_SHIFT)) & UART_MA2_MA_MASK) +/*! @} */ /*! @name C4 - UART Control Register 4 */ +/*! @{ */ #define UART_C4_BRFA_MASK (0x1FU) #define UART_C4_BRFA_SHIFT (0U) #define UART_C4_BRFA(x) (((uint8_t)(((uint8_t)(x)) << UART_C4_BRFA_SHIFT)) & UART_C4_BRFA_MASK) #define UART_C4_M10_MASK (0x20U) #define UART_C4_M10_SHIFT (5U) +/*! M10 - 10-bit Mode select + * 0b0..The parity bit is the ninth bit in the serial transmission. + * 0b1..The parity bit is the tenth bit in the serial transmission. + */ #define UART_C4_M10(x) (((uint8_t)(((uint8_t)(x)) << UART_C4_M10_SHIFT)) & UART_C4_M10_MASK) #define UART_C4_MAEN2_MASK (0x40U) #define UART_C4_MAEN2_SHIFT (6U) +/*! MAEN2 - Match Address Mode Enable 2 + * 0b0..All data received is transferred to the data buffer if MAEN1 is cleared. + * 0b1..All data received with the most significant bit cleared, is discarded. All data received with the most significant bit set, is compared with contents of MA2 register. If no match occurs, the data is discarded. If a match occurs, data is transferred to the data buffer. This field must be cleared when C7816[ISO7816E] is set/enabled. + */ #define UART_C4_MAEN2(x) (((uint8_t)(((uint8_t)(x)) << UART_C4_MAEN2_SHIFT)) & UART_C4_MAEN2_MASK) #define UART_C4_MAEN1_MASK (0x80U) #define UART_C4_MAEN1_SHIFT (7U) +/*! MAEN1 - Match Address Mode Enable 1 + * 0b0..All data received is transferred to the data buffer if MAEN2 is cleared. + * 0b1..All data received with the most significant bit cleared, is discarded. All data received with the most significant bit set, is compared with contents of MA1 register. If no match occurs, the data is discarded. If match occurs, data is transferred to the data buffer. This field must be cleared when C7816[ISO7816E] is set/enabled. + */ #define UART_C4_MAEN1(x) (((uint8_t)(((uint8_t)(x)) << UART_C4_MAEN1_SHIFT)) & UART_C4_MAEN1_MASK) +/*! @} */ /*! @name C5 - UART Control Register 5 */ +/*! @{ */ #define UART_C5_LBKDDMAS_MASK (0x8U) #define UART_C5_LBKDDMAS_SHIFT (3U) +/*! LBKDDMAS - LIN Break Detect DMA Select Bit + * 0b0..If BDH[LBKDIE] and S2[LBKDIF] are set, the LBKDIF interrupt signal is asserted to request an interrupt service. + * 0b1..If BDH[LBKDIE] and S2[LBKDIF] are set, the LBKDIF DMA request signal is asserted to request a DMA transfer. + */ #define UART_C5_LBKDDMAS(x) (((uint8_t)(((uint8_t)(x)) << UART_C5_LBKDDMAS_SHIFT)) & UART_C5_LBKDDMAS_MASK) #define UART_C5_ILDMAS_MASK (0x10U) #define UART_C5_ILDMAS_SHIFT (4U) +/*! ILDMAS - Idle Line DMA Select + * 0b0..If C2[ILIE] and S1[IDLE] are set, the IDLE interrupt request signal is asserted to request an interrupt service. + * 0b1..If C2[ILIE] and S1[IDLE] are set, the IDLE DMA request signal is asserted to request a DMA transfer. + */ #define UART_C5_ILDMAS(x) (((uint8_t)(((uint8_t)(x)) << UART_C5_ILDMAS_SHIFT)) & UART_C5_ILDMAS_MASK) #define UART_C5_RDMAS_MASK (0x20U) #define UART_C5_RDMAS_SHIFT (5U) +/*! RDMAS - Receiver Full DMA Select + * 0b0..If C2[RIE] and S1[RDRF] are set, the RDFR interrupt request signal is asserted to request an interrupt service. + * 0b1..If C2[RIE] and S1[RDRF] are set, the RDRF DMA request signal is asserted to request a DMA transfer. + */ #define UART_C5_RDMAS(x) (((uint8_t)(((uint8_t)(x)) << UART_C5_RDMAS_SHIFT)) & UART_C5_RDMAS_MASK) #define UART_C5_TCDMAS_MASK (0x40U) #define UART_C5_TCDMAS_SHIFT (6U) +/*! TCDMAS - Transmission Complete DMA Select + * 0b0..If C2[TCIE] is set and the S1[TC] flag is set, the TC interrupt request signal is asserted to request an interrupt service. + * 0b1..If C2[TCIE] is set and the S1[TC] flag is set, the TC DMA request signal is asserted to request a DMA transfer. + */ #define UART_C5_TCDMAS(x) (((uint8_t)(((uint8_t)(x)) << UART_C5_TCDMAS_SHIFT)) & UART_C5_TCDMAS_MASK) #define UART_C5_TDMAS_MASK (0x80U) #define UART_C5_TDMAS_SHIFT (7U) +/*! TDMAS - Transmitter DMA Select + * 0b0..If C2[TIE] is set and the S1[TDRE] flag is set, the TDRE interrupt request signal is asserted to request interrupt service. + * 0b1..If C2[TIE] is set and the S1[TDRE] flag is set, the TDRE DMA request signal is asserted to request a DMA transfer. + */ #define UART_C5_TDMAS(x) (((uint8_t)(((uint8_t)(x)) << UART_C5_TDMAS_SHIFT)) & UART_C5_TDMAS_MASK) +/*! @} */ /*! @name ED - UART Extended Data Register */ +/*! @{ */ #define UART_ED_PARITYE_MASK (0x40U) #define UART_ED_PARITYE_SHIFT (6U) +/*! PARITYE + * 0b0..The dataword was received without a parity error. + * 0b1..The dataword was received with a parity error. + */ #define UART_ED_PARITYE(x) (((uint8_t)(((uint8_t)(x)) << UART_ED_PARITYE_SHIFT)) & UART_ED_PARITYE_MASK) #define UART_ED_NOISY_MASK (0x80U) #define UART_ED_NOISY_SHIFT (7U) +/*! NOISY + * 0b0..The dataword was received without noise. + * 0b1..The data was received with noise. + */ #define UART_ED_NOISY(x) (((uint8_t)(((uint8_t)(x)) << UART_ED_NOISY_SHIFT)) & UART_ED_NOISY_MASK) +/*! @} */ /*! @name MODEM - UART Modem Register */ +/*! @{ */ #define UART_MODEM_TXCTSE_MASK (0x1U) #define UART_MODEM_TXCTSE_SHIFT (0U) +/*! TXCTSE - Transmitter clear-to-send enable + * 0b0..CTS has no effect on the transmitter. + * 0b1..Enables clear-to-send operation. The transmitter checks the state of CTS each time it is ready to send a character. If CTS is asserted, the character is sent. If CTS is deasserted, the signal TXD remains in the mark state and transmission is delayed until CTS is asserted. Changes in CTS as a character is being sent do not affect its transmission. + */ #define UART_MODEM_TXCTSE(x) (((uint8_t)(((uint8_t)(x)) << UART_MODEM_TXCTSE_SHIFT)) & UART_MODEM_TXCTSE_MASK) #define UART_MODEM_TXRTSE_MASK (0x2U) #define UART_MODEM_TXRTSE_SHIFT (1U) +/*! TXRTSE - Transmitter request-to-send enable + * 0b0..The transmitter has no effect on RTS. + * 0b1..When a character is placed into an empty transmitter data buffer , RTS asserts one bit time before the start bit is transmitted. RTS deasserts one bit time after all characters in the transmitter data buffer and shift register are completely sent, including the last stop bit. (FIFO) (FIFO) + */ #define UART_MODEM_TXRTSE(x) (((uint8_t)(((uint8_t)(x)) << UART_MODEM_TXRTSE_SHIFT)) & UART_MODEM_TXRTSE_MASK) #define UART_MODEM_TXRTSPOL_MASK (0x4U) #define UART_MODEM_TXRTSPOL_SHIFT (2U) +/*! TXRTSPOL - Transmitter request-to-send polarity + * 0b0..Transmitter RTS is active low. + * 0b1..Transmitter RTS is active high. + */ #define UART_MODEM_TXRTSPOL(x) (((uint8_t)(((uint8_t)(x)) << UART_MODEM_TXRTSPOL_SHIFT)) & UART_MODEM_TXRTSPOL_MASK) #define UART_MODEM_RXRTSE_MASK (0x8U) #define UART_MODEM_RXRTSE_SHIFT (3U) +/*! RXRTSE - Receiver request-to-send enable + * 0b0..The receiver has no effect on RTS. + * 0b1..RTS is deasserted if the number of characters in the receiver data register (FIFO) is equal to or greater than RWFIFO[RXWATER]. RTS is asserted when the number of characters in the receiver data register (FIFO) is less than RWFIFO[RXWATER]. + */ #define UART_MODEM_RXRTSE(x) (((uint8_t)(((uint8_t)(x)) << UART_MODEM_RXRTSE_SHIFT)) & UART_MODEM_RXRTSE_MASK) +/*! @} */ /*! @name IR - UART Infrared Register */ +/*! @{ */ #define UART_IR_TNP_MASK (0x3U) #define UART_IR_TNP_SHIFT (0U) +/*! TNP - Transmitter narrow pulse + * 0b00..3/16. + * 0b01..1/16. + * 0b10..1/32. + * 0b11..1/4. + */ #define UART_IR_TNP(x) (((uint8_t)(((uint8_t)(x)) << UART_IR_TNP_SHIFT)) & UART_IR_TNP_MASK) #define UART_IR_IREN_MASK (0x4U) #define UART_IR_IREN_SHIFT (2U) +/*! IREN - Infrared enable + * 0b0..IR disabled. + * 0b1..IR enabled. + */ #define UART_IR_IREN(x) (((uint8_t)(((uint8_t)(x)) << UART_IR_IREN_SHIFT)) & UART_IR_IREN_MASK) +/*! @} */ /*! @name PFIFO - UART FIFO Parameters */ +/*! @{ */ #define UART_PFIFO_RXFIFOSIZE_MASK (0x7U) #define UART_PFIFO_RXFIFOSIZE_SHIFT (0U) +/*! RXFIFOSIZE - Receive FIFO. Buffer Depth + * 0b000..Receive FIFO/Buffer depth = 1 dataword. + * 0b001..Receive FIFO/Buffer depth = 4 datawords. + * 0b010..Receive FIFO/Buffer depth = 8 datawords. + * 0b011..Receive FIFO/Buffer depth = 16 datawords. + * 0b100..Receive FIFO/Buffer depth = 32 datawords. + * 0b101..Receive FIFO/Buffer depth = 64 datawords. + * 0b110..Receive FIFO/Buffer depth = 128 datawords. + * 0b111..Reserved. + */ #define UART_PFIFO_RXFIFOSIZE(x) (((uint8_t)(((uint8_t)(x)) << UART_PFIFO_RXFIFOSIZE_SHIFT)) & UART_PFIFO_RXFIFOSIZE_MASK) #define UART_PFIFO_RXFE_MASK (0x8U) #define UART_PFIFO_RXFE_SHIFT (3U) +/*! RXFE - Receive FIFO Enable + * 0b0..Receive FIFO is not enabled. Buffer is depth 1. (Legacy support) + * 0b1..Receive FIFO is enabled. Buffer is depth indicted by RXFIFOSIZE. + */ #define UART_PFIFO_RXFE(x) (((uint8_t)(((uint8_t)(x)) << UART_PFIFO_RXFE_SHIFT)) & UART_PFIFO_RXFE_MASK) #define UART_PFIFO_TXFIFOSIZE_MASK (0x70U) #define UART_PFIFO_TXFIFOSIZE_SHIFT (4U) +/*! TXFIFOSIZE - Transmit FIFO. Buffer Depth + * 0b000..Transmit FIFO/Buffer depth = 1 dataword. + * 0b001..Transmit FIFO/Buffer depth = 4 datawords. + * 0b010..Transmit FIFO/Buffer depth = 8 datawords. + * 0b011..Transmit FIFO/Buffer depth = 16 datawords. + * 0b100..Transmit FIFO/Buffer depth = 32 datawords. + * 0b101..Transmit FIFO/Buffer depth = 64 datawords. + * 0b110..Transmit FIFO/Buffer depth = 128 datawords. + * 0b111..Reserved. + */ #define UART_PFIFO_TXFIFOSIZE(x) (((uint8_t)(((uint8_t)(x)) << UART_PFIFO_TXFIFOSIZE_SHIFT)) & UART_PFIFO_TXFIFOSIZE_MASK) #define UART_PFIFO_TXFE_MASK (0x80U) #define UART_PFIFO_TXFE_SHIFT (7U) +/*! TXFE - Transmit FIFO Enable + * 0b0..Transmit FIFO is not enabled. Buffer is depth 1. (Legacy support). + * 0b1..Transmit FIFO is enabled. Buffer is depth indicated by TXFIFOSIZE. + */ #define UART_PFIFO_TXFE(x) (((uint8_t)(((uint8_t)(x)) << UART_PFIFO_TXFE_SHIFT)) & UART_PFIFO_TXFE_MASK) +/*! @} */ /*! @name CFIFO - UART FIFO Control Register */ +/*! @{ */ #define UART_CFIFO_RXUFE_MASK (0x1U) #define UART_CFIFO_RXUFE_SHIFT (0U) +/*! RXUFE - Receive FIFO Underflow Interrupt Enable + * 0b0..RXUF flag does not generate an interrupt to the host. + * 0b1..RXUF flag generates an interrupt to the host. + */ #define UART_CFIFO_RXUFE(x) (((uint8_t)(((uint8_t)(x)) << UART_CFIFO_RXUFE_SHIFT)) & UART_CFIFO_RXUFE_MASK) #define UART_CFIFO_TXOFE_MASK (0x2U) #define UART_CFIFO_TXOFE_SHIFT (1U) +/*! TXOFE - Transmit FIFO Overflow Interrupt Enable + * 0b0..TXOF flag does not generate an interrupt to the host. + * 0b1..TXOF flag generates an interrupt to the host. + */ #define UART_CFIFO_TXOFE(x) (((uint8_t)(((uint8_t)(x)) << UART_CFIFO_TXOFE_SHIFT)) & UART_CFIFO_TXOFE_MASK) #define UART_CFIFO_RXOFE_MASK (0x4U) #define UART_CFIFO_RXOFE_SHIFT (2U) +/*! RXOFE - Receive FIFO Overflow Interrupt Enable + * 0b0..RXOF flag does not generate an interrupt to the host. + * 0b1..RXOF flag generates an interrupt to the host. + */ #define UART_CFIFO_RXOFE(x) (((uint8_t)(((uint8_t)(x)) << UART_CFIFO_RXOFE_SHIFT)) & UART_CFIFO_RXOFE_MASK) #define UART_CFIFO_RXFLUSH_MASK (0x40U) #define UART_CFIFO_RXFLUSH_SHIFT (6U) +/*! RXFLUSH - Receive FIFO/Buffer Flush + * 0b0..No flush operation occurs. + * 0b1..All data in the receive FIFO/buffer is cleared out. + */ #define UART_CFIFO_RXFLUSH(x) (((uint8_t)(((uint8_t)(x)) << UART_CFIFO_RXFLUSH_SHIFT)) & UART_CFIFO_RXFLUSH_MASK) #define UART_CFIFO_TXFLUSH_MASK (0x80U) #define UART_CFIFO_TXFLUSH_SHIFT (7U) +/*! TXFLUSH - Transmit FIFO/Buffer Flush + * 0b0..No flush operation occurs. + * 0b1..All data in the transmit FIFO/Buffer is cleared out. + */ #define UART_CFIFO_TXFLUSH(x) (((uint8_t)(((uint8_t)(x)) << UART_CFIFO_TXFLUSH_SHIFT)) & UART_CFIFO_TXFLUSH_MASK) +/*! @} */ /*! @name SFIFO - UART FIFO Status Register */ +/*! @{ */ #define UART_SFIFO_RXUF_MASK (0x1U) #define UART_SFIFO_RXUF_SHIFT (0U) +/*! RXUF - Receiver Buffer Underflow Flag + * 0b0..No receive buffer underflow has occurred since the last time the flag was cleared. + * 0b1..At least one receive buffer underflow has occurred since the last time the flag was cleared. + */ #define UART_SFIFO_RXUF(x) (((uint8_t)(((uint8_t)(x)) << UART_SFIFO_RXUF_SHIFT)) & UART_SFIFO_RXUF_MASK) #define UART_SFIFO_TXOF_MASK (0x2U) #define UART_SFIFO_TXOF_SHIFT (1U) +/*! TXOF - Transmitter Buffer Overflow Flag + * 0b0..No transmit buffer overflow has occurred since the last time the flag was cleared. + * 0b1..At least one transmit buffer overflow has occurred since the last time the flag was cleared. + */ #define UART_SFIFO_TXOF(x) (((uint8_t)(((uint8_t)(x)) << UART_SFIFO_TXOF_SHIFT)) & UART_SFIFO_TXOF_MASK) #define UART_SFIFO_RXOF_MASK (0x4U) #define UART_SFIFO_RXOF_SHIFT (2U) +/*! RXOF - Receiver Buffer Overflow Flag + * 0b0..No receive buffer overflow has occurred since the last time the flag was cleared. + * 0b1..At least one receive buffer overflow has occurred since the last time the flag was cleared. + */ #define UART_SFIFO_RXOF(x) (((uint8_t)(((uint8_t)(x)) << UART_SFIFO_RXOF_SHIFT)) & UART_SFIFO_RXOF_MASK) #define UART_SFIFO_RXEMPT_MASK (0x40U) #define UART_SFIFO_RXEMPT_SHIFT (6U) +/*! RXEMPT - Receive Buffer/FIFO Empty + * 0b0..Receive buffer is not empty. + * 0b1..Receive buffer is empty. + */ #define UART_SFIFO_RXEMPT(x) (((uint8_t)(((uint8_t)(x)) << UART_SFIFO_RXEMPT_SHIFT)) & UART_SFIFO_RXEMPT_MASK) #define UART_SFIFO_TXEMPT_MASK (0x80U) #define UART_SFIFO_TXEMPT_SHIFT (7U) +/*! TXEMPT - Transmit Buffer/FIFO Empty + * 0b0..Transmit buffer is not empty. + * 0b1..Transmit buffer is empty. + */ #define UART_SFIFO_TXEMPT(x) (((uint8_t)(((uint8_t)(x)) << UART_SFIFO_TXEMPT_SHIFT)) & UART_SFIFO_TXEMPT_MASK) +/*! @} */ /*! @name TWFIFO - UART FIFO Transmit Watermark */ +/*! @{ */ #define UART_TWFIFO_TXWATER_MASK (0xFFU) #define UART_TWFIFO_TXWATER_SHIFT (0U) #define UART_TWFIFO_TXWATER(x) (((uint8_t)(((uint8_t)(x)) << UART_TWFIFO_TXWATER_SHIFT)) & UART_TWFIFO_TXWATER_MASK) +/*! @} */ /*! @name TCFIFO - UART FIFO Transmit Count */ +/*! @{ */ #define UART_TCFIFO_TXCOUNT_MASK (0xFFU) #define UART_TCFIFO_TXCOUNT_SHIFT (0U) #define UART_TCFIFO_TXCOUNT(x) (((uint8_t)(((uint8_t)(x)) << UART_TCFIFO_TXCOUNT_SHIFT)) & UART_TCFIFO_TXCOUNT_MASK) +/*! @} */ /*! @name RWFIFO - UART FIFO Receive Watermark */ +/*! @{ */ #define UART_RWFIFO_RXWATER_MASK (0xFFU) #define UART_RWFIFO_RXWATER_SHIFT (0U) #define UART_RWFIFO_RXWATER(x) (((uint8_t)(((uint8_t)(x)) << UART_RWFIFO_RXWATER_SHIFT)) & UART_RWFIFO_RXWATER_MASK) +/*! @} */ /*! @name RCFIFO - UART FIFO Receive Count */ +/*! @{ */ #define UART_RCFIFO_RXCOUNT_MASK (0xFFU) #define UART_RCFIFO_RXCOUNT_SHIFT (0U) #define UART_RCFIFO_RXCOUNT(x) (((uint8_t)(((uint8_t)(x)) << UART_RCFIFO_RXCOUNT_SHIFT)) & UART_RCFIFO_RXCOUNT_MASK) +/*! @} */ /*! @name C7816 - UART 7816 Control Register */ +/*! @{ */ #define UART_C7816_ISO_7816E_MASK (0x1U) #define UART_C7816_ISO_7816E_SHIFT (0U) +/*! ISO_7816E - ISO-7816 Functionality Enabled + * 0b0..ISO-7816 functionality is turned off/not enabled. + * 0b1..ISO-7816 functionality is turned on/enabled. + */ #define UART_C7816_ISO_7816E(x) (((uint8_t)(((uint8_t)(x)) << UART_C7816_ISO_7816E_SHIFT)) & UART_C7816_ISO_7816E_MASK) #define UART_C7816_TTYPE_MASK (0x2U) #define UART_C7816_TTYPE_SHIFT (1U) +/*! TTYPE - Transfer Type + * 0b0..T = 0 per the ISO-7816 specification. + * 0b1..T = 1 per the ISO-7816 specification. + */ #define UART_C7816_TTYPE(x) (((uint8_t)(((uint8_t)(x)) << UART_C7816_TTYPE_SHIFT)) & UART_C7816_TTYPE_MASK) #define UART_C7816_INIT_MASK (0x4U) #define UART_C7816_INIT_SHIFT (2U) +/*! INIT - Detect Initial Character + * 0b0..Normal operating mode. Receiver does not seek to identify initial character. + * 0b1..Receiver searches for initial character. + */ #define UART_C7816_INIT(x) (((uint8_t)(((uint8_t)(x)) << UART_C7816_INIT_SHIFT)) & UART_C7816_INIT_MASK) #define UART_C7816_ANACK_MASK (0x8U) #define UART_C7816_ANACK_SHIFT (3U) +/*! ANACK - Generate NACK on Error + * 0b0..No NACK is automatically generated. + * 0b1..A NACK is automatically generated if a parity error is detected or if an invalid initial character is detected. + */ #define UART_C7816_ANACK(x) (((uint8_t)(((uint8_t)(x)) << UART_C7816_ANACK_SHIFT)) & UART_C7816_ANACK_MASK) #define UART_C7816_ONACK_MASK (0x10U) #define UART_C7816_ONACK_SHIFT (4U) +/*! ONACK - Generate NACK on Overflow + * 0b0..The received data does not generate a NACK when the receipt of the data results in an overflow event. + * 0b1..If the receiver buffer overflows, a NACK is automatically sent on a received character. + */ #define UART_C7816_ONACK(x) (((uint8_t)(((uint8_t)(x)) << UART_C7816_ONACK_SHIFT)) & UART_C7816_ONACK_MASK) +/*! @} */ /*! @name IE7816 - UART 7816 Interrupt Enable Register */ +/*! @{ */ #define UART_IE7816_RXTE_MASK (0x1U) #define UART_IE7816_RXTE_SHIFT (0U) +/*! RXTE - Receive Threshold Exceeded Interrupt Enable + * 0b0..The assertion of IS7816[RXT] does not result in the generation of an interrupt. + * 0b1..The assertion of IS7816[RXT] results in the generation of an interrupt. + */ #define UART_IE7816_RXTE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_RXTE_SHIFT)) & UART_IE7816_RXTE_MASK) #define UART_IE7816_TXTE_MASK (0x2U) #define UART_IE7816_TXTE_SHIFT (1U) +/*! TXTE - Transmit Threshold Exceeded Interrupt Enable + * 0b0..The assertion of IS7816[TXT] does not result in the generation of an interrupt. + * 0b1..The assertion of IS7816[TXT] results in the generation of an interrupt. + */ #define UART_IE7816_TXTE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_TXTE_SHIFT)) & UART_IE7816_TXTE_MASK) #define UART_IE7816_GTVE_MASK (0x4U) #define UART_IE7816_GTVE_SHIFT (2U) +/*! GTVE - Guard Timer Violated Interrupt Enable + * 0b0..The assertion of IS7816[GTV] does not result in the generation of an interrupt. + * 0b1..The assertion of IS7816[GTV] results in the generation of an interrupt. + */ #define UART_IE7816_GTVE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_GTVE_SHIFT)) & UART_IE7816_GTVE_MASK) #define UART_IE7816_INITDE_MASK (0x10U) #define UART_IE7816_INITDE_SHIFT (4U) +/*! INITDE - Initial Character Detected Interrupt Enable + * 0b0..The assertion of IS7816[INITD] does not result in the generation of an interrupt. + * 0b1..The assertion of IS7816[INITD] results in the generation of an interrupt. + */ #define UART_IE7816_INITDE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_INITDE_SHIFT)) & UART_IE7816_INITDE_MASK) #define UART_IE7816_BWTE_MASK (0x20U) #define UART_IE7816_BWTE_SHIFT (5U) +/*! BWTE - Block Wait Timer Interrupt Enable + * 0b0..The assertion of IS7816[BWT] does not result in the generation of an interrupt. + * 0b1..The assertion of IS7816[BWT] results in the generation of an interrupt. + */ #define UART_IE7816_BWTE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_BWTE_SHIFT)) & UART_IE7816_BWTE_MASK) #define UART_IE7816_CWTE_MASK (0x40U) #define UART_IE7816_CWTE_SHIFT (6U) +/*! CWTE - Character Wait Timer Interrupt Enable + * 0b0..The assertion of IS7816[CWT] does not result in the generation of an interrupt. + * 0b1..The assertion of IS7816[CWT] results in the generation of an interrupt. + */ #define UART_IE7816_CWTE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_CWTE_SHIFT)) & UART_IE7816_CWTE_MASK) #define UART_IE7816_WTE_MASK (0x80U) #define UART_IE7816_WTE_SHIFT (7U) +/*! WTE - Wait Timer Interrupt Enable + * 0b0..The assertion of IS7816[WT] does not result in the generation of an interrupt. + * 0b1..The assertion of IS7816[WT] results in the generation of an interrupt. + */ #define UART_IE7816_WTE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_WTE_SHIFT)) & UART_IE7816_WTE_MASK) +/*! @} */ /*! @name IS7816 - UART 7816 Interrupt Status Register */ +/*! @{ */ #define UART_IS7816_RXT_MASK (0x1U) #define UART_IS7816_RXT_SHIFT (0U) +/*! RXT - Receive Threshold Exceeded Interrupt + * 0b0..The number of consecutive NACKS generated as a result of parity errors and buffer overruns is less than or equal to the value in ET7816[RXTHRESHOLD]. + * 0b1..The number of consecutive NACKS generated as a result of parity errors and buffer overruns is greater than the value in ET7816[RXTHRESHOLD]. + */ #define UART_IS7816_RXT(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_RXT_SHIFT)) & UART_IS7816_RXT_MASK) #define UART_IS7816_TXT_MASK (0x2U) #define UART_IS7816_TXT_SHIFT (1U) +/*! TXT - Transmit Threshold Exceeded Interrupt + * 0b0..The number of retries and corresponding NACKS does not exceed the value in ET7816[TXTHRESHOLD]. + * 0b1..The number of retries and corresponding NACKS exceeds the value in ET7816[TXTHRESHOLD]. + */ #define UART_IS7816_TXT(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_TXT_SHIFT)) & UART_IS7816_TXT_MASK) #define UART_IS7816_GTV_MASK (0x4U) #define UART_IS7816_GTV_SHIFT (2U) +/*! GTV - Guard Timer Violated Interrupt + * 0b0..A guard time (GT, CGT, or BGT) has not been violated. + * 0b1..A guard time (GT, CGT, or BGT) has been violated. + */ #define UART_IS7816_GTV(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_GTV_SHIFT)) & UART_IS7816_GTV_MASK) #define UART_IS7816_INITD_MASK (0x10U) #define UART_IS7816_INITD_SHIFT (4U) +/*! INITD - Initial Character Detected Interrupt + * 0b0..A valid initial character has not been received. + * 0b1..A valid initial character has been received. + */ #define UART_IS7816_INITD(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_INITD_SHIFT)) & UART_IS7816_INITD_MASK) #define UART_IS7816_BWT_MASK (0x20U) #define UART_IS7816_BWT_SHIFT (5U) +/*! BWT - Block Wait Timer Interrupt + * 0b0..Block wait time (BWT) has not been violated. + * 0b1..Block wait time (BWT) has been violated. + */ #define UART_IS7816_BWT(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_BWT_SHIFT)) & UART_IS7816_BWT_MASK) #define UART_IS7816_CWT_MASK (0x40U) #define UART_IS7816_CWT_SHIFT (6U) +/*! CWT - Character Wait Timer Interrupt + * 0b0..Character wait time (CWT) has not been violated. + * 0b1..Character wait time (CWT) has been violated. + */ #define UART_IS7816_CWT(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_CWT_SHIFT)) & UART_IS7816_CWT_MASK) #define UART_IS7816_WT_MASK (0x80U) #define UART_IS7816_WT_SHIFT (7U) +/*! WT - Wait Timer Interrupt + * 0b0..Wait time (WT) has not been violated. + * 0b1..Wait time (WT) has been violated. + */ #define UART_IS7816_WT(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_WT_SHIFT)) & UART_IS7816_WT_MASK) +/*! @} */ /*! @name WP7816T0 - UART 7816 Wait Parameter Register */ +/*! @{ */ #define UART_WP7816T0_WI_MASK (0xFFU) #define UART_WP7816T0_WI_SHIFT (0U) #define UART_WP7816T0_WI(x) (((uint8_t)(((uint8_t)(x)) << UART_WP7816T0_WI_SHIFT)) & UART_WP7816T0_WI_MASK) +/*! @} */ /*! @name WP7816T1 - UART 7816 Wait Parameter Register */ +/*! @{ */ #define UART_WP7816T1_BWI_MASK (0xFU) #define UART_WP7816T1_BWI_SHIFT (0U) #define UART_WP7816T1_BWI(x) (((uint8_t)(((uint8_t)(x)) << UART_WP7816T1_BWI_SHIFT)) & UART_WP7816T1_BWI_MASK) #define UART_WP7816T1_CWI_MASK (0xF0U) #define UART_WP7816T1_CWI_SHIFT (4U) #define UART_WP7816T1_CWI(x) (((uint8_t)(((uint8_t)(x)) << UART_WP7816T1_CWI_SHIFT)) & UART_WP7816T1_CWI_MASK) +/*! @} */ /*! @name WN7816 - UART 7816 Wait N Register */ +/*! @{ */ #define UART_WN7816_GTN_MASK (0xFFU) #define UART_WN7816_GTN_SHIFT (0U) #define UART_WN7816_GTN(x) (((uint8_t)(((uint8_t)(x)) << UART_WN7816_GTN_SHIFT)) & UART_WN7816_GTN_MASK) +/*! @} */ /*! @name WF7816 - UART 7816 Wait FD Register */ +/*! @{ */ #define UART_WF7816_GTFD_MASK (0xFFU) #define UART_WF7816_GTFD_SHIFT (0U) #define UART_WF7816_GTFD(x) (((uint8_t)(((uint8_t)(x)) << UART_WF7816_GTFD_SHIFT)) & UART_WF7816_GTFD_MASK) +/*! @} */ /*! @name ET7816 - UART 7816 Error Threshold Register */ +/*! @{ */ #define UART_ET7816_RXTHRESHOLD_MASK (0xFU) #define UART_ET7816_RXTHRESHOLD_SHIFT (0U) #define UART_ET7816_RXTHRESHOLD(x) (((uint8_t)(((uint8_t)(x)) << UART_ET7816_RXTHRESHOLD_SHIFT)) & UART_ET7816_RXTHRESHOLD_MASK) #define UART_ET7816_TXTHRESHOLD_MASK (0xF0U) #define UART_ET7816_TXTHRESHOLD_SHIFT (4U) +/*! TXTHRESHOLD - Transmit NACK Threshold + * 0b0000..TXT asserts on the first NACK that is received. + * 0b0001..TXT asserts on the second NACK that is received. + */ #define UART_ET7816_TXTHRESHOLD(x) (((uint8_t)(((uint8_t)(x)) << UART_ET7816_TXTHRESHOLD_SHIFT)) & UART_ET7816_TXTHRESHOLD_MASK) +/*! @} */ /*! @name TL7816 - UART 7816 Transmit Length Register */ +/*! @{ */ #define UART_TL7816_TLEN_MASK (0xFFU) #define UART_TL7816_TLEN_SHIFT (0U) #define UART_TL7816_TLEN(x) (((uint8_t)(((uint8_t)(x)) << UART_TL7816_TLEN_SHIFT)) & UART_TL7816_TLEN_MASK) +/*! @} */ /*! @@ -11868,29 +21077,38 @@ typedef struct { */ /*! @name PERID - Peripheral ID register */ +/*! @{ */ #define USB_PERID_ID_MASK (0x3FU) #define USB_PERID_ID_SHIFT (0U) #define USB_PERID_ID(x) (((uint8_t)(((uint8_t)(x)) << USB_PERID_ID_SHIFT)) & USB_PERID_ID_MASK) +/*! @} */ /*! @name IDCOMP - Peripheral ID Complement register */ +/*! @{ */ #define USB_IDCOMP_NID_MASK (0x3FU) #define USB_IDCOMP_NID_SHIFT (0U) #define USB_IDCOMP_NID(x) (((uint8_t)(((uint8_t)(x)) << USB_IDCOMP_NID_SHIFT)) & USB_IDCOMP_NID_MASK) +/*! @} */ /*! @name REV - Peripheral Revision register */ +/*! @{ */ #define USB_REV_REV_MASK (0xFFU) #define USB_REV_REV_SHIFT (0U) #define USB_REV_REV(x) (((uint8_t)(((uint8_t)(x)) << USB_REV_REV_SHIFT)) & USB_REV_REV_MASK) +/*! @} */ /*! @name ADDINFO - Peripheral Additional Info register */ +/*! @{ */ #define USB_ADDINFO_IEHOST_MASK (0x1U) #define USB_ADDINFO_IEHOST_SHIFT (0U) #define USB_ADDINFO_IEHOST(x) (((uint8_t)(((uint8_t)(x)) << USB_ADDINFO_IEHOST_SHIFT)) & USB_ADDINFO_IEHOST_MASK) #define USB_ADDINFO_IRQNUM_MASK (0xF8U) #define USB_ADDINFO_IRQNUM_SHIFT (3U) #define USB_ADDINFO_IRQNUM(x) (((uint8_t)(((uint8_t)(x)) << USB_ADDINFO_IRQNUM_SHIFT)) & USB_ADDINFO_IRQNUM_MASK) +/*! @} */ /*! @name OTGISTAT - OTG Interrupt Status register */ +/*! @{ */ #define USB_OTGISTAT_AVBUSCHG_MASK (0x1U) #define USB_OTGISTAT_AVBUSCHG_SHIFT (0U) #define USB_OTGISTAT_AVBUSCHG(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_AVBUSCHG_SHIFT)) & USB_OTGISTAT_AVBUSCHG_MASK) @@ -11909,62 +21127,130 @@ typedef struct { #define USB_OTGISTAT_IDCHG_MASK (0x80U) #define USB_OTGISTAT_IDCHG_SHIFT (7U) #define USB_OTGISTAT_IDCHG(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_IDCHG_SHIFT)) & USB_OTGISTAT_IDCHG_MASK) +/*! @} */ /*! @name OTGICR - OTG Interrupt Control register */ +/*! @{ */ #define USB_OTGICR_AVBUSEN_MASK (0x1U) #define USB_OTGICR_AVBUSEN_SHIFT (0U) +/*! AVBUSEN - A VBUS Valid Interrupt Enable + * 0b0..Disables the AVBUSCHG interrupt. + * 0b1..Enables the AVBUSCHG interrupt. + */ #define USB_OTGICR_AVBUSEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_AVBUSEN_SHIFT)) & USB_OTGICR_AVBUSEN_MASK) #define USB_OTGICR_BSESSEN_MASK (0x4U) #define USB_OTGICR_BSESSEN_SHIFT (2U) +/*! BSESSEN - B Session END Interrupt Enable + * 0b0..Disables the B_SESS_CHG interrupt. + * 0b1..Enables the B_SESS_CHG interrupt. + */ #define USB_OTGICR_BSESSEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_BSESSEN_SHIFT)) & USB_OTGICR_BSESSEN_MASK) #define USB_OTGICR_SESSVLDEN_MASK (0x8U) #define USB_OTGICR_SESSVLDEN_SHIFT (3U) +/*! SESSVLDEN - Session Valid Interrupt Enable + * 0b0..Disables the SESSVLDCHG interrupt. + * 0b1..Enables the SESSVLDCHG interrupt. + */ #define USB_OTGICR_SESSVLDEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_SESSVLDEN_SHIFT)) & USB_OTGICR_SESSVLDEN_MASK) #define USB_OTGICR_LINESTATEEN_MASK (0x20U) #define USB_OTGICR_LINESTATEEN_SHIFT (5U) +/*! LINESTATEEN - Line State Change Interrupt Enable + * 0b0..Disables the LINE_STAT_CHG interrupt. + * 0b1..Enables the LINE_STAT_CHG interrupt. + */ #define USB_OTGICR_LINESTATEEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_LINESTATEEN_SHIFT)) & USB_OTGICR_LINESTATEEN_MASK) #define USB_OTGICR_ONEMSECEN_MASK (0x40U) #define USB_OTGICR_ONEMSECEN_SHIFT (6U) +/*! ONEMSECEN - One Millisecond Interrupt Enable + * 0b0..Diables the 1ms timer interrupt. + * 0b1..Enables the 1ms timer interrupt. + */ #define USB_OTGICR_ONEMSECEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_ONEMSECEN_SHIFT)) & USB_OTGICR_ONEMSECEN_MASK) #define USB_OTGICR_IDEN_MASK (0x80U) #define USB_OTGICR_IDEN_SHIFT (7U) +/*! IDEN - ID Interrupt Enable + * 0b0..The ID interrupt is disabled + * 0b1..The ID interrupt is enabled + */ #define USB_OTGICR_IDEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_IDEN_SHIFT)) & USB_OTGICR_IDEN_MASK) +/*! @} */ /*! @name OTGSTAT - OTG Status register */ +/*! @{ */ #define USB_OTGSTAT_AVBUSVLD_MASK (0x1U) #define USB_OTGSTAT_AVBUSVLD_SHIFT (0U) +/*! AVBUSVLD - A VBUS Valid + * 0b0..The VBUS voltage is below the A VBUS Valid threshold. + * 0b1..The VBUS voltage is above the A VBUS Valid threshold. + */ #define USB_OTGSTAT_AVBUSVLD(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_AVBUSVLD_SHIFT)) & USB_OTGSTAT_AVBUSVLD_MASK) #define USB_OTGSTAT_BSESSEND_MASK (0x4U) #define USB_OTGSTAT_BSESSEND_SHIFT (2U) +/*! BSESSEND - B Session End + * 0b0..The VBUS voltage is above the B session end threshold. + * 0b1..The VBUS voltage is below the B session end threshold. + */ #define USB_OTGSTAT_BSESSEND(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_BSESSEND_SHIFT)) & USB_OTGSTAT_BSESSEND_MASK) #define USB_OTGSTAT_SESS_VLD_MASK (0x8U) #define USB_OTGSTAT_SESS_VLD_SHIFT (3U) +/*! SESS_VLD - Session Valid + * 0b0..The VBUS voltage is below the B session valid threshold + * 0b1..The VBUS voltage is above the B session valid threshold. + */ #define USB_OTGSTAT_SESS_VLD(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_SESS_VLD_SHIFT)) & USB_OTGSTAT_SESS_VLD_MASK) #define USB_OTGSTAT_LINESTATESTABLE_MASK (0x20U) #define USB_OTGSTAT_LINESTATESTABLE_SHIFT (5U) +/*! LINESTATESTABLE + * 0b0..The LINE_STAT_CHG bit is not yet stable. + * 0b1..The LINE_STAT_CHG bit has been debounced and is stable. + */ #define USB_OTGSTAT_LINESTATESTABLE(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_LINESTATESTABLE_SHIFT)) & USB_OTGSTAT_LINESTATESTABLE_MASK) #define USB_OTGSTAT_ONEMSECEN_MASK (0x40U) #define USB_OTGSTAT_ONEMSECEN_SHIFT (6U) #define USB_OTGSTAT_ONEMSECEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_ONEMSECEN_SHIFT)) & USB_OTGSTAT_ONEMSECEN_MASK) #define USB_OTGSTAT_ID_MASK (0x80U) #define USB_OTGSTAT_ID_SHIFT (7U) +/*! ID + * 0b0..Indicates a Type A cable is plugged into the USB connector. + * 0b1..Indicates no cable is attached or a Type B cable is plugged into the USB connector. + */ #define USB_OTGSTAT_ID(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_ID_SHIFT)) & USB_OTGSTAT_ID_MASK) +/*! @} */ /*! @name OTGCTL - OTG Control register */ +/*! @{ */ #define USB_OTGCTL_OTGEN_MASK (0x4U) #define USB_OTGCTL_OTGEN_SHIFT (2U) +/*! OTGEN - On-The-Go pullup/pulldown resistor enable + * 0b0..If USB_EN is 1 and HOST_MODE is 0 in the Control Register (CTL), then the D+ Data Line pull-up resistors are enabled. If HOST_MODE is 1 the D+ and D- Data Line pull-down resistors are engaged. + * 0b1..The pull-up and pull-down controls in this register are used. + */ #define USB_OTGCTL_OTGEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGCTL_OTGEN_SHIFT)) & USB_OTGCTL_OTGEN_MASK) #define USB_OTGCTL_DMLOW_MASK (0x10U) #define USB_OTGCTL_DMLOW_SHIFT (4U) +/*! DMLOW - D- Data Line pull-down resistor enable + * 0b0..D- pulldown resistor is not enabled. + * 0b1..D- pulldown resistor is enabled. + */ #define USB_OTGCTL_DMLOW(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGCTL_DMLOW_SHIFT)) & USB_OTGCTL_DMLOW_MASK) #define USB_OTGCTL_DPLOW_MASK (0x20U) #define USB_OTGCTL_DPLOW_SHIFT (5U) +/*! DPLOW - D+ Data Line pull-down resistor enable + * 0b0..D+ pulldown resistor is not enabled. + * 0b1..D+ pulldown resistor is enabled. + */ #define USB_OTGCTL_DPLOW(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGCTL_DPLOW_SHIFT)) & USB_OTGCTL_DPLOW_MASK) #define USB_OTGCTL_DPHIGH_MASK (0x80U) #define USB_OTGCTL_DPHIGH_SHIFT (7U) +/*! DPHIGH - D+ Data Line pullup resistor enable + * 0b0..D+ pullup resistor is not enabled + * 0b1..D+ pullup resistor is enabled + */ #define USB_OTGCTL_DPHIGH(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGCTL_DPHIGH_SHIFT)) & USB_OTGCTL_DPHIGH_MASK) +/*! @} */ /*! @name ISTAT - Interrupt Status register */ +/*! @{ */ #define USB_ISTAT_USBRST_MASK (0x1U) #define USB_ISTAT_USBRST_SHIFT (0U) #define USB_ISTAT_USBRST(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_USBRST_SHIFT)) & USB_ISTAT_USBRST_MASK) @@ -11989,34 +21275,70 @@ typedef struct { #define USB_ISTAT_STALL_MASK (0x80U) #define USB_ISTAT_STALL_SHIFT (7U) #define USB_ISTAT_STALL(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_STALL_SHIFT)) & USB_ISTAT_STALL_MASK) +/*! @} */ /*! @name INTEN - Interrupt Enable register */ +/*! @{ */ #define USB_INTEN_USBRSTEN_MASK (0x1U) #define USB_INTEN_USBRSTEN_SHIFT (0U) +/*! USBRSTEN - USBRST Interrupt Enable + * 0b0..Disables the USBRST interrupt. + * 0b1..Enables the USBRST interrupt. + */ #define USB_INTEN_USBRSTEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_USBRSTEN_SHIFT)) & USB_INTEN_USBRSTEN_MASK) #define USB_INTEN_ERROREN_MASK (0x2U) #define USB_INTEN_ERROREN_SHIFT (1U) +/*! ERROREN - ERROR Interrupt Enable + * 0b0..Disables the ERROR interrupt. + * 0b1..Enables the ERROR interrupt. + */ #define USB_INTEN_ERROREN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_ERROREN_SHIFT)) & USB_INTEN_ERROREN_MASK) #define USB_INTEN_SOFTOKEN_MASK (0x4U) #define USB_INTEN_SOFTOKEN_SHIFT (2U) +/*! SOFTOKEN - SOFTOK Interrupt Enable + * 0b0..Disbles the SOFTOK interrupt. + * 0b1..Enables the SOFTOK interrupt. + */ #define USB_INTEN_SOFTOKEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_SOFTOKEN_SHIFT)) & USB_INTEN_SOFTOKEN_MASK) #define USB_INTEN_TOKDNEEN_MASK (0x8U) #define USB_INTEN_TOKDNEEN_SHIFT (3U) +/*! TOKDNEEN - TOKDNE Interrupt Enable + * 0b0..Disables the TOKDNE interrupt. + * 0b1..Enables the TOKDNE interrupt. + */ #define USB_INTEN_TOKDNEEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_TOKDNEEN_SHIFT)) & USB_INTEN_TOKDNEEN_MASK) #define USB_INTEN_SLEEPEN_MASK (0x10U) #define USB_INTEN_SLEEPEN_SHIFT (4U) +/*! SLEEPEN - SLEEP Interrupt Enable + * 0b0..Disables the SLEEP interrupt. + * 0b1..Enables the SLEEP interrupt. + */ #define USB_INTEN_SLEEPEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_SLEEPEN_SHIFT)) & USB_INTEN_SLEEPEN_MASK) #define USB_INTEN_RESUMEEN_MASK (0x20U) #define USB_INTEN_RESUMEEN_SHIFT (5U) +/*! RESUMEEN - RESUME Interrupt Enable + * 0b0..Disables the RESUME interrupt. + * 0b1..Enables the RESUME interrupt. + */ #define USB_INTEN_RESUMEEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_RESUMEEN_SHIFT)) & USB_INTEN_RESUMEEN_MASK) #define USB_INTEN_ATTACHEN_MASK (0x40U) #define USB_INTEN_ATTACHEN_SHIFT (6U) +/*! ATTACHEN - ATTACH Interrupt Enable + * 0b0..Disables the ATTACH interrupt. + * 0b1..Enables the ATTACH interrupt. + */ #define USB_INTEN_ATTACHEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_ATTACHEN_SHIFT)) & USB_INTEN_ATTACHEN_MASK) #define USB_INTEN_STALLEN_MASK (0x80U) #define USB_INTEN_STALLEN_SHIFT (7U) +/*! STALLEN - STALL Interrupt Enable + * 0b0..Diasbles the STALL interrupt. + * 0b1..Enables the STALL interrupt. + */ #define USB_INTEN_STALLEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_STALLEN_SHIFT)) & USB_INTEN_STALLEN_MASK) +/*! @} */ /*! @name ERRSTAT - Error Interrupt Status register */ +/*! @{ */ #define USB_ERRSTAT_PIDERR_MASK (0x1U) #define USB_ERRSTAT_PIDERR_SHIFT (0U) #define USB_ERRSTAT_PIDERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_PIDERR_SHIFT)) & USB_ERRSTAT_PIDERR_MASK) @@ -12038,44 +21360,86 @@ typedef struct { #define USB_ERRSTAT_BTSERR_MASK (0x80U) #define USB_ERRSTAT_BTSERR_SHIFT (7U) #define USB_ERRSTAT_BTSERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_BTSERR_SHIFT)) & USB_ERRSTAT_BTSERR_MASK) +/*! @} */ /*! @name ERREN - Error Interrupt Enable register */ +/*! @{ */ #define USB_ERREN_PIDERREN_MASK (0x1U) #define USB_ERREN_PIDERREN_SHIFT (0U) +/*! PIDERREN - PIDERR Interrupt Enable + * 0b0..Disables the PIDERR interrupt. + * 0b1..Enters the PIDERR interrupt. + */ #define USB_ERREN_PIDERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_PIDERREN_SHIFT)) & USB_ERREN_PIDERREN_MASK) #define USB_ERREN_CRC5EOFEN_MASK (0x2U) #define USB_ERREN_CRC5EOFEN_SHIFT (1U) +/*! CRC5EOFEN - CRC5/EOF Interrupt Enable + * 0b0..Disables the CRC5/EOF interrupt. + * 0b1..Enables the CRC5/EOF interrupt. + */ #define USB_ERREN_CRC5EOFEN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_CRC5EOFEN_SHIFT)) & USB_ERREN_CRC5EOFEN_MASK) #define USB_ERREN_CRC16EN_MASK (0x4U) #define USB_ERREN_CRC16EN_SHIFT (2U) +/*! CRC16EN - CRC16 Interrupt Enable + * 0b0..Disables the CRC16 interrupt. + * 0b1..Enables the CRC16 interrupt. + */ #define USB_ERREN_CRC16EN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_CRC16EN_SHIFT)) & USB_ERREN_CRC16EN_MASK) #define USB_ERREN_DFN8EN_MASK (0x8U) #define USB_ERREN_DFN8EN_SHIFT (3U) +/*! DFN8EN - DFN8 Interrupt Enable + * 0b0..Disables the DFN8 interrupt. + * 0b1..Enables the DFN8 interrupt. + */ #define USB_ERREN_DFN8EN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_DFN8EN_SHIFT)) & USB_ERREN_DFN8EN_MASK) #define USB_ERREN_BTOERREN_MASK (0x10U) #define USB_ERREN_BTOERREN_SHIFT (4U) +/*! BTOERREN - BTOERR Interrupt Enable + * 0b0..Disables the BTOERR interrupt. + * 0b1..Enables the BTOERR interrupt. + */ #define USB_ERREN_BTOERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_BTOERREN_SHIFT)) & USB_ERREN_BTOERREN_MASK) #define USB_ERREN_DMAERREN_MASK (0x20U) #define USB_ERREN_DMAERREN_SHIFT (5U) +/*! DMAERREN - DMAERR Interrupt Enable + * 0b0..Disables the DMAERR interrupt. + * 0b1..Enables the DMAERR interrupt. + */ #define USB_ERREN_DMAERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_DMAERREN_SHIFT)) & USB_ERREN_DMAERREN_MASK) #define USB_ERREN_BTSERREN_MASK (0x80U) #define USB_ERREN_BTSERREN_SHIFT (7U) +/*! BTSERREN - BTSERR Interrupt Enable + * 0b0..Disables the BTSERR interrupt. + * 0b1..Enables the BTSERR interrupt. + */ #define USB_ERREN_BTSERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_BTSERREN_SHIFT)) & USB_ERREN_BTSERREN_MASK) +/*! @} */ /*! @name STAT - Status register */ +/*! @{ */ #define USB_STAT_ODD_MASK (0x4U) #define USB_STAT_ODD_SHIFT (2U) #define USB_STAT_ODD(x) (((uint8_t)(((uint8_t)(x)) << USB_STAT_ODD_SHIFT)) & USB_STAT_ODD_MASK) #define USB_STAT_TX_MASK (0x8U) #define USB_STAT_TX_SHIFT (3U) +/*! TX - Transmit Indicator + * 0b0..The most recent transaction was a receive operation. + * 0b1..The most recent transaction was a transmit operation. + */ #define USB_STAT_TX(x) (((uint8_t)(((uint8_t)(x)) << USB_STAT_TX_SHIFT)) & USB_STAT_TX_MASK) #define USB_STAT_ENDP_MASK (0xF0U) #define USB_STAT_ENDP_SHIFT (4U) #define USB_STAT_ENDP(x) (((uint8_t)(((uint8_t)(x)) << USB_STAT_ENDP_SHIFT)) & USB_STAT_ENDP_MASK) +/*! @} */ /*! @name CTL - Control register */ +/*! @{ */ #define USB_CTL_USBENSOFEN_MASK (0x1U) #define USB_CTL_USBENSOFEN_SHIFT (0U) +/*! USBENSOFEN - USB Enable + * 0b0..Disables the USB Module. + * 0b1..Enables the USB Module. + */ #define USB_CTL_USBENSOFEN(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_USBENSOFEN_SHIFT)) & USB_CTL_USBENSOFEN_MASK) #define USB_CTL_ODDRST_MASK (0x2U) #define USB_CTL_ODDRST_SHIFT (1U) @@ -12098,54 +21462,77 @@ typedef struct { #define USB_CTL_JSTATE_MASK (0x80U) #define USB_CTL_JSTATE_SHIFT (7U) #define USB_CTL_JSTATE(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_JSTATE_SHIFT)) & USB_CTL_JSTATE_MASK) +/*! @} */ /*! @name ADDR - Address register */ +/*! @{ */ #define USB_ADDR_ADDR_MASK (0x7FU) #define USB_ADDR_ADDR_SHIFT (0U) #define USB_ADDR_ADDR(x) (((uint8_t)(((uint8_t)(x)) << USB_ADDR_ADDR_SHIFT)) & USB_ADDR_ADDR_MASK) #define USB_ADDR_LSEN_MASK (0x80U) #define USB_ADDR_LSEN_SHIFT (7U) #define USB_ADDR_LSEN(x) (((uint8_t)(((uint8_t)(x)) << USB_ADDR_LSEN_SHIFT)) & USB_ADDR_LSEN_MASK) +/*! @} */ /*! @name BDTPAGE1 - BDT Page register 1 */ +/*! @{ */ #define USB_BDTPAGE1_BDTBA_MASK (0xFEU) #define USB_BDTPAGE1_BDTBA_SHIFT (1U) #define USB_BDTPAGE1_BDTBA(x) (((uint8_t)(((uint8_t)(x)) << USB_BDTPAGE1_BDTBA_SHIFT)) & USB_BDTPAGE1_BDTBA_MASK) +/*! @} */ /*! @name FRMNUML - Frame Number register Low */ +/*! @{ */ #define USB_FRMNUML_FRM_MASK (0xFFU) #define USB_FRMNUML_FRM_SHIFT (0U) #define USB_FRMNUML_FRM(x) (((uint8_t)(((uint8_t)(x)) << USB_FRMNUML_FRM_SHIFT)) & USB_FRMNUML_FRM_MASK) +/*! @} */ /*! @name FRMNUMH - Frame Number register High */ +/*! @{ */ #define USB_FRMNUMH_FRM_MASK (0x7U) #define USB_FRMNUMH_FRM_SHIFT (0U) #define USB_FRMNUMH_FRM(x) (((uint8_t)(((uint8_t)(x)) << USB_FRMNUMH_FRM_SHIFT)) & USB_FRMNUMH_FRM_MASK) +/*! @} */ /*! @name TOKEN - Token register */ +/*! @{ */ #define USB_TOKEN_TOKENENDPT_MASK (0xFU) #define USB_TOKEN_TOKENENDPT_SHIFT (0U) #define USB_TOKEN_TOKENENDPT(x) (((uint8_t)(((uint8_t)(x)) << USB_TOKEN_TOKENENDPT_SHIFT)) & USB_TOKEN_TOKENENDPT_MASK) #define USB_TOKEN_TOKENPID_MASK (0xF0U) #define USB_TOKEN_TOKENPID_SHIFT (4U) +/*! TOKENPID + * 0b0001..OUT Token. USB Module performs an OUT (TX) transaction. + * 0b1001..IN Token. USB Module performs an In (RX) transaction. + * 0b1101..SETUP Token. USB Module performs a SETUP (TX) transaction + */ #define USB_TOKEN_TOKENPID(x) (((uint8_t)(((uint8_t)(x)) << USB_TOKEN_TOKENPID_SHIFT)) & USB_TOKEN_TOKENPID_MASK) +/*! @} */ /*! @name SOFTHLD - SOF Threshold register */ +/*! @{ */ #define USB_SOFTHLD_CNT_MASK (0xFFU) #define USB_SOFTHLD_CNT_SHIFT (0U) #define USB_SOFTHLD_CNT(x) (((uint8_t)(((uint8_t)(x)) << USB_SOFTHLD_CNT_SHIFT)) & USB_SOFTHLD_CNT_MASK) +/*! @} */ /*! @name BDTPAGE2 - BDT Page Register 2 */ +/*! @{ */ #define USB_BDTPAGE2_BDTBA_MASK (0xFFU) #define USB_BDTPAGE2_BDTBA_SHIFT (0U) #define USB_BDTPAGE2_BDTBA(x) (((uint8_t)(((uint8_t)(x)) << USB_BDTPAGE2_BDTBA_SHIFT)) & USB_BDTPAGE2_BDTBA_MASK) +/*! @} */ /*! @name BDTPAGE3 - BDT Page Register 3 */ +/*! @{ */ #define USB_BDTPAGE3_BDTBA_MASK (0xFFU) #define USB_BDTPAGE3_BDTBA_SHIFT (0U) #define USB_BDTPAGE3_BDTBA(x) (((uint8_t)(((uint8_t)(x)) << USB_BDTPAGE3_BDTBA_SHIFT)) & USB_BDTPAGE3_BDTBA_MASK) +/*! @} */ /*! @name ENDPT - Endpoint Control register */ +/*! @{ */ #define USB_ENDPT_EPHSHK_MASK (0x1U) #define USB_ENDPT_EPHSHK_SHIFT (0U) #define USB_ENDPT_EPHSHK(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPHSHK_SHIFT)) & USB_ENDPT_EPHSHK_MASK) @@ -12167,79 +21554,160 @@ typedef struct { #define USB_ENDPT_HOSTWOHUB_MASK (0x80U) #define USB_ENDPT_HOSTWOHUB_SHIFT (7U) #define USB_ENDPT_HOSTWOHUB(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_HOSTWOHUB_SHIFT)) & USB_ENDPT_HOSTWOHUB_MASK) +/*! @} */ /* The count of USB_ENDPT */ #define USB_ENDPT_COUNT (16U) /*! @name USBCTRL - USB Control register */ +/*! @{ */ #define USB_USBCTRL_PDE_MASK (0x40U) #define USB_USBCTRL_PDE_SHIFT (6U) +/*! PDE + * 0b0..Weak pulldowns are disabled on D+ and D-. + * 0b1..Weak pulldowns are enabled on D+ and D-. + */ #define USB_USBCTRL_PDE(x) (((uint8_t)(((uint8_t)(x)) << USB_USBCTRL_PDE_SHIFT)) & USB_USBCTRL_PDE_MASK) #define USB_USBCTRL_SUSP_MASK (0x80U) #define USB_USBCTRL_SUSP_SHIFT (7U) +/*! SUSP + * 0b0..USB transceiver is not in suspend state. + * 0b1..USB transceiver is in suspend state. + */ #define USB_USBCTRL_SUSP(x) (((uint8_t)(((uint8_t)(x)) << USB_USBCTRL_SUSP_SHIFT)) & USB_USBCTRL_SUSP_MASK) +/*! @} */ /*! @name OBSERVE - USB OTG Observe register */ +/*! @{ */ #define USB_OBSERVE_DMPD_MASK (0x10U) #define USB_OBSERVE_DMPD_SHIFT (4U) +/*! DMPD + * 0b0..D- pulldown disabled. + * 0b1..D- pulldown enabled. + */ #define USB_OBSERVE_DMPD(x) (((uint8_t)(((uint8_t)(x)) << USB_OBSERVE_DMPD_SHIFT)) & USB_OBSERVE_DMPD_MASK) #define USB_OBSERVE_DPPD_MASK (0x40U) #define USB_OBSERVE_DPPD_SHIFT (6U) +/*! DPPD + * 0b0..D+ pulldown disabled. + * 0b1..D+ pulldown enabled. + */ #define USB_OBSERVE_DPPD(x) (((uint8_t)(((uint8_t)(x)) << USB_OBSERVE_DPPD_SHIFT)) & USB_OBSERVE_DPPD_MASK) #define USB_OBSERVE_DPPU_MASK (0x80U) #define USB_OBSERVE_DPPU_SHIFT (7U) +/*! DPPU + * 0b0..D+ pullup disabled. + * 0b1..D+ pullup enabled. + */ #define USB_OBSERVE_DPPU(x) (((uint8_t)(((uint8_t)(x)) << USB_OBSERVE_DPPU_SHIFT)) & USB_OBSERVE_DPPU_MASK) +/*! @} */ /*! @name CONTROL - USB OTG Control register */ +/*! @{ */ #define USB_CONTROL_DPPULLUPNONOTG_MASK (0x10U) #define USB_CONTROL_DPPULLUPNONOTG_SHIFT (4U) +/*! DPPULLUPNONOTG + * 0b0..DP Pullup in non-OTG device mode is not enabled. + * 0b1..DP Pullup in non-OTG device mode is enabled. + */ #define USB_CONTROL_DPPULLUPNONOTG(x) (((uint8_t)(((uint8_t)(x)) << USB_CONTROL_DPPULLUPNONOTG_SHIFT)) & USB_CONTROL_DPPULLUPNONOTG_MASK) +/*! @} */ /*! @name USBTRC0 - USB Transceiver Control register 0 */ +/*! @{ */ #define USB_USBTRC0_USB_RESUME_INT_MASK (0x1U) #define USB_USBTRC0_USB_RESUME_INT_SHIFT (0U) +/*! USB_RESUME_INT - USB Asynchronous Interrupt + * 0b0..No interrupt was generated. + * 0b1..Interrupt was generated because of the USB asynchronous interrupt. + */ #define USB_USBTRC0_USB_RESUME_INT(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USB_RESUME_INT_SHIFT)) & USB_USBTRC0_USB_RESUME_INT_MASK) #define USB_USBTRC0_SYNC_DET_MASK (0x2U) #define USB_USBTRC0_SYNC_DET_SHIFT (1U) +/*! SYNC_DET - Synchronous USB Interrupt Detect + * 0b0..Synchronous interrupt has not been detected. + * 0b1..Synchronous interrupt has been detected. + */ #define USB_USBTRC0_SYNC_DET(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_SYNC_DET_SHIFT)) & USB_USBTRC0_SYNC_DET_MASK) #define USB_USBTRC0_USB_CLK_RECOVERY_INT_MASK (0x4U) #define USB_USBTRC0_USB_CLK_RECOVERY_INT_SHIFT (2U) #define USB_USBTRC0_USB_CLK_RECOVERY_INT(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USB_CLK_RECOVERY_INT_SHIFT)) & USB_USBTRC0_USB_CLK_RECOVERY_INT_MASK) #define USB_USBTRC0_USBRESMEN_MASK (0x20U) #define USB_USBTRC0_USBRESMEN_SHIFT (5U) +/*! USBRESMEN - Asynchronous Resume Interrupt Enable + * 0b0..USB asynchronous wakeup from suspend mode disabled. + * 0b1..USB asynchronous wakeup from suspend mode enabled. The asynchronous resume interrupt differs from the synchronous resume interrupt in that it asynchronously detects K-state using the unfiltered state of the D+ and D- pins. This interrupt should only be enabled when the Transceiver is suspended. + */ #define USB_USBTRC0_USBRESMEN(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USBRESMEN_SHIFT)) & USB_USBTRC0_USBRESMEN_MASK) #define USB_USBTRC0_USBRESET_MASK (0x80U) #define USB_USBTRC0_USBRESET_SHIFT (7U) +/*! USBRESET - USB Reset + * 0b0..Normal USB module operation. + * 0b1..Returns the USB module to its reset state. + */ #define USB_USBTRC0_USBRESET(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USBRESET_SHIFT)) & USB_USBTRC0_USBRESET_MASK) +/*! @} */ /*! @name USBFRMADJUST - Frame Adjust Register */ +/*! @{ */ #define USB_USBFRMADJUST_ADJ_MASK (0xFFU) #define USB_USBFRMADJUST_ADJ_SHIFT (0U) #define USB_USBFRMADJUST_ADJ(x) (((uint8_t)(((uint8_t)(x)) << USB_USBFRMADJUST_ADJ_SHIFT)) & USB_USBFRMADJUST_ADJ_MASK) +/*! @} */ /*! @name CLK_RECOVER_CTRL - USB Clock recovery control */ +/*! @{ */ #define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_MASK (0x20U) #define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_SHIFT (5U) +/*! RESTART_IFRTRIM_EN - Restart from IFR trim value + * 0b0..Trim fine adjustment always works based on the previous updated trim fine value (default) + * 0b1..Trim fine restarts from the IFR trim value whenever bus_reset/bus_resume is detected or module enable is desasserted + */ #define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_SHIFT)) & USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_MASK) #define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_MASK (0x40U) #define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_SHIFT (6U) +/*! RESET_RESUME_ROUGH_EN - Reset/resume to rough phase enable + * 0b0..Always works in tracking phase after the 1st time rough to track transition (default) + * 0b1..Go back to rough stage whenever bus reset or bus resume occurs + */ #define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_SHIFT)) & USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_MASK) #define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_MASK (0x80U) #define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_SHIFT (7U) +/*! CLOCK_RECOVER_EN - Crystal-less USB enable + * 0b0..Disable clock recovery block (default) + * 0b1..Enable clock recovery block + */ #define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_SHIFT)) & USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_MASK) +/*! @} */ /*! @name CLK_RECOVER_IRC_EN - IRC48M oscillator enable register */ +/*! @{ */ #define USB_CLK_RECOVER_IRC_EN_REG_EN_MASK (0x1U) #define USB_CLK_RECOVER_IRC_EN_REG_EN_SHIFT (0U) +/*! REG_EN - IRC48M regulator enable + * 0b0..IRC48M local regulator is disabled + * 0b1..IRC48M local regulator is enabled (default) + */ #define USB_CLK_RECOVER_IRC_EN_REG_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_IRC_EN_REG_EN_SHIFT)) & USB_CLK_RECOVER_IRC_EN_REG_EN_MASK) #define USB_CLK_RECOVER_IRC_EN_IRC_EN_MASK (0x2U) #define USB_CLK_RECOVER_IRC_EN_IRC_EN_SHIFT (1U) +/*! IRC_EN - IRC48M enable + * 0b0..Disable the IRC48M module (default) + * 0b1..Enable the IRC48M module + */ #define USB_CLK_RECOVER_IRC_EN_IRC_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_IRC_EN_IRC_EN_SHIFT)) & USB_CLK_RECOVER_IRC_EN_IRC_EN_MASK) +/*! @} */ /*! @name CLK_RECOVER_INT_STATUS - Clock recovery separated interrupt status */ +/*! @{ */ #define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_MASK (0x10U) #define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_SHIFT (4U) +/*! OVF_ERROR + * 0b0..No interrupt is reported + * 0b1..Unmasked interrupt has been generated + */ #define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_SHIFT)) & USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_MASK) +/*! @} */ /*! @@ -12297,81 +21765,147 @@ typedef struct { */ /*! @name CONTROL - Control register */ +/*! @{ */ #define USBDCD_CONTROL_IACK_MASK (0x1U) #define USBDCD_CONTROL_IACK_SHIFT (0U) +/*! IACK - Interrupt Acknowledge + * 0b0..Do not clear the interrupt. + * 0b1..Clear the IF bit (interrupt flag). + */ #define USBDCD_CONTROL_IACK(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_CONTROL_IACK_SHIFT)) & USBDCD_CONTROL_IACK_MASK) #define USBDCD_CONTROL_IF_MASK (0x100U) #define USBDCD_CONTROL_IF_SHIFT (8U) +/*! IF - Interrupt Flag + * 0b0..No interrupt is pending. + * 0b1..An interrupt is pending. + */ #define USBDCD_CONTROL_IF(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_CONTROL_IF_SHIFT)) & USBDCD_CONTROL_IF_MASK) #define USBDCD_CONTROL_IE_MASK (0x10000U) #define USBDCD_CONTROL_IE_SHIFT (16U) +/*! IE - Interrupt Enable + * 0b0..Disable interrupts to the system. + * 0b1..Enable interrupts to the system. + */ #define USBDCD_CONTROL_IE(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_CONTROL_IE_SHIFT)) & USBDCD_CONTROL_IE_MASK) #define USBDCD_CONTROL_BC12_MASK (0x20000U) #define USBDCD_CONTROL_BC12_SHIFT (17U) +/*! BC12 + * 0b0..Compatible with BC1.1 (default) + * 0b1..Compatible with BC1.2 + */ #define USBDCD_CONTROL_BC12(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_CONTROL_BC12_SHIFT)) & USBDCD_CONTROL_BC12_MASK) #define USBDCD_CONTROL_START_MASK (0x1000000U) #define USBDCD_CONTROL_START_SHIFT (24U) +/*! START - Start Change Detection Sequence + * 0b0..Do not start the sequence. Writes of this value have no effect. + * 0b1..Initiate the charger detection sequence. If the sequence is already running, writes of this value have no effect. + */ #define USBDCD_CONTROL_START(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_CONTROL_START_SHIFT)) & USBDCD_CONTROL_START_MASK) #define USBDCD_CONTROL_SR_MASK (0x2000000U) #define USBDCD_CONTROL_SR_SHIFT (25U) +/*! SR - Software Reset + * 0b0..Do not perform a software reset. + * 0b1..Perform a software reset. + */ #define USBDCD_CONTROL_SR(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_CONTROL_SR_SHIFT)) & USBDCD_CONTROL_SR_MASK) +/*! @} */ /*! @name CLOCK - Clock register */ +/*! @{ */ #define USBDCD_CLOCK_CLOCK_UNIT_MASK (0x1U) #define USBDCD_CLOCK_CLOCK_UNIT_SHIFT (0U) +/*! CLOCK_UNIT - Unit of Measurement Encoding for Clock Speed + * 0b0..kHz Speed (between 1 kHz and 1023 kHz) + * 0b1..MHz Speed (between 1 MHz and 1023 MHz) + */ #define USBDCD_CLOCK_CLOCK_UNIT(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_CLOCK_CLOCK_UNIT_SHIFT)) & USBDCD_CLOCK_CLOCK_UNIT_MASK) #define USBDCD_CLOCK_CLOCK_SPEED_MASK (0xFFCU) #define USBDCD_CLOCK_CLOCK_SPEED_SHIFT (2U) #define USBDCD_CLOCK_CLOCK_SPEED(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_CLOCK_CLOCK_SPEED_SHIFT)) & USBDCD_CLOCK_CLOCK_SPEED_MASK) +/*! @} */ /*! @name STATUS - Status register */ +/*! @{ */ #define USBDCD_STATUS_SEQ_RES_MASK (0x30000U) #define USBDCD_STATUS_SEQ_RES_SHIFT (16U) +/*! SEQ_RES - Charger Detection Sequence Results + * 0b00..No results to report. + * 0b01..Attached to a standard host. Must comply with USB 2.0 by drawing only 2.5 mA (max) until connected. + * 0b10..Attached to a charging port. The exact meaning depends on bit 18: 0: Attached to either a charging host or a dedicated charger. The charger type detection has not completed. 1: Attached to a charging host. The charger type detection has completed. + * 0b11..Attached to a dedicated charger. + */ #define USBDCD_STATUS_SEQ_RES(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_STATUS_SEQ_RES_SHIFT)) & USBDCD_STATUS_SEQ_RES_MASK) #define USBDCD_STATUS_SEQ_STAT_MASK (0xC0000U) #define USBDCD_STATUS_SEQ_STAT_SHIFT (18U) +/*! SEQ_STAT - Charger Detection Sequence Status + * 0b00..The module is either not enabled, or the module is enabled but the data pins have not yet been detected. + * 0b01..Data pin contact detection is complete. + * 0b10..Charging port detection is complete. + * 0b11..Charger type detection is complete. + */ #define USBDCD_STATUS_SEQ_STAT(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_STATUS_SEQ_STAT_SHIFT)) & USBDCD_STATUS_SEQ_STAT_MASK) #define USBDCD_STATUS_ERR_MASK (0x100000U) #define USBDCD_STATUS_ERR_SHIFT (20U) +/*! ERR - Error Flag + * 0b0..No sequence errors. + * 0b1..Error in the detection sequence. See the SEQ_STAT field to determine the phase in which the error occurred. + */ #define USBDCD_STATUS_ERR(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_STATUS_ERR_SHIFT)) & USBDCD_STATUS_ERR_MASK) #define USBDCD_STATUS_TO_MASK (0x200000U) #define USBDCD_STATUS_TO_SHIFT (21U) +/*! TO - Timeout Flag + * 0b0..The detection sequence has not been running for over 1 s. + * 0b1..It has been over 1 s since the data pin contact was detected and debounced. + */ #define USBDCD_STATUS_TO(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_STATUS_TO_SHIFT)) & USBDCD_STATUS_TO_MASK) #define USBDCD_STATUS_ACTIVE_MASK (0x400000U) #define USBDCD_STATUS_ACTIVE_SHIFT (22U) +/*! ACTIVE - Active Status Indicator + * 0b0..The sequence is not running. + * 0b1..The sequence is running. + */ #define USBDCD_STATUS_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_STATUS_ACTIVE_SHIFT)) & USBDCD_STATUS_ACTIVE_MASK) +/*! @} */ /*! @name TIMER0 - TIMER0 register */ +/*! @{ */ #define USBDCD_TIMER0_TUNITCON_MASK (0xFFFU) #define USBDCD_TIMER0_TUNITCON_SHIFT (0U) #define USBDCD_TIMER0_TUNITCON(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER0_TUNITCON_SHIFT)) & USBDCD_TIMER0_TUNITCON_MASK) #define USBDCD_TIMER0_TSEQ_INIT_MASK (0x3FF0000U) #define USBDCD_TIMER0_TSEQ_INIT_SHIFT (16U) #define USBDCD_TIMER0_TSEQ_INIT(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER0_TSEQ_INIT_SHIFT)) & USBDCD_TIMER0_TSEQ_INIT_MASK) +/*! @} */ /*! @name TIMER1 - TIMER1 register */ +/*! @{ */ #define USBDCD_TIMER1_TVDPSRC_ON_MASK (0x3FFU) #define USBDCD_TIMER1_TVDPSRC_ON_SHIFT (0U) #define USBDCD_TIMER1_TVDPSRC_ON(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER1_TVDPSRC_ON_SHIFT)) & USBDCD_TIMER1_TVDPSRC_ON_MASK) #define USBDCD_TIMER1_TDCD_DBNC_MASK (0x3FF0000U) #define USBDCD_TIMER1_TDCD_DBNC_SHIFT (16U) #define USBDCD_TIMER1_TDCD_DBNC(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER1_TDCD_DBNC_SHIFT)) & USBDCD_TIMER1_TDCD_DBNC_MASK) +/*! @} */ /*! @name TIMER2_BC11 - TIMER2_BC11 register */ +/*! @{ */ #define USBDCD_TIMER2_BC11_CHECK_DM_MASK (0xFU) #define USBDCD_TIMER2_BC11_CHECK_DM_SHIFT (0U) #define USBDCD_TIMER2_BC11_CHECK_DM(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER2_BC11_CHECK_DM_SHIFT)) & USBDCD_TIMER2_BC11_CHECK_DM_MASK) #define USBDCD_TIMER2_BC11_TVDPSRC_CON_MASK (0x3FF0000U) #define USBDCD_TIMER2_BC11_TVDPSRC_CON_SHIFT (16U) #define USBDCD_TIMER2_BC11_TVDPSRC_CON(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER2_BC11_TVDPSRC_CON_SHIFT)) & USBDCD_TIMER2_BC11_TVDPSRC_CON_MASK) +/*! @} */ /*! @name TIMER2_BC12 - TIMER2_BC12 register */ +/*! @{ */ #define USBDCD_TIMER2_BC12_TVDMSRC_ON_MASK (0x3FFU) #define USBDCD_TIMER2_BC12_TVDMSRC_ON_SHIFT (0U) #define USBDCD_TIMER2_BC12_TVDMSRC_ON(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER2_BC12_TVDMSRC_ON_SHIFT)) & USBDCD_TIMER2_BC12_TVDMSRC_ON_MASK) #define USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD_MASK (0x3FF0000U) #define USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD_SHIFT (16U) #define USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD_SHIFT)) & USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD_MASK) +/*! @} */ /*! @@ -12421,29 +21955,63 @@ typedef struct { */ /*! @name TRM - VREF Trim Register */ +/*! @{ */ #define VREF_TRM_TRIM_MASK (0x3FU) #define VREF_TRM_TRIM_SHIFT (0U) +/*! TRIM - Trim bits + * 0b000000..Min + * 0b111111..Max + */ #define VREF_TRM_TRIM(x) (((uint8_t)(((uint8_t)(x)) << VREF_TRM_TRIM_SHIFT)) & VREF_TRM_TRIM_MASK) #define VREF_TRM_CHOPEN_MASK (0x40U) #define VREF_TRM_CHOPEN_SHIFT (6U) +/*! CHOPEN - Chop oscillator enable. When set, internal chopping operation is enabled and the internal analog offset will be minimized. + * 0b0..Chop oscillator is disabled. + * 0b1..Chop oscillator is enabled. + */ #define VREF_TRM_CHOPEN(x) (((uint8_t)(((uint8_t)(x)) << VREF_TRM_CHOPEN_SHIFT)) & VREF_TRM_CHOPEN_MASK) +/*! @} */ /*! @name SC - VREF Status and Control Register */ +/*! @{ */ #define VREF_SC_MODE_LV_MASK (0x3U) #define VREF_SC_MODE_LV_SHIFT (0U) +/*! MODE_LV - Buffer Mode selection + * 0b00..Bandgap on only, for stabilization and startup + * 0b01..High power buffer mode enabled + * 0b10..Low-power buffer mode enabled + * 0b11..Reserved + */ #define VREF_SC_MODE_LV(x) (((uint8_t)(((uint8_t)(x)) << VREF_SC_MODE_LV_SHIFT)) & VREF_SC_MODE_LV_MASK) #define VREF_SC_VREFST_MASK (0x4U) #define VREF_SC_VREFST_SHIFT (2U) +/*! VREFST - Internal Voltage Reference stable + * 0b0..The module is disabled or not stable. + * 0b1..The module is stable. + */ #define VREF_SC_VREFST(x) (((uint8_t)(((uint8_t)(x)) << VREF_SC_VREFST_SHIFT)) & VREF_SC_VREFST_MASK) #define VREF_SC_ICOMPEN_MASK (0x20U) #define VREF_SC_ICOMPEN_SHIFT (5U) +/*! ICOMPEN - Second order curvature compensation enable + * 0b0..Disabled + * 0b1..Enabled + */ #define VREF_SC_ICOMPEN(x) (((uint8_t)(((uint8_t)(x)) << VREF_SC_ICOMPEN_SHIFT)) & VREF_SC_ICOMPEN_MASK) #define VREF_SC_REGEN_MASK (0x40U) #define VREF_SC_REGEN_SHIFT (6U) +/*! REGEN - Regulator enable + * 0b0..Internal 1.75 V regulator is disabled. + * 0b1..Internal 1.75 V regulator is enabled. + */ #define VREF_SC_REGEN(x) (((uint8_t)(((uint8_t)(x)) << VREF_SC_REGEN_SHIFT)) & VREF_SC_REGEN_MASK) #define VREF_SC_VREFEN_MASK (0x80U) #define VREF_SC_VREFEN_SHIFT (7U) +/*! VREFEN - Internal Voltage Reference enable + * 0b0..The module is disabled. + * 0b1..The module is enabled. + */ #define VREF_SC_VREFEN(x) (((uint8_t)(((uint8_t)(x)) << VREF_SC_VREFEN_SHIFT)) & VREF_SC_VREFEN_MASK) +/*! @} */ /*! @@ -12501,97 +22069,167 @@ typedef struct { */ /*! @name STCTRLH - Watchdog Status and Control Register High */ +/*! @{ */ #define WDOG_STCTRLH_WDOGEN_MASK (0x1U) #define WDOG_STCTRLH_WDOGEN_SHIFT (0U) +/*! WDOGEN + * 0b0..WDOG is disabled. + * 0b1..WDOG is enabled. + */ #define WDOG_STCTRLH_WDOGEN(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_WDOGEN_SHIFT)) & WDOG_STCTRLH_WDOGEN_MASK) #define WDOG_STCTRLH_CLKSRC_MASK (0x2U) #define WDOG_STCTRLH_CLKSRC_SHIFT (1U) +/*! CLKSRC + * 0b0..WDOG clock sourced from LPO . + * 0b1..WDOG clock sourced from alternate clock source. + */ #define WDOG_STCTRLH_CLKSRC(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_CLKSRC_SHIFT)) & WDOG_STCTRLH_CLKSRC_MASK) #define WDOG_STCTRLH_IRQRSTEN_MASK (0x4U) #define WDOG_STCTRLH_IRQRSTEN_SHIFT (2U) +/*! IRQRSTEN + * 0b0..WDOG time-out generates reset only. + * 0b1..WDOG time-out initially generates an interrupt. After WCT, it generates a reset. + */ #define WDOG_STCTRLH_IRQRSTEN(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_IRQRSTEN_SHIFT)) & WDOG_STCTRLH_IRQRSTEN_MASK) #define WDOG_STCTRLH_WINEN_MASK (0x8U) #define WDOG_STCTRLH_WINEN_SHIFT (3U) +/*! WINEN + * 0b0..Windowing mode is disabled. + * 0b1..Windowing mode is enabled. + */ #define WDOG_STCTRLH_WINEN(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_WINEN_SHIFT)) & WDOG_STCTRLH_WINEN_MASK) #define WDOG_STCTRLH_ALLOWUPDATE_MASK (0x10U) #define WDOG_STCTRLH_ALLOWUPDATE_SHIFT (4U) +/*! ALLOWUPDATE + * 0b0..No further updates allowed to WDOG write-once registers. + * 0b1..WDOG write-once registers can be unlocked for updating. + */ #define WDOG_STCTRLH_ALLOWUPDATE(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_ALLOWUPDATE_SHIFT)) & WDOG_STCTRLH_ALLOWUPDATE_MASK) #define WDOG_STCTRLH_DBGEN_MASK (0x20U) #define WDOG_STCTRLH_DBGEN_SHIFT (5U) +/*! DBGEN + * 0b0..WDOG is disabled in CPU Debug mode. + * 0b1..WDOG is enabled in CPU Debug mode. + */ #define WDOG_STCTRLH_DBGEN(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_DBGEN_SHIFT)) & WDOG_STCTRLH_DBGEN_MASK) #define WDOG_STCTRLH_STOPEN_MASK (0x40U) #define WDOG_STCTRLH_STOPEN_SHIFT (6U) +/*! STOPEN + * 0b0..WDOG is disabled in CPU Stop mode. + * 0b1..WDOG is enabled in CPU Stop mode. + */ #define WDOG_STCTRLH_STOPEN(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_STOPEN_SHIFT)) & WDOG_STCTRLH_STOPEN_MASK) #define WDOG_STCTRLH_WAITEN_MASK (0x80U) #define WDOG_STCTRLH_WAITEN_SHIFT (7U) +/*! WAITEN + * 0b0..WDOG is disabled in CPU Wait mode. + * 0b1..WDOG is enabled in CPU Wait mode. + */ #define WDOG_STCTRLH_WAITEN(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_WAITEN_SHIFT)) & WDOG_STCTRLH_WAITEN_MASK) #define WDOG_STCTRLH_TESTWDOG_MASK (0x400U) #define WDOG_STCTRLH_TESTWDOG_SHIFT (10U) #define WDOG_STCTRLH_TESTWDOG(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_TESTWDOG_SHIFT)) & WDOG_STCTRLH_TESTWDOG_MASK) #define WDOG_STCTRLH_TESTSEL_MASK (0x800U) #define WDOG_STCTRLH_TESTSEL_SHIFT (11U) +/*! TESTSEL + * 0b0..Quick test. The timer runs in normal operation. You can load a small time-out value to do a quick test. + * 0b1..Byte test. Puts the timer in the byte test mode where individual bytes of the timer are enabled for operation and are compared for time-out against the corresponding byte of the programmed time-out value. Select the byte through BYTESEL[1:0] for testing. + */ #define WDOG_STCTRLH_TESTSEL(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_TESTSEL_SHIFT)) & WDOG_STCTRLH_TESTSEL_MASK) #define WDOG_STCTRLH_BYTESEL_MASK (0x3000U) #define WDOG_STCTRLH_BYTESEL_SHIFT (12U) +/*! BYTESEL + * 0b00..Byte 0 selected + * 0b01..Byte 1 selected + * 0b10..Byte 2 selected + * 0b11..Byte 3 selected + */ #define WDOG_STCTRLH_BYTESEL(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_BYTESEL_SHIFT)) & WDOG_STCTRLH_BYTESEL_MASK) #define WDOG_STCTRLH_DISTESTWDOG_MASK (0x4000U) #define WDOG_STCTRLH_DISTESTWDOG_SHIFT (14U) +/*! DISTESTWDOG + * 0b0..WDOG functional test mode is not disabled. + * 0b1..WDOG functional test mode is disabled permanently until reset. + */ #define WDOG_STCTRLH_DISTESTWDOG(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_DISTESTWDOG_SHIFT)) & WDOG_STCTRLH_DISTESTWDOG_MASK) +/*! @} */ /*! @name STCTRLL - Watchdog Status and Control Register Low */ +/*! @{ */ #define WDOG_STCTRLL_INTFLG_MASK (0x8000U) #define WDOG_STCTRLL_INTFLG_SHIFT (15U) #define WDOG_STCTRLL_INTFLG(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLL_INTFLG_SHIFT)) & WDOG_STCTRLL_INTFLG_MASK) +/*! @} */ /*! @name TOVALH - Watchdog Time-out Value Register High */ +/*! @{ */ #define WDOG_TOVALH_TOVALHIGH_MASK (0xFFFFU) #define WDOG_TOVALH_TOVALHIGH_SHIFT (0U) #define WDOG_TOVALH_TOVALHIGH(x) (((uint16_t)(((uint16_t)(x)) << WDOG_TOVALH_TOVALHIGH_SHIFT)) & WDOG_TOVALH_TOVALHIGH_MASK) +/*! @} */ /*! @name TOVALL - Watchdog Time-out Value Register Low */ +/*! @{ */ #define WDOG_TOVALL_TOVALLOW_MASK (0xFFFFU) #define WDOG_TOVALL_TOVALLOW_SHIFT (0U) #define WDOG_TOVALL_TOVALLOW(x) (((uint16_t)(((uint16_t)(x)) << WDOG_TOVALL_TOVALLOW_SHIFT)) & WDOG_TOVALL_TOVALLOW_MASK) +/*! @} */ /*! @name WINH - Watchdog Window Register High */ +/*! @{ */ #define WDOG_WINH_WINHIGH_MASK (0xFFFFU) #define WDOG_WINH_WINHIGH_SHIFT (0U) #define WDOG_WINH_WINHIGH(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WINH_WINHIGH_SHIFT)) & WDOG_WINH_WINHIGH_MASK) +/*! @} */ /*! @name WINL - Watchdog Window Register Low */ +/*! @{ */ #define WDOG_WINL_WINLOW_MASK (0xFFFFU) #define WDOG_WINL_WINLOW_SHIFT (0U) #define WDOG_WINL_WINLOW(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WINL_WINLOW_SHIFT)) & WDOG_WINL_WINLOW_MASK) +/*! @} */ /*! @name REFRESH - Watchdog Refresh register */ +/*! @{ */ #define WDOG_REFRESH_WDOGREFRESH_MASK (0xFFFFU) #define WDOG_REFRESH_WDOGREFRESH_SHIFT (0U) #define WDOG_REFRESH_WDOGREFRESH(x) (((uint16_t)(((uint16_t)(x)) << WDOG_REFRESH_WDOGREFRESH_SHIFT)) & WDOG_REFRESH_WDOGREFRESH_MASK) +/*! @} */ /*! @name UNLOCK - Watchdog Unlock register */ +/*! @{ */ #define WDOG_UNLOCK_WDOGUNLOCK_MASK (0xFFFFU) #define WDOG_UNLOCK_WDOGUNLOCK_SHIFT (0U) #define WDOG_UNLOCK_WDOGUNLOCK(x) (((uint16_t)(((uint16_t)(x)) << WDOG_UNLOCK_WDOGUNLOCK_SHIFT)) & WDOG_UNLOCK_WDOGUNLOCK_MASK) +/*! @} */ /*! @name TMROUTH - Watchdog Timer Output Register High */ +/*! @{ */ #define WDOG_TMROUTH_TIMEROUTHIGH_MASK (0xFFFFU) #define WDOG_TMROUTH_TIMEROUTHIGH_SHIFT (0U) #define WDOG_TMROUTH_TIMEROUTHIGH(x) (((uint16_t)(((uint16_t)(x)) << WDOG_TMROUTH_TIMEROUTHIGH_SHIFT)) & WDOG_TMROUTH_TIMEROUTHIGH_MASK) +/*! @} */ /*! @name TMROUTL - Watchdog Timer Output Register Low */ +/*! @{ */ #define WDOG_TMROUTL_TIMEROUTLOW_MASK (0xFFFFU) #define WDOG_TMROUTL_TIMEROUTLOW_SHIFT (0U) #define WDOG_TMROUTL_TIMEROUTLOW(x) (((uint16_t)(((uint16_t)(x)) << WDOG_TMROUTL_TIMEROUTLOW_SHIFT)) & WDOG_TMROUTL_TIMEROUTLOW_MASK) +/*! @} */ /*! @name RSTCNT - Watchdog Reset Count register */ +/*! @{ */ #define WDOG_RSTCNT_RSTCNT_MASK (0xFFFFU) #define WDOG_RSTCNT_RSTCNT_SHIFT (0U) #define WDOG_RSTCNT_RSTCNT(x) (((uint16_t)(((uint16_t)(x)) << WDOG_RSTCNT_RSTCNT_SHIFT)) & WDOG_RSTCNT_RSTCNT_MASK) +/*! @} */ /*! @name PRESC - Watchdog Prescaler register */ +/*! @{ */ #define WDOG_PRESC_PRESCVAL_MASK (0x700U) #define WDOG_PRESC_PRESCVAL_SHIFT (8U) #define WDOG_PRESC_PRESCVAL(x) (((uint16_t)(((uint16_t)(x)) << WDOG_PRESC_PRESCVAL_SHIFT)) & WDOG_PRESC_PRESCVAL_MASK) +/*! @} */ /*! @@ -12621,7 +22259,11 @@ typedef struct { */ #if defined(__ARMCC_VERSION) - #pragma pop + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop + #else + #pragma pop + #endif #elif defined(__CWCC__) #pragma pop #elif defined(__GNUC__) diff --git a/ext/hal/nxp/mcux/devices/MK64F12/MK64F12.xml b/ext/hal/nxp/mcux/devices/MK64F12/MK64F12.xml index 312e343c2b1..6f326c61236 100644 --- a/ext/hal/nxp/mcux/devices/MK64F12/MK64F12.xml +++ b/ext/hal/nxp/mcux/devices/MK64F12/MK64F12.xml @@ -6,7 +6,8 @@ Kinetis_K 1.6 MK64F12 NXP Microcontroller - Redistribution and use in source and binary forms, with or without modification,\nare permitted provided that the following conditions are met:\n o Redistributions of source code must retain the above copyright notice, this list\n of conditions and the following disclaimer.\n o Redistributions in binary form must reproduce the above copyright notice, this\n list of conditions and the following disclaimer in the documentation and/or\n other materials provided with the distribution.\n o Neither the name of the copyright holder nor the names of its\n contributors may be used to endorse or promote products derived from this\n software without specific prior written permission.\n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND\n ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\n WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR\n ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON\n ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\n SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + Copyright 2016-2018 NXP + SPDX-License-Identifier: BSD-3-Clause CM4 r0p1 @@ -24162,10 +24163,599 @@ 0xFFFFFFFF - MG + MG0 Rx Mailboxes Global Mask Bits 0 - 32 + 1 + read-write + + + 0 + The corresponding bit in the filter is "don't care." + #0 + + + 1 + The corresponding bit in the filter is checked. + #1 + + + + + MG1 + Rx Mailboxes Global Mask Bits + 1 + 1 + read-write + + + 0 + The corresponding bit in the filter is "don't care." + #0 + + + 1 + The corresponding bit in the filter is checked. + #1 + + + + + MG2 + Rx Mailboxes Global Mask Bits + 2 + 1 + read-write + + + 0 + The corresponding bit in the filter is "don't care." + #0 + + + 1 + The corresponding bit in the filter is checked. + #1 + + + + + MG3 + Rx Mailboxes Global Mask Bits + 3 + 1 + read-write + + + 0 + The corresponding bit in the filter is "don't care." + #0 + + + 1 + The corresponding bit in the filter is checked. + #1 + + + + + MG4 + Rx Mailboxes Global Mask Bits + 4 + 1 + read-write + + + 0 + The corresponding bit in the filter is "don't care." + #0 + + + 1 + The corresponding bit in the filter is checked. + #1 + + + + + MG5 + Rx Mailboxes Global Mask Bits + 5 + 1 + read-write + + + 0 + The corresponding bit in the filter is "don't care." + #0 + + + 1 + The corresponding bit in the filter is checked. + #1 + + + + + MG6 + Rx Mailboxes Global Mask Bits + 6 + 1 + read-write + + + 0 + The corresponding bit in the filter is "don't care." + #0 + + + 1 + The corresponding bit in the filter is checked. + #1 + + + + + MG7 + Rx Mailboxes Global Mask Bits + 7 + 1 + read-write + + + 0 + The corresponding bit in the filter is "don't care." + #0 + + + 1 + The corresponding bit in the filter is checked. + #1 + + + + + MG8 + Rx Mailboxes Global Mask Bits + 8 + 1 + read-write + + + 0 + The corresponding bit in the filter is "don't care." + #0 + + + 1 + The corresponding bit in the filter is checked. + #1 + + + + + MG9 + Rx Mailboxes Global Mask Bits + 9 + 1 + read-write + + + 0 + The corresponding bit in the filter is "don't care." + #0 + + + 1 + The corresponding bit in the filter is checked. + #1 + + + + + MG10 + Rx Mailboxes Global Mask Bits + 10 + 1 + read-write + + + 0 + The corresponding bit in the filter is "don't care." + #0 + + + 1 + The corresponding bit in the filter is checked. + #1 + + + + + MG11 + Rx Mailboxes Global Mask Bits + 11 + 1 + read-write + + + 0 + The corresponding bit in the filter is "don't care." + #0 + + + 1 + The corresponding bit in the filter is checked. + #1 + + + + + MG12 + Rx Mailboxes Global Mask Bits + 12 + 1 + read-write + + + 0 + The corresponding bit in the filter is "don't care." + #0 + + + 1 + The corresponding bit in the filter is checked. + #1 + + + + + MG13 + Rx Mailboxes Global Mask Bits + 13 + 1 + read-write + + + 0 + The corresponding bit in the filter is "don't care." + #0 + + + 1 + The corresponding bit in the filter is checked. + #1 + + + + + MG14 + Rx Mailboxes Global Mask Bits + 14 + 1 + read-write + + + 0 + The corresponding bit in the filter is "don't care." + #0 + + + 1 + The corresponding bit in the filter is checked. + #1 + + + + + MG15 + Rx Mailboxes Global Mask Bits + 15 + 1 + read-write + + + 0 + The corresponding bit in the filter is "don't care." + #0 + + + 1 + The corresponding bit in the filter is checked. + #1 + + + + + MG16 + Rx Mailboxes Global Mask Bits + 16 + 1 + read-write + + + 0 + The corresponding bit in the filter is "don't care." + #0 + + + 1 + The corresponding bit in the filter is checked. + #1 + + + + + MG17 + Rx Mailboxes Global Mask Bits + 17 + 1 + read-write + + + 0 + The corresponding bit in the filter is "don't care." + #0 + + + 1 + The corresponding bit in the filter is checked. + #1 + + + + + MG18 + Rx Mailboxes Global Mask Bits + 18 + 1 + read-write + + + 0 + The corresponding bit in the filter is "don't care." + #0 + + + 1 + The corresponding bit in the filter is checked. + #1 + + + + + MG19 + Rx Mailboxes Global Mask Bits + 19 + 1 + read-write + + + 0 + The corresponding bit in the filter is "don't care." + #0 + + + 1 + The corresponding bit in the filter is checked. + #1 + + + + + MG20 + Rx Mailboxes Global Mask Bits + 20 + 1 + read-write + + + 0 + The corresponding bit in the filter is "don't care." + #0 + + + 1 + The corresponding bit in the filter is checked. + #1 + + + + + MG21 + Rx Mailboxes Global Mask Bits + 21 + 1 + read-write + + + 0 + The corresponding bit in the filter is "don't care." + #0 + + + 1 + The corresponding bit in the filter is checked. + #1 + + + + + MG22 + Rx Mailboxes Global Mask Bits + 22 + 1 + read-write + + + 0 + The corresponding bit in the filter is "don't care." + #0 + + + 1 + The corresponding bit in the filter is checked. + #1 + + + + + MG23 + Rx Mailboxes Global Mask Bits + 23 + 1 + read-write + + + 0 + The corresponding bit in the filter is "don't care." + #0 + + + 1 + The corresponding bit in the filter is checked. + #1 + + + + + MG24 + Rx Mailboxes Global Mask Bits + 24 + 1 + read-write + + + 0 + The corresponding bit in the filter is "don't care." + #0 + + + 1 + The corresponding bit in the filter is checked. + #1 + + + + + MG25 + Rx Mailboxes Global Mask Bits + 25 + 1 + read-write + + + 0 + The corresponding bit in the filter is "don't care." + #0 + + + 1 + The corresponding bit in the filter is checked. + #1 + + + + + MG26 + Rx Mailboxes Global Mask Bits + 26 + 1 + read-write + + + 0 + The corresponding bit in the filter is "don't care." + #0 + + + 1 + The corresponding bit in the filter is checked. + #1 + + + + + MG27 + Rx Mailboxes Global Mask Bits + 27 + 1 + read-write + + + 0 + The corresponding bit in the filter is "don't care." + #0 + + + 1 + The corresponding bit in the filter is checked. + #1 + + + + + MG28 + Rx Mailboxes Global Mask Bits + 28 + 1 + read-write + + + 0 + The corresponding bit in the filter is "don't care." + #0 + + + 1 + The corresponding bit in the filter is checked. + #1 + + + + + MG29 + Rx Mailboxes Global Mask Bits + 29 + 1 + read-write + + + 0 + The corresponding bit in the filter is "don't care." + #0 + + + 1 + The corresponding bit in the filter is checked. + #1 + + + + + MG30 + Rx Mailboxes Global Mask Bits + 30 + 1 + read-write + + + 0 + The corresponding bit in the filter is "don't care." + #0 + + + 1 + The corresponding bit in the filter is checked. + #1 + + + + + MG31 + Rx Mailboxes Global Mask Bits + 31 + 1 read-write @@ -24192,10 +24782,599 @@ 0xFFFFFFFF - RX14M + RX14M0 Rx Buffer 14 Mask Bits 0 - 32 + 1 + read-write + + + 0 + The corresponding bit in the filter is "don't care." + #0 + + + 1 + The corresponding bit in the filter is checked. + #1 + + + + + RX14M1 + Rx Buffer 14 Mask Bits + 1 + 1 + read-write + + + 0 + The corresponding bit in the filter is "don't care." + #0 + + + 1 + The corresponding bit in the filter is checked. + #1 + + + + + RX14M2 + Rx Buffer 14 Mask Bits + 2 + 1 + read-write + + + 0 + The corresponding bit in the filter is "don't care." + #0 + + + 1 + The corresponding bit in the filter is checked. + #1 + + + + + RX14M3 + Rx Buffer 14 Mask Bits + 3 + 1 + read-write + + + 0 + The corresponding bit in the filter is "don't care." + #0 + + + 1 + The corresponding bit in the filter is checked. + #1 + + + + + RX14M4 + Rx Buffer 14 Mask Bits + 4 + 1 + read-write + + + 0 + The corresponding bit in the filter is "don't care." + #0 + + + 1 + The corresponding bit in the filter is checked. + #1 + + + + + RX14M5 + Rx Buffer 14 Mask Bits + 5 + 1 + read-write + + + 0 + The corresponding bit in the filter is "don't care." + #0 + + + 1 + The corresponding bit in the filter is checked. + #1 + + + + + RX14M6 + Rx Buffer 14 Mask Bits + 6 + 1 + read-write + + + 0 + The corresponding bit in the filter is "don't care." + #0 + + + 1 + The corresponding bit in the filter is checked. + #1 + + + + + RX14M7 + Rx Buffer 14 Mask Bits + 7 + 1 + read-write + + + 0 + The corresponding bit in the filter is "don't care." + #0 + + + 1 + The corresponding bit in the filter is checked. + #1 + + + + + RX14M8 + Rx Buffer 14 Mask Bits + 8 + 1 + read-write + + + 0 + The corresponding bit in the filter is "don't care." + #0 + + + 1 + The corresponding bit in the filter is checked. + #1 + + + + + RX14M9 + Rx Buffer 14 Mask Bits + 9 + 1 + read-write + + + 0 + The corresponding bit in the filter is "don't care." + #0 + + + 1 + The corresponding bit in the filter is checked. + #1 + + + + + RX14M10 + Rx Buffer 14 Mask Bits + 10 + 1 + read-write + + + 0 + The corresponding bit in the filter is "don't care." + #0 + + + 1 + The corresponding bit in the filter is checked. + #1 + + + + + RX14M11 + Rx Buffer 14 Mask Bits + 11 + 1 + read-write + + + 0 + The corresponding bit in the filter is "don't care." + #0 + + + 1 + The corresponding bit in the filter is checked. + #1 + + + + + RX14M12 + Rx Buffer 14 Mask Bits + 12 + 1 + read-write + + + 0 + The corresponding bit in the filter is "don't care." + #0 + + + 1 + The corresponding bit in the filter is checked. + #1 + + + + + RX14M13 + Rx Buffer 14 Mask Bits + 13 + 1 + read-write + + + 0 + The corresponding bit in the filter is "don't care." + #0 + + + 1 + The corresponding bit in the filter is checked. + #1 + + + + + RX14M14 + Rx Buffer 14 Mask Bits + 14 + 1 + read-write + + + 0 + The corresponding bit in the filter is "don't care." + #0 + + + 1 + The corresponding bit in the filter is checked. + #1 + + + + + RX14M15 + Rx Buffer 14 Mask Bits + 15 + 1 + read-write + + + 0 + The corresponding bit in the filter is "don't care." + #0 + + + 1 + The corresponding bit in the filter is checked. + #1 + + + + + RX14M16 + Rx Buffer 14 Mask Bits + 16 + 1 + read-write + + + 0 + The corresponding bit in the filter is "don't care." + #0 + + + 1 + The corresponding bit in the filter is checked. + #1 + + + + + RX14M17 + Rx Buffer 14 Mask Bits + 17 + 1 + read-write + + + 0 + The corresponding bit in the filter is "don't care." + #0 + + + 1 + The corresponding bit in the filter is checked. + #1 + + + + + RX14M18 + Rx Buffer 14 Mask Bits + 18 + 1 + read-write + + + 0 + The corresponding bit in the filter is "don't care." + #0 + + + 1 + The corresponding bit in the filter is checked. + #1 + + + + + RX14M19 + Rx Buffer 14 Mask Bits + 19 + 1 + read-write + + + 0 + The corresponding bit in the filter is "don't care." + #0 + + + 1 + The corresponding bit in the filter is checked. + #1 + + + + + RX14M20 + Rx Buffer 14 Mask Bits + 20 + 1 + read-write + + + 0 + The corresponding bit in the filter is "don't care." + #0 + + + 1 + The corresponding bit in the filter is checked. + #1 + + + + + RX14M21 + Rx Buffer 14 Mask Bits + 21 + 1 + read-write + + + 0 + The corresponding bit in the filter is "don't care." + #0 + + + 1 + The corresponding bit in the filter is checked. + #1 + + + + + RX14M22 + Rx Buffer 14 Mask Bits + 22 + 1 + read-write + + + 0 + The corresponding bit in the filter is "don't care." + #0 + + + 1 + The corresponding bit in the filter is checked. + #1 + + + + + RX14M23 + Rx Buffer 14 Mask Bits + 23 + 1 + read-write + + + 0 + The corresponding bit in the filter is "don't care." + #0 + + + 1 + The corresponding bit in the filter is checked. + #1 + + + + + RX14M24 + Rx Buffer 14 Mask Bits + 24 + 1 + read-write + + + 0 + The corresponding bit in the filter is "don't care." + #0 + + + 1 + The corresponding bit in the filter is checked. + #1 + + + + + RX14M25 + Rx Buffer 14 Mask Bits + 25 + 1 + read-write + + + 0 + The corresponding bit in the filter is "don't care." + #0 + + + 1 + The corresponding bit in the filter is checked. + #1 + + + + + RX14M26 + Rx Buffer 14 Mask Bits + 26 + 1 + read-write + + + 0 + The corresponding bit in the filter is "don't care." + #0 + + + 1 + The corresponding bit in the filter is checked. + #1 + + + + + RX14M27 + Rx Buffer 14 Mask Bits + 27 + 1 + read-write + + + 0 + The corresponding bit in the filter is "don't care." + #0 + + + 1 + The corresponding bit in the filter is checked. + #1 + + + + + RX14M28 + Rx Buffer 14 Mask Bits + 28 + 1 + read-write + + + 0 + The corresponding bit in the filter is "don't care." + #0 + + + 1 + The corresponding bit in the filter is checked. + #1 + + + + + RX14M29 + Rx Buffer 14 Mask Bits + 29 + 1 + read-write + + + 0 + The corresponding bit in the filter is "don't care." + #0 + + + 1 + The corresponding bit in the filter is checked. + #1 + + + + + RX14M30 + Rx Buffer 14 Mask Bits + 30 + 1 + read-write + + + 0 + The corresponding bit in the filter is "don't care." + #0 + + + 1 + The corresponding bit in the filter is checked. + #1 + + + + + RX14M31 + Rx Buffer 14 Mask Bits + 31 + 1 read-write @@ -24222,10 +25401,599 @@ 0xFFFFFFFF - RX15M + RX15M0 Rx Buffer 15 Mask Bits 0 - 32 + 1 + read-write + + + 0 + The corresponding bit in the filter is "don't care." + #0 + + + 1 + The corresponding bit in the filter is checked. + #1 + + + + + RX15M1 + Rx Buffer 15 Mask Bits + 1 + 1 + read-write + + + 0 + The corresponding bit in the filter is "don't care." + #0 + + + 1 + The corresponding bit in the filter is checked. + #1 + + + + + RX15M2 + Rx Buffer 15 Mask Bits + 2 + 1 + read-write + + + 0 + The corresponding bit in the filter is "don't care." + #0 + + + 1 + The corresponding bit in the filter is checked. + #1 + + + + + RX15M3 + Rx Buffer 15 Mask Bits + 3 + 1 + read-write + + + 0 + The corresponding bit in the filter is "don't care." + #0 + + + 1 + The corresponding bit in the filter is checked. + #1 + + + + + RX15M4 + Rx Buffer 15 Mask Bits + 4 + 1 + read-write + + + 0 + The corresponding bit in the filter is "don't care." + #0 + + + 1 + The corresponding bit in the filter is checked. + #1 + + + + + RX15M5 + Rx Buffer 15 Mask Bits + 5 + 1 + read-write + + + 0 + The corresponding bit in the filter is "don't care." + #0 + + + 1 + The corresponding bit in the filter is checked. + #1 + + + + + RX15M6 + Rx Buffer 15 Mask Bits + 6 + 1 + read-write + + + 0 + The corresponding bit in the filter is "don't care." + #0 + + + 1 + The corresponding bit in the filter is checked. + #1 + + + + + RX15M7 + Rx Buffer 15 Mask Bits + 7 + 1 + read-write + + + 0 + The corresponding bit in the filter is "don't care." + #0 + + + 1 + The corresponding bit in the filter is checked. + #1 + + + + + RX15M8 + Rx Buffer 15 Mask Bits + 8 + 1 + read-write + + + 0 + The corresponding bit in the filter is "don't care." + #0 + + + 1 + The corresponding bit in the filter is checked. + #1 + + + + + RX15M9 + Rx Buffer 15 Mask Bits + 9 + 1 + read-write + + + 0 + The corresponding bit in the filter is "don't care." + #0 + + + 1 + The corresponding bit in the filter is checked. + #1 + + + + + RX15M10 + Rx Buffer 15 Mask Bits + 10 + 1 + read-write + + + 0 + The corresponding bit in the filter is "don't care." + #0 + + + 1 + The corresponding bit in the filter is checked. + #1 + + + + + RX15M11 + Rx Buffer 15 Mask Bits + 11 + 1 + read-write + + + 0 + The corresponding bit in the filter is "don't care." + #0 + + + 1 + The corresponding bit in the filter is checked. + #1 + + + + + RX15M12 + Rx Buffer 15 Mask Bits + 12 + 1 + read-write + + + 0 + The corresponding bit in the filter is "don't care." + #0 + + + 1 + The corresponding bit in the filter is checked. + #1 + + + + + RX15M13 + Rx Buffer 15 Mask Bits + 13 + 1 + read-write + + + 0 + The corresponding bit in the filter is "don't care." + #0 + + + 1 + The corresponding bit in the filter is checked. + #1 + + + + + RX15M14 + Rx Buffer 15 Mask Bits + 14 + 1 + read-write + + + 0 + The corresponding bit in the filter is "don't care." + #0 + + + 1 + The corresponding bit in the filter is checked. + #1 + + + + + RX15M15 + Rx Buffer 15 Mask Bits + 15 + 1 + read-write + + + 0 + The corresponding bit in the filter is "don't care." + #0 + + + 1 + The corresponding bit in the filter is checked. + #1 + + + + + RX15M16 + Rx Buffer 15 Mask Bits + 16 + 1 + read-write + + + 0 + The corresponding bit in the filter is "don't care." + #0 + + + 1 + The corresponding bit in the filter is checked. + #1 + + + + + RX15M17 + Rx Buffer 15 Mask Bits + 17 + 1 + read-write + + + 0 + The corresponding bit in the filter is "don't care." + #0 + + + 1 + The corresponding bit in the filter is checked. + #1 + + + + + RX15M18 + Rx Buffer 15 Mask Bits + 18 + 1 + read-write + + + 0 + The corresponding bit in the filter is "don't care." + #0 + + + 1 + The corresponding bit in the filter is checked. + #1 + + + + + RX15M19 + Rx Buffer 15 Mask Bits + 19 + 1 + read-write + + + 0 + The corresponding bit in the filter is "don't care." + #0 + + + 1 + The corresponding bit in the filter is checked. + #1 + + + + + RX15M20 + Rx Buffer 15 Mask Bits + 20 + 1 + read-write + + + 0 + The corresponding bit in the filter is "don't care." + #0 + + + 1 + The corresponding bit in the filter is checked. + #1 + + + + + RX15M21 + Rx Buffer 15 Mask Bits + 21 + 1 + read-write + + + 0 + The corresponding bit in the filter is "don't care." + #0 + + + 1 + The corresponding bit in the filter is checked. + #1 + + + + + RX15M22 + Rx Buffer 15 Mask Bits + 22 + 1 + read-write + + + 0 + The corresponding bit in the filter is "don't care." + #0 + + + 1 + The corresponding bit in the filter is checked. + #1 + + + + + RX15M23 + Rx Buffer 15 Mask Bits + 23 + 1 + read-write + + + 0 + The corresponding bit in the filter is "don't care." + #0 + + + 1 + The corresponding bit in the filter is checked. + #1 + + + + + RX15M24 + Rx Buffer 15 Mask Bits + 24 + 1 + read-write + + + 0 + The corresponding bit in the filter is "don't care." + #0 + + + 1 + The corresponding bit in the filter is checked. + #1 + + + + + RX15M25 + Rx Buffer 15 Mask Bits + 25 + 1 + read-write + + + 0 + The corresponding bit in the filter is "don't care." + #0 + + + 1 + The corresponding bit in the filter is checked. + #1 + + + + + RX15M26 + Rx Buffer 15 Mask Bits + 26 + 1 + read-write + + + 0 + The corresponding bit in the filter is "don't care." + #0 + + + 1 + The corresponding bit in the filter is checked. + #1 + + + + + RX15M27 + Rx Buffer 15 Mask Bits + 27 + 1 + read-write + + + 0 + The corresponding bit in the filter is "don't care." + #0 + + + 1 + The corresponding bit in the filter is checked. + #1 + + + + + RX15M28 + Rx Buffer 15 Mask Bits + 28 + 1 + read-write + + + 0 + The corresponding bit in the filter is "don't care." + #0 + + + 1 + The corresponding bit in the filter is checked. + #1 + + + + + RX15M29 + Rx Buffer 15 Mask Bits + 29 + 1 + read-write + + + 0 + The corresponding bit in the filter is "don't care." + #0 + + + 1 + The corresponding bit in the filter is checked. + #1 + + + + + RX15M30 + Rx Buffer 15 Mask Bits + 30 + 1 + read-write + + + 0 + The corresponding bit in the filter is "don't care." + #0 + + + 1 + The corresponding bit in the filter is checked. + #1 + + + + + RX15M31 + Rx Buffer 15 Mask Bits + 31 + 1 read-write @@ -24630,10 +26398,599 @@ 0xFFFFFFFF - BUFLM + BUFLM0 Buffer MB i Mask 0 - 32 + 1 + read-write + + + 0 + The corresponding buffer Interrupt is disabled. + #0 + + + 1 + The corresponding buffer Interrupt is enabled. + #1 + + + + + BUFLM1 + Buffer MB i Mask + 1 + 1 + read-write + + + 0 + The corresponding buffer Interrupt is disabled. + #0 + + + 1 + The corresponding buffer Interrupt is enabled. + #1 + + + + + BUFLM2 + Buffer MB i Mask + 2 + 1 + read-write + + + 0 + The corresponding buffer Interrupt is disabled. + #0 + + + 1 + The corresponding buffer Interrupt is enabled. + #1 + + + + + BUFLM3 + Buffer MB i Mask + 3 + 1 + read-write + + + 0 + The corresponding buffer Interrupt is disabled. + #0 + + + 1 + The corresponding buffer Interrupt is enabled. + #1 + + + + + BUFLM4 + Buffer MB i Mask + 4 + 1 + read-write + + + 0 + The corresponding buffer Interrupt is disabled. + #0 + + + 1 + The corresponding buffer Interrupt is enabled. + #1 + + + + + BUFLM5 + Buffer MB i Mask + 5 + 1 + read-write + + + 0 + The corresponding buffer Interrupt is disabled. + #0 + + + 1 + The corresponding buffer Interrupt is enabled. + #1 + + + + + BUFLM6 + Buffer MB i Mask + 6 + 1 + read-write + + + 0 + The corresponding buffer Interrupt is disabled. + #0 + + + 1 + The corresponding buffer Interrupt is enabled. + #1 + + + + + BUFLM7 + Buffer MB i Mask + 7 + 1 + read-write + + + 0 + The corresponding buffer Interrupt is disabled. + #0 + + + 1 + The corresponding buffer Interrupt is enabled. + #1 + + + + + BUFLM8 + Buffer MB i Mask + 8 + 1 + read-write + + + 0 + The corresponding buffer Interrupt is disabled. + #0 + + + 1 + The corresponding buffer Interrupt is enabled. + #1 + + + + + BUFLM9 + Buffer MB i Mask + 9 + 1 + read-write + + + 0 + The corresponding buffer Interrupt is disabled. + #0 + + + 1 + The corresponding buffer Interrupt is enabled. + #1 + + + + + BUFLM10 + Buffer MB i Mask + 10 + 1 + read-write + + + 0 + The corresponding buffer Interrupt is disabled. + #0 + + + 1 + The corresponding buffer Interrupt is enabled. + #1 + + + + + BUFLM11 + Buffer MB i Mask + 11 + 1 + read-write + + + 0 + The corresponding buffer Interrupt is disabled. + #0 + + + 1 + The corresponding buffer Interrupt is enabled. + #1 + + + + + BUFLM12 + Buffer MB i Mask + 12 + 1 + read-write + + + 0 + The corresponding buffer Interrupt is disabled. + #0 + + + 1 + The corresponding buffer Interrupt is enabled. + #1 + + + + + BUFLM13 + Buffer MB i Mask + 13 + 1 + read-write + + + 0 + The corresponding buffer Interrupt is disabled. + #0 + + + 1 + The corresponding buffer Interrupt is enabled. + #1 + + + + + BUFLM14 + Buffer MB i Mask + 14 + 1 + read-write + + + 0 + The corresponding buffer Interrupt is disabled. + #0 + + + 1 + The corresponding buffer Interrupt is enabled. + #1 + + + + + BUFLM15 + Buffer MB i Mask + 15 + 1 + read-write + + + 0 + The corresponding buffer Interrupt is disabled. + #0 + + + 1 + The corresponding buffer Interrupt is enabled. + #1 + + + + + BUFLM16 + Buffer MB i Mask + 16 + 1 + read-write + + + 0 + The corresponding buffer Interrupt is disabled. + #0 + + + 1 + The corresponding buffer Interrupt is enabled. + #1 + + + + + BUFLM17 + Buffer MB i Mask + 17 + 1 + read-write + + + 0 + The corresponding buffer Interrupt is disabled. + #0 + + + 1 + The corresponding buffer Interrupt is enabled. + #1 + + + + + BUFLM18 + Buffer MB i Mask + 18 + 1 + read-write + + + 0 + The corresponding buffer Interrupt is disabled. + #0 + + + 1 + The corresponding buffer Interrupt is enabled. + #1 + + + + + BUFLM19 + Buffer MB i Mask + 19 + 1 + read-write + + + 0 + The corresponding buffer Interrupt is disabled. + #0 + + + 1 + The corresponding buffer Interrupt is enabled. + #1 + + + + + BUFLM20 + Buffer MB i Mask + 20 + 1 + read-write + + + 0 + The corresponding buffer Interrupt is disabled. + #0 + + + 1 + The corresponding buffer Interrupt is enabled. + #1 + + + + + BUFLM21 + Buffer MB i Mask + 21 + 1 + read-write + + + 0 + The corresponding buffer Interrupt is disabled. + #0 + + + 1 + The corresponding buffer Interrupt is enabled. + #1 + + + + + BUFLM22 + Buffer MB i Mask + 22 + 1 + read-write + + + 0 + The corresponding buffer Interrupt is disabled. + #0 + + + 1 + The corresponding buffer Interrupt is enabled. + #1 + + + + + BUFLM23 + Buffer MB i Mask + 23 + 1 + read-write + + + 0 + The corresponding buffer Interrupt is disabled. + #0 + + + 1 + The corresponding buffer Interrupt is enabled. + #1 + + + + + BUFLM24 + Buffer MB i Mask + 24 + 1 + read-write + + + 0 + The corresponding buffer Interrupt is disabled. + #0 + + + 1 + The corresponding buffer Interrupt is enabled. + #1 + + + + + BUFLM25 + Buffer MB i Mask + 25 + 1 + read-write + + + 0 + The corresponding buffer Interrupt is disabled. + #0 + + + 1 + The corresponding buffer Interrupt is enabled. + #1 + + + + + BUFLM26 + Buffer MB i Mask + 26 + 1 + read-write + + + 0 + The corresponding buffer Interrupt is disabled. + #0 + + + 1 + The corresponding buffer Interrupt is enabled. + #1 + + + + + BUFLM27 + Buffer MB i Mask + 27 + 1 + read-write + + + 0 + The corresponding buffer Interrupt is disabled. + #0 + + + 1 + The corresponding buffer Interrupt is enabled. + #1 + + + + + BUFLM28 + Buffer MB i Mask + 28 + 1 + read-write + + + 0 + The corresponding buffer Interrupt is disabled. + #0 + + + 1 + The corresponding buffer Interrupt is enabled. + #1 + + + + + BUFLM29 + Buffer MB i Mask + 29 + 1 + read-write + + + 0 + The corresponding buffer Interrupt is disabled. + #0 + + + 1 + The corresponding buffer Interrupt is enabled. + #1 + + + + + BUFLM30 + Buffer MB i Mask + 30 + 1 + read-write + + + 0 + The corresponding buffer Interrupt is disabled. + #0 + + + 1 + The corresponding buffer Interrupt is enabled. + #1 + + + + + BUFLM31 + Buffer MB i Mask + 31 + 1 read-write @@ -24679,10 +27036,67 @@ - BUF4TO1I + BUF4TO1I0 Buffer MB i Interrupt Or "reserved" 1 - 4 + 1 + read-write + + + 0 + The corresponding buffer has no occurrence of successfully completed transmission or reception when MCR[RFEN]=0. + #0000 + + + 1 + The corresponding buffer has successfully completed transmission or reception when MCR[RFEN]=0. + #0001 + + + + + BUF4TO1I1 + Buffer MB i Interrupt Or "reserved" + 2 + 1 + read-write + + + 0 + The corresponding buffer has no occurrence of successfully completed transmission or reception when MCR[RFEN]=0. + #0000 + + + 1 + The corresponding buffer has successfully completed transmission or reception when MCR[RFEN]=0. + #0001 + + + + + BUF4TO1I2 + Buffer MB i Interrupt Or "reserved" + 3 + 1 + read-write + + + 0 + The corresponding buffer has no occurrence of successfully completed transmission or reception when MCR[RFEN]=0. + #0000 + + + 1 + The corresponding buffer has successfully completed transmission or reception when MCR[RFEN]=0. + #0001 + + + + + BUF4TO1I3 + Buffer MB i Interrupt Or "reserved" + 4 + 1 read-write @@ -24755,10 +27169,447 @@ - BUF31TO8I + BUF31TO8I0 Buffer MBi Interrupt 8 - 24 + 1 + read-write + + + 0 + The corresponding buffer has no occurrence of successfully completed transmission or reception. + #0 + + + 1 + The corresponding buffer has successfully completed transmission or reception. + #1 + + + + + BUF31TO8I1 + Buffer MBi Interrupt + 9 + 1 + read-write + + + 0 + The corresponding buffer has no occurrence of successfully completed transmission or reception. + #0 + + + 1 + The corresponding buffer has successfully completed transmission or reception. + #1 + + + + + BUF31TO8I2 + Buffer MBi Interrupt + 10 + 1 + read-write + + + 0 + The corresponding buffer has no occurrence of successfully completed transmission or reception. + #0 + + + 1 + The corresponding buffer has successfully completed transmission or reception. + #1 + + + + + BUF31TO8I3 + Buffer MBi Interrupt + 11 + 1 + read-write + + + 0 + The corresponding buffer has no occurrence of successfully completed transmission or reception. + #0 + + + 1 + The corresponding buffer has successfully completed transmission or reception. + #1 + + + + + BUF31TO8I4 + Buffer MBi Interrupt + 12 + 1 + read-write + + + 0 + The corresponding buffer has no occurrence of successfully completed transmission or reception. + #0 + + + 1 + The corresponding buffer has successfully completed transmission or reception. + #1 + + + + + BUF31TO8I5 + Buffer MBi Interrupt + 13 + 1 + read-write + + + 0 + The corresponding buffer has no occurrence of successfully completed transmission or reception. + #0 + + + 1 + The corresponding buffer has successfully completed transmission or reception. + #1 + + + + + BUF31TO8I6 + Buffer MBi Interrupt + 14 + 1 + read-write + + + 0 + The corresponding buffer has no occurrence of successfully completed transmission or reception. + #0 + + + 1 + The corresponding buffer has successfully completed transmission or reception. + #1 + + + + + BUF31TO8I7 + Buffer MBi Interrupt + 15 + 1 + read-write + + + 0 + The corresponding buffer has no occurrence of successfully completed transmission or reception. + #0 + + + 1 + The corresponding buffer has successfully completed transmission or reception. + #1 + + + + + BUF31TO8I8 + Buffer MBi Interrupt + 16 + 1 + read-write + + + 0 + The corresponding buffer has no occurrence of successfully completed transmission or reception. + #0 + + + 1 + The corresponding buffer has successfully completed transmission or reception. + #1 + + + + + BUF31TO8I9 + Buffer MBi Interrupt + 17 + 1 + read-write + + + 0 + The corresponding buffer has no occurrence of successfully completed transmission or reception. + #0 + + + 1 + The corresponding buffer has successfully completed transmission or reception. + #1 + + + + + BUF31TO8I10 + Buffer MBi Interrupt + 18 + 1 + read-write + + + 0 + The corresponding buffer has no occurrence of successfully completed transmission or reception. + #0 + + + 1 + The corresponding buffer has successfully completed transmission or reception. + #1 + + + + + BUF31TO8I11 + Buffer MBi Interrupt + 19 + 1 + read-write + + + 0 + The corresponding buffer has no occurrence of successfully completed transmission or reception. + #0 + + + 1 + The corresponding buffer has successfully completed transmission or reception. + #1 + + + + + BUF31TO8I12 + Buffer MBi Interrupt + 20 + 1 + read-write + + + 0 + The corresponding buffer has no occurrence of successfully completed transmission or reception. + #0 + + + 1 + The corresponding buffer has successfully completed transmission or reception. + #1 + + + + + BUF31TO8I13 + Buffer MBi Interrupt + 21 + 1 + read-write + + + 0 + The corresponding buffer has no occurrence of successfully completed transmission or reception. + #0 + + + 1 + The corresponding buffer has successfully completed transmission or reception. + #1 + + + + + BUF31TO8I14 + Buffer MBi Interrupt + 22 + 1 + read-write + + + 0 + The corresponding buffer has no occurrence of successfully completed transmission or reception. + #0 + + + 1 + The corresponding buffer has successfully completed transmission or reception. + #1 + + + + + BUF31TO8I15 + Buffer MBi Interrupt + 23 + 1 + read-write + + + 0 + The corresponding buffer has no occurrence of successfully completed transmission or reception. + #0 + + + 1 + The corresponding buffer has successfully completed transmission or reception. + #1 + + + + + BUF31TO8I16 + Buffer MBi Interrupt + 24 + 1 + read-write + + + 0 + The corresponding buffer has no occurrence of successfully completed transmission or reception. + #0 + + + 1 + The corresponding buffer has successfully completed transmission or reception. + #1 + + + + + BUF31TO8I17 + Buffer MBi Interrupt + 25 + 1 + read-write + + + 0 + The corresponding buffer has no occurrence of successfully completed transmission or reception. + #0 + + + 1 + The corresponding buffer has successfully completed transmission or reception. + #1 + + + + + BUF31TO8I18 + Buffer MBi Interrupt + 26 + 1 + read-write + + + 0 + The corresponding buffer has no occurrence of successfully completed transmission or reception. + #0 + + + 1 + The corresponding buffer has successfully completed transmission or reception. + #1 + + + + + BUF31TO8I19 + Buffer MBi Interrupt + 27 + 1 + read-write + + + 0 + The corresponding buffer has no occurrence of successfully completed transmission or reception. + #0 + + + 1 + The corresponding buffer has successfully completed transmission or reception. + #1 + + + + + BUF31TO8I20 + Buffer MBi Interrupt + 28 + 1 + read-write + + + 0 + The corresponding buffer has no occurrence of successfully completed transmission or reception. + #0 + + + 1 + The corresponding buffer has successfully completed transmission or reception. + #1 + + + + + BUF31TO8I21 + Buffer MBi Interrupt + 29 + 1 + read-write + + + 0 + The corresponding buffer has no occurrence of successfully completed transmission or reception. + #0 + + + 1 + The corresponding buffer has successfully completed transmission or reception. + #1 + + + + + BUF31TO8I22 + Buffer MBi Interrupt + 30 + 1 + read-write + + + 0 + The corresponding buffer has no occurrence of successfully completed transmission or reception. + #0 + + + 1 + The corresponding buffer has successfully completed transmission or reception. + #1 + + + + + BUF31TO8I23 + Buffer MBi Interrupt + 31 + 1 read-write @@ -24967,10 +27818,599 @@ 0xFFFFFFFF - FGM + FGM0 Rx FIFO Global Mask Bits 0 - 32 + 1 + read-write + + + 0 + The corresponding bit in the filter is "don't care." + #0 + + + 1 + The corresponding bit in the filter is checked. + #1 + + + + + FGM1 + Rx FIFO Global Mask Bits + 1 + 1 + read-write + + + 0 + The corresponding bit in the filter is "don't care." + #0 + + + 1 + The corresponding bit in the filter is checked. + #1 + + + + + FGM2 + Rx FIFO Global Mask Bits + 2 + 1 + read-write + + + 0 + The corresponding bit in the filter is "don't care." + #0 + + + 1 + The corresponding bit in the filter is checked. + #1 + + + + + FGM3 + Rx FIFO Global Mask Bits + 3 + 1 + read-write + + + 0 + The corresponding bit in the filter is "don't care." + #0 + + + 1 + The corresponding bit in the filter is checked. + #1 + + + + + FGM4 + Rx FIFO Global Mask Bits + 4 + 1 + read-write + + + 0 + The corresponding bit in the filter is "don't care." + #0 + + + 1 + The corresponding bit in the filter is checked. + #1 + + + + + FGM5 + Rx FIFO Global Mask Bits + 5 + 1 + read-write + + + 0 + The corresponding bit in the filter is "don't care." + #0 + + + 1 + The corresponding bit in the filter is checked. + #1 + + + + + FGM6 + Rx FIFO Global Mask Bits + 6 + 1 + read-write + + + 0 + The corresponding bit in the filter is "don't care." + #0 + + + 1 + The corresponding bit in the filter is checked. + #1 + + + + + FGM7 + Rx FIFO Global Mask Bits + 7 + 1 + read-write + + + 0 + The corresponding bit in the filter is "don't care." + #0 + + + 1 + The corresponding bit in the filter is checked. + #1 + + + + + FGM8 + Rx FIFO Global Mask Bits + 8 + 1 + read-write + + + 0 + The corresponding bit in the filter is "don't care." + #0 + + + 1 + The corresponding bit in the filter is checked. + #1 + + + + + FGM9 + Rx FIFO Global Mask Bits + 9 + 1 + read-write + + + 0 + The corresponding bit in the filter is "don't care." + #0 + + + 1 + The corresponding bit in the filter is checked. + #1 + + + + + FGM10 + Rx FIFO Global Mask Bits + 10 + 1 + read-write + + + 0 + The corresponding bit in the filter is "don't care." + #0 + + + 1 + The corresponding bit in the filter is checked. + #1 + + + + + FGM11 + Rx FIFO Global Mask Bits + 11 + 1 + read-write + + + 0 + The corresponding bit in the filter is "don't care." + #0 + + + 1 + The corresponding bit in the filter is checked. + #1 + + + + + FGM12 + Rx FIFO Global Mask Bits + 12 + 1 + read-write + + + 0 + The corresponding bit in the filter is "don't care." + #0 + + + 1 + The corresponding bit in the filter is checked. + #1 + + + + + FGM13 + Rx FIFO Global Mask Bits + 13 + 1 + read-write + + + 0 + The corresponding bit in the filter is "don't care." + #0 + + + 1 + The corresponding bit in the filter is checked. + #1 + + + + + FGM14 + Rx FIFO Global Mask Bits + 14 + 1 + read-write + + + 0 + The corresponding bit in the filter is "don't care." + #0 + + + 1 + The corresponding bit in the filter is checked. + #1 + + + + + FGM15 + Rx FIFO Global Mask Bits + 15 + 1 + read-write + + + 0 + The corresponding bit in the filter is "don't care." + #0 + + + 1 + The corresponding bit in the filter is checked. + #1 + + + + + FGM16 + Rx FIFO Global Mask Bits + 16 + 1 + read-write + + + 0 + The corresponding bit in the filter is "don't care." + #0 + + + 1 + The corresponding bit in the filter is checked. + #1 + + + + + FGM17 + Rx FIFO Global Mask Bits + 17 + 1 + read-write + + + 0 + The corresponding bit in the filter is "don't care." + #0 + + + 1 + The corresponding bit in the filter is checked. + #1 + + + + + FGM18 + Rx FIFO Global Mask Bits + 18 + 1 + read-write + + + 0 + The corresponding bit in the filter is "don't care." + #0 + + + 1 + The corresponding bit in the filter is checked. + #1 + + + + + FGM19 + Rx FIFO Global Mask Bits + 19 + 1 + read-write + + + 0 + The corresponding bit in the filter is "don't care." + #0 + + + 1 + The corresponding bit in the filter is checked. + #1 + + + + + FGM20 + Rx FIFO Global Mask Bits + 20 + 1 + read-write + + + 0 + The corresponding bit in the filter is "don't care." + #0 + + + 1 + The corresponding bit in the filter is checked. + #1 + + + + + FGM21 + Rx FIFO Global Mask Bits + 21 + 1 + read-write + + + 0 + The corresponding bit in the filter is "don't care." + #0 + + + 1 + The corresponding bit in the filter is checked. + #1 + + + + + FGM22 + Rx FIFO Global Mask Bits + 22 + 1 + read-write + + + 0 + The corresponding bit in the filter is "don't care." + #0 + + + 1 + The corresponding bit in the filter is checked. + #1 + + + + + FGM23 + Rx FIFO Global Mask Bits + 23 + 1 + read-write + + + 0 + The corresponding bit in the filter is "don't care." + #0 + + + 1 + The corresponding bit in the filter is checked. + #1 + + + + + FGM24 + Rx FIFO Global Mask Bits + 24 + 1 + read-write + + + 0 + The corresponding bit in the filter is "don't care." + #0 + + + 1 + The corresponding bit in the filter is checked. + #1 + + + + + FGM25 + Rx FIFO Global Mask Bits + 25 + 1 + read-write + + + 0 + The corresponding bit in the filter is "don't care." + #0 + + + 1 + The corresponding bit in the filter is checked. + #1 + + + + + FGM26 + Rx FIFO Global Mask Bits + 26 + 1 + read-write + + + 0 + The corresponding bit in the filter is "don't care." + #0 + + + 1 + The corresponding bit in the filter is checked. + #1 + + + + + FGM27 + Rx FIFO Global Mask Bits + 27 + 1 + read-write + + + 0 + The corresponding bit in the filter is "don't care." + #0 + + + 1 + The corresponding bit in the filter is checked. + #1 + + + + + FGM28 + Rx FIFO Global Mask Bits + 28 + 1 + read-write + + + 0 + The corresponding bit in the filter is "don't care." + #0 + + + 1 + The corresponding bit in the filter is checked. + #1 + + + + + FGM29 + Rx FIFO Global Mask Bits + 29 + 1 + read-write + + + 0 + The corresponding bit in the filter is "don't care." + #0 + + + 1 + The corresponding bit in the filter is checked. + #1 + + + + + FGM30 + Rx FIFO Global Mask Bits + 30 + 1 + read-write + + + 0 + The corresponding bit in the filter is "don't care." + #0 + + + 1 + The corresponding bit in the filter is checked. + #1 + + + + + FGM31 + Rx FIFO Global Mask Bits + 31 + 1 read-write @@ -27626,10 +31066,599 @@ 0 - MI + MI0 Individual Mask Bits 0 - 32 + 1 + read-write + + + 0 + The corresponding bit in the filter is "don't care." + #0 + + + 1 + The corresponding bit in the filter is checked. + #1 + + + + + MI1 + Individual Mask Bits + 1 + 1 + read-write + + + 0 + The corresponding bit in the filter is "don't care." + #0 + + + 1 + The corresponding bit in the filter is checked. + #1 + + + + + MI2 + Individual Mask Bits + 2 + 1 + read-write + + + 0 + The corresponding bit in the filter is "don't care." + #0 + + + 1 + The corresponding bit in the filter is checked. + #1 + + + + + MI3 + Individual Mask Bits + 3 + 1 + read-write + + + 0 + The corresponding bit in the filter is "don't care." + #0 + + + 1 + The corresponding bit in the filter is checked. + #1 + + + + + MI4 + Individual Mask Bits + 4 + 1 + read-write + + + 0 + The corresponding bit in the filter is "don't care." + #0 + + + 1 + The corresponding bit in the filter is checked. + #1 + + + + + MI5 + Individual Mask Bits + 5 + 1 + read-write + + + 0 + The corresponding bit in the filter is "don't care." + #0 + + + 1 + The corresponding bit in the filter is checked. + #1 + + + + + MI6 + Individual Mask Bits + 6 + 1 + read-write + + + 0 + The corresponding bit in the filter is "don't care." + #0 + + + 1 + The corresponding bit in the filter is checked. + #1 + + + + + MI7 + Individual Mask Bits + 7 + 1 + read-write + + + 0 + The corresponding bit in the filter is "don't care." + #0 + + + 1 + The corresponding bit in the filter is checked. + #1 + + + + + MI8 + Individual Mask Bits + 8 + 1 + read-write + + + 0 + The corresponding bit in the filter is "don't care." + #0 + + + 1 + The corresponding bit in the filter is checked. + #1 + + + + + MI9 + Individual Mask Bits + 9 + 1 + read-write + + + 0 + The corresponding bit in the filter is "don't care." + #0 + + + 1 + The corresponding bit in the filter is checked. + #1 + + + + + MI10 + Individual Mask Bits + 10 + 1 + read-write + + + 0 + The corresponding bit in the filter is "don't care." + #0 + + + 1 + The corresponding bit in the filter is checked. + #1 + + + + + MI11 + Individual Mask Bits + 11 + 1 + read-write + + + 0 + The corresponding bit in the filter is "don't care." + #0 + + + 1 + The corresponding bit in the filter is checked. + #1 + + + + + MI12 + Individual Mask Bits + 12 + 1 + read-write + + + 0 + The corresponding bit in the filter is "don't care." + #0 + + + 1 + The corresponding bit in the filter is checked. + #1 + + + + + MI13 + Individual Mask Bits + 13 + 1 + read-write + + + 0 + The corresponding bit in the filter is "don't care." + #0 + + + 1 + The corresponding bit in the filter is checked. + #1 + + + + + MI14 + Individual Mask Bits + 14 + 1 + read-write + + + 0 + The corresponding bit in the filter is "don't care." + #0 + + + 1 + The corresponding bit in the filter is checked. + #1 + + + + + MI15 + Individual Mask Bits + 15 + 1 + read-write + + + 0 + The corresponding bit in the filter is "don't care." + #0 + + + 1 + The corresponding bit in the filter is checked. + #1 + + + + + MI16 + Individual Mask Bits + 16 + 1 + read-write + + + 0 + The corresponding bit in the filter is "don't care." + #0 + + + 1 + The corresponding bit in the filter is checked. + #1 + + + + + MI17 + Individual Mask Bits + 17 + 1 + read-write + + + 0 + The corresponding bit in the filter is "don't care." + #0 + + + 1 + The corresponding bit in the filter is checked. + #1 + + + + + MI18 + Individual Mask Bits + 18 + 1 + read-write + + + 0 + The corresponding bit in the filter is "don't care." + #0 + + + 1 + The corresponding bit in the filter is checked. + #1 + + + + + MI19 + Individual Mask Bits + 19 + 1 + read-write + + + 0 + The corresponding bit in the filter is "don't care." + #0 + + + 1 + The corresponding bit in the filter is checked. + #1 + + + + + MI20 + Individual Mask Bits + 20 + 1 + read-write + + + 0 + The corresponding bit in the filter is "don't care." + #0 + + + 1 + The corresponding bit in the filter is checked. + #1 + + + + + MI21 + Individual Mask Bits + 21 + 1 + read-write + + + 0 + The corresponding bit in the filter is "don't care." + #0 + + + 1 + The corresponding bit in the filter is checked. + #1 + + + + + MI22 + Individual Mask Bits + 22 + 1 + read-write + + + 0 + The corresponding bit in the filter is "don't care." + #0 + + + 1 + The corresponding bit in the filter is checked. + #1 + + + + + MI23 + Individual Mask Bits + 23 + 1 + read-write + + + 0 + The corresponding bit in the filter is "don't care." + #0 + + + 1 + The corresponding bit in the filter is checked. + #1 + + + + + MI24 + Individual Mask Bits + 24 + 1 + read-write + + + 0 + The corresponding bit in the filter is "don't care." + #0 + + + 1 + The corresponding bit in the filter is checked. + #1 + + + + + MI25 + Individual Mask Bits + 25 + 1 + read-write + + + 0 + The corresponding bit in the filter is "don't care." + #0 + + + 1 + The corresponding bit in the filter is checked. + #1 + + + + + MI26 + Individual Mask Bits + 26 + 1 + read-write + + + 0 + The corresponding bit in the filter is "don't care." + #0 + + + 1 + The corresponding bit in the filter is checked. + #1 + + + + + MI27 + Individual Mask Bits + 27 + 1 + read-write + + + 0 + The corresponding bit in the filter is "don't care." + #0 + + + 1 + The corresponding bit in the filter is checked. + #1 + + + + + MI28 + Individual Mask Bits + 28 + 1 + read-write + + + 0 + The corresponding bit in the filter is "don't care." + #0 + + + 1 + The corresponding bit in the filter is checked. + #1 + + + + + MI29 + Individual Mask Bits + 29 + 1 + read-write + + + 0 + The corresponding bit in the filter is "don't care." + #0 + + + 1 + The corresponding bit in the filter is checked. + #1 + + + + + MI30 + Individual Mask Bits + 30 + 1 + read-write + + + 0 + The corresponding bit in the filter is "don't care." + #0 + + + 1 + The corresponding bit in the filter is checked. + #1 + + + + + MI31 + Individual Mask Bits + 31 + 1 read-write @@ -28136,10 +32165,105 @@ - PCSIS + PCSIS0 Peripheral Chip Select x Inactive State 16 - 6 + 1 + read-write + + + 0 + The inactive state of PCSx is low. + #0 + + + 1 + The inactive state of PCSx is high. + #1 + + + + + PCSIS1 + Peripheral Chip Select x Inactive State + 17 + 1 + read-write + + + 0 + The inactive state of PCSx is low. + #0 + + + 1 + The inactive state of PCSx is high. + #1 + + + + + PCSIS2 + Peripheral Chip Select x Inactive State + 18 + 1 + read-write + + + 0 + The inactive state of PCSx is low. + #0 + + + 1 + The inactive state of PCSx is high. + #1 + + + + + PCSIS3 + Peripheral Chip Select x Inactive State + 19 + 1 + read-write + + + 0 + The inactive state of PCSx is low. + #0 + + + 1 + The inactive state of PCSx is high. + #1 + + + + + PCSIS4 + Peripheral Chip Select x Inactive State + 20 + 1 + read-write + + + 0 + The inactive state of PCSx is low. + #0 + + + 1 + The inactive state of PCSx is high. + #1 + + + + + PCSIS5 + Peripheral Chip Select x Inactive State + 21 + 1 read-write @@ -28954,10 +33078,105 @@ read-write - PCS + PCS0 Select which PCS signals are to be asserted for the transfer 16 - 6 + 1 + read-write + + + 0 + Negate the PCS[x] signal. + #0 + + + 1 + Assert the PCS[x] signal. + #1 + + + + + PCS1 + Select which PCS signals are to be asserted for the transfer + 17 + 1 + read-write + + + 0 + Negate the PCS[x] signal. + #0 + + + 1 + Assert the PCS[x] signal. + #1 + + + + + PCS2 + Select which PCS signals are to be asserted for the transfer + 18 + 1 + read-write + + + 0 + Negate the PCS[x] signal. + #0 + + + 1 + Assert the PCS[x] signal. + #1 + + + + + PCS3 + Select which PCS signals are to be asserted for the transfer + 19 + 1 + read-write + + + 0 + Negate the PCS[x] signal. + #0 + + + 1 + Assert the PCS[x] signal. + #1 + + + + + PCS4 + Select which PCS signals are to be asserted for the transfer + 20 + 1 + read-write + + + 0 + Negate the PCS[x] signal. + #0 + + + 1 + Assert the PCS[x] signal. + #1 + + + + + PCS5 + Select which PCS signals are to be asserted for the transfer + 21 + 1 read-write @@ -29321,10 +33540,105 @@ - PCSIS + PCSIS0 Peripheral Chip Select x Inactive State 16 - 6 + 1 + read-write + + + 0 + The inactive state of PCSx is low. + #0 + + + 1 + The inactive state of PCSx is high. + #1 + + + + + PCSIS1 + Peripheral Chip Select x Inactive State + 17 + 1 + read-write + + + 0 + The inactive state of PCSx is low. + #0 + + + 1 + The inactive state of PCSx is high. + #1 + + + + + PCSIS2 + Peripheral Chip Select x Inactive State + 18 + 1 + read-write + + + 0 + The inactive state of PCSx is low. + #0 + + + 1 + The inactive state of PCSx is high. + #1 + + + + + PCSIS3 + Peripheral Chip Select x Inactive State + 19 + 1 + read-write + + + 0 + The inactive state of PCSx is low. + #0 + + + 1 + The inactive state of PCSx is high. + #1 + + + + + PCSIS4 + Peripheral Chip Select x Inactive State + 20 + 1 + read-write + + + 0 + The inactive state of PCSx is low. + #0 + + + 1 + The inactive state of PCSx is high. + #1 + + + + + PCSIS5 + Peripheral Chip Select x Inactive State + 21 + 1 read-write @@ -30139,10 +34453,105 @@ read-write - PCS + PCS0 Select which PCS signals are to be asserted for the transfer 16 - 6 + 1 + read-write + + + 0 + Negate the PCS[x] signal. + #0 + + + 1 + Assert the PCS[x] signal. + #1 + + + + + PCS1 + Select which PCS signals are to be asserted for the transfer + 17 + 1 + read-write + + + 0 + Negate the PCS[x] signal. + #0 + + + 1 + Assert the PCS[x] signal. + #1 + + + + + PCS2 + Select which PCS signals are to be asserted for the transfer + 18 + 1 + read-write + + + 0 + Negate the PCS[x] signal. + #0 + + + 1 + Assert the PCS[x] signal. + #1 + + + + + PCS3 + Select which PCS signals are to be asserted for the transfer + 19 + 1 + read-write + + + 0 + Negate the PCS[x] signal. + #0 + + + 1 + Assert the PCS[x] signal. + #1 + + + + + PCS4 + Select which PCS signals are to be asserted for the transfer + 20 + 1 + read-write + + + 0 + Negate the PCS[x] signal. + #0 + + + 1 + Assert the PCS[x] signal. + #1 + + + + + PCS5 + Select which PCS signals are to be asserted for the transfer + 21 + 1 read-write @@ -30506,10 +34915,105 @@ - PCSIS + PCSIS0 Peripheral Chip Select x Inactive State 16 - 6 + 1 + read-write + + + 0 + The inactive state of PCSx is low. + #0 + + + 1 + The inactive state of PCSx is high. + #1 + + + + + PCSIS1 + Peripheral Chip Select x Inactive State + 17 + 1 + read-write + + + 0 + The inactive state of PCSx is low. + #0 + + + 1 + The inactive state of PCSx is high. + #1 + + + + + PCSIS2 + Peripheral Chip Select x Inactive State + 18 + 1 + read-write + + + 0 + The inactive state of PCSx is low. + #0 + + + 1 + The inactive state of PCSx is high. + #1 + + + + + PCSIS3 + Peripheral Chip Select x Inactive State + 19 + 1 + read-write + + + 0 + The inactive state of PCSx is low. + #0 + + + 1 + The inactive state of PCSx is high. + #1 + + + + + PCSIS4 + Peripheral Chip Select x Inactive State + 20 + 1 + read-write + + + 0 + The inactive state of PCSx is low. + #0 + + + 1 + The inactive state of PCSx is high. + #1 + + + + + PCSIS5 + Peripheral Chip Select x Inactive State + 21 + 1 read-write @@ -31324,10 +35828,105 @@ read-write - PCS + PCS0 Select which PCS signals are to be asserted for the transfer 16 - 6 + 1 + read-write + + + 0 + Negate the PCS[x] signal. + #0 + + + 1 + Assert the PCS[x] signal. + #1 + + + + + PCS1 + Select which PCS signals are to be asserted for the transfer + 17 + 1 + read-write + + + 0 + Negate the PCS[x] signal. + #0 + + + 1 + Assert the PCS[x] signal. + #1 + + + + + PCS2 + Select which PCS signals are to be asserted for the transfer + 18 + 1 + read-write + + + 0 + Negate the PCS[x] signal. + #0 + + + 1 + Assert the PCS[x] signal. + #1 + + + + + PCS3 + Select which PCS signals are to be asserted for the transfer + 19 + 1 + read-write + + + 0 + Negate the PCS[x] signal. + #0 + + + 1 + Assert the PCS[x] signal. + #1 + + + + + PCS4 + Select which PCS signals are to be asserted for the transfer + 20 + 1 + read-write + + + 0 + Negate the PCS[x] signal. + #0 + + + 1 + Assert the PCS[x] signal. + #1 + + + + + PCS5 + Select which PCS signals are to be asserted for the transfer + 21 + 1 read-write @@ -32067,10 +36666,29 @@ read-write - TCE + TCE0 Transmit Channel Enable 16 - 2 + 1 + read-write + + + 0 + Transmit data channel N is disabled. + #00 + + + 1 + Transmit data channel N is enabled. + #01 + + + + + TCE1 + Transmit Channel Enable + 17 + 1 read-write @@ -32279,10 +36897,599 @@ 0xFFFFFFFF - TWM + TWM0 Transmit Word Mask 0 - 32 + 1 + read-write + + + 0 + Word N is enabled. + #0 + + + 1 + Word N is masked. The transmit data pins are tri-stated when masked. + #1 + + + + + TWM1 + Transmit Word Mask + 1 + 1 + read-write + + + 0 + Word N is enabled. + #0 + + + 1 + Word N is masked. The transmit data pins are tri-stated when masked. + #1 + + + + + TWM2 + Transmit Word Mask + 2 + 1 + read-write + + + 0 + Word N is enabled. + #0 + + + 1 + Word N is masked. The transmit data pins are tri-stated when masked. + #1 + + + + + TWM3 + Transmit Word Mask + 3 + 1 + read-write + + + 0 + Word N is enabled. + #0 + + + 1 + Word N is masked. The transmit data pins are tri-stated when masked. + #1 + + + + + TWM4 + Transmit Word Mask + 4 + 1 + read-write + + + 0 + Word N is enabled. + #0 + + + 1 + Word N is masked. The transmit data pins are tri-stated when masked. + #1 + + + + + TWM5 + Transmit Word Mask + 5 + 1 + read-write + + + 0 + Word N is enabled. + #0 + + + 1 + Word N is masked. The transmit data pins are tri-stated when masked. + #1 + + + + + TWM6 + Transmit Word Mask + 6 + 1 + read-write + + + 0 + Word N is enabled. + #0 + + + 1 + Word N is masked. The transmit data pins are tri-stated when masked. + #1 + + + + + TWM7 + Transmit Word Mask + 7 + 1 + read-write + + + 0 + Word N is enabled. + #0 + + + 1 + Word N is masked. The transmit data pins are tri-stated when masked. + #1 + + + + + TWM8 + Transmit Word Mask + 8 + 1 + read-write + + + 0 + Word N is enabled. + #0 + + + 1 + Word N is masked. The transmit data pins are tri-stated when masked. + #1 + + + + + TWM9 + Transmit Word Mask + 9 + 1 + read-write + + + 0 + Word N is enabled. + #0 + + + 1 + Word N is masked. The transmit data pins are tri-stated when masked. + #1 + + + + + TWM10 + Transmit Word Mask + 10 + 1 + read-write + + + 0 + Word N is enabled. + #0 + + + 1 + Word N is masked. The transmit data pins are tri-stated when masked. + #1 + + + + + TWM11 + Transmit Word Mask + 11 + 1 + read-write + + + 0 + Word N is enabled. + #0 + + + 1 + Word N is masked. The transmit data pins are tri-stated when masked. + #1 + + + + + TWM12 + Transmit Word Mask + 12 + 1 + read-write + + + 0 + Word N is enabled. + #0 + + + 1 + Word N is masked. The transmit data pins are tri-stated when masked. + #1 + + + + + TWM13 + Transmit Word Mask + 13 + 1 + read-write + + + 0 + Word N is enabled. + #0 + + + 1 + Word N is masked. The transmit data pins are tri-stated when masked. + #1 + + + + + TWM14 + Transmit Word Mask + 14 + 1 + read-write + + + 0 + Word N is enabled. + #0 + + + 1 + Word N is masked. The transmit data pins are tri-stated when masked. + #1 + + + + + TWM15 + Transmit Word Mask + 15 + 1 + read-write + + + 0 + Word N is enabled. + #0 + + + 1 + Word N is masked. The transmit data pins are tri-stated when masked. + #1 + + + + + TWM16 + Transmit Word Mask + 16 + 1 + read-write + + + 0 + Word N is enabled. + #0 + + + 1 + Word N is masked. The transmit data pins are tri-stated when masked. + #1 + + + + + TWM17 + Transmit Word Mask + 17 + 1 + read-write + + + 0 + Word N is enabled. + #0 + + + 1 + Word N is masked. The transmit data pins are tri-stated when masked. + #1 + + + + + TWM18 + Transmit Word Mask + 18 + 1 + read-write + + + 0 + Word N is enabled. + #0 + + + 1 + Word N is masked. The transmit data pins are tri-stated when masked. + #1 + + + + + TWM19 + Transmit Word Mask + 19 + 1 + read-write + + + 0 + Word N is enabled. + #0 + + + 1 + Word N is masked. The transmit data pins are tri-stated when masked. + #1 + + + + + TWM20 + Transmit Word Mask + 20 + 1 + read-write + + + 0 + Word N is enabled. + #0 + + + 1 + Word N is masked. The transmit data pins are tri-stated when masked. + #1 + + + + + TWM21 + Transmit Word Mask + 21 + 1 + read-write + + + 0 + Word N is enabled. + #0 + + + 1 + Word N is masked. The transmit data pins are tri-stated when masked. + #1 + + + + + TWM22 + Transmit Word Mask + 22 + 1 + read-write + + + 0 + Word N is enabled. + #0 + + + 1 + Word N is masked. The transmit data pins are tri-stated when masked. + #1 + + + + + TWM23 + Transmit Word Mask + 23 + 1 + read-write + + + 0 + Word N is enabled. + #0 + + + 1 + Word N is masked. The transmit data pins are tri-stated when masked. + #1 + + + + + TWM24 + Transmit Word Mask + 24 + 1 + read-write + + + 0 + Word N is enabled. + #0 + + + 1 + Word N is masked. The transmit data pins are tri-stated when masked. + #1 + + + + + TWM25 + Transmit Word Mask + 25 + 1 + read-write + + + 0 + Word N is enabled. + #0 + + + 1 + Word N is masked. The transmit data pins are tri-stated when masked. + #1 + + + + + TWM26 + Transmit Word Mask + 26 + 1 + read-write + + + 0 + Word N is enabled. + #0 + + + 1 + Word N is masked. The transmit data pins are tri-stated when masked. + #1 + + + + + TWM27 + Transmit Word Mask + 27 + 1 + read-write + + + 0 + Word N is enabled. + #0 + + + 1 + Word N is masked. The transmit data pins are tri-stated when masked. + #1 + + + + + TWM28 + Transmit Word Mask + 28 + 1 + read-write + + + 0 + Word N is enabled. + #0 + + + 1 + Word N is masked. The transmit data pins are tri-stated when masked. + #1 + + + + + TWM29 + Transmit Word Mask + 29 + 1 + read-write + + + 0 + Word N is enabled. + #0 + + + 1 + Word N is masked. The transmit data pins are tri-stated when masked. + #1 + + + + + TWM30 + Transmit Word Mask + 30 + 1 + read-write + + + 0 + Word N is enabled. + #0 + + + 1 + Word N is masked. The transmit data pins are tri-stated when masked. + #1 + + + + + TWM31 + Transmit Word Mask + 31 + 1 read-write @@ -32839,10 +38046,29 @@ read-write - RCE + RCE0 Receive Channel Enable 16 - 2 + 1 + read-write + + + 0 + Receive data channel N is disabled. + #00 + + + 1 + Receive data channel N is enabled. + #01 + + + + + RCE1 + Receive Channel Enable + 17 + 1 read-write @@ -33051,10 +38277,599 @@ 0xFFFFFFFF - RWM + RWM0 Receive Word Mask 0 - 32 + 1 + read-write + + + 0 + Word N is enabled. + #0 + + + 1 + Word N is masked. + #1 + + + + + RWM1 + Receive Word Mask + 1 + 1 + read-write + + + 0 + Word N is enabled. + #0 + + + 1 + Word N is masked. + #1 + + + + + RWM2 + Receive Word Mask + 2 + 1 + read-write + + + 0 + Word N is enabled. + #0 + + + 1 + Word N is masked. + #1 + + + + + RWM3 + Receive Word Mask + 3 + 1 + read-write + + + 0 + Word N is enabled. + #0 + + + 1 + Word N is masked. + #1 + + + + + RWM4 + Receive Word Mask + 4 + 1 + read-write + + + 0 + Word N is enabled. + #0 + + + 1 + Word N is masked. + #1 + + + + + RWM5 + Receive Word Mask + 5 + 1 + read-write + + + 0 + Word N is enabled. + #0 + + + 1 + Word N is masked. + #1 + + + + + RWM6 + Receive Word Mask + 6 + 1 + read-write + + + 0 + Word N is enabled. + #0 + + + 1 + Word N is masked. + #1 + + + + + RWM7 + Receive Word Mask + 7 + 1 + read-write + + + 0 + Word N is enabled. + #0 + + + 1 + Word N is masked. + #1 + + + + + RWM8 + Receive Word Mask + 8 + 1 + read-write + + + 0 + Word N is enabled. + #0 + + + 1 + Word N is masked. + #1 + + + + + RWM9 + Receive Word Mask + 9 + 1 + read-write + + + 0 + Word N is enabled. + #0 + + + 1 + Word N is masked. + #1 + + + + + RWM10 + Receive Word Mask + 10 + 1 + read-write + + + 0 + Word N is enabled. + #0 + + + 1 + Word N is masked. + #1 + + + + + RWM11 + Receive Word Mask + 11 + 1 + read-write + + + 0 + Word N is enabled. + #0 + + + 1 + Word N is masked. + #1 + + + + + RWM12 + Receive Word Mask + 12 + 1 + read-write + + + 0 + Word N is enabled. + #0 + + + 1 + Word N is masked. + #1 + + + + + RWM13 + Receive Word Mask + 13 + 1 + read-write + + + 0 + Word N is enabled. + #0 + + + 1 + Word N is masked. + #1 + + + + + RWM14 + Receive Word Mask + 14 + 1 + read-write + + + 0 + Word N is enabled. + #0 + + + 1 + Word N is masked. + #1 + + + + + RWM15 + Receive Word Mask + 15 + 1 + read-write + + + 0 + Word N is enabled. + #0 + + + 1 + Word N is masked. + #1 + + + + + RWM16 + Receive Word Mask + 16 + 1 + read-write + + + 0 + Word N is enabled. + #0 + + + 1 + Word N is masked. + #1 + + + + + RWM17 + Receive Word Mask + 17 + 1 + read-write + + + 0 + Word N is enabled. + #0 + + + 1 + Word N is masked. + #1 + + + + + RWM18 + Receive Word Mask + 18 + 1 + read-write + + + 0 + Word N is enabled. + #0 + + + 1 + Word N is masked. + #1 + + + + + RWM19 + Receive Word Mask + 19 + 1 + read-write + + + 0 + Word N is enabled. + #0 + + + 1 + Word N is masked. + #1 + + + + + RWM20 + Receive Word Mask + 20 + 1 + read-write + + + 0 + Word N is enabled. + #0 + + + 1 + Word N is masked. + #1 + + + + + RWM21 + Receive Word Mask + 21 + 1 + read-write + + + 0 + Word N is enabled. + #0 + + + 1 + Word N is masked. + #1 + + + + + RWM22 + Receive Word Mask + 22 + 1 + read-write + + + 0 + Word N is enabled. + #0 + + + 1 + Word N is masked. + #1 + + + + + RWM23 + Receive Word Mask + 23 + 1 + read-write + + + 0 + Word N is enabled. + #0 + + + 1 + Word N is masked. + #1 + + + + + RWM24 + Receive Word Mask + 24 + 1 + read-write + + + 0 + Word N is enabled. + #0 + + + 1 + Word N is masked. + #1 + + + + + RWM25 + Receive Word Mask + 25 + 1 + read-write + + + 0 + Word N is enabled. + #0 + + + 1 + Word N is masked. + #1 + + + + + RWM26 + Receive Word Mask + 26 + 1 + read-write + + + 0 + Word N is enabled. + #0 + + + 1 + Word N is masked. + #1 + + + + + RWM27 + Receive Word Mask + 27 + 1 + read-write + + + 0 + Word N is enabled. + #0 + + + 1 + Word N is masked. + #1 + + + + + RWM28 + Receive Word Mask + 28 + 1 + read-write + + + 0 + Word N is enabled. + #0 + + + 1 + Word N is masked. + #1 + + + + + RWM29 + Receive Word Mask + 29 + 1 + read-write + + + 0 + Word N is enabled. + #0 + + + 1 + Word N is masked. + #1 + + + + + RWM30 + Receive Word Mask + 30 + 1 + read-write + + + 0 + Word N is enabled. + #0 + + + 1 + Word N is masked. + #1 + + + + + RWM31 + Receive Word Mask + 31 + 1 read-write @@ -34543,10 +40358,10 @@ 0xFFFFFFFF - EN + EN0 PDB Channel Pre-Trigger Enable 0 - 8 + 1 read-write @@ -34562,10 +40377,143 @@ - TOS + EN1 + PDB Channel Pre-Trigger Enable + 1 + 1 + read-write + + + 0 + PDB channel's corresponding pre-trigger disabled. + #0 + + + 1 + PDB channel's corresponding pre-trigger enabled. + #1 + + + + + EN2 + PDB Channel Pre-Trigger Enable + 2 + 1 + read-write + + + 0 + PDB channel's corresponding pre-trigger disabled. + #0 + + + 1 + PDB channel's corresponding pre-trigger enabled. + #1 + + + + + EN3 + PDB Channel Pre-Trigger Enable + 3 + 1 + read-write + + + 0 + PDB channel's corresponding pre-trigger disabled. + #0 + + + 1 + PDB channel's corresponding pre-trigger enabled. + #1 + + + + + EN4 + PDB Channel Pre-Trigger Enable + 4 + 1 + read-write + + + 0 + PDB channel's corresponding pre-trigger disabled. + #0 + + + 1 + PDB channel's corresponding pre-trigger enabled. + #1 + + + + + EN5 + PDB Channel Pre-Trigger Enable + 5 + 1 + read-write + + + 0 + PDB channel's corresponding pre-trigger disabled. + #0 + + + 1 + PDB channel's corresponding pre-trigger enabled. + #1 + + + + + EN6 + PDB Channel Pre-Trigger Enable + 6 + 1 + read-write + + + 0 + PDB channel's corresponding pre-trigger disabled. + #0 + + + 1 + PDB channel's corresponding pre-trigger enabled. + #1 + + + + + EN7 + PDB Channel Pre-Trigger Enable + 7 + 1 + read-write + + + 0 + PDB channel's corresponding pre-trigger disabled. + #0 + + + 1 + PDB channel's corresponding pre-trigger enabled. + #1 + + + + + TOS0 PDB Channel Pre-Trigger Output Select 8 - 8 + 1 read-write @@ -34581,10 +40529,276 @@ - BB + TOS1 + PDB Channel Pre-Trigger Output Select + 9 + 1 + read-write + + + 0 + PDB channel's corresponding pre-trigger is in bypassed mode. The pre-trigger asserts one peripheral clock cycle after a rising edge is detected on selected trigger input source or software trigger is selected and SWTRIG is written with 1. + #0 + + + 1 + PDB channel's corresponding pre-trigger asserts when the counter reaches the channel delay register and one peripheral clock cycle after a rising edge is detected on selected trigger input source or software trigger is selected and SETRIG is written with 1. + #1 + + + + + TOS2 + PDB Channel Pre-Trigger Output Select + 10 + 1 + read-write + + + 0 + PDB channel's corresponding pre-trigger is in bypassed mode. The pre-trigger asserts one peripheral clock cycle after a rising edge is detected on selected trigger input source or software trigger is selected and SWTRIG is written with 1. + #0 + + + 1 + PDB channel's corresponding pre-trigger asserts when the counter reaches the channel delay register and one peripheral clock cycle after a rising edge is detected on selected trigger input source or software trigger is selected and SETRIG is written with 1. + #1 + + + + + TOS3 + PDB Channel Pre-Trigger Output Select + 11 + 1 + read-write + + + 0 + PDB channel's corresponding pre-trigger is in bypassed mode. The pre-trigger asserts one peripheral clock cycle after a rising edge is detected on selected trigger input source or software trigger is selected and SWTRIG is written with 1. + #0 + + + 1 + PDB channel's corresponding pre-trigger asserts when the counter reaches the channel delay register and one peripheral clock cycle after a rising edge is detected on selected trigger input source or software trigger is selected and SETRIG is written with 1. + #1 + + + + + TOS4 + PDB Channel Pre-Trigger Output Select + 12 + 1 + read-write + + + 0 + PDB channel's corresponding pre-trigger is in bypassed mode. The pre-trigger asserts one peripheral clock cycle after a rising edge is detected on selected trigger input source or software trigger is selected and SWTRIG is written with 1. + #0 + + + 1 + PDB channel's corresponding pre-trigger asserts when the counter reaches the channel delay register and one peripheral clock cycle after a rising edge is detected on selected trigger input source or software trigger is selected and SETRIG is written with 1. + #1 + + + + + TOS5 + PDB Channel Pre-Trigger Output Select + 13 + 1 + read-write + + + 0 + PDB channel's corresponding pre-trigger is in bypassed mode. The pre-trigger asserts one peripheral clock cycle after a rising edge is detected on selected trigger input source or software trigger is selected and SWTRIG is written with 1. + #0 + + + 1 + PDB channel's corresponding pre-trigger asserts when the counter reaches the channel delay register and one peripheral clock cycle after a rising edge is detected on selected trigger input source or software trigger is selected and SETRIG is written with 1. + #1 + + + + + TOS6 + PDB Channel Pre-Trigger Output Select + 14 + 1 + read-write + + + 0 + PDB channel's corresponding pre-trigger is in bypassed mode. The pre-trigger asserts one peripheral clock cycle after a rising edge is detected on selected trigger input source or software trigger is selected and SWTRIG is written with 1. + #0 + + + 1 + PDB channel's corresponding pre-trigger asserts when the counter reaches the channel delay register and one peripheral clock cycle after a rising edge is detected on selected trigger input source or software trigger is selected and SETRIG is written with 1. + #1 + + + + + TOS7 + PDB Channel Pre-Trigger Output Select + 15 + 1 + read-write + + + 0 + PDB channel's corresponding pre-trigger is in bypassed mode. The pre-trigger asserts one peripheral clock cycle after a rising edge is detected on selected trigger input source or software trigger is selected and SWTRIG is written with 1. + #0 + + + 1 + PDB channel's corresponding pre-trigger asserts when the counter reaches the channel delay register and one peripheral clock cycle after a rising edge is detected on selected trigger input source or software trigger is selected and SETRIG is written with 1. + #1 + + + + + BB0 PDB Channel Pre-Trigger Back-to-Back Operation Enable 16 - 8 + 1 + read-write + + + 0 + PDB channel's corresponding pre-trigger back-to-back operation disabled. + #0 + + + 1 + PDB channel's corresponding pre-trigger back-to-back operation enabled. + #1 + + + + + BB1 + PDB Channel Pre-Trigger Back-to-Back Operation Enable + 17 + 1 + read-write + + + 0 + PDB channel's corresponding pre-trigger back-to-back operation disabled. + #0 + + + 1 + PDB channel's corresponding pre-trigger back-to-back operation enabled. + #1 + + + + + BB2 + PDB Channel Pre-Trigger Back-to-Back Operation Enable + 18 + 1 + read-write + + + 0 + PDB channel's corresponding pre-trigger back-to-back operation disabled. + #0 + + + 1 + PDB channel's corresponding pre-trigger back-to-back operation enabled. + #1 + + + + + BB3 + PDB Channel Pre-Trigger Back-to-Back Operation Enable + 19 + 1 + read-write + + + 0 + PDB channel's corresponding pre-trigger back-to-back operation disabled. + #0 + + + 1 + PDB channel's corresponding pre-trigger back-to-back operation enabled. + #1 + + + + + BB4 + PDB Channel Pre-Trigger Back-to-Back Operation Enable + 20 + 1 + read-write + + + 0 + PDB channel's corresponding pre-trigger back-to-back operation disabled. + #0 + + + 1 + PDB channel's corresponding pre-trigger back-to-back operation enabled. + #1 + + + + + BB5 + PDB Channel Pre-Trigger Back-to-Back Operation Enable + 21 + 1 + read-write + + + 0 + PDB channel's corresponding pre-trigger back-to-back operation disabled. + #0 + + + 1 + PDB channel's corresponding pre-trigger back-to-back operation enabled. + #1 + + + + + BB6 + PDB Channel Pre-Trigger Back-to-Back Operation Enable + 22 + 1 + read-write + + + 0 + PDB channel's corresponding pre-trigger back-to-back operation disabled. + #0 + + + 1 + PDB channel's corresponding pre-trigger back-to-back operation enabled. + #1 + + + + + BB7 + PDB Channel Pre-Trigger Back-to-Back Operation Enable + 23 + 1 read-write @@ -34614,10 +40828,143 @@ 0xFFFFFFFF - ERR + ERR0 PDB Channel Sequence Error Flags 0 - 8 + 1 + read-write + + + 0 + Sequence error not detected on PDB channel's corresponding pre-trigger. + #0 + + + 1 + Sequence error detected on PDB channel's corresponding pre-trigger. ADCn block can be triggered for a conversion by one pre-trigger from PDB channel n. When one conversion, which is triggered by one of the pre-triggers from PDB channel n, is in progress, new trigger from PDB channel's corresponding pre-trigger m cannot be accepted by ADCn, and ERR[m] is set. Writing 0's to clear the sequence error flags. + #1 + + + + + ERR1 + PDB Channel Sequence Error Flags + 1 + 1 + read-write + + + 0 + Sequence error not detected on PDB channel's corresponding pre-trigger. + #0 + + + 1 + Sequence error detected on PDB channel's corresponding pre-trigger. ADCn block can be triggered for a conversion by one pre-trigger from PDB channel n. When one conversion, which is triggered by one of the pre-triggers from PDB channel n, is in progress, new trigger from PDB channel's corresponding pre-trigger m cannot be accepted by ADCn, and ERR[m] is set. Writing 0's to clear the sequence error flags. + #1 + + + + + ERR2 + PDB Channel Sequence Error Flags + 2 + 1 + read-write + + + 0 + Sequence error not detected on PDB channel's corresponding pre-trigger. + #0 + + + 1 + Sequence error detected on PDB channel's corresponding pre-trigger. ADCn block can be triggered for a conversion by one pre-trigger from PDB channel n. When one conversion, which is triggered by one of the pre-triggers from PDB channel n, is in progress, new trigger from PDB channel's corresponding pre-trigger m cannot be accepted by ADCn, and ERR[m] is set. Writing 0's to clear the sequence error flags. + #1 + + + + + ERR3 + PDB Channel Sequence Error Flags + 3 + 1 + read-write + + + 0 + Sequence error not detected on PDB channel's corresponding pre-trigger. + #0 + + + 1 + Sequence error detected on PDB channel's corresponding pre-trigger. ADCn block can be triggered for a conversion by one pre-trigger from PDB channel n. When one conversion, which is triggered by one of the pre-triggers from PDB channel n, is in progress, new trigger from PDB channel's corresponding pre-trigger m cannot be accepted by ADCn, and ERR[m] is set. Writing 0's to clear the sequence error flags. + #1 + + + + + ERR4 + PDB Channel Sequence Error Flags + 4 + 1 + read-write + + + 0 + Sequence error not detected on PDB channel's corresponding pre-trigger. + #0 + + + 1 + Sequence error detected on PDB channel's corresponding pre-trigger. ADCn block can be triggered for a conversion by one pre-trigger from PDB channel n. When one conversion, which is triggered by one of the pre-triggers from PDB channel n, is in progress, new trigger from PDB channel's corresponding pre-trigger m cannot be accepted by ADCn, and ERR[m] is set. Writing 0's to clear the sequence error flags. + #1 + + + + + ERR5 + PDB Channel Sequence Error Flags + 5 + 1 + read-write + + + 0 + Sequence error not detected on PDB channel's corresponding pre-trigger. + #0 + + + 1 + Sequence error detected on PDB channel's corresponding pre-trigger. ADCn block can be triggered for a conversion by one pre-trigger from PDB channel n. When one conversion, which is triggered by one of the pre-triggers from PDB channel n, is in progress, new trigger from PDB channel's corresponding pre-trigger m cannot be accepted by ADCn, and ERR[m] is set. Writing 0's to clear the sequence error flags. + #1 + + + + + ERR6 + PDB Channel Sequence Error Flags + 6 + 1 + read-write + + + 0 + Sequence error not detected on PDB channel's corresponding pre-trigger. + #0 + + + 1 + Sequence error detected on PDB channel's corresponding pre-trigger. ADCn block can be triggered for a conversion by one pre-trigger from PDB channel n. When one conversion, which is triggered by one of the pre-triggers from PDB channel n, is in progress, new trigger from PDB channel's corresponding pre-trigger m cannot be accepted by ADCn, and ERR[m] is set. Writing 0's to clear the sequence error flags. + #1 + + + + + ERR7 + PDB Channel Sequence Error Flags + 7 + 1 read-write @@ -34766,10 +41113,143 @@ 0xFFFFFFFF - POEN + POEN0 PDB Pulse-Out Enable 0 - 8 + 1 + read-write + + + 0 + PDB Pulse-Out disabled + #0 + + + 1 + PDB Pulse-Out enabled + #1 + + + + + POEN1 + PDB Pulse-Out Enable + 1 + 1 + read-write + + + 0 + PDB Pulse-Out disabled + #0 + + + 1 + PDB Pulse-Out enabled + #1 + + + + + POEN2 + PDB Pulse-Out Enable + 2 + 1 + read-write + + + 0 + PDB Pulse-Out disabled + #0 + + + 1 + PDB Pulse-Out enabled + #1 + + + + + POEN3 + PDB Pulse-Out Enable + 3 + 1 + read-write + + + 0 + PDB Pulse-Out disabled + #0 + + + 1 + PDB Pulse-Out enabled + #1 + + + + + POEN4 + PDB Pulse-Out Enable + 4 + 1 + read-write + + + 0 + PDB Pulse-Out disabled + #0 + + + 1 + PDB Pulse-Out enabled + #1 + + + + + POEN5 + PDB Pulse-Out Enable + 5 + 1 + read-write + + + 0 + PDB Pulse-Out disabled + #0 + + + 1 + PDB Pulse-Out enabled + #1 + + + + + POEN6 + PDB Pulse-Out Enable + 6 + 1 + read-write + + + 0 + PDB Pulse-Out disabled + #0 + + + 1 + PDB Pulse-Out enabled + #1 + + + + + POEN7 + PDB Pulse-Out Enable + 7 + 1 read-write @@ -35186,7 +41666,7 @@ Timer Overflow Flag 7 1 - read-only + read-write 0 @@ -35321,7 +41801,7 @@ Channel Flag 7 1 - read-only + read-write 0 @@ -36897,7 +43377,7 @@ Channel Trigger Flag 7 1 - read-only + read-write 0 @@ -37090,7 +43570,7 @@ Fault Detection Flag 0 0 1 - read-only + read-write 0 @@ -37109,7 +43589,7 @@ Fault Detection Flag 1 1 1 - read-only + read-write 0 @@ -37128,7 +43608,7 @@ Fault Detection Flag 2 2 1 - read-only + read-write 0 @@ -37147,7 +43627,7 @@ Fault Detection Flag 3 3 1 - read-only + read-write 0 @@ -37204,7 +43684,7 @@ Fault Detection Flag 7 1 - read-only + read-write 0 @@ -38770,7 +45250,7 @@ Timer Overflow Flag 7 1 - read-only + read-write 0 @@ -38905,7 +45385,7 @@ Channel Flag 7 1 - read-only + read-write 0 @@ -40481,7 +46961,7 @@ Channel Trigger Flag 7 1 - read-only + read-write 0 @@ -40674,7 +47154,7 @@ Fault Detection Flag 0 0 1 - read-only + read-write 0 @@ -40693,7 +47173,7 @@ Fault Detection Flag 1 1 1 - read-only + read-write 0 @@ -40712,7 +47192,7 @@ Fault Detection Flag 2 2 1 - read-only + read-write 0 @@ -40731,7 +47211,7 @@ Fault Detection Flag 3 3 1 - read-only + read-write 0 @@ -40788,7 +47268,7 @@ Fault Detection Flag 7 1 - read-only + read-write 0 @@ -42354,7 +48834,7 @@ Timer Overflow Flag 7 1 - read-only + read-write 0 @@ -42489,7 +48969,7 @@ Channel Flag 7 1 - read-only + read-write 0 @@ -44065,7 +50545,7 @@ Channel Trigger Flag 7 1 - read-only + read-write 0 @@ -44258,7 +50738,7 @@ Fault Detection Flag 0 0 1 - read-only + read-write 0 @@ -44277,7 +50757,7 @@ Fault Detection Flag 1 1 1 - read-only + read-write 0 @@ -44296,7 +50776,7 @@ Fault Detection Flag 2 2 1 - read-only + read-write 0 @@ -44315,7 +50795,7 @@ Fault Detection Flag 3 3 1 - read-only + read-write 0 @@ -44372,7 +50852,7 @@ Fault Detection Flag 7 1 - read-only + read-write 0 @@ -45938,7 +52418,7 @@ Timer Overflow Flag 7 1 - read-only + read-write 0 @@ -46073,7 +52553,7 @@ Channel Flag 7 1 - read-only + read-write 0 @@ -47649,7 +54129,7 @@ Channel Trigger Flag 7 1 - read-only + read-write 0 @@ -47842,7 +54322,7 @@ Fault Detection Flag 0 0 1 - read-only + read-write 0 @@ -47861,7 +54341,7 @@ Fault Detection Flag 1 1 1 - read-only + read-write 0 @@ -47880,7 +54360,7 @@ Fault Detection Flag 2 2 1 - read-only + read-write 0 @@ -47899,7 +54379,7 @@ Fault Detection Flag 3 3 1 - read-only + read-write 0 @@ -47956,7 +54436,7 @@ Fault Detection Flag 7 1 - read-only + read-write 0 @@ -64619,10 +71099,295 @@ write-only - GPWE + GPWE0 Global Pin Write Enable 16 - 16 + 1 + write-only + + + 0 + Corresponding Pin Control Register is not updated with the value in GPWD. + #0 + + + 1 + Corresponding Pin Control Register is updated with the value in GPWD. + #1 + + + + + GPWE1 + Global Pin Write Enable + 17 + 1 + write-only + + + 0 + Corresponding Pin Control Register is not updated with the value in GPWD. + #0 + + + 1 + Corresponding Pin Control Register is updated with the value in GPWD. + #1 + + + + + GPWE2 + Global Pin Write Enable + 18 + 1 + write-only + + + 0 + Corresponding Pin Control Register is not updated with the value in GPWD. + #0 + + + 1 + Corresponding Pin Control Register is updated with the value in GPWD. + #1 + + + + + GPWE3 + Global Pin Write Enable + 19 + 1 + write-only + + + 0 + Corresponding Pin Control Register is not updated with the value in GPWD. + #0 + + + 1 + Corresponding Pin Control Register is updated with the value in GPWD. + #1 + + + + + GPWE4 + Global Pin Write Enable + 20 + 1 + write-only + + + 0 + Corresponding Pin Control Register is not updated with the value in GPWD. + #0 + + + 1 + Corresponding Pin Control Register is updated with the value in GPWD. + #1 + + + + + GPWE5 + Global Pin Write Enable + 21 + 1 + write-only + + + 0 + Corresponding Pin Control Register is not updated with the value in GPWD. + #0 + + + 1 + Corresponding Pin Control Register is updated with the value in GPWD. + #1 + + + + + GPWE6 + Global Pin Write Enable + 22 + 1 + write-only + + + 0 + Corresponding Pin Control Register is not updated with the value in GPWD. + #0 + + + 1 + Corresponding Pin Control Register is updated with the value in GPWD. + #1 + + + + + GPWE7 + Global Pin Write Enable + 23 + 1 + write-only + + + 0 + Corresponding Pin Control Register is not updated with the value in GPWD. + #0 + + + 1 + Corresponding Pin Control Register is updated with the value in GPWD. + #1 + + + + + GPWE8 + Global Pin Write Enable + 24 + 1 + write-only + + + 0 + Corresponding Pin Control Register is not updated with the value in GPWD. + #0 + + + 1 + Corresponding Pin Control Register is updated with the value in GPWD. + #1 + + + + + GPWE9 + Global Pin Write Enable + 25 + 1 + write-only + + + 0 + Corresponding Pin Control Register is not updated with the value in GPWD. + #0 + + + 1 + Corresponding Pin Control Register is updated with the value in GPWD. + #1 + + + + + GPWE10 + Global Pin Write Enable + 26 + 1 + write-only + + + 0 + Corresponding Pin Control Register is not updated with the value in GPWD. + #0 + + + 1 + Corresponding Pin Control Register is updated with the value in GPWD. + #1 + + + + + GPWE11 + Global Pin Write Enable + 27 + 1 + write-only + + + 0 + Corresponding Pin Control Register is not updated with the value in GPWD. + #0 + + + 1 + Corresponding Pin Control Register is updated with the value in GPWD. + #1 + + + + + GPWE12 + Global Pin Write Enable + 28 + 1 + write-only + + + 0 + Corresponding Pin Control Register is not updated with the value in GPWD. + #0 + + + 1 + Corresponding Pin Control Register is updated with the value in GPWD. + #1 + + + + + GPWE13 + Global Pin Write Enable + 29 + 1 + write-only + + + 0 + Corresponding Pin Control Register is not updated with the value in GPWD. + #0 + + + 1 + Corresponding Pin Control Register is updated with the value in GPWD. + #1 + + + + + GPWE14 + Global Pin Write Enable + 30 + 1 + write-only + + + 0 + Corresponding Pin Control Register is not updated with the value in GPWD. + #0 + + + 1 + Corresponding Pin Control Register is updated with the value in GPWD. + #1 + + + + + GPWE15 + Global Pin Write Enable + 31 + 1 write-only @@ -64656,10 +71421,295 @@ write-only - GPWE + GPWE0 Global Pin Write Enable 16 - 16 + 1 + write-only + + + 0 + Corresponding Pin Control Register is not updated with the value in GPWD. + #0 + + + 1 + Corresponding Pin Control Register is updated with the value in GPWD. + #1 + + + + + GPWE1 + Global Pin Write Enable + 17 + 1 + write-only + + + 0 + Corresponding Pin Control Register is not updated with the value in GPWD. + #0 + + + 1 + Corresponding Pin Control Register is updated with the value in GPWD. + #1 + + + + + GPWE2 + Global Pin Write Enable + 18 + 1 + write-only + + + 0 + Corresponding Pin Control Register is not updated with the value in GPWD. + #0 + + + 1 + Corresponding Pin Control Register is updated with the value in GPWD. + #1 + + + + + GPWE3 + Global Pin Write Enable + 19 + 1 + write-only + + + 0 + Corresponding Pin Control Register is not updated with the value in GPWD. + #0 + + + 1 + Corresponding Pin Control Register is updated with the value in GPWD. + #1 + + + + + GPWE4 + Global Pin Write Enable + 20 + 1 + write-only + + + 0 + Corresponding Pin Control Register is not updated with the value in GPWD. + #0 + + + 1 + Corresponding Pin Control Register is updated with the value in GPWD. + #1 + + + + + GPWE5 + Global Pin Write Enable + 21 + 1 + write-only + + + 0 + Corresponding Pin Control Register is not updated with the value in GPWD. + #0 + + + 1 + Corresponding Pin Control Register is updated with the value in GPWD. + #1 + + + + + GPWE6 + Global Pin Write Enable + 22 + 1 + write-only + + + 0 + Corresponding Pin Control Register is not updated with the value in GPWD. + #0 + + + 1 + Corresponding Pin Control Register is updated with the value in GPWD. + #1 + + + + + GPWE7 + Global Pin Write Enable + 23 + 1 + write-only + + + 0 + Corresponding Pin Control Register is not updated with the value in GPWD. + #0 + + + 1 + Corresponding Pin Control Register is updated with the value in GPWD. + #1 + + + + + GPWE8 + Global Pin Write Enable + 24 + 1 + write-only + + + 0 + Corresponding Pin Control Register is not updated with the value in GPWD. + #0 + + + 1 + Corresponding Pin Control Register is updated with the value in GPWD. + #1 + + + + + GPWE9 + Global Pin Write Enable + 25 + 1 + write-only + + + 0 + Corresponding Pin Control Register is not updated with the value in GPWD. + #0 + + + 1 + Corresponding Pin Control Register is updated with the value in GPWD. + #1 + + + + + GPWE10 + Global Pin Write Enable + 26 + 1 + write-only + + + 0 + Corresponding Pin Control Register is not updated with the value in GPWD. + #0 + + + 1 + Corresponding Pin Control Register is updated with the value in GPWD. + #1 + + + + + GPWE11 + Global Pin Write Enable + 27 + 1 + write-only + + + 0 + Corresponding Pin Control Register is not updated with the value in GPWD. + #0 + + + 1 + Corresponding Pin Control Register is updated with the value in GPWD. + #1 + + + + + GPWE12 + Global Pin Write Enable + 28 + 1 + write-only + + + 0 + Corresponding Pin Control Register is not updated with the value in GPWD. + #0 + + + 1 + Corresponding Pin Control Register is updated with the value in GPWD. + #1 + + + + + GPWE13 + Global Pin Write Enable + 29 + 1 + write-only + + + 0 + Corresponding Pin Control Register is not updated with the value in GPWD. + #0 + + + 1 + Corresponding Pin Control Register is updated with the value in GPWD. + #1 + + + + + GPWE14 + Global Pin Write Enable + 30 + 1 + write-only + + + 0 + Corresponding Pin Control Register is not updated with the value in GPWD. + #0 + + + 1 + Corresponding Pin Control Register is updated with the value in GPWD. + #1 + + + + + GPWE15 + Global Pin Write Enable + 31 + 1 write-only @@ -64686,10 +71736,599 @@ 0xFFFFFFFF - ISF + ISF0 Interrupt Status Flag 0 - 32 + 1 + read-write + + + 0 + Configured interrupt is not detected. + #0 + + + 1 + Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. + #1 + + + + + ISF1 + Interrupt Status Flag + 1 + 1 + read-write + + + 0 + Configured interrupt is not detected. + #0 + + + 1 + Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. + #1 + + + + + ISF2 + Interrupt Status Flag + 2 + 1 + read-write + + + 0 + Configured interrupt is not detected. + #0 + + + 1 + Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. + #1 + + + + + ISF3 + Interrupt Status Flag + 3 + 1 + read-write + + + 0 + Configured interrupt is not detected. + #0 + + + 1 + Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. + #1 + + + + + ISF4 + Interrupt Status Flag + 4 + 1 + read-write + + + 0 + Configured interrupt is not detected. + #0 + + + 1 + Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. + #1 + + + + + ISF5 + Interrupt Status Flag + 5 + 1 + read-write + + + 0 + Configured interrupt is not detected. + #0 + + + 1 + Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. + #1 + + + + + ISF6 + Interrupt Status Flag + 6 + 1 + read-write + + + 0 + Configured interrupt is not detected. + #0 + + + 1 + Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. + #1 + + + + + ISF7 + Interrupt Status Flag + 7 + 1 + read-write + + + 0 + Configured interrupt is not detected. + #0 + + + 1 + Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. + #1 + + + + + ISF8 + Interrupt Status Flag + 8 + 1 + read-write + + + 0 + Configured interrupt is not detected. + #0 + + + 1 + Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. + #1 + + + + + ISF9 + Interrupt Status Flag + 9 + 1 + read-write + + + 0 + Configured interrupt is not detected. + #0 + + + 1 + Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. + #1 + + + + + ISF10 + Interrupt Status Flag + 10 + 1 + read-write + + + 0 + Configured interrupt is not detected. + #0 + + + 1 + Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. + #1 + + + + + ISF11 + Interrupt Status Flag + 11 + 1 + read-write + + + 0 + Configured interrupt is not detected. + #0 + + + 1 + Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. + #1 + + + + + ISF12 + Interrupt Status Flag + 12 + 1 + read-write + + + 0 + Configured interrupt is not detected. + #0 + + + 1 + Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. + #1 + + + + + ISF13 + Interrupt Status Flag + 13 + 1 + read-write + + + 0 + Configured interrupt is not detected. + #0 + + + 1 + Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. + #1 + + + + + ISF14 + Interrupt Status Flag + 14 + 1 + read-write + + + 0 + Configured interrupt is not detected. + #0 + + + 1 + Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. + #1 + + + + + ISF15 + Interrupt Status Flag + 15 + 1 + read-write + + + 0 + Configured interrupt is not detected. + #0 + + + 1 + Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. + #1 + + + + + ISF16 + Interrupt Status Flag + 16 + 1 + read-write + + + 0 + Configured interrupt is not detected. + #0 + + + 1 + Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. + #1 + + + + + ISF17 + Interrupt Status Flag + 17 + 1 + read-write + + + 0 + Configured interrupt is not detected. + #0 + + + 1 + Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. + #1 + + + + + ISF18 + Interrupt Status Flag + 18 + 1 + read-write + + + 0 + Configured interrupt is not detected. + #0 + + + 1 + Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. + #1 + + + + + ISF19 + Interrupt Status Flag + 19 + 1 + read-write + + + 0 + Configured interrupt is not detected. + #0 + + + 1 + Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. + #1 + + + + + ISF20 + Interrupt Status Flag + 20 + 1 + read-write + + + 0 + Configured interrupt is not detected. + #0 + + + 1 + Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. + #1 + + + + + ISF21 + Interrupt Status Flag + 21 + 1 + read-write + + + 0 + Configured interrupt is not detected. + #0 + + + 1 + Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. + #1 + + + + + ISF22 + Interrupt Status Flag + 22 + 1 + read-write + + + 0 + Configured interrupt is not detected. + #0 + + + 1 + Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. + #1 + + + + + ISF23 + Interrupt Status Flag + 23 + 1 + read-write + + + 0 + Configured interrupt is not detected. + #0 + + + 1 + Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. + #1 + + + + + ISF24 + Interrupt Status Flag + 24 + 1 + read-write + + + 0 + Configured interrupt is not detected. + #0 + + + 1 + Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. + #1 + + + + + ISF25 + Interrupt Status Flag + 25 + 1 + read-write + + + 0 + Configured interrupt is not detected. + #0 + + + 1 + Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. + #1 + + + + + ISF26 + Interrupt Status Flag + 26 + 1 + read-write + + + 0 + Configured interrupt is not detected. + #0 + + + 1 + Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. + #1 + + + + + ISF27 + Interrupt Status Flag + 27 + 1 + read-write + + + 0 + Configured interrupt is not detected. + #0 + + + 1 + Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. + #1 + + + + + ISF28 + Interrupt Status Flag + 28 + 1 + read-write + + + 0 + Configured interrupt is not detected. + #0 + + + 1 + Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. + #1 + + + + + ISF29 + Interrupt Status Flag + 29 + 1 + read-write + + + 0 + Configured interrupt is not detected. + #0 + + + 1 + Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. + #1 + + + + + ISF30 + Interrupt Status Flag + 30 + 1 + read-write + + + 0 + Configured interrupt is not detected. + #0 + + + 1 + Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. + #1 + + + + + ISF31 + Interrupt Status Flag + 31 + 1 read-write @@ -73253,10 +80892,295 @@ write-only - GPWE + GPWE0 Global Pin Write Enable 16 - 16 + 1 + write-only + + + 0 + Corresponding Pin Control Register is not updated with the value in GPWD. + #0 + + + 1 + Corresponding Pin Control Register is updated with the value in GPWD. + #1 + + + + + GPWE1 + Global Pin Write Enable + 17 + 1 + write-only + + + 0 + Corresponding Pin Control Register is not updated with the value in GPWD. + #0 + + + 1 + Corresponding Pin Control Register is updated with the value in GPWD. + #1 + + + + + GPWE2 + Global Pin Write Enable + 18 + 1 + write-only + + + 0 + Corresponding Pin Control Register is not updated with the value in GPWD. + #0 + + + 1 + Corresponding Pin Control Register is updated with the value in GPWD. + #1 + + + + + GPWE3 + Global Pin Write Enable + 19 + 1 + write-only + + + 0 + Corresponding Pin Control Register is not updated with the value in GPWD. + #0 + + + 1 + Corresponding Pin Control Register is updated with the value in GPWD. + #1 + + + + + GPWE4 + Global Pin Write Enable + 20 + 1 + write-only + + + 0 + Corresponding Pin Control Register is not updated with the value in GPWD. + #0 + + + 1 + Corresponding Pin Control Register is updated with the value in GPWD. + #1 + + + + + GPWE5 + Global Pin Write Enable + 21 + 1 + write-only + + + 0 + Corresponding Pin Control Register is not updated with the value in GPWD. + #0 + + + 1 + Corresponding Pin Control Register is updated with the value in GPWD. + #1 + + + + + GPWE6 + Global Pin Write Enable + 22 + 1 + write-only + + + 0 + Corresponding Pin Control Register is not updated with the value in GPWD. + #0 + + + 1 + Corresponding Pin Control Register is updated with the value in GPWD. + #1 + + + + + GPWE7 + Global Pin Write Enable + 23 + 1 + write-only + + + 0 + Corresponding Pin Control Register is not updated with the value in GPWD. + #0 + + + 1 + Corresponding Pin Control Register is updated with the value in GPWD. + #1 + + + + + GPWE8 + Global Pin Write Enable + 24 + 1 + write-only + + + 0 + Corresponding Pin Control Register is not updated with the value in GPWD. + #0 + + + 1 + Corresponding Pin Control Register is updated with the value in GPWD. + #1 + + + + + GPWE9 + Global Pin Write Enable + 25 + 1 + write-only + + + 0 + Corresponding Pin Control Register is not updated with the value in GPWD. + #0 + + + 1 + Corresponding Pin Control Register is updated with the value in GPWD. + #1 + + + + + GPWE10 + Global Pin Write Enable + 26 + 1 + write-only + + + 0 + Corresponding Pin Control Register is not updated with the value in GPWD. + #0 + + + 1 + Corresponding Pin Control Register is updated with the value in GPWD. + #1 + + + + + GPWE11 + Global Pin Write Enable + 27 + 1 + write-only + + + 0 + Corresponding Pin Control Register is not updated with the value in GPWD. + #0 + + + 1 + Corresponding Pin Control Register is updated with the value in GPWD. + #1 + + + + + GPWE12 + Global Pin Write Enable + 28 + 1 + write-only + + + 0 + Corresponding Pin Control Register is not updated with the value in GPWD. + #0 + + + 1 + Corresponding Pin Control Register is updated with the value in GPWD. + #1 + + + + + GPWE13 + Global Pin Write Enable + 29 + 1 + write-only + + + 0 + Corresponding Pin Control Register is not updated with the value in GPWD. + #0 + + + 1 + Corresponding Pin Control Register is updated with the value in GPWD. + #1 + + + + + GPWE14 + Global Pin Write Enable + 30 + 1 + write-only + + + 0 + Corresponding Pin Control Register is not updated with the value in GPWD. + #0 + + + 1 + Corresponding Pin Control Register is updated with the value in GPWD. + #1 + + + + + GPWE15 + Global Pin Write Enable + 31 + 1 write-only @@ -73290,10 +81214,295 @@ write-only - GPWE + GPWE0 Global Pin Write Enable 16 - 16 + 1 + write-only + + + 0 + Corresponding Pin Control Register is not updated with the value in GPWD. + #0 + + + 1 + Corresponding Pin Control Register is updated with the value in GPWD. + #1 + + + + + GPWE1 + Global Pin Write Enable + 17 + 1 + write-only + + + 0 + Corresponding Pin Control Register is not updated with the value in GPWD. + #0 + + + 1 + Corresponding Pin Control Register is updated with the value in GPWD. + #1 + + + + + GPWE2 + Global Pin Write Enable + 18 + 1 + write-only + + + 0 + Corresponding Pin Control Register is not updated with the value in GPWD. + #0 + + + 1 + Corresponding Pin Control Register is updated with the value in GPWD. + #1 + + + + + GPWE3 + Global Pin Write Enable + 19 + 1 + write-only + + + 0 + Corresponding Pin Control Register is not updated with the value in GPWD. + #0 + + + 1 + Corresponding Pin Control Register is updated with the value in GPWD. + #1 + + + + + GPWE4 + Global Pin Write Enable + 20 + 1 + write-only + + + 0 + Corresponding Pin Control Register is not updated with the value in GPWD. + #0 + + + 1 + Corresponding Pin Control Register is updated with the value in GPWD. + #1 + + + + + GPWE5 + Global Pin Write Enable + 21 + 1 + write-only + + + 0 + Corresponding Pin Control Register is not updated with the value in GPWD. + #0 + + + 1 + Corresponding Pin Control Register is updated with the value in GPWD. + #1 + + + + + GPWE6 + Global Pin Write Enable + 22 + 1 + write-only + + + 0 + Corresponding Pin Control Register is not updated with the value in GPWD. + #0 + + + 1 + Corresponding Pin Control Register is updated with the value in GPWD. + #1 + + + + + GPWE7 + Global Pin Write Enable + 23 + 1 + write-only + + + 0 + Corresponding Pin Control Register is not updated with the value in GPWD. + #0 + + + 1 + Corresponding Pin Control Register is updated with the value in GPWD. + #1 + + + + + GPWE8 + Global Pin Write Enable + 24 + 1 + write-only + + + 0 + Corresponding Pin Control Register is not updated with the value in GPWD. + #0 + + + 1 + Corresponding Pin Control Register is updated with the value in GPWD. + #1 + + + + + GPWE9 + Global Pin Write Enable + 25 + 1 + write-only + + + 0 + Corresponding Pin Control Register is not updated with the value in GPWD. + #0 + + + 1 + Corresponding Pin Control Register is updated with the value in GPWD. + #1 + + + + + GPWE10 + Global Pin Write Enable + 26 + 1 + write-only + + + 0 + Corresponding Pin Control Register is not updated with the value in GPWD. + #0 + + + 1 + Corresponding Pin Control Register is updated with the value in GPWD. + #1 + + + + + GPWE11 + Global Pin Write Enable + 27 + 1 + write-only + + + 0 + Corresponding Pin Control Register is not updated with the value in GPWD. + #0 + + + 1 + Corresponding Pin Control Register is updated with the value in GPWD. + #1 + + + + + GPWE12 + Global Pin Write Enable + 28 + 1 + write-only + + + 0 + Corresponding Pin Control Register is not updated with the value in GPWD. + #0 + + + 1 + Corresponding Pin Control Register is updated with the value in GPWD. + #1 + + + + + GPWE13 + Global Pin Write Enable + 29 + 1 + write-only + + + 0 + Corresponding Pin Control Register is not updated with the value in GPWD. + #0 + + + 1 + Corresponding Pin Control Register is updated with the value in GPWD. + #1 + + + + + GPWE14 + Global Pin Write Enable + 30 + 1 + write-only + + + 0 + Corresponding Pin Control Register is not updated with the value in GPWD. + #0 + + + 1 + Corresponding Pin Control Register is updated with the value in GPWD. + #1 + + + + + GPWE15 + Global Pin Write Enable + 31 + 1 write-only @@ -73320,10 +81529,599 @@ 0xFFFFFFFF - ISF + ISF0 Interrupt Status Flag 0 - 32 + 1 + read-write + + + 0 + Configured interrupt is not detected. + #0 + + + 1 + Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. + #1 + + + + + ISF1 + Interrupt Status Flag + 1 + 1 + read-write + + + 0 + Configured interrupt is not detected. + #0 + + + 1 + Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. + #1 + + + + + ISF2 + Interrupt Status Flag + 2 + 1 + read-write + + + 0 + Configured interrupt is not detected. + #0 + + + 1 + Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. + #1 + + + + + ISF3 + Interrupt Status Flag + 3 + 1 + read-write + + + 0 + Configured interrupt is not detected. + #0 + + + 1 + Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. + #1 + + + + + ISF4 + Interrupt Status Flag + 4 + 1 + read-write + + + 0 + Configured interrupt is not detected. + #0 + + + 1 + Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. + #1 + + + + + ISF5 + Interrupt Status Flag + 5 + 1 + read-write + + + 0 + Configured interrupt is not detected. + #0 + + + 1 + Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. + #1 + + + + + ISF6 + Interrupt Status Flag + 6 + 1 + read-write + + + 0 + Configured interrupt is not detected. + #0 + + + 1 + Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. + #1 + + + + + ISF7 + Interrupt Status Flag + 7 + 1 + read-write + + + 0 + Configured interrupt is not detected. + #0 + + + 1 + Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. + #1 + + + + + ISF8 + Interrupt Status Flag + 8 + 1 + read-write + + + 0 + Configured interrupt is not detected. + #0 + + + 1 + Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. + #1 + + + + + ISF9 + Interrupt Status Flag + 9 + 1 + read-write + + + 0 + Configured interrupt is not detected. + #0 + + + 1 + Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. + #1 + + + + + ISF10 + Interrupt Status Flag + 10 + 1 + read-write + + + 0 + Configured interrupt is not detected. + #0 + + + 1 + Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. + #1 + + + + + ISF11 + Interrupt Status Flag + 11 + 1 + read-write + + + 0 + Configured interrupt is not detected. + #0 + + + 1 + Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. + #1 + + + + + ISF12 + Interrupt Status Flag + 12 + 1 + read-write + + + 0 + Configured interrupt is not detected. + #0 + + + 1 + Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. + #1 + + + + + ISF13 + Interrupt Status Flag + 13 + 1 + read-write + + + 0 + Configured interrupt is not detected. + #0 + + + 1 + Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. + #1 + + + + + ISF14 + Interrupt Status Flag + 14 + 1 + read-write + + + 0 + Configured interrupt is not detected. + #0 + + + 1 + Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. + #1 + + + + + ISF15 + Interrupt Status Flag + 15 + 1 + read-write + + + 0 + Configured interrupt is not detected. + #0 + + + 1 + Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. + #1 + + + + + ISF16 + Interrupt Status Flag + 16 + 1 + read-write + + + 0 + Configured interrupt is not detected. + #0 + + + 1 + Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. + #1 + + + + + ISF17 + Interrupt Status Flag + 17 + 1 + read-write + + + 0 + Configured interrupt is not detected. + #0 + + + 1 + Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. + #1 + + + + + ISF18 + Interrupt Status Flag + 18 + 1 + read-write + + + 0 + Configured interrupt is not detected. + #0 + + + 1 + Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. + #1 + + + + + ISF19 + Interrupt Status Flag + 19 + 1 + read-write + + + 0 + Configured interrupt is not detected. + #0 + + + 1 + Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. + #1 + + + + + ISF20 + Interrupt Status Flag + 20 + 1 + read-write + + + 0 + Configured interrupt is not detected. + #0 + + + 1 + Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. + #1 + + + + + ISF21 + Interrupt Status Flag + 21 + 1 + read-write + + + 0 + Configured interrupt is not detected. + #0 + + + 1 + Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. + #1 + + + + + ISF22 + Interrupt Status Flag + 22 + 1 + read-write + + + 0 + Configured interrupt is not detected. + #0 + + + 1 + Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. + #1 + + + + + ISF23 + Interrupt Status Flag + 23 + 1 + read-write + + + 0 + Configured interrupt is not detected. + #0 + + + 1 + Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. + #1 + + + + + ISF24 + Interrupt Status Flag + 24 + 1 + read-write + + + 0 + Configured interrupt is not detected. + #0 + + + 1 + Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. + #1 + + + + + ISF25 + Interrupt Status Flag + 25 + 1 + read-write + + + 0 + Configured interrupt is not detected. + #0 + + + 1 + Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. + #1 + + + + + ISF26 + Interrupt Status Flag + 26 + 1 + read-write + + + 0 + Configured interrupt is not detected. + #0 + + + 1 + Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. + #1 + + + + + ISF27 + Interrupt Status Flag + 27 + 1 + read-write + + + 0 + Configured interrupt is not detected. + #0 + + + 1 + Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. + #1 + + + + + ISF28 + Interrupt Status Flag + 28 + 1 + read-write + + + 0 + Configured interrupt is not detected. + #0 + + + 1 + Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. + #1 + + + + + ISF29 + Interrupt Status Flag + 29 + 1 + read-write + + + 0 + Configured interrupt is not detected. + #0 + + + 1 + Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. + #1 + + + + + ISF30 + Interrupt Status Flag + 30 + 1 + read-write + + + 0 + Configured interrupt is not detected. + #0 + + + 1 + Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. + #1 + + + + + ISF31 + Interrupt Status Flag + 31 + 1 read-write @@ -81887,10 +90685,295 @@ write-only - GPWE + GPWE0 Global Pin Write Enable 16 - 16 + 1 + write-only + + + 0 + Corresponding Pin Control Register is not updated with the value in GPWD. + #0 + + + 1 + Corresponding Pin Control Register is updated with the value in GPWD. + #1 + + + + + GPWE1 + Global Pin Write Enable + 17 + 1 + write-only + + + 0 + Corresponding Pin Control Register is not updated with the value in GPWD. + #0 + + + 1 + Corresponding Pin Control Register is updated with the value in GPWD. + #1 + + + + + GPWE2 + Global Pin Write Enable + 18 + 1 + write-only + + + 0 + Corresponding Pin Control Register is not updated with the value in GPWD. + #0 + + + 1 + Corresponding Pin Control Register is updated with the value in GPWD. + #1 + + + + + GPWE3 + Global Pin Write Enable + 19 + 1 + write-only + + + 0 + Corresponding Pin Control Register is not updated with the value in GPWD. + #0 + + + 1 + Corresponding Pin Control Register is updated with the value in GPWD. + #1 + + + + + GPWE4 + Global Pin Write Enable + 20 + 1 + write-only + + + 0 + Corresponding Pin Control Register is not updated with the value in GPWD. + #0 + + + 1 + Corresponding Pin Control Register is updated with the value in GPWD. + #1 + + + + + GPWE5 + Global Pin Write Enable + 21 + 1 + write-only + + + 0 + Corresponding Pin Control Register is not updated with the value in GPWD. + #0 + + + 1 + Corresponding Pin Control Register is updated with the value in GPWD. + #1 + + + + + GPWE6 + Global Pin Write Enable + 22 + 1 + write-only + + + 0 + Corresponding Pin Control Register is not updated with the value in GPWD. + #0 + + + 1 + Corresponding Pin Control Register is updated with the value in GPWD. + #1 + + + + + GPWE7 + Global Pin Write Enable + 23 + 1 + write-only + + + 0 + Corresponding Pin Control Register is not updated with the value in GPWD. + #0 + + + 1 + Corresponding Pin Control Register is updated with the value in GPWD. + #1 + + + + + GPWE8 + Global Pin Write Enable + 24 + 1 + write-only + + + 0 + Corresponding Pin Control Register is not updated with the value in GPWD. + #0 + + + 1 + Corresponding Pin Control Register is updated with the value in GPWD. + #1 + + + + + GPWE9 + Global Pin Write Enable + 25 + 1 + write-only + + + 0 + Corresponding Pin Control Register is not updated with the value in GPWD. + #0 + + + 1 + Corresponding Pin Control Register is updated with the value in GPWD. + #1 + + + + + GPWE10 + Global Pin Write Enable + 26 + 1 + write-only + + + 0 + Corresponding Pin Control Register is not updated with the value in GPWD. + #0 + + + 1 + Corresponding Pin Control Register is updated with the value in GPWD. + #1 + + + + + GPWE11 + Global Pin Write Enable + 27 + 1 + write-only + + + 0 + Corresponding Pin Control Register is not updated with the value in GPWD. + #0 + + + 1 + Corresponding Pin Control Register is updated with the value in GPWD. + #1 + + + + + GPWE12 + Global Pin Write Enable + 28 + 1 + write-only + + + 0 + Corresponding Pin Control Register is not updated with the value in GPWD. + #0 + + + 1 + Corresponding Pin Control Register is updated with the value in GPWD. + #1 + + + + + GPWE13 + Global Pin Write Enable + 29 + 1 + write-only + + + 0 + Corresponding Pin Control Register is not updated with the value in GPWD. + #0 + + + 1 + Corresponding Pin Control Register is updated with the value in GPWD. + #1 + + + + + GPWE14 + Global Pin Write Enable + 30 + 1 + write-only + + + 0 + Corresponding Pin Control Register is not updated with the value in GPWD. + #0 + + + 1 + Corresponding Pin Control Register is updated with the value in GPWD. + #1 + + + + + GPWE15 + Global Pin Write Enable + 31 + 1 write-only @@ -81924,10 +91007,295 @@ write-only - GPWE + GPWE0 Global Pin Write Enable 16 - 16 + 1 + write-only + + + 0 + Corresponding Pin Control Register is not updated with the value in GPWD. + #0 + + + 1 + Corresponding Pin Control Register is updated with the value in GPWD. + #1 + + + + + GPWE1 + Global Pin Write Enable + 17 + 1 + write-only + + + 0 + Corresponding Pin Control Register is not updated with the value in GPWD. + #0 + + + 1 + Corresponding Pin Control Register is updated with the value in GPWD. + #1 + + + + + GPWE2 + Global Pin Write Enable + 18 + 1 + write-only + + + 0 + Corresponding Pin Control Register is not updated with the value in GPWD. + #0 + + + 1 + Corresponding Pin Control Register is updated with the value in GPWD. + #1 + + + + + GPWE3 + Global Pin Write Enable + 19 + 1 + write-only + + + 0 + Corresponding Pin Control Register is not updated with the value in GPWD. + #0 + + + 1 + Corresponding Pin Control Register is updated with the value in GPWD. + #1 + + + + + GPWE4 + Global Pin Write Enable + 20 + 1 + write-only + + + 0 + Corresponding Pin Control Register is not updated with the value in GPWD. + #0 + + + 1 + Corresponding Pin Control Register is updated with the value in GPWD. + #1 + + + + + GPWE5 + Global Pin Write Enable + 21 + 1 + write-only + + + 0 + Corresponding Pin Control Register is not updated with the value in GPWD. + #0 + + + 1 + Corresponding Pin Control Register is updated with the value in GPWD. + #1 + + + + + GPWE6 + Global Pin Write Enable + 22 + 1 + write-only + + + 0 + Corresponding Pin Control Register is not updated with the value in GPWD. + #0 + + + 1 + Corresponding Pin Control Register is updated with the value in GPWD. + #1 + + + + + GPWE7 + Global Pin Write Enable + 23 + 1 + write-only + + + 0 + Corresponding Pin Control Register is not updated with the value in GPWD. + #0 + + + 1 + Corresponding Pin Control Register is updated with the value in GPWD. + #1 + + + + + GPWE8 + Global Pin Write Enable + 24 + 1 + write-only + + + 0 + Corresponding Pin Control Register is not updated with the value in GPWD. + #0 + + + 1 + Corresponding Pin Control Register is updated with the value in GPWD. + #1 + + + + + GPWE9 + Global Pin Write Enable + 25 + 1 + write-only + + + 0 + Corresponding Pin Control Register is not updated with the value in GPWD. + #0 + + + 1 + Corresponding Pin Control Register is updated with the value in GPWD. + #1 + + + + + GPWE10 + Global Pin Write Enable + 26 + 1 + write-only + + + 0 + Corresponding Pin Control Register is not updated with the value in GPWD. + #0 + + + 1 + Corresponding Pin Control Register is updated with the value in GPWD. + #1 + + + + + GPWE11 + Global Pin Write Enable + 27 + 1 + write-only + + + 0 + Corresponding Pin Control Register is not updated with the value in GPWD. + #0 + + + 1 + Corresponding Pin Control Register is updated with the value in GPWD. + #1 + + + + + GPWE12 + Global Pin Write Enable + 28 + 1 + write-only + + + 0 + Corresponding Pin Control Register is not updated with the value in GPWD. + #0 + + + 1 + Corresponding Pin Control Register is updated with the value in GPWD. + #1 + + + + + GPWE13 + Global Pin Write Enable + 29 + 1 + write-only + + + 0 + Corresponding Pin Control Register is not updated with the value in GPWD. + #0 + + + 1 + Corresponding Pin Control Register is updated with the value in GPWD. + #1 + + + + + GPWE14 + Global Pin Write Enable + 30 + 1 + write-only + + + 0 + Corresponding Pin Control Register is not updated with the value in GPWD. + #0 + + + 1 + Corresponding Pin Control Register is updated with the value in GPWD. + #1 + + + + + GPWE15 + Global Pin Write Enable + 31 + 1 write-only @@ -81954,10 +91322,599 @@ 0xFFFFFFFF - ISF + ISF0 Interrupt Status Flag 0 - 32 + 1 + read-write + + + 0 + Configured interrupt is not detected. + #0 + + + 1 + Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. + #1 + + + + + ISF1 + Interrupt Status Flag + 1 + 1 + read-write + + + 0 + Configured interrupt is not detected. + #0 + + + 1 + Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. + #1 + + + + + ISF2 + Interrupt Status Flag + 2 + 1 + read-write + + + 0 + Configured interrupt is not detected. + #0 + + + 1 + Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. + #1 + + + + + ISF3 + Interrupt Status Flag + 3 + 1 + read-write + + + 0 + Configured interrupt is not detected. + #0 + + + 1 + Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. + #1 + + + + + ISF4 + Interrupt Status Flag + 4 + 1 + read-write + + + 0 + Configured interrupt is not detected. + #0 + + + 1 + Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. + #1 + + + + + ISF5 + Interrupt Status Flag + 5 + 1 + read-write + + + 0 + Configured interrupt is not detected. + #0 + + + 1 + Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. + #1 + + + + + ISF6 + Interrupt Status Flag + 6 + 1 + read-write + + + 0 + Configured interrupt is not detected. + #0 + + + 1 + Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. + #1 + + + + + ISF7 + Interrupt Status Flag + 7 + 1 + read-write + + + 0 + Configured interrupt is not detected. + #0 + + + 1 + Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. + #1 + + + + + ISF8 + Interrupt Status Flag + 8 + 1 + read-write + + + 0 + Configured interrupt is not detected. + #0 + + + 1 + Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. + #1 + + + + + ISF9 + Interrupt Status Flag + 9 + 1 + read-write + + + 0 + Configured interrupt is not detected. + #0 + + + 1 + Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. + #1 + + + + + ISF10 + Interrupt Status Flag + 10 + 1 + read-write + + + 0 + Configured interrupt is not detected. + #0 + + + 1 + Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. + #1 + + + + + ISF11 + Interrupt Status Flag + 11 + 1 + read-write + + + 0 + Configured interrupt is not detected. + #0 + + + 1 + Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. + #1 + + + + + ISF12 + Interrupt Status Flag + 12 + 1 + read-write + + + 0 + Configured interrupt is not detected. + #0 + + + 1 + Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. + #1 + + + + + ISF13 + Interrupt Status Flag + 13 + 1 + read-write + + + 0 + Configured interrupt is not detected. + #0 + + + 1 + Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. + #1 + + + + + ISF14 + Interrupt Status Flag + 14 + 1 + read-write + + + 0 + Configured interrupt is not detected. + #0 + + + 1 + Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. + #1 + + + + + ISF15 + Interrupt Status Flag + 15 + 1 + read-write + + + 0 + Configured interrupt is not detected. + #0 + + + 1 + Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. + #1 + + + + + ISF16 + Interrupt Status Flag + 16 + 1 + read-write + + + 0 + Configured interrupt is not detected. + #0 + + + 1 + Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. + #1 + + + + + ISF17 + Interrupt Status Flag + 17 + 1 + read-write + + + 0 + Configured interrupt is not detected. + #0 + + + 1 + Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. + #1 + + + + + ISF18 + Interrupt Status Flag + 18 + 1 + read-write + + + 0 + Configured interrupt is not detected. + #0 + + + 1 + Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. + #1 + + + + + ISF19 + Interrupt Status Flag + 19 + 1 + read-write + + + 0 + Configured interrupt is not detected. + #0 + + + 1 + Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. + #1 + + + + + ISF20 + Interrupt Status Flag + 20 + 1 + read-write + + + 0 + Configured interrupt is not detected. + #0 + + + 1 + Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. + #1 + + + + + ISF21 + Interrupt Status Flag + 21 + 1 + read-write + + + 0 + Configured interrupt is not detected. + #0 + + + 1 + Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. + #1 + + + + + ISF22 + Interrupt Status Flag + 22 + 1 + read-write + + + 0 + Configured interrupt is not detected. + #0 + + + 1 + Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. + #1 + + + + + ISF23 + Interrupt Status Flag + 23 + 1 + read-write + + + 0 + Configured interrupt is not detected. + #0 + + + 1 + Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. + #1 + + + + + ISF24 + Interrupt Status Flag + 24 + 1 + read-write + + + 0 + Configured interrupt is not detected. + #0 + + + 1 + Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. + #1 + + + + + ISF25 + Interrupt Status Flag + 25 + 1 + read-write + + + 0 + Configured interrupt is not detected. + #0 + + + 1 + Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. + #1 + + + + + ISF26 + Interrupt Status Flag + 26 + 1 + read-write + + + 0 + Configured interrupt is not detected. + #0 + + + 1 + Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. + #1 + + + + + ISF27 + Interrupt Status Flag + 27 + 1 + read-write + + + 0 + Configured interrupt is not detected. + #0 + + + 1 + Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. + #1 + + + + + ISF28 + Interrupt Status Flag + 28 + 1 + read-write + + + 0 + Configured interrupt is not detected. + #0 + + + 1 + Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. + #1 + + + + + ISF29 + Interrupt Status Flag + 29 + 1 + read-write + + + 0 + Configured interrupt is not detected. + #0 + + + 1 + Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. + #1 + + + + + ISF30 + Interrupt Status Flag + 30 + 1 + read-write + + + 0 + Configured interrupt is not detected. + #0 + + + 1 + Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. + #1 + + + + + ISF31 + Interrupt Status Flag + 31 + 1 read-write @@ -90521,10 +100478,295 @@ write-only - GPWE + GPWE0 Global Pin Write Enable 16 - 16 + 1 + write-only + + + 0 + Corresponding Pin Control Register is not updated with the value in GPWD. + #0 + + + 1 + Corresponding Pin Control Register is updated with the value in GPWD. + #1 + + + + + GPWE1 + Global Pin Write Enable + 17 + 1 + write-only + + + 0 + Corresponding Pin Control Register is not updated with the value in GPWD. + #0 + + + 1 + Corresponding Pin Control Register is updated with the value in GPWD. + #1 + + + + + GPWE2 + Global Pin Write Enable + 18 + 1 + write-only + + + 0 + Corresponding Pin Control Register is not updated with the value in GPWD. + #0 + + + 1 + Corresponding Pin Control Register is updated with the value in GPWD. + #1 + + + + + GPWE3 + Global Pin Write Enable + 19 + 1 + write-only + + + 0 + Corresponding Pin Control Register is not updated with the value in GPWD. + #0 + + + 1 + Corresponding Pin Control Register is updated with the value in GPWD. + #1 + + + + + GPWE4 + Global Pin Write Enable + 20 + 1 + write-only + + + 0 + Corresponding Pin Control Register is not updated with the value in GPWD. + #0 + + + 1 + Corresponding Pin Control Register is updated with the value in GPWD. + #1 + + + + + GPWE5 + Global Pin Write Enable + 21 + 1 + write-only + + + 0 + Corresponding Pin Control Register is not updated with the value in GPWD. + #0 + + + 1 + Corresponding Pin Control Register is updated with the value in GPWD. + #1 + + + + + GPWE6 + Global Pin Write Enable + 22 + 1 + write-only + + + 0 + Corresponding Pin Control Register is not updated with the value in GPWD. + #0 + + + 1 + Corresponding Pin Control Register is updated with the value in GPWD. + #1 + + + + + GPWE7 + Global Pin Write Enable + 23 + 1 + write-only + + + 0 + Corresponding Pin Control Register is not updated with the value in GPWD. + #0 + + + 1 + Corresponding Pin Control Register is updated with the value in GPWD. + #1 + + + + + GPWE8 + Global Pin Write Enable + 24 + 1 + write-only + + + 0 + Corresponding Pin Control Register is not updated with the value in GPWD. + #0 + + + 1 + Corresponding Pin Control Register is updated with the value in GPWD. + #1 + + + + + GPWE9 + Global Pin Write Enable + 25 + 1 + write-only + + + 0 + Corresponding Pin Control Register is not updated with the value in GPWD. + #0 + + + 1 + Corresponding Pin Control Register is updated with the value in GPWD. + #1 + + + + + GPWE10 + Global Pin Write Enable + 26 + 1 + write-only + + + 0 + Corresponding Pin Control Register is not updated with the value in GPWD. + #0 + + + 1 + Corresponding Pin Control Register is updated with the value in GPWD. + #1 + + + + + GPWE11 + Global Pin Write Enable + 27 + 1 + write-only + + + 0 + Corresponding Pin Control Register is not updated with the value in GPWD. + #0 + + + 1 + Corresponding Pin Control Register is updated with the value in GPWD. + #1 + + + + + GPWE12 + Global Pin Write Enable + 28 + 1 + write-only + + + 0 + Corresponding Pin Control Register is not updated with the value in GPWD. + #0 + + + 1 + Corresponding Pin Control Register is updated with the value in GPWD. + #1 + + + + + GPWE13 + Global Pin Write Enable + 29 + 1 + write-only + + + 0 + Corresponding Pin Control Register is not updated with the value in GPWD. + #0 + + + 1 + Corresponding Pin Control Register is updated with the value in GPWD. + #1 + + + + + GPWE14 + Global Pin Write Enable + 30 + 1 + write-only + + + 0 + Corresponding Pin Control Register is not updated with the value in GPWD. + #0 + + + 1 + Corresponding Pin Control Register is updated with the value in GPWD. + #1 + + + + + GPWE15 + Global Pin Write Enable + 31 + 1 write-only @@ -90558,10 +100800,295 @@ write-only - GPWE + GPWE0 Global Pin Write Enable 16 - 16 + 1 + write-only + + + 0 + Corresponding Pin Control Register is not updated with the value in GPWD. + #0 + + + 1 + Corresponding Pin Control Register is updated with the value in GPWD. + #1 + + + + + GPWE1 + Global Pin Write Enable + 17 + 1 + write-only + + + 0 + Corresponding Pin Control Register is not updated with the value in GPWD. + #0 + + + 1 + Corresponding Pin Control Register is updated with the value in GPWD. + #1 + + + + + GPWE2 + Global Pin Write Enable + 18 + 1 + write-only + + + 0 + Corresponding Pin Control Register is not updated with the value in GPWD. + #0 + + + 1 + Corresponding Pin Control Register is updated with the value in GPWD. + #1 + + + + + GPWE3 + Global Pin Write Enable + 19 + 1 + write-only + + + 0 + Corresponding Pin Control Register is not updated with the value in GPWD. + #0 + + + 1 + Corresponding Pin Control Register is updated with the value in GPWD. + #1 + + + + + GPWE4 + Global Pin Write Enable + 20 + 1 + write-only + + + 0 + Corresponding Pin Control Register is not updated with the value in GPWD. + #0 + + + 1 + Corresponding Pin Control Register is updated with the value in GPWD. + #1 + + + + + GPWE5 + Global Pin Write Enable + 21 + 1 + write-only + + + 0 + Corresponding Pin Control Register is not updated with the value in GPWD. + #0 + + + 1 + Corresponding Pin Control Register is updated with the value in GPWD. + #1 + + + + + GPWE6 + Global Pin Write Enable + 22 + 1 + write-only + + + 0 + Corresponding Pin Control Register is not updated with the value in GPWD. + #0 + + + 1 + Corresponding Pin Control Register is updated with the value in GPWD. + #1 + + + + + GPWE7 + Global Pin Write Enable + 23 + 1 + write-only + + + 0 + Corresponding Pin Control Register is not updated with the value in GPWD. + #0 + + + 1 + Corresponding Pin Control Register is updated with the value in GPWD. + #1 + + + + + GPWE8 + Global Pin Write Enable + 24 + 1 + write-only + + + 0 + Corresponding Pin Control Register is not updated with the value in GPWD. + #0 + + + 1 + Corresponding Pin Control Register is updated with the value in GPWD. + #1 + + + + + GPWE9 + Global Pin Write Enable + 25 + 1 + write-only + + + 0 + Corresponding Pin Control Register is not updated with the value in GPWD. + #0 + + + 1 + Corresponding Pin Control Register is updated with the value in GPWD. + #1 + + + + + GPWE10 + Global Pin Write Enable + 26 + 1 + write-only + + + 0 + Corresponding Pin Control Register is not updated with the value in GPWD. + #0 + + + 1 + Corresponding Pin Control Register is updated with the value in GPWD. + #1 + + + + + GPWE11 + Global Pin Write Enable + 27 + 1 + write-only + + + 0 + Corresponding Pin Control Register is not updated with the value in GPWD. + #0 + + + 1 + Corresponding Pin Control Register is updated with the value in GPWD. + #1 + + + + + GPWE12 + Global Pin Write Enable + 28 + 1 + write-only + + + 0 + Corresponding Pin Control Register is not updated with the value in GPWD. + #0 + + + 1 + Corresponding Pin Control Register is updated with the value in GPWD. + #1 + + + + + GPWE13 + Global Pin Write Enable + 29 + 1 + write-only + + + 0 + Corresponding Pin Control Register is not updated with the value in GPWD. + #0 + + + 1 + Corresponding Pin Control Register is updated with the value in GPWD. + #1 + + + + + GPWE14 + Global Pin Write Enable + 30 + 1 + write-only + + + 0 + Corresponding Pin Control Register is not updated with the value in GPWD. + #0 + + + 1 + Corresponding Pin Control Register is updated with the value in GPWD. + #1 + + + + + GPWE15 + Global Pin Write Enable + 31 + 1 write-only @@ -90588,10 +101115,599 @@ 0xFFFFFFFF - ISF + ISF0 Interrupt Status Flag 0 - 32 + 1 + read-write + + + 0 + Configured interrupt is not detected. + #0 + + + 1 + Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. + #1 + + + + + ISF1 + Interrupt Status Flag + 1 + 1 + read-write + + + 0 + Configured interrupt is not detected. + #0 + + + 1 + Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. + #1 + + + + + ISF2 + Interrupt Status Flag + 2 + 1 + read-write + + + 0 + Configured interrupt is not detected. + #0 + + + 1 + Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. + #1 + + + + + ISF3 + Interrupt Status Flag + 3 + 1 + read-write + + + 0 + Configured interrupt is not detected. + #0 + + + 1 + Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. + #1 + + + + + ISF4 + Interrupt Status Flag + 4 + 1 + read-write + + + 0 + Configured interrupt is not detected. + #0 + + + 1 + Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. + #1 + + + + + ISF5 + Interrupt Status Flag + 5 + 1 + read-write + + + 0 + Configured interrupt is not detected. + #0 + + + 1 + Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. + #1 + + + + + ISF6 + Interrupt Status Flag + 6 + 1 + read-write + + + 0 + Configured interrupt is not detected. + #0 + + + 1 + Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. + #1 + + + + + ISF7 + Interrupt Status Flag + 7 + 1 + read-write + + + 0 + Configured interrupt is not detected. + #0 + + + 1 + Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. + #1 + + + + + ISF8 + Interrupt Status Flag + 8 + 1 + read-write + + + 0 + Configured interrupt is not detected. + #0 + + + 1 + Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. + #1 + + + + + ISF9 + Interrupt Status Flag + 9 + 1 + read-write + + + 0 + Configured interrupt is not detected. + #0 + + + 1 + Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. + #1 + + + + + ISF10 + Interrupt Status Flag + 10 + 1 + read-write + + + 0 + Configured interrupt is not detected. + #0 + + + 1 + Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. + #1 + + + + + ISF11 + Interrupt Status Flag + 11 + 1 + read-write + + + 0 + Configured interrupt is not detected. + #0 + + + 1 + Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. + #1 + + + + + ISF12 + Interrupt Status Flag + 12 + 1 + read-write + + + 0 + Configured interrupt is not detected. + #0 + + + 1 + Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. + #1 + + + + + ISF13 + Interrupt Status Flag + 13 + 1 + read-write + + + 0 + Configured interrupt is not detected. + #0 + + + 1 + Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. + #1 + + + + + ISF14 + Interrupt Status Flag + 14 + 1 + read-write + + + 0 + Configured interrupt is not detected. + #0 + + + 1 + Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. + #1 + + + + + ISF15 + Interrupt Status Flag + 15 + 1 + read-write + + + 0 + Configured interrupt is not detected. + #0 + + + 1 + Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. + #1 + + + + + ISF16 + Interrupt Status Flag + 16 + 1 + read-write + + + 0 + Configured interrupt is not detected. + #0 + + + 1 + Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. + #1 + + + + + ISF17 + Interrupt Status Flag + 17 + 1 + read-write + + + 0 + Configured interrupt is not detected. + #0 + + + 1 + Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. + #1 + + + + + ISF18 + Interrupt Status Flag + 18 + 1 + read-write + + + 0 + Configured interrupt is not detected. + #0 + + + 1 + Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. + #1 + + + + + ISF19 + Interrupt Status Flag + 19 + 1 + read-write + + + 0 + Configured interrupt is not detected. + #0 + + + 1 + Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. + #1 + + + + + ISF20 + Interrupt Status Flag + 20 + 1 + read-write + + + 0 + Configured interrupt is not detected. + #0 + + + 1 + Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. + #1 + + + + + ISF21 + Interrupt Status Flag + 21 + 1 + read-write + + + 0 + Configured interrupt is not detected. + #0 + + + 1 + Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. + #1 + + + + + ISF22 + Interrupt Status Flag + 22 + 1 + read-write + + + 0 + Configured interrupt is not detected. + #0 + + + 1 + Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. + #1 + + + + + ISF23 + Interrupt Status Flag + 23 + 1 + read-write + + + 0 + Configured interrupt is not detected. + #0 + + + 1 + Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. + #1 + + + + + ISF24 + Interrupt Status Flag + 24 + 1 + read-write + + + 0 + Configured interrupt is not detected. + #0 + + + 1 + Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. + #1 + + + + + ISF25 + Interrupt Status Flag + 25 + 1 + read-write + + + 0 + Configured interrupt is not detected. + #0 + + + 1 + Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. + #1 + + + + + ISF26 + Interrupt Status Flag + 26 + 1 + read-write + + + 0 + Configured interrupt is not detected. + #0 + + + 1 + Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. + #1 + + + + + ISF27 + Interrupt Status Flag + 27 + 1 + read-write + + + 0 + Configured interrupt is not detected. + #0 + + + 1 + Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. + #1 + + + + + ISF28 + Interrupt Status Flag + 28 + 1 + read-write + + + 0 + Configured interrupt is not detected. + #0 + + + 1 + Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. + #1 + + + + + ISF29 + Interrupt Status Flag + 29 + 1 + read-write + + + 0 + Configured interrupt is not detected. + #0 + + + 1 + Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. + #1 + + + + + ISF30 + Interrupt Status Flag + 30 + 1 + read-write + + + 0 + Configured interrupt is not detected. + #0 + + + 1 + Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. + #1 + + + + + ISF31 + Interrupt Status Flag + 31 + 1 read-write @@ -90618,10 +101734,599 @@ 0xFFFFFFFF - DFE + DFE0 Digital Filter Enable 0 - 32 + 1 + read-write + + + 0 + Digital filter is disabled on the corresponding pin and output of the digital filter is reset to zero. + #0 + + + 1 + Digital filter is enabled on the corresponding pin, if the pin is configured as a digital input. + #1 + + + + + DFE1 + Digital Filter Enable + 1 + 1 + read-write + + + 0 + Digital filter is disabled on the corresponding pin and output of the digital filter is reset to zero. + #0 + + + 1 + Digital filter is enabled on the corresponding pin, if the pin is configured as a digital input. + #1 + + + + + DFE2 + Digital Filter Enable + 2 + 1 + read-write + + + 0 + Digital filter is disabled on the corresponding pin and output of the digital filter is reset to zero. + #0 + + + 1 + Digital filter is enabled on the corresponding pin, if the pin is configured as a digital input. + #1 + + + + + DFE3 + Digital Filter Enable + 3 + 1 + read-write + + + 0 + Digital filter is disabled on the corresponding pin and output of the digital filter is reset to zero. + #0 + + + 1 + Digital filter is enabled on the corresponding pin, if the pin is configured as a digital input. + #1 + + + + + DFE4 + Digital Filter Enable + 4 + 1 + read-write + + + 0 + Digital filter is disabled on the corresponding pin and output of the digital filter is reset to zero. + #0 + + + 1 + Digital filter is enabled on the corresponding pin, if the pin is configured as a digital input. + #1 + + + + + DFE5 + Digital Filter Enable + 5 + 1 + read-write + + + 0 + Digital filter is disabled on the corresponding pin and output of the digital filter is reset to zero. + #0 + + + 1 + Digital filter is enabled on the corresponding pin, if the pin is configured as a digital input. + #1 + + + + + DFE6 + Digital Filter Enable + 6 + 1 + read-write + + + 0 + Digital filter is disabled on the corresponding pin and output of the digital filter is reset to zero. + #0 + + + 1 + Digital filter is enabled on the corresponding pin, if the pin is configured as a digital input. + #1 + + + + + DFE7 + Digital Filter Enable + 7 + 1 + read-write + + + 0 + Digital filter is disabled on the corresponding pin and output of the digital filter is reset to zero. + #0 + + + 1 + Digital filter is enabled on the corresponding pin, if the pin is configured as a digital input. + #1 + + + + + DFE8 + Digital Filter Enable + 8 + 1 + read-write + + + 0 + Digital filter is disabled on the corresponding pin and output of the digital filter is reset to zero. + #0 + + + 1 + Digital filter is enabled on the corresponding pin, if the pin is configured as a digital input. + #1 + + + + + DFE9 + Digital Filter Enable + 9 + 1 + read-write + + + 0 + Digital filter is disabled on the corresponding pin and output of the digital filter is reset to zero. + #0 + + + 1 + Digital filter is enabled on the corresponding pin, if the pin is configured as a digital input. + #1 + + + + + DFE10 + Digital Filter Enable + 10 + 1 + read-write + + + 0 + Digital filter is disabled on the corresponding pin and output of the digital filter is reset to zero. + #0 + + + 1 + Digital filter is enabled on the corresponding pin, if the pin is configured as a digital input. + #1 + + + + + DFE11 + Digital Filter Enable + 11 + 1 + read-write + + + 0 + Digital filter is disabled on the corresponding pin and output of the digital filter is reset to zero. + #0 + + + 1 + Digital filter is enabled on the corresponding pin, if the pin is configured as a digital input. + #1 + + + + + DFE12 + Digital Filter Enable + 12 + 1 + read-write + + + 0 + Digital filter is disabled on the corresponding pin and output of the digital filter is reset to zero. + #0 + + + 1 + Digital filter is enabled on the corresponding pin, if the pin is configured as a digital input. + #1 + + + + + DFE13 + Digital Filter Enable + 13 + 1 + read-write + + + 0 + Digital filter is disabled on the corresponding pin and output of the digital filter is reset to zero. + #0 + + + 1 + Digital filter is enabled on the corresponding pin, if the pin is configured as a digital input. + #1 + + + + + DFE14 + Digital Filter Enable + 14 + 1 + read-write + + + 0 + Digital filter is disabled on the corresponding pin and output of the digital filter is reset to zero. + #0 + + + 1 + Digital filter is enabled on the corresponding pin, if the pin is configured as a digital input. + #1 + + + + + DFE15 + Digital Filter Enable + 15 + 1 + read-write + + + 0 + Digital filter is disabled on the corresponding pin and output of the digital filter is reset to zero. + #0 + + + 1 + Digital filter is enabled on the corresponding pin, if the pin is configured as a digital input. + #1 + + + + + DFE16 + Digital Filter Enable + 16 + 1 + read-write + + + 0 + Digital filter is disabled on the corresponding pin and output of the digital filter is reset to zero. + #0 + + + 1 + Digital filter is enabled on the corresponding pin, if the pin is configured as a digital input. + #1 + + + + + DFE17 + Digital Filter Enable + 17 + 1 + read-write + + + 0 + Digital filter is disabled on the corresponding pin and output of the digital filter is reset to zero. + #0 + + + 1 + Digital filter is enabled on the corresponding pin, if the pin is configured as a digital input. + #1 + + + + + DFE18 + Digital Filter Enable + 18 + 1 + read-write + + + 0 + Digital filter is disabled on the corresponding pin and output of the digital filter is reset to zero. + #0 + + + 1 + Digital filter is enabled on the corresponding pin, if the pin is configured as a digital input. + #1 + + + + + DFE19 + Digital Filter Enable + 19 + 1 + read-write + + + 0 + Digital filter is disabled on the corresponding pin and output of the digital filter is reset to zero. + #0 + + + 1 + Digital filter is enabled on the corresponding pin, if the pin is configured as a digital input. + #1 + + + + + DFE20 + Digital Filter Enable + 20 + 1 + read-write + + + 0 + Digital filter is disabled on the corresponding pin and output of the digital filter is reset to zero. + #0 + + + 1 + Digital filter is enabled on the corresponding pin, if the pin is configured as a digital input. + #1 + + + + + DFE21 + Digital Filter Enable + 21 + 1 + read-write + + + 0 + Digital filter is disabled on the corresponding pin and output of the digital filter is reset to zero. + #0 + + + 1 + Digital filter is enabled on the corresponding pin, if the pin is configured as a digital input. + #1 + + + + + DFE22 + Digital Filter Enable + 22 + 1 + read-write + + + 0 + Digital filter is disabled on the corresponding pin and output of the digital filter is reset to zero. + #0 + + + 1 + Digital filter is enabled on the corresponding pin, if the pin is configured as a digital input. + #1 + + + + + DFE23 + Digital Filter Enable + 23 + 1 + read-write + + + 0 + Digital filter is disabled on the corresponding pin and output of the digital filter is reset to zero. + #0 + + + 1 + Digital filter is enabled on the corresponding pin, if the pin is configured as a digital input. + #1 + + + + + DFE24 + Digital Filter Enable + 24 + 1 + read-write + + + 0 + Digital filter is disabled on the corresponding pin and output of the digital filter is reset to zero. + #0 + + + 1 + Digital filter is enabled on the corresponding pin, if the pin is configured as a digital input. + #1 + + + + + DFE25 + Digital Filter Enable + 25 + 1 + read-write + + + 0 + Digital filter is disabled on the corresponding pin and output of the digital filter is reset to zero. + #0 + + + 1 + Digital filter is enabled on the corresponding pin, if the pin is configured as a digital input. + #1 + + + + + DFE26 + Digital Filter Enable + 26 + 1 + read-write + + + 0 + Digital filter is disabled on the corresponding pin and output of the digital filter is reset to zero. + #0 + + + 1 + Digital filter is enabled on the corresponding pin, if the pin is configured as a digital input. + #1 + + + + + DFE27 + Digital Filter Enable + 27 + 1 + read-write + + + 0 + Digital filter is disabled on the corresponding pin and output of the digital filter is reset to zero. + #0 + + + 1 + Digital filter is enabled on the corresponding pin, if the pin is configured as a digital input. + #1 + + + + + DFE28 + Digital Filter Enable + 28 + 1 + read-write + + + 0 + Digital filter is disabled on the corresponding pin and output of the digital filter is reset to zero. + #0 + + + 1 + Digital filter is enabled on the corresponding pin, if the pin is configured as a digital input. + #1 + + + + + DFE29 + Digital Filter Enable + 29 + 1 + read-write + + + 0 + Digital filter is disabled on the corresponding pin and output of the digital filter is reset to zero. + #0 + + + 1 + Digital filter is enabled on the corresponding pin, if the pin is configured as a digital input. + #1 + + + + + DFE30 + Digital Filter Enable + 30 + 1 + read-write + + + 0 + Digital filter is disabled on the corresponding pin and output of the digital filter is reset to zero. + #0 + + + 1 + Digital filter is enabled on the corresponding pin, if the pin is configured as a digital input. + #1 + + + + + DFE31 + Digital Filter Enable + 31 + 1 read-write @@ -99233,10 +110938,295 @@ write-only - GPWE + GPWE0 Global Pin Write Enable 16 - 16 + 1 + write-only + + + 0 + Corresponding Pin Control Register is not updated with the value in GPWD. + #0 + + + 1 + Corresponding Pin Control Register is updated with the value in GPWD. + #1 + + + + + GPWE1 + Global Pin Write Enable + 17 + 1 + write-only + + + 0 + Corresponding Pin Control Register is not updated with the value in GPWD. + #0 + + + 1 + Corresponding Pin Control Register is updated with the value in GPWD. + #1 + + + + + GPWE2 + Global Pin Write Enable + 18 + 1 + write-only + + + 0 + Corresponding Pin Control Register is not updated with the value in GPWD. + #0 + + + 1 + Corresponding Pin Control Register is updated with the value in GPWD. + #1 + + + + + GPWE3 + Global Pin Write Enable + 19 + 1 + write-only + + + 0 + Corresponding Pin Control Register is not updated with the value in GPWD. + #0 + + + 1 + Corresponding Pin Control Register is updated with the value in GPWD. + #1 + + + + + GPWE4 + Global Pin Write Enable + 20 + 1 + write-only + + + 0 + Corresponding Pin Control Register is not updated with the value in GPWD. + #0 + + + 1 + Corresponding Pin Control Register is updated with the value in GPWD. + #1 + + + + + GPWE5 + Global Pin Write Enable + 21 + 1 + write-only + + + 0 + Corresponding Pin Control Register is not updated with the value in GPWD. + #0 + + + 1 + Corresponding Pin Control Register is updated with the value in GPWD. + #1 + + + + + GPWE6 + Global Pin Write Enable + 22 + 1 + write-only + + + 0 + Corresponding Pin Control Register is not updated with the value in GPWD. + #0 + + + 1 + Corresponding Pin Control Register is updated with the value in GPWD. + #1 + + + + + GPWE7 + Global Pin Write Enable + 23 + 1 + write-only + + + 0 + Corresponding Pin Control Register is not updated with the value in GPWD. + #0 + + + 1 + Corresponding Pin Control Register is updated with the value in GPWD. + #1 + + + + + GPWE8 + Global Pin Write Enable + 24 + 1 + write-only + + + 0 + Corresponding Pin Control Register is not updated with the value in GPWD. + #0 + + + 1 + Corresponding Pin Control Register is updated with the value in GPWD. + #1 + + + + + GPWE9 + Global Pin Write Enable + 25 + 1 + write-only + + + 0 + Corresponding Pin Control Register is not updated with the value in GPWD. + #0 + + + 1 + Corresponding Pin Control Register is updated with the value in GPWD. + #1 + + + + + GPWE10 + Global Pin Write Enable + 26 + 1 + write-only + + + 0 + Corresponding Pin Control Register is not updated with the value in GPWD. + #0 + + + 1 + Corresponding Pin Control Register is updated with the value in GPWD. + #1 + + + + + GPWE11 + Global Pin Write Enable + 27 + 1 + write-only + + + 0 + Corresponding Pin Control Register is not updated with the value in GPWD. + #0 + + + 1 + Corresponding Pin Control Register is updated with the value in GPWD. + #1 + + + + + GPWE12 + Global Pin Write Enable + 28 + 1 + write-only + + + 0 + Corresponding Pin Control Register is not updated with the value in GPWD. + #0 + + + 1 + Corresponding Pin Control Register is updated with the value in GPWD. + #1 + + + + + GPWE13 + Global Pin Write Enable + 29 + 1 + write-only + + + 0 + Corresponding Pin Control Register is not updated with the value in GPWD. + #0 + + + 1 + Corresponding Pin Control Register is updated with the value in GPWD. + #1 + + + + + GPWE14 + Global Pin Write Enable + 30 + 1 + write-only + + + 0 + Corresponding Pin Control Register is not updated with the value in GPWD. + #0 + + + 1 + Corresponding Pin Control Register is updated with the value in GPWD. + #1 + + + + + GPWE15 + Global Pin Write Enable + 31 + 1 write-only @@ -99270,10 +111260,295 @@ write-only - GPWE + GPWE0 Global Pin Write Enable 16 - 16 + 1 + write-only + + + 0 + Corresponding Pin Control Register is not updated with the value in GPWD. + #0 + + + 1 + Corresponding Pin Control Register is updated with the value in GPWD. + #1 + + + + + GPWE1 + Global Pin Write Enable + 17 + 1 + write-only + + + 0 + Corresponding Pin Control Register is not updated with the value in GPWD. + #0 + + + 1 + Corresponding Pin Control Register is updated with the value in GPWD. + #1 + + + + + GPWE2 + Global Pin Write Enable + 18 + 1 + write-only + + + 0 + Corresponding Pin Control Register is not updated with the value in GPWD. + #0 + + + 1 + Corresponding Pin Control Register is updated with the value in GPWD. + #1 + + + + + GPWE3 + Global Pin Write Enable + 19 + 1 + write-only + + + 0 + Corresponding Pin Control Register is not updated with the value in GPWD. + #0 + + + 1 + Corresponding Pin Control Register is updated with the value in GPWD. + #1 + + + + + GPWE4 + Global Pin Write Enable + 20 + 1 + write-only + + + 0 + Corresponding Pin Control Register is not updated with the value in GPWD. + #0 + + + 1 + Corresponding Pin Control Register is updated with the value in GPWD. + #1 + + + + + GPWE5 + Global Pin Write Enable + 21 + 1 + write-only + + + 0 + Corresponding Pin Control Register is not updated with the value in GPWD. + #0 + + + 1 + Corresponding Pin Control Register is updated with the value in GPWD. + #1 + + + + + GPWE6 + Global Pin Write Enable + 22 + 1 + write-only + + + 0 + Corresponding Pin Control Register is not updated with the value in GPWD. + #0 + + + 1 + Corresponding Pin Control Register is updated with the value in GPWD. + #1 + + + + + GPWE7 + Global Pin Write Enable + 23 + 1 + write-only + + + 0 + Corresponding Pin Control Register is not updated with the value in GPWD. + #0 + + + 1 + Corresponding Pin Control Register is updated with the value in GPWD. + #1 + + + + + GPWE8 + Global Pin Write Enable + 24 + 1 + write-only + + + 0 + Corresponding Pin Control Register is not updated with the value in GPWD. + #0 + + + 1 + Corresponding Pin Control Register is updated with the value in GPWD. + #1 + + + + + GPWE9 + Global Pin Write Enable + 25 + 1 + write-only + + + 0 + Corresponding Pin Control Register is not updated with the value in GPWD. + #0 + + + 1 + Corresponding Pin Control Register is updated with the value in GPWD. + #1 + + + + + GPWE10 + Global Pin Write Enable + 26 + 1 + write-only + + + 0 + Corresponding Pin Control Register is not updated with the value in GPWD. + #0 + + + 1 + Corresponding Pin Control Register is updated with the value in GPWD. + #1 + + + + + GPWE11 + Global Pin Write Enable + 27 + 1 + write-only + + + 0 + Corresponding Pin Control Register is not updated with the value in GPWD. + #0 + + + 1 + Corresponding Pin Control Register is updated with the value in GPWD. + #1 + + + + + GPWE12 + Global Pin Write Enable + 28 + 1 + write-only + + + 0 + Corresponding Pin Control Register is not updated with the value in GPWD. + #0 + + + 1 + Corresponding Pin Control Register is updated with the value in GPWD. + #1 + + + + + GPWE13 + Global Pin Write Enable + 29 + 1 + write-only + + + 0 + Corresponding Pin Control Register is not updated with the value in GPWD. + #0 + + + 1 + Corresponding Pin Control Register is updated with the value in GPWD. + #1 + + + + + GPWE14 + Global Pin Write Enable + 30 + 1 + write-only + + + 0 + Corresponding Pin Control Register is not updated with the value in GPWD. + #0 + + + 1 + Corresponding Pin Control Register is updated with the value in GPWD. + #1 + + + + + GPWE15 + Global Pin Write Enable + 31 + 1 write-only @@ -99300,10 +111575,599 @@ 0xFFFFFFFF - ISF + ISF0 Interrupt Status Flag 0 - 32 + 1 + read-write + + + 0 + Configured interrupt is not detected. + #0 + + + 1 + Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. + #1 + + + + + ISF1 + Interrupt Status Flag + 1 + 1 + read-write + + + 0 + Configured interrupt is not detected. + #0 + + + 1 + Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. + #1 + + + + + ISF2 + Interrupt Status Flag + 2 + 1 + read-write + + + 0 + Configured interrupt is not detected. + #0 + + + 1 + Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. + #1 + + + + + ISF3 + Interrupt Status Flag + 3 + 1 + read-write + + + 0 + Configured interrupt is not detected. + #0 + + + 1 + Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. + #1 + + + + + ISF4 + Interrupt Status Flag + 4 + 1 + read-write + + + 0 + Configured interrupt is not detected. + #0 + + + 1 + Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. + #1 + + + + + ISF5 + Interrupt Status Flag + 5 + 1 + read-write + + + 0 + Configured interrupt is not detected. + #0 + + + 1 + Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. + #1 + + + + + ISF6 + Interrupt Status Flag + 6 + 1 + read-write + + + 0 + Configured interrupt is not detected. + #0 + + + 1 + Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. + #1 + + + + + ISF7 + Interrupt Status Flag + 7 + 1 + read-write + + + 0 + Configured interrupt is not detected. + #0 + + + 1 + Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. + #1 + + + + + ISF8 + Interrupt Status Flag + 8 + 1 + read-write + + + 0 + Configured interrupt is not detected. + #0 + + + 1 + Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. + #1 + + + + + ISF9 + Interrupt Status Flag + 9 + 1 + read-write + + + 0 + Configured interrupt is not detected. + #0 + + + 1 + Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. + #1 + + + + + ISF10 + Interrupt Status Flag + 10 + 1 + read-write + + + 0 + Configured interrupt is not detected. + #0 + + + 1 + Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. + #1 + + + + + ISF11 + Interrupt Status Flag + 11 + 1 + read-write + + + 0 + Configured interrupt is not detected. + #0 + + + 1 + Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. + #1 + + + + + ISF12 + Interrupt Status Flag + 12 + 1 + read-write + + + 0 + Configured interrupt is not detected. + #0 + + + 1 + Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. + #1 + + + + + ISF13 + Interrupt Status Flag + 13 + 1 + read-write + + + 0 + Configured interrupt is not detected. + #0 + + + 1 + Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. + #1 + + + + + ISF14 + Interrupt Status Flag + 14 + 1 + read-write + + + 0 + Configured interrupt is not detected. + #0 + + + 1 + Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. + #1 + + + + + ISF15 + Interrupt Status Flag + 15 + 1 + read-write + + + 0 + Configured interrupt is not detected. + #0 + + + 1 + Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. + #1 + + + + + ISF16 + Interrupt Status Flag + 16 + 1 + read-write + + + 0 + Configured interrupt is not detected. + #0 + + + 1 + Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. + #1 + + + + + ISF17 + Interrupt Status Flag + 17 + 1 + read-write + + + 0 + Configured interrupt is not detected. + #0 + + + 1 + Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. + #1 + + + + + ISF18 + Interrupt Status Flag + 18 + 1 + read-write + + + 0 + Configured interrupt is not detected. + #0 + + + 1 + Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. + #1 + + + + + ISF19 + Interrupt Status Flag + 19 + 1 + read-write + + + 0 + Configured interrupt is not detected. + #0 + + + 1 + Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. + #1 + + + + + ISF20 + Interrupt Status Flag + 20 + 1 + read-write + + + 0 + Configured interrupt is not detected. + #0 + + + 1 + Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. + #1 + + + + + ISF21 + Interrupt Status Flag + 21 + 1 + read-write + + + 0 + Configured interrupt is not detected. + #0 + + + 1 + Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. + #1 + + + + + ISF22 + Interrupt Status Flag + 22 + 1 + read-write + + + 0 + Configured interrupt is not detected. + #0 + + + 1 + Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. + #1 + + + + + ISF23 + Interrupt Status Flag + 23 + 1 + read-write + + + 0 + Configured interrupt is not detected. + #0 + + + 1 + Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. + #1 + + + + + ISF24 + Interrupt Status Flag + 24 + 1 + read-write + + + 0 + Configured interrupt is not detected. + #0 + + + 1 + Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. + #1 + + + + + ISF25 + Interrupt Status Flag + 25 + 1 + read-write + + + 0 + Configured interrupt is not detected. + #0 + + + 1 + Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. + #1 + + + + + ISF26 + Interrupt Status Flag + 26 + 1 + read-write + + + 0 + Configured interrupt is not detected. + #0 + + + 1 + Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. + #1 + + + + + ISF27 + Interrupt Status Flag + 27 + 1 + read-write + + + 0 + Configured interrupt is not detected. + #0 + + + 1 + Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. + #1 + + + + + ISF28 + Interrupt Status Flag + 28 + 1 + read-write + + + 0 + Configured interrupt is not detected. + #0 + + + 1 + Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. + #1 + + + + + ISF29 + Interrupt Status Flag + 29 + 1 + read-write + + + 0 + Configured interrupt is not detected. + #0 + + + 1 + Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. + #1 + + + + + ISF30 + Interrupt Status Flag + 30 + 1 + read-write + + + 0 + Configured interrupt is not detected. + #0 + + + 1 + Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. + #1 + + + + + ISF31 + Interrupt Status Flag + 31 + 1 read-write @@ -128448,10 +141312,599 @@ 0xFFFFFFFF - PDO + PDO0 Port Data Output 0 - 32 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO1 + Port Data Output + 1 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO2 + Port Data Output + 2 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO3 + Port Data Output + 3 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO4 + Port Data Output + 4 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO5 + Port Data Output + 5 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO6 + Port Data Output + 6 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO7 + Port Data Output + 7 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO8 + Port Data Output + 8 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO9 + Port Data Output + 9 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO10 + Port Data Output + 10 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO11 + Port Data Output + 11 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO12 + Port Data Output + 12 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO13 + Port Data Output + 13 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO14 + Port Data Output + 14 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO15 + Port Data Output + 15 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO16 + Port Data Output + 16 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO17 + Port Data Output + 17 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO18 + Port Data Output + 18 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO19 + Port Data Output + 19 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO20 + Port Data Output + 20 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO21 + Port Data Output + 21 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO22 + Port Data Output + 22 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO23 + Port Data Output + 23 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO24 + Port Data Output + 24 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO25 + Port Data Output + 25 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO26 + Port Data Output + 26 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO27 + Port Data Output + 27 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO28 + Port Data Output + 28 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO29 + Port Data Output + 29 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO30 + Port Data Output + 30 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO31 + Port Data Output + 31 + 1 read-write @@ -128478,10 +141931,599 @@ 0xFFFFFFFF - PTSO + PTSO0 Port Set Output 0 - 32 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO1 + Port Set Output + 1 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO2 + Port Set Output + 2 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO3 + Port Set Output + 3 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO4 + Port Set Output + 4 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO5 + Port Set Output + 5 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO6 + Port Set Output + 6 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO7 + Port Set Output + 7 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO8 + Port Set Output + 8 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO9 + Port Set Output + 9 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO10 + Port Set Output + 10 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO11 + Port Set Output + 11 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO12 + Port Set Output + 12 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO13 + Port Set Output + 13 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO14 + Port Set Output + 14 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO15 + Port Set Output + 15 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO16 + Port Set Output + 16 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO17 + Port Set Output + 17 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO18 + Port Set Output + 18 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO19 + Port Set Output + 19 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO20 + Port Set Output + 20 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO21 + Port Set Output + 21 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO22 + Port Set Output + 22 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO23 + Port Set Output + 23 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO24 + Port Set Output + 24 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO25 + Port Set Output + 25 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO26 + Port Set Output + 26 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO27 + Port Set Output + 27 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO28 + Port Set Output + 28 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO29 + Port Set Output + 29 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO30 + Port Set Output + 30 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO31 + Port Set Output + 31 + 1 write-only @@ -128508,10 +142550,599 @@ 0xFFFFFFFF - PTCO + PTCO0 Port Clear Output 0 - 32 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO1 + Port Clear Output + 1 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO2 + Port Clear Output + 2 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO3 + Port Clear Output + 3 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO4 + Port Clear Output + 4 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO5 + Port Clear Output + 5 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO6 + Port Clear Output + 6 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO7 + Port Clear Output + 7 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO8 + Port Clear Output + 8 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO9 + Port Clear Output + 9 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO10 + Port Clear Output + 10 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO11 + Port Clear Output + 11 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO12 + Port Clear Output + 12 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO13 + Port Clear Output + 13 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO14 + Port Clear Output + 14 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO15 + Port Clear Output + 15 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO16 + Port Clear Output + 16 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO17 + Port Clear Output + 17 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO18 + Port Clear Output + 18 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO19 + Port Clear Output + 19 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO20 + Port Clear Output + 20 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO21 + Port Clear Output + 21 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO22 + Port Clear Output + 22 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO23 + Port Clear Output + 23 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO24 + Port Clear Output + 24 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO25 + Port Clear Output + 25 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO26 + Port Clear Output + 26 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO27 + Port Clear Output + 27 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO28 + Port Clear Output + 28 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO29 + Port Clear Output + 29 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO30 + Port Clear Output + 30 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO31 + Port Clear Output + 31 + 1 write-only @@ -128538,10 +143169,599 @@ 0xFFFFFFFF - PTTO + PTTO0 Port Toggle Output 0 - 32 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO1 + Port Toggle Output + 1 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO2 + Port Toggle Output + 2 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO3 + Port Toggle Output + 3 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO4 + Port Toggle Output + 4 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO5 + Port Toggle Output + 5 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO6 + Port Toggle Output + 6 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO7 + Port Toggle Output + 7 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO8 + Port Toggle Output + 8 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO9 + Port Toggle Output + 9 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO10 + Port Toggle Output + 10 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO11 + Port Toggle Output + 11 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO12 + Port Toggle Output + 12 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO13 + Port Toggle Output + 13 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO14 + Port Toggle Output + 14 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO15 + Port Toggle Output + 15 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO16 + Port Toggle Output + 16 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO17 + Port Toggle Output + 17 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO18 + Port Toggle Output + 18 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO19 + Port Toggle Output + 19 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO20 + Port Toggle Output + 20 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO21 + Port Toggle Output + 21 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO22 + Port Toggle Output + 22 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO23 + Port Toggle Output + 23 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO24 + Port Toggle Output + 24 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO25 + Port Toggle Output + 25 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO26 + Port Toggle Output + 26 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO27 + Port Toggle Output + 27 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO28 + Port Toggle Output + 28 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO29 + Port Toggle Output + 29 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO30 + Port Toggle Output + 30 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO31 + Port Toggle Output + 31 + 1 write-only @@ -128568,10 +143788,599 @@ 0xFFFFFFFF - PDI + PDI0 Port Data Input 0 - 32 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI1 + Port Data Input + 1 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI2 + Port Data Input + 2 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI3 + Port Data Input + 3 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI4 + Port Data Input + 4 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI5 + Port Data Input + 5 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI6 + Port Data Input + 6 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI7 + Port Data Input + 7 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI8 + Port Data Input + 8 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI9 + Port Data Input + 9 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI10 + Port Data Input + 10 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI11 + Port Data Input + 11 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI12 + Port Data Input + 12 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI13 + Port Data Input + 13 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI14 + Port Data Input + 14 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI15 + Port Data Input + 15 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI16 + Port Data Input + 16 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI17 + Port Data Input + 17 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI18 + Port Data Input + 18 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI19 + Port Data Input + 19 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI20 + Port Data Input + 20 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI21 + Port Data Input + 21 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI22 + Port Data Input + 22 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI23 + Port Data Input + 23 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI24 + Port Data Input + 24 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI25 + Port Data Input + 25 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI26 + Port Data Input + 26 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI27 + Port Data Input + 27 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI28 + Port Data Input + 28 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI29 + Port Data Input + 29 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI30 + Port Data Input + 30 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI31 + Port Data Input + 31 + 1 read-only @@ -128598,10 +144407,599 @@ 0xFFFFFFFF - PDD + PDD0 Port Data Direction 0 - 32 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD1 + Port Data Direction + 1 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD2 + Port Data Direction + 2 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD3 + Port Data Direction + 3 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD4 + Port Data Direction + 4 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD5 + Port Data Direction + 5 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD6 + Port Data Direction + 6 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD7 + Port Data Direction + 7 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD8 + Port Data Direction + 8 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD9 + Port Data Direction + 9 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD10 + Port Data Direction + 10 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD11 + Port Data Direction + 11 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD12 + Port Data Direction + 12 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD13 + Port Data Direction + 13 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD14 + Port Data Direction + 14 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD15 + Port Data Direction + 15 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD16 + Port Data Direction + 16 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD17 + Port Data Direction + 17 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD18 + Port Data Direction + 18 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD19 + Port Data Direction + 19 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD20 + Port Data Direction + 20 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD21 + Port Data Direction + 21 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD22 + Port Data Direction + 22 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD23 + Port Data Direction + 23 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD24 + Port Data Direction + 24 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD25 + Port Data Direction + 25 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD26 + Port Data Direction + 26 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD27 + Port Data Direction + 27 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD28 + Port Data Direction + 28 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD29 + Port Data Direction + 29 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD30 + Port Data Direction + 30 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD31 + Port Data Direction + 31 + 1 read-write @@ -128646,10 +145044,599 @@ 0xFFFFFFFF - PDO + PDO0 Port Data Output 0 - 32 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO1 + Port Data Output + 1 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO2 + Port Data Output + 2 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO3 + Port Data Output + 3 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO4 + Port Data Output + 4 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO5 + Port Data Output + 5 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO6 + Port Data Output + 6 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO7 + Port Data Output + 7 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO8 + Port Data Output + 8 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO9 + Port Data Output + 9 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO10 + Port Data Output + 10 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO11 + Port Data Output + 11 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO12 + Port Data Output + 12 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO13 + Port Data Output + 13 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO14 + Port Data Output + 14 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO15 + Port Data Output + 15 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO16 + Port Data Output + 16 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO17 + Port Data Output + 17 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO18 + Port Data Output + 18 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO19 + Port Data Output + 19 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO20 + Port Data Output + 20 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO21 + Port Data Output + 21 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO22 + Port Data Output + 22 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO23 + Port Data Output + 23 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO24 + Port Data Output + 24 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO25 + Port Data Output + 25 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO26 + Port Data Output + 26 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO27 + Port Data Output + 27 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO28 + Port Data Output + 28 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO29 + Port Data Output + 29 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO30 + Port Data Output + 30 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO31 + Port Data Output + 31 + 1 read-write @@ -128676,10 +145663,599 @@ 0xFFFFFFFF - PTSO + PTSO0 Port Set Output 0 - 32 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO1 + Port Set Output + 1 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO2 + Port Set Output + 2 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO3 + Port Set Output + 3 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO4 + Port Set Output + 4 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO5 + Port Set Output + 5 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO6 + Port Set Output + 6 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO7 + Port Set Output + 7 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO8 + Port Set Output + 8 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO9 + Port Set Output + 9 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO10 + Port Set Output + 10 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO11 + Port Set Output + 11 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO12 + Port Set Output + 12 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO13 + Port Set Output + 13 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO14 + Port Set Output + 14 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO15 + Port Set Output + 15 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO16 + Port Set Output + 16 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO17 + Port Set Output + 17 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO18 + Port Set Output + 18 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO19 + Port Set Output + 19 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO20 + Port Set Output + 20 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO21 + Port Set Output + 21 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO22 + Port Set Output + 22 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO23 + Port Set Output + 23 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO24 + Port Set Output + 24 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO25 + Port Set Output + 25 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO26 + Port Set Output + 26 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO27 + Port Set Output + 27 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO28 + Port Set Output + 28 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO29 + Port Set Output + 29 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO30 + Port Set Output + 30 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO31 + Port Set Output + 31 + 1 write-only @@ -128706,10 +146282,599 @@ 0xFFFFFFFF - PTCO + PTCO0 Port Clear Output 0 - 32 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO1 + Port Clear Output + 1 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO2 + Port Clear Output + 2 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO3 + Port Clear Output + 3 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO4 + Port Clear Output + 4 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO5 + Port Clear Output + 5 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO6 + Port Clear Output + 6 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO7 + Port Clear Output + 7 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO8 + Port Clear Output + 8 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO9 + Port Clear Output + 9 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO10 + Port Clear Output + 10 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO11 + Port Clear Output + 11 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO12 + Port Clear Output + 12 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO13 + Port Clear Output + 13 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO14 + Port Clear Output + 14 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO15 + Port Clear Output + 15 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO16 + Port Clear Output + 16 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO17 + Port Clear Output + 17 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO18 + Port Clear Output + 18 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO19 + Port Clear Output + 19 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO20 + Port Clear Output + 20 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO21 + Port Clear Output + 21 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO22 + Port Clear Output + 22 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO23 + Port Clear Output + 23 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO24 + Port Clear Output + 24 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO25 + Port Clear Output + 25 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO26 + Port Clear Output + 26 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO27 + Port Clear Output + 27 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO28 + Port Clear Output + 28 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO29 + Port Clear Output + 29 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO30 + Port Clear Output + 30 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO31 + Port Clear Output + 31 + 1 write-only @@ -128736,10 +146901,599 @@ 0xFFFFFFFF - PTTO + PTTO0 Port Toggle Output 0 - 32 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO1 + Port Toggle Output + 1 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO2 + Port Toggle Output + 2 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO3 + Port Toggle Output + 3 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO4 + Port Toggle Output + 4 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO5 + Port Toggle Output + 5 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO6 + Port Toggle Output + 6 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO7 + Port Toggle Output + 7 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO8 + Port Toggle Output + 8 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO9 + Port Toggle Output + 9 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO10 + Port Toggle Output + 10 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO11 + Port Toggle Output + 11 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO12 + Port Toggle Output + 12 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO13 + Port Toggle Output + 13 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO14 + Port Toggle Output + 14 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO15 + Port Toggle Output + 15 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO16 + Port Toggle Output + 16 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO17 + Port Toggle Output + 17 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO18 + Port Toggle Output + 18 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO19 + Port Toggle Output + 19 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO20 + Port Toggle Output + 20 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO21 + Port Toggle Output + 21 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO22 + Port Toggle Output + 22 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO23 + Port Toggle Output + 23 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO24 + Port Toggle Output + 24 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO25 + Port Toggle Output + 25 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO26 + Port Toggle Output + 26 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO27 + Port Toggle Output + 27 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO28 + Port Toggle Output + 28 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO29 + Port Toggle Output + 29 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO30 + Port Toggle Output + 30 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO31 + Port Toggle Output + 31 + 1 write-only @@ -128766,10 +147520,599 @@ 0xFFFFFFFF - PDI + PDI0 Port Data Input 0 - 32 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI1 + Port Data Input + 1 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI2 + Port Data Input + 2 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI3 + Port Data Input + 3 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI4 + Port Data Input + 4 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI5 + Port Data Input + 5 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI6 + Port Data Input + 6 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI7 + Port Data Input + 7 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI8 + Port Data Input + 8 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI9 + Port Data Input + 9 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI10 + Port Data Input + 10 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI11 + Port Data Input + 11 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI12 + Port Data Input + 12 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI13 + Port Data Input + 13 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI14 + Port Data Input + 14 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI15 + Port Data Input + 15 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI16 + Port Data Input + 16 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI17 + Port Data Input + 17 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI18 + Port Data Input + 18 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI19 + Port Data Input + 19 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI20 + Port Data Input + 20 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI21 + Port Data Input + 21 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI22 + Port Data Input + 22 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI23 + Port Data Input + 23 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI24 + Port Data Input + 24 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI25 + Port Data Input + 25 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI26 + Port Data Input + 26 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI27 + Port Data Input + 27 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI28 + Port Data Input + 28 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI29 + Port Data Input + 29 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI30 + Port Data Input + 30 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI31 + Port Data Input + 31 + 1 read-only @@ -128796,10 +148139,599 @@ 0xFFFFFFFF - PDD + PDD0 Port Data Direction 0 - 32 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD1 + Port Data Direction + 1 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD2 + Port Data Direction + 2 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD3 + Port Data Direction + 3 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD4 + Port Data Direction + 4 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD5 + Port Data Direction + 5 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD6 + Port Data Direction + 6 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD7 + Port Data Direction + 7 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD8 + Port Data Direction + 8 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD9 + Port Data Direction + 9 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD10 + Port Data Direction + 10 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD11 + Port Data Direction + 11 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD12 + Port Data Direction + 12 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD13 + Port Data Direction + 13 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD14 + Port Data Direction + 14 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD15 + Port Data Direction + 15 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD16 + Port Data Direction + 16 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD17 + Port Data Direction + 17 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD18 + Port Data Direction + 18 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD19 + Port Data Direction + 19 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD20 + Port Data Direction + 20 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD21 + Port Data Direction + 21 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD22 + Port Data Direction + 22 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD23 + Port Data Direction + 23 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD24 + Port Data Direction + 24 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD25 + Port Data Direction + 25 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD26 + Port Data Direction + 26 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD27 + Port Data Direction + 27 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD28 + Port Data Direction + 28 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD29 + Port Data Direction + 29 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD30 + Port Data Direction + 30 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD31 + Port Data Direction + 31 + 1 read-write @@ -128844,10 +148776,599 @@ 0xFFFFFFFF - PDO + PDO0 Port Data Output 0 - 32 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO1 + Port Data Output + 1 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO2 + Port Data Output + 2 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO3 + Port Data Output + 3 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO4 + Port Data Output + 4 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO5 + Port Data Output + 5 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO6 + Port Data Output + 6 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO7 + Port Data Output + 7 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO8 + Port Data Output + 8 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO9 + Port Data Output + 9 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO10 + Port Data Output + 10 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO11 + Port Data Output + 11 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO12 + Port Data Output + 12 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO13 + Port Data Output + 13 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO14 + Port Data Output + 14 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO15 + Port Data Output + 15 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO16 + Port Data Output + 16 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO17 + Port Data Output + 17 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO18 + Port Data Output + 18 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO19 + Port Data Output + 19 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO20 + Port Data Output + 20 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO21 + Port Data Output + 21 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO22 + Port Data Output + 22 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO23 + Port Data Output + 23 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO24 + Port Data Output + 24 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO25 + Port Data Output + 25 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO26 + Port Data Output + 26 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO27 + Port Data Output + 27 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO28 + Port Data Output + 28 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO29 + Port Data Output + 29 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO30 + Port Data Output + 30 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO31 + Port Data Output + 31 + 1 read-write @@ -128874,10 +149395,599 @@ 0xFFFFFFFF - PTSO + PTSO0 Port Set Output 0 - 32 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO1 + Port Set Output + 1 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO2 + Port Set Output + 2 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO3 + Port Set Output + 3 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO4 + Port Set Output + 4 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO5 + Port Set Output + 5 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO6 + Port Set Output + 6 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO7 + Port Set Output + 7 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO8 + Port Set Output + 8 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO9 + Port Set Output + 9 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO10 + Port Set Output + 10 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO11 + Port Set Output + 11 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO12 + Port Set Output + 12 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO13 + Port Set Output + 13 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO14 + Port Set Output + 14 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO15 + Port Set Output + 15 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO16 + Port Set Output + 16 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO17 + Port Set Output + 17 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO18 + Port Set Output + 18 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO19 + Port Set Output + 19 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO20 + Port Set Output + 20 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO21 + Port Set Output + 21 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO22 + Port Set Output + 22 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO23 + Port Set Output + 23 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO24 + Port Set Output + 24 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO25 + Port Set Output + 25 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO26 + Port Set Output + 26 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO27 + Port Set Output + 27 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO28 + Port Set Output + 28 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO29 + Port Set Output + 29 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO30 + Port Set Output + 30 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO31 + Port Set Output + 31 + 1 write-only @@ -128904,10 +150014,599 @@ 0xFFFFFFFF - PTCO + PTCO0 Port Clear Output 0 - 32 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO1 + Port Clear Output + 1 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO2 + Port Clear Output + 2 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO3 + Port Clear Output + 3 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO4 + Port Clear Output + 4 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO5 + Port Clear Output + 5 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO6 + Port Clear Output + 6 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO7 + Port Clear Output + 7 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO8 + Port Clear Output + 8 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO9 + Port Clear Output + 9 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO10 + Port Clear Output + 10 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO11 + Port Clear Output + 11 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO12 + Port Clear Output + 12 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO13 + Port Clear Output + 13 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO14 + Port Clear Output + 14 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO15 + Port Clear Output + 15 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO16 + Port Clear Output + 16 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO17 + Port Clear Output + 17 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO18 + Port Clear Output + 18 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO19 + Port Clear Output + 19 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO20 + Port Clear Output + 20 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO21 + Port Clear Output + 21 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO22 + Port Clear Output + 22 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO23 + Port Clear Output + 23 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO24 + Port Clear Output + 24 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO25 + Port Clear Output + 25 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO26 + Port Clear Output + 26 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO27 + Port Clear Output + 27 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO28 + Port Clear Output + 28 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO29 + Port Clear Output + 29 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO30 + Port Clear Output + 30 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO31 + Port Clear Output + 31 + 1 write-only @@ -128934,10 +150633,599 @@ 0xFFFFFFFF - PTTO + PTTO0 Port Toggle Output 0 - 32 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO1 + Port Toggle Output + 1 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO2 + Port Toggle Output + 2 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO3 + Port Toggle Output + 3 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO4 + Port Toggle Output + 4 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO5 + Port Toggle Output + 5 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO6 + Port Toggle Output + 6 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO7 + Port Toggle Output + 7 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO8 + Port Toggle Output + 8 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO9 + Port Toggle Output + 9 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO10 + Port Toggle Output + 10 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO11 + Port Toggle Output + 11 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO12 + Port Toggle Output + 12 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO13 + Port Toggle Output + 13 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO14 + Port Toggle Output + 14 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO15 + Port Toggle Output + 15 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO16 + Port Toggle Output + 16 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO17 + Port Toggle Output + 17 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO18 + Port Toggle Output + 18 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO19 + Port Toggle Output + 19 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO20 + Port Toggle Output + 20 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO21 + Port Toggle Output + 21 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO22 + Port Toggle Output + 22 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO23 + Port Toggle Output + 23 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO24 + Port Toggle Output + 24 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO25 + Port Toggle Output + 25 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO26 + Port Toggle Output + 26 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO27 + Port Toggle Output + 27 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO28 + Port Toggle Output + 28 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO29 + Port Toggle Output + 29 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO30 + Port Toggle Output + 30 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO31 + Port Toggle Output + 31 + 1 write-only @@ -128964,10 +151252,599 @@ 0xFFFFFFFF - PDI + PDI0 Port Data Input 0 - 32 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI1 + Port Data Input + 1 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI2 + Port Data Input + 2 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI3 + Port Data Input + 3 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI4 + Port Data Input + 4 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI5 + Port Data Input + 5 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI6 + Port Data Input + 6 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI7 + Port Data Input + 7 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI8 + Port Data Input + 8 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI9 + Port Data Input + 9 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI10 + Port Data Input + 10 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI11 + Port Data Input + 11 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI12 + Port Data Input + 12 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI13 + Port Data Input + 13 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI14 + Port Data Input + 14 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI15 + Port Data Input + 15 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI16 + Port Data Input + 16 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI17 + Port Data Input + 17 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI18 + Port Data Input + 18 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI19 + Port Data Input + 19 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI20 + Port Data Input + 20 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI21 + Port Data Input + 21 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI22 + Port Data Input + 22 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI23 + Port Data Input + 23 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI24 + Port Data Input + 24 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI25 + Port Data Input + 25 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI26 + Port Data Input + 26 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI27 + Port Data Input + 27 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI28 + Port Data Input + 28 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI29 + Port Data Input + 29 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI30 + Port Data Input + 30 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI31 + Port Data Input + 31 + 1 read-only @@ -128994,10 +151871,599 @@ 0xFFFFFFFF - PDD + PDD0 Port Data Direction 0 - 32 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD1 + Port Data Direction + 1 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD2 + Port Data Direction + 2 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD3 + Port Data Direction + 3 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD4 + Port Data Direction + 4 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD5 + Port Data Direction + 5 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD6 + Port Data Direction + 6 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD7 + Port Data Direction + 7 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD8 + Port Data Direction + 8 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD9 + Port Data Direction + 9 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD10 + Port Data Direction + 10 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD11 + Port Data Direction + 11 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD12 + Port Data Direction + 12 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD13 + Port Data Direction + 13 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD14 + Port Data Direction + 14 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD15 + Port Data Direction + 15 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD16 + Port Data Direction + 16 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD17 + Port Data Direction + 17 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD18 + Port Data Direction + 18 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD19 + Port Data Direction + 19 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD20 + Port Data Direction + 20 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD21 + Port Data Direction + 21 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD22 + Port Data Direction + 22 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD23 + Port Data Direction + 23 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD24 + Port Data Direction + 24 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD25 + Port Data Direction + 25 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD26 + Port Data Direction + 26 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD27 + Port Data Direction + 27 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD28 + Port Data Direction + 28 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD29 + Port Data Direction + 29 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD30 + Port Data Direction + 30 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD31 + Port Data Direction + 31 + 1 read-write @@ -129042,10 +152508,599 @@ 0xFFFFFFFF - PDO + PDO0 Port Data Output 0 - 32 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO1 + Port Data Output + 1 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO2 + Port Data Output + 2 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO3 + Port Data Output + 3 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO4 + Port Data Output + 4 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO5 + Port Data Output + 5 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO6 + Port Data Output + 6 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO7 + Port Data Output + 7 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO8 + Port Data Output + 8 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO9 + Port Data Output + 9 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO10 + Port Data Output + 10 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO11 + Port Data Output + 11 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO12 + Port Data Output + 12 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO13 + Port Data Output + 13 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO14 + Port Data Output + 14 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO15 + Port Data Output + 15 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO16 + Port Data Output + 16 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO17 + Port Data Output + 17 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO18 + Port Data Output + 18 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO19 + Port Data Output + 19 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO20 + Port Data Output + 20 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO21 + Port Data Output + 21 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO22 + Port Data Output + 22 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO23 + Port Data Output + 23 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO24 + Port Data Output + 24 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO25 + Port Data Output + 25 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO26 + Port Data Output + 26 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO27 + Port Data Output + 27 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO28 + Port Data Output + 28 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO29 + Port Data Output + 29 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO30 + Port Data Output + 30 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO31 + Port Data Output + 31 + 1 read-write @@ -129072,10 +153127,599 @@ 0xFFFFFFFF - PTSO + PTSO0 Port Set Output 0 - 32 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO1 + Port Set Output + 1 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO2 + Port Set Output + 2 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO3 + Port Set Output + 3 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO4 + Port Set Output + 4 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO5 + Port Set Output + 5 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO6 + Port Set Output + 6 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO7 + Port Set Output + 7 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO8 + Port Set Output + 8 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO9 + Port Set Output + 9 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO10 + Port Set Output + 10 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO11 + Port Set Output + 11 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO12 + Port Set Output + 12 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO13 + Port Set Output + 13 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO14 + Port Set Output + 14 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO15 + Port Set Output + 15 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO16 + Port Set Output + 16 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO17 + Port Set Output + 17 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO18 + Port Set Output + 18 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO19 + Port Set Output + 19 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO20 + Port Set Output + 20 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO21 + Port Set Output + 21 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO22 + Port Set Output + 22 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO23 + Port Set Output + 23 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO24 + Port Set Output + 24 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO25 + Port Set Output + 25 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO26 + Port Set Output + 26 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO27 + Port Set Output + 27 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO28 + Port Set Output + 28 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO29 + Port Set Output + 29 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO30 + Port Set Output + 30 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO31 + Port Set Output + 31 + 1 write-only @@ -129102,10 +153746,599 @@ 0xFFFFFFFF - PTCO + PTCO0 Port Clear Output 0 - 32 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO1 + Port Clear Output + 1 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO2 + Port Clear Output + 2 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO3 + Port Clear Output + 3 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO4 + Port Clear Output + 4 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO5 + Port Clear Output + 5 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO6 + Port Clear Output + 6 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO7 + Port Clear Output + 7 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO8 + Port Clear Output + 8 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO9 + Port Clear Output + 9 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO10 + Port Clear Output + 10 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO11 + Port Clear Output + 11 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO12 + Port Clear Output + 12 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO13 + Port Clear Output + 13 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO14 + Port Clear Output + 14 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO15 + Port Clear Output + 15 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO16 + Port Clear Output + 16 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO17 + Port Clear Output + 17 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO18 + Port Clear Output + 18 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO19 + Port Clear Output + 19 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO20 + Port Clear Output + 20 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO21 + Port Clear Output + 21 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO22 + Port Clear Output + 22 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO23 + Port Clear Output + 23 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO24 + Port Clear Output + 24 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO25 + Port Clear Output + 25 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO26 + Port Clear Output + 26 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO27 + Port Clear Output + 27 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO28 + Port Clear Output + 28 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO29 + Port Clear Output + 29 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO30 + Port Clear Output + 30 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO31 + Port Clear Output + 31 + 1 write-only @@ -129132,10 +154365,599 @@ 0xFFFFFFFF - PTTO + PTTO0 Port Toggle Output 0 - 32 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO1 + Port Toggle Output + 1 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO2 + Port Toggle Output + 2 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO3 + Port Toggle Output + 3 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO4 + Port Toggle Output + 4 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO5 + Port Toggle Output + 5 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO6 + Port Toggle Output + 6 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO7 + Port Toggle Output + 7 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO8 + Port Toggle Output + 8 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO9 + Port Toggle Output + 9 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO10 + Port Toggle Output + 10 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO11 + Port Toggle Output + 11 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO12 + Port Toggle Output + 12 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO13 + Port Toggle Output + 13 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO14 + Port Toggle Output + 14 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO15 + Port Toggle Output + 15 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO16 + Port Toggle Output + 16 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO17 + Port Toggle Output + 17 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO18 + Port Toggle Output + 18 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO19 + Port Toggle Output + 19 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO20 + Port Toggle Output + 20 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO21 + Port Toggle Output + 21 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO22 + Port Toggle Output + 22 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO23 + Port Toggle Output + 23 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO24 + Port Toggle Output + 24 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO25 + Port Toggle Output + 25 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO26 + Port Toggle Output + 26 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO27 + Port Toggle Output + 27 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO28 + Port Toggle Output + 28 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO29 + Port Toggle Output + 29 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO30 + Port Toggle Output + 30 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO31 + Port Toggle Output + 31 + 1 write-only @@ -129162,10 +154984,599 @@ 0xFFFFFFFF - PDI + PDI0 Port Data Input 0 - 32 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI1 + Port Data Input + 1 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI2 + Port Data Input + 2 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI3 + Port Data Input + 3 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI4 + Port Data Input + 4 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI5 + Port Data Input + 5 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI6 + Port Data Input + 6 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI7 + Port Data Input + 7 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI8 + Port Data Input + 8 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI9 + Port Data Input + 9 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI10 + Port Data Input + 10 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI11 + Port Data Input + 11 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI12 + Port Data Input + 12 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI13 + Port Data Input + 13 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI14 + Port Data Input + 14 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI15 + Port Data Input + 15 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI16 + Port Data Input + 16 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI17 + Port Data Input + 17 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI18 + Port Data Input + 18 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI19 + Port Data Input + 19 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI20 + Port Data Input + 20 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI21 + Port Data Input + 21 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI22 + Port Data Input + 22 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI23 + Port Data Input + 23 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI24 + Port Data Input + 24 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI25 + Port Data Input + 25 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI26 + Port Data Input + 26 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI27 + Port Data Input + 27 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI28 + Port Data Input + 28 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI29 + Port Data Input + 29 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI30 + Port Data Input + 30 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI31 + Port Data Input + 31 + 1 read-only @@ -129192,10 +155603,599 @@ 0xFFFFFFFF - PDD + PDD0 Port Data Direction 0 - 32 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD1 + Port Data Direction + 1 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD2 + Port Data Direction + 2 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD3 + Port Data Direction + 3 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD4 + Port Data Direction + 4 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD5 + Port Data Direction + 5 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD6 + Port Data Direction + 6 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD7 + Port Data Direction + 7 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD8 + Port Data Direction + 8 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD9 + Port Data Direction + 9 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD10 + Port Data Direction + 10 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD11 + Port Data Direction + 11 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD12 + Port Data Direction + 12 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD13 + Port Data Direction + 13 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD14 + Port Data Direction + 14 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD15 + Port Data Direction + 15 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD16 + Port Data Direction + 16 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD17 + Port Data Direction + 17 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD18 + Port Data Direction + 18 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD19 + Port Data Direction + 19 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD20 + Port Data Direction + 20 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD21 + Port Data Direction + 21 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD22 + Port Data Direction + 22 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD23 + Port Data Direction + 23 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD24 + Port Data Direction + 24 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD25 + Port Data Direction + 25 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD26 + Port Data Direction + 26 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD27 + Port Data Direction + 27 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD28 + Port Data Direction + 28 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD29 + Port Data Direction + 29 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD30 + Port Data Direction + 30 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD31 + Port Data Direction + 31 + 1 read-write @@ -129240,10 +156240,599 @@ 0xFFFFFFFF - PDO + PDO0 Port Data Output 0 - 32 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO1 + Port Data Output + 1 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO2 + Port Data Output + 2 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO3 + Port Data Output + 3 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO4 + Port Data Output + 4 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO5 + Port Data Output + 5 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO6 + Port Data Output + 6 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO7 + Port Data Output + 7 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO8 + Port Data Output + 8 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO9 + Port Data Output + 9 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO10 + Port Data Output + 10 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO11 + Port Data Output + 11 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO12 + Port Data Output + 12 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO13 + Port Data Output + 13 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO14 + Port Data Output + 14 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO15 + Port Data Output + 15 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO16 + Port Data Output + 16 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO17 + Port Data Output + 17 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO18 + Port Data Output + 18 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO19 + Port Data Output + 19 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO20 + Port Data Output + 20 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO21 + Port Data Output + 21 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO22 + Port Data Output + 22 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO23 + Port Data Output + 23 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO24 + Port Data Output + 24 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO25 + Port Data Output + 25 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO26 + Port Data Output + 26 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO27 + Port Data Output + 27 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO28 + Port Data Output + 28 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO29 + Port Data Output + 29 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO30 + Port Data Output + 30 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO31 + Port Data Output + 31 + 1 read-write @@ -129270,10 +156859,599 @@ 0xFFFFFFFF - PTSO + PTSO0 Port Set Output 0 - 32 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO1 + Port Set Output + 1 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO2 + Port Set Output + 2 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO3 + Port Set Output + 3 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO4 + Port Set Output + 4 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO5 + Port Set Output + 5 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO6 + Port Set Output + 6 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO7 + Port Set Output + 7 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO8 + Port Set Output + 8 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO9 + Port Set Output + 9 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO10 + Port Set Output + 10 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO11 + Port Set Output + 11 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO12 + Port Set Output + 12 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO13 + Port Set Output + 13 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO14 + Port Set Output + 14 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO15 + Port Set Output + 15 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO16 + Port Set Output + 16 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO17 + Port Set Output + 17 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO18 + Port Set Output + 18 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO19 + Port Set Output + 19 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO20 + Port Set Output + 20 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO21 + Port Set Output + 21 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO22 + Port Set Output + 22 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO23 + Port Set Output + 23 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO24 + Port Set Output + 24 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO25 + Port Set Output + 25 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO26 + Port Set Output + 26 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO27 + Port Set Output + 27 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO28 + Port Set Output + 28 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO29 + Port Set Output + 29 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO30 + Port Set Output + 30 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO31 + Port Set Output + 31 + 1 write-only @@ -129300,10 +157478,599 @@ 0xFFFFFFFF - PTCO + PTCO0 Port Clear Output 0 - 32 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO1 + Port Clear Output + 1 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO2 + Port Clear Output + 2 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO3 + Port Clear Output + 3 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO4 + Port Clear Output + 4 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO5 + Port Clear Output + 5 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO6 + Port Clear Output + 6 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO7 + Port Clear Output + 7 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO8 + Port Clear Output + 8 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO9 + Port Clear Output + 9 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO10 + Port Clear Output + 10 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO11 + Port Clear Output + 11 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO12 + Port Clear Output + 12 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO13 + Port Clear Output + 13 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO14 + Port Clear Output + 14 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO15 + Port Clear Output + 15 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO16 + Port Clear Output + 16 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO17 + Port Clear Output + 17 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO18 + Port Clear Output + 18 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO19 + Port Clear Output + 19 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO20 + Port Clear Output + 20 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO21 + Port Clear Output + 21 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO22 + Port Clear Output + 22 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO23 + Port Clear Output + 23 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO24 + Port Clear Output + 24 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO25 + Port Clear Output + 25 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO26 + Port Clear Output + 26 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO27 + Port Clear Output + 27 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO28 + Port Clear Output + 28 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO29 + Port Clear Output + 29 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO30 + Port Clear Output + 30 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO31 + Port Clear Output + 31 + 1 write-only @@ -129330,10 +158097,599 @@ 0xFFFFFFFF - PTTO + PTTO0 Port Toggle Output 0 - 32 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO1 + Port Toggle Output + 1 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO2 + Port Toggle Output + 2 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO3 + Port Toggle Output + 3 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO4 + Port Toggle Output + 4 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO5 + Port Toggle Output + 5 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO6 + Port Toggle Output + 6 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO7 + Port Toggle Output + 7 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO8 + Port Toggle Output + 8 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO9 + Port Toggle Output + 9 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO10 + Port Toggle Output + 10 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO11 + Port Toggle Output + 11 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO12 + Port Toggle Output + 12 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO13 + Port Toggle Output + 13 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO14 + Port Toggle Output + 14 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO15 + Port Toggle Output + 15 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO16 + Port Toggle Output + 16 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO17 + Port Toggle Output + 17 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO18 + Port Toggle Output + 18 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO19 + Port Toggle Output + 19 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO20 + Port Toggle Output + 20 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO21 + Port Toggle Output + 21 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO22 + Port Toggle Output + 22 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO23 + Port Toggle Output + 23 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO24 + Port Toggle Output + 24 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO25 + Port Toggle Output + 25 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO26 + Port Toggle Output + 26 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO27 + Port Toggle Output + 27 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO28 + Port Toggle Output + 28 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO29 + Port Toggle Output + 29 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO30 + Port Toggle Output + 30 + 1 + write-only + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO31 + Port Toggle Output + 31 + 1 write-only @@ -129360,10 +158716,599 @@ 0xFFFFFFFF - PDI + PDI0 Port Data Input 0 - 32 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI1 + Port Data Input + 1 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI2 + Port Data Input + 2 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI3 + Port Data Input + 3 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI4 + Port Data Input + 4 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI5 + Port Data Input + 5 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI6 + Port Data Input + 6 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI7 + Port Data Input + 7 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI8 + Port Data Input + 8 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI9 + Port Data Input + 9 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI10 + Port Data Input + 10 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI11 + Port Data Input + 11 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI12 + Port Data Input + 12 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI13 + Port Data Input + 13 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI14 + Port Data Input + 14 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI15 + Port Data Input + 15 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI16 + Port Data Input + 16 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI17 + Port Data Input + 17 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI18 + Port Data Input + 18 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI19 + Port Data Input + 19 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI20 + Port Data Input + 20 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI21 + Port Data Input + 21 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI22 + Port Data Input + 22 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI23 + Port Data Input + 23 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI24 + Port Data Input + 24 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI25 + Port Data Input + 25 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI26 + Port Data Input + 26 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI27 + Port Data Input + 27 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI28 + Port Data Input + 28 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI29 + Port Data Input + 29 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI30 + Port Data Input + 30 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI31 + Port Data Input + 31 + 1 read-only @@ -129390,10 +159335,599 @@ 0xFFFFFFFF - PDD + PDD0 Port Data Direction 0 - 32 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD1 + Port Data Direction + 1 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD2 + Port Data Direction + 2 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD3 + Port Data Direction + 3 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD4 + Port Data Direction + 4 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD5 + Port Data Direction + 5 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD6 + Port Data Direction + 6 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD7 + Port Data Direction + 7 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD8 + Port Data Direction + 8 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD9 + Port Data Direction + 9 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD10 + Port Data Direction + 10 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD11 + Port Data Direction + 11 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD12 + Port Data Direction + 12 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD13 + Port Data Direction + 13 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD14 + Port Data Direction + 14 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD15 + Port Data Direction + 15 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD16 + Port Data Direction + 16 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD17 + Port Data Direction + 17 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD18 + Port Data Direction + 18 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD19 + Port Data Direction + 19 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD20 + Port Data Direction + 20 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD21 + Port Data Direction + 21 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD22 + Port Data Direction + 22 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD23 + Port Data Direction + 23 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD24 + Port Data Direction + 24 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD25 + Port Data Direction + 25 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD26 + Port Data Direction + 26 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD27 + Port Data Direction + 27 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD28 + Port Data Direction + 28 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD29 + Port Data Direction + 29 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD30 + Port Data Direction + 30 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD31 + Port Data Direction + 31 + 1 read-write diff --git a/ext/hal/nxp/mcux/devices/MK64F12/MK64F12_features.h b/ext/hal/nxp/mcux/devices/MK64F12/MK64F12_features.h index 277f1c60bf3..a0a4d29e430 100644 --- a/ext/hal/nxp/mcux/devices/MK64F12/MK64F12_features.h +++ b/ext/hal/nxp/mcux/devices/MK64F12/MK64F12_features.h @@ -1,37 +1,15 @@ /* ** ################################################################### ** Version: rev. 2.15, 2016-03-21 -** Build: b170228 +** Build: b180801 ** ** Abstract: ** Chip specific module features. ** ** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2017 NXP -** Redistribution and use in source and binary forms, with or without modification, -** are permitted provided that the following conditions are met: +** Copyright 2016-2018 NXP ** -** o Redistributions of source code must retain the above copyright notice, this list -** of conditions and the following disclaimer. -** -** o Redistributions in binary form must reproduce the above copyright notice, this -** list of conditions and the following disclaimer in the documentation and/or -** other materials provided with the distribution. -** -** o Neither the name of the copyright holder nor the names of its -** contributors may be used to endorse or promote products derived from this -** software without specific prior written permission. -** -** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** SPDX-License-Identifier: BSD-3-Clause ** ** http: www.nxp.com ** mail: support@nxp.com @@ -95,24 +73,12 @@ #if defined(CPU_MK64FN1M0CAJ12) || defined(CPU_MK64FN1M0VDC12) || defined(CPU_MK64FN1M0VLQ12) || defined(CPU_MK64FN1M0VMD12) || \ defined(CPU_MK64FX512VDC12) || defined(CPU_MK64FX512VLQ12) || defined(CPU_MK64FX512VMD12) - /* @brief ACMP availability on the SoC. */ - #define FSL_FEATURE_SOC_ACMP_COUNT (0) /* @brief ADC16 availability on the SoC. */ #define FSL_FEATURE_SOC_ADC16_COUNT (2) - /* @brief ADC12 availability on the SoC. */ - #define FSL_FEATURE_SOC_ADC12_COUNT (0) - /* @brief AFE availability on the SoC. */ - #define FSL_FEATURE_SOC_AFE_COUNT (0) /* @brief AIPS availability on the SoC. */ #define FSL_FEATURE_SOC_AIPS_COUNT (2) - /* @brief AOI availability on the SoC. */ - #define FSL_FEATURE_SOC_AOI_COUNT (0) /* @brief AXBS availability on the SoC. */ #define FSL_FEATURE_SOC_AXBS_COUNT (1) - /* @brief ASMC availability on the SoC. */ - #define FSL_FEATURE_SOC_ASMC_COUNT (0) - /* @brief CADC availability on the SoC. */ - #define FSL_FEATURE_SOC_CADC_COUNT (0) /* @brief FLEXCAN availability on the SoC. */ #define FSL_FEATURE_SOC_FLEXCAN_COUNT (1) /* @brief MMCAU availability on the SoC. */ @@ -121,154 +87,54 @@ #define FSL_FEATURE_SOC_CMP_COUNT (3) /* @brief CMT availability on the SoC. */ #define FSL_FEATURE_SOC_CMT_COUNT (1) - /* @brief CNC availability on the SoC. */ - #define FSL_FEATURE_SOC_CNC_COUNT (0) /* @brief CRC availability on the SoC. */ #define FSL_FEATURE_SOC_CRC_COUNT (1) /* @brief DAC availability on the SoC. */ #define FSL_FEATURE_SOC_DAC_COUNT (2) - /* @brief DAC32 availability on the SoC. */ - #define FSL_FEATURE_SOC_DAC32_COUNT (0) - /* @brief DCDC availability on the SoC. */ - #define FSL_FEATURE_SOC_DCDC_COUNT (0) - /* @brief DDR availability on the SoC. */ - #define FSL_FEATURE_SOC_DDR_COUNT (0) - /* @brief DMA availability on the SoC. */ - #define FSL_FEATURE_SOC_DMA_COUNT (0) /* @brief EDMA availability on the SoC. */ #define FSL_FEATURE_SOC_EDMA_COUNT (1) /* @brief DMAMUX availability on the SoC. */ #define FSL_FEATURE_SOC_DMAMUX_COUNT (1) - /* @brief DRY availability on the SoC. */ - #define FSL_FEATURE_SOC_DRY_COUNT (0) /* @brief DSPI availability on the SoC. */ #define FSL_FEATURE_SOC_DSPI_COUNT (3) - /* @brief EMVSIM availability on the SoC. */ - #define FSL_FEATURE_SOC_EMVSIM_COUNT (0) - /* @brief ENC availability on the SoC. */ - #define FSL_FEATURE_SOC_ENC_COUNT (0) /* @brief ENET availability on the SoC. */ #define FSL_FEATURE_SOC_ENET_COUNT (1) /* @brief EWM availability on the SoC. */ #define FSL_FEATURE_SOC_EWM_COUNT (1) /* @brief FB availability on the SoC. */ #define FSL_FEATURE_SOC_FB_COUNT (1) - /* @brief FGPIO availability on the SoC. */ - #define FSL_FEATURE_SOC_FGPIO_COUNT (0) - /* @brief FLEXIO availability on the SoC. */ - #define FSL_FEATURE_SOC_FLEXIO_COUNT (0) /* @brief FMC availability on the SoC. */ #define FSL_FEATURE_SOC_FMC_COUNT (1) - /* @brief FSKDT availability on the SoC. */ - #define FSL_FEATURE_SOC_FSKDT_COUNT (0) - /* @brief FTFA availability on the SoC. */ - #define FSL_FEATURE_SOC_FTFA_COUNT (0) /* @brief FTFE availability on the SoC. */ #define FSL_FEATURE_SOC_FTFE_COUNT (1) - /* @brief FTFL availability on the SoC. */ - #define FSL_FEATURE_SOC_FTFL_COUNT (0) /* @brief FTM availability on the SoC. */ #define FSL_FEATURE_SOC_FTM_COUNT (4) - /* @brief FTMRA availability on the SoC. */ - #define FSL_FEATURE_SOC_FTMRA_COUNT (0) - /* @brief FTMRE availability on the SoC. */ - #define FSL_FEATURE_SOC_FTMRE_COUNT (0) - /* @brief FTMRH availability on the SoC. */ - #define FSL_FEATURE_SOC_FTMRH_COUNT (0) /* @brief GPIO availability on the SoC. */ #define FSL_FEATURE_SOC_GPIO_COUNT (5) - /* @brief HSADC availability on the SoC. */ - #define FSL_FEATURE_SOC_HSADC_COUNT (0) /* @brief I2C availability on the SoC. */ #define FSL_FEATURE_SOC_I2C_COUNT (3) /* @brief I2S availability on the SoC. */ #define FSL_FEATURE_SOC_I2S_COUNT (1) - /* @brief ICS availability on the SoC. */ - #define FSL_FEATURE_SOC_ICS_COUNT (0) - /* @brief INTMUX availability on the SoC. */ - #define FSL_FEATURE_SOC_INTMUX_COUNT (0) - /* @brief IRQ availability on the SoC. */ - #define FSL_FEATURE_SOC_IRQ_COUNT (0) - /* @brief KBI availability on the SoC. */ - #define FSL_FEATURE_SOC_KBI_COUNT (0) - /* @brief SLCD availability on the SoC. */ - #define FSL_FEATURE_SOC_SLCD_COUNT (0) - /* @brief LCDC availability on the SoC. */ - #define FSL_FEATURE_SOC_LCDC_COUNT (0) - /* @brief LDO availability on the SoC. */ - #define FSL_FEATURE_SOC_LDO_COUNT (0) /* @brief LLWU availability on the SoC. */ #define FSL_FEATURE_SOC_LLWU_COUNT (1) - /* @brief LMEM availability on the SoC. */ - #define FSL_FEATURE_SOC_LMEM_COUNT (0) - /* @brief LPI2C availability on the SoC. */ - #define FSL_FEATURE_SOC_LPI2C_COUNT (0) - /* @brief LPIT availability on the SoC. */ - #define FSL_FEATURE_SOC_LPIT_COUNT (0) - /* @brief LPSCI availability on the SoC. */ - #define FSL_FEATURE_SOC_LPSCI_COUNT (0) - /* @brief LPSPI availability on the SoC. */ - #define FSL_FEATURE_SOC_LPSPI_COUNT (0) /* @brief LPTMR availability on the SoC. */ #define FSL_FEATURE_SOC_LPTMR_COUNT (1) - /* @brief LPTPM availability on the SoC. */ - #define FSL_FEATURE_SOC_LPTPM_COUNT (0) - /* @brief LPUART availability on the SoC. */ - #define FSL_FEATURE_SOC_LPUART_COUNT (0) - /* @brief LTC availability on the SoC. */ - #define FSL_FEATURE_SOC_LTC_COUNT (0) - /* @brief MC availability on the SoC. */ - #define FSL_FEATURE_SOC_MC_COUNT (0) /* @brief MCG availability on the SoC. */ #define FSL_FEATURE_SOC_MCG_COUNT (1) - /* @brief MCGLITE availability on the SoC. */ - #define FSL_FEATURE_SOC_MCGLITE_COUNT (0) /* @brief MCM availability on the SoC. */ #define FSL_FEATURE_SOC_MCM_COUNT (1) - /* @brief MMAU availability on the SoC. */ - #define FSL_FEATURE_SOC_MMAU_COUNT (0) - /* @brief MMDVSQ availability on the SoC. */ - #define FSL_FEATURE_SOC_MMDVSQ_COUNT (0) /* @brief SYSMPU availability on the SoC. */ #define FSL_FEATURE_SOC_SYSMPU_COUNT (1) - /* @brief MSCAN availability on the SoC. */ - #define FSL_FEATURE_SOC_MSCAN_COUNT (0) - /* @brief MSCM availability on the SoC. */ - #define FSL_FEATURE_SOC_MSCM_COUNT (0) - /* @brief MTB availability on the SoC. */ - #define FSL_FEATURE_SOC_MTB_COUNT (0) - /* @brief MTBDWT availability on the SoC. */ - #define FSL_FEATURE_SOC_MTBDWT_COUNT (0) - /* @brief MU availability on the SoC. */ - #define FSL_FEATURE_SOC_MU_COUNT (0) - /* @brief NFC availability on the SoC. */ - #define FSL_FEATURE_SOC_NFC_COUNT (0) - /* @brief OPAMP availability on the SoC. */ - #define FSL_FEATURE_SOC_OPAMP_COUNT (0) /* @brief OSC availability on the SoC. */ #define FSL_FEATURE_SOC_OSC_COUNT (1) - /* @brief OSC32 availability on the SoC. */ - #define FSL_FEATURE_SOC_OSC32_COUNT (0) - /* @brief OTFAD availability on the SoC. */ - #define FSL_FEATURE_SOC_OTFAD_COUNT (0) /* @brief PDB availability on the SoC. */ #define FSL_FEATURE_SOC_PDB_COUNT (1) - /* @brief PCC availability on the SoC. */ - #define FSL_FEATURE_SOC_PCC_COUNT (0) - /* @brief PGA availability on the SoC. */ - #define FSL_FEATURE_SOC_PGA_COUNT (0) /* @brief PIT availability on the SoC. */ #define FSL_FEATURE_SOC_PIT_COUNT (1) /* @brief PMC availability on the SoC. */ #define FSL_FEATURE_SOC_PMC_COUNT (1) /* @brief PORT availability on the SoC. */ #define FSL_FEATURE_SOC_PORT_COUNT (5) - /* @brief PWM availability on the SoC. */ - #define FSL_FEATURE_SOC_PWM_COUNT (0) - /* @brief PWT availability on the SoC. */ - #define FSL_FEATURE_SOC_PWT_COUNT (0) - /* @brief QuadSPI availability on the SoC. */ - #define FSL_FEATURE_SOC_QuadSPI_COUNT (0) /* @brief RCM availability on the SoC. */ #define FSL_FEATURE_SOC_RCM_COUNT (1) /* @brief RFSYS availability on the SoC. */ @@ -277,91 +143,31 @@ #define FSL_FEATURE_SOC_RFVBAT_COUNT (1) /* @brief RNG availability on the SoC. */ #define FSL_FEATURE_SOC_RNG_COUNT (1) - /* @brief RNGB availability on the SoC. */ - #define FSL_FEATURE_SOC_RNGB_COUNT (0) - /* @brief ROM availability on the SoC. */ - #define FSL_FEATURE_SOC_ROM_COUNT (0) - /* @brief RSIM availability on the SoC. */ - #define FSL_FEATURE_SOC_RSIM_COUNT (0) /* @brief RTC availability on the SoC. */ #define FSL_FEATURE_SOC_RTC_COUNT (1) - /* @brief SCG availability on the SoC. */ - #define FSL_FEATURE_SOC_SCG_COUNT (0) - /* @brief SCI availability on the SoC. */ - #define FSL_FEATURE_SOC_SCI_COUNT (0) /* @brief SDHC availability on the SoC. */ #define FSL_FEATURE_SOC_SDHC_COUNT (1) - /* @brief SDRAM availability on the SoC. */ - #define FSL_FEATURE_SOC_SDRAM_COUNT (0) - /* @brief SEMA42 availability on the SoC. */ - #define FSL_FEATURE_SOC_SEMA42_COUNT (0) /* @brief SIM availability on the SoC. */ #define FSL_FEATURE_SOC_SIM_COUNT (1) /* @brief SMC availability on the SoC. */ #define FSL_FEATURE_SOC_SMC_COUNT (1) - /* @brief SPI availability on the SoC. */ - #define FSL_FEATURE_SOC_SPI_COUNT (0) - /* @brief TMR availability on the SoC. */ - #define FSL_FEATURE_SOC_TMR_COUNT (0) - /* @brief TPM availability on the SoC. */ - #define FSL_FEATURE_SOC_TPM_COUNT (0) - /* @brief TRGMUX availability on the SoC. */ - #define FSL_FEATURE_SOC_TRGMUX_COUNT (0) - /* @brief TRIAMP availability on the SoC. */ - #define FSL_FEATURE_SOC_TRIAMP_COUNT (0) - /* @brief TRNG availability on the SoC. */ - #define FSL_FEATURE_SOC_TRNG_COUNT (0) - /* @brief TSI availability on the SoC. */ - #define FSL_FEATURE_SOC_TSI_COUNT (0) - /* @brief TSTMR availability on the SoC. */ - #define FSL_FEATURE_SOC_TSTMR_COUNT (0) /* @brief UART availability on the SoC. */ #define FSL_FEATURE_SOC_UART_COUNT (6) /* @brief USB availability on the SoC. */ #define FSL_FEATURE_SOC_USB_COUNT (1) /* @brief USBDCD availability on the SoC. */ #define FSL_FEATURE_SOC_USBDCD_COUNT (1) - /* @brief USBHS availability on the SoC. */ - #define FSL_FEATURE_SOC_USBHS_COUNT (0) - /* @brief USBHSDCD availability on the SoC. */ - #define FSL_FEATURE_SOC_USBHSDCD_COUNT (0) - /* @brief USBPHY availability on the SoC. */ - #define FSL_FEATURE_SOC_USBPHY_COUNT (0) /* @brief VREF availability on the SoC. */ #define FSL_FEATURE_SOC_VREF_COUNT (1) /* @brief WDOG availability on the SoC. */ #define FSL_FEATURE_SOC_WDOG_COUNT (1) - /* @brief XBAR availability on the SoC. */ - #define FSL_FEATURE_SOC_XBAR_COUNT (0) - /* @brief XBARA availability on the SoC. */ - #define FSL_FEATURE_SOC_XBARA_COUNT (0) - /* @brief XBARB availability on the SoC. */ - #define FSL_FEATURE_SOC_XBARB_COUNT (0) - /* @brief XCVR availability on the SoC. */ - #define FSL_FEATURE_SOC_XCVR_COUNT (0) - /* @brief XRDC availability on the SoC. */ - #define FSL_FEATURE_SOC_XRDC_COUNT (0) - /* @brief ZLL availability on the SoC. */ - #define FSL_FEATURE_SOC_ZLL_COUNT (0) #elif defined(CPU_MK64FN1M0VLL12) || defined(CPU_MK64FX512VLL12) - /* @brief ACMP availability on the SoC. */ - #define FSL_FEATURE_SOC_ACMP_COUNT (0) /* @brief ADC16 availability on the SoC. */ #define FSL_FEATURE_SOC_ADC16_COUNT (2) - /* @brief ADC12 availability on the SoC. */ - #define FSL_FEATURE_SOC_ADC12_COUNT (0) - /* @brief AFE availability on the SoC. */ - #define FSL_FEATURE_SOC_AFE_COUNT (0) /* @brief AIPS availability on the SoC. */ #define FSL_FEATURE_SOC_AIPS_COUNT (2) - /* @brief AOI availability on the SoC. */ - #define FSL_FEATURE_SOC_AOI_COUNT (0) /* @brief AXBS availability on the SoC. */ #define FSL_FEATURE_SOC_AXBS_COUNT (1) - /* @brief ASMC availability on the SoC. */ - #define FSL_FEATURE_SOC_ASMC_COUNT (0) - /* @brief CADC availability on the SoC. */ - #define FSL_FEATURE_SOC_CADC_COUNT (0) /* @brief FLEXCAN availability on the SoC. */ #define FSL_FEATURE_SOC_FLEXCAN_COUNT (1) /* @brief MMCAU availability on the SoC. */ @@ -370,154 +176,54 @@ #define FSL_FEATURE_SOC_CMP_COUNT (3) /* @brief CMT availability on the SoC. */ #define FSL_FEATURE_SOC_CMT_COUNT (1) - /* @brief CNC availability on the SoC. */ - #define FSL_FEATURE_SOC_CNC_COUNT (0) /* @brief CRC availability on the SoC. */ #define FSL_FEATURE_SOC_CRC_COUNT (1) /* @brief DAC availability on the SoC. */ #define FSL_FEATURE_SOC_DAC_COUNT (1) - /* @brief DAC32 availability on the SoC. */ - #define FSL_FEATURE_SOC_DAC32_COUNT (0) - /* @brief DCDC availability on the SoC. */ - #define FSL_FEATURE_SOC_DCDC_COUNT (0) - /* @brief DDR availability on the SoC. */ - #define FSL_FEATURE_SOC_DDR_COUNT (0) - /* @brief DMA availability on the SoC. */ - #define FSL_FEATURE_SOC_DMA_COUNT (0) /* @brief EDMA availability on the SoC. */ #define FSL_FEATURE_SOC_EDMA_COUNT (1) /* @brief DMAMUX availability on the SoC. */ #define FSL_FEATURE_SOC_DMAMUX_COUNT (1) - /* @brief DRY availability on the SoC. */ - #define FSL_FEATURE_SOC_DRY_COUNT (0) /* @brief DSPI availability on the SoC. */ #define FSL_FEATURE_SOC_DSPI_COUNT (3) - /* @brief EMVSIM availability on the SoC. */ - #define FSL_FEATURE_SOC_EMVSIM_COUNT (0) - /* @brief ENC availability on the SoC. */ - #define FSL_FEATURE_SOC_ENC_COUNT (0) /* @brief ENET availability on the SoC. */ #define FSL_FEATURE_SOC_ENET_COUNT (1) /* @brief EWM availability on the SoC. */ #define FSL_FEATURE_SOC_EWM_COUNT (1) /* @brief FB availability on the SoC. */ #define FSL_FEATURE_SOC_FB_COUNT (1) - /* @brief FGPIO availability on the SoC. */ - #define FSL_FEATURE_SOC_FGPIO_COUNT (0) - /* @brief FLEXIO availability on the SoC. */ - #define FSL_FEATURE_SOC_FLEXIO_COUNT (0) /* @brief FMC availability on the SoC. */ #define FSL_FEATURE_SOC_FMC_COUNT (1) - /* @brief FSKDT availability on the SoC. */ - #define FSL_FEATURE_SOC_FSKDT_COUNT (0) - /* @brief FTFA availability on the SoC. */ - #define FSL_FEATURE_SOC_FTFA_COUNT (0) /* @brief FTFE availability on the SoC. */ #define FSL_FEATURE_SOC_FTFE_COUNT (1) - /* @brief FTFL availability on the SoC. */ - #define FSL_FEATURE_SOC_FTFL_COUNT (0) /* @brief FTM availability on the SoC. */ #define FSL_FEATURE_SOC_FTM_COUNT (4) - /* @brief FTMRA availability on the SoC. */ - #define FSL_FEATURE_SOC_FTMRA_COUNT (0) - /* @brief FTMRE availability on the SoC. */ - #define FSL_FEATURE_SOC_FTMRE_COUNT (0) - /* @brief FTMRH availability on the SoC. */ - #define FSL_FEATURE_SOC_FTMRH_COUNT (0) /* @brief GPIO availability on the SoC. */ #define FSL_FEATURE_SOC_GPIO_COUNT (5) - /* @brief HSADC availability on the SoC. */ - #define FSL_FEATURE_SOC_HSADC_COUNT (0) /* @brief I2C availability on the SoC. */ #define FSL_FEATURE_SOC_I2C_COUNT (3) /* @brief I2S availability on the SoC. */ #define FSL_FEATURE_SOC_I2S_COUNT (1) - /* @brief ICS availability on the SoC. */ - #define FSL_FEATURE_SOC_ICS_COUNT (0) - /* @brief INTMUX availability on the SoC. */ - #define FSL_FEATURE_SOC_INTMUX_COUNT (0) - /* @brief IRQ availability on the SoC. */ - #define FSL_FEATURE_SOC_IRQ_COUNT (0) - /* @brief KBI availability on the SoC. */ - #define FSL_FEATURE_SOC_KBI_COUNT (0) - /* @brief SLCD availability on the SoC. */ - #define FSL_FEATURE_SOC_SLCD_COUNT (0) - /* @brief LCDC availability on the SoC. */ - #define FSL_FEATURE_SOC_LCDC_COUNT (0) - /* @brief LDO availability on the SoC. */ - #define FSL_FEATURE_SOC_LDO_COUNT (0) /* @brief LLWU availability on the SoC. */ #define FSL_FEATURE_SOC_LLWU_COUNT (1) - /* @brief LMEM availability on the SoC. */ - #define FSL_FEATURE_SOC_LMEM_COUNT (0) - /* @brief LPI2C availability on the SoC. */ - #define FSL_FEATURE_SOC_LPI2C_COUNT (0) - /* @brief LPIT availability on the SoC. */ - #define FSL_FEATURE_SOC_LPIT_COUNT (0) - /* @brief LPSCI availability on the SoC. */ - #define FSL_FEATURE_SOC_LPSCI_COUNT (0) - /* @brief LPSPI availability on the SoC. */ - #define FSL_FEATURE_SOC_LPSPI_COUNT (0) /* @brief LPTMR availability on the SoC. */ #define FSL_FEATURE_SOC_LPTMR_COUNT (1) - /* @brief LPTPM availability on the SoC. */ - #define FSL_FEATURE_SOC_LPTPM_COUNT (0) - /* @brief LPUART availability on the SoC. */ - #define FSL_FEATURE_SOC_LPUART_COUNT (0) - /* @brief LTC availability on the SoC. */ - #define FSL_FEATURE_SOC_LTC_COUNT (0) - /* @brief MC availability on the SoC. */ - #define FSL_FEATURE_SOC_MC_COUNT (0) /* @brief MCG availability on the SoC. */ #define FSL_FEATURE_SOC_MCG_COUNT (1) - /* @brief MCGLITE availability on the SoC. */ - #define FSL_FEATURE_SOC_MCGLITE_COUNT (0) /* @brief MCM availability on the SoC. */ #define FSL_FEATURE_SOC_MCM_COUNT (1) - /* @brief MMAU availability on the SoC. */ - #define FSL_FEATURE_SOC_MMAU_COUNT (0) - /* @brief MMDVSQ availability on the SoC. */ - #define FSL_FEATURE_SOC_MMDVSQ_COUNT (0) /* @brief SYSMPU availability on the SoC. */ #define FSL_FEATURE_SOC_SYSMPU_COUNT (1) - /* @brief MSCAN availability on the SoC. */ - #define FSL_FEATURE_SOC_MSCAN_COUNT (0) - /* @brief MSCM availability on the SoC. */ - #define FSL_FEATURE_SOC_MSCM_COUNT (0) - /* @brief MTB availability on the SoC. */ - #define FSL_FEATURE_SOC_MTB_COUNT (0) - /* @brief MTBDWT availability on the SoC. */ - #define FSL_FEATURE_SOC_MTBDWT_COUNT (0) - /* @brief MU availability on the SoC. */ - #define FSL_FEATURE_SOC_MU_COUNT (0) - /* @brief NFC availability on the SoC. */ - #define FSL_FEATURE_SOC_NFC_COUNT (0) - /* @brief OPAMP availability on the SoC. */ - #define FSL_FEATURE_SOC_OPAMP_COUNT (0) /* @brief OSC availability on the SoC. */ #define FSL_FEATURE_SOC_OSC_COUNT (1) - /* @brief OSC32 availability on the SoC. */ - #define FSL_FEATURE_SOC_OSC32_COUNT (0) - /* @brief OTFAD availability on the SoC. */ - #define FSL_FEATURE_SOC_OTFAD_COUNT (0) /* @brief PDB availability on the SoC. */ #define FSL_FEATURE_SOC_PDB_COUNT (1) - /* @brief PCC availability on the SoC. */ - #define FSL_FEATURE_SOC_PCC_COUNT (0) - /* @brief PGA availability on the SoC. */ - #define FSL_FEATURE_SOC_PGA_COUNT (0) /* @brief PIT availability on the SoC. */ #define FSL_FEATURE_SOC_PIT_COUNT (1) /* @brief PMC availability on the SoC. */ #define FSL_FEATURE_SOC_PMC_COUNT (1) /* @brief PORT availability on the SoC. */ #define FSL_FEATURE_SOC_PORT_COUNT (5) - /* @brief PWM availability on the SoC. */ - #define FSL_FEATURE_SOC_PWM_COUNT (0) - /* @brief PWT availability on the SoC. */ - #define FSL_FEATURE_SOC_PWT_COUNT (0) - /* @brief QuadSPI availability on the SoC. */ - #define FSL_FEATURE_SOC_QuadSPI_COUNT (0) /* @brief RCM availability on the SoC. */ #define FSL_FEATURE_SOC_RCM_COUNT (1) /* @brief RFSYS availability on the SoC. */ @@ -526,72 +232,24 @@ #define FSL_FEATURE_SOC_RFVBAT_COUNT (1) /* @brief RNG availability on the SoC. */ #define FSL_FEATURE_SOC_RNG_COUNT (1) - /* @brief RNGB availability on the SoC. */ - #define FSL_FEATURE_SOC_RNGB_COUNT (0) - /* @brief ROM availability on the SoC. */ - #define FSL_FEATURE_SOC_ROM_COUNT (0) - /* @brief RSIM availability on the SoC. */ - #define FSL_FEATURE_SOC_RSIM_COUNT (0) /* @brief RTC availability on the SoC. */ #define FSL_FEATURE_SOC_RTC_COUNT (1) - /* @brief SCG availability on the SoC. */ - #define FSL_FEATURE_SOC_SCG_COUNT (0) - /* @brief SCI availability on the SoC. */ - #define FSL_FEATURE_SOC_SCI_COUNT (0) /* @brief SDHC availability on the SoC. */ #define FSL_FEATURE_SOC_SDHC_COUNT (1) - /* @brief SDRAM availability on the SoC. */ - #define FSL_FEATURE_SOC_SDRAM_COUNT (0) - /* @brief SEMA42 availability on the SoC. */ - #define FSL_FEATURE_SOC_SEMA42_COUNT (0) /* @brief SIM availability on the SoC. */ #define FSL_FEATURE_SOC_SIM_COUNT (1) /* @brief SMC availability on the SoC. */ #define FSL_FEATURE_SOC_SMC_COUNT (1) - /* @brief SPI availability on the SoC. */ - #define FSL_FEATURE_SOC_SPI_COUNT (0) - /* @brief TMR availability on the SoC. */ - #define FSL_FEATURE_SOC_TMR_COUNT (0) - /* @brief TPM availability on the SoC. */ - #define FSL_FEATURE_SOC_TPM_COUNT (0) - /* @brief TRGMUX availability on the SoC. */ - #define FSL_FEATURE_SOC_TRGMUX_COUNT (0) - /* @brief TRIAMP availability on the SoC. */ - #define FSL_FEATURE_SOC_TRIAMP_COUNT (0) - /* @brief TRNG availability on the SoC. */ - #define FSL_FEATURE_SOC_TRNG_COUNT (0) - /* @brief TSI availability on the SoC. */ - #define FSL_FEATURE_SOC_TSI_COUNT (0) - /* @brief TSTMR availability on the SoC. */ - #define FSL_FEATURE_SOC_TSTMR_COUNT (0) /* @brief UART availability on the SoC. */ #define FSL_FEATURE_SOC_UART_COUNT (5) /* @brief USB availability on the SoC. */ #define FSL_FEATURE_SOC_USB_COUNT (1) /* @brief USBDCD availability on the SoC. */ #define FSL_FEATURE_SOC_USBDCD_COUNT (1) - /* @brief USBHS availability on the SoC. */ - #define FSL_FEATURE_SOC_USBHS_COUNT (0) - /* @brief USBHSDCD availability on the SoC. */ - #define FSL_FEATURE_SOC_USBHSDCD_COUNT (0) - /* @brief USBPHY availability on the SoC. */ - #define FSL_FEATURE_SOC_USBPHY_COUNT (0) /* @brief VREF availability on the SoC. */ #define FSL_FEATURE_SOC_VREF_COUNT (1) /* @brief WDOG availability on the SoC. */ #define FSL_FEATURE_SOC_WDOG_COUNT (1) - /* @brief XBAR availability on the SoC. */ - #define FSL_FEATURE_SOC_XBAR_COUNT (0) - /* @brief XBARA availability on the SoC. */ - #define FSL_FEATURE_SOC_XBARA_COUNT (0) - /* @brief XBARB availability on the SoC. */ - #define FSL_FEATURE_SOC_XBARB_COUNT (0) - /* @brief XCVR availability on the SoC. */ - #define FSL_FEATURE_SOC_XCVR_COUNT (0) - /* @brief XRDC availability on the SoC. */ - #define FSL_FEATURE_SOC_XRDC_COUNT (0) - /* @brief ZLL availability on the SoC. */ - #define FSL_FEATURE_SOC_ZLL_COUNT (0) #endif /* ADC16 module features */ @@ -631,14 +289,18 @@ #define FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(x) (16) /* @brief Has doze mode support (register bit field MCR[DOZE]). */ #define FSL_FEATURE_FLEXCAN_HAS_DOZE_MODE_SUPPORT (0) +/* @brief Insatnce has doze mode support (register bit field MCR[DOZE]). */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_DOZE_MODE_SUPPORTn(x) (0) /* @brief Has a glitch filter on the receive pin (register bit field MCR[WAKSRC]). */ #define FSL_FEATURE_FLEXCAN_HAS_GLITCH_FILTER (1) /* @brief Has extended interrupt mask and flag register (register IMASK2, IFLAG2). */ #define FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER (0) -/* @brief Has extended bit timing register (register CBT). */ -#define FSL_FEATURE_FLEXCAN_HAS_EXTENDED_TIMING_REGISTER (0) +/* @brief Instance has extended bit timing register (register CBT). */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_EXTENDED_TIMING_REGISTERn(x) (0) /* @brief Has a receive FIFO DMA feature (register bit field MCR[DMA]). */ #define FSL_FEATURE_FLEXCAN_HAS_RX_FIFO_DMA (0) +/* @brief Instance has a receive FIFO DMA feature (register bit field MCR[DMA]). */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_RX_FIFO_DMAn(x) (0) /* @brief Has separate message buffer 0 interrupt flag (register bit field IFLAG1[BUF0I]). */ #define FSL_FEATURE_FLEXCAN_HAS_SEPARATE_BUFFER_0_FLAG (1) /* @brief Has bitfield name BUF31TO0M. */ @@ -761,6 +423,8 @@ #define FSL_FEATURE_FLASH_HAS_MSCM_FLASH_CACHE_CONTROLS (0) /* @brief Has prefetch speculation control in flash, such as kv5x. */ #define FSL_FEATURE_FLASH_PREFETCH_SPECULATION_CONTROL_IN_FLASH (0) + /* @brief P-Flash flash size coding rule version, value 0 for K1 and K2, value 1 for K3. */ + #define FSL_FEATURE_FLASH_SIZE_ENCODING_RULE_VERSION (0) /* @brief P-Flash start address. */ #define FSL_FEATURE_FLASH_PFLASH_START_ADDRESS (0x00000000) /* @brief P-Flash block count. */ @@ -948,6 +612,8 @@ #define FSL_FEATURE_FLASH_HAS_MSCM_FLASH_CACHE_CONTROLS (0) /* @brief Has prefetch speculation control in flash, such as kv5x. */ #define FSL_FEATURE_FLASH_PREFETCH_SPECULATION_CONTROL_IN_FLASH (0) + /* @brief P-Flash flash size coding rule version, value 0 for K1 and K2, value 1 for K3. */ + #define FSL_FEATURE_FLASH_SIZE_ENCODING_RULE_VERSION (0) /* @brief P-Flash start address. */ #define FSL_FEATURE_FLASH_PFLASH_START_ADDRESS (0x00000000) /* @brief P-Flash block count. */ @@ -1133,6 +799,14 @@ #define FSL_FEATURE_FTM_HAS_RELOAD_INTERRUPT (0) /* @brief Has reload initialization trigger. */ #define FSL_FEATURE_FTM_HAS_RELOAD_INITIALIZATION_TRIGGER (0) +/* @brief Has DMA support, bitfield CnSC[DMA]. */ +#define FSL_FEATURE_FTM_HAS_DMA_SUPPORT (1) +/* @brief If channel 6 is used to generate channel trigger, bitfield EXTTRIG[CH6TRIG]. */ +#define FSL_FEATURE_FTM_HAS_CHANNEL6_TRIGGER (0) +/* @brief If channel 7 is used to generate channel trigger, bitfield EXTTRIG[CH7TRIG]. */ +#define FSL_FEATURE_FTM_HAS_CHANNEL7_TRIGGER (0) +/* @brief Has no QDCTRL. */ +#define FSL_FEATURE_FTM_HAS_NO_QDCTRL (0) /* GPIO module features */ @@ -1549,6 +1223,8 @@ #define FSL_FEATURE_PIT_HAS_CHAIN_MODE (1) /* @brief Has shared interrupt handler (has not individual interrupt handler for each channel). */ #define FSL_FEATURE_PIT_HAS_SHARED_IRQ_HANDLER (0) +/* @brief Has timer enable control. */ +#define FSL_FEATURE_PIT_HAS_MDIS (1) /* PMC module features */ @@ -1669,6 +1345,28 @@ #define FSL_FEATURE_RTC_HAS_TSIC (0) /* @brief Has OSC capacitor setting RTC_CR[SC2P ~ SC16P] */ #define FSL_FEATURE_RTC_HAS_OSC_SCXP (1) + /* @brief Has Tamper Interrupt Register (register TIR). */ + #define FSL_FEATURE_RTC_HAS_TIR (0) + /* @brief Has Tamper Pin Interrupt Enable (bitfield TIR[TPIE]). */ + #define FSL_FEATURE_RTC_HAS_TIR_TPIE (0) + /* @brief Has Security Interrupt Enable (bitfield TIR[SIE]). */ + #define FSL_FEATURE_RTC_HAS_TIR_SIE (0) + /* @brief Has Loss of Clock Interrupt Enable (bitfield TIR[LCIE]). */ + #define FSL_FEATURE_RTC_HAS_TIR_LCIE (0) + /* @brief Has Tamper Interrupt Detect Flag (bitfield SR[TIDF]). */ + #define FSL_FEATURE_RTC_HAS_SR_TIDF (0) + /* @brief Has Tamper Detect Register (register TDR). */ + #define FSL_FEATURE_RTC_HAS_TDR (0) + /* @brief Has Tamper Pin Flag (bitfield TDR[TPF]). */ + #define FSL_FEATURE_RTC_HAS_TDR_TPF (0) + /* @brief Has Security Tamper Flag (bitfield TDR[STF]). */ + #define FSL_FEATURE_RTC_HAS_TDR_STF (0) + /* @brief Has Loss of Clock Tamper Flag (bitfield TDR[LCTF]). */ + #define FSL_FEATURE_RTC_HAS_TDR_LCTF (0) + /* @brief Has Tamper Time Seconds Register (register TTSR). */ + #define FSL_FEATURE_RTC_HAS_TTSR (0) + /* @brief Has Pin Configuration Register (register PCR). */ + #define FSL_FEATURE_RTC_HAS_PCR (0) #elif defined(CPU_MK64FN1M0VMD12) || defined(CPU_MK64FX512VMD12) /* @brief Has wakeup pin. */ #define FSL_FEATURE_RTC_HAS_WAKEUP_PIN (1) @@ -1690,6 +1388,28 @@ #define FSL_FEATURE_RTC_HAS_TSIC (0) /* @brief Has OSC capacitor setting RTC_CR[SC2P ~ SC16P] */ #define FSL_FEATURE_RTC_HAS_OSC_SCXP (1) + /* @brief Has Tamper Interrupt Register (register TIR). */ + #define FSL_FEATURE_RTC_HAS_TIR (0) + /* @brief Has Tamper Pin Interrupt Enable (bitfield TIR[TPIE]). */ + #define FSL_FEATURE_RTC_HAS_TIR_TPIE (0) + /* @brief Has Security Interrupt Enable (bitfield TIR[SIE]). */ + #define FSL_FEATURE_RTC_HAS_TIR_SIE (0) + /* @brief Has Loss of Clock Interrupt Enable (bitfield TIR[LCIE]). */ + #define FSL_FEATURE_RTC_HAS_TIR_LCIE (0) + /* @brief Has Tamper Interrupt Detect Flag (bitfield SR[TIDF]). */ + #define FSL_FEATURE_RTC_HAS_SR_TIDF (0) + /* @brief Has Tamper Detect Register (register TDR). */ + #define FSL_FEATURE_RTC_HAS_TDR (0) + /* @brief Has Tamper Pin Flag (bitfield TDR[TPF]). */ + #define FSL_FEATURE_RTC_HAS_TDR_TPF (0) + /* @brief Has Security Tamper Flag (bitfield TDR[STF]). */ + #define FSL_FEATURE_RTC_HAS_TDR_STF (0) + /* @brief Has Loss of Clock Tamper Flag (bitfield TDR[LCTF]). */ + #define FSL_FEATURE_RTC_HAS_TDR_LCTF (0) + /* @brief Has Tamper Time Seconds Register (register TTSR). */ + #define FSL_FEATURE_RTC_HAS_TTSR (0) + /* @brief Has Pin Configuration Register (register PCR). */ + #define FSL_FEATURE_RTC_HAS_PCR (0) #endif /* defined(CPU_MK64FN1M0CAJ12) || defined(CPU_MK64FN1M0VDC12) || defined(CPU_MK64FN1M0VLL12) || defined(CPU_MK64FN1M0VLQ12) || \ defined(CPU_MK64FX512VDC12) || defined(CPU_MK64FX512VLL12) || defined(CPU_MK64FX512VLQ12) */ @@ -1975,6 +1695,8 @@ #define FSL_FEATURE_SMC_HAS_SUB_STOP_MODE (1) /* @brief Has stop submode 0(VLLS0). */ #define FSL_FEATURE_SMC_HAS_STOP_SUBMODE0 (1) +/* @brief Has stop submode 1(VLLS1). */ +#define FSL_FEATURE_SMC_HAS_STOP_SUBMODE1 (1) /* @brief Has stop submode 2(VLLS2). */ #define FSL_FEATURE_SMC_HAS_STOP_SUBMODE2 (1) /* @brief Has SMC_PARAM. */ @@ -1992,15 +1714,17 @@ /* @brief Receive/transmit FIFO size in number of items. */ #define FSL_FEATURE_DSPI_FIFO_SIZEn(x) \ - ((x) == DSPI0 ? (4) : \ - ((x) == DSPI1 ? (1) : \ - ((x) == DSPI2 ? (1) : (-1)))) + ((x) == SPI0 ? (4) : \ + ((x) == SPI1 ? (1) : \ + ((x) == SPI2 ? (1) : (-1)))) /* @brief Maximum transfer data width in bits. */ #define FSL_FEATURE_DSPI_MAX_DATA_WIDTH (16) /* @brief Maximum number of chip select pins. (Reflects the width of register bit field PUSHR[PCS].) */ #define FSL_FEATURE_DSPI_MAX_CHIP_SELECT_COUNT (6) /* @brief Number of chip select pins. */ #define FSL_FEATURE_DSPI_CHIP_SELECT_COUNT (6) +/* @brief Number of CTAR registers. */ +#define FSL_FEATURE_DSPI_CTAR_COUNT (2) /* @brief Has chip select strobe capability on the PCS5 pin. */ #define FSL_FEATURE_DSPI_HAS_CHIP_SELECT_STROBE (1) /* @brief Has separated TXDATA and CMD FIFOs (register SREX). */ @@ -2009,9 +1733,9 @@ #define FSL_FEATURE_DSPI_16BIT_TRANSFERS (1) /* @brief Has separate DMA RX and TX requests. */ #define FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(x) \ - ((x) == DSPI0 ? (1) : \ - ((x) == DSPI1 ? (0) : \ - ((x) == DSPI2 ? (0) : (-1)))) + ((x) == SPI0 ? (1) : \ + ((x) == SPI1 ? (0) : \ + ((x) == SPI2 ? (0) : (-1)))) /* SYSMPU module features */ @@ -2189,6 +1913,10 @@ #define FSL_FEATURE_USB_KHCI_IRC48M_MODULE_CLOCK_ENABLED (1) /* @brief Number of endpoints supported */ #define FSL_FEATURE_USB_ENDPT_COUNT (16) +/* @brief Has STALL_IL/OL_DIS registers */ +#define FSL_FEATURE_USB_KHCI_HAS_STALL_LOW (0) +/* @brief Has STALL_IH/OH_DIS registers */ +#define FSL_FEATURE_USB_KHCI_HAS_STALL_HIGH (0) /* VREF module features */ diff --git a/ext/hal/nxp/mcux/devices/MK64F12/fsl_clock.c b/ext/hal/nxp/mcux/devices/MK64F12/fsl_clock.c index a258bd41bbd..4fff3904444 100644 --- a/ext/hal/nxp/mcux/devices/MK64F12/fsl_clock.c +++ b/ext/hal/nxp/mcux/devices/MK64F12/fsl_clock.c @@ -3,30 +3,8 @@ * Copyright (c) 2016 - 2017 , NXP * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * SPDX-License-Identifier: BSD-3-Clause */ #include "fsl_clock.h" @@ -34,6 +12,10 @@ /******************************************************************************* * Definitions ******************************************************************************/ +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.clock" +#endif /* Macro definition remap workaround. */ #if (defined(MCG_C2_EREFS_MASK) && !(defined(MCG_C2_EREFS0_MASK))) @@ -119,9 +101,9 @@ static uint32_t s_slowIrcFreq = 32768U; static uint32_t s_fastIrcFreq = 4000000U; /* External XTAL0 (OSC0) clock frequency. */ -uint32_t g_xtal0Freq; +volatile uint32_t g_xtal0Freq; /* External XTAL32K clock frequency. */ -uint32_t g_xtal32Freq; +volatile uint32_t g_xtal32Freq; /******************************************************************************* * Prototypes @@ -190,10 +172,6 @@ static uint32_t CLOCK_GetPll0RefFreq(void); */ static uint8_t CLOCK_GetOscRangeFromFreq(uint32_t freq); -/******************************************************************************* - * Code - ******************************************************************************/ - #ifndef MCG_USER_CONFIG_FLL_STABLE_DELAY_EN /*! * @brief Delay function to wait FLL stable. @@ -201,7 +179,15 @@ static uint8_t CLOCK_GetOscRangeFromFreq(uint32_t freq); * Delay function to wait FLL stable in FEI mode or FEE mode, should wait at least * 1ms. Every time changes FLL setting, should wait this time for FLL stable. */ -void CLOCK_FllStableDelay(void) +static void CLOCK_FllStableDelay(void); +#endif + +/******************************************************************************* + * Code + ******************************************************************************/ + +#ifndef MCG_USER_CONFIG_FLL_STABLE_DELAY_EN +static void CLOCK_FllStableDelay(void) { /* Should wait at least 1ms. Because in these modes, the core clock is 100MHz @@ -216,7 +202,7 @@ void CLOCK_FllStableDelay(void) #else /* With MCG_USER_CONFIG_FLL_STABLE_DELAY_EN defined. */ /* Once user defines the MCG_USER_CONFIG_FLL_STABLE_DELAY_EN to use their own delay function, he has to * create his own CLOCK_FllStableDelay() function in application code. Since the clock functions in this - * file would call the CLOCK_FllStableDelay() regardness how it is defined. + * file would call the CLOCK_FllStableDelay() regardless how it is defined. */ extern void CLOCK_FllStableDelay(void); #endif /* MCG_USER_CONFIG_FLL_STABLE_DELAY_EN */ @@ -356,6 +342,11 @@ static uint8_t CLOCK_GetOscRangeFromFreq(uint32_t freq) return range; } +/*! + * brief Get the OSC0 external reference clock frequency (OSC0ERCLK). + * + * return Clock frequency in Hz. + */ uint32_t CLOCK_GetOsc0ErClkFreq(void) { if (OSC0->CR & OSC_CR_ERCLKEN_MASK) @@ -370,6 +361,11 @@ uint32_t CLOCK_GetOsc0ErClkFreq(void) } } +/*! + * brief Get the external reference 32K clock frequency (ERCLK32K). + * + * return Clock frequency in Hz. + */ uint32_t CLOCK_GetEr32kClkFreq(void) { uint32_t freq; @@ -394,6 +390,11 @@ uint32_t CLOCK_GetEr32kClkFreq(void) return freq; } +/*! + * brief Get the output clock frequency selected by SIM[PLLFLLSEL]. + * + * return Clock frequency in Hz. + */ uint32_t CLOCK_GetPllFllSelClkFreq(void) { uint32_t freq; @@ -417,31 +418,66 @@ uint32_t CLOCK_GetPllFllSelClkFreq(void) return freq; } +/*! + * brief Get the platform clock frequency. + * + * return Clock frequency in Hz. + */ uint32_t CLOCK_GetPlatClkFreq(void) { return CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV1_VAL + 1); } +/*! + * brief Get the flash clock frequency. + * + * return Clock frequency in Hz. + */ uint32_t CLOCK_GetFlashClkFreq(void) { return CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV4_VAL + 1); } +/*! + * brief Get the flexbus clock frequency. + * + * return Clock frequency in Hz. + */ uint32_t CLOCK_GetFlexBusClkFreq(void) { return CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV3_VAL + 1); } +/*! + * brief Get the bus clock frequency. + * + * return Clock frequency in Hz. + */ uint32_t CLOCK_GetBusClkFreq(void) { return CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV2_VAL + 1); } +/*! + * brief Get the core clock or system clock frequency. + * + * return Clock frequency in Hz. + */ uint32_t CLOCK_GetCoreSysClkFreq(void) { return CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV1_VAL + 1); } +/*! + * brief Gets the clock frequency for a specific clock name. + * + * This function checks the current clock configurations and then calculates + * the clock frequency for a specific clock name defined in clock_name_t. + * The MCG must be properly configured before using this function. + * + * param clockName Clock names defined in clock_name_t + * return Clock frequency value in Hertz + */ uint32_t CLOCK_GetFreq(clock_name_t clockName) { uint32_t freq; @@ -496,6 +532,13 @@ uint32_t CLOCK_GetFreq(clock_name_t clockName) return freq; } +/*! + * brief Set the clock configure in SIM module. + * + * This function sets system layer clock settings in SIM module. + * + * param config Pointer to the configure structure. + */ void CLOCK_SetSimConfig(sim_clock_config_t const *config) { SIM->CLKDIV1 = config->clkdiv1; @@ -503,6 +546,13 @@ void CLOCK_SetSimConfig(sim_clock_config_t const *config) CLOCK_SetEr32kClock(config->er32kSrc); } +/*! brief Enable USB FS clock. + * + * param src USB FS clock source. + * param freq The frequency specified by src. + * retval true The clock is set successfully. + * retval false The clock source is invalid to get proper USB FS clock. + */ bool CLOCK_EnableUsbfs0Clock(clock_usb_src_t src, uint32_t freq) { bool ret = true; @@ -547,6 +597,14 @@ bool CLOCK_EnableUsbfs0Clock(clock_usb_src_t src, uint32_t freq) return ret; } +/*! + * brief Gets the MCG output clock (MCGOUTCLK) frequency. + * + * This function gets the MCG output clock frequency in Hz based on the current MCG + * register value. + * + * return The frequency of MCGOUTCLK. + */ uint32_t CLOCK_GetOutClkFreq(void) { uint32_t mcgoutclk; @@ -573,6 +631,15 @@ uint32_t CLOCK_GetOutClkFreq(void) return mcgoutclk; } +/*! + * brief Gets the MCG FLL clock (MCGFLLCLK) frequency. + * + * This function gets the MCG FLL clock frequency in Hz based on the current MCG + * register value. The FLL is enabled in FEI/FBI/FEE/FBE mode and + * disabled in low power state in other modes. + * + * return The frequency of MCGFLLCLK. + */ uint32_t CLOCK_GetFllFreq(void) { static const uint16_t fllFactorTable[4][2] = {{640, 732}, {1280, 1464}, {1920, 2197}, {2560, 2929}}; @@ -599,6 +666,14 @@ uint32_t CLOCK_GetFllFreq(void) return freq * fllFactorTable[drs][dmx32]; } +/*! + * brief Gets the MCG internal reference clock (MCGIRCLK) frequency. + * + * This function gets the MCG internal reference clock frequency in Hz based + * on the current MCG register value. + * + * return The frequency of MCGIRCLK. + */ uint32_t CLOCK_GetInternalRefClkFreq(void) { /* If MCGIRCLK is gated. */ @@ -610,6 +685,14 @@ uint32_t CLOCK_GetInternalRefClkFreq(void) return CLOCK_GetInternalRefClkSelectFreq(); } +/*! + * brief Gets the MCG fixed frequency clock (MCGFFCLK) frequency. + * + * This function gets the MCG fixed frequency clock frequency in Hz based + * on the current MCG register value. + * + * return The frequency of MCGFFCLK. + */ uint32_t CLOCK_GetFixedFreqClkFreq(void) { uint32_t freq = CLOCK_GetFllRefClkFreq(); @@ -625,6 +708,14 @@ uint32_t CLOCK_GetFixedFreqClkFreq(void) } } +/*! + * brief Gets the MCG PLL0 clock (MCGPLL0CLK) frequency. + * + * This function gets the MCG PLL0 clock frequency in Hz based on the current MCG + * register value. + * + * return The frequency of MCGPLL0CLK. + */ uint32_t CLOCK_GetPll0Freq(void) { uint32_t mcgpll0clk; @@ -649,6 +740,18 @@ uint32_t CLOCK_GetPll0Freq(void) return mcgpll0clk; } +/*! + * brief Selects the MCG external reference clock. + * + * Selects the MCG external reference clock source, changes the MCG_C7[OSCSEL], + * and waits for the clock source to be stable. Because the external reference + * clock should not be changed in FEE/FBE/BLPE/PBE/PEE modes, do not call this function in these modes. + * + * param oscsel MCG external reference clock source, MCG_C7[OSCSEL]. + * retval kStatus_MCG_SourceUsed Because the external reference clock is used as a clock source, + * the configuration should not be changed. Otherwise, a glitch occurs. + * retval kStatus_Success External reference clock set successfully. + */ status_t CLOCK_SetExternalRefClkConfig(mcg_oscsel_t oscsel) { bool needDelay; @@ -686,6 +789,22 @@ status_t CLOCK_SetExternalRefClkConfig(mcg_oscsel_t oscsel) return kStatus_Success; } +/*! + * brief Configures the Internal Reference clock (MCGIRCLK). + * + * This function sets the \c MCGIRCLK base on parameters. It also selects the IRC + * source. If the fast IRC is used, this function sets the fast IRC divider. + * This function also sets whether the \c MCGIRCLK is enabled in stop mode. + * Calling this function in FBI/PBI/BLPI modes may change the system clock. As a result, + * using the function in these modes it is not allowed. + * + * param enableMode MCGIRCLK enable mode, OR'ed value of ref _mcg_irclk_enable_mode. + * param ircs MCGIRCLK clock source, choose fast or slow. + * param fcrdiv Fast IRC divider setting (\c FCRDIV). + * retval kStatus_MCG_SourceUsed Because the internal reference clock is used as a clock source, + * the configuration should not be changed. Otherwise, a glitch occurs. + * retval kStatus_Success MCGIRCLK configuration finished successfully. + */ status_t CLOCK_SetInternalRefClkConfig(uint8_t enableMode, mcg_irc_mode_t ircs, uint8_t fcrdiv) { uint32_t mcgOutClkState = MCG_S_CLKST_VAL; @@ -734,6 +853,21 @@ status_t CLOCK_SetInternalRefClkConfig(uint8_t enableMode, mcg_irc_mode_t ircs, return kStatus_Success; } +/*! + * brief Calculates the PLL divider setting for a desired output frequency. + * + * This function calculates the correct reference clock divider (\c PRDIV) and + * VCO divider (\c VDIV) to generate a desired PLL output frequency. It returns the + * closest frequency match with the corresponding \c PRDIV/VDIV + * returned from parameters. If a desired frequency is not valid, this function + * returns 0. + * + * param refFreq PLL reference clock frequency. + * param desireFreq Desired PLL output frequency. + * param prdiv PRDIV value to generate desired PLL frequency. + * param vdiv VDIV value to generate desired PLL frequency. + * return Closest frequency match that the PLL was able generate. + */ uint32_t CLOCK_CalcPllDiv(uint32_t refFreq, uint32_t desireFreq, uint8_t *prdiv, uint8_t *vdiv) { uint8_t ret_prdiv; /* PRDIV to return. */ @@ -742,7 +876,7 @@ uint32_t CLOCK_CalcPllDiv(uint32_t refFreq, uint32_t desireFreq, uint8_t *prdiv, uint8_t prdiv_max; /* Max PRDIV value to make reference clock in allowed range. */ uint8_t prdiv_cur; /* PRDIV value for iteration. */ uint8_t vdiv_cur; /* VDIV value for iteration. */ - uint32_t ret_freq = 0U; /* PLL output fequency to return. */ + uint32_t ret_freq = 0U; /* PLL output frequency to return. */ uint32_t diff = 0xFFFFFFFFU; /* Difference between desireFreq and return frequency. */ uint32_t ref_div; /* Reference frequency after PRDIV. */ @@ -831,6 +965,17 @@ uint32_t CLOCK_CalcPllDiv(uint32_t refFreq, uint32_t desireFreq, uint8_t *prdiv, } } +/*! + * brief Enables the PLL0 in FLL mode. + * + * This function sets us the PLL0 in FLL mode and reconfigures + * the PLL0. Ensure that the PLL reference + * clock is enabled before calling this function and that the PLL0 is not used as a clock source. + * The function CLOCK_CalcPllDiv gets the correct PLL + * divider values. + * + * param config Pointer to the configuration structure. + */ void CLOCK_EnablePll0(mcg_pll_config_t const *config) { assert(config); @@ -851,6 +996,13 @@ void CLOCK_EnablePll0(mcg_pll_config_t const *config) } } +/*! + * brief Sets the OSC0 clock monitor mode. + * + * This function sets the OSC0 clock monitor mode. See ref mcg_monitor_mode_t for details. + * + * param mode Monitor mode to set. + */ void CLOCK_SetOsc0MonitorMode(mcg_monitor_mode_t mode) { /* Clear the previous flag, MCG_SC[LOCS0]. */ @@ -874,6 +1026,13 @@ void CLOCK_SetOsc0MonitorMode(mcg_monitor_mode_t mode) } } +/*! + * brief Sets the RTC OSC clock monitor mode. + * + * This function sets the RTC OSC clock monitor mode. See ref mcg_monitor_mode_t for details. + * + * param mode Monitor mode to set. + */ void CLOCK_SetRtcOscMonitorMode(mcg_monitor_mode_t mode) { uint8_t mcg_c8 = MCG->C8; @@ -891,6 +1050,13 @@ void CLOCK_SetRtcOscMonitorMode(mcg_monitor_mode_t mode) MCG->C8 = mcg_c8; } +/*! + * brief Sets the PLL0 clock monitor mode. + * + * This function sets the PLL0 clock monitor mode. See ref mcg_monitor_mode_t for details. + * + * param mode Monitor mode to set. + */ void CLOCK_SetPll0MonitorMode(mcg_monitor_mode_t mode) { uint8_t mcg_c8; @@ -921,6 +1087,32 @@ void CLOCK_SetPll0MonitorMode(mcg_monitor_mode_t mode) } } +/*! + * brief Gets the MCG status flags. + * + * This function gets the MCG clock status flags. All status flags are + * returned as a logical OR of the enumeration ref _mcg_status_flags_t. To + * check a specific flag, compare the return value with the flag. + * + * Example: + * code + // To check the clock lost lock status of OSC0 and PLL0. + uint32_t mcgFlags; + + mcgFlags = CLOCK_GetStatusFlags(); + + if (mcgFlags & kMCG_Osc0LostFlag) + { + // OSC0 clock lock lost. Do something. + } + if (mcgFlags & kMCG_Pll0LostFlag) + { + // PLL0 clock lock lost. Do something. + } + endcode + * + * return Logical OR value of the ref _mcg_status_flags_t. + */ uint32_t CLOCK_GetStatusFlags(void) { uint32_t ret = 0U; @@ -949,6 +1141,22 @@ uint32_t CLOCK_GetStatusFlags(void) return ret; } +/*! + * brief Clears the MCG status flags. + * + * This function clears the MCG clock lock lost status. The parameter is a logical + * OR value of the flags to clear. See ref _mcg_status_flags_t. + * + * Example: + * code + // To clear the clock lost lock status flags of OSC0 and PLL0. + + CLOCK_ClearStatusFlags(kMCG_Osc0LostFlag | kMCG_Pll0LostFlag); + endcode + * + * param mask The status flags to clear. This is a logical OR of members of the + * enumeration ref _mcg_status_flags_t. + */ void CLOCK_ClearStatusFlags(uint32_t mask) { uint8_t reg; @@ -968,6 +1176,13 @@ void CLOCK_ClearStatusFlags(uint32_t mask) } } +/*! + * brief Initializes the OSC0. + * + * This function initializes the OSC0 according to the board configuration. + * + * param config Pointer to the OSC0 configuration structure. + */ void CLOCK_InitOsc0(osc_config_t const *config) { uint8_t range = CLOCK_GetOscRangeFromFreq(config->freq); @@ -986,12 +1201,35 @@ void CLOCK_InitOsc0(osc_config_t const *config) } } +/*! + * brief Deinitializes the OSC0. + * + * This function deinitializes the OSC0. + */ void CLOCK_DeinitOsc0(void) { OSC0->CR = 0U; MCG->C2 &= ~OSC_MODE_MASK; } +/*! + * brief Auto trims the internal reference clock. + * + * This function trims the internal reference clock by using the external clock. If + * successful, it returns the kStatus_Success and the frequency after + * trimming is received in the parameter p actualFreq. If an error occurs, + * the error code is returned. + * + * param extFreq External clock frequency, which should be a bus clock. + * param desireFreq Frequency to trim to. + * param actualFreq Actual frequency after trimming. + * param atms Trim fast or slow internal reference clock. + * retval kStatus_Success ATM success. + * retval kStatus_MCG_AtmBusClockInvalid The bus clock is not in allowed range for the ATM. + * retval kStatus_MCG_AtmDesiredFreqInvalid MCGIRCLK could not be trimmed to the desired frequency. + * retval kStatus_MCG_AtmIrcUsed Could not trim because MCGIRCLK is used as a bus clock source. + * retval kStatus_MCG_AtmHardwareFail Hardware fails while trimming. + */ status_t CLOCK_TrimInternalRefClk(uint32_t extFreq, uint32_t desireFreq, uint32_t *actualFreq, mcg_atm_select_t atms) { uint32_t multi; /* extFreq / desireFreq */ @@ -1068,6 +1306,13 @@ status_t CLOCK_TrimInternalRefClk(uint32_t extFreq, uint32_t desireFreq, uint32_ return kStatus_Success; } +/*! + * brief Gets the current MCG mode. + * + * This function checks the MCG registers and determines the current MCG mode. + * + * return Current MCG mode or error code; See ref mcg_mode_t. + */ mcg_mode_t CLOCK_GetMode(void) { mcg_mode_t mode = kMCG_ModeError; @@ -1168,6 +1413,21 @@ mcg_mode_t CLOCK_GetMode(void) return mode; } +/*! + * brief Sets the MCG to FEI mode. + * + * This function sets the MCG to FEI mode. If setting to FEI mode fails + * from the current mode, this function returns an error. + * + * param dmx32 DMX32 in FEI mode. + * param drs The DCO range selection. + * param fllStableDelay Delay function to ensure that the FLL is stable. Passing + * NULL does not cause a delay. + * retval kStatus_MCG_ModeUnreachable Could not switch to the target mode. + * retval kStatus_Success Switched to the target mode successfully. + * note If p dmx32 is set to kMCG_Dmx32Fine, the slow IRC must not be trimmed + * to a frequency above 32768 Hz. + */ status_t CLOCK_SetFeiMode(mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void)) { uint8_t mcg_c4; @@ -1228,6 +1488,21 @@ status_t CLOCK_SetFeiMode(mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDela return kStatus_Success; } +/*! + * brief Sets the MCG to FEE mode. + * + * This function sets the MCG to FEE mode. If setting to FEE mode fails + * from the current mode, this function returns an error. + * + * param frdiv FLL reference clock divider setting, FRDIV. + * param dmx32 DMX32 in FEE mode. + * param drs The DCO range selection. + * param fllStableDelay Delay function to make sure FLL is stable. Passing + * NULL does not cause a delay. + * + * retval kStatus_MCG_ModeUnreachable Could not switch to the target mode. + * retval kStatus_Success Switched to the target mode successfully. + */ status_t CLOCK_SetFeeMode(uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void)) { uint8_t mcg_c4; @@ -1306,6 +1581,22 @@ status_t CLOCK_SetFeeMode(uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void return kStatus_Success; } +/*! + * brief Sets the MCG to FBI mode. + * + * This function sets the MCG to FBI mode. If setting to FBI mode fails + * from the current mode, this function returns an error. + * + * param dmx32 DMX32 in FBI mode. + * param drs The DCO range selection. + * param fllStableDelay Delay function to make sure FLL is stable. If the FLL + * is not used in FBI mode, this parameter can be NULL. Passing + * NULL does not cause a delay. + * retval kStatus_MCG_ModeUnreachable Could not switch to the target mode. + * retval kStatus_Success Switched to the target mode successfully. + * note If p dmx32 is set to kMCG_Dmx32Fine, the slow IRC must not be trimmed + * to frequency above 32768 Hz. + */ status_t CLOCK_SetFbiMode(mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void)) { uint8_t mcg_c4; @@ -1370,6 +1661,21 @@ status_t CLOCK_SetFbiMode(mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDela return kStatus_Success; } +/*! + * brief Sets the MCG to FBE mode. + * + * This function sets the MCG to FBE mode. If setting to FBE mode fails + * from the current mode, this function returns an error. + * + * param frdiv FLL reference clock divider setting, FRDIV. + * param dmx32 DMX32 in FBE mode. + * param drs The DCO range selection. + * param fllStableDelay Delay function to make sure FLL is stable. If the FLL + * is not used in FBE mode, this parameter can be NULL. Passing NULL + * does not cause a delay. + * retval kStatus_MCG_ModeUnreachable Could not switch to the target mode. + * retval kStatus_Success Switched to the target mode successfully. + */ status_t CLOCK_SetFbeMode(uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void)) { uint8_t mcg_c4; @@ -1453,6 +1759,15 @@ status_t CLOCK_SetFbeMode(uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void return kStatus_Success; } +/*! + * brief Sets the MCG to BLPI mode. + * + * This function sets the MCG to BLPI mode. If setting to BLPI mode fails + * from the current mode, this function returns an error. + * + * retval kStatus_MCG_ModeUnreachable Could not switch to the target mode. + * retval kStatus_Success Switched to the target mode successfully. + */ status_t CLOCK_SetBlpiMode(void) { #if (defined(MCG_CONFIG_CHECK_PARAM) && MCG_CONFIG_CHECK_PARAM) @@ -1468,6 +1783,15 @@ status_t CLOCK_SetBlpiMode(void) return kStatus_Success; } +/*! + * brief Sets the MCG to BLPE mode. + * + * This function sets the MCG to BLPE mode. If setting to BLPE mode fails + * from the current mode, this function returns an error. + * + * retval kStatus_MCG_ModeUnreachable Could not switch to the target mode. + * retval kStatus_Success Switched to the target mode successfully. + */ status_t CLOCK_SetBlpeMode(void) { #if (defined(MCG_CONFIG_CHECK_PARAM) && MCG_CONFIG_CHECK_PARAM) @@ -1483,6 +1807,25 @@ status_t CLOCK_SetBlpeMode(void) return kStatus_Success; } +/*! + * brief Sets the MCG to PBE mode. + * + * This function sets the MCG to PBE mode. If setting to PBE mode fails + * from the current mode, this function returns an error. + * + * param pllcs The PLL selection, PLLCS. + * param config Pointer to the PLL configuration. + * retval kStatus_MCG_ModeUnreachable Could not switch to the target mode. + * retval kStatus_Success Switched to the target mode successfully. + * + * note + * 1. The parameter \c pllcs selects the PLL. For platforms with + * only one PLL, the parameter pllcs is kept for interface compatibility. + * 2. The parameter \c config is the PLL configuration structure. On some + * platforms, it is possible to choose the external PLL directly, which renders the + * configuration structure not necessary. In this case, pass in NULL. + * For example: CLOCK_SetPbeMode(kMCG_OscselOsc, kMCG_PllClkSelExtPll, NULL); + */ status_t CLOCK_SetPbeMode(mcg_pll_clk_select_t pllcs, mcg_pll_config_t const *config) { assert(config); @@ -1524,6 +1867,18 @@ status_t CLOCK_SetPbeMode(mcg_pll_clk_select_t pllcs, mcg_pll_config_t const *co return kStatus_Success; } +/*! + * brief Sets the MCG to PEE mode. + * + * This function sets the MCG to PEE mode. + * + * retval kStatus_MCG_ModeUnreachable Could not switch to the target mode. + * retval kStatus_Success Switched to the target mode successfully. + * + * note This function only changes the CLKS to use the PLL/FLL output. If the + * PRDIV/VDIV are different than in the PBE mode, set them up + * in PBE mode and wait. When the clock is stable, switch to PEE mode. + */ status_t CLOCK_SetPeeMode(void) { #if (defined(MCG_CONFIG_CHECK_PARAM) && MCG_CONFIG_CHECK_PARAM) @@ -1545,6 +1900,22 @@ status_t CLOCK_SetPeeMode(void) return kStatus_Success; } +/*! + * brief Switches the MCG to FBE mode from the external mode. + * + * This function switches the MCG from external modes (PEE/PBE/BLPE/FEE) to the FBE mode quickly. + * The external clock is used as the system clock source and PLL is disabled. However, + * the FLL settings are not configured. This is a lite function with a small code size, which is useful + * during the mode switch. For example, to switch from PEE mode to FEI mode: + * + * code + * CLOCK_ExternalModeToFbeModeQuick(); + * CLOCK_SetFeiMode(...); + * endcode + * + * retval kStatus_Success Switched successfully. + * retval kStatus_MCG_ModeInvalid If the current mode is not an external mode, do not call this function. + */ status_t CLOCK_ExternalModeToFbeModeQuick(void) { #if (defined(MCG_CONFIG_CHECK_PARAM) && MCG_CONFIG_CHECK_PARAM) @@ -1571,6 +1942,22 @@ status_t CLOCK_ExternalModeToFbeModeQuick(void) return kStatus_Success; } +/*! + * brief Switches the MCG to FBI mode from internal modes. + * + * This function switches the MCG from internal modes (PEI/PBI/BLPI/FEI) to the FBI mode quickly. + * The MCGIRCLK is used as the system clock source and PLL is disabled. However, + * FLL settings are not configured. This is a lite function with a small code size, which is useful + * during the mode switch. For example, to switch from PEI mode to FEE mode: + * + * code + * CLOCK_InternalModeToFbiModeQuick(); + * CLOCK_SetFeeMode(...); + * endcode + * + * retval kStatus_Success Switched successfully. + * retval kStatus_MCG_ModeInvalid If the current mode is not an internal mode, do not call this function. + */ status_t CLOCK_InternalModeToFbiModeQuick(void) { #if (defined(MCG_CONFIG_CHECK_PARAM) && MCG_CONFIG_CHECK_PARAM) @@ -1591,11 +1978,41 @@ status_t CLOCK_InternalModeToFbiModeQuick(void) return kStatus_Success; } +/*! + * brief Sets the MCG to FEI mode during system boot up. + * + * This function sets the MCG to FEI mode from the reset mode. It can also be used to + * set up MCG during system boot up. + * + * param dmx32 DMX32 in FEI mode. + * param drs The DCO range selection. + * param fllStableDelay Delay function to ensure that the FLL is stable. + * + * retval kStatus_MCG_ModeUnreachable Could not switch to the target mode. + * retval kStatus_Success Switched to the target mode successfully. + * note If p dmx32 is set to kMCG_Dmx32Fine, the slow IRC must not be trimmed + * to frequency above 32768 Hz. + */ status_t CLOCK_BootToFeiMode(mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void)) { return CLOCK_SetFeiMode(dmx32, drs, fllStableDelay); } +/*! + * brief Sets the MCG to FEE mode during system bootup. + * + * This function sets MCG to FEE mode from the reset mode. It can also be used to + * set up the MCG during system boot up. + * + * param oscsel OSC clock select, OSCSEL. + * param frdiv FLL reference clock divider setting, FRDIV. + * param dmx32 DMX32 in FEE mode. + * param drs The DCO range selection. + * param fllStableDelay Delay function to ensure that the FLL is stable. + * + * retval kStatus_MCG_ModeUnreachable Could not switch to the target mode. + * retval kStatus_Success Switched to the target mode successfully. + */ status_t CLOCK_BootToFeeMode( mcg_oscsel_t oscsel, uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void)) { @@ -1604,6 +2021,19 @@ status_t CLOCK_BootToFeeMode( return CLOCK_SetFeeMode(frdiv, dmx32, drs, fllStableDelay); } +/*! + * brief Sets the MCG to BLPI mode during system boot up. + * + * This function sets the MCG to BLPI mode from the reset mode. It can also be used to + * set up the MCG during system boot up. + * + * param fcrdiv Fast IRC divider, FCRDIV. + * param ircs The internal reference clock to select, IRCS. + * param ircEnableMode The MCGIRCLK enable mode, OR'ed value of ref _mcg_irclk_enable_mode. + * + * retval kStatus_MCG_SourceUsed Could not change MCGIRCLK setting. + * retval kStatus_Success Switched to the target mode successfully. + */ status_t CLOCK_BootToBlpiMode(uint8_t fcrdiv, mcg_irc_mode_t ircs, uint8_t ircEnableMode) { /* If reset mode is FEI mode, set MCGIRCLK and always success. */ @@ -1621,6 +2051,17 @@ status_t CLOCK_BootToBlpiMode(uint8_t fcrdiv, mcg_irc_mode_t ircs, uint8_t ircEn return kStatus_Success; } +/*! + * brief Sets the MCG to BLPE mode during system boot up. + * + * This function sets the MCG to BLPE mode from the reset mode. It can also be used to + * set up the MCG during system boot up. + * + * param oscsel OSC clock select, MCG_C7[OSCSEL]. + * + * retval kStatus_MCG_ModeUnreachable Could not switch to the target mode. + * retval kStatus_Success Switched to the target mode successfully. + */ status_t CLOCK_BootToBlpeMode(mcg_oscsel_t oscsel) { CLOCK_SetExternalRefClkConfig(oscsel); @@ -1653,6 +2094,19 @@ status_t CLOCK_BootToBlpeMode(mcg_oscsel_t oscsel) return kStatus_Success; } +/*! + * brief Sets the MCG to PEE mode during system boot up. + * + * This function sets the MCG to PEE mode from reset mode. It can also be used to + * set up the MCG during system boot up. + * + * param oscsel OSC clock select, MCG_C7[OSCSEL]. + * param pllcs The PLL selection, PLLCS. + * param config Pointer to the PLL configuration. + * + * retval kStatus_MCG_ModeUnreachable Could not switch to the target mode. + * retval kStatus_Success Switched to the target mode successfully. + */ status_t CLOCK_BootToPeeMode(mcg_oscsel_t oscsel, mcg_pll_clk_select_t pllcs, mcg_pll_config_t const *config) { assert(config); @@ -1699,6 +2153,20 @@ static const mcg_mode_t mcgModeMatrix[8][8] = { /* FEI FBI BLPI FEE FBE BLPE PBE PEE */ }; +/*! + * brief Sets the MCG to a target mode. + * + * This function sets MCG to a target mode defined by the configuration + * structure. If switching to the target mode fails, this function + * chooses the correct path. + * + * param config Pointer to the target MCG mode configuration structure. + * return Return kStatus_Success if switched successfully; Otherwise, it returns an error code #_mcg_status. + * + * note If the external clock is used in the target mode, ensure that it is + * enabled. For example, if the OSC0 is used, set up OSC0 correctly before calling this + * function. + */ status_t CLOCK_SetMcgConfig(const mcg_config_t *config) { mcg_mode_t next_mode; @@ -1710,10 +2178,10 @@ status_t CLOCK_SetMcgConfig(const mcg_config_t *config) if (MCG_C7_OSCSEL_VAL != config->oscsel) { /* If external clock is in use, change to FEI first. */ - if (!(MCG->S & MCG_S_IRCST_MASK)) + if (kMCG_FllSrcExternal == MCG_S_IREFST_VAL) { CLOCK_ExternalModeToFbeModeQuick(); - CLOCK_SetFeiMode(config->dmx32, config->drs, (void (*)(void))0); + CLOCK_SetFeiMode(config->dmx32, config->drs, NULL); } CLOCK_SetExternalRefClkConfig(config->oscsel); @@ -1747,10 +2215,10 @@ status_t CLOCK_SetMcgConfig(const mcg_config_t *config) status = CLOCK_SetFeeMode(config->frdiv, config->dmx32, config->drs, CLOCK_FllStableDelay); break; case kMCG_ModeFBI: - status = CLOCK_SetFbiMode(config->dmx32, config->drs, (void (*)(void))0); + status = CLOCK_SetFbiMode(config->dmx32, config->drs, NULL); break; case kMCG_ModeFBE: - status = CLOCK_SetFbeMode(config->frdiv, config->dmx32, config->drs, (void (*)(void))0); + status = CLOCK_SetFbeMode(config->frdiv, config->dmx32, config->drs, NULL); break; case kMCG_ModeBLPI: status = CLOCK_SetBlpiMode(); diff --git a/ext/hal/nxp/mcux/devices/MK64F12/fsl_clock.h b/ext/hal/nxp/mcux/devices/MK64F12/fsl_clock.h index 3db95a04e57..13ac8fa98a4 100644 --- a/ext/hal/nxp/mcux/devices/MK64F12/fsl_clock.h +++ b/ext/hal/nxp/mcux/devices/MK64F12/fsl_clock.h @@ -3,30 +3,8 @@ * Copyright (c) 2016 - 2017 , NXP * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * SPDX-License-Identifier: BSD-3-Clause */ #ifndef _FSL_CLOCK_H_ @@ -65,7 +43,7 @@ * * When set to 0, peripheral drivers will enable clock in initialize function * and disable clock in de-initialize function. When set to 1, peripheral - * driver will not control the clock, application could contol the clock out of + * driver will not control the clock, application could control the clock out of * the driver. * * @note All drivers share this feature switcher. If it is set to 1, application @@ -99,7 +77,7 @@ * OSC0 using the CLOCK_InitOsc0. All other cores need to call the CLOCK_SetXtal0Freq * to get a valid clock frequency. */ -extern uint32_t g_xtal0Freq; +extern volatile uint32_t g_xtal0Freq; /*! @brief External XTAL32/EXTAL32/RTC_CLKIN clock frequency. * @@ -110,7 +88,7 @@ extern uint32_t g_xtal0Freq; * the clock. All other cores need to call the CLOCK_SetXtal32Freq * to get a valid clock frequency. */ -extern uint32_t g_xtal32Freq; +extern volatile uint32_t g_xtal32Freq; /*! @brief IRC48M clock frequency in Hz. */ #define MCG_INTERNAL_IRC_48M 48000000U @@ -1005,8 +983,8 @@ static inline void CLOCK_SetLowPowerEnable(bool enable) * @param enableMode MCGIRCLK enable mode, OR'ed value of @ref _mcg_irclk_enable_mode. * @param ircs MCGIRCLK clock source, choose fast or slow. * @param fcrdiv Fast IRC divider setting (\c FCRDIV). - * @retval kStatus_MCG_SourceUsed Because the internall reference clock is used as a clock source, - * the confuration should not be changed. Otherwise, a glitch occurs. + * @retval kStatus_MCG_SourceUsed Because the internal reference clock is used as a clock source, + * the configuration should not be changed. Otherwise, a glitch occurs. * @retval kStatus_Success MCGIRCLK configuration finished successfully. */ status_t CLOCK_SetInternalRefClkConfig(uint8_t enableMode, mcg_irc_mode_t ircs, uint8_t fcrdiv); @@ -1020,7 +998,7 @@ status_t CLOCK_SetInternalRefClkConfig(uint8_t enableMode, mcg_irc_mode_t ircs, * * @param oscsel MCG external reference clock source, MCG_C7[OSCSEL]. * @retval kStatus_MCG_SourceUsed Because the external reference clock is used as a clock source, - * the confuration should not be changed. Otherwise, a glitch occurs. + * the configuration should not be changed. Otherwise, a glitch occurs. * @retval kStatus_Success External reference clock set successfully. */ status_t CLOCK_SetExternalRefClkConfig(mcg_oscsel_t oscsel); @@ -1431,7 +1409,7 @@ status_t CLOCK_SetPeeMode(void); * @brief Switches the MCG to FBE mode from the external mode. * * This function switches the MCG from external modes (PEE/PBE/BLPE/FEE) to the FBE mode quickly. - * The external clock is used as the system clock souce and PLL is disabled. However, + * The external clock is used as the system clock source and PLL is disabled. However, * the FLL settings are not configured. This is a lite function with a small code size, which is useful * during the mode switch. For example, to switch from PEE mode to FEI mode: * @@ -1449,7 +1427,7 @@ status_t CLOCK_ExternalModeToFbeModeQuick(void); * @brief Switches the MCG to FBI mode from internal modes. * * This function switches the MCG from internal modes (PEI/PBI/BLPI/FEI) to the FBI mode quickly. - * The MCGIRCLK is used as the system clock souce and PLL is disabled. However, + * The MCGIRCLK is used as the system clock source and PLL is disabled. However, * FLL settings are not configured. This is a lite function with a small code size, which is useful * during the mode switch. For example, to switch from PEI mode to FEE mode: * @@ -1502,7 +1480,7 @@ status_t CLOCK_BootToFeeMode( * @brief Sets the MCG to BLPI mode during system boot up. * * This function sets the MCG to BLPI mode from the reset mode. It can also be used to - * set up the MCG during sytem boot up. + * set up the MCG during system boot up. * * @param fcrdiv Fast IRC divider, FCRDIV. * @param ircs The internal reference clock to select, IRCS. @@ -1514,10 +1492,10 @@ status_t CLOCK_BootToFeeMode( status_t CLOCK_BootToBlpiMode(uint8_t fcrdiv, mcg_irc_mode_t ircs, uint8_t ircEnableMode); /*! - * @brief Sets the MCG to BLPE mode during sytem boot up. + * @brief Sets the MCG to BLPE mode during system boot up. * * This function sets the MCG to BLPE mode from the reset mode. It can also be used to - * set up the MCG during sytem boot up. + * set up the MCG during system boot up. * * @param oscsel OSC clock select, MCG_C7[OSCSEL]. * diff --git a/ext/hal/nxp/mcux/devices/MK64F12/fsl_device_registers.h b/ext/hal/nxp/mcux/devices/MK64F12/fsl_device_registers.h index 2ca0dc42a53..562a5b97066 100644 --- a/ext/hal/nxp/mcux/devices/MK64F12/fsl_device_registers.h +++ b/ext/hal/nxp/mcux/devices/MK64F12/fsl_device_registers.h @@ -1,31 +1,9 @@ /* - * Copyright (c) 2014 - 2016, Freescale Semiconductor, Inc. - * All rights reserved. + * Copyright 2014-2016 Freescale Semiconductor, Inc. + * Copyright 2016-2018 NXP * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * SPDX-License-Identifier: BSD-3-Clause * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of Freescale Semiconductor, Inc. nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #ifndef __FSL_DEVICE_REGISTERS_H__ diff --git a/ext/hal/nxp/mcux/devices/MK64F12/system_MK64F12.c b/ext/hal/nxp/mcux/devices/MK64F12/system_MK64F12.c index 21f31aa63d5..df96c1046eb 100644 --- a/ext/hal/nxp/mcux/devices/MK64F12/system_MK64F12.c +++ b/ext/hal/nxp/mcux/devices/MK64F12/system_MK64F12.c @@ -18,39 +18,17 @@ ** ** Reference manual: K64P144M120SF5RM, Rev.2, January 2014 ** Version: rev. 2.9, 2016-03-21 -** Build: b170112 +** Build: b180801 ** ** Abstract: ** Provides a system configuration function and a global variable that ** contains the system frequency. It configures the device and initializes ** the oscillator (PLL) that is part of the microcontroller device. ** -** Copyright (c) 2016 Freescale Semiconductor, Inc. -** Copyright 2016 - 2017 NXP -** Redistribution and use in source and binary forms, with or without modification, -** are permitted provided that the following conditions are met: +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2018 NXP ** -** o Redistributions of source code must retain the above copyright notice, this list -** of conditions and the following disclaimer. -** -** o Redistributions in binary form must reproduce the above copyright notice, this -** list of conditions and the following disclaimer in the documentation and/or -** other materials provided with the distribution. -** -** o Neither the name of the copyright holder nor the names of its -** contributors may be used to endorse or promote products derived from this -** software without specific prior written permission. -** -** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** SPDX-License-Identifier: BSD-3-Clause ** ** http: www.nxp.com ** mail: support@nxp.com @@ -138,6 +116,7 @@ void SystemInit (void) { 0x0100U; #endif /* (DISABLE_WDOG) */ + SystemInitHook(); } /* ---------------------------------------------------------------------------- @@ -249,3 +228,11 @@ void SystemCoreClockUpdate (void) { } /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U)) */ SystemCoreClock = (MCGOUTClock / (0x01U + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT))); } + +/* ---------------------------------------------------------------------------- + -- SystemInitHook() + ---------------------------------------------------------------------------- */ + +__attribute__ ((weak)) void SystemInitHook (void) { + /* Void implementation of the weak function. */ +} diff --git a/ext/hal/nxp/mcux/devices/MK64F12/system_MK64F12.h b/ext/hal/nxp/mcux/devices/MK64F12/system_MK64F12.h index d4bc76e8e08..cdaf2d2e080 100644 --- a/ext/hal/nxp/mcux/devices/MK64F12/system_MK64F12.h +++ b/ext/hal/nxp/mcux/devices/MK64F12/system_MK64F12.h @@ -18,39 +18,17 @@ ** ** Reference manual: K64P144M120SF5RM, Rev.2, January 2014 ** Version: rev. 2.9, 2016-03-21 -** Build: b170112 +** Build: b180801 ** ** Abstract: ** Provides a system configuration function and a global variable that ** contains the system frequency. It configures the device and initializes ** the oscillator (PLL) that is part of the microcontroller device. ** -** Copyright (c) 2016 Freescale Semiconductor, Inc. -** Copyright 2016 - 2017 NXP -** Redistribution and use in source and binary forms, with or without modification, -** are permitted provided that the following conditions are met: +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2018 NXP ** -** o Redistributions of source code must retain the above copyright notice, this list -** of conditions and the following disclaimer. -** -** o Redistributions in binary form must reproduce the above copyright notice, this -** list of conditions and the following disclaimer in the documentation and/or -** other materials provided with the distribution. -** -** o Neither the name of the copyright holder nor the names of its -** contributors may be used to endorse or promote products derived from this -** software without specific prior written permission. -** -** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** SPDX-License-Identifier: BSD-3-Clause ** ** http: www.nxp.com ** mail: support@nxp.com @@ -167,6 +145,18 @@ void SystemInit (void); */ void SystemCoreClockUpdate (void); +/** + * @brief SystemInit function hook. + * + * This weak function allows to call specific initialization code during the + * SystemInit() execution.This can be used when an application specific code needs + * to be called as close to the reset entry as possible (for example the Multicore + * Manager MCMGR_EarlyInit() function call). + * NOTE: No global r/w variables can be used in this hook function because the + * initialization of these variables happens after this function. + */ +void SystemInitHook (void); + #ifdef __cplusplus } #endif diff --git a/ext/hal/nxp/mcux/drivers/imx/fsl_adc.c b/ext/hal/nxp/mcux/drivers/imx/fsl_adc.c index 265e196936a..f8eb336c498 100644 --- a/ext/hal/nxp/mcux/drivers/imx/fsl_adc.c +++ b/ext/hal/nxp/mcux/drivers/imx/fsl_adc.c @@ -55,6 +55,12 @@ static uint32_t ADC_GetInstance(ADC_Type *base) return instance; } +/*! + * brief Initialize the ADC module. + * + * param base ADC peripheral base address. + * param config Pointer to "adc_config_t" structure. + */ void ADC_Init(ADC_Type *base, const adc_config_t *config) { assert(NULL != config); @@ -100,6 +106,11 @@ void ADC_Init(ADC_Type *base, const adc_config_t *config) base->GC = tmp32; } +/*! + * brief De-initializes the ADC module. + * + * param base ADC peripheral base address. + */ void ADC_Deinit(ADC_Type *base) { #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) @@ -108,10 +119,33 @@ void ADC_Deinit(ADC_Type *base) #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ } +/*! + * brief Gets an available pre-defined settings for the converter's configuration. + * + * This function initializes the converter configuration structure with available settings. The default values are: + * code + * config->enableAsynchronousClockOutput = true; + * config->enableOverWrite = false; + * config->enableContinuousConversion = false; + * config->enableHighSpeed = false; + * config->enableLowPower = false; + * config->enableLongSample = false; + * config->referenceVoltageSource = kADC_ReferenceVoltageSourceAlt0; + * config->samplePeriodMode = kADC_SamplePeriod2or12Clocks; + * config->clockSource = kADC_ClockSourceAD; + * config->clockDriver = kADC_ClockDriver1; + * config->resolution = kADC_Resolution12Bit; + * endcode + * param base ADC peripheral base address. + * param config Pointer to the configuration structure. + */ void ADC_GetDefaultConfig(adc_config_t *config) { assert(NULL != config); + /* Initializes the configure structure to zero. */ + memset(config, 0, sizeof(*config)); + config->enableAsynchronousClockOutput = true; config->enableOverWrite = false; config->enableContinuousConversion = false; @@ -125,6 +159,33 @@ void ADC_GetDefaultConfig(adc_config_t *config) config->resolution = kADC_Resolution12Bit; } +/*! + * brief Configures the conversion channel. + * + * This operation triggers the conversion when in software trigger mode. When in hardware trigger mode, this API + * configures the channel while the external trigger source helps to trigger the conversion. + * + * Note that the "Channel Group" has a detailed description. + * To allow sequential conversions of the ADC to be triggered by internal peripherals, the ADC has more than one + * group of status and control registers, one for each conversion. The channel group parameter indicates which group of + * registers are used, for example channel group 0 is for Group A registers and channel group 1 is for Group B + * registers. The + * channel groups are used in a "ping-pong" approach to control the ADC operation. At any point, only one of + * the channel groups is actively controlling ADC conversions. The channel group 0 is used for both software and + * hardware + * trigger modes. Channel groups 1 and greater indicate potentially multiple channel group registers for + * use only in hardware trigger mode. See the chip configuration information in the appropriate MCU reference manual + * about the + * number of SC1n registers (channel groups) specific to this device. None of the channel groups 1 or greater are used + * for software trigger operation. Therefore, writing to these channel groups does not initiate a new conversion. + * Updating the channel group 0 while a different channel group is actively controlling a conversion is allowed and + * vice versa. Writing any of the channel group registers while that specific channel group is actively controlling a + * conversion aborts the current conversion. + * + * param base ADC peripheral base address. + * param channelGroup Channel group index. + * param config Pointer to the "adc_channel_config_t" structure for the conversion channel. + */ void ADC_SetChannelConfig(ADC_Type *base, uint32_t channelGroup, const adc_channel_config_t *config) { assert(NULL != config); @@ -147,6 +208,19 @@ void ADC_SetChannelConfig(ADC_Type *base, uint32_t channelGroup, const adc_chann * 3. Check the status of CALF bit in ADC_GS and the CAL bit in ADC_GC. * 4. When CAL bit becomes '0' then check the CALF status and COCO[0] bit status. */ +/*! + * brief Automates the hardware calibration. + * + * This auto calibration helps to adjust the plus/minus side gain automatically. + * Execute the calibration before using the converter. Note that the software trigger should be used + * during calibration. + * + * param base ADC peripheral base address. + * + * return Execution status. + * retval kStatus_Success Calibration is done successfully. + * retval kStatus_Fail Calibration has failed. + */ status_t ADC_DoAutoCalibration(ADC_Type *base) { status_t status = kStatus_Success; @@ -201,6 +275,12 @@ status_t ADC_DoAutoCalibration(ADC_Type *base) return status; } +/*! + * brief Set user defined offset. + * + * param base ADC peripheral base address. + * param config Pointer to "adc_offest_config_t" structure. + */ void ADC_SetOffsetConfig(ADC_Type *base, const adc_offest_config_t *config) { assert(NULL != config); @@ -215,6 +295,19 @@ void ADC_SetOffsetConfig(ADC_Type *base, const adc_offest_config_t *config) base->OFS = tmp32; } +/*! + * brief Configures the hardware compare mode. + * + * The hardware compare mode provides a way to process the conversion result automatically by using hardware. Only the + * result + * in the compare range is available. To compare the range, see "adc_hardware_compare_mode_t" or the appopriate + * reference + * manual for more information. + * + * param base ADC peripheral base address. + * param Pointer to "adc_hardware_compare_config_t" structure. + * + */ void ADC_SetHardwareCompareConfig(ADC_Type *base, const adc_hardware_compare_config_t *config) { uint32_t tmp32; @@ -252,6 +345,16 @@ void ADC_SetHardwareCompareConfig(ADC_Type *base, const adc_hardware_compare_con base->CV = tmp32; } +/*! + * brief Configures the hardware average mode. + * + * The hardware average mode provides a way to process the conversion result automatically by using hardware. The + * multiple + * conversion results are accumulated and averaged internally making them easier to read. + * + * param base ADC peripheral base address. + * param mode Setting the hardware average mode. See "adc_hardware_average_mode_t". + */ void ADC_SetHardwareAverageConfig(ADC_Type *base, adc_hardware_average_mode_t mode) { uint32_t tmp32; @@ -269,6 +372,12 @@ void ADC_SetHardwareAverageConfig(ADC_Type *base, adc_hardware_average_mode_t mo } } +/*! + * brief Clears the converter's status falgs. + * + * param base ADC peripheral base address. + * param mask Mask value for the cleared flags. See "adc_status_flags_t". + */ void ADC_ClearStatusFlags(ADC_Type *base, uint32_t mask) { uint32_t tmp32 = 0; diff --git a/ext/hal/nxp/mcux/drivers/imx/fsl_adc_etc.c b/ext/hal/nxp/mcux/drivers/imx/fsl_adc_etc.c index 66f7fee9a8a..4a81c9fd9fc 100644 --- a/ext/hal/nxp/mcux/drivers/imx/fsl_adc_etc.c +++ b/ext/hal/nxp/mcux/drivers/imx/fsl_adc_etc.c @@ -55,6 +55,12 @@ static uint32_t ADC_ETC_GetInstance(ADC_ETC_Type *base) } #endif /* ADC_ETC_CLOCKS */ +/*! +* brief Initialize the ADC_ETC module. +* +* param base ADC_ETC peripheral base address. +* param config Pointer to "adc_etc_config_t" structure. +*/ void ADC_ETC_Init(ADC_ETC_Type *base, const adc_etc_config_t *config) { assert(NULL != config); @@ -94,6 +100,11 @@ void ADC_ETC_Init(ADC_ETC_Type *base, const adc_etc_config_t *config) base->CTRL = tmp32; } +/*! +* brief De-Initialize the ADC_ETC module. +* +* param base ADC_ETC peripheral base address. +*/ void ADC_ETC_Deinit(ADC_ETC_Type *base) { /* Do software reset to clear all logical. */ @@ -107,8 +118,26 @@ void ADC_ETC_Deinit(ADC_ETC_Type *base) #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ } +/*! +* brief Gets an available pre-defined settings for the ADC_ETC's configuration. +* This function initializes the ADC_ETC's configuration structure with available settings. The default values are: +* code +* config->enableTSCBypass = true; +* config->enableTSC0Trigger = false; +* config->enableTSC1Trigger = false; +* config->TSC0triggerPriority = 0U; +* config->TSC1triggerPriority = 0U; +* config->clockPreDivider = 0U; +* config->XBARtriggerMask = 0U; +* endCode +* +* param config Pointer to "adc_etc_config_t" structure. +*/ void ADC_ETC_GetDefaultConfig(adc_etc_config_t *config) { + /* Initializes the configure structure to zero. */ + memset(config, 0, sizeof(*config)); + config->enableTSCBypass = true; config->enableTSC0Trigger = false; config->enableTSC1Trigger = false; @@ -121,6 +150,13 @@ void ADC_ETC_GetDefaultConfig(adc_etc_config_t *config) config->XBARtriggerMask = 0U; } +/*! +* brief Set the external XBAR trigger configuration. +* +* param base ADC_ETC peripheral base address. +* param triggerGroup Trigger group index. +* param config Pointer to "adc_etc_trigger_config_t" structure. +*/ void ADC_ETC_SetTriggerConfig(ADC_ETC_Type *base, uint32_t triggerGroup, const adc_etc_trigger_config_t *config) { assert(triggerGroup < ADC_ETC_TRIGn_CTRL_COUNT); @@ -147,6 +183,16 @@ void ADC_ETC_SetTriggerConfig(ADC_ETC_Type *base, uint32_t triggerGroup, const a base->TRIG[triggerGroup].TRIGn_COUNTER = tmp32; } +/*! +* brief Set the external XBAR trigger chain configuration. +* For example, if triggerGroup is set to 0U and chainGroup is set to 1U, which means Trigger0 source's chain1 would be +* configurated. +* +* param base ADC_ETC peripheral base address. +* param triggerGroup Trigger group index. Available number is 0~7. +* param chainGroup Trigger chain group index. Available number is 0~7. +* param config Pointer to "adc_etc_trigger_chain_config_t" structure. +*/ void ADC_ETC_SetTriggerChainConfig(ADC_ETC_Type *base, uint32_t triggerGroup, uint32_t chainGroup, @@ -237,6 +283,14 @@ void ADC_ETC_SetTriggerChainConfig(ADC_ETC_Type *base, } } +/*! +* brief Gets the interrupt status flags of external XBAR and TSC triggers. +* +* param base ADC_ETC peripheral base address. +* param sourceIndex trigger source index. +* +* return Status flags mask of trigger. Refer to "_adc_etc_status_flag_mask". +*/ uint32_t ADC_ETC_GetInterruptStatusFlags(ADC_ETC_Type *base, adc_etc_external_trigger_source_t sourceIndex) { uint32_t tmp32 = 0U; @@ -264,6 +318,13 @@ uint32_t ADC_ETC_GetInterruptStatusFlags(ADC_ETC_Type *base, adc_etc_external_tr return tmp32; } +/*! +* brief Clears the ADC_ETC's interrupt status falgs. +* +* param base ADC_ETC peripheral base address. +* param sourceIndex trigger source index. +* param mask Status flags mask of trigger. Refer to "_adc_etc_status_flag_mask". +*/ void ADC_ETC_ClearInterruptStatusFlags(ADC_ETC_Type *base, adc_etc_external_trigger_source_t sourceIndex, uint32_t mask) { if (0U != (mask & kADC_ETC_Done0StatusFlagMask)) /* Write 1 to clear DONE0 status flags. */ @@ -284,6 +345,16 @@ void ADC_ETC_ClearInterruptStatusFlags(ADC_ETC_Type *base, adc_etc_external_trig } } +/*! +* brief Get ADC conversion result from external XBAR sources. +* For example, if triggerGroup is set to 0U and chainGroup is set to 1U, which means the API would +* return Trigger0 source's chain1 conversion result. +* +* param base ADC_ETC peripheral base address. +* param triggerGroup Trigger group index. Available number is 0~7. +* param chainGroup Trigger chain group index. Available number is 0~7. +* return ADC conversion result value. +*/ uint32_t ADC_ETC_GetADCConversionValue(ADC_ETC_Type *base, uint32_t triggerGroup, uint32_t chainGroup) { assert(triggerGroup < ADC_ETC_TRIGn_RESULT_1_0_COUNT); diff --git a/ext/hal/nxp/mcux/drivers/imx/fsl_aipstz.c b/ext/hal/nxp/mcux/drivers/imx/fsl_aipstz.c index abb11f31d72..d124af4728f 100644 --- a/ext/hal/nxp/mcux/drivers/imx/fsl_aipstz.c +++ b/ext/hal/nxp/mcux/drivers/imx/fsl_aipstz.c @@ -2,7 +2,7 @@ * Copyright (c) 2015, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP * All rights reserved. - * + * * SPDX-License-Identifier: BSD-3-Clause */ @@ -17,10 +17,16 @@ #define FSL_COMPONENT_ID "platform.drivers.aipstz" #endif - /******************************************************************************* * Prototypes ******************************************************************************/ +/*! + * brief Configure the privilege level for master. + * + * param base AIPSTZ peripheral base pointer + * param master Masters for AIPSTZ. + * param privilegeConfig Configuration is ORed from aipstz_master_privilege_level_t. + */ void AIPSTZ_SetMasterPriviledgeLevel(AIPSTZ_Type *base, aipstz_master_t master, uint32_t privilegeConfig) { uint32_t mask = ((uint32_t)master >> 8) - 1; @@ -28,6 +34,13 @@ void AIPSTZ_SetMasterPriviledgeLevel(AIPSTZ_Type *base, aipstz_master_t master, base->MPR = (base->MPR & (~(mask << shift))) | (privilegeConfig << shift); } +/*! + * brief Configure the access for peripheral. + * + * param base AIPSTZ peripheral base pointer + * param master Peripheral for AIPSTZ. + * param accessControl Configuration is ORed from aipstz_peripheral_access_control_t. + */ void AIPSTZ_SetPeripheralAccessControl(AIPSTZ_Type *base, aipstz_peripheral_t peripheral, uint32_t accessControl) { volatile uint32_t *reg = (uint32_t *)((uint32_t)base + ((uint32_t)peripheral >> 16)); @@ -36,5 +49,3 @@ void AIPSTZ_SetPeripheralAccessControl(AIPSTZ_Type *base, aipstz_peripheral_t pe *reg = (*reg & (~(mask << shift))) | ((accessControl & mask) << shift); } - - diff --git a/ext/hal/nxp/mcux/drivers/imx/fsl_aoi.c b/ext/hal/nxp/mcux/drivers/imx/fsl_aoi.c index 50337f82304..85d8b1fe974 100644 --- a/ext/hal/nxp/mcux/drivers/imx/fsl_aoi.c +++ b/ext/hal/nxp/mcux/drivers/imx/fsl_aoi.c @@ -2,7 +2,7 @@ * Copyright (c) 2015, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP * All rights reserved. - * + * * SPDX-License-Identifier: BSD-3-Clause */ #include "fsl_aoi.h" @@ -12,7 +12,6 @@ #define FSL_COMPONENT_ID "platform.drivers.aoi" #endif - /******************************************************************************* * Variables ******************************************************************************/ @@ -23,9 +22,9 @@ static AOI_Type *const s_aoiBases[] = AOI_BASE_PTRS; /*! @brief Pointers to aoi clocks for each instance. */ static const clock_ip_name_t s_aoiClocks[] = AOI_CLOCKS; #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -/******************************************************************************* - * Prototypes - ******************************************************************************/ + /******************************************************************************* + * Prototypes + ******************************************************************************/ /*! * @brief Get instance number for AOI module. * @@ -56,6 +55,13 @@ static uint32_t AOI_GetInstance(AOI_Type *base) return instance; } +/*! + * brief Initializes an AOI instance for operation. + * + * This function un-gates the AOI clock. + * + * param base AOI peripheral address. + */ void AOI_Init(AOI_Type *base) { #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) @@ -64,6 +70,13 @@ void AOI_Init(AOI_Type *base) #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ } +/*! + * brief Deinitializes an AOI instance for operation. + * + * This function shutdowns AOI module. + * + * param base AOI peripheral address. + */ void AOI_Deinit(AOI_Type *base) { #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) @@ -72,6 +85,22 @@ void AOI_Deinit(AOI_Type *base) #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ } +/*! + * brief Gets the Boolean evaluation associated. + * + * This function returns the Boolean evaluation associated. + * + * Example: + code + aoi_event_config_t demoEventLogicStruct; + + AOI_GetEventLogicConfig(AOI, kAOI_Event0, &demoEventLogicStruct); + endcode + * + * param base AOI peripheral address. + * param event Index of the event which will be set of type aoi_event_t. + * param config Selected input configuration . + */ void AOI_GetEventLogicConfig(AOI_Type *base, aoi_event_t event, aoi_event_config_t *config) { assert(event < FSL_FEATURE_AOI_EVENT_COUNT); @@ -106,6 +135,45 @@ void AOI_GetEventLogicConfig(AOI_Type *base, aoi_event_t event, aoi_event_config config->PT3DC = (aoi_input_config_t)((value & AOI_BFCRT23_PT3_DC_MASK) >> AOI_BFCRT23_PT3_DC_SHIFT); } +/*! + * brief Configures an AOI event. + * + * This function configures an AOI event according + * to the aoiEventConfig structure. This function configures all inputs (A, B, C, and D) + * of all product terms (0, 1, 2, and 3) of a desired event. + * + * Example: + code + aoi_event_config_t demoEventLogicStruct; + + demoEventLogicStruct.PT0AC = kAOI_InvInputSignal; + demoEventLogicStruct.PT0BC = kAOI_InputSignal; + demoEventLogicStruct.PT0CC = kAOI_LogicOne; + demoEventLogicStruct.PT0DC = kAOI_LogicOne; + + demoEventLogicStruct.PT1AC = kAOI_LogicZero; + demoEventLogicStruct.PT1BC = kAOI_LogicOne; + demoEventLogicStruct.PT1CC = kAOI_LogicOne; + demoEventLogicStruct.PT1DC = kAOI_LogicOne; + + demoEventLogicStruct.PT2AC = kAOI_LogicZero; + demoEventLogicStruct.PT2BC = kAOI_LogicOne; + demoEventLogicStruct.PT2CC = kAOI_LogicOne; + demoEventLogicStruct.PT2DC = kAOI_LogicOne; + + demoEventLogicStruct.PT3AC = kAOI_LogicZero; + demoEventLogicStruct.PT3BC = kAOI_LogicOne; + demoEventLogicStruct.PT3CC = kAOI_LogicOne; + demoEventLogicStruct.PT3DC = kAOI_LogicOne; + + AOI_SetEventLogicConfig(AOI, kAOI_Event0, demoEventLogicStruct); + endcode + * + * param base AOI peripheral address. + * param event Event which will be configured of type aoi_event_t. + * param eventConfig Pointer to type aoi_event_config_t structure. The user is responsible for + * filling out the members of this structure and passing the pointer to this function. + */ void AOI_SetEventLogicConfig(AOI_Type *base, aoi_event_t event, const aoi_event_config_t *eventConfig) { assert(eventConfig != NULL); diff --git a/ext/hal/nxp/mcux/drivers/imx/fsl_bee.c b/ext/hal/nxp/mcux/drivers/imx/fsl_bee.c index ff6d1a0ff3a..8342476a197 100644 --- a/ext/hal/nxp/mcux/drivers/imx/fsl_bee.c +++ b/ext/hal/nxp/mcux/drivers/imx/fsl_bee.c @@ -2,7 +2,7 @@ * Copyright 2017 NXP * All rights reserved. * - * + * * SPDX-License-Identifier: BSD-3-Clause */ @@ -17,7 +17,6 @@ #define FSL_COMPONENT_ID "platform.drivers.bee" #endif - /******************************************************************************* * Variables ******************************************************************************/ @@ -40,6 +39,13 @@ static void aligned_memcpy(void *dst, const void *src, size_t size) } } +/*! + * brief Resets BEE module to factory default values. + * + * This function performs hardware reset of BEE module. Attributes and keys from software for both regions are cleared. + * + * param base BEE peripheral address. + */ void BEE_Init(BEE_Type *base) { #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) @@ -49,6 +55,14 @@ void BEE_Init(BEE_Type *base) base->CTRL = BEE_CTRL_CTRL_SFTRST_N_MASK | BEE_CTRL_CTRL_CLK_EN_MASK; } +/*! + * brief Resets BEE module, clears keys for both regions and disables clock to the BEE. + * + * This function performs hardware reset of BEE module and disables clocks. Attributes and keys from software for both + * regions are cleared. + * + * param base BEE peripheral address. + */ void BEE_Deinit(BEE_Type *base) { base->CTRL &= @@ -59,10 +73,32 @@ void BEE_Deinit(BEE_Type *base) #endif } +/*! + * brief Loads default values to the BEE region configuration structure. + * + * Loads default values to the BEE region configuration structure. The default values are as follows: + * code + * config->region0Mode = kBEE_AesCtrMode; + * config->region1Mode = kBEE_AesCtrMode; + * config->region0AddrOffset = 0U; + * config->region1AddrOffset = 0U; + * config->region0SecLevel = kBEE_SecurityLevel3; + * config->region1SecLevel = kBEE_SecurityLevel3; + * config->region1Bot = 0U; + * config->region1Top = 0U; + * config->accessPermission = kBEE_AccessProtDisabled; + * config->endianSwapEn = kBEE_EndianSwapEnabled; + * endcode + * + * param config Configuration structure for BEE peripheral. + */ void BEE_GetDefaultConfig(bee_region_config_t *config) { assert(config); + /* Initializes the configure structure to zero. */ + memset(config, 0, sizeof(*config)); + config->region0Mode = kBEE_AesCtrMode; config->region1Mode = kBEE_AesCtrMode; config->region0AddrOffset = 0U; @@ -75,6 +111,14 @@ void BEE_GetDefaultConfig(bee_region_config_t *config) config->endianSwapEn = kBEE_EndianSwapEnabled; } +/*! + * brief Sets BEE configuration. + * + * This function sets BEE peripheral and BEE region settings accorging to given configuration structure. + * + * param base BEE peripheral address. + * param config Configuration structure for BEE. + */ void BEE_SetConfig(BEE_Type *base, const bee_region_config_t *config) { uint32_t beeCtrlVal; @@ -96,8 +140,8 @@ void BEE_SetConfig(BEE_Type *base, const bee_region_config_t *config) beeCtrlVal = base->CTRL & 0xFFFF0037; /* Set variable according to configuration */ - beeCtrlVal |= BEE_CTRL_AC_PROT_EN(config->accessPermission) | BEE_CTRL_LITTLE_ENDIAN(config->endianSwapEn) |\ - BEE_CTRL_SECURITY_LEVEL_R0(config->region0SecLevel) | BEE_CTRL_CTRL_AES_MODE_R0(config->region0Mode) |\ + beeCtrlVal |= BEE_CTRL_AC_PROT_EN(config->accessPermission) | BEE_CTRL_LITTLE_ENDIAN(config->endianSwapEn) | + BEE_CTRL_SECURITY_LEVEL_R0(config->region0SecLevel) | BEE_CTRL_CTRL_AES_MODE_R0(config->region0Mode) | BEE_CTRL_SECURITY_LEVEL_R1(config->region1SecLevel) | BEE_CTRL_CTRL_AES_MODE_R1(config->region1Mode); /* Load values to registers */ @@ -114,8 +158,21 @@ void BEE_SetConfig(BEE_Type *base, const bee_region_config_t *config) } } -status_t BEE_SetRegionKey( - BEE_Type *base, bee_region_t region, const uint8_t *key, size_t keySize) +/*! + * brief Loads the AES key for selected region into BEE key registers. + * + * This function loads given AES key to BEE register for the given region. + * The key must be 32-bit aligned and stored in little-endian format. + * + * Please note, that eFuse BEE_KEYx_SEL must be set accordingly to be able to load and use key loaded in BEE registers. + * Otherwise, key cannot loaded and BEE will use key from OTPMK or SW_GP2. + * + * param base BEE peripheral address. + * param region Selection of the BEE region to be configured. + * param key AES key (in little-endian format). + * param keySize Size of AES key. + */ +status_t BEE_SetRegionKey(BEE_Type *base, bee_region_t region, const uint8_t *key, size_t keySize) { bool redisable = false; @@ -174,8 +231,18 @@ status_t BEE_SetRegionKey( return kStatus_Success; } -status_t BEE_SetRegionNonce( - BEE_Type *base, bee_region_t region, const uint8_t *nonce, size_t nonceSize) +/*! + * brief Loads the nonce for selected region into BEE nonce registers. + * + * This function loads given nonce(only AES CTR mode) to BEE register for the given region. + * The nonce must be 32-bit aligned and stored in little-endian format. + * + * param base BEE peripheral address. + * param region Selection of the BEE region to be configured. + * param nonce AES nonce (in little-endian format). + * param nonceSize Size of AES nonce. + */ +status_t BEE_SetRegionNonce(BEE_Type *base, bee_region_t region, const uint8_t *nonce, size_t nonceSize) { /* Nonce must be 32-bit aligned */ if (((uintptr_t)nonce & 0x3u) || (nonceSize != 16)) @@ -207,11 +274,28 @@ status_t BEE_SetRegionNonce( return kStatus_Success; } +/*! + * brief Gets the BEE status flags. + * + * This function returns status of BEE peripheral. + * + * param base BEE peripheral address. + * + * return The status flags. This is the logical OR of members of the + * enumeration ::bee_status_flags_t + */ uint32_t BEE_GetStatusFlags(BEE_Type *base) { return base->STATUS; } +/*! + * brief Clears the BEE status flags. + * + * param base BEE peripheral base address. + * param mask The status flags to clear. This is a logical OR of members of the + * enumeration ::bee_status_flags_t + */ void BEE_ClearStatusFlags(BEE_Type *base, uint32_t mask) { /* w1c */ diff --git a/ext/hal/nxp/mcux/drivers/imx/fsl_cache.c b/ext/hal/nxp/mcux/drivers/imx/fsl_cache.c index 3c3ccd16ca9..d4ce59e1039 100644 --- a/ext/hal/nxp/mcux/drivers/imx/fsl_cache.c +++ b/ext/hal/nxp/mcux/drivers/imx/fsl_cache.c @@ -2,7 +2,7 @@ * Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP * All rights reserved. - * + * * SPDX-License-Identifier: BSD-3-Clause */ @@ -24,10 +24,10 @@ #define L2CACHE_SMALLWAYS_NUM 8U #define L2CACHE_1KBCOVERTOB 1024U #define L2CACHE_SAMLLWAYS_SIZE 16U -#define L2CACHE_LOCKDOWN_REGNUM 8 /*!< Lock down register numbers.*/ -/******************************************************************************* -* Prototypes -******************************************************************************/ +#define L2CACHE_LOCKDOWN_REGNUM 8 /*!< Lock down register numbers.*/ + /******************************************************************************* + * Prototypes + ******************************************************************************/ /*! * @brief Set for all ways and waiting for the operation finished. * This is provided for all the background operations. @@ -166,10 +166,15 @@ static void L2CACHE_GetWayNumSize(uint32_t *num_ways, uint32_t *size_way) *size_way = (1 << (size - 1)) * L2CACHE_SAMLLWAYS_SIZE * L2CACHE_1KBCOVERTOB; } +/*! + * brief Initializes the level 2 cache controller module. + * + * param config Pointer to configuration structure. See "l2cache_config_t". + */ void L2CACHE_Init(l2cache_config_t *config) { - assert (config); - + assert(config); + uint16_t waysNum = 0xFFU; /* Default use the 8-way mask. */ uint8_t count; uint32_t auxReg = 0; @@ -180,7 +185,7 @@ void L2CACHE_Init(l2cache_config_t *config) if (L2CACHEC->REG1_CONTROL & L2CACHEC_REG1_CONTROL_CE_MASK) { L2CACHE_Disable(); - } + } /* Unlock all entries. */ if (L2CACHEC->REG1_AUX_CONTROL & L2CACHEC_REG1_AUX_CONTROL_ASSOCIATIVITY_MASK) @@ -188,20 +193,18 @@ void L2CACHE_Init(l2cache_config_t *config) waysNum = 0xFFFFU; } - for (count = 0; count < L2CACHE_LOCKDOWN_REGNUM; count ++) + for (count = 0; count < L2CACHE_LOCKDOWN_REGNUM; count++) { - L2CACHE_LockdownByWayEnable(count, waysNum, false); + L2CACHE_LockdownByWayEnable(count, waysNum, false); } - + /* Set the ways and way-size etc. */ auxReg = L2CACHEC_REG1_AUX_CONTROL_ASSOCIATIVITY(config->wayNum) | - L2CACHEC_REG1_AUX_CONTROL_WAYSIZE(config->waySize) | - L2CACHEC_REG1_AUX_CONTROL_CRP(config->repacePolicy) | - L2CACHEC_REG1_AUX_CONTROL_IPE(config->istrPrefetchEnable) | - L2CACHEC_REG1_AUX_CONTROL_DPE(config->dataPrefetchEnable) | - L2CACHEC_REG1_AUX_CONTROL_NLE(config->nsLockdownEnable) | - L2CACHEC_REG1_AUX_CONTROL_FWA(config->writeAlloc) | - L2CACHEC_REG1_AUX_CONTROL_HPSDRE(config->writeAlloc); + L2CACHEC_REG1_AUX_CONTROL_WAYSIZE(config->waySize) | L2CACHEC_REG1_AUX_CONTROL_CRP(config->repacePolicy) | + L2CACHEC_REG1_AUX_CONTROL_IPE(config->istrPrefetchEnable) | + L2CACHEC_REG1_AUX_CONTROL_DPE(config->dataPrefetchEnable) | + L2CACHEC_REG1_AUX_CONTROL_NLE(config->nsLockdownEnable) | + L2CACHEC_REG1_AUX_CONTROL_FWA(config->writeAlloc) | L2CACHEC_REG1_AUX_CONTROL_HPSDRE(config->writeAlloc); L2CACHEC->REG1_AUX_CONTROL = auxReg; /* Set the tag/data ram latency. */ @@ -209,23 +212,44 @@ void L2CACHE_Init(l2cache_config_t *config) { uint32_t data = 0; /* Tag latency. */ - data = L2CACHEC_REG1_TAG_RAM_CONTROL_SL(config->lateConfig->tagSetupLate)| - L2CACHEC_REG1_TAG_RAM_CONTROL_SL(config->lateConfig->tagSetupLate)| - L2CACHEC_REG1_TAG_RAM_CONTROL_RAL(config->lateConfig->tagReadLate)| - L2CACHEC_REG1_TAG_RAM_CONTROL_WAL(config->lateConfig->dataWriteLate); + data = L2CACHEC_REG1_TAG_RAM_CONTROL_SL(config->lateConfig->tagSetupLate) | + L2CACHEC_REG1_TAG_RAM_CONTROL_SL(config->lateConfig->tagSetupLate) | + L2CACHEC_REG1_TAG_RAM_CONTROL_RAL(config->lateConfig->tagReadLate) | + L2CACHEC_REG1_TAG_RAM_CONTROL_WAL(config->lateConfig->dataWriteLate); L2CACHEC->REG1_TAG_RAM_CONTROL = data; /* Data latency. */ - data = L2CACHEC_REG1_DATA_RAM_CONTROL_SL(config->lateConfig->dataSetupLate)| - L2CACHEC_REG1_DATA_RAM_CONTROL_SL(config->lateConfig->dataSetupLate)| - L2CACHEC_REG1_DATA_RAM_CONTROL_RAL(config->lateConfig->dataReadLate)| - L2CACHEC_REG1_DATA_RAM_CONTROL_WAL(config->lateConfig->dataWriteLate); + data = L2CACHEC_REG1_DATA_RAM_CONTROL_SL(config->lateConfig->dataSetupLate) | + L2CACHEC_REG1_DATA_RAM_CONTROL_SL(config->lateConfig->dataSetupLate) | + L2CACHEC_REG1_DATA_RAM_CONTROL_RAL(config->lateConfig->dataReadLate) | + L2CACHEC_REG1_DATA_RAM_CONTROL_WAL(config->lateConfig->dataWriteLate); L2CACHEC->REG1_DATA_RAM_CONTROL = data; } } +/*! + * brief Gets an available default settings for the cache controller. + * + * This function initializes the cache controller configuration structure with default settings. + * The default values are: + * code + * config->waysNum = kL2CACHE_8ways; + * config->waySize = kL2CACHE_32KbSize; + * config->repacePolicy = kL2CACHE_Roundrobin; + * config->lateConfig = NULL; + * config->istrPrefetchEnable = false; + * config->dataPrefetchEnable = false; + * config->nsLockdownEnable = false; + * config->writeAlloc = kL2CACHE_UseAwcache; + * endcode + * param config Pointer to the configuration structure. + */ void L2CACHE_GetDefaultConfig(l2cache_config_t *config) { assert(config); + + /* Initializes the configure structure to zero. */ + memset(config, 0, sizeof(*config)); + uint32_t number = (L2CACHEC->REG1_AUX_CONTROL & L2CACHEC_REG1_AUX_CONTROL_ASSOCIATIVITY_MASK) >> L2CACHEC_REG1_AUX_CONTROL_ASSOCIATIVITY_SHIFT; uint32_t size = (L2CACHEC->REG1_AUX_CONTROL & L2CACHEC_REG1_AUX_CONTROL_WAYSIZE_MASK) >> @@ -239,9 +263,15 @@ void L2CACHE_GetDefaultConfig(l2cache_config_t *config) config->istrPrefetchEnable = false; config->dataPrefetchEnable = false; config->nsLockdownEnable = false; - config->writeAlloc = kL2CACHE_UseAwcache; + config->writeAlloc = kL2CACHE_UseAwcache; } +/*! + * brief Enables the level 2 cache controller. + * This function enables the cache controller. Must be written using a secure access. + * If write with a Non-secure access will cause a DECERR response. + * + */ void L2CACHE_Enable(void) { /* Invalidate first. */ @@ -250,6 +280,12 @@ void L2CACHE_Enable(void) L2CACHEC->REG1_CONTROL = L2CACHEC_REG1_CONTROL_CE_MASK; } +/*! + * brief Disables the level 2 cache controller. + * This function disables the cache controller. Must be written using a secure access. + * If write with a Non-secure access will cause a DECERR response. + * + */ void L2CACHE_Disable(void) { /* First CleanInvalidate all enties in the cache. */ @@ -260,6 +296,11 @@ void L2CACHE_Disable(void) __DSB(); } +/*! + * brief Invalidates the Level 2 cache. + * This function invalidates all entries in cache. + * + */ void L2CACHE_Invalidate(void) { /* Invalidate all entries in cache. */ @@ -268,6 +309,11 @@ void L2CACHE_Invalidate(void) L2CACHEC->REG7_CACHE_SYNC = 0; } +/*! + * brief Cleans the level 2 cache controller. + * This function cleans all entries in the level 2 cache controller. + * + */ void L2CACHE_Clean(void) { /* Clean all entries of the cache. */ @@ -276,6 +322,11 @@ void L2CACHE_Clean(void) L2CACHEC->REG7_CACHE_SYNC = 0; } +/*! + * brief Cleans and invalidates the level 2 cache controller. + * This function cleans and invalidates all entries in the level 2 cache controller. + * + */ void L2CACHE_CleanInvalidate(void) { /* Clean all entries of the cache. */ @@ -284,6 +335,17 @@ void L2CACHE_CleanInvalidate(void) L2CACHEC->REG7_CACHE_SYNC = 0; } +/*! + * brief Invalidates the Level 2 cache lines in the range of two physical addresses. + * This function invalidates all cache lines between two physical addresses. + * + * param address The start address of the memory to be invalidated. + * param size_byte The memory size. + * note The start address and size_byte should be 32-byte(FSL_FEATURE_L2CACHE_LINESIZE_BYTE) aligned. + * The startAddr here will be forced to align to L2 line size if startAddr + * is not aligned. For the size_byte, application should make sure the + * alignment or make sure the right operation order if the size_byte is not aligned. + */ void L2CACHE_InvalidateByRange(uint32_t address, uint32_t size_byte) { uint32_t endAddr = address + size_byte; @@ -300,6 +362,17 @@ void L2CACHE_InvalidateByRange(uint32_t address, uint32_t size_byte) L2CACHEC->REG7_CACHE_SYNC = 0; } +/*! + * brief Cleans the Level 2 cache lines in the range of two physical addresses. + * This function cleans all cache lines between two physical addresses. + * + * param address The start address of the memory to be cleaned. + * param size_byte The memory size. + * note The start address and size_byte should be 32-byte(FSL_FEATURE_L2CACHE_LINESIZE_BYTE) aligned. + * The startAddr here will be forced to align to L2 line size if startAddr + * is not aligned. For the size_byte, application should make sure the + * alignment or make sure the right operation order if the size_byte is not aligned. + */ void L2CACHE_CleanByRange(uint32_t address, uint32_t size_byte) { uint32_t num_ways = 0; @@ -327,6 +400,17 @@ void L2CACHE_CleanByRange(uint32_t address, uint32_t size_byte) L2CACHEC->REG7_CACHE_SYNC = 0; } +/*! + * brief Cleans and invalidates the Level 2 cache lines in the range of two physical addresses. + * This function cleans and invalidates all cache lines between two physical addresses. + * + * param address The start address of the memory to be cleaned and invalidated. + * param size_byte The memory size. + * note The start address and size_byte should be 32-byte(FSL_FEATURE_L2CACHE_LINESIZE_BYTE) aligned. + * The startAddr here will be forced to align to L2 line size if startAddr + * is not aligned. For the size_byte, application should make sure the + * alignment or make sure the right operation order if the size_byte is not aligned. + */ void L2CACHE_CleanInvalidateByRange(uint32_t address, uint32_t size_byte) { uint32_t num_ways = 0; @@ -354,6 +438,23 @@ void L2CACHE_CleanInvalidateByRange(uint32_t address, uint32_t size_byte) L2CACHEC->REG7_CACHE_SYNC = 0; } +/*! + * brief Enables or disables to lock down the data and instruction by way. + * This function locks down the cached instruction/data by way and prevent the adresses from + * being allocated and prevent dara from being evicted out of the level 2 cache. + * But the normal cache maintenance operations that invalidate, clean or clean + * and validate cache contents affect the locked-down cache lines as normal. + * + * param masterId The master id, range from 0 ~ 7. + * param mask The ways to be enabled or disabled to lockdown. + * each bit in value is related to each way of the cache. for example: + * value: bit 0 ------ way 0. + * value: bit 1 ------ way 1. + * -------------------------- + * value: bit 15 ------ way 15. + * Note: please make sure the value setting is align with your supported ways. + * param enable True enable the lockdown, false to disable the lockdown. + */ void L2CACHE_LockdownByWayEnable(uint32_t masterId, uint32_t mask, bool enable) { uint8_t num_ways = (L2CACHEC->REG1_AUX_CONTROL & L2CACHEC_REG1_AUX_CONTROL_ASSOCIATIVITY_MASK) >> @@ -381,12 +482,22 @@ void L2CACHE_LockdownByWayEnable(uint32_t masterId, uint32_t mask, bool enable) L2CACHEC->LOCKDOWN[masterId].REG9_I_LOCKDOWN = istrReg & ~mask; } } -#endif /* FSL_FEATURE_SOC_L2CACHEC_COUNT */ +#endif /* FSL_FEATURE_SOC_L2CACHEC_COUNT */ +/*! + * brief Invalidate cortex-m7 L1 instruction cache by range. + * + * param address The start address of the memory to be invalidated. + * param size_byte The memory size. + * note The start address and size_byte should be 32-byte(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE) aligned. + * The startAddr here will be forced to align to L1 I-cache line size if + * startAddr is not aligned. For the size_byte, application should make sure the + * alignment or make sure the right operation order if the size_byte is not aligned. + */ void L1CACHE_InvalidateICacheByRange(uint32_t address, uint32_t size_byte) { #if (__DCACHE_PRESENT == 1U) - uint32_t addr = address & (uint32_t)~(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE - 1); + uint32_t addr = address & (uint32_t) ~(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE - 1); int32_t size = size_byte + address - addr; uint32_t linesize = 32U; @@ -399,9 +510,21 @@ void L1CACHE_InvalidateICacheByRange(uint32_t address, uint32_t size_byte) } __DSB(); __ISB(); -#endif +#endif } +/*! + * brief Invalidates all instruction caches by range. + * + * Both cortex-m7 L1 cache line and L2 PL310 cache line length is 32-byte. + * + * param address The physical address. + * param size_byte size of the memory to be invalidated. + * note address and size should be aligned to cache line size + * 32-Byte due to the cache operation unit is one cache line. The startAddr here will be forced + * to align to the cache line size if startAddr is not aligned. For the size_byte, application should + * make sure the alignment or make sure the right operation order if the size_byte is not aligned. + */ void ICACHE_InvalidateByRange(uint32_t address, uint32_t size_byte) { #if defined(FSL_FEATURE_SOC_L2CACHEC_COUNT) && FSL_FEATURE_SOC_L2CACHEC_COUNT @@ -410,9 +533,21 @@ void ICACHE_InvalidateByRange(uint32_t address, uint32_t size_byte) #endif /* !FSL_SDK_DISBLE_L2CACHE_PRESENT */ #endif /* FSL_FEATURE_SOC_L2CACHEC_COUNT */ - L1CACHE_InvalidateICacheByRange(address, size_byte); + L1CACHE_InvalidateICacheByRange(address, size_byte); } +/*! + * brief Invalidates all data caches by range. + * + * Both cortex-m7 L1 cache line and L2 PL310 cache line length is 32-byte. + * + * param address The physical address. + * param size_byte size of the memory to be invalidated. + * note address and size should be aligned to cache line size + * 32-Byte due to the cache operation unit is one cache line. The startAddr here will be forced + * to align to the cache line size if startAddr is not aligned. For the size_byte, application should + * make sure the alignment or make sure the right operation order if the size_byte is not aligned. + */ void DCACHE_InvalidateByRange(uint32_t address, uint32_t size_byte) { #if defined(FSL_FEATURE_SOC_L2CACHEC_COUNT) && FSL_FEATURE_SOC_L2CACHEC_COUNT @@ -423,6 +558,18 @@ void DCACHE_InvalidateByRange(uint32_t address, uint32_t size_byte) L1CACHE_InvalidateDCacheByRange(address, size_byte); } +/*! + * brief Cleans all data caches by range. + * + * Both cortex-m7 L1 cache line and L2 PL310 cache line length is 32-byte. + * + * param address The physical address. + * param size_byte size of the memory to be cleaned. + * note address and size should be aligned to cache line size + * 32-Byte due to the cache operation unit is one cache line. The startAddr here will be forced + * to align to the cache line size if startAddr is not aligned. For the size_byte, application should + * make sure the alignment or make sure the right operation order if the size_byte is not aligned. + */ void DCACHE_CleanByRange(uint32_t address, uint32_t size_byte) { L1CACHE_CleanDCacheByRange(address, size_byte); @@ -433,6 +580,18 @@ void DCACHE_CleanByRange(uint32_t address, uint32_t size_byte) #endif /* FSL_FEATURE_SOC_L2CACHEC_COUNT */ } +/*! + * brief Cleans and Invalidates all data caches by range. + * + * Both cortex-m7 L1 cache line and L2 PL310 cache line length is 32-byte. + * + * param address The physical address. + * param size_byte size of the memory to be cleaned and invalidated. + * note address and size should be aligned to cache line size + * 32-Byte due to the cache operation unit is one cache line. The startAddr here will be forced + * to align to the cache line size if startAddr is not aligned. For the size_byte, application should + * make sure the alignment or make sure the right operation order if the size_byte is not aligned. + */ void DCACHE_CleanInvalidateByRange(uint32_t address, uint32_t size_byte) { L1CACHE_CleanInvalidateDCacheByRange(address, size_byte); diff --git a/ext/hal/nxp/mcux/drivers/imx/fsl_cmp.c b/ext/hal/nxp/mcux/drivers/imx/fsl_cmp.c index e7c9ee6573f..c4eef9b8af6 100644 --- a/ext/hal/nxp/mcux/drivers/imx/fsl_cmp.c +++ b/ext/hal/nxp/mcux/drivers/imx/fsl_cmp.c @@ -2,7 +2,7 @@ * Copyright (c) 2015, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP * All rights reserved. - * + * * SPDX-License-Identifier: BSD-3-Clause */ @@ -13,7 +13,6 @@ #define FSL_COMPONENT_ID "platform.drivers.cmp" #endif - /******************************************************************************* * Prototypes ******************************************************************************/ @@ -55,6 +54,19 @@ static uint32_t CMP_GetInstance(CMP_Type *base) return instance; } +/*! + * brief Initializes the CMP. + * + * This function initializes the CMP module. The operations included are as follows. + * - Enabling the clock for CMP module. + * - Configuring the comparator. + * - Enabling the CMP module. + * Note that for some devices, multiple CMP instances share the same clock gate. In this case, to enable the clock for + * any instance enables all CMPs. See the appropriate MCU reference manual for the clock assignment of the CMP. + * + * param base CMP peripheral base address. + * param config Pointer to the configuration structure. + */ void CMP_Init(CMP_Type *base, const cmp_config_t *config) { assert(NULL != config); @@ -106,6 +118,19 @@ void CMP_Init(CMP_Type *base, const cmp_config_t *config) CMP_Enable(base, config->enableCmp); /* Enable the CMP module after configured or not. */ } +/*! + * brief De-initializes the CMP module. + * + * This function de-initializes the CMP module. The operations included are as follows. + * - Disabling the CMP module. + * - Disabling the clock for CMP module. + * + * This function disables the clock for the CMP. + * Note that for some devices, multiple CMP instances share the same clock gate. In this case, before disabling the + * clock for the CMP, ensure that all the CMP instances are not used. + * + * param base CMP peripheral base address. + */ void CMP_Deinit(CMP_Type *base) { /* Disable the CMP module. */ @@ -117,10 +142,28 @@ void CMP_Deinit(CMP_Type *base) #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ } +/*! +* brief Initializes the CMP user configuration structure. +* +* This function initializes the user configuration structure to these default values. +* code +* config->enableCmp = true; +* config->hysteresisMode = kCMP_HysteresisLevel0; +* config->enableHighSpeed = false; +* config->enableInvertOutput = false; +* config->useUnfilteredOutput = false; +* config->enablePinOut = false; +* config->enableTriggerMode = false; +* endcode +* param config Pointer to the configuration structure. +*/ void CMP_GetDefaultConfig(cmp_config_t *config) { assert(NULL != config); + /* Initializes the configure structure to zero. */ + memset(config, 0, sizeof(*config)); + config->enableCmp = true; /* Enable the CMP module after initialization. */ config->hysteresisMode = kCMP_HysteresisLevel0; config->enableHighSpeed = false; @@ -132,6 +175,17 @@ void CMP_GetDefaultConfig(cmp_config_t *config) #endif /* FSL_FEATURE_CMP_HAS_TRIGGER_MODE */ } +/*! + * brief Sets the input channels for the comparator. + * + * This function sets the input channels for the comparator. + * Note that two input channels cannot be set the same way in the application. When the user selects the same input + * from the analog mux to the positive and negative port, the comparator is disabled automatically. + * + * param base CMP peripheral base address. + * param positiveChannel Positive side input channel number. Available range is 0-7. + * param negativeChannel Negative side input channel number. Available range is 0-7. + */ void CMP_SetInputChannels(CMP_Type *base, uint8_t positiveChannel, uint8_t negativeChannel) { uint8_t tmp8 = base->MUXCR; @@ -142,6 +196,17 @@ void CMP_SetInputChannels(CMP_Type *base, uint8_t positiveChannel, uint8_t negat } #if defined(FSL_FEATURE_CMP_HAS_DMA) && FSL_FEATURE_CMP_HAS_DMA +/*! + * brief Enables/disables the DMA request for rising/falling events. + * + * This function enables/disables the DMA request for rising/falling events. Either event triggers the generation of + * the DMA request from CMP if the DMA feature is enabled. Both events are ignored for generating the DMA request from + * the CMP + * if the DMA is disabled. + * + * param base CMP peripheral base address. + * param enable Enables or disables the feature. + */ void CMP_EnableDMA(CMP_Type *base, bool enable) { uint8_t tmp8 = base->SCR & ~(CMP_SCR_CFR_MASK | CMP_SCR_CFF_MASK); /* To avoid change the w1c bits. */ @@ -158,6 +223,12 @@ void CMP_EnableDMA(CMP_Type *base, bool enable) } #endif /* FSL_FEATURE_CMP_HAS_DMA */ +/*! + * brief Configures the filter. + * + * param base CMP peripheral base address. + * param config Pointer to the configuration structure. + */ void CMP_SetFilterConfig(CMP_Type *base, const cmp_filter_config_t *config) { assert(NULL != config); @@ -183,6 +254,12 @@ void CMP_SetFilterConfig(CMP_Type *base, const cmp_filter_config_t *config) base->FPR = CMP_FPR_FILT_PER(config->filterPeriod); } +/*! + * brief Configures the internal DAC. + * + * param base CMP peripheral base address. + * param config Pointer to the configuration structure. "NULL" disables the feature. + */ void CMP_SetDACConfig(CMP_Type *base, const cmp_dac_config_t *config) { uint8_t tmp8 = 0U; @@ -204,6 +281,12 @@ void CMP_SetDACConfig(CMP_Type *base, const cmp_dac_config_t *config) base->DACCR = tmp8; } +/*! + * brief Enables the interrupts. + * + * param base CMP peripheral base address. + * param mask Mask value for interrupts. See "_cmp_interrupt_enable". + */ void CMP_EnableInterrupts(CMP_Type *base, uint32_t mask) { uint8_t tmp8 = base->SCR & ~(CMP_SCR_CFR_MASK | CMP_SCR_CFF_MASK); /* To avoid change the w1c bits. */ @@ -219,6 +302,12 @@ void CMP_EnableInterrupts(CMP_Type *base, uint32_t mask) base->SCR = tmp8; } +/*! + * brief Disables the interrupts. + * + * param base CMP peripheral base address. + * param mask Mask value for interrupts. See "_cmp_interrupt_enable". + */ void CMP_DisableInterrupts(CMP_Type *base, uint32_t mask) { uint8_t tmp8 = base->SCR & ~(CMP_SCR_CFR_MASK | CMP_SCR_CFF_MASK); /* To avoid change the w1c bits. */ @@ -234,6 +323,13 @@ void CMP_DisableInterrupts(CMP_Type *base, uint32_t mask) base->SCR = tmp8; } +/*! + * brief Gets the status flags. + * + * param base CMP peripheral base address. + * + * return Mask value for the asserted flags. See "_cmp_status_flags". + */ uint32_t CMP_GetStatusFlags(CMP_Type *base) { uint32_t ret32 = 0U; @@ -253,6 +349,12 @@ uint32_t CMP_GetStatusFlags(CMP_Type *base) return ret32; } +/*! + * brief Clears the status flags. + * + * param base CMP peripheral base address. + * param mask Mask value for the flags. See "_cmp_status_flags". + */ void CMP_ClearStatusFlags(CMP_Type *base, uint32_t mask) { uint8_t tmp8 = base->SCR & ~(CMP_SCR_CFR_MASK | CMP_SCR_CFF_MASK); /* To avoid change the w1c bits. */ diff --git a/ext/hal/nxp/mcux/drivers/imx/fsl_common.c b/ext/hal/nxp/mcux/drivers/imx/fsl_common.c index c5ae4deeb82..39e78bcd9f2 100644 --- a/ext/hal/nxp/mcux/drivers/imx/fsl_common.c +++ b/ext/hal/nxp/mcux/drivers/imx/fsl_common.c @@ -1,6 +1,6 @@ /* * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. - * Copyright 2016 NXP + * Copyright 2016-2018 NXP * All rights reserved. * * @@ -26,7 +26,7 @@ typedef struct _mem_align_control_block uint32_t InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler) { /* Addresses for VECTOR_TABLE and VECTOR_RAM come from the linker file */ -#if defined(__CC_ARM) +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) extern uint32_t Image$$VECTOR_ROM$$Base[]; extern uint32_t Image$$VECTOR_RAM$$Base[]; extern uint32_t Image$$RW_m_data$$Base[]; @@ -43,7 +43,7 @@ uint32_t InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler) extern uint32_t __VECTOR_RAM[]; extern uint32_t __RAM_VECTOR_TABLE_SIZE_BYTES[]; uint32_t __RAM_VECTOR_TABLE_SIZE = (uint32_t)(__RAM_VECTOR_TABLE_SIZE_BYTES); -#endif /* defined(__CC_ARM) */ +#endif /* defined(__CC_ARM) || defined(__ARMCC_VERSION) */ uint32_t n; uint32_t ret; uint32_t irqMaskValue; @@ -77,30 +77,22 @@ uint32_t InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler) #endif /* ENABLE_RAM_VECTOR_TABLE. */ #endif /* __GIC_PRIO_BITS. */ -#ifndef QN908XC_SERIES #if (defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0)) +#if !(defined(FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS) && FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS) void EnableDeepSleepIRQ(IRQn_Type interrupt) { uint32_t intNumber = (uint32_t)interrupt; -#if (defined(FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS) && (FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS == 1)) - { - SYSCON->STARTERP1 = 1u << intNumber; - } -#else - { - uint32_t index = 0; + uint32_t index = 0; - while (intNumber >= 32u) - { - index++; - intNumber -= 32u; - } - - SYSCON->STARTERSET[index] = 1u << intNumber; + while (intNumber >= 32u) + { + index++; + intNumber -= 32u; } -#endif /* FSL_FEATURE_STARTER_DISCONTINUOUS */ + + SYSCON->STARTERSET[index] = 1u << intNumber; EnableIRQ(interrupt); /* also enable interrupt at NVIC */ } @@ -109,28 +101,19 @@ void DisableDeepSleepIRQ(IRQn_Type interrupt) uint32_t intNumber = (uint32_t)interrupt; DisableIRQ(interrupt); /* also disable interrupt at NVIC */ -#if (defined(FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS) && (FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS == 1)) - { - SYSCON->STARTERP1 &= ~(1u << intNumber); - } -#else - { - uint32_t index = 0; + uint32_t index = 0; - while (intNumber >= 32u) - { - index++; - intNumber -= 32u; - } - - SYSCON->STARTERCLR[index] = 1u << intNumber; + while (intNumber >= 32u) + { + index++; + intNumber -= 32u; } -#endif /* FSL_FEATURE_STARTER_DISCONTINUOUS */ + + SYSCON->STARTERCLR[index] = 1u << intNumber; } +#endif /* FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS */ #endif /* FSL_FEATURE_SOC_SYSCON_COUNT */ -#endif /* QN908XC_SERIES */ - void *SDK_Malloc(size_t size, size_t alignbytes) { mem_align_cb_t *p_cb = NULL; diff --git a/ext/hal/nxp/mcux/drivers/imx/fsl_common.h b/ext/hal/nxp/mcux/drivers/imx/fsl_common.h index f3468b412b4..d8a74ce412b 100644 --- a/ext/hal/nxp/mcux/drivers/imx/fsl_common.h +++ b/ext/hal/nxp/mcux/drivers/imx/fsl_common.h @@ -38,8 +38,8 @@ /*! @name Driver version */ /*@{*/ -/*! @brief common driver version 2.0.0. */ -#define FSL_COMMON_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) +/*! @brief common driver version 2.0.1. */ +#define FSL_COMMON_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) /*@}*/ /* Debug console type definition. */ @@ -121,11 +121,34 @@ enum _status_groups kStatusGroup_ICS = 74, /*!< Group number for ICS status codes. */ kStatusGroup_SPDIF = 75, /*!< Group number for SPDIF status codes. */ kStatusGroup_LPC_MINISPI = 76, /*!< Group number for LPC_MINISPI status codes. */ + kStatusGroup_HASHCRYPT = 77, /*!< Group number for Hashcrypt status codes */ + kStatusGroup_LPC_SPI_SSP = 78, /*!< Group number for LPC_SPI_SSP status codes. */ + kStatusGroup_LPC_I2C_1 = 97, /*!< Group number for LPC_I2C_1 status codes. */ kStatusGroup_NOTIFIER = 98, /*!< Group number for NOTIFIER status codes. */ kStatusGroup_DebugConsole = 99, /*!< Group number for debug console status codes. */ kStatusGroup_SEMC = 100, /*!< Group number for SEMC status codes. */ kStatusGroup_ApplicationRangeStart = 101, /*!< Starting number for application groups. */ kStatusGroup_IAP = 102, /*!< Group number for IAP status codes */ + + kStatusGroup_HAL_GPIO = 121, /*!< Group number for HAL GPIO status codes. */ + kStatusGroup_HAL_UART = 122, /*!< Group number for HAL UART status codes. */ + kStatusGroup_HAL_TIMER = 123, /*!< Group number for HAL TIMER status codes. */ + kStatusGroup_HAL_SPI = 124, /*!< Group number for HAL SPI status codes. */ + kStatusGroup_HAL_I2C = 125, /*!< Group number for HAL I2C status codes. */ + kStatusGroup_HAL_FLASH = 126, /*!< Group number for HAL FLASH status codes. */ + kStatusGroup_HAL_PWM = 127, /*!< Group number for HAL PWM status codes. */ + kStatusGroup_HAL_RNG = 128, /*!< Group number for HAL RNG status codes. */ + kStatusGroup_TIMERMANAGER = 135, /*!< Group number for TiMER MANAGER status codes. */ + kStatusGroup_SERIALMANAGER = 136, /*!< Group number for SERIAL MANAGER status codes. */ + kStatusGroup_LED = 137, /*!< Group number for LED status codes. */ + kStatusGroup_BUTTON = 138, /*!< Group number for BUTTON status codes. */ + kStatusGroup_EXTERN_EEPROM = 139, /*!< Group number for EXTERN EEPROM status codes. */ + kStatusGroup_SHELL = 140, /*!< Group number for SHELL status codes. */ + kStatusGroup_MEM_MANAGER = 141, /*!< Group number for MEM MANAGER status codes. */ + kStatusGroup_LIST = 142, /*!< Group number for List status codes. */ + kStatusGroup_OSA = 143, /*!< Group number for OSA status codes. */ + kStatusGroup_COMMON_TASK = 144, /*!< Group number for Common task status codes. */ + kStatusGroup_MSG = 145, /*!< Group number for messaging status codes. */ }; /*! @brief Generic status return codes. */ @@ -224,16 +247,16 @@ _Pragma("diag_suppress=Pm120") #if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE) #define SDK_L2CACHE_ALIGN(var) SDK_PRAGMA(data_alignment = FSL_FEATURE_L2CACHE_LINESIZE_BYTE) var #endif -#elif defined(__ARMCC_VERSION) +#elif defined(__CC_ARM) || defined(__ARMCC_VERSION) /*! Macro to define a variable with alignbytes alignment */ -#define SDK_ALIGN(var, alignbytes) __align(alignbytes) var +#define SDK_ALIGN(var, alignbytes) __attribute__((aligned(alignbytes))) var /*! Macro to define a variable with L1 d-cache line size alignment */ #if defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) -#define SDK_L1DCACHE_ALIGN(var) __align(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) var +#define SDK_L1DCACHE_ALIGN(var) __attribute__((aligned(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE))) var #endif /*! Macro to define a variable with L2 cache line size alignment */ #if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE) -#define SDK_L2CACHE_ALIGN(var) __align(FSL_FEATURE_L2CACHE_LINESIZE_BYTE) var +#define SDK_L2CACHE_ALIGN(var) __attribute__((aligned(FSL_FEATURE_L2CACHE_LINESIZE_BYTE))) var #endif #elif defined(__GNUC__) /*! Macro to define a variable with alignbytes alignment */ @@ -270,7 +293,7 @@ _Pragma("diag_suppress=Pm120") */ /* @{ */ #if (defined(__ICCARM__)) -#if defined(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE) +#if ((!(defined(FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION) && FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION)) && defined(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE)) #define AT_NONCACHEABLE_SECTION(var) var @"NonCacheable" #define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var @"NonCacheable" #define AT_NONCACHEABLE_SECTION_INIT(var) var @"NonCacheable.init" @@ -281,25 +304,25 @@ _Pragma("diag_suppress=Pm120") #define AT_NONCACHEABLE_SECTION_INIT(var) var #define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var #endif -#elif(defined(__ARMCC_VERSION)) -#if defined(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE) +#elif(defined(__CC_ARM) || defined(__ARMCC_VERSION)) +#if ((!(defined(FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION) && FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION)) && defined(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE)) #define AT_NONCACHEABLE_SECTION(var) __attribute__((section("NonCacheable"), zero_init)) var #define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) \ - __attribute__((section("NonCacheable"), zero_init)) __align(alignbytes) var + __attribute__((section("NonCacheable"), zero_init)) __attribute__((aligned(alignbytes))) var #define AT_NONCACHEABLE_SECTION_INIT(var) __attribute__((section("NonCacheable.init"))) var #define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) \ - __attribute__((section("NonCacheable.init"))) __align(alignbytes) var + __attribute__((section("NonCacheable.init"))) __attribute__((aligned(alignbytes))) var #else #define AT_NONCACHEABLE_SECTION(var) var -#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) __align(alignbytes) var +#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) __attribute__((aligned(alignbytes))) var #define AT_NONCACHEABLE_SECTION_INIT(var) var -#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) __align(alignbytes) var +#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) __attribute__((aligned(alignbytes))) var #endif #elif(defined(__GNUC__)) /* For GCC, when the non-cacheable section is required, please define "__STARTUP_INITIALIZE_NONCACHEDATA" * in your projects to make sure the non-cacheable section variables will be initialized in system startup. */ -#if defined(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE) +#if ((!(defined(FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION) && FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION)) && defined(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE)) #define AT_NONCACHEABLE_SECTION_INIT(var) __attribute__((section("NonCacheable.init"))) var #define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) \ __attribute__((section("NonCacheable.init"))) var __attribute__((aligned(alignbytes))) @@ -327,7 +350,7 @@ _Pragma("diag_suppress=Pm120") #if (defined(__ICCARM__)) #define AT_QUICKACCESS_SECTION_CODE(func) func @"CodeQuickAccess" #define AT_QUICKACCESS_SECTION_DATA(func) func @"DataQuickAccess" -#elif(defined(__ARMCC_VERSION)) +#elif(defined(__CC_ARM) || defined(__ARMCC_VERSION)) #define AT_QUICKACCESS_SECTION_CODE(func) __attribute__((section("CodeQuickAccess"))) func #define AT_QUICKACCESS_SECTION_DATA(func) __attribute__((section("DataQuickAccess"))) func #elif(defined(__GNUC__)) @@ -340,7 +363,7 @@ _Pragma("diag_suppress=Pm120") #if (defined(__ICCARM__)) #define AT_QUICKACCESS_SECTION_CODE(func) func #define AT_QUICKACCESS_SECTION_DATA(func) func -#elif(defined(__ARMCC_VERSION)) +#elif(defined(__CC_ARM) || defined(__ARMCC_VERSION)) #define AT_QUICKACCESS_SECTION_CODE(func) func #define AT_QUICKACCESS_SECTION_DATA(func) func #elif(defined(__GNUC__)) @@ -352,6 +375,17 @@ _Pragma("diag_suppress=Pm120") #endif /* __FSL_SDK_DRIVER_QUICK_ACCESS_ENABLE */ /* @} */ +/*! @name Ram Function */ +#if (defined(__ICCARM__)) +#define RAMFUNCTION_SECTION_CODE(func) func @"RamFunction" +#elif(defined(__CC_ARM) || defined(__ARMCC_VERSION)) +#define RAMFUNCTION_SECTION_CODE(func) __attribute__((section("RamFunction"))) func +#elif(defined(__GNUC__)) +#define RAMFUNCTION_SECTION_CODE(func) __attribute__((section("RamFunction"))) func +#else +#error Toolchain not supported. +#endif /* defined(__ICCARM__) */ +/* @} */ /******************************************************************************* * API ******************************************************************************/ @@ -463,7 +497,7 @@ _Pragma("diag_suppress=Pm120") } /*! - * @brief Enaable the global IRQ + * @brief Enable the global IRQ * * Set the primask register with the provided primask value but not just enable the primask. The idea is for the * convenience of integration of RTOS. some RTOS get its own management mechanism of primask. User is required to @@ -491,7 +525,7 @@ _Pragma("diag_suppress=Pm120") */ uint32_t InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler); #endif /* ENABLE_RAM_VECTOR_TABLE. */ - + #if (defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0)) /*! * @brief Enable specific interrupt for wake-up from deep-sleep mode. diff --git a/ext/hal/nxp/mcux/drivers/imx/fsl_csi.c b/ext/hal/nxp/mcux/drivers/imx/fsl_csi.c index e9fb84d2474..7b8c980870b 100644 --- a/ext/hal/nxp/mcux/drivers/imx/fsl_csi.c +++ b/ext/hal/nxp/mcux/drivers/imx/fsl_csi.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017, NXP Semiconductors, Inc. + * Copyright (c) 2017-2018, NXP Semiconductors, Inc. * All rights reserved. * * @@ -7,6 +7,9 @@ */ #include "fsl_csi.h" +#if CSI_DRIVER_FRAG_MODE +#include "fsl_cache.h" +#endif /******************************************************************************* * Definitions @@ -20,9 +23,13 @@ /* Two frame buffer loaded to CSI register at most. */ #define CSI_MAX_ACTIVE_FRAME_NUM 2 +/* CSI driver only support RGB565 and YUV422 in fragment mode, 2 bytes per pixel. */ +#define CSI_FRAG_INPUT_BYTES_PER_PIXEL 2 + /******************************************************************************* * Prototypes ******************************************************************************/ + /*! * @brief Get the instance from the base address * @@ -32,6 +39,7 @@ */ static uint32_t CSI_GetInstance(CSI_Type *base); +#if !CSI_DRIVER_FRAG_MODE /*! * @brief Get the delta value of two index in queue. * @@ -78,6 +86,12 @@ static void CSI_TransferLoadBufferToDevice(CSI_Type *base, csi_handle_t *handle) /* Typedef for interrupt handler. */ typedef void (*csi_isr_t)(CSI_Type *base, csi_handle_t *handle); +#else + +/* Typedef for interrupt handler to work in fragment mode. */ +typedef void (*csi_isr_t)(CSI_Type *base, csi_frag_handle_t *handle); +#endif /* CSI_DRIVER_FRAG_MODE */ + /******************************************************************************* * Variables ******************************************************************************/ @@ -90,7 +104,11 @@ static const clock_ip_name_t s_csiClocks[] = CSI_CLOCKS; #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ /* Array for the CSI driver handle. */ +#if !CSI_DRIVER_FRAG_MODE static csi_handle_t *s_csiHandle[ARRAY_SIZE(s_csiBases)]; +#else +static csi_frag_handle_t *s_csiHandle[ARRAY_SIZE(s_csiBases)]; +#endif /* Array of CSI IRQ number. */ static const IRQn_Type s_csiIRQ[] = CSI_IRQS; @@ -119,6 +137,7 @@ static uint32_t CSI_GetInstance(CSI_Type *base) return instance; } +#if !CSI_DRIVER_FRAG_MODE static uint32_t CSI_TransferGetQueueDelta(uint32_t startIdx, uint32_t endIdx) { if (endIdx >= startIdx) @@ -168,7 +187,19 @@ static void CSI_TransferLoadBufferToDevice(CSI_Type *base, csi_handle_t *handle) /* There are two CSI buffers, so could use XOR to get the next index. */ handle->nextBufferIdx ^= 1U; } +#endif /* CSI_DRIVER_FRAG_MODE */ +/*! + * brief Initialize the CSI. + * + * This function enables the CSI peripheral clock, and resets the CSI registers. + * + * param base CSI peripheral base address. + * param config Pointer to the configuration structure. + * + * retval kStatus_Success Initialize successfully. + * retval kStatus_InvalidArgument Initialize failed because of invalid argument. + */ status_t CSI_Init(CSI_Type *base, const csi_config_t *config) { assert(config); @@ -261,6 +292,13 @@ status_t CSI_Init(CSI_Type *base, const csi_config_t *config) return kStatus_Success; } +/*! + * brief De-initialize the CSI. + * + * This function disables the CSI peripheral clock. + * + * param base CSI peripheral base address. + */ void CSI_Deinit(CSI_Type *base) { /* Disable transfer first. */ @@ -271,6 +309,13 @@ void CSI_Deinit(CSI_Type *base) #endif } +/*! + * brief Reset the CSI. + * + * This function resets the CSI peripheral registers to default status. + * + * param base CSI peripheral base address. + */ void CSI_Reset(CSI_Type *base) { uint32_t csisr; @@ -310,10 +355,31 @@ void CSI_Reset(CSI_Type *base) base->CSIIMAG_PARA = 0U; } +/*! + * brief Get the default configuration for to initialize the CSI. + * + * The default configuration value is: + * + * code + config->width = 320U; + config->height = 240U; + config->polarityFlags = kCSI_HsyncActiveHigh | kCSI_DataLatchOnRisingEdge; + config->bytesPerPixel = 2U; + config->linePitch_Bytes = 320U * 2U; + config->workMode = kCSI_GatedClockMode; + config->dataBus = kCSI_DataBus8Bit; + config->useExtVsync = true; + endcode + * + * param config Pointer to the CSI configuration. + */ void CSI_GetDefaultConfig(csi_config_t *config) { assert(config); + /* Initializes the configure structure to zero. */ + memset(config, 0, sizeof(*config)); + config->width = 320U; config->height = 240U; config->polarityFlags = kCSI_HsyncActiveHigh | kCSI_DataLatchOnRisingEdge; @@ -324,6 +390,13 @@ void CSI_GetDefaultConfig(csi_config_t *config) config->useExtVsync = true; } +/*! + * brief Set the RX frame buffer address. + * + * param base CSI peripheral base address. + * param index Buffer index. + * param addr Frame buffer address to set. + */ void CSI_SetRxBufferAddr(CSI_Type *base, uint8_t index, uint32_t addr) { if (index) @@ -336,6 +409,14 @@ void CSI_SetRxBufferAddr(CSI_Type *base, uint8_t index, uint32_t addr) } } +/*! + * brief Clear the CSI FIFO. + * + * This function clears the CSI FIFO. + * + * param base CSI peripheral base address. + * param fifo The FIFO to clear. + */ void CSI_ClearFifo(CSI_Type *base, csi_fifo_t fifo) { uint32_t cr1; @@ -366,6 +447,19 @@ void CSI_ClearFifo(CSI_Type *base, csi_fifo_t fifo) base->CSICR1 = cr1; } +/*! + * brief Reflash the CSI FIFO DMA. + * + * This function reflashes the CSI FIFO DMA. + * + * For RXFIFO, there are two frame buffers. When the CSI module started, it saves + * the frames to frame buffer 0 then frame buffer 1, the two buffers will be + * written by turns. After reflash DMA using this function, the CSI is reset to + * save frame to buffer 0. + * + * param base CSI peripheral base address. + * param fifo The FIFO DMA to reflash. + */ void CSI_ReflashFifoDma(CSI_Type *base, csi_fifo_t fifo) { uint32_t cr3 = 0U; @@ -388,6 +482,13 @@ void CSI_ReflashFifoDma(CSI_Type *base, csi_fifo_t fifo) } } +/*! + * brief Enable or disable the CSI FIFO DMA request. + * + * param base CSI peripheral base address. + * param fifo The FIFO DMA reques to enable or disable. + * param enable True to enable, false to disable. + */ void CSI_EnableFifoDmaRequest(CSI_Type *base, csi_fifo_t fifo, bool enable) { uint32_t cr3 = 0U; @@ -412,6 +513,12 @@ void CSI_EnableFifoDmaRequest(CSI_Type *base, csi_fifo_t fifo, bool enable) } } +/*! + * brief Enables CSI interrupt requests. + * + * param base CSI peripheral base address. + * param mask The interrupts to enable, pass in as OR'ed value of ref _csi_interrupt_enable. + */ void CSI_EnableInterrupts(CSI_Type *base, uint32_t mask) { base->CSICR1 |= (mask & CSI_CSICR1_INT_EN_MASK); @@ -419,6 +526,12 @@ void CSI_EnableInterrupts(CSI_Type *base, uint32_t mask) base->CSICR18 |= ((mask & CSI_CSICR18_INT_EN_MASK) >> 6U); } +/*! + * brief Disable CSI interrupt requests. + * + * param base CSI peripheral base address. + * param mask The interrupts to disable, pass in as OR'ed value of ref _csi_interrupt_enable. + */ void CSI_DisableInterrupts(CSI_Type *base, uint32_t mask) { base->CSICR1 &= ~(mask & CSI_CSICR1_INT_EN_MASK); @@ -426,6 +539,20 @@ void CSI_DisableInterrupts(CSI_Type *base, uint32_t mask) base->CSICR18 &= ~((mask & CSI_CSICR18_INT_EN_MASK) >> 6U); } +#if !CSI_DRIVER_FRAG_MODE +/*! + * brief Initializes the CSI handle. + * + * This function initializes CSI handle, it should be called before any other + * CSI transactional functions. + * + * param base CSI peripheral base address. + * param handle Pointer to the handle structure. + * param callback Callback function for CSI transfer. + * param userData Callback function parameter. + * + * retval kStatus_Success Handle created successfully. + */ status_t CSI_TransferCreateHandle(CSI_Type *base, csi_handle_t *handle, csi_transfer_callback_t callback, @@ -454,6 +581,20 @@ status_t CSI_TransferCreateHandle(CSI_Type *base, return kStatus_Success; } +/*! + * brief Start the transfer using transactional functions. + * + * When the empty frame buffers have been submit to CSI driver using function + * ref CSI_TransferSubmitEmptyBuffer, user could call this function to start + * the transfer. The incoming frame will be saved to the empty frame buffer, + * and user could be optionally notified through callback function. + * + * param base CSI peripheral base address. + * param handle Pointer to the handle structure. + * + * retval kStatus_Success Started successfully. + * retval kStatus_CSI_NoEmptyBuffer Could not start because no empty frame buffer in queue. + */ status_t CSI_TransferStart(CSI_Type *base, csi_handle_t *handle) { assert(handle); @@ -495,6 +636,18 @@ status_t CSI_TransferStart(CSI_Type *base, csi_handle_t *handle) return kStatus_Success; } +/*! + * brief Stop the transfer using transactional functions. + * + * The driver does not clean the full frame buffers in queue. In other words, after + * calling this function, user still could get the full frame buffers in queue + * using function ref CSI_TransferGetFullBuffer. + * + * param base CSI peripheral base address. + * param handle Pointer to the handle structure. + * + * retval kStatus_Success Stoped successfully. + */ status_t CSI_TransferStop(CSI_Type *base, csi_handle_t *handle) { assert(handle); @@ -512,6 +665,20 @@ status_t CSI_TransferStop(CSI_Type *base, csi_handle_t *handle) return kStatus_Success; } +/*! + * brief Submit empty frame buffer to queue. + * + * This function could be called before ref CSI_TransferStart or after ref + * CSI_TransferStart. If there is no room in queue to store the empty frame + * buffer, this function returns error. + * + * param base CSI peripheral base address. + * param handle Pointer to the handle structure. + * param frameBuffer Empty frame buffer to submit. + * + * retval kStatus_Success Started successfully. + * retval kStatus_CSI_QueueFull Could not submit because there is no room in queue. + */ status_t CSI_TransferSubmitEmptyBuffer(CSI_Type *base, csi_handle_t *handle, uint32_t frameBuffer) { uint32_t csicr1; @@ -554,6 +721,21 @@ status_t CSI_TransferSubmitEmptyBuffer(CSI_Type *base, csi_handle_t *handle, uin return kStatus_Success; } +/*! + * brief Get one full frame buffer from queue. + * + * After the transfer started using function ref CSI_TransferStart, the incoming + * frames will be saved to the empty frame buffers in queue. This function gets + * the full-filled frame buffer from the queue. If there is no full frame buffer + * in queue, this function returns error. + * + * param base CSI peripheral base address. + * param handle Pointer to the handle structure. + * param frameBuffer Full frame buffer. + * + * retval kStatus_Success Started successfully. + * retval kStatus_CSI_NoFullBuffer There is no full frame buffer in queue. + */ status_t CSI_TransferGetFullBuffer(CSI_Type *base, csi_handle_t *handle, uint32_t *frameBuffer) { uint32_t csicr1; @@ -578,6 +760,15 @@ status_t CSI_TransferGetFullBuffer(CSI_Type *base, csi_handle_t *handle, uint32_ return kStatus_Success; } +/*! + * brief CSI IRQ handle function. + * + * This function handles the CSI IRQ request to work with CSI driver transactional + * APIs. + * + * param base CSI peripheral base address. + * param handle CSI handle pointer. + */ void CSI_TransferHandleIRQ(CSI_Type *base, csi_handle_t *handle) { uint32_t queueDrvWriteIdx; @@ -647,6 +838,455 @@ void CSI_TransferHandleIRQ(CSI_Type *base, csi_handle_t *handle) } } +#else /* CSI_DRIVER_FRAG_MODE */ + +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) +__asm void CSI_ExtractYFromYUYV(void *datBase, const void *dmaBase, size_t count) +{ + /* clang-format off */ + push {r4-r7, lr} +10 + LDMIA R1!, {r3-r6} + bfi r7, r3, #0, #8 /* Y0 */ + bfi ip, r5, #0, #8 /* Y4 */ + lsr r3, r3, #16 + lsr r5, r5, #16 + bfi r7, r3, #8, #8 /* Y1 */ + bfi ip, r5, #8, #8 /* Y5 */ + bfi r7, r4, #16, #8 /* Y2 */ + bfi ip, r6, #16, #8 /* Y6 */ + lsr r4, r4, #16 + lsr r6, r6, #16 + bfi r7, r4, #24, #8 /* Y3 */ + bfi ip, r6, #24, #8 /* Y7 */ + STMIA r0!, {r7, ip} + subs r2, #8 + bne %b10 + pop {r4-r7, pc} + /* clang-format on */ +} + +__asm void CSI_ExtractYFromUYVY(void *datBase, const void *dmaBase, size_t count) +{ + /* clang-format off */ + push {r4-r7, lr} +10 + LDMIA R1!, {r3-r6} + lsr r3, r3, #8 + lsr r5, r5, #8 + bfi r7, r3, #0, #8 /* Y0 */ + bfi ip, r5, #0, #8 /* Y4 */ + lsr r3, r3, #16 + lsr r5, r5, #16 + bfi r7, r3, #8, #8 /* Y1 */ + bfi ip, r5, #8, #8 /* Y5 */ + lsr r4, r4, #8 + lsr r6, r6, #8 + bfi r7, r4, #16, #8 /* Y2 */ + bfi ip, r6, #16, #8 /* Y6 */ + lsr r4, r4, #16 + lsr r6, r6, #16 + bfi r7, r4, #24, #8 /* Y3 */ + bfi ip, r6, #24, #8 /* Y7 */ + STMIA r0!, {r7, ip} + subs r2, #8 + bne %b10 + pop {r4-r7, pc} + /* clang-format on */ +} + +#elif(defined(__GNUC__) || defined(__ICCARM__)) +#if defined(__ICCARM__) +#pragma diag_suppress = Pe940 +#endif +__attribute__((naked)) void CSI_ExtractYFromYUYV(void *datBase, const void *dmaBase, size_t count) +{ + /* clang-format off */ + __asm volatile( + " push {r1-r7, r12, lr} \n" + "loop0: \n" + " ldmia r1!, {r3-r6} \n" + " bfi r7, r3, #0, #8 \n" /* Y0 */ + " bfi r12, r5, #0, #8 \n" /* Y4 */ + " lsr r3, r3, #16 \n" + " lsr r5, r5, #16 \n" + " bfi r7, r3, #8, #8 \n" /* Y1 */ + " bfi r12, r5, #8, #8 \n" /* Y5 */ + " bfi r7, r4, #16, #8 \n" /* Y2 */ + " bfi r12, r6, #16, #8 \n" /* Y6 */ + " lsr r4, r4, #16 \n" + " lsr r6, r6, #16 \n" + " bfi r7, r4, #24, #8 \n" /* Y3 */ + " bfi r12, r6, #24, #8 \n" /* Y7 */ + " stmia r0!, {r7, r12} \n" + " subs r2, #8 \n" + " bne loop0 \n" + " pop {r1-r7, r12, pc} \n"); + /* clang-format on */ +} + +__attribute__((naked)) void CSI_ExtractYFromUYVY(void *datBase, const void *dmaBase, size_t count) +{ + /* clang-format off */ + __asm volatile( + " push {r1-r7, r12, lr} \n" + "loop1: \n" + " ldmia r1!, {r3-r6} \n" + " lsr r3, r3, #8 \n" + " lsr r5, r5, #8 \n" + " bfi r7, r3, #0, #8 \n" /* Y0 */ + " bfi r12, r5, #0, #8 \n" /* Y4 */ + " lsr r3, r3, #16 \n" + " lsr r5, r5, #16 \n" + " bfi r7, r3, #8, #8 \n" /* Y1 */ + " bfi r12, r5, #8, #8 \n" /* Y5 */ + " lsr r4, r4, #8 \n" + " lsr r6, r6, #8 \n" + " bfi r7, r4, #16, #8 \n" /* Y2 */ + " bfi r12, r6, #16, #8 \n" /* Y6 */ + " lsr r4, r4, #16 \n" + " lsr r6, r6, #16 \n" + " bfi r7, r4, #24, #8 \n" /* Y3 */ + " bfi r12, r6, #24, #8 \n" /* Y7 */ + " stmia r0!, {r7, r12} \n" + " subs r2, #8 \n" + " bne loop1 \n" + " pop {r1-r7, r12, pc} \n"); + /* clang-format on */ +} +#if defined(__ICCARM__) +#pragma diag_default = Pe940 +#endif +#else +#error Toolchain not supported. +#endif + +static void CSI_MemCopy(void *pDest, const void *pSrc, size_t cnt) +{ + memcpy(pDest, pSrc, cnt); +} + +/*! + * brief Initialize the CSI to work in fragment mode. + * + * This function enables the CSI peripheral clock, and resets the CSI registers. + * + * param base CSI peripheral base address. + */ +void CSI_FragModeInit(CSI_Type *base) +{ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + uint32_t instance = CSI_GetInstance(base); + CLOCK_EnableClock(s_csiClocks[instance]); +#endif + + CSI_Reset(base); +} + +/*! + * brief De-initialize the CSI. + * + * This function disables the CSI peripheral clock. + * + * param base CSI peripheral base address. + */ +void CSI_FragModeDeinit(CSI_Type *base) +{ + CSI_Deinit(base); +} + +/*! + * brief Create handle for CSI work in fragment mode. + * + * param base CSI peripheral base address. + * param handle Pointer to the transactional handle. + * param config Pointer to the configuration structure. + * param callback Callback function for CSI transfer. + * param userData Callback function parameter. + * + * retval kStatus_Success Initialize successfully. + * retval kStatus_InvalidArgument Initialize failed because of invalid argument. + */ +status_t CSI_FragModeCreateHandle(CSI_Type *base, + csi_frag_handle_t *handle, + const csi_frag_config_t *config, + csi_frag_transfer_callback_t callback, + void *userData) +{ + assert(config); + uint32_t reg; + uint32_t instance; + uint32_t imgWidth_Bytes; + + imgWidth_Bytes = config->width * CSI_FRAG_INPUT_BYTES_PER_PIXEL; + + /* The image buffer line width should be multiple of 8-bytes. */ + if ((imgWidth_Bytes & 0x07) != 0) + { + return kStatus_InvalidArgument; + } + + /* Camera frame height must be dividable by DMA buffer line. */ + if (config->height % config->dmaBufferLine != 0) + { + return kStatus_InvalidArgument; + } + + memset(handle, 0, sizeof(*handle)); + handle->callback = callback; + handle->userData = userData; + handle->height = config->height; + handle->width = config->width; + handle->maxLinePerFrag = config->dmaBufferLine; + handle->dmaBytePerLine = config->width * CSI_FRAG_INPUT_BYTES_PER_PIXEL; + handle->isDmaBufferCachable = config->isDmaBufferCachable; + + /* Get instance from peripheral base address. */ + instance = CSI_GetInstance(base); + /* Save the handle in global variables to support the double weak mechanism. */ + s_csiHandle[instance] = handle; + + s_csiIsr = CSI_FragModeTransferHandleIRQ; + + EnableIRQ(s_csiIRQ[instance]); + + /* Configure CSICR1. CSICR1 has been reset to the default value, so could write it directly. */ + reg = ((uint32_t)config->workMode) | config->polarityFlags | CSI_CSICR1_FCC_MASK; + + if (config->useExtVsync) + { + reg |= CSI_CSICR1_EXT_VSYNC_MASK; + } + + base->CSICR1 = reg; + + /* No stride. */ + base->CSIFBUF_PARA = 0; + + /* Enable auto ECC. */ + base->CSICR3 |= CSI_CSICR3_ECC_AUTO_EN_MASK; + + /* + * For better performance. + * The DMA burst size could be set to 16 * 8 byte, 8 * 8 byte, or 4 * 8 byte, + * choose the best burst size based on bytes per line. + */ + if (!(imgWidth_Bytes % (8 * 16))) + { + base->CSICR2 = CSI_CSICR2_DMA_BURST_TYPE_RFF(3U); + base->CSICR3 = (CSI->CSICR3 & ~CSI_CSICR3_RxFF_LEVEL_MASK) | ((2U << CSI_CSICR3_RxFF_LEVEL_SHIFT)); + } + else if (!(imgWidth_Bytes % (8 * 8))) + { + base->CSICR2 = CSI_CSICR2_DMA_BURST_TYPE_RFF(2U); + base->CSICR3 = (CSI->CSICR3 & ~CSI_CSICR3_RxFF_LEVEL_MASK) | ((1U << CSI_CSICR3_RxFF_LEVEL_SHIFT)); + } + else + { + base->CSICR2 = CSI_CSICR2_DMA_BURST_TYPE_RFF(1U); + base->CSICR3 = (CSI->CSICR3 & ~CSI_CSICR3_RxFF_LEVEL_MASK) | ((0U << CSI_CSICR3_RxFF_LEVEL_SHIFT)); + } + + base->CSIDMASA_FB1 = config->dmaBufferAddr0; + base->CSIDMASA_FB2 = config->dmaBufferAddr1; + + if (handle->isDmaBufferCachable) + { + DCACHE_CleanInvalidateByRange(config->dmaBufferAddr0, + config->dmaBufferLine * config->width * CSI_FRAG_INPUT_BYTES_PER_PIXEL); + DCACHE_CleanInvalidateByRange(config->dmaBufferAddr1, + config->dmaBufferLine * config->width * CSI_FRAG_INPUT_BYTES_PER_PIXEL); + } + + return kStatus_Success; +} + +/*! + * brief Start to capture a image. + * + * param base CSI peripheral base address. + * param handle Pointer to the transactional handle. + * param config Pointer to the capture configuration. + * + * retval kStatus_Success Initialize successfully. + * retval kStatus_InvalidArgument Initialize failed because of invalid argument. + */ +status_t CSI_FragModeTransferCaptureImage(CSI_Type *base, + csi_frag_handle_t *handle, + const csi_frag_capture_config_t *config) +{ + assert(config); + + uint16_t windowWidth; + + /* + * If no special window setting, capture full frame. + * If capture window, then capture 1 one each fragment. + */ + if (config->window != NULL) + { + handle->windowULX = config->window->windowULX; + handle->windowULY = config->window->windowULY; + handle->windowLRX = config->window->windowLRX; + handle->windowLRY = config->window->windowLRY; + handle->linePerFrag = 1; + } + else + { + handle->windowULX = 0; + handle->windowULY = 0; + handle->windowLRX = handle->width - 1; + handle->windowLRY = handle->height - 1; + handle->linePerFrag = handle->maxLinePerFrag; + } + + windowWidth = handle->windowLRX - handle->windowULX + 1; + + if (config->outputGrayScale) + { + /* When output format is gray, the window width must be multiple value of 8. */ + if (windowWidth % 8 != 0) + { + return kStatus_InvalidArgument; + } + + handle->datBytePerLine = windowWidth; + if (handle->inputFormat == kCSI_FragInputYUYV) + { + handle->copyFunc = CSI_ExtractYFromYUYV; + } + else + { + handle->copyFunc = CSI_ExtractYFromUYVY; + } + } + else + { + handle->datBytePerLine = windowWidth * CSI_FRAG_INPUT_BYTES_PER_PIXEL; + handle->copyFunc = CSI_MemCopy; + } + + handle->dmaCurLine = 0; + handle->outputBuffer = (uint32_t)config->buffer; + handle->datCurWriteAddr = (uint32_t)config->buffer; + + /* Image parameter. */ + base->CSIIMAG_PARA = + ((uint32_t)(handle->width * CSI_FRAG_INPUT_BYTES_PER_PIXEL) << CSI_CSIIMAG_PARA_IMAGE_WIDTH_SHIFT) | + ((uint32_t)(handle->linePerFrag) << CSI_CSIIMAG_PARA_IMAGE_HEIGHT_SHIFT); + + /* + * Write to memory from first completed frame. + * DMA base addr switch at dma transfer done. + */ + base->CSICR18 = (base->CSICR18 & ~CSI_CSICR18_MASK_OPTION_MASK) | CSI_CSICR18_MASK_OPTION(0); + + CSI_EnableInterrupts(base, kCSI_StartOfFrameInterruptEnable | kCSI_RxBuffer1DmaDoneInterruptEnable | + kCSI_RxBuffer0DmaDoneInterruptEnable); + + return kStatus_Success; +} + +/*! + * brief Abort image capture. + * + * Abort image capture initialized by ref CSI_FragModeTransferCaptureImage. + * + * param base CSI peripheral base address. + * param handle Pointer to the transactional handle. + */ +void CSI_FragModeTransferAbortCaptureImage(CSI_Type *base, csi_frag_handle_t *handle) +{ + CSI_Stop(base); + CSI_DisableInterrupts(base, kCSI_StartOfFrameInterruptEnable | kCSI_RxBuffer1DmaDoneInterruptEnable | + kCSI_RxBuffer0DmaDoneInterruptEnable); +} + +/*! + * brief CSI IRQ handle function. + * + * This function handles the CSI IRQ request to work with CSI driver fragment mode + * APIs. + * + * param base CSI peripheral base address. + * param handle CSI handle pointer. + */ +void CSI_FragModeTransferHandleIRQ(CSI_Type *base, csi_frag_handle_t *handle) +{ + uint32_t csisr = base->CSISR; + uint32_t dmaBufAddr; + uint16_t line; + + /* Clear the error flags. */ + base->CSISR = csisr; + + /* Start of frame, clear the FIFO and start receiving. */ + if (csisr & kCSI_StartOfFrameFlag) + { + /* Reflash the DMA and enable RX DMA request. */ + base->CSICR3 |= (CSI_CSICR3_DMA_REFLASH_RFF_MASK | CSI_CSICR3_DMA_REQ_EN_RFF_MASK); + CSI_Start(base); + handle->dmaCurLine = 0; + handle->datCurWriteAddr = handle->outputBuffer; + } + else if ((csisr & (CSI_CSISR_DMA_TSF_DONE_FB2_MASK | CSI_CSISR_DMA_TSF_DONE_FB1_MASK)) != 0) + { + if ((csisr & CSI_CSISR_DMA_TSF_DONE_FB1_MASK) == CSI_CSISR_DMA_TSF_DONE_FB1_MASK) + { + dmaBufAddr = base->CSIDMASA_FB1; + } + else + { + dmaBufAddr = base->CSIDMASA_FB2; + } + + if (handle->isDmaBufferCachable) + { + DCACHE_InvalidateByRange(dmaBufAddr, handle->dmaBytePerLine * handle->linePerFrag); + } + + /* Copy from DMA buffer to user data buffer. */ + dmaBufAddr += (handle->windowULX * CSI_FRAG_INPUT_BYTES_PER_PIXEL); + + for (line = 0; line < handle->linePerFrag; line++) + { + if (handle->dmaCurLine + line > handle->windowLRY) + { + /* out of window range */ + break; + } + else if (handle->dmaCurLine + line >= handle->windowULY) + { + handle->copyFunc((void *)(handle->datCurWriteAddr), (void const *)dmaBufAddr, handle->datBytePerLine); + handle->datCurWriteAddr += handle->datBytePerLine; + dmaBufAddr += handle->dmaBytePerLine; + } + else + { + } + } + + handle->dmaCurLine += handle->linePerFrag; + + if (handle->dmaCurLine >= handle->height) + { + CSI_Stop(base); + CSI_DisableInterrupts(base, kCSI_StartOfFrameInterruptEnable | kCSI_RxBuffer1DmaDoneInterruptEnable | + kCSI_RxBuffer0DmaDoneInterruptEnable); + + /* Image captured. Stop the CSI. */ + if (handle->callback) + { + handle->callback(base, handle, kStatus_CSI_FrameDone, handle->userData); + } + } + } + else + { + } +} +#endif /* CSI_DRIVER_FRAG_MODE */ + #if defined(CSI) void CSI_DriverIRQHandler(void) { diff --git a/ext/hal/nxp/mcux/drivers/imx/fsl_csi.h b/ext/hal/nxp/mcux/drivers/imx/fsl_csi.h index b9fb3eeb817..eb3eb964bc5 100644 --- a/ext/hal/nxp/mcux/drivers/imx/fsl_csi.h +++ b/ext/hal/nxp/mcux/drivers/imx/fsl_csi.h @@ -1,8 +1,8 @@ /* - * Copyright (c) 2017, NXP Semiconductors, Inc. + * Copyright (c) 2017-2018, NXP Semiconductors, Inc. * All rights reserved. * - * + * * SPDX-License-Identifier: BSD-3-Clause */ @@ -22,7 +22,7 @@ /*! @name Driver version */ /*@{*/ -#define FSL_CSI_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) +#define FSL_CSI_DRIVER_VERSION (MAKE_VERSION(2, 0, 2)) /*@}*/ /*! @brief Size of the frame buffer queue used in CSI transactional function. */ @@ -30,6 +30,11 @@ #define CSI_DRIVER_QUEUE_SIZE 4U #endif +/*! @brief Enable fragment capture function or not. */ +#ifndef CSI_DRIVER_FRAG_MODE +#define CSI_DRIVER_FRAG_MODE 0U +#endif + /* * There is one empty room in queue, used to distinguish whether the queue * is full or empty. When header equals tail, the queue is empty; when header @@ -100,8 +105,8 @@ enum _csi_polarity_flags kCSI_HsyncActiveHigh = CSI_CSICR1_HSYNC_POL_MASK, /*!< HSYNC is active high. */ kCSI_DataLatchOnRisingEdge = CSI_CSICR1_REDGE_MASK, /*!< Pixel data latched at rising edge of pixel clock. */ kCSI_DataLatchOnFallingEdge = 0U, /*!< Pixel data latched at falling edge of pixel clock. */ - kCSI_VsyncActiveHigh = 0U, /*!< VSYNC is active high. */ - kCSI_VsyncActiveLow = CSI_CSICR1_SOF_POL_MASK, /*!< VSYNC is active low. */ + kCSI_VsyncActiveHigh = 0U, /*!< VSYNC is active high. */ + kCSI_VsyncActiveLow = CSI_CSICR1_SOF_POL_MASK, /*!< VSYNC is active low. */ }; /*! @brief Configuration to initialize the CSI module. */ @@ -232,6 +237,99 @@ struct _csi_handle void *userData; /*!< CSI callback function parameter.*/ }; +#if CSI_DRIVER_FRAG_MODE + +/*! @brief Input pixel format when CSI works in fragment mode. */ +typedef enum _csi_frag_input_pixel_format +{ + kCSI_FragInputRGB565 = 0, /*!< Input pixel format is RGB565. */ + kCSI_FragInputYUYV, /*!< Input pixel format is YUV422 (Y-U-Y-V). */ + kCSI_FragInputUYVY, /*!< Input pixel format is YUV422 (U-Y-V-Y). */ +} csi_frag_input_pixel_format_t; + +/*! @brief Configuration for CSI module to work in fragment mode. */ +typedef struct _csi_frag_config +{ + uint16_t width; /*!< Pixels of the input frame. */ + uint16_t height; /*!< Lines of the input frame. */ + uint32_t polarityFlags; /*!< Timing signal polarity flags, OR'ed value of @ref _csi_polarity_flags. */ + csi_work_mode_t workMode; /*!< CSI work mode. */ + csi_data_bus_t dataBus; /*!< Data bus width. */ + bool useExtVsync; /*!< In CCIR656 progressive mode, set true to use external VSYNC signal, set false + to use internal VSYNC signal decoded from SOF. */ + csi_frag_input_pixel_format_t inputFormat; /*!< Input pixel format. */ + + uint32_t dmaBufferAddr0; /*!< Buffer 0 used for CSI DMA, must be double word aligned. */ + uint32_t dmaBufferAddr1; /*!< Buffer 1 used for CSI DMA, must be double word aligned. */ + uint16_t dmaBufferLine; /*!< Lines of each DMA buffer. The size of DMA buffer 0 and + buffer 1 must be the same. Camera frame height must be + dividable by this value. */ + bool isDmaBufferCachable; /*!< Is DMA buffer cachable or not. */ +} csi_frag_config_t; + +/* Forward declaration of the handle typedef. */ +typedef struct _csi_frag_handle csi_frag_handle_t; + +/*! + * @brief CSI fragment transfer callback function. + * + * When a new frame is received and saved to the frame buffer queue, the callback + * is called and the pass the status @ref kStatus_CSI_FrameDone to upper layer. + */ +typedef void (*csi_frag_transfer_callback_t)(CSI_Type *base, + csi_frag_handle_t *handle, + status_t status, + void *userData); + +/*! + * @brief Function to copy data from CSI DMA buffer to user buffer. + */ +typedef void (*csi_frag_copy_func_t)(void *pDest, const void *pSrc, size_t cnt); + +/*! @brief Handle for CSI module to work in fragment mode. */ +struct _csi_frag_handle +{ + uint16_t width; /*!< Pixels of the input frame. */ + uint16_t height; /*!< Lines of the input frame. */ + uint16_t maxLinePerFrag; /*!< Max line saved per fragment. */ + uint16_t linePerFrag; /*!< Actual line saved per fragment. */ + uint16_t dmaBytePerLine; /*!< How many bytes DMA transfered each line. */ + uint16_t datBytePerLine; /*!< How many bytes copied to user buffer each line. */ + uint16_t dmaCurLine; /*!< Current line index in whole frame. */ + uint16_t windowULX; /*!< X of windows upper left corner. */ + uint16_t windowULY; /*!< Y of windows upper left corner. */ + uint16_t windowLRX; /*!< X of windows lower right corner. */ + uint16_t windowLRY; /*!< Y of windows lower right corner. */ + uint32_t outputBuffer; /*!< Address of buffer to save the captured image. */ + uint32_t datCurWriteAddr; /*!< Current write address to the user buffer. */ + csi_frag_input_pixel_format_t inputFormat; /*!< Input pixel format. */ + + csi_frag_transfer_callback_t callback; /*!< Callback function. */ + void *userData; /*!< CSI callback function parameter.*/ + csi_frag_copy_func_t copyFunc; /*!< Function to copy data from CSI DMA buffer to user buffer. */ + bool isDmaBufferCachable; /*!< Is DMA buffer cachable or not. */ +}; + +/*! @brief Handle for CSI module to work in fragment mode. */ +typedef struct _csi_frag_window +{ + uint16_t windowULX; /*!< X of windows upper left corner. */ + uint16_t windowULY; /*!< Y of windows upper left corner. */ + uint16_t windowLRX; /*!< X of windows lower right corner. */ + uint16_t windowLRY; /*!< Y of windows lower right corner. */ +} csi_frag_window_t; + +/*! @brief Handle for CSI module to work in fragment mode. */ +typedef struct _csi_frag_capture_config +{ + bool outputGrayScale; /*!< Output gray scale image or not, could only enable when input format is YUV. */ + uint32_t buffer; /*!< Buffer to save the captured image. */ + csi_frag_window_t *window; /*!< Capture window. Capture full frame if set this to NULL. When output format is gray, + the window width must be multiple value of 8. */ +} csi_frag_capture_config_t; + +#endif /* CSI_DRIVER_FRAG_MODE */ + /******************************************************************************* * API ******************************************************************************/ @@ -429,6 +527,7 @@ static inline void CSI_ClearStatusFlags(CSI_Type *base, uint32_t statusMask) } /* @} */ +#if !CSI_DRIVER_FRAG_MODE /*! * @name Transactional * @{ @@ -527,6 +626,88 @@ status_t CSI_TransferGetFullBuffer(CSI_Type *base, csi_handle_t *handle, uint32_ void CSI_TransferHandleIRQ(CSI_Type *base, csi_handle_t *handle); /* @} */ +#else + +/*! + * @name Fragment mode + * @{ + */ + +/*! + * @brief Initialize the CSI to work in fragment mode. + * + * This function enables the CSI peripheral clock, and resets the CSI registers. + * + * @param base CSI peripheral base address. + */ +void CSI_FragModeInit(CSI_Type *base); + +/*! + * @brief De-initialize the CSI. + * + * This function disables the CSI peripheral clock. + * + * @param base CSI peripheral base address. + */ +void CSI_FragModeDeinit(CSI_Type *base); + +/*! + * @brief Create handle for CSI work in fragment mode. + * + * @param base CSI peripheral base address. + * @param handle Pointer to the transactional handle. + * @param config Pointer to the configuration structure. + * @param callback Callback function for CSI transfer. + * @param userData Callback function parameter. + * + * @retval kStatus_Success Initialize successfully. + * @retval kStatus_InvalidArgument Initialize failed because of invalid argument. + */ +status_t CSI_FragModeCreateHandle(CSI_Type *base, + csi_frag_handle_t *handle, + const csi_frag_config_t *config, + csi_frag_transfer_callback_t callback, + void *userData); + +/*! + * @brief Start to capture a image. + * + * @param base CSI peripheral base address. + * @param handle Pointer to the transactional handle. + * @param config Pointer to the capture configuration. + * + * @retval kStatus_Success Initialize successfully. + * @retval kStatus_InvalidArgument Initialize failed because of invalid argument. + */ +status_t CSI_FragModeTransferCaptureImage(CSI_Type *base, + csi_frag_handle_t *handle, + const csi_frag_capture_config_t *config); + +/*! + * @brief Abort image capture. + * + * Abort image capture initialized by @ref CSI_FragModeTransferCaptureImage. + * + * @param base CSI peripheral base address. + * @param handle Pointer to the transactional handle. + */ +void CSI_FragModeTransferAbortCaptureImage(CSI_Type *base, csi_frag_handle_t *handle); + +/*! + * @brief CSI IRQ handle function. + * + * This function handles the CSI IRQ request to work with CSI driver fragment mode + * APIs. + * + * @param base CSI peripheral base address. + * @param handle CSI handle pointer. + */ +void CSI_FragModeTransferHandleIRQ(CSI_Type *base, csi_frag_handle_t *handle); + +/* @} */ + +#endif /* CSI_DRIVER_FRAG_MODE */ + #if defined(__cplusplus) } #endif diff --git a/ext/hal/nxp/mcux/drivers/imx/fsl_dcdc.c b/ext/hal/nxp/mcux/drivers/imx/fsl_dcdc.c index 39008aed441..272cd482f3e 100644 --- a/ext/hal/nxp/mcux/drivers/imx/fsl_dcdc.c +++ b/ext/hal/nxp/mcux/drivers/imx/fsl_dcdc.c @@ -2,7 +2,7 @@ * Copyright (c) 2017, NXP * All rights reserved. * - * + * * SPDX-License-Identifier: BSD-3-Clause */ @@ -13,7 +13,6 @@ #define FSL_COMPONENT_ID "platform.drivers.dcdc_1" #endif - /******************************************************************************* * Prototypes ******************************************************************************/ @@ -56,6 +55,11 @@ static uint32_t DCDC_GetInstance(DCDC_Type *base) return instance; } +/*! +* brief Enable the access to DCDC registers. +* +* param base DCDC peripheral base address. +*/ void DCDC_Init(DCDC_Type *base) { #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) @@ -64,6 +68,11 @@ void DCDC_Init(DCDC_Type *base) #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ } +/*! +* brief Disable the access to DCDC registers. +* +* param base DCDC peripheral base address. +*/ void DCDC_Deinit(DCDC_Type *base) { #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) @@ -72,6 +81,12 @@ void DCDC_Deinit(DCDC_Type *base) #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ } +/*! +* brief Configure the DCDC clock source. +* +* param base DCDC peripheral base address. +* param clockSource Clock source for DCDC. See to "dcdc_clock_source_t". +*/ void DCDC_SetClockSource(DCDC_Type *base, dcdc_clock_source_t clockSource) { uint32_t tmp32; @@ -99,10 +114,31 @@ void DCDC_SetClockSource(DCDC_Type *base, dcdc_clock_source_t clockSource) base->REG0 = tmp32; } +/*! +* brief Get the default setting for detection configuration. +* +* The default configuration are set according to responding registers' setting when powered on. +* They are: +* code +* config->enableXtalokDetection = false; +* config->powerDownOverVoltageDetection = true; +* config->powerDownLowVlotageDetection = false; +* config->powerDownOverCurrentDetection = true; +* config->powerDownPeakCurrentDetection = true; +* config->powerDownZeroCrossDetection = true; +* config->OverCurrentThreshold = kDCDC_OverCurrentThresholdAlt0; +* config->PeakCurrentThreshold = kDCDC_PeakCurrentThresholdAlt0; +* endcode +* +* param config Pointer to configuration structure. See to "dcdc_detection_config_t" +*/ void DCDC_GetDefaultDetectionConfig(dcdc_detection_config_t *config) { assert(NULL != config); + /* Initializes the configure structure to zero. */ + memset(config, 0, sizeof(*config)); + config->enableXtalokDetection = false; config->powerDownOverVoltageDetection = true; config->powerDownLowVlotageDetection = false; @@ -113,6 +149,12 @@ void DCDC_GetDefaultDetectionConfig(dcdc_detection_config_t *config) config->PeakCurrentThreshold = kDCDC_PeakCurrentThresholdAlt0; } +/*! +* breif Configure the DCDC detection. +* +* param base DCDC peripheral base address. +* param config Pointer to configuration structure. See to "dcdc_detection_config_t" +*/ void DCDC_SetDetectionConfig(DCDC_Type *base, const dcdc_detection_config_t *config) { assert(NULL != config); @@ -153,16 +195,39 @@ void DCDC_SetDetectionConfig(DCDC_Type *base, const dcdc_detection_config_t *con base->REG0 = tmp32; } +/*! +* brief Get the default setting for low power configuration. +* +* The default configuration are set according to responding registers' setting when powered on. +* They are: +* code +* config->enableOverloadDetection = true; +* config->enableAdjustHystereticValue = false; +* config->countChargingTimePeriod = kDCDC_CountChargingTimePeriod8Cycle; +* config->countChargingTimeThreshold = kDCDC_CountChargingTimeThreshold32; +* endcode +* +* param config Pointer to configuration structure. See to "dcdc_low_power_config_t" +*/ void DCDC_GetDefaultLowPowerConfig(dcdc_low_power_config_t *config) { assert(NULL != config); + /* Initializes the configure structure to zero. */ + memset(config, 0, sizeof(*config)); + config->enableOverloadDetection = true; config->enableAdjustHystereticValue = false; config->countChargingTimePeriod = kDCDC_CountChargingTimePeriod8Cycle; config->countChargingTimeThreshold = kDCDC_CountChargingTimeThreshold32; } +/*! +* brief Configure the DCDC low power. +* +* param base DCDC peripheral base address. +* param config Pointer to configuration structure. See to "dcdc_low_power_config_t". +*/ void DCDC_SetLowPowerConfig(DCDC_Type *base, const dcdc_low_power_config_t *config) { assert(NULL != config); @@ -185,6 +250,12 @@ void DCDC_SetLowPowerConfig(DCDC_Type *base, const dcdc_low_power_config_t *conf base->REG0 = tmp32; } +/*! +* brief Get DCDC status flags. +* +* param base peripheral base address. +* return Mask of asserted status flags. See to "_dcdc_status_flags_t". +*/ uint32_t DCDC_GetstatusFlags(DCDC_Type *base) { uint32_t tmp32 = 0U; @@ -197,6 +268,12 @@ uint32_t DCDC_GetstatusFlags(DCDC_Type *base) return tmp32; } +/*! +* brief Reset current alert signal. Alert signal is generate by peak current detection. +* +* param base DCDC peripheral base address. +* param enable Switcher to reset signal. True means reset signal. False means don't reset signal. +*/ void DCDC_ResetCurrentAlertSignal(DCDC_Type *base, bool enable) { if (enable) @@ -209,10 +286,31 @@ void DCDC_ResetCurrentAlertSignal(DCDC_Type *base, bool enable) } } +/*! +* brief Get the default setting for loop control configuration. +* +* The default configuration are set according to responding registers' setting when powered on. +* They are: +* code +* config->enableCommonHysteresis = false; +* config->enableCommonThresholdDetection = false; +* config->enableInvertHysteresisSign = false; +* config->enableRCThresholdDetection = false; +* config->enableRCScaleCircuit = 0U; +* config->complementFeedForwardStep = 0U; +* config->controlParameterMagnitude = 2U; +* config->integralProportionalRatio = 2U; +* endcode +* +* param config Pointer to configuration structure. See to "dcdc_loop_control_config_t" +*/ void DCDC_GetDefaultLoopControlConfig(dcdc_loop_control_config_t *config) { assert(NULL != config); + /* Initializes the configure structure to zero. */ + memset(config, 0, sizeof(*config)); + config->enableCommonHysteresis = false; config->enableCommonThresholdDetection = false; config->enableInvertHysteresisSign = false; @@ -223,6 +321,12 @@ void DCDC_GetDefaultLoopControlConfig(dcdc_loop_control_config_t *config) config->integralProportionalRatio = 2U; } +/*! +* brief Configure the DCDC loop control. +* +* param base DCDC peripheral base address. +* param config Pointer to configuration structure. See to "dcdc_loop_control_config_t". +*/ void DCDC_SetLoopControlConfig(DCDC_Type *base, const dcdc_loop_control_config_t *config) { assert(NULL != config); @@ -261,6 +365,12 @@ void DCDC_SetLoopControlConfig(DCDC_Type *base, const dcdc_loop_control_config_t base->REG2 = tmp32; } +/*! + * brief Configure for the min power. + * + * param base DCDC peripheral base address. + * param config Pointer to configuration structure. See to "dcdc_min_power_config_t". + */ void DCDC_SetMinPowerConfig(DCDC_Type *base, const dcdc_min_power_config_t *config) { assert(NULL != config); @@ -275,6 +385,18 @@ void DCDC_SetMinPowerConfig(DCDC_Type *base, const dcdc_min_power_config_t *conf base->REG3 = tmp32; } +/*! +* brief Adjust the target voltage of VDD_SOC in run mode and low power mode. +* +* This function is to adjust the target voltage of DCDC output. Change them and finally wait until the output is +* stabled. +* Set the target value of run mode the same as low power mode before entering power save mode, because DCDC will switch +* back to run mode if it detects the current loading is larger than about 50 mA(typical value). +* +* param base DCDC peripheral base address. +* param VDDRun Target value in run mode. 25 mV each step from 0x00 to 0x1F. 00 is for 0.8V, 0x1F is for 1.575V. +* param VDDStandby Target value in low power mode. 25 mV each step from 0x00 to 0x4. 00 is for 0.9V, 0x4 is for 1.0V. +*/ void DCDC_AdjustTargetVoltage(DCDC_Type *base, uint32_t VDDRun, uint32_t VDDStandby) { uint32_t tmp32; @@ -295,6 +417,12 @@ void DCDC_AdjustTargetVoltage(DCDC_Type *base, uint32_t VDDRun, uint32_t VDDStan } } +/*! +* brief Configure the DCDC internal regulator. +* +* param base DCDC peripheral base address. +* param config Pointer to configuration structure. See to "dcdc_internal_regulator_config_t". +*/ void DCDC_SetInternalRegulatorConfig(DCDC_Type *base, const dcdc_internal_regulator_config_t *config) { assert(NULL != config); @@ -311,6 +439,16 @@ void DCDC_SetInternalRegulatorConfig(DCDC_Type *base, const dcdc_internal_regula base->REG1 = tmp32; } +/*! +* brief Boot DCDC into DCM(discontinous conduction mode). +* +* pwd_zcd=0x0; +* pwd_cmp_offset=0x0; +* dcdc_loopctrl_en_rcscale=0x3 or 0x5; +* DCM_set_ctrl=1'b1; +* +* param base DCDC peripheral base address. +*/ void DCDC_BootIntoDCM(DCDC_Type *base) { base->REG0 &= ~(DCDC_REG0_PWD_ZCD_MASK | DCDC_REG0_PWD_CMP_OFFSET_MASK); @@ -318,6 +456,15 @@ void DCDC_BootIntoDCM(DCDC_Type *base) DCDC_REG2_DCM_SET_CTRL_MASK; } +/*! +* brief Boot DCDC into CCM(continous conduction mode). +* +* pwd_zcd=0x1; +* pwd_cmp_offset=0x0; +* dcdc_loopctrl_en_rcscale=0x3; +* +* param base DCDC peripheral base address. +*/ void DCDC_BootIntoCCM(DCDC_Type *base) { base->REG0 = (~DCDC_REG0_PWD_CMP_OFFSET_MASK & base->REG0) | DCDC_REG0_PWD_ZCD_MASK; diff --git a/ext/hal/nxp/mcux/drivers/imx/fsl_dcp.c b/ext/hal/nxp/mcux/drivers/imx/fsl_dcp.c index c9ef8531dc1..67fba7fbd2a 100644 --- a/ext/hal/nxp/mcux/drivers/imx/fsl_dcp.c +++ b/ext/hal/nxp/mcux/drivers/imx/fsl_dcp.c @@ -2,7 +2,7 @@ * Copyright 2017 NXP * All rights reserved. * - * + * * SPDX-License-Identifier: BSD-3-Clause */ @@ -17,7 +17,6 @@ #define FSL_COMPONENT_ID "platform.drivers.dcp" #endif - /*! Compile time sizeof() check */ #define BUILD_ASSURE(condition, msg) extern int msg[1 - 2 * (!(condition))] __attribute__((unused)) @@ -260,6 +259,24 @@ static status_t dcp_schedule_work(DCP_Type *base, dcp_handle_t *handle, dcp_work return status; } +/*! + * brief Set AES key to dcp_handle_t struct and optionally to DCP. + * + * Sets the AES key for encryption/decryption with the dcp_handle_t structure. + * The dcp_handle_t input argument specifies keySlot. + * If the keySlot is kDCP_OtpKey, the function will check the OTP_KEY_READY bit and will return it's ready to use + * status. + * For other keySlot selections, the function will copy and hold the key in dcp_handle_t struct. + * If the keySlot is one of the four DCP SRAM-based keys (one of kDCP_KeySlot0, kDCP_KeySlot1, kDCP_KeySlot2, + * kDCP_KeySlot3), + * this function will also load the supplied key to the specified keySlot in DCP. + * + * param base DCP peripheral base address. + * param handle Handle used for the request. + * param key 0-mod-4 aligned pointer to AES key. + * param keySize AES key size in bytes. Shall equal 16. + * return status from set key operation + */ status_t DCP_AES_SetKey(DCP_Type *base, dcp_handle_t *handle, const uint8_t *key, size_t keySize) { status_t status = kStatus_Fail; @@ -310,6 +327,19 @@ status_t DCP_AES_SetKey(DCP_Type *base, dcp_handle_t *handle, const uint8_t *key return status; } +/*! + * brief Encrypts AES on one or multiple 128-bit block(s). + * + * Encrypts AES. + * The source plaintext and destination ciphertext can overlap in system memory. + * + * param base DCP peripheral base address + * param handle Handle used for this request. + * param plaintext Input plain text to encrypt + * param[out] ciphertext Output cipher text + * param size Size of input and output data in bytes. Must be multiple of 16 bytes. + * return Status from encrypt operation + */ status_t DCP_AES_EncryptEcb( DCP_Type *base, dcp_handle_t *handle, const uint8_t *plaintext, uint8_t *ciphertext, size_t size) { @@ -329,6 +359,20 @@ status_t DCP_AES_EncryptEcb( return DCP_WaitForChannelComplete(base, handle); } +/*! +* brief Encrypts AES using the ECB block mode. +* +* Puts AES ECB encrypt work packet to DCP channel. +* +* param base DCP peripheral base address +* param handle Handle used for this request. +* param[out] dcpPacket Memory for the DCP work packet. +* param plaintext Input plain text to encrypt. +* param[out] ciphertext Output cipher text +* param size Size of input and output data in bytes. Must be multiple of 16 bytes. +* return kStatus_Success The work packet has been scheduled at DCP channel. +* return kStatus_DCP_Again The DCP channel is busy processing previous request. +*/ status_t DCP_AES_EncryptEcbNonBlocking(DCP_Type *base, dcp_handle_t *handle, dcp_work_packet_t *dcpPacket, @@ -342,7 +386,8 @@ status_t DCP_AES_EncryptEcbNonBlocking(DCP_Type *base, return kStatus_InvalidArgument; } - dcpPacket->control0 = 0x122u | (handle->swapConfig & 0xFC0000u); /* CIPHER_ENCRYPT | ENABLE_CIPHER | DECR_SEMAPHORE */ + dcpPacket->control0 = + 0x122u | (handle->swapConfig & 0xFC0000u); /* CIPHER_ENCRYPT | ENABLE_CIPHER | DECR_SEMAPHORE */ dcpPacket->sourceBufferAddress = (uint32_t)plaintext; dcpPacket->destinationBufferAddress = (uint32_t)ciphertext; dcpPacket->bufferSize = (uint32_t)size; @@ -371,6 +416,19 @@ status_t DCP_AES_EncryptEcbNonBlocking(DCP_Type *base, return dcp_schedule_work(base, handle, dcpPacket); } +/*! + * brief Decrypts AES on one or multiple 128-bit block(s). + * + * Decrypts AES. + * The source ciphertext and destination plaintext can overlap in system memory. + * + * param base DCP peripheral base address + * param handle Handle used for this request. + * param ciphertext Input plain text to encrypt + * param[out] plaintext Output cipher text + * param size Size of input and output data in bytes. Must be multiple of 16 bytes. + * return Status from decrypt operation + */ status_t DCP_AES_DecryptEcb( DCP_Type *base, dcp_handle_t *handle, const uint8_t *ciphertext, uint8_t *plaintext, size_t size) { @@ -390,6 +448,20 @@ status_t DCP_AES_DecryptEcb( return DCP_WaitForChannelComplete(base, handle); } +/*! + * brief Decrypts AES using ECB block mode. + * + * Puts AES ECB decrypt dcpPacket to DCP input job ring. + * + * param base DCP peripheral base address + * param handle Handle used for this request. + * param[out] dcpPacket Memory for the DCP work packet. + * param ciphertext Input cipher text to decrypt + * param[out] plaintext Output plain text + * param size Size of input and output data in bytes. Must be multiple of 16 bytes. + * return kStatus_Success The work packet has been scheduled at DCP channel. + * return kStatus_DCP_Again The DCP channel is busy processing previous request. + */ status_t DCP_AES_DecryptEcbNonBlocking(DCP_Type *base, dcp_handle_t *handle, dcp_work_packet_t *dcpPacket, @@ -432,6 +504,20 @@ status_t DCP_AES_DecryptEcbNonBlocking(DCP_Type *base, return dcp_schedule_work(base, handle, dcpPacket); } +/*! + * brief Encrypts AES using CBC block mode. + * + * Encrypts AES using CBC block mode. + * The source plaintext and destination ciphertext can overlap in system memory. + * + * param base DCP peripheral base address + * param handle Handle used for this request. + * param plaintext Input plain text to encrypt + * param[out] ciphertext Output cipher text + * param size Size of input and output data in bytes. Must be multiple of 16 bytes. + * param iv Input initial vector to combine with the first input block. + * return Status from encrypt operation + */ status_t DCP_AES_EncryptCbc(DCP_Type *base, dcp_handle_t *handle, const uint8_t *plaintext, @@ -455,6 +541,21 @@ status_t DCP_AES_EncryptCbc(DCP_Type *base, return DCP_WaitForChannelComplete(base, handle); } +/*! + * brief Encrypts AES using CBC block mode. + * + * Puts AES CBC encrypt dcpPacket to DCP input job ring. + * + * param base DCP peripheral base address + * param handle Handle used for this request. Specifies jobRing. + * param[out] dcpPacket Memory for the DCP work packet. + * param plaintext Input plain text to encrypt + * param[out] ciphertext Output cipher text + * param size Size of input and output data in bytes. Must be multiple of 16 bytes. + * param iv Input initial vector to combine with the first input block. + * return kStatus_Success The work packet has been scheduled at DCP channel. + * return kStatus_DCP_Again The DCP channel is busy processing previous request. + */ status_t DCP_AES_EncryptCbcNonBlocking(DCP_Type *base, dcp_handle_t *handle, dcp_work_packet_t *dcpPacket, @@ -469,8 +570,9 @@ status_t DCP_AES_EncryptCbcNonBlocking(DCP_Type *base, return kStatus_InvalidArgument; } - dcpPacket->control0 = 0x322u | (handle->swapConfig & 0xFC0000u); /* CIPHER_INIT | CIPHER_ENCRYPT | ENABLE_CIPHER | DECR_SEMAPHORE */ - dcpPacket->control1 = 0x10u; /* CBC */ + dcpPacket->control0 = + 0x322u | (handle->swapConfig & 0xFC0000u); /* CIPHER_INIT | CIPHER_ENCRYPT | ENABLE_CIPHER | DECR_SEMAPHORE */ + dcpPacket->control1 = 0x10u; /* CBC */ dcpPacket->sourceBufferAddress = (uint32_t)plaintext; dcpPacket->destinationBufferAddress = (uint32_t)ciphertext; dcpPacket->bufferSize = (uint32_t)size; @@ -504,6 +606,20 @@ status_t DCP_AES_EncryptCbcNonBlocking(DCP_Type *base, return dcp_schedule_work(base, handle, dcpPacket); } +/*! + * brief Decrypts AES using CBC block mode. + * + * Decrypts AES using CBC block mode. + * The source ciphertext and destination plaintext can overlap in system memory. + * + * param base DCP peripheral base address + * param handle Handle used for this request. + * param ciphertext Input cipher text to decrypt + * param[out] plaintext Output plain text + * param size Size of input and output data in bytes. Must be multiple of 16 bytes. + * param iv Input initial vector to combine with the first input block. + * return Status from decrypt operation + */ status_t DCP_AES_DecryptCbc(DCP_Type *base, dcp_handle_t *handle, const uint8_t *ciphertext, @@ -527,6 +643,21 @@ status_t DCP_AES_DecryptCbc(DCP_Type *base, return DCP_WaitForChannelComplete(base, handle); } +/*! + * brief Decrypts AES using CBC block mode. + * + * Puts AES CBC decrypt dcpPacket to DCP input job ring. + * + * param base DCP peripheral base address + * param handle Handle used for this request. Specifies jobRing. + * param[out] dcpPacket Memory for the DCP work packet. + * param ciphertext Input cipher text to decrypt + * param[out] plaintext Output plain text + * param size Size of input and output data in bytes. Must be multiple of 16 bytes. + * param iv Input initial vector to combine with the first input block. + * return kStatus_Success The work packet has been scheduled at DCP channel. + * return kStatus_DCP_Again The DCP channel is busy processing previous request. + */ status_t DCP_AES_DecryptCbcNonBlocking(DCP_Type *base, dcp_handle_t *handle, dcp_work_packet_t *dcpPacket, @@ -542,7 +673,7 @@ status_t DCP_AES_DecryptCbcNonBlocking(DCP_Type *base, } dcpPacket->control0 = 0x222u | (handle->swapConfig & 0xFC0000u); /* CIPHER_INIT | ENABLE_CIPHER | DECR_SEMAPHORE */ - dcpPacket->control1 = 0x10u; /* CBC */ + dcpPacket->control1 = 0x10u; /* CBC */ dcpPacket->sourceBufferAddress = (uint32_t)ciphertext; dcpPacket->destinationBufferAddress = (uint32_t)plaintext; dcpPacket->bufferSize = (uint32_t)size; @@ -576,12 +707,29 @@ status_t DCP_AES_DecryptCbcNonBlocking(DCP_Type *base, return dcp_schedule_work(base, handle, dcpPacket); } +/*! + * brief Gets the default configuration structure. + * + * This function initializes the DCP configuration structure to a default value. The default + * values are as follows. + * dcpConfig->gatherResidualWrites = true; + * dcpConfig->enableContextCaching = true; + * dcpConfig->enableContextSwitching = true; + * dcpConfig->enableChannnel = kDCP_chEnableAll; + * dcpConfig->enableChannelInterrupt = kDCP_chIntDisable; + * + * param[out] config Pointer to configuration structure. + */ void DCP_GetDefaultConfig(dcp_config_t *config) { /* ENABLE_CONTEXT_CACHING is disabled by default as the DCP Hash driver uses * dcp_hash_save_running_hash() and dcp_hash_restore_running_hash() to support * Hash context switch (different messages interleaved) on the same channel. */ + + /* Initializes the configure structure to zero. */ + memset(config, 0, sizeof(*config)); + dcp_config_t userConfig = { true, false, true, kDCP_chEnableAll, kDCP_chIntDisable, }; @@ -589,6 +737,14 @@ void DCP_GetDefaultConfig(dcp_config_t *config) *config = userConfig; } +/*! + * brief Enables clock to and enables DCP + * + * Enable DCP clock and configure DCP. + * + * param base DCP base address + * param config Pointer to configuration structure. + */ void DCP_Init(DCP_Type *base, const dcp_config_t *config) { #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) @@ -613,6 +769,13 @@ void DCP_Init(DCP_Type *base, const dcp_config_t *config) base->CONTEXT = (uint32_t)&s_dcpContextSwitchingBuffer; } +/*! + * brief Disable DCP clock + * + * Reset DCP and Disable DCP clock. + * + * param base DCP base address + */ void DCP_Deinit(DCP_Type *base) { base->CTRL = 0xF0800000u; /* reset value */ @@ -623,6 +786,16 @@ void DCP_Deinit(DCP_Type *base) #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ } +/*! + * brief Poll and wait on DCP channel. + * + * Polls the specified DCP channel until current it completes activity. + * + * param base DCP peripheral base address. + * param handle Specifies DCP channel. + * return kStatus_Success When data processing completes without error. + * return kStatus_Fail When error occurs. + */ status_t DCP_WaitForChannelComplete(DCP_Type *base, dcp_handle_t *handle) { /* wait if our channel is still active */ @@ -728,7 +901,8 @@ static status_t dcp_hash_engine_init(DCP_Type *base, dcp_hash_ctx_internal_t *ct static status_t dcp_hash_update_non_blocking( DCP_Type *base, dcp_hash_ctx_internal_t *ctxInternal, dcp_work_packet_t *dcpPacket, const uint8_t *msg, size_t size) { - dcpPacket->control0 = ctxInternal->ctrl0 | (ctxInternal->handle->swapConfig & 0xFC0000u) | kDCP_CONTROL0_ENABLE_HASH | kDCP_CONTROL0_DECR_SEMAPHOR; + dcpPacket->control0 = ctxInternal->ctrl0 | (ctxInternal->handle->swapConfig & 0xFC0000u) | + kDCP_CONTROL0_ENABLE_HASH | kDCP_CONTROL0_DECR_SEMAPHOR; if (ctxInternal->algo == kDCP_Sha256) { dcpPacket->control1 = kDCP_CONTROL1_HASH_SELECT_SHA256; @@ -906,6 +1080,17 @@ static void dcp_hash_restore_running_hash(dcp_hash_ctx_internal_t *ctxInternal) } } +/*! + * brief Initialize HASH context + * + * This function initializes the HASH. + * + * param base DCP peripheral base address + * param handle Specifies the DCP channel used for hashing. + * param[out] ctx Output hash context + * param algo Underlaying algorithm to use for hash computation. + * return Status of initialization + */ status_t DCP_HASH_Init(DCP_Type *base, dcp_handle_t *handle, dcp_hash_ctx_t *ctx, dcp_hash_algo_t algo) { status_t status; @@ -935,6 +1120,21 @@ status_t DCP_HASH_Init(DCP_Type *base, dcp_handle_t *handle, dcp_hash_ctx_t *ctx return status; } +/*! + * brief Add data to current HASH + * + * Add data to current HASH. This can be called repeatedly with an arbitrary amount of data to be + * hashed. The functions blocks. If it returns kStatus_Success, the running hash + * has been updated (DCP has processed the input data), so the memory at ref input pointer + * can be released back to system. The DCP context buffer is updated with the running hash + * and with all necessary information to support possible context switch. + * + * param base DCP peripheral base address + * param[in,out] ctx HASH context + * param input Input data + * param inputSize Size of input data in bytes + * return Status of the hash update operation + */ status_t DCP_HASH_Update(DCP_Type *base, dcp_hash_ctx_t *ctx, const uint8_t *input, size_t inputSize) { bool isUpdateState; @@ -988,6 +1188,17 @@ status_t DCP_HASH_Update(DCP_Type *base, dcp_hash_ctx_t *ctx, const uint8_t *inp return status; } +/*! + * brief Finalize hashing + * + * Outputs the final hash (computed by DCP_HASH_Update()) and erases the context. + * + * param[in,out] ctx Input hash context + * param[out] output Output hash data + * param[in,out] outputSize Optional parameter (can be passed as NULL). On function entry, it specifies the size of + * output[] buffer. On function return, it stores the number of updated output bytes. + * return Status of the hash finish operation + */ status_t DCP_HASH_Finish(DCP_Type *base, dcp_hash_ctx_t *ctx, uint8_t *output, size_t *outputSize) { size_t algOutSize = 0; @@ -1074,6 +1285,20 @@ status_t DCP_HASH_Finish(DCP_Type *base, dcp_hash_ctx_t *ctx, uint8_t *output, s return status; } +/*! + * brief Create HASH on given data + * + * Perform the full SHA or CRC32 in one function call. The function is blocking. + * + * param base DCP peripheral base address + * param handle Handle used for the request. + * param algo Underlaying algorithm to use for hash computation. + * param input Input data + * param inputSize Size of input data in bytes + * param[out] output Output hash data + * param[out] outputSize Output parameter storing the size of the output hash in bytes + * return Status of the one call hash operation. + */ status_t DCP_HASH(DCP_Type *base, dcp_handle_t *handle, dcp_hash_algo_t algo, diff --git a/ext/hal/nxp/mcux/drivers/imx/fsl_dcp.h b/ext/hal/nxp/mcux/drivers/imx/fsl_dcp.h index 5d0dc2bc8b1..cadfe8c76cb 100644 --- a/ext/hal/nxp/mcux/drivers/imx/fsl_dcp.h +++ b/ext/hal/nxp/mcux/drivers/imx/fsl_dcp.h @@ -27,15 +27,18 @@ enum _dcp_status */ /*! @name Driver version */ /*@{*/ -/*! @brief DCP driver version. Version 2.0.0. +/*! @brief DCP driver version. Version 2.1.0. * - * Current version: 2.0.0 + * Current version: 2.1.0 * * Change log: + * - Version 2.1.0 + * - Add byte/word swap feature for key, input and output data + * * - Version 2.0.0 * - Initial version */ -#define FSL_DCP_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) +#define FSL_DCP_DRIVER_VERSION (MAKE_VERSION(2, 1, 0)) /*@}*/ /*! @brief DCP channel enable. diff --git a/ext/hal/nxp/mcux/drivers/imx/fsl_dmamux.c b/ext/hal/nxp/mcux/drivers/imx/fsl_dmamux.c index 411c4b64a6b..8bfbe6c3676 100644 --- a/ext/hal/nxp/mcux/drivers/imx/fsl_dmamux.c +++ b/ext/hal/nxp/mcux/drivers/imx/fsl_dmamux.c @@ -2,7 +2,7 @@ * Copyright (c) 2015, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP * All rights reserved. - * + * * SPDX-License-Identifier: BSD-3-Clause */ @@ -17,7 +17,6 @@ #define FSL_COMPONENT_ID "platform.drivers.dmamux" #endif - /******************************************************************************* * Prototypes ******************************************************************************/ @@ -62,6 +61,14 @@ static uint32_t DMAMUX_GetInstance(DMAMUX_Type *base) return instance; } +/*! + * brief Initializes the DMAMUX peripheral. + * + * This function ungates the DMAMUX clock. + * + * param base DMAMUX peripheral base address. + * + */ void DMAMUX_Init(DMAMUX_Type *base) { #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) @@ -69,6 +76,13 @@ void DMAMUX_Init(DMAMUX_Type *base) #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ } +/*! + * brief Deinitializes the DMAMUX peripheral. + * + * This function gates the DMAMUX clock. + * + * param base DMAMUX peripheral base address. + */ void DMAMUX_Deinit(DMAMUX_Type *base) { #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) diff --git a/ext/hal/nxp/mcux/drivers/imx/fsl_edma.c b/ext/hal/nxp/mcux/drivers/imx/fsl_edma.c index 77ae12d43db..cd4b56b5e9b 100644 --- a/ext/hal/nxp/mcux/drivers/imx/fsl_edma.c +++ b/ext/hal/nxp/mcux/drivers/imx/fsl_edma.c @@ -1,6 +1,6 @@ /* * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP + * Copyright 2016-2018 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -70,6 +70,13 @@ static uint32_t EDMA_GetInstance(DMA_Type *base) return instance; } +/*! + * brief Push content of TCD structure into hardware TCD register. + * + * param base EDMA peripheral base address. + * param channel EDMA channel number. + * param tcd Point to TCD structure. + */ void EDMA_InstallTCD(DMA_Type *base, uint32_t channel, edma_tcd_t *tcd) { assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL); @@ -92,6 +99,16 @@ void EDMA_InstallTCD(DMA_Type *base, uint32_t channel, edma_tcd_t *tcd) base->TCD[channel].BITER_ELINKNO = tcd->BITER; } +/*! + * brief Initializes the eDMA peripheral. + * + * This function ungates the eDMA clock and configures the eDMA peripheral according + * to the configuration structure. + * + * param base eDMA peripheral base address. + * param config A pointer to the configuration structure, see "edma_config_t". + * note This function enables the minor loop map feature. + */ void EDMA_Init(DMA_Type *base, const edma_config_t *config) { assert(config != NULL); @@ -102,6 +119,11 @@ void EDMA_Init(DMA_Type *base, const edma_config_t *config) /* Ungate EDMA peripheral clock */ CLOCK_EnableClock(s_edmaClockName[EDMA_GetInstance(base)]); #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + + /* clear all the enabled request, status to make sure EDMA status is in normal condition */ + base->ERQ = 0U; + base->INT = 0xFFFFFFFFU; + base->ERR = 0xFFFFFFFFU; /* Configure EDMA peripheral according to the configuration structure. */ tmpreg = base->CR; tmpreg &= ~(DMA_CR_ERCA_MASK | DMA_CR_HOE_MASK | DMA_CR_CLM_MASK | DMA_CR_EDBG_MASK); @@ -110,6 +132,13 @@ void EDMA_Init(DMA_Type *base, const edma_config_t *config) base->CR = tmpreg; } +/*! + * brief Deinitializes the eDMA peripheral. + * + * This function gates the eDMA clock. + * + * param base eDMA peripheral base address. + */ void EDMA_Deinit(DMA_Type *base) { #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) @@ -118,16 +147,44 @@ void EDMA_Deinit(DMA_Type *base) #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ } +/*! + * brief Gets the eDMA default configuration structure. + * + * This function sets the configuration structure to default values. + * The default configuration is set to the following values. + * code + * config.enableContinuousLinkMode = false; + * config.enableHaltOnError = true; + * config.enableRoundRobinArbitration = false; + * config.enableDebugMode = false; + * endcode + * + * param config A pointer to the eDMA configuration structure. + */ void EDMA_GetDefaultConfig(edma_config_t *config) { assert(config != NULL); + /* Initializes the configure structure to zero. */ + memset(config, 0, sizeof(*config)); + config->enableRoundRobinArbitration = false; config->enableHaltOnError = true; config->enableContinuousLinkMode = false; config->enableDebugMode = false; } +/*! + * brief Sets all TCD registers to default values. + * + * This function sets TCD registers for this channel to default values. + * + * param base eDMA peripheral base address. + * param channel eDMA channel number. + * note This function must not be called while the channel transfer is ongoing + * or it causes unpredictable results. + * note This function enables the auto stop request feature. + */ void EDMA_ResetChannel(DMA_Type *base, uint32_t channel) { assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL); @@ -135,6 +192,31 @@ void EDMA_ResetChannel(DMA_Type *base, uint32_t channel) EDMA_TcdReset((edma_tcd_t *)&base->TCD[channel]); } +/*! + * brief Configures the eDMA transfer attribute. + * + * This function configures the transfer attribute, including source address, destination address, + * transfer size, address offset, and so on. It also configures the scatter gather feature if the + * user supplies the TCD address. + * Example: + * code + * edma_transfer_t config; + * edma_tcd_t tcd; + * config.srcAddr = ..; + * config.destAddr = ..; + * ... + * EDMA_SetTransferConfig(DMA0, channel, &config, &stcd); + * endcode + * + * param base eDMA peripheral base address. + * param channel eDMA channel number. + * param config Pointer to eDMA transfer configuration structure. + * param nextTcd Point to TCD structure. It can be NULL if users + * do not want to enable scatter/gather feature. + * note If nextTcd is not NULL, it means scatter gather feature is enabled + * and DREQ bit is cleared in the previous transfer configuration, which + * is set in the eDMA_ResetChannel. + */ void EDMA_SetTransferConfig(DMA_Type *base, uint32_t channel, const edma_transfer_config_t *config, edma_tcd_t *nextTcd) { assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL); @@ -144,6 +226,16 @@ void EDMA_SetTransferConfig(DMA_Type *base, uint32_t channel, const edma_transfe EDMA_TcdSetTransferConfig((edma_tcd_t *)&base->TCD[channel], config, nextTcd); } +/*! + * brief Configures the eDMA minor offset feature. + * + * The minor offset means that the signed-extended value is added to the source address or destination + * address after each minor loop. + * + * param base eDMA peripheral base address. + * param channel eDMA channel number. + * param config A pointer to the minor offset configuration structure. + */ void EDMA_SetMinorOffsetConfig(DMA_Type *base, uint32_t channel, const edma_minor_offset_config_t *config) { assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL); @@ -159,6 +251,22 @@ void EDMA_SetMinorOffsetConfig(DMA_Type *base, uint32_t channel, const edma_mino base->TCD[channel].NBYTES_MLOFFYES = tmpreg; } +/*! + * brief Sets the channel link for the eDMA transfer. + * + * This function configures either the minor link or the major link mode. The minor link means that the channel link is + * triggered every time CITER decreases by 1. The major link means that the channel link is triggered when the CITER is + * exhausted. + * + * param base eDMA peripheral base address. + * param channel eDMA channel number. + * param type A channel link type, which can be one of the following: + * arg kEDMA_LinkNone + * arg kEDMA_MinorLink + * arg kEDMA_MajorLink + * param linkedChannel The linked channel number. + * note Users should ensure that DONE flag is cleared before calling this interface, or the configuration is invalid. + */ void EDMA_SetChannelLink(DMA_Type *base, uint32_t channel, edma_channel_link_type_t type, uint32_t linkedChannel) { assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL); @@ -167,6 +275,20 @@ void EDMA_SetChannelLink(DMA_Type *base, uint32_t channel, edma_channel_link_typ EDMA_TcdSetChannelLink((edma_tcd_t *)&base->TCD[channel], type, linkedChannel); } +/*! + * brief Sets the bandwidth for the eDMA transfer. + * + * Because the eDMA processes the minor loop, it continuously generates read/write sequences + * until the minor count is exhausted. The bandwidth forces the eDMA to stall after the completion of + * each read/write access to control the bus request bandwidth seen by the crossbar switch. + * + * param base eDMA peripheral base address. + * param channel eDMA channel number. + * param bandWidth A bandwidth setting, which can be one of the following: + * arg kEDMABandwidthStallNone + * arg kEDMABandwidthStall4Cycle + * arg kEDMABandwidthStall8Cycle + */ void EDMA_SetBandWidth(DMA_Type *base, uint32_t channel, edma_bandwidth_t bandWidth) { assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL); @@ -174,6 +296,18 @@ void EDMA_SetBandWidth(DMA_Type *base, uint32_t channel, edma_bandwidth_t bandWi base->TCD[channel].CSR = (base->TCD[channel].CSR & (~DMA_CSR_BWC_MASK)) | DMA_CSR_BWC(bandWidth); } +/*! + * brief Sets the source modulo and the destination modulo for the eDMA transfer. + * + * This function defines a specific address range specified to be the value after (SADDR + SOFF)/(DADDR + DOFF) + * calculation is performed or the original register value. It provides the ability to implement a circular data + * queue easily. + * + * param base eDMA peripheral base address. + * param channel eDMA channel number. + * param srcModulo A source modulo value. + * param destModulo A destination modulo value. + */ void EDMA_SetModulo(DMA_Type *base, uint32_t channel, edma_modulo_t srcModulo, edma_modulo_t destModulo) { assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL); @@ -184,6 +318,14 @@ void EDMA_SetModulo(DMA_Type *base, uint32_t channel, edma_modulo_t srcModulo, e base->TCD[channel].ATTR = tmpreg | DMA_ATTR_DMOD(destModulo) | DMA_ATTR_SMOD(srcModulo); } +/*! + * brief Enables the interrupt source for the eDMA transfer. + * + * param base eDMA peripheral base address. + * param channel eDMA channel number. + * param mask The mask of interrupt source to be set. Users need to use + * the defined edma_interrupt_enable_t type. + */ void EDMA_EnableChannelInterrupts(DMA_Type *base, uint32_t channel, uint32_t mask) { assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL); @@ -207,6 +349,14 @@ void EDMA_EnableChannelInterrupts(DMA_Type *base, uint32_t channel, uint32_t mas } } +/*! + * brief Disables the interrupt source for the eDMA transfer. + * + * param base eDMA peripheral base address. + * param channel eDMA channel number. + * param mask The mask of the interrupt source to be set. Use + * the defined edma_interrupt_enable_t type. + */ void EDMA_DisableChannelInterrupts(DMA_Type *base, uint32_t channel, uint32_t mask) { assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL); @@ -230,6 +380,14 @@ void EDMA_DisableChannelInterrupts(DMA_Type *base, uint32_t channel, uint32_t ma } } +/*! + * brief Sets all fields to default values for the TCD structure. + * + * This function sets all fields for this TCD structure to default value. + * + * param tcd Pointer to the TCD structure. + * note This function enables the auto stop request feature. + */ void EDMA_TcdReset(edma_tcd_t *tcd) { assert(tcd != NULL); @@ -250,6 +408,33 @@ void EDMA_TcdReset(edma_tcd_t *tcd) tcd->BITER = 0U; } +/*! + * brief Configures the eDMA TCD transfer attribute. + * + * The TCD is a transfer control descriptor. The content of the TCD is the same as the hardware TCD registers. + * The STCD is used in the scatter-gather mode. + * This function configures the TCD transfer attribute, including source address, destination address, + * transfer size, address offset, and so on. It also configures the scatter gather feature if the + * user supplies the next TCD address. + * Example: + * code + * edma_transfer_t config = { + * ... + * } + * edma_tcd_t tcd __aligned(32); + * edma_tcd_t nextTcd __aligned(32); + * EDMA_TcdSetTransferConfig(&tcd, &config, &nextTcd); + * endcode + * + * param tcd Pointer to the TCD structure. + * param config Pointer to eDMA transfer configuration structure. + * param nextTcd Pointer to the next TCD structure. It can be NULL if users + * do not want to enable scatter/gather feature. + * note TCD address should be 32 bytes aligned or it causes an eDMA error. + * note If the nextTcd is not NULL, the scatter gather feature is enabled + * and DREQ bit is cleared in the previous transfer configuration, which + * is set in the EDMA_TcdReset. + */ void EDMA_TcdSetTransferConfig(edma_tcd_t *tcd, const edma_transfer_config_t *config, edma_tcd_t *nextTcd) { assert(tcd != NULL); @@ -290,6 +475,15 @@ void EDMA_TcdSetTransferConfig(edma_tcd_t *tcd, const edma_transfer_config_t *co } } +/*! + * brief Configures the eDMA TCD minor offset feature. + * + * A minor offset is a signed-extended value added to the source address or a destination + * address after each minor loop. + * + * param tcd A point to the TCD structure. + * param config A pointer to the minor offset configuration structure. + */ void EDMA_TcdSetMinorOffsetConfig(edma_tcd_t *tcd, const edma_minor_offset_config_t *config) { assert(tcd != NULL); @@ -305,6 +499,21 @@ void EDMA_TcdSetMinorOffsetConfig(edma_tcd_t *tcd, const edma_minor_offset_confi tcd->NBYTES = tmpreg; } +/*! + * brief Sets the channel link for the eDMA TCD. + * + * This function configures either a minor link or a major link. The minor link means the channel link is + * triggered every time CITER decreases by 1. The major link means that the channel link is triggered when the CITER is + * exhausted. + * + * note Users should ensure that DONE flag is cleared before calling this interface, or the configuration is invalid. + * param tcd Point to the TCD structure. + * param type Channel link type, it can be one of: + * arg kEDMA_LinkNone + * arg kEDMA_MinorLink + * arg kEDMA_MajorLink + * param linkedChannel The linked channel number. + */ void EDMA_TcdSetChannelLink(edma_tcd_t *tcd, edma_channel_link_type_t type, uint32_t linkedChannel) { assert(tcd != NULL); @@ -344,6 +553,17 @@ void EDMA_TcdSetChannelLink(edma_tcd_t *tcd, edma_channel_link_type_t type, uint } } +/*! + * brief Sets the source modulo and the destination modulo for the eDMA TCD. + * + * This function defines a specific address range specified to be the value after (SADDR + SOFF)/(DADDR + DOFF) + * calculation is performed or the original register value. It provides the ability to implement a circular data + * queue easily. + * + * param tcd A pointer to the TCD structure. + * param srcModulo A source modulo value. + * param destModulo A destination modulo value. + */ void EDMA_TcdSetModulo(edma_tcd_t *tcd, edma_modulo_t srcModulo, edma_modulo_t destModulo) { assert(tcd != NULL); @@ -355,6 +575,13 @@ void EDMA_TcdSetModulo(edma_tcd_t *tcd, edma_modulo_t srcModulo, edma_modulo_t d tcd->ATTR = tmpreg | DMA_ATTR_DMOD(destModulo) | DMA_ATTR_SMOD(srcModulo); } +/*! + * brief Enables the interrupt source for the eDMA TCD. + * + * param tcd Point to the TCD structure. + * param mask The mask of interrupt source to be set. Users need to use + * the defined edma_interrupt_enable_t type. + */ void EDMA_TcdEnableInterrupts(edma_tcd_t *tcd, uint32_t mask) { assert(tcd != NULL); @@ -372,6 +599,13 @@ void EDMA_TcdEnableInterrupts(edma_tcd_t *tcd, uint32_t mask) } } +/*! + * brief Disables the interrupt source for the eDMA TCD. + * + * param tcd Point to the TCD structure. + * param mask The mask of interrupt source to be set. Users need to use + * the defined edma_interrupt_enable_t type. + */ void EDMA_TcdDisableInterrupts(edma_tcd_t *tcd, uint32_t mask) { assert(tcd != NULL); @@ -389,6 +623,27 @@ void EDMA_TcdDisableInterrupts(edma_tcd_t *tcd, uint32_t mask) } } +/*! + * brief Gets the remaining major loop count from the eDMA current channel TCD. + * + * This function checks the TCD (Task Control Descriptor) status for a specified + * eDMA channel and returns the number of major loop count that has not finished. + * + * param base eDMA peripheral base address. + * param channel eDMA channel number. + * return Major loop count which has not been transferred yet for the current TCD. + * note 1. This function can only be used to get unfinished major loop count of transfer without + * the next TCD, or it might be inaccuracy. + * 2. The unfinished/remaining transfer bytes cannot be obtained directly from registers while + * the channel is running. + * Because to calculate the remaining bytes, the initial NBYTES configured in DMA_TCDn_NBYTES_MLNO + * register is needed while the eDMA IP does not support getting it while a channel is active. + * In another word, the NBYTES value reading is always the actual (decrementing) NBYTES value the dma_engine + * is working with while a channel is running. + * Consequently, to get the remaining transfer bytes, a software-saved initial value of NBYTES (for example + * copied before enabling the channel) is needed. The formula to calculate it is shown below: + * RemainingBytes = RemainingMajorLoopCount * NBYTES(initially configured) + */ uint32_t EDMA_GetRemainingMajorLoopCount(DMA_Type *base, uint32_t channel) { assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL); @@ -417,6 +672,14 @@ uint32_t EDMA_GetRemainingMajorLoopCount(DMA_Type *base, uint32_t channel) return remainingCount; } +/*! + * brief Gets the eDMA channel status flags. + * + * param base eDMA peripheral base address. + * param channel eDMA channel number. + * return The mask of channel status flags. Users need to use the + * _edma_channel_status_flags type to decode the return variables. + */ uint32_t EDMA_GetChannelStatusFlags(DMA_Type *base, uint32_t channel) { assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL); @@ -433,6 +696,14 @@ uint32_t EDMA_GetChannelStatusFlags(DMA_Type *base, uint32_t channel) return retval; } +/*! + * brief Clears the eDMA channel status flags. + * + * param base eDMA peripheral base address. + * param channel eDMA channel number. + * param mask The mask of channel status to be cleared. Users need to use + * the defined _edma_channel_status_flags type. + */ void EDMA_ClearChannelStatusFlags(DMA_Type *base, uint32_t channel, uint32_t mask) { assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL); @@ -471,6 +742,17 @@ static uint8_t Get_StartInstance(void) return StartInstanceNum; } +/*! + * brief Creates the eDMA handle. + * + * This function is called if using the transactional API for eDMA. This function + * initializes the internal state of the eDMA handle. + * + * param handle eDMA handle pointer. The eDMA handle stores callback function and + * parameters. + * param base eDMA peripheral base address. + * param channel eDMA channel number. + */ void EDMA_CreateHandle(edma_handle_t *handle, DMA_Type *base, uint32_t channel) { assert(handle != NULL); @@ -514,6 +796,18 @@ void EDMA_CreateHandle(edma_handle_t *handle, DMA_Type *base, uint32_t channel) tcdRegs->BITER = 0; } +/*! + * brief Installs the TCDs memory pool into the eDMA handle. + * + * This function is called after the EDMA_CreateHandle to use scatter/gather feature. This function shall only be used + * while users need to use scatter gather mode. Scatter gather mode enables EDMA to load a new transfer control block + * (tcd) in hardware, and automatically reconfigure that DMA channel for a new transfer. + * Users need to prepare tcd memory and also configure tcds using interface EDMA_SubmitTransfer. + * + * param handle eDMA handle pointer. + * param tcdPool A memory pool to store TCDs. It must be 32 bytes aligned. + * param tcdSize The number of TCD slots. + */ void EDMA_InstallTCDMemory(edma_handle_t *handle, edma_tcd_t *tcdPool, uint32_t tcdSize) { assert(handle != NULL); @@ -528,6 +822,16 @@ void EDMA_InstallTCDMemory(edma_handle_t *handle, edma_tcd_t *tcdPool, uint32_t handle->tcdPool = tcdPool; } +/*! + * brief Installs a callback function for the eDMA transfer. + * + * This callback is called in the eDMA IRQ handler. Use the callback to do something after + * the current major loop transfer completes. This function will be called every time one tcd finished transfer. + * + * param handle eDMA handle pointer. + * param callback eDMA callback function pointer. + * param userData A parameter for the callback function. + */ void EDMA_SetCallback(edma_handle_t *handle, edma_callback callback, void *userData) { assert(handle != NULL); @@ -536,6 +840,23 @@ void EDMA_SetCallback(edma_handle_t *handle, edma_callback callback, void *userD handle->userData = userData; } +/*! + * brief Prepares the eDMA transfer structure. + * + * This function prepares the transfer configuration structure according to the user input. + * + * param config The user configuration structure of type edma_transfer_t. + * param srcAddr eDMA transfer source address. + * param srcWidth eDMA transfer source address width(bytes). + * param destAddr eDMA transfer destination address. + * param destWidth eDMA transfer destination address width(bytes). + * param bytesEachRequest eDMA transfer bytes per channel request. + * param transferBytes eDMA transfer bytes to be transferred. + * param type eDMA transfer type. + * note The data address and the data width must be consistent. For example, if the SRC + * is 4 bytes, the source address must be 4 bytes aligned, or it results in + * source address error (SAE). + */ void EDMA_PrepareTransfer(edma_transfer_config_t *config, void *srcAddr, uint32_t srcWidth, @@ -552,6 +873,9 @@ void EDMA_PrepareTransfer(edma_transfer_config_t *config, assert((destWidth == 1U) || (destWidth == 2U) || (destWidth == 4U) || (destWidth == 16U) || (destWidth == 32U)); assert(transferBytes % bytesEachRequest == 0); + /* Initializes the configure structure to zero. */ + memset(config, 0, sizeof(*config)); + config->destAddr = (uint32_t)destAddr; config->srcAddr = (uint32_t)srcAddr; config->minorLoopBytes = bytesEachRequest; @@ -615,6 +939,19 @@ void EDMA_PrepareTransfer(edma_transfer_config_t *config, } } +/*! + * brief Submits the eDMA transfer request. + * + * This function submits the eDMA transfer request according to the transfer configuration structure. + * In scatter gather mode, call this function will add a configured tcd to the circular list of tcd pool. + * The tcd pools is setup by call function EDMA_InstallTCDMemory before. + * + * param handle eDMA handle pointer. + * param config Pointer to eDMA transfer configuration structure. + * retval kStatus_EDMA_Success It means submit transfer request succeed. + * retval kStatus_EDMA_QueueFull It means TCD queue is full. Submit transfer request is not allowed. + * retval kStatus_EDMA_Busy It means the given channel is busy, need to submit request later. + */ status_t EDMA_SubmitTransfer(edma_handle_t *handle, const edma_transfer_config_t *config) { assert(handle != NULL); @@ -754,6 +1091,14 @@ status_t EDMA_SubmitTransfer(edma_handle_t *handle, const edma_transfer_config_t } } +/*! + * brief eDMA starts transfer. + * + * This function enables the channel request. Users can call this function after submitting the transfer request + * or before submitting the transfer request. + * + * param handle eDMA handle pointer. + */ void EDMA_StartTransfer(edma_handle_t *handle) { assert(handle != NULL); @@ -791,6 +1136,14 @@ void EDMA_StartTransfer(edma_handle_t *handle) } } +/*! + * brief eDMA stops transfer. + * + * This function disables the channel request to pause the transfer. Users can call EDMA_StartTransfer() + * again to resume the transfer. + * + * param handle eDMA handle pointer. + */ void EDMA_StopTransfer(edma_handle_t *handle) { assert(handle != NULL); @@ -799,6 +1152,14 @@ void EDMA_StopTransfer(edma_handle_t *handle) handle->base->CERQ = DMA_CERQ_CERQ(handle->channel); } +/*! + * brief eDMA aborts transfer. + * + * This function disables the channel request and clear transfer status bits. + * Users can submit another transfer after calling this API. + * + * param handle DMA handle pointer. + */ void EDMA_AbortTransfer(edma_handle_t *handle) { handle->base->CERQ = DMA_CERQ_CERQ(handle->channel); @@ -820,6 +1181,34 @@ void EDMA_AbortTransfer(edma_handle_t *handle) } } +/*! + * brief eDMA IRQ handler for the current major loop transfer completion. + * + * This function clears the channel major interrupt flag and calls + * the callback function if it is not NULL. + * + * Note: + * For the case using TCD queue, when the major iteration count is exhausted, additional operations are performed. + * These include the final address adjustments and reloading of the BITER field into the CITER. + * Assertion of an optional interrupt request also occurs at this time, as does a possible fetch of a new TCD from + * memory using the scatter/gather address pointer included in the descriptor (if scatter/gather is enabled). + * + * For instance, when the time interrupt of TCD[0] happens, the TCD[1] has already been loaded into the eDMA engine. + * As sga and sga_index are calculated based on the DLAST_SGA bitfield lies in the TCD_CSR register, the sga_index + * in this case should be 2 (DLAST_SGA of TCD[1] stores the address of TCD[2]). Thus, the "tcdUsed" updated should be + * (tcdUsed - 2U) which indicates the number of TCDs can be loaded in the memory pool (because TCD[0] and TCD[1] have + * been loaded into the eDMA engine at this point already.). + * + * For the last two continuous ISRs in a scatter/gather process, they both load the last TCD (The last ISR does not + * load a new TCD) from the memory pool to the eDMA engine when major loop completes. + * Therefore, ensure that the header and tcdUsed updated are identical for them. + * tcdUsed are both 0 in this case as no TCD to be loaded. + * + * See the "eDMA basic data flow" in the eDMA Functional description section of the Reference Manual for + * further details. + * + * param handle eDMA handle pointer. + */ void EDMA_HandleIRQ(edma_handle_t *handle) { assert(handle != NULL); diff --git a/ext/hal/nxp/mcux/drivers/imx/fsl_edma.h b/ext/hal/nxp/mcux/drivers/imx/fsl_edma.h index 705369deed0..802f1303598 100644 --- a/ext/hal/nxp/mcux/drivers/imx/fsl_edma.h +++ b/ext/hal/nxp/mcux/drivers/imx/fsl_edma.h @@ -1,6 +1,6 @@ /* * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP + * Copyright 2016-2018 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -23,7 +23,7 @@ /*! @name Driver version */ /*@{*/ /*! @brief eDMA driver version */ -#define FSL_EDMA_DRIVER_VERSION (MAKE_VERSION(2, 1, 3)) /*!< Version 2.1.3. */ +#define FSL_EDMA_DRIVER_VERSION (MAKE_VERSION(2, 1, 4)) /*!< Version 2.1.4. */ /*@}*/ /*! @brief Compute the offset unit from DCHPRI3 */ @@ -121,7 +121,7 @@ enum _edma_error_status_flags #if defined(FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT) && FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT > 1 kEDMA_GroupPriorityErrorFlag = DMA_ES_GPE_MASK, /*!< Group priority is not unique. */ #endif - kEDMA_ValidFlag = DMA_ES_VLD_MASK, /*!< No error occurred, this bit is 0. Otherwise, it is 1. */ + kEDMA_ValidFlag = (int)DMA_ES_VLD_MASK, /*!< No error occurred, this bit is 0. Otherwise, it is 1. */ }; /*! @brief eDMA interrupt source */ diff --git a/ext/hal/nxp/mcux/drivers/imx/fsl_elcdif.c b/ext/hal/nxp/mcux/drivers/imx/fsl_elcdif.c index 3922e500775..583286c8a29 100644 --- a/ext/hal/nxp/mcux/drivers/imx/fsl_elcdif.c +++ b/ext/hal/nxp/mcux/drivers/imx/fsl_elcdif.c @@ -2,7 +2,7 @@ * Copyright (c) 2017, NXP Semiconductors, Inc. * All rights reserved. * - * + * * SPDX-License-Identifier: BSD-3-Clause */ @@ -13,7 +13,6 @@ #define FSL_COMPONENT_ID "platform.drivers.elcdif" #endif - /******************************************************************************* * Prototypes ******************************************************************************/ @@ -91,6 +90,15 @@ static uint32_t ELCDIF_GetInstance(LCDIF_Type *base) return instance; } +/*! + * brief Initializes the eLCDIF to work in RGB mode (DOTCLK mode). + * + * This function ungates the eLCDIF clock and configures the eLCDIF peripheral according + * to the configuration structure. + * + * param base eLCDIF peripheral base address. + * param config Pointer to the configuration structure. + */ void ELCDIF_RgbModeInit(LCDIF_Type *base, const elcdif_rgb_mode_config_t *config) { assert(config); @@ -138,10 +146,38 @@ void ELCDIF_RgbModeInit(LCDIF_Type *base, const elcdif_rgb_mode_config_t *config base->NEXT_BUF = config->bufferAddr; } +/*! + * brief Gets the eLCDIF default configuration structure for RGB (DOTCLK) mode. + * + * This function sets the configuration structure to default values. + * The default configuration is set to the following values. + * code + config->panelWidth = 480U; + config->panelHeight = 272U; + config->hsw = 41; + config->hfp = 4; + config->hbp = 8; + config->vsw = 10; + config->vfp = 4; + config->vbp = 2; + config->polarityFlags = kELCDIF_VsyncActiveLow | + kELCDIF_HsyncActiveLow | + kELCDIF_DataEnableActiveLow | + kELCDIF_DriveDataOnFallingClkEdge; + config->bufferAddr = 0U; + config->pixelFormat = kELCDIF_PixelFormatRGB888; + config->dataBus = kELCDIF_DataBus24Bit; + code + * + * param config Pointer to the eLCDIF configuration structure. + */ void ELCDIF_RgbModeGetDefaultConfig(elcdif_rgb_mode_config_t *config) { assert(config); + /* Initializes the configure structure to zero. */ + memset(config, 0, sizeof(*config)); + config->panelWidth = 480U; config->panelHeight = 272U; config->hsw = 41; @@ -157,6 +193,11 @@ void ELCDIF_RgbModeGetDefaultConfig(elcdif_rgb_mode_config_t *config) config->dataBus = kELCDIF_DataBus24Bit; } +/*! + * brief Deinitializes the eLCDIF peripheral. + * + * param base eLCDIF peripheral base address. + */ void ELCDIF_Deinit(LCDIF_Type *base) { ELCDIF_Reset(base); @@ -171,6 +212,11 @@ void ELCDIF_Deinit(LCDIF_Type *base) #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ } +/*! + * brief Stop display in RGB (DOTCLK) mode and wait until finished. + * + * param base eLCDIF peripheral base address. + */ void ELCDIF_RgbModeStop(LCDIF_Type *base) { base->CTRL_CLR = LCDIF_CTRL_DOTCLK_MODE_MASK; @@ -181,6 +227,11 @@ void ELCDIF_RgbModeStop(LCDIF_Type *base) } } +/*! + * brief Reset the eLCDIF peripheral. + * + * param base eLCDIF peripheral base address. + */ void ELCDIF_Reset(LCDIF_Type *base) { volatile uint32_t i = 0x100; @@ -211,6 +262,12 @@ void ELCDIF_Reset(LCDIF_Type *base) } #if !(defined(FSL_FEATURE_LCDIF_HAS_NO_AS) && FSL_FEATURE_LCDIF_HAS_NO_AS) +/*! + * brief Set the configuration for alpha surface buffer. + * + * param base eLCDIF peripheral base address. + * param config Pointer to the configuration structure. + */ void ELCDIF_SetAlphaSurfaceBufferConfig(LCDIF_Type *base, const elcdif_as_buffer_config_t *config) { assert(config); @@ -220,6 +277,12 @@ void ELCDIF_SetAlphaSurfaceBufferConfig(LCDIF_Type *base, const elcdif_as_buffer base->AS_NEXT_BUF = config->bufferAddr; } +/*! + * brief Set the alpha surface blending configuration. + * + * param base eLCDIF peripheral base address. + * param config Pointer to the configuration structure. + */ void ELCDIF_SetAlphaSurfaceBlendConfig(LCDIF_Type *base, const elcdif_as_blend_config_t *config) { assert(config); @@ -241,6 +304,20 @@ void ELCDIF_SetAlphaSurfaceBlendConfig(LCDIF_Type *base, const elcdif_as_blend_c #endif /* FSL_FEATURE_LCDIF_HAS_NO_AS */ #if (defined(FSL_FEATURE_LCDIF_HAS_LUT) && FSL_FEATURE_LCDIF_HAS_LUT) +/*! + * brief Load the LUT value. + * + * This function loads the LUT value to the specific LUT memory, user can + * specify the start entry index. + * + * param base eLCDIF peripheral base address. + * param lut Which LUT to load. + * param startIndex The start index of the LUT entry to update. + * param lutData The LUT data to load. + * param count Count of p lutData. + * retval kStatus_Success Initialization success. + * retval kStatus_InvalidArgument Wrong argument. + */ status_t ELCDIF_UpdateLut( LCDIF_Type *base, elcdif_lut_t lut, uint16_t startIndex, const uint32_t *lutData, uint16_t count) { diff --git a/ext/hal/nxp/mcux/drivers/imx/fsl_enc.c b/ext/hal/nxp/mcux/drivers/imx/fsl_enc.c index 700158238a9..e9d7e048880 100644 --- a/ext/hal/nxp/mcux/drivers/imx/fsl_enc.c +++ b/ext/hal/nxp/mcux/drivers/imx/fsl_enc.c @@ -2,7 +2,7 @@ * Copyright (c) 2015, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP * All rights reserved. - * + * * SPDX-License-Identifier: BSD-3-Clause */ @@ -62,6 +62,17 @@ static uint32_t ENC_GetInstance(ENC_Type *base) return instance; } +/*! + * brief Initialization for the ENC module. + * + * This function is to make the initialization for the ENC module. It should be called firstly before any operation to + * the ENC with the operations like: + * - Enable the clock for ENC module. + * - Configure the ENC's working attributes. + * + * param base ENC peripheral base address. + * param config Pointer to configuration structure. See to "enc_config_t". + */ void ENC_Init(ENC_Type *base, const enc_config_t *config) { assert(NULL != config); @@ -151,6 +162,15 @@ void ENC_Init(ENC_Type *base, const enc_config_t *config) base->LINIT = (uint16_t)(config->positionInitialValue); /* Lower 16 bits. */ } +/*! + * brief De-initialization for the ENC module. + * + * This function is to make the de-initialization for the ENC module. It could be called when ENC is no longer used with + * the operations like: + * - Disable the clock for ENC module. + * + * param base ENC peripheral base address. + */ void ENC_Deinit(ENC_Type *base) { #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) @@ -159,10 +179,37 @@ void ENC_Deinit(ENC_Type *base) #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ } +/*! + * brief Get an available pre-defined settings for ENC's configuration. + * + * This function initializes the ENC configuration structure with an available settings, the default value are: + * code + * config->enableReverseDirection = false; + * config->decoderWorkMode = kENC_DecoderWorkAsNormalMode; + * config->HOMETriggerMode = kENC_HOMETriggerDisabled; + * config->INDEXTriggerMode = kENC_INDEXTriggerDisabled; + * config->enableTRIGGERClearPositionCounter = false; + * config->enableTRIGGERClearHoldPositionCounter = false; + * config->enableWatchdog = false; + * config->watchdogTimeoutValue = 0U; + * config->filterCount = 0U; + * config->filterSamplePeriod = 0U; + * config->positionMatchMode = kENC_POSMATCHOnPositionCounterEqualToComapreValue; + * config->positionCompareValue = 0xFFFFFFFFU; + * config->revolutionCountCondition = kENC_RevolutionCountOnINDEXPulse; + * config->enableModuloCountMode = false; + * config->positionModulusValue = 0U; + * config->positionInitialValue = 0U; + * endcode + * param config Pointer to a variable of configuration structure. See to "enc_config_t". + */ void ENC_GetDefaultConfig(enc_config_t *config) { assert(NULL != config); + /* Initializes the configure structure to zero. */ + memset(config, 0, sizeof(*config)); + config->enableReverseDirection = false; config->decoderWorkMode = kENC_DecoderWorkAsNormalMode; config->HOMETriggerMode = kENC_HOMETriggerDisabled; @@ -181,6 +228,14 @@ void ENC_GetDefaultConfig(enc_config_t *config) config->positionInitialValue = 0U; } +/*! + * brief Load the initial position value to position counter. + * + * This function is to transfer the initial position value (UINIT and LINIT) contents to position counter (UPOS and + * LPOS), so that to provide the consistent operation the position counter registers. + * + * param base ENC peripheral base address. + */ void ENC_DoSoftwareLoadInitialPositionValue(ENC_Type *base) { uint16_t tmp16 = base->CTRL & (uint16_t)(~ENC_CTRL_W1C_FLAGS); @@ -189,6 +244,16 @@ void ENC_DoSoftwareLoadInitialPositionValue(ENC_Type *base) base->CTRL = tmp16; } +/*! + * brief Enable and configure the self test function. + * + * This function is to enable and configuration the self test function. It controls and sets the frequency of a + * quadrature signal generator. It provides a quadrature test signal to the inputs of the quadrature decoder module. + * It is a factory test feature; however, it may be useful to customers' software development and testing. + * + * param base ENC peripheral base address. + * param config Pointer to configuration structure. See to "enc_self_test_config_t". Pass "NULL" to disable. + */ void ENC_SetSelfTestConfig(ENC_Type *base, const enc_self_test_config_t *config) { uint16_t tmp16 = 0U; @@ -207,6 +272,12 @@ void ENC_SetSelfTestConfig(ENC_Type *base, const enc_self_test_config_t *config) base->TST = tmp16; } +/*! + * brief Enable watchdog for ENC module. + * + * param base ENC peripheral base address + * param enable Enables or disables the watchdog + */ void ENC_EnableWatchdog(ENC_Type *base, bool enable) { uint16_t tmp16 = base->CTRL & (uint16_t)(~(ENC_CTRL_W1C_FLAGS | ENC_CTRL_WDE_MASK)); @@ -218,6 +289,13 @@ void ENC_EnableWatchdog(ENC_Type *base, bool enable) base->CTRL = tmp16; } +/*! + * brief Get the status flags. + * + * param base ENC peripheral base address. + * + * return Mask value of status flags. For available mask, see to "_enc_status_flags". + */ uint32_t ENC_GetStatusFlags(ENC_Type *base) { uint32_t ret32 = 0U; @@ -261,6 +339,12 @@ uint32_t ENC_GetStatusFlags(ENC_Type *base) return ret32; } +/*! + * brief Clear the status flags. + * + * param base ENC peripheral base address. + * param mask Mask value of status flags to be cleared. For available mask, see to "_enc_status_flags". + */ void ENC_ClearStatusFlags(ENC_Type *base, uint32_t mask) { uint32_t tmp16 = 0U; @@ -307,6 +391,12 @@ void ENC_ClearStatusFlags(ENC_Type *base, uint32_t mask) } } +/*! + * brief Enable the interrupts. + * + * param base ENC peripheral base address. + * param mask Mask value of interrupts to be enabled. For available mask, see to "_enc_interrupt_enable". + */ void ENC_EnableInterrupts(ENC_Type *base, uint32_t mask) { uint32_t tmp16 = 0U; @@ -352,6 +442,12 @@ void ENC_EnableInterrupts(ENC_Type *base, uint32_t mask) } } +/*! + * brief Disable the interrupts. + * + * param base ENC peripheral base address. + * param mask Mask value of interrupts to be disabled. For available mask, see to "_enc_interrupt_enable". + */ void ENC_DisableInterrupts(ENC_Type *base, uint32_t mask) { uint16_t tmp16 = 0U; @@ -397,6 +493,13 @@ void ENC_DisableInterrupts(ENC_Type *base, uint32_t mask) } } +/*! + * brief Get the enabled interrupts' flags. + * + * param base ENC peripheral base address. + * + * return Mask value of enabled interrupts. + */ uint32_t ENC_GetEnabledInterrupts(ENC_Type *base) { uint32_t ret32 = 0U; @@ -434,12 +537,25 @@ uint32_t ENC_GetEnabledInterrupts(ENC_Type *base) return ret32; } +/*! + * brief Set initial position value for ENC module. + * + * param base ENC peripheral base address + * param value Positive initial value + */ void ENC_SetInitialPositionValue(ENC_Type *base, uint32_t value) { base->UINIT = (uint16_t)(value >> 16U); /* Set upper 16 bits. */ base->LINIT = (uint16_t)(value); /* Set lower 16 bits. */ } +/*! + * brief Get the current position counter's value. + * + * param base ENC peripheral base address. + * + * return Current position counter's value. + */ uint32_t ENC_GetPositionValue(ENC_Type *base) { uint32_t ret32; @@ -451,6 +567,17 @@ uint32_t ENC_GetPositionValue(ENC_Type *base) return ret32; } +/*! + * brief Get the hold position counter's value. + * + * When any of the counter registers is read, the contents of each counter register is written to the corresponding hold + * register. Taking a snapshot of the counters' values provides a consistent view of a system position and a velocity to + * be attained. + * + * param base ENC peripheral base address. + * + * return Hold position counter's value. + */ uint32_t ENC_GetHoldPositionValue(ENC_Type *base) { uint32_t ret32; diff --git a/ext/hal/nxp/mcux/drivers/imx/fsl_enet.c b/ext/hal/nxp/mcux/drivers/imx/fsl_enet.c index f5c6613ad21..b8bb27ea1ab 100644 --- a/ext/hal/nxp/mcux/drivers/imx/fsl_enet.c +++ b/ext/hal/nxp/mcux/drivers/imx/fsl_enet.c @@ -2,7 +2,7 @@ * Copyright (c) 2015 - 2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP * All rights reserved. - * + * * SPDX-License-Identifier: BSD-3-Clause */ @@ -155,7 +155,9 @@ static void ENET_SetHandler(ENET_Type *base, * @param config The ENET configuration structure. * @param bufferConfig The ENET buffer configuration. */ -static void ENET_SetTxBufferDescriptors(enet_handle_t *handle, const enet_config_t *config, const enet_buffer_config_t *bufferConfig); +static void ENET_SetTxBufferDescriptors(enet_handle_t *handle, + const enet_config_t *config, + const enet_buffer_config_t *bufferConfig); /*! * @brief Set ENET MAC receive buffer descriptors. @@ -164,7 +166,9 @@ static void ENET_SetTxBufferDescriptors(enet_handle_t *handle, const enet_config * @param config The ENET configuration structure. * @param bufferConfig The ENET buffer configuration. */ -static void ENET_SetRxBufferDescriptors(enet_handle_t *handle, const enet_config_t *config, const enet_buffer_config_t *bufferConfig); +static void ENET_SetRxBufferDescriptors(enet_handle_t *handle, + const enet_config_t *config, + const enet_buffer_config_t *bufferConfig); /*! * @brief Updates the ENET read buffer descriptors. @@ -312,6 +316,20 @@ uint32_t ENET_GetInstance(ENET_Type *base) return instance; } +/*! + * brief Gets the ENET default configuration structure. + * + * The purpose of this API is to get the default ENET MAC controller + * configure structure for ENET_Init(). User may use the initialized + * structure unchanged in ENET_Init(), or modify some fields of the + * structure before calling ENET_Init(). + * Example: + code + enet_config_t config; + ENET_GetDefaultConfig(&config); + endcode + * param config The ENET mac controller configuration structure pointer. + */ void ENET_GetDefaultConfig(enet_config_t *config) { /* Checks input parameter. */ @@ -320,13 +338,13 @@ void ENET_GetDefaultConfig(enet_config_t *config) /* Initializes the MAC configure structure to zero. */ memset(config, 0, sizeof(enet_config_t)); - /* Sets MII mode, full duplex, 100Mbps for MAC and PHY data interface. */ -#if defined(FSL_FEATURE_ENET_HAS_AVB) && FSL_FEATURE_ENET_HAS_AVB +/* Sets MII mode, full duplex, 100Mbps for MAC and PHY data interface. */ +#if defined(FSL_FEATURE_ENET_HAS_AVB) && FSL_FEATURE_ENET_HAS_AVB config->miiMode = kENET_RgmiiMode; #else config->miiMode = kENET_RmiiMode; #endif - config->miiSpeed = kENET_MiiSpeed100M; + config->miiSpeed = kENET_MiiSpeed100M; config->miiDuplex = kENET_MiiFullDuplex; config->ringNum = 1; @@ -335,6 +353,33 @@ void ENET_GetDefaultConfig(enet_config_t *config) config->rxMaxFrameLen = ENET_FRAME_MAX_FRAMELEN; } +/*! + * brief Initializes the ENET module. + * + * This function ungates the module clock and initializes it with the ENET configuration. + * + * param base ENET peripheral base address. + * param handle ENET handler pointer. + * param config ENET mac configuration structure pointer. + * The "enet_config_t" type mac configuration return from ENET_GetDefaultConfig + * can be used directly. It is also possible to verify the Mac configuration using other methods. + * param bufferConfig ENET buffer configuration structure pointer. + * The buffer configuration should be prepared for ENET Initialization. + * It is the start address of "ringNum" enet_buffer_config structures. + * To support added multi-ring features in some soc and compatible with the previous + * enet driver version. For single ring supported, this bufferConfig is a buffer + * configure structure pointer, for multi-ring supported and used case, this bufferConfig + * pointer should be a buffer configure structure array pointer. + * param macAddr ENET mac address of Ethernet device. This MAC address should be + * provided. + * param srcClock_Hz The internal module clock source for MII clock. + * + * note ENET has two buffer descriptors legacy buffer descriptors and + * enhanced IEEE 1588 buffer descriptors. The legacy descriptor is used by default. To + * use the IEEE 1588 feature, use the enhanced IEEE 1588 buffer descriptor + * by defining "ENET_ENHANCEDBUFFERDESCRIPTOR_MODE" and calling ENET_Ptp1588Configure() + * to configure the 1588 feature and related buffers after calling ENET_Init(). + */ void ENET_Init(ENET_Type *base, enet_handle_t *handle, const enet_config_t *config, @@ -371,6 +416,13 @@ void ENET_Init(ENET_Type *base, ENET_SetHandler(base, handle, config, bufferConfig); } +/*! + * brief Deinitializes the ENET module. + + * This function gates the module clock, clears ENET interrupts, and disables the ENET module. + * + * param base ENET peripheral base address. + */ void ENET_Deinit(ENET_Type *base) { /* Disable interrupt. */ @@ -379,13 +431,21 @@ void ENET_Deinit(ENET_Type *base) /* Disable ENET. */ base->ECR &= ~ENET_ECR_ETHEREN_MASK; - #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) /* Disables the clock source. */ CLOCK_DisableClock(s_enetClock[ENET_GetInstance(base)]); #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ } +/*! + * brief Sets the callback function. + * This API is provided for the application callback required case when ENET + * interrupt is enabled. This API should be called after calling ENET_Init. + * + * param handle ENET handler pointer. Should be provided by application. + * param callback The ENET callback function. + * param userData The callback function parameter. + */ void ENET_SetCallback(enet_handle_t *handle, enet_callback_t callback, void *userData) { assert(handle); @@ -487,7 +547,7 @@ static void ENET_SetMacController(ENET_Type *base, ((macSpecialConfig & kENET_ControlRxPadRemoveEnable) ? ENET_RCR_PADEN_MASK : 0) | ((macSpecialConfig & kENET_ControlRxBroadCastRejectEnable) ? ENET_RCR_BC_REJ_MASK : 0) | ((macSpecialConfig & kENET_ControlPromiscuousEnable) ? ENET_RCR_PROM_MASK : 0) | - ENET_RCR_MAX_FL(maxFrameLen) | ENET_RCR_CRCFWD_MASK; + ENET_RCR_MAX_FL(maxFrameLen) | ENET_RCR_CRCFWD_MASK; /* Set the RGMII or RMII, MII mode and control register. */ #if defined(FSL_FEATURE_ENET_HAS_AVB) && FSL_FEATURE_ENET_HAS_AVB @@ -580,14 +640,14 @@ static void ENET_SetMacController(ENET_Type *base, base->RSFL = 0; } - /* Initializes the ring 0. */ +/* Initializes the ring 0. */ #if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET base->TDSR = MEMORY_ConvertMemoryMapAddress((uint32_t)bufferConfig->txBdStartAddrAlign, kMEMORY_Local2DMA); - base->RDSR = MEMORY_ConvertMemoryMapAddress((uint32_t)bufferConfig->rxBdStartAddrAlign, kMEMORY_Local2DMA); + base->RDSR = MEMORY_ConvertMemoryMapAddress((uint32_t)bufferConfig->rxBdStartAddrAlign, kMEMORY_Local2DMA); #else base->TDSR = (uint32_t)bufferConfig->txBdStartAddrAlign; base->RDSR = (uint32_t)bufferConfig->rxBdStartAddrAlign; -#endif +#endif base->MRBR = bufferConfig->rxBuffSizeAlign; #if defined(FSL_FEATURE_ENET_HAS_AVB) && FSL_FEATURE_ENET_HAS_AVB @@ -602,7 +662,7 @@ static void ENET_SetMacController(ENET_Type *base, base->RDSR1 = MEMORY_ConvertMemoryMapAddress((uint32_t)buffCfg->rxBdStartAddrAlign, kMEMORY_Local2DMA); #else base->TDSR1 = (uint32_t)buffCfg->txBdStartAddrAlign; - base->RDSR1 = (uint32_t)buffCfg->rxBdStartAddrAlign; + base->RDSR1 = (uint32_t)buffCfg->rxBdStartAddrAlign; #endif base->MRBR1 = buffCfg->rxBuffSizeAlign; /* Enable the DMAC for ring 1 and with no rx classification set. */ @@ -684,7 +744,9 @@ static void ENET_SetMacController(ENET_Type *base, base->ECR = ecr; } -static void ENET_SetTxBufferDescriptors(enet_handle_t *handle, const enet_config_t *config, const enet_buffer_config_t *bufferConfig) +static void ENET_SetTxBufferDescriptors(enet_handle_t *handle, + const enet_config_t *config, + const enet_buffer_config_t *bufferConfig) { assert(config); assert(bufferConfig); @@ -738,7 +800,9 @@ static void ENET_SetTxBufferDescriptors(enet_handle_t *handle, const enet_config } } -static void ENET_SetRxBufferDescriptors(enet_handle_t *handle, const enet_config_t *config, const enet_buffer_config_t *bufferConfig) +static void ENET_SetRxBufferDescriptors(enet_handle_t *handle, + const enet_config_t *config, + const enet_buffer_config_t *bufferConfig) { assert(config); assert(bufferConfig); @@ -782,7 +846,7 @@ static void ENET_SetRxBufferDescriptors(enet_handle_t *handle, const enet_config #if defined(FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL) && FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL /* Invalidate rx buffers before DMA transfer data into them. */ - DCACHE_InvalidateByRange((uint32_t)rxBuffer, (buffCfg->rxBdNumber * rxBuffSizeAlign)); + DCACHE_InvalidateByRange((uint32_t)rxBuffer, (buffCfg->rxBdNumber * rxBuffSizeAlign)); #endif /* FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL */ for (count = 0; count < buffCfg->rxBdNumber; count++) @@ -841,6 +905,15 @@ static void ENET_ActiveSend(ENET_Type *base, uint32_t ringId) } } +/*! + * brief Sets the ENET MII speed and duplex. + * + * This API is provided to dynamically change the speed and dulpex for MAC. + * + * param base ENET peripheral base address. + * param speed The speed of the RMII mode. + * param duplex The duplex of the RMII mode. + */ void ENET_SetMII(ENET_Type *base, enet_mii_speed_t speed, enet_mii_duplex_t duplex) { uint32_t rcr = base->RCR; @@ -887,6 +960,13 @@ void ENET_SetMII(ENET_Type *base, enet_mii_speed_t speed, enet_mii_duplex_t dupl base->TCR = tcr; } +/*! + * brief Sets the ENET module Mac address. + * + * param base ENET peripheral base address. + * param macAddr The six-byte Mac address pointer. + * The pointer is allocated by application and input into the API. + */ void ENET_SetMacAddr(ENET_Type *base, uint8_t *macAddr) { uint32_t address; @@ -900,6 +980,13 @@ void ENET_SetMacAddr(ENET_Type *base, uint8_t *macAddr) base->PAUR = address << ENET_PAUR_PADDR2_SHIFT; } +/*! + * brief Gets the ENET module Mac address. + * + * param base ENET peripheral base address. + * param macAddr The six-byte Mac address pointer. + * The pointer is allocated by application and input into the API. + */ void ENET_GetMacAddr(ENET_Type *base, uint8_t *macAddr) { assert(macAddr); @@ -919,6 +1006,15 @@ void ENET_GetMacAddr(ENET_Type *base, uint8_t *macAddr) macAddr[5] = 0xFFU & address; } +/*! + * brief Sets the ENET SMI(serial management interface)- MII management interface. + * + * param base ENET peripheral base address. + * param srcClock_Hz This is the ENET module clock frequency. Normally it's the system clock. See clock distribution. + * param isPreambleDisabled The preamble disable flag. + * - true Enables the preamble. + * - false Disables the preamble. + */ void ENET_SetSMI(ENET_Type *base, uint32_t srcClock_Hz, bool isPreambleDisabled) { assert(srcClock_Hz); @@ -932,10 +1028,22 @@ void ENET_SetSMI(ENET_Type *base, uint32_t srcClock_Hz, bool isPreambleDisabled) /* Calculate the hold time on the MDIO output. */ clkCycle = (10 + ENET_NANOSECOND_ONE_SECOND / srcClock_Hz - 1) / (ENET_NANOSECOND_ONE_SECOND / srcClock_Hz) - 1; /* Build the configuration for MDC/MDIO control. */ - mscr = ENET_MSCR_MII_SPEED(speed) | ENET_MSCR_HOLDTIME(clkCycle) | (isPreambleDisabled ? ENET_MSCR_DIS_PRE_MASK : 0); + mscr = + ENET_MSCR_MII_SPEED(speed) | ENET_MSCR_HOLDTIME(clkCycle) | (isPreambleDisabled ? ENET_MSCR_DIS_PRE_MASK : 0); base->MSCR = mscr; } +/*! + * brief Starts an SMI write command. + * + * Used for standard IEEE802.3 MDIO Clause 22 format. + * + * param base ENET peripheral base address. + * param phyAddr The PHY address. + * param phyReg The PHY register. Range from 0 ~ 31. + * param operation The write operation. + * param data The data written to PHY. + */ void ENET_StartSMIWrite(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg, enet_mii_write_t operation, uint32_t data) { uint32_t mmfr = 0; @@ -946,6 +1054,16 @@ void ENET_StartSMIWrite(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg, enet base->MMFR = mmfr; } +/*! + * brief Starts an SMI (Serial Management Interface) read command. + * + * Used for standard IEEE802.3 MDIO Clause 22 format. + * + * param base ENET peripheral base address. + * param phyAddr The PHY address. + * param phyReg The PHY register. Range from 0 ~ 31. + * param operation The read operation. + */ void ENET_StartSMIRead(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg, enet_mii_read_t operation) { uint32_t mmfr = 0; @@ -956,6 +1074,16 @@ void ENET_StartSMIRead(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg, enet_ } #if defined(FSL_FEATURE_ENET_HAS_EXTEND_MDIO) && FSL_FEATURE_ENET_HAS_EXTEND_MDIO +/*! + * brief Starts the extended IEEE802.3 Clause 45 MDIO format SMI write command. + * + * param base ENET peripheral base address. + * param phyAddr The PHY address. + * param phyReg The PHY register. For MDIO IEEE802.3 Clause 45, + * the phyReg is a 21-bits combination of the devaddr (5 bits device address) + * and the regAddr (16 bits phy register): phyReg = (devaddr << 16) | regAddr. + * param data The data written to PHY. + */ void ENET_StartExtC45SMIWrite(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg, uint32_t data) { uint32_t mmfr = 0; @@ -975,6 +1103,15 @@ void ENET_StartExtC45SMIWrite(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg base->MMFR = mmfr; } +/*! + * brief Starts the extended IEEE802.3 Clause 45 MDIO format SMI read command. + * + * param base ENET peripheral base address. + * param phyAddr The PHY address. + * param phyReg The PHY register. For MDIO IEEE802.3 Clause 45, + * the phyReg is a 21-bits combination of the devaddr (5 bits device address) + * and the regAddr (16 bits phy register): phyReg = (devaddr << 16) | regAddr. + */ void ENET_StartExtC45SMIRead(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg) { uint32_t mmfr = 0; @@ -995,6 +1132,26 @@ void ENET_StartExtC45SMIRead(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg) } #endif /* FSL_FEATURE_ENET_HAS_EXTEND_MDIO */ +/*! + * brief Gets the error statistics of a received frame for ENET single ring. + * + * This API must be called after the ENET_GetRxFrameSize and before the ENET_ReadFrame(). + * If the ENET_GetRxFrameSize returns kStatus_ENET_RxFrameError, + * the ENET_GetRxErrBeforeReadFrame can be used to get the exact error statistics. + * This is an example. + * code + * status = ENET_GetRxFrameSize(&g_handle, &length); + * if (status == kStatus_ENET_RxFrameError) + * { + * // Get the error information of the received frame. + * ENET_GetRxErrBeforeReadFrame(&g_handle, &eErrStatic); + * // update the receive buffer. + * ENET_ReadFrame(EXAMPLE_ENET, &g_handle, NULL, 0); + * } + * endcode + * param handle The ENET handler structure pointer. This is the same handler pointer used in the ENET_Init. + * param eErrorStatic The error statistics structure pointer. + */ void ENET_GetRxErrBeforeReadFrame(enet_handle_t *handle, enet_data_error_stats_t *eErrorStatic) { assert(handle); @@ -1070,6 +1227,22 @@ void ENET_GetRxErrBeforeReadFrame(enet_handle_t *handle, enet_data_error_stats_t } while (curBuffDescrip != handle->rxBdCurrent[0]); } +/*! +* brief Gets the size of the read frame for single ring. +* +* This function gets a received frame size from the ENET buffer descriptors. +* note The FCS of the frame is automatically removed by MAC and the size is the length without the FCS. +* After calling ENET_GetRxFrameSize, ENET_ReadFrame() should be called to update the +* receive buffers If the result is not "kStatus_ENET_RxFrameEmpty". +* +* param handle The ENET handler structure. This is the same handler pointer used in the ENET_Init. +* param length The length of the valid frame received. +* retval kStatus_ENET_RxFrameEmpty No frame received. Should not call ENET_ReadFrame to read frame. +* retval kStatus_ENET_RxFrameError Data error happens. ENET_ReadFrame should be called with NULL data +* and NULL length to update the receive buffers. +* retval kStatus_Success Receive a frame Successfully then the ENET_ReadFrame +* should be called with the right data buffer and the captured data length input. +*/ status_t ENET_GetRxFrameSize(enet_handle_t *handle, uint32_t *length) { assert(handle); @@ -1128,6 +1301,43 @@ status_t ENET_GetRxFrameSize(enet_handle_t *handle, uint32_t *length) return kStatus_ENET_RxFrameEmpty; } +/*! + * brief Reads a frame from the ENET device for single ring. + * This function reads a frame (both the data and the length) from the ENET buffer descriptors. + * The ENET_GetRxFrameSize should be used to get the size of the prepared data buffer. + * This is an example: + * code + * uint32_t length; + * enet_handle_t g_handle; + * //Get the received frame size firstly. + * status = ENET_GetRxFrameSize(&g_handle, &length); + * if (length != 0) + * { + * //Allocate memory here with the size of "length" + * uint8_t *data = memory allocate interface; + * if (!data) + * { + * ENET_ReadFrame(ENET, &g_handle, NULL, 0); + * //Add the console warning log. + * } + * else + * { + * status = ENET_ReadFrame(ENET, &g_handle, data, length); + * //Call stack input API to deliver the data to stack + * } + * } + * else if (status == kStatus_ENET_RxFrameError) + * { + * //Update the received buffer when a error frame is received. + * ENET_ReadFrame(ENET, &g_handle, NULL, 0); + * } + * endcode + * param base ENET peripheral base address. + * param handle The ENET handler structure. This is the same handler pointer used in the ENET_Init. + * param data The data buffer provided by user to store the frame which memory size should be at least "length". + * param length The size of the data buffer which is still the length of the received frame. + * return The execute status, successful or failure. + */ status_t ENET_ReadFrame(ENET_Type *base, enet_handle_t *handle, uint8_t *data, uint32_t length) { assert(handle); @@ -1163,19 +1373,19 @@ status_t ENET_ReadFrame(ENET_Type *base, enet_handle_t *handle, uint8_t *data, u } else { - /* A frame on one buffer or several receive buffers are both considered. */ +/* A frame on one buffer or several receive buffers are both considered. */ #if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET - address = MEMORY_ConvertMemoryMapAddress((uint32_t)curBuffDescrip->buffer,kMEMORY_DMA2Local); + address = MEMORY_ConvertMemoryMapAddress((uint32_t)curBuffDescrip->buffer, kMEMORY_DMA2Local); #else address = (uint32_t)curBuffDescrip->buffer; -#endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */ +#endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */ #if defined(FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL) && FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL /* Add the cache invalidate maintain. */ DCACHE_InvalidateByRange(address, handle->rxBuffSizeAlign[0]); -#endif /* FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL */ +#endif /* FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL */ #ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE enet_ptp_time_data_t ptpTimestamp; - bool isPtpEventMessage = false; + bool isPtpEventMessage = false; /* Parse the PTP message according to the header message. */ isPtpEventMessage = ENET_Ptp1588ParseFrame((uint8_t *)address, &ptpTimestamp, false); #endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ @@ -1231,15 +1441,15 @@ status_t ENET_ReadFrame(ENET_Type *base, enet_handle_t *handle, uint8_t *data, u /* Get the current buffer descriptor. */ curBuffDescrip = handle->rxBdCurrent[0]; - /* Add the cache invalidate maintain. */ +/* Add the cache invalidate maintain. */ #if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET - address = MEMORY_ConvertMemoryMapAddress((uint32_t)curBuffDescrip->buffer,kMEMORY_DMA2Local); + address = MEMORY_ConvertMemoryMapAddress((uint32_t)curBuffDescrip->buffer, kMEMORY_DMA2Local); #else address = (uint32_t)curBuffDescrip->buffer; -#endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */ -#if defined(FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL) && FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL +#endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */ +#if defined(FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL) && FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL DCACHE_InvalidateByRange(address, handle->rxBuffSizeAlign[0]); -#endif /* FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL */ +#endif /* FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL */ } } @@ -1286,6 +1496,22 @@ static void ENET_UpdateReadBuffers(ENET_Type *base, enet_handle_t *handle, uint3 } } +/*! + * brief Transmits an ENET frame for single ring. + * note The CRC is automatically appended to the data. Input the data + * to send without the CRC. + * + * + * param base ENET peripheral base address. + * param handle The ENET handler pointer. This is the same handler pointer used in the ENET_Init. + * param data The data buffer provided by user to be send. + * param length The length of the data to be send. + * retval kStatus_Success Send frame succeed. + * retval kStatus_ENET_TxFrameBusy Transmit buffer descriptor is busy under transmission. + * The transmit busy happens when the data send rate is over the MAC capacity. + * The waiting mechanism is recommended to be added after each call return with + * kStatus_ENET_TxFrameBusy. + */ status_t ENET_SendFrame(ENET_Type *base, enet_handle_t *handle, const uint8_t *data, uint32_t length) { assert(handle); @@ -1316,16 +1542,16 @@ status_t ENET_SendFrame(ENET_Type *base, enet_handle_t *handle, const uint8_t *d /* One transmit buffer is enough for one frame. */ if (handle->txBuffSizeAlign[0] >= length) { - /* Copy data to the buffer for uDMA transfer. */ +/* Copy data to the buffer for uDMA transfer. */ #if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET - address = MEMORY_ConvertMemoryMapAddress((uint32_t)curBuffDescrip->buffer,kMEMORY_DMA2Local); + address = MEMORY_ConvertMemoryMapAddress((uint32_t)curBuffDescrip->buffer, kMEMORY_DMA2Local); #else address = (uint32_t)curBuffDescrip->buffer; #endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */ memcpy((void *)address, data, length); #if defined(FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL) && FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL DCACHE_CleanByRange(address, length); -#endif /* FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL */ +#endif /* FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL */ /* Set data length. */ curBuffDescrip->length = length; #ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE @@ -1385,10 +1611,10 @@ status_t ENET_SendFrame(ENET_Type *base, enet_handle_t *handle, const uint8_t *d /* update the size left to be transmit. */ sizeleft = length - len; #if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET - address = MEMORY_ConvertMemoryMapAddress((uint32_t)curBuffDescrip->buffer,kMEMORY_DMA2Local); + address = MEMORY_ConvertMemoryMapAddress((uint32_t)curBuffDescrip->buffer, kMEMORY_DMA2Local); #else address = (uint32_t)curBuffDescrip->buffer; -#endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */ +#endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */ if (sizeleft > handle->txBuffSizeAlign[0]) { /* Data copy. */ @@ -1396,7 +1622,7 @@ status_t ENET_SendFrame(ENET_Type *base, enet_handle_t *handle, const uint8_t *d #if defined(FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL) && FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL /* Add the cache clean maintain. */ DCACHE_CleanByRange(address, handle->txBuffSizeAlign[0]); -#endif /* FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL */ +#endif /* FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL */ /* Data length update. */ curBuffDescrip->length = handle->txBuffSizeAlign[0]; len += handle->txBuffSizeAlign[0]; @@ -1408,15 +1634,14 @@ status_t ENET_SendFrame(ENET_Type *base, enet_handle_t *handle, const uint8_t *d } else { - memcpy((void *)address, data + len, sizeleft); #if defined(FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL) && FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL /* Add the cache clean maintain. */ DCACHE_CleanByRange(address, sizeleft); -#endif /* FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL */ +#endif /* FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL */ curBuffDescrip->length = sizeleft; /* Set Last buffer wrap flag. */ - curBuffDescrip->control |= ENET_BUFFDESCRIPTOR_TX_READY_MASK | ENET_BUFFDESCRIPTOR_TX_LAST_MASK; + curBuffDescrip->control |= ENET_BUFFDESCRIPTOR_TX_READY_MASK | ENET_BUFFDESCRIPTOR_TX_LAST_MASK; /* Active the transmit buffer descriptor. */ ENET_ActiveSend(base, 0); @@ -1433,6 +1658,17 @@ status_t ENET_SendFrame(ENET_Type *base, enet_handle_t *handle, const uint8_t *d } #if FSL_FEATURE_ENET_QUEUE > 1 +/*! + * brief Gets the error statistics of received frame for extended multi-ring. + * + * This API must be called after the ENET_GetRxFrameSizeMultiRing and before the ENET_ReadFrameMultiRing(). + * If the ENET_GetRxFrameSizeMultiRing returns kStatus_ENET_RxFrameError, + * the ENET_GetRxErrBeforeReadFrameMultiRing can be used to get the exact error statistics. + * + * param handle The ENET handler structure pointer. This is the same handler pointer used in the ENET_Init. + * param eErrorStatic The error statistics structure pointer. + * param ringId The ring index, range from 0 ~ FSL_FEATURE_ENET_QUEUE - 1. + */ void ENET_GetRxErrBeforeReadFrameMultiRing(enet_handle_t *handle, enet_data_error_stats_t *eErrorStatic, uint32_t ringId) @@ -1510,6 +1746,24 @@ void ENET_GetRxErrBeforeReadFrameMultiRing(enet_handle_t *handle, } while (curBuffDescrip != handle->rxBdCurrent[ringId]); } +/*! +* brief Gets the size of the read frame for extended mutli-ring. +* +* This function gets a received frame size from the ENET buffer descriptors. +* note The FCS of the frame is automatically removed by MAC and the size is the length without the FCS. +* After calling ENET_GetRxFrameSizeMultiRing, ENET_ReadFrameMultiRing() should be called to update the +* receive buffers If the result is not "kStatus_ENET_RxFrameEmpty". The usage is +* the same to the single ring, refer to ENET_GetRxFrameSize. +* +* param handle The ENET handler structure. This is the same handler pointer used in the ENET_Init. +* param length The length of the valid frame received. +* param ringId The ring index or ring number; +* retval kStatus_ENET_RxFrameEmpty No frame received. Should not call ENET_ReadFrameMultiRing to read frame. +* retval kStatus_ENET_RxFrameError Data error happens. ENET_ReadFrameMultiRing should be called with NULL data +* and NULL length to update the receive buffers. +* retval kStatus_Success Receive a frame Successfully then the ENET_ReadFrame +* should be called with the right data buffer and the captured data length input. +*/ status_t ENET_GetRxFrameSizeMultiRing(enet_handle_t *handle, uint32_t *length, uint32_t ringId) { assert(handle); @@ -1534,7 +1788,7 @@ status_t ENET_GetRxFrameSizeMultiRing(enet_handle_t *handle, uint32_t *length, u if ((!(curBuffDescrip->control & ENET_BUFFDESCRIPTOR_RX_EMPTY_MASK)) && (!curBuffDescrip->length)) { return kStatus_ENET_RxFrameError; - } + } /* Find the last buffer descriptor. */ if ((curBuffDescrip->control & validLastMask) == ENET_BUFFDESCRIPTOR_RX_LAST_MASK) { @@ -1566,6 +1820,20 @@ status_t ENET_GetRxFrameSizeMultiRing(enet_handle_t *handle, uint32_t *length, u return kStatus_ENET_RxFrameEmpty; } +/*! + * brief Reads a frame from the ENET device for multi-ring. + * + * This function reads a frame (both the data and the length) from the ENET buffer descriptors. + * The ENET_GetRxFrameSizeMultiRing should be used to get the size of the prepared data buffer. + * This usage is the same as the single ring, refer to ENET_ReadFrame. + + * param base ENET peripheral base address. + * param handle The ENET handler structure. This is the same handler pointer used in the ENET_Init. + * param data The data buffer provided by user to store the frame which memory size should be at least "length". + * param length The size of the data buffer which is still the length of the received frame. + * param ringId The ring index or ring number; + * return The execute status, successful or failure. + */ status_t ENET_ReadFrameMultiRing( ENET_Type *base, enet_handle_t *handle, uint8_t *data, uint32_t length, uint32_t ringId) { @@ -1602,9 +1870,9 @@ status_t ENET_ReadFrameMultiRing( } else { - /* A frame on one buffer or several receive buffers are both considered. */ +/* A frame on one buffer or several receive buffers are both considered. */ #if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET - address = MEMORY_ConvertMemoryMapAddress((uint32_t)curBuffDescrip->buffer,kMEMORY_DMA2Local); + address = MEMORY_ConvertMemoryMapAddress((uint32_t)curBuffDescrip->buffer, kMEMORY_DMA2Local); #else address = (uint32_t)curBuffDescrip->buffer; #endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */ @@ -1663,7 +1931,6 @@ status_t ENET_ReadFrameMultiRing( memcpy(data + offset, (void *)address, handle->rxBuffSizeAlign[ringId]); offset += handle->rxBuffSizeAlign[ringId]; - /* Updates the receive buffer descriptors. */ ENET_UpdateReadBuffers(base, handle, ringId); } @@ -1672,7 +1939,7 @@ status_t ENET_ReadFrameMultiRing( curBuffDescrip = handle->rxBdCurrent[ringId]; #if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET - address = MEMORY_ConvertMemoryMapAddress((uint32_t)curBuffDescrip->buffer,kMEMORY_DMA2Local); + address = MEMORY_ConvertMemoryMapAddress((uint32_t)curBuffDescrip->buffer, kMEMORY_DMA2Local); #else address = (uint32_t)curBuffDescrip->buffer; #endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */ @@ -1686,7 +1953,27 @@ status_t ENET_ReadFrameMultiRing( return kStatus_ENET_RxFrameFail; } - +/*! + * brief Transmits an ENET frame for extended multi-ring. + * note The CRC is automatically appended to the data. Input the data + * to send without the CRC. + * + * In this API, multiple-ring are mainly used for extended avb frames are supported. + * The transmit scheme for avb frames is the credit-based scheme, the AVB class A, AVB class B + * and the non-AVB frame are transmitted in ring 1, ring 2 and ring 0 independently. + * So application should care about the transmit ring index when use multiple-ring transmission. + * + * param base ENET peripheral base address. + * param handle The ENET handler pointer. This is the same handler pointer used in the ENET_Init. + * param data The data buffer provided by user to be send. + * param length The length of the data to be send. + * param ringId The ring index for transmission. + * retval kStatus_Success Send frame succeed. + * retval kStatus_ENET_TxFrameBusy Transmit buffer descriptor is busy under transmission. + * The transmit busy happens when the data send rate is over the MAC capacity. + * The waiting mechanism is recommended to be added after each call return with + * kStatus_ENET_TxFrameBusy. + */ status_t ENET_SendFrameMultiRing( ENET_Type *base, enet_handle_t *handle, uint8_t *data, uint32_t length, uint32_t ringId) { @@ -1719,9 +2006,9 @@ status_t ENET_SendFrameMultiRing( /* One transmit buffer is enough for one frame. */ if (handle->txBuffSizeAlign[ringId] >= length) { - /* Copy data to the buffer for uDMA transfer. */ +/* Copy data to the buffer for uDMA transfer. */ #if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET - address = MEMORY_ConvertMemoryMapAddress((uint32_t)curBuffDescrip->buffer,kMEMORY_DMA2Local); + address = MEMORY_ConvertMemoryMapAddress((uint32_t)curBuffDescrip->buffer, kMEMORY_DMA2Local); #else address = (uint32_t)curBuffDescrip->buffer; #endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */ @@ -1792,14 +2079,14 @@ status_t ENET_SendFrameMultiRing( /* update the size left to be transmit. */ sizeleft = length - len; #if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET - address = MEMORY_ConvertMemoryMapAddress((uint32_t)curBuffDescrip->buffer,kMEMORY_DMA2Local); + address = MEMORY_ConvertMemoryMapAddress((uint32_t)curBuffDescrip->buffer, kMEMORY_DMA2Local); #else address = (uint32_t)curBuffDescrip->buffer; #endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */ if (sizeleft > handle->txBuffSizeAlign[ringId]) { /* Data copy. */ - memcpy((void*)address, data + len, handle->txBuffSizeAlign[ringId]); + memcpy((void *)address, data + len, handle->txBuffSizeAlign[ringId]); #if defined(FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL) && FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL /* Add the cache clean maintain. */ DCACHE_CleanByRange(address, handle->txBuffSizeAlign[ringId]); @@ -1816,7 +2103,6 @@ status_t ENET_SendFrameMultiRing( } else { - memcpy((void *)address, data + len, sizeleft); #if defined(FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL) && FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL /* Add the cache clean maintain. */ @@ -1841,6 +2127,12 @@ status_t ENET_SendFrameMultiRing( } #endif /* FSL_FEATURE_ENET_QUEUE > 1 */ +/*! + * brief Adds the ENET device to a multicast group. + * + * param base ENET peripheral base address. + * param address The six-byte multicast group address which is provided by application. + */ void ENET_AddMulticastGroup(ENET_Type *base, uint8_t *address) { assert(address); @@ -1880,6 +2172,12 @@ void ENET_AddMulticastGroup(ENET_Type *base, uint8_t *address) } } +/*! + * brief Moves the ENET device from a multicast group. + * + * param base ENET peripheral base address. + * param address The six-byte multicast group address which is provided by application. + */ void ENET_LeaveMulticastGroup(ENET_Type *base, uint8_t *address) { assert(address); @@ -1920,6 +2218,19 @@ void ENET_LeaveMulticastGroup(ENET_Type *base, uint8_t *address) } #ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE +/*! + * brief Gets the ENET transmit frame statistics after the data send for single ring. + * + * This interface gets the error statistics of the transmit frame. + * Because the error information is reported by the uDMA after the data delivery, this interface + * should be called after the data transmit API. It is recommended to call this function on + * transmit interrupt handler. After calling the ENET_SendFrame, the + * transmit interrupt notifies the transmit completion. + * + * param handle The PTP handler pointer. This is the same handler pointer used in the ENET_Init. + * param eErrorStatic The error statistics structure pointer. + * return The execute status. + */ status_t ENET_GetTxErrAfterSendFrame(enet_handle_t *handle, enet_data_error_stats_t *eErrorStatic) { assert(handle); @@ -1931,8 +2242,8 @@ status_t ENET_GetTxErrAfterSendFrame(enet_handle_t *handle, enet_data_error_stat do { /* Get the current dirty transmit buffer descriptor. */ - control = handle->txBdDirtyStatic[0]->control; - controlExt = handle->txBdDirtyStatic[0]->controlExtend0; + control = handle->txBdDirtyStatic[0]->control; + controlExt = handle->txBdDirtyStatic[0]->controlExtend0; /* Get the control status data, If the buffer descriptor has not been processed break out. */ if (control & ENET_BUFFDESCRIPTOR_TX_READY_MASK) @@ -1985,9 +2296,23 @@ status_t ENET_GetTxErrAfterSendFrame(enet_handle_t *handle, enet_data_error_stat return kStatus_ENET_TxFrameFail; } -#if FSL_FEATURE_ENET_QUEUE > 1 -status_t ENET_GetTxErrAfterSendFrameMultiRing(enet_handle_t *handle, enet_data_error_stats_t *eErrorStatic, - uint32_t ringId) +#if FSL_FEATURE_ENET_QUEUE > 1 +/*! + * brief Gets the ENET transmit frame statistics after the data send for extended multi-ring. + * + * This interface gets the error statistics of the transmit frame. + * Because the error information is reported by the uDMA after the data delivery, this interface + * should be called after the data transmit API and shall be called by transmit interrupt handler. + * After calling the ENET_SendFrame, the transmit interrupt notifies the transmit completion. + * + * param handle The PTP handler pointer. This is the same handler pointer used in the ENET_Init. + * param eErrorStatic The error statistics structure pointer. + * param ringId The ring index. + * return The execute status. + */ +status_t ENET_GetTxErrAfterSendFrameMultiRing(enet_handle_t *handle, + enet_data_error_stats_t *eErrorStatic, + uint32_t ringId) { assert(handle); assert(eErrorStatic); @@ -2069,15 +2394,15 @@ static bool ENET_Ptp1588ParseFrame(const uint8_t *data, enet_ptp_time_data_t *pt * Add Double vlan tag check for receiving extended QIN vlan frame. */ if (*(uint16_t *)(buffer + ENET_PTP1588_ETHL2_PACKETTYPE_OFFSET) == (ENET_HTONS(ENET_8021QVLAN) #if defined(FSL_FEATUR_ENET_HAS_AVB) && FSL_FEATURE_HAS_AVB - || ENET_HTONS(ENET_8021QSVLAN) + || ENET_HTONS(ENET_8021QSVLAN) #endif /* FSL_FEATURE_ENET_HAS_AVB */ - )) + )) { buffer += ENET_FRAME_VLAN_TAGLEN; #if defined(FSL_FEATUR_ENET_HAS_AVB) && FSL_FEATURE_HAS_AVB if (*(uint16_t *)(buffer + ENET_PTP1588_ETHL2_PACKETTYPE_OFFSET) == ENET_HTONS(ENET_8021QVLAN) { - buffer += ENET_FRAME_VLAN_TAGLEN; + buffer += ENET_FRAME_VLAN_TAGLEN; } #endif /* FSL_FEATURE_ENET_HAS_AVB */ } @@ -2150,6 +2475,22 @@ static bool ENET_Ptp1588ParseFrame(const uint8_t *data, enet_ptp_time_data_t *pt return isPtpMsg; } +/*! + * brief Configures the ENET PTP IEEE 1588 feature with the basic configuration. + * The function sets the clock for PTP 1588 timer and enables + * time stamp interrupts and transmit interrupts for PTP 1588 features. + * This API should be called when the 1588 feature is enabled + * or the ENET_ENHANCEDBUFFERDESCRIPTOR_MODE is defined. + * ENET_Init should be called before calling this API. + * + * note The PTP 1588 time-stamp second increase though time-stamp interrupt handler + * and the transmit time-stamp store is done through transmit interrupt handler. + * As a result, the TS interrupt and TX interrupt are enabled when you call this API. + * + * param base ENET peripheral base address. + * param handle ENET handler pointer. + * param ptpConfig The ENET PTP1588 configuration. + */ void ENET_Ptp1588Configure(ENET_Type *base, enet_handle_t *handle, enet_ptp_config_t *ptpConfig) { assert(handle); @@ -2195,6 +2536,14 @@ void ENET_Ptp1588Configure(ENET_Type *base, enet_handle_t *handle, enet_ptp_conf EnableIRQ(s_enetTxIrqId[instance]); } +/*! + * brief Starts the ENET PTP 1588 Timer. + * This function is used to initialize the PTP timer. After the PTP starts, + * the PTP timer starts running. + * + * param base ENET peripheral base address. + * param ptpClkSrc The clock source of the PTP timer. + */ void ENET_Ptp1588StartTimer(ENET_Type *base, uint32_t ptpClkSrc) { /* Restart PTP 1588 timer, master clock. */ @@ -2207,6 +2556,13 @@ void ENET_Ptp1588StartTimer(ENET_Type *base, uint32_t ptpClkSrc) base->ATCR = ENET_ATCR_PEREN_MASK | ENET_ATCR_PINPER_MASK | ENET_ATCR_EN_MASK; } +/*! + * brief Gets the current ENET time from the PTP 1588 timer. + * + * param base ENET peripheral base address. + * param handle The ENET state pointer. This is the same state pointer used in the ENET_Init. + * param ptpTime The PTP timer structure. + */ void ENET_Ptp1588GetTimer(ENET_Type *base, enet_handle_t *handle, enet_ptp_time_t *ptpTime) { assert(handle); @@ -2236,6 +2592,13 @@ void ENET_Ptp1588GetTimer(ENET_Type *base, enet_handle_t *handle, enet_ptp_time_ EnableGlobalIRQ(primask); } +/*! + * brief Sets the ENET PTP 1588 timer to the assigned time. + * + * param base ENET peripheral base address. + * param handle The ENET state pointer. This is the same state pointer used in the ENET_Init. + * param ptpTime The timer to be set to the PTP timer. + */ void ENET_Ptp1588SetTimer(ENET_Type *base, enet_handle_t *handle, enet_ptp_time_t *ptpTime) { assert(handle); @@ -2254,6 +2617,17 @@ void ENET_Ptp1588SetTimer(ENET_Type *base, enet_handle_t *handle, enet_ptp_time_ EnableGlobalIRQ(primask); } +/*! + * brief Adjusts the ENET PTP 1588 timer. + * + * param base ENET peripheral base address. + * param corrIncrease The correction increment value. This value is added every time the correction + * timer expires. A value less than the PTP timer frequency(1/ptpClkSrc) slows down the timer, + * a value greater than the 1/ptpClkSrc speeds up the timer. + * param corrPeriod The PTP timer correction counter wrap-around value. This defines after how + * many timer clock the correction counter should be reset and trigger a correction + * increment on the timer. A value of 0 disables the correction counter and no correction occurs. + */ void ENET_Ptp1588AdjustTimer(ENET_Type *base, uint32_t corrIncrease, uint32_t corrPeriod) { /* Set correction for PTP timer increment. */ @@ -2410,16 +2784,16 @@ static status_t ENET_StoreTxFrameTime(ENET_Type *base, enet_handle_t *handle, ui return kStatus_ENET_TxFrameBusy; } - /* Parse the PTP message. */ +/* Parse the PTP message. */ #if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET - address = MEMORY_ConvertMemoryMapAddress((uint32_t)curBuffDescrip->buffer,kMEMORY_DMA2Local); + address = MEMORY_ConvertMemoryMapAddress((uint32_t)curBuffDescrip->buffer, kMEMORY_DMA2Local); #else address = (uint32_t)curBuffDescrip->buffer; #endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */ isPtpEventMessage = ENET_Ptp1588ParseFrame((uint8_t *)address, &ptpTimeData, false); if (isPtpEventMessage) { - /* Only store tx timestamp for ptp event message. */ + /* Only store tx timestamp for ptp event message. */ do { /* Increase current buffer descriptor to the next one. */ @@ -2486,11 +2860,23 @@ static status_t ENET_StoreTxFrameTime(ENET_Type *base, enet_handle_t *handle, ui else { handle->txBdDirtyTime[ringId]++; - } + } } return kStatus_Success; } +/*! + * brief Gets the time stamp of the transmit frame. + * + * This function is used for PTP stack to get the timestamp captured by the ENET driver. + * + * param handle The ENET handler pointer.This is the same state pointer used in + * ENET_Init. + * param ptpTimeData The special PTP timestamp data for search the receive timestamp. + * retval kStatus_Success Get 1588 timestamp success. + * retval kStatus_ENET_PtpTsRingEmpty 1588 timestamp ring empty. + * retval kStatus_ENET_PtpTsRingFull 1588 timestamp ring full. + */ status_t ENET_GetTxFrameTime(enet_handle_t *handle, enet_ptp_time_data_t *ptpTimeData) { assert(handle); @@ -2499,6 +2885,18 @@ status_t ENET_GetTxFrameTime(enet_handle_t *handle, enet_ptp_time_data_t *ptpTim return ENET_Ptp1588SearchTimeRing(&handle->txPtpTsDataRing, ptpTimeData); } +/*! + * brief Gets the time stamp of the received frame. + * + * This function is used for PTP stack to get the timestamp captured by the ENET driver. + * + * param handle The ENET handler pointer.This is the same state pointer used in + * ENET_Init. + * param ptpTimeData The special PTP timestamp data for search the receive timestamp. + * retval kStatus_Success Get 1588 timestamp success. + * retval kStatus_ENET_PtpTsRingEmpty 1588 timestamp ring empty. + * retval kStatus_ENET_PtpTsRingFull 1588 timestamp ring full. + */ status_t ENET_GetRxFrameTime(enet_handle_t *handle, enet_ptp_time_data_t *ptpTimeData) { assert(handle); @@ -2508,6 +2906,21 @@ status_t ENET_GetRxFrameTime(enet_handle_t *handle, enet_ptp_time_data_t *ptpTim } #if defined(FSL_FEATURE_ENET_HAS_AVB) && FSL_FEATURE_ENET_HAS_AVB +/*! + * brief Sets the ENET AVB feature. + * + * ENET AVB feature configuration, set the Receive classification match and transmit + * bandwidth. This API is called when the AVB feature is required. + * + * Note: The AVB frames transmission scheme is credit-based tx scheme and it's only supported + * with the Enhanced buffer descriptors. so the AVB configuration should only done with + * Enhanced buffer descriptor. so when the AVB feature is required, please make sure the + * the "ENET_ENHANCEDBUFFERDESCRIPTOR_MODE" is defined. + * + * param base ENET peripheral base address. + * param handle ENET handler pointer. + * param config The ENET AVB feature configuration structure. + */ void ENET_AVBConfigure(ENET_Type *base, enet_handle_t *handle, const enet_avb_config_t *config) { assert(config); @@ -2533,8 +2946,20 @@ void ENET_AVBConfigure(ENET_Type *base, enet_handle_t *handle, const enet_avb_co #endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ #if FSL_FEATURE_ENET_QUEUE > 1 +/*! + * brief The transmit IRQ handler. + * + * param base ENET peripheral base address. + * param handle The ENET handler pointer. + */ void ENET_TransmitIRQHandler(ENET_Type *base, enet_handle_t *handle, uint32_t ringId) #else +/*! + * brief The transmit IRQ handler. + * + * param base ENET peripheral base address. + * param handle The ENET handler pointer. + */ void ENET_TransmitIRQHandler(ENET_Type *base, enet_handle_t *handle) #endif /* FSL_FEATURE_ENET_QUEUE > 1 */ { @@ -2586,8 +3011,20 @@ void ENET_TransmitIRQHandler(ENET_Type *base, enet_handle_t *handle) } #if FSL_FEATURE_ENET_QUEUE > 1 +/*! + * brief The receive IRQ handler. + * + * param base ENET peripheral base address. + * param handle The ENET handler pointer. + */ void ENET_ReceiveIRQHandler(ENET_Type *base, enet_handle_t *handle, uint32_t ringId) #else +/*! + * brief The receive IRQ handler. + * + * param base ENET peripheral base address. + * param handle The ENET handler pointer. + */ void ENET_ReceiveIRQHandler(ENET_Type *base, enet_handle_t *handle) #endif /* FSL_FEATURE_ENET_QUEUE > 1 */ { @@ -2626,6 +3063,12 @@ void ENET_ReceiveIRQHandler(ENET_Type *base, enet_handle_t *handle) } } +/*! + * brief Some special IRQ handler including the error, mii, wakeup irq handler. + * + * param base ENET peripheral base address. + * param handle The ENET handler pointer. + */ void ENET_ErrorIRQHandler(ENET_Type *base, enet_handle_t *handle) { assert(handle); @@ -2665,14 +3108,20 @@ void ENET_ErrorIRQHandler(ENET_Type *base, enet_handle_t *handle) #endif /* FSL_FEATURE_ENET_QUEUE > 1 */ } } - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ #if defined __CORTEX_M && (__CORTEX_M == 4U) __DSB(); #endif } #ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE +/*! + * brief The IEEE 1588 PTP time stamp interrupt handler. + * + * param base ENET peripheral base address. + * param handle The ENET state pointer. This is the same state pointer used in the ENET_Init. + */ void ENET_Ptp1588TimerIRQHandler(ENET_Type *base, enet_handle_t *handle) { assert(handle); @@ -2710,14 +3159,21 @@ void ENET_Ptp1588TimerIRQHandler(ENET_Type *base, enet_handle_t *handle) #endif /* FSL_FEATURE_ENET_QUEUE > 1 */ } } - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ #if defined __CORTEX_M && (__CORTEX_M == 4U) __DSB(); #endif } #endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ +/*! + * brief the common IRQ handler for the tx/rx/error etc irq handler. + * + * This is used for the combined tx/rx/error interrupt for single/mutli-ring (frame 0). + * + * param base ENET peripheral base address. + */ void ENET_CommonFrame0IRQHandler(ENET_Type *base) { uint32_t event = base->EIR; @@ -2749,14 +3205,21 @@ void ENET_CommonFrame0IRQHandler(ENET_Type *base) { s_enetErrIsr(base, s_ENETHandle[instance]); } - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ #if defined __CORTEX_M && (__CORTEX_M == 4U) __DSB(); #endif } #if FSL_FEATURE_ENET_QUEUE > 1 +/*! + * brief the common IRQ handler for the tx/rx irq handler. + * + * This is used for the combined tx/rx interrupt for multi-ring (frame 1). + * + * param base ENET peripheral base address. + */ void ENET_CommonFrame1IRQHandler(ENET_Type *base) { uint32_t event = base->EIR; @@ -2771,13 +3234,20 @@ void ENET_CommonFrame1IRQHandler(ENET_Type *base) { s_enetRxIsr(base, s_ENETHandle[instance], 1); } - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ #if defined __CORTEX_M && (__CORTEX_M == 4U) __DSB(); #endif } +/*! + * brief the common IRQ handler for the tx/rx irq handler. + * + * This is used for the combined tx/rx interrupt for multi-ring (frame 2). + * + * param base ENET peripheral base address. + */ void ENET_CommonFrame2IRQHandler(ENET_Type *base) { uint32_t event = base->EIR; @@ -2792,8 +3262,8 @@ void ENET_CommonFrame2IRQHandler(ENET_Type *base) { s_enetRxIsr(base, s_ENETHandle[instance], 2); } - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ #if defined __CORTEX_M && (__CORTEX_M == 4U) __DSB(); #endif @@ -2804,8 +3274,8 @@ void ENET_CommonFrame2IRQHandler(ENET_Type *base) void ENET_Transmit_IRQHandler(void) { s_enetTxIsr(ENET, s_ENETHandle[0]); - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ #if defined __CORTEX_M && (__CORTEX_M == 4U) __DSB(); #endif @@ -2814,8 +3284,8 @@ void ENET_Transmit_IRQHandler(void) void ENET_Receive_IRQHandler(void) { s_enetRxIsr(ENET, s_ENETHandle[0]); - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ #if defined __CORTEX_M && (__CORTEX_M == 4U) __DSB(); #endif @@ -2824,8 +3294,8 @@ void ENET_Receive_IRQHandler(void) void ENET_Error_IRQHandler(void) { s_enetErrIsr(ENET, s_ENETHandle[0]); - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ #if defined __CORTEX_M && (__CORTEX_M == 4U) __DSB(); #endif @@ -2834,8 +3304,8 @@ void ENET_Error_IRQHandler(void) void ENET_1588_Timer_IRQHandler(void) { s_enetTsIsr(ENET, s_ENETHandle[0]); - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ #if defined __CORTEX_M && (__CORTEX_M == 4U) __DSB(); #endif @@ -2848,9 +3318,9 @@ void ENET_DriverIRQHandler(void) exception return operation might vector to incorrect interrupt */ #if defined __CORTEX_M && (__CORTEX_M == 4U) __DSB(); -#endif - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ +#endif +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ #if defined __CORTEX_M && (__CORTEX_M == 4U) __DSB(); #endif @@ -2858,13 +3328,12 @@ void ENET_DriverIRQHandler(void) #endif - -#if defined(ENET1) +#if defined(ENET1) void ENET1_DriverIRQHandler(void) { ENET_CommonFrame0IRQHandler(ENET1); - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ #if defined __CORTEX_M && (__CORTEX_M == 4U) __DSB(); #endif @@ -2875,21 +3344,20 @@ void ENET1_DriverIRQHandler(void) void ENET2_DriverIRQHandler(void) { ENET_CommonFrame0IRQHandler(ENET2); - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ #if defined __CORTEX_M && (__CORTEX_M == 4U) __DSB(); #endif } #endif - -#if defined(CONNECTIVITY__ENET0) +#if defined(CONNECTIVITY__ENET0) void CONNECTIVITY_ENET0_FRAME0_EVENT_INT_DriverIRQHandler(void) { ENET_CommonFrame0IRQHandler(CONNECTIVITY__ENET0); - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ #if defined __CORTEX_M && (__CORTEX_M == 4U) __DSB(); #endif @@ -2898,8 +3366,8 @@ void CONNECTIVITY_ENET0_FRAME0_EVENT_INT_DriverIRQHandler(void) void CONNECTIVITY_ENET0_FRAME1_INT_DriverIRQHandler(void) { ENET_CommonFrame1IRQHandler(CONNECTIVITY__ENET0); - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ #if defined __CORTEX_M && (__CORTEX_M == 4U) __DSB(); #endif @@ -2907,8 +3375,8 @@ void CONNECTIVITY_ENET0_FRAME1_INT_DriverIRQHandler(void) void CONNECTIVITY_ENET0_FRAME2_INT_DriverIRQHandler(void) { ENET_CommonFrame2IRQHandler(CONNECTIVITY__ENET0); - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ #if defined __CORTEX_M && (__CORTEX_M == 4U) __DSB(); #endif @@ -2919,8 +3387,8 @@ void CONNECTIVITY_ENET0_FRAME2_INT_DriverIRQHandler(void) void CONNECTIVITY_ENET1_FRAME0_EVENT_INT_DriverIRQHandler(void) { ENET_CommonFrame0IRQHandler(CONNECTIVITY__ENET1); - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ #if defined __CORTEX_M && (__CORTEX_M == 4U) __DSB(); #endif @@ -2929,8 +3397,8 @@ void CONNECTIVITY_ENET1_FRAME0_EVENT_INT_DriverIRQHandler(void) void CONNECTIVITY_ENET1_FRAME1_INT_DriverIRQHandler(void) { ENET_CommonFrame1IRQHandler(CONNECTIVITY__ENET1); - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ #if defined __CORTEX_M && (__CORTEX_M == 4U) __DSB(); #endif @@ -2938,12 +3406,11 @@ void CONNECTIVITY_ENET1_FRAME1_INT_DriverIRQHandler(void) void CONNECTIVITY_ENET1_FRAME2_INT_DriverIRQHandler(void) { ENET_CommonFrame2IRQHandler(CONNECTIVITY__ENET1); - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ #if defined __CORTEX_M && (__CORTEX_M == 4U) __DSB(); #endif } #endif #endif - diff --git a/ext/hal/nxp/mcux/drivers/imx/fsl_ewm.c b/ext/hal/nxp/mcux/drivers/imx/fsl_ewm.c index a8ca2412ed3..28dda267466 100644 --- a/ext/hal/nxp/mcux/drivers/imx/fsl_ewm.c +++ b/ext/hal/nxp/mcux/drivers/imx/fsl_ewm.c @@ -2,7 +2,7 @@ * Copyright (c) 2015, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP * All rights reserved. - * + * * SPDX-License-Identifier: BSD-3-Clause */ @@ -13,11 +13,29 @@ #define FSL_COMPONENT_ID "platform.drivers.ewm" #endif - /******************************************************************************* * Code ******************************************************************************/ +/*! + * brief Initializes the EWM peripheral. + * + * This function is used to initialize the EWM. After calling, the EWM + * runs immediately according to the configuration. + * Note that, except for the interrupt enable control bit, other control bits and registers are write once after a + * CPU reset. Modifying them more than once generates a bus transfer error. + * + * This is an example. + * code + * ewm_config_t config; + * EWM_GetDefaultConfig(&config); + * config.compareHighValue = 0xAAU; + * EWM_Init(ewm_base,&config); + * endcode + * + * param base EWM peripheral base address + * param config The configuration of the EWM +*/ void EWM_Init(EWM_Type *base, const ewm_config_t *config) { assert(config); @@ -25,7 +43,7 @@ void EWM_Init(EWM_Type *base, const ewm_config_t *config) uint32_t value = 0U; #if !((defined(FSL_FEATURE_SOC_PCC_COUNT) && FSL_FEATURE_SOC_PCC_COUNT) && \ - (defined(FSL_FEATURE_PCC_SUPPORT_EWM_CLOCK_REMOVE) && FSL_FEATURE_PCC_SUPPORT_EWM_CLOCK_REMOVE)) + (defined(FSL_FEATURE_PCC_SUPPORT_EWM_CLOCK_REMOVE) && FSL_FEATURE_PCC_SUPPORT_EWM_CLOCK_REMOVE)) #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) CLOCK_EnableClock(kCLOCK_Ewm0); #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ @@ -45,21 +63,50 @@ void EWM_Init(EWM_Type *base, const ewm_config_t *config) base->CTRL = value; } +/*! + * brief Deinitializes the EWM peripheral. + * + * This function is used to shut down the EWM. + * + * param base EWM peripheral base address +*/ void EWM_Deinit(EWM_Type *base) { EWM_DisableInterrupts(base, kEWM_InterruptEnable); #if !((defined(FSL_FEATURE_SOC_PCC_COUNT) && FSL_FEATURE_SOC_PCC_COUNT) && \ - (defined(FSL_FEATURE_PCC_SUPPORT_EWM_CLOCK_REMOVE) && FSL_FEATURE_PCC_SUPPORT_EWM_CLOCK_REMOVE)) + (defined(FSL_FEATURE_PCC_SUPPORT_EWM_CLOCK_REMOVE) && FSL_FEATURE_PCC_SUPPORT_EWM_CLOCK_REMOVE)) #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) CLOCK_DisableClock(kCLOCK_Ewm0); #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ #endif /* FSL_FEATURE_PCC_SUPPORT_EWM_CLOCK_REMOVE */ } +/*! + * brief Initializes the EWM configuration structure. + * + * This function initializes the EWM configuration structure to default values. The default + * values are as follows. + * code + * ewmConfig->enableEwm = true; + * ewmConfig->enableEwmInput = false; + * ewmConfig->setInputAssertLogic = false; + * ewmConfig->enableInterrupt = false; + * ewmConfig->ewm_lpo_clock_source_t = kEWM_LpoClockSource0; + * ewmConfig->prescaler = 0; + * ewmConfig->compareLowValue = 0; + * ewmConfig->compareHighValue = 0xFEU; + * endcode + * + * param config Pointer to the EWM configuration structure. + * see ewm_config_t + */ void EWM_GetDefaultConfig(ewm_config_t *config) { assert(config); + /* Initializes the configure structure to zero. */ + memset(config, 0, sizeof(*config)); + config->enableEwm = true; config->enableEwmInput = false; config->setInputAssertLogic = false; @@ -74,6 +121,13 @@ void EWM_GetDefaultConfig(ewm_config_t *config) config->compareHighValue = 0xFEU; } +/*! + * brief Services the EWM. + * + * This function resets the EWM counter to zero. + * + * param base EWM peripheral base address +*/ void EWM_Refresh(EWM_Type *base) { uint32_t primaskValue = 0U; diff --git a/ext/hal/nxp/mcux/drivers/imx/fsl_flexcan.c b/ext/hal/nxp/mcux/drivers/imx/fsl_flexcan.c index fe78b8ed7ec..5ce709ddbee 100644 --- a/ext/hal/nxp/mcux/drivers/imx/fsl_flexcan.c +++ b/ext/hal/nxp/mcux/drivers/imx/fsl_flexcan.c @@ -17,6 +17,24 @@ #define FSL_COMPONENT_ID "platform.drivers.flexcan" #endif +#if (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_6032) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_6032) +/*! @name DBG1 - Debug 1 register */ +#if !(defined(CAN_DBG1_CFSM_MASK) && defined(CAN_DBG1_CBN_MASK)) +#define CAN_DBG1_CFSM_MASK (0x7FU) +#define CAN_DBG1_CFSM_SHIFT (0U) +#define CAN_DBG1_CFSM(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBG1_CFSM_SHIFT)) & CAN_DBG1_CFSM_MASK) +#define CAN_DBG1_CBN_MASK (0x3FF0000U) +#define CAN_DBG1_CBN_SHIFT (16U) +#define CAN_DBG1_CBN(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBG1_CBN_SHIFT)) & CAN_DBG1_CBN_MASK) +#endif + +#define OFFSET_DBG1 (0x58U) +#define RXINTERMISSION (CAN_DBG1_CFSM(0x2f)) +#define TXINTERMISSION (CAN_DBG1_CFSM(0x14)) +#define BUSIDLE (CAN_DBG1_CFSM(0x02)) +#define CBN_VALUE3 (CAN_DBG1_CBN(0x03)) +#define DELAY_BUSIDLE (200) +#endif /*! @brief FlexCAN Internal State. */ enum _flexcan_state @@ -92,7 +110,8 @@ static void FLEXCAN_ExitFreezeMode(CAN_Type *base); static bool FLEXCAN_IsMbOccupied(CAN_Type *base, uint8_t mbIdx); #endif -#if (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) +#if ((defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) || \ + (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5829) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5829)) /*! * @brief Get the first valid Message buffer ID of give FlexCAN instance. * @@ -151,7 +170,10 @@ static void FLEXCAN_SetBaudRate(CAN_Type *base, * @param baudRateFD_Bps FD frame Baud Rate in Bps. * @param timingConfig FlexCAN timingConfig. */ -static void FLEXCAN_SetFDBaudRate(CAN_Type *base, uint32_t sourceClock_Hz, uint32_t baudRateFD_Bps, flexcan_timing_config_t timingConfig); +static void FLEXCAN_SetFDBaudRate(CAN_Type *base, + uint32_t sourceClock_Hz, + uint32_t baudRateFD_Bps, + flexcan_timing_config_t timingConfig); /*! * @brief Get Mailbox offset number by dword. @@ -203,6 +225,12 @@ static flexcan_isr_t s_flexcanIsr; * Code ******************************************************************************/ +/*! + * brief Get the FlexCAN instance from peripheral base address. + * + * param base FlexCAN peripheral base address. + * return FlexCAN instance. + */ uint32_t FLEXCAN_GetInstance(CAN_Type *base) { uint32_t instance; @@ -223,14 +251,54 @@ uint32_t FLEXCAN_GetInstance(CAN_Type *base) static void FLEXCAN_EnterFreezeMode(CAN_Type *base) { +#if (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_9595) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_9595) + uint32_t u32TempMCR = 0U; + uint32_t u32TimeoutCount = 0U; +#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) + uint32_t u32TempIMASK2 = 0U; +#endif + uint32_t u32TempIMASK1 = 0U; +#endif /* Set Freeze, Halt bits. */ base->MCR |= CAN_MCR_FRZ_MASK; base->MCR |= CAN_MCR_HALT_MASK; - /* Wait until the FlexCAN Module enter freeze mode. */ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_9595) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_9595) + u32TimeoutCount = (uint32_t)FLEXCAN_WAIT_TIMEOUT; + do + { + u32TempMCR = base->MCR; + u32TimeoutCount--; + } while ((!(u32TempMCR & CAN_MCR_FRZACK_MASK)) && (u32TimeoutCount > 0)); + + if (!(u32TempMCR & CAN_MCR_FRZACK_MASK)) + { + /* Backup IMASK register */ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) + u32TempIMASK2 = base->IMASK2; +#endif + u32TempIMASK1 = base->IMASK1; + base->MCR |= CAN_MCR_SOFTRST_MASK; + + /* Wait until until the Soft Reset (SOFTRST in MCR) bit is cleared */ + u32TimeoutCount = (uint32_t)FLEXCAN_WAIT_TIMEOUT; + do + { + u32TempMCR = base->MCR; + u32TimeoutCount--; + } while ((!(u32TempMCR & CAN_MCR_SOFTRST_MASK)) && (u32TimeoutCount > 0)); + /* Reconfigure the MCR and all Interrupt Mask Registers (IMASKn) */ + base->MCR = u32TempMCR; +#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) + base->IMASK2 = u32TempIMASK2; +#endif + base->IMASK1 = u32TempIMASK1; + } +#else while (!(base->MCR & CAN_MCR_FRZACK_MASK)) { } +#endif } static void FLEXCAN_ExitFreezeMode(CAN_Type *base) @@ -258,7 +326,8 @@ static bool FLEXCAN_IsMbOccupied(CAN_Type *base, uint8_t mbIdx) /* Calculate the number of last Message Buffer occupied by Rx FIFO. */ lastOccupiedMb = ((lastOccupiedMb + 1) * 2) + 5; -#if (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) +#if ((defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) || \ + (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5829) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5829)) if (mbIdx <= (lastOccupiedMb + 1)) #else if (mbIdx <= lastOccupiedMb) @@ -273,7 +342,8 @@ static bool FLEXCAN_IsMbOccupied(CAN_Type *base, uint8_t mbIdx) } else { -#if (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) +#if ((defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) || \ + (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5829) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5829)) if (0 == mbIdx) { return true; @@ -289,7 +359,8 @@ static bool FLEXCAN_IsMbOccupied(CAN_Type *base, uint8_t mbIdx) } #endif -#if (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) +#if ((defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) || \ + (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5829) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5829)) static uint32_t FLEXCAN_GetFirstValidMb(CAN_Type *base) { uint32_t firstValidMbNum; @@ -370,7 +441,7 @@ static void FLEXCAN_Reset(CAN_Type *base) { } - /* Reset MCR register. */ +/* Reset MCR register. */ #if (defined(FSL_FEATURE_FLEXCAN_HAS_GLITCH_FILTER) && FSL_FEATURE_FLEXCAN_HAS_GLITCH_FILTER) base->MCR |= CAN_MCR_WRNEN_MASK | CAN_MCR_WAKSRC_MASK | CAN_MCR_MAXMB(FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(base) - 1); @@ -378,7 +449,7 @@ static void FLEXCAN_Reset(CAN_Type *base) base->MCR |= CAN_MCR_WRNEN_MASK | CAN_MCR_MAXMB(FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(base) - 1); #endif - /* Reset CTRL1 and CTRL2 register. */ +/* Reset CTRL1 and CTRL2 register. */ #if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) /* SMP bit cannot be asserted when CAN FD is enabled */ if (FSL_FEATURE_FLEXCAN_INSTANCE_HAS_FLEXIBLE_DATA_RATEn(base)) @@ -488,6 +559,29 @@ static void FLEXCAN_SetFDBaudRate(CAN_Type *base, } #endif +/*! + * brief Initializes a FlexCAN instance. + * + * This function initializes the FlexCAN module with user-defined settings. + * This example shows how to set up the flexcan_config_t parameters and how + * to call the FLEXCAN_Init function by passing in these parameters. + * code + * flexcan_config_t flexcanConfig; + * flexcanConfig.clkSrc = kFLEXCAN_ClkSrcOsc; + * flexcanConfig.baudRate = 1000000U; + * flexcanConfig.maxMbNum = 16; + * flexcanConfig.enableLoopBack = false; + * flexcanConfig.enableSelfWakeup = false; + * flexcanConfig.enableIndividMask = false; + * flexcanConfig.enableDoze = false; + * flexcanConfig.timingConfig = timingConfig; + * FLEXCAN_Init(CAN0, &flexcanConfig, 8000000UL); + * endcode + * + * param base FlexCAN peripheral base address. + * param config Pointer to the user-defined configuration structure. + * param sourceClock_Hz FlexCAN Protocol Engine clock source frequency in Hz. + */ void FLEXCAN_Init(CAN_Type *base, const flexcan_config_t *config, uint32_t sourceClock_Hz) { uint32_t mcrTemp; @@ -529,7 +623,7 @@ void FLEXCAN_Init(CAN_Type *base, const flexcan_config_t *config, uint32_t sourc * when FlexCAN Module in Disable Mode. */ base->CTRL1 = (kFLEXCAN_ClkSrcOsc == config->clkSrc) ? base->CTRL1 & ~CAN_CTRL1_CLKSRC_MASK : - base->CTRL1 | CAN_CTRL1_CLKSRC_MASK; + base->CTRL1 | CAN_CTRL1_CLKSRC_MASK; } #endif #endif /* FSL_FEATURE_FLEXCAN_SUPPORT_ENGINE_CLK_SEL_REMOVE */ @@ -552,8 +646,10 @@ void FLEXCAN_Init(CAN_Type *base, const flexcan_config_t *config, uint32_t sourc /* Enable Timer Sync? */ base->CTRL1 = (config->enableTimerSync) ? base->CTRL1 | CAN_CTRL1_TSYN_MASK : base->CTRL1 & ~CAN_CTRL1_TSYN_MASK; - /* Enable Self Wake Up Mode? */ + /* Enable Self Wake Up Mode and configure the wake up source. */ mcrTemp = (config->enableSelfWakeup) ? mcrTemp | CAN_MCR_SLFWAK_MASK : mcrTemp & ~CAN_MCR_SLFWAK_MASK; + mcrTemp = (kFLEXCAN_WakeupSrcFiltered == config->wakeupSrc) ? mcrTemp | CAN_MCR_WAKSRC_MASK : + mcrTemp & ~CAN_MCR_WAKSRC_MASK; /* Enable Individual Rx Masking? */ mcrTemp = (config->enableIndividMask) ? mcrTemp | CAN_MCR_IRMQ_MASK : mcrTemp & ~CAN_MCR_IRMQ_MASK; @@ -574,7 +670,34 @@ void FLEXCAN_Init(CAN_Type *base, const flexcan_config_t *config, uint32_t sourc } #if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) -void FLEXCAN_FDInit(CAN_Type *base, const flexcan_config_t *config, uint32_t sourceClock_Hz, flexcan_mb_size_t dataSize, bool brs) +/*! + * brief Initializes a FlexCAN instance. + * + * This function initializes the FlexCAN module with user-defined settings. + * This example shows how to set up the flexcan_config_t parameters and how + * to call the FLEXCAN_FDInit function by passing in these parameters. + * code + * flexcan_config_t flexcanConfig; + * flexcanConfig.clkSrc = kFLEXCAN_ClkSrcOsc; + * flexcanConfig.baudRate = 1000000U; + * flexcanConfig.baudRateFD = 2000000U; + * flexcanConfig.maxMbNum = 16; + * flexcanConfig.enableLoopBack = false; + * flexcanConfig.enableSelfWakeup = false; + * flexcanConfig.enableIndividMask = false; + * flexcanConfig.enableDoze = false; + * flexcanConfig.timingConfig = timingConfig; + * FLEXCAN_FDInit(CAN0, &flexcanConfig, 8000000UL, kFLEXCAN_16BperMB, false); + * endcode + * + * param base FlexCAN peripheral base address. + * param config Pointer to the user-defined configuration structure. + * param sourceClock_Hz FlexCAN Protocol Engine clock source frequency in Hz. + * param dataSize FlexCAN FD frame payload size. + * param brs If bitrate switch is enabled in FD mode. + */ +void FLEXCAN_FDInit( + CAN_Type *base, const flexcan_config_t *config, uint32_t sourceClock_Hz, flexcan_mb_size_t dataSize, bool brs) { assert(dataSize <= 3U); @@ -595,7 +718,7 @@ void FLEXCAN_FDInit(CAN_Type *base, const flexcan_config_t *config, uint32_t sou } /* Enter Freeze Mode. */ FLEXCAN_EnterFreezeMode(base); - if (brs && !config->enableLoopBack) + if (brs && (!config->enableLoopBack)) { base->FDCTRL |= CAN_FDCTRL_TDCEN_MASK | CAN_FDCTRL_TDCOFF(0x2U); } @@ -615,6 +738,14 @@ void FLEXCAN_FDInit(CAN_Type *base, const flexcan_config_t *config, uint32_t sou } #endif +/*! + * brief De-initializes a FlexCAN instance. + * + * This function disables the FlexCAN module clock and sets all register values + * to the reset value. + * + * param base FlexCAN peripheral base address. + */ void FLEXCAN_Deinit(CAN_Type *base) { #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) @@ -637,11 +768,31 @@ void FLEXCAN_Deinit(CAN_Type *base) #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ } +/*! + * brief Gets the default configuration structure. + * + * This function initializes the FlexCAN configuration structure to default values. The default + * values are as follows. + * flexcanConfig->clkSrc = kFLEXCAN_ClkSrcOsc; + * flexcanConfig->baudRate = 1000000U; + * flexcanConfig->baudRateFD = 2000000U; + * flexcanConfig->maxMbNum = 16; + * flexcanConfig->enableLoopBack = false; + * flexcanConfig->enableSelfWakeup = false; + * flexcanConfig->enableIndividMask = false; + * flexcanConfig->enableDoze = false; + * flexcanConfig.timingConfig = timingConfig; + * + * param config Pointer to the FlexCAN configuration structure. + */ void FLEXCAN_GetDefaultConfig(flexcan_config_t *config) { /* Assertion. */ assert(config); + /* Initializes the configure structure to zero. */ + memset(config, 0, sizeof(*config)); + /* Initialize FlexCAN Module config struct with default value. */ config->clkSrc = kFLEXCAN_ClkSrcOsc; config->baudRate = 1000000U; @@ -652,6 +803,7 @@ void FLEXCAN_GetDefaultConfig(flexcan_config_t *config) config->enableLoopBack = false; config->enableTimerSync = true; config->enableSelfWakeup = false; + config->wakeupSrc = kFLEXCAN_WakeupSrcUnfiltered; config->enableIndividMask = false; #if (defined(FSL_FEATURE_FLEXCAN_HAS_DOZE_MODE_SUPPORT) && FSL_FEATURE_FLEXCAN_HAS_DOZE_MODE_SUPPORT) config->enableDoze = false; @@ -669,6 +821,20 @@ void FLEXCAN_GetDefaultConfig(flexcan_config_t *config) #endif } +/*! + * brief Sets the FlexCAN protocol timing characteristic. + * + * This function gives user settings to CAN bus timing characteristic. + * The function is for an experienced user. For less experienced users, call + * the FLEXCAN_Init() and fill the baud rate field with a desired value. + * This provides the default timing characteristics to the module. + * + * Note that calling FLEXCAN_SetTimingConfig() overrides the baud rate set + * in FLEXCAN_Init(). + * + * param base FlexCAN peripheral base address. + * param config Pointer to the timing configuration structure. + */ void FLEXCAN_SetTimingConfig(CAN_Type *base, const flexcan_timing_config_t *config) { /* Assertion. */ @@ -682,12 +848,12 @@ void FLEXCAN_SetTimingConfig(CAN_Type *base, const flexcan_timing_config_t *conf { /* Cleaning previous Timing Setting. */ base->CBT &= ~(CAN_CBT_EPRESDIV_MASK | CAN_CBT_ERJW_MASK | CAN_CBT_EPSEG1_MASK | CAN_CBT_EPSEG2_MASK | - CAN_CBT_EPROPSEG_MASK); + CAN_CBT_EPROPSEG_MASK); /* Updating Timing Setting according to configuration structure. */ base->CBT |= - (CAN_CBT_EPRESDIV(config->preDivider) | CAN_CBT_ERJW(config->rJumpwidth) | CAN_CBT_EPSEG1(config->phaseSeg1) | - CAN_CBT_EPSEG2(config->phaseSeg2) | CAN_CBT_EPROPSEG(config->propSeg)); + (CAN_CBT_EPRESDIV(config->preDivider) | CAN_CBT_ERJW(config->rJumpwidth) | + CAN_CBT_EPSEG1(config->phaseSeg1) | CAN_CBT_EPSEG2(config->phaseSeg2) | CAN_CBT_EPROPSEG(config->propSeg)); } else { @@ -696,9 +862,9 @@ void FLEXCAN_SetTimingConfig(CAN_Type *base, const flexcan_timing_config_t *conf CAN_CTRL1_PROPSEG_MASK); /* Updating Timing Setting according to configuration structure. */ - base->CTRL1 |= - (CAN_CTRL1_PRESDIV(config->preDivider) | CAN_CTRL1_RJW(config->rJumpwidth) | - CAN_CTRL1_PSEG1(config->phaseSeg1) | CAN_CTRL1_PSEG2(config->phaseSeg2) | CAN_CTRL1_PROPSEG(config->propSeg)); + base->CTRL1 |= (CAN_CTRL1_PRESDIV(config->preDivider) | CAN_CTRL1_RJW(config->rJumpwidth) | + CAN_CTRL1_PSEG1(config->phaseSeg1) | CAN_CTRL1_PSEG2(config->phaseSeg2) | + CAN_CTRL1_PROPSEG(config->propSeg)); } #else /* Cleaning previous Timing Setting. */ @@ -716,6 +882,20 @@ void FLEXCAN_SetTimingConfig(CAN_Type *base, const flexcan_timing_config_t *conf } #if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) +/*! + * brief Sets the FlexCAN FD protocol timing characteristic. + * + * This function gives user settings to CAN bus timing characteristic. + * The function is for an experienced user. For less experienced users, call + * the FLEXCAN_Init() and fill the baud rate field with a desired value. + * This provides the default timing characteristics to the module. + * + * Note that calling FLEXCAN_SetFDTimingConfig() overrides the baud rate set + * in FLEXCAN_Init(). + * + * param base FlexCAN peripheral base address. + * param config Pointer to the timing configuration structure. + */ void FLEXCAN_SetFDTimingConfig(CAN_Type *base, const flexcan_timing_config_t *config) { /* Assertion. */ @@ -739,6 +919,15 @@ void FLEXCAN_SetFDTimingConfig(CAN_Type *base, const flexcan_timing_config_t *co } #endif +/*! + * brief Sets the FlexCAN receive message buffer global mask. + * + * This function sets the global mask for the FlexCAN message buffer in a matching process. + * The configuration is only effective when the Rx individual mask is disabled in the FLEXCAN_Init(). + * + * param base FlexCAN peripheral base address. + * param mask Rx Message Buffer Global Mask value. + */ void FLEXCAN_SetRxMbGlobalMask(CAN_Type *base, uint32_t mask) { /* Enter Freeze Mode. */ @@ -753,6 +942,14 @@ void FLEXCAN_SetRxMbGlobalMask(CAN_Type *base, uint32_t mask) FLEXCAN_ExitFreezeMode(base); } +/*! + * brief Sets the FlexCAN receive FIFO global mask. + * + * This function sets the global mask for FlexCAN FIFO in a matching process. + * + * param base FlexCAN peripheral base address. + * param mask Rx Fifo Global Mask value. + */ void FLEXCAN_SetRxFifoGlobalMask(CAN_Type *base, uint32_t mask) { /* Enter Freeze Mode. */ @@ -765,6 +962,20 @@ void FLEXCAN_SetRxFifoGlobalMask(CAN_Type *base, uint32_t mask) FLEXCAN_ExitFreezeMode(base); } +/*! + * brief Sets the FlexCAN receive individual mask. + * + * This function sets the individual mask for the FlexCAN matching process. + * The configuration is only effective when the Rx individual mask is enabled in the FLEXCAN_Init(). + * If the Rx FIFO is disabled, the individual mask is applied to the corresponding Message Buffer. + * If the Rx FIFO is enabled, the individual mask for Rx FIFO occupied Message Buffer is applied to + * the Rx Filter with the same index. Note that only the first 32 + * individual masks can be used as the Rx FIFO filter mask. + * + * param base FlexCAN peripheral base address. + * param maskIdx The Index of individual Mask. + * param mask Rx Individual Mask value. + */ void FLEXCAN_SetRxIndividualMask(CAN_Type *base, uint8_t maskIdx, uint32_t mask) { assert(maskIdx <= (base->MCR & CAN_MCR_MAXMB_MASK)); @@ -779,6 +990,18 @@ void FLEXCAN_SetRxIndividualMask(CAN_Type *base, uint8_t maskIdx, uint32_t mask) FLEXCAN_ExitFreezeMode(base); } +/*! + * brief Configures a FlexCAN transmit message buffer. + * + * This function aborts the previous transmission, cleans the Message Buffer, and + * configures it as a Transmit Message Buffer. + * + * param base FlexCAN peripheral base address. + * param mbIdx The Message Buffer index. + * param enable Enable/disable Tx Message Buffer. + * - true: Enable Tx Message Buffer. + * - false: Disable Tx Message Buffer. + */ void FLEXCAN_SetTxMbConfig(CAN_Type *base, uint8_t mbIdx, bool enable) { /* Assertion. */ @@ -831,6 +1054,18 @@ static uint32_t FLEXCAN_GetFDMailboxOffset(CAN_Type *base, uint8_t mbIdx) #endif #if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) +/*! + * brief Configures a FlexCAN transmit message buffer. + * + * This function aborts the previous transmission, cleans the Message Buffer, and + * configures it as a Transmit Message Buffer. + * + * param base FlexCAN peripheral base address. + * param mbIdx The Message Buffer index. + * param enable Enable/disable Tx Message Buffer. + * - true: Enable Tx Message Buffer. + * - false: Disable Tx Message Buffer. + */ void FLEXCAN_SetFDTxMbConfig(CAN_Type *base, uint8_t mbIdx, bool enable) { /* Assertion. */ @@ -842,7 +1077,8 @@ void FLEXCAN_SetFDTxMbConfig(CAN_Type *base, uint8_t mbIdx, bool enable) dataSize = (base->FDCTRL & CAN_FDCTRL_MBDSR0_MASK) >> CAN_FDCTRL_MBDSR0_SHIFT; volatile uint32_t *mbAddr = &(base->MB[0].CS); uint32_t offset = FLEXCAN_GetFDMailboxOffset(base, mbIdx); -#if (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) +#if ((defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) || \ + (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5829) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5829)) uint32_t availoffset = FLEXCAN_GetFDMailboxOffset(base, FLEXCAN_GetFirstValidMb(base)); #endif @@ -872,12 +1108,26 @@ void FLEXCAN_SetFDTxMbConfig(CAN_Type *base, uint8_t mbIdx, bool enable) mbAddr[offset + 2 + cnt] = 0x0; } -#if (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) +#if ((defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) || \ + (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5829) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5829)) mbAddr[availoffset] = CAN_CS_CODE(kFLEXCAN_TxMbInactive); #endif } #endif +/*! + * brief Configures a FlexCAN Receive Message Buffer. + * + * This function cleans a FlexCAN build-in Message Buffer and configures it + * as a Receive Message Buffer. + * + * param base FlexCAN peripheral base address. + * param mbIdx The Message Buffer index. + * param config Pointer to the FlexCAN Message Buffer configuration structure. + * param enable Enable/disable Rx Message Buffer. + * - true: Enable Rx Message Buffer. + * - false: Disable Rx Message Buffer. + */ void FLEXCAN_SetRxMbConfig(CAN_Type *base, uint8_t mbIdx, const flexcan_rx_mb_config_t *config, bool enable) { /* Assertion. */ @@ -919,6 +1169,19 @@ void FLEXCAN_SetRxMbConfig(CAN_Type *base, uint8_t mbIdx, const flexcan_rx_mb_co } #if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) +/*! + * brief Configures a FlexCAN Receive Message Buffer. + * + * This function cleans a FlexCAN build-in Message Buffer and configures it + * as a Receive Message Buffer. + * + * param base FlexCAN peripheral base address. + * param mbIdx The Message Buffer index. + * param config Pointer to the FlexCAN Message Buffer configuration structure. + * param enable Enable/disable Rx Message Buffer. + * - true: Enable Rx Message Buffer. + * - false: Disable Rx Message Buffer. + */ void FLEXCAN_SetFDRxMbConfig(CAN_Type *base, uint8_t mbIdx, const flexcan_rx_mb_config_t *config, bool enable) { /* Assertion. */ @@ -934,10 +1197,10 @@ void FLEXCAN_SetFDRxMbConfig(CAN_Type *base, uint8_t mbIdx, const flexcan_rx_mb_ /* Inactivate all mailboxes first, clean ID and Message Buffer content. */ for (cnt = 0; cnt < FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(base); cnt++) { - base->MB[cnt].CS = 0; - base->MB[cnt].ID = 0; - base->MB[cnt].WORD0 = 0; - base->MB[cnt].WORD1 = 0; + base->MB[cnt].CS = 0; + base->MB[cnt].ID = 0; + base->MB[cnt].WORD0 = 0; + base->MB[cnt].WORD1 = 0; } if (enable) @@ -958,6 +1221,17 @@ void FLEXCAN_SetFDRxMbConfig(CAN_Type *base, uint8_t mbIdx, const flexcan_rx_mb_ } #endif +/*! + * brief Configures the FlexCAN Rx FIFO. + * + * This function configures the Rx FIFO with given Rx FIFO configuration. + * + * param base FlexCAN peripheral base address. + * param config Pointer to the FlexCAN Rx FIFO configuration structure. + * param enable Enable/disable Rx FIFO. + * - true: Enable Rx FIFO. + * - false: Disable Rx FIFO. + */ void FLEXCAN_SetRxFifoConfig(CAN_Type *base, const flexcan_rx_fifo_config_t *config, bool enable) { /* Assertion. */ @@ -1064,6 +1338,14 @@ void FLEXCAN_SetRxFifoConfig(CAN_Type *base, const flexcan_rx_fifo_config_t *con } #if (defined(FSL_FEATURE_FLEXCAN_HAS_RX_FIFO_DMA) && FSL_FEATURE_FLEXCAN_HAS_RX_FIFO_DMA) +/*! + * brief Enables or disables the FlexCAN Rx FIFO DMA request. + * + * This function enables or disables the DMA feature of FlexCAN build-in Rx FIFO. + * + * param base FlexCAN peripheral base address. + * param enable true to enable, false to disable. + */ void FLEXCAN_EnableRxFifoDMA(CAN_Type *base, bool enable) { if (enable) @@ -1091,6 +1373,86 @@ void FLEXCAN_EnableRxFifoDMA(CAN_Type *base, bool enable) } #endif /* FSL_FEATURE_FLEXCAN_HAS_RX_FIFO_DMA */ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_6032) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_6032) +/*! + * FlexCAN: A frame with wrong ID or payload is transmitted into + * the CAN bus when the Message Buffer under transmission is + * either aborted or deactivated while the CAN bus is in the Bus Idle state + * + * This function to do workaround for ERR006032 + * + * param base FlexCAN peripheral base address. + * param mbIdx The FlexCAN Message Buffer index. + */ +static void FLEXCAN_ERRATA_6032(CAN_Type *base, uint8_t mbIdx) +{ + uint32_t dbg_temp = 0U; + volatile const uint32_t *dbg1Addr = &(base->MCR) + OFFSET_DBG1 / 4; + /*after backup all interruption, disable ALL interruption*/ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) + uint32_t u32TempIMASK2 = base->IMASK2; + base->IMASK2 = 0; +#endif + uint32_t u32TempIMASK1 = base->IMASK1; + base->IMASK1 = 0; + dbg_temp = (uint32_t)(*dbg1Addr); + switch (dbg_temp & CAN_DBG1_CBN_MASK) + { + case RXINTERMISSION: + if ((dbg_temp & CAN_DBG1_CBN_MASK) == CBN_VALUE3) + { + /*wait until CFSM is different from RXINTERMISSION */ + while ((((uint32_t)(*dbg1Addr)) & CAN_DBG1_CBN_MASK) == RXINTERMISSION) + { + __NOP(); + } + } + break; + case TXINTERMISSION: + if ((dbg_temp & CAN_DBG1_CBN_MASK) == CBN_VALUE3) + { + /*wait until CFSM is different from TXINTERMISSION*/ + while ((((uint32_t)(*dbg1Addr)) & CAN_DBG1_CBN_MASK) == TXINTERMISSION) + { + __NOP(); + } + } + break; + default: + break; + } + /*Anyway, BUSIDLE need to delay*/ + if ((((uint32_t)(*dbg1Addr)) & CAN_DBG1_CBN_MASK) == BUSIDLE) + { + uint32_t n = DELAY_BUSIDLE; + while (n-- > 0) + { + __NOP(); + } + } + /*Write 0x0 into Code field of CS word.*/ + base->MB[mbIdx].CS &= ~CAN_CS_CODE_MASK; +/*restore interruption*/ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) + base->IMASK2 = u32TempIMASK2; +#endif + base->IMASK1 = u32TempIMASK1; +} +#endif + +/*! + * brief Writes a FlexCAN Message to the Transmit Message Buffer. + * + * This function writes a CAN Message to the specified Transmit Message Buffer + * and changes the Message Buffer state to start CAN Message transmit. After + * that the function returns immediately. + * + * param base FlexCAN peripheral base address. + * param mbIdx The FlexCAN Message Buffer index. + * param txFrame Pointer to CAN message frame to be sent. + * retval kStatus_Success - Write Tx Message Buffer Successfully. + * retval kStatus_Fail - Tx Message Buffer is currently in use. + */ status_t FLEXCAN_WriteTxMb(CAN_Type *base, uint8_t mbIdx, const flexcan_frame_t *txFrame) { /* Assertion. */ @@ -1101,6 +1463,9 @@ status_t FLEXCAN_WriteTxMb(CAN_Type *base, uint8_t mbIdx, const flexcan_frame_t uint32_t cs_temp = 0; +#if (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_6032) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_6032) + FLEXCAN_ERRATA_6032(base, mbIdx); +#endif /* Check if Message Buffer is available. */ if (CAN_CS_CODE(kFLEXCAN_TxMbDataOrRemote) != (base->MB[mbIdx].CS & CAN_CS_CODE_MASK)) { @@ -1131,7 +1496,8 @@ status_t FLEXCAN_WriteTxMb(CAN_Type *base, uint8_t mbIdx, const flexcan_frame_t /* Activate Tx Message Buffer. */ base->MB[mbIdx].CS = cs_temp; -#if (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) +#if ((defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) || \ + (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5829) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5829)) base->MB[FLEXCAN_GetFirstValidMb(base)].CS = CAN_CS_CODE(kFLEXCAN_TxMbInactive); base->MB[FLEXCAN_GetFirstValidMb(base)].CS = CAN_CS_CODE(kFLEXCAN_TxMbInactive); #endif @@ -1146,6 +1512,19 @@ status_t FLEXCAN_WriteTxMb(CAN_Type *base, uint8_t mbIdx, const flexcan_frame_t } #if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) +/*! + * brief Writes a FlexCAN FD Message to the Transmit Message Buffer. + * + * This function writes a CAN FD Message to the specified Transmit Message Buffer + * and changes the Message Buffer state to start CAN FD Message transmit. After + * that the function returns immediately. + * + * param base FlexCAN peripheral base address. + * param mbIdx The FlexCAN FD Message Buffer index. + * param txFrame Pointer to CAN FD message frame to be sent. + * retval kStatus_Success - Write Tx Message Buffer Successfully. + * retval kStatus_Fail - Tx Message Buffer is currently in use. + */ status_t FLEXCAN_WriteFDTxMb(CAN_Type *base, uint8_t mbIdx, const flexcan_fd_frame_t *txFrame) { /* Assertion. */ @@ -1158,8 +1537,12 @@ status_t FLEXCAN_WriteFDTxMb(CAN_Type *base, uint8_t mbIdx, const flexcan_fd_fra uint32_t can_cs = 0; uint8_t payload_dword = 1; uint32_t dataSize; +#if (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_6032) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_6032) + FLEXCAN_ERRATA_6032(base, mbIdx); +#endif dataSize = (base->FDCTRL & CAN_FDCTRL_MBDSR0_MASK) >> CAN_FDCTRL_MBDSR0_SHIFT; -#if (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) +#if ((defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) || \ + (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5829) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5829)) uint32_t availoffset = FLEXCAN_GetFDMailboxOffset(base, FLEXCAN_GetFirstValidMb(base)); #endif volatile uint32_t *mbAddr = &(base->MB[0].CS); @@ -1179,7 +1562,8 @@ status_t FLEXCAN_WriteFDTxMb(CAN_Type *base, uint8_t mbIdx, const flexcan_fd_fra cs_temp |= CAN_CS_SRR_MASK | CAN_CS_IDE_MASK; } - cs_temp |= CAN_CS_CODE(kFLEXCAN_TxMbDataOrRemote) | CAN_CS_DLC(txFrame->length) | CAN_CS_EDL(1) | CAN_CS_BRS(txFrame->brs); + cs_temp |= CAN_CS_CODE(kFLEXCAN_TxMbDataOrRemote) | CAN_CS_DLC(txFrame->length) | CAN_CS_EDL(1) | + CAN_CS_BRS(txFrame->brs); /* Calculate the DWORD number, dataSize 0/1/2/3 corresponds to 8/16/32/64 Bytes payload. */ @@ -1195,7 +1579,8 @@ status_t FLEXCAN_WriteFDTxMb(CAN_Type *base, uint8_t mbIdx, const flexcan_fd_fra } mbAddr[offset] = cs_temp; -#if (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) +#if ((defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) || \ + (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5829) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5829)) mbAddr[availoffset] = CAN_CS_CODE(kFLEXCAN_TxMbInactive); mbAddr[availoffset] = CAN_CS_CODE(kFLEXCAN_TxMbInactive); #endif @@ -1210,6 +1595,21 @@ status_t FLEXCAN_WriteFDTxMb(CAN_Type *base, uint8_t mbIdx, const flexcan_fd_fra } #endif +/*! + * brief Reads a FlexCAN Message from Receive Message Buffer. + * + * This function reads a CAN message from a specified Receive Message Buffer. + * The function fills a receive CAN message frame structure with + * just received data and activates the Message Buffer again. + * The function returns immediately. + * + * param base FlexCAN peripheral base address. + * param mbIdx The FlexCAN Message Buffer index. + * param rxFrame Pointer to CAN message frame structure for reception. + * retval kStatus_Success - Rx Message Buffer is full and has been read successfully. + * retval kStatus_FLEXCAN_RxOverflow - Rx Message Buffer is already overflowed and has been read successfully. + * retval kStatus_Fail - Rx Message Buffer is empty. + */ status_t FLEXCAN_ReadRxMb(CAN_Type *base, uint8_t mbIdx, flexcan_frame_t *rxFrame) { /* Assertion. */ @@ -1269,6 +1669,21 @@ status_t FLEXCAN_ReadRxMb(CAN_Type *base, uint8_t mbIdx, flexcan_frame_t *rxFram } #if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) +/*! + * brief Reads a FlexCAN FD Message from Receive Message Buffer. + * + * This function reads a CAN FD message from a specified Receive Message Buffer. + * The function fills a receive CAN FD message frame structure with + * just received data and activates the Message Buffer again. + * The function returns immediately. + * + * param base FlexCAN peripheral base address. + * param mbIdx The FlexCAN FD Message Buffer index. + * param rxFrame Pointer to CAN FD message frame structure for reception. + * retval kStatus_Success - Rx Message Buffer is full and has been read successfully. + * retval kStatus_FLEXCAN_RxOverflow - Rx Message Buffer is already overflowed and has been read successfully. + * retval kStatus_Fail - Rx Message Buffer is empty. + */ status_t FLEXCAN_ReadFDRxMb(CAN_Type *base, uint8_t mbIdx, flexcan_fd_frame_t *rxFrame) { /* Assertion. */ @@ -1346,6 +1761,16 @@ status_t FLEXCAN_ReadFDRxMb(CAN_Type *base, uint8_t mbIdx, flexcan_fd_frame_t *r } #endif +/*! + * brief Reads a FlexCAN Message from Rx FIFO. + * + * This function reads a CAN message from the FlexCAN build-in Rx FIFO. + * + * param base FlexCAN peripheral base address. + * param rxFrame Pointer to CAN message frame structure for reception. + * retval kStatus_Success - Read Message from Rx FIFO successfully. + * retval kStatus_Fail - Rx FIFO is not enabled. + */ status_t FLEXCAN_ReadRxFifo(CAN_Type *base, flexcan_frame_t *rxFrame) { /* Assertion. */ @@ -1390,12 +1815,23 @@ status_t FLEXCAN_ReadRxFifo(CAN_Type *base, flexcan_frame_t *rxFrame) } } +/*! + * brief Performs a polling send transaction on the CAN bus. + * + * Note that a transfer handle does not need to be created before calling this API. + * + * param base FlexCAN peripheral base pointer. + * param mbIdx The FlexCAN Message Buffer index. + * param txFrame Pointer to CAN message frame to be sent. + * retval kStatus_Success - Write Tx Message Buffer Successfully. + * retval kStatus_Fail - Tx Message Buffer is currently in use. + */ status_t FLEXCAN_TransferSendBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_frame_t *txFrame) { /* Write Tx Message Buffer to initiate a data sending. */ if (kStatus_Success == FLEXCAN_WriteTxMb(base, mbIdx, txFrame)) { - /* Wait until CAN Message send out. */ +/* Wait until CAN Message send out. */ #if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) while (!FLEXCAN_GetMbStatusFlags(base, (uint64_t)1 << mbIdx)) #else @@ -1404,7 +1840,7 @@ status_t FLEXCAN_TransferSendBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_fra { } - /* Clean Tx Message Buffer Flag. */ +/* Clean Tx Message Buffer Flag. */ #if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) FLEXCAN_ClearMbStatusFlags(base, (uint64_t)1 << mbIdx); #else @@ -1419,9 +1855,21 @@ status_t FLEXCAN_TransferSendBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_fra } } +/*! + * brief Performs a polling receive transaction on the CAN bus. + * + * Note that a transfer handle does not need to be created before calling this API. + * + * param base FlexCAN peripheral base pointer. + * param mbIdx The FlexCAN Message Buffer index. + * param rxFrame Pointer to CAN message frame structure for reception. + * retval kStatus_Success - Rx Message Buffer is full and has been read successfully. + * retval kStatus_FLEXCAN_RxOverflow - Rx Message Buffer is already overflowed and has been read successfully. + * retval kStatus_Fail - Rx Message Buffer is empty. + */ status_t FLEXCAN_TransferReceiveBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_frame_t *rxFrame) { - /* Wait until Rx Message Buffer non-empty. */ +/* Wait until Rx Message Buffer non-empty. */ #if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) while (!FLEXCAN_GetMbStatusFlags(base, (uint64_t)1 << mbIdx)) #else @@ -1430,7 +1878,7 @@ status_t FLEXCAN_TransferReceiveBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_ { } - /* Clean Rx Message Buffer Flag. */ +/* Clean Rx Message Buffer Flag. */ #if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) FLEXCAN_ClearMbStatusFlags(base, (uint64_t)1 << mbIdx); #else @@ -1442,12 +1890,23 @@ status_t FLEXCAN_TransferReceiveBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_ } #if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) +/*! + * brief Performs a polling send transaction on the CAN bus. + * + * Note that a transfer handle does not need to be created before calling this API. + * + * param base FlexCAN peripheral base pointer. + * param mbIdx The FlexCAN FD Message Buffer index. + * param txFrame Pointer to CAN FD message frame to be sent. + * retval kStatus_Success - Write Tx Message Buffer Successfully. + * retval kStatus_Fail - Tx Message Buffer is currently in use. + */ status_t FLEXCAN_TransferFDSendBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_fd_frame_t *txFrame) { /* Write Tx Message Buffer to initiate a data sending. */ if (kStatus_Success == FLEXCAN_WriteFDTxMb(base, mbIdx, txFrame)) { - /* Wait until CAN Message send out. */ +/* Wait until CAN Message send out. */ #if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) while (!FLEXCAN_GetMbStatusFlags(base, (uint64_t)1 << mbIdx)) #else @@ -1456,7 +1915,7 @@ status_t FLEXCAN_TransferFDSendBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_f { } - /* Clean Tx Message Buffer Flag. */ +/* Clean Tx Message Buffer Flag. */ #if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) FLEXCAN_ClearMbStatusFlags(base, (uint64_t)1 << mbIdx); #else @@ -1471,9 +1930,21 @@ status_t FLEXCAN_TransferFDSendBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_f } } +/*! + * brief Performs a polling receive transaction on the CAN bus. + * + * Note that a transfer handle does not need to be created before calling this API. + * + * param base FlexCAN peripheral base pointer. + * param mbIdx The FlexCAN FD Message Buffer index. + * param rxFrame Pointer to CAN FD message frame structure for reception. + * retval kStatus_Success - Rx Message Buffer is full and has been read successfully. + * retval kStatus_FLEXCAN_RxOverflow - Rx Message Buffer is already overflowed and has been read successfully. + * retval kStatus_Fail - Rx Message Buffer is empty. + */ status_t FLEXCAN_TransferFDReceiveBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_fd_frame_t *rxFrame) { - /* Wait until Rx Message Buffer non-empty. */ +/* Wait until Rx Message Buffer non-empty. */ #if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) while (!FLEXCAN_GetMbStatusFlags(base, (uint64_t)1 << mbIdx)) #else @@ -1482,7 +1953,7 @@ status_t FLEXCAN_TransferFDReceiveBlocking(CAN_Type *base, uint8_t mbIdx, flexca { } - /* Clean Rx Message Buffer Flag. */ +/* Clean Rx Message Buffer Flag. */ #if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) FLEXCAN_ClearMbStatusFlags(base, (uint64_t)1 << mbIdx); #else @@ -1494,6 +1965,16 @@ status_t FLEXCAN_TransferFDReceiveBlocking(CAN_Type *base, uint8_t mbIdx, flexca } #endif +/*! + * brief Performs a polling receive transaction from Rx FIFO on the CAN bus. + * + * Note that a transfer handle does not need to be created before calling this API. + * + * param base FlexCAN peripheral base pointer. + * param rxFrame Pointer to CAN message frame structure for reception. + * retval kStatus_Success - Read Message from Rx FIFO successfully. + * retval kStatus_Fail - Rx FIFO is not enabled. + */ status_t FLEXCAN_TransferReceiveFifoBlocking(CAN_Type *base, flexcan_frame_t *rxFrame) { status_t rxFifoStatus; @@ -1512,6 +1993,18 @@ status_t FLEXCAN_TransferReceiveFifoBlocking(CAN_Type *base, flexcan_frame_t *rx return rxFifoStatus; } +/*! + * brief Initializes the FlexCAN handle. + * + * This function initializes the FlexCAN handle, which can be used for other FlexCAN + * transactional APIs. Usually, for a specified FlexCAN instance, + * call this API once to get the initialized handle. + * + * param base FlexCAN peripheral base address. + * param handle FlexCAN handle pointer. + * param callback The callback function. + * param userData The parameter of the callback function. + */ void FLEXCAN_TransferCreateHandle(CAN_Type *base, flexcan_handle_t *handle, flexcan_transfer_callback_t callback, @@ -1562,6 +2055,19 @@ void FLEXCAN_TransferCreateHandle(CAN_Type *base, EnableIRQ((IRQn_Type)(s_flexcanMbIRQ[instance])); } +/*! + * brief Sends a message using IRQ. + * + * This function sends a message using IRQ. This is a non-blocking function, which returns + * right away. When messages have been sent out, the send callback function is called. + * + * param base FlexCAN peripheral base address. + * param handle FlexCAN handle pointer. + * param xfer FlexCAN Message Buffer transfer structure. See the #flexcan_mb_transfer_t. + * retval kStatus_Success Start Tx Message Buffer sending process successfully. + * retval kStatus_Fail Write Tx Message Buffer failed. + * retval kStatus_FLEXCAN_TxBusy Tx Message Buffer is in use. + */ status_t FLEXCAN_TransferSendNonBlocking(CAN_Type *base, flexcan_handle_t *handle, flexcan_mb_transfer_t *xfer) { /* Assertion. */ @@ -1588,7 +2094,7 @@ status_t FLEXCAN_TransferSendNonBlocking(CAN_Type *base, flexcan_handle_t *handl if (kStatus_Success == FLEXCAN_WriteTxMb(base, xfer->mbIdx, xfer->frame)) { - /* Enable Message Buffer Interrupt. */ +/* Enable Message Buffer Interrupt. */ #if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) FLEXCAN_EnableMbInterrupts(base, (uint64_t)1 << xfer->mbIdx); #else @@ -1609,6 +2115,18 @@ status_t FLEXCAN_TransferSendNonBlocking(CAN_Type *base, flexcan_handle_t *handl } } +/*! + * brief Receives a message using IRQ. + * + * This function receives a message using IRQ. This is non-blocking function, which returns + * right away. When the message has been received, the receive callback function is called. + * + * param base FlexCAN peripheral base address. + * param handle FlexCAN handle pointer. + * param xfer FlexCAN Message Buffer transfer structure. See the #flexcan_mb_transfer_t. + * retval kStatus_Success - Start Rx Message Buffer receiving process successfully. + * retval kStatus_FLEXCAN_RxBusy - Rx Message Buffer is in use. + */ status_t FLEXCAN_TransferReceiveNonBlocking(CAN_Type *base, flexcan_handle_t *handle, flexcan_mb_transfer_t *xfer) { /* Assertion. */ @@ -1625,7 +2143,7 @@ status_t FLEXCAN_TransferReceiveNonBlocking(CAN_Type *base, flexcan_handle_t *ha /* Register Message Buffer. */ handle->mbFrameBuf[xfer->mbIdx] = xfer->frame; - /* Enable Message Buffer Interrupt. */ +/* Enable Message Buffer Interrupt. */ #if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) FLEXCAN_EnableMbInterrupts(base, (uint64_t)1 << xfer->mbIdx); #else @@ -1641,6 +2159,19 @@ status_t FLEXCAN_TransferReceiveNonBlocking(CAN_Type *base, flexcan_handle_t *ha } #if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) +/*! + * brief Sends a message using IRQ. + * + * This function sends a message using IRQ. This is a non-blocking function, which returns + * right away. When messages have been sent out, the send callback function is called. + * + * param base FlexCAN peripheral base address. + * param handle FlexCAN handle pointer. + * param xfer FlexCAN FD Message Buffer transfer structure. See the #flexcan_mb_transfer_t. + * retval kStatus_Success Start Tx Message Buffer sending process successfully. + * retval kStatus_Fail Write Tx Message Buffer failed. + * retval kStatus_FLEXCAN_TxBusy Tx Message Buffer is in use. + */ status_t FLEXCAN_TransferFDSendNonBlocking(CAN_Type *base, flexcan_handle_t *handle, flexcan_mb_transfer_t *xfer) { /* Assertion. */ @@ -1667,7 +2198,7 @@ status_t FLEXCAN_TransferFDSendNonBlocking(CAN_Type *base, flexcan_handle_t *han if (kStatus_Success == FLEXCAN_WriteFDTxMb(base, xfer->mbIdx, xfer->framefd)) { - /* Enable Message Buffer Interrupt. */ +/* Enable Message Buffer Interrupt. */ #if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) FLEXCAN_EnableMbInterrupts(base, (uint64_t)1 << xfer->mbIdx); #else @@ -1688,6 +2219,18 @@ status_t FLEXCAN_TransferFDSendNonBlocking(CAN_Type *base, flexcan_handle_t *han } } +/*! + * brief Receives a message using IRQ. + * + * This function receives a message using IRQ. This is non-blocking function, which returns + * right away. When the message has been received, the receive callback function is called. + * + * param base FlexCAN peripheral base address. + * param handle FlexCAN handle pointer. + * param xfer FlexCAN FD Message Buffer transfer structure. See the #flexcan_mb_transfer_t. + * retval kStatus_Success - Start Rx Message Buffer receiving process successfully. + * retval kStatus_FLEXCAN_RxBusy - Rx Message Buffer is in use. + */ status_t FLEXCAN_TransferFDReceiveNonBlocking(CAN_Type *base, flexcan_handle_t *handle, flexcan_mb_transfer_t *xfer) { /* Assertion. */ @@ -1704,7 +2247,7 @@ status_t FLEXCAN_TransferFDReceiveNonBlocking(CAN_Type *base, flexcan_handle_t * /* Register Message Buffer. */ handle->mbFDFrameBuf[xfer->mbIdx] = xfer->framefd; - /* Enable Message Buffer Interrupt. */ +/* Enable Message Buffer Interrupt. */ #if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) FLEXCAN_EnableMbInterrupts(base, (uint64_t)1 << xfer->mbIdx); #else @@ -1720,6 +2263,18 @@ status_t FLEXCAN_TransferFDReceiveNonBlocking(CAN_Type *base, flexcan_handle_t * } #endif +/*! + * brief Receives a message from Rx FIFO using IRQ. + * + * This function receives a message using IRQ. This is a non-blocking function, which returns + * right away. When all messages have been received, the receive callback function is called. + * + * param base FlexCAN peripheral base address. + * param handle FlexCAN handle pointer. + * param xfer FlexCAN Rx FIFO transfer structure. See the ref flexcan_fifo_transfer_t. + * retval kStatus_Success - Start Rx FIFO receiving process successfully. + * retval kStatus_FLEXCAN_RxFifoBusy - Rx FIFO is currently in use. + */ status_t FLEXCAN_TransferReceiveFifoNonBlocking(CAN_Type *base, flexcan_handle_t *handle, flexcan_fifo_transfer_t *xfer) { /* Assertion. */ @@ -1746,6 +2301,15 @@ status_t FLEXCAN_TransferReceiveFifoNonBlocking(CAN_Type *base, flexcan_handle_t } } +/*! + * brief Aborts the interrupt driven message send process. + * + * This function aborts the interrupt driven message send process. + * + * param base FlexCAN peripheral base address. + * param handle FlexCAN handle pointer. + * param mbIdx The FlexCAN Message Buffer index. + */ void FLEXCAN_TransferAbortSend(CAN_Type *base, flexcan_handle_t *handle, uint8_t mbIdx) { /* Assertion. */ @@ -1753,7 +2317,7 @@ void FLEXCAN_TransferAbortSend(CAN_Type *base, flexcan_handle_t *handle, uint8_t assert(mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK)); assert(!FLEXCAN_IsMbOccupied(base, mbIdx)); - /* Disable Message Buffer Interrupt. */ +/* Disable Message Buffer Interrupt. */ #if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) FLEXCAN_DisableMbInterrupts(base, (uint64_t)1 << mbIdx); #else @@ -1770,6 +2334,15 @@ void FLEXCAN_TransferAbortSend(CAN_Type *base, flexcan_handle_t *handle, uint8_t } #if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) +/*! + * brief Aborts the interrupt driven message send process. + * + * This function aborts the interrupt driven message send process. + * + * param base FlexCAN peripheral base address. + * param handle FlexCAN handle pointer. + * param mbIdx The FlexCAN FD Message Buffer index. + */ void FLEXCAN_TransferFDAbortSend(CAN_Type *base, flexcan_handle_t *handle, uint8_t mbIdx) { /* Assertion. */ @@ -1777,7 +2350,7 @@ void FLEXCAN_TransferFDAbortSend(CAN_Type *base, flexcan_handle_t *handle, uint8 assert(mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK)); assert(!FLEXCAN_IsMbOccupied(base, mbIdx)); - /* Disable Message Buffer Interrupt. */ +/* Disable Message Buffer Interrupt. */ #if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) FLEXCAN_DisableMbInterrupts(base, (uint64_t)1 << mbIdx); #else @@ -1800,7 +2373,7 @@ void FLEXCAN_TransferFDAbortReceive(CAN_Type *base, flexcan_handle_t *handle, ui assert(mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK)); assert(!FLEXCAN_IsMbOccupied(base, mbIdx)); - /* Disable Message Buffer Interrupt. */ +/* Disable Message Buffer Interrupt. */ #if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) FLEXCAN_DisableMbInterrupts(base, (uint64_t)1 << mbIdx); #else @@ -1813,6 +2386,15 @@ void FLEXCAN_TransferFDAbortReceive(CAN_Type *base, flexcan_handle_t *handle, ui } #endif +/*! + * brief Aborts the interrupt driven message receive process. + * + * This function aborts the interrupt driven message receive process. + * + * param base FlexCAN peripheral base address. + * param handle FlexCAN handle pointer. + * param mbIdx The FlexCAN Message Buffer index. + */ void FLEXCAN_TransferAbortReceive(CAN_Type *base, flexcan_handle_t *handle, uint8_t mbIdx) { /* Assertion. */ @@ -1820,7 +2402,7 @@ void FLEXCAN_TransferAbortReceive(CAN_Type *base, flexcan_handle_t *handle, uint assert(mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK)); assert(!FLEXCAN_IsMbOccupied(base, mbIdx)); - /* Disable Message Buffer Interrupt. */ +/* Disable Message Buffer Interrupt. */ #if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) FLEXCAN_DisableMbInterrupts(base, (uint64_t)1 << mbIdx); #else @@ -1832,6 +2414,14 @@ void FLEXCAN_TransferAbortReceive(CAN_Type *base, flexcan_handle_t *handle, uint handle->mbState[mbIdx] = kFLEXCAN_StateIdle; } +/*! + * brief Aborts the interrupt driven message receive from Rx FIFO process. + * + * This function aborts the interrupt driven message receive from Rx FIFO process. + * + * param base FlexCAN peripheral base address. + * param handle FlexCAN handle pointer. + */ void FLEXCAN_TransferAbortReceiveFifo(CAN_Type *base, flexcan_handle_t *handle) { /* Assertion. */ @@ -1851,6 +2441,14 @@ void FLEXCAN_TransferAbortReceiveFifo(CAN_Type *base, flexcan_handle_t *handle) handle->rxFifoState = kFLEXCAN_StateIdle; } +/*! + * brief FlexCAN IRQ handle function. + * + * This function handles the FlexCAN Error, the Message Buffer, and the Rx FIFO IRQ request. + * + * param base FlexCAN peripheral base address. + * param handle FlexCAN handle pointer. + */ void FLEXCAN_TransferHandleIRQ(CAN_Type *base, flexcan_handle_t *handle) { /* Assertion. */ @@ -1865,14 +2463,19 @@ void FLEXCAN_TransferHandleIRQ(CAN_Type *base, flexcan_handle_t *handle) do { /* Solve FlexCAN Error and Status Interrupt. */ - if (result & (kFLEXCAN_TxWarningIntFlag | kFLEXCAN_RxWarningIntFlag | kFLEXCAN_BusOffIntFlag | - kFLEXCAN_ErrorIntFlag | kFLEXCAN_WakeUpIntFlag)) + if (result & + (kFLEXCAN_TxWarningIntFlag | kFLEXCAN_RxWarningIntFlag | kFLEXCAN_BusOffIntFlag | kFLEXCAN_ErrorIntFlag)) { status = kStatus_FLEXCAN_ErrorStatus; /* Clear FlexCAN Error and Status Interrupt. */ FLEXCAN_ClearStatusFlags(base, kFLEXCAN_TxWarningIntFlag | kFLEXCAN_RxWarningIntFlag | - kFLEXCAN_BusOffIntFlag | kFLEXCAN_ErrorIntFlag | kFLEXCAN_WakeUpIntFlag); + kFLEXCAN_BusOffIntFlag | kFLEXCAN_ErrorIntFlag); + } + else if (result & kFLEXCAN_WakeUpIntFlag) + { + status = kStatus_FLEXCAN_WakeUp; + FLEXCAN_ClearStatusFlags(base, kFLEXCAN_WakeUpIntFlag); } /* Solve FlexCAN Rx FIFO & Message Buffer Interrupt. */ else @@ -1880,7 +2483,7 @@ void FLEXCAN_TransferHandleIRQ(CAN_Type *base, flexcan_handle_t *handle) /* For this implementation, we solve the Message with lowest MB index first. */ for (result = 0; result < FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(base); result++) { - /* Get the lowest unhandled Message Buffer */ +/* Get the lowest unhandled Message Buffer */ #if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) if ((FLEXCAN_GetMbStatusFlags(base, (uint64_t)1 << result)) && (FLEXCAN_IsMbIntEnabled(base, result))) #else @@ -1992,6 +2595,18 @@ void FLEXCAN_TransferHandleIRQ(CAN_Type *base, flexcan_handle_t *handle) case kFLEXCAN_StateTxRemote: handle->mbState[result] = kFLEXCAN_StateRxRemote; status = kStatus_FLEXCAN_TxSwitchToRx; +#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) + if (base->MCR & CAN_MCR_FDEN_MASK) + { + FLEXCAN_TransferFDAbortReceive(base, handle, result); + } + else + { + FLEXCAN_TransferAbortReceive(base, handle, result); + } +#else + FLEXCAN_TransferAbortReceive(base, handle, result); +#endif break; default: @@ -2000,7 +2615,7 @@ void FLEXCAN_TransferHandleIRQ(CAN_Type *base, flexcan_handle_t *handle) } } - /* Clear resolved Message Buffer IRQ. */ +/* Clear resolved Message Buffer IRQ. */ #if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) FLEXCAN_ClearMbStatusFlags(base, (uint64_t)1 << result); #else @@ -2037,8 +2652,8 @@ void CAN0_DriverIRQHandler(void) assert(s_flexcanHandle[0]); s_flexcanIsr(CAN0, s_flexcanHandle[0]); - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ #if defined __CORTEX_M && (__CORTEX_M == 4U) __DSB(); #endif @@ -2051,8 +2666,8 @@ void CAN1_DriverIRQHandler(void) assert(s_flexcanHandle[1]); s_flexcanIsr(CAN1, s_flexcanHandle[1]); - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ #if defined __CORTEX_M && (__CORTEX_M == 4U) __DSB(); #endif @@ -2065,8 +2680,8 @@ void CAN2_DriverIRQHandler(void) assert(s_flexcanHandle[2]); s_flexcanIsr(CAN2, s_flexcanHandle[2]); - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ #if defined __CORTEX_M && (__CORTEX_M == 4U) __DSB(); #endif @@ -2079,8 +2694,8 @@ void CAN3_DriverIRQHandler(void) assert(s_flexcanHandle[3]); s_flexcanIsr(CAN3, s_flexcanHandle[3]); - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ #if defined __CORTEX_M && (__CORTEX_M == 4U) __DSB(); #endif @@ -2093,8 +2708,8 @@ void CAN4_DriverIRQHandler(void) assert(s_flexcanHandle[4]); s_flexcanIsr(CAN4, s_flexcanHandle[4]); - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ #if defined __CORTEX_M && (__CORTEX_M == 4U) __DSB(); #endif @@ -2107,8 +2722,8 @@ void DMA_FLEXCAN0_INT_DriverIRQHandler(void) assert(s_flexcanHandle[FLEXCAN_GetInstance(DMA__CAN0)]); s_flexcanIsr(DMA__CAN0, s_flexcanHandle[FLEXCAN_GetInstance(DMA__CAN0)]); - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ #if defined __CORTEX_M && (__CORTEX_M == 4U) __DSB(); #endif @@ -2121,8 +2736,8 @@ void DMA_FLEXCAN1_INT_DriverIRQHandler(void) assert(s_flexcanHandle[FLEXCAN_GetInstance(DMA__CAN1)]); s_flexcanIsr(DMA__CAN1, s_flexcanHandle[FLEXCAN_GetInstance(DMA__CAN1)]); - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ #if defined __CORTEX_M && (__CORTEX_M == 4U) __DSB(); #endif @@ -2135,8 +2750,8 @@ void DMA_FLEXCAN2_INT_DriverIRQHandler(void) assert(s_flexcanHandle[FLEXCAN_GetInstance(DMA__CAN2)]); s_flexcanIsr(DMA__CAN2, s_flexcanHandle[FLEXCAN_GetInstance(DMA__CAN2)]); - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ #if defined __CORTEX_M && (__CORTEX_M == 4U) __DSB(); #endif @@ -2149,8 +2764,8 @@ void ADMA_FLEXCAN0_INT_DriverIRQHandler(void) assert(s_flexcanHandle[FLEXCAN_GetInstance(ADMA__CAN0)]); s_flexcanIsr(ADMA__CAN0, s_flexcanHandle[FLEXCAN_GetInstance(ADMA__CAN0)]); - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ #if defined __CORTEX_M && (__CORTEX_M == 4U) __DSB(); #endif @@ -2163,8 +2778,8 @@ void ADMA_FLEXCAN1_INT_DriverIRQHandler(void) assert(s_flexcanHandle[FLEXCAN_GetInstance(ADMA__CAN1)]); s_flexcanIsr(ADMA__CAN1, s_flexcanHandle[FLEXCAN_GetInstance(ADMA__CAN1)]); - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ #if defined __CORTEX_M && (__CORTEX_M == 4U) __DSB(); #endif @@ -2177,8 +2792,8 @@ void ADMA_FLEXCAN2_INT_DriverIRQHandler(void) assert(s_flexcanHandle[FLEXCAN_GetInstance(ADMA__CAN2)]); s_flexcanIsr(ADMA__CAN2, s_flexcanHandle[FLEXCAN_GetInstance(ADMA__CAN2)]); - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ #if defined __CORTEX_M && (__CORTEX_M == 4U) __DSB(); #endif diff --git a/ext/hal/nxp/mcux/drivers/imx/fsl_flexcan.h b/ext/hal/nxp/mcux/drivers/imx/fsl_flexcan.h index d1cba4542e8..6b2d820113a 100644 --- a/ext/hal/nxp/mcux/drivers/imx/fsl_flexcan.h +++ b/ext/hal/nxp/mcux/drivers/imx/fsl_flexcan.h @@ -21,10 +21,15 @@ /*! @name Driver version */ /*@{*/ -/*! @brief FlexCAN driver version 2.2.3. */ -#define FSL_FLEXCAN_DRIVER_VERSION (MAKE_VERSION(2, 2, 3)) +/*! @brief FlexCAN driver version 2.3.0. */ +#define FSL_FLEXCAN_DRIVER_VERSION (MAKE_VERSION(2, 3, 2)) /*@}*/ +#ifndef FLEXCAN_WAIT_TIMEOUT +/* Define to 1000 means keep waiting 1000 times until the flag is assert/deassert. */ +#define FLEXCAN_WAIT_TIMEOUT (1000U) +#endif + /*! @brief FlexCAN Frame ID helper macro. */ #define FLEXCAN_ID_STD(id) \ (((uint32_t)(((uint32_t)(id)) << CAN_ID_STD_SHIFT)) & CAN_ID_STD_MASK) /*!< Standard Frame ID helper macro. */ @@ -99,10 +104,9 @@ #define FLEXCAN_RX_FIFO_STD_FILTER_TYPE_C_MID_LOW(id) \ FLEXCAN_RX_FIFO_STD_MASK_TYPE_C_MID_LOW( \ id) /*!< Standard Rx FIFO Filter helper macro Type C mid-lower part helper macro. */ -#define FLEXCAN_RX_FIFO_STD_FILTER_TYPE_C_LOW(id) \ - FLEXCAN_RX_FIFO_STD_MASK_TYPE_C_LOW( \ - id) /*!< Standard Rx FIFO Filter helper macro Type C lower part helper macro. \ \ \ \ \ \ - */ +#define FLEXCAN_RX_FIFO_STD_FILTER_TYPE_C_LOW(id) \ + FLEXCAN_RX_FIFO_STD_MASK_TYPE_C_LOW( \ + id) /*!< Standard Rx FIFO Filter helper macro Type C lower part helper macro. */ #define FLEXCAN_RX_FIFO_EXT_FILTER_TYPE_A(id, rtr, ide) \ FLEXCAN_RX_FIFO_EXT_MASK_TYPE_A(id, rtr, ide) /*!< Extend Rx FIFO Filter helper macro Type A helper macro. */ #define FLEXCAN_RX_FIFO_EXT_FILTER_TYPE_B_HIGH(id, rtr, ide) \ @@ -111,10 +115,9 @@ #define FLEXCAN_RX_FIFO_EXT_FILTER_TYPE_B_LOW(id, rtr, ide) \ FLEXCAN_RX_FIFO_EXT_MASK_TYPE_B_LOW( \ id, rtr, ide) /*!< Extend Rx FIFO Filter helper macro Type B lower part helper macro. */ -#define FLEXCAN_RX_FIFO_EXT_FILTER_TYPE_C_HIGH(id) \ - FLEXCAN_RX_FIFO_EXT_MASK_TYPE_C_HIGH( \ - id) /*!< Extend Rx FIFO Filter helper macro Type C upper part helper macro. \ \ \ \ \ \ - */ +#define FLEXCAN_RX_FIFO_EXT_FILTER_TYPE_C_HIGH(id) \ + FLEXCAN_RX_FIFO_EXT_MASK_TYPE_C_HIGH( \ + id) /*!< Extend Rx FIFO Filter helper macro Type C upper part helper macro. */ #define FLEXCAN_RX_FIFO_EXT_FILTER_TYPE_C_MID_HIGH(id) \ FLEXCAN_RX_FIFO_EXT_MASK_TYPE_C_MID_HIGH( \ id) /*!< Extend Rx FIFO Filter helper macro Type C mid-upper part helper macro. */ @@ -139,7 +142,8 @@ enum _flexcan_status kStatus_FLEXCAN_RxFifoOverflow = MAKE_STATUS(kStatusGroup_FLEXCAN, 8), /*!< Rx Message FIFO is overflowed. */ kStatus_FLEXCAN_RxFifoWarning = MAKE_STATUS(kStatusGroup_FLEXCAN, 9), /*!< Rx Message FIFO is almost overflowed. */ kStatus_FLEXCAN_ErrorStatus = MAKE_STATUS(kStatusGroup_FLEXCAN, 10), /*!< FlexCAN Module Error and Status. */ - kStatus_FLEXCAN_UnHandled = MAKE_STATUS(kStatusGroup_FLEXCAN, 11), /*!< UnHadled Interrupt asserted. */ + kStatus_FLEXCAN_WakeUp = MAKE_STATUS(kStatusGroup_FLEXCAN, 11), /*!< FlexCAN is waken up from STOP mode. */ + kStatus_FLEXCAN_UnHandled = MAKE_STATUS(kStatusGroup_FLEXCAN, 12), /*!< UnHadled Interrupt asserted. */ }; /*! @brief FlexCAN frame format. */ @@ -163,6 +167,13 @@ typedef enum _flexcan_clock_source kFLEXCAN_ClkSrcPeri = 0x1U, /*!< FlexCAN Protocol Engine clock from Peripheral Clock. */ } flexcan_clock_source_t; +/*! @brief FlexCAN wake up source. */ +typedef enum _flexcan_wake_up_source +{ + kFLEXCAN_WakeupSrcUnfiltered = 0x0U, /*!< FlexCAN uses unfiltered Rx input to detect edge. */ + kFLEXCAN_WakeupSrcFiltered = 0x1U, /*!< FlexCAN uses filtered Rx input to detect edge. */ +} flexcan_wake_up_source_t; + /*! @brief FlexCAN Rx Fifo Filter type. */ typedef enum _flexcan_rx_fifo_filter_type { @@ -241,13 +252,13 @@ enum _flexcan_flags kFLEXCAN_BusOffIntFlag = CAN_ESR1_BOFFINT_MASK, /*!< Bus Off Interrupt Flag. */ kFLEXCAN_ErrorIntFlag = CAN_ESR1_ERRINT_MASK, /*!< Error Interrupt Flag. */ kFLEXCAN_WakeUpIntFlag = CAN_ESR1_WAKINT_MASK, /*!< Wake-Up Interrupt Flag. */ - kFLEXCAN_ErrorFlag = /*!< All FlexCAN Error Status. */ + kFLEXCAN_ErrorFlag = (int)( /*!< All FlexCAN Error Status. */ #if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) - CAN_ESR1_STFERR_FAST_MASK | CAN_ESR1_FRMERR_FAST_MASK | CAN_ESR1_CRCERR_FAST_MASK | CAN_ESR1_BIT0ERR_FAST_MASK | - CAN_ESR1_BIT1ERR_FAST_MASK | CAN_ESR1_ERROVR_MASK | + CAN_ESR1_STFERR_FAST_MASK | CAN_ESR1_FRMERR_FAST_MASK | CAN_ESR1_CRCERR_FAST_MASK | + CAN_ESR1_BIT0ERR_FAST_MASK | CAN_ESR1_BIT1ERR_FAST_MASK | CAN_ESR1_ERROVR_MASK | #endif - CAN_ESR1_BIT1ERR_MASK | CAN_ESR1_BIT0ERR_MASK | CAN_ESR1_ACKERR_MASK | CAN_ESR1_CRCERR_MASK | CAN_ESR1_FRMERR_MASK | - CAN_ESR1_STFERR_MASK, + CAN_ESR1_BIT1ERR_MASK | CAN_ESR1_BIT0ERR_MASK | CAN_ESR1_ACKERR_MASK | + CAN_ESR1_CRCERR_MASK | CAN_ESR1_FRMERR_MASK | CAN_ESR1_STFERR_MASK), }; /*! @@ -260,12 +271,12 @@ enum _flexcan_flags enum _flexcan_error_flags { #if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) - kFLEXCAN_FDStuffingError = CAN_ESR1_STFERR_FAST_MASK, /*!< Stuffing Error. */ - kFLEXCAN_FDFormError = CAN_ESR1_FRMERR_FAST_MASK, /*!< Form Error. */ - kFLEXCAN_FDCrcError = CAN_ESR1_CRCERR_FAST_MASK, /*!< Cyclic Redundancy Check Error. */ - kFLEXCAN_FDBit0Error = CAN_ESR1_BIT0ERR_FAST_MASK, /*!< Unable to send dominant bit. */ - kFLEXCAN_FDBit1Error = CAN_ESR1_BIT1ERR_FAST_MASK, /*!< Unable to send recessive bit. */ - kFLEXCAN_OverrunError = CAN_ESR1_ERROVR_MASK, /*!< Error Overrun Status. */ + kFLEXCAN_FDStuffingError = CAN_ESR1_STFERR_FAST_MASK, /*!< Stuffing Error. */ + kFLEXCAN_FDFormError = CAN_ESR1_FRMERR_FAST_MASK, /*!< Form Error. */ + kFLEXCAN_FDCrcError = CAN_ESR1_CRCERR_FAST_MASK, /*!< Cyclic Redundancy Check Error. */ + kFLEXCAN_FDBit0Error = CAN_ESR1_BIT0ERR_FAST_MASK, /*!< Unable to send dominant bit. */ + kFLEXCAN_FDBit1Error = (int)CAN_ESR1_BIT1ERR_FAST_MASK, /*!< Unable to send recessive bit. */ + kFLEXCAN_OverrunError = CAN_ESR1_ERROVR_MASK, /*!< Error Overrun Status. */ #endif kFLEXCAN_StuffingError = CAN_ESR1_STFERR_MASK, /*!< Stuffing Error. */ kFLEXCAN_FormError = CAN_ESR1_FRMERR_MASK, /*!< Form Error. */ @@ -343,11 +354,11 @@ typedef struct _flexcan_fd_frame uint32_t format : 1; /*!< CAN Frame Identifier(STD or EXT format). */ uint32_t srr : 1; /*!< Substitute Remote request. */ uint32_t : 1; - uint32_t code : 4; /*!< Message Buffer Code. */ + uint32_t code : 4; /*!< Message Buffer Code. */ uint32_t : 1; - uint32_t esi : 1; /*!< Error State Indicator. */ - uint32_t brs : 1; /*!< Bit Rate Switch. */ - uint32_t edl : 1; /*!< Extended Data Length. */ + uint32_t esi : 1; /*!< Error State Indicator. */ + uint32_t brs : 1; /*!< Bit Rate Switch. */ + uint32_t edl : 1; /*!< Extended Data Length. */ }; struct { @@ -401,12 +412,13 @@ typedef struct _flexcan_config #if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) uint32_t baudRateFD; /*!< FlexCAN FD baud rate in bps. */ #endif - flexcan_clock_source_t clkSrc; /*!< Clock source for FlexCAN Protocol Engine. */ - uint8_t maxMbNum; /*!< The maximum number of Message Buffers used by user. */ - bool enableLoopBack; /*!< Enable or Disable Loop Back Self Test Mode. */ - bool enableTimerSync; /*!< Enable or Disable Timer Synchronization. */ - bool enableSelfWakeup; /*!< Enable or Disable Self Wakeup Mode. */ - bool enableIndividMask; /*!< Enable or Disable Rx Individual Mask. */ + flexcan_clock_source_t clkSrc; /*!< Clock source for FlexCAN Protocol Engine. */ + flexcan_wake_up_source_t wakeupSrc; /*!< Wake up source selection. */ + uint8_t maxMbNum; /*!< The maximum number of Message Buffers used by user. */ + bool enableLoopBack; /*!< Enable or Disable Loop Back Self Test Mode. */ + bool enableTimerSync; /*!< Enable or Disable Timer Synchronization. */ + bool enableSelfWakeup; /*!< Enable or Disable Self Wakeup Mode. */ + bool enableIndividMask; /*!< Enable or Disable Rx Individual Mask. */ #if (defined(FSL_FEATURE_FLEXCAN_HAS_DOZE_MODE_SUPPORT) && FSL_FEATURE_FLEXCAN_HAS_DOZE_MODE_SUPPORT) bool enableDoze; /*!< Enable or Disable Doze Mode. */ #endif @@ -559,7 +571,8 @@ void FLEXCAN_Init(CAN_Type *base, const flexcan_config_t *config, uint32_t sourc * @param dataSize FlexCAN FD frame payload size. * @param brs If bitrate switch is enabled in FD mode. */ -void FLEXCAN_FDInit(CAN_Type *base, const flexcan_config_t *config, uint32_t sourceClock_Hz, flexcan_mb_size_t dataSize, bool brs); +void FLEXCAN_FDInit( + CAN_Type *base, const flexcan_config_t *config, uint32_t sourceClock_Hz, flexcan_mb_size_t dataSize, bool brs); #endif /*! diff --git a/ext/hal/nxp/mcux/drivers/imx/fsl_flexio.c b/ext/hal/nxp/mcux/drivers/imx/fsl_flexio.c index b5d9c863278..f3c45f624cd 100644 --- a/ext/hal/nxp/mcux/drivers/imx/fsl_flexio.c +++ b/ext/hal/nxp/mcux/drivers/imx/fsl_flexio.c @@ -2,7 +2,7 @@ * Copyright (c) 2015, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP * All rights reserved. - * + * * SPDX-License-Identifier: BSD-3-Clause */ @@ -17,7 +17,6 @@ #define FSL_COMPONENT_ID "platform.drivers.flexio" #endif - /*< @brief user configurable flexio handle count. */ #define FLEXIO_HANDLE_COUNT 2 @@ -45,6 +44,11 @@ static flexio_isr_t s_flexioIsr[FLEXIO_HANDLE_COUNT]; * Codes ******************************************************************************/ +/*! + * brief Get instance number for FLEXIO module. + * + * param base FLEXIO peripheral base address. + */ uint32_t FLEXIO_GetInstance(FLEXIO_Type *base) { uint32_t instance; @@ -63,6 +67,24 @@ uint32_t FLEXIO_GetInstance(FLEXIO_Type *base) return instance; } +/*! + * brief Configures the FlexIO with a FlexIO configuration. The configuration structure + * can be filled by the user or be set with default values by FLEXIO_GetDefaultConfig(). + * + * Example + code + flexio_config_t config = { + .enableFlexio = true, + .enableInDoze = false, + .enableInDebug = true, + .enableFastAccess = false + }; + FLEXIO_Configure(base, &config); + endcode + * + * param base FlexIO peripheral base address + * param userConfig pointer to flexio_config_t structure +*/ void FLEXIO_Init(FLEXIO_Type *base, const flexio_config_t *userConfig) { uint32_t ctrlReg = 0; @@ -85,6 +107,13 @@ void FLEXIO_Init(FLEXIO_Type *base, const flexio_config_t *userConfig) base->CTRL = ctrlReg; } +/*! + * brief Gates the FlexIO clock. Call this API to stop the FlexIO clock. + * + * note After calling this API, call the FLEXO_Init to use the FlexIO module. + * + * param base FlexIO peripheral base address +*/ void FLEXIO_Deinit(FLEXIO_Type *base) { FLEXIO_Enable(base, false); @@ -93,16 +122,36 @@ void FLEXIO_Deinit(FLEXIO_Type *base) #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ } +/*! + * brief Gets the default configuration to configure the FlexIO module. The configuration + * can used directly to call the FLEXIO_Configure(). + * + * Example: + code + flexio_config_t config; + FLEXIO_GetDefaultConfig(&config); + endcode + * + * param userConfig pointer to flexio_config_t structure +*/ void FLEXIO_GetDefaultConfig(flexio_config_t *userConfig) { assert(userConfig); + /* Initializes the configure structure to zero. */ + memset(userConfig, 0, sizeof(*userConfig)); + userConfig->enableFlexio = true; userConfig->enableInDoze = false; userConfig->enableInDebug = true; userConfig->enableFastAccess = false; } +/*! + * brief Resets the FlexIO module. + * + * param base FlexIO peripheral base address +*/ void FLEXIO_Reset(FLEXIO_Type *base) { /*do software reset, software reset operation affect all other FLEXIO registers except CTRL*/ @@ -110,6 +159,14 @@ void FLEXIO_Reset(FLEXIO_Type *base) base->CTRL = 0; } +/*! + * brief Gets the shifter buffer address for the DMA transfer usage. + * + * param base FlexIO peripheral base address + * param type Shifter type of flexio_shifter_buffer_type_t + * param index Shifter index + * return Corresponding shifter buffer index +*/ uint32_t FLEXIO_GetShifterBufferAddress(FLEXIO_Type *base, flexio_shifter_buffer_type_t type, uint8_t index) { assert(index < FLEXIO_SHIFTBUF_COUNT); @@ -158,6 +215,31 @@ uint32_t FLEXIO_GetShifterBufferAddress(FLEXIO_Type *base, flexio_shifter_buffer return address; } +/*! + * brief Configures the shifter with the shifter configuration. The configuration structure + * covers both the SHIFTCTL and SHIFTCFG registers. To configure the shifter to the proper + * mode, select which timer controls the shifter to shift, whether to generate start bit/stop + * bit, and the polarity of start bit and stop bit. + * + * Example + code + flexio_shifter_config_t config = { + .timerSelect = 0, + .timerPolarity = kFLEXIO_ShifterTimerPolarityOnPositive, + .pinConfig = kFLEXIO_PinConfigOpenDrainOrBidirection, + .pinPolarity = kFLEXIO_PinActiveLow, + .shifterMode = kFLEXIO_ShifterModeTransmit, + .inputSource = kFLEXIO_ShifterInputFromPin, + .shifterStop = kFLEXIO_ShifterStopBitHigh, + .shifterStart = kFLEXIO_ShifterStartBitLow + }; + FLEXIO_SetShifterConfig(base, &config); + endcode + * + * param base FlexIO peripheral base address + * param index Shifter index + * param shifterConfig Pointer to flexio_shifter_config_t structure +*/ void FLEXIO_SetShifterConfig(FLEXIO_Type *base, uint8_t index, const flexio_shifter_config_t *shifterConfig) { base->SHIFTCFG[index] = FLEXIO_SHIFTCFG_INSRC(shifterConfig->inputSource) @@ -173,6 +255,36 @@ void FLEXIO_SetShifterConfig(FLEXIO_Type *base, uint8_t index, const flexio_shif FLEXIO_SHIFTCTL_PINPOL(shifterConfig->pinPolarity) | FLEXIO_SHIFTCTL_SMOD(shifterConfig->shifterMode); } +/*! + * brief Configures the timer with the timer configuration. The configuration structure + * covers both the TIMCTL and TIMCFG registers. To configure the timer to the proper + * mode, select trigger source for timer and the timer pin output and the timing for timer. + * + * Example + code + flexio_timer_config_t config = { + .triggerSelect = FLEXIO_TIMER_TRIGGER_SEL_SHIFTnSTAT(0), + .triggerPolarity = kFLEXIO_TimerTriggerPolarityActiveLow, + .triggerSource = kFLEXIO_TimerTriggerSourceInternal, + .pinConfig = kFLEXIO_PinConfigOpenDrainOrBidirection, + .pinSelect = 0, + .pinPolarity = kFLEXIO_PinActiveHigh, + .timerMode = kFLEXIO_TimerModeDual8BitBaudBit, + .timerOutput = kFLEXIO_TimerOutputZeroNotAffectedByReset, + .timerDecrement = kFLEXIO_TimerDecSrcOnFlexIOClockShiftTimerOutput, + .timerReset = kFLEXIO_TimerResetOnTimerPinEqualToTimerOutput, + .timerDisable = kFLEXIO_TimerDisableOnTimerCompare, + .timerEnable = kFLEXIO_TimerEnableOnTriggerHigh, + .timerStop = kFLEXIO_TimerStopBitEnableOnTimerDisable, + .timerStart = kFLEXIO_TimerStartBitEnabled + }; + FLEXIO_SetTimerConfig(base, &config); + endcode + * + * param base FlexIO peripheral base address + * param index Timer index + * param timerConfig Pointer to the flexio_timer_config_t structure +*/ void FLEXIO_SetTimerConfig(FLEXIO_Type *base, uint8_t index, const flexio_timer_config_t *timerConfig) { base->TIMCFG[index] = @@ -190,6 +302,15 @@ void FLEXIO_SetTimerConfig(FLEXIO_Type *base, uint8_t index, const flexio_timer_ FLEXIO_TIMCTL_PINPOL(timerConfig->pinPolarity) | FLEXIO_TIMCTL_TIMOD(timerConfig->timerMode); } +/*! + * brief Registers the handle and the interrupt handler for the FlexIO-simulated peripheral. + * + * param base Pointer to the FlexIO simulated peripheral type. + * param handle Pointer to the handler for FlexIO simulated peripheral. + * param isr FlexIO simulated peripheral interrupt handler. + * retval kStatus_Success Successfully create the handle. + * retval kStatus_OutOfRange The FlexIO type/handle/ISR table out of range. +*/ status_t FLEXIO_RegisterHandleIRQ(void *base, void *handle, flexio_isr_t isr) { assert(base); @@ -221,6 +342,13 @@ status_t FLEXIO_RegisterHandleIRQ(void *base, void *handle, flexio_isr_t isr) } } +/*! + * brief Unregisters the handle and the interrupt handler for the FlexIO-simulated peripheral. + * + * param base Pointer to the FlexIO simulated peripheral type. + * retval kStatus_Success Successfully create the handle. + * retval kStatus_OutOfRange The FlexIO type/handle/ISR table out of range. +*/ status_t FLEXIO_UnregisterHandleIRQ(void *base) { assert(base); diff --git a/ext/hal/nxp/mcux/drivers/imx/fsl_flexio.h b/ext/hal/nxp/mcux/drivers/imx/fsl_flexio.h index cd9fbfe5c55..da74e1f4540 100644 --- a/ext/hal/nxp/mcux/drivers/imx/fsl_flexio.h +++ b/ext/hal/nxp/mcux/drivers/imx/fsl_flexio.h @@ -151,8 +151,8 @@ typedef enum _flexio_timer_start_bit_condition /*! @brief Define type of timer polarity for shifter control. */ typedef enum _flexio_shifter_timer_polarity { - kFLEXIO_ShifterTimerPolarityOnPositive = 0x0U, /* Shift on positive edge of shift clock. */ - kFLEXIO_ShifterTimerPolarityOnNegitive = 0x1U, /* Shift on negative edge of shift clock. */ + kFLEXIO_ShifterTimerPolarityOnPositive = 0x0U, /*!< Shift on positive edge of shift clock. */ + kFLEXIO_ShifterTimerPolarityOnNegitive = 0x1U, /*!< Shift on negative edge of shift clock. */ } flexio_shifter_timer_polarity_t; /*! @brief Define type of shifter working mode.*/ diff --git a/ext/hal/nxp/mcux/drivers/imx/fsl_flexio_i2c_master.c b/ext/hal/nxp/mcux/drivers/imx/fsl_flexio_i2c_master.c index e448d1a8cdf..fc060d9e9ab 100644 --- a/ext/hal/nxp/mcux/drivers/imx/fsl_flexio_i2c_master.c +++ b/ext/hal/nxp/mcux/drivers/imx/fsl_flexio_i2c_master.c @@ -353,6 +353,34 @@ static void FLEXIO_I2C_MasterTransferComplete(FLEXIO_I2C_Type *base, } } +/*! + * brief Ungates the FlexIO clock, resets the FlexIO module, and configures the FlexIO I2C + * hardware configuration. + * + * Example + code + FLEXIO_I2C_Type base = { + .flexioBase = FLEXIO, + .SDAPinIndex = 0, + .SCLPinIndex = 1, + .shifterIndex = {0,1}, + .timerIndex = {0,1} + }; + flexio_i2c_master_config_t config = { + .enableInDoze = false, + .enableInDebug = true, + .enableFastAccess = false, + .baudRate_Bps = 100000 + }; + FLEXIO_I2C_MasterInit(base, &config, srcClock_Hz); + endcode + * + * param base Pointer to FLEXIO_I2C_Type structure. + * param masterConfig Pointer to flexio_i2c_master_config_t structure. + * param srcClock_Hz FlexIO source clock in Hz. + * retval kStatus_Success Initialization successful + * retval kStatus_InvalidArgument The source clock exceed upper range limitation +*/ status_t FLEXIO_I2C_MasterInit(FLEXIO_I2C_Type *base, flexio_i2c_master_config_t *masterConfig, uint32_t srcClock_Hz) { assert(base && masterConfig); @@ -463,6 +491,12 @@ status_t FLEXIO_I2C_MasterInit(FLEXIO_I2C_Type *base, flexio_i2c_master_config_t return result; } +/*! + * brief De-initializes the FlexIO I2C master peripheral. Calling this API Resets the FlexIO I2C master + * shifer and timer config, module can't work unless the FLEXIO_I2C_MasterInit is called. + * + * param base pointer to FLEXIO_I2C_Type structure. + */ void FLEXIO_I2C_MasterDeinit(FLEXIO_I2C_Type *base) { base->flexioBase->SHIFTCFG[base->shifterIndex[0]] = 0; @@ -483,10 +517,24 @@ void FLEXIO_I2C_MasterDeinit(FLEXIO_I2C_Type *base) base->flexioBase->TIMSTAT = (1U << base->timerIndex[1]); } +/*! + * brief Gets the default configuration to configure the FlexIO module. The configuration + * can be used directly for calling the FLEXIO_I2C_MasterInit(). + * + * Example: + code + flexio_i2c_master_config_t config; + FLEXIO_I2C_MasterGetDefaultConfig(&config); + endcode + * param masterConfig Pointer to flexio_i2c_master_config_t structure. +*/ void FLEXIO_I2C_MasterGetDefaultConfig(flexio_i2c_master_config_t *masterConfig) { assert(masterConfig); + /* Initializes the configure structure to zero. */ + memset(masterConfig, 0, sizeof(*masterConfig)); + masterConfig->enableMaster = true; masterConfig->enableInDoze = false; masterConfig->enableInDebug = true; @@ -496,6 +544,13 @@ void FLEXIO_I2C_MasterGetDefaultConfig(flexio_i2c_master_config_t *masterConfig) masterConfig->baudRate_Bps = 100000U; } +/*! + * brief Gets the FlexIO I2C master status flags. + * + * param base Pointer to FLEXIO_I2C_Type structure + * return Status flag, use status flag to AND #_flexio_i2c_master_status_flags can get the related status. +*/ + uint32_t FLEXIO_I2C_MasterGetStatusFlags(FLEXIO_I2C_Type *base) { uint32_t status = 0; @@ -512,6 +567,16 @@ uint32_t FLEXIO_I2C_MasterGetStatusFlags(FLEXIO_I2C_Type *base) return status; } +/*! + * brief Clears the FlexIO I2C master status flags. + * + * param base Pointer to FLEXIO_I2C_Type structure. + * param mask Status flag. + * The parameter can be any combination of the following values: + * arg kFLEXIO_I2C_RxFullFlag + * arg kFLEXIO_I2C_ReceiveNakFlag +*/ + void FLEXIO_I2C_MasterClearStatusFlags(FLEXIO_I2C_Type *base, uint32_t mask) { if (mask & kFLEXIO_I2C_TxEmptyFlag) @@ -530,6 +595,14 @@ void FLEXIO_I2C_MasterClearStatusFlags(FLEXIO_I2C_Type *base, uint32_t mask) } } +/*! + * brief Enables the FlexIO i2c master interrupt requests. + * + * param base Pointer to FLEXIO_I2C_Type structure. + * param mask Interrupt source. + * Currently only one interrupt request source: + * arg kFLEXIO_I2C_TransferCompleteInterruptEnable + */ void FLEXIO_I2C_MasterEnableInterrupts(FLEXIO_I2C_Type *base, uint32_t mask) { if (mask & kFLEXIO_I2C_TxEmptyInterruptEnable) @@ -542,6 +615,12 @@ void FLEXIO_I2C_MasterEnableInterrupts(FLEXIO_I2C_Type *base, uint32_t mask) } } +/*! + * brief Disables the FlexIO I2C master interrupt requests. + * + * param base Pointer to FLEXIO_I2C_Type structure. + * param mask Interrupt source. + */ void FLEXIO_I2C_MasterDisableInterrupts(FLEXIO_I2C_Type *base, uint32_t mask) { if (mask & kFLEXIO_I2C_TxEmptyInterruptEnable) @@ -554,6 +633,13 @@ void FLEXIO_I2C_MasterDisableInterrupts(FLEXIO_I2C_Type *base, uint32_t mask) } } +/*! + * brief Sets the FlexIO I2C master transfer baudrate. + * + * param base Pointer to FLEXIO_I2C_Type structure + * param baudRate_Bps the baud rate value in HZ + * param srcClock_Hz source clock in HZ + */ void FLEXIO_I2C_MasterSetBaudRate(FLEXIO_I2C_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz) { uint16_t timerDiv = 0; @@ -571,6 +657,17 @@ void FLEXIO_I2C_MasterSetBaudRate(FLEXIO_I2C_Type *base, uint32_t baudRate_Bps, flexioBase->TIMCMP[base->timerIndex[0]] = timerCmp; } +/*! + * brief Sets the number of bytes to be transferred from a start signal to a stop signal. + * + * note Call this API before a transfer begins because the timer generates a number of clocks according + * to the number of bytes that need to be transferred. + * + * param base Pointer to FLEXIO_I2C_Type structure. + * param count Number of bytes need to be transferred from a start signal to a re-start/stop signal + * retval kStatus_Success Successfully configured the count. + * retval kStatus_InvalidArgument Input argument is invalid. +*/ status_t FLEXIO_I2C_MasterSetTransferCount(FLEXIO_I2C_Type *base, uint8_t count) { if (count > 14U) @@ -594,6 +691,21 @@ status_t FLEXIO_I2C_MasterSetTransferCount(FLEXIO_I2C_Type *base, uint8_t count) return kStatus_Success; } +/*! + * brief Sends START + 7-bit address to the bus. + * + * note This API should be called when the transfer configuration is ready to send a START signal + * and 7-bit address to the bus. This is a non-blocking API, which returns directly after the address + * is put into the data register but the address transfer is not finished on the bus. Ensure that + * the kFLEXIO_I2C_RxFullFlag status is asserted before calling this API. + * param base Pointer to FLEXIO_I2C_Type structure. + * param address 7-bit address. + * param direction transfer direction. + * This parameter is one of the values in flexio_i2c_direction_t: + * arg kFLEXIO_I2C_Write: Transmit + * arg kFLEXIO_I2C_Read: Receive + */ + void FLEXIO_I2C_MasterStart(FLEXIO_I2C_Type *base, uint8_t address, flexio_i2c_direction_t direction) { uint32_t data; @@ -603,12 +715,22 @@ void FLEXIO_I2C_MasterStart(FLEXIO_I2C_Type *base, uint8_t address, flexio_i2c_d FLEXIO_I2C_MasterWriteByte(base, data); } +/*! + * brief Sends the repeated start signal on the bus. + * + * param base Pointer to FLEXIO_I2C_Type structure. + */ void FLEXIO_I2C_MasterRepeatedStart(FLEXIO_I2C_Type *base) { /* Prepare for RESTART condition, no stop.*/ FLEXIO_I2C_MasterWriteByte(base, 0xFFFFFFFFU); } +/*! + * brief Sends the stop signal on the bus. + * + * param base Pointer to FLEXIO_I2C_Type structure. + */ void FLEXIO_I2C_MasterStop(FLEXIO_I2C_Type *base) { /* Prepare normal stop. */ @@ -616,6 +738,11 @@ void FLEXIO_I2C_MasterStop(FLEXIO_I2C_Type *base) FLEXIO_I2C_MasterWriteByte(base, 0x0U); } +/*! + * brief Sends the stop signal when transfer is still on-going. + * + * param base Pointer to FLEXIO_I2C_Type structure. + */ void FLEXIO_I2C_MasterAbortStop(FLEXIO_I2C_Type *base) { uint32_t tmpConfig; @@ -627,6 +754,12 @@ void FLEXIO_I2C_MasterAbortStop(FLEXIO_I2C_Type *base) base->flexioBase->TIMCFG[base->timerIndex[0]] = tmpConfig; } +/*! + * brief Configures the sent ACK/NAK for the following byte. + * + * param base Pointer to FLEXIO_I2C_Type structure. + * param enable True to configure send ACK, false configure to send NAK. + */ void FLEXIO_I2C_MasterEnableAck(FLEXIO_I2C_Type *base, bool enable) { uint32_t tmpConfig = 0; @@ -644,6 +777,17 @@ void FLEXIO_I2C_MasterEnableAck(FLEXIO_I2C_Type *base, bool enable) base->flexioBase->SHIFTCFG[base->shifterIndex[0]] = tmpConfig; } +/*! + * brief Sends a buffer of data in bytes. + * + * note This function blocks via polling until all bytes have been sent. + * + * param base Pointer to FLEXIO_I2C_Type structure. + * param txBuff The data bytes to send. + * param txSize The number of data bytes to send. + * retval kStatus_Success Successfully write data. + * retval kStatus_FLEXIO_I2C_Nak Receive NAK during writing data. + */ status_t FLEXIO_I2C_MasterWriteBlocking(FLEXIO_I2C_Type *base, const uint8_t *txBuff, uint8_t txSize) { assert(txBuff); @@ -669,6 +813,15 @@ status_t FLEXIO_I2C_MasterWriteBlocking(FLEXIO_I2C_Type *base, const uint8_t *tx return kStatus_Success; } +/*! + * brief Receives a buffer of bytes. + * + * note This function blocks via polling until all bytes have been received. + * + * param base Pointer to FLEXIO_I2C_Type structure. + * param rxBuff The buffer to store the received bytes. + * param rxSize The number of data bytes to be received. + */ void FLEXIO_I2C_MasterReadBlocking(FLEXIO_I2C_Type *base, uint8_t *rxBuff, uint8_t rxSize) { assert(rxBuff); @@ -685,6 +838,16 @@ void FLEXIO_I2C_MasterReadBlocking(FLEXIO_I2C_Type *base, uint8_t *rxBuff, uint8 } } +/*! + * brief Performs a master polling transfer on the I2C bus. + * + * note The API does not return until the transfer succeeds or fails due + * to receiving NAK. + * + * param base pointer to FLEXIO_I2C_Type structure. + * param xfer pointer to flexio_i2c_master_transfer_t structure. + * return status of status_t. + */ status_t FLEXIO_I2C_MasterTransferBlocking(FLEXIO_I2C_Type *base, flexio_i2c_master_transfer_t *xfer) { assert(xfer); @@ -714,6 +877,16 @@ status_t FLEXIO_I2C_MasterTransferBlocking(FLEXIO_I2C_Type *base, flexio_i2c_mas return result; } +/*! + * brief Initializes the I2C handle which is used in transactional functions. + * + * param base Pointer to FLEXIO_I2C_Type structure. + * param handle Pointer to flexio_i2c_master_handle_t structure to store the transfer state. + * param callback Pointer to user callback function. + * param userData User param passed to the callback function. + * retval kStatus_Success Successfully create the handle. + * retval kStatus_OutOfRange The FlexIO type/handle/isr table out of range. + */ status_t FLEXIO_I2C_MasterTransferCreateHandle(FLEXIO_I2C_Type *base, flexio_i2c_master_handle_t *handle, flexio_i2c_master_transfer_callback_t callback, @@ -737,6 +910,20 @@ status_t FLEXIO_I2C_MasterTransferCreateHandle(FLEXIO_I2C_Type *base, return FLEXIO_RegisterHandleIRQ(base, handle, FLEXIO_I2C_MasterTransferHandleIRQ); } +/*! + * brief Performs a master interrupt non-blocking transfer on the I2C bus. + * + * note The API returns immediately after the transfer initiates. + * Call FLEXIO_I2C_MasterGetTransferCount to poll the transfer status to check whether + * the transfer is finished. If the return status is not kStatus_FLEXIO_I2C_Busy, the transfer + * is finished. + * + * param base Pointer to FLEXIO_I2C_Type structure + * param handle Pointer to flexio_i2c_master_handle_t structure which stores the transfer state + * param xfer pointer to flexio_i2c_master_transfer_t structure + * retval kStatus_Success Successfully start a transfer. + * retval kStatus_FLEXIO_I2C_Busy FlexIO I2C is not idle, is running another transfer. + */ status_t FLEXIO_I2C_MasterTransferNonBlocking(FLEXIO_I2C_Type *base, flexio_i2c_master_handle_t *handle, flexio_i2c_master_transfer_t *xfer) @@ -760,6 +947,15 @@ status_t FLEXIO_I2C_MasterTransferNonBlocking(FLEXIO_I2C_Type *base, } } +/*! + * brief Aborts an interrupt non-blocking transfer early. + * + * note This API can be called at any time when an interrupt non-blocking transfer initiates + * to abort the transfer early. + * + * param base Pointer to FLEXIO_I2C_Type structure + * param handle Pointer to flexio_i2c_master_handle_t structure which stores the transfer state + */ void FLEXIO_I2C_MasterTransferAbort(FLEXIO_I2C_Type *base, flexio_i2c_master_handle_t *handle) { assert(handle); @@ -771,6 +967,15 @@ void FLEXIO_I2C_MasterTransferAbort(FLEXIO_I2C_Type *base, flexio_i2c_master_han handle->state = kFLEXIO_I2C_Idle; } +/*! + * brief Gets the master transfer status during a interrupt non-blocking transfer. + * + * param base Pointer to FLEXIO_I2C_Type structure. + * param handle Pointer to flexio_i2c_master_handle_t structure which stores the transfer state. + * param count Number of bytes transferred so far by the non-blocking transaction. + * retval kStatus_InvalidArgument count is Invalid. + * retval kStatus_Success Successfully return the count. + */ status_t FLEXIO_I2C_MasterTransferGetCount(FLEXIO_I2C_Type *base, flexio_i2c_master_handle_t *handle, size_t *count) { if (!count) @@ -783,6 +988,12 @@ status_t FLEXIO_I2C_MasterTransferGetCount(FLEXIO_I2C_Type *base, flexio_i2c_mas return kStatus_Success; } +/*! + * brief Master interrupt handler. + * + * param i2cType Pointer to FLEXIO_I2C_Type structure + * param i2cHandle Pointer to flexio_i2c_master_transfer_t structure + */ void FLEXIO_I2C_MasterTransferHandleIRQ(void *i2cType, void *i2cHandle) { FLEXIO_I2C_Type *base = (FLEXIO_I2C_Type *)i2cType; diff --git a/ext/hal/nxp/mcux/drivers/imx/fsl_flexio_i2s.c b/ext/hal/nxp/mcux/drivers/imx/fsl_flexio_i2s.c index ae96d9e64fb..41457284a41 100644 --- a/ext/hal/nxp/mcux/drivers/imx/fsl_flexio_i2s.c +++ b/ext/hal/nxp/mcux/drivers/imx/fsl_flexio_i2s.c @@ -1,8 +1,8 @@ /* * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP + * Copyright 2016-2018 NXP * All rights reserved. - * + * * SPDX-License-Identifier: BSD-3-Clause */ @@ -13,7 +13,6 @@ #define FSL_COMPONENT_ID "platform.drivers.flexio_i2s" #endif - /******************************************************************************* * Definitations ******************************************************************************/ @@ -75,7 +74,7 @@ static void FLEXIO_I2S_WriteNonBlocking(FLEXIO_I2S_Type *base, uint8_t bitWidth, data |= (temp << (8U * j)); txData++; } - base->flexioBase->SHIFTBUFBIS[base->txShifterIndex] = (data << (32U - bitWidth)); + base->flexioBase->SHIFTBUFBIS[base->txShifterIndex] = data << (32U - bitWidth); data = 0; } } @@ -89,7 +88,7 @@ static void FLEXIO_I2S_ReadNonBlocking(FLEXIO_I2S_Type *base, uint8_t bitWidth, for (i = 0; i < size / bytesPerWord; i++) { - data = (base->flexioBase->SHIFTBUFBIS[base->rxShifterIndex] >> (32U - bitWidth)); + data = (base->flexioBase->SHIFTBUFBIS[base->rxShifterIndex]); for (j = 0; j < bytesPerWord; j++) { *rxData = (data >> (8U * j)) & 0xFF; @@ -98,6 +97,20 @@ static void FLEXIO_I2S_ReadNonBlocking(FLEXIO_I2S_Type *base, uint8_t bitWidth, } } +/*! + * brief Initializes the FlexIO I2S. + * + * This API configures FlexIO pins and shifter to I2S and configures the FlexIO I2S with a configuration structure. + * The configuration structure can be filled by the user, or be set with default values by + * FLEXIO_I2S_GetDefaultConfig(). + * + * note This API should be called at the beginning of the application to use + * the FlexIO I2S driver. Otherwise, any access to the FlexIO I2S module can cause hard fault + * because the clock is not enabled. + * + * param base FlexIO I2S base pointer + * param config FlexIO I2S configure structure. +*/ void FLEXIO_I2S_Init(FLEXIO_I2S_Type *base, const flexio_i2s_config_t *config) { assert(base && config); @@ -110,6 +123,9 @@ void FLEXIO_I2S_Init(FLEXIO_I2S_Type *base, const flexio_i2s_config_t *config) CLOCK_EnableClock(s_flexioClocks[FLEXIO_I2S_GetInstance(base)]); #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + /* reset Flexio */ + FLEXIO_Reset(base->flexioBase); + /* Set shifter for I2S Tx data */ shifterConfig.timerSelect = base->bclkTimerIndex; shifterConfig.pinSelect = base->txPinIndex; @@ -228,8 +244,20 @@ void FLEXIO_I2S_Init(FLEXIO_I2S_Type *base, const flexio_i2s_config_t *config) } } +/*! + * brief Sets the FlexIO I2S configuration structure to default values. + * + * The purpose of this API is to get the configuration structure initialized for use in FLEXIO_I2S_Init(). + * Users may use the initialized structure unchanged in FLEXIO_I2S_Init() or modify + * some fields of the structure before calling FLEXIO_I2S_Init(). + * + * param config pointer to master configuration structure + */ void FLEXIO_I2S_GetDefaultConfig(flexio_i2s_config_t *config) { + /* Initializes the configure structure to zero. */ + memset(config, 0, sizeof(*config)); + config->masterSlave = kFLEXIO_I2S_Master; config->enableI2S = true; config->txPinPolarity = kFLEXIO_PinActiveHigh; @@ -240,6 +268,14 @@ void FLEXIO_I2S_GetDefaultConfig(flexio_i2s_config_t *config) config->rxTimerPolarity = kFLEXIO_ShifterTimerPolarityOnNegitive; } +/*! + * brief De-initializes the FlexIO I2S. + * + * Calling this API resets the FlexIO I2S shifter and timer config. After calling this API, + * call the FLEXO_I2S_Init to use the FlexIO I2S module. + * + * param base FlexIO I2S base pointer +*/ void FLEXIO_I2S_Deinit(FLEXIO_I2S_Type *base) { base->flexioBase->SHIFTCFG[base->txShifterIndex] = 0; @@ -254,6 +290,14 @@ void FLEXIO_I2S_Deinit(FLEXIO_I2S_Type *base) base->flexioBase->TIMCTL[base->bclkTimerIndex] = 0; } +/*! + * brief Enables the FlexIO I2S interrupt. + * + * This function enables the FlexIO UART interrupt. + * + * param base Pointer to FLEXIO_I2S_Type structure + * param mask interrupt source + */ void FLEXIO_I2S_EnableInterrupts(FLEXIO_I2S_Type *base, uint32_t mask) { if (mask & kFLEXIO_I2S_TxDataRegEmptyInterruptEnable) @@ -266,6 +310,12 @@ void FLEXIO_I2S_EnableInterrupts(FLEXIO_I2S_Type *base, uint32_t mask) } } +/*! + * brief Gets the FlexIO I2S status flags. + * + * param base Pointer to FLEXIO_I2S_Type structure + * return Status flag, which are ORed by the enumerators in the _flexio_i2s_status_flags. +*/ uint32_t FLEXIO_I2S_GetStatusFlags(FLEXIO_I2S_Type *base) { uint32_t status = 0; @@ -276,6 +326,14 @@ uint32_t FLEXIO_I2S_GetStatusFlags(FLEXIO_I2S_Type *base) return status; } +/*! + * brief Disables the FlexIO I2S interrupt. + * + * This function enables the FlexIO UART interrupt. + * + * param base pointer to FLEXIO_I2S_Type structure + * param mask interrupt source + */ void FLEXIO_I2S_DisableInterrupts(FLEXIO_I2S_Type *base, uint32_t mask) { if (mask & kFLEXIO_I2S_TxDataRegEmptyInterruptEnable) @@ -288,9 +346,19 @@ void FLEXIO_I2S_DisableInterrupts(FLEXIO_I2S_Type *base, uint32_t mask) } } +/*! + * brief Configures the FlexIO I2S audio format in master mode. + * + * Audio format can be changed in run-time of FlexIO I2S. This function configures the sample rate and audio data + * format to be transferred. + * + * param base Pointer to FLEXIO_I2S_Type structure + * param format Pointer to FlexIO I2S audio data format structure. + * param srcClock_Hz I2S master clock source frequency in Hz. +*/ void FLEXIO_I2S_MasterSetFormat(FLEXIO_I2S_Type *base, flexio_i2s_format_t *format, uint32_t srcClock_Hz) { - uint32_t timDiv = srcClock_Hz / (format->sampleRate_Hz * 32U * 2U); + uint32_t timDiv = srcClock_Hz / (format->sampleRate_Hz * format->bitWidth * 2U); uint32_t bclkDiv = 0; /* Shall keep bclk and fs div an integer */ @@ -299,22 +367,41 @@ void FLEXIO_I2S_MasterSetFormat(FLEXIO_I2S_Type *base, flexio_i2s_format_t *form timDiv += 1U; } /* Set Frame sync timer cmp */ - base->flexioBase->TIMCMP[base->fsTimerIndex] = FLEXIO_TIMCMP_CMP(32U * timDiv - 1U); + base->flexioBase->TIMCMP[base->fsTimerIndex] = FLEXIO_TIMCMP_CMP(format->bitWidth * timDiv - 1U); /* Set bit clock timer cmp */ - bclkDiv = ((timDiv / 2U - 1U) | (63U << 8U)); + bclkDiv = ((timDiv / 2U - 1U) | ((format->bitWidth * 2U - 1U) << 8U)); base->flexioBase->TIMCMP[base->bclkTimerIndex] = FLEXIO_TIMCMP_CMP(bclkDiv); } +/*! + * brief Configures the FlexIO I2S audio format in slave mode. + * + * Audio format can be changed in run-time of FlexIO I2S. This function configures the sample rate and audio data + * format to be transferred. + * + * param base Pointer to FLEXIO_I2S_Type structure + * param format Pointer to FlexIO I2S audio data format structure. +*/ void FLEXIO_I2S_SlaveSetFormat(FLEXIO_I2S_Type *base, flexio_i2s_format_t *format) { /* Set Frame sync timer cmp */ - base->flexioBase->TIMCMP[base->fsTimerIndex] = FLEXIO_TIMCMP_CMP(32U * 4U - 3U); + base->flexioBase->TIMCMP[base->fsTimerIndex] = FLEXIO_TIMCMP_CMP(format->bitWidth * 4U - 3U); /* Set bit clock timer cmp */ - base->flexioBase->TIMCMP[base->bclkTimerIndex] = FLEXIO_TIMCMP_CMP(32U * 2U - 1U); + base->flexioBase->TIMCMP[base->bclkTimerIndex] = FLEXIO_TIMCMP_CMP(format->bitWidth * 2U - 1U); } +/*! + * brief Sends data using a blocking method. + * + * note This function blocks via polling until data is ready to be sent. + * + * param base FlexIO I2S base pointer. + * param bitWidth How many bits in a audio word, usually 8/16/24/32 bits. + * param txData Pointer to the data to be written. + * param size Bytes to be written. + */ void FLEXIO_I2S_WriteBlocking(FLEXIO_I2S_Type *base, uint8_t bitWidth, uint8_t *txData, size_t size) { uint32_t i = 0; @@ -337,6 +424,16 @@ void FLEXIO_I2S_WriteBlocking(FLEXIO_I2S_Type *base, uint8_t bitWidth, uint8_t * } } +/*! + * brief Receives a piece of data using a blocking method. + * + * note This function blocks via polling until data is ready to be sent. + * + * param base FlexIO I2S base pointer + * param bitWidth How many bits in a audio word, usually 8/16/24/32 bits. + * param rxData Pointer to the data to be read. + * param size Bytes to be read. + */ void FLEXIO_I2S_ReadBlocking(FLEXIO_I2S_Type *base, uint8_t bitWidth, uint8_t *rxData, size_t size) { uint32_t i = 0; @@ -354,6 +451,18 @@ void FLEXIO_I2S_ReadBlocking(FLEXIO_I2S_Type *base, uint8_t bitWidth, uint8_t *r } } +/*! + * brief Initializes the FlexIO I2S handle. + * + * This function initializes the FlexIO I2S handle which can be used for other + * FlexIO I2S transactional APIs. Call this API once to get the + * initialized handle. + * + * param base Pointer to FLEXIO_I2S_Type structure + * param handle Pointer to flexio_i2s_handle_t structure to store the transfer state. + * param callback FlexIO I2S callback function, which is called while finished a block. + * param userData User parameter for the FlexIO I2S callback. + */ void FLEXIO_I2S_TransferTxCreateHandle(FLEXIO_I2S_Type *base, flexio_i2s_handle_t *handle, flexio_i2s_callback_t callback, @@ -380,6 +489,18 @@ void FLEXIO_I2S_TransferTxCreateHandle(FLEXIO_I2S_Type *base, EnableIRQ(flexio_irqs[FLEXIO_I2S_GetInstance(base)]); } +/*! + * brief Initializes the FlexIO I2S receive handle. + * + * This function initializes the FlexIO I2S handle which can be used for other + * FlexIO I2S transactional APIs. Call this API once to get the + * initialized handle. + * + * param base Pointer to FLEXIO_I2S_Type structure. + * param handle Pointer to flexio_i2s_handle_t structure to store the transfer state. + * param callback FlexIO I2S callback function, which is called while finished a block. + * param userData User parameter for the FlexIO I2S callback. + */ void FLEXIO_I2S_TransferRxCreateHandle(FLEXIO_I2S_Type *base, flexio_i2s_handle_t *handle, flexio_i2s_callback_t callback, @@ -406,6 +527,17 @@ void FLEXIO_I2S_TransferRxCreateHandle(FLEXIO_I2S_Type *base, EnableIRQ(flexio_irqs[FLEXIO_I2S_GetInstance(base)]); } +/*! + * brief Configures the FlexIO I2S audio format. + * + * Audio format can be changed at run-time of FlexIO I2S. This function configures the sample rate and audio data + * format to be transferred. + * + * param base Pointer to FLEXIO_I2S_Type structure. + * param handle FlexIO I2S handle pointer. + * param format Pointer to audio data format structure. + * param srcClock_Hz FlexIO I2S bit clock source frequency in Hz. This parameter should be 0 while in slave mode. +*/ void FLEXIO_I2S_TransferSetFormat(FLEXIO_I2S_Type *base, flexio_i2s_handle_t *handle, flexio_i2s_format_t *format, @@ -428,6 +560,20 @@ void FLEXIO_I2S_TransferSetFormat(FLEXIO_I2S_Type *base, } } +/*! + * brief Performs an interrupt non-blocking send transfer on FlexIO I2S. + * + * note The API returns immediately after transfer initiates. + * Call FLEXIO_I2S_GetRemainingBytes to poll the transfer status and check whether + * the transfer is finished. If the return status is 0, the transfer is finished. + * + * param base Pointer to FLEXIO_I2S_Type structure. + * param handle Pointer to flexio_i2s_handle_t structure which stores the transfer state + * param xfer Pointer to flexio_i2s_transfer_t structure + * retval kStatus_Success Successfully start the data transmission. + * retval kStatus_FLEXIO_I2S_TxBusy Previous transmission still not finished, data not all written to TX register yet. + * retval kStatus_InvalidArgument The input parameter is invalid. + */ status_t FLEXIO_I2S_TransferSendNonBlocking(FLEXIO_I2S_Type *base, flexio_i2s_handle_t *handle, flexio_i2s_transfer_t *xfer) @@ -461,6 +607,20 @@ status_t FLEXIO_I2S_TransferSendNonBlocking(FLEXIO_I2S_Type *base, return kStatus_Success; } +/*! + * brief Performs an interrupt non-blocking receive transfer on FlexIO I2S. + * + * note The API returns immediately after transfer initiates. + * Call FLEXIO_I2S_GetRemainingBytes to poll the transfer status to check whether + * the transfer is finished. If the return status is 0, the transfer is finished. + * + * param base Pointer to FLEXIO_I2S_Type structure. + * param handle Pointer to flexio_i2s_handle_t structure which stores the transfer state + * param xfer Pointer to flexio_i2s_transfer_t structure + * retval kStatus_Success Successfully start the data receive. + * retval kStatus_FLEXIO_I2S_RxBusy Previous receive still not finished. + * retval kStatus_InvalidArgument The input parameter is invalid. + */ status_t FLEXIO_I2S_TransferReceiveNonBlocking(FLEXIO_I2S_Type *base, flexio_i2s_handle_t *handle, flexio_i2s_transfer_t *xfer) @@ -496,6 +656,15 @@ status_t FLEXIO_I2S_TransferReceiveNonBlocking(FLEXIO_I2S_Type *base, return kStatus_Success; } +/*! + * brief Aborts the current send. + * + * note This API can be called at any time when interrupt non-blocking transfer initiates + * to abort the transfer in a early time. + * + * param base Pointer to FLEXIO_I2S_Type structure. + * param handle Pointer to flexio_i2s_handle_t structure which stores the transfer state + */ void FLEXIO_I2S_TransferAbortSend(FLEXIO_I2S_Type *base, flexio_i2s_handle_t *handle) { assert(handle); @@ -510,6 +679,15 @@ void FLEXIO_I2S_TransferAbortSend(FLEXIO_I2S_Type *base, flexio_i2s_handle_t *ha handle->queueUser = 0; } +/*! + * brief Aborts the current receive. + * + * note This API can be called at any time when interrupt non-blocking transfer initiates + * to abort the transfer in a early time. + * + * param base Pointer to FLEXIO_I2S_Type structure. + * param handle Pointer to flexio_i2s_handle_t structure which stores the transfer state + */ void FLEXIO_I2S_TransferAbortReceive(FLEXIO_I2S_Type *base, flexio_i2s_handle_t *handle) { assert(handle); @@ -524,6 +702,15 @@ void FLEXIO_I2S_TransferAbortReceive(FLEXIO_I2S_Type *base, flexio_i2s_handle_t handle->queueUser = 0; } +/*! + * brief Gets the remaining bytes to be sent. + * + * param base Pointer to FLEXIO_I2S_Type structure. + * param handle Pointer to flexio_i2s_handle_t structure which stores the transfer state + * param count Bytes sent. + * retval kStatus_Success Succeed get the transfer count. + * retval kStatus_NoTransferInProgress There is not a non-blocking transaction currently in progress. + */ status_t FLEXIO_I2S_TransferGetSendCount(FLEXIO_I2S_Type *base, flexio_i2s_handle_t *handle, size_t *count) { assert(handle); @@ -542,6 +729,15 @@ status_t FLEXIO_I2S_TransferGetSendCount(FLEXIO_I2S_Type *base, flexio_i2s_handl return status; } +/*! + * brief Gets the remaining bytes to be received. + * + * param base Pointer to FLEXIO_I2S_Type structure. + * param handle Pointer to flexio_i2s_handle_t structure which stores the transfer state + * return count Bytes received. + * retval kStatus_Success Succeed get the transfer count. + * retval kStatus_NoTransferInProgress There is not a non-blocking transaction currently in progress. + */ status_t FLEXIO_I2S_TransferGetReceiveCount(FLEXIO_I2S_Type *base, flexio_i2s_handle_t *handle, size_t *count) { assert(handle); @@ -560,6 +756,12 @@ status_t FLEXIO_I2S_TransferGetReceiveCount(FLEXIO_I2S_Type *base, flexio_i2s_ha return status; } +/*! + * brief Tx interrupt handler. + * + * param i2sBase Pointer to FLEXIO_I2S_Type structure. + * param i2sHandle Pointer to flexio_i2s_handle_t structure + */ void FLEXIO_I2S_TransferTxHandleIRQ(void *i2sBase, void *i2sHandle) { assert(i2sHandle); @@ -603,6 +805,12 @@ void FLEXIO_I2S_TransferTxHandleIRQ(void *i2sBase, void *i2sHandle) } } +/*! + * brief Rx interrupt handler. + * + * param i2sBase Pointer to FLEXIO_I2S_Type structure. + * param i2sHandle Pointer to flexio_i2s_handle_t structure. + */ void FLEXIO_I2S_TransferRxHandleIRQ(void *i2sBase, void *i2sHandle) { assert(i2sHandle); diff --git a/ext/hal/nxp/mcux/drivers/imx/fsl_flexio_i2s.h b/ext/hal/nxp/mcux/drivers/imx/fsl_flexio_i2s.h index c4a8069ddd8..6d9a713cb5f 100644 --- a/ext/hal/nxp/mcux/drivers/imx/fsl_flexio_i2s.h +++ b/ext/hal/nxp/mcux/drivers/imx/fsl_flexio_i2s.h @@ -1,8 +1,8 @@ /* * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP + * Copyright 2016-2018 NXP * All rights reserved. - * + * * SPDX-License-Identifier: BSD-3-Clause */ #ifndef _FSL_FLEXIO_I2S_H_ @@ -22,8 +22,8 @@ /*! @name Driver version */ /*@{*/ -/*! @brief FlexIO I2S driver version 2.1.4. */ -#define FSL_FLEXIO_I2S_DRIVER_VERSION (MAKE_VERSION(2, 1, 4)) +/*! @brief FlexIO I2S driver version 2.1.6. */ +#define FSL_FLEXIO_I2S_DRIVER_VERSION (MAKE_VERSION(2, 1, 6)) /*@}*/ /*! @brief FlexIO I2S transfer status */ diff --git a/ext/hal/nxp/mcux/drivers/imx/fsl_flexio_i2s_edma.c b/ext/hal/nxp/mcux/drivers/imx/fsl_flexio_i2s_edma.c index 2eddcb9b24f..253f278f9e1 100644 --- a/ext/hal/nxp/mcux/drivers/imx/fsl_flexio_i2s_edma.c +++ b/ext/hal/nxp/mcux/drivers/imx/fsl_flexio_i2s_edma.c @@ -1,8 +1,8 @@ /* * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP + * Copyright 2016-2018 NXP * All rights reserved. - * + * * SPDX-License-Identifier: BSD-3-Clause */ @@ -13,7 +13,6 @@ #define FSL_COMPONENT_ID "platform.drivers.flexio_i2s_edma" #endif - /******************************************************************************* * Definitations ******************************************************************************/ @@ -102,6 +101,19 @@ static void FLEXIO_I2S_RxEDMACallback(edma_handle_t *handle, void *userData, boo } } +/*! + * brief Initializes the FlexIO I2S eDMA handle. + * + * This function initializes the FlexIO I2S master DMA handle which can be used for other FlexIO I2S master + * transactional APIs. + * Usually, for a specified FlexIO I2S instance, call this API once to get the initialized handle. + * + * param base FlexIO I2S peripheral base address. + * param handle FlexIO I2S eDMA handle pointer. + * param callback FlexIO I2S eDMA callback function called while finished a block. + * param userData User parameter for callback. + * param dmaHandle eDMA handle for FlexIO I2S. This handle is a static value allocated by users. + */ void FLEXIO_I2S_TransferTxCreateHandleEDMA(FLEXIO_I2S_Type *base, flexio_i2s_edma_handle_t *handle, flexio_i2s_edma_callback_t callback, @@ -131,6 +143,19 @@ void FLEXIO_I2S_TransferTxCreateHandleEDMA(FLEXIO_I2S_Type *base, EDMA_SetCallback(dmaHandle, FLEXIO_I2S_TxEDMACallback, &s_edmaPrivateHandle[0]); } +/*! + * brief Initializes the FlexIO I2S Rx eDMA handle. + * + * This function initializes the FlexIO I2S slave DMA handle which can be used for other FlexIO I2S master transactional + * APIs. + * Usually, for a specified FlexIO I2S instance, call this API once to get the initialized handle. + * + * param base FlexIO I2S peripheral base address. + * param handle FlexIO I2S eDMA handle pointer. + * param callback FlexIO I2S eDMA callback function called while finished a block. + * param userData User parameter for callback. + * param dmaHandle eDMA handle for FlexIO I2S. This handle is a static value allocated by users. + */ void FLEXIO_I2S_TransferRxCreateHandleEDMA(FLEXIO_I2S_Type *base, flexio_i2s_edma_handle_t *handle, flexio_i2s_edma_callback_t callback, @@ -160,6 +185,19 @@ void FLEXIO_I2S_TransferRxCreateHandleEDMA(FLEXIO_I2S_Type *base, EDMA_SetCallback(dmaHandle, FLEXIO_I2S_RxEDMACallback, &s_edmaPrivateHandle[1]); } +/*! + * brief Configures the FlexIO I2S Tx audio format. + * + * Audio format can be changed in run-time of FlexIO I2S. This function configures the sample rate and audio data + * format to be transferred. This function also sets the eDMA parameter according to format. + * + * param base FlexIO I2S peripheral base address. + * param handle FlexIO I2S eDMA handle pointer + * param format Pointer to FlexIO I2S audio data format structure. + * param srcClock_Hz FlexIO I2S clock source frequency in Hz, it should be 0 while in slave mode. + * retval kStatus_Success Audio format set successfully. + * retval kStatus_InvalidArgument The input arguments is invalid. +*/ void FLEXIO_I2S_TransferSetFormatEDMA(FLEXIO_I2S_Type *base, flexio_i2s_edma_handle_t *handle, flexio_i2s_format_t *format, @@ -182,6 +220,19 @@ void FLEXIO_I2S_TransferSetFormatEDMA(FLEXIO_I2S_Type *base, handle->bytesPerFrame = format->bitWidth / 8U; } +/*! + * brief Performs a non-blocking FlexIO I2S transfer using DMA. + * + * note This interface returned immediately after transfer initiates. Users should call + * FLEXIO_I2S_GetTransferStatus to poll the transfer status and check whether the FlexIO I2S transfer is finished. + * + * param base FlexIO I2S peripheral base address. + * param handle FlexIO I2S DMA handle pointer. + * param xfer Pointer to DMA transfer structure. + * retval kStatus_Success Start a FlexIO I2S eDMA send successfully. + * retval kStatus_InvalidArgument The input arguments is invalid. + * retval kStatus_TxBusy FlexIO I2S is busy sending data. + */ status_t FLEXIO_I2S_TransferSendEDMA(FLEXIO_I2S_Type *base, flexio_i2s_edma_handle_t *handle, flexio_i2s_transfer_t *xfer) @@ -232,6 +283,20 @@ status_t FLEXIO_I2S_TransferSendEDMA(FLEXIO_I2S_Type *base, return kStatus_Success; } +/*! + * brief Performs a non-blocking FlexIO I2S receive using eDMA. + * + * note This interface returned immediately after transfer initiates. Users should call + * FLEXIO_I2S_GetReceiveRemainingBytes to poll the transfer status and check whether the FlexIO I2S transfer is + * finished. + * + * param base FlexIO I2S peripheral base address. + * param handle FlexIO I2S DMA handle pointer. + * param xfer Pointer to DMA transfer structure. + * retval kStatus_Success Start a FlexIO I2S eDMA receive successfully. + * retval kStatus_InvalidArgument The input arguments is invalid. + * retval kStatus_RxBusy FlexIO I2S is busy receiving data. + */ status_t FLEXIO_I2S_TransferReceiveEDMA(FLEXIO_I2S_Type *base, flexio_i2s_edma_handle_t *handle, flexio_i2s_transfer_t *xfer) @@ -239,7 +304,7 @@ status_t FLEXIO_I2S_TransferReceiveEDMA(FLEXIO_I2S_Type *base, assert(handle && xfer); edma_transfer_config_t config = {0}; - uint32_t srcAddr = FLEXIO_I2S_RxGetDataRegisterAddress(base) + (4U - handle->bytesPerFrame); + uint32_t srcAddr = FLEXIO_I2S_RxGetDataRegisterAddress(base); /* Check if input parameter invalid */ if ((xfer->data == NULL) || (xfer->dataSize == 0U)) @@ -282,6 +347,12 @@ status_t FLEXIO_I2S_TransferReceiveEDMA(FLEXIO_I2S_Type *base, return kStatus_Success; } +/*! + * brief Aborts a FlexIO I2S transfer using eDMA. + * + * param base FlexIO I2S peripheral base address. + * param handle FlexIO I2S DMA handle pointer. + */ void FLEXIO_I2S_TransferAbortSendEDMA(FLEXIO_I2S_Type *base, flexio_i2s_edma_handle_t *handle) { assert(handle); @@ -296,6 +367,12 @@ void FLEXIO_I2S_TransferAbortSendEDMA(FLEXIO_I2S_Type *base, flexio_i2s_edma_han handle->state = kFLEXIO_I2S_Idle; } +/*! + * brief Aborts a FlexIO I2S receive using eDMA. + * + * param base FlexIO I2S peripheral base address. + * param handle FlexIO I2S DMA handle pointer. + */ void FLEXIO_I2S_TransferAbortReceiveEDMA(FLEXIO_I2S_Type *base, flexio_i2s_edma_handle_t *handle) { assert(handle); @@ -310,6 +387,15 @@ void FLEXIO_I2S_TransferAbortReceiveEDMA(FLEXIO_I2S_Type *base, flexio_i2s_edma_ handle->state = kFLEXIO_I2S_Idle; } +/*! + * brief Gets the remaining bytes to be sent. + * + * param base FlexIO I2S peripheral base address. + * param handle FlexIO I2S DMA handle pointer. + * param count Bytes sent. + * retval kStatus_Success Succeed get the transfer count. + * retval kStatus_NoTransferInProgress There is not a non-blocking transaction currently in progress. + */ status_t FLEXIO_I2S_TransferGetSendCountEDMA(FLEXIO_I2S_Type *base, flexio_i2s_edma_handle_t *handle, size_t *count) { assert(handle); @@ -330,6 +416,15 @@ status_t FLEXIO_I2S_TransferGetSendCountEDMA(FLEXIO_I2S_Type *base, flexio_i2s_e return status; } +/*! + * brief Get the remaining bytes to be received. + * + * param base FlexIO I2S peripheral base address. + * param handle FlexIO I2S DMA handle pointer. + * param count Bytes received. + * retval kStatus_Success Succeed get the transfer count. + * retval kStatus_NoTransferInProgress There is not a non-blocking transaction currently in progress. + */ status_t FLEXIO_I2S_TransferGetReceiveCountEDMA(FLEXIO_I2S_Type *base, flexio_i2s_edma_handle_t *handle, size_t *count) { assert(handle); diff --git a/ext/hal/nxp/mcux/drivers/imx/fsl_flexio_i2s_edma.h b/ext/hal/nxp/mcux/drivers/imx/fsl_flexio_i2s_edma.h index 5f7eae2f634..47221dac85b 100644 --- a/ext/hal/nxp/mcux/drivers/imx/fsl_flexio_i2s_edma.h +++ b/ext/hal/nxp/mcux/drivers/imx/fsl_flexio_i2s_edma.h @@ -1,8 +1,8 @@ /* * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP + * Copyright 2016-2018 NXP * All rights reserved. - * + * * SPDX-License-Identifier: BSD-3-Clause */ #ifndef _FSL_FLEXIO_I2S_EDMA_H_ @@ -22,8 +22,8 @@ /*! @name Driver version */ /*@{*/ -/*! @brief FlexIO I2S EDMA driver version 2.1.4. */ -#define FSL_FLEXIO_I2S_EDMA_DRIVER_VERSION (MAKE_VERSION(2, 1, 4)) +/*! @brief FlexIO I2S EDMA driver version 2.1.5. */ +#define FSL_FLEXIO_I2S_EDMA_DRIVER_VERSION (MAKE_VERSION(2, 1, 5)) /*@}*/ typedef struct _flexio_i2s_edma_handle flexio_i2s_edma_handle_t; diff --git a/ext/hal/nxp/mcux/drivers/imx/fsl_flexio_spi.c b/ext/hal/nxp/mcux/drivers/imx/fsl_flexio_spi.c index c2ef8a7c65e..af8d08e42e3 100644 --- a/ext/hal/nxp/mcux/drivers/imx/fsl_flexio_spi.c +++ b/ext/hal/nxp/mcux/drivers/imx/fsl_flexio_spi.c @@ -2,7 +2,7 @@ * Copyright (c) 2015, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP * All rights reserved. - * + * * SPDX-License-Identifier: BSD-3-Clause */ @@ -17,7 +17,6 @@ #define FSL_COMPONENT_ID "platform.drivers.flexio_spi" #endif - /*! @brief FLEXIO SPI transfer state, which is used for SPI transactiaonl APIs' internal state. */ enum _flexio_spi_transfer_states { @@ -137,6 +136,42 @@ static void FLEXIO_SPI_TransferReceiveTransaction(FLEXIO_SPI_Type *base, flexio_ handle->rxRemainingBytes -= handle->bytePerFrame; } +/*! + * brief Ungates the FlexIO clock, resets the FlexIO module, configures the FlexIO SPI master hardware, + * and configures the FlexIO SPI with FlexIO SPI master configuration. The + * configuration structure can be filled by the user, or be set with default values + * by the FLEXIO_SPI_MasterGetDefaultConfig(). + * + * note FlexIO SPI master only support CPOL = 0, which means clock inactive low. + * + * Example + code + FLEXIO_SPI_Type spiDev = { + .flexioBase = FLEXIO, + .SDOPinIndex = 0, + .SDIPinIndex = 1, + .SCKPinIndex = 2, + .CSnPinIndex = 3, + .shifterIndex = {0,1}, + .timerIndex = {0,1} + }; + flexio_spi_master_config_t config = { + .enableMaster = true, + .enableInDoze = false, + .enableInDebug = true, + .enableFastAccess = false, + .baudRate_Bps = 500000, + .phase = kFLEXIO_SPI_ClockPhaseFirstEdge, + .direction = kFLEXIO_SPI_MsbFirst, + .dataMode = kFLEXIO_SPI_8BitMode + }; + FLEXIO_SPI_MasterInit(&spiDev, &config, srcClock_Hz); + endcode + * + * param base Pointer to the FLEXIO_SPI_Type structure. + * param masterConfig Pointer to the flexio_spi_master_config_t structure. + * param srcClock_Hz FlexIO source clock in Hz. +*/ void FLEXIO_SPI_MasterInit(FLEXIO_SPI_Type *base, flexio_spi_master_config_t *masterConfig, uint32_t srcClock_Hz) { assert(base); @@ -259,6 +294,11 @@ void FLEXIO_SPI_MasterInit(FLEXIO_SPI_Type *base, flexio_spi_master_config_t *ma FLEXIO_SetTimerConfig(base->flexioBase, base->timerIndex[1], &timerConfig); } +/*! + * brief Resets the FlexIO SPI timer and shifter config. + * + * param base Pointer to the FLEXIO_SPI_Type. +*/ void FLEXIO_SPI_MasterDeinit(FLEXIO_SPI_Type *base) { base->flexioBase->SHIFTCFG[base->shifterIndex[0]] = 0; @@ -273,10 +313,23 @@ void FLEXIO_SPI_MasterDeinit(FLEXIO_SPI_Type *base) base->flexioBase->TIMCTL[base->timerIndex[1]] = 0; } +/*! + * brief Gets the default configuration to configure the FlexIO SPI master. The configuration + * can be used directly by calling the FLEXIO_SPI_MasterConfigure(). + * Example: + code + flexio_spi_master_config_t masterConfig; + FLEXIO_SPI_MasterGetDefaultConfig(&masterConfig); + endcode + * param masterConfig Pointer to the flexio_spi_master_config_t structure. +*/ void FLEXIO_SPI_MasterGetDefaultConfig(flexio_spi_master_config_t *masterConfig) { assert(masterConfig); + /* Initializes the configure structure to zero. */ + memset(masterConfig, 0, sizeof(*masterConfig)); + masterConfig->enableMaster = true; masterConfig->enableInDoze = false; masterConfig->enableInDebug = true; @@ -289,6 +342,39 @@ void FLEXIO_SPI_MasterGetDefaultConfig(flexio_spi_master_config_t *masterConfig) masterConfig->dataMode = kFLEXIO_SPI_8BitMode; } +/*! + * brief Ungates the FlexIO clock, resets the FlexIO module, configures the FlexIO SPI slave hardware + * configuration, and configures the FlexIO SPI with FlexIO SPI slave configuration. The + * configuration structure can be filled by the user, or be set with default values + * by the FLEXIO_SPI_SlaveGetDefaultConfig(). + * + * note Only one timer is needed in the FlexIO SPI slave. As a result, the second timer index is ignored. + * FlexIO SPI slave only support CPOL = 0, which means clock inactive low. + * Example + code + FLEXIO_SPI_Type spiDev = { + .flexioBase = FLEXIO, + .SDOPinIndex = 0, + .SDIPinIndex = 1, + .SCKPinIndex = 2, + .CSnPinIndex = 3, + .shifterIndex = {0,1}, + .timerIndex = {0} + }; + flexio_spi_slave_config_t config = { + .enableSlave = true, + .enableInDoze = false, + .enableInDebug = true, + .enableFastAccess = false, + .phase = kFLEXIO_SPI_ClockPhaseFirstEdge, + .direction = kFLEXIO_SPI_MsbFirst, + .dataMode = kFLEXIO_SPI_8BitMode + }; + FLEXIO_SPI_SlaveInit(&spiDev, &config); + endcode + * param base Pointer to the FLEXIO_SPI_Type structure. + * param slaveConfig Pointer to the flexio_spi_slave_config_t structure. +*/ void FLEXIO_SPI_SlaveInit(FLEXIO_SPI_Type *base, flexio_spi_slave_config_t *slaveConfig) { assert(base && slaveConfig); @@ -391,15 +477,33 @@ void FLEXIO_SPI_SlaveInit(FLEXIO_SPI_Type *base, flexio_spi_slave_config_t *slav FLEXIO_SetTimerConfig(base->flexioBase, base->timerIndex[0], &timerConfig); } +/*! + * brief Gates the FlexIO clock. + * + * param base Pointer to the FLEXIO_SPI_Type. +*/ void FLEXIO_SPI_SlaveDeinit(FLEXIO_SPI_Type *base) { FLEXIO_SPI_MasterDeinit(base); } +/*! + * brief Gets the default configuration to configure the FlexIO SPI slave. The configuration + * can be used directly for calling the FLEXIO_SPI_SlaveConfigure(). + * Example: + code + flexio_spi_slave_config_t slaveConfig; + FLEXIO_SPI_SlaveGetDefaultConfig(&slaveConfig); + endcode + * param slaveConfig Pointer to the flexio_spi_slave_config_t structure. +*/ void FLEXIO_SPI_SlaveGetDefaultConfig(flexio_spi_slave_config_t *slaveConfig) { assert(slaveConfig); + /* Initializes the configure structure to zero. */ + memset(slaveConfig, 0, sizeof(*slaveConfig)); + slaveConfig->enableSlave = true; slaveConfig->enableInDoze = false; slaveConfig->enableInDebug = true; @@ -410,6 +514,16 @@ void FLEXIO_SPI_SlaveGetDefaultConfig(flexio_spi_slave_config_t *slaveConfig) slaveConfig->dataMode = kFLEXIO_SPI_8BitMode; } +/*! + * brief Enables the FlexIO SPI interrupt. + * + * This function enables the FlexIO SPI interrupt. + * + * param base Pointer to the FLEXIO_SPI_Type structure. + * param mask interrupt source. The parameter can be any combination of the following values: + * arg kFLEXIO_SPI_RxFullInterruptEnable + * arg kFLEXIO_SPI_TxEmptyInterruptEnable + */ void FLEXIO_SPI_EnableInterrupts(FLEXIO_SPI_Type *base, uint32_t mask) { if (mask & kFLEXIO_SPI_TxEmptyInterruptEnable) @@ -422,6 +536,16 @@ void FLEXIO_SPI_EnableInterrupts(FLEXIO_SPI_Type *base, uint32_t mask) } } +/*! + * brief Disables the FlexIO SPI interrupt. + * + * This function disables the FlexIO SPI interrupt. + * + * param base Pointer to the FLEXIO_SPI_Type structure. + * param mask interrupt source The parameter can be any combination of the following values: + * arg kFLEXIO_SPI_RxFullInterruptEnable + * arg kFLEXIO_SPI_TxEmptyInterruptEnable + */ void FLEXIO_SPI_DisableInterrupts(FLEXIO_SPI_Type *base, uint32_t mask) { if (mask & kFLEXIO_SPI_TxEmptyInterruptEnable) @@ -434,6 +558,14 @@ void FLEXIO_SPI_DisableInterrupts(FLEXIO_SPI_Type *base, uint32_t mask) } } +/*! + * brief Enables/disables the FlexIO SPI transmit DMA. This function enables/disables the FlexIO SPI Tx DMA, + * which means that asserting the kFLEXIO_SPI_TxEmptyFlag does/doesn't trigger the DMA request. + * + * param base Pointer to the FLEXIO_SPI_Type structure. + * param mask SPI DMA source. + * param enable True means enable DMA, false means disable DMA. + */ void FLEXIO_SPI_EnableDMA(FLEXIO_SPI_Type *base, uint32_t mask, bool enable) { if (mask & kFLEXIO_SPI_TxDmaEnable) @@ -447,6 +579,15 @@ void FLEXIO_SPI_EnableDMA(FLEXIO_SPI_Type *base, uint32_t mask, bool enable) } } +/*! + * brief Gets FlexIO SPI status flags. + * + * param base Pointer to the FLEXIO_SPI_Type structure. + * return status flag; Use the status flag to AND the following flag mask and get the status. + * arg kFLEXIO_SPI_TxEmptyFlag + * arg kFLEXIO_SPI_RxEmptyFlag +*/ + uint32_t FLEXIO_SPI_GetStatusFlags(FLEXIO_SPI_Type *base) { uint32_t shifterStatus = FLEXIO_GetShifterStatusFlags(base->flexioBase); @@ -458,6 +599,16 @@ uint32_t FLEXIO_SPI_GetStatusFlags(FLEXIO_SPI_Type *base) return status; } +/*! + * brief Clears FlexIO SPI status flags. + * + * param base Pointer to the FLEXIO_SPI_Type structure. + * param mask status flag + * The parameter can be any combination of the following values: + * arg kFLEXIO_SPI_TxEmptyFlag + * arg kFLEXIO_SPI_RxEmptyFlag +*/ + void FLEXIO_SPI_ClearStatusFlags(FLEXIO_SPI_Type *base, uint32_t mask) { if (mask & kFLEXIO_SPI_TxBufferEmptyFlag) @@ -470,6 +621,13 @@ void FLEXIO_SPI_ClearStatusFlags(FLEXIO_SPI_Type *base, uint32_t mask) } } +/*! + * brief Sets baud rate for the FlexIO SPI transfer, which is only used for the master. + * + * param base Pointer to the FLEXIO_SPI_Type structure. + * param baudRate_Bps Baud Rate needed in Hz. + * param srcClockHz SPI source clock frequency in Hz. + */ void FLEXIO_SPI_MasterSetBaudRate(FLEXIO_SPI_Type *base, uint32_t baudRate_Bps, uint32_t srcClockHz) { uint16_t timerDiv = 0; @@ -487,6 +645,16 @@ void FLEXIO_SPI_MasterSetBaudRate(FLEXIO_SPI_Type *base, uint32_t baudRate_Bps, flexioBase->TIMCMP[base->timerIndex[0]] = timerCmp; } +/*! + * brief Sends a buffer of data bytes. + * + * note This function blocks using the polling method until all bytes have been sent. + * + * param base Pointer to the FLEXIO_SPI_Type structure. + * param direction Shift direction of MSB first or LSB first. + * param buffer The data bytes to send. + * param size The number of data bytes to send. + */ void FLEXIO_SPI_WriteBlocking(FLEXIO_SPI_Type *base, flexio_spi_shift_direction_t direction, const uint8_t *buffer, @@ -505,6 +673,17 @@ void FLEXIO_SPI_WriteBlocking(FLEXIO_SPI_Type *base, } } +/*! + * brief Receives a buffer of bytes. + * + * note This function blocks using the polling method until all bytes have been received. + * + * param base Pointer to the FLEXIO_SPI_Type structure. + * param direction Shift direction of MSB first or LSB first. + * param buffer The buffer to store the received bytes. + * param size The number of data bytes to be received. + * param direction Shift direction of MSB first or LSB first. + */ void FLEXIO_SPI_ReadBlocking(FLEXIO_SPI_Type *base, flexio_spi_shift_direction_t direction, uint8_t *buffer, @@ -523,6 +702,14 @@ void FLEXIO_SPI_ReadBlocking(FLEXIO_SPI_Type *base, } } +/*! + * brief Receives a buffer of bytes. + * + * note This function blocks via polling until all bytes have been received. + * + * param base pointer to FLEXIO_SPI_Type structure + * param xfer FlexIO SPI transfer structure, see #flexio_spi_transfer_t. + */ void FLEXIO_SPI_MasterTransferBlocking(FLEXIO_SPI_Type *base, flexio_spi_transfer_t *xfer) { flexio_spi_shift_direction_t direction; @@ -638,6 +825,16 @@ void FLEXIO_SPI_MasterTransferBlocking(FLEXIO_SPI_Type *base, flexio_spi_transfe } } +/*! + * brief Initializes the FlexIO SPI Master handle, which is used in transactional functions. + * + * param base Pointer to the FLEXIO_SPI_Type structure. + * param handle Pointer to the flexio_spi_master_handle_t structure to store the transfer state. + * param callback The callback function. + * param userData The parameter of the callback function. + * retval kStatus_Success Successfully create the handle. + * retval kStatus_OutOfRange The FlexIO type/handle/ISR table out of range. + */ status_t FLEXIO_SPI_MasterTransferCreateHandle(FLEXIO_SPI_Type *base, flexio_spi_master_handle_t *handle, flexio_spi_master_transfer_callback_t callback, @@ -661,6 +858,19 @@ status_t FLEXIO_SPI_MasterTransferCreateHandle(FLEXIO_SPI_Type *base, return FLEXIO_RegisterHandleIRQ(base, handle, FLEXIO_SPI_MasterTransferHandleIRQ); } +/*! + * brief Master transfer data using IRQ. + * + * This function sends data using IRQ. This is a non-blocking function, which returns + * right away. When all data is sent out/received, the callback function is called. + * + * param base Pointer to the FLEXIO_SPI_Type structure. + * param handle Pointer to the flexio_spi_master_handle_t structure to store the transfer state. + * param xfer FlexIO SPI transfer structure. See #flexio_spi_transfer_t. + * retval kStatus_Success Successfully start a transfer. + * retval kStatus_InvalidArgument Input argument is invalid. + * retval kStatus_FLEXIO_SPI_Busy SPI is not idle, is running another transfer. + */ status_t FLEXIO_SPI_MasterTransferNonBlocking(FLEXIO_SPI_Type *base, flexio_spi_master_handle_t *handle, flexio_spi_transfer_t *xfer) @@ -769,6 +979,15 @@ status_t FLEXIO_SPI_MasterTransferNonBlocking(FLEXIO_SPI_Type *base, return kStatus_Success; } +/*! + * brief Gets the data transfer status which used IRQ. + * + * param base Pointer to the FLEXIO_SPI_Type structure. + * param handle Pointer to the flexio_spi_master_handle_t structure to store the transfer state. + * param count Number of bytes transferred so far by the non-blocking transaction. + * retval kStatus_InvalidArgument count is Invalid. + * retval kStatus_Success Successfully return the count. + */ status_t FLEXIO_SPI_MasterTransferGetCount(FLEXIO_SPI_Type *base, flexio_spi_master_handle_t *handle, size_t *count) { assert(handle); @@ -791,6 +1010,12 @@ status_t FLEXIO_SPI_MasterTransferGetCount(FLEXIO_SPI_Type *base, flexio_spi_mas return kStatus_Success; } +/*! + * brief Aborts the master data transfer, which used IRQ. + * + * param base Pointer to the FLEXIO_SPI_Type structure. + * param handle Pointer to the flexio_spi_master_handle_t structure to store the transfer state. + */ void FLEXIO_SPI_MasterTransferAbort(FLEXIO_SPI_Type *base, flexio_spi_master_handle_t *handle) { assert(handle); @@ -806,6 +1031,12 @@ void FLEXIO_SPI_MasterTransferAbort(FLEXIO_SPI_Type *base, flexio_spi_master_han handle->txRemainingBytes = 0; } +/*! + * brief FlexIO SPI master IRQ handler function. + * + * param spiType Pointer to the FLEXIO_SPI_Type structure. + * param spiHandle Pointer to the flexio_spi_master_handle_t structure to store the transfer state. + */ void FLEXIO_SPI_MasterTransferHandleIRQ(void *spiType, void *spiHandle) { assert(spiHandle); @@ -845,6 +1076,16 @@ void FLEXIO_SPI_MasterTransferHandleIRQ(void *spiType, void *spiHandle) } } +/*! + * brief Initializes the FlexIO SPI Slave handle, which is used in transactional functions. + * + * param base Pointer to the FLEXIO_SPI_Type structure. + * param handle Pointer to the flexio_spi_slave_handle_t structure to store the transfer state. + * param callback The callback function. + * param userData The parameter of the callback function. + * retval kStatus_Success Successfully create the handle. + * retval kStatus_OutOfRange The FlexIO type/handle/ISR table out of range. + */ status_t FLEXIO_SPI_SlaveTransferCreateHandle(FLEXIO_SPI_Type *base, flexio_spi_slave_handle_t *handle, flexio_spi_slave_transfer_callback_t callback, @@ -868,6 +1109,19 @@ status_t FLEXIO_SPI_SlaveTransferCreateHandle(FLEXIO_SPI_Type *base, return FLEXIO_RegisterHandleIRQ(base, handle, FLEXIO_SPI_SlaveTransferHandleIRQ); } +/*! + * brief Slave transfer data using IRQ. + * + * This function sends data using IRQ. This is a non-blocking function, which returns + * right away. When all data is sent out/received, the callback function is called. + * param handle Pointer to the flexio_spi_slave_handle_t structure to store the transfer state. + * + * param base Pointer to the FLEXIO_SPI_Type structure. + * param xfer FlexIO SPI transfer structure. See #flexio_spi_transfer_t. + * retval kStatus_Success Successfully start a transfer. + * retval kStatus_InvalidArgument Input argument is invalid. + * retval kStatus_FLEXIO_SPI_Busy SPI is not idle; it is running another transfer. + */ status_t FLEXIO_SPI_SlaveTransferNonBlocking(FLEXIO_SPI_Type *base, flexio_spi_slave_handle_t *handle, flexio_spi_transfer_t *xfer) @@ -939,6 +1193,12 @@ status_t FLEXIO_SPI_SlaveTransferNonBlocking(FLEXIO_SPI_Type *base, return kStatus_Success; } +/*! + * brief FlexIO SPI slave IRQ handler function. + * + * param spiType Pointer to the FLEXIO_SPI_Type structure. + * param spiHandle Pointer to the flexio_spi_slave_handle_t structure to store the transfer state. + */ void FLEXIO_SPI_SlaveTransferHandleIRQ(void *spiType, void *spiHandle) { assert(spiHandle); diff --git a/ext/hal/nxp/mcux/drivers/imx/fsl_flexio_spi_edma.c b/ext/hal/nxp/mcux/drivers/imx/fsl_flexio_spi_edma.c index f6f28685a05..916b8c0cfc3 100644 --- a/ext/hal/nxp/mcux/drivers/imx/fsl_flexio_spi_edma.c +++ b/ext/hal/nxp/mcux/drivers/imx/fsl_flexio_spi_edma.c @@ -2,7 +2,7 @@ * Copyright (c) 2015, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP * All rights reserved. - * + * * SPDX-License-Identifier: BSD-3-Clause */ @@ -126,8 +126,8 @@ static void FLEXIO_SPI_EDMAConfig(FLEXIO_SPI_Type *base, flexio_spi_master_edma_handle_t *handle, flexio_spi_transfer_t *xfer) { - edma_transfer_config_t xferConfig; - flexio_spi_shift_direction_t direction; + edma_transfer_config_t xferConfig = {0}; + flexio_spi_shift_direction_t direction = kFLEXIO_SPI_MsbFirst; uint8_t bytesPerFrame; /* Configure the values in handle. */ @@ -231,6 +231,23 @@ static void FLEXIO_SPI_EDMAConfig(FLEXIO_SPI_Type *base, } } +/*! + * brief Initializes the FlexIO SPI master eDMA handle. + * + * This function initializes the FlexIO SPI master eDMA handle which can be used for other FlexIO SPI master + * transactional + * APIs. + * For a specified FlexIO SPI instance, call this API once to get the initialized handle. + * + * param base Pointer to FLEXIO_SPI_Type structure. + * param handle Pointer to flexio_spi_master_edma_handle_t structure to store the transfer state. + * param callback SPI callback, NULL means no callback. + * param userData callback function parameter. + * param txHandle User requested eDMA handle for FlexIO SPI RX eDMA transfer. + * param rxHandle User requested eDMA handle for FlexIO SPI TX eDMA transfer. + * retval kStatus_Success Successfully create the handle. + * retval kStatus_OutOfRange The FlexIO SPI eDMA type/handle table out of range. + */ status_t FLEXIO_SPI_MasterTransferCreateHandleEDMA(FLEXIO_SPI_Type *base, flexio_spi_master_edma_handle_t *handle, flexio_spi_master_edma_transfer_callback_t callback, @@ -283,6 +300,20 @@ status_t FLEXIO_SPI_MasterTransferCreateHandleEDMA(FLEXIO_SPI_Type *base, return kStatus_Success; } +/*! + * brief Performs a non-blocking FlexIO SPI transfer using eDMA. + * + * note This interface returns immediately after transfer initiates. Call + * FLEXIO_SPI_MasterGetTransferCountEDMA to poll the transfer status and check + * whether the FlexIO SPI transfer is finished. + * + * param base Pointer to FLEXIO_SPI_Type structure. + * param handle Pointer to flexio_spi_master_edma_handle_t structure to store the transfer state. + * param xfer Pointer to FlexIO SPI transfer structure. + * retval kStatus_Success Successfully start a transfer. + * retval kStatus_InvalidArgument Input argument is invalid. + * retval kStatus_FLEXIO_SPI_Busy FlexIO SPI is not idle, is running another transfer. + */ status_t FLEXIO_SPI_MasterTransferEDMA(FLEXIO_SPI_Type *base, flexio_spi_master_edma_handle_t *handle, flexio_spi_transfer_t *xfer) @@ -330,6 +361,13 @@ status_t FLEXIO_SPI_MasterTransferEDMA(FLEXIO_SPI_Type *base, return kStatus_Success; } +/*! + * brief Gets the remaining bytes for FlexIO SPI eDMA transfer. + * + * param base Pointer to FLEXIO_SPI_Type structure. + * param handle FlexIO SPI eDMA handle pointer. + * param count Number of bytes transferred so far by the non-blocking transaction. + */ status_t FLEXIO_SPI_MasterTransferGetCountEDMA(FLEXIO_SPI_Type *base, flexio_spi_master_edma_handle_t *handle, size_t *count) @@ -357,6 +395,12 @@ status_t FLEXIO_SPI_MasterTransferGetCountEDMA(FLEXIO_SPI_Type *base, return kStatus_Success; } +/*! + * brief Aborts a FlexIO SPI transfer using eDMA. + * + * param base Pointer to FLEXIO_SPI_Type structure. + * param handle FlexIO SPI eDMA handle pointer. + */ void FLEXIO_SPI_MasterTransferAbortEDMA(FLEXIO_SPI_Type *base, flexio_spi_master_edma_handle_t *handle) { assert(handle); @@ -373,6 +417,20 @@ void FLEXIO_SPI_MasterTransferAbortEDMA(FLEXIO_SPI_Type *base, flexio_spi_master handle->rxInProgress = false; } +/*! + * brief Performs a non-blocking FlexIO SPI transfer using eDMA. + * + * note This interface returns immediately after transfer initiates. Call + * FLEXIO_SPI_SlaveGetTransferCountEDMA to poll the transfer status and + * check whether the FlexIO SPI transfer is finished. + * + * param base Pointer to FLEXIO_SPI_Type structure. + * param handle Pointer to flexio_spi_slave_edma_handle_t structure to store the transfer state. + * param xfer Pointer to FlexIO SPI transfer structure. + * retval kStatus_Success Successfully start a transfer. + * retval kStatus_InvalidArgument Input argument is invalid. + * retval kStatus_FLEXIO_SPI_Busy FlexIO SPI is not idle, is running another transfer. + */ status_t FLEXIO_SPI_SlaveTransferEDMA(FLEXIO_SPI_Type *base, flexio_spi_slave_edma_handle_t *handle, flexio_spi_transfer_t *xfer) diff --git a/ext/hal/nxp/mcux/drivers/imx/fsl_flexio_uart.c b/ext/hal/nxp/mcux/drivers/imx/fsl_flexio_uart.c index 35e318570d1..101087fa06c 100644 --- a/ext/hal/nxp/mcux/drivers/imx/fsl_flexio_uart.c +++ b/ext/hal/nxp/mcux/drivers/imx/fsl_flexio_uart.c @@ -1,8 +1,8 @@ /* * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP + * Copyright 2016-2018 NXP * All rights reserved. - * + * * SPDX-License-Identifier: BSD-3-Clause */ @@ -17,7 +17,6 @@ #define FSL_COMPONENT_ID "platform.drivers.flexio_uart" #endif - /*flexioBase->SHIFTCFG[base->shifterIndex[0]] = 0; @@ -222,10 +259,23 @@ void FLEXIO_UART_Deinit(FLEXIO_UART_Type *base) base->flexioBase->TIMSTAT = (1U << base->timerIndex[1]); } +/*! + * brief Gets the default configuration to configure the FlexIO UART. The configuration + * can be used directly for calling the FLEXIO_UART_Init(). + * Example: + code + flexio_uart_config_t config; + FLEXIO_UART_GetDefaultConfig(&userConfig); + endcode + * param userConfig Pointer to the flexio_uart_config_t structure. +*/ void FLEXIO_UART_GetDefaultConfig(flexio_uart_config_t *userConfig) { assert(userConfig); + /* Initializes the configure structure to zero. */ + memset(userConfig, 0, sizeof(*userConfig)); + userConfig->enableUart = true; userConfig->enableInDoze = false; userConfig->enableInDebug = true; @@ -236,6 +286,14 @@ void FLEXIO_UART_GetDefaultConfig(flexio_uart_config_t *userConfig) userConfig->bitCountPerChar = kFLEXIO_UART_8BitsPerChar; } +/*! + * brief Enables the FlexIO UART interrupt. + * + * This function enables the FlexIO UART interrupt. + * + * param base Pointer to the FLEXIO_UART_Type structure. + * param mask Interrupt source. + */ void FLEXIO_UART_EnableInterrupts(FLEXIO_UART_Type *base, uint32_t mask) { if (mask & kFLEXIO_UART_TxDataRegEmptyInterruptEnable) @@ -248,6 +306,14 @@ void FLEXIO_UART_EnableInterrupts(FLEXIO_UART_Type *base, uint32_t mask) } } +/*! + * brief Disables the FlexIO UART interrupt. + * + * This function disables the FlexIO UART interrupt. + * + * param base Pointer to the FLEXIO_UART_Type structure. + * param mask Interrupt source. + */ void FLEXIO_UART_DisableInterrupts(FLEXIO_UART_Type *base, uint32_t mask) { if (mask & kFLEXIO_UART_TxDataRegEmptyInterruptEnable) @@ -260,6 +326,13 @@ void FLEXIO_UART_DisableInterrupts(FLEXIO_UART_Type *base, uint32_t mask) } } +/*! + * brief Gets the FlexIO UART status flags. + * + * param base Pointer to the FLEXIO_UART_Type structure. + * return FlexIO UART status flags. +*/ + uint32_t FLEXIO_UART_GetStatusFlags(FLEXIO_UART_Type *base) { uint32_t status = 0; @@ -274,6 +347,17 @@ uint32_t FLEXIO_UART_GetStatusFlags(FLEXIO_UART_Type *base) return status; } +/*! + * brief Gets the FlexIO UART status flags. + * + * param base Pointer to the FLEXIO_UART_Type structure. + * param mask Status flag. + * The parameter can be any combination of the following values: + * arg kFLEXIO_UART_TxDataRegEmptyFlag + * arg kFLEXIO_UART_RxEmptyFlag + * arg kFLEXIO_UART_RxOverRunFlag +*/ + void FLEXIO_UART_ClearStatusFlags(FLEXIO_UART_Type *base, uint32_t mask) { if (mask & kFLEXIO_UART_TxDataRegEmptyFlag) @@ -290,6 +374,15 @@ void FLEXIO_UART_ClearStatusFlags(FLEXIO_UART_Type *base, uint32_t mask) } } +/*! + * brief Sends a buffer of data bytes. + * + * note This function blocks using the polling method until all bytes have been sent. + * + * param base Pointer to the FLEXIO_UART_Type structure. + * param txData The data bytes to send. + * param txSize The number of data bytes to send. + */ void FLEXIO_UART_WriteBlocking(FLEXIO_UART_Type *base, const uint8_t *txData, size_t txSize) { assert(txData); @@ -306,6 +399,15 @@ void FLEXIO_UART_WriteBlocking(FLEXIO_UART_Type *base, const uint8_t *txData, si } } +/*! + * brief Receives a buffer of bytes. + * + * note This function blocks using the polling method until all bytes have been received. + * + * param base Pointer to the FLEXIO_UART_Type structure. + * param rxData The buffer to store the received bytes. + * param rxSize The number of data bytes to be received. + */ void FLEXIO_UART_ReadBlocking(FLEXIO_UART_Type *base, uint8_t *rxData, size_t rxSize) { assert(rxData); @@ -322,6 +424,26 @@ void FLEXIO_UART_ReadBlocking(FLEXIO_UART_Type *base, uint8_t *rxData, size_t rx } } +/*! + * brief Initializes the UART handle. + * + * This function initializes the FlexIO UART handle, which can be used for other FlexIO + * UART transactional APIs. Call this API once to get the + * initialized handle. + * + * The UART driver supports the "background" receiving, which means that users can set up + * a RX ring buffer optionally. Data received is stored into the ring buffer even when + * the user doesn't call the FLEXIO_UART_TransferReceiveNonBlocking() API. If there is already data + * received in the ring buffer, users can get the received data from the ring buffer + * directly. The ring buffer is disabled if passing NULL as p ringBuffer. + * + * param base to FLEXIO_UART_Type structure. + * param handle Pointer to the flexio_uart_handle_t structure to store the transfer state. + * param callback The callback function. + * param userData The parameter of the callback function. + * retval kStatus_Success Successfully create the handle. + * retval kStatus_OutOfRange The FlexIO type/handle/ISR table out of range. + */ status_t FLEXIO_UART_TransferCreateHandle(FLEXIO_UART_Type *base, flexio_uart_handle_t *handle, flexio_uart_transfer_callback_t callback, @@ -349,6 +471,23 @@ status_t FLEXIO_UART_TransferCreateHandle(FLEXIO_UART_Type *base, return FLEXIO_RegisterHandleIRQ(base, handle, FLEXIO_UART_TransferHandleIRQ); } +/*! + * brief Sets up the RX ring buffer. + * + * This function sets up the RX ring buffer to a specific UART handle. + * + * When the RX ring buffer is used, data received is stored into the ring buffer even when + * the user doesn't call the UART_ReceiveNonBlocking() API. If there is already data received + * in the ring buffer, users can get the received data from the ring buffer directly. + * + * note When using the RX ring buffer, one byte is reserved for internal use. In other + * words, if p ringBufferSize is 32, only 31 bytes are used for saving data. + * + * param base Pointer to the FLEXIO_UART_Type structure. + * param handle Pointer to the flexio_uart_handle_t structure to store the transfer state. + * param ringBuffer Start address of ring buffer for background receiving. Pass NULL to disable the ring buffer. + * param ringBufferSize Size of the ring buffer. + */ void FLEXIO_UART_TransferStartRingBuffer(FLEXIO_UART_Type *base, flexio_uart_handle_t *handle, uint8_t *ringBuffer, @@ -369,6 +508,14 @@ void FLEXIO_UART_TransferStartRingBuffer(FLEXIO_UART_Type *base, } } +/*! + * brief Aborts the background transfer and uninstalls the ring buffer. + * + * This function aborts the background transfer and uninstalls the ring buffer. + * + * param base Pointer to the FLEXIO_UART_Type structure. + * param handle Pointer to the flexio_uart_handle_t structure to store the transfer state. + */ void FLEXIO_UART_TransferStopRingBuffer(FLEXIO_UART_Type *base, flexio_uart_handle_t *handle) { assert(handle); @@ -384,6 +531,23 @@ void FLEXIO_UART_TransferStopRingBuffer(FLEXIO_UART_Type *base, flexio_uart_hand handle->rxRingBufferTail = 0U; } +/*! + * brief Transmits a buffer of data using the interrupt method. + * + * This function sends data using an interrupt method. This is a non-blocking function, + * which returns directly without waiting for all data to be written to the TX register. When + * all data is written to the TX register in ISR, the FlexIO UART driver calls the callback + * function and passes the ref kStatus_FLEXIO_UART_TxIdle as status parameter. + * + * note The kStatus_FLEXIO_UART_TxIdle is passed to the upper layer when all data is written + * to the TX register. However, it does not ensure that all data is sent out. + * + * param base Pointer to the FLEXIO_UART_Type structure. + * param handle Pointer to the flexio_uart_handle_t structure to store the transfer state. + * param xfer FlexIO UART transfer structure. See #flexio_uart_transfer_t. + * retval kStatus_Success Successfully starts the data transmission. + * retval kStatus_UART_TxBusy Previous transmission still not finished, data not written to the TX register. + */ status_t FLEXIO_UART_TransferSendNonBlocking(FLEXIO_UART_Type *base, flexio_uart_handle_t *handle, flexio_uart_transfer_t *xfer) @@ -417,6 +581,15 @@ status_t FLEXIO_UART_TransferSendNonBlocking(FLEXIO_UART_Type *base, return status; } +/*! + * brief Aborts the interrupt-driven data transmit. + * + * This function aborts the interrupt-driven data sending. Get the remainBytes to find out + * how many bytes are still not sent out. + * + * param base Pointer to the FLEXIO_UART_Type structure. + * param handle Pointer to the flexio_uart_handle_t structure to store the transfer state. + */ void FLEXIO_UART_TransferAbortSend(FLEXIO_UART_Type *base, flexio_uart_handle_t *handle) { /* Disable the transmitter and disable the interrupt. */ @@ -426,6 +599,17 @@ void FLEXIO_UART_TransferAbortSend(FLEXIO_UART_Type *base, flexio_uart_handle_t handle->txState = kFLEXIO_UART_TxIdle; } +/*! + * brief Gets the number of bytes sent. + * + * This function gets the number of bytes sent driven by interrupt. + * + * param base Pointer to the FLEXIO_UART_Type structure. + * param handle Pointer to the flexio_uart_handle_t structure to store the transfer state. + * param count Number of bytes sent so far by the non-blocking transaction. + * retval kStatus_NoTransferInProgress transfer has finished or no transfer in progress. + * retval kStatus_Success Successfully return the count. + */ status_t FLEXIO_UART_TransferGetSendCount(FLEXIO_UART_Type *base, flexio_uart_handle_t *handle, size_t *count) { assert(handle); @@ -441,6 +625,31 @@ status_t FLEXIO_UART_TransferGetSendCount(FLEXIO_UART_Type *base, flexio_uart_ha return kStatus_Success; } +/*! + * brief Receives a buffer of data using the interrupt method. + * + * This function receives data using the interrupt method. This is a non-blocking function, + * which returns without waiting for all data to be received. + * If the RX ring buffer is used and not empty, the data in ring buffer is copied and + * the parameter p receivedBytes shows how many bytes are copied from the ring buffer. + * After copying, if the data in ring buffer is not enough to read, the receive + * request is saved by the UART driver. When new data arrives, the receive request + * is serviced first. When all data is received, the UART driver notifies the upper layer + * through a callback function and passes the status parameter ref kStatus_UART_RxIdle. + * For example, if the upper layer needs 10 bytes but there are only 5 bytes in the ring buffer, + * the 5 bytes are copied to xfer->data. This function returns with the + * parameter p receivedBytes set to 5. For the last 5 bytes, newly arrived data is + * saved from the xfer->data[5]. When 5 bytes are received, the UART driver notifies upper layer. + * If the RX ring buffer is not enabled, this function enables the RX and RX interrupt + * to receive data to xfer->data. When all data is received, the upper layer is notified. + * + * param base Pointer to the FLEXIO_UART_Type structure. + * param handle Pointer to the flexio_uart_handle_t structure to store the transfer state. + * param xfer UART transfer structure. See #flexio_uart_transfer_t. + * param receivedBytes Bytes received from the ring buffer directly. + * retval kStatus_Success Successfully queue the transfer into the transmit queue. + * retval kStatus_FLEXIO_UART_RxBusy Previous receive request is not finished. + */ status_t FLEXIO_UART_TransferReceiveNonBlocking(FLEXIO_UART_Type *base, flexio_uart_handle_t *handle, flexio_uart_transfer_t *xfer, @@ -524,6 +733,15 @@ status_t FLEXIO_UART_TransferReceiveNonBlocking(FLEXIO_UART_Type *base, /* Enable FLEXIO_UART RX IRQ if previously enabled. */ FLEXIO_UART_EnableInterrupts(base, kFLEXIO_UART_RxDataRegFullInterruptEnable); + + /* Call user callback since all data are received. */ + if (0 == bytesToReceive) + { + if (handle->callback) + { + handle->callback(base, handle, kStatus_FLEXIO_UART_RxIdle, handle->userData); + } + } } /* Ring buffer not used. */ else @@ -549,6 +767,14 @@ status_t FLEXIO_UART_TransferReceiveNonBlocking(FLEXIO_UART_Type *base, return status; } +/*! + * brief Aborts the receive data which was using IRQ. + * + * This function aborts the receive data which was using IRQ. + * + * param base Pointer to the FLEXIO_UART_Type structure. + * param handle Pointer to the flexio_uart_handle_t structure to store the transfer state. + */ void FLEXIO_UART_TransferAbortReceive(FLEXIO_UART_Type *base, flexio_uart_handle_t *handle) { /* Only abort the receive to handle->rxData, the RX ring buffer is still working. */ @@ -562,6 +788,17 @@ void FLEXIO_UART_TransferAbortReceive(FLEXIO_UART_Type *base, flexio_uart_handle handle->rxState = kFLEXIO_UART_RxIdle; } +/*! + * brief Gets the number of bytes received. + * + * This function gets the number of bytes received driven by interrupt. + * + * param base Pointer to the FLEXIO_UART_Type structure. + * param handle Pointer to the flexio_uart_handle_t structure to store the transfer state. + * param count Number of bytes received so far by the non-blocking transaction. + * retval kStatus_NoTransferInProgress transfer has finished or no transfer in progress. + * retval kStatus_Success Successfully return the count. + */ status_t FLEXIO_UART_TransferGetReceiveCount(FLEXIO_UART_Type *base, flexio_uart_handle_t *handle, size_t *count) { assert(handle); @@ -577,6 +814,14 @@ status_t FLEXIO_UART_TransferGetReceiveCount(FLEXIO_UART_Type *base, flexio_uart return kStatus_Success; } +/*! + * brief FlexIO UART IRQ handler function. + * + * This function processes the FlexIO UART transmit and receives the IRQ request. + * + * param uartType Pointer to the FLEXIO_UART_Type structure. + * param uartHandle Pointer to the flexio_uart_handle_t structure to store the transfer state. + */ void FLEXIO_UART_TransferHandleIRQ(void *uartType, void *uartHandle) { uint8_t count = 1; diff --git a/ext/hal/nxp/mcux/drivers/imx/fsl_flexio_uart.h b/ext/hal/nxp/mcux/drivers/imx/fsl_flexio_uart.h index 37b85c644d1..b9c5622cef9 100644 --- a/ext/hal/nxp/mcux/drivers/imx/fsl_flexio_uart.h +++ b/ext/hal/nxp/mcux/drivers/imx/fsl_flexio_uart.h @@ -1,8 +1,8 @@ /* * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP + * Copyright 2016-2018 NXP * All rights reserved. - * + * * SPDX-License-Identifier: BSD-3-Clause */ @@ -23,8 +23,8 @@ /*! @name Driver version */ /*@{*/ -/*! @brief FlexIO UART driver version 2.1.4. */ -#define FSL_FLEXIO_UART_DRIVER_VERSION (MAKE_VERSION(2, 1, 4)) +/*! @brief FlexIO UART driver version 2.1.5. */ +#define FSL_FLEXIO_UART_DRIVER_VERSION (MAKE_VERSION(2, 1, 5)) /*@}*/ /*! @brief Error codes for the UART driver. */ diff --git a/ext/hal/nxp/mcux/drivers/imx/fsl_flexio_uart_edma.c b/ext/hal/nxp/mcux/drivers/imx/fsl_flexio_uart_edma.c index 3fa908053ec..4bec051160a 100644 --- a/ext/hal/nxp/mcux/drivers/imx/fsl_flexio_uart_edma.c +++ b/ext/hal/nxp/mcux/drivers/imx/fsl_flexio_uart_edma.c @@ -2,7 +2,7 @@ * Copyright (c) 2015, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP * All rights reserved. - * + * * SPDX-License-Identifier: BSD-3-Clause */ @@ -17,7 +17,6 @@ #define FSL_COMPONENT_ID "platform.drivers.flexio_uart_edma" #endif - /*txEdmaHandle); @@ -282,6 +325,14 @@ void FLEXIO_UART_TransferAbortSendEDMA(FLEXIO_UART_Type *base, flexio_uart_edma_ handle->txState = kFLEXIO_UART_TxIdle; } +/*! + * brief Aborts the receive data which using eDMA. + * + * This function aborts the receive data which using eDMA. + * + * param base Pointer to FLEXIO_UART_Type + * param handle Pointer to flexio_uart_edma_handle_t structure + */ void FLEXIO_UART_TransferAbortReceiveEDMA(FLEXIO_UART_Type *base, flexio_uart_edma_handle_t *handle) { assert(handle->rxEdmaHandle); @@ -295,6 +346,17 @@ void FLEXIO_UART_TransferAbortReceiveEDMA(FLEXIO_UART_Type *base, flexio_uart_ed handle->rxState = kFLEXIO_UART_RxIdle; } +/*! + * brief Gets the number of bytes received. + * + * This function gets the number of bytes received. + * + * param base Pointer to FLEXIO_UART_Type + * param handle Pointer to flexio_uart_edma_handle_t structure + * param count Number of bytes received so far by the non-blocking transaction. + * retval kStatus_NoTransferInProgress transfer has finished or no transfer in progress. + * retval kStatus_Success Successfully return the count. + */ status_t FLEXIO_UART_TransferGetReceiveCountEDMA(FLEXIO_UART_Type *base, flexio_uart_edma_handle_t *handle, size_t *count) @@ -315,6 +377,17 @@ status_t FLEXIO_UART_TransferGetReceiveCountEDMA(FLEXIO_UART_Type *base, return kStatus_Success; } +/*! + * brief Gets the number of bytes sent out. + * + * This function gets the number of bytes sent out. + * + * param base Pointer to FLEXIO_UART_Type + * param handle Pointer to flexio_uart_edma_handle_t structure + * param count Number of bytes sent so far by the non-blocking transaction. + * retval kStatus_NoTransferInProgress transfer has finished or no transfer in progress. + * retval kStatus_Success Successfully return the count. + */ status_t FLEXIO_UART_TransferGetSendCountEDMA(FLEXIO_UART_Type *base, flexio_uart_edma_handle_t *handle, size_t *count) { assert(handle); diff --git a/ext/hal/nxp/mcux/drivers/imx/fsl_flexram.c b/ext/hal/nxp/mcux/drivers/imx/fsl_flexram.c index 4aac150d375..a2f68853589 100644 --- a/ext/hal/nxp/mcux/drivers/imx/fsl_flexram.c +++ b/ext/hal/nxp/mcux/drivers/imx/fsl_flexram.c @@ -2,7 +2,7 @@ * Copyright 2017 NXP * All rights reserved. * - * + * * SPDX-License-Identifier: BSD-3-Clause */ @@ -37,15 +37,6 @@ static uint32_t FLEXRAM_GetInstance(FLEXRAM_Type *base); */ static uint8_t FLEXRAM_MapTcmSizeToRegister(uint8_t tcmBankNum); -/*! - * @brief FLEXRAM configure TCM size - * This function is used to set the TCM to the actual size.When access to the TCM memory boundary ,hardfault will - * raised by core. - * @param itcmBankNum itcm bank number to allocate - * @param dtcmBankNum dtcm bank number to allocate - */ -static status_t FLEXRAM_SetTCMSize(uint8_t itcmBankNum, uint8_t dtcmBankNum); - /******************************************************************************* * Variables ******************************************************************************/ @@ -78,6 +69,11 @@ static uint32_t FLEXRAM_GetInstance(FLEXRAM_Type *base) return instance; } +/*! + * brief FLEXRAM module initialization function. + * + * param base FLEXRAM base address. + */ void FLEXRAM_Init(FLEXRAM_Type *base) { #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) @@ -93,6 +89,10 @@ void FLEXRAM_Init(FLEXRAM_Type *base) base->INT_SIG_EN = 0U; } +/*! + * brief Deinitializes the FLEXRAM. + * + */ void FLEXRAN_Deinit(FLEXRAM_Type *base) { #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) @@ -104,38 +104,40 @@ void FLEXRAN_Deinit(FLEXRAM_Type *base) static uint8_t FLEXRAM_MapTcmSizeToRegister(uint8_t tcmBankNum) { uint8_t tcmSizeConfig = 0U; + uint32_t totalTcmSize = 0U; - switch (tcmBankNum * FSL_FEATURE_FLEXRAM_INTERNAL_RAM_BANK_SIZE) + /* if bank number is a odd value, use a new bank number which bigger than target */ + do { - case kFLEXRAM_TCMSize32KB: - tcmSizeConfig = 6U; + if ((tcmBankNum & (tcmBankNum - 1U)) == 0U) + { break; + } + } while (++tcmBankNum < FSL_FEATURE_FLEXRAM_INTERNAL_RAM_TOTAL_BANK_NUMBERS); - case kFLEXRAM_TCMSize64KB: - tcmSizeConfig = 7U; - break; - - case kFLEXRAM_TCMSize128KB: - tcmSizeConfig = 8U; - break; - - case kFLEXRAM_TCMSize256KB: - tcmSizeConfig = 9U; - break; - - case kFLEXRAM_TCMSize512KB: - tcmSizeConfig = 10U; - break; - - default: + totalTcmSize = tcmBankNum * (FSL_FEATURE_FLEXRAM_INTERNAL_RAM_BANK_SIZE >> 10U); + /* get bit '1' position */ + while (totalTcmSize) + { + if ((totalTcmSize & 1U) == 0U) + { + tcmSizeConfig++; + } + else + { break; + } + totalTcmSize >>= 1U; } - return tcmSizeConfig; + return tcmSizeConfig + 1U; } -static status_t FLEXRAM_SetTCMSize(uint8_t itcmBankNum, uint8_t dtcmBankNum) +void FLEXRAM_SetTCMSize(uint8_t itcmBankNum, uint8_t dtcmBankNum) { + assert(itcmBankNum <= FSL_FEATURE_FLEXRAM_INTERNAL_RAM_TOTAL_BANK_NUMBERS); + assert(dtcmBankNum <= FSL_FEATURE_FLEXRAM_INTERNAL_RAM_TOTAL_BANK_NUMBERS); + /* dtcm configuration */ if (dtcmBankNum != 0U) { @@ -147,6 +149,7 @@ static status_t FLEXRAM_SetTCMSize(uint8_t itcmBankNum, uint8_t dtcmBankNum) { IOMUXC_GPR->GPR16 &= ~IOMUXC_GPR_GPR16_INIT_DTCM_EN_MASK; } + /* itcm configuration */ if (itcmBankNum != 0U) { @@ -158,21 +161,27 @@ static status_t FLEXRAM_SetTCMSize(uint8_t itcmBankNum, uint8_t dtcmBankNum) { IOMUXC_GPR->GPR16 &= ~IOMUXC_GPR_GPR16_INIT_ITCM_EN_MASK; } - - return kStatus_Success; } +/*! + * brief FLEXRAM allocate on-chip ram for OCRAM,ITCM,DTCM + * This function is independent of FLEXRAM_Init, it can be called directly if ram re-allocate + * is needed. + * param config allocate configuration. + * retval kStatus_InvalidArgument the argument is invalid + * kStatus_Success allocate success + */ status_t FLEXRAM_AllocateRam(flexram_allocate_ram_t *config) { + assert(config != NULL); + uint8_t dtcmBankNum = config->dtcmBankNum; uint8_t itcmBankNum = config->itcmBankNum; uint8_t ocramBankNum = config->ocramBankNum; uint32_t bankCfg = 0U, i = 0U; /* check the arguments */ - if ((FSL_FEATURE_FLEXRAM_INTERNAL_RAM_TOTAL_BANK_NUMBERS < (dtcmBankNum + itcmBankNum + ocramBankNum)) || - ((dtcmBankNum != 0U) && ((dtcmBankNum & (dtcmBankNum - 1u)) != 0U)) || - ((itcmBankNum != 0U) && ((itcmBankNum & (itcmBankNum - 1u)) != 0U))) + if (FSL_FEATURE_FLEXRAM_INTERNAL_RAM_TOTAL_BANK_NUMBERS < (dtcmBankNum + itcmBankNum + ocramBankNum)) { return kStatus_InvalidArgument; } diff --git a/ext/hal/nxp/mcux/drivers/imx/fsl_flexram.h b/ext/hal/nxp/mcux/drivers/imx/fsl_flexram.h index 9fdce9f87fb..0963e76df66 100644 --- a/ext/hal/nxp/mcux/drivers/imx/fsl_flexram.h +++ b/ext/hal/nxp/mcux/drivers/imx/fsl_flexram.h @@ -2,7 +2,7 @@ * Copyright 2017 NXP * All rights reserved. * - * + * * SPDX-License-Identifier: BSD-3-Clause */ @@ -22,8 +22,8 @@ /*! @name Driver version */ /*@{*/ -/*! @brief Driver version 2.0.2. */ -#define FSL_FLEXRAM_DRIVER_VERSION (MAKE_VERSION(2U, 0U, 2U)) +/*! @brief Driver version 2.0.4. */ +#define FSL_FLEXRAM_DRIVER_VERSION (MAKE_VERSION(2U, 0U, 4U)) /*@}*/ /*! @brief flexram write read sel */ @@ -36,14 +36,12 @@ enum _flexram_wr_rd_sel /*! @brief Interrupt status flag mask */ enum _flexram_interrupt_status { - kFLEXRAM_OCRAMAccessError = FLEXRAM_INT_STATUS_OCRAM_ERR_STATUS_MASK, /*!< ocram access unallocated address */ - kFLEXRAM_DTCMAccessError = FLEXRAM_INT_STATUS_DTCM_ERR_STATUS_MASK, /*!< dtcm access unallocated address */ - kFLEXRAM_ITCMAccessError = FLEXRAM_INT_STATUS_ITCM_ERR_STATUS_MASK, /*!< itcm access unallocated address */ - kFLEXRAM_OCRAMMagicAddrMatch = FLEXRAM_INT_STATUS_OCRAM_MAM_STATUS_MASK, /*!< ocram maigc address match */ - kFLEXRAM_DTCMMagicAddrMatch = FLEXRAM_INT_STATUS_DTCM_MAM_STATUS_MASK, /*!< dtcm maigc address match */ - kFLEXRAM_ITCMMagicAddrMatch = FLEXRAM_INT_STATUS_ITCM_MAM_STATUS_MASK, /*!< itcm maigc address match */ + kFLEXRAM_OCRAMAccessError = FLEXRAM_INT_STATUS_OCRAM_ERR_STATUS_MASK, /*!< ocram access unallocated address */ + kFLEXRAM_DTCMAccessError = FLEXRAM_INT_STATUS_DTCM_ERR_STATUS_MASK, /*!< dtcm access unallocated address */ + kFLEXRAM_ITCMAccessError = FLEXRAM_INT_STATUS_ITCM_ERR_STATUS_MASK, /*!< itcm access unallocated address */ - kFLEXRAM_InterruptStatusAll = 0x3FU, /*!< all the interrupt status mask */ + kFLEXRAM_InterruptStatusAll = FLEXRAM_INT_STATUS_OCRAM_ERR_STATUS_MASK | FLEXRAM_INT_STATUS_DTCM_ERR_STATUS_MASK | + FLEXRAM_INT_STATUS_ITCM_ERR_STATUS_MASK, /*!< all the interrupt status mask */ }; /*! @brief FLEXRAM TCM access mode @@ -92,6 +90,15 @@ typedef struct _flexram_allocate_ram const uint8_t dtcmBankNum; /*!< dtcm bank number to allocate, the number should be power of 2 */ const uint8_t itcmBankNum; /*!< itcm bank number to allocate, the number should be power of 2 */ } flexram_allocate_ram_t; + +/******************************************************************************* + * APIs + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + /*! * @name Initialization and deinitialization * @{ @@ -236,42 +243,6 @@ static inline void FLEXRAM_EnableForceRamClockOn(FLEXRAM_Type *base, bool enable } } -/*! - * @brief FLEXRAM OCRAM magic addr configuration - * When read/write access hit magic address, it will generate interrupt - * @param magicAddr magic address. - * @param rwsel read write select, 0 read access , 1 write access - */ -static inline void FLEXRAM_SetOCRAMMagicAddr(FLEXRAM_Type *base, uint16_t magicAddr, uint32_t rwSel) -{ - base->OCRAM_MAGIC_ADDR = - FLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_WR_RD_SEL(rwSel) | FLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_MAGIC_ADDR(magicAddr >> 3U); -} - -/*! - * @brief FLEXRAM DTCM magic addr configuration - * When read/write access hit magic address, it will generate interrupt - * @param magicAddr magic address. - * @param rwsel read write select, 0 read access , 1 write access - */ -static inline void FLEXRAM_SetDTCMMagicAddr(FLEXRAM_Type *base, uint16_t magicAddr, uint32_t rwSel) -{ - base->DTCM_MAGIC_ADDR = - FLEXRAM_DTCM_MAGIC_ADDR_DTCM_WR_RD_SEL(rwSel) | FLEXRAM_DTCM_MAGIC_ADDR_DTCM_MAGIC_ADDR(magicAddr >> 3U); -} - -/*! - * @brief FLEXRAM ITCM magic addr configuration - * When read/write access hit magic address, it will generate interrupt - * @param magicAddr magic address. - * @param rwsel read write select, 0 read access , 1 write access - */ -static inline void FLEXRAM_SetITCMMagicAddr(FLEXRAM_Type *base, uint16_t magicAddr, uint32_t rwSel) -{ - base->ITCM_MAGIC_ADDR = - FLEXRAM_ITCM_MAGIC_ADDR_ITCM_WR_RD_SEL(rwSel) | FLEXRAM_ITCM_MAGIC_ADDR_ITCM_MAGIC_ADDR(magicAddr >> 3U); -} - /*! * @brief FLEXRAM allocate on-chip ram for OCRAM,ITCM,DTCM * This function is independent of FLEXRAM_Init, it can be called directly if ram re-allocate @@ -292,6 +263,22 @@ static inline void FLEXRAM_SetAllocateRamSrc(flexram_bank_allocate_src_t src) IOMUXC_GPR->GPR16 |= IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL(src); } +/*! + * @brief FLEXRAM configure TCM size + * This function is used to set the TCM to the target size. If a odd bank number is used, + * a new banknumber will be used which is bigger than target value, application can set tcm + * size to the biggest bank number always, then boundary access error can be captured by flexram only. + * When access to the TCM memory boundary ,hardfault will raised by core. + * @param itcmBankNum itcm bank number to allocate + * @param dtcmBankNum dtcm bank number to allocate + * + */ +void FLEXRAM_SetTCMSize(uint8_t itcmBankNum, uint8_t dtcmBankNum); + +#if defined(__cplusplus) +} +#endif + /*! @}*/ #endif diff --git a/ext/hal/nxp/mcux/drivers/imx/fsl_flexspi.c b/ext/hal/nxp/mcux/drivers/imx/fsl_flexspi.c index 60024d91269..a1fc50fb692 100644 --- a/ext/hal/nxp/mcux/drivers/imx/fsl_flexspi.c +++ b/ext/hal/nxp/mcux/drivers/imx/fsl_flexspi.c @@ -2,7 +2,7 @@ * Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP * All rights reserved. - * + * * SPDX-License-Identifier: BSD-3-Clause */ @@ -13,7 +13,6 @@ #define FSL_COMPONENT_ID "platform.drivers.flexspi" #endif - /******************************************************************************* * Definitations ******************************************************************************/ @@ -80,12 +79,6 @@ status_t FLEXSPI_CheckAndClearError(FLEXSPI_Type *base, uint32_t status); /******************************************************************************* * Variables ******************************************************************************/ - -#if defined(FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ) && FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ -/*! @brief Pointers to flexspi handles for each instance. */ -static void *s_flexspiHandle[FSL_FEATURE_SOC_FLEXSPI_COUNT]; -#endif - /*! @brief Pointers to flexspi bases for each instance. */ static FLEXSPI_Type *const s_flexspiBases[] = FLEXSPI_BASE_PTRS; @@ -97,6 +90,11 @@ static const IRQn_Type s_flexspiIrqs[] = FLEXSPI_IRQS; static const clock_ip_name_t s_flexspiClock[] = FLEXSPI_CLOCKS; #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +#if defined(FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ) && FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ +/*! @brief Pointers to flexspi handles for each instance. */ +static void *s_flexspiHandle[ARRAY_SIZE(s_flexspiBases)]; +#endif + /******************************************************************************* * Code ******************************************************************************/ @@ -106,7 +104,7 @@ uint32_t FLEXSPI_GetInstance(FLEXSPI_Type *base) uint32_t instance; /* Find the instance index from base address mappings. */ - for (instance = 0; instance < FSL_FEATURE_SOC_FLEXSPI_COUNT; instance++) + for (instance = 0; instance < ARRAY_SIZE(s_flexspiBases); instance++) { if (s_flexspiBases[instance] == base) { @@ -114,7 +112,7 @@ uint32_t FLEXSPI_GetInstance(FLEXSPI_Type *base) } } - assert(instance < FSL_FEATURE_SOC_FLEXSPI_COUNT); + assert(instance < ARRAY_SIZE(s_flexspiBases)); return instance; } @@ -210,6 +208,15 @@ status_t FLEXSPI_CheckAndClearError(FLEXSPI_Type *base, uint32_t status) return result; } +/*! + * brief Initializes the FLEXSPI module and internal state. + * + * This function enables the clock for FLEXSPI and also configures the FLEXSPI with the + * input configure parameters. Users should call this function before any FLEXSPI operations. + * + * param base FLEXSPI peripheral base address. + * param config FLEXSPI configure structure. + */ void FLEXSPI_Init(FLEXSPI_Type *base, const flexspi_config_t *config) { uint32_t configValue = 0; @@ -281,10 +288,24 @@ void FLEXSPI_Init(FLEXSPI_Type *base, const flexspi_config_t *config) base->IPRXFCR |= FLEXSPI_IPRXFCR_RXWMRK(config->rxWatermark / 8 - 1); base->IPTXFCR &= ~FLEXSPI_IPTXFCR_TXWMRK_MASK; base->IPTXFCR |= FLEXSPI_IPTXFCR_TXWMRK(config->txWatermark / 8 - 1); + + /* Reset flash size on all ports */ + for (i = 0; i < kFLEXSPI_PortCount; i++) + { + base->FLSHCR0[i] = 0; + } } +/*! + * brief Gets default settings for FLEXSPI. + * + * param config FLEXSPI configuration structure. + */ void FLEXSPI_GetDefaultConfig(flexspi_config_t *config) { + /* Initializes the configure structure to zero. */ + memset(config, 0, sizeof(*config)); + config->rxSampleClock = kFLEXSPI_ReadSampleClkLoopbackInternally; config->enableSckFreeRunning = false; config->enableCombination = false; @@ -313,12 +334,29 @@ void FLEXSPI_GetDefaultConfig(flexspi_config_t *config) config->ahbConfig.enableAHBCachable = false; } +/*! + * brief Deinitializes the FLEXSPI module. + * + * Clears the FLEXSPI state and FLEXSPI module registers. + * param base FLEXSPI peripheral base address. + */ void FLEXSPI_Deinit(FLEXSPI_Type *base) { /* Reset peripheral. */ FLEXSPI_SoftwareReset(base); } +/*! + * brief Configures the connected device parameter. + * + * This function configures the connected device relevant parameters, such as the size, command, and so on. + * The flash configuration value cannot have a default value. The user needs to configure it according to the + * connected device. + * + * param base FLEXSPI peripheral base address. + * param config Flash configuration parameters. + * param port FLEXSPI Operation port. + */ void FLEXSPI_SetFlashConfig(FLEXSPI_Type *base, flexspi_device_config_t *config, flexspi_port_t port) { uint32_t configValue = 0; @@ -330,7 +368,6 @@ void FLEXSPI_SetFlashConfig(FLEXSPI_Type *base, flexspi_device_config_t *config, } /* Configure flash size. */ - base->FLSHCR0[index] = 0; base->FLSHCR0[port] = config->flashSize; /* Configure flash parameters. */ @@ -390,6 +427,15 @@ void FLEXSPI_SetFlashConfig(FLEXSPI_Type *base, flexspi_device_config_t *config, base->MCR0 &= ~FLEXSPI_MCR0_MDIS_MASK; } +/*! brief Updates the LUT table. +* +* param base FLEXSPI peripheral base address. +* param index From which index start to update. It could be any index of the LUT table, which +* also allows user to update command content inside a command. Each command consists of up to +* 8 instructions and occupy 4*32-bit memory. +* param cmd Command sequence array. +* param count Number of sequences. +*/ void FLEXSPI_UpdateLUT(FLEXSPI_Type *base, uint32_t index, const uint32_t *cmd, uint32_t count) { assert(index < 64U); @@ -407,7 +453,7 @@ void FLEXSPI_UpdateLUT(FLEXSPI_Type *base, uint32_t index, const uint32_t *cmd, base->LUTCR = 0x02; lutBase = &base->LUT[index]; - for (i = index; i < count; i++) + for (i = 0; i < count; i++) { *lutBase++ = *cmd++; } @@ -417,6 +463,17 @@ void FLEXSPI_UpdateLUT(FLEXSPI_Type *base, uint32_t index, const uint32_t *cmd, base->LUTCR = 0x01; } +/*! + * brief Sends a buffer of data bytes using blocking method. + * note This function blocks via polling until all bytes have been sent. + * param base FLEXSPI peripheral base address + * param buffer The data bytes to send + * param size The number of data bytes to send + * retval kStatus_Success write success without error + * retval kStatus_FLEXSPI_SequenceExecutionTimeout sequence execution timeout + * retval kStatus_FLEXSPI_IpCommandSequenceError IP command sequencen error detected + * retval kStatus_FLEXSPI_IpCommandGrantTimeout IP command grant timeout detected + */ status_t FLEXSPI_WriteBlocking(FLEXSPI_Type *base, uint32_t *buffer, size_t size) { uint8_t txWatermark = ((base->IPTXFCR & FLEXSPI_IPTXFCR_TXWMRK_MASK) >> FLEXSPI_IPTXFCR_TXWMRK_SHIFT) + 1; @@ -465,6 +522,17 @@ status_t FLEXSPI_WriteBlocking(FLEXSPI_Type *base, uint32_t *buffer, size_t size return result; } +/*! + * brief Receives a buffer of data bytes using a blocking method. + * note This function blocks via polling until all bytes have been sent. + * param base FLEXSPI peripheral base address + * param buffer The data bytes to send + * param size The number of data bytes to receive + * retval kStatus_Success read success without error + * retval kStatus_FLEXSPI_SequenceExecutionTimeout sequence execution timeout + * retval kStatus_FLEXSPI_IpCommandSequenceError IP command sequencen error detected + * retval kStatus_FLEXSPI_IpCommandGrantTimeout IP command grant timeout detected + */ status_t FLEXSPI_ReadBlocking(FLEXSPI_Type *base, uint32_t *buffer, size_t size) { uint8_t rxWatermark = ((base->IPRXFCR & FLEXSPI_IPRXFCR_RXWMRK_MASK) >> FLEXSPI_IPRXFCR_RXWMRK_SHIFT) + 1; @@ -535,6 +603,15 @@ status_t FLEXSPI_ReadBlocking(FLEXSPI_Type *base, uint32_t *buffer, size_t size) return result; } +/*! + * brief Execute command to transfer a buffer data bytes using a blocking method. + * param base FLEXSPI peripheral base address + * param xfer pointer to the transfer structure. + * retval kStatus_Success command transfer success without error + * retval kStatus_FLEXSPI_SequenceExecutionTimeout sequence execution timeout + * retval kStatus_FLEXSPI_IpCommandSequenceError IP command sequencen error detected + * retval kStatus_FLEXSPI_IpCommandGrantTimeout IP command grant timeout detected +*/ status_t FLEXSPI_TransferBlocking(FLEXSPI_Type *base, flexspi_transfer_t *xfer) { uint32_t configValue = 0; @@ -592,6 +669,14 @@ status_t FLEXSPI_TransferBlocking(FLEXSPI_Type *base, flexspi_transfer_t *xfer) return result; } +/*! + * brief Initializes the FLEXSPI handle which is used in transactional functions. + * + * param base FLEXSPI peripheral base address. + * param handle pointer to flexspi_handle_t structure to store the transfer state. + * param callback pointer to user callback function. + * param userData user parameter passed to the callback function. + */ void FLEXSPI_TransferCreateHandle(FLEXSPI_Type *base, flexspi_handle_t *handle, flexspi_transfer_callback_t callback, @@ -617,6 +702,21 @@ void FLEXSPI_TransferCreateHandle(FLEXSPI_Type *base, EnableIRQ(s_flexspiIrqs[instance]); } +/*! + * brief Performs a interrupt non-blocking transfer on the FLEXSPI bus. + * + * note Calling the API returns immediately after transfer initiates. The user needs + * to call FLEXSPI_GetTransferCount to poll the transfer status to check whether + * the transfer is finished. If the return status is not kStatus_FLEXSPI_Busy, the transfer + * is finished. For FLEXSPI_Read, the dataSize should be multiple of rx watermark levle, or + * FLEXSPI could not read data properly. + * + * param base FLEXSPI peripheral base address. + * param handle pointer to flexspi_handle_t structure which stores the transfer state. + * param xfer pointer to flexspi_transfer_t structure. + * retval kStatus_Success Successfully start the data transmission. + * retval kStatus_FLEXSPI_Busy Previous transmission still not finished. + */ status_t FLEXSPI_TransferNonBlocking(FLEXSPI_Type *base, flexspi_handle_t *handle, flexspi_transfer_t *xfer) { uint32_t configValue = 0; @@ -683,6 +783,15 @@ status_t FLEXSPI_TransferNonBlocking(FLEXSPI_Type *base, flexspi_handle_t *handl return result; } +/*! + * brief Gets the master transfer status during a interrupt non-blocking transfer. + * + * param base FLEXSPI peripheral base address. + * param handle pointer to flexspi_handle_t structure which stores the transfer state. + * param count Number of bytes transferred so far by the non-blocking transaction. + * retval kStatus_InvalidArgument count is Invalid. + * retval kStatus_Success Successfully return the count. + */ status_t FLEXSPI_TransferGetCount(FLEXSPI_Type *base, flexspi_handle_t *handle, size_t *count) { assert(handle); @@ -701,6 +810,15 @@ status_t FLEXSPI_TransferGetCount(FLEXSPI_Type *base, flexspi_handle_t *handle, return result; } +/*! + * brief Aborts an interrupt non-blocking transfer early. + * + * note This API can be called at any time when an interrupt non-blocking transfer initiates + * to abort the transfer early. + * + * param base FLEXSPI peripheral base address. + * param handle pointer to flexspi_handle_t structure which stores the transfer state + */ void FLEXSPI_TransferAbort(FLEXSPI_Type *base, flexspi_handle_t *handle) { assert(handle); @@ -709,6 +827,12 @@ void FLEXSPI_TransferAbort(FLEXSPI_Type *base, flexspi_handle_t *handle) handle->state = kFLEXSPI_Idle; } +/*! + * brief Master interrupt handler. + * + * param base FLEXSPI peripheral base address. + * param handle pointer to flexspi_handle_t structure. + */ void FLEXSPI_TransferHandleIRQ(FLEXSPI_Type *base, flexspi_handle_t *handle) { uint8_t status; diff --git a/ext/hal/nxp/mcux/drivers/imx/fsl_flexspi.h b/ext/hal/nxp/mcux/drivers/imx/fsl_flexspi.h index 79aaf26415f..d355462a91d 100644 --- a/ext/hal/nxp/mcux/drivers/imx/fsl_flexspi.h +++ b/ext/hal/nxp/mcux/drivers/imx/fsl_flexspi.h @@ -2,7 +2,7 @@ * Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP * All rights reserved. - * + * * SPDX-License-Identifier: BSD-3-Clause */ @@ -24,8 +24,8 @@ /*! @name Driver version */ /*@{*/ -/*! @brief FLEXSPI driver version 2.0.3. */ -#define FSL_FLEXSPI_DRIVER_VERSION (MAKE_VERSION(2, 0, 3)) +/*! @brief FLEXSPI driver version 2.0.5. */ +#define FSL_FLEXSPI_DRIVER_VERSION (MAKE_VERSION(2, 0, 5)) /*@}*/ #define FSL_FEATURE_FLEXSPI_AHB_BUFFER_COUNT FSL_FEATURE_FLEXSPI_AHB_BUFFER_COUNTn(0) @@ -185,9 +185,10 @@ typedef enum _flexspi_ahb_error_code typedef enum _flexspi_port { kFLEXSPI_PortA1 = 0x0U, /*!< Access flash on A1 port. */ - kFLEXSPI_PortA2 = 0x1U, /*!< Access flash on A2 port. */ - kFLEXSPI_PortB1 = 0x2U, /*!< Access flash on B1 port. */ - kFLEXSPI_PortB2 = 0x3U, /*!< Access flash on B2 port. */ + kFLEXSPI_PortA2, /*!< Access flash on A2 port. */ + kFLEXSPI_PortB1, /*!< Access flash on B1 port. */ + kFLEXSPI_PortB2, /*!< Access flash on B2 port. */ + kFLEXSPI_PortCount } flexspi_port_t; /*! @brief Trigger source of current command sequence granted by arbitrator.*/ diff --git a/ext/hal/nxp/mcux/drivers/imx/fsl_flexspi_nor_boot.c b/ext/hal/nxp/mcux/drivers/imx/fsl_flexspi_nor_boot.c new file mode 100644 index 00000000000..41b273f70b4 --- /dev/null +++ b/ext/hal/nxp/mcux/drivers/imx/fsl_flexspi_nor_boot.c @@ -0,0 +1,51 @@ +/* + * Copyright 2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_flexspi_nor_boot.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.xip_device" +#endif + +#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1) +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__) + __attribute__((section(".boot_hdr.ivt"))) +#elif defined(__ICCARM__) +#pragma location=".boot_hdr.ivt" +#endif +/************************************* + * IVT Data + *************************************/ +const ivt image_vector_table = { + IVT_HEADER, /* IVT Header */ + IMAGE_ENTRY_ADDRESS, /* Image Entry Function */ + IVT_RSVD, /* Reserved = 0 */ + (uint32_t)DCD_ADDRESS, /* Address where DCD information is stored */ + (uint32_t)BOOT_DATA_ADDRESS, /* Address where BOOT Data Structure is stored */ + (uint32_t)&image_vector_table, /* Pointer to IVT Self (absolute address */ + (uint32_t)CSF_ADDRESS, /* Address where CSF file is stored */ + IVT_RSVD /* Reserved = 0 */ +}; + +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__) + __attribute__((section(".boot_hdr.boot_data"))) +#elif defined(__ICCARM__) +#pragma location=".boot_hdr.boot_data" +#endif +/************************************* + * Boot Data + *************************************/ +const BOOT_DATA_T boot_data = { + FLASH_BASE, /* boot start location */ + FLASH_SIZE, /* size */ + PLUGIN_FLAG, /* Plugin flag*/ + 0xFFFFFFFF /* empty - extra data word */ +}; +#endif + + diff --git a/ext/hal/nxp/mcux/drivers/imx/fsl_flexspi_nor_boot.h b/ext/hal/nxp/mcux/drivers/imx/fsl_flexspi_nor_boot.h new file mode 100644 index 00000000000..b95411fd83f --- /dev/null +++ b/ext/hal/nxp/mcux/drivers/imx/fsl_flexspi_nor_boot.h @@ -0,0 +1,111 @@ +/* + * Copyright 2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __FLEXSPI_NOR_BOOT_H__ +#define __FLEXSPI_NOR_BOOT_H__ + +#include +#include "board.h" + +/*! @name Driver version */ +/*@{*/ +/*! @brief XIP_DEVICE driver version 2.0.0. */ +#define FSL_XIP_DEVICE_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) +/*@}*/ + +/************************************* + * IVT Data + *************************************/ +typedef struct _ivt_ { + /** @ref hdr with tag #HAB_TAG_IVT, length and HAB version fields + * (see @ref data) + */ + uint32_t hdr; + /** Absolute address of the first instruction to execute from the + * image + */ + uint32_t entry; + /** Reserved in this version of HAB: should be NULL. */ + uint32_t reserved1; + /** Absolute address of the image DCD: may be NULL. */ + uint32_t dcd; + /** Absolute address of the Boot Data: may be NULL, but not interpreted + * any further by HAB + */ + uint32_t boot_data; + /** Absolute address of the IVT.*/ + uint32_t self; + /** Absolute address of the image CSF.*/ + uint32_t csf; + /** Reserved in this version of HAB: should be zero. */ + uint32_t reserved2; +} ivt; + +#define IVT_MAJOR_VERSION 0x4 +#define IVT_MAJOR_VERSION_SHIFT 0x4 +#define IVT_MAJOR_VERSION_MASK 0xF +#define IVT_MINOR_VERSION 0x1 +#define IVT_MINOR_VERSION_SHIFT 0x0 +#define IVT_MINOR_VERSION_MASK 0xF + +#define IVT_VERSION(major, minor) \ + ((((major) & IVT_MAJOR_VERSION_MASK) << IVT_MAJOR_VERSION_SHIFT) | \ + (((minor) & IVT_MINOR_VERSION_MASK) << IVT_MINOR_VERSION_SHIFT)) + +/* IVT header */ +#define IVT_TAG_HEADER 0xD1 /**< Image Vector Table */ +#define IVT_SIZE 0x2000 +#define IVT_PAR IVT_VERSION(IVT_MAJOR_VERSION, IVT_MINOR_VERSION) +#define IVT_HEADER (IVT_TAG_HEADER | (IVT_SIZE << 8) | (IVT_PAR << 24)) + +/* Set resume entry */ +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) + extern uint32_t __Vectors[]; + extern uint32_t Image$$RW_m_config_text$$Base[]; +#define IMAGE_ENTRY_ADDRESS ((uint32_t)__Vectors) +#define FLASH_BASE ((uint32_t)Image$$RW_m_config_text$$Base) +#elif defined(__MCUXPRESSO) + extern uint32_t __Vectors[]; + extern uint32_t __boot_hdr_start__[]; +#define IMAGE_ENTRY_ADDRESS ((uint32_t)__Vectors) +#define FLASH_BASE ((uint32_t)__boot_hdr_start__) +#elif defined(__ICCARM__) + extern uint32_t __VECTOR_TABLE[]; + extern uint32_t m_boot_hdr_conf_start[]; +#define IMAGE_ENTRY_ADDRESS ((uint32_t)__VECTOR_TABLE) +#define FLASH_BASE ((uint32_t)m_boot_hdr_conf_start) +#elif defined(__GNUC__) + extern uint32_t __VECTOR_TABLE[]; + extern uint32_t __FLASH_BASE[]; +#define IMAGE_ENTRY_ADDRESS ((uint32_t)__VECTOR_TABLE) +#define FLASH_BASE ((uint32_t)__FLASH_BASE) +#endif + +#define DCD_ADDRESS dcd_data +#define BOOT_DATA_ADDRESS &boot_data +#define CSF_ADDRESS 0 +#define IVT_RSVD (uint32_t)(0x00000000) + +/************************************* + * Boot Data + *************************************/ +typedef struct _boot_data_ { + uint32_t start; /* boot start location */ + uint32_t size; /* size */ + uint32_t plugin; /* plugin flag - 1 if downloaded application is plugin */ + uint32_t placeholder; /* placehoder to make even 0x10 size */ +}BOOT_DATA_T; + +#define FLASH_SIZE BOARD_FLASH_SIZE +#define PLUGIN_FLAG (uint32_t)0 + +/* External Variables */ +const BOOT_DATA_T boot_data; +extern const uint8_t dcd_data[]; + +#endif /* __FLEXSPI_NOR_BOOT_H__ */ + diff --git a/ext/hal/nxp/mcux/drivers/imx/fsl_gpc.c b/ext/hal/nxp/mcux/drivers/imx/fsl_gpc.c index 60a80214fd9..9569ce26bcb 100644 --- a/ext/hal/nxp/mcux/drivers/imx/fsl_gpc.c +++ b/ext/hal/nxp/mcux/drivers/imx/fsl_gpc.c @@ -3,7 +3,7 @@ * Copyright 2016 NXP * All rights reserved. * - * + * * SPDX-License-Identifier: BSD-3-Clause */ @@ -14,7 +14,12 @@ #define FSL_COMPONENT_ID "platform.drivers.gpc_1" #endif - +/*! + * brief Enable the IRQ. + * + * param base GPC peripheral base address. + * param irqId ID number of IRQ to be enabled, available range is 32-159. + */ void GPC_EnableIRQ(GPC_Type *base, uint32_t irqId) { uint32_t irqRegNum = irqId / 32U; @@ -37,6 +42,12 @@ void GPC_EnableIRQ(GPC_Type *base, uint32_t irqId) #endif /* FSL_FEATURE_GPC_HAS_IRQ_0_31 */ } +/*! + * brief Disable the IRQ. + * + * param base GPC peripheral base address. + * param irqId ID number of IRQ to be disabled, available range is 32-159. + */ void GPC_DisableIRQ(GPC_Type *base, uint32_t irqId) { uint32_t irqRegNum = irqId / 32U; @@ -59,6 +70,13 @@ void GPC_DisableIRQ(GPC_Type *base, uint32_t irqId) #endif /* FSL_FEATURE_GPC_HAS_IRQ_0_31 */ } +/*! + * brief Get the IRQ/Event flag. + * + * param base GPC peripheral base address. + * param irqId ID number of IRQ to be enabled, available range is 32-159. + * return Indicated IRQ/Event is asserted or not. + */ bool GPC_GetIRQStatusFlag(GPC_Type *base, uint32_t irqId) { uint32_t irqRegNum = irqId / 32U; diff --git a/ext/hal/nxp/mcux/drivers/imx/fsl_gpio.c b/ext/hal/nxp/mcux/drivers/imx/fsl_gpio.c index 1ea944e871d..959f926c707 100644 --- a/ext/hal/nxp/mcux/drivers/imx/fsl_gpio.c +++ b/ext/hal/nxp/mcux/drivers/imx/fsl_gpio.c @@ -13,7 +13,6 @@ #define FSL_COMPONENT_ID "platform.drivers.igpio" #endif - /******************************************************************************* * Variables ******************************************************************************/ @@ -60,6 +59,15 @@ static uint32_t GPIO_GetInstance(GPIO_Type *base) return instance; } +/*! + * brief Initializes the GPIO peripheral according to the specified + * parameters in the initConfig. + * + * param base GPIO base pointer. + * param pin Specifies the pin number + * param initConfig pointer to a ref gpio_pin_config_t structure that + * contains the configuration information. + */ void GPIO_PinInit(GPIO_Type *base, uint32_t pin, const gpio_pin_config_t *Config) { #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) @@ -85,6 +93,15 @@ void GPIO_PinInit(GPIO_Type *base, uint32_t pin, const gpio_pin_config_t *Config GPIO_SetPinInterruptConfig(base, pin, Config->interruptMode); } +/*! + * brief Sets the output level of the individual GPIO pin to logic 1 or 0. + * + * param base GPIO base pointer. + * param pin GPIO port pin number. + * param output GPIOpin output logic level. + * - 0: corresponding pin output low-logic level. + * - 1: corresponding pin output high-logic level. + */ void GPIO_PinWrite(GPIO_Type *base, uint32_t pin, uint8_t output) { assert(pin < 32); @@ -98,6 +115,14 @@ void GPIO_PinWrite(GPIO_Type *base, uint32_t pin, uint8_t output) } } +/*! + * brief Sets the current pin interrupt mode. + * + * param base GPIO base pointer. + * param pin GPIO port pin number. + * param pininterruptMode pointer to a ref gpio_interrupt_mode_t structure + * that contains the interrupt mode information. + */ void GPIO_PinSetInterruptConfig(GPIO_Type *base, uint32_t pin, gpio_interrupt_mode_t pinInterruptMode) { volatile uint32_t *icr; diff --git a/ext/hal/nxp/mcux/drivers/imx/fsl_gpt.c b/ext/hal/nxp/mcux/drivers/imx/fsl_gpt.c index 234f6688379..57b13c42ee2 100644 --- a/ext/hal/nxp/mcux/drivers/imx/fsl_gpt.c +++ b/ext/hal/nxp/mcux/drivers/imx/fsl_gpt.c @@ -2,7 +2,7 @@ * Copyright (c) 2015, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP * All rights reserved. - * + * * SPDX-License-Identifier: BSD-3-Clause */ @@ -13,7 +13,6 @@ #define FSL_COMPONENT_ID "platform.drivers.gpt" #endif - /******************************************************************************* * Prototypes ******************************************************************************/ @@ -50,6 +49,12 @@ static uint32_t GPT_GetInstance(GPT_Type *base) return instance; } +/*! + * brief Initialize GPT to reset state and initialize running mode. + * + * param base GPT peripheral base address. + * param initConfig GPT mode setting configuration. + */ void GPT_Init(GPT_Type *base, const gpt_config_t *initConfig) { assert(initConfig); @@ -72,6 +77,11 @@ void GPT_Init(GPT_Type *base, const gpt_config_t *initConfig) GPT_SetClockDivider(base, initConfig->divider); } +/*! + * brief Disables the module and gates the GPT clock. + * + * param base GPT peripheral base address. + */ void GPT_Deinit(GPT_Type *base) { /* Disable GPT timers */ @@ -83,10 +93,29 @@ void GPT_Deinit(GPT_Type *base) #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ } +/*! + * brief Fills in the GPT configuration structure with default settings. + * + * The default values are: + * code + * config->clockSource = kGPT_ClockSource_Periph; + * config->divider = 1U; + * config->enableRunInStop = true; + * config->enableRunInWait = true; + * config->enableRunInDoze = false; + * config->enableRunInDbg = false; + * config->enableFreeRun = true; + * config->enableMode = true; + * endcode + * param config Pointer to the user configuration structure. + */ void GPT_GetDefaultConfig(gpt_config_t *config) { assert(config); + /* Initializes the configure structure to zero. */ + memset(config, 0, sizeof(*config)); + config->clockSource = kGPT_ClockSource_Periph; config->divider = 1U; config->enableRunInStop = true; diff --git a/ext/hal/nxp/mcux/drivers/imx/fsl_kpp.c b/ext/hal/nxp/mcux/drivers/imx/fsl_kpp.c index 9abdd4ced70..7c6470e9e9c 100644 --- a/ext/hal/nxp/mcux/drivers/imx/fsl_kpp.c +++ b/ext/hal/nxp/mcux/drivers/imx/fsl_kpp.c @@ -1,7 +1,7 @@ /* * Copyright 2017 NXP * All rights reserved. - * + * * SPDX-License-Identifier: BSD-3-Clause */ @@ -63,6 +63,14 @@ static void KPP_Mdelay(uint64_t tickets) } } +/*! + * brief KPP initialize. + * This function ungates the KPP clock and initializes KPP. + * This function must be called before calling any other KPP driver functions. + * + * param base KPP peripheral base address. + * param configure The KPP configuration structure pointer. + */ void KPP_Init(KPP_Type *base, kpp_config_t *configure) { assert(configure); @@ -79,15 +87,14 @@ void KPP_Init(KPP_Type *base, kpp_config_t *configure) /* Enable the keypad row and set the column strobe output to open drain. */ base->KPCR = KPP_KPCR_KRE(configure->activeRow); - base->KPDR = KPP_KPDR_KCD((uint8_t)~(configure->activeColumn)); + base->KPDR = KPP_KPDR_KCD((uint8_t) ~(configure->activeColumn)); base->KPCR |= KPP_KPCR_KCO(configure->activeColumn); /* Set the input direction for row and output direction for column. */ - base->KDDR = KPP_KDDR_KCDD(configure->activeColumn) | KPP_KDDR_KRDD((uint8_t)~(configure->activeRow)); + base->KDDR = KPP_KDDR_KCDD(configure->activeColumn) | KPP_KDDR_KRDD((uint8_t) ~(configure->activeRow)); /* Clear the status flag and enable the interrupt. */ - base->KPSR = - KPP_KPSR_KPKR_MASK | KPP_KPSR_KPKD_MASK | KPP_KPSR_KDSC_MASK | configure->interrupt; + base->KPSR = KPP_KPSR_KPKR_MASK | KPP_KPSR_KPKD_MASK | KPP_KPSR_KDSC_MASK | configure->interrupt; if (configure->interrupt) { @@ -96,6 +103,13 @@ void KPP_Init(KPP_Type *base, kpp_config_t *configure) } } +/*! + * brief Deinitializes the KPP module and gates the clock. + * This function gates the KPP clock. As a result, the KPP + * module doesn't work after calling this function. + * + * param base KPP peripheral base address. + */ void KPP_Deinit(KPP_Type *base) { /* Disable interrupts and disable all rows. */ @@ -108,6 +122,18 @@ void KPP_Deinit(KPP_Type *base) #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ } +/*! + * brief Keypad press scanning. + * + * This function will scanning all columns and rows. so + * all scanning data will be stored in the data pointer. + * + * param base KPP peripheral base address. + * param data KPP key press scanning data. The data buffer should be prepared with + * length at least equal to KPP_KEYPAD_COLUMNNUM_MAX * KPP_KEYPAD_ROWNUM_MAX. + * the data pointer is recommended to be a array like uint8_t data[KPP_KEYPAD_COLUMNNUM_MAX]. + * for example the data[2] = 4, that means in column 1 row 2 has a key press event. + */ void KPP_keyPressScanning(KPP_Type *base, uint8_t *data, uint32_t clockSrc_Hz) { assert(data); @@ -152,7 +178,7 @@ void KPP_keyPressScanning(KPP_Type *base, uint8_t *data, uint32_t clockSrc_Hz) } } } - + /* Return all columns to 0 in preparation for standby mode. */ base->KPDR &= ~KPP_KPDR_KCD_MASK; diff --git a/ext/hal/nxp/mcux/drivers/imx/fsl_lpi2c.c b/ext/hal/nxp/mcux/drivers/imx/fsl_lpi2c.c index aa90a4152af..27c80eb4988 100644 --- a/ext/hal/nxp/mcux/drivers/imx/fsl_lpi2c.c +++ b/ext/hal/nxp/mcux/drivers/imx/fsl_lpi2c.c @@ -213,6 +213,7 @@ static uint32_t LPI2C_GetCyclesForWidth(uint32_t sourceClock_Hz, * @retval #kStatus_LPI2C_Nak * @retval #kStatus_LPI2C_FifoError */ +/* Not static so it can be used from fsl_lpi2c_edma.c. */ status_t LPI2C_MasterCheckAndClearError(LPI2C_Type *base, uint32_t status) { status_t result = kStatus_Success; @@ -310,6 +311,7 @@ static status_t LPI2C_MasterWaitForTxReady(LPI2C_Type *base) * @retval #kStatus_Success * @retval #kStatus_LPI2C_Busy */ +/* Not static so it can be used from fsl_lpi2c_edma.c. */ status_t LPI2C_CheckForBusyBus(LPI2C_Type *base) { uint32_t status = LPI2C_MasterGetStatusFlags(base); @@ -321,8 +323,35 @@ status_t LPI2C_CheckForBusyBus(LPI2C_Type *base) return kStatus_Success; } +/*! + * brief Provides a default configuration for the LPI2C master peripheral. + * + * This function provides the following default configuration for the LPI2C master peripheral: + * code + * masterConfig->enableMaster = true; + * masterConfig->debugEnable = false; + * masterConfig->ignoreAck = false; + * masterConfig->pinConfig = kLPI2C_2PinOpenDrain; + * masterConfig->baudRate_Hz = 100000U; + * masterConfig->busIdleTimeout_ns = 0; + * masterConfig->pinLowTimeout_ns = 0; + * masterConfig->sdaGlitchFilterWidth_ns = 0; + * masterConfig->sclGlitchFilterWidth_ns = 0; + * masterConfig->hostRequest.enable = false; + * masterConfig->hostRequest.source = kLPI2C_HostRequestExternalPin; + * masterConfig->hostRequest.polarity = kLPI2C_HostRequestPinActiveHigh; + * endcode + * + * After calling this function, you can override any settings in order to customize the configuration, + * prior to initializing the master driver with LPI2C_MasterInit(). + * + * param[out] masterConfig User provided configuration structure for default values. Refer to #lpi2c_master_config_t. + */ void LPI2C_MasterGetDefaultConfig(lpi2c_master_config_t *masterConfig) { + /* Initializes the configure structure to zero. */ + memset(masterConfig, 0, sizeof(*masterConfig)); + masterConfig->enableMaster = true; masterConfig->debugEnable = false; masterConfig->enableDoze = true; @@ -338,6 +367,19 @@ void LPI2C_MasterGetDefaultConfig(lpi2c_master_config_t *masterConfig) masterConfig->hostRequest.polarity = kLPI2C_HostRequestPinActiveHigh; } +/*! + * brief Initializes the LPI2C master peripheral. + * + * This function enables the peripheral clock and initializes the LPI2C master peripheral as described by the user + * provided configuration. A software reset is performed prior to configuration. + * + * param base The LPI2C peripheral base address. + * param masterConfig User provided peripheral configuration. Use LPI2C_MasterGetDefaultConfig() to get a set of + * defaults + * that you can override. + * param sourceClock_Hz Frequency in Hertz of the LPI2C functional clock. Used to calculate the baud rate divisors, + * filter widths, and timeout periods. + */ void LPI2C_MasterInit(LPI2C_Type *base, const lpi2c_master_config_t *masterConfig, uint32_t sourceClock_Hz) { uint32_t prescaler; @@ -418,6 +460,14 @@ void LPI2C_MasterInit(LPI2C_Type *base, const lpi2c_master_config_t *masterConfi LPI2C_MasterEnable(base, masterConfig->enableMaster); } +/*! +* brief Deinitializes the LPI2C master peripheral. +* + * This function disables the LPI2C master peripheral and gates the clock. It also performs a software + * reset to restore the peripheral to reset conditions. + * + * param base The LPI2C peripheral base address. + */ void LPI2C_MasterDeinit(LPI2C_Type *base) { /* Restore to reset state. */ @@ -437,6 +487,12 @@ void LPI2C_MasterDeinit(LPI2C_Type *base) #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ } +/*! + * brief Configures LPI2C master data match feature. + * + * param base The LPI2C peripheral base address. + * param config Settings for the data match feature. + */ void LPI2C_MasterConfigureDataMatch(LPI2C_Type *base, const lpi2c_data_match_config_t *config) { /* Disable master mode. */ @@ -454,6 +510,20 @@ void LPI2C_MasterConfigureDataMatch(LPI2C_Type *base, const lpi2c_data_match_con } } +/*! + * brief Sets the I2C bus frequency for master transactions. + * + * The LPI2C master is automatically disabled and re-enabled as necessary to configure the baud + * rate. Do not call this function during a transfer, or the transfer is aborted. + * + * note Please note that the second parameter is the clock frequency of LPI2C module, the third + * parameter means user configured bus baudrate, this implementation is different from other I2C drivers + * which use baudrate configuration as second parameter and source clock frequency as third parameter. + * + * param base The LPI2C peripheral base address. + * param sourceClock_Hz LPI2C functional clock frequency in Hertz. + * param baudRate_Hz Requested bus frequency in Hertz. + */ void LPI2C_MasterSetBaudRate(LPI2C_Type *base, uint32_t sourceClock_Hz, uint32_t baudRate_Hz) { uint32_t prescale = 0; @@ -534,6 +604,21 @@ void LPI2C_MasterSetBaudRate(LPI2C_Type *base, uint32_t sourceClock_Hz, uint32_t } } +/*! + * brief Sends a START signal and slave address on the I2C bus. + * + * This function is used to initiate a new master mode transfer. First, the bus state is checked to ensure + * that another master is not occupying the bus. Then a START signal is transmitted, followed by the + * 7-bit address specified in the a address parameter. Note that this function does not actually wait + * until the START and address are successfully sent on the bus before returning. + * + * param base The LPI2C peripheral base address. + * param address 7-bit slave device address, in bits [6:0]. + * param dir Master transfer direction, either #kLPI2C_Read or #kLPI2C_Write. This parameter is used to set + * the R/w bit (bit 0) in the transmitted slave address. + * retval #kStatus_Success START signal and address were successfully enqueued in the transmit FIFO. + * retval #kStatus_LPI2C_Busy Another master is currently utilizing the bus. + */ status_t LPI2C_MasterStart(LPI2C_Type *base, uint8_t address, lpi2c_direction_t dir) { /* Return an error if the bus is already in use not by us. */ @@ -562,6 +647,19 @@ status_t LPI2C_MasterStart(LPI2C_Type *base, uint8_t address, lpi2c_direction_t return kStatus_Success; } +/*! + * brief Sends a STOP signal on the I2C bus. + * + * This function does not return until the STOP signal is seen on the bus, or an error occurs. + * + * param base The LPI2C peripheral base address. + * retval #kStatus_Success The STOP signal was successfully sent on the bus and the transaction terminated. + * retval #kStatus_LPI2C_Busy Another master is currently utilizing the bus. + * retval #kStatus_LPI2C_Nak The slave device sent a NAK in response to a byte. + * retval #kStatus_LPI2C_FifoError FIFO under run or overrun. + * retval #kStatus_LPI2C_ArbitrationLost Arbitration lost error. + * retval #kStatus_LPI2C_PinLowTimeout SCL or SDA were held low longer than the timeout. + */ status_t LPI2C_MasterStop(LPI2C_Type *base) { /* Wait until there is room in the fifo. */ @@ -609,6 +707,19 @@ status_t LPI2C_MasterStop(LPI2C_Type *base) return result; } +/*! + * brief Performs a polling receive transfer on the I2C bus. + * + * param base The LPI2C peripheral base address. + * param rxBuff The pointer to the data to be transferred. + * param rxSize The length in bytes of the data to be transferred. + * retval #kStatus_Success Data was received successfully. + * retval #kStatus_LPI2C_Busy Another master is currently utilizing the bus. + * retval #kStatus_LPI2C_Nak The slave device sent a NAK in response to a byte. + * retval #kStatus_LPI2C_FifoError FIFO under run or overrun. + * retval #kStatus_LPI2C_ArbitrationLost Arbitration lost error. + * retval #kStatus_LPI2C_PinLowTimeout SCL or SDA were held low longer than the timeout. + */ status_t LPI2C_MasterReceive(LPI2C_Type *base, void *rxBuff, size_t rxSize) { status_t result; @@ -670,9 +781,26 @@ status_t LPI2C_MasterReceive(LPI2C_Type *base, void *rxBuff, size_t rxSize) return kStatus_Success; } -status_t LPI2C_MasterSend(LPI2C_Type *base, const void *txBuff, size_t txSize) +/*! + * brief Performs a polling send transfer on the I2C bus. + * + * Sends up to a txSize number of bytes to the previously addressed slave device. The slave may + * reply with a NAK to any byte in order to terminate the transfer early. If this happens, this + * function returns #kStatus_LPI2C_Nak. + * + * param base The LPI2C peripheral base address. + * param txBuff The pointer to the data to be transferred. + * param txSize The length in bytes of the data to be transferred. + * retval #kStatus_Success Data was sent successfully. + * retval #kStatus_LPI2C_Busy Another master is currently utilizing the bus. + * retval #kStatus_LPI2C_Nak The slave device sent a NAK in response to a byte. + * retval #kStatus_LPI2C_FifoError FIFO under run or over run. + * retval #kStatus_LPI2C_ArbitrationLost Arbitration lost error. + * retval #kStatus_LPI2C_PinLowTimeout SCL or SDA were held low longer than the timeout. + */ +status_t LPI2C_MasterSend(LPI2C_Type *base, void *txBuff, size_t txSize) { - const uint8_t *buf = (const uint8_t *)((const void *)txBuff); + uint8_t *buf = (uint8_t *)txBuff; assert(txBuff); @@ -693,6 +821,21 @@ status_t LPI2C_MasterSend(LPI2C_Type *base, const void *txBuff, size_t txSize) return kStatus_Success; } +/*! + * brief Performs a master polling transfer on the I2C bus. + * + * note The API does not return until the transfer succeeds or fails due + * to error happens during transfer. + * + * param base The LPI2C peripheral base address. + * param transfer Pointer to the transfer structure. + * retval #kStatus_Success Data was received successfully. + * retval #kStatus_LPI2C_Busy Another master is currently utilizing the bus. + * retval #kStatus_LPI2C_Nak The slave device sent a NAK in response to a byte. + * retval #kStatus_LPI2C_FifoError FIFO under run or overrun. + * retval #kStatus_LPI2C_ArbitrationLost Arbitration lost error. + * retval #kStatus_LPI2C_PinLowTimeout SCL or SDA were held low longer than the timeout. + */ status_t LPI2C_MasterTransferBlocking(LPI2C_Type *base, lpi2c_master_transfer_t *transfer) { status_t result = kStatus_Success; @@ -787,6 +930,23 @@ status_t LPI2C_MasterTransferBlocking(LPI2C_Type *base, lpi2c_master_transfer_t return result; } +/*! + * brief Creates a new handle for the LPI2C master non-blocking APIs. + * + * The creation of a handle is for use with the non-blocking APIs. Once a handle + * is created, there is not a corresponding destroy handle. If the user wants to + * terminate a transfer, the LPI2C_MasterTransferAbort() API shall be called. + * + * + * note The function also enables the NVIC IRQ for the input LPI2C. Need to notice + * that on some SoCs the LPI2C IRQ is connected to INTMUX, in this case user needs to + * enable the associated INTMUX IRQ in application. + * + * param base The LPI2C peripheral base address. + * param[out] handle Pointer to the LPI2C master driver handle. + * param callback User provided pointer to the asynchronous callback function. + * param userData User provided pointer to the application callback data. + */ void LPI2C_MasterTransferCreateHandle(LPI2C_Type *base, lpi2c_master_handle_t *handle, lpi2c_master_transfer_callback_t callback, @@ -1064,6 +1224,16 @@ static void LPI2C_InitTransferStateMachine(lpi2c_master_handle_t *handle) } } +/*! + * brief Performs a non-blocking transaction on the I2C bus. + * + * param base The LPI2C peripheral base address. + * param handle Pointer to the LPI2C master driver handle. + * param transfer The pointer to the transfer descriptor. + * retval #kStatus_Success The transaction was started successfully. + * retval #kStatus_LPI2C_Busy Either another master is currently utilizing the bus, or a non-blocking + * transaction is already in progress. + */ status_t LPI2C_MasterTransferNonBlocking(LPI2C_Type *base, lpi2c_master_handle_t *handle, lpi2c_master_transfer_t *transfer) @@ -1108,6 +1278,14 @@ status_t LPI2C_MasterTransferNonBlocking(LPI2C_Type *base, return result; } +/*! + * brief Returns number of bytes transferred so far. + * param base The LPI2C peripheral base address. + * param handle Pointer to the LPI2C master driver handle. + * param[out] count Number of bytes transferred so far by the non-blocking transaction. + * retval #kStatus_Success + * retval #kStatus_NoTransferInProgress There is not a non-blocking transaction currently in progress. + */ status_t LPI2C_MasterTransferGetCount(LPI2C_Type *base, lpi2c_master_handle_t *handle, size_t *count) { assert(handle); @@ -1160,6 +1338,17 @@ status_t LPI2C_MasterTransferGetCount(LPI2C_Type *base, lpi2c_master_handle_t *h return kStatus_Success; } +/*! + * brief Terminates a non-blocking LPI2C master transmission early. + * + * note It is not safe to call this function from an IRQ handler that has a higher priority than the + * LPI2C peripheral's IRQ priority. + * + * param base The LPI2C peripheral base address. + * param handle Pointer to the LPI2C master driver handle. + * retval #kStatus_Success A transaction was successfully aborted. + * retval #kStatus_LPI2C_Idle There is not a non-blocking transaction currently in progress. + */ void LPI2C_MasterTransferAbort(LPI2C_Type *base, lpi2c_master_handle_t *handle) { if (handle->state != kIdleState) @@ -1178,6 +1367,13 @@ void LPI2C_MasterTransferAbort(LPI2C_Type *base, lpi2c_master_handle_t *handle) } } +/*! + * brief Reusable routine to handle master interrupts. + * note This function does not need to be called unless you are reimplementing the + * nonblocking API's interrupt handler routines to add special functionality. + * param base The LPI2C peripheral base address. + * param handle Pointer to the LPI2C master driver handle. + */ void LPI2C_MasterTransferHandleIRQ(LPI2C_Type *base, lpi2c_master_handle_t *handle) { bool isDone; @@ -1216,8 +1412,42 @@ void LPI2C_MasterTransferHandleIRQ(LPI2C_Type *base, lpi2c_master_handle_t *hand } } +/*! + * brief Provides a default configuration for the LPI2C slave peripheral. + * + * This function provides the following default configuration for the LPI2C slave peripheral: + * code + * slaveConfig->enableSlave = true; + * slaveConfig->address0 = 0U; + * slaveConfig->address1 = 0U; + * slaveConfig->addressMatchMode = kLPI2C_MatchAddress0; + * slaveConfig->filterDozeEnable = true; + * slaveConfig->filterEnable = true; + * slaveConfig->enableGeneralCall = false; + * slaveConfig->sclStall.enableAck = false; + * slaveConfig->sclStall.enableTx = true; + * slaveConfig->sclStall.enableRx = true; + * slaveConfig->sclStall.enableAddress = true; + * slaveConfig->ignoreAck = false; + * slaveConfig->enableReceivedAddressRead = false; + * slaveConfig->sdaGlitchFilterWidth_ns = 0; + * slaveConfig->sclGlitchFilterWidth_ns = 0; + * slaveConfig->dataValidDelay_ns = 0; + * slaveConfig->clockHoldTime_ns = 0; + * endcode + * + * After calling this function, override any settings to customize the configuration, + * prior to initializing the master driver with LPI2C_SlaveInit(). Be sure to override at least the a + * address0 member of the configuration structure with the desired slave address. + * + * param[out] slaveConfig User provided configuration structure that is set to default values. Refer to + * #lpi2c_slave_config_t. + */ void LPI2C_SlaveGetDefaultConfig(lpi2c_slave_config_t *slaveConfig) { + /* Initializes the configure structure to zero. */ + memset(slaveConfig, 0, sizeof(*slaveConfig)); + slaveConfig->enableSlave = true; slaveConfig->address0 = 0U; slaveConfig->address1 = 0U; @@ -1237,6 +1467,18 @@ void LPI2C_SlaveGetDefaultConfig(lpi2c_slave_config_t *slaveConfig) slaveConfig->clockHoldTime_ns = 0; } +/*! + * brief Initializes the LPI2C slave peripheral. + * + * This function enables the peripheral clock and initializes the LPI2C slave peripheral as described by the user + * provided configuration. + * + * param base The LPI2C peripheral base address. + * param slaveConfig User provided peripheral configuration. Use LPI2C_SlaveGetDefaultConfig() to get a set of defaults + * that you can override. + * param sourceClock_Hz Frequency in Hertz of the LPI2C functional clock. Used to calculate the filter widths, + * data valid delay, and clock hold time. + */ void LPI2C_SlaveInit(LPI2C_Type *base, const lpi2c_slave_config_t *slaveConfig, uint32_t sourceClock_Hz) { #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) @@ -1280,6 +1522,14 @@ void LPI2C_SlaveInit(LPI2C_Type *base, const lpi2c_slave_config_t *slaveConfig, LPI2C_SCR_SEN(slaveConfig->enableSlave); } +/*! +* brief Deinitializes the LPI2C slave peripheral. +* + * This function disables the LPI2C slave peripheral and gates the clock. It also performs a software + * reset to restore the peripheral to reset conditions. + * + * param base The LPI2C peripheral base address. + */ void LPI2C_SlaveDeinit(LPI2C_Type *base) { LPI2C_SlaveReset(base); @@ -1334,9 +1584,18 @@ static status_t LPI2C_SlaveCheckAndClearError(LPI2C_Type *base, uint32_t flags) return result; } -status_t LPI2C_SlaveSend(LPI2C_Type *base, const void *txBuff, size_t txSize, size_t *actualTxSize) +/*! + * brief Performs a polling send transfer on the I2C bus. + * + * param base The LPI2C peripheral base address. + * param txBuff The pointer to the data to be transferred. + * param txSize The length in bytes of the data to be transferred. + * param[out] actualTxSize + * return Error or success status returned by API. + */ +status_t LPI2C_SlaveSend(LPI2C_Type *base, void *txBuff, size_t txSize, size_t *actualTxSize) { - const uint8_t *buf = (const uint8_t *)((const void *)txBuff); + uint8_t *buf = (uint8_t *)txBuff; size_t remaining = txSize; assert(txBuff); @@ -1400,6 +1659,15 @@ status_t LPI2C_SlaveSend(LPI2C_Type *base, const void *txBuff, size_t txSize, si return kStatus_Success; } +/*! + * brief Performs a polling receive transfer on the I2C bus. + * + * param base The LPI2C peripheral base address. + * param rxBuff The pointer to the data to be transferred. + * param rxSize The length in bytes of the data to be transferred. + * param[out] actualRxSize + * return Error or success status returned by API. + */ status_t LPI2C_SlaveReceive(LPI2C_Type *base, void *rxBuff, size_t rxSize, size_t *actualRxSize) { uint8_t *buf = (uint8_t *)rxBuff; @@ -1466,6 +1734,22 @@ status_t LPI2C_SlaveReceive(LPI2C_Type *base, void *rxBuff, size_t rxSize, size_ return kStatus_Success; } +/*! + * brief Creates a new handle for the LPI2C slave non-blocking APIs. + * + * The creation of a handle is for use with the non-blocking APIs. Once a handle + * is created, there is not a corresponding destroy handle. If the user wants to + * terminate a transfer, the LPI2C_SlaveTransferAbort() API shall be called. + * + * note The function also enables the NVIC IRQ for the input LPI2C. Need to notice + * that on some SoCs the LPI2C IRQ is connected to INTMUX, in this case user needs to + * enable the associated INTMUX IRQ in application. + + * param base The LPI2C peripheral base address. + * param[out] handle Pointer to the LPI2C slave driver handle. + * param callback User provided pointer to the asynchronous callback function. + * param userData User provided pointer to the application callback data. + */ void LPI2C_SlaveTransferCreateHandle(LPI2C_Type *base, lpi2c_slave_handle_t *handle, lpi2c_slave_transfer_callback_t callback, @@ -1499,6 +1783,30 @@ void LPI2C_SlaveTransferCreateHandle(LPI2C_Type *base, base->STAR = LPI2C_STAR_TXNACK_MASK; } +/*! + * brief Starts accepting slave transfers. + * + * Call this API after calling I2C_SlaveInit() and LPI2C_SlaveTransferCreateHandle() to start processing + * transactions driven by an I2C master. The slave monitors the I2C bus and pass events to the + * callback that was passed into the call to LPI2C_SlaveTransferCreateHandle(). The callback is always invoked + * from the interrupt context. + * + * The set of events received by the callback is customizable. To do so, set the a eventMask parameter to + * the OR'd combination of #lpi2c_slave_transfer_event_t enumerators for the events you wish to receive. + * The #kLPI2C_SlaveTransmitEvent and #kLPI2C_SlaveReceiveEvent events are always enabled and do not need + * to be included in the mask. Alternatively, you can pass 0 to get a default set of only the transmit and + * receive events that are always enabled. In addition, the #kLPI2C_SlaveAllEvents constant is provided as + * a convenient way to enable all events. + * + * param base The LPI2C peripheral base address. + * param handle Pointer to #lpi2c_slave_handle_t structure which stores the transfer state. + * param eventMask Bit mask formed by OR'ing together #lpi2c_slave_transfer_event_t enumerators to specify + * which events to send to the callback. Other accepted values are 0 to get a default set of + * only the transmit and receive events, and #kLPI2C_SlaveAllEvents to enable all events. + * + * retval #kStatus_Success Slave transfers were successfully started. + * retval #kStatus_LPI2C_Busy Slave transfers have already been started on this handle. + */ status_t LPI2C_SlaveTransferNonBlocking(LPI2C_Type *base, lpi2c_slave_handle_t *handle, uint32_t eventMask) { uint32_t status; @@ -1542,6 +1850,15 @@ status_t LPI2C_SlaveTransferNonBlocking(LPI2C_Type *base, lpi2c_slave_handle_t * return kStatus_Success; } +/*! + * brief Gets the slave transfer status during a non-blocking transfer. + * param base The LPI2C peripheral base address. + * param handle Pointer to i2c_slave_handle_t structure. + * param[out] count Pointer to a value to hold the number of bytes transferred. May be NULL if the count is not + * required. + * retval #kStatus_Success + * retval #kStatus_NoTransferInProgress + */ status_t LPI2C_SlaveTransferGetCount(LPI2C_Type *base, lpi2c_slave_handle_t *handle, size_t *count) { assert(handle); @@ -1564,6 +1881,14 @@ status_t LPI2C_SlaveTransferGetCount(LPI2C_Type *base, lpi2c_slave_handle_t *han return kStatus_Success; } +/*! + * brief Aborts the slave non-blocking transfers. + * note This API could be called at any time to stop slave for handling the bus events. + * param base The LPI2C peripheral base address. + * param handle Pointer to #lpi2c_slave_handle_t structure which stores the transfer state. + * retval #kStatus_Success + * retval #kStatus_LPI2C_Idle + */ void LPI2C_SlaveTransferAbort(LPI2C_Type *base, lpi2c_slave_handle_t *handle) { assert(handle); @@ -1585,6 +1910,13 @@ void LPI2C_SlaveTransferAbort(LPI2C_Type *base, lpi2c_slave_handle_t *handle) } } +/*! + * brief Reusable routine to handle slave interrupts. + * note This function does not need to be called unless you are reimplementing the + * non blocking API's interrupt handler routines to add special functionality. + * param base The LPI2C peripheral base address. + * param handle Pointer to #lpi2c_slave_handle_t structure which stores the transfer state. + */ void LPI2C_SlaveTransferHandleIRQ(LPI2C_Type *base, lpi2c_slave_handle_t *handle) { uint32_t flags; diff --git a/ext/hal/nxp/mcux/drivers/imx/fsl_lpi2c.h b/ext/hal/nxp/mcux/drivers/imx/fsl_lpi2c.h index ac511f46b8a..8ed0e658acf 100644 --- a/ext/hal/nxp/mcux/drivers/imx/fsl_lpi2c.h +++ b/ext/hal/nxp/mcux/drivers/imx/fsl_lpi2c.h @@ -23,8 +23,8 @@ /*! @name Driver version */ /*@{*/ -/*! @brief LPI2C driver version 2.1.5. */ -#define FSL_LPI2C_DRIVER_VERSION (MAKE_VERSION(2, 1, 5)) +/*! @brief LPI2C driver version 2.1.6. */ +#define FSL_LPI2C_DRIVER_VERSION (MAKE_VERSION(2, 1, 6)) /*@}*/ /*! @brief Timeout times for waiting flag. */ @@ -771,7 +771,7 @@ static inline status_t LPI2C_MasterRepeatedStart(LPI2C_Type *base, uint8_t addre * @retval #kStatus_LPI2C_ArbitrationLost Arbitration lost error. * @retval #kStatus_LPI2C_PinLowTimeout SCL or SDA were held low longer than the timeout. */ -status_t LPI2C_MasterSend(LPI2C_Type *base, const void *txBuff, size_t txSize); +status_t LPI2C_MasterSend(LPI2C_Type *base, void *txBuff, size_t txSize); /*! * @brief Performs a polling receive transfer on the I2C bus. @@ -1156,7 +1156,7 @@ static inline uint32_t LPI2C_SlaveGetReceivedAddress(LPI2C_Type *base) * @param[out] actualTxSize * @return Error or success status returned by API. */ -status_t LPI2C_SlaveSend(LPI2C_Type *base, const void *txBuff, size_t txSize, size_t *actualTxSize); +status_t LPI2C_SlaveSend(LPI2C_Type *base, void *txBuff, size_t txSize, size_t *actualTxSize); /*! * @brief Performs a polling receive transfer on the I2C bus. diff --git a/ext/hal/nxp/mcux/drivers/imx/fsl_lpi2c_edma.c b/ext/hal/nxp/mcux/drivers/imx/fsl_lpi2c_edma.c index 431f144f364..da100d66f2b 100644 --- a/ext/hal/nxp/mcux/drivers/imx/fsl_lpi2c_edma.c +++ b/ext/hal/nxp/mcux/drivers/imx/fsl_lpi2c_edma.c @@ -87,6 +87,23 @@ static void LPI2C_MasterEDMACallback(edma_handle_t *dmaHandle, void *userData, b * Code ******************************************************************************/ +/*! + * brief Create a new handle for the LPI2C master DMA APIs. + * + * The creation of a handle is for use with the DMA APIs. Once a handle + * is created, there is not a corresponding destroy handle. If the user wants to + * terminate a transfer, the LPI2C_MasterTransferAbortEDMA() API shall be called. + * + * For devices where the LPI2C send and receive DMA requests are OR'd together, the a txDmaHandle + * parameter is ignored and may be set to NULL. + * + * param base The LPI2C peripheral base address. + * param[out] handle Pointer to the LPI2C master driver handle. + * param rxDmaHandle Handle for the eDMA receive channel. Created by the user prior to calling this function. + * param txDmaHandle Handle for the eDMA transmit channel. Created by the user prior to calling this function. + * param callback User provided pointer to the asynchronous callback function. + * param userData User provided pointer to the application callback data. + */ void LPI2C_MasterCreateEDMAHandle(LPI2C_Type *base, lpi2c_master_edma_handle_t *handle, edma_handle_t *rxDmaHandle, @@ -178,6 +195,19 @@ static uint32_t LPI2C_GenerateCommands(lpi2c_master_edma_handle_t *handle) return cmdCount; } +/*! + * brief Performs a non-blocking DMA-based transaction on the I2C bus. + * + * The callback specified when the a handle was created is invoked when the transaction has + * completed. + * + * param base The LPI2C peripheral base address. + * param handle Pointer to the LPI2C master driver handle. + * param transfer The pointer to the transfer descriptor. + * retval #kStatus_Success The transaction was started successfully. + * retval #kStatus_LPI2C_Busy Either another master is currently utilizing the bus, or another DMA + * transaction is already in progress. + */ status_t LPI2C_MasterTransferEDMA(LPI2C_Type *base, lpi2c_master_edma_handle_t *handle, lpi2c_master_transfer_t *transfer) @@ -346,6 +376,15 @@ status_t LPI2C_MasterTransferEDMA(LPI2C_Type *base, return result; } +/*! + * brief Returns number of bytes transferred so far. + * + * param base The LPI2C peripheral base address. + * param handle Pointer to the LPI2C master driver handle. + * param[out] count Number of bytes transferred so far by the non-blocking transaction. + * retval #kStatus_Success + * retval #kStatus_NoTransferInProgress There is not a DMA transaction currently in progress. + */ status_t LPI2C_MasterTransferGetCountEDMA(LPI2C_Type *base, lpi2c_master_edma_handle_t *handle, size_t *count) { assert(handle); @@ -385,6 +424,17 @@ status_t LPI2C_MasterTransferGetCountEDMA(LPI2C_Type *base, lpi2c_master_edma_ha return kStatus_Success; } +/*! + * brief Terminates a non-blocking LPI2C master transmission early. + * + * note It is not safe to call this function from an IRQ handler that has a higher priority than the + * eDMA peripheral's IRQ priority. + * + * param base The LPI2C peripheral base address. + * param handle Pointer to the LPI2C master driver handle. + * retval #kStatus_Success A transaction was successfully aborted. + * retval #kStatus_LPI2C_Idle There is not a DMA transaction currently in progress. + */ status_t LPI2C_MasterTransferAbortEDMA(LPI2C_Type *base, lpi2c_master_edma_handle_t *handle) { /* Catch when there is not an active transfer. */ diff --git a/ext/hal/nxp/mcux/drivers/imx/fsl_lpspi.c b/ext/hal/nxp/mcux/drivers/imx/fsl_lpspi.c index a1c645a4f16..fcf18473011 100644 --- a/ext/hal/nxp/mcux/drivers/imx/fsl_lpspi.c +++ b/ext/hal/nxp/mcux/drivers/imx/fsl_lpspi.c @@ -160,12 +160,29 @@ uint32_t LPSPI_GetInstance(LPSPI_Type *base) return instance; } +/*! + * brief Set up the dummy data. + * + * param base LPSPI peripheral address. + * param dummyData Data to be transferred when tx buffer is NULL. + * Note: + * This API has no effect when LPSPI in slave interrupt mode, because driver + * will set the TXMSK bit to 1 if txData is NULL, no data is loaded from transmit + * FIFO and output pin is tristated. + */ void LPSPI_SetDummyData(LPSPI_Type *base, uint8_t dummyData) { uint32_t instance = LPSPI_GetInstance(base); g_lpspiDummyData[instance] = dummyData; } +/*! + * brief Initializes the LPSPI master. + * + * param base LPSPI peripheral address. + * param masterConfig Pointer to structure lpspi_master_config_t. + * param srcClock_Hz Module source input clock in Hertz + */ void LPSPI_MasterInit(LPSPI_Type *base, const lpspi_master_config_t *masterConfig, uint32_t srcClock_Hz) { assert(masterConfig); @@ -184,9 +201,6 @@ void LPSPI_MasterInit(LPSPI_Type *base, const lpspi_master_config_t *masterConfi #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - /* Reset to known status */ - LPSPI_Reset(base); - /* Set LPSPI to master */ LPSPI_SetMasterSlaveMode(base, kLPSPI_Master); @@ -218,10 +232,26 @@ void LPSPI_MasterInit(LPSPI_Type *base, const lpspi_master_config_t *masterConfi LPSPI_SetDummyData(base, LPSPI_DUMMY_DATA); } +/*! + * brief Sets the lpspi_master_config_t structure to default values. + * + * This API initializes the configuration structure for LPSPI_MasterInit(). + * The initialized structure can remain unchanged in LPSPI_MasterInit(), or can be modified + * before calling the LPSPI_MasterInit(). + * Example: + * code + * lpspi_master_config_t masterConfig; + * LPSPI_MasterGetDefaultConfig(&masterConfig); + * endcode + * param masterConfig pointer to lpspi_master_config_t structure + */ void LPSPI_MasterGetDefaultConfig(lpspi_master_config_t *masterConfig) { assert(masterConfig); + /* Initializes the configure structure to zero. */ + memset(masterConfig, 0, sizeof(*masterConfig)); + masterConfig->baudRate = 500000; masterConfig->bitsPerFrame = 8; masterConfig->cpol = kLPSPI_ClockPolarityActiveHigh; @@ -239,6 +269,12 @@ void LPSPI_MasterGetDefaultConfig(lpspi_master_config_t *masterConfig) masterConfig->dataOutConfig = kLpspiDataOutRetained; } +/*! + * brief LPSPI slave configuration. + * + * param base LPSPI peripheral address. + * param slaveConfig Pointer to a structure lpspi_slave_config_t. + */ void LPSPI_SlaveInit(LPSPI_Type *base, const lpspi_slave_config_t *slaveConfig) { assert(slaveConfig); @@ -255,9 +291,6 @@ void LPSPI_SlaveInit(LPSPI_Type *base, const lpspi_slave_config_t *slaveConfig) #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - /* Reset to known status */ - LPSPI_Reset(base); - LPSPI_SetMasterSlaveMode(base, kLPSPI_Slave); LPSPI_SetOnePcsPolarity(base, slaveConfig->whichPcs, slaveConfig->pcsActiveHighOrLow); @@ -276,10 +309,26 @@ void LPSPI_SlaveInit(LPSPI_Type *base, const lpspi_slave_config_t *slaveConfig) LPSPI_Enable(base, true); } +/*! + * brief Sets the lpspi_slave_config_t structure to default values. + * + * This API initializes the configuration structure for LPSPI_SlaveInit(). + * The initialized structure can remain unchanged in LPSPI_SlaveInit() or can be modified + * before calling the LPSPI_SlaveInit(). + * Example: + * code + * lpspi_slave_config_t slaveConfig; + * LPSPI_SlaveGetDefaultConfig(&slaveConfig); + * endcode + * param slaveConfig pointer to lpspi_slave_config_t structure. + */ void LPSPI_SlaveGetDefaultConfig(lpspi_slave_config_t *slaveConfig) { assert(slaveConfig); + /* Initializes the configure structure to zero. */ + memset(slaveConfig, 0, sizeof(*slaveConfig)); + slaveConfig->bitsPerFrame = 8; /*!< Bits per frame, minimum 8, maximum 4096.*/ slaveConfig->cpol = kLPSPI_ClockPolarityActiveHigh; /*!< Clock polarity. */ slaveConfig->cpha = kLPSPI_ClockPhaseFirstEdge; /*!< Clock phase. */ @@ -292,6 +341,12 @@ void LPSPI_SlaveGetDefaultConfig(lpspi_slave_config_t *slaveConfig) slaveConfig->dataOutConfig = kLpspiDataOutRetained; } +/*! + * brief Restores the LPSPI peripheral to reset state. Note that this function + * sets all registers to reset state. As a result, the LPSPI module can't work after calling + * this API. + * param base LPSPI peripheral address. +*/ void LPSPI_Reset(LPSPI_Type *base) { /* Reset all internal logic and registers, except the Control Register. Remains set until cleared by software.*/ @@ -304,6 +359,10 @@ void LPSPI_Reset(LPSPI_Type *base) base->CR = 0x00U; } +/*! + * brief De-initializes the LPSPI peripheral. Call this API to disable the LPSPI clock. + * param base LPSPI peripheral address. + */ void LPSPI_Deinit(LPSPI_Type *base) { /* Reset to default value */ @@ -334,6 +393,29 @@ static void LPSPI_SetOnePcsPolarity(LPSPI_Type *base, base->CFGR1 = cfgr1Value | ((uint32_t)activeLowOrHigh << (LPSPI_CFGR1_PCSPOL_SHIFT + pcs)); } +/*! + * brief Sets the LPSPI baud rate in bits per second. + * + * This function takes in the desired bitsPerSec (baud rate) and calculates the nearest + * possible baud rate without exceeding the desired baud rate and returns the + * calculated baud rate in bits-per-second. It requires the caller to provide + * the frequency of the module source clock (in Hertz). Note that the baud rate + * does not go into effect until the Transmit Control Register (TCR) is programmed + * with the prescale value. Hence, this function returns the prescale tcrPrescaleValue + * parameter for later programming in the TCR. The higher level + * peripheral driver should alert the user of an out of range baud rate input. + * + * Note that the LPSPI module must first be disabled before configuring this. + * Note that the LPSPI module must be configured for master mode before configuring this. + * + * param base LPSPI peripheral address. + * param baudRate_Bps The desired baud rate in bits per second. + * param srcClock_Hz Module source input clock in Hertz. + * param tcrPrescaleValue The TCR prescale value needed to program the TCR. + * return The actual calculated baud rate. This function may also return a "0" if the + * LPSPI is not configured for master mode or if the LPSPI module is not disabled. + */ + uint32_t LPSPI_MasterSetBaudRate(LPSPI_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz, @@ -408,6 +490,28 @@ uint32_t LPSPI_MasterSetBaudRate(LPSPI_Type *base, return bestBaudrate; } +/*! + * brief Manually configures a specific LPSPI delay parameter (module must be disabled to + * change the delay values). + * + * This function configures the following: + * SCK to PCS delay, or + * PCS to SCK delay, or + * The configurations must occur between the transfer delay. + * + * The delay names are available in type lpspi_delay_type_t. + * + * The user passes the desired delay along with the delay value. + * This allows the user to directly set the delay values if they have + * pre-calculated them or if they simply wish to manually increment the value. + * + * Note that the LPSPI module must first be disabled before configuring this. + * Note that the LPSPI module must be configured for master mode before configuring this. + * + * param base LPSPI peripheral address. + * param scaler The 8-bit delay value 0x00 to 0xFF (255). + * param whichDelay The desired delay to configure, must be of type lpspi_delay_type_t. + */ void LPSPI_MasterSetDelayScaler(LPSPI_Type *base, uint32_t scaler, lpspi_delay_type_t whichDelay) { /*These settings are only relevant in master mode */ @@ -431,6 +535,34 @@ void LPSPI_MasterSetDelayScaler(LPSPI_Type *base, uint32_t scaler, lpspi_delay_t } } +/*! + * brief Calculates the delay based on the desired delay input in nanoseconds (module must be + * disabled to change the delay values). + * + * This function calculates the values for the following: + * SCK to PCS delay, or + * PCS to SCK delay, or + * The configurations must occur between the transfer delay. + * + * The delay names are available in type lpspi_delay_type_t. + * + * The user passes the desired delay and the desired delay value in + * nano-seconds. The function calculates the value needed for the desired delay parameter + * and returns the actual calculated delay because an exact delay match may not be possible. In this + * case, the closest match is calculated without going below the desired delay value input. + * It is possible to input a very large delay value that exceeds the capability of the part, in + * which case the maximum supported delay is returned. It is up to the higher level + * peripheral driver to alert the user of an out of range delay input. + * + * Note that the LPSPI module must be configured for master mode before configuring this. And note that + * the delayTime = LPSPI_clockSource / (PRESCALE * Delay_scaler). + * + * param base LPSPI peripheral address. + * param delayTimeInNanoSec The desired delay value in nano-seconds. + * param whichDelay The desired delay to configuration, which must be of type lpspi_delay_type_t. + * param srcClock_Hz Module source input clock in Hertz. + * return actual Calculated delay value in nano-seconds. + */ uint32_t LPSPI_MasterSetDelayTimes(LPSPI_Type *base, uint32_t delayTimeInNanoSec, lpspi_delay_type_t whichDelay, @@ -539,6 +671,17 @@ uint32_t LPSPI_MasterSetDelayTimes(LPSPI_Type *base, /*Transactional APIs -- Master*/ +/*! + * brief Initializes the LPSPI master handle. + * + * This function initializes the LPSPI handle, which can be used for other LPSPI transactional APIs. Usually, for a + * specified LPSPI instance, call this API once to get the initialized handle. + + * param base LPSPI peripheral address. + * param handle LPSPI handle pointer to lpspi_master_handle_t. + * param callback DSPI callback. + * param userData callback function parameter. + */ void LPSPI_MasterTransferCreateHandle(LPSPI_Type *base, lpspi_master_handle_t *handle, lpspi_master_transfer_callback_t callback, @@ -558,6 +701,14 @@ void LPSPI_MasterTransferCreateHandle(LPSPI_Type *base, handle->userData = userData; } +/*! +* brief Check the argument for transfer . +* +* param transfer the transfer struct to be used. +* param bitPerFrame The bit size of one frame. +* param bytePerFrame The byte size of one frame. +* return Return true for right and false for wrong. +*/ bool LPSPI_CheckTransferArgument(lpspi_transfer_t *transfer, uint32_t bitsPerFrame, uint32_t bytesPerFrame) { assert(transfer); @@ -607,6 +758,23 @@ bool LPSPI_CheckTransferArgument(lpspi_transfer_t *transfer, uint32_t bitsPerFra return true; } +/*! + * brief LPSPI master transfer data using a polling method. + * + * This function transfers data using a polling method. This is a blocking function, which does not return until all + * transfers have been + * completed. + * + * Note: + * The transfer data size should be integer multiples of bytesPerFrame if bytesPerFrame is less than or equal to 4. + * For bytesPerFrame greater than 4: + * The transfer data size should be equal to bytesPerFrame if the bytesPerFrame is not integer multiples of 4. + * Otherwise, the transfer data size can be an integer multiple of bytesPerFrame. + * + * param base LPSPI peripheral address. + * param transfer pointer to lpspi_transfer_t structure. + * return status of status_t. + */ status_t LPSPI_MasterTransferBlocking(LPSPI_Type *base, lpspi_transfer_t *transfer) { assert(transfer); @@ -771,6 +939,24 @@ status_t LPSPI_MasterTransferBlocking(LPSPI_Type *base, lpspi_transfer_t *transf return kStatus_Success; } +/*! + * brief LPSPI master transfer data using an interrupt method. + * + * This function transfers data using an interrupt method. This is a non-blocking function, which returns right away. + * When all data + * is transferred, the callback function is called. + * + * Note: + * The transfer data size should be integer multiples of bytesPerFrame if bytesPerFrame is less than or equal to 4. + * For bytesPerFrame greater than 4: + * The transfer data size should be equal to bytesPerFrame if the bytesPerFrame is not integer multiples of 4. + * Otherwise, the transfer data size can be an integer multiple of bytesPerFrame. + * + * param base LPSPI peripheral address. + * param handle pointer to lpspi_master_handle_t structure which stores the transfer state. + * param transfer pointer to lpspi_transfer_t structure. + * return status of status_t. + */ status_t LPSPI_MasterTransferNonBlocking(LPSPI_Type *base, lpspi_master_handle_t *handle, lpspi_transfer_t *transfer) { assert(handle); @@ -995,6 +1181,16 @@ static void LPSPI_MasterTransferComplete(LPSPI_Type *base, lpspi_master_handle_t } } +/*! + * brief Gets the master transfer remaining bytes. + * + * This function gets the master transfer remaining bytes. + * + * param base LPSPI peripheral address. + * param handle pointer to lpspi_master_handle_t structure which stores the transfer state. + * param count Number of bytes transferred so far by the non-blocking transaction. + * return status of status_t. + */ status_t LPSPI_MasterTransferGetCount(LPSPI_Type *base, lpspi_master_handle_t *handle, size_t *count) { assert(handle); @@ -1027,6 +1223,14 @@ status_t LPSPI_MasterTransferGetCount(LPSPI_Type *base, lpspi_master_handle_t *h return kStatus_Success; } +/*! + * brief LPSPI master abort transfer which uses an interrupt method. + * + * This function aborts a transfer which uses an interrupt method. + * + * param base LPSPI peripheral address. + * param handle pointer to lpspi_master_handle_t structure which stores the transfer state. + */ void LPSPI_MasterTransferAbort(LPSPI_Type *base, lpspi_master_handle_t *handle) { assert(handle); @@ -1041,6 +1245,14 @@ void LPSPI_MasterTransferAbort(LPSPI_Type *base, lpspi_master_handle_t *handle) handle->rxRemainingByteCount = 0; } +/*! + * brief LPSPI Master IRQ handler function. + * + * This function processes the LPSPI transmit and receive IRQ. + * + * param base LPSPI peripheral address. + * param handle pointer to lpspi_master_handle_t structure which stores the transfer state. + */ void LPSPI_MasterTransferHandleIRQ(LPSPI_Type *base, lpspi_master_handle_t *handle) { assert(handle); @@ -1139,6 +1351,17 @@ void LPSPI_MasterTransferHandleIRQ(LPSPI_Type *base, lpspi_master_handle_t *hand } /*Transactional APIs -- Slave*/ +/*! + * brief Initializes the LPSPI slave handle. + * + * This function initializes the LPSPI handle, which can be used for other LPSPI transactional APIs. Usually, for a + * specified LPSPI instance, call this API once to get the initialized handle. + * + * param base LPSPI peripheral address. + * param handle LPSPI handle pointer to lpspi_slave_handle_t. + * param callback DSPI callback. + * param userData callback function parameter. + */ void LPSPI_SlaveTransferCreateHandle(LPSPI_Type *base, lpspi_slave_handle_t *handle, lpspi_slave_transfer_callback_t callback, @@ -1158,6 +1381,24 @@ void LPSPI_SlaveTransferCreateHandle(LPSPI_Type *base, handle->userData = userData; } +/*! + * brief LPSPI slave transfer data using an interrupt method. + * + * This function transfer data using an interrupt method. This is a non-blocking function, which returns right away. + * When all data + * is transferred, the callback function is called. + * + * Note: + * The transfer data size should be integer multiples of bytesPerFrame if bytesPerFrame is less than or equal to 4. + * For bytesPerFrame greater than 4: + * The transfer data size should be equal to bytesPerFrame if the bytesPerFrame is not an integer multiple of 4. + * Otherwise, the transfer data size can be an integer multiple of bytesPerFrame. + * + * param base LPSPI peripheral address. + * param handle pointer to lpspi_slave_handle_t structure which stores the transfer state. + * param transfer pointer to lpspi_transfer_t structure. + * return status of status_t. + */ status_t LPSPI_SlaveTransferNonBlocking(LPSPI_Type *base, lpspi_slave_handle_t *handle, lpspi_transfer_t *transfer) { assert(handle); @@ -1374,6 +1615,16 @@ static void LPSPI_SlaveTransferComplete(LPSPI_Type *base, lpspi_slave_handle_t * } } +/*! + * brief Gets the slave transfer remaining bytes. + * + * This function gets the slave transfer remaining bytes. + * + * param base LPSPI peripheral address. + * param handle pointer to lpspi_slave_handle_t structure which stores the transfer state. + * param count Number of bytes transferred so far by the non-blocking transaction. + * return status of status_t. + */ status_t LPSPI_SlaveTransferGetCount(LPSPI_Type *base, lpspi_slave_handle_t *handle, size_t *count) { assert(handle); @@ -1406,6 +1657,14 @@ status_t LPSPI_SlaveTransferGetCount(LPSPI_Type *base, lpspi_slave_handle_t *han return kStatus_Success; } +/*! + * brief LPSPI slave aborts a transfer which uses an interrupt method. + * + * This function aborts a transfer which uses an interrupt method. + * + * param base LPSPI peripheral address. + * param handle pointer to lpspi_slave_handle_t structure which stores the transfer state. + */ void LPSPI_SlaveTransferAbort(LPSPI_Type *base, lpspi_slave_handle_t *handle) { assert(handle); @@ -1420,6 +1679,14 @@ void LPSPI_SlaveTransferAbort(LPSPI_Type *base, lpspi_slave_handle_t *handle) handle->rxRemainingByteCount = 0; } +/*! + * brief LPSPI Slave IRQ handler function. + * + * This function processes the LPSPI transmit and receives an IRQ. + * + * param base LPSPI peripheral address. + * param handle pointer to lpspi_slave_handle_t structure which stores the transfer state. + */ void LPSPI_SlaveTransferHandleIRQ(LPSPI_Type *base, lpspi_slave_handle_t *handle) { assert(handle); diff --git a/ext/hal/nxp/mcux/drivers/imx/fsl_lpspi.h b/ext/hal/nxp/mcux/drivers/imx/fsl_lpspi.h index 1ac59504ed6..c31d3de285d 100644 --- a/ext/hal/nxp/mcux/drivers/imx/fsl_lpspi.h +++ b/ext/hal/nxp/mcux/drivers/imx/fsl_lpspi.h @@ -21,8 +21,8 @@ /*! @name Driver version */ /*@{*/ -/*! @brief LPSPI driver version 2.0.1. */ -#define FSL_LPSPI_DRIVER_VERSION (MAKE_VERSION(2, 0, 2)) +/*! @brief LPSPI driver version 2.0.3. */ +#define FSL_LPSPI_DRIVER_VERSION (MAKE_VERSION(2, 0, 3)) /*@}*/ #ifndef LPSPI_DUMMY_DATA @@ -204,17 +204,17 @@ enum _lpspi_transfer_config_flag_for_master kLPSPI_MasterByteSwap = 1U << 22 /*!< Is master swap the byte. - * For example, when want to send data 1 2 3 4 5 6 7 8 (suppose you set - * lpspi_shift_direction_t to MSB). - * 1. If you set bitPerFrame = 8 , no matter the kLPSPI_MasterByteSwapyou flag is used - * or not, the waveform is 1 2 3 4 5 6 7 8. - * 2. If you set bitPerFrame = 16 : - * (1) the waveform is 2 1 4 3 6 5 8 7 if you do not use the kLPSPI_MasterByteSwap flag. - * (2) the waveform is 1 2 3 4 5 6 7 8 if you use the kLPSPI_MasterByteSwap flag. - * 3. If you set bitPerFrame = 32 : - * (1) the waveform is 4 3 2 1 8 7 6 5 if you do not use the kLPSPI_MasterByteSwap flag. - * (2) the waveform is 1 2 3 4 5 6 7 8 if you use the kLPSPI_MasterByteSwap flag. - */ + * For example, when want to send data 1 2 3 4 5 6 7 8 (suppose you set + * lpspi_shift_direction_t to MSB). + * 1. If you set bitPerFrame = 8 , no matter the kLPSPI_MasterByteSwapyou flag is used + * or not, the waveform is 1 2 3 4 5 6 7 8. + * 2. If you set bitPerFrame = 16 : + * (1) the waveform is 2 1 4 3 6 5 8 7 if you do not use the kLPSPI_MasterByteSwap flag. + * (2) the waveform is 1 2 3 4 5 6 7 8 if you use the kLPSPI_MasterByteSwap flag. + * 3. If you set bitPerFrame = 32 : + * (1) the waveform is 4 3 2 1 8 7 6 5 if you do not use the kLPSPI_MasterByteSwap flag. + * (2) the waveform is 1 2 3 4 5 6 7 8 if you use the kLPSPI_MasterByteSwap flag. + */ }; #define LPSPI_SLAVE_PCS_SHIFT (4U) /*!< LPSPI slave PCS shift macro , internal used. */ @@ -230,17 +230,17 @@ enum _lpspi_transfer_config_flag_for_slave kLPSPI_SlaveByteSwap = 1U << 22 /*!< Is slave swap the byte. - * For example, when want to send data 1 2 3 4 5 6 7 8 (suppose you set - * lpspi_shift_direction_t to MSB). - * 1. If you set bitPerFrame = 8 , no matter the kLPSPI_SlaveByteSwap flag is used - * or not, the waveform is 1 2 3 4 5 6 7 8. - * 2. If you set bitPerFrame = 16 : - * (1) the waveform is 2 1 4 3 6 5 8 7 if you do not use the kLPSPI_SlaveByteSwap flag. - * (2) the waveform is 1 2 3 4 5 6 7 8 if you use the kLPSPI_SlaveByteSwap flag. - * 3. If you set bitPerFrame = 32 : - * (1) the waveform is 4 3 2 1 8 7 6 5 if you do not use the kLPSPI_SlaveByteSwap flag. - * (2) the waveform is 1 2 3 4 5 6 7 8 if you use the kLPSPI_SlaveByteSwap flag. - */ + * For example, when want to send data 1 2 3 4 5 6 7 8 (suppose you set + * lpspi_shift_direction_t to MSB). + * 1. If you set bitPerFrame = 8 , no matter the kLPSPI_SlaveByteSwap flag is used + * or not, the waveform is 1 2 3 4 5 6 7 8. + * 2. If you set bitPerFrame = 16 : + * (1) the waveform is 2 1 4 3 6 5 8 7 if you do not use the kLPSPI_SlaveByteSwap flag. + * (2) the waveform is 1 2 3 4 5 6 7 8 if you use the kLPSPI_SlaveByteSwap flag. + * 3. If you set bitPerFrame = 32 : + * (1) the waveform is 4 3 2 1 8 7 6 5 if you do not use the kLPSPI_SlaveByteSwap flag. + * (2) the waveform is 1 2 3 4 5 6 7 8 if you use the kLPSPI_SlaveByteSwap flag. + */ }; /*! @brief LPSPI transfer state, which is used for LPSPI transactional API state machine. */ diff --git a/ext/hal/nxp/mcux/drivers/imx/fsl_lpspi_edma.c b/ext/hal/nxp/mcux/drivers/imx/fsl_lpspi_edma.c index 2a2616a75ff..effca2527ce 100644 --- a/ext/hal/nxp/mcux/drivers/imx/fsl_lpspi_edma.c +++ b/ext/hal/nxp/mcux/drivers/imx/fsl_lpspi_edma.c @@ -154,6 +154,25 @@ static void LPSPI_SeparateEdmaReadData(uint8_t *rxData, uint32_t readData, uint3 } } +/*! + * brief Initializes the LPSPI master eDMA handle. + * + * This function initializes the LPSPI eDMA handle which can be used for other LPSPI transactional APIs. Usually, for a + * specified LPSPI instance, call this API once to get the initialized handle. + * + * Note that the LPSPI eDMA has a separated (Rx and Rx as two sources) or shared (Rx and Tx are the same source) DMA + * request source. + * (1) For a separated DMA request source, enable and set the Rx DMAMUX source for edmaRxRegToRxDataHandle and + * Tx DMAMUX source for edmaIntermediaryToTxRegHandle. + * (2) For a shared DMA request source, enable and set the Rx/Rx DMAMUX source for edmaRxRegToRxDataHandle. + * + * param base LPSPI peripheral base address. + * param handle LPSPI handle pointer to lpspi_master_edma_handle_t. + * param callback LPSPI callback. + * param userData callback function parameter. + * param edmaRxRegToRxDataHandle edmaRxRegToRxDataHandle pointer to edma_handle_t. + * param edmaTxDataToTxRegHandle edmaTxDataToTxRegHandle pointer to edma_handle_t. + */ void LPSPI_MasterTransferCreateHandleEDMA(LPSPI_Type *base, lpspi_master_edma_handle_t *handle, lpspi_master_edma_transfer_callback_t callback, @@ -180,6 +199,23 @@ void LPSPI_MasterTransferCreateHandleEDMA(LPSPI_Type *base, handle->edmaTxDataToTxRegHandle = edmaTxDataToTxRegHandle; } +/*! + * brief LPSPI master transfer data using eDMA. + * + * This function transfers data using eDMA. This is a non-blocking function, which returns right away. When all data + * is transferred, the callback function is called. + * + * Note: + * The transfer data size should be an integer multiple of bytesPerFrame if bytesPerFrame is less than or equal to 4. + * For bytesPerFrame greater than 4: + * The transfer data size should be equal to bytesPerFrame if the bytesPerFrame is not an integer multiple of 4. + * Otherwise, the transfer data size can be an integer multiple of bytesPerFrame. + * + * param base LPSPI peripheral base address. + * param handle pointer to lpspi_master_edma_handle_t structure which stores the transfer state. + * param transfer pointer to lpspi_transfer_t structure. + * return status of status_t. + */ status_t LPSPI_MasterTransferEDMA(LPSPI_Type *base, lpspi_master_edma_handle_t *handle, lpspi_transfer_t *transfer) { assert(handle); @@ -583,6 +619,14 @@ static void EDMA_LpspiMasterCallback(edma_handle_t *edmaHandle, } } +/*! + * brief LPSPI master aborts a transfer which is using eDMA. + * + * This function aborts a transfer which is using eDMA. + * + * param base LPSPI peripheral base address. + * param handle pointer to lpspi_master_edma_handle_t structure which stores the transfer state. + */ void LPSPI_MasterTransferAbortEDMA(LPSPI_Type *base, lpspi_master_edma_handle_t *handle) { assert(handle); @@ -595,6 +639,16 @@ void LPSPI_MasterTransferAbortEDMA(LPSPI_Type *base, lpspi_master_edma_handle_t handle->state = kLPSPI_Idle; } +/*! + * brief Gets the master eDMA transfer remaining bytes. + * + * This function gets the master eDMA transfer remaining bytes. + * + * param base LPSPI peripheral base address. + * param handle pointer to lpspi_master_edma_handle_t structure which stores the transfer state. + * param count Number of bytes transferred so far by the EDMA transaction. + * return status of status_t. + */ status_t LPSPI_MasterTransferGetCountEDMA(LPSPI_Type *base, lpspi_master_edma_handle_t *handle, size_t *count) { assert(handle); @@ -622,6 +676,26 @@ status_t LPSPI_MasterTransferGetCountEDMA(LPSPI_Type *base, lpspi_master_edma_ha return kStatus_Success; } +/*! + * brief Initializes the LPSPI slave eDMA handle. + * + * This function initializes the LPSPI eDMA handle which can be used for other LPSPI transactional APIs. Usually, for a + * specified LPSPI instance, call this API once to get the initialized handle. + * + * Note that LPSPI eDMA has a separated (Rx and Tx as two sources) or shared (Rx and Tx as the same source) DMA request + * source. + * + * (1) For a separated DMA request source, enable and set the Rx DMAMUX source for edmaRxRegToRxDataHandle and + * Tx DMAMUX source for edmaTxDataToTxRegHandle. + * (2) For a shared DMA request source, enable and set the Rx/Rx DMAMUX source for edmaRxRegToRxDataHandle . + * + * param base LPSPI peripheral base address. + * param handle LPSPI handle pointer to lpspi_slave_edma_handle_t. + * param callback LPSPI callback. + * param userData callback function parameter. + * param edmaRxRegToRxDataHandle edmaRxRegToRxDataHandle pointer to edma_handle_t. + * param edmaTxDataToTxRegHandle edmaTxDataToTxRegHandle pointer to edma_handle_t. + */ void LPSPI_SlaveTransferCreateHandleEDMA(LPSPI_Type *base, lpspi_slave_edma_handle_t *handle, lpspi_slave_edma_transfer_callback_t callback, @@ -648,6 +722,23 @@ void LPSPI_SlaveTransferCreateHandleEDMA(LPSPI_Type *base, handle->edmaTxDataToTxRegHandle = edmaTxDataToTxRegHandle; } +/*! + * brief LPSPI slave transfers data using eDMA. + * + * This function transfers data using eDMA. This is a non-blocking function, which return right away. When all data + * is transferred, the callback function is called. + * + * Note: + * The transfer data size should be an integer multiple of bytesPerFrame if bytesPerFrame is less than or equal to 4. + * For bytesPerFrame greater than 4: + * The transfer data size should be equal to bytesPerFrame if the bytesPerFrame is not an integer multiple of 4. + * Otherwise, the transfer data size can be an integer multiple of bytesPerFrame. + * + * param base LPSPI peripheral base address. + * param handle pointer to lpspi_slave_edma_handle_t structure which stores the transfer state. + * param transfer pointer to lpspi_transfer_t structure. + * return status of status_t. + */ status_t LPSPI_SlaveTransferEDMA(LPSPI_Type *base, lpspi_slave_edma_handle_t *handle, lpspi_transfer_t *transfer) { assert(handle); @@ -1020,6 +1111,14 @@ static void EDMA_LpspiSlaveCallback(edma_handle_t *edmaHandle, } } +/*! + * brief LPSPI slave aborts a transfer which is using eDMA. + * + * This function aborts a transfer which is using eDMA. + * + * param base LPSPI peripheral base address. + * param handle pointer to lpspi_slave_edma_handle_t structure which stores the transfer state. + */ void LPSPI_SlaveTransferAbortEDMA(LPSPI_Type *base, lpspi_slave_edma_handle_t *handle) { assert(handle); @@ -1032,6 +1131,16 @@ void LPSPI_SlaveTransferAbortEDMA(LPSPI_Type *base, lpspi_slave_edma_handle_t *h handle->state = kLPSPI_Idle; } +/*! + * brief Gets the slave eDMA transfer remaining bytes. + * + * This function gets the slave eDMA transfer remaining bytes. + * + * param base LPSPI peripheral base address. + * param handle pointer to lpspi_slave_edma_handle_t structure which stores the transfer state. + * param count Number of bytes transferred so far by the eDMA transaction. + * return status of status_t. + */ status_t LPSPI_SlaveTransferGetCountEDMA(LPSPI_Type *base, lpspi_slave_edma_handle_t *handle, size_t *count) { assert(handle); diff --git a/ext/hal/nxp/mcux/drivers/imx/fsl_lpuart.c b/ext/hal/nxp/mcux/drivers/imx/fsl_lpuart.c index abe804c5496..76c71ea4c07 100644 --- a/ext/hal/nxp/mcux/drivers/imx/fsl_lpuart.c +++ b/ext/hal/nxp/mcux/drivers/imx/fsl_lpuart.c @@ -100,6 +100,12 @@ static lpuart_isr_t s_lpuartIsr; /******************************************************************************* * Code ******************************************************************************/ +/*! + * brief Get the LPUART instance from peripheral base address. + * + * param base LPUART peripheral base address. + * return LPUART instance. + */ uint32_t LPUART_GetInstance(LPUART_Type *base) { uint32_t instance; @@ -118,6 +124,12 @@ uint32_t LPUART_GetInstance(LPUART_Type *base) return instance; } +/*! + * brief Get the length of received data in RX ring buffer. + * + * userData handle LPUART handle pointer. + * return Length of received data in RX ring buffer. + */ size_t LPUART_TransferGetRxRingBufferLength(LPUART_Type *base, lpuart_handle_t *handle) { assert(handle); @@ -197,6 +209,30 @@ static void LPUART_ReadNonBlocking(LPUART_Type *base, uint8_t *data, size_t leng } } +/*! + * brief Initializes an LPUART instance with the user configuration structure and the peripheral clock. + * + * This function configures the LPUART module with user-defined settings. Call the LPUART_GetDefaultConfig() function + * to configure the configuration structure and get the default configuration. + * The example below shows how to use this API to configure the LPUART. + * code + * lpuart_config_t lpuartConfig; + * lpuartConfig.baudRate_Bps = 115200U; + * lpuartConfig.parityMode = kLPUART_ParityDisabled; + * lpuartConfig.dataBitsCount = kLPUART_EightDataBits; + * lpuartConfig.isMsb = false; + * lpuartConfig.stopBitCount = kLPUART_OneStopBit; + * lpuartConfig.txFifoWatermark = 0; + * lpuartConfig.rxFifoWatermark = 1; + * LPUART_Init(LPUART1, &lpuartConfig, 20000000U); + * endcode + * + * param base LPUART peripheral base address. + * param config Pointer to a user-defined configuration structure. + * param srcClock_Hz LPUART clock source frequency in HZ. + * retval kStatus_LPUART_BaudrateNotSupport Baudrate is not support in current clock source. + * retval kStatus_Success LPUART initialize succeed + */ status_t LPUART_Init(LPUART_Type *base, const lpuart_config_t *config, uint32_t srcClock_Hz) { assert(config); @@ -406,6 +442,13 @@ status_t LPUART_Init(LPUART_Type *base, const lpuart_config_t *config, uint32_t return kStatus_Success; } +/*! + * brief Deinitializes a LPUART instance. + * + * This function waits for transmit to complete, disables TX and RX, and disables the LPUART clock. + * + * param base LPUART peripheral base address. + */ void LPUART_Deinit(LPUART_Type *base) { uint32_t temp; @@ -451,10 +494,32 @@ void LPUART_Deinit(LPUART_Type *base) #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ } +/*! + * brief Gets the default configuration structure. + * + * This function initializes the LPUART configuration structure to a default value. The default + * values are: + * lpuartConfig->baudRate_Bps = 115200U; + * lpuartConfig->parityMode = kLPUART_ParityDisabled; + * lpuartConfig->dataBitsCount = kLPUART_EightDataBits; + * lpuartConfig->isMsb = false; + * lpuartConfig->stopBitCount = kLPUART_OneStopBit; + * lpuartConfig->txFifoWatermark = 0; + * lpuartConfig->rxFifoWatermark = 1; + * lpuartConfig->rxIdleType = kLPUART_IdleTypeStartBit; + * lpuartConfig->rxIdleConfig = kLPUART_IdleCharacter1; + * lpuartConfig->enableTx = false; + * lpuartConfig->enableRx = false; + * + * param config Pointer to a configuration structure. + */ void LPUART_GetDefaultConfig(lpuart_config_t *config) { assert(config); + /* Initializes the configure structure to zero. */ + memset(config, 0, sizeof(*config)); + config->baudRate_Bps = 115200U; config->parityMode = kLPUART_ParityDisabled; config->dataBitsCount = kLPUART_EightDataBits; @@ -478,6 +543,21 @@ void LPUART_GetDefaultConfig(lpuart_config_t *config) config->enableRx = false; } +/*! + * brief Sets the LPUART instance baudrate. + * + * This function configures the LPUART module baudrate. This function is used to update + * the LPUART module baudrate after the LPUART module is initialized by the LPUART_Init. + * code + * LPUART_SetBaudRate(LPUART1, 115200U, 20000000U); + * endcode + * + * param base LPUART peripheral base address. + * param baudRate_Bps LPUART baudrate to be set. + * param srcClock_Hz LPUART clock source frequency in HZ. + * retval kStatus_LPUART_BaudrateNotSupport Baudrate is not supported in the current clock source. + * retval kStatus_Success Set baudrate succeeded. + */ status_t LPUART_SetBaudRate(LPUART_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz) { assert(baudRate_Bps); @@ -563,6 +643,19 @@ status_t LPUART_SetBaudRate(LPUART_Type *base, uint32_t baudRate_Bps, uint32_t s } } +/*! + * brief Enables LPUART interrupts according to a provided mask. + * + * This function enables the LPUART interrupts according to a provided mask. The mask + * is a logical OR of enumeration members. See the ref _lpuart_interrupt_enable. + * This examples shows how to enable TX empty interrupt and RX full interrupt: + * code + * LPUART_EnableInterrupts(LPUART1,kLPUART_TxDataRegEmptyInterruptEnable | kLPUART_RxDataRegFullInterruptEnable); + * endcode + * + * param base LPUART peripheral base address. + * param mask The interrupts to enable. Logical OR of ref _uart_interrupt_enable. + */ void LPUART_EnableInterrupts(LPUART_Type *base, uint32_t mask) { base->BAUD |= ((mask << 8) & (LPUART_BAUD_LBKDIE_MASK | LPUART_BAUD_RXEDGIE_MASK)); @@ -574,6 +667,19 @@ void LPUART_EnableInterrupts(LPUART_Type *base, uint32_t mask) base->CTRL |= mask; } +/*! + * brief Disables LPUART interrupts according to a provided mask. + * + * This function disables the LPUART interrupts according to a provided mask. The mask + * is a logical OR of enumeration members. See ref _lpuart_interrupt_enable. + * This example shows how to disable the TX empty interrupt and RX full interrupt: + * code + * LPUART_DisableInterrupts(LPUART1,kLPUART_TxDataRegEmptyInterruptEnable | kLPUART_RxDataRegFullInterruptEnable); + * endcode + * + * param base LPUART peripheral base address. + * param mask The interrupts to disable. Logical OR of ref _lpuart_interrupt_enable. + */ void LPUART_DisableInterrupts(LPUART_Type *base, uint32_t mask) { base->BAUD &= ~((mask << 8) & (LPUART_BAUD_LBKDIE_MASK | LPUART_BAUD_RXEDGIE_MASK)); @@ -585,6 +691,26 @@ void LPUART_DisableInterrupts(LPUART_Type *base, uint32_t mask) base->CTRL &= ~mask; } +/*! + * brief Gets enabled LPUART interrupts. + * + * This function gets the enabled LPUART interrupts. The enabled interrupts are returned + * as the logical OR value of the enumerators ref _lpuart_interrupt_enable. To check + * a specific interrupt enable status, compare the return value with enumerators + * in ref _lpuart_interrupt_enable. + * For example, to check whether the TX empty interrupt is enabled: + * code + * uint32_t enabledInterrupts = LPUART_GetEnabledInterrupts(LPUART1); + * + * if (kLPUART_TxDataRegEmptyInterruptEnable & enabledInterrupts) + * { + * ... + * } + * endcode + * + * param base LPUART peripheral base address. + * return LPUART interrupt flags which are logical OR of the enumerators in ref _lpuart_interrupt_enable. + */ uint32_t LPUART_GetEnabledInterrupts(LPUART_Type *base) { uint32_t temp; @@ -597,6 +723,23 @@ uint32_t LPUART_GetEnabledInterrupts(LPUART_Type *base) return temp; } +/*! + * brief Gets LPUART status flags. + * + * This function gets all LPUART status flags. The flags are returned as the logical + * OR value of the enumerators ref _lpuart_flags. To check for a specific status, + * compare the return value with enumerators in the ref _lpuart_flags. + * For example, to check whether the TX is empty: + * code + * if (kLPUART_TxDataRegEmptyFlag & LPUART_GetStatusFlags(LPUART1)) + * { + * ... + * } + * endcode + * + * param base LPUART peripheral base address. + * return LPUART status flags which are ORed by the enumerators in the _lpuart_flags. + */ uint32_t LPUART_GetStatusFlags(LPUART_Type *base) { uint32_t temp; @@ -609,6 +752,25 @@ uint32_t LPUART_GetStatusFlags(LPUART_Type *base) return temp; } +/*! + * brief Clears status flags with a provided mask. + * + * This function clears LPUART status flags with a provided mask. Automatically cleared flags + * can't be cleared by this function. + * Flags that can only cleared or set by hardware are: + * kLPUART_TxDataRegEmptyFlag, kLPUART_TransmissionCompleteFlag, kLPUART_RxDataRegFullFlag, + * kLPUART_RxActiveFlag, kLPUART_NoiseErrorInRxDataRegFlag, kLPUART_ParityErrorInRxDataRegFlag, + * kLPUART_TxFifoEmptyFlag,kLPUART_RxFifoEmptyFlag + * Note: This API should be called when the Tx/Rx is idle, otherwise it takes no effects. + * + * param base LPUART peripheral base address. + * param mask the status flags to be cleared. The user can use the enumerators in the + * _lpuart_status_flag_t to do the OR operation and get the mask. + * return 0 succeed, others failed. + * retval kStatus_LPUART_FlagCannotClearManually The flag can't be cleared by this function but + * it is cleared automatically by hardware. + * retval kStatus_Success Status in the mask are cleared. + */ status_t LPUART_ClearStatusFlags(LPUART_Type *base, uint32_t mask) { uint32_t temp; @@ -650,6 +812,20 @@ status_t LPUART_ClearStatusFlags(LPUART_Type *base, uint32_t mask) return status; } +/*! + * brief Writes to the transmitter register using a blocking method. + * + * This function polls the transmitter register, waits for the register to be empty or for TX FIFO to have + * room, and writes data to the transmitter buffer. + * + * note This function does not check whether all data has been sent out to the bus. + * Before disabling the transmitter, check the kLPUART_TransmissionCompleteFlag to ensure that the transmit is + * finished. + * + * param base LPUART peripheral base address. + * param data Start address of the data to write. + * param length Size of the data to write. + */ void LPUART_WriteBlocking(LPUART_Type *base, const uint8_t *data, size_t length) { assert(data); @@ -665,6 +841,21 @@ void LPUART_WriteBlocking(LPUART_Type *base, const uint8_t *data, size_t length) } } +/*! +* brief Reads the receiver data register using a blocking method. + * + * This function polls the receiver register, waits for the receiver register full or receiver FIFO + * has data, and reads data from the TX register. + * + * param base LPUART peripheral base address. + * param data Start address of the buffer to store the received data. + * param length Size of the buffer. + * retval kStatus_LPUART_RxHardwareOverrun Receiver overrun happened while receiving data. + * retval kStatus_LPUART_NoiseError Noise error happened while receiving data. + * retval kStatus_LPUART_FramingError Framing error happened while receiving data. + * retval kStatus_LPUART_ParityError Parity error happened while receiving data. + * retval kStatus_Success Successfully received all data. + */ status_t LPUART_ReadBlocking(LPUART_Type *base, uint8_t *data, size_t length) { assert(data); @@ -727,6 +918,24 @@ status_t LPUART_ReadBlocking(LPUART_Type *base, uint8_t *data, size_t length) return kStatus_Success; } +/*! + * brief Initializes the LPUART handle. + * + * This function initializes the LPUART handle, which can be used for other LPUART + * transactional APIs. Usually, for a specified LPUART instance, + * call this API once to get the initialized handle. + * + * The LPUART driver supports the "background" receiving, which means that user can set up + * an RX ring buffer optionally. Data received is stored into the ring buffer even when the + * user doesn't call the LPUART_TransferReceiveNonBlocking() API. If there is already data received + * in the ring buffer, the user can get the received data from the ring buffer directly. + * The ring buffer is disabled if passing NULL as p ringBuffer. + * + * param base LPUART peripheral base address. + * param handle LPUART handle pointer. + * param callback Callback function. + * param userData User data. + */ void LPUART_TransferCreateHandle(LPUART_Type *base, lpuart_handle_t *handle, lpuart_transfer_callback_t callback, @@ -774,6 +983,23 @@ void LPUART_TransferCreateHandle(LPUART_Type *base, #endif } +/*! + * brief Sets up the RX ring buffer. + * + * This function sets up the RX ring buffer to a specific UART handle. + * + * When the RX ring buffer is used, data received is stored into the ring buffer even when + * the user doesn't call the UART_TransferReceiveNonBlocking() API. If there is already data received + * in the ring buffer, the user can get the received data from the ring buffer directly. + * + * note When using RX ring buffer, one byte is reserved for internal use. In other + * words, if p ringBufferSize is 32, then only 31 bytes are used for saving data. + * + * param base LPUART peripheral base address. + * param handle LPUART handle pointer. + * param ringBuffer Start address of ring buffer for background receiving. Pass NULL to disable the ring buffer. + * param ringBufferSize size of the ring buffer. + */ void LPUART_TransferStartRingBuffer(LPUART_Type *base, lpuart_handle_t *handle, uint8_t *ringBuffer, @@ -792,6 +1018,14 @@ void LPUART_TransferStartRingBuffer(LPUART_Type *base, LPUART_EnableInterrupts(base, kLPUART_RxDataRegFullInterruptEnable | kLPUART_RxOverrunInterruptEnable); } +/*! + * brief Aborts the background transfer and uninstalls the ring buffer. + * + * This function aborts the background transfer and uninstalls the ring buffer. + * + * param base LPUART peripheral base address. + * param handle LPUART handle pointer. + */ void LPUART_TransferStopRingBuffer(LPUART_Type *base, lpuart_handle_t *handle) { assert(handle); @@ -807,6 +1041,25 @@ void LPUART_TransferStopRingBuffer(LPUART_Type *base, lpuart_handle_t *handle) handle->rxRingBufferTail = 0U; } +/*! + * brief Transmits a buffer of data using the interrupt method. + * + * This function send data using an interrupt method. This is a non-blocking function, which + * returns directly without waiting for all data written to the transmitter register. When + * all data is written to the TX register in the ISR, the LPUART driver calls the callback + * function and passes the ref kStatus_LPUART_TxIdle as status parameter. + * + * note The kStatus_LPUART_TxIdle is passed to the upper layer when all data are written + * to the TX register. However, there is no check to ensure that all the data sent out. Before disabling the TX, + * check the kLPUART_TransmissionCompleteFlag to ensure that the transmit is finished. + * + * param base LPUART peripheral base address. + * param handle LPUART handle pointer. + * param xfer LPUART transfer structure, see #lpuart_transfer_t. + * retval kStatus_Success Successfully start the data transmission. + * retval kStatus_LPUART_TxBusy Previous transmission still not finished, data not all written to the TX register. + * retval kStatus_InvalidArgument Invalid argument. + */ status_t LPUART_TransferSendNonBlocking(LPUART_Type *base, lpuart_handle_t *handle, lpuart_transfer_t *xfer) { assert(handle); @@ -837,6 +1090,15 @@ status_t LPUART_TransferSendNonBlocking(LPUART_Type *base, lpuart_handle_t *hand return status; } +/*! + * brief Aborts the interrupt-driven data transmit. + * + * This function aborts the interrupt driven data sending. The user can get the remainBtyes to find out + * how many bytes are not sent out. + * + * param base LPUART peripheral base address. + * param handle LPUART handle pointer. + */ void LPUART_TransferAbortSend(LPUART_Type *base, lpuart_handle_t *handle) { assert(handle); @@ -847,6 +1109,19 @@ void LPUART_TransferAbortSend(LPUART_Type *base, lpuart_handle_t *handle) handle->txState = kLPUART_TxIdle; } +/*! + * brief Gets the number of bytes that have been written to the LPUART transmitter register. + * + * This function gets the number of bytes that have been written to LPUART TX + * register by an interrupt method. + * + * param base LPUART peripheral base address. + * param handle LPUART handle pointer. + * param count Send bytes count. + * retval kStatus_NoTransferInProgress No send in progress. + * retval kStatus_InvalidArgument Parameter is invalid. + * retval kStatus_Success Get successfully through the parameter \p count; + */ status_t LPUART_TransferGetSendCount(LPUART_Type *base, lpuart_handle_t *handle, uint32_t *count) { assert(handle); @@ -862,6 +1137,32 @@ status_t LPUART_TransferGetSendCount(LPUART_Type *base, lpuart_handle_t *handle, return kStatus_Success; } +/*! + * brief Receives a buffer of data using the interrupt method. + * + * This function receives data using an interrupt method. This is a non-blocking function + * which returns without waiting to ensure that all data are received. + * If the RX ring buffer is used and not empty, the data in the ring buffer is copied and + * the parameter p receivedBytes shows how many bytes are copied from the ring buffer. + * After copying, if the data in the ring buffer is not enough for read, the receive + * request is saved by the LPUART driver. When the new data arrives, the receive request + * is serviced first. When all data is received, the LPUART driver notifies the upper layer + * through a callback function and passes a status parameter ref kStatus_UART_RxIdle. + * For example, the upper layer needs 10 bytes but there are only 5 bytes in ring buffer. + * The 5 bytes are copied to xfer->data, which returns with the + * parameter p receivedBytes set to 5. For the remaining 5 bytes, the newly arrived data is + * saved from xfer->data[5]. When 5 bytes are received, the LPUART driver notifies the upper layer. + * If the RX ring buffer is not enabled, this function enables the RX and RX interrupt + * to receive data to xfer->data. When all data is received, the upper layer is notified. + * + * param base LPUART peripheral base address. + * param handle LPUART handle pointer. + * param xfer LPUART transfer structure, see #uart_transfer_t. + * param receivedBytes Bytes received from the ring buffer directly. + * retval kStatus_Success Successfully queue the transfer into the transmit queue. + * retval kStatus_LPUART_RxBusy Previous receive request is not finished. + * retval kStatus_InvalidArgument Invalid argument. + */ status_t LPUART_TransferReceiveNonBlocking(LPUART_Type *base, lpuart_handle_t *handle, lpuart_transfer_t *xfer, @@ -978,6 +1279,15 @@ status_t LPUART_TransferReceiveNonBlocking(LPUART_Type *base, return status; } +/*! + * brief Aborts the interrupt-driven data receiving. + * + * This function aborts the interrupt-driven data receiving. The user can get the remainBytes to find out + * how many bytes not received yet. + * + * param base LPUART peripheral base address. + * param handle LPUART handle pointer. + */ void LPUART_TransferAbortReceive(LPUART_Type *base, lpuart_handle_t *handle) { assert(handle); @@ -994,6 +1304,18 @@ void LPUART_TransferAbortReceive(LPUART_Type *base, lpuart_handle_t *handle) handle->rxState = kLPUART_RxIdle; } +/*! + * brief Gets the number of bytes that have been received. + * + * This function gets the number of bytes that have been received. + * + * param base LPUART peripheral base address. + * param handle LPUART handle pointer. + * param count Receive bytes count. + * retval kStatus_NoTransferInProgress No receive in progress. + * retval kStatus_InvalidArgument Parameter is invalid. + * retval kStatus_Success Get successfully through the parameter \p count; + */ status_t LPUART_TransferGetReceiveCount(LPUART_Type *base, lpuart_handle_t *handle, uint32_t *count) { assert(handle); @@ -1009,15 +1331,25 @@ status_t LPUART_TransferGetReceiveCount(LPUART_Type *base, lpuart_handle_t *hand return kStatus_Success; } +/*! + * brief LPUART IRQ handle function. + * + * This function handles the LPUART transmit and receive IRQ request. + * + * param base LPUART peripheral base address. + * param handle LPUART handle pointer. + */ void LPUART_TransferHandleIRQ(LPUART_Type *base, lpuart_handle_t *handle) { assert(handle); uint8_t count; uint8_t tempCount; + uint32_t status = LPUART_GetStatusFlags(base); + uint32_t enabledInterrupts = LPUART_GetEnabledInterrupts(base); /* If RX overrun. */ - if (LPUART_STAT_OR_MASK & base->STAT) + if (kLPUART_RxOverrunFlag & status) { /* Clear overrun flag, otherwise the RX does not work. */ base->STAT = ((base->STAT & 0x3FE00000U) | LPUART_STAT_OR_MASK); @@ -1030,7 +1362,7 @@ void LPUART_TransferHandleIRQ(LPUART_Type *base, lpuart_handle_t *handle) } /* If IDLE flag is set and the IDLE interrupt is enabled. */ - if ((LPUART_STAT_IDLE_MASK & base->STAT) && (LPUART_CTRL_ILIE_MASK & base->CTRL)) + if ((kLPUART_IdleLineFlag & status) && (kLPUART_IdleLineInterruptEnable & enabledInterrupts)) { #if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO count = ((uint8_t)((base->WATER & LPUART_WATER_RXCOUNT_MASK) >> LPUART_WATER_RXCOUNT_SHIFT)); @@ -1073,7 +1405,7 @@ void LPUART_TransferHandleIRQ(LPUART_Type *base, lpuart_handle_t *handle) } } /* Receive data register full */ - if ((LPUART_STAT_RDRF_MASK & base->STAT) && (LPUART_CTRL_RIE_MASK & base->CTRL)) + if ((kLPUART_RxDataRegFullFlag & status) && (kLPUART_RxDataRegFullInterruptEnable & enabledInterrupts)) { /* Get the size that can be stored into buffer for this interrupt. */ #if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO @@ -1173,7 +1505,7 @@ void LPUART_TransferHandleIRQ(LPUART_Type *base, lpuart_handle_t *handle) } /* Send data register empty and the interrupt is enabled. */ - if ((base->STAT & LPUART_STAT_TDRE_MASK) && (base->CTRL & LPUART_CTRL_TIE_MASK)) + if ((kLPUART_TxDataRegEmptyFlag & status) && (kLPUART_TxDataRegEmptyInterruptEnable & enabledInterrupts)) { /* Get the bytes that available at this moment. */ #if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO @@ -1215,6 +1547,14 @@ void LPUART_TransferHandleIRQ(LPUART_Type *base, lpuart_handle_t *handle) } } +/*! + * brief LPUART Error IRQ handle function. + * + * This function handles the LPUART error IRQ request. + * + * param base LPUART peripheral base address. + * param handle LPUART handle pointer. + */ void LPUART_TransferHandleErrorIRQ(LPUART_Type *base, lpuart_handle_t *handle) { /* To be implemented by User. */ diff --git a/ext/hal/nxp/mcux/drivers/imx/fsl_lpuart.h b/ext/hal/nxp/mcux/drivers/imx/fsl_lpuart.h index 5c149de37f4..419951fcbf9 100644 --- a/ext/hal/nxp/mcux/drivers/imx/fsl_lpuart.h +++ b/ext/hal/nxp/mcux/drivers/imx/fsl_lpuart.h @@ -21,8 +21,8 @@ /*! @name Driver version */ /*@{*/ -/*! @brief LPUART driver version 2.2.5. */ -#define FSL_LPUART_DRIVER_VERSION (MAKE_VERSION(2, 2, 5)) +/*! @brief LPUART driver version 2.2.6. */ +#define FSL_LPUART_DRIVER_VERSION (MAKE_VERSION(2, 2, 6)) /*@}*/ /*! @brief Error codes for the LPUART driver. */ @@ -157,8 +157,9 @@ enum _lpuart_flags (LPUART_STAT_FE_MASK), /*!< Frame error flag, sets if logic 0 was detected where stop bit expected */ kLPUART_ParityErrorFlag = (LPUART_STAT_PF_MASK), /*!< If parity enabled, sets upon parity error detection */ #if defined(FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT) && FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT - kLPUART_LinBreakFlag = (LPUART_STAT_LBKDIF_MASK), /*!< LIN break detect interrupt flag, sets when LIN break char - detected and LIN circuit enabled */ + kLPUART_LinBreakFlag = + (int)(LPUART_STAT_LBKDIF_MASK), /*!< LIN break detect interrupt flag, sets when LIN break char + detected and LIN circuit enabled */ #endif kLPUART_RxActiveEdgeFlag = (LPUART_STAT_RXEDGIF_MASK), /*!< Receive pin active edge interrupt flag, sets when active edge detected */ @@ -736,7 +737,7 @@ void LPUART_TransferStopRingBuffer(LPUART_Type *base, lpuart_handle_t *handle); /*! * @brief Get the length of received data in RX ring buffer. * - * @userData handle LPUART handle pointer. + * @param handle LPUART handle pointer. * @return Length of received data in RX ring buffer. */ size_t LPUART_TransferGetRxRingBufferLength(LPUART_Type *base, lpuart_handle_t *handle); diff --git a/ext/hal/nxp/mcux/drivers/imx/fsl_lpuart_edma.c b/ext/hal/nxp/mcux/drivers/imx/fsl_lpuart_edma.c index 01bc6b1ed8c..4313f147c60 100644 --- a/ext/hal/nxp/mcux/drivers/imx/fsl_lpuart_edma.c +++ b/ext/hal/nxp/mcux/drivers/imx/fsl_lpuart_edma.c @@ -154,6 +154,15 @@ static void LPUART_ReceiveEDMACallback(edma_handle_t *handle, void *param, bool } } +/*! + * brief Initializes the LPUART handle which is used in transactional functions. + * param base LPUART peripheral base address. + * param handle Pointer to lpuart_edma_handle_t structure. + * param callback Callback function. + * param userData User data. + * param txEdmaHandle User requested DMA handle for TX DMA transfer. + * param rxEdmaHandle User requested DMA handle for RX DMA transfer. + */ void LPUART_TransferCreateHandleEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle, lpuart_edma_transfer_callback_t callback, @@ -207,6 +216,19 @@ void LPUART_TransferCreateHandleEDMA(LPUART_Type *base, } } +/*! + * brief Sends data using eDMA. + * + * This function sends data using eDMA. This is a non-blocking function, which returns + * right away. When all data is sent, the send callback function is called. + * + * param base LPUART peripheral base address. + * param handle LPUART handle pointer. + * param xfer LPUART eDMA transfer structure. See #lpuart_transfer_t. + * retval kStatus_Success if succeed, others failed. + * retval kStatus_LPUART_TxBusy Previous transfer on going. + * retval kStatus_InvalidArgument Invalid argument. + */ status_t LPUART_SendEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle, lpuart_transfer_t *xfer) { assert(handle); @@ -248,6 +270,19 @@ status_t LPUART_SendEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle, lpuart return status; } +/*! + * brief Receives data using eDMA. + * + * This function receives data using eDMA. This is non-blocking function, which returns + * right away. When all data is received, the receive callback function is called. + * + * param base LPUART peripheral base address. + * param handle Pointer to lpuart_edma_handle_t structure. + * param xfer LPUART eDMA transfer structure, see #lpuart_transfer_t. + * retval kStatus_Success if succeed, others fail. + * retval kStatus_LPUART_RxBusy Previous transfer ongoing. + * retval kStatus_InvalidArgument Invalid argument. + */ status_t LPUART_ReceiveEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle, lpuart_transfer_t *xfer) { assert(handle); @@ -289,6 +324,14 @@ status_t LPUART_ReceiveEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle, lpu return status; } +/*! + * brief Aborts the sent data using eDMA. + * + * This function aborts the sent data using eDMA. + * + * param base LPUART peripheral base address. + * param handle Pointer to lpuart_edma_handle_t structure. + */ void LPUART_TransferAbortSendEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle) { assert(handle); @@ -303,6 +346,14 @@ void LPUART_TransferAbortSendEDMA(LPUART_Type *base, lpuart_edma_handle_t *handl handle->txState = kLPUART_TxIdle; } +/*! + * brief Aborts the received data using eDMA. + * + * This function aborts the received data using eDMA. + * + * param base LPUART peripheral base address. + * param handle Pointer to lpuart_edma_handle_t structure. + */ void LPUART_TransferAbortReceiveEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle) { assert(handle); @@ -317,6 +368,18 @@ void LPUART_TransferAbortReceiveEDMA(LPUART_Type *base, lpuart_edma_handle_t *ha handle->rxState = kLPUART_RxIdle; } +/*! + * brief Gets the number of received bytes. + * + * This function gets the number of received bytes. + * + * param base LPUART peripheral base address. + * param handle LPUART handle pointer. + * param count Receive bytes count. + * retval kStatus_NoTransferInProgress No receive in progress. + * retval kStatus_InvalidArgument Parameter is invalid. + * retval kStatus_Success Get successfully through the parameter \p count; + */ status_t LPUART_TransferGetReceiveCountEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle, uint32_t *count) { assert(handle); @@ -335,6 +398,19 @@ status_t LPUART_TransferGetReceiveCountEDMA(LPUART_Type *base, lpuart_edma_handl return kStatus_Success; } +/*! + * brief Gets the number of bytes written to the LPUART TX register. + * + * This function gets the number of bytes written to the LPUART TX + * register by DMA. + * + * param base LPUART peripheral base address. + * param handle LPUART handle pointer. + * param count Send bytes count. + * retval kStatus_NoTransferInProgress No send in progress. + * retval kStatus_InvalidArgument Parameter is invalid. + * retval kStatus_Success Get successfully through the parameter \p count; + */ status_t LPUART_TransferGetSendCountEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle, uint32_t *count) { assert(handle); diff --git a/ext/hal/nxp/mcux/drivers/imx/fsl_lpuart_edma.h b/ext/hal/nxp/mcux/drivers/imx/fsl_lpuart_edma.h index 3d6e25b7c93..70e456fbd83 100644 --- a/ext/hal/nxp/mcux/drivers/imx/fsl_lpuart_edma.h +++ b/ext/hal/nxp/mcux/drivers/imx/fsl_lpuart_edma.h @@ -2,7 +2,7 @@ * Copyright (c) 2015, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP * All rights reserved. - * + * * SPDX-License-Identifier: BSD-3-Clause */ #ifndef _FSL_LPUART_EDMA_H_ @@ -22,8 +22,8 @@ /*! @name Driver version */ /*@{*/ -/*! @brief LPUART EDMA driver version 2.2.5. */ -#define FSL_LPUART_EDMA_DRIVER_VERSION (MAKE_VERSION(2, 2, 5)) +/*! @brief LPUART EDMA driver version 2.2.6. */ +#define FSL_LPUART_EDMA_DRIVER_VERSION (MAKE_VERSION(2, 2, 6)) /*@}*/ /* Forward declaration of the handle typedef. */ diff --git a/ext/hal/nxp/mcux/drivers/imx/fsl_pit.c b/ext/hal/nxp/mcux/drivers/imx/fsl_pit.c index 60171732d31..5de59188526 100644 --- a/ext/hal/nxp/mcux/drivers/imx/fsl_pit.c +++ b/ext/hal/nxp/mcux/drivers/imx/fsl_pit.c @@ -57,6 +57,14 @@ static uint32_t PIT_GetInstance(PIT_Type *base) return instance; } +/*! + * brief Ungates the PIT clock, enables the PIT module, and configures the peripheral for basic operations. + * + * note This API should be called at the beginning of the application using the PIT driver. + * + * param base PIT peripheral base address + * param config Pointer to the user's PIT config structure + */ void PIT_Init(PIT_Type *base, const pit_config_t *config) { assert(config); @@ -90,6 +98,11 @@ void PIT_Init(PIT_Type *base, const pit_config_t *config) } } +/*! + * brief Gates the PIT clock and disables the PIT module. + * + * param base PIT peripheral base address + */ void PIT_Deinit(PIT_Type *base) { #if defined(FSL_FEATURE_PIT_HAS_MDIS) && FSL_FEATURE_PIT_HAS_MDIS @@ -105,6 +118,19 @@ void PIT_Deinit(PIT_Type *base) #if defined(FSL_FEATURE_PIT_HAS_LIFETIME_TIMER) && FSL_FEATURE_PIT_HAS_LIFETIME_TIMER +/*! + * brief Reads the current lifetime counter value. + * + * The lifetime timer is a 64-bit timer which chains timer 0 and timer 1 together. + * Timer 0 and 1 are chained by calling the PIT_SetTimerChainMode before using this timer. + * The period of lifetime timer is equal to the "period of timer 0 * period of timer 1". + * For the 64-bit value, the higher 32-bit has the value of timer 1, and the lower 32-bit + * has the value of timer 0. + * + * param base PIT peripheral base address + * + * return Current lifetime timer value + */ uint64_t PIT_GetLifetimeTimerCount(PIT_Type *base) { uint32_t valueH = 0U; diff --git a/ext/hal/nxp/mcux/drivers/imx/fsl_pmu.c b/ext/hal/nxp/mcux/drivers/imx/fsl_pmu.c index f591f1865b2..f3e0571f0d1 100644 --- a/ext/hal/nxp/mcux/drivers/imx/fsl_pmu.c +++ b/ext/hal/nxp/mcux/drivers/imx/fsl_pmu.c @@ -2,7 +2,7 @@ * Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP * All rights reserved. - * + * * SPDX-License-Identifier: BSD-3-Clause */ #include "fsl_pmu.h" @@ -12,6 +12,10 @@ #define FSL_COMPONENT_ID "platform.drivers.pmu" #endif +/*! + * name Status. + * { + */ uint32_t PMU_GetStatusFlags(PMU_Type *base) { diff --git a/ext/hal/nxp/mcux/drivers/imx/fsl_pmu.h b/ext/hal/nxp/mcux/drivers/imx/fsl_pmu.h index 49f3f854ba3..e8856468255 100644 --- a/ext/hal/nxp/mcux/drivers/imx/fsl_pmu.h +++ b/ext/hal/nxp/mcux/drivers/imx/fsl_pmu.h @@ -107,6 +107,13 @@ extern "C" { * @{ */ +/*! + * @brief Get PMU status flags. + * + * @param base PMU peripheral base address. + * @return PMU status flags.It indicate if regulator output of 1P1,3P0 and 2P5 is ok + * and brownout output of 1P1,3P0 and 2P5 is detected. + */ uint32_t PMU_GetStatusFlags(PMU_Type *base); /*@}*/ diff --git a/ext/hal/nxp/mcux/drivers/imx/fsl_pwm.c b/ext/hal/nxp/mcux/drivers/imx/fsl_pwm.c index aecd02fc012..fb6ad2237f0 100644 --- a/ext/hal/nxp/mcux/drivers/imx/fsl_pwm.c +++ b/ext/hal/nxp/mcux/drivers/imx/fsl_pwm.c @@ -2,7 +2,7 @@ * Copyright (c) 2015, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP * All rights reserved. - * + * * SPDX-License-Identifier: BSD-3-Clause */ @@ -13,7 +13,6 @@ #define FSL_COMPONENT_ID "platform.drivers.pwm" #endif - /******************************************************************************* * Prototypes ******************************************************************************/ @@ -58,6 +57,17 @@ static uint32_t PWM_GetInstance(PWM_Type *base) return instance; } +/*! + * brief Ungates the PWM submodule clock and configures the peripheral for basic operation. + * + * note This API should be called at the beginning of the application using the PWM driver. + * + * param base PWM peripheral base address + * param subModule PWM submodule to configure + * param config Pointer to user's PWM config structure. + * + * return kStatus_Success means success; else failed. + */ status_t PWM_Init(PWM_Type *base, pwm_submodule_t subModule, const pwm_config_t *config) { assert(config); @@ -161,6 +171,12 @@ status_t PWM_Init(PWM_Type *base, pwm_submodule_t subModule, const pwm_config_t return kStatus_Success; } +/*! + * brief Gate the PWM submodule clock + * + * param base PWM peripheral base address + * param subModule PWM submodule to deinitialize + */ void PWM_Deinit(PWM_Type *base, pwm_submodule_t subModule) { /* Stop the submodule */ @@ -172,10 +188,33 @@ void PWM_Deinit(PWM_Type *base, pwm_submodule_t subModule) #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ } +/*! + * brief Fill in the PWM config struct with the default settings + * + * The default values are: + * code + * config->enableDebugMode = false; + * config->enableWait = false; + * config->reloadSelect = kPWM_LocalReload; + * config->faultFilterCount = 0; + * config->faultFilterPeriod = 0; + * config->clockSource = kPWM_BusClock; + * config->prescale = kPWM_Prescale_Divide_1; + * config->initializationControl = kPWM_Initialize_LocalSync; + * config->forceTrigger = kPWM_Force_Local; + * config->reloadFrequency = kPWM_LoadEveryOportunity; + * config->reloadLogic = kPWM_ReloadImmediate; + * config->pairOperation = kPWM_Independent; + * endcode + * param config Pointer to user's PWM config structure. + */ void PWM_GetDefaultConfig(pwm_config_t *config) { assert(config); + /* Initializes the configure structure to zero. */ + memset(config, 0, sizeof(*config)); + /* PWM is paused in debug mode */ config->enableDebugMode = false; /* PWM is paused in wait mode */ @@ -204,6 +243,25 @@ void PWM_GetDefaultConfig(pwm_config_t *config) config->pairOperation = kPWM_Independent; } +/*! + * brief Sets up the PWM signals for a PWM submodule. + * + * The function initializes the submodule according to the parameters passed in by the user. The function + * also sets up the value compare registers to match the PWM signal requirements. + * If the dead time insertion logic is enabled, the pulse period is reduced by the + * dead time period specified by the user. + * + * param base PWM peripheral base address + * param subModule PWM submodule to configure + * param chnlParams Array of PWM channel parameters to configure the channel(s) + * param numOfChnls Number of channels to configure, this should be the size of the array passed in. + * Array size should not be more than 2 as each submodule has 2 pins to output PWM + * param mode PWM operation mode, options available in enumeration ::pwm_mode_t + * param pwmFreq_Hz PWM signal frequency in Hz + * param srcClock_Hz PWM main counter clock in Hz. + * + * return Returns kStatusFail if there was error setting up the signal; kStatusSuccess otherwise + */ status_t PWM_SetupPwm(PWM_Type *base, pwm_submodule_t subModule, const pwm_signal_param_t *chnlParams, @@ -365,6 +423,21 @@ status_t PWM_SetupPwm(PWM_Type *base, return kStatus_Success; } +/*! + * brief Updates the PWM signal's dutycycle. + * + * The function updates the PWM dutycyle to the new value that is passed in. + * If the dead time insertion logic is enabled then the pulse period is reduced by the + * dead time period specified by the user. + * + * param base PWM peripheral base address + * param subModule PWM submodule to configure + * param pwmSignal Signal (PWM A or PWM B) to update + * param currPwmMode The current PWM mode set during PWM setup + * param dutyCyclePercent New PWM pulse width, value should be between 0 to 100 + * 0=inactive signal(0% duty cycle)... + * 100=active signal (100% duty cycle) + */ void PWM_UpdatePwmDutycycle(PWM_Type *base, pwm_submodule_t subModule, pwm_channels_t pwmSignal, @@ -453,6 +526,17 @@ void PWM_UpdatePwmDutycycle(PWM_Type *base, } } +/*! + * brief Sets up the PWM input capture + * + * Each PWM submodule has 3 pins that can be configured for use as input capture pins. This function + * sets up the capture parameters for each pin and enables the pin for input capture operation. + * + * param base PWM peripheral base address + * param subModule PWM submodule to configure + * param pwmChannel Channel in the submodule to setup + * param inputCaptureParams Parameters passed in to set up the input pin + */ void PWM_SetupInputCapture(PWM_Type *base, pwm_submodule_t subModule, pwm_channels_t pwmChannel, @@ -529,6 +613,15 @@ void PWM_SetupInputCapture(PWM_Type *base, } } +/*! + * brief Sets up the PWM fault protection. + * + * PWM has 4 fault inputs. + * + * param base PWM peripheral base address + * param faultNum PWM fault to configure. + * param faultParams Pointer to the PWM fault config structure + */ void PWM_SetupFaults(PWM_Type *base, pwm_fault_input_t faultNum, const pwm_fault_param_t *faultParams) { assert(faultParams); @@ -603,6 +696,17 @@ void PWM_SetupFaults(PWM_Type *base, pwm_fault_input_t faultNum, const pwm_fault base->FSTS = reg; } +/*! + * brief Selects the signal to output on a PWM pin when a FORCE_OUT signal is asserted. + * + * The user specifies which channel to configure by supplying the submodule number and whether + * to modify PWM A or PWM B within that submodule. + * + * param base PWM peripheral base address + * param subModule PWM submodule to configure + * param pwmChannel Channel to configure + * param mode Signal to output when a FORCE_OUT is triggered + */ void PWM_SetupForceSignal(PWM_Type *base, pwm_submodule_t subModule, pwm_channels_t pwmChannel, pwm_force_signal_t mode) { @@ -619,6 +723,14 @@ void PWM_SetupForceSignal(PWM_Type *base, pwm_submodule_t subModule, pwm_channel base->DTSRCSEL = reg; } +/*! + * brief Enables the selected PWM interrupts + * + * param base PWM peripheral base address + * param subModule PWM submodule to configure + * param mask The interrupts to enable. This is a logical OR of members of the + * enumeration ::pwm_interrupt_enable_t + */ void PWM_EnableInterrupts(PWM_Type *base, pwm_submodule_t subModule, uint32_t mask) { /* Upper 16 bits are for related to the submodule */ @@ -627,12 +739,29 @@ void PWM_EnableInterrupts(PWM_Type *base, pwm_submodule_t subModule, uint32_t ma base->FCTRL |= ((mask >> 16U) & PWM_FCTRL_FIE_MASK); } +/*! + * brief Disables the selected PWM interrupts + * + * param base PWM peripheral base address + * param subModule PWM submodule to configure + * param mask The interrupts to enable. This is a logical OR of members of the + * enumeration ::pwm_interrupt_enable_t + */ void PWM_DisableInterrupts(PWM_Type *base, pwm_submodule_t subModule, uint32_t mask) { base->SM[subModule].INTEN &= ~(mask & 0xFFFF); base->FCTRL &= ~((mask >> 16U) & PWM_FCTRL_FIE_MASK); } +/*! + * brief Gets the enabled PWM interrupts + * + * param base PWM peripheral base address + * param subModule PWM submodule to configure + * + * return The enabled interrupts. This is the logical OR of members of the + * enumeration ::pwm_interrupt_enable_t + */ uint32_t PWM_GetEnabledInterrupts(PWM_Type *base, pwm_submodule_t subModule) { uint32_t enabledInterrupts; @@ -642,6 +771,15 @@ uint32_t PWM_GetEnabledInterrupts(PWM_Type *base, pwm_submodule_t subModule) return enabledInterrupts; } +/*! + * brief Gets the PWM status flags + * + * param base PWM peripheral base address + * param subModule PWM submodule to configure + * + * return The status flags. This is the logical OR of members of the + * enumeration ::pwm_status_flags_t + */ uint32_t PWM_GetStatusFlags(PWM_Type *base, pwm_submodule_t subModule) { uint32_t statusFlags; @@ -652,6 +790,14 @@ uint32_t PWM_GetStatusFlags(PWM_Type *base, pwm_submodule_t subModule) return statusFlags; } +/*! + * brief Clears the PWM status flags + * + * param base PWM peripheral base address + * param subModule PWM submodule to configure + * param mask The status flags to clear. This is a logical OR of members of the + * enumeration ::pwm_status_flags_t + */ void PWM_ClearStatusFlags(PWM_Type *base, pwm_submodule_t subModule, uint32_t mask) { uint16_t reg; diff --git a/ext/hal/nxp/mcux/drivers/imx/fsl_pxp.c b/ext/hal/nxp/mcux/drivers/imx/fsl_pxp.c index 6e1edc357f1..602d578c25d 100644 --- a/ext/hal/nxp/mcux/drivers/imx/fsl_pxp.c +++ b/ext/hal/nxp/mcux/drivers/imx/fsl_pxp.c @@ -2,7 +2,7 @@ * Copyright (c) 2017, NXP Semiconductors, Inc. * All rights reserved. * - * + * * SPDX-License-Identifier: BSD-3-Clause */ @@ -192,6 +192,14 @@ static void PXP_GetScalerParam(uint16_t inputDimension, uint16_t outputDimension } } +/*! + * brief Initialize the PXP. + * + * This function enables the PXP peripheral clock, and resets the PXP registers + * to default status. + * + * param base PXP peripheral base address. + */ void PXP_Init(PXP_Type *base) { uint32_t ctrl = 0U; @@ -222,6 +230,13 @@ void PXP_Init(PXP_Type *base) base->CTRL = ctrl; } +/*! + * brief De-initialize the PXP. + * + * This function disables the PXP peripheral clock. + * + * param base PXP peripheral base address. + */ void PXP_Deinit(PXP_Type *base) { #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) @@ -230,12 +245,25 @@ void PXP_Deinit(PXP_Type *base) #endif } +/*! + * brief Reset the PXP. + * + * This function resets the PXP peripheral registers to default status. + * + * param base PXP peripheral base address. + */ void PXP_Reset(PXP_Type *base) { base->CTRL_SET = PXP_CTRL_SFTRST_MASK; base->CTRL_CLR = (PXP_CTRL_SFTRST_MASK | PXP_CTRL_CLKGATE_MASK); } +/*! + * brief Set the alpha surface input buffer configuration. + * + * param base PXP peripheral base address. + * param config Pointer to the configuration. + */ void PXP_SetAlphaSurfaceBufferConfig(PXP_Type *base, const pxp_as_buffer_config_t *config) { assert(config); @@ -246,6 +274,12 @@ void PXP_SetAlphaSurfaceBufferConfig(PXP_Type *base, const pxp_as_buffer_config_ base->AS_PITCH = config->pitchBytes; } +/*! + * brief Set the alpha surface blending configuration. + * + * param base PXP peripheral base address. + * param config Pointer to the configuration structure. + */ void PXP_SetAlphaSurfaceBlendConfig(PXP_Type *base, const pxp_as_blend_config_t *config) { assert(config); @@ -265,6 +299,15 @@ void PXP_SetAlphaSurfaceBlendConfig(PXP_Type *base, const pxp_as_blend_config_t base->AS_CTRL = reg; } +/*! + * brief Set the alpha surface position in output buffer. + * + * param base PXP peripheral base address. + * param upperLeftX X of the upper left corner. + * param upperLeftY Y of the upper left corner. + * param lowerRightX X of the lower right corner. + * param lowerRightY Y of the lower right corner. + */ void PXP_SetAlphaSurfacePosition( PXP_Type *base, uint16_t upperLeftX, uint16_t upperLeftY, uint16_t lowerRightX, uint16_t lowerRightY) { @@ -272,12 +315,32 @@ void PXP_SetAlphaSurfacePosition( base->OUT_AS_LRC = PXP_OUT_AS_LRC_Y(lowerRightY) | PXP_OUT_AS_LRC_X(lowerRightX); } +/*! + * brief Set the alpha surface overlay color key. + * + * If a pixel in the current overlay image with a color that falls in the range + * from the p colorKeyLow to p colorKeyHigh range, it will use the process surface + * pixel value for that location. If no PS image is present or if the PS image also + * matches its colorkey range, the PS background color is used. + * + * param base PXP peripheral base address. + * param colorKeyLow Color key low range. + * param colorKeyHigh Color key high range. + * + * note Colorkey operations are higher priority than alpha or ROP operations + */ void PXP_SetAlphaSurfaceOverlayColorKey(PXP_Type *base, uint32_t colorKeyLow, uint32_t colorKeyHigh) { base->AS_CLRKEYLOW = colorKeyLow; base->AS_CLRKEYHIGH = colorKeyHigh; } +/*! + * brief Set the process surface input buffer configuration. + * + * param base PXP peripheral base address. + * param config Pointer to the configuration. + */ void PXP_SetProcessSurfaceBufferConfig(PXP_Type *base, const pxp_ps_buffer_config_t *config) { assert(config); @@ -291,6 +354,17 @@ void PXP_SetProcessSurfaceBufferConfig(PXP_Type *base, const pxp_ps_buffer_confi base->PS_PITCH = config->pitchBytes; } +/*! + * brief Set the process surface scaler configuration. + * + * The valid down scale fact is 1/(2^12) ~ 16. + * + * param base PXP peripheral base address. + * param inputWidth Input image width. + * param inputHeight Input image height. + * param outputWidth Output image width. + * param outputHeight Output image height. + */ void PXP_SetProcessSurfaceScaler( PXP_Type *base, uint16_t inputWidth, uint16_t inputHeight, uint16_t outputWidth, uint16_t outputHeight) { @@ -306,6 +380,15 @@ void PXP_SetProcessSurfaceScaler( base->PS_SCALE = PXP_PS_SCALE_XSCALE(scaleX) | PXP_PS_SCALE_YSCALE(scaleY); } +/*! + * brief Set the process surface position in output buffer. + * + * param base PXP peripheral base address. + * param upperLeftX X of the upper left corner. + * param upperLeftY Y of the upper left corner. + * param lowerRightX X of the lower right corner. + * param lowerRightY Y of the lower right corner. + */ void PXP_SetProcessSurfacePosition( PXP_Type *base, uint16_t upperLeftX, uint16_t upperLeftY, uint16_t lowerRightX, uint16_t lowerRightY) { @@ -313,12 +396,28 @@ void PXP_SetProcessSurfacePosition( base->OUT_PS_LRC = PXP_OUT_PS_LRC_Y(lowerRightY) | PXP_OUT_PS_LRC_X(lowerRightX); } +/*! + * brief Set the process surface color key. + * + * If the PS image matches colorkey range, the PS background color is output. Set + * p colorKeyLow to 0xFFFFFFFF and p colorKeyHigh to 0 will disable the colorkeying. + * + * param base PXP peripheral base address. + * param colorKeyLow Color key low range. + * param colorKeyHigh Color key high range. + */ void PXP_SetProcessSurfaceColorKey(PXP_Type *base, uint32_t colorKeyLow, uint32_t colorKeyHigh) { base->PS_CLRKEYLOW = colorKeyLow; base->PS_CLRKEYHIGH = colorKeyHigh; } +/*! + * brief Set the PXP outpt buffer configuration. + * + * param base PXP peripheral base address. + * param config Pointer to the configuration. + */ void PXP_SetOutputBufferConfig(PXP_Type *base, const pxp_output_buffer_config_t *config) { assert(config); @@ -343,6 +442,16 @@ void PXP_SetOutputBufferConfig(PXP_Type *base, const pxp_output_buffer_config_t } #if !(defined(FSL_FEATURE_PXP_HAS_NO_CSC2) && FSL_FEATURE_PXP_HAS_NO_CSC2) +/*! + * brief Set the CSC2 configuration. + * + * The CSC2 module receives pixels in any color space and can convert the pixels + * into any of RGB, YUV, or YCbCr color spaces. The output pixels are passed + * onto the LUT and rotation engine for further processing + * + * param base PXP peripheral base address. + * param config Pointer to the configuration. + */ void PXP_SetCsc2Config(PXP_Type *base, const pxp_csc2_config_t *config) { assert(config); @@ -373,6 +482,16 @@ void PXP_SetCsc2Config(PXP_Type *base, const pxp_csc2_config_t *config) } #endif +/*! + * brief Set the CSC1 mode. + * + * The CSC1 module receives scaled YUV/YCbCr444 pixels from the scale engine and + * converts the pixels to the RGB888 color space. It could only be used by process + * surface. + * + * param base PXP peripheral base address. + * param mode The conversion mode. + */ void PXP_SetCsc1Mode(PXP_Type *base, pxp_csc1_mode_t mode) { /* @@ -411,6 +530,19 @@ void PXP_SetCsc1Mode(PXP_Type *base, pxp_csc1_mode_t mode) } #if !(defined(FSL_FEATURE_PXP_HAS_NO_LUT) && FSL_FEATURE_PXP_HAS_NO_LUT) +/*! + * brief Set the LUT configuration. + * + * The lookup table (LUT) is used to modify pixels in a manner that is not linear + * and that cannot be achieved by the color space conversion modules. To setup + * the LUT, the complete workflow is: + * 1. Use ref PXP_SetLutConfig to set the configuration, such as the lookup mode. + * 2. Use ref PXP_LoadLutTable to load the lookup table to PXP. + * 3. Use ref PXP_EnableLut to enable the function. + * + * param base PXP peripheral base address. + * param config Pointer to the configuration. + */ void PXP_SetLutConfig(PXP_Type *base, const pxp_lut_config_t *config) { base->LUT_CTRL = (base->LUT_CTRL & ~(PXP_LUT_CTRL_OUT_MODE_MASK | PXP_LUT_CTRL_LOOKUP_MODE_MASK)) | @@ -423,6 +555,28 @@ void PXP_SetLutConfig(PXP_Type *base, const pxp_lut_config_t *config) } } +/*! + * brief Set the look up table to PXP. + * + * If lookup mode is DIRECT mode, this function loads p bytesNum of values + * from the address p memAddr into PXP LUT address p lutStartAddr. So this + * function allows only update part of the PXP LUT. + * + * If lookup mode is CACHE mode, this function sets the new address to p memAddr + * and invalid the PXP LUT cache. + * + * param base PXP peripheral base address. + * param lookupMode Which lookup mode is used. Note that this parameter is only + * used to distinguish DIRECT mode and CACHE mode, it does not change the register + * value PXP_LUT_CTRL[LOOKUP_MODE]. To change that value, use function ref PXP_SetLutConfig. + * param bytesNum How many bytes to set. This value must be divisable by 8. + * param memAddr Address of look up table to set. + * param lutStartAddr The LUT value will be loaded to LUT from index lutAddr. It should + * be 8 bytes aligned. + * + * retval kStatus_Success Load successfully. + * retval kStatus_InvalidArgument Failed because of invalid argument. + */ status_t PXP_LoadLutTable( PXP_Type *base, pxp_lut_lookup_mode_t lookupMode, uint32_t bytesNum, uint32_t memAddr, uint16_t lutStartAddr) { @@ -465,6 +619,15 @@ status_t PXP_LoadLutTable( #endif /* FSL_FEATURE_PXP_HAS_NO_LUT */ #if (defined(FSL_FEATURE_PXP_HAS_DITHER) && FSL_FEATURE_PXP_HAS_DITHER) +/*! + * brief Write data to the PXP internal memory. + * + * param base PXP peripheral base address. + * param ram Which internal memory to write. + * param bytesNum How many bytes to write. + * param data Pointer to the data to write. + * param memStartAddr The start address in the internal memory to write the data. + */ void PXP_SetInternalRamData(PXP_Type *base, pxp_ram_t ram, uint32_t bytesNum, uint8_t *data, uint16_t memStartAddr) { assert((memStartAddr + bytesNum) <= PXP_INTERNAL_RAM_LUT_BYTE); @@ -481,6 +644,16 @@ void PXP_SetInternalRamData(PXP_Type *base, pxp_ram_t ram, uint32_t bytesNum, ui base->INIT_MEM_CTRL = 0U; } +/*! + * brief Set the dither final LUT data. + * + * The dither final LUT is only applicble to dither engine 0. It takes the bits[7:4] + * of the output pixel and looks up and 8 bit value from the 16 value LUT to generate + * the final output pixel to the next process module. + * + * param base PXP peripheral base address. + * param data Pointer to the LUT data to set. + */ void PXP_SetDitherFinalLutData(PXP_Type *base, const pxp_dither_final_lut_data_t *data) { base->DITHER_FINAL_LUT_DATA0 = data->data_3_0; @@ -489,6 +662,19 @@ void PXP_SetDitherFinalLutData(PXP_Type *base, const pxp_dither_final_lut_data_t base->DITHER_FINAL_LUT_DATA3 = data->data_15_12; } +/*! + * brief Enable or disable dither engine in the PXP process path. + * + * After the initialize function ref PXP_Init, the dither engine is disabled and not + * use in the PXP processing path. This function enables the dither engine and + * routes the dither engine output to the output buffer. When the dither engine + * is enabled using this function, ref PXP_SetDitherConfig must be called to + * configure dither engine correctly, otherwise there is not output to the output + * buffer. + * + * param base PXP peripheral base address. + * param enable Pass in true to enable, false to disable. + */ void PXP_EnableDither(PXP_Type *base, bool enable) { if (enable) diff --git a/ext/hal/nxp/mcux/drivers/imx/fsl_pxp.h b/ext/hal/nxp/mcux/drivers/imx/fsl_pxp.h index 870cf97fbbb..3fdad8de9fa 100644 --- a/ext/hal/nxp/mcux/drivers/imx/fsl_pxp.h +++ b/ext/hal/nxp/mcux/drivers/imx/fsl_pxp.h @@ -2,7 +2,7 @@ * Copyright (c) 2017, NXP Semiconductors, Inc. * All rights reserved. * - * + * * SPDX-License-Identifier: BSD-3-Clause */ @@ -48,7 +48,7 @@ /*! @name Driver version */ /*@{*/ -#define FSL_PXP_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0 */ +#define FSL_PXP_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) /*!< Version 2.0.1 */ /*@}*/ /* This macto indicates whether the rotate sub module is shared by process surface and output buffer. */ @@ -888,11 +888,31 @@ static inline void PXP_SetRotateConfig(PXP_Type *base, if (kPXP_RotateOutputBuffer == position) { + if ((degree != kPXP_Rotate0) || (flipMode != kPXP_FlipDisable)) + { + base->DATA_PATH_CTRL0 = + (base->DATA_PATH_CTRL0 & (~PXP_DATA_PATH_CTRL0_MUX12_SEL_MASK)) | PXP_DATA_PATH_CTRL0_MUX12_SEL(0); + } + else + { + base->DATA_PATH_CTRL0 = + (base->DATA_PATH_CTRL0 & (~PXP_DATA_PATH_CTRL0_MUX12_SEL_MASK)) | PXP_DATA_PATH_CTRL0_MUX12_SEL(1); + } ctrl &= ~(PXP_CTRL_HFLIP0_MASK | PXP_CTRL_VFLIP0_MASK | PXP_CTRL_ROTATE0_MASK); ctrl |= (PXP_CTRL_ROTATE0(degree) | ((uint32_t)flipMode << PXP_CTRL_HFLIP0_SHIFT)); } else { + if ((degree != kPXP_Rotate0) || (flipMode != kPXP_FlipDisable)) + { + base->DATA_PATH_CTRL0 = + (base->DATA_PATH_CTRL0 & (~PXP_DATA_PATH_CTRL0_MUX3_SEL_MASK)) | PXP_DATA_PATH_CTRL0_MUX3_SEL(1); + } + else + { + base->DATA_PATH_CTRL0 = + (base->DATA_PATH_CTRL0 & (~PXP_DATA_PATH_CTRL0_MUX3_SEL_MASK)) | PXP_DATA_PATH_CTRL0_MUX3_SEL(0); + } ctrl &= ~(PXP_CTRL_HFLIP1_MASK | PXP_CTRL_VFLIP1_MASK | PXP_CTRL_ROTATE1_MASK); ctrl |= (PXP_CTRL_ROTATE1(degree) | ((uint32_t)flipMode << PXP_CTRL_HFLIP1_SHIFT)); } diff --git a/ext/hal/nxp/mcux/drivers/imx/fsl_qtmr.c b/ext/hal/nxp/mcux/drivers/imx/fsl_qtmr.c index c18fc91f418..5d4c556aee1 100644 --- a/ext/hal/nxp/mcux/drivers/imx/fsl_qtmr.c +++ b/ext/hal/nxp/mcux/drivers/imx/fsl_qtmr.c @@ -1,7 +1,7 @@ /* * Copyright 2017 NXP * All rights reserved. - * + * * SPDX-License-Identifier: BSD-3-Clause */ @@ -12,7 +12,6 @@ #define FSL_COMPONENT_ID "platform.drivers.qtmr" #endif - /******************************************************************************* * Prototypes ******************************************************************************/ @@ -57,6 +56,15 @@ static uint32_t QTMR_GetInstance(TMR_Type *base) return instance; } +/*! + * brief Ungates the Quad Timer clock and configures the peripheral for basic operation. + * + * note This API should be called at the beginning of the application using the Quad Timer driver. + * + * param base Quad Timer peripheral base address + * param channel Quad Timer channel number + * param config Pointer to user's Quad Timer config structure + */ void QTMR_Init(TMR_Type *base, qtmr_channel_selection_t channel, const qtmr_config_t *config) { assert(config); @@ -65,21 +73,29 @@ void QTMR_Init(TMR_Type *base, qtmr_channel_selection_t channel, const qtmr_conf /* Enable the module clock */ CLOCK_EnableClock(s_qtmrClocks[QTMR_GetInstance(base)]); #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - + /* Setup the counter sources */ base->CHANNEL[channel].CTRL = (TMR_CTRL_PCS(config->primarySource) | TMR_CTRL_SCS(config->secondarySource)); /* Setup the master mode operation */ - base->CHANNEL[channel].SCTRL = (TMR_SCTRL_EEOF(config->enableExternalForce) | TMR_SCTRL_MSTR(config->enableMasterMode)); + base->CHANNEL[channel].SCTRL = + (TMR_SCTRL_EEOF(config->enableExternalForce) | TMR_SCTRL_MSTR(config->enableMasterMode)); /* Setup debug mode */ base->CHANNEL[channel].CSCTRL = TMR_CSCTRL_DBG_EN(config->debugMode); - - base->CHANNEL[channel].FILT &= ~( TMR_FILT_FILT_CNT_MASK | TMR_FILT_FILT_PER_MASK); + + base->CHANNEL[channel].FILT &= ~(TMR_FILT_FILT_CNT_MASK | TMR_FILT_FILT_PER_MASK); /* Setup input filter */ - base->CHANNEL[channel].FILT = (TMR_FILT_FILT_CNT(config->faultFilterCount) | TMR_FILT_FILT_PER(config->faultFilterPeriod)); + base->CHANNEL[channel].FILT = + (TMR_FILT_FILT_CNT(config->faultFilterCount) | TMR_FILT_FILT_PER(config->faultFilterPeriod)); } +/*! + * brief Stops the counter and gates the Quad Timer clock + * + * param base Quad Timer peripheral base address + * param channel Quad Timer channel number + */ void QTMR_Deinit(TMR_Type *base, qtmr_channel_selection_t channel) { /* Stop the counter */ @@ -91,10 +107,28 @@ void QTMR_Deinit(TMR_Type *base, qtmr_channel_selection_t channel) #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ } +/*! + * brief Fill in the Quad Timer config struct with the default settings + * + * The default values are: + * code + * config->debugMode = kQTMR_RunNormalInDebug; + * config->enableExternalForce = false; + * config->enableMasterMode = false; + * config->faultFilterCount = 0; + * config->faultFilterPeriod = 0; + * config->primarySource = kQTMR_ClockDivide_2; + * config->secondarySource = kQTMR_Counter0InputPin; + * endcode + * param config Pointer to user's Quad Timer config structure. + */ void QTMR_GetDefaultConfig(qtmr_config_t *config) { assert(config); + /* Initializes the configure structure to zero. */ + memset(config, 0, sizeof(*config)); + /* Halt counter during debug mode */ config->debugMode = kQTMR_RunNormalInDebug; /* Another counter cannot force state of OFLAG signal */ @@ -111,8 +145,29 @@ void QTMR_GetDefaultConfig(qtmr_config_t *config) config->secondarySource = kQTMR_Counter0InputPin; } -status_t QTMR_SetupPwm( - TMR_Type *base, qtmr_channel_selection_t channel, uint32_t pwmFreqHz, uint8_t dutyCyclePercent, bool outputPolarity, uint32_t srcClock_Hz) +/*! + * brief Sets up Quad timer module for PWM signal output. + * + * The function initializes the timer module according to the parameters passed in by the user. The + * function also sets up the value compare registers to match the PWM signal requirements. + * + * param base Quad Timer peripheral base address + * param channel Quad Timer channel number + * param pwmFreqHz PWM signal frequency in Hz + * param dutyCyclePercent PWM pulse width, value should be between 0 to 100 + * 0=inactive signal(0% duty cycle)... + * 100=active signal (100% duty cycle) + * param outputPolarity true: invert polarity of the output signal, false: no inversion + * param srcClock_Hz Main counter clock in Hz. + * + * return Returns an error if there was error setting up the signal. + */ +status_t QTMR_SetupPwm(TMR_Type *base, + qtmr_channel_selection_t channel, + uint32_t pwmFreqHz, + uint8_t dutyCyclePercent, + bool outputPolarity, + uint32_t srcClock_Hz) { uint32_t periodCount, highCount, lowCount, reg; @@ -164,10 +219,22 @@ status_t QTMR_SetupPwm( */ reg |= (TMR_CTRL_LENGTH_MASK | TMR_CTRL_OUTMODE(kQTMR_ToggleOnAltCompareReg)); base->CHANNEL[channel].CTRL = reg; - + return kStatus_Success; } +/*! + * brief Allows the user to count the source clock cycles until a capture event arrives. + * + * The count is stored in the capture register. + * + * param base Quad Timer peripheral base address + * param channel Quad Timer channel number + * param capturePin Pin through which we receive the input signal to trigger the capture + * param inputPolarity true: invert polarity of the input signal, false: no inversion + * param reloadOnCapture true: reload the counter when an input capture occurs, false: no reload + * param captureMode Specifies which edge of the input signal triggers a capture + */ void QTMR_SetupInputCapture(TMR_Type *base, qtmr_channel_selection_t channel, qtmr_input_source_t capturePin, @@ -201,6 +268,14 @@ void QTMR_SetupInputCapture(TMR_Type *base, } } +/*! + * brief Enables the selected Quad Timer interrupts + * + * param base Quad Timer peripheral base address + * param channel Quad Timer channel number + * param mask The interrupts to enable. This is a logical OR of members of the + * enumeration ::qtmr_interrupt_enable_t + */ void QTMR_EnableInterrupts(TMR_Type *base, qtmr_channel_selection_t channel, uint32_t mask) { uint16_t reg; @@ -239,6 +314,14 @@ void QTMR_EnableInterrupts(TMR_Type *base, qtmr_channel_selection_t channel, uin base->CHANNEL[channel].CSCTRL = reg; } +/*! + * brief Disables the selected Quad Timer interrupts + * + * param base Quad Timer peripheral base addres + * param channel Quad Timer channel number + * param mask The interrupts to enable. This is a logical OR of members of the + * enumeration ::qtmr_interrupt_enable_t + */ void QTMR_DisableInterrupts(TMR_Type *base, qtmr_channel_selection_t channel, uint32_t mask) { uint16_t reg; @@ -275,6 +358,15 @@ void QTMR_DisableInterrupts(TMR_Type *base, qtmr_channel_selection_t channel, ui base->CHANNEL[channel].CSCTRL = reg; } +/*! + * brief Gets the enabled Quad Timer interrupts + * + * param base Quad Timer peripheral base address + * param channel Quad Timer channel number + * + * return The enabled interrupts. This is the logical OR of members of the + * enumeration ::qtmr_interrupt_enable_t + */ uint32_t QTMR_GetEnabledInterrupts(TMR_Type *base, qtmr_channel_selection_t channel) { uint32_t enabledInterrupts = 0; @@ -312,6 +404,15 @@ uint32_t QTMR_GetEnabledInterrupts(TMR_Type *base, qtmr_channel_selection_t chan return enabledInterrupts; } +/*! + * brief Gets the Quad Timer status flags + * + * param base Quad Timer peripheral base address + * param channel Quad Timer channel number + * + * return The status flags. This is the logical OR of members of the + * enumeration ::qtmr_status_flags_t + */ uint32_t QTMR_GetStatus(TMR_Type *base, qtmr_channel_selection_t channel) { uint32_t statusFlags = 0; @@ -349,6 +450,14 @@ uint32_t QTMR_GetStatus(TMR_Type *base, qtmr_channel_selection_t channel) return statusFlags; } +/*! + * brief Clears the Quad Timer status flags. + * + * param base Quad Timer peripheral base address + * param channel Quad Timer channel number + * param mask The status flags to clear. This is a logical OR of members of the + * enumeration ::qtmr_status_flags_t + */ void QTMR_ClearStatusFlags(TMR_Type *base, qtmr_channel_selection_t channel, uint32_t mask) { uint16_t reg; @@ -385,6 +494,22 @@ void QTMR_ClearStatusFlags(TMR_Type *base, qtmr_channel_selection_t channel, uin base->CHANNEL[channel].CSCTRL = reg; } +/*! + * brief Sets the timer period in ticks. + * + * Timers counts from initial value till it equals the count value set here. The counter + * will then reinitialize to the value specified in the Load register. + * + * note + * 1. This function will write the time period in ticks to COMP1 or COMP2 register + * depending on the count direction + * 2. User can call the utility macros provided in fsl_common.h to convert to ticks + * 3. This function supports cases, providing only primary source clock without secondary source clock. + * + * param base Quad Timer peripheral base address + * param channel Quad Timer channel number + * param ticks Timer period in units of ticks + */ void QTMR_SetTimerPeriod(TMR_Type *base, qtmr_channel_selection_t channel, uint16_t ticks) { /* Set the length bit to reinitialize the counters on a match */ @@ -402,6 +527,14 @@ void QTMR_SetTimerPeriod(TMR_Type *base, qtmr_channel_selection_t channel, uint1 } } +/*! + * brief Enable the Quad Timer DMA. + * + * param base Quad Timer peripheral base address + * param channel Quad Timer channel number + * param mask The DMA to enable. This is a logical OR of members of the + * enumeration ::qtmr_dma_enable_t + */ void QTMR_EnableDma(TMR_Type *base, qtmr_channel_selection_t channel, uint32_t mask) { uint16_t reg; @@ -410,7 +543,7 @@ void QTMR_EnableDma(TMR_Type *base, qtmr_channel_selection_t channel, uint32_t m /* Input Edge Flag DMA Enable */ if (mask & kQTMR_InputEdgeFlagDmaEnable) { - /* Restriction: Do not set both DMA[IEFDE] and SCTRL[IEFIE] */ + /* Restriction: Do not set both DMA[IEFDE] and SCTRL[IEFIE] */ base->CHANNEL[channel].SCTRL &= ~TMR_SCTRL_IEFIE_MASK; reg |= TMR_DMA_IEFDE_MASK; } @@ -427,6 +560,14 @@ void QTMR_EnableDma(TMR_Type *base, qtmr_channel_selection_t channel, uint32_t m base->CHANNEL[channel].DMA = reg; } +/*! + * brief Disable the Quad Timer DMA. + * + * param base Quad Timer peripheral base address + * param channel Quad Timer channel number + * param mask The DMA to enable. This is a logical OR of members of the + * enumeration ::qtmr_dma_enable_t + */ void QTMR_DisableDma(TMR_Type *base, qtmr_channel_selection_t channel, uint32_t mask) { uint16_t reg; diff --git a/ext/hal/nxp/mcux/drivers/imx/fsl_rtwdog.c b/ext/hal/nxp/mcux/drivers/imx/fsl_rtwdog.c index 56f70572ada..da3587a55a7 100644 --- a/ext/hal/nxp/mcux/drivers/imx/fsl_rtwdog.c +++ b/ext/hal/nxp/mcux/drivers/imx/fsl_rtwdog.c @@ -1,8 +1,8 @@ /* * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP + * Copyright 2016-2018 NXP * All rights reserved. - * + * * SPDX-License-Identifier: BSD-3-Clause */ @@ -13,11 +13,24 @@ #define FSL_COMPONENT_ID "platform.drivers.rtwdog" #endif - /******************************************************************************* * Code ******************************************************************************/ +/*! + * brief Clears the RTWDOG flag. + * + * This function clears the RTWDOG status flag. + * + * Example to clear an interrupt flag: + * code + * RTWDOG_ClearStatusFlags(wdog_base,kRTWDOG_InterruptFlag); + * endcode + * param base RTWDOG peripheral base address. + * param mask The status flags to clear. + * The parameter can be any combination of the following values: + * arg kRTWDOG_InterruptFlag + */ void RTWDOG_ClearStatusFlags(RTWDOG_Type *base, uint32_t mask) { if (mask & kRTWDOG_InterruptFlag) @@ -26,10 +39,36 @@ void RTWDOG_ClearStatusFlags(RTWDOG_Type *base, uint32_t mask) } } +/*! + * brief Initializes the RTWDOG configuration structure. + * + * This function initializes the RTWDOG configuration structure to default values. The default + * values are: + * code + * rtwdogConfig->enableRtwdog = true; + * rtwdogConfig->clockSource = kRTWDOG_ClockSource1; + * rtwdogConfig->prescaler = kRTWDOG_ClockPrescalerDivide1; + * rtwdogConfig->workMode.enableWait = true; + * rtwdogConfig->workMode.enableStop = false; + * rtwdogConfig->workMode.enableDebug = false; + * rtwdogConfig->testMode = kRTWDOG_TestModeDisabled; + * rtwdogConfig->enableUpdate = true; + * rtwdogConfig->enableInterrupt = false; + * rtwdogConfig->enableWindowMode = false; + * rtwdogConfig->windowValue = 0U; + * rtwdogConfig->timeoutValue = 0xFFFFU; + * endcode + * + * param config Pointer to the RTWDOG configuration structure. + * see rtwdog_config_t + */ void RTWDOG_GetDefaultConfig(rtwdog_config_t *config) { assert(config); + /* Initializes the configure structure to zero. */ + memset(config, 0, sizeof(*config)); + config->enableRtwdog = true; config->clockSource = kRTWDOG_ClockSource1; config->prescaler = kRTWDOG_ClockPrescalerDivide1; @@ -44,18 +83,37 @@ void RTWDOG_GetDefaultConfig(rtwdog_config_t *config) config->timeoutValue = 0xFFFFU; } +/*! + * brief Initializes the RTWDOG module. + * + * This function initializes the RTWDOG. + * To reconfigure the RTWDOG without forcing a reset first, enableUpdate must be set to true + * in the configuration. + * + * Example: + * code + * rtwdog_config_t config; + * RTWDOG_GetDefaultConfig(&config); + * config.timeoutValue = 0x7ffU; + * config.enableUpdate = true; + * RTWDOG_Init(wdog_base,&config); + * endcode + * + * param base RTWDOG peripheral base address. + * param config The configuration of the RTWDOG. + */ void RTWDOG_Init(RTWDOG_Type *base, const rtwdog_config_t *config) { assert(config); uint32_t value = 0U; uint32_t primaskValue = 0U; - - value = RTWDOG_CS_EN(config->enableRtwdog) | RTWDOG_CS_CLK(config->clockSource) | RTWDOG_CS_INT(config->enableInterrupt) | - RTWDOG_CS_WIN(config->enableWindowMode) | RTWDOG_CS_UPDATE(config->enableUpdate) | - RTWDOG_CS_DBG(config->workMode.enableDebug) | RTWDOG_CS_STOP(config->workMode.enableStop) | - RTWDOG_CS_WAIT(config->workMode.enableWait) | RTWDOG_CS_PRES(config->prescaler) | RTWDOG_CS_CMD32EN(true) | - RTWDOG_CS_TST(config->testMode); + + value = RTWDOG_CS_EN(config->enableRtwdog) | RTWDOG_CS_CLK(config->clockSource) | + RTWDOG_CS_INT(config->enableInterrupt) | RTWDOG_CS_WIN(config->enableWindowMode) | + RTWDOG_CS_UPDATE(config->enableUpdate) | RTWDOG_CS_DBG(config->workMode.enableDebug) | + RTWDOG_CS_STOP(config->workMode.enableStop) | RTWDOG_CS_WAIT(config->workMode.enableWait) | + RTWDOG_CS_PRES(config->prescaler) | RTWDOG_CS_CMD32EN(true) | RTWDOG_CS_TST(config->testMode); /* Disable the global interrupts. Otherwise, an interrupt could effectively invalidate the unlock sequence * and the WCT may expire. After the configuration finishes, re-enable the global interrupts. */ @@ -64,9 +122,20 @@ void RTWDOG_Init(RTWDOG_Type *base, const rtwdog_config_t *config) base->WIN = config->windowValue; base->TOVAL = config->timeoutValue; base->CS = value; + while ((base->CS & RTWDOG_CS_RCS_MASK) == 0) + { + } EnableGlobalIRQ(primaskValue); } +/*! + * brief De-initializes the RTWDOG module. + * + * This function shuts down the RTWDOG. + * Ensure that the WDOG_CS.UPDATE is 1, which means that the register update is enabled. + * + * param base RTWDOG peripheral base address. + */ void RTWDOG_Deinit(RTWDOG_Type *base) { uint32_t primaskValue = 0U; diff --git a/ext/hal/nxp/mcux/drivers/imx/fsl_rtwdog.h b/ext/hal/nxp/mcux/drivers/imx/fsl_rtwdog.h index 333ac7761b8..42c5eb78782 100644 --- a/ext/hal/nxp/mcux/drivers/imx/fsl_rtwdog.h +++ b/ext/hal/nxp/mcux/drivers/imx/fsl_rtwdog.h @@ -1,8 +1,8 @@ /* * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP + * Copyright 2016-2018 NXP * All rights reserved. - * + * * SPDX-License-Identifier: BSD-3-Clause */ #ifndef _FSL_RTWDOG_H_ @@ -15,25 +15,24 @@ * @{ */ - /******************************************************************************* * Definitions *******************************************************************************/ /*! @name Unlock sequence */ /*@{*/ -#define WDOG_FIRST_WORD_OF_UNLOCK (RTWDOG_UPDATE_KEY & 0xFFFFU) /*!< First word of unlock sequence */ -#define WDOG_SECOND_WORD_OF_UNLOCK ((RTWDOG_UPDATE_KEY >> 16U)& 0xFFFFU) /*!< Second word of unlock sequence */ +#define WDOG_FIRST_WORD_OF_UNLOCK (RTWDOG_UPDATE_KEY & 0xFFFFU) /*!< First word of unlock sequence */ +#define WDOG_SECOND_WORD_OF_UNLOCK ((RTWDOG_UPDATE_KEY >> 16U) & 0xFFFFU) /*!< Second word of unlock sequence */ /*@}*/ /*! @name Refresh sequence */ /*@{*/ -#define WDOG_FIRST_WORD_OF_REFRESH (RTWDOG_REFRESH_KEY & 0xFFFFU) /*!< First word of refresh sequence */ -#define WDOG_SECOND_WORD_OF_REFRESH ((RTWDOG_REFRESH_KEY >> 16U)& 0xFFFFU) /*!< Second word of refresh sequence */ +#define WDOG_FIRST_WORD_OF_REFRESH (RTWDOG_REFRESH_KEY & 0xFFFFU) /*!< First word of refresh sequence */ +#define WDOG_SECOND_WORD_OF_REFRESH ((RTWDOG_REFRESH_KEY >> 16U) & 0xFFFFU) /*!< Second word of refresh sequence */ /*@}*/ /*! @name Driver version */ /*@{*/ -/*! @brief RTWDOG driver version 2.0.0. */ -#define FSL_RTWDOG_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) +/*! @brief RTWDOG driver version 2.0.1. */ +#define FSL_RTWDOG_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) /*@}*/ /*! @brief Describes RTWDOG clock source. */ @@ -331,6 +330,9 @@ static inline void RTWDOG_Unlock(RTWDOG_Type *base) base->CNT = WDOG_FIRST_WORD_OF_UNLOCK; base->CNT = WDOG_SECOND_WORD_OF_UNLOCK; } + while ((base->CS & RTWDOG_CS_ULK_MASK) == 0) + { + } } /*! @@ -343,6 +345,8 @@ static inline void RTWDOG_Unlock(RTWDOG_Type *base) */ static inline void RTWDOG_Refresh(RTWDOG_Type *base) { + uint32_t primaskValue = 0U; + primaskValue = DisableGlobalIRQ(); if ((base->CS) & RTWDOG_CS_CMD32EN_MASK) { base->CNT = RTWDOG_REFRESH_KEY; @@ -352,6 +356,7 @@ static inline void RTWDOG_Refresh(RTWDOG_Type *base) base->CNT = WDOG_FIRST_WORD_OF_REFRESH; base->CNT = WDOG_SECOND_WORD_OF_REFRESH; } + EnableGlobalIRQ(primaskValue); } /*! diff --git a/ext/hal/nxp/mcux/drivers/imx/fsl_sai.c b/ext/hal/nxp/mcux/drivers/imx/fsl_sai.c index 9739f537798..19cd7e49893 100644 --- a/ext/hal/nxp/mcux/drivers/imx/fsl_sai.c +++ b/ext/hal/nxp/mcux/drivers/imx/fsl_sai.c @@ -58,23 +58,39 @@ static uint32_t SAI_GetInstance(I2S_Type *base); * @brief sends a piece of data in non-blocking way. * * @param base SAI base pointer - * @param channel Data channel used. + * @param channel start channel number. + * @param channelMask enabled channels mask. + * @param endChannel end channel numbers. * @param bitWidth How many bits in a audio word, usually 8/16/24/32 bits. * @param buffer Pointer to the data to be written. * @param size Bytes to be written. */ -static void SAI_WriteNonBlocking(I2S_Type *base, uint32_t channel, uint32_t bitWidth, uint8_t *buffer, uint32_t size); +static void SAI_WriteNonBlocking(I2S_Type *base, + uint32_t channel, + uint32_t channelMask, + uint32_t endChannel, + uint32_t bitWidth, + uint8_t *buffer, + uint32_t size); /*! * @brief Receive a piece of data in non-blocking way. * * @param base SAI base pointer - * @param channel Data channel used. + * @param channel start channel number. + * @param channelMask enabled channels mask. + * @param endChannel end channel numbers. * @param bitWidth How many bits in a audio word, usually 8/16/24/32 bits. * @param buffer Pointer to the data to be read. * @param size Bytes to be read. */ -static void SAI_ReadNonBlocking(I2S_Type *base, uint32_t channel, uint32_t bitWidth, uint8_t *buffer, uint32_t size); +static void SAI_ReadNonBlocking(I2S_Type *base, + uint32_t channel, + uint32_t channelMask, + uint32_t endChannel, + uint32_t bitWidth, + uint8_t *buffer, + uint32_t size); /******************************************************************************* * Variables ******************************************************************************/ @@ -179,45 +195,83 @@ static uint32_t SAI_GetInstance(I2S_Type *base) return instance; } -static void SAI_WriteNonBlocking(I2S_Type *base, uint32_t channel, uint32_t bitWidth, uint8_t *buffer, uint32_t size) +static void SAI_WriteNonBlocking(I2S_Type *base, + uint32_t channel, + uint32_t channelMask, + uint32_t endChannel, + uint32_t bitWidth, + uint8_t *buffer, + uint32_t size) { uint32_t i = 0; - uint8_t j = 0; + uint8_t j = 0, m = 0; uint8_t bytesPerWord = bitWidth / 8U; uint32_t data = 0; uint32_t temp = 0; for (i = 0; i < size / bytesPerWord; i++) { - for (j = 0; j < bytesPerWord; j++) + for (j = channel; j <= endChannel; j++) { - temp = (uint32_t)(*buffer); - data |= (temp << (8U * j)); - buffer++; + if ((1U << j) & channelMask) + { + for (m = 0; m < bytesPerWord; m++) + { + temp = (uint32_t)(*buffer); + data |= (temp << (8U * m)); + buffer++; + } + base->TDR[j] = data; + data = 0; + } } - base->TDR[channel] = data; - data = 0; } } -static void SAI_ReadNonBlocking(I2S_Type *base, uint32_t channel, uint32_t bitWidth, uint8_t *buffer, uint32_t size) +static void SAI_ReadNonBlocking(I2S_Type *base, + uint32_t channel, + uint32_t channelMask, + uint32_t endChannel, + uint32_t bitWidth, + uint8_t *buffer, + uint32_t size) { uint32_t i = 0; - uint8_t j = 0; + uint8_t j = 0, m = 0; uint8_t bytesPerWord = bitWidth / 8U; uint32_t data = 0; for (i = 0; i < size / bytesPerWord; i++) { - data = base->RDR[channel]; - for (j = 0; j < bytesPerWord; j++) + for (j = channel; j <= endChannel; j++) { - *buffer = (data >> (8U * j)) & 0xFF; - buffer++; + if ((1U << j) & channelMask) + { + data = base->RDR[j]; + for (m = 0; m < bytesPerWord; m++) + { + *buffer = (data >> (8U * m)) & 0xFF; + buffer++; + } + } } } } +/*! + * brief Initializes the SAI Tx peripheral. + * + * Ungates the SAI clock, resets the module, and configures SAI Tx with a configuration structure. + * The configuration structure can be custom filled or set with default values by + * SAI_TxGetDefaultConfig(). + * + * note This API should be called at the beginning of the application to use + * the SAI driver. Otherwise, accessing the SAIM module can cause a hard fault + * because the clock is not enabled. + * + * param base SAI base pointer + * param config SAI configuration structure. +*/ void SAI_TxInit(I2S_Type *base, const sai_config_t *config) { uint32_t val = 0; @@ -228,8 +282,7 @@ void SAI_TxInit(I2S_Type *base, const sai_config_t *config) #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ #if defined(FSL_FEATURE_SAI_HAS_MCR) && (FSL_FEATURE_SAI_HAS_MCR) - -#if defined(FSL_FEATURE_SAI_HAS_MCR_MICS) && (FSL_FEATURE_SAI_HAS_MCR_MICS) +#if !(defined(FSL_FEATURE_SAI_HAS_NO_MCR_MICS) && (FSL_FEATURE_SAI_HAS_NO_MCR_MICS)) /* Master clock source setting */ val = (base->MCR & ~I2S_MCR_MICS_MASK); base->MCR = (val | I2S_MCR_MICS(config->mclkSource)); @@ -331,6 +384,20 @@ void SAI_TxInit(I2S_Type *base, const sai_config_t *config) #endif /* FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR */ } +/*! + * brief Initializes the SAI Rx peripheral. + * + * Ungates the SAI clock, resets the module, and configures the SAI Rx with a configuration structure. + * The configuration structure can be custom filled or set with default values by + * SAI_RxGetDefaultConfig(). + * + * note This API should be called at the beginning of the application to use + * the SAI driver. Otherwise, accessing the SAI module can cause a hard fault + * because the clock is not enabled. + * + * param base SAI base pointer + * param config SAI configuration structure. + */ void SAI_RxInit(I2S_Type *base, const sai_config_t *config) { uint32_t val = 0; @@ -341,8 +408,7 @@ void SAI_RxInit(I2S_Type *base, const sai_config_t *config) #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ #if defined(FSL_FEATURE_SAI_HAS_MCR) && (FSL_FEATURE_SAI_HAS_MCR) - -#if defined(FSL_FEATURE_SAI_HAS_MCR_MICS) && (FSL_FEATURE_SAI_HAS_MCR_MICS) +#if !(defined(FSL_FEATURE_SAI_HAS_NO_MCR_MICS) && (FSL_FEATURE_SAI_HAS_NO_MCR_MICS)) /* Master clock source setting */ val = (base->MCR & ~I2S_MCR_MICS_MASK); base->MCR = (val | I2S_MCR_MICS(config->mclkSource)); @@ -444,6 +510,14 @@ void SAI_RxInit(I2S_Type *base, const sai_config_t *config) #endif /* FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR */ } +/*! + * brief De-initializes the SAI peripheral. + * + * This API gates the SAI clock. The SAI module can't operate unless SAI_TxInit + * or SAI_RxInit is called to enable the clock. + * + * param base SAI base pointer +*/ void SAI_Deinit(I2S_Type *base) { SAI_TxEnable(base, false); @@ -453,30 +527,75 @@ void SAI_Deinit(I2S_Type *base) #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ } +/*! + * brief Sets the SAI Tx configuration structure to default values. + * + * This API initializes the configuration structure for use in SAI_TxConfig(). + * The initialized structure can remain unchanged in SAI_TxConfig(), or it can be modified + * before calling SAI_TxConfig(). + * This is an example. + code + sai_config_t config; + SAI_TxGetDefaultConfig(&config); + endcode + * + * param config pointer to master configuration structure + */ void SAI_TxGetDefaultConfig(sai_config_t *config) { + /* Initializes the configure structure to zero. */ + memset(config, 0, sizeof(*config)); + config->bclkSource = kSAI_BclkSourceMclkDiv; config->masterSlave = kSAI_Master; +#if defined(FSL_FEATURE_SAI_HAS_MCR) && (FSL_FEATURE_SAI_HAS_MCR) + config->mclkOutputEnable = true; +#if !(defined(FSL_FEATURE_SAI_HAS_NO_MCR_MICS) && (FSL_FEATURE_SAI_HAS_NO_MCR_MICS)) config->mclkSource = kSAI_MclkSourceSysclk; +#endif +#endif /* FSL_FEATURE_SAI_HAS_MCR */ config->protocol = kSAI_BusI2S; config->syncMode = kSAI_ModeAsync; -#if defined(FSL_FEATURE_SAI_HAS_MCR) && (FSL_FEATURE_SAI_HAS_MCR) - config->mclkOutputEnable = true; -#endif /* FSL_FEATURE_SAI_HAS_MCR */ } +/*! + * brief Sets the SAI Rx configuration structure to default values. + * + * This API initializes the configuration structure for use in SAI_RxConfig(). + * The initialized structure can remain unchanged in SAI_RxConfig() or it can be modified + * before calling SAI_RxConfig(). + * This is an example. + code + sai_config_t config; + SAI_RxGetDefaultConfig(&config); + endcode + * + * param config pointer to master configuration structure + */ void SAI_RxGetDefaultConfig(sai_config_t *config) { + /* Initializes the configure structure to zero. */ + memset(config, 0, sizeof(*config)); + config->bclkSource = kSAI_BclkSourceMclkDiv; config->masterSlave = kSAI_Master; - config->mclkSource = kSAI_MclkSourceSysclk; - config->protocol = kSAI_BusI2S; - config->syncMode = kSAI_ModeSync; #if defined(FSL_FEATURE_SAI_HAS_MCR) && (FSL_FEATURE_SAI_HAS_MCR) config->mclkOutputEnable = true; +#if !(defined(FSL_FEATURE_SAI_HAS_NO_MCR_MICS) && (FSL_FEATURE_SAI_HAS_NO_MCR_MICS)) + config->mclkSource = kSAI_MclkSourceSysclk; +#endif #endif /* FSL_FEATURE_SAI_HAS_MCR */ + config->protocol = kSAI_BusI2S; + config->syncMode = kSAI_ModeSync; } +/*! + * brief Resets the SAI Tx. + * + * This function enables the software reset and FIFO reset of SAI Tx. After reset, clear the reset bit. + * + * param base SAI base pointer + */ void SAI_TxReset(I2S_Type *base) { /* Set the software reset and FIFO reset to clear internal state */ @@ -493,6 +612,13 @@ void SAI_TxReset(I2S_Type *base) base->TMR = 0; } +/*! + * brief Resets the SAI Rx. + * + * This function enables the software reset and FIFO reset of SAI Rx. After reset, clear the reset bit. + * + * param base SAI base pointer + */ void SAI_RxReset(I2S_Type *base) { /* Set the software reset and FIFO reset to clear internal state */ @@ -509,6 +635,12 @@ void SAI_RxReset(I2S_Type *base) base->RMR = 0; } +/*! + * brief Enables/disables the SAI Tx. + * + * param base SAI base pointer + * param enable True means enable SAI Tx, false means disable. + */ void SAI_TxEnable(I2S_Type *base, bool enable) { if (enable) @@ -533,6 +665,12 @@ void SAI_TxEnable(I2S_Type *base, bool enable) } } +/*! + * brief Enables/disables the SAI Rx. + * + * param base SAI base pointer + * param enable True means enable SAI Rx, false means disable. + */ void SAI_RxEnable(I2S_Type *base, bool enable) { if (enable) @@ -556,6 +694,17 @@ void SAI_RxEnable(I2S_Type *base, bool enable) } } +/*! + * brief Do software reset or FIFO reset . + * + * FIFO reset means clear all the data in the FIFO, and make the FIFO pointer both to 0. + * Software reset means claer the Tx internal logic, including the bit clock, frame count etc. But software + * reset will not clear any configuration registers like TCR1~TCR5. + * This function will also clear all the error flags such as FIFO error, sync error etc. + * + * param base SAI base pointer + * param type Reset type, FIFO reset or software reset + */ void SAI_TxSoftwareReset(I2S_Type *base, sai_reset_type_t type) { base->TCSR |= (uint32_t)type; @@ -564,6 +713,17 @@ void SAI_TxSoftwareReset(I2S_Type *base, sai_reset_type_t type) base->TCSR &= ~I2S_TCSR_SR_MASK; } +/*! + * brief Do software reset or FIFO reset . + * + * FIFO reset means clear all the data in the FIFO, and make the FIFO pointer both to 0. + * Software reset means claer the Rx internal logic, including the bit clock, frame count etc. But software + * reset will not clear any configuration registers like RCR1~RCR5. + * This function will also clear all the error flags such as FIFO error, sync error etc. + * + * param base SAI base pointer + * param type Reset type, FIFO reset or software reset + */ void SAI_RxSoftwareReset(I2S_Type *base, sai_reset_type_t type) { base->RCSR |= (uint32_t)type; @@ -572,18 +732,38 @@ void SAI_RxSoftwareReset(I2S_Type *base, sai_reset_type_t type) base->RCSR &= ~I2S_RCSR_SR_MASK; } +/*! + * brief Set the Tx channel FIFO enable mask. + * + * param base SAI base pointer + * param mask Channel enable mask, 0 means all channel FIFO disabled, 1 means channel 0 enabled, + * 3 means both channel 0 and channel 1 enabled. + */ void SAI_TxSetChannelFIFOMask(I2S_Type *base, uint8_t mask) { base->TCR3 &= ~I2S_TCR3_TCE_MASK; base->TCR3 |= I2S_TCR3_TCE(mask); } +/*! + * brief Set the Rx channel FIFO enable mask. + * + * param base SAI base pointer + * param mask Channel enable mask, 0 means all channel FIFO disabled, 1 means channel 0 enabled, + * 3 means both channel 0 and channel 1 enabled. + */ void SAI_RxSetChannelFIFOMask(I2S_Type *base, uint8_t mask) { base->RCR3 &= ~I2S_RCR3_RCE_MASK; base->RCR3 |= I2S_RCR3_RCE(mask); } +/*! + * brief Set the Tx data order. + * + * param base SAI base pointer + * param order Data order MSB or LSB + */ void SAI_TxSetDataOrder(I2S_Type *base, sai_data_order_t order) { uint32_t val = (base->TCR4) & (~I2S_TCR4_MF_MASK); @@ -592,6 +772,12 @@ void SAI_TxSetDataOrder(I2S_Type *base, sai_data_order_t order) base->TCR4 = val; } +/*! + * brief Set the Rx data order. + * + * param base SAI base pointer + * param order Data order MSB or LSB + */ void SAI_RxSetDataOrder(I2S_Type *base, sai_data_order_t order) { uint32_t val = (base->RCR4) & (~I2S_RCR4_MF_MASK); @@ -600,6 +786,12 @@ void SAI_RxSetDataOrder(I2S_Type *base, sai_data_order_t order) base->RCR4 = val; } +/*! + * brief Set the Tx data order. + * + * param base SAI base pointer + * param order Data order MSB or LSB + */ void SAI_TxSetBitClockPolarity(I2S_Type *base, sai_clock_polarity_t polarity) { uint32_t val = (base->TCR2) & (~I2S_TCR2_BCP_MASK); @@ -608,6 +800,12 @@ void SAI_TxSetBitClockPolarity(I2S_Type *base, sai_clock_polarity_t polarity) base->TCR2 = val; } +/*! + * brief Set the Rx data order. + * + * param base SAI base pointer + * param order Data order MSB or LSB + */ void SAI_RxSetBitClockPolarity(I2S_Type *base, sai_clock_polarity_t polarity) { uint32_t val = (base->RCR2) & (~I2S_RCR2_BCP_MASK); @@ -616,6 +814,12 @@ void SAI_RxSetBitClockPolarity(I2S_Type *base, sai_clock_polarity_t polarity) base->RCR2 = val; } +/*! + * brief Set the Tx data order. + * + * param base SAI base pointer + * param order Data order MSB or LSB + */ void SAI_TxSetFrameSyncPolarity(I2S_Type *base, sai_clock_polarity_t polarity) { uint32_t val = (base->TCR4) & (~I2S_TCR4_FSP_MASK); @@ -624,6 +828,12 @@ void SAI_TxSetFrameSyncPolarity(I2S_Type *base, sai_clock_polarity_t polarity) base->TCR4 = val; } +/*! + * brief Set the Rx data order. + * + * param base SAI base pointer + * param order Data order MSB or LSB + */ void SAI_RxSetFrameSyncPolarity(I2S_Type *base, sai_clock_polarity_t polarity) { uint32_t val = (base->RCR4) & (~I2S_RCR4_FSP_MASK); @@ -633,6 +843,12 @@ void SAI_RxSetFrameSyncPolarity(I2S_Type *base, sai_clock_polarity_t polarity) } #if defined(FSL_FEATURE_SAI_HAS_FIFO_PACKING) && FSL_FEATURE_SAI_HAS_FIFO_PACKING +/*! + * brief Set Tx FIFO packing feature. + * + * param base SAI base pointer. + * param pack FIFO pack type. It is element of sai_fifo_packing_t. + */ void SAI_TxSetFIFOPacking(I2S_Type *base, sai_fifo_packing_t pack) { uint32_t val = base->TCR4; @@ -642,6 +858,12 @@ void SAI_TxSetFIFOPacking(I2S_Type *base, sai_fifo_packing_t pack) base->TCR4 = val; } +/*! +* brief Set Rx FIFO packing feature. +* +* param base SAI base pointer. +* param pack FIFO pack type. It is element of sai_fifo_packing_t. +*/ void SAI_RxSetFIFOPacking(I2S_Type *base, sai_fifo_packing_t pack) { uint32_t val = base->RCR4; @@ -652,6 +874,18 @@ void SAI_RxSetFIFOPacking(I2S_Type *base, sai_fifo_packing_t pack) } #endif /* FSL_FEATURE_SAI_HAS_FIFO_PACKING */ +/*! + * brief Configures the SAI Tx audio format. + * + * The audio format can be changed at run-time. This function configures the sample rate and audio data + * format to be transferred. + * + * param base SAI base pointer. + * param format Pointer to the SAI audio data format structure. + * param mclkSourceClockHz SAI master clock source frequency in Hz. + * param bclkSourceClockHz SAI bit clock source frequency in Hz. If the bit clock source is a master + * clock, this value should equal the masterClockHz. +*/ void SAI_TxSetFormat(I2S_Type *base, sai_transfer_format_t *format, uint32_t mclkSourceClockHz, @@ -659,16 +893,12 @@ void SAI_TxSetFormat(I2S_Type *base, { uint32_t bclk = 0; uint32_t val = 0; - uint32_t channels = 2U; - - if (format->stereo != kSAI_Stereo) - { - channels = 1U; - } + uint32_t i = 0U; + uint32_t divider = 0U, channelNums = 0U; if (format->isFrameSyncCompact) { - bclk = format->sampleRate_Hz * format->bitWidth * channels; + bclk = format->sampleRate_Hz * format->bitWidth * (format->stereo == kSAI_Stereo ? 2U : 1U); val = (base->TCR4 & (~I2S_TCR4_SYWD_MASK)); val |= I2S_TCR4_SYWD(format->bitWidth - 1U); base->TCR4 = val; @@ -691,7 +921,30 @@ void SAI_TxSetFormat(I2S_Type *base, if (base->TCR2 & I2S_TCR2_BCD_MASK) { base->TCR2 &= ~I2S_TCR2_DIV_MASK; - base->TCR2 |= I2S_TCR2_DIV((bclkSourceClockHz / bclk) / 2U - 1U); + /* need to check the divided bclk, if bigger than target, then divider need to re-calculate. */ + divider = bclkSourceClockHz / bclk; + /* for the condition where the source clock is smaller than target bclk */ + if (divider == 0U) + { + divider++; + } + /* recheck the divider if properly or not, to make sure output blck not bigger than target*/ + if ((bclkSourceClockHz / divider) > bclk) + { + divider++; + } + +#if defined(FSL_FEATURE_SAI_HAS_BCLK_BYPASS) && (FSL_FEATURE_SAI_HAS_BCLK_BYPASS) + /* if bclk same with MCLK, bypass the divider */ + if (divider == 1U) + { + base->TCR2 |= I2S_TCR2_BYP_MASK; + } + else +#endif + { + base->TCR2 |= I2S_TCR2_DIV(divider / 2U - 1U); + } } /* Set bitWidth */ @@ -715,9 +968,41 @@ void SAI_TxSetFormat(I2S_Type *base, /* Set mono or stereo */ base->TMR = (uint32_t)format->stereo; + /* if channel mask is not set, then format->channel must be set, + use it to get channel mask value */ + if (format->channelMask == 0U) + { + format->channelMask = 1U << format->channel; + } + + /* if channel nums is not set, calculate it here according to channelMask*/ + for (i = 0U; i < FSL_FEATURE_SAI_CHANNEL_COUNT; i++) + { + if (((uint32_t)1 << i) & format->channelMask) + { + /* geet start channel number when channelNums = 0 only */ + if (channelNums == 0U) + { + format->channel = i; + } + channelNums++; + format->endChannel = i; + } + } + format->channelNums = channelNums; + assert(format->channelNums <= FSL_FEATURE_SAI_CHANNEL_COUNT); + +#if defined(FSL_FEATURE_SAI_HAS_FIFO_COMBINE_MODE) && (FSL_FEATURE_SAI_HAS_FIFO_COMBINE_MODE) + /* make sure combine mode disabled while multipe channel is used */ + if (format->channelNums > 1U) + { + base->TCR4 &= ~I2S_TCR4_FCOMB_MASK; + } +#endif + /* Set data channel */ base->TCR3 &= ~I2S_TCR3_TCE_MASK; - base->TCR3 |= I2S_TCR3_TCE(1U << format->channel); + base->TCR3 |= I2S_TCR3_TCE(format->channelMask); #if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) /* Set watermark */ @@ -725,6 +1010,18 @@ void SAI_TxSetFormat(I2S_Type *base, #endif /* FSL_FEATURE_SAI_FIFO_COUNT */ } +/*! + * brief Configures the SAI Rx audio format. + * + * The audio format can be changed at run-time. This function configures the sample rate and audio data + * format to be transferred. + * + * param base SAI base pointer. + * param format Pointer to the SAI audio data format structure. + * param mclkSourceClockHz SAI master clock source frequency in Hz. + * param bclkSourceClockHz SAI bit clock source frequency in Hz. If the bit clock source is a master + * clock, this value should equal the masterClockHz. +*/ void SAI_RxSetFormat(I2S_Type *base, sai_transfer_format_t *format, uint32_t mclkSourceClockHz, @@ -732,16 +1029,12 @@ void SAI_RxSetFormat(I2S_Type *base, { uint32_t bclk = 0; uint32_t val = 0; - uint32_t channels = 2U; - - if (format->stereo != kSAI_Stereo) - { - channels = 1U; - } + uint32_t i = 0U; + uint32_t divider = 0U, channelNums = 0U; if (format->isFrameSyncCompact) { - bclk = format->sampleRate_Hz * format->bitWidth * channels; + bclk = format->sampleRate_Hz * format->bitWidth * (format->stereo == kSAI_Stereo ? 2U : 1U); val = (base->RCR4 & (~I2S_RCR4_SYWD_MASK)); val |= I2S_RCR4_SYWD(format->bitWidth - 1U); base->RCR4 = val; @@ -764,7 +1057,29 @@ void SAI_RxSetFormat(I2S_Type *base, if (base->RCR2 & I2S_RCR2_BCD_MASK) { base->RCR2 &= ~I2S_RCR2_DIV_MASK; - base->RCR2 |= I2S_RCR2_DIV((bclkSourceClockHz / bclk) / 2U - 1U); + /* need to check the divided bclk, if bigger than target, then divider need to re-calculate. */ + divider = bclkSourceClockHz / bclk; + /* for the condition where the source clock is smaller than target bclk */ + if (divider == 0U) + { + divider++; + } + /* recheck the divider if properly or not, to make sure output blck not bigger than target*/ + if ((bclkSourceClockHz / divider) > bclk) + { + divider++; + } +#if defined(FSL_FEATURE_SAI_HAS_BCLK_BYPASS) && (FSL_FEATURE_SAI_HAS_BCLK_BYPASS) + /* if bclk same with MCLK, bypass the divider */ + if (divider == 1U) + { + base->RCR2 |= I2S_RCR2_BYP_MASK; + } + else +#endif + { + base->RCR2 |= I2S_RCR2_DIV(divider / 2U - 1U); + } } /* Set bitWidth */ @@ -788,9 +1103,42 @@ void SAI_RxSetFormat(I2S_Type *base, /* Set mono or stereo */ base->RMR = (uint32_t)format->stereo; + /* if channel mask is not set, then format->channel must be set, + use it to get channel mask value */ + if (format->channelMask == 0U) + { + format->channelMask = 1U << format->channel; + } + + /* if channel nums is not set, calculate it here according to channelMask*/ + for (i = 0U; i < FSL_FEATURE_SAI_CHANNEL_COUNT; i++) + { + if (((uint32_t)1 << i) & format->channelMask) + { + /* geet start channel number when channelNums = 0 only */ + if (channelNums == 0U) + { + format->channel = i; + } + channelNums++; + format->endChannel = i; + } + } + format->channelNums = channelNums; + assert(format->channelNums <= FSL_FEATURE_SAI_CHANNEL_COUNT); + +#if defined(FSL_FEATURE_SAI_HAS_FIFO_COMBINE_MODE) && (FSL_FEATURE_SAI_HAS_FIFO_COMBINE_MODE) + /* make sure combine mode disabled while multipe channel is used */ + if (format->channelNums > 1U) + { + base->RCR4 &= ~I2S_RCR4_FCOMB_MASK; + } +#endif + /* Set data channel */ base->RCR3 &= ~I2S_RCR3_RCE_MASK; - base->RCR3 |= I2S_RCR3_RCE(1U << format->channel); + /* enable all the channel */ + base->RCR3 |= I2S_RCR3_RCE(format->channelMask); #if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) /* Set watermark */ @@ -798,10 +1146,24 @@ void SAI_RxSetFormat(I2S_Type *base, #endif /* FSL_FEATURE_SAI_FIFO_COUNT */ } +/*! + * brief Sends data using a blocking method. + * + * note This function blocks by polling until data is ready to be sent. + * + * param base SAI base pointer. + * param channel Data channel used. + * param bitWidth How many bits in an audio word; usually 8/16/24/32 bits. + * param buffer Pointer to the data to be written. + * param size Bytes to be written. + */ void SAI_WriteBlocking(I2S_Type *base, uint32_t channel, uint32_t bitWidth, uint8_t *buffer, uint32_t size) { uint32_t i = 0; uint8_t bytesPerWord = bitWidth / 8U; +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + bytesPerWord = (size_t)((FSL_FEATURE_SAI_FIFO_COUNT - base->TCR1) * bytesPerWord); +#endif while (i < size) { @@ -810,7 +1172,7 @@ void SAI_WriteBlocking(I2S_Type *base, uint32_t channel, uint32_t bitWidth, uint { } - SAI_WriteNonBlocking(base, channel, bitWidth, buffer, bytesPerWord); + SAI_WriteNonBlocking(base, channel, 1U << channel, channel, bitWidth, buffer, bytesPerWord); buffer += bytesPerWord; i += bytesPerWord; } @@ -821,10 +1183,123 @@ void SAI_WriteBlocking(I2S_Type *base, uint32_t channel, uint32_t bitWidth, uint } } +/*! + * brief Sends data to multi channel using a blocking method. + * + * note This function blocks by polling until data is ready to be sent. + * + * param base SAI base pointer. + * param channel Data channel used. + * param channelMask channel mask. + * param bitWidth How many bits in an audio word; usually 8/16/24/32 bits. + * param buffer Pointer to the data to be written. + * param size Bytes to be written. + */ +void SAI_WriteMultiChannelBlocking( + I2S_Type *base, uint32_t channel, uint32_t channelMask, uint32_t bitWidth, uint8_t *buffer, uint32_t size) +{ + uint32_t i = 0, j = 0; + uint8_t bytesPerWord = bitWidth / 8U; + uint32_t channelNums = 0U, endChannel = 0U; + +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + bytesPerWord = (size_t)((FSL_FEATURE_SAI_FIFO_COUNT - base->TCR1) * bytesPerWord); +#endif + + for (i = 0U; (i < FSL_FEATURE_SAI_CHANNEL_COUNT); i++) + { + if ((1U << i) & (channelMask)) + { + channelNums++; + endChannel = i; + } + } + + assert(channelNums <= FSL_FEATURE_SAI_CHANNEL_COUNT); + bytesPerWord *= channelNums; + + while (j < size) + { + /* Wait until it can write data */ + while (!(base->TCSR & I2S_TCSR_FWF_MASK)) + { + } + + SAI_WriteNonBlocking(base, channel, channelMask, endChannel, bitWidth, buffer, bytesPerWord); + buffer += bytesPerWord; + j += bytesPerWord; + } + + /* Wait until the last data is sent */ + while (!(base->TCSR & I2S_TCSR_FWF_MASK)) + { + } +} + +/*! + * brief Receives multi channel data using a blocking method. + * + * note This function blocks by polling until data is ready to be sent. + * + * param base SAI base pointer. + * param channel Data channel used. + * param channelMask channel mask. + * param bitWidth How many bits in an audio word; usually 8/16/24/32 bits. + * param buffer Pointer to the data to be read. + * param size Bytes to be read. + */ +void SAI_ReadMultiChannelBlocking( + I2S_Type *base, uint32_t channel, uint32_t channelMask, uint32_t bitWidth, uint8_t *buffer, uint32_t size) +{ + uint32_t i = 0, j = 0; + uint8_t bytesPerWord = bitWidth / 8U; + uint32_t channelNums = 0U, endChannel = 0U; +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + bytesPerWord = (size_t)(base->RCR1 * bytesPerWord); +#endif + for (i = 0U; (i < FSL_FEATURE_SAI_CHANNEL_COUNT); i++) + { + if ((1U << i) & (channelMask)) + { + channelNums++; + endChannel = i; + } + } + + assert(channelNums <= FSL_FEATURE_SAI_CHANNEL_COUNT); + bytesPerWord *= channelNums; + + while (j < size) + { + /* Wait until data is received */ + while (!(base->RCSR & I2S_RCSR_FWF_MASK)) + { + } + + SAI_ReadNonBlocking(base, channel, channelMask, endChannel, bitWidth, buffer, bytesPerWord); + buffer += bytesPerWord; + j += bytesPerWord; + } +} + +/*! + * brief Receives data using a blocking method. + * + * note This function blocks by polling until data is ready to be sent. + * + * param base SAI base pointer. + * param channel Data channel used. + * param bitWidth How many bits in an audio word; usually 8/16/24/32 bits. + * param buffer Pointer to the data to be read. + * param size Bytes to be read. + */ void SAI_ReadBlocking(I2S_Type *base, uint32_t channel, uint32_t bitWidth, uint8_t *buffer, uint32_t size) { uint32_t i = 0; uint8_t bytesPerWord = bitWidth / 8U; +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + bytesPerWord = (size_t)(base->RCR1 * bytesPerWord); +#endif while (i < size) { @@ -833,12 +1308,23 @@ void SAI_ReadBlocking(I2S_Type *base, uint32_t channel, uint32_t bitWidth, uint8 { } - SAI_ReadNonBlocking(base, channel, bitWidth, buffer, bytesPerWord); + SAI_ReadNonBlocking(base, channel, 1U << channel, channel, bitWidth, buffer, bytesPerWord); buffer += bytesPerWord; i += bytesPerWord; } } +/*! + * brief Initializes the SAI Tx handle. + * + * This function initializes the Tx handle for the SAI Tx transactional APIs. Call + * this function once to get the handle initialized. + * + * param base SAI base pointer + * param handle SAI handle pointer. + * param callback Pointer to the user callback function. + * param userData User parameter passed to the callback function + */ void SAI_TransferTxCreateHandle(I2S_Type *base, sai_handle_t *handle, sai_transfer_callback_t callback, void *userData) { assert(handle); @@ -859,6 +1345,17 @@ void SAI_TransferTxCreateHandle(I2S_Type *base, sai_handle_t *handle, sai_transf EnableIRQ(s_saiTxIRQ[SAI_GetInstance(base)]); } +/*! + * brief Initializes the SAI Rx handle. + * + * This function initializes the Rx handle for the SAI Rx transactional APIs. Call + * this function once to get the handle initialized. + * + * param base SAI base pointer. + * param handle SAI handle pointer. + * param callback Pointer to the user callback function. + * param userData User parameter passed to the callback function. + */ void SAI_TransferRxCreateHandle(I2S_Type *base, sai_handle_t *handle, sai_transfer_callback_t callback, void *userData) { assert(handle); @@ -879,6 +1376,20 @@ void SAI_TransferRxCreateHandle(I2S_Type *base, sai_handle_t *handle, sai_transf EnableIRQ(s_saiRxIRQ[SAI_GetInstance(base)]); } +/*! + * brief Configures the SAI Tx audio format. + * + * The audio format can be changed at run-time. This function configures the sample rate and audio data + * format to be transferred. + * + * param base SAI base pointer. + * param handle SAI handle pointer. + * param format Pointer to the SAI audio data format structure. + * param mclkSourceClockHz SAI master clock source frequency in Hz. + * param bclkSourceClockHz SAI bit clock source frequency in Hz. If a bit clock source is a master + * clock, this value should equal the masterClockHz in format. + * return Status of this function. Return value is the status_t. +*/ status_t SAI_TransferTxSetFormat(I2S_Type *base, sai_handle_t *handle, sai_transfer_format_t *format, @@ -887,7 +1398,11 @@ status_t SAI_TransferTxSetFormat(I2S_Type *base, { assert(handle); - if ((mclkSourceClockHz < format->sampleRate_Hz) || (bclkSourceClockHz < format->sampleRate_Hz)) + if ((bclkSourceClockHz < format->sampleRate_Hz) +#if defined(FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER) && (FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER) + || (mclkSourceClockHz < format->sampleRate_Hz) +#endif + ) { return kStatus_InvalidArgument; } @@ -897,13 +1412,32 @@ status_t SAI_TransferTxSetFormat(I2S_Type *base, #if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) handle->watermark = format->watermark; #endif - handle->channel = format->channel; SAI_TxSetFormat(base, format, mclkSourceClockHz, bclkSourceClockHz); + handle->channel = format->channel; + /* used for multi channel */ + handle->channelMask = format->channelMask; + handle->channelNums = format->channelNums; + handle->endChannel = format->endChannel; + return kStatus_Success; } +/*! + * brief Configures the SAI Rx audio format. + * + * The audio format can be changed at run-time. This function configures the sample rate and audio data + * format to be transferred. + * + * param base SAI base pointer. + * param handle SAI handle pointer. + * param format Pointer to the SAI audio data format structure. + * param mclkSourceClockHz SAI master clock source frequency in Hz. + * param bclkSourceClockHz SAI bit clock source frequency in Hz. If a bit clock source is a master + * clock, this value should equal the masterClockHz in format. + * return Status of this function. Return value is one of status_t. +*/ status_t SAI_TransferRxSetFormat(I2S_Type *base, sai_handle_t *handle, sai_transfer_format_t *format, @@ -912,7 +1446,11 @@ status_t SAI_TransferRxSetFormat(I2S_Type *base, { assert(handle); - if ((mclkSourceClockHz < format->sampleRate_Hz) || (bclkSourceClockHz < format->sampleRate_Hz)) + if ((bclkSourceClockHz < format->sampleRate_Hz) +#if defined(FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER) && (FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER) + || (mclkSourceClockHz < format->sampleRate_Hz) +#endif + ) { return kStatus_InvalidArgument; } @@ -922,13 +1460,33 @@ status_t SAI_TransferRxSetFormat(I2S_Type *base, #if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) handle->watermark = format->watermark; #endif - handle->channel = format->channel; SAI_RxSetFormat(base, format, mclkSourceClockHz, bclkSourceClockHz); + handle->channel = format->channel; + /* used for multi channel */ + handle->channelMask = format->channelMask; + handle->channelNums = format->channelNums; + handle->endChannel = format->endChannel; + return kStatus_Success; } +/*! + * brief Performs an interrupt non-blocking send transfer on SAI. + * + * note This API returns immediately after the transfer initiates. + * Call the SAI_TxGetTransferStatusIRQ to poll the transfer status and check whether + * the transfer is finished. If the return status is not kStatus_SAI_Busy, the transfer + * is finished. + * + * param base SAI base pointer. + * param handle Pointer to the sai_handle_t structure which stores the transfer state. + * param xfer Pointer to the sai_transfer_t structure. + * retval kStatus_Success Successfully started the data receive. + * retval kStatus_SAI_TxBusy Previous receive still not finished. + * retval kStatus_InvalidArgument The input parameter is invalid. + */ status_t SAI_TransferSendNonBlocking(I2S_Type *base, sai_handle_t *handle, sai_transfer_t *xfer) { assert(handle); @@ -962,6 +1520,21 @@ status_t SAI_TransferSendNonBlocking(I2S_Type *base, sai_handle_t *handle, sai_t return kStatus_Success; } +/*! + * brief Performs an interrupt non-blocking receive transfer on SAI. + * + * note This API returns immediately after the transfer initiates. + * Call the SAI_RxGetTransferStatusIRQ to poll the transfer status and check whether + * the transfer is finished. If the return status is not kStatus_SAI_Busy, the transfer + * is finished. + * + * param base SAI base pointer + * param handle Pointer to the sai_handle_t structure which stores the transfer state. + * param xfer Pointer to the sai_transfer_t structure. + * retval kStatus_Success Successfully started the data receive. + * retval kStatus_SAI_RxBusy Previous receive still not finished. + * retval kStatus_InvalidArgument The input parameter is invalid. + */ status_t SAI_TransferReceiveNonBlocking(I2S_Type *base, sai_handle_t *handle, sai_transfer_t *xfer) { assert(handle); @@ -995,6 +1568,15 @@ status_t SAI_TransferReceiveNonBlocking(I2S_Type *base, sai_handle_t *handle, sa return kStatus_Success; } +/*! + * brief Gets a set byte count. + * + * param base SAI base pointer. + * param handle Pointer to the sai_handle_t structure which stores the transfer state. + * param count Bytes count sent. + * retval kStatus_Success Succeed get the transfer count. + * retval kStatus_NoTransferInProgress There is not a non-blocking transaction currently in progress. + */ status_t SAI_TransferGetSendCount(I2S_Type *base, sai_handle_t *handle, size_t *count) { assert(handle); @@ -1013,6 +1595,15 @@ status_t SAI_TransferGetSendCount(I2S_Type *base, sai_handle_t *handle, size_t * return status; } +/*! + * brief Gets a received byte count. + * + * param base SAI base pointer. + * param handle Pointer to the sai_handle_t structure which stores the transfer state. + * param count Bytes count received. + * retval kStatus_Success Succeed get the transfer count. + * retval kStatus_NoTransferInProgress There is not a non-blocking transaction currently in progress. + */ status_t SAI_TransferGetReceiveCount(I2S_Type *base, sai_handle_t *handle, size_t *count) { assert(handle); @@ -1031,6 +1622,15 @@ status_t SAI_TransferGetReceiveCount(I2S_Type *base, sai_handle_t *handle, size_ return status; } +/*! + * brief Aborts the current send. + * + * note This API can be called any time when an interrupt non-blocking transfer initiates + * to abort the transfer early. + * + * param base SAI base pointer. + * param handle Pointer to the sai_handle_t structure which stores the transfer state. + */ void SAI_TransferAbortSend(I2S_Type *base, sai_handle_t *handle) { assert(handle); @@ -1052,6 +1652,15 @@ void SAI_TransferAbortSend(I2S_Type *base, sai_handle_t *handle) handle->queueUser = 0; } +/*! + * brief Aborts the current IRQ receive. + * + * note This API can be called when an interrupt non-blocking transfer initiates + * to abort the transfer early. + * + * param base SAI base pointer + * param handle Pointer to the sai_handle_t structure which stores the transfer state. + */ void SAI_TransferAbortReceive(I2S_Type *base, sai_handle_t *handle) { assert(handle); @@ -1073,6 +1682,15 @@ void SAI_TransferAbortReceive(I2S_Type *base, sai_handle_t *handle) handle->queueUser = 0; } +/*! + * brief Terminate all SAI send. + * + * This function will clear all transfer slots buffered in the sai queue. If users only want to abort the + * current transfer slot, please call SAI_TransferAbortSend. + * + * param base SAI base pointer. + * param handle SAI eDMA handle pointer. + */ void SAI_TransferTerminateSend(I2S_Type *base, sai_handle_t *handle) { assert(handle); @@ -1087,6 +1705,15 @@ void SAI_TransferTerminateSend(I2S_Type *base, sai_handle_t *handle) handle->queueDriver = 0U; } +/*! + * brief Terminate all SAI receive. + * + * This function will clear all transfer slots buffered in the sai queue. If users only want to abort the + * current transfer slot, please call SAI_TransferAbortReceive. + * + * param base SAI base pointer. + * param handle SAI eDMA handle pointer. + */ void SAI_TransferTerminateReceive(I2S_Type *base, sai_handle_t *handle) { assert(handle); @@ -1101,12 +1728,18 @@ void SAI_TransferTerminateReceive(I2S_Type *base, sai_handle_t *handle) handle->queueDriver = 0U; } +/*! + * brief Tx interrupt handler. + * + * param base SAI base pointer. + * param handle Pointer to the sai_handle_t structure. + */ void SAI_TransferTxHandleIRQ(I2S_Type *base, sai_handle_t *handle) { assert(handle); uint8_t *buffer = handle->saiQueue[handle->queueDriver].data; - uint8_t dataSize = handle->bitWidth / 8U; + uint8_t dataSize = (handle->bitWidth / 8U) * handle->channelNums; /* Handle Error */ if (base->TCSR & I2S_TCSR_FEF_MASK) @@ -1133,7 +1766,8 @@ void SAI_TransferTxHandleIRQ(I2S_Type *base, sai_handle_t *handle) (size_t)((FSL_FEATURE_SAI_FIFO_COUNT - handle->watermark) * dataSize)); /* Copy the data from sai buffer to FIFO */ - SAI_WriteNonBlocking(base, handle->channel, handle->bitWidth, buffer, size); + SAI_WriteNonBlocking(base, handle->channel, handle->channelMask, handle->endChannel, handle->bitWidth, buffer, + size); /* Update the internal counter */ handle->saiQueue[handle->queueDriver].dataSize -= size; @@ -1144,7 +1778,8 @@ void SAI_TransferTxHandleIRQ(I2S_Type *base, sai_handle_t *handle) { uint8_t size = MIN((handle->saiQueue[handle->queueDriver].dataSize), dataSize); - SAI_WriteNonBlocking(base, handle->channel, handle->bitWidth, buffer, size); + SAI_WriteNonBlocking(base, handle->channel, handle->channelMask, handle->endChannel, handle->bitWidth, buffer, + size); /* Update internal counter */ handle->saiQueue[handle->queueDriver].dataSize -= size; @@ -1170,12 +1805,18 @@ void SAI_TransferTxHandleIRQ(I2S_Type *base, sai_handle_t *handle) } } +/*! + * brief Tx interrupt handler. + * + * param base SAI base pointer. + * param handle Pointer to the sai_handle_t structure. + */ void SAI_TransferRxHandleIRQ(I2S_Type *base, sai_handle_t *handle) { assert(handle); uint8_t *buffer = handle->saiQueue[handle->queueDriver].data; - uint8_t dataSize = handle->bitWidth / 8U; + uint8_t dataSize = (handle->bitWidth / 8U) * handle->channelNums; /* Handle Error */ if (base->RCSR & I2S_RCSR_FEF_MASK) @@ -1201,7 +1842,8 @@ void SAI_TransferRxHandleIRQ(I2S_Type *base, sai_handle_t *handle) uint8_t size = MIN((handle->saiQueue[handle->queueDriver].dataSize), (handle->watermark * dataSize)); /* Copy the data from sai buffer to FIFO */ - SAI_ReadNonBlocking(base, handle->channel, handle->bitWidth, buffer, size); + SAI_ReadNonBlocking(base, handle->channel, handle->channelMask, handle->endChannel, handle->bitWidth, buffer, + size); /* Update the internal counter */ handle->saiQueue[handle->queueDriver].dataSize -= size; @@ -1212,7 +1854,8 @@ void SAI_TransferRxHandleIRQ(I2S_Type *base, sai_handle_t *handle) { uint8_t size = MIN((handle->saiQueue[handle->queueDriver].dataSize), dataSize); - SAI_ReadNonBlocking(base, handle->channel, handle->bitWidth, buffer, size); + SAI_ReadNonBlocking(base, handle->channel, handle->channelMask, handle->endChannel, handle->bitWidth, buffer, + size); /* Update internal state */ handle->saiQueue[handle->queueDriver].dataSize -= size; diff --git a/ext/hal/nxp/mcux/drivers/imx/fsl_sai.h b/ext/hal/nxp/mcux/drivers/imx/fsl_sai.h index 45c0d4ce7bc..c6d33c746e0 100644 --- a/ext/hal/nxp/mcux/drivers/imx/fsl_sai.h +++ b/ext/hal/nxp/mcux/drivers/imx/fsl_sai.h @@ -22,7 +22,7 @@ /*! @name Driver version */ /*@{*/ -#define FSL_SAI_DRIVER_VERSION (MAKE_VERSION(2, 1, 5)) /*!< Version 2.1.5 */ +#define FSL_SAI_DRIVER_VERSION (MAKE_VERSION(2, 1, 7)) /*!< Version 2.1.7 */ /*@}*/ /*! @brief SAI return status*/ @@ -37,6 +37,19 @@ enum _sai_status_t kStatus_SAI_RxIdle = MAKE_STATUS(kStatusGroup_SAI, 6) /*!< SAI Rx is idle */ }; +/*< sai channel mask value, actual channel numbers is depend soc specific */ +enum _sai_channel_mask +{ + kSAI_Channel0Mask = 1 << 0U, /*!< channel 0 mask value */ + kSAI_Channel1Mask = 1 << 1U, /*!< channel 1 mask value */ + kSAI_Channel2Mask = 1 << 2U, /*!< channel 2 mask value */ + kSAI_Channel3Mask = 1 << 3U, /*!< channel 3 mask value */ + kSAI_Channel4Mask = 1 << 4U, /*!< channel 4 mask value */ + kSAI_Channel5Mask = 1 << 5U, /*!< channel 5 mask value */ + kSAI_Channel6Mask = 1 << 6U, /*!< channel 6 mask value */ + kSAI_Channel7Mask = 1 << 7U, /*!< channel 7 mask value */ +}; + /*! @brief Define the SAI bus type */ typedef enum _sai_protocol { @@ -85,6 +98,7 @@ typedef enum _sai_sync_mode kSAI_ModeSyncWithOtherRx /*!< Synchronous with another SAI receiver */ } sai_sync_mode_t; +#if !(defined(FSL_FEATURE_SAI_HAS_NO_MCR_MICS) && (FSL_FEATURE_SAI_HAS_NO_MCR_MICS)) /*! @brief Mater clock source */ typedef enum _sai_mclk_source { @@ -93,14 +107,20 @@ typedef enum _sai_mclk_source kSAI_MclkSourceSelect2, /*!< Master clock from source 2 */ kSAI_MclkSourceSelect3 /*!< Master clock from source 3 */ } sai_mclk_source_t; +#endif /*! @brief Bit clock source */ typedef enum _sai_bclk_source { kSAI_BclkSourceBusclk = 0x0U, /*!< Bit clock using bus clock */ - kSAI_BclkSourceMclkDiv, /*!< Bit clock using master clock divider */ - kSAI_BclkSourceOtherSai0, /*!< Bit clock from other SAI device */ - kSAI_BclkSourceOtherSai1 /*!< Bit clock from other SAI device */ + /* General device bit source definition */ + kSAI_BclkSourceMclkOption1 = 0x1U, /*!< Bit clock MCLK option 1 */ + kSAI_BclkSourceMclkOption2 = 0x2U, /*!< Bit clock MCLK option2 */ + kSAI_BclkSourceMclkOption3 = 0x3U, /*!< Bit clock MCLK option3 */ + /* Kinetis device bit clock source definition */ + kSAI_BclkSourceMclkDiv = 0x1U, /*!< Bit clock using master clock divider */ + kSAI_BclkSourceOtherSai0 = 0x2U, /*!< Bit clock from other SAI device */ + kSAI_BclkSourceOtherSai1 = 0x3U /*!< Bit clock from other SAI device */ } sai_bclk_source_t; /*! @brief The SAI interrupt enable flag */ @@ -164,9 +184,11 @@ typedef struct _sai_config sai_protocol_t protocol; /*!< Audio bus protocol in SAI */ sai_sync_mode_t syncMode; /*!< SAI sync mode, control Tx/Rx clock sync */ #if defined(FSL_FEATURE_SAI_HAS_MCR) && (FSL_FEATURE_SAI_HAS_MCR) - bool mclkOutputEnable; /*!< Master clock output enable, true means master clock divider enabled */ -#endif /* FSL_FEATURE_SAI_HAS_MCR */ - sai_mclk_source_t mclkSource; /*!< Master Clock source */ + bool mclkOutputEnable; /*!< Master clock output enable, true means master clock divider enabled */ +#if !(defined(FSL_FEATURE_SAI_HAS_NO_MCR_MICS) && (FSL_FEATURE_SAI_HAS_NO_MCR_MICS)) + sai_mclk_source_t mclkSource; /*!< Master Clock source */ +#endif /* FSL_FEATURE_SAI_HAS_MCR */ +#endif sai_bclk_source_t bclkSource; /*!< Bit Clock source */ sai_master_slave_t masterSlave; /*!< Master or slave */ } sai_config_t; @@ -189,7 +211,6 @@ typedef enum _sai_sample_rate kSAI_SampleRate96KHz = 96000U, /*!< Sample rate 96000 Hz */ kSAI_SampleRate192KHz = 192000U, /*!< Sample rate 192000 Hz */ kSAI_SampleRate384KHz = 384000U, /*!< Sample rate 384000 Hz */ - } sai_sample_rate_t; /*! @brief Audio word width */ @@ -209,9 +230,21 @@ typedef struct _sai_transfer_format sai_mono_stereo_t stereo; /*!< Mono or stereo */ uint32_t masterClockHz; /*!< Master clock frequency in Hz */ #if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) - uint8_t watermark; /*!< Watermark value */ -#endif /* FSL_FEATURE_SAI_FIFO_COUNT */ - uint8_t channel; /*!< Data channel used in transfer.*/ + uint8_t watermark; /*!< Watermark value */ +#endif /* FSL_FEATURE_SAI_FIFO_COUNT */ + + /* for the multi channel usage, user can provide channelMask Oonly, then sai driver will handle + * other parameter carefully, such as + * channelMask = kSAI_Channel0Mask | kSAI_Channel1Mask | kSAI_Channel4Mask + * then in SAI_RxSetFormat/SAI_TxSetFormat function, channel/endChannel/channelNums will be calculated. + * for the single channel usage, user can provide channel or channel mask only, such as, + * channel = 0 or channelMask = kSAI_Channel0Mask. + */ + uint8_t channel; /*!< Transfer start channel */ + uint8_t channelMask; /*!< enabled channel mask value, reference _sai_channel_mask */ + uint8_t endChannel; /*!< end channel number */ + uint8_t channelNums; /*!< Total enabled channel numbers */ + sai_protocol_t protocol; /*!< Which audio protocol used */ bool isFrameSyncCompact; /*!< True means Frame sync length is configurable according to bitWidth, false means frame sync length is 64 times of bit clock. */ @@ -232,12 +265,25 @@ typedef void (*sai_transfer_callback_t)(I2S_Type *base, sai_handle_t *handle, st /*! @brief SAI handle structure */ struct _sai_handle { - I2S_Type *base; /*!< base address */ - uint32_t state; /*!< Transfer status */ - sai_transfer_callback_t callback; /*!< Callback function called at transfer event*/ - void *userData; /*!< Callback parameter passed to callback function*/ - uint8_t bitWidth; /*!< Bit width for transfer, 8/16/24/32 bits */ - uint8_t channel; /*!< Transfer channel */ + I2S_Type *base; /*!< base address */ + + uint32_t state; /*!< Transfer status */ + sai_transfer_callback_t callback; /*!< Callback function called at transfer event*/ + void *userData; /*!< Callback parameter passed to callback function*/ + uint8_t bitWidth; /*!< Bit width for transfer, 8/16/24/32 bits */ + + /* for the multi channel usage, user can provide channelMask Oonly, then sai driver will handle + * other parameter carefully, such as + * channelMask = kSAI_Channel0Mask | kSAI_Channel1Mask | kSAI_Channel4Mask + * then in SAI_RxSetFormat/SAI_TxSetFormat function, channel/endChannel/channelNums will be calculated. + * for the single channel usage, user can provide channel or channel mask only, such as, + * channel = 0 or channelMask = kSAI_Channel0Mask. + */ + uint8_t channel; /*!< Transfer start channel */ + uint8_t channelMask; /*!< enabled channel mask value, refernece _sai_channel_mask */ + uint8_t endChannel; /*!< end channel number */ + uint8_t channelNums; /*!< Total enabled channel numbers */ + sai_transfer_t saiQueue[SAI_XFER_QUEUE_SIZE]; /*!< Transfer queue storing queued transfer */ size_t transferSize[SAI_XFER_QUEUE_SIZE]; /*!< Data bytes need to transfer */ volatile uint8_t queueUser; /*!< Index for user to queue transfer */ @@ -784,6 +830,21 @@ void SAI_RxSetFormat(I2S_Type *base, */ void SAI_WriteBlocking(I2S_Type *base, uint32_t channel, uint32_t bitWidth, uint8_t *buffer, uint32_t size); +/*! + * @brief Sends data to multi channel using a blocking method. + * + * @note This function blocks by polling until data is ready to be sent. + * + * @param base SAI base pointer. + * @param channel Data channel used. + * @param channelMask channel mask. + * @param bitWidth How many bits in an audio word; usually 8/16/24/32 bits. + * @param buffer Pointer to the data to be written. + * @param size Bytes to be written. + */ +void SAI_WriteMultiChannelBlocking( + I2S_Type *base, uint32_t channel, uint32_t channelMask, uint32_t bitWidth, uint8_t *buffer, uint32_t size); + /*! * @brief Writes data into SAI FIFO. * @@ -809,6 +870,21 @@ static inline void SAI_WriteData(I2S_Type *base, uint32_t channel, uint32_t data */ void SAI_ReadBlocking(I2S_Type *base, uint32_t channel, uint32_t bitWidth, uint8_t *buffer, uint32_t size); +/*! + * @brief Receives multi channel data using a blocking method. + * + * @note This function blocks by polling until data is ready to be sent. + * + * @param base SAI base pointer. + * @param channel Data channel used. + * @param channelMask channel mask. + * @param bitWidth How many bits in an audio word; usually 8/16/24/32 bits. + * @param buffer Pointer to the data to be read. + * @param size Bytes to be read. + */ +void SAI_ReadMultiChannelBlocking( + I2S_Type *base, uint32_t channel, uint32_t channelMask, uint32_t bitWidth, uint8_t *buffer, uint32_t size); + /*! * @brief Reads data from the SAI FIFO. * diff --git a/ext/hal/nxp/mcux/drivers/imx/fsl_sai_edma.c b/ext/hal/nxp/mcux/drivers/imx/fsl_sai_edma.c index 16009417087..116d088d9f2 100644 --- a/ext/hal/nxp/mcux/drivers/imx/fsl_sai_edma.c +++ b/ext/hal/nxp/mcux/drivers/imx/fsl_sai_edma.c @@ -132,6 +132,19 @@ static void SAI_RxEDMACallback(edma_handle_t *handle, void *userData, bool done, } } +/*! + * brief Initializes the SAI eDMA handle. + * + * This function initializes the SAI master DMA handle, which can be used for other SAI master transactional APIs. + * Usually, for a specified SAI instance, call this API once to get the initialized handle. + * + * param base SAI base pointer. + * param handle SAI eDMA handle pointer. + * param base SAI peripheral base address. + * param callback Pointer to user callback function. + * param userData User parameter passed to the callback function. + * param dmaHandle eDMA handle pointer, this handle shall be static allocated by users. + */ void SAI_TransferTxCreateHandleEDMA( I2S_Type *base, sai_edma_handle_t *handle, sai_edma_callback_t callback, void *userData, edma_handle_t *dmaHandle) { @@ -160,6 +173,19 @@ void SAI_TransferTxCreateHandleEDMA( EDMA_SetCallback(dmaHandle, SAI_TxEDMACallback, &s_edmaPrivateHandle[instance][0]); } +/*! + * brief Initializes the SAI Rx eDMA handle. + * + * This function initializes the SAI slave DMA handle, which can be used for other SAI master transactional APIs. + * Usually, for a specified SAI instance, call this API once to get the initialized handle. + * + * param base SAI base pointer. + * param handle SAI eDMA handle pointer. + * param base SAI peripheral base address. + * param callback Pointer to user callback function. + * param userData User parameter passed to the callback function. + * param dmaHandle eDMA handle pointer, this handle shall be static allocated by users. + */ void SAI_TransferRxCreateHandleEDMA( I2S_Type *base, sai_edma_handle_t *handle, sai_edma_callback_t callback, void *userData, edma_handle_t *dmaHandle) { @@ -188,6 +214,21 @@ void SAI_TransferRxCreateHandleEDMA( EDMA_SetCallback(dmaHandle, SAI_RxEDMACallback, &s_edmaPrivateHandle[instance][1]); } +/*! + * brief Configures the SAI Tx audio format. + * + * The audio format can be changed at run-time. This function configures the sample rate and audio data + * format to be transferred. This function also sets the eDMA parameter according to formatting requirements. + * + * param base SAI base pointer. + * param handle SAI eDMA handle pointer. + * param format Pointer to SAI audio data format structure. + * param mclkSourceClockHz SAI master clock source frequency in Hz. + * param bclkSourceClockHz SAI bit clock source frequency in Hz. If bit clock source is master + * clock, this value should equals to masterClockHz in format. + * retval kStatus_Success Audio format set successfully. + * retval kStatus_InvalidArgument The input argument is invalid. +*/ void SAI_TransferTxSetFormatEDMA(I2S_Type *base, sai_edma_handle_t *handle, sai_transfer_format_t *format, @@ -221,6 +262,21 @@ void SAI_TransferTxSetFormatEDMA(I2S_Type *base, #endif /* FSL_FEATURE_SAI_FIFO_COUNT */ } +/*! + * brief Configures the SAI Rx audio format. + * + * The audio format can be changed at run-time. This function configures the sample rate and audio data + * format to be transferred. This function also sets the eDMA parameter according to formatting requirements. + * + * param base SAI base pointer. + * param handle SAI eDMA handle pointer. + * param format Pointer to SAI audio data format structure. + * param mclkSourceClockHz SAI master clock source frequency in Hz. + * param bclkSourceClockHz SAI bit clock source frequency in Hz. If a bit clock source is the master + * clock, this value should equal to masterClockHz in format. + * retval kStatus_Success Audio format set successfully. + * retval kStatus_InvalidArgument The input argument is invalid. +*/ void SAI_TransferRxSetFormatEDMA(I2S_Type *base, sai_edma_handle_t *handle, sai_transfer_format_t *format, @@ -254,6 +310,19 @@ void SAI_TransferRxSetFormatEDMA(I2S_Type *base, #endif /* FSL_FEATURE_SAI_FIFO_COUNT */ } +/*! + * brief Performs a non-blocking SAI transfer using DMA. + * + * note This interface returns immediately after the transfer initiates. Call + * SAI_GetTransferStatus to poll the transfer status and check whether the SAI transfer is finished. + * + * param base SAI base pointer. + * param handle SAI eDMA handle pointer. + * param xfer Pointer to the DMA transfer structure. + * retval kStatus_Success Start a SAI eDMA send successfully. + * retval kStatus_InvalidArgument The input argument is invalid. + * retval kStatus_TxBusy SAI is busy sending data. + */ status_t SAI_TransferSendEDMA(I2S_Type *base, sai_edma_handle_t *handle, sai_transfer_t *xfer) { assert(handle && xfer); @@ -305,6 +374,19 @@ status_t SAI_TransferSendEDMA(I2S_Type *base, sai_edma_handle_t *handle, sai_tra return kStatus_Success; } +/*! + * brief Performs a non-blocking SAI receive using eDMA. + * + * note This interface returns immediately after the transfer initiates. Call + * the SAI_GetReceiveRemainingBytes to poll the transfer status and check whether the SAI transfer is finished. + * + * param base SAI base pointer + * param handle SAI eDMA handle pointer. + * param xfer Pointer to DMA transfer structure. + * retval kStatus_Success Start a SAI eDMA receive successfully. + * retval kStatus_InvalidArgument The input argument is invalid. + * retval kStatus_RxBusy SAI is busy receiving data. + */ status_t SAI_TransferReceiveEDMA(I2S_Type *base, sai_edma_handle_t *handle, sai_transfer_t *xfer) { assert(handle && xfer); @@ -356,6 +438,15 @@ status_t SAI_TransferReceiveEDMA(I2S_Type *base, sai_edma_handle_t *handle, sai_ return kStatus_Success; } +/*! + * brief Aborts a SAI transfer using eDMA. + * + * This function only aborts the current transfer slots, the other transfer slots' information still kept + * in the handler. If users want to terminate all transfer slots, just call SAI_TransferTerminateSendEDMA. + * + * param base SAI base pointer. + * param handle SAI eDMA handle pointer. + */ void SAI_TransferAbortSendEDMA(I2S_Type *base, sai_edma_handle_t *handle) { assert(handle); @@ -384,6 +475,15 @@ void SAI_TransferAbortSendEDMA(I2S_Type *base, sai_edma_handle_t *handle) handle->state = kSAI_Idle; } +/*! + * brief Aborts a SAI receive using eDMA. + * + * This function only aborts the current transfer slots, the other transfer slots' information still kept + * in the handler. If users want to terminate all transfer slots, just call SAI_TransferTerminateReceiveEDMA. + * + * param base SAI base pointer + * param handle SAI eDMA handle pointer. + */ void SAI_TransferAbortReceiveEDMA(I2S_Type *base, sai_edma_handle_t *handle) { assert(handle); @@ -412,6 +512,15 @@ void SAI_TransferAbortReceiveEDMA(I2S_Type *base, sai_edma_handle_t *handle) handle->state = kSAI_Idle; } +/*! + * brief Terminate all SAI send. + * + * This function will clear all transfer slots buffered in the sai queue. If users only want to abort the + * current transfer slot, please call SAI_TransferAbortSendEDMA. + * + * param base SAI base pointer. + * param handle SAI eDMA handle pointer. + */ void SAI_TransferTerminateSendEDMA(I2S_Type *base, sai_edma_handle_t *handle) { assert(handle); @@ -427,6 +536,15 @@ void SAI_TransferTerminateSendEDMA(I2S_Type *base, sai_edma_handle_t *handle) handle->queueDriver = 0U; } +/*! + * brief Terminate all SAI receive. + * + * This function will clear all transfer slots buffered in the sai queue. If users only want to abort the + * current transfer slot, please call SAI_TransferAbortReceiveEDMA. + * + * param base SAI base pointer. + * param handle SAI eDMA handle pointer. + */ void SAI_TransferTerminateReceiveEDMA(I2S_Type *base, sai_edma_handle_t *handle) { assert(handle); @@ -442,6 +560,15 @@ void SAI_TransferTerminateReceiveEDMA(I2S_Type *base, sai_edma_handle_t *handle) handle->queueDriver = 0U; } +/*! + * brief Gets byte count sent by SAI. + * + * param base SAI base pointer. + * param handle SAI eDMA handle pointer. + * param count Bytes count sent by SAI. + * retval kStatus_Success Succeed get the transfer count. + * retval kStatus_NoTransferInProgress There is no non-blocking transaction in progress. + */ status_t SAI_TransferGetSendCountEDMA(I2S_Type *base, sai_edma_handle_t *handle, size_t *count) { assert(handle); @@ -462,6 +589,15 @@ status_t SAI_TransferGetSendCountEDMA(I2S_Type *base, sai_edma_handle_t *handle, return status; } +/*! + * brief Gets byte count received by SAI. + * + * param base SAI base pointer + * param handle SAI eDMA handle pointer. + * param count Bytes count received by SAI. + * retval kStatus_Success Succeed get the transfer count. + * retval kStatus_NoTransferInProgress There is no non-blocking transaction in progress. + */ status_t SAI_TransferGetReceiveCountEDMA(I2S_Type *base, sai_edma_handle_t *handle, size_t *count) { assert(handle); diff --git a/ext/hal/nxp/mcux/drivers/imx/fsl_sai_edma.h b/ext/hal/nxp/mcux/drivers/imx/fsl_sai_edma.h index 7be59ea4798..b3d913948b5 100644 --- a/ext/hal/nxp/mcux/drivers/imx/fsl_sai_edma.h +++ b/ext/hal/nxp/mcux/drivers/imx/fsl_sai_edma.h @@ -22,7 +22,7 @@ /*! @name Driver version */ /*@{*/ -#define FSL_SAI_EDMA_DRIVER_VERSION (MAKE_VERSION(2, 1, 4)) /*!< Version 2.1.4 */ +#define FSL_SAI_EDMA_DRIVER_VERSION (MAKE_VERSION(2, 1, 5)) /*!< Version 2.1.5 */ /*@}*/ typedef struct _sai_edma_handle sai_edma_handle_t; diff --git a/ext/hal/nxp/mcux/drivers/imx/fsl_semc.c b/ext/hal/nxp/mcux/drivers/imx/fsl_semc.c index 78c935e1373..842ebe3a809 100644 --- a/ext/hal/nxp/mcux/drivers/imx/fsl_semc.c +++ b/ext/hal/nxp/mcux/drivers/imx/fsl_semc.c @@ -215,10 +215,27 @@ static status_t SEMC_IsIPCommandDone(SEMC_Type *base) return kStatus_Success; } +/*! + * brief Gets the SEMC default basic configuration structure. + * + * The purpose of this API is to get the default SEMC + * configure structure for SEMC_Init(). User may use the initialized + * structure unchanged in SEMC_Init(), or modify some fields of the + * structure before calling SEMC_Init(). + * Example: + code + semc_config_t config; + SEMC_GetDefaultConfig(&config); + endcode + * param config The SEMC configuration structure pointer. + */ void SEMC_GetDefaultConfig(semc_config_t *config) { assert(config); + /* Initializes the configure structure to zero. */ + memset(config, 0, sizeof(*config)); + semc_queuea_weight_struct_t *queueaWeight = &(config->queueWeight.queueaWeight.queueaConfig); semc_queueb_weight_struct_t *queuebWeight = &(config->queueWeight.queuebWeight.queuebConfig); @@ -238,6 +255,14 @@ void SEMC_GetDefaultConfig(semc_config_t *config) queuebWeight->bankRotation = SEMC_BMCR1_TYPICAL_WBR; } +/*! + * brief Initializes SEMC. + * This function ungates the SEMC clock and initializes SEMC. + * This function must be called before calling any other SEMC driver functions. + * + * param base SEMC peripheral base address. + * param configure The SEMC configuration structure pointer. + */ void SEMC_Init(SEMC_Type *base, semc_config_t *configure) { assert(configure); @@ -274,6 +299,13 @@ void SEMC_Init(SEMC_Type *base, semc_config_t *configure) base->MCR &= ~SEMC_MCR_MDIS_MASK; } +/*! + * brief Deinitializes the SEMC module and gates the clock. + * This function gates the SEMC clock. As a result, the SEMC + * module doesn't work after calling this function. + * + * param base SEMC peripheral base address. + */ void SEMC_Deinit(SEMC_Type *base) { /* Disable module. Check there is no pending command before disable module. */ @@ -291,6 +323,14 @@ void SEMC_Deinit(SEMC_Type *base) #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ } +/*! + * brief Configures SDRAM controller in SEMC. + * + * param base SEMC peripheral base address. + * param cs The chip selection. + * param config The sdram configuration. + * param clkSrc_Hz The SEMC clock frequency. + */ status_t SEMC_ConfigureSDRAM(SEMC_Type *base, semc_sdram_cs_t cs, semc_sdram_config_t *config, uint32_t clkSrc_Hz) { assert(config); @@ -392,6 +432,13 @@ status_t SEMC_ConfigureSDRAM(SEMC_Type *base, semc_sdram_cs_t cs, semc_sdram_con return kStatus_Success; } +/*! + * brief Configures NAND controller in SEMC. + * + * param base SEMC peripheral base address. + * param config The nand configuration. + * param clkSrc_Hz The SEMC clock frequency. + */ status_t SEMC_ConfigureNAND(SEMC_Type *base, semc_nand_config_t *config, uint32_t clkSrc_Hz) { assert(config); @@ -466,6 +513,13 @@ status_t SEMC_ConfigureNAND(SEMC_Type *base, semc_nand_config_t *config, uint32_ return kStatus_Success; } +/*! + * brief Configures NOR controller in SEMC. + * + * param base SEMC peripheral base address. + * param config The nor configuration. + * param clkSrc_Hz The SEMC clock frequency. + */ status_t SEMC_ConfigureNOR(SEMC_Type *base, semc_nor_config_t *config, uint32_t clkSrc_Hz) { assert(config); @@ -584,6 +638,13 @@ status_t SEMC_ConfigureNOR(SEMC_Type *base, semc_nor_config_t *config, uint32_t return SEMC_ConfigureIPCommand(base, (config->portSize + 1)); } +/*! + * brief Configures SRAM controller in SEMC. + * + * param base SEMC peripheral base address. + * param config The sram configuration. + * param clkSrc_Hz The SEMC clock frequency. + */ status_t SEMC_ConfigureSRAM(SEMC_Type *base, semc_sram_config_t *config, uint32_t clkSrc_Hz) { assert(config); @@ -690,6 +751,13 @@ status_t SEMC_ConfigureSRAM(SEMC_Type *base, semc_sram_config_t *config, uint32_ return result; } +/*! + * brief Configures DBI controller in SEMC. + * + * param base SEMC peripheral base address. + * param config The dbi configuration. + * param clkSrc_Hz The SEMC clock frequency. + */ status_t SEMC_ConfigureDBI(SEMC_Type *base, semc_dbi_config_t *config, uint32_t clkSrc_Hz) { assert(config); @@ -720,16 +788,30 @@ status_t SEMC_ConfigureDBI(SEMC_Type *base, semc_dbi_config_t *config, uint32_t SEMC_DBICR0_PS(config->portSize) | SEMC_DBICR0_BL(config->burstLen) | SEMC_DBICR0_COL(config->columnAddrBitNum); /* Timing setting. */ - base->DBICR1 = SEMC_DBICR1_CES(SEMC_ConvertTiming(config->tCsxSetup_Ns, clkSrc_Hz)) | - SEMC_DBICR1_CEH(SEMC_ConvertTiming(config->tCsxHold_Ns, clkSrc_Hz)) | - SEMC_DBICR1_WEL(SEMC_ConvertTiming(config->tWexLow_Ns, clkSrc_Hz)) | - SEMC_DBICR1_WEH(SEMC_ConvertTiming(config->tWexHigh_Ns, clkSrc_Hz)) | - SEMC_DBICR1_REL(SEMC_ConvertTiming(config->tRdxLow_Ns, clkSrc_Hz)) | - SEMC_DBICR1_REH(SEMC_ConvertTiming(config->tRdxHigh_Ns, clkSrc_Hz)) | - SEMC_DBICR1_CEITV(SEMC_ConvertTiming(config->tCsxInterval_Ns, clkSrc_Hz)); + base->DBICR1 = SEMC_DBICR1_CES(SEMC_ConvertTiming(config->tCsxSetup_Ns, clkSrc_Hz) - 1) | + SEMC_DBICR1_CEH(SEMC_ConvertTiming(config->tCsxHold_Ns, clkSrc_Hz) - 1) | + SEMC_DBICR1_WEL(SEMC_ConvertTiming(config->tWexLow_Ns, clkSrc_Hz) - 1) | + SEMC_DBICR1_WEH(SEMC_ConvertTiming(config->tWexHigh_Ns, clkSrc_Hz) - 1) | + SEMC_DBICR1_REL(SEMC_ConvertTiming(config->tRdxLow_Ns, clkSrc_Hz) - 1) | + SEMC_DBICR1_REH(SEMC_ConvertTiming(config->tRdxHigh_Ns, clkSrc_Hz) - 1) | + SEMC_DBICR1_CEITV(SEMC_ConvertTiming(config->tCsxInterval_Ns, clkSrc_Hz) - 1); return SEMC_ConfigureIPCommand(base, (config->portSize + 1)); } +/*! + * brief SEMC IP command access. + * + * param base SEMC peripheral base address. + * param type SEMC memory type. refer to "semc_mem_type_t" + * param address SEMC device address. + * param command SEMC IP command. + * For NAND device, we should use the SEMC_BuildNandIPCommand to get the right nand command. + * For NOR/DBI device, take refer to "semc_ipcmd_nor_dbi_t". + * For SRAM device, take refer to "semc_ipcmd_sram_t". + * For SDRAM device, take refer to "semc_ipcmd_sdram_t". + * param write Data for write access. + * param read Data pointer for read data out. + */ status_t SEMC_SendIPCommand( SEMC_Type *base, semc_mem_type_t type, uint32_t address, uint16_t command, uint32_t write, uint32_t *read) { @@ -794,6 +876,14 @@ status_t SEMC_SendIPCommand( return kStatus_Success; } +/*! + * brief SEMC NAND device memory write through IP command. + * + * param base SEMC peripheral base address. + * param address SEMC NAND device address. + * param data Data for write access. + * param size_bytes Data length. + */ status_t SEMC_IPCommandNandWrite(SEMC_Type *base, uint32_t address, uint8_t *data, uint32_t size_bytes) { assert(data); @@ -834,6 +924,14 @@ status_t SEMC_IPCommandNandWrite(SEMC_Type *base, uint32_t address, uint8_t *dat return result; } +/*! + * brief SEMC NAND device memory read through IP command. + * + * param base SEMC peripheral base address. + * param address SEMC NAND device address. + * param data Data pointer for data read out. + * param size_bytes Data length. + */ status_t SEMC_IPCommandNandRead(SEMC_Type *base, uint32_t address, uint8_t *data, uint32_t size_bytes) { assert(data); @@ -874,6 +972,14 @@ status_t SEMC_IPCommandNandRead(SEMC_Type *base, uint32_t address, uint8_t *data return result; } +/*! + * brief SEMC NOR device memory read through IP command. + * + * param base SEMC peripheral base address. + * param address SEMC NOR device address. + * param data Data pointer for data read out. + * param size_bytes Data length. + */ status_t SEMC_IPCommandNorRead(SEMC_Type *base, uint32_t address, uint8_t *data, uint32_t size_bytes) { assert(data); @@ -912,6 +1018,14 @@ status_t SEMC_IPCommandNorRead(SEMC_Type *base, uint32_t address, uint8_t *data, return result; } +/*! + * brief SEMC NOR device memory write through IP command. + * + * param base SEMC peripheral base address. + * param address SEMC NOR device address. + * param data Data for write access. + * param size_bytes Data length. + */ status_t SEMC_IPCommandNorWrite(SEMC_Type *base, uint32_t address, uint8_t *data, uint32_t size_bytes) { assert(data); diff --git a/ext/hal/nxp/mcux/drivers/imx/fsl_semc.h b/ext/hal/nxp/mcux/drivers/imx/fsl_semc.h index daca0804429..8f24d4e95c1 100644 --- a/ext/hal/nxp/mcux/drivers/imx/fsl_semc.h +++ b/ext/hal/nxp/mcux/drivers/imx/fsl_semc.h @@ -579,8 +579,12 @@ void SEMC_Init(SEMC_Type *base, semc_config_t *configure); /*! * @brief Deinitializes the SEMC module and gates the clock. - * This function gates the SEMC clock. As a result, the SEMC - * module doesn't work after calling this function. + * + * This function gates the SEMC clock. As a result, the SEMC module doesn't work after + * calling this function, for some IDE, calling this API may cause the next downloading + * operation failed. so, please call this API cautiously. Additional, users can + * using "#define FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL (1)" to disable the clock control + * operation in drivers. * * @param base SEMC peripheral base address. */ diff --git a/ext/hal/nxp/mcux/drivers/imx/fsl_snvs_hp.c b/ext/hal/nxp/mcux/drivers/imx/fsl_snvs_hp.c index 00ffbbced76..77796e75ce9 100644 --- a/ext/hal/nxp/mcux/drivers/imx/fsl_snvs_hp.c +++ b/ext/hal/nxp/mcux/drivers/imx/fsl_snvs_hp.c @@ -2,7 +2,7 @@ * Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright (c) 2017, NXP * All rights reserved. - * + * * SPDX-License-Identifier: BSD-3-Clause */ @@ -239,6 +239,13 @@ static uint32_t SNVS_HP_GetInstance(SNVS_Type *base) } #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +/*! + * brief Initialize the SNVS. + * + * note This API should be called at the beginning of the application using the SNVS driver. + * + * param base SNVS peripheral base address + */ void SNVS_HP_Init(SNVS_Type *base) { #if (!(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && \ @@ -248,6 +255,11 @@ void SNVS_HP_Init(SNVS_Type *base) #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ } +/*! + * brief Deinitialize the SNVS. + * + * param base SNVS peripheral base address + */ void SNVS_HP_Deinit(SNVS_Type *base) { #if (!(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && \ @@ -257,6 +269,14 @@ void SNVS_HP_Deinit(SNVS_Type *base) #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ } +/*! + * brief Ungates the SNVS clock and configures the peripheral for basic operation. + * + * note This API should be called at the beginning of the application using the SNVS driver. + * + * param base SNVS peripheral base address + * param config Pointer to the user's SNVS configuration structure. + */ void SNVS_HP_RTC_Init(SNVS_Type *base, const snvs_hp_rtc_config_t *config) { assert(config); @@ -278,6 +298,11 @@ void SNVS_HP_RTC_Init(SNVS_Type *base, const snvs_hp_rtc_config_t *config) } } +/*! + * brief Stops the RTC and SRTC timers. + * + * param base SNVS peripheral base address + */ void SNVS_HP_RTC_Deinit(SNVS_Type *base) { base->HPCR &= ~SNVS_HPCR_RTC_EN_MASK; @@ -289,10 +314,24 @@ void SNVS_HP_RTC_Deinit(SNVS_Type *base) #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ } +/*! + * brief Fills in the SNVS config struct with the default settings. + * + * The default values are as follows. + * code + * config->rtccalenable = false; + * config->rtccalvalue = 0U; + * config->PIFreq = 0U; + * endcode + * param config Pointer to the user's SNVS configuration structure. + */ void SNVS_HP_RTC_GetDefaultConfig(snvs_hp_rtc_config_t *config) { assert(config); + /* Initializes the configure structure to zero. */ + memset(config, 0, sizeof(*config)); + config->rtcCalEnable = false; config->rtcCalValue = 0U; config->periodicInterruptFreq = 0U; @@ -313,6 +352,15 @@ static uint32_t SNVS_HP_RTC_GetSeconds(SNVS_Type *base) return seconds; } +/*! + * brief Sets the SNVS RTC date and time according to the given time structure. + * + * param base SNVS peripheral base address + * param datetime Pointer to the structure where the date and time details are stored. + * + * return kStatus_Success: Success in setting the time and starting the SNVS RTC + * kStatus_InvalidArgument: Error because the datetime format is incorrect + */ status_t SNVS_HP_RTC_SetDatetime(SNVS_Type *base, const snvs_hp_rtc_datetime_t *datetime) { assert(datetime); @@ -344,6 +392,12 @@ status_t SNVS_HP_RTC_SetDatetime(SNVS_Type *base, const snvs_hp_rtc_datetime_t * return kStatus_Success; } +/*! + * brief Gets the SNVS RTC time and stores it in the given time structure. + * + * param base SNVS peripheral base address + * param datetime Pointer to the structure where the date and time details are stored. + */ void SNVS_HP_RTC_GetDatetime(SNVS_Type *base, snvs_hp_rtc_datetime_t *datetime) { assert(datetime); @@ -351,6 +405,20 @@ void SNVS_HP_RTC_GetDatetime(SNVS_Type *base, snvs_hp_rtc_datetime_t *datetime) SNVS_HP_ConvertSecondsToDatetime(SNVS_HP_RTC_GetSeconds(base), datetime); } +/*! + * brief Sets the SNVS RTC alarm time. + * + * The function sets the RTC alarm. It also checks whether the specified alarm time + * is greater than the present time. If not, the function does not set the alarm + * and returns an error. + * + * param base SNVS peripheral base address + * param alarmTime Pointer to the structure where the alarm time is stored. + * + * return kStatus_Success: success in setting the SNVS RTC alarm + * kStatus_InvalidArgument: Error because the alarm datetime format is incorrect + * kStatus_Fail: Error because the alarm time has already passed + */ status_t SNVS_HP_RTC_SetAlarm(SNVS_Type *base, const snvs_hp_rtc_datetime_t *alarmTime) { assert(alarmTime); @@ -390,6 +458,12 @@ status_t SNVS_HP_RTC_SetAlarm(SNVS_Type *base, const snvs_hp_rtc_datetime_t *ala return kStatus_Success; } +/*! + * brief Returns the SNVS RTC alarm time. + * + * param base SNVS peripheral base address + * param datetime Pointer to the structure where the alarm date and time details are stored. + */ void SNVS_HP_RTC_GetAlarm(SNVS_Type *base, snvs_hp_rtc_datetime_t *datetime) { assert(datetime); @@ -403,6 +477,11 @@ void SNVS_HP_RTC_GetAlarm(SNVS_Type *base, snvs_hp_rtc_datetime_t *datetime) } #if (defined(FSL_FEATURE_SNVS_HAS_SRTC) && (FSL_FEATURE_SNVS_HAS_SRTC > 0)) +/*! + * brief The function synchronizes RTC counter value with SRTC. + * + * param base SNVS peripheral base address + */ void SNVS_HP_RTC_TimeSynchronize(SNVS_Type *base) { uint32_t tmp = base->HPCR; @@ -420,6 +499,14 @@ void SNVS_HP_RTC_TimeSynchronize(SNVS_Type *base) } #endif /* FSL_FEATURE_SNVS_HAS_SRTC */ +/*! + * brief Gets the SNVS status flags. + * + * param base SNVS peripheral base address + * + * return The status flags. This is the logical OR of members of the + * enumeration ::snvs_status_flags_t + */ uint32_t SNVS_HP_RTC_GetStatusFlags(SNVS_Type *base) { uint32_t flags = 0U; @@ -437,6 +524,14 @@ uint32_t SNVS_HP_RTC_GetStatusFlags(SNVS_Type *base) return flags; } +/*! + * brief Gets the enabled SNVS interrupts. + * + * param base SNVS peripheral base address + * + * return The enabled interrupts. This is the logical OR of members of the + * enumeration ::snvs_interrupt_enable_t + */ uint32_t SNVS_HP_RTC_GetEnabledInterrupts(SNVS_Type *base) { uint32_t val = 0U; diff --git a/ext/hal/nxp/mcux/drivers/imx/fsl_snvs_hp.h b/ext/hal/nxp/mcux/drivers/imx/fsl_snvs_hp.h index 015897c06db..2f1cf36d476 100644 --- a/ext/hal/nxp/mcux/drivers/imx/fsl_snvs_hp.h +++ b/ext/hal/nxp/mcux/drivers/imx/fsl_snvs_hp.h @@ -1,8 +1,8 @@ /* * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright (c) 2017, NXP + * Copyright (c) 2017-2018, NXP * All rights reserved. - * + * * SPDX-License-Identifier: BSD-3-Clause */ @@ -22,7 +22,7 @@ /*! @name Driver version */ /*@{*/ -#define FSL_SNVS_HP_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0 */ +#define FSL_SNVS_HP_DRIVER_VERSION (MAKE_VERSION(2, 1, 1)) /*!< Version 2.1.1 */ /*@}*/ /*! @brief List of SNVS interrupts */ @@ -37,10 +37,35 @@ typedef enum _snvs_hp_status_flags { kSNVS_RTC_AlarmInterruptFlag = SNVS_HPSR_HPTA_MASK, /*!< RTC time alarm flag */ kSNVS_RTC_PeriodicInterruptFlag = SNVS_HPSR_PI_MASK, /*!< RTC periodic interrupt flag */ - kSNVS_ZMK_ZeroFlag = SNVS_HPSR_ZMK_ZERO_MASK, /*!< The ZMK is zero */ + kSNVS_ZMK_ZeroFlag = (int)SNVS_HPSR_ZMK_ZERO_MASK, /*!< The ZMK is zero */ kSNVS_OTPMK_ZeroFlag = SNVS_HPSR_OTPMK_ZERO_MASK, /*!< The OTPMK is zero */ } snvs_hp_status_flags_t; +/*! @brief List of SNVS security violation flags */ +typedef enum _snvs_hp_sv_status_flags +{ + kSNVS_LP_ViolationFlag = SNVS_HPSVSR_SW_LPSV_MASK, /*!< Low Power section Security Violation */ + kSNVS_ZMK_EccFailFlag = SNVS_HPSVSR_ZMK_ECC_FAIL_MASK, /*!< Zeroizable Master Key Error Correcting Code Check + Failure */ + kSNVS_LP_SoftwareViolationFlag = SNVS_HPSVSR_SW_LPSV_MASK, /*!< LP Software Security Violation */ + kSNVS_FatalSoftwareViolationFlag = SNVS_HPSVSR_SW_FSV_MASK, /*!< Software Fatal Security Violation */ + kSNVS_SoftwareViolationFlag = SNVS_HPSVSR_SW_SV_MASK, /*!< Software Security Violation */ + kSNVS_Violation0Flag = SNVS_HPSVSR_SV0_MASK, /*!< Security Violation 0 */ + kSNVS_Violation1Flag = SNVS_HPSVSR_SV1_MASK, /*!< Security Violation 1 */ + kSNVS_Violation2Flag = SNVS_HPSVSR_SV2_MASK, /*!< Security Violation 2 */ + kSNVS_Violation3Flag = SNVS_HPSVSR_SV3_MASK, /*!< Security Violation 3 */ + kSNVS_Violation4Flag = SNVS_HPSVSR_SV4_MASK, /*!< Security Violation 4 */ + kSNVS_Violation5Flag = SNVS_HPSVSR_SV5_MASK, /*!< Security Violation 5 */ +} snvs_hp_sv_status_flags_t; + +/*! + * @brief Macro to make security violation flag + * + * Macro help to make security violation flag kSNVS_Violation0Flag to kSNVS_Violation5Flag, + * For example, SNVS_MAKE_HP_SV_FLAG(0) is kSNVS_Violation0Flag. + */ +#define SNVS_MAKE_HP_SV_FLAG(x) (1U << (SNVS_HPSVSR_SV0_SHIFT + (x))) + /*! @brief Structure is used to hold the date and time */ typedef struct _snvs_hp_rtc_datetime { @@ -83,7 +108,6 @@ typedef enum _snvs_hp_ssm_state kSNVS_SSMSecure = 0x0F, /*!< Secure */ } snvs_hp_ssm_state_t; - /******************************************************************************* * API ******************************************************************************/ @@ -518,7 +542,7 @@ static inline void SNVS_HP_LockHighAssuranceCounter(SNVS_Type *base) /*! * @brief Get the SNVS HP status flags. * - * The flags are returned as the OR'ed value of @ref snvs_hp_status_flags_t. + * The flags are returned as the OR'ed value of @ref snvs_hp_sgtatus_flags_t. * * @param base SNVS peripheral base address * @return The OR'ed value of status flags. @@ -544,6 +568,40 @@ static inline void SNVS_HP_ClearStatusFlags(SNVS_Type *base, uint32_t mask) base->HPSR = mask; } +/*! + * @brief Get the SNVS HP security violation status flags. + * + * The flags are returned as the OR'ed value of @ref snvs_hp_sv_status_flags_t. + * + * @param base SNVS peripheral base address + * @return The OR'ed value of security violation status flags. + */ +static inline uint32_t SNVS_HP_GetSecurityViolationStatusFlags(SNVS_Type *base) +{ + return base->HPSVSR; +} + +/*! + * @brief Clear the SNVS HP security violation status flags. + * + * The flags to clear are passed in as the OR'ed value of @ref snvs_hp_sv_status_flags_t. + * Only these flags could be cleared using this API. + * + * - @ref kSNVS_ZMK_EccFailFlag + * - @ref kSNVS_Violation0Flag + * - @ref kSNVS_Violation1Flag + * - @ref kSNVS_Violation2Flag + * - @ref kSNVS_Violation3Flag + * - @ref kSNVS_Violation4Flag + * - @ref kSNVS_Violation5Flag + * + * @param base SNVS peripheral base address + * @param mask OR'ed value of the flags to clear. + */ +static inline void SNVS_HP_ClearSecurityViolationStatusFlags(SNVS_Type *base, uint32_t mask) +{ + base->HPSVSR = mask; +} #if defined(__cplusplus) } diff --git a/ext/hal/nxp/mcux/drivers/imx/fsl_snvs_lp.c b/ext/hal/nxp/mcux/drivers/imx/fsl_snvs_lp.c index c5dddbfd20c..2fb8b71c88d 100644 --- a/ext/hal/nxp/mcux/drivers/imx/fsl_snvs_lp.c +++ b/ext/hal/nxp/mcux/drivers/imx/fsl_snvs_lp.c @@ -2,7 +2,7 @@ * Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright (c) 2017, NXP * All rights reserved. - * + * * SPDX-License-Identifier: BSD-3-Clause */ @@ -231,6 +231,14 @@ static uint32_t SNVS_LP_GetInstance(SNVS_Type *base) } #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +/*! + * brief Ungates the SNVS clock and configures the peripheral for basic operation. + * + * note This API should be called at the beginning of the application using the SNVS driver. + * + * param base SNVS peripheral base address + * param config Pointer to the user's SNVS configuration structure. + */ void SNVS_LP_Init(SNVS_Type *base) { #if (!(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && \ @@ -244,6 +252,11 @@ void SNVS_LP_Init(SNVS_Type *base) base->LPSR = SNVS_LPSR_PGD_MASK; } +/*! + * brief Deinit the SNVS LP section. + * + * param base SNVS peripheral base address + */ void SNVS_LP_Deinit(SNVS_Type *base) { #if (!(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && \ @@ -253,7 +266,14 @@ void SNVS_LP_Deinit(SNVS_Type *base) #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ } - +/*! + * brief Ungates the SNVS clock and configures the peripheral for basic operation. + * + * note This API should be called at the beginning of the application using the SNVS driver. + * + * param base SNVS peripheral base address + * param config Pointer to the user's SNVS configuration structure. + */ void SNVS_LP_SRTC_Init(SNVS_Type *base, const snvs_lp_srtc_config_t *config) { assert(config); @@ -279,6 +299,11 @@ void SNVS_LP_SRTC_Init(SNVS_Type *base, const snvs_lp_srtc_config_t *config) } } +/*! + * brief Stops the SRTC timer. + * + * param base SNVS peripheral base address + */ void SNVS_LP_SRTC_Deinit(SNVS_Type *base) { base->LPCR &= ~SNVS_LPCR_SRTC_ENV_MASK; @@ -290,10 +315,23 @@ void SNVS_LP_SRTC_Deinit(SNVS_Type *base) #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ } +/*! + * brief Fills in the SNVS_LP config struct with the default settings. + * + * The default values are as follows. + * code + * config->srtccalenable = false; + * config->srtccalvalue = 0U; + * endcode + * param config Pointer to the user's SNVS configuration structure. + */ void SNVS_LP_SRTC_GetDefaultConfig(snvs_lp_srtc_config_t *config) { assert(config); + /* Initializes the configure structure to zero. */ + memset(config, 0, sizeof(*config)); + config->srtcCalEnable = false; config->srtcCalValue = 0U; } @@ -313,6 +351,15 @@ static uint32_t SNVS_LP_SRTC_GetSeconds(SNVS_Type *base) return seconds; } +/*! + * brief Sets the SNVS SRTC date and time according to the given time structure. + * + * param base SNVS peripheral base address + * param datetime Pointer to the structure where the date and time details are stored. + * + * return kStatus_Success: Success in setting the time and starting the SNVS SRTC + * kStatus_InvalidArgument: Error because the datetime format is incorrect + */ status_t SNVS_LP_SRTC_SetDatetime(SNVS_Type *base, const snvs_lp_srtc_datetime_t *datetime) { assert(datetime); @@ -344,6 +391,12 @@ status_t SNVS_LP_SRTC_SetDatetime(SNVS_Type *base, const snvs_lp_srtc_datetime_t return kStatus_Success; } +/*! + * brief Gets the SNVS SRTC time and stores it in the given time structure. + * + * param base SNVS peripheral base address + * param datetime Pointer to the structure where the date and time details are stored. + */ void SNVS_LP_SRTC_GetDatetime(SNVS_Type *base, snvs_lp_srtc_datetime_t *datetime) { assert(datetime); @@ -351,6 +404,24 @@ void SNVS_LP_SRTC_GetDatetime(SNVS_Type *base, snvs_lp_srtc_datetime_t *datetime SNVS_LP_ConvertSecondsToDatetime(SNVS_LP_SRTC_GetSeconds(base), datetime); } +/*! + * brief Sets the SNVS SRTC alarm time. + * + * The function sets the SRTC alarm. It also checks whether the specified alarm + * time is greater than the present time. If not, the function does not set the alarm + * and returns an error. + * Please note, that SRTC alarm has limited resolution because only 32 most + * significant bits of SRTC counter are compared to SRTC Alarm register. + * If the alarm time is beyond SRTC resolution, the function does not set the alarm + * and returns an error. + * + * param base SNVS peripheral base address + * param alarmTime Pointer to the structure where the alarm time is stored. + * + * return kStatus_Success: success in setting the SNVS SRTC alarm + * kStatus_InvalidArgument: Error because the alarm datetime format is incorrect + * kStatus_Fail: Error because the alarm time has already passed or is beyond resolution + */ status_t SNVS_LP_SRTC_SetAlarm(SNVS_Type *base, const snvs_lp_srtc_datetime_t *alarmTime) { assert(alarmTime); @@ -389,6 +460,12 @@ status_t SNVS_LP_SRTC_SetAlarm(SNVS_Type *base, const snvs_lp_srtc_datetime_t *a return kStatus_Success; } +/*! + * brief Returns the SNVS SRTC alarm time. + * + * param base SNVS peripheral base address + * param datetime Pointer to the structure where the alarm date and time details are stored. + */ void SNVS_LP_SRTC_GetAlarm(SNVS_Type *base, snvs_lp_srtc_datetime_t *datetime) { assert(datetime); @@ -401,6 +478,14 @@ void SNVS_LP_SRTC_GetAlarm(SNVS_Type *base, snvs_lp_srtc_datetime_t *datetime) SNVS_LP_ConvertSecondsToDatetime(alarmSeconds, datetime); } +/*! + * brief Gets the SNVS status flags. + * + * param base SNVS peripheral base address + * + * return The status flags. This is the logical OR of members of the + * enumeration ::snvs_status_flags_t + */ uint32_t SNVS_LP_SRTC_GetStatusFlags(SNVS_Type *base) { uint32_t flags = 0U; @@ -413,6 +498,14 @@ uint32_t SNVS_LP_SRTC_GetStatusFlags(SNVS_Type *base) return flags; } +/*! + * brief Gets the enabled SNVS interrupts. + * + * param base SNVS peripheral base address + * + * return The enabled interrupts. This is the logical OR of members of the + * enumeration ::snvs_interrupt_enable_t + */ uint32_t SNVS_LP_SRTC_GetEnabledInterrupts(SNVS_Type *base) { uint32_t val = 0U; @@ -425,6 +518,13 @@ uint32_t SNVS_LP_SRTC_GetEnabledInterrupts(SNVS_Type *base) return val; } +/*! + * brief Enables the specified SNVS external tamper. + * + * param base SNVS peripheral base address + * param pin SNVS external tamper pin + * param polarity Polarity of external tamper + */ void SNVS_LP_EnableExternalTamper(SNVS_Type *base, snvs_lp_external_tamper_t pin, snvs_lp_external_tamper_polarity_t polarity) @@ -479,6 +579,12 @@ void SNVS_LP_EnableExternalTamper(SNVS_Type *base, } } +/*! + * brief Disables the specified SNVS external tamper. + * + * param base SNVS peripheral base address + * param pin SNVS external tamper pin + */ void SNVS_LP_DisableExternalTamper(SNVS_Type *base, snvs_lp_external_tamper_t pin) { switch (pin) @@ -520,6 +626,14 @@ void SNVS_LP_DisableExternalTamper(SNVS_Type *base, snvs_lp_external_tamper_t pi } } +/*! + * brief Returns status of the specified external tamper. + * + * param base SNVS peripheral base address + * param pin SNVS external tamper pin + * + * return The status flag. This is the enumeration ::snvs_external_tamper_status_t + */ snvs_lp_external_tamper_status_t SNVS_LP_GetExternalTamperStatus(SNVS_Type *base, snvs_lp_external_tamper_t pin) { snvs_lp_external_tamper_status_t status = kSNVS_TamperNotDetected; @@ -564,6 +678,12 @@ snvs_lp_external_tamper_status_t SNVS_LP_GetExternalTamperStatus(SNVS_Type *base return status; } +/*! + * brief Clears status of the specified external tamper. + * + * param base SNVS peripheral base address + * param pin SNVS external tamper pin + */ void SNVS_LP_ClearExternalTamperStatus(SNVS_Type *base, snvs_lp_external_tamper_t pin) { base->LPSR |= SNVS_LPSR_ET1D_MASK; @@ -607,6 +727,12 @@ void SNVS_LP_ClearExternalTamperStatus(SNVS_Type *base, snvs_lp_external_tamper_ } } +/*! + * brief Get the current Monotonic Counter. + * + * param base SNVS peripheral base address + * return Current Monotonic Counter value. + */ uint64_t SNVS_LP_GetMonotonicCounter(SNVS_Type *base) { uint32_t mc_lsb, mc_msb; @@ -617,11 +743,17 @@ uint64_t SNVS_LP_GetMonotonicCounter(SNVS_Type *base) return ((uint64_t)mc_msb << 32UL) | (uint64_t)mc_lsb; } +/*! + * brief Write Zeroizable Master Key (ZMK) to the SNVS registers. + * + * param base SNVS peripheral base address + * param ZMKey The ZMK write to the SNVS register. + */ void SNVS_LP_WriteZeroizableMasterKey(SNVS_Type *base, uint32_t ZMKey[SNVS_ZMK_REG_COUNT]) { uint8_t i = 0; - for (i=0; iLPZMKR[i] = ZMKey[i]; } diff --git a/ext/hal/nxp/mcux/drivers/imx/fsl_snvs_lp.h b/ext/hal/nxp/mcux/drivers/imx/fsl_snvs_lp.h index 97e56eb8d0e..bbf2ede9920 100644 --- a/ext/hal/nxp/mcux/drivers/imx/fsl_snvs_lp.h +++ b/ext/hal/nxp/mcux/drivers/imx/fsl_snvs_lp.h @@ -22,7 +22,7 @@ /*! @name Driver version */ /*@{*/ -#define FSL_SNVS_LP_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0 */ +#define FSL_SNVS_LP_DRIVER_VERSION (MAKE_VERSION(2, 1, 0)) /*!< Version 2.1.0 */ /*@}*/ #define SNVS_ZMK_REG_COUNT 8 /* 8 Zeroizable Master Key registers. */ diff --git a/ext/hal/nxp/mcux/drivers/imx/fsl_spdif.c b/ext/hal/nxp/mcux/drivers/imx/fsl_spdif.c index 2ec785ce97e..6b73432e74b 100644 --- a/ext/hal/nxp/mcux/drivers/imx/fsl_spdif.c +++ b/ext/hal/nxp/mcux/drivers/imx/fsl_spdif.c @@ -2,7 +2,7 @@ * Copyright (c) 2017, NXP Semiconductor, Inc. * All rights reserved. * - * + * * SPDX-License-Identifier: BSD-3-Clause */ @@ -13,7 +13,6 @@ #define FSL_COMPONENT_ID "platform.drivers.spdif" #endif - /******************************************************************************* * Definitations ******************************************************************************/ @@ -80,6 +79,20 @@ uint32_t SPDIF_GetInstance(SPDIF_Type *base) return instance; } +/*! + * brief Initializes the SPDIF peripheral. + * + * Ungates the SPDIF clock, resets the module, and configures SPDIF with a configuration structure. + * The configuration structure can be custom filled or set with default values by + * SPDIF_GetDefaultConfig(). + * + * note This API should be called at the beginning of the application to use + * the SPDIF driver. Otherwise, accessing the SPDIF module can cause a hard fault + * because the clock is not enabled. + * + * param base SPDIF base pointer + * param config SPDIF configuration structure. +*/ void SPDIF_Init(SPDIF_Type *base, const spdif_config_t *config) { uint32_t val = 0; @@ -112,6 +125,13 @@ void SPDIF_Init(SPDIF_Type *base, const spdif_config_t *config) base->STC = val; } +/*! + * brief De-initializes the SPDIF peripheral. + * + * This API gates the SPDIF clock. The SPDIF module can't operate unless SPDIF_Init is called to enable the clock. + * + * param base SPDIF base pointer +*/ void SPDIF_Deinit(SPDIF_Type *base) { SPDIF_TxEnable(base, false); @@ -121,8 +141,25 @@ void SPDIF_Deinit(SPDIF_Type *base) #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ } +/*! + * brief Sets the SPDIF configuration structure to default values. + * + * This API initializes the configuration structure for use in SPDIF_Init. + * The initialized structure can remain unchanged in SPDIF_Init, or it can be modified + * before calling SPDIF_Init. + * This is an example. + code + spdif_config_t config; + SPDIF_GetDefaultConfig(&config); + endcode + * + * param config pointer to master configuration structure + */ void SPDIF_GetDefaultConfig(spdif_config_t *config) { + /* Initializes the configure structure to zero. */ + memset(config, 0, sizeof(*config)); + config->isTxAutoSync = true; config->isRxAutoSync = true; config->DPLLClkSource = 1; @@ -135,6 +172,12 @@ void SPDIF_GetDefaultConfig(spdif_config_t *config) config->gain = kSPDIF_GAIN_8; } +/*! + * brief Enables/disables the SPDIF Tx. + * + * param base SPDIF base pointer + * param enable True means enable SPDIF Tx, false means disable. + */ void SPDIF_TxEnable(SPDIF_Type *base, bool enable) { uint32_t val = 0; @@ -156,6 +199,15 @@ void SPDIF_TxEnable(SPDIF_Type *base, bool enable) } } +/*! + * brief Configures the SPDIF Tx sample rate. + * + * The audio format can be changed at run-time. This function configures the sample rate. + * + * param base SPDIF base pointer. + * param sampleRate_Hz SPDIF sample rate frequency in Hz. + * param sourceClockFreq_Hz SPDIF tx clock source frequency in Hz. +*/ void SPDIF_TxSetSampleRate(SPDIF_Type *base, uint32_t sampleRate_Hz, uint32_t sourceClockFreq_Hz) { uint32_t clkDiv = sourceClockFreq_Hz / (sampleRate_Hz * 64); @@ -194,6 +246,15 @@ void SPDIF_TxSetSampleRate(SPDIF_Type *base, uint32_t sampleRate_Hz, uint32_t so } } +/*! + * brief Configures the SPDIF Rx audio format. + * + * The audio format can be changed at run-time. This function configures the sample rate and audio data + * format to be transferred. + * + * param base SPDIF base pointer. + * param clockSourceFreq_Hz SPDIF system clock frequency in hz. + */ uint32_t SPDIF_GetRxSampleRate(SPDIF_Type *base, uint32_t clockSourceFreq_Hz) { uint32_t gain = s_spdif_gain[((base->SRPC & SPDIF_SRPC_GAINSEL_MASK) >> SPDIF_SRPC_GAINSEL_SHIFT)]; @@ -214,6 +275,15 @@ uint32_t SPDIF_GetRxSampleRate(SPDIF_Type *base, uint32_t clockSourceFreq_Hz) return sampleRate; } +/*! + * brief Sends data using a blocking method. + * + * note This function blocks by polling until data is ready to be sent. + * + * param base SPDIF base pointer. + * param buffer Pointer to the data to be written. + * param size Bytes to be written. + */ void SPDIF_WriteBlocking(SPDIF_Type *base, uint8_t *buffer, uint32_t size) { assert(buffer); @@ -249,6 +319,15 @@ void SPDIF_WriteBlocking(SPDIF_Type *base, uint8_t *buffer, uint32_t size) } } +/*! + * brief Receives data using a blocking method. + * + * note This function blocks by polling until data is ready to be sent. + * + * param base SPDIF base pointer. + * param buffer Pointer to the data to be read. + * param size Bytes to be read. + */ void SPDIF_ReadBlocking(SPDIF_Type *base, uint8_t *buffer, uint32_t size) { assert(buffer); @@ -283,6 +362,17 @@ void SPDIF_ReadBlocking(SPDIF_Type *base, uint8_t *buffer, uint32_t size) } } +/*! + * brief Initializes the SPDIF Tx handle. + * + * This function initializes the Tx handle for the SPDIF Tx transactional APIs. Call + * this function once to get the handle initialized. + * + * param base SPDIF base pointer + * param handle SPDIF handle pointer. + * param callback Pointer to the user callback function. + * param userData User parameter passed to the callback function + */ void SPDIF_TransferTxCreateHandle(SPDIF_Type *base, spdif_handle_t *handle, spdif_transfer_callback_t callback, @@ -307,6 +397,17 @@ void SPDIF_TransferTxCreateHandle(SPDIF_Type *base, EnableIRQ(s_spdifIRQ[SPDIF_GetInstance(base)]); } +/*! + * brief Initializes the SPDIF Rx handle. + * + * This function initializes the Rx handle for the SPDIF Rx transactional APIs. Call + * this function once to get the handle initialized. + * + * param base SPDIF base pointer. + * param handle SPDIF handle pointer. + * param callback Pointer to the user callback function. + * param userData User parameter passed to the callback function. + */ void SPDIF_TransferRxCreateHandle(SPDIF_Type *base, spdif_handle_t *handle, spdif_transfer_callback_t callback, @@ -331,6 +432,21 @@ void SPDIF_TransferRxCreateHandle(SPDIF_Type *base, EnableIRQ(s_spdifIRQ[SPDIF_GetInstance(base)]); } +/*! + * brief Performs an interrupt non-blocking send transfer on SPDIF. + * + * note This API returns immediately after the transfer initiates. + * Call the SPDIF_TxGetTransferStatusIRQ to poll the transfer status and check whether + * the transfer is finished. If the return status is not kStatus_SPDIF_Busy, the transfer + * is finished. + * + * param base SPDIF base pointer. + * param handle Pointer to the spdif_handle_t structure which stores the transfer state. + * param xfer Pointer to the spdif_transfer_t structure. + * retval kStatus_Success Successfully started the data receive. + * retval kStatus_SPDIF_TxBusy Previous receive still not finished. + * retval kStatus_InvalidArgument The input parameter is invalid. + */ status_t SPDIF_TransferSendNonBlocking(SPDIF_Type *base, spdif_handle_t *handle, spdif_transfer_t *xfer) { assert(handle); @@ -359,6 +475,21 @@ status_t SPDIF_TransferSendNonBlocking(SPDIF_Type *base, spdif_handle_t *handle, return kStatus_Success; } +/*! + * brief Performs an interrupt non-blocking receive transfer on SPDIF. + * + * note This API returns immediately after the transfer initiates. + * Call the SPDIF_RxGetTransferStatusIRQ to poll the transfer status and check whether + * the transfer is finished. If the return status is not kStatus_SPDIF_Busy, the transfer + * is finished. + * + * param base SPDIF base pointer + * param handle Pointer to the spdif_handle_t structure which stores the transfer state. + * param xfer Pointer to the spdif_transfer_t structure. + * retval kStatus_Success Successfully started the data receive. + * retval kStatus_SPDIF_RxBusy Previous receive still not finished. + * retval kStatus_InvalidArgument The input parameter is invalid. + */ status_t SPDIF_TransferReceiveNonBlocking(SPDIF_Type *base, spdif_handle_t *handle, spdif_transfer_t *xfer) { assert(handle); @@ -390,6 +521,15 @@ status_t SPDIF_TransferReceiveNonBlocking(SPDIF_Type *base, spdif_handle_t *hand return kStatus_Success; } +/*! + * brief Gets a set byte count. + * + * param base SPDIF base pointer. + * param handle Pointer to the spdif_handle_t structure which stores the transfer state. + * param count Bytes count sent. + * retval kStatus_Success Succeed get the transfer count. + * retval kStatus_NoTransferInProgress There is not a non-blocking transaction currently in progress. + */ status_t SPDIF_TransferGetSendCount(SPDIF_Type *base, spdif_handle_t *handle, size_t *count) { assert(handle); @@ -408,6 +548,15 @@ status_t SPDIF_TransferGetSendCount(SPDIF_Type *base, spdif_handle_t *handle, si return status; } +/*! + * brief Gets a received byte count. + * + * param base SPDIF base pointer. + * param handle Pointer to the spdif_handle_t structure which stores the transfer state. + * param count Bytes count received. + * retval kStatus_Success Succeed get the transfer count. + * retval kStatus_NoTransferInProgress There is not a non-blocking transaction currently in progress. + */ status_t SPDIF_TransferGetReceiveCount(SPDIF_Type *base, spdif_handle_t *handle, size_t *count) { assert(handle); @@ -426,6 +575,15 @@ status_t SPDIF_TransferGetReceiveCount(SPDIF_Type *base, spdif_handle_t *handle, return status; } +/*! + * brief Aborts the current send. + * + * note This API can be called any time when an interrupt non-blocking transfer initiates + * to abort the transfer early. + * + * param base SPDIF base pointer. + * param handle Pointer to the spdif_handle_t structure which stores the transfer state. + */ void SPDIF_TransferAbortSend(SPDIF_Type *base, spdif_handle_t *handle) { assert(handle); @@ -441,6 +599,15 @@ void SPDIF_TransferAbortSend(SPDIF_Type *base, spdif_handle_t *handle) handle->queueUser = 0; } +/*! + * brief Aborts the current IRQ receive. + * + * note This API can be called when an interrupt non-blocking transfer initiates + * to abort the transfer early. + * + * param base SPDIF base pointer + * param handle Pointer to the spdif_handle_t structure which stores the transfer state. + */ void SPDIF_TransferAbortReceive(SPDIF_Type *base, spdif_handle_t *handle) { assert(handle); @@ -457,6 +624,12 @@ void SPDIF_TransferAbortReceive(SPDIF_Type *base, spdif_handle_t *handle) handle->queueUser = 0; } +/*! + * brief Tx interrupt handler. + * + * param base SPDIF base pointer. + * param handle Pointer to the spdif_handle_t structure. + */ void SPDIF_TransferTxHandleIRQ(SPDIF_Type *base, spdif_handle_t *handle) { assert(handle); @@ -513,6 +686,12 @@ void SPDIF_TransferTxHandleIRQ(SPDIF_Type *base, spdif_handle_t *handle) } } +/*! + * brief Tx interrupt handler. + * + * param base SPDIF base pointer. + * param handle Pointer to the spdif_handle_t structure. + */ void SPDIF_TransferRxHandleIRQ(SPDIF_Type *base, spdif_handle_t *handle) { assert(handle); diff --git a/ext/hal/nxp/mcux/drivers/imx/fsl_spdif_edma.c b/ext/hal/nxp/mcux/drivers/imx/fsl_spdif_edma.c index 418393c957d..363c46ff3c8 100644 --- a/ext/hal/nxp/mcux/drivers/imx/fsl_spdif_edma.c +++ b/ext/hal/nxp/mcux/drivers/imx/fsl_spdif_edma.c @@ -229,6 +229,20 @@ static status_t SPDIF_SubmitTransfer(edma_handle_t *handle, const edma_transfer_ return kStatus_Success; } +/*! + * brief Initializes the SPDIF eDMA handle. + * + * This function initializes the SPDIF master DMA handle, which can be used for other SPDIF master transactional APIs. + * Usually, for a specified SPDIF instance, call this API once to get the initialized handle. + * + * param base SPDIF base pointer. + * param handle SPDIF eDMA handle pointer. + * param base SPDIF peripheral base address. + * param callback Pointer to user callback function. + * param userData User parameter passed to the callback function. + * param dmaLeftHandle eDMA handle pointer for left channel, this handle shall be static allocated by users. + * param dmaRightHandle eDMA handle pointer for right channel, this handle shall be static allocated by users. + */ void SPDIF_TransferTxCreateHandleEDMA(SPDIF_Type *base, spdif_edma_handle_t *handle, spdif_edma_callback_t callback, @@ -265,6 +279,20 @@ void SPDIF_TransferTxCreateHandleEDMA(SPDIF_Type *base, EDMA_SetCallback(dmaRightHandle, SPDIF_TxEDMACallback, &s_edmaPrivateHandle[instance][0]); } +/*! + * brief Initializes the SPDIF Rx eDMA handle. + * + * This function initializes the SPDIF slave DMA handle, which can be used for other SPDIF master transactional APIs. + * Usually, for a specified SPDIF instance, call this API once to get the initialized handle. + * + * param base SPDIF base pointer. + * param handle SPDIF eDMA handle pointer. + * param base SPDIF peripheral base address. + * param callback Pointer to user callback function. + * param userData User parameter passed to the callback function. + * param dmaLeftHandle eDMA handle pointer for left channel, this handle shall be static allocated by users. + * param dmaRightHandle eDMA handle pointer for right channel, this handle shall be static allocated by users. + */ void SPDIF_TransferRxCreateHandleEDMA(SPDIF_Type *base, spdif_edma_handle_t *handle, spdif_edma_callback_t callback, @@ -300,6 +328,19 @@ void SPDIF_TransferRxCreateHandleEDMA(SPDIF_Type *base, EDMA_SetCallback(dmaRightHandle, SPDIF_RxEDMACallback, &s_edmaPrivateHandle[instance][1]); } +/*! + * brief Performs a non-blocking SPDIF transfer using DMA. + * + * note This interface returns immediately after the transfer initiates. Call + * SPDIF_GetTransferStatus to poll the transfer status and check whether the SPDIF transfer is finished. + * + * param base SPDIF base pointer. + * param handle SPDIF eDMA handle pointer. + * param xfer Pointer to the DMA transfer structure. + * retval kStatus_Success Start a SPDIF eDMA send successfully. + * retval kStatus_InvalidArgument The input argument is invalid. + * retval kStatus_TxBusy SPDIF is busy sending data. + */ status_t SPDIF_TransferSendEDMA(SPDIF_Type *base, spdif_edma_handle_t *handle, spdif_edma_transfer_t *xfer) { assert(handle && xfer); @@ -355,6 +396,19 @@ status_t SPDIF_TransferSendEDMA(SPDIF_Type *base, spdif_edma_handle_t *handle, s return kStatus_Success; } +/*! + * brief Performs a non-blocking SPDIF receive using eDMA. + * + * note This interface returns immediately after the transfer initiates. Call + * the SPDIF_GetReceiveRemainingBytes to poll the transfer status and check whether the SPDIF transfer is finished. + * + * param base SPDIF base pointer + * param handle SPDIF eDMA handle pointer. + * param xfer Pointer to DMA transfer structure. + * retval kStatus_Success Start a SPDIF eDMA receive successfully. + * retval kStatus_InvalidArgument The input argument is invalid. + * retval kStatus_RxBusy SPDIF is busy receiving data. + */ status_t SPDIF_TransferReceiveEDMA(SPDIF_Type *base, spdif_edma_handle_t *handle, spdif_edma_transfer_t *xfer) { assert(handle && xfer); @@ -411,6 +465,12 @@ status_t SPDIF_TransferReceiveEDMA(SPDIF_Type *base, spdif_edma_handle_t *handle return kStatus_Success; } +/*! + * brief Aborts a SPDIF transfer using eDMA. + * + * param base SPDIF base pointer. + * param handle SPDIF eDMA handle pointer. + */ void SPDIF_TransferAbortSendEDMA(SPDIF_Type *base, spdif_edma_handle_t *handle) { assert(handle); @@ -432,6 +492,12 @@ void SPDIF_TransferAbortSendEDMA(SPDIF_Type *base, spdif_edma_handle_t *handle) handle->state = kSPDIF_Idle; } +/*! + * brief Aborts a SPDIF receive using eDMA. + * + * param base SPDIF base pointer + * param handle SPDIF eDMA handle pointer. + */ void SPDIF_TransferAbortReceiveEDMA(SPDIF_Type *base, spdif_edma_handle_t *handle) { assert(handle); @@ -453,6 +519,15 @@ void SPDIF_TransferAbortReceiveEDMA(SPDIF_Type *base, spdif_edma_handle_t *handl handle->state = kSPDIF_Idle; } +/*! + * brief Gets byte count sent by SPDIF. + * + * param base SPDIF base pointer. + * param handle SPDIF eDMA handle pointer. + * param count Bytes count sent by SPDIF. + * retval kStatus_Success Succeed get the transfer count. + * retval kStatus_NoTransferInProgress There is no non-blocking transaction in progress. + */ status_t SPDIF_TransferGetSendCountEDMA(SPDIF_Type *base, spdif_edma_handle_t *handle, size_t *count) { assert(handle); @@ -473,6 +548,15 @@ status_t SPDIF_TransferGetSendCountEDMA(SPDIF_Type *base, spdif_edma_handle_t *h return status; } +/*! + * brief Gets byte count received by SPDIF. + * + * param base SPDIF base pointer + * param handle SPDIF eDMA handle pointer. + * param count Bytes count received by SPDIF. + * retval kStatus_Success Succeed get the transfer count. + * retval kStatus_NoTransferInProgress There is no non-blocking transaction in progress. + */ status_t SPDIF_TransferGetReceiveCountEDMA(SPDIF_Type *base, spdif_edma_handle_t *handle, size_t *count) { assert(handle); diff --git a/ext/hal/nxp/mcux/drivers/imx/fsl_src.c b/ext/hal/nxp/mcux/drivers/imx/fsl_src.c index a00691b6c75..10af22893aa 100644 --- a/ext/hal/nxp/mcux/drivers/imx/fsl_src.c +++ b/ext/hal/nxp/mcux/drivers/imx/fsl_src.c @@ -2,7 +2,7 @@ * Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP * All rights reserved. - * + * * SPDX-License-Identifier: BSD-3-Clause */ @@ -13,7 +13,6 @@ #define FSL_COMPONENT_ID "platform.drivers.src" #endif - /******************************************************************************* * Prototypes ******************************************************************************/ @@ -26,6 +25,12 @@ * Code ******************************************************************************/ +/*! + * brief Clear the status flags of SRC. + * + * param base SRC peripheral base address. + * param Mask value of status flags to be cleared, see to #_src_reset_status_flags. + */ void SRC_ClearResetStatusFlags(SRC_Type *base, uint32_t flags) { uint32_t tmp32 = base->SRSR; diff --git a/ext/hal/nxp/mcux/drivers/imx/fsl_tempmon.c b/ext/hal/nxp/mcux/drivers/imx/fsl_tempmon.c index 6e176c13b39..2f2b08dde32 100644 --- a/ext/hal/nxp/mcux/drivers/imx/fsl_tempmon.c +++ b/ext/hal/nxp/mcux/drivers/imx/fsl_tempmon.c @@ -44,6 +44,12 @@ static uint32_t s_roomC_hotC; /*!< The value of s_roomCount minus s_hotCount.*/ /******************************************************************************* * Code ******************************************************************************/ +/*! + * brief Initializes the TEMPMON module. + * + * param base TEMPMON base pointer + * param config Pointer to configuration structure. + */ void TEMPMON_Init(TEMPMON_Type *base, const tempmon_config_t *config) { assert(NULL != config); @@ -72,15 +78,35 @@ void TEMPMON_Init(TEMPMON_Type *base, const tempmon_config_t *config) TEMPMON_SetTempAlarm(base, config->lowAlarmTemp, kTEMPMON_LowAlarmMode); } +/*! + * brief Deinitializes the TEMPMON module. + * + * param base TEMPMON base pointer + */ void TEMPMON_Deinit(TEMPMON_Type *base) { base->TEMPSENSE0 |= TEMPMON_TEMPSENSE0_POWER_DOWN_MASK; } +/*! + * brief Gets the default configuration structure. + * + * This function initializes the TEMPMON configuration structure to a default value. The default + * values are: + * tempmonConfig->frequency = 0x02U; + * tempmonConfig->highAlarmTemp = 44U; + * tempmonConfig->panicAlarmTemp = 90U; + * tempmonConfig->lowAlarmTemp = 39U; + * + * param config Pointer to a configuration structure. + */ void TEMPMON_GetDefaultConfig(tempmon_config_t *config) { assert(config); + /* Initializes the configure structure to zero. */ + memset(config, 0, sizeof(*config)); + /* Default measure frequency */ config->frequency = 0x03U; /* Default high alarm temperature */ @@ -91,6 +117,12 @@ void TEMPMON_GetDefaultConfig(tempmon_config_t *config) config->lowAlarmTemp = 20U; } +/*! + * brief Get current temperature with the fused temperature calibration data. + * + * param base TEMPMON base pointer + * return current temperature with degrees Celsius. + */ float TEMPMON_GetCurrentTemperature(TEMPMON_Type *base) { /* Check arguments */ @@ -112,6 +144,13 @@ float TEMPMON_GetCurrentTemperature(TEMPMON_Type *base) return tmeas; } +/*! + * brief Set the temperature count (raw sensor output) that will generate an alarm interrupt. + * + * param base TEMPMON base pointer + * param tempVal The alarm temperature with degrees Celsius + * param alarmMode The alarm mode. + */ void TEMPMON_SetTempAlarm(TEMPMON_Type *base, uint32_t tempVal, tempmon_alarm_mode alarmMode) { /* Check arguments */ diff --git a/ext/hal/nxp/mcux/drivers/imx/fsl_trng.c b/ext/hal/nxp/mcux/drivers/imx/fsl_trng.c index a182e5e7f53..5590a883c55 100644 --- a/ext/hal/nxp/mcux/drivers/imx/fsl_trng.c +++ b/ext/hal/nxp/mcux/drivers/imx/fsl_trng.c @@ -2,7 +2,7 @@ * Copyright (c) 2015, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP * All rights reserved. - * + * * SPDX-License-Identifier: BSD-3-Clause */ #include "fsl_trng.h" @@ -1222,6 +1222,44 @@ static uint32_t trng_GetInstance(TRNG_Type *base) * Description : Initializes user configuration structure to default settings. * *END*************************************************************************/ +/*! + * brief Initializes the user configuration structure to default values. + * + * This function initializes the configuration structure to default values. The default + * values are as follows. + * code + * user_config->lock = 0; + * user_config->clockMode = kTRNG_ClockModeRingOscillator; + * user_config->ringOscDiv = kTRNG_RingOscDiv0; Or to other kTRNG_RingOscDiv[2|8] depending on the platform. + * user_config->sampleMode = kTRNG_SampleModeRaw; + * user_config->entropyDelay = 3200; + * user_config->sampleSize = 2500; + * user_config->sparseBitLimit = TRNG_USER_CONFIG_DEFAULT_SPARSE_BIT_LIMIT; + * user_config->retryCount = 63; + * user_config->longRunMaxLimit = 34; + * user_config->monobitLimit.maximum = 1384; + * user_config->monobitLimit.minimum = 1116; + * user_config->runBit1Limit.maximum = 405; + * user_config->runBit1Limit.minimum = 227; + * user_config->runBit2Limit.maximum = 220; + * user_config->runBit2Limit.minimum = 98; + * user_config->runBit3Limit.maximum = 125; + * user_config->runBit3Limit.minimum = 37; + * user_config->runBit4Limit.maximum = 75; + * user_config->runBit4Limit.minimum = 11; + * user_config->runBit5Limit.maximum = 47; + * user_config->runBit5Limit.minimum = 1; + * user_config->runBit6PlusLimit.maximum = 47; + * user_config->runBit6PlusLimit.minimum = 1; + * user_config->pokerLimit.maximum = 26912; + * user_config->pokerLimit.minimum = 24445; + * user_config->frequencyCountLimit.maximum = 25600; + * user_config->frequencyCountLimit.minimum = 1600; + * endcode + * + * param user_config User configuration structure. + * return If successful, returns the kStatus_TRNG_Success. Otherwise, it returns an error. + */ status_t TRNG_GetDefaultConfig(trng_config_t *userConfig) { status_t result; @@ -1498,6 +1536,16 @@ static uint32_t trng_ReadEntropy(TRNG_Type *base, uint32_t index) return data; } +/*! + * brief Initializes the TRNG. + * + * This function initializes the TRNG. + * When called, the TRNG entropy generation starts immediately. + * + * param base TRNG base address + * param userConfig Pointer to the initialization configuration structure. + * return If successful, returns the kStatus_TRNG_Success. Otherwise, it returns an error. + */ status_t TRNG_Init(TRNG_Type *base, const trng_config_t *userConfig) { status_t result; @@ -1528,6 +1576,8 @@ status_t TRNG_Init(TRNG_Type *base, const trng_config_t *userConfig) TRNG_WR_MCTL_TRNG_ACC(base, 1); #endif /* !FSL_FEATURE_TRNG_HAS_NO_TRNG_ACC */ + (void)trng_ReadEntropy(base, (TRNG_ENT_COUNT - 1)); + if (userConfig->lock == 1) /* Disable programmability of TRNG registers. */ { TRNG_WR_SEC_CFG_NO_PRGM(base, 1); @@ -1544,6 +1594,13 @@ status_t TRNG_Init(TRNG_Type *base, const trng_config_t *userConfig) return result; } +/*! + * brief Shuts down the TRNG. + * + * This function shuts down the TRNG. + * + * param base TRNG base address. + */ void TRNG_Deinit(TRNG_Type *base) { /* Check input parameters.*/ @@ -1569,6 +1626,16 @@ void TRNG_Deinit(TRNG_Type *base) } } +/*! + * brief Gets random data. + * + * This function gets random data from the TRNG. + * + * param base TRNG base address. + * param data Pointer address used to store random data. + * param dataSize Size of the buffer pointed by the data parameter. + * return random data + */ status_t TRNG_GetRandomData(TRNG_Type *base, void *data, size_t dataSize) { status_t result = kStatus_Success; diff --git a/ext/hal/nxp/mcux/drivers/imx/fsl_trng.h b/ext/hal/nxp/mcux/drivers/imx/fsl_trng.h index e29ab0c60c8..ec58261747a 100644 --- a/ext/hal/nxp/mcux/drivers/imx/fsl_trng.h +++ b/ext/hal/nxp/mcux/drivers/imx/fsl_trng.h @@ -2,7 +2,7 @@ * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. * Copyright 2016-2018 NXP * All rights reserved. - * + * * SPDX-License-Identifier: BSD-3-Clause */ #ifndef _FSL_TRNG_DRIVER_H_ @@ -17,25 +17,26 @@ * @{ */ - /******************************************************************************* * Definitions *******************************************************************************/ /*! @name Driver version */ /*@{*/ -/*! @brief TRNG driver version 2.0.2. +/*! @brief TRNG driver version 2.0.3. * - * Current version: 2.0.2 + * Current version: 2.0.3 * * Change log: + * - Version 2.0.3 + * - update TRNG_Init to restart entropy generation * - Version 2.0.2 * - fix MISRA issues * - Version 2.0.1 * - add support for KL8x and KL28Z * - update default OSCDIV for K81 to divide by 2 */ -#define FSL_TRNG_DRIVER_VERSION (MAKE_VERSION(2, 0, 2)) +#define FSL_TRNG_DRIVER_VERSION (MAKE_VERSION(2, 0, 3)) /*@}*/ /*! @brief TRNG sample mode. Used by trng_config_t. */ diff --git a/ext/hal/nxp/mcux/drivers/imx/fsl_tsc.c b/ext/hal/nxp/mcux/drivers/imx/fsl_tsc.c index 5ceae13b01a..33037f1c329 100644 --- a/ext/hal/nxp/mcux/drivers/imx/fsl_tsc.c +++ b/ext/hal/nxp/mcux/drivers/imx/fsl_tsc.c @@ -55,6 +55,12 @@ static uint32_t TSC_GetInstance(TSC_Type *base) return instance; } +/*! +* brief Initialize the TSC module. +* +* param base TSC peripheral base address. +* param config Pointer to "tsc_config_t" structure. +*/ void TSC_Init(TSC_Type *base, const tsc_config_t *config) { assert(NULL != config); @@ -78,6 +84,11 @@ void TSC_Init(TSC_Type *base, const tsc_config_t *config) base->PRE_CHARGE_TIME = TSC_PRE_CHARGE_TIME_PRE_CHARGE_TIME(config->prechargeTime); } +/*! +* brief De-initializes the TSC module. +* +* param base TSC peripheral base address. +*/ void TSC_Deinit(TSC_Type *base) { #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) @@ -86,14 +97,40 @@ void TSC_Deinit(TSC_Type *base) #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ } +/*! +* brief Gets an available pre-defined settings for the controller's configuration. +* +* This function initializes the converter configuration structure with available settings. +* The default values of measureDelayTime and prechargeTime is tested on LCD8000-43T screen and work normally. +* The default values are: +* code +* config->enableAutoMeausre = false; +* config->measureDelayTime = 0xFFFFU; +* config->prechargeTime = 0xFFFFU; +* config->detectionMode = kTSC_4WireDetectionMode; +* endCode +* param config Pointer to "tsc_config_t" structure. +*/ void TSC_GetDefaultConfig(tsc_config_t *config) { + /* Initializes the configure structure to zero. */ + memset(config, 0, sizeof(*config)); + config->enableAutoMeasure = false; config->measureDelayTime = 0xFFFFU; config->prechargeTime = 0xFFFFU; config->detectionMode = kTSC_Detection4WireMode; } +/*! +* brief Get Y coordinate value or X coordinate value. The value is an ADC conversion value. +* +* param base TSC peripheral base address. +* param selection Select alternative measure value which is Y coordinate value or X coordinate value. +* See "tsc_corrdinate_value_selection_t". +* return If selection is "kTSC_XCoordinateValueSelection", the API returns x-coordinate vlaue. +* If selection is "kTSC_YCoordinateValueSelection", the API returns y-coordinate vlaue. +*/ uint32_t TSC_GetMeasureValue(TSC_Type *base, tsc_corrdinate_value_selection_t selection) { uint32_t tmp32 = 0; @@ -112,6 +149,15 @@ uint32_t TSC_GetMeasureValue(TSC_Type *base, tsc_corrdinate_value_selection_t se return tmp32; } +/*! +* brief Send hardware trigger signal to ADC in debug mode. The trigger signal must last at least 1 ips clock period. +* +* param base TSC peripheral base address. +* param hwts Hardware trigger select signal, select which channel to start conversion. See "tsc_trigger_signal_t". +* On ADC side, HWTS = 1 << x indicates the x logic channel is selected to start hardware ADC conversion. +* param enable Switcher of the trigger signal. "true" means generate trigger signal, "false" means don't generate +* trigger signal. +*/ void TSC_DebugTriggerSignalToADC(TSC_Type *base, tsc_trigger_signal_t hwts, bool enable) { if (enable) @@ -128,6 +174,13 @@ void TSC_DebugTriggerSignalToADC(TSC_Type *base, tsc_trigger_signal_t hwts, bool } } +/*! +* brief Enable/Disable detection in debug mode. +* +* param base TSC peripheral base address. +* param detectionMode Set detect mode. See "tsc_detection_mode_t" +* param enable Switcher of detect enable. "true" means enable detection, "false" means disable detection. +*/ void TSC_DebugEnableDetection(TSC_Type *base, tsc_detection_mode_t detectionMode, bool enable) { if (detectionMode == kTSC_Detection4WireMode) @@ -157,6 +210,13 @@ void TSC_DebugEnableDetection(TSC_Type *base, tsc_detection_mode_t detectionMode } } +/*! +* brief Set TSC port mode in debug mode.(pull down, pull up and 200k-pull up) +* +* param base TSC peripheral base address. +* param port TSC controller ports. +* param mode TSC port mode.(pull down, pull up and 200k-pull up) +*/ void TSC_DebugSetPortMode(TSC_Type *base, tsc_port_source_t port, tsc_port_mode_t mode) { uint32_t tmp32; diff --git a/ext/hal/nxp/mcux/drivers/imx/fsl_usdhc.c b/ext/hal/nxp/mcux/drivers/imx/fsl_usdhc.c index 3bc22e82ad2..60f4cc6ab4c 100644 --- a/ext/hal/nxp/mcux/drivers/imx/fsl_usdhc.c +++ b/ext/hal/nxp/mcux/drivers/imx/fsl_usdhc.c @@ -56,8 +56,12 @@ static void USDHC_SetTransferInterrupt(USDHC_Type *base, bool usingInterruptSign * @param base USDHC peripheral base address. * @param data Data to be transferred. * @param flag data present flag + * @param enDMA DMA enable flag */ -static status_t USDHC_SetDataTransferConfig(USDHC_Type *base, usdhc_data_t *data, uint32_t *dataPresentFlag); +static status_t USDHC_SetDataTransferConfig(USDHC_Type *base, + usdhc_data_t *data, + uint32_t *dataPresentFlag, + bool enDMA); /*! * @brief Receive command response @@ -237,7 +241,7 @@ static void USDHC_SetTransferInterrupt(USDHC_Type *base, bool usingInterruptSign } } -static status_t USDHC_SetDataTransferConfig(USDHC_Type *base, usdhc_data_t *data, uint32_t *dataPresentFlag) +static status_t USDHC_SetDataTransferConfig(USDHC_Type *base, usdhc_data_t *data, uint32_t *dataPresentFlag, bool enDMA) { uint32_t mixCtrl = base->MIX_CTRL; @@ -311,12 +315,23 @@ static status_t USDHC_SetDataTransferConfig(USDHC_Type *base, usdhc_data_t *data /* data present flag */ *dataPresentFlag |= kUSDHC_DataPresentFlag; + /* Disable useless interrupt */ + if (enDMA) + { + base->INT_SIGNAL_EN &= ~(kUSDHC_BufferWriteReadyFlag | kUSDHC_BufferReadReadyFlag | kUSDHC_DmaCompleteFlag); + base->INT_STATUS_EN &= ~(kUSDHC_BufferWriteReadyFlag | kUSDHC_BufferReadReadyFlag | kUSDHC_DmaCompleteFlag); + } + else + { + base->INT_SIGNAL_EN |= kUSDHC_BufferWriteReadyFlag | kUSDHC_BufferReadReadyFlag; + base->INT_STATUS_EN |= kUSDHC_BufferWriteReadyFlag | kUSDHC_BufferReadReadyFlag; + } } else { /* clear data flags */ mixCtrl &= ~(USDHC_MIX_CTRL_MSBSEL_MASK | USDHC_MIX_CTRL_BCEN_MASK | USDHC_MIX_CTRL_DTDSEL_MASK | - USDHC_MIX_CTRL_AC12EN_MASK); + USDHC_MIX_CTRL_AC12EN_MASK | USDHC_MIX_CTRL_AC23EN_MASK); if (base->PRES_STATE & kUSDHC_CommandInhibitFlag) { @@ -615,6 +630,12 @@ static status_t USDHC_WriteByDataPortBlocking(USDHC_Type *base, usdhc_data_t *da return error; } +/*! +* brief send command function +* +* param base USDHC peripheral base address. +* param command configuration +*/ void USDHC_SendCommand(USDHC_Type *base, usdhc_command_t *command) { assert(NULL != command); @@ -770,6 +791,26 @@ static status_t USDHC_TransferDataBlocking(USDHC_Type *base, usdhc_data_t *data, return error; } +/*! + * brief USDHC module initialization function. + * + * Configures the USDHC according to the user configuration. + * + * Example: + code + usdhc_config_t config; + config.cardDetectDat3 = false; + config.endianMode = kUSDHC_EndianModeLittle; + config.dmaMode = kUSDHC_DmaModeAdma2; + config.readWatermarkLevel = 128U; + config.writeWatermarkLevel = 128U; + USDHC_Init(USDHC, &config); + endcode + * + * param base USDHC peripheral base address. + * param config USDHC configuration information. + * retval kStatus_Success Operate successfully. + */ void USDHC_Init(USDHC_Type *base, const usdhc_config_t *config) { assert(config); @@ -819,6 +860,11 @@ void USDHC_Init(USDHC_Type *base, const usdhc_config_t *config) USDHC_SetTransferInterrupt(base, false); } +/*! + * brief Deinitializes the USDHC. + * + * param base USDHC peripheral base address. + */ void USDHC_Deinit(USDHC_Type *base) { #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) @@ -827,6 +873,15 @@ void USDHC_Deinit(USDHC_Type *base) #endif } +/*! + * brief Resets the USDHC. + * + * param base USDHC peripheral base address. + * param mask The reset type mask(_usdhc_reset). + * param timeout Timeout for reset. + * retval true Reset successfully. + * retval false Reset failed. + */ bool USDHC_Reset(USDHC_Type *base, uint32_t mask, uint32_t timeout) { base->SYS_CTRL |= (mask & (USDHC_SYS_CTRL_RSTA_MASK | USDHC_SYS_CTRL_RSTC_MASK | USDHC_SYS_CTRL_RSTD_MASK)); @@ -843,6 +898,12 @@ bool USDHC_Reset(USDHC_Type *base, uint32_t mask, uint32_t timeout) return ((!timeout) ? false : true); } +/*! + * brief Gets the capability information. + * + * param base USDHC peripheral base address. + * param capability Structure to save capability information. + */ void USDHC_GetCapability(USDHC_Type *base, usdhc_capability_t *capability) { assert(capability); @@ -867,6 +928,15 @@ void USDHC_GetCapability(USDHC_Type *base, usdhc_capability_t *capability) capability->flags |= (kUSDHC_Support4BitFlag | kUSDHC_Support8BitFlag); } +/*! + * brief Sets the SD bus clock frequency. + * + * param base USDHC peripheral base address. + * param srcClock_Hz USDHC source clock frequency united in Hz. + * param busClock_Hz SD bus clock frequency united in Hz. + * + * return The nearest frequency of busClock_Hz configured to SD bus. + */ uint32_t USDHC_SetSdClock(USDHC_Type *base, uint32_t srcClock_Hz, uint32_t busClock_Hz) { assert(srcClock_Hz != 0U); @@ -969,6 +1039,17 @@ uint32_t USDHC_SetSdClock(USDHC_Type *base, uint32_t srcClock_Hz, uint32_t busCl return nearestFrequency; } +/*! + * brief Sends 80 clocks to the card to set it to the active state. + * + * This function must be called each time the card is inserted to ensure that the card can receive the command + * correctly. + * + * param base USDHC peripheral base address. + * param timeout Timeout to initialize card. + * retval true Set card active successfully. + * retval false Set card active failed. + */ bool USDHC_SetCardActive(USDHC_Type *base, uint32_t timeout) { base->SYS_CTRL |= USDHC_SYS_CTRL_INITA_MASK; @@ -985,6 +1066,13 @@ bool USDHC_SetCardActive(USDHC_Type *base, uint32_t timeout) return ((!timeout) ? false : true); } +/*! + * brief the enable/disable DDR mode + * + * param base USDHC peripheral base address. + * param enable/disable flag + * param nibble position + */ void USDHC_EnableDDRMode(USDHC_Type *base, bool enable, uint32_t nibblePos) { uint32_t prescaler = (base->SYS_CTRL & USDHC_SYS_CTRL_SDCLKFS_MASK) >> USDHC_SYS_CTRL_SDCLKFS_SHIFT; @@ -1012,6 +1100,24 @@ void USDHC_EnableDDRMode(USDHC_Type *base, bool enable, uint32_t nibblePos) base->SYS_CTRL = (base->SYS_CTRL & (~USDHC_SYS_CTRL_SDCLKFS_MASK)) | USDHC_SYS_CTRL_SDCLKFS(prescaler); } +/*! + * brief Configures the MMC boot feature. + * + * Example: + code + usdhc_boot_config_t config; + config.ackTimeoutCount = 4; + config.bootMode = kUSDHC_BootModeNormal; + config.blockCount = 5; + config.enableBootAck = true; + config.enableBoot = true; + config.enableAutoStopAtBlockGap = true; + USDHC_SetMmcBootConfig(USDHC, &config); + endcode + * + * param base USDHC peripheral base address. + * param config The MMC boot configuration information. + */ void USDHC_SetMmcBootConfig(USDHC_Type *base, const usdhc_boot_config_t *config) { assert(config); @@ -1044,6 +1150,18 @@ void USDHC_SetMmcBootConfig(USDHC_Type *base, const usdhc_boot_config_t *config) base->MMC_BOOT = mmcboot; } +/*! + * brief Sets the ADMA1 descriptor table configuration. + * + * param admaTable Adma table address. + * param admaTableWords Adma table length. + * param dataBufferAddr Data buffer address. + * param dataBytes Data length. + * param flags ADAM descriptor flag, used to indicate to create multiple or single descriptor, please + * reference _usdhc_adma_flag. + * retval kStatus_OutOfRange ADMA descriptor table length isn't enough to describe data. + * retval kStatus_Success Operate successfully. + */ status_t USDHC_SetADMA1Descriptor( uint32_t *admaTable, uint32_t admaTableWords, const uint32_t *dataBufferAddr, uint32_t dataBytes, uint32_t flags) { @@ -1118,6 +1236,18 @@ status_t USDHC_SetADMA1Descriptor( return kStatus_Success; } +/*! + * brief Sets the ADMA2 descriptor table configuration. + * + * param admaTable Adma table address. + * param admaTableWords Adma table length. + * param dataBufferAddr Data buffer address. + * param dataBytes Data Data length. + * param flags ADAM descriptor flag, used to indicate to create multiple or single descriptor, please + * reference _usdhc_adma_flag. + * retval kStatus_OutOfRange ADMA descriptor table length isn't enough to describe data. + * retval kStatus_Success Operate successfully. + */ status_t USDHC_SetADMA2Descriptor( uint32_t *admaTable, uint32_t admaTableWords, const uint32_t *dataBufferAddr, uint32_t dataBytes, uint32_t flags) { @@ -1216,6 +1346,17 @@ status_t USDHC_SetADMA2Descriptor( return kStatus_Success; } +/*! + * brief Internal DMA configuration. + * This function is used to config the USDHC DMA related registers. + * param base USDHC peripheral base address. + * param adma configuration + * param dataAddr tranfer data address, a simple DMA parameter, if ADMA is used, leave it to NULL. + * param enAutoCmd23 flag to indicate Auto CMD23 is enable or not, a simple DMA parameter,if ADMA is used, leave it to + * false. + * retval kStatus_OutOfRange ADMA descriptor table length isn't enough to describe data. + * retval kStatus_Success Operate successfully. + */ status_t USDHC_SetInternalDmaConfig(USDHC_Type *base, usdhc_adma_config_t *dmaConfig, const uint32_t *dataAddr, @@ -1263,6 +1404,17 @@ status_t USDHC_SetInternalDmaConfig(USDHC_Type *base, return kStatus_Success; } +/*! + * brief Sets the DMA descriptor table configuration. + * A high level DMA descriptor configuration function. + * param base USDHC peripheral base address. + * param adma configuration + * param data Data descriptor + * param flags ADAM descriptor flag, used to indicate to create multiple or single descriptor, please + * reference _usdhc_adma_flag + * retval kStatus_OutOfRange ADMA descriptor table length isn't enough to describe data. + * retval kStatus_Success Operate successfully. + */ status_t USDHC_SetAdmaTableConfig(USDHC_Type *base, usdhc_adma_config_t *dmaConfig, usdhc_data_t *dataConfig, @@ -1313,6 +1465,26 @@ status_t USDHC_SetAdmaTableConfig(USDHC_Type *base, return error; } +/*! + * brief Transfers the command/data using a blocking method. + * + * This function waits until the command response/data is received or the USDHC encounters an error by polling the + * status + * flag. + * The application must not call this API in multiple threads at the same time. Because of that this API doesn't support + * the re-entry mechanism. + * + * note There is no need to call the API 'USDHC_TransferCreateHandle' when calling this API. + * + * param base USDHC peripheral base address. + * param adma configuration + * param transfer Transfer content. + * retval kStatus_InvalidArgument Argument is invalid. + * retval kStatus_USDHC_PrepareAdmaDescriptorFailed Prepare ADMA descriptor failed. + * retval kStatus_USDHC_SendCommandFailed Send command failed. + * retval kStatus_USDHC_TransferDataFailed Transfer data failed. + * retval kStatus_Success Operate successfully. + */ status_t USDHC_TransferBlocking(USDHC_Type *base, usdhc_adma_config_t *dmaConfig, usdhc_transfer_t *transfer) { assert(transfer); @@ -1362,7 +1534,7 @@ status_t USDHC_TransferBlocking(USDHC_Type *base, usdhc_adma_config_t *dmaConfig #endif /* config the data transfer parameter */ - error = USDHC_SetDataTransferConfig(base, data, &(command->flags)); + error = USDHC_SetDataTransferConfig(base, data, &(command->flags), enDMA); if (kStatus_Success != error) { return error; @@ -1381,6 +1553,25 @@ status_t USDHC_TransferBlocking(USDHC_Type *base, usdhc_adma_config_t *dmaConfig return error; } +/*! + * brief Transfers the command/data using an interrupt and an asynchronous method. + * + * This function sends a command and data and returns immediately. It doesn't wait the transfer complete or encounter an + * error. + * The application must not call this API in multiple threads at the same time. Because of that this API doesn't support + * the re-entry mechanism. + * + * note Call the API 'USDHC_TransferCreateHandle' when calling this API. + * + * param base USDHC peripheral base address. + * param handle USDHC handle. + * param adma configuration. + * param transfer Transfer content. + * retval kStatus_InvalidArgument Argument is invalid. + * retval kStatus_USDHC_BusyTransferring Busy transferring. + * retval kStatus_USDHC_PrepareAdmaDescriptorFailed Prepare ADMA descriptor failed. + * retval kStatus_Success Operate successfully. + */ status_t USDHC_TransferNonBlocking(USDHC_Type *base, usdhc_handle_t *handle, usdhc_adma_config_t *dmaConfig, @@ -1393,6 +1584,7 @@ status_t USDHC_TransferNonBlocking(USDHC_Type *base, usdhc_command_t *command = transfer->command; usdhc_data_t *data = transfer->data; bool executeTuning = ((data == NULL) ? false : data->dataType == kUSDHC_TransferDataTuning); + bool enDMA = true; /*check re-tuning request*/ if ((USDHC_GetInterruptStatusFlags(base) & (kUSDHC_ReTuningEventFlag)) != 0U) @@ -1421,6 +1613,7 @@ status_t USDHC_TransferNonBlocking(USDHC_Type *base, { /* disable DMA, using polling mode in this situation */ USDHC_EnableInternalDMA(base, false); + enDMA = false; } #if defined(FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL) && FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL else @@ -1438,7 +1631,7 @@ status_t USDHC_TransferNonBlocking(USDHC_Type *base, } #endif - error = USDHC_SetDataTransferConfig(base, data, &(command->flags)); + error = USDHC_SetDataTransferConfig(base, data, &(command->flags), enDMA); if (kStatus_Success != error) { return error; @@ -1451,6 +1644,14 @@ status_t USDHC_TransferNonBlocking(USDHC_Type *base, } #if defined(FSL_FEATURE_USDHC_HAS_SDR50_MODE) && (FSL_FEATURE_USDHC_HAS_SDR50_MODE) +/*! + * brief manual tuning trigger or abort + * User should handle the tuning cmd and find the boundary of the delay + * then calucate a average value which will be config to the CLK_TUNE_CTRL_STATUS + * This function should called before USDHC_AdjustDelayforSDR104 function + * param base USDHC peripheral base address. + * param tuning enable flag + */ void USDHC_EnableManualTuning(USDHC_Type *base, bool enable) { if (enable) @@ -1469,6 +1670,14 @@ void USDHC_EnableManualTuning(USDHC_Type *base, bool enable) } } +/*! + * brief the SDR104 mode delay setting adjust + * This function should called after USDHC_ManualTuningForSDR104 + * param base USDHC peripheral base address. + * param delay setting configuration + * retval kStatus_Fail config the delay setting fail + * retval kStatus_Success config the delay setting success + */ status_t USDHC_AdjustDelayForManualTuning(USDHC_Type *base, uint32_t delay) { uint32_t clkTuneCtrl = 0U; @@ -1491,6 +1700,16 @@ status_t USDHC_AdjustDelayForManualTuning(USDHC_Type *base, uint32_t delay) return kStatus_Success; } +/*! + * brief the enable standard tuning function + * The standard tuning window and tuning counter use the default config + * tuning cmd is send by the software, user need to check the tuning result + * can be used for SDR50,SDR104,HS200 mode tuning + * param base USDHC peripheral base address. + * param tuning start tap + * param tuning step + * param enable/disable flag + */ void USDHC_EnableStandardTuning(USDHC_Type *base, uint32_t tuningStartTap, uint32_t step, bool enable) { uint32_t tuningCtrl = 0U; @@ -1520,6 +1739,11 @@ void USDHC_EnableStandardTuning(USDHC_Type *base, uint32_t tuningStartTap, uint3 } } +/*! + * brief the auto tuning enbale for CMD/DATA line + * + * param base USDHC peripheral base address. + */ void USDHC_EnableAutoTuningForCmdAndData(USDHC_Type *base) { uint32_t busWidth = 0U; @@ -1569,7 +1793,7 @@ static void USDHC_TransferHandleCommand(USDHC_Type *base, usdhc_handle_t *handle { assert(handle->command); - if ((interruptFlags & kUSDHC_CommandErrorFlag) && (!(handle->data))) + if (interruptFlags & kUSDHC_CommandErrorFlag) { if (handle->callback.TransferComplete) { @@ -1673,6 +1897,14 @@ static void USDHC_TransferHandleBlockGap(USDHC_Type *base, usdhc_handle_t *handl } } +/*! + * brief Creates the USDHC handle. + * + * param base USDHC peripheral base address. + * param handle USDHC handle pointer. + * param callback Structure pointer to contain all callback functions. + * param userData Callback function parameter. + */ void USDHC_TransferCreateHandle(USDHC_Type *base, usdhc_handle_t *handle, const usdhc_transfer_callback_t *callback, @@ -1698,14 +1930,20 @@ void USDHC_TransferCreateHandle(USDHC_Type *base, /* Enable interrupt in NVIC. */ USDHC_SetTransferInterrupt(base, true); - /* disable the tuning pass interrupt */ - USDHC_DisableInterruptSignal(base, kUSDHC_TuningPassFlag | kUSDHC_ReTuningEventFlag); /* save IRQ handler */ s_usdhcIsr = USDHC_TransferHandleIRQ; EnableIRQ(s_usdhcIRQ[USDHC_GetInstance(base)]); } +/*! + * brief IRQ handler for the USDHC. + * + * This function deals with the IRQs on the given host controller. + * + * param base USDHC peripheral base address. + * param handle USDHC handle. + */ void USDHC_TransferHandleIRQ(USDHC_Type *base, usdhc_handle_t *handle) { assert(handle); diff --git a/ext/hal/nxp/mcux/drivers/imx/fsl_usdhc.h b/ext/hal/nxp/mcux/drivers/imx/fsl_usdhc.h index 41093084f12..658a42739b8 100644 --- a/ext/hal/nxp/mcux/drivers/imx/fsl_usdhc.h +++ b/ext/hal/nxp/mcux/drivers/imx/fsl_usdhc.h @@ -21,8 +21,8 @@ /*! @name Driver version */ /*@{*/ -/*! @brief Driver version 2.2.4. */ -#define FSL_USDHC_DRIVER_VERSION (MAKE_VERSION(2U, 2U, 4U)) +/*! @brief Driver version 2.2.5. */ +#define FSL_USDHC_DRIVER_VERSION (MAKE_VERSION(2U, 2U, 5U)) /*@}*/ /*! @brief Maximum block count can be set one time */ @@ -144,14 +144,14 @@ enum _usdhc_present_status_flag kUSDHC_CardInsertedFlag = USDHC_PRES_STATE_CINST_MASK, /*!< Card inserted */ kUSDHC_CommandLineLevelFlag = USDHC_PRES_STATE_CLSL_MASK, /*!< Command line signal level */ - kUSDHC_Data0LineLevelFlag = (1U << USDHC_PRES_STATE_DLSL_SHIFT), /*!< Data0 line signal level */ - kUSDHC_Data1LineLevelFlag = (1U << (USDHC_PRES_STATE_DLSL_SHIFT + 1U)), /*!< Data1 line signal level */ - kUSDHC_Data2LineLevelFlag = (1U << (USDHC_PRES_STATE_DLSL_SHIFT + 2U)), /*!< Data2 line signal level */ - kUSDHC_Data3LineLevelFlag = (1U << (USDHC_PRES_STATE_DLSL_SHIFT + 3U)), /*!< Data3 line signal level */ - kUSDHC_Data4LineLevelFlag = (1U << (USDHC_PRES_STATE_DLSL_SHIFT + 4U)), /*!< Data4 line signal level */ - kUSDHC_Data5LineLevelFlag = (1U << (USDHC_PRES_STATE_DLSL_SHIFT + 5U)), /*!< Data5 line signal level */ - kUSDHC_Data6LineLevelFlag = (1U << (USDHC_PRES_STATE_DLSL_SHIFT + 6U)), /*!< Data6 line signal level */ - kUSDHC_Data7LineLevelFlag = (1U << (USDHC_PRES_STATE_DLSL_SHIFT + 7U)), /*!< Data7 line signal level */ + kUSDHC_Data0LineLevelFlag = 1U << USDHC_PRES_STATE_DLSL_SHIFT, /*!< Data0 line signal level */ + kUSDHC_Data1LineLevelFlag = 1U << (USDHC_PRES_STATE_DLSL_SHIFT + 1U), /*!< Data1 line signal level */ + kUSDHC_Data2LineLevelFlag = 1U << (USDHC_PRES_STATE_DLSL_SHIFT + 2U), /*!< Data2 line signal level */ + kUSDHC_Data3LineLevelFlag = 1U << (USDHC_PRES_STATE_DLSL_SHIFT + 3U), /*!< Data3 line signal level */ + kUSDHC_Data4LineLevelFlag = 1U << (USDHC_PRES_STATE_DLSL_SHIFT + 4U), /*!< Data4 line signal level */ + kUSDHC_Data5LineLevelFlag = 1U << (USDHC_PRES_STATE_DLSL_SHIFT + 5U), /*!< Data5 line signal level */ + kUSDHC_Data6LineLevelFlag = 1U << (USDHC_PRES_STATE_DLSL_SHIFT + 6U), /*!< Data6 line signal level */ + kUSDHC_Data7LineLevelFlag = (int)(1U << (USDHC_PRES_STATE_DLSL_SHIFT + 7U)), /*!< Data7 line signal level */ }; /*! @brief Interrupt status flag mask */ @@ -255,7 +255,7 @@ enum _usdhc_adma_error_state kUSDHC_AdmaErrorStateFetchDescriptor, /*!< ADMA error state */ }; -/*! @brief Force event mask */ +/*! @brief Force event bit position */ enum _usdhc_force_event { kUSDHC_ForceEventAutoCommand12NotExecuted = USDHC_FORCE_EVENT_FEVTAC12NE_MASK, /*!< Auto CMD12 not executed error */ @@ -272,21 +272,22 @@ enum _usdhc_force_event kUSDHC_ForceEventDataCrcError = USDHC_FORCE_EVENT_FEVTDCE_MASK, /*!< Data CRC error */ kUSDHC_ForceEventDataEndBitError = USDHC_FORCE_EVENT_FEVTDEBE_MASK, /*!< Data end bit error */ kUSDHC_ForceEventAutoCommand12Error = USDHC_FORCE_EVENT_FEVTAC12E_MASK, /*!< Auto CMD12 error */ - kUSDHC_ForceEventCardInt = USDHC_FORCE_EVENT_FEVTCINT_MASK, /*!< Card interrupt */ + kUSDHC_ForceEventCardInt = (int)USDHC_FORCE_EVENT_FEVTCINT_MASK, /*!< Card interrupt */ kUSDHC_ForceEventDmaError = USDHC_FORCE_EVENT_FEVTDMAE_MASK, /*!< Dma error */ #if defined(FSL_FEATURE_USDHC_HAS_SDR50_MODE) && (!FSL_FEATURE_USDHC_HAS_SDR50_MODE) kUSDHC_ForceEventTuningError = 0U, /*!< not support */ #else kUSDHC_ForceEventTuningError = USDHC_FORCE_EVENT_FEVTTNE_MASK, /*!< Tuning error */ #endif + kUSDHC_ForceEventsAll = - (kUSDHC_ForceEventAutoCommand12NotExecuted | kUSDHC_ForceEventAutoCommand12Timeout | - kUSDHC_ForceEventAutoCommand12CrcError | kUSDHC_ForceEventEndBitError | - kUSDHC_ForceEventAutoCommand12IndexError | kUSDHC_ForceEventAutoCommand12NotIssued | - kUSDHC_ForceEventCommandTimeout | kUSDHC_ForceEventCommandCrcError | kUSDHC_ForceEventCommandEndBitError | - kUSDHC_ForceEventCommandIndexError | kUSDHC_ForceEventDataTimeout | kUSDHC_ForceEventDataCrcError | - kUSDHC_ForceEventDataEndBitError | kUSDHC_ForceEventAutoCommand12Error | kUSDHC_ForceEventCardInt | - kUSDHC_ForceEventDmaError | kUSDHC_ForceEventTuningError), /*!< All force event flags mask */ + (int)(USDHC_FORCE_EVENT_FEVTAC12NE_MASK | USDHC_FORCE_EVENT_FEVTAC12TOE_MASK | + USDHC_FORCE_EVENT_FEVTAC12CE_MASK | USDHC_FORCE_EVENT_FEVTAC12EBE_MASK | + USDHC_FORCE_EVENT_FEVTAC12IE_MASK | USDHC_FORCE_EVENT_FEVTCNIBAC12E_MASK | + USDHC_FORCE_EVENT_FEVTCTOE_MASK | USDHC_FORCE_EVENT_FEVTCCE_MASK | USDHC_FORCE_EVENT_FEVTCEBE_MASK | + USDHC_FORCE_EVENT_FEVTCIE_MASK | USDHC_FORCE_EVENT_FEVTDTOE_MASK | USDHC_FORCE_EVENT_FEVTDCE_MASK | + USDHC_FORCE_EVENT_FEVTDEBE_MASK | USDHC_FORCE_EVENT_FEVTAC12E_MASK | USDHC_FORCE_EVENT_FEVTCINT_MASK | + USDHC_FORCE_EVENT_FEVTDMAE_MASK | kUSDHC_ForceEventTuningError), /*!< All force event flags mask */ }; /*! @brief Data transfer width */ @@ -1161,7 +1162,7 @@ static inline void USDHC_EnableMmcBoot(USDHC_Type *base, bool enable) * @brief Forces generating events according to the given mask. * * @param base USDHC peripheral base address. - * @param mask The force events mask(_usdhc_force_event). + * @param mask The force events bit posistion (_usdhc_force_event). */ static inline void USDHC_SetForceEvent(USDHC_Type *base, uint32_t mask) { diff --git a/ext/hal/nxp/mcux/drivers/imx/fsl_wdog.c b/ext/hal/nxp/mcux/drivers/imx/fsl_wdog.c index fb4e4994ba2..275b98377a4 100644 --- a/ext/hal/nxp/mcux/drivers/imx/fsl_wdog.c +++ b/ext/hal/nxp/mcux/drivers/imx/fsl_wdog.c @@ -1,6 +1,6 @@ /* * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP + * Copyright 2016-2018 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -22,6 +22,8 @@ static WDOG_Type *const s_wdogBases[] = WDOG_BASE_PTRS; static const clock_ip_name_t s_wdogClock[] = WDOG_CLOCKS; #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +static const IRQn_Type s_wdogIRQ[] = WDOG_IRQS; + /******************************************************************************* * Code ******************************************************************************/ @@ -43,10 +45,33 @@ static uint32_t WDOG_GetInstance(WDOG_Type *base) return instance; } +/*! + * brief Initializes the WDOG configuration sturcture. + * + * This function initializes the WDOG configuration structure to default values. The default + * values are as follows. + * code + * wdogConfig->enableWdog = true; + * wdogConfig->workMode.enableWait = true; + * wdogConfig->workMode.enableStop = false; + * wdogConfig->workMode.enableDebug = false; + * wdogConfig->enableInterrupt = false; + * wdogConfig->enablePowerdown = false; + * wdogConfig->resetExtension = flase; + * wdogConfig->timeoutValue = 0xFFU; + * wdogConfig->interruptTimeValue = 0x04u; + * endcode + * + * param config Pointer to the WDOG configuration structure. + * see wdog_config_t + */ void WDOG_GetDefaultConfig(wdog_config_t *config) { assert(config); + /* Initializes the configure structure to zero. */ + memset(config, 0, sizeof(*config)); + config->enableWdog = true; config->workMode.enableWait = false; config->workMode.enableStop = false; @@ -54,12 +79,28 @@ void WDOG_GetDefaultConfig(wdog_config_t *config) config->enableInterrupt = false; config->softwareResetExtension = false; config->enablePowerDown = false; - config->softwareAssertion = true; - config->softwareResetSignal = true; config->timeoutValue = 0xffu; config->interruptTimeValue = 0x04u; + config->enableTimeOutAssert = false; } +/*! + * brief Initializes the WDOG. + * + * This function initializes the WDOG. When called, the WDOG runs according to the configuration. + * + * This is an example. + * code + * wdog_config_t config; + * WDOG_GetDefaultConfig(&config); + * config.timeoutValue = 0xffU; + * config->interruptTimeValue = 0x04u; + * WDOG_Init(wdog_base,&config); + * endcode + * + * param base WDOG peripheral base address + * param config The configuration of WDOG + */ void WDOG_Init(WDOG_Type *base, const wdog_config_t *config) { assert(config); @@ -69,7 +110,7 @@ void WDOG_Init(WDOG_Type *base, const wdog_config_t *config) value = WDOG_WCR_WDE(config->enableWdog) | WDOG_WCR_WDW(config->workMode.enableWait) | WDOG_WCR_WDZST(config->workMode.enableStop) | WDOG_WCR_WDBG(config->workMode.enableDebug) | WDOG_WCR_SRE(config->softwareResetExtension) | WDOG_WCR_WT(config->timeoutValue) | - WDOG_WCR_WDA(config->softwareAssertion) | WDOG_WCR_SRS(config->softwareResetSignal); + WDOG_WCR_WDT(config->enableTimeOutAssert) | WDOG_WCR_SRS_MASK | WDOG_WCR_WDA_MASK; #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) /* Set configruation */ @@ -79,8 +120,20 @@ void WDOG_Init(WDOG_Type *base, const wdog_config_t *config) base->WICR = WDOG_WICR_WICT(config->interruptTimeValue) | WDOG_WICR_WIE(config->enableInterrupt); base->WMCR = WDOG_WMCR_PDE(config->enablePowerDown); base->WCR = value; + if (config->enableInterrupt) + { + EnableIRQ(s_wdogIRQ[WDOG_GetInstance(base)]); + } } +/*! + * brief Shuts down the WDOG. + * + * This function shuts down the WDOG. + * Watchdog Enable bit is a write one once only bit. It is not + * possible to clear this bit by a software write, once the bit is set. + * This bit(WDE) can be set/reset only in debug mode(exception). + */ void WDOG_Deinit(WDOG_Type *base) { if (base->WCR & WDOG_WCR_WDBG_MASK) @@ -89,6 +142,20 @@ void WDOG_Deinit(WDOG_Type *base) } } +/*! + * brief Gets the WDOG all reset status flags. + * + * This function gets all reset status flags. + * + * code + * uint16_t status; + * status = WDOG_GetStatusFlags (wdog_base); + * endcode + * param base WDOG peripheral base address + * return State of the status flag: asserted (true) or not-asserted (false).see _wdog_status_flags + * - true: a related status flag has been set. + * - false: a related status flag is not set. + */ uint16_t WDOG_GetStatusFlags(WDOG_Type *base) { uint16_t status_flag = 0U; @@ -102,6 +169,20 @@ uint16_t WDOG_GetStatusFlags(WDOG_Type *base) return status_flag; } +/*! + * brief Clears the WDOG flag. + * + * This function clears the WDOG status flag. + * + * This is an example for clearing the interrupt flag. + * code + * WDOG_ClearStatusFlags(wdog_base,KWDOG_InterruptFlag); + * endcode + * param base WDOG peripheral base address + * param mask The status flags to clear. + * The parameter could be any combination of the following values. + * kWDOG_TimeoutFlag + */ void WDOG_ClearInterruptStatus(WDOG_Type *base, uint16_t mask) { if (mask & kWDOG_InterruptFlag) @@ -110,6 +191,14 @@ void WDOG_ClearInterruptStatus(WDOG_Type *base, uint16_t mask) } } +/*! + * brief Refreshes the WDOG timer. + * + * This function feeds the WDOG. + * This function should be called before the WDOG timer is in timeout. Otherwise, a reset is asserted. + * + * param base WDOG peripheral base address + */ void WDOG_Refresh(WDOG_Type *base) { base->WSR = WDOG_REFRESH_KEY & 0xFFFFU; diff --git a/ext/hal/nxp/mcux/drivers/imx/fsl_wdog.h b/ext/hal/nxp/mcux/drivers/imx/fsl_wdog.h index d088e7b61aa..d3b533f2dcd 100644 --- a/ext/hal/nxp/mcux/drivers/imx/fsl_wdog.h +++ b/ext/hal/nxp/mcux/drivers/imx/fsl_wdog.h @@ -1,6 +1,6 @@ /* * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP + * Copyright 2016-2018 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -21,7 +21,7 @@ /*! @name Driver version */ /*@{*/ /*! @brief Defines WDOG driver version */ -#define FSL_WDOG_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) +#define FSL_WDOG_DRIVER_VERSION (MAKE_VERSION(2, 1, 0)) /*@}*/ /*! @name Refresh sequence */ /*@{*/ @@ -46,8 +46,7 @@ typedef struct _wdog_config uint16_t interruptTimeValue; /*!< Interrupt count timeout value */ bool softwareResetExtension; /*!< software reset extension */ bool enablePowerDown; /*!< power down enable bit */ - bool softwareAssertion; /*!< software assertion bit*/ - bool softwareResetSignal; /*!< software reset signalbit*/ + bool enableTimeOutAssert; /*!< Enable WDOG_B timeout assertion. */ } wdog_config_t; /*! @@ -164,6 +163,36 @@ static inline void WDOG_Disable(WDOG_Type *base) base->WCR &= ~WDOG_WCR_WDE_MASK; } +/*! + * @brief Trigger the system software reset. + * + * This function will write to the WCR[SRS] bit to trigger a software system reset. + * This bit will automatically resets to "1" after it has been asserted to "0". + * Note: Calling this API will reset the system right now, please using it with more attention. + * + * @param base WDOG peripheral base address + */ +static inline void WDOG_TriggerSystemSoftwareReset(WDOG_Type *base) +{ + base->WCR &= ~WDOG_WCR_SRS_MASK; +} + +/*! + * @brief Trigger an output assertion. + * + * This function will write to the WCR[WDA] bit to trigger WDOG_B signal assertion. + * The WDOG_B signal can be routed to external pin of the chip, the output pin will turn to + * assertion along with WDOG_B signal. + * Note: The WDOG_B signal will remain assert until a power on reset occurred, so, please + * take more attention while calling it. + * + * @param base WDOG peripheral base address + */ +static inline void WDOG_TriggerSoftwareSignal(WDOG_Type *base) +{ + base->WCR &= ~WDOG_WCR_WDA_MASK; +} + /*! * @brief Enables the WDOG interrupt. * @@ -265,7 +294,6 @@ static inline void WDOG_DisablePowerDownEnable(WDOG_Type *base) * @param base WDOG peripheral base address */ void WDOG_Refresh(WDOG_Type *base); - /*@}*/ #if defined(__cplusplus) diff --git a/ext/hal/nxp/mcux/drivers/imx/fsl_xbara.c b/ext/hal/nxp/mcux/drivers/imx/fsl_xbara.c index b107d60c7ca..9b081c0d704 100644 --- a/ext/hal/nxp/mcux/drivers/imx/fsl_xbara.c +++ b/ext/hal/nxp/mcux/drivers/imx/fsl_xbara.c @@ -2,7 +2,7 @@ * Copyright (c) 2015, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP * All rights reserved. - * + * * SPDX-License-Identifier: BSD-3-Clause */ @@ -17,7 +17,6 @@ #define FSL_COMPONENT_ID "platform.drivers.xbara" #endif - /******************************************************************************* * Prototypes ******************************************************************************/ @@ -64,6 +63,13 @@ static uint32_t XBARA_GetInstance(XBARA_Type *base) return instance; } +/*! + * brief Initializes the XBARA module. + * + * This function un-gates the XBARA clock. + * + * param base XBARA peripheral address. + */ void XBARA_Init(XBARA_Type *base) { #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) @@ -72,6 +78,13 @@ void XBARA_Init(XBARA_Type *base) #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ } +/*! + * brief Shuts down the XBARA module. + * + * This function disables XBARA clock. + * + * param base XBARA peripheral address. + */ void XBARA_Deinit(XBARA_Type *base) { #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) @@ -80,11 +93,39 @@ void XBARA_Deinit(XBARA_Type *base) #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ } +/*! + * brief Sets a connection between the selected XBARA_IN[*] input and the XBARA_OUT[*] output signal. + * + * This function connects the XBARA input to the selected XBARA output. + * If more than one XBARA module is available, only the inputs and outputs from the same module + * can be connected. + * + * Example: + code + XBARA_SetSignalsConnection(XBARA, kXBARA_InputPIT_TRG0, kXBARA_OutputDMAMUX18); + endcode + * + * param base XBARA peripheral address. + * param input XBARA input signal. + * param output XBARA output signal. + */ void XBARA_SetSignalsConnection(XBARA_Type *base, xbar_input_signal_t input, xbar_output_signal_t output) { XBARA_WR_SELx_SELx(base, (((uint16_t)input) & 0xFFU), (((uint16_t)output) & 0xFFU)); } +/*! + * brief Gets the active edge detection status. + * + * This function gets the active edge detect status of all XBARA_OUTs. If the + * active edge occurs, the return value is asserted. When the interrupt or the DMA + * functionality is enabled for the XBARA_OUTx, this field is 1 when the interrupt + * or DMA request is asserted and 0 when the interrupt or DMA request has been + * cleared. + * + * param base XBARA peripheral address. + * return the mask of these status flag bits. + */ uint32_t XBARA_GetStatusFlags(XBARA_Type *base) { uint32_t status_flag; @@ -95,6 +136,12 @@ uint32_t XBARA_GetStatusFlags(XBARA_Type *base) return status_flag; } +/*! + * brief Clears the edge detection status flags of relative mask. + * + * param base XBARA peripheral address. + * param mask the status flags to clear. + */ void XBARA_ClearStatusFlags(XBARA_Type *base, uint32_t mask) { uint16_t regVal; @@ -118,6 +165,24 @@ void XBARA_ClearStatusFlags(XBARA_Type *base, uint32_t mask) base->CTRL1 = regVal; } +/*! + * brief Configures the XBARA control register. + * + * This function configures an XBARA control register. The active edge detection + * and the DMA/IRQ function on the corresponding XBARA output can be set. + * + * Example: + code + xbara_control_config_t userConfig; + userConfig.activeEdge = kXBARA_EdgeRising; + userConfig.requestType = kXBARA_RequestInterruptEnalbe; + XBARA_SetOutputSignalConfig(XBARA, kXBARA_OutputDMAMUX18, &userConfig); + endcode + * + * param base XBARA peripheral address. + * param output XBARA output number. + * param controlConfig Pointer to structure that keeps configuration of control register. + */ void XBARA_SetOutputSignalConfig(XBARA_Type *base, xbar_output_signal_t output, const xbara_control_config_t *controlConfig) @@ -126,7 +191,7 @@ void XBARA_SetOutputSignalConfig(XBARA_Type *base, /* Set active edge for edge detection, set interrupt or DMA function. */ switch ((uint16_t)output) { -#if defined(FSL_FEATURE_XBARA_OUTPUT_DMA_CH_MUX_REQ_30) && FSL_FEATURE_XBARA_OUTPUT_DMA_CH_MUX_REQ_30 +#if defined(FSL_FEATURE_XBARA_OUTPUT_DMA_CH_MUX_REQ_30) && FSL_FEATURE_XBARA_OUTPUT_DMA_CH_MUX_REQ_30 case kXBARA1_OutputDmaChMuxReq30: #else case kXBARA_OutputDmamux18: @@ -142,7 +207,7 @@ void XBARA_SetOutputSignalConfig(XBARA_Type *base, /* Write regVal value into CTRL0 register */ base->CTRL0 = regVal; break; -#if defined(FSL_FEATURE_XBARA_OUTPUT_DMA_CH_MUX_REQ_31) && FSL_FEATURE_XBARA_OUTPUT_DMA_CH_MUX_REQ_31 +#if defined(FSL_FEATURE_XBARA_OUTPUT_DMA_CH_MUX_REQ_31) && FSL_FEATURE_XBARA_OUTPUT_DMA_CH_MUX_REQ_31 case kXBARA1_OutputDmaChMuxReq31: #else case kXBARA_OutputDmamux19: @@ -158,7 +223,7 @@ void XBARA_SetOutputSignalConfig(XBARA_Type *base, /* Write regVal value into CTRL0 register */ base->CTRL0 = regVal; break; -#if defined(FSL_FEATURE_XBARA_OUTPUT_DMA_CH_MUX_REQ_94) && FSL_FEATURE_XBARA_OUTPUT_DMA_CH_MUX_REQ_94 +#if defined(FSL_FEATURE_XBARA_OUTPUT_DMA_CH_MUX_REQ_94) && FSL_FEATURE_XBARA_OUTPUT_DMA_CH_MUX_REQ_94 case kXBARA1_OutputDmaChMuxReq94: #else case kXBARA_OutputDmamux20: @@ -174,10 +239,10 @@ void XBARA_SetOutputSignalConfig(XBARA_Type *base, /* Write regVal value into CTRL1 register */ base->CTRL1 = regVal; break; -#if defined(FSL_FEATURE_XBARA_OUTPUT_DMA_CH_MUX_REQ_95) && FSL_FEATURE_XBARA_OUTPUT_DMA_CH_MUX_REQ_95 +#if defined(FSL_FEATURE_XBARA_OUTPUT_DMA_CH_MUX_REQ_95) && FSL_FEATURE_XBARA_OUTPUT_DMA_CH_MUX_REQ_95 case kXBARA1_OutputDmaChMuxReq95: #else - case kXBARA_OutputDmamux21: + case kXBARA_OutputDmamux21: #endif /* Assign regVal to CTRL1 register's value */ regVal = (base->CTRL1); diff --git a/ext/hal/nxp/mcux/drivers/imx/fsl_xbarb.c b/ext/hal/nxp/mcux/drivers/imx/fsl_xbarb.c index 02e89ed2d56..ec8c05f1a5a 100644 --- a/ext/hal/nxp/mcux/drivers/imx/fsl_xbarb.c +++ b/ext/hal/nxp/mcux/drivers/imx/fsl_xbarb.c @@ -2,7 +2,7 @@ * Copyright (c) 2015, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP * All rights reserved. - * + * * SPDX-License-Identifier: BSD-3-Clause */ @@ -17,7 +17,6 @@ #define FSL_COMPONENT_ID "platform.drivers.xbarb" #endif - /******************************************************************************* * Prototypes ******************************************************************************/ @@ -64,6 +63,13 @@ static uint32_t XBARB_GetInstance(XBARB_Type *base) return instance; } +/*! + * brief Initializes the XBARB module. + * + * This function un-gates the XBARB clock. + * + * param base XBARB peripheral address. + */ void XBARB_Init(XBARB_Type *base) { #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) @@ -72,6 +78,13 @@ void XBARB_Init(XBARB_Type *base) #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ } +/*! + * brief Shuts down the XBARB module. + * + * This function disables XBARB clock. + * + * param base XBARB peripheral address. + */ void XBARB_Deinit(XBARB_Type *base) { #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) @@ -80,6 +93,17 @@ void XBARB_Deinit(XBARB_Type *base) #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ } +/*! + * brief Configures a connection between the selected XBARB_IN[*] input and the XBARB_OUT[*] output signal. + * + * This function configures which XBARB input is connected to the selected XBARB output. + * If more than one XBARB module is available, only the inputs and outputs from the same module + * can be connected. + * + * param base XBARB peripheral address. + * param input XBARB input signal. + * param output XBARB output signal. + */ void XBARB_SetSignalsConnection(XBARB_Type *base, xbar_input_signal_t input, xbar_output_signal_t output) { XBARB_WR_SELx_SELx(base, (((uint16_t)input) & 0xFFU), (((uint16_t)output) & 0xFFU)); diff --git a/ext/hal/nxp/mcux/drivers/kinetis/CMakeLists.txt b/ext/hal/nxp/mcux/drivers/kinetis/CMakeLists.txt index 67e2dbaf9b6..bdb4180e129 100644 --- a/ext/hal/nxp/mcux/drivers/kinetis/CMakeLists.txt +++ b/ext/hal/nxp/mcux/drivers/kinetis/CMakeLists.txt @@ -16,7 +16,7 @@ zephyr_sources_ifdef(CONFIG_I2C_MCUX fsl_i2c.c) zephyr_sources_ifdef(CONFIG_PWM_MCUX_FTM fsl_ftm.c) zephyr_sources_ifdef(CONFIG_ENTROPY_MCUX_RNGA fsl_rnga.c) zephyr_sources_ifdef(CONFIG_ENTROPY_MCUX_TRNG fsl_trng.c) -zephyr_sources_ifdef(CONFIG_SOC_FLASH_MCUX fsl_flash.c) +zephyr_sources_ifdef(CONFIG_SOC_FLASH_MCUX fsl_ftfx_flash.c fsl_ftfx_controller.c) zephyr_sources_ifdef(CONFIG_SPI_MCUX_DSPI fsl_dspi.c) zephyr_sources_ifdef(CONFIG_UART_MCUX fsl_uart.c) zephyr_sources_ifdef(CONFIG_UART_MCUX_LPSCI fsl_lpsci.c) diff --git a/ext/hal/nxp/mcux/drivers/kinetis/fsl_adc16.c b/ext/hal/nxp/mcux/drivers/kinetis/fsl_adc16.c index 0af6a4443e9..637911eaf90 100644 --- a/ext/hal/nxp/mcux/drivers/kinetis/fsl_adc16.c +++ b/ext/hal/nxp/mcux/drivers/kinetis/fsl_adc16.c @@ -1,35 +1,18 @@ /* * Copyright (c) 2015, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP + * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * SPDX-License-Identifier: BSD-3-Clause */ #include "fsl_adc16.h" +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.adc16" +#endif + /******************************************************************************* * Prototypes ******************************************************************************/ @@ -72,6 +55,12 @@ static uint32_t ADC16_GetInstance(ADC_Type *base) return instance; } +/*! + * brief Initializes the ADC16 module. + * + * param base ADC16 peripheral base address. + * param config Pointer to configuration structure. See "adc16_config_t". + */ void ADC16_Init(ADC_Type *base, const adc16_config_t *config) { assert(NULL != config); @@ -128,6 +117,11 @@ void ADC16_Init(ADC_Type *base, const adc16_config_t *config) } } +/*! + * brief De-initializes the ADC16 module. + * + * param base ADC16 peripheral base address. + */ void ADC16_Deinit(ADC_Type *base) { #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) @@ -136,10 +130,31 @@ void ADC16_Deinit(ADC_Type *base) #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ } +/*! + * brief Gets an available pre-defined settings for the converter's configuration. + * + * This function initializes the converter configuration structure with available settings. The default values are as + * follows. + * code + * config->referenceVoltageSource = kADC16_ReferenceVoltageSourceVref; + * config->clockSource = kADC16_ClockSourceAsynchronousClock; + * config->enableAsynchronousClock = true; + * config->clockDivider = kADC16_ClockDivider8; + * config->resolution = kADC16_ResolutionSE12Bit; + * config->longSampleMode = kADC16_LongSampleDisabled; + * config->enableHighSpeed = false; + * config->enableLowPower = false; + * config->enableContinuousConversion = false; + * endcode + * param config Pointer to the configuration structure. + */ void ADC16_GetDefaultConfig(adc16_config_t *config) { assert(NULL != config); + /* Initializes the configure structure to zero. */ + memset(config, 0, sizeof(*config)); + config->referenceVoltageSource = kADC16_ReferenceVoltageSourceVref; config->clockSource = kADC16_ClockSourceAsynchronousClock; config->enableAsynchronousClock = true; @@ -152,6 +167,19 @@ void ADC16_GetDefaultConfig(adc16_config_t *config) } #if defined(FSL_FEATURE_ADC16_HAS_CALIBRATION) && FSL_FEATURE_ADC16_HAS_CALIBRATION +/*! + * brief Automates the hardware calibration. + * + * This auto calibration helps to adjust the plus/minus side gain automatically. + * Execute the calibration before using the converter. Note that the hardware trigger should be used + * during the calibration. + * + * param base ADC16 peripheral base address. + * + * return Execution status. + * retval kStatus_Success Calibration is done successfully. + * retval kStatus_Fail Calibration has failed. + */ status_t ADC16_DoAutoCalibration(ADC_Type *base) { bool bHWTrigger = false; @@ -210,6 +238,15 @@ status_t ADC16_DoAutoCalibration(ADC_Type *base) #endif /* FSL_FEATURE_ADC16_HAS_CALIBRATION */ #if defined(FSL_FEATURE_ADC16_HAS_MUX_SELECT) && FSL_FEATURE_ADC16_HAS_MUX_SELECT +/*! + * brief Sets the channel mux mode. + * + * Some sample pins share the same channel index. The channel mux mode decides which pin is used for an + * indicated channel. + * + * param base ADC16 peripheral base address. + * param mode Setting channel mux mode. See "adc16_channel_mux_mode_t". + */ void ADC16_SetChannelMuxMode(ADC_Type *base, adc16_channel_mux_mode_t mode) { if (kADC16_ChannelMuxA == mode) @@ -223,6 +260,18 @@ void ADC16_SetChannelMuxMode(ADC_Type *base, adc16_channel_mux_mode_t mode) } #endif /* FSL_FEATURE_ADC16_HAS_MUX_SELECT */ +/*! + * brief Configures the hardware compare mode. + * + * The hardware compare mode provides a way to process the conversion result automatically by using hardware. Only the + * result + * in the compare range is available. To compare the range, see "adc16_hardware_compare_mode_t" or the appopriate + * reference + * manual for more information. + * + * param base ADC16 peripheral base address. + * param config Pointer to the "adc16_hardware_compare_config_t" structure. Passing "NULL" disables the feature. + */ void ADC16_SetHardwareCompareConfig(ADC_Type *base, const adc16_hardware_compare_config_t *config) { uint32_t tmp32 = base->SC2 & ~(ADC_SC2_ACFE_MASK | ADC_SC2_ACFGT_MASK | ADC_SC2_ACREN_MASK); @@ -260,6 +309,16 @@ void ADC16_SetHardwareCompareConfig(ADC_Type *base, const adc16_hardware_compare } #if defined(FSL_FEATURE_ADC16_HAS_HW_AVERAGE) && FSL_FEATURE_ADC16_HAS_HW_AVERAGE +/*! + * brief Sets the hardware average mode. + * + * The hardware average mode provides a way to process the conversion result automatically by using hardware. The + * multiple + * conversion results are accumulated and averaged internally making them easier to read. + * + * param base ADC16 peripheral base address. + * param mode Setting the hardware average mode. See "adc16_hardware_average_mode_t". + */ void ADC16_SetHardwareAverage(ADC_Type *base, adc16_hardware_average_mode_t mode) { uint32_t tmp32 = base->SC3 & ~(ADC_SC3_AVGE_MASK | ADC_SC3_AVGS_MASK); @@ -273,6 +332,12 @@ void ADC16_SetHardwareAverage(ADC_Type *base, adc16_hardware_average_mode_t mode #endif /* FSL_FEATURE_ADC16_HAS_HW_AVERAGE */ #if defined(FSL_FEATURE_ADC16_HAS_PGA) && FSL_FEATURE_ADC16_HAS_PGA +/*! + * brief Configures the PGA for the converter's front end. + * + * param base ADC16 peripheral base address. + * param config Pointer to the "adc16_pga_config_t" structure. Passing "NULL" disables the feature. + */ void ADC16_SetPGAConfig(ADC_Type *base, const adc16_pga_config_t *config) { uint32_t tmp32; @@ -307,6 +372,13 @@ void ADC16_SetPGAConfig(ADC_Type *base, const adc16_pga_config_t *config) } #endif /* FSL_FEATURE_ADC16_HAS_PGA */ +/*! + * brief Gets the status flags of the converter. + * + * param base ADC16 peripheral base address. + * + * return Flags' mask if indicated flags are asserted. See "_adc16_status_flags". + */ uint32_t ADC16_GetStatusFlags(ADC_Type *base) { uint32_t ret = 0; @@ -324,6 +396,12 @@ uint32_t ADC16_GetStatusFlags(ADC_Type *base) return ret; } +/*! + * brief Clears the status flags of the converter. + * + * param base ADC16 peripheral base address. + * param mask Mask value for the cleared flags. See "_adc16_status_flags". + */ void ADC16_ClearStatusFlags(ADC_Type *base, uint32_t mask) { #if defined(FSL_FEATURE_ADC16_HAS_CALIBRATION) && FSL_FEATURE_ADC16_HAS_CALIBRATION @@ -334,6 +412,33 @@ void ADC16_ClearStatusFlags(ADC_Type *base, uint32_t mask) #endif /* FSL_FEATURE_ADC16_HAS_CALIBRATION */ } +/*! + * brief Configures the conversion channel. + * + * This operation triggers the conversion when in software trigger mode. When in hardware trigger mode, this API + * configures the channel while the external trigger source helps to trigger the conversion. + * + * Note that the "Channel Group" has a detailed description. + * To allow sequential conversions of the ADC to be triggered by internal peripherals, the ADC has more than one + * group of status and control registers, one for each conversion. The channel group parameter indicates which group of + * registers are used, for example, channel group 0 is for Group A registers and channel group 1 is for Group B + * registers. The + * channel groups are used in a "ping-pong" approach to control the ADC operation. At any point, only one of + * the channel groups is actively controlling ADC conversions. The channel group 0 is used for both software and + * hardware + * trigger modes. Channel group 1 and greater indicates multiple channel group registers for + * use only in hardware trigger mode. See the chip configuration information in the appropriate MCU reference manual for + * the + * number of SC1n registers (channel groups) specific to this device. Channel group 1 or greater are not used + * for software trigger operation. Therefore, writing to these channel groups does not initiate a new conversion. + * Updating the channel group 0 while a different channel group is actively controlling a conversion is allowed and + * vice versa. Writing any of the channel group registers while that specific channel group is actively controlling a + * conversion aborts the current conversion. + * + * param base ADC16 peripheral base address. + * param channelGroup Channel group index. + * param config Pointer to the "adc16_channel_config_t" structure for the conversion channel. + */ void ADC16_SetChannelConfig(ADC_Type *base, uint32_t channelGroup, const adc16_channel_config_t *config) { assert(channelGroup < ADC_SC1_COUNT); @@ -356,6 +461,14 @@ void ADC16_SetChannelConfig(ADC_Type *base, uint32_t channelGroup, const adc16_c base->SC1[channelGroup] = sc1; } +/*! + * brief Gets the status flags of channel. + * + * param base ADC16 peripheral base address. + * param channelGroup Channel group index. + * + * return Flags' mask if indicated flags are asserted. See "_adc16_channel_status_flags". + */ uint32_t ADC16_GetChannelStatusFlags(ADC_Type *base, uint32_t channelGroup) { assert(channelGroup < ADC_SC1_COUNT); diff --git a/ext/hal/nxp/mcux/drivers/kinetis/fsl_adc16.h b/ext/hal/nxp/mcux/drivers/kinetis/fsl_adc16.h index ea62c55fee6..4cf0d6fa19f 100644 --- a/ext/hal/nxp/mcux/drivers/kinetis/fsl_adc16.h +++ b/ext/hal/nxp/mcux/drivers/kinetis/fsl_adc16.h @@ -1,31 +1,9 @@ /* * Copyright (c) 2015, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause */ #ifndef _FSL_ADC16_H_ diff --git a/ext/hal/nxp/mcux/drivers/kinetis/fsl_cmp.c b/ext/hal/nxp/mcux/drivers/kinetis/fsl_cmp.c index 6a5f15a75b1..c4eef9b8af6 100644 --- a/ext/hal/nxp/mcux/drivers/kinetis/fsl_cmp.c +++ b/ext/hal/nxp/mcux/drivers/kinetis/fsl_cmp.c @@ -1,35 +1,18 @@ /* * Copyright (c) 2015, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP + * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * SPDX-License-Identifier: BSD-3-Clause */ #include "fsl_cmp.h" +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.cmp" +#endif + /******************************************************************************* * Prototypes ******************************************************************************/ @@ -71,6 +54,19 @@ static uint32_t CMP_GetInstance(CMP_Type *base) return instance; } +/*! + * brief Initializes the CMP. + * + * This function initializes the CMP module. The operations included are as follows. + * - Enabling the clock for CMP module. + * - Configuring the comparator. + * - Enabling the CMP module. + * Note that for some devices, multiple CMP instances share the same clock gate. In this case, to enable the clock for + * any instance enables all CMPs. See the appropriate MCU reference manual for the clock assignment of the CMP. + * + * param base CMP peripheral base address. + * param config Pointer to the configuration structure. + */ void CMP_Init(CMP_Type *base, const cmp_config_t *config) { assert(NULL != config); @@ -122,6 +118,19 @@ void CMP_Init(CMP_Type *base, const cmp_config_t *config) CMP_Enable(base, config->enableCmp); /* Enable the CMP module after configured or not. */ } +/*! + * brief De-initializes the CMP module. + * + * This function de-initializes the CMP module. The operations included are as follows. + * - Disabling the CMP module. + * - Disabling the clock for CMP module. + * + * This function disables the clock for the CMP. + * Note that for some devices, multiple CMP instances share the same clock gate. In this case, before disabling the + * clock for the CMP, ensure that all the CMP instances are not used. + * + * param base CMP peripheral base address. + */ void CMP_Deinit(CMP_Type *base) { /* Disable the CMP module. */ @@ -133,10 +142,28 @@ void CMP_Deinit(CMP_Type *base) #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ } +/*! +* brief Initializes the CMP user configuration structure. +* +* This function initializes the user configuration structure to these default values. +* code +* config->enableCmp = true; +* config->hysteresisMode = kCMP_HysteresisLevel0; +* config->enableHighSpeed = false; +* config->enableInvertOutput = false; +* config->useUnfilteredOutput = false; +* config->enablePinOut = false; +* config->enableTriggerMode = false; +* endcode +* param config Pointer to the configuration structure. +*/ void CMP_GetDefaultConfig(cmp_config_t *config) { assert(NULL != config); + /* Initializes the configure structure to zero. */ + memset(config, 0, sizeof(*config)); + config->enableCmp = true; /* Enable the CMP module after initialization. */ config->hysteresisMode = kCMP_HysteresisLevel0; config->enableHighSpeed = false; @@ -148,6 +175,17 @@ void CMP_GetDefaultConfig(cmp_config_t *config) #endif /* FSL_FEATURE_CMP_HAS_TRIGGER_MODE */ } +/*! + * brief Sets the input channels for the comparator. + * + * This function sets the input channels for the comparator. + * Note that two input channels cannot be set the same way in the application. When the user selects the same input + * from the analog mux to the positive and negative port, the comparator is disabled automatically. + * + * param base CMP peripheral base address. + * param positiveChannel Positive side input channel number. Available range is 0-7. + * param negativeChannel Negative side input channel number. Available range is 0-7. + */ void CMP_SetInputChannels(CMP_Type *base, uint8_t positiveChannel, uint8_t negativeChannel) { uint8_t tmp8 = base->MUXCR; @@ -158,6 +196,17 @@ void CMP_SetInputChannels(CMP_Type *base, uint8_t positiveChannel, uint8_t negat } #if defined(FSL_FEATURE_CMP_HAS_DMA) && FSL_FEATURE_CMP_HAS_DMA +/*! + * brief Enables/disables the DMA request for rising/falling events. + * + * This function enables/disables the DMA request for rising/falling events. Either event triggers the generation of + * the DMA request from CMP if the DMA feature is enabled. Both events are ignored for generating the DMA request from + * the CMP + * if the DMA is disabled. + * + * param base CMP peripheral base address. + * param enable Enables or disables the feature. + */ void CMP_EnableDMA(CMP_Type *base, bool enable) { uint8_t tmp8 = base->SCR & ~(CMP_SCR_CFR_MASK | CMP_SCR_CFF_MASK); /* To avoid change the w1c bits. */ @@ -174,6 +223,12 @@ void CMP_EnableDMA(CMP_Type *base, bool enable) } #endif /* FSL_FEATURE_CMP_HAS_DMA */ +/*! + * brief Configures the filter. + * + * param base CMP peripheral base address. + * param config Pointer to the configuration structure. + */ void CMP_SetFilterConfig(CMP_Type *base, const cmp_filter_config_t *config) { assert(NULL != config); @@ -199,6 +254,12 @@ void CMP_SetFilterConfig(CMP_Type *base, const cmp_filter_config_t *config) base->FPR = CMP_FPR_FILT_PER(config->filterPeriod); } +/*! + * brief Configures the internal DAC. + * + * param base CMP peripheral base address. + * param config Pointer to the configuration structure. "NULL" disables the feature. + */ void CMP_SetDACConfig(CMP_Type *base, const cmp_dac_config_t *config) { uint8_t tmp8 = 0U; @@ -220,6 +281,12 @@ void CMP_SetDACConfig(CMP_Type *base, const cmp_dac_config_t *config) base->DACCR = tmp8; } +/*! + * brief Enables the interrupts. + * + * param base CMP peripheral base address. + * param mask Mask value for interrupts. See "_cmp_interrupt_enable". + */ void CMP_EnableInterrupts(CMP_Type *base, uint32_t mask) { uint8_t tmp8 = base->SCR & ~(CMP_SCR_CFR_MASK | CMP_SCR_CFF_MASK); /* To avoid change the w1c bits. */ @@ -235,6 +302,12 @@ void CMP_EnableInterrupts(CMP_Type *base, uint32_t mask) base->SCR = tmp8; } +/*! + * brief Disables the interrupts. + * + * param base CMP peripheral base address. + * param mask Mask value for interrupts. See "_cmp_interrupt_enable". + */ void CMP_DisableInterrupts(CMP_Type *base, uint32_t mask) { uint8_t tmp8 = base->SCR & ~(CMP_SCR_CFR_MASK | CMP_SCR_CFF_MASK); /* To avoid change the w1c bits. */ @@ -250,6 +323,13 @@ void CMP_DisableInterrupts(CMP_Type *base, uint32_t mask) base->SCR = tmp8; } +/*! + * brief Gets the status flags. + * + * param base CMP peripheral base address. + * + * return Mask value for the asserted flags. See "_cmp_status_flags". + */ uint32_t CMP_GetStatusFlags(CMP_Type *base) { uint32_t ret32 = 0U; @@ -269,6 +349,12 @@ uint32_t CMP_GetStatusFlags(CMP_Type *base) return ret32; } +/*! + * brief Clears the status flags. + * + * param base CMP peripheral base address. + * param mask Mask value for the flags. See "_cmp_status_flags". + */ void CMP_ClearStatusFlags(CMP_Type *base, uint32_t mask) { uint8_t tmp8 = base->SCR & ~(CMP_SCR_CFR_MASK | CMP_SCR_CFF_MASK); /* To avoid change the w1c bits. */ diff --git a/ext/hal/nxp/mcux/drivers/kinetis/fsl_cmp.h b/ext/hal/nxp/mcux/drivers/kinetis/fsl_cmp.h index 5d16bf08de4..8b5b9a87f8d 100644 --- a/ext/hal/nxp/mcux/drivers/kinetis/fsl_cmp.h +++ b/ext/hal/nxp/mcux/drivers/kinetis/fsl_cmp.h @@ -1,31 +1,9 @@ /* * Copyright (c) 2015, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause */ #ifndef _FSL_CMP_H_ diff --git a/ext/hal/nxp/mcux/drivers/kinetis/fsl_cmt.c b/ext/hal/nxp/mcux/drivers/kinetis/fsl_cmt.c index 8cf72bc7e7d..9a27261adb7 100644 --- a/ext/hal/nxp/mcux/drivers/kinetis/fsl_cmt.c +++ b/ext/hal/nxp/mcux/drivers/kinetis/fsl_cmt.c @@ -1,31 +1,9 @@ /* * Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP + * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * SPDX-License-Identifier: BSD-3-Clause */ #include "fsl_cmt.h" @@ -34,6 +12,11 @@ * Definitions ******************************************************************************/ +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.cmt" +#endif + /* The standard intermediate frequency (IF). */ #define CMT_INTERMEDIATEFREQUENCY_8MHZ (8000000U) /* CMT data modulate mask. */ @@ -95,10 +78,21 @@ static uint32_t CMT_GetInstance(CMT_Type *base) return instance; } +/*! + * brief Gets the CMT default configuration structure. This API + * gets the default configuration structure for the CMT_Init(). + * Use the initialized structure unchanged in CMT_Init() or modify + * fields of the structure before calling the CMT_Init(). + * + * param config The CMT configuration structure pointer. + */ void CMT_GetDefaultConfig(cmt_config_t *config) { assert(config); + /* Initializes the configure structure to zero. */ + memset(config, 0, sizeof(*config)); + /* Default infrared output is enabled and set with high active, the divider is set to 1. */ config->isInterruptEnabled = false; config->isIroEnabled = true; @@ -106,6 +100,16 @@ void CMT_GetDefaultConfig(cmt_config_t *config) config->divider = kCMT_SecondClkDiv1; } +/*! + * brief Initializes the CMT module. + * + * This function ungates the module clock and sets the CMT internal clock, + * interrupt, and infrared output signal for the CMT module. + * + * param base CMT peripheral base address. + * param config The CMT basic configuration structure. + * param busClock_Hz The CMT module input clock - bus clock frequency. + */ void CMT_Init(CMT_Type *base, const cmt_config_t *config, uint32_t busClock_Hz) { assert(config); @@ -137,6 +141,14 @@ void CMT_Init(CMT_Type *base, const cmt_config_t *config, uint32_t busClock_Hz) } } +/*! + * brief Disables the CMT module and gate control. + * + * This function disables CMT modulator, interrupts, and gates the + * CMT clock control. CMT_Init must be called to use the CMT again. + * + * param base CMT peripheral base address. + */ void CMT_Deinit(CMT_Type *base) { /*Disable the CMT modulator. */ @@ -152,6 +164,13 @@ void CMT_Deinit(CMT_Type *base) #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ } +/*! + * brief Selects the mode for CMT. + * + * param base CMT peripheral base address. + * param mode The CMT feature mode enumeration. See "cmt_mode_t". + * param modulateConfig The carrier generation and modulator configuration. + */ void CMT_SetMode(CMT_Type *base, cmt_mode_t mode, cmt_modulate_config_t *modulateConfig) { uint8_t mscReg = base->MSC; @@ -170,7 +189,7 @@ void CMT_SetMode(CMT_Type *base, cmt_mode_t mode, cmt_modulate_config_t *modulat /* Set carrier modulator. */ CMT_SetModulateMarkSpace(base, modulateConfig->markCount, modulateConfig->spaceCount); - mscReg &= ~ (CMT_MSC_FSK_MASK | CMT_MSC_BASE_MASK); + mscReg &= ~(CMT_MSC_FSK_MASK | CMT_MSC_BASE_MASK); mscReg |= mode; } else @@ -181,6 +200,16 @@ void CMT_SetMode(CMT_Type *base, cmt_mode_t mode, cmt_modulate_config_t *modulat base->MSC = mscReg; } +/*! + * brief Gets the mode of the CMT module. + * + * param base CMT peripheral base address. + * return The CMT mode. + * kCMT_DirectIROCtl Carrier modulator is disabled; the IRO signal is directly in software control. + * kCMT_TimeMode Carrier modulator is enabled in time mode. + * kCMT_FSKMode Carrier modulator is enabled in FSK mode. + * kCMT_BasebandMode Carrier modulator is enabled in baseband mode. + */ cmt_mode_t CMT_GetMode(CMT_Type *base) { uint8_t mode = base->MSC; @@ -210,6 +239,13 @@ cmt_mode_t CMT_GetMode(CMT_Type *base) } } +/*! + * brief Gets the actual CMT clock frequency. + * + * param base CMT peripheral base address. + * param busClock_Hz CMT module input clock - bus clock frequency. + * return The CMT clock frequency. + */ uint32_t CMT_GetCMTFrequency(CMT_Type *base, uint32_t busClock_Hz) { uint32_t frequency; @@ -243,6 +279,23 @@ uint32_t CMT_GetCMTFrequency(CMT_Type *base, uint32_t busClock_Hz) return frequency; } +/*! + * brief Sets the modulation mark and space time period for the CMT modulator. + * + * This function sets the mark time period of the CMT modulator counter + * to control the mark time of the output modulated signal from the carrier generator output signal. + * If the CMT clock frequency is Fcmt and the carrier out signal frequency is fcg: + * - In Time and Baseband mode: The mark period of the generated signal equals (markCount + 1) / (Fcmt/8). + * The space period of the generated signal equals spaceCount / (Fcmt/8). + * - In FSK mode: The mark period of the generated signal equals (markCount + 1)/fcg. + * The space period of the generated signal equals spaceCount / fcg. + * + * param base Base address for current CMT instance. + * param markCount The number of clock period for CMT modulator signal mark period, + * in the range of 0 ~ 0xFFFF. + * param spaceCount The number of clock period for CMT modulator signal space period, + * in the range of the 0 ~ 0xFFFF. + */ void CMT_SetModulateMarkSpace(CMT_Type *base, uint32_t markCount, uint32_t spaceCount) { /* Set modulate mark. */ @@ -253,6 +306,15 @@ void CMT_SetModulateMarkSpace(CMT_Type *base, uint32_t markCount, uint32_t space base->CMD4 = spaceCount & CMT_CMD4_SB_MASK; } +/*! + * brief Sets the IRO (infrared output) signal state. + * + * Changes the states of the IRO signal when the kCMT_DirectIROMode mode is set + * and the IRO signal is enabled. + * + * param base CMT peripheral base address. + * param state The control of the IRO signal. See "cmt_infrared_output_state_t" + */ void CMT_SetIroState(CMT_Type *base, cmt_infrared_output_state_t state) { uint8_t ocReg = base->OC; diff --git a/ext/hal/nxp/mcux/drivers/kinetis/fsl_cmt.h b/ext/hal/nxp/mcux/drivers/kinetis/fsl_cmt.h index 3d81f8a9a4a..e774dda3ed5 100644 --- a/ext/hal/nxp/mcux/drivers/kinetis/fsl_cmt.h +++ b/ext/hal/nxp/mcux/drivers/kinetis/fsl_cmt.h @@ -1,31 +1,9 @@ /* * Copyright (c) 2015, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause */ #ifndef _FSL_CMT_H_ #define _FSL_CMT_H_ diff --git a/ext/hal/nxp/mcux/drivers/kinetis/fsl_common.c b/ext/hal/nxp/mcux/drivers/kinetis/fsl_common.c index 86f1625343d..39e78bcd9f2 100644 --- a/ext/hal/nxp/mcux/drivers/kinetis/fsl_common.c +++ b/ext/hal/nxp/mcux/drivers/kinetis/fsl_common.c @@ -1,49 +1,32 @@ /* * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. - * Copyright 2016 NXP + * Copyright 2016-2018 NXP * All rights reserved. * -* Redistribution and use in source and binary forms, with or without modification, -* are permitted provided that the following conditions are met: * -* o Redistributions of source code must retain the above copyright notice, this list -* of conditions and the following disclaimer. -* -* o Redistributions in binary form must reproduce the above copyright notice, this -* list of conditions and the following disclaimer in the documentation and/or -* other materials provided with the distribution. -* -* o Neither the name of the copyright holder nor the names of its -* contributors may be used to endorse or promote products derived from this -* software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* SPDX-License-Identifier: BSD-3-Clause */ #include "fsl_common.h" -#define SDK_MEM_MAGIC_NUMBER 12345U +#define SDK_MEM_MAGIC_NUMBER 12345U typedef struct _mem_align_control_block { - uint16_t identifier; /*!< Identifier for the memory control block. */ - uint16_t offset; /*!< offset from aligned adress to real address */ + uint16_t identifier; /*!< Identifier for the memory control block. */ + uint16_t offset; /*!< offset from aligned address to real address */ } mem_align_cb_t; +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.common" +#endif + #ifndef __GIC_PRIO_BITS #if defined(ENABLE_RAM_VECTOR_TABLE) uint32_t InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler) { /* Addresses for VECTOR_TABLE and VECTOR_RAM come from the linker file */ -#if defined(__CC_ARM) +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) extern uint32_t Image$$VECTOR_ROM$$Base[]; extern uint32_t Image$$VECTOR_RAM$$Base[]; extern uint32_t Image$$RW_m_data$$Base[]; @@ -60,7 +43,7 @@ uint32_t InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler) extern uint32_t __VECTOR_RAM[]; extern uint32_t __RAM_VECTOR_TABLE_SIZE_BYTES[]; uint32_t __RAM_VECTOR_TABLE_SIZE = (uint32_t)(__RAM_VECTOR_TABLE_SIZE_BYTES); -#endif /* defined(__CC_ARM) */ +#endif /* defined(__CC_ARM) || defined(__ARMCC_VERSION) */ uint32_t n; uint32_t ret; uint32_t irqMaskValue; @@ -94,13 +77,15 @@ uint32_t InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler) #endif /* ENABLE_RAM_VECTOR_TABLE. */ #endif /* __GIC_PRIO_BITS. */ -#ifndef QN908XC_SERIES #if (defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0)) +#if !(defined(FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS) && FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS) void EnableDeepSleepIRQ(IRQn_Type interrupt) { - uint32_t index = 0; uint32_t intNumber = (uint32_t)interrupt; + + uint32_t index = 0; + while (intNumber >= 32u) { index++; @@ -113,21 +98,22 @@ void EnableDeepSleepIRQ(IRQn_Type interrupt) void DisableDeepSleepIRQ(IRQn_Type interrupt) { - uint32_t index = 0; uint32_t intNumber = (uint32_t)interrupt; + + DisableIRQ(interrupt); /* also disable interrupt at NVIC */ + uint32_t index = 0; + while (intNumber >= 32u) { index++; intNumber -= 32u; } - DisableIRQ(interrupt); /* also disable interrupt at NVIC */ SYSCON->STARTERCLR[index] = 1u << intNumber; } +#endif /* FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS */ #endif /* FSL_FEATURE_SOC_SYSCON_COUNT */ -#endif /* QN908XC_SERIES */ - void *SDK_Malloc(size_t size, size_t alignbytes) { mem_align_cb_t *p_cb = NULL; @@ -159,4 +145,3 @@ void SDK_Free(void *ptr) free((void *)((uint32_t)ptr - p_cb->offset)); } - diff --git a/ext/hal/nxp/mcux/drivers/kinetis/fsl_common.h b/ext/hal/nxp/mcux/drivers/kinetis/fsl_common.h index cd563c2e704..d8a74ce412b 100644 --- a/ext/hal/nxp/mcux/drivers/kinetis/fsl_common.h +++ b/ext/hal/nxp/mcux/drivers/kinetis/fsl_common.h @@ -1,31 +1,9 @@ /* * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * Copyright 2016-2018 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause */ #ifndef _FSL_COMMON_H_ @@ -60,19 +38,21 @@ /*! @name Driver version */ /*@{*/ -/*! @brief common driver version 2.0.0. */ -#define FSL_COMMON_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) +/*! @brief common driver version 2.0.1. */ +#define FSL_COMMON_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) /*@}*/ /* Debug console type definition. */ -#define DEBUG_CONSOLE_DEVICE_TYPE_NONE 0U /*!< No debug console. */ -#define DEBUG_CONSOLE_DEVICE_TYPE_UART 1U /*!< Debug console base on UART. */ -#define DEBUG_CONSOLE_DEVICE_TYPE_LPUART 2U /*!< Debug console base on LPUART. */ -#define DEBUG_CONSOLE_DEVICE_TYPE_LPSCI 3U /*!< Debug console base on LPSCI. */ -#define DEBUG_CONSOLE_DEVICE_TYPE_USBCDC 4U /*!< Debug console base on USBCDC. */ -#define DEBUG_CONSOLE_DEVICE_TYPE_FLEXCOMM 5U /*!< Debug console base on USBCDC. */ -#define DEBUG_CONSOLE_DEVICE_TYPE_IUART 6U /*!< Debug console base on i.MX UART. */ -#define DEBUG_CONSOLE_DEVICE_TYPE_VUSART 7U /*!< Debug console base on LPC_USART. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_NONE 0U /*!< No debug console. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_UART 1U /*!< Debug console based on UART. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_LPUART 2U /*!< Debug console based on LPUART. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_LPSCI 3U /*!< Debug console based on LPSCI. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_USBCDC 4U /*!< Debug console based on USBCDC. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_FLEXCOMM 5U /*!< Debug console based on FLEXCOMM. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_IUART 6U /*!< Debug console based on i.MX UART. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_VUSART 7U /*!< Debug console based on LPC_VUSART. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_MINI_USART 8U /*!< Debug console based on LPC_USART. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_SWO 9U /*!< Debug console based on SWO. */ /*! @brief Status group numbers. */ enum _status_groups @@ -136,14 +116,39 @@ enum _status_groups kStatusGroup_ESAI = 69, /*!< Group number for ESAI status codes. */ kStatusGroup_FLEXSPI = 70, /*!< Group number for FLEXSPI status codes. */ kStatusGroup_MMDC = 71, /*!< Group number for MMDC status codes. */ - kStatusGroup_MICFIL = 72, /*!< Group number for MIC status codes. */ + kStatusGroup_PDM = 72, /*!< Group number for MIC status codes. */ kStatusGroup_SDMA = 73, /*!< Group number for SDMA status codes. */ kStatusGroup_ICS = 74, /*!< Group number for ICS status codes. */ kStatusGroup_SPDIF = 75, /*!< Group number for SPDIF status codes. */ + kStatusGroup_LPC_MINISPI = 76, /*!< Group number for LPC_MINISPI status codes. */ + kStatusGroup_HASHCRYPT = 77, /*!< Group number for Hashcrypt status codes */ + kStatusGroup_LPC_SPI_SSP = 78, /*!< Group number for LPC_SPI_SSP status codes. */ + kStatusGroup_LPC_I2C_1 = 97, /*!< Group number for LPC_I2C_1 status codes. */ kStatusGroup_NOTIFIER = 98, /*!< Group number for NOTIFIER status codes. */ kStatusGroup_DebugConsole = 99, /*!< Group number for debug console status codes. */ - kStatusGroup_SEMC = 100, /*!< Group number for SEMC status codes. */ + kStatusGroup_SEMC = 100, /*!< Group number for SEMC status codes. */ kStatusGroup_ApplicationRangeStart = 101, /*!< Starting number for application groups. */ + kStatusGroup_IAP = 102, /*!< Group number for IAP status codes */ + + kStatusGroup_HAL_GPIO = 121, /*!< Group number for HAL GPIO status codes. */ + kStatusGroup_HAL_UART = 122, /*!< Group number for HAL UART status codes. */ + kStatusGroup_HAL_TIMER = 123, /*!< Group number for HAL TIMER status codes. */ + kStatusGroup_HAL_SPI = 124, /*!< Group number for HAL SPI status codes. */ + kStatusGroup_HAL_I2C = 125, /*!< Group number for HAL I2C status codes. */ + kStatusGroup_HAL_FLASH = 126, /*!< Group number for HAL FLASH status codes. */ + kStatusGroup_HAL_PWM = 127, /*!< Group number for HAL PWM status codes. */ + kStatusGroup_HAL_RNG = 128, /*!< Group number for HAL RNG status codes. */ + kStatusGroup_TIMERMANAGER = 135, /*!< Group number for TiMER MANAGER status codes. */ + kStatusGroup_SERIALMANAGER = 136, /*!< Group number for SERIAL MANAGER status codes. */ + kStatusGroup_LED = 137, /*!< Group number for LED status codes. */ + kStatusGroup_BUTTON = 138, /*!< Group number for BUTTON status codes. */ + kStatusGroup_EXTERN_EEPROM = 139, /*!< Group number for EXTERN EEPROM status codes. */ + kStatusGroup_SHELL = 140, /*!< Group number for SHELL status codes. */ + kStatusGroup_MEM_MANAGER = 141, /*!< Group number for MEM MANAGER status codes. */ + kStatusGroup_LIST = 142, /*!< Group number for List status codes. */ + kStatusGroup_OSA = 143, /*!< Group number for OSA status codes. */ + kStatusGroup_COMMON_TASK = 144, /*!< Group number for Common task status codes. */ + kStatusGroup_MSG = 145, /*!< Group number for messaging status codes. */ }; /*! @brief Generic status return codes. */ @@ -175,6 +180,13 @@ typedef int32_t status_t; #include "fsl_reset.h" #endif +/* + * Macro guard for whether to use default weak IRQ implementation in drivers + */ +#ifndef FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ +#define FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ 1 +#endif + /*! @name Min/max macros */ /* @{ */ #if !defined(MIN) @@ -235,16 +247,16 @@ _Pragma("diag_suppress=Pm120") #if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE) #define SDK_L2CACHE_ALIGN(var) SDK_PRAGMA(data_alignment = FSL_FEATURE_L2CACHE_LINESIZE_BYTE) var #endif -#elif defined(__ARMCC_VERSION) +#elif defined(__CC_ARM) || defined(__ARMCC_VERSION) /*! Macro to define a variable with alignbytes alignment */ -#define SDK_ALIGN(var, alignbytes) __align(alignbytes) var +#define SDK_ALIGN(var, alignbytes) __attribute__((aligned(alignbytes))) var /*! Macro to define a variable with L1 d-cache line size alignment */ #if defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) -#define SDK_L1DCACHE_ALIGN(var) __align(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) var +#define SDK_L1DCACHE_ALIGN(var) __attribute__((aligned(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE))) var #endif /*! Macro to define a variable with L2 cache line size alignment */ #if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE) -#define SDK_L2CACHE_ALIGN(var) __align(FSL_FEATURE_L2CACHE_LINESIZE_BYTE) var +#define SDK_L2CACHE_ALIGN(var) __attribute__((aligned(FSL_FEATURE_L2CACHE_LINESIZE_BYTE))) var #endif #elif defined(__GNUC__) /*! Macro to define a variable with alignbytes alignment */ @@ -273,13 +285,6 @@ _Pragma("diag_suppress=Pm120") ((unsigned int)((var) + ((alignbytes)-1)) & (unsigned int)(~(unsigned int)((alignbytes)-1))) /* @} */ -/*! Function to allocate/free L1 cache aligned memory using the malloc/free. */ -void *SDK_Malloc(size_t size, size_t alignbytes); - -void SDK_Free(void *ptr); - -/* @} */ - /*! @name Non-cacheable region definition macros */ /* For initialized non-zero non-cacheable variables, please using "AT_NONCACHEABLE_SECTION_INIT(var) ={xx};" or * "AT_NONCACHEABLE_SECTION_ALIGN_INIT(var) ={xx};" in your projects to define them, for zero-inited non-cacheable variables, @@ -288,7 +293,7 @@ void SDK_Free(void *ptr); */ /* @{ */ #if (defined(__ICCARM__)) -#if defined(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE) +#if ((!(defined(FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION) && FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION)) && defined(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE)) #define AT_NONCACHEABLE_SECTION(var) var @"NonCacheable" #define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var @"NonCacheable" #define AT_NONCACHEABLE_SECTION_INIT(var) var @"NonCacheable.init" @@ -299,25 +304,25 @@ void SDK_Free(void *ptr); #define AT_NONCACHEABLE_SECTION_INIT(var) var #define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var #endif -#elif(defined(__ARMCC_VERSION)) -#if defined(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE) +#elif(defined(__CC_ARM) || defined(__ARMCC_VERSION)) +#if ((!(defined(FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION) && FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION)) && defined(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE)) #define AT_NONCACHEABLE_SECTION(var) __attribute__((section("NonCacheable"), zero_init)) var #define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) \ - __attribute__((section("NonCacheable"), zero_init)) __align(alignbytes) var + __attribute__((section("NonCacheable"), zero_init)) __attribute__((aligned(alignbytes))) var #define AT_NONCACHEABLE_SECTION_INIT(var) __attribute__((section("NonCacheable.init"))) var #define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) \ - __attribute__((section("NonCacheable.init"))) __align(alignbytes) var + __attribute__((section("NonCacheable.init"))) __attribute__((aligned(alignbytes))) var #else #define AT_NONCACHEABLE_SECTION(var) var -#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) __align(alignbytes) var +#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) __attribute__((aligned(alignbytes))) var #define AT_NONCACHEABLE_SECTION_INIT(var) var -#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) __align(alignbytes) var +#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) __attribute__((aligned(alignbytes))) var #endif #elif(defined(__GNUC__)) /* For GCC, when the non-cacheable section is required, please define "__STARTUP_INITIALIZE_NONCACHEDATA" * in your projects to make sure the non-cacheable section variables will be initialized in system startup. */ -#if defined(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE) +#if ((!(defined(FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION) && FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION)) && defined(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE)) #define AT_NONCACHEABLE_SECTION_INIT(var) __attribute__((section("NonCacheable.init"))) var #define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) \ __attribute__((section("NonCacheable.init"))) var __attribute__((aligned(alignbytes))) @@ -339,6 +344,48 @@ void SDK_Free(void *ptr); #endif /* @} */ +/*! @name Time sensitive region */ +/* @{ */ +#if defined(FSL_SDK_DRIVER_QUICK_ACCESS_ENABLE) && FSL_SDK_DRIVER_QUICK_ACCESS_ENABLE +#if (defined(__ICCARM__)) +#define AT_QUICKACCESS_SECTION_CODE(func) func @"CodeQuickAccess" +#define AT_QUICKACCESS_SECTION_DATA(func) func @"DataQuickAccess" +#elif(defined(__CC_ARM) || defined(__ARMCC_VERSION)) +#define AT_QUICKACCESS_SECTION_CODE(func) __attribute__((section("CodeQuickAccess"))) func +#define AT_QUICKACCESS_SECTION_DATA(func) __attribute__((section("DataQuickAccess"))) func +#elif(defined(__GNUC__)) +#define AT_QUICKACCESS_SECTION_CODE(func) __attribute__((section("CodeQuickAccess"))) func +#define AT_QUICKACCESS_SECTION_DATA(func) __attribute__((section("DataQuickAccess"))) func +#else +#error Toolchain not supported. +#endif /* defined(__ICCARM__) */ +#else +#if (defined(__ICCARM__)) +#define AT_QUICKACCESS_SECTION_CODE(func) func +#define AT_QUICKACCESS_SECTION_DATA(func) func +#elif(defined(__CC_ARM) || defined(__ARMCC_VERSION)) +#define AT_QUICKACCESS_SECTION_CODE(func) func +#define AT_QUICKACCESS_SECTION_DATA(func) func +#elif(defined(__GNUC__)) +#define AT_QUICKACCESS_SECTION_CODE(func) func +#define AT_QUICKACCESS_SECTION_DATA(func) func +#else +#error Toolchain not supported. +#endif +#endif /* __FSL_SDK_DRIVER_QUICK_ACCESS_ENABLE */ +/* @} */ + +/*! @name Ram Function */ +#if (defined(__ICCARM__)) +#define RAMFUNCTION_SECTION_CODE(func) func @"RamFunction" +#elif(defined(__CC_ARM) || defined(__ARMCC_VERSION)) +#define RAMFUNCTION_SECTION_CODE(func) __attribute__((section("RamFunction"))) func +#elif(defined(__GNUC__)) +#define RAMFUNCTION_SECTION_CODE(func) __attribute__((section("RamFunction"))) func +#else +#error Toolchain not supported. +#endif /* defined(__ICCARM__) */ +/* @} */ /******************************************************************************* * API ******************************************************************************/ @@ -450,10 +497,10 @@ void SDK_Free(void *ptr); } /*! - * @brief Enaable the global IRQ + * @brief Enable the global IRQ * * Set the primask register with the provided primask value but not just enable the primask. The idea is for the - * convinience of integration of RTOS. some RTOS get its own management mechanism of primask. User is required to + * convenience of integration of RTOS. some RTOS get its own management mechanism of primask. User is required to * use the EnableGlobalIRQ() and DisableGlobalIRQ() in pair. * * @param primask value of primask register to be restored. The primask value is supposed to be provided by the @@ -478,7 +525,7 @@ void SDK_Free(void *ptr); */ uint32_t InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler); #endif /* ENABLE_RAM_VECTOR_TABLE. */ - + #if (defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0)) /*! * @brief Enable specific interrupt for wake-up from deep-sleep mode. @@ -489,7 +536,7 @@ void SDK_Free(void *ptr); * those clocks (significantly increasing power consumption in the reduced power mode), * making these wake-ups possible. * - * @note This function also enables the interrupt in the NVIC (EnableIRQ() is called internally). + * @note This function also enables the interrupt in the NVIC (EnableIRQ() is called internaly). * * @param interrupt The IRQ number. */ @@ -504,13 +551,31 @@ void SDK_Free(void *ptr); * those clocks (significantly increasing power consumption in the reduced power mode), * making these wake-ups possible. * - * @note This function also disables the interrupt in the NVIC (DisableIRQ() is called internally). + * @note This function also disables the interrupt in the NVIC (DisableIRQ() is called internaly). * * @param interrupt The IRQ number. */ void DisableDeepSleepIRQ(IRQn_Type interrupt); #endif /* FSL_FEATURE_SOC_SYSCON_COUNT */ + /*! + * @brief Allocate memory with given alignment and aligned size. + * + * This is provided to support the dynamically allocated memory + * used in cache-able region. + * @param size The length required to malloc. + * @param alignbytes The alignment size. + * @retval The allocated memory. + */ + void *SDK_Malloc(size_t size, size_t alignbytes); + + /*! + * @brief Free memory. + * + * @param ptr The memory to be release. + */ + void SDK_Free(void *ptr); + #if defined(__cplusplus) } #endif diff --git a/ext/hal/nxp/mcux/drivers/kinetis/fsl_crc.c b/ext/hal/nxp/mcux/drivers/kinetis/fsl_crc.c index dba1db8c463..f92ce51e75f 100644 --- a/ext/hal/nxp/mcux/drivers/kinetis/fsl_crc.c +++ b/ext/hal/nxp/mcux/drivers/kinetis/fsl_crc.c @@ -1,37 +1,21 @@ /* * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP + * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * SPDX-License-Identifier: BSD-3-Clause */ #include "fsl_crc.h" /******************************************************************************* * Definitions ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.crc" +#endif + /*! @internal @brief Has data register with name CRC. */ #if defined(FSL_FEATURE_CRC_HAS_CRC_REG) && FSL_FEATURE_CRC_HAS_CRC_REG #define DATA CRC @@ -192,6 +176,15 @@ static void CRC_SetRawProtocolConfig(CRC_Type *base, const crc_config_t *protoco CRC_ConfigureAndStart(base, &moduleConfig); } +/*! + * brief Enables and configures the CRC peripheral module. + * + * This function enables the clock gate in the SIM module for the CRC peripheral. + * It also configures the CRC module and starts a checksum computation by writing the seed. + * + * param base CRC peripheral address. + * param config CRC module configuration structure. + */ void CRC_Init(CRC_Type *base, const crc_config_t *config) { #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) @@ -209,8 +202,27 @@ void CRC_Init(CRC_Type *base, const crc_config_t *config) } } +/*! + * brief Loads default values to the CRC protocol configuration structure. + * + * Loads default values to the CRC protocol configuration structure. The default values are as follows. + * code + * config->polynomial = 0x1021; + * config->seed = 0xFFFF; + * config->reflectIn = false; + * config->reflectOut = false; + * config->complementChecksum = false; + * config->crcBits = kCrcBits16; + * config->crcResult = kCrcFinalChecksum; + * endcode + * + * param config CRC protocol configuration structure. + */ void CRC_GetDefaultConfig(crc_config_t *config) { + /* Initializes the configure structure to zero. */ + memset(config, 0, sizeof(*config)); + static const crc_config_t crc16ccit = { CRC_DRIVER_DEFAULT_POLYNOMIAL, CRC_DRIVER_DEFAULT_SEED, CRC_DRIVER_DEFAULT_REFLECT_IN, CRC_DRIVER_DEFAULT_REFLECT_OUT, @@ -221,6 +233,16 @@ void CRC_GetDefaultConfig(crc_config_t *config) *config = crc16ccit; } +/*! + * brief Writes data to the CRC module. + * + * Writes input data buffer bytes to the CRC data register. + * The configured type of transpose is applied. + * + * param base CRC peripheral address. + * param data Input data stream, MSByte in data[0]. + * param dataSize Size in bytes of the input data buffer. + */ void CRC_WriteData(CRC_Type *base, const uint8_t *data, size_t dataSize) { const uint32_t *data32; @@ -253,11 +275,29 @@ void CRC_WriteData(CRC_Type *base, const uint8_t *data, size_t dataSize) } } +/*! + * brief Reads the 32-bit checksum from the CRC module. + * + * Reads the CRC data register (either an intermediate or the final checksum). + * The configured type of transpose and complement is applied. + * + * param base CRC peripheral address. + * return An intermediate or the final 32-bit checksum, after configured transpose and complement operations. + */ uint32_t CRC_Get32bitResult(CRC_Type *base) { return base->DATA; } +/*! + * brief Reads a 16-bit checksum from the CRC module. + * + * Reads the CRC data register (either an intermediate or the final checksum). + * The configured type of transpose and complement is applied. + * + * param base CRC peripheral address. + * return An intermediate or the final 16-bit checksum, after configured transpose and complement operations. + */ uint16_t CRC_Get16bitResult(CRC_Type *base) { uint32_t retval; diff --git a/ext/hal/nxp/mcux/drivers/kinetis/fsl_crc.h b/ext/hal/nxp/mcux/drivers/kinetis/fsl_crc.h index 247a9bac781..f8907d363b2 100644 --- a/ext/hal/nxp/mcux/drivers/kinetis/fsl_crc.h +++ b/ext/hal/nxp/mcux/drivers/kinetis/fsl_crc.h @@ -1,31 +1,9 @@ /* * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause */ #ifndef _FSL_CRC_H_ diff --git a/ext/hal/nxp/mcux/drivers/kinetis/fsl_dac.c b/ext/hal/nxp/mcux/drivers/kinetis/fsl_dac.c index 8d13d622835..7a3c3bbd55a 100644 --- a/ext/hal/nxp/mcux/drivers/kinetis/fsl_dac.c +++ b/ext/hal/nxp/mcux/drivers/kinetis/fsl_dac.c @@ -1,35 +1,18 @@ /* * Copyright (c) 2015, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP + * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * SPDX-License-Identifier: BSD-3-Clause */ #include "fsl_dac.h" +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.dac" +#endif + /******************************************************************************* * Prototypes ******************************************************************************/ @@ -71,6 +54,17 @@ static uint32_t DAC_GetInstance(DAC_Type *base) return instance; } +/*! + * brief Initializes the DAC module. + * + * This function initializes the DAC module including the following operations. + * - Enabling the clock for DAC module. + * - Configuring the DAC converter with a user configuration. + * - Enabling the DAC module. + * + * param base DAC peripheral base address. + * param config Pointer to the configuration structure. See "dac_config_t". + */ void DAC_Init(DAC_Type *base, const dac_config_t *config) { assert(NULL != config); @@ -99,6 +93,15 @@ void DAC_Init(DAC_Type *base, const dac_config_t *config) /* Tip: The DAC output can be enabled till then after user sets their own available data in application. */ } +/*! + * brief De-initializes the DAC module. + * + * This function de-initializes the DAC module including the following operations. + * - Disabling the DAC module. + * - Disabling the clock for the DAC module. + * + * param base DAC peripheral base address. + */ void DAC_Deinit(DAC_Type *base) { DAC_Enable(base, false); @@ -109,14 +112,33 @@ void DAC_Deinit(DAC_Type *base) #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ } +/*! + * brief Initializes the DAC user configuration structure. + * + * This function initializes the user configuration structure to a default value. The default values are as follows. + * code + * config->referenceVoltageSource = kDAC_ReferenceVoltageSourceVref2; + * config->enableLowPowerMode = false; + * endcode + * param config Pointer to the configuration structure. See "dac_config_t". + */ void DAC_GetDefaultConfig(dac_config_t *config) { assert(NULL != config); + /* Initializes the configure structure to zero. */ + memset(config, 0, sizeof(*config)); + config->referenceVoltageSource = kDAC_ReferenceVoltageSourceVref2; config->enableLowPowerMode = false; } +/*! + * brief Configures the CMP buffer. + * + * param base DAC peripheral base address. + * param config Pointer to the configuration structure. See "dac_buffer_config_t". + */ void DAC_SetBufferConfig(DAC_Type *base, const dac_buffer_config_t *config) { assert(NULL != config); @@ -150,10 +172,26 @@ void DAC_SetBufferConfig(DAC_Type *base, const dac_buffer_config_t *config) base->C2 = tmp8; } +/*! + * brief Initializes the DAC buffer configuration structure. + * + * This function initializes the DAC buffer configuration structure to default values. The default values are as + * follows. + * code + * config->triggerMode = kDAC_BufferTriggerBySoftwareMode; + * config->watermark = kDAC_BufferWatermark1Word; + * config->workMode = kDAC_BufferWorkAsNormalMode; + * config->upperLimit = DAC_DATL_COUNT - 1U; + * endcode + * param config Pointer to the configuration structure. See "dac_buffer_config_t". + */ void DAC_GetDefaultBufferConfig(dac_buffer_config_t *config) { assert(NULL != config); + /* Initializes the configure structure to zero. */ + memset(config, 0, sizeof(*config)); + config->triggerMode = kDAC_BufferTriggerBySoftwareMode; #if defined(FSL_FEATURE_DAC_HAS_WATERMARK_SELECTION) && FSL_FEATURE_DAC_HAS_WATERMARK_SELECTION config->watermark = kDAC_BufferWatermark1Word; @@ -162,6 +200,14 @@ void DAC_GetDefaultBufferConfig(dac_buffer_config_t *config) config->upperLimit = DAC_DATL_COUNT - 1U; } +/*! + * brief Sets the value for items in the buffer. + * + * param base DAC peripheral base address. + * param index Setting the index for items in the buffer. The available index should not exceed the size of the DAC + * buffer. + * param value Setting the value for items in the buffer. 12-bits are available. + */ void DAC_SetBufferValue(DAC_Type *base, uint8_t index, uint16_t value) { assert(index < DAC_DATL_COUNT); @@ -170,6 +216,16 @@ void DAC_SetBufferValue(DAC_Type *base, uint8_t index, uint16_t value) base->DAT[index].DATH = (uint8_t)((0xF00U & value) >> 8); /* High 4-bit. */ } +/*! + * brief Sets the current read pointer of the DAC buffer. + * + * This function sets the current read pointer of the DAC buffer. + * The current output value depends on the item indexed by the read pointer. It is updated either by a + * software trigger or a hardware trigger. After the read pointer changes, the DAC output value also changes. + * + * param base DAC peripheral base address. + * param index Setting an index value for the pointer. + */ void DAC_SetBufferReadPointer(DAC_Type *base, uint8_t index) { assert(index < DAC_DATL_COUNT); @@ -180,6 +236,12 @@ void DAC_SetBufferReadPointer(DAC_Type *base, uint8_t index) base->C2 = tmp8; } +/*! + * brief Enables interrupts for the DAC buffer. + * + * param base DAC peripheral base address. + * param mask Mask value for interrupts. See "_dac_buffer_interrupt_enable". + */ void DAC_EnableBufferInterrupts(DAC_Type *base, uint32_t mask) { mask &= ( @@ -190,6 +252,12 @@ void DAC_EnableBufferInterrupts(DAC_Type *base, uint32_t mask) base->C0 |= ((uint8_t)mask); /* Write 1 to enable. */ } +/*! + * brief Disables interrupts for the DAC buffer. + * + * param base DAC peripheral base address. + * param mask Mask value for interrupts. See "_dac_buffer_interrupt_enable". + */ void DAC_DisableBufferInterrupts(DAC_Type *base, uint32_t mask) { mask &= ( @@ -200,6 +268,13 @@ void DAC_DisableBufferInterrupts(DAC_Type *base, uint32_t mask) base->C0 &= (uint8_t)(~((uint8_t)mask)); /* Write 0 to disable. */ } +/*! + * brief Gets the flags of events for the DAC buffer. + * + * param base DAC peripheral base address. + * + * return Mask value for the asserted flags. See "_dac_buffer_status_flags". + */ uint32_t DAC_GetBufferStatusFlags(DAC_Type *base) { return (uint32_t)(base->SR & ( @@ -209,6 +284,12 @@ uint32_t DAC_GetBufferStatusFlags(DAC_Type *base) DAC_SR_DACBFRPTF_MASK | DAC_SR_DACBFRPBF_MASK)); } +/*! + * brief Clears the flags of events for the DAC buffer. + * + * param base DAC peripheral base address. + * param mask Mask value for flags. See "_dac_buffer_status_flags_t". + */ void DAC_ClearBufferStatusFlags(DAC_Type *base, uint32_t mask) { mask &= ( diff --git a/ext/hal/nxp/mcux/drivers/kinetis/fsl_dac.h b/ext/hal/nxp/mcux/drivers/kinetis/fsl_dac.h index b71febf3bc3..199284bcf1d 100644 --- a/ext/hal/nxp/mcux/drivers/kinetis/fsl_dac.h +++ b/ext/hal/nxp/mcux/drivers/kinetis/fsl_dac.h @@ -1,31 +1,9 @@ /* * Copyright (c) 2015, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause */ #ifndef _FSL_DAC_H_ diff --git a/ext/hal/nxp/mcux/drivers/kinetis/fsl_dmamux.c b/ext/hal/nxp/mcux/drivers/kinetis/fsl_dmamux.c index 39ce9cfbead..8bfbe6c3676 100644 --- a/ext/hal/nxp/mcux/drivers/kinetis/fsl_dmamux.c +++ b/ext/hal/nxp/mcux/drivers/kinetis/fsl_dmamux.c @@ -1,31 +1,9 @@ /* * Copyright (c) 2015, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP + * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * SPDX-License-Identifier: BSD-3-Clause */ #include "fsl_dmamux.h" @@ -34,6 +12,11 @@ * Definitions ******************************************************************************/ +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.dmamux" +#endif + /******************************************************************************* * Prototypes ******************************************************************************/ @@ -78,6 +61,14 @@ static uint32_t DMAMUX_GetInstance(DMAMUX_Type *base) return instance; } +/*! + * brief Initializes the DMAMUX peripheral. + * + * This function ungates the DMAMUX clock. + * + * param base DMAMUX peripheral base address. + * + */ void DMAMUX_Init(DMAMUX_Type *base) { #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) @@ -85,6 +76,13 @@ void DMAMUX_Init(DMAMUX_Type *base) #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ } +/*! + * brief Deinitializes the DMAMUX peripheral. + * + * This function gates the DMAMUX clock. + * + * param base DMAMUX peripheral base address. + */ void DMAMUX_Deinit(DMAMUX_Type *base) { #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) diff --git a/ext/hal/nxp/mcux/drivers/kinetis/fsl_dmamux.h b/ext/hal/nxp/mcux/drivers/kinetis/fsl_dmamux.h index 071348b2c25..f458f8de2d6 100644 --- a/ext/hal/nxp/mcux/drivers/kinetis/fsl_dmamux.h +++ b/ext/hal/nxp/mcux/drivers/kinetis/fsl_dmamux.h @@ -1,31 +1,9 @@ /* * Copyright (c) 2015, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause */ #ifndef _FSL_DMAMUX_H_ diff --git a/ext/hal/nxp/mcux/drivers/kinetis/fsl_dspi.c b/ext/hal/nxp/mcux/drivers/kinetis/fsl_dspi.c index e2b90ba56a9..11e63db7a20 100644 --- a/ext/hal/nxp/mcux/drivers/kinetis/fsl_dspi.c +++ b/ext/hal/nxp/mcux/drivers/kinetis/fsl_dspi.c @@ -1,31 +1,9 @@ /* * Copyright (c) 2015, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP + * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * SPDX-License-Identifier: BSD-3-Clause */ #include "fsl_dspi.h" @@ -33,6 +11,12 @@ /******************************************************************************* * Definitions ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.dspi" +#endif + /*! @brief Typedef for master interrupt handler. */ typedef void (*dspi_master_isr_t)(SPI_Type *base, dspi_master_handle_t *handle); @@ -42,13 +26,6 @@ typedef void (*dspi_slave_isr_t)(SPI_Type *base, dspi_slave_handle_t *handle); /******************************************************************************* * Prototypes ******************************************************************************/ -/*! - * @brief Get instance number for DSPI module. - * - * @param base DSPI peripheral base address. - */ -uint32_t DSPI_GetInstance(SPI_Type *base); - /*! * @brief Configures the DSPI peripheral chip select polarity. * @@ -137,9 +114,16 @@ static dspi_master_isr_t s_dspiMasterIsr; /*! @brief Pointer to slave IRQ handler for each instance. */ static dspi_slave_isr_t s_dspiSlaveIsr; +/* @brief Dummy data for each instance. This data is used when user's tx buffer is NULL*/ +volatile uint8_t g_dspiDummyData[ARRAY_SIZE(s_dspiBases)] = {0}; /********************************************************************************************************************** * Code *********************************************************************************************************************/ +/*! + * brief Get instance number for DSPI module. + * + * param base DSPI peripheral base address. + */ uint32_t DSPI_GetInstance(SPI_Type *base) { uint32_t instance; @@ -158,6 +142,46 @@ uint32_t DSPI_GetInstance(SPI_Type *base) return instance; } +/*! + * brief Set up the dummy data. + * + * param base DSPI peripheral address. + * param dummyData Data to be transferred when tx buffer is NULL. + */ +void DSPI_SetDummyData(SPI_Type *base, uint8_t dummyData) +{ + uint32_t instance = DSPI_GetInstance(base); + g_dspiDummyData[instance] = dummyData; +} + +/*! + * brief Initializes the DSPI master. + * + * This function initializes the DSPI master configuration. This is an example use case. + * code + * dspi_master_config_t masterConfig; + * masterConfig.whichCtar = kDSPI_Ctar0; + * masterConfig.ctarConfig.baudRate = 500000000U; + * masterConfig.ctarConfig.bitsPerFrame = 8; + * masterConfig.ctarConfig.cpol = kDSPI_ClockPolarityActiveHigh; + * masterConfig.ctarConfig.cpha = kDSPI_ClockPhaseFirstEdge; + * masterConfig.ctarConfig.direction = kDSPI_MsbFirst; + * masterConfig.ctarConfig.pcsToSckDelayInNanoSec = 1000000000U / masterConfig.ctarConfig.baudRate ; + * masterConfig.ctarConfig.lastSckToPcsDelayInNanoSec = 1000000000U / masterConfig.ctarConfig.baudRate ; + * masterConfig.ctarConfig.betweenTransferDelayInNanoSec = 1000000000U / masterConfig.ctarConfig.baudRate ; + * masterConfig.whichPcs = kDSPI_Pcs0; + * masterConfig.pcsActiveHighOrLow = kDSPI_PcsActiveLow; + * masterConfig.enableContinuousSCK = false; + * masterConfig.enableRxFifoOverWrite = false; + * masterConfig.enableModifiedTimingFormat = false; + * masterConfig.samplePoint = kDSPI_SckToSin0Clock; + * DSPI_MasterInit(base, &masterConfig, srcClock_Hz); + * endcode + * + * param base DSPI peripheral address. + * param masterConfig Pointer to the structure dspi_master_config_t. + * param srcClock_Hz Module source input clock in Hertz. + */ void DSPI_MasterInit(SPI_Type *base, const dspi_master_config_t *masterConfig, uint32_t srcClock_Hz) { assert(masterConfig); @@ -202,13 +226,30 @@ void DSPI_MasterInit(SPI_Type *base, const dspi_master_config_t *masterConfig, u DSPI_MasterSetDelayTimes(base, masterConfig->whichCtar, kDSPI_BetweenTransfer, srcClock_Hz, masterConfig->ctarConfig.betweenTransferDelayInNanoSec); + DSPI_SetDummyData(base, DSPI_DUMMY_DATA); DSPI_StartTransfer(base); } +/*! + * brief Sets the dspi_master_config_t structure to default values. + * + * The purpose of this API is to get the configuration structure initialized for the DSPI_MasterInit(). + * Users may use the initialized structure unchanged in the DSPI_MasterInit() or modify the structure + * before calling the DSPI_MasterInit(). + * Example: + * code + * dspi_master_config_t masterConfig; + * DSPI_MasterGetDefaultConfig(&masterConfig); + * endcode + * param masterConfig pointer to dspi_master_config_t structure + */ void DSPI_MasterGetDefaultConfig(dspi_master_config_t *masterConfig) { assert(masterConfig); + /* Initializes the configure structure to zero. */ + memset(masterConfig, 0, sizeof(*masterConfig)); + masterConfig->whichCtar = kDSPI_Ctar0; masterConfig->ctarConfig.baudRate = 500000; masterConfig->ctarConfig.bitsPerFrame = 8; @@ -229,6 +270,26 @@ void DSPI_MasterGetDefaultConfig(dspi_master_config_t *masterConfig) masterConfig->samplePoint = kDSPI_SckToSin0Clock; } +/*! + * brief DSPI slave configuration. + * + * This function initializes the DSPI slave configuration. This is an example use case. + * code + * dspi_slave_config_t slaveConfig; + * slaveConfig->whichCtar = kDSPI_Ctar0; + * slaveConfig->ctarConfig.bitsPerFrame = 8; + * slaveConfig->ctarConfig.cpol = kDSPI_ClockPolarityActiveHigh; + * slaveConfig->ctarConfig.cpha = kDSPI_ClockPhaseFirstEdge; + * slaveConfig->enableContinuousSCK = false; + * slaveConfig->enableRxFifoOverWrite = false; + * slaveConfig->enableModifiedTimingFormat = false; + * slaveConfig->samplePoint = kDSPI_SckToSin0Clock; + * DSPI_SlaveInit(base, &slaveConfig); + * endcode + * + * param base DSPI peripheral address. + * param slaveConfig Pointer to the structure dspi_master_config_t. + */ void DSPI_SlaveInit(SPI_Type *base, const dspi_slave_config_t *slaveConfig) { assert(slaveConfig); @@ -262,13 +323,31 @@ void DSPI_SlaveInit(SPI_Type *base, const dspi_slave_config_t *slaveConfig) SPI_CTAR_SLAVE_CPOL(slaveConfig->ctarConfig.cpol) | SPI_CTAR_SLAVE_CPHA(slaveConfig->ctarConfig.cpha); + DSPI_SetDummyData(base, DSPI_DUMMY_DATA); + DSPI_StartTransfer(base); } +/*! + * brief Sets the dspi_slave_config_t structure to a default value. + * + * The purpose of this API is to get the configuration structure initialized for the DSPI_SlaveInit(). + * Users may use the initialized structure unchanged in the DSPI_SlaveInit() or modify the structure + * before calling the DSPI_SlaveInit(). + * This is an example. + * code + * dspi_slave_config_t slaveConfig; + * DSPI_SlaveGetDefaultConfig(&slaveConfig); + * endcode + * param slaveConfig Pointer to the dspi_slave_config_t structure. + */ void DSPI_SlaveGetDefaultConfig(dspi_slave_config_t *slaveConfig) { assert(slaveConfig); + /* Initializes the configure structure to zero. */ + memset(slaveConfig, 0, sizeof(*slaveConfig)); + slaveConfig->whichCtar = kDSPI_Ctar0; slaveConfig->ctarConfig.bitsPerFrame = 8; slaveConfig->ctarConfig.cpol = kDSPI_ClockPolarityActiveHigh; @@ -280,6 +359,10 @@ void DSPI_SlaveGetDefaultConfig(dspi_slave_config_t *slaveConfig) slaveConfig->samplePoint = kDSPI_SckToSin0Clock; } +/*! + * brief De-initializes the DSPI peripheral. Call this API to disable the DSPI clock. + * param base DSPI peripheral address. + */ void DSPI_Deinit(SPI_Type *base) { DSPI_StopTransfer(base); @@ -309,6 +392,19 @@ static void DSPI_SetOnePcsPolarity(SPI_Type *base, dspi_which_pcs_t pcs, dspi_pc base->MCR = temp; } +/*! + * brief Sets the DSPI baud rate in bits per second. + * + * This function takes in the desired baudRate_Bps (baud rate) and calculates the nearest possible baud rate without + * exceeding the desired baud rate, and returns the calculated baud rate in bits-per-second. It requires that the + * caller also provide the frequency of the module source clock (in Hertz). + * + * param base DSPI peripheral address. + * param whichCtar The desired Clock and Transfer Attributes Register (CTAR) of the type dspi_ctar_selection_t + * param baudRate_Bps The desired baud rate in bits per second + * param srcClock_Hz Module source input clock in Hertz + * return The actual calculated baud rate + */ uint32_t DSPI_MasterSetBaudRate(SPI_Type *base, dspi_ctar_selection_t whichCtar, uint32_t baudRate_Bps, @@ -373,6 +469,24 @@ uint32_t DSPI_MasterSetBaudRate(SPI_Type *base, return bestBaudrate; } +/*! + * brief Manually configures the delay prescaler and scaler for a particular CTAR. + * + * This function configures the PCS to SCK delay pre-scalar (PcsSCK) and scalar (CSSCK), after SCK delay pre-scalar + * (PASC) and scalar (ASC), and the delay after transfer pre-scalar (PDT) and scalar (DT). + * + * These delay names are available in the type dspi_delay_type_t. + * + * The user passes the delay to the configuration along with the prescaler and scaler value. + * This allows the user to directly set the prescaler/scaler values if pre-calculated or + * to manually increment either value. + * + * param base DSPI peripheral address. + * param whichCtar The desired Clock and Transfer Attributes Register (CTAR) of type dspi_ctar_selection_t. + * param prescaler The prescaler delay value (can be an integer 0, 1, 2, or 3). + * param scaler The scaler delay value (can be any integer between 0 to 15). + * param whichDelay The desired delay to configure; must be of type dspi_delay_type_t + */ void DSPI_MasterSetDelayScaler( SPI_Type *base, dspi_ctar_selection_t whichCtar, uint32_t prescaler, uint32_t scaler, dspi_delay_type_t whichDelay) { @@ -399,6 +513,31 @@ void DSPI_MasterSetDelayScaler( } } +/*! + * brief Calculates the delay prescaler and scaler based on the desired delay input in nanoseconds. + * + * This function calculates the values for the following. + * PCS to SCK delay pre-scalar (PCSSCK) and scalar (CSSCK), or + * After SCK delay pre-scalar (PASC) and scalar (ASC), or + * Delay after transfer pre-scalar (PDT) and scalar (DT). + * + * These delay names are available in the type dspi_delay_type_t. + * + * The user passes which delay to configure along with the desired delay value in nanoseconds. The function + * calculates the values needed for the prescaler and scaler. Note that returning the calculated delay as an exact + * delay match may not be possible. In this case, the closest match is calculated without going below the desired + * delay value input. + * It is possible to input a very large delay value that exceeds the capability of the part, in which case the maximum + * supported delay is returned. The higher-level peripheral driver alerts the user of an out of range delay + * input. + * + * param base DSPI peripheral address. + * param whichCtar The desired Clock and Transfer Attributes Register (CTAR) of type dspi_ctar_selection_t. + * param whichDelay The desired delay to configure, must be of type dspi_delay_type_t + * param srcClock_Hz Module source input clock in Hertz + * param delayTimeInNanoSec The desired delay value in nanoseconds. + * return The actual calculated delay value. + */ uint32_t DSPI_MasterSetDelayTimes(SPI_Type *base, dspi_ctar_selection_t whichCtar, dspi_delay_type_t whichDelay, @@ -471,10 +610,26 @@ uint32_t DSPI_MasterSetDelayTimes(SPI_Type *base, return bestDelay; } +/*! + * brief Sets the dspi_command_data_config_t structure to default values. + * + * The purpose of this API is to get the configuration structure initialized for use in the DSPI_MasterWrite_xx(). + * Users may use the initialized structure unchanged in the DSPI_MasterWrite_xx() or modify the structure + * before calling the DSPI_MasterWrite_xx(). + * This is an example. + * code + * dspi_command_data_config_t command; + * DSPI_GetDefaultDataCommandConfig(&command); + * endcode + * param command Pointer to the dspi_command_data_config_t structure. + */ void DSPI_GetDefaultDataCommandConfig(dspi_command_data_config_t *command) { assert(command); + /* Initializes the configure structure to zero. */ + memset(command, 0, sizeof(*command)); + command->isPcsContinuous = false; command->whichCtar = kDSPI_Ctar0; command->whichPcs = kDSPI_Pcs0; @@ -482,12 +637,39 @@ void DSPI_GetDefaultDataCommandConfig(dspi_command_data_config_t *command) command->clearTransferCount = false; } +/*! + * brief Writes data into the data buffer master mode and waits till complete to return. + * + * In master mode, the 16-bit data is appended to the 16-bit command info. The command portion + * provides characteristics of the data, such as the optional continuous chip select + * operation between transfers, the desired Clock and Transfer Attributes register to use for the + * associated SPI frame, the desired PCS signal to use for the data transfer, whether the current + * transfer is the last in the queue, and whether to clear the transfer count (normally needed when + * sending the first frame of a data packet). This is an example. + * code + * dspi_command_config_t commandConfig; + * commandConfig.isPcsContinuous = true; + * commandConfig.whichCtar = kDSPICtar0; + * commandConfig.whichPcs = kDSPIPcs1; + * commandConfig.clearTransferCount = false; + * commandConfig.isEndOfQueue = false; + * DSPI_MasterWriteDataBlocking(base, &commandConfig, dataWord); + * endcode + * + * Note that this function does not return until after the transmit is complete. Also note that the DSPI must be + * enabled and running to transmit data (MCR[MDIS] & [HALT] = 0). Because the SPI is a synchronous protocol, + * the received data is available when the transmit completes. + * + * param base DSPI peripheral address. + * param command Pointer to the command structure. + * param data The data word to be sent. + */ void DSPI_MasterWriteDataBlocking(SPI_Type *base, dspi_command_data_config_t *command, uint16_t data) { assert(command); /* First, clear Transmit Complete Flag (TCF) */ - DSPI_ClearStatusFlags(base, kDSPI_TxCompleteFlag); + DSPI_ClearStatusFlags(base, (uint32_t)kDSPI_TxCompleteFlag); while (!(DSPI_GetStatusFlags(base) & kDSPI_TxFifoFillRequestFlag)) { @@ -500,15 +682,56 @@ void DSPI_MasterWriteDataBlocking(SPI_Type *base, dspi_command_data_config_t *co DSPI_ClearStatusFlags(base, kDSPI_TxFifoFillRequestFlag); /* Wait till TCF sets */ - while (!(DSPI_GetStatusFlags(base) & kDSPI_TxCompleteFlag)) + while (!(DSPI_GetStatusFlags(base) & (uint32_t)kDSPI_TxCompleteFlag)) { } } +/*! + * brief Writes a 32-bit data word (16-bit command appended with 16-bit data) into the data + * buffer master mode and waits till complete to return. + * + * In this function, the user must append the 16-bit data to the 16-bit command information and then provide the total +* 32-bit word + * as the data to send. + * The command portion provides characteristics of the data, such as the optional continuous chip select operation + * between transfers, the desired Clock and Transfer Attributes register to use for the associated SPI frame, the +* desired PCS + * signal to use for the data transfer, whether the current transfer is the last in the queue, and whether to clear the + * transfer count (normally needed when sending the first frame of a data packet). The user is responsible for + * appending this command with the data to send. This is an example: + * code + * dataWord = <16-bit command> | <16-bit data>; + * DSPI_MasterWriteCommandDataBlocking(base, dataWord); + * endcode + * + * Note that this function does not return until after the transmit is complete. Also note that the DSPI must be + * enabled and running to transmit data (MCR[MDIS] & [HALT] = 0). + * Because the SPI is a synchronous protocol, the received data is available when the transmit completes. + * + * For a blocking polling transfer, see methods below. + * Option 1: +* uint32_t command_to_send = DSPI_MasterGetFormattedCommand(&command); +* uint32_t data0 = command_to_send | data_need_to_send_0; +* uint32_t data1 = command_to_send | data_need_to_send_1; +* uint32_t data2 = command_to_send | data_need_to_send_2; +* +* DSPI_MasterWriteCommandDataBlocking(base,data0); +* DSPI_MasterWriteCommandDataBlocking(base,data1); +* DSPI_MasterWriteCommandDataBlocking(base,data2); +* +* Option 2: +* DSPI_MasterWriteDataBlocking(base,&command,data_need_to_send_0); +* DSPI_MasterWriteDataBlocking(base,&command,data_need_to_send_1); +* DSPI_MasterWriteDataBlocking(base,&command,data_need_to_send_2); +* + * param base DSPI peripheral address. + * param data The data word (command and data combined) to be sent. + */ void DSPI_MasterWriteCommandDataBlocking(SPI_Type *base, uint32_t data) { /* First, clear Transmit Complete Flag (TCF) */ - DSPI_ClearStatusFlags(base, kDSPI_TxCompleteFlag); + DSPI_ClearStatusFlags(base, (uint32_t)kDSPI_TxCompleteFlag); while (!(DSPI_GetStatusFlags(base) & kDSPI_TxFifoFillRequestFlag)) { @@ -520,15 +743,24 @@ void DSPI_MasterWriteCommandDataBlocking(SPI_Type *base, uint32_t data) DSPI_ClearStatusFlags(base, kDSPI_TxFifoFillRequestFlag); /* Wait till TCF sets */ - while (!(DSPI_GetStatusFlags(base) & kDSPI_TxCompleteFlag)) + while (!(DSPI_GetStatusFlags(base) & (uint32_t)kDSPI_TxCompleteFlag)) { } } +/*! + * brief Writes data into the data buffer in slave mode, waits till data was transmitted, and returns. + * + * In slave mode, up to 16-bit words may be written. The function first clears the transmit complete flag, writes data + * into data register, and finally waits until the data is transmitted. + * + * param base DSPI peripheral address. + * param data The data to send. + */ void DSPI_SlaveWriteDataBlocking(SPI_Type *base, uint32_t data) { /* First, clear Transmit Complete Flag (TCF) */ - DSPI_ClearStatusFlags(base, kDSPI_TxCompleteFlag); + DSPI_ClearStatusFlags(base, (uint32_t)kDSPI_TxCompleteFlag); while (!(DSPI_GetStatusFlags(base) & kDSPI_TxFifoFillRequestFlag)) { @@ -540,11 +772,25 @@ void DSPI_SlaveWriteDataBlocking(SPI_Type *base, uint32_t data) DSPI_ClearStatusFlags(base, kDSPI_TxFifoFillRequestFlag); /* Wait till TCF sets */ - while (!(DSPI_GetStatusFlags(base) & kDSPI_TxCompleteFlag)) + while (!(DSPI_GetStatusFlags(base) & (uint32_t)kDSPI_TxCompleteFlag)) { } } +/*! + * brief Enables the DSPI interrupts. + * + * This function configures the various interrupt masks of the DSPI. The parameters are a base and an interrupt mask. + * Note, for Tx Fill and Rx FIFO drain requests, enable the interrupt request and disable the DMA request. + * Do not use this API(write to RSER register) while DSPI is in running state. + * + * code + * DSPI_EnableInterrupts(base, kDSPI_TxCompleteInterruptEnable | kDSPI_EndOfQueueInterruptEnable ); + * endcode + * + * param base DSPI peripheral address. + * param mask The interrupt mask; use the enum _dspi_interrupt_enable. + */ void DSPI_EnableInterrupts(SPI_Type *base, uint32_t mask) { if (mask & SPI_RSER_TFFF_RE_MASK) @@ -560,6 +806,17 @@ void DSPI_EnableInterrupts(SPI_Type *base, uint32_t mask) /*Transactional APIs -- Master*/ +/*! + * brief Initializes the DSPI master handle. + * + * This function initializes the DSPI handle, which can be used for other DSPI transactional APIs. Usually, for a + * specified DSPI instance, call this API once to get the initialized handle. + * + * param base DSPI peripheral base address. + * param handle DSPI handle pointer to dspi_master_handle_t. + * param callback DSPI callback. + * param userData Callback function parameter. + */ void DSPI_MasterTransferCreateHandle(SPI_Type *base, dspi_master_handle_t *handle, dspi_master_transfer_callback_t callback, @@ -576,13 +833,23 @@ void DSPI_MasterTransferCreateHandle(SPI_Type *base, handle->userData = userData; } +/*! + * brief DSPI master transfer data using polling. + * + * This function transfers data using polling. This is a blocking function, which does not return until all transfers + * have been completed. + * + * param base DSPI peripheral base address. + * param transfer Pointer to the dspi_transfer_t structure. + * return status of status_t. + */ status_t DSPI_MasterTransferBlocking(SPI_Type *base, dspi_transfer_t *transfer) { assert(transfer); uint16_t wordToSend = 0; uint16_t wordReceived = 0; - uint8_t dummyData = DSPI_DUMMY_DATA; + uint8_t dummyData = g_dspiDummyData[DSPI_GetInstance(base)]; uint8_t bitsPerFrame; uint32_t command; @@ -603,9 +870,9 @@ status_t DSPI_MasterTransferBlocking(SPI_Type *base, dspi_transfer_t *transfer) } DSPI_StopTransfer(base); - DSPI_DisableInterrupts(base, kDSPI_AllInterruptEnable); + DSPI_DisableInterrupts(base, (uint32_t)kDSPI_AllInterruptEnable); DSPI_FlushFifo(base, true, true); - DSPI_ClearStatusFlags(base, kDSPI_AllStatusFlag); + DSPI_ClearStatusFlags(base, (uint32_t)kDSPI_AllStatusFlag); /*Calculate the command and lastCommand*/ commandStruct.whichPcs = @@ -841,11 +1108,11 @@ static void DSPI_MasterTransferPrepare(SPI_Type *base, dspi_master_handle_t *han assert(handle); assert(transfer); - dspi_command_data_config_t commandStruct; + dspi_command_data_config_t commandStruct = {0}; DSPI_StopTransfer(base); DSPI_FlushFifo(base, true, true); - DSPI_ClearStatusFlags(base, kDSPI_AllStatusFlag); + DSPI_ClearStatusFlags(base, (uint32_t)kDSPI_AllStatusFlag); commandStruct.whichPcs = (dspi_which_pcs_t)(1U << ((transfer->configFlags & DSPI_MASTER_PCS_MASK) >> DSPI_MASTER_PCS_SHIFT)); @@ -877,6 +1144,17 @@ static void DSPI_MasterTransferPrepare(SPI_Type *base, dspi_master_handle_t *han handle->totalByteCount = transfer->dataSize; } +/*! + * brief DSPI master transfer data using interrupts. + * + * This function transfers data using interrupts. This is a non-blocking function, which returns right away. When all + * data is transferred, the callback function is called. + + * param base DSPI peripheral base address. + * param handle Pointer to the dspi_master_handle_t structure which stores the transfer state. + * param transfer Pointer to the dspi_transfer_t structure. + * return status of status_t. + */ status_t DSPI_MasterTransferNonBlocking(SPI_Type *base, dspi_master_handle_t *handle, dspi_transfer_t *transfer) { assert(handle); @@ -896,13 +1174,10 @@ status_t DSPI_MasterTransferNonBlocking(SPI_Type *base, dspi_master_handle_t *ha handle->state = kDSPI_Busy; + /* Disable the NVIC for DSPI peripheral. */ + DisableIRQ(s_dspiIRQ[DSPI_GetInstance(base)]); + DSPI_MasterTransferPrepare(base, handle, transfer); - DSPI_StartTransfer(base); - - /* Enable the NVIC for DSPI peripheral. */ - EnableIRQ(s_dspiIRQ[DSPI_GetInstance(base)]); - - DSPI_MasterTransferFillUpTxFifo(base, handle); /* RX FIFO Drain request: RFDF_RE to enable RFDF interrupt * Since SPI is a synchronous interface, we only need to enable the RX interrupt. @@ -911,10 +1186,161 @@ status_t DSPI_MasterTransferNonBlocking(SPI_Type *base, dspi_master_handle_t *ha s_dspiMasterIsr = DSPI_MasterTransferHandleIRQ; DSPI_EnableInterrupts(base, kDSPI_RxFifoDrainRequestInterruptEnable); + DSPI_StartTransfer(base); + + /* Fill up the Tx FIFO to trigger the transfer. */ + DSPI_MasterTransferFillUpTxFifo(base, handle); + + /* Enable the NVIC for DSPI peripheral. */ + EnableIRQ(s_dspiIRQ[DSPI_GetInstance(base)]); return kStatus_Success; } +/*! + * brief Transfers a block of data using a polling method. + * + * This function will do a half-duplex transfer for DSPI master, This is a blocking function, + * which does not retuen until all transfer have been completed. And data transfer will be half-duplex, + * users can set transmit first or receive first. + * + * param base DSPI base pointer + * param xfer pointer to dspi_half_duplex_transfer_t structure + * return status of status_t. + */ +status_t DSPI_MasterHalfDuplexTransferBlocking(SPI_Type *base, dspi_half_duplex_transfer_t *xfer) +{ + assert(xfer); + + dspi_transfer_t tempXfer = {0}; + status_t status; + + if (xfer->isTransmitFirst) + { + tempXfer.txData = xfer->txData; + tempXfer.rxData = NULL; + tempXfer.dataSize = xfer->txDataSize; + } + else + { + tempXfer.txData = NULL; + tempXfer.rxData = xfer->rxData; + tempXfer.dataSize = xfer->rxDataSize; + } + /* If the pcs pin keep assert between transmit and receive. */ + if (xfer->isPcsAssertInTransfer) + { + tempXfer.configFlags = (xfer->configFlags) | kDSPI_MasterActiveAfterTransfer; + } + else + { + tempXfer.configFlags = (xfer->configFlags) & (uint32_t)(~kDSPI_MasterActiveAfterTransfer); + } + + status = DSPI_MasterTransferBlocking(base, &tempXfer); + if (status != kStatus_Success) + { + return status; + } + + if (xfer->isTransmitFirst) + { + tempXfer.txData = NULL; + tempXfer.rxData = xfer->rxData; + tempXfer.dataSize = xfer->rxDataSize; + } + else + { + tempXfer.txData = xfer->txData; + tempXfer.rxData = NULL; + tempXfer.dataSize = xfer->txDataSize; + } + tempXfer.configFlags = xfer->configFlags; + + /* DSPI transfer blocking. */ + status = DSPI_MasterTransferBlocking(base, &tempXfer); + + return status; +} + +/*! + * brief Performs a non-blocking DSPI interrupt transfer. + * + * This function transfers data using interrupts, the transfer mechanism is half-duplex. This is a non-blocking + * function, + * which returns right away. When all data is transferred, the callback function is called. + * + * param base DSPI peripheral base address. + * param handle pointer to dspi_master_handle_t structure which stores the transfer state + * param xfer pointer to dspi_half_duplex_transfer_t structure + * return status of status_t. + */ +status_t DSPI_MasterHalfDuplexTransferNonBlocking(SPI_Type *base, + dspi_master_handle_t *handle, + dspi_half_duplex_transfer_t *xfer) +{ + assert(xfer); + assert(handle); + dspi_transfer_t tempXfer = {0}; + status_t status; + + if (xfer->isTransmitFirst) + { + tempXfer.txData = xfer->txData; + tempXfer.rxData = NULL; + tempXfer.dataSize = xfer->txDataSize; + } + else + { + tempXfer.txData = NULL; + tempXfer.rxData = xfer->rxData; + tempXfer.dataSize = xfer->rxDataSize; + } + /* If the pcs pin keep assert between transmit and receive. */ + if (xfer->isPcsAssertInTransfer) + { + tempXfer.configFlags = (xfer->configFlags) | kDSPI_MasterActiveAfterTransfer; + } + else + { + tempXfer.configFlags = (xfer->configFlags) & (uint32_t)(~kDSPI_MasterActiveAfterTransfer); + } + + status = DSPI_MasterTransferBlocking(base, &tempXfer); + if (status != kStatus_Success) + { + return status; + } + + if (xfer->isTransmitFirst) + { + tempXfer.txData = NULL; + tempXfer.rxData = xfer->rxData; + tempXfer.dataSize = xfer->rxDataSize; + } + else + { + tempXfer.txData = xfer->txData; + tempXfer.rxData = NULL; + tempXfer.dataSize = xfer->txDataSize; + } + tempXfer.configFlags = xfer->configFlags; + + status = DSPI_MasterTransferNonBlocking(base, handle, &tempXfer); + + return status; +} + +/*! + * brief Gets the master transfer count. + * + * This function gets the master transfer count. + * + * param base DSPI peripheral base address. + * param handle Pointer to the dspi_master_handle_t structure which stores the transfer state. + * param count The number of bytes transferred by using the non-blocking transaction. + * return status of status_t. + */ status_t DSPI_MasterTransferGetCount(SPI_Type *base, dspi_master_handle_t *handle, size_t *count) { assert(handle); @@ -965,7 +1391,7 @@ static void DSPI_MasterTransferFillUpTxFifo(SPI_Type *base, dspi_master_handle_t assert(handle); uint16_t wordToSend = 0; - uint8_t dummyData = DSPI_DUMMY_DATA; + uint8_t dummyData = g_dspiDummyData[DSPI_GetInstance(base)]; /* If bits/frame is greater than one byte */ if (handle->bitsPerFrame > 8) @@ -1025,8 +1451,10 @@ static void DSPI_MasterTransferFillUpTxFifo(SPI_Type *base, dspi_master_handle_t /* Try to clear the TFFF; if the TX FIFO is full this will clear */ DSPI_ClearStatusFlags(base, kDSPI_TxFifoFillRequestFlag); - /* exit loop if send count is zero, else update local variables for next loop */ - if (handle->remainingSendByteCount == 0) + /* exit loop if send count is zero, else update local variables for next loop. + * If this is the first time write to the PUSHR, write only once. + */ + if ((handle->remainingSendByteCount == 0) || (handle->remainingSendByteCount == handle->totalByteCount - 2)) { break; } @@ -1067,8 +1495,10 @@ static void DSPI_MasterTransferFillUpTxFifo(SPI_Type *base, dspi_master_handle_t --handle->remainingSendByteCount; - /* exit loop if send count is zero, else update local variables for next loop */ - if (handle->remainingSendByteCount == 0) + /* exit loop if send count is zero, else update local variables for next loop + * If this is the first time write to the PUSHR, write only once. + */ + if ((handle->remainingSendByteCount == 0) || (handle->remainingSendByteCount == handle->totalByteCount - 1)) { break; } @@ -1076,6 +1506,14 @@ static void DSPI_MasterTransferFillUpTxFifo(SPI_Type *base, dspi_master_handle_t } } +/*! + * brief DSPI master aborts a transfer using an interrupt. + * + * This function aborts a transfer using an interrupt. + * + * param base DSPI peripheral base address. + * param handle Pointer to the dspi_master_handle_t structure which stores the transfer state. + */ void DSPI_MasterTransferAbort(SPI_Type *base, dspi_master_handle_t *handle) { assert(handle); @@ -1088,6 +1526,14 @@ void DSPI_MasterTransferAbort(SPI_Type *base, dspi_master_handle_t *handle) handle->state = kDSPI_Idle; } +/*! + * brief DSPI Master IRQ handler function. + * + * This function processes the DSPI transmit and receive IRQ. + + * param base DSPI peripheral base address. + * param handle Pointer to the dspi_master_handle_t structure which stores the transfer state. + */ void DSPI_MasterTransferHandleIRQ(SPI_Type *base, dspi_master_handle_t *handle) { assert(handle); @@ -1115,7 +1561,7 @@ void DSPI_MasterTransferHandleIRQ(SPI_Type *base, dspi_master_handle_t *handle) if (handle->rxData) { /* For the last word received, if there is an extra byte due to the odd transfer - * byte count, only save the the last byte and discard the upper byte + * byte count, only save the last byte and discard the upper byte */ if (handle->remainingReceiveByteCount == 1) { @@ -1195,6 +1641,17 @@ void DSPI_MasterTransferHandleIRQ(SPI_Type *base, dspi_master_handle_t *handle) } /*Transactional APIs -- Slave*/ +/*! + * brief Initializes the DSPI slave handle. + * + * This function initializes the DSPI handle, which can be used for other DSPI transactional APIs. Usually, for a + * specified DSPI instance, call this API once to get the initialized handle. + * + * param handle DSPI handle pointer to the dspi_slave_handle_t. + * param base DSPI peripheral base address. + * param callback DSPI callback. + * param userData Callback function parameter. + */ void DSPI_SlaveTransferCreateHandle(SPI_Type *base, dspi_slave_handle_t *handle, dspi_slave_transfer_callback_t callback, @@ -1211,6 +1668,17 @@ void DSPI_SlaveTransferCreateHandle(SPI_Type *base, handle->userData = userData; } +/*! + * brief DSPI slave transfers data using an interrupt. + * + * This function transfers data using an interrupt. This is a non-blocking function, which returns right away. When all + * data is transferred, the callback function is called. + * + * param base DSPI peripheral base address. + * param handle Pointer to the dspi_slave_handle_t structure which stores the transfer state. + * param transfer Pointer to the dspi_transfer_t structure. + * return status of status_t. + */ status_t DSPI_SlaveTransferNonBlocking(SPI_Type *base, dspi_slave_handle_t *handle, dspi_transfer_t *transfer) { assert(handle); @@ -1254,12 +1722,7 @@ status_t DSPI_SlaveTransferNonBlocking(SPI_Type *base, dspi_slave_handle_t *hand DSPI_StopTransfer(base); DSPI_FlushFifo(base, true, true); - DSPI_ClearStatusFlags(base, kDSPI_AllStatusFlag); - - DSPI_StartTransfer(base); - - /* Prepare data to transmit */ - DSPI_SlaveTransferFillUpTxFifo(base, handle); + DSPI_ClearStatusFlags(base, (uint32_t)kDSPI_AllStatusFlag); s_dspiSlaveIsr = DSPI_SlaveTransferHandleIRQ; @@ -1277,9 +1740,24 @@ status_t DSPI_SlaveTransferNonBlocking(SPI_Type *base, dspi_slave_handle_t *hand DSPI_EnableInterrupts(base, kDSPI_TxFifoUnderflowInterruptEnable); } + DSPI_StartTransfer(base); + + /* Prepare data to transmit */ + DSPI_SlaveTransferFillUpTxFifo(base, handle); + return kStatus_Success; } +/*! + * brief Gets the slave transfer count. + * + * This function gets the slave transfer count. + * + * param base DSPI peripheral base address. + * param handle Pointer to the dspi_master_handle_t structure which stores the transfer state. + * param count The number of bytes transferred by using the non-blocking transaction. + * return status of status_t. + */ status_t DSPI_SlaveTransferGetCount(SPI_Type *base, dspi_slave_handle_t *handle, size_t *count) { assert(handle); @@ -1305,7 +1783,7 @@ static void DSPI_SlaveTransferFillUpTxFifo(SPI_Type *base, dspi_slave_handle_t * assert(handle); uint16_t transmitData = 0; - uint8_t dummyPattern = DSPI_DUMMY_DATA; + uint8_t dummyPattern = g_dspiDummyData[DSPI_GetInstance(base)]; /* Service the transmitter, if transmit buffer provided, transmit the data, * else transmit dummy pattern @@ -1420,6 +1898,14 @@ static void DSPI_SlaveTransferComplete(SPI_Type *base, dspi_slave_handle_t *hand } } +/*! + * brief DSPI slave aborts a transfer using an interrupt. + * + * This function aborts a transfer using an interrupt. + * + * param base DSPI peripheral base address. + * param handle Pointer to the dspi_slave_handle_t structure which stores the transfer state. + */ void DSPI_SlaveTransferAbort(SPI_Type *base, dspi_slave_handle_t *handle) { assert(handle); @@ -1435,11 +1921,19 @@ void DSPI_SlaveTransferAbort(SPI_Type *base, dspi_slave_handle_t *handle) handle->remainingReceiveByteCount = 0; } +/*! + * brief DSPI Master IRQ handler function. + * + * This function processes the DSPI transmit and receive IRQ. + * + * param base DSPI peripheral base address. + * param handle Pointer to the dspi_slave_handle_t structure which stores the transfer state. + */ void DSPI_SlaveTransferHandleIRQ(SPI_Type *base, dspi_slave_handle_t *handle) { assert(handle); - uint8_t dummyPattern = DSPI_DUMMY_DATA; + uint8_t dummyPattern = g_dspiDummyData[DSPI_GetInstance(base)]; uint32_t dataReceived; uint32_t dataSend = 0; @@ -1614,6 +2108,11 @@ static void DSPI_CommonIRQHandler(SPI_Type *base, void *param) { s_dspiSlaveIsr(base, (dspi_slave_handle_t *)param); } +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif } #if defined(SPI0) diff --git a/ext/hal/nxp/mcux/drivers/kinetis/fsl_dspi.h b/ext/hal/nxp/mcux/drivers/kinetis/fsl_dspi.h index 5dd96afcbe0..5bc6566c073 100644 --- a/ext/hal/nxp/mcux/drivers/kinetis/fsl_dspi.h +++ b/ext/hal/nxp/mcux/drivers/kinetis/fsl_dspi.h @@ -1,31 +1,9 @@ /* * Copyright (c) 2015, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP + * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * SPDX-License-Identifier: BSD-3-Clause */ #ifndef _FSL_DSPI_H_ #define _FSL_DSPI_H_ @@ -37,15 +15,14 @@ * @{ */ - /********************************************************************************************************************** * Definitions *********************************************************************************************************************/ /*! @name Driver version */ /*@{*/ -/*! @brief DSPI driver version 2.1.4. */ -#define FSL_DSPI_DRIVER_VERSION (MAKE_VERSION(2, 1, 4)) +/*! @brief DSPI driver version 2.2.0. */ +#define FSL_DSPI_DRIVER_VERSION (MAKE_VERSION(2, 2, 0)) /*@}*/ #ifndef DSPI_DUMMY_DATA @@ -53,6 +30,9 @@ #define DSPI_DUMMY_DATA (0x00U) /*!< Dummy data used for Tx if there is no txData. */ #endif +/*! @brief Global variable for dummy data value setting. */ +extern volatile uint8_t g_dspiDummyData[]; + /*! @brief Status for the DSPI driver.*/ enum _dspi_status { @@ -65,28 +45,28 @@ enum _dspi_status /*! @brief DSPI status flags in SPIx_SR register.*/ enum _dspi_flags { - kDSPI_TxCompleteFlag = SPI_SR_TCF_MASK, /*!< Transfer Complete Flag. */ + kDSPI_TxCompleteFlag = (int)SPI_SR_TCF_MASK, /*!< Transfer Complete Flag. */ kDSPI_EndOfQueueFlag = SPI_SR_EOQF_MASK, /*!< End of Queue Flag.*/ kDSPI_TxFifoUnderflowFlag = SPI_SR_TFUF_MASK, /*!< Transmit FIFO Underflow Flag.*/ kDSPI_TxFifoFillRequestFlag = SPI_SR_TFFF_MASK, /*!< Transmit FIFO Fill Flag.*/ kDSPI_RxFifoOverflowFlag = SPI_SR_RFOF_MASK, /*!< Receive FIFO Overflow Flag.*/ kDSPI_RxFifoDrainRequestFlag = SPI_SR_RFDF_MASK, /*!< Receive FIFO Drain Flag.*/ kDSPI_TxAndRxStatusFlag = SPI_SR_TXRXS_MASK, /*!< The module is in Stopped/Running state.*/ - kDSPI_AllStatusFlag = SPI_SR_TCF_MASK | SPI_SR_EOQF_MASK | SPI_SR_TFUF_MASK | SPI_SR_TFFF_MASK | SPI_SR_RFOF_MASK | - SPI_SR_RFDF_MASK | SPI_SR_TXRXS_MASK /*!< All statuses above.*/ + kDSPI_AllStatusFlag = (int)(SPI_SR_TCF_MASK | SPI_SR_EOQF_MASK | SPI_SR_TFUF_MASK | SPI_SR_TFFF_MASK | + SPI_SR_RFOF_MASK | SPI_SR_RFDF_MASK | SPI_SR_TXRXS_MASK) /*!< All statuses above.*/ }; /*! @brief DSPI interrupt source.*/ enum _dspi_interrupt_enable { - kDSPI_TxCompleteInterruptEnable = SPI_RSER_TCF_RE_MASK, /*!< TCF interrupt enable.*/ + kDSPI_TxCompleteInterruptEnable = (int)SPI_RSER_TCF_RE_MASK, /*!< TCF interrupt enable.*/ kDSPI_EndOfQueueInterruptEnable = SPI_RSER_EOQF_RE_MASK, /*!< EOQF interrupt enable.*/ kDSPI_TxFifoUnderflowInterruptEnable = SPI_RSER_TFUF_RE_MASK, /*!< TFUF interrupt enable.*/ kDSPI_TxFifoFillRequestInterruptEnable = SPI_RSER_TFFF_RE_MASK, /*!< TFFF interrupt enable, DMA disable.*/ kDSPI_RxFifoOverflowInterruptEnable = SPI_RSER_RFOF_RE_MASK, /*!< RFOF interrupt enable.*/ kDSPI_RxFifoDrainRequestInterruptEnable = SPI_RSER_RFDF_RE_MASK, /*!< RFDF interrupt enable, DMA disable.*/ - kDSPI_AllInterruptEnable = SPI_RSER_TCF_RE_MASK | SPI_RSER_EOQF_RE_MASK | SPI_RSER_TFUF_RE_MASK | - SPI_RSER_TFFF_RE_MASK | SPI_RSER_RFOF_RE_MASK | SPI_RSER_RFDF_RE_MASK + kDSPI_AllInterruptEnable = (int)(SPI_RSER_TCF_RE_MASK | SPI_RSER_EOQF_RE_MASK | SPI_RSER_TFUF_RE_MASK | + SPI_RSER_TFFF_RE_MASK | SPI_RSER_RFOF_RE_MASK | SPI_RSER_RFDF_RE_MASK) /*!< All above interrupts enable.*/ }; @@ -107,7 +87,8 @@ typedef enum _dspi_master_slave_mode } dspi_master_slave_mode_t; /*! - * @brief DSPI Sample Point: Controls when the DSPI master samples SIN in the Modified Transfer Format. This field is valid + * @brief DSPI Sample Point: Controls when the DSPI master samples SIN in the Modified Transfer Format. This field is + * valid * only when the CPHA bit in the CTAR register is 0. */ typedef enum _dspi_master_sample_point @@ -216,8 +197,9 @@ enum _dspi_transfer_config_flag_for_master kDSPI_MasterPcs4 = 4U << DSPI_MASTER_PCS_SHIFT, /*!< DSPI master transfer use PCS4 signal. */ kDSPI_MasterPcs5 = 5U << DSPI_MASTER_PCS_SHIFT, /*!< DSPI master transfer use PCS5 signal. */ - kDSPI_MasterPcsContinuous = 1U << 20, /*!< Indicates whether the PCS signal is continuous. */ - kDSPI_MasterActiveAfterTransfer = 1U << 21, /*!< Indicates whether the PCS signal is active after the last frame transfer.*/ + kDSPI_MasterPcsContinuous = 1U << 20, /*!< Indicates whether the PCS signal is continuous. */ + kDSPI_MasterActiveAfterTransfer = + 1U << 21, /*!< Indicates whether the PCS signal is active after the last frame transfer.*/ }; #define DSPI_SLAVE_CTAR_SHIFT (0U) /*!< DSPI slave CTAR shift macro; used internally. */ @@ -240,7 +222,7 @@ enum _dspi_transfer_state /*! @brief DSPI master command date configuration used for the SPIx_PUSHR.*/ typedef struct _dspi_command_data_config { - bool isPcsContinuous; /*!< Option to enable the continuous assertion of the chip select between transfers.*/ + bool isPcsContinuous; /*!< Option to enable the continuous assertion of the chip select between transfers.*/ dspi_ctar_selection_t whichCtar; /*!< The desired Clock and Transfer Attributes Register (CTAR) to use for CTAS.*/ dspi_which_pcs_t whichPcs; /*!< The desired PCS signal to use for the data transfer.*/ @@ -257,10 +239,10 @@ typedef struct _dspi_master_ctar_config dspi_clock_phase_t cpha; /*!< Clock phase. */ dspi_shift_direction_t direction; /*!< MSB or LSB data shift direction. */ - uint32_t pcsToSckDelayInNanoSec; /*!< PCS to SCK delay time in nanoseconds; setting to 0 sets the minimum - delay. It also sets the boundary value if out of range.*/ - uint32_t lastSckToPcsDelayInNanoSec; /*!< The last SCK to PCS delay time in nanoseconds; setting to 0 sets the - minimum delay. It also sets the boundary value if out of range.*/ + uint32_t pcsToSckDelayInNanoSec; /*!< PCS to SCK delay time in nanoseconds; setting to 0 sets the minimum + delay. It also sets the boundary value if out of range.*/ + uint32_t lastSckToPcsDelayInNanoSec; /*!< The last SCK to PCS delay time in nanoseconds; setting to 0 sets the + minimum delay. It also sets the boundary value if out of range.*/ uint32_t betweenTransferDelayInNanoSec; /*!< After the SCK delay time in nanoseconds; setting to 0 sets the minimum delay. It also sets the boundary value if out of range.*/ @@ -361,6 +343,19 @@ typedef struct _dspi_transfer is used for slave.*/ } dspi_transfer_t; +/*! @brief DSPI half-duplex(master) transfer structure */ +typedef struct _dspi_half_duplex_transfer +{ + uint8_t *txData; /*!< Send buffer */ + uint8_t *rxData; /*!< Receive buffer */ + size_t txDataSize; /*!< Transfer bytes for transmit */ + size_t rxDataSize; /*!< Transfer bytes */ + uint32_t configFlags; /*!< Transfer configuration flags; set from _dspi_transfer_config_flag_for_master. */ + bool isPcsAssertInTransfer; /*!< If Pcs pin keep assert between transmit and receive. true for assert and false for + deassert. */ + bool isTransmitFirst; /*!< True for transmit first and false for receive first. */ +} dspi_half_duplex_transfer_t; + /*! @brief DSPI master transfer handle structure used for transactional API. */ struct _dspi_master_handle { @@ -370,8 +365,9 @@ struct _dspi_master_handle uint8_t fifoSize; /*!< FIFO dataSize. */ - volatile bool isPcsActiveAfterTransfer; /*!< Indicates whether the PCS signal is active after the last frame transfer.*/ - volatile bool isThereExtraByte; /*!< Indicates whether there are extra bytes.*/ + volatile bool + isPcsActiveAfterTransfer; /*!< Indicates whether the PCS signal is active after the last frame transfer.*/ + volatile bool isThereExtraByte; /*!< Indicates whether there are extra bytes.*/ uint8_t *volatile txData; /*!< Send buffer. */ uint8_t *volatile rxData; /*!< Receive buffer. */ @@ -575,6 +571,7 @@ static inline void DSPI_ClearStatusFlags(SPI_Type *base, uint32_t statusFlags) * * This function configures the various interrupt masks of the DSPI. The parameters are a base and an interrupt mask. * Note, for Tx Fill and Rx FIFO drain requests, enable the interrupt request and disable the DMA request. + * Do not use this API(write to RSER register) while DSPI is in running state. * * @code * DSPI_EnableInterrupts(base, kDSPI_TxCompleteInterruptEnable | kDSPI_EndOfQueueInterruptEnable ); @@ -688,6 +685,12 @@ static inline uint32_t DSPI_GetRxRegisterAddress(SPI_Type *base) * @name Bus Operations * @{ */ +/*! + * @brief Get instance number for DSPI module. + * + * @param base DSPI peripheral base address. + */ +uint32_t DSPI_GetInstance(SPI_Type *base); /*! * @brief Configures the DSPI for master or slave. @@ -950,10 +953,12 @@ static inline uint32_t DSPI_MasterGetFormattedCommand(dspi_command_data_config_t * @brief Writes a 32-bit data word (16-bit command appended with 16-bit data) into the data * buffer master mode and waits till complete to return. * - * In this function, the user must append the 16-bit data to the 16-bit command information and then provide the total 32-bit word + * In this function, the user must append the 16-bit data to the 16-bit command information and then provide the total +* 32-bit word * as the data to send. * The command portion provides characteristics of the data, such as the optional continuous chip select operation - * between transfers, the desired Clock and Transfer Attributes register to use for the associated SPI frame, the desired PCS + * between transfers, the desired Clock and Transfer Attributes register to use for the associated SPI frame, the +* desired PCS * signal to use for the data transfer, whether the current transfer is the last in the queue, and whether to clear the * transfer count (normally needed when sending the first frame of a data packet). The user is responsible for * appending this command with the data to send. This is an example: @@ -1022,6 +1027,14 @@ static inline uint32_t DSPI_ReadData(SPI_Type *base) return (base->POPR); } +/*! + * @brief Set up the dummy data. + * + * @param base DSPI peripheral address. + * @param dummyData Data to be transferred when tx buffer is NULL. + */ +void DSPI_SetDummyData(SPI_Type *base, uint8_t dummyData); + /*! *@} */ @@ -1073,6 +1086,35 @@ status_t DSPI_MasterTransferBlocking(SPI_Type *base, dspi_transfer_t *transfer); */ status_t DSPI_MasterTransferNonBlocking(SPI_Type *base, dspi_master_handle_t *handle, dspi_transfer_t *transfer); +/*! + * @brief Transfers a block of data using a polling method. + * + * This function will do a half-duplex transfer for DSPI master, This is a blocking function, + * which does not retuen until all transfer have been completed. And data transfer will be half-duplex, + * users can set transmit first or receive first. + * + * @param base DSPI base pointer + * @param xfer pointer to dspi_half_duplex_transfer_t structure + * @return status of status_t. + */ +status_t DSPI_MasterHalfDuplexTransferBlocking(SPI_Type *base, dspi_half_duplex_transfer_t *xfer); + +/*! + * @brief Performs a non-blocking DSPI interrupt transfer. + * + * This function transfers data using interrupts, the transfer mechanism is half-duplex. This is a non-blocking + * function, + * which returns right away. When all data is transferred, the callback function is called. + * + * @param base DSPI peripheral base address. + * @param handle pointer to dspi_master_handle_t structure which stores the transfer state + * @param xfer pointer to dspi_half_duplex_transfer_t structure + * @return status of status_t. + */ +status_t DSPI_MasterHalfDuplexTransferNonBlocking(SPI_Type *base, + dspi_master_handle_t *handle, + dspi_half_duplex_transfer_t *xfer); + /*! * @brief Gets the master transfer count. * diff --git a/ext/hal/nxp/mcux/drivers/kinetis/fsl_dspi_edma.c b/ext/hal/nxp/mcux/drivers/kinetis/fsl_dspi_edma.c index ef0d15174f5..be8d6bd2c55 100644 --- a/ext/hal/nxp/mcux/drivers/kinetis/fsl_dspi_edma.c +++ b/ext/hal/nxp/mcux/drivers/kinetis/fsl_dspi_edma.c @@ -1,39 +1,22 @@ /* * Copyright (c) 2015, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP + * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * SPDX-License-Identifier: BSD-3-Clause */ #include "fsl_dspi_edma.h" /*********************************************************************************************************************** -* Definitons +* Definitions ***********************************************************************************************************************/ +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.dspi_edma" +#endif + /*! * @brief Structure definition for dspi_master_edma_private_handle_t. The structure is private. */ @@ -72,14 +55,6 @@ static void EDMA_DspiSlaveCallback(edma_handle_t *edmaHandle, void *g_dspiEdmaPrivateHandle, bool transferDone, uint32_t tcds); -/*! -* @brief Get instance number for DSPI module. -* -* This is not a public API and it's extern from fsl_dspi.c. -* -* @param base DSPI peripheral base address -*/ -extern uint32_t DSPI_GetInstance(SPI_Type *base); /*********************************************************************************************************************** * Variables @@ -93,6 +68,26 @@ static dspi_slave_edma_private_handle_t s_dspiSlaveEdmaPrivateHandle[FSL_FEATURE * Code ***********************************************************************************************************************/ +/*! + * brief Initializes the DSPI master eDMA handle. + * + * This function initializes the DSPI eDMA handle which can be used for other DSPI transactional APIs. Usually, for a + * specified DSPI instance, call this API once to get the initialized handle. + * + * Note that DSPI eDMA has separated (RX and TX as two sources) or shared (RX and TX are the same source) DMA request + * source. + * (1) For the separated DMA request source, enable and set the RX DMAMUX source for edmaRxRegToRxDataHandle and + * TX DMAMUX source for edmaIntermediaryToTxRegHandle. + * (2) For the shared DMA request source, enable and set the RX/RX DMAMUX source for the edmaRxRegToRxDataHandle. + * + * param base DSPI peripheral base address. + * param handle DSPI handle pointer to dspi_master_edma_handle_t. + * param callback DSPI callback. + * param userData A callback function parameter. + * param edmaRxRegToRxDataHandle edmaRxRegToRxDataHandle pointer to edma_handle_t. + * param edmaTxDataToIntermediaryHandle edmaTxDataToIntermediaryHandle pointer to edma_handle_t. + * param edmaIntermediaryToTxRegHandle edmaIntermediaryToTxRegHandle pointer to edma_handle_t. + */ void DSPI_MasterTransferCreateHandleEDMA(SPI_Type *base, dspi_master_edma_handle_t *handle, dspi_master_edma_transfer_callback_t callback, @@ -103,7 +98,9 @@ void DSPI_MasterTransferCreateHandleEDMA(SPI_Type *base, { assert(handle); assert(edmaRxRegToRxDataHandle); +#if (!(defined(FSL_FEATURE_DSPI_HAS_GASKET) && FSL_FEATURE_DSPI_HAS_GASKET)) assert(edmaTxDataToIntermediaryHandle); +#endif assert(edmaIntermediaryToTxRegHandle); /* Zero the handle. */ @@ -122,6 +119,17 @@ void DSPI_MasterTransferCreateHandleEDMA(SPI_Type *base, handle->edmaIntermediaryToTxRegHandle = edmaIntermediaryToTxRegHandle; } +/*! + * brief DSPI master transfer data using eDMA. + * + * This function transfers data using eDMA. This is a non-blocking function, which returns right away. When all data + * is transferred, the callback function is called. + * + * param base DSPI peripheral base address. + * param handle A pointer to the dspi_master_edma_handle_t structure which stores the transfer state. + * param transfer A pointer to the dspi_transfer_t structure. + * return status of status_t. + */ status_t DSPI_MasterTransferEDMA(SPI_Type *base, dspi_master_edma_handle_t *handle, dspi_transfer_t *transfer) { assert(handle); @@ -149,7 +157,7 @@ status_t DSPI_MasterTransferEDMA(SPI_Type *base, dspi_master_edma_handle_t *hand uint32_t instance = DSPI_GetInstance(base); uint16_t wordToSend = 0; - uint8_t dummyData = DSPI_DUMMY_DATA; + uint8_t dummyData = g_dspiDummyData[DSPI_GetInstance(base)]; uint8_t dataAlreadyFed = 0; uint8_t dataFedMax = 2; @@ -160,14 +168,13 @@ status_t DSPI_MasterTransferEDMA(SPI_Type *base, dspi_master_edma_handle_t *hand edma_transfer_config_t transferConfigA; edma_transfer_config_t transferConfigB; - edma_transfer_config_t transferConfigC; - handle->txBuffIfNull = ((uint32_t)DSPI_DUMMY_DATA << 8) | DSPI_DUMMY_DATA; + handle->txBuffIfNull = ((uint32_t)dummyData << 8) | dummyData; dspi_command_data_config_t commandStruct; DSPI_StopTransfer(base); DSPI_FlushFifo(base, true, true); - DSPI_ClearStatusFlags(base, kDSPI_AllStatusFlag); + DSPI_ClearStatusFlags(base, (uint32_t)kDSPI_AllStatusFlag); commandStruct.whichPcs = (dspi_which_pcs_t)(1U << ((transfer->configFlags & DSPI_MASTER_PCS_MASK) >> DSPI_MASTER_PCS_SHIFT)); @@ -331,11 +338,10 @@ status_t DSPI_MasterTransferEDMA(SPI_Type *base, dspi_master_edma_handle_t *hand } else /*dspi has shared dma request*/ - { /* For DSPI instances with shared RX/TX DMA requests, we'll use the RX DMA request to - * trigger ongoing transfers and will link to the TX DMA channel from the RX DMA channel. - */ + * trigger ongoing transfers and will link to the TX DMA channel from the RX DMA channel. + */ /* If bits/frame is greater than one byte */ if (handle->bitsPerFrame > 8) @@ -466,12 +472,6 @@ status_t DSPI_MasterTransferEDMA(SPI_Type *base, dspi_master_edma_handle_t *hand EDMA_EnableChannelInterrupts(handle->edmaRxRegToRxDataHandle->base, handle->edmaRxRegToRxDataHandle->channel, kEDMA_MajorInterruptEnable); - /***channel_B *** used for carry the data from User_Send_Buffer to "intermediary" because the SPIx_PUSHR should - write the 32bits at once time . Then use channel_C to carry the "intermediary" to SPIx_PUSHR. Note that the - SPIx_PUSHR upper 16 bits are the "command" and the low 16bits are data */ - - EDMA_ResetChannel(handle->edmaTxDataToIntermediaryHandle->base, handle->edmaTxDataToIntermediaryHandle->channel); - /*Calculate the last data : handle->lastCommand*/ if (((handle->remainingSendByteCount > 0) && (1 != FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base))) || ((((handle->remainingSendByteCount > 1) && (handle->bitsPerFrame <= 8)) || @@ -523,6 +523,153 @@ status_t DSPI_MasterTransferEDMA(SPI_Type *base, dspi_master_edma_handle_t *hand } } +/* The feature of GASKET is that the SPI supports 8-bit or 16-bit writes to the PUSH TX FIFO, + * allowing a single write to the command word followed by multiple writes to the transmit word. + * The TX FIFO will save the last command word written, and convert a 8-bit/16-bit write to the + * transmit word into a 32-bit write that pushes both the command word and transmit word into + * the TX FIFO (PUSH TX FIFO Register In Master Mode) + * So, if this feature is supported, we can use use one channel to carry the receive data from + * receive regsiter to user data buffer, use the other channel to carry the data from user data buffer + * to transmit register,and use the scatter/gather function to prepare the last data. + * That is to say, if GASKET feature is supported, we can use only two channels for tansferring data. + */ +#if defined(FSL_FEATURE_DSPI_HAS_GASKET) && FSL_FEATURE_DSPI_HAS_GASKET + /* For DSPI instances with separate RX and TX DMA requests: use the scatter/gather to prepare the last data + * (handle->lastCommand) to PUSHR register. + */ + + EDMA_ResetChannel(handle->edmaIntermediaryToTxRegHandle->base, handle->edmaIntermediaryToTxRegHandle->channel); + + if ((1 == FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base)) || + ((handle->remainingSendByteCount > 0) && (1 != FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base)))) + { + transferConfigB.srcAddr = (uint32_t) & (handle->lastCommand); + transferConfigB.destAddr = (uint32_t)txAddr; + transferConfigB.srcTransferSize = kEDMA_TransferSize4Bytes; + transferConfigB.destTransferSize = kEDMA_TransferSize4Bytes; + transferConfigB.srcOffset = 0; + transferConfigB.destOffset = 0; + transferConfigB.minorLoopBytes = 4; + transferConfigB.majorLoopCounts = 1; + + EDMA_TcdReset(softwareTCD); + EDMA_TcdSetTransferConfig(softwareTCD, &transferConfigB, NULL); + } + + /*User_Send_Buffer(txData) to PUSHR register. */ + if (((handle->remainingSendByteCount > 2) && (handle->bitsPerFrame <= 8)) || + ((handle->remainingSendByteCount > 4) && (handle->bitsPerFrame > 8))) + { + if (handle->txData) + { + if (1 == FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base)) + { + /* For DSPI with separate RX and TX DMA requests, one frame data has been carry + * to handle->command, so need to reduce the pointer of txData. + */ + transferConfigB.srcAddr = + (uint32_t)((uint8_t *)(handle->txData) - ((handle->bitsPerFrame <= 8) ? (1U) : (2U))); + transferConfigB.srcOffset = 1; + } + else + { + /* For DSPI with shared RX and TX DMA requests, one or two frame data have been carry + * to PUSHR register, so no need to change the pointer of txData. + */ + transferConfigB.srcAddr = (uint32_t)((uint8_t *)(handle->txData)); + transferConfigB.srcOffset = 1; + } + } + else + { + transferConfigB.srcAddr = (uint32_t)(&handle->txBuffIfNull); + transferConfigB.srcOffset = 0; + } + + transferConfigB.destAddr = (uint32_t)txAddr; + transferConfigB.destOffset = 0; + + transferConfigB.srcTransferSize = kEDMA_TransferSize1Bytes; + + if (handle->bitsPerFrame <= 8) + { + transferConfigB.destTransferSize = kEDMA_TransferSize1Bytes; + transferConfigB.minorLoopBytes = 1; + + transferConfigB.majorLoopCounts = handle->remainingSendByteCount - 1; + } + else + { + transferConfigB.destTransferSize = kEDMA_TransferSize2Bytes; + transferConfigB.minorLoopBytes = 2; + transferConfigB.majorLoopCounts = (handle->remainingSendByteCount / 2) - 1; + } + + EDMA_SetTransferConfig(handle->edmaIntermediaryToTxRegHandle->base, + handle->edmaIntermediaryToTxRegHandle->channel, &transferConfigB, softwareTCD); + } + /* If only one word to transmit, only carry the lastcommand. */ + else + { + EDMA_SetTransferConfig(handle->edmaIntermediaryToTxRegHandle->base, + handle->edmaIntermediaryToTxRegHandle->channel, &transferConfigB, NULL); + } + + /*Start the EDMA channel_A , channel_C. */ + EDMA_StartTransfer(handle->edmaRxRegToRxDataHandle); + EDMA_StartTransfer(handle->edmaIntermediaryToTxRegHandle); + + /* Set the channel link. + * For DSPI instances with shared TX and RX DMA requests, setup channel minor link, first receive data from the + * receive register, and then carry transmit data to PUSHER register. + * For DSPI instance with separate TX and RX DMA requests, there is no need to set up channel link. + */ + if (1 != FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base)) + { + /*Set channel priority*/ + uint8_t channelPriorityLow = handle->edmaRxRegToRxDataHandle->channel; + uint8_t channelPriorityHigh = handle->edmaIntermediaryToTxRegHandle->channel; + uint8_t t = 0; + + if (channelPriorityLow > channelPriorityHigh) + { + t = channelPriorityLow; + channelPriorityLow = channelPriorityHigh; + channelPriorityHigh = t; + } + + edma_channel_Preemption_config_t preemption_config_t; + preemption_config_t.enableChannelPreemption = true; + preemption_config_t.enablePreemptAbility = true; + preemption_config_t.channelPriority = channelPriorityLow; + + EDMA_SetChannelPreemptionConfig(handle->edmaRxRegToRxDataHandle->base, handle->edmaRxRegToRxDataHandle->channel, + &preemption_config_t); + + preemption_config_t.channelPriority = channelPriorityHigh; + EDMA_SetChannelPreemptionConfig(handle->edmaIntermediaryToTxRegHandle->base, + handle->edmaIntermediaryToTxRegHandle->channel, &preemption_config_t); + /*if there is Rx DMA request , carry the 32bits data (handle->command) to user data first , then link to + channelC to carry the next data to PUSHER register.(txData to PUSHER) */ + if (handle->remainingSendByteCount > 0) + { + EDMA_SetChannelLink(handle->edmaRxRegToRxDataHandle->base, handle->edmaRxRegToRxDataHandle->channel, + kEDMA_MinorLink, handle->edmaIntermediaryToTxRegHandle->channel); + } + } + + DSPI_EnableDMA(base, kDSPI_RxDmaEnable | kDSPI_TxDmaEnable); + + /* Setup control info to PUSHER register. */ + *((uint16_t *)&(base->PUSHR) + 1) = (handle->command >> 16U); +#else + + /***channel_B *** used for carry the data from User_Send_Buffer to "intermediary" because the SPIx_PUSHR should + write the 32bits at once time . Then use channel_C to carry the "intermediary" to SPIx_PUSHR. Note that the + SPIx_PUSHR upper 16 bits are the "command" and the low 16bits are data */ + + EDMA_ResetChannel(handle->edmaTxDataToIntermediaryHandle->base, handle->edmaTxDataToIntermediaryHandle->channel); + /*For DSPI instances with separate RX and TX DMA requests: use the scatter/gather to prepare the last data * (handle->lastCommand) to handle->Command*/ if (1 == FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base)) @@ -616,6 +763,7 @@ status_t DSPI_MasterTransferEDMA(SPI_Type *base, dspi_master_edma_handle_t *hand /***channel_C ***carry the "intermediary" to SPIx_PUSHR. used the edma Scatter Gather function on channel_C to handle the last data */ + edma_transfer_config_t transferConfigC; EDMA_ResetChannel(handle->edmaIntermediaryToTxRegHandle->base, handle->edmaIntermediaryToTxRegHandle->channel); /*For DSPI instances with shared RX/TX DMA requests: use the scatter/gather to prepare the last data @@ -768,12 +916,78 @@ status_t DSPI_MasterTransferEDMA(SPI_Type *base, dspi_master_edma_handle_t *hand DSPI_EnableDMA(base, kDSPI_RxDmaEnable); } - +#endif DSPI_StartTransfer(base); return kStatus_Success; } +/*! + * brief Transfers a block of data using a eDMA method. + * + * This function transfers data using eDNA, the transfer mechanism is half-duplex. This is a non-blocking function, + * which returns right away. When all data is transferred, the callback function is called. + * + * param base DSPI base pointer + * param handle A pointer to the dspi_master_edma_handle_t structure which stores the transfer state. + * param transfer A pointer to the dspi_half_duplex_transfer_t structure. + * return status of status_t. + */ +status_t DSPI_MasterHalfDuplexTransferEDMA(SPI_Type *base, + dspi_master_edma_handle_t *handle, + dspi_half_duplex_transfer_t *xfer) +{ + assert(xfer); + assert(handle); + dspi_transfer_t tempXfer = {0}; + status_t status; + + if (xfer->isTransmitFirst) + { + tempXfer.txData = xfer->txData; + tempXfer.rxData = NULL; + tempXfer.dataSize = xfer->txDataSize; + } + else + { + tempXfer.txData = NULL; + tempXfer.rxData = xfer->rxData; + tempXfer.dataSize = xfer->rxDataSize; + } + /* If the pcs pin keep assert between transmit and receive. */ + if (xfer->isPcsAssertInTransfer) + { + tempXfer.configFlags = (xfer->configFlags) | kDSPI_MasterActiveAfterTransfer; + } + else + { + tempXfer.configFlags = (xfer->configFlags) & (uint32_t)(~kDSPI_MasterActiveAfterTransfer); + } + + status = DSPI_MasterTransferBlocking(base, &tempXfer); + if (status != kStatus_Success) + { + return status; + } + + if (xfer->isTransmitFirst) + { + tempXfer.txData = NULL; + tempXfer.rxData = xfer->rxData; + tempXfer.dataSize = xfer->rxDataSize; + } + else + { + tempXfer.txData = xfer->txData; + tempXfer.rxData = NULL; + tempXfer.dataSize = xfer->txDataSize; + } + tempXfer.configFlags = xfer->configFlags; + + status = DSPI_MasterTransferEDMA(base, handle, &tempXfer); + + return status; +} static void EDMA_DspiMasterCallback(edma_handle_t *edmaHandle, void *g_dspiEdmaPrivateHandle, bool transferDone, @@ -797,6 +1011,14 @@ static void EDMA_DspiMasterCallback(edma_handle_t *edmaHandle, } } +/*! + * brief DSPI master aborts a transfer which is using eDMA. + * + * This function aborts a transfer which is using eDMA. + * + * param base DSPI peripheral base address. + * param handle A pointer to the dspi_master_edma_handle_t structure which stores the transfer state. + */ void DSPI_MasterTransferAbortEDMA(SPI_Type *base, dspi_master_edma_handle_t *handle) { assert(handle); @@ -812,6 +1034,16 @@ void DSPI_MasterTransferAbortEDMA(SPI_Type *base, dspi_master_edma_handle_t *han handle->state = kDSPI_Idle; } +/*! + * brief Gets the master eDMA transfer count. + * + * This function gets the master eDMA transfer count. + * + * param base DSPI peripheral base address. + * param handle A pointer to the dspi_master_edma_handle_t structure which stores the transfer state. + * param count A number of bytes transferred by the non-blocking transaction. + * return status of status_t. + */ status_t DSPI_MasterTransferGetCountEDMA(SPI_Type *base, dspi_master_edma_handle_t *handle, size_t *count) { assert(handle); @@ -838,6 +1070,25 @@ status_t DSPI_MasterTransferGetCountEDMA(SPI_Type *base, dspi_master_edma_handle return kStatus_Success; } +/*! + * brief Initializes the DSPI slave eDMA handle. + * + * This function initializes the DSPI eDMA handle which can be used for other DSPI transactional APIs. Usually, for a + * specified DSPI instance, call this API once to get the initialized handle. + * + * Note that DSPI eDMA has separated (RN and TX in 2 sources) or shared (RX and TX are the same source) DMA request + * source. + * (1)For the separated DMA request source, enable and set the RX DMAMUX source for edmaRxRegToRxDataHandle and + * TX DMAMUX source for edmaTxDataToTxRegHandle. + * (2)For the shared DMA request source, enable and set the RX/RX DMAMUX source for the edmaRxRegToRxDataHandle. + * + * param base DSPI peripheral base address. + * param handle DSPI handle pointer to dspi_slave_edma_handle_t. + * param callback DSPI callback. + * param userData A callback function parameter. + * param edmaRxRegToRxDataHandle edmaRxRegToRxDataHandle pointer to edma_handle_t. + * param edmaTxDataToTxRegHandle edmaTxDataToTxRegHandle pointer to edma_handle_t. + */ void DSPI_SlaveTransferCreateHandleEDMA(SPI_Type *base, dspi_slave_edma_handle_t *handle, dspi_slave_edma_transfer_callback_t callback, @@ -864,6 +1115,19 @@ void DSPI_SlaveTransferCreateHandleEDMA(SPI_Type *base, handle->edmaTxDataToTxRegHandle = edmaTxDataToTxRegHandle; } +/*! + * brief DSPI slave transfer data using eDMA. + * + * This function transfers data using eDMA. This is a non-blocking function, which returns right away. When all data + * is transferred, the callback function is called. + * Note that the slave eDMA transfer doesn't support transfer_size is 1 when the bitsPerFrame is greater + * than eight. + + * param base DSPI peripheral base address. + * param handle A pointer to the dspi_slave_edma_handle_t structure which stores the transfer state. + * param transfer A pointer to the dspi_transfer_t structure. + * return status of status_t. + */ status_t DSPI_SlaveTransferEDMA(SPI_Type *base, dspi_slave_edma_handle_t *handle, dspi_transfer_t *transfer) { assert(handle); @@ -941,7 +1205,7 @@ status_t DSPI_SlaveTransferEDMA(SPI_Type *base, dspi_slave_edma_handle_t *handle handle->totalByteCount = transfer->dataSize; uint16_t wordToSend = 0; - uint8_t dummyData = DSPI_DUMMY_DATA; + uint8_t dummyData = g_dspiDummyData[DSPI_GetInstance(base)]; uint8_t dataAlreadyFed = 0; uint8_t dataFedMax = 2; @@ -954,7 +1218,7 @@ status_t DSPI_SlaveTransferEDMA(SPI_Type *base, dspi_slave_edma_handle_t *handle DSPI_StopTransfer(base); DSPI_FlushFifo(base, true, true); - DSPI_ClearStatusFlags(base, kDSPI_AllStatusFlag); + DSPI_ClearStatusFlags(base, (uint32_t)kDSPI_AllStatusFlag); DSPI_DisableDMA(base, kDSPI_RxDmaEnable | kDSPI_TxDmaEnable); @@ -1095,11 +1359,11 @@ status_t DSPI_SlaveTransferEDMA(SPI_Type *base, dspi_slave_edma_handle_t *handle transferConfigC.srcOffset = 0; if (handle->bitsPerFrame <= 8) { - handle->txBuffIfNull = DSPI_DUMMY_DATA; + handle->txBuffIfNull = dummyData; } else { - handle->txBuffIfNull = (DSPI_DUMMY_DATA << 8) | DSPI_DUMMY_DATA; + handle->txBuffIfNull = ((uint32_t)dummyData << 8) | dummyData; } } @@ -1207,6 +1471,14 @@ static void EDMA_DspiSlaveCallback(edma_handle_t *edmaHandle, } } +/*! + * brief DSPI slave aborts a transfer which is using eDMA. + * + * This function aborts a transfer which is using eDMA. + * + * param base DSPI peripheral base address. + * param handle A pointer to the dspi_slave_edma_handle_t structure which stores the transfer state. + */ void DSPI_SlaveTransferAbortEDMA(SPI_Type *base, dspi_slave_edma_handle_t *handle) { assert(handle); @@ -1221,6 +1493,16 @@ void DSPI_SlaveTransferAbortEDMA(SPI_Type *base, dspi_slave_edma_handle_t *handl handle->state = kDSPI_Idle; } +/*! + * brief Gets the slave eDMA transfer count. + * + * This function gets the slave eDMA transfer count. + * + * param base DSPI peripheral base address. + * param handle A pointer to the dspi_slave_edma_handle_t structure which stores the transfer state. + * param count A number of bytes transferred so far by the non-blocking transaction. + * return status of status_t. + */ status_t DSPI_SlaveTransferGetCountEDMA(SPI_Type *base, dspi_slave_edma_handle_t *handle, size_t *count) { assert(handle); diff --git a/ext/hal/nxp/mcux/drivers/kinetis/fsl_dspi_edma.h b/ext/hal/nxp/mcux/drivers/kinetis/fsl_dspi_edma.h index 23e29ce2983..7b0a8024954 100644 --- a/ext/hal/nxp/mcux/drivers/kinetis/fsl_dspi_edma.h +++ b/ext/hal/nxp/mcux/drivers/kinetis/fsl_dspi_edma.h @@ -1,31 +1,9 @@ /* * Copyright (c) 2015, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP + * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * SPDX-License-Identifier: BSD-3-Clause */ #ifndef _FSL_DSPI_EDMA_H_ #define _FSL_DSPI_EDMA_H_ @@ -41,6 +19,12 @@ * Definitions **********************************************************************************************************************/ +/*! @name Driver version */ +/*@{*/ +/*! @brief DSPI EDMA driver version 2.2.0. */ +#define FSL_DSPI_EDMA_DRIVER_VERSION (MAKE_VERSION(2, 2, 0)) +/*@}*/ + /*! * @brief Forward declaration of the DSPI eDMA master handle typedefs. */ @@ -186,6 +170,21 @@ void DSPI_MasterTransferCreateHandleEDMA(SPI_Type *base, */ status_t DSPI_MasterTransferEDMA(SPI_Type *base, dspi_master_edma_handle_t *handle, dspi_transfer_t *transfer); +/*! + * @brief Transfers a block of data using a eDMA method. + * + * This function transfers data using eDNA, the transfer mechanism is half-duplex. This is a non-blocking function, + * which returns right away. When all data is transferred, the callback function is called. + * + * @param base DSPI base pointer + * @param handle A pointer to the dspi_master_edma_handle_t structure which stores the transfer state. + * @param transfer A pointer to the dspi_half_duplex_transfer_t structure. + * @return status of status_t. + */ +status_t DSPI_MasterHalfDuplexTransferEDMA(SPI_Type *base, + dspi_master_edma_handle_t *handle, + dspi_half_duplex_transfer_t *xfer); + /*! * @brief DSPI master aborts a transfer which is using eDMA. * diff --git a/ext/hal/nxp/mcux/drivers/kinetis/fsl_edma.c b/ext/hal/nxp/mcux/drivers/kinetis/fsl_edma.c index 65f37619fe7..cd4b56b5e9b 100644 --- a/ext/hal/nxp/mcux/drivers/kinetis/fsl_edma.c +++ b/ext/hal/nxp/mcux/drivers/kinetis/fsl_edma.c @@ -1,31 +1,9 @@ /* * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP + * Copyright 2016-2018 NXP + * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * SPDX-License-Identifier: BSD-3-Clause */ #include "fsl_edma.h" @@ -34,6 +12,11 @@ * Definitions ******************************************************************************/ +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.edma" +#endif + #define EDMA_TRANSFER_ENABLED_MASK 0x80U /******************************************************************************* @@ -87,6 +70,13 @@ static uint32_t EDMA_GetInstance(DMA_Type *base) return instance; } +/*! + * brief Push content of TCD structure into hardware TCD register. + * + * param base EDMA peripheral base address. + * param channel EDMA channel number. + * param tcd Point to TCD structure. + */ void EDMA_InstallTCD(DMA_Type *base, uint32_t channel, edma_tcd_t *tcd) { assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL); @@ -109,6 +99,16 @@ void EDMA_InstallTCD(DMA_Type *base, uint32_t channel, edma_tcd_t *tcd) base->TCD[channel].BITER_ELINKNO = tcd->BITER; } +/*! + * brief Initializes the eDMA peripheral. + * + * This function ungates the eDMA clock and configures the eDMA peripheral according + * to the configuration structure. + * + * param base eDMA peripheral base address. + * param config A pointer to the configuration structure, see "edma_config_t". + * note This function enables the minor loop map feature. + */ void EDMA_Init(DMA_Type *base, const edma_config_t *config) { assert(config != NULL); @@ -116,9 +116,14 @@ void EDMA_Init(DMA_Type *base, const edma_config_t *config) uint32_t tmpreg; #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Ungate EDMA periphral clock */ + /* Ungate EDMA peripheral clock */ CLOCK_EnableClock(s_edmaClockName[EDMA_GetInstance(base)]); #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + + /* clear all the enabled request, status to make sure EDMA status is in normal condition */ + base->ERQ = 0U; + base->INT = 0xFFFFFFFFU; + base->ERR = 0xFFFFFFFFU; /* Configure EDMA peripheral according to the configuration structure. */ tmpreg = base->CR; tmpreg &= ~(DMA_CR_ERCA_MASK | DMA_CR_HOE_MASK | DMA_CR_CLM_MASK | DMA_CR_EDBG_MASK); @@ -127,24 +132,59 @@ void EDMA_Init(DMA_Type *base, const edma_config_t *config) base->CR = tmpreg; } +/*! + * brief Deinitializes the eDMA peripheral. + * + * This function gates the eDMA clock. + * + * param base eDMA peripheral base address. + */ void EDMA_Deinit(DMA_Type *base) { #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Gate EDMA periphral clock */ + /* Gate EDMA peripheral clock */ CLOCK_DisableClock(s_edmaClockName[EDMA_GetInstance(base)]); #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ } +/*! + * brief Gets the eDMA default configuration structure. + * + * This function sets the configuration structure to default values. + * The default configuration is set to the following values. + * code + * config.enableContinuousLinkMode = false; + * config.enableHaltOnError = true; + * config.enableRoundRobinArbitration = false; + * config.enableDebugMode = false; + * endcode + * + * param config A pointer to the eDMA configuration structure. + */ void EDMA_GetDefaultConfig(edma_config_t *config) { assert(config != NULL); + /* Initializes the configure structure to zero. */ + memset(config, 0, sizeof(*config)); + config->enableRoundRobinArbitration = false; config->enableHaltOnError = true; config->enableContinuousLinkMode = false; config->enableDebugMode = false; } +/*! + * brief Sets all TCD registers to default values. + * + * This function sets TCD registers for this channel to default values. + * + * param base eDMA peripheral base address. + * param channel eDMA channel number. + * note This function must not be called while the channel transfer is ongoing + * or it causes unpredictable results. + * note This function enables the auto stop request feature. + */ void EDMA_ResetChannel(DMA_Type *base, uint32_t channel) { assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL); @@ -152,6 +192,31 @@ void EDMA_ResetChannel(DMA_Type *base, uint32_t channel) EDMA_TcdReset((edma_tcd_t *)&base->TCD[channel]); } +/*! + * brief Configures the eDMA transfer attribute. + * + * This function configures the transfer attribute, including source address, destination address, + * transfer size, address offset, and so on. It also configures the scatter gather feature if the + * user supplies the TCD address. + * Example: + * code + * edma_transfer_t config; + * edma_tcd_t tcd; + * config.srcAddr = ..; + * config.destAddr = ..; + * ... + * EDMA_SetTransferConfig(DMA0, channel, &config, &stcd); + * endcode + * + * param base eDMA peripheral base address. + * param channel eDMA channel number. + * param config Pointer to eDMA transfer configuration structure. + * param nextTcd Point to TCD structure. It can be NULL if users + * do not want to enable scatter/gather feature. + * note If nextTcd is not NULL, it means scatter gather feature is enabled + * and DREQ bit is cleared in the previous transfer configuration, which + * is set in the eDMA_ResetChannel. + */ void EDMA_SetTransferConfig(DMA_Type *base, uint32_t channel, const edma_transfer_config_t *config, edma_tcd_t *nextTcd) { assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL); @@ -161,6 +226,16 @@ void EDMA_SetTransferConfig(DMA_Type *base, uint32_t channel, const edma_transfe EDMA_TcdSetTransferConfig((edma_tcd_t *)&base->TCD[channel], config, nextTcd); } +/*! + * brief Configures the eDMA minor offset feature. + * + * The minor offset means that the signed-extended value is added to the source address or destination + * address after each minor loop. + * + * param base eDMA peripheral base address. + * param channel eDMA channel number. + * param config A pointer to the minor offset configuration structure. + */ void EDMA_SetMinorOffsetConfig(DMA_Type *base, uint32_t channel, const edma_minor_offset_config_t *config) { assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL); @@ -176,6 +251,22 @@ void EDMA_SetMinorOffsetConfig(DMA_Type *base, uint32_t channel, const edma_mino base->TCD[channel].NBYTES_MLOFFYES = tmpreg; } +/*! + * brief Sets the channel link for the eDMA transfer. + * + * This function configures either the minor link or the major link mode. The minor link means that the channel link is + * triggered every time CITER decreases by 1. The major link means that the channel link is triggered when the CITER is + * exhausted. + * + * param base eDMA peripheral base address. + * param channel eDMA channel number. + * param type A channel link type, which can be one of the following: + * arg kEDMA_LinkNone + * arg kEDMA_MinorLink + * arg kEDMA_MajorLink + * param linkedChannel The linked channel number. + * note Users should ensure that DONE flag is cleared before calling this interface, or the configuration is invalid. + */ void EDMA_SetChannelLink(DMA_Type *base, uint32_t channel, edma_channel_link_type_t type, uint32_t linkedChannel) { assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL); @@ -184,6 +275,20 @@ void EDMA_SetChannelLink(DMA_Type *base, uint32_t channel, edma_channel_link_typ EDMA_TcdSetChannelLink((edma_tcd_t *)&base->TCD[channel], type, linkedChannel); } +/*! + * brief Sets the bandwidth for the eDMA transfer. + * + * Because the eDMA processes the minor loop, it continuously generates read/write sequences + * until the minor count is exhausted. The bandwidth forces the eDMA to stall after the completion of + * each read/write access to control the bus request bandwidth seen by the crossbar switch. + * + * param base eDMA peripheral base address. + * param channel eDMA channel number. + * param bandWidth A bandwidth setting, which can be one of the following: + * arg kEDMABandwidthStallNone + * arg kEDMABandwidthStall4Cycle + * arg kEDMABandwidthStall8Cycle + */ void EDMA_SetBandWidth(DMA_Type *base, uint32_t channel, edma_bandwidth_t bandWidth) { assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL); @@ -191,6 +296,18 @@ void EDMA_SetBandWidth(DMA_Type *base, uint32_t channel, edma_bandwidth_t bandWi base->TCD[channel].CSR = (base->TCD[channel].CSR & (~DMA_CSR_BWC_MASK)) | DMA_CSR_BWC(bandWidth); } +/*! + * brief Sets the source modulo and the destination modulo for the eDMA transfer. + * + * This function defines a specific address range specified to be the value after (SADDR + SOFF)/(DADDR + DOFF) + * calculation is performed or the original register value. It provides the ability to implement a circular data + * queue easily. + * + * param base eDMA peripheral base address. + * param channel eDMA channel number. + * param srcModulo A source modulo value. + * param destModulo A destination modulo value. + */ void EDMA_SetModulo(DMA_Type *base, uint32_t channel, edma_modulo_t srcModulo, edma_modulo_t destModulo) { assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL); @@ -201,6 +318,14 @@ void EDMA_SetModulo(DMA_Type *base, uint32_t channel, edma_modulo_t srcModulo, e base->TCD[channel].ATTR = tmpreg | DMA_ATTR_DMOD(destModulo) | DMA_ATTR_SMOD(srcModulo); } +/*! + * brief Enables the interrupt source for the eDMA transfer. + * + * param base eDMA peripheral base address. + * param channel eDMA channel number. + * param mask The mask of interrupt source to be set. Users need to use + * the defined edma_interrupt_enable_t type. + */ void EDMA_EnableChannelInterrupts(DMA_Type *base, uint32_t channel, uint32_t mask) { assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL); @@ -224,6 +349,14 @@ void EDMA_EnableChannelInterrupts(DMA_Type *base, uint32_t channel, uint32_t mas } } +/*! + * brief Disables the interrupt source for the eDMA transfer. + * + * param base eDMA peripheral base address. + * param channel eDMA channel number. + * param mask The mask of the interrupt source to be set. Use + * the defined edma_interrupt_enable_t type. + */ void EDMA_DisableChannelInterrupts(DMA_Type *base, uint32_t channel, uint32_t mask) { assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL); @@ -247,6 +380,14 @@ void EDMA_DisableChannelInterrupts(DMA_Type *base, uint32_t channel, uint32_t ma } } +/*! + * brief Sets all fields to default values for the TCD structure. + * + * This function sets all fields for this TCD structure to default value. + * + * param tcd Pointer to the TCD structure. + * note This function enables the auto stop request feature. + */ void EDMA_TcdReset(edma_tcd_t *tcd) { assert(tcd != NULL); @@ -267,6 +408,33 @@ void EDMA_TcdReset(edma_tcd_t *tcd) tcd->BITER = 0U; } +/*! + * brief Configures the eDMA TCD transfer attribute. + * + * The TCD is a transfer control descriptor. The content of the TCD is the same as the hardware TCD registers. + * The STCD is used in the scatter-gather mode. + * This function configures the TCD transfer attribute, including source address, destination address, + * transfer size, address offset, and so on. It also configures the scatter gather feature if the + * user supplies the next TCD address. + * Example: + * code + * edma_transfer_t config = { + * ... + * } + * edma_tcd_t tcd __aligned(32); + * edma_tcd_t nextTcd __aligned(32); + * EDMA_TcdSetTransferConfig(&tcd, &config, &nextTcd); + * endcode + * + * param tcd Pointer to the TCD structure. + * param config Pointer to eDMA transfer configuration structure. + * param nextTcd Pointer to the next TCD structure. It can be NULL if users + * do not want to enable scatter/gather feature. + * note TCD address should be 32 bytes aligned or it causes an eDMA error. + * note If the nextTcd is not NULL, the scatter gather feature is enabled + * and DREQ bit is cleared in the previous transfer configuration, which + * is set in the EDMA_TcdReset. + */ void EDMA_TcdSetTransferConfig(edma_tcd_t *tcd, const edma_transfer_config_t *config, edma_tcd_t *nextTcd) { assert(tcd != NULL); @@ -307,6 +475,15 @@ void EDMA_TcdSetTransferConfig(edma_tcd_t *tcd, const edma_transfer_config_t *co } } +/*! + * brief Configures the eDMA TCD minor offset feature. + * + * A minor offset is a signed-extended value added to the source address or a destination + * address after each minor loop. + * + * param tcd A point to the TCD structure. + * param config A pointer to the minor offset configuration structure. + */ void EDMA_TcdSetMinorOffsetConfig(edma_tcd_t *tcd, const edma_minor_offset_config_t *config) { assert(tcd != NULL); @@ -322,6 +499,21 @@ void EDMA_TcdSetMinorOffsetConfig(edma_tcd_t *tcd, const edma_minor_offset_confi tcd->NBYTES = tmpreg; } +/*! + * brief Sets the channel link for the eDMA TCD. + * + * This function configures either a minor link or a major link. The minor link means the channel link is + * triggered every time CITER decreases by 1. The major link means that the channel link is triggered when the CITER is + * exhausted. + * + * note Users should ensure that DONE flag is cleared before calling this interface, or the configuration is invalid. + * param tcd Point to the TCD structure. + * param type Channel link type, it can be one of: + * arg kEDMA_LinkNone + * arg kEDMA_MinorLink + * arg kEDMA_MajorLink + * param linkedChannel The linked channel number. + */ void EDMA_TcdSetChannelLink(edma_tcd_t *tcd, edma_channel_link_type_t type, uint32_t linkedChannel) { assert(tcd != NULL); @@ -335,7 +527,7 @@ void EDMA_TcdSetChannelLink(edma_tcd_t *tcd, edma_channel_link_type_t type, uint /* Enable minor link */ tcd->CITER |= DMA_CITER_ELINKYES_ELINK_MASK; tcd->BITER |= DMA_BITER_ELINKYES_ELINK_MASK; - /* Set likned channel */ + /* Set linked channel */ tmpreg = tcd->CITER & (~DMA_CITER_ELINKYES_LINKCH_MASK); tmpreg |= DMA_CITER_ELINKYES_LINKCH(linkedChannel); tcd->CITER = tmpreg; @@ -361,6 +553,17 @@ void EDMA_TcdSetChannelLink(edma_tcd_t *tcd, edma_channel_link_type_t type, uint } } +/*! + * brief Sets the source modulo and the destination modulo for the eDMA TCD. + * + * This function defines a specific address range specified to be the value after (SADDR + SOFF)/(DADDR + DOFF) + * calculation is performed or the original register value. It provides the ability to implement a circular data + * queue easily. + * + * param tcd A pointer to the TCD structure. + * param srcModulo A source modulo value. + * param destModulo A destination modulo value. + */ void EDMA_TcdSetModulo(edma_tcd_t *tcd, edma_modulo_t srcModulo, edma_modulo_t destModulo) { assert(tcd != NULL); @@ -372,6 +575,13 @@ void EDMA_TcdSetModulo(edma_tcd_t *tcd, edma_modulo_t srcModulo, edma_modulo_t d tcd->ATTR = tmpreg | DMA_ATTR_DMOD(destModulo) | DMA_ATTR_SMOD(srcModulo); } +/*! + * brief Enables the interrupt source for the eDMA TCD. + * + * param tcd Point to the TCD structure. + * param mask The mask of interrupt source to be set. Users need to use + * the defined edma_interrupt_enable_t type. + */ void EDMA_TcdEnableInterrupts(edma_tcd_t *tcd, uint32_t mask) { assert(tcd != NULL); @@ -389,6 +599,13 @@ void EDMA_TcdEnableInterrupts(edma_tcd_t *tcd, uint32_t mask) } } +/*! + * brief Disables the interrupt source for the eDMA TCD. + * + * param tcd Point to the TCD structure. + * param mask The mask of interrupt source to be set. Users need to use + * the defined edma_interrupt_enable_t type. + */ void EDMA_TcdDisableInterrupts(edma_tcd_t *tcd, uint32_t mask) { assert(tcd != NULL); @@ -406,6 +623,27 @@ void EDMA_TcdDisableInterrupts(edma_tcd_t *tcd, uint32_t mask) } } +/*! + * brief Gets the remaining major loop count from the eDMA current channel TCD. + * + * This function checks the TCD (Task Control Descriptor) status for a specified + * eDMA channel and returns the number of major loop count that has not finished. + * + * param base eDMA peripheral base address. + * param channel eDMA channel number. + * return Major loop count which has not been transferred yet for the current TCD. + * note 1. This function can only be used to get unfinished major loop count of transfer without + * the next TCD, or it might be inaccuracy. + * 2. The unfinished/remaining transfer bytes cannot be obtained directly from registers while + * the channel is running. + * Because to calculate the remaining bytes, the initial NBYTES configured in DMA_TCDn_NBYTES_MLNO + * register is needed while the eDMA IP does not support getting it while a channel is active. + * In another word, the NBYTES value reading is always the actual (decrementing) NBYTES value the dma_engine + * is working with while a channel is running. + * Consequently, to get the remaining transfer bytes, a software-saved initial value of NBYTES (for example + * copied before enabling the channel) is needed. The formula to calculate it is shown below: + * RemainingBytes = RemainingMajorLoopCount * NBYTES(initially configured) + */ uint32_t EDMA_GetRemainingMajorLoopCount(DMA_Type *base, uint32_t channel) { assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL); @@ -434,6 +672,14 @@ uint32_t EDMA_GetRemainingMajorLoopCount(DMA_Type *base, uint32_t channel) return remainingCount; } +/*! + * brief Gets the eDMA channel status flags. + * + * param base eDMA peripheral base address. + * param channel eDMA channel number. + * return The mask of channel status flags. Users need to use the + * _edma_channel_status_flags type to decode the return variables. + */ uint32_t EDMA_GetChannelStatusFlags(DMA_Type *base, uint32_t channel) { assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL); @@ -450,6 +696,14 @@ uint32_t EDMA_GetChannelStatusFlags(DMA_Type *base, uint32_t channel) return retval; } +/*! + * brief Clears the eDMA channel status flags. + * + * param base eDMA peripheral base address. + * param channel eDMA channel number. + * param mask The mask of channel status to be cleared. Users need to use + * the defined _edma_channel_status_flags type. + */ void EDMA_ClearChannelStatusFlags(DMA_Type *base, uint32_t channel, uint32_t mask) { assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL); @@ -488,6 +742,17 @@ static uint8_t Get_StartInstance(void) return StartInstanceNum; } +/*! + * brief Creates the eDMA handle. + * + * This function is called if using the transactional API for eDMA. This function + * initializes the internal state of the eDMA handle. + * + * param handle eDMA handle pointer. The eDMA handle stores callback function and + * parameters. + * param base eDMA peripheral base address. + * param channel eDMA channel number. + */ void EDMA_CreateHandle(edma_handle_t *handle, DMA_Type *base, uint32_t channel) { assert(handle != NULL); @@ -531,12 +796,24 @@ void EDMA_CreateHandle(edma_handle_t *handle, DMA_Type *base, uint32_t channel) tcdRegs->BITER = 0; } +/*! + * brief Installs the TCDs memory pool into the eDMA handle. + * + * This function is called after the EDMA_CreateHandle to use scatter/gather feature. This function shall only be used + * while users need to use scatter gather mode. Scatter gather mode enables EDMA to load a new transfer control block + * (tcd) in hardware, and automatically reconfigure that DMA channel for a new transfer. + * Users need to prepare tcd memory and also configure tcds using interface EDMA_SubmitTransfer. + * + * param handle eDMA handle pointer. + * param tcdPool A memory pool to store TCDs. It must be 32 bytes aligned. + * param tcdSize The number of TCD slots. + */ void EDMA_InstallTCDMemory(edma_handle_t *handle, edma_tcd_t *tcdPool, uint32_t tcdSize) { assert(handle != NULL); assert(((uint32_t)tcdPool & 0x1FU) == 0); - /* Initialize tcd queue attibute. */ + /* Initialize tcd queue attribute. */ handle->header = 0; handle->tail = 0; handle->tcdUsed = 0; @@ -545,6 +822,16 @@ void EDMA_InstallTCDMemory(edma_handle_t *handle, edma_tcd_t *tcdPool, uint32_t handle->tcdPool = tcdPool; } +/*! + * brief Installs a callback function for the eDMA transfer. + * + * This callback is called in the eDMA IRQ handler. Use the callback to do something after + * the current major loop transfer completes. This function will be called every time one tcd finished transfer. + * + * param handle eDMA handle pointer. + * param callback eDMA callback function pointer. + * param userData A parameter for the callback function. + */ void EDMA_SetCallback(edma_handle_t *handle, edma_callback callback, void *userData) { assert(handle != NULL); @@ -553,6 +840,23 @@ void EDMA_SetCallback(edma_handle_t *handle, edma_callback callback, void *userD handle->userData = userData; } +/*! + * brief Prepares the eDMA transfer structure. + * + * This function prepares the transfer configuration structure according to the user input. + * + * param config The user configuration structure of type edma_transfer_t. + * param srcAddr eDMA transfer source address. + * param srcWidth eDMA transfer source address width(bytes). + * param destAddr eDMA transfer destination address. + * param destWidth eDMA transfer destination address width(bytes). + * param bytesEachRequest eDMA transfer bytes per channel request. + * param transferBytes eDMA transfer bytes to be transferred. + * param type eDMA transfer type. + * note The data address and the data width must be consistent. For example, if the SRC + * is 4 bytes, the source address must be 4 bytes aligned, or it results in + * source address error (SAE). + */ void EDMA_PrepareTransfer(edma_transfer_config_t *config, void *srcAddr, uint32_t srcWidth, @@ -569,6 +873,9 @@ void EDMA_PrepareTransfer(edma_transfer_config_t *config, assert((destWidth == 1U) || (destWidth == 2U) || (destWidth == 4U) || (destWidth == 16U) || (destWidth == 32U)); assert(transferBytes % bytesEachRequest == 0); + /* Initializes the configure structure to zero. */ + memset(config, 0, sizeof(*config)); + config->destAddr = (uint32_t)destAddr; config->srcAddr = (uint32_t)srcAddr; config->minorLoopBytes = bytesEachRequest; @@ -632,6 +939,19 @@ void EDMA_PrepareTransfer(edma_transfer_config_t *config, } } +/*! + * brief Submits the eDMA transfer request. + * + * This function submits the eDMA transfer request according to the transfer configuration structure. + * In scatter gather mode, call this function will add a configured tcd to the circular list of tcd pool. + * The tcd pools is setup by call function EDMA_InstallTCDMemory before. + * + * param handle eDMA handle pointer. + * param config Pointer to eDMA transfer configuration structure. + * retval kStatus_EDMA_Success It means submit transfer request succeed. + * retval kStatus_EDMA_QueueFull It means TCD queue is full. Submit transfer request is not allowed. + * retval kStatus_EDMA_Busy It means the given channel is busy, need to submit request later. + */ status_t EDMA_SubmitTransfer(edma_handle_t *handle, const edma_transfer_config_t *config) { assert(handle != NULL); @@ -704,15 +1024,17 @@ status_t EDMA_SubmitTransfer(edma_handle_t *handle, const edma_transfer_config_t csr = (handle->tcdPool[previousTcd].CSR | DMA_CSR_ESG_MASK) & ~DMA_CSR_DREQ_MASK; handle->tcdPool[previousTcd].CSR = csr; /* - Check if the TCD blcok in the registers is the previous one (points to current TCD block). It + Check if the TCD block in the registers is the previous one (points to current TCD block). It is used to check if the previous TCD linked has been loaded in TCD register. If so, it need to link the TCD register in case link the current TCD with the dead chain when TCD loading occurs before link the previous TCD block. */ if (tcdRegs->DLAST_SGA == (uint32_t)&handle->tcdPool[currentTcd]) { + /* Clear the DREQ bits for the dynamic scatter gather */ + tcdRegs->CSR |= DMA_CSR_DREQ_MASK; /* Enable scatter/gather also in the TCD registers. */ - csr = (tcdRegs->CSR | DMA_CSR_ESG_MASK) & ~DMA_CSR_DREQ_MASK; + csr = tcdRegs->CSR | DMA_CSR_ESG_MASK; /* Must write the CSR register one-time, because the transfer maybe finished anytime. */ tcdRegs->CSR = csr; /* @@ -722,11 +1044,12 @@ status_t EDMA_SubmitTransfer(edma_handle_t *handle, const edma_transfer_config_t and the DLAST_SGA is not the next TCD address(it means the dynamic TCD link succeed and the current TCD block has been loaded into TCD registers), it means transfer finished and TCD link operation fail, so must install TCD content into TCD registers and enable - transfer again. And if ESG is set, it means transfer has notfinished, so TCD dynamic + transfer again. And if ESG is set, it means transfer has not finished, so TCD dynamic link succeed. */ if (tcdRegs->CSR & DMA_CSR_ESG_MASK) { + tcdRegs->CSR &= ~DMA_CSR_DREQ_MASK; return kStatus_Success; } /* @@ -768,6 +1091,14 @@ status_t EDMA_SubmitTransfer(edma_handle_t *handle, const edma_transfer_config_t } } +/*! + * brief eDMA starts transfer. + * + * This function enables the channel request. Users can call this function after submitting the transfer request + * or before submitting the transfer request. + * + * param handle eDMA handle pointer. + */ void EDMA_StartTransfer(edma_handle_t *handle) { assert(handle != NULL); @@ -805,6 +1136,14 @@ void EDMA_StartTransfer(edma_handle_t *handle) } } +/*! + * brief eDMA stops transfer. + * + * This function disables the channel request to pause the transfer. Users can call EDMA_StartTransfer() + * again to resume the transfer. + * + * param handle eDMA handle pointer. + */ void EDMA_StopTransfer(edma_handle_t *handle) { assert(handle != NULL); @@ -813,6 +1152,14 @@ void EDMA_StopTransfer(edma_handle_t *handle) handle->base->CERQ = DMA_CERQ_CERQ(handle->channel); } +/*! + * brief eDMA aborts transfer. + * + * This function disables the channel request and clear transfer status bits. + * Users can submit another transfer after calling this API. + * + * param handle DMA handle pointer. + */ void EDMA_AbortTransfer(edma_handle_t *handle) { handle->base->CERQ = DMA_CERQ_CERQ(handle->channel); @@ -834,6 +1181,34 @@ void EDMA_AbortTransfer(edma_handle_t *handle) } } +/*! + * brief eDMA IRQ handler for the current major loop transfer completion. + * + * This function clears the channel major interrupt flag and calls + * the callback function if it is not NULL. + * + * Note: + * For the case using TCD queue, when the major iteration count is exhausted, additional operations are performed. + * These include the final address adjustments and reloading of the BITER field into the CITER. + * Assertion of an optional interrupt request also occurs at this time, as does a possible fetch of a new TCD from + * memory using the scatter/gather address pointer included in the descriptor (if scatter/gather is enabled). + * + * For instance, when the time interrupt of TCD[0] happens, the TCD[1] has already been loaded into the eDMA engine. + * As sga and sga_index are calculated based on the DLAST_SGA bitfield lies in the TCD_CSR register, the sga_index + * in this case should be 2 (DLAST_SGA of TCD[1] stores the address of TCD[2]). Thus, the "tcdUsed" updated should be + * (tcdUsed - 2U) which indicates the number of TCDs can be loaded in the memory pool (because TCD[0] and TCD[1] have + * been loaded into the eDMA engine at this point already.). + * + * For the last two continuous ISRs in a scatter/gather process, they both load the last TCD (The last ISR does not + * load a new TCD) from the memory pool to the eDMA engine when major loop completes. + * Therefore, ensure that the header and tcdUsed updated are identical for them. + * tcdUsed are both 0 in this case as no TCD to be loaded. + * + * See the "eDMA basic data flow" in the eDMA Functional description section of the Reference Manual for + * further details. + * + * param handle eDMA handle pointer. + */ void EDMA_HandleIRQ(edma_handle_t *handle) { assert(handle != NULL); @@ -854,9 +1229,9 @@ void EDMA_HandleIRQ(edma_handle_t *handle) /* Check if transfer is already finished. */ transfer_done = ((handle->base->TCD[handle->channel].CSR & DMA_CSR_DONE_MASK) != 0); - /* Get the offset of the next transfer TCD blcoks to be loaded into the eDMA engine. */ + /* Get the offset of the next transfer TCD blocks to be loaded into the eDMA engine. */ sga -= (uint32_t)handle->tcdPool; - /* Get the index of the next transfer TCD blcoks to be loaded into the eDMA engine. */ + /* Get the index of the next transfer TCD blocks to be loaded into the eDMA engine. */ sga_index = sga / sizeof(edma_tcd_t); /* Adjust header positions. */ if (transfer_done) @@ -899,6 +1274,19 @@ void EDMA_HandleIRQ(edma_handle_t *handle) { (handle->callback)(handle, handle->userData, transfer_done, tcds_done); } + + /* clear the DONE bit here is meaningful for below cases: + *1.A new TCD has been loaded to EDMA already: + * need to clear the DONE bit in the IRQ handler to avoid TCD in EDMA been overwritten + * if peripheral request isn't coming before next transfer request. + *2.A new TCD has not been loaded to EDMA: + * for the case that transfer request occur in the privious edma callback, this is a case that doesn't + * need scatter gather, so keep DONE bit during the next transfer request will re-install the TCD. + */ + if (transfer_done) + { + handle->base->CDNE = handle->channel; + } } } @@ -916,8 +1304,8 @@ void DMA0_04_DriverIRQHandler(void) { EDMA_HandleIRQ(s_EDMAHandle[4]); } - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ #if defined __CORTEX_M && (__CORTEX_M == 4U) __DSB(); #endif @@ -933,8 +1321,8 @@ void DMA0_15_DriverIRQHandler(void) { EDMA_HandleIRQ(s_EDMAHandle[5]); } - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ #if defined __CORTEX_M && (__CORTEX_M == 4U) __DSB(); #endif @@ -950,8 +1338,8 @@ void DMA0_26_DriverIRQHandler(void) { EDMA_HandleIRQ(s_EDMAHandle[6]); } - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ #if defined __CORTEX_M && (__CORTEX_M == 4U) __DSB(); #endif @@ -967,8 +1355,8 @@ void DMA0_37_DriverIRQHandler(void) { EDMA_HandleIRQ(s_EDMAHandle[7]); } - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ #if defined __CORTEX_M && (__CORTEX_M == 4U) __DSB(); #endif @@ -988,8 +1376,8 @@ void DMA1_04_DriverIRQHandler(void) { EDMA_HandleIRQ(s_EDMAHandle[12]); } - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ #if defined __CORTEX_M && (__CORTEX_M == 4U) __DSB(); #endif @@ -1005,8 +1393,8 @@ void DMA1_15_DriverIRQHandler(void) { EDMA_HandleIRQ(s_EDMAHandle[13]); } - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ #if defined __CORTEX_M && (__CORTEX_M == 4U) __DSB(); #endif @@ -1022,8 +1410,8 @@ void DMA1_26_DriverIRQHandler(void) { EDMA_HandleIRQ(s_EDMAHandle[14]); } - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ #if defined __CORTEX_M && (__CORTEX_M == 4U) __DSB(); #endif @@ -1039,8 +1427,8 @@ void DMA1_37_DriverIRQHandler(void) { EDMA_HandleIRQ(s_EDMAHandle[15]); } - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ #if defined __CORTEX_M && (__CORTEX_M == 4U) __DSB(); #endif @@ -1057,8 +1445,8 @@ void DMA1_04_DriverIRQHandler(void) { EDMA_HandleIRQ(s_EDMAHandle[4]); } - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ #if defined __CORTEX_M && (__CORTEX_M == 4U) __DSB(); #endif @@ -1074,8 +1462,8 @@ void DMA1_15_DriverIRQHandler(void) { EDMA_HandleIRQ(s_EDMAHandle[5]); } - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ #if defined __CORTEX_M && (__CORTEX_M == 4U) __DSB(); #endif @@ -1091,8 +1479,8 @@ void DMA1_26_DriverIRQHandler(void) { EDMA_HandleIRQ(s_EDMAHandle[6]); } - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ #if defined __CORTEX_M && (__CORTEX_M == 4U) __DSB(); #endif @@ -1108,8 +1496,8 @@ void DMA1_37_DriverIRQHandler(void) { EDMA_HandleIRQ(s_EDMAHandle[7]); } - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ #if defined __CORTEX_M && (__CORTEX_M == 4U) __DSB(); #endif @@ -1131,8 +1519,8 @@ void DMA0_08_DriverIRQHandler(void) { EDMA_HandleIRQ(s_EDMAHandle[8]); } - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ #if defined __CORTEX_M && (__CORTEX_M == 4U) __DSB(); #endif @@ -1148,8 +1536,8 @@ void DMA0_19_DriverIRQHandler(void) { EDMA_HandleIRQ(s_EDMAHandle[9]); } - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ #if defined __CORTEX_M && (__CORTEX_M == 4U) __DSB(); #endif @@ -1165,8 +1553,8 @@ void DMA0_210_DriverIRQHandler(void) { EDMA_HandleIRQ(s_EDMAHandle[10]); } - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ #if defined __CORTEX_M && (__CORTEX_M == 4U) __DSB(); #endif @@ -1182,8 +1570,8 @@ void DMA0_311_DriverIRQHandler(void) { EDMA_HandleIRQ(s_EDMAHandle[11]); } - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ #if defined __CORTEX_M && (__CORTEX_M == 4U) __DSB(); #endif @@ -1199,8 +1587,8 @@ void DMA0_412_DriverIRQHandler(void) { EDMA_HandleIRQ(s_EDMAHandle[12]); } - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ #if defined __CORTEX_M && (__CORTEX_M == 4U) __DSB(); #endif @@ -1216,8 +1604,8 @@ void DMA0_513_DriverIRQHandler(void) { EDMA_HandleIRQ(s_EDMAHandle[13]); } - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ #if defined __CORTEX_M && (__CORTEX_M == 4U) __DSB(); #endif @@ -1233,8 +1621,8 @@ void DMA0_614_DriverIRQHandler(void) { EDMA_HandleIRQ(s_EDMAHandle[14]); } - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ #if defined __CORTEX_M && (__CORTEX_M == 4U) __DSB(); #endif @@ -1250,8 +1638,8 @@ void DMA0_715_DriverIRQHandler(void) { EDMA_HandleIRQ(s_EDMAHandle[15]); } - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ #if defined __CORTEX_M && (__CORTEX_M == 4U) __DSB(); #endif @@ -1268,8 +1656,8 @@ void DMA1_08_DriverIRQHandler(void) { EDMA_HandleIRQ(s_EDMAHandle[24]); } - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ #if defined __CORTEX_M && (__CORTEX_M == 4U) __DSB(); #endif @@ -1285,8 +1673,8 @@ void DMA1_19_DriverIRQHandler(void) { EDMA_HandleIRQ(s_EDMAHandle[25]); } - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ #if defined __CORTEX_M && (__CORTEX_M == 4U) __DSB(); #endif @@ -1302,8 +1690,8 @@ void DMA1_210_DriverIRQHandler(void) { EDMA_HandleIRQ(s_EDMAHandle[26]); } - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ #if defined __CORTEX_M && (__CORTEX_M == 4U) __DSB(); #endif @@ -1319,8 +1707,8 @@ void DMA1_311_DriverIRQHandler(void) { EDMA_HandleIRQ(s_EDMAHandle[27]); } - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ #if defined __CORTEX_M && (__CORTEX_M == 4U) __DSB(); #endif @@ -1336,8 +1724,8 @@ void DMA1_412_DriverIRQHandler(void) { EDMA_HandleIRQ(s_EDMAHandle[28]); } - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ #if defined __CORTEX_M && (__CORTEX_M == 4U) __DSB(); #endif @@ -1353,8 +1741,8 @@ void DMA1_513_DriverIRQHandler(void) { EDMA_HandleIRQ(s_EDMAHandle[29]); } - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ #if defined __CORTEX_M && (__CORTEX_M == 4U) __DSB(); #endif @@ -1370,8 +1758,8 @@ void DMA1_614_DriverIRQHandler(void) { EDMA_HandleIRQ(s_EDMAHandle[30]); } - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ #if defined __CORTEX_M && (__CORTEX_M == 4U) __DSB(); #endif @@ -1387,8 +1775,8 @@ void DMA1_715_DriverIRQHandler(void) { EDMA_HandleIRQ(s_EDMAHandle[31]); } - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ #if defined __CORTEX_M && (__CORTEX_M == 4U) __DSB(); #endif @@ -1409,8 +1797,8 @@ void DMA0_DMA16_DriverIRQHandler(void) { EDMA_HandleIRQ(s_EDMAHandle[16]); } - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ #if defined __CORTEX_M && (__CORTEX_M == 4U) __DSB(); #endif @@ -1426,8 +1814,8 @@ void DMA1_DMA17_DriverIRQHandler(void) { EDMA_HandleIRQ(s_EDMAHandle[17]); } - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ #if defined __CORTEX_M && (__CORTEX_M == 4U) __DSB(); #endif @@ -1443,8 +1831,8 @@ void DMA2_DMA18_DriverIRQHandler(void) { EDMA_HandleIRQ(s_EDMAHandle[18]); } - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ #if defined __CORTEX_M && (__CORTEX_M == 4U) __DSB(); #endif @@ -1460,8 +1848,8 @@ void DMA3_DMA19_DriverIRQHandler(void) { EDMA_HandleIRQ(s_EDMAHandle[19]); } - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ #if defined __CORTEX_M && (__CORTEX_M == 4U) __DSB(); #endif @@ -1477,8 +1865,8 @@ void DMA4_DMA20_DriverIRQHandler(void) { EDMA_HandleIRQ(s_EDMAHandle[20]); } - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ #if defined __CORTEX_M && (__CORTEX_M == 4U) __DSB(); #endif @@ -1494,8 +1882,8 @@ void DMA5_DMA21_DriverIRQHandler(void) { EDMA_HandleIRQ(s_EDMAHandle[21]); } - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ #if defined __CORTEX_M && (__CORTEX_M == 4U) __DSB(); #endif @@ -1511,8 +1899,8 @@ void DMA6_DMA22_DriverIRQHandler(void) { EDMA_HandleIRQ(s_EDMAHandle[22]); } - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ #if defined __CORTEX_M && (__CORTEX_M == 4U) __DSB(); #endif @@ -1528,8 +1916,8 @@ void DMA7_DMA23_DriverIRQHandler(void) { EDMA_HandleIRQ(s_EDMAHandle[23]); } - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ #if defined __CORTEX_M && (__CORTEX_M == 4U) __DSB(); #endif @@ -1545,8 +1933,8 @@ void DMA8_DMA24_DriverIRQHandler(void) { EDMA_HandleIRQ(s_EDMAHandle[24]); } - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ #if defined __CORTEX_M && (__CORTEX_M == 4U) __DSB(); #endif @@ -1562,8 +1950,8 @@ void DMA9_DMA25_DriverIRQHandler(void) { EDMA_HandleIRQ(s_EDMAHandle[25]); } - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ #if defined __CORTEX_M && (__CORTEX_M == 4U) __DSB(); #endif @@ -1579,8 +1967,8 @@ void DMA10_DMA26_DriverIRQHandler(void) { EDMA_HandleIRQ(s_EDMAHandle[26]); } - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ #if defined __CORTEX_M && (__CORTEX_M == 4U) __DSB(); #endif @@ -1596,8 +1984,8 @@ void DMA11_DMA27_DriverIRQHandler(void) { EDMA_HandleIRQ(s_EDMAHandle[27]); } - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ #if defined __CORTEX_M && (__CORTEX_M == 4U) __DSB(); #endif @@ -1613,8 +2001,8 @@ void DMA12_DMA28_DriverIRQHandler(void) { EDMA_HandleIRQ(s_EDMAHandle[28]); } - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ #if defined __CORTEX_M && (__CORTEX_M == 4U) __DSB(); #endif @@ -1630,8 +2018,8 @@ void DMA13_DMA29_DriverIRQHandler(void) { EDMA_HandleIRQ(s_EDMAHandle[29]); } - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ #if defined __CORTEX_M && (__CORTEX_M == 4U) __DSB(); #endif @@ -1647,8 +2035,8 @@ void DMA14_DMA30_DriverIRQHandler(void) { EDMA_HandleIRQ(s_EDMAHandle[30]); } - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ #if defined __CORTEX_M && (__CORTEX_M == 4U) __DSB(); #endif @@ -1664,8 +2052,8 @@ void DMA15_DMA31_DriverIRQHandler(void) { EDMA_HandleIRQ(s_EDMAHandle[31]); } - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ #if defined __CORTEX_M && (__CORTEX_M == 4U) __DSB(); #endif @@ -1685,8 +2073,8 @@ void DMA0_0_4_DriverIRQHandler(void) { EDMA_HandleIRQ(s_EDMAHandle[4]); } - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ #if defined __CORTEX_M && (__CORTEX_M == 4U) __DSB(); #endif @@ -1702,8 +2090,8 @@ void DMA0_1_5_DriverIRQHandler(void) { EDMA_HandleIRQ(s_EDMAHandle[5]); } - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ #if defined __CORTEX_M && (__CORTEX_M == 4U) __DSB(); #endif @@ -1719,8 +2107,8 @@ void DMA0_2_6_DriverIRQHandler(void) { EDMA_HandleIRQ(s_EDMAHandle[6]); } - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ #if defined __CORTEX_M && (__CORTEX_M == 4U) __DSB(); #endif @@ -1736,8 +2124,8 @@ void DMA0_3_7_DriverIRQHandler(void) { EDMA_HandleIRQ(s_EDMAHandle[7]); } - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ #if defined __CORTEX_M && (__CORTEX_M == 4U) __DSB(); #endif @@ -1753,8 +2141,8 @@ void DMA0_8_12_DriverIRQHandler(void) { EDMA_HandleIRQ(s_EDMAHandle[12]); } - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ #if defined __CORTEX_M && (__CORTEX_M == 4U) __DSB(); #endif @@ -1770,8 +2158,8 @@ void DMA0_9_13_DriverIRQHandler(void) { EDMA_HandleIRQ(s_EDMAHandle[13]); } - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ #if defined __CORTEX_M && (__CORTEX_M == 4U) __DSB(); #endif @@ -1787,8 +2175,8 @@ void DMA0_10_14_DriverIRQHandler(void) { EDMA_HandleIRQ(s_EDMAHandle[14]); } - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ #if defined __CORTEX_M && (__CORTEX_M == 4U) __DSB(); #endif @@ -1804,8 +2192,8 @@ void DMA0_11_15_DriverIRQHandler(void) { EDMA_HandleIRQ(s_EDMAHandle[15]); } - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ #if defined __CORTEX_M && (__CORTEX_M == 4U) __DSB(); #endif @@ -1821,8 +2209,8 @@ void DMA0_16_20_DriverIRQHandler(void) { EDMA_HandleIRQ(s_EDMAHandle[20]); } - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ #if defined __CORTEX_M && (__CORTEX_M == 4U) __DSB(); #endif @@ -1838,8 +2226,8 @@ void DMA0_17_21_DriverIRQHandler(void) { EDMA_HandleIRQ(s_EDMAHandle[21]); } - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ #if defined __CORTEX_M && (__CORTEX_M == 4U) __DSB(); #endif @@ -1855,8 +2243,8 @@ void DMA0_18_22_DriverIRQHandler(void) { EDMA_HandleIRQ(s_EDMAHandle[22]); } - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ #if defined __CORTEX_M && (__CORTEX_M == 4U) __DSB(); #endif @@ -1872,8 +2260,8 @@ void DMA0_19_23_DriverIRQHandler(void) { EDMA_HandleIRQ(s_EDMAHandle[23]); } - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ #if defined __CORTEX_M && (__CORTEX_M == 4U) __DSB(); #endif @@ -1889,8 +2277,8 @@ void DMA0_24_28_DriverIRQHandler(void) { EDMA_HandleIRQ(s_EDMAHandle[28]); } - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ #if defined __CORTEX_M && (__CORTEX_M == 4U) __DSB(); #endif @@ -1906,8 +2294,8 @@ void DMA0_25_29_DriverIRQHandler(void) { EDMA_HandleIRQ(s_EDMAHandle[29]); } - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ #if defined __CORTEX_M && (__CORTEX_M == 4U) __DSB(); #endif @@ -1923,8 +2311,8 @@ void DMA0_26_30_DriverIRQHandler(void) { EDMA_HandleIRQ(s_EDMAHandle[30]); } - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ #if defined __CORTEX_M && (__CORTEX_M == 4U) __DSB(); #endif @@ -1940,8 +2328,8 @@ void DMA0_27_31_DriverIRQHandler(void) { EDMA_HandleIRQ(s_EDMAHandle[31]); } - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ #if defined __CORTEX_M && (__CORTEX_M == 4U) __DSB(); #endif @@ -1954,8 +2342,8 @@ void DMA0_27_31_DriverIRQHandler(void) void DMA0_DriverIRQHandler(void) { EDMA_HandleIRQ(s_EDMAHandle[0]); - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ #if defined __CORTEX_M && (__CORTEX_M == 4U) __DSB(); #endif @@ -1964,8 +2352,8 @@ void DMA0_DriverIRQHandler(void) void DMA1_DriverIRQHandler(void) { EDMA_HandleIRQ(s_EDMAHandle[1]); - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ #if defined __CORTEX_M && (__CORTEX_M == 4U) __DSB(); #endif @@ -1974,8 +2362,8 @@ void DMA1_DriverIRQHandler(void) void DMA2_DriverIRQHandler(void) { EDMA_HandleIRQ(s_EDMAHandle[2]); - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ #if defined __CORTEX_M && (__CORTEX_M == 4U) __DSB(); #endif @@ -1984,8 +2372,8 @@ void DMA2_DriverIRQHandler(void) void DMA3_DriverIRQHandler(void) { EDMA_HandleIRQ(s_EDMAHandle[3]); - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ #if defined __CORTEX_M && (__CORTEX_M == 4U) __DSB(); #endif @@ -1997,8 +2385,8 @@ void DMA3_DriverIRQHandler(void) void DMA4_DriverIRQHandler(void) { EDMA_HandleIRQ(s_EDMAHandle[4]); - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ #if defined __CORTEX_M && (__CORTEX_M == 4U) __DSB(); #endif @@ -2007,8 +2395,8 @@ void DMA4_DriverIRQHandler(void) void DMA5_DriverIRQHandler(void) { EDMA_HandleIRQ(s_EDMAHandle[5]); - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ #if defined __CORTEX_M && (__CORTEX_M == 4U) __DSB(); #endif @@ -2017,8 +2405,8 @@ void DMA5_DriverIRQHandler(void) void DMA6_DriverIRQHandler(void) { EDMA_HandleIRQ(s_EDMAHandle[6]); - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ #if defined __CORTEX_M && (__CORTEX_M == 4U) __DSB(); #endif @@ -2027,8 +2415,8 @@ void DMA6_DriverIRQHandler(void) void DMA7_DriverIRQHandler(void) { EDMA_HandleIRQ(s_EDMAHandle[7]); - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ #if defined __CORTEX_M && (__CORTEX_M == 4U) __DSB(); #endif @@ -2041,8 +2429,8 @@ void DMA7_DriverIRQHandler(void) void DMA8_DriverIRQHandler(void) { EDMA_HandleIRQ(s_EDMAHandle[8]); - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ #if defined __CORTEX_M && (__CORTEX_M == 4U) __DSB(); #endif @@ -2051,8 +2439,8 @@ void DMA8_DriverIRQHandler(void) void DMA9_DriverIRQHandler(void) { EDMA_HandleIRQ(s_EDMAHandle[9]); - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ #if defined __CORTEX_M && (__CORTEX_M == 4U) __DSB(); #endif @@ -2061,8 +2449,8 @@ void DMA9_DriverIRQHandler(void) void DMA10_DriverIRQHandler(void) { EDMA_HandleIRQ(s_EDMAHandle[10]); - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ #if defined __CORTEX_M && (__CORTEX_M == 4U) __DSB(); #endif @@ -2071,8 +2459,8 @@ void DMA10_DriverIRQHandler(void) void DMA11_DriverIRQHandler(void) { EDMA_HandleIRQ(s_EDMAHandle[11]); - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ #if defined __CORTEX_M && (__CORTEX_M == 4U) __DSB(); #endif @@ -2081,8 +2469,8 @@ void DMA11_DriverIRQHandler(void) void DMA12_DriverIRQHandler(void) { EDMA_HandleIRQ(s_EDMAHandle[12]); - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ #if defined __CORTEX_M && (__CORTEX_M == 4U) __DSB(); #endif @@ -2091,8 +2479,8 @@ void DMA12_DriverIRQHandler(void) void DMA13_DriverIRQHandler(void) { EDMA_HandleIRQ(s_EDMAHandle[13]); - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ #if defined __CORTEX_M && (__CORTEX_M == 4U) __DSB(); #endif @@ -2101,8 +2489,8 @@ void DMA13_DriverIRQHandler(void) void DMA14_DriverIRQHandler(void) { EDMA_HandleIRQ(s_EDMAHandle[14]); - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ #if defined __CORTEX_M && (__CORTEX_M == 4U) __DSB(); #endif @@ -2111,8 +2499,8 @@ void DMA14_DriverIRQHandler(void) void DMA15_DriverIRQHandler(void) { EDMA_HandleIRQ(s_EDMAHandle[15]); - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ #if defined __CORTEX_M && (__CORTEX_M == 4U) __DSB(); #endif @@ -2125,8 +2513,8 @@ void DMA15_DriverIRQHandler(void) void DMA16_DriverIRQHandler(void) { EDMA_HandleIRQ(s_EDMAHandle[16]); - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ #if defined __CORTEX_M && (__CORTEX_M == 4U) __DSB(); #endif @@ -2135,8 +2523,8 @@ void DMA16_DriverIRQHandler(void) void DMA17_DriverIRQHandler(void) { EDMA_HandleIRQ(s_EDMAHandle[17]); - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ #if defined __CORTEX_M && (__CORTEX_M == 4U) __DSB(); #endif @@ -2145,8 +2533,8 @@ void DMA17_DriverIRQHandler(void) void DMA18_DriverIRQHandler(void) { EDMA_HandleIRQ(s_EDMAHandle[18]); - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ #if defined __CORTEX_M && (__CORTEX_M == 4U) __DSB(); #endif @@ -2155,8 +2543,8 @@ void DMA18_DriverIRQHandler(void) void DMA19_DriverIRQHandler(void) { EDMA_HandleIRQ(s_EDMAHandle[19]); - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ #if defined __CORTEX_M && (__CORTEX_M == 4U) __DSB(); #endif @@ -2165,8 +2553,8 @@ void DMA19_DriverIRQHandler(void) void DMA20_DriverIRQHandler(void) { EDMA_HandleIRQ(s_EDMAHandle[20]); - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ #if defined __CORTEX_M && (__CORTEX_M == 4U) __DSB(); #endif @@ -2175,8 +2563,8 @@ void DMA20_DriverIRQHandler(void) void DMA21_DriverIRQHandler(void) { EDMA_HandleIRQ(s_EDMAHandle[21]); - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ #if defined __CORTEX_M && (__CORTEX_M == 4U) __DSB(); #endif @@ -2185,8 +2573,8 @@ void DMA21_DriverIRQHandler(void) void DMA22_DriverIRQHandler(void) { EDMA_HandleIRQ(s_EDMAHandle[22]); - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ #if defined __CORTEX_M && (__CORTEX_M == 4U) __DSB(); #endif @@ -2195,8 +2583,8 @@ void DMA22_DriverIRQHandler(void) void DMA23_DriverIRQHandler(void) { EDMA_HandleIRQ(s_EDMAHandle[23]); - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ #if defined __CORTEX_M && (__CORTEX_M == 4U) __DSB(); #endif @@ -2205,8 +2593,8 @@ void DMA23_DriverIRQHandler(void) void DMA24_DriverIRQHandler(void) { EDMA_HandleIRQ(s_EDMAHandle[24]); - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ #if defined __CORTEX_M && (__CORTEX_M == 4U) __DSB(); #endif @@ -2215,8 +2603,8 @@ void DMA24_DriverIRQHandler(void) void DMA25_DriverIRQHandler(void) { EDMA_HandleIRQ(s_EDMAHandle[25]); - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ #if defined __CORTEX_M && (__CORTEX_M == 4U) __DSB(); #endif @@ -2225,8 +2613,8 @@ void DMA25_DriverIRQHandler(void) void DMA26_DriverIRQHandler(void) { EDMA_HandleIRQ(s_EDMAHandle[26]); - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ #if defined __CORTEX_M && (__CORTEX_M == 4U) __DSB(); #endif @@ -2235,8 +2623,8 @@ void DMA26_DriverIRQHandler(void) void DMA27_DriverIRQHandler(void) { EDMA_HandleIRQ(s_EDMAHandle[27]); - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ #if defined __CORTEX_M && (__CORTEX_M == 4U) __DSB(); #endif @@ -2245,8 +2633,8 @@ void DMA27_DriverIRQHandler(void) void DMA28_DriverIRQHandler(void) { EDMA_HandleIRQ(s_EDMAHandle[28]); - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ #if defined __CORTEX_M && (__CORTEX_M == 4U) __DSB(); #endif @@ -2255,8 +2643,8 @@ void DMA28_DriverIRQHandler(void) void DMA29_DriverIRQHandler(void) { EDMA_HandleIRQ(s_EDMAHandle[29]); - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ #if defined __CORTEX_M && (__CORTEX_M == 4U) __DSB(); #endif @@ -2265,8 +2653,8 @@ void DMA29_DriverIRQHandler(void) void DMA30_DriverIRQHandler(void) { EDMA_HandleIRQ(s_EDMAHandle[30]); - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ #if defined __CORTEX_M && (__CORTEX_M == 4U) __DSB(); #endif @@ -2275,8 +2663,8 @@ void DMA30_DriverIRQHandler(void) void DMA31_DriverIRQHandler(void) { EDMA_HandleIRQ(s_EDMAHandle[31]); - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ #if defined __CORTEX_M && (__CORTEX_M == 4U) __DSB(); #endif diff --git a/ext/hal/nxp/mcux/drivers/kinetis/fsl_edma.h b/ext/hal/nxp/mcux/drivers/kinetis/fsl_edma.h index e3564762035..802f1303598 100644 --- a/ext/hal/nxp/mcux/drivers/kinetis/fsl_edma.h +++ b/ext/hal/nxp/mcux/drivers/kinetis/fsl_edma.h @@ -1,31 +1,9 @@ /* * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP + * Copyright 2016-2018 NXP + * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * SPDX-License-Identifier: BSD-3-Clause */ #ifndef _FSL_EDMA_H_ @@ -45,14 +23,14 @@ /*! @name Driver version */ /*@{*/ /*! @brief eDMA driver version */ -#define FSL_EDMA_DRIVER_VERSION (MAKE_VERSION(2, 1, 2)) /*!< Version 2.1.2. */ +#define FSL_EDMA_DRIVER_VERSION (MAKE_VERSION(2, 1, 4)) /*!< Version 2.1.4. */ /*@}*/ /*! @brief Compute the offset unit from DCHPRI3 */ #define DMA_DCHPRI_INDEX(channel) (((channel) & ~0x03U) | (3 - ((channel)&0x03U))) /*! @brief Get the pointer of DCHPRIn */ -#define DMA_DCHPRIn(base, channel) ((volatile uint8_t *)&(base->DCHPRI3))[DMA_DCHPRI_INDEX(channel)] +#define DMA_DCHPRIn(base, channel) ((volatile uint8_t *)&((base)->DCHPRI3))[DMA_DCHPRI_INDEX(channel)] /*! @brief eDMA transfer configuration */ typedef enum _edma_transfer_size @@ -60,6 +38,7 @@ typedef enum _edma_transfer_size kEDMA_TransferSize1Bytes = 0x0U, /*!< Source/Destination data transfer size is 1 byte every time */ kEDMA_TransferSize2Bytes = 0x1U, /*!< Source/Destination data transfer size is 2 bytes every time */ kEDMA_TransferSize4Bytes = 0x2U, /*!< Source/Destination data transfer size is 4 bytes every time */ + kEDMA_TransferSize8Bytes = 0x3U, /*!< Source/Destination data transfer size is 8 bytes every time */ kEDMA_TransferSize16Bytes = 0x4U, /*!< Source/Destination data transfer size is 16 bytes every time */ kEDMA_TransferSize32Bytes = 0x5U, /*!< Source/Destination data transfer size is 32 bytes every time */ } edma_transfer_size_t; @@ -142,7 +121,7 @@ enum _edma_error_status_flags #if defined(FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT) && FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT > 1 kEDMA_GroupPriorityErrorFlag = DMA_ES_GPE_MASK, /*!< Group priority is not unique. */ #endif - kEDMA_ValidFlag = DMA_ES_VLD_MASK, /*!< No error occurred, this bit is 0. Otherwise, it is 1. */ + kEDMA_ValidFlag = (int)DMA_ES_VLD_MASK, /*!< No error occurred, this bit is 0. Otherwise, it is 1. */ }; /*! @brief eDMA interrupt source */ @@ -234,7 +213,7 @@ typedef struct _edma_tcd __IO uint32_t DADDR; /*!< DADDR register, used for destination address */ __IO uint16_t DOFF; /*!< DOFF register, used for destination offset */ __IO uint16_t CITER; /*!< CITER register, current minor loop numbers, for unfinished minor loop.*/ - __IO uint32_t DLAST_SGA; /*!< DLASTSGA register, next stcd address used in scatter-gather mode */ + __IO uint32_t DLAST_SGA; /*!< DLASTSGA register, next tcd address used in scatter-gather mode */ __IO uint16_t CSR; /*!< CSR register, for TCD control status */ __IO uint16_t BITER; /*!< BITER register, begin minor loop count. */ } edma_tcd_t; @@ -242,7 +221,24 @@ typedef struct _edma_tcd /*! @brief Callback for eDMA */ struct _edma_handle; -/*! @brief Define callback function for eDMA. */ +/*! @brief Define callback function for eDMA. + * + * This callback function is called in the EDMA interrupt handle. + * In normal mode, run into callback function means the transfer users need is done. + * In scatter gather mode, run into callback function means a transfer control block (tcd) is finished. Not + * all transfer finished, users can get the finished tcd numbers using interface EDMA_GetUnusedTCDNumber. + * + * @param handle EDMA handle pointer, users shall not touch the values inside. + * @param userData The callback user parameter pointer. Users can use this parameter to involve things users need to + * change in EDMA callback function. + * @param transferDone If the current loaded transfer done. In normal mode it means if all transfer done. In scatter + * gather mode, this parameter shows is the current transfer block in EDMA register is done. As the + * load of core is different, it will be different if the new tcd loaded into EDMA registers while + * this callback called. If true, it always means new tcd still not loaded into registers, while + * false means new tcd already loaded into registers. + * @param tcds How many tcds are done from the last callback. This parameter only used in scatter gather mode. It + * tells user how many tcds are finished between the last callback and this. + */ typedef void (*edma_callback)(struct _edma_handle *handle, void *userData, bool transferDone, uint32_t tcds); /*! @brief eDMA transfer handle structure */ @@ -702,7 +698,7 @@ static inline void EDMA_TriggerChannelStart(DMA_Type *base, uint32_t channel) * @brief Gets the remaining major loop count from the eDMA current channel TCD. * * This function checks the TCD (Task Control Descriptor) status for a specified - * eDMA channel and returns the the number of major loop count that has not finished. + * eDMA channel and returns the number of major loop count that has not finished. * * @param base eDMA peripheral base address. * @param channel eDMA channel number. @@ -774,7 +770,10 @@ void EDMA_CreateHandle(edma_handle_t *handle, DMA_Type *base, uint32_t channel); /*! * @brief Installs the TCDs memory pool into the eDMA handle. * - * This function is called after the EDMA_CreateHandle to use scatter/gather feature. + * This function is called after the EDMA_CreateHandle to use scatter/gather feature. This function shall only be used + * while users need to use scatter gather mode. Scatter gather mode enables EDMA to load a new transfer control block + * (tcd) in hardware, and automatically reconfigure that DMA channel for a new transfer. + * Users need to prepare tcd memory and also configure tcds using interface EDMA_SubmitTransfer. * * @param handle eDMA handle pointer. * @param tcdPool A memory pool to store TCDs. It must be 32 bytes aligned. @@ -786,7 +785,7 @@ void EDMA_InstallTCDMemory(edma_handle_t *handle, edma_tcd_t *tcdPool, uint32_t * @brief Installs a callback function for the eDMA transfer. * * This callback is called in the eDMA IRQ handler. Use the callback to do something after - * the current major loop transfer completes. + * the current major loop transfer completes. This function will be called every time one tcd finished transfer. * * @param handle eDMA handle pointer. * @param callback eDMA callback function pointer. @@ -824,8 +823,8 @@ void EDMA_PrepareTransfer(edma_transfer_config_t *config, * @brief Submits the eDMA transfer request. * * This function submits the eDMA transfer request according to the transfer configuration structure. - * If submitting the transfer request repeatedly, this function packs an unprocessed request as - * a TCD and enables scatter/gather feature to process it in the next time. + * In scatter gather mode, call this function will add a configured tcd to the circular list of tcd pool. + * The tcd pools is setup by call function EDMA_InstallTCDMemory before. * * @param handle eDMA handle pointer. * @param config Pointer to eDMA transfer configuration structure. diff --git a/ext/hal/nxp/mcux/drivers/kinetis/fsl_enet.c b/ext/hal/nxp/mcux/drivers/kinetis/fsl_enet.c index 737bf9a5468..b8bb27ea1ab 100644 --- a/ext/hal/nxp/mcux/drivers/kinetis/fsl_enet.c +++ b/ext/hal/nxp/mcux/drivers/kinetis/fsl_enet.c @@ -1,31 +1,9 @@ /* * Copyright (c) 2015 - 2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP + * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * SPDX-License-Identifier: BSD-3-Clause */ #include "fsl_enet.h" @@ -36,6 +14,12 @@ /******************************************************************************* * Definitions ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.enet" +#endif + /*! @brief IPv4 PTP message IP version offset. */ #define ENET_PTP1588_IPVERSION_OFFSET 0x0EU /*! @brief IPv4 PTP message UDP protocol offset. */ @@ -99,7 +83,9 @@ /*! @brief NanoSecond in one second. */ #define ENET_NANOSECOND_ONE_SECOND 1000000000U /*! @brief Define a common clock cycle delays used for time stamp capture. */ -#define ENET_1588TIME_DELAY_COUNT 38U +#ifndef ENET_1588TIME_DELAY_COUNT +#define ENET_1588TIME_DELAY_COUNT 10U +#endif /*! @brief Defines the macro for converting constants from host byte order to network byte order. */ #define ENET_HTONS(n) __REV16(n) @@ -169,7 +155,9 @@ static void ENET_SetHandler(ENET_Type *base, * @param config The ENET configuration structure. * @param bufferConfig The ENET buffer configuration. */ -static void ENET_SetTxBufferDescriptors(enet_handle_t *handle, const enet_config_t *config, const enet_buffer_config_t *bufferConfig); +static void ENET_SetTxBufferDescriptors(enet_handle_t *handle, + const enet_config_t *config, + const enet_buffer_config_t *bufferConfig); /*! * @brief Set ENET MAC receive buffer descriptors. @@ -178,7 +166,9 @@ static void ENET_SetTxBufferDescriptors(enet_handle_t *handle, const enet_config * @param config The ENET configuration structure. * @param bufferConfig The ENET buffer configuration. */ -static void ENET_SetRxBufferDescriptors(enet_handle_t *handle, const enet_config_t *config, const enet_buffer_config_t *bufferConfig); +static void ENET_SetRxBufferDescriptors(enet_handle_t *handle, + const enet_config_t *config, + const enet_buffer_config_t *bufferConfig); /*! * @brief Updates the ENET read buffer descriptors. @@ -326,6 +316,20 @@ uint32_t ENET_GetInstance(ENET_Type *base) return instance; } +/*! + * brief Gets the ENET default configuration structure. + * + * The purpose of this API is to get the default ENET MAC controller + * configure structure for ENET_Init(). User may use the initialized + * structure unchanged in ENET_Init(), or modify some fields of the + * structure before calling ENET_Init(). + * Example: + code + enet_config_t config; + ENET_GetDefaultConfig(&config); + endcode + * param config The ENET mac controller configuration structure pointer. + */ void ENET_GetDefaultConfig(enet_config_t *config) { /* Checks input parameter. */ @@ -334,13 +338,13 @@ void ENET_GetDefaultConfig(enet_config_t *config) /* Initializes the MAC configure structure to zero. */ memset(config, 0, sizeof(enet_config_t)); - /* Sets MII mode, full duplex, 100Mbps for MAC and PHY data interface. */ -#if defined(FSL_FEATURE_ENET_HAS_AVB) && FSL_FEATURE_ENET_HAS_AVB +/* Sets MII mode, full duplex, 100Mbps for MAC and PHY data interface. */ +#if defined(FSL_FEATURE_ENET_HAS_AVB) && FSL_FEATURE_ENET_HAS_AVB config->miiMode = kENET_RgmiiMode; #else config->miiMode = kENET_RmiiMode; #endif - config->miiSpeed = kENET_MiiSpeed100M; + config->miiSpeed = kENET_MiiSpeed100M; config->miiDuplex = kENET_MiiFullDuplex; config->ringNum = 1; @@ -349,6 +353,33 @@ void ENET_GetDefaultConfig(enet_config_t *config) config->rxMaxFrameLen = ENET_FRAME_MAX_FRAMELEN; } +/*! + * brief Initializes the ENET module. + * + * This function ungates the module clock and initializes it with the ENET configuration. + * + * param base ENET peripheral base address. + * param handle ENET handler pointer. + * param config ENET mac configuration structure pointer. + * The "enet_config_t" type mac configuration return from ENET_GetDefaultConfig + * can be used directly. It is also possible to verify the Mac configuration using other methods. + * param bufferConfig ENET buffer configuration structure pointer. + * The buffer configuration should be prepared for ENET Initialization. + * It is the start address of "ringNum" enet_buffer_config structures. + * To support added multi-ring features in some soc and compatible with the previous + * enet driver version. For single ring supported, this bufferConfig is a buffer + * configure structure pointer, for multi-ring supported and used case, this bufferConfig + * pointer should be a buffer configure structure array pointer. + * param macAddr ENET mac address of Ethernet device. This MAC address should be + * provided. + * param srcClock_Hz The internal module clock source for MII clock. + * + * note ENET has two buffer descriptors legacy buffer descriptors and + * enhanced IEEE 1588 buffer descriptors. The legacy descriptor is used by default. To + * use the IEEE 1588 feature, use the enhanced IEEE 1588 buffer descriptor + * by defining "ENET_ENHANCEDBUFFERDESCRIPTOR_MODE" and calling ENET_Ptp1588Configure() + * to configure the 1588 feature and related buffers after calling ENET_Init(). + */ void ENET_Init(ENET_Type *base, enet_handle_t *handle, const enet_config_t *config, @@ -385,6 +416,13 @@ void ENET_Init(ENET_Type *base, ENET_SetHandler(base, handle, config, bufferConfig); } +/*! + * brief Deinitializes the ENET module. + + * This function gates the module clock, clears ENET interrupts, and disables the ENET module. + * + * param base ENET peripheral base address. + */ void ENET_Deinit(ENET_Type *base) { /* Disable interrupt. */ @@ -393,13 +431,21 @@ void ENET_Deinit(ENET_Type *base) /* Disable ENET. */ base->ECR &= ~ENET_ECR_ETHEREN_MASK; - #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) /* Disables the clock source. */ CLOCK_DisableClock(s_enetClock[ENET_GetInstance(base)]); #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ } +/*! + * brief Sets the callback function. + * This API is provided for the application callback required case when ENET + * interrupt is enabled. This API should be called after calling ENET_Init. + * + * param handle ENET handler pointer. Should be provided by application. + * param callback The ENET callback function. + * param userData The callback function parameter. + */ void ENET_SetCallback(enet_handle_t *handle, enet_callback_t callback, void *userData) { assert(handle); @@ -501,7 +547,7 @@ static void ENET_SetMacController(ENET_Type *base, ((macSpecialConfig & kENET_ControlRxPadRemoveEnable) ? ENET_RCR_PADEN_MASK : 0) | ((macSpecialConfig & kENET_ControlRxBroadCastRejectEnable) ? ENET_RCR_BC_REJ_MASK : 0) | ((macSpecialConfig & kENET_ControlPromiscuousEnable) ? ENET_RCR_PROM_MASK : 0) | - ENET_RCR_MAX_FL(maxFrameLen) | ENET_RCR_CRCFWD_MASK; + ENET_RCR_MAX_FL(maxFrameLen) | ENET_RCR_CRCFWD_MASK; /* Set the RGMII or RMII, MII mode and control register. */ #if defined(FSL_FEATURE_ENET_HAS_AVB) && FSL_FEATURE_ENET_HAS_AVB @@ -594,14 +640,14 @@ static void ENET_SetMacController(ENET_Type *base, base->RSFL = 0; } - /* Initializes the ring 0. */ +/* Initializes the ring 0. */ #if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET base->TDSR = MEMORY_ConvertMemoryMapAddress((uint32_t)bufferConfig->txBdStartAddrAlign, kMEMORY_Local2DMA); - base->RDSR = MEMORY_ConvertMemoryMapAddress((uint32_t)bufferConfig->rxBdStartAddrAlign, kMEMORY_Local2DMA); + base->RDSR = MEMORY_ConvertMemoryMapAddress((uint32_t)bufferConfig->rxBdStartAddrAlign, kMEMORY_Local2DMA); #else base->TDSR = (uint32_t)bufferConfig->txBdStartAddrAlign; base->RDSR = (uint32_t)bufferConfig->rxBdStartAddrAlign; -#endif +#endif base->MRBR = bufferConfig->rxBuffSizeAlign; #if defined(FSL_FEATURE_ENET_HAS_AVB) && FSL_FEATURE_ENET_HAS_AVB @@ -616,7 +662,7 @@ static void ENET_SetMacController(ENET_Type *base, base->RDSR1 = MEMORY_ConvertMemoryMapAddress((uint32_t)buffCfg->rxBdStartAddrAlign, kMEMORY_Local2DMA); #else base->TDSR1 = (uint32_t)buffCfg->txBdStartAddrAlign; - base->RDSR1 = (uint32_t)buffCfg->rxBdStartAddrAlign; + base->RDSR1 = (uint32_t)buffCfg->rxBdStartAddrAlign; #endif base->MRBR1 = buffCfg->rxBuffSizeAlign; /* Enable the DMAC for ring 1 and with no rx classification set. */ @@ -698,7 +744,9 @@ static void ENET_SetMacController(ENET_Type *base, base->ECR = ecr; } -static void ENET_SetTxBufferDescriptors(enet_handle_t *handle, const enet_config_t *config, const enet_buffer_config_t *bufferConfig) +static void ENET_SetTxBufferDescriptors(enet_handle_t *handle, + const enet_config_t *config, + const enet_buffer_config_t *bufferConfig) { assert(config); assert(bufferConfig); @@ -752,7 +800,9 @@ static void ENET_SetTxBufferDescriptors(enet_handle_t *handle, const enet_config } } -static void ENET_SetRxBufferDescriptors(enet_handle_t *handle, const enet_config_t *config, const enet_buffer_config_t *bufferConfig) +static void ENET_SetRxBufferDescriptors(enet_handle_t *handle, + const enet_config_t *config, + const enet_buffer_config_t *bufferConfig) { assert(config); assert(bufferConfig); @@ -793,6 +843,12 @@ static void ENET_SetRxBufferDescriptors(enet_handle_t *handle, const enet_config #else rxBuffer = buffCfg->rxBufferAlign; #endif + +#if defined(FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL) && FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL + /* Invalidate rx buffers before DMA transfer data into them. */ + DCACHE_InvalidateByRange((uint32_t)rxBuffer, (buffCfg->rxBdNumber * rxBuffSizeAlign)); +#endif /* FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL */ + for (count = 0; count < buffCfg->rxBdNumber; count++) { /* Set data buffer and the length. */ @@ -849,6 +905,15 @@ static void ENET_ActiveSend(ENET_Type *base, uint32_t ringId) } } +/*! + * brief Sets the ENET MII speed and duplex. + * + * This API is provided to dynamically change the speed and dulpex for MAC. + * + * param base ENET peripheral base address. + * param speed The speed of the RMII mode. + * param duplex The duplex of the RMII mode. + */ void ENET_SetMII(ENET_Type *base, enet_mii_speed_t speed, enet_mii_duplex_t duplex) { uint32_t rcr = base->RCR; @@ -895,6 +960,13 @@ void ENET_SetMII(ENET_Type *base, enet_mii_speed_t speed, enet_mii_duplex_t dupl base->TCR = tcr; } +/*! + * brief Sets the ENET module Mac address. + * + * param base ENET peripheral base address. + * param macAddr The six-byte Mac address pointer. + * The pointer is allocated by application and input into the API. + */ void ENET_SetMacAddr(ENET_Type *base, uint8_t *macAddr) { uint32_t address; @@ -908,6 +980,13 @@ void ENET_SetMacAddr(ENET_Type *base, uint8_t *macAddr) base->PAUR = address << ENET_PAUR_PADDR2_SHIFT; } +/*! + * brief Gets the ENET module Mac address. + * + * param base ENET peripheral base address. + * param macAddr The six-byte Mac address pointer. + * The pointer is allocated by application and input into the API. + */ void ENET_GetMacAddr(ENET_Type *base, uint8_t *macAddr) { assert(macAddr); @@ -927,6 +1006,15 @@ void ENET_GetMacAddr(ENET_Type *base, uint8_t *macAddr) macAddr[5] = 0xFFU & address; } +/*! + * brief Sets the ENET SMI(serial management interface)- MII management interface. + * + * param base ENET peripheral base address. + * param srcClock_Hz This is the ENET module clock frequency. Normally it's the system clock. See clock distribution. + * param isPreambleDisabled The preamble disable flag. + * - true Enables the preamble. + * - false Disables the preamble. + */ void ENET_SetSMI(ENET_Type *base, uint32_t srcClock_Hz, bool isPreambleDisabled) { assert(srcClock_Hz); @@ -940,10 +1028,22 @@ void ENET_SetSMI(ENET_Type *base, uint32_t srcClock_Hz, bool isPreambleDisabled) /* Calculate the hold time on the MDIO output. */ clkCycle = (10 + ENET_NANOSECOND_ONE_SECOND / srcClock_Hz - 1) / (ENET_NANOSECOND_ONE_SECOND / srcClock_Hz) - 1; /* Build the configuration for MDC/MDIO control. */ - mscr = ENET_MSCR_MII_SPEED(speed) | ENET_MSCR_HOLDTIME(clkCycle) | (isPreambleDisabled ? ENET_MSCR_DIS_PRE_MASK : 0); + mscr = + ENET_MSCR_MII_SPEED(speed) | ENET_MSCR_HOLDTIME(clkCycle) | (isPreambleDisabled ? ENET_MSCR_DIS_PRE_MASK : 0); base->MSCR = mscr; } +/*! + * brief Starts an SMI write command. + * + * Used for standard IEEE802.3 MDIO Clause 22 format. + * + * param base ENET peripheral base address. + * param phyAddr The PHY address. + * param phyReg The PHY register. Range from 0 ~ 31. + * param operation The write operation. + * param data The data written to PHY. + */ void ENET_StartSMIWrite(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg, enet_mii_write_t operation, uint32_t data) { uint32_t mmfr = 0; @@ -954,6 +1054,16 @@ void ENET_StartSMIWrite(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg, enet base->MMFR = mmfr; } +/*! + * brief Starts an SMI (Serial Management Interface) read command. + * + * Used for standard IEEE802.3 MDIO Clause 22 format. + * + * param base ENET peripheral base address. + * param phyAddr The PHY address. + * param phyReg The PHY register. Range from 0 ~ 31. + * param operation The read operation. + */ void ENET_StartSMIRead(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg, enet_mii_read_t operation) { uint32_t mmfr = 0; @@ -964,6 +1074,16 @@ void ENET_StartSMIRead(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg, enet_ } #if defined(FSL_FEATURE_ENET_HAS_EXTEND_MDIO) && FSL_FEATURE_ENET_HAS_EXTEND_MDIO +/*! + * brief Starts the extended IEEE802.3 Clause 45 MDIO format SMI write command. + * + * param base ENET peripheral base address. + * param phyAddr The PHY address. + * param phyReg The PHY register. For MDIO IEEE802.3 Clause 45, + * the phyReg is a 21-bits combination of the devaddr (5 bits device address) + * and the regAddr (16 bits phy register): phyReg = (devaddr << 16) | regAddr. + * param data The data written to PHY. + */ void ENET_StartExtC45SMIWrite(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg, uint32_t data) { uint32_t mmfr = 0; @@ -983,6 +1103,15 @@ void ENET_StartExtC45SMIWrite(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg base->MMFR = mmfr; } +/*! + * brief Starts the extended IEEE802.3 Clause 45 MDIO format SMI read command. + * + * param base ENET peripheral base address. + * param phyAddr The PHY address. + * param phyReg The PHY register. For MDIO IEEE802.3 Clause 45, + * the phyReg is a 21-bits combination of the devaddr (5 bits device address) + * and the regAddr (16 bits phy register): phyReg = (devaddr << 16) | regAddr. + */ void ENET_StartExtC45SMIRead(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg) { uint32_t mmfr = 0; @@ -1003,6 +1132,26 @@ void ENET_StartExtC45SMIRead(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg) } #endif /* FSL_FEATURE_ENET_HAS_EXTEND_MDIO */ +/*! + * brief Gets the error statistics of a received frame for ENET single ring. + * + * This API must be called after the ENET_GetRxFrameSize and before the ENET_ReadFrame(). + * If the ENET_GetRxFrameSize returns kStatus_ENET_RxFrameError, + * the ENET_GetRxErrBeforeReadFrame can be used to get the exact error statistics. + * This is an example. + * code + * status = ENET_GetRxFrameSize(&g_handle, &length); + * if (status == kStatus_ENET_RxFrameError) + * { + * // Get the error information of the received frame. + * ENET_GetRxErrBeforeReadFrame(&g_handle, &eErrStatic); + * // update the receive buffer. + * ENET_ReadFrame(EXAMPLE_ENET, &g_handle, NULL, 0); + * } + * endcode + * param handle The ENET handler structure pointer. This is the same handler pointer used in the ENET_Init. + * param eErrorStatic The error statistics structure pointer. + */ void ENET_GetRxErrBeforeReadFrame(enet_handle_t *handle, enet_data_error_stats_t *eErrorStatic) { assert(handle); @@ -1078,6 +1227,22 @@ void ENET_GetRxErrBeforeReadFrame(enet_handle_t *handle, enet_data_error_stats_t } while (curBuffDescrip != handle->rxBdCurrent[0]); } +/*! +* brief Gets the size of the read frame for single ring. +* +* This function gets a received frame size from the ENET buffer descriptors. +* note The FCS of the frame is automatically removed by MAC and the size is the length without the FCS. +* After calling ENET_GetRxFrameSize, ENET_ReadFrame() should be called to update the +* receive buffers If the result is not "kStatus_ENET_RxFrameEmpty". +* +* param handle The ENET handler structure. This is the same handler pointer used in the ENET_Init. +* param length The length of the valid frame received. +* retval kStatus_ENET_RxFrameEmpty No frame received. Should not call ENET_ReadFrame to read frame. +* retval kStatus_ENET_RxFrameError Data error happens. ENET_ReadFrame should be called with NULL data +* and NULL length to update the receive buffers. +* retval kStatus_Success Receive a frame Successfully then the ENET_ReadFrame +* should be called with the right data buffer and the captured data length input. +*/ status_t ENET_GetRxFrameSize(enet_handle_t *handle, uint32_t *length) { assert(handle); @@ -1136,6 +1301,43 @@ status_t ENET_GetRxFrameSize(enet_handle_t *handle, uint32_t *length) return kStatus_ENET_RxFrameEmpty; } +/*! + * brief Reads a frame from the ENET device for single ring. + * This function reads a frame (both the data and the length) from the ENET buffer descriptors. + * The ENET_GetRxFrameSize should be used to get the size of the prepared data buffer. + * This is an example: + * code + * uint32_t length; + * enet_handle_t g_handle; + * //Get the received frame size firstly. + * status = ENET_GetRxFrameSize(&g_handle, &length); + * if (length != 0) + * { + * //Allocate memory here with the size of "length" + * uint8_t *data = memory allocate interface; + * if (!data) + * { + * ENET_ReadFrame(ENET, &g_handle, NULL, 0); + * //Add the console warning log. + * } + * else + * { + * status = ENET_ReadFrame(ENET, &g_handle, data, length); + * //Call stack input API to deliver the data to stack + * } + * } + * else if (status == kStatus_ENET_RxFrameError) + * { + * //Update the received buffer when a error frame is received. + * ENET_ReadFrame(ENET, &g_handle, NULL, 0); + * } + * endcode + * param base ENET peripheral base address. + * param handle The ENET handler structure. This is the same handler pointer used in the ENET_Init. + * param data The data buffer provided by user to store the frame which memory size should be at least "length". + * param length The size of the data buffer which is still the length of the received frame. + * return The execute status, successful or failure. + */ status_t ENET_ReadFrame(ENET_Type *base, enet_handle_t *handle, uint8_t *data, uint32_t length) { assert(handle); @@ -1171,25 +1373,19 @@ status_t ENET_ReadFrame(ENET_Type *base, enet_handle_t *handle, uint8_t *data, u } else { - /* A frame on one buffer or several receive buffers are both considered. */ -#if defined(FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL) && FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL - /* Add the cache invalidate maintain. */ +/* A frame on one buffer or several receive buffers are both considered. */ #if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET - address = MEMORY_ConvertMemoryMapAddress((uint32_t)curBuffDescrip->buffer,kMEMORY_DMA2Local); + address = MEMORY_ConvertMemoryMapAddress((uint32_t)curBuffDescrip->buffer, kMEMORY_DMA2Local); #else address = (uint32_t)curBuffDescrip->buffer; #endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */ +#if defined(FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL) && FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL + /* Add the cache invalidate maintain. */ DCACHE_InvalidateByRange(address, handle->rxBuffSizeAlign[0]); -#endif /* FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL */ -/* A frame on one buffer or several receive buffers are both considered. */ +#endif /* FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL */ #ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE enet_ptp_time_data_t ptpTimestamp; bool isPtpEventMessage = false; -#if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET - address = MEMORY_ConvertMemoryMapAddress((uint32_t)curBuffDescrip->buffer,kMEMORY_DMA2Local); -#else - address = (uint32_t)curBuffDescrip->buffer; -#endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */ /* Parse the PTP message according to the header message. */ isPtpEventMessage = ENET_Ptp1588ParseFrame((uint8_t *)address, &ptpTimestamp, false); #endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ @@ -1205,11 +1401,6 @@ status_t ENET_ReadFrame(ENET_Type *base, enet_handle_t *handle, uint8_t *data, u { /* Copy the frame to user's buffer without FCS. */ len = curBuffDescrip->length - offset; -#if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET - address = MEMORY_ConvertMemoryMapAddress((uint32_t)curBuffDescrip->buffer,kMEMORY_DMA2Local); -#else - address = (uint32_t)curBuffDescrip->buffer; -#endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */ memcpy(data + offset, (void *)address, len); #ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE /* Store the PTP 1588 timestamp for received PTP event frame. */ @@ -1240,11 +1431,7 @@ status_t ENET_ReadFrame(ENET_Type *base, enet_handle_t *handle, uint8_t *data, u { break; } -#if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET - address = MEMORY_ConvertMemoryMapAddress((uint32_t)curBuffDescrip->buffer,kMEMORY_DMA2Local); -#else - address = (uint32_t)curBuffDescrip->buffer; -#endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */ + memcpy(data + offset, (void *)address, handle->rxBuffSizeAlign[0]); offset += handle->rxBuffSizeAlign[0]; @@ -1254,15 +1441,15 @@ status_t ENET_ReadFrame(ENET_Type *base, enet_handle_t *handle, uint8_t *data, u /* Get the current buffer descriptor. */ curBuffDescrip = handle->rxBdCurrent[0]; -#if defined(FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL) && FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL - /* Add the cache invalidate maintain. */ +/* Add the cache invalidate maintain. */ #if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET - address = MEMORY_ConvertMemoryMapAddress((uint32_t)curBuffDescrip->buffer,kMEMORY_DMA2Local); + address = MEMORY_ConvertMemoryMapAddress((uint32_t)curBuffDescrip->buffer, kMEMORY_DMA2Local); #else address = (uint32_t)curBuffDescrip->buffer; -#endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */ +#endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */ +#if defined(FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL) && FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL DCACHE_InvalidateByRange(address, handle->rxBuffSizeAlign[0]); -#endif /* FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL */ +#endif /* FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL */ } } @@ -1309,6 +1496,22 @@ static void ENET_UpdateReadBuffers(ENET_Type *base, enet_handle_t *handle, uint3 } } +/*! + * brief Transmits an ENET frame for single ring. + * note The CRC is automatically appended to the data. Input the data + * to send without the CRC. + * + * + * param base ENET peripheral base address. + * param handle The ENET handler pointer. This is the same handler pointer used in the ENET_Init. + * param data The data buffer provided by user to be send. + * param length The length of the data to be send. + * retval kStatus_Success Send frame succeed. + * retval kStatus_ENET_TxFrameBusy Transmit buffer descriptor is busy under transmission. + * The transmit busy happens when the data send rate is over the MAC capacity. + * The waiting mechanism is recommended to be added after each call return with + * kStatus_ENET_TxFrameBusy. + */ status_t ENET_SendFrame(ENET_Type *base, enet_handle_t *handle, const uint8_t *data, uint32_t length) { assert(handle); @@ -1339,13 +1542,16 @@ status_t ENET_SendFrame(ENET_Type *base, enet_handle_t *handle, const uint8_t *d /* One transmit buffer is enough for one frame. */ if (handle->txBuffSizeAlign[0] >= length) { - /* Copy data to the buffer for uDMA transfer. */ +/* Copy data to the buffer for uDMA transfer. */ #if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET - address = MEMORY_ConvertMemoryMapAddress((uint32_t)curBuffDescrip->buffer,kMEMORY_DMA2Local); + address = MEMORY_ConvertMemoryMapAddress((uint32_t)curBuffDescrip->buffer, kMEMORY_DMA2Local); #else address = (uint32_t)curBuffDescrip->buffer; #endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */ memcpy((void *)address, data, length); +#if defined(FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL) && FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL + DCACHE_CleanByRange(address, length); +#endif /* FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL */ /* Set data length. */ curBuffDescrip->length = length; #ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE @@ -1371,15 +1577,6 @@ status_t ENET_SendFrame(ENET_Type *base, enet_handle_t *handle, const uint8_t *d { handle->txBdCurrent[0]++; } -#if defined(FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL) && FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL - /* Add the cache clean maintain. */ -#if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET - address = MEMORY_ConvertMemoryMapAddress((uint32_t)curBuffDescrip->buffer,kMEMORY_DMA2Local); -#else - address = (uint32_t)curBuffDescrip->buffer; -#endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */ - DCACHE_CleanByRange(address, length); -#endif /* FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL */ /* Active the transmit buffer descriptor. */ ENET_ActiveSend(base, 0); @@ -1413,15 +1610,19 @@ status_t ENET_SendFrame(ENET_Type *base, enet_handle_t *handle, const uint8_t *d } /* update the size left to be transmit. */ sizeleft = length - len; +#if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET + address = MEMORY_ConvertMemoryMapAddress((uint32_t)curBuffDescrip->buffer, kMEMORY_DMA2Local); +#else + address = (uint32_t)curBuffDescrip->buffer; +#endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */ if (sizeleft > handle->txBuffSizeAlign[0]) { /* Data copy. */ -#if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET - address = MEMORY_ConvertMemoryMapAddress((uint32_t)curBuffDescrip->buffer,kMEMORY_DMA2Local); -#else - address = (uint32_t)curBuffDescrip->buffer; -#endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */ memcpy((void *)address, data + len, handle->txBuffSizeAlign[0]); +#if defined(FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL) && FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL + /* Add the cache clean maintain. */ + DCACHE_CleanByRange(address, handle->txBuffSizeAlign[0]); +#endif /* FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL */ /* Data length update. */ curBuffDescrip->length = handle->txBuffSizeAlign[0]; len += handle->txBuffSizeAlign[0]; @@ -1433,24 +1634,14 @@ status_t ENET_SendFrame(ENET_Type *base, enet_handle_t *handle, const uint8_t *d } else { -#if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET - address = MEMORY_ConvertMemoryMapAddress((uint32_t)curBuffDescrip->buffer,kMEMORY_DMA2Local); -#else - address = (uint32_t)curBuffDescrip->buffer; -#endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */ memcpy((void *)address, data + len, sizeleft); +#if defined(FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL) && FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL + /* Add the cache clean maintain. */ + DCACHE_CleanByRange(address, sizeleft); +#endif /* FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL */ curBuffDescrip->length = sizeleft; /* Set Last buffer wrap flag. */ curBuffDescrip->control |= ENET_BUFFDESCRIPTOR_TX_READY_MASK | ENET_BUFFDESCRIPTOR_TX_LAST_MASK; -#if defined(FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL) && FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL - /* Add the cache clean maintain. */ -#if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET - address = MEMORY_ConvertMemoryMapAddress((uint32_t)curBuffDescrip->buffer,kMEMORY_DMA2Local); -#else - address = (uint32_t)curBuffDescrip->buffer; -#endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */ - DCACHE_CleanByRange(address, handle->txBuffSizeAlign[0]); -#endif /* FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL */ /* Active the transmit buffer descriptor. */ ENET_ActiveSend(base, 0); @@ -1467,6 +1658,17 @@ status_t ENET_SendFrame(ENET_Type *base, enet_handle_t *handle, const uint8_t *d } #if FSL_FEATURE_ENET_QUEUE > 1 +/*! + * brief Gets the error statistics of received frame for extended multi-ring. + * + * This API must be called after the ENET_GetRxFrameSizeMultiRing and before the ENET_ReadFrameMultiRing(). + * If the ENET_GetRxFrameSizeMultiRing returns kStatus_ENET_RxFrameError, + * the ENET_GetRxErrBeforeReadFrameMultiRing can be used to get the exact error statistics. + * + * param handle The ENET handler structure pointer. This is the same handler pointer used in the ENET_Init. + * param eErrorStatic The error statistics structure pointer. + * param ringId The ring index, range from 0 ~ FSL_FEATURE_ENET_QUEUE - 1. + */ void ENET_GetRxErrBeforeReadFrameMultiRing(enet_handle_t *handle, enet_data_error_stats_t *eErrorStatic, uint32_t ringId) @@ -1544,6 +1746,24 @@ void ENET_GetRxErrBeforeReadFrameMultiRing(enet_handle_t *handle, } while (curBuffDescrip != handle->rxBdCurrent[ringId]); } +/*! +* brief Gets the size of the read frame for extended mutli-ring. +* +* This function gets a received frame size from the ENET buffer descriptors. +* note The FCS of the frame is automatically removed by MAC and the size is the length without the FCS. +* After calling ENET_GetRxFrameSizeMultiRing, ENET_ReadFrameMultiRing() should be called to update the +* receive buffers If the result is not "kStatus_ENET_RxFrameEmpty". The usage is +* the same to the single ring, refer to ENET_GetRxFrameSize. +* +* param handle The ENET handler structure. This is the same handler pointer used in the ENET_Init. +* param length The length of the valid frame received. +* param ringId The ring index or ring number; +* retval kStatus_ENET_RxFrameEmpty No frame received. Should not call ENET_ReadFrameMultiRing to read frame. +* retval kStatus_ENET_RxFrameError Data error happens. ENET_ReadFrameMultiRing should be called with NULL data +* and NULL length to update the receive buffers. +* retval kStatus_Success Receive a frame Successfully then the ENET_ReadFrame +* should be called with the right data buffer and the captured data length input. +*/ status_t ENET_GetRxFrameSizeMultiRing(enet_handle_t *handle, uint32_t *length, uint32_t ringId) { assert(handle); @@ -1568,7 +1788,7 @@ status_t ENET_GetRxFrameSizeMultiRing(enet_handle_t *handle, uint32_t *length, u if ((!(curBuffDescrip->control & ENET_BUFFDESCRIPTOR_RX_EMPTY_MASK)) && (!curBuffDescrip->length)) { return kStatus_ENET_RxFrameError; - } + } /* Find the last buffer descriptor. */ if ((curBuffDescrip->control & validLastMask) == ENET_BUFFDESCRIPTOR_RX_LAST_MASK) { @@ -1600,6 +1820,20 @@ status_t ENET_GetRxFrameSizeMultiRing(enet_handle_t *handle, uint32_t *length, u return kStatus_ENET_RxFrameEmpty; } +/*! + * brief Reads a frame from the ENET device for multi-ring. + * + * This function reads a frame (both the data and the length) from the ENET buffer descriptors. + * The ENET_GetRxFrameSizeMultiRing should be used to get the size of the prepared data buffer. + * This usage is the same as the single ring, refer to ENET_ReadFrame. + + * param base ENET peripheral base address. + * param handle The ENET handler structure. This is the same handler pointer used in the ENET_Init. + * param data The data buffer provided by user to store the frame which memory size should be at least "length". + * param length The size of the data buffer which is still the length of the received frame. + * param ringId The ring index or ring number; + * return The execute status, successful or failure. + */ status_t ENET_ReadFrameMultiRing( ENET_Type *base, enet_handle_t *handle, uint8_t *data, uint32_t length, uint32_t ringId) { @@ -1636,26 +1870,20 @@ status_t ENET_ReadFrameMultiRing( } else { - /* A frame on one buffer or several receive buffers are both considered. */ -#if defined(FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL) && FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL - /* Add the cache invalidate maintain. */ +/* A frame on one buffer or several receive buffers are both considered. */ #if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET - address = MEMORY_ConvertMemoryMapAddress((uint32_t)curBuffDescrip->buffer,kMEMORY_DMA2Local); + address = MEMORY_ConvertMemoryMapAddress((uint32_t)curBuffDescrip->buffer, kMEMORY_DMA2Local); #else address = (uint32_t)curBuffDescrip->buffer; #endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */ +#if defined(FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL) && FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL + /* Add the cache invalidate maintain. */ DCACHE_InvalidateByRange(address, handle->rxBuffSizeAlign[ringId]); #endif /* FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL */ #ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE enet_ptp_time_data_t ptpTimestamp; bool isPtpEventMessage = false; - /* Parse the PTP message according to the header message. */ -#if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET - address = MEMORY_ConvertMemoryMapAddress((uint32_t)curBuffDescrip->buffer,kMEMORY_DMA2Local); -#else - address = (uint32_t)curBuffDescrip->buffer; -#endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */ isPtpEventMessage = ENET_Ptp1588ParseFrame((uint8_t *)address, &ptpTimestamp, false); #endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ @@ -1670,11 +1898,6 @@ status_t ENET_ReadFrameMultiRing( { /* Copy the frame to user's buffer without FCS. */ len = curBuffDescrip->length - offset; -#if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET - address = MEMORY_ConvertMemoryMapAddress((uint32_t)curBuffDescrip->buffer,kMEMORY_DMA2Local); -#else - address = (uint32_t)curBuffDescrip->buffer; -#endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */ memcpy(data + offset, (void *)address, len); #ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE /* Store the PTP 1588 timestamp for received PTP event frame. */ @@ -1705,15 +1928,9 @@ status_t ENET_ReadFrameMultiRing( { break; } -#if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET - address = MEMORY_ConvertMemoryMapAddress((uint32_t)curBuffDescrip->buffer,kMEMORY_DMA2Local); -#else - address = (uint32_t)curBuffDescrip->buffer; -#endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */ memcpy(data + offset, (void *)address, handle->rxBuffSizeAlign[ringId]); offset += handle->rxBuffSizeAlign[ringId]; - /* Updates the receive buffer descriptors. */ ENET_UpdateReadBuffers(base, handle, ringId); } @@ -1721,13 +1938,13 @@ status_t ENET_ReadFrameMultiRing( /* Get the current buffer descriptor. */ curBuffDescrip = handle->rxBdCurrent[ringId]; -#if defined(FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL) && FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL - /* Add the cache invalidate maintain. */ #if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET - address = MEMORY_ConvertMemoryMapAddress((uint32_t)curBuffDescrip->buffer,kMEMORY_DMA2Local); + address = MEMORY_ConvertMemoryMapAddress((uint32_t)curBuffDescrip->buffer, kMEMORY_DMA2Local); #else address = (uint32_t)curBuffDescrip->buffer; #endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */ +#if defined(FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL) && FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL + /* Add the cache invalidate maintain. */ DCACHE_InvalidateByRange(address, handle->rxBuffSizeAlign[ringId]); #endif /* FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL */ } @@ -1736,7 +1953,27 @@ status_t ENET_ReadFrameMultiRing( return kStatus_ENET_RxFrameFail; } - +/*! + * brief Transmits an ENET frame for extended multi-ring. + * note The CRC is automatically appended to the data. Input the data + * to send without the CRC. + * + * In this API, multiple-ring are mainly used for extended avb frames are supported. + * The transmit scheme for avb frames is the credit-based scheme, the AVB class A, AVB class B + * and the non-AVB frame are transmitted in ring 1, ring 2 and ring 0 independently. + * So application should care about the transmit ring index when use multiple-ring transmission. + * + * param base ENET peripheral base address. + * param handle The ENET handler pointer. This is the same handler pointer used in the ENET_Init. + * param data The data buffer provided by user to be send. + * param length The length of the data to be send. + * param ringId The ring index for transmission. + * retval kStatus_Success Send frame succeed. + * retval kStatus_ENET_TxFrameBusy Transmit buffer descriptor is busy under transmission. + * The transmit busy happens when the data send rate is over the MAC capacity. + * The waiting mechanism is recommended to be added after each call return with + * kStatus_ENET_TxFrameBusy. + */ status_t ENET_SendFrameMultiRing( ENET_Type *base, enet_handle_t *handle, uint8_t *data, uint32_t length, uint32_t ringId) { @@ -1769,14 +2006,19 @@ status_t ENET_SendFrameMultiRing( /* One transmit buffer is enough for one frame. */ if (handle->txBuffSizeAlign[ringId] >= length) { - /* Copy data to the buffer for uDMA transfer. */ +/* Copy data to the buffer for uDMA transfer. */ #if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET - address = MEMORY_ConvertMemoryMapAddress((uint32_t)curBuffDescrip->buffer,kMEMORY_DMA2Local); + address = MEMORY_ConvertMemoryMapAddress((uint32_t)curBuffDescrip->buffer, kMEMORY_DMA2Local); #else address = (uint32_t)curBuffDescrip->buffer; #endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */ memcpy((void *)address, data, length); +#if defined(FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL) && FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL + /* Add the cache clean maintain. */ + DCACHE_CleanByRange(address, length); +#endif /* FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL */ + /* Set data length. */ curBuffDescrip->length = length; #ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE @@ -1802,15 +2044,7 @@ status_t ENET_SendFrameMultiRing( { handle->txBdCurrent[ringId]++; } -#if defined(FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL) && FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL - /* Add the cache clean maintain. */ -#if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET - address = MEMORY_ConvertMemoryMapAddress((uint32_t)curBuffDescrip->buffer,kMEMORY_DMA2Local); -#else - address = (uint32_t)curBuffDescrip->buffer; -#endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */ - DCACHE_CleanByRange(address, length); -#endif /* FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL */ + /* Active the transmit buffer descriptor. */ ENET_ActiveSend(base, ringId); @@ -1844,53 +2078,40 @@ status_t ENET_SendFrameMultiRing( } /* update the size left to be transmit. */ sizeleft = length - len; +#if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET + address = MEMORY_ConvertMemoryMapAddress((uint32_t)curBuffDescrip->buffer, kMEMORY_DMA2Local); +#else + address = (uint32_t)curBuffDescrip->buffer; +#endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */ if (sizeleft > handle->txBuffSizeAlign[ringId]) { /* Data copy. */ -#if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET - address = MEMORY_ConvertMemoryMapAddress((uint32_t)curBuffDescrip->buffer,kMEMORY_DMA2Local); -#else - address = (uint32_t)curBuffDescrip->buffer; -#endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */ - memcpy((void*)address, data + len, handle->txBuffSizeAlign[ringId]); + memcpy((void *)address, data + len, handle->txBuffSizeAlign[ringId]); +#if defined(FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL) && FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL + /* Add the cache clean maintain. */ + DCACHE_CleanByRange(address, handle->txBuffSizeAlign[ringId]); +#endif /* FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL */ /* Data length update. */ curBuffDescrip->length = handle->txBuffSizeAlign[ringId]; len += handle->txBuffSizeAlign[ringId]; /* Sets the control flag. */ curBuffDescrip->control &= ~ENET_BUFFDESCRIPTOR_TX_LAST_MASK; curBuffDescrip->control |= ENET_BUFFDESCRIPTOR_TX_READY_MASK; -#if defined(FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL) && FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL - /* Add the cache clean maintain. */ -#if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET - address = MEMORY_ConvertMemoryMapAddress((uint32_t)curBuffDescrip->buffer,kMEMORY_DMA2Local); -#else - address = (uint32_t)curBuffDescrip->buffer; -#endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */ - DCACHE_CleanByRange(address, handle->txBuffSizeAlign[ringId]); -#endif /* FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL */ + /* Active the transmit buffer descriptor*/ ENET_ActiveSend(base, ringId); } else { -#if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET - address = MEMORY_ConvertMemoryMapAddress((uint32_t)curBuffDescrip->buffer,kMEMORY_DMA2Local); -#else - address = (uint32_t)curBuffDescrip->buffer; -#endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */ memcpy((void *)address, data + len, sizeleft); +#if defined(FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL) && FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL + /* Add the cache clean maintain. */ + DCACHE_CleanByRange(address, sizeleft); +#endif /* FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL */ curBuffDescrip->length = sizeleft; /* Set Last buffer wrap flag. */ curBuffDescrip->control |= ENET_BUFFDESCRIPTOR_TX_READY_MASK | ENET_BUFFDESCRIPTOR_TX_LAST_MASK; -#if defined(FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL) && FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL - /* Add the cache clean maintain. */ -#if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET - address = MEMORY_ConvertMemoryMapAddress((uint32_t)curBuffDescrip->buffer,kMEMORY_DMA2Local); -#else - address = (uint32_t)curBuffDescrip->buffer; -#endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */ - DCACHE_CleanByRange(address, sizeleft); -#endif /* FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL */ + /* Active the transmit buffer descriptor. */ ENET_ActiveSend(base, ringId); @@ -1899,9 +2120,6 @@ status_t ENET_SendFrameMultiRing( /* Get the current buffer descriptor address. */ curBuffDescrip = handle->txBdCurrent[ringId]; -#if defined(FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL) && FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL -/* Add the cache invalidate maintain. */ -#endif /* FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL */ } while (!(curBuffDescrip->control & ENET_BUFFDESCRIPTOR_TX_READY_MASK)); return kStatus_ENET_TxFrameBusy; @@ -1909,6 +2127,12 @@ status_t ENET_SendFrameMultiRing( } #endif /* FSL_FEATURE_ENET_QUEUE > 1 */ +/*! + * brief Adds the ENET device to a multicast group. + * + * param base ENET peripheral base address. + * param address The six-byte multicast group address which is provided by application. + */ void ENET_AddMulticastGroup(ENET_Type *base, uint8_t *address) { assert(address); @@ -1948,6 +2172,12 @@ void ENET_AddMulticastGroup(ENET_Type *base, uint8_t *address) } } +/*! + * brief Moves the ENET device from a multicast group. + * + * param base ENET peripheral base address. + * param address The six-byte multicast group address which is provided by application. + */ void ENET_LeaveMulticastGroup(ENET_Type *base, uint8_t *address) { assert(address); @@ -1988,6 +2218,19 @@ void ENET_LeaveMulticastGroup(ENET_Type *base, uint8_t *address) } #ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE +/*! + * brief Gets the ENET transmit frame statistics after the data send for single ring. + * + * This interface gets the error statistics of the transmit frame. + * Because the error information is reported by the uDMA after the data delivery, this interface + * should be called after the data transmit API. It is recommended to call this function on + * transmit interrupt handler. After calling the ENET_SendFrame, the + * transmit interrupt notifies the transmit completion. + * + * param handle The PTP handler pointer. This is the same handler pointer used in the ENET_Init. + * param eErrorStatic The error statistics structure pointer. + * return The execute status. + */ status_t ENET_GetTxErrAfterSendFrame(enet_handle_t *handle, enet_data_error_stats_t *eErrorStatic) { assert(handle); @@ -1999,8 +2242,8 @@ status_t ENET_GetTxErrAfterSendFrame(enet_handle_t *handle, enet_data_error_stat do { /* Get the current dirty transmit buffer descriptor. */ - control = handle->txBdDirtyStatic[0]->control; - controlExt = handle->txBdDirtyStatic[0]->controlExtend0; + control = handle->txBdDirtyStatic[0]->control; + controlExt = handle->txBdDirtyStatic[0]->controlExtend0; /* Get the control status data, If the buffer descriptor has not been processed break out. */ if (control & ENET_BUFFDESCRIPTOR_TX_READY_MASK) @@ -2053,9 +2296,23 @@ status_t ENET_GetTxErrAfterSendFrame(enet_handle_t *handle, enet_data_error_stat return kStatus_ENET_TxFrameFail; } -#if FSL_FEATURE_ENET_QUEUE > 1 -status_t ENET_GetTxErrAfterSendFrameMultiRing(enet_handle_t *handle, enet_data_error_stats_t *eErrorStatic, - uint32_t ringId) +#if FSL_FEATURE_ENET_QUEUE > 1 +/*! + * brief Gets the ENET transmit frame statistics after the data send for extended multi-ring. + * + * This interface gets the error statistics of the transmit frame. + * Because the error information is reported by the uDMA after the data delivery, this interface + * should be called after the data transmit API and shall be called by transmit interrupt handler. + * After calling the ENET_SendFrame, the transmit interrupt notifies the transmit completion. + * + * param handle The PTP handler pointer. This is the same handler pointer used in the ENET_Init. + * param eErrorStatic The error statistics structure pointer. + * param ringId The ring index. + * return The execute status. + */ +status_t ENET_GetTxErrAfterSendFrameMultiRing(enet_handle_t *handle, + enet_data_error_stats_t *eErrorStatic, + uint32_t ringId) { assert(handle); assert(eErrorStatic); @@ -2137,15 +2394,15 @@ static bool ENET_Ptp1588ParseFrame(const uint8_t *data, enet_ptp_time_data_t *pt * Add Double vlan tag check for receiving extended QIN vlan frame. */ if (*(uint16_t *)(buffer + ENET_PTP1588_ETHL2_PACKETTYPE_OFFSET) == (ENET_HTONS(ENET_8021QVLAN) #if defined(FSL_FEATUR_ENET_HAS_AVB) && FSL_FEATURE_HAS_AVB - || ENET_HTONS(ENET_8021QSVLAN) + || ENET_HTONS(ENET_8021QSVLAN) #endif /* FSL_FEATURE_ENET_HAS_AVB */ - )) + )) { buffer += ENET_FRAME_VLAN_TAGLEN; #if defined(FSL_FEATUR_ENET_HAS_AVB) && FSL_FEATURE_HAS_AVB if (*(uint16_t *)(buffer + ENET_PTP1588_ETHL2_PACKETTYPE_OFFSET) == ENET_HTONS(ENET_8021QVLAN) { - buffer += ENET_FRAME_VLAN_TAGLEN; + buffer += ENET_FRAME_VLAN_TAGLEN; } #endif /* FSL_FEATURE_ENET_HAS_AVB */ } @@ -2154,7 +2411,7 @@ static bool ENET_Ptp1588ParseFrame(const uint8_t *data, enet_ptp_time_data_t *pt switch (ENET_HTONS(ptpType)) { /* Ethernet layer 2. */ case ENET_ETHERNETL2: - if ((*(uint8_t *)(buffer + ENET_PTP1588_ETHL2_MSGTYPE_OFFSET) & 0xf) <= kENET_PtpEventMsgType) + if ((*(uint8_t *)(buffer + ENET_PTP1588_ETHL2_MSGTYPE_OFFSET) & 0x0F) <= kENET_PtpEventMsgType) { isPtpMsg = true; if (!isFastEnabled) @@ -2218,6 +2475,22 @@ static bool ENET_Ptp1588ParseFrame(const uint8_t *data, enet_ptp_time_data_t *pt return isPtpMsg; } +/*! + * brief Configures the ENET PTP IEEE 1588 feature with the basic configuration. + * The function sets the clock for PTP 1588 timer and enables + * time stamp interrupts and transmit interrupts for PTP 1588 features. + * This API should be called when the 1588 feature is enabled + * or the ENET_ENHANCEDBUFFERDESCRIPTOR_MODE is defined. + * ENET_Init should be called before calling this API. + * + * note The PTP 1588 time-stamp second increase though time-stamp interrupt handler + * and the transmit time-stamp store is done through transmit interrupt handler. + * As a result, the TS interrupt and TX interrupt are enabled when you call this API. + * + * param base ENET peripheral base address. + * param handle ENET handler pointer. + * param ptpConfig The ENET PTP1588 configuration. + */ void ENET_Ptp1588Configure(ENET_Type *base, enet_handle_t *handle, enet_ptp_config_t *ptpConfig) { assert(handle); @@ -2263,6 +2536,14 @@ void ENET_Ptp1588Configure(ENET_Type *base, enet_handle_t *handle, enet_ptp_conf EnableIRQ(s_enetTxIrqId[instance]); } +/*! + * brief Starts the ENET PTP 1588 Timer. + * This function is used to initialize the PTP timer. After the PTP starts, + * the PTP timer starts running. + * + * param base ENET peripheral base address. + * param ptpClkSrc The clock source of the PTP timer. + */ void ENET_Ptp1588StartTimer(ENET_Type *base, uint32_t ptpClkSrc) { /* Restart PTP 1588 timer, master clock. */ @@ -2275,6 +2556,13 @@ void ENET_Ptp1588StartTimer(ENET_Type *base, uint32_t ptpClkSrc) base->ATCR = ENET_ATCR_PEREN_MASK | ENET_ATCR_PINPER_MASK | ENET_ATCR_EN_MASK; } +/*! + * brief Gets the current ENET time from the PTP 1588 timer. + * + * param base ENET peripheral base address. + * param handle The ENET state pointer. This is the same state pointer used in the ENET_Init. + * param ptpTime The PTP timer structure. + */ void ENET_Ptp1588GetTimer(ENET_Type *base, enet_handle_t *handle, enet_ptp_time_t *ptpTime) { assert(handle); @@ -2304,6 +2592,13 @@ void ENET_Ptp1588GetTimer(ENET_Type *base, enet_handle_t *handle, enet_ptp_time_ EnableGlobalIRQ(primask); } +/*! + * brief Sets the ENET PTP 1588 timer to the assigned time. + * + * param base ENET peripheral base address. + * param handle The ENET state pointer. This is the same state pointer used in the ENET_Init. + * param ptpTime The timer to be set to the PTP timer. + */ void ENET_Ptp1588SetTimer(ENET_Type *base, enet_handle_t *handle, enet_ptp_time_t *ptpTime) { assert(handle); @@ -2322,6 +2617,17 @@ void ENET_Ptp1588SetTimer(ENET_Type *base, enet_handle_t *handle, enet_ptp_time_ EnableGlobalIRQ(primask); } +/*! + * brief Adjusts the ENET PTP 1588 timer. + * + * param base ENET peripheral base address. + * param corrIncrease The correction increment value. This value is added every time the correction + * timer expires. A value less than the PTP timer frequency(1/ptpClkSrc) slows down the timer, + * a value greater than the 1/ptpClkSrc speeds up the timer. + * param corrPeriod The PTP timer correction counter wrap-around value. This defines after how + * many timer clock the correction counter should be reset and trigger a correction + * increment on the timer. A value of 0 disables the correction counter and no correction occurs. + */ void ENET_Ptp1588AdjustTimer(ENET_Type *base, uint32_t corrIncrease, uint32_t corrPeriod) { /* Set correction for PTP timer increment. */ @@ -2478,15 +2784,16 @@ static status_t ENET_StoreTxFrameTime(ENET_Type *base, enet_handle_t *handle, ui return kStatus_ENET_TxFrameBusy; } - /* Parse the PTP message. */ +/* Parse the PTP message. */ #if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET - address = MEMORY_ConvertMemoryMapAddress((uint32_t)curBuffDescrip->buffer,kMEMORY_DMA2Local); + address = MEMORY_ConvertMemoryMapAddress((uint32_t)curBuffDescrip->buffer, kMEMORY_DMA2Local); #else address = (uint32_t)curBuffDescrip->buffer; #endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */ isPtpEventMessage = ENET_Ptp1588ParseFrame((uint8_t *)address, &ptpTimeData, false); if (isPtpEventMessage) { + /* Only store tx timestamp for ptp event message. */ do { /* Increase current buffer descriptor to the next one. */ @@ -2535,7 +2842,6 @@ static status_t ENET_StoreTxFrameTime(ENET_Type *base, enet_handle_t *handle, ui /* Get the current transmit buffer descriptor. */ curBuffDescrip = handle->txBdDirtyTime[ringId]; - /* Get the control status data, If the buffer descriptor has not been processed break out. */ if (curBuffDescrip->control & ENET_BUFFDESCRIPTOR_TX_READY_MASK) { @@ -2544,9 +2850,33 @@ static status_t ENET_StoreTxFrameTime(ENET_Type *base, enet_handle_t *handle, ui } while (handle->txBdDirtyTime[ringId] != handle->txBdCurrent[ringId]); return kStatus_ENET_TxFrameFail; } + else + { + /* Only increase current buffer descriptor to the next one. */ + if (handle->txBdDirtyTime[ringId]->control & ENET_BUFFDESCRIPTOR_TX_WRAP_MASK) + { + handle->txBdDirtyTime[ringId] = handle->txBdBase[ringId]; + } + else + { + handle->txBdDirtyTime[ringId]++; + } + } return kStatus_Success; } +/*! + * brief Gets the time stamp of the transmit frame. + * + * This function is used for PTP stack to get the timestamp captured by the ENET driver. + * + * param handle The ENET handler pointer.This is the same state pointer used in + * ENET_Init. + * param ptpTimeData The special PTP timestamp data for search the receive timestamp. + * retval kStatus_Success Get 1588 timestamp success. + * retval kStatus_ENET_PtpTsRingEmpty 1588 timestamp ring empty. + * retval kStatus_ENET_PtpTsRingFull 1588 timestamp ring full. + */ status_t ENET_GetTxFrameTime(enet_handle_t *handle, enet_ptp_time_data_t *ptpTimeData) { assert(handle); @@ -2555,6 +2885,18 @@ status_t ENET_GetTxFrameTime(enet_handle_t *handle, enet_ptp_time_data_t *ptpTim return ENET_Ptp1588SearchTimeRing(&handle->txPtpTsDataRing, ptpTimeData); } +/*! + * brief Gets the time stamp of the received frame. + * + * This function is used for PTP stack to get the timestamp captured by the ENET driver. + * + * param handle The ENET handler pointer.This is the same state pointer used in + * ENET_Init. + * param ptpTimeData The special PTP timestamp data for search the receive timestamp. + * retval kStatus_Success Get 1588 timestamp success. + * retval kStatus_ENET_PtpTsRingEmpty 1588 timestamp ring empty. + * retval kStatus_ENET_PtpTsRingFull 1588 timestamp ring full. + */ status_t ENET_GetRxFrameTime(enet_handle_t *handle, enet_ptp_time_data_t *ptpTimeData) { assert(handle); @@ -2564,6 +2906,21 @@ status_t ENET_GetRxFrameTime(enet_handle_t *handle, enet_ptp_time_data_t *ptpTim } #if defined(FSL_FEATURE_ENET_HAS_AVB) && FSL_FEATURE_ENET_HAS_AVB +/*! + * brief Sets the ENET AVB feature. + * + * ENET AVB feature configuration, set the Receive classification match and transmit + * bandwidth. This API is called when the AVB feature is required. + * + * Note: The AVB frames transmission scheme is credit-based tx scheme and it's only supported + * with the Enhanced buffer descriptors. so the AVB configuration should only done with + * Enhanced buffer descriptor. so when the AVB feature is required, please make sure the + * the "ENET_ENHANCEDBUFFERDESCRIPTOR_MODE" is defined. + * + * param base ENET peripheral base address. + * param handle ENET handler pointer. + * param config The ENET AVB feature configuration structure. + */ void ENET_AVBConfigure(ENET_Type *base, enet_handle_t *handle, const enet_avb_config_t *config) { assert(config); @@ -2589,8 +2946,20 @@ void ENET_AVBConfigure(ENET_Type *base, enet_handle_t *handle, const enet_avb_co #endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ #if FSL_FEATURE_ENET_QUEUE > 1 +/*! + * brief The transmit IRQ handler. + * + * param base ENET peripheral base address. + * param handle The ENET handler pointer. + */ void ENET_TransmitIRQHandler(ENET_Type *base, enet_handle_t *handle, uint32_t ringId) #else +/*! + * brief The transmit IRQ handler. + * + * param base ENET peripheral base address. + * param handle The ENET handler pointer. + */ void ENET_TransmitIRQHandler(ENET_Type *base, enet_handle_t *handle) #endif /* FSL_FEATURE_ENET_QUEUE > 1 */ { @@ -2642,8 +3011,20 @@ void ENET_TransmitIRQHandler(ENET_Type *base, enet_handle_t *handle) } #if FSL_FEATURE_ENET_QUEUE > 1 +/*! + * brief The receive IRQ handler. + * + * param base ENET peripheral base address. + * param handle The ENET handler pointer. + */ void ENET_ReceiveIRQHandler(ENET_Type *base, enet_handle_t *handle, uint32_t ringId) #else +/*! + * brief The receive IRQ handler. + * + * param base ENET peripheral base address. + * param handle The ENET handler pointer. + */ void ENET_ReceiveIRQHandler(ENET_Type *base, enet_handle_t *handle) #endif /* FSL_FEATURE_ENET_QUEUE > 1 */ { @@ -2682,6 +3063,12 @@ void ENET_ReceiveIRQHandler(ENET_Type *base, enet_handle_t *handle) } } +/*! + * brief Some special IRQ handler including the error, mii, wakeup irq handler. + * + * param base ENET peripheral base address. + * param handle The ENET handler pointer. + */ void ENET_ErrorIRQHandler(ENET_Type *base, enet_handle_t *handle) { assert(handle); @@ -2721,14 +3108,20 @@ void ENET_ErrorIRQHandler(ENET_Type *base, enet_handle_t *handle) #endif /* FSL_FEATURE_ENET_QUEUE > 1 */ } } - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ #if defined __CORTEX_M && (__CORTEX_M == 4U) __DSB(); #endif } #ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE +/*! + * brief The IEEE 1588 PTP time stamp interrupt handler. + * + * param base ENET peripheral base address. + * param handle The ENET state pointer. This is the same state pointer used in the ENET_Init. + */ void ENET_Ptp1588TimerIRQHandler(ENET_Type *base, enet_handle_t *handle) { assert(handle); @@ -2766,14 +3159,21 @@ void ENET_Ptp1588TimerIRQHandler(ENET_Type *base, enet_handle_t *handle) #endif /* FSL_FEATURE_ENET_QUEUE > 1 */ } } - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ #if defined __CORTEX_M && (__CORTEX_M == 4U) __DSB(); #endif } #endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ +/*! + * brief the common IRQ handler for the tx/rx/error etc irq handler. + * + * This is used for the combined tx/rx/error interrupt for single/mutli-ring (frame 0). + * + * param base ENET peripheral base address. + */ void ENET_CommonFrame0IRQHandler(ENET_Type *base) { uint32_t event = base->EIR; @@ -2805,14 +3205,21 @@ void ENET_CommonFrame0IRQHandler(ENET_Type *base) { s_enetErrIsr(base, s_ENETHandle[instance]); } - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ #if defined __CORTEX_M && (__CORTEX_M == 4U) __DSB(); #endif } #if FSL_FEATURE_ENET_QUEUE > 1 +/*! + * brief the common IRQ handler for the tx/rx irq handler. + * + * This is used for the combined tx/rx interrupt for multi-ring (frame 1). + * + * param base ENET peripheral base address. + */ void ENET_CommonFrame1IRQHandler(ENET_Type *base) { uint32_t event = base->EIR; @@ -2827,13 +3234,20 @@ void ENET_CommonFrame1IRQHandler(ENET_Type *base) { s_enetRxIsr(base, s_ENETHandle[instance], 1); } - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ #if defined __CORTEX_M && (__CORTEX_M == 4U) __DSB(); #endif } +/*! + * brief the common IRQ handler for the tx/rx irq handler. + * + * This is used for the combined tx/rx interrupt for multi-ring (frame 2). + * + * param base ENET peripheral base address. + */ void ENET_CommonFrame2IRQHandler(ENET_Type *base) { uint32_t event = base->EIR; @@ -2848,8 +3262,8 @@ void ENET_CommonFrame2IRQHandler(ENET_Type *base) { s_enetRxIsr(base, s_ENETHandle[instance], 2); } - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ #if defined __CORTEX_M && (__CORTEX_M == 4U) __DSB(); #endif @@ -2860,8 +3274,8 @@ void ENET_CommonFrame2IRQHandler(ENET_Type *base) void ENET_Transmit_IRQHandler(void) { s_enetTxIsr(ENET, s_ENETHandle[0]); - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ #if defined __CORTEX_M && (__CORTEX_M == 4U) __DSB(); #endif @@ -2870,8 +3284,8 @@ void ENET_Transmit_IRQHandler(void) void ENET_Receive_IRQHandler(void) { s_enetRxIsr(ENET, s_ENETHandle[0]); - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ #if defined __CORTEX_M && (__CORTEX_M == 4U) __DSB(); #endif @@ -2880,8 +3294,8 @@ void ENET_Receive_IRQHandler(void) void ENET_Error_IRQHandler(void) { s_enetErrIsr(ENET, s_ENETHandle[0]); - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ #if defined __CORTEX_M && (__CORTEX_M == 4U) __DSB(); #endif @@ -2890,8 +3304,8 @@ void ENET_Error_IRQHandler(void) void ENET_1588_Timer_IRQHandler(void) { s_enetTsIsr(ENET, s_ENETHandle[0]); - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ #if defined __CORTEX_M && (__CORTEX_M == 4U) __DSB(); #endif @@ -2904,9 +3318,9 @@ void ENET_DriverIRQHandler(void) exception return operation might vector to incorrect interrupt */ #if defined __CORTEX_M && (__CORTEX_M == 4U) __DSB(); -#endif - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ +#endif +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ #if defined __CORTEX_M && (__CORTEX_M == 4U) __DSB(); #endif @@ -2914,13 +3328,12 @@ void ENET_DriverIRQHandler(void) #endif - -#if defined(ENET1) +#if defined(ENET1) void ENET1_DriverIRQHandler(void) { ENET_CommonFrame0IRQHandler(ENET1); - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ #if defined __CORTEX_M && (__CORTEX_M == 4U) __DSB(); #endif @@ -2931,21 +3344,20 @@ void ENET1_DriverIRQHandler(void) void ENET2_DriverIRQHandler(void) { ENET_CommonFrame0IRQHandler(ENET2); - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ #if defined __CORTEX_M && (__CORTEX_M == 4U) __DSB(); #endif } #endif - -#if defined(CONNECTIVITY__ENET0) +#if defined(CONNECTIVITY__ENET0) void CONNECTIVITY_ENET0_FRAME0_EVENT_INT_DriverIRQHandler(void) { ENET_CommonFrame0IRQHandler(CONNECTIVITY__ENET0); - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ #if defined __CORTEX_M && (__CORTEX_M == 4U) __DSB(); #endif @@ -2954,8 +3366,8 @@ void CONNECTIVITY_ENET0_FRAME0_EVENT_INT_DriverIRQHandler(void) void CONNECTIVITY_ENET0_FRAME1_INT_DriverIRQHandler(void) { ENET_CommonFrame1IRQHandler(CONNECTIVITY__ENET0); - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ #if defined __CORTEX_M && (__CORTEX_M == 4U) __DSB(); #endif @@ -2963,8 +3375,8 @@ void CONNECTIVITY_ENET0_FRAME1_INT_DriverIRQHandler(void) void CONNECTIVITY_ENET0_FRAME2_INT_DriverIRQHandler(void) { ENET_CommonFrame2IRQHandler(CONNECTIVITY__ENET0); - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ #if defined __CORTEX_M && (__CORTEX_M == 4U) __DSB(); #endif @@ -2975,8 +3387,8 @@ void CONNECTIVITY_ENET0_FRAME2_INT_DriverIRQHandler(void) void CONNECTIVITY_ENET1_FRAME0_EVENT_INT_DriverIRQHandler(void) { ENET_CommonFrame0IRQHandler(CONNECTIVITY__ENET1); - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ #if defined __CORTEX_M && (__CORTEX_M == 4U) __DSB(); #endif @@ -2985,8 +3397,8 @@ void CONNECTIVITY_ENET1_FRAME0_EVENT_INT_DriverIRQHandler(void) void CONNECTIVITY_ENET1_FRAME1_INT_DriverIRQHandler(void) { ENET_CommonFrame1IRQHandler(CONNECTIVITY__ENET1); - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ #if defined __CORTEX_M && (__CORTEX_M == 4U) __DSB(); #endif @@ -2994,12 +3406,11 @@ void CONNECTIVITY_ENET1_FRAME1_INT_DriverIRQHandler(void) void CONNECTIVITY_ENET1_FRAME2_INT_DriverIRQHandler(void) { ENET_CommonFrame2IRQHandler(CONNECTIVITY__ENET1); - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ #if defined __CORTEX_M && (__CORTEX_M == 4U) __DSB(); #endif } #endif #endif - diff --git a/ext/hal/nxp/mcux/drivers/kinetis/fsl_enet.h b/ext/hal/nxp/mcux/drivers/kinetis/fsl_enet.h index d652e2bafb5..fc741d009ed 100644 --- a/ext/hal/nxp/mcux/drivers/kinetis/fsl_enet.h +++ b/ext/hal/nxp/mcux/drivers/kinetis/fsl_enet.h @@ -1,31 +1,9 @@ /* * Copyright (c) 2015 - 2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP + * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * SPDX-License-Identifier: BSD-3-Clause */ #ifndef _FSL_ENET_H_ #define _FSL_ENET_H_ @@ -46,7 +24,7 @@ /*! @name Driver version */ /*@{*/ /*! @brief Defines the driver version. */ -#define FSL_ENET_DRIVER_VERSION (MAKE_VERSION(2, 2, 1)) /*!< Version 2.2.1. */ +#define FSL_ENET_DRIVER_VERSION (MAKE_VERSION(2, 2, 3)) /*!< Version 2.2.3. */ /*@}*/ /*! @name ENET DESCRIPTOR QUEUE */ @@ -194,7 +172,7 @@ typedef enum _enet_mii_mode * * Notice: "kENET_MiiSpeed1000M" only supported when mii mode is "kENET_RgmiiMode". */ -typedef enum _enet_mii_speed +typedef enum _enet_mii_speed { kENET_MiiSpeed10M = 0U, /*!< Speed 10 Mbps. */ kENET_MiiSpeed100M = 1U, /*!< Speed 100 Mbps. */ @@ -204,21 +182,21 @@ typedef enum _enet_mii_speed } enet_mii_speed_t; /*! @brief Defines the half or full duplex for the MII data interface. */ -typedef enum _enet_mii_duplex +typedef enum _enet_mii_duplex { kENET_MiiHalfDuplex = 0U, /*!< Half duplex mode. */ kENET_MiiFullDuplex /*!< Full duplex mode. */ } enet_mii_duplex_t; /*! @brief Define the MII opcode for normal MDIO_CLAUSES_22 Frame. */ -typedef enum _enet_mii_write +typedef enum _enet_mii_write { kENET_MiiWriteNoCompliant = 0U, /*!< Write frame operation, but not MII-compliant. */ kENET_MiiWriteValidFrame /*!< Write frame operation for a valid MII management frame. */ } enet_mii_write_t; /*! @brief Defines the read operation for the MII management frame. */ -typedef enum _enet_mii_read +typedef enum _enet_mii_read { kENET_MiiReadValidFrame = 2U, /*!< Read frame operation for a valid MII management frame. */ kENET_MiiReadNoCompliant = 3U /*!< Read frame operation, but not MII-compliant. */ @@ -226,7 +204,8 @@ typedef enum _enet_mii_read #if defined(FSL_FEATURE_ENET_HAS_EXTEND_MDIO) && FSL_FEATURE_ENET_HAS_EXTEND_MDIO /*! @brief Define the MII opcode for extended MDIO_CLAUSES_45 Frame. */ -typedef enum _enet_mii_extend_opcode { +typedef enum _enet_mii_extend_opcode +{ kENET_MiiAddrWrite_C45 = 0U, /*!< Address Write operation. */ kENET_MiiWriteFrame_C45 = 1U, /*!< Write frame operation for a valid MII management frame. */ kENET_MiiReadFrame_C45 = 3U /*!< Read frame operation for a valid MII management frame. */ @@ -245,7 +224,7 @@ typedef enum _enet_mii_extend_opcode { * configure rxFifoFullThreshold and txFifoWatermark * in the enet_config_t. */ -typedef enum _enet_special_control_flag +typedef enum _enet_special_control_flag { kENET_ControlFlowControlEnable = 0x0001U, /*!< Enable ENET flow control: pause frame. */ kENET_ControlRxPayloadCheckEnable = 0x0002U, /*!< Enable ENET receive payload length check. */ @@ -268,7 +247,7 @@ typedef enum _enet_special_control_flag * members. Members usually map to interrupt enable bits in one or more * peripheral registers. */ -typedef enum _enet_interrupt_enable +typedef enum _enet_interrupt_enable { kENET_BabrInterrupt = ENET_EIR_BABR_MASK, /*!< Babbling receive error interrupt source */ kENET_BabtInterrupt = ENET_EIR_BABT_MASK, /*!< Babbling transmit error interrupt source */ @@ -302,7 +281,7 @@ typedef enum _enet_interrupt_enable } enet_interrupt_enable_t; /*! @brief Defines the common interrupt event for callback use. */ -typedef enum _enet_event +typedef enum _enet_event { kENET_RxEvent, /*!< Receive event. */ kENET_TxEvent, /*!< Transmit event. */ @@ -314,7 +293,7 @@ typedef enum _enet_event #if defined(FSL_FEATURE_ENET_HAS_AVB) && FSL_FEATURE_ENET_HAS_AVB /*! @brief Defines certain idle slope for bandwidth fraction. */ -typedef enum _enet_idle_slope +typedef enum _enet_idle_slope { kENET_IdleSlope1 = 1U, /*!< The bandwidth fraction is about 0.002. */ kENET_IdleSlope2 = 2U, /*!< The bandwidth fraction is about 0.003. */ @@ -339,7 +318,7 @@ typedef enum _enet_idle_slope #endif /* FSL_FEATURE_ENET_HAS_AVB */ /*! @brief Defines the transmit accelerator configuration. */ -typedef enum _enet_tx_accelerator +typedef enum _enet_tx_accelerator { kENET_TxAccelIsShift16Enabled = ENET_TACC_SHIFT16_MASK, /*!< Transmit FIFO shift-16. */ kENET_TxAccelIpCheckEnabled = ENET_TACC_IPCHK_MASK, /*!< Insert IP header checksum. */ @@ -347,7 +326,7 @@ typedef enum _enet_tx_accelerator } enet_tx_accelerator_t; /*! @brief Defines the receive accelerator configuration. */ -typedef enum _enet_rx_accelerator +typedef enum _enet_rx_accelerator { kENET_RxAccelPadRemoveEnabled = ENET_RACC_PADREM_MASK, /*!< Padding removal for short IP frames. */ kENET_RxAccelIpCheckEnabled = ENET_RACC_IPDIS_MASK, /*!< Discard with wrong IP header checksum. */ @@ -358,7 +337,7 @@ typedef enum _enet_rx_accelerator #ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE /*! @brief Defines the ENET PTP message related constant. */ -typedef enum _enet_ptp_event_type +typedef enum _enet_ptp_event_type { kENET_PtpEventMsgType = 3U, /*!< PTP event message type. */ kENET_PtpSrcPortIdLen = 10U, /*!< PTP message sequence id length. */ @@ -367,7 +346,7 @@ typedef enum _enet_ptp_event_type } enet_ptp_event_type_t; /*! @brief Defines the IEEE 1588 PTP timer channel numbers. */ -typedef enum _enet_ptp_timer_channel +typedef enum _enet_ptp_timer_channel { kENET_PtpTimerChannel1 = 0U, /*!< IEEE 1588 PTP timer Channel 1. */ kENET_PtpTimerChannel2, /*!< IEEE 1588 PTP timer Channel 2. */ @@ -440,7 +419,7 @@ typedef struct _enet_tx_bd_struct #endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ } enet_tx_bd_struct_t; -/*! @brief Defines the ENET data error statistic structure. */ +/*! @brief Defines the ENET data error statistics structure. */ typedef struct _enet_data_error_stats { uint32_t statsRxLenGreaterErr; /*!< Receive length greater than RCR[MAX_FL]. */ @@ -481,14 +460,16 @@ typedef struct _enet_data_error_stats */ typedef struct _enet_buffer_config { - uint16_t rxBdNumber; /*!< Receive buffer descriptor number. */ - uint16_t txBdNumber; /*!< Transmit buffer descriptor number. */ - uint32_t rxBuffSizeAlign; /*!< Aligned receive data buffer size. */ - uint32_t txBuffSizeAlign; /*!< Aligned transmit data buffer size. */ - volatile enet_rx_bd_struct_t *rxBdStartAddrAlign; /*!< Aligned receive buffer descriptor start address: should be non-cacheable. */ - volatile enet_tx_bd_struct_t *txBdStartAddrAlign; /*!< Aligned transmit buffer descriptor start address: should be non-cacheable. */ - uint8_t *rxBufferAlign; /*!< Receive data buffer start address. */ - uint8_t *txBufferAlign; /*!< Transmit data buffer start address. */ + uint16_t rxBdNumber; /*!< Receive buffer descriptor number. */ + uint16_t txBdNumber; /*!< Transmit buffer descriptor number. */ + uint32_t rxBuffSizeAlign; /*!< Aligned receive data buffer size. */ + uint32_t txBuffSizeAlign; /*!< Aligned transmit data buffer size. */ + volatile enet_rx_bd_struct_t + *rxBdStartAddrAlign; /*!< Aligned receive buffer descriptor start address: should be non-cacheable. */ + volatile enet_tx_bd_struct_t + *txBdStartAddrAlign; /*!< Aligned transmit buffer descriptor start address: should be non-cacheable. */ + uint8_t *rxBufferAlign; /*!< Receive data buffer start address. */ + uint8_t *txBufferAlign; /*!< Transmit data buffer start address. */ } enet_buffer_config_t; #ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE diff --git a/ext/hal/nxp/mcux/drivers/kinetis/fsl_ewm.c b/ext/hal/nxp/mcux/drivers/kinetis/fsl_ewm.c index f22eff941e9..28dda267466 100644 --- a/ext/hal/nxp/mcux/drivers/kinetis/fsl_ewm.c +++ b/ext/hal/nxp/mcux/drivers/kinetis/fsl_ewm.c @@ -1,39 +1,41 @@ /* * Copyright (c) 2015, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP + * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * SPDX-License-Identifier: BSD-3-Clause */ #include "fsl_ewm.h" +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.ewm" +#endif + /******************************************************************************* * Code ******************************************************************************/ +/*! + * brief Initializes the EWM peripheral. + * + * This function is used to initialize the EWM. After calling, the EWM + * runs immediately according to the configuration. + * Note that, except for the interrupt enable control bit, other control bits and registers are write once after a + * CPU reset. Modifying them more than once generates a bus transfer error. + * + * This is an example. + * code + * ewm_config_t config; + * EWM_GetDefaultConfig(&config); + * config.compareHighValue = 0xAAU; + * EWM_Init(ewm_base,&config); + * endcode + * + * param base EWM peripheral base address + * param config The configuration of the EWM +*/ void EWM_Init(EWM_Type *base, const ewm_config_t *config) { assert(config); @@ -41,7 +43,7 @@ void EWM_Init(EWM_Type *base, const ewm_config_t *config) uint32_t value = 0U; #if !((defined(FSL_FEATURE_SOC_PCC_COUNT) && FSL_FEATURE_SOC_PCC_COUNT) && \ - (defined(FSL_FEATURE_PCC_SUPPORT_EWM_CLOCK_REMOVE) && FSL_FEATURE_PCC_SUPPORT_EWM_CLOCK_REMOVE)) + (defined(FSL_FEATURE_PCC_SUPPORT_EWM_CLOCK_REMOVE) && FSL_FEATURE_PCC_SUPPORT_EWM_CLOCK_REMOVE)) #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) CLOCK_EnableClock(kCLOCK_Ewm0); #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ @@ -61,21 +63,50 @@ void EWM_Init(EWM_Type *base, const ewm_config_t *config) base->CTRL = value; } +/*! + * brief Deinitializes the EWM peripheral. + * + * This function is used to shut down the EWM. + * + * param base EWM peripheral base address +*/ void EWM_Deinit(EWM_Type *base) { EWM_DisableInterrupts(base, kEWM_InterruptEnable); #if !((defined(FSL_FEATURE_SOC_PCC_COUNT) && FSL_FEATURE_SOC_PCC_COUNT) && \ - (defined(FSL_FEATURE_PCC_SUPPORT_EWM_CLOCK_REMOVE) && FSL_FEATURE_PCC_SUPPORT_EWM_CLOCK_REMOVE)) + (defined(FSL_FEATURE_PCC_SUPPORT_EWM_CLOCK_REMOVE) && FSL_FEATURE_PCC_SUPPORT_EWM_CLOCK_REMOVE)) #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) CLOCK_DisableClock(kCLOCK_Ewm0); #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ #endif /* FSL_FEATURE_PCC_SUPPORT_EWM_CLOCK_REMOVE */ } +/*! + * brief Initializes the EWM configuration structure. + * + * This function initializes the EWM configuration structure to default values. The default + * values are as follows. + * code + * ewmConfig->enableEwm = true; + * ewmConfig->enableEwmInput = false; + * ewmConfig->setInputAssertLogic = false; + * ewmConfig->enableInterrupt = false; + * ewmConfig->ewm_lpo_clock_source_t = kEWM_LpoClockSource0; + * ewmConfig->prescaler = 0; + * ewmConfig->compareLowValue = 0; + * ewmConfig->compareHighValue = 0xFEU; + * endcode + * + * param config Pointer to the EWM configuration structure. + * see ewm_config_t + */ void EWM_GetDefaultConfig(ewm_config_t *config) { assert(config); + /* Initializes the configure structure to zero. */ + memset(config, 0, sizeof(*config)); + config->enableEwm = true; config->enableEwmInput = false; config->setInputAssertLogic = false; @@ -90,6 +121,13 @@ void EWM_GetDefaultConfig(ewm_config_t *config) config->compareHighValue = 0xFEU; } +/*! + * brief Services the EWM. + * + * This function resets the EWM counter to zero. + * + * param base EWM peripheral base address +*/ void EWM_Refresh(EWM_Type *base) { uint32_t primaskValue = 0U; diff --git a/ext/hal/nxp/mcux/drivers/kinetis/fsl_ewm.h b/ext/hal/nxp/mcux/drivers/kinetis/fsl_ewm.h index aa32ed3c713..15a9e61d252 100644 --- a/ext/hal/nxp/mcux/drivers/kinetis/fsl_ewm.h +++ b/ext/hal/nxp/mcux/drivers/kinetis/fsl_ewm.h @@ -1,31 +1,9 @@ /* * Copyright (c) 2015, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause */ #ifndef _FSL_EWM_H_ #define _FSL_EWM_H_ diff --git a/ext/hal/nxp/mcux/drivers/kinetis/fsl_flash.c b/ext/hal/nxp/mcux/drivers/kinetis/fsl_flash.c deleted file mode 100644 index f63e6c98145..00000000000 --- a/ext/hal/nxp/mcux/drivers/kinetis/fsl_flash.c +++ /dev/null @@ -1,3432 +0,0 @@ -/* - * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "fsl_flash.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! - * @name Misc utility defines - * @{ - */ -/*! @brief Alignment utility. */ -#ifndef ALIGN_DOWN -#define ALIGN_DOWN(x, a) ((x) & (uint32_t)(-((int32_t)(a)))) -#endif -#ifndef ALIGN_UP -#define ALIGN_UP(x, a) (-((int32_t)((uint32_t)(-((int32_t)(x))) & (uint32_t)(-((int32_t)(a)))))) -#endif - -/*! @brief Join bytes to word utility. */ -#define B1P4(b) (((uint32_t)(b)&0xFFU) << 24) -#define B1P3(b) (((uint32_t)(b)&0xFFU) << 16) -#define B1P2(b) (((uint32_t)(b)&0xFFU) << 8) -#define B1P1(b) ((uint32_t)(b)&0xFFU) -#define B2P3(b) (((uint32_t)(b)&0xFFFFU) << 16) -#define B2P2(b) (((uint32_t)(b)&0xFFFFU) << 8) -#define B2P1(b) ((uint32_t)(b)&0xFFFFU) -#define B3P2(b) (((uint32_t)(b)&0xFFFFFFU) << 8) -#define B3P1(b) ((uint32_t)(b)&0xFFFFFFU) -#define BYTES_JOIN_TO_WORD_1_3(x, y) (B1P4(x) | B3P1(y)) -#define BYTES_JOIN_TO_WORD_2_2(x, y) (B2P3(x) | B2P1(y)) -#define BYTES_JOIN_TO_WORD_3_1(x, y) (B3P2(x) | B1P1(y)) -#define BYTES_JOIN_TO_WORD_1_1_2(x, y, z) (B1P4(x) | B1P3(y) | B2P1(z)) -#define BYTES_JOIN_TO_WORD_1_2_1(x, y, z) (B1P4(x) | B2P2(y) | B1P1(z)) -#define BYTES_JOIN_TO_WORD_2_1_1(x, y, z) (B2P3(x) | B1P2(y) | B1P1(z)) -#define BYTES_JOIN_TO_WORD_1_1_1_1(x, y, z, w) (B1P4(x) | B1P3(y) | B1P2(z) | B1P1(w)) -/*@}*/ - -/*! - * @name Secondary flash configuration - * @{ - */ -/*! @brief Indicates whether the secondary flash has its own protection register in flash module. */ -#if defined(FSL_FEATURE_FLASH_HAS_MULTIPLE_FLASH) && defined(FTFE_FPROTS_PROTS_MASK) -#define FLASH_SSD_SECONDARY_FLASH_HAS_ITS_OWN_PROTECTION_REGISTER (1) -#else -#define FLASH_SSD_SECONDARY_FLASH_HAS_ITS_OWN_PROTECTION_REGISTER (0) -#endif - -/*! @brief Indicates whether the secondary flash has its own Execute-Only access register in flash module. */ -#if defined(FSL_FEATURE_FLASH_HAS_MULTIPLE_FLASH) && defined(FTFE_FACSSS_SGSIZE_S_MASK) -#define FLASH_SSD_SECONDARY_FLASH_HAS_ITS_OWN_ACCESS_REGISTER (1) -#else -#define FLASH_SSD_SECONDARY_FLASH_HAS_ITS_OWN_ACCESS_REGISTER (0) -#endif -/*@}*/ - -/*! - * @name Flash cache ands speculation control defines - * @{ - */ -#if defined(MCM_PLACR_CFCC_MASK) || defined(MCM_CPCR2_CCBC_MASK) -#define FLASH_CACHE_IS_CONTROLLED_BY_MCM (1) -#else -#define FLASH_CACHE_IS_CONTROLLED_BY_MCM (0) -#endif -#if defined(FMC_PFB0CR_CINV_WAY_MASK) || defined(FMC_PFB01CR_CINV_WAY_MASK) -#define FLASH_CACHE_IS_CONTROLLED_BY_FMC (1) -#else -#define FLASH_CACHE_IS_CONTROLLED_BY_FMC (0) -#endif -#if defined(MCM_PLACR_DFCS_MASK) -#define FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_MCM (1) -#else -#define FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_MCM (0) -#endif -#if defined(MSCM_OCMDR_OCM1_MASK) || defined(MSCM_OCMDR_OCMC1_MASK) -#define FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_MSCM (1) -#else -#define FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_MSCM (0) -#endif -#if defined(FMC_PFB0CR_S_INV_MASK) || defined(FMC_PFB0CR_S_B_INV_MASK) || defined(FMC_PFB01CR_S_INV_MASK) || \ - defined(FMC_PFB01CR_S_B_INV_MASK) -#define FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_FMC (1) -#else -#define FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_FMC (0) -#endif -/*@}*/ - -/*! @brief Data flash IFR map Field*/ -#if defined(FSL_FEATURE_FLASH_IS_FTFE) && FSL_FEATURE_FLASH_IS_FTFE -#define DFLASH_IFR_READRESOURCE_START_ADDRESS 0x8003F8U -#else /* FSL_FEATURE_FLASH_IS_FTFL == 1 or FSL_FEATURE_FLASH_IS_FTFA = =1 */ -#define DFLASH_IFR_READRESOURCE_START_ADDRESS 0x8000F8U -#endif - -/*! - * @name Reserved FlexNVM size (For a variety of purposes) defines - * @{ - */ -#define FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED 0xFFFFFFFFU -#define FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_RESERVED 0xFFFFU -/*@}*/ - -/*! - * @name Flash Program Once Field defines - * @{ - */ -#if defined(FSL_FEATURE_FLASH_IS_FTFA) && FSL_FEATURE_FLASH_IS_FTFA -/* FTFA parts(eg. K80, KL80, L5K) support both 4-bytes and 8-bytes unit size */ -#define FLASH_PROGRAM_ONCE_MIN_ID_8BYTES \ - 0x10U /* Minimum Index indcating one of Progam Once Fields which is accessed in 8-byte records */ -#define FLASH_PROGRAM_ONCE_MAX_ID_8BYTES \ - 0x13U /* Maximum Index indcating one of Progam Once Fields which is accessed in 8-byte records */ -#define FLASH_PROGRAM_ONCE_IS_4BYTES_UNIT_SUPPORT 1 -#define FLASH_PROGRAM_ONCE_IS_8BYTES_UNIT_SUPPORT 1 -#elif defined(FSL_FEATURE_FLASH_IS_FTFE) && FSL_FEATURE_FLASH_IS_FTFE -/* FTFE parts(eg. K65, KE18) only support 8-bytes unit size */ -#define FLASH_PROGRAM_ONCE_IS_4BYTES_UNIT_SUPPORT 0 -#define FLASH_PROGRAM_ONCE_IS_8BYTES_UNIT_SUPPORT 1 -#elif defined(FSL_FEATURE_FLASH_IS_FTFL) && FSL_FEATURE_FLASH_IS_FTFL -/* FTFL parts(eg. K20) only support 4-bytes unit size */ -#define FLASH_PROGRAM_ONCE_IS_4BYTES_UNIT_SUPPORT 1 -#define FLASH_PROGRAM_ONCE_IS_8BYTES_UNIT_SUPPORT 0 -#endif -/*@}*/ - -/*! - * @name Flash security status defines - * @{ - */ -#define FLASH_SECURITY_STATE_KEYEN 0x80U -#define FLASH_SECURITY_STATE_UNSECURED 0x02U -#define FLASH_NOT_SECURE 0x01U -#define FLASH_SECURE_BACKDOOR_ENABLED 0x02U -#define FLASH_SECURE_BACKDOOR_DISABLED 0x04U -/*@}*/ - -/*! - * @name Flash controller command numbers - * @{ - */ -#define FTFx_VERIFY_BLOCK 0x00U /*!< RD1BLK*/ -#define FTFx_VERIFY_SECTION 0x01U /*!< RD1SEC*/ -#define FTFx_PROGRAM_CHECK 0x02U /*!< PGMCHK*/ -#define FTFx_READ_RESOURCE 0x03U /*!< RDRSRC*/ -#define FTFx_PROGRAM_LONGWORD 0x06U /*!< PGM4*/ -#define FTFx_PROGRAM_PHRASE 0x07U /*!< PGM8*/ -#define FTFx_ERASE_BLOCK 0x08U /*!< ERSBLK*/ -#define FTFx_ERASE_SECTOR 0x09U /*!< ERSSCR*/ -#define FTFx_PROGRAM_SECTION 0x0BU /*!< PGMSEC*/ -#define FTFx_GENERATE_CRC 0x0CU /*!< CRCGEN*/ -#define FTFx_VERIFY_ALL_BLOCK 0x40U /*!< RD1ALL*/ -#define FTFx_READ_ONCE 0x41U /*!< RDONCE or RDINDEX*/ -#define FTFx_PROGRAM_ONCE 0x43U /*!< PGMONCE or PGMINDEX*/ -#define FTFx_ERASE_ALL_BLOCK 0x44U /*!< ERSALL*/ -#define FTFx_SECURITY_BY_PASS 0x45U /*!< VFYKEY*/ -#define FTFx_SWAP_CONTROL 0x46U /*!< SWAP*/ -#define FTFx_ERASE_ALL_BLOCK_UNSECURE 0x49U /*!< ERSALLU*/ -#define FTFx_VERIFY_ALL_EXECUTE_ONLY_SEGMENT 0x4AU /*!< RD1XA*/ -#define FTFx_ERASE_ALL_EXECUTE_ONLY_SEGMENT 0x4BU /*!< ERSXA*/ -#define FTFx_PROGRAM_PARTITION 0x80U /*!< PGMPART)*/ -#define FTFx_SET_FLEXRAM_FUNCTION 0x81U /*!< SETRAM*/ - /*@}*/ - -/*! - * @name Common flash register info defines - * @{ - */ -#if defined(FTFA) -#define FTFx FTFA -#define FTFx_BASE FTFA_BASE -#define FTFx_FSTAT_CCIF_MASK FTFA_FSTAT_CCIF_MASK -#define FTFx_FSTAT_RDCOLERR_MASK FTFA_FSTAT_RDCOLERR_MASK -#define FTFx_FSTAT_ACCERR_MASK FTFA_FSTAT_ACCERR_MASK -#define FTFx_FSTAT_FPVIOL_MASK FTFA_FSTAT_FPVIOL_MASK -#define FTFx_FSTAT_MGSTAT0_MASK FTFA_FSTAT_MGSTAT0_MASK -#define FTFx_FSEC_SEC_MASK FTFA_FSEC_SEC_MASK -#define FTFx_FSEC_KEYEN_MASK FTFA_FSEC_KEYEN_MASK -#if defined(FSL_FEATURE_FLASH_HAS_FLEX_RAM) && FSL_FEATURE_FLASH_HAS_FLEX_RAM -#define FTFx_FCNFG_RAMRDY_MASK FTFA_FCNFG_RAMRDY_MASK -#endif /* FSL_FEATURE_FLASH_HAS_FLEX_RAM */ -#if defined(FSL_FEATURE_FLASH_HAS_FLEX_NVM) && FSL_FEATURE_FLASH_HAS_FLEX_NVM -#define FTFx_FCNFG_EEERDY_MASK FTFA_FCNFG_EEERDY_MASK -#endif /* FSL_FEATURE_FLASH_HAS_FLEX_NVM */ -#elif defined(FTFE) -#define FTFx FTFE -#define FTFx_BASE FTFE_BASE -#define FTFx_FSTAT_CCIF_MASK FTFE_FSTAT_CCIF_MASK -#define FTFx_FSTAT_RDCOLERR_MASK FTFE_FSTAT_RDCOLERR_MASK -#define FTFx_FSTAT_ACCERR_MASK FTFE_FSTAT_ACCERR_MASK -#define FTFx_FSTAT_FPVIOL_MASK FTFE_FSTAT_FPVIOL_MASK -#define FTFx_FSTAT_MGSTAT0_MASK FTFE_FSTAT_MGSTAT0_MASK -#define FTFx_FSEC_SEC_MASK FTFE_FSEC_SEC_MASK -#define FTFx_FSEC_KEYEN_MASK FTFE_FSEC_KEYEN_MASK -#if defined(FSL_FEATURE_FLASH_HAS_FLEX_RAM) && FSL_FEATURE_FLASH_HAS_FLEX_RAM -#define FTFx_FCNFG_RAMRDY_MASK FTFE_FCNFG_RAMRDY_MASK -#endif /* FSL_FEATURE_FLASH_HAS_FLEX_RAM */ -#if defined(FSL_FEATURE_FLASH_HAS_FLEX_NVM) && FSL_FEATURE_FLASH_HAS_FLEX_NVM -#define FTFx_FCNFG_EEERDY_MASK FTFE_FCNFG_EEERDY_MASK -#endif /* FSL_FEATURE_FLASH_HAS_FLEX_NVM */ -#elif defined(FTFL) -#define FTFx FTFL -#define FTFx_BASE FTFL_BASE -#define FTFx_FSTAT_CCIF_MASK FTFL_FSTAT_CCIF_MASK -#define FTFx_FSTAT_RDCOLERR_MASK FTFL_FSTAT_RDCOLERR_MASK -#define FTFx_FSTAT_ACCERR_MASK FTFL_FSTAT_ACCERR_MASK -#define FTFx_FSTAT_FPVIOL_MASK FTFL_FSTAT_FPVIOL_MASK -#define FTFx_FSTAT_MGSTAT0_MASK FTFL_FSTAT_MGSTAT0_MASK -#define FTFx_FSEC_SEC_MASK FTFL_FSEC_SEC_MASK -#define FTFx_FSEC_KEYEN_MASK FTFL_FSEC_KEYEN_MASK -#if defined(FSL_FEATURE_FLASH_HAS_FLEX_RAM) && FSL_FEATURE_FLASH_HAS_FLEX_RAM -#define FTFx_FCNFG_RAMRDY_MASK FTFL_FCNFG_RAMRDY_MASK -#endif /* FSL_FEATURE_FLASH_HAS_FLEX_RAM */ -#if defined(FSL_FEATURE_FLASH_HAS_FLEX_NVM) && FSL_FEATURE_FLASH_HAS_FLEX_NVM -#define FTFx_FCNFG_EEERDY_MASK FTFL_FCNFG_EEERDY_MASK -#endif /* FSL_FEATURE_FLASH_HAS_FLEX_NVM */ -#else -#error "Unknown flash controller" -#endif -/*@}*/ - -/*! - * @name Common flash register access info defines - * @{ - */ -#define FTFx_FCCOB3_REG (FTFx->FCCOB3) -#define FTFx_FCCOB5_REG (FTFx->FCCOB5) -#define FTFx_FCCOB6_REG (FTFx->FCCOB6) -#define FTFx_FCCOB7_REG (FTFx->FCCOB7) - -#if defined(FTFA_FPROTH0_PROT_MASK) || defined(FTFE_FPROTH0_PROT_MASK) || defined(FTFL_FPROTH0_PROT_MASK) -#define FTFx_FPROT_HIGH_REG (FTFx->FPROTH3) -#define FTFx_FPROTH3_REG (FTFx->FPROTH3) -#define FTFx_FPROTH2_REG (FTFx->FPROTH2) -#define FTFx_FPROTH1_REG (FTFx->FPROTH1) -#define FTFx_FPROTH0_REG (FTFx->FPROTH0) -#endif - -#if defined(FTFA_FPROTL0_PROT_MASK) || defined(FTFE_FPROTL0_PROT_MASK) || defined(FTFL_FPROTL0_PROT_MASK) -#define FTFx_FPROT_LOW_REG (FTFx->FPROTL3) -#define FTFx_FPROTL3_REG (FTFx->FPROTL3) -#define FTFx_FPROTL2_REG (FTFx->FPROTL2) -#define FTFx_FPROTL1_REG (FTFx->FPROTL1) -#define FTFx_FPROTL0_REG (FTFx->FPROTL0) -#elif defined(FTFA_FPROT0_PROT_MASK) || defined(FTFE_FPROT0_PROT_MASK) || defined(FTFL_FPROT0_PROT_MASK) -#define FTFx_FPROT_LOW_REG (FTFx->FPROT3) -#define FTFx_FPROTL3_REG (FTFx->FPROT3) -#define FTFx_FPROTL2_REG (FTFx->FPROT2) -#define FTFx_FPROTL1_REG (FTFx->FPROT1) -#define FTFx_FPROTL0_REG (FTFx->FPROT0) -#endif - -#if FLASH_SSD_IS_SECONDARY_FLASH_ENABLED && FLASH_SSD_SECONDARY_FLASH_HAS_ITS_OWN_PROTECTION_REGISTER -#define FTFx_FPROTSH_REG (FTFx->FPROTSH) -#define FTFx_FPROTSL_REG (FTFx->FPROTSL) -#endif - -#define FTFx_XACCH3_REG (FTFx->XACCH3) -#define FTFx_XACCL3_REG (FTFx->XACCL3) - -#if FLASH_SSD_IS_SECONDARY_FLASH_ENABLED && FLASH_SSD_SECONDARY_FLASH_HAS_ITS_OWN_ACCESS_REGISTER -#define FTFx_XACCSH_REG (FTFx->XACCSH) -#define FTFx_XACCSL_REG (FTFx->XACCSL) -#endif -/*@}*/ - -/*! - * @brief Enumeration for access segment property. - */ -enum _flash_access_segment_property -{ - kFLASH_AccessSegmentBase = 256UL, -}; - -/*! - * @brief Enumeration for flash config area. - */ -enum _flash_config_area_range -{ - kFLASH_ConfigAreaStart = 0x400U, - kFLASH_ConfigAreaEnd = 0x40FU -}; - -/*! - * @name Flash register access type defines - * @{ - */ -#define FTFx_REG8_ACCESS_TYPE volatile uint8_t * -#define FTFx_REG32_ACCESS_TYPE volatile uint32_t * -/*@}*/ - -/*! - * @brief MCM cache register access info defines. - */ -#if defined(MCM_PLACR_CFCC_MASK) -#define MCM_CACHE_CLEAR_MASK MCM_PLACR_CFCC_MASK -#define MCM_CACHE_CLEAR_SHIFT MCM_PLACR_CFCC_SHIFT -#if defined(MCM) -#define MCM0_CACHE_REG MCM->PLACR -#elif defined(MCM0) -#define MCM0_CACHE_REG MCM0->PLACR -#endif -#if defined(MCM1) -#define MCM1_CACHE_REG MCM1->PLACR -#endif -#elif defined(MCM_CPCR2_CCBC_MASK) -#define MCM_CACHE_CLEAR_MASK MCM_CPCR2_CCBC_MASK -#define MCM_CACHE_CLEAR_SHIFT MCM_CPCR2_CCBC_SHIFT -#if defined(MCM) -#define MCM0_CACHE_REG MCM->CPCR2 -#elif defined(MCM0) -#define MCM0_CACHE_REG MCM0->CPCR2 -#endif -#if defined(MCM1) -#define MCM1_CACHE_REG MCM1->CPCR2 -#endif -#endif - -/*! - * @brief MSCM cache register access info defines. - */ -#if defined(MSCM_OCMDR_OCM1_MASK) -#define MSCM_SPECULATION_DISABLE_MASK MSCM_OCMDR_OCM1_MASK -#define MSCM_SPECULATION_DISABLE_SHIFT MSCM_OCMDR_OCM1_SHIFT -#define MSCM_SPECULATION_DISABLE(x) MSCM_OCMDR_OCM1(x) -#elif defined(MSCM_OCMDR_OCMC1_MASK) -#define MSCM_SPECULATION_DISABLE_MASK MSCM_OCMDR_OCMC1_MASK -#define MSCM_SPECULATION_DISABLE_SHIFT MSCM_OCMDR_OCMC1_SHIFT -#define MSCM_SPECULATION_DISABLE(x) MSCM_OCMDR_OCMC1(x) -#endif - -/*! - * @brief MSCM prefetch speculation defines. - */ -#define MSCM_OCMDR_OCMC1_DFDS_MASK (0x10U) -#define MSCM_OCMDR_OCMC1_DFCS_MASK (0x20U) - -#define MSCM_OCMDR_OCMC1_DFDS_SHIFT (4U) -#define MSCM_OCMDR_OCMC1_DFCS_SHIFT (5U) - -/*! - * @brief Flash size encoding rule. - */ -#define FLASH_MEMORY_SIZE_ENCODING_RULE_K1_2 (0x00U) -#define FLASH_MEMORY_SIZE_ENCODING_RULE_K3 (0x01U) - -#if defined(K32W042S1M2_M0P_SERIES) || defined(K32W042S1M2_M4_SERIES) -#define FLASH_MEMORY_SIZE_ENCODING_RULE (FLASH_MEMORY_SIZE_ENCODING_RULE_K3) -#else -#define FLASH_MEMORY_SIZE_ENCODING_RULE (FLASH_MEMORY_SIZE_ENCODING_RULE_K1_2) -#endif - -/******************************************************************************* - * Prototypes - ******************************************************************************/ - -#if FLASH_DRIVER_IS_FLASH_RESIDENT -/*! @brief Copy flash_run_command() to RAM*/ -static void copy_flash_run_command(uint32_t *flashRunCommand); -/*! @brief Copy flash_cache_clear_command() to RAM*/ -static void copy_flash_common_bit_operation(uint32_t *flashCommonBitOperation); -/*! @brief Check whether flash execute-in-ram functions are ready*/ -static status_t flash_check_execute_in_ram_function_info(flash_config_t *config); -#endif /* FLASH_DRIVER_IS_FLASH_RESIDENT */ - -/*! @brief Internal function Flash command sequence. Called by driver APIs only*/ -static status_t flash_command_sequence(flash_config_t *config); - -/*! @brief Perform the cache clear to the flash*/ -void flash_cache_clear(flash_config_t *config); - -/*! @brief Process the cache to the flash*/ -static void flash_cache_clear_process(flash_config_t *config, flash_cache_clear_process_t process); - -/*! @brief Validates the range and alignment of the given address range.*/ -static status_t flash_check_range(flash_config_t *config, - uint32_t startAddress, - uint32_t lengthInBytes, - uint32_t alignmentBaseline); -/*! @brief Gets the right address, sector and block size of current flash type which is indicated by address.*/ -static status_t flash_get_matched_operation_info(flash_config_t *config, - uint32_t address, - flash_operation_config_t *info); -/*! @brief Validates the given user key for flash erase APIs.*/ -static status_t flash_check_user_key(uint32_t key); - -#if FLASH_SSD_IS_FLEXNVM_ENABLED -/*! @brief Updates FlexNVM memory partition status according to data flash 0 IFR.*/ -static status_t flash_update_flexnvm_memory_partition_status(flash_config_t *config); -#endif /* FLASH_SSD_IS_FLEXNVM_ENABLED */ - -#if defined(FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD) && FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD -/*! @brief Validates the range of the given resource address.*/ -static status_t flash_check_resource_range(uint32_t start, - uint32_t lengthInBytes, - uint32_t alignmentBaseline, - flash_read_resource_option_t option); -#endif /* FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD */ - -#if defined(FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD) && FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD -/*! @brief Validates the gived swap control option.*/ -static status_t flash_check_swap_control_option(flash_swap_control_option_t option); -#endif /* FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD */ - -#if defined(FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP) && FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP -/*! @brief Validates the gived address to see if it is equal to swap indicator address in pflash swap IFR.*/ -static status_t flash_validate_swap_indicator_address(flash_config_t *config, uint32_t address); -#endif /* FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP */ - -#if defined(FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD) && FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD -/*! @brief Validates the gived flexram function option.*/ -static inline status_t flasn_check_flexram_function_option_range(flash_flexram_function_option_t option); -#endif /* FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD */ - -/*! @brief Gets the flash protection information (region size, region count).*/ -static status_t flash_get_protection_info(flash_config_t *config, flash_protection_config_t *info); - -#if defined(FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL) && FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL -/*! @brief Gets the flash Execute-Only access information (Segment size, Segment count).*/ -static status_t flash_get_access_info(flash_config_t *config, flash_access_config_t *info); -#endif /* FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL */ - -#if FLASH_CACHE_IS_CONTROLLED_BY_MCM -/*! @brief Performs the cache clear to the flash by MCM.*/ -void mcm_flash_cache_clear(flash_config_t *config); -#endif /* FLASH_CACHE_IS_CONTROLLED_BY_MCM */ - -#if FLASH_CACHE_IS_CONTROLLED_BY_FMC -/*! @brief Performs the cache clear to the flash by FMC.*/ -void fmc_flash_cache_clear(void); -#endif /* FLASH_CACHE_IS_CONTROLLED_BY_FMC */ - -#if FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_MSCM -/*! @brief Sets the prefetch speculation buffer to the flash by MSCM.*/ -void mscm_flash_prefetch_speculation_enable(bool enable); -#endif /* FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_MSCM */ - -#if FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_FMC -/*! @brief Performs the prefetch speculation buffer clear to the flash by FMC.*/ -void fmc_flash_prefetch_speculation_clear(void); -#endif /* FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_FMC */ - -/******************************************************************************* - * Variables - ******************************************************************************/ - -/*! @brief Access to FTFx->FCCOB */ -volatile uint32_t *const kFCCOBx = (volatile uint32_t *)&FTFx_FCCOB3_REG; -/*! @brief Access to FTFx->FPROT */ -volatile uint32_t *const kFPROTL = (volatile uint32_t *)&FTFx_FPROT_LOW_REG; -#if defined(FTFx_FPROT_HIGH_REG) -volatile uint32_t *const kFPROTH = (volatile uint32_t *)&FTFx_FPROT_HIGH_REG; -#endif - -#if FLASH_SSD_IS_SECONDARY_FLASH_ENABLED && FLASH_SSD_SECONDARY_FLASH_HAS_ITS_OWN_PROTECTION_REGISTER -volatile uint8_t *const kFPROTSL = (volatile uint8_t *)&FTFx_FPROTSL_REG; -volatile uint8_t *const kFPROTSH = (volatile uint8_t *)&FTFx_FPROTSH_REG; -#endif - -#if FLASH_DRIVER_IS_FLASH_RESIDENT -/*! @brief A function pointer used to point to relocated flash_run_command() */ -static void (*callFlashRunCommand)(FTFx_REG8_ACCESS_TYPE ftfx_fstat); -/*! @brief A function pointer used to point to relocated flash_common_bit_operation() */ -static void (*callFlashCommonBitOperation)(FTFx_REG32_ACCESS_TYPE base, - uint32_t bitMask, - uint32_t bitShift, - uint32_t bitValue); - -/*! - * @brief Position independent code of flash_run_command() - * - * Note1: The prototype of C function is shown as below: - * @code - * void flash_run_command(FTFx_REG8_ACCESS_TYPE ftfx_fstat) - * { - * // clear CCIF bit - * *ftfx_fstat = FTFx_FSTAT_CCIF_MASK; - * - * // Check CCIF bit of the flash status register, wait till it is set. - * // IP team indicates that this loop will always complete. - * while (!((*ftfx_fstat) & FTFx_FSTAT_CCIF_MASK)) - * { - * } - * } - * @endcode - * Note2: The binary code is generated by IAR 7.70.1 - */ -const static uint16_t s_flashRunCommandFunctionCode[] = { - 0x2180, /* MOVS R1, #128 ; 0x80 */ - 0x7001, /* STRB R1, [R0] */ - /* @4: */ - 0x7802, /* LDRB R2, [R0] */ - 0x420a, /* TST R2, R1 */ - 0xd0fc, /* BEQ.N @4 */ - 0x4770 /* BX LR */ -}; - -/*! - * @brief Position independent code of flash_common_bit_operation() - * - * Note1: The prototype of C function is shown as below: - * @code - * void flash_common_bit_operation(FTFx_REG32_ACCESS_TYPE base, uint32_t bitMask, uint32_t bitShift, uint32_t - * bitValue) - * { - * if (bitMask) - * { - * uint32_t value = (((uint32_t)(((uint32_t)(bitValue)) << bitShift)) & bitMask); - * *base = (*base & (~bitMask)) | value; - * } - * - * __ISB(); - * __DSB(); - * } - * @endcode - * Note2: The binary code is generated by IAR 7.70.1 - */ -const static uint16_t s_flashCommonBitOperationFunctionCode[] = { - 0xb510, /* PUSH {R4, LR} */ - 0x2900, /* CMP R1, #0 */ - 0xd005, /* BEQ.N @12 */ - 0x6804, /* LDR R4, [R0] */ - 0x438c, /* BICS R4, R4, R1 */ - 0x4093, /* LSLS R3, R3, R2 */ - 0x4019, /* ANDS R1, R1, R3 */ - 0x4321, /* ORRS R1, R1, R4 */ - 0x6001, /* STR R1, [R0] */ - /* @12: */ - 0xf3bf, 0x8f6f, /* ISB */ - 0xf3bf, 0x8f4f, /* DSB */ - 0xbd10 /* POP {R4, PC} */ -}; -#endif /* FLASH_DRIVER_IS_FLASH_RESIDENT */ - -#if (FLASH_DRIVER_IS_FLASH_RESIDENT && !FLASH_DRIVER_IS_EXPORTED) -/*! @brief A static buffer used to hold flash_run_command() */ -static uint32_t s_flashRunCommand[kFLASH_ExecuteInRamFunctionMaxSizeInWords]; -/*! @brief A static buffer used to hold flash_common_bit_operation() */ -static uint32_t s_flashCommonBitOperation[kFLASH_ExecuteInRamFunctionMaxSizeInWords]; -/*! @brief Flash execute-in-ram function information */ -static flash_execute_in_ram_function_config_t s_flashExecuteInRamFunctionInfo; -#endif - -/*! - * @brief Table of pflash sizes. - * - * The index into this table is the value of the SIM_FCFG1.PFSIZE bitfield. - * - * The values in this table have been right shifted 10 bits so that they will all fit within - * an 16-bit integer. To get the actual flash density, you must left shift the looked up value - * by 10 bits. - * - * Elements of this table have a value of 0 in cases where the PFSIZE bitfield value is - * reserved. - * - * Code to use the table: - * @code - * uint8_t pfsize = (SIM->FCFG1 & SIM_FCFG1_PFSIZE_MASK) >> SIM_FCFG1_PFSIZE_SHIFT; - * flashDensity = ((uint32_t)kPFlashDensities[pfsize]) << 10; - * @endcode - */ -#if (FLASH_MEMORY_SIZE_ENCODING_RULE == FLASH_MEMORY_SIZE_ENCODING_RULE_K1_2) -const uint16_t kPFlashDensities[] = { - 8, /* 0x0 - 8192, 8KB */ - 16, /* 0x1 - 16384, 16KB */ - 24, /* 0x2 - 24576, 24KB */ - 32, /* 0x3 - 32768, 32KB */ - 48, /* 0x4 - 49152, 48KB */ - 64, /* 0x5 - 65536, 64KB */ - 96, /* 0x6 - 98304, 96KB */ - 128, /* 0x7 - 131072, 128KB */ - 192, /* 0x8 - 196608, 192KB */ - 256, /* 0x9 - 262144, 256KB */ - 384, /* 0xa - 393216, 384KB */ - 512, /* 0xb - 524288, 512KB */ - 768, /* 0xc - 786432, 768KB */ - 1024, /* 0xd - 1048576, 1MB */ - 1536, /* 0xe - 1572864, 1.5MB */ - /* 2048, 0xf - 2097152, 2MB */ -}; -#elif(FLASH_MEMORY_SIZE_ENCODING_RULE == FLASH_MEMORY_SIZE_ENCODING_RULE_K3) -const uint16_t kPFlashDensities[] = { - 0, /* 0x0 - undefined */ - 0, /* 0x1 - undefined */ - 0, /* 0x2 - undefined */ - 0, /* 0x3 - undefined */ - 0, /* 0x4 - undefined */ - 0, /* 0x5 - undefined */ - 0, /* 0x6 - undefined */ - 0, /* 0x7 - undefined */ - 0, /* 0x8 - undefined */ - 0, /* 0x9 - undefined */ - 256, /* 0xa - 262144, 256KB */ - 0, /* 0xb - undefined */ - 1024, /* 0xc - 1048576, 1MB */ - 0, /* 0xd - undefined */ - 0, /* 0xe - undefined */ - 0, /* 0xf - undefined */ -}; -#endif - -/******************************************************************************* - * Code - ******************************************************************************/ - -status_t FLASH_Init(flash_config_t *config) -{ - if (config == NULL) - { - return kStatus_FLASH_InvalidArgument; - } - -#if FLASH_SSD_IS_SECONDARY_FLASH_ENABLED - if (config->FlashMemoryIndex == (uint8_t)kFLASH_MemoryIndexSecondaryFlash) - { -/* calculate the flash density from SIM_FCFG1.PFSIZE */ -#if defined(SIM_FCFG1_CORE1_PFSIZE_MASK) - uint32_t flashDensity; - uint8_t pfsize = (SIM->FCFG1 & SIM_FCFG1_CORE1_PFSIZE_MASK) >> SIM_FCFG1_CORE1_PFSIZE_SHIFT; - if (pfsize == 0xf) - { - flashDensity = FSL_FEATURE_FLASH_PFLASH_1_BLOCK_COUNT * FSL_FEATURE_FLASH_PFLASH_1_BLOCK_SIZE; - } - else - { - flashDensity = ((uint32_t)kPFlashDensities[pfsize]) << 10; - } - config->PFlashTotalSize = flashDensity; -#else - /* Unused code to solve MISRA-C issue*/ - config->PFlashBlockBase = kPFlashDensities[0]; - config->PFlashTotalSize = FSL_FEATURE_FLASH_PFLASH_1_BLOCK_COUNT * FSL_FEATURE_FLASH_PFLASH_1_BLOCK_SIZE; -#endif - config->PFlashBlockBase = FSL_FEATURE_FLASH_PFLASH_1_START_ADDRESS; - config->PFlashBlockCount = FSL_FEATURE_FLASH_PFLASH_1_BLOCK_COUNT; - config->PFlashSectorSize = FSL_FEATURE_FLASH_PFLASH_1_BLOCK_SECTOR_SIZE; - } - else -#endif /* FLASH_SSD_IS_SECONDARY_FLASH_ENABLED */ - { - uint32_t flashDensity; - -/* calculate the flash density from SIM_FCFG1.PFSIZE */ -#if defined(SIM_FCFG1_CORE0_PFSIZE_MASK) - uint8_t pfsize = (SIM->FCFG1 & SIM_FCFG1_CORE0_PFSIZE_MASK) >> SIM_FCFG1_CORE0_PFSIZE_SHIFT; -#elif defined(SIM_FCFG1_PFSIZE_MASK) - uint8_t pfsize = (SIM->FCFG1 & SIM_FCFG1_PFSIZE_MASK) >> SIM_FCFG1_PFSIZE_SHIFT; -#else -#error "Unknown flash size" -#endif - /* PFSIZE=0xf means that on customer parts the IFR was not correctly programmed. - * We just use the pre-defined flash size in feature file here to support pre-production parts */ - if (pfsize == 0xf) - { - flashDensity = FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT * FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE; - } - else - { - flashDensity = ((uint32_t)kPFlashDensities[pfsize]) << 10; - } - - /* fill out a few of the structure members */ - config->PFlashBlockBase = FSL_FEATURE_FLASH_PFLASH_START_ADDRESS; - config->PFlashTotalSize = flashDensity; - config->PFlashBlockCount = FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT; - config->PFlashSectorSize = FSL_FEATURE_FLASH_PFLASH_BLOCK_SECTOR_SIZE; - } - - { -#if defined(FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL) && FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL -#if FLASH_SSD_IS_SECONDARY_FLASH_ENABLED && FLASH_SSD_SECONDARY_FLASH_HAS_ITS_OWN_ACCESS_REGISTER - if (config->FlashMemoryIndex == (uint8_t)kFLASH_MemoryIndexSecondaryFlash) - { - config->PFlashAccessSegmentSize = kFLASH_AccessSegmentBase << FTFx->FACSSS; - config->PFlashAccessSegmentCount = FTFx->FACSNS; - } - else -#endif - { - config->PFlashAccessSegmentSize = kFLASH_AccessSegmentBase << FTFx->FACSS; - config->PFlashAccessSegmentCount = FTFx->FACSN; - } -#else - config->PFlashAccessSegmentSize = 0; - config->PFlashAccessSegmentCount = 0; -#endif /* FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL */ - } - - config->PFlashCallback = NULL; - -/* copy required flash commands to RAM */ -#if (FLASH_DRIVER_IS_FLASH_RESIDENT && !FLASH_DRIVER_IS_EXPORTED) - if (kStatus_FLASH_Success != flash_check_execute_in_ram_function_info(config)) - { - s_flashExecuteInRamFunctionInfo.activeFunctionCount = 0; - s_flashExecuteInRamFunctionInfo.flashRunCommand = s_flashRunCommand; - s_flashExecuteInRamFunctionInfo.flashCommonBitOperation = s_flashCommonBitOperation; - config->flashExecuteInRamFunctionInfo = &s_flashExecuteInRamFunctionInfo.activeFunctionCount; - FLASH_PrepareExecuteInRamFunctions(config); - } -#endif - - config->FlexRAMBlockBase = FSL_FEATURE_FLASH_FLEX_RAM_START_ADDRESS; - config->FlexRAMTotalSize = FSL_FEATURE_FLASH_FLEX_RAM_SIZE; - -#if FLASH_SSD_IS_FLEXNVM_ENABLED - { - status_t returnCode; - config->DFlashBlockBase = FSL_FEATURE_FLASH_FLEX_NVM_START_ADDRESS; - returnCode = flash_update_flexnvm_memory_partition_status(config); - if (returnCode != kStatus_FLASH_Success) - { - return returnCode; - } - } -#endif - - return kStatus_FLASH_Success; -} - -status_t FLASH_SetCallback(flash_config_t *config, flash_callback_t callback) -{ - if (config == NULL) - { - return kStatus_FLASH_InvalidArgument; - } - - config->PFlashCallback = callback; - - return kStatus_FLASH_Success; -} - -#if FLASH_DRIVER_IS_FLASH_RESIDENT -status_t FLASH_PrepareExecuteInRamFunctions(flash_config_t *config) -{ - flash_execute_in_ram_function_config_t *flashExecuteInRamFunctionInfo; - - if (config == NULL) - { - return kStatus_FLASH_InvalidArgument; - } - - flashExecuteInRamFunctionInfo = (flash_execute_in_ram_function_config_t *)config->flashExecuteInRamFunctionInfo; - - copy_flash_run_command(flashExecuteInRamFunctionInfo->flashRunCommand); - copy_flash_common_bit_operation(flashExecuteInRamFunctionInfo->flashCommonBitOperation); - flashExecuteInRamFunctionInfo->activeFunctionCount = kFLASH_ExecuteInRamFunctionTotalNum; - - return kStatus_FLASH_Success; -} -#endif /* FLASH_DRIVER_IS_FLASH_RESIDENT */ - -status_t FLASH_EraseAll(flash_config_t *config, uint32_t key) -{ - status_t returnCode; - - if (config == NULL) - { - return kStatus_FLASH_InvalidArgument; - } - - /* preparing passing parameter to erase all flash blocks */ - kFCCOBx[0] = BYTES_JOIN_TO_WORD_1_3(FTFx_ERASE_ALL_BLOCK, 0xFFFFFFU); - - /* Validate the user key */ - returnCode = flash_check_user_key(key); - if (returnCode) - { - return returnCode; - } - - flash_cache_clear_process(config, kFLASH_CacheClearProcessPre); - - /* calling flash command sequence function to execute the command */ - returnCode = flash_command_sequence(config); - - flash_cache_clear(config); - -#if FLASH_SSD_IS_FLEXNVM_ENABLED - /* Data flash IFR will be erased by erase all command, so we need to - * update FlexNVM memory partition status synchronously */ - if (returnCode == kStatus_FLASH_Success) - { - returnCode = flash_update_flexnvm_memory_partition_status(config); - } -#endif - - return returnCode; -} - -status_t FLASH_Erase(flash_config_t *config, uint32_t start, uint32_t lengthInBytes, uint32_t key) -{ - uint32_t sectorSize; - flash_operation_config_t flashOperationInfo; - uint32_t endAddress; /* storing end address */ - uint32_t numberOfSectors; /* number of sectors calculated by endAddress */ - status_t returnCode; - - flash_get_matched_operation_info(config, start, &flashOperationInfo); - - /* Check the supplied address range. */ - returnCode = flash_check_range(config, start, lengthInBytes, flashOperationInfo.sectorCmdAddressAligment); - if (returnCode) - { - return returnCode; - } - - /* Validate the user key */ - returnCode = flash_check_user_key(key); - if (returnCode) - { - return returnCode; - } - - start = flashOperationInfo.convertedAddress; - sectorSize = flashOperationInfo.activeSectorSize; - - /* calculating Flash end address */ - endAddress = start + lengthInBytes - 1; - - /* re-calculate the endAddress and align it to the start of the next sector - * which will be used in the comparison below */ - if (endAddress % sectorSize) - { - numberOfSectors = endAddress / sectorSize + 1; - endAddress = numberOfSectors * sectorSize - 1; - } - - flash_cache_clear_process(config, kFLASH_CacheClearProcessPre); - - /* the start address will increment to the next sector address - * until it reaches the endAdddress */ - while (start <= endAddress) - { - /* preparing passing parameter to erase a flash block */ - kFCCOBx[0] = BYTES_JOIN_TO_WORD_1_3(FTFx_ERASE_SECTOR, start); - - /* calling flash command sequence function to execute the command */ - returnCode = flash_command_sequence(config); - - /* calling flash callback function if it is available */ - if (config->PFlashCallback) - { - config->PFlashCallback(); - } - - /* checking the success of command execution */ - if (kStatus_FLASH_Success != returnCode) - { - break; - } - else - { - /* Increment to the next sector */ - start += sectorSize; - } - } - - flash_cache_clear(config); - - return (returnCode); -} - -#if defined(FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_UNSECURE_CMD) && FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_UNSECURE_CMD -status_t FLASH_EraseAllUnsecure(flash_config_t *config, uint32_t key) -{ - status_t returnCode; - - if (config == NULL) - { - return kStatus_FLASH_InvalidArgument; - } - - /* Prepare passing parameter to erase all flash blocks (unsecure). */ - kFCCOBx[0] = BYTES_JOIN_TO_WORD_1_3(FTFx_ERASE_ALL_BLOCK_UNSECURE, 0xFFFFFFU); - - /* Validate the user key */ - returnCode = flash_check_user_key(key); - if (returnCode) - { - return returnCode; - } - - flash_cache_clear_process(config, kFLASH_CacheClearProcessPre); - - /* calling flash command sequence function to execute the command */ - returnCode = flash_command_sequence(config); - - flash_cache_clear(config); - -#if FLASH_SSD_IS_FLEXNVM_ENABLED - /* Data flash IFR will be erased by erase all unsecure command, so we need to - * update FlexNVM memory partition status synchronously */ - if (returnCode == kStatus_FLASH_Success) - { - returnCode = flash_update_flexnvm_memory_partition_status(config); - } -#endif - - return returnCode; -} -#endif /* FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_UNSECURE_CMD */ - -status_t FLASH_EraseAllExecuteOnlySegments(flash_config_t *config, uint32_t key) -{ - status_t returnCode; - - if (config == NULL) - { - return kStatus_FLASH_InvalidArgument; - } - - /* preparing passing parameter to erase all execute-only segments - * 1st element for the FCCOB register */ - kFCCOBx[0] = BYTES_JOIN_TO_WORD_1_3(FTFx_ERASE_ALL_EXECUTE_ONLY_SEGMENT, 0xFFFFFFU); - - /* Validate the user key */ - returnCode = flash_check_user_key(key); - if (returnCode) - { - return returnCode; - } - - flash_cache_clear_process(config, kFLASH_CacheClearProcessPre); - - /* calling flash command sequence function to execute the command */ - returnCode = flash_command_sequence(config); - - flash_cache_clear(config); - - return returnCode; -} - -status_t FLASH_Program(flash_config_t *config, uint32_t start, uint32_t *src, uint32_t lengthInBytes) -{ - status_t returnCode; - flash_operation_config_t flashOperationInfo; - - if (src == NULL) - { - return kStatus_FLASH_InvalidArgument; - } - - flash_get_matched_operation_info(config, start, &flashOperationInfo); - - /* Check the supplied address range. */ - returnCode = flash_check_range(config, start, lengthInBytes, flashOperationInfo.blockWriteUnitSize); - if (returnCode) - { - return returnCode; - } - - start = flashOperationInfo.convertedAddress; - - flash_cache_clear_process(config, kFLASH_CacheClearProcessPre); - - while (lengthInBytes > 0) - { - /* preparing passing parameter to program the flash block */ - kFCCOBx[1] = *src++; - if (4 == flashOperationInfo.blockWriteUnitSize) - { - kFCCOBx[0] = BYTES_JOIN_TO_WORD_1_3(FTFx_PROGRAM_LONGWORD, start); - } - else if (8 == flashOperationInfo.blockWriteUnitSize) - { - kFCCOBx[2] = *src++; - kFCCOBx[0] = BYTES_JOIN_TO_WORD_1_3(FTFx_PROGRAM_PHRASE, start); - } - else - { - } - - /* calling flash command sequence function to execute the command */ - returnCode = flash_command_sequence(config); - - /* calling flash callback function if it is available */ - if (config->PFlashCallback) - { - config->PFlashCallback(); - } - - /* checking for the success of command execution */ - if (kStatus_FLASH_Success != returnCode) - { - break; - } - else - { - /* update start address for next iteration */ - start += flashOperationInfo.blockWriteUnitSize; - - /* update lengthInBytes for next iteration */ - lengthInBytes -= flashOperationInfo.blockWriteUnitSize; - } - } - - flash_cache_clear(config); - - return (returnCode); -} - -status_t FLASH_ProgramOnce(flash_config_t *config, uint32_t index, uint32_t *src, uint32_t lengthInBytes) -{ - status_t returnCode; - - if ((config == NULL) || (src == NULL)) - { - return kStatus_FLASH_InvalidArgument; - } - - /* pass paramters to FTFx */ - kFCCOBx[0] = BYTES_JOIN_TO_WORD_1_1_2(FTFx_PROGRAM_ONCE, index, 0xFFFFU); - - kFCCOBx[1] = *src; - -/* Note: Have to seperate the first index from the rest if it equals 0 - * to avoid a pointless comparison of unsigned int to 0 compiler warning */ -#if FLASH_PROGRAM_ONCE_IS_8BYTES_UNIT_SUPPORT -#if FLASH_PROGRAM_ONCE_IS_4BYTES_UNIT_SUPPORT - if (((index == FLASH_PROGRAM_ONCE_MIN_ID_8BYTES) || - /* Range check */ - ((index >= FLASH_PROGRAM_ONCE_MIN_ID_8BYTES + 1) && (index <= FLASH_PROGRAM_ONCE_MAX_ID_8BYTES))) && - (lengthInBytes == 8)) -#endif /* FLASH_PROGRAM_ONCE_IS_4BYTES_UNIT_SUPPORT */ - { - kFCCOBx[2] = *(src + 1); - } -#endif /* FLASH_PROGRAM_ONCE_IS_8BYTES_UNIT_SUPPORT */ - - flash_cache_clear_process(config, kFLASH_CacheClearProcessPre); - - /* calling flash command sequence function to execute the command */ - returnCode = flash_command_sequence(config); - - flash_cache_clear(config); - - return returnCode; -} - -#if defined(FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD) && FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD -status_t FLASH_ProgramSection(flash_config_t *config, uint32_t start, uint32_t *src, uint32_t lengthInBytes) -{ - status_t returnCode; - uint32_t sectorSize; - flash_operation_config_t flashOperationInfo; -#if defined(FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD) && FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD - bool needSwitchFlexRamMode = false; -#endif /* FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD */ - - if (src == NULL) - { - return kStatus_FLASH_InvalidArgument; - } - - flash_get_matched_operation_info(config, start, &flashOperationInfo); - - /* Check the supplied address range. */ - returnCode = flash_check_range(config, start, lengthInBytes, flashOperationInfo.sectionCmdAddressAligment); - if (returnCode) - { - return returnCode; - } - - start = flashOperationInfo.convertedAddress; - sectorSize = flashOperationInfo.activeSectorSize; - -#if defined(FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD) && FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD - /* Switch function of FlexRAM if needed */ - if (!(FTFx->FCNFG & FTFx_FCNFG_RAMRDY_MASK)) - { - needSwitchFlexRamMode = true; - - returnCode = FLASH_SetFlexramFunction(config, kFLASH_FlexramFunctionOptionAvailableAsRam); - if (returnCode != kStatus_FLASH_Success) - { - return kStatus_FLASH_SetFlexramAsRamError; - } - } -#endif /* FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD */ - - flash_cache_clear_process(config, kFLASH_CacheClearProcessPre); - - while (lengthInBytes > 0) - { - /* Make sure the write operation doesn't span two sectors */ - uint32_t endAddressOfCurrentSector = ALIGN_UP(start, sectorSize); - uint32_t lengthTobeProgrammedOfCurrentSector; - uint32_t currentOffset = 0; - - if (endAddressOfCurrentSector == start) - { - endAddressOfCurrentSector += sectorSize; - } - - if (lengthInBytes + start > endAddressOfCurrentSector) - { - lengthTobeProgrammedOfCurrentSector = endAddressOfCurrentSector - start; - } - else - { - lengthTobeProgrammedOfCurrentSector = lengthInBytes; - } - - /* Program Current Sector */ - while (lengthTobeProgrammedOfCurrentSector > 0) - { - /* Make sure the program size doesn't exceeds Acceleration RAM size */ - uint32_t programSizeOfCurrentPass; - uint32_t numberOfPhases; - - if (lengthTobeProgrammedOfCurrentSector > kFLASH_AccelerationRamSize) - { - programSizeOfCurrentPass = kFLASH_AccelerationRamSize; - } - else - { - programSizeOfCurrentPass = lengthTobeProgrammedOfCurrentSector; - } - - /* Copy data to FlexRAM */ - memcpy((void *)FSL_FEATURE_FLASH_FLEX_RAM_START_ADDRESS, src + currentOffset / 4, programSizeOfCurrentPass); - /* Set start address of the data to be programmed */ - kFCCOBx[0] = BYTES_JOIN_TO_WORD_1_3(FTFx_PROGRAM_SECTION, start + currentOffset); - /* Set program size in terms of FEATURE_FLASH_SECTION_CMD_ADDRESS_ALIGMENT */ - numberOfPhases = programSizeOfCurrentPass / flashOperationInfo.sectionCmdAddressAligment; - - kFCCOBx[1] = BYTES_JOIN_TO_WORD_2_2(numberOfPhases, 0xFFFFU); - - /* Peform command sequence */ - returnCode = flash_command_sequence(config); - - /* calling flash callback function if it is available */ - if (config->PFlashCallback) - { - config->PFlashCallback(); - } - - if (returnCode != kStatus_FLASH_Success) - { - flash_cache_clear(config); - return returnCode; - } - - lengthTobeProgrammedOfCurrentSector -= programSizeOfCurrentPass; - currentOffset += programSizeOfCurrentPass; - } - - src += currentOffset / 4; - start += currentOffset; - lengthInBytes -= currentOffset; - } - - flash_cache_clear(config); - -#if defined(FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD) && FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD - /* Restore function of FlexRAM if needed. */ - if (needSwitchFlexRamMode) - { - returnCode = FLASH_SetFlexramFunction(config, kFLASH_FlexramFunctionOptionAvailableForEeprom); - if (returnCode != kStatus_FLASH_Success) - { - return kStatus_FLASH_RecoverFlexramAsEepromError; - } - } -#endif /* FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD */ - - return returnCode; -} -#endif /* FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD */ - -#if FLASH_SSD_IS_FLEXNVM_ENABLED -status_t FLASH_EepromWrite(flash_config_t *config, uint32_t start, uint8_t *src, uint32_t lengthInBytes) -{ - status_t returnCode; - bool needSwitchFlexRamMode = false; - - if (config == NULL) - { - return kStatus_FLASH_InvalidArgument; - } - - /* Validates the range of the given address */ - if ((start < config->FlexRAMBlockBase) || - ((start + lengthInBytes) > (config->FlexRAMBlockBase + config->EEpromTotalSize))) - { - return kStatus_FLASH_AddressError; - } - - returnCode = kStatus_FLASH_Success; - - /* Switch function of FlexRAM if needed */ - if (!(FTFx->FCNFG & FTFx_FCNFG_EEERDY_MASK)) - { - needSwitchFlexRamMode = true; - - returnCode = FLASH_SetFlexramFunction(config, kFLASH_FlexramFunctionOptionAvailableForEeprom); - if (returnCode != kStatus_FLASH_Success) - { - return kStatus_FLASH_SetFlexramAsEepromError; - } - } - - /* Write data to FlexRAM when it is used as EEPROM emulator */ - while (lengthInBytes > 0) - { - if ((!(start & 0x3U)) && (lengthInBytes >= 4)) - { - *(uint32_t *)start = *(uint32_t *)src; - start += 4; - src += 4; - lengthInBytes -= 4; - } - else if ((!(start & 0x1U)) && (lengthInBytes >= 2)) - { - *(uint16_t *)start = *(uint16_t *)src; - start += 2; - src += 2; - lengthInBytes -= 2; - } - else - { - *(uint8_t *)start = *src; - start += 1; - src += 1; - lengthInBytes -= 1; - } - /* Wait till EEERDY bit is set */ - while (!(FTFx->FCNFG & FTFx_FCNFG_EEERDY_MASK)) - { - } - - /* Check for protection violation error */ - if (FTFx->FSTAT & FTFx_FSTAT_FPVIOL_MASK) - { - return kStatus_FLASH_ProtectionViolation; - } - } - - /* Switch function of FlexRAM if needed */ - if (needSwitchFlexRamMode) - { - returnCode = FLASH_SetFlexramFunction(config, kFLASH_FlexramFunctionOptionAvailableAsRam); - if (returnCode != kStatus_FLASH_Success) - { - return kStatus_FLASH_RecoverFlexramAsRamError; - } - } - - return returnCode; -} -#endif /* FLASH_SSD_IS_FLEXNVM_ENABLED */ - -#if defined(FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD) && FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD -status_t FLASH_ReadResource( - flash_config_t *config, uint32_t start, uint32_t *dst, uint32_t lengthInBytes, flash_read_resource_option_t option) -{ - status_t returnCode; - flash_operation_config_t flashOperationInfo; - - if ((config == NULL) || (dst == NULL)) - { - return kStatus_FLASH_InvalidArgument; - } - - flash_get_matched_operation_info(config, start, &flashOperationInfo); - - /* Check the supplied address range. */ - returnCode = - flash_check_resource_range(start, lengthInBytes, flashOperationInfo.resourceCmdAddressAligment, option); - if (returnCode != kStatus_FLASH_Success) - { - return returnCode; - } - - while (lengthInBytes > 0) - { - /* preparing passing parameter */ - kFCCOBx[0] = BYTES_JOIN_TO_WORD_1_3(FTFx_READ_RESOURCE, start); - if (flashOperationInfo.resourceCmdAddressAligment == 4) - { - kFCCOBx[2] = BYTES_JOIN_TO_WORD_1_3(option, 0xFFFFFFU); - } - else if (flashOperationInfo.resourceCmdAddressAligment == 8) - { - kFCCOBx[1] = BYTES_JOIN_TO_WORD_1_3(option, 0xFFFFFFU); - } - else - { - } - - /* calling flash command sequence function to execute the command */ - returnCode = flash_command_sequence(config); - - if (kStatus_FLASH_Success != returnCode) - { - break; - } - - /* fetch data */ - *dst++ = kFCCOBx[1]; - if (flashOperationInfo.resourceCmdAddressAligment == 8) - { - *dst++ = kFCCOBx[2]; - } - /* update start address for next iteration */ - start += flashOperationInfo.resourceCmdAddressAligment; - /* update lengthInBytes for next iteration */ - lengthInBytes -= flashOperationInfo.resourceCmdAddressAligment; - } - - return (returnCode); -} -#endif /* FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD */ - -status_t FLASH_ReadOnce(flash_config_t *config, uint32_t index, uint32_t *dst, uint32_t lengthInBytes) -{ - status_t returnCode; - - if ((config == NULL) || (dst == NULL)) - { - return kStatus_FLASH_InvalidArgument; - } - - /* pass paramters to FTFx */ - kFCCOBx[0] = BYTES_JOIN_TO_WORD_1_1_2(FTFx_READ_ONCE, index, 0xFFFFU); - - /* calling flash command sequence function to execute the command */ - returnCode = flash_command_sequence(config); - - if (kStatus_FLASH_Success == returnCode) - { - *dst = kFCCOBx[1]; -/* Note: Have to seperate the first index from the rest if it equals 0 - * to avoid a pointless comparison of unsigned int to 0 compiler warning */ -#if FLASH_PROGRAM_ONCE_IS_8BYTES_UNIT_SUPPORT -#if FLASH_PROGRAM_ONCE_IS_4BYTES_UNIT_SUPPORT - if (((index == FLASH_PROGRAM_ONCE_MIN_ID_8BYTES) || - /* Range check */ - ((index >= FLASH_PROGRAM_ONCE_MIN_ID_8BYTES + 1) && (index <= FLASH_PROGRAM_ONCE_MAX_ID_8BYTES))) && - (lengthInBytes == 8)) -#endif /* FLASH_PROGRAM_ONCE_IS_4BYTES_UNIT_SUPPORT */ - { - *(dst + 1) = kFCCOBx[2]; - } -#endif /* FLASH_PROGRAM_ONCE_IS_8BYTES_UNIT_SUPPORT */ - } - - return returnCode; -} - -status_t FLASH_GetSecurityState(flash_config_t *config, flash_security_state_t *state) -{ - /* store data read from flash register */ - uint8_t registerValue; - - if ((config == NULL) || (state == NULL)) - { - return kStatus_FLASH_InvalidArgument; - } - - /* Get flash security register value */ - registerValue = FTFx->FSEC; - - /* check the status of the flash security bits in the security register */ - if (FLASH_SECURITY_STATE_UNSECURED == (registerValue & FTFx_FSEC_SEC_MASK)) - { - /* Flash in unsecured state */ - *state = kFLASH_SecurityStateNotSecure; - } - else - { - /* Flash in secured state - * check for backdoor key security enable bit */ - if (FLASH_SECURITY_STATE_KEYEN == (registerValue & FTFx_FSEC_KEYEN_MASK)) - { - /* Backdoor key security enabled */ - *state = kFLASH_SecurityStateBackdoorEnabled; - } - else - { - /* Backdoor key security disabled */ - *state = kFLASH_SecurityStateBackdoorDisabled; - } - } - - return (kStatus_FLASH_Success); -} - -status_t FLASH_SecurityBypass(flash_config_t *config, const uint8_t *backdoorKey) -{ - uint8_t registerValue; /* registerValue */ - status_t returnCode; /* return code variable */ - - if ((config == NULL) || (backdoorKey == NULL)) - { - return kStatus_FLASH_InvalidArgument; - } - - /* set the default return code as kStatus_Success */ - returnCode = kStatus_FLASH_Success; - - /* Get flash security register value */ - registerValue = FTFx->FSEC; - - /* Check to see if flash is in secure state (any state other than 0x2) - * If not, then skip this since flash is not secure */ - if (0x02 != (registerValue & 0x03)) - { - /* preparing passing parameter to erase a flash block */ - kFCCOBx[0] = BYTES_JOIN_TO_WORD_1_3(FTFx_SECURITY_BY_PASS, 0xFFFFFFU); - kFCCOBx[1] = BYTES_JOIN_TO_WORD_1_1_1_1(backdoorKey[0], backdoorKey[1], backdoorKey[2], backdoorKey[3]); - kFCCOBx[2] = BYTES_JOIN_TO_WORD_1_1_1_1(backdoorKey[4], backdoorKey[5], backdoorKey[6], backdoorKey[7]); - - /* calling flash command sequence function to execute the command */ - returnCode = flash_command_sequence(config); - } - - return (returnCode); -} - -status_t FLASH_VerifyEraseAll(flash_config_t *config, flash_margin_value_t margin) -{ - if (config == NULL) - { - return kStatus_FLASH_InvalidArgument; - } - - /* preparing passing parameter to verify all block command */ - kFCCOBx[0] = BYTES_JOIN_TO_WORD_1_1_2(FTFx_VERIFY_ALL_BLOCK, margin, 0xFFFFU); - - /* calling flash command sequence function to execute the command */ - return flash_command_sequence(config); -} - -status_t FLASH_VerifyErase(flash_config_t *config, uint32_t start, uint32_t lengthInBytes, flash_margin_value_t margin) -{ - /* Check arguments. */ - uint32_t blockSize; - flash_operation_config_t flashOperationInfo; - uint32_t nextBlockStartAddress; - uint32_t remainingBytes; - status_t returnCode; - - flash_get_matched_operation_info(config, start, &flashOperationInfo); - - returnCode = flash_check_range(config, start, lengthInBytes, flashOperationInfo.sectionCmdAddressAligment); - if (returnCode) - { - return returnCode; - } - - flash_get_matched_operation_info(config, start, &flashOperationInfo); - start = flashOperationInfo.convertedAddress; - blockSize = flashOperationInfo.activeBlockSize; - - nextBlockStartAddress = ALIGN_UP(start, blockSize); - if (nextBlockStartAddress == start) - { - nextBlockStartAddress += blockSize; - } - - remainingBytes = lengthInBytes; - - while (remainingBytes) - { - uint32_t numberOfPhrases; - uint32_t verifyLength = nextBlockStartAddress - start; - if (verifyLength > remainingBytes) - { - verifyLength = remainingBytes; - } - - numberOfPhrases = verifyLength / flashOperationInfo.sectionCmdAddressAligment; - - /* Fill in verify section command parameters. */ - kFCCOBx[0] = BYTES_JOIN_TO_WORD_1_3(FTFx_VERIFY_SECTION, start); - kFCCOBx[1] = BYTES_JOIN_TO_WORD_2_1_1(numberOfPhrases, margin, 0xFFU); - - /* calling flash command sequence function to execute the command */ - returnCode = flash_command_sequence(config); - if (returnCode) - { - return returnCode; - } - - remainingBytes -= verifyLength; - start += verifyLength; - nextBlockStartAddress += blockSize; - } - - return kStatus_FLASH_Success; -} - -status_t FLASH_VerifyProgram(flash_config_t *config, - uint32_t start, - uint32_t lengthInBytes, - const uint32_t *expectedData, - flash_margin_value_t margin, - uint32_t *failedAddress, - uint32_t *failedData) -{ - status_t returnCode; - flash_operation_config_t flashOperationInfo; - - if (expectedData == NULL) - { - return kStatus_FLASH_InvalidArgument; - } - - flash_get_matched_operation_info(config, start, &flashOperationInfo); - - returnCode = flash_check_range(config, start, lengthInBytes, flashOperationInfo.checkCmdAddressAligment); - if (returnCode) - { - return returnCode; - } - - start = flashOperationInfo.convertedAddress; - - while (lengthInBytes) - { - /* preparing passing parameter to program check the flash block */ - kFCCOBx[0] = BYTES_JOIN_TO_WORD_1_3(FTFx_PROGRAM_CHECK, start); - kFCCOBx[1] = BYTES_JOIN_TO_WORD_1_3(margin, 0xFFFFFFU); - kFCCOBx[2] = *expectedData; - - /* calling flash command sequence function to execute the command */ - returnCode = flash_command_sequence(config); - - /* checking for the success of command execution */ - if (kStatus_FLASH_Success != returnCode) - { - if (failedAddress) - { - *failedAddress = start; - } - if (failedData) - { - *failedData = 0; - } - break; - } - - lengthInBytes -= flashOperationInfo.checkCmdAddressAligment; - expectedData += flashOperationInfo.checkCmdAddressAligment / sizeof(*expectedData); - start += flashOperationInfo.checkCmdAddressAligment; - } - - return (returnCode); -} - -status_t FLASH_VerifyEraseAllExecuteOnlySegments(flash_config_t *config, flash_margin_value_t margin) -{ - if (config == NULL) - { - return kStatus_FLASH_InvalidArgument; - } - - /* preparing passing parameter to verify erase all execute-only segments command */ - kFCCOBx[0] = BYTES_JOIN_TO_WORD_1_1_2(FTFx_VERIFY_ALL_EXECUTE_ONLY_SEGMENT, margin, 0xFFFFU); - - /* calling flash command sequence function to execute the command */ - return flash_command_sequence(config); -} - -status_t FLASH_IsProtected(flash_config_t *config, - uint32_t start, - uint32_t lengthInBytes, - flash_protection_state_t *protection_state) -{ - uint32_t endAddress; /* end address for protection check */ - uint32_t regionCheckedCounter; /* increments each time the flash address was checked for - * protection status */ - uint32_t regionCounter; /* incrementing variable used to increment through the flash - * protection regions */ - uint32_t protectStatusCounter; /* increments each time a flash region was detected as protected */ - - uint8_t flashRegionProtectStatus[FSL_FEATURE_FLASH_PFLASH_PROTECTION_REGION_COUNT]; /* array of the protection - * status for each - * protection region */ - uint32_t flashRegionAddress[FSL_FEATURE_FLASH_PFLASH_PROTECTION_REGION_COUNT + - 1]; /* array of the start addresses for each flash - * protection region. Note this is REGION_COUNT+1 - * due to requiring the next start address after - * the end of flash for loop-check purposes below */ - flash_protection_config_t flashProtectionInfo; /* flash protection information */ - status_t returnCode; - - if (protection_state == NULL) - { - return kStatus_FLASH_InvalidArgument; - } - - /* Check the supplied address range. */ - returnCode = flash_check_range(config, start, lengthInBytes, FSL_FEATURE_FLASH_PFLASH_BLOCK_WRITE_UNIT_SIZE); - if (returnCode) - { - return returnCode; - } - - /* Get necessary flash protection information. */ - returnCode = flash_get_protection_info(config, &flashProtectionInfo); - if (returnCode) - { - return returnCode; - } - - /* calculating Flash end address */ - endAddress = start + lengthInBytes; - - /* populate the flashRegionAddress array with the start address of each flash region */ - regionCounter = 0; /* make sure regionCounter is initialized to 0 first */ - - /* populate up to 33rd element of array, this is the next address after end of flash array */ - while (regionCounter <= flashProtectionInfo.regionCount) - { - flashRegionAddress[regionCounter] = - flashProtectionInfo.regionBase + flashProtectionInfo.regionSize * regionCounter; - regionCounter++; - } - - /* populate flashRegionProtectStatus array with status information - * Protection status for each region is stored in the FPROT[3:0] registers - * Each bit represents one region of flash - * 4 registers * 8-bits-per-register = 32-bits (32-regions) - * The convention is: - * FPROT3[bit 0] is the first protection region (start of flash memory) - * FPROT0[bit 7] is the last protection region (end of flash memory) - * regionCounter is used to determine which FPROT[3:0] register to check for protection status - * Note: FPROT=1 means NOT protected, FPROT=0 means protected */ - regionCounter = 0; /* make sure regionCounter is initialized to 0 first */ - while (regionCounter < flashProtectionInfo.regionCount) - { -#if FLASH_SSD_IS_SECONDARY_FLASH_ENABLED && FLASH_SSD_SECONDARY_FLASH_HAS_ITS_OWN_PROTECTION_REGISTER - if (config->FlashMemoryIndex == (uint8_t)kFLASH_MemoryIndexSecondaryFlash) - { - if (regionCounter < 8) - { - flashRegionProtectStatus[regionCounter] = (FTFx_FPROTSL_REG >> regionCounter) & (0x01u); - } - else if ((regionCounter >= 8) && (regionCounter < 16)) - { - flashRegionProtectStatus[regionCounter] = (FTFx_FPROTSH_REG >> (regionCounter - 8)) & (0x01u); - } - else - { - break; - } - } - else -#endif - { - /* Note: So far protection region count may be 16/20/24/32/64 */ - if (regionCounter < 8) - { - flashRegionProtectStatus[regionCounter] = (FTFx_FPROTL3_REG >> regionCounter) & (0x01u); - } - else if ((regionCounter >= 8) && (regionCounter < 16)) - { - flashRegionProtectStatus[regionCounter] = (FTFx_FPROTL2_REG >> (regionCounter - 8)) & (0x01u); - } -#if defined(FSL_FEATURE_FLASH_PFLASH_PROTECTION_REGION_COUNT) && (FSL_FEATURE_FLASH_PFLASH_PROTECTION_REGION_COUNT > 16) -#if (FSL_FEATURE_FLASH_PFLASH_PROTECTION_REGION_COUNT == 20) - else if ((regionCounter >= 16) && (regionCounter < 20)) - { - flashRegionProtectStatus[regionCounter] = (FTFx_FPROTL1_REG >> (regionCounter - 16)) & (0x01u); - } -#else - else if ((regionCounter >= 16) && (regionCounter < 24)) - { - flashRegionProtectStatus[regionCounter] = (FTFx_FPROTL1_REG >> (regionCounter - 16)) & (0x01u); - } -#endif /* (FSL_FEATURE_FLASH_PFLASH_PROTECTION_REGION_COUNT == 20) */ -#endif -#if defined(FSL_FEATURE_FLASH_PFLASH_PROTECTION_REGION_COUNT) && (FSL_FEATURE_FLASH_PFLASH_PROTECTION_REGION_COUNT > 24) - else if ((regionCounter >= 24) && (regionCounter < 32)) - { - flashRegionProtectStatus[regionCounter] = (FTFx_FPROTL0_REG >> (regionCounter - 24)) & (0x01u); - } -#endif -#if defined(FSL_FEATURE_FLASH_PFLASH_PROTECTION_REGION_COUNT) && \ - (FSL_FEATURE_FLASH_PFLASH_PROTECTION_REGION_COUNT == 64) - else if (regionCounter < 40) - { - flashRegionProtectStatus[regionCounter] = (FTFx_FPROTH3_REG >> (regionCounter - 32)) & (0x01u); - } - else if (regionCounter < 48) - { - flashRegionProtectStatus[regionCounter] = (FTFx_FPROTH2_REG >> (regionCounter - 40)) & (0x01u); - } - else if (regionCounter < 56) - { - flashRegionProtectStatus[regionCounter] = (FTFx_FPROTH1_REG >> (regionCounter - 48)) & (0x01u); - } - else if (regionCounter < 64) - { - flashRegionProtectStatus[regionCounter] = (FTFx_FPROTH0_REG >> (regionCounter - 56)) & (0x01u); - } -#endif - else - { - break; - } - } - - regionCounter++; - } - - /* loop through the flash regions and check - * desired flash address range for protection status - * loop stops when it is detected that start has exceeded the endAddress */ - regionCounter = 0; /* make sure regionCounter is initialized to 0 first */ - regionCheckedCounter = 0; - protectStatusCounter = 0; /* make sure protectStatusCounter is initialized to 0 first */ - while (start < endAddress) - { - /* check to see if the address falls within this protection region - * Note that if the entire flash is to be checked, the last protection - * region checked would consist of the last protection start address and - * the start address following the end of flash */ - if ((start >= flashRegionAddress[regionCounter]) && (start < flashRegionAddress[regionCounter + 1])) - { - /* increment regionCheckedCounter to indicate this region was checked */ - regionCheckedCounter++; - - /* check the protection status of this region - * Note: FPROT=1 means NOT protected, FPROT=0 means protected */ - if (!flashRegionProtectStatus[regionCounter]) - { - /* increment protectStatusCounter to indicate this region is protected */ - protectStatusCounter++; - } - start += flashProtectionInfo.regionSize; /* increment to an address within the next region */ - } - regionCounter++; /* increment regionCounter to check for the next flash protection region */ - } - - /* if protectStatusCounter == 0, then no region of the desired flash region is protected */ - if (protectStatusCounter == 0) - { - *protection_state = kFLASH_ProtectionStateUnprotected; - } - /* if protectStatusCounter == regionCheckedCounter, then each region checked was protected */ - else if (protectStatusCounter == regionCheckedCounter) - { - *protection_state = kFLASH_ProtectionStateProtected; - } - /* if protectStatusCounter != regionCheckedCounter, then protection status is mixed - * In other words, some regions are protected while others are unprotected */ - else - { - *protection_state = kFLASH_ProtectionStateMixed; - } - - return (returnCode); -} - -status_t FLASH_IsExecuteOnly(flash_config_t *config, - uint32_t start, - uint32_t lengthInBytes, - flash_execute_only_access_state_t *access_state) -{ -#if defined(FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL) && FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL - flash_access_config_t flashAccessInfo; /* flash Execute-Only information */ -#endif /* FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL */ - status_t returnCode; - - if (access_state == NULL) - { - return kStatus_FLASH_InvalidArgument; - } - - /* Check the supplied address range. */ - returnCode = flash_check_range(config, start, lengthInBytes, FSL_FEATURE_FLASH_PFLASH_BLOCK_WRITE_UNIT_SIZE); - if (returnCode) - { - return returnCode; - } - -#if defined(FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL) && FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL - /* Get necessary flash Execute-Only information. */ - returnCode = flash_get_access_info(config, &flashAccessInfo); - if (returnCode) - { - return returnCode; - } - - { - uint32_t executeOnlySegmentCounter = 0; - - /* calculating end address */ - uint32_t endAddress = start + lengthInBytes; - - /* Aligning start address and end address */ - uint32_t alignedStartAddress = ALIGN_DOWN(start, flashAccessInfo.SegmentSize); - uint32_t alignedEndAddress = ALIGN_UP(endAddress, flashAccessInfo.SegmentSize); - - uint32_t segmentIndex = 0; - uint32_t maxSupportedExecuteOnlySegmentCount = - (alignedEndAddress - alignedStartAddress) / flashAccessInfo.SegmentSize; - - while (start < endAddress) - { - uint32_t xacc; - - segmentIndex = (start - flashAccessInfo.SegmentBase) / flashAccessInfo.SegmentSize; - -#if FLASH_SSD_IS_SECONDARY_FLASH_ENABLED && FLASH_SSD_SECONDARY_FLASH_HAS_ITS_OWN_ACCESS_REGISTER - if (config->FlashMemoryIndex == (uint8_t)kFLASH_MemoryIndexSecondaryFlash) - { - /* For secondary flash, The two XACCS registers allow up to 16 restricted segments of equal memory size. - */ - if (segmentIndex < 8) - { - xacc = *(const volatile uint8_t *)&FTFx_XACCSL_REG; - } - else if (segmentIndex < flashAccessInfo.SegmentCount) - { - xacc = *(const volatile uint8_t *)&FTFx_XACCSH_REG; - segmentIndex -= 8; - } - else - { - break; - } - } - else -#endif - { - /* For primary flash, The eight XACC registers allow up to 64 restricted segments of equal memory size. - */ - if (segmentIndex < 32) - { - xacc = *(const volatile uint32_t *)&FTFx_XACCL3_REG; - } - else if (segmentIndex < flashAccessInfo.SegmentCount) - { - xacc = *(const volatile uint32_t *)&FTFx_XACCH3_REG; - segmentIndex -= 32; - } - else - { - break; - } - } - - /* Determine if this address range is in a execute-only protection flash segment. */ - if ((~xacc) & (1u << segmentIndex)) - { - executeOnlySegmentCounter++; - } - - start += flashAccessInfo.SegmentSize; - } - - if (executeOnlySegmentCounter < 1u) - { - *access_state = kFLASH_AccessStateUnLimited; - } - else if (executeOnlySegmentCounter < maxSupportedExecuteOnlySegmentCount) - { - *access_state = kFLASH_AccessStateMixed; - } - else - { - *access_state = kFLASH_AccessStateExecuteOnly; - } - } -#else - *access_state = kFLASH_AccessStateUnLimited; -#endif /* FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL */ - - return (returnCode); -} - -status_t FLASH_GetProperty(flash_config_t *config, flash_property_tag_t whichProperty, uint32_t *value) -{ - if ((config == NULL) || (value == NULL)) - { - return kStatus_FLASH_InvalidArgument; - } - - switch (whichProperty) - { - case kFLASH_PropertyPflashSectorSize: - *value = config->PFlashSectorSize; - break; - - case kFLASH_PropertyPflashTotalSize: - *value = config->PFlashTotalSize; - break; - - case kFLASH_PropertyPflashBlockSize: - *value = config->PFlashTotalSize / FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT; - break; - - case kFLASH_PropertyPflashBlockCount: - *value = (uint32_t)config->PFlashBlockCount; - break; - - case kFLASH_PropertyPflashBlockBaseAddr: - *value = config->PFlashBlockBase; - break; - - case kFLASH_PropertyPflashFacSupport: -#if defined(FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL) - *value = FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL; -#else - *value = 0; -#endif /* FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL */ - break; - - case kFLASH_PropertyPflashAccessSegmentSize: - *value = config->PFlashAccessSegmentSize; - break; - - case kFLASH_PropertyPflashAccessSegmentCount: - *value = config->PFlashAccessSegmentCount; - break; - - case kFLASH_PropertyFlexRamBlockBaseAddr: - *value = config->FlexRAMBlockBase; - break; - - case kFLASH_PropertyFlexRamTotalSize: - *value = config->FlexRAMTotalSize; - break; - -#if FLASH_SSD_IS_FLEXNVM_ENABLED - case kFLASH_PropertyDflashSectorSize: - *value = FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SECTOR_SIZE; - break; - case kFLASH_PropertyDflashTotalSize: - *value = config->DFlashTotalSize; - break; - case kFLASH_PropertyDflashBlockSize: - *value = FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SIZE; - break; - case kFLASH_PropertyDflashBlockCount: - *value = FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_COUNT; - break; - case kFLASH_PropertyDflashBlockBaseAddr: - *value = config->DFlashBlockBase; - break; - case kFLASH_PropertyEepromTotalSize: - *value = config->EEpromTotalSize; - break; -#endif /* FLASH_SSD_IS_FLEXNVM_ENABLED */ - - default: /* catch inputs that are not recognized */ - return kStatus_FLASH_UnknownProperty; - } - - return kStatus_FLASH_Success; -} - -status_t FLASH_SetProperty(flash_config_t *config, flash_property_tag_t whichProperty, uint32_t value) -{ - status_t status = kStatus_FLASH_Success; - - if (config == NULL) - { - return kStatus_FLASH_InvalidArgument; - } - - switch (whichProperty) - { -#if FLASH_SSD_IS_SECONDARY_FLASH_ENABLED - case kFLASH_PropertyFlashMemoryIndex: - if ((value != (uint32_t)kFLASH_MemoryIndexPrimaryFlash) && - (value != (uint32_t)kFLASH_MemoryIndexSecondaryFlash)) - { - return kStatus_FLASH_InvalidPropertyValue; - } - config->FlashMemoryIndex = (uint8_t)value; - break; -#endif /* FLASH_SSD_IS_SECONDARY_FLASH_ENABLED */ - - case kFLASH_PropertyFlashCacheControllerIndex: - if ((value != (uint32_t)kFLASH_CacheControllerIndexForCore0) && - (value != (uint32_t)kFLASH_CacheControllerIndexForCore1)) - { - return kStatus_FLASH_InvalidPropertyValue; - } - config->FlashCacheControllerIndex = (uint8_t)value; - break; - - case kFLASH_PropertyPflashSectorSize: - case kFLASH_PropertyPflashTotalSize: - case kFLASH_PropertyPflashBlockSize: - case kFLASH_PropertyPflashBlockCount: - case kFLASH_PropertyPflashBlockBaseAddr: - case kFLASH_PropertyPflashFacSupport: - case kFLASH_PropertyPflashAccessSegmentSize: - case kFLASH_PropertyPflashAccessSegmentCount: - case kFLASH_PropertyFlexRamBlockBaseAddr: - case kFLASH_PropertyFlexRamTotalSize: -#if FLASH_SSD_IS_FLEXNVM_ENABLED - case kFLASH_PropertyDflashSectorSize: - case kFLASH_PropertyDflashTotalSize: - case kFLASH_PropertyDflashBlockSize: - case kFLASH_PropertyDflashBlockCount: - case kFLASH_PropertyDflashBlockBaseAddr: - case kFLASH_PropertyEepromTotalSize: -#endif /* FLASH_SSD_IS_FLEXNVM_ENABLED */ - status = kStatus_FLASH_ReadOnlyProperty; - break; - default: /* catch inputs that are not recognized */ - status = kStatus_FLASH_UnknownProperty; - break; - } - - return status; -} - -#if defined(FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD) && FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD -status_t FLASH_SetFlexramFunction(flash_config_t *config, flash_flexram_function_option_t option) -{ - status_t status; - - if (config == NULL) - { - return kStatus_FLASH_InvalidArgument; - } - - status = flasn_check_flexram_function_option_range(option); - if (status != kStatus_FLASH_Success) - { - return status; - } - - /* preparing passing parameter to verify all block command */ - kFCCOBx[0] = BYTES_JOIN_TO_WORD_1_1_2(FTFx_SET_FLEXRAM_FUNCTION, option, 0xFFFFU); - - /* calling flash command sequence function to execute the command */ - return flash_command_sequence(config); -} -#endif /* FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD */ - -#if defined(FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD) && FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD -status_t FLASH_SwapControl(flash_config_t *config, - uint32_t address, - flash_swap_control_option_t option, - flash_swap_state_config_t *returnInfo) -{ - status_t returnCode; - - if ((config == NULL) || (returnInfo == NULL)) - { - return kStatus_FLASH_InvalidArgument; - } - - if (address & (FSL_FEATURE_FLASH_PFLASH_SWAP_CONTROL_CMD_ADDRESS_ALIGMENT - 1)) - { - return kStatus_FLASH_AlignmentError; - } - - /* Make sure address provided is in the lower half of Program flash but not in the Flash Configuration Field */ - if ((address >= (config->PFlashTotalSize / 2)) || - ((address >= kFLASH_ConfigAreaStart) && (address <= kFLASH_ConfigAreaEnd))) - { - return kStatus_FLASH_SwapIndicatorAddressError; - } - - /* Check the option. */ - returnCode = flash_check_swap_control_option(option); - if (returnCode) - { - return returnCode; - } - - kFCCOBx[0] = BYTES_JOIN_TO_WORD_1_3(FTFx_SWAP_CONTROL, address); - kFCCOBx[1] = BYTES_JOIN_TO_WORD_1_3(option, 0xFFFFFFU); - - returnCode = flash_command_sequence(config); - - returnInfo->flashSwapState = (flash_swap_state_t)FTFx_FCCOB5_REG; - returnInfo->currentSwapBlockStatus = (flash_swap_block_status_t)FTFx_FCCOB6_REG; - returnInfo->nextSwapBlockStatus = (flash_swap_block_status_t)FTFx_FCCOB7_REG; - - return returnCode; -} -#endif /* FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD */ - -#if defined(FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP) && FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP -status_t FLASH_Swap(flash_config_t *config, uint32_t address, flash_swap_function_option_t option) -{ - flash_swap_state_config_t returnInfo; - status_t returnCode; - - memset(&returnInfo, 0xFFU, sizeof(returnInfo)); - - do - { - returnCode = FLASH_SwapControl(config, address, kFLASH_SwapControlOptionReportStatus, &returnInfo); - if (returnCode != kStatus_FLASH_Success) - { - return returnCode; - } - - if (kFLASH_SwapFunctionOptionDisable == option) - { - if (returnInfo.flashSwapState == kFLASH_SwapStateDisabled) - { - return kStatus_FLASH_Success; - } - else if (returnInfo.flashSwapState == kFLASH_SwapStateUninitialized) - { - /* The swap system changed to the DISABLED state with Program flash block 0 - * located at relative flash address 0x0_0000 */ - returnCode = FLASH_SwapControl(config, address, kFLASH_SwapControlOptionDisableSystem, &returnInfo); - } - else - { - /* Swap disable should be requested only when swap system is in the uninitialized state */ - return kStatus_FLASH_SwapSystemNotInUninitialized; - } - } - else - { - /* When first swap: the initial swap state is Uninitialized, flash swap inidicator address is unset, - * the swap procedure should be Uninitialized -> Update-Erased -> Complete. - * After the first swap has been completed, the flash swap inidicator address cannot be modified - * unless EraseAllBlocks command is issued, the swap procedure is changed to Update -> Update-Erased -> - * Complete. */ - switch (returnInfo.flashSwapState) - { - case kFLASH_SwapStateUninitialized: - /* If current swap mode is Uninitialized, Initialize Swap to Initialized/READY state. */ - returnCode = - FLASH_SwapControl(config, address, kFLASH_SwapControlOptionIntializeSystem, &returnInfo); - break; - case kFLASH_SwapStateReady: - /* Validate whether the address provided to the swap system is matched to - * swap indicator address in the IFR */ - returnCode = flash_validate_swap_indicator_address(config, address); - if (returnCode == kStatus_FLASH_Success) - { - /* If current swap mode is Initialized/Ready, Initialize Swap to UPDATE state. */ - returnCode = - FLASH_SwapControl(config, address, kFLASH_SwapControlOptionSetInUpdateState, &returnInfo); - } - break; - case kFLASH_SwapStateUpdate: - /* If current swap mode is Update, Erase indicator sector in non active block - * to proceed swap system to update-erased state */ - returnCode = FLASH_Erase(config, address + (config->PFlashTotalSize >> 1), - FSL_FEATURE_FLASH_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT, kFLASH_ApiEraseKey); - break; - case kFLASH_SwapStateUpdateErased: - /* If current swap mode is Update or Update-Erased, progress Swap to COMPLETE State */ - returnCode = - FLASH_SwapControl(config, address, kFLASH_SwapControlOptionSetInCompleteState, &returnInfo); - break; - case kFLASH_SwapStateComplete: - break; - case kFLASH_SwapStateDisabled: - /* When swap system is in disabled state, We need to clear swap system back to uninitialized - * by issuing EraseAllBlocks command */ - returnCode = kStatus_FLASH_SwapSystemNotInUninitialized; - break; - default: - returnCode = kStatus_FLASH_InvalidArgument; - break; - } - } - if (returnCode != kStatus_FLASH_Success) - { - break; - } - } while (!((kFLASH_SwapStateComplete == returnInfo.flashSwapState) && (kFLASH_SwapFunctionOptionEnable == option))); - - return returnCode; -} -#endif /* FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP */ - -#if defined(FSL_FEATURE_FLASH_HAS_PROGRAM_PARTITION_CMD) && FSL_FEATURE_FLASH_HAS_PROGRAM_PARTITION_CMD -status_t FLASH_ProgramPartition(flash_config_t *config, - flash_partition_flexram_load_option_t option, - uint32_t eepromDataSizeCode, - uint32_t flexnvmPartitionCode) -{ - status_t returnCode; - - if (config == NULL) - { - return kStatus_FLASH_InvalidArgument; - } - - /* eepromDataSizeCode[7:6], flexnvmPartitionCode[7:4] should be all 1'b0 - * or it will cause access error. */ - /* eepromDataSizeCode &= 0x3FU; */ - /* flexnvmPartitionCode &= 0x0FU; */ - - /* preparing passing parameter to program the flash block */ - kFCCOBx[0] = BYTES_JOIN_TO_WORD_1_2_1(FTFx_PROGRAM_PARTITION, 0xFFFFU, option); - kFCCOBx[1] = BYTES_JOIN_TO_WORD_1_1_2(eepromDataSizeCode, flexnvmPartitionCode, 0xFFFFU); - - flash_cache_clear_process(config, kFLASH_CacheClearProcessPre); - - /* calling flash command sequence function to execute the command */ - returnCode = flash_command_sequence(config); - - flash_cache_clear(config); - -#if FLASH_SSD_IS_FLEXNVM_ENABLED - /* Data flash IFR will be updated by program partition command during reset sequence, - * so we just set reserved values for partitioned FlexNVM size here */ - config->EEpromTotalSize = FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_RESERVED; - config->DFlashTotalSize = FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED; -#endif - - return (returnCode); -} -#endif /* FSL_FEATURE_FLASH_HAS_PROGRAM_PARTITION_CMD */ - -status_t FLASH_PflashSetProtection(flash_config_t *config, pflash_protection_status_t *protectStatus) -{ - if (config == NULL) - { - return kStatus_FLASH_InvalidArgument; - } - -#if FLASH_SSD_IS_SECONDARY_FLASH_ENABLED && FLASH_SSD_SECONDARY_FLASH_HAS_ITS_OWN_PROTECTION_REGISTER - if (config->FlashMemoryIndex == (uint8_t)kFLASH_MemoryIndexSecondaryFlash) - { - *kFPROTSL = protectStatus->valueLow32b.prots16b.protsl; - if (protectStatus->valueLow32b.prots16b.protsl != *kFPROTSL) - { - return kStatus_FLASH_CommandFailure; - } - - *kFPROTSH = protectStatus->valueLow32b.prots16b.protsh; - if (protectStatus->valueLow32b.prots16b.protsh != *kFPROTSH) - { - return kStatus_FLASH_CommandFailure; - } - } - else -#endif - { - *kFPROTL = protectStatus->valueLow32b.protl32b; - if (protectStatus->valueLow32b.protl32b != *kFPROTL) - { - return kStatus_FLASH_CommandFailure; - } - -#if defined(FTFx_FPROT_HIGH_REG) - *kFPROTH = protectStatus->valueHigh32b.proth32b; - if (protectStatus->valueHigh32b.proth32b != *kFPROTH) - { - return kStatus_FLASH_CommandFailure; - } -#endif - } - - return kStatus_FLASH_Success; -} - -status_t FLASH_PflashGetProtection(flash_config_t *config, pflash_protection_status_t *protectStatus) -{ - if ((config == NULL) || (protectStatus == NULL)) - { - return kStatus_FLASH_InvalidArgument; - } - -#if FLASH_SSD_IS_SECONDARY_FLASH_ENABLED && FLASH_SSD_SECONDARY_FLASH_HAS_ITS_OWN_PROTECTION_REGISTER - if (config->FlashMemoryIndex == (uint8_t)kFLASH_MemoryIndexSecondaryFlash) - { - protectStatus->valueLow32b.prots16b.protsl = *kFPROTSL; - protectStatus->valueLow32b.prots16b.protsh = *kFPROTSH; - } - else -#endif - { - protectStatus->valueLow32b.protl32b = *kFPROTL; -#if defined(FTFx_FPROT_HIGH_REG) - protectStatus->valueHigh32b.proth32b = *kFPROTH; -#endif - } - - return kStatus_FLASH_Success; -} - -#if FLASH_SSD_IS_FLEXNVM_ENABLED -status_t FLASH_DflashSetProtection(flash_config_t *config, uint8_t protectStatus) -{ - if (config == NULL) - { - return kStatus_FLASH_InvalidArgument; - } - - if ((config->DFlashTotalSize == 0) || (config->DFlashTotalSize == FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED)) - { - return kStatus_FLASH_CommandNotSupported; - } - - FTFx->FDPROT = protectStatus; - - if (FTFx->FDPROT != protectStatus) - { - return kStatus_FLASH_CommandFailure; - } - - return kStatus_FLASH_Success; -} -#endif /* FLASH_SSD_IS_FLEXNVM_ENABLED */ - -#if FLASH_SSD_IS_FLEXNVM_ENABLED -status_t FLASH_DflashGetProtection(flash_config_t *config, uint8_t *protectStatus) -{ - if ((config == NULL) || (protectStatus == NULL)) - { - return kStatus_FLASH_InvalidArgument; - } - - if ((config->DFlashTotalSize == 0) || (config->DFlashTotalSize == FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED)) - { - return kStatus_FLASH_CommandNotSupported; - } - - *protectStatus = FTFx->FDPROT; - - return kStatus_FLASH_Success; -} -#endif /* FLASH_SSD_IS_FLEXNVM_ENABLED */ - -#if FLASH_SSD_IS_FLEXNVM_ENABLED -status_t FLASH_EepromSetProtection(flash_config_t *config, uint8_t protectStatus) -{ - if (config == NULL) - { - return kStatus_FLASH_InvalidArgument; - } - - if ((config->EEpromTotalSize == 0) || (config->EEpromTotalSize == FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_RESERVED)) - { - return kStatus_FLASH_CommandNotSupported; - } - - FTFx->FEPROT = protectStatus; - - if (FTFx->FEPROT != protectStatus) - { - return kStatus_FLASH_CommandFailure; - } - - return kStatus_FLASH_Success; -} -#endif /* FLASH_SSD_IS_FLEXNVM_ENABLED */ - -#if FLASH_SSD_IS_FLEXNVM_ENABLED -status_t FLASH_EepromGetProtection(flash_config_t *config, uint8_t *protectStatus) -{ - if ((config == NULL) || (protectStatus == NULL)) - { - return kStatus_FLASH_InvalidArgument; - } - - if ((config->EEpromTotalSize == 0) || (config->EEpromTotalSize == FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_RESERVED)) - { - return kStatus_FLASH_CommandNotSupported; - } - - *protectStatus = FTFx->FEPROT; - - return kStatus_FLASH_Success; -} -#endif /* FLASH_SSD_IS_FLEXNVM_ENABLED */ - -status_t FLASH_PflashSetPrefetchSpeculation(flash_prefetch_speculation_status_t *speculationStatus) -{ -#if FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_MCM - { - FTFx_REG32_ACCESS_TYPE regBase; -#if defined(MCM) - regBase = (FTFx_REG32_ACCESS_TYPE)&MCM->PLACR; -#elif defined(MCM0) - regBase = (FTFx_REG32_ACCESS_TYPE)&MCM0->PLACR; -#endif - if (speculationStatus->instructionOption == kFLASH_prefetchSpeculationOptionDisable) - { - if (speculationStatus->dataOption == kFLASH_prefetchSpeculationOptionEnable) - { - return kStatus_FLASH_InvalidSpeculationOption; - } - else - { - *regBase |= MCM_PLACR_DFCS_MASK; - } - } - else - { - *regBase &= ~MCM_PLACR_DFCS_MASK; - if (speculationStatus->dataOption == kFLASH_prefetchSpeculationOptionEnable) - { - *regBase |= MCM_PLACR_EFDS_MASK; - } - else - { - *regBase &= ~MCM_PLACR_EFDS_MASK; - } - } - } -#elif FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_FMC - { - FTFx_REG32_ACCESS_TYPE regBase; - uint32_t b0dpeMask, b0ipeMask; -#if defined(FMC_PFB01CR_B0DPE_MASK) - regBase = (FTFx_REG32_ACCESS_TYPE)&FMC->PFB01CR; - b0dpeMask = FMC_PFB01CR_B0DPE_MASK; - b0ipeMask = FMC_PFB01CR_B0IPE_MASK; -#elif defined(FMC_PFB0CR_B0DPE_MASK) - regBase = (FTFx_REG32_ACCESS_TYPE)&FMC->PFB0CR; - b0dpeMask = FMC_PFB0CR_B0DPE_MASK; - b0ipeMask = FMC_PFB0CR_B0IPE_MASK; -#endif - if (speculationStatus->instructionOption == kFLASH_prefetchSpeculationOptionEnable) - { - *regBase |= b0ipeMask; - } - else - { - *regBase &= ~b0ipeMask; - } - if (speculationStatus->dataOption == kFLASH_prefetchSpeculationOptionEnable) - { - *regBase |= b0dpeMask; - } - else - { - *regBase &= ~b0dpeMask; - } - -/* Invalidate Prefetch Speculation Buffer */ -#if defined(FMC_PFB01CR_S_INV_MASK) - FMC->PFB01CR |= FMC_PFB01CR_S_INV_MASK; -#elif defined(FMC_PFB01CR_S_B_INV_MASK) - FMC->PFB01CR |= FMC_PFB01CR_S_B_INV_MASK; -#elif defined(FMC_PFB0CR_S_INV_MASK) - FMC->PFB0CR |= FMC_PFB0CR_S_INV_MASK; -#elif defined(FMC_PFB0CR_S_B_INV_MASK) - FMC->PFB0CR |= FMC_PFB0CR_S_B_INV_MASK; -#endif - } -#elif FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_MSCM - { - FTFx_REG32_ACCESS_TYPE regBase; - uint32_t flashSpeculationMask, dataPrefetchMask; - regBase = (FTFx_REG32_ACCESS_TYPE)&MSCM->OCMDR[0]; - flashSpeculationMask = MSCM_OCMDR_OCMC1_DFCS_MASK; - dataPrefetchMask = MSCM_OCMDR_OCMC1_DFDS_MASK; - - if (speculationStatus->instructionOption == kFLASH_prefetchSpeculationOptionDisable) - { - if (speculationStatus->dataOption == kFLASH_prefetchSpeculationOptionEnable) - { - return kStatus_FLASH_InvalidSpeculationOption; - } - else - { - *regBase |= flashSpeculationMask; - } - } - else - { - *regBase &= ~flashSpeculationMask; - if (speculationStatus->dataOption == kFLASH_prefetchSpeculationOptionEnable) - { - *regBase &= ~dataPrefetchMask; - } - else - { - *regBase |= dataPrefetchMask; - } - } - } -#endif /* FSL_FEATURE_FTFx_MCM_FLASH_CACHE_CONTROLS */ - - return kStatus_FLASH_Success; -} - -status_t FLASH_PflashGetPrefetchSpeculation(flash_prefetch_speculation_status_t *speculationStatus) -{ - memset(speculationStatus, 0, sizeof(flash_prefetch_speculation_status_t)); - - /* Assuming that all speculation options are enabled. */ - speculationStatus->instructionOption = kFLASH_prefetchSpeculationOptionEnable; - speculationStatus->dataOption = kFLASH_prefetchSpeculationOptionEnable; - -#if FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_MCM - { - uint32_t value; -#if defined(MCM) - value = MCM->PLACR; -#elif defined(MCM0) - value = MCM0->PLACR; -#endif - if (value & MCM_PLACR_DFCS_MASK) - { - /* Speculation buffer is off. */ - speculationStatus->instructionOption = kFLASH_prefetchSpeculationOptionDisable; - speculationStatus->dataOption = kFLASH_prefetchSpeculationOptionDisable; - } - else - { - /* Speculation buffer is on for instruction. */ - if (!(value & MCM_PLACR_EFDS_MASK)) - { - /* Speculation buffer is off for data. */ - speculationStatus->dataOption = kFLASH_prefetchSpeculationOptionDisable; - } - } - } -#elif FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_FMC - { - uint32_t value; - uint32_t b0dpeMask, b0ipeMask; -#if defined(FMC_PFB01CR_B0DPE_MASK) - value = FMC->PFB01CR; - b0dpeMask = FMC_PFB01CR_B0DPE_MASK; - b0ipeMask = FMC_PFB01CR_B0IPE_MASK; -#elif defined(FMC_PFB0CR_B0DPE_MASK) - value = FMC->PFB0CR; - b0dpeMask = FMC_PFB0CR_B0DPE_MASK; - b0ipeMask = FMC_PFB0CR_B0IPE_MASK; -#endif - if (!(value & b0dpeMask)) - { - /* Do not prefetch in response to data references. */ - speculationStatus->dataOption = kFLASH_prefetchSpeculationOptionDisable; - } - if (!(value & b0ipeMask)) - { - /* Do not prefetch in response to instruction fetches. */ - speculationStatus->instructionOption = kFLASH_prefetchSpeculationOptionDisable; - } - } -#elif FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_MSCM - { - uint32_t value; - uint32_t flashSpeculationMask, dataPrefetchMask; - value = MSCM->OCMDR[0]; - flashSpeculationMask = MSCM_OCMDR_OCMC1_DFCS_MASK; - dataPrefetchMask = MSCM_OCMDR_OCMC1_DFDS_MASK; - - if (value & flashSpeculationMask) - { - /* Speculation buffer is off. */ - speculationStatus->instructionOption = kFLASH_prefetchSpeculationOptionDisable; - speculationStatus->dataOption = kFLASH_prefetchSpeculationOptionDisable; - } - else - { - /* Speculation buffer is on for instruction. */ - if (value & dataPrefetchMask) - { - /* Speculation buffer is off for data. */ - speculationStatus->dataOption = kFLASH_prefetchSpeculationOptionDisable; - } - } - } -#endif - - return kStatus_FLASH_Success; -} - -#if FLASH_DRIVER_IS_FLASH_RESIDENT -/*! - * @brief Copy PIC of flash_run_command() to RAM - */ -static void copy_flash_run_command(uint32_t *flashRunCommand) -{ - assert(sizeof(s_flashRunCommandFunctionCode) <= (kFLASH_ExecuteInRamFunctionMaxSizeInWords * 4)); - - /* Since the value of ARM function pointer is always odd, but the real start address - * of function memory should be even, that's why +1 operation exist. */ - memcpy((void *)flashRunCommand, (void *)s_flashRunCommandFunctionCode, sizeof(s_flashRunCommandFunctionCode)); - callFlashRunCommand = (void (*)(FTFx_REG8_ACCESS_TYPE ftfx_fstat))((uint32_t)flashRunCommand + 1); -} -#endif /* FLASH_DRIVER_IS_FLASH_RESIDENT */ - -/*! - * @brief Flash Command Sequence - * - * This function is used to perform the command write sequence to the flash. - * - * @param driver Pointer to storage for the driver runtime state. - * @return An error code or kStatus_FLASH_Success - */ -static status_t flash_command_sequence(flash_config_t *config) -{ - uint8_t registerValue; - -#if FLASH_DRIVER_IS_FLASH_RESIDENT - /* clear RDCOLERR & ACCERR & FPVIOL flag in flash status register */ - FTFx->FSTAT = FTFx_FSTAT_RDCOLERR_MASK | FTFx_FSTAT_ACCERR_MASK | FTFx_FSTAT_FPVIOL_MASK; - - status_t returnCode = flash_check_execute_in_ram_function_info(config); - if (kStatus_FLASH_Success != returnCode) - { - return returnCode; - } - - /* We pass the ftfx_fstat address as a parameter to flash_run_comamnd() instead of using - * pre-processed MICRO sentences or operating global variable in flash_run_comamnd() - * to make sure that flash_run_command() will be compiled into position-independent code (PIC). */ - callFlashRunCommand((FTFx_REG8_ACCESS_TYPE)(&FTFx->FSTAT)); -#else - /* clear RDCOLERR & ACCERR & FPVIOL flag in flash status register */ - FTFx->FSTAT = FTFx_FSTAT_RDCOLERR_MASK | FTFx_FSTAT_ACCERR_MASK | FTFx_FSTAT_FPVIOL_MASK; - - /* clear CCIF bit */ - FTFx->FSTAT = FTFx_FSTAT_CCIF_MASK; - - /* Check CCIF bit of the flash status register, wait till it is set. - * IP team indicates that this loop will always complete. */ - while (!(FTFx->FSTAT & FTFx_FSTAT_CCIF_MASK)) - { - } -#endif /* FLASH_DRIVER_IS_FLASH_RESIDENT */ - - /* Check error bits */ - /* Get flash status register value */ - registerValue = FTFx->FSTAT; - - /* checking access error */ - if (registerValue & FTFx_FSTAT_ACCERR_MASK) - { - return kStatus_FLASH_AccessError; - } - /* checking protection error */ - else if (registerValue & FTFx_FSTAT_FPVIOL_MASK) - { - return kStatus_FLASH_ProtectionViolation; - } - /* checking MGSTAT0 non-correctable error */ - else if (registerValue & FTFx_FSTAT_MGSTAT0_MASK) - { - return kStatus_FLASH_CommandFailure; - } - else - { - return kStatus_FLASH_Success; - } -} - -#if FLASH_DRIVER_IS_FLASH_RESIDENT -/*! - * @brief Copy PIC of flash_common_bit_operation() to RAM - * - */ -static void copy_flash_common_bit_operation(uint32_t *flashCommonBitOperation) -{ - assert(sizeof(s_flashCommonBitOperationFunctionCode) <= (kFLASH_ExecuteInRamFunctionMaxSizeInWords * 4)); - - /* Since the value of ARM function pointer is always odd, but the real start address - * of function memory should be even, that's why +1 operation exist. */ - memcpy((void *)flashCommonBitOperation, (void *)s_flashCommonBitOperationFunctionCode, - sizeof(s_flashCommonBitOperationFunctionCode)); - callFlashCommonBitOperation = (void (*)(FTFx_REG32_ACCESS_TYPE base, uint32_t bitMask, uint32_t bitShift, - uint32_t bitValue))((uint32_t)flashCommonBitOperation + 1); - /* Workround for some devices which doesn't need this function */ - callFlashCommonBitOperation((FTFx_REG32_ACCESS_TYPE)0, 0, 0, 0); -} -#endif /* FLASH_DRIVER_IS_FLASH_RESIDENT */ - -#if FLASH_CACHE_IS_CONTROLLED_BY_MCM -/*! @brief Performs the cache clear to the flash by MCM.*/ -void mcm_flash_cache_clear(flash_config_t *config) -{ - FTFx_REG32_ACCESS_TYPE regBase = (FTFx_REG32_ACCESS_TYPE)&MCM0_CACHE_REG; - -#if defined(MCM0) && defined(MCM1) - if (config->FlashCacheControllerIndex == (uint8_t)kFLASH_CacheControllerIndexForCore1) - { - regBase = (FTFx_REG32_ACCESS_TYPE)&MCM1_CACHE_REG; - } -#endif - -#if FLASH_DRIVER_IS_FLASH_RESIDENT - callFlashCommonBitOperation(regBase, MCM_CACHE_CLEAR_MASK, MCM_CACHE_CLEAR_SHIFT, 1U); -#else /* !FLASH_DRIVER_IS_FLASH_RESIDENT */ - *regBase |= MCM_CACHE_CLEAR_MASK; - - /* Memory barriers for good measure. - * All Cache, Branch predictor and TLB maintenance operations before this instruction complete */ - __ISB(); - __DSB(); -#endif /* FLASH_DRIVER_IS_FLASH_RESIDENT */ -} -#endif /* FLASH_CACHE_IS_CONTROLLED_BY_MCM */ - -#if FLASH_CACHE_IS_CONTROLLED_BY_FMC -/*! @brief Performs the cache clear to the flash by FMC.*/ -void fmc_flash_cache_clear(void) -{ -#if FLASH_DRIVER_IS_FLASH_RESIDENT - FTFx_REG32_ACCESS_TYPE regBase = (FTFx_REG32_ACCESS_TYPE)0; -#if defined(FMC_PFB01CR_CINV_WAY_MASK) - regBase = (FTFx_REG32_ACCESS_TYPE)&FMC->PFB01CR; - callFlashCommonBitOperation(regBase, FMC_PFB01CR_CINV_WAY_MASK, FMC_PFB01CR_CINV_WAY_SHIFT, 0xFU); -#else - regBase = (FTFx_REG32_ACCESS_TYPE)&FMC->PFB0CR; - callFlashCommonBitOperation(regBase, FMC_PFB0CR_CINV_WAY_MASK, FMC_PFB0CR_CINV_WAY_SHIFT, 0xFU); -#endif -#else /* !FLASH_DRIVER_IS_FLASH_RESIDENT */ -#if defined(FMC_PFB01CR_CINV_WAY_MASK) - FMC->PFB01CR = (FMC->PFB01CR & ~FMC_PFB01CR_CINV_WAY_MASK) | FMC_PFB01CR_CINV_WAY(~0); -#else - FMC->PFB0CR = (FMC->PFB0CR & ~FMC_PFB0CR_CINV_WAY_MASK) | FMC_PFB0CR_CINV_WAY(~0); -#endif - /* Memory barriers for good measure. - * All Cache, Branch predictor and TLB maintenance operations before this instruction complete */ - __ISB(); - __DSB(); -#endif /* FLASH_DRIVER_IS_FLASH_RESIDENT */ -} -#endif /* FLASH_CACHE_IS_CONTROLLED_BY_FMC */ - -#if FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_MSCM -/*! @brief Performs the prefetch speculation buffer clear to the flash by MSCM.*/ -void mscm_flash_prefetch_speculation_enable(bool enable) -{ - uint8_t setValue; - if (enable) - { - setValue = 0x0U; - } - else - { - setValue = 0x3U; - } - -/* The OCMDR[0] is always used to prefetch main Pflash*/ -/* For device with FlexNVM support, the OCMDR[1] is used to prefetch Dflash. - * For device with secondary flash support, the OCMDR[1] is used to prefetch secondary Pflash. */ -#if FLASH_DRIVER_IS_FLASH_RESIDENT - callFlashCommonBitOperation((FTFx_REG32_ACCESS_TYPE)&MSCM->OCMDR[0], MSCM_SPECULATION_DISABLE_MASK, - MSCM_SPECULATION_DISABLE_SHIFT, setValue); -#if FLASH_SSD_IS_FLEXNVM_ENABLED || BL_HAS_SECONDARY_INTERNAL_FLASH - callFlashCommonBitOperation((FTFx_REG32_ACCESS_TYPE)&MSCM->OCMDR[1], MSCM_SPECULATION_DISABLE_MASK, - MSCM_SPECULATION_DISABLE_SHIFT, setValue); -#endif -#else /* !FLASH_DRIVER_IS_FLASH_RESIDENT */ - MSCM->OCMDR[0] |= MSCM_SPECULATION_DISABLE(setValue); - - /* Memory barriers for good measure. - * All Cache, Branch predictor and TLB maintenance operations before this instruction complete */ - __ISB(); - __DSB(); -#if FLASH_SSD_IS_FLEXNVM_ENABLED || BL_HAS_SECONDARY_INTERNAL_FLASH - MSCM->OCMDR[1] |= MSCM_SPECULATION_DISABLE(setValue); - - /* Each cahce clear instaruction should be followed by below code*/ - __ISB(); - __DSB(); -#endif - -#endif /* FLASH_DRIVER_IS_FLASH_RESIDENT */ -} -#endif /* FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_MSCM */ - -#if FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_FMC -/*! @brief Performs the prefetch speculation buffer clear to the flash by FMC.*/ -void fmc_flash_prefetch_speculation_clear(void) -{ -#if FLASH_DRIVER_IS_FLASH_RESIDENT - FTFx_REG32_ACCESS_TYPE regBase = (FTFx_REG32_ACCESS_TYPE)0; -#if defined(FMC_PFB01CR_S_INV_MASK) - regBase = (FTFx_REG32_ACCESS_TYPE)&FMC->PFB01CR; - callFlashCommonBitOperation(regBase, FMC_PFB01CR_S_INV_MASK, FMC_PFB01CR_S_INV_SHIFT, 1U); -#elif defined(FMC_PFB01CR_S_B_INV_MASK) - regBase = (FTFx_REG32_ACCESS_TYPE)&FMC->PFB01CR; - callFlashCommonBitOperation(regBase, FMC_PFB01CR_S_B_INV_MASK, FMC_PFB01CR_S_B_INV_SHIFT, 1U); -#elif defined(FMC_PFB0CR_S_INV_MASK) - regBase = (FTFx_REG32_ACCESS_TYPE)&FMC->PFB0CR; - callFlashCommonBitOperation(regBase, FMC_PFB0CR_S_INV_MASK, FMC_PFB0CR_S_INV_SHIFT, 1U); -#elif defined(FMC_PFB0CR_S_B_INV_MASK) - regBase = (FTFx_REG32_ACCESS_TYPE)&FMC->PFB0CR; - callFlashCommonBitOperation(regBase, FMC_PFB0CR_S_B_INV_MASK, FMC_PFB0CR_S_B_INV_SHIFT, 1U); -#endif -#else /* !FLASH_DRIVER_IS_FLASH_RESIDENT */ -#if defined(FMC_PFB01CR_S_INV_MASK) - FMC->PFB01CR |= FMC_PFB01CR_S_INV_MASK; -#elif defined(FMC_PFB01CR_S_B_INV_MASK) - FMC->PFB01CR |= FMC_PFB01CR_S_B_INV_MASK; -#elif defined(FMC_PFB0CR_S_INV_MASK) - FMC->PFB0CR |= FMC_PFB0CR_S_INV_MASK; -#elif defined(FMC_PFB0CR_S_B_INV_MASK) - FMC->PFB0CR |= FMC_PFB0CR_S_B_INV_MASK; -#endif - /* Memory barriers for good measure. - * All Cache, Branch predictor and TLB maintenance operations before this instruction complete */ - __ISB(); - __DSB(); -#endif /* FLASH_DRIVER_IS_FLASH_RESIDENT */ -} -#endif /* FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_FMC */ - -/*! - * @brief Flash Cache Clear - * - * This function is used to perform the cache and prefetch speculation clear to the flash. - */ -void flash_cache_clear(flash_config_t *config) -{ - flash_cache_clear_process(config, kFLASH_CacheClearProcessPost); -} - -/*! - * @brief Flash Cache Clear Process - * - * This function is used to perform the cache and prefetch speculation clear process to the flash. - */ -static void flash_cache_clear_process(flash_config_t *config, flash_cache_clear_process_t process) -{ -#if FLASH_DRIVER_IS_FLASH_RESIDENT - status_t returnCode = flash_check_execute_in_ram_function_info(config); - if (kStatus_FLASH_Success != returnCode) - { - return; - } -#endif /* FLASH_DRIVER_IS_FLASH_RESIDENT */ - - /* We pass the ftfx register address as a parameter to flash_common_bit_operation() instead of using - * pre-processed MACROs or a global variable in flash_common_bit_operation() - * to make sure that flash_common_bit_operation() will be compiled into position-independent code (PIC). */ - if (process == kFLASH_CacheClearProcessPost) - { -#if FLASH_CACHE_IS_CONTROLLED_BY_MCM - mcm_flash_cache_clear(config); -#endif -#if FLASH_CACHE_IS_CONTROLLED_BY_FMC - fmc_flash_cache_clear(); -#endif -#if FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_MSCM - mscm_flash_prefetch_speculation_enable(true); -#endif -#if FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_FMC - fmc_flash_prefetch_speculation_clear(); -#endif - } - if (process == kFLASH_CacheClearProcessPre) - { -#if FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_MSCM - mscm_flash_prefetch_speculation_enable(false); -#endif - } -} - -#if FLASH_DRIVER_IS_FLASH_RESIDENT -/*! @brief Check whether flash execute-in-ram functions are ready */ -static status_t flash_check_execute_in_ram_function_info(flash_config_t *config) -{ - flash_execute_in_ram_function_config_t *flashExecuteInRamFunctionInfo; - - if (config == NULL) - { - return kStatus_FLASH_InvalidArgument; - } - - flashExecuteInRamFunctionInfo = (flash_execute_in_ram_function_config_t *)config->flashExecuteInRamFunctionInfo; - - if ((config->flashExecuteInRamFunctionInfo) && - (kFLASH_ExecuteInRamFunctionTotalNum == flashExecuteInRamFunctionInfo->activeFunctionCount)) - { - return kStatus_FLASH_Success; - } - - return kStatus_FLASH_ExecuteInRamFunctionNotReady; -} -#endif /* FLASH_DRIVER_IS_FLASH_RESIDENT */ - -/*! @brief Validates the range and alignment of the given address range.*/ -static status_t flash_check_range(flash_config_t *config, - uint32_t startAddress, - uint32_t lengthInBytes, - uint32_t alignmentBaseline) -{ - if (config == NULL) - { - return kStatus_FLASH_InvalidArgument; - } - - /* Verify the start and length are alignmentBaseline aligned. */ - if ((startAddress & (alignmentBaseline - 1)) || (lengthInBytes & (alignmentBaseline - 1))) - { - return kStatus_FLASH_AlignmentError; - } - - /* check for valid range of the target addresses */ - if ( -#if FLASH_SSD_IS_FLEXNVM_ENABLED - ((startAddress >= config->DFlashBlockBase) && - ((startAddress + lengthInBytes) <= (config->DFlashBlockBase + config->DFlashTotalSize))) || -#endif - ((startAddress >= config->PFlashBlockBase) && - ((startAddress + lengthInBytes) <= (config->PFlashBlockBase + config->PFlashTotalSize)))) - { - return kStatus_FLASH_Success; - } - - return kStatus_FLASH_AddressError; -} - -/*! @brief Gets the right address, sector and block size of current flash type which is indicated by address.*/ -static status_t flash_get_matched_operation_info(flash_config_t *config, - uint32_t address, - flash_operation_config_t *info) -{ - if (config == NULL) - { - return kStatus_FLASH_InvalidArgument; - } - - /* Clean up info Structure*/ - memset(info, 0, sizeof(flash_operation_config_t)); - -#if FLASH_SSD_IS_FLEXNVM_ENABLED - if ((address >= config->DFlashBlockBase) && (address <= (config->DFlashBlockBase + config->DFlashTotalSize))) - { - /* When required by the command, address bit 23 selects between program flash memory - * (=0) and data flash memory (=1).*/ - info->convertedAddress = address - config->DFlashBlockBase + 0x800000U; - info->activeSectorSize = FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SECTOR_SIZE; - info->activeBlockSize = config->DFlashTotalSize / FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_COUNT; - - info->blockWriteUnitSize = FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_WRITE_UNIT_SIZE; - info->sectorCmdAddressAligment = FSL_FEATURE_FLASH_FLEX_NVM_SECTOR_CMD_ADDRESS_ALIGMENT; - info->sectionCmdAddressAligment = FSL_FEATURE_FLASH_FLEX_NVM_SECTION_CMD_ADDRESS_ALIGMENT; - info->resourceCmdAddressAligment = FSL_FEATURE_FLASH_FLEX_NVM_RESOURCE_CMD_ADDRESS_ALIGMENT; - info->checkCmdAddressAligment = FSL_FEATURE_FLASH_FLEX_NVM_CHECK_CMD_ADDRESS_ALIGMENT; - } - else -#endif /* FLASH_SSD_IS_FLEXNVM_ENABLED */ - { - info->convertedAddress = address - config->PFlashBlockBase; - info->activeSectorSize = config->PFlashSectorSize; - info->activeBlockSize = config->PFlashTotalSize / config->PFlashBlockCount; -#if FLASH_SSD_IS_SECONDARY_FLASH_ENABLED - if (config->FlashMemoryIndex == (uint8_t)kFLASH_MemoryIndexSecondaryFlash) - { -#if FLASH_SSD_SECONDARY_FLASH_HAS_ITS_OWN_PROTECTION_REGISTER || FLASH_SSD_SECONDARY_FLASH_HAS_ITS_OWN_ACCESS_REGISTER - /* When required by the command, address bit 23 selects between main flash memory - * (=0) and secondary flash memory (=1).*/ - info->convertedAddress += 0x800000U; -#endif - info->blockWriteUnitSize = FSL_FEATURE_FLASH_PFLASH_1_BLOCK_WRITE_UNIT_SIZE; - } - else -#endif /* FLASH_SSD_IS_SECONDARY_FLASH_ENABLED */ - { - info->blockWriteUnitSize = FSL_FEATURE_FLASH_PFLASH_BLOCK_WRITE_UNIT_SIZE; - } - - info->sectorCmdAddressAligment = FSL_FEATURE_FLASH_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT; - info->sectionCmdAddressAligment = FSL_FEATURE_FLASH_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT; - info->resourceCmdAddressAligment = FSL_FEATURE_FLASH_PFLASH_RESOURCE_CMD_ADDRESS_ALIGMENT; - info->checkCmdAddressAligment = FSL_FEATURE_FLASH_PFLASH_CHECK_CMD_ADDRESS_ALIGMENT; - } - - return kStatus_FLASH_Success; -} - -/*! @brief Validates the given user key for flash erase APIs.*/ -static status_t flash_check_user_key(uint32_t key) -{ - /* Validate the user key */ - if (key != kFLASH_ApiEraseKey) - { - return kStatus_FLASH_EraseKeyError; - } - - return kStatus_FLASH_Success; -} - -#if FLASH_SSD_IS_FLEXNVM_ENABLED -/*! @brief Updates FlexNVM memory partition status according to data flash 0 IFR.*/ -static status_t flash_update_flexnvm_memory_partition_status(flash_config_t *config) -{ - struct - { - uint32_t reserved0; - uint8_t FlexNVMPartitionCode; - uint8_t EEPROMDataSetSize; - uint16_t reserved1; - } dataIFRReadOut; - status_t returnCode; - - if (config == NULL) - { - return kStatus_FLASH_InvalidArgument; - } - -#if defined(FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD) && FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD - /* Get FlexNVM memory partition info from data flash IFR */ - returnCode = FLASH_ReadResource(config, DFLASH_IFR_READRESOURCE_START_ADDRESS, (uint32_t *)&dataIFRReadOut, - sizeof(dataIFRReadOut), kFLASH_ResourceOptionFlashIfr); - if (returnCode != kStatus_FLASH_Success) - { - return kStatus_FLASH_PartitionStatusUpdateFailure; - } -#else -#error "Cannot get FlexNVM memory partition info" -#endif - - /* Fill out partitioned EEPROM size */ - dataIFRReadOut.EEPROMDataSetSize &= 0x0FU; - switch (dataIFRReadOut.EEPROMDataSetSize) - { - case 0x00U: - config->EEpromTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0000; - break; - case 0x01U: - config->EEpromTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0001; - break; - case 0x02U: - config->EEpromTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0010; - break; - case 0x03U: - config->EEpromTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0011; - break; - case 0x04U: - config->EEpromTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0100; - break; - case 0x05U: - config->EEpromTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0101; - break; - case 0x06U: - config->EEpromTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0110; - break; - case 0x07U: - config->EEpromTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0111; - break; - case 0x08U: - config->EEpromTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1000; - break; - case 0x09U: - config->EEpromTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1001; - break; - case 0x0AU: - config->EEpromTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1010; - break; - case 0x0BU: - config->EEpromTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1011; - break; - case 0x0CU: - config->EEpromTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1100; - break; - case 0x0DU: - config->EEpromTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1101; - break; - case 0x0EU: - config->EEpromTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1110; - break; - case 0x0FU: - config->EEpromTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1111; - break; - default: - config->EEpromTotalSize = FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_RESERVED; - break; - } - - /* Fill out partitioned DFlash size */ - dataIFRReadOut.FlexNVMPartitionCode &= 0x0FU; - switch (dataIFRReadOut.FlexNVMPartitionCode) - { - case 0x00U: -#if (FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0000 != 0xFFFFFFFF) - config->DFlashTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0000; -#else - config->DFlashTotalSize = FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED; -#endif /* FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0000 */ - break; - case 0x01U: -#if (FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0001 != 0xFFFFFFFF) - config->DFlashTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0001; -#else - config->DFlashTotalSize = FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED; -#endif /* FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0001 */ - break; - case 0x02U: -#if (FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0010 != 0xFFFFFFFF) - config->DFlashTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0010; -#else - config->DFlashTotalSize = FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED; -#endif /* FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0010 */ - break; - case 0x03U: -#if (FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0011 != 0xFFFFFFFF) - config->DFlashTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0011; -#else - config->DFlashTotalSize = FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED; -#endif /* FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0011 */ - break; - case 0x04U: -#if (FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0100 != 0xFFFFFFFF) - config->DFlashTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0100; -#else - config->DFlashTotalSize = FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED; -#endif /* FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0100 */ - break; - case 0x05U: -#if (FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0101 != 0xFFFFFFFF) - config->DFlashTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0101; -#else - config->DFlashTotalSize = FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED; -#endif /* FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0101 */ - break; - case 0x06U: -#if (FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0110 != 0xFFFFFFFF) - config->DFlashTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0110; -#else - config->DFlashTotalSize = FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED; -#endif /* FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0110 */ - break; - case 0x07U: -#if (FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0111 != 0xFFFFFFFF) - config->DFlashTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0111; -#else - config->DFlashTotalSize = FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED; -#endif /* FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0111 */ - break; - case 0x08U: -#if (FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1000 != 0xFFFFFFFF) - config->DFlashTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1000; -#else - config->DFlashTotalSize = FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED; -#endif /* FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1000 */ - break; - case 0x09U: -#if (FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1001 != 0xFFFFFFFF) - config->DFlashTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1001; -#else - config->DFlashTotalSize = FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED; -#endif /* FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1001 */ - break; - case 0x0AU: -#if (FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1010 != 0xFFFFFFFF) - config->DFlashTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1010; -#else - config->DFlashTotalSize = FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED; -#endif /* FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1010 */ - break; - case 0x0BU: -#if (FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1011 != 0xFFFFFFFF) - config->DFlashTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1011; -#else - config->DFlashTotalSize = FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED; -#endif /* FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1011 */ - break; - case 0x0CU: -#if (FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1100 != 0xFFFFFFFF) - config->DFlashTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1100; -#else - config->DFlashTotalSize = FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED; -#endif /* FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1100 */ - break; - case 0x0DU: -#if (FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1101 != 0xFFFFFFFF) - config->DFlashTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1101; -#else - config->DFlashTotalSize = FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED; -#endif /* FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1101 */ - break; - case 0x0EU: -#if (FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1110 != 0xFFFFFFFF) - config->DFlashTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1110; -#else - config->DFlashTotalSize = FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED; -#endif /* FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1110 */ - break; - case 0x0FU: -#if (FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1111 != 0xFFFFFFFF) - config->DFlashTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1111; -#else - config->DFlashTotalSize = FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED; -#endif /* FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1111 */ - break; - default: - config->DFlashTotalSize = FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED; - break; - } - - return kStatus_FLASH_Success; -} -#endif /* FLASH_SSD_IS_FLEXNVM_ENABLED */ - -#if defined(FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD) && FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD -/*! @brief Validates the range of the given resource address.*/ -static status_t flash_check_resource_range(uint32_t start, - uint32_t lengthInBytes, - uint32_t alignmentBaseline, - flash_read_resource_option_t option) -{ - status_t status; - uint32_t maxReadbleAddress; - - if ((start & (alignmentBaseline - 1)) || (lengthInBytes & (alignmentBaseline - 1))) - { - return kStatus_FLASH_AlignmentError; - } - - status = kStatus_FLASH_Success; - - maxReadbleAddress = start + lengthInBytes - 1; - if (option == kFLASH_ResourceOptionVersionId) - { - if ((start != kFLASH_ResourceRangeVersionIdStart) || - ((start + lengthInBytes - 1) != kFLASH_ResourceRangeVersionIdEnd)) - { - status = kStatus_FLASH_InvalidArgument; - } - } - else if (option == kFLASH_ResourceOptionFlashIfr) - { - if (maxReadbleAddress < kFLASH_ResourceRangePflashIfrSizeInBytes) - { - } -#if defined(FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP) && FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP - else if ((start >= kFLASH_ResourceRangePflashSwapIfrStart) && - (maxReadbleAddress <= kFLASH_ResourceRangePflashSwapIfrEnd)) - { - } -#endif /* FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP */ - else if ((start >= kFLASH_ResourceRangeDflashIfrStart) && - (maxReadbleAddress <= kFLASH_ResourceRangeDflashIfrEnd)) - { - } - else - { - status = kStatus_FLASH_InvalidArgument; - } - } - else - { - status = kStatus_FLASH_InvalidArgument; - } - - return status; -} -#endif /* FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD */ - -#if defined(FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD) && FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD -/*! @brief Validates the gived swap control option.*/ -static status_t flash_check_swap_control_option(flash_swap_control_option_t option) -{ - if ((option == kFLASH_SwapControlOptionIntializeSystem) || (option == kFLASH_SwapControlOptionSetInUpdateState) || - (option == kFLASH_SwapControlOptionSetInCompleteState) || (option == kFLASH_SwapControlOptionReportStatus) || - (option == kFLASH_SwapControlOptionDisableSystem)) - { - return kStatus_FLASH_Success; - } - - return kStatus_FLASH_InvalidArgument; -} -#endif /* FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD */ - -#if defined(FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP) && FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP -/*! @brief Validates the gived address to see if it is equal to swap indicator address in pflash swap IFR.*/ -static status_t flash_validate_swap_indicator_address(flash_config_t *config, uint32_t address) -{ - flash_swap_ifr_field_data_t flashSwapIfrFieldData; - uint32_t swapIndicatorAddress; - - status_t returnCode; -#if defined(FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD) && FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD - returnCode = - FLASH_ReadResource(config, kFLASH_ResourceRangePflashSwapIfrStart, flashSwapIfrFieldData.flashSwapIfrData, - sizeof(flashSwapIfrFieldData.flashSwapIfrData), kFLASH_ResourceOptionFlashIfr); - - if (returnCode != kStatus_FLASH_Success) - { - return returnCode; - } -#else - { - /* From RM, the actual info are stored in FCCOB6,7 */ - uint32_t returnValue[2]; - returnCode = FLASH_ReadOnce(config, kFLASH_RecordIndexSwapAddr, returnValue, 4); - if (returnCode != kStatus_FLASH_Success) - { - return returnCode; - } - flashSwapIfrFieldData.flashSwapIfrField.swapIndicatorAddress = (uint16_t)returnValue[0]; - returnCode = FLASH_ReadOnce(config, kFLASH_RecordIndexSwapEnable, returnValue, 4); - if (returnCode != kStatus_FLASH_Success) - { - return returnCode; - } - flashSwapIfrFieldData.flashSwapIfrField.swapEnableWord = (uint16_t)returnValue[0]; - returnCode = FLASH_ReadOnce(config, kFLASH_RecordIndexSwapDisable, returnValue, 4); - if (returnCode != kStatus_FLASH_Success) - { - return returnCode; - } - flashSwapIfrFieldData.flashSwapIfrField.swapDisableWord = (uint16_t)returnValue[0]; - } -#endif - - /* The high bits value of Swap Indicator Address is stored in Program Flash Swap IFR Field, - * the low severval bit value of Swap Indicator Address is always 1'b0 */ - swapIndicatorAddress = (uint32_t)flashSwapIfrFieldData.flashSwapIfrField.swapIndicatorAddress * - FSL_FEATURE_FLASH_PFLASH_SWAP_CONTROL_CMD_ADDRESS_ALIGMENT; - if (address != swapIndicatorAddress) - { - return kStatus_FLASH_SwapIndicatorAddressError; - } - - return returnCode; -} -#endif /* FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP */ - -#if defined(FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD) && FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD -/*! @brief Validates the gived flexram function option.*/ -static inline status_t flasn_check_flexram_function_option_range(flash_flexram_function_option_t option) -{ - if ((option != kFLASH_FlexramFunctionOptionAvailableAsRam) && - (option != kFLASH_FlexramFunctionOptionAvailableForEeprom)) - { - return kStatus_FLASH_InvalidArgument; - } - - return kStatus_FLASH_Success; -} -#endif /* FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD */ - -/*! @brief Gets the flash protection information (region size, region count).*/ -static status_t flash_get_protection_info(flash_config_t *config, flash_protection_config_t *info) -{ - uint32_t pflashTotalSize; - - if (config == NULL) - { - return kStatus_FLASH_InvalidArgument; - } - - /* Clean up info Structure*/ - memset(info, 0, sizeof(flash_protection_config_t)); - -/* Note: KW40 has a secondary flash, but it doesn't have independent protection register*/ -#if FLASH_SSD_IS_SECONDARY_FLASH_ENABLED && (!FLASH_SSD_SECONDARY_FLASH_HAS_ITS_OWN_PROTECTION_REGISTER) - pflashTotalSize = FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT * FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE + - FSL_FEATURE_FLASH_PFLASH_1_BLOCK_COUNT * FSL_FEATURE_FLASH_PFLASH_1_BLOCK_SIZE; - info->regionBase = FSL_FEATURE_FLASH_PFLASH_START_ADDRESS; -#else - pflashTotalSize = config->PFlashTotalSize; - info->regionBase = config->PFlashBlockBase; -#endif - -#if FLASH_SSD_IS_SECONDARY_FLASH_ENABLED && FLASH_SSD_SECONDARY_FLASH_HAS_ITS_OWN_PROTECTION_REGISTER - if (config->FlashMemoryIndex == (uint8_t)kFLASH_MemoryIndexSecondaryFlash) - { - info->regionCount = FSL_FEATURE_FLASH_PFLASH_1_PROTECTION_REGION_COUNT; - } - else -#endif - { - info->regionCount = FSL_FEATURE_FLASH_PFLASH_PROTECTION_REGION_COUNT; - } - - /* Calculate the size of the flash protection region - * If the flash density is > 32KB, then protection region is 1/32 of total flash density - * Else if flash density is < 32KB, then flash protection region is set to 1KB */ - if (pflashTotalSize > info->regionCount * 1024) - { - info->regionSize = (pflashTotalSize) / info->regionCount; - } - else - { - info->regionSize = 1024; - } - - return kStatus_FLASH_Success; -} - -#if defined(FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL) && FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL -/*! @brief Gets the flash Execute-Only access information (Segment size, Segment count).*/ -static status_t flash_get_access_info(flash_config_t *config, flash_access_config_t *info) -{ - if (config == NULL) - { - return kStatus_FLASH_InvalidArgument; - } - - /* Clean up info Structure*/ - memset(info, 0, sizeof(flash_access_config_t)); - -/* Note: KW40 has a secondary flash, but it doesn't have independent access register*/ -#if FLASH_SSD_IS_SECONDARY_FLASH_ENABLED && (!FLASH_SSD_SECONDARY_FLASH_HAS_ITS_OWN_ACCESS_REGISTER) - info->SegmentBase = FSL_FEATURE_FLASH_PFLASH_START_ADDRESS; -#else - info->SegmentBase = config->PFlashBlockBase; -#endif - info->SegmentSize = config->PFlashAccessSegmentSize; - info->SegmentCount = config->PFlashAccessSegmentCount; - - return kStatus_FLASH_Success; -} -#endif /* FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL */ diff --git a/ext/hal/nxp/mcux/drivers/kinetis/fsl_flash.h b/ext/hal/nxp/mcux/drivers/kinetis/fsl_flash.h index e143cb3e1f6..16a4d669dff 100644 --- a/ext/hal/nxp/mcux/drivers/kinetis/fsl_flash.h +++ b/ext/hal/nxp/mcux/drivers/kinetis/fsl_flash.h @@ -1,597 +1,28 @@ /* - * Copyright (c) 2013-2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ +* Copyright 2013-2016 Freescale Semiconductor, Inc. +* Copyright 2016-2018 NXP +* All rights reserved. +* +* SPDX-License-Identifier: BSD-3-Clause +* +*/ #ifndef _FSL_FLASH_H_ #define _FSL_FLASH_H_ -#if (defined(BL_TARGET_FLASH) || defined(BL_TARGET_ROM) || defined(BL_TARGET_RAM)) -#include -#include -#include "fsl_device_registers.h" -#include "bootloader_common.h" -#else -#include "fsl_common.h" +#include "fsl_ftfx_cache.h" +#include "fsl_ftfx_flash.h" +#if FSL_FEATURE_FLASH_HAS_FLEX_NVM +#include "fsl_ftfx_flexnvm.h" #endif -/******************************************************************************* - * Definitions - ******************************************************************************/ - /*! * @addtogroup flash_driver * @{ */ - -/*! - * @name Flash version - * @{ - */ -/*! @brief Constructs the version number for drivers. */ -#if !defined(MAKE_VERSION) -#define MAKE_VERSION(major, minor, bugfix) (((major) << 16) | ((minor) << 8) | (bugfix)) -#endif - -/*! @brief Flash driver version for SDK*/ -#define FSL_FLASH_DRIVER_VERSION (MAKE_VERSION(2, 3, 1)) /*!< Version 2.3.1. */ - -/*! @brief Flash driver version for ROM*/ -enum _flash_driver_version_constants -{ - kFLASH_DriverVersionName = 'F', /*!< Flash driver version name.*/ - kFLASH_DriverVersionMajor = 2, /*!< Major flash driver version.*/ - kFLASH_DriverVersionMinor = 3, /*!< Minor flash driver version.*/ - kFLASH_DriverVersionBugfix = 1 /*!< Bugfix for flash driver version.*/ -}; -/*@}*/ - -/*! - * @name Flash configuration - * @{ - */ -/*! @brief Indicates whether to support FlexNVM in the Flash driver */ -#if !defined(FLASH_SSD_CONFIG_ENABLE_FLEXNVM_SUPPORT) -#define FLASH_SSD_CONFIG_ENABLE_FLEXNVM_SUPPORT 1 /*!< Enables the FlexNVM support by default. */ -#endif - -/*! @brief Indicates whether the FlexNVM is enabled in the Flash driver */ -#define FLASH_SSD_IS_FLEXNVM_ENABLED (FLASH_SSD_CONFIG_ENABLE_FLEXNVM_SUPPORT && FSL_FEATURE_FLASH_HAS_FLEX_NVM) - -/*! @brief Indicates whether to support Secondary flash in the Flash driver */ -#if !defined(FLASH_SSD_CONFIG_ENABLE_SECONDARY_FLASH_SUPPORT) -#define FLASH_SSD_CONFIG_ENABLE_SECONDARY_FLASH_SUPPORT 1 /*!< Enables the secondary flash support by default. */ -#endif - -/*! @brief Indicates whether the secondary flash is supported in the Flash driver */ -#if defined(FSL_FEATURE_FLASH_HAS_MULTIPLE_FLASH) || defined(FSL_FEATURE_FLASH_PFLASH_1_START_ADDRESS) -#define FLASH_SSD_IS_SECONDARY_FLASH_ENABLED (FLASH_SSD_CONFIG_ENABLE_SECONDARY_FLASH_SUPPORT) -#else -#define FLASH_SSD_IS_SECONDARY_FLASH_ENABLED (0) -#endif - -/*! @brief Flash driver location. */ -#if !defined(FLASH_DRIVER_IS_FLASH_RESIDENT) -#if (!defined(BL_TARGET_ROM) && !defined(BL_TARGET_RAM)) -#define FLASH_DRIVER_IS_FLASH_RESIDENT 1 /*!< Used for the flash resident application. */ -#else -#define FLASH_DRIVER_IS_FLASH_RESIDENT 0 /*!< Used for the non-flash resident application. */ -#endif -#endif - -/*! @brief Flash Driver Export option */ -#if !defined(FLASH_DRIVER_IS_EXPORTED) -#if (defined(BL_TARGET_ROM) || defined(BL_TARGET_FLASH)) -#define FLASH_DRIVER_IS_EXPORTED 1 /*!< Used for the ROM bootloader. */ -#else -#define FLASH_DRIVER_IS_EXPORTED 0 /*!< Used for the MCUXpresso SDK application. */ -#endif -#endif -/*@}*/ - -/*! - * @name Flash status - * @{ - */ -/*! @brief Flash driver status group. */ -#if defined(kStatusGroup_FlashDriver) -#define kStatusGroupGeneric kStatusGroup_Generic -#define kStatusGroupFlashDriver kStatusGroup_FlashDriver -#elif defined(kStatusGroup_FLASH) -#define kStatusGroupGeneric kStatusGroup_Generic -#define kStatusGroupFlashDriver kStatusGroup_FLASH -#else -#define kStatusGroupGeneric 0 -#define kStatusGroupFlashDriver 1 -#endif - -/*! @brief Constructs a status code value from a group and a code number. */ -#if !defined(MAKE_STATUS) -#define MAKE_STATUS(group, code) ((((group)*100) + (code))) -#endif - -/*! - * @brief Flash driver status codes. - */ -enum _flash_status -{ - kStatus_FLASH_Success = MAKE_STATUS(kStatusGroupGeneric, 0), /*!< API is executed successfully*/ - kStatus_FLASH_InvalidArgument = MAKE_STATUS(kStatusGroupGeneric, 4), /*!< Invalid argument*/ - kStatus_FLASH_SizeError = MAKE_STATUS(kStatusGroupFlashDriver, 0), /*!< Error size*/ - kStatus_FLASH_AlignmentError = - MAKE_STATUS(kStatusGroupFlashDriver, 1), /*!< Parameter is not aligned with the specified baseline*/ - kStatus_FLASH_AddressError = MAKE_STATUS(kStatusGroupFlashDriver, 2), /*!< Address is out of range */ - kStatus_FLASH_AccessError = - MAKE_STATUS(kStatusGroupFlashDriver, 3), /*!< Invalid instruction codes and out-of bound addresses */ - kStatus_FLASH_ProtectionViolation = MAKE_STATUS( - kStatusGroupFlashDriver, 4), /*!< The program/erase operation is requested to execute on protected areas */ - kStatus_FLASH_CommandFailure = - MAKE_STATUS(kStatusGroupFlashDriver, 5), /*!< Run-time error during command execution. */ - kStatus_FLASH_UnknownProperty = MAKE_STATUS(kStatusGroupFlashDriver, 6), /*!< Unknown property.*/ - kStatus_FLASH_EraseKeyError = MAKE_STATUS(kStatusGroupFlashDriver, 7), /*!< API erase key is invalid.*/ - kStatus_FLASH_RegionExecuteOnly = - MAKE_STATUS(kStatusGroupFlashDriver, 8), /*!< The current region is execute-only.*/ - kStatus_FLASH_ExecuteInRamFunctionNotReady = - MAKE_STATUS(kStatusGroupFlashDriver, 9), /*!< Execute-in-RAM function is not available.*/ - kStatus_FLASH_PartitionStatusUpdateFailure = - MAKE_STATUS(kStatusGroupFlashDriver, 10), /*!< Failed to update partition status.*/ - kStatus_FLASH_SetFlexramAsEepromError = - MAKE_STATUS(kStatusGroupFlashDriver, 11), /*!< Failed to set FlexRAM as EEPROM.*/ - kStatus_FLASH_RecoverFlexramAsRamError = - MAKE_STATUS(kStatusGroupFlashDriver, 12), /*!< Failed to recover FlexRAM as RAM.*/ - kStatus_FLASH_SetFlexramAsRamError = MAKE_STATUS(kStatusGroupFlashDriver, 13), /*!< Failed to set FlexRAM as RAM.*/ - kStatus_FLASH_RecoverFlexramAsEepromError = - MAKE_STATUS(kStatusGroupFlashDriver, 14), /*!< Failed to recover FlexRAM as EEPROM.*/ - kStatus_FLASH_CommandNotSupported = MAKE_STATUS(kStatusGroupFlashDriver, 15), /*!< Flash API is not supported.*/ - kStatus_FLASH_SwapSystemNotInUninitialized = - MAKE_STATUS(kStatusGroupFlashDriver, 16), /*!< Swap system is not in an uninitialzed state.*/ - kStatus_FLASH_SwapIndicatorAddressError = - MAKE_STATUS(kStatusGroupFlashDriver, 17), /*!< The swap indicator address is invalid.*/ - kStatus_FLASH_ReadOnlyProperty = MAKE_STATUS(kStatusGroupFlashDriver, 18), /*!< The flash property is read-only.*/ - kStatus_FLASH_InvalidPropertyValue = - MAKE_STATUS(kStatusGroupFlashDriver, 19), /*!< The flash property value is out of range.*/ - kStatus_FLASH_InvalidSpeculationOption = - MAKE_STATUS(kStatusGroupFlashDriver, 20), /*!< The option of flash prefetch speculation is invalid.*/ -}; -/*@}*/ - -/*! - * @name Flash API key - * @{ - */ -/*! @brief Constructs the four character code for the Flash driver API key. */ -#if !defined(FOUR_CHAR_CODE) -#define FOUR_CHAR_CODE(a, b, c, d) (((d) << 24) | ((c) << 16) | ((b) << 8) | ((a))) -#endif - -/*! - * @brief Enumeration for Flash driver API keys. - * - * @note The resulting value is built with a byte order such that the string - * being readable in expected order when viewed in a hex editor, if the value - * is treated as a 32-bit little endian value. - */ -enum _flash_driver_api_keys -{ - kFLASH_ApiEraseKey = FOUR_CHAR_CODE('k', 'f', 'e', 'k') /*!< Key value used to validate all flash erase APIs.*/ -}; -/*@}*/ - -/*! - * @brief Enumeration for supported flash margin levels. - */ -typedef enum _flash_margin_value -{ - kFLASH_MarginValueNormal, /*!< Use the 'normal' read level for 1s.*/ - kFLASH_MarginValueUser, /*!< Apply the 'User' margin to the normal read-1 level.*/ - kFLASH_MarginValueFactory, /*!< Apply the 'Factory' margin to the normal read-1 level.*/ - kFLASH_MarginValueInvalid /*!< Not real margin level, Used to determine the range of valid margin level. */ -} flash_margin_value_t; - -/*! - * @brief Enumeration for the three possible flash security states. - */ -typedef enum _flash_security_state -{ - kFLASH_SecurityStateNotSecure, /*!< Flash is not secure.*/ - kFLASH_SecurityStateBackdoorEnabled, /*!< Flash backdoor is enabled.*/ - kFLASH_SecurityStateBackdoorDisabled /*!< Flash backdoor is disabled.*/ -} flash_security_state_t; - -/*! - * @brief Enumeration for the three possible flash protection levels. - */ -typedef enum _flash_protection_state -{ - kFLASH_ProtectionStateUnprotected, /*!< Flash region is not protected.*/ - kFLASH_ProtectionStateProtected, /*!< Flash region is protected.*/ - kFLASH_ProtectionStateMixed /*!< Flash is mixed with protected and unprotected region.*/ -} flash_protection_state_t; - -/*! - * @brief Enumeration for the three possible flash execute access levels. - */ -typedef enum _flash_execute_only_access_state -{ - kFLASH_AccessStateUnLimited, /*!< Flash region is unlimited.*/ - kFLASH_AccessStateExecuteOnly, /*!< Flash region is execute only.*/ - kFLASH_AccessStateMixed /*!< Flash is mixed with unlimited and execute only region.*/ -} flash_execute_only_access_state_t; - -/*! - * @brief Enumeration for various flash properties. - */ -typedef enum _flash_property_tag -{ - kFLASH_PropertyPflashSectorSize = 0x00U, /*!< Pflash sector size property.*/ - kFLASH_PropertyPflashTotalSize = 0x01U, /*!< Pflash total size property.*/ - kFLASH_PropertyPflashBlockSize = 0x02U, /*!< Pflash block size property.*/ - kFLASH_PropertyPflashBlockCount = 0x03U, /*!< Pflash block count property.*/ - kFLASH_PropertyPflashBlockBaseAddr = 0x04U, /*!< Pflash block base address property.*/ - kFLASH_PropertyPflashFacSupport = 0x05U, /*!< Pflash fac support property.*/ - kFLASH_PropertyPflashAccessSegmentSize = 0x06U, /*!< Pflash access segment size property.*/ - kFLASH_PropertyPflashAccessSegmentCount = 0x07U, /*!< Pflash access segment count property.*/ - kFLASH_PropertyFlexRamBlockBaseAddr = 0x08U, /*!< FlexRam block base address property.*/ - kFLASH_PropertyFlexRamTotalSize = 0x09U, /*!< FlexRam total size property.*/ - kFLASH_PropertyDflashSectorSize = 0x10U, /*!< Dflash sector size property.*/ - kFLASH_PropertyDflashTotalSize = 0x11U, /*!< Dflash total size property.*/ - kFLASH_PropertyDflashBlockSize = 0x12U, /*!< Dflash block size property.*/ - kFLASH_PropertyDflashBlockCount = 0x13U, /*!< Dflash block count property.*/ - kFLASH_PropertyDflashBlockBaseAddr = 0x14U, /*!< Dflash block base address property.*/ - kFLASH_PropertyEepromTotalSize = 0x15U, /*!< EEPROM total size property.*/ - kFLASH_PropertyFlashMemoryIndex = 0x20U, /*!< Flash memory index property.*/ - kFLASH_PropertyFlashCacheControllerIndex = 0x21U /*!< Flash cache controller index property.*/ -} flash_property_tag_t; - -/*! - * @brief Constants for execute-in-RAM flash function. - */ -enum _flash_execute_in_ram_function_constants -{ - kFLASH_ExecuteInRamFunctionMaxSizeInWords = 16U, /*!< The maximum size of execute-in-RAM function.*/ - kFLASH_ExecuteInRamFunctionTotalNum = 2U /*!< Total number of execute-in-RAM functions.*/ -}; - -/*! - * @brief Flash execute-in-RAM function information. - */ -typedef struct _flash_execute_in_ram_function_config -{ - uint32_t activeFunctionCount; /*!< Number of available execute-in-RAM functions.*/ - uint32_t *flashRunCommand; /*!< Execute-in-RAM function: flash_run_command.*/ - uint32_t *flashCommonBitOperation; /*!< Execute-in-RAM function: flash_common_bit_operation.*/ -} flash_execute_in_ram_function_config_t; - -/*! - * @brief Enumeration for the two possible options of flash read resource command. - */ -typedef enum _flash_read_resource_option -{ - kFLASH_ResourceOptionFlashIfr = - 0x00U, /*!< Select code for Program flash 0 IFR, Program flash swap 0 IFR, Data flash 0 IFR */ - kFLASH_ResourceOptionVersionId = 0x01U /*!< Select code for the version ID*/ -} flash_read_resource_option_t; - -/*! - * @brief Enumeration for the range of special-purpose flash resource - */ -enum _flash_read_resource_range -{ -#if (FSL_FEATURE_FLASH_IS_FTFE == 1) - kFLASH_ResourceRangePflashIfrSizeInBytes = 1024U, /*!< Pflash IFR size in byte.*/ - kFLASH_ResourceRangeVersionIdSizeInBytes = 8U, /*!< Version ID IFR size in byte.*/ - kFLASH_ResourceRangeVersionIdStart = 0x08U, /*!< Version ID IFR start address.*/ - kFLASH_ResourceRangeVersionIdEnd = 0x0FU, /*!< Version ID IFR end address.*/ - kFLASH_ResourceRangePflashSwapIfrStart = 0x40000U, /*!< Pflash swap IFR start address.*/ - kFLASH_ResourceRangePflashSwapIfrEnd = - (kFLASH_ResourceRangePflashSwapIfrStart + 0x3FFU), /*!< Pflash swap IFR end address.*/ -#else /* FSL_FEATURE_FLASH_IS_FTFL == 1 or FSL_FEATURE_FLASH_IS_FTFA = =1 */ - kFLASH_ResourceRangePflashIfrSizeInBytes = 256U, /*!< Pflash IFR size in byte.*/ - kFLASH_ResourceRangeVersionIdSizeInBytes = 8U, /*!< Version ID IFR size in byte.*/ - kFLASH_ResourceRangeVersionIdStart = 0x00U, /*!< Version ID IFR start address.*/ - kFLASH_ResourceRangeVersionIdEnd = 0x07U, /*!< Version ID IFR end address.*/ -#if 0x20000U == (FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT * FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE) - kFLASH_ResourceRangePflashSwapIfrStart = 0x8000U, /*!< Pflash swap IFR start address.*/ -#elif 0x40000U == (FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT * FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE) - kFLASH_ResourceRangePflashSwapIfrStart = 0x10000U, /*!< Pflash swap IFR start address.*/ -#elif 0x80000U == (FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT * FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE) - kFLASH_ResourceRangePflashSwapIfrStart = 0x20000U, /*!< Pflash swap IFR start address.*/ -#else - kFLASH_ResourceRangePflashSwapIfrStart = 0, -#endif - kFLASH_ResourceRangePflashSwapIfrEnd = - (kFLASH_ResourceRangePflashSwapIfrStart + 0xFFU), /*!< Pflash swap IFR end address.*/ -#endif - kFLASH_ResourceRangeDflashIfrStart = 0x800000U, /*!< Dflash IFR start address.*/ - kFLASH_ResourceRangeDflashIfrEnd = 0x8003FFU, /*!< Dflash IFR end address.*/ -}; - -/*! - * @brief Enumeration for the index of read/program once record - */ -enum _k3_flash_read_once_index -{ - kFLASH_RecordIndexSwapAddr = 0xA1U, /*!< Index of Swap indicator address.*/ - kFLASH_RecordIndexSwapEnable = 0xA2U, /*!< Index of Swap system enable.*/ - kFLASH_RecordIndexSwapDisable = 0xA3U, /*!< Index of Swap system disable.*/ -}; - -/*! - * @brief Enumeration for the two possilbe options of set FlexRAM function command. - */ -typedef enum _flash_flexram_function_option -{ - kFLASH_FlexramFunctionOptionAvailableAsRam = 0xFFU, /*!< An option used to make FlexRAM available as RAM */ - kFLASH_FlexramFunctionOptionAvailableForEeprom = 0x00U /*!< An option used to make FlexRAM available for EEPROM */ -} flash_flexram_function_option_t; - -/*! - * @brief Enumeration for acceleration RAM property. - */ -enum _flash_acceleration_ram_property -{ - kFLASH_AccelerationRamSize = 0x400U -}; - -/*! - * @brief Enumeration for the possible options of Swap function - */ -typedef enum _flash_swap_function_option -{ - kFLASH_SwapFunctionOptionEnable = 0x00U, /*!< An option used to enable the Swap function */ - kFLASH_SwapFunctionOptionDisable = 0x01U /*!< An option used to disable the Swap function */ -} flash_swap_function_option_t; - -/*! - * @brief Enumeration for the possible options of Swap control commands - */ -typedef enum _flash_swap_control_option -{ - kFLASH_SwapControlOptionIntializeSystem = 0x01U, /*!< An option used to initialize the Swap system */ - kFLASH_SwapControlOptionSetInUpdateState = 0x02U, /*!< An option used to set the Swap in an update state */ - kFLASH_SwapControlOptionSetInCompleteState = 0x04U, /*!< An option used to set the Swap in a complete state */ - kFLASH_SwapControlOptionReportStatus = 0x08U, /*!< An option used to report the Swap status */ - kFLASH_SwapControlOptionDisableSystem = 0x10U /*!< An option used to disable the Swap status */ -} flash_swap_control_option_t; - -/*! - * @brief Enumeration for the possible flash Swap status. - */ -typedef enum _flash_swap_state -{ - kFLASH_SwapStateUninitialized = 0x00U, /*!< Flash Swap system is in an uninitialized state.*/ - kFLASH_SwapStateReady = 0x01U, /*!< Flash Swap system is in a ready state.*/ - kFLASH_SwapStateUpdate = 0x02U, /*!< Flash Swap system is in an update state.*/ - kFLASH_SwapStateUpdateErased = 0x03U, /*!< Flash Swap system is in an updateErased state.*/ - kFLASH_SwapStateComplete = 0x04U, /*!< Flash Swap system is in a complete state.*/ - kFLASH_SwapStateDisabled = 0x05U /*!< Flash Swap system is in a disabled state.*/ -} flash_swap_state_t; - -/*! - * @breif Enumeration for the possible flash Swap block status - */ -typedef enum _flash_swap_block_status -{ - kFLASH_SwapBlockStatusLowerHalfProgramBlocksAtZero = - 0x00U, /*!< Swap block status is that lower half program block at zero.*/ - kFLASH_SwapBlockStatusUpperHalfProgramBlocksAtZero = - 0x01U, /*!< Swap block status is that upper half program block at zero.*/ -} flash_swap_block_status_t; - -/*! - * @brief Flash Swap information - */ -typedef struct _flash_swap_state_config -{ - flash_swap_state_t flashSwapState; /*!chip < FB_CSAR_COUNT); assert(config->waitStates <= 0x3FU); - uint32_t chip = 0; + uint32_t chip = config->chip; uint32_t reg_value = 0; #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) @@ -91,16 +96,14 @@ void FLEXBUS_Init(FB_Type *base, const flexbus_config_t *config) CLOCK_EnableClock(s_flexbusClocks[FLEXBUS_GetInstance(base)]); #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - /* Reset all the register to default state */ - for (chip = 0; chip < FB_CSAR_COUNT; chip++) - { - /* Reset CSMR register, all chips not valid (disabled) */ - base->CS[chip].CSMR = 0x0000U; - /* Set default base address */ - base->CS[chip].CSAR &= (~FB_CSAR_BA_MASK); - /* Reset FB_CSCRx register */ - base->CS[chip].CSCR = 0x0000U; - } + /* Reset the associated register to default state */ + /* Set CSMR register, all chips not valid (disabled) */ + base->CS[chip].CSMR = 0x0000U; + /* Set default base address */ + base->CS[chip].CSAR &= (~FB_CSAR_BA_MASK); + /* Reset FB_CSCRx register */ + base->CS[chip].CSCR = 0x0000U; + /* Set FB_CSPMCR register */ /* FlexBus signal group 1 multiplex control */ reg_value |= kFLEXBUS_MultiplexGroup1_FB_ALE << FB_CSPMCR_GROUP1_SHIFT; @@ -115,9 +118,6 @@ void FLEXBUS_Init(FB_Type *base, const flexbus_config_t *config) /* Write to CSPMCR register */ base->CSPMCR = reg_value; - /* Update chip value */ - chip = config->chip; - /* Base address */ reg_value = config->chipBaseAddress; /* Write to CSAR register */ @@ -168,8 +168,20 @@ void FLEXBUS_Init(FB_Type *base, const flexbus_config_t *config) reg_value |= (uint32_t)config->group5MultiplexControl << FB_CSPMCR_GROUP5_SHIFT; /* Write to CSPMCR register */ base->CSPMCR = reg_value; + /* Enable CSPMCR0[V] to make all chip select registers take effect. */ + if (chip) + { + base->CS[0].CSMR |= FB_CSMR_V_MASK; + } } +/*! + * brief De-initializes a FlexBus instance. + * + * This function disables the clock gate of the FlexBus module clock. + * + * param base FlexBus peripheral address. + */ void FLEXBUS_Deinit(FB_Type *base) { #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) @@ -178,8 +190,39 @@ void FLEXBUS_Deinit(FB_Type *base) #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ } +/*! + * brief Initializes the FlexBus configuration structure. + * + * This function initializes the FlexBus configuration structure to default value. The default + * values are. + code + fbConfig->chip = 0; + fbConfig->writeProtect = 0; + fbConfig->burstWrite = 0; + fbConfig->burstRead = 0; + fbConfig->byteEnableMode = 0; + fbConfig->autoAcknowledge = true; + fbConfig->extendTransferAddress = 0; + fbConfig->secondaryWaitStates = 0; + fbConfig->byteLaneShift = kFLEXBUS_NotShifted; + fbConfig->writeAddressHold = kFLEXBUS_Hold1Cycle; + fbConfig->readAddressHold = kFLEXBUS_Hold1Or0Cycles; + fbConfig->addressSetup = kFLEXBUS_FirstRisingEdge; + fbConfig->portSize = kFLEXBUS_1Byte; + fbConfig->group1MultiplexControl = kFLEXBUS_MultiplexGroup1_FB_ALE; + fbConfig->group2MultiplexControl = kFLEXBUS_MultiplexGroup2_FB_CS4 ; + fbConfig->group3MultiplexControl = kFLEXBUS_MultiplexGroup3_FB_CS5; + fbConfig->group4MultiplexControl = kFLEXBUS_MultiplexGroup4_FB_TBST; + fbConfig->group5MultiplexControl = kFLEXBUS_MultiplexGroup5_FB_TA; + endcode + * param config Pointer to the initialization structure. + * see FLEXBUS_Init + */ void FLEXBUS_GetDefaultConfig(flexbus_config_t *config) { + /* Initializes the configure structure to zero. */ + memset(config, 0, sizeof(*config)); + config->chip = 0; /* Chip 0 FlexBus for validation */ config->writeProtect = 0; /* Write accesses are allowed */ config->burstWrite = 0; /* Burst-Write disable */ diff --git a/ext/hal/nxp/mcux/drivers/kinetis/fsl_flexbus.h b/ext/hal/nxp/mcux/drivers/kinetis/fsl_flexbus.h index f20ed44f055..6accb1b17d9 100644 --- a/ext/hal/nxp/mcux/drivers/kinetis/fsl_flexbus.h +++ b/ext/hal/nxp/mcux/drivers/kinetis/fsl_flexbus.h @@ -1,31 +1,9 @@ /* * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP + * Copyright 2016-2018 NXP + * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * SPDX-License-Identifier: BSD-3-Clause */ #ifndef _FSL_FLEXBUS_H_ @@ -38,15 +16,14 @@ * @{ */ - /******************************************************************************* * Definitions ******************************************************************************/ /*! @name Driver version */ /*@{*/ -#define FSL_FLEXBUS_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) /*!< Version 2.0.1. */ -/*@}*/ +#define FSL_FLEXBUS_DRIVER_VERSION (MAKE_VERSION(2, 0, 2)) /*!< Version 2.0.2. */ + /*@}*/ /*! * @brief Defines port size for FlexBus peripheral. diff --git a/ext/hal/nxp/mcux/drivers/kinetis/fsl_flexcan.c b/ext/hal/nxp/mcux/drivers/kinetis/fsl_flexcan.c index caf73d56b54..5ce709ddbee 100644 --- a/ext/hal/nxp/mcux/drivers/kinetis/fsl_flexcan.c +++ b/ext/hal/nxp/mcux/drivers/kinetis/fsl_flexcan.c @@ -1,40 +1,40 @@ /* * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP + * Copyright 2016-2018 NXP + * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * SPDX-License-Identifier: BSD-3-Clause */ #include "fsl_flexcan.h" /******************************************************************************* - * Definitons + * Definitions ******************************************************************************/ -#define FLEXCAN_TIME_QUANTA_NUM (10) +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.flexcan" +#endif + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_6032) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_6032) +/*! @name DBG1 - Debug 1 register */ +#if !(defined(CAN_DBG1_CFSM_MASK) && defined(CAN_DBG1_CBN_MASK)) +#define CAN_DBG1_CFSM_MASK (0x7FU) +#define CAN_DBG1_CFSM_SHIFT (0U) +#define CAN_DBG1_CFSM(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBG1_CFSM_SHIFT)) & CAN_DBG1_CFSM_MASK) +#define CAN_DBG1_CBN_MASK (0x3FF0000U) +#define CAN_DBG1_CBN_SHIFT (16U) +#define CAN_DBG1_CBN(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBG1_CBN_SHIFT)) & CAN_DBG1_CBN_MASK) +#endif + +#define OFFSET_DBG1 (0x58U) +#define RXINTERMISSION (CAN_DBG1_CFSM(0x2f)) +#define TXINTERMISSION (CAN_DBG1_CFSM(0x14)) +#define BUSIDLE (CAN_DBG1_CFSM(0x02)) +#define CBN_VALUE3 (CAN_DBG1_CBN(0x03)) +#define DELAY_BUSIDLE (200) +#endif /*! @brief FlexCAN Internal State. */ enum _flexcan_state @@ -80,14 +80,6 @@ typedef void (*flexcan_isr_t)(CAN_Type *base, flexcan_handle_t *handle); * Prototypes ******************************************************************************/ -/*! - * @brief Get the FlexCAN instance from peripheral base address. - * - * @param base FlexCAN peripheral base address. - * @return FlexCAN instance. - */ -uint32_t FLEXCAN_GetInstance(CAN_Type *base); - /*! * @brief Enter FlexCAN Freeze Mode. * @@ -118,7 +110,8 @@ static void FLEXCAN_ExitFreezeMode(CAN_Type *base); static bool FLEXCAN_IsMbOccupied(CAN_Type *base, uint8_t mbIdx); #endif -#if (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) +#if ((defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) || \ + (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5829) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5829)) /*! * @brief Get the first valid Message buffer ID of give FlexCAN instance. * @@ -159,8 +152,12 @@ static void FLEXCAN_Reset(CAN_Type *base); * @param base FlexCAN peripheral base address. * @param sourceClock_Hz Source Clock in Hz. * @param baudRate_Bps Baud Rate in Bps. + * @param timingConfig FlexCAN timingConfig. */ -static void FLEXCAN_SetBaudRate(CAN_Type *base, uint32_t sourceClock_Hz, uint32_t baudRate_Bps); +static void FLEXCAN_SetBaudRate(CAN_Type *base, + uint32_t sourceClock_Hz, + uint32_t baudRate_Bps, + flexcan_timing_config_t timingConfig); #if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) /*! @@ -171,8 +168,27 @@ static void FLEXCAN_SetBaudRate(CAN_Type *base, uint32_t sourceClock_Hz, uint32_ * @param base FlexCAN peripheral base address. * @param sourceClock_Hz Source Clock in Hz. * @param baudRateFD_Bps FD frame Baud Rate in Bps. + * @param timingConfig FlexCAN timingConfig. */ -static void FLEXCAN_SetFDBaudRate(CAN_Type *base, uint32_t sourceClock_Hz, uint32_t baudRateFD_Bps); +static void FLEXCAN_SetFDBaudRate(CAN_Type *base, + uint32_t sourceClock_Hz, + uint32_t baudRateFD_Bps, + flexcan_timing_config_t timingConfig); + +/*! + * @brief Get Mailbox offset number by dword. + * + * This function gets the offset number of the specified mailbox. + * Mailbox is not consecutive between memory regions when payload is not 8 bytes + * so need to calculate the specified mailbox address. + * For example, in the first memory region, MB[0].CS address is 0x4002_4080. For 32 bytes + * payload frame, the second mailbox is ((1/12)*512 + 1%12*40)/4 = 10, meaning 10 dword + * after the 0x4002_4080, which is actually the address of mailbox MB[1].CS. + * + * @param base FlexCAN peripheral base address. + * @param mbIdx Mailbox index. + */ +static uint32_t FLEXCAN_GetFDMailboxOffset(CAN_Type *base, uint8_t mbIdx); #endif /******************************************************************************* @@ -209,6 +225,12 @@ static flexcan_isr_t s_flexcanIsr; * Code ******************************************************************************/ +/*! + * brief Get the FlexCAN instance from peripheral base address. + * + * param base FlexCAN peripheral base address. + * return FlexCAN instance. + */ uint32_t FLEXCAN_GetInstance(CAN_Type *base) { uint32_t instance; @@ -229,19 +251,61 @@ uint32_t FLEXCAN_GetInstance(CAN_Type *base) static void FLEXCAN_EnterFreezeMode(CAN_Type *base) { +#if (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_9595) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_9595) + uint32_t u32TempMCR = 0U; + uint32_t u32TimeoutCount = 0U; +#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) + uint32_t u32TempIMASK2 = 0U; +#endif + uint32_t u32TempIMASK1 = 0U; +#endif /* Set Freeze, Halt bits. */ + base->MCR |= CAN_MCR_FRZ_MASK; base->MCR |= CAN_MCR_HALT_MASK; - /* Wait until the FlexCAN Module enter freeze mode. */ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_9595) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_9595) + u32TimeoutCount = (uint32_t)FLEXCAN_WAIT_TIMEOUT; + do + { + u32TempMCR = base->MCR; + u32TimeoutCount--; + } while ((!(u32TempMCR & CAN_MCR_FRZACK_MASK)) && (u32TimeoutCount > 0)); + + if (!(u32TempMCR & CAN_MCR_FRZACK_MASK)) + { + /* Backup IMASK register */ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) + u32TempIMASK2 = base->IMASK2; +#endif + u32TempIMASK1 = base->IMASK1; + base->MCR |= CAN_MCR_SOFTRST_MASK; + + /* Wait until until the Soft Reset (SOFTRST in MCR) bit is cleared */ + u32TimeoutCount = (uint32_t)FLEXCAN_WAIT_TIMEOUT; + do + { + u32TempMCR = base->MCR; + u32TimeoutCount--; + } while ((!(u32TempMCR & CAN_MCR_SOFTRST_MASK)) && (u32TimeoutCount > 0)); + /* Reconfigure the MCR and all Interrupt Mask Registers (IMASKn) */ + base->MCR = u32TempMCR; +#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) + base->IMASK2 = u32TempIMASK2; +#endif + base->IMASK1 = u32TempIMASK1; + } +#else while (!(base->MCR & CAN_MCR_FRZACK_MASK)) { } +#endif } static void FLEXCAN_ExitFreezeMode(CAN_Type *base) { /* Clear Freeze, Halt bits. */ base->MCR &= ~CAN_MCR_HALT_MASK; + base->MCR &= ~CAN_MCR_FRZ_MASK; /* Wait until the FlexCAN Module exit freeze mode. */ while (base->MCR & CAN_MCR_FRZACK_MASK) @@ -262,7 +326,8 @@ static bool FLEXCAN_IsMbOccupied(CAN_Type *base, uint8_t mbIdx) /* Calculate the number of last Message Buffer occupied by Rx FIFO. */ lastOccupiedMb = ((lastOccupiedMb + 1) * 2) + 5; -#if (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) +#if ((defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) || \ + (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5829) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5829)) if (mbIdx <= (lastOccupiedMb + 1)) #else if (mbIdx <= lastOccupiedMb) @@ -277,7 +342,8 @@ static bool FLEXCAN_IsMbOccupied(CAN_Type *base, uint8_t mbIdx) } else { -#if (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) +#if ((defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) || \ + (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5829) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5829)) if (0 == mbIdx) { return true; @@ -293,7 +359,8 @@ static bool FLEXCAN_IsMbOccupied(CAN_Type *base, uint8_t mbIdx) } #endif -#if (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) +#if ((defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) || \ + (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5829) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5829)) static uint32_t FLEXCAN_GetFirstValidMb(CAN_Type *base) { uint32_t firstValidMbNum; @@ -354,9 +421,12 @@ static void FLEXCAN_Reset(CAN_Type *base) uint8_t i; -#if (FSL_FEATURE_FLEXCAN_HAS_DOZE_MODE_SUPPORT != 0) - /* De-assert DOZE Enable Bit. */ - base->MCR &= ~CAN_MCR_DOZE_MASK; +#if (defined(FSL_FEATURE_FLEXCAN_HAS_DOZE_MODE_SUPPORT) && FSL_FEATURE_FLEXCAN_HAS_DOZE_MODE_SUPPORT) + if (FSL_FEATURE_FLEXCAN_INSTANCE_HAS_DOZE_MODE_SUPPORTn(base)) + { + /* De-assert DOZE Enable Bit. */ + base->MCR &= ~CAN_MCR_DOZE_MASK; + } #endif /* Wait until FlexCAN exit from any Low Power Mode. */ @@ -371,7 +441,7 @@ static void FLEXCAN_Reset(CAN_Type *base) { } -/* Reset MCR rigister. */ +/* Reset MCR register. */ #if (defined(FSL_FEATURE_FLEXCAN_HAS_GLITCH_FILTER) && FSL_FEATURE_FLEXCAN_HAS_GLITCH_FILTER) base->MCR |= CAN_MCR_WRNEN_MASK | CAN_MCR_WAKSRC_MASK | CAN_MCR_MAXMB(FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(base) - 1); @@ -379,8 +449,20 @@ static void FLEXCAN_Reset(CAN_Type *base) base->MCR |= CAN_MCR_WRNEN_MASK | CAN_MCR_MAXMB(FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(base) - 1); #endif - /* Reset CTRL1 and CTRL2 rigister. */ +/* Reset CTRL1 and CTRL2 register. */ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) + /* SMP bit cannot be asserted when CAN FD is enabled */ + if (FSL_FEATURE_FLEXCAN_INSTANCE_HAS_FLEXIBLE_DATA_RATEn(base)) + { + base->CTRL1 = 0x0; + } + else + { + base->CTRL1 = CAN_CTRL1_SMP_MASK; + } +#else base->CTRL1 = CAN_CTRL1_SMP_MASK; +#endif base->CTRL2 = CAN_CTRL2_TASD(0x16) | CAN_CTRL2_RRS_MASK | CAN_CTRL2_EACEN_MASK; /* Clean all individual Rx Mask of Message Buffers. */ @@ -405,14 +487,20 @@ static void FLEXCAN_Reset(CAN_Type *base) } } -static void FLEXCAN_SetBaudRate(CAN_Type *base, uint32_t sourceClock_Hz, uint32_t baudRate_Bps) +static void FLEXCAN_SetBaudRate(CAN_Type *base, + uint32_t sourceClock_Hz, + uint32_t baudRate_Bps, + flexcan_timing_config_t timingConfig) { - flexcan_timing_config_t timingConfig; - uint32_t priDiv = baudRate_Bps * FLEXCAN_TIME_QUANTA_NUM; + /* FlexCAN timing setting formula: + * quantum = 1 + (PSEG1 + 1) + (PSEG2 + 1) + (PROPSEG + 1); + */ + uint32_t quantum = 1 + (timingConfig.phaseSeg1 + 1) + (timingConfig.phaseSeg2 + 1) + (timingConfig.propSeg + 1); + uint32_t priDiv = baudRate_Bps * quantum; /* Assertion: Desired baud rate is too high. */ assert(baudRate_Bps <= 1000000U); - /* Assertion: Source clock should greater than baud rate * FLEXCAN_TIME_QUANTA_NUM. */ + /* Assertion: Source clock should greater than baud rate * quantum. */ assert(priDiv <= sourceClock_Hz); if (0 == priDiv) @@ -428,27 +516,26 @@ static void FLEXCAN_SetBaudRate(CAN_Type *base, uint32_t sourceClock_Hz, uint32_ priDiv = 0xFF; } - /* FlexCAN timing setting formula: - * FLEXCAN_TIME_QUANTA_NUM = 1 + (PSEG1 + 1) + (PSEG2 + 1) + (PROPSEG + 1); - */ timingConfig.preDivider = priDiv; - timingConfig.phaseSeg1 = 3; - timingConfig.phaseSeg2 = 2; - timingConfig.propSeg = 1; - timingConfig.rJumpwidth = 1; /* Update actual timing characteristic. */ FLEXCAN_SetTimingConfig(base, &timingConfig); } #if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) -static void FLEXCAN_SetFDBaudRate(CAN_Type *base, uint32_t sourceClock_Hz, uint32_t baudRateFD_Bps) +static void FLEXCAN_SetFDBaudRate(CAN_Type *base, + uint32_t sourceClock_Hz, + uint32_t baudRateFD_Bps, + flexcan_timing_config_t timingConfig) { - flexcan_timing_config_t timingConfig; - uint32_t priDiv = baudRateFD_Bps * FLEXCAN_TIME_QUANTA_NUM; + /* FlexCAN FD timing setting formula: + * quantum = 1 + (FPSEG1 + 1) + (FPSEG2 + 1) + FPROPSEG; + */ + uint32_t quantum = 1 + (timingConfig.fphaseSeg1 + 1) + (timingConfig.fphaseSeg2 + 1) + timingConfig.fpropSeg; + uint32_t priDiv = baudRateFD_Bps * quantum; /* Assertion: Desired baud rate is too high. */ - assert(baudRateFD_Bps <= 1000000U); + assert(baudRateFD_Bps <= 8000000U); /* Assertion: Source clock should greater than baud rate * FLEXCAN_TIME_QUANTA_NUM. */ assert(priDiv <= sourceClock_Hz); @@ -465,20 +552,36 @@ static void FLEXCAN_SetFDBaudRate(CAN_Type *base, uint32_t sourceClock_Hz, uint3 priDiv = 0xFF; } - /* FlexCAN timing setting formula: - * FLEXCAN_TIME_QUANTA_NUM = 1 + (PSEG1 + 1) + (PSEG2 + 1) + (PROPSEG + 1); - */ - timingConfig.preDivider = priDiv; - timingConfig.phaseSeg1 = 3; - timingConfig.phaseSeg2 = 2; - timingConfig.propSeg = 1; - timingConfig.rJumpwidth = 1; + timingConfig.fpreDivider = priDiv; /* Update actual timing characteristic. */ FLEXCAN_SetFDTimingConfig(base, &timingConfig); } #endif +/*! + * brief Initializes a FlexCAN instance. + * + * This function initializes the FlexCAN module with user-defined settings. + * This example shows how to set up the flexcan_config_t parameters and how + * to call the FLEXCAN_Init function by passing in these parameters. + * code + * flexcan_config_t flexcanConfig; + * flexcanConfig.clkSrc = kFLEXCAN_ClkSrcOsc; + * flexcanConfig.baudRate = 1000000U; + * flexcanConfig.maxMbNum = 16; + * flexcanConfig.enableLoopBack = false; + * flexcanConfig.enableSelfWakeup = false; + * flexcanConfig.enableIndividMask = false; + * flexcanConfig.enableDoze = false; + * flexcanConfig.timingConfig = timingConfig; + * FLEXCAN_Init(CAN0, &flexcanConfig, 8000000UL); + * endcode + * + * param base FlexCAN peripheral base address. + * param config Pointer to the user-defined configuration structure. + * param sourceClock_Hz FlexCAN Protocol Engine clock source frequency in Hz. + */ void FLEXCAN_Init(CAN_Type *base, const flexcan_config_t *config, uint32_t sourceClock_Hz) { uint32_t mcrTemp; @@ -509,9 +612,23 @@ void FLEXCAN_Init(CAN_Type *base, const flexcan_config_t *config, uint32_t sourc */ base->CTRL1 = (kFLEXCAN_ClkSrcOsc == config->clkSrc) ? base->CTRL1 & ~CAN_CTRL1_CLKSRC_MASK : base->CTRL1 | CAN_CTRL1_CLKSRC_MASK; +#else +#if defined(CAN_CTRL1_CLKSRC_MASK) + if (!FSL_FEATURE_FLEXCAN_INSTANCE_SUPPORT_ENGINE_CLK_SEL_REMOVEn(base)) + { + /* Disable FlexCAN Module. */ + FLEXCAN_Enable(base, false); + + /* Protocol-Engine clock source selection, This bit must be set + * when FlexCAN Module in Disable Mode. + */ + base->CTRL1 = (kFLEXCAN_ClkSrcOsc == config->clkSrc) ? base->CTRL1 & ~CAN_CTRL1_CLKSRC_MASK : + base->CTRL1 | CAN_CTRL1_CLKSRC_MASK; + } +#endif #endif /* FSL_FEATURE_FLEXCAN_SUPPORT_ENGINE_CLK_SEL_REMOVE */ - /* Enable FlexCAN Module for configuartion. */ + /* Enable FlexCAN Module for configuration. */ FLEXCAN_Enable(base, true); /* Reset to known status. */ @@ -526,27 +643,109 @@ void FLEXCAN_Init(CAN_Type *base, const flexcan_config_t *config, uint32_t sourc /* Enable Loop Back Mode? */ base->CTRL1 = (config->enableLoopBack) ? base->CTRL1 | CAN_CTRL1_LPB_MASK : base->CTRL1 & ~CAN_CTRL1_LPB_MASK; - /* Enable Self Wake Up Mode? */ + /* Enable Timer Sync? */ + base->CTRL1 = (config->enableTimerSync) ? base->CTRL1 | CAN_CTRL1_TSYN_MASK : base->CTRL1 & ~CAN_CTRL1_TSYN_MASK; + + /* Enable Self Wake Up Mode and configure the wake up source. */ mcrTemp = (config->enableSelfWakeup) ? mcrTemp | CAN_MCR_SLFWAK_MASK : mcrTemp & ~CAN_MCR_SLFWAK_MASK; + mcrTemp = (kFLEXCAN_WakeupSrcFiltered == config->wakeupSrc) ? mcrTemp | CAN_MCR_WAKSRC_MASK : + mcrTemp & ~CAN_MCR_WAKSRC_MASK; /* Enable Individual Rx Masking? */ mcrTemp = (config->enableIndividMask) ? mcrTemp | CAN_MCR_IRMQ_MASK : mcrTemp & ~CAN_MCR_IRMQ_MASK; #if (defined(FSL_FEATURE_FLEXCAN_HAS_DOZE_MODE_SUPPORT) && FSL_FEATURE_FLEXCAN_HAS_DOZE_MODE_SUPPORT) - /* Enable Doze Mode? */ - mcrTemp = (config->enableDoze) ? mcrTemp | CAN_MCR_DOZE_MASK : mcrTemp & ~CAN_MCR_DOZE_MASK; + if (FSL_FEATURE_FLEXCAN_INSTANCE_HAS_DOZE_MODE_SUPPORTn(base)) + { + /* Enable Doze Mode? */ + mcrTemp = (config->enableDoze) ? mcrTemp | CAN_MCR_DOZE_MASK : mcrTemp & ~CAN_MCR_DOZE_MASK; + } #endif - /* Save MCR Configuation. */ + /* Save MCR Configuration. */ base->MCR = mcrTemp; /* Baud Rate Configuration.*/ - FLEXCAN_SetBaudRate(base, sourceClock_Hz, config->baudRate); -#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) - FLEXCAN_SetFDBaudRate(base, sourceClock_Hz, config->baudRateFD); -#endif + FLEXCAN_SetBaudRate(base, sourceClock_Hz, config->baudRate, config->timingConfig); } +#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) +/*! + * brief Initializes a FlexCAN instance. + * + * This function initializes the FlexCAN module with user-defined settings. + * This example shows how to set up the flexcan_config_t parameters and how + * to call the FLEXCAN_FDInit function by passing in these parameters. + * code + * flexcan_config_t flexcanConfig; + * flexcanConfig.clkSrc = kFLEXCAN_ClkSrcOsc; + * flexcanConfig.baudRate = 1000000U; + * flexcanConfig.baudRateFD = 2000000U; + * flexcanConfig.maxMbNum = 16; + * flexcanConfig.enableLoopBack = false; + * flexcanConfig.enableSelfWakeup = false; + * flexcanConfig.enableIndividMask = false; + * flexcanConfig.enableDoze = false; + * flexcanConfig.timingConfig = timingConfig; + * FLEXCAN_FDInit(CAN0, &flexcanConfig, 8000000UL, kFLEXCAN_16BperMB, false); + * endcode + * + * param base FlexCAN peripheral base address. + * param config Pointer to the user-defined configuration structure. + * param sourceClock_Hz FlexCAN Protocol Engine clock source frequency in Hz. + * param dataSize FlexCAN FD frame payload size. + * param brs If bitrate switch is enabled in FD mode. + */ +void FLEXCAN_FDInit( + CAN_Type *base, const flexcan_config_t *config, uint32_t sourceClock_Hz, flexcan_mb_size_t dataSize, bool brs) +{ + assert(dataSize <= 3U); + + /* Initialization of classical CAN. */ + FLEXCAN_Init(base, config, sourceClock_Hz); + + /* Extra bitrate setting for CANFD. */ + FLEXCAN_SetFDBaudRate(base, sourceClock_Hz, config->baudRateFD, config->timingConfig); + + /* Enable FD operation and set bitrate switch. */ + if (brs) + { + base->FDCTRL &= CAN_FDCTRL_FDRATE_MASK; + } + else + { + base->FDCTRL &= ~CAN_FDCTRL_FDRATE_MASK; + } + /* Enter Freeze Mode. */ + FLEXCAN_EnterFreezeMode(base); + if (brs && (!config->enableLoopBack)) + { + base->FDCTRL |= CAN_FDCTRL_TDCEN_MASK | CAN_FDCTRL_TDCOFF(0x2U); + } + base->MCR |= CAN_MCR_FDEN_MASK; + base->FDCTRL |= CAN_FDCTRL_MBDSR0(dataSize); +#if defined(CAN_FDCTRL_MBDSR1_MASK) + base->FDCTRL |= CAN_FDCTRL_MBDSR1(dataSize); +#endif +#if defined(CAN_FDCTRL_MBDSR2_MASK) + base->FDCTRL |= CAN_FDCTRL_MBDSR2(dataSize); +#endif +#if defined(CAN_FDCTRL_MBDSR3_MASK) + base->FDCTRL |= CAN_FDCTRL_MBDSR3(dataSize); +#endif + /* Exit Freeze Mode. */ + FLEXCAN_ExitFreezeMode(base); +} +#endif + +/*! + * brief De-initializes a FlexCAN instance. + * + * This function disables the FlexCAN module clock and sets all register values + * to the reset value. + * + * param base FlexCAN peripheral base address. + */ void FLEXCAN_Deinit(CAN_Type *base) { #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) @@ -569,48 +768,73 @@ void FLEXCAN_Deinit(CAN_Type *base) #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ } +/*! + * brief Gets the default configuration structure. + * + * This function initializes the FlexCAN configuration structure to default values. The default + * values are as follows. + * flexcanConfig->clkSrc = kFLEXCAN_ClkSrcOsc; + * flexcanConfig->baudRate = 1000000U; + * flexcanConfig->baudRateFD = 2000000U; + * flexcanConfig->maxMbNum = 16; + * flexcanConfig->enableLoopBack = false; + * flexcanConfig->enableSelfWakeup = false; + * flexcanConfig->enableIndividMask = false; + * flexcanConfig->enableDoze = false; + * flexcanConfig.timingConfig = timingConfig; + * + * param config Pointer to the FlexCAN configuration structure. + */ void FLEXCAN_GetDefaultConfig(flexcan_config_t *config) { /* Assertion. */ assert(config); + /* Initializes the configure structure to zero. */ + memset(config, 0, sizeof(*config)); + /* Initialize FlexCAN Module config struct with default value. */ -#if (!defined(FSL_FEATURE_FLEXCAN_SUPPORT_ENGINE_CLK_SEL_REMOVE)) || !FSL_FEATURE_FLEXCAN_SUPPORT_ENGINE_CLK_SEL_REMOVE config->clkSrc = kFLEXCAN_ClkSrcOsc; -#endif /* FSL_FEATURE_FLEXCAN_SUPPORT_ENGINE_CLK_SEL_REMOVE */ config->baudRate = 1000000U; #if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) - config->baudRateFD = 1000000U; + config->baudRateFD = 2000000U; #endif config->maxMbNum = 16; config->enableLoopBack = false; + config->enableTimerSync = true; config->enableSelfWakeup = false; + config->wakeupSrc = kFLEXCAN_WakeupSrcUnfiltered; config->enableIndividMask = false; #if (defined(FSL_FEATURE_FLEXCAN_HAS_DOZE_MODE_SUPPORT) && FSL_FEATURE_FLEXCAN_HAS_DOZE_MODE_SUPPORT) config->enableDoze = false; #endif -} - + /* Default protocol timing configuration, time quantum is 10. */ + config->timingConfig.phaseSeg1 = 3; + config->timingConfig.phaseSeg2 = 2; + config->timingConfig.propSeg = 1; + config->timingConfig.rJumpwidth = 1; #if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) -void FLEXCAN_FDEnable(CAN_Type *base, flexcan_mb_size_t dataSize, bool brs) -{ - if (brs) - { - base->FDCTRL &= CAN_FDCTRL_FDRATE_MASK; - } - else - { - base->FDCTRL &= ~CAN_FDCTRL_FDRATE_MASK; - } - /* Enter Freeze Mode. */ - FLEXCAN_EnterFreezeMode(base); - base->MCR |= CAN_MCR_FDEN_MASK; - base->FDCTRL |= CAN_FDCTRL_MBDSR0(dataSize); - /* Exit Freeze Mode. */ - FLEXCAN_ExitFreezeMode(base); -} + config->timingConfig.fphaseSeg1 = 3; + config->timingConfig.fphaseSeg2 = 3; + config->timingConfig.fpropSeg = 1; + config->timingConfig.frJumpwidth = 1; #endif +} +/*! + * brief Sets the FlexCAN protocol timing characteristic. + * + * This function gives user settings to CAN bus timing characteristic. + * The function is for an experienced user. For less experienced users, call + * the FLEXCAN_Init() and fill the baud rate field with a desired value. + * This provides the default timing characteristics to the module. + * + * Note that calling FLEXCAN_SetTimingConfig() overrides the baud rate set + * in FLEXCAN_Init(). + * + * param base FlexCAN peripheral base address. + * param config Pointer to the timing configuration structure. + */ void FLEXCAN_SetTimingConfig(CAN_Type *base, const flexcan_timing_config_t *config) { /* Assertion. */ @@ -620,14 +844,28 @@ void FLEXCAN_SetTimingConfig(CAN_Type *base, const flexcan_timing_config_t *conf FLEXCAN_EnterFreezeMode(base); #if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) - /* Cleaning previous Timing Setting. */ - base->CBT &= ~(CAN_CBT_EPRESDIV_MASK | CAN_CBT_ERJW_MASK | CAN_CBT_EPSEG1_MASK | CAN_CBT_EPSEG2_MASK | - CAN_CBT_EPROPSEG_MASK); + if (FSL_FEATURE_FLEXCAN_INSTANCE_HAS_FLEXIBLE_DATA_RATEn(base)) + { + /* Cleaning previous Timing Setting. */ + base->CBT &= ~(CAN_CBT_EPRESDIV_MASK | CAN_CBT_ERJW_MASK | CAN_CBT_EPSEG1_MASK | CAN_CBT_EPSEG2_MASK | + CAN_CBT_EPROPSEG_MASK); - /* Updating Timing Setting according to configuration structure. */ - base->CBT |= - (CAN_CBT_EPRESDIV(config->preDivider) | CAN_CBT_ERJW(config->rJumpwidth) | CAN_CBT_EPSEG1(config->phaseSeg1) | - CAN_CBT_EPSEG2(config->phaseSeg2) | CAN_CBT_EPROPSEG(config->propSeg)); + /* Updating Timing Setting according to configuration structure. */ + base->CBT |= + (CAN_CBT_EPRESDIV(config->preDivider) | CAN_CBT_ERJW(config->rJumpwidth) | + CAN_CBT_EPSEG1(config->phaseSeg1) | CAN_CBT_EPSEG2(config->phaseSeg2) | CAN_CBT_EPROPSEG(config->propSeg)); + } + else + { + /* Cleaning previous Timing Setting. */ + base->CTRL1 &= ~(CAN_CTRL1_PRESDIV_MASK | CAN_CTRL1_RJW_MASK | CAN_CTRL1_PSEG1_MASK | CAN_CTRL1_PSEG2_MASK | + CAN_CTRL1_PROPSEG_MASK); + + /* Updating Timing Setting according to configuration structure. */ + base->CTRL1 |= (CAN_CTRL1_PRESDIV(config->preDivider) | CAN_CTRL1_RJW(config->rJumpwidth) | + CAN_CTRL1_PSEG1(config->phaseSeg1) | CAN_CTRL1_PSEG2(config->phaseSeg2) | + CAN_CTRL1_PROPSEG(config->propSeg)); + } #else /* Cleaning previous Timing Setting. */ base->CTRL1 &= ~(CAN_CTRL1_PRESDIV_MASK | CAN_CTRL1_RJW_MASK | CAN_CTRL1_PSEG1_MASK | CAN_CTRL1_PSEG2_MASK | @@ -644,6 +882,20 @@ void FLEXCAN_SetTimingConfig(CAN_Type *base, const flexcan_timing_config_t *conf } #if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) +/*! + * brief Sets the FlexCAN FD protocol timing characteristic. + * + * This function gives user settings to CAN bus timing characteristic. + * The function is for an experienced user. For less experienced users, call + * the FLEXCAN_Init() and fill the baud rate field with a desired value. + * This provides the default timing characteristics to the module. + * + * Note that calling FLEXCAN_SetFDTimingConfig() overrides the baud rate set + * in FLEXCAN_Init(). + * + * param base FlexCAN peripheral base address. + * param config Pointer to the timing configuration structure. + */ void FLEXCAN_SetFDTimingConfig(CAN_Type *base, const flexcan_timing_config_t *config) { /* Assertion. */ @@ -652,20 +904,30 @@ void FLEXCAN_SetFDTimingConfig(CAN_Type *base, const flexcan_timing_config_t *co /* Enter Freeze Mode. */ FLEXCAN_EnterFreezeMode(base); + base->CBT |= CAN_CBT_BTF(1); /* Cleaning previous Timing Setting. */ base->FDCBT &= ~(CAN_FDCBT_FPRESDIV_MASK | CAN_FDCBT_FRJW_MASK | CAN_FDCBT_FPSEG1_MASK | CAN_FDCBT_FPSEG2_MASK | CAN_FDCBT_FPROPSEG_MASK); /* Updating Timing Setting according to configuration structure. */ - base->FDCBT |= (CAN_FDCBT_FPRESDIV(config->preDivider) | CAN_FDCBT_FRJW(config->rJumpwidth) | - CAN_FDCBT_FPSEG1(config->phaseSeg1) | CAN_FDCBT_FPSEG2(config->phaseSeg2) | - CAN_FDCBT_FPROPSEG(config->propSeg)); + base->FDCBT |= (CAN_FDCBT_FPRESDIV(config->fpreDivider) | CAN_FDCBT_FRJW(config->frJumpwidth) | + CAN_FDCBT_FPSEG1(config->fphaseSeg1) | CAN_FDCBT_FPSEG2(config->fphaseSeg2) | + CAN_FDCBT_FPROPSEG(config->fpropSeg)); /* Exit Freeze Mode. */ FLEXCAN_ExitFreezeMode(base); } #endif +/*! + * brief Sets the FlexCAN receive message buffer global mask. + * + * This function sets the global mask for the FlexCAN message buffer in a matching process. + * The configuration is only effective when the Rx individual mask is disabled in the FLEXCAN_Init(). + * + * param base FlexCAN peripheral base address. + * param mask Rx Message Buffer Global Mask value. + */ void FLEXCAN_SetRxMbGlobalMask(CAN_Type *base, uint32_t mask) { /* Enter Freeze Mode. */ @@ -680,6 +942,14 @@ void FLEXCAN_SetRxMbGlobalMask(CAN_Type *base, uint32_t mask) FLEXCAN_ExitFreezeMode(base); } +/*! + * brief Sets the FlexCAN receive FIFO global mask. + * + * This function sets the global mask for FlexCAN FIFO in a matching process. + * + * param base FlexCAN peripheral base address. + * param mask Rx Fifo Global Mask value. + */ void FLEXCAN_SetRxFifoGlobalMask(CAN_Type *base, uint32_t mask) { /* Enter Freeze Mode. */ @@ -692,6 +962,20 @@ void FLEXCAN_SetRxFifoGlobalMask(CAN_Type *base, uint32_t mask) FLEXCAN_ExitFreezeMode(base); } +/*! + * brief Sets the FlexCAN receive individual mask. + * + * This function sets the individual mask for the FlexCAN matching process. + * The configuration is only effective when the Rx individual mask is enabled in the FLEXCAN_Init(). + * If the Rx FIFO is disabled, the individual mask is applied to the corresponding Message Buffer. + * If the Rx FIFO is enabled, the individual mask for Rx FIFO occupied Message Buffer is applied to + * the Rx Filter with the same index. Note that only the first 32 + * individual masks can be used as the Rx FIFO filter mask. + * + * param base FlexCAN peripheral base address. + * param maskIdx The Index of individual Mask. + * param mask Rx Individual Mask value. + */ void FLEXCAN_SetRxIndividualMask(CAN_Type *base, uint8_t maskIdx, uint32_t mask) { assert(maskIdx <= (base->MCR & CAN_MCR_MAXMB_MASK)); @@ -706,6 +990,18 @@ void FLEXCAN_SetRxIndividualMask(CAN_Type *base, uint8_t maskIdx, uint32_t mask) FLEXCAN_ExitFreezeMode(base); } +/*! + * brief Configures a FlexCAN transmit message buffer. + * + * This function aborts the previous transmission, cleans the Message Buffer, and + * configures it as a Transmit Message Buffer. + * + * param base FlexCAN peripheral base address. + * param mbIdx The Message Buffer index. + * param enable Enable/disable Tx Message Buffer. + * - true: Enable Tx Message Buffer. + * - false: Disable Tx Message Buffer. + */ void FLEXCAN_SetTxMbConfig(CAN_Type *base, uint8_t mbIdx, bool enable) { /* Assertion. */ @@ -729,94 +1025,109 @@ void FLEXCAN_SetTxMbConfig(CAN_Type *base, uint8_t mbIdx, bool enable) } #if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) +static uint32_t FLEXCAN_GetFDMailboxOffset(CAN_Type *base, uint8_t mbIdx) +{ + uint32_t dataSize; + uint32_t offset = 0; + dataSize = (base->FDCTRL & CAN_FDCTRL_MBDSR0_MASK) >> CAN_FDCTRL_MBDSR0_SHIFT; + switch (dataSize) + { + case kFLEXCAN_8BperMB: + offset = (mbIdx / 32) * 512 + mbIdx % 32 * 16; + break; + case kFLEXCAN_16BperMB: + offset = (mbIdx / 21) * 512 + mbIdx % 21 * 24; + break; + case kFLEXCAN_32BperMB: + offset = (mbIdx / 12) * 512 + mbIdx % 12 * 40; + break; + case kFLEXCAN_64BperMB: + offset = (mbIdx / 7) * 512 + mbIdx % 7 * 72; + break; + default: + break; + } + /* To get the dword aligned offset, need to divide by 4. */ + offset = offset / 4; + return offset; +} +#endif + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) +/*! + * brief Configures a FlexCAN transmit message buffer. + * + * This function aborts the previous transmission, cleans the Message Buffer, and + * configures it as a Transmit Message Buffer. + * + * param base FlexCAN peripheral base address. + * param mbIdx The Message Buffer index. + * param enable Enable/disable Tx Message Buffer. + * - true: Enable Tx Message Buffer. + * - false: Disable Tx Message Buffer. + */ void FLEXCAN_SetFDTxMbConfig(CAN_Type *base, uint8_t mbIdx, bool enable) { /* Assertion. */ assert(mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK)); assert(!FLEXCAN_IsMbOccupied(base, mbIdx)); uint8_t cnt = 0; + uint8_t payload_dword = 1; uint32_t dataSize; dataSize = (base->FDCTRL & CAN_FDCTRL_MBDSR0_MASK) >> CAN_FDCTRL_MBDSR0_SHIFT; + volatile uint32_t *mbAddr = &(base->MB[0].CS); + uint32_t offset = FLEXCAN_GetFDMailboxOffset(base, mbIdx); +#if ((defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) || \ + (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5829) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5829)) + uint32_t availoffset = FLEXCAN_GetFDMailboxOffset(base, FLEXCAN_GetFirstValidMb(base)); +#endif /* Inactivate Message Buffer. */ if (enable) { - switch (dataSize) - { - case kFLEXCAN_8BperMB: - base->MB_8B[mbIdx].CS = CAN_CS_CODE(kFLEXCAN_TxMbInactive); - break; - case kFLEXCAN_16BperMB: - base->MB_16B[mbIdx].CS = CAN_CS_CODE(kFLEXCAN_TxMbInactive); - break; - case kFLEXCAN_32BperMB: - base->MB_32B[mbIdx].CS = CAN_CS_CODE(kFLEXCAN_TxMbInactive); - break; - case kFLEXCAN_64BperMB: - base->MB_64B[mbIdx].CS = CAN_CS_CODE(kFLEXCAN_TxMbInactive); - break; - default: - break; - } + /* Inactivate by writing CS. */ + mbAddr[offset] = CAN_CS_CODE(kFLEXCAN_TxMbInactive); } else { - switch (dataSize) - { - case kFLEXCAN_8BperMB: - base->MB_8B[mbIdx].CS = 0; - break; - case kFLEXCAN_16BperMB: - base->MB_16B[mbIdx].CS = 0; - break; - case kFLEXCAN_32BperMB: - base->MB_32B[mbIdx].CS = 0; - break; - case kFLEXCAN_64BperMB: - base->MB_64B[mbIdx].CS = 0; - break; - default: - break; - } + mbAddr[offset] = 0x0; } - /* Clean ID and Message Buffer content. */ - switch (dataSize) + /* Calculate the DWORD number, dataSize 0/1/2/3 corresponds to 8/16/32/64 + Bytes payload. */ + for (cnt = 0; cnt < dataSize + 1; cnt++) { - case kFLEXCAN_8BperMB: - base->MB_8B[mbIdx].ID = 0x0; - for (cnt = 0; cnt < 2; cnt++) - { - base->MB_8B[mbIdx].WORD[cnt] = 0x0; - } - break; - case kFLEXCAN_16BperMB: - base->MB_16B[mbIdx].ID = 0x0; - for (cnt = 0; cnt < 4; cnt++) - { - base->MB_16B[mbIdx].WORD[cnt] = 0x0; - } - break; - case kFLEXCAN_32BperMB: - base->MB_32B[mbIdx].ID = 0x0; - for (cnt = 0; cnt < 8; cnt++) - { - base->MB_32B[mbIdx].WORD[cnt] = 0x0; - } - break; - case kFLEXCAN_64BperMB: - base->MB_64B[mbIdx].ID = 0x0; - for (cnt = 0; cnt < 16; cnt++) - { - base->MB_64B[mbIdx].WORD[cnt] = 0x0; - } - break; - default: - break; + payload_dword *= 2; } + + /* Clean ID. */ + mbAddr[offset + 1] = 0x0; + /* Clean Message Buffer content, DWORD by DWORD. */ + for (cnt = 0; cnt < payload_dword; cnt++) + { + mbAddr[offset + 2 + cnt] = 0x0; + } + +#if ((defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) || \ + (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5829) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5829)) + mbAddr[availoffset] = CAN_CS_CODE(kFLEXCAN_TxMbInactive); +#endif } #endif +/*! + * brief Configures a FlexCAN Receive Message Buffer. + * + * This function cleans a FlexCAN build-in Message Buffer and configures it + * as a Receive Message Buffer. + * + * param base FlexCAN peripheral base address. + * param mbIdx The Message Buffer index. + * param config Pointer to the FlexCAN Message Buffer configuration structure. + * param enable Enable/disable Rx Message Buffer. + * - true: Enable Rx Message Buffer. + * - false: Disable Rx Message Buffer. + */ void FLEXCAN_SetRxMbConfig(CAN_Type *base, uint8_t mbIdx, const flexcan_rx_mb_config_t *config, bool enable) { /* Assertion. */ @@ -858,6 +1169,19 @@ void FLEXCAN_SetRxMbConfig(CAN_Type *base, uint8_t mbIdx, const flexcan_rx_mb_co } #if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) +/*! + * brief Configures a FlexCAN Receive Message Buffer. + * + * This function cleans a FlexCAN build-in Message Buffer and configures it + * as a Receive Message Buffer. + * + * param base FlexCAN peripheral base address. + * param mbIdx The Message Buffer index. + * param config Pointer to the FlexCAN Message Buffer configuration structure. + * param enable Enable/disable Rx Message Buffer. + * - true: Enable Rx Message Buffer. + * - false: Disable Rx Message Buffer. + */ void FLEXCAN_SetFDRxMbConfig(CAN_Type *base, uint8_t mbIdx, const flexcan_rx_mb_config_t *config, bool enable) { /* Assertion. */ @@ -867,68 +1191,22 @@ void FLEXCAN_SetFDRxMbConfig(CAN_Type *base, uint8_t mbIdx, const flexcan_rx_mb_ uint32_t cs_temp = 0; uint8_t cnt = 0; - uint32_t dataSize; - dataSize = (base->FDCTRL & CAN_FDCTRL_MBDSR0_MASK) >> CAN_FDCTRL_MBDSR0_SHIFT; + volatile uint32_t *mbAddr = &(base->MB[0].CS); + uint32_t offset = FLEXCAN_GetFDMailboxOffset(base, mbIdx); - /* Inactivate Message Buffer and clean ID, Message Buffer content. */ - switch (dataSize) + /* Inactivate all mailboxes first, clean ID and Message Buffer content. */ + for (cnt = 0; cnt < FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(base); cnt++) { - case kFLEXCAN_8BperMB: - base->MB_8B[mbIdx].CS = 0; - base->MB_8B[mbIdx].ID = 0x0; - for (cnt = 0; cnt < 2; cnt++) - { - base->MB_8B[mbIdx].WORD[cnt] = 0x0; - } - break; - case kFLEXCAN_16BperMB: - base->MB_16B[mbIdx].CS = 0; - base->MB_16B[mbIdx].ID = 0x0; - for (cnt = 0; cnt < 4; cnt++) - { - base->MB_16B[mbIdx].WORD[cnt] = 0x0; - } - break; - case kFLEXCAN_32BperMB: - base->MB_32B[mbIdx].CS = 0; - base->MB_32B[mbIdx].ID = 0x0; - for (cnt = 0; cnt < 8; cnt++) - { - base->MB_32B[mbIdx].WORD[cnt] = 0x0; - } - break; - case kFLEXCAN_64BperMB: - base->MB_64B[mbIdx].CS = 0; - base->MB_64B[mbIdx].ID = 0x0; - for (cnt = 0; cnt < 16; cnt++) - { - base->MB_64B[mbIdx].WORD[cnt] = 0x0; - } - break; - default: - break; + base->MB[cnt].CS = 0; + base->MB[cnt].ID = 0; + base->MB[cnt].WORD0 = 0; + base->MB[cnt].WORD1 = 0; } if (enable) { /* Setup Message Buffer ID. */ - switch (dataSize) - { - case kFLEXCAN_8BperMB: - base->MB_8B[mbIdx].ID = config->id; - break; - case kFLEXCAN_16BperMB: - base->MB_16B[mbIdx].ID = config->id; - break; - case kFLEXCAN_32BperMB: - base->MB_32B[mbIdx].ID = config->id; - break; - case kFLEXCAN_64BperMB: - base->MB_64B[mbIdx].ID = config->id; - break; - default: - break; - } + mbAddr[offset + 1] = config->id; /* Setup Message Buffer format. */ if (kFLEXCAN_FrameFormatExtend == config->format) @@ -938,27 +1216,22 @@ void FLEXCAN_SetFDRxMbConfig(CAN_Type *base, uint8_t mbIdx, const flexcan_rx_mb_ /* Activate Rx Message Buffer. */ cs_temp |= CAN_CS_CODE(kFLEXCAN_RxMbEmpty); - switch (dataSize) - { - case kFLEXCAN_8BperMB: - base->MB_8B[mbIdx].CS = cs_temp; - break; - case kFLEXCAN_16BperMB: - base->MB_16B[mbIdx].CS = cs_temp; - break; - case kFLEXCAN_32BperMB: - base->MB_32B[mbIdx].CS = cs_temp; - break; - case kFLEXCAN_64BperMB: - base->MB_64B[mbIdx].CS = cs_temp; - break; - default: - break; - } + mbAddr[offset] = cs_temp; } } #endif +/*! + * brief Configures the FlexCAN Rx FIFO. + * + * This function configures the Rx FIFO with given Rx FIFO configuration. + * + * param base FlexCAN peripheral base address. + * param config Pointer to the FlexCAN Rx FIFO configuration structure. + * param enable Enable/disable Rx FIFO. + * - true: Enable Rx FIFO. + * - false: Disable Rx FIFO. + */ void FLEXCAN_SetRxFifoConfig(CAN_Type *base, const flexcan_rx_fifo_config_t *config, bool enable) { /* Assertion. */ @@ -1065,6 +1338,14 @@ void FLEXCAN_SetRxFifoConfig(CAN_Type *base, const flexcan_rx_fifo_config_t *con } #if (defined(FSL_FEATURE_FLEXCAN_HAS_RX_FIFO_DMA) && FSL_FEATURE_FLEXCAN_HAS_RX_FIFO_DMA) +/*! + * brief Enables or disables the FlexCAN Rx FIFO DMA request. + * + * This function enables or disables the DMA feature of FlexCAN build-in Rx FIFO. + * + * param base FlexCAN peripheral base address. + * param enable true to enable, false to disable. + */ void FLEXCAN_EnableRxFifoDMA(CAN_Type *base, bool enable) { if (enable) @@ -1092,6 +1373,86 @@ void FLEXCAN_EnableRxFifoDMA(CAN_Type *base, bool enable) } #endif /* FSL_FEATURE_FLEXCAN_HAS_RX_FIFO_DMA */ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_6032) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_6032) +/*! + * FlexCAN: A frame with wrong ID or payload is transmitted into + * the CAN bus when the Message Buffer under transmission is + * either aborted or deactivated while the CAN bus is in the Bus Idle state + * + * This function to do workaround for ERR006032 + * + * param base FlexCAN peripheral base address. + * param mbIdx The FlexCAN Message Buffer index. + */ +static void FLEXCAN_ERRATA_6032(CAN_Type *base, uint8_t mbIdx) +{ + uint32_t dbg_temp = 0U; + volatile const uint32_t *dbg1Addr = &(base->MCR) + OFFSET_DBG1 / 4; + /*after backup all interruption, disable ALL interruption*/ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) + uint32_t u32TempIMASK2 = base->IMASK2; + base->IMASK2 = 0; +#endif + uint32_t u32TempIMASK1 = base->IMASK1; + base->IMASK1 = 0; + dbg_temp = (uint32_t)(*dbg1Addr); + switch (dbg_temp & CAN_DBG1_CBN_MASK) + { + case RXINTERMISSION: + if ((dbg_temp & CAN_DBG1_CBN_MASK) == CBN_VALUE3) + { + /*wait until CFSM is different from RXINTERMISSION */ + while ((((uint32_t)(*dbg1Addr)) & CAN_DBG1_CBN_MASK) == RXINTERMISSION) + { + __NOP(); + } + } + break; + case TXINTERMISSION: + if ((dbg_temp & CAN_DBG1_CBN_MASK) == CBN_VALUE3) + { + /*wait until CFSM is different from TXINTERMISSION*/ + while ((((uint32_t)(*dbg1Addr)) & CAN_DBG1_CBN_MASK) == TXINTERMISSION) + { + __NOP(); + } + } + break; + default: + break; + } + /*Anyway, BUSIDLE need to delay*/ + if ((((uint32_t)(*dbg1Addr)) & CAN_DBG1_CBN_MASK) == BUSIDLE) + { + uint32_t n = DELAY_BUSIDLE; + while (n-- > 0) + { + __NOP(); + } + } + /*Write 0x0 into Code field of CS word.*/ + base->MB[mbIdx].CS &= ~CAN_CS_CODE_MASK; +/*restore interruption*/ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) + base->IMASK2 = u32TempIMASK2; +#endif + base->IMASK1 = u32TempIMASK1; +} +#endif + +/*! + * brief Writes a FlexCAN Message to the Transmit Message Buffer. + * + * This function writes a CAN Message to the specified Transmit Message Buffer + * and changes the Message Buffer state to start CAN Message transmit. After + * that the function returns immediately. + * + * param base FlexCAN peripheral base address. + * param mbIdx The FlexCAN Message Buffer index. + * param txFrame Pointer to CAN message frame to be sent. + * retval kStatus_Success - Write Tx Message Buffer Successfully. + * retval kStatus_Fail - Tx Message Buffer is currently in use. + */ status_t FLEXCAN_WriteTxMb(CAN_Type *base, uint8_t mbIdx, const flexcan_frame_t *txFrame) { /* Assertion. */ @@ -1102,6 +1463,9 @@ status_t FLEXCAN_WriteTxMb(CAN_Type *base, uint8_t mbIdx, const flexcan_frame_t uint32_t cs_temp = 0; +#if (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_6032) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_6032) + FLEXCAN_ERRATA_6032(base, mbIdx); +#endif /* Check if Message Buffer is available. */ if (CAN_CS_CODE(kFLEXCAN_TxMbDataOrRemote) != (base->MB[mbIdx].CS & CAN_CS_CODE_MASK)) { @@ -1132,7 +1496,8 @@ status_t FLEXCAN_WriteTxMb(CAN_Type *base, uint8_t mbIdx, const flexcan_frame_t /* Activate Tx Message Buffer. */ base->MB[mbIdx].CS = cs_temp; -#if (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) +#if ((defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) || \ + (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5829) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5829)) base->MB[FLEXCAN_GetFirstValidMb(base)].CS = CAN_CS_CODE(kFLEXCAN_TxMbInactive); base->MB[FLEXCAN_GetFirstValidMb(base)].CS = CAN_CS_CODE(kFLEXCAN_TxMbInactive); #endif @@ -1147,62 +1512,49 @@ status_t FLEXCAN_WriteTxMb(CAN_Type *base, uint8_t mbIdx, const flexcan_frame_t } #if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) +/*! + * brief Writes a FlexCAN FD Message to the Transmit Message Buffer. + * + * This function writes a CAN FD Message to the specified Transmit Message Buffer + * and changes the Message Buffer state to start CAN FD Message transmit. After + * that the function returns immediately. + * + * param base FlexCAN peripheral base address. + * param mbIdx The FlexCAN FD Message Buffer index. + * param txFrame Pointer to CAN FD message frame to be sent. + * retval kStatus_Success - Write Tx Message Buffer Successfully. + * retval kStatus_Fail - Tx Message Buffer is currently in use. + */ status_t FLEXCAN_WriteFDTxMb(CAN_Type *base, uint8_t mbIdx, const flexcan_fd_frame_t *txFrame) { /* Assertion. */ assert(mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK)); assert(txFrame); - assert(txFrame->length <= 15); assert(!FLEXCAN_IsMbOccupied(base, mbIdx)); uint32_t cs_temp = 0; uint8_t cnt = 0; uint32_t can_cs = 0; + uint8_t payload_dword = 1; uint32_t dataSize; +#if (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_6032) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_6032) + FLEXCAN_ERRATA_6032(base, mbIdx); +#endif dataSize = (base->FDCTRL & CAN_FDCTRL_MBDSR0_MASK) >> CAN_FDCTRL_MBDSR0_SHIFT; +#if ((defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) || \ + (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5829) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5829)) + uint32_t availoffset = FLEXCAN_GetFDMailboxOffset(base, FLEXCAN_GetFirstValidMb(base)); +#endif + volatile uint32_t *mbAddr = &(base->MB[0].CS); + uint32_t offset = FLEXCAN_GetFDMailboxOffset(base, mbIdx); - switch (dataSize) - { - case kFLEXCAN_8BperMB: - can_cs = base->MB_8B[mbIdx].CS; - break; - case kFLEXCAN_16BperMB: - can_cs = base->MB_16B[mbIdx].CS; - break; - case kFLEXCAN_32BperMB: - can_cs = base->MB_32B[mbIdx].CS; - break; - case kFLEXCAN_64BperMB: - can_cs = base->MB_64B[mbIdx].CS; - break; - default: - break; - } + can_cs = mbAddr[0]; /* Check if Message Buffer is available. */ if (CAN_CS_CODE(kFLEXCAN_TxMbDataOrRemote) != (can_cs & CAN_CS_CODE_MASK)) { /* Inactive Tx Message Buffer and Fill Message ID field. */ - switch (dataSize) - { - case kFLEXCAN_8BperMB: - base->MB_8B[mbIdx].CS = (can_cs & ~CAN_CS_CODE_MASK) | CAN_CS_CODE(kFLEXCAN_TxMbInactive); - base->MB_8B[mbIdx].ID = txFrame->id; - break; - case kFLEXCAN_16BperMB: - base->MB_16B[mbIdx].CS = (can_cs & ~CAN_CS_CODE_MASK) | CAN_CS_CODE(kFLEXCAN_TxMbInactive); - base->MB_16B[mbIdx].ID = txFrame->id; - break; - case kFLEXCAN_32BperMB: - base->MB_32B[mbIdx].CS = (can_cs & ~CAN_CS_CODE_MASK) | CAN_CS_CODE(kFLEXCAN_TxMbInactive); - base->MB_32B[mbIdx].ID = txFrame->id; - break; - case kFLEXCAN_64BperMB: - base->MB_64B[mbIdx].CS = (can_cs & ~CAN_CS_CODE_MASK) | CAN_CS_CODE(kFLEXCAN_TxMbInactive); - base->MB_64B[mbIdx].ID = txFrame->id; - break; - default: - break; - } + mbAddr[offset] = (can_cs & ~CAN_CS_CODE_MASK) | CAN_CS_CODE(kFLEXCAN_TxMbInactive); + mbAddr[offset + 1] = txFrame->id; /* Fill Message Format field. */ if (kFLEXCAN_FrameFormatExtend == txFrame->format) @@ -1210,46 +1562,27 @@ status_t FLEXCAN_WriteFDTxMb(CAN_Type *base, uint8_t mbIdx, const flexcan_fd_fra cs_temp |= CAN_CS_SRR_MASK | CAN_CS_IDE_MASK; } - cs_temp |= CAN_CS_CODE(kFLEXCAN_TxMbDataOrRemote) | CAN_CS_DLC(txFrame->length) | CAN_CS_EDL(1); + cs_temp |= CAN_CS_CODE(kFLEXCAN_TxMbDataOrRemote) | CAN_CS_DLC(txFrame->length) | CAN_CS_EDL(1) | + CAN_CS_BRS(txFrame->brs); - /* Load Message Payload and Activate Tx Message Buffer. */ - switch (dataSize) + /* Calculate the DWORD number, dataSize 0/1/2/3 corresponds to 8/16/32/64 + Bytes payload. */ + for (cnt = 0; cnt < dataSize + 1; cnt++) { - case kFLEXCAN_8BperMB: - for (cnt = 0; cnt < 2; cnt++) - { - base->MB_8B[mbIdx].WORD[cnt] = txFrame->dataWord[cnt]; - } - base->MB_8B[mbIdx].CS = cs_temp; - break; - case kFLEXCAN_16BperMB: - for (cnt = 0; cnt < 4; cnt++) - { - base->MB_16B[mbIdx].WORD[cnt] = txFrame->dataWord[cnt]; - } - base->MB_16B[mbIdx].CS = cs_temp; - break; - case kFLEXCAN_32BperMB: - for (cnt = 0; cnt < 8; cnt++) - { - base->MB_32B[mbIdx].WORD[cnt] = txFrame->dataWord[cnt]; - } - base->MB_32B[mbIdx].CS = cs_temp; - break; - case kFLEXCAN_64BperMB: - for (cnt = 0; cnt < 16; cnt++) - { - base->MB_64B[mbIdx].WORD[cnt] = txFrame->dataWord[cnt]; - } - base->MB_64B[mbIdx].CS = cs_temp; - break; - default: - break; + payload_dword *= 2; } -#if (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) - base->MB[FLEXCAN_GetFirstValidMb(base)].CS = CAN_CS_CODE(kFLEXCAN_TxMbInactive); - base->MB[FLEXCAN_GetFirstValidMb(base)].CS = CAN_CS_CODE(kFLEXCAN_TxMbInactive); + /* Load Message Payload and Activate Tx Message Buffer. */ + for (cnt = 0; cnt < payload_dword; cnt++) + { + mbAddr[offset + 2 + cnt] = txFrame->dataWord[cnt]; + } + mbAddr[offset] = cs_temp; + +#if ((defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) || \ + (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5829) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5829)) + mbAddr[availoffset] = CAN_CS_CODE(kFLEXCAN_TxMbInactive); + mbAddr[availoffset] = CAN_CS_CODE(kFLEXCAN_TxMbInactive); #endif return kStatus_Success; @@ -1262,6 +1595,21 @@ status_t FLEXCAN_WriteFDTxMb(CAN_Type *base, uint8_t mbIdx, const flexcan_fd_fra } #endif +/*! + * brief Reads a FlexCAN Message from Receive Message Buffer. + * + * This function reads a CAN message from a specified Receive Message Buffer. + * The function fills a receive CAN message frame structure with + * just received data and activates the Message Buffer again. + * The function returns immediately. + * + * param base FlexCAN peripheral base address. + * param mbIdx The FlexCAN Message Buffer index. + * param rxFrame Pointer to CAN message frame structure for reception. + * retval kStatus_Success - Rx Message Buffer is full and has been read successfully. + * retval kStatus_FLEXCAN_RxOverflow - Rx Message Buffer is already overflowed and has been read successfully. + * retval kStatus_Fail - Rx Message Buffer is empty. + */ status_t FLEXCAN_ReadRxMb(CAN_Type *base, uint8_t mbIdx, flexcan_frame_t *rxFrame) { /* Assertion. */ @@ -1292,6 +1640,9 @@ status_t FLEXCAN_ReadRxMb(CAN_Type *base, uint8_t mbIdx, flexcan_frame_t *rxFram /* Get the message length. */ rxFrame->length = (cs_temp & CAN_CS_DLC_MASK) >> CAN_CS_DLC_SHIFT; + /* Get the time stamp. */ + rxFrame->timestamp = (cs_temp & CAN_CS_TIME_STAMP_MASK) >> CAN_CS_TIME_STAMP_SHIFT; + /* Store Message Payload. */ rxFrame->dataWord0 = base->MB[mbIdx].WORD0; rxFrame->dataWord1 = base->MB[mbIdx].WORD1; @@ -1318,6 +1669,21 @@ status_t FLEXCAN_ReadRxMb(CAN_Type *base, uint8_t mbIdx, flexcan_frame_t *rxFram } #if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) +/*! + * brief Reads a FlexCAN FD Message from Receive Message Buffer. + * + * This function reads a CAN FD message from a specified Receive Message Buffer. + * The function fills a receive CAN FD message frame structure with + * just received data and activates the Message Buffer again. + * The function returns immediately. + * + * param base FlexCAN peripheral base address. + * param mbIdx The FlexCAN FD Message Buffer index. + * param rxFrame Pointer to CAN FD message frame structure for reception. + * retval kStatus_Success - Rx Message Buffer is full and has been read successfully. + * retval kStatus_FLEXCAN_RxOverflow - Rx Message Buffer is already overflowed and has been read successfully. + * retval kStatus_Fail - Rx Message Buffer is empty. + */ status_t FLEXCAN_ReadFDRxMb(CAN_Type *base, uint8_t mbIdx, flexcan_fd_frame_t *rxFrame) { /* Assertion. */ @@ -1331,30 +1697,14 @@ status_t FLEXCAN_ReadFDRxMb(CAN_Type *base, uint8_t mbIdx, flexcan_fd_frame_t *r uint32_t can_id = 0; uint32_t dataSize; dataSize = (base->FDCTRL & CAN_FDCTRL_MBDSR0_MASK) >> CAN_FDCTRL_MBDSR0_SHIFT; - cs_temp = base->MB[mbIdx].CS; + uint8_t payload_dword = 1; + volatile uint32_t *mbAddr = &(base->MB[0].CS); + uint32_t offset = FLEXCAN_GetFDMailboxOffset(base, mbIdx); /* Read CS field of Rx Message Buffer to lock Message Buffer. */ - switch (dataSize) - { - case kFLEXCAN_8BperMB: - cs_temp = base->MB_8B[mbIdx].CS; - can_id = base->MB_8B[mbIdx].ID; - break; - case kFLEXCAN_16BperMB: - cs_temp = base->MB_16B[mbIdx].CS; - can_id = base->MB_16B[mbIdx].ID; - break; - case kFLEXCAN_32BperMB: - cs_temp = base->MB_32B[mbIdx].CS; - can_id = base->MB_32B[mbIdx].ID; - break; - case kFLEXCAN_64BperMB: - cs_temp = base->MB_64B[mbIdx].CS; - can_id = base->MB_64B[mbIdx].ID; - break; - default: - break; - } + cs_temp = mbAddr[offset]; + can_id = mbAddr[offset + 1]; + /* Get Rx Message Buffer Code field. */ rx_code = (cs_temp & CAN_CS_CODE_MASK) >> CAN_CS_CODE_SHIFT; @@ -1373,35 +1723,20 @@ status_t FLEXCAN_ReadFDRxMb(CAN_Type *base, uint8_t mbIdx, flexcan_fd_frame_t *r /* Get the message length. */ rxFrame->length = (cs_temp & CAN_CS_DLC_MASK) >> CAN_CS_DLC_SHIFT; - /* Store Message Payload. */ - switch (dataSize) + /* Get the time stamp. */ + rxFrame->timestamp = (cs_temp & CAN_CS_TIME_STAMP_MASK) >> CAN_CS_TIME_STAMP_SHIFT; + + /* Calculate the DWORD number, dataSize 0/1/2/3 corresponds to 8/16/32/64 + Bytes payload. */ + for (cnt = 0; cnt < dataSize + 1; cnt++) { - case kFLEXCAN_8BperMB: - for (cnt = 0; cnt < 2; cnt++) - { - rxFrame->dataWord[cnt] = base->MB_8B[mbIdx].WORD[cnt]; - } - break; - case kFLEXCAN_16BperMB: - for (cnt = 0; cnt < 4; cnt++) - { - rxFrame->dataWord[cnt] = base->MB_16B[mbIdx].WORD[cnt]; - } - break; - case kFLEXCAN_32BperMB: - for (cnt = 0; cnt < 8; cnt++) - { - rxFrame->dataWord[cnt] = base->MB_32B[mbIdx].WORD[cnt]; - } - break; - case kFLEXCAN_64BperMB: - for (cnt = 0; cnt < 16; cnt++) - { - rxFrame->dataWord[cnt] = base->MB_64B[mbIdx].WORD[cnt]; - } - break; - default: - break; + payload_dword *= 2; + } + + /* Store Message Payload. */ + for (cnt = 0; cnt < payload_dword; cnt++) + { + rxFrame->dataWord[cnt] = mbAddr[offset + 2 + cnt]; } /* Read free-running timer to unlock Rx Message Buffer. */ @@ -1426,6 +1761,16 @@ status_t FLEXCAN_ReadFDRxMb(CAN_Type *base, uint8_t mbIdx, flexcan_fd_frame_t *r } #endif +/*! + * brief Reads a FlexCAN Message from Rx FIFO. + * + * This function reads a CAN message from the FlexCAN build-in Rx FIFO. + * + * param base FlexCAN peripheral base address. + * param rxFrame Pointer to CAN message frame structure for reception. + * retval kStatus_Success - Read Message from Rx FIFO successfully. + * retval kStatus_Fail - Rx FIFO is not enabled. + */ status_t FLEXCAN_ReadRxFifo(CAN_Type *base, flexcan_frame_t *rxFrame) { /* Assertion. */ @@ -1470,12 +1815,23 @@ status_t FLEXCAN_ReadRxFifo(CAN_Type *base, flexcan_frame_t *rxFrame) } } +/*! + * brief Performs a polling send transaction on the CAN bus. + * + * Note that a transfer handle does not need to be created before calling this API. + * + * param base FlexCAN peripheral base pointer. + * param mbIdx The FlexCAN Message Buffer index. + * param txFrame Pointer to CAN message frame to be sent. + * retval kStatus_Success - Write Tx Message Buffer Successfully. + * retval kStatus_Fail - Tx Message Buffer is currently in use. + */ status_t FLEXCAN_TransferSendBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_frame_t *txFrame) { /* Write Tx Message Buffer to initiate a data sending. */ if (kStatus_Success == FLEXCAN_WriteTxMb(base, mbIdx, txFrame)) { - /* Wait until CAN Message send out. */ +/* Wait until CAN Message send out. */ #if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) while (!FLEXCAN_GetMbStatusFlags(base, (uint64_t)1 << mbIdx)) #else @@ -1484,7 +1840,7 @@ status_t FLEXCAN_TransferSendBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_fra { } - /* Clean Tx Message Buffer Flag. */ +/* Clean Tx Message Buffer Flag. */ #if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) FLEXCAN_ClearMbStatusFlags(base, (uint64_t)1 << mbIdx); #else @@ -1499,9 +1855,21 @@ status_t FLEXCAN_TransferSendBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_fra } } +/*! + * brief Performs a polling receive transaction on the CAN bus. + * + * Note that a transfer handle does not need to be created before calling this API. + * + * param base FlexCAN peripheral base pointer. + * param mbIdx The FlexCAN Message Buffer index. + * param rxFrame Pointer to CAN message frame structure for reception. + * retval kStatus_Success - Rx Message Buffer is full and has been read successfully. + * retval kStatus_FLEXCAN_RxOverflow - Rx Message Buffer is already overflowed and has been read successfully. + * retval kStatus_Fail - Rx Message Buffer is empty. + */ status_t FLEXCAN_TransferReceiveBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_frame_t *rxFrame) { - /* Wait until Rx Message Buffer non-empty. */ +/* Wait until Rx Message Buffer non-empty. */ #if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) while (!FLEXCAN_GetMbStatusFlags(base, (uint64_t)1 << mbIdx)) #else @@ -1510,7 +1878,7 @@ status_t FLEXCAN_TransferReceiveBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_ { } - /* Clean Rx Message Buffer Flag. */ +/* Clean Rx Message Buffer Flag. */ #if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) FLEXCAN_ClearMbStatusFlags(base, (uint64_t)1 << mbIdx); #else @@ -1522,12 +1890,23 @@ status_t FLEXCAN_TransferReceiveBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_ } #if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) +/*! + * brief Performs a polling send transaction on the CAN bus. + * + * Note that a transfer handle does not need to be created before calling this API. + * + * param base FlexCAN peripheral base pointer. + * param mbIdx The FlexCAN FD Message Buffer index. + * param txFrame Pointer to CAN FD message frame to be sent. + * retval kStatus_Success - Write Tx Message Buffer Successfully. + * retval kStatus_Fail - Tx Message Buffer is currently in use. + */ status_t FLEXCAN_TransferFDSendBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_fd_frame_t *txFrame) { /* Write Tx Message Buffer to initiate a data sending. */ if (kStatus_Success == FLEXCAN_WriteFDTxMb(base, mbIdx, txFrame)) { - /* Wait until CAN Message send out. */ +/* Wait until CAN Message send out. */ #if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) while (!FLEXCAN_GetMbStatusFlags(base, (uint64_t)1 << mbIdx)) #else @@ -1536,7 +1915,7 @@ status_t FLEXCAN_TransferFDSendBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_f { } - /* Clean Tx Message Buffer Flag. */ +/* Clean Tx Message Buffer Flag. */ #if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) FLEXCAN_ClearMbStatusFlags(base, (uint64_t)1 << mbIdx); #else @@ -1551,9 +1930,21 @@ status_t FLEXCAN_TransferFDSendBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_f } } +/*! + * brief Performs a polling receive transaction on the CAN bus. + * + * Note that a transfer handle does not need to be created before calling this API. + * + * param base FlexCAN peripheral base pointer. + * param mbIdx The FlexCAN FD Message Buffer index. + * param rxFrame Pointer to CAN FD message frame structure for reception. + * retval kStatus_Success - Rx Message Buffer is full and has been read successfully. + * retval kStatus_FLEXCAN_RxOverflow - Rx Message Buffer is already overflowed and has been read successfully. + * retval kStatus_Fail - Rx Message Buffer is empty. + */ status_t FLEXCAN_TransferFDReceiveBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_fd_frame_t *rxFrame) { - /* Wait until Rx Message Buffer non-empty. */ +/* Wait until Rx Message Buffer non-empty. */ #if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) while (!FLEXCAN_GetMbStatusFlags(base, (uint64_t)1 << mbIdx)) #else @@ -1562,7 +1953,7 @@ status_t FLEXCAN_TransferFDReceiveBlocking(CAN_Type *base, uint8_t mbIdx, flexca { } - /* Clean Rx Message Buffer Flag. */ +/* Clean Rx Message Buffer Flag. */ #if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) FLEXCAN_ClearMbStatusFlags(base, (uint64_t)1 << mbIdx); #else @@ -1574,6 +1965,16 @@ status_t FLEXCAN_TransferFDReceiveBlocking(CAN_Type *base, uint8_t mbIdx, flexca } #endif +/*! + * brief Performs a polling receive transaction from Rx FIFO on the CAN bus. + * + * Note that a transfer handle does not need to be created before calling this API. + * + * param base FlexCAN peripheral base pointer. + * param rxFrame Pointer to CAN message frame structure for reception. + * retval kStatus_Success - Read Message from Rx FIFO successfully. + * retval kStatus_Fail - Rx FIFO is not enabled. + */ status_t FLEXCAN_TransferReceiveFifoBlocking(CAN_Type *base, flexcan_frame_t *rxFrame) { status_t rxFifoStatus; @@ -1592,6 +1993,18 @@ status_t FLEXCAN_TransferReceiveFifoBlocking(CAN_Type *base, flexcan_frame_t *rx return rxFifoStatus; } +/*! + * brief Initializes the FlexCAN handle. + * + * This function initializes the FlexCAN handle, which can be used for other FlexCAN + * transactional APIs. Usually, for a specified FlexCAN instance, + * call this API once to get the initialized handle. + * + * param base FlexCAN peripheral base address. + * param handle FlexCAN handle pointer. + * param callback The callback function. + * param userData The parameter of the callback function. + */ void FLEXCAN_TransferCreateHandle(CAN_Type *base, flexcan_handle_t *handle, flexcan_transfer_callback_t callback, @@ -1642,6 +2055,19 @@ void FLEXCAN_TransferCreateHandle(CAN_Type *base, EnableIRQ((IRQn_Type)(s_flexcanMbIRQ[instance])); } +/*! + * brief Sends a message using IRQ. + * + * This function sends a message using IRQ. This is a non-blocking function, which returns + * right away. When messages have been sent out, the send callback function is called. + * + * param base FlexCAN peripheral base address. + * param handle FlexCAN handle pointer. + * param xfer FlexCAN Message Buffer transfer structure. See the #flexcan_mb_transfer_t. + * retval kStatus_Success Start Tx Message Buffer sending process successfully. + * retval kStatus_Fail Write Tx Message Buffer failed. + * retval kStatus_FLEXCAN_TxBusy Tx Message Buffer is in use. + */ status_t FLEXCAN_TransferSendNonBlocking(CAN_Type *base, flexcan_handle_t *handle, flexcan_mb_transfer_t *xfer) { /* Assertion. */ @@ -1668,7 +2094,7 @@ status_t FLEXCAN_TransferSendNonBlocking(CAN_Type *base, flexcan_handle_t *handl if (kStatus_Success == FLEXCAN_WriteTxMb(base, xfer->mbIdx, xfer->frame)) { - /* Enable Message Buffer Interrupt. */ +/* Enable Message Buffer Interrupt. */ #if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) FLEXCAN_EnableMbInterrupts(base, (uint64_t)1 << xfer->mbIdx); #else @@ -1689,6 +2115,18 @@ status_t FLEXCAN_TransferSendNonBlocking(CAN_Type *base, flexcan_handle_t *handl } } +/*! + * brief Receives a message using IRQ. + * + * This function receives a message using IRQ. This is non-blocking function, which returns + * right away. When the message has been received, the receive callback function is called. + * + * param base FlexCAN peripheral base address. + * param handle FlexCAN handle pointer. + * param xfer FlexCAN Message Buffer transfer structure. See the #flexcan_mb_transfer_t. + * retval kStatus_Success - Start Rx Message Buffer receiving process successfully. + * retval kStatus_FLEXCAN_RxBusy - Rx Message Buffer is in use. + */ status_t FLEXCAN_TransferReceiveNonBlocking(CAN_Type *base, flexcan_handle_t *handle, flexcan_mb_transfer_t *xfer) { /* Assertion. */ @@ -1705,7 +2143,7 @@ status_t FLEXCAN_TransferReceiveNonBlocking(CAN_Type *base, flexcan_handle_t *ha /* Register Message Buffer. */ handle->mbFrameBuf[xfer->mbIdx] = xfer->frame; - /* Enable Message Buffer Interrupt. */ +/* Enable Message Buffer Interrupt. */ #if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) FLEXCAN_EnableMbInterrupts(base, (uint64_t)1 << xfer->mbIdx); #else @@ -1721,6 +2159,19 @@ status_t FLEXCAN_TransferReceiveNonBlocking(CAN_Type *base, flexcan_handle_t *ha } #if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) +/*! + * brief Sends a message using IRQ. + * + * This function sends a message using IRQ. This is a non-blocking function, which returns + * right away. When messages have been sent out, the send callback function is called. + * + * param base FlexCAN peripheral base address. + * param handle FlexCAN handle pointer. + * param xfer FlexCAN FD Message Buffer transfer structure. See the #flexcan_mb_transfer_t. + * retval kStatus_Success Start Tx Message Buffer sending process successfully. + * retval kStatus_Fail Write Tx Message Buffer failed. + * retval kStatus_FLEXCAN_TxBusy Tx Message Buffer is in use. + */ status_t FLEXCAN_TransferFDSendNonBlocking(CAN_Type *base, flexcan_handle_t *handle, flexcan_mb_transfer_t *xfer) { /* Assertion. */ @@ -1747,7 +2198,7 @@ status_t FLEXCAN_TransferFDSendNonBlocking(CAN_Type *base, flexcan_handle_t *han if (kStatus_Success == FLEXCAN_WriteFDTxMb(base, xfer->mbIdx, xfer->framefd)) { - /* Enable Message Buffer Interrupt. */ +/* Enable Message Buffer Interrupt. */ #if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) FLEXCAN_EnableMbInterrupts(base, (uint64_t)1 << xfer->mbIdx); #else @@ -1768,6 +2219,18 @@ status_t FLEXCAN_TransferFDSendNonBlocking(CAN_Type *base, flexcan_handle_t *han } } +/*! + * brief Receives a message using IRQ. + * + * This function receives a message using IRQ. This is non-blocking function, which returns + * right away. When the message has been received, the receive callback function is called. + * + * param base FlexCAN peripheral base address. + * param handle FlexCAN handle pointer. + * param xfer FlexCAN FD Message Buffer transfer structure. See the #flexcan_mb_transfer_t. + * retval kStatus_Success - Start Rx Message Buffer receiving process successfully. + * retval kStatus_FLEXCAN_RxBusy - Rx Message Buffer is in use. + */ status_t FLEXCAN_TransferFDReceiveNonBlocking(CAN_Type *base, flexcan_handle_t *handle, flexcan_mb_transfer_t *xfer) { /* Assertion. */ @@ -1784,7 +2247,7 @@ status_t FLEXCAN_TransferFDReceiveNonBlocking(CAN_Type *base, flexcan_handle_t * /* Register Message Buffer. */ handle->mbFDFrameBuf[xfer->mbIdx] = xfer->framefd; - /* Enable Message Buffer Interrupt. */ +/* Enable Message Buffer Interrupt. */ #if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) FLEXCAN_EnableMbInterrupts(base, (uint64_t)1 << xfer->mbIdx); #else @@ -1800,6 +2263,18 @@ status_t FLEXCAN_TransferFDReceiveNonBlocking(CAN_Type *base, flexcan_handle_t * } #endif +/*! + * brief Receives a message from Rx FIFO using IRQ. + * + * This function receives a message using IRQ. This is a non-blocking function, which returns + * right away. When all messages have been received, the receive callback function is called. + * + * param base FlexCAN peripheral base address. + * param handle FlexCAN handle pointer. + * param xfer FlexCAN Rx FIFO transfer structure. See the ref flexcan_fifo_transfer_t. + * retval kStatus_Success - Start Rx FIFO receiving process successfully. + * retval kStatus_FLEXCAN_RxFifoBusy - Rx FIFO is currently in use. + */ status_t FLEXCAN_TransferReceiveFifoNonBlocking(CAN_Type *base, flexcan_handle_t *handle, flexcan_fifo_transfer_t *xfer) { /* Assertion. */ @@ -1826,6 +2301,15 @@ status_t FLEXCAN_TransferReceiveFifoNonBlocking(CAN_Type *base, flexcan_handle_t } } +/*! + * brief Aborts the interrupt driven message send process. + * + * This function aborts the interrupt driven message send process. + * + * param base FlexCAN peripheral base address. + * param handle FlexCAN handle pointer. + * param mbIdx The FlexCAN Message Buffer index. + */ void FLEXCAN_TransferAbortSend(CAN_Type *base, flexcan_handle_t *handle, uint8_t mbIdx) { /* Assertion. */ @@ -1833,7 +2317,7 @@ void FLEXCAN_TransferAbortSend(CAN_Type *base, flexcan_handle_t *handle, uint8_t assert(mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK)); assert(!FLEXCAN_IsMbOccupied(base, mbIdx)); - /* Disable Message Buffer Interrupt. */ +/* Disable Message Buffer Interrupt. */ #if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) FLEXCAN_DisableMbInterrupts(base, (uint64_t)1 << mbIdx); #else @@ -1850,6 +2334,15 @@ void FLEXCAN_TransferAbortSend(CAN_Type *base, flexcan_handle_t *handle, uint8_t } #if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) +/*! + * brief Aborts the interrupt driven message send process. + * + * This function aborts the interrupt driven message send process. + * + * param base FlexCAN peripheral base address. + * param handle FlexCAN handle pointer. + * param mbIdx The FlexCAN FD Message Buffer index. + */ void FLEXCAN_TransferFDAbortSend(CAN_Type *base, flexcan_handle_t *handle, uint8_t mbIdx) { /* Assertion. */ @@ -1857,7 +2350,7 @@ void FLEXCAN_TransferFDAbortSend(CAN_Type *base, flexcan_handle_t *handle, uint8 assert(mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK)); assert(!FLEXCAN_IsMbOccupied(base, mbIdx)); - /* Disable Message Buffer Interrupt. */ +/* Disable Message Buffer Interrupt. */ #if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) FLEXCAN_DisableMbInterrupts(base, (uint64_t)1 << mbIdx); #else @@ -1880,7 +2373,7 @@ void FLEXCAN_TransferFDAbortReceive(CAN_Type *base, flexcan_handle_t *handle, ui assert(mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK)); assert(!FLEXCAN_IsMbOccupied(base, mbIdx)); - /* Disable Message Buffer Interrupt. */ +/* Disable Message Buffer Interrupt. */ #if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) FLEXCAN_DisableMbInterrupts(base, (uint64_t)1 << mbIdx); #else @@ -1893,6 +2386,15 @@ void FLEXCAN_TransferFDAbortReceive(CAN_Type *base, flexcan_handle_t *handle, ui } #endif +/*! + * brief Aborts the interrupt driven message receive process. + * + * This function aborts the interrupt driven message receive process. + * + * param base FlexCAN peripheral base address. + * param handle FlexCAN handle pointer. + * param mbIdx The FlexCAN Message Buffer index. + */ void FLEXCAN_TransferAbortReceive(CAN_Type *base, flexcan_handle_t *handle, uint8_t mbIdx) { /* Assertion. */ @@ -1900,7 +2402,7 @@ void FLEXCAN_TransferAbortReceive(CAN_Type *base, flexcan_handle_t *handle, uint assert(mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK)); assert(!FLEXCAN_IsMbOccupied(base, mbIdx)); - /* Disable Message Buffer Interrupt. */ +/* Disable Message Buffer Interrupt. */ #if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) FLEXCAN_DisableMbInterrupts(base, (uint64_t)1 << mbIdx); #else @@ -1912,6 +2414,14 @@ void FLEXCAN_TransferAbortReceive(CAN_Type *base, flexcan_handle_t *handle, uint handle->mbState[mbIdx] = kFLEXCAN_StateIdle; } +/*! + * brief Aborts the interrupt driven message receive from Rx FIFO process. + * + * This function aborts the interrupt driven message receive from Rx FIFO process. + * + * param base FlexCAN peripheral base address. + * param handle FlexCAN handle pointer. + */ void FLEXCAN_TransferAbortReceiveFifo(CAN_Type *base, flexcan_handle_t *handle) { /* Assertion. */ @@ -1931,6 +2441,14 @@ void FLEXCAN_TransferAbortReceiveFifo(CAN_Type *base, flexcan_handle_t *handle) handle->rxFifoState = kFLEXCAN_StateIdle; } +/*! + * brief FlexCAN IRQ handle function. + * + * This function handles the FlexCAN Error, the Message Buffer, and the Rx FIFO IRQ request. + * + * param base FlexCAN peripheral base address. + * param handle FlexCAN handle pointer. + */ void FLEXCAN_TransferHandleIRQ(CAN_Type *base, flexcan_handle_t *handle) { /* Assertion. */ @@ -1945,14 +2463,19 @@ void FLEXCAN_TransferHandleIRQ(CAN_Type *base, flexcan_handle_t *handle) do { /* Solve FlexCAN Error and Status Interrupt. */ - if (result & (kFLEXCAN_TxWarningIntFlag | kFLEXCAN_RxWarningIntFlag | kFLEXCAN_BusOffIntFlag | - kFLEXCAN_ErrorIntFlag | kFLEXCAN_WakeUpIntFlag)) + if (result & + (kFLEXCAN_TxWarningIntFlag | kFLEXCAN_RxWarningIntFlag | kFLEXCAN_BusOffIntFlag | kFLEXCAN_ErrorIntFlag)) { status = kStatus_FLEXCAN_ErrorStatus; /* Clear FlexCAN Error and Status Interrupt. */ FLEXCAN_ClearStatusFlags(base, kFLEXCAN_TxWarningIntFlag | kFLEXCAN_RxWarningIntFlag | - kFLEXCAN_BusOffIntFlag | kFLEXCAN_ErrorIntFlag | kFLEXCAN_WakeUpIntFlag); + kFLEXCAN_BusOffIntFlag | kFLEXCAN_ErrorIntFlag); + } + else if (result & kFLEXCAN_WakeUpIntFlag) + { + status = kStatus_FLEXCAN_WakeUp; + FLEXCAN_ClearStatusFlags(base, kFLEXCAN_WakeUpIntFlag); } /* Solve FlexCAN Rx FIFO & Message Buffer Interrupt. */ else @@ -1960,7 +2483,7 @@ void FLEXCAN_TransferHandleIRQ(CAN_Type *base, flexcan_handle_t *handle) /* For this implementation, we solve the Message with lowest MB index first. */ for (result = 0; result < FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(base); result++) { - /* Get the lowest unhandled Message Buffer */ +/* Get the lowest unhandled Message Buffer */ #if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) if ((FLEXCAN_GetMbStatusFlags(base, (uint64_t)1 << result)) && (FLEXCAN_IsMbIntEnabled(base, result))) #else @@ -2012,7 +2535,14 @@ void FLEXCAN_TransferHandleIRQ(CAN_Type *base, flexcan_handle_t *handle) /* Solve Rx Data Frame. */ case kFLEXCAN_StateRxData: #if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) - status = FLEXCAN_ReadFDRxMb(base, result, handle->mbFDFrameBuf[result]); + if (base->MCR & CAN_MCR_FDEN_MASK) + { + status = FLEXCAN_ReadFDRxMb(base, result, handle->mbFDFrameBuf[result]); + } + else + { + status = FLEXCAN_ReadRxMb(base, result, handle->mbFrameBuf[result]); + } #else status = FLEXCAN_ReadRxMb(base, result, handle->mbFrameBuf[result]); #endif @@ -2021,7 +2551,14 @@ void FLEXCAN_TransferHandleIRQ(CAN_Type *base, flexcan_handle_t *handle) status = kStatus_FLEXCAN_RxIdle; } #if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) - FLEXCAN_TransferFDAbortReceive(base, handle, result); + if (base->MCR & CAN_MCR_FDEN_MASK) + { + FLEXCAN_TransferFDAbortReceive(base, handle, result); + } + else + { + FLEXCAN_TransferAbortReceive(base, handle, result); + } #else FLEXCAN_TransferAbortReceive(base, handle, result); #endif @@ -2041,7 +2578,14 @@ void FLEXCAN_TransferHandleIRQ(CAN_Type *base, flexcan_handle_t *handle) case kFLEXCAN_StateTxData: status = kStatus_FLEXCAN_TxIdle; #if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) - FLEXCAN_TransferFDAbortSend(base, handle, result); + if (base->MCR & CAN_MCR_FDEN_MASK) + { + FLEXCAN_TransferFDAbortSend(base, handle, result); + } + else + { + FLEXCAN_TransferAbortSend(base, handle, result); + } #else FLEXCAN_TransferAbortSend(base, handle, result); #endif @@ -2051,6 +2595,18 @@ void FLEXCAN_TransferHandleIRQ(CAN_Type *base, flexcan_handle_t *handle) case kFLEXCAN_StateTxRemote: handle->mbState[result] = kFLEXCAN_StateRxRemote; status = kStatus_FLEXCAN_TxSwitchToRx; +#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) + if (base->MCR & CAN_MCR_FDEN_MASK) + { + FLEXCAN_TransferFDAbortReceive(base, handle, result); + } + else + { + FLEXCAN_TransferAbortReceive(base, handle, result); + } +#else + FLEXCAN_TransferAbortReceive(base, handle, result); +#endif break; default: @@ -2059,7 +2615,7 @@ void FLEXCAN_TransferHandleIRQ(CAN_Type *base, flexcan_handle_t *handle) } } - /* Clear resolved Message Buffer IRQ. */ +/* Clear resolved Message Buffer IRQ. */ #if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) FLEXCAN_ClearMbStatusFlags(base, (uint64_t)1 << result); #else @@ -2096,8 +2652,8 @@ void CAN0_DriverIRQHandler(void) assert(s_flexcanHandle[0]); s_flexcanIsr(CAN0, s_flexcanHandle[0]); - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ #if defined __CORTEX_M && (__CORTEX_M == 4U) __DSB(); #endif @@ -2110,8 +2666,8 @@ void CAN1_DriverIRQHandler(void) assert(s_flexcanHandle[1]); s_flexcanIsr(CAN1, s_flexcanHandle[1]); - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ #if defined __CORTEX_M && (__CORTEX_M == 4U) __DSB(); #endif @@ -2124,8 +2680,8 @@ void CAN2_DriverIRQHandler(void) assert(s_flexcanHandle[2]); s_flexcanIsr(CAN2, s_flexcanHandle[2]); - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ #if defined __CORTEX_M && (__CORTEX_M == 4U) __DSB(); #endif @@ -2138,8 +2694,8 @@ void CAN3_DriverIRQHandler(void) assert(s_flexcanHandle[3]); s_flexcanIsr(CAN3, s_flexcanHandle[3]); - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ #if defined __CORTEX_M && (__CORTEX_M == 4U) __DSB(); #endif @@ -2152,8 +2708,8 @@ void CAN4_DriverIRQHandler(void) assert(s_flexcanHandle[4]); s_flexcanIsr(CAN4, s_flexcanHandle[4]); - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ #if defined __CORTEX_M && (__CORTEX_M == 4U) __DSB(); #endif @@ -2166,8 +2722,8 @@ void DMA_FLEXCAN0_INT_DriverIRQHandler(void) assert(s_flexcanHandle[FLEXCAN_GetInstance(DMA__CAN0)]); s_flexcanIsr(DMA__CAN0, s_flexcanHandle[FLEXCAN_GetInstance(DMA__CAN0)]); - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ #if defined __CORTEX_M && (__CORTEX_M == 4U) __DSB(); #endif @@ -2180,8 +2736,8 @@ void DMA_FLEXCAN1_INT_DriverIRQHandler(void) assert(s_flexcanHandle[FLEXCAN_GetInstance(DMA__CAN1)]); s_flexcanIsr(DMA__CAN1, s_flexcanHandle[FLEXCAN_GetInstance(DMA__CAN1)]); - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ #if defined __CORTEX_M && (__CORTEX_M == 4U) __DSB(); #endif @@ -2194,8 +2750,50 @@ void DMA_FLEXCAN2_INT_DriverIRQHandler(void) assert(s_flexcanHandle[FLEXCAN_GetInstance(DMA__CAN2)]); s_flexcanIsr(DMA__CAN2, s_flexcanHandle[FLEXCAN_GetInstance(DMA__CAN2)]); - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif + +#if defined(ADMA__CAN0) +void ADMA_FLEXCAN0_INT_DriverIRQHandler(void) +{ + assert(s_flexcanHandle[FLEXCAN_GetInstance(ADMA__CAN0)]); + + s_flexcanIsr(ADMA__CAN0, s_flexcanHandle[FLEXCAN_GetInstance(ADMA__CAN0)]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif + +#if defined(ADMA__CAN1) +void ADMA_FLEXCAN1_INT_DriverIRQHandler(void) +{ + assert(s_flexcanHandle[FLEXCAN_GetInstance(ADMA__CAN1)]); + + s_flexcanIsr(ADMA__CAN1, s_flexcanHandle[FLEXCAN_GetInstance(ADMA__CAN1)]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif + +#if defined(ADMA__CAN2) +void ADMA_FLEXCAN2_INT_DriverIRQHandler(void) +{ + assert(s_flexcanHandle[FLEXCAN_GetInstance(ADMA__CAN2)]); + + s_flexcanIsr(ADMA__CAN2, s_flexcanHandle[FLEXCAN_GetInstance(ADMA__CAN2)]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ #if defined __CORTEX_M && (__CORTEX_M == 4U) __DSB(); #endif diff --git a/ext/hal/nxp/mcux/drivers/kinetis/fsl_flexcan.h b/ext/hal/nxp/mcux/drivers/kinetis/fsl_flexcan.h index 3ae7598f00f..6b2d820113a 100644 --- a/ext/hal/nxp/mcux/drivers/kinetis/fsl_flexcan.h +++ b/ext/hal/nxp/mcux/drivers/kinetis/fsl_flexcan.h @@ -1,31 +1,9 @@ /* * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP + * Copyright 2016-2018 NXP + * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * SPDX-License-Identifier: BSD-3-Clause */ #ifndef _FSL_FLEXCAN_H_ #define _FSL_FLEXCAN_H_ @@ -43,10 +21,15 @@ /*! @name Driver version */ /*@{*/ -/*! @brief FlexCAN driver version 2.2.0. */ -#define FLEXCAN_DRIVER_VERSION (MAKE_VERSION(2, 2, 0)) +/*! @brief FlexCAN driver version 2.3.0. */ +#define FSL_FLEXCAN_DRIVER_VERSION (MAKE_VERSION(2, 3, 2)) /*@}*/ +#ifndef FLEXCAN_WAIT_TIMEOUT +/* Define to 1000 means keep waiting 1000 times until the flag is assert/deassert. */ +#define FLEXCAN_WAIT_TIMEOUT (1000U) +#endif + /*! @brief FlexCAN Frame ID helper macro. */ #define FLEXCAN_ID_STD(id) \ (((uint32_t)(((uint32_t)(id)) << CAN_ID_STD_SHIFT)) & CAN_ID_STD_MASK) /*!< Standard Frame ID helper macro. */ @@ -68,24 +51,26 @@ (FLEXCAN_ID_STD(id) << 1)) /*!< Standard Rx FIFO Mask helper macro Type A helper macro. */ #define FLEXCAN_RX_FIFO_STD_MASK_TYPE_B_HIGH(id, rtr, ide) \ (((uint32_t)((uint32_t)(rtr) << 31) | (uint32_t)((uint32_t)(ide) << 30)) | \ - (((uint32_t)(id) & 0x7FF) << 19)) /*!< Standard Rx FIFO Mask helper macro Type B upper part helper macro. */ + (((uint32_t)(id)&0x7FF) << 19)) /*!< Standard Rx FIFO Mask helper macro Type B upper part helper macro. */ #define FLEXCAN_RX_FIFO_STD_MASK_TYPE_B_LOW(id, rtr, ide) \ (((uint32_t)((uint32_t)(rtr) << 15) | (uint32_t)((uint32_t)(ide) << 14)) | \ - (((uint32_t)(id) & 0x7FF) << 3)) /*!< Standard Rx FIFO Mask helper macro Type B lower part helper macro. */ + (((uint32_t)(id)&0x7FF) << 3)) /*!< Standard Rx FIFO Mask helper macro Type B lower part helper macro. */ #define FLEXCAN_RX_FIFO_STD_MASK_TYPE_C_HIGH(id) \ - (((uint32_t)(id) & 0x7F8) << 21) /*!< Standard Rx FIFO Mask helper macro Type C upper part helper macro. */ + (((uint32_t)(id)&0x7F8) << 21) /*!< Standard Rx FIFO Mask helper macro Type C upper part helper macro. */ #define FLEXCAN_RX_FIFO_STD_MASK_TYPE_C_MID_HIGH(id) \ - (((uint32_t)(id) & 0x7F8) << 13) /*!< Standard Rx FIFO Mask helper macro Type C mid-upper part helper macro. */ + (((uint32_t)(id)&0x7F8) << 13) /*!< Standard Rx FIFO Mask helper macro Type C mid-upper part helper macro. */ #define FLEXCAN_RX_FIFO_STD_MASK_TYPE_C_MID_LOW(id) \ - (((uint32_t)(id) & 0x7F8) << 5) /*!< Standard Rx FIFO Mask helper macro Type C mid-lower part helper macro. */ + (((uint32_t)(id)&0x7F8) << 5) /*!< Standard Rx FIFO Mask helper macro Type C mid-lower part helper macro. */ #define FLEXCAN_RX_FIFO_STD_MASK_TYPE_C_LOW(id) \ - (((uint32_t)(id) & 0x7F8) >> 3) /*!< Standard Rx FIFO Mask helper macro Type C lower part helper macro. */ + (((uint32_t)(id)&0x7F8) >> 3) /*!< Standard Rx FIFO Mask helper macro Type C lower part helper macro. */ #define FLEXCAN_RX_FIFO_EXT_MASK_TYPE_A(id, rtr, ide) \ (((uint32_t)((uint32_t)(rtr) << 31) | (uint32_t)((uint32_t)(ide) << 30)) | \ (FLEXCAN_ID_EXT(id) << 1)) /*!< Extend Rx FIFO Mask helper macro Type A helper macro. */ #define FLEXCAN_RX_FIFO_EXT_MASK_TYPE_B_HIGH(id, rtr, ide) \ - (((uint32_t)((uint32_t)(rtr) << 31) | (uint32_t)((uint32_t)(ide) << 30)) | \ - ((FLEXCAN_ID_EXT(id) & 0x1FFF8000) << 1)) /*!< Extend Rx FIFO Mask helper macro Type B upper part helper macro. */ + ( \ + ((uint32_t)((uint32_t)(rtr) << 31) | (uint32_t)((uint32_t)(ide) << 30)) | \ + ((FLEXCAN_ID_EXT(id) & 0x1FFF8000) \ + << 1)) /*!< Extend Rx FIFO Mask helper macro Type B upper part helper macro. */ #define FLEXCAN_RX_FIFO_EXT_MASK_TYPE_B_LOW(id, rtr, ide) \ (((uint32_t)((uint32_t)(rtr) << 15) | (uint32_t)((uint32_t)(ide) << 14)) | \ ((FLEXCAN_ID_EXT(id) & 0x1FFF8000) >> \ @@ -119,9 +104,9 @@ #define FLEXCAN_RX_FIFO_STD_FILTER_TYPE_C_MID_LOW(id) \ FLEXCAN_RX_FIFO_STD_MASK_TYPE_C_MID_LOW( \ id) /*!< Standard Rx FIFO Filter helper macro Type C mid-lower part helper macro. */ -#define FLEXCAN_RX_FIFO_STD_FILTER_TYPE_C_LOW(id) \ - FLEXCAN_RX_FIFO_STD_MASK_TYPE_C_LOW(id) /*!< Standard Rx FIFO Filter helper macro Type C lower part helper macro. \ - */ +#define FLEXCAN_RX_FIFO_STD_FILTER_TYPE_C_LOW(id) \ + FLEXCAN_RX_FIFO_STD_MASK_TYPE_C_LOW( \ + id) /*!< Standard Rx FIFO Filter helper macro Type C lower part helper macro. */ #define FLEXCAN_RX_FIFO_EXT_FILTER_TYPE_A(id, rtr, ide) \ FLEXCAN_RX_FIFO_EXT_MASK_TYPE_A(id, rtr, ide) /*!< Extend Rx FIFO Filter helper macro Type A helper macro. */ #define FLEXCAN_RX_FIFO_EXT_FILTER_TYPE_B_HIGH(id, rtr, ide) \ @@ -130,9 +115,9 @@ #define FLEXCAN_RX_FIFO_EXT_FILTER_TYPE_B_LOW(id, rtr, ide) \ FLEXCAN_RX_FIFO_EXT_MASK_TYPE_B_LOW( \ id, rtr, ide) /*!< Extend Rx FIFO Filter helper macro Type B lower part helper macro. */ -#define FLEXCAN_RX_FIFO_EXT_FILTER_TYPE_C_HIGH(id) \ - FLEXCAN_RX_FIFO_EXT_MASK_TYPE_C_HIGH(id) /*!< Extend Rx FIFO Filter helper macro Type C upper part helper macro. \ - */ +#define FLEXCAN_RX_FIFO_EXT_FILTER_TYPE_C_HIGH(id) \ + FLEXCAN_RX_FIFO_EXT_MASK_TYPE_C_HIGH( \ + id) /*!< Extend Rx FIFO Filter helper macro Type C upper part helper macro. */ #define FLEXCAN_RX_FIFO_EXT_FILTER_TYPE_C_MID_HIGH(id) \ FLEXCAN_RX_FIFO_EXT_MASK_TYPE_C_MID_HIGH( \ id) /*!< Extend Rx FIFO Filter helper macro Type C mid-upper part helper macro. */ @@ -157,7 +142,8 @@ enum _flexcan_status kStatus_FLEXCAN_RxFifoOverflow = MAKE_STATUS(kStatusGroup_FLEXCAN, 8), /*!< Rx Message FIFO is overflowed. */ kStatus_FLEXCAN_RxFifoWarning = MAKE_STATUS(kStatusGroup_FLEXCAN, 9), /*!< Rx Message FIFO is almost overflowed. */ kStatus_FLEXCAN_ErrorStatus = MAKE_STATUS(kStatusGroup_FLEXCAN, 10), /*!< FlexCAN Module Error and Status. */ - kStatus_FLEXCAN_UnHandled = MAKE_STATUS(kStatusGroup_FLEXCAN, 11), /*!< UnHadled Interrupt asserted. */ + kStatus_FLEXCAN_WakeUp = MAKE_STATUS(kStatusGroup_FLEXCAN, 11), /*!< FlexCAN is waken up from STOP mode. */ + kStatus_FLEXCAN_UnHandled = MAKE_STATUS(kStatusGroup_FLEXCAN, 12), /*!< UnHadled Interrupt asserted. */ }; /*! @brief FlexCAN frame format. */ @@ -174,14 +160,19 @@ typedef enum _flexcan_frame_type kFLEXCAN_FrameTypeRemote = 0x1U, /*!< Remote frame type attribute. */ } flexcan_frame_type_t; -#if (!defined(FSL_FEATURE_FLEXCAN_SUPPORT_ENGINE_CLK_SEL_REMOVE)) || !FSL_FEATURE_FLEXCAN_SUPPORT_ENGINE_CLK_SEL_REMOVE /*! @brief FlexCAN clock source. */ typedef enum _flexcan_clock_source { kFLEXCAN_ClkSrcOsc = 0x0U, /*!< FlexCAN Protocol Engine clock from Oscillator. */ kFLEXCAN_ClkSrcPeri = 0x1U, /*!< FlexCAN Protocol Engine clock from Peripheral Clock. */ } flexcan_clock_source_t; -#endif /* FSL_FEATURE_FLEXCAN_SUPPORT_ENGINE_CLK_SEL_REMOVE */ + +/*! @brief FlexCAN wake up source. */ +typedef enum _flexcan_wake_up_source +{ + kFLEXCAN_WakeupSrcUnfiltered = 0x0U, /*!< FlexCAN uses unfiltered Rx input to detect edge. */ + kFLEXCAN_WakeupSrcFiltered = 0x1U, /*!< FlexCAN uses filtered Rx input to detect edge. */ +} flexcan_wake_up_source_t; /*! @brief FlexCAN Rx Fifo Filter type. */ typedef enum _flexcan_rx_fifo_filter_type @@ -261,13 +252,13 @@ enum _flexcan_flags kFLEXCAN_BusOffIntFlag = CAN_ESR1_BOFFINT_MASK, /*!< Bus Off Interrupt Flag. */ kFLEXCAN_ErrorIntFlag = CAN_ESR1_ERRINT_MASK, /*!< Error Interrupt Flag. */ kFLEXCAN_WakeUpIntFlag = CAN_ESR1_WAKINT_MASK, /*!< Wake-Up Interrupt Flag. */ - kFLEXCAN_ErrorFlag = /*!< All FlexCAN Error Status. */ + kFLEXCAN_ErrorFlag = (int)( /*!< All FlexCAN Error Status. */ #if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) - CAN_ESR1_STFERR_FAST_MASK | CAN_ESR1_FRMERR_FAST_MASK | CAN_ESR1_CRCERR_FAST_MASK | CAN_ESR1_BIT0ERR_FAST_MASK | - CAN_ESR1_BIT1ERR_FAST_MASK | CAN_ESR1_ERROVR_MASK | + CAN_ESR1_STFERR_FAST_MASK | CAN_ESR1_FRMERR_FAST_MASK | CAN_ESR1_CRCERR_FAST_MASK | + CAN_ESR1_BIT0ERR_FAST_MASK | CAN_ESR1_BIT1ERR_FAST_MASK | CAN_ESR1_ERROVR_MASK | #endif - CAN_ESR1_BIT1ERR_MASK | CAN_ESR1_BIT0ERR_MASK | CAN_ESR1_ACKERR_MASK | CAN_ESR1_CRCERR_MASK | CAN_ESR1_FRMERR_MASK | - CAN_ESR1_STFERR_MASK, + CAN_ESR1_BIT1ERR_MASK | CAN_ESR1_BIT0ERR_MASK | CAN_ESR1_ACKERR_MASK | + CAN_ESR1_CRCERR_MASK | CAN_ESR1_FRMERR_MASK | CAN_ESR1_STFERR_MASK), }; /*! @@ -280,12 +271,12 @@ enum _flexcan_flags enum _flexcan_error_flags { #if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) - kFLEXCAN_FDStuffingError = CAN_ESR1_STFERR_FAST_MASK, /*!< Stuffing Error. */ - kFLEXCAN_FDFormError = CAN_ESR1_FRMERR_FAST_MASK, /*!< Form Error. */ - kFLEXCAN_FDCrcError = CAN_ESR1_CRCERR_FAST_MASK, /*!< Cyclic Redundancy Check Error. */ - kFLEXCAN_FDBit0Error = CAN_ESR1_BIT0ERR_FAST_MASK, /*!< Unable to send dominant bit. */ - kFLEXCAN_FDBit1Error = CAN_ESR1_BIT1ERR_FAST_MASK, /*!< Unable to send recessive bit. */ - kFLEXCAN_OverrunError = CAN_ESR1_ERROVR_MASK, /*!< Error Overrun Status. */ + kFLEXCAN_FDStuffingError = CAN_ESR1_STFERR_FAST_MASK, /*!< Stuffing Error. */ + kFLEXCAN_FDFormError = CAN_ESR1_FRMERR_FAST_MASK, /*!< Form Error. */ + kFLEXCAN_FDCrcError = CAN_ESR1_CRCERR_FAST_MASK, /*!< Cyclic Redundancy Check Error. */ + kFLEXCAN_FDBit0Error = CAN_ESR1_BIT0ERR_FAST_MASK, /*!< Unable to send dominant bit. */ + kFLEXCAN_FDBit1Error = (int)CAN_ESR1_BIT1ERR_FAST_MASK, /*!< Unable to send recessive bit. */ + kFLEXCAN_OverrunError = CAN_ESR1_ERROVR_MASK, /*!< Error Overrun Status. */ #endif kFLEXCAN_StuffingError = CAN_ESR1_STFERR_MASK, /*!< Stuffing Error. */ kFLEXCAN_FormError = CAN_ESR1_FRMERR_MASK, /*!< Form Error. */ @@ -363,11 +354,11 @@ typedef struct _flexcan_fd_frame uint32_t format : 1; /*!< CAN Frame Identifier(STD or EXT format). */ uint32_t srr : 1; /*!< Substitute Remote request. */ uint32_t : 1; - uint32_t code : 4; /*!< Message Buffer Code. */ + uint32_t code : 4; /*!< Message Buffer Code. */ uint32_t : 1; - uint32_t esi : 1; /*!< Error State Indicator. */ - uint32_t brs : 1; /*!< Bit Rate Switch. */ - uint32_t edl : 1; /*!< Extended Data Length. */ + uint32_t esi : 1; /*!< Error State Indicator. */ + uint32_t brs : 1; /*!< Bit Rate Switch. */ + uint32_t edl : 1; /*!< Extended Data Length. */ }; struct { @@ -380,6 +371,8 @@ typedef struct _flexcan_fd_frame { uint32_t dataWord[16]; /*!< CAN FD Frame payload, 16 double word maximum. */ }; + /* Note: the maximum databyte* below is actually 64, user can add them if needed, + or just use dataWord[*] instead. */ struct { uint8_t dataByte3; /*!< CAN Frame payload byte3. */ @@ -395,25 +388,6 @@ typedef struct _flexcan_fd_frame } flexcan_fd_frame_t; #endif -/*! @brief FlexCAN module configuration structure. */ -typedef struct _flexcan_config -{ - uint32_t baudRate; /*!< FlexCAN baud rate in bps. */ -#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) - uint32_t baudRateFD; /*!< FlexCAN FD baud rate in bps. */ -#endif -#if (!defined(FSL_FEATURE_FLEXCAN_SUPPORT_ENGINE_CLK_SEL_REMOVE)) || !FSL_FEATURE_FLEXCAN_SUPPORT_ENGINE_CLK_SEL_REMOVE - flexcan_clock_source_t clkSrc; /*!< Clock source for FlexCAN Protocol Engine. */ -#endif /* FSL_FEATURE_FLEXCAN_SUPPORT_ENGINE_CLK_SEL_REMOVE */ - uint8_t maxMbNum; /*!< The maximum number of Message Buffers used by user. */ - bool enableLoopBack; /*!< Enable or Disable Loop Back Self Test Mode. */ - bool enableSelfWakeup; /*!< Enable or Disable Self Wakeup Mode. */ - bool enableIndividMask; /*!< Enable or Disable Rx Individual Mask. */ -#if (defined(FSL_FEATURE_FLEXCAN_HAS_DOZE_MODE_SUPPORT) && FSL_FEATURE_FLEXCAN_HAS_DOZE_MODE_SUPPORT) - bool enableDoze; /*!< Enable or Disable Doze Mode. */ -#endif -} flexcan_config_t; - /*! @brief FlexCAN protocol timing characteristic configuration structure. */ typedef struct _flexcan_timing_config { @@ -422,8 +396,35 @@ typedef struct _flexcan_timing_config uint8_t phaseSeg1; /*!< Phase Segment 1. */ uint8_t phaseSeg2; /*!< Phase Segment 2. */ uint8_t propSeg; /*!< Propagation Segment. */ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) + uint16_t fpreDivider; /*!< Fast Clock Pre-scaler Division Factor. */ + uint8_t frJumpwidth; /*!< Fast Re-sync Jump Width. */ + uint8_t fphaseSeg1; /*!< Fast Phase Segment 1. */ + uint8_t fphaseSeg2; /*!< Fast Phase Segment 2. */ + uint8_t fpropSeg; /*!< Fast Propagation Segment. */ +#endif } flexcan_timing_config_t; +/*! @brief FlexCAN module configuration structure. */ +typedef struct _flexcan_config +{ + uint32_t baudRate; /*!< FlexCAN baud rate in bps. */ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) + uint32_t baudRateFD; /*!< FlexCAN FD baud rate in bps. */ +#endif + flexcan_clock_source_t clkSrc; /*!< Clock source for FlexCAN Protocol Engine. */ + flexcan_wake_up_source_t wakeupSrc; /*!< Wake up source selection. */ + uint8_t maxMbNum; /*!< The maximum number of Message Buffers used by user. */ + bool enableLoopBack; /*!< Enable or Disable Loop Back Self Test Mode. */ + bool enableTimerSync; /*!< Enable or Disable Timer Synchronization. */ + bool enableSelfWakeup; /*!< Enable or Disable Self Wakeup Mode. */ + bool enableIndividMask; /*!< Enable or Disable Rx Individual Mask. */ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_DOZE_MODE_SUPPORT) && FSL_FEATURE_FLEXCAN_HAS_DOZE_MODE_SUPPORT) + bool enableDoze; /*!< Enable or Disable Doze Mode. */ +#endif + flexcan_timing_config_t timingConfig; /* Protocol timing . */ +} flexcan_config_t; + /*! * @brief FlexCAN Receive Message Buffer configuration structure * @@ -510,6 +511,14 @@ extern "C" { * @{ */ +/*! + * @brief Get the FlexCAN instance from peripheral base address. + * + * @param base FlexCAN peripheral base address. + * @return FlexCAN instance. + */ +uint32_t FLEXCAN_GetInstance(CAN_Type *base); + /*! * @brief Initializes a FlexCAN instance. * @@ -525,6 +534,7 @@ extern "C" { * flexcanConfig.enableSelfWakeup = false; * flexcanConfig.enableIndividMask = false; * flexcanConfig.enableDoze = false; + * flexcanConfig.timingConfig = timingConfig; * FLEXCAN_Init(CAN0, &flexcanConfig, 8000000UL); * @endcode * @@ -534,6 +544,37 @@ extern "C" { */ void FLEXCAN_Init(CAN_Type *base, const flexcan_config_t *config, uint32_t sourceClock_Hz); +#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) +/*! + * @brief Initializes a FlexCAN instance. + * + * This function initializes the FlexCAN module with user-defined settings. + * This example shows how to set up the flexcan_config_t parameters and how + * to call the FLEXCAN_FDInit function by passing in these parameters. + * @code + * flexcan_config_t flexcanConfig; + * flexcanConfig.clkSrc = kFLEXCAN_ClkSrcOsc; + * flexcanConfig.baudRate = 1000000U; + * flexcanConfig.baudRateFD = 2000000U; + * flexcanConfig.maxMbNum = 16; + * flexcanConfig.enableLoopBack = false; + * flexcanConfig.enableSelfWakeup = false; + * flexcanConfig.enableIndividMask = false; + * flexcanConfig.enableDoze = false; + * flexcanConfig.timingConfig = timingConfig; + * FLEXCAN_FDInit(CAN0, &flexcanConfig, 8000000UL, kFLEXCAN_16BperMB, false); + * @endcode + * + * @param base FlexCAN peripheral base address. + * @param config Pointer to the user-defined configuration structure. + * @param sourceClock_Hz FlexCAN Protocol Engine clock source frequency in Hz. + * @param dataSize FlexCAN FD frame payload size. + * @param brs If bitrate switch is enabled in FD mode. + */ +void FLEXCAN_FDInit( + CAN_Type *base, const flexcan_config_t *config, uint32_t sourceClock_Hz, flexcan_mb_size_t dataSize, bool brs); +#endif + /*! * @brief De-initializes a FlexCAN instance. * @@ -549,31 +590,20 @@ void FLEXCAN_Deinit(CAN_Type *base); * * This function initializes the FlexCAN configuration structure to default values. The default * values are as follows. - * flexcanConfig->clkSrc = KFLEXCAN_ClkSrcOsc; + * flexcanConfig->clkSrc = kFLEXCAN_ClkSrcOsc; * flexcanConfig->baudRate = 1000000U; + * flexcanConfig->baudRateFD = 2000000U; * flexcanConfig->maxMbNum = 16; * flexcanConfig->enableLoopBack = false; * flexcanConfig->enableSelfWakeup = false; * flexcanConfig->enableIndividMask = false; * flexcanConfig->enableDoze = false; + * flexcanConfig.timingConfig = timingConfig; * * @param config Pointer to the FlexCAN configuration structure. */ void FLEXCAN_GetDefaultConfig(flexcan_config_t *config); -#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) -/*! - * @brief Sets the FlexCAN FD protocol characteristic. - * - * This function gives user settings to CAN FD characteristic. - * - * @param base FlexCAN peripheral base address. - * @param dataSize Quantity of data bytes allocated for the message payload. - * @param brs Enable/Disable the effect of bit rate switch during data phase of Tx messages. - */ -void FLEXCAN_FDEnable(CAN_Type *base, flexcan_mb_size_t dataSize, bool brs); -#endif - /* @} */ /*! diff --git a/ext/hal/nxp/mcux/drivers/kinetis/fsl_ftfx_adapter.h b/ext/hal/nxp/mcux/drivers/kinetis/fsl_ftfx_adapter.h new file mode 100644 index 00000000000..5d4aef45429 --- /dev/null +++ b/ext/hal/nxp/mcux/drivers/kinetis/fsl_ftfx_adapter.h @@ -0,0 +1,397 @@ +/* +* Copyright 2017-2018 NXP +* All rights reserved. +* +* SPDX-License-Identifier: BSD-3-Clause +* +*/ + +#ifndef _FSL_FTFX_ADAPTER_H_ +#define _FSL_FTFX_ADAPTER_H_ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +#define INVALID_REG_MASK (0) +#define INVALID_REG_SHIFT (0) +#define INVALID_REG_ADDRESS (0x00U) +#define INVALID_REG_VALUE (0x00U) + +/* @brief Flash register access type defines */ +#define FTFx_REG8_ACCESS_TYPE volatile uint8_t * +#define FTFx_REG32_ACCESS_TYPE volatile uint32_t * + +/*! + * @name Common flash register info defines + * @{ + */ +#if defined(FTFA) +#define FTFx FTFA +#define FTFx_BASE FTFA_BASE +#define FTFx_FSTAT_CCIF_MASK FTFA_FSTAT_CCIF_MASK +#define FTFx_FSTAT_RDCOLERR_MASK FTFA_FSTAT_RDCOLERR_MASK +#define FTFx_FSTAT_ACCERR_MASK FTFA_FSTAT_ACCERR_MASK +#define FTFx_FSTAT_FPVIOL_MASK FTFA_FSTAT_FPVIOL_MASK +#define FTFx_FSTAT_MGSTAT0_MASK FTFA_FSTAT_MGSTAT0_MASK +#define FTFx_FSEC_SEC_MASK FTFA_FSEC_SEC_MASK +#define FTFx_FSEC_KEYEN_MASK FTFA_FSEC_KEYEN_MASK +#if defined(FSL_FEATURE_FLASH_HAS_FLEX_RAM) && FSL_FEATURE_FLASH_HAS_FLEX_RAM +#define FTFx_FCNFG_RAMRDY_MASK FTFA_FCNFG_RAMRDY_MASK +#endif /* FSL_FEATURE_FLASH_HAS_FLEX_RAM */ +#if defined(FSL_FEATURE_FLASH_HAS_FLEX_NVM) && FSL_FEATURE_FLASH_HAS_FLEX_NVM +#define FTFx_FCNFG_EEERDY_MASK FTFA_FCNFG_EEERDY_MASK +#endif /* FSL_FEATURE_FLASH_HAS_FLEX_NVM */ +#elif defined(FTFE) +#define FTFx FTFE +#define FTFx_BASE FTFE_BASE +#define FTFx_FSTAT_CCIF_MASK FTFE_FSTAT_CCIF_MASK +#define FTFx_FSTAT_RDCOLERR_MASK FTFE_FSTAT_RDCOLERR_MASK +#define FTFx_FSTAT_ACCERR_MASK FTFE_FSTAT_ACCERR_MASK +#define FTFx_FSTAT_FPVIOL_MASK FTFE_FSTAT_FPVIOL_MASK +#define FTFx_FSTAT_MGSTAT0_MASK FTFE_FSTAT_MGSTAT0_MASK +#define FTFx_FSEC_SEC_MASK FTFE_FSEC_SEC_MASK +#define FTFx_FSEC_KEYEN_MASK FTFE_FSEC_KEYEN_MASK +#if defined(FSL_FEATURE_FLASH_HAS_FLEX_RAM) && FSL_FEATURE_FLASH_HAS_FLEX_RAM +#define FTFx_FCNFG_RAMRDY_MASK FTFE_FCNFG_RAMRDY_MASK +#endif /* FSL_FEATURE_FLASH_HAS_FLEX_RAM */ +#if defined(FSL_FEATURE_FLASH_HAS_FLEX_NVM) && FSL_FEATURE_FLASH_HAS_FLEX_NVM +#define FTFx_FCNFG_EEERDY_MASK FTFE_FCNFG_EEERDY_MASK +#endif /* FSL_FEATURE_FLASH_HAS_FLEX_NVM */ +#elif defined(FTFL) +#define FTFx FTFL +#define FTFx_BASE FTFL_BASE +#define FTFx_FSTAT_CCIF_MASK FTFL_FSTAT_CCIF_MASK +#define FTFx_FSTAT_RDCOLERR_MASK FTFL_FSTAT_RDCOLERR_MASK +#define FTFx_FSTAT_ACCERR_MASK FTFL_FSTAT_ACCERR_MASK +#define FTFx_FSTAT_FPVIOL_MASK FTFL_FSTAT_FPVIOL_MASK +#define FTFx_FSTAT_MGSTAT0_MASK FTFL_FSTAT_MGSTAT0_MASK +#define FTFx_FSEC_SEC_MASK FTFL_FSEC_SEC_MASK +#define FTFx_FSEC_KEYEN_MASK FTFL_FSEC_KEYEN_MASK +#if defined(FSL_FEATURE_FLASH_HAS_FLEX_RAM) && FSL_FEATURE_FLASH_HAS_FLEX_RAM +#define FTFx_FCNFG_RAMRDY_MASK FTFL_FCNFG_RAMRDY_MASK +#endif /* FSL_FEATURE_FLASH_HAS_FLEX_RAM */ +#if defined(FSL_FEATURE_FLASH_HAS_FLEX_NVM) && FSL_FEATURE_FLASH_HAS_FLEX_NVM +#define FTFx_FCNFG_EEERDY_MASK FTFL_FCNFG_EEERDY_MASK +#endif /* FSL_FEATURE_FLASH_HAS_FLEX_NVM */ +#else +#error "Unknown flash controller" +#endif +/*@}*/ + +/*! + * @name Common flash register access info defines + * @{ + */ +#define FTFx_FCCOB3_REG (FTFx->FCCOB3) +#define FTFx_FCCOB5_REG (FTFx->FCCOB5) +#define FTFx_FCCOB6_REG (FTFx->FCCOB6) +#define FTFx_FCCOB7_REG (FTFx->FCCOB7) + +#if defined(FTFA_FPROTSL_PROTS_MASK) || defined(FTFE_FPROTSL_PROTS_MASK) || defined(FTFL_FPROTSL_PROTS_MASK) +#define FTFx_FLASH1_HAS_INT_PROT_REG (1) +#define FTFx_FPROTSH_REG (FTFx->FPROTSH) +#define FTFx_FPROTSL_REG (FTFx->FPROTSL) +#else +#define FTFx_FLASH1_HAS_INT_PROT_REG (0) +#define FTFx_FPROTSH_REG (*(uint8_t *)INVALID_REG_ADDRESS) +#define FTFx_FPROTSL_REG (*(uint8_t *)INVALID_REG_ADDRESS) +#endif + +#if defined(FTFA_FPROTH0_PROT_MASK) || defined(FTFE_FPROTH0_PROT_MASK) || defined(FTFL_FPROTH0_PROT_MASK) +#define FTFx_FPROT_HIGH_REG (FTFx->FPROTH3) +#define FTFx_FPROTH3_REG (FTFx->FPROTH3) +#define FTFx_FPROTH2_REG (FTFx->FPROTH2) +#define FTFx_FPROTH1_REG (FTFx->FPROTH1) +#define FTFx_FPROTH0_REG (FTFx->FPROTH0) +#else +#define FTFx_FPROT_HIGH_REG (*(uint8_t *)INVALID_REG_ADDRESS) +#define FTFx_FPROTH3_REG (*(uint8_t *)INVALID_REG_ADDRESS) +#define FTFx_FPROTH2_REG (*(uint8_t *)INVALID_REG_ADDRESS) +#define FTFx_FPROTH1_REG (*(uint8_t *)INVALID_REG_ADDRESS) +#define FTFx_FPROTH0_REG (*(uint8_t *)INVALID_REG_ADDRESS) +#endif + +#if defined(FTFA_FPROTL0_PROT_MASK) || defined(FTFE_FPROTL0_PROT_MASK) || defined(FTFL_FPROTL0_PROT_MASK) +#define FTFx_FPROT_LOW_REG (FTFx->FPROTL3) +#define FTFx_FPROTL3_REG (FTFx->FPROTL3) +#define FTFx_FPROTL2_REG (FTFx->FPROTL2) +#define FTFx_FPROTL1_REG (FTFx->FPROTL1) +#define FTFx_FPROTL0_REG (FTFx->FPROTL0) +#elif defined(FTFA_FPROT0_PROT_MASK) || defined(FTFE_FPROT0_PROT_MASK) || defined(FTFL_FPROT0_PROT_MASK) +#define FTFx_FPROT_LOW_REG (FTFx->FPROT3) +#define FTFx_FPROTL3_REG (FTFx->FPROT3) +#define FTFx_FPROTL2_REG (FTFx->FPROT2) +#define FTFx_FPROTL1_REG (FTFx->FPROT1) +#define FTFx_FPROTL0_REG (FTFx->FPROT0) +#else +#define FTFx_FPROT_LOW_REG (*(uint8_t *)INVALID_REG_ADDRESS) +#define FTFx_FPROTL3_REG (*(uint8_t *)INVALID_REG_ADDRESS) +#define FTFx_FPROTL2_REG (*(uint8_t *)INVALID_REG_ADDRESS) +#define FTFx_FPROTL1_REG (*(uint8_t *)INVALID_REG_ADDRESS) +#define FTFx_FPROTL0_REG (*(uint8_t *)INVALID_REG_ADDRESS) +#endif + +#if defined(FTFA_FACSSS_SGSIZE_S_MASK) || defined(FTFE_FACSSS_SGSIZE_S_MASK) || defined(FTFL_FACSSS_SGSIZE_S_MASK) +#define FTFx_FLASH1_HAS_INT_XACC_REG (1) +#define FTFx_XACCSH_REG (FTFx->XACCSH) +#define FTFx_XACCSL_REG (FTFx->XACCSL) +#define FTFx_FACSSS_REG (FTFx->FACSSS) +#define FTFx_FACSNS_REG (FTFx->FACSNS) +#else +#define FTFx_FLASH1_HAS_INT_XACC_REG (0) +#define FTFx_XACCSH_REG (*(uint8_t *)INVALID_REG_ADDRESS) +#define FTFx_XACCSL_REG (*(uint8_t *)INVALID_REG_ADDRESS) +#define FTFx_FACSSS_REG (*(uint8_t *)INVALID_REG_ADDRESS) +#define FTFx_FACSNS_REG (*(uint8_t *)INVALID_REG_ADDRESS) +#endif + +#if (defined(FTFA_FACSS_SGSIZE_MASK) || defined(FTFE_FACSS_SGSIZE_MASK) || defined(FTFL_FACSS_SGSIZE_MASK) || \ + defined(FTFA_FACSS_SGSIZE_S_MASK) || defined(FTFE_FACSS_SGSIZE_S_MASK) || defined(FTFL_FACSS_SGSIZE_S_MASK)) +//#define FTFx_FLASH0_HAS_INT_XACC_REG (FTFx_FLASH1_HAS_INT_XACC_REG) +#define FTFx_XACCH3_REG (FTFx->XACCH3) +#define FTFx_XACCL3_REG (FTFx->XACCL3) +#define FTFx_FACSS_REG (FTFx->FACSS) +#define FTFx_FACSN_REG (FTFx->FACSN) +#else +#define FTFx_FLASH0_HAS_INT_XACC_REG (0) +#define FTFx_XACCH3_REG (*(uint8_t *)INVALID_REG_ADDRESS) +#define FTFx_XACCL3_REG (*(uint8_t *)INVALID_REG_ADDRESS) +#define FTFx_FACSS_REG (*(uint8_t *)INVALID_REG_ADDRESS) +#define FTFx_FACSN_REG (*(uint8_t *)INVALID_REG_ADDRESS) +#endif +/*@}*/ + +/*! + * @brief MCM cache register access info defines. + */ +#if defined(MCM_PLACR_CFCC_MASK) +#define MCM_CACHE_CLEAR_MASK MCM_PLACR_CFCC_MASK +#define MCM_CACHE_CLEAR_SHIFT MCM_PLACR_CFCC_SHIFT +#if defined(MCM0) +#define MCM0_CACHE_REG MCM0->PLACR +#elif defined(MCM) && (!defined(MCM1)) +#define MCM0_CACHE_REG MCM->PLACR +#endif +#if defined(MCM1) +#define MCM1_CACHE_REG MCM1->PLACR +#elif defined(MCM) && (!defined(MCM0)) +#define MCM1_CACHE_REG MCM->PLACR +#endif +#else +#define MCM_CACHE_CLEAR_MASK INVALID_REG_MASK +#define MCM_CACHE_CLEAR_SHIFT INVALID_REG_SHIFT +#define MCM0_CACHE_REG (*(uint32_t *)INVALID_REG_ADDRESS) +#define MCM1_CACHE_REG (*(uint32_t *)INVALID_REG_ADDRESS) +#endif + +/*! + * @brief FMC cache register access info defines. + */ +#if defined(FMC_PFB01CR_S_INV_MASK) +#define FMC_SPECULATION_INVALIDATE_MASK FMC_PFB01CR_S_INV_MASK +#define FMC_SPECULATION_INVALIDATE_SHIFT FMC_PFB01CR_S_INV_SHIFT +#define FMC_SPECULATION_INVALIDATE_REG FMC->PFB01CR +#elif defined(FMC_PFB01CR_S_B_INV_MASK) +#define FMC_SPECULATION_INVALIDATE_MASK FMC_PFB01CR_S_B_INV_MASK +#define FMC_SPECULATION_INVALIDATE_SHIFT FMC_PFB01CR_S_B_INV_SHIFT +#define FMC_SPECULATION_INVALIDATE_REG FMC->PFB01CR +#elif defined(FMC_PFB0CR_S_INV_MASK) +#define FMC_SPECULATION_INVALIDATE_MASK FMC_PFB0CR_S_INV_MASK +#define FMC_SPECULATION_INVALIDATE_SHIFT FMC_PFB0CR_S_INV_SHIFT +#define FMC_SPECULATION_INVALIDATE_REG FMC->PFB0CR +#elif defined(FMC_PFB0CR_S_B_INV_MASK) +#define FMC_SPECULATION_INVALIDATE_MASK FMC_PFB0CR_S_B_INV_MASK +#define FMC_SPECULATION_INVALIDATE_SHIFT FMC_PFB0CR_S_B_INV_SHIFT +#define FMC_SPECULATION_INVALIDATE_REG FMC->PFB0CR +#else +#define FMC_SPECULATION_INVALIDATE_MASK INVALID_REG_MASK +#define FMC_SPECULATION_INVALIDATE_SHIFT INVALID_REG_SHIFT +#define FMC_SPECULATION_INVALIDATE(x) (((uint32_t)(((uint32_t)(x)) << INVALID_REG_SHIFT)) & INVALID_REG_MASK) +#define FMC_SPECULATION_INVALIDATE_REG (*(uint32_t *)INVALID_REG_ADDRESS) +#endif + +#if defined(FMC_PFB01CR_CINV_WAY_MASK) +#define FMC_CACHE_CLEAR_MASK FMC_PFB01CR_CINV_WAY_MASK +#define FMC_CACHE_CLEAR_SHIFT FMC_PFB01CR_CINV_WAY_SHIFT +#define FMC_CACHE_CLEAR(x) FMC_PFB01CR_CINV_WAY(x) +#elif defined(FMC_PFB0CR_CINV_WAY_MASK) +#define FMC_CACHE_CLEAR_MASK FMC_PFB0CR_CINV_WAY_MASK +#define FMC_CACHE_CLEAR_SHIFT FMC_PFB0CR_CINV_WAY_SHIFT +#define FMC_CACHE_CLEAR(x) FMC_PFB0CR_CINV_WAY(x) +#else +#define FMC_CACHE_CLEAR_MASK INVALID_REG_MASK +#define FMC_CACHE_CLEAR_SHIFT INVALID_REG_SHIFT +#define FMC_CACHE_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << INVALID_REG_SHIFT)) & INVALID_REG_MASK) +#endif + +#if defined(FMC_PFB01CR_B0DPE_MASK) +#define FMC_CACHE_B0DPE_MASK FMC_PFB01CR_B0DPE_MASK +#define FMC_CACHE_B0IPE_MASK FMC_PFB01CR_B0IPE_MASK +#define FMC_CACHE_REG FMC->PFB01CR +#elif defined(FMC_PFB0CR_B0DPE_MASK) +#define FMC_CACHE_B0DPE_MASK FMC_PFB0CR_B0DPE_MASK +#define FMC_CACHE_B0IPE_MASK FMC_PFB0CR_B0IPE_MASK +#define FMC_CACHE_REG FMC->PFB0CR +#else +#define FMC_CACHE_B0DPE_MASK INVALID_REG_MASK +#define FMC_CACHE_B0IPE_MASK INVALID_REG_MASK +#define FMC_CACHE_REG (*(uint32_t *)INVALID_REG_ADDRESS) +#endif + +/*! + * @brief MSCM cache register access info defines. + */ +#if defined(MSCM_OCMDR_OCM1_MASK) +#define MSCM_SPECULATION_SET_MASK MSCM_OCMDR_OCM1_MASK +#define MSCM_SPECULATION_SET_SHIFT MSCM_OCMDR_OCM1_SHIFT +#define MSCM_SPECULATION_SET(x) MSCM_OCMDR_OCM1(x) +#elif defined(MSCM_OCMDR0_OCM1_MASK) || defined(MSCM_OCMDR1_OCM1_MASK) +#define MSCM_SPECULATION_SET_MASK MSCM_OCMDR0_OCM1_MASK +#define MSCM_SPECULATION_SET_SHIFT MSCM_OCMDR0_OCM1_SHIFT +#define MSCM_SPECULATION_SET(x) MSCM_OCMDR0_OCM1(x) +#elif defined(MSCM_OCMDR_OCMC1_MASK) +#define MSCM_SPECULATION_SET_MASK MSCM_OCMDR_OCMC1_MASK +#define MSCM_SPECULATION_SET_SHIFT MSCM_OCMDR_OCMC1_SHIFT +#define MSCM_SPECULATION_SET(x) MSCM_OCMDR_OCMC1(x) +#else +#define MSCM_SPECULATION_SET_MASK INVALID_REG_MASK +#define MSCM_SPECULATION_SET_SHIFT INVALID_REG_SHIFT +#define MSCM_SPECULATION_SET(x) (((uint32_t)(((uint32_t)(x)) << INVALID_REG_SHIFT)) & INVALID_REG_MASK) +#endif + +#if defined(MSCM_OCMDR_OCM2_MASK) +#define MSCM_CACHE_CLEAR_MASK MSCM_OCMDR_OCM2_MASK +#define MSCM_CACHE_CLEAR_SHIFT MSCM_OCMDR_OCM2_SHIFT +#define MSCM_CACHE_CLEAR(x) MSCM_OCMDR_OCM2(x) +#else +#define MSCM_CACHE_CLEAR_MASK INVALID_REG_MASK +#define MSCM_CACHE_CLEAR_SHIFT INVALID_REG_SHIFT +#define MSCM_CACHE_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << INVALID_REG_SHIFT)) & INVALID_REG_MASK) +#endif + +#if defined(MSCM_OCMDR_OCM1_MASK) || defined(MSCM_OCMDR_OCMC1_MASK) +#define MSCM_OCMDR0_REG MSCM->OCMDR[0] +#define MSCM_OCMDR1_REG MSCM->OCMDR[1] +#elif defined(MSCM_OCMDR0_OCM1_MASK) || defined(MSCM_OCMDR1_OCM1_MASK) +#define MSCM_OCMDR0_REG MSCM->OCMDR0 +#define MSCM_OCMDR1_REG MSCM->OCMDR1 +#else +#define MSCM_OCMDR0_REG (*(uint32_t *)INVALID_REG_ADDRESS) +#define MSCM_OCMDR1_REG (*(uint32_t *)INVALID_REG_ADDRESS) +#endif + +/*! + * @brief MSCM prefetch speculation defines. + */ +#define MSCM_OCMDR_OCMC1_DFDS_MASK (0x10U) +#define MSCM_OCMDR_OCMC1_DFCS_MASK (0x20U) +#define MSCM_OCMDR_OCMC1_DFDS_SHIFT (4U) +#define MSCM_OCMDR_OCMC1_DFCS_SHIFT (5U) + +/*! + * @brief SIM PFSIZE register access info defines. + */ +#if defined(SIM_FCFG1_CORE0_PFSIZE_MASK) +#define SIM_FLASH0_PFSIZE_MASK SIM_FCFG1_CORE0_PFSIZE_MASK +#define SIM_FLASH0_PFSIZE_SHIFT SIM_FCFG1_CORE0_PFSIZE_SHIFT +#define SIM_FCFG1_REG SIM->FCFG1 +#elif defined(SIM_FCFG1_PFSIZE_MASK) +#define SIM_FLASH0_PFSIZE_MASK SIM_FCFG1_PFSIZE_MASK +#define SIM_FLASH0_PFSIZE_SHIFT SIM_FCFG1_PFSIZE_SHIFT +#define SIM_FCFG1_REG SIM->FCFG1 +#else +#define SIM_FLASH0_PFSIZE_MASK INVALID_REG_MASK +#define SIM_FLASH0_PFSIZE_SHIFT INVALID_REG_SHIFT +#define SIM_FCFG1_REG INVALID_REG_VALUE +#endif + +#if defined(SIM_FCFG1_CORE1_PFSIZE_MASK) +#define SIM_FLASH1_PFSIZE_MASK SIM_FCFG1_CORE1_PFSIZE_MASK +#define SIM_FLASH1_PFSIZE_SHIFT SIM_FCFG1_CORE1_PFSIZE_SHIFT +#else +#define SIM_FLASH1_PFSIZE_MASK INVALID_REG_MASK +#define SIM_FLASH1_PFSIZE_SHIFT INVALID_REG_SHIFT +#endif + +/*! + * @name Dual core/flash configuration + * @{ + */ +/*! @brief Redefines some flash features. */ +#if defined(FSL_FEATURE_FLASH_CURRENT_CORE_ID) +#if (FSL_FEATURE_FLASH_CURRENT_CORE_ID == 0u) +#define FLASH0_FEATURE_PFLASH_START_ADDRESS FSL_FEATURE_FLASH_PFLASH_START_ADDRESS +#define FLASH0_FEATURE_PFLASH_BLOCK_COUNT FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT +#define FLASH0_FEATURE_PFLASH_BLOCK_SIZE FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE +#define FLASH0_FEATURE_PFLASH_BLOCK_SECTOR_SIZE FSL_FEATURE_FLASH_PFLASH_BLOCK_SECTOR_SIZE +#define FLASH0_FEATURE_PFLASH_BLOCK_WRITE_UNIT_SIZE FSL_FEATURE_FLASH_PFLASH_BLOCK_WRITE_UNIT_SIZE +#define FLASH0_FEATURE_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT FSL_FEATURE_FLASH_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT +#define FLASH0_FEATURE_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT FSL_FEATURE_FLASH_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT +#define FLASH0_FEATURE_PFLASH_PROTECTION_REGION_COUNT FSL_FEATURE_FLASH_PFLASH_PROTECTION_REGION_COUNT +#define FLASH1_FEATURE_PFLASH_START_ADDRESS FSL_FEATURE_FLASH_PFLASH_1_START_ADDRESS +#define FLASH1_FEATURE_PFLASH_BLOCK_COUNT FSL_FEATURE_FLASH_PFLASH_1_BLOCK_COUNT +#define FLASH1_FEATURE_PFLASH_BLOCK_SIZE FSL_FEATURE_FLASH_PFLASH_1_BLOCK_SIZE +#define FLASH1_FEATURE_PFLASH_BLOCK_SECTOR_SIZE FSL_FEATURE_FLASH_PFLASH_1_BLOCK_SECTOR_SIZE +#define FLASH1_FEATURE_PFLASH_BLOCK_WRITE_UNIT_SIZE FSL_FEATURE_FLASH_PFLASH_1_BLOCK_WRITE_UNIT_SIZE +#if defined(FSL_FEATURE_FLASH_PFLASH_1_SECTOR_CMD_ADDRESS_ALIGMENT) && defined(FSL_FEATURE_FLASH_PFLASH_1_SECTION_CMD_ADDRESS_ALIGMENT) +#define FLASH1_FEATURE_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT FSL_FEATURE_FLASH_PFLASH_1_SECTOR_CMD_ADDRESS_ALIGMENT +#define FLASH1_FEATURE_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT FSL_FEATURE_FLASH_PFLASH_1_SECTION_CMD_ADDRESS_ALIGMENT +#else +#define FLASH1_FEATURE_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT FSL_FEATURE_FLASH_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT +#define FLASH1_FEATURE_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT FSL_FEATURE_FLASH_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT +#endif +#define FLASH1_FEATURE_PFLASH_PROTECTION_REGION_COUNT FSL_FEATURE_FLASH_PFLASH_1_PROTECTION_REGION_COUNT +#elif (FSL_FEATURE_FLASH_CURRENT_CORE_ID == 1u) +#define FLASH0_FEATURE_PFLASH_START_ADDRESS FSL_FEATURE_FLASH_PFLASH_1_START_ADDRESS +#define FLASH0_FEATURE_PFLASH_BLOCK_COUNT FSL_FEATURE_FLASH_PFLASH_1_BLOCK_COUNT +#define FLASH0_FEATURE_PFLASH_BLOCK_SIZE FSL_FEATURE_FLASH_PFLASH_1_BLOCK_SIZE +#define FLASH0_FEATURE_PFLASH_BLOCK_SECTOR_SIZE FSL_FEATURE_FLASH_PFLASH_1_BLOCK_SECTOR_SIZE +#define FLASH0_FEATURE_PFLASH_BLOCK_WRITE_UNIT_SIZE FSL_FEATURE_FLASH_PFLASH_1_BLOCK_WRITE_UNIT_SIZE +#if defined(FSL_FEATURE_FLASH_PFLASH_1_SECTOR_CMD_ADDRESS_ALIGMENT) && defined(FSL_FEATURE_FLASH_PFLASH_1_SECTION_CMD_ADDRESS_ALIGMENT) +#define FLASH0_FEATURE_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT FSL_FEATURE_FLASH_PFLASH_1_SECTOR_CMD_ADDRESS_ALIGMENT +#define FLASH0_FEATURE_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT FSL_FEATURE_FLASH_PFLASH_1_SECTION_CMD_ADDRESS_ALIGMENT +#else +#define FLASH0_FEATURE_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT FSL_FEATURE_FLASH_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT +#define FLASH0_FEATURE_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT FSL_FEATURE_FLASH_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT +#endif +#define FLASH0_FEATURE_PFLASH_PROTECTION_REGION_COUNT FSL_FEATURE_FLASH_PFLASH_1_PROTECTION_REGION_COUNT +#define FLASH1_FEATURE_PFLASH_START_ADDRESS FSL_FEATURE_FLASH_PFLASH_START_ADDRESS +#define FLASH1_FEATURE_PFLASH_BLOCK_COUNT FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT +#define FLASH1_FEATURE_PFLASH_BLOCK_SIZE FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE +#define FLASH1_FEATURE_PFLASH_BLOCK_SECTOR_SIZE FSL_FEATURE_FLASH_PFLASH_BLOCK_SECTOR_SIZE +#define FLASH1_FEATURE_PFLASH_BLOCK_WRITE_UNIT_SIZE FSL_FEATURE_FLASH_PFLASH_BLOCK_WRITE_UNIT_SIZE +#define FLASH1_FEATURE_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT FSL_FEATURE_FLASH_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT +#define FLASH1_FEATURE_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT FSL_FEATURE_FLASH_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT +#define FLASH1_FEATURE_PFLASH_PROTECTION_REGION_COUNT FSL_FEATURE_FLASH_PFLASH_PROTECTION_REGION_COUNT +#endif +#else +#define FLASH0_FEATURE_PFLASH_START_ADDRESS FSL_FEATURE_FLASH_PFLASH_START_ADDRESS +#define FLASH0_FEATURE_PFLASH_BLOCK_COUNT FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT +#define FLASH0_FEATURE_PFLASH_BLOCK_SIZE FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE +#define FLASH0_FEATURE_PFLASH_BLOCK_SECTOR_SIZE FSL_FEATURE_FLASH_PFLASH_BLOCK_SECTOR_SIZE +#define FLASH0_FEATURE_PFLASH_BLOCK_WRITE_UNIT_SIZE FSL_FEATURE_FLASH_PFLASH_BLOCK_WRITE_UNIT_SIZE +#define FLASH0_FEATURE_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT FSL_FEATURE_FLASH_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT +#define FLASH0_FEATURE_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT FSL_FEATURE_FLASH_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT +#define FLASH0_FEATURE_PFLASH_PROTECTION_REGION_COUNT FSL_FEATURE_FLASH_PFLASH_PROTECTION_REGION_COUNT +#define FLASH1_FEATURE_PFLASH_START_ADDRESS 0 +#define FLASH1_FEATURE_PFLASH_BLOCK_COUNT 0 +#define FLASH1_FEATURE_PFLASH_BLOCK_SIZE 0 +#define FLASH1_FEATURE_PFLASH_BLOCK_SECTOR_SIZE 0 +#define FLASH1_FEATURE_PFLASH_BLOCK_WRITE_UNIT_SIZE 0 +#define FLASH1_FEATURE_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT 0 +#define FLASH1_FEATURE_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT 0 +#define FLASH1_FEATURE_PFLASH_PROTECTION_REGION_COUNT 0 +#endif + +#if FLASH0_FEATURE_PFLASH_PROTECTION_REGION_COUNT > FLASH1_FEATURE_PFLASH_PROTECTION_REGION_COUNT +#define MAX_FLASH_PROT_REGION_COUNT FLASH0_FEATURE_PFLASH_PROTECTION_REGION_COUNT +#else +#define MAX_FLASH_PROT_REGION_COUNT FLASH1_FEATURE_PFLASH_PROTECTION_REGION_COUNT +#endif + +/*@}*/ + + +#endif /* _FSL_FTFX_ADAPTER_H_ */ + diff --git a/ext/hal/nxp/mcux/drivers/kinetis/fsl_ftfx_cache.c b/ext/hal/nxp/mcux/drivers/kinetis/fsl_ftfx_cache.c new file mode 100644 index 00000000000..58b805218b6 --- /dev/null +++ b/ext/hal/nxp/mcux/drivers/kinetis/fsl_ftfx_cache.c @@ -0,0 +1,539 @@ +/* +* Copyright 2013-2016 Freescale Semiconductor, Inc. +* Copyright 2016-2018 NXP +* All rights reserved. +* +* SPDX-License-Identifier: BSD-3-Clause +* +*/ + +#include "fsl_ftfx_cache.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! + * @name Flash cache and speculation control defines + * @{ + */ +#if defined(MCM_PLACR_CFCC_MASK) +#define FLASH_CACHE_IS_CONTROLLED_BY_MCM (1) +#else +#define FLASH_CACHE_IS_CONTROLLED_BY_MCM (0) +#endif + +#define FLASH_CACHE_IS_CONTROLLED_BY_MSCM (0) + +#if defined(FMC_PFB0CR_CINV_WAY_MASK) || defined(FMC_PFB01CR_CINV_WAY_MASK) +#define FLASH_CACHE_IS_CONTROLLED_BY_FMC (1) +#else +#define FLASH_CACHE_IS_CONTROLLED_BY_FMC (0) +#endif + +#if defined(MCM_PLACR_DFCS_MASK) +#define FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_MCM (1) +#else +#define FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_MCM (0) +#endif + +#if defined(MSCM_OCMDR_OCMC1_MASK) || defined(MSCM_OCMDR_OCM1_MASK) || defined(MSCM_OCMDR0_OCM1_MASK) || \ + defined(MSCM_OCMDR1_OCM1_MASK) +#define FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_MSCM (1) +#else +#define FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_MSCM (0) +#endif + +#if defined(FMC_PFB0CR_S_INV_MASK) || defined(FMC_PFB0CR_S_B_INV_MASK) || defined(FMC_PFB01CR_S_INV_MASK) || \ + defined(FMC_PFB01CR_S_B_INV_MASK) +#define FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_FMC (1) +#else +#define FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_FMC (0) +#endif + +#if FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_MSCM || FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_FMC || \ + FLASH_CACHE_IS_CONTROLLED_BY_MCM || FLASH_CACHE_IS_CONTROLLED_BY_FMC || FLASH_CACHE_IS_CONTROLLED_BY_MSCM +#define FLASH_IS_CACHE_INVALIDATION_AVAILABLE (1) +#else +#define FLASH_IS_CACHE_INVALIDATION_AVAILABLE (0) +#endif +/*@}*/ + +/*! @brief A function pointer used to point to relocated ftfx_common_bit_operation() */ +typedef void (*callftfxCommonBitOperation_t)(FTFx_REG32_ACCESS_TYPE base, + uint32_t bitMask, + uint32_t bitShift, + uint32_t bitValue); + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +#if FLASH_CACHE_IS_CONTROLLED_BY_MCM +/*! @brief Performs the cache clear to the flash by MCM.*/ +void mcm_flash_cache_clear(ftfx_cache_config_t *config); +#endif /* FLASH_CACHE_IS_CONTROLLED_BY_MCM */ + +#if FLASH_CACHE_IS_CONTROLLED_BY_MSCM +/*! @brief Performs the cache clear to the flash by MSCM.*/ +void mscm_flash_cache_clear(ftfx_cache_config_t *config); +#endif /* FLASH_CACHE_IS_CONTROLLED_BY_MSCM */ + +#if FLASH_CACHE_IS_CONTROLLED_BY_FMC +/*! @brief Performs the cache clear to the flash by FMC.*/ +void fmc_flash_cache_clear(ftfx_cache_config_t *config); +#endif /* FLASH_CACHE_IS_CONTROLLED_BY_FMC */ + +#if FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_MSCM +/*! @brief Sets the prefetch speculation buffer to the flash by MSCM.*/ +void mscm_flash_prefetch_speculation_enable(ftfx_cache_config_t *config, bool enable); +#endif /* FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_MSCM */ + +#if FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_FMC +/*! @brief Performs the prefetch speculation buffer clear to the flash by FMC.*/ +void fmc_flash_prefetch_speculation_clear(ftfx_cache_config_t *config); +#endif /* FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_FMC */ + +#if FTFx_DRIVER_IS_FLASH_RESIDENT && FLASH_IS_CACHE_INVALIDATION_AVAILABLE +/*! @brief Copy flash_cache_clear_command() to RAM*/ +static void ftfx_copy_common_bit_operation_to_ram(uint32_t *ftfxCommonBitOperation); +#endif /* FTFx_DRIVER_IS_FLASH_RESIDENT */ + +/******************************************************************************* + * Variables + ******************************************************************************/ + +#if FTFx_DRIVER_IS_FLASH_RESIDENT && FLASH_IS_CACHE_INVALIDATION_AVAILABLE +/*! + * @brief Position independent code of ftfx_common_bit_operation() + * + * Note1: The prototype of C function is shown as below: + * @code + * void ftfx_common_bit_operation(FTFx_REG32_ACCESS_TYPE base, uint32_t bitMask, uint32_t bitShift, uint32_t + * bitValue) + * { + * if (bitMask) + * { + * uint32_t value = (((uint32_t)(((uint32_t)(bitValue)) << bitShift)) & bitMask); + * *base = (*base & (~bitMask)) | value; + * } + * + * __ISB(); + * __DSB(); + * } + * @endcode + * Note2: The binary code is generated by IAR 7.70.1 + */ +static const uint16_t s_ftfxCommonBitOperationFunctionCode[] = { + 0xb510, /* PUSH {R4, LR} */ + 0x2900, /* CMP R1, #0 */ + 0xd005, /* BEQ.N @12 */ + 0x6804, /* LDR R4, [R0] */ + 0x438c, /* BICS R4, R4, R1 */ + 0x4093, /* LSLS R3, R3, R2 */ + 0x4019, /* ANDS R1, R1, R3 */ + 0x4321, /* ORRS R1, R1, R4 */ + 0x6001, /* STR R1, [R0] */ + /* @12: */ + 0xf3bf, 0x8f6f, /* ISB */ + 0xf3bf, 0x8f4f, /* DSB */ + 0xbd10 /* POP {R4, PC} */ +}; + +#if (!FTFx_DRIVER_IS_EXPORTED) +/*! @brief A static buffer used to hold ftfx_common_bit_operation() */ +static uint32_t s_ftfxCommonBitOperation[kFTFx_CACHE_RamFuncMaxSizeInWords]; +#endif /* (!FTFx_DRIVER_IS_EXPORTED) */ +#endif /* FLASH_IS_CACHE_INVALIDATION_AVAILABLE && FTFx_DRIVER_IS_FLASH_RESIDENT */ + +/******************************************************************************* + * Code + ******************************************************************************/ + +status_t FTFx_CACHE_Init(ftfx_cache_config_t *config) +{ + if (config == NULL) + { + return kStatus_FTFx_InvalidArgument; + } + +/* copy required flash commands to RAM */ +#if FTFx_DRIVER_IS_FLASH_RESIDENT && FLASH_IS_CACHE_INVALIDATION_AVAILABLE + if (NULL == config->comBitOperFuncAddr) + { +#if FTFx_DRIVER_IS_EXPORTED + return kStatus_FTFx_ExecuteInRamFunctionNotReady; +#else + config->comBitOperFuncAddr = s_ftfxCommonBitOperation; +#endif /* FTFx_DRIVER_IS_EXPORTED */ + } + ftfx_copy_common_bit_operation_to_ram(config->comBitOperFuncAddr); +#endif /* FLASH_IS_CACHE_INVALIDATION_AVAILABLE && FTFx_DRIVER_IS_FLASH_RESIDENT */ + + return kStatus_FTFx_Success; +} + +/*! + * @brief Flash Cache/Prefetch/Speculation Clear Process + * + * This function is used to perform the cache and prefetch speculation clear process to the flash. + */ +status_t FTFx_CACHE_ClearCachePrefetchSpeculation(ftfx_cache_config_t *config, bool isPreProcess) +{ + /* We pass the ftfx register address as a parameter to ftfx_common_bit_operation() instead of using + * pre-processed MACROs or a global variable in ftfx_common_bit_operation() + * to make sure that ftfx_common_bit_operation() will be compiled into position-independent code (PIC). */ + if (!isPreProcess) + { +#if FLASH_CACHE_IS_CONTROLLED_BY_MCM + mcm_flash_cache_clear(config); +#endif +#if FLASH_CACHE_IS_CONTROLLED_BY_MSCM + mscm_flash_cache_clear(config); +#endif +#if FLASH_CACHE_IS_CONTROLLED_BY_FMC + fmc_flash_cache_clear(config); +#endif +#if FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_MSCM + mscm_flash_prefetch_speculation_enable(config, true); +#endif +#if FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_FMC + fmc_flash_prefetch_speculation_clear(config); +#endif + } + if (isPreProcess) + { +#if FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_MSCM + mscm_flash_prefetch_speculation_enable(config, false); +#endif + } + + return kStatus_FTFx_Success; +} + +status_t FTFx_CACHE_PflashSetPrefetchSpeculation(ftfx_prefetch_speculation_status_t *speculationStatus) +{ +#if FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_MCM + { + if (speculationStatus->instructionOff) + { + if (!speculationStatus->dataOff) + { + return kStatus_FTFx_InvalidSpeculationOption; + } + else + { + MCM0_CACHE_REG |= MCM_PLACR_DFCS_MASK; + } + } + else + { + MCM0_CACHE_REG &= ~MCM_PLACR_DFCS_MASK; + if (!speculationStatus->dataOff) + { + MCM0_CACHE_REG |= MCM_PLACR_EFDS_MASK; + } + else + { + MCM0_CACHE_REG &= ~MCM_PLACR_EFDS_MASK; + } + } + } +#elif FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_FMC + { + if (!speculationStatus->instructionOff) + { + FMC_CACHE_REG |= FMC_CACHE_B0IPE_MASK; + } + else + { + FMC_CACHE_REG &= ~FMC_CACHE_B0IPE_MASK; + } + if (!speculationStatus->dataOff) + { + FMC_CACHE_REG |= FMC_CACHE_B0DPE_MASK; + } + else + { + FMC_CACHE_REG &= ~FMC_CACHE_B0DPE_MASK; + } + + /* Invalidate Prefetch Speculation Buffer */ + FMC_SPECULATION_INVALIDATE_REG |= FMC_SPECULATION_INVALIDATE_MASK; + } +#elif FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_MSCM + { + if (speculationStatus->instructionOff) + { + if (!speculationStatus->dataOff) + { + return kStatus_FTFx_InvalidSpeculationOption; + } + else + { + MSCM_OCMDR0_REG |= MSCM_OCMDR_OCMC1_DFCS_MASK; + } + } + else + { + MSCM_OCMDR0_REG &= ~MSCM_OCMDR_OCMC1_DFCS_MASK; + if (!speculationStatus->dataOff) + { + MSCM_OCMDR0_REG &= ~MSCM_OCMDR_OCMC1_DFDS_MASK; + } + else + { + MSCM_OCMDR0_REG |= MSCM_OCMDR_OCMC1_DFDS_MASK; + } + } + } +#endif /* FSL_FEATURE_FTFx_MCM_FLASH_CACHE_CONTROLS */ + + return kStatus_FTFx_Success; +} + +status_t FTFx_CACHE_PflashGetPrefetchSpeculation(ftfx_prefetch_speculation_status_t *speculationStatus) +{ + memset(speculationStatus, 0, sizeof(ftfx_prefetch_speculation_status_t)); + + /* Assuming that all speculation options are enabled. */ + speculationStatus->instructionOff = false; + speculationStatus->dataOff = false; + +#if FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_MCM + { + uint32_t value = MCM0_CACHE_REG; + if (value & MCM_PLACR_DFCS_MASK) + { + /* Speculation buffer is off. */ + speculationStatus->instructionOff = true; + speculationStatus->dataOff = true; + } + else + { + /* Speculation buffer is on for instruction. */ + if (!(value & MCM_PLACR_EFDS_MASK)) + { + /* Speculation buffer is off for data. */ + speculationStatus->dataOff = true; + } + } + } +#elif FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_FMC + { + uint32_t value = FMC_CACHE_REG; + if (!(value & FMC_CACHE_B0DPE_MASK)) + { + /* Do not prefetch in response to data references. */ + speculationStatus->dataOff = true; + } + if (!(value & FMC_CACHE_B0IPE_MASK)) + { + /* Do not prefetch in response to instruction fetches. */ + speculationStatus->instructionOff = true; + } + } +#elif FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_MSCM + { + uint32_t value = MSCM_OCMDR0_REG; + if (value & MSCM_OCMDR_OCMC1_DFCS_MASK) + { + /* Speculation buffer is off. */ + speculationStatus->instructionOff = true; + speculationStatus->dataOff = true; + } + else + { + /* Speculation buffer is on for instruction. */ + if (value & MSCM_OCMDR_OCMC1_DFDS_MASK) + { + /* Speculation buffer is off for data. */ + speculationStatus->dataOff = true; + } + } + } +#endif + + return kStatus_FTFx_Success; +} + +#if FTFx_DRIVER_IS_FLASH_RESIDENT && FLASH_IS_CACHE_INVALIDATION_AVAILABLE +/*! @brief Copy PIC of ftfx_common_bit_operation() to RAM */ +static void ftfx_copy_common_bit_operation_to_ram(uint32_t *ftfxCommonBitOperation) +{ + assert(sizeof(s_ftfxCommonBitOperationFunctionCode) <= (kFTFx_CACHE_RamFuncMaxSizeInWords * 4)); + + memcpy(ftfxCommonBitOperation, s_ftfxCommonBitOperationFunctionCode, + sizeof(s_ftfxCommonBitOperationFunctionCode)); +} +#endif /* FTFx_DRIVER_IS_FLASH_RESIDENT && FLASH_IS_CACHE_INVALIDATION_AVAILABLE */ + +#if FLASH_CACHE_IS_CONTROLLED_BY_MCM +/*! @brief Performs the cache clear to the flash by MCM.*/ +void mcm_flash_cache_clear(ftfx_cache_config_t *config) +{ + FTFx_REG32_ACCESS_TYPE regBase; + +#if defined(MCM0_CACHE_REG) + regBase = (FTFx_REG32_ACCESS_TYPE)&MCM0_CACHE_REG; +#elif defined(MCM1_CACHE_REG) + regBase = (FTFx_REG32_ACCESS_TYPE)&MCM1_CACHE_REG; +#endif + +#if FTFx_DRIVER_IS_FLASH_RESIDENT + /* Since the value of ARM function pointer is always odd, but the real start address + * of function memory should be even, that's why +1 operation exist. */ + callftfxCommonBitOperation_t callftfxCommonBitOperation = (callftfxCommonBitOperation_t)((uint32_t)config->comBitOperFuncAddr + 1); + callftfxCommonBitOperation(regBase, MCM_CACHE_CLEAR_MASK, MCM_CACHE_CLEAR_SHIFT, 1U); +#else /* !FTFx_DRIVER_IS_FLASH_RESIDENT */ + *regBase |= MCM_CACHE_CLEAR_MASK; + + /* Memory barriers for good measure. + * All Cache, Branch predictor and TLB maintenance operations before this instruction complete */ + __ISB(); + __DSB(); +#endif /* FTFx_DRIVER_IS_FLASH_RESIDENT */ +} +#endif /* FLASH_CACHE_IS_CONTROLLED_BY_MCM */ + +#if FLASH_CACHE_IS_CONTROLLED_BY_MSCM +/*! @brief Performs the cache clear to the flash by MSCM.*/ +void mscm_flash_cache_clear(ftfx_cache_config_t *config) +{ + uint8_t setValue = 0x1U; + +/* The OCMDR[0] is always used to cache main Pflash*/ +/* For device with FlexNVM support, the OCMDR[1] is used to cache Dflash. + * For device with secondary flash support, the OCMDR[1] is used to cache secondary Pflash. */ +#if FTFx_DRIVER_IS_FLASH_RESIDENT + /* Since the value of ARM function pointer is always odd, but the real start address + * of function memory should be even, that's why +1 operation exist. */ + callftfxCommonBitOperation_t callftfxCommonBitOperation = (callftfxCommonBitOperation_t)((uint32_t)config->comBitOperFuncAddr + 1); + switch (config->flashMemoryIndex) + { + case kFLASH_MemoryIndexSecondaryFlash: + callftfxCommonBitOperation((FTFx_REG32_ACCESS_TYPE)&MSCM_OCMDR1_REG, MSCM_CACHE_CLEAR_MASK, + MSCM_CACHE_CLEAR_SHIFT, setValue); + break; + case kFLASH_MemoryIndexPrimaryFlash: + default: + callftfxCommonBitOperation((FTFx_REG32_ACCESS_TYPE)&MSCM_OCMDR0_REG, MSCM_CACHE_CLEAR_MASK, + MSCM_CACHE_CLEAR_SHIFT, setValue); + break; + } +#else /* !FTFx_DRIVER_IS_FLASH_RESIDENT */ + switch (config->flashMemoryIndex) + { + case kFLASH_MemoryIndexSecondaryFlash: + MSCM_OCMDR1_REG = (MSCM_OCMDR1_REG & (~MSCM_CACHE_CLEAR_MASK)) | MSCM_CACHE_CLEAR(setValue); + /* Each cache clear instruction should be followed by below code*/ + __ISB(); + __DSB(); + break; + case kFLASH_MemoryIndexPrimaryFlash: + default: + MSCM_OCMDR0_REG = (MSCM_OCMDR0_REG & (~MSCM_CACHE_CLEAR_MASK)) | MSCM_CACHE_CLEAR(setValue); + /* Memory barriers for good measure. + * All Cache, Branch predictor and TLB maintenance operations before this instruction complete */ + __ISB(); + __DSB(); + break; + } +#endif /* FTFx_DRIVER_IS_FLASH_RESIDENT */ +} +#endif /* FLASH_CACHE_IS_CONTROLLED_BY_MSCM */ + +#if FLASH_CACHE_IS_CONTROLLED_BY_FMC +/*! @brief Performs the cache clear to the flash by FMC.*/ +void fmc_flash_cache_clear(ftfx_cache_config_t *config) +{ +#if FTFx_DRIVER_IS_FLASH_RESIDENT + /* Since the value of ARM function pointer is always odd, but the real start address + * of function memory should be even, that's why +1 operation exist. */ + callftfxCommonBitOperation_t callftfxCommonBitOperation = (callftfxCommonBitOperation_t)((uint32_t)config->comBitOperFuncAddr + 1); + callftfxCommonBitOperation((FTFx_REG32_ACCESS_TYPE)&FMC_CACHE_REG, FMC_CACHE_CLEAR_MASK, FMC_CACHE_CLEAR_SHIFT, 0xFU); +#else /* !FTFx_DRIVER_IS_FLASH_RESIDENT */ + FMC_CACHE_REG = (FMC_CACHE_REG & (~FMC_CACHE_CLEAR_MASK)) | FMC_CACHE_CLEAR(~0); + /* Memory barriers for good measure. + * All Cache, Branch predictor and TLB maintenance operations before this instruction complete */ + __ISB(); + __DSB(); +#endif /* FTFx_DRIVER_IS_FLASH_RESIDENT */ +} +#endif /* FLASH_CACHE_IS_CONTROLLED_BY_FMC */ + +#if FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_MSCM +/*! @brief Performs the prefetch speculation buffer clear to the flash by MSCM.*/ +void mscm_flash_prefetch_speculation_enable(ftfx_cache_config_t *config, bool enable) +{ + uint8_t setValue; + if (enable) + { + setValue = 0x0U; + } + else + { + setValue = 0x3U; + } + +/* The OCMDR[0] is always used to prefetch main Pflash*/ +/* For device with FlexNVM support, the OCMDR[1] is used to prefetch Dflash. + * For device with secondary flash support, the OCMDR[1] is used to prefetch secondary Pflash. */ +#if FTFx_DRIVER_IS_FLASH_RESIDENT + /* Since the value of ARM function pointer is always odd, but the real start address + * of function memory should be even, that's why +1 operation exist. */ + callftfxCommonBitOperation_t callftfxCommonBitOperation = (callftfxCommonBitOperation_t)((uint32_t)config->comBitOperFuncAddr + 1); + switch (config->flashMemoryIndex) + { + case 1: + callftfxCommonBitOperation((FTFx_REG32_ACCESS_TYPE)&MSCM_OCMDR1_REG, MSCM_SPECULATION_SET_MASK, + MSCM_SPECULATION_SET_SHIFT, setValue); + break; + case 0: + default: + callftfxCommonBitOperation((FTFx_REG32_ACCESS_TYPE)&MSCM_OCMDR0_REG, MSCM_SPECULATION_SET_MASK, + MSCM_SPECULATION_SET_SHIFT, setValue); + break; + } +#else /* !FTFx_DRIVER_IS_FLASH_RESIDENT */ + switch (config->flashMemoryIndex) + { + case kFLASH_MemoryIndexSecondaryFlash: + MSCM_OCMDR1_REG = (MSCM_OCMDR1_REG & (~MSCM_SPECULATION_SET_MASK)) | MSCM_SPECULATION_SET(setValue); + /* Each cache clear instruction should be followed by below code*/ + __ISB(); + __DSB(); + break; + case kFLASH_MemoryIndexPrimaryFlash: + default: + MSCM_OCMDR0_REG = (MSCM_OCMDR0_REG & (~MSCM_SPECULATION_SET_MASK)) | MSCM_SPECULATION_SET(setValue); + /* Memory barriers for good measure. + * All Cache, Branch predictor and TLB maintenance operations before this instruction complete */ + __ISB(); + __DSB(); + break; + } +#endif /* FTFx_DRIVER_IS_FLASH_RESIDENT */ +} +#endif /* FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_MSCM */ + +#if FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_FMC +/*! @brief Performs the prefetch speculation buffer clear to the flash by FMC.*/ +void fmc_flash_prefetch_speculation_clear(ftfx_cache_config_t *config) +{ +#if FTFx_DRIVER_IS_FLASH_RESIDENT + /* Since the value of ARM function pointer is always odd, but the real start address + * of function memory should be even, that's why +1 operation exist. */ + callftfxCommonBitOperation_t callftfxCommonBitOperation = (callftfxCommonBitOperation_t)((uint32_t)config->comBitOperFuncAddr + 1); + callftfxCommonBitOperation((FTFx_REG32_ACCESS_TYPE)&FMC_SPECULATION_INVALIDATE_REG, FMC_SPECULATION_INVALIDATE_MASK, FMC_SPECULATION_INVALIDATE_SHIFT, 1U); +#else /* !FTFx_DRIVER_IS_FLASH_RESIDENT */ + FMC_SPECULATION_INVALIDATE_REG |= FMC_SPECULATION_INVALIDATE_MASK; + /* Memory barriers for good measure. + * All Cache, Branch predictor and TLB maintenance operations before this instruction complete */ + __ISB(); + __DSB(); +#endif /* FTFx_DRIVER_IS_FLASH_RESIDENT */ +} +#endif /* FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_FMC */ + + diff --git a/ext/hal/nxp/mcux/drivers/kinetis/fsl_ftfx_cache.h b/ext/hal/nxp/mcux/drivers/kinetis/fsl_ftfx_cache.h new file mode 100644 index 00000000000..0ed67151cb7 --- /dev/null +++ b/ext/hal/nxp/mcux/drivers/kinetis/fsl_ftfx_cache.h @@ -0,0 +1,116 @@ +/* +* Copyright 2013-2016 Freescale Semiconductor, Inc. +* Copyright 2016-2018 NXP +* All rights reserved. +* +* SPDX-License-Identifier: BSD-3-Clause +* +*/ + +#ifndef _FSL_FTFX_CACHE_H_ +#define _FSL_FTFX_CACHE_H_ + +#include "fsl_ftfx_controller.h" + +/*! + * @addtogroup ftfx_cache_driver + * @{ + */ +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! + * @name FTFx cache version + * @{ + */ +/*! @brief Flexnvm driver version for SDK*/ +#define FSL_FTFX_CACHE_DRIVER_VERSION (MAKE_VERSION(3, 0, 0)) /*!< Version 1.0.0. */ +/*@}*/ + +/*! + * @brief FTFx prefetch speculation status. + */ +typedef struct _flash_prefetch_speculation_status +{ + bool instructionOff; /*!< Instruction speculation.*/ + bool dataOff; /*!< Data speculation.*/ +} ftfx_prefetch_speculation_status_t; + +/*! + * @brief Constants for execute-in-RAM flash function. + */ +enum _ftfx_cache_ram_func_constants +{ + kFTFx_CACHE_RamFuncMaxSizeInWords = 16U, /*!< The maximum size of execute-in-RAM function.*/ +}; + +/*! @brief FTFx cache driver state information. + * + * An instance of this structure is allocated by the user of the flash driver and + * passed into each of the driver APIs. + */ +typedef struct _ftfx_cache_config +{ + uint8_t flashMemoryIndex; /*!< 0 - primary flash; 1 - secondary flash*/ + uint8_t reserved[3]; + uint32_t *comBitOperFuncAddr; /*!< An buffer point to the flash execute-in-RAM function. */ +} ftfx_cache_config_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @brief Initializes the global FTFx cache structure members. + * + * This function checks and initializes the Flash module for the other FTFx cache APIs. + * + * @param config Pointer to the storage for the driver runtime state. + * + * @retval #kStatus_FTFx_Success API was executed successfully. + * @retval #kStatus_FTFx_InvalidArgument An invalid argument is provided. + * @retval #kStatus_FTFx_ExecuteInRamFunctionNotReady Execute-in-RAM function is not available. + */ +status_t FTFx_CACHE_Init(ftfx_cache_config_t *config); + +/*! + * @brief Process the cache/prefetch/speculation to the flash. + * + * @param config A pointer to the storage for the driver runtime state. + * @param process The possible option used to control flash cache/prefetch/speculation + * @retval #kStatus_FTFx_Success API was executed successfully. + * @retval #kStatus_FTFx_InvalidArgument Invalid argument is provided. + * @retval #kStatus_FTFx_ExecuteInRamFunctionNotReady Execute-in-RAM function is not available. + */ +status_t FTFx_CACHE_ClearCachePrefetchSpeculation(ftfx_cache_config_t *config, bool isPreProcess); + +/*! + * @brief Sets the PFlash prefetch speculation to the intended speculation status. + * + * @param speculationStatus The expected protect status to set to the PFlash protection register. Each bit is + * @retval #kStatus_FTFx_Success API was executed successfully. + * @retval #kStatus_FTFx_InvalidSpeculationOption An invalid speculation option argument is provided. + */ +status_t FTFx_CACHE_PflashSetPrefetchSpeculation(ftfx_prefetch_speculation_status_t *speculationStatus); + +/*! + * @brief Gets the PFlash prefetch speculation status. + * + * @param speculationStatus Speculation status returned by the PFlash IP. + * @retval #kStatus_FTFx_Success API was executed successfully. + */ +status_t FTFx_CACHE_PflashGetPrefetchSpeculation(ftfx_prefetch_speculation_status_t *speculationStatus); + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* _FSL_FTFX_CACHE_H_ */ + diff --git a/ext/hal/nxp/mcux/drivers/kinetis/fsl_ftfx_controller.c b/ext/hal/nxp/mcux/drivers/kinetis/fsl_ftfx_controller.c new file mode 100644 index 00000000000..ed0f48566cc --- /dev/null +++ b/ext/hal/nxp/mcux/drivers/kinetis/fsl_ftfx_controller.c @@ -0,0 +1,1376 @@ +/* +* Copyright 2013-2016 Freescale Semiconductor, Inc. +* Copyright 2016-2018 NXP +* All rights reserved. +* +* SPDX-License-Identifier: BSD-3-Clause +* +*/ + +#include "fsl_ftfx_controller.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! + * @name Flash controller command numbers + * @{ + */ +#define FTFx_VERIFY_BLOCK 0x00U /*!< RD1BLK*/ +#define FTFx_VERIFY_SECTION 0x01U /*!< RD1SEC*/ +#define FTFx_PROGRAM_CHECK 0x02U /*!< PGMCHK*/ +#define FTFx_READ_RESOURCE 0x03U /*!< RDRSRC*/ +#define FTFx_PROGRAM_LONGWORD 0x06U /*!< PGM4*/ +#define FTFx_PROGRAM_PHRASE 0x07U /*!< PGM8*/ +#define FTFx_ERASE_BLOCK 0x08U /*!< ERSBLK*/ +#define FTFx_ERASE_SECTOR 0x09U /*!< ERSSCR*/ +#define FTFx_PROGRAM_SECTION 0x0BU /*!< PGMSEC*/ +#define FTFx_GENERATE_CRC 0x0CU /*!< CRCGEN*/ +#define FTFx_VERIFY_ALL_BLOCK 0x40U /*!< RD1ALL*/ +#define FTFx_READ_ONCE 0x41U /*!< RDONCE or RDINDEX*/ +#define FTFx_PROGRAM_ONCE 0x43U /*!< PGMONCE or PGMINDEX*/ +#define FTFx_ERASE_ALL_BLOCK 0x44U /*!< ERSALL*/ +#define FTFx_SECURITY_BY_PASS 0x45U /*!< VFYKEY*/ +#define FTFx_SWAP_CONTROL 0x46U /*!< SWAP*/ +#define FTFx_ERASE_ALL_BLOCK_UNSECURE 0x49U /*!< ERSALLU*/ +#define FTFx_VERIFY_ALL_EXECUTE_ONLY_SEGMENT 0x4AU /*!< RD1XA*/ +#define FTFx_ERASE_ALL_EXECUTE_ONLY_SEGMENT 0x4BU /*!< ERSXA*/ +#define FTFx_PROGRAM_PARTITION 0x80U /*!< PGMPART*/ +#define FTFx_SET_FLEXRAM_FUNCTION 0x81U /*!< SETRAM*/ +/*@}*/ + +/*! + * @brief Constants for execute-in-RAM flash function. + */ +enum _ftfx_ram_func_constants +{ + kFTFx_RamFuncMaxSizeInWords = 16U, /*!< The maximum size of execute-in-RAM function.*/ +}; + +/*! @brief A function pointer used to point to relocated flash_run_command() */ +typedef void (*callFtfxRunCommand_t)(FTFx_REG8_ACCESS_TYPE ftfx_fstat); + +/*! + * @name Enumeration for Flash security register code + * @{ + */ +enum _ftfx_fsec_register_code +{ + kFTFx_FsecRegCode_KEYEN_Enabled = 0x80U, + kFTFx_FsecRegCode_SEC_Unsecured = 0x02U +}; +/*@}*/ + +/*! + * @brief Enumeration for flash config area. + */ +enum _ftfx_pflash_config_area_range +{ + kFTFx_PflashConfigAreaStart = 0x400U, + kFTFx_PflashConfigAreaEnd = 0x40FU +}; + + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/*! @brief Init IFR memory related info */ +static status_t ftfx_init_ifr(ftfx_config_t *config); + +#if FTFx_DRIVER_IS_FLASH_RESIDENT +/*! @brief Copy flash_run_command() to RAM*/ +static void ftfx_copy_run_command_to_ram(uint32_t *ftfxRunCommand); +#endif /* FTFx_DRIVER_IS_FLASH_RESIDENT */ + +/*! @brief Internal function Flash command sequence. Called by driver APIs only*/ +static status_t ftfx_command_sequence(ftfx_config_t *config); + +/*! @brief Validates the range and alignment of the given address range.*/ +static status_t ftfx_check_mem_range(ftfx_config_t *config, + uint32_t startAddress, + uint32_t lengthInBytes, + uint8_t alignmentBaseline); + +/*! @brief Validates the given user key for flash erase APIs.*/ +static status_t ftfx_check_user_key(uint32_t key); + +/*! @brief Reads word from byte address.*/ +static uint32_t ftfx_read_word_from_byte_address(const uint8_t *src); + +/*! @brief Writes word to byte address.*/ +static void ftfx_write_word_to_byte_address(uint8_t *dst, uint32_t word); + +#if defined(FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD) && FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD +/*! @brief Validates the range of the given resource address.*/ +static status_t ftfx_check_resource_range(ftfx_config_t *config, + uint32_t start, + uint32_t lengthInBytes, + uint32_t alignmentBaseline, + ftfx_read_resource_opt_t option); +#endif /* FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD */ + +#if defined(FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD) && FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD +/*! @brief Validates the given flexram function option.*/ +static inline status_t ftfx_check_flexram_function_option(ftfx_flexram_func_opt_t option); +#endif /* FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD */ + +#if defined(FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD) && FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD +/*! @brief Validates the given swap control option.*/ +static status_t ftfx_check_swap_control_option(ftfx_swap_control_opt_t option); +#endif /* FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD */ + +/******************************************************************************* + * Variables + ******************************************************************************/ + +#if FTFx_DRIVER_IS_FLASH_RESIDENT +/*! + * @brief Position independent code of flash_run_command() + * + * Note1: The prototype of C function is shown as below: + * @code + * void flash_run_command(FTFx_REG8_ACCESS_TYPE ftfx_fstat) + * { + * // clear CCIF bit + * *ftfx_fstat = FTFx_FSTAT_CCIF_MASK; + * + * // Check CCIF bit of the flash status register, wait till it is set. + * // IP team indicates that this loop will always complete. + * while (!((*ftfx_fstat) & FTFx_FSTAT_CCIF_MASK)) + * { + * } + * } + * @endcode + * Note2: The binary code is generated by IAR 7.70.1 + */ +static const uint16_t s_ftfxRunCommandFunctionCode[] = { + 0x2180, /* MOVS R1, #128 ; 0x80 */ + 0x7001, /* STRB R1, [R0] */ + /* @4: */ + 0x7802, /* LDRB R2, [R0] */ + 0x420a, /* TST R2, R1 */ + 0xd0fc, /* BEQ.N @4 */ + 0x4770 /* BX LR */ +}; +#if (!FTFx_DRIVER_IS_EXPORTED) +/*! @brief A static buffer used to hold flash_run_command() */ +static uint32_t s_ftfxRunCommand[kFTFx_RamFuncMaxSizeInWords]; +#endif /* (!FTFx_DRIVER_IS_EXPORTED) */ +#endif /* FTFx_DRIVER_IS_FLASH_RESIDENT */ + +/*! @brief Access to FTFx Registers */ +static volatile uint32_t *const kFCCOBx = (volatile uint32_t *)&FTFx_FCCOB3_REG; + +#if FSL_FEATURE_FLASH_HAS_FLEX_NVM +/*! @brief Table of eeprom sizes. */ +static const uint16_t kEepromDensities[16] = { + FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0000, + FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0001, + FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0010, + FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0011, + FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0100, + FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0101, + FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0110, + FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0111, + FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1000, + FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1001, + FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1010, + FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1011, + FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1100, + FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1101, + FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1110, + FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1111 +}; +/*! @brief Table of dflash sizes. */ +static const uint32_t kDflashDensities[16] = { + FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0000, + FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0001, + FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0010, + FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0011, + FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0100, + FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0101, + FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0110, + FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0111, + FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1000, + FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1001, + FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1010, + FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1011, + FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1100, + FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1101, + FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1110, + FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1111 +}; +#endif /* FSL_FEATURE_FLASH_HAS_FLEX_NVM */ + +/******************************************************************************* + * Code + ******************************************************************************/ + +status_t FTFx_API_Init(ftfx_config_t *config) +{ + if (config == NULL) + { + return kStatus_FTFx_InvalidArgument; + } + + config->flexramBlockBase = FSL_FEATURE_FLASH_FLEX_RAM_START_ADDRESS; + config->flexramTotalSize = FSL_FEATURE_FLASH_FLEX_RAM_SIZE; + + /* copy required flash command to RAM */ +#if FTFx_DRIVER_IS_FLASH_RESIDENT + if (NULL == config->runCmdFuncAddr) + { +#if FTFx_DRIVER_IS_EXPORTED + return kStatus_FTFx_ExecuteInRamFunctionNotReady; +#else + config->runCmdFuncAddr = s_ftfxRunCommand; +#endif /* FTFx_DRIVER_IS_EXPORTED */ + } + ftfx_copy_run_command_to_ram(config->runCmdFuncAddr); +#endif /* FTFx_DRIVER_IS_FLASH_RESIDENT */ + + ftfx_init_ifr(config); + + return kStatus_FTFx_Success; +} + +#if FSL_FEATURE_FLASH_HAS_FLEX_NVM +status_t FTFx_API_UpdateFlexnvmPartitionStatus(ftfx_config_t *config) +{ + struct _dflash_ifr_field_config + { + uint32_t reserved0; + uint8_t FlexNVMPartitionCode; + uint8_t EEPROMDataSetSize; + uint16_t reserved1; + } dataIFRReadOut; + uint32_t flexnvmInfoIfrAddr; + status_t returnCode; + + if (config == NULL) + { + return kStatus_FTFx_InvalidArgument; + } + + flexnvmInfoIfrAddr = config->ifrDesc.resRange.dflashIfrStart + config->ifrDesc.resRange.ifrMemSize - sizeof(dataIFRReadOut); + +#if defined(FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD) && FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD + /* Get FlexNVM memory partition info from data flash IFR */ + returnCode = FTFx_CMD_ReadResource(config, flexnvmInfoIfrAddr, (uint8_t *)&dataIFRReadOut, + sizeof(dataIFRReadOut), kFTFx_ResourceOptionFlashIfr); + if (returnCode != kStatus_FTFx_Success) + { + return kStatus_FTFx_PartitionStatusUpdateFailure; + } +#else +#error "Cannot get FlexNVM memory partition info" +#endif + + /* Fill out partitioned EEPROM size */ + dataIFRReadOut.EEPROMDataSetSize &= 0x0FU; + config->eepromTotalSize = kEepromDensities[dataIFRReadOut.EEPROMDataSetSize]; + + /* Fill out partitioned DFlash size */ + dataIFRReadOut.FlexNVMPartitionCode &= 0x0FU; + config->flashDesc.totalSize = kDflashDensities[dataIFRReadOut.FlexNVMPartitionCode]; + + return kStatus_FTFx_Success; +} +#endif /* FSL_FEATURE_FLASH_HAS_FLEX_NVM */ + +status_t FTFx_CMD_Erase(ftfx_config_t *config, + uint32_t start, + uint32_t lengthInBytes, + uint32_t key) +{ + uint32_t sectorSize; + uint32_t endAddress; /* storing end address */ + uint32_t numberOfSectors; /* number of sectors calculated by endAddress */ + status_t returnCode; + + /* Check the supplied address range. */ + returnCode = ftfx_check_mem_range(config, start, lengthInBytes, config->opsConfig.addrAligment.sectorCmd); + if (returnCode) + { + return returnCode; + } + + /* Validate the user key */ + returnCode = ftfx_check_user_key(key); + if (returnCode) + { + return returnCode; + } + + start = config->opsConfig.convertedAddress; + sectorSize = config->flashDesc.sectorSize; + + /* calculating Flash end address */ + endAddress = start + lengthInBytes - 1; + + /* re-calculate the endAddress and align it to the start of the next sector + * which will be used in the comparison below */ + if (endAddress % sectorSize) + { + numberOfSectors = endAddress / sectorSize + 1; + endAddress = numberOfSectors * sectorSize - 1; + } + + /* the start address will increment to the next sector address + * until it reaches the endAdddress */ + while (start <= endAddress) + { + /* preparing passing parameter to erase a flash block */ + kFCCOBx[0] = BYTE2WORD_1_3(FTFx_ERASE_SECTOR, start); + + /* calling flash command sequence function to execute the command */ + returnCode = ftfx_command_sequence(config); + + /* checking the success of command execution */ + if (kStatus_FTFx_Success != returnCode) + { + break; + } + else + { + /* Increment to the next sector */ + start += sectorSize; + } + } + + return (returnCode); +} + +status_t FTFx_CMD_EraseAll(ftfx_config_t *config, uint32_t key) +{ + status_t returnCode; + + if (config == NULL) + { + return kStatus_FTFx_InvalidArgument; + } + + /* preparing passing parameter to erase all flash blocks */ + kFCCOBx[0] = BYTE2WORD_1_3(FTFx_ERASE_ALL_BLOCK, 0xFFFFFFU); + + /* Validate the user key */ + returnCode = ftfx_check_user_key(key); + if (returnCode) + { + return returnCode; + } + + /* calling flash command sequence function to execute the command */ + returnCode = ftfx_command_sequence(config); + +#if FSL_FEATURE_FLASH_HAS_FLEX_NVM + /* Data flash IFR will be erased by erase all command, so we need to + * update FlexNVM memory partition status synchronously */ + if (returnCode == kStatus_FTFx_Success) + { + returnCode = FTFx_API_UpdateFlexnvmPartitionStatus(config); + } +#endif + + return returnCode; +} + +#if defined(FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_UNSECURE_CMD) && FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_UNSECURE_CMD +status_t FTFx_CMD_EraseAllUnsecure(ftfx_config_t *config, uint32_t key) +{ + status_t returnCode; + + if (config == NULL) + { + return kStatus_FTFx_InvalidArgument; + } + + /* Prepare passing parameter to erase all flash blocks (unsecure). */ + kFCCOBx[0] = BYTE2WORD_1_3(FTFx_ERASE_ALL_BLOCK_UNSECURE, 0xFFFFFFU); + + /* Validate the user key */ + returnCode = ftfx_check_user_key(key); + if (returnCode) + { + return returnCode; + } + + /* calling flash command sequence function to execute the command */ + returnCode = ftfx_command_sequence(config); + +#if FSL_FEATURE_FLASH_HAS_FLEX_NVM + /* Data flash IFR will be erased by erase all unsecure command, so we need to + * update FlexNVM memory partition status synchronously */ + if (returnCode == kStatus_FTFx_Success) + { + returnCode = FTFx_API_UpdateFlexnvmPartitionStatus(config); + } +#endif + + return returnCode; +} +#endif /* FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_UNSECURE_CMD */ + +status_t FTFx_CMD_EraseAllExecuteOnlySegments(ftfx_config_t *config, uint32_t key) +{ + status_t returnCode; + + if (config == NULL) + { + return kStatus_FTFx_InvalidArgument; + } + + /* preparing passing parameter to erase all execute-only segments + * 1st element for the FCCOB register */ + kFCCOBx[0] = BYTE2WORD_1_3(FTFx_ERASE_ALL_EXECUTE_ONLY_SEGMENT, 0xFFFFFFU); + + /* Validate the user key */ + returnCode = ftfx_check_user_key(key); + if (returnCode) + { + return returnCode; + } + + /* calling flash command sequence function to execute the command */ + returnCode = ftfx_command_sequence(config); + + return returnCode; +} + +status_t FTFx_CMD_Program(ftfx_config_t *config, + uint32_t start, + uint8_t *src, + uint32_t lengthInBytes) +{ + status_t returnCode; + uint8_t blockWriteUnitSize = config->opsConfig.addrAligment.blockWriteUnitSize; + + if (src == NULL) + { + return kStatus_FTFx_InvalidArgument; + } + + /* Check the supplied address range. */ + returnCode = ftfx_check_mem_range(config, start, lengthInBytes, blockWriteUnitSize); + if (returnCode) + { + return returnCode; + } + + start = config->opsConfig.convertedAddress; + + while (lengthInBytes > 0) + { + /* preparing passing parameter to program the flash block */ + kFCCOBx[1] = ftfx_read_word_from_byte_address((const uint8_t*)src); + src += 4; + + if (4 == blockWriteUnitSize) + { + kFCCOBx[0] = BYTE2WORD_1_3(FTFx_PROGRAM_LONGWORD, start); + } + else if (8 == blockWriteUnitSize) + { + kFCCOBx[2] = ftfx_read_word_from_byte_address((const uint8_t*)src); + src += 4; + kFCCOBx[0] = BYTE2WORD_1_3(FTFx_PROGRAM_PHRASE, start); + } + else + { + } + + /* calling flash command sequence function to execute the command */ + returnCode = ftfx_command_sequence(config); + + /* checking for the success of command execution */ + if (kStatus_FTFx_Success != returnCode) + { + break; + } + else + { + /* update start address for next iteration */ + start += blockWriteUnitSize; + + /* update lengthInBytes for next iteration */ + lengthInBytes -= blockWriteUnitSize; + } + } + + return (returnCode); +} + +status_t FTFx_CMD_ProgramOnce(ftfx_config_t *config, uint32_t index, uint8_t *src, uint32_t lengthInBytes) +{ + status_t returnCode; + + if ((config == NULL) || (src == NULL)) + { + return kStatus_FTFx_InvalidArgument; + } + + /* pass parameters to FTFx */ + kFCCOBx[0] = BYTE2WORD_1_1_2(FTFx_PROGRAM_ONCE, index, 0xFFFFU); + + kFCCOBx[1] = ftfx_read_word_from_byte_address((const uint8_t*)src); + + /* Note: Have to separate the first index from the rest if it equals 0 + * to avoid a pointless comparison of unsigned int to 0 compiler warning */ + if (config->ifrDesc.feature.has8ByteIdxSupport) + { + if (config->ifrDesc.feature.has4ByteIdxSupport) + { + if (((index == config->ifrDesc.idxInfo.mix8byteIdxStart) || + ((index >= config->ifrDesc.idxInfo.mix8byteIdxStart + 1) && (index <= config->ifrDesc.idxInfo.mix8byteIdxStart))) && + (lengthInBytes == 8)) + { + kFCCOBx[2] = ftfx_read_word_from_byte_address((const uint8_t*)src + 4); + } + } + else + { + kFCCOBx[2] = ftfx_read_word_from_byte_address((const uint8_t*)src + 4); + } + } + + /* calling flash command sequence function to execute the command */ + returnCode = ftfx_command_sequence(config); + + return returnCode; +} + +#if defined(FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD) && FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD +status_t FTFx_CMD_ProgramSection(ftfx_config_t *config, + uint32_t start, + uint8_t *src, + uint32_t lengthInBytes) +{ + status_t returnCode; + uint32_t sectorSize; + uint8_t aligmentInBytes = config->opsConfig.addrAligment.sectionCmd; +#if defined(FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD) && FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD + bool needSwitchFlexRamMode = false; +#endif /* FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD */ + + if (src == NULL) + { + return kStatus_FTFx_InvalidArgument; + } + + /* Check the supplied address range. */ + returnCode = ftfx_check_mem_range(config, start, lengthInBytes, aligmentInBytes); + if (returnCode) + { + return returnCode; + } + + start = config->opsConfig.convertedAddress; + sectorSize = config->flashDesc.sectorSize; + +#if defined(FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD) && FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD + /* Switch function of FlexRAM if needed */ + if (!(FTFx->FCNFG & FTFx_FCNFG_RAMRDY_MASK)) + { + needSwitchFlexRamMode = true; + + returnCode = FTFx_CMD_SetFlexramFunction(config, kFTFx_FlexramFuncOptAvailableAsRam); + if (returnCode != kStatus_FTFx_Success) + { + return kStatus_FTFx_SetFlexramAsRamError; + } + } +#endif /* FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD */ + + while (lengthInBytes > 0) + { + /* Make sure the write operation doesn't span two sectors */ + uint32_t endAddressOfCurrentSector = ALIGN_UP(start, sectorSize); + uint32_t lengthTobeProgrammedOfCurrentSector; + uint32_t currentOffset = 0; + + if (endAddressOfCurrentSector == start) + { + endAddressOfCurrentSector += sectorSize; + } + + if (lengthInBytes + start > endAddressOfCurrentSector) + { + lengthTobeProgrammedOfCurrentSector = endAddressOfCurrentSector - start; + } + else + { + lengthTobeProgrammedOfCurrentSector = lengthInBytes; + } + + /* Program Current Sector */ + while (lengthTobeProgrammedOfCurrentSector > 0) + { + /* Make sure the program size doesn't exceeds Acceleration RAM size */ + uint32_t programSizeOfCurrentPass; + uint32_t numberOfPhases; + + if (lengthTobeProgrammedOfCurrentSector > config->flexramTotalSize) + { + programSizeOfCurrentPass = config->flexramTotalSize; + } + else + { + programSizeOfCurrentPass = lengthTobeProgrammedOfCurrentSector; + } + + /* Copy data to FlexRAM */ + memcpy((void *)config->flexramBlockBase, src + currentOffset, programSizeOfCurrentPass); + /* Set start address of the data to be programmed */ + kFCCOBx[0] = BYTE2WORD_1_3(FTFx_PROGRAM_SECTION, start + currentOffset); + /* Set program size in terms of FEATURE_FLASH_SECTION_CMD_ADDRESS_ALIGMENT */ + numberOfPhases = programSizeOfCurrentPass / aligmentInBytes; + + kFCCOBx[1] = BYTE2WORD_2_2(numberOfPhases, 0xFFFFU); + + /* Peform command sequence */ + returnCode = ftfx_command_sequence(config); + + if (returnCode != kStatus_FTFx_Success) + { + return returnCode; + } + + lengthTobeProgrammedOfCurrentSector -= programSizeOfCurrentPass; + currentOffset += programSizeOfCurrentPass; + } + + src += currentOffset; + start += currentOffset; + lengthInBytes -= currentOffset; + } + +#if defined(FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD) && FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD + /* Restore function of FlexRAM if needed. */ + if (needSwitchFlexRamMode) + { + returnCode = FTFx_CMD_SetFlexramFunction(config, kFTFx_FlexramFuncOptAvailableForEeprom); + if (returnCode != kStatus_FTFx_Success) + { + return kStatus_FTFx_RecoverFlexramAsEepromError; + } + } +#endif /* FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD */ + + return returnCode; +} +#endif /* FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD */ + +#if defined(FSL_FEATURE_FLASH_HAS_PROGRAM_PARTITION_CMD) && FSL_FEATURE_FLASH_HAS_PROGRAM_PARTITION_CMD +status_t FTFx_CMD_ProgramPartition(ftfx_config_t *config, + ftfx_partition_flexram_load_opt_t option, + uint32_t eepromDataSizeCode, + uint32_t flexnvmPartitionCode) +{ + status_t returnCode; + + if (config == NULL) + { + return kStatus_FTFx_InvalidArgument; + } + + /* eepromDataSizeCode[7:6], flexnvmPartitionCode[7:4] should be all 1'b0 + * or it will cause access error. */ + /* eepromDataSizeCode &= 0x3FU; */ + /* flexnvmPartitionCode &= 0x0FU; */ + + /* preparing passing parameter to program the flash block */ + kFCCOBx[0] = BYTE2WORD_1_2_1(FTFx_PROGRAM_PARTITION, 0xFFFFU, option); + kFCCOBx[1] = BYTE2WORD_1_1_2(eepromDataSizeCode, flexnvmPartitionCode, 0xFFFFU); + + /* calling flash command sequence function to execute the command */ + returnCode = ftfx_command_sequence(config); + +#if FSL_FEATURE_FLASH_HAS_FLEX_NVM + /* Data flash IFR will be updated by program partition command during reset sequence, + * so we just set reserved values for partitioned FlexNVM size here */ + config->eepromTotalSize = 0xFFFFU; + config->flashDesc.totalSize = 0xFFFFFFFFU; +#endif + + return (returnCode); +} +#endif /* FSL_FEATURE_FLASH_HAS_PROGRAM_PARTITION_CMD */ + +status_t FTFx_CMD_ReadOnce(ftfx_config_t *config, uint32_t index, uint8_t *dst, uint32_t lengthInBytes) +{ + status_t returnCode; + + if ((config == NULL) || (dst == NULL)) + { + return kStatus_FTFx_InvalidArgument; + } + + /* pass parameters to FTFx */ + kFCCOBx[0] = BYTE2WORD_1_1_2(FTFx_READ_ONCE, index, 0xFFFFU); + + /* calling flash command sequence function to execute the command */ + returnCode = ftfx_command_sequence(config); + + if (kStatus_FTFx_Success == returnCode) + { + ftfx_write_word_to_byte_address(dst, kFCCOBx[1]); + /* Note: Have to separate the first index from the rest if it equals 0 + * to avoid a pointless comparison of unsigned int to 0 compiler warning */ + if (config->ifrDesc.feature.has8ByteIdxSupport) + { + if (config->ifrDesc.feature.has4ByteIdxSupport) + { + if (((index == config->ifrDesc.idxInfo.mix8byteIdxStart) || + ((index >= config->ifrDesc.idxInfo.mix8byteIdxStart + 1) && (index <= config->ifrDesc.idxInfo.mix8byteIdxStart))) && + (lengthInBytes == 8)) + { + ftfx_write_word_to_byte_address(dst + 4, kFCCOBx[2]); + } + } + else + { + ftfx_write_word_to_byte_address(dst + 4, kFCCOBx[2]); + } + } + } + + return returnCode; +} + +#if defined(FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD) && FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD +status_t FTFx_CMD_ReadResource(ftfx_config_t *config, + uint32_t start, + uint8_t *dst, + uint32_t lengthInBytes, + ftfx_read_resource_opt_t option) +{ + status_t returnCode; + + if ((config == NULL) || (dst == NULL)) + { + return kStatus_FTFx_InvalidArgument; + } + + uint8_t aligmentInBytes = config->opsConfig.addrAligment.resourceCmd; + + /* Check the supplied address range. */ + returnCode = ftfx_check_resource_range(config, start, lengthInBytes, aligmentInBytes, option); + if (returnCode != kStatus_FTFx_Success) + { + return returnCode; + } + + while (lengthInBytes > 0) + { + /* preparing passing parameter */ + kFCCOBx[0] = BYTE2WORD_1_3(FTFx_READ_RESOURCE, start); + if (aligmentInBytes == 4) + { + kFCCOBx[2] = BYTE2WORD_1_3(option, 0xFFFFFFU); + } + else if (aligmentInBytes == 8) + { + kFCCOBx[1] = BYTE2WORD_1_3(option, 0xFFFFFFU); + } + else + { + } + + /* calling flash command sequence function to execute the command */ + returnCode = ftfx_command_sequence(config); + + if (kStatus_FTFx_Success != returnCode) + { + break; + } + + /* fetch data */ + ftfx_write_word_to_byte_address(dst, kFCCOBx[1]); + dst += 4; + if (aligmentInBytes == 8) + { + ftfx_write_word_to_byte_address(dst, kFCCOBx[2]); + dst += 4; + } + /* update start address for next iteration */ + start += aligmentInBytes; + /* update lengthInBytes for next iteration */ + lengthInBytes -= aligmentInBytes; + } + + return (returnCode); +} +#endif /* FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD */ + +status_t FTFx_CMD_VerifyErase(ftfx_config_t *config, + uint32_t start, + uint32_t lengthInBytes, + ftfx_margin_value_t margin) +{ + /* Check arguments. */ + uint32_t blockSize; + uint32_t nextBlockStartAddress; + uint32_t remainingBytes; + uint8_t aligmentInBytes = config->opsConfig.addrAligment.sectionCmd; + status_t returnCode; + + returnCode = ftfx_check_mem_range(config, start, lengthInBytes, aligmentInBytes); + if (returnCode) + { + return returnCode; + } + + start = config->opsConfig.convertedAddress; + blockSize = config->flashDesc.totalSize / config->flashDesc.blockCount; + + nextBlockStartAddress = ALIGN_UP(start, blockSize); + if (nextBlockStartAddress == start) + { + nextBlockStartAddress += blockSize; + } + + remainingBytes = lengthInBytes; + + while (remainingBytes) + { + uint32_t numberOfPhrases; + uint32_t verifyLength = nextBlockStartAddress - start; + if (verifyLength > remainingBytes) + { + verifyLength = remainingBytes; + } + + numberOfPhrases = verifyLength / aligmentInBytes; + + /* Fill in verify section command parameters. */ + kFCCOBx[0] = BYTE2WORD_1_3(FTFx_VERIFY_SECTION, start); + kFCCOBx[1] = BYTE2WORD_2_1_1(numberOfPhrases, margin, 0xFFU); + + /* calling flash command sequence function to execute the command */ + returnCode = ftfx_command_sequence(config); + if (returnCode) + { + return returnCode; + } + + remainingBytes -= verifyLength; + start += verifyLength; + nextBlockStartAddress += blockSize; + } + + return kStatus_FTFx_Success; +} + +status_t FTFx_CMD_VerifyEraseAll(ftfx_config_t *config, ftfx_margin_value_t margin) +{ + if (config == NULL) + { + return kStatus_FTFx_InvalidArgument; + } + + /* preparing passing parameter to verify all block command */ + kFCCOBx[0] = BYTE2WORD_1_1_2(FTFx_VERIFY_ALL_BLOCK, margin, 0xFFFFU); + + /* calling flash command sequence function to execute the command */ + return ftfx_command_sequence(config); +} + +status_t FTFx_CMD_VerifyEraseAllExecuteOnlySegments(ftfx_config_t *config, ftfx_margin_value_t margin) +{ + if (config == NULL) + { + return kStatus_FTFx_InvalidArgument; + } + + /* preparing passing parameter to verify erase all execute-only segments command */ + kFCCOBx[0] = BYTE2WORD_1_1_2(FTFx_VERIFY_ALL_EXECUTE_ONLY_SEGMENT, margin, 0xFFFFU); + + /* calling flash command sequence function to execute the command */ + return ftfx_command_sequence(config); +} + +status_t FTFx_CMD_VerifyProgram(ftfx_config_t *config, + uint32_t start, + uint32_t lengthInBytes, + const uint8_t *expectedData, + ftfx_margin_value_t margin, + uint32_t *failedAddress, + uint32_t *failedData) +{ + status_t returnCode; + uint8_t aligmentInBytes = config->opsConfig.addrAligment.checkCmd; + if (expectedData == NULL) + { + return kStatus_FTFx_InvalidArgument; + } + + returnCode = ftfx_check_mem_range(config, start, lengthInBytes, aligmentInBytes); + if (returnCode) + { + return returnCode; + } + + start = config->opsConfig.convertedAddress; + + while (lengthInBytes) + { + /* preparing passing parameter to program check the flash block */ + kFCCOBx[0] = BYTE2WORD_1_3(FTFx_PROGRAM_CHECK, start); + kFCCOBx[1] = BYTE2WORD_1_3(margin, 0xFFFFFFU); + kFCCOBx[2] = ftfx_read_word_from_byte_address((const uint8_t*)expectedData); + + /* calling flash command sequence function to execute the command */ + returnCode = ftfx_command_sequence(config); + + /* checking for the success of command execution */ + if (kStatus_FTFx_Success != returnCode) + { + if (failedAddress) + { + *failedAddress = start; + } + if (failedData) + { + *failedData = 0; + } + break; + } + + lengthInBytes -= aligmentInBytes; + expectedData += aligmentInBytes; + start += aligmentInBytes; + } + + return (returnCode); +} + +status_t FTFx_CMD_SecurityBypass(ftfx_config_t *config, const uint8_t *backdoorKey) +{ + uint8_t registerValue; /* registerValue */ + status_t returnCode; /* return code variable */ + + if ((config == NULL) || (backdoorKey == NULL)) + { + return kStatus_FTFx_InvalidArgument; + } + + /* set the default return code as kStatus_Success */ + returnCode = kStatus_FTFx_Success; + + /* Get flash security register value */ + registerValue = FTFx->FSEC; + + /* Check to see if flash is in secure state (any state other than 0x2) + * If not, then skip this since flash is not secure */ + if (0x02 != (registerValue & 0x03)) + { + /* preparing passing parameter to erase a flash block */ + kFCCOBx[0] = BYTE2WORD_1_3(FTFx_SECURITY_BY_PASS, 0xFFFFFFU); + kFCCOBx[1] = BYTE2WORD_1_1_1_1(backdoorKey[0], backdoorKey[1], backdoorKey[2], backdoorKey[3]); + kFCCOBx[2] = BYTE2WORD_1_1_1_1(backdoorKey[4], backdoorKey[5], backdoorKey[6], backdoorKey[7]); + + /* calling flash command sequence function to execute the command */ + returnCode = ftfx_command_sequence(config); + } + + return (returnCode); +} + +status_t FTFx_REG_GetSecurityState(ftfx_config_t *config, ftfx_security_state_t *state) +{ + /* store data read from flash register */ + uint8_t registerValue; + + if ((config == NULL) || (state == NULL)) + { + return kStatus_FTFx_InvalidArgument; + } + + /* Get flash security register value */ + registerValue = FTFx->FSEC; + + /* check the status of the flash security bits in the security register */ + if (kFTFx_FsecRegCode_SEC_Unsecured == (registerValue & FTFx_FSEC_SEC_MASK)) + { + /* Flash in unsecured state */ + *state = kFTFx_SecurityStateNotSecure; + } + else + { + /* Flash in secured state + * check for backdoor key security enable bit */ + if (kFTFx_FsecRegCode_KEYEN_Enabled == (registerValue & FTFx_FSEC_KEYEN_MASK)) + { + /* Backdoor key security enabled */ + *state = kFTFx_SecurityStateBackdoorEnabled; + } + else + { + /* Backdoor key security disabled */ + *state = kFTFx_SecurityStateBackdoorDisabled; + } + } + + return (kStatus_FTFx_Success); +} + +#if defined(FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD) && FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD + status_t FTFx_CMD_SetFlexramFunction(ftfx_config_t *config, ftfx_flexram_func_opt_t option) + { + status_t status; + + if (config == NULL) + { + return kStatus_FTFx_InvalidArgument; + } + + status = ftfx_check_flexram_function_option(option); + if (status != kStatus_FTFx_Success) + { + return status; + } + + /* preparing passing parameter to verify all block command */ + kFCCOBx[0] = BYTE2WORD_1_1_2(FTFx_SET_FLEXRAM_FUNCTION, option, 0xFFFFU); + + /* calling flash command sequence function to execute the command */ + return ftfx_command_sequence(config); + } +#endif /* FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD */ + +#if defined(FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD) && FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD +status_t FTFx_CMD_SwapControl(ftfx_config_t *config, + uint32_t address, + ftfx_swap_control_opt_t option, + ftfx_swap_state_config_t *returnInfo) +{ + status_t returnCode; + + if ((config == NULL) || (returnInfo == NULL)) + { + return kStatus_FTFx_InvalidArgument; + } + + if (address & (FSL_FEATURE_FLASH_PFLASH_SWAP_CONTROL_CMD_ADDRESS_ALIGMENT - 1)) + { + return kStatus_FTFx_AlignmentError; + } + + /* Make sure address provided is in the lower half of Program flash but not in the Flash Configuration Field */ + if ((address >= (config->flashDesc.totalSize / 2)) || + ((address >= kFTFx_PflashConfigAreaStart) && (address <= kFTFx_PflashConfigAreaEnd))) + { + return kStatus_FTFx_SwapIndicatorAddressError; + } + + /* Check the option. */ + returnCode = ftfx_check_swap_control_option(option); + if (returnCode) + { + return returnCode; + } + + kFCCOBx[0] = BYTE2WORD_1_3(FTFx_SWAP_CONTROL, address); + kFCCOBx[1] = BYTE2WORD_1_3(option, 0xFFFFFFU); + + returnCode = ftfx_command_sequence(config); + + returnInfo->flashSwapState = (ftfx_swap_state_t)FTFx_FCCOB5_REG; + returnInfo->currentSwapBlockStatus = (ftfx_swap_block_status_t)FTFx_FCCOB6_REG; + returnInfo->nextSwapBlockStatus = (ftfx_swap_block_status_t)FTFx_FCCOB7_REG; + + return returnCode; +} +#endif /* FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD */ + +static status_t ftfx_init_ifr(ftfx_config_t *config) +{ + if (config == NULL) + { + return kStatus_FTFx_InvalidArgument; + } + +#if FSL_FEATURE_FLASH_IS_FTFA + /* FTFA parts(eg. K80, KL80, L5K) support both 4-bytes and 8-bytes unit size */ + config->ifrDesc.feature.has4ByteIdxSupport = 1; + config->ifrDesc.feature.has8ByteIdxSupport = 1; + config->ifrDesc.idxInfo.mix8byteIdxStart = 0x10U; + config->ifrDesc.idxInfo.mix8byteIdxEnd = 0x13U; +#elif FSL_FEATURE_FLASH_IS_FTFE + /* FTFE parts(eg. K65, KE18) only support 8-bytes unit size */ + config->ifrDesc.feature.has4ByteIdxSupport = 0; + config->ifrDesc.feature.has8ByteIdxSupport = 1; +#elif FSL_FEATURE_FLASH_IS_FTFL + /* FTFL parts(eg. K20) only support 4-bytes unit size */ + config->ifrDesc.feature.has4ByteIdxSupport = 1; + config->ifrDesc.feature.has8ByteIdxSupport = 0; +#endif + + config->ifrDesc.resRange.pflashIfrStart = 0x0000U; + config->ifrDesc.resRange.versionIdSize = 0x08U; +#if FSL_FEATURE_FLASH_IS_FTFE + config->ifrDesc.resRange.versionIdStart = 0x08U; + config->ifrDesc.resRange.ifrMemSize = 0x0400U; +#else /* FSL_FEATURE_FLASH_IS_FTFL == 1 or FSL_FEATURE_FLASH_IS_FTFA = =1 */ + config->ifrDesc.resRange.versionIdStart = 0x00U; + config->ifrDesc.resRange.ifrMemSize = 0x0100U; +#endif + +#if FSL_FEATURE_FLASH_HAS_FLEX_NVM + config->ifrDesc.resRange.dflashIfrStart = 0x800000U; +#endif + +#if FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD +#if FSL_FEATURE_FLASH_IS_FTFE + config->ifrDesc.resRange.pflashSwapIfrStart = 0x40000U; +#else /* FSL_FEATURE_FLASH_IS_FTFL == 1 or FSL_FEATURE_FLASH_IS_FTFA == 1 */ + config->ifrDesc.resRange.pflashSwapIfrStart = config->flashDesc.totalSize / 4; +#endif +#endif /* FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD */ + + return kStatus_FTFx_Success; +} + +#if FTFx_DRIVER_IS_FLASH_RESIDENT +/*! + * @brief Copy PIC of flash_run_command() to RAM + */ +static void ftfx_copy_run_command_to_ram(uint32_t *ftfxRunCommand) +{ + assert(sizeof(s_ftfxRunCommandFunctionCode) <= (kFTFx_RamFuncMaxSizeInWords * 4)); + + /* Since the value of ARM function pointer is always odd, but the real start address + * of function memory should be even, that's why +1 operation exist. */ + memcpy((uint8_t *)ftfxRunCommand, (const uint8_t *)s_ftfxRunCommandFunctionCode, sizeof(s_ftfxRunCommandFunctionCode)); +} +#endif /* FTFx_DRIVER_IS_FLASH_RESIDENT */ + +/*! + * @brief FTFx Command Sequence + * + * This function is used to perform the command write sequence to the flash. + * + * @param driver Pointer to storage for the driver runtime state. + * @return An error code or kStatus_FTFx_Success + */ +static status_t ftfx_command_sequence(ftfx_config_t *config) +{ + uint8_t registerValue; + +#if FTFx_DRIVER_IS_FLASH_RESIDENT + /* clear RDCOLERR & ACCERR & FPVIOL flag in flash status register */ + FTFx->FSTAT = FTFx_FSTAT_RDCOLERR_MASK | FTFx_FSTAT_ACCERR_MASK | FTFx_FSTAT_FPVIOL_MASK; + + /* Since the value of ARM function pointer is always odd, but the real start address + * of function memory should be even, that's why +1 operation exist. */ + callFtfxRunCommand_t callFtfxRunCommand = (callFtfxRunCommand_t)((uint32_t)config->runCmdFuncAddr + 1); + + /* We pass the ftfx_fstat address as a parameter to flash_run_comamnd() instead of using + * pre-processed MICRO sentences or operating global variable in flash_run_comamnd() + * to make sure that flash_run_command() will be compiled into position-independent code (PIC). */ + callFtfxRunCommand((FTFx_REG8_ACCESS_TYPE)(&FTFx->FSTAT)); +#else + /* clear RDCOLERR & ACCERR & FPVIOL flag in flash status register */ + FTFx->FSTAT = FTFx_FSTAT_RDCOLERR_MASK | FTFx_FSTAT_ACCERR_MASK | FTFx_FSTAT_FPVIOL_MASK; + + /* clear CCIF bit */ + FTFx->FSTAT = FTFx_FSTAT_CCIF_MASK; + + /* Check CCIF bit of the flash status register, wait till it is set. + * IP team indicates that this loop will always complete. */ + while (!(FTFx->FSTAT & FTFx_FSTAT_CCIF_MASK)) + { + } +#endif /* FTFx_DRIVER_IS_FLASH_RESIDENT */ + + /* Check error bits */ + /* Get flash status register value */ + registerValue = FTFx->FSTAT; + + /* checking access error */ + if (registerValue & FTFx_FSTAT_ACCERR_MASK) + { + return kStatus_FTFx_AccessError; + } + /* checking protection error */ + else if (registerValue & FTFx_FSTAT_FPVIOL_MASK) + { + return kStatus_FTFx_ProtectionViolation; + } + /* checking MGSTAT0 non-correctable error */ + else if (registerValue & FTFx_FSTAT_MGSTAT0_MASK) + { + return kStatus_FTFx_CommandFailure; + } + else + { + return kStatus_FTFx_Success; + } +} + +/*! @brief Validates the range and alignment of the given address range.*/ +static status_t ftfx_check_mem_range(ftfx_config_t *config, + uint32_t startAddress, + uint32_t lengthInBytes, + uint8_t alignmentBaseline) +{ + if (config == NULL) + { + return kStatus_FTFx_InvalidArgument; + } + + /* Verify the start and length are alignmentBaseline aligned. */ + if ((startAddress & (alignmentBaseline - 1)) || (lengthInBytes & (alignmentBaseline - 1))) + { + return kStatus_FTFx_AlignmentError; + } + + /* check for valid range of the target addresses */ + if ((startAddress >= config->flashDesc.blockBase) && + ((startAddress + lengthInBytes) <= (config->flashDesc.blockBase + config->flashDesc.totalSize))) + { + return kStatus_FTFx_Success; + } + + return kStatus_FTFx_AddressError; +} + +/*! @brief Validates the given user key for flash erase APIs.*/ +static status_t ftfx_check_user_key(uint32_t key) +{ + /* Validate the user key */ + if (key != kFTFx_ApiEraseKey) + { + return kStatus_FTFx_EraseKeyError; + } + + return kStatus_FTFx_Success; +} + +/*! @brief Reads word from byte address.*/ +static uint32_t ftfx_read_word_from_byte_address(const uint8_t *src) +{ + uint32_t word = 0; + + if (!((uint32_t)src % 4)) + { + word = *(const uint32_t *)src; + } + else + { + for (uint32_t i = 0; i < 4; i++) + { + word |= (uint32_t)(*src) << (i * 8); + src++; + } + } + + return word; +} + +/*! @brief Writes word to byte address.*/ +static void ftfx_write_word_to_byte_address(uint8_t *dst, uint32_t word) +{ + if (!((uint32_t)dst % 4)) + { + *(uint32_t *)dst = word; + } + else + { + for (uint32_t i = 0; i < 4; i++) + { + *dst = (uint8_t)((word >> (i * 8)) & 0xFFU); + dst++; + } + } +} + +#if defined(FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD) && FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD +/*! @brief Validates the range of the given resource address.*/ +static status_t ftfx_check_resource_range(ftfx_config_t *config, + uint32_t start, + uint32_t lengthInBytes, + uint32_t alignmentBaseline, + ftfx_read_resource_opt_t option) +{ + status_t status; + uint32_t maxReadbleAddress; + + if ((start & (alignmentBaseline - 1)) || (lengthInBytes & (alignmentBaseline - 1))) + { + return kStatus_FTFx_AlignmentError; + } + + status = kStatus_FTFx_Success; + + maxReadbleAddress = start + lengthInBytes - 1; + if (option == kFTFx_ResourceOptionVersionId) + { + if ((start != config->ifrDesc.resRange.versionIdStart) || + (lengthInBytes != config->ifrDesc.resRange.versionIdSize)) + { + status = kStatus_FTFx_InvalidArgument; + } + } + else if (option == kFTFx_ResourceOptionFlashIfr) + { + if ((start >= config->ifrDesc.resRange.pflashIfrStart) && + (maxReadbleAddress < (config->ifrDesc.resRange.pflashIfrStart + config->ifrDesc.resRange.ifrMemSize))) + { + } +#if FSL_FEATURE_FLASH_HAS_FLEX_NVM + else if ((start >= config->ifrDesc.resRange.dflashIfrStart) && + (maxReadbleAddress < (config->ifrDesc.resRange.dflashIfrStart + config->ifrDesc.resRange.ifrMemSize))) + { + } +#endif +#if FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD + else if ((start >= config->ifrDesc.resRange.pflashSwapIfrStart) && + (maxReadbleAddress < (config->ifrDesc.resRange.pflashSwapIfrStart + config->ifrDesc.resRange.ifrMemSize))) + { + } +#endif + else + { + status = kStatus_FTFx_InvalidArgument; + } + } + else + { + status = kStatus_FTFx_InvalidArgument; + } + + return status; +} +#endif /* FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD */ + +#if defined(FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD) && FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD +/*! @brief Validates the given flexram function option.*/ +static inline status_t ftfx_check_flexram_function_option(ftfx_flexram_func_opt_t option) +{ + if ((option != kFTFx_FlexramFuncOptAvailableAsRam) && + (option != kFTFx_FlexramFuncOptAvailableForEeprom)) + { + return kStatus_FTFx_InvalidArgument; + } + + return kStatus_FTFx_Success; +} +#endif /* FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD */ + +#if defined(FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD) && FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD +/*! @brief Validates the given swap control option.*/ +static status_t ftfx_check_swap_control_option(ftfx_swap_control_opt_t option) +{ + if ((option == kFTFx_SwapControlOptionIntializeSystem) || (option == kFTFx_SwapControlOptionSetInUpdateState) || + (option == kFTFx_SwapControlOptionSetInCompleteState) || (option == kFTFx_SwapControlOptionReportStatus) || + (option == kFTFx_SwapControlOptionDisableSystem)) + { + return kStatus_FTFx_Success; + } + + return kStatus_FTFx_InvalidArgument; +} +#endif /* FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD */ diff --git a/ext/hal/nxp/mcux/drivers/kinetis/fsl_ftfx_controller.h b/ext/hal/nxp/mcux/drivers/kinetis/fsl_ftfx_controller.h new file mode 100644 index 00000000000..96ebeb3464d --- /dev/null +++ b/ext/hal/nxp/mcux/drivers/kinetis/fsl_ftfx_controller.h @@ -0,0 +1,812 @@ +/* +* Copyright 2013-2016 Freescale Semiconductor, Inc. +* Copyright 2016-2018 NXP +* All rights reserved. +* +* SPDX-License-Identifier: BSD-3-Clause +* +*/ + +#ifndef _FSL_FTFX_CONTROLLER_H_ +#define _FSL_FTFX_CONTROLLER_H_ + +#include "fsl_ftfx_features.h" +#include "fsl_ftfx_utilities.h" + +/*! + * @addtogroup ftfx_controller + * @{ + */ +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.flash" +#endif + +/*! + * @name FTFx status + * @{ + */ +/*! @brief FTFx driver status group. */ +#if defined(kStatusGroup_FlashDriver) +#define kStatusGroupGeneric kStatusGroup_Generic +#define kStatusGroupFtfxDriver kStatusGroup_FlashDriver +#elif defined(kStatusGroup_FLASH) +#define kStatusGroupGeneric kStatusGroup_Generic +#define kStatusGroupFtfxDriver kStatusGroup_FLASH +#else +#define kStatusGroupGeneric 0 +#define kStatusGroupFtfxDriver 1 +#endif + +/*! + * @brief FTFx driver status codes. + */ +enum _ftfx_status +{ + kStatus_FTFx_Success = MAKE_STATUS(kStatusGroupGeneric, 0), /*!< API is executed successfully*/ + kStatus_FTFx_InvalidArgument = MAKE_STATUS(kStatusGroupGeneric, 4), /*!< Invalid argument*/ + kStatus_FTFx_SizeError = MAKE_STATUS(kStatusGroupFtfxDriver, 0), /*!< Error size*/ + kStatus_FTFx_AlignmentError = + MAKE_STATUS(kStatusGroupFtfxDriver, 1), /*!< Parameter is not aligned with the specified baseline*/ + kStatus_FTFx_AddressError = MAKE_STATUS(kStatusGroupFtfxDriver, 2), /*!< Address is out of range */ + kStatus_FTFx_AccessError = + MAKE_STATUS(kStatusGroupFtfxDriver, 3), /*!< Invalid instruction codes and out-of bound addresses */ + kStatus_FTFx_ProtectionViolation = MAKE_STATUS( + kStatusGroupFtfxDriver, 4), /*!< The program/erase operation is requested to execute on protected areas */ + kStatus_FTFx_CommandFailure = + MAKE_STATUS(kStatusGroupFtfxDriver, 5), /*!< Run-time error during command execution. */ + kStatus_FTFx_UnknownProperty = MAKE_STATUS(kStatusGroupFtfxDriver, 6), /*!< Unknown property.*/ + kStatus_FTFx_EraseKeyError = MAKE_STATUS(kStatusGroupFtfxDriver, 7), /*!< API erase key is invalid.*/ + kStatus_FTFx_RegionExecuteOnly = + MAKE_STATUS(kStatusGroupFtfxDriver, 8), /*!< The current region is execute-only.*/ + kStatus_FTFx_ExecuteInRamFunctionNotReady = + MAKE_STATUS(kStatusGroupFtfxDriver, 9), /*!< Execute-in-RAM function is not available.*/ + kStatus_FTFx_PartitionStatusUpdateFailure = + MAKE_STATUS(kStatusGroupFtfxDriver, 10), /*!< Failed to update partition status.*/ + kStatus_FTFx_SetFlexramAsEepromError = + MAKE_STATUS(kStatusGroupFtfxDriver, 11), /*!< Failed to set FlexRAM as EEPROM.*/ + kStatus_FTFx_RecoverFlexramAsRamError = + MAKE_STATUS(kStatusGroupFtfxDriver, 12), /*!< Failed to recover FlexRAM as RAM.*/ + kStatus_FTFx_SetFlexramAsRamError = MAKE_STATUS(kStatusGroupFtfxDriver, 13), /*!< Failed to set FlexRAM as RAM.*/ + kStatus_FTFx_RecoverFlexramAsEepromError = + MAKE_STATUS(kStatusGroupFtfxDriver, 14), /*!< Failed to recover FlexRAM as EEPROM.*/ + kStatus_FTFx_CommandNotSupported = MAKE_STATUS(kStatusGroupFtfxDriver, 15), /*!< Flash API is not supported.*/ + kStatus_FTFx_SwapSystemNotInUninitialized = + MAKE_STATUS(kStatusGroupFtfxDriver, 16), /*!< Swap system is not in an uninitialzed state.*/ + kStatus_FTFx_SwapIndicatorAddressError = + MAKE_STATUS(kStatusGroupFtfxDriver, 17), /*!< The swap indicator address is invalid.*/ + kStatus_FTFx_ReadOnlyProperty = MAKE_STATUS(kStatusGroupFtfxDriver, 18), /*!< The flash property is read-only.*/ + kStatus_FTFx_InvalidPropertyValue = + MAKE_STATUS(kStatusGroupFtfxDriver, 19), /*!< The flash property value is out of range.*/ + kStatus_FTFx_InvalidSpeculationOption = + MAKE_STATUS(kStatusGroupFtfxDriver, 20), /*!< The option of flash prefetch speculation is invalid.*/ +}; +/*@}*/ + +/*! + * @name FTFx API key + * @{ + */ +/*! + * @brief Enumeration for FTFx driver API keys. + * + * @note The resulting value is built with a byte order such that the string + * being readable in expected order when viewed in a hex editor, if the value + * is treated as a 32-bit little endian value. + */ +enum _ftfx_driver_api_keys +{ + kFTFx_ApiEraseKey = FOUR_CHAR_CODE('k', 'f', 'e', 'k') /*!< Key value used to validate all FTFx erase APIs.*/ +}; +/*@}*/ + +/*! + * @brief Enumeration for the FlexRAM load during reset option. + */ +typedef enum _ftfx_partition_flexram_load_option +{ + kFTFx_PartitionFlexramLoadOptLoadedWithValidEepromData = + 0x00U, /*!< FlexRAM is loaded with valid EEPROM data during reset sequence.*/ + kFTFx_PartitionFlexramLoadOptNotLoaded = 0x01U /*!< FlexRAM is not loaded during reset sequence.*/ +} ftfx_partition_flexram_load_opt_t; + +/*! + * @brief Enumeration for the two possible options of flash read resource command. + */ +typedef enum _ftfx_read_resource_opt +{ + kFTFx_ResourceOptionFlashIfr = + 0x00U, /*!< Select code for Program flash 0 IFR, Program flash swap 0 IFR, Data flash 0 IFR */ + kFTFx_ResourceOptionVersionId = 0x01U /*!< Select code for the version ID*/ +} ftfx_read_resource_opt_t; + +/*! + * @brief Enumeration for supported FTFx margin levels. + */ +typedef enum _ftfx_margin_value +{ + kFTFx_MarginValueNormal, /*!< Use the 'normal' read level for 1s.*/ + kFTFx_MarginValueUser, /*!< Apply the 'User' margin to the normal read-1 level.*/ + kFTFx_MarginValueFactory, /*!< Apply the 'Factory' margin to the normal read-1 level.*/ + kFTFx_MarginValueInvalid /*!< Not real margin level, Used to determine the range of valid margin level. */ +} ftfx_margin_value_t; + +/*! + * @brief Enumeration for the three possible FTFx security states. + */ +typedef enum _ftfx_security_state +{ + kFTFx_SecurityStateNotSecure = (int)0xc33cc33c, /*!< Flash is not secure.*/ + kFTFx_SecurityStateBackdoorEnabled = (int)0x5aa55aa5, /*!< Flash backdoor is enabled.*/ + kFTFx_SecurityStateBackdoorDisabled = (int)0x5ac33ca5 /*!< Flash backdoor is disabled.*/ +} ftfx_security_state_t; + +/*! + * @brief Enumeration for the two possilbe options of set FlexRAM function command. + */ +typedef enum _ftfx_flexram_function_option +{ + kFTFx_FlexramFuncOptAvailableAsRam = 0xFFU, /*!< An option used to make FlexRAM available as RAM */ + kFTFx_FlexramFuncOptAvailableForEeprom = 0x00U /*!< An option used to make FlexRAM available for EEPROM */ +} ftfx_flexram_func_opt_t; + +/*! + * @brief Enumeration for the possible options of Swap control commands + */ +typedef enum _ftfx_swap_control_option +{ + kFTFx_SwapControlOptionIntializeSystem = 0x01U, /*!< An option used to initialize the Swap system */ + kFTFx_SwapControlOptionSetInUpdateState = 0x02U, /*!< An option used to set the Swap in an update state */ + kFTFx_SwapControlOptionSetInCompleteState = 0x04U, /*!< An option used to set the Swap in a complete state */ + kFTFx_SwapControlOptionReportStatus = 0x08U, /*!< An option used to report the Swap status */ + kFTFx_SwapControlOptionDisableSystem = 0x10U /*!< An option used to disable the Swap status */ +} ftfx_swap_control_opt_t; + +/*! + * @brief Enumeration for the possible flash Swap status. + */ +typedef enum _ftfx_swap_state +{ + kFTFx_SwapStateUninitialized = 0x00U, /*!< Flash Swap system is in an uninitialized state.*/ + kFTFx_SwapStateReady = 0x01U, /*!< Flash Swap system is in a ready state.*/ + kFTFx_SwapStateUpdate = 0x02U, /*!< Flash Swap system is in an update state.*/ + kFTFx_SwapStateUpdateErased = 0x03U, /*!< Flash Swap system is in an updateErased state.*/ + kFTFx_SwapStateComplete = 0x04U, /*!< Flash Swap system is in a complete state.*/ + kFTFx_SwapStateDisabled = 0x05U /*!< Flash Swap system is in a disabled state.*/ +} ftfx_swap_state_t; + +/*! + * @breif Enumeration for the possible flash Swap block status + */ +typedef enum _ftfx_swap_block_status +{ + kFTFx_SwapBlockStatusLowerHalfProgramBlocksAtZero = + 0x00U, /*!< Swap block status is that lower half program block at zero.*/ + kFTFx_SwapBlockStatusUpperHalfProgramBlocksAtZero = + 0x01U, /*!< Swap block status is that upper half program block at zero.*/ +} ftfx_swap_block_status_t; + +/*! + * @brief Flash Swap information + */ +typedef struct _ftfx_swap_state_config +{ + ftfx_swap_state_t flashSwapState; /*! +#include +#include "fsl_device_registers.h" +#include "bootloader_common.h" +#else +#include "fsl_common.h" +#endif + +#include "fsl_ftfx_adapter.h" + +/*! + * @addtogroup ftfx_feature + * @{ + */ +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! + * @name FTFx configuration + * @{ + */ +/*! @brief Flash driver location. */ +#if !defined(FTFx_DRIVER_IS_FLASH_RESIDENT) +#if (!defined(BL_TARGET_ROM) && !defined(BL_TARGET_RAM)) +#define FTFx_DRIVER_IS_FLASH_RESIDENT 1 /*!< Used for the flash resident application. */ +#else +#define FTFx_DRIVER_IS_FLASH_RESIDENT 0 /*!< Used for the non-flash resident application. */ +#endif +#endif + +/*! @brief Flash Driver Export option */ +#if !defined(FTFx_DRIVER_IS_EXPORTED) +#if defined(BL_TARGET_ROM) +#define FTFx_DRIVER_IS_EXPORTED 1 /*!< Used for the ROM bootloader. */ +#else +#define FTFx_DRIVER_IS_EXPORTED 0 /*!< Used for the MCUXpresso SDK application. */ +#endif +#endif +/*@}*/ + +/*! @brief Indicates whether the secondary flash is supported in the Flash driver */ +#if defined(FSL_FEATURE_FLASH_HAS_MULTIPLE_FLASH) || defined(FSL_FEATURE_FLASH_PFLASH_1_START_ADDRESS) +#define FTFx_DRIVER_HAS_FLASH1_SUPPORT (1) +#define FTFx_FLASH_COUNT (2) +#else +#define FTFx_DRIVER_HAS_FLASH1_SUPPORT (0) +#define FTFx_FLASH_COUNT (1) +#endif + +/*! + * @name Secondary flash configuration + * @{ + */ +/*! @brief Indicates whether the secondary flash has its own protection register in flash module. */ +#if defined(FSL_FEATURE_FLASH_HAS_MULTIPLE_FLASH) && defined(FTFE_FPROTS_PROTS_MASK) +#define FTFx_FLASH1_HAS_PROT_CONTROL (1) +#else +#define FTFx_FLASH1_HAS_PROT_CONTROL (0) +#endif + +/*! @brief Indicates whether the secondary flash has its own Execute-Only access register in flash module. */ +#if defined(FSL_FEATURE_FLASH_HAS_MULTIPLE_FLASH) && defined(FTFE_FACSSS_SGSIZE_S_MASK) +#define FTFx_FLASH1_HAS_XACC_CONTROL (1) +#else +#define FTFx_FLASH1_HAS_XACC_CONTROL (0) +#endif +/*@}*/ + +#if FTFx_FLASH1_HAS_XACC_CONTROL || FTFx_FLASH1_HAS_PROT_CONTROL +#define FTFx_FLASH1_IS_INDEPENDENT_BLOCK (1) +#else +#define FTFx_FLASH1_IS_INDEPENDENT_BLOCK (0) +#endif + +#endif /* _FSL_FTFX_FEATURES_H_ */ + diff --git a/ext/hal/nxp/mcux/drivers/kinetis/fsl_ftfx_flash.c b/ext/hal/nxp/mcux/drivers/kinetis/fsl_ftfx_flash.c new file mode 100644 index 00000000000..60df8e38d54 --- /dev/null +++ b/ext/hal/nxp/mcux/drivers/kinetis/fsl_ftfx_flash.c @@ -0,0 +1,1176 @@ +/* +* Copyright 2013-2016 Freescale Semiconductor, Inc. +* Copyright 2016-2018 NXP +* All rights reserved. +* +* SPDX-License-Identifier: BSD-3-Clause +* +*/ + +#include "fsl_ftfx_flash.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! + * @brief Enumeration for special memory property. + */ +enum _ftfx_special_mem_property +{ + kFTFx_AccessSegmentUnitSize = 256UL, + kFTFx_MinProtectBlockSize = 1024UL, +}; + +/*! + * @brief Enumeration for the index of read/program once record + */ +enum _k3_flash_read_once_index +{ + kFLASH_RecordIndexSwapAddr = 0xA1U, /*!< Index of Swap indicator address.*/ + kFLASH_RecordIndexSwapEnable = 0xA2U, /*!< Index of Swap system enable.*/ + kFLASH_RecordIndexSwapDisable = 0xA3U, /*!< Index of Swap system disable.*/ +}; + + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +static void flash_init_features(ftfx_config_t *config); + +static uint32_t flash_calculate_mem_size(uint32_t pflashBlockCount, + uint32_t pflashBlockSize, + uint32_t pfsizeMask, + uint32_t pfsizeShift); + +static uint32_t flash_calculate_prot_segment_size(uint32_t flashSize, uint32_t segmentCount); + +static status_t flash_check_range_to_get_index(flash_config_t *config, uint32_t start, uint32_t lengthInBytes, uint8_t *flashIndex); + +/*! @brief Convert address for flash.*/ +static status_t flash_convert_start_address(ftfx_config_t *config, uint32_t start); + +#if defined(FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP) && FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP +/*! @brief Validates the gived address to see if it is equal to swap indicator address in pflash swap IFR.*/ +static status_t flash_validate_swap_indicator_address(ftfx_config_t *config, uint32_t address); +#endif /* FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP */ + +/******************************************************************************* + * Variables + ******************************************************************************/ + +static volatile uint32_t *const kFPROTL = (volatile uint32_t *)&FTFx_FPROT_LOW_REG; +static volatile uint32_t *const kFPROTH = (volatile uint32_t *)&FTFx_FPROT_HIGH_REG; +#if FTFx_DRIVER_HAS_FLASH1_SUPPORT +volatile uint8_t *const kFPROTSL = (volatile uint8_t *)&FTFx_FPROTSL_REG; +volatile uint8_t *const kFPROTSH = (volatile uint8_t *)&FTFx_FPROTSH_REG; +#endif + +/*! + * @brief Table of pflash sizes. + * + * The index into this table is the value of the SIM_FCFG1.PFSIZE bitfield. + * + * The values in this table have been right shifted 10 bits so that they will all fit within + * an 16-bit integer. To get the actual flash density, you must left shift the looked up value + * by 10 bits. + * + * Elements of this table have a value of 0 in cases where the PFSIZE bitfield value is + * reserved. + * + * Code to use the table: + * @code + * uint8_t pfsize = (SIM->FCFG1 & SIM_FCFG1_PFSIZE_MASK) >> SIM_FCFG1_PFSIZE_SHIFT; + * flashDensity = ((uint32_t)kPFlashDensities[pfsize]) << 10; + * @endcode + */ +#if defined(FSL_FEATURE_FLASH_SIZE_ENCODING_RULE_VERSION) && (FSL_FEATURE_FLASH_SIZE_ENCODING_RULE_VERSION == 1) +static const uint16_t kPFlashDensities[] = { + 0, /* 0x0 - undefined */ + 0, /* 0x1 - undefined */ + 0, /* 0x2 - undefined */ + 0, /* 0x3 - undefined */ + 0, /* 0x4 - undefined */ + 0, /* 0x5 - undefined */ + 0, /* 0x6 - undefined */ + 0, /* 0x7 - undefined */ + 0, /* 0x8 - undefined */ + 0, /* 0x9 - undefined */ + 256, /* 0xa - 262144, 256KB */ + 0, /* 0xb - undefined */ + 1024, /* 0xc - 1048576, 1MB */ + 0, /* 0xd - undefined */ + 0, /* 0xe - undefined */ + 0, /* 0xf - undefined */ +}; +#else +static const uint16_t kPFlashDensities[] = { + 8, /* 0x0 - 8192, 8KB */ + 16, /* 0x1 - 16384, 16KB */ + 24, /* 0x2 - 24576, 24KB */ + 32, /* 0x3 - 32768, 32KB */ + 48, /* 0x4 - 49152, 48KB */ + 64, /* 0x5 - 65536, 64KB */ + 96, /* 0x6 - 98304, 96KB */ + 128, /* 0x7 - 131072, 128KB */ + 192, /* 0x8 - 196608, 192KB */ + 256, /* 0x9 - 262144, 256KB */ + 384, /* 0xa - 393216, 384KB */ + 512, /* 0xb - 524288, 512KB */ + 768, /* 0xc - 786432, 768KB */ + 1024, /* 0xd - 1048576, 1MB */ + 1536, /* 0xe - 1572864, 1.5MB */ + /* 2048, 0xf - 2097152, 2MB */ +}; +#endif + +/******************************************************************************* + * Code + ******************************************************************************/ + +status_t FLASH_Init(flash_config_t *config) +{ + status_t returnCode; + + if (config == NULL) + { + return kStatus_FTFx_InvalidArgument; + } + + for (uint8_t flashIndex = 0; flashIndex < FTFx_FLASH_COUNT; flashIndex++) + { + uint32_t pflashStartAddress; + uint32_t pflashBlockSize; + uint32_t pflashBlockCount; + uint32_t pflashBlockSectorSize; + uint32_t pflashProtectionRegionCount; + uint32_t pflashBlockWriteUnitSize; + uint32_t pflashSectorCmdAlignment; + uint32_t pflashSectionCmdAlignment; + uint32_t pfsizeMask; + uint32_t pfsizeShift; + uint32_t facssValue; + uint32_t facsnValue; + + config->ftfxConfig[flashIndex].flashDesc.type = kFTFx_MemTypePflash; + config->ftfxConfig[flashIndex].flashDesc.index = flashIndex; + flash_init_features(&config->ftfxConfig[flashIndex]); + +#if FTFx_DRIVER_HAS_FLASH1_SUPPORT + if(flashIndex == 1) + { + pflashStartAddress = FLASH1_FEATURE_PFLASH_START_ADDRESS; + pflashBlockSize = FLASH1_FEATURE_PFLASH_BLOCK_SIZE; + pflashBlockCount = FLASH1_FEATURE_PFLASH_BLOCK_COUNT; + pflashBlockSectorSize = FLASH1_FEATURE_PFLASH_BLOCK_SECTOR_SIZE; + pflashProtectionRegionCount = FLASH1_FEATURE_PFLASH_PROTECTION_REGION_COUNT; + pflashBlockWriteUnitSize = FLASH1_FEATURE_PFLASH_BLOCK_WRITE_UNIT_SIZE; + pflashSectorCmdAlignment = FLASH1_FEATURE_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT; + pflashSectionCmdAlignment = FLASH1_FEATURE_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT; + pfsizeMask = SIM_FLASH1_PFSIZE_MASK; + pfsizeShift = SIM_FLASH1_PFSIZE_SHIFT; + facssValue = FTFx_FACSSS_REG; + facsnValue = FTFx_FACSNS_REG; + } + else +#endif + { + pflashStartAddress = FLASH0_FEATURE_PFLASH_START_ADDRESS; + pflashBlockSize = FLASH0_FEATURE_PFLASH_BLOCK_SIZE; + pflashBlockCount = FLASH0_FEATURE_PFLASH_BLOCK_COUNT; + pflashBlockSectorSize = FLASH0_FEATURE_PFLASH_BLOCK_SECTOR_SIZE; + pflashProtectionRegionCount = FLASH0_FEATURE_PFLASH_PROTECTION_REGION_COUNT; + pflashBlockWriteUnitSize = FLASH0_FEATURE_PFLASH_BLOCK_WRITE_UNIT_SIZE; + pflashSectorCmdAlignment = FLASH0_FEATURE_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT; + pflashSectionCmdAlignment = FLASH0_FEATURE_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT; + pfsizeMask = SIM_FLASH0_PFSIZE_MASK; + pfsizeShift = SIM_FLASH0_PFSIZE_SHIFT; + facssValue = FTFx_FACSS_REG; + facsnValue = FTFx_FACSN_REG; + } + + config->ftfxConfig[flashIndex].flashDesc.blockBase = pflashStartAddress; + config->ftfxConfig[flashIndex].flashDesc.blockCount = pflashBlockCount; + config->ftfxConfig[flashIndex].flashDesc.sectorSize = pflashBlockSectorSize; + + if (config->ftfxConfig[flashIndex].flashDesc.feature.isIndBlock && + config->ftfxConfig[flashIndex].flashDesc.feature.hasIndPfsizeReg) + { + config->ftfxConfig[flashIndex].flashDesc.totalSize = flash_calculate_mem_size(pflashBlockCount, pflashBlockSize, pfsizeMask, pfsizeShift); + } + else + { + config->ftfxConfig[flashIndex].flashDesc.totalSize = pflashBlockCount * pflashBlockSize; + } + + if (config->ftfxConfig[flashIndex].flashDesc.feature.hasXaccControl) + { + ftfx_spec_mem_t *specMem; + specMem = &config->ftfxConfig[flashIndex].flashDesc.accessSegmentMem; + if (config->ftfxConfig[flashIndex].flashDesc.feature.hasIndXaccReg) + { + specMem->base = config->ftfxConfig[flashIndex].flashDesc.blockBase; + specMem->size = kFTFx_AccessSegmentUnitSize << facssValue; + specMem->count = facsnValue; + } + else + { + specMem->base = config->ftfxConfig[0].flashDesc.blockBase; + specMem->size = kFTFx_AccessSegmentUnitSize << FTFx_FACSS_REG; + specMem->count = FTFx_FACSN_REG; + } + } + + if (config->ftfxConfig[flashIndex].flashDesc.feature.hasProtControl) + { + ftfx_spec_mem_t *specMem; + specMem = &config->ftfxConfig[flashIndex].flashDesc.protectRegionMem; + if (config->ftfxConfig[flashIndex].flashDesc.feature.hasIndProtReg) + { + specMem->base = config->ftfxConfig[flashIndex].flashDesc.blockBase; + specMem->count = pflashProtectionRegionCount; + specMem->size = flash_calculate_prot_segment_size(config->ftfxConfig[flashIndex].flashDesc.totalSize, specMem->count); + } + else + { + uint32_t pflashTotalSize = 0; + specMem->base = config->ftfxConfig[0].flashDesc.blockBase; + specMem->count = FLASH0_FEATURE_PFLASH_PROTECTION_REGION_COUNT; +#if (FTFx_FLASH_COUNT != 1) + if (flashIndex == FTFx_FLASH_COUNT - 1) +#endif + { + uint32_t segmentSize; + for (uint32_t i = 0; i < FTFx_FLASH_COUNT; i++) + { + pflashTotalSize += config->ftfxConfig[flashIndex].flashDesc.totalSize; + } + segmentSize = flash_calculate_prot_segment_size(pflashTotalSize, specMem->count); + for (uint32_t i = 0; i < FTFx_FLASH_COUNT; i++) + { + config->ftfxConfig[i].flashDesc.protectRegionMem.size = segmentSize; + } + } + } + } + + config->ftfxConfig[flashIndex].opsConfig.addrAligment.blockWriteUnitSize = pflashBlockWriteUnitSize; + config->ftfxConfig[flashIndex].opsConfig.addrAligment.sectorCmd = pflashSectorCmdAlignment; + config->ftfxConfig[flashIndex].opsConfig.addrAligment.sectionCmd = pflashSectionCmdAlignment; + config->ftfxConfig[flashIndex].opsConfig.addrAligment.resourceCmd = FSL_FEATURE_FLASH_PFLASH_RESOURCE_CMD_ADDRESS_ALIGMENT; + config->ftfxConfig[flashIndex].opsConfig.addrAligment.checkCmd = FSL_FEATURE_FLASH_PFLASH_CHECK_CMD_ADDRESS_ALIGMENT; + config->ftfxConfig[flashIndex].opsConfig.addrAligment.swapCtrlCmd = FSL_FEATURE_FLASH_PFLASH_SWAP_CONTROL_CMD_ADDRESS_ALIGMENT; + + /* Init FTFx Kernel */ + returnCode = FTFx_API_Init(&config->ftfxConfig[flashIndex]); + if (returnCode != kStatus_FTFx_Success) + { + return returnCode; + } + } + + return kStatus_FTFx_Success; +} + +status_t FLASH_Erase(flash_config_t *config, uint32_t start, uint32_t lengthInBytes, uint32_t key) +{ + status_t returnCode; + uint8_t flashIndex; + + returnCode = flash_check_range_to_get_index(config, start, lengthInBytes, &flashIndex); + if (returnCode != kStatus_FTFx_Success) + { + return returnCode; + } + + returnCode = flash_convert_start_address(&config->ftfxConfig[flashIndex], start); + if (returnCode != kStatus_FTFx_Success) + { + return returnCode; + } + + return FTFx_CMD_Erase(&config->ftfxConfig[flashIndex], start, lengthInBytes, key); +} + +status_t FLASH_EraseAll(flash_config_t *config, uint32_t key) +{ + return FTFx_CMD_EraseAll(&config->ftfxConfig[0], key); +} + +#if defined(FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_UNSECURE_CMD) && FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_UNSECURE_CMD +status_t FLASH_EraseAllUnsecure(flash_config_t *config, uint32_t key) +{ + return FTFx_CMD_EraseAllUnsecure(&config->ftfxConfig[0], key); +} +#endif + +status_t FLASH_Program(flash_config_t *config, uint32_t start, uint8_t *src, uint32_t lengthInBytes) +{ + status_t returnCode; + uint8_t flashIndex; + + returnCode = flash_check_range_to_get_index(config, start, lengthInBytes, &flashIndex); + if (returnCode != kStatus_FTFx_Success) + { + return returnCode; + } + + returnCode = flash_convert_start_address(&config->ftfxConfig[flashIndex], start); + if (returnCode != kStatus_FTFx_Success) + { + return returnCode; + } + + return FTFx_CMD_Program(&config->ftfxConfig[flashIndex], start, src, lengthInBytes); +} + +#if defined(FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD) && FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD +status_t FLASH_ProgramSection(flash_config_t *config, uint32_t start, uint8_t *src, uint32_t lengthInBytes) +{ + status_t returnCode; + uint8_t flashIndex; + + returnCode = flash_check_range_to_get_index(config, start, lengthInBytes, &flashIndex); + if (returnCode != kStatus_FTFx_Success) + { + return returnCode; + } + + returnCode = flash_convert_start_address(&config->ftfxConfig[flashIndex], start); + if (returnCode != kStatus_FTFx_Success) + { + return returnCode; + } + + return FTFx_CMD_ProgramSection(&config->ftfxConfig[flashIndex], start, src, lengthInBytes); +} +#endif + +#if defined(FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD) && FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD +status_t FLASH_ReadResource(flash_config_t *config, + uint32_t start, + uint8_t *dst, + uint32_t lengthInBytes, + ftfx_read_resource_opt_t option) +{ + return FTFx_CMD_ReadResource(&config->ftfxConfig[0], start, dst, lengthInBytes, option); +} +#endif + +status_t FLASH_VerifyErase(flash_config_t *config, uint32_t start, uint32_t lengthInBytes, ftfx_margin_value_t margin) +{ + status_t returnCode; + uint8_t flashIndex; + + returnCode = flash_check_range_to_get_index(config, start, lengthInBytes, &flashIndex); + if (returnCode != kStatus_FTFx_Success) + { + return returnCode; + } + + returnCode = flash_convert_start_address(&config->ftfxConfig[flashIndex], start); + if (returnCode != kStatus_FTFx_Success) + { + return returnCode; + } + + return FTFx_CMD_VerifyErase(&config->ftfxConfig[flashIndex], start, lengthInBytes, margin); +} + +status_t FLASH_VerifyEraseAll(flash_config_t *config, ftfx_margin_value_t margin) +{ + return FTFx_CMD_VerifyEraseAll(&config->ftfxConfig[0], margin); +} + +status_t FLASH_VerifyProgram(flash_config_t *config, + uint32_t start, + uint32_t lengthInBytes, + const uint8_t *expectedData, + ftfx_margin_value_t margin, + uint32_t *failedAddress, + uint32_t *failedData) +{ + status_t returnCode; + uint8_t flashIndex; + + returnCode = flash_check_range_to_get_index(config, start, lengthInBytes, &flashIndex); + if (returnCode != kStatus_FTFx_Success) + { + return returnCode; + } + + returnCode = flash_convert_start_address(&config->ftfxConfig[flashIndex], start); + if (returnCode != kStatus_FTFx_Success) + { + return returnCode; + } + + return FTFx_CMD_VerifyProgram(&config->ftfxConfig[flashIndex], start, lengthInBytes, expectedData, margin, failedAddress, failedData); +} + +status_t FLASH_GetSecurityState(flash_config_t *config, ftfx_security_state_t *state) +{ + return FTFx_REG_GetSecurityState(&config->ftfxConfig[0], state); +} + +status_t FLASH_SecurityBypass(flash_config_t *config, const uint8_t *backdoorKey) +{ + return FTFx_CMD_SecurityBypass(&config->ftfxConfig[0], backdoorKey); +} + +#if defined(FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD) && FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD +status_t FLASH_SetFlexramFunction(flash_config_t *config, ftfx_flexram_func_opt_t option) +{ + return FTFx_CMD_SetFlexramFunction(&config->ftfxConfig[0], option); +} +#endif + +#if defined(FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP) && FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP +status_t FLASH_Swap(flash_config_t *config, uint32_t address, bool isSetEnable) +{ + status_t returnCode; + ftfx_swap_state_config_t returnInfo; + ftfx_config_t *ftfxConfig; + uint8_t flashIndex; + + returnCode = flash_check_range_to_get_index(config, address, 1, &flashIndex); + if (returnCode != kStatus_FTFx_Success) + { + return returnCode; + } + + ftfxConfig = &config->ftfxConfig[flashIndex]; + + memset(&returnInfo, 0xFFU, sizeof(returnInfo)); + + do + { + returnCode = FTFx_CMD_SwapControl(ftfxConfig, address, kFTFx_SwapControlOptionReportStatus, &returnInfo); + if (returnCode != kStatus_FTFx_Success) + { + return returnCode; + } + + if (!isSetEnable) + { + if (returnInfo.flashSwapState == kFTFx_SwapStateDisabled) + { + return kStatus_FTFx_Success; + } + else if (returnInfo.flashSwapState == kFTFx_SwapStateUninitialized) + { + /* The swap system changed to the DISABLED state with Program flash block 0 + * located at relative flash address 0x0_0000 */ + returnCode = FTFx_CMD_SwapControl(ftfxConfig, address, kFTFx_SwapControlOptionDisableSystem, &returnInfo); + } + else + { + /* Swap disable should be requested only when swap system is in the uninitialized state */ + return kStatus_FTFx_SwapSystemNotInUninitialized; + } + } + else + { + /* When first swap: the initial swap state is Uninitialized, flash swap indicator address is unset, + * the swap procedure should be Uninitialized -> Update-Erased -> Complete. + * After the first swap has been completed, the flash swap inidicator address cannot be modified + * unless EraseAllBlocks command is issued, the swap procedure is changed to Update -> Update-Erased -> + * Complete. */ + switch (returnInfo.flashSwapState) + { + case kFTFx_SwapStateUninitialized: + /* If current swap mode is Uninitialized, Initialize Swap to Initialized/READY state. */ + returnCode = + FTFx_CMD_SwapControl(ftfxConfig, address, kFTFx_SwapControlOptionIntializeSystem, &returnInfo); + break; + case kFTFx_SwapStateReady: + /* Validate whether the address provided to the swap system is matched to + * swap indicator address in the IFR */ + returnCode = flash_validate_swap_indicator_address(ftfxConfig, address); + if (returnCode == kStatus_FTFx_Success) + { + /* If current swap mode is Initialized/Ready, Initialize Swap to UPDATE state. */ + returnCode = + FTFx_CMD_SwapControl(ftfxConfig, address, kFTFx_SwapControlOptionSetInUpdateState, &returnInfo); + } + break; + case kFTFx_SwapStateUpdate: + /* If current swap mode is Update, Erase indicator sector in non active block + * to proceed swap system to update-erased state */ + returnCode = FLASH_Erase(config, address + (ftfxConfig->flashDesc.totalSize >> 1), + ftfxConfig->opsConfig.addrAligment.sectorCmd, kFTFx_ApiEraseKey); + break; + case kFTFx_SwapStateUpdateErased: + /* If current swap mode is Update or Update-Erased, progress Swap to COMPLETE State */ + returnCode = + FTFx_CMD_SwapControl(ftfxConfig, address, kFTFx_SwapControlOptionSetInCompleteState, &returnInfo); + break; + case kFTFx_SwapStateComplete: + break; + case kFTFx_SwapStateDisabled: + /* When swap system is in disabled state, We need to clear swap system back to uninitialized + * by issuing EraseAllBlocks command */ + returnCode = kStatus_FTFx_SwapSystemNotInUninitialized; + break; + default: + returnCode = kStatus_FTFx_InvalidArgument; + break; + } + } + if (returnCode != kStatus_FTFx_Success) + { + break; + } + } while (!((kFTFx_SwapStateComplete == returnInfo.flashSwapState) && isSetEnable)); + + return returnCode; +} +#endif /* FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP */ + +status_t FLASH_IsProtected(flash_config_t *config, + uint32_t start, + uint32_t lengthInBytes, + flash_prot_state_t *protection_state) +{ + status_t returnCode; + ftfx_config_t *ftfxConfig; + uint8_t flashIndex; + + if (protection_state == NULL) + { + return kStatus_FTFx_InvalidArgument; + } + + returnCode = flash_check_range_to_get_index(config, start, lengthInBytes, &flashIndex); + if (returnCode != kStatus_FTFx_Success) + { + return returnCode; + } + + ftfxConfig = &config->ftfxConfig[flashIndex]; + + if (ftfxConfig->flashDesc.feature.hasProtControl) + { + uint32_t endAddress; /* end address for protection check */ + uint32_t regionCheckedCounter; /* increments each time the flash address was checked for + * protection status */ + uint32_t regionCounter; /* incrementing variable used to increment through the flash + * protection regions */ + uint32_t protectStatusCounter; /* increments each time a flash region was detected as protected */ + uint8_t flashRegionProtectStatus[MAX_FLASH_PROT_REGION_COUNT]; /* array of the protection + * status for each + * protection region */ + uint32_t flashRegionAddress[MAX_FLASH_PROT_REGION_COUNT + 1]; /* array of the start addresses for each flash + * protection region. Note this is REGION_COUNT+1 + * due to requiring the next start address after + * the end of flash for loop-check purposes below */ + bool isBreakNeeded = false; + /* calculating Flash end address */ + endAddress = start + lengthInBytes; + + /* populate the flashRegionAddress array with the start address of each flash region */ + regionCounter = 0; /* make sure regionCounter is initialized to 0 first */ + /* populate up to 33rd element of array, this is the next address after end of flash array */ + while (regionCounter <= ftfxConfig->flashDesc.protectRegionMem.count) + { + flashRegionAddress[regionCounter] = + ftfxConfig->flashDesc.protectRegionMem.base + ftfxConfig->flashDesc.protectRegionMem.size * regionCounter; + regionCounter++; + } + + /* populate flashRegionProtectStatus array with status information + * Protection status for each region is stored in the FPROT[3:0] registers + * Each bit represents one region of flash + * 4 registers * 8-bits-per-register = 32-bits (32-regions) + * The convention is: + * FPROT3[bit 0] is the first protection region (start of flash memory) + * FPROT0[bit 7] is the last protection region (end of flash memory) + * regionCounter is used to determine which FPROT[3:0] register to check for protection status + * Note: FPROT=1 means NOT protected, FPROT=0 means protected */ + regionCounter = 0; /* make sure regionCounter is initialized to 0 first */ + while (regionCounter < ftfxConfig->flashDesc.protectRegionMem.count) + { + if ((ftfxConfig->flashDesc.index == 0) || (!ftfxConfig->flashDesc.feature.hasIndProtReg)) + { + /* Note: So far protection region count may be 16/20/24/32/64 */ + if (regionCounter < 8) + { + flashRegionProtectStatus[regionCounter] = (FTFx_FPROTL3_REG >> regionCounter) & (0x01u); + } + else if (regionCounter < 16) + { + flashRegionProtectStatus[regionCounter] = (FTFx_FPROTL2_REG >> (regionCounter - 8)) & (0x01u); + } +#if defined(MAX_FLASH_PROT_REGION_COUNT) && (MAX_FLASH_PROT_REGION_COUNT > 16) +#if (MAX_FLASH_PROT_REGION_COUNT == 20) + else if (regionCounter < 20) + { + flashRegionProtectStatus[regionCounter] = (FTFx_FPROTL1_REG >> (regionCounter - 16)) & (0x01u); + } +#else + else if (regionCounter < 24) + { + flashRegionProtectStatus[regionCounter] = (FTFx_FPROTL1_REG >> (regionCounter - 16)) & (0x01u); + } +#endif /*(MAX_FLASH_PROT_REGION_COUNT == 20)*/ +#endif +#if defined(MAX_FLASH_PROT_REGION_COUNT) && (MAX_FLASH_PROT_REGION_COUNT > 24) + else if (regionCounter < 32) + { + flashRegionProtectStatus[regionCounter] = (FTFx_FPROTL0_REG >> (regionCounter - 24)) & (0x01u); + } +#endif +#if defined(MAX_FLASH_PROT_REGION_COUNT) && (MAX_FLASH_PROT_REGION_COUNT == 64) + else if (regionCounter < 40) + { + flashRegionProtectStatus[regionCounter] = (FTFx_FPROTH3_REG >> (regionCounter - 32)) & (0x01u); + } + else if (regionCounter < 48) + { + flashRegionProtectStatus[regionCounter] = (FTFx_FPROTH2_REG >> (regionCounter - 40)) & (0x01u); + } + else if (regionCounter < 56) + { + flashRegionProtectStatus[regionCounter] = (FTFx_FPROTH1_REG >> (regionCounter - 48)) & (0x01u); + } + else if (regionCounter < 64) + { + flashRegionProtectStatus[regionCounter] = (FTFx_FPROTH0_REG >> (regionCounter - 56)) & (0x01u); + } +#endif + else + { + isBreakNeeded = true; + } + regionCounter++; + } + else if ((ftfxConfig->flashDesc.index == 1) && ftfxConfig->flashDesc.feature.hasIndProtReg) + { + /* Note: So far protection region count may be 8/16 */ + if (regionCounter < 8) + { + flashRegionProtectStatus[regionCounter] = (FTFx_FPROTSL_REG >> regionCounter) & (0x01u); + } + else if (regionCounter < 16) + { + flashRegionProtectStatus[regionCounter] = (FTFx_FPROTSH_REG >> (regionCounter - 8)) & (0x01u); + } + else + { + isBreakNeeded = true; + } + regionCounter++; + } + else + {} + + if (isBreakNeeded) + { + break; + } + } + + /* loop through the flash regions and check + * desired flash address range for protection status + * loop stops when it is detected that start has exceeded the endAddress */ + regionCounter = 0; /* make sure regionCounter is initialized to 0 first */ + regionCheckedCounter = 0; + protectStatusCounter = 0; /* make sure protectStatusCounter is initialized to 0 first */ + while (start < endAddress) + { + /* check to see if the address falls within this protection region + * Note that if the entire flash is to be checked, the last protection + * region checked would consist of the last protection start address and + * the start address following the end of flash */ + if ((start >= flashRegionAddress[regionCounter]) && (start < flashRegionAddress[regionCounter + 1])) + { + /* increment regionCheckedCounter to indicate this region was checked */ + regionCheckedCounter++; + + /* check the protection status of this region + * Note: FPROT=1 means NOT protected, FPROT=0 means protected */ + if (!flashRegionProtectStatus[regionCounter]) + { + /* increment protectStatusCounter to indicate this region is protected */ + protectStatusCounter++; + } + start += ftfxConfig->flashDesc.protectRegionMem.size; /* increment to an address within the next region */ + } + regionCounter++; /* increment regionCounter to check for the next flash protection region */ + } + + /* if protectStatusCounter == 0, then no region of the desired flash region is protected */ + if (protectStatusCounter == 0) + { + *protection_state = kFLASH_ProtectionStateUnprotected; + } + /* if protectStatusCounter == regionCheckedCounter, then each region checked was protected */ + else if (protectStatusCounter == regionCheckedCounter) + { + *protection_state = kFLASH_ProtectionStateProtected; + } + /* if protectStatusCounter != regionCheckedCounter, then protection status is mixed + * In other words, some regions are protected while others are unprotected */ + else + { + *protection_state = kFLASH_ProtectionStateMixed; + } + } + else + { + *protection_state = kFLASH_ProtectionStateUnprotected; + } + + return kStatus_FTFx_Success; +} + +status_t FLASH_IsExecuteOnly(flash_config_t *config, + uint32_t start, + uint32_t lengthInBytes, + flash_xacc_state_t *access_state) +{ + status_t returnCode; + ftfx_config_t *ftfxConfig; + uint8_t flashIndex; + + if (access_state == NULL) + { + return kStatus_FTFx_InvalidArgument; + } + + returnCode = flash_check_range_to_get_index(config, start, lengthInBytes, &flashIndex); + if (returnCode != kStatus_FTFx_Success) + { + return returnCode; + } + + ftfxConfig = &config->ftfxConfig[flashIndex]; + + if (ftfxConfig->flashDesc.feature.hasXaccControl) + { +#if defined(FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL) && FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL + uint32_t executeOnlySegmentCounter = 0; + + /* calculating end address */ + uint32_t endAddress = start + lengthInBytes; + + /* Aligning start address and end address */ + uint32_t alignedStartAddress = ALIGN_DOWN(start, ftfxConfig->flashDesc.accessSegmentMem.size); + uint32_t alignedEndAddress = ALIGN_UP(endAddress, ftfxConfig->flashDesc.accessSegmentMem.size); + + uint32_t segmentIndex = 0; + uint32_t maxSupportedExecuteOnlySegmentCount = + (alignedEndAddress - alignedStartAddress) / ftfxConfig->flashDesc.accessSegmentMem.size; + + while (start < endAddress) + { + uint32_t xacc = 0; + bool isInvalidSegmentIndex = false; + + segmentIndex = (start - ftfxConfig->flashDesc.accessSegmentMem.base) / ftfxConfig->flashDesc.accessSegmentMem.size; + + if ((ftfxConfig->flashDesc.index == 0) || (!ftfxConfig->flashDesc.feature.hasIndXaccReg)) + { + /* For primary flash, The eight XACC registers allow up to 64 restricted segments of equal memory size. + */ + if (segmentIndex < 32) + { + xacc = *(const volatile uint32_t *)&FTFx_XACCL3_REG; + } + else if (segmentIndex < ftfxConfig->flashDesc.accessSegmentMem.count) + { + xacc = *(const volatile uint32_t *)&FTFx_XACCH3_REG; + segmentIndex -= 32; + } + else + { + isInvalidSegmentIndex = true; + } + } +#if FTFx_DRIVER_HAS_FLASH1_SUPPORT + else if ((ftfxConfig->flashDesc.index == 1) && ftfxConfig->flashDesc.feature.hasIndXaccReg) + { + /* For secondary flash, The two XACCS registers allow up to 16 restricted segments of equal memory size. + */ + if (segmentIndex < 8) + { + xacc = *(const volatile uint8_t *)&FTFx_XACCSL_REG; + } + else if (segmentIndex < ftfxConfig->flashDesc.accessSegmentMem.count) + { + xacc = *(const volatile uint8_t *)&FTFx_XACCSH_REG; + segmentIndex -= 8; + } + else + { + isInvalidSegmentIndex = true; + } + } +#endif + else + {} + + if (isInvalidSegmentIndex) + { + break; + } + + /* Determine if this address range is in a execute-only protection flash segment. */ + if ((~xacc) & (1u << segmentIndex)) + { + executeOnlySegmentCounter++; + } + + start += ftfxConfig->flashDesc.accessSegmentMem.size; + } + + if (executeOnlySegmentCounter < 1u) + { + *access_state = kFLASH_AccessStateUnLimited; + } + else if (executeOnlySegmentCounter < maxSupportedExecuteOnlySegmentCount) + { + *access_state = kFLASH_AccessStateMixed; + } + else + { + *access_state = kFLASH_AccessStateExecuteOnly; + } +#endif /* FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL */ + } + else + { + *access_state = kFLASH_AccessStateUnLimited; + } + + return kStatus_FTFx_Success; +} + +status_t FLASH_PflashSetProtection(flash_config_t *config, pflash_prot_status_t *protectStatus) +{ + if (config == NULL) + { + return kStatus_FTFx_InvalidArgument; + } + + if (config->ftfxConfig[0].flashDesc.feature.hasProtControl) + { + if (config->ftfxConfig[0].flashDesc.feature.ProtRegBits >= 32) + { + *kFPROTL = protectStatus->protl; + if (protectStatus->protl != *kFPROTL) + { + return kStatus_FTFx_CommandFailure; + } + } + if (config->ftfxConfig[0].flashDesc.feature.ProtRegBits == 64) + { + *kFPROTH = protectStatus->proth; + if (protectStatus->proth != *kFPROTH) + { + return kStatus_FTFx_CommandFailure; + } + } + } +#if FTFx_DRIVER_HAS_FLASH1_SUPPORT + else if (config->ftfxConfig[1].flashDesc.feature.hasProtControl && \ + config->ftfxConfig[1].flashDesc.feature.hasIndProtReg) + { + if (config->ftfxConfig[1].flashDesc.feature.ProtRegBits == 16) + { + *kFPROTSL = protectStatus->protsl; + if (protectStatus->protsl != *kFPROTSL) + { + return kStatus_FTFx_CommandFailure; + } + *kFPROTSH = protectStatus->protsh; + if (protectStatus->protsh != *kFPROTSH) + { + return kStatus_FTFx_CommandFailure; + } + } + } +#endif + + return kStatus_FTFx_Success; +} + +status_t FLASH_PflashGetProtection(flash_config_t *config, pflash_prot_status_t *protectStatus) +{ + if ((config == NULL) || (protectStatus == NULL)) + { + return kStatus_FTFx_InvalidArgument; + } + + if (config->ftfxConfig[0].flashDesc.feature.hasProtControl) + { + if (config->ftfxConfig[0].flashDesc.feature.ProtRegBits >= 32) + { + protectStatus->protl = *kFPROTL; + } + if (config->ftfxConfig[0].flashDesc.feature.ProtRegBits == 64) + { + protectStatus->proth = *kFPROTH; + } + } +#if FTFx_DRIVER_HAS_FLASH1_SUPPORT + else if (config->ftfxConfig[1].flashDesc.feature.hasProtControl && \ + config->ftfxConfig[1].flashDesc.feature.hasIndProtReg) + { + if (config->ftfxConfig[0].flashDesc.feature.ProtRegBits == 16) + { + protectStatus->protsl = *kFPROTSL; + protectStatus->protsh = *kFPROTSH; + } + } +#endif + + return kStatus_FTFx_Success; +} + +status_t FLASH_GetProperty(flash_config_t *config, flash_property_tag_t whichProperty, uint32_t *value) +{ + if ((config == NULL) || (value == NULL)) + { + return kStatus_FTFx_InvalidArgument; + } + + switch (whichProperty) + { + case kFLASH_PropertyPflash0SectorSize: + *value = config->ftfxConfig[0].flashDesc.sectorSize; + break; + case kFLASH_PropertyPflash0TotalSize: + *value = config->ftfxConfig[0].flashDesc.totalSize; + break; + case kFLASH_PropertyPflash0BlockSize: + *value = config->ftfxConfig[0].flashDesc.totalSize / config->ftfxConfig[0].flashDesc.blockCount; + break; + case kFLASH_PropertyPflash0BlockCount: + *value = config->ftfxConfig[0].flashDesc.blockCount; + break; + case kFLASH_PropertyPflash0BlockBaseAddr: + *value = config->ftfxConfig[0].flashDesc.blockBase; + break; + case kFLASH_PropertyPflash0FacSupport: + *value = (uint32_t)config->ftfxConfig[0].flashDesc.feature.hasXaccControl; + break; + case kFLASH_PropertyPflash0AccessSegmentSize: + *value = config->ftfxConfig[0].flashDesc.accessSegmentMem.size; + break; + case kFLASH_PropertyPflash0AccessSegmentCount: + *value = config->ftfxConfig[0].flashDesc.accessSegmentMem.count; + break; + +#if FTFx_DRIVER_HAS_FLASH1_SUPPORT + case kFLASH_PropertyPflash1SectorSize: + *value = config->ftfxConfig[1].flashDesc.sectorSize; + break; + case kFLASH_PropertyPflash1TotalSize: + *value = config->ftfxConfig[1].flashDesc.totalSize; + break; + case kFLASH_PropertyPflash1BlockSize: + *value = config->ftfxConfig[1].flashDesc.totalSize / config->ftfxConfig[1].flashDesc.blockCount; + break; + case kFLASH_PropertyPflash1BlockCount: + *value = config->ftfxConfig[1].flashDesc.blockCount; + break; + case kFLASH_PropertyPflash1BlockBaseAddr: + *value = config->ftfxConfig[1].flashDesc.blockBase; + break; + case kFLASH_PropertyPflash1FacSupport: + *value = (uint32_t)config->ftfxConfig[1].flashDesc.feature.hasXaccControl; + break; + case kFLASH_PropertyPflash1AccessSegmentSize: + *value = config->ftfxConfig[1].flashDesc.accessSegmentMem.size; + break; + case kFLASH_PropertyPflash1AccessSegmentCount: + *value = config->ftfxConfig[1].flashDesc.accessSegmentMem.count; + break; +#endif + + case kFLASH_PropertyFlexRamBlockBaseAddr: + *value = config->ftfxConfig[0].flexramBlockBase; + break; + case kFLASH_PropertyFlexRamTotalSize: + *value = config->ftfxConfig[0].flexramTotalSize; + break; + + default: /* catch inputs that are not recognized */ + return kStatus_FTFx_UnknownProperty; + } + + return kStatus_FTFx_Success; +} + +static void flash_init_features(ftfx_config_t *config) +{ + if (config->flashDesc.index == 0) + { + config->flashDesc.feature.isIndBlock = 1; + config->flashDesc.feature.hasIndPfsizeReg = 1; + config->flashDesc.feature.hasIndProtReg = 1; + config->flashDesc.feature.hasIndXaccReg = 1; + } +#if FTFx_DRIVER_HAS_FLASH1_SUPPORT + else if (config->flashDesc.index == 1) + { + config->flashDesc.feature.isIndBlock = FTFx_FLASH1_IS_INDEPENDENT_BLOCK; + config->flashDesc.feature.hasIndPfsizeReg = config->flashDesc.feature.isIndBlock; + config->flashDesc.feature.hasIndProtReg = FTFx_FLASH1_HAS_INT_PROT_REG; + config->flashDesc.feature.hasIndXaccReg = FTFx_FLASH1_HAS_INT_XACC_REG; + } +#endif + + config->flashDesc.feature.hasProtControl = 1; + config->flashDesc.feature.hasXaccControl = FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL; +} + +static uint32_t flash_calculate_mem_size(uint32_t pflashBlockCount, + uint32_t pflashBlockSize, + uint32_t pfsizeMask, + uint32_t pfsizeShift) +{ + uint8_t pfsize; + uint32_t flashDensity; + + /* PFSIZE=0xf means that on customer parts the IFR was not correctly programmed. + * We just use the pre-defined flash size in feature file here to support pre-production parts */ + pfsize = (SIM_FCFG1_REG & pfsizeMask) >> pfsizeShift; + if (pfsize == 0xf) + { + flashDensity = pflashBlockCount * pflashBlockSize; + } + else + { + flashDensity = ((uint32_t)kPFlashDensities[pfsize]) << 10; + } + + return flashDensity; +} + +static uint32_t flash_calculate_prot_segment_size(uint32_t flashSize, uint32_t segmentCount) +{ + uint32_t segmentSize; + + /* Calculate the size of the flash protection region + * If the flash density is > 32KB, then protection region is 1/32 of total flash density + * Else if flash density is < 32KB, then flash protection region is set to 1KB */ + if (flashSize > segmentCount * kFTFx_MinProtectBlockSize) + { + segmentSize = flashSize / segmentCount; + } + else + { + segmentSize = kFTFx_MinProtectBlockSize; + } + + return segmentSize; +} + +static status_t flash_check_range_to_get_index(flash_config_t *config, uint32_t start, uint32_t lengthInBytes, uint8_t *flashIndex) +{ + if (config == NULL) + { + return kStatus_FTFx_InvalidArgument; + } + + /* Validates the range of the given address */ + for (uint8_t index = 0; index < FTFx_FLASH_COUNT; index++) + { + if ((start >= config->ftfxConfig[index].flashDesc.blockBase) && + ((start + lengthInBytes) <= (config->ftfxConfig[index].flashDesc.blockBase + config->ftfxConfig[index].flashDesc.totalSize))) + { + *flashIndex = config->ftfxConfig[index].flashDesc.index; + return kStatus_FTFx_Success; + } + } + + return kStatus_FTFx_AddressError; +} + +static status_t flash_convert_start_address(ftfx_config_t *config, uint32_t start) +{ + if (config == NULL) + { + return kStatus_FTFx_InvalidArgument; + } + + if (config->flashDesc.index && config->flashDesc.feature.isIndBlock) + { + /* When required by the command, address bit 23 selects between main flash memory + * (=0) and secondary flash memory (=1).*/ + config->opsConfig.convertedAddress = start - config->flashDesc.blockBase + 0x800000U; + } + else + { + config->opsConfig.convertedAddress = start; + } + + return kStatus_FTFx_Success; +} + +#if defined(FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP) && FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP +/*! @brief Validates the gived address to see if it is equal to swap indicator address in pflash swap IFR.*/ +static status_t flash_validate_swap_indicator_address(ftfx_config_t *config, uint32_t address) +{ + status_t returnCode; + struct _flash_swap_ifr_field_config + { + uint16_t swapIndicatorAddress; /*!< A Swap indicator address field.*/ + uint16_t swapEnableWord; /*!< A Swap enable word field.*/ + uint8_t reserved0[4]; /*!< A reserved field.*/ + uint8_t reserved1[2]; /*!< A reserved field.*/ + uint16_t swapDisableWord; /*!< A Swap disable word field.*/ + uint8_t reserved2[4]; /*!< A reserved field.*/ + } flashSwapIfrFieldData; + uint32_t swapIndicatorAddress; + +#if defined(FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD) && FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD + returnCode = + FTFx_CMD_ReadResource(config, config->ifrDesc.resRange.pflashSwapIfrStart, (uint8_t *)&flashSwapIfrFieldData, + sizeof(flashSwapIfrFieldData), kFTFx_ResourceOptionFlashIfr); + + if (returnCode != kStatus_FTFx_Success) + { + return returnCode; + } +#else + { + /* From RM, the actual info are stored in FCCOB6,7 */ + uint32_t returnValue[2]; + returnCode = FTFx_CMD_ReadOnce(config, kFLASH_RecordIndexSwapAddr, (uint8_t *)returnValue, 4); + if (returnCode != kStatus_FTFx_Success) + { + return returnCode; + } + flashSwapIfrFieldData.swapIndicatorAddress = (uint16_t)returnValue[0]; + returnCode = FTFx_CMD_ReadOnce(config, kFLASH_RecordIndexSwapEnable, (uint8_t *)returnValue, 4); + if (returnCode != kStatus_FTFx_Success) + { + return returnCode; + } + flashSwapIfrFieldData.swapEnableWord = (uint16_t)returnValue[0]; + returnCode = FTFx_CMD_ReadOnce(config, kFLASH_RecordIndexSwapDisable, (uint8_t *)returnValue, 4); + if (returnCode != kStatus_FTFx_Success) + { + return returnCode; + } + flashSwapIfrFieldData.swapDisableWord = (uint16_t)returnValue[0]; + } +#endif + + /* The high bits value of Swap Indicator Address is stored in Program Flash Swap IFR Field, + * the low severval bit value of Swap Indicator Address is always 1'b0 */ + swapIndicatorAddress = (uint32_t)flashSwapIfrFieldData.swapIndicatorAddress * + config->opsConfig.addrAligment.swapCtrlCmd; + if (address != swapIndicatorAddress) + { + return kStatus_FTFx_SwapIndicatorAddressError; + } + + return returnCode; +} +#endif /* FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP */ + diff --git a/ext/hal/nxp/mcux/drivers/kinetis/fsl_ftfx_flash.h b/ext/hal/nxp/mcux/drivers/kinetis/fsl_ftfx_flash.h new file mode 100644 index 00000000000..0cde8b84967 --- /dev/null +++ b/ext/hal/nxp/mcux/drivers/kinetis/fsl_ftfx_flash.h @@ -0,0 +1,611 @@ +/* +* Copyright 2013-2016 Freescale Semiconductor, Inc. +* Copyright 2016-2018 NXP +* All rights reserved. +* +* SPDX-License-Identifier: BSD-3-Clause +* +*/ + +#ifndef _FSL_FTFX_FLASH_H_ +#define _FSL_FTFX_FLASH_H_ + +#include "fsl_ftfx_controller.h" + +/*! + * @addtogroup ftfx_flash_driver + * @{ + */ +/******************************************************************************* + * Definitions + ******************************************************************************/ +#define kStatus_FLASH_Success kStatus_FTFx_Success +#define kFLASH_ApiEraseKey kFTFx_ApiEraseKey + +/*! + * @name Flash version + * @{ + */ +/*! @brief Flash driver version for SDK*/ +#define FSL_FLASH_DRIVER_VERSION (MAKE_VERSION(3, 0, 0)) /*!< Version 3.0.0. */ + +/*! @brief Flash driver version for ROM*/ +enum _flash_driver_version_constants +{ + kFLASH_DriverVersionName = 'F', /*!< Flash driver version name.*/ + kFLASH_DriverVersionMajor = 3, /*!< Major flash driver version.*/ + kFLASH_DriverVersionMinor = 0, /*!< Minor flash driver version.*/ + kFLASH_DriverVersionBugfix = 0 /*!< Bugfix for flash driver version.*/ +}; +/*@}*/ + +/*! + * @brief Enumeration for the three possible flash protection levels. + */ +typedef enum _flash_protection_state +{ + kFLASH_ProtectionStateUnprotected, /*!< Flash region is not protected.*/ + kFLASH_ProtectionStateProtected, /*!< Flash region is protected.*/ + kFLASH_ProtectionStateMixed /*!< Flash is mixed with protected and unprotected region.*/ +} flash_prot_state_t; + +/*! + * @brief Enumeration for the three possible flash execute access levels. + */ +typedef enum _flash_execute_only_access_state +{ + kFLASH_AccessStateUnLimited, /*!< Flash region is unlimited.*/ + kFLASH_AccessStateExecuteOnly, /*!< Flash region is execute only.*/ + kFLASH_AccessStateMixed /*!< Flash is mixed with unlimited and execute only region.*/ +} flash_xacc_state_t; + +/*! + * @brief PFlash protection status + */ +typedef union _pflash_protection_status +{ + uint32_t protl; /*!< PROT[31:0] .*/ + uint32_t proth; /*!< PROT[63:32].*/ + uint8_t protsl; /*!< PROTS[7:0] .*/ + uint8_t protsh; /*!< PROTS[15:8] .*/ + uint8_t reserved[2]; +} pflash_prot_status_t; + +/*! + * @brief Enumeration for various flash properties. + */ +typedef enum _flash_property_tag +{ + kFLASH_PropertyPflash0SectorSize = 0x00U, /*!< Pflash sector size property.*/ + kFLASH_PropertyPflash0TotalSize = 0x01U, /*!< Pflash total size property.*/ + kFLASH_PropertyPflash0BlockSize = 0x02U, /*!< Pflash block size property.*/ + kFLASH_PropertyPflash0BlockCount = 0x03U, /*!< Pflash block count property.*/ + kFLASH_PropertyPflash0BlockBaseAddr = 0x04U, /*!< Pflash block base address property.*/ + kFLASH_PropertyPflash0FacSupport = 0x05U, /*!< Pflash fac support property.*/ + kFLASH_PropertyPflash0AccessSegmentSize = 0x06U, /*!< Pflash access segment size property.*/ + kFLASH_PropertyPflash0AccessSegmentCount = 0x07U, /*!< Pflash access segment count property.*/ + + kFLASH_PropertyPflash1SectorSize = 0x10U, /*!< Pflash sector size property.*/ + kFLASH_PropertyPflash1TotalSize = 0x11U, /*!< Pflash total size property.*/ + kFLASH_PropertyPflash1BlockSize = 0x12U, /*!< Pflash block size property.*/ + kFLASH_PropertyPflash1BlockCount = 0x13U, /*!< Pflash block count property.*/ + kFLASH_PropertyPflash1BlockBaseAddr = 0x14U, /*!< Pflash block base address property.*/ + kFLASH_PropertyPflash1FacSupport = 0x15U, /*!< Pflash fac support property.*/ + kFLASH_PropertyPflash1AccessSegmentSize = 0x16U, /*!< Pflash access segment size property.*/ + kFLASH_PropertyPflash1AccessSegmentCount = 0x17U, /*!< Pflash access segment count property.*/ + + kFLASH_PropertyFlexRamBlockBaseAddr = 0x20U, /*!< FlexRam block base address property.*/ + kFLASH_PropertyFlexRamTotalSize = 0x21U, /*!< FlexRam total size property.*/ +} flash_property_tag_t; + +/*! @brief Flash driver state information. + * + * An instance of this structure is allocated by the user of the flash driver and + * passed into each of the driver APIs. + */ +typedef struct _flash_config +{ + ftfx_config_t ftfxConfig[FTFx_FLASH_COUNT]; +} flash_config_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name Initialization + * @{ + */ + +/*! + * @brief Initializes the global flash properties structure members. + * + * This function checks and initializes the Flash module for the other Flash APIs. + * + * @param config Pointer to the storage for the driver runtime state. + * + * @retval #kStatus_FTFx_Success API was executed successfully. + * @retval #kStatus_FTFx_InvalidArgument An invalid argument is provided. + * @retval #kStatus_FTFx_ExecuteInRamFunctionNotReady Execute-in-RAM function is not available. + * @retval #kStatus_FTFx_PartitionStatusUpdateFailure Failed to update the partition status. + */ +status_t FLASH_Init(flash_config_t *config); + +/*@}*/ + +/*! + * @name Erasing + * @{ + */ + +/*! + * @brief Erases the Dflash sectors encompassed by parameters passed into function. + * + * This function erases the appropriate number of flash sectors based on the + * desired start address and length. + * + * @param config The pointer to the storage for the driver runtime state. + * @param start The start address of the desired flash memory to be erased. + * The start address does not need to be sector-aligned but must be word-aligned. + * @param lengthInBytes The length, given in bytes (not words or long-words) + * to be erased. Must be word-aligned. + * @param key The value used to validate all flash erase APIs. + * + * @retval #kStatus_FTFx_Success API was executed successfully. + * @retval #kStatus_FTFx_InvalidArgument An invalid argument is provided. + * @retval #kStatus_FTFx_AlignmentError The parameter is not aligned with the specified baseline. + * @retval #kStatus_FTFx_AddressError The address is out of range. + * @retval #kStatus_FTFx_EraseKeyError The API erase key is invalid. + * @retval #kStatus_FTFx_ExecuteInRamFunctionNotReady Execute-in-RAM function is not available. + * @retval #kStatus_FTFx_AccessError Invalid instruction codes and out-of bounds addresses. + * @retval #kStatus_FTFx_ProtectionViolation The program/erase operation is requested to execute on protected areas. + * @retval #kStatus_FTFx_CommandFailure Run-time error during the command execution. + */ +status_t FLASH_Erase(flash_config_t *config, + uint32_t start, + uint32_t lengthInBytes, + uint32_t key); + +/*! + * @brief Erases entire flexnvm + * + * @param config Pointer to the storage for the driver runtime state. + * @param key A value used to validate all flash erase APIs. + * + * @retval #kStatus_FTFx_Success API was executed successfully. + * @retval #kStatus_FTFx_InvalidArgument An invalid argument is provided. + * @retval #kStatus_FTFx_EraseKeyError API erase key is invalid. + * @retval #kStatus_FTFx_ExecuteInRamFunctionNotReady Execute-in-RAM function is not available. + * @retval #kStatus_FTFx_AccessError Invalid instruction codes and out-of bounds addresses. + * @retval #kStatus_FTFx_ProtectionViolation The program/erase operation is requested to execute on protected areas. + * @retval #kStatus_FTFx_CommandFailure Run-time error during command execution. + * @retval #kStatus_FTFx_PartitionStatusUpdateFailure Failed to update the partition status. + */ +status_t FLASH_EraseAll(flash_config_t *config, uint32_t key); + +/*! + * @brief Erases the entire flexnvm, including protected sectors. + * + * @param config Pointer to the storage for the driver runtime state. + * @param key A value used to validate all flash erase APIs. + * + * @retval #kStatus_FTFx_Success API was executed successfully. + * @retval #kStatus_FTFx_InvalidArgument An invalid argument is provided. + * @retval #kStatus_FTFx_EraseKeyError API erase key is invalid. + * @retval #kStatus_FTFx_ExecuteInRamFunctionNotReady Execute-in-RAM function is not available. + * @retval #kStatus_FTFx_AccessError Invalid instruction codes and out-of bounds addresses. + * @retval #kStatus_FTFx_ProtectionViolation The program/erase operation is requested to execute on protected areas. + * @retval #kStatus_FTFx_CommandFailure Run-time error during command execution. + * @retval #kStatus_FTFx_PartitionStatusUpdateFailure Failed to update the partition status. + */ +#if defined(FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_UNSECURE_CMD) && FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_UNSECURE_CMD +status_t FLASH_EraseAllUnsecure(flash_config_t *config, uint32_t key); +#endif + +/*@}*/ + +/*! + * @name Programming + * @{ + */ + +/*! + * @brief Programs flash with data at locations passed in through parameters. + * + * This function programs the flash memory with the desired data for a given + * flash area as determined by the start address and the length. + * + * @param config A pointer to the storage for the driver runtime state. + * @param start The start address of the desired flash memory to be programmed. Must be + * word-aligned. + * @param src A pointer to the source buffer of data that is to be programmed + * into the flash. + * @param lengthInBytes The length, given in bytes (not words or long-words), + * to be programmed. Must be word-aligned. + * + * @retval #kStatus_FTFx_Success API was executed successfully. + * @retval #kStatus_FTFx_InvalidArgument An invalid argument is provided. + * @retval #kStatus_FTFx_AlignmentError Parameter is not aligned with the specified baseline. + * @retval #kStatus_FTFx_AddressError Address is out of range. + * @retval #kStatus_FTFx_ExecuteInRamFunctionNotReady Execute-in-RAM function is not available. + * @retval #kStatus_FTFx_AccessError Invalid instruction codes and out-of bounds addresses. + * @retval #kStatus_FTFx_ProtectionViolation The program/erase operation is requested to execute on protected areas. + * @retval #kStatus_FTFx_CommandFailure Run-time error during the command execution. + */ +status_t FLASH_Program(flash_config_t *config, + uint32_t start, + uint8_t *src, + uint32_t lengthInBytes); + +/*! + * @brief Programs flash with data at locations passed in through parameters via the Program Section command. + * + * This function programs the flash memory with the desired data for a given + * flash area as determined by the start address and length. + * + * @param config A pointer to the storage for the driver runtime state. + * @param start The start address of the desired flash memory to be programmed. Must be + * word-aligned. + * @param src A pointer to the source buffer of data that is to be programmed + * into the flash. + * @param lengthInBytes The length, given in bytes (not words or long-words), + * to be programmed. Must be word-aligned. + * + * @retval #kStatus_FTFx_Success API was executed successfully. + * @retval #kStatus_FTFx_InvalidArgument An invalid argument is provided. + * @retval #kStatus_FTFx_AlignmentError Parameter is not aligned with specified baseline. + * @retval #kStatus_FTFx_AddressError Address is out of range. + * @retval #kStatus_FTFx_SetFlexramAsRamError Failed to set flexram as RAM. + * @retval #kStatus_FTFx_ExecuteInRamFunctionNotReady Execute-in-RAM function is not available. + * @retval #kStatus_FTFx_AccessError Invalid instruction codes and out-of bounds addresses. + * @retval #kStatus_FTFx_ProtectionViolation The program/erase operation is requested to execute on protected areas. + * @retval #kStatus_FTFx_CommandFailure Run-time error during command execution. + * @retval #kStatus_FTFx_RecoverFlexramAsEepromError Failed to recover FlexRAM as EEPROM. + */ +#if defined(FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD) && FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD +status_t FLASH_ProgramSection(flash_config_t *config, + uint32_t start, + uint8_t *src, + uint32_t lengthInBytes); +#endif + +/*@}*/ + +/*! + * @name Reading + * @{ + */ + +/*! + * @brief Reads the resource with data at locations passed in through parameters. + * + * This function reads the flash memory with the desired location for a given + * flash area as determined by the start address and length. + * + * @param config A pointer to the storage for the driver runtime state. + * @param start The start address of the desired flash memory to be programmed. Must be + * word-aligned. + * @param dst A pointer to the destination buffer of data that is used to store + * data to be read. + * @param lengthInBytes The length, given in bytes (not words or long-words), + * to be read. Must be word-aligned. + * @param option The resource option which indicates which area should be read back. + * + * @retval #kStatus_FTFx_Success API was executed successfully. + * @retval #kStatus_FTFx_InvalidArgument An invalid argument is provided. + * @retval #kStatus_FTFx_AlignmentError Parameter is not aligned with the specified baseline. + * @retval #kStatus_FTFx_ExecuteInRamFunctionNotReady Execute-in-RAM function is not available. + * @retval #kStatus_FTFx_AccessError Invalid instruction codes and out-of bounds addresses. + * @retval #kStatus_FTFx_ProtectionViolation The program/erase operation is requested to execute on protected areas. + * @retval #kStatus_FTFx_CommandFailure Run-time error during the command execution. + */ +#if defined(FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD) && FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD +status_t FLASH_ReadResource(flash_config_t *config, + uint32_t start, + uint8_t *dst, + uint32_t lengthInBytes, + ftfx_read_resource_opt_t option); +#endif + +/*@}*/ + +/*! + * @name Verification + * @{ + */ + +/*! + * @brief Verifies an erasure of the desired flash area at a specified margin level. + * + * This function checks the appropriate number of flash sectors based on + * the desired start address and length to check whether the flash is erased + * to the specified read margin level. + * + * @param config A pointer to the storage for the driver runtime state. + * @param start The start address of the desired flash memory to be verified. + * The start address does not need to be sector-aligned but must be word-aligned. + * @param lengthInBytes The length, given in bytes (not words or long-words), + * to be verified. Must be word-aligned. + * @param margin Read margin choice. + * + * @retval #kStatus_FTFx_Success API was executed successfully. + * @retval #kStatus_FTFx_InvalidArgument An invalid argument is provided. + * @retval #kStatus_FTFx_AlignmentError Parameter is not aligned with specified baseline. + * @retval #kStatus_FTFx_AddressError Address is out of range. + * @retval #kStatus_FTFx_ExecuteInRamFunctionNotReady Execute-in-RAM function is not available. + * @retval #kStatus_FTFx_AccessError Invalid instruction codes and out-of bounds addresses. + * @retval #kStatus_FTFx_ProtectionViolation The program/erase operation is requested to execute on protected areas. + * @retval #kStatus_FTFx_CommandFailure Run-time error during the command execution. + */ +status_t FLASH_VerifyErase(flash_config_t *config, + uint32_t start, + uint32_t lengthInBytes, + ftfx_margin_value_t margin); + +/*! + * @brief Verifies erasure of the entire flash at a specified margin level. + * + * This function checks whether the flash is erased to the + * specified read margin level. + * + * @param config A pointer to the storage for the driver runtime state. + * @param margin Read margin choice. + * + * @retval #kStatus_FTFx_Success API was executed successfully. + * @retval #kStatus_FTFx_InvalidArgument An invalid argument is provided. + * @retval #kStatus_FTFx_ExecuteInRamFunctionNotReady Execute-in-RAM function is not available. + * @retval #kStatus_FTFx_AccessError Invalid instruction codes and out-of bounds addresses. + * @retval #kStatus_FTFx_ProtectionViolation The program/erase operation is requested to execute on protected areas. + * @retval #kStatus_FTFx_CommandFailure Run-time error during the command execution. + */ +status_t FLASH_VerifyEraseAll(flash_config_t *config, ftfx_margin_value_t margin); + +/*! + * @brief Verifies programming of the desired flash area at a specified margin level. + * + * This function verifies the data programmed in the flash memory using the + * Flash Program Check Command and compares it to the expected data for a given + * flash area as determined by the start address and length. + * + * @param config A pointer to the storage for the driver runtime state. + * @param start The start address of the desired flash memory to be verified. Must be word-aligned. + * @param lengthInBytes The length, given in bytes (not words or long-words), + * to be verified. Must be word-aligned. + * @param expectedData A pointer to the expected data that is to be + * verified against. + * @param margin Read margin choice. + * @param failedAddress A pointer to the returned failing address. + * @param failedData A pointer to the returned failing data. Some derivatives do + * not include failed data as part of the FCCOBx registers. In this + * case, zeros are returned upon failure. + * + * @retval #kStatus_FTFx_Success API was executed successfully. + * @retval #kStatus_FTFx_InvalidArgument An invalid argument is provided. + * @retval #kStatus_FTFx_AlignmentError Parameter is not aligned with specified baseline. + * @retval #kStatus_FTFx_AddressError Address is out of range. + * @retval #kStatus_FTFx_ExecuteInRamFunctionNotReady Execute-in-RAM function is not available. + * @retval #kStatus_FTFx_AccessError Invalid instruction codes and out-of bounds addresses. + * @retval #kStatus_FTFx_ProtectionViolation The program/erase operation is requested to execute on protected areas. + * @retval #kStatus_FTFx_CommandFailure Run-time error during the command execution. + */ +status_t FLASH_VerifyProgram(flash_config_t *config, + uint32_t start, + uint32_t lengthInBytes, + const uint8_t *expectedData, + ftfx_margin_value_t margin, + uint32_t *failedAddress, + uint32_t *failedData); + +/*@}*/ + +/*! + * @name Security + * @{ + */ + +/*! + * @brief Returns the security state via the pointer passed into the function. + * + * This function retrieves the current flash security status, including the + * security enabling state and the backdoor key enabling state. + * + * @param config A pointer to storage for the driver runtime state. + * @param state A pointer to the value returned for the current security status code: + * + * @retval #kStatus_FTFx_Success API was executed successfully. + * @retval #kStatus_FTFx_InvalidArgument An invalid argument is provided. + */ +status_t FLASH_GetSecurityState(flash_config_t *config, ftfx_security_state_t *state); + +/*! + * @brief Allows users to bypass security with a backdoor key. + * + * If the MCU is in secured state, this function unsecures the MCU by + * comparing the provided backdoor key with ones in the flash configuration + * field. + * + * @param config A pointer to the storage for the driver runtime state. + * @param backdoorKey A pointer to the user buffer containing the backdoor key. + * + * @retval #kStatus_FTFx_Success API was executed successfully. + * @retval #kStatus_FTFx_InvalidArgument An invalid argument is provided. + * @retval #kStatus_FTFx_ExecuteInRamFunctionNotReady Execute-in-RAM function is not available. + * @retval #kStatus_FTFx_AccessError Invalid instruction codes and out-of bounds addresses. + * @retval #kStatus_FTFx_ProtectionViolation The program/erase operation is requested to execute on protected areas. + * @retval #kStatus_FTFx_CommandFailure Run-time error during the command execution. + */ +status_t FLASH_SecurityBypass(flash_config_t *config, const uint8_t *backdoorKey); + +/*@}*/ + +/*! + * @name FlexRAM + * @{ + */ + +/*! + * @brief Sets the FlexRAM function command. + * + * @param config A pointer to the storage for the driver runtime state. + * @param option The option used to set the work mode of FlexRAM. + * + * @retval #kStatus_FTFx_Success API was executed successfully. + * @retval #kStatus_FTFx_InvalidArgument An invalid argument is provided. + * @retval #kStatus_FTFx_ExecuteInRamFunctionNotReady Execute-in-RAM function is not available. + * @retval #kStatus_FTFx_AccessError Invalid instruction codes and out-of bounds addresses. + * @retval #kStatus_FTFx_ProtectionViolation The program/erase operation is requested to execute on protected areas. + * @retval #kStatus_FTFx_CommandFailure Run-time error during the command execution. + */ +#if defined(FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD) && FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD +status_t FLASH_SetFlexramFunction(flash_config_t *config, ftfx_flexram_func_opt_t option); +#endif + +/*@}*/ + +/*! + * @name Swap + * @{ + */ + +/*! + * @brief Swaps the lower half flash with the higher half flash. + * + * @param config A pointer to the storage for the driver runtime state. + * @param address Address used to configure the flash swap function + * @param isSetEnable The possible option used to configure the Flash Swap function or check the flash Swap status. + * + * @retval #kStatus_FTFx_Success API was executed successfully. + * @retval #kStatus_FTFx_InvalidArgument An invalid argument is provided. + * @retval #kStatus_FTFx_AlignmentError Parameter is not aligned with specified baseline. + * @retval #kStatus_FTFx_SwapIndicatorAddressError Swap indicator address is invalid. + * @retval #kStatus_FTFx_ExecuteInRamFunctionNotReady Execute-in-RAM function is not available. + * @retval #kStatus_FTFx_AccessError Invalid instruction codes and out-of bounds addresses. + * @retval #kStatus_FTFx_ProtectionViolation The program/erase operation is requested to execute on protected areas. + * @retval #kStatus_FTFx_CommandFailure Run-time error during command execution. + * @retval #kStatus_FTFx_SwapSystemNotInUninitialized Swap system is not in an uninitialized state. + */ +#if defined(FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP) && FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP +status_t FLASH_Swap(flash_config_t *config, uint32_t address, bool isSetEnable); +#endif + +/*@}*/ + +/*! + * @name Protection + * @{ + */ + +/*! + * @brief Returns the protection state of the desired flash area via the pointer passed into the function. + * + * This function retrieves the current flash protect status for a given + * flash area as determined by the start address and length. + * + * @param config A pointer to the storage for the driver runtime state. + * @param start The start address of the desired flash memory to be checked. Must be word-aligned. + * @param lengthInBytes The length, given in bytes (not words or long-words) + * to be checked. Must be word-aligned. + * @param protection_state A pointer to the value returned for the current + * protection status code for the desired flash area. + * + * @retval #kStatus_FTFx_Success API was executed successfully. + * @retval #kStatus_FTFx_InvalidArgument An invalid argument is provided. + * @retval #kStatus_FTFx_AlignmentError Parameter is not aligned with specified baseline. + * @retval #kStatus_FTFx_AddressError The address is out of range. + */ +status_t FLASH_IsProtected(flash_config_t *config, + uint32_t start, + uint32_t lengthInBytes, + flash_prot_state_t *protection_state); + +/*! + * @brief Returns the access state of the desired flash area via the pointer passed into the function. + * + * This function retrieves the current flash access status for a given + * flash area as determined by the start address and length. + * + * @param config A pointer to the storage for the driver runtime state. + * @param start The start address of the desired flash memory to be checked. Must be word-aligned. + * @param lengthInBytes The length, given in bytes (not words or long-words), + * to be checked. Must be word-aligned. + * @param access_state A pointer to the value returned for the current + * access status code for the desired flash area. + * + * @retval #kStatus_FTFx_Success API was executed successfully. + * @retval #kStatus_FTFx_InvalidArgument An invalid argument is provided. + * @retval #kStatus_FTFx_AlignmentError The parameter is not aligned to the specified baseline. + * @retval #kStatus_FTFx_AddressError The address is out of range. + */ +status_t FLASH_IsExecuteOnly(flash_config_t *config, + uint32_t start, + uint32_t lengthInBytes, + flash_xacc_state_t *access_state); + +/*! + * @brief Sets the PFlash Protection to the intended protection status. + * + * @param config A pointer to storage for the driver runtime state. + * @param protectStatus The expected protect status to set to the PFlash protection register. Each bit is + * corresponding to protection of 1/32(64) of the total PFlash. The least significant bit is corresponding to the lowest + * address area of PFlash. The most significant bit is corresponding to the highest address area of PFlash. There are + * two possible cases as shown below: + * 0: this area is protected. + * 1: this area is unprotected. + * + * @retval #kStatus_FTFx_Success API was executed successfully. + * @retval #kStatus_FTFx_InvalidArgument An invalid argument is provided. + * @retval #kStatus_FTFx_CommandFailure Run-time error during command execution. + */ +status_t FLASH_PflashSetProtection(flash_config_t *config, pflash_prot_status_t *protectStatus); + +/*! + * @brief Gets the PFlash protection status. + * + * @param config A pointer to the storage for the driver runtime state. + * @param protectStatus Protect status returned by the PFlash IP. Each bit is corresponding to the protection of + * 1/32(64) + * of the + * total PFlash. The least significant bit corresponds to the lowest address area of the PFlash. The most significant + * bit corresponds to the highest address area of PFlash. There are two possible cases as shown below: + * 0: this area is protected. + * 1: this area is unprotected. + * + * @retval #kStatus_FTFx_Success API was executed successfully. + * @retval #kStatus_FTFx_InvalidArgument An invalid argument is provided. + */ +status_t FLASH_PflashGetProtection(flash_config_t *config, pflash_prot_status_t *protectStatus); + +/*@}*/ + +/*! + * @name Properties + * @{ + */ + +/*! + * @brief Returns the desired flash property. + * + * @param config A pointer to the storage for the driver runtime state. + * @param whichProperty The desired property from the list of properties in + * enum flash_property_tag_t + * @param value A pointer to the value returned for the desired flash property. + * + * @retval #kStatus_FTFx_Success API was executed successfully. + * @retval #kStatus_FTFx_InvalidArgument An invalid argument is provided. + * @retval #kStatus_FTFx_UnknownProperty An unknown property tag. + */ +status_t FLASH_GetProperty(flash_config_t *config, flash_property_tag_t whichProperty, uint32_t *value); + +/*@}*/ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* _FSL_FTFX_FLASH_H_ */ diff --git a/ext/hal/nxp/mcux/drivers/kinetis/fsl_ftfx_flexnvm.c b/ext/hal/nxp/mcux/drivers/kinetis/fsl_ftfx_flexnvm.c new file mode 100644 index 00000000000..ff4d2604e06 --- /dev/null +++ b/ext/hal/nxp/mcux/drivers/kinetis/fsl_ftfx_flexnvm.c @@ -0,0 +1,410 @@ +/* +* Copyright 2013-2016 Freescale Semiconductor, Inc. +* Copyright 2016-2018 NXP +* All rights reserved. +* +* SPDX-License-Identifier: BSD-3-Clause +* +*/ + +#include "fsl_ftfx_flexnvm.h" + +#if FSL_FEATURE_FLASH_HAS_FLEX_NVM + +/******************************************************************************* + * Definitions + ******************************************************************************/ + + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/*! @brief Convert address for Flexnvm dflash.*/ +static status_t flexnvm_convert_start_address(flexnvm_config_t *config, uint32_t start); + +/******************************************************************************* + * Variables + ******************************************************************************/ + + +/******************************************************************************* + * Code + ******************************************************************************/ + +status_t FLEXNVM_Init(flexnvm_config_t *config) +{ + status_t returnCode; + + if (config == NULL) + { + return kStatus_FTFx_InvalidArgument; + } + + config->ftfxConfig.flashDesc.type = kFTFx_MemTypeFlexnvm; + config->ftfxConfig.flashDesc.index = 0; + + /* Set Flexnvm memory operation parameters */ + config->ftfxConfig.opsConfig.addrAligment.blockWriteUnitSize = FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_WRITE_UNIT_SIZE; + config->ftfxConfig.opsConfig.addrAligment.sectorCmd = FSL_FEATURE_FLASH_FLEX_NVM_SECTOR_CMD_ADDRESS_ALIGMENT; + config->ftfxConfig.opsConfig.addrAligment.sectionCmd = FSL_FEATURE_FLASH_FLEX_NVM_SECTION_CMD_ADDRESS_ALIGMENT; + config->ftfxConfig.opsConfig.addrAligment.resourceCmd = FSL_FEATURE_FLASH_FLEX_NVM_RESOURCE_CMD_ADDRESS_ALIGMENT; + config->ftfxConfig.opsConfig.addrAligment.checkCmd = FSL_FEATURE_FLASH_FLEX_NVM_CHECK_CMD_ADDRESS_ALIGMENT; + + /* Set Flexnvm memory properties */ + config->ftfxConfig.flashDesc.blockBase = FSL_FEATURE_FLASH_FLEX_NVM_START_ADDRESS; + config->ftfxConfig.flashDesc.sectorSize = FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SECTOR_SIZE; + config->ftfxConfig.flashDesc.blockCount = FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_COUNT; + + /* Init FTFx Kernel */ + returnCode = FTFx_API_Init(&config->ftfxConfig); + if (returnCode != kStatus_FTFx_Success) + { + return returnCode; + } + + returnCode = FTFx_API_UpdateFlexnvmPartitionStatus(&config->ftfxConfig); + if (returnCode != kStatus_FTFx_Success) + { + return returnCode; + } + + return kStatus_FTFx_Success; +} + +status_t FLEXNVM_DflashErase(flexnvm_config_t *config, uint32_t start, uint32_t lengthInBytes, uint32_t key) +{ + status_t returnCode; + returnCode = flexnvm_convert_start_address(config, start); + if (returnCode != kStatus_FTFx_Success) + { + return returnCode; + } + + return FTFx_CMD_Erase(&config->ftfxConfig, start, lengthInBytes, key); +} + +status_t FLEXNVM_EraseAll(flexnvm_config_t *config, uint32_t key) +{ + return FTFx_CMD_EraseAll(&config->ftfxConfig, key); +} + +#if defined(FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_UNSECURE_CMD) && FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_UNSECURE_CMD +status_t FLEXNVM_EraseAllUnsecure(flexnvm_config_t *config, uint32_t key) +{ + return FTFx_CMD_EraseAllUnsecure(&config->ftfxConfig, key); +} +#endif + +status_t FLEXNVM_DflashProgram(flexnvm_config_t *config, uint32_t start, uint8_t *src, uint32_t lengthInBytes) +{ + status_t returnCode; + returnCode = flexnvm_convert_start_address(config, start); + if (returnCode != kStatus_FTFx_Success) + { + return returnCode; + } + + return FTFx_CMD_Program(&config->ftfxConfig, start, src, lengthInBytes); +} + +#if defined(FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD) && FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD +status_t FLEXNVM_DflashProgramSection(flexnvm_config_t *config, uint32_t start, uint8_t *src, uint32_t lengthInBytes) +{ + status_t returnCode; + returnCode = flexnvm_convert_start_address(config, start); + if (returnCode != kStatus_FTFx_Success) + { + return returnCode; + } + + return FTFx_CMD_ProgramSection(&config->ftfxConfig, start, src, lengthInBytes); +} +#endif + +status_t FLEXNVM_ProgramPartition(flexnvm_config_t *config, + ftfx_partition_flexram_load_opt_t option, + uint32_t eepromDataSizeCode, + uint32_t flexnvmPartitionCode) +{ + return FTFx_CMD_ProgramPartition(&config->ftfxConfig, option, eepromDataSizeCode, flexnvmPartitionCode); +} + +#if defined(FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD) && FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD +status_t FLEXNVM_ReadResource(flexnvm_config_t *config, + uint32_t start, + uint8_t *dst, + uint32_t lengthInBytes, + ftfx_read_resource_opt_t option) +{ + return FTFx_CMD_ReadResource(&config->ftfxConfig, start, dst, lengthInBytes, option); +} +#endif + +status_t FLEXNVM_DflashVerifyErase(flexnvm_config_t *config, uint32_t start, uint32_t lengthInBytes, ftfx_margin_value_t margin) +{ + status_t returnCode; + returnCode = flexnvm_convert_start_address(config, start); + if (returnCode != kStatus_FTFx_Success) + { + return returnCode; + } + + return FTFx_CMD_VerifyErase(&config->ftfxConfig, start, lengthInBytes, margin); +} + +status_t FLEXNVM_VerifyEraseAll(flexnvm_config_t *config, ftfx_margin_value_t margin) +{ + return FTFx_CMD_VerifyEraseAll(&config->ftfxConfig, margin); +} + +status_t FLEXNVM_DflashVerifyProgram(flexnvm_config_t *config, + uint32_t start, + uint32_t lengthInBytes, + const uint8_t *expectedData, + ftfx_margin_value_t margin, + uint32_t *failedAddress, + uint32_t *failedData) +{ + status_t returnCode; + returnCode = flexnvm_convert_start_address(config, start); + if (returnCode != kStatus_FTFx_Success) + { + return returnCode; + } + + return FTFx_CMD_VerifyProgram(&config->ftfxConfig, start, lengthInBytes, expectedData, margin, failedAddress, failedData); +} + +status_t FLEXNVM_GetSecurityState(flexnvm_config_t *config, ftfx_security_state_t *state) +{ + return FTFx_REG_GetSecurityState(&config->ftfxConfig, state); +} + +status_t FLEXNVM_SecurityBypass(flexnvm_config_t *config, const uint8_t *backdoorKey) +{ + return FTFx_CMD_SecurityBypass(&config->ftfxConfig, backdoorKey); +} + +#if defined(FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD) && FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD +status_t FLEXNVM_SetFlexramFunction(flexnvm_config_t *config, ftfx_flexram_func_opt_t option) +{ + return FTFx_CMD_SetFlexramFunction(&config->ftfxConfig, option); +} +#endif + +status_t FLEXNVM_EepromWrite(flexnvm_config_t *config, uint32_t start, uint8_t *src, uint32_t lengthInBytes) +{ + status_t returnCode; + bool needSwitchFlexRamMode = false; + + if (config == NULL) + { + return kStatus_FTFx_InvalidArgument; + } + + /* Validates the range of the given address */ + if ((start < config->ftfxConfig.flexramBlockBase) || + ((start + lengthInBytes) > (config->ftfxConfig.flexramBlockBase + config->ftfxConfig.eepromTotalSize))) + { + return kStatus_FTFx_AddressError; + } + + returnCode = kStatus_FTFx_Success; + + /* Switch function of FlexRAM if needed */ + if (!(FTFx->FCNFG & FTFx_FCNFG_EEERDY_MASK)) + { + needSwitchFlexRamMode = true; + + returnCode = FTFx_CMD_SetFlexramFunction(&config->ftfxConfig, kFTFx_FlexramFuncOptAvailableForEeprom); + if (returnCode != kStatus_FTFx_Success) + { + return kStatus_FTFx_SetFlexramAsEepromError; + } + } + + /* Write data to FlexRAM when it is used as EEPROM emulator */ + while (lengthInBytes > 0) + { + if ((!(start & 0x3U)) && (lengthInBytes >= 4)) + { + *(uint32_t *)start = *(uint32_t *)src; + start += 4; + src += 4; + lengthInBytes -= 4; + } + else if ((!(start & 0x1U)) && (lengthInBytes >= 2)) + { + *(uint16_t *)start = *(uint16_t *)src; + start += 2; + src += 2; + lengthInBytes -= 2; + } + else + { + *(uint8_t *)start = *src; + start += 1; + src += 1; + lengthInBytes -= 1; + } + /* Wait till EEERDY bit is set */ + while (!(FTFx->FCNFG & FTFx_FCNFG_EEERDY_MASK)) + { + } + + /* Check for protection violation error */ + if (FTFx->FSTAT & FTFx_FSTAT_FPVIOL_MASK) + { + return kStatus_FTFx_ProtectionViolation; + } + } + + /* Switch function of FlexRAM if needed */ + if (needSwitchFlexRamMode) + { + returnCode = FTFx_CMD_SetFlexramFunction(&config->ftfxConfig, kFTFx_FlexramFuncOptAvailableAsRam); + if (returnCode != kStatus_FTFx_Success) + { + return kStatus_FTFx_RecoverFlexramAsRamError; + } + } + + return returnCode; +} + +status_t FLEXNVM_DflashSetProtection(flexnvm_config_t *config, uint8_t protectStatus) +{ + if (config == NULL) + { + return kStatus_FTFx_InvalidArgument; + } + + if ((config->ftfxConfig.flashDesc.totalSize == 0) || (config->ftfxConfig.flashDesc.totalSize == 0xFFFFFFFFU)) + { + return kStatus_FTFx_CommandNotSupported; + } + + FTFx->FDPROT = protectStatus; + + if (FTFx->FDPROT != protectStatus) + { + return kStatus_FTFx_CommandFailure; + } + + return kStatus_FTFx_Success; +} + +status_t FLEXNVM_DflashGetProtection(flexnvm_config_t *config, uint8_t *protectStatus) +{ + if ((config == NULL) || (protectStatus == NULL)) + { + return kStatus_FTFx_InvalidArgument; + } + + if ((config->ftfxConfig.flashDesc.totalSize == 0) || (config->ftfxConfig.flashDesc.totalSize == 0xFFFFFFFFU)) + { + return kStatus_FTFx_CommandNotSupported; + } + + *protectStatus = FTFx->FDPROT; + + return kStatus_FTFx_Success; +} + +status_t FLEXNVM_EepromSetProtection(flexnvm_config_t *config, uint8_t protectStatus) +{ + if (config == NULL) + { + return kStatus_FTFx_InvalidArgument; + } + + if ((config->ftfxConfig.eepromTotalSize == 0) || (config->ftfxConfig.eepromTotalSize == 0xFFFFU)) + { + return kStatus_FTFx_CommandNotSupported; + } + + FTFx->FEPROT = protectStatus; + + if (FTFx->FEPROT != protectStatus) + { + return kStatus_FTFx_CommandFailure; + } + + return kStatus_FTFx_Success; +} + +status_t FLEXNVM_EepromGetProtection(flexnvm_config_t *config, uint8_t *protectStatus) +{ + if ((config == NULL) || (protectStatus == NULL)) + { + return kStatus_FTFx_InvalidArgument; + } + + if ((config->ftfxConfig.eepromTotalSize == 0) || (config->ftfxConfig.eepromTotalSize == 0xFFFFU)) + { + return kStatus_FTFx_CommandNotSupported; + } + + *protectStatus = FTFx->FEPROT; + + return kStatus_FTFx_Success; +} + +status_t FLEXNVM_GetProperty(flexnvm_config_t *config, flexnvm_property_tag_t whichProperty, uint32_t *value) +{ + if ((config == NULL) || (value == NULL)) + { + return kStatus_FTFx_InvalidArgument; + } + + switch (whichProperty) + { + case kFLEXNVM_PropertyDflashSectorSize: + *value = config->ftfxConfig.flashDesc.sectorSize; + break; + case kFLEXNVM_PropertyDflashTotalSize: + *value = config->ftfxConfig.flashDesc.totalSize; + break; + case kFLEXNVM_PropertyDflashBlockSize: + *value = config->ftfxConfig.flashDesc.totalSize / config->ftfxConfig.flashDesc.blockCount; + break; + case kFLEXNVM_PropertyDflashBlockCount: + *value = config->ftfxConfig.flashDesc.blockCount; + break; + case kFLEXNVM_PropertyDflashBlockBaseAddr: + *value = config->ftfxConfig.flashDesc.blockBase; + break; + case kFLEXNVM_PropertyFlexRamBlockBaseAddr: + *value = config->ftfxConfig.flexramBlockBase; + break; + case kFLEXNVM_PropertyFlexRamTotalSize: + *value = config->ftfxConfig.flexramTotalSize; + break; + case kFLEXNVM_PropertyEepromTotalSize: + *value = config->ftfxConfig.eepromTotalSize; + break; + + default: /* catch inputs that are not recognized */ + return kStatus_FTFx_UnknownProperty; + } + + return kStatus_FTFx_Success; +} + +static status_t flexnvm_convert_start_address(flexnvm_config_t *config, uint32_t start) +{ + if (config == NULL) + { + return kStatus_FTFx_InvalidArgument; + } + + /* From Spec: When required by the command, address bit 23 selects between program flash memory + * (=0) and data flash memory (=1).*/ + config->ftfxConfig.opsConfig.convertedAddress = start - config->ftfxConfig.flashDesc.blockBase + 0x800000U; + + return kStatus_FTFx_Success; +} + +#endif /* FSL_FEATURE_FLASH_HAS_FLEX_NVM */ + diff --git a/ext/hal/nxp/mcux/drivers/kinetis/fsl_ftfx_flexnvm.h b/ext/hal/nxp/mcux/drivers/kinetis/fsl_ftfx_flexnvm.h new file mode 100644 index 00000000000..2b885f84e37 --- /dev/null +++ b/ext/hal/nxp/mcux/drivers/kinetis/fsl_ftfx_flexnvm.h @@ -0,0 +1,564 @@ +/* +* Copyright 2013-2016 Freescale Semiconductor, Inc. +* Copyright 2016-2018 NXP +* All rights reserved. +* +* SPDX-License-Identifier: BSD-3-Clause +* +*/ + +#ifndef _FSL_FTFX_FLEXNVM_H_ +#define _FSL_FTFX_FLEXNVM_H_ + +#include "fsl_ftfx_controller.h" + +/*! + * @addtogroup ftfx_flexnvm_driver + * @{ + */ +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! + * @name Flexnvm version + * @{ + */ +/*! @brief Flexnvm driver version for SDK*/ +#define FSL_FLEXNVM_DRIVER_VERSION (MAKE_VERSION(3, 0, 0)) /*!< Version 1.0.0. */ +/*@}*/ + +/*! + * @brief Enumeration for various flexnvm properties. + */ +typedef enum _flexnvm_property_tag +{ + kFLEXNVM_PropertyDflashSectorSize = 0x00U, /*!< Dflash sector size property.*/ + kFLEXNVM_PropertyDflashTotalSize = 0x01U, /*!< Dflash total size property.*/ + kFLEXNVM_PropertyDflashBlockSize = 0x02U, /*!< Dflash block size property.*/ + kFLEXNVM_PropertyDflashBlockCount = 0x03U, /*!< Dflash block count property.*/ + kFLEXNVM_PropertyDflashBlockBaseAddr = 0x04U, /*!< Dflash block base address property.*/ + kFLEXNVM_PropertyFlexRamBlockBaseAddr = 0x05U, /*!< FlexRam block base address property.*/ + kFLEXNVM_PropertyFlexRamTotalSize = 0x06U, /*!< FlexRam total size property.*/ + kFLEXNVM_PropertyEepromTotalSize = 0x07U, /*!< EEPROM total size property.*/ +} flexnvm_property_tag_t; + +/*! @brief Flexnvm driver state information. + * + * An instance of this structure is allocated by the user of the Flexnvm driver and + * passed into each of the driver APIs. + */ +typedef struct _flexnvm_config +{ + ftfx_config_t ftfxConfig; +} flexnvm_config_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name Initialization + * @{ + */ + +/*! + * @brief Initializes the global flash properties structure members. + * + * This function checks and initializes the Flash module for the other Flash APIs. + * + * @param config Pointer to the storage for the driver runtime state. + * + * @retval #kStatus_FTFx_Success API was executed successfully. + * @retval #kStatus_FTFx_InvalidArgument An invalid argument is provided. + * @retval #kStatus_FTFx_ExecuteInRamFunctionNotReady Execute-in-RAM function is not available. + * @retval #kStatus_FTFx_PartitionStatusUpdateFailure Failed to update the partition status. + */ +status_t FLEXNVM_Init(flexnvm_config_t *config); + +/*@}*/ + +/*! + * @name Erasing + * @{ + */ + +/*! + * @brief Erases the Dflash sectors encompassed by parameters passed into function. + * + * This function erases the appropriate number of flash sectors based on the + * desired start address and length. + * + * @param config The pointer to the storage for the driver runtime state. + * @param start The start address of the desired flash memory to be erased. + * The start address does not need to be sector-aligned but must be word-aligned. + * @param lengthInBytes The length, given in bytes (not words or long-words) + * to be erased. Must be word-aligned. + * @param key The value used to validate all flash erase APIs. + * + * @retval #kStatus_FTFx_Success API was executed successfully. + * @retval #kStatus_FTFx_InvalidArgument An invalid argument is provided. + * @retval #kStatus_FTFx_AlignmentError The parameter is not aligned with the specified baseline. + * @retval #kStatus_FTFx_AddressError The address is out of range. + * @retval #kStatus_FTFx_EraseKeyError The API erase key is invalid. + * @retval #kStatus_FTFx_ExecuteInRamFunctionNotReady Execute-in-RAM function is not available. + * @retval #kStatus_FTFx_AccessError Invalid instruction codes and out-of bounds addresses. + * @retval #kStatus_FTFx_ProtectionViolation The program/erase operation is requested to execute on protected areas. + * @retval #kStatus_FTFx_CommandFailure Run-time error during the command execution. + */ +status_t FLEXNVM_DflashErase(flexnvm_config_t *config, + uint32_t start, + uint32_t lengthInBytes, + uint32_t key); + +/*! + * @brief Erases entire flexnvm + * + * @param config Pointer to the storage for the driver runtime state. + * @param key A value used to validate all flash erase APIs. + * + * @retval #kStatus_FTFx_Success API was executed successfully. + * @retval #kStatus_FTFx_InvalidArgument An invalid argument is provided. + * @retval #kStatus_FTFx_EraseKeyError API erase key is invalid. + * @retval #kStatus_FTFx_ExecuteInRamFunctionNotReady Execute-in-RAM function is not available. + * @retval #kStatus_FTFx_AccessError Invalid instruction codes and out-of bounds addresses. + * @retval #kStatus_FTFx_ProtectionViolation The program/erase operation is requested to execute on protected areas. + * @retval #kStatus_FTFx_CommandFailure Run-time error during command execution. + * @retval #kStatus_FTFx_PartitionStatusUpdateFailure Failed to update the partition status. + */ +status_t FLEXNVM_EraseAll(flexnvm_config_t *config, uint32_t key); + +/*! + * @brief Erases the entire flexnvm, including protected sectors. + * + * @param config Pointer to the storage for the driver runtime state. + * @param key A value used to validate all flash erase APIs. + * + * @retval #kStatus_FTFx_Success API was executed successfully. + * @retval #kStatus_FTFx_InvalidArgument An invalid argument is provided. + * @retval #kStatus_FTFx_EraseKeyError API erase key is invalid. + * @retval #kStatus_FTFx_ExecuteInRamFunctionNotReady Execute-in-RAM function is not available. + * @retval #kStatus_FTFx_AccessError Invalid instruction codes and out-of bounds addresses. + * @retval #kStatus_FTFx_ProtectionViolation The program/erase operation is requested to execute on protected areas. + * @retval #kStatus_FTFx_CommandFailure Run-time error during command execution. + * @retval #kStatus_FTFx_PartitionStatusUpdateFailure Failed to update the partition status. + */ +#if defined(FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_UNSECURE_CMD) && FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_UNSECURE_CMD +status_t FLEXNVM_EraseAllUnsecure(flexnvm_config_t *config, uint32_t key); +#endif + +/*@}*/ + +/*! + * @name Programming + * @{ + */ + +/*! + * @brief Programs flash with data at locations passed in through parameters. + * + * This function programs the flash memory with the desired data for a given + * flash area as determined by the start address and the length. + * + * @param config A pointer to the storage for the driver runtime state. + * @param start The start address of the desired flash memory to be programmed. Must be + * word-aligned. + * @param src A pointer to the source buffer of data that is to be programmed + * into the flash. + * @param lengthInBytes The length, given in bytes (not words or long-words), + * to be programmed. Must be word-aligned. + * + * @retval #kStatus_FTFx_Success API was executed successfully. + * @retval #kStatus_FTFx_InvalidArgument An invalid argument is provided. + * @retval #kStatus_FTFx_AlignmentError Parameter is not aligned with the specified baseline. + * @retval #kStatus_FTFx_AddressError Address is out of range. + * @retval #kStatus_FTFx_ExecuteInRamFunctionNotReady Execute-in-RAM function is not available. + * @retval #kStatus_FTFx_AccessError Invalid instruction codes and out-of bounds addresses. + * @retval #kStatus_FTFx_ProtectionViolation The program/erase operation is requested to execute on protected areas. + * @retval #kStatus_FTFx_CommandFailure Run-time error during the command execution. + */ +status_t FLEXNVM_DflashProgram(flexnvm_config_t *config, + uint32_t start, + uint8_t *src, + uint32_t lengthInBytes); + +/*! + * @brief Programs flash with data at locations passed in through parameters via the Program Section command. + * + * This function programs the flash memory with the desired data for a given + * flash area as determined by the start address and length. + * + * @param config A pointer to the storage for the driver runtime state. + * @param start The start address of the desired flash memory to be programmed. Must be + * word-aligned. + * @param src A pointer to the source buffer of data that is to be programmed + * into the flash. + * @param lengthInBytes The length, given in bytes (not words or long-words), + * to be programmed. Must be word-aligned. + * + * @retval #kStatus_FTFx_Success API was executed successfully. + * @retval #kStatus_FTFx_InvalidArgument An invalid argument is provided. + * @retval #kStatus_FTFx_AlignmentError Parameter is not aligned with specified baseline. + * @retval #kStatus_FTFx_AddressError Address is out of range. + * @retval #kStatus_FTFx_SetFlexramAsRamError Failed to set flexram as RAM. + * @retval #kStatus_FTFx_ExecuteInRamFunctionNotReady Execute-in-RAM function is not available. + * @retval #kStatus_FTFx_AccessError Invalid instruction codes and out-of bounds addresses. + * @retval #kStatus_FTFx_ProtectionViolation The program/erase operation is requested to execute on protected areas. + * @retval #kStatus_FTFx_CommandFailure Run-time error during command execution. + * @retval #kStatus_FTFx_RecoverFlexramAsEepromError Failed to recover FlexRAM as EEPROM. + */ +#if defined(FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD) && FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD +status_t FLEXNVM_DflashProgramSection(flexnvm_config_t *config, + uint32_t start, + uint8_t *src, + uint32_t lengthInBytes); +#endif + +/*! + * @brief Prepares the FlexNVM block for use as data flash, EEPROM backup, or a combination of both and initializes the + * FlexRAM. + * + * @param config Pointer to storage for the driver runtime state. + * @param option The option used to set FlexRAM load behavior during reset. + * @param eepromDataSizeCode Determines the amount of FlexRAM used in each of the available EEPROM subsystems. + * @param flexnvmPartitionCode Specifies how to split the FlexNVM block between data flash memory and EEPROM backup + * memory supporting EEPROM functions. + * + * @retval #kStatus_FTFx_Success API was executed successfully. + * @retval #kStatus_FTFx_InvalidArgument Invalid argument is provided. + * @retval #kStatus_FTFx_ExecuteInRamFunctionNotReady Execute-in-RAM function is not available. + * @retval #kStatus_FTFx_AccessError Invalid instruction codes and out-of bounds addresses. + * @retval #kStatus_FTFx_ProtectionViolation The program/erase operation is requested to execute on protected areas. + * @retval #kStatus_FTFx_CommandFailure Run-time error during command execution. + */ +status_t FLEXNVM_ProgramPartition(flexnvm_config_t *config, + ftfx_partition_flexram_load_opt_t option, + uint32_t eepromDataSizeCode, + uint32_t flexnvmPartitionCode); + +/*@}*/ + +/*! + * @name Reading + * @{ + */ + +/*! + * @brief Reads the resource with data at locations passed in through parameters. + * + * This function reads the flash memory with the desired location for a given + * flash area as determined by the start address and length. + * + * @param config A pointer to the storage for the driver runtime state. + * @param start The start address of the desired flash memory to be programmed. Must be + * word-aligned. + * @param dst A pointer to the destination buffer of data that is used to store + * data to be read. + * @param lengthInBytes The length, given in bytes (not words or long-words), + * to be read. Must be word-aligned. + * @param option The resource option which indicates which area should be read back. + * + * @retval #kStatus_FTFx_Success API was executed successfully. + * @retval #kStatus_FTFx_InvalidArgument An invalid argument is provided. + * @retval #kStatus_FTFx_AlignmentError Parameter is not aligned with the specified baseline. + * @retval #kStatus_FTFx_ExecuteInRamFunctionNotReady Execute-in-RAM function is not available. + * @retval #kStatus_FTFx_AccessError Invalid instruction codes and out-of bounds addresses. + * @retval #kStatus_FTFx_ProtectionViolation The program/erase operation is requested to execute on protected areas. + * @retval #kStatus_FTFx_CommandFailure Run-time error during the command execution. + */ +#if defined(FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD) && FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD +status_t FLEXNVM_ReadResource(flexnvm_config_t *config, + uint32_t start, + uint8_t *dst, + uint32_t lengthInBytes, + ftfx_read_resource_opt_t option); +#endif + +/*@}*/ + +/*! + * @name Verification + * @{ + */ + +/*! + * @brief Verifies an erasure of the desired flash area at a specified margin level. + * + * This function checks the appropriate number of flash sectors based on + * the desired start address and length to check whether the flash is erased + * to the specified read margin level. + * + * @param config A pointer to the storage for the driver runtime state. + * @param start The start address of the desired flash memory to be verified. + * The start address does not need to be sector-aligned but must be word-aligned. + * @param lengthInBytes The length, given in bytes (not words or long-words), + * to be verified. Must be word-aligned. + * @param margin Read margin choice. + * + * @retval #kStatus_FTFx_Success API was executed successfully. + * @retval #kStatus_FTFx_InvalidArgument An invalid argument is provided. + * @retval #kStatus_FTFx_AlignmentError Parameter is not aligned with specified baseline. + * @retval #kStatus_FTFx_AddressError Address is out of range. + * @retval #kStatus_FTFx_ExecuteInRamFunctionNotReady Execute-in-RAM function is not available. + * @retval #kStatus_FTFx_AccessError Invalid instruction codes and out-of bounds addresses. + * @retval #kStatus_FTFx_ProtectionViolation The program/erase operation is requested to execute on protected areas. + * @retval #kStatus_FTFx_CommandFailure Run-time error during the command execution. + */ +status_t FLEXNVM_DflashVerifyErase(flexnvm_config_t *config, + uint32_t start, + uint32_t lengthInBytes, + ftfx_margin_value_t margin); + +/*! + * @brief Verifies erasure of the entire flash at a specified margin level. + * + * This function checks whether the flash is erased to the + * specified read margin level. + * + * @param config A pointer to the storage for the driver runtime state. + * @param margin Read margin choice. + * + * @retval #kStatus_FTFx_Success API was executed successfully. + * @retval #kStatus_FTFx_InvalidArgument An invalid argument is provided. + * @retval #kStatus_FTFx_ExecuteInRamFunctionNotReady Execute-in-RAM function is not available. + * @retval #kStatus_FTFx_AccessError Invalid instruction codes and out-of bounds addresses. + * @retval #kStatus_FTFx_ProtectionViolation The program/erase operation is requested to execute on protected areas. + * @retval #kStatus_FTFx_CommandFailure Run-time error during the command execution. + */ +status_t FLEXNVM_VerifyEraseAll(flexnvm_config_t *config, ftfx_margin_value_t margin); + +/*! + * @brief Verifies programming of the desired flash area at a specified margin level. + * + * This function verifies the data programmed in the flash memory using the + * Flash Program Check Command and compares it to the expected data for a given + * flash area as determined by the start address and length. + * + * @param config A pointer to the storage for the driver runtime state. + * @param start The start address of the desired flash memory to be verified. Must be word-aligned. + * @param lengthInBytes The length, given in bytes (not words or long-words), + * to be verified. Must be word-aligned. + * @param expectedData A pointer to the expected data that is to be + * verified against. + * @param margin Read margin choice. + * @param failedAddress A pointer to the returned failing address. + * @param failedData A pointer to the returned failing data. Some derivatives do + * not include failed data as part of the FCCOBx registers. In this + * case, zeros are returned upon failure. + * + * @retval #kStatus_FTFx_Success API was executed successfully. + * @retval #kStatus_FTFx_InvalidArgument An invalid argument is provided. + * @retval #kStatus_FTFx_AlignmentError Parameter is not aligned with specified baseline. + * @retval #kStatus_FTFx_AddressError Address is out of range. + * @retval #kStatus_FTFx_ExecuteInRamFunctionNotReady Execute-in-RAM function is not available. + * @retval #kStatus_FTFx_AccessError Invalid instruction codes and out-of bounds addresses. + * @retval #kStatus_FTFx_ProtectionViolation The program/erase operation is requested to execute on protected areas. + * @retval #kStatus_FTFx_CommandFailure Run-time error during the command execution. + */ +status_t FLEXNVM_DflashVerifyProgram(flexnvm_config_t *config, + uint32_t start, + uint32_t lengthInBytes, + const uint8_t *expectedData, + ftfx_margin_value_t margin, + uint32_t *failedAddress, + uint32_t *failedData); + +/*@}*/ + +/*! + * @name Security + * @{ + */ + +/*! + * @brief Returns the security state via the pointer passed into the function. + * + * This function retrieves the current flash security status, including the + * security enabling state and the backdoor key enabling state. + * + * @param config A pointer to storage for the driver runtime state. + * @param state A pointer to the value returned for the current security status code: + * + * @retval #kStatus_FTFx_Success API was executed successfully. + * @retval #kStatus_FTFx_InvalidArgument An invalid argument is provided. + */ +status_t FLEXNVM_GetSecurityState(flexnvm_config_t *config, ftfx_security_state_t *state); + +/*! + * @brief Allows users to bypass security with a backdoor key. + * + * If the MCU is in secured state, this function unsecures the MCU by + * comparing the provided backdoor key with ones in the flash configuration + * field. + * + * @param config A pointer to the storage for the driver runtime state. + * @param backdoorKey A pointer to the user buffer containing the backdoor key. + * + * @retval #kStatus_FTFx_Success API was executed successfully. + * @retval #kStatus_FTFx_InvalidArgument An invalid argument is provided. + * @retval #kStatus_FTFx_ExecuteInRamFunctionNotReady Execute-in-RAM function is not available. + * @retval #kStatus_FTFx_AccessError Invalid instruction codes and out-of bounds addresses. + * @retval #kStatus_FTFx_ProtectionViolation The program/erase operation is requested to execute on protected areas. + * @retval #kStatus_FTFx_CommandFailure Run-time error during the command execution. + */ +status_t FLEXNVM_SecurityBypass(flexnvm_config_t *config, const uint8_t *backdoorKey); + +/*@}*/ + +/*! + * @name FlexRAM + * @{ + */ + +/*! + * @brief Sets the FlexRAM function command. + * + * @param config A pointer to the storage for the driver runtime state. + * @param option The option used to set the work mode of FlexRAM. + * + * @retval #kStatus_FTFx_Success API was executed successfully. + * @retval #kStatus_FTFx_InvalidArgument An invalid argument is provided. + * @retval #kStatus_FTFx_ExecuteInRamFunctionNotReady Execute-in-RAM function is not available. + * @retval #kStatus_FTFx_AccessError Invalid instruction codes and out-of bounds addresses. + * @retval #kStatus_FTFx_ProtectionViolation The program/erase operation is requested to execute on protected areas. + * @retval #kStatus_FTFx_CommandFailure Run-time error during the command execution. + */ +#if defined(FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD) && FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD +status_t FLEXNVM_SetFlexramFunction(flexnvm_config_t *config, ftfx_flexram_func_opt_t option); +#endif + +/*@}*/ + +/*! + * @brief Programs the EEPROM with data at locations passed in through parameters. + * + * This function programs the emulated EEPROM with the desired data for a given + * flash area as determined by the start address and length. + * + * @param config A pointer to the storage for the driver runtime state. + * @param start The start address of the desired flash memory to be programmed. Must be + * word-aligned. + * @param src A pointer to the source buffer of data that is to be programmed + * into the flash. + * @param lengthInBytes The length, given in bytes (not words or long-words), + * to be programmed. Must be word-aligned. + * + * @retval #kStatus_FTFx_Success API was executed successfully. + * @retval #kStatus_FTFx_InvalidArgument An invalid argument is provided. + * @retval #kStatus_FTFx_AddressError Address is out of range. + * @retval #kStatus_FTFx_SetFlexramAsEepromError Failed to set flexram as eeprom. + * @retval #kStatus_FTFx_ProtectionViolation The program/erase operation is requested to execute on protected areas. + * @retval #kStatus_FTFx_RecoverFlexramAsRamError Failed to recover the FlexRAM as RAM. + */ +status_t FLEXNVM_EepromWrite(flexnvm_config_t *config, uint32_t start, uint8_t *src, uint32_t lengthInBytes); + +/*! +* @name Flash Protection Utilities +* @{ +*/ + +/*! + * @brief Sets the DFlash protection to the intended protection status. + * + * @param config A pointer to the storage for the driver runtime state. + * @param protectStatus The expected protect status to set to the DFlash protection register. Each bit + * corresponds to the protection of the 1/8 of the total DFlash. The least significant bit corresponds to the lowest + * address area of the DFlash. The most significant bit corresponds to the highest address area of the DFlash. There + * are + * two possible cases as shown below: + * 0: this area is protected. + * 1: this area is unprotected. + * + * @retval #kStatus_FTFx_Success API was executed successfully. + * @retval #kStatus_FTFx_InvalidArgument An invalid argument is provided. + * @retval #kStatus_FTFx_CommandNotSupported Flash API is not supported. + * @retval #kStatus_FTFx_CommandFailure Run-time error during command execution. + */ +status_t FLEXNVM_DflashSetProtection(flexnvm_config_t *config, uint8_t protectStatus); + +/*! + * @brief Gets the DFlash protection status. + * + * @param config A pointer to the storage for the driver runtime state. + * @param protectStatus DFlash Protect status returned by the PFlash IP. Each bit corresponds to the protection of the + * 1/8 of + * the total DFlash. The least significant bit corresponds to the lowest address area of the DFlash. The most + * significant bit corresponds to the highest address area of the DFlash, and so on. There are two possible cases as + * below: + * 0: this area is protected. + * 1: this area is unprotected. + * + * @retval #kStatus_FTFx_Success API was executed successfully. + * @retval #kStatus_FTFx_InvalidArgument An invalid argument is provided. + * @retval #kStatus_FTFx_CommandNotSupported Flash API is not supported. + */ +status_t FLEXNVM_DflashGetProtection(flexnvm_config_t *config, uint8_t *protectStatus); + +/*! + * @brief Sets the EEPROM protection to the intended protection status. + * + * @param config A pointer to the storage for the driver runtime state. + * @param protectStatus The expected protect status to set to the EEPROM protection register. Each bit + * corresponds to the protection of the 1/8 of the total EEPROM. The least significant bit corresponds to the lowest + * address area of the EEPROM. The most significant bit corresponds to the highest address area of EEPROM, and so on. + * There are two possible cases as shown below: + * 0: this area is protected. + * 1: this area is unprotected. + * + * @retval #kStatus_FTFx_Success API was executed successfully. + * @retval #kStatus_FTFx_InvalidArgument An invalid argument is provided. + * @retval #kStatus_FTFx_CommandNotSupported Flash API is not supported. + * @retval #kStatus_FTFx_CommandFailure Run-time error during command execution. + */ +status_t FLEXNVM_EepromSetProtection(flexnvm_config_t *config, uint8_t protectStatus); + +/*! + * @brief Gets the EEPROM protection status. + * + * @param config A pointer to the storage for the driver runtime state. + * @param protectStatus DFlash Protect status returned by the PFlash IP. Each bit corresponds to the protection of the + * 1/8 of + * the total EEPROM. The least significant bit corresponds to the lowest address area of the EEPROM. The most + * significant bit corresponds to the highest address area of the EEPROM. There are two possible cases as below: + * 0: this area is protected. + * 1: this area is unprotected. + * + * @retval #kStatus_FTFx_Success API was executed successfully. + * @retval #kStatus_FTFx_InvalidArgument An invalid argument is provided. + * @retval #kStatus_FTFx_CommandNotSupported Flash API is not supported. + */ +status_t FLEXNVM_EepromGetProtection(flexnvm_config_t *config, uint8_t *protectStatus); + +/*@}*/ + +/*! + * @name Properties + * @{ + */ + +/*! + * @brief Returns the desired flexnvm property. + * + * @param config A pointer to the storage for the driver runtime state. + * @param whichProperty The desired property from the list of properties in + * enum flexnvm_property_tag_t + * @param value A pointer to the value returned for the desired flexnvm property. + * + * @retval #kStatus_FTFx_Success API was executed successfully. + * @retval #kStatus_FTFx_InvalidArgument An invalid argument is provided. + * @retval #kStatus_FTFx_UnknownProperty An unknown property tag. + */ +status_t FLEXNVM_GetProperty(flexnvm_config_t *config, flexnvm_property_tag_t whichProperty, uint32_t *value); + + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* _FSL_FTFX_FLEXNVM_H_ */ diff --git a/ext/hal/nxp/mcux/drivers/kinetis/fsl_ftfx_utilities.h b/ext/hal/nxp/mcux/drivers/kinetis/fsl_ftfx_utilities.h new file mode 100644 index 00000000000..80a058cdbfa --- /dev/null +++ b/ext/hal/nxp/mcux/drivers/kinetis/fsl_ftfx_utilities.h @@ -0,0 +1,66 @@ +/* +* Copyright 2017-2018 NXP +* All rights reserved. +* +* SPDX-License-Identifier: BSD-3-Clause +* +*/ + +#ifndef _FSL_FTFX_UTILITIES_H_ +#define _FSL_FTFX_UTILITIES_H_ + +/*! + * @addtogroup ftfx_utilities + * @{ + */ +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @brief Constructs the version number for drivers. */ +#if !defined(MAKE_VERSION) +#define MAKE_VERSION(major, minor, bugfix) (((major) << 16) | ((minor) << 8) | (bugfix)) +#endif + +/*! @brief Constructs a status code value from a group and a code number. */ +#if !defined(MAKE_STATUS) +#define MAKE_STATUS(group, code) ((((group)*100) + (code))) +#endif + +/*! @brief Constructs the four character code for the Flash driver API key. */ +#if !defined(FOUR_CHAR_CODE) +#define FOUR_CHAR_CODE(a, b, c, d) (((d) << 24) | ((c) << 16) | ((b) << 8) | ((a))) +#endif + +/*! @brief Alignment(down) utility. */ +#if !defined(ALIGN_DOWN) +#define ALIGN_DOWN(x, a) ((x) & (uint32_t)(-((int32_t)(a)))) +#endif + +/*! @brief Alignment(up) utility. */ +#if !defined(ALIGN_UP) +#define ALIGN_UP(x, a) (-((int32_t)((uint32_t)(-((int32_t)(x))) & (uint32_t)(-((int32_t)(a)))))) +#endif + +/*! @brief bytes2word utility. */ +#define B1P4(b) (((uint32_t)(b)&0xFFU) << 24) +#define B1P3(b) (((uint32_t)(b)&0xFFU) << 16) +#define B1P2(b) (((uint32_t)(b)&0xFFU) << 8) +#define B1P1(b) ((uint32_t)(b)&0xFFU) +#define B2P3(b) (((uint32_t)(b)&0xFFFFU) << 16) +#define B2P2(b) (((uint32_t)(b)&0xFFFFU) << 8) +#define B2P1(b) ((uint32_t)(b)&0xFFFFU) +#define B3P2(b) (((uint32_t)(b)&0xFFFFFFU) << 8) +#define B3P1(b) ((uint32_t)(b)&0xFFFFFFU) + +#define BYTE2WORD_1_3(x, y) (B1P4(x) | B3P1(y)) +#define BYTE2WORD_2_2(x, y) (B2P3(x) | B2P1(y)) +#define BYTE2WORD_3_1(x, y) (B3P2(x) | B1P1(y)) +#define BYTE2WORD_1_1_2(x, y, z) (B1P4(x) | B1P3(y) | B2P1(z)) +#define BYTE2WORD_1_2_1(x, y, z) (B1P4(x) | B2P2(y) | B1P1(z)) +#define BYTE2WORD_2_1_1(x, y, z) (B2P3(x) | B1P2(y) | B1P1(z)) +#define BYTE2WORD_1_1_1_1(x, y, z, w) (B1P4(x) | B1P3(y) | B1P2(z) | B1P1(w)) + + +#endif /* _FSL_FTFX_UTILITIES_H_ */ + diff --git a/ext/hal/nxp/mcux/drivers/kinetis/fsl_ftm.c b/ext/hal/nxp/mcux/drivers/kinetis/fsl_ftm.c index 9cca44b0e41..8a4373bbe43 100644 --- a/ext/hal/nxp/mcux/drivers/kinetis/fsl_ftm.c +++ b/ext/hal/nxp/mcux/drivers/kinetis/fsl_ftm.c @@ -1,35 +1,18 @@ /* * Copyright (c) 2015, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP + * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * SPDX-License-Identifier: BSD-3-Clause */ #include "fsl_ftm.h" +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.ftm" +#endif + /******************************************************************************* * Prototypes ******************************************************************************/ @@ -49,7 +32,7 @@ static uint32_t FTM_GetInstance(FTM_Type *base); * user wishes to use. * * @param base FTM peripheral base address - * @param syncMethod Syncronization methods to use to update buffered registers. This is a logical + * @param syncMethod Synchronization methods to use to update buffered registers. This is a logical * OR of members of the enumeration ::ftm_pwm_sync_method_t */ static void FTM_SetPwmSync(FTM_Type *base, uint32_t syncMethod); @@ -217,6 +200,16 @@ static void FTM_SetReloadPoints(FTM_Type *base, uint32_t reloadPoints) base->SYNC = reg; } +/*! + * brief Ungates the FTM clock and configures the peripheral for basic operation. + * + * note This API should be called at the beginning of the application which is using the FTM driver. + * + * param base FTM peripheral base address + * param config Pointer to the user configuration structure. + * + * return kStatus_Success indicates success; Else indicates failure. + */ status_t FTM_Init(FTM_Type *base, const ftm_config_t *config) { assert(config); @@ -270,13 +263,12 @@ status_t FTM_Init(FTM_Type *base, const ftm_config_t *config) #endif /* FSL_FEATURE_FTM_HAS_RELOAD_INITIALIZATION_TRIGGER */ /* FTM deadtime insertion control */ - base->DEADTIME = (0u | + base->DEADTIME = (0u | #if defined(FSL_FEATURE_FTM_HAS_EXTENDED_DEADTIME_VALUE) && (FSL_FEATURE_FTM_HAS_EXTENDED_DEADTIME_VALUE) - /* Has extended deadtime value register) */ - FTM_DEADTIME_DTVALEX(config->deadTimeValue >> 6) | + /* Has extended deadtime value register) */ + FTM_DEADTIME_DTVALEX(config->deadTimeValue >> 6) | #endif /* FSL_FEATURE_FTM_HAS_EXTENDED_DEADTIME_VALUE */ - FTM_DEADTIME_DTPS(config->deadTimePrescale) | - FTM_DEADTIME_DTVAL(config->deadTimeValue)); + FTM_DEADTIME_DTPS(config->deadTimePrescale) | FTM_DEADTIME_DTVAL(config->deadTimeValue)); /* FTM fault filter value */ reg = base->FLTCTRL; @@ -287,6 +279,11 @@ status_t FTM_Init(FTM_Type *base, const ftm_config_t *config) return kStatus_Success; } +/*! + * brief Gates the FTM clock. + * + * param base FTM peripheral base address + */ void FTM_Deinit(FTM_Type *base) { /* Set clock source to none to disable counter */ @@ -298,10 +295,33 @@ void FTM_Deinit(FTM_Type *base) #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ } +/*! + * brief Fills in the FTM configuration structure with the default settings. + * + * The default values are: + * code + * config->prescale = kFTM_Prescale_Divide_1; + * config->bdmMode = kFTM_BdmMode_0; + * config->pwmSyncMode = kFTM_SoftwareTrigger; + * config->reloadPoints = 0; + * config->faultMode = kFTM_Fault_Disable; + * config->faultFilterValue = 0; + * config->deadTimePrescale = kFTM_Deadtime_Prescale_1; + * config->deadTimeValue = 0; + * config->extTriggers = 0; + * config->chnlInitState = 0; + * config->chnlPolarity = 0; + * config->useGlobalTimeBase = false; + * endcode + * param config Pointer to the user configuration structure. + */ void FTM_GetDefaultConfig(ftm_config_t *config) { assert(config); + /* Initializes the configure structure to zero. */ + memset(config, 0, sizeof(*config)); + /* Divide FTM clock by 1 */ config->prescale = kFTM_Prescale_Divide_1; /* FTM behavior in BDM mode */ @@ -328,6 +348,22 @@ void FTM_GetDefaultConfig(ftm_config_t *config) config->useGlobalTimeBase = false; } +/*! + * brief Configures the PWM signal parameters. + * + * Call this function to configure the PWM signal period, mode, duty cycle, and edge. Use this + * function to configure all FTM channels that are used to output a PWM signal. + * + * param base FTM peripheral base address + * param chnlParams Array of PWM channel parameters to configure the channel(s) + * param numOfChnls Number of channels to configure; This should be the size of the array passed in + * param mode PWM operation mode, options available in enumeration ::ftm_pwm_mode_t + * param pwmFreq_Hz PWM signal frequency in Hz + * param srcClock_Hz FTM counter clock in Hz + * + * return kStatus_Success if the PWM setup was successful + * kStatus_Error on failure + */ status_t FTM_SetupPwm(FTM_Type *base, const ftm_chnl_pwm_signal_param_t *chnlParams, uint8_t numOfChnls, @@ -496,6 +532,17 @@ status_t FTM_SetupPwm(FTM_Type *base, return kStatus_Success; } +/*! + * brief Updates the duty cycle of an active PWM signal. + * + * param base FTM peripheral base address + * param chnlNumber The channel/channel pair number. In combined mode, this represents + * the channel pair number + * param currentPwmMode The current PWM mode set during PWM setup + * param dutyCyclePercent New PWM pulse width; The value should be between 0 to 100 + * 0=inactive signal(0% duty cycle)... + * 100=active signal (100% duty cycle) + */ void FTM_UpdatePwmDutycycle(FTM_Type *base, ftm_chnl_t chnlNumber, ftm_pwm_mode_t currentPwmMode, @@ -533,6 +580,14 @@ void FTM_UpdatePwmDutycycle(FTM_Type *base, } } +/*! + * brief Updates the edge level selection for a channel. + * + * param base FTM peripheral base address + * param chnlNumber The channel number + * param level The level to be set to the ELSnB:ELSnA field; Valid values are 00, 01, 10, 11. + * See the Kinetis SoC reference manual for details about this field. + */ void FTM_UpdateChnlEdgeLevelSelect(FTM_Type *base, ftm_chnl_t chnlNumber, uint8_t level) { uint32_t reg = base->CONTROLS[chnlNumber].CnSC; @@ -544,6 +599,131 @@ void FTM_UpdateChnlEdgeLevelSelect(FTM_Type *base, ftm_chnl_t chnlNumber, uint8_ base->CONTROLS[chnlNumber].CnSC = reg; } +/*! + * brief Configures the PWM mode parameters. + * + * Call this function to configure the PWM signal mode, duty cycle in ticks, and edge. Use this + * function to configure all FTM channels that are used to output a PWM signal. + * Please note that: This API is similar with FTM_SetupPwm() API, but will not set the timer period, + * and this API will set channel match value in timer ticks, not period percent. + * + * param base FTM peripheral base address + * param chnlParams Array of PWM channel parameters to configure the channel(s) + * param numOfChnls Number of channels to configure; This should be the size of the array passed in + * param mode PWM operation mode, options available in enumeration ::ftm_pwm_mode_t + * + * return kStatus_Success if the PWM setup was successful + * kStatus_Error on failure + */ +status_t FTM_SetupPwmMode(FTM_Type *base, + const ftm_chnl_pwm_config_param_t *chnlParams, + uint8_t numOfChnls, + ftm_pwm_mode_t mode) +{ + assert(chnlParams); + assert(numOfChnls); + + uint32_t reg; + uint8_t i; + + switch (mode) + { + case kFTM_EdgeAlignedPwm: + case kFTM_CombinedPwm: + base->SC &= ~FTM_SC_CPWMS_MASK; + break; + case kFTM_CenterAlignedPwm: + base->SC |= FTM_SC_CPWMS_MASK; + break; + default: + break; + } + + /* Setup each FTM channel */ + for (i = 0; i < numOfChnls; i++) + { + if ((mode == kFTM_EdgeAlignedPwm) || (mode == kFTM_CenterAlignedPwm)) + { + /* Clear the current mode and edge level bits */ + reg = base->CONTROLS[chnlParams->chnlNumber].CnSC; + reg &= ~(FTM_CnSC_MSA_MASK | FTM_CnSC_MSB_MASK | FTM_CnSC_ELSA_MASK | FTM_CnSC_ELSB_MASK); + + /* Setup the active level */ + reg |= (uint32_t)(chnlParams->level << FTM_CnSC_ELSA_SHIFT); + + /* Edge-aligned mode needs MSB to be 1, don't care for Center-aligned mode */ + reg |= FTM_CnSC_MSB(1U); + + /* Update the mode and edge level */ + base->CONTROLS[chnlParams->chnlNumber].CnSC = reg; + + base->CONTROLS[chnlParams->chnlNumber].CnV = chnlParams->dutyValue; +#if defined(FSL_FEATURE_FTM_HAS_ENABLE_PWM_OUTPUT) && (FSL_FEATURE_FTM_HAS_ENABLE_PWM_OUTPUT) + /* Set to output mode */ + FTM_SetPwmOutputEnable(base, chnlParams->chnlNumber, true); +#endif + } + else + { + /* This check is added for combined mode as the channel number should be the pair number */ + if (chnlParams->chnlNumber >= (FSL_FEATURE_FTM_CHANNEL_COUNTn(base) / 2)) + { + return kStatus_Fail; + } + + /* Clear the current mode and edge level bits for channel n */ + reg = base->CONTROLS[chnlParams->chnlNumber * 2].CnSC; + reg &= ~(FTM_CnSC_MSA_MASK | FTM_CnSC_MSB_MASK | FTM_CnSC_ELSA_MASK | FTM_CnSC_ELSB_MASK); + + /* Setup the active level for channel n */ + reg |= (uint32_t)(chnlParams->level << FTM_CnSC_ELSA_SHIFT); + + /* Update the mode and edge level for channel n */ + base->CONTROLS[chnlParams->chnlNumber * 2].CnSC = reg; + + /* Clear the current mode and edge level bits for channel n + 1 */ + reg = base->CONTROLS[(chnlParams->chnlNumber * 2) + 1].CnSC; + reg &= ~(FTM_CnSC_MSA_MASK | FTM_CnSC_MSB_MASK | FTM_CnSC_ELSA_MASK | FTM_CnSC_ELSB_MASK); + + /* Setup the active level for channel n + 1 */ + reg |= (uint32_t)(chnlParams->level << FTM_CnSC_ELSA_SHIFT); + + /* Update the mode and edge level for channel n + 1*/ + base->CONTROLS[(chnlParams->chnlNumber * 2) + 1].CnSC = reg; + + /* Set the combine bit for the channel pair */ + base->COMBINE |= + (1U << (FTM_COMBINE_COMBINE0_SHIFT + (FTM_COMBINE_COMBINE1_SHIFT * chnlParams->chnlNumber))); + + /* Set the channel pair values */ + base->CONTROLS[chnlParams->chnlNumber * 2].CnV = chnlParams->firstEdgeValue; + base->CONTROLS[(chnlParams->chnlNumber * 2) + 1].CnV = chnlParams->dutyValue; + +#if defined(FSL_FEATURE_FTM_HAS_ENABLE_PWM_OUTPUT) && (FSL_FEATURE_FTM_HAS_ENABLE_PWM_OUTPUT) + /* Set to output mode */ + FTM_SetPwmOutputEnable(base, (ftm_chnl_t)((uint8_t)chnlParams->chnlNumber * 2), true); + FTM_SetPwmOutputEnable(base, (ftm_chnl_t)((uint8_t)chnlParams->chnlNumber * 2 + 1), true); +#endif + } + chnlParams++; + } + + return kStatus_Success; +} + +/*! + * brief Enables capturing an input signal on the channel using the function parameters. + * + * When the edge specified in the captureMode argument occurs on the channel, the FTM counter is + * captured into the CnV register. The user has to read the CnV register separately to get this + * value. The filter function is disabled if the filterVal argument passed in is 0. The filter + * function is available only for channels 0, 1, 2, 3. + * + * param base FTM peripheral base address + * param chnlNumber The channel number + * param captureMode Specifies which edge to capture + * param filterValue Filter value, specify 0 to disable filter. Available only for channels 0-3. + */ void FTM_SetupInputCapture(FTM_Type *base, ftm_chnl_t chnlNumber, ftm_input_capture_edge_t captureMode, @@ -555,8 +735,10 @@ void FTM_SetupInputCapture(FTM_Type *base, base->COMBINE &= ~(1U << (FTM_COMBINE_COMBINE0_SHIFT + (FTM_COMBINE_COMBINE1_SHIFT * (chnlNumber >> 1)))); /* Clear the dual edge capture mode because it's it's higher priority */ base->COMBINE &= ~(1U << (FTM_COMBINE_DECAPEN0_SHIFT + (FTM_COMBINE_COMBINE1_SHIFT * (chnlNumber >> 1)))); +#if !(defined(FSL_FEATURE_FTM_HAS_NO_QDCTRL) && FSL_FEATURE_FTM_HAS_NO_QDCTRL) /* Clear the quadrature decoder mode beacause it's higher priority */ base->QDCTRL &= ~FTM_QDCTRL_QUADEN_MASK; +#endif reg = base->CONTROLS[chnlNumber].CnSC; reg &= ~(FTM_CnSC_MSA_MASK | FTM_CnSC_MSB_MASK | FTM_CnSC_ELSA_MASK | FTM_CnSC_ELSB_MASK); @@ -578,6 +760,17 @@ void FTM_SetupInputCapture(FTM_Type *base, #endif } +/*! + * brief Configures the FTM to generate timed pulses. + * + * When the FTM counter matches the value of compareVal argument (this is written into CnV reg), + * the channel output is changed based on what is specified in the compareMode argument. + * + * param base FTM peripheral base address + * param chnlNumber The channel number + * param compareMode Action to take on the channel output when the compare condition is met + * param compareValue Value to be programmed in the CnV register. + */ void FTM_SetupOutputCompare(FTM_Type *base, ftm_chnl_t chnlNumber, ftm_output_compare_mode_t compareMode, @@ -589,8 +782,10 @@ void FTM_SetupOutputCompare(FTM_Type *base, base->COMBINE &= ~(1U << (FTM_COMBINE_COMBINE0_SHIFT + (FTM_COMBINE_COMBINE1_SHIFT * (chnlNumber >> 1)))); /* Clear the dual edge capture mode because it's it's higher priority */ base->COMBINE &= ~(1U << (FTM_COMBINE_DECAPEN0_SHIFT + (FTM_COMBINE_COMBINE1_SHIFT * (chnlNumber >> 1)))); +#if !(defined(FSL_FEATURE_FTM_HAS_NO_QDCTRL) && FSL_FEATURE_FTM_HAS_NO_QDCTRL) /* Clear the quadrature decoder mode beacause it's higher priority */ base->QDCTRL &= ~FTM_QDCTRL_QUADEN_MASK; +#endif reg = base->CONTROLS[chnlNumber].CnSC; reg &= ~(FTM_CnSC_MSA_MASK | FTM_CnSC_MSB_MASK | FTM_CnSC_ELSA_MASK | FTM_CnSC_ELSB_MASK); @@ -607,6 +802,20 @@ void FTM_SetupOutputCompare(FTM_Type *base, #endif } +/*! + * brief Configures the dual edge capture mode of the FTM. + * + * This function sets up the dual edge capture mode on a channel pair. The capture edge for the + * channel pair and the capture mode (one-shot or continuous) is specified in the parameter + * argument. The filter function is disabled if the filterVal argument passed is zero. The filter + * function is available only on channels 0 and 2. The user has to read the channel CnV registers + * separately to get the capture values. + * + * param base FTM peripheral base address + * param chnlPairNumber The FTM channel pair number; options are 0, 1, 2, 3 + * param edgeParam Sets up the dual edge capture function + * param filterValue Filter value, specify 0 to disable filter. Available only for channel pair 0 and 1. + */ void FTM_SetupDualEdgeCapture(FTM_Type *base, ftm_chnl_t chnlPairNumber, const ftm_dual_edge_capture_param_t *edgeParam, @@ -650,6 +859,14 @@ void FTM_SetupDualEdgeCapture(FTM_Type *base, #endif } +/*! + * brief Configures the parameters and activates the quadrature decoder mode. + * + * param base FTM peripheral base address + * param phaseAParams Phase A configuration parameters + * param phaseBParams Phase B configuration parameters + * param quadMode Selects encoding mode used in quadrature decoder mode + */ void FTM_SetupQuadDecode(FTM_Type *base, const ftm_phase_params_t *phaseAParams, const ftm_phase_params_t *phaseBParams, @@ -677,7 +894,7 @@ void FTM_SetupQuadDecode(FTM_Type *base, reg |= FTM_FILTER_CH1FVAL(phaseBParams->phaseFilterVal); base->FILTER = reg; } - +#if !(defined(FSL_FEATURE_FTM_HAS_NO_QDCTRL) && FSL_FEATURE_FTM_HAS_NO_QDCTRL) /* Set Quadrature decode properties */ reg = base->QDCTRL; reg &= ~(FTM_QDCTRL_QUADMODE_MASK | FTM_QDCTRL_PHAFLTREN_MASK | FTM_QDCTRL_PHBFLTREN_MASK | FTM_QDCTRL_PHAPOL_MASK | @@ -688,37 +905,32 @@ void FTM_SetupQuadDecode(FTM_Type *base, base->QDCTRL = reg; /* Enable Quad decode */ base->QDCTRL |= FTM_QDCTRL_QUADEN_MASK; +#endif } +/*! + * brief Sets up the working of the FTM fault protection. + * + * FTM can have up to 4 fault inputs. This function sets up fault parameters, fault level, and a filter. + * + * param base FTM peripheral base address + * param faultNumber FTM fault to configure. + * param faultParams Parameters passed in to set up the fault + */ void FTM_SetupFault(FTM_Type *base, ftm_fault_input_t faultNumber, const ftm_fault_param_t *faultParams) { assert(faultParams); - uint32_t reg; - - reg = base->FLTCTRL; - if (faultParams->enableFaultInput) - { - /* Enable the fault input */ - reg |= (FTM_FLTCTRL_FAULT0EN_MASK << faultNumber); - } - else - { - /* Disable the fault input */ - reg &= ~(FTM_FLTCTRL_FAULT0EN_MASK << faultNumber); - } - if (faultParams->useFaultFilter) { /* Enable the fault filter */ - reg |= (FTM_FLTCTRL_FFLTR0EN_MASK << (FTM_FLTCTRL_FFLTR0EN_SHIFT + faultNumber)); + base->FLTCTRL |= (FTM_FLTCTRL_FFLTR0EN_MASK << (FTM_FLTCTRL_FFLTR0EN_SHIFT + faultNumber)); } else { /* Disable the fault filter */ - reg &= ~(FTM_FLTCTRL_FFLTR0EN_MASK << (FTM_FLTCTRL_FFLTR0EN_SHIFT + faultNumber)); + base->FLTCTRL &= ~(FTM_FLTCTRL_FFLTR0EN_MASK << (FTM_FLTCTRL_FFLTR0EN_SHIFT + faultNumber)); } - base->FLTCTRL = reg; if (faultParams->faultLevel) { @@ -730,8 +942,26 @@ void FTM_SetupFault(FTM_Type *base, ftm_fault_input_t faultNumber, const ftm_fau /* Active high polarity for the fault input pin */ base->FLTPOL &= ~(1U << faultNumber); } + + if (faultParams->enableFaultInput) + { + /* Enable the fault input */ + base->FLTCTRL |= (FTM_FLTCTRL_FAULT0EN_MASK << faultNumber); + } + else + { + /* Disable the fault input */ + base->FLTCTRL &= ~(FTM_FLTCTRL_FAULT0EN_MASK << faultNumber); + } } +/*! + * brief Enables the selected FTM interrupts. + * + * param base FTM peripheral base address + * param mask The interrupts to enable. This is a logical OR of members of the + * enumeration ::ftm_interrupt_enable_t + */ void FTM_EnableInterrupts(FTM_Type *base, uint32_t mask) { uint32_t chnlInts = (mask & 0xFFU); @@ -769,6 +999,13 @@ void FTM_EnableInterrupts(FTM_Type *base, uint32_t mask) } } +/*! + * brief Disables the selected FTM interrupts. + * + * param base FTM peripheral base address + * param mask The interrupts to enable. This is a logical OR of members of the + * enumeration ::ftm_interrupt_enable_t + */ void FTM_DisableInterrupts(FTM_Type *base, uint32_t mask) { uint32_t chnlInts = (mask & 0xFF); @@ -805,6 +1042,14 @@ void FTM_DisableInterrupts(FTM_Type *base, uint32_t mask) } } +/*! + * brief Gets the enabled FTM interrupts. + * + * param base FTM peripheral base address + * + * return The enabled interrupts. This is the logical OR of members of the + * enumeration ::ftm_interrupt_enable_t + */ uint32_t FTM_GetEnabledInterrupts(FTM_Type *base) { uint32_t enabledInterrupts = 0; @@ -845,6 +1090,14 @@ uint32_t FTM_GetEnabledInterrupts(FTM_Type *base) return enabledInterrupts; } +/*! + * brief Gets the FTM status flags. + * + * param base FTM peripheral base address + * + * return The status flags. This is the logical OR of members of the + * enumeration ::ftm_status_flags_t + */ uint32_t FTM_GetStatusFlags(FTM_Type *base) { uint32_t statusFlags = 0; @@ -878,6 +1131,13 @@ uint32_t FTM_GetStatusFlags(FTM_Type *base) return statusFlags; } +/*! + * brief Clears the FTM status flags. + * + * param base FTM peripheral base address + * param mask The status flags to clear. This is a logical OR of members of the + * enumeration ::ftm_status_flags_t + */ void FTM_ClearStatusFlags(FTM_Type *base, uint32_t mask) { /* Clear the timer overflow flag by writing a 0 to the bit while it is set */ diff --git a/ext/hal/nxp/mcux/drivers/kinetis/fsl_ftm.h b/ext/hal/nxp/mcux/drivers/kinetis/fsl_ftm.h index 8db81a633ac..7a56dd5ea9e 100644 --- a/ext/hal/nxp/mcux/drivers/kinetis/fsl_ftm.h +++ b/ext/hal/nxp/mcux/drivers/kinetis/fsl_ftm.h @@ -1,31 +1,9 @@ /* * Copyright (c) 2015, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP + * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * SPDX-License-Identifier: BSD-3-Clause */ #ifndef _FSL_FTM_H_ #define _FSL_FTM_H_ @@ -37,15 +15,15 @@ * @{ */ - /******************************************************************************* * Definitions ******************************************************************************/ /*! @name Driver version */ /*@{*/ -#define FSL_FTM_DRIVER_VERSION (MAKE_VERSION(2, 0, 2)) /*!< Version 2.0.2 */ - /*@}*/ +/*! @brief FTM driver version 2.1.0. */ +#define FSL_FTM_DRIVER_VERSION (MAKE_VERSION(2, 1, 0)) +/*@}*/ /*! * @brief List of FTM channels @@ -103,6 +81,18 @@ typedef struct _ftm_chnl_pwm_signal_param percentage of the PWM period */ } ftm_chnl_pwm_signal_param_t; +/*! @brief Options to configure a FTM channel using precise setting.*/ +typedef struct _ftm_chnl_pwm_config_param +{ + ftm_chnl_t chnlNumber; /*!< The channel/channel pair number. + In combined mode, this represents the channel pair number. */ + ftm_pwm_level_select_t level; /*!< PWM output active level select. */ + uint16_t dutyValue; /*!< PWM pulse width, the uint of this value is timer ticks. */ + uint16_t firstEdgeValue; /*!< Used only in combined PWM mode to generate an asymmetrical PWM. + Specifies the delay to the first edge in a PWM period. + If unsure leave as 0, uint of this value is timer ticks. */ +} ftm_chnl_pwm_config_param_t; + /*! @brief FlexTimer output compare mode */ typedef enum _ftm_output_compare_mode { @@ -234,12 +224,18 @@ typedef enum _ftm_external_trigger kFTM_Chnl3Trigger = (1U << 1), /*!< Generate trigger when counter equals chnl 3 CnV reg */ kFTM_Chnl4Trigger = (1U << 2), /*!< Generate trigger when counter equals chnl 4 CnV reg */ kFTM_Chnl5Trigger = (1U << 3), /*!< Generate trigger when counter equals chnl 5 CnV reg */ +#if defined(FSL_FEATURE_FTM_HAS_CHANNEL6_TRIGGER) && (FSL_FEATURE_FTM_HAS_CHANNEL6_TRIGGER) kFTM_Chnl6Trigger = (1U << 8), /*!< Available on certain SoC's, generate trigger when counter equals chnl 6 CnV reg */ +#endif +#if defined(FSL_FEATURE_FTM_HAS_CHANNEL7_TRIGGER) && (FSL_FEATURE_FTM_HAS_CHANNEL7_TRIGGER) kFTM_Chnl7Trigger = (1U << 9), /*!< Available on certain SoC's, generate trigger when counter equals chnl 7 CnV reg */ - kFTM_InitTrigger = (1U << 6), /*!< Generate Trigger when counter is updated with CNTIN */ +#endif + kFTM_InitTrigger = (1U << 6), /*!< Generate Trigger when counter is updated with CNTIN */ +#if defined(FSL_FEATURE_FTM_HAS_RELOAD_INITIALIZATION_TRIGGER) && (FSL_FEATURE_FTM_HAS_RELOAD_INITIALIZATION_TRIGGER) kFTM_ReloadInitTrigger = (1U << 7) /*!< Available on certain SoC's, trigger on reload point */ +#endif } ftm_external_trigger_t; /*! @brief FlexTimer PWM sync options to update registers with buffer */ @@ -309,6 +305,7 @@ typedef enum _ftm_status_flags kFTM_ReloadFlag = (1U << 11) /*!< Reload Flag; Available only on certain SoC's */ } ftm_status_flags_t; +#if !(defined(FSL_FEATURE_FTM_HAS_NO_QDCTRL) && FSL_FEATURE_FTM_HAS_NO_QDCTRL) /*! * @brief List of FTM Quad Decoder flags. */ @@ -319,6 +316,7 @@ enum _ftm_quad_decoder_flags kFTM_QuadDecoderCountingOverflowOnTopFlag = FTM_QDCTRL_TOFDIR_MASK, /*!< Indicates if the TOF bit was set on the top or the bottom of counting. */ }; +#endif /*! * @brief FTM configuration structure @@ -465,6 +463,27 @@ void FTM_UpdatePwmDutycycle(FTM_Type *base, */ void FTM_UpdateChnlEdgeLevelSelect(FTM_Type *base, ftm_chnl_t chnlNumber, uint8_t level); +/*! + * @brief Configures the PWM mode parameters. + * + * Call this function to configure the PWM signal mode, duty cycle in ticks, and edge. Use this + * function to configure all FTM channels that are used to output a PWM signal. + * Please note that: This API is similar with FTM_SetupPwm() API, but will not set the timer period, + * and this API will set channel match value in timer ticks, not period percent. + * + * @param base FTM peripheral base address + * @param chnlParams Array of PWM channel parameters to configure the channel(s) + * @param numOfChnls Number of channels to configure; This should be the size of the array passed in + * @param mode PWM operation mode, options available in enumeration ::ftm_pwm_mode_t + * + * @return kStatus_Success if the PWM setup was successful + * kStatus_Error on failure + */ +status_t FTM_SetupPwmMode(FTM_Type *base, + const ftm_chnl_pwm_config_param_t *chnlParams, + uint8_t numOfChnls, + ftm_pwm_mode_t mode); + /*! * @brief Enables capturing an input signal on the channel using the function parameters. * @@ -875,6 +894,7 @@ void FTM_SetupQuadDecode(FTM_Type *base, const ftm_phase_params_t *phaseBParams, ftm_quad_decode_mode_t quadMode); +#if !(defined(FSL_FEATURE_FTM_HAS_NO_QDCTRL) && FSL_FEATURE_FTM_HAS_NO_QDCTRL) /*! * @brief Gets the FTM Quad Decoder flags. * @@ -885,12 +905,13 @@ static inline uint32_t FTM_GetQuadDecoderFlags(FTM_Type *base) { return base->QDCTRL & (FTM_QDCTRL_QUADIR_MASK | FTM_QDCTRL_TOFDIR_MASK); } +#endif /*! * @brief Sets the modulo values for Quad Decoder. * - * The modulo values configure the minimum and maximum values that the Quad decoder counter can reach. After the counter goes - * over, the counter value goes to the other side and decrease/increase again. + * The modulo values configure the minimum and maximum values that the Quad decoder counter can reach. After the + * counter goes over, the counter value goes to the other side and decrease/increase again. * * @param base FTM peripheral base address. * @param startValue The low limit value for Quad Decoder counter. @@ -964,6 +985,33 @@ static inline void FTM_SetWriteProtection(FTM_Type *base, bool enable) } } +#if defined(FSL_FEATURE_FTM_HAS_DMA_SUPPORT) && FSL_FEATURE_FTM_HAS_DMA_SUPPORT +/*! + * @brief Enable DMA transfer or not. + * + * Note: CHnIE bit needs to be set when calling this API. The channel DMA transfer request + * is generated and the channel interrupt is not generated if (CHnF = 1) when DMA and CHnIE + * bits are set. + * + * @param base FTM peripheral base address. + * @param chnlNumber Channel to be configured + * @param enable true to enable, false to disable + */ +static inline void FTM_EnableDmaTransfer(FTM_Type *base, ftm_chnl_t chnlNumber, bool enable) +{ + if (enable) + { + /* Enable DMA transfer */ + base->CONTROLS[chnlNumber].CnSC |= FTM_CnSC_DMA_MASK; + } + else + { + /* Disable DMA transfer */ + base->CONTROLS[chnlNumber].CnSC &= ~FTM_CnSC_DMA_MASK; + } +} +#endif /* FSL_FEATURE_FTM_HAS_DMA_SUPPORT */ + #if defined(__cplusplus) } #endif diff --git a/ext/hal/nxp/mcux/drivers/kinetis/fsl_gpio.c b/ext/hal/nxp/mcux/drivers/kinetis/fsl_gpio.c index b40ee3ac11c..60e62ab8c7a 100644 --- a/ext/hal/nxp/mcux/drivers/kinetis/fsl_gpio.c +++ b/ext/hal/nxp/mcux/drivers/kinetis/fsl_gpio.c @@ -1,45 +1,44 @@ /* * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP + * Copyright 2016-2018 NXP + * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * SPDX-License-Identifier: BSD-3-Clause */ #include "fsl_gpio.h" +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.gpio" +#endif + /******************************************************************************* * Variables ******************************************************************************/ + +#if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT) static PORT_Type *const s_portBases[] = PORT_BASE_PTRS; static GPIO_Type *const s_gpioBases[] = GPIO_BASE_PTRS; +#endif + +#if defined(FSL_FEATURE_SOC_FGPIO_COUNT) && FSL_FEATURE_SOC_FGPIO_COUNT + +#if defined(FSL_FEATURE_PCC_HAS_FGPIO_CLOCK_GATE_CONTROL) && FSL_FEATURE_PCC_HAS_FGPIO_CLOCK_GATE_CONTROL + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/*! @brief Array to map FGPIO instance number to clock name. */ +static const clock_ip_name_t s_fgpioClockName[] = FGPIO_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#endif /* FSL_FEATURE_PCC_HAS_FGPIO_CLOCK_GATE_CONTROL */ + +#endif /* FSL_FEATURE_SOC_FGPIO_COUNT */ /******************************************************************************* * Prototypes ******************************************************************************/ - +#if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT) /*! * @brief Gets the GPIO instance according to the GPIO base * @@ -47,11 +46,11 @@ static GPIO_Type *const s_gpioBases[] = GPIO_BASE_PTRS; * @retval GPIO instance */ static uint32_t GPIO_GetInstance(GPIO_Type *base); - +#endif /******************************************************************************* * Code ******************************************************************************/ - +#if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT) static uint32_t GPIO_GetInstance(GPIO_Type *base) { uint32_t instance; @@ -69,7 +68,33 @@ static uint32_t GPIO_GetInstance(GPIO_Type *base) return instance; } - +#endif +/*! + * brief Initializes a GPIO pin used by the board. + * + * To initialize the GPIO, define a pin configuration, as either input or output, in the user file. + * Then, call the GPIO_PinInit() function. + * + * This is an example to define an input pin or an output pin configuration. + * code + * // Define a digital input pin configuration, + * gpio_pin_config_t config = + * { + * kGPIO_DigitalInput, + * 0, + * } + * //Define a digital output pin configuration, + * gpio_pin_config_t config = + * { + * kGPIO_DigitalOutput, + * 0, + * } + * endcode + * + * param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.) + * param pin GPIO port pin number + * param config GPIO pin configuration pointer + */ void GPIO_PinInit(GPIO_Type *base, uint32_t pin, const gpio_pin_config_t *config) { assert(config); @@ -80,12 +105,26 @@ void GPIO_PinInit(GPIO_Type *base, uint32_t pin, const gpio_pin_config_t *config } else { - GPIO_WritePinOutput(base, pin, config->outputLogic); + GPIO_PinWrite(base, pin, config->outputLogic); base->PDDR |= (1U << pin); } } -uint32_t GPIO_GetPinsInterruptFlags(GPIO_Type *base) +#if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT) +/*! + * brief Reads the GPIO port interrupt status flag. + * + * If a pin is configured to generate the DMA request, the corresponding flag + * is cleared automatically at the completion of the requested DMA transfer. + * Otherwise, the flag remains set until a logic one is written to that flag. + * If configured for a level sensitive interrupt that remains asserted, the flag + * is set again immediately. + * + * param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.) + * retval The current GPIO port interrupt status flag, for example, 0x00010001 means the + * pin 0 and 17 have the interrupt. + */ +uint32_t GPIO_PortGetInterruptFlags(GPIO_Type *base) { uint8_t instance; PORT_Type *portBase; @@ -94,7 +133,13 @@ uint32_t GPIO_GetPinsInterruptFlags(GPIO_Type *base) return portBase->ISFR; } -void GPIO_ClearPinsInterruptFlags(GPIO_Type *base, uint32_t mask) +/*! + * brief Clears multiple GPIO pin interrupt status flags. + * + * param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.) + * param mask GPIO pin number macro + */ +void GPIO_PortClearInterruptFlags(GPIO_Type *base, uint32_t mask) { uint8_t instance; PORT_Type *portBase; @@ -102,8 +147,19 @@ void GPIO_ClearPinsInterruptFlags(GPIO_Type *base, uint32_t mask) portBase = s_portBases[instance]; portBase->ISFR = mask; } +#endif #if defined(FSL_FEATURE_GPIO_HAS_ATTRIBUTE_CHECKER) && FSL_FEATURE_GPIO_HAS_ATTRIBUTE_CHECKER +/*! + * brief The GPIO module supports a device-specific number of data ports, organized as 32-bit + * words. Each 32-bit data port includes a GACR register, which defines the byte-level + * attributes required for a successful access to the GPIO programming model. The attribute controls for the 4 data + * bytes in the GACR follow a standard little endian + * data convention. + * + * param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.) + * param mask GPIO pin number macro + */ void GPIO_CheckAttributeBytes(GPIO_Type *base, gpio_checker_attribute_t attribute) { base->GACR = ((uint32_t)attribute << GPIO_GACR_ACB0_SHIFT) | ((uint32_t)attribute << GPIO_GACR_ACB1_SHIFT) | @@ -116,11 +172,13 @@ void GPIO_CheckAttributeBytes(GPIO_Type *base, gpio_checker_attribute_t attribut /******************************************************************************* * Variables ******************************************************************************/ +#if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT) static FGPIO_Type *const s_fgpioBases[] = FGPIO_BASE_PTRS; - +#endif /******************************************************************************* * Prototypes ******************************************************************************/ +#if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT) /*! * @brief Gets the FGPIO instance according to the GPIO base * @@ -128,11 +186,11 @@ static FGPIO_Type *const s_fgpioBases[] = FGPIO_BASE_PTRS; * @retval FGPIO instance */ static uint32_t FGPIO_GetInstance(FGPIO_Type *base); - +#endif /******************************************************************************* * Code ******************************************************************************/ - +#if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT) static uint32_t FGPIO_GetInstance(FGPIO_Type *base) { uint32_t instance; @@ -150,7 +208,50 @@ static uint32_t FGPIO_GetInstance(FGPIO_Type *base) return instance; } +#endif +#if defined(FSL_FEATURE_PCC_HAS_FGPIO_CLOCK_GATE_CONTROL) && FSL_FEATURE_PCC_HAS_FGPIO_CLOCK_GATE_CONTROL +/*! + * brief Initializes the FGPIO peripheral. + * + * This function ungates the FGPIO clock. + * + * param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.) + */ +void FGPIO_PortInit(FGPIO_Type *base) +{ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Ungate FGPIO periphral clock */ + CLOCK_EnableClock(s_fgpioClockName[FGPIO_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} +#endif /* FSL_FEATURE_PCC_HAS_FGPIO_CLOCK_GATE_CONTROL */ +/*! + * brief Initializes a FGPIO pin used by the board. + * + * To initialize the FGPIO driver, define a pin configuration, as either input or output, in the user file. + * Then, call the FGPIO_PinInit() function. + * + * This is an example to define an input pin or an output pin configuration: + * code + * // Define a digital input pin configuration, + * gpio_pin_config_t config = + * { + * kGPIO_DigitalInput, + * 0, + * } + * //Define a digital output pin configuration, + * gpio_pin_config_t config = + * { + * kGPIO_DigitalOutput, + * 0, + * } + * endcode + * + * param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.) + * param pin FGPIO port pin number + * param config FGPIO pin configuration pointer + */ void FGPIO_PinInit(FGPIO_Type *base, uint32_t pin, const gpio_pin_config_t *config) { assert(config); @@ -161,12 +262,25 @@ void FGPIO_PinInit(FGPIO_Type *base, uint32_t pin, const gpio_pin_config_t *conf } else { - FGPIO_WritePinOutput(base, pin, config->outputLogic); + FGPIO_PinWrite(base, pin, config->outputLogic); base->PDDR |= (1U << pin); } } - -uint32_t FGPIO_GetPinsInterruptFlags(FGPIO_Type *base) +#if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT) +/*! + * brief Reads the FGPIO port interrupt status flag. + * + * If a pin is configured to generate the DMA request, the corresponding flag + * is cleared automatically at the completion of the requested DMA transfer. + * Otherwise, the flag remains set until a logic one is written to that flag. + * If configured for a level-sensitive interrupt that remains asserted, the flag + * is set again immediately. + * + * param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.) + * retval The current FGPIO port interrupt status flags, for example, 0x00010001 means the + * pin 0 and 17 have the interrupt. + */ +uint32_t FGPIO_PortGetInterruptFlags(FGPIO_Type *base) { uint8_t instance; instance = FGPIO_GetInstance(base); @@ -175,7 +289,13 @@ uint32_t FGPIO_GetPinsInterruptFlags(FGPIO_Type *base) return portBase->ISFR; } -void FGPIO_ClearPinsInterruptFlags(FGPIO_Type *base, uint32_t mask) +/*! + * brief Clears the multiple FGPIO pin interrupt status flag. + * + * param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.) + * param mask FGPIO pin number macro + */ +void FGPIO_PortClearInterruptFlags(FGPIO_Type *base, uint32_t mask) { uint8_t instance; instance = FGPIO_GetInstance(base); @@ -183,8 +303,18 @@ void FGPIO_ClearPinsInterruptFlags(FGPIO_Type *base, uint32_t mask) portBase = s_portBases[instance]; portBase->ISFR = mask; } - +#endif #if defined(FSL_FEATURE_FGPIO_HAS_ATTRIBUTE_CHECKER) && FSL_FEATURE_FGPIO_HAS_ATTRIBUTE_CHECKER +/*! + * brief The FGPIO module supports a device-specific number of data ports, organized as 32-bit + * words. Each 32-bit data port includes a GACR register, which defines the byte-level + * attributes required for a successful access to the GPIO programming model. The attribute controls for the 4 data + * bytes in the GACR follow a standard little endian + * data convention. + * + * param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.) + * param mask FGPIO pin number macro + */ void FGPIO_CheckAttributeBytes(FGPIO_Type *base, gpio_checker_attribute_t attribute) { base->GACR = (attribute << FGPIO_GACR_ACB0_SHIFT) | (attribute << FGPIO_GACR_ACB1_SHIFT) | diff --git a/ext/hal/nxp/mcux/drivers/kinetis/fsl_gpio.h b/ext/hal/nxp/mcux/drivers/kinetis/fsl_gpio.h index 410e2b8ee46..ba98fb23646 100644 --- a/ext/hal/nxp/mcux/drivers/kinetis/fsl_gpio.h +++ b/ext/hal/nxp/mcux/drivers/kinetis/fsl_gpio.h @@ -1,31 +1,9 @@ /* * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP + * Copyright 2016-2018 NXP + * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * SPDX-License-Identifier: BSD-3-Clause */ #ifndef _FSL_GPIO_H_ @@ -44,8 +22,8 @@ /*! @name Driver version */ /*@{*/ -/*! @brief GPIO driver version 2.1.1. */ -#define FSL_GPIO_DRIVER_VERSION (MAKE_VERSION(2, 1, 1)) +/*! @brief GPIO driver version 2.3.1. */ +#define FSL_GPIO_DRIVER_VERSION (MAKE_VERSION(2, 3, 1)) /*@}*/ /*! @brief GPIO direction definition */ @@ -75,7 +53,7 @@ typedef enum _gpio_checker_attribute 0x06U, /*!< User nonsecure:None; User Secure:None; Privileged Secure:Read */ kGPIO_UsernonsecureNUsersecureNPrivilegedsecureN = 0x07U, /*!< User nonsecure:None; User Secure:None; Privileged Secure:None */ - kGPIO_IgnoreAttributeCheck = 0x10U, /*!< Ignores the attribute check */ + kGPIO_IgnoreAttributeCheck = 0x80U, /*!< Ignores the attribute check */ } gpio_checker_attribute_t; #endif @@ -94,6 +72,26 @@ typedef struct _gpio_pin_config uint8_t outputLogic; /*!< Set a default output logic, which has no use in input */ } gpio_pin_config_t; +#if (defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT) +/*! @brief Configures the interrupt generation condition. */ +typedef enum _gpio_interrupt_config +{ + kGPIO_InterruptStatusFlagDisabled = 0x0U, /*!< Interrupt status flag is disabled. */ + kGPIO_DMARisingEdge = 0x1U, /*!< ISF flag and DMA request on rising edge. */ + kGPIO_DMAFallingEdge = 0x2U, /*!< ISF flag and DMA request on falling edge. */ + kGPIO_DMAEitherEdge = 0x3U, /*!< ISF flag and DMA request on either edge. */ + kGPIO_FlagRisingEdge = 0x05U, /*!< Flag sets on rising edge. */ + kGPIO_FlagFallingEdge = 0x06U, /*!< Flag sets on falling edge. */ + kGPIO_FlagEitherEdge = 0x07U, /*!< Flag sets on either edge. */ + kGPIO_InterruptLogicZero = 0x8U, /*!< Interrupt when logic zero. */ + kGPIO_InterruptRisingEdge = 0x9U, /*!< Interrupt on rising edge. */ + kGPIO_InterruptFallingEdge = 0xAU, /*!< Interrupt on falling edge. */ + kGPIO_InterruptEitherEdge = 0xBU, /*!< Interrupt on either edge. */ + kGPIO_InterruptLogicOne = 0xCU, /*!< Interrupt when logic one. */ + kGPIO_ActiveHighTriggerOutputEnable = 0xDU, /*!< Enable active high-trigger output. */ + kGPIO_ActiveLowTriggerOutputEnable = 0xEU, /*!< Enable active low-trigger output. */ +} gpio_interrupt_config_t; +#endif /*! @} */ /******************************************************************************* @@ -154,7 +152,7 @@ void GPIO_PinInit(GPIO_Type *base, uint32_t pin, const gpio_pin_config_t *config * - 0: corresponding pin output low-logic level. * - 1: corresponding pin output high-logic level. */ -static inline void GPIO_WritePinOutput(GPIO_Type *base, uint32_t pin, uint8_t output) +static inline void GPIO_PinWrite(GPIO_Type *base, uint32_t pin, uint8_t output) { if (output == 0U) { @@ -172,7 +170,7 @@ static inline void GPIO_WritePinOutput(GPIO_Type *base, uint32_t pin, uint8_t ou * @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.) * @param mask GPIO pin number macro */ -static inline void GPIO_SetPinsOutput(GPIO_Type *base, uint32_t mask) +static inline void GPIO_PortSet(GPIO_Type *base, uint32_t mask) { base->PSOR = mask; } @@ -183,7 +181,7 @@ static inline void GPIO_SetPinsOutput(GPIO_Type *base, uint32_t mask) * @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.) * @param mask GPIO pin number macro */ -static inline void GPIO_ClearPinsOutput(GPIO_Type *base, uint32_t mask) +static inline void GPIO_PortClear(GPIO_Type *base, uint32_t mask) { base->PCOR = mask; } @@ -194,10 +192,11 @@ static inline void GPIO_ClearPinsOutput(GPIO_Type *base, uint32_t mask) * @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.) * @param mask GPIO pin number macro */ -static inline void GPIO_TogglePinsOutput(GPIO_Type *base, uint32_t mask) +static inline void GPIO_PortToggle(GPIO_Type *base, uint32_t mask) { base->PTOR = mask; } + /*@}*/ /*! @name GPIO Input Operations */ @@ -212,15 +211,16 @@ static inline void GPIO_TogglePinsOutput(GPIO_Type *base, uint32_t mask) * - 0: corresponding pin input low-logic level. * - 1: corresponding pin input high-logic level. */ -static inline uint32_t GPIO_ReadPinInput(GPIO_Type *base, uint32_t pin) +static inline uint32_t GPIO_PinRead(GPIO_Type *base, uint32_t pin) { return (((base->PDIR) >> pin) & 0x01U); } + /*@}*/ /*! @name GPIO Interrupt */ /*@{*/ - +#if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT) /*! * @brief Reads the GPIO port interrupt status flag. * @@ -234,7 +234,7 @@ static inline uint32_t GPIO_ReadPinInput(GPIO_Type *base, uint32_t pin) * @retval The current GPIO port interrupt status flag, for example, 0x00010001 means the * pin 0 and 17 have the interrupt. */ -uint32_t GPIO_GetPinsInterruptFlags(GPIO_Type *base); +uint32_t GPIO_PortGetInterruptFlags(GPIO_Type *base); /*! * @brief Clears multiple GPIO pin interrupt status flags. @@ -242,7 +242,83 @@ uint32_t GPIO_GetPinsInterruptFlags(GPIO_Type *base); * @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.) * @param mask GPIO pin number macro */ -void GPIO_ClearPinsInterruptFlags(GPIO_Type *base, uint32_t mask); +void GPIO_PortClearInterruptFlags(GPIO_Type *base, uint32_t mask); +#else +/*! + * @brief Configures the gpio pin interrupt/DMA request. + * + * @param base GPIO peripheral base pointer. + * @param pin GPIO pin number. + * @param config GPIO pin interrupt configuration. + * - #kGPIO_InterruptStatusFlagDisabled: Interrupt/DMA request disabled. + * - #kGPIO_DMARisingEdge : DMA request on rising edge(if the DMA requests exit). + * - #kGPIO_DMAFallingEdge: DMA request on falling edge(if the DMA requests exit). + * - #kGPIO_DMAEitherEdge : DMA request on either edge(if the DMA requests exit). + * - #kGPIO_FlagRisingEdge : Flag sets on rising edge(if the Flag states exit). + * - #kGPIO_FlagFallingEdge : Flag sets on falling edge(if the Flag states exit). + * - #kGPIO_FlagEitherEdge : Flag sets on either edge(if the Flag states exit). + * - #kGPIO_InterruptLogicZero : Interrupt when logic zero. + * - #kGPIO_InterruptRisingEdge : Interrupt on rising edge. + * - #kGPIO_InterruptFallingEdge: Interrupt on falling edge. + * - #kGPIO_InterruptEitherEdge : Interrupt on either edge. + * - #kGPIO_InterruptLogicOne : Interrupt when logic one. + * - #kGPIO_ActiveHighTriggerOutputEnable : Enable active high-trigger output (if the trigger states exit). + * - #kGPIO_ActiveLowTriggerOutputEnable : Enable active low-trigger output (if the trigger states exit). + */ +static inline void GPIO_SetPinInterruptConfig(GPIO_Type *base, uint32_t pin, gpio_interrupt_config_t config) +{ + assert(base); + + base->ICR[pin] = (base->ICR[pin] & ~GPIO_ICR_IRQC_MASK) | GPIO_ICR_IRQC(config); +} + +/*! + * @brief Reads the GPIO DMA request flags. + * The corresponding flag will be cleared automatically at the completion of the requested + * DMA transfer + */ +static inline uint32_t GPIO_GetPinsDMARequestFlags(GPIO_Type *base) +{ + assert(base); + return (base->ISFR[1]); +} + +/*! + * @brief Sets the GPIO interrupt configuration in PCR register for multiple pins. + * + * @param base GPIO peripheral base pointer. + * @param mask GPIO pin number macro. + * @param config GPIO pin interrupt configuration. + * - #kGPIO_InterruptStatusFlagDisabled: Interrupt disabled. + * - #kGPIO_DMARisingEdge : DMA request on rising edge(if the DMA requests exit). + * - #kGPIO_DMAFallingEdge: DMA request on falling edge(if the DMA requests exit). + * - #kGPIO_DMAEitherEdge : DMA request on either edge(if the DMA requests exit). + * - #kGPIO_FlagRisingEdge : Flag sets on rising edge(if the Flag states exit). + * - #kGPIO_FlagFallingEdge : Flag sets on falling edge(if the Flag states exit). + * - #kGPIO_FlagEitherEdge : Flag sets on either edge(if the Flag states exit). + * - #kGPIO_InterruptLogicZero : Interrupt when logic zero. + * - #kGPIO_InterruptRisingEdge : Interrupt on rising edge. + * - #kGPIO_InterruptFallingEdge: Interrupt on falling edge. + * - #kGPIO_InterruptEitherEdge : Interrupt on either edge. + * - #kGPIO_InterruptLogicOne : Interrupt when logic one. + * - #kGPIO_ActiveHighTriggerOutputEnable : Enable active high-trigger output (if the trigger states exit). + * - #kGPIO_ActiveLowTriggerOutputEnable : Enable active low-trigger output (if the trigger states exit).. + */ +static inline void GPIO_SetMultipleInterruptPinsConfig(GPIO_Type *base, uint32_t mask, gpio_interrupt_config_t config) +{ + assert(base); + + if (mask & 0xffffU) + { + base->GICLR = (GPIO_ICR_IRQC(config)) | (mask & 0xffffU); + } + mask = mask >> 16; + if (mask) + { + base->GICHR = (GPIO_ICR_IRQC(config)) | (mask & 0xffffU); + } +} +#endif #if defined(FSL_FEATURE_GPIO_HAS_ATTRIBUTE_CHECKER) && FSL_FEATURE_GPIO_HAS_ATTRIBUTE_CHECKER /*! @@ -279,6 +355,15 @@ void GPIO_CheckAttributeBytes(GPIO_Type *base, gpio_checker_attribute_t attribut /*! @name FGPIO Configuration */ /*@{*/ +/*! + * @brief Initializes the FGPIO peripheral. + * + * This function ungates the FGPIO clock. + * + * @param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.) + */ +void FGPIO_PortInit(FGPIO_Type *base); + /*! * @brief Initializes a FGPIO pin used by the board. * @@ -321,7 +406,7 @@ void FGPIO_PinInit(FGPIO_Type *base, uint32_t pin, const gpio_pin_config_t *conf * - 0: corresponding pin output low-logic level. * - 1: corresponding pin output high-logic level. */ -static inline void FGPIO_WritePinOutput(FGPIO_Type *base, uint32_t pin, uint8_t output) +static inline void FGPIO_PinWrite(FGPIO_Type *base, uint32_t pin, uint8_t output) { if (output == 0U) { @@ -339,7 +424,7 @@ static inline void FGPIO_WritePinOutput(FGPIO_Type *base, uint32_t pin, uint8_t * @param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.) * @param mask FGPIO pin number macro */ -static inline void FGPIO_SetPinsOutput(FGPIO_Type *base, uint32_t mask) +static inline void FGPIO_PortSet(FGPIO_Type *base, uint32_t mask) { base->PSOR = mask; } @@ -350,7 +435,7 @@ static inline void FGPIO_SetPinsOutput(FGPIO_Type *base, uint32_t mask) * @param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.) * @param mask FGPIO pin number macro */ -static inline void FGPIO_ClearPinsOutput(FGPIO_Type *base, uint32_t mask) +static inline void FGPIO_PortClear(FGPIO_Type *base, uint32_t mask) { base->PCOR = mask; } @@ -361,7 +446,7 @@ static inline void FGPIO_ClearPinsOutput(FGPIO_Type *base, uint32_t mask) * @param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.) * @param mask FGPIO pin number macro */ -static inline void FGPIO_TogglePinsOutput(FGPIO_Type *base, uint32_t mask) +static inline void FGPIO_PortToggle(FGPIO_Type *base, uint32_t mask) { base->PTOR = mask; } @@ -379,7 +464,7 @@ static inline void FGPIO_TogglePinsOutput(FGPIO_Type *base, uint32_t mask) * - 0: corresponding pin input low-logic level. * - 1: corresponding pin input high-logic level. */ -static inline uint32_t FGPIO_ReadPinInput(FGPIO_Type *base, uint32_t pin) +static inline uint32_t FGPIO_PinRead(FGPIO_Type *base, uint32_t pin) { return (((base->PDIR) >> pin) & 0x01U); } @@ -387,6 +472,7 @@ static inline uint32_t FGPIO_ReadPinInput(FGPIO_Type *base, uint32_t pin) /*! @name FGPIO Interrupt */ /*@{*/ +#if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT) /*! * @brief Reads the FGPIO port interrupt status flag. @@ -401,7 +487,7 @@ static inline uint32_t FGPIO_ReadPinInput(FGPIO_Type *base, uint32_t pin) * @retval The current FGPIO port interrupt status flags, for example, 0x00010001 means the * pin 0 and 17 have the interrupt. */ -uint32_t FGPIO_GetPinsInterruptFlags(FGPIO_Type *base); +uint32_t FGPIO_PortGetInterruptFlags(FGPIO_Type *base); /*! * @brief Clears the multiple FGPIO pin interrupt status flag. @@ -409,8 +495,8 @@ uint32_t FGPIO_GetPinsInterruptFlags(FGPIO_Type *base); * @param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.) * @param mask FGPIO pin number macro */ -void FGPIO_ClearPinsInterruptFlags(FGPIO_Type *base, uint32_t mask); - +void FGPIO_PortClearInterruptFlags(FGPIO_Type *base, uint32_t mask); +#endif #if defined(FSL_FEATURE_GPIO_HAS_ATTRIBUTE_CHECKER) && FSL_FEATURE_GPIO_HAS_ATTRIBUTE_CHECKER /*! * @brief The FGPIO module supports a device-specific number of data ports, organized as 32-bit diff --git a/ext/hal/nxp/mcux/drivers/kinetis/fsl_i2c.c b/ext/hal/nxp/mcux/drivers/kinetis/fsl_i2c.c index 6c9770af256..4f95760dfa8 100644 --- a/ext/hal/nxp/mcux/drivers/kinetis/fsl_i2c.c +++ b/ext/hal/nxp/mcux/drivers/kinetis/fsl_i2c.c @@ -1,31 +1,9 @@ /* * Copyright (c) 2015, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP + * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * SPDX-License-Identifier: BSD-3-Clause */ #include "fsl_i2c.h" @@ -33,6 +11,11 @@ * Definitions ******************************************************************************/ +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.i2c" +#endif + /*! @brief i2c transfer state. */ enum _i2c_transfer_states { @@ -68,13 +51,6 @@ typedef void (*i2c_isr_t)(I2C_Type *base, void *i2cHandle); * Prototypes ******************************************************************************/ -/*! - * @brief Get instance number for I2C module. - * - * @param base I2C peripheral base address. - */ -uint32_t I2C_GetInstance(I2C_Type *base); - /*! * @brief Set SCL/SDA hold time, this API receives SCL stop hold time, calculate the * closest SCL divider and MULT value for the SDA hold time, SCL start and SCL stop @@ -134,6 +110,9 @@ static void I2C_TransferCommonIRQHandler(I2C_Type *base, void *handle); * Variables ******************************************************************************/ +/*! @brief Pointers to i2c bases for each instance. */ +I2C_Type *const s_i2cBases[] = I2C_BASE_PTRS; + /*! @brief Pointers to i2c handles for each instance. */ static void *s_i2cHandle[FSL_FEATURE_SOC_I2C_COUNT] = {NULL}; @@ -144,9 +123,6 @@ static const uint16_t s_i2cDividerTable[] = { 160, 192, 224, 256, 288, 320, 384, 480, 320, 384, 448, 512, 576, 640, 768, 960, 640, 768, 896, 1024, 1152, 1280, 1536, 1920, 1280, 1536, 1792, 2048, 2304, 2560, 3072, 3840}; -/*! @brief Pointers to i2c bases for each instance. */ -static I2C_Type *const s_i2cBases[] = I2C_BASE_PTRS; - /*! @brief Pointers to i2c IRQ number for each instance. */ static const IRQn_Type s_i2cIrqs[] = I2C_IRQS; @@ -165,6 +141,11 @@ static i2c_isr_t s_i2cSlaveIsr; * Codes ******************************************************************************/ +/*! + * brief Get instance number for I2C module. + * + * param base I2C peripheral base address. + */ uint32_t I2C_GetInstance(I2C_Type *base) { uint32_t instance; @@ -208,7 +189,7 @@ static void I2C_SetHoldTime(I2C_Type *base, uint32_t sclStopHoldTime_ns, uint32_ for (i = 0u; i < sizeof(s_i2cDividerTable) / sizeof(s_i2cDividerTable[0]); ++i) { /* Assume SCL hold(stop) value = s_i2cDividerTable[i]/2. */ - computedSclHoldTime = ((multiplier * s_i2cDividerTable[i]) * 500000000U) / sourceClock_Hz; + computedSclHoldTime = ((multiplier * s_i2cDividerTable[i]) * 500000U) / (sourceClock_Hz / 1000U); absError = sclStopHoldTime_ns > computedSclHoldTime ? (sclStopHoldTime_ns - computedSclHoldTime) : (computedSclHoldTime - sclStopHoldTime_ns); @@ -256,8 +237,36 @@ static status_t I2C_InitTransferStateMachine(I2C_Type *base, i2c_master_handle_t /* Clear all status before transfer. */ I2C_MasterClearStatusFlags(base, kClearFlags); + /* Handle no start option. */ + if (handle->transfer.flags & kI2C_TransferNoStartFlag) + { + /* No need to send start flag, directly go to send command or data */ + if (handle->transfer.subaddressSize > 0) + { + handle->state = kSendCommandState; + } + else + { + if (direction == kI2C_Write) + { + /* Next state, send data. */ + handle->state = kSendDataState; + } + else + { + /* Only support write with no stop signal. */ + return kStatus_InvalidArgument; + } + } + + /* Wait for TCF bit and manually trigger tx interrupt. */ + while (!(base->S & kI2C_TransferCompleteFlag)) + { + } + I2C_MasterTransferHandleIRQ(base, handle); + } /* If repeated start is requested, send repeated start. */ - if (handle->transfer.flags & kI2C_TransferRepeatedStartFlag) + else if (handle->transfer.flags & kI2C_TransferRepeatedStartFlag) { result = I2C_MasterRepeatedStart(base, handle->transfer.slaveAddress, direction); } @@ -362,16 +371,19 @@ static status_t I2C_MasterTransferRunStateMachine(I2C_Type *base, i2c_master_han { if (handle->transfer.direction == kI2C_Write) { - /* Next state, send data. */ - handle->state = kSendDataState; - /* Send first byte of data. */ if (handle->transfer.dataSize > 0) { + /* Next state, send data. */ + handle->state = kSendDataState; base->D = *handle->transfer.data; handle->transfer.data++; handle->transfer.dataSize--; } + else + { + *isDone = true; + } } else { @@ -469,6 +481,31 @@ static void I2C_TransferCommonIRQHandler(I2C_Type *base, void *handle) __DSB(); } +/*! + * brief Initializes the I2C peripheral. Call this API to ungate the I2C clock + * and configure the I2C with master configuration. + * + * note This API should be called at the beginning of the application. + * Otherwise, any operation to the I2C module can cause a hard fault + * because the clock is not enabled. The configuration structure can be custom filled + * or it can be set with default values by using the I2C_MasterGetDefaultConfig(). + * After calling this API, the master is ready to transfer. + * This is an example. + * code + * i2c_master_config_t config = { + * .enableMaster = true, + * .enableStopHold = false, + * .highDrive = false, + * .baudRate_Bps = 100000, + * .glitchFilterWidth = 0 + * }; + * I2C_MasterInit(I2C0, &config, 12000000U); + * endcode + * + * param base I2C base pointer + * param masterConfig A pointer to the master configuration structure + * param srcClock_Hz I2C peripheral clock frequency in Hz + */ void I2C_MasterInit(I2C_Type *base, const i2c_master_config_t *masterConfig, uint32_t srcClock_Hz) { assert(masterConfig && srcClock_Hz); @@ -531,6 +568,11 @@ void I2C_MasterInit(I2C_Type *base, const i2c_master_config_t *masterConfig, uin base->C1 = I2C_C1_IICEN(masterConfig->enableMaster); } +/*! + * brief De-initializes the I2C master peripheral. Call this API to gate the I2C clock. + * The I2C master module can't work unless the I2C_MasterInit is called. + * param base I2C base pointer + */ void I2C_MasterDeinit(I2C_Type *base) { /* Disable I2C module. */ @@ -542,10 +584,26 @@ void I2C_MasterDeinit(I2C_Type *base) #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ } +/*! + * brief Sets the I2C master configuration structure to default values. + * + * The purpose of this API is to get the configuration structure initialized for use in the I2C_MasterConfigure(). + * Use the initialized structure unchanged in the I2C_MasterConfigure() or modify + * the structure before calling the I2C_MasterConfigure(). + * This is an example. + * code + * i2c_master_config_t config; + * I2C_MasterGetDefaultConfig(&config); + * endcode + * param masterConfig A pointer to the master configuration structure. +*/ void I2C_MasterGetDefaultConfig(i2c_master_config_t *masterConfig) { assert(masterConfig); + /* Initializes the configure structure to zero. */ + memset(masterConfig, 0, sizeof(*masterConfig)); + /* Default baud rate at 100kbps. */ masterConfig->baudRate_Bps = 100000U; @@ -566,6 +624,16 @@ void I2C_MasterGetDefaultConfig(i2c_master_config_t *masterConfig) masterConfig->enableMaster = true; } +/*! + * brief Enables I2C interrupt requests. + * + * param base I2C base pointer + * param mask interrupt source + * The parameter can be combination of the following source if defined: + * arg kI2C_GlobalInterruptEnable + * arg kI2C_StopDetectInterruptEnable/kI2C_StartDetectInterruptEnable + * arg kI2C_SdaTimeoutInterruptEnable + */ void I2C_EnableInterrupts(I2C_Type *base, uint32_t mask) { #ifdef I2C_HAS_STOP_DETECT @@ -606,6 +674,16 @@ void I2C_EnableInterrupts(I2C_Type *base, uint32_t mask) #endif /* FSL_FEATURE_I2C_HAS_START_STOP_DETECT */ } +/*! + * brief Disables I2C interrupt requests. + * + * param base I2C base pointer + * param mask interrupt source + * The parameter can be combination of the following source if defined: + * arg kI2C_GlobalInterruptEnable + * arg kI2C_StopDetectInterruptEnable/kI2C_StartDetectInterruptEnable + * arg kI2C_SdaTimeoutInterruptEnable + */ void I2C_DisableInterrupts(I2C_Type *base, uint32_t mask) { if (mask & kI2C_GlobalInterruptEnable) @@ -628,6 +706,13 @@ void I2C_DisableInterrupts(I2C_Type *base, uint32_t mask) #endif /* FSL_FEATURE_I2C_HAS_START_STOP_DETECT */ } +/*! + * brief Sets the I2C master transfer baud rate. + * + * param base I2C base pointer + * param baudRate_Bps the baud rate value in bps + * param srcClock_Hz Source clock + */ void I2C_MasterSetBaudRate(I2C_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz) { uint32_t multiplier; @@ -670,6 +755,18 @@ void I2C_MasterSetBaudRate(I2C_Type *base, uint32_t baudRate_Bps, uint32_t srcCl base->F = I2C_F_MULT(bestMult) | I2C_F_ICR(bestIcr); } +/*! + * brief Sends a START on the I2C bus. + * + * This function is used to initiate a new master mode transfer by sending the START signal. + * The slave address is sent following the I2C START signal. + * + * param base I2C peripheral base pointer + * param address 7-bit slave device address. + * param direction Master transfer directions(transmit/receive). + * retval kStatus_Success Successfully send the start signal. + * retval kStatus_I2C_Busy Current bus is busy. + */ status_t I2C_MasterStart(I2C_Type *base, uint8_t address, i2c_direction_t direction) { status_t result = kStatus_Success; @@ -686,9 +783,20 @@ status_t I2C_MasterStart(I2C_Type *base, uint8_t address, i2c_direction_t direct base->C1 |= I2C_C1_MST_MASK | I2C_C1_TX_MASK; #if defined(FSL_FEATURE_I2C_HAS_DOUBLE_BUFFERING) && FSL_FEATURE_I2C_HAS_DOUBLE_BUFFERING +#if I2C_WAIT_TIMEOUT + uint32_t waitTimes = I2C_WAIT_TIMEOUT; + while ((!(base->S2 & I2C_S2_EMPTY_MASK)) && (--waitTimes)) + { + } + if (waitTimes == 0) + { + return kStatus_I2C_Timeout; + } +#else while (!(base->S2 & I2C_S2_EMPTY_MASK)) { } +#endif #endif /* FSL_FEATURE_I2C_HAS_DOUBLE_BUFFERING */ base->D = (((uint32_t)address) << 1U | ((direction == kI2C_Read) ? 1U : 0U)); @@ -697,6 +805,15 @@ status_t I2C_MasterStart(I2C_Type *base, uint8_t address, i2c_direction_t direct return result; } +/*! + * brief Sends a REPEATED START on the I2C bus. + * + * param base I2C peripheral base pointer + * param address 7-bit slave device address. + * param direction Master transfer directions(transmit/receive). + * retval kStatus_Success Successfully send the start signal. + * retval kStatus_I2C_Busy Current bus is busy but not occupied by current I2C master. + */ status_t I2C_MasterRepeatedStart(I2C_Type *base, uint8_t address, i2c_direction_t direction) { status_t result = kStatus_Success; @@ -727,9 +844,20 @@ status_t I2C_MasterRepeatedStart(I2C_Type *base, uint8_t address, i2c_direction_ } #if defined(FSL_FEATURE_I2C_HAS_DOUBLE_BUFFERING) && FSL_FEATURE_I2C_HAS_DOUBLE_BUFFERING +#if I2C_WAIT_TIMEOUT + uint32_t waitTimes = I2C_WAIT_TIMEOUT; + while ((!(base->S2 & I2C_S2_EMPTY_MASK)) && (--waitTimes)) + { + } + if (waitTimes == 0) + { + return kStatus_I2C_Timeout; + } +#else while (!(base->S2 & I2C_S2_EMPTY_MASK)) { } +#endif #endif /* FSL_FEATURE_I2C_HAS_DOUBLE_BUFFERING */ base->D = (((uint32_t)address) << 1U | ((direction == kI2C_Read) ? 1U : 0U)); @@ -738,27 +866,46 @@ status_t I2C_MasterRepeatedStart(I2C_Type *base, uint8_t address, i2c_direction_ return result; } +/*! + * brief Sends a STOP signal on the I2C bus. + * + * retval kStatus_Success Successfully send the stop signal. + * retval kStatus_I2C_Timeout Send stop signal failed, timeout. + */ status_t I2C_MasterStop(I2C_Type *base) { status_t result = kStatus_Success; - uint16_t timeout = UINT16_MAX; /* Issue the STOP command on the bus. */ base->C1 &= ~(I2C_C1_MST_MASK | I2C_C1_TX_MASK | I2C_C1_TXAK_MASK); - /* Wait until data transfer complete. */ - while ((base->S & kI2C_BusBusyFlag) && (--timeout)) +#if I2C_WAIT_TIMEOUT + uint32_t waitTimes = I2C_WAIT_TIMEOUT; + /* Wait until bus not busy. */ + while ((base->S & kI2C_BusBusyFlag) && (--waitTimes)) { } - if (timeout == 0) + if (waitTimes == 0) { result = kStatus_I2C_Timeout; } +#else + /* Wait until data transfer complete. */ + while (base->S & kI2C_BusBusyFlag) + { + } +#endif return result; } +/*! + * brief Gets the I2C status flags. + * + * param base I2C base pointer + * return status flag, use status flag to AND #_i2c_flags to get the related status. + */ uint32_t I2C_MasterGetStatusFlags(I2C_Type *base) { uint32_t statusFlags = base->S; @@ -782,15 +929,39 @@ uint32_t I2C_MasterGetStatusFlags(I2C_Type *base) return statusFlags; } +/*! + * brief Performs a polling send transaction on the I2C bus. + * + * param base The I2C peripheral base pointer. + * param txBuff The pointer to the data to be transferred. + * param txSize The length in bytes of the data to be transferred. + * param flags Transfer control flag to decide whether need to send a stop, use kI2C_TransferDefaultFlag +* to issue a stop and kI2C_TransferNoStop to not send a stop. + * retval kStatus_Success Successfully complete the data transmission. + * retval kStatus_I2C_ArbitrationLost Transfer error, arbitration lost. + * retval kStataus_I2C_Nak Transfer error, receive NAK during transfer. + */ status_t I2C_MasterWriteBlocking(I2C_Type *base, const uint8_t *txBuff, size_t txSize, uint32_t flags) { status_t result = kStatus_Success; uint8_t statusFlags = 0; +#if I2C_WAIT_TIMEOUT + uint32_t waitTimes = I2C_WAIT_TIMEOUT; + /* Wait until the data register is ready for transmit. */ + while ((!(base->S & kI2C_TransferCompleteFlag)) && (--waitTimes)) + { + } + if (waitTimes == 0) + { + return kStatus_I2C_Timeout; + } +#else /* Wait until the data register is ready for transmit. */ while (!(base->S & kI2C_TransferCompleteFlag)) { } +#endif /* Clear the IICIF flag. */ base->S = kI2C_IntPendingFlag; @@ -803,11 +974,22 @@ status_t I2C_MasterWriteBlocking(I2C_Type *base, const uint8_t *txBuff, size_t t /* Send a byte of data. */ base->D = *txBuff++; +#if I2C_WAIT_TIMEOUT + waitTimes = I2C_WAIT_TIMEOUT; + /* Wait until data transfer complete. */ + while ((!(base->S & kI2C_IntPendingFlag)) && (--waitTimes)) + { + } + if (waitTimes == 0) + { + return kStatus_I2C_Timeout; + } +#else /* Wait until data transfer complete. */ while (!(base->S & kI2C_IntPendingFlag)) { } - +#endif statusFlags = base->S; /* Clear the IICIF flag. */ @@ -845,6 +1027,21 @@ status_t I2C_MasterWriteBlocking(I2C_Type *base, const uint8_t *txBuff, size_t t return result; } +/*! + * brief Performs a polling receive transaction on the I2C bus. + * + * note The I2C_MasterReadBlocking function stops the bus before reading the final byte. + * Without stopping the bus prior for the final read, the bus issues another read, resulting + * in garbage data being read into the data register. + * + * param base I2C peripheral base pointer. + * param rxBuff The pointer to the data to store the received data. + * param rxSize The length in bytes of the data to be received. + * param flags Transfer control flag to decide whether need to send a stop, use kI2C_TransferDefaultFlag +* to issue a stop and kI2C_TransferNoStop to not send a stop. + * retval kStatus_Success Successfully complete the data transmission. + * retval kStatus_I2C_Timeout Send stop signal failed, timeout. + */ status_t I2C_MasterReadBlocking(I2C_Type *base, uint8_t *rxBuff, size_t rxSize, uint32_t flags) { status_t result = kStatus_Success; @@ -853,10 +1050,22 @@ status_t I2C_MasterReadBlocking(I2C_Type *base, uint8_t *rxBuff, size_t rxSize, /* Add this to avoid build warning. */ dummy++; +#if I2C_WAIT_TIMEOUT + uint32_t waitTimes = I2C_WAIT_TIMEOUT; + /* Wait until the data register is ready for transmit. */ + while ((!(base->S & kI2C_TransferCompleteFlag)) && (--waitTimes)) + { + } + if (waitTimes == 0) + { + return kStatus_I2C_Timeout; + } +#else /* Wait until the data register is ready for transmit. */ while (!(base->S & kI2C_TransferCompleteFlag)) { } +#endif /* Clear the IICIF flag. */ base->S = kI2C_IntPendingFlag; @@ -876,11 +1085,22 @@ status_t I2C_MasterReadBlocking(I2C_Type *base, uint8_t *rxBuff, size_t rxSize, while ((rxSize--)) { +#if I2C_WAIT_TIMEOUT + waitTimes = I2C_WAIT_TIMEOUT; + /* Wait until data transfer complete. */ + while ((!(base->S & kI2C_IntPendingFlag)) && (--waitTimes)) + { + } + if (waitTimes == 0) + { + return kStatus_I2C_Timeout; + } +#else /* Wait until data transfer complete. */ while (!(base->S & kI2C_IntPendingFlag)) { } - +#endif /* Clear the IICIF flag. */ base->S = kI2C_IntPendingFlag; @@ -912,6 +1132,20 @@ status_t I2C_MasterReadBlocking(I2C_Type *base, uint8_t *rxBuff, size_t rxSize, return result; } +/*! + * brief Performs a master polling transfer on the I2C bus. + * + * note The API does not return until the transfer succeeds or fails due + * to arbitration lost or receiving a NAK. + * + * param base I2C peripheral base address. + * param xfer Pointer to the transfer structure. + * retval kStatus_Success Successfully complete the data transmission. + * retval kStatus_I2C_Busy Previous transmission still not finished. + * retval kStatus_I2C_Timeout Transfer error, wait signal timeout. + * retval kStatus_I2C_ArbitrationLost Transfer error, arbitration lost. + * retval kStataus_I2C_Nak Transfer error, receive NAK during transfer. + */ status_t I2C_MasterTransferBlocking(I2C_Type *base, i2c_master_transfer_t *xfer) { assert(xfer); @@ -922,10 +1156,22 @@ status_t I2C_MasterTransferBlocking(I2C_Type *base, i2c_master_transfer_t *xfer) /* Clear all status before transfer. */ I2C_MasterClearStatusFlags(base, kClearFlags); - /* Wait until ready to complete. */ +#if I2C_WAIT_TIMEOUT + uint32_t waitTimes = I2C_WAIT_TIMEOUT; + /* Wait until the data register is ready for transmit. */ + while ((!(base->S & kI2C_TransferCompleteFlag)) && (--waitTimes)) + { + } + if (waitTimes == 0) + { + return kStatus_I2C_Timeout; + } +#else + /* Wait until the data register is ready for transmit. */ while (!(base->S & kI2C_TransferCompleteFlag)) { } +#endif /* Change to send write address when it's a read operation with command. */ if ((xfer->subaddressSize > 0) && (xfer->direction == kI2C_Read)) @@ -933,8 +1179,16 @@ status_t I2C_MasterTransferBlocking(I2C_Type *base, i2c_master_transfer_t *xfer) direction = kI2C_Write; } + /* Handle no start option, only support write with no start signal. */ + if (xfer->flags & kI2C_TransferNoStartFlag) + { + if (direction == kI2C_Read) + { + return kStatus_InvalidArgument; + } + } /* If repeated start is requested, send repeated start. */ - if (xfer->flags & kI2C_TransferRepeatedStartFlag) + else if (xfer->flags & kI2C_TransferRepeatedStartFlag) { result = I2C_MasterRepeatedStart(base, xfer->slaveAddress, direction); } @@ -943,30 +1197,45 @@ status_t I2C_MasterTransferBlocking(I2C_Type *base, i2c_master_transfer_t *xfer) result = I2C_MasterStart(base, xfer->slaveAddress, direction); } - /* Return if error. */ - if (result) + if (!(xfer->flags & kI2C_TransferNoStartFlag)) { - return result; - } - - while (!(base->S & kI2C_IntPendingFlag)) - { - } - - /* Check if there's transfer error. */ - result = I2C_CheckAndClearError(base, base->S); - - /* Return if error. */ - if (result) - { - if (result == kStatus_I2C_Nak) + /* Return if error. */ + if (result) { - result = kStatus_I2C_Addr_Nak; - - I2C_MasterStop(base); + return result; } - return result; +#if I2C_WAIT_TIMEOUT + waitTimes = I2C_WAIT_TIMEOUT; + /* Wait until data transfer complete. */ + while ((!(base->S & kI2C_IntPendingFlag)) && (--waitTimes)) + { + } + if (waitTimes == 0) + { + return kStatus_I2C_Timeout; + } +#else + /* Wait until data transfer complete. */ + while (!(base->S & kI2C_IntPendingFlag)) + { + } +#endif + /* Check if there's transfer error. */ + result = I2C_CheckAndClearError(base, base->S); + + /* Return if error. */ + if (result) + { + if (result == kStatus_I2C_Nak) + { + result = kStatus_I2C_Addr_Nak; + + I2C_MasterStop(base); + } + + return result; + } } /* Send subaddress. */ @@ -980,10 +1249,22 @@ status_t I2C_MasterTransferBlocking(I2C_Type *base, i2c_master_transfer_t *xfer) xfer->subaddressSize--; base->D = ((xfer->subaddress) >> (8 * xfer->subaddressSize)); +#if I2C_WAIT_TIMEOUT + waitTimes = I2C_WAIT_TIMEOUT; + /* Wait until data transfer complete. */ + while ((!(base->S & kI2C_IntPendingFlag)) && (--waitTimes)) + { + } + if (waitTimes == 0) + { + return kStatus_I2C_Timeout; + } +#else /* Wait until data transfer complete. */ while (!(base->S & kI2C_IntPendingFlag)) { } +#endif /* Check if there's transfer error. */ result = I2C_CheckAndClearError(base, base->S); @@ -998,7 +1279,7 @@ status_t I2C_MasterTransferBlocking(I2C_Type *base, i2c_master_transfer_t *xfer) return result; } - } while ((xfer->subaddressSize > 0) && (result == kStatus_Success)); + } while (xfer->subaddressSize > 0); if (xfer->direction == kI2C_Read) { @@ -1014,10 +1295,22 @@ status_t I2C_MasterTransferBlocking(I2C_Type *base, i2c_master_transfer_t *xfer) return result; } +#if I2C_WAIT_TIMEOUT + waitTimes = I2C_WAIT_TIMEOUT; + /* Wait until data transfer complete. */ + while ((!(base->S & kI2C_IntPendingFlag)) && (--waitTimes)) + { + } + if (waitTimes == 0) + { + return kStatus_I2C_Timeout; + } +#else /* Wait until data transfer complete. */ while (!(base->S & kI2C_IntPendingFlag)) { } +#endif /* Check if there's transfer error. */ result = I2C_CheckAndClearError(base, base->S); @@ -1037,10 +1330,21 @@ status_t I2C_MasterTransferBlocking(I2C_Type *base, i2c_master_transfer_t *xfer) } /* Transmit data. */ - if ((xfer->direction == kI2C_Write) && (xfer->dataSize > 0)) + if (xfer->direction == kI2C_Write) { - /* Send Data. */ - result = I2C_MasterWriteBlocking(base, xfer->data, xfer->dataSize, xfer->flags); + if (xfer->dataSize > 0) + { + /* Send Data. */ + result = I2C_MasterWriteBlocking(base, xfer->data, xfer->dataSize, xfer->flags); + } + else if (!(xfer->flags & kI2C_TransferNoStopFlag)) + { + /* Send stop. */ + result = I2C_MasterStop(base); + } + else + { + } } /* Receive Data. */ @@ -1052,6 +1356,14 @@ status_t I2C_MasterTransferBlocking(I2C_Type *base, i2c_master_transfer_t *xfer) return result; } +/*! + * brief Initializes the I2C handle which is used in transactional functions. + * + * param base I2C base pointer. + * param handle pointer to i2c_master_handle_t structure to store the transfer state. + * param callback pointer to user callback function. + * param userData user parameter passed to the callback function. + */ void I2C_MasterTransferCreateHandle(I2C_Type *base, i2c_master_handle_t *handle, i2c_master_transfer_callback_t callback, @@ -1078,6 +1390,21 @@ void I2C_MasterTransferCreateHandle(I2C_Type *base, EnableIRQ(s_i2cIrqs[instance]); } +/*! + * brief Performs a master interrupt non-blocking transfer on the I2C bus. + * + * note Calling the API returns immediately after transfer initiates. The user needs + * to call I2C_MasterGetTransferCount to poll the transfer status to check whether + * the transfer is finished. If the return status is not kStatus_I2C_Busy, the transfer + * is finished. + * + * param base I2C base pointer. + * param handle pointer to i2c_master_handle_t structure which stores the transfer state. + * param xfer pointer to i2c_master_transfer_t structure. + * retval kStatus_Success Successfully start the data transmission. + * retval kStatus_I2C_Busy Previous transmission still not finished. + * retval kStatus_I2C_Timeout Transfer error, wait signal timeout. + */ status_t I2C_MasterTransferNonBlocking(I2C_Type *base, i2c_master_handle_t *handle, i2c_master_transfer_t *xfer) { assert(handle); @@ -1105,11 +1432,25 @@ status_t I2C_MasterTransferNonBlocking(I2C_Type *base, i2c_master_handle_t *hand return result; } -void I2C_MasterTransferAbort(I2C_Type *base, i2c_master_handle_t *handle) +/*! + * brief Aborts an interrupt non-blocking transfer early. + * + * note This API can be called at any time when an interrupt non-blocking transfer initiates + * to abort the transfer early. + * + * param base I2C base pointer. + * param handle pointer to i2c_master_handle_t structure which stores the transfer state + * retval kStatus_I2C_Timeout Timeout during polling flag. + * retval kStatus_Success Successfully abort the transfer. + */ +status_t I2C_MasterTransferAbort(I2C_Type *base, i2c_master_handle_t *handle) { assert(handle); volatile uint8_t dummy = 0; +#if I2C_WAIT_TIMEOUT + uint32_t waitTimes = I2C_WAIT_TIMEOUT; +#endif /* Add this to avoid build warning. */ dummy++; @@ -1120,13 +1461,32 @@ void I2C_MasterTransferAbort(I2C_Type *base, i2c_master_handle_t *handle) /* Reset the state to idle. */ handle->state = kIdleState; + /* If the bus is already in use, but not by us */ + if (!(base->C1 & I2C_C1_MST_MASK)) + { + return kStatus_I2C_Busy; + } + /* Send STOP signal. */ if (handle->transfer.direction == kI2C_Read) { base->C1 |= I2C_C1_TXAK_MASK; + +#if I2C_WAIT_TIMEOUT + /* Wait until data transfer complete. */ + while ((!(base->S & kI2C_IntPendingFlag)) && (--waitTimes)) + { + } + if (waitTimes == 0) + { + return kStatus_I2C_Timeout; + } +#else + /* Wait until data transfer complete. */ while (!(base->S & kI2C_IntPendingFlag)) { } +#endif base->S = kI2C_IntPendingFlag; base->C1 &= ~(I2C_C1_MST_MASK | I2C_C1_TX_MASK | I2C_C1_TXAK_MASK); @@ -1134,14 +1494,37 @@ void I2C_MasterTransferAbort(I2C_Type *base, i2c_master_handle_t *handle) } else { +#if I2C_WAIT_TIMEOUT + /* Wait until data transfer complete. */ + while ((!(base->S & kI2C_IntPendingFlag)) && (--waitTimes)) + { + } + if (waitTimes == 0) + { + return kStatus_I2C_Timeout; + } +#else + /* Wait until data transfer complete. */ while (!(base->S & kI2C_IntPendingFlag)) { } +#endif base->S = kI2C_IntPendingFlag; base->C1 &= ~(I2C_C1_MST_MASK | I2C_C1_TX_MASK | I2C_C1_TXAK_MASK); } + + return kStatus_Success; } +/*! + * brief Gets the master transfer status during a interrupt non-blocking transfer. + * + * param base I2C base pointer. + * param handle pointer to i2c_master_handle_t structure which stores the transfer state. + * param count Number of bytes transferred so far by the non-blocking transaction. + * retval kStatus_InvalidArgument count is Invalid. + * retval kStatus_Success Successfully return the count. + */ status_t I2C_MasterTransferGetCount(I2C_Type *base, i2c_master_handle_t *handle, size_t *count) { assert(handle); @@ -1156,6 +1539,12 @@ status_t I2C_MasterTransferGetCount(I2C_Type *base, i2c_master_handle_t *handle, return kStatus_Success; } +/*! + * brief Master interrupt handler. + * + * param base I2C base pointer. + * param i2cHandle pointer to i2c_master_handle_t structure. + */ void I2C_MasterTransferHandleIRQ(I2C_Type *base, void *i2cHandle) { assert(i2cHandle); @@ -1200,6 +1589,33 @@ void I2C_MasterTransferHandleIRQ(I2C_Type *base, void *i2cHandle) } } +/*! + * brief Initializes the I2C peripheral. Call this API to ungate the I2C clock + * and initialize the I2C with the slave configuration. + * + * note This API should be called at the beginning of the application. + * Otherwise, any operation to the I2C module can cause a hard fault + * because the clock is not enabled. The configuration structure can partly be set + * with default values by I2C_SlaveGetDefaultConfig() or it can be custom filled by the user. + * This is an example. + * code + * i2c_slave_config_t config = { + * .enableSlave = true, + * .enableGeneralCall = false, + * .addressingMode = kI2C_Address7bit, + * .slaveAddress = 0x1DU, + * .enableWakeUp = false, + * .enablehighDrive = false, + * .enableBaudRateCtl = false, + * .sclStopHoldTime_ns = 4000 + * }; + * I2C_SlaveInit(I2C0, &config, 12000000U); + * endcode + * + * param base I2C base pointer + * param slaveConfig A pointer to the slave configuration structure + * param srcClock_Hz I2C peripheral clock frequency in Hz + */ void I2C_SlaveInit(I2C_Type *base, const i2c_slave_config_t *slaveConfig, uint32_t srcClock_Hz) { assert(slaveConfig); @@ -1262,6 +1678,11 @@ void I2C_SlaveInit(I2C_Type *base, const i2c_slave_config_t *slaveConfig, uint32 I2C_SetHoldTime(base, slaveConfig->sclStopHoldTime_ns, srcClock_Hz); } +/*! + * brief De-initializes the I2C slave peripheral. Calling this API gates the I2C clock. + * The I2C slave module can't work unless the I2C_SlaveInit is called to enable the clock. + * param base I2C base pointer + */ void I2C_SlaveDeinit(I2C_Type *base) { /* Disable I2C module. */ @@ -1273,10 +1694,25 @@ void I2C_SlaveDeinit(I2C_Type *base) #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ } +/*! + * brief Sets the I2C slave configuration structure to default values. + * + * The purpose of this API is to get the configuration structure initialized for use in the I2C_SlaveConfigure(). + * Modify fields of the structure before calling the I2C_SlaveConfigure(). + * This is an example. + * code + * i2c_slave_config_t config; + * I2C_SlaveGetDefaultConfig(&config); + * endcode + * param slaveConfig A pointer to the slave configuration structure. + */ void I2C_SlaveGetDefaultConfig(i2c_slave_config_t *slaveConfig) { assert(slaveConfig); + /* Initializes the configure structure to zero. */ + memset(slaveConfig, 0, sizeof(*slaveConfig)); + /* By default slave is addressed with 7-bit address. */ slaveConfig->addressingMode = kI2C_Address7bit; @@ -1301,6 +1737,16 @@ void I2C_SlaveGetDefaultConfig(i2c_slave_config_t *slaveConfig) slaveConfig->enableSlave = true; } +/*! + * brief Performs a polling send transaction on the I2C bus. + * + * param base The I2C peripheral base pointer. + * param txBuff The pointer to the data to be transferred. + * param txSize The length in bytes of the data to be transferred. + * retval kStatus_Success Successfully complete the data transmission. + * retval kStatus_I2C_ArbitrationLost Transfer error, arbitration lost. + * retval kStataus_I2C_Nak Transfer error, receive NAK during transfer. + */ status_t I2C_SlaveWriteBlocking(I2C_Type *base, const uint8_t *txBuff, size_t txSize) { status_t result = kStatus_Success; @@ -1320,11 +1766,22 @@ status_t I2C_SlaveWriteBlocking(I2C_Type *base, const uint8_t *txBuff, size_t tx base->S = kI2C_IntPendingFlag; #endif /* FSL_FEATURE_I2C_HAS_START_STOP_DETECT */ +#if I2C_WAIT_TIMEOUT + uint32_t waitTimes = I2C_WAIT_TIMEOUT; + /* Wait until data transfer complete. */ + while ((!(base->S & kI2C_AddressMatchFlag)) && (--waitTimes)) + { + } + if (waitTimes == 0) + { + return kStatus_I2C_Timeout; + } +#else /* Wait for address match flag. */ while (!(base->S & kI2C_AddressMatchFlag)) { } - +#endif /* Read dummy to release bus. */ dummy = base->D; @@ -1339,8 +1796,18 @@ status_t I2C_SlaveWriteBlocking(I2C_Type *base, const uint8_t *txBuff, size_t tx return result; } -void I2C_SlaveReadBlocking(I2C_Type *base, uint8_t *rxBuff, size_t rxSize) +/*! + * brief Performs a polling receive transaction on the I2C bus. + * + * param base I2C peripheral base pointer. + * param rxBuff The pointer to the data to store the received data. + * param rxSize The length in bytes of the data to be received. + * retval kStatus_Success Successfully complete data receive. + * retval kStatus_I2C_Timeout Wait status flag timeout. + */ +status_t I2C_SlaveReadBlocking(I2C_Type *base, uint8_t *rxBuff, size_t rxSize) { + status_t result = kStatus_Success; volatile uint8_t dummy = 0; /* Add this to avoid build warning. */ @@ -1358,6 +1825,26 @@ void I2C_SlaveReadBlocking(I2C_Type *base, uint8_t *rxBuff, size_t rxSize) base->S = kI2C_IntPendingFlag; #endif /* FSL_FEATURE_I2C_HAS_START_STOP_DETECT */ +#if I2C_WAIT_TIMEOUT + uint32_t waitTimes = I2C_WAIT_TIMEOUT; + /* Wait for address match and int pending flag. */ + while ((!(base->S & kI2C_AddressMatchFlag)) && (--waitTimes)) + { + } + if (waitTimes == 0) + { + return kStatus_I2C_Timeout; + } + + waitTimes = I2C_WAIT_TIMEOUT; + while ((!(base->S & kI2C_IntPendingFlag)) && (--waitTimes)) + { + } + if (waitTimes == 0) + { + return kStatus_I2C_Timeout; + } +#else /* Wait for address match and int pending flag. */ while (!(base->S & kI2C_AddressMatchFlag)) { @@ -1365,6 +1852,7 @@ void I2C_SlaveReadBlocking(I2C_Type *base, uint8_t *rxBuff, size_t rxSize) while (!(base->S & kI2C_IntPendingFlag)) { } +#endif /* Read dummy to release bus. */ dummy = base->D; @@ -1377,18 +1865,40 @@ void I2C_SlaveReadBlocking(I2C_Type *base, uint8_t *rxBuff, size_t rxSize) while (rxSize--) { +#if I2C_WAIT_TIMEOUT + waitTimes = I2C_WAIT_TIMEOUT; + /* Wait until data transfer complete. */ + while ((!(base->S & kI2C_IntPendingFlag)) && (--waitTimes)) + { + } + if (waitTimes == 0) + { + return kStatus_I2C_Timeout; + } +#else /* Wait until data transfer complete. */ while (!(base->S & kI2C_IntPendingFlag)) { } +#endif /* Clear the IICIF flag. */ base->S = kI2C_IntPendingFlag; /* Read from the data register. */ *rxBuff++ = base->D; } + + return result; } +/*! + * brief Initializes the I2C handle which is used in transactional functions. + * + * param base I2C base pointer. + * param handle pointer to i2c_slave_handle_t structure to store the transfer state. + * param callback pointer to user callback function. + * param userData user parameter passed to the callback function. + */ void I2C_SlaveTransferCreateHandle(I2C_Type *base, i2c_slave_handle_t *handle, i2c_slave_transfer_callback_t callback, @@ -1415,6 +1925,30 @@ void I2C_SlaveTransferCreateHandle(I2C_Type *base, EnableIRQ(s_i2cIrqs[instance]); } +/*! + * brief Starts accepting slave transfers. + * + * Call this API after calling the I2C_SlaveInit() and I2C_SlaveTransferCreateHandle() to start processing + * transactions driven by an I2C master. The slave monitors the I2C bus and passes events to the + * callback that was passed into the call to I2C_SlaveTransferCreateHandle(). The callback is always invoked + * from the interrupt context. + * + * The set of events received by the callback is customizable. To do so, set the a eventMask parameter to + * the OR'd combination of #i2c_slave_transfer_event_t enumerators for the events you wish to receive. + * The #kI2C_SlaveTransmitEvent and #kLPI2C_SlaveReceiveEvent events are always enabled and do not need + * to be included in the mask. Alternatively, pass 0 to get a default set of only the transmit and + * receive events that are always enabled. In addition, the #kI2C_SlaveAllEvents constant is provided as + * a convenient way to enable all events. + * + * param base The I2C peripheral base address. + * param handle Pointer to #i2c_slave_handle_t structure which stores the transfer state. + * param eventMask Bit mask formed by OR'ing together #i2c_slave_transfer_event_t enumerators to specify + * which events to send to the callback. Other accepted values are 0 to get a default set of + * only the transmit and receive events, and #kI2C_SlaveAllEvents to enable all events. + * + * retval #kStatus_Success Slave transfers were successfully started. + * retval #kStatus_I2C_Busy Slave transfers have already been started on this handle. + */ status_t I2C_SlaveTransferNonBlocking(I2C_Type *base, i2c_slave_handle_t *handle, uint32_t eventMask) { assert(handle); @@ -1448,6 +1982,14 @@ status_t I2C_SlaveTransferNonBlocking(I2C_Type *base, i2c_slave_handle_t *handle return kStatus_Success; } +/*! + * brief Aborts the slave transfer. + * + * note This API can be called at any time to stop slave for handling the bus events. + * + * param base I2C base pointer. + * param handle pointer to i2c_slave_handle_t structure which stores the transfer state. + */ void I2C_SlaveTransferAbort(I2C_Type *base, i2c_slave_handle_t *handle) { assert(handle); @@ -1465,6 +2007,15 @@ void I2C_SlaveTransferAbort(I2C_Type *base, i2c_slave_handle_t *handle) } } +/*! + * brief Gets the slave transfer remaining bytes during a interrupt non-blocking transfer. + * + * param base I2C base pointer. + * param handle pointer to i2c_slave_handle_t structure. + * param count Number of bytes transferred so far by the non-blocking transaction. + * retval kStatus_InvalidArgument count is Invalid. + * retval kStatus_Success Successfully return the count. + */ status_t I2C_SlaveTransferGetCount(I2C_Type *base, i2c_slave_handle_t *handle, size_t *count) { assert(handle); @@ -1487,6 +2038,12 @@ status_t I2C_SlaveTransferGetCount(I2C_Type *base, i2c_slave_handle_t *handle, s return kStatus_Success; } +/*! + * brief Slave interrupt handler. + * + * param base I2C base pointer. + * param i2cHandle pointer to i2c_slave_handle_t structure which stores the transfer state + */ void I2C_SlaveTransferHandleIRQ(I2C_Type *base, void *i2cHandle) { assert(i2cHandle); diff --git a/ext/hal/nxp/mcux/drivers/kinetis/fsl_i2c.h b/ext/hal/nxp/mcux/drivers/kinetis/fsl_i2c.h index d55fd1d8ea3..d377a668c7d 100644 --- a/ext/hal/nxp/mcux/drivers/kinetis/fsl_i2c.h +++ b/ext/hal/nxp/mcux/drivers/kinetis/fsl_i2c.h @@ -1,31 +1,9 @@ /* * Copyright (c) 2015, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP + * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * SPDX-License-Identifier: BSD-3-Clause */ #ifndef _FSL_I2C_H_ #define _FSL_I2C_H_ @@ -43,10 +21,15 @@ /*! @name Driver version */ /*@{*/ -/*! @brief I2C driver version 2.0.3. */ -#define FSL_I2C_DRIVER_VERSION (MAKE_VERSION(2, 0, 3)) +/*! @brief I2C driver version 2.0.6. */ +#define FSL_I2C_DRIVER_VERSION (MAKE_VERSION(2, 0, 6)) /*@}*/ +/*! @brief Timeout times for waiting flag. */ +#ifndef I2C_WAIT_TIMEOUT +#define I2C_WAIT_TIMEOUT 0U /* Define to zero means keep waiting until the flag is assert/deassert. */ +#endif + #if (defined(FSL_FEATURE_I2C_HAS_START_STOP_DETECT) && FSL_FEATURE_I2C_HAS_START_STOP_DETECT || \ defined(FSL_FEATURE_I2C_HAS_STOP_DETECT) && FSL_FEATURE_I2C_HAS_STOP_DETECT) #define I2C_HAS_STOP_DETECT @@ -59,7 +42,7 @@ enum _i2c_status kStatus_I2C_Idle = MAKE_STATUS(kStatusGroup_I2C, 1), /*!< Bus is Idle. */ kStatus_I2C_Nak = MAKE_STATUS(kStatusGroup_I2C, 2), /*!< NAK received during transfer. */ kStatus_I2C_ArbitrationLost = MAKE_STATUS(kStatusGroup_I2C, 3), /*!< Arbitration lost during transfer. */ - kStatus_I2C_Timeout = MAKE_STATUS(kStatusGroup_I2C, 4), /*!< Wait event timeout. */ + kStatus_I2C_Timeout = MAKE_STATUS(kStatusGroup_I2C, 4), /*!< Timeout poling status flags. */ kStatus_I2C_Addr_Nak = MAKE_STATUS(kStatusGroup_I2C, 5), /*!< NAK received during the address probe. */ }; @@ -126,7 +109,8 @@ typedef enum _i2c_slave_address_mode enum _i2c_master_transfer_flags { kI2C_TransferDefaultFlag = 0x0U, /*!< A transfer starts with a start signal, stops with a stop signal. */ - kI2C_TransferNoStartFlag = 0x1U, /*!< A transfer starts without a start signal. */ + kI2C_TransferNoStartFlag = 0x1U, /*!< A transfer starts without a start signal, only support write only or + write+read with no start flag, do not support read only with no start flag. */ kI2C_TransferRepeatedStartFlag = 0x2U, /*!< A transfer starts with a repeated start signal. */ kI2C_TransferNoStopFlag = 0x4U, /*!< A transfer ends without a stop signal. */ }; @@ -257,6 +241,12 @@ struct _i2c_slave_handle void *userData; /*!< A callback parameter passed to the callback. */ }; +/******************************************************************************* + * Variables + ******************************************************************************/ +/*! @brief Pointers to i2c bases for each instance. */ +extern I2C_Type *const s_i2cBases[]; + /******************************************************************************* * API ******************************************************************************/ @@ -340,6 +330,13 @@ void I2C_MasterDeinit(I2C_Type *base); */ void I2C_SlaveDeinit(I2C_Type *base); +/*! + * @brief Get instance number for I2C module. + * + * @param base I2C peripheral base address. + */ +uint32_t I2C_GetInstance(I2C_Type *base); + /*! * @brief Sets the I2C master configuration structure to default values. * @@ -631,8 +628,10 @@ status_t I2C_SlaveWriteBlocking(I2C_Type *base, const uint8_t *txBuff, size_t tx * @param base I2C peripheral base pointer. * @param rxBuff The pointer to the data to store the received data. * @param rxSize The length in bytes of the data to be received. + * @retval kStatus_Success Successfully complete data receive. + * @retval kStatus_I2C_Timeout Wait status flag timeout. */ -void I2C_SlaveReadBlocking(I2C_Type *base, uint8_t *rxBuff, size_t rxSize); +status_t I2C_SlaveReadBlocking(I2C_Type *base, uint8_t *rxBuff, size_t rxSize); /*! * @brief Performs a master polling transfer on the I2C bus. @@ -706,8 +705,10 @@ status_t I2C_MasterTransferGetCount(I2C_Type *base, i2c_master_handle_t *handle, * * @param base I2C base pointer. * @param handle pointer to i2c_master_handle_t structure which stores the transfer state + * @retval kStatus_I2C_Timeout Timeout during polling flag. + * @retval kStatus_Success Successfully abort the transfer. */ -void I2C_MasterTransferAbort(I2C_Type *base, i2c_master_handle_t *handle); +status_t I2C_MasterTransferAbort(I2C_Type *base, i2c_master_handle_t *handle); /*! * @brief Master interrupt handler. diff --git a/ext/hal/nxp/mcux/drivers/kinetis/fsl_i2c_edma.c b/ext/hal/nxp/mcux/drivers/kinetis/fsl_i2c_edma.c index 28a415e075a..eb96d2e402a 100644 --- a/ext/hal/nxp/mcux/drivers/kinetis/fsl_i2c_edma.c +++ b/ext/hal/nxp/mcux/drivers/kinetis/fsl_i2c_edma.c @@ -1,31 +1,9 @@ /* * Copyright (c) 2015, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP + * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * SPDX-License-Identifier: BSD-3-Clause */ #include "fsl_i2c_edma.h" @@ -34,6 +12,11 @@ * Definitions ******************************************************************************/ +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.i2c_edma" +#endif + /*transfer.subaddressSize > 0) && (result == kStatus_Success)); + } while (handle->transfer.subaddressSize > 0); if (handle->transfer.direction == kI2C_Read) { @@ -355,7 +330,7 @@ static status_t I2C_InitTransferStateMachineEDMA(I2C_Type *base, static void I2C_MasterTransferEDMAConfig(I2C_Type *base, i2c_master_edma_handle_t *handle) { - edma_transfer_config_t transfer_config; + edma_transfer_config_t transfer_config = {0}; if (handle->transfer.direction == kI2C_Read) { @@ -387,6 +362,15 @@ static void I2C_MasterTransferEDMAConfig(I2C_Type *base, i2c_master_edma_handle_ EDMA_StartTransfer(handle->dmaHandle); } +/*! + * brief Initializes the I2C handle which is used in transcational functions. + * + * param base I2C peripheral base address. + * param handle A pointer to the i2c_master_edma_handle_t structure. + * param callback A pointer to the user callback function. + * param userData A user parameter passed to the callback function. + * param edmaHandle eDMA handle pointer. + */ void I2C_MasterCreateEDMAHandle(I2C_Type *base, i2c_master_edma_handle_t *handle, i2c_master_edma_transfer_callback_t callback, @@ -417,6 +401,18 @@ void I2C_MasterCreateEDMAHandle(I2C_Type *base, EDMA_SetCallback(edmaHandle, (edma_callback)I2C_MasterTransferCallbackEDMA, &s_edmaPrivateHandle[instance]); } +/*! + * brief Performs a master eDMA non-blocking transfer on the I2C bus. + * + * param base I2C peripheral base address. + * param handle A pointer to the i2c_master_edma_handle_t structure. + * param xfer A pointer to the transfer structure of i2c_master_transfer_t. + * retval kStatus_Success Sucessfully completed the data transmission. + * retval kStatus_I2C_Busy A previous transmission is still not finished. + * retval kStatus_I2C_Timeout Transfer error, waits for a signal timeout. + * retval kStatus_I2C_ArbitrationLost Transfer error, arbitration lost. + * retval kStataus_I2C_Nak Transfer error, receive NAK during transfer. + */ status_t I2C_MasterTransferEDMA(I2C_Type *base, i2c_master_edma_handle_t *handle, i2c_master_transfer_t *xfer) { assert(handle); @@ -533,6 +529,13 @@ status_t I2C_MasterTransferEDMA(I2C_Type *base, i2c_master_edma_handle_t *handle return result; } +/*! + * brief Gets a master transfer status during the eDMA non-blocking transfer. + * + * param base I2C peripheral base address. + * param handle A pointer to the i2c_master_edma_handle_t structure. + * param count A number of bytes transferred by the non-blocking transaction. + */ status_t I2C_MasterTransferGetCountEDMA(I2C_Type *base, i2c_master_edma_handle_t *handle, size_t *count) { assert(handle->dmaHandle); @@ -556,6 +559,12 @@ status_t I2C_MasterTransferGetCountEDMA(I2C_Type *base, i2c_master_edma_handle_t return kStatus_Success; } +/*! + * brief Aborts a master eDMA non-blocking transfer early. + * + * param base I2C peripheral base address. + * param handle A pointer to the i2c_master_edma_handle_t structure. + */ void I2C_MasterTransferAbortEDMA(I2C_Type *base, i2c_master_edma_handle_t *handle) { EDMA_AbortTransfer(handle->dmaHandle); diff --git a/ext/hal/nxp/mcux/drivers/kinetis/fsl_i2c_edma.h b/ext/hal/nxp/mcux/drivers/kinetis/fsl_i2c_edma.h index 40cb648ea99..ccdedef63a8 100644 --- a/ext/hal/nxp/mcux/drivers/kinetis/fsl_i2c_edma.h +++ b/ext/hal/nxp/mcux/drivers/kinetis/fsl_i2c_edma.h @@ -1,37 +1,14 @@ /* * Copyright (c) 2015, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause */ #ifndef _FSL_I2C_DMA_H_ #define _FSL_I2C_DMA_H_ #include "fsl_i2c.h" -#include "fsl_dmamux.h" #include "fsl_edma.h" /*! @@ -43,6 +20,12 @@ * Definitions ******************************************************************************/ +/*! @name Driver version */ +/*@{*/ +/*! @brief I2C EDMA driver version 2.0.5. */ +#define FSL_I2C_EDMA_DRIVER_VERSION (MAKE_VERSION(2, 0, 5)) +/*@}*/ + /*! @brief I2C master eDMA handle typedef. */ typedef struct _i2c_master_edma_handle i2c_master_edma_handle_t; diff --git a/ext/hal/nxp/mcux/drivers/kinetis/fsl_llwu.c b/ext/hal/nxp/mcux/drivers/kinetis/fsl_llwu.c index 74b1001a88a..7e163a671db 100644 --- a/ext/hal/nxp/mcux/drivers/kinetis/fsl_llwu.c +++ b/ext/hal/nxp/mcux/drivers/kinetis/fsl_llwu.c @@ -1,36 +1,29 @@ /* * Copyright (c) 2015, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP + * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * SPDX-License-Identifier: BSD-3-Clause */ #include "fsl_llwu.h" +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.llwu" +#endif + #if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) +/*! + * brief Sets the external input pin source mode. + * + * This function sets the external input pin source mode that is used + * as a wake up source. + * + * param base LLWU peripheral base address. + * param pinIndex A pin index to be enabled as an external wakeup source starting from 1. + * param pinMode A pin configuration mode defined in the llwu_external_pin_modes_t. + */ void LLWU_SetExternalWakeupPinMode(LLWU_Type *base, uint32_t pinIndex, llwu_external_pin_mode_t pinMode) { #if (defined(FSL_FEATURE_LLWU_REG_BITWIDTH) && (FSL_FEATURE_LLWU_REG_BITWIDTH == 32)) @@ -114,6 +107,16 @@ void LLWU_SetExternalWakeupPinMode(LLWU_Type *base, uint32_t pinIndex, llwu_exte } } +/*! + * brief Gets the external wakeup source flag. + * + * This function checks the external pin flag to detect whether the MCU is + * woken up by the specific pin. + * + * param base LLWU peripheral base address. + * param pinIndex A pin index, which starts from 1. + * return True if the specific pin is a wakeup source. + */ bool LLWU_GetExternalWakeupPinFlag(LLWU_Type *base, uint32_t pinIndex) { #if (defined(FSL_FEATURE_LLWU_REG_BITWIDTH) && (FSL_FEATURE_LLWU_REG_BITWIDTH == 32)) @@ -178,6 +181,14 @@ bool LLWU_GetExternalWakeupPinFlag(LLWU_Type *base, uint32_t pinIndex) #endif /* FSL_FEATURE_LLWU_REG_BITWIDTH */ } +/*! + * brief Clears the external wakeup source flag. + * + * This function clears the external wakeup source flag for a specific pin. + * + * param base LLWU peripheral base address. + * param pinIndex A pin index, which starts from 1. + */ void LLWU_ClearExternalWakeupPinFlag(LLWU_Type *base, uint32_t pinIndex) { #if (defined(FSL_FEATURE_LLWU_REG_BITWIDTH) && (FSL_FEATURE_LLWU_REG_BITWIDTH == 32)) @@ -238,39 +249,43 @@ void LLWU_ClearExternalWakeupPinFlag(LLWU_Type *base, uint32_t pinIndex) #endif /* FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN */ #if (defined(FSL_FEATURE_LLWU_HAS_PIN_FILTER) && FSL_FEATURE_LLWU_HAS_PIN_FILTER) +/*! + * brief Sets the pin filter configuration. + * + * This function sets the pin filter configuration. + * + * param base LLWU peripheral base address. + * param filterIndex A pin filter index used to enable/disable the digital filter, starting from 1. + * param filterMode A filter mode configuration + */ void LLWU_SetPinFilterMode(LLWU_Type *base, uint32_t filterIndex, llwu_external_pin_filter_mode_t filterMode) { #if (defined(FSL_FEATURE_LLWU_REG_BITWIDTH) && (FSL_FEATURE_LLWU_REG_BITWIDTH == 32)) - uint32_t reg; - - reg = base->FILT; - reg &= ~((LLWU_FILT_FILTSEL1_MASK | LLWU_FILT_FILTE1_MASK) << (filterIndex * 8U - 1U)); - reg |= (((filterMode.pinIndex << LLWU_FILT_FILTSEL1_SHIFT) | (filterMode.filterMode << LLWU_FILT_FILTE1_SHIFT) - /* Clear the Filter Detect Flag */ - | LLWU_FILT_FILTF1_MASK) - << (filterIndex * 8U - 1U)); - base->FILT = reg; + base->FILT = ((base->FILT) & ~((LLWU_FILT_FILTSEL1_MASK | LLWU_FILT_FILTE1_MASK) << ((filterIndex - 1U) * 8U))) | + ((LLWU_FILT_FILTSEL1(filterMode.pinIndex) | LLWU_FILT_FILTE1(filterMode.filterMode)) + << ((filterIndex - 1U) * 8U)) | + LLWU_FILT_FILTF1_MASK /* W1C to clear the FILTF flag bit. */ + ; #else volatile uint8_t *regBase; - uint8_t reg; switch (filterIndex) { - case 1: + case 1U: regBase = &base->FILT1; break; #if (defined(FSL_FEATURE_LLWU_HAS_PIN_FILTER) && (FSL_FEATURE_LLWU_HAS_PIN_FILTER > 1)) - case 2: + case 2U: regBase = &base->FILT2; break; #endif /* FSL_FEATURE_LLWU_HAS_PIN_FILTER */ #if (defined(FSL_FEATURE_LLWU_HAS_PIN_FILTER) && (FSL_FEATURE_LLWU_HAS_PIN_FILTER > 2)) - case 3: + case 3U: regBase = &base->FILT3; break; #endif /* FSL_FEATURE_LLWU_HAS_PIN_FILTER */ #if (defined(FSL_FEATURE_LLWU_HAS_PIN_FILTER) && (FSL_FEATURE_LLWU_HAS_PIN_FILTER > 3)) - case 4: + case 4U: regBase = &base->FILT4; break; #endif /* FSL_FEATURE_LLWU_HAS_PIN_FILTER */ @@ -279,19 +294,25 @@ void LLWU_SetPinFilterMode(LLWU_Type *base, uint32_t filterIndex, llwu_external_ break; } - if (regBase) + if (NULL != regBase) { - reg = *regBase; - reg &= ~(LLWU_FILT1_FILTSEL_MASK | LLWU_FILT1_FILTE_MASK); - reg |= ((uint32_t)filterMode.pinIndex << LLWU_FILT1_FILTSEL_SHIFT); - reg |= ((uint32_t)filterMode.filterMode << LLWU_FILT1_FILTE_SHIFT); - /* Clear the Filter Detect Flag */ - reg |= LLWU_FILT1_FILTF_MASK; - *regBase = reg; + *regBase = (*regBase & ~(LLWU_FILT1_FILTSEL_MASK | LLWU_FILT1_FILTE_MASK)) | + LLWU_FILT1_FILTSEL(filterMode.pinIndex) | LLWU_FILT1_FILTE(filterMode.filterMode) | + LLWU_FILT1_FILTF_MASK /* W1C to clear the FILTF flag bit. */ + ; } #endif /* FSL_FEATURE_LLWU_REG_BITWIDTH */ } +/*! + * brief Gets the pin filter configuration. + * + * This function gets the pin filter flag. + * + * param base LLWU peripheral base address. + * param filterIndex A pin filter index, which starts from 1. + * return True if the flag is a source of the existing low-leakage power mode. + */ bool LLWU_GetPinFilterFlag(LLWU_Type *base, uint32_t filterIndex) { #if (defined(FSL_FEATURE_LLWU_REG_BITWIDTH) && (FSL_FEATURE_LLWU_REG_BITWIDTH == 32)) @@ -327,6 +348,14 @@ bool LLWU_GetPinFilterFlag(LLWU_Type *base, uint32_t filterIndex) #endif /* FSL_FEATURE_LLWU_REG_BITWIDTH */ } +/*! + * brief Clears the pin filter configuration. + * + * This function clears the pin filter flag. + * + * param base LLWU peripheral base address. + * param filterIndex A pin filter index to clear the flag, starting from 1. + */ void LLWU_ClearPinFilterFlag(LLWU_Type *base, uint32_t filterIndex) { #if (defined(FSL_FEATURE_LLWU_REG_BITWIDTH) && (FSL_FEATURE_LLWU_REG_BITWIDTH == 32)) @@ -338,15 +367,21 @@ void LLWU_ClearPinFilterFlag(LLWU_Type *base, uint32_t filterIndex) case 1: reg |= LLWU_FILT_FILTF1_MASK; break; +#if (defined(FSL_FEATURE_LLWU_HAS_PIN_FILTER) && (FSL_FEATURE_LLWU_HAS_PIN_FILTER > 1)) case 2: reg |= LLWU_FILT_FILTF2_MASK; break; +#endif /* FSL_FEATURE_LLWU_HAS_PIN_FILTER > 1 */ +#if (defined(FSL_FEATURE_LLWU_HAS_PIN_FILTER) && (FSL_FEATURE_LLWU_HAS_PIN_FILTER > 2)) case 3: reg |= LLWU_FILT_FILTF3_MASK; break; +#endif /* FSL_FEATURE_LLWU_HAS_PIN_FILTER > 2 */ +#if (defined(FSL_FEATURE_LLWU_HAS_PIN_FILTER) && (FSL_FEATURE_LLWU_HAS_PIN_FILTER > 3)) case 4: reg |= LLWU_FILT_FILTF4_MASK; break; +#endif /* FSL_FEATURE_LLWU_HAS_PIN_FILTER > 3 */ default: break; } @@ -391,14 +426,21 @@ void LLWU_ClearPinFilterFlag(LLWU_Type *base, uint32_t filterIndex) #endif /* FSL_FEATURE_LLWU_HAS_PIN_FILTER */ #if (defined(FSL_FEATURE_LLWU_HAS_RESET_ENABLE) && FSL_FEATURE_LLWU_HAS_RESET_ENABLE) -void LLWU_SetResetPinMode(LLWU_Type *base, bool pinEnable, bool enableInLowLeakageMode) +/*! + * brief Sets the reset pin mode. + * + * This function determines how the reset pin is used as a low leakage mode exit source. + * + * param pinEnable Enable reset the pin filter + * param pinFilterEnable Specify whether the pin filter is enabled in Low-Leakage power mode. + */ +void LLWU_SetResetPinMode(LLWU_Type *base, bool pinEnable, bool pinFilterEnable) { uint8_t reg; reg = base->RST; reg &= ~(LLWU_RST_LLRSTE_MASK | LLWU_RST_RSTFILT_MASK); - reg |= - (((uint32_t)pinEnable << LLWU_RST_LLRSTE_SHIFT) | ((uint32_t)enableInLowLeakageMode << LLWU_RST_RSTFILT_SHIFT)); + reg |= (((uint32_t)pinEnable << LLWU_RST_LLRSTE_SHIFT) | ((uint32_t)pinFilterEnable << LLWU_RST_RSTFILT_SHIFT)); base->RST = reg; } #endif /* FSL_FEATURE_LLWU_HAS_RESET_ENABLE */ diff --git a/ext/hal/nxp/mcux/drivers/kinetis/fsl_llwu.h b/ext/hal/nxp/mcux/drivers/kinetis/fsl_llwu.h index d5a0037bb58..8f23bebb0d6 100644 --- a/ext/hal/nxp/mcux/drivers/kinetis/fsl_llwu.h +++ b/ext/hal/nxp/mcux/drivers/kinetis/fsl_llwu.h @@ -1,31 +1,9 @@ /* * Copyright (c) 2015, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause */ #ifndef _FSL_LLWU_H_ #define _FSL_LLWU_H_ @@ -35,15 +13,14 @@ /*! @addtogroup llwu */ /*! @{ */ - /******************************************************************************* * Definitions ******************************************************************************/ /*! @name Driver version */ /*@{*/ -/*! @brief LLWU driver version 2.0.1. */ -#define FSL_LLWU_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) +/*! @brief LLWU driver version 2.0.2. */ +#define FSL_LLWU_DRIVER_VERSION (MAKE_VERSION(2, 0, 2)) /*@}*/ /*! @@ -208,6 +185,27 @@ static inline void LLWU_EnableInternalModuleInterruptWakup(LLWU_Type *base, uint } } +#if (!(defined(FSL_FEATURE_LLWU_HAS_NO_INTERNAL_MODULE_WAKEUP_FLAG_REG) && \ + FSL_FEATURE_LLWU_HAS_NO_INTERNAL_MODULE_WAKEUP_FLAG_REG)) +/* Re-define the register which includes the internal wakeup module flag. */ +#if (defined(FSL_FEATURE_LLWU_REG_BITWIDTH) && (FSL_FEATURE_LLWU_REG_BITWIDTH == 32)) /* 32-bit LLWU. */ +#if (defined(FSL_FEATURE_LLWU_HAS_MF) && FSL_FEATURE_LLWU_HAS_MF) +#define INTERNAL_WAKEUP_MODULE_FLAG_REG MF +#else +#error "Unsupported internal module flag register." +#endif +#else /* 8-bit LLUW. */ +#if (defined(FSL_FEATURE_LLWU_HAS_MF) && FSL_FEATURE_LLWU_HAS_MF) +#define INTERNAL_WAKEUP_MODULE_FLAG_REG MF5 +#elif(defined(FSL_FEATURE_LLWU_HAS_PF) && FSL_FEATURE_LLWU_HAS_PF) +#define INTERNAL_WAKEUP_MODULE_FLAG_REG PF3 +#elif(!(defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN > 16))) +#define INTERNAL_WAKEUP_MODULE_FLAG_REG F3 +#else +#error "Unsupported internal module flag register." +#endif +#endif /* FSL_FEATURE_LLWU_REG_BITWIDTH */ + /*! * @brief Gets the external wakeup source flag. * @@ -220,24 +218,9 @@ static inline void LLWU_EnableInternalModuleInterruptWakup(LLWU_Type *base, uint */ static inline bool LLWU_GetInternalWakeupModuleFlag(LLWU_Type *base, uint32_t moduleIndex) { -#if (defined(FSL_FEATURE_LLWU_HAS_MF) && FSL_FEATURE_LLWU_HAS_MF) -#if (defined(FSL_FEATURE_LLWU_REG_BITWIDTH) && (FSL_FEATURE_LLWU_REG_BITWIDTH == 32)) - return (bool)(base->MF & (1U << moduleIndex)); -#else - return (bool)(base->MF5 & (1U << moduleIndex)); -#endif /* FSL_FEATURE_LLWU_REG_BITWIDTH */ -#else -#if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN > 16)) - return (bool)(base->F5 & (1U << moduleIndex)); -#else -#if (defined(FSL_FEATURE_LLWU_HAS_PF) && FSL_FEATURE_LLWU_HAS_PF) - return (bool)(base->PF3 & (1U << moduleIndex)); -#else - return (bool)(base->F3 & (1U << moduleIndex)); -#endif /* FSL_FEATURE_LLWU_HAS_PF */ -#endif /* FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN */ -#endif /* FSL_FEATURE_LLWU_HAS_MF */ + return ((1U << moduleIndex) == (base->INTERNAL_WAKEUP_MODULE_FLAG_REG & (1U << moduleIndex))); } +#endif /* FSL_FEATURE_LLWU_HAS_NO_INTERNAL_MODULE_WAKEUP_FLAG_REG */ #endif /* FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE */ #if (defined(FSL_FEATURE_LLWU_HAS_DMA_ENABLE_REG) && FSL_FEATURE_LLWU_HAS_DMA_ENABLE_REG) @@ -307,7 +290,7 @@ void LLWU_ClearPinFilterFlag(LLWU_Type *base, uint32_t filterIndex); * @param pinEnable Enable reset the pin filter * @param pinFilterEnable Specify whether the pin filter is enabled in Low-Leakage power mode. */ -void LLWU_SetResetPinMode(LLWU_Type *base, bool pinEnable, bool enableInLowLeakageMode); +void LLWU_SetResetPinMode(LLWU_Type *base, bool pinEnable, bool pinFilterEnable); #endif /* FSL_FEATURE_LLWU_HAS_RESET_ENABLE */ /*@}*/ diff --git a/ext/hal/nxp/mcux/drivers/kinetis/fsl_lptmr.c b/ext/hal/nxp/mcux/drivers/kinetis/fsl_lptmr.c index 67b3b9785cf..4112f234219 100644 --- a/ext/hal/nxp/mcux/drivers/kinetis/fsl_lptmr.c +++ b/ext/hal/nxp/mcux/drivers/kinetis/fsl_lptmr.c @@ -1,38 +1,22 @@ /* * Copyright (c) 2015, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP + * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * SPDX-License-Identifier: BSD-3-Clause */ #include "fsl_lptmr.h" +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.lptmr" +#endif + /******************************************************************************* * Prototypes ******************************************************************************/ +#if defined(LPTMR_CLOCKS) /*! * @brief Gets the instance from the base address to be used to gate or ungate the module clock * @@ -41,10 +25,12 @@ * @return The LPTMR instance */ static uint32_t LPTMR_GetInstance(LPTMR_Type *base); +#endif /* LPTMR_CLOCKS */ /******************************************************************************* * Variables ******************************************************************************/ +#if defined(LPTMR_CLOCKS) /*! @brief Pointers to LPTMR bases for each instance. */ static LPTMR_Type *const s_lptmrBases[] = LPTMR_BASE_PTRS; @@ -58,10 +44,12 @@ static const clock_ip_name_t s_lptmrPeriphClocks[] = LPTMR_PERIPH_CLOCKS; #endif #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +#endif /* LPTMR_CLOCKS */ /******************************************************************************* * Code ******************************************************************************/ +#if defined(LPTMR_CLOCKS) static uint32_t LPTMR_GetInstance(LPTMR_Type *base) { uint32_t instance; @@ -79,13 +67,23 @@ static uint32_t LPTMR_GetInstance(LPTMR_Type *base) return instance; } +#endif /* LPTMR_CLOCKS */ +/*! + * brief Ungates the LPTMR clock and configures the peripheral for a basic operation. + * + * note This API should be called at the beginning of the application using the LPTMR driver. + * + * param base LPTMR peripheral base address + * param config A pointer to the LPTMR configuration structure. + */ void LPTMR_Init(LPTMR_Type *base, const lptmr_config_t *config) { assert(config); +#if defined(LPTMR_CLOCKS) #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - + uint32_t instance = LPTMR_GetInstance(base); /* Ungate the LPTMR clock*/ @@ -95,6 +93,7 @@ void LPTMR_Init(LPTMR_Type *base, const lptmr_config_t *config) #endif #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +#endif /* LPTMR_CLOCKS */ /* Configure the timers operation mode and input pin setup */ base->CSR = (LPTMR_CSR_TMS(config->timerMode) | LPTMR_CSR_TFC(config->enableFreeRunning) | @@ -105,10 +104,17 @@ void LPTMR_Init(LPTMR_Type *base, const lptmr_config_t *config) LPTMR_PSR_PCS(config->prescalerClockSource)); } +/*! + * brief Gates the LPTMR clock. + * + * param base LPTMR peripheral base address + */ void LPTMR_Deinit(LPTMR_Type *base) { /* Disable the LPTMR and reset the internal logic */ base->CSR &= ~LPTMR_CSR_TEN_MASK; + +#if defined(LPTMR_CLOCKS) #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) uint32_t instance = LPTMR_GetInstance(base); @@ -120,12 +126,31 @@ void LPTMR_Deinit(LPTMR_Type *base) #endif #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +#endif /* LPTMR_CLOCKS */ } +/*! + * brief Fills in the LPTMR configuration structure with default settings. + * + * The default values are as follows. + * code + * config->timerMode = kLPTMR_TimerModeTimeCounter; + * config->pinSelect = kLPTMR_PinSelectInput_0; + * config->pinPolarity = kLPTMR_PinPolarityActiveHigh; + * config->enableFreeRunning = false; + * config->bypassPrescaler = true; + * config->prescalerClockSource = kLPTMR_PrescalerClock_1; + * config->value = kLPTMR_Prescale_Glitch_0; + * endcode + * param config A pointer to the LPTMR configuration structure. + */ void LPTMR_GetDefaultConfig(lptmr_config_t *config) { assert(config); + /* Initializes the configure structure to zero. */ + memset(config, 0, sizeof(*config)); + /* Use time counter mode */ config->timerMode = kLPTMR_TimerModeTimeCounter; /* Use input 0 as source in pulse counter mode */ diff --git a/ext/hal/nxp/mcux/drivers/kinetis/fsl_lptmr.h b/ext/hal/nxp/mcux/drivers/kinetis/fsl_lptmr.h index 6cc909b3148..bad57e88a6a 100644 --- a/ext/hal/nxp/mcux/drivers/kinetis/fsl_lptmr.h +++ b/ext/hal/nxp/mcux/drivers/kinetis/fsl_lptmr.h @@ -1,31 +1,9 @@ /* * Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause */ #ifndef _FSL_LPTMR_H_ #define _FSL_LPTMR_H_ @@ -238,6 +216,26 @@ static inline uint32_t LPTMR_GetEnabledInterrupts(LPTMR_Type *base) /*! @}*/ +#if defined(FSL_FEATURE_LPTMR_HAS_CSR_TDRE) && (FSL_FEATURE_LPTMR_HAS_CSR_TDRE) +/*! + * @brief Enable or disable timer DMA request + * + * @param base base LPTMR peripheral base address + * @param enable Switcher of timer DMA feature. "true" means to enable, "false" means to disable. + */ +static inline void LPTMR_EnableTimerDMA(LPTMR_Type *base, bool enable) +{ + if(enable) + { + base->CSR |= LPTMR_CSR_TDRE_MASK; + } + else + { + base->CSR &= ~(LPTMR_CSR_TDRE_MASK); + } +} +#endif /* FSL_FEATURE_LPTMR_HAS_CSR_TDRE */ + /*! * @name Status Interface * @{ diff --git a/ext/hal/nxp/mcux/drivers/kinetis/fsl_pdb.c b/ext/hal/nxp/mcux/drivers/kinetis/fsl_pdb.c index 1fc4a9a486a..4044a7a7d74 100644 --- a/ext/hal/nxp/mcux/drivers/kinetis/fsl_pdb.c +++ b/ext/hal/nxp/mcux/drivers/kinetis/fsl_pdb.c @@ -1,35 +1,18 @@ /* * Copyright (c) 2015, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP + * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * SPDX-License-Identifier: BSD-3-Clause */ #include "fsl_pdb.h" +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.pdb" +#endif + /******************************************************************************* * Prototypes ******************************************************************************/ @@ -71,6 +54,17 @@ static uint32_t PDB_GetInstance(PDB_Type *base) return instance; } +/*! + * brief Initializes the PDB module. + * + * This function initializes the PDB module. The operations included are as follows. + * - Enable the clock for PDB instance. + * - Configure the PDB module. + * - Enable the PDB module. + * + * param base PDB peripheral base address. + * param config Pointer to the configuration structure. See "pdb_config_t". + */ void PDB_Init(PDB_Type *base, const pdb_config_t *config) { assert(NULL != config); @@ -98,6 +92,11 @@ void PDB_Init(PDB_Type *base, const pdb_config_t *config) PDB_Enable(base, true); /* Enable the PDB module. */ } +/*! + * brief De-initializes the PDB module. + * + * param base PDB peripheral base address. + */ void PDB_Deinit(PDB_Type *base) { PDB_Enable(base, false); /* Disable the PDB module. */ @@ -108,10 +107,26 @@ void PDB_Deinit(PDB_Type *base) #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ } +/*! + * brief Initializes the PDB user configuration structure. + * + * This function initializes the user configuration structure to a default value. The default values are as follows. + * code + * config->loadValueMode = kPDB_LoadValueImmediately; + * config->prescalerDivider = kPDB_PrescalerDivider1; + * config->dividerMultiplicationFactor = kPDB_DividerMultiplicationFactor1; + * config->triggerInputSource = kPDB_TriggerSoftware; + * config->enableContinuousMode = false; + * endcode + * param config Pointer to configuration structure. See "pdb_config_t". + */ void PDB_GetDefaultConfig(pdb_config_t *config) { assert(NULL != config); + /* Initializes the configure structure to zero. */ + memset(config, 0, sizeof(*config)); + config->loadValueMode = kPDB_LoadValueImmediately; config->prescalerDivider = kPDB_PrescalerDivider1; config->dividerMultiplicationFactor = kPDB_DividerMultiplicationFactor1; @@ -120,7 +135,14 @@ void PDB_GetDefaultConfig(pdb_config_t *config) } #if defined(FSL_FEATURE_PDB_HAS_DAC) && FSL_FEATURE_PDB_HAS_DAC -void PDB_SetDACTriggerConfig(PDB_Type *base, uint32_t channel, pdb_dac_trigger_config_t *config) +/*! + * brief Configures the DAC trigger in the PDB module. + * + * param base PDB peripheral base address. + * param channel Channel index for DAC instance. + * param config Pointer to the configuration structure. See "pdb_dac_trigger_config_t". + */ +void PDB_SetDACTriggerConfig(PDB_Type *base, pdb_dac_trigger_channel_t channel, pdb_dac_trigger_config_t *config) { assert(channel < PDB_INTC_COUNT); assert(NULL != config); diff --git a/ext/hal/nxp/mcux/drivers/kinetis/fsl_pdb.h b/ext/hal/nxp/mcux/drivers/kinetis/fsl_pdb.h index 3dec9463462..ea7ec269389 100644 --- a/ext/hal/nxp/mcux/drivers/kinetis/fsl_pdb.h +++ b/ext/hal/nxp/mcux/drivers/kinetis/fsl_pdb.h @@ -1,31 +1,9 @@ /* * Copyright (c) 2015, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause */ #ifndef _FSL_PDB_H_ @@ -179,6 +157,68 @@ typedef enum _pdb_trigger_input_source kPDB_TriggerSoftware = 15U, /*!< Trigger-In 15, software trigger. */ } pdb_trigger_input_source_t; +/*! + * @brief List of PDB ADC trigger channels + * @note Actual number of available channels is SoC dependent + */ +typedef enum _pdb_adc_trigger_channel +{ + kPDB_ADCTriggerChannel0 = 0U, /*!< PDB ADC trigger channel number 0 */ + kPDB_ADCTriggerChannel1 = 1U, /*!< PDB ADC trigger channel number 1 */ + kPDB_ADCTriggerChannel2 = 2U, /*!< PDB ADC trigger channel number 2 */ + kPDB_ADCTriggerChannel3 = 3U, /*!< PDB ADC trigger channel number 3 */ +} pdb_adc_trigger_channel_t; + +/*! + * @brief List of PDB ADC pretrigger + * @note Actual number of available pretrigger channels is SoC dependent + */ +typedef enum _pdb_adc_pretrigger +{ + kPDB_ADCPreTrigger0 = 0U, /*!< PDB ADC pretrigger number 0 */ + kPDB_ADCPreTrigger1 = 1U, /*!< PDB ADC pretrigger number 1 */ + kPDB_ADCPreTrigger2 = 2U, /*!< PDB ADC pretrigger number 2 */ + kPDB_ADCPreTrigger3 = 3U, /*!< PDB ADC pretrigger number 3 */ + kPDB_ADCPreTrigger4 = 4U, /*!< PDB ADC pretrigger number 4 */ + kPDB_ADCPreTrigger5 = 5U, /*!< PDB ADC pretrigger number 5 */ + kPDB_ADCPreTrigger6 = 6U, /*!< PDB ADC pretrigger number 6 */ + kPDB_ADCPreTrigger7 = 7U, /*!< PDB ADC pretrigger number 7 */ +} pdb_adc_pretrigger_t; + +/*! + * @brief List of PDB DAC trigger channels + * @note Actual number of available channels is SoC dependent + */ +typedef enum _pdb_dac_trigger_channel +{ + kPDB_DACTriggerChannel0 = 0U, /*!< PDB DAC trigger channel number 0 */ + kPDB_DACTriggerChannel1 = 1U, /*!< PDB DAC trigger channel number 1 */ +} pdb_dac_trigger_channel_t; + +/*! + * @brief List of PDB pulse out trigger channels + * @note Actual number of available channels is SoC dependent + */ +typedef enum _pdb_pulse_out_trigger_channel +{ + kPDB_PulseOutTriggerChannel0 = 0U, /*!< PDB pulse out trigger channel number 0 */ + kPDB_PulseOutTriggerChannel1 = 1U, /*!< PDB pulse out trigger channel number 1 */ + kPDB_PulseOutTriggerChannel2 = 2U, /*!< PDB pulse out trigger channel number 2 */ + kPDB_PulseOutTriggerChannel3 = 3U, /*!< PDB pulse out trigger channel number 3 */ +} pdb_pulse_out_trigger_channel_t; + +/*! + * @brief List of PDB pulse out trigger channels mask + * @note Actual number of available channels mask is SoC dependent + */ +typedef enum _pdb_pulse_out_channel_mask +{ + kPDB_PulseOutChannel0Mask = (1U << 0U), /*!< PDB pulse out trigger channel number 0 mask */ + kPDB_PulseOutChannel1Mask = (1U << 1U), /*!< PDB pulse out trigger channel number 1 mask */ + kPDB_PulseOutChannel2Mask = (1U << 2U), /*!< PDB pulse out trigger channel number 2 mask */ + kPDB_PulseOutChannel3Mask = (1U << 3U), /*!< PDB pulse out trigger channel number 3 mask */ +} pdb_pulse_out_channel_mask_t; + /*! * @brief PDB module configuration. */ @@ -427,7 +467,7 @@ static inline void PDB_SetCounterDelayValue(PDB_Type *base, uint32_t value) * @param channel Channel index for ADC instance. * @param config Pointer to the configuration structure. See "pdb_adc_pretrigger_config_t". */ -static inline void PDB_SetADCPreTriggerConfig(PDB_Type *base, uint32_t channel, pdb_adc_pretrigger_config_t *config) +static inline void PDB_SetADCPreTriggerConfig(PDB_Type *base, pdb_adc_trigger_channel_t channel, pdb_adc_pretrigger_config_t *config) { assert(channel < PDB_C1_COUNT); assert(NULL != config); @@ -442,18 +482,18 @@ static inline void PDB_SetADCPreTriggerConfig(PDB_Type *base, uint32_t channel, * This function sets the value for ADC pre-trigger delay event. It specifies the delay value for the channel's * corresponding pre-trigger. The pre-trigger asserts when the PDB counter is equal to the set value. * - * @param base PDB peripheral base address. - * @param channel Channel index for ADC instance. - * @param preChannel Channel group index for ADC instance. - * @param value Setting value for ADC pre-trigger delay event. 16-bit is available. + * @param base PDB peripheral base address. + * @param channel Channel index for ADC instance. + * @param pretriggerNumber Channel group index for ADC instance. + * @param value Setting value for ADC pre-trigger delay event. 16-bit is available. */ -static inline void PDB_SetADCPreTriggerDelayValue(PDB_Type *base, uint32_t channel, uint32_t preChannel, uint32_t value) +static inline void PDB_SetADCPreTriggerDelayValue(PDB_Type *base, pdb_adc_trigger_channel_t channel, pdb_adc_pretrigger_t pretriggerNumber, uint32_t value) { assert(channel < PDB_C1_COUNT); - assert(preChannel < PDB_DLY_COUNT2); + assert(pretriggerNumber < PDB_DLY_COUNT2); /* xx_COUNT2 is actually the count for pre-triggers in header file. xx_COUNT is used for the count of channels. */ - base->CH[channel].DLY[preChannel] = PDB_DLY_DLY(value); + base->CH[channel].DLY[pretriggerNumber] = PDB_DLY_DLY(value); } /*! @@ -464,7 +504,7 @@ static inline void PDB_SetADCPreTriggerDelayValue(PDB_Type *base, uint32_t chann * * @return Mask value for asserted flags. See "_pdb_adc_pretrigger_flags". */ -static inline uint32_t PDB_GetADCPreTriggerStatusFlags(PDB_Type *base, uint32_t channel) +static inline uint32_t PDB_GetADCPreTriggerStatusFlags(PDB_Type *base, pdb_adc_trigger_channel_t channel) { assert(channel < PDB_C1_COUNT); @@ -478,7 +518,7 @@ static inline uint32_t PDB_GetADCPreTriggerStatusFlags(PDB_Type *base, uint32_t * @param channel Channel index for ADC instance. * @param mask Mask value for flags. See "_pdb_adc_pretrigger_flags". */ -static inline void PDB_ClearADCPreTriggerStatusFlags(PDB_Type *base, uint32_t channel, uint32_t mask) +static inline void PDB_ClearADCPreTriggerStatusFlags(PDB_Type *base, pdb_adc_trigger_channel_t channel, uint32_t mask) { assert(channel < PDB_C1_COUNT); @@ -500,7 +540,7 @@ static inline void PDB_ClearADCPreTriggerStatusFlags(PDB_Type *base, uint32_t ch * @param channel Channel index for DAC instance. * @param config Pointer to the configuration structure. See "pdb_dac_trigger_config_t". */ -void PDB_SetDACTriggerConfig(PDB_Type *base, uint32_t channel, pdb_dac_trigger_config_t *config); +void PDB_SetDACTriggerConfig(PDB_Type *base, pdb_dac_trigger_channel_t channel, pdb_dac_trigger_config_t *config); /*! * @brief Sets the value for the DAC interval event. @@ -512,7 +552,7 @@ void PDB_SetDACTriggerConfig(PDB_Type *base, uint32_t channel, pdb_dac_trigger_c * @param channel Channel index for DAC instance. * @param value Setting value for the DAC interval event. */ -static inline void PDB_SetDACTriggerIntervalValue(PDB_Type *base, uint32_t channel, uint32_t value) +static inline void PDB_SetDACTriggerIntervalValue(PDB_Type *base, pdb_dac_trigger_channel_t channel, uint32_t value) { assert(channel < PDB_INT_COUNT); @@ -534,8 +574,10 @@ static inline void PDB_SetDACTriggerIntervalValue(PDB_Type *base, uint32_t chann * @param channelMask Channel mask value for multiple pulse out trigger channel. * @param enable Whether the feature is enabled or not. */ -static inline void PDB_EnablePulseOutTrigger(PDB_Type *base, uint32_t channelMask, bool enable) +static inline void PDB_EnablePulseOutTrigger(PDB_Type *base, pdb_pulse_out_channel_mask_t channelMask, bool enable) { + assert(channelMask < (1 << PDB_PODLY_COUNT)); + if (enable) { base->POEN |= PDB_POEN_POEN(channelMask); @@ -559,7 +601,7 @@ static inline void PDB_EnablePulseOutTrigger(PDB_Type *base, uint32_t channelMas * @param value1 Setting value for pulse out high. * @param value2 Setting value for pulse out low. */ -static inline void PDB_SetPulseOutTriggerDelayValue(PDB_Type *base, uint32_t channel, uint32_t value1, uint32_t value2) +static inline void PDB_SetPulseOutTriggerDelayValue(PDB_Type *base, pdb_pulse_out_trigger_channel_t channel, uint32_t value1, uint32_t value2) { assert(channel < PDB_PODLY_COUNT); diff --git a/ext/hal/nxp/mcux/drivers/kinetis/fsl_pit.c b/ext/hal/nxp/mcux/drivers/kinetis/fsl_pit.c index a4d08717d86..5de59188526 100644 --- a/ext/hal/nxp/mcux/drivers/kinetis/fsl_pit.c +++ b/ext/hal/nxp/mcux/drivers/kinetis/fsl_pit.c @@ -1,35 +1,18 @@ /* * Copyright (c) 2015, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP + * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * SPDX-License-Identifier: BSD-3-Clause */ #include "fsl_pit.h" +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.pit" +#endif + /******************************************************************************* * Prototypes ******************************************************************************/ @@ -74,6 +57,14 @@ static uint32_t PIT_GetInstance(PIT_Type *base) return instance; } +/*! + * brief Ungates the PIT clock, enables the PIT module, and configures the peripheral for basic operations. + * + * note This API should be called at the beginning of the application using the PIT driver. + * + * param base PIT peripheral base address + * param config Pointer to the user's PIT config structure + */ void PIT_Init(PIT_Type *base, const pit_config_t *config) { assert(config); @@ -87,6 +78,15 @@ void PIT_Init(PIT_Type *base, const pit_config_t *config) /* Enable PIT timers */ base->MCR &= ~PIT_MCR_MDIS_MASK; #endif + +#if defined(FSL_FEATURE_PIT_TIMER_COUNT) && (FSL_FEATURE_PIT_TIMER_COUNT) + /* Clear the timer enable bit for all channels to make sure the channel's timer is disabled. */ + for (uint8_t i = 0U; i < FSL_FEATURE_PIT_TIMER_COUNT; i++) + { + base->CHANNEL[i].TCTRL &= ~PIT_TCTRL_TEN_MASK; + } +#endif /* FSL_FEATURE_PIT_TIMER_COUNT */ + /* Config timer operation when in debug mode */ if (config->enableRunInDebug) { @@ -98,6 +98,11 @@ void PIT_Init(PIT_Type *base, const pit_config_t *config) } } +/*! + * brief Gates the PIT clock and disables the PIT module. + * + * param base PIT peripheral base address + */ void PIT_Deinit(PIT_Type *base) { #if defined(FSL_FEATURE_PIT_HAS_MDIS) && FSL_FEATURE_PIT_HAS_MDIS @@ -113,6 +118,19 @@ void PIT_Deinit(PIT_Type *base) #if defined(FSL_FEATURE_PIT_HAS_LIFETIME_TIMER) && FSL_FEATURE_PIT_HAS_LIFETIME_TIMER +/*! + * brief Reads the current lifetime counter value. + * + * The lifetime timer is a 64-bit timer which chains timer 0 and timer 1 together. + * Timer 0 and 1 are chained by calling the PIT_SetTimerChainMode before using this timer. + * The period of lifetime timer is equal to the "period of timer 0 * period of timer 1". + * For the 64-bit value, the higher 32-bit has the value of timer 1, and the lower 32-bit + * has the value of timer 0. + * + * param base PIT peripheral base address + * + * return Current lifetime timer value + */ uint64_t PIT_GetLifetimeTimerCount(PIT_Type *base) { uint32_t valueH = 0U; diff --git a/ext/hal/nxp/mcux/drivers/kinetis/fsl_pit.h b/ext/hal/nxp/mcux/drivers/kinetis/fsl_pit.h index 99c30e1e4bc..667ce8df269 100644 --- a/ext/hal/nxp/mcux/drivers/kinetis/fsl_pit.h +++ b/ext/hal/nxp/mcux/drivers/kinetis/fsl_pit.h @@ -1,31 +1,9 @@ /* * Copyright (c) 2015, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP + * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * SPDX-License-Identifier: BSD-3-Clause */ #ifndef _FSL_PIT_H_ #define _FSL_PIT_H_ @@ -37,14 +15,14 @@ * @{ */ - /******************************************************************************* * Definitions ******************************************************************************/ /*! @name Driver version */ /*@{*/ -#define FSL_PIT_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0 */ +/*! @brief PIT Driver Version 2.0.1 */ +#define FSL_PIT_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) /*@}*/ /*! @@ -122,7 +100,7 @@ void PIT_Deinit(PIT_Type *base); * @code * config->enableRunInDebug = false; * @endcode - * @param config Pointer to the onfiguration structure. + * @param config Pointer to the configuration structure. */ static inline void PIT_GetDefaultConfig(pit_config_t *config) { diff --git a/ext/hal/nxp/mcux/drivers/kinetis/fsl_pmc.c b/ext/hal/nxp/mcux/drivers/kinetis/fsl_pmc.c index bcdd5cb8231..da7029aeb91 100644 --- a/ext/hal/nxp/mcux/drivers/kinetis/fsl_pmc.c +++ b/ext/hal/nxp/mcux/drivers/kinetis/fsl_pmc.c @@ -1,35 +1,26 @@ /* * Copyright (c) 2015, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP + * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * SPDX-License-Identifier: BSD-3-Clause */ #include "fsl_pmc.h" +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.pmc" +#endif + #if (defined(FSL_FEATURE_PMC_HAS_PARAM) && FSL_FEATURE_PMC_HAS_PARAM) +/*! + * brief Gets the PMC parameter. + * + * This function gets the PMC parameter including the VLPO enable and the HVD enable. + * + * param base PMC peripheral base address. + * param param Pointer to PMC param structure. + */ void PMC_GetParam(PMC_Type *base, pmc_param_t *param) { uint32_t reg = base->PARAM; @@ -39,6 +30,15 @@ void PMC_GetParam(PMC_Type *base, pmc_param_t *param) } #endif /* FSL_FEATURE_PMC_HAS_PARAM */ +/*! + * brief Configures the low-voltage detect setting. + * + * This function configures the low-voltage detect setting, including the trip + * point voltage setting, enables or disables the interrupt, enables or disables the system reset. + * + * param base PMC peripheral base address. + * param config Low-voltage detect configuration structure. + */ void PMC_ConfigureLowVoltDetect(PMC_Type *base, const pmc_low_volt_detect_config_t *config) { base->LVDSC1 = (0U | @@ -51,6 +51,15 @@ void PMC_ConfigureLowVoltDetect(PMC_Type *base, const pmc_low_volt_detect_config | PMC_LVDSC1_LVDACK_MASK); } +/*! + * brief Configures the low-voltage warning setting. + * + * This function configures the low-voltage warning setting, including the trip + * point voltage setting and enabling or disabling the interrupt. + * + * param base PMC peripheral base address. + * param config Low-voltage warning configuration structure. + */ void PMC_ConfigureLowVoltWarning(PMC_Type *base, const pmc_low_volt_warning_config_t *config) { base->LVDSC2 = (0U | @@ -63,6 +72,15 @@ void PMC_ConfigureLowVoltWarning(PMC_Type *base, const pmc_low_volt_warning_conf } #if (defined(FSL_FEATURE_PMC_HAS_HVDSC1) && FSL_FEATURE_PMC_HAS_HVDSC1) +/*! + * brief Configures the high-voltage detect setting. + * + * This function configures the high-voltage detect setting, including the trip + * point voltage setting, enabling or disabling the interrupt, enabling or disabling the system reset. + * + * param base PMC peripheral base address. + * param config High-voltage detect configuration structure. + */ void PMC_ConfigureHighVoltDetect(PMC_Type *base, const pmc_high_volt_detect_config_t *config) { base->HVDSC1 = (((uint32_t)config->voltSelect << PMC_HVDSC1_HVDV_SHIFT) | @@ -76,6 +94,15 @@ void PMC_ConfigureHighVoltDetect(PMC_Type *base, const pmc_high_volt_detect_conf #if ((defined(FSL_FEATURE_PMC_HAS_BGBE) && FSL_FEATURE_PMC_HAS_BGBE) || \ (defined(FSL_FEATURE_PMC_HAS_BGEN) && FSL_FEATURE_PMC_HAS_BGEN) || \ (defined(FSL_FEATURE_PMC_HAS_BGBDS) && FSL_FEATURE_PMC_HAS_BGBDS)) +/*! + * brief Configures the PMC bandgap. + * + * This function configures the PMC bandgap, including the drive select and + * behavior in low-power mode. + * + * param base PMC peripheral base address. + * param config Pointer to the configuration structure + */ void PMC_ConfigureBandgapBuffer(PMC_Type *base, const pmc_bandgap_buffer_config_t *config) { base->REGSC = (0U diff --git a/ext/hal/nxp/mcux/drivers/kinetis/fsl_pmc.h b/ext/hal/nxp/mcux/drivers/kinetis/fsl_pmc.h index 99fc149fc22..6546fd0722c 100644 --- a/ext/hal/nxp/mcux/drivers/kinetis/fsl_pmc.h +++ b/ext/hal/nxp/mcux/drivers/kinetis/fsl_pmc.h @@ -1,31 +1,9 @@ /* * Copyright (c) 2015, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause */ #ifndef _FSL_PMC_H_ #define _FSL_PMC_H_ diff --git a/ext/hal/nxp/mcux/drivers/kinetis/fsl_port.h b/ext/hal/nxp/mcux/drivers/kinetis/fsl_port.h index eb8e77e6ddd..c72a789c4d7 100644 --- a/ext/hal/nxp/mcux/drivers/kinetis/fsl_port.h +++ b/ext/hal/nxp/mcux/drivers/kinetis/fsl_port.h @@ -1,31 +1,9 @@ /* * Copyright (c) 2015, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP + * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * SPDX-License-Identifier: BSD-3-Clause */ #ifndef _FSL_PORT_H_ #define _FSL_PORT_H_ @@ -41,10 +19,15 @@ * Definitions ******************************************************************************/ +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.port" +#endif + /*! @name Driver version */ /*@{*/ -/*! Version 2.0.2. */ -#define FSL_PORT_DRIVER_VERSION (MAKE_VERSION(2, 0, 2)) +/*! Version 2.1.0. */ +#define FSL_PORT_DRIVER_VERSION (MAKE_VERSION(2, 1, 0)) /*@}*/ #if defined(FSL_FEATURE_PORT_HAS_PULL_ENABLE) && FSL_FEATURE_PORT_HAS_PULL_ENABLE @@ -125,6 +108,7 @@ typedef enum _port_mux } port_mux_t; #endif /* FSL_FEATURE_PORT_PCR_MUX_WIDTH */ +#if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT) /*! @brief Configures the interrupt generation condition. */ typedef enum _port_interrupt { @@ -149,6 +133,7 @@ typedef enum _port_interrupt kPORT_ActiveLowTriggerOutputEnable = 0xEU, /*!< Enable active low-trigger output. */ #endif } port_interrupt_t; +#endif #if defined(FSL_FEATURE_PORT_HAS_DIGITAL_FILTER) && FSL_FEATURE_PORT_HAS_DIGITAL_FILTER /*! @brief Digital filter clock source selection */ @@ -204,13 +189,15 @@ typedef struct _port_pin_config uint16_t : 1; -#if defined(FSL_FEATURE_PORT_PCR_MUX_WIDTH) && FSL_FEATURE_PORT_PCR_MUX_WIDTH +#if defined(FSL_FEATURE_PORT_PCR_MUX_WIDTH) && (FSL_FEATURE_PORT_PCR_MUX_WIDTH == 3) uint16_t mux : 3; /*!< Pin mux Configure */ -#else - uint16_t : 3; -#endif - uint16_t : 4; +#elif defined(FSL_FEATURE_PORT_PCR_MUX_WIDTH) && (FSL_FEATURE_PORT_PCR_MUX_WIDTH == 4) + uint16_t mux : 4; /*!< Pin mux Configure */ + uint16_t : 3; +#else + uint16_t : 7, +#endif #if defined(FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK) && FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK uint16_t lockRegister : 1; /*!< Lock/unlock the PCR field[15:0] */ @@ -298,6 +285,44 @@ static inline void PORT_SetMultiplePinsConfig(PORT_Type *base, uint32_t mask, co } } +#if defined(FSL_FEATURE_PORT_HAS_MULTIPLE_IRQ_CONFIG) && FSL_FEATURE_PORT_HAS_MULTIPLE_IRQ_CONFIG +/*! + * @brief Sets the port interrupt configuration in PCR register for multiple pins. + * + * @param base PORT peripheral base pointer. + * @param mask PORT pin number macro. + * @param config PORT pin interrupt configuration. + * - #kPORT_InterruptOrDMADisabled: Interrupt/DMA request disabled. + * - #kPORT_DMARisingEdge : DMA request on rising edge(if the DMA requests exit). + * - #kPORT_DMAFallingEdge: DMA request on falling edge(if the DMA requests exit). + * - #kPORT_DMAEitherEdge : DMA request on either edge(if the DMA requests exit). + * - #kPORT_FlagRisingEdge : Flag sets on rising edge(if the Flag states exit). + * - #kPORT_FlagFallingEdge : Flag sets on falling edge(if the Flag states exit). + * - #kPORT_FlagEitherEdge : Flag sets on either edge(if the Flag states exit). + * - #kPORT_InterruptLogicZero : Interrupt when logic zero. + * - #kPORT_InterruptRisingEdge : Interrupt on rising edge. + * - #kPORT_InterruptFallingEdge: Interrupt on falling edge. + * - #kPORT_InterruptEitherEdge : Interrupt on either edge. + * - #kPORT_InterruptLogicOne : Interrupt when logic one. + * - #kPORT_ActiveHighTriggerOutputEnable : Enable active high-trigger output (if the trigger states exit). + * - #kPORT_ActiveLowTriggerOutputEnable : Enable active low-trigger output (if the trigger states exit).. + */ +static inline void PORT_SetMultipleInterruptPinsConfig(PORT_Type *base, uint32_t mask, port_interrupt_t config) +{ + assert(config); + + if (mask & 0xffffU) + { + base->GICLR = (config << 16) | (mask & 0xffffU); + } + mask = mask >> 16; + if (mask) + { + base->GICHR = (config << 16) | (mask & 0xffffU); + } +} +#endif + /*! * @brief Configures the pin muxing. * @@ -365,6 +390,7 @@ static inline void PORT_SetDigitalFilterConfig(PORT_Type *base, const port_digit /*! @name Interrupt */ /*@{*/ +#if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT) /*! * @brief Configures the port pin interrupt/DMA request. * @@ -390,7 +416,25 @@ static inline void PORT_SetPinInterruptConfig(PORT_Type *base, uint32_t pin, por { base->PCR[pin] = (base->PCR[pin] & ~PORT_PCR_IRQC_MASK) | PORT_PCR_IRQC(config); } +#endif +#if defined(FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH) && FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH +/*! + * @brief Configures the port pin drive strength. + * + * @param base PORT peripheral base pointer. + * @param pin PORT pin number. + * @param config PORT pin drive strength + * - #kPORT_LowDriveStrength = 0U - Low-drive strength is configured. + * - #kPORT_HighDriveStrength = 1U - High-drive strength is configured. + */ +static inline void PORT_SetPinDriveStrength(PORT_Type *base, uint32_t pin, uint8_t strength) +{ + base->PCR[pin] = (base->PCR[pin] & ~PORT_PCR_DSE_MASK) | PORT_PCR_DSE(strength); +} +#endif + +#if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT) /*! * @brief Reads the whole port status flag. * @@ -419,6 +463,7 @@ static inline void PORT_ClearPinsInterruptFlags(PORT_Type *base, uint32_t mask) { base->ISFR = mask; } +#endif /*@}*/ diff --git a/ext/hal/nxp/mcux/drivers/kinetis/fsl_rcm.c b/ext/hal/nxp/mcux/drivers/kinetis/fsl_rcm.c index 0d738643b53..fdc491a9efc 100644 --- a/ext/hal/nxp/mcux/drivers/kinetis/fsl_rcm.c +++ b/ext/hal/nxp/mcux/drivers/kinetis/fsl_rcm.c @@ -1,35 +1,27 @@ /* * Copyright (c) 2015, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP + * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * SPDX-License-Identifier: BSD-3-Clause */ #include "fsl_rcm.h" +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.rcm" +#endif + +/*! + * brief Configures the reset pin filter. + * + * This function sets the reset pin filter including the filter source, filter + * width, and so on. + * + * param base RCM peripheral base address. + * param config Pointer to the configuration structure. + */ void RCM_ConfigureResetPinFilter(RCM_Type *base, const rcm_reset_pin_filter_config_t *config) { assert(config); @@ -53,6 +45,14 @@ void RCM_ConfigureResetPinFilter(RCM_Type *base, const rcm_reset_pin_filter_conf } #if (defined(FSL_FEATURE_RCM_HAS_BOOTROM) && FSL_FEATURE_RCM_HAS_BOOTROM) +/*! + * brief Forces the boot from ROM. + * + * This function forces booting from ROM during all subsequent system resets. + * + * param base RCM peripheral base address. + * param config Boot configuration. + */ void RCM_SetForceBootRomSource(RCM_Type *base, rcm_boot_rom_config_t config) { uint32_t reg; diff --git a/ext/hal/nxp/mcux/drivers/kinetis/fsl_rcm.h b/ext/hal/nxp/mcux/drivers/kinetis/fsl_rcm.h index 99b843aaf3a..3229e548434 100644 --- a/ext/hal/nxp/mcux/drivers/kinetis/fsl_rcm.h +++ b/ext/hal/nxp/mcux/drivers/kinetis/fsl_rcm.h @@ -1,31 +1,9 @@ /* * Copyright (c) 2015, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP + * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * SPDX-License-Identifier: BSD-3-Clause */ #ifndef _FSL_RCM_H_ #define _FSL_RCM_H_ @@ -35,7 +13,6 @@ /*! @addtogroup rcm */ /*! @{*/ - /******************************************************************************* * Definitions ******************************************************************************/ @@ -107,7 +84,7 @@ typedef enum _rcm_reset_source #endif /* FSL_FEATURE_RCM_HAS_EZPORT */ kRCM_SourceSackerr = RCM_SRS1_SACKERR_MASK << 8U, /*!< Parameter could get all reset flags */ #endif /* (FSL_FEATURE_RCM_REG_WIDTH == 32) */ - kRCM_SourceAll = 0xffffffffU, + kRCM_SourceAll = (int)0xffffffffU, } rcm_reset_source_t; /*! diff --git a/ext/hal/nxp/mcux/drivers/kinetis/fsl_rnga.c b/ext/hal/nxp/mcux/drivers/kinetis/fsl_rnga.c index 6f0adc66f59..43d77e9fa51 100644 --- a/ext/hal/nxp/mcux/drivers/kinetis/fsl_rnga.c +++ b/ext/hal/nxp/mcux/drivers/kinetis/fsl_rnga.c @@ -1,31 +1,9 @@ /* * Copyright (c) 2015, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP + * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * SPDX-License-Identifier: BSD-3-Clause */ #include "fsl_rnga.h" @@ -36,6 +14,11 @@ * Definitions *******************************************************************************/ +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.rnga" +#endif + /******************************************************************************* * RNG_CR - RNGA Control Register ******************************************************************************/ @@ -179,12 +162,20 @@ static uint32_t rnga_ReadEntropy(RNG_Type *base); * Code ******************************************************************************/ +/*! + * brief Initializes the RNGA. + * + * This function initializes the RNGA. + * When called, the RNGA entropy generation starts immediately. + * + * param base RNGA base address + */ void RNGA_Init(RNG_Type *base) { #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) /* Enable the clock gate. */ CLOCK_EnableClock(kCLOCK_Rnga0); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ CLOCK_DisableClock(kCLOCK_Rnga0); /* To solve the release version on twrkm43z75m */ #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) CLOCK_EnableClock(kCLOCK_Rnga0); @@ -196,6 +187,13 @@ void RNGA_Init(RNG_Type *base) RNG_WR_CR_GO(base, 1); } +/*! + * brief Shuts down the RNGA. + * + * This function shuts down the RNGA. + * + * param base RNGA base address + */ void RNGA_Deinit(RNG_Type *base) { #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) @@ -224,6 +222,16 @@ static uint32_t rnga_ReadEntropy(RNG_Type *base) return data; } +/*! + * brief Gets random data. + * + * This function gets random data from the RNGA. + * + * param base RNGA base address + * param data pointer to user buffer to be filled by random data + * param data_size size of data in bytes + * return RNGA status + */ status_t RNGA_GetRandomData(RNG_Type *base, void *data, size_t data_size) { status_t result = kStatus_Success; @@ -268,16 +276,41 @@ status_t RNGA_GetRandomData(RNG_Type *base, void *data, size_t data_size) return result; } +/*! + * brief Sets the RNGA in normal mode or sleep mode. + * + * This function sets the RNGA in sleep mode or normal mode. + * + * param base RNGA base address + * param mode normal mode or sleep mode + */ void RNGA_SetMode(RNG_Type *base, rnga_mode_t mode) { RNG_WR_CR_SLP(base, (uint32_t)mode); } +/*! + * brief Gets the RNGA working mode. + * + * This function gets the RNGA working mode. + * + * param base RNGA base address + * return normal mode or sleep mode + */ rnga_mode_t RNGA_GetMode(RNG_Type *base) { return (rnga_mode_t)RNG_RD_SR_SLP(base); } +/*! + * brief Feeds the RNGA module. + * + * This function inputs an entropy value that the RNGA uses to seed its + * pseudo-random algorithm. + * + * param base RNGA base address + * param seed input seed value + */ void RNGA_Seed(RNG_Type *base, uint32_t seed) { /* Write to RNGA Entropy Register.*/ diff --git a/ext/hal/nxp/mcux/drivers/kinetis/fsl_rnga.h b/ext/hal/nxp/mcux/drivers/kinetis/fsl_rnga.h index 92f5bff8bec..93d8709b39a 100644 --- a/ext/hal/nxp/mcux/drivers/kinetis/fsl_rnga.h +++ b/ext/hal/nxp/mcux/drivers/kinetis/fsl_rnga.h @@ -1,31 +1,9 @@ /* * Copyright (c) 2015, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause */ #ifndef _FSL_RNGA_DRIVER_H_ #define _FSL_RNGA_DRIVER_H_ diff --git a/ext/hal/nxp/mcux/drivers/kinetis/fsl_rtc.c b/ext/hal/nxp/mcux/drivers/kinetis/fsl_rtc.c index d68055a2690..e37408ed72b 100644 --- a/ext/hal/nxp/mcux/drivers/kinetis/fsl_rtc.c +++ b/ext/hal/nxp/mcux/drivers/kinetis/fsl_rtc.c @@ -1,31 +1,9 @@ /* * Copyright (c) 2015, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP + * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * SPDX-License-Identifier: BSD-3-Clause */ #include "fsl_rtc.h" @@ -33,6 +11,12 @@ /******************************************************************************* * Definitions ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.rtc" +#endif + #define SECONDS_IN_A_DAY (86400U) #define SECONDS_IN_A_HOUR (3600U) #define SECONDS_IN_A_MINUTE (60U) @@ -205,15 +189,27 @@ static void RTC_ConvertSecondsToDatetime(uint32_t seconds, rtc_datetime_t *datet datetime->day = days; } +/*! + * brief Ungates the RTC clock and configures the peripheral for basic operation. + * + * This function issues a software reset if the timer invalid flag is set. + * + * note This API should be called at the beginning of the application using the RTC driver. + * + * param base RTC peripheral base address + * param config Pointer to the user's RTC configuration structure. + */ void RTC_Init(RTC_Type *base, const rtc_config_t *config) { assert(config); uint32_t reg; +#if defined(RTC_CLOCKS) #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) CLOCK_EnableClock(kCLOCK_Rtc0); #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +#endif /* RTC_CLOCKS */ /* Issue a software reset if timer is invalid */ if (RTC_GetStatusFlags(RTC) & kRTC_TimeInvalidFlag) @@ -222,9 +218,15 @@ void RTC_Init(RTC_Type *base, const rtc_config_t *config) } reg = base->CR; - /* Setup the update mode and supervisor access mode */ +/* Setup the update mode and supervisor access mode */ +#if !(defined(FSL_FEATURE_RTC_HAS_NO_CR_OSCE) && FSL_FEATURE_RTC_HAS_NO_CR_OSCE) reg &= ~(RTC_CR_UM_MASK | RTC_CR_SUP_MASK); reg |= RTC_CR_UM(config->updateMode) | RTC_CR_SUP(config->supervisorAccess); +#else + reg &= ~RTC_CR_UM_MASK; + reg |= RTC_CR_UM(config->updateMode); +#endif + #if defined(FSL_FEATURE_RTC_HAS_WAKEUP_PIN_SELECTION) && FSL_FEATURE_RTC_HAS_WAKEUP_PIN_SELECTION /* Setup the wakeup pin select */ reg &= ~(RTC_CR_WPS_MASK); @@ -234,12 +236,33 @@ void RTC_Init(RTC_Type *base, const rtc_config_t *config) /* Configure the RTC time compensation register */ base->TCR = (RTC_TCR_CIR(config->compensationInterval) | RTC_TCR_TCR(config->compensationTime)); + +#if defined(FSL_FEATURE_RTC_HAS_TSIC) && FSL_FEATURE_RTC_HAS_TSIC + /* Configure RTC timer seconds interrupt to be generated once per second */ + base->IER &= ~(RTC_IER_TSIC_MASK | RTC_IER_TSIE_MASK); +#endif } +/*! + * brief Fills in the RTC config struct with the default settings. + * + * The default values are as follows. + * code + * config->wakeupSelect = false; + * config->updateMode = false; + * config->supervisorAccess = false; + * config->compensationInterval = 0; + * config->compensationTime = 0; + * endcode + * param config Pointer to the user's RTC configuration structure. + */ void RTC_GetDefaultConfig(rtc_config_t *config) { assert(config); + /* Initializes the configure structure to zero. */ + memset(config, 0, sizeof(*config)); + /* Wakeup pin will assert if the RTC interrupt asserts or if the wakeup pin is turned on */ config->wakeupSelect = false; /* Registers cannot be written when locked */ @@ -252,6 +275,18 @@ void RTC_GetDefaultConfig(rtc_config_t *config) config->compensationTime = 0; } +/*! + * brief Sets the RTC date and time according to the given time structure. + * + * The RTC counter must be stopped prior to calling this function because writes to the RTC + * seconds register fail if the RTC counter is running. + * + * param base RTC peripheral base address + * param datetime Pointer to the structure where the date and time details are stored. + * + * return kStatus_Success: Success in setting the time and starting the RTC + * kStatus_InvalidArgument: Error because the datetime format is incorrect + */ status_t RTC_SetDatetime(RTC_Type *base, const rtc_datetime_t *datetime) { assert(datetime); @@ -268,6 +303,12 @@ status_t RTC_SetDatetime(RTC_Type *base, const rtc_datetime_t *datetime) return kStatus_Success; } +/*! + * brief Gets the RTC time and stores it in the given time structure. + * + * param base RTC peripheral base address + * param datetime Pointer to the structure where the date and time details are stored. + */ void RTC_GetDatetime(RTC_Type *base, rtc_datetime_t *datetime) { assert(datetime); @@ -278,6 +319,19 @@ void RTC_GetDatetime(RTC_Type *base, rtc_datetime_t *datetime) RTC_ConvertSecondsToDatetime(seconds, datetime); } +/*! + * brief Sets the RTC alarm time. + * + * The function checks whether the specified alarm time is greater than the present + * time. If not, the function does not set the alarm and returns an error. + * + * param base RTC peripheral base address + * param alarmTime Pointer to the structure where the alarm time is stored. + * + * return kStatus_Success: success in setting the RTC alarm + * kStatus_InvalidArgument: Error because the alarm datetime format is incorrect + * kStatus_Fail: Error because the alarm time has already passed + */ status_t RTC_SetAlarm(RTC_Type *base, const rtc_datetime_t *alarmTime) { assert(alarmTime); @@ -308,6 +362,12 @@ status_t RTC_SetAlarm(RTC_Type *base, const rtc_datetime_t *alarmTime) return kStatus_Success; } +/*! + * brief Returns the RTC alarm time. + * + * param base RTC peripheral base address + * param datetime Pointer to the structure where the alarm date and time details are stored. + */ void RTC_GetAlarm(RTC_Type *base, rtc_datetime_t *datetime) { assert(datetime); @@ -320,6 +380,293 @@ void RTC_GetAlarm(RTC_Type *base, rtc_datetime_t *datetime) RTC_ConvertSecondsToDatetime(alarmSeconds, datetime); } +/*! + * brief Enables the selected RTC interrupts. + * + * param base RTC peripheral base address + * param mask The interrupts to enable. This is a logical OR of members of the + * enumeration ::rtc_interrupt_enable_t + */ +void RTC_EnableInterrupts(RTC_Type *base, uint32_t mask) +{ + uint32_t tmp32 = 0U; + + /* RTC_IER */ + if (kRTC_TimeInvalidInterruptEnable == (kRTC_TimeInvalidInterruptEnable & mask)) + { + tmp32 |= RTC_IER_TIIE_MASK; + } + if (kRTC_TimeOverflowInterruptEnable == (kRTC_TimeOverflowInterruptEnable & mask)) + { + tmp32 |= RTC_IER_TOIE_MASK; + } + if (kRTC_AlarmInterruptEnable == (kRTC_AlarmInterruptEnable & mask)) + { + tmp32 |= RTC_IER_TAIE_MASK; + } + if (kRTC_SecondsInterruptEnable == (kRTC_SecondsInterruptEnable & mask)) + { + tmp32 |= RTC_IER_TSIE_MASK; + } +#if defined(FSL_FEATURE_RTC_HAS_MONOTONIC) && (FSL_FEATURE_RTC_HAS_MONOTONIC) + if (kRTC_MonotonicOverflowInterruptEnable == (kRTC_MonotonicOverflowInterruptEnable & mask)) + { + tmp32 |= RTC_IER_MOIE_MASK; + } +#endif /* FSL_FEATURE_RTC_HAS_MONOTONIC */ + base->IER |= tmp32; + +#if (defined(FSL_FEATURE_RTC_HAS_TIR) && FSL_FEATURE_RTC_HAS_TIR) + tmp32 = 0U; + + /* RTC_TIR */ + if (kRTC_TestModeInterruptEnable == (kRTC_TestModeInterruptEnable & mask)) + { + tmp32 |= RTC_TIR_TMIE_MASK; + } + if (kRTC_FlashSecurityInterruptEnable == (kRTC_FlashSecurityInterruptEnable & mask)) + { + tmp32 |= RTC_TIR_FSIE_MASK; + } +#if (defined(FSL_FEATURE_RTC_HAS_TIR_TPIE) && FSL_FEATURE_RTC_HAS_TIR_TPIE) + if (kRTC_TamperPinInterruptEnable == (kRTC_TamperPinInterruptEnable & mask)) + { + tmp32 |= RTC_TIR_TPIE_MASK; + } +#endif /* FSL_FEATURE_RTC_HAS_TIR_TPIE */ +#if (defined(FSL_FEATURE_RTC_HAS_TIR_SIE) && FSL_FEATURE_RTC_HAS_TIR_SIE) + if (kRTC_SecurityModuleInterruptEnable == (kRTC_SecurityModuleInterruptEnable & mask)) + { + tmp32 |= RTC_TIR_SIE_MASK; + } +#endif /* FSL_FEATURE_RTC_HAS_TIR_SIE */ +#if (defined(FSL_FEATURE_RTC_HAS_TIR_LCIE) && FSL_FEATURE_RTC_HAS_TIR_LCIE) + if (kRTC_LossOfClockInterruptEnable == (kRTC_LossOfClockInterruptEnable & mask)) + { + tmp32 |= RTC_TIR_LCIE_MASK; + } +#endif /* FSL_FEATURE_RTC_HAS_TIR_LCIE */ + base->TIR |= tmp32; +#endif /* FSL_FEATURE_RTC_HAS_TIR */ +} + +/*! + * brief Disables the selected RTC interrupts. + * + * param base RTC peripheral base address + * param mask The interrupts to enable. This is a logical OR of members of the + * enumeration ::rtc_interrupt_enable_t + */ +void RTC_DisableInterrupts(RTC_Type *base, uint32_t mask) +{ + uint32_t tmp32 = 0U; + + /* RTC_IER */ + if (kRTC_TimeInvalidInterruptEnable == (kRTC_TimeInvalidInterruptEnable & mask)) + { + tmp32 |= RTC_IER_TIIE_MASK; + } + if (kRTC_TimeOverflowInterruptEnable == (kRTC_TimeOverflowInterruptEnable & mask)) + { + tmp32 |= RTC_IER_TOIE_MASK; + } + if (kRTC_AlarmInterruptEnable == (kRTC_AlarmInterruptEnable & mask)) + { + tmp32 |= RTC_IER_TAIE_MASK; + } + if (kRTC_SecondsInterruptEnable == (kRTC_SecondsInterruptEnable & mask)) + { + tmp32 |= RTC_IER_TSIE_MASK; + } +#if defined(FSL_FEATURE_RTC_HAS_MONOTONIC) && (FSL_FEATURE_RTC_HAS_MONOTONIC) + if (kRTC_MonotonicOverflowInterruptEnable == (kRTC_MonotonicOverflowInterruptEnable & mask)) + { + tmp32 |= RTC_IER_MOIE_MASK; + } +#endif /* FSL_FEATURE_RTC_HAS_MONOTONIC */ + base->IER &= (uint32_t)(~tmp32); + +#if (defined(FSL_FEATURE_RTC_HAS_TIR) && FSL_FEATURE_RTC_HAS_TIR) + tmp32 = 0U; + + /* RTC_TIR */ + if (kRTC_TestModeInterruptEnable == (kRTC_TestModeInterruptEnable & mask)) + { + tmp32 |= RTC_TIR_TMIE_MASK; + } + if (kRTC_FlashSecurityInterruptEnable == (kRTC_FlashSecurityInterruptEnable & mask)) + { + tmp32 |= RTC_TIR_FSIE_MASK; + } +#if (defined(FSL_FEATURE_RTC_HAS_TIR_TPIE) && FSL_FEATURE_RTC_HAS_TIR_TPIE) + if (kRTC_TamperPinInterruptEnable == (kRTC_TamperPinInterruptEnable & mask)) + { + tmp32 |= RTC_TIR_TPIE_MASK; + } +#endif /* FSL_FEATURE_RTC_HAS_TIR_TPIE */ +#if (defined(FSL_FEATURE_RTC_HAS_TIR_SIE) && FSL_FEATURE_RTC_HAS_TIR_SIE) + if (kRTC_SecurityModuleInterruptEnable == (kRTC_SecurityModuleInterruptEnable & mask)) + { + tmp32 |= RTC_TIR_SIE_MASK; + } +#endif /* FSL_FEATURE_RTC_HAS_TIR_SIE */ +#if (defined(FSL_FEATURE_RTC_HAS_TIR_LCIE) && FSL_FEATURE_RTC_HAS_TIR_LCIE) + if (kRTC_LossOfClockInterruptEnable == (kRTC_LossOfClockInterruptEnable & mask)) + { + tmp32 |= RTC_TIR_LCIE_MASK; + } +#endif /* FSL_FEATURE_RTC_HAS_TIR_LCIE */ + base->TIR &= (uint32_t)(~tmp32); +#endif /* FSL_FEATURE_RTC_HAS_TIR */ +} + +/*! + * brief Gets the enabled RTC interrupts. + * + * param base RTC peripheral base address + * + * return The enabled interrupts. This is the logical OR of members of the + * enumeration ::rtc_interrupt_enable_t + */ +uint32_t RTC_GetEnabledInterrupts(RTC_Type *base) +{ + uint32_t tmp32 = 0U; + + /* RTC_IER */ + if (RTC_IER_TIIE_MASK == (RTC_IER_TIIE_MASK & base->IER)) + { + tmp32 |= kRTC_TimeInvalidInterruptEnable; + } + if (RTC_IER_TOIE_MASK == (RTC_IER_TOIE_MASK & base->IER)) + { + tmp32 |= kRTC_TimeOverflowInterruptEnable; + } + if (RTC_IER_TAIE_MASK == (RTC_IER_TAIE_MASK & base->IER)) + { + tmp32 |= kRTC_AlarmInterruptEnable; + } + if (RTC_IER_TSIE_MASK == (RTC_IER_TSIE_MASK & base->IER)) + { + tmp32 |= kRTC_SecondsInterruptEnable; + } +#if defined(FSL_FEATURE_RTC_HAS_MONOTONIC) && (FSL_FEATURE_RTC_HAS_MONOTONIC) + if (RTC_IER_MOIE_MASK == (RTC_IER_MOIE_MASK & base->IER)) + { + tmp32 |= kRTC_MonotonicOverflowInterruptEnable; + } +#endif /* FSL_FEATURE_RTC_HAS_MONOTONIC */ + +#if (defined(FSL_FEATURE_RTC_HAS_TIR) && FSL_FEATURE_RTC_HAS_TIR) + /* RTC_TIR */ + if (RTC_TIR_TMIE_MASK == (RTC_TIR_TMIE_MASK & base->TIR)) + { + tmp32 |= kRTC_TestModeInterruptEnable; + } + if (RTC_TIR_FSIE_MASK == (RTC_TIR_FSIE_MASK & base->TIR)) + { + tmp32 |= kRTC_FlashSecurityInterruptEnable; + } +#if (defined(FSL_FEATURE_RTC_HAS_TIR_TPIE) && FSL_FEATURE_RTC_HAS_TIR_TPIE) + if (RTC_TIR_TPIE_MASK == (RTC_TIR_TPIE_MASK & base->TIR)) + { + tmp32 |= kRTC_TamperPinInterruptEnable; + } +#endif /* FSL_FEATURE_RTC_HAS_TIR_TPIE */ +#if (defined(FSL_FEATURE_RTC_HAS_TIR_SIE) && FSL_FEATURE_RTC_HAS_TIR_SIE) + if (RTC_TIR_SIE_MASK == (RTC_TIR_SIE_MASK & base->TIR)) + { + tmp32 |= kRTC_SecurityModuleInterruptEnable; + } +#endif /* FSL_FEATURE_RTC_HAS_TIR_SIE */ +#if (defined(FSL_FEATURE_RTC_HAS_TIR_LCIE) && FSL_FEATURE_RTC_HAS_TIR_LCIE) + if (RTC_TIR_LCIE_MASK == (RTC_TIR_LCIE_MASK & base->TIR)) + { + tmp32 |= kRTC_LossOfClockInterruptEnable; + } +#endif /* FSL_FEATURE_RTC_HAS_TIR_LCIE */ +#endif /* FSL_FEATURE_RTC_HAS_TIR */ + + return tmp32; +} + +/*! + * brief Gets the RTC status flags. + * + * param base RTC peripheral base address + * + * return The status flags. This is the logical OR of members of the + * enumeration ::rtc_status_flags_t + */ +uint32_t RTC_GetStatusFlags(RTC_Type *base) +{ + uint32_t tmp32 = 0U; + + /* RTC_SR */ + if (RTC_SR_TIF_MASK == (RTC_SR_TIF_MASK & base->SR)) + { + tmp32 |= kRTC_TimeInvalidFlag; + } + if (RTC_SR_TOF_MASK == (RTC_SR_TOF_MASK & base->SR)) + { + tmp32 |= kRTC_TimeOverflowFlag; + } + if (RTC_SR_TAF_MASK == (RTC_SR_TAF_MASK & base->SR)) + { + tmp32 |= kRTC_AlarmFlag; + } +#if defined(FSL_FEATURE_RTC_HAS_MONOTONIC) && (FSL_FEATURE_RTC_HAS_MONOTONIC) + if (RTC_SR_MOF_MASK == (RTC_SR_MOF_MASK & base->SR)) + { + tmp32 |= kRTC_MonotonicOverflowFlag; + } +#endif /* FSL_FEATURE_RTC_HAS_MONOTONIC */ +#if (defined(FSL_FEATURE_RTC_HAS_SR_TIDF) && FSL_FEATURE_RTC_HAS_SR_TIDF) + if (RTC_SR_TIDF_MASK == (RTC_SR_TIDF_MASK & base->SR)) + { + tmp32 |= kRTC_TamperInterruptDetectFlag; + } +#endif /* FSL_FEATURE_RTC_HAS_SR_TIDF */ + +#if (defined(FSL_FEATURE_RTC_HAS_TDR) && FSL_FEATURE_RTC_HAS_TDR) + /* RTC_TDR */ + if (RTC_TDR_TMF_MASK == (RTC_TDR_TMF_MASK & base->TDR)) + { + tmp32 |= kRTC_TestModeFlag; + } + if (RTC_TDR_FSF_MASK == (RTC_TDR_FSF_MASK & base->TDR)) + { + tmp32 |= kRTC_FlashSecurityFlag; + } +#if (defined(FSL_FEATURE_RTC_HAS_TDR_TPF) && FSL_FEATURE_RTC_HAS_TDR_TPF) + if (RTC_TDR_TPF_MASK == (RTC_TDR_TPF_MASK & base->TDR)) + { + tmp32 |= kRTC_TamperPinFlag; + } +#endif /* FSL_FEATURE_RTC_HAS_TDR_TPF */ +#if (defined(FSL_FEATURE_RTC_HAS_TDR_STF) && FSL_FEATURE_RTC_HAS_TDR_STF) + if (RTC_TDR_STF_MASK == (RTC_TDR_STF_MASK & base->TDR)) + { + tmp32 |= kRTC_SecurityTamperFlag; + } +#endif /* FSL_FEATURE_RTC_HAS_TDR_STF */ +#if (defined(FSL_FEATURE_RTC_HAS_TDR_LCTF) && FSL_FEATURE_RTC_HAS_TDR_LCTF) + if (RTC_TDR_LCTF_MASK == (RTC_TDR_LCTF_MASK & base->TDR)) + { + tmp32 |= kRTC_LossOfClockTamperFlag; + } +#endif /* FSL_FEATURE_RTC_HAS_TDR_LCTF */ +#endif /* FSL_FEATURE_RTC_HAS_TDR */ + + return tmp32; +} + +/*! + * brief Clears the RTC status flags. + * + * param base RTC peripheral base address + * param mask The status flags to clear. This is a logical OR of members of the + * enumeration ::rtc_status_flags_t + */ void RTC_ClearStatusFlags(RTC_Type *base, uint32_t mask) { /* The alarm flag is cleared by writing to the TAR register */ @@ -343,10 +690,51 @@ void RTC_ClearStatusFlags(RTC_Type *base, uint32_t mask) { base->TSR = 1U; } + +#if (defined(FSL_FEATURE_RTC_HAS_TDR) && FSL_FEATURE_RTC_HAS_TDR) + /* To clear, write logic one to this flag after exiting from all test modes */ + if (kRTC_TestModeFlag == (kRTC_TestModeFlag & mask)) + { + base->TDR = RTC_TDR_TMF_MASK; + } + /* To clear, write logic one to this flag after flash security is enabled */ + if (kRTC_FlashSecurityFlag == (kRTC_FlashSecurityFlag & mask)) + { + base->TDR = RTC_TDR_FSF_MASK; + } +#if (defined(FSL_FEATURE_RTC_HAS_TDR_TPF) && FSL_FEATURE_RTC_HAS_TDR_TPF) + /* To clear, write logic one to the corresponding flag after that tamper pin negates */ + if (kRTC_TamperPinFlag == (kRTC_TamperPinFlag & mask)) + { + base->TDR = RTC_TDR_TPF_MASK; + } +#endif /* FSL_FEATURE_RTC_HAS_TDR_TPF */ +#if (defined(FSL_FEATURE_RTC_HAS_TDR_STF) && FSL_FEATURE_RTC_HAS_TDR_STF) + /* To clear, write logic one to this flag after security module has negated its tamper detect */ + if (kRTC_SecurityTamperFlag == (kRTC_SecurityTamperFlag & mask)) + { + base->TDR = RTC_TDR_STF_MASK; + } +#endif /* FSL_FEATURE_RTC_HAS_TDR_STF */ +#if (defined(FSL_FEATURE_RTC_HAS_TDR_LCTF) && FSL_FEATURE_RTC_HAS_TDR_LCTF) + /* To clear, write logic one to this flag after loss of clock negates */ + if (kRTC_LossOfClockTamperFlag == (kRTC_LossOfClockTamperFlag & mask)) + { + base->TDR = RTC_TDR_LCTF_MASK; + } +#endif /* FSL_FEATURE_RTC_HAS_TDR_LCTF */ +#endif /* FSL_FEATURE_RTC_HAS_TDR */ } #if defined(FSL_FEATURE_RTC_HAS_MONOTONIC) && (FSL_FEATURE_RTC_HAS_MONOTONIC) +/*! + * brief Reads the values of the Monotonic Counter High and Monotonic Counter Low and returns + * them as a single value. + * + * param base RTC peripheral base address + * param counter Pointer to variable where the value is stored. + */ void RTC_GetMonotonicCounter(RTC_Type *base, uint64_t *counter) { assert(counter); @@ -354,6 +742,13 @@ void RTC_GetMonotonicCounter(RTC_Type *base, uint64_t *counter) *counter = (((uint64_t)base->MCHR << 32) | ((uint64_t)base->MCLR)); } +/*! + * brief Writes values Monotonic Counter High and Monotonic Counter Low by decomposing + * the given single value. The Monotonic Overflow Flag in RTC_SR is cleared due to the API. + * + * param base RTC peripheral base address + * param counter Counter value + */ void RTC_SetMonotonicCounter(RTC_Type *base, uint64_t counter) { /* Prepare to initialize the register with the new value written */ @@ -363,6 +758,18 @@ void RTC_SetMonotonicCounter(RTC_Type *base, uint64_t counter) base->MCLR = (uint32_t)(counter); } +/*! + * brief Increments the Monotonic Counter by one. + * + * Increments the Monotonic Counter (registers RTC_MCLR and RTC_MCHR accordingly) by setting + * the monotonic counter enable (MER[MCE]) and then writing to the RTC_MCLR register. A write to the + * monotonic counter low that causes it to overflow also increments the monotonic counter high. + * + * param base RTC peripheral base address + * + * return kStatus_Success: success + * kStatus_Fail: error occurred, either time invalid or monotonic overflow flag was found + */ status_t RTC_IncrementMonotonicCounter(RTC_Type *base) { if (base->SR & (RTC_SR_MOF_MASK | RTC_SR_TIF_MASK)) diff --git a/ext/hal/nxp/mcux/drivers/kinetis/fsl_rtc.h b/ext/hal/nxp/mcux/drivers/kinetis/fsl_rtc.h index 99effc6dcb9..cca704205b4 100644 --- a/ext/hal/nxp/mcux/drivers/kinetis/fsl_rtc.h +++ b/ext/hal/nxp/mcux/drivers/kinetis/fsl_rtc.h @@ -1,31 +1,9 @@ /* * Copyright (c) 2015, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause */ #ifndef _FSL_RTC_H_ #define _FSL_RTC_H_ @@ -37,31 +15,65 @@ * @{ */ - /******************************************************************************* * Definitions ******************************************************************************/ /*! @name Driver version */ /*@{*/ -#define FSL_RTC_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0 */ +#define FSL_RTC_DRIVER_VERSION (MAKE_VERSION(2, 1, 0)) /*!< Version 2.1.0 */ /*@}*/ /*! @brief List of RTC interrupts */ typedef enum _rtc_interrupt_enable { - kRTC_TimeInvalidInterruptEnable = RTC_IER_TIIE_MASK, /*!< Time invalid interrupt.*/ - kRTC_TimeOverflowInterruptEnable = RTC_IER_TOIE_MASK, /*!< Time overflow interrupt.*/ - kRTC_AlarmInterruptEnable = RTC_IER_TAIE_MASK, /*!< Alarm interrupt.*/ - kRTC_SecondsInterruptEnable = RTC_IER_TSIE_MASK /*!< Seconds interrupt.*/ + kRTC_TimeInvalidInterruptEnable = (1U << 0U), /*!< Time invalid interrupt.*/ + kRTC_TimeOverflowInterruptEnable = (1U << 1U), /*!< Time overflow interrupt.*/ + kRTC_AlarmInterruptEnable = (1U << 2U), /*!< Alarm interrupt.*/ + kRTC_SecondsInterruptEnable = (1U << 3U), /*!< Seconds interrupt.*/ +#if defined(FSL_FEATURE_RTC_HAS_MONOTONIC) && (FSL_FEATURE_RTC_HAS_MONOTONIC) + kRTC_MonotonicOverflowInterruptEnable = (1U << 4U), /*!< Monotonic Overflow Interrupt Enable */ +#endif /* FSL_FEATURE_RTC_HAS_MONOTONIC */ +#if (defined(FSL_FEATURE_RTC_HAS_TIR) && FSL_FEATURE_RTC_HAS_TIR) + kRTC_TestModeInterruptEnable = (1U << 5U), /* test mode interrupt */ + kRTC_FlashSecurityInterruptEnable = (1U << 6U), /* flash security interrupt */ +#if (defined(FSL_FEATURE_RTC_HAS_TIR_TPIE) && FSL_FEATURE_RTC_HAS_TIR_TPIE) + kRTC_TamperPinInterruptEnable = (1U << 7U), /* Tamper pin interrupt */ +#endif /* FSL_FEATURE_RTC_HAS_TIR_TPIE */ +#if (defined(FSL_FEATURE_RTC_HAS_TIR_SIE) && FSL_FEATURE_RTC_HAS_TIR_SIE) + kRTC_SecurityModuleInterruptEnable = (1U << 8U), /* security module interrupt */ +#endif /* FSL_FEATURE_RTC_HAS_TIR_SIE */ +#if (defined(FSL_FEATURE_RTC_HAS_TIR_LCIE) && FSL_FEATURE_RTC_HAS_TIR_LCIE) + kRTC_LossOfClockInterruptEnable = (1U << 9U), /* loss of clock interrupt */ +#endif /* FSL_FEATURE_RTC_HAS_TIR_LCIE */ +#endif /* FSL_FEATURE_RTC_HAS_TIR */ } rtc_interrupt_enable_t; /*! @brief List of RTC flags */ typedef enum _rtc_status_flags { - kRTC_TimeInvalidFlag = RTC_SR_TIF_MASK, /*!< Time invalid flag */ - kRTC_TimeOverflowFlag = RTC_SR_TOF_MASK, /*!< Time overflow flag */ - kRTC_AlarmFlag = RTC_SR_TAF_MASK /*!< Alarm flag*/ + kRTC_TimeInvalidFlag = (1U << 0U), /*!< Time invalid flag */ + kRTC_TimeOverflowFlag = (1U << 1U), /*!< Time overflow flag */ + kRTC_AlarmFlag = (1U << 2U), /*!< Alarm flag*/ +#if defined(FSL_FEATURE_RTC_HAS_MONOTONIC) && (FSL_FEATURE_RTC_HAS_MONOTONIC) + kRTC_MonotonicOverflowFlag = (1U << 3U), /*!< Monotonic Overflow Flag */ +#endif /* FSL_FEATURE_RTC_HAS_MONOTONIC */ +#if (defined(FSL_FEATURE_RTC_HAS_SR_TIDF) && FSL_FEATURE_RTC_HAS_SR_TIDF) + kRTC_TamperInterruptDetectFlag = (1U << 4U), /*!< Tamper interrupt detect flag */ +#endif /* FSL_FEATURE_RTC_HAS_SR_TIDF */ +#if (defined(FSL_FEATURE_RTC_HAS_TDR) && FSL_FEATURE_RTC_HAS_TDR) + kRTC_TestModeFlag = (1U << 5U), /* Test mode flag */ + kRTC_FlashSecurityFlag = (1U << 6U), /* Flash security flag */ +#if (defined(FSL_FEATURE_RTC_HAS_TDR_TPF) && FSL_FEATURE_RTC_HAS_TDR_TPF) + kRTC_TamperPinFlag = (1U << 7U), /* Tamper pin flag */ +#endif /* FSL_FEATURE_RTC_HAS_TDR_TPF */ +#if (defined(FSL_FEATURE_RTC_HAS_TDR_STF) && FSL_FEATURE_RTC_HAS_TDR_STF) + kRTC_SecurityTamperFlag = (1U << 8U), /* Security tamper flag */ +#endif /* FSL_FEATURE_RTC_HAS_TDR_STF */ +#if (defined(FSL_FEATURE_RTC_HAS_TDR_LCTF) && FSL_FEATURE_RTC_HAS_TDR_LCTF) + kRTC_LossOfClockTamperFlag = (1U << 9U), /* Loss of clock flag */ +#endif /* FSL_FEATURE_RTC_HAS_TDR_LCTF */ +#endif /* FSL_FEATURE_RTC_HAS_TDR */ } rtc_status_flags_t; #if (defined(FSL_FEATURE_RTC_HAS_OSC_SCXP) && FSL_FEATURE_RTC_HAS_OSC_SCXP) @@ -88,6 +100,27 @@ typedef struct _rtc_datetime uint8_t second; /*!< Range from 0 to 59.*/ } rtc_datetime_t; +#if (defined(FSL_FEATURE_RTC_HAS_PCR) && FSL_FEATURE_RTC_HAS_PCR) + +/*! + * @brief RTC pin config structure + */ +typedef struct _rtc_pin_config +{ + bool inputLogic; /*!< true: Tamper pin input data is logic one. + false: Tamper pin input data is logic zero. */ + bool pinActiveLow; /*!< true: Tamper pin is active low. + false: Tamper pin is active high. */ + bool filterEnable; /*!< true: Input filter is enabled on the tamper pin. + false: Input filter is disabled on the tamper pin. */ + bool pullSelectNegate; /*!< true: Tamper pin pull resistor direction will negate the tamper pin. + false: Tamper pin pull resistor direction will assert the tamper pin. */ + bool pullEnable; /*!< true: Pull resistor is enabled on tamper pin. + false: Pull resistor is disabled on tamper pin. */ +} rtc_pin_config_t; + +#endif /* FSL_FEATURE_RTC_HAS_PCR */ + /*! * @brief RTC config structure * @@ -144,10 +177,12 @@ static inline void RTC_Deinit(RTC_Type *base) /* Stop the RTC timer */ base->SR &= ~RTC_SR_TCE_MASK; +#if defined(RTC_CLOCKS) #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) /* Gate the module clock */ CLOCK_DisableClock(kCLOCK_Rtc0); #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +#endif /* RTC_CLOCKS */ } /*! @@ -231,10 +266,7 @@ void RTC_GetAlarm(RTC_Type *base, rtc_datetime_t *datetime); * @param mask The interrupts to enable. This is a logical OR of members of the * enumeration ::rtc_interrupt_enable_t */ -static inline void RTC_EnableInterrupts(RTC_Type *base, uint32_t mask) -{ - base->IER |= mask; -} +void RTC_EnableInterrupts(RTC_Type *base, uint32_t mask); /*! * @brief Disables the selected RTC interrupts. @@ -243,10 +275,7 @@ static inline void RTC_EnableInterrupts(RTC_Type *base, uint32_t mask) * @param mask The interrupts to enable. This is a logical OR of members of the * enumeration ::rtc_interrupt_enable_t */ -static inline void RTC_DisableInterrupts(RTC_Type *base, uint32_t mask) -{ - base->IER &= ~mask; -} +void RTC_DisableInterrupts(RTC_Type *base, uint32_t mask); /*! * @brief Gets the enabled RTC interrupts. @@ -256,10 +285,7 @@ static inline void RTC_DisableInterrupts(RTC_Type *base, uint32_t mask) * @return The enabled interrupts. This is the logical OR of members of the * enumeration ::rtc_interrupt_enable_t */ -static inline uint32_t RTC_GetEnabledInterrupts(RTC_Type *base) -{ - return (base->IER & (RTC_IER_TIIE_MASK | RTC_IER_TOIE_MASK | RTC_IER_TAIE_MASK | RTC_IER_TSIE_MASK)); -} +uint32_t RTC_GetEnabledInterrupts(RTC_Type *base); /*! @}*/ @@ -276,10 +302,7 @@ static inline uint32_t RTC_GetEnabledInterrupts(RTC_Type *base) * @return The status flags. This is the logical OR of members of the * enumeration ::rtc_status_flags_t */ -static inline uint32_t RTC_GetStatusFlags(RTC_Type *base) -{ - return (base->SR & (RTC_SR_TIF_MASK | RTC_SR_TOF_MASK | RTC_SR_TAF_MASK)); -} +uint32_t RTC_GetStatusFlags(RTC_Type *base); /*! * @brief Clears the RTC status flags. @@ -292,6 +315,36 @@ void RTC_ClearStatusFlags(RTC_Type *base, uint32_t mask); /*! @}*/ +#if !(defined(FSL_FEATURE_RTC_HAS_NO_CR_OSCE) && FSL_FEATURE_RTC_HAS_NO_CR_OSCE) +/*! + * @brief Set RTC clock source. + * + * @param base RTC peripheral base address + * + * @note After setting this bit, wait the oscillator startup time before enabling + * the time counter to allow the 32.768 kHz clock time to stabilize. + */ +static inline void RTC_SetClockSource(RTC_Type *base) +{ + /* Enable the RTC 32KHz oscillator */ + base->CR |= RTC_CR_OSCE_MASK; +} +#endif /* FSL_FEATURE_RTC_HAS_NO_CR_OSCE */ + +#if (defined(FSL_FEATURE_RTC_HAS_TTSR) && FSL_FEATURE_RTC_HAS_TTSR) + +/*! + * @brief Get the RTC tamper time seconds. + * + * @param base RTC peripheral base address + */ +static inline uint32_t RTC_GetTamperTimeSeconds(RTC_Type *base) +{ + return base->TTSR; +} + +#endif /* FSL_FEATURE_RTC_HAS_TTSR */ + /*! * @name Timer Start and Stop * @{ @@ -380,7 +433,7 @@ void RTC_GetMonotonicCounter(RTC_Type *base, uint64_t *counter); /*! * @brief Writes values Monotonic Counter High and Monotonic Counter Low by decomposing - * the given single value. + * the given single value. The Monotonic Overflow Flag in RTC_SR is cleared due to the API. * * @param base RTC peripheral base address * @param counter Counter value diff --git a/ext/hal/nxp/mcux/drivers/kinetis/fsl_sai.c b/ext/hal/nxp/mcux/drivers/kinetis/fsl_sai.c index 31fd061e4c2..19cd7e49893 100644 --- a/ext/hal/nxp/mcux/drivers/kinetis/fsl_sai.c +++ b/ext/hal/nxp/mcux/drivers/kinetis/fsl_sai.c @@ -1,35 +1,18 @@ /* * Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP + * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * SPDX-License-Identifier: BSD-3-Clause */ #include "fsl_sai.h" +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.sai" +#endif + /******************************************************************************* * Definitations ******************************************************************************/ @@ -69,36 +52,52 @@ static void SAI_SetMasterClockDivider(I2S_Type *base, uint32_t mclk_Hz, uint32_t * * @param base SAI base pointer. */ -uint32_t SAI_GetInstance(I2S_Type *base); +static uint32_t SAI_GetInstance(I2S_Type *base); /*! * @brief sends a piece of data in non-blocking way. * * @param base SAI base pointer - * @param channel Data channel used. + * @param channel start channel number. + * @param channelMask enabled channels mask. + * @param endChannel end channel numbers. * @param bitWidth How many bits in a audio word, usually 8/16/24/32 bits. * @param buffer Pointer to the data to be written. * @param size Bytes to be written. */ -static void SAI_WriteNonBlocking(I2S_Type *base, uint32_t channel, uint32_t bitWidth, uint8_t *buffer, uint32_t size); +static void SAI_WriteNonBlocking(I2S_Type *base, + uint32_t channel, + uint32_t channelMask, + uint32_t endChannel, + uint32_t bitWidth, + uint8_t *buffer, + uint32_t size); /*! * @brief Receive a piece of data in non-blocking way. * * @param base SAI base pointer - * @param channel Data channel used. + * @param channel start channel number. + * @param channelMask enabled channels mask. + * @param endChannel end channel numbers. * @param bitWidth How many bits in a audio word, usually 8/16/24/32 bits. * @param buffer Pointer to the data to be read. * @param size Bytes to be read. */ -static void SAI_ReadNonBlocking(I2S_Type *base, uint32_t channel, uint32_t bitWidth, uint8_t *buffer, uint32_t size); +static void SAI_ReadNonBlocking(I2S_Type *base, + uint32_t channel, + uint32_t channelMask, + uint32_t endChannel, + uint32_t bitWidth, + uint8_t *buffer, + uint32_t size); /******************************************************************************* * Variables ******************************************************************************/ /* Base pointer array */ static I2S_Type *const s_saiBases[] = I2S_BASE_PTRS; /*!@brief SAI handle pointer */ -sai_handle_t *s_saiHandle[ARRAY_SIZE(s_saiBases)][2]; +static sai_handle_t *s_saiHandle[ARRAY_SIZE(s_saiBases)][2]; /* IRQ number array */ static const IRQn_Type s_saiTxIRQ[] = I2S_TX_IRQS; static const IRQn_Type s_saiRxIRQ[] = I2S_RX_IRQS; @@ -178,7 +177,7 @@ static void SAI_SetMasterClockDivider(I2S_Type *base, uint32_t mclk_Hz, uint32_t } #endif /* FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER */ -uint32_t SAI_GetInstance(I2S_Type *base) +static uint32_t SAI_GetInstance(I2S_Type *base) { uint32_t instance; @@ -196,45 +195,83 @@ uint32_t SAI_GetInstance(I2S_Type *base) return instance; } -static void SAI_WriteNonBlocking(I2S_Type *base, uint32_t channel, uint32_t bitWidth, uint8_t *buffer, uint32_t size) +static void SAI_WriteNonBlocking(I2S_Type *base, + uint32_t channel, + uint32_t channelMask, + uint32_t endChannel, + uint32_t bitWidth, + uint8_t *buffer, + uint32_t size) { uint32_t i = 0; - uint8_t j = 0; + uint8_t j = 0, m = 0; uint8_t bytesPerWord = bitWidth / 8U; uint32_t data = 0; uint32_t temp = 0; for (i = 0; i < size / bytesPerWord; i++) { - for (j = 0; j < bytesPerWord; j++) + for (j = channel; j <= endChannel; j++) { - temp = (uint32_t)(*buffer); - data |= (temp << (8U * j)); - buffer++; + if ((1U << j) & channelMask) + { + for (m = 0; m < bytesPerWord; m++) + { + temp = (uint32_t)(*buffer); + data |= (temp << (8U * m)); + buffer++; + } + base->TDR[j] = data; + data = 0; + } } - base->TDR[channel] = data; - data = 0; } } -static void SAI_ReadNonBlocking(I2S_Type *base, uint32_t channel, uint32_t bitWidth, uint8_t *buffer, uint32_t size) +static void SAI_ReadNonBlocking(I2S_Type *base, + uint32_t channel, + uint32_t channelMask, + uint32_t endChannel, + uint32_t bitWidth, + uint8_t *buffer, + uint32_t size) { uint32_t i = 0; - uint8_t j = 0; + uint8_t j = 0, m = 0; uint8_t bytesPerWord = bitWidth / 8U; uint32_t data = 0; for (i = 0; i < size / bytesPerWord; i++) { - data = base->RDR[channel]; - for (j = 0; j < bytesPerWord; j++) + for (j = channel; j <= endChannel; j++) { - *buffer = (data >> (8U * j)) & 0xFF; - buffer++; + if ((1U << j) & channelMask) + { + data = base->RDR[j]; + for (m = 0; m < bytesPerWord; m++) + { + *buffer = (data >> (8U * m)) & 0xFF; + buffer++; + } + } } } } +/*! + * brief Initializes the SAI Tx peripheral. + * + * Ungates the SAI clock, resets the module, and configures SAI Tx with a configuration structure. + * The configuration structure can be custom filled or set with default values by + * SAI_TxGetDefaultConfig(). + * + * note This API should be called at the beginning of the application to use + * the SAI driver. Otherwise, accessing the SAIM module can cause a hard fault + * because the clock is not enabled. + * + * param base SAI base pointer + * param config SAI configuration structure. +*/ void SAI_TxInit(I2S_Type *base, const sai_config_t *config) { uint32_t val = 0; @@ -245,15 +282,19 @@ void SAI_TxInit(I2S_Type *base, const sai_config_t *config) #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ #if defined(FSL_FEATURE_SAI_HAS_MCR) && (FSL_FEATURE_SAI_HAS_MCR) +#if !(defined(FSL_FEATURE_SAI_HAS_NO_MCR_MICS) && (FSL_FEATURE_SAI_HAS_NO_MCR_MICS)) /* Master clock source setting */ val = (base->MCR & ~I2S_MCR_MICS_MASK); base->MCR = (val | I2S_MCR_MICS(config->mclkSource)); +#endif /* Configure Master clock output enable */ val = (base->MCR & ~I2S_MCR_MOE_MASK); base->MCR = (val | I2S_MCR_MOE(config->mclkOutputEnable)); #endif /* FSL_FEATURE_SAI_HAS_MCR */ + SAI_TxReset(base); + /* Configure audio protocol */ switch (config->protocol) { @@ -337,8 +378,26 @@ void SAI_TxInit(I2S_Type *base, const sai_config_t *config) default: break; } + +#if defined(FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR) && FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR + SAI_TxSetFIFOErrorContinue(base, true); +#endif /* FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR */ } +/*! + * brief Initializes the SAI Rx peripheral. + * + * Ungates the SAI clock, resets the module, and configures the SAI Rx with a configuration structure. + * The configuration structure can be custom filled or set with default values by + * SAI_RxGetDefaultConfig(). + * + * note This API should be called at the beginning of the application to use + * the SAI driver. Otherwise, accessing the SAI module can cause a hard fault + * because the clock is not enabled. + * + * param base SAI base pointer + * param config SAI configuration structure. + */ void SAI_RxInit(I2S_Type *base, const sai_config_t *config) { uint32_t val = 0; @@ -349,15 +408,19 @@ void SAI_RxInit(I2S_Type *base, const sai_config_t *config) #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ #if defined(FSL_FEATURE_SAI_HAS_MCR) && (FSL_FEATURE_SAI_HAS_MCR) +#if !(defined(FSL_FEATURE_SAI_HAS_NO_MCR_MICS) && (FSL_FEATURE_SAI_HAS_NO_MCR_MICS)) /* Master clock source setting */ val = (base->MCR & ~I2S_MCR_MICS_MASK); base->MCR = (val | I2S_MCR_MICS(config->mclkSource)); +#endif /* Configure Master clock output enable */ val = (base->MCR & ~I2S_MCR_MOE_MASK); base->MCR = (val | I2S_MCR_MOE(config->mclkOutputEnable)); #endif /* FSL_FEATURE_SAI_HAS_MCR */ + SAI_RxReset(base); + /* Configure audio protocol */ switch (config->protocol) { @@ -441,8 +504,20 @@ void SAI_RxInit(I2S_Type *base, const sai_config_t *config) default: break; } + +#if defined(FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR) && FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR + SAI_RxSetFIFOErrorContinue(base, true); +#endif /* FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR */ } +/*! + * brief De-initializes the SAI peripheral. + * + * This API gates the SAI clock. The SAI module can't operate unless SAI_TxInit + * or SAI_RxInit is called to enable the clock. + * + * param base SAI base pointer +*/ void SAI_Deinit(I2S_Type *base) { SAI_TxEnable(base, false); @@ -452,30 +527,75 @@ void SAI_Deinit(I2S_Type *base) #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ } +/*! + * brief Sets the SAI Tx configuration structure to default values. + * + * This API initializes the configuration structure for use in SAI_TxConfig(). + * The initialized structure can remain unchanged in SAI_TxConfig(), or it can be modified + * before calling SAI_TxConfig(). + * This is an example. + code + sai_config_t config; + SAI_TxGetDefaultConfig(&config); + endcode + * + * param config pointer to master configuration structure + */ void SAI_TxGetDefaultConfig(sai_config_t *config) { + /* Initializes the configure structure to zero. */ + memset(config, 0, sizeof(*config)); + config->bclkSource = kSAI_BclkSourceMclkDiv; config->masterSlave = kSAI_Master; - config->mclkSource = kSAI_MclkSourceSysclk; - config->protocol = kSAI_BusLeftJustified; - config->syncMode = kSAI_ModeAsync; #if defined(FSL_FEATURE_SAI_HAS_MCR) && (FSL_FEATURE_SAI_HAS_MCR) config->mclkOutputEnable = true; +#if !(defined(FSL_FEATURE_SAI_HAS_NO_MCR_MICS) && (FSL_FEATURE_SAI_HAS_NO_MCR_MICS)) + config->mclkSource = kSAI_MclkSourceSysclk; +#endif #endif /* FSL_FEATURE_SAI_HAS_MCR */ + config->protocol = kSAI_BusI2S; + config->syncMode = kSAI_ModeAsync; } +/*! + * brief Sets the SAI Rx configuration structure to default values. + * + * This API initializes the configuration structure for use in SAI_RxConfig(). + * The initialized structure can remain unchanged in SAI_RxConfig() or it can be modified + * before calling SAI_RxConfig(). + * This is an example. + code + sai_config_t config; + SAI_RxGetDefaultConfig(&config); + endcode + * + * param config pointer to master configuration structure + */ void SAI_RxGetDefaultConfig(sai_config_t *config) { + /* Initializes the configure structure to zero. */ + memset(config, 0, sizeof(*config)); + config->bclkSource = kSAI_BclkSourceMclkDiv; config->masterSlave = kSAI_Master; - config->mclkSource = kSAI_MclkSourceSysclk; - config->protocol = kSAI_BusLeftJustified; - config->syncMode = kSAI_ModeSync; #if defined(FSL_FEATURE_SAI_HAS_MCR) && (FSL_FEATURE_SAI_HAS_MCR) config->mclkOutputEnable = true; +#if !(defined(FSL_FEATURE_SAI_HAS_NO_MCR_MICS) && (FSL_FEATURE_SAI_HAS_NO_MCR_MICS)) + config->mclkSource = kSAI_MclkSourceSysclk; +#endif #endif /* FSL_FEATURE_SAI_HAS_MCR */ + config->protocol = kSAI_BusI2S; + config->syncMode = kSAI_ModeSync; } +/*! + * brief Resets the SAI Tx. + * + * This function enables the software reset and FIFO reset of SAI Tx. After reset, clear the reset bit. + * + * param base SAI base pointer + */ void SAI_TxReset(I2S_Type *base) { /* Set the software reset and FIFO reset to clear internal state */ @@ -492,6 +612,13 @@ void SAI_TxReset(I2S_Type *base) base->TMR = 0; } +/*! + * brief Resets the SAI Rx. + * + * This function enables the software reset and FIFO reset of SAI Rx. After reset, clear the reset bit. + * + * param base SAI base pointer + */ void SAI_RxReset(I2S_Type *base) { /* Set the software reset and FIFO reset to clear internal state */ @@ -508,6 +635,12 @@ void SAI_RxReset(I2S_Type *base) base->RMR = 0; } +/*! + * brief Enables/disables the SAI Tx. + * + * param base SAI base pointer + * param enable True means enable SAI Tx, false means disable. + */ void SAI_TxEnable(I2S_Type *base, bool enable) { if (enable) @@ -532,6 +665,12 @@ void SAI_TxEnable(I2S_Type *base, bool enable) } } +/*! + * brief Enables/disables the SAI Rx. + * + * param base SAI base pointer + * param enable True means enable SAI Rx, false means disable. + */ void SAI_RxEnable(I2S_Type *base, bool enable) { if (enable) @@ -555,6 +694,17 @@ void SAI_RxEnable(I2S_Type *base, bool enable) } } +/*! + * brief Do software reset or FIFO reset . + * + * FIFO reset means clear all the data in the FIFO, and make the FIFO pointer both to 0. + * Software reset means claer the Tx internal logic, including the bit clock, frame count etc. But software + * reset will not clear any configuration registers like TCR1~TCR5. + * This function will also clear all the error flags such as FIFO error, sync error etc. + * + * param base SAI base pointer + * param type Reset type, FIFO reset or software reset + */ void SAI_TxSoftwareReset(I2S_Type *base, sai_reset_type_t type) { base->TCSR |= (uint32_t)type; @@ -563,6 +713,17 @@ void SAI_TxSoftwareReset(I2S_Type *base, sai_reset_type_t type) base->TCSR &= ~I2S_TCSR_SR_MASK; } +/*! + * brief Do software reset or FIFO reset . + * + * FIFO reset means clear all the data in the FIFO, and make the FIFO pointer both to 0. + * Software reset means claer the Rx internal logic, including the bit clock, frame count etc. But software + * reset will not clear any configuration registers like RCR1~RCR5. + * This function will also clear all the error flags such as FIFO error, sync error etc. + * + * param base SAI base pointer + * param type Reset type, FIFO reset or software reset + */ void SAI_RxSoftwareReset(I2S_Type *base, sai_reset_type_t type) { base->RCSR |= (uint32_t)type; @@ -571,18 +732,160 @@ void SAI_RxSoftwareReset(I2S_Type *base, sai_reset_type_t type) base->RCSR &= ~I2S_RCSR_SR_MASK; } +/*! + * brief Set the Tx channel FIFO enable mask. + * + * param base SAI base pointer + * param mask Channel enable mask, 0 means all channel FIFO disabled, 1 means channel 0 enabled, + * 3 means both channel 0 and channel 1 enabled. + */ void SAI_TxSetChannelFIFOMask(I2S_Type *base, uint8_t mask) { base->TCR3 &= ~I2S_TCR3_TCE_MASK; base->TCR3 |= I2S_TCR3_TCE(mask); } +/*! + * brief Set the Rx channel FIFO enable mask. + * + * param base SAI base pointer + * param mask Channel enable mask, 0 means all channel FIFO disabled, 1 means channel 0 enabled, + * 3 means both channel 0 and channel 1 enabled. + */ void SAI_RxSetChannelFIFOMask(I2S_Type *base, uint8_t mask) { base->RCR3 &= ~I2S_RCR3_RCE_MASK; base->RCR3 |= I2S_RCR3_RCE(mask); } +/*! + * brief Set the Tx data order. + * + * param base SAI base pointer + * param order Data order MSB or LSB + */ +void SAI_TxSetDataOrder(I2S_Type *base, sai_data_order_t order) +{ + uint32_t val = (base->TCR4) & (~I2S_TCR4_MF_MASK); + + val |= I2S_TCR4_MF(order); + base->TCR4 = val; +} + +/*! + * brief Set the Rx data order. + * + * param base SAI base pointer + * param order Data order MSB or LSB + */ +void SAI_RxSetDataOrder(I2S_Type *base, sai_data_order_t order) +{ + uint32_t val = (base->RCR4) & (~I2S_RCR4_MF_MASK); + + val |= I2S_RCR4_MF(order); + base->RCR4 = val; +} + +/*! + * brief Set the Tx data order. + * + * param base SAI base pointer + * param order Data order MSB or LSB + */ +void SAI_TxSetBitClockPolarity(I2S_Type *base, sai_clock_polarity_t polarity) +{ + uint32_t val = (base->TCR2) & (~I2S_TCR2_BCP_MASK); + + val |= I2S_TCR2_BCP(polarity); + base->TCR2 = val; +} + +/*! + * brief Set the Rx data order. + * + * param base SAI base pointer + * param order Data order MSB or LSB + */ +void SAI_RxSetBitClockPolarity(I2S_Type *base, sai_clock_polarity_t polarity) +{ + uint32_t val = (base->RCR2) & (~I2S_RCR2_BCP_MASK); + + val |= I2S_RCR2_BCP(polarity); + base->RCR2 = val; +} + +/*! + * brief Set the Tx data order. + * + * param base SAI base pointer + * param order Data order MSB or LSB + */ +void SAI_TxSetFrameSyncPolarity(I2S_Type *base, sai_clock_polarity_t polarity) +{ + uint32_t val = (base->TCR4) & (~I2S_TCR4_FSP_MASK); + + val |= I2S_TCR4_FSP(polarity); + base->TCR4 = val; +} + +/*! + * brief Set the Rx data order. + * + * param base SAI base pointer + * param order Data order MSB or LSB + */ +void SAI_RxSetFrameSyncPolarity(I2S_Type *base, sai_clock_polarity_t polarity) +{ + uint32_t val = (base->RCR4) & (~I2S_RCR4_FSP_MASK); + + val |= I2S_RCR4_FSP(polarity); + base->RCR4 = val; +} + +#if defined(FSL_FEATURE_SAI_HAS_FIFO_PACKING) && FSL_FEATURE_SAI_HAS_FIFO_PACKING +/*! + * brief Set Tx FIFO packing feature. + * + * param base SAI base pointer. + * param pack FIFO pack type. It is element of sai_fifo_packing_t. + */ +void SAI_TxSetFIFOPacking(I2S_Type *base, sai_fifo_packing_t pack) +{ + uint32_t val = base->TCR4; + + val &= ~I2S_TCR4_FPACK_MASK; + val |= I2S_TCR4_FPACK(pack); + base->TCR4 = val; +} + +/*! +* brief Set Rx FIFO packing feature. +* +* param base SAI base pointer. +* param pack FIFO pack type. It is element of sai_fifo_packing_t. +*/ +void SAI_RxSetFIFOPacking(I2S_Type *base, sai_fifo_packing_t pack) +{ + uint32_t val = base->RCR4; + + val &= ~I2S_RCR4_FPACK_MASK; + val |= I2S_RCR4_FPACK(pack); + base->RCR4 = val; +} +#endif /* FSL_FEATURE_SAI_HAS_FIFO_PACKING */ + +/*! + * brief Configures the SAI Tx audio format. + * + * The audio format can be changed at run-time. This function configures the sample rate and audio data + * format to be transferred. + * + * param base SAI base pointer. + * param format Pointer to the SAI audio data format structure. + * param mclkSourceClockHz SAI master clock source frequency in Hz. + * param bclkSourceClockHz SAI bit clock source frequency in Hz. If the bit clock source is a master + * clock, this value should equal the masterClockHz. +*/ void SAI_TxSetFormat(I2S_Type *base, sai_transfer_format_t *format, uint32_t mclkSourceClockHz, @@ -590,16 +893,12 @@ void SAI_TxSetFormat(I2S_Type *base, { uint32_t bclk = 0; uint32_t val = 0; - uint32_t channels = 2U; - - if (format->stereo != kSAI_Stereo) - { - channels = 1U; - } + uint32_t i = 0U; + uint32_t divider = 0U, channelNums = 0U; if (format->isFrameSyncCompact) { - bclk = format->sampleRate_Hz * format->bitWidth * channels; + bclk = format->sampleRate_Hz * format->bitWidth * (format->stereo == kSAI_Stereo ? 2U : 1U); val = (base->TCR4 & (~I2S_TCR4_SYWD_MASK)); val |= I2S_TCR4_SYWD(format->bitWidth - 1U); base->TCR4 = val; @@ -622,7 +921,30 @@ void SAI_TxSetFormat(I2S_Type *base, if (base->TCR2 & I2S_TCR2_BCD_MASK) { base->TCR2 &= ~I2S_TCR2_DIV_MASK; - base->TCR2 |= I2S_TCR2_DIV((bclkSourceClockHz / bclk) / 2U - 1U); + /* need to check the divided bclk, if bigger than target, then divider need to re-calculate. */ + divider = bclkSourceClockHz / bclk; + /* for the condition where the source clock is smaller than target bclk */ + if (divider == 0U) + { + divider++; + } + /* recheck the divider if properly or not, to make sure output blck not bigger than target*/ + if ((bclkSourceClockHz / divider) > bclk) + { + divider++; + } + +#if defined(FSL_FEATURE_SAI_HAS_BCLK_BYPASS) && (FSL_FEATURE_SAI_HAS_BCLK_BYPASS) + /* if bclk same with MCLK, bypass the divider */ + if (divider == 1U) + { + base->TCR2 |= I2S_TCR2_BYP_MASK; + } + else +#endif + { + base->TCR2 |= I2S_TCR2_DIV(divider / 2U - 1U); + } } /* Set bitWidth */ @@ -633,15 +955,54 @@ void SAI_TxSetFormat(I2S_Type *base, } else { - base->TCR5 = I2S_TCR5_WNW(val) | I2S_TCR5_W0W(val) | I2S_TCR5_FBT(format->bitWidth - 1); + if (base->TCR4 & I2S_TCR4_MF_MASK) + { + base->TCR5 = I2S_TCR5_WNW(val) | I2S_TCR5_W0W(val) | I2S_TCR5_FBT(format->bitWidth - 1); + } + else + { + base->TCR5 = I2S_TCR5_WNW(val) | I2S_TCR5_W0W(val) | I2S_TCR5_FBT(0); + } } /* Set mono or stereo */ base->TMR = (uint32_t)format->stereo; + /* if channel mask is not set, then format->channel must be set, + use it to get channel mask value */ + if (format->channelMask == 0U) + { + format->channelMask = 1U << format->channel; + } + + /* if channel nums is not set, calculate it here according to channelMask*/ + for (i = 0U; i < FSL_FEATURE_SAI_CHANNEL_COUNT; i++) + { + if (((uint32_t)1 << i) & format->channelMask) + { + /* geet start channel number when channelNums = 0 only */ + if (channelNums == 0U) + { + format->channel = i; + } + channelNums++; + format->endChannel = i; + } + } + format->channelNums = channelNums; + assert(format->channelNums <= FSL_FEATURE_SAI_CHANNEL_COUNT); + +#if defined(FSL_FEATURE_SAI_HAS_FIFO_COMBINE_MODE) && (FSL_FEATURE_SAI_HAS_FIFO_COMBINE_MODE) + /* make sure combine mode disabled while multipe channel is used */ + if (format->channelNums > 1U) + { + base->TCR4 &= ~I2S_TCR4_FCOMB_MASK; + } +#endif + /* Set data channel */ base->TCR3 &= ~I2S_TCR3_TCE_MASK; - base->TCR3 |= I2S_TCR3_TCE(1U << format->channel); + base->TCR3 |= I2S_TCR3_TCE(format->channelMask); #if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) /* Set watermark */ @@ -649,6 +1010,18 @@ void SAI_TxSetFormat(I2S_Type *base, #endif /* FSL_FEATURE_SAI_FIFO_COUNT */ } +/*! + * brief Configures the SAI Rx audio format. + * + * The audio format can be changed at run-time. This function configures the sample rate and audio data + * format to be transferred. + * + * param base SAI base pointer. + * param format Pointer to the SAI audio data format structure. + * param mclkSourceClockHz SAI master clock source frequency in Hz. + * param bclkSourceClockHz SAI bit clock source frequency in Hz. If the bit clock source is a master + * clock, this value should equal the masterClockHz. +*/ void SAI_RxSetFormat(I2S_Type *base, sai_transfer_format_t *format, uint32_t mclkSourceClockHz, @@ -656,16 +1029,12 @@ void SAI_RxSetFormat(I2S_Type *base, { uint32_t bclk = 0; uint32_t val = 0; - uint32_t channels = 2U; - - if (format->stereo != kSAI_Stereo) - { - channels = 1U; - } + uint32_t i = 0U; + uint32_t divider = 0U, channelNums = 0U; if (format->isFrameSyncCompact) { - bclk = format->sampleRate_Hz * format->bitWidth * channels; + bclk = format->sampleRate_Hz * format->bitWidth * (format->stereo == kSAI_Stereo ? 2U : 1U); val = (base->RCR4 & (~I2S_RCR4_SYWD_MASK)); val |= I2S_RCR4_SYWD(format->bitWidth - 1U); base->RCR4 = val; @@ -688,7 +1057,29 @@ void SAI_RxSetFormat(I2S_Type *base, if (base->RCR2 & I2S_RCR2_BCD_MASK) { base->RCR2 &= ~I2S_RCR2_DIV_MASK; - base->RCR2 |= I2S_RCR2_DIV((bclkSourceClockHz / bclk) / 2U - 1U); + /* need to check the divided bclk, if bigger than target, then divider need to re-calculate. */ + divider = bclkSourceClockHz / bclk; + /* for the condition where the source clock is smaller than target bclk */ + if (divider == 0U) + { + divider++; + } + /* recheck the divider if properly or not, to make sure output blck not bigger than target*/ + if ((bclkSourceClockHz / divider) > bclk) + { + divider++; + } +#if defined(FSL_FEATURE_SAI_HAS_BCLK_BYPASS) && (FSL_FEATURE_SAI_HAS_BCLK_BYPASS) + /* if bclk same with MCLK, bypass the divider */ + if (divider == 1U) + { + base->RCR2 |= I2S_RCR2_BYP_MASK; + } + else +#endif + { + base->RCR2 |= I2S_RCR2_DIV(divider / 2U - 1U); + } } /* Set bitWidth */ @@ -699,15 +1090,55 @@ void SAI_RxSetFormat(I2S_Type *base, } else { - base->RCR5 = I2S_RCR5_WNW(val) | I2S_RCR5_W0W(val) | I2S_RCR5_FBT(format->bitWidth - 1); + if (base->RCR4 & I2S_RCR4_MF_MASK) + { + base->RCR5 = I2S_RCR5_WNW(val) | I2S_RCR5_W0W(val) | I2S_RCR5_FBT(format->bitWidth - 1); + } + else + { + base->RCR5 = I2S_RCR5_WNW(val) | I2S_RCR5_W0W(val) | I2S_RCR5_FBT(0); + } } /* Set mono or stereo */ base->RMR = (uint32_t)format->stereo; + /* if channel mask is not set, then format->channel must be set, + use it to get channel mask value */ + if (format->channelMask == 0U) + { + format->channelMask = 1U << format->channel; + } + + /* if channel nums is not set, calculate it here according to channelMask*/ + for (i = 0U; i < FSL_FEATURE_SAI_CHANNEL_COUNT; i++) + { + if (((uint32_t)1 << i) & format->channelMask) + { + /* geet start channel number when channelNums = 0 only */ + if (channelNums == 0U) + { + format->channel = i; + } + channelNums++; + format->endChannel = i; + } + } + format->channelNums = channelNums; + assert(format->channelNums <= FSL_FEATURE_SAI_CHANNEL_COUNT); + +#if defined(FSL_FEATURE_SAI_HAS_FIFO_COMBINE_MODE) && (FSL_FEATURE_SAI_HAS_FIFO_COMBINE_MODE) + /* make sure combine mode disabled while multipe channel is used */ + if (format->channelNums > 1U) + { + base->RCR4 &= ~I2S_RCR4_FCOMB_MASK; + } +#endif + /* Set data channel */ base->RCR3 &= ~I2S_RCR3_RCE_MASK; - base->RCR3 |= I2S_RCR3_RCE(1U << format->channel); + /* enable all the channel */ + base->RCR3 |= I2S_RCR3_RCE(format->channelMask); #if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) /* Set watermark */ @@ -715,10 +1146,24 @@ void SAI_RxSetFormat(I2S_Type *base, #endif /* FSL_FEATURE_SAI_FIFO_COUNT */ } +/*! + * brief Sends data using a blocking method. + * + * note This function blocks by polling until data is ready to be sent. + * + * param base SAI base pointer. + * param channel Data channel used. + * param bitWidth How many bits in an audio word; usually 8/16/24/32 bits. + * param buffer Pointer to the data to be written. + * param size Bytes to be written. + */ void SAI_WriteBlocking(I2S_Type *base, uint32_t channel, uint32_t bitWidth, uint8_t *buffer, uint32_t size) { uint32_t i = 0; uint8_t bytesPerWord = bitWidth / 8U; +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + bytesPerWord = (size_t)((FSL_FEATURE_SAI_FIFO_COUNT - base->TCR1) * bytesPerWord); +#endif while (i < size) { @@ -727,7 +1172,7 @@ void SAI_WriteBlocking(I2S_Type *base, uint32_t channel, uint32_t bitWidth, uint { } - SAI_WriteNonBlocking(base, channel, bitWidth, buffer, bytesPerWord); + SAI_WriteNonBlocking(base, channel, 1U << channel, channel, bitWidth, buffer, bytesPerWord); buffer += bytesPerWord; i += bytesPerWord; } @@ -738,10 +1183,123 @@ void SAI_WriteBlocking(I2S_Type *base, uint32_t channel, uint32_t bitWidth, uint } } +/*! + * brief Sends data to multi channel using a blocking method. + * + * note This function blocks by polling until data is ready to be sent. + * + * param base SAI base pointer. + * param channel Data channel used. + * param channelMask channel mask. + * param bitWidth How many bits in an audio word; usually 8/16/24/32 bits. + * param buffer Pointer to the data to be written. + * param size Bytes to be written. + */ +void SAI_WriteMultiChannelBlocking( + I2S_Type *base, uint32_t channel, uint32_t channelMask, uint32_t bitWidth, uint8_t *buffer, uint32_t size) +{ + uint32_t i = 0, j = 0; + uint8_t bytesPerWord = bitWidth / 8U; + uint32_t channelNums = 0U, endChannel = 0U; + +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + bytesPerWord = (size_t)((FSL_FEATURE_SAI_FIFO_COUNT - base->TCR1) * bytesPerWord); +#endif + + for (i = 0U; (i < FSL_FEATURE_SAI_CHANNEL_COUNT); i++) + { + if ((1U << i) & (channelMask)) + { + channelNums++; + endChannel = i; + } + } + + assert(channelNums <= FSL_FEATURE_SAI_CHANNEL_COUNT); + bytesPerWord *= channelNums; + + while (j < size) + { + /* Wait until it can write data */ + while (!(base->TCSR & I2S_TCSR_FWF_MASK)) + { + } + + SAI_WriteNonBlocking(base, channel, channelMask, endChannel, bitWidth, buffer, bytesPerWord); + buffer += bytesPerWord; + j += bytesPerWord; + } + + /* Wait until the last data is sent */ + while (!(base->TCSR & I2S_TCSR_FWF_MASK)) + { + } +} + +/*! + * brief Receives multi channel data using a blocking method. + * + * note This function blocks by polling until data is ready to be sent. + * + * param base SAI base pointer. + * param channel Data channel used. + * param channelMask channel mask. + * param bitWidth How many bits in an audio word; usually 8/16/24/32 bits. + * param buffer Pointer to the data to be read. + * param size Bytes to be read. + */ +void SAI_ReadMultiChannelBlocking( + I2S_Type *base, uint32_t channel, uint32_t channelMask, uint32_t bitWidth, uint8_t *buffer, uint32_t size) +{ + uint32_t i = 0, j = 0; + uint8_t bytesPerWord = bitWidth / 8U; + uint32_t channelNums = 0U, endChannel = 0U; +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + bytesPerWord = (size_t)(base->RCR1 * bytesPerWord); +#endif + for (i = 0U; (i < FSL_FEATURE_SAI_CHANNEL_COUNT); i++) + { + if ((1U << i) & (channelMask)) + { + channelNums++; + endChannel = i; + } + } + + assert(channelNums <= FSL_FEATURE_SAI_CHANNEL_COUNT); + bytesPerWord *= channelNums; + + while (j < size) + { + /* Wait until data is received */ + while (!(base->RCSR & I2S_RCSR_FWF_MASK)) + { + } + + SAI_ReadNonBlocking(base, channel, channelMask, endChannel, bitWidth, buffer, bytesPerWord); + buffer += bytesPerWord; + j += bytesPerWord; + } +} + +/*! + * brief Receives data using a blocking method. + * + * note This function blocks by polling until data is ready to be sent. + * + * param base SAI base pointer. + * param channel Data channel used. + * param bitWidth How many bits in an audio word; usually 8/16/24/32 bits. + * param buffer Pointer to the data to be read. + * param size Bytes to be read. + */ void SAI_ReadBlocking(I2S_Type *base, uint32_t channel, uint32_t bitWidth, uint8_t *buffer, uint32_t size) { uint32_t i = 0; uint8_t bytesPerWord = bitWidth / 8U; +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + bytesPerWord = (size_t)(base->RCR1 * bytesPerWord); +#endif while (i < size) { @@ -750,12 +1308,23 @@ void SAI_ReadBlocking(I2S_Type *base, uint32_t channel, uint32_t bitWidth, uint8 { } - SAI_ReadNonBlocking(base, channel, bitWidth, buffer, bytesPerWord); + SAI_ReadNonBlocking(base, channel, 1U << channel, channel, bitWidth, buffer, bytesPerWord); buffer += bytesPerWord; i += bytesPerWord; } } +/*! + * brief Initializes the SAI Tx handle. + * + * This function initializes the Tx handle for the SAI Tx transactional APIs. Call + * this function once to get the handle initialized. + * + * param base SAI base pointer + * param handle SAI handle pointer. + * param callback Pointer to the user callback function. + * param userData User parameter passed to the callback function + */ void SAI_TransferTxCreateHandle(I2S_Type *base, sai_handle_t *handle, sai_transfer_callback_t callback, void *userData) { assert(handle); @@ -767,6 +1336,7 @@ void SAI_TransferTxCreateHandle(I2S_Type *base, sai_handle_t *handle, sai_transf handle->callback = callback; handle->userData = userData; + handle->base = base; /* Set the isr pointer */ s_saiTxIsr = SAI_TransferTxHandleIRQ; @@ -775,6 +1345,17 @@ void SAI_TransferTxCreateHandle(I2S_Type *base, sai_handle_t *handle, sai_transf EnableIRQ(s_saiTxIRQ[SAI_GetInstance(base)]); } +/*! + * brief Initializes the SAI Rx handle. + * + * This function initializes the Rx handle for the SAI Rx transactional APIs. Call + * this function once to get the handle initialized. + * + * param base SAI base pointer. + * param handle SAI handle pointer. + * param callback Pointer to the user callback function. + * param userData User parameter passed to the callback function. + */ void SAI_TransferRxCreateHandle(I2S_Type *base, sai_handle_t *handle, sai_transfer_callback_t callback, void *userData) { assert(handle); @@ -786,6 +1367,7 @@ void SAI_TransferRxCreateHandle(I2S_Type *base, sai_handle_t *handle, sai_transf handle->callback = callback; handle->userData = userData; + handle->base = base; /* Set the isr pointer */ s_saiRxIsr = SAI_TransferRxHandleIRQ; @@ -794,6 +1376,20 @@ void SAI_TransferRxCreateHandle(I2S_Type *base, sai_handle_t *handle, sai_transf EnableIRQ(s_saiRxIRQ[SAI_GetInstance(base)]); } +/*! + * brief Configures the SAI Tx audio format. + * + * The audio format can be changed at run-time. This function configures the sample rate and audio data + * format to be transferred. + * + * param base SAI base pointer. + * param handle SAI handle pointer. + * param format Pointer to the SAI audio data format structure. + * param mclkSourceClockHz SAI master clock source frequency in Hz. + * param bclkSourceClockHz SAI bit clock source frequency in Hz. If a bit clock source is a master + * clock, this value should equal the masterClockHz in format. + * return Status of this function. Return value is the status_t. +*/ status_t SAI_TransferTxSetFormat(I2S_Type *base, sai_handle_t *handle, sai_transfer_format_t *format, @@ -802,7 +1398,11 @@ status_t SAI_TransferTxSetFormat(I2S_Type *base, { assert(handle); - if ((mclkSourceClockHz < format->sampleRate_Hz) || (bclkSourceClockHz < format->sampleRate_Hz)) + if ((bclkSourceClockHz < format->sampleRate_Hz) +#if defined(FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER) && (FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER) + || (mclkSourceClockHz < format->sampleRate_Hz) +#endif + ) { return kStatus_InvalidArgument; } @@ -812,13 +1412,32 @@ status_t SAI_TransferTxSetFormat(I2S_Type *base, #if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) handle->watermark = format->watermark; #endif - handle->channel = format->channel; SAI_TxSetFormat(base, format, mclkSourceClockHz, bclkSourceClockHz); + handle->channel = format->channel; + /* used for multi channel */ + handle->channelMask = format->channelMask; + handle->channelNums = format->channelNums; + handle->endChannel = format->endChannel; + return kStatus_Success; } +/*! + * brief Configures the SAI Rx audio format. + * + * The audio format can be changed at run-time. This function configures the sample rate and audio data + * format to be transferred. + * + * param base SAI base pointer. + * param handle SAI handle pointer. + * param format Pointer to the SAI audio data format structure. + * param mclkSourceClockHz SAI master clock source frequency in Hz. + * param bclkSourceClockHz SAI bit clock source frequency in Hz. If a bit clock source is a master + * clock, this value should equal the masterClockHz in format. + * return Status of this function. Return value is one of status_t. +*/ status_t SAI_TransferRxSetFormat(I2S_Type *base, sai_handle_t *handle, sai_transfer_format_t *format, @@ -827,7 +1446,11 @@ status_t SAI_TransferRxSetFormat(I2S_Type *base, { assert(handle); - if ((mclkSourceClockHz < format->sampleRate_Hz) || (bclkSourceClockHz < format->sampleRate_Hz)) + if ((bclkSourceClockHz < format->sampleRate_Hz) +#if defined(FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER) && (FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER) + || (mclkSourceClockHz < format->sampleRate_Hz) +#endif + ) { return kStatus_InvalidArgument; } @@ -837,13 +1460,33 @@ status_t SAI_TransferRxSetFormat(I2S_Type *base, #if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) handle->watermark = format->watermark; #endif - handle->channel = format->channel; SAI_RxSetFormat(base, format, mclkSourceClockHz, bclkSourceClockHz); + handle->channel = format->channel; + /* used for multi channel */ + handle->channelMask = format->channelMask; + handle->channelNums = format->channelNums; + handle->endChannel = format->endChannel; + return kStatus_Success; } +/*! + * brief Performs an interrupt non-blocking send transfer on SAI. + * + * note This API returns immediately after the transfer initiates. + * Call the SAI_TxGetTransferStatusIRQ to poll the transfer status and check whether + * the transfer is finished. If the return status is not kStatus_SAI_Busy, the transfer + * is finished. + * + * param base SAI base pointer. + * param handle Pointer to the sai_handle_t structure which stores the transfer state. + * param xfer Pointer to the sai_transfer_t structure. + * retval kStatus_Success Successfully started the data receive. + * retval kStatus_SAI_TxBusy Previous receive still not finished. + * retval kStatus_InvalidArgument The input parameter is invalid. + */ status_t SAI_TransferSendNonBlocking(I2S_Type *base, sai_handle_t *handle, sai_transfer_t *xfer) { assert(handle); @@ -877,6 +1520,21 @@ status_t SAI_TransferSendNonBlocking(I2S_Type *base, sai_handle_t *handle, sai_t return kStatus_Success; } +/*! + * brief Performs an interrupt non-blocking receive transfer on SAI. + * + * note This API returns immediately after the transfer initiates. + * Call the SAI_RxGetTransferStatusIRQ to poll the transfer status and check whether + * the transfer is finished. If the return status is not kStatus_SAI_Busy, the transfer + * is finished. + * + * param base SAI base pointer + * param handle Pointer to the sai_handle_t structure which stores the transfer state. + * param xfer Pointer to the sai_transfer_t structure. + * retval kStatus_Success Successfully started the data receive. + * retval kStatus_SAI_RxBusy Previous receive still not finished. + * retval kStatus_InvalidArgument The input parameter is invalid. + */ status_t SAI_TransferReceiveNonBlocking(I2S_Type *base, sai_handle_t *handle, sai_transfer_t *xfer) { assert(handle); @@ -910,6 +1568,15 @@ status_t SAI_TransferReceiveNonBlocking(I2S_Type *base, sai_handle_t *handle, sa return kStatus_Success; } +/*! + * brief Gets a set byte count. + * + * param base SAI base pointer. + * param handle Pointer to the sai_handle_t structure which stores the transfer state. + * param count Bytes count sent. + * retval kStatus_Success Succeed get the transfer count. + * retval kStatus_NoTransferInProgress There is not a non-blocking transaction currently in progress. + */ status_t SAI_TransferGetSendCount(I2S_Type *base, sai_handle_t *handle, size_t *count) { assert(handle); @@ -928,6 +1595,15 @@ status_t SAI_TransferGetSendCount(I2S_Type *base, sai_handle_t *handle, size_t * return status; } +/*! + * brief Gets a received byte count. + * + * param base SAI base pointer. + * param handle Pointer to the sai_handle_t structure which stores the transfer state. + * param count Bytes count received. + * retval kStatus_Success Succeed get the transfer count. + * retval kStatus_NoTransferInProgress There is not a non-blocking transaction currently in progress. + */ status_t SAI_TransferGetReceiveCount(I2S_Type *base, sai_handle_t *handle, size_t *count) { assert(handle); @@ -946,6 +1622,15 @@ status_t SAI_TransferGetReceiveCount(I2S_Type *base, sai_handle_t *handle, size_ return status; } +/*! + * brief Aborts the current send. + * + * note This API can be called any time when an interrupt non-blocking transfer initiates + * to abort the transfer early. + * + * param base SAI base pointer. + * param handle Pointer to the sai_handle_t structure which stores the transfer state. + */ void SAI_TransferAbortSend(I2S_Type *base, sai_handle_t *handle) { assert(handle); @@ -967,6 +1652,15 @@ void SAI_TransferAbortSend(I2S_Type *base, sai_handle_t *handle) handle->queueUser = 0; } +/*! + * brief Aborts the current IRQ receive. + * + * note This API can be called when an interrupt non-blocking transfer initiates + * to abort the transfer early. + * + * param base SAI base pointer + * param handle Pointer to the sai_handle_t structure which stores the transfer state. + */ void SAI_TransferAbortReceive(I2S_Type *base, sai_handle_t *handle) { assert(handle); @@ -988,6 +1682,15 @@ void SAI_TransferAbortReceive(I2S_Type *base, sai_handle_t *handle) handle->queueUser = 0; } +/*! + * brief Terminate all SAI send. + * + * This function will clear all transfer slots buffered in the sai queue. If users only want to abort the + * current transfer slot, please call SAI_TransferAbortSend. + * + * param base SAI base pointer. + * param handle SAI eDMA handle pointer. + */ void SAI_TransferTerminateSend(I2S_Type *base, sai_handle_t *handle) { assert(handle); @@ -1002,6 +1705,15 @@ void SAI_TransferTerminateSend(I2S_Type *base, sai_handle_t *handle) handle->queueDriver = 0U; } +/*! + * brief Terminate all SAI receive. + * + * This function will clear all transfer slots buffered in the sai queue. If users only want to abort the + * current transfer slot, please call SAI_TransferAbortReceive. + * + * param base SAI base pointer. + * param handle SAI eDMA handle pointer. + */ void SAI_TransferTerminateReceive(I2S_Type *base, sai_handle_t *handle) { assert(handle); @@ -1016,12 +1728,18 @@ void SAI_TransferTerminateReceive(I2S_Type *base, sai_handle_t *handle) handle->queueDriver = 0U; } +/*! + * brief Tx interrupt handler. + * + * param base SAI base pointer. + * param handle Pointer to the sai_handle_t structure. + */ void SAI_TransferTxHandleIRQ(I2S_Type *base, sai_handle_t *handle) { assert(handle); uint8_t *buffer = handle->saiQueue[handle->queueDriver].data; - uint8_t dataSize = handle->bitWidth / 8U; + uint8_t dataSize = (handle->bitWidth / 8U) * handle->channelNums; /* Handle Error */ if (base->TCSR & I2S_TCSR_FEF_MASK) @@ -1048,7 +1766,8 @@ void SAI_TransferTxHandleIRQ(I2S_Type *base, sai_handle_t *handle) (size_t)((FSL_FEATURE_SAI_FIFO_COUNT - handle->watermark) * dataSize)); /* Copy the data from sai buffer to FIFO */ - SAI_WriteNonBlocking(base, handle->channel, handle->bitWidth, buffer, size); + SAI_WriteNonBlocking(base, handle->channel, handle->channelMask, handle->endChannel, handle->bitWidth, buffer, + size); /* Update the internal counter */ handle->saiQueue[handle->queueDriver].dataSize -= size; @@ -1059,7 +1778,8 @@ void SAI_TransferTxHandleIRQ(I2S_Type *base, sai_handle_t *handle) { uint8_t size = MIN((handle->saiQueue[handle->queueDriver].dataSize), dataSize); - SAI_WriteNonBlocking(base, handle->channel, handle->bitWidth, buffer, size); + SAI_WriteNonBlocking(base, handle->channel, handle->channelMask, handle->endChannel, handle->bitWidth, buffer, + size); /* Update internal counter */ handle->saiQueue[handle->queueDriver].dataSize -= size; @@ -1085,12 +1805,18 @@ void SAI_TransferTxHandleIRQ(I2S_Type *base, sai_handle_t *handle) } } +/*! + * brief Tx interrupt handler. + * + * param base SAI base pointer. + * param handle Pointer to the sai_handle_t structure. + */ void SAI_TransferRxHandleIRQ(I2S_Type *base, sai_handle_t *handle) { assert(handle); uint8_t *buffer = handle->saiQueue[handle->queueDriver].data; - uint8_t dataSize = handle->bitWidth / 8U; + uint8_t dataSize = (handle->bitWidth / 8U) * handle->channelNums; /* Handle Error */ if (base->RCSR & I2S_RCSR_FEF_MASK) @@ -1116,7 +1842,8 @@ void SAI_TransferRxHandleIRQ(I2S_Type *base, sai_handle_t *handle) uint8_t size = MIN((handle->saiQueue[handle->queueDriver].dataSize), (handle->watermark * dataSize)); /* Copy the data from sai buffer to FIFO */ - SAI_ReadNonBlocking(base, handle->channel, handle->bitWidth, buffer, size); + SAI_ReadNonBlocking(base, handle->channel, handle->channelMask, handle->endChannel, handle->bitWidth, buffer, + size); /* Update the internal counter */ handle->saiQueue[handle->queueDriver].dataSize -= size; @@ -1127,7 +1854,8 @@ void SAI_TransferRxHandleIRQ(I2S_Type *base, sai_handle_t *handle) { uint8_t size = MIN((handle->saiQueue[handle->queueDriver].dataSize), dataSize); - SAI_ReadNonBlocking(base, handle->channel, handle->bitWidth, buffer, size); + SAI_ReadNonBlocking(base, handle->channel, handle->channelMask, handle->endChannel, handle->bitWidth, buffer, + size); /* Update internal state */ handle->saiQueue[handle->queueDriver].dataSize -= size; @@ -1365,6 +2093,226 @@ void I2S3_Rx_DriverIRQHandler(void) } #endif /* I2S3*/ +#if defined(I2S4) +void I2S4_DriverIRQHandler(void) +{ +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + if ((s_saiHandle[4][1]) && ((I2S4->RCSR & kSAI_FIFORequestFlag) || (I2S4->RCSR & kSAI_FIFOErrorFlag)) && + ((I2S4->RCSR & kSAI_FIFORequestInterruptEnable) || (I2S4->RCSR & kSAI_FIFOErrorInterruptEnable))) +#else + if ((s_saiHandle[4][1]) && ((I2S4->RCSR & kSAI_FIFOWarningFlag) || (I2S4->RCSR & kSAI_FIFOErrorFlag)) && + ((I2S4->RCSR & kSAI_FIFOWarningInterruptEnable) || (I2S4->RCSR & kSAI_FIFOErrorInterruptEnable))) +#endif + { + s_saiRxIsr(I2S4, s_saiHandle[4][1]); + } +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + if ((s_saiHandle[4][0]) && ((I2S4->TCSR & kSAI_FIFORequestFlag) || (I2S4->TCSR & kSAI_FIFOErrorFlag)) && + ((I2S4->TCSR & kSAI_FIFORequestInterruptEnable) || (I2S4->TCSR & kSAI_FIFOErrorInterruptEnable))) +#else + if ((s_saiHandle[4][0]) && ((I2S4->TCSR & kSAI_FIFOWarningFlag) || (I2S4->TCSR & kSAI_FIFOErrorFlag)) && + ((I2S4->TCSR & kSAI_FIFOWarningInterruptEnable) || (I2S4->TCSR & kSAI_FIFOErrorInterruptEnable))) +#endif + { + s_saiTxIsr(I2S4, s_saiHandle[4][0]); + } +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +void I2S4_Tx_DriverIRQHandler(void) +{ + assert(s_saiHandle[4][0]); + s_saiTxIsr(I2S4, s_saiHandle[4][0]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +void I2S4_Rx_DriverIRQHandler(void) +{ + assert(s_saiHandle[4][1]); + s_saiRxIsr(I2S4, s_saiHandle[4][1]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif + +#if defined(FSL_FEATURE_SAI5_SAI6_SHARE_IRQ) && (FSL_FEATURE_SAI5_SAI6_SHARE_IRQ) && defined(I2S5) && defined(I2S6) +void I2S56_DriverIRQHandler(void) +{ + /* use index 5 to get handle when I2S5 & I2S6 share IRQ NUMBER */ + I2S_Type *base = s_saiHandle[5][1]->base; +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + if ((s_saiHandle[5][1]) && base && ((base->RCSR & kSAI_FIFORequestFlag) || (base->RCSR & kSAI_FIFOErrorFlag)) && + ((base->RCSR & kSAI_FIFORequestInterruptEnable) || (base->RCSR & kSAI_FIFOErrorInterruptEnable))) +#else + if ((s_saiHandle[5][1]) && base && ((base->RCSR & kSAI_FIFOWarningFlag) || (base->RCSR & kSAI_FIFOErrorFlag)) && + ((base->RCSR & kSAI_FIFOWarningInterruptEnable) || (base->RCSR & kSAI_FIFOErrorInterruptEnable))) +#endif + { + s_saiRxIsr(base, s_saiHandle[5][1]); + } + + base = s_saiHandle[5][0]->base; +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + if ((s_saiHandle[5][0]) && base && ((base->TCSR & kSAI_FIFORequestFlag) || (base->TCSR & kSAI_FIFOErrorFlag)) && + ((base->TCSR & kSAI_FIFORequestInterruptEnable) || (base->TCSR & kSAI_FIFOErrorInterruptEnable))) +#else + if ((s_saiHandle[5][0]) && base && ((base->TCSR & kSAI_FIFOWarningFlag) || (base->TCSR & kSAI_FIFOErrorFlag)) && + ((base->TCSR & kSAI_FIFOWarningInterruptEnable) || (base->TCSR & kSAI_FIFOErrorInterruptEnable))) +#endif + { + s_saiTxIsr(base, s_saiHandle[5][0]); + } +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +void I2S56_Tx_DriverIRQHandler(void) +{ + /* use index 5 to get handle when I2S5 & I2S6 share IRQ NUMBER */ + assert(s_saiHandle[5][0]); + s_saiTxIsr(s_saiHandle[5][0]->base, s_saiHandle[5][0]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +void I2S56_Rx_DriverIRQHandler(void) +{ + /* use index 5 to get handle when I2S5 & I2S6 share IRQ NUMBER */ + assert(s_saiHandle[5][1]); + s_saiRxIsr(s_saiHandle[5][1]->base, s_saiHandle[5][1]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +#else + +#if defined(I2S5) +void I2S5_DriverIRQHandler(void) +{ +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + if ((s_saiHandle[5][1]) && ((I2S5->RCSR & kSAI_FIFORequestFlag) || (I2S5->RCSR & kSAI_FIFOErrorFlag)) && + ((I2S5->RCSR & kSAI_FIFORequestInterruptEnable) || (I2S5->RCSR & kSAI_FIFOErrorInterruptEnable))) +#else + if ((s_saiHandle[5][1]) && ((I2S5->RCSR & kSAI_FIFOWarningFlag) || (I2S5->RCSR & kSAI_FIFOErrorFlag)) && + ((I2S5->RCSR & kSAI_FIFOWarningInterruptEnable) || (I2S5->RCSR & kSAI_FIFOErrorInterruptEnable))) +#endif + { + s_saiRxIsr(I2S5, s_saiHandle[5][1]); + } +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + if ((s_saiHandle[5][0]) && ((I2S5->TCSR & kSAI_FIFORequestFlag) || (I2S5->TCSR & kSAI_FIFOErrorFlag)) && + ((I2S5->TCSR & kSAI_FIFORequestInterruptEnable) || (I2S5->TCSR & kSAI_FIFOErrorInterruptEnable))) +#else + if ((s_saiHandle[5][0]) && ((I2S5->TCSR & kSAI_FIFOWarningFlag) || (I2S5->TCSR & kSAI_FIFOErrorFlag)) && + ((I2S5->TCSR & kSAI_FIFOWarningInterruptEnable) || (I2S5->TCSR & kSAI_FIFOErrorInterruptEnable))) +#endif + { + s_saiTxIsr(I2S5, s_saiHandle[5][0]); + } +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +void I2S5_Tx_DriverIRQHandler(void) +{ + assert(s_saiHandle[5][0]); + s_saiTxIsr(I2S5, s_saiHandle[5][0]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +void I2S5_Rx_DriverIRQHandler(void) +{ + assert(s_saiHandle[5][1]); + s_saiRxIsr(I2S5, s_saiHandle[5][1]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif + +#if defined(I2S6) +void I2S6_DriverIRQHandler(void) +{ +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + if ((s_saiHandle[6][1]) && ((I2S6->RCSR & kSAI_FIFORequestFlag) || (I2S6->RCSR & kSAI_FIFOErrorFlag)) && + ((I2S6->RCSR & kSAI_FIFORequestInterruptEnable) || (I2S6->RCSR & kSAI_FIFOErrorInterruptEnable))) +#else + if ((s_saiHandle[6][1]) && ((I2S6->RCSR & kSAI_FIFOWarningFlag) || (I2S6->RCSR & kSAI_FIFOErrorFlag)) && + ((I2S6->RCSR & kSAI_FIFOWarningInterruptEnable) || (I2S6->RCSR & kSAI_FIFOErrorInterruptEnable))) +#endif + { + s_saiRxIsr(I2S6, s_saiHandle[6][1]); + } +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + if ((s_saiHandle[6][0]) && ((I2S6->TCSR & kSAI_FIFORequestFlag) || (I2S6->TCSR & kSAI_FIFOErrorFlag)) && + ((I2S6->TCSR & kSAI_FIFORequestInterruptEnable) || (I2S6->TCSR & kSAI_FIFOErrorInterruptEnable))) +#else + if ((s_saiHandle[6][0]) && ((I2S6->TCSR & kSAI_FIFOWarningFlag) || (I2S6->TCSR & kSAI_FIFOErrorFlag)) && + ((I2S6->TCSR & kSAI_FIFOWarningInterruptEnable) || (I2S6->TCSR & kSAI_FIFOErrorInterruptEnable))) +#endif + { + s_saiTxIsr(I2S6, s_saiHandle[6][0]); + } +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +void I2S6_Tx_DriverIRQHandler(void) +{ + assert(s_saiHandle[6][0]); + s_saiTxIsr(I2S6, s_saiHandle[6][0]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +void I2S6_Rx_DriverIRQHandler(void) +{ + assert(s_saiHandle[6][1]); + s_saiRxIsr(I2S6, s_saiHandle[6][1]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif +#endif + #if defined(AUDIO__SAI0) void AUDIO_SAI0_INT_DriverIRQHandler(void) { @@ -1575,6 +2523,192 @@ void AUDIO_SAI7_INT_DriverIRQHandler(void) } #endif /* AUDIO__SAI7 */ +#if defined(ADMA__SAI0) +void ADMA_SAI0_INT_DriverIRQHandler(void) +{ +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + if ((s_saiHandle[1][1]) && ((ADMA__SAI0->RCSR & kSAI_FIFORequestFlag) || (ADMA__SAI0->RCSR & kSAI_FIFOErrorFlag)) && + ((ADMA__SAI0->RCSR & kSAI_FIFORequestInterruptEnable) || (ADMA__SAI0->RCSR & kSAI_FIFOErrorInterruptEnable))) +#else + if ((s_saiHandle[1][1]) && ((ADMA__SAI0->RCSR & kSAI_FIFOWarningFlag) || (ADMA__SAI0->RCSR & kSAI_FIFOErrorFlag)) && + ((ADMA__SAI0->RCSR & kSAI_FIFOWarningInterruptEnable) || (ADMA__SAI0->RCSR & kSAI_FIFOErrorInterruptEnable))) +#endif + { + s_saiRxIsr(ADMA__SAI0, s_saiHandle[1][1]); + } +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + if ((s_saiHandle[1][0]) && ((ADMA__SAI0->TCSR & kSAI_FIFORequestFlag) || (ADMA__SAI0->TCSR & kSAI_FIFOErrorFlag)) && + ((ADMA__SAI0->TCSR & kSAI_FIFORequestInterruptEnable) || (ADMA__SAI0->TCSR & kSAI_FIFOErrorInterruptEnable))) +#else + if ((s_saiHandle[1][0]) && ((ADMA__SAI0->TCSR & kSAI_FIFOWarningFlag) || (ADMA__SAI0->TCSR & kSAI_FIFOErrorFlag)) && + ((ADMA__SAI0->TCSR & kSAI_FIFOWarningInterruptEnable) || (ADMA__SAI0->TCSR & kSAI_FIFOErrorInterruptEnable))) +#endif + { + s_saiTxIsr(ADMA__SAI0, s_saiHandle[1][0]); + } +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif /* ADMA__SAI0 */ + +#if defined(ADMA__SAI1) +void ADMA_SAI1_INT_DriverIRQHandler(void) +{ +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + if ((s_saiHandle[1][1]) && ((ADMA__SAI1->RCSR & kSAI_FIFORequestFlag) || (ADMA__SAI1->RCSR & kSAI_FIFOErrorFlag)) && + ((ADMA__SAI1->RCSR & kSAI_FIFORequestInterruptEnable) || (ADMA__SAI1->RCSR & kSAI_FIFOErrorInterruptEnable))) +#else + if ((s_saiHandle[1][1]) && ((ADMA__SAI1->RCSR & kSAI_FIFOWarningFlag) || (ADMA__SAI1->RCSR & kSAI_FIFOErrorFlag)) && + ((ADMA__SAI1->RCSR & kSAI_FIFOWarningInterruptEnable) || (ADMA__SAI1->RCSR & kSAI_FIFOErrorInterruptEnable))) +#endif + { + s_saiRxIsr(ADMA__SAI1, s_saiHandle[1][1]); + } +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + if ((s_saiHandle[1][0]) && ((ADMA__SAI1->TCSR & kSAI_FIFORequestFlag) || (ADMA__SAI1->TCSR & kSAI_FIFOErrorFlag)) && + ((ADMA__SAI1->TCSR & kSAI_FIFORequestInterruptEnable) || (ADMA__SAI1->TCSR & kSAI_FIFOErrorInterruptEnable))) +#else + if ((s_saiHandle[1][0]) && ((ADMA__SAI1->TCSR & kSAI_FIFOWarningFlag) || (ADMA__SAI1->TCSR & kSAI_FIFOErrorFlag)) && + ((ADMA__SAI1->TCSR & kSAI_FIFOWarningInterruptEnable) || (ADMA__SAI1->TCSR & kSAI_FIFOErrorInterruptEnable))) +#endif + { + s_saiTxIsr(ADMA__SAI1, s_saiHandle[1][0]); + } +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif /* ADMA__SAI1 */ + +#if defined(ADMA__SAI2) +void ADMA_SAI2_INT_DriverIRQHandler(void) +{ +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + if ((s_saiHandle[1][1]) && ((ADMA__SAI2->RCSR & kSAI_FIFORequestFlag) || (ADMA__SAI2->RCSR & kSAI_FIFOErrorFlag)) && + ((ADMA__SAI2->RCSR & kSAI_FIFORequestInterruptEnable) || (ADMA__SAI2->RCSR & kSAI_FIFOErrorInterruptEnable))) +#else + if ((s_saiHandle[1][1]) && ((ADMA__SAI2->RCSR & kSAI_FIFOWarningFlag) || (ADMA__SAI2->RCSR & kSAI_FIFOErrorFlag)) && + ((ADMA__SAI2->RCSR & kSAI_FIFOWarningInterruptEnable) || (ADMA__SAI2->RCSR & kSAI_FIFOErrorInterruptEnable))) +#endif + { + s_saiRxIsr(ADMA__SAI2, s_saiHandle[1][1]); + } +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + if ((s_saiHandle[1][0]) && ((ADMA__SAI2->TCSR & kSAI_FIFORequestFlag) || (ADMA__SAI2->TCSR & kSAI_FIFOErrorFlag)) && + ((ADMA__SAI2->TCSR & kSAI_FIFORequestInterruptEnable) || (ADMA__SAI2->TCSR & kSAI_FIFOErrorInterruptEnable))) +#else + if ((s_saiHandle[1][0]) && ((ADMA__SAI2->TCSR & kSAI_FIFOWarningFlag) || (ADMA__SAI2->TCSR & kSAI_FIFOErrorFlag)) && + ((ADMA__SAI2->TCSR & kSAI_FIFOWarningInterruptEnable) || (ADMA__SAI2->TCSR & kSAI_FIFOErrorInterruptEnable))) +#endif + { + s_saiTxIsr(ADMA__SAI2, s_saiHandle[1][0]); + } +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif /* ADMA__SAI2 */ + +#if defined(ADMA__SAI3) +void ADMA_SAI3_INT_DriverIRQHandler(void) +{ +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + if ((s_saiHandle[1][1]) && ((ADMA__SAI3->RCSR & kSAI_FIFORequestFlag) || (ADMA__SAI3->RCSR & kSAI_FIFOErrorFlag)) && + ((ADMA__SAI3->RCSR & kSAI_FIFORequestInterruptEnable) || (ADMA__SAI3->RCSR & kSAI_FIFOErrorInterruptEnable))) +#else + if ((s_saiHandle[1][1]) && ((ADMA__SAI3->RCSR & kSAI_FIFOWarningFlag) || (ADMA__SAI3->RCSR & kSAI_FIFOErrorFlag)) && + ((ADMA__SAI3->RCSR & kSAI_FIFOWarningInterruptEnable) || (ADMA__SAI3->RCSR & kSAI_FIFOErrorInterruptEnable))) +#endif + { + s_saiRxIsr(ADMA__SAI3, s_saiHandle[1][1]); + } +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + if ((s_saiHandle[1][0]) && ((ADMA__SAI3->TCSR & kSAI_FIFORequestFlag) || (ADMA__SAI3->TCSR & kSAI_FIFOErrorFlag)) && + ((ADMA__SAI3->TCSR & kSAI_FIFORequestInterruptEnable) || (ADMA__SAI3->TCSR & kSAI_FIFOErrorInterruptEnable))) +#else + if ((s_saiHandle[1][0]) && ((ADMA__SAI3->TCSR & kSAI_FIFOWarningFlag) || (ADMA__SAI3->TCSR & kSAI_FIFOErrorFlag)) && + ((ADMA__SAI3->TCSR & kSAI_FIFOWarningInterruptEnable) || (ADMA__SAI3->TCSR & kSAI_FIFOErrorInterruptEnable))) +#endif + { + s_saiTxIsr(ADMA__SAI3, s_saiHandle[1][0]); + } +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif /* ADMA__SAI3 */ + +#if defined(ADMA__SAI4) +void ADMA_SAI4_INT_DriverIRQHandler(void) +{ +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + if ((s_saiHandle[1][1]) && ((ADMA__SAI4->RCSR & kSAI_FIFORequestFlag) || (ADMA__SAI4->RCSR & kSAI_FIFOErrorFlag)) && + ((ADMA__SAI4->RCSR & kSAI_FIFORequestInterruptEnable) || (ADMA__SAI4->RCSR & kSAI_FIFOErrorInterruptEnable))) +#else + if ((s_saiHandle[1][1]) && ((ADMA__SAI4->RCSR & kSAI_FIFOWarningFlag) || (ADMA__SAI4->RCSR & kSAI_FIFOErrorFlag)) && + ((ADMA__SAI4->RCSR & kSAI_FIFOWarningInterruptEnable) || (ADMA__SAI4->RCSR & kSAI_FIFOErrorInterruptEnable))) +#endif + { + s_saiRxIsr(ADMA__SAI4, s_saiHandle[1][1]); + } +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + if ((s_saiHandle[1][0]) && ((ADMA__SAI4->TCSR & kSAI_FIFORequestFlag) || (ADMA__SAI4->TCSR & kSAI_FIFOErrorFlag)) && + ((ADMA__SAI4->TCSR & kSAI_FIFORequestInterruptEnable) || (ADMA__SAI4->TCSR & kSAI_FIFOErrorInterruptEnable))) +#else + if ((s_saiHandle[1][0]) && ((ADMA__SAI4->TCSR & kSAI_FIFOWarningFlag) || (ADMA__SAI4->TCSR & kSAI_FIFOErrorFlag)) && + ((ADMA__SAI4->TCSR & kSAI_FIFOWarningInterruptEnable) || (ADMA__SAI4->TCSR & kSAI_FIFOErrorInterruptEnable))) +#endif + { + s_saiTxIsr(ADMA__SAI4, s_saiHandle[1][0]); + } +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif /* ADMA__SAI4 */ + +#if defined(ADMA__SAI5) +void ADMA_SAI5_INT_DriverIRQHandler(void) +{ +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + if ((s_saiHandle[1][1]) && ((ADMA__SAI5->RCSR & kSAI_FIFORequestFlag) || (ADMA__SAI5->RCSR & kSAI_FIFOErrorFlag)) && + ((ADMA__SAI5->RCSR & kSAI_FIFORequestInterruptEnable) || (ADMA__SAI5->RCSR & kSAI_FIFOErrorInterruptEnable))) +#else + if ((s_saiHandle[1][1]) && ((ADMA__SAI5->RCSR & kSAI_FIFOWarningFlag) || (ADMA__SAI5->RCSR & kSAI_FIFOErrorFlag)) && + ((ADMA__SAI5->RCSR & kSAI_FIFOWarningInterruptEnable) || (ADMA__SAI5->RCSR & kSAI_FIFOErrorInterruptEnable))) +#endif + { + s_saiRxIsr(ADMA__SAI5, s_saiHandle[1][1]); + } +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + if ((s_saiHandle[1][0]) && ((ADMA__SAI5->TCSR & kSAI_FIFORequestFlag) || (ADMA__SAI5->TCSR & kSAI_FIFOErrorFlag)) && + ((ADMA__SAI5->TCSR & kSAI_FIFORequestInterruptEnable) || (ADMA__SAI5->TCSR & kSAI_FIFOErrorInterruptEnable))) +#else + if ((s_saiHandle[1][0]) && ((ADMA__SAI5->TCSR & kSAI_FIFOWarningFlag) || (ADMA__SAI5->TCSR & kSAI_FIFOErrorFlag)) && + ((ADMA__SAI5->TCSR & kSAI_FIFOWarningInterruptEnable) || (ADMA__SAI5->TCSR & kSAI_FIFOErrorInterruptEnable))) +#endif + { + s_saiTxIsr(ADMA__SAI5, s_saiHandle[1][0]); + } +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif /* ADMA__SAI5 */ + #if defined(SAI0) void SAI0_DriverIRQHandler(void) { @@ -1697,6 +2831,28 @@ void SAI3_DriverIRQHandler(void) __DSB(); #endif } + +void SAI3_TX_DriverIRQHandler(void) +{ + assert(s_saiHandle[3][0]); + s_saiTxIsr(SAI3, s_saiHandle[3][0]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +void SAI3_RX_DriverIRQHandler(void) +{ + assert(s_saiHandle[3][1]); + s_saiRxIsr(SAI3, s_saiHandle[3][1]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} #endif /* SAI3 */ #if defined(SAI4) diff --git a/ext/hal/nxp/mcux/drivers/kinetis/fsl_sai.h b/ext/hal/nxp/mcux/drivers/kinetis/fsl_sai.h index 857e9c22123..c6d33c746e0 100644 --- a/ext/hal/nxp/mcux/drivers/kinetis/fsl_sai.h +++ b/ext/hal/nxp/mcux/drivers/kinetis/fsl_sai.h @@ -1,31 +1,9 @@ /* * Copyright (c) 2015, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP + * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * SPDX-License-Identifier: BSD-3-Clause */ #ifndef _FSL_SAI_H_ @@ -44,7 +22,7 @@ /*! @name Driver version */ /*@{*/ -#define FSL_SAI_DRIVER_VERSION (MAKE_VERSION(2, 1, 3)) /*!< Version 2.1.3 */ +#define FSL_SAI_DRIVER_VERSION (MAKE_VERSION(2, 1, 7)) /*!< Version 2.1.7 */ /*@}*/ /*! @brief SAI return status*/ @@ -59,6 +37,19 @@ enum _sai_status_t kStatus_SAI_RxIdle = MAKE_STATUS(kStatusGroup_SAI, 6) /*!< SAI Rx is idle */ }; +/*< sai channel mask value, actual channel numbers is depend soc specific */ +enum _sai_channel_mask +{ + kSAI_Channel0Mask = 1 << 0U, /*!< channel 0 mask value */ + kSAI_Channel1Mask = 1 << 1U, /*!< channel 1 mask value */ + kSAI_Channel2Mask = 1 << 2U, /*!< channel 2 mask value */ + kSAI_Channel3Mask = 1 << 3U, /*!< channel 3 mask value */ + kSAI_Channel4Mask = 1 << 4U, /*!< channel 4 mask value */ + kSAI_Channel5Mask = 1 << 5U, /*!< channel 5 mask value */ + kSAI_Channel6Mask = 1 << 6U, /*!< channel 6 mask value */ + kSAI_Channel7Mask = 1 << 7U, /*!< channel 7 mask value */ +}; + /*! @brief Define the SAI bus type */ typedef enum _sai_protocol { @@ -84,6 +75,20 @@ typedef enum _sai_mono_stereo kSAI_MonoLeft /*!< Only left channel have sound. */ } sai_mono_stereo_t; +/*! @brief SAI data order, MSB or LSB */ +typedef enum _sai_data_order +{ + kSAI_DataLSB = 0x0U, /*!< LSB bit transferred first */ + kSAI_DataMSB /*!< MSB bit transferred first */ +} sai_data_order_t; + +/*! @brief SAI clock polarity, active high or low */ +typedef enum _sai_clock_polarity +{ + kSAI_PolarityActiveHigh = 0x0U, /*!< Clock active high */ + kSAI_PolarityActiveLow /*!< Clock active low */ +} sai_clock_polarity_t; + /*! @brief Synchronous or asynchronous mode */ typedef enum _sai_sync_mode { @@ -93,6 +98,7 @@ typedef enum _sai_sync_mode kSAI_ModeSyncWithOtherRx /*!< Synchronous with another SAI receiver */ } sai_sync_mode_t; +#if !(defined(FSL_FEATURE_SAI_HAS_NO_MCR_MICS) && (FSL_FEATURE_SAI_HAS_NO_MCR_MICS)) /*! @brief Mater clock source */ typedef enum _sai_mclk_source { @@ -101,14 +107,20 @@ typedef enum _sai_mclk_source kSAI_MclkSourceSelect2, /*!< Master clock from source 2 */ kSAI_MclkSourceSelect3 /*!< Master clock from source 3 */ } sai_mclk_source_t; +#endif /*! @brief Bit clock source */ typedef enum _sai_bclk_source { kSAI_BclkSourceBusclk = 0x0U, /*!< Bit clock using bus clock */ - kSAI_BclkSourceMclkDiv, /*!< Bit clock using master clock divider */ - kSAI_BclkSourceOtherSai0, /*!< Bit clock from other SAI device */ - kSAI_BclkSourceOtherSai1 /*!< Bit clock from other SAI device */ + /* General device bit source definition */ + kSAI_BclkSourceMclkOption1 = 0x1U, /*!< Bit clock MCLK option 1 */ + kSAI_BclkSourceMclkOption2 = 0x2U, /*!< Bit clock MCLK option2 */ + kSAI_BclkSourceMclkOption3 = 0x3U, /*!< Bit clock MCLK option3 */ + /* Kinetis device bit clock source definition */ + kSAI_BclkSourceMclkDiv = 0x1U, /*!< Bit clock using master clock divider */ + kSAI_BclkSourceOtherSai0 = 0x2U, /*!< Bit clock from other SAI device */ + kSAI_BclkSourceOtherSai1 = 0x3U /*!< Bit clock from other SAI device */ } sai_bclk_source_t; /*! @brief The SAI interrupt enable flag */ @@ -172,9 +184,11 @@ typedef struct _sai_config sai_protocol_t protocol; /*!< Audio bus protocol in SAI */ sai_sync_mode_t syncMode; /*!< SAI sync mode, control Tx/Rx clock sync */ #if defined(FSL_FEATURE_SAI_HAS_MCR) && (FSL_FEATURE_SAI_HAS_MCR) - bool mclkOutputEnable; /*!< Master clock output enable, true means master clock divider enabled */ -#endif /* FSL_FEATURE_SAI_HAS_MCR */ - sai_mclk_source_t mclkSource; /*!< Master Clock source */ + bool mclkOutputEnable; /*!< Master clock output enable, true means master clock divider enabled */ +#if !(defined(FSL_FEATURE_SAI_HAS_NO_MCR_MICS) && (FSL_FEATURE_SAI_HAS_NO_MCR_MICS)) + sai_mclk_source_t mclkSource; /*!< Master Clock source */ +#endif /* FSL_FEATURE_SAI_HAS_MCR */ +#endif sai_bclk_source_t bclkSource; /*!< Bit Clock source */ sai_master_slave_t masterSlave; /*!< Master or slave */ } sai_config_t; @@ -194,7 +208,9 @@ typedef enum _sai_sample_rate kSAI_SampleRate32KHz = 32000U, /*!< Sample rate 32000 Hz */ kSAI_SampleRate44100Hz = 44100U, /*!< Sample rate 44100 Hz */ kSAI_SampleRate48KHz = 48000U, /*!< Sample rate 48000 Hz */ - kSAI_SampleRate96KHz = 96000U /*!< Sample rate 96000 Hz */ + kSAI_SampleRate96KHz = 96000U, /*!< Sample rate 96000 Hz */ + kSAI_SampleRate192KHz = 192000U, /*!< Sample rate 192000 Hz */ + kSAI_SampleRate384KHz = 384000U, /*!< Sample rate 384000 Hz */ } sai_sample_rate_t; /*! @brief Audio word width */ @@ -214,9 +230,21 @@ typedef struct _sai_transfer_format sai_mono_stereo_t stereo; /*!< Mono or stereo */ uint32_t masterClockHz; /*!< Master clock frequency in Hz */ #if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) - uint8_t watermark; /*!< Watermark value */ -#endif /* FSL_FEATURE_SAI_FIFO_COUNT */ - uint8_t channel; /*!< Data channel used in transfer.*/ + uint8_t watermark; /*!< Watermark value */ +#endif /* FSL_FEATURE_SAI_FIFO_COUNT */ + + /* for the multi channel usage, user can provide channelMask Oonly, then sai driver will handle + * other parameter carefully, such as + * channelMask = kSAI_Channel0Mask | kSAI_Channel1Mask | kSAI_Channel4Mask + * then in SAI_RxSetFormat/SAI_TxSetFormat function, channel/endChannel/channelNums will be calculated. + * for the single channel usage, user can provide channel or channel mask only, such as, + * channel = 0 or channelMask = kSAI_Channel0Mask. + */ + uint8_t channel; /*!< Transfer start channel */ + uint8_t channelMask; /*!< enabled channel mask value, reference _sai_channel_mask */ + uint8_t endChannel; /*!< end channel number */ + uint8_t channelNums; /*!< Total enabled channel numbers */ + sai_protocol_t protocol; /*!< Which audio protocol used */ bool isFrameSyncCompact; /*!< True means Frame sync length is configurable according to bitWidth, false means frame sync length is 64 times of bit clock. */ @@ -237,11 +265,25 @@ typedef void (*sai_transfer_callback_t)(I2S_Type *base, sai_handle_t *handle, st /*! @brief SAI handle structure */ struct _sai_handle { - uint32_t state; /*!< Transfer status */ - sai_transfer_callback_t callback; /*!< Callback function called at transfer event*/ - void *userData; /*!< Callback parameter passed to callback function*/ - uint8_t bitWidth; /*!< Bit width for transfer, 8/16/24/32 bits */ - uint8_t channel; /*!< Transfer channel */ + I2S_Type *base; /*!< base address */ + + uint32_t state; /*!< Transfer status */ + sai_transfer_callback_t callback; /*!< Callback function called at transfer event*/ + void *userData; /*!< Callback parameter passed to callback function*/ + uint8_t bitWidth; /*!< Bit width for transfer, 8/16/24/32 bits */ + + /* for the multi channel usage, user can provide channelMask Oonly, then sai driver will handle + * other parameter carefully, such as + * channelMask = kSAI_Channel0Mask | kSAI_Channel1Mask | kSAI_Channel4Mask + * then in SAI_RxSetFormat/SAI_TxSetFormat function, channel/endChannel/channelNums will be calculated. + * for the single channel usage, user can provide channel or channel mask only, such as, + * channel = 0 or channelMask = kSAI_Channel0Mask. + */ + uint8_t channel; /*!< Transfer start channel */ + uint8_t channelMask; /*!< enabled channel mask value, refernece _sai_channel_mask */ + uint8_t endChannel; /*!< end channel number */ + uint8_t channelNums; /*!< Total enabled channel numbers */ + sai_transfer_t saiQueue[SAI_XFER_QUEUE_SIZE]; /*!< Transfer queue storing queued transfer */ size_t transferSize[SAI_XFER_QUEUE_SIZE]; /*!< Data bytes need to transfer */ volatile uint8_t queueUser; /*!< Index for user to queue transfer */ @@ -281,7 +323,7 @@ extern "C" { void SAI_TxInit(I2S_Type *base, const sai_config_t *config); /*! - * @brief Initializes the the SAI Rx peripheral. + * @brief Initializes the SAI Rx peripheral. * * Ungates the SAI clock, resets the module, and configures the SAI Rx with a configuration structure. * The configuration structure can be custom filled or set with default values by @@ -473,6 +515,115 @@ void SAI_TxSetChannelFIFOMask(I2S_Type *base, uint8_t mask); */ void SAI_RxSetChannelFIFOMask(I2S_Type *base, uint8_t mask); +/*! + * @brief Set the Tx data order. + * + * @param base SAI base pointer + * @param order Data order MSB or LSB + */ +void SAI_TxSetDataOrder(I2S_Type *base, sai_data_order_t order); + +/*! + * @brief Set the Rx data order. + * + * @param base SAI base pointer + * @param order Data order MSB or LSB + */ +void SAI_RxSetDataOrder(I2S_Type *base, sai_data_order_t order); + +/*! + * @brief Set the Tx data order. + * + * @param base SAI base pointer + * @param order Data order MSB or LSB + */ +void SAI_TxSetBitClockPolarity(I2S_Type *base, sai_clock_polarity_t polarity); + +/*! + * @brief Set the Rx data order. + * + * @param base SAI base pointer + * @param order Data order MSB or LSB + */ +void SAI_RxSetBitClockPolarity(I2S_Type *base, sai_clock_polarity_t polarity); + +/*! + * @brief Set the Tx data order. + * + * @param base SAI base pointer + * @param order Data order MSB or LSB + */ +void SAI_TxSetFrameSyncPolarity(I2S_Type *base, sai_clock_polarity_t polarity); + +/*! + * @brief Set the Rx data order. + * + * @param base SAI base pointer + * @param order Data order MSB or LSB + */ +void SAI_RxSetFrameSyncPolarity(I2S_Type *base, sai_clock_polarity_t polarity); + +#if defined(FSL_FEATURE_SAI_HAS_FIFO_PACKING) && FSL_FEATURE_SAI_HAS_FIFO_PACKING +/*! + * @brief Set Tx FIFO packing feature. + * + * @param base SAI base pointer. + * @param pack FIFO pack type. It is element of sai_fifo_packing_t. + */ +void SAI_TxSetFIFOPacking(I2S_Type *base, sai_fifo_packing_t pack); + +/*! +* @brief Set Rx FIFO packing feature. +* +* @param base SAI base pointer. +* @param pack FIFO pack type. It is element of sai_fifo_packing_t. +*/ +void SAI_RxSetFIFOPacking(I2S_Type *base, sai_fifo_packing_t pack); +#endif /* FSL_FEATURE_SAI_HAS_FIFO_PACKING */ + +#if defined(FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR) && FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR +/*! +* @brief Set Tx FIFO error continue. +* +* FIFO error continue mode means SAI will keep running while FIFO error occured. If this feature +* not enabled, SAI will hang and users need to clear FEF flag in TCSR register. +* +* @param base SAI base pointer. +* @param isEnabled Is FIFO error continue enabled, true means enable, false means disable. +*/ +static inline void SAI_TxSetFIFOErrorContinue(I2S_Type *base, bool isEnabled) +{ + if (isEnabled) + { + base->TCR4 |= I2S_TCR4_FCONT_MASK; + } + else + { + base->TCR4 &= ~I2S_TCR4_FCONT_MASK; + } +} + +/*! +* @brief Set Rx FIFO error continue. +* +* FIFO error continue mode means SAI will keep running while FIFO error occured. If this feature +* not enabled, SAI will hang and users need to clear FEF flag in RCSR register. +* +* @param base SAI base pointer. +* @param isEnabled Is FIFO error continue enabled, true means enable, false means disable. +*/ +static inline void SAI_RxSetFIFOErrorContinue(I2S_Type *base, bool isEnabled) +{ + if (isEnabled) + { + base->RCR4 |= I2S_RCR4_FCONT_MASK; + } + else + { + base->RCR4 &= ~I2S_RCR4_FCONT_MASK; + } +} +#endif /*! @} */ /*! @@ -679,6 +830,21 @@ void SAI_RxSetFormat(I2S_Type *base, */ void SAI_WriteBlocking(I2S_Type *base, uint32_t channel, uint32_t bitWidth, uint8_t *buffer, uint32_t size); +/*! + * @brief Sends data to multi channel using a blocking method. + * + * @note This function blocks by polling until data is ready to be sent. + * + * @param base SAI base pointer. + * @param channel Data channel used. + * @param channelMask channel mask. + * @param bitWidth How many bits in an audio word; usually 8/16/24/32 bits. + * @param buffer Pointer to the data to be written. + * @param size Bytes to be written. + */ +void SAI_WriteMultiChannelBlocking( + I2S_Type *base, uint32_t channel, uint32_t channelMask, uint32_t bitWidth, uint8_t *buffer, uint32_t size); + /*! * @brief Writes data into SAI FIFO. * @@ -704,6 +870,21 @@ static inline void SAI_WriteData(I2S_Type *base, uint32_t channel, uint32_t data */ void SAI_ReadBlocking(I2S_Type *base, uint32_t channel, uint32_t bitWidth, uint8_t *buffer, uint32_t size); +/*! + * @brief Receives multi channel data using a blocking method. + * + * @note This function blocks by polling until data is ready to be sent. + * + * @param base SAI base pointer. + * @param channel Data channel used. + * @param channelMask channel mask. + * @param bitWidth How many bits in an audio word; usually 8/16/24/32 bits. + * @param buffer Pointer to the data to be read. + * @param size Bytes to be read. + */ +void SAI_ReadMultiChannelBlocking( + I2S_Type *base, uint32_t channel, uint32_t channelMask, uint32_t bitWidth, uint8_t *buffer, uint32_t size); + /*! * @brief Reads data from the SAI FIFO. * @@ -857,7 +1038,7 @@ status_t SAI_TransferGetReceiveCount(I2S_Type *base, sai_handle_t *handle, size_ void SAI_TransferAbortSend(I2S_Type *base, sai_handle_t *handle); /*! - * @brief Aborts the the current IRQ receive. + * @brief Aborts the current IRQ receive. * * @note This API can be called when an interrupt non-blocking transfer initiates * to abort the transfer early. diff --git a/ext/hal/nxp/mcux/drivers/kinetis/fsl_sai_edma.c b/ext/hal/nxp/mcux/drivers/kinetis/fsl_sai_edma.c index 6f4dda6998b..116d088d9f2 100644 --- a/ext/hal/nxp/mcux/drivers/kinetis/fsl_sai_edma.c +++ b/ext/hal/nxp/mcux/drivers/kinetis/fsl_sai_edma.c @@ -1,40 +1,25 @@ /* * Copyright (c) 2015, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP + * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * SPDX-License-Identifier: BSD-3-Clause */ #include "fsl_sai_edma.h" +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.sai_edma" +#endif + /******************************************************************************* * Definitations ******************************************************************************/ /* Used for 32byte aligned */ -#define STCD_ADDR(address) (edma_tcd_t *)(((uint32_t)address + 32) & ~0x1FU) +#define STCD_ADDR(address) (edma_tcd_t *)(((uint32_t)(address) + 32) & ~0x1FU) + +static I2S_Type *const s_saiBases[] = I2S_BASE_PTRS; /*tcd), SAI_XFER_QUEUE_SIZE); + EDMA_InstallTCDMemory(dmaHandle, (edma_tcd_t *)(STCD_ADDR(handle->tcd)), SAI_XFER_QUEUE_SIZE); /* Install callback for Tx dma channel */ EDMA_SetCallback(dmaHandle, SAI_TxEDMACallback, &s_edmaPrivateHandle[instance][0]); } +/*! + * brief Initializes the SAI Rx eDMA handle. + * + * This function initializes the SAI slave DMA handle, which can be used for other SAI master transactional APIs. + * Usually, for a specified SAI instance, call this API once to get the initialized handle. + * + * param base SAI base pointer. + * param handle SAI eDMA handle pointer. + * param base SAI peripheral base address. + * param callback Pointer to user callback function. + * param userData User parameter passed to the callback function. + * param dmaHandle eDMA handle pointer, this handle shall be static allocated by users. + */ void SAI_TransferRxCreateHandleEDMA( I2S_Type *base, sai_edma_handle_t *handle, sai_edma_callback_t callback, void *userData, edma_handle_t *dmaHandle) { @@ -185,6 +214,21 @@ void SAI_TransferRxCreateHandleEDMA( EDMA_SetCallback(dmaHandle, SAI_RxEDMACallback, &s_edmaPrivateHandle[instance][1]); } +/*! + * brief Configures the SAI Tx audio format. + * + * The audio format can be changed at run-time. This function configures the sample rate and audio data + * format to be transferred. This function also sets the eDMA parameter according to formatting requirements. + * + * param base SAI base pointer. + * param handle SAI eDMA handle pointer. + * param format Pointer to SAI audio data format structure. + * param mclkSourceClockHz SAI master clock source frequency in Hz. + * param bclkSourceClockHz SAI bit clock source frequency in Hz. If bit clock source is master + * clock, this value should equals to masterClockHz in format. + * retval kStatus_Success Audio format set successfully. + * retval kStatus_InvalidArgument The input argument is invalid. +*/ void SAI_TransferTxSetFormatEDMA(I2S_Type *base, sai_edma_handle_t *handle, sai_transfer_format_t *format, @@ -218,6 +262,21 @@ void SAI_TransferTxSetFormatEDMA(I2S_Type *base, #endif /* FSL_FEATURE_SAI_FIFO_COUNT */ } +/*! + * brief Configures the SAI Rx audio format. + * + * The audio format can be changed at run-time. This function configures the sample rate and audio data + * format to be transferred. This function also sets the eDMA parameter according to formatting requirements. + * + * param base SAI base pointer. + * param handle SAI eDMA handle pointer. + * param format Pointer to SAI audio data format structure. + * param mclkSourceClockHz SAI master clock source frequency in Hz. + * param bclkSourceClockHz SAI bit clock source frequency in Hz. If a bit clock source is the master + * clock, this value should equal to masterClockHz in format. + * retval kStatus_Success Audio format set successfully. + * retval kStatus_InvalidArgument The input argument is invalid. +*/ void SAI_TransferRxSetFormatEDMA(I2S_Type *base, sai_edma_handle_t *handle, sai_transfer_format_t *format, @@ -251,6 +310,19 @@ void SAI_TransferRxSetFormatEDMA(I2S_Type *base, #endif /* FSL_FEATURE_SAI_FIFO_COUNT */ } +/*! + * brief Performs a non-blocking SAI transfer using DMA. + * + * note This interface returns immediately after the transfer initiates. Call + * SAI_GetTransferStatus to poll the transfer status and check whether the SAI transfer is finished. + * + * param base SAI base pointer. + * param handle SAI eDMA handle pointer. + * param xfer Pointer to the DMA transfer structure. + * retval kStatus_Success Start a SAI eDMA send successfully. + * retval kStatus_InvalidArgument The input argument is invalid. + * retval kStatus_TxBusy SAI is busy sending data. + */ status_t SAI_TransferSendEDMA(I2S_Type *base, sai_edma_handle_t *handle, sai_transfer_t *xfer) { assert(handle && xfer); @@ -302,6 +374,19 @@ status_t SAI_TransferSendEDMA(I2S_Type *base, sai_edma_handle_t *handle, sai_tra return kStatus_Success; } +/*! + * brief Performs a non-blocking SAI receive using eDMA. + * + * note This interface returns immediately after the transfer initiates. Call + * the SAI_GetReceiveRemainingBytes to poll the transfer status and check whether the SAI transfer is finished. + * + * param base SAI base pointer + * param handle SAI eDMA handle pointer. + * param xfer Pointer to DMA transfer structure. + * retval kStatus_Success Start a SAI eDMA receive successfully. + * retval kStatus_InvalidArgument The input argument is invalid. + * retval kStatus_RxBusy SAI is busy receiving data. + */ status_t SAI_TransferReceiveEDMA(I2S_Type *base, sai_edma_handle_t *handle, sai_transfer_t *xfer) { assert(handle && xfer); @@ -353,6 +438,15 @@ status_t SAI_TransferReceiveEDMA(I2S_Type *base, sai_edma_handle_t *handle, sai_ return kStatus_Success; } +/*! + * brief Aborts a SAI transfer using eDMA. + * + * This function only aborts the current transfer slots, the other transfer slots' information still kept + * in the handler. If users want to terminate all transfer slots, just call SAI_TransferTerminateSendEDMA. + * + * param base SAI base pointer. + * param handle SAI eDMA handle pointer. + */ void SAI_TransferAbortSendEDMA(I2S_Type *base, sai_edma_handle_t *handle) { assert(handle); @@ -381,6 +475,15 @@ void SAI_TransferAbortSendEDMA(I2S_Type *base, sai_edma_handle_t *handle) handle->state = kSAI_Idle; } +/*! + * brief Aborts a SAI receive using eDMA. + * + * This function only aborts the current transfer slots, the other transfer slots' information still kept + * in the handler. If users want to terminate all transfer slots, just call SAI_TransferTerminateReceiveEDMA. + * + * param base SAI base pointer + * param handle SAI eDMA handle pointer. + */ void SAI_TransferAbortReceiveEDMA(I2S_Type *base, sai_edma_handle_t *handle) { assert(handle); @@ -409,6 +512,15 @@ void SAI_TransferAbortReceiveEDMA(I2S_Type *base, sai_edma_handle_t *handle) handle->state = kSAI_Idle; } +/*! + * brief Terminate all SAI send. + * + * This function will clear all transfer slots buffered in the sai queue. If users only want to abort the + * current transfer slot, please call SAI_TransferAbortSendEDMA. + * + * param base SAI base pointer. + * param handle SAI eDMA handle pointer. + */ void SAI_TransferTerminateSendEDMA(I2S_Type *base, sai_edma_handle_t *handle) { assert(handle); @@ -424,6 +536,15 @@ void SAI_TransferTerminateSendEDMA(I2S_Type *base, sai_edma_handle_t *handle) handle->queueDriver = 0U; } +/*! + * brief Terminate all SAI receive. + * + * This function will clear all transfer slots buffered in the sai queue. If users only want to abort the + * current transfer slot, please call SAI_TransferAbortReceiveEDMA. + * + * param base SAI base pointer. + * param handle SAI eDMA handle pointer. + */ void SAI_TransferTerminateReceiveEDMA(I2S_Type *base, sai_edma_handle_t *handle) { assert(handle); @@ -439,6 +560,15 @@ void SAI_TransferTerminateReceiveEDMA(I2S_Type *base, sai_edma_handle_t *handle) handle->queueDriver = 0U; } +/*! + * brief Gets byte count sent by SAI. + * + * param base SAI base pointer. + * param handle SAI eDMA handle pointer. + * param count Bytes count sent by SAI. + * retval kStatus_Success Succeed get the transfer count. + * retval kStatus_NoTransferInProgress There is no non-blocking transaction in progress. + */ status_t SAI_TransferGetSendCountEDMA(I2S_Type *base, sai_edma_handle_t *handle, size_t *count) { assert(handle); @@ -459,6 +589,15 @@ status_t SAI_TransferGetSendCountEDMA(I2S_Type *base, sai_edma_handle_t *handle, return status; } +/*! + * brief Gets byte count received by SAI. + * + * param base SAI base pointer + * param handle SAI eDMA handle pointer. + * param count Bytes count received by SAI. + * retval kStatus_Success Succeed get the transfer count. + * retval kStatus_NoTransferInProgress There is no non-blocking transaction in progress. + */ status_t SAI_TransferGetReceiveCountEDMA(I2S_Type *base, sai_edma_handle_t *handle, size_t *count) { assert(handle); diff --git a/ext/hal/nxp/mcux/drivers/kinetis/fsl_sai_edma.h b/ext/hal/nxp/mcux/drivers/kinetis/fsl_sai_edma.h index ef4f5c005a9..b3d913948b5 100644 --- a/ext/hal/nxp/mcux/drivers/kinetis/fsl_sai_edma.h +++ b/ext/hal/nxp/mcux/drivers/kinetis/fsl_sai_edma.h @@ -1,31 +1,9 @@ /* * Copyright (c) 2015, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP + * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * SPDX-License-Identifier: BSD-3-Clause */ #ifndef _FSL_SAI_EDMA_H_ #define _FSL_SAI_EDMA_H_ @@ -42,6 +20,11 @@ * Definitions ******************************************************************************/ +/*! @name Driver version */ +/*@{*/ +#define FSL_SAI_EDMA_DRIVER_VERSION (MAKE_VERSION(2, 1, 5)) /*!< Version 2.1.5 */ +/*@}*/ + typedef struct _sai_edma_handle sai_edma_handle_t; /*! @brief SAI eDMA transfer callback function for finish and error */ @@ -50,19 +33,19 @@ typedef void (*sai_edma_callback_t)(I2S_Type *base, sai_edma_handle_t *handle, s /*! @brief SAI DMA transfer handle, users should not touch the content of the handle.*/ struct _sai_edma_handle { - edma_handle_t *dmaHandle; /*!< DMA handler for SAI send */ - uint8_t nbytes; /*!< eDMA minor byte transfer count initially configured. */ - uint8_t bytesPerFrame; /*!< Bytes in a frame */ - uint8_t channel; /*!< Which data channel */ - uint8_t count; /*!< The transfer data count in a DMA request */ - uint32_t state; /*!< Internal state for SAI eDMA transfer */ - sai_edma_callback_t callback; /*!< Callback for users while transfer finish or error occurs */ - void *userData; /*!< User callback parameter */ - edma_tcd_t tcd[SAI_XFER_QUEUE_SIZE + 1U]; /*!< TCD pool for eDMA transfer. */ - sai_transfer_t saiQueue[SAI_XFER_QUEUE_SIZE]; /*!< Transfer queue storing queued transfer. */ - size_t transferSize[SAI_XFER_QUEUE_SIZE]; /*!< Data bytes need to transfer */ - volatile uint8_t queueUser; /*!< Index for user to queue transfer. */ - volatile uint8_t queueDriver; /*!< Index for driver to get the transfer data and size */ + edma_handle_t *dmaHandle; /*!< DMA handler for SAI send */ + uint8_t nbytes; /*!< eDMA minor byte transfer count initially configured. */ + uint8_t bytesPerFrame; /*!< Bytes in a frame */ + uint8_t channel; /*!< Which data channel */ + uint8_t count; /*!< The transfer data count in a DMA request */ + uint32_t state; /*!< Internal state for SAI eDMA transfer */ + sai_edma_callback_t callback; /*!< Callback for users while transfer finish or error occurs */ + void *userData; /*!< User callback parameter */ + uint8_t tcd[(SAI_XFER_QUEUE_SIZE + 1U) * sizeof(edma_tcd_t)]; /*!< TCD pool for eDMA transfer. */ + sai_transfer_t saiQueue[SAI_XFER_QUEUE_SIZE]; /*!< Transfer queue storing queued transfer. */ + size_t transferSize[SAI_XFER_QUEUE_SIZE]; /*!< Data bytes need to transfer */ + volatile uint8_t queueUser; /*!< Index for user to queue transfer. */ + volatile uint8_t queueDriver; /*!< Index for driver to get the transfer data and size */ }; /******************************************************************************* diff --git a/ext/hal/nxp/mcux/drivers/kinetis/fsl_sdhc.c b/ext/hal/nxp/mcux/drivers/kinetis/fsl_sdhc.c index 3151cd22ed9..24dce540474 100644 --- a/ext/hal/nxp/mcux/drivers/kinetis/fsl_sdhc.c +++ b/ext/hal/nxp/mcux/drivers/kinetis/fsl_sdhc.c @@ -1,31 +1,9 @@ /* * Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP + * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * SPDX-License-Identifier: BSD-3-Clause */ #include "fsl_sdhc.h" @@ -33,6 +11,12 @@ /******************************************************************************* * Definitions ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.sdhc" +#endif + /*! @brief Clock setting */ /* Max SD clock divisor from base clock */ #define SDHC_MAX_DVS ((SDHC_SYSCTL_DVS_MASK >> SDHC_SYSCTL_DVS_SHIFT) + 1U) @@ -172,10 +156,11 @@ static status_t SDHC_TransferDataBlocking(sdhc_dma_mode_t dmaMode, SDHC_Type *ba /*! * @brief Handle card detect interrupt. * + * @param base SDHC peripheral base address. * @param handle SDHC handle. * @param interruptFlags Card detect related interrupt flags. */ -static void SDHC_TransferHandleCardDetect(sdhc_handle_t *handle, uint32_t interruptFlags); +static void SDHC_TransferHandleCardDetect(SDHC_Type *base, sdhc_handle_t *handle, uint32_t interruptFlags); /*! * @brief Handle command interrupt. @@ -198,16 +183,18 @@ static void SDHC_TransferHandleData(SDHC_Type *base, sdhc_handle_t *handle, uint /*! * @brief Handle SDIO card interrupt signal. * + * @param base SDHC peripheral base address. * @param handle SDHC handle. */ -static void SDHC_TransferHandleSdioInterrupt(sdhc_handle_t *handle); +static void SDHC_TransferHandleSdioInterrupt(SDHC_Type *base, sdhc_handle_t *handle); /*! * @brief Handle SDIO block gap event. * + * @param base SDHC peripheral base address. * @param handle SDHC handle. */ -static void SDHC_TransferHandleSdioBlockGap(sdhc_handle_t *handle); +static void SDHC_TransferHandleSdioBlockGap(SDHC_Type *base, sdhc_handle_t *handle); /******************************************************************************* * Variables @@ -325,7 +312,15 @@ static void SDHC_StartTransfer(SDHC_Type *base, sdhc_command_t *command, sdhc_da if (dmaMode != kSDHC_DmaModeNo) { flags |= kSDHC_EnableDmaFlag; + base->IRQSIGEN &= ~(kSDHC_BufferWriteReadyFlag | kSDHC_BufferReadReadyFlag | kSDHC_DmaCompleteFlag); + base->IRQSTATEN &= ~(kSDHC_BufferWriteReadyFlag | kSDHC_BufferReadReadyFlag | kSDHC_DmaCompleteFlag); } + else + { + base->IRQSIGEN |= kSDHC_BufferWriteReadyFlag | kSDHC_BufferReadReadyFlag; + base->IRQSTATEN |= kSDHC_BufferWriteReadyFlag | kSDHC_BufferReadReadyFlag; + } + if (data->rxData) { flags |= kSDHC_DataReadFlag; @@ -684,20 +679,20 @@ static status_t SDHC_TransferDataBlocking(sdhc_dma_mode_t dmaMode, SDHC_Type *ba return error; } -static void SDHC_TransferHandleCardDetect(sdhc_handle_t *handle, uint32_t interruptFlags) +static void SDHC_TransferHandleCardDetect(SDHC_Type *base, sdhc_handle_t *handle, uint32_t interruptFlags) { if (interruptFlags & kSDHC_CardInsertionFlag) { if (handle->callback.CardInserted) { - handle->callback.CardInserted(); + handle->callback.CardInserted(base, handle->userData); } } else { if (handle->callback.CardRemoved) { - handle->callback.CardRemoved(); + handle->callback.CardRemoved(base, handle->userData); } } } @@ -755,22 +750,42 @@ static void SDHC_TransferHandleData(SDHC_Type *base, sdhc_handle_t *handle, uint } } -static void SDHC_TransferHandleSdioInterrupt(sdhc_handle_t *handle) +static void SDHC_TransferHandleSdioInterrupt(SDHC_Type *base, sdhc_handle_t *handle) { if (handle->callback.SdioInterrupt) { - handle->callback.SdioInterrupt(); + handle->callback.SdioInterrupt(base, handle->userData); } } -static void SDHC_TransferHandleSdioBlockGap(sdhc_handle_t *handle) +static void SDHC_TransferHandleSdioBlockGap(SDHC_Type *base, sdhc_handle_t *handle) { if (handle->callback.SdioBlockGap) { - handle->callback.SdioBlockGap(); + handle->callback.SdioBlockGap(base, handle->userData); } } +/*! + * brief SDHC module initialization function. + * + * Configures the SDHC according to the user configuration. + * + * Example: + code + sdhc_config_t config; + config.cardDetectDat3 = false; + config.endianMode = kSDHC_EndianModeLittle; + config.dmaMode = kSDHC_DmaModeAdma2; + config.readWatermarkLevel = 128U; + config.writeWatermarkLevel = 128U; + SDHC_Init(SDHC, &config); + endcode + * + * param base SDHC peripheral base address. + * param config SDHC configuration information. + * retval kStatus_Success Operate successfully. + */ void SDHC_Init(SDHC_Type *base, const sdhc_config_t *config) { assert(config); @@ -818,6 +833,11 @@ void SDHC_Init(SDHC_Type *base, const sdhc_config_t *config) SDHC_SetTransferInterrupt(base, false); } +/*! + * brief Deinitializes the SDHC. + * + * param base SDHC peripheral base address. + */ void SDHC_Deinit(SDHC_Type *base) { #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) @@ -826,6 +846,15 @@ void SDHC_Deinit(SDHC_Type *base) #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ } +/*! + * brief Resets the SDHC. + * + * param base SDHC peripheral base address. + * param mask The reset type mask(_sdhc_reset). + * param timeout Timeout for reset. + * retval true Reset successfully. + * retval false Reset failed. + */ bool SDHC_Reset(SDHC_Type *base, uint32_t mask, uint32_t timeout) { base->SYSCTL |= (mask & (SDHC_SYSCTL_RSTA_MASK | SDHC_SYSCTL_RSTC_MASK | SDHC_SYSCTL_RSTD_MASK)); @@ -842,6 +871,12 @@ bool SDHC_Reset(SDHC_Type *base, uint32_t mask, uint32_t timeout) return ((!timeout) ? false : true); } +/*! + * brief Gets the capability information. + * + * param base SDHC peripheral base address. + * param capability Structure to save capability information. + */ void SDHC_GetCapability(SDHC_Type *base, sdhc_capability_t *capability) { assert(capability); @@ -872,6 +907,15 @@ void SDHC_GetCapability(SDHC_Type *base, sdhc_capability_t *capability) capability->flags |= (kSDHC_Support4BitFlag | kSDHC_Support8BitFlag); } +/*! + * brief Sets the SD bus clock frequency. + * + * param base SDHC peripheral base address. + * param srcClock_Hz SDHC source clock frequency united in Hz. + * param busClock_Hz SD bus clock frequency united in Hz. + * + * return The nearest frequency of busClock_Hz configured to SD bus. + */ uint32_t SDHC_SetSdClock(SDHC_Type *base, uint32_t srcClock_Hz, uint32_t busClock_Hz) { assert(srcClock_Hz != 0U); @@ -884,7 +928,10 @@ uint32_t SDHC_SetSdClock(SDHC_Type *base, uint32_t srcClock_Hz, uint32_t busCloc uint32_t nearestFrequency = 0U; /* calucate total divisor first */ - totalDiv = srcClock_Hz / busClock_Hz; + if ((totalDiv = srcClock_Hz / busClock_Hz) > (SDHC_MAX_CLKFS * SDHC_MAX_DVS)) + { + return 0U; + } if (totalDiv != 0U) { @@ -910,7 +957,8 @@ uint32_t SDHC_SetSdClock(SDHC_Type *base, uint32_t srcClock_Hz, uint32_t busCloc { divisor++; } - nearestFrequency = srcClock_Hz / divisor / prescaler; + + nearestFrequency = srcClock_Hz / (divisor == 0U ? 1U : divisor) / prescaler; } else { @@ -958,6 +1006,17 @@ uint32_t SDHC_SetSdClock(SDHC_Type *base, uint32_t srcClock_Hz, uint32_t busCloc return nearestFrequency; } +/*! + * brief Sends 80 clocks to the card to set it to the active state. + * + * This function must be called each time the card is inserted to ensure that the card can receive the command + * correctly. + * + * param base SDHC peripheral base address. + * param timeout Timeout to initialize card. + * retval true Set card active successfully. + * retval false Set card active failed. + */ bool SDHC_SetCardActive(SDHC_Type *base, uint32_t timeout) { base->SYSCTL |= SDHC_SYSCTL_INITA_MASK; @@ -974,6 +1033,27 @@ bool SDHC_SetCardActive(SDHC_Type *base, uint32_t timeout) return ((!timeout) ? false : true); } +/*! + * brief Sets the card transfer-related configuration. + * + * This function fills the card transfer-related command argument/transfer flag/data size. The command and data are sent + by + * SDHC after calling this function. + * + * Example: + code + sdhc_transfer_config_t transferConfig; + transferConfig.dataBlockSize = 512U; + transferConfig.dataBlockCount = 2U; + transferConfig.commandArgument = 0x01AAU; + transferConfig.commandIndex = 8U; + transferConfig.flags |= (kSDHC_EnableDmaFlag | kSDHC_EnableAutoCommand12Flag | kSDHC_MultipleBlockFlag); + SDHC_SetTransferConfig(SDHC, &transferConfig); + endcode + * + * param base SDHC peripheral base address. + * param config Command configuration structure. + */ void SDHC_SetTransferConfig(SDHC_Type *base, const sdhc_transfer_config_t *config) { assert(config); @@ -990,6 +1070,13 @@ void SDHC_SetTransferConfig(SDHC_Type *base, const sdhc_transfer_config_t *confi SDHC_XFERTYP_AC12EN_MASK))); } +/*! + * brief Enables or disables the SDIO card control. + * + * param base SDHC peripheral base address. + * param mask SDIO card control flags mask(_sdhc_sdio_control_flag). + * param enable True to enable, false to disable. + */ void SDHC_EnableSdioControl(SDHC_Type *base, uint32_t mask, bool enable) { uint32_t proctl = base->PROCTL; @@ -1038,6 +1125,24 @@ void SDHC_EnableSdioControl(SDHC_Type *base, uint32_t mask, bool enable) base->VENDOR = vendor; } +/*! + * brief Configures the MMC boot feature. + * + * Example: + code + sdhc_boot_config_t config; + config.ackTimeoutCount = 4; + config.bootMode = kSDHC_BootModeNormal; + config.blockCount = 5; + config.enableBootAck = true; + config.enableBoot = true; + config.enableAutoStopAtBlockGap = true; + SDHC_SetMmcBootConfig(SDHC, &config); + endcode + * + * param base SDHC peripheral base address. + * param config The MMC boot configuration information. + */ void SDHC_SetMmcBootConfig(SDHC_Type *base, const sdhc_boot_config_t *config) { assert(config); @@ -1063,6 +1168,18 @@ void SDHC_SetMmcBootConfig(SDHC_Type *base, const sdhc_boot_config_t *config) base->MMCBOOT = mmcboot; } +/*! + * brief Sets the ADMA descriptor table configuration. + * + * param base SDHC peripheral base address. + * param dmaMode DMA mode. + * param table ADMA table address. + * param tableWords ADMA table buffer length united as Words. + * param data Data buffer address. + * param dataBytes Data length united as bytes. + * retval kStatus_OutOfRange ADMA descriptor table length isn't enough to describe data. + * retval kStatus_Success Operate successfully. + */ status_t SDHC_SetAdmaTableConfig(SDHC_Type *base, sdhc_dma_mode_t dmaMode, uint32_t *table, @@ -1136,8 +1253,7 @@ status_t SDHC_SetAdmaTableConfig(SDHC_Type *base, adma1EntryAddress[i] = ((uint32_t)(dataBytes - sizeof(uint32_t) * (startAddress - data)) << SDHC_ADMA1_DESCRIPTOR_LENGTH_SHIFT); adma1EntryAddress[i] |= kSDHC_Adma1DescriptorTypeSetLength; - adma1EntryAddress[i + 1U] = - ((uint32_t)(startAddress) << SDHC_ADMA1_DESCRIPTOR_ADDRESS_SHIFT); + adma1EntryAddress[i + 1U] = (uint32_t)(startAddress); adma1EntryAddress[i + 1U] |= (kSDHC_Adma1DescriptorTypeTransfer | kSDHC_Adma1DescriptorEndFlag); } @@ -1156,9 +1272,6 @@ status_t SDHC_SetAdmaTableConfig(SDHC_Type *base, /* When use ADMA, disable simple DMA */ base->DSADDR = 0U; base->ADSADDR = (uint32_t)table; - /* disable the buffer ready flag in DMA mode */ - SDHC_DisableInterruptSignal(base, kSDHC_BufferReadReadyFlag | kSDHC_BufferWriteReadyFlag); - SDHC_DisableInterruptStatus(base, kSDHC_BufferReadReadyFlag | kSDHC_BufferWriteReadyFlag); } break; #endif /* FSL_SDHC_ENABLE_ADMA1 */ @@ -1210,9 +1323,6 @@ status_t SDHC_SetAdmaTableConfig(SDHC_Type *base, /* When use ADMA, disable simple DMA */ base->DSADDR = 0U; base->ADSADDR = (uint32_t)table; - /* disable the buffer read flag in DMA mode */ - SDHC_DisableInterruptSignal(base, kSDHC_BufferReadReadyFlag | kSDHC_BufferWriteReadyFlag); - SDHC_DisableInterruptStatus(base, kSDHC_BufferReadReadyFlag | kSDHC_BufferWriteReadyFlag); } break; default: @@ -1223,6 +1333,28 @@ status_t SDHC_SetAdmaTableConfig(SDHC_Type *base, return error; } +/*! + * brief Transfers the command/data using a blocking method. + * + * This function waits until the command response/data is received or the SDHC encounters an error by polling the status + * flag. + * This function support non word align data addr transfer support, if data buffer addr is not align in DMA mode, + * the API will continue finish the transfer by polling IO directly + * The application must not call this API in multiple threads at the same time. Because of that this API doesn't support + * the re-entry mechanism. + * + * note There is no need to call the API 'SDHC_TransferCreateHandle' when calling this API. + * + * param base SDHC peripheral base address. + * param admaTable ADMA table address, can't be null if transfer way is ADMA1/ADMA2. + * param admaTableWords ADMA table length united as words, can't be 0 if transfer way is ADMA1/ADMA2. + * param transfer Transfer content. + * retval kStatus_InvalidArgument Argument is invalid. + * retval kStatus_SDHC_PrepareAdmaDescriptorFailed Prepare ADMA descriptor failed. + * retval kStatus_SDHC_SendCommandFailed Send command failed. + * retval kStatus_SDHC_TransferDataFailed Transfer data failed. + * retval kStatus_Success Operate successfully. + */ status_t SDHC_TransferBlocking(SDHC_Type *base, uint32_t *admaTable, uint32_t admaTableWords, sdhc_transfer_t *transfer) { assert(transfer); @@ -1253,37 +1385,36 @@ status_t SDHC_TransferBlocking(SDHC_Type *base, uint32_t *admaTable, uint32_t ad SDHC_SetAdmaTableConfig(base, dmaMode, admaTable, admaTableWords, (data->rxData ? data->rxData : data->txData), (data->blockCount * data->blockSize)); /* in this situation , we disable the DMA instead of polling transfer mode */ - if (error == kStatus_SDHC_DMADataBufferAddrNotAlign) + if (error != kStatus_Success) { dmaMode = kSDHC_DmaModeNo; - SDHC_EnableInterruptStatus(base, kSDHC_BufferReadReadyFlag | kSDHC_BufferWriteReadyFlag); - } - else if (error != kStatus_Success) - { - return error; - } - else - { } } /* Send command and receive data. */ SDHC_StartTransfer(base, command, data, dmaMode); + if (kStatus_Success != SDHC_SendCommandBlocking(base, command)) { return kStatus_SDHC_SendCommandFailed; } - else if (data && (kStatus_Success != SDHC_TransferDataBlocking(dmaMode, base, data))) + + if (data && (kStatus_Success != SDHC_TransferDataBlocking(dmaMode, base, data))) { return kStatus_SDHC_TransferDataFailed; } - else - { - } return kStatus_Success; } +/*! + * brief Creates the SDHC handle. + * + * param base SDHC peripheral base address. + * param handle SDHC handle pointer. + * param callback Structure pointer to contain all callback functions. + * param userData Callback function parameter. + */ void SDHC_TransferCreateHandle(SDHC_Type *base, sdhc_handle_t *handle, const sdhc_transfer_callback_t *callback, @@ -1315,6 +1446,28 @@ void SDHC_TransferCreateHandle(SDHC_Type *base, EnableIRQ(s_sdhcIRQ[SDHC_GetInstance(base)]); } +/*! + * brief Transfers the command/data using an interrupt and an asynchronous method. + * + * This function sends a command and data and returns immediately. It doesn't wait the transfer complete or encounter an + * error. + * This function support non word align data addr transfer support, if data buffer addr is not align in DMA mode, + * the API will continue finish the transfer by polling IO directly + * The application must not call this API in multiple threads at the same time. Because of that this API doesn't support + * the re-entry mechanism. + * + * note Call the API 'SDHC_TransferCreateHandle' when calling this API. + * + * param base SDHC peripheral base address. + * param handle SDHC handle. + * param admaTable ADMA table address, can't be null if transfer way is ADMA1/ADMA2. + * param admaTableWords ADMA table length united as words, can't be 0 if transfer way is ADMA1/ADMA2. + * param transfer Transfer content. + * retval kStatus_InvalidArgument Argument is invalid. + * retval kStatus_SDHC_BusyTransferring Busy transferring. + * retval kStatus_SDHC_PrepareAdmaDescriptorFailed Prepare ADMA descriptor failed. + * retval kStatus_Success Operate successfully. + */ status_t SDHC_TransferNonBlocking( SDHC_Type *base, sdhc_handle_t *handle, uint32_t *admaTable, uint32_t admaTableWords, sdhc_transfer_t *transfer) { @@ -1345,19 +1498,10 @@ status_t SDHC_TransferNonBlocking( SDHC_SetAdmaTableConfig(base, dmaMode, admaTable, admaTableWords, (data->rxData ? data->rxData : data->txData), (data->blockCount * data->blockSize)); /* in this situation , we disable the DMA instead of polling transfer mode */ - if (error == kStatus_SDHC_DMADataBufferAddrNotAlign) + if (error != kStatus_Success) { /* change to polling mode */ dmaMode = kSDHC_DmaModeNo; - SDHC_EnableInterruptSignal(base, kSDHC_BufferReadReadyFlag | kSDHC_BufferWriteReadyFlag); - SDHC_EnableInterruptStatus(base, kSDHC_BufferReadReadyFlag | kSDHC_BufferWriteReadyFlag); - } - else if (error != kStatus_Success) - { - return error; - } - else - { } } @@ -1373,6 +1517,14 @@ status_t SDHC_TransferNonBlocking( return kStatus_Success; } +/*! + * brief IRQ handler for the SDHC. + * + * This function deals with the IRQs on the given host controller. + * + * param base SDHC peripheral base address. + * param handle SDHC handle. + */ void SDHC_TransferHandleIRQ(SDHC_Type *base, sdhc_handle_t *handle) { assert(handle); @@ -1384,7 +1536,7 @@ void SDHC_TransferHandleIRQ(SDHC_Type *base, sdhc_handle_t *handle) if (interruptFlags & kSDHC_CardDetectFlag) { - SDHC_TransferHandleCardDetect(handle, (interruptFlags & kSDHC_CardDetectFlag)); + SDHC_TransferHandleCardDetect(base, handle, (interruptFlags & kSDHC_CardDetectFlag)); } if (interruptFlags & kSDHC_CommandFlag) { @@ -1396,11 +1548,11 @@ void SDHC_TransferHandleIRQ(SDHC_Type *base, sdhc_handle_t *handle) } if (interruptFlags & kSDHC_CardInterruptFlag) { - SDHC_TransferHandleSdioInterrupt(handle); + SDHC_TransferHandleSdioInterrupt(base, handle); } if (interruptFlags & kSDHC_BlockGapEventFlag) { - SDHC_TransferHandleSdioBlockGap(handle); + SDHC_TransferHandleSdioBlockGap(base, handle); } SDHC_ClearInterruptStatusFlags(base, interruptFlags); @@ -1412,5 +1564,10 @@ void SDHC_DriverIRQHandler(void) assert(s_sdhcHandle[0]); s_sdhcIsr(SDHC, s_sdhcHandle[0]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif } #endif diff --git a/ext/hal/nxp/mcux/drivers/kinetis/fsl_sdhc.h b/ext/hal/nxp/mcux/drivers/kinetis/fsl_sdhc.h index 336b9618e5b..52dc86d1acb 100644 --- a/ext/hal/nxp/mcux/drivers/kinetis/fsl_sdhc.h +++ b/ext/hal/nxp/mcux/drivers/kinetis/fsl_sdhc.h @@ -1,31 +1,9 @@ /* * Copyright (c) 2015, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP + * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * SPDX-License-Identifier: BSD-3-Clause */ #ifndef _FSL_SDHC_H_ #define _FSL_SDHC_H_ @@ -43,8 +21,8 @@ /*! @name Driver version */ /*@{*/ -/*! @brief Driver version 2.1.5. */ -#define FSL_SDHC_DRIVER_VERSION (MAKE_VERSION(2U, 1U, 5U)) +/*! @brief Driver version 2.1.8. */ +#define FSL_SDHC_DRIVER_VERSION (MAKE_VERSION(2U, 1U, 8U)) /*@}*/ /*! @brief Maximum block count can be set one time */ @@ -137,14 +115,15 @@ enum _sdhc_present_status_flag kSDHC_BufferReadEnableFlag = SDHC_PRSSTAT_BREN_MASK, /*!< Buffer read enable */ kSDHC_CardInsertedFlag = SDHC_PRSSTAT_CINS_MASK, /*!< Card inserted */ kSDHC_CommandLineLevelFlag = SDHC_PRSSTAT_CLSL_MASK, /*!< Command line signal level */ - kSDHC_Data0LineLevelFlag = (1U << 24U), /*!< Data0 line signal level */ - kSDHC_Data1LineLevelFlag = (1U << 25U), /*!< Data1 line signal level */ - kSDHC_Data2LineLevelFlag = (1U << 26U), /*!< Data2 line signal level */ - kSDHC_Data3LineLevelFlag = (1U << 27U), /*!< Data3 line signal level */ - kSDHC_Data4LineLevelFlag = (1U << 28U), /*!< Data4 line signal level */ - kSDHC_Data5LineLevelFlag = (1U << 29U), /*!< Data5 line signal level */ - kSDHC_Data6LineLevelFlag = (1U << 30U), /*!< Data6 line signal level */ - kSDHC_Data7LineLevelFlag = (1U << 31U), /*!< Data7 line signal level */ + + kSDHC_Data0LineLevelFlag = (1U << 24U), /*!< Data0 line signal level */ + kSDHC_Data1LineLevelFlag = (1U << 25U), /*!< Data1 line signal level */ + kSDHC_Data2LineLevelFlag = (1U << 26U), /*!< Data2 line signal level */ + kSDHC_Data3LineLevelFlag = (1U << 27U), /*!< Data3 line signal level */ + kSDHC_Data4LineLevelFlag = (1U << 28U), /*!< Data4 line signal level */ + kSDHC_Data5LineLevelFlag = (1U << 29U), /*!< Data5 line signal level */ + kSDHC_Data6LineLevelFlag = (1U << 30U), /*!< Data6 line signal level */ + kSDHC_Data7LineLevelFlag = (int)(1U << 31U), /*!< Data7 line signal level */ }; /*! @brief Interrupt status flag mask */ @@ -214,7 +193,7 @@ typedef enum _sdhc_adma_error_state kSDHC_AdmaErrorStateTransferData = 0x03U, /*!< Transfer data */ } sdhc_adma_error_state_t; -/*! @brief Force event mask */ +/*! @brief Force event bit position */ enum _sdhc_force_event { kSDHC_ForceEventAutoCommand12NotExecuted = SDHC_FEVT_AC12NE_MASK, /*!< Auto CMD12 not executed error */ @@ -231,16 +210,14 @@ enum _sdhc_force_event kSDHC_ForceEventDataCrcError = SDHC_FEVT_DCE_MASK, /*!< Data CRC error */ kSDHC_ForceEventDataEndBitError = SDHC_FEVT_DEBE_MASK, /*!< Data end bit error */ kSDHC_ForceEventAutoCommand12Error = SDHC_FEVT_AC12E_MASK, /*!< Auto CMD12 error */ - kSDHC_ForceEventCardInt = SDHC_FEVT_CINT_MASK, /*!< Card interrupt */ + kSDHC_ForceEventCardInt = (int)SDHC_FEVT_CINT_MASK, /*!< Card interrupt */ kSDHC_ForceEventDmaError = SDHC_FEVT_DMAE_MASK, /*!< Dma error */ - kSDHC_ForceEventsAll = - (kSDHC_ForceEventAutoCommand12NotExecuted | kSDHC_ForceEventAutoCommand12Timeout | - kSDHC_ForceEventAutoCommand12CrcError | kSDHC_ForceEventEndBitError | kSDHC_ForceEventAutoCommand12IndexError | - kSDHC_ForceEventAutoCommand12NotIssued | kSDHC_ForceEventCommandTimeout | kSDHC_ForceEventCommandCrcError | - kSDHC_ForceEventCommandEndBitError | kSDHC_ForceEventCommandIndexError | kSDHC_ForceEventDataTimeout | - kSDHC_ForceEventDataCrcError | kSDHC_ForceEventDataEndBitError | kSDHC_ForceEventAutoCommand12Error | - kSDHC_ForceEventCardInt | kSDHC_ForceEventDmaError), /*!< All force event flags mask */ + kSDHC_ForceEventsAll = (int)(SDHC_FEVT_AC12NE_MASK | SDHC_FEVT_AC12TOE_MASK | SDHC_FEVT_AC12CE_MASK | + SDHC_FEVT_AC12EBE_MASK | SDHC_FEVT_AC12IE_MASK | SDHC_FEVT_CNIBAC12E_MASK | + SDHC_FEVT_CTOE_MASK | SDHC_FEVT_CCE_MASK | SDHC_FEVT_CEBE_MASK | SDHC_FEVT_CIE_MASK | + SDHC_FEVT_DTOE_MASK | SDHC_FEVT_DCE_MASK | SDHC_FEVT_DEBE_MASK | SDHC_FEVT_AC12E_MASK | + SDHC_FEVT_CINT_MASK | SDHC_FEVT_DMAE_MASK), /*!< All force event flags mask */ }; /*! @brief Data transfer width */ @@ -522,10 +499,11 @@ typedef struct _sdhc_handle sdhc_handle_t; /*! @brief SDHC callback functions. */ typedef struct _sdhc_transfer_callback { - void (*CardInserted)(void); /*!< Card inserted occurs when DAT3/CD pin is for card detect */ - void (*CardRemoved)(void); /*!< Card removed occurs */ - void (*SdioInterrupt)(void); /*!< SDIO card interrupt occurs */ - void (*SdioBlockGap)(void); /*!< SDIO card stopped at block gap occurs */ + void (*CardInserted)(SDHC_Type *base, + void *userData); /*!< Card inserted occurs when DAT3/CD pin is for card detect */ + void (*CardRemoved)(SDHC_Type *base, void *userData); /*!< Card removed occurs */ + void (*SdioInterrupt)(SDHC_Type *base, void *userData); /*!< SDIO card interrupt occurs */ + void (*SdioBlockGap)(SDHC_Type *base, void *userData); /*!< SDIO card stopped at block gap occurs */ void (*TransferComplete)(SDHC_Type *base, sdhc_handle_t *handle, status_t status, @@ -830,6 +808,24 @@ static inline void SDHC_SetDataBusWidth(SDHC_Type *base, sdhc_data_bus_width_t w base->PROCTL = ((base->PROCTL & ~SDHC_PROCTL_DTW_MASK) | SDHC_PROCTL_DTW(width)); } +/*! + * @brief detect card insert status. + * + * @param base SDHC peripheral base address. + * @param enable/disable flag + */ +static inline void SDHC_CardDetectByData3(SDHC_Type *base, bool enable) +{ + if (enable) + { + base->PROCTL |= SDHC_PROCTL_D3CD_MASK; + } + else + { + base->PROCTL &= ~SDHC_PROCTL_D3CD_MASK; + } +} + /*! * @brief Sets the card transfer-related configuration. * @@ -868,7 +864,7 @@ static inline uint32_t SDHC_GetCommandResponse(SDHC_Type *base, uint32_t index) } /*! - * @brief Fills the the data port. + * @brief Fills the data port. * * This function is used to implement the data transfer by Data Port instead of DMA. * diff --git a/ext/hal/nxp/mcux/drivers/kinetis/fsl_sim.c b/ext/hal/nxp/mcux/drivers/kinetis/fsl_sim.c old mode 100644 new mode 100755 index ade512f0306..5a613c55a1f --- a/ext/hal/nxp/mcux/drivers/kinetis/fsl_sim.c +++ b/ext/hal/nxp/mcux/drivers/kinetis/fsl_sim.c @@ -1,39 +1,35 @@ /* * Copyright (c) 2015, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP + * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * SPDX-License-Identifier: BSD-3-Clause */ #include "fsl_sim.h" +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.sim" +#endif + /******************************************************************************* * Codes ******************************************************************************/ #if (defined(FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR) && FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR) +/*! + * brief Sets the USB voltage regulator setting. + * + * This function configures whether the USB voltage regulator is enabled in + * normal RUN mode, STOP/VLPS/LLS/VLLS modes, and VLPR/VLPW modes. The configurations + * are passed in as mask value of \ref _sim_usb_volt_reg_enable_mode. For example, to enable + * USB voltage regulator in RUN/VLPR/VLPW modes and disable in STOP/VLPS/LLS/VLLS mode, + * use: + * + * SIM_SetUsbVoltRegulatorEnableMode(kSIM_UsbVoltRegEnable | kSIM_UsbVoltRegEnableInLowPower); + * + * param mask USB voltage regulator enable setting. + */ void SIM_SetUsbVoltRegulatorEnableMode(uint32_t mask) { SIM->SOPT1CFG |= (SIM_SOPT1CFG_URWE_MASK | SIM_SOPT1CFG_UVSWE_MASK | SIM_SOPT1CFG_USSWE_MASK); @@ -42,12 +38,34 @@ void SIM_SetUsbVoltRegulatorEnableMode(uint32_t mask) } #endif /* FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR */ +/*! + * brief Gets the unique identification register value. + * + * param uid Pointer to the structure to save the UID value. + */ void SIM_GetUniqueId(sim_uid_t *uid) { #if defined(SIM_UIDH) uid->H = SIM->UIDH; #endif +#if (defined(FSL_FEATURE_SIM_HAS_UIDM) && FSL_FEATURE_SIM_HAS_UIDM) + uid->M = SIM->UIDM; +#else uid->MH = SIM->UIDMH; uid->ML = SIM->UIDML; +#endif /* FSL_FEATURE_SIM_HAS_UIDM */ uid->L = SIM->UIDL; } + +#if (defined(FSL_FEATURE_SIM_HAS_RF_MAC_ADDR) && FSL_FEATURE_SIM_HAS_RF_MAC_ADDR) +/*! + * brief Gets the RF address register value. + * + * param info Pointer to the structure to save the RF address value. + */ +void SIM_GetRfAddr(sim_rf_addr_t *info) +{ + info->rfAddrL = SIM->RFADDRL; + info->rfAddrH = SIM->RFADDRH; +} +#endif /* FSL_FEATURE_SIM_HAS_RF_MAC_ADDR */ diff --git a/ext/hal/nxp/mcux/drivers/kinetis/fsl_sim.h b/ext/hal/nxp/mcux/drivers/kinetis/fsl_sim.h old mode 100644 new mode 100755 index 0a0e4fb3092..c49ff3dc6be --- a/ext/hal/nxp/mcux/drivers/kinetis/fsl_sim.h +++ b/ext/hal/nxp/mcux/drivers/kinetis/fsl_sim.h @@ -1,31 +1,9 @@ /* * Copyright (c) 2015, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP + * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * SPDX-License-Identifier: BSD-3-Clause */ #ifndef _FSL_SIM_H_ @@ -36,25 +14,25 @@ /*! @addtogroup sim */ /*! @{*/ - /******************************************************************************* * Definitions *******************************************************************************/ /*! @name Driver version */ /*@{*/ -#define FSL_SIM_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Driver version 2.0.0 */ +#define FSL_SIM_DRIVER_VERSION (MAKE_VERSION(2, 1, 0)) /*!< Driver version 2.0.0 */ /*@}*/ #if (defined(FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR) && FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR) /*!@brief USB voltage regulator enable setting. */ enum _sim_usb_volt_reg_enable_mode { - kSIM_UsbVoltRegEnable = SIM_SOPT1_USBREGEN_MASK, /*!< Enable voltage regulator. */ + kSIM_UsbVoltRegEnable = (int)SIM_SOPT1_USBREGEN_MASK, /*!< Enable voltage regulator. */ kSIM_UsbVoltRegEnableInLowPower = SIM_SOPT1_USBVSTBY_MASK, /*!< Enable voltage regulator in VLPR/VLPW modes. */ kSIM_UsbVoltRegEnableInStop = SIM_SOPT1_USBSSTBY_MASK, /*!< Enable voltage regulator in STOP/VLPS/LLS/VLLS modes. */ - kSIM_UsbVoltRegEnableInAllModes = SIM_SOPT1_USBREGEN_MASK | SIM_SOPT1_USBSSTBY_MASK | - SIM_SOPT1_USBVSTBY_MASK /*!< Enable voltage regulator in all power modes. */ + kSIM_UsbVoltRegEnableInAllModes = + (int)(SIM_SOPT1_USBREGEN_MASK | SIM_SOPT1_USBSSTBY_MASK | + SIM_SOPT1_USBVSTBY_MASK) /*!< Enable voltage regulator in all power modes. */ }; #endif /* (defined(FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR) && FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR) */ @@ -64,11 +42,25 @@ typedef struct _sim_uid #if defined(SIM_UIDH) uint32_t H; /*!< UIDH. */ #endif + +#if (defined(FSL_FEATURE_SIM_HAS_UIDM) && FSL_FEATURE_SIM_HAS_UIDM) + uint32_t M; /*!< SIM_UIDM. */ +#else uint32_t MH; /*!< UIDMH. */ uint32_t ML; /*!< UIDML. */ - uint32_t L; /*!< UIDL. */ +#endif /* FSL_FEATURE_SIM_HAS_UIDM */ + uint32_t L; /*!< UIDL. */ } sim_uid_t; +#if (defined(FSL_FEATURE_SIM_HAS_RF_MAC_ADDR) && FSL_FEATURE_SIM_HAS_RF_MAC_ADDR) +/*! @brief RF Mac Address.*/ +typedef struct _sim_rf_addr +{ + uint32_t rfAddrL; /*!< RFADDRL. */ + uint32_t rfAddrH; /*!< RFADDRH. */ +} sim_rf_addr_t; +#endif /* FSL_FEATURE_SIM_HAS_RF_MAC_ADDR */ + /*!@brief Flash enable mode. */ enum _sim_flash_mode { @@ -118,6 +110,38 @@ static inline void SIM_SetFlashMode(uint8_t mode) SIM->FCFG1 = mode; } +#if (defined(FSL_FEATURE_SIM_HAS_RF_MAC_ADDR) && FSL_FEATURE_SIM_HAS_RF_MAC_ADDR) +/*! + * @brief Gets the RF address register value. + * + * @param info Pointer to the structure to save the RF address value. + */ +void SIM_GetRfAddr(sim_rf_addr_t *info); +#endif /* FSL_FEATURE_SIM_HAS_RF_MAC_ADDR */ + +#if (defined(FSL_FEATURE_SIM_MISC2_HAS_SYSTICK_CLK_EN) && FSL_FEATURE_SIM_MISC2_HAS_SYSTICK_CLK_EN) + +/*! + * @brief Enable the Systick clock or not. + * + * The Systick clock is enabled by default. + * + * @param enable The switcher for Systick clock. + */ +static inline void SIM_EnableSystickClock(bool enable) +{ + if (enable) + { + SIM->MISC2 &= ~SIM_MISC2_SYSTICK_CLK_EN_MASK; /* Clear to enable. */ + } + else + { + SIM->MISC2 |= SIM_MISC2_SYSTICK_CLK_EN_MASK; /* Set to disable. */ + } +} + +#endif /* FSL_FEATURE_SIM_MISC2_HAS_SYSTICK_CLK_EN */ + #if defined(__cplusplus) } #endif /* __cplusplus*/ diff --git a/ext/hal/nxp/mcux/drivers/kinetis/fsl_smc.c b/ext/hal/nxp/mcux/drivers/kinetis/fsl_smc.c index dacf193476c..ccbe4a6a1f8 100644 --- a/ext/hal/nxp/mcux/drivers/kinetis/fsl_smc.c +++ b/ext/hal/nxp/mcux/drivers/kinetis/fsl_smc.c @@ -1,37 +1,86 @@ /* * Copyright (c) 2015, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP + * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * SPDX-License-Identifier: BSD-3-Clause */ #include "fsl_smc.h" -#include "fsl_flash.h" +#include "fsl_common.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.smc" +#endif + +typedef void (*smc_stop_ram_func_t)(void); + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +static void SMC_EnterStopRamFunc(void); + +/******************************************************************************* + * Variables + ******************************************************************************/ +static uint32_t g_savedPrimask; + +/* + * The ram function code is: + * + * uint32_t i; + * for (i=0; i<0x8; i++) + * { + * __NOP(); + * } + * __DSB(); + * __WFI(); + * __ISB(); + * + * When entring the stop modes, the flash prefetch might be interrupted, thus + * the prefetched code or data might be broken. To make sure the flash is idle + * when entring the stop modes, the code is moved to ram. And delay for a while + * before WFI to make sure previous flash prefetch is finished. + * + * Only need to do like this when code is in flash, if code is in rom or ram, + * this is not necessary. + */ +static uint16_t s_stopRamFuncArray[] = { + 0x2000, /* MOVS R0, #0 */ + 0x2808, /* CMP R0, #8 */ + 0xD202, /* BCS.N */ + 0xBF00, /* NOP */ + 0x1C40, /* ADDS R0, R0, #1 */ + 0xE7FA, /* B.N */ + 0xF3BF, 0x8F4F, /* DSB */ + 0xBF30, /* WFI */ + 0xF3BF, 0x8F6F, /* ISB */ + 0x4770, /* BX LR */ +}; + +/******************************************************************************* + * Code + ******************************************************************************/ +static void SMC_EnterStopRamFunc(void) +{ + uint32_t ramFuncEntry = ((uint32_t)(s_stopRamFuncArray)) + 1U; + smc_stop_ram_func_t stopRamFunc = (smc_stop_ram_func_t)ramFuncEntry; + stopRamFunc(); +} #if (defined(FSL_FEATURE_SMC_HAS_PARAM) && FSL_FEATURE_SMC_HAS_PARAM) +/*! + * brief Gets the SMC parameter. + * + * This function gets the SMC parameter including the enabled power mdoes. + * + * param base SMC peripheral base address. + * param param Pointer to the SMC param structure. + */ void SMC_GetParam(SMC_Type *base, smc_param_t *param) { uint32_t reg = base->PARAM; @@ -42,39 +91,58 @@ void SMC_GetParam(SMC_Type *base, smc_param_t *param) } #endif /* FSL_FEATURE_SMC_HAS_PARAM */ +/*! + * brief Prepares to enter stop modes. + * + * This function should be called before entering STOP/VLPS/LLS/VLLS modes. + */ void SMC_PreEnterStopModes(void) { - flash_prefetch_speculation_status_t speculationStatus = - { - kFLASH_prefetchSpeculationOptionDisable, /* Disable instruction speculation.*/ - kFLASH_prefetchSpeculationOptionDisable, /* Disable data speculation.*/ - }; - - __disable_irq(); + g_savedPrimask = DisableGlobalIRQ(); __ISB(); - - /* - * Before enter stop modes, the flash cache prefetch should be disabled. - * Otherwise the prefetch might be interrupted by stop, then the data and - * and instruction from flash are wrong. - */ - FLASH_PflashSetPrefetchSpeculation(&speculationStatus); } +/*! + * brief Recovers after wake up from stop modes. + * + * This function should be called after wake up from STOP/VLPS/LLS/VLLS modes. + * It is used with ref SMC_PreEnterStopModes. + */ void SMC_PostExitStopModes(void) { - flash_prefetch_speculation_status_t speculationStatus = - { - kFLASH_prefetchSpeculationOptionEnable, /* Enable instruction speculation.*/ - kFLASH_prefetchSpeculationOptionEnable, /* Enable data speculation.*/ - }; - - FLASH_PflashSetPrefetchSpeculation(&speculationStatus); - - __enable_irq(); + EnableGlobalIRQ(g_savedPrimask); __ISB(); } +/*! + * brief Prepares to enter wait modes. + * + * This function should be called before entering WAIT/VLPW modes. + */ +void SMC_PreEnterWaitModes(void) +{ + g_savedPrimask = DisableGlobalIRQ(); + __ISB(); +} + +/*! + * brief Recovers after wake up from stop modes. + * + * This function should be called after wake up from WAIT/VLPW modes. + * It is used with ref SMC_PreEnterWaitModes. + */ +void SMC_PostExitWaitModes(void) +{ + EnableGlobalIRQ(g_savedPrimask); + __ISB(); +} + +/*! + * brief Configures the system to RUN power mode. + * + * param base SMC peripheral base address. + * return SMC configuration error code. + */ status_t SMC_SetPowerModeRun(SMC_Type *base) { uint8_t reg; @@ -89,6 +157,12 @@ status_t SMC_SetPowerModeRun(SMC_Type *base) } #if (defined(FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE) && FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE) +/*! + * brief Configures the system to HSRUN power mode. + * + * param base SMC peripheral base address. + * return SMC configuration error code. + */ status_t SMC_SetPowerModeHsrun(SMC_Type *base) { uint8_t reg; @@ -103,6 +177,12 @@ status_t SMC_SetPowerModeHsrun(SMC_Type *base) } #endif /* FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE */ +/*! + * brief Configures the system to WAIT power mode. + * + * param base SMC peripheral base address. + * return SMC configuration error code. + */ status_t SMC_SetPowerModeWait(SMC_Type *base) { /* configure Normal Wait mode */ @@ -114,12 +194,19 @@ status_t SMC_SetPowerModeWait(SMC_Type *base) return kStatus_Success; } +/*! + * brief Configures the system to Stop power mode. + * + * param base SMC peripheral base address. + * param option Partial Stop mode option. + * return SMC configuration error code. + */ status_t SMC_SetPowerModeStop(SMC_Type *base, smc_partial_stop_option_t option) { uint8_t reg; #if (defined(FSL_FEATURE_SMC_HAS_PSTOPO) && FSL_FEATURE_SMC_HAS_PSTOPO) - /* configure the Partial Stop mode in Noraml Stop mode */ + /* configure the Partial Stop mode in Normal Stop mode */ reg = base->STOPCTRL; reg &= ~SMC_STOPCTRL_PSTOPO_MASK; reg |= ((uint32_t)option << SMC_STOPCTRL_PSTOPO_SHIFT); @@ -137,9 +224,7 @@ status_t SMC_SetPowerModeStop(SMC_Type *base, smc_partial_stop_option_t option) /* read back to make sure the configuration valid before enter stop mode */ (void)base->PMCTRL; - __DSB(); - __WFI(); - __ISB(); + SMC_EnterStopRamFunc(); /* check whether the power mode enter Stop mode succeed */ if (base->PMCTRL & SMC_PMCTRL_STOPA_MASK) @@ -152,6 +237,12 @@ status_t SMC_SetPowerModeStop(SMC_Type *base, smc_partial_stop_option_t option) } } +/*! + * brief Configures the system to VLPR power mode. + * + * param base SMC peripheral base address. + * return SMC configuration error code. + */ status_t SMC_SetPowerModeVlpr(SMC_Type *base #if (defined(FSL_FEATURE_SMC_HAS_LPWUI) && FSL_FEATURE_SMC_HAS_LPWUI) , @@ -184,6 +275,12 @@ status_t SMC_SetPowerModeVlpr(SMC_Type *base return kStatus_Success; } +/*! + * brief Configures the system to VLPW power mode. + * + * param base SMC peripheral base address. + * return SMC configuration error code. + */ status_t SMC_SetPowerModeVlpw(SMC_Type *base) { /* configure VLPW mode */ @@ -196,6 +293,12 @@ status_t SMC_SetPowerModeVlpw(SMC_Type *base) return kStatus_Success; } +/*! + * brief Configures the system to VLPS power mode. + * + * param base SMC peripheral base address. + * return SMC configuration error code. + */ status_t SMC_SetPowerModeVlps(SMC_Type *base) { uint8_t reg; @@ -211,9 +314,7 @@ status_t SMC_SetPowerModeVlps(SMC_Type *base) /* read back to make sure the configuration valid before enter stop mode */ (void)base->PMCTRL; - __DSB(); - __WFI(); - __ISB(); + SMC_EnterStopRamFunc(); /* check whether the power mode enter VLPS mode succeed */ if (base->PMCTRL & SMC_PMCTRL_STOPA_MASK) @@ -227,6 +328,12 @@ status_t SMC_SetPowerModeVlps(SMC_Type *base) } #if (defined(FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE) && FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE) +/*! + * brief Configures the system to LLS power mode. + * + * param base SMC peripheral base address. + * return SMC configuration error code. + */ status_t SMC_SetPowerModeLls(SMC_Type *base #if ((defined(FSL_FEATURE_SMC_HAS_LLS_SUBMODE) && FSL_FEATURE_SMC_HAS_LLS_SUBMODE) || \ (defined(FSL_FEATURE_SMC_HAS_LPOPO) && FSL_FEATURE_SMC_HAS_LPOPO)) @@ -267,9 +374,7 @@ status_t SMC_SetPowerModeLls(SMC_Type *base /* read back to make sure the configuration valid before enter stop mode */ (void)base->PMCTRL; - __DSB(); - __WFI(); - __ISB(); + SMC_EnterStopRamFunc(); /* check whether the power mode enter LLS mode succeed */ if (base->PMCTRL & SMC_PMCTRL_STOPA_MASK) @@ -284,6 +389,13 @@ status_t SMC_SetPowerModeLls(SMC_Type *base #endif /* FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE */ #if (defined(FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE) && FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE) +/*! + * brief Configures the system to VLLS power mode. + * + * param base SMC peripheral base address. + * param config The VLLS power mode configuration structure. + * return SMC configuration error code. + */ status_t SMC_SetPowerModeVlls(SMC_Type *base, const smc_power_mode_vlls_config_t *config) { uint8_t reg; @@ -383,9 +495,7 @@ status_t SMC_SetPowerModeVlls(SMC_Type *base, const smc_power_mode_vlls_config_t /* read back to make sure the configuration valid before enter stop mode */ (void)base->PMCTRL; - __DSB(); - __WFI(); - __ISB(); + SMC_EnterStopRamFunc(); /* check whether the power mode enter LLS mode succeed */ if (base->PMCTRL & SMC_PMCTRL_STOPA_MASK) diff --git a/ext/hal/nxp/mcux/drivers/kinetis/fsl_smc.h b/ext/hal/nxp/mcux/drivers/kinetis/fsl_smc.h index 168ce835013..d5624d8bc96 100644 --- a/ext/hal/nxp/mcux/drivers/kinetis/fsl_smc.h +++ b/ext/hal/nxp/mcux/drivers/kinetis/fsl_smc.h @@ -1,31 +1,9 @@ /* * Copyright (c) 2015, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause */ #ifndef _FSL_SMC_H_ @@ -36,15 +14,14 @@ /*! @addtogroup smc */ /*! @{ */ - /******************************************************************************* * Definitions ******************************************************************************/ /*! @name Driver version */ /*@{*/ -/*! @brief SMC driver version 2.0.3. */ -#define FSL_SMC_DRIVER_VERSION (MAKE_VERSION(2, 0, 3)) +/*! @brief SMC driver version 2.0.4. */ +#define FSL_SMC_DRIVER_VERSION (MAKE_VERSION(2, 0, 4)) /*@}*/ /*! @@ -324,11 +301,7 @@ void SMC_PostExitStopModes(void); * * This function should be called before entering WAIT/VLPW modes. */ -static inline void SMC_PreEnterWaitModes(void) -{ - __disable_irq(); - __ISB(); -} +void SMC_PreEnterWaitModes(void); /*! * @brief Recovers after wake up from stop modes. @@ -336,11 +309,7 @@ static inline void SMC_PreEnterWaitModes(void) * This function should be called after wake up from WAIT/VLPW modes. * It is used with @ref SMC_PreEnterWaitModes. */ -static inline void SMC_PostExitWaitModes(void) -{ - __enable_irq(); - __ISB(); -} +void SMC_PostExitWaitModes(void); /*! * @brief Configures the system to RUN power mode. diff --git a/ext/hal/nxp/mcux/drivers/kinetis/fsl_sysmpu.c b/ext/hal/nxp/mcux/drivers/kinetis/fsl_sysmpu.c index b89a7b20e4e..a4640e70901 100644 --- a/ext/hal/nxp/mcux/drivers/kinetis/fsl_sysmpu.c +++ b/ext/hal/nxp/mcux/drivers/kinetis/fsl_sysmpu.c @@ -1,47 +1,38 @@ /* * Copyright (c) 2015 - 2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP + * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * SPDX-License-Identifier: BSD-3-Clause */ #include "fsl_sysmpu.h" +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.sysmpu" +#endif + /******************************************************************************* * Variables ******************************************************************************/ #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -const clock_ip_name_t g_sysmpuClock[FSL_FEATURE_SOC_SYSMPU_COUNT] = SYSMPU_CLOCKS; +static const clock_ip_name_t g_sysmpuClock[] = SYSMPU_CLOCKS; #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ /******************************************************************************* * Codes ******************************************************************************/ +/*! + * brief Initializes the SYSMPU with the user configuration structure. + * + * This function configures the SYSMPU module with the user-defined configuration. + * + * param base SYSMPU peripheral base address. + * param config The pointer to the configuration structure. + */ void SYSMPU_Init(SYSMPU_Type *base, const sysmpu_config_t *config) { assert(config); @@ -72,6 +63,11 @@ void SYSMPU_Init(SYSMPU_Type *base, const sysmpu_config_t *config) SYSMPU_Enable(base, true); } +/*! + * brief Deinitializes the SYSMPU regions. + * + * param base SYSMPU peripheral base address. + */ void SYSMPU_Deinit(SYSMPU_Type *base) { /* Disable SYSMPU. */ @@ -83,6 +79,12 @@ void SYSMPU_Deinit(SYSMPU_Type *base) #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ } +/*! + * brief Gets the SYSMPU basic hardware information. + * + * param base SYSMPU peripheral base address. + * param hardwareInform The pointer to the SYSMPU hardware information structure. See "sysmpu_hardware_info_t". + */ void SYSMPU_GetHardwareInfo(SYSMPU_Type *base, sysmpu_hardware_info_t *hardwareInform) { assert(hardwareInform); @@ -91,9 +93,21 @@ void SYSMPU_GetHardwareInfo(SYSMPU_Type *base, sysmpu_hardware_info_t *hardwareI hardwareInform->hardwareRevisionLevel = (cesReg & SYSMPU_CESR_HRL_MASK) >> SYSMPU_CESR_HRL_SHIFT; hardwareInform->slavePortsNumbers = (cesReg & SYSMPU_CESR_NSP_MASK) >> SYSMPU_CESR_NSP_SHIFT; - hardwareInform->regionsNumbers = (sysmpu_region_total_num_t)((cesReg & SYSMPU_CESR_NRGD_MASK) >> SYSMPU_CESR_NRGD_SHIFT); + hardwareInform->regionsNumbers = + (sysmpu_region_total_num_t)((cesReg & SYSMPU_CESR_NRGD_MASK) >> SYSMPU_CESR_NRGD_SHIFT); } +/*! + * brief Sets the SYSMPU region. + * + * Note: Due to the SYSMPU protection, the region number 0 does not allow writes from + * core to affect the start and end address nor the permissions associated with + * the debugger. It can only write the permission fields associated + * with the other masters. + * + * param base SYSMPU peripheral base address. + * param regionConfig The pointer to the SYSMPU user configuration structure. See "sysmpu_region_config_t". + */ void SYSMPU_SetRegionConfig(SYSMPU_Type *base, const sysmpu_region_config_t *regionConfig) { assert(regionConfig); @@ -115,19 +129,19 @@ void SYSMPU_SetRegionConfig(SYSMPU_Type *base, const sysmpu_region_config_t *reg (uint32_t)regionConfig->accessRights1[msPortNum].userAccessRights)); #if FSL_FEATURE_SYSMPU_HAS_PROCESS_IDENTIFIER - wordReg |= - SYSMPU_REGION_RWXRIGHTS_MASTER_PE(msPortNum, regionConfig->accessRights1[msPortNum].processIdentifierEnable); + wordReg |= SYSMPU_REGION_RWXRIGHTS_MASTER_PE(msPortNum, + regionConfig->accessRights1[msPortNum].processIdentifierEnable); #endif /* FSL_FEATURE_SYSMPU_HAS_PROCESS_IDENTIFIER */ } #if FSL_FEATURE_SYSMPU_MASTER_COUNT > SYSMPU_MASTER_RWATTRIBUTE_START_PORT /* Set the normal read write rights for master 4 ~ master 7. */ - for (msPortNum = SYSMPU_MASTER_RWATTRIBUTE_START_PORT; msPortNum < FSL_FEATURE_SYSMPU_MASTER_COUNT; - msPortNum++) + for (msPortNum = SYSMPU_MASTER_RWATTRIBUTE_START_PORT; msPortNum < FSL_FEATURE_SYSMPU_MASTER_COUNT; msPortNum++) { - wordReg |= SYSMPU_REGION_RWRIGHTS_MASTER(msPortNum, + wordReg |= SYSMPU_REGION_RWRIGHTS_MASTER( + msPortNum, ((uint32_t)regionConfig->accessRights2[msPortNum - SYSMPU_MASTER_RWATTRIBUTE_START_PORT].readEnable << 1U | - (uint32_t)regionConfig->accessRights2[msPortNum - SYSMPU_MASTER_RWATTRIBUTE_START_PORT].writeEnable)); + (uint32_t)regionConfig->accessRights2[msPortNum - SYSMPU_MASTER_RWATTRIBUTE_START_PORT].writeEnable)); } #endif /* FSL_FEATURE_SYSMPU_MASTER_COUNT > SYSMPU_MASTER_RWATTRIBUTE_START_PORT */ @@ -142,6 +156,22 @@ void SYSMPU_SetRegionConfig(SYSMPU_Type *base, const sysmpu_region_config_t *reg base->WORD[regNumber][3] = wordReg; } +/*! + * brief Sets the region start and end address. + * + * Memory region start address. Note: bit0 ~ bit4 is always marked as 0 by SYSMPU. + * The actual start address by SYSMPU is 0-modulo-32 byte address. + * Memory region end address. Note: bit0 ~ bit4 always be marked as 1 by SYSMPU. + * The end address used by the SYSMPU is 31-modulo-32 byte address. + * Note: Due to the SYSMPU protection, the startAddr and endAddr can't be + * changed by the core when regionNum is 0. + * + * param base SYSMPU peripheral base address. + * param regionNum SYSMPU region number. The range is from 0 to + * FSL_FEATURE_SYSMPU_DESCRIPTOR_COUNT - 1. + * param startAddr Region start address. + * param endAddr Region end address. + */ void SYSMPU_SetRegionAddr(SYSMPU_Type *base, uint32_t regionNum, uint32_t startAddr, uint32_t endAddr) { assert(regionNum < FSL_FEATURE_SYSMPU_DESCRIPTOR_COUNT); @@ -150,10 +180,30 @@ void SYSMPU_SetRegionAddr(SYSMPU_Type *base, uint32_t regionNum, uint32_t startA base->WORD[regionNum][1] = endAddr; } +/*! + * brief Sets the SYSMPU region access rights for masters with read, write, and execute rights. + * The SYSMPU access rights depend on two board classifications of bus masters. + * The privilege rights masters and the normal rights masters. + * The privilege rights masters have the read, write, and execute access rights. + * Except the normal read and write rights, the execute rights are also + * allowed for these masters. The privilege rights masters normally range from + * bus masters 0 - 3. However, the maximum master number is device-specific. + * See the "SYSMPU_PRIVILEGED_RIGHTS_MASTER_MAX_INDEX". + * The normal rights masters access rights control see + * "SYSMPU_SetRegionRwMasterAccessRights()". + * + * param base SYSMPU peripheral base address. + * param regionNum SYSMPU region number. Should range from 0 to + * FSL_FEATURE_SYSMPU_DESCRIPTOR_COUNT - 1. + * param masterNum SYSMPU bus master number. Should range from 0 to + * SYSMPU_PRIVILEGED_RIGHTS_MASTER_MAX_INDEX. + * param accessRights The pointer to the SYSMPU access rights configuration. See + * "sysmpu_rwxrights_master_access_control_t". + */ void SYSMPU_SetRegionRwxMasterAccessRights(SYSMPU_Type *base, - uint32_t regionNum, - uint32_t masterNum, - const sysmpu_rwxrights_master_access_control_t *accessRights) + uint32_t regionNum, + uint32_t masterNum, + const sysmpu_rwxrights_master_access_control_t *accessRights) { assert(accessRights); assert(regionNum < FSL_FEATURE_SYSMPU_DESCRIPTOR_COUNT); @@ -179,10 +229,25 @@ void SYSMPU_SetRegionRwxMasterAccessRights(SYSMPU_Type *base, } #if FSL_FEATURE_SYSMPU_MASTER_COUNT > 4 +/*! + * brief Sets the SYSMPU region access rights for masters with read and write rights. + * The SYSMPU access rights depend on two board classifications of bus masters. + * The privilege rights masters and the normal rights masters. + * The normal rights masters only have the read and write access permissions. + * The privilege rights access control see "SYSMPU_SetRegionRwxMasterAccessRights". + * + * param base SYSMPU peripheral base address. + * param regionNum SYSMPU region number. The range is from 0 to + * FSL_FEATURE_SYSMPU_DESCRIPTOR_COUNT - 1. + * param masterNum SYSMPU bus master number. Should range from SYSMPU_MASTER_RWATTRIBUTE_START_PORT + * to ~ FSL_FEATURE_SYSMPU_MASTER_COUNT - 1. + * param accessRights The pointer to the SYSMPU access rights configuration. See + * "sysmpu_rwrights_master_access_control_t". + */ void SYSMPU_SetRegionRwMasterAccessRights(SYSMPU_Type *base, - uint32_t regionNum, - uint32_t masterNum, - const sysmpu_rwrights_master_access_control_t *accessRights) + uint32_t regionNum, + uint32_t masterNum, + const sysmpu_rwrights_master_access_control_t *accessRights) { assert(accessRights); assert(regionNum < FSL_FEATURE_SYSMPU_DESCRIPTOR_COUNT); @@ -194,22 +259,39 @@ void SYSMPU_SetRegionRwMasterAccessRights(SYSMPU_Type *base, /* Build rights control value. */ right &= ~mask; - right |= - SYSMPU_REGION_RWRIGHTS_MASTER(masterNum, (((uint32_t)accessRights->readEnable << 1U) | accessRights->writeEnable)); + right |= SYSMPU_REGION_RWRIGHTS_MASTER(masterNum, + (((uint32_t)accessRights->readEnable << 1U) | accessRights->writeEnable)); /* Set low master region access rights. */ base->RGDAAC[regionNum] = right; } #endif /* FSL_FEATURE_SYSMPU_MASTER_COUNT > 4 */ +/*! + * brief Gets the numbers of slave ports where errors occur. + * + * param base SYSMPU peripheral base address. + * param slaveNum SYSMPU slave port number. + * return The slave ports error status. + * true - error happens in this slave port. + * false - error didn't happen in this slave port. + */ bool SYSMPU_GetSlavePortErrorStatus(SYSMPU_Type *base, sysmpu_slave_t slaveNum) { uint8_t sperr; - sperr = ((base->CESR & SYSMPU_CESR_SPERR_MASK) >> SYSMPU_CESR_SPERR_SHIFT) & (0x1U << (FSL_FEATURE_SYSMPU_SLAVE_COUNT - slaveNum - 1)); + sperr = ((base->CESR & SYSMPU_CESR_SPERR_MASK) >> SYSMPU_CESR_SPERR_SHIFT) & + (0x1U << (FSL_FEATURE_SYSMPU_SLAVE_COUNT - slaveNum - 1)); return (sperr != 0) ? true : false; } +/*! + * brief Gets the SYSMPU detailed error access information. + * + * param base SYSMPU peripheral base address. + * param slaveNum SYSMPU slave port number. + * param errInform The pointer to the SYSMPU access error information. See "sysmpu_access_err_info_t". + */ void SYSMPU_GetDetailErrorAccessInfo(SYSMPU_Type *base, sysmpu_slave_t slaveNum, sysmpu_access_err_info_t *errInform) { assert(errInform); @@ -244,6 +326,7 @@ void SYSMPU_GetDetailErrorAccessInfo(SYSMPU_Type *base, sysmpu_slave_t slaveNum, #endif /* Clears error slave port bit. */ - cesReg = (base->CESR & ~SYSMPU_CESR_SPERR_MASK) | ((0x1U << (FSL_FEATURE_SYSMPU_SLAVE_COUNT - slaveNum - 1)) << SYSMPU_CESR_SPERR_SHIFT); + cesReg = (base->CESR & ~SYSMPU_CESR_SPERR_MASK) | + ((0x1U << (FSL_FEATURE_SYSMPU_SLAVE_COUNT - slaveNum - 1)) << SYSMPU_CESR_SPERR_SHIFT); base->CESR = cesReg; } diff --git a/ext/hal/nxp/mcux/drivers/kinetis/fsl_sysmpu.h b/ext/hal/nxp/mcux/drivers/kinetis/fsl_sysmpu.h index 6341a31e9d1..21cf02bea89 100644 --- a/ext/hal/nxp/mcux/drivers/kinetis/fsl_sysmpu.h +++ b/ext/hal/nxp/mcux/drivers/kinetis/fsl_sysmpu.h @@ -1,31 +1,9 @@ /* * Copyright (c) 2015 - 2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause */ #ifndef _FSL_SYSMPU_H_ #define _FSL_SYSMPU_H_ @@ -45,14 +23,14 @@ /*! @name Driver version */ /*@{*/ /*! @brief SYSMPU driver version 2.2.0. */ -#define FSL_SYSMPU_DRIVER_VERSION (MAKE_VERSION(2, 2, 0)) +#define FSL_SYSMPU_DRIVER_VERSION (MAKE_VERSION(2, 2, 1)) /*@}*/ /*! @brief define the start master port with read and write attributes. */ #define SYSMPU_MASTER_RWATTRIBUTE_START_PORT (4) /*! @brief SYSMPU the bit shift for masters with privilege rights: read write and execute. */ -#define SYSMPU_REGION_RWXRIGHTS_MASTER_SHIFT(n) (n * 6) +#define SYSMPU_REGION_RWXRIGHTS_MASTER_SHIFT(n) ((n) * 6) /*! @brief SYSMPU masters with read, write and execute rights bit mask. */ #define SYSMPU_REGION_RWXRIGHTS_MASTER_MASK(n) (0x1Fu << SYSMPU_REGION_RWXRIGHTS_MASTER_SHIFT(n)) @@ -65,7 +43,7 @@ (((uint32_t)(((uint32_t)(x)) << SYSMPU_REGION_RWXRIGHTS_MASTER_SHIFT(n))) & SYSMPU_REGION_RWXRIGHTS_MASTER_MASK(n)) /*! @brief SYSMPU masters with read, write and execute rights process enable bit shift. */ -#define SYSMPU_REGION_RWXRIGHTS_MASTER_PE_SHIFT(n) (n * 6 + SYSMPU_REGION_RWXRIGHTS_MASTER_WIDTH) +#define SYSMPU_REGION_RWXRIGHTS_MASTER_PE_SHIFT(n) ((n) * 6 + SYSMPU_REGION_RWXRIGHTS_MASTER_WIDTH) /*! @brief SYSMPU masters with read, write and execute rights process enable bit mask. */ #define SYSMPU_REGION_RWXRIGHTS_MASTER_PE_MASK(n) (0x1u << SYSMPU_REGION_RWXRIGHTS_MASTER_PE_SHIFT(n)) @@ -75,7 +53,7 @@ (((uint32_t)(((uint32_t)(x)) << SYSMPU_REGION_RWXRIGHTS_MASTER_PE_SHIFT(n))) & SYSMPU_REGION_RWXRIGHTS_MASTER_PE_MASK(n)) /*! @brief SYSMPU masters with normal read write permission bit shift. */ -#define SYSMPU_REGION_RWRIGHTS_MASTER_SHIFT(n) ((n - SYSMPU_MASTER_RWATTRIBUTE_START_PORT) * 2 + 24) +#define SYSMPU_REGION_RWRIGHTS_MASTER_SHIFT(n) (((n) - SYSMPU_MASTER_RWATTRIBUTE_START_PORT) * 2 + 24) /*! @brief SYSMPU masters with normal read write rights bit mask. */ #define SYSMPU_REGION_RWRIGHTS_MASTER_MASK(n) (0x3u << SYSMPU_REGION_RWRIGHTS_MASTER_SHIFT(n)) diff --git a/ext/hal/nxp/mcux/drivers/kinetis/fsl_uart.c b/ext/hal/nxp/mcux/drivers/kinetis/fsl_uart.c index 17d9260027b..7d2b6f30924 100644 --- a/ext/hal/nxp/mcux/drivers/kinetis/fsl_uart.c +++ b/ext/hal/nxp/mcux/drivers/kinetis/fsl_uart.c @@ -1,31 +1,9 @@ /* * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP + * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * SPDX-License-Identifier: BSD-3-Clause */ #include "fsl_uart.h" @@ -34,6 +12,11 @@ * Definitions ******************************************************************************/ +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.uart" +#endif + /* UART transfer state. */ enum _uart_tansfer_states { @@ -51,23 +34,6 @@ typedef void (*uart_isr_t)(UART_Type *base, uart_handle_t *handle); /******************************************************************************* * Prototypes ******************************************************************************/ - -/*! - * @brief Get the UART instance from peripheral base address. - * - * @param base UART peripheral base address. - * @return UART instance. - */ -uint32_t UART_GetInstance(UART_Type *base); - -/*! - * @brief Get the length of received data in RX ring buffer. - * - * @param handle UART handle pointer. - * @return Length of received data in RX ring buffer. - */ -static size_t UART_TransferGetRxRingBufferLength(uart_handle_t *handle); - /*! * @brief Check whether the RX ring buffer is full. * @@ -100,7 +66,7 @@ static void UART_ReadNonBlocking(UART_Type *base, uint8_t *data, size_t length); * finished. * * @param base UART peripheral base address. - * @param data Start addresss of the data to write. + * @param data Start address of the data to write. * @param length Size of the buffer to be sent. */ static void UART_WriteNonBlocking(UART_Type *base, const uint8_t *data, size_t length); @@ -152,6 +118,12 @@ static uart_isr_t s_uartIsr; * Code ******************************************************************************/ +/*! + * brief Get the UART instance from peripheral base address. + * + * param base UART peripheral base address. + * return UART instance. + */ uint32_t UART_GetInstance(UART_Type *base) { uint32_t instance; @@ -171,7 +143,13 @@ uint32_t UART_GetInstance(UART_Type *base) return instance; } -static size_t UART_TransferGetRxRingBufferLength(uart_handle_t *handle) +/*! + * brief Get the length of received data in RX ring buffer. + * + * param handle UART handle pointer. + * return Length of received data in RX ring buffer. + */ +size_t UART_TransferGetRxRingBufferLength(uart_handle_t *handle) { assert(handle); @@ -207,6 +185,28 @@ static bool UART_TransferIsRxRingBufferFull(uart_handle_t *handle) return full; } +/*! + * brief Initializes a UART instance with a user configuration structure and peripheral clock. + * + * This function configures the UART module with the user-defined settings. The user can configure the configuration + * structure and also get the default configuration by using the UART_GetDefaultConfig() function. + * The example below shows how to use this API to configure UART. + * code + * uart_config_t uartConfig; + * uartConfig.baudRate_Bps = 115200U; + * uartConfig.parityMode = kUART_ParityDisabled; + * uartConfig.stopBitCount = kUART_OneStopBit; + * uartConfig.txFifoWatermark = 0; + * uartConfig.rxFifoWatermark = 1; + * UART_Init(UART1, &uartConfig, 20000000U); + * endcode + * + * param base UART peripheral base address. + * param config Pointer to the user-defined configuration structure. + * param srcClock_Hz UART clock source frequency in HZ. + * retval kStatus_UART_BaudrateNotSupport Baudrate is not support in current clock source. + * retval kStatus_Success Status UART initialize succeed + */ status_t UART_Init(UART_Type *base, const uart_config_t *config, uint32_t srcClock_Hz) { assert(config); @@ -277,8 +277,10 @@ status_t UART_Init(UART_Type *base, const uart_config_t *config, uint32_t srcClo base->C4 = (base->C4 & ~UART_C4_BRFA_MASK) | (brfa & UART_C4_BRFA_MASK); #endif - /* Set bit count and parity mode. */ - temp = base->C1 & ~(UART_C1_PE_MASK | UART_C1_PT_MASK | UART_C1_M_MASK); + /* Set bit count/parity mode/idle type. */ + temp = base->C1 & ~(UART_C1_PE_MASK | UART_C1_PT_MASK | UART_C1_M_MASK | UART_C1_ILT_MASK); + + temp |= UART_C1_ILT(config->idleType); if (kUART_ParityDisabled != config->parityMode) { @@ -293,7 +295,15 @@ status_t UART_Init(UART_Type *base, const uart_config_t *config, uint32_t srcClo #endif #if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO - /* Set tx/rx FIFO watermark */ + /* Set tx/rx FIFO watermark + Note: + Take care of the RX FIFO, RX interrupt request only assert when received bytes + equal or more than RX water mark, there is potential issue if RX water + mark larger than 1. + For example, if RX FIFO water mark is 2, upper layer needs 5 bytes and + 5 bytes are received. the last byte will be saved in FIFO but not trigger + RX interrupt because the water mark is 2. + */ base->TWFIFO = config->txFifoWatermark; base->RWFIFO = config->rxFifoWatermark; @@ -303,6 +313,18 @@ status_t UART_Init(UART_Type *base, const uart_config_t *config, uint32_t srcClo /* Flush FIFO */ base->CFIFO |= (UART_CFIFO_TXFLUSH_MASK | UART_CFIFO_RXFLUSH_MASK); #endif +#if defined(FSL_FEATURE_UART_HAS_MODEM_SUPPORT) && FSL_FEATURE_UART_HAS_MODEM_SUPPORT + if (config->enableRxRTS) + { + /* Enable receiver RTS(request-to-send) function. */ + base->MODEM |= UART_MODEM_RXRTSE_MASK; + } + if (config->enableTxCTS) + { + /* Enable transmitter CTS(clear-to-send) function. */ + base->MODEM |= UART_MODEM_TXCTSE_MASK; + } +#endif /* Enable TX/RX base on configure structure. */ temp = base->C2; @@ -322,6 +344,13 @@ status_t UART_Init(UART_Type *base, const uart_config_t *config, uint32_t srcClo return kStatus_Success; } +/*! + * brief Deinitializes a UART instance. + * + * This function waits for TX complete, disables TX and RX, and disables the UART clock. + * + * param base UART peripheral base address. + */ void UART_Deinit(UART_Type *base) { #if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO @@ -344,10 +373,30 @@ void UART_Deinit(UART_Type *base) #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ } +/*! + * brief Gets the default configuration structure. + * + * This function initializes the UART configuration structure to a default value. The default + * values are as follows. + * uartConfig->baudRate_Bps = 115200U; + * uartConfig->bitCountPerChar = kUART_8BitsPerChar; + * uartConfig->parityMode = kUART_ParityDisabled; + * uartConfig->stopBitCount = kUART_OneStopBit; + * uartConfig->txFifoWatermark = 0; + * uartConfig->rxFifoWatermark = 1; + * uartConfig->idleType = kUART_IdleTypeStartBit; + * uartConfig->enableTx = false; + * uartConfig->enableRx = false; + * + * param config Pointer to configuration structure. + */ void UART_GetDefaultConfig(uart_config_t *config) { assert(config); + /* Initializes the configure structure to zero. */ + memset(config, 0, sizeof(*config)); + config->baudRate_Bps = 115200U; config->parityMode = kUART_ParityDisabled; #if defined(FSL_FEATURE_UART_HAS_STOP_BIT_CONFIG_SUPPORT) && FSL_FEATURE_UART_HAS_STOP_BIT_CONFIG_SUPPORT @@ -357,10 +406,30 @@ void UART_GetDefaultConfig(uart_config_t *config) config->txFifoWatermark = 0; config->rxFifoWatermark = 1; #endif +#if defined(FSL_FEATURE_UART_HAS_MODEM_SUPPORT) && FSL_FEATURE_UART_HAS_MODEM_SUPPORT + config->enableRxRTS = false; + config->enableTxCTS = false; +#endif + config->idleType = kUART_IdleTypeStartBit; config->enableTx = false; config->enableRx = false; } +/*! + * brief Sets the UART instance baud rate. + * + * This function configures the UART module baud rate. This function is used to update + * the UART module baud rate after the UART module is initialized by the UART_Init. + * code + * UART_SetBaudRate(UART1, 115200U, 20000000U); + * endcode + * + * param base UART peripheral base address. + * param baudRate_Bps UART baudrate to be set. + * param srcClock_Hz UART clock source freqency in Hz. + * retval kStatus_UART_BaudrateNotSupport Baudrate is not support in the current clock source. + * retval kStatus_Success Set baudrate succeeded. + */ status_t UART_SetBaudRate(UART_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz) { assert(baudRate_Bps); @@ -429,6 +498,19 @@ status_t UART_SetBaudRate(UART_Type *base, uint32_t baudRate_Bps, uint32_t srcCl } } +/*! + * brief Enables UART interrupts according to the provided mask. + * + * This function enables the UART interrupts according to the provided mask. The mask + * is a logical OR of enumeration members. See ref _uart_interrupt_enable. + * For example, to enable TX empty interrupt and RX full interrupt, do the following. + * code + * UART_EnableInterrupts(UART1,kUART_TxDataRegEmptyInterruptEnable | kUART_RxDataRegFullInterruptEnable); + * endcode + * + * param base UART peripheral base address. + * param mask The interrupts to enable. Logical OR of ref _uart_interrupt_enable. + */ void UART_EnableInterrupts(UART_Type *base, uint32_t mask) { mask &= kUART_AllInterruptsEnable; @@ -444,6 +526,19 @@ void UART_EnableInterrupts(UART_Type *base, uint32_t mask) #endif } +/*! + * brief Disables the UART interrupts according to the provided mask. + * + * This function disables the UART interrupts according to the provided mask. The mask + * is a logical OR of enumeration members. See ref _uart_interrupt_enable. + * For example, to disable TX empty interrupt and RX full interrupt do the following. + * code + * UART_DisableInterrupts(UART1,kUART_TxDataRegEmptyInterruptEnable | kUART_RxDataRegFullInterruptEnable); + * endcode + * + * param base UART peripheral base address. + * param mask The interrupts to disable. Logical OR of ref _uart_interrupt_enable. + */ void UART_DisableInterrupts(UART_Type *base, uint32_t mask) { mask &= kUART_AllInterruptsEnable; @@ -459,6 +554,26 @@ void UART_DisableInterrupts(UART_Type *base, uint32_t mask) #endif } +/*! + * brief Gets the enabled UART interrupts. + * + * This function gets the enabled UART interrupts. The enabled interrupts are returned + * as the logical OR value of the enumerators ref _uart_interrupt_enable. To check + * a specific interrupts enable status, compare the return value with enumerators + * in ref _uart_interrupt_enable. + * For example, to check whether TX empty interrupt is enabled, do the following. + * code + * uint32_t enabledInterrupts = UART_GetEnabledInterrupts(UART1); + * + * if (kUART_TxDataRegEmptyInterruptEnable & enabledInterrupts) + * { + * ... + * } + * endcode + * + * param base UART peripheral base address. + * return UART interrupt flags which are logical OR of the enumerators in ref _uart_interrupt_enable. + */ uint32_t UART_GetEnabledInterrupts(UART_Type *base) { uint32_t temp; @@ -472,6 +587,23 @@ uint32_t UART_GetEnabledInterrupts(UART_Type *base) return temp & kUART_AllInterruptsEnable; } +/*! + * brief Gets UART status flags. + * + * This function gets all UART status flags. The flags are returned as the logical + * OR value of the enumerators ref _uart_flags. To check a specific status, + * compare the return value with enumerators in ref _uart_flags. + * For example, to check whether the TX is empty, do the following. + * code + * if (kUART_TxDataRegEmptyFlag & UART_GetStatusFlags(UART1)) + * { + * ... + * } + * endcode + * + * param base UART peripheral base address. + * return UART status flags which are ORed by the enumerators in the _uart_flags. + */ uint32_t UART_GetStatusFlags(UART_Type *base) { uint32_t status_flag; @@ -489,6 +621,23 @@ uint32_t UART_GetStatusFlags(UART_Type *base) return status_flag; } +/*! + * brief Clears status flags with the provided mask. + * + * This function clears UART status flags with a provided mask. An automatically cleared flag + * can't be cleared by this function. + * These flags can only be cleared or set by hardware. + * kUART_TxDataRegEmptyFlag, kUART_TransmissionCompleteFlag, kUART_RxDataRegFullFlag, + * kUART_RxActiveFlag, kUART_NoiseErrorInRxDataRegFlag, kUART_ParityErrorInRxDataRegFlag, + * kUART_TxFifoEmptyFlag,kUART_RxFifoEmptyFlag + * Note that this API should be called when the Tx/Rx is idle. Otherwise it has no effect. + * + * param base UART peripheral base address. + * param mask The status flags to be cleared; it is logical OR value of ref _uart_flags. + * retval kStatus_UART_FlagCannotClearManually The flag can't be cleared by this function but + * it is cleared automatically by hardware. + * retval kStatus_Success Status in the mask is cleared. + */ status_t UART_ClearStatusFlags(UART_Type *base, uint32_t mask) { uint8_t reg = base->S2; @@ -540,6 +689,20 @@ status_t UART_ClearStatusFlags(UART_Type *base, uint32_t mask) return status; } +/*! + * brief Writes to the TX register using a blocking method. + * + * This function polls the TX register, waits for the TX register to be empty or for the TX FIFO + * to have room and writes data to the TX buffer. + * + * note This function does not check whether all data is sent out to the bus. + * Before disabling the TX, check kUART_TransmissionCompleteFlag to ensure that the TX is + * finished. + * + * param base UART peripheral base address. + * param data Start address of the data to write. + * param length Size of the data to write. + */ void UART_WriteBlocking(UART_Type *base, const uint8_t *data, size_t length) { /* This API can only ensure that the data is written into the data buffer but can't @@ -567,6 +730,21 @@ static void UART_WriteNonBlocking(UART_Type *base, const uint8_t *data, size_t l } } +/*! + * brief Read RX data register using a blocking method. + * + * This function polls the RX register, waits for the RX register to be full or for RX FIFO to + * have data, and reads data from the TX register. + * + * param base UART peripheral base address. + * param data Start address of the buffer to store the received data. + * param length Size of the buffer. + * retval kStatus_UART_RxHardwareOverrun Receiver overrun occurred while receiving data. + * retval kStatus_UART_NoiseError A noise error occurred while receiving data. + * retval kStatus_UART_FramingError A framing error occurred while receiving data. + * retval kStatus_UART_ParityError A parity error occurred while receiving data. + * retval kStatus_Success Successfully received all data. + */ status_t UART_ReadBlocking(UART_Type *base, uint8_t *data, size_t length) { assert(data); @@ -623,6 +801,18 @@ static void UART_ReadNonBlocking(UART_Type *base, uint8_t *data, size_t length) } } +/*! + * brief Initializes the UART handle. + * + * This function initializes the UART handle which can be used for other UART + * transactional APIs. Usually, for a specified UART instance, + * call this API once to get the initialized handle. + * + * param base UART peripheral base address. + * param handle UART handle pointer. + * param callback The callback function. + * param userData The parameter of the callback function. + */ void UART_TransferCreateHandle(UART_Type *base, uart_handle_t *handle, uart_transfer_callback_t callback, @@ -643,18 +833,6 @@ void UART_TransferCreateHandle(UART_Type *base, handle->callback = callback; handle->userData = userData; -#if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO - /* Note: - Take care of the RX FIFO, RX interrupt request only assert when received bytes - equal or more than RX water mark, there is potential issue if RX water - mark larger than 1. - For example, if RX FIFO water mark is 2, upper layer needs 5 bytes and - 5 bytes are received. the last byte will be saved in FIFO but not trigger - RX interrupt because the water mark is 2. - */ - base->RWFIFO = 1U; -#endif - /* Get instance from peripheral base address. */ instance = UART_GetInstance(base); @@ -666,6 +844,23 @@ void UART_TransferCreateHandle(UART_Type *base, EnableIRQ(s_uartIRQ[instance]); } +/*! + * brief Sets up the RX ring buffer. + * + * This function sets up the RX ring buffer to a specific UART handle. + * + * When the RX ring buffer is used, data received are stored into the ring buffer even when the + * user doesn't call the UART_TransferReceiveNonBlocking() API. If data is already received + * in the ring buffer, the user can get the received data from the ring buffer directly. + * + * note When using the RX ring buffer, one byte is reserved for internal use. In other + * words, if p ringBufferSize is 32, only 31 bytes are used for saving data. + * + * param base UART peripheral base address. + * param handle UART handle pointer. + * param ringBuffer Start address of the ring buffer for background receiving. Pass NULL to disable the ring buffer. + * param ringBufferSize Size of the ring buffer. + */ void UART_TransferStartRingBuffer(UART_Type *base, uart_handle_t *handle, uint8_t *ringBuffer, size_t ringBufferSize) { assert(handle); @@ -687,6 +882,14 @@ void UART_TransferStartRingBuffer(UART_Type *base, uart_handle_t *handle, uint8_ } } +/*! + * brief Aborts the background transfer and uninstalls the ring buffer. + * + * This function aborts the background transfer and uninstalls the ring buffer. + * + * param base UART peripheral base address. + * param handle UART handle pointer. + */ void UART_TransferStopRingBuffer(UART_Type *base, uart_handle_t *handle) { assert(handle); @@ -708,6 +911,25 @@ void UART_TransferStopRingBuffer(UART_Type *base, uart_handle_t *handle) handle->rxRingBufferTail = 0U; } +/*! + * brief Transmits a buffer of data using the interrupt method. + * + * This function sends data using an interrupt method. This is a non-blocking function, which + * returns directly without waiting for all data to be written to the TX register. When + * all data is written to the TX register in the ISR, the UART driver calls the callback + * function and passes the ref kStatus_UART_TxIdle as status parameter. + * + * note The kStatus_UART_TxIdle is passed to the upper layer when all data is written + * to the TX register. However, it does not ensure that all data is sent out. Before disabling the TX, + * check the kUART_TransmissionCompleteFlag to ensure that the TX is finished. + * + * param base UART peripheral base address. + * param handle UART handle pointer. + * param xfer UART transfer structure. See #uart_transfer_t. + * retval kStatus_Success Successfully start the data transmission. + * retval kStatus_UART_TxBusy Previous transmission still not finished; data not all written to TX register yet. + * retval kStatus_InvalidArgument Invalid argument. + */ status_t UART_TransferSendNonBlocking(UART_Type *base, uart_handle_t *handle, uart_transfer_t *xfer) { assert(handle); @@ -729,7 +951,7 @@ status_t UART_TransferSendNonBlocking(UART_Type *base, uart_handle_t *handle, ua handle->txDataSizeAll = xfer->dataSize; handle->txState = kUART_TxBusy; - /* Enable transmiter interrupt. */ + /* Enable transmitter interrupt. */ UART_EnableInterrupts(base, kUART_TxDataRegEmptyInterruptEnable); status = kStatus_Success; @@ -738,6 +960,15 @@ status_t UART_TransferSendNonBlocking(UART_Type *base, uart_handle_t *handle, ua return status; } +/*! + * brief Aborts the interrupt-driven data transmit. + * + * This function aborts the interrupt-driven data sending. The user can get the remainBytes to find out + * how many bytes are not sent out. + * + * param base UART peripheral base address. + * param handle UART handle pointer. + */ void UART_TransferAbortSend(UART_Type *base, uart_handle_t *handle) { assert(handle); @@ -748,6 +979,19 @@ void UART_TransferAbortSend(UART_Type *base, uart_handle_t *handle) handle->txState = kUART_TxIdle; } +/*! + * brief Gets the number of bytes written to the UART TX register. + * + * This function gets the number of bytes written to the UART TX + * register by using the interrupt method. + * + * param base UART peripheral base address. + * param handle UART handle pointer. + * param count Send bytes count. + * retval kStatus_NoTransferInProgress No send in progress. + * retval kStatus_InvalidArgument The parameter is invalid. + * retval kStatus_Success Get successfully through the parameter \p count; + */ status_t UART_TransferGetSendCount(UART_Type *base, uart_handle_t *handle, uint32_t *count) { assert(handle); @@ -763,6 +1007,32 @@ status_t UART_TransferGetSendCount(UART_Type *base, uart_handle_t *handle, uint3 return kStatus_Success; } +/*! + * brief Receives a buffer of data using an interrupt method. + * + * This function receives data using an interrupt method. This is a non-blocking function, which + * returns without waiting for all data to be received. + * If the RX ring buffer is used and not empty, the data in the ring buffer is copied and + * the parameter p receivedBytes shows how many bytes are copied from the ring buffer. + * After copying, if the data in the ring buffer is not enough to read, the receive + * request is saved by the UART driver. When the new data arrives, the receive request + * is serviced first. When all data is received, the UART driver notifies the upper layer + * through a callback function and passes the status parameter ref kStatus_UART_RxIdle. + * For example, the upper layer needs 10 bytes but there are only 5 bytes in the ring buffer. + * The 5 bytes are copied to the xfer->data and this function returns with the + * parameter p receivedBytes set to 5. For the left 5 bytes, newly arrived data is + * saved from the xfer->data[5]. When 5 bytes are received, the UART driver notifies the upper layer. + * If the RX ring buffer is not enabled, this function enables the RX and RX interrupt + * to receive data to the xfer->data. When all data is received, the upper layer is notified. + * + * param base UART peripheral base address. + * param handle UART handle pointer. + * param xfer UART transfer structure, see #uart_transfer_t. + * param receivedBytes Bytes received from the ring buffer directly. + * retval kStatus_Success Successfully queue the transfer into transmit queue. + * retval kStatus_UART_RxBusy Previous receive request is not finished. + * retval kStatus_InvalidArgument Invalid argument. + */ status_t UART_TransferReceiveNonBlocking(UART_Type *base, uart_handle_t *handle, uart_transfer_t *xfer, @@ -863,9 +1133,9 @@ status_t UART_TransferReceiveNonBlocking(UART_Type *base, handle->rxDataSizeAll = bytesToReceive; handle->rxState = kUART_RxBusy; - /* Enable RX/Rx overrun/framing error interrupt. */ + /* Enable RX/Rx overrun/framing error/idle line interrupt. */ UART_EnableInterrupts(base, kUART_RxDataRegFullInterruptEnable | kUART_RxOverrunInterruptEnable | - kUART_FramingErrorInterruptEnable); + kUART_FramingErrorInterruptEnable | kUART_IdleLineInterruptEnable); /* Enable parity error interrupt when parity mode is enable*/ if (UART_C1_PE_MASK & base->C1) { @@ -885,6 +1155,15 @@ status_t UART_TransferReceiveNonBlocking(UART_Type *base, return status; } +/*! + * brief Aborts the interrupt-driven data receiving. + * + * This function aborts the interrupt-driven data receiving. The user can get the remainBytes to know + * how many bytes are not received yet. + * + * param base UART peripheral base address. + * param handle UART handle pointer. + */ void UART_TransferAbortReceive(UART_Type *base, uart_handle_t *handle) { assert(handle); @@ -894,7 +1173,7 @@ void UART_TransferAbortReceive(UART_Type *base, uart_handle_t *handle) { /* Disable RX interrupt. */ UART_DisableInterrupts(base, kUART_RxDataRegFullInterruptEnable | kUART_RxOverrunInterruptEnable | - kUART_FramingErrorInterruptEnable); + kUART_FramingErrorInterruptEnable | kUART_IdleLineInterruptEnable); /* Disable parity error interrupt when parity mode is enable*/ if (UART_C1_PE_MASK & base->C1) { @@ -906,6 +1185,18 @@ void UART_TransferAbortReceive(UART_Type *base, uart_handle_t *handle) handle->rxState = kUART_RxIdle; } +/*! + * brief Gets the number of bytes that have been received. + * + * This function gets the number of bytes that have been received. + * + * param base UART peripheral base address. + * param handle UART handle pointer. + * param count Receive bytes count. + * retval kStatus_NoTransferInProgress No receive in progress. + * retval kStatus_InvalidArgument Parameter is invalid. + * retval kStatus_Success Get successfully through the parameter \p count; + */ status_t UART_TransferGetReceiveCount(UART_Type *base, uart_handle_t *handle, uint32_t *count) { assert(handle); @@ -926,15 +1217,24 @@ status_t UART_TransferGetReceiveCount(UART_Type *base, uart_handle_t *handle, ui return kStatus_Success; } +/*! + * brief UART IRQ handle function. + * + * This function handles the UART transmit and receive IRQ request. + * + * param base UART peripheral base address. + * param handle UART handle pointer. + */ void UART_TransferHandleIRQ(UART_Type *base, uart_handle_t *handle) { assert(handle); uint8_t count; uint8_t tempCount; + uint32_t status = UART_GetStatusFlags(base); /* If RX framing error */ - if (UART_S1_FE_MASK & base->S1) + if (kUART_FramingErrorFlag & status) { /* Read base->D to clear framing error flag, otherwise the RX does not work. */ while (base->S1 & UART_S1_RDRF_MASK) @@ -956,7 +1256,7 @@ void UART_TransferHandleIRQ(UART_Type *base, uart_handle_t *handle) } /* If RX parity error */ - if (UART_S1_PF_MASK & base->S1) + if (kUART_ParityErrorFlag & status) { /* Read base->D to clear parity error flag, otherwise the RX does not work. */ while (base->S1 & UART_S1_RDRF_MASK) @@ -978,7 +1278,7 @@ void UART_TransferHandleIRQ(UART_Type *base, uart_handle_t *handle) } /* If RX overrun. */ - if (UART_S1_OR_MASK & base->S1) + if (kUART_RxOverrunFlag & status) { /* Read base->D to clear overrun flag, otherwise the RX does not work. */ while (base->S1 & UART_S1_RDRF_MASK) @@ -996,8 +1296,67 @@ void UART_TransferHandleIRQ(UART_Type *base, uart_handle_t *handle) } } + /* If IDLE line was detected. */ + if ((kUART_IdleLineFlag & status) && (UART_C2_ILIE_MASK & base->C2)) + { +#if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO + /* If still some data in the FIFO, read out these data to user data buffer. */ + count = base->RCFIFO; + /* If handle->rxDataSize is not 0, first save data to handle->rxData. */ + while ((count) && (handle->rxDataSize)) + { + tempCount = MIN(handle->rxDataSize, count); + + /* Using non block API to read the data from the registers. */ + UART_ReadNonBlocking(base, handle->rxData, tempCount); + handle->rxData += tempCount; + handle->rxDataSize -= tempCount; + count -= tempCount; + + /* If all the data required for upper layer is ready, trigger callback. */ + if (!handle->rxDataSize) + { + handle->rxState = kUART_RxIdle; + + /* Disable RX interrupt/overrun interrupt/fram error/idle line detected interrupt */ + UART_DisableInterrupts(base, kUART_RxDataRegFullInterruptEnable | kUART_RxOverrunInterruptEnable | + kUART_FramingErrorInterruptEnable); + + /* Disable parity error interrupt when parity mode is enable*/ + if (UART_C1_PE_MASK & base->C1) + { + UART_DisableInterrupts(base, kUART_ParityErrorInterruptEnable); + } + + if (handle->callback) + { + handle->callback(base, handle, kStatus_UART_RxIdle, handle->userData); + } + } + } +#endif + /* To clear IDLE, read UART status S1 with IDLE set and then read D.*/ + while (UART_S1_IDLE_MASK & base->S1) + { + (void)base->D; + } +#if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO + /* Flush FIFO date, otherwise FIFO pointer will be in unknown state. */ + base->CFIFO |= UART_CFIFO_RXFLUSH_MASK; +#endif + /* If rxDataSize is 0, disable idle line interrupt.*/ + if (!(handle->rxDataSize)) + { + UART_DisableInterrupts(base, kUART_IdleLineInterruptEnable); + } + /* If callback is not NULL and rxDataSize is not 0. */ + if ((handle->callback) && (handle->rxDataSize)) + { + handle->callback(base, handle, kStatus_UART_IdleLineDetected, handle->userData); + } + } /* Receive data register full */ - if ((UART_S1_RDRF_MASK & base->S1) && (UART_C2_RIE_MASK & base->C2)) + if ((kUART_RxDataRegFullFlag & status) && (UART_C2_RIE_MASK & base->C2)) { /* Get the size that can be stored into buffer for this interrupt. */ #if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO @@ -1078,7 +1437,7 @@ void UART_TransferHandleIRQ(UART_Type *base, uart_handle_t *handle) else if (!handle->rxDataSize) { - /* Disable RX interrupt/overrun interrupt/fram error interrupt */ + /* Disable RX interrupt/overrun interrupt/fram error/idle line detected interrupt */ UART_DisableInterrupts(base, kUART_RxDataRegFullInterruptEnable | kUART_RxOverrunInterruptEnable | kUART_FramingErrorInterruptEnable); @@ -1098,7 +1457,7 @@ void UART_TransferHandleIRQ(UART_Type *base, uart_handle_t *handle) (!handle->rxRingBuffer)) { UART_DisableInterrupts(base, kUART_RxDataRegFullInterruptEnable | kUART_RxOverrunInterruptEnable | - kUART_FramingErrorInterruptEnable); + kUART_FramingErrorInterruptEnable | kUART_IdleLineInterruptEnable); /* Disable parity error interrupt when parity mode is enable*/ if (UART_C1_PE_MASK & base->C1) @@ -1108,7 +1467,7 @@ void UART_TransferHandleIRQ(UART_Type *base, uart_handle_t *handle) } /* Send data register empty and the interrupt is enabled. */ - if ((base->S1 & UART_S1_TDRE_MASK) && (base->C2 & UART_C2_TIE_MASK)) + if ((kUART_TxDataRegEmptyFlag & status) && (base->C2 & UART_C2_TIE_MASK)) { /* Get the bytes that available at this moment. */ #if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO @@ -1149,6 +1508,14 @@ void UART_TransferHandleIRQ(UART_Type *base, uart_handle_t *handle) } } +/*! + * brief UART Error IRQ handle function. + * + * This function handles the UART error IRQ request. + * + * param base UART peripheral base address. + * param handle UART handle pointer. + */ void UART_TransferHandleErrorIRQ(UART_Type *base, uart_handle_t *handle) { /* To be implemented by User. */ @@ -1160,11 +1527,21 @@ void UART_TransferHandleErrorIRQ(UART_Type *base, uart_handle_t *handle) void UART0_DriverIRQHandler(void) { s_uartIsr(UART0, s_uartHandle[0]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif } void UART0_RX_TX_DriverIRQHandler(void) { UART0_DriverIRQHandler(); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif } #endif #endif @@ -1173,11 +1550,21 @@ void UART0_RX_TX_DriverIRQHandler(void) void UART1_DriverIRQHandler(void) { s_uartIsr(UART1, s_uartHandle[1]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif } void UART1_RX_TX_DriverIRQHandler(void) { UART1_DriverIRQHandler(); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif } #endif @@ -1185,11 +1572,21 @@ void UART1_RX_TX_DriverIRQHandler(void) void UART2_DriverIRQHandler(void) { s_uartIsr(UART2, s_uartHandle[2]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif } void UART2_RX_TX_DriverIRQHandler(void) { UART2_DriverIRQHandler(); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif } #endif @@ -1197,11 +1594,21 @@ void UART2_RX_TX_DriverIRQHandler(void) void UART3_DriverIRQHandler(void) { s_uartIsr(UART3, s_uartHandle[3]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif } void UART3_RX_TX_DriverIRQHandler(void) { UART3_DriverIRQHandler(); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif } #endif @@ -1209,11 +1616,21 @@ void UART3_RX_TX_DriverIRQHandler(void) void UART4_DriverIRQHandler(void) { s_uartIsr(UART4, s_uartHandle[4]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif } void UART4_RX_TX_DriverIRQHandler(void) { UART4_DriverIRQHandler(); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif } #endif @@ -1221,10 +1638,20 @@ void UART4_RX_TX_DriverIRQHandler(void) void UART5_DriverIRQHandler(void) { s_uartIsr(UART5, s_uartHandle[5]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif } void UART5_RX_TX_DriverIRQHandler(void) { UART5_DriverIRQHandler(); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif } #endif diff --git a/ext/hal/nxp/mcux/drivers/kinetis/fsl_uart.h b/ext/hal/nxp/mcux/drivers/kinetis/fsl_uart.h index 451baa9ffd3..4a810443d2b 100644 --- a/ext/hal/nxp/mcux/drivers/kinetis/fsl_uart.h +++ b/ext/hal/nxp/mcux/drivers/kinetis/fsl_uart.h @@ -1,31 +1,9 @@ /* * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP + * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * SPDX-License-Identifier: BSD-3-Clause */ #ifndef _FSL_UART_H_ #define _FSL_UART_H_ @@ -43,8 +21,8 @@ /*! @name Driver version */ /*@{*/ -/*! @brief UART driver version 2.1.4. */ -#define FSL_UART_DRIVER_VERSION (MAKE_VERSION(2, 1, 4)) +/*! @brief UART driver version 2.1.6. */ +#define FSL_UART_DRIVER_VERSION (MAKE_VERSION(2, 1, 6)) /*@}*/ /*! @brief Error codes for the UART driver. */ @@ -66,6 +44,7 @@ enum _uart_status kStatus_UART_ParityError = MAKE_STATUS(kStatusGroup_UART, 12), /*!< UART parity error. */ kStatus_UART_BaudrateNotSupport = MAKE_STATUS(kStatusGroup_UART, 13), /*!< Baudrate is not support in current clock source */ + kStatus_UART_IdleLineDetected = MAKE_STATUS(kStatusGroup_UART, 14), /*!< UART IDLE line detected. */ }; /*! @brief UART parity mode. */ @@ -83,6 +62,13 @@ typedef enum _uart_stop_bit_count kUART_TwoStopBit = 1U, /*!< Two stop bits */ } uart_stop_bit_count_t; +/*! @brief UART idle type select. */ +typedef enum _uart_idle_type_select +{ + kUART_IdleTypeStartBit = 0U, /*!< Start counting after a valid start bit. */ + kUART_IdleTypeStopBit = 1U, /*!< Start counting after a stop bit. */ +} uart_idle_type_select_t; + /*! * @brief UART interrupt configuration structure, default settings all disabled. * @@ -142,25 +128,22 @@ enum _uart_flags #if defined(FSL_FEATURE_UART_HAS_LIN_BREAK_DETECT) && FSL_FEATURE_UART_HAS_LIN_BREAK_DETECT kUART_LinBreakFlag = (UART_S2_LBKDIF_MASK - << 8), /*!< LIN break detect interrupt flag, sets when - LIN break char detected and LIN circuit enabled */ + << 8), /*!< LIN break detect interrupt flag, sets when LIN break char detected and LIN circuit enabled */ #endif kUART_RxActiveEdgeFlag = - (UART_S2_RXEDGIF_MASK << 8), /*!< RX pin active edge interrupt flag, - sets when active edge detected */ + (UART_S2_RXEDGIF_MASK << 8), /*!< RX pin active edge interrupt flag,sets when active edge detected */ kUART_RxActiveFlag = - (UART_S2_RAF_MASK << 8), /*!< Receiver Active Flag (RAF), - sets at beginning of valid start bit */ + (UART_S2_RAF_MASK << 8), /*!< Receiver Active Flag (RAF), sets at beginning of valid start bit */ #if defined(FSL_FEATURE_UART_HAS_EXTENDED_DATA_REGISTER_FLAGS) && FSL_FEATURE_UART_HAS_EXTENDED_DATA_REGISTER_FLAGS kUART_NoiseErrorInRxDataRegFlag = (UART_ED_NOISY_MASK << 16), /*!< Noisy bit, sets if noise detected. */ - kUART_ParityErrorInRxDataRegFlag = (UART_ED_PARITYE_MASK << 16), /*!< Paritye bit, sets if parity error detected. */ + kUART_ParityErrorInRxDataRegFlag = (UART_ED_PARITYE_MASK << 16), /*!< Parity bit, sets if parity error detected. */ #endif #if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO - kUART_TxFifoEmptyFlag = (UART_SFIFO_TXEMPT_MASK << 24), /*!< TXEMPT bit, sets if TX buffer is empty */ - kUART_RxFifoEmptyFlag = (UART_SFIFO_RXEMPT_MASK << 24), /*!< RXEMPT bit, sets if RX buffer is empty */ - kUART_TxFifoOverflowFlag = (UART_SFIFO_TXOF_MASK << 24), /*!< TXOF bit, sets if TX buffer overflow occurred */ - kUART_RxFifoOverflowFlag = (UART_SFIFO_RXOF_MASK << 24), /*!< RXOF bit, sets if receive buffer overflow */ - kUART_RxFifoUnderflowFlag = (UART_SFIFO_RXUF_MASK << 24), /*!< RXUF bit, sets if receive buffer underflow */ + kUART_TxFifoEmptyFlag = (int)(UART_SFIFO_TXEMPT_MASK << 24), /*!< TXEMPT bit, sets if TX buffer is empty */ + kUART_RxFifoEmptyFlag = (UART_SFIFO_RXEMPT_MASK << 24), /*!< RXEMPT bit, sets if RX buffer is empty */ + kUART_TxFifoOverflowFlag = (UART_SFIFO_TXOF_MASK << 24), /*!< TXOF bit, sets if TX buffer overflow occurred */ + kUART_RxFifoOverflowFlag = (UART_SFIFO_RXOF_MASK << 24), /*!< RXOF bit, sets if receive buffer overflow */ + kUART_RxFifoUnderflowFlag = (UART_SFIFO_RXUF_MASK << 24), /*!< RXUF bit, sets if receive buffer underflow */ #endif }; @@ -176,8 +159,13 @@ typedef struct _uart_config uint8_t txFifoWatermark; /*!< TX FIFO watermark */ uint8_t rxFifoWatermark; /*!< RX FIFO watermark */ #endif - bool enableTx; /*!< Enable TX */ - bool enableRx; /*!< Enable RX */ +#if defined(FSL_FEATURE_UART_HAS_MODEM_SUPPORT) && FSL_FEATURE_UART_HAS_MODEM_SUPPORT + bool enableRxRTS; /*!< RX RTS enable */ + bool enableTxCTS; /*!< TX CTS enable */ +#endif + uart_idle_type_select_t idleType; /*!< IDLE type select. */ + bool enableTx; /*!< Enable TX */ + bool enableRx; /*!< Enable RX */ } uart_config_t; /*! @brief UART transfer structure. */ @@ -223,6 +211,14 @@ struct _uart_handle extern "C" { #endif /* _cplusplus */ +/*! + * @brief Get the UART instance from peripheral base address. + * + * @param base UART peripheral base address. + * @return UART instance. + */ +uint32_t UART_GetInstance(UART_Type *base); + /*! * @name Initialization and deinitialization * @{ @@ -272,6 +268,7 @@ void UART_Deinit(UART_Type *base); * uartConfig->stopBitCount = kUART_OneStopBit; * uartConfig->txFifoWatermark = 0; * uartConfig->rxFifoWatermark = 1; + * uartConfig->idleType = kUART_IdleTypeStartBit; * uartConfig->enableTx = false; * uartConfig->enableRx = false; * @@ -643,6 +640,14 @@ void UART_TransferStartRingBuffer(UART_Type *base, uart_handle_t *handle, uint8_ */ void UART_TransferStopRingBuffer(UART_Type *base, uart_handle_t *handle); +/*! + * @brief Get the length of received data in RX ring buffer. + * + * @param handle UART handle pointer. + * @return Length of received data in RX ring buffer. + */ +size_t UART_TransferGetRxRingBufferLength(uart_handle_t *handle); + /*! * @brief Transmits a buffer of data using the interrupt method. * diff --git a/ext/hal/nxp/mcux/drivers/kinetis/fsl_uart_edma.c b/ext/hal/nxp/mcux/drivers/kinetis/fsl_uart_edma.c index c51e4934639..3aa73640754 100644 --- a/ext/hal/nxp/mcux/drivers/kinetis/fsl_uart_edma.c +++ b/ext/hal/nxp/mcux/drivers/kinetis/fsl_uart_edma.c @@ -1,40 +1,22 @@ /* * Copyright (c) 2015, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP + * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * SPDX-License-Identifier: BSD-3-Clause */ #include "fsl_uart_edma.h" -#include "fsl_dmamux.h" /******************************************************************************* * Definitions ******************************************************************************/ +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.uart_edma" +#endif + /* Array of UART handle. */ #if (defined(UART5)) #define UART_HANDLE_ARRAY_SIZE 6 @@ -79,7 +61,7 @@ enum _uart_edma_tansfer_states }; /******************************************************************************* - * Definitions + * Variables ******************************************************************************/ /*txState = kUART_TxIdle; } +/*! + * brief Aborts the receive data using eDMA. + * + * This function aborts receive data using eDMA. + * + * param base UART peripheral base address. + * param handle Pointer to the uart_edma_handle_t structure. + */ void UART_TransferAbortReceiveEDMA(UART_Type *base, uart_edma_handle_t *handle) { assert(handle); @@ -331,6 +356,18 @@ void UART_TransferAbortReceiveEDMA(UART_Type *base, uart_edma_handle_t *handle) handle->rxState = kUART_RxIdle; } +/*! + * brief Gets the number of received bytes. + * + * This function gets the number of received bytes. + * + * param base UART peripheral base address. + * param handle UART handle pointer. + * param count Receive bytes count. + * retval kStatus_NoTransferInProgress No receive in progress. + * retval kStatus_InvalidArgument Parameter is invalid. + * retval kStatus_Success Get successfully through the parameter \p count; + */ status_t UART_TransferGetReceiveCountEDMA(UART_Type *base, uart_edma_handle_t *handle, uint32_t *count) { assert(handle); @@ -349,6 +386,19 @@ status_t UART_TransferGetReceiveCountEDMA(UART_Type *base, uart_edma_handle_t *h return kStatus_Success; } +/*! + * brief Gets the number of bytes that have been written to UART TX register. + * + * This function gets the number of bytes that have been written to UART TX + * register by DMA. + * + * param base UART peripheral base address. + * param handle UART handle pointer. + * param count Send bytes count. + * retval kStatus_NoTransferInProgress No send in progress. + * retval kStatus_InvalidArgument Parameter is invalid. + * retval kStatus_Success Get successfully through the parameter \p count; + */ status_t UART_TransferGetSendCountEDMA(UART_Type *base, uart_edma_handle_t *handle, uint32_t *count) { assert(handle); diff --git a/ext/hal/nxp/mcux/drivers/kinetis/fsl_uart_edma.h b/ext/hal/nxp/mcux/drivers/kinetis/fsl_uart_edma.h index e411ffd7a44..cffec3548e4 100644 --- a/ext/hal/nxp/mcux/drivers/kinetis/fsl_uart_edma.h +++ b/ext/hal/nxp/mcux/drivers/kinetis/fsl_uart_edma.h @@ -1,37 +1,14 @@ /* * Copyright (c) 2015, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP + * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * SPDX-License-Identifier: BSD-3-Clause */ #ifndef _FSL_UART_EDMA_H_ #define _FSL_UART_EDMA_H_ #include "fsl_uart.h" -#include "fsl_dmamux.h" #include "fsl_edma.h" /*! @@ -43,6 +20,12 @@ * Definitions ******************************************************************************/ +/*! @name Driver version */ +/*@{*/ +/*! @brief UART EDMA driver version 2.1.6. */ +#define FSL_UART_EDMA_DRIVER_VERSION (MAKE_VERSION(2, 1, 6)) +/*@}*/ + /* Forward declaration of the handle typedef. */ typedef struct _uart_edma_handle uart_edma_handle_t; diff --git a/ext/hal/nxp/mcux/drivers/kinetis/fsl_vref.c b/ext/hal/nxp/mcux/drivers/kinetis/fsl_vref.c index 24f2d1dc280..a958a075453 100644 --- a/ext/hal/nxp/mcux/drivers/kinetis/fsl_vref.c +++ b/ext/hal/nxp/mcux/drivers/kinetis/fsl_vref.c @@ -1,35 +1,18 @@ /* * Copyright (c) 2015, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP + * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * SPDX-License-Identifier: BSD-3-Clause */ #include "fsl_vref.h" +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.vref" +#endif + /******************************************************************************* * Prototypes ******************************************************************************/ @@ -77,6 +60,25 @@ static uint32_t VREF_GetInstance(VREF_Type *base) return instance; } +/*! + * brief Enables the clock gate and configures the VREF module according to the configuration structure. + * + * This function must be called before calling all other VREF driver functions, + * read/write registers, and configurations with user-defined settings. + * The example below shows how to set up vref_config_t parameters and + * how to call the VREF_Init function by passing in these parameters. + * This is an example. + * code + * vref_config_t vrefConfig; + * vrefConfig.bufferMode = kVREF_ModeHighPowerBuffer; + * vrefConfig.enableExternalVoltRef = false; + * vrefConfig.enableLowRef = false; + * VREF_Init(VREF, &vrefConfig); + * endcode + * + * param base VREF peripheral address. + * param config Pointer to the configuration structure. + */ void VREF_Init(VREF_Type *base, const vref_config_t *config) { assert(config != NULL); @@ -93,12 +95,12 @@ void VREF_Init(VREF_Type *base, const vref_config_t *config) /* Set chop oscillator bit */ base->TRM |= VREF_TRM_CHOPEN_MASK; #endif /* FSL_FEATURE_VREF_HAS_CHOP_OSC */ - /* Get current SC register */ +/* Get current SC register */ #if defined(FSL_FEATURE_VREF_HAS_LOW_REFERENCE) && FSL_FEATURE_VREF_HAS_LOW_REFERENCE reg = base->VREFH_SC; #else reg = base->SC; -#endif/* FSL_FEATURE_VREF_HAS_LOW_REFERENCE */ +#endif /* FSL_FEATURE_VREF_HAS_LOW_REFERENCE */ /* Clear old buffer mode selection bits */ reg &= ~VREF_SC_MODE_LV_MASK; /* Set buffer Mode selection and Regulator enable bit */ @@ -109,12 +111,12 @@ void VREF_Init(VREF_Type *base, const vref_config_t *config) #endif /* FSL_FEATURE_VREF_HAS_COMPENSATION */ /* Enable VREF module */ reg |= VREF_SC_VREFEN(1U); - /* Update bit-field from value to Status and Control register */ +/* Update bit-field from value to Status and Control register */ #if defined(FSL_FEATURE_VREF_HAS_LOW_REFERENCE) && FSL_FEATURE_VREF_HAS_LOW_REFERENCE base->VREFH_SC = reg; #else base->SC = reg; -#endif/* FSL_FEATURE_VREF_HAS_LOW_REFERENCE */ +#endif /* FSL_FEATURE_VREF_HAS_LOW_REFERENCE */ #if defined(FSL_FEATURE_VREF_HAS_LOW_REFERENCE) && FSL_FEATURE_VREF_HAS_LOW_REFERENCE reg = base->VREFL_TRM; /* Clear old select external voltage reference and VREFL (0.4 V) reference buffer enable bits */ @@ -133,16 +135,31 @@ void VREF_Init(VREF_Type *base, const vref_config_t *config) base->TRM4 = reg; #endif /* FSL_FEATURE_VREF_HAS_TRM4 */ - /* Wait until internal voltage stable */ +/* Wait until internal voltage stable */ #if defined(FSL_FEATURE_VREF_HAS_LOW_REFERENCE) && FSL_FEATURE_VREF_HAS_LOW_REFERENCE - while ((base->VREFH_SC & VREF_SC_VREFST_MASK) == 0) + while ((base->VREFH_SC & VREF_SC_VREFST_MASK) == 0) #else while ((base->SC & VREF_SC_VREFST_MASK) == 0) -#endif/* FSL_FEATURE_VREF_HAS_LOW_REFERENCE */ +#endif /* FSL_FEATURE_VREF_HAS_LOW_REFERENCE */ { } } +/*! + * brief Stops and disables the clock for the VREF module. + * + * This function should be called to shut down the module. + * This is an example. + * code + * vref_config_t vrefUserConfig; + * VREF_Init(VREF); + * VREF_GetDefaultConfig(&vrefUserConfig); + * ... + * VREF_Deinit(VREF); + * endcode + * + * param base VREF peripheral address. + */ void VREF_Deinit(VREF_Type *base) { #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) @@ -151,10 +168,26 @@ void VREF_Deinit(VREF_Type *base) #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ } +/*! + * brief Initializes the VREF configuration structure. + * + * This function initializes the VREF configuration structure to default values. + * This is an example. + * code + * vrefConfig->bufferMode = kVREF_ModeHighPowerBuffer; + * vrefConfig->enableExternalVoltRef = false; + * vrefConfig->enableLowRef = false; + * endcode + * + * param config Pointer to the initialization structure. + */ void VREF_GetDefaultConfig(vref_config_t *config) { assert(config); + /* Initializes the configure structure to zero. */ + memset(config, 0, sizeof(*config)); + /* Set High power buffer mode in */ #if defined(FSL_FEATURE_VREF_MODE_LV_TYPE) && FSL_FEATURE_VREF_MODE_LV_TYPE config->bufferMode = kVREF_ModeHighPowerBuffer; @@ -175,6 +208,15 @@ void VREF_GetDefaultConfig(vref_config_t *config) #endif /* FSL_FEATURE_VREF_HAS_TRM4 */ } +/*! + * brief Sets a TRIM value for the reference voltage. + * + * This function sets a TRIM value for the reference voltage. + * Note that the TRIM value maximum is 0x3F. + * + * param base VREF peripheral address. + * param trimValue Value of the trim register to set the output reference voltage (maximum 0x3F (6-bit)). + */ void VREF_SetTrimVal(VREF_Type *base, uint8_t trimValue) { uint8_t reg = 0U; @@ -183,17 +225,26 @@ void VREF_SetTrimVal(VREF_Type *base, uint8_t trimValue) reg = base->TRM; reg = ((reg & ~VREF_TRM_TRIM_MASK) | VREF_TRM_TRIM(trimValue)); base->TRM = reg; - /* Wait until internal voltage stable */ +/* Wait until internal voltage stable */ #if defined(FSL_FEATURE_VREF_HAS_LOW_REFERENCE) && FSL_FEATURE_VREF_HAS_LOW_REFERENCE - while ((base->VREFH_SC & VREF_SC_VREFST_MASK) == 0) + while ((base->VREFH_SC & VREF_SC_VREFST_MASK) == 0) #else while ((base->SC & VREF_SC_VREFST_MASK) == 0) -#endif/* FSL_FEATURE_VREF_HAS_LOW_REFERENCE */ +#endif /* FSL_FEATURE_VREF_HAS_LOW_REFERENCE */ { } } #if defined(FSL_FEATURE_VREF_HAS_TRM4) && FSL_FEATURE_VREF_HAS_TRM4 +/*! + * brief Sets a TRIM value for the reference voltage (2V1). + * + * This function sets a TRIM value for the reference voltage (2V1). + * Note that the TRIM value maximum is 0x3F. + * + * param base VREF peripheral address. + * param trimValue Value of the trim register to set the output reference voltage (maximum 0x3F (6-bit)). + */ void VREF_SetTrim2V1Val(VREF_Type *base, uint8_t trimValue) { uint8_t reg = 0U; @@ -210,6 +261,17 @@ void VREF_SetTrim2V1Val(VREF_Type *base, uint8_t trimValue) #endif /* FSL_FEATURE_VREF_HAS_TRM4 */ #if defined(FSL_FEATURE_VREF_HAS_LOW_REFERENCE) && FSL_FEATURE_VREF_HAS_LOW_REFERENCE +/*! + * brief Sets the TRIM value for the low voltage reference. + * + * This function sets the TRIM value for low reference voltage. + * Note the following. + * - The TRIM value maximum is 0x05U + * - The values 111b and 110b are not valid/allowed. + * + * param base VREF peripheral address. + * param trimValue Value of the trim register to set output low reference voltage (maximum 0x05U (3-bit)). + */ void VREF_SetLowReferenceTrimVal(VREF_Type *base, uint8_t trimValue) { /* The values 111b and 110b are NOT valid/allowed */ @@ -223,7 +285,7 @@ void VREF_SetLowReferenceTrimVal(VREF_Type *base, uint8_t trimValue) base->VREFL_TRM = reg; /* Wait until internal voltage stable */ - while ((base->VREFH_SC & VREF_SC_VREFST_MASK) == 0) + while ((base->VREFH_SC & VREF_SC_VREFST_MASK) == 0) { } } diff --git a/ext/hal/nxp/mcux/drivers/kinetis/fsl_vref.h b/ext/hal/nxp/mcux/drivers/kinetis/fsl_vref.h index 6c6c014b913..d049f6c1562 100644 --- a/ext/hal/nxp/mcux/drivers/kinetis/fsl_vref.h +++ b/ext/hal/nxp/mcux/drivers/kinetis/fsl_vref.h @@ -1,31 +1,9 @@ /* * Copyright (c) 2015, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause */ #ifndef _FSL_VREF_H_ diff --git a/ext/hal/nxp/mcux/drivers/kinetis/fsl_wdog.c b/ext/hal/nxp/mcux/drivers/kinetis/fsl_wdog.c index 781ac133c1a..4c15707ab5b 100644 --- a/ext/hal/nxp/mcux/drivers/kinetis/fsl_wdog.c +++ b/ext/hal/nxp/mcux/drivers/kinetis/fsl_wdog.c @@ -1,43 +1,51 @@ /* * Copyright (c) 2015, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP + * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * SPDX-License-Identifier: BSD-3-Clause */ #include "fsl_wdog.h" +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.wdog" +#endif + /******************************************************************************* * Code ******************************************************************************/ +/*! + * brief Initializes the WDOG configuration sturcture. + * + * This function initializes the WDOG configuration structure to default values. The default + * values are as follows. + * code + * wdogConfig->enableWdog = true; + * wdogConfig->clockSource = kWDOG_LpoClockSource; + * wdogConfig->prescaler = kWDOG_ClockPrescalerDivide1; + * wdogConfig->workMode.enableWait = true; + * wdogConfig->workMode.enableStop = false; + * wdogConfig->workMode.enableDebug = false; + * wdogConfig->enableUpdate = true; + * wdogConfig->enableInterrupt = false; + * wdogConfig->enableWindowMode = false; + * wdogConfig->windowValue = 0; + * wdogConfig->timeoutValue = 0xFFFFU; + * endcode + * + * param config Pointer to the WDOG configuration structure. + * see wdog_config_t + */ void WDOG_GetDefaultConfig(wdog_config_t *config) { assert(config); + /* Initializes the configure structure to zero. */ + memset(config, 0, sizeof(*config)); + config->enableWdog = true; config->clockSource = kWDOG_LpoClockSource; config->prescaler = kWDOG_ClockPrescalerDivide1; @@ -53,6 +61,25 @@ void WDOG_GetDefaultConfig(wdog_config_t *config) config->timeoutValue = 0xFFFFU; } +/*! + * brief Initializes the WDOG. + * + * This function initializes the WDOG. When called, the WDOG runs according to the configuration. + * To reconfigure WDOG without forcing a reset first, enableUpdate must be set to true + * in the configuration. + * + * This is an example. + * code + * wdog_config_t config; + * WDOG_GetDefaultConfig(&config); + * config.timeoutValue = 0x7ffU; + * config.enableUpdate = true; + * WDOG_Init(wdog_base,&config); + * endcode + * + * param base WDOG peripheral base address + * param config The configuration of WDOG + */ void WDOG_Init(WDOG_Type *base, const wdog_config_t *config) { assert(config); @@ -85,6 +112,12 @@ void WDOG_Init(WDOG_Type *base, const wdog_config_t *config) EnableGlobalIRQ(primaskValue); } +/*! + * brief Shuts down the WDOG. + * + * This function shuts down the WDOG. + * Ensure that the WDOG_STCTRLH.ALLOWUPDATE is 1 which indicates that the register update is enabled. + */ void WDOG_Deinit(WDOG_Type *base) { uint32_t primaskValue = 0U; @@ -99,6 +132,23 @@ void WDOG_Deinit(WDOG_Type *base) WDOG_ClearResetCount(base); } +/*! + * brief Configures the WDOG functional test. + * + * This function is used to configure the WDOG functional test. When called, the WDOG goes into test mode + * and runs according to the configuration. + * Ensure that the WDOG_STCTRLH.ALLOWUPDATE is 1 which means that the register update is enabled. + * + * This is an example. + * code + * wdog_test_config_t test_config; + * test_config.testMode = kWDOG_QuickTest; + * test_config.timeoutValue = 0xfffffu; + * WDOG_SetTestModeConfig(wdog_base, &test_config); + * endcode + * param base WDOG peripheral base address + * param config The functional test configuration of WDOG + */ void WDOG_SetTestModeConfig(WDOG_Type *base, wdog_test_config_t *config) { assert(config); @@ -123,6 +173,21 @@ void WDOG_SetTestModeConfig(WDOG_Type *base, wdog_test_config_t *config) EnableGlobalIRQ(primaskValue); } +/*! + * brief Gets the WDOG all status flags. + * + * This function gets all status flags. + * + * This is an example for getting the Running Flag. + * code + * uint32_t status; + * status = WDOG_GetStatusFlags (wdog_base) & kWDOG_RunningFlag; + * endcode + * param base WDOG peripheral base address + * return State of the status flag: asserted (true) or not-asserted (false).see _wdog_status_flags_t + * - true: a related status flag has been set. + * - false: a related status flag is not set. + */ uint32_t WDOG_GetStatusFlags(WDOG_Type *base) { uint32_t status_flag = 0U; @@ -133,6 +198,20 @@ uint32_t WDOG_GetStatusFlags(WDOG_Type *base) return status_flag; } +/*! + * brief Clears the WDOG flag. + * + * This function clears the WDOG status flag. + * + * This is an example for clearing the timeout (interrupt) flag. + * code + * WDOG_ClearStatusFlags(wdog_base,kWDOG_TimeoutFlag); + * endcode + * param base WDOG peripheral base address + * param mask The status flags to clear. + * The parameter could be any combination of the following values. + * kWDOG_TimeoutFlag + */ void WDOG_ClearStatusFlags(WDOG_Type *base, uint32_t mask) { if (mask & kWDOG_TimeoutFlag) @@ -141,6 +220,14 @@ void WDOG_ClearStatusFlags(WDOG_Type *base, uint32_t mask) } } +/*! + * brief Refreshes the WDOG timer. + * + * This function feeds the WDOG. + * This function should be called before the WDOG timer is in timeout. Otherwise, a reset is asserted. + * + * param base WDOG peripheral base address + */ void WDOG_Refresh(WDOG_Type *base) { uint32_t primaskValue = 0U; diff --git a/ext/hal/nxp/mcux/drivers/kinetis/fsl_wdog.h b/ext/hal/nxp/mcux/drivers/kinetis/fsl_wdog.h index 580adb95a0f..a573f75f9d5 100644 --- a/ext/hal/nxp/mcux/drivers/kinetis/fsl_wdog.h +++ b/ext/hal/nxp/mcux/drivers/kinetis/fsl_wdog.h @@ -1,31 +1,9 @@ /* * Copyright (c) 2015, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause */ #ifndef _FSL_WDOG_H_ #define _FSL_WDOG_H_ diff --git a/ext/hal/nxp/mcux/drivers/lpc/CMakeLists.txt b/ext/hal/nxp/mcux/drivers/lpc/CMakeLists.txt index 2faff464195..1cc9916af78 100644 --- a/ext/hal/nxp/mcux/drivers/lpc/CMakeLists.txt +++ b/ext/hal/nxp/mcux/drivers/lpc/CMakeLists.txt @@ -6,4 +6,5 @@ zephyr_include_directories(.) +zephyr_sources(fsl_reset.c) zephyr_sources_ifdef(CONFIG_USART_MCUX_LPC fsl_usart.c fsl_flexcomm.c) diff --git a/ext/hal/nxp/mcux/drivers/lpc/fsl_adc.c b/ext/hal/nxp/mcux/drivers/lpc/fsl_adc.c index 2c8b2cb1110..c9272ec660d 100644 --- a/ext/hal/nxp/mcux/drivers/lpc/fsl_adc.c +++ b/ext/hal/nxp/mcux/drivers/lpc/fsl_adc.c @@ -1,36 +1,19 @@ /* * Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP + * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * SPDX-License-Identifier: BSD-3-Clause */ #include "fsl_adc.h" #include "fsl_clock.h" +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.lpc_adc" +#endif + static ADC_Type *const s_adcBases[] = ADC_BASE_PTRS; #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) static const clock_ip_name_t s_adcClocks[] = ADC_CLOCKS; @@ -54,6 +37,12 @@ static uint32_t ADC_GetInstance(ADC_Type *base) return instance; } +/*! + * brief Initialize the ADC module. + * + * param base ADC peripheral base address. + * param config Pointer to configuration structure, see to #adc_config_t. + */ void ADC_Init(ADC_Type *base, const adc_config_t *config) { assert(config != NULL); @@ -71,6 +60,7 @@ void ADC_Init(ADC_Type *base, const adc_config_t *config) /* Configure the ADC block. */ tmp32 = ADC_CTRL_CLKDIV(config->clockDividerNumber); +#if defined(FSL_FEATURE_ADC_HAS_CTRL_ASYNMODE) & FSL_FEATURE_ADC_HAS_CTRL_ASYNMODE /* Async or Sync clock mode. */ switch (config->clockMode) { @@ -80,31 +70,87 @@ void ADC_Init(ADC_Type *base, const adc_config_t *config) default: /* kADC_ClockSynchronousMode */ break; } +#endif /* FSL_FEATURE_ADC_HAS_CTRL_ASYNMODE. */ +#if defined(FSL_FEATURE_ADC_HAS_CTRL_RESOL) & FSL_FEATURE_ADC_HAS_CTRL_RESOL /* Resolution. */ tmp32 |= ADC_CTRL_RESOL(config->resolution); +#endif /* FSL_FEATURE_ADC_HAS_CTRL_RESOL. */ +#if defined(FSL_FEATURE_ADC_HAS_CTRL_BYPASSCAL) & FSL_FEATURE_ADC_HAS_CTRL_BYPASSCAL /* Bypass calibration. */ if (config->enableBypassCalibration) { tmp32 |= ADC_CTRL_BYPASSCAL_MASK; } +#endif /* FSL_FEATURE_ADC_HAS_CTRL_BYPASSCAL. */ +#if defined(FSL_FEATURE_ADC_HAS_CTRL_TSAMP) & FSL_FEATURE_ADC_HAS_CTRL_TSAMP /* Sample time clock count. */ tmp32 |= ADC_CTRL_TSAMP(config->sampleTimeNumber); +#endif /* FSL_FEATURE_ADC_HAS_CTRL_TSAMP. */ + +#if defined(FSL_FEATURE_ADC_HAS_CTRL_LPWRMODE) & FSL_FEATURE_ADC_HAS_CTRL_LPWRMODE + if (config->enableLowPowerMode) + { + tmp32 |= ADC_CTRL_LPWRMODE_MASK; + } +#endif /* FSL_FEATURE_ADC_HAS_CTRL_LPWRMODE. */ base->CTRL = tmp32; + +#if defined(FSL_FEATURE_ADC_HAS_TRIM_REG) & FSL_FEATURE_ADC_HAS_TRIM_REG + base->TRM &= ~ADC_TRM_VRANGE_MASK; + base->TRM |= ADC_TRM_VRANGE(config->voltageRange); +#endif /* FSL_FEATURE_ADC_HAS_TRIM_REG. */ } +/*! + * brief Gets an available pre-defined settings for initial configuration. + * + * This function initializes the initial configuration structure with an available settings. The default values are: + * code + * config->clockMode = kADC_ClockSynchronousMode; + * config->clockDividerNumber = 0U; + * config->resolution = kADC_Resolution12bit; + * config->enableBypassCalibration = false; + * config->sampleTimeNumber = 0U; + * endcode + * param config Pointer to configuration structure. + */ void ADC_GetDefaultConfig(adc_config_t *config) { + /* Initializes the configure structure to zero. */ + memset(config, 0, sizeof(*config)); + +#if defined(FSL_FEATURE_ADC_HAS_CTRL_ASYNMODE) & FSL_FEATURE_ADC_HAS_CTRL_ASYNMODE + config->clockMode = kADC_ClockSynchronousMode; +#endif /* FSL_FEATURE_ADC_HAS_CTRL_ASYNMODE. */ + config->clockDividerNumber = 0U; +#if defined(FSL_FEATURE_ADC_HAS_CTRL_RESOL) & FSL_FEATURE_ADC_HAS_CTRL_RESOL config->resolution = kADC_Resolution12bit; +#endif /* FSL_FEATURE_ADC_HAS_CTRL_RESOL. */ +#if defined(FSL_FEATURE_ADC_HAS_CTRL_BYPASSCAL) & FSL_FEATURE_ADC_HAS_CTRL_BYPASSCAL config->enableBypassCalibration = false; +#endif /* FSL_FEATURE_ADC_HAS_CTRL_BYPASSCAL. */ +#if defined(FSL_FEATURE_ADC_HAS_CTRL_TSAMP) & FSL_FEATURE_ADC_HAS_CTRL_TSAMP config->sampleTimeNumber = 0U; +#endif /* FSL_FEATURE_ADC_HAS_CTRL_TSAMP. */ +#if defined(FSL_FEATURE_ADC_HAS_CTRL_LPWRMODE) & FSL_FEATURE_ADC_HAS_CTRL_LPWRMODE + config->enableLowPowerMode = false; +#endif /* FSL_FEATURE_ADC_HAS_CTRL_LPWRMODE. */ +#if defined(FSL_FEATURE_ADC_HAS_TRIM_REG) & FSL_FEATURE_ADC_HAS_TRIM_REG + config->voltageRange = kADC_HighVoltageRange; +#endif /* FSL_FEATURE_ADC_HAS_TRIM_REG. */ } +/*! + * brief Deinitialize the ADC module. + * + * param base ADC peripheral base address. + */ void ADC_Deinit(ADC_Type *base) { #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) @@ -113,6 +159,18 @@ void ADC_Deinit(ADC_Type *base) #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ } +#if !(defined(FSL_FEATURE_ADC_HAS_NO_CALIB_FUNC) && FSL_FEATURE_ADC_HAS_NO_CALIB_FUNC) +#if defined(FSL_FEATURE_ADC_HAS_CALIB_REG) & FSL_FEATURE_ADC_HAS_CALIB_REG +/*! + * brief Do the self calibration. To calibrate the ADC, set the ADC clock to 500 kHz. + * In order to achieve the specified ADC accuracy, the A/D converter must be recalibrated, at a minimum, + * following every chip reset before initiating normal ADC operation. + * + * param base ADC peripheral base address. + * param frequency The ststem clock frequency to ADC. + * retval true Calibration succeed. + * retval false Calibration failed. + */ bool ADC_DoSelfCalibration(ADC_Type *base) { uint32_t i; @@ -159,7 +217,59 @@ bool ADC_DoSelfCalibration(ADC_Type *base) return true; } +#else +/*! + * brief Do the self calibration. To calibrate the ADC, set the ADC clock to 500 kHz. + * In order to achieve the specified ADC accuracy, the A/D converter must be recalibrated, at a minimum, + * following every chip reset before initiating normal ADC operation. + * + * param base ADC peripheral base address. + * param frequency The ststem clock frequency to ADC. + * retval true Calibration succeed. + * retval false Calibration failed. + */ +bool ADC_DoSelfCalibration(ADC_Type *base, uint32_t frequency) +{ + uint32_t tmp32; + uint32_t i = 0xF0000; + /* Store the current contents of the ADC CTRL register. */ + tmp32 = base->CTRL; + + /* Start ADC self-calibration. */ + base->CTRL |= ADC_CTRL_CALMODE_MASK; + + /* Divide the system clock to yield an ADC clock of about 500 kHz. */ + base->CTRL &= ~ADC_CTRL_CLKDIV_MASK; + base->CTRL |= ADC_CTRL_CLKDIV((frequency / 500000U) - 1U); + + /* Clear the LPWR bit. */ + base->CTRL &= ~ADC_CTRL_LPWRMODE_MASK; + + /* Wait for the completion of calibration. */ + while ((ADC_CTRL_CALMODE_MASK == (base->CTRL & ADC_CTRL_CALMODE_MASK)) && (--i)) + { + } + /* Restore the contents of the ADC CTRL register. */ + base->CTRL = tmp32; + + /* Judge whether the calibration is overtime. */ + if (i == 0U) + { + return false; /* Calibration timeout. */ + } + + return true; +} +#endif /* FSL_FEATURE_ADC_HAS_CALIB_REG */ +#endif /* FSL_FEATURE_ADC_HAS_NO_CALIB_FUNC*/ + +/*! + * brief Configure the conversion sequence A. + * + * param base ADC peripheral base address. + * param config Pointer to configuration structure, see to #adc_conv_seq_config_t. + */ void ADC_SetConvSeqAConfig(ADC_Type *base, const adc_conv_seq_config_t *config) { assert(config != NULL); @@ -204,6 +314,12 @@ void ADC_SetConvSeqAConfig(ADC_Type *base, const adc_conv_seq_config_t *config) base->SEQ_CTRL[0] = tmp32; } +/*! + * brief Configure the conversion sequence B. + * + * param base ADC peripheral base address. + * param config Pointer to configuration structure, see to #adc_conv_seq_config_t. + */ void ADC_SetConvSeqBConfig(ADC_Type *base, const adc_conv_seq_config_t *config) { assert(config != NULL); @@ -248,6 +364,14 @@ void ADC_SetConvSeqBConfig(ADC_Type *base, const adc_conv_seq_config_t *config) base->SEQ_CTRL[1] = tmp32; } +/*! + * brief Get the global ADC conversion infomation of sequence A. + * + * param base ADC peripheral base address. + * param info Pointer to information structure, see to #adc_result_info_t; + * retval true The conversion result is ready. + * retval false The conversion result is not ready yet. + */ bool ADC_GetConvSeqAGlobalConversionResult(ADC_Type *base, adc_result_info_t *info) { assert(info != NULL); @@ -270,6 +394,14 @@ bool ADC_GetConvSeqAGlobalConversionResult(ADC_Type *base, adc_result_info_t *in return true; } +/*! + * brief Get the global ADC conversion infomation of sequence B. + * + * param base ADC peripheral base address. + * param info Pointer to information structure, see to #adc_result_info_t; + * retval true The conversion result is ready. + * retval false The conversion result is not ready yet. + */ bool ADC_GetConvSeqBGlobalConversionResult(ADC_Type *base, adc_result_info_t *info) { assert(info != NULL); @@ -292,6 +424,15 @@ bool ADC_GetConvSeqBGlobalConversionResult(ADC_Type *base, adc_result_info_t *in return true; } +/*! + * brief Get the channel's ADC conversion completed under each conversion sequence. + * + * param base ADC peripheral base address. + * param channel The indicated channel number. + * param info Pointer to information structure, see to #adc_result_info_t; + * retval true The conversion result is ready. + * retval false The conversion result is not ready yet. + */ bool ADC_GetChannelConversionResult(ADC_Type *base, uint32_t channel, adc_result_info_t *info) { assert(info != NULL); diff --git a/ext/hal/nxp/mcux/drivers/lpc/fsl_adc.h b/ext/hal/nxp/mcux/drivers/lpc/fsl_adc.h index 6db5030cd8c..4f33afafc08 100644 --- a/ext/hal/nxp/mcux/drivers/lpc/fsl_adc.h +++ b/ext/hal/nxp/mcux/drivers/lpc/fsl_adc.h @@ -1,31 +1,9 @@ /* * Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP + * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * SPDX-License-Identifier: BSD-3-Clause */ #ifndef __FSL_ADC_H__ @@ -46,8 +24,8 @@ /*! @name Driver version */ /*@{*/ -/*! @brief ADC driver version 2.0.0. */ -#define LPC_ADC_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) +/*! @brief ADC driver version 2.2.0. */ +#define FSL_ADC_DRIVER_VERSION (MAKE_VERSION(2, 2, 0)) /*@}*/ /*! @@ -96,7 +74,7 @@ enum _adc_status_flags kADC_ConvSeqAInterruptFlag = 1U << 28U, /*!< Sequence A interrupt/DMA trigger. */ kADC_ConvSeqBInterruptFlag = 1U << 29U, /*!< Sequence B interrupt/DMA trigger. */ kADC_ThresholdCompareInterruptFlag = 1U << 30U, /*!< Threshold comparision interrupt flag. */ - kADC_OverrunInterruptFlag = 1U << 31U, /*!< Overrun interrupt flag. */ + kADC_OverrunInterruptFlag = (int)(1U << 31U), /*!< Overrun interrupt flag. */ }; /*! @@ -114,6 +92,7 @@ enum _adc_interrupt_enable interrupt/DMA trigger. */ }; +#if defined(FSL_FEATURE_ADC_HAS_CTRL_ASYNMODE) & FSL_FEATURE_ADC_HAS_CTRL_ASYNMODE /*! * @brief Define selection of clock mode. */ @@ -123,7 +102,9 @@ typedef enum _adc_clock_mode 0U, /*!< The ADC clock would be derived from the system clock based on "clockDividerNumber". */ kADC_ClockAsynchronousMode = 1U, /*!< The ADC clock would be based on the SYSCON block's divider. */ } adc_clock_mode_t; +#endif /* FSL_FEATURE_ADC_HAS_CTRL_ASYNMODE. */ +#if defined(FSL_FEATURE_ADC_HAS_CTRL_RESOL) & FSL_FEATURE_ADC_HAS_CTRL_RESOL /*! * @brief Define selection of resolution. */ @@ -134,6 +115,18 @@ typedef enum _adc_resolution kADC_Resolution10bit = 2U, /*!< 10-bit resolution. */ kADC_Resolution12bit = 3U, /*!< 12-bit resolution. */ } adc_resolution_t; +#endif /* FSL_FEATURE_ADC_HAS_CTRL_RESOL. */ + +#if defined(FSL_FEATURE_ADC_HAS_TRIM_REG) & FSL_FEATURE_ADC_HAS_TRIM_REG +/*! +* @brief Definfe range of the analog supply voltage VDDA. +*/ +typedef enum _adc_voltage_range +{ + kADC_HighVoltageRange = 0U, /* High voltage. VDD = 2.7 V to 3.6 V. */ + kADC_LowVoltageRange = 1U, /* Low voltage. VDD = 2.4 V to 2.7 V. */ +} adc_vdda_range_t; +#endif /* FSL_FEATURE_ADC_HAS_TRIM_REG. */ /*! * @brief Define selection of polarity of selected input trigger for conversion sequence. @@ -150,7 +143,7 @@ typedef enum _adc_trigger_polarity typedef enum _adc_priority { kADC_PriorityLow = 0U, /*!< This sequence would be preempted when another sequence is started. */ - kADC_PriorityHigh = 1U, /*!< This sequence would preempt other sequence even when is is started. */ + kADC_PriorityHigh = 1U, /*!< This sequence would preempt other sequence even when it is started. */ } adc_priority_t; /*! @@ -209,17 +202,36 @@ typedef enum _adc_threshold_interrupt_mode */ typedef struct _adc_config { - adc_clock_mode_t clockMode; /*!< Select the clock mode for ADC converter. */ - uint32_t clockDividerNumber; /*!< This field is only available when using kADC_ClockSynchronousMode for "clockMode" - field. The divider would be plused by 1 based on the value in this field. The - available range is in 8 bits. */ - adc_resolution_t resolution; /*!< Select the conversion bits. */ +#if defined(FSL_FEATURE_ADC_HAS_CTRL_ASYNMODE) & FSL_FEATURE_ADC_HAS_CTRL_ASYNMODE + adc_clock_mode_t clockMode; /*!< Select the clock mode for ADC converter. */ +#endif /* FSL_FEATURE_ADC_HAS_CTRL_ASYNMODE. */ + uint32_t clockDividerNumber; /*!< This field is only available when using kADC_ClockSynchronousMode for "clockMode" + field. The divider would be plused by 1 based on the value in this field. The + available range is in 8 bits. */ +#if defined(FSL_FEATURE_ADC_HAS_CTRL_RESOL) & FSL_FEATURE_ADC_HAS_CTRL_RESOL + adc_resolution_t resolution; /*!< Select the conversion bits. */ +#endif /* FSL_FEATURE_ADC_HAS_CTRL_RESOL. */ +#if defined(FSL_FEATURE_ADC_HAS_CTRL_BYPASSCAL) & FSL_FEATURE_ADC_HAS_CTRL_BYPASSCAL bool enableBypassCalibration; /*!< By default, a calibration cycle must be performed each time the chip is powered-up. Re-calibration may be warranted periodically - especially if operating conditions have changed. To enable this option would avoid the need to calibrate if offset error is not a concern in the application. */ - uint32_t sampleTimeNumber; /*!< By default, with value as "0U", the sample period would be 2.5 ADC clocks. Then, - to plus the "sampleTimeNumber" value here. The available value range is in 3 bits.*/ +#endif /* FSL_FEATURE_ADC_HAS_CTRL_BYPASSCAL. */ +#if defined(FSL_FEATURE_ADC_HAS_CTRL_TSAMP) & FSL_FEATURE_ADC_HAS_CTRL_TSAMP + uint32_t sampleTimeNumber; /*!< By default, with value as "0U", the sample period would be 2.5 ADC clocks. Then, + to plus the "sampleTimeNumber" value here. The available value range is in 3 bits.*/ +#endif /* FSL_FEATURE_ADC_HAS_CTRL_TSAMP. */ +#if defined(FSL_FEATURE_ADC_HAS_CTRL_LPWRMODE) & FSL_FEATURE_ADC_HAS_CTRL_LPWRMODE + bool enableLowPowerMode; /*!< If disable low-power mode, ADC remains activated even when no conversions are + requested. + If enable low-power mode, The ADC is automatically powered-down when no conversions are + taking place. */ +#endif /* FSL_FEATURE_ADC_HAS_CTRL_LPWRMODE. */ +#if defined(FSL_FEATURE_ADC_HAS_TRIM_REG) & FSL_FEATURE_ADC_HAS_TRIM_REG + adc_vdda_range_t + voltageRange; /*!< Configure the ADC for the appropriate operating range of the analog supply voltage VDDA. + Failure to set the area correctly causes the ADC to return incorrect conversion results. */ +#endif /* FSL_FEATURE_ADC_HAS_TRIM_REG. */ } adc_config_t; /*! @@ -247,7 +259,7 @@ typedef struct _adc_conv_seq_config */ typedef struct _adc_result_info { - uint32_t result; /*!< Keey the conversion data value. */ + uint32_t result; /*!< Keep the conversion data value. */ adc_threshold_compare_status_t thresholdCompareStatus; /*!< Keep the threshold compare status. */ adc_threshold_crossing_status_t thresholdCorssingStatus; /*!< Keep the threshold crossing status. */ uint32_t channelNumber; /*!< Keep the channel number for this conversion. */ @@ -298,6 +310,8 @@ void ADC_Deinit(ADC_Type *base); */ void ADC_GetDefaultConfig(adc_config_t *config); +#if !(defined(FSL_FEATURE_ADC_HAS_NO_CALIB_FUNC) && FSL_FEATURE_ADC_HAS_NO_CALIB_FUNC) +#if defined(FSL_FEATURE_ADC_HAS_CALIB_REG) && FSL_FEATURE_ADC_HAS_CALIB_REG /*! * @brief Do the self hardware calibration. * @@ -306,7 +320,22 @@ void ADC_GetDefaultConfig(adc_config_t *config); * @retval false Calibration failed. */ bool ADC_DoSelfCalibration(ADC_Type *base); +#else +/*! + * @brief Do the self calibration. To calibrate the ADC, set the ADC clock to 500 kHz. + * In order to achieve the specified ADC accuracy, the A/D converter must be recalibrated, at a minimum, + * following every chip reset before initiating normal ADC operation. + * + * @param base ADC peripheral base address. + * @param frequency The ststem clock frequency to ADC. + * @retval true Calibration succeed. + * @retval false Calibration failed. + */ +bool ADC_DoSelfCalibration(ADC_Type *base, uint32_t frequency); +#endif /* FSL_FEATURE_ADC_HAS_CALIB_REG */ +#endif /* FSL_FEATURE_ADC_HAS_NO_CALIB_FUNC */ +#if !(defined(FSL_FEATURE_ADC_HAS_NO_INSEL) && FSL_FEATURE_ADC_HAS_NO_INSEL) /*! * @brief Enable the internal temperature sensor measurement. * @@ -327,7 +356,7 @@ static inline void ADC_EnableTemperatureSensor(ADC_Type *base, bool enable) base->INSEL = (base->INSEL & ~ADC_INSEL_SEL_MASK) | ADC_INSEL_SEL(0); } } - +#endif /* FSL_FEATURE_ADC_HAS_NO_INSEL. */ /* @} */ /*! @@ -611,13 +640,24 @@ static inline void ADC_DisableInterrupts(ADC_Type *base, uint32_t mask) } /*! - * @brief Enable the interrupt of shreshold compare event for each channel. + * @brief Enable the interrupt of threshold compare event for each channel. + * @deprecated Do not use this function. It has been superceded by @ADC_EnableThresholdCompareInterrupt + */ +static inline void ADC_EnableShresholdCompareInterrupt(ADC_Type *base, + uint32_t channel, + adc_threshold_interrupt_mode_t mode) +{ + base->INTEN = (base->INTEN & ~(0x3U << ((channel << 1U) + 3U))) | ((uint32_t)(mode) << ((channel << 1U) + 3U)); +} + +/*! + * @brief Enable the interrupt of threshold compare event for each channel. * * @param base ADC peripheral base address. * @param channel Channel number. * @param mode Interrupt mode for threshold compare event, see to #adc_threshold_interrupt_mode_t. */ -static inline void ADC_EnableShresholdCompareInterrupt(ADC_Type *base, +static inline void ADC_EnableThresholdCompareInterrupt(ADC_Type *base, uint32_t channel, adc_threshold_interrupt_mode_t mode) { diff --git a/ext/hal/nxp/mcux/drivers/lpc/fsl_common.c b/ext/hal/nxp/mcux/drivers/lpc/fsl_common.c index 86f1625343d..39e78bcd9f2 100644 --- a/ext/hal/nxp/mcux/drivers/lpc/fsl_common.c +++ b/ext/hal/nxp/mcux/drivers/lpc/fsl_common.c @@ -1,49 +1,32 @@ /* * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. - * Copyright 2016 NXP + * Copyright 2016-2018 NXP * All rights reserved. * -* Redistribution and use in source and binary forms, with or without modification, -* are permitted provided that the following conditions are met: * -* o Redistributions of source code must retain the above copyright notice, this list -* of conditions and the following disclaimer. -* -* o Redistributions in binary form must reproduce the above copyright notice, this -* list of conditions and the following disclaimer in the documentation and/or -* other materials provided with the distribution. -* -* o Neither the name of the copyright holder nor the names of its -* contributors may be used to endorse or promote products derived from this -* software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* SPDX-License-Identifier: BSD-3-Clause */ #include "fsl_common.h" -#define SDK_MEM_MAGIC_NUMBER 12345U +#define SDK_MEM_MAGIC_NUMBER 12345U typedef struct _mem_align_control_block { - uint16_t identifier; /*!< Identifier for the memory control block. */ - uint16_t offset; /*!< offset from aligned adress to real address */ + uint16_t identifier; /*!< Identifier for the memory control block. */ + uint16_t offset; /*!< offset from aligned address to real address */ } mem_align_cb_t; +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.common" +#endif + #ifndef __GIC_PRIO_BITS #if defined(ENABLE_RAM_VECTOR_TABLE) uint32_t InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler) { /* Addresses for VECTOR_TABLE and VECTOR_RAM come from the linker file */ -#if defined(__CC_ARM) +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) extern uint32_t Image$$VECTOR_ROM$$Base[]; extern uint32_t Image$$VECTOR_RAM$$Base[]; extern uint32_t Image$$RW_m_data$$Base[]; @@ -60,7 +43,7 @@ uint32_t InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler) extern uint32_t __VECTOR_RAM[]; extern uint32_t __RAM_VECTOR_TABLE_SIZE_BYTES[]; uint32_t __RAM_VECTOR_TABLE_SIZE = (uint32_t)(__RAM_VECTOR_TABLE_SIZE_BYTES); -#endif /* defined(__CC_ARM) */ +#endif /* defined(__CC_ARM) || defined(__ARMCC_VERSION) */ uint32_t n; uint32_t ret; uint32_t irqMaskValue; @@ -94,13 +77,15 @@ uint32_t InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler) #endif /* ENABLE_RAM_VECTOR_TABLE. */ #endif /* __GIC_PRIO_BITS. */ -#ifndef QN908XC_SERIES #if (defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0)) +#if !(defined(FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS) && FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS) void EnableDeepSleepIRQ(IRQn_Type interrupt) { - uint32_t index = 0; uint32_t intNumber = (uint32_t)interrupt; + + uint32_t index = 0; + while (intNumber >= 32u) { index++; @@ -113,21 +98,22 @@ void EnableDeepSleepIRQ(IRQn_Type interrupt) void DisableDeepSleepIRQ(IRQn_Type interrupt) { - uint32_t index = 0; uint32_t intNumber = (uint32_t)interrupt; + + DisableIRQ(interrupt); /* also disable interrupt at NVIC */ + uint32_t index = 0; + while (intNumber >= 32u) { index++; intNumber -= 32u; } - DisableIRQ(interrupt); /* also disable interrupt at NVIC */ SYSCON->STARTERCLR[index] = 1u << intNumber; } +#endif /* FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS */ #endif /* FSL_FEATURE_SOC_SYSCON_COUNT */ -#endif /* QN908XC_SERIES */ - void *SDK_Malloc(size_t size, size_t alignbytes) { mem_align_cb_t *p_cb = NULL; @@ -159,4 +145,3 @@ void SDK_Free(void *ptr) free((void *)((uint32_t)ptr - p_cb->offset)); } - diff --git a/ext/hal/nxp/mcux/drivers/lpc/fsl_common.h b/ext/hal/nxp/mcux/drivers/lpc/fsl_common.h index cd563c2e704..d8a74ce412b 100644 --- a/ext/hal/nxp/mcux/drivers/lpc/fsl_common.h +++ b/ext/hal/nxp/mcux/drivers/lpc/fsl_common.h @@ -1,31 +1,9 @@ /* * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * Copyright 2016-2018 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause */ #ifndef _FSL_COMMON_H_ @@ -60,19 +38,21 @@ /*! @name Driver version */ /*@{*/ -/*! @brief common driver version 2.0.0. */ -#define FSL_COMMON_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) +/*! @brief common driver version 2.0.1. */ +#define FSL_COMMON_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) /*@}*/ /* Debug console type definition. */ -#define DEBUG_CONSOLE_DEVICE_TYPE_NONE 0U /*!< No debug console. */ -#define DEBUG_CONSOLE_DEVICE_TYPE_UART 1U /*!< Debug console base on UART. */ -#define DEBUG_CONSOLE_DEVICE_TYPE_LPUART 2U /*!< Debug console base on LPUART. */ -#define DEBUG_CONSOLE_DEVICE_TYPE_LPSCI 3U /*!< Debug console base on LPSCI. */ -#define DEBUG_CONSOLE_DEVICE_TYPE_USBCDC 4U /*!< Debug console base on USBCDC. */ -#define DEBUG_CONSOLE_DEVICE_TYPE_FLEXCOMM 5U /*!< Debug console base on USBCDC. */ -#define DEBUG_CONSOLE_DEVICE_TYPE_IUART 6U /*!< Debug console base on i.MX UART. */ -#define DEBUG_CONSOLE_DEVICE_TYPE_VUSART 7U /*!< Debug console base on LPC_USART. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_NONE 0U /*!< No debug console. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_UART 1U /*!< Debug console based on UART. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_LPUART 2U /*!< Debug console based on LPUART. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_LPSCI 3U /*!< Debug console based on LPSCI. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_USBCDC 4U /*!< Debug console based on USBCDC. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_FLEXCOMM 5U /*!< Debug console based on FLEXCOMM. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_IUART 6U /*!< Debug console based on i.MX UART. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_VUSART 7U /*!< Debug console based on LPC_VUSART. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_MINI_USART 8U /*!< Debug console based on LPC_USART. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_SWO 9U /*!< Debug console based on SWO. */ /*! @brief Status group numbers. */ enum _status_groups @@ -136,14 +116,39 @@ enum _status_groups kStatusGroup_ESAI = 69, /*!< Group number for ESAI status codes. */ kStatusGroup_FLEXSPI = 70, /*!< Group number for FLEXSPI status codes. */ kStatusGroup_MMDC = 71, /*!< Group number for MMDC status codes. */ - kStatusGroup_MICFIL = 72, /*!< Group number for MIC status codes. */ + kStatusGroup_PDM = 72, /*!< Group number for MIC status codes. */ kStatusGroup_SDMA = 73, /*!< Group number for SDMA status codes. */ kStatusGroup_ICS = 74, /*!< Group number for ICS status codes. */ kStatusGroup_SPDIF = 75, /*!< Group number for SPDIF status codes. */ + kStatusGroup_LPC_MINISPI = 76, /*!< Group number for LPC_MINISPI status codes. */ + kStatusGroup_HASHCRYPT = 77, /*!< Group number for Hashcrypt status codes */ + kStatusGroup_LPC_SPI_SSP = 78, /*!< Group number for LPC_SPI_SSP status codes. */ + kStatusGroup_LPC_I2C_1 = 97, /*!< Group number for LPC_I2C_1 status codes. */ kStatusGroup_NOTIFIER = 98, /*!< Group number for NOTIFIER status codes. */ kStatusGroup_DebugConsole = 99, /*!< Group number for debug console status codes. */ - kStatusGroup_SEMC = 100, /*!< Group number for SEMC status codes. */ + kStatusGroup_SEMC = 100, /*!< Group number for SEMC status codes. */ kStatusGroup_ApplicationRangeStart = 101, /*!< Starting number for application groups. */ + kStatusGroup_IAP = 102, /*!< Group number for IAP status codes */ + + kStatusGroup_HAL_GPIO = 121, /*!< Group number for HAL GPIO status codes. */ + kStatusGroup_HAL_UART = 122, /*!< Group number for HAL UART status codes. */ + kStatusGroup_HAL_TIMER = 123, /*!< Group number for HAL TIMER status codes. */ + kStatusGroup_HAL_SPI = 124, /*!< Group number for HAL SPI status codes. */ + kStatusGroup_HAL_I2C = 125, /*!< Group number for HAL I2C status codes. */ + kStatusGroup_HAL_FLASH = 126, /*!< Group number for HAL FLASH status codes. */ + kStatusGroup_HAL_PWM = 127, /*!< Group number for HAL PWM status codes. */ + kStatusGroup_HAL_RNG = 128, /*!< Group number for HAL RNG status codes. */ + kStatusGroup_TIMERMANAGER = 135, /*!< Group number for TiMER MANAGER status codes. */ + kStatusGroup_SERIALMANAGER = 136, /*!< Group number for SERIAL MANAGER status codes. */ + kStatusGroup_LED = 137, /*!< Group number for LED status codes. */ + kStatusGroup_BUTTON = 138, /*!< Group number for BUTTON status codes. */ + kStatusGroup_EXTERN_EEPROM = 139, /*!< Group number for EXTERN EEPROM status codes. */ + kStatusGroup_SHELL = 140, /*!< Group number for SHELL status codes. */ + kStatusGroup_MEM_MANAGER = 141, /*!< Group number for MEM MANAGER status codes. */ + kStatusGroup_LIST = 142, /*!< Group number for List status codes. */ + kStatusGroup_OSA = 143, /*!< Group number for OSA status codes. */ + kStatusGroup_COMMON_TASK = 144, /*!< Group number for Common task status codes. */ + kStatusGroup_MSG = 145, /*!< Group number for messaging status codes. */ }; /*! @brief Generic status return codes. */ @@ -175,6 +180,13 @@ typedef int32_t status_t; #include "fsl_reset.h" #endif +/* + * Macro guard for whether to use default weak IRQ implementation in drivers + */ +#ifndef FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ +#define FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ 1 +#endif + /*! @name Min/max macros */ /* @{ */ #if !defined(MIN) @@ -235,16 +247,16 @@ _Pragma("diag_suppress=Pm120") #if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE) #define SDK_L2CACHE_ALIGN(var) SDK_PRAGMA(data_alignment = FSL_FEATURE_L2CACHE_LINESIZE_BYTE) var #endif -#elif defined(__ARMCC_VERSION) +#elif defined(__CC_ARM) || defined(__ARMCC_VERSION) /*! Macro to define a variable with alignbytes alignment */ -#define SDK_ALIGN(var, alignbytes) __align(alignbytes) var +#define SDK_ALIGN(var, alignbytes) __attribute__((aligned(alignbytes))) var /*! Macro to define a variable with L1 d-cache line size alignment */ #if defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) -#define SDK_L1DCACHE_ALIGN(var) __align(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) var +#define SDK_L1DCACHE_ALIGN(var) __attribute__((aligned(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE))) var #endif /*! Macro to define a variable with L2 cache line size alignment */ #if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE) -#define SDK_L2CACHE_ALIGN(var) __align(FSL_FEATURE_L2CACHE_LINESIZE_BYTE) var +#define SDK_L2CACHE_ALIGN(var) __attribute__((aligned(FSL_FEATURE_L2CACHE_LINESIZE_BYTE))) var #endif #elif defined(__GNUC__) /*! Macro to define a variable with alignbytes alignment */ @@ -273,13 +285,6 @@ _Pragma("diag_suppress=Pm120") ((unsigned int)((var) + ((alignbytes)-1)) & (unsigned int)(~(unsigned int)((alignbytes)-1))) /* @} */ -/*! Function to allocate/free L1 cache aligned memory using the malloc/free. */ -void *SDK_Malloc(size_t size, size_t alignbytes); - -void SDK_Free(void *ptr); - -/* @} */ - /*! @name Non-cacheable region definition macros */ /* For initialized non-zero non-cacheable variables, please using "AT_NONCACHEABLE_SECTION_INIT(var) ={xx};" or * "AT_NONCACHEABLE_SECTION_ALIGN_INIT(var) ={xx};" in your projects to define them, for zero-inited non-cacheable variables, @@ -288,7 +293,7 @@ void SDK_Free(void *ptr); */ /* @{ */ #if (defined(__ICCARM__)) -#if defined(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE) +#if ((!(defined(FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION) && FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION)) && defined(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE)) #define AT_NONCACHEABLE_SECTION(var) var @"NonCacheable" #define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var @"NonCacheable" #define AT_NONCACHEABLE_SECTION_INIT(var) var @"NonCacheable.init" @@ -299,25 +304,25 @@ void SDK_Free(void *ptr); #define AT_NONCACHEABLE_SECTION_INIT(var) var #define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var #endif -#elif(defined(__ARMCC_VERSION)) -#if defined(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE) +#elif(defined(__CC_ARM) || defined(__ARMCC_VERSION)) +#if ((!(defined(FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION) && FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION)) && defined(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE)) #define AT_NONCACHEABLE_SECTION(var) __attribute__((section("NonCacheable"), zero_init)) var #define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) \ - __attribute__((section("NonCacheable"), zero_init)) __align(alignbytes) var + __attribute__((section("NonCacheable"), zero_init)) __attribute__((aligned(alignbytes))) var #define AT_NONCACHEABLE_SECTION_INIT(var) __attribute__((section("NonCacheable.init"))) var #define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) \ - __attribute__((section("NonCacheable.init"))) __align(alignbytes) var + __attribute__((section("NonCacheable.init"))) __attribute__((aligned(alignbytes))) var #else #define AT_NONCACHEABLE_SECTION(var) var -#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) __align(alignbytes) var +#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) __attribute__((aligned(alignbytes))) var #define AT_NONCACHEABLE_SECTION_INIT(var) var -#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) __align(alignbytes) var +#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) __attribute__((aligned(alignbytes))) var #endif #elif(defined(__GNUC__)) /* For GCC, when the non-cacheable section is required, please define "__STARTUP_INITIALIZE_NONCACHEDATA" * in your projects to make sure the non-cacheable section variables will be initialized in system startup. */ -#if defined(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE) +#if ((!(defined(FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION) && FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION)) && defined(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE)) #define AT_NONCACHEABLE_SECTION_INIT(var) __attribute__((section("NonCacheable.init"))) var #define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) \ __attribute__((section("NonCacheable.init"))) var __attribute__((aligned(alignbytes))) @@ -339,6 +344,48 @@ void SDK_Free(void *ptr); #endif /* @} */ +/*! @name Time sensitive region */ +/* @{ */ +#if defined(FSL_SDK_DRIVER_QUICK_ACCESS_ENABLE) && FSL_SDK_DRIVER_QUICK_ACCESS_ENABLE +#if (defined(__ICCARM__)) +#define AT_QUICKACCESS_SECTION_CODE(func) func @"CodeQuickAccess" +#define AT_QUICKACCESS_SECTION_DATA(func) func @"DataQuickAccess" +#elif(defined(__CC_ARM) || defined(__ARMCC_VERSION)) +#define AT_QUICKACCESS_SECTION_CODE(func) __attribute__((section("CodeQuickAccess"))) func +#define AT_QUICKACCESS_SECTION_DATA(func) __attribute__((section("DataQuickAccess"))) func +#elif(defined(__GNUC__)) +#define AT_QUICKACCESS_SECTION_CODE(func) __attribute__((section("CodeQuickAccess"))) func +#define AT_QUICKACCESS_SECTION_DATA(func) __attribute__((section("DataQuickAccess"))) func +#else +#error Toolchain not supported. +#endif /* defined(__ICCARM__) */ +#else +#if (defined(__ICCARM__)) +#define AT_QUICKACCESS_SECTION_CODE(func) func +#define AT_QUICKACCESS_SECTION_DATA(func) func +#elif(defined(__CC_ARM) || defined(__ARMCC_VERSION)) +#define AT_QUICKACCESS_SECTION_CODE(func) func +#define AT_QUICKACCESS_SECTION_DATA(func) func +#elif(defined(__GNUC__)) +#define AT_QUICKACCESS_SECTION_CODE(func) func +#define AT_QUICKACCESS_SECTION_DATA(func) func +#else +#error Toolchain not supported. +#endif +#endif /* __FSL_SDK_DRIVER_QUICK_ACCESS_ENABLE */ +/* @} */ + +/*! @name Ram Function */ +#if (defined(__ICCARM__)) +#define RAMFUNCTION_SECTION_CODE(func) func @"RamFunction" +#elif(defined(__CC_ARM) || defined(__ARMCC_VERSION)) +#define RAMFUNCTION_SECTION_CODE(func) __attribute__((section("RamFunction"))) func +#elif(defined(__GNUC__)) +#define RAMFUNCTION_SECTION_CODE(func) __attribute__((section("RamFunction"))) func +#else +#error Toolchain not supported. +#endif /* defined(__ICCARM__) */ +/* @} */ /******************************************************************************* * API ******************************************************************************/ @@ -450,10 +497,10 @@ void SDK_Free(void *ptr); } /*! - * @brief Enaable the global IRQ + * @brief Enable the global IRQ * * Set the primask register with the provided primask value but not just enable the primask. The idea is for the - * convinience of integration of RTOS. some RTOS get its own management mechanism of primask. User is required to + * convenience of integration of RTOS. some RTOS get its own management mechanism of primask. User is required to * use the EnableGlobalIRQ() and DisableGlobalIRQ() in pair. * * @param primask value of primask register to be restored. The primask value is supposed to be provided by the @@ -478,7 +525,7 @@ void SDK_Free(void *ptr); */ uint32_t InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler); #endif /* ENABLE_RAM_VECTOR_TABLE. */ - + #if (defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0)) /*! * @brief Enable specific interrupt for wake-up from deep-sleep mode. @@ -489,7 +536,7 @@ void SDK_Free(void *ptr); * those clocks (significantly increasing power consumption in the reduced power mode), * making these wake-ups possible. * - * @note This function also enables the interrupt in the NVIC (EnableIRQ() is called internally). + * @note This function also enables the interrupt in the NVIC (EnableIRQ() is called internaly). * * @param interrupt The IRQ number. */ @@ -504,13 +551,31 @@ void SDK_Free(void *ptr); * those clocks (significantly increasing power consumption in the reduced power mode), * making these wake-ups possible. * - * @note This function also disables the interrupt in the NVIC (DisableIRQ() is called internally). + * @note This function also disables the interrupt in the NVIC (DisableIRQ() is called internaly). * * @param interrupt The IRQ number. */ void DisableDeepSleepIRQ(IRQn_Type interrupt); #endif /* FSL_FEATURE_SOC_SYSCON_COUNT */ + /*! + * @brief Allocate memory with given alignment and aligned size. + * + * This is provided to support the dynamically allocated memory + * used in cache-able region. + * @param size The length required to malloc. + * @param alignbytes The alignment size. + * @retval The allocated memory. + */ + void *SDK_Malloc(size_t size, size_t alignbytes); + + /*! + * @brief Free memory. + * + * @param ptr The memory to be release. + */ + void SDK_Free(void *ptr); + #if defined(__cplusplus) } #endif diff --git a/ext/hal/nxp/mcux/drivers/lpc/fsl_crc.c b/ext/hal/nxp/mcux/drivers/lpc/fsl_crc.c index e413222dec8..e63dd88b6d6 100644 --- a/ext/hal/nxp/mcux/drivers/lpc/fsl_crc.c +++ b/ext/hal/nxp/mcux/drivers/lpc/fsl_crc.c @@ -1,31 +1,9 @@ /* * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP + * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * SPDX-License-Identifier: BSD-3-Clause */ #include "fsl_crc.h" @@ -33,6 +11,11 @@ * Definitions ******************************************************************************/ +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.lpc_crc" +#endif + #if defined(CRC_DRIVER_USE_CRC16_CCITT_FALSE_AS_DEFAULT) && CRC_DRIVER_USE_CRC16_CCITT_FALSE_AS_DEFAULT /* @brief Default user configuration structure for CRC-CCITT */ #define CRC_DRIVER_DEFAULT_POLYNOMIAL kCRC_Polynomial_CRC_CCITT @@ -53,6 +36,15 @@ * Code ******************************************************************************/ +/*! + * brief Enables and configures the CRC peripheral module. + * + * This functions enables the CRC peripheral clock in the LPC SYSCON block. + * It also configures the CRC engine and starts checksum computation by writing the seed. + * + * param base CRC peripheral address. + * param config CRC module configuration structure. + */ void CRC_Init(CRC_Type *base, const crc_config_t *config) { #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) @@ -60,6 +52,10 @@ void CRC_Init(CRC_Type *base, const crc_config_t *config) CLOCK_EnableClock(kCLOCK_Crc); #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +#if !(defined(FSL_FEATURE_CRC_HAS_NO_RESET) && FSL_FEATURE_CRC_HAS_NO_RESET) + RESET_PeripheralReset(kCRC_RST_SHIFT_RSTn); +#endif + /* configure CRC module and write the seed */ base->MODE = 0 | CRC_MODE_CRC_POLY(config->polynomial) | CRC_MODE_BIT_RVS_WR(config->reverseIn) | CRC_MODE_CMPL_WR(config->complementIn) | CRC_MODE_BIT_RVS_SUM(config->reverseOut) | @@ -67,8 +63,26 @@ void CRC_Init(CRC_Type *base, const crc_config_t *config) base->SEED = config->seed; } +/*! + * brief Loads default values to CRC protocol configuration structure. + * + * Loads default values to CRC protocol configuration structure. The default values are: + * code + * config->polynomial = kCRC_Polynomial_CRC_CCITT; + * config->reverseIn = false; + * config->complementIn = false; + * config->reverseOut = false; + * config->complementOut = false; + * config->seed = 0xFFFFU; + * endcode + * + * param config CRC protocol configuration structure + */ void CRC_GetDefaultConfig(crc_config_t *config) { + /* Initializes the configure structure to zero. */ + memset(config, 0, sizeof(*config)); + static const crc_config_t default_config = {CRC_DRIVER_DEFAULT_POLYNOMIAL, CRC_DRIVER_DEFAULT_REVERSE_IN, CRC_DRIVER_DEFAULT_COMPLEMENT_IN, CRC_DRIVER_DEFAULT_REVERSE_OUT, CRC_DRIVER_DEFAULT_COMPLEMENT_OUT, CRC_DRIVER_DEFAULT_SEED}; @@ -76,6 +90,11 @@ void CRC_GetDefaultConfig(crc_config_t *config) *config = default_config; } +/*! + * brief resets CRC peripheral module. + * + * param base CRC peripheral address. + */ void CRC_Reset(CRC_Type *base) { crc_config_t config; @@ -83,6 +102,14 @@ void CRC_Reset(CRC_Type *base) CRC_Init(base, &config); } +/*! + * brief Loads actual values configured in CRC peripheral to CRC protocol configuration structure. + * + * The values, including seed, can be used to resume CRC calculation later. + + * param base CRC peripheral address. + * param config CRC protocol configuration structure + */ void CRC_GetConfig(CRC_Type *base, crc_config_t *config) { /* extract CRC mode settings */ @@ -103,6 +130,15 @@ void CRC_GetConfig(CRC_Type *base, crc_config_t *config) base->MODE = mode; } +/*! + * brief Writes data to the CRC module. + * + * Writes input data buffer bytes to CRC data register. + * + * param base CRC peripheral address. + * param data Input data stream, MSByte in data[0]. + * param dataSize Size of the input data buffer in bytes. + */ void CRC_WriteData(CRC_Type *base, const uint8_t *data, size_t dataSize) { const uint32_t *data32; diff --git a/ext/hal/nxp/mcux/drivers/lpc/fsl_crc.h b/ext/hal/nxp/mcux/drivers/lpc/fsl_crc.h index 5b1338d9b19..ac3500afaa0 100644 --- a/ext/hal/nxp/mcux/drivers/lpc/fsl_crc.h +++ b/ext/hal/nxp/mcux/drivers/lpc/fsl_crc.h @@ -1,31 +1,9 @@ /* * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause */ #ifndef _FSL_CRC_H_ diff --git a/ext/hal/nxp/mcux/drivers/lpc/fsl_ctimer.c b/ext/hal/nxp/mcux/drivers/lpc/fsl_ctimer.c index ac69e33344b..4d87d004c43 100644 --- a/ext/hal/nxp/mcux/drivers/lpc/fsl_ctimer.c +++ b/ext/hal/nxp/mcux/drivers/lpc/fsl_ctimer.c @@ -1,35 +1,18 @@ /* * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP + * Copyright 2016-2018 NXP + * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * SPDX-License-Identifier: BSD-3-Clause */ #include "fsl_ctimer.h" +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.ctimer" +#endif + /******************************************************************************* * Prototypes ******************************************************************************/ @@ -53,8 +36,17 @@ static CTIMER_Type *const s_ctimerBases[] = CTIMER_BASE_PTRS; static const clock_ip_name_t s_ctimerClocks[] = CTIMER_CLOCKS; #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -/*! @brief Pointers to Timer resets for each instance. */ +#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_RESET) && (FSL_FEATURE_CTIMER_HAS_NO_RESET)) +#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) +#if defined(FSL_FEATURE_CTIMER_WRITE_ZERO_ASSERT_RESET) && FSL_FEATURE_CTIMER_WRITE_ZERO_ASSERT_RESET +/*! @brief Pointers to Timer resets for each instance, writing a zero asserts the reset */ +static const reset_ip_name_t s_ctimerResets[] = CTIMER_RSTS_N; +#else +/*! @brief Pointers to Timer resets for each instance, writing a one asserts the reset */ static const reset_ip_name_t s_ctimerResets[] = CTIMER_RSTS; +#endif +#endif +#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ /*! @brief Pointers real ISRs installed by drivers for each instance. */ static ctimer_callback_t *s_ctimerCallback[FSL_FEATURE_SOC_CTIMER_COUNT] = {0}; @@ -87,6 +79,14 @@ static uint32_t CTIMER_GetInstance(CTIMER_Type *base) return instance; } +/*! + * brief Ungates the clock and configures the peripheral for basic operation. + * + * note This API should be called at the beginning of the application before using the driver. + * + * param base Ctimer peripheral base address + * param config Pointer to the user configuration structure. + */ void CTIMER_Init(CTIMER_Type *base, const ctimer_config_t *config) { assert(config); @@ -96,16 +96,26 @@ void CTIMER_Init(CTIMER_Type *base, const ctimer_config_t *config) CLOCK_EnableClock(s_ctimerClocks[CTIMER_GetInstance(base)]); #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - /* Reset the module */ +#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) +/* Reset the module. */ +#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_RESET) && (FSL_FEATURE_CTIMER_HAS_NO_RESET)) RESET_PeripheralReset(s_ctimerResets[CTIMER_GetInstance(base)]); +#endif +#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ - /* Setup the cimer mode and count select */ +/* Setup the cimer mode and count select */ +#if !defined(FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE) && FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE base->CTCR = CTIMER_CTCR_CTMODE(config->mode) | CTIMER_CTCR_CINSEL(config->input); - +#endif /* Setup the timer prescale value */ base->PR = CTIMER_PR_PRVAL(config->prescale); } +/*! + * brief Gates the timer clock. + * + * param base Ctimer peripheral base address + */ void CTIMER_Deinit(CTIMER_Type *base) { uint32_t index = CTIMER_GetInstance(base); @@ -121,10 +131,24 @@ void CTIMER_Deinit(CTIMER_Type *base) DisableIRQ(s_ctimerIRQ[index]); } +/*! + * brief Fills in the timers configuration structure with the default settings. + * + * The default values are: + * code + * config->mode = kCTIMER_TimerMode; + * config->input = kCTIMER_Capture_0; + * config->prescale = 0; + * endcode + * param config Pointer to the user configuration structure. + */ void CTIMER_GetDefaultConfig(ctimer_config_t *config) { assert(config); + /* Initializes the configure structure to zero. */ + memset(config, 0, sizeof(*config)); + /* Run as a timer */ config->mode = kCTIMER_TimerMode; /* This field is ignored when mode is timer */ @@ -133,6 +157,27 @@ void CTIMER_GetDefaultConfig(ctimer_config_t *config) config->prescale = 0; } +/*! + * brief Configures the PWM signal parameters. + * + * Enables PWM mode on the match channel passed in and will then setup the match value + * and other match parameters to generate a PWM signal. + * This function will assign match channel 3 to set the PWM cycle. + * + * note When setting PWM output from multiple output pins, all should use the same PWM + * frequency. Please use CTIMER_SetupPwmPeriod to set up the PWM with high resolution. + * + * param base Ctimer peripheral base address + * param matchChannel Match pin to be used to output the PWM signal + * param dutyCyclePercent PWM pulse width; the value should be between 0 to 100 + * param pwmFreq_Hz PWM signal frequency in Hz + * param srcClock_Hz Timer counter clock in Hz + * param enableInt Enable interrupt when the timer value reaches the match value of the PWM pulse, + * if it is 0 then no interrupt is generated + * + * return kStatus_Success on success + * kStatus_Fail If matchChannel passed in is 3; this channel is reserved to set the PWM cycle + */ status_t CTIMER_SetupPwm(CTIMER_Type *base, ctimer_match_t matchChannel, uint8_t dutyCyclePercent, @@ -199,6 +244,85 @@ status_t CTIMER_SetupPwm(CTIMER_Type *base, return kStatus_Success; } +/*! + * brief Configures the PWM signal parameters. + * + * Enables PWM mode on the match channel passed in and will then setup the match value + * and other match parameters to generate a PWM signal. + * This function will assign match channel 3 to set the PWM cycle. + * + * note When setting PWM output from multiple output pins, all should use the same PWM + * period + * + * param base Ctimer peripheral base address + * param matchChannel Match pin to be used to output the PWM signal + * param pwmPeriod PWM period match value + * param pulsePeriod Pulse width match value + * param enableInt Enable interrupt when the timer value reaches the match value of the PWM pulse, + * if it is 0 then no interrupt is generated + * + * return kStatus_Success on success + * kStatus_Fail If matchChannel passed in is 3; this channel is reserved to set the PWM period + */ +status_t CTIMER_SetupPwmPeriod( + CTIMER_Type *base, ctimer_match_t matchChannel, uint32_t pwmPeriod, uint32_t pulsePeriod, bool enableInt) +{ +/* Some CTimers only have 16bits , so the value is limited*/ +#if defined(FSL_FEATURE_SOC_CTIMER16B) && FSL_FEATURE_SOC_CTIMER16B + assert(!((FSL_FEATURE_CTIMER_BIT_SIZEn(base) < 32) && (pulsePeriod > 0xFFFFU))); +#endif + + uint32_t reg; + uint32_t index = CTIMER_GetInstance(base); + + if (matchChannel == kCTIMER_Match_3) + { + return kStatus_Fail; + } + + /* Enable PWM mode on the channel */ + base->PWMC |= (1U << matchChannel); + + /* Clear the stop, reset and interrupt bits for this channel */ + reg = base->MCR; + reg &= ~((CTIMER_MCR_MR0R_MASK | CTIMER_MCR_MR0S_MASK | CTIMER_MCR_MR0I_MASK) << (matchChannel * 3)); + + /* If call back function is valid then enable match interrupt for the channel */ + if (enableInt) + { + reg |= (CTIMER_MCR_MR0I_MASK << (CTIMER_MCR_MR0I_SHIFT + (matchChannel * 3))); + } + + /* Reset the counter when match on channel 3 */ + reg |= CTIMER_MCR_MR3R_MASK; + + base->MCR = reg; + + /* Match on channel 3 will define the PWM period */ + base->MR[kCTIMER_Match_3] = pwmPeriod; + + /* This will define the PWM pulse period */ + base->MR[matchChannel] = pulsePeriod; + /* Clear status flags */ + CTIMER_ClearStatusFlags(base, CTIMER_IR_MR0INT_MASK << matchChannel); + /* If call back function is valid then enable interrupt and update the call back function */ + if (enableInt) + { + EnableIRQ(s_ctimerIRQ[index]); + } + + return kStatus_Success; +} + +/*! + * brief Updates the duty cycle of an active PWM signal. + * + * note Please use CTIMER_UpdatePwmPulsePeriod to update the PWM with high resolution. + * + * param base Ctimer peripheral base address + * param matchChannel Match pin to be used to output the PWM signal + * param dutyCyclePercent New PWM pulse width; the value should be between 0 to 100 + */ void CTIMER_UpdatePwmDutycycle(CTIMER_Type *base, ctimer_match_t matchChannel, uint8_t dutyCyclePercent) { uint32_t pulsePeriod = 0, period; @@ -223,8 +347,21 @@ void CTIMER_UpdatePwmDutycycle(CTIMER_Type *base, ctimer_match_t matchChannel, u base->MR[matchChannel] = pulsePeriod; } +/*! + * brief Setup the match register. + * + * User configuration is used to setup the match value and action to be taken when a match occurs. + * + * param base Ctimer peripheral base address + * param matchChannel Match register to configure + * param config Pointer to the match configuration structure + */ void CTIMER_SetupMatch(CTIMER_Type *base, ctimer_match_t matchChannel, const ctimer_match_config_t *config) { +/* Some CTimers only have 16bits , so the value is limited*/ +#if defined(FSL_FEATURE_SOC_CTIMER16B) && FSL_FEATURE_SOC_CTIMER16B + assert(!(FSL_FEATURE_CTIMER_BIT_SIZEn(base) < 32 && config->matchValue > 0xFFFFU)); +#endif uint32_t reg; uint32_t index = CTIMER_GetInstance(base); @@ -257,6 +394,16 @@ void CTIMER_SetupMatch(CTIMER_Type *base, ctimer_match_t matchChannel, const cti } } +#if !defined(FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE) && FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE +/*! + * brief Setup the capture. + * + * param base Ctimer peripheral base address + * param capture Capture channel to configure + * param edge Edge on the channel that will trigger a capture + * param enableInt Flag to enable channel interrupts, if enabled then the registered call back + * is called upon capture + */ void CTIMER_SetupCapture(CTIMER_Type *base, ctimer_capture_channel_t capture, ctimer_capture_edge_t edge, @@ -278,7 +425,15 @@ void CTIMER_SetupCapture(CTIMER_Type *base, } base->CCR = reg; } +#endif +/*! + * brief Register callback. + * + * param base Ctimer peripheral base address + * param cb_func callback function + * param cb_type callback function type, singular or multiple + */ void CTIMER_RegisterCallBack(CTIMER_Type *base, ctimer_callback_t *cb_func, ctimer_callback_type_t cb_type) { uint32_t index = CTIMER_GetInstance(base); @@ -302,7 +457,15 @@ void CTIMER_GenericIRQHandler(uint32_t index) } else { +#if defined(FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE) && FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE + for (i = 0; i <= CTIMER_IR_MR3INT_SHIFT; i++) +#else +#if defined(FSL_FEATURE_CTIMER_HAS_IR_CR3INT) && FSL_FEATURE_CTIMER_HAS_IR_CR3INT for (i = 0; i <= CTIMER_IR_CR3INT_SHIFT; i++) +#else + for (i = 0; i <= CTIMER_IR_CR2INT_SHIFT; i++) +#endif /* FSL_FEATURE_CTIMER_HAS_IR_CR3INT */ +#endif { mask = 0x01 << i; /* For each status flag bit that was set call the callback function if it is valid */ @@ -312,6 +475,11 @@ void CTIMER_GenericIRQHandler(uint32_t index) } } } +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif } /* IRQ handler functions overloading weak symbols in the startup */ @@ -319,6 +487,11 @@ void CTIMER_GenericIRQHandler(uint32_t index) void CTIMER0_DriverIRQHandler(void) { CTIMER_GenericIRQHandler(0); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif } #endif @@ -326,6 +499,11 @@ void CTIMER0_DriverIRQHandler(void) void CTIMER1_DriverIRQHandler(void) { CTIMER_GenericIRQHandler(1); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif } #endif @@ -333,6 +511,11 @@ void CTIMER1_DriverIRQHandler(void) void CTIMER2_DriverIRQHandler(void) { CTIMER_GenericIRQHandler(2); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif } #endif @@ -340,6 +523,11 @@ void CTIMER2_DriverIRQHandler(void) void CTIMER3_DriverIRQHandler(void) { CTIMER_GenericIRQHandler(3); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif } #endif @@ -347,6 +535,10 @@ void CTIMER3_DriverIRQHandler(void) void CTIMER4_DriverIRQHandler(void) { CTIMER_GenericIRQHandler(4); -} - +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} #endif diff --git a/ext/hal/nxp/mcux/drivers/lpc/fsl_ctimer.h b/ext/hal/nxp/mcux/drivers/lpc/fsl_ctimer.h index 6d4e9ae11a3..3319125a807 100644 --- a/ext/hal/nxp/mcux/drivers/lpc/fsl_ctimer.h +++ b/ext/hal/nxp/mcux/drivers/lpc/fsl_ctimer.h @@ -1,31 +1,9 @@ /* * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP + * Copyright 2016-2018 NXP + * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * SPDX-License-Identifier: BSD-3-Clause */ #ifndef _FSL_CTIMER_H_ #define _FSL_CTIMER_H_ @@ -45,7 +23,7 @@ /*! @name Driver version */ /*@{*/ -#define FSL_CTIMER_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0 */ +#define FSL_CTIMER_DRIVER_VERSION (MAKE_VERSION(2, 0, 2)) /*!< Version 2.0.2 */ /*@}*/ /*! @brief List of Timer capture channels */ @@ -54,7 +32,9 @@ typedef enum _ctimer_capture_channel kCTIMER_Capture_0 = 0U, /*!< Timer capture channel 0 */ kCTIMER_Capture_1, /*!< Timer capture channel 1 */ kCTIMER_Capture_2, /*!< Timer capture channel 2 */ - kCTIMER_Capture_3 /*!< Timer capture channel 3 */ +#if defined(FSL_FEATURE_CTIMER_HAS_CCR_CAP3) && FSL_FEATURE_CTIMER_HAS_CCR_CAP3 + kCTIMER_Capture_3 /*!< Timer capture channel 3 */ +#endif /* FSL_FEATURE_CTIMER_HAS_IR_CR3INT */ } ctimer_capture_channel_t; /*! @brief List of capture edge options */ @@ -95,27 +75,35 @@ typedef enum _ctimer_timer_mode /*! @brief List of Timer interrupts */ typedef enum _ctimer_interrupt_enable { - kCTIMER_Match0InterruptEnable = CTIMER_MCR_MR0I_MASK, /*!< Match 0 interrupt */ - kCTIMER_Match1InterruptEnable = CTIMER_MCR_MR1I_MASK, /*!< Match 1 interrupt */ - kCTIMER_Match2InterruptEnable = CTIMER_MCR_MR2I_MASK, /*!< Match 2 interrupt */ - kCTIMER_Match3InterruptEnable = CTIMER_MCR_MR3I_MASK, /*!< Match 3 interrupt */ + kCTIMER_Match0InterruptEnable = CTIMER_MCR_MR0I_MASK, /*!< Match 0 interrupt */ + kCTIMER_Match1InterruptEnable = CTIMER_MCR_MR1I_MASK, /*!< Match 1 interrupt */ + kCTIMER_Match2InterruptEnable = CTIMER_MCR_MR2I_MASK, /*!< Match 2 interrupt */ + kCTIMER_Match3InterruptEnable = CTIMER_MCR_MR3I_MASK, /*!< Match 3 interrupt */ +#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE) && (FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE)) kCTIMER_Capture0InterruptEnable = CTIMER_CCR_CAP0I_MASK, /*!< Capture 0 interrupt */ kCTIMER_Capture1InterruptEnable = CTIMER_CCR_CAP1I_MASK, /*!< Capture 1 interrupt */ kCTIMER_Capture2InterruptEnable = CTIMER_CCR_CAP2I_MASK, /*!< Capture 2 interrupt */ +#if defined(FSL_FEATURE_CTIMER_HAS_CCR_CAP3) && FSL_FEATURE_CTIMER_HAS_CCR_CAP3 kCTIMER_Capture3InterruptEnable = CTIMER_CCR_CAP3I_MASK, /*!< Capture 3 interrupt */ +#endif /* FSL_FEATURE_CTIMER_HAS_CCR_CAP3 */ +#endif } ctimer_interrupt_enable_t; /*! @brief List of Timer flags */ typedef enum _ctimer_status_flags { - kCTIMER_Match0Flag = CTIMER_IR_MR0INT_MASK, /*!< Match 0 interrupt flag */ - kCTIMER_Match1Flag = CTIMER_IR_MR1INT_MASK, /*!< Match 1 interrupt flag */ - kCTIMER_Match2Flag = CTIMER_IR_MR2INT_MASK, /*!< Match 2 interrupt flag */ - kCTIMER_Match3Flag = CTIMER_IR_MR3INT_MASK, /*!< Match 3 interrupt flag */ + kCTIMER_Match0Flag = CTIMER_IR_MR0INT_MASK, /*!< Match 0 interrupt flag */ + kCTIMER_Match1Flag = CTIMER_IR_MR1INT_MASK, /*!< Match 1 interrupt flag */ + kCTIMER_Match2Flag = CTIMER_IR_MR2INT_MASK, /*!< Match 2 interrupt flag */ + kCTIMER_Match3Flag = CTIMER_IR_MR3INT_MASK, /*!< Match 3 interrupt flag */ +#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE) && (FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE)) kCTIMER_Capture0Flag = CTIMER_IR_CR0INT_MASK, /*!< Capture 0 interrupt flag */ kCTIMER_Capture1Flag = CTIMER_IR_CR1INT_MASK, /*!< Capture 1 interrupt flag */ kCTIMER_Capture2Flag = CTIMER_IR_CR2INT_MASK, /*!< Capture 2 interrupt flag */ +#if defined(FSL_FEATURE_CTIMER_HAS_IR_CR3INT) && FSL_FEATURE_CTIMER_HAS_IR_CR3INT kCTIMER_Capture3Flag = CTIMER_IR_CR3INT_MASK, /*!< Capture 3 interrupt flag */ +#endif /* FSL_FEATURE_CTIMER_HAS_IR_CR3INT */ +#endif } ctimer_status_flags_t; typedef void (*ctimer_callback_t)(uint32_t flags); @@ -126,9 +114,9 @@ typedef void (*ctimer_callback_t)(uint32_t flags); */ typedef enum { - kCTIMER_SingleCallback, /*!< Single Callback type where there is only one callback for the timer. + kCTIMER_SingleCallback, /*!< Single Callback type where there is only one callback for the timer. based on the status flags different channels needs to be handled differently */ - kCTIMER_MultipleCallback /*!< Multiple Callback type where there can be 8 valid callbacks, one per channel. + kCTIMER_MultipleCallback /*!< Multiple Callback type where there can be 8 valid callbacks, one per channel. for both match/capture */ } ctimer_callback_type_t; @@ -226,7 +214,30 @@ void CTIMER_GetDefaultConfig(ctimer_config_t *config); * This function will assign match channel 3 to set the PWM cycle. * * @note When setting PWM output from multiple output pins, all should use the same PWM - * frequency + * period + * + * @param base Ctimer peripheral base address + * @param matchChannel Match pin to be used to output the PWM signal + * @param pwmPeriod PWM period match value + * @param pulsePeriod Pulse width match value + * @param enableInt Enable interrupt when the timer value reaches the match value of the PWM pulse, + * if it is 0 then no interrupt is generated + * + * @return kStatus_Success on success + * kStatus_Fail If matchChannel passed in is 3; this channel is reserved to set the PWM period + */ +status_t CTIMER_SetupPwmPeriod( + CTIMER_Type *base, ctimer_match_t matchChannel, uint32_t pwmPeriod, uint32_t pulsePeriod, bool enableInt); + +/*! + * @brief Configures the PWM signal parameters. + * + * Enables PWM mode on the match channel passed in and will then setup the match value + * and other match parameters to generate a PWM signal. + * This function will assign match channel 3 to set the PWM cycle. + * + * @note When setting PWM output from multiple output pins, all should use the same PWM + * frequency. Please use CTIMER_SetupPwmPeriod to set up the PWM with high resolution. * * @param base Ctimer peripheral base address * @param matchChannel Match pin to be used to output the PWM signal @@ -246,9 +257,24 @@ status_t CTIMER_SetupPwm(CTIMER_Type *base, uint32_t srcClock_Hz, bool enableInt); +/*! + * @brief Updates the pulse period of an active PWM signal. + * + * @param base Ctimer peripheral base address + * @param matchChannel Match pin to be used to output the PWM signal + * @param pulsePeriod New PWM pulse width match value + */ +static inline void CTIMER_UpdatePwmPulsePeriod(CTIMER_Type *base, ctimer_match_t matchChannel, uint32_t pulsePeriod) +{ + /* Update PWM pulse period match value */ + base->MR[matchChannel] = pulsePeriod; +} + /*! * @brief Updates the duty cycle of an active PWM signal. * + * @note Please use CTIMER_UpdatePwmPulsePeriod to update the PWM with high resolution. + * * @param base Ctimer peripheral base address * @param matchChannel Match pin to be used to output the PWM signal * @param dutyCyclePercent New PWM pulse width; the value should be between 0 to 100 @@ -282,6 +308,17 @@ void CTIMER_SetupCapture(CTIMER_Type *base, ctimer_capture_edge_t edge, bool enableInt); +/*! + * @brief Get the timer count value from TC register. + * + * @param base Ctimer peripheral base address. + * @return return the timer count value. + */ +static inline uint32_t CTIMER_GetTimerCountValue(CTIMER_Type *base) +{ + return (base->TC); +} + /*! * @brief Register callback. * @@ -306,10 +343,16 @@ void CTIMER_RegisterCallBack(CTIMER_Type *base, ctimer_callback_t *cb_func, ctim static inline void CTIMER_EnableInterrupts(CTIMER_Type *base, uint32_t mask) { /* Enable match interrupts */ - base->MCR |= mask; + base->MCR |= mask & (CTIMER_MCR_MR0I_MASK | CTIMER_MCR_MR1I_MASK | CTIMER_MCR_MR2I_MASK | CTIMER_MCR_MR3I_MASK); - /* Enable capture interrupts */ - base->CCR |= mask; +/* Enable capture interrupts */ +#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE) && (FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE)) + base->CCR |= mask & (CTIMER_CCR_CAP0I_MASK | CTIMER_CCR_CAP1I_MASK | CTIMER_CCR_CAP2I_MASK +#if defined(FSL_FEATURE_CTIMER_HAS_CCR_CAP3) && FSL_FEATURE_CTIMER_HAS_CCR_CAP3 + | CTIMER_CCR_CAP3I_MASK +#endif /* FSL_FEATURE_CTIMER_HAS_CCR_CAP3 */ + ); +#endif } /*! @@ -322,10 +365,16 @@ static inline void CTIMER_EnableInterrupts(CTIMER_Type *base, uint32_t mask) static inline void CTIMER_DisableInterrupts(CTIMER_Type *base, uint32_t mask) { /* Disable match interrupts */ - base->MCR &= ~mask; + base->MCR &= ~(mask & (CTIMER_MCR_MR0I_MASK | CTIMER_MCR_MR1I_MASK | CTIMER_MCR_MR2I_MASK | CTIMER_MCR_MR3I_MASK)); - /* Disable capture interrupts */ - base->CCR &= ~mask; +/* Disable capture interrupts */ +#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE) && (FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE)) + base->CCR &= ~(mask & (CTIMER_CCR_CAP0I_MASK | CTIMER_CCR_CAP1I_MASK | CTIMER_CCR_CAP2I_MASK +#if defined(FSL_FEATURE_CTIMER_HAS_CCR_CAP3) && FSL_FEATURE_CTIMER_HAS_CCR_CAP3 + | CTIMER_CCR_CAP3I_MASK +#endif /* FSL_FEATURE_CTIMER_HAS_CCR_CAP3 */ + )); +#endif } /*! @@ -342,11 +391,16 @@ static inline uint32_t CTIMER_GetEnabledInterrupts(CTIMER_Type *base) /* Get all the match interrupts enabled */ enabledIntrs = - base->MCR & (CTIMER_MCR_MR0I_SHIFT | CTIMER_MCR_MR1I_SHIFT | CTIMER_MCR_MR2I_SHIFT | CTIMER_MCR_MR3I_SHIFT); + base->MCR & (CTIMER_MCR_MR0I_MASK | CTIMER_MCR_MR1I_MASK | CTIMER_MCR_MR2I_MASK | CTIMER_MCR_MR3I_MASK); - /* Get all the capture interrupts enabled */ - enabledIntrs |= - base->CCR & (CTIMER_CCR_CAP0I_SHIFT | CTIMER_CCR_CAP1I_SHIFT | CTIMER_CCR_CAP2I_SHIFT | CTIMER_CCR_CAP3I_SHIFT); +/* Get all the capture interrupts enabled */ +#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE) && (FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE)) + enabledIntrs |= base->CCR & (CTIMER_CCR_CAP0I_MASK | CTIMER_CCR_CAP1I_MASK | CTIMER_CCR_CAP2I_MASK +#if defined(FSL_FEATURE_CTIMER_HAS_CCR_CAP3) && FSL_FEATURE_CTIMER_HAS_CCR_CAP3 + | CTIMER_CCR_CAP3I_MASK +#endif /* FSL_FEATURE_CTIMER_HAS_CCR_CAP3 */ + ); +#endif return enabledIntrs; } diff --git a/ext/hal/nxp/mcux/drivers/lpc/fsl_dma.c b/ext/hal/nxp/mcux/drivers/lpc/fsl_dma.c index 99b9dd8a4ce..a6024da1e32 100644 --- a/ext/hal/nxp/mcux/drivers/lpc/fsl_dma.c +++ b/ext/hal/nxp/mcux/drivers/lpc/fsl_dma.c @@ -1,31 +1,9 @@ /* * Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP + * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * SPDX-License-Identifier: BSD-3-Clause */ #include "fsl_dma.h" @@ -34,6 +12,11 @@ * Definitions ******************************************************************************/ +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.lpc_dma" +#endif + /******************************************************************************* * Prototypes ******************************************************************************/ @@ -43,7 +26,14 @@ * * @param base DMA peripheral base address. */ -static int32_t DMA_GetInstance(DMA_Type *base); +static uint32_t DMA_GetInstance(DMA_Type *base); + +/*! + * @brief Get virtual channel number. + * + * @param base DMA peripheral base address. + */ +static uint32_t DMA_GetVirtualStartChannel(DMA_Type *base); /******************************************************************************* * Variables @@ -52,27 +42,34 @@ static int32_t DMA_GetInstance(DMA_Type *base); /*! @brief Array to map DMA instance number to base pointer. */ static DMA_Type *const s_dmaBases[] = DMA_BASE_PTRS; +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/*! @brief Array to map DMA instance number to clock name. */ +static const clock_ip_name_t s_dmaClockName[] = DMA_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + /*! @brief Array to map DMA instance number to IRQ number. */ static const IRQn_Type s_dmaIRQNumber[] = DMA_IRQS; /*! @brief Pointers to transfer handle for each DMA channel. */ -static dma_handle_t *s_DMAHandle[FSL_FEATURE_DMA_NUMBER_OF_CHANNELS]; +static dma_handle_t *s_DMAHandle[FSL_FEATURE_DMA_ALL_CHANNELS]; /*! @brief Static table of descriptors */ #if defined(__ICCARM__) -#pragma data_alignment = 512 -dma_descriptor_t s_dma_descriptor_table[FSL_FEATURE_DMA_NUMBER_OF_CHANNELS] = {0}; -#elif defined(__CC_ARM) -__attribute__((aligned(512))) dma_descriptor_t s_dma_descriptor_table[FSL_FEATURE_DMA_NUMBER_OF_CHANNELS] = {0}; +#pragma data_alignment = FSL_FEATURE_DMA_DESCRIPTOR_ALIGN_SIZE +static dma_descriptor_t s_dma_descriptor_table[FSL_FEATURE_SOC_DMA_COUNT][FSL_FEATURE_DMA_MAX_CHANNELS] = {0}; +#elif defined(__CC_ARM) || defined(__ARMCC_VERSION) +__attribute__((aligned(FSL_FEATURE_DMA_DESCRIPTOR_ALIGN_SIZE))) static dma_descriptor_t + s_dma_descriptor_table[FSL_FEATURE_SOC_DMA_COUNT][FSL_FEATURE_DMA_MAX_CHANNELS] = {0}; #elif defined(__GNUC__) -__attribute__((aligned(512))) dma_descriptor_t s_dma_descriptor_table[FSL_FEATURE_DMA_NUMBER_OF_CHANNELS] = {0}; +__attribute__((aligned(FSL_FEATURE_DMA_DESCRIPTOR_ALIGN_SIZE))) static dma_descriptor_t + s_dma_descriptor_table[FSL_FEATURE_SOC_DMA_COUNT][FSL_FEATURE_DMA_MAX_CHANNELS] = {0}; #endif /******************************************************************************* * Code ******************************************************************************/ -static int32_t DMA_GetInstance(DMA_Type *base) +static uint32_t DMA_GetInstance(DMA_Type *base) { int32_t instance; /* Find the instance index from base address mappings. */ @@ -84,38 +81,77 @@ static int32_t DMA_GetInstance(DMA_Type *base) } } assert(instance < ARRAY_SIZE(s_dmaBases)); - return instance < ARRAY_SIZE(s_dmaBases) ? instance : -1; + + return instance; } +static uint32_t DMA_GetVirtualStartChannel(DMA_Type *base) +{ + uint32_t startChannel = 0, instance = 0; + uint32_t i = 0; + + instance = DMA_GetInstance(base); + + /* Compute start channel */ + for (i = 0; i < instance; i++) + { + startChannel += FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(s_dmaBases[i]); + } + + return startChannel; +} + +/*! + * brief Initializes DMA peripheral. + * + * This function enable the DMA clock, set descriptor table and + * enable DMA peripheral. + * + * param base DMA peripheral base address. + */ void DMA_Init(DMA_Type *base) { #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) /* enable dma clock gate */ - CLOCK_EnableClock(kCLOCK_Dma); + CLOCK_EnableClock(s_dmaClockName[DMA_GetInstance(base)]); #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + /* set descriptor table */ base->SRAMBASE = (uint32_t)s_dma_descriptor_table; /* enable dma peripheral */ base->CTRL |= DMA_CTRL_ENABLE_MASK; } +/*! + * brief Deinitializes DMA peripheral. + * + * This function gates the DMA clock. + * + * param base DMA peripheral base address. + */ void DMA_Deinit(DMA_Type *base) { #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + CLOCK_DisableClock(s_dmaClockName[DMA_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ /* Disable DMA peripheral */ base->CTRL &= ~(DMA_CTRL_ENABLE_MASK); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ } +/*! + * brief Set trigger settings of DMA channel. + * + * param base DMA peripheral base address. + * param channel DMA channel number. + * param trigger trigger configuration. + */ void DMA_ConfigureChannelTrigger(DMA_Type *base, uint32_t channel, dma_channel_trigger_t *trigger) { - assert((channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELS) && (NULL != trigger)); + assert((channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base)) && (NULL != trigger)); - uint32_t tmp = ( - DMA_CHANNEL_CFG_HWTRIGEN_MASK | DMA_CHANNEL_CFG_TRIGPOL_MASK | DMA_CHANNEL_CFG_TRIGTYPE_MASK | - DMA_CHANNEL_CFG_TRIGBURST_MASK | DMA_CHANNEL_CFG_BURSTPOWER_MASK | DMA_CHANNEL_CFG_SRCBURSTWRAP_MASK | - DMA_CHANNEL_CFG_DSTBURSTWRAP_MASK - ); + uint32_t tmp = (DMA_CHANNEL_CFG_HWTRIGEN_MASK | DMA_CHANNEL_CFG_TRIGPOL_MASK | DMA_CHANNEL_CFG_TRIGTYPE_MASK | + DMA_CHANNEL_CFG_TRIGBURST_MASK | DMA_CHANNEL_CFG_BURSTPOWER_MASK | + DMA_CHANNEL_CFG_SRCBURSTWRAP_MASK | DMA_CHANNEL_CFG_DSTBURSTWRAP_MASK); tmp = base->CHANNEL[channel].CFG & (~tmp); tmp |= (uint32_t)(trigger->type) | (uint32_t)(trigger->burst) | (uint32_t)(trigger->wrap); base->CHANNEL[channel].CFG = tmp; @@ -128,11 +164,18 @@ void DMA_ConfigureChannelTrigger(DMA_Type *base, uint32_t channel, dma_channel_t * @param channel DMA channel number. * @return The number of bytes which have not been transferred yet. */ +/*! + * brief Gets the remaining bytes of the current DMA descriptor transfer. + * + * param base DMA peripheral base address. + * param channel DMA channel number. + * return The number of bytes which have not been transferred yet. + */ uint32_t DMA_GetRemainingBytes(DMA_Type *base, uint32_t channel) { - assert(channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELS); + assert(channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base)); - /* NOTE: when descriptors are chained, ACTIVE bit is set for whole chain. It makes + /* NOTE: when descriptors are chained, ACTIVE bit is set for whole chain. It makes * impossible to distinguish between: * - transfer finishes (represented by value '0x3FF') * - and remaining 1024 bytes to transfer (value 0x3FF) @@ -140,24 +183,20 @@ uint32_t DMA_GetRemainingBytes(DMA_Type *base, uint32_t channel) * If you decide to use this function, please use 1023 transfers as maximal value */ /* Channel not active (transfer finished) and value is 0x3FF - nothing to transfer */ - if ( - (!(base->COMMON[DMA_CHANNEL_GROUP(channel)].ACTIVE & (1U << (DMA_CHANNEL_INDEX(channel))))) && - (0x3FF == ((base->CHANNEL[channel].XFERCFG & DMA_CHANNEL_XFERCFG_XFERCOUNT_MASK) >> DMA_CHANNEL_XFERCFG_XFERCOUNT_SHIFT)) - ) + if ((!DMA_ChannelIsActive(base, channel)) && + (0x3FF == ((base->CHANNEL[channel].XFERCFG & DMA_CHANNEL_XFERCFG_XFERCOUNT_MASK) >> + DMA_CHANNEL_XFERCFG_XFERCOUNT_SHIFT))) { return 0; } - return base->CHANNEL[channel].XFERCFG + 1; + return ((base->CHANNEL[channel].XFERCFG & DMA_CHANNEL_XFERCFG_XFERCOUNT_MASK) >> + DMA_CHANNEL_XFERCFG_XFERCOUNT_SHIFT) + + 1; } static void DMA_SetupDescriptor( - dma_descriptor_t *desc, - uint32_t xfercfg, - void *srcEndAddr, - void *dstEndAddr, - void *nextDesc -) + dma_descriptor_t *desc, uint32_t xfercfg, void *srcEndAddr, void *dstEndAddr, void *nextDesc) { desc->xfercfg = xfercfg; desc->srcEndAddr = srcEndAddr; @@ -166,10 +205,7 @@ static void DMA_SetupDescriptor( } /* Verify and convert dma_xfercfg_t to XFERCFG register */ -static void DMA_SetupXferCFG( - dma_xfercfg_t *xfercfg, - uint32_t *xfercfg_addr -) +static void DMA_SetupXferCFG(dma_xfercfg_t *xfercfg, uint32_t *xfercfg_addr) { assert(xfercfg != NULL); /* check source increment */ @@ -187,9 +223,9 @@ static void DMA_SetupXferCFG( /* set reload - allow link to next descriptor */ xfer |= DMA_CHANNEL_XFERCFG_RELOAD(xfercfg->reload ? 1 : 0); /* set swtrig flag - start transfer */ - xfer |= DMA_CHANNEL_XFERCFG_SWTRIG(xfercfg->swtrig? 1 : 0); + xfer |= DMA_CHANNEL_XFERCFG_SWTRIG(xfercfg->swtrig ? 1 : 0); /* set transfer count */ - xfer |= DMA_CHANNEL_XFERCFG_CLRTRIG(xfercfg->clrtrig? 1 : 0); + xfer |= DMA_CHANNEL_XFERCFG_CLRTRIG(xfercfg->clrtrig ? 1 : 0); /* set INTA */ xfer |= DMA_CHANNEL_XFERCFG_SETINTA(xfercfg->intA ? 1 : 0); /* set INTB */ @@ -210,13 +246,17 @@ static void DMA_SetupXferCFG( *xfercfg_addr = xfer; } -void DMA_CreateDescriptor( - dma_descriptor_t *desc, - dma_xfercfg_t *xfercfg, - void *srcAddr, - void *dstAddr, - void *nextDesc -) +/*! + * brief Create application specific DMA descriptor + * to be used in a chain in transfer + * + * param desc DMA descriptor address. + * param xfercfg Transfer configuration for DMA descriptor. + * param srcAddr Address of last item to transmit + * param dstAddr Address of last item to receive. + * param nextDesc Address of next descriptor in chain. + */ +void DMA_CreateDescriptor(dma_descriptor_t *desc, dma_xfercfg_t *xfercfg, void *srcAddr, void *dstAddr, void *nextDesc) { uint32_t xfercfg_reg = 0; @@ -229,40 +269,69 @@ void DMA_CreateDescriptor( DMA_SetupXferCFG(xfercfg, &xfercfg_reg); /* Set descriptor structure */ - DMA_SetupDescriptor(desc, xfercfg_reg, - (uint8_t*)srcAddr + (xfercfg->srcInc * xfercfg->byteWidth * (xfercfg->transferCount - 1)), - (uint8_t*)dstAddr + (xfercfg->dstInc * xfercfg->byteWidth * (xfercfg->transferCount - 1)), - nextDesc - ); + DMA_SetupDescriptor( + desc, xfercfg_reg, (uint8_t *)srcAddr + (xfercfg->srcInc * xfercfg->byteWidth * (xfercfg->transferCount - 1)), + (uint8_t *)dstAddr + (xfercfg->dstInc * xfercfg->byteWidth * (xfercfg->transferCount - 1)), nextDesc); } +/*! + * brief Abort running transfer by handle. + * + * This function aborts DMA transfer specified by handle. + * + * param handle DMA handle pointer. + */ void DMA_AbortTransfer(dma_handle_t *handle) { assert(NULL != handle); DMA_DisableChannel(handle->base, handle->channel); - while (handle->base->COMMON[DMA_CHANNEL_GROUP(handle->channel)].BUSY & (1U << DMA_CHANNEL_INDEX(handle->channel))) - { } - handle->base->COMMON[DMA_CHANNEL_GROUP(handle->channel)].ABORT |= 1U << DMA_CHANNEL_INDEX(handle->channel); + while (DMA_COMMON_CONST_REG_GET(handle->base, handle->channel, BUSY) & (1U << DMA_CHANNEL_INDEX(handle->channel))) + { + } + DMA_COMMON_REG_GET(handle->base, handle->channel, ABORT) |= 1U << DMA_CHANNEL_INDEX(handle->channel); DMA_EnableChannel(handle->base, handle->channel); } +/*! + * brief Creates the DMA handle. + * + * This function is called if using transaction API for DMA. This function + * initializes the internal state of DMA handle. + * + * param handle DMA handle pointer. The DMA handle stores callback function and + * parameters. + * param base DMA peripheral base address. + * param channel DMA channel number. + */ void DMA_CreateHandle(dma_handle_t *handle, DMA_Type *base, uint32_t channel) { - int32_t dmaInstance; - assert((NULL != handle) && (channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELS)); + assert((NULL != handle) && (channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base))); + int32_t dmaInstance; + uint32_t startChannel = 0; /* base address is invalid DMA instance */ dmaInstance = DMA_GetInstance(base); + startChannel = DMA_GetVirtualStartChannel(base); memset(handle, 0, sizeof(*handle)); handle->base = base; handle->channel = channel; - s_DMAHandle[channel] = handle; + s_DMAHandle[startChannel + channel] = handle; /* Enable NVIC interrupt */ EnableIRQ(s_dmaIRQNumber[dmaInstance]); } +/*! + * brief Installs a callback function for the DMA transfer. + * + * This callback is called in DMA IRQ handler. Use the callback to do something after + * the current major loop transfer completes. + * + * param handle DMA handle pointer. + * param callback DMA callback function pointer. + * param userData Parameter for callback function. + */ void DMA_SetCallback(dma_handle_t *handle, dma_callback callback, void *userData) { assert(handle != NULL); @@ -271,13 +340,29 @@ void DMA_SetCallback(dma_handle_t *handle, dma_callback callback, void *userData handle->userData = userData; } +/*! + * brief Prepares the DMA transfer structure. + * + * This function prepares the transfer configuration structure according to the user input. + * + * param config The user configuration structure of type dma_transfer_t. + * param srcAddr DMA transfer source address. + * param dstAddr DMA transfer destination address. + * param byteWidth DMA transfer destination address width(bytes). + * param transferBytes DMA transfer bytes to be transferred. + * param type DMA transfer type. + * param nextDesc Chain custom descriptor to transfer. + * note The data address and the data width must be consistent. For example, if the SRC + * is 4 bytes, so the source address must be 4 bytes aligned, or it shall result in + * source address error(SAE). + */ void DMA_PrepareTransfer(dma_transfer_config_t *config, - void *srcAddr, - void *dstAddr, - uint32_t byteWidth, - uint32_t transferBytes, - dma_transfer_type_t type, - void *nextDesc) + void *srcAddr, + void *dstAddr, + uint32_t byteWidth, + uint32_t transferBytes, + dma_transfer_type_t type, + void *nextDesc) { uint32_t xfer_count; assert((NULL != config) && (NULL != srcAddr) && (NULL != dstAddr)); @@ -290,35 +375,35 @@ void DMA_PrepareTransfer(dma_transfer_config_t *config, memset(config, 0, sizeof(*config)); switch (type) { - case kDMA_MemoryToMemory: - config->xfercfg.srcInc = 1; - config->xfercfg.dstInc = 1; - config->isPeriph = false; - break; - case kDMA_PeripheralToMemory: - /* Peripheral register - source doesn't increment */ - config->xfercfg.srcInc = 0; - config->xfercfg.dstInc = 1; - config->isPeriph = true; - break; - case kDMA_MemoryToPeripheral: - /* Peripheral register - destination doesn't increment */ - config->xfercfg.srcInc = 1; - config->xfercfg.dstInc = 0; - config->isPeriph = true; - break; - case kDMA_StaticToStatic: - config->xfercfg.srcInc = 0; - config->xfercfg.dstInc = 0; - config->isPeriph = true; - break; - default: - return; + case kDMA_MemoryToMemory: + config->xfercfg.srcInc = 1; + config->xfercfg.dstInc = 1; + config->isPeriph = false; + break; + case kDMA_PeripheralToMemory: + /* Peripheral register - source doesn't increment */ + config->xfercfg.srcInc = 0; + config->xfercfg.dstInc = 1; + config->isPeriph = true; + break; + case kDMA_MemoryToPeripheral: + /* Peripheral register - destination doesn't increment */ + config->xfercfg.srcInc = 1; + config->xfercfg.dstInc = 0; + config->isPeriph = true; + break; + case kDMA_StaticToStatic: + config->xfercfg.srcInc = 0; + config->xfercfg.dstInc = 0; + config->isPeriph = true; + break; + default: + return; } - config->dstAddr = (uint8_t*)dstAddr; - config->srcAddr = (uint8_t*)srcAddr; - config->nextDesc = (uint8_t*)nextDesc; + config->dstAddr = (uint8_t *)dstAddr; + config->srcAddr = (uint8_t *)srcAddr; + config->nextDesc = (uint8_t *)nextDesc; config->xfercfg.transferCount = xfer_count; config->xfercfg.byteWidth = byteWidth; config->xfercfg.intA = true; @@ -326,14 +411,28 @@ void DMA_PrepareTransfer(dma_transfer_config_t *config, config->xfercfg.valid = true; } +/*! + * brief Submits the DMA transfer request. + * + * This function submits the DMA transfer request according to the transfer configuration structure. + * If the user submits the transfer request repeatedly, this function packs an unprocessed request as + * a TCD and enables scatter/gather feature to process it in the next time. + * + * param handle DMA handle pointer. + * param config Pointer to DMA transfer configuration structure. + * retval kStatus_DMA_Success It means submit transfer request succeed. + * retval kStatus_DMA_QueueFull It means TCD queue is full. Submit transfer request is not allowed. + * retval kStatus_DMA_Busy It means the given channel is busy, need to submit request later. + */ status_t DMA_SubmitTransfer(dma_handle_t *handle, dma_transfer_config_t *config) { assert((NULL != handle) && (NULL != config)); + uint32_t instance = DMA_GetInstance(handle->base); /* Previous transfer has not finished */ if (DMA_ChannelIsActive(handle->base, handle->channel)) { - return kStatus_DMA_Busy; + return kStatus_DMA_Busy; } /* enable/disable peripheral request */ @@ -346,76 +445,115 @@ status_t DMA_SubmitTransfer(dma_handle_t *handle, dma_transfer_config_t *config) DMA_DisableChannelPeriphRq(handle->base, handle->channel); } - DMA_CreateDescriptor( - &s_dma_descriptor_table[ handle->channel ], &config->xfercfg, - config->srcAddr, config->dstAddr, config->nextDesc - ); + DMA_CreateDescriptor(&(s_dma_descriptor_table[instance][handle->channel]), &config->xfercfg, config->srcAddr, + config->dstAddr, config->nextDesc); return kStatus_Success; } +/*! + * brief DMA start transfer. + * + * This function enables the channel request. User can call this function after submitting the transfer request + * or before submitting the transfer request. + * + * param handle DMA handle pointer. + */ void DMA_StartTransfer(dma_handle_t *handle) { assert(NULL != handle); + uint32_t instance = DMA_GetInstance(handle->base); + /* Enable channel interrupt */ - handle->base->COMMON[DMA_CHANNEL_GROUP(handle->channel)].INTENSET |= 1U << DMA_CHANNEL_INDEX(handle->channel); + DMA_EnableChannelInterrupts(handle->base, handle->channel); /* If HW trigger is enabled - disable SW trigger */ if (handle->base->CHANNEL[handle->channel].CFG & DMA_CHANNEL_CFG_HWTRIGEN_MASK) { - s_dma_descriptor_table[ handle->channel ].xfercfg &= ~(DMA_CHANNEL_XFERCFG_SWTRIG_MASK); + s_dma_descriptor_table[instance][handle->channel].xfercfg &= ~(DMA_CHANNEL_XFERCFG_SWTRIG_MASK); } /* Otherwise enable SW trigger */ else { - s_dma_descriptor_table[ handle->channel ].xfercfg |= DMA_CHANNEL_XFERCFG_SWTRIG_MASK; + s_dma_descriptor_table[instance][handle->channel].xfercfg |= DMA_CHANNEL_XFERCFG_SWTRIG_MASK; } /* Set channel XFERCFG register according first channel descriptor. */ - handle->base->CHANNEL[handle->channel].XFERCFG = s_dma_descriptor_table[ handle->channel ].xfercfg; - /* At this moment, the channel ACTIVE bit is set and application cannot modify - * or start another transfer using this channel. Channel ACTIVE bit is cleared by + handle->base->CHANNEL[handle->channel].XFERCFG = s_dma_descriptor_table[instance][handle->channel].xfercfg; + /* At this moment, the channel ACTIVE bit is set and application cannot modify + * or start another transfer using this channel. Channel ACTIVE bit is cleared by * 'AbortTransfer' function or when the transfer finishes */ } -void DMA0_DriverIRQHandler(void) +void DMA_IRQHandle(DMA_Type *base) { dma_handle_t *handle; - int32_t channel_group; int32_t channel_index; + uint32_t startChannel = DMA_GetVirtualStartChannel(base); + uint32_t i = 0; /* Find channels that have completed transfer */ - for (int i = 0; i < FSL_FEATURE_DMA_NUMBER_OF_CHANNELS; i++) + for (i = 0; i < FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base); i++) { - handle = s_DMAHandle[i]; + handle = s_DMAHandle[i + startChannel]; /* Handle is not present */ if (NULL == handle) { continue; } - channel_group = DMA_CHANNEL_GROUP(handle->channel); channel_index = DMA_CHANNEL_INDEX(handle->channel); /* Channel uses INTA flag */ - if (handle->base->COMMON[channel_group].INTA & (1U << channel_index)) + if (DMA_COMMON_REG_GET(handle->base, handle->channel, INTA) & (1U << channel_index)) { /* Clear INTA flag */ - handle->base->COMMON[channel_group].INTA = 1U << channel_index; + DMA_COMMON_REG_SET(handle->base, handle->channel, INTA, (1U << channel_index)); if (handle->callback) { (handle->callback)(handle, handle->userData, true, kDMA_IntA); } } /* Channel uses INTB flag */ - if (handle->base->COMMON[channel_group].INTB & (1U << channel_index)) + if (DMA_COMMON_REG_GET(handle->base, handle->channel, INTB) & (1U << channel_index)) { /* Clear INTB flag */ - handle->base->COMMON[channel_group].INTB = 1U << channel_index; + DMA_COMMON_REG_SET(handle->base, handle->channel, INTB, (1U << channel_index)); if (handle->callback) { (handle->callback)(handle, handle->userData, true, kDMA_IntB); } } + /* Error flag */ + if (DMA_COMMON_REG_GET(handle->base, handle->channel, ERRINT) & (1U << channel_index)) + { + /* Clear error flag */ + DMA_COMMON_REG_SET(handle->base, handle->channel, ERRINT, (1U << channel_index)); + if (handle->callback) + { + (handle->callback)(handle, handle->userData, false, kDMA_IntError); + } + } } } +void DMA0_DriverIRQHandler(void) +{ + DMA_IRQHandle(DMA0); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +#if defined(DMA1) +void DMA1_DriverIRQHandler(void) +{ + DMA_IRQHandle(DMA1); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif diff --git a/ext/hal/nxp/mcux/drivers/lpc/fsl_dma.h b/ext/hal/nxp/mcux/drivers/lpc/fsl_dma.h index fbe7d007abe..aeedd679492 100644 --- a/ext/hal/nxp/mcux/drivers/lpc/fsl_dma.h +++ b/ext/hal/nxp/mcux/drivers/lpc/fsl_dma.h @@ -1,31 +1,9 @@ /* * Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP + * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * SPDX-License-Identifier: BSD-3-Clause */ #ifndef _FSL_DMA_H_ @@ -46,27 +24,42 @@ /*! @name Driver version */ /*@{*/ /*! @brief DMA driver version */ -#define FSL_DMA_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0. */ +#define FSL_DMA_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) /*!< Version 2.0.1. */ /*@}*/ #define DMA_MAX_TRANSFER_COUNT 0x400 -/* Channel group consists of 32 channels. channel_group = (channel / 32) */ -#define DMA_CHANNEL_GROUP(channel) (((uint8_t)channel) >> 5U) -/* Channel index in channel group. channel_index = (channel % 32) */ -#define DMA_CHANNEL_INDEX(channel) (((uint8_t)channel) & 0x1F) +#if defined FSL_FEATURE_DMA_NUMBER_OF_CHANNELS +#define FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(x) FSL_FEATURE_DMA_NUMBER_OF_CHANNELS +#define FSL_FEATURE_DMA_MAX_CHANNELS FSL_FEATURE_DMA_NUMBER_OF_CHANNELS +#define FSL_FEATURE_DMA_ALL_CHANNELS (FSL_FEATURE_DMA_NUMBER_OF_CHANNELS * FSL_FEATURE_SOC_DMA_COUNT) +#define FSL_FEATURE_DMA_DESCRIPTOR_ALIGN_SIZE (512) +#endif +/* Channel group consists of 32 channels. channel_group = (channel / 32) */ +#define DMA_CHANNEL_GROUP(channel) (((uint8_t)(channel)) >> 5U) +/* Channel index in channel group. channel_index = (channel % 32) */ +#define DMA_CHANNEL_INDEX(channel) (((uint8_t)(channel)) & 0x1F) + +#define DMA_COMMON_REG_GET(base, channel, reg) \ + (((volatile uint32_t *)(&((base)->COMMON[0].reg)))[DMA_CHANNEL_GROUP(channel)]) +#define DMA_COMMON_CONST_REG_GET(base, channel, reg) \ + (((volatile const uint32_t *)(&((base)->COMMON[0].reg)))[DMA_CHANNEL_GROUP(channel)]) +#define DMA_COMMON_REG_SET(base, channel, reg, value) \ + (((volatile uint32_t *)(&((base)->COMMON[0].reg)))[DMA_CHANNEL_GROUP(channel)] = (value)) /*! @brief DMA descriptor structure */ -typedef struct _dma_descriptor { - uint32_t xfercfg; /*!< Transfer configuration */ - void *srcEndAddr; /*!< Last source address of DMA transfer */ - void *dstEndAddr; /*!< Last destination address of DMA transfer */ - void *linkToNextDesc; /*!< Address of next DMA descriptor in chain */ +typedef struct _dma_descriptor +{ + volatile uint32_t xfercfg; /*!< Transfer configuration */ + void *srcEndAddr; /*!< Last source address of DMA transfer */ + void *dstEndAddr; /*!< Last destination address of DMA transfer */ + void *linkToNextDesc; /*!< Address of next DMA descriptor in chain */ } dma_descriptor_t; /*! @brief DMA transfer configuration */ -typedef struct _dma_xfercfg { +typedef struct _dma_xfercfg +{ bool valid; /*!< Descriptor is ready to transfer */ bool reload; /*!< Reload channel configuration register after current descriptor is exhausted */ @@ -82,55 +75,74 @@ typedef struct _dma_xfercfg { } dma_xfercfg_t; /*! @brief DMA channel priority */ -typedef enum _dma_priority { - kDMA_ChannelPriority0 = 0, /*!< Highest channel priority - priority 0 */ - kDMA_ChannelPriority1, /*!< Channel priority 1 */ - kDMA_ChannelPriority2, /*!< Channel priority 2 */ - kDMA_ChannelPriority3, /*!< Channel priority 3 */ - kDMA_ChannelPriority4, /*!< Channel priority 4 */ - kDMA_ChannelPriority5, /*!< Channel priority 5 */ - kDMA_ChannelPriority6, /*!< Channel priority 6 */ - kDMA_ChannelPriority7, /*!< Lowest channel priority - priority 7 */ +typedef enum _dma_priority +{ + kDMA_ChannelPriority0 = 0, /*!< Highest channel priority - priority 0 */ + kDMA_ChannelPriority1, /*!< Channel priority 1 */ + kDMA_ChannelPriority2, /*!< Channel priority 2 */ + kDMA_ChannelPriority3, /*!< Channel priority 3 */ + kDMA_ChannelPriority4, /*!< Channel priority 4 */ + kDMA_ChannelPriority5, /*!< Channel priority 5 */ + kDMA_ChannelPriority6, /*!< Channel priority 6 */ + kDMA_ChannelPriority7, /*!< Lowest channel priority - priority 7 */ } dma_priority_t; /*! @brief DMA interrupt flags */ -typedef enum _dma_int { - kDMA_IntA, /*!< DMA interrupt flag A */ - kDMA_IntB, /*!< DMA interrupt flag B */ +typedef enum _dma_int +{ + kDMA_IntA, /*!< DMA interrupt flag A */ + kDMA_IntB, /*!< DMA interrupt flag B */ + kDMA_IntError, /*!< DMA interrupt flag error */ } dma_irq_t; /*! @brief DMA trigger type*/ -typedef enum _dma_trigger_type { - kDMA_NoTrigger = 0, /*!< Trigger is disabled */ +typedef enum _dma_trigger_type +{ + kDMA_NoTrigger = 0, /*!< Trigger is disabled */ kDMA_LowLevelTrigger = DMA_CHANNEL_CFG_HWTRIGEN(1) | DMA_CHANNEL_CFG_TRIGTYPE(1), /*!< Low level active trigger */ - kDMA_HighLevelTrigger = DMA_CHANNEL_CFG_HWTRIGEN(1) | DMA_CHANNEL_CFG_TRIGTYPE(1) | DMA_CHANNEL_CFG_TRIGPOL(1), /*!< High level active trigger */ + kDMA_HighLevelTrigger = DMA_CHANNEL_CFG_HWTRIGEN(1) | DMA_CHANNEL_CFG_TRIGTYPE(1) | + DMA_CHANNEL_CFG_TRIGPOL(1), /*!< High level active trigger */ kDMA_FallingEdgeTrigger = DMA_CHANNEL_CFG_HWTRIGEN(1), /*!< Falling edge active trigger */ - kDMA_RisingEdgeTrigger = DMA_CHANNEL_CFG_HWTRIGEN(1) | DMA_CHANNEL_CFG_TRIGPOL(1), /*!< Rising edge active trigger */ + kDMA_RisingEdgeTrigger = + DMA_CHANNEL_CFG_HWTRIGEN(1) | DMA_CHANNEL_CFG_TRIGPOL(1), /*!< Rising edge active trigger */ } dma_trigger_type_t; /*! @brief DMA trigger burst */ -typedef enum _dma_trigger_burst { - kDMA_SingleTransfer = 0, /*!< Single transfer */ - kDMA_LevelBurstTransfer = DMA_CHANNEL_CFG_TRIGBURST(1), /*!< Burst transfer driven by level trigger */ - kDMA_EdgeBurstTransfer1 = DMA_CHANNEL_CFG_TRIGBURST(1), /*!< Perform 1 transfer by edge trigger */ - kDMA_EdgeBurstTransfer2 = DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(1), /*!< Perform 2 transfers by edge trigger */ - kDMA_EdgeBurstTransfer4 = DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(2), /*!< Perform 4 transfers by edge trigger */ - kDMA_EdgeBurstTransfer8 = DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(3), /*!< Perform 8 transfers by edge trigger */ - kDMA_EdgeBurstTransfer16 = DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(4), /*!< Perform 16 transfers by edge trigger */ - kDMA_EdgeBurstTransfer32 = DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(5), /*!< Perform 32 transfers by edge trigger */ - kDMA_EdgeBurstTransfer64 = DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(6), /*!< Perform 64 transfers by edge trigger */ - kDMA_EdgeBurstTransfer128 = DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(7), /*!< Perform 128 transfers by edge trigger */ - kDMA_EdgeBurstTransfer256 = DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(8), /*!< Perform 256 transfers by edge trigger */ - kDMA_EdgeBurstTransfer512 = DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(9), /*!< Perform 512 transfers by edge trigger */ - kDMA_EdgeBurstTransfer1024 = DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(10), /*!< Perform 1024 transfers by edge trigger */ -} dma_trigger_burst_t; +typedef enum _dma_trigger_burst +{ + kDMA_SingleTransfer = 0, /*!< Single transfer */ + kDMA_LevelBurstTransfer = DMA_CHANNEL_CFG_TRIGBURST(1), /*!< Burst transfer driven by level trigger */ + kDMA_EdgeBurstTransfer1 = DMA_CHANNEL_CFG_TRIGBURST(1), /*!< Perform 1 transfer by edge trigger */ + kDMA_EdgeBurstTransfer2 = + DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(1), /*!< Perform 2 transfers by edge trigger */ + kDMA_EdgeBurstTransfer4 = + DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(2), /*!< Perform 4 transfers by edge trigger */ + kDMA_EdgeBurstTransfer8 = + DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(3), /*!< Perform 8 transfers by edge trigger */ + kDMA_EdgeBurstTransfer16 = + DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(4), /*!< Perform 16 transfers by edge trigger */ + kDMA_EdgeBurstTransfer32 = + DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(5), /*!< Perform 32 transfers by edge trigger */ + kDMA_EdgeBurstTransfer64 = + DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(6), /*!< Perform 64 transfers by edge trigger */ + kDMA_EdgeBurstTransfer128 = + DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(7), /*!< Perform 128 transfers by edge trigger */ + kDMA_EdgeBurstTransfer256 = + DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(8), /*!< Perform 256 transfers by edge trigger */ + kDMA_EdgeBurstTransfer512 = + DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(9), /*!< Perform 512 transfers by edge trigger */ + kDMA_EdgeBurstTransfer1024 = + DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(10), /*!< Perform 1024 transfers by edge trigger */ +} dma_trigger_burst_t; /*! @brief DMA burst wrapping */ -typedef enum _dma_burst_wrap { - kDMA_NoWrap = 0, /*!< Wrapping is disabled */ - kDMA_SrcWrap = DMA_CHANNEL_CFG_SRCBURSTWRAP(1), /*!< Wrapping is enabled for source */ - kDMA_DstWrap = DMA_CHANNEL_CFG_DSTBURSTWRAP(1), /*!< Wrapping is enabled for destination */ - kDMA_SrcAndDstWrap = DMA_CHANNEL_CFG_SRCBURSTWRAP(1) | DMA_CHANNEL_CFG_DSTBURSTWRAP(1), /*!< Wrapping is enabled for source and destination */ +typedef enum _dma_burst_wrap +{ + kDMA_NoWrap = 0, /*!< Wrapping is disabled */ + kDMA_SrcWrap = DMA_CHANNEL_CFG_SRCBURSTWRAP(1), /*!< Wrapping is enabled for source */ + kDMA_DstWrap = DMA_CHANNEL_CFG_DSTBURSTWRAP(1), /*!< Wrapping is enabled for destination */ + kDMA_SrcAndDstWrap = DMA_CHANNEL_CFG_SRCBURSTWRAP(1) | + DMA_CHANNEL_CFG_DSTBURSTWRAP(1), /*!< Wrapping is enabled for source and destination */ } dma_burst_wrap_t; /*! @brief DMA transfer type */ @@ -143,27 +155,28 @@ typedef enum _dma_transfer_type } dma_transfer_type_t; /*! @brief DMA channel trigger */ -typedef struct _dma_channel_trigger { - dma_trigger_type_t type; - dma_trigger_burst_t burst; - dma_burst_wrap_t wrap; +typedef struct _dma_channel_trigger +{ + dma_trigger_type_t type; /*!< Select hardware trigger as edge triggered or level triggered. */ + dma_trigger_burst_t burst; /*!< Select whether hardware triggers cause a single or burst transfer. */ + dma_burst_wrap_t wrap; /*!< Select wrap type, source wrap or dest wrap, or both. */ } dma_channel_trigger_t; /*! @brief DMA transfer status */ enum _dma_transfer_status { - kStatus_DMA_Busy = MAKE_STATUS(kStatusGroup_DMA, 0), /*!< Channel is busy and can't handle the - transfer request. */ + kStatus_DMA_Busy = MAKE_STATUS(kStatusGroup_DMA, 0), /*!< Channel is busy and can't handle the + transfer request. */ }; /*! @brief DMA transfer configuration */ typedef struct _dma_transfer_config { - uint8_t *srcAddr; /*!< Source data address */ - uint8_t *dstAddr; /*!< Destination data address */ - uint8_t *nextDesc; /*!< Chain custom descriptor */ - dma_xfercfg_t xfercfg; /*!< Transfer options */ - bool isPeriph; /*!< DMA transfer is driven by peripheral */ + uint8_t *srcAddr; /*!< Source data address */ + uint8_t *dstAddr; /*!< Destination data address */ + uint8_t *nextDesc; /*!< Chain custom descriptor */ + dma_xfercfg_t xfercfg; /*!< Transfer options */ + bool isPeriph; /*!< DMA transfer is driven by peripheral */ } dma_transfer_config_t; /*! @brief Callback for DMA */ @@ -175,11 +188,11 @@ typedef void (*dma_callback)(struct _dma_handle *handle, void *userData, bool tr /*! @brief DMA transfer handle structure */ typedef struct _dma_handle { - dma_callback callback; /*!< Callback function. Invoked when transfer - of descriptor with interrupt flag finishes */ - void *userData; /*!< Callback function parameter */ - DMA_Type *base; /*!< DMA peripheral base address */ - uint8_t channel; /*!< DMA channel number */ + dma_callback callback; /*!< Callback function. Invoked when transfer + of descriptor with interrupt flag finishes */ + void *userData; /*!< Callback function parameter */ + DMA_Type *base; /*!< DMA peripheral base address */ + uint8_t channel; /*!< DMA channel number */ } dma_handle_t; /******************************************************************************* @@ -219,17 +232,17 @@ void DMA_Deinit(DMA_Type *base); * @{ */ - /*! - * @brief Return whether DMA channel is processing transfer - * - * @param base DMA peripheral base address. - * @param channel DMA channel number. - * @return True for active state, false otherwise. - */ +/*! +* @brief Return whether DMA channel is processing transfer +* +* @param base DMA peripheral base address. +* @param channel DMA channel number. +* @return True for active state, false otherwise. +*/ static inline bool DMA_ChannelIsActive(DMA_Type *base, uint32_t channel) { - assert(channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELS); - return (base->COMMON[DMA_CHANNEL_GROUP(channel)].ACTIVE & (1U << DMA_CHANNEL_INDEX(channel))) ? true : false; + assert(channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base)); + return (DMA_COMMON_CONST_REG_GET(base, channel, ACTIVE) & (1U << DMA_CHANNEL_INDEX(channel))) ? true : false; } /*! @@ -240,8 +253,8 @@ static inline bool DMA_ChannelIsActive(DMA_Type *base, uint32_t channel) */ static inline void DMA_EnableChannelInterrupts(DMA_Type *base, uint32_t channel) { - assert(channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELS); - base->COMMON[DMA_CHANNEL_GROUP(channel)].INTENSET |= 1U << DMA_CHANNEL_INDEX(channel); + assert(channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base)); + DMA_COMMON_REG_GET(base, channel, INTENSET) |= 1U << DMA_CHANNEL_INDEX(channel); } /*! @@ -252,8 +265,8 @@ static inline void DMA_EnableChannelInterrupts(DMA_Type *base, uint32_t channel) */ static inline void DMA_DisableChannelInterrupts(DMA_Type *base, uint32_t channel) { - assert(channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELS); - base->COMMON[DMA_CHANNEL_GROUP(channel)].INTENCLR |= 1U << DMA_CHANNEL_INDEX(channel); + assert(channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base)); + DMA_COMMON_REG_GET(base, channel, INTENCLR) |= 1U << DMA_CHANNEL_INDEX(channel); } /*! @@ -264,8 +277,8 @@ static inline void DMA_DisableChannelInterrupts(DMA_Type *base, uint32_t channel */ static inline void DMA_EnableChannel(DMA_Type *base, uint32_t channel) { - assert(channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELS); - base->COMMON[DMA_CHANNEL_GROUP(channel)].ENABLESET |= 1U << DMA_CHANNEL_INDEX(channel); + assert(channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base)); + DMA_COMMON_REG_GET(base, channel, ENABLESET) |= 1U << DMA_CHANNEL_INDEX(channel); } /*! @@ -276,8 +289,8 @@ static inline void DMA_EnableChannel(DMA_Type *base, uint32_t channel) */ static inline void DMA_DisableChannel(DMA_Type *base, uint32_t channel) { - assert(channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELS); - base->COMMON[DMA_CHANNEL_GROUP(channel)].ENABLECLR |= 1U << DMA_CHANNEL_INDEX(channel); + assert(channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base)); + DMA_COMMON_REG_GET(base, channel, ENABLECLR) |= 1U << DMA_CHANNEL_INDEX(channel); } /*! @@ -288,7 +301,7 @@ static inline void DMA_DisableChannel(DMA_Type *base, uint32_t channel) */ static inline void DMA_EnableChannelPeriphRq(DMA_Type *base, uint32_t channel) { - assert(channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELS); + assert(channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base)); base->CHANNEL[channel].CFG |= DMA_CHANNEL_CFG_PERIPHREQEN_MASK; } @@ -301,7 +314,7 @@ static inline void DMA_EnableChannelPeriphRq(DMA_Type *base, uint32_t channel) */ static inline void DMA_DisableChannelPeriphRq(DMA_Type *base, uint32_t channel) { - assert(channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELS); + assert(channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base)); base->CHANNEL[channel].CFG &= ~DMA_CHANNEL_CFG_PERIPHREQEN_MASK; } @@ -332,8 +345,9 @@ uint32_t DMA_GetRemainingBytes(DMA_Type *base, uint32_t channel); */ static inline void DMA_SetChannelPriority(DMA_Type *base, uint32_t channel, dma_priority_t priority) { - assert(channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELS); - base->CHANNEL[channel].CFG = (base->CHANNEL[channel].CFG & (~(DMA_CHANNEL_CFG_CHPRIORITY_MASK))) | DMA_CHANNEL_CFG_CHPRIORITY(priority); + assert(channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base)); + base->CHANNEL[channel].CFG = + (base->CHANNEL[channel].CFG & (~(DMA_CHANNEL_CFG_CHPRIORITY_MASK))) | DMA_CHANNEL_CFG_CHPRIORITY(priority); } /*! @@ -345,12 +359,13 @@ static inline void DMA_SetChannelPriority(DMA_Type *base, uint32_t channel, dma_ */ static inline dma_priority_t DMA_GetChannelPriority(DMA_Type *base, uint32_t channel) { - assert(channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELS); - return (dma_priority_t)((base->CHANNEL[channel].CFG & DMA_CHANNEL_CFG_CHPRIORITY_MASK) >> DMA_CHANNEL_CFG_CHPRIORITY_SHIFT); + assert(channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base)); + return (dma_priority_t)((base->CHANNEL[channel].CFG & DMA_CHANNEL_CFG_CHPRIORITY_MASK) >> + DMA_CHANNEL_CFG_CHPRIORITY_SHIFT); } /*! - * @brief Create application specific DMA descriptor + * @brief Create application specific DMA descriptor * to be used in a chain in transfer * * @param desc DMA descriptor address. @@ -359,13 +374,7 @@ static inline dma_priority_t DMA_GetChannelPriority(DMA_Type *base, uint32_t cha * @param dstAddr Address of last item to receive. * @param nextDesc Address of next descriptor in chain. */ -void DMA_CreateDescriptor( - dma_descriptor_t *desc, - dma_xfercfg_t *xfercfg, - void *srcAddr, - void *dstAddr, - void *nextDesc -); +void DMA_CreateDescriptor(dma_descriptor_t *desc, dma_xfercfg_t *xfercfg, void *srcAddr, void *dstAddr, void *nextDesc); /* @} */ @@ -379,7 +388,7 @@ void DMA_CreateDescriptor( * * This function aborts DMA transfer specified by handle. * - * @param handle DMA handle pointer. + * @param handle DMA handle pointer. */ void DMA_AbortTransfer(dma_handle_t *handle); @@ -425,12 +434,12 @@ void DMA_SetCallback(dma_handle_t *handle, dma_callback callback, void *userData * source address error(SAE). */ void DMA_PrepareTransfer(dma_transfer_config_t *config, - void *srcAddr, - void *dstAddr, - uint32_t byteWidth, - uint32_t transferBytes, - dma_transfer_type_t type, - void *nextDesc); + void *srcAddr, + void *dstAddr, + uint32_t byteWidth, + uint32_t transferBytes, + dma_transfer_type_t type, + void *nextDesc); /*! * @brief Submits the DMA transfer request. diff --git a/ext/hal/nxp/mcux/drivers/lpc/fsl_dmic.c b/ext/hal/nxp/mcux/drivers/lpc/fsl_dmic.c index bf88fd76b96..362f51a4403 100644 --- a/ext/hal/nxp/mcux/drivers/lpc/fsl_dmic.c +++ b/ext/hal/nxp/mcux/drivers/lpc/fsl_dmic.c @@ -1,35 +1,18 @@ /* * Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP + * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * SPDX-License-Identifier: BSD-3-Clause */ #include "fsl_dmic.h" +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.dmic" +#endif + /******************************************************************************* * Variables ******************************************************************************/ @@ -37,8 +20,10 @@ /* Array of DMIC peripheral base address. */ static DMIC_Type *const s_dmicBases[FSL_FEATURE_SOC_DMIC_COUNT] = DMIC_BASE_PTRS; +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) /* Array of DMIC clock name. */ static const clock_ip_name_t s_dmicClock[FSL_FEATURE_SOC_DMIC_COUNT] = DMIC_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ /* Array of DMIC IRQ number. */ static const IRQn_Type s_dmicIRQ[FSL_FEATURE_SOC_DMIC_COUNT] = DMIC_IRQS; @@ -61,6 +46,12 @@ static dmic_hwvad_callback_t s_dmicHwvadCallback[FSL_FEATURE_SOC_DMIC_COUNT]; * @param base DMIC peripheral base address. * @return DMIC instance. */ +/*! + * brief Get the DMIC instance from peripheral base address. + * + * param base DMIC peripheral base address. + * return DMIC instance. + */ uint32_t DMIC_GetInstance(DMIC_Type *base) { uint32_t instance; @@ -79,15 +70,24 @@ uint32_t DMIC_GetInstance(DMIC_Type *base) return instance; } +/*! + * brief Turns DMIC Clock on + * param base : DMIC base + * return Nothing + */ void DMIC_Init(DMIC_Type *base) { assert(base); - /* Enable the clock to the register interface */ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Enable the clock. */ CLOCK_EnableClock(s_dmicClock[DMIC_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - /* Reset the peripheral */ +#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) + /* Reset the module. */ RESET_PeripheralReset(kDMIC_RST_SHIFT_RSTn); +#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ /* Disable DMA request*/ base->CHANNEL[0].FIFO_CTRL &= ~DMIC_CHANNEL_FIFO_CTRL_DMAEN(1); @@ -98,18 +98,38 @@ void DMIC_Init(DMIC_Type *base) base->CHANNEL[1].FIFO_CTRL &= ~DMIC_CHANNEL_FIFO_CTRL_INTEN(1); } +/*! + * brief Turns DMIC Clock off + * param base : DMIC base + * return Nothing + */ void DMIC_DeInit(DMIC_Type *base) { assert(base); - /* Disable the clock to the register interface */ + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Disable the clock. */ CLOCK_DisableClock(s_dmicClock[DMIC_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ } +/*! + * brief Configure DMIC io + * param base : The base address of DMIC interface + * param config : DMIC io configuration + * return Nothing + */ void DMIC_ConfigIO(DMIC_Type *base, dmic_io_t config) { base->IOCFG = config; } +/*! + * brief Set DMIC operating mode + * param base : The base address of DMIC interface + * param mode : DMIC mode + * return Nothing + */ void DMIC_SetOperationMode(DMIC_Type *base, operation_mode_t mode) { if (mode == kDMIC_OperationModeInterrupt) @@ -126,6 +146,14 @@ void DMIC_SetOperationMode(DMIC_Type *base, operation_mode_t mode) } } +/*! + * brief Configure DMIC channel + * param base : The base address of DMIC interface + * param channel : DMIC channel + * param side : stereo_side_t, choice of left or right + * param channel_config : Channel configuration + * return Nothing + */ void DMIC_ConfigChannel(DMIC_Type *base, dmic_channel_t channel, stereo_side_t side, @@ -143,6 +171,14 @@ void DMIC_ConfigChannel(DMIC_Type *base, DMIC_CHANNEL_DC_CTRL_SATURATEAT16BIT(channel_config->saturate16bit); } +/*! + * brief Configure DMIC channel + * param base : The base address of DMIC interface + * param channel : DMIC channel + * param dc_cut_level : dc_removal_t, Cut off Frequency + * param post_dc_gain_reduce : Fine gain adjustment in the form of a number of bits to downshift. + * param saturate16bit : If selects 16-bit saturation. + */ void DMIC_CfgChannelDc(DMIC_Type *base, dmic_channel_t channel, dc_removal_t dc_cut_level, @@ -154,16 +190,37 @@ void DMIC_CfgChannelDc(DMIC_Type *base, DMIC_CHANNEL_DC_CTRL_SATURATEAT16BIT(saturate16bit); } +/*! + * brief Configure Clock scaling + * param base : The base address of DMIC interface + * param use2fs : clock scaling + * return Nothing + */ void DMIC_Use2fs(DMIC_Type *base, bool use2fs) { base->USE2FS = (use2fs) ? 0x1 : 0x0; } +/*! + * brief Enable a particualr channel + * param base : The base address of DMIC interface + * param channelmask : Channel selection + * return Nothing + */ void DMIC_EnableChannnel(DMIC_Type *base, uint32_t channelmask) { base->CHANEN = channelmask; } +/*! + * brief Configure fifo settings for DMIC channel + * param base : The base address of DMIC interface + * param channel : DMIC channel + * param trig_level : FIFO trigger level + * param enable : FIFO level + * param resetn : FIFO reset + * return Nothing + */ void DMIC_FifoChannel(DMIC_Type *base, uint32_t channel, uint32_t trig_level, uint32_t enable, uint32_t resetn) { base->CHANNEL[channel].FIFO_CTRL |= @@ -172,6 +229,16 @@ void DMIC_FifoChannel(DMIC_Type *base, uint32_t channel, uint32_t trig_level, ui DMIC_CHANNEL_FIFO_CTRL_RESETN(resetn); } +/*! + * brief Enable callback. + + * This function enables the interrupt for the selected DMIC peripheral. + * The callback function is not enabled until this function is called. + * + * param base Base address of the DMIC peripheral. + * param cb callback Pointer to store callback function. + * retval None. + */ void DMIC_EnableIntCallback(DMIC_Type *base, dmic_callback_t cb) { uint32_t instance; @@ -183,6 +250,15 @@ void DMIC_EnableIntCallback(DMIC_Type *base, dmic_callback_t cb) EnableIRQ(s_dmicIRQ[instance]); } +/*! + * brief Disable callback. + + * This function disables the interrupt for the selected DMIC peripheral. + * + * param base Base address of the DMIC peripheral. + * param cb callback Pointer to store callback function.. + * retval None. + */ void DMIC_DisableIntCallback(DMIC_Type *base, dmic_callback_t cb) { uint32_t instance; @@ -193,6 +269,16 @@ void DMIC_DisableIntCallback(DMIC_Type *base, dmic_callback_t cb) NVIC_ClearPendingIRQ(s_dmicIRQ[instance]); } +/*! + * brief Enable hwvad callback. + + * This function enables the hwvad interrupt for the selected DMIC peripheral. + * The callback function is not enabled until this function is called. + * + * param base Base address of the DMIC peripheral. + * param vadcb callback Pointer to store callback function. + * retval None. + */ void DMIC_HwvadEnableIntCallback(DMIC_Type *base, dmic_hwvad_callback_t vadcb) { uint32_t instance; @@ -204,6 +290,15 @@ void DMIC_HwvadEnableIntCallback(DMIC_Type *base, dmic_hwvad_callback_t vadcb) EnableIRQ(s_dmicHwvadIRQ[instance]); } +/*! + * brief Disable callback. + + * This function disables the hwvad interrupt for the selected DMIC peripheral. + * + * param base Base address of the DMIC peripheral. + * param vadcb callback Pointer to store callback function.. + * retval None. + */ void DMIC_HwvadDisableIntCallback(DMIC_Type *base, dmic_hwvad_callback_t vadcb) { uint32_t instance; @@ -223,13 +318,23 @@ void DMIC0_DriverIRQHandler(void) { s_dmicCallback[0](); } +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif } /*DMIC0 HWVAD IRQ handler */ -void HWVAD0_IRQHandler(void) +void HWVAD0_DriverIRQHandler(void) { if (s_dmicHwvadCallback[0] != NULL) { s_dmicHwvadCallback[0](); } +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif } #endif diff --git a/ext/hal/nxp/mcux/drivers/lpc/fsl_dmic.h b/ext/hal/nxp/mcux/drivers/lpc/fsl_dmic.h index a97948d7df7..99e9a85e04a 100644 --- a/ext/hal/nxp/mcux/drivers/lpc/fsl_dmic.h +++ b/ext/hal/nxp/mcux/drivers/lpc/fsl_dmic.h @@ -1,31 +1,9 @@ /* * Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP + * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * SPDX-License-Identifier: BSD-3-Clause */ #ifndef _FSL_DMIC_H_ @@ -49,8 +27,8 @@ * @{ */ -/*! @brief DMIC driver version 2.0.0. */ -#define FSL_DMIC_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) +/*! @brief DMIC driver version 2.0.1. */ +#define FSL_DMIC_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) /*@}*/ /*! @brief DMIC different operation modes. */ @@ -222,6 +200,20 @@ void DMIC_ConfigChannel(DMIC_Type *base, stereo_side_t side, dmic_channel_config_t *channel_config); +/*! + * @brief Configure DMIC channel + * @param base : The base address of DMIC interface + * @param channel : DMIC channel + * @param dc_cut_level : dc_removal_t, Cut off Frequency + * @param post_dc_gain_reduce : Fine gain adjustment in the form of a number of bits to downshift. + * @param saturate16bit : If selects 16-bit saturation. + */ +void DMIC_CfgChannelDc(DMIC_Type *base, + dmic_channel_t channel, + dc_removal_t dc_cut_level, + uint32_t post_dc_gain_reduce, + bool saturate16bit); + /*! * @brief Configure Clock scaling * @param base : The base address of DMIC interface diff --git a/ext/hal/nxp/mcux/drivers/lpc/fsl_dmic_dma.c b/ext/hal/nxp/mcux/drivers/lpc/fsl_dmic_dma.c index 8ac8ffffc47..1bb52ac6d2a 100644 --- a/ext/hal/nxp/mcux/drivers/lpc/fsl_dmic_dma.c +++ b/ext/hal/nxp/mcux/drivers/lpc/fsl_dmic_dma.c @@ -1,31 +1,9 @@ /* * Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP + * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * SPDX-License-Identifier: BSD-3-Clause */ #include "fsl_dmic_dma.h" @@ -33,6 +11,12 @@ /******************************************************************************* * Definitions ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.dmic_dma" +#endif + #define DMIC_HANDLE_ARRAY_SIZE 1 /*CHANNEL[dmic_channel].FIFO_DATA); /* Check if the device is busy. If previous RX not finished.*/ if (handle->state == kDMIC_Busy) @@ -157,8 +156,8 @@ status_t DMIC_TransferReceiveDMA(DMIC_Type *base, handle->transferSize = xfer->dataSize; /* Prepare transfer. */ - DMA_PrepareTransfer(&xferConfig, (void *)&base->CHANNEL[dmic_channel].FIFO_DATA, xfer->data, sizeof(uint16_t), - xfer->dataSize, kDMA_PeripheralToMemory, NULL); + DMA_PrepareTransfer(&xferConfig, (void *)srcAddr, xfer->data, sizeof(uint16_t), xfer->dataSize, + kDMA_PeripheralToMemory, NULL); /* Submit transfer. */ DMA_SubmitTransfer(handle->rxDmaHandle, &xferConfig); @@ -170,6 +169,14 @@ status_t DMIC_TransferReceiveDMA(DMIC_Type *base, return status; } +/*! + * brief Aborts the received data using DMA. + * + * This function aborts the received data using DMA. + * + * param base DMIC peripheral base address + * param handle Pointer to dmic_dma_handle_t structure + */ void DMIC_TransferAbortReceiveDMA(DMIC_Type *base, dmic_dma_handle_t *handle) { assert(NULL != handle); @@ -180,6 +187,18 @@ void DMIC_TransferAbortReceiveDMA(DMIC_Type *base, dmic_dma_handle_t *handle) handle->state = kDMIC_Idle; } +/*! + * brief Get the number of bytes that have been received. + * + * This function gets the number of bytes that have been received. + * + * param base DMIC peripheral base address. + * param handle DMIC handle pointer. + * param count Receive bytes count. + * retval kStatus_NoTransferInProgress No receive in progress. + * retval kStatus_InvalidArgument Parameter is invalid. + * retval kStatus_Success Get successfully through the parameter count; + */ status_t DMIC_TransferGetReceiveCountDMA(DMIC_Type *base, dmic_dma_handle_t *handle, uint32_t *count) { assert(handle); diff --git a/ext/hal/nxp/mcux/drivers/lpc/fsl_dmic_dma.h b/ext/hal/nxp/mcux/drivers/lpc/fsl_dmic_dma.h index 8d3be059b0a..643d0dc6532 100644 --- a/ext/hal/nxp/mcux/drivers/lpc/fsl_dmic_dma.h +++ b/ext/hal/nxp/mcux/drivers/lpc/fsl_dmic_dma.h @@ -1,31 +1,9 @@ /* * Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause */ #ifndef _FSL_DMIC_DMA_H_ #define _FSL_DMIC_DMA_H_ @@ -44,6 +22,15 @@ * Definitions ******************************************************************************/ +/*! + * @name DMIC DMA version + * @{ + */ + +/*! @brief DMIC DMA driver version 2.0.0. */ +#define FSL_DMIC_DMA_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) +/*@}*/ + /*! @brief DMIC transfer structure. */ typedef struct _dmic_transfer { diff --git a/ext/hal/nxp/mcux/drivers/lpc/fsl_flashiap.c b/ext/hal/nxp/mcux/drivers/lpc/fsl_flashiap.c index 862fd2d227a..bda25e8061e 100644 --- a/ext/hal/nxp/mcux/drivers/lpc/fsl_flashiap.c +++ b/ext/hal/nxp/mcux/drivers/lpc/fsl_flashiap.c @@ -1,35 +1,18 @@ /* * Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP + * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * SPDX-License-Identifier: BSD-3-Clause */ #include "fsl_flashiap.h" +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.flashiap" +#endif + #define HZ_TO_KHZ_DIV 1000 /******************************************************************************* @@ -49,6 +32,26 @@ static status_t translate_iap_status(uint32_t status) } } +/*! + * brief Prepare sector for write operation + + * This function prepares sector(s) for write/erase operation. This function must be + * called before calling the FLASHIAP_CopyRamToFlash() or FLASHIAP_EraseSector() or + * FLASHIAP_ErasePage() function. The end sector must be greater than or equal to + * start sector number. + * + * deprecated Do not use this function. It has benn moved to iap driver. + * + * param startSector Start sector number. + * param endSector End sector number. + * + * retval #kStatus_FLASHIAP_Success Api was executed successfully. + * retval #kStatus_FLASHIAP_NoPower Flash memory block is powered down. + * retval #kStatus_FLASHIAP_NoClock Flash memory block or controller is not clocked. + * retval #kStatus_FLASHIAP_InvalidSector Sector number is invalid or end sector number + * is greater than start sector number. + * retval #kStatus_FLASHIAP_Busy Flash programming hardware interface is busy. + */ status_t FLASHIAP_PrepareSectorForWrite(uint32_t startSector, uint32_t endSector) { uint32_t command[5], result[4]; @@ -61,6 +64,32 @@ status_t FLASHIAP_PrepareSectorForWrite(uint32_t startSector, uint32_t endSector return translate_iap_status(result[0]); } +/*! + * brief Copy RAM to flash. + + * This function programs the flash memory. Corresponding sectors must be prepared + * via FLASHIAP_PrepareSectorForWrite before calling calling this function. The addresses + * should be a 256 byte boundary and the number of bytes should be 256 | 512 | 1024 | 4096. + * + * deprecated Do not use this function. It has benn moved to iap driver. + * + * param dstAddr Destination flash address where data bytes are to be written. + * param srcAddr Source ram address from where data bytes are to be read. + * param numOfBytes Number of bytes to be written. + * param systemCoreClock SystemCoreClock in Hz. It is converted to KHz before calling the + * rom IAP function. + * + * retval #kStatus_FLASHIAP_Success Api was executed successfully. + * retval #kStatus_FLASHIAP_NoPower Flash memory block is powered down. + * retval #kStatus_FLASHIAP_NoClock Flash memory block or controller is not clocked. + * retval #kStatus_FLASHIAP_SrcAddrError Source address is not on word boundary. + * retval #kStatus_FLASHIAP_DstAddrError Destination address is not on a correct boundary. + * retval #kStatus_FLASHIAP_SrcAddrNotMapped Source address is not mapped in the memory map. + * retval #kStatus_FLASHIAP_DstAddrNotMapped Destination address is not mapped in the memory map. + * retval #kStatus_FLASHIAP_CountError Byte count is not multiple of 4 or is not a permitted value. + * retval #kStatus_FLASHIAP_NotPrepared Command to prepare sector for write operation was not executed. + * retval #kStatus_FLASHIAP_Busy Flash programming hardware interface is busy. + */ status_t FLASHIAP_CopyRamToFlash(uint32_t dstAddr, uint32_t *srcAddr, uint32_t numOfBytes, uint32_t systemCoreClock) { uint32_t command[5], result[4]; @@ -75,6 +104,28 @@ status_t FLASHIAP_CopyRamToFlash(uint32_t dstAddr, uint32_t *srcAddr, uint32_t n return translate_iap_status(result[0]); } +/*! + * brief Erase sector + + * This function erases sector(s). The end sector must be greater than or equal to + * start sector number. FLASHIAP_PrepareSectorForWrite must be called before + * calling this function. + * + * deprecated Do not use this function. It has benn moved to iap driver. + * + * param startSector Start sector number. + * param endSector End sector number. + * param systemCoreClock SystemCoreClock in Hz. It is converted to KHz before calling the + * rom IAP function. + * + * retval #kStatus_FLASHIAP_Success Api was executed successfully. + * retval #kStatus_FLASHIAP_NoPower Flash memory block is powered down. + * retval #kStatus_FLASHIAP_NoClock Flash memory block or controller is not clocked. + * retval #kStatus_FLASHIAP_InvalidSector Sector number is invalid or end sector number + * is greater than start sector number. + * retval #kStatus_FLASHIAP_NotPrepared Command to prepare sector for write operation was not executed. + * retval #kStatus_FLASHIAP_Busy Flash programming hardware interface is busy. + */ status_t FLASHIAP_EraseSector(uint32_t startSector, uint32_t endSector, uint32_t systemCoreClock) { uint32_t command[5], result[4]; @@ -88,6 +139,27 @@ status_t FLASHIAP_EraseSector(uint32_t startSector, uint32_t endSector, uint32_t return translate_iap_status(result[0]); } +/*! + + * This function erases page(s). The end page must be greater than or equal to + * start page number. Corresponding sectors must be prepared via FLASHIAP_PrepareSectorForWrite + * before calling calling this function. + * + * deprecated Do not use this function. It has benn moved to iap driver. + * + * param startPage Start page number + * param endPage End page number + * param systemCoreClock SystemCoreClock in Hz. It is converted to KHz before calling the + * rom IAP function. + * + * retval #kStatus_FLASHIAP_Success Api was executed successfully. + * retval #kStatus_FLASHIAP_NoPower Flash memory block is powered down. + * retval #kStatus_FLASHIAP_NoClock Flash memory block or controller is not clocked. + * retval #kStatus_FLASHIAP_InvalidSector Page number is invalid or end page number + * is greater than start page number + * retval #kStatus_FLASHIAP_NotPrepared Command to prepare sector for write operation was not executed. + * retval #kStatus_FLASHIAP_Busy Flash programming hardware interface is busy. + */ status_t FLASHIAP_ErasePage(uint32_t startPage, uint32_t endPage, uint32_t systemCoreClock) { uint32_t command[5], result[4]; @@ -101,6 +173,21 @@ status_t FLASHIAP_ErasePage(uint32_t startPage, uint32_t endPage, uint32_t syste return translate_iap_status(result[0]); } +/*! + * brief Blank check sector(s) + * + * Blank check single or multiples sectors of flash memory. The end sector must be greater than or equal to + * start sector number. It can be used to verify the sector eraseure after FLASHIAP_EraseSector call. + * + * deprecated Do not use this function. It has benn moved to iap driver. + * + * param startSector : Start sector number. Must be greater than or equal to start sector number + * param endSector : End sector number + * retval #kStatus_FLASHIAP_Success One or more sectors are in erased state. + * retval #kStatus_FLASHIAP_NoPower Flash memory block is powered down. + * retval #kStatus_FLASHIAP_NoClock Flash memory block or controller is not clocked. + * retval #kStatus_FLASHIAP_SectorNotblank One or more sectors are not blank. + */ status_t FLASHIAP_BlankCheckSector(uint32_t startSector, uint32_t endSector) { uint32_t command[5], result[4]; @@ -113,6 +200,26 @@ status_t FLASHIAP_BlankCheckSector(uint32_t startSector, uint32_t endSector) return translate_iap_status(result[0]); } +/*! + * brief Compare memory contents of flash with ram. + + * This function compares the contents of flash and ram. It can be used to verify the flash + * memory contents after FLASHIAP_CopyRamToFlash call. + * + * deprecated Do not use this function. It has benn moved to iap driver. + * + * param dstAddr Destination flash address. + * param srcAddr Source ram address. + * param numOfBytes Number of bytes to be compared. + * + * retval #kStatus_FLASHIAP_Success Contents of flash and ram match. + * retval #kStatus_FLASHIAP_NoPower Flash memory block is powered down. + * retval #kStatus_FLASHIAP_NoClock Flash memory block or controller is not clocked. + * retval #kStatus_FLASHIAP_AddrError Address is not on word boundary. + * retval #kStatus_FLASHIAP_AddrNotMapped Address is not mapped in the memory map. + * retval #kStatus_FLASHIAP_CountError Byte count is not multiple of 4 or is not a permitted value. + * retval #kStatus_FLASHIAP_CompareError Destination and source memory contents do not match. + */ status_t FLASHIAP_Compare(uint32_t dstAddr, uint32_t *srcAddr, uint32_t numOfBytes) { uint32_t command[5], result[4]; diff --git a/ext/hal/nxp/mcux/drivers/lpc/fsl_flashiap.h b/ext/hal/nxp/mcux/drivers/lpc/fsl_flashiap.h index 3325ea7ce98..c1ed85c1e48 100644 --- a/ext/hal/nxp/mcux/drivers/lpc/fsl_flashiap.h +++ b/ext/hal/nxp/mcux/drivers/lpc/fsl_flashiap.h @@ -1,31 +1,9 @@ /* * Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP + * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * SPDX-License-Identifier: BSD-3-Clause */ #ifndef _FSL_FLASHIAP_H_ @@ -46,7 +24,7 @@ /*! @name Driver version */ /*@{*/ -#define FSL_FLASHIAP_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0. */ +#define FSL_FLASHIAP_DRIVER_VERSION (MAKE_VERSION(2, 0, 3)) /*!< Version 2.0.3. */ /*@}*/ /*! @@ -139,6 +117,8 @@ static inline void iap_entry(uint32_t *cmd_param, uint32_t *status_result) * FLASHIAP_ErasePage() function. The end sector must be greater than or equal to * start sector number. * + * @deprecated Do not use this function. It has benn moved to iap driver. + * * @param startSector Start sector number. * @param endSector End sector number. * @@ -158,6 +138,8 @@ status_t FLASHIAP_PrepareSectorForWrite(uint32_t startSector, uint32_t endSector * via FLASHIAP_PrepareSectorForWrite before calling calling this function. The addresses * should be a 256 byte boundary and the number of bytes should be 256 | 512 | 1024 | 4096. * + * @deprecated Do not use this function. It has benn moved to iap driver. + * * @param dstAddr Destination flash address where data bytes are to be written. * @param srcAddr Source ram address from where data bytes are to be read. * @param numOfBytes Number of bytes to be written. @@ -184,6 +166,8 @@ status_t FLASHIAP_CopyRamToFlash(uint32_t dstAddr, uint32_t *srcAddr, uint32_t n * start sector number. FLASHIAP_PrepareSectorForWrite must be called before * calling this function. * + * @deprecated Do not use this function. It has benn moved to iap driver. + * * @param startSector Start sector number. * @param endSector End sector number. * @param systemCoreClock SystemCoreClock in Hz. It is converted to KHz before calling the @@ -205,6 +189,8 @@ status_t FLASHIAP_EraseSector(uint32_t startSector, uint32_t endSector, uint32_t * start page number. Corresponding sectors must be prepared via FLASHIAP_PrepareSectorForWrite * before calling calling this function. * + * @deprecated Do not use this function. It has benn moved to iap driver. + * * @param startPage Start page number * @param endPage End page number * @param systemCoreClock SystemCoreClock in Hz. It is converted to KHz before calling the @@ -226,6 +212,8 @@ status_t FLASHIAP_ErasePage(uint32_t startPage, uint32_t endPage, uint32_t syste * Blank check single or multiples sectors of flash memory. The end sector must be greater than or equal to * start sector number. It can be used to verify the sector eraseure after FLASHIAP_EraseSector call. * + * @deprecated Do not use this function. It has benn moved to iap driver. + * * @param startSector : Start sector number. Must be greater than or equal to start sector number * @param endSector : End sector number * @retval #kStatus_FLASHIAP_Success One or more sectors are in erased state. @@ -241,6 +229,8 @@ status_t FLASHIAP_BlankCheckSector(uint32_t startSector, uint32_t endSector); * This function compares the contents of flash and ram. It can be used to verify the flash * memory contents after FLASHIAP_CopyRamToFlash call. * + * @deprecated Do not use this function. It has benn moved to iap driver. + * * @param dstAddr Destination flash address. * @param srcAddr Source ram address. * @param numOfBytes Number of bytes to be compared. diff --git a/ext/hal/nxp/mcux/drivers/lpc/fsl_flexcomm.c b/ext/hal/nxp/mcux/drivers/lpc/fsl_flexcomm.c index ffb240e0648..8b8e72851f6 100644 --- a/ext/hal/nxp/mcux/drivers/lpc/fsl_flexcomm.c +++ b/ext/hal/nxp/mcux/drivers/lpc/fsl_flexcomm.c @@ -1,31 +1,9 @@ /* * Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP + * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * SPDX-License-Identifier: BSD-3-Clause */ #include "fsl_common.h" @@ -35,6 +13,20 @@ * Definitions ******************************************************************************/ +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.flexcomm" +#endif + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! @brief Set the FLEXCOMM mode . */ +static status_t FLEXCOMM_SetPeriph(FLEXCOMM_Type *base, FLEXCOMM_PERIPH_T periph, int lock); + +/*! @brief check whether flexcomm supports peripheral type */ +static bool FLEXCOMM_PeripheralIsPresent(FLEXCOMM_Type *base, FLEXCOMM_PERIPH_T periph); + /******************************************************************************* * Variables ******************************************************************************/ @@ -56,6 +48,11 @@ static const uint32_t s_flexcommBaseAddrs[FSL_FEATURE_SOC_FLEXCOMM_COUNT] = FLEX static const clock_ip_name_t s_flexcommClocks[] = FLEXCOMM_CLOCKS; #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +#if !(defined(FSL_FEATURE_FLEXCOMM_HAS_NO_RESET) && FSL_FEATURE_FLEXCOMM_HAS_NO_RESET) +/*! @brief Pointers to FLEXCOMM resets for each instance. */ +static const reset_ip_name_t s_flexcommResets[] = FLEXCOMM_RSTS; +#endif + /******************************************************************************* * Code ******************************************************************************/ @@ -67,13 +64,13 @@ static bool FLEXCOMM_PeripheralIsPresent(FLEXCOMM_Type *base, FLEXCOMM_PERIPH_T { return true; } - else if ((periph >= FLEXCOMM_PERIPH_USART) && (periph <= FLEXCOMM_PERIPH_I2S_TX)) + else if (periph <= FLEXCOMM_PERIPH_I2S_TX) { - return (base->PSELID & (uint32_t)(1 << ((uint32_t)periph + 3))) > 0 ? true : false; + return (base->PSELID & (uint32_t)(1 << ((uint32_t)periph + 3))) > (uint32_t)0 ? true : false; } else if (periph == FLEXCOMM_PERIPH_I2S_RX) { - return (base->PSELID & (1 << 7)) > 0 ? true : false; + return (base->PSELID & (1 << 7)) > (uint32_t)0 ? true : false; } else { @@ -82,6 +79,7 @@ static bool FLEXCOMM_PeripheralIsPresent(FLEXCOMM_Type *base, FLEXCOMM_PERIPH_T } /* Get the index corresponding to the FLEXCOMM */ +/*! brief Returns instance number for FLEXCOMM module with given base address. */ uint32_t FLEXCOMM_GetInstance(void *base) { int i; @@ -99,7 +97,7 @@ uint32_t FLEXCOMM_GetInstance(void *base) } /* Changes FLEXCOMM mode */ -status_t FLEXCOMM_SetPeriph(FLEXCOMM_Type *base, FLEXCOMM_PERIPH_T periph, int lock) +static status_t FLEXCOMM_SetPeriph(FLEXCOMM_Type *base, FLEXCOMM_PERIPH_T periph, int lock) { /* Check whether peripheral type is present */ if (!FLEXCOMM_PeripheralIsPresent(base, periph)) @@ -126,6 +124,7 @@ status_t FLEXCOMM_SetPeriph(FLEXCOMM_Type *base, FLEXCOMM_PERIPH_T periph, int l return kStatus_Success; } +/*! brief Initializes FLEXCOMM and selects peripheral mode according to the second parameter. */ status_t FLEXCOMM_Init(void *base, FLEXCOMM_PERIPH_T periph) { int idx = FLEXCOMM_GetInstance(base); @@ -140,10 +139,17 @@ status_t FLEXCOMM_Init(void *base, FLEXCOMM_PERIPH_T periph) CLOCK_EnableClock(s_flexcommClocks[idx]); #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +#if !(defined(FSL_FEATURE_FLEXCOMM_HAS_NO_RESET) && FSL_FEATURE_FLEXCOMM_HAS_NO_RESET) + /* Reset the FLEXCOMM module */ + RESET_PeripheralReset(s_flexcommResets[idx]); +#endif + /* Set the FLEXCOMM to given peripheral */ return FLEXCOMM_SetPeriph((FLEXCOMM_Type *)base, periph, 0); } +/*! brief Sets IRQ handler for given FLEXCOMM module. It is used by drivers register IRQ handler according to FLEXCOMM + * mode */ void FLEXCOMM_SetIRQHandler(void *base, flexcomm_irq_handler_t handler, void *handle) { uint32_t instance; @@ -155,6 +161,11 @@ void FLEXCOMM_SetIRQHandler(void *base, flexcomm_irq_handler_t handler, void *ha s_flexcommIrqHandler[instance] = NULL; s_flexcommHandle[instance] = handle; s_flexcommIrqHandler[instance] = handler; +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif } /* IRQ handler functions overloading weak symbols in the startup */ @@ -163,6 +174,11 @@ void FLEXCOMM0_DriverIRQHandler(void) { assert(s_flexcommIrqHandler[0]); s_flexcommIrqHandler[0]((void *)s_flexcommBaseAddrs[0], s_flexcommHandle[0]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif } #endif @@ -171,6 +187,11 @@ void FLEXCOMM1_DriverIRQHandler(void) { assert(s_flexcommIrqHandler[1]); s_flexcommIrqHandler[1]((void *)s_flexcommBaseAddrs[1], s_flexcommHandle[1]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif } #endif @@ -179,6 +200,11 @@ void FLEXCOMM2_DriverIRQHandler(void) { assert(s_flexcommIrqHandler[2]); s_flexcommIrqHandler[2]((void *)s_flexcommBaseAddrs[2], s_flexcommHandle[2]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif } #endif @@ -187,6 +213,11 @@ void FLEXCOMM3_DriverIRQHandler(void) { assert(s_flexcommIrqHandler[3]); s_flexcommIrqHandler[3]((void *)s_flexcommBaseAddrs[3], s_flexcommHandle[3]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif } #endif @@ -195,6 +226,11 @@ void FLEXCOMM4_DriverIRQHandler(void) { assert(s_flexcommIrqHandler[4]); s_flexcommIrqHandler[4]((void *)s_flexcommBaseAddrs[4], s_flexcommHandle[4]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif } #endif @@ -204,6 +240,11 @@ void FLEXCOMM5_DriverIRQHandler(void) { assert(s_flexcommIrqHandler[5]); s_flexcommIrqHandler[5]((void *)s_flexcommBaseAddrs[5], s_flexcommHandle[5]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif } #endif @@ -212,6 +253,11 @@ void FLEXCOMM6_DriverIRQHandler(void) { assert(s_flexcommIrqHandler[6]); s_flexcommIrqHandler[6]((void *)s_flexcommBaseAddrs[6], s_flexcommHandle[6]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif } #endif @@ -220,6 +266,11 @@ void FLEXCOMM7_DriverIRQHandler(void) { assert(s_flexcommIrqHandler[7]); s_flexcommIrqHandler[7]((void *)s_flexcommBaseAddrs[7], s_flexcommHandle[7]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif } #endif @@ -228,6 +279,11 @@ void FLEXCOMM8_DriverIRQHandler(void) { assert(s_flexcommIrqHandler[8]); s_flexcommIrqHandler[8]((void *)s_flexcommBaseAddrs[8], s_flexcommHandle[8]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif } #endif @@ -236,5 +292,44 @@ void FLEXCOMM9_DriverIRQHandler(void) { assert(s_flexcommIrqHandler[9]); s_flexcommIrqHandler[9]((void *)s_flexcommBaseAddrs[9], s_flexcommHandle[9]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif + +#if defined(FLEXCOMM14) +void FLEXCOMM14_DriverIRQHandler(void) +{ + uint32_t instance; + + /* Look up instance number */ + instance = FLEXCOMM_GetInstance(FLEXCOMM14); + assert(s_flexcommIrqHandler[instance]); + s_flexcommIrqHandler[instance]((void *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif + +#if defined(FLEXCOMM15) +void FLEXCOMM15_DriverIRQHandler(void) +{ + uint32_t instance; + + /* Look up instance number */ + instance = FLEXCOMM_GetInstance(FLEXCOMM14); + assert(s_flexcommIrqHandler[instance]); + s_flexcommIrqHandler[instance]((void *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif } #endif diff --git a/ext/hal/nxp/mcux/drivers/lpc/fsl_flexcomm.h b/ext/hal/nxp/mcux/drivers/lpc/fsl_flexcomm.h index 3e305dc6202..915e3b81b1b 100644 --- a/ext/hal/nxp/mcux/drivers/lpc/fsl_flexcomm.h +++ b/ext/hal/nxp/mcux/drivers/lpc/fsl_flexcomm.h @@ -1,31 +1,9 @@ /* * Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause */ #ifndef _FSL_FLEXCOMM_H_ #define _FSL_FLEXCOMM_H_ @@ -37,6 +15,12 @@ * @{ */ +/*! @name Driver version */ +/*@{*/ +/*! @brief FlexCOMM driver version 2.0.0. */ +#define FSL_FLEXCOMM_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) +/*@}*/ + /*! @brief FLEXCOMM peripheral modes. */ typedef enum { diff --git a/ext/hal/nxp/mcux/drivers/lpc/fsl_fmeas.c b/ext/hal/nxp/mcux/drivers/lpc/fsl_fmeas.c index 6e6e7c0c663..9e6c6a236a4 100644 --- a/ext/hal/nxp/mcux/drivers/lpc/fsl_fmeas.c +++ b/ext/hal/nxp/mcux/drivers/lpc/fsl_fmeas.c @@ -1,31 +1,9 @@ /* * Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP + * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * SPDX-License-Identifier: BSD-3-Clause */ #include "fsl_fmeas.h" @@ -34,6 +12,11 @@ * Definitions *******************************************************************************/ +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.fmeas" +#endif + /*! @brief Target clock counter value. * According to user manual, 2 has to be subtracted from captured value (CAPVAL). */ #define TARGET_CLOCK_COUNT(base) \ @@ -47,6 +30,14 @@ * Code ******************************************************************************/ +/*! + * brief Returns the computed value for a frequency measurement cycle + * + * param base : SYSCON peripheral base address. + * param refClockRate : Reference clock rate used during the frequency measurement cycle. + * + * return Frequency in Hz. + */ uint32_t FMEAS_GetFrequency(SYSCON_Type *base, uint32_t refClockRate) { uint32_t targetClockCount = TARGET_CLOCK_COUNT(base); diff --git a/ext/hal/nxp/mcux/drivers/lpc/fsl_fmeas.h b/ext/hal/nxp/mcux/drivers/lpc/fsl_fmeas.h index 354f513e972..b24e2f84a05 100644 --- a/ext/hal/nxp/mcux/drivers/lpc/fsl_fmeas.h +++ b/ext/hal/nxp/mcux/drivers/lpc/fsl_fmeas.h @@ -1,31 +1,9 @@ /* * Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause */ #ifndef _FSL_FMEAS_H_ #define _FSL_FMEAS_H_ diff --git a/ext/hal/nxp/mcux/drivers/lpc/fsl_fro_calib.h b/ext/hal/nxp/mcux/drivers/lpc/fsl_fro_calib.h new file mode 100644 index 00000000000..7821d2bc787 --- /dev/null +++ b/ext/hal/nxp/mcux/drivers/lpc/fsl_fro_calib.h @@ -0,0 +1,39 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright (c) 2016 - 2018 , NXP + * All rights reserved. + * + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __FSL_FRO_CALIB_H_ +#define __FSL_FRO_CALIB_H_ +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.fro_calib" +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +/* Returns the version of the FRO Calibration library */ +unsigned int fro_calib_Get_Lib_Ver(void); + +/* timer instance */ +/* timer clock frquency in KHz */ +ErrorCode_t Chip_TIMER_Instance_Freq(CTIMER_Type *base, unsigned int timerFreq); + +/* USB_SOF_Event */ +ErrorCode_t USB_SOF_Event(USBD_HANDLE_T hUsb); + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __FSL_FRO_CALIB_H_ */ diff --git a/ext/hal/nxp/mcux/drivers/lpc/fsl_gint.c b/ext/hal/nxp/mcux/drivers/lpc/fsl_gint.c index ac7c615df8c..da60c3ccb7e 100644 --- a/ext/hal/nxp/mcux/drivers/lpc/fsl_gint.c +++ b/ext/hal/nxp/mcux/drivers/lpc/fsl_gint.c @@ -1,35 +1,18 @@ /* * Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP + * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * SPDX-License-Identifier: BSD-3-Clause */ #include "fsl_gint.h" +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.gint" +#endif + /******************************************************************************* * Variables ******************************************************************************/ @@ -41,8 +24,10 @@ static GINT_Type *const s_gintBases[FSL_FEATURE_SOC_GINT_COUNT] = GINT_BASE_PTRS static const clock_ip_name_t s_gintClocks[FSL_FEATURE_SOC_GINT_COUNT] = GINT_CLOCKS; #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) /*! @brief Resets for each instance. */ static const reset_ip_name_t s_gintResets[FSL_FEATURE_SOC_GINT_COUNT] = GINT_RSTS; +#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ /* @brief Irq number for each instance */ static const IRQn_Type s_gintIRQ[FSL_FEATURE_SOC_GINT_COUNT] = GINT_IRQS; @@ -72,6 +57,15 @@ static uint32_t GINT_GetInstance(GINT_Type *base) return instance; } +/*! + * brief Initialize GINT peripheral. + + * This function initializes the GINT peripheral and enables the clock. + * + * param base Base address of the GINT peripheral. + * + * retval None. + */ void GINT_Init(GINT_Type *base) { uint32_t instance; @@ -85,10 +79,24 @@ void GINT_Init(GINT_Type *base) CLOCK_EnableClock(s_gintClocks[instance]); #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - /* Reset the peripheral */ +#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) + /* Reset the module. */ RESET_PeripheralReset(s_gintResets[instance]); +#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ } +/*! + * brief Setup GINT peripheral control parameters. + + * This function sets the control parameters of GINT peripheral. + * + * param base Base address of the GINT peripheral. + * param comb Controls if the enabled inputs are logically ORed or ANDed for interrupt generation. + * param trig Controls if the enabled inputs are level or edge sensitive based on polarity. + * param callback This function is called when configured group interrupt is generated. + * + * retval None. + */ void GINT_SetCtrl(GINT_Type *base, gint_comb_t comb, gint_trig_t trig, gint_cb_t callback) { uint32_t instance; @@ -101,6 +109,18 @@ void GINT_SetCtrl(GINT_Type *base, gint_comb_t comb, gint_trig_t trig, gint_cb_t s_gintCallback[instance] = callback; } +/*! + * brief Get GINT peripheral control parameters. + + * This function returns the control parameters of GINT peripheral. + * + * param base Base address of the GINT peripheral. + * param comb Pointer to store combine input value. + * param trig Pointer to store trigger value. + * param callback Pointer to store callback function. + * + * retval None. + */ void GINT_GetCtrl(GINT_Type *base, gint_comb_t *comb, gint_trig_t *trig, gint_cb_t *callback) { uint32_t instance; @@ -112,18 +132,58 @@ void GINT_GetCtrl(GINT_Type *base, gint_comb_t *comb, gint_trig_t *trig, gint_cb *callback = s_gintCallback[instance]; } +/*! + * brief Configure GINT peripheral pins. + + * This function enables and controls the polarity of enabled pin(s) of a given port. + * + * param base Base address of the GINT peripheral. + * param port Port number. + * param polarityMask Each bit position selects the polarity of the corresponding enabled pin. + * 0 = The pin is active LOW. 1 = The pin is active HIGH. + * param enableMask Each bit position selects if the corresponding pin is enabled or not. + * 0 = The pin is disabled. 1 = The pin is enabled. + * + * retval None. + */ void GINT_ConfigPins(GINT_Type *base, gint_port_t port, uint32_t polarityMask, uint32_t enableMask) { base->PORT_POL[port] = polarityMask; base->PORT_ENA[port] = enableMask; } +/*! + * brief Get GINT peripheral pin configuration. + + * This function returns the pin configuration of a given port. + * + * param base Base address of the GINT peripheral. + * param port Port number. + * param polarityMask Pointer to store the polarity mask Each bit position indicates the polarity of the corresponding + enabled pin. + * 0 = The pin is active LOW. 1 = The pin is active HIGH. + * param enableMask Pointer to store the enable mask. Each bit position indicates if the corresponding pin is enabled + or not. + * 0 = The pin is disabled. 1 = The pin is enabled. + * + * retval None. + */ void GINT_GetConfigPins(GINT_Type *base, gint_port_t port, uint32_t *polarityMask, uint32_t *enableMask) { *polarityMask = base->PORT_POL[port]; *enableMask = base->PORT_ENA[port]; } +/*! + * brief Enable callback. + + * This function enables the interrupt for the selected GINT peripheral. Although the pin(s) are monitored + * as soon as they are enabled, the callback function is not enabled until this function is called. + * + * param base Base address of the GINT peripheral. + * + * retval None. + */ void GINT_EnableCallback(GINT_Type *base) { uint32_t instance; @@ -136,6 +196,16 @@ void GINT_EnableCallback(GINT_Type *base) EnableIRQ(s_gintIRQ[instance]); } +/*! + * brief Disable callback. + + * This function disables the interrupt for the selected GINT peripheral. Although the pins are still + * being monitored but the callback function is not called. + * + * param base Base address of the peripheral. + * + * retval None. + */ void GINT_DisableCallback(GINT_Type *base) { uint32_t instance; @@ -146,6 +216,15 @@ void GINT_DisableCallback(GINT_Type *base) NVIC_ClearPendingIRQ(s_gintIRQ[instance]); } +/*! + * brief Deinitialize GINT peripheral. + + * This function disables the GINT clock. + * + * param base Base address of the GINT peripheral. + * + * retval None. + */ void GINT_Deinit(GINT_Type *base) { uint32_t instance; @@ -156,8 +235,10 @@ void GINT_Deinit(GINT_Type *base) GINT_DisableCallback(base); s_gintCallback[instance] = NULL; - /* Reset the peripheral */ +#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) + /* Reset the module. */ RESET_PeripheralReset(s_gintResets[instance]); +#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) /* Disable the peripheral clock */ @@ -176,6 +257,11 @@ void GINT0_DriverIRQHandler(void) { s_gintCallback[0](); } +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif } #endif @@ -189,6 +275,11 @@ void GINT1_DriverIRQHandler(void) { s_gintCallback[1](); } +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif } #endif @@ -202,6 +293,11 @@ void GINT2_DriverIRQHandler(void) { s_gintCallback[2](); } +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif } #endif @@ -215,6 +311,11 @@ void GINT3_DriverIRQHandler(void) { s_gintCallback[3](); } +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif } #endif @@ -228,6 +329,11 @@ void GINT4_DriverIRQHandler(void) { s_gintCallback[4](); } +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif } #endif @@ -241,6 +347,11 @@ void GINT5_DriverIRQHandler(void) { s_gintCallback[5](); } +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif } #endif @@ -254,6 +365,11 @@ void GINT6_DriverIRQHandler(void) { s_gintCallback[6](); } +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif } #endif @@ -267,5 +383,10 @@ void GINT7_DriverIRQHandler(void) { s_gintCallback[7](); } +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif } #endif diff --git a/ext/hal/nxp/mcux/drivers/lpc/fsl_gint.h b/ext/hal/nxp/mcux/drivers/lpc/fsl_gint.h index 499536c4ae3..462618e5ea3 100644 --- a/ext/hal/nxp/mcux/drivers/lpc/fsl_gint.h +++ b/ext/hal/nxp/mcux/drivers/lpc/fsl_gint.h @@ -1,31 +1,9 @@ /* * Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP + * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * SPDX-License-Identifier: BSD-3-Clause */ #ifndef _FSL_GINT_H_ @@ -46,7 +24,7 @@ /*! @name Driver version */ /*@{*/ -#define FSL_GINT_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0. */ +#define FSL_GINT_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) /*!< Version 2.0.1. */ /*@}*/ /*! @brief GINT combine inputs type */ diff --git a/ext/hal/nxp/mcux/drivers/lpc/fsl_gpio.c b/ext/hal/nxp/mcux/drivers/lpc/fsl_gpio.c index 3b70fb467ba..89cbba8e024 100644 --- a/ext/hal/nxp/mcux/drivers/lpc/fsl_gpio.c +++ b/ext/hal/nxp/mcux/drivers/lpc/fsl_gpio.c @@ -1,39 +1,30 @@ /* * Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP + * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * SPDX-License-Identifier: BSD-3-Clause */ #include "fsl_gpio.h" +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.lpc_gpio" +#endif + /******************************************************************************* * Variables ******************************************************************************/ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/*! @brief Array to map FGPIO instance number to clock name. */ +static const clock_ip_name_t s_gpioClockName[] = GPIO_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +#if !(defined(FSL_FEATURE_GPIO_HAS_NO_RESET) && FSL_FEATURE_GPIO_HAS_NO_RESET) +/*! @brief Pointers to GPIO resets for each instance. */ +static const reset_ip_name_t s_gpioResets[] = GPIO_RSTS_N; +#endif /******************************************************************************* * Prototypes ************ ******************************************************************/ @@ -41,7 +32,55 @@ /******************************************************************************* * Code ******************************************************************************/ +/*! + * brief Initializes the GPIO peripheral. + * + * This function ungates the GPIO clock. + * + * param base GPIO peripheral base pointer. + * param port GPIO port number. + */ +void GPIO_PortInit(GPIO_Type *base, uint32_t port) +{ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + assert(port < ARRAY_SIZE(s_gpioClockName)); + /* Upgate the GPIO clock */ + CLOCK_EnableClock(s_gpioClockName[port]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +#if !(defined(FSL_FEATURE_GPIO_HAS_NO_RESET) && FSL_FEATURE_GPIO_HAS_NO_RESET) + /* Reset the GPIO module */ + RESET_PeripheralReset(s_gpioResets[port]); +#endif +} + +/*! + * brief Initializes a GPIO pin used by the board. + * + * To initialize the GPIO, define a pin configuration, either input or output, in the user file. + * Then, call the GPIO_PinInit() function. + * + * This is an example to define an input pin or output pin configuration: + * code + * // Define a digital input pin configuration, + * gpio_pin_config_t config = + * { + * kGPIO_DigitalInput, + * 0, + * } + * //Define a digital output pin configuration, + * gpio_pin_config_t config = + * { + * kGPIO_DigitalOutput, + * 0, + * } + * endcode + * + * param base GPIO peripheral base pointer(Typically GPIO) + * param port GPIO port number + * param pin GPIO pin number + * param config GPIO pin configuration pointer + */ void GPIO_PinInit(GPIO_Type *base, uint32_t port, uint32_t pin, const gpio_pin_config_t *config) { if (config->pinDirection == kGPIO_DigitalInput) diff --git a/ext/hal/nxp/mcux/drivers/lpc/fsl_gpio.h b/ext/hal/nxp/mcux/drivers/lpc/fsl_gpio.h index eb384655f1f..77a71da7e9d 100644 --- a/ext/hal/nxp/mcux/drivers/lpc/fsl_gpio.h +++ b/ext/hal/nxp/mcux/drivers/lpc/fsl_gpio.h @@ -1,35 +1,13 @@ /* * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * Copyright 2016-2018 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause */ -#ifndef FSL_GPIO_H_ -#define FSL_GPIO_H_ +#ifndef _LPC_GPIO_H_ +#define _LPC_GPIO_H_ #include "fsl_common.h" @@ -46,8 +24,8 @@ /*! @name Driver version */ /*@{*/ -/*! @brief LPC GPIO driver version 2.0.0. */ -#define FSL_GPIO_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) +/*! @brief LPC GPIO driver version 2.1.2. */ +#define FSL_GPIO_DRIVER_VERSION (MAKE_VERSION(2, 1, 2)) /*@}*/ /*! @brief LPC GPIO direction definition */ @@ -80,6 +58,16 @@ extern "C" { /*! @name GPIO Configuration */ /*@{*/ +/*! + * @brief Initializes the GPIO peripheral. + * + * This function ungates the GPIO clock. + * + * @param base GPIO peripheral base pointer. + * @param port GPIO port number. + */ +void GPIO_PortInit(GPIO_Type *base, uint32_t port); + /*! * @brief Initializes a GPIO pin used by the board. * @@ -124,10 +112,11 @@ void GPIO_PinInit(GPIO_Type *base, uint32_t port, uint32_t pin, const gpio_pin_c * - 0: corresponding pin output low-logic level. * - 1: corresponding pin output high-logic level. */ -static inline void GPIO_WritePinOutput(GPIO_Type *base, uint32_t port, uint32_t pin, uint8_t output) +static inline void GPIO_PinWrite(GPIO_Type *base, uint32_t port, uint32_t pin, uint8_t output) { base->B[port][pin] = output; } + /*@}*/ /*! @name GPIO Input Operations */ /*@{*/ @@ -142,10 +131,11 @@ static inline void GPIO_WritePinOutput(GPIO_Type *base, uint32_t port, uint32_t * - 0: corresponding pin input low-logic level. * - 1: corresponding pin input high-logic level. */ -static inline uint32_t GPIO_ReadPinInput(GPIO_Type *base, uint32_t port, uint32_t pin) +static inline uint32_t GPIO_PinRead(GPIO_Type *base, uint32_t port, uint32_t pin) { return (uint32_t)base->B[port][pin]; } + /*@}*/ /*! @@ -155,7 +145,7 @@ static inline uint32_t GPIO_ReadPinInput(GPIO_Type *base, uint32_t port, uint32_ * @param port GPIO port number * @param mask GPIO pin number macro */ -static inline void GPIO_SetPinsOutput(GPIO_Type *base, uint32_t port, uint32_t mask) +static inline void GPIO_PortSet(GPIO_Type *base, uint32_t port, uint32_t mask) { base->SET[port] = mask; } @@ -167,7 +157,7 @@ static inline void GPIO_SetPinsOutput(GPIO_Type *base, uint32_t port, uint32_t m * @param port GPIO port number * @param mask GPIO pin number macro */ -static inline void GPIO_ClearPinsOutput(GPIO_Type *base, uint32_t port, uint32_t mask) +static inline void GPIO_PortClear(GPIO_Type *base, uint32_t port, uint32_t mask) { base->CLR[port] = mask; } @@ -179,10 +169,11 @@ static inline void GPIO_ClearPinsOutput(GPIO_Type *base, uint32_t port, uint32_t * @param port GPIO port number * @param mask GPIO pin number macro */ -static inline void GPIO_TogglePinsOutput(GPIO_Type *base, uint32_t port, uint32_t mask) +static inline void GPIO_PortToggle(GPIO_Type *base, uint32_t port, uint32_t mask) { base->NOT[port] = mask; } + /*@}*/ /*! @@ -191,7 +182,7 @@ static inline void GPIO_TogglePinsOutput(GPIO_Type *base, uint32_t port, uint32_ * @param base GPIO peripheral base pointer(Typically GPIO) * @param port GPIO port number */ -static inline uint32_t GPIO_ReadPinsInput(GPIO_Type *base, uint32_t port) +static inline uint32_t GPIO_PortRead(GPIO_Type *base, uint32_t port) { return (uint32_t)base->PIN[port]; } @@ -207,7 +198,7 @@ static inline uint32_t GPIO_ReadPinsInput(GPIO_Type *base, uint32_t port) * @param port GPIO port number * @param mask GPIO pin number macro */ -static inline void GPIO_SetPortMask(GPIO_Type *base, uint32_t port, uint32_t mask) +static inline void GPIO_PortMaskedSet(GPIO_Type *base, uint32_t port, uint32_t mask) { base->MASK[port] = mask; } @@ -219,7 +210,7 @@ static inline void GPIO_SetPortMask(GPIO_Type *base, uint32_t port, uint32_t mas * @param port GPIO port number * @param output GPIO port output value. */ -static inline void GPIO_WriteMPort(GPIO_Type *base, uint32_t port, uint32_t output) +static inline void GPIO_PortMaskedWrite(GPIO_Type *base, uint32_t port, uint32_t output) { base->MPIN[port] = output; } @@ -232,7 +223,7 @@ static inline void GPIO_WriteMPort(GPIO_Type *base, uint32_t port, uint32_t outp * @param port GPIO port number * @retval masked GPIO port value */ -static inline uint32_t GPIO_ReadMPort(GPIO_Type *base, uint32_t port) +static inline uint32_t GPIO_PortMaskedRead(GPIO_Type *base, uint32_t port) { return (uint32_t)base->MPIN[port]; } diff --git a/ext/hal/nxp/mcux/drivers/lpc/fsl_i2c.c b/ext/hal/nxp/mcux/drivers/lpc/fsl_i2c.c index ad519e41080..d11fa6c98ca 100644 --- a/ext/hal/nxp/mcux/drivers/lpc/fsl_i2c.c +++ b/ext/hal/nxp/mcux/drivers/lpc/fsl_i2c.c @@ -1,31 +1,9 @@ /* * Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP + * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * SPDX-License-Identifier: BSD-3-Clause */ #include "fsl_i2c.h" @@ -37,6 +15,11 @@ * Definitions ******************************************************************************/ +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.flexcomm_i2c" +#endif + /*! @brief Common sets of flags used by the driver. */ enum _i2c_flag_constants { @@ -85,6 +68,15 @@ static const IRQn_Type s_i2cIRQ[] = I2C_IRQS; * @param base The I2C peripheral base address. * @return I2C instance number starting from 0. */ +/*! + * brief Returns an instance number given a base address. + * + * If an invalid base address is passed, debug builds will assert. Release builds will just return + * instance number 0. + * + * param base The I2C peripheral base address. + * return I2C instance number starting from 0. + */ uint32_t I2C_GetInstance(I2C_Type *base) { int i; @@ -99,13 +91,44 @@ uint32_t I2C_GetInstance(I2C_Type *base) return 0; } +/*! + * brief Provides a default configuration for the I2C master peripheral. + * + * This function provides the following default configuration for the I2C master peripheral: + * code + * masterConfig->enableMaster = true; + * masterConfig->baudRate_Bps = 100000U; + * masterConfig->enableTimeout = false; + * endcode + * + * After calling this function, you can override any settings in order to customize the configuration, + * prior to initializing the master driver with I2C_MasterInit(). + * + * param[out] masterConfig User provided configuration structure for default values. Refer to #i2c_master_config_t. + */ void I2C_MasterGetDefaultConfig(i2c_master_config_t *masterConfig) { + /* Initializes the configure structure to zero. */ + memset(masterConfig, 0, sizeof(*masterConfig)); + masterConfig->enableMaster = true; masterConfig->baudRate_Bps = 100000U; masterConfig->enableTimeout = false; } +/*! + * brief Initializes the I2C master peripheral. + * + * This function enables the peripheral clock and initializes the I2C master peripheral as described by the user + * provided configuration. A software reset is performed prior to configuration. + * + * param base The I2C peripheral base address. + * param masterConfig User provided peripheral configuration. Use I2C_MasterGetDefaultConfig() to get a set of + * defaults + * that you can override. + * param srcClock_Hz Frequency in Hertz of the I2C functional clock. Used to calculate the baud rate divisors, + * filter widths, and timeout periods. + */ void I2C_MasterInit(I2C_Type *base, const i2c_master_config_t *masterConfig, uint32_t srcClock_Hz) { FLEXCOMM_Init(base, FLEXCOMM_PERIPH_I2C); @@ -113,11 +136,29 @@ void I2C_MasterInit(I2C_Type *base, const i2c_master_config_t *masterConfig, uin I2C_MasterSetBaudRate(base, masterConfig->baudRate_Bps, srcClock_Hz); } +/*! +* brief Deinitializes the I2C master peripheral. +* + * This function disables the I2C master peripheral and gates the clock. It also performs a software + * reset to restore the peripheral to reset conditions. + * + * param base The I2C peripheral base address. + */ void I2C_MasterDeinit(I2C_Type *base) { I2C_MasterEnable(base, false); } +/*! + * brief Sets the I2C bus frequency for master transactions. + * + * The I2C master is automatically disabled and re-enabled as necessary to configure the baud + * rate. Do not call this function during a transfer, or the transfer is aborted. + * + * param base The I2C peripheral base address. + * param srcClock_Hz I2C functional clock frequency in Hertz. + * param baudRate_Bps Requested bus frequency in bits per second. + */ void I2C_MasterSetBaudRate(I2C_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz) { uint32_t scl, divider; @@ -159,10 +200,23 @@ static uint32_t I2C_PendingStatusWait(I2C_Type *base) { uint32_t status; +#if I2C_WAIT_TIMEOUT + uint32_t waitTimes = I2C_WAIT_TIMEOUT; +#endif + do { status = I2C_GetStatusFlags(base); +#if I2C_WAIT_TIMEOUT + } while (((status & I2C_STAT_MSTPENDING_MASK) == 0) && (--waitTimes)); + + if (waitTimes == 0) + { + return kStatus_I2C_Timeout; + } +#else } while ((status & I2C_STAT_MSTPENDING_MASK) == 0); +#endif /* Clear controller state. */ I2C_MasterClearStatusFlags(base, I2C_STAT_MSTARBLOSS_MASK | I2C_STAT_MSTSTSTPERR_MASK); @@ -170,9 +224,26 @@ static uint32_t I2C_PendingStatusWait(I2C_Type *base) return status; } +/*! + * brief Sends a START on the I2C bus. + * + * This function is used to initiate a new master mode transfer by sending the START signal. + * The slave address is sent following the I2C START signal. + * + * param base I2C peripheral base pointer + * param address 7-bit slave device address. + * param direction Master transfer directions(transmit/receive). + * retval kStatus_Success Successfully send the start signal. + * retval kStatus_I2C_Busy Current bus is busy. + */ status_t I2C_MasterStart(I2C_Type *base, uint8_t address, i2c_direction_t direction) { - I2C_PendingStatusWait(base); + status_t result; + result = I2C_PendingStatusWait(base); + if (result == kStatus_I2C_Timeout) + { + return kStatus_I2C_Timeout; + } /* Write Address and RW bit to data register */ base->MSTDAT = ((uint32_t)address << 1) | ((uint32_t)direction & 1u); @@ -182,14 +253,42 @@ status_t I2C_MasterStart(I2C_Type *base, uint8_t address, i2c_direction_t direct return kStatus_Success; } +/*! + * brief Sends a STOP signal on the I2C bus. + * + * retval kStatus_Success Successfully send the stop signal. + * retval kStatus_I2C_Timeout Send stop signal failed, timeout. + */ status_t I2C_MasterStop(I2C_Type *base) { - I2C_PendingStatusWait(base); + status_t result; + result = I2C_PendingStatusWait(base); + if (result == kStatus_I2C_Timeout) + { + return kStatus_I2C_Timeout; + } base->MSTCTL = I2C_MSTCTL_MSTSTOP_MASK; return kStatus_Success; } +/*! + * brief Performs a polling send transfer on the I2C bus. + * + * Sends up to a txSize number of bytes to the previously addressed slave device. The slave may + * reply with a NAK to any byte in order to terminate the transfer early. If this happens, this + * function returns #kStatus_I2C_Nak. + * + * param base The I2C peripheral base address. + * param txBuff The pointer to the data to be transferred. + * param txSize The length in bytes of the data to be transferred. + * param flags Transfer control flag to control special behavior like suppressing start or stop, for normal transfers + * use kI2C_TransferDefaultFlag + * retval kStatus_Success Data was sent successfully. + * retval #kStatus_I2C_Busy Another master is currently utilizing the bus. + * retval #kStatus_I2C_Nak The slave device sent a NAK in response to a byte. + * retval #kStatus_I2C_ArbitrationLost Arbitration lost error. + */ status_t I2C_MasterWriteBlocking(I2C_Type *base, const void *txBuff, size_t txSize, uint32_t flags) { uint32_t status; @@ -205,6 +304,13 @@ status_t I2C_MasterWriteBlocking(I2C_Type *base, const void *txBuff, size_t txSi { status = I2C_PendingStatusWait(base); +#if I2C_WAIT_TIMEOUT + if (status == kStatus_I2C_Timeout) + { + return kStatus_I2C_Timeout; + } +#endif + if (status & I2C_STAT_MSTARBLOSS_MASK) { return kStatus_I2C_ArbitrationLost; @@ -245,6 +351,13 @@ status_t I2C_MasterWriteBlocking(I2C_Type *base, const void *txBuff, size_t txSi status = I2C_PendingStatusWait(base); +#if I2C_WAIT_TIMEOUT + if (status == kStatus_I2C_Timeout) + { + return kStatus_I2C_Timeout; + } +#endif + if ((status & (I2C_STAT_MSTARBLOSS_MASK | I2C_STAT_MSTSTSTPERR_MASK)) == 0) { if (!(flags & kI2C_TransferNoStopFlag)) @@ -252,6 +365,10 @@ status_t I2C_MasterWriteBlocking(I2C_Type *base, const void *txBuff, size_t txSi /* Initiate stop */ base->MSTCTL = I2C_MSTCTL_MSTSTOP_MASK; status = I2C_PendingStatusWait(base); + if (status == kStatus_I2C_Timeout) + { + return kStatus_I2C_Timeout; + } } } @@ -268,6 +385,19 @@ status_t I2C_MasterWriteBlocking(I2C_Type *base, const void *txBuff, size_t txSi return kStatus_Success; } +/*! + * brief Performs a polling receive transfer on the I2C bus. + * + * param base The I2C peripheral base address. + * param rxBuff The pointer to the data to be transferred. + * param rxSize The length in bytes of the data to be transferred. + * param flags Transfer control flag to control special behavior like suppressing start or stop, for normal transfers + * use kI2C_TransferDefaultFlag + * retval kStatus_Success Data was received successfully. + * retval #kStatus_I2C_Busy Another master is currently utilizing the bus. + * retval #kStatus_I2C_Nak The slave device sent a NAK in response to a byte. + * retval #kStatus_I2C_ArbitrationLost Arbitration lost error. + */ status_t I2C_MasterReadBlocking(I2C_Type *base, void *rxBuff, size_t rxSize, uint32_t flags) { uint32_t status = 0; @@ -283,6 +413,13 @@ status_t I2C_MasterReadBlocking(I2C_Type *base, void *rxBuff, size_t rxSize, uin { status = I2C_PendingStatusWait(base); +#if I2C_WAIT_TIMEOUT + if (status == kStatus_I2C_Timeout) + { + return kStatus_I2C_Timeout; + } +#endif + if (status & (I2C_STAT_MSTARBLOSS_MASK | I2C_STAT_MSTSTSTPERR_MASK)) { break; @@ -305,6 +442,13 @@ status_t I2C_MasterReadBlocking(I2C_Type *base, void *rxBuff, size_t rxSize, uin /* initiate NAK and stop */ base->MSTCTL = I2C_MSTCTL_MSTSTOP_MASK; status = I2C_PendingStatusWait(base); + +#if I2C_WAIT_TIMEOUT + if (status == kStatus_I2C_Timeout) + { + return kStatus_I2C_Timeout; + } +#endif } } break; @@ -340,6 +484,20 @@ status_t I2C_MasterReadBlocking(I2C_Type *base, void *rxBuff, size_t rxSize, uin return kStatus_Success; } +/*! + * brief Performs a master polling transfer on the I2C bus. + * + * note The API does not return until the transfer succeeds or fails due + * to arbitration lost or receiving a NAK. + * + * param base I2C peripheral base address. + * param xfer Pointer to the transfer structure. + * retval kStatus_Success Successfully complete the data transmission. + * retval kStatus_I2C_Busy Previous transmission still not finished. + * retval kStatus_I2C_Timeout Transfer error, wait signal timeout. + * retval kStatus_I2C_ArbitrationLost Transfer error, arbitration lost. + * retval kStataus_I2C_Nak Transfer error, receive NAK during transfer. + */ status_t I2C_MasterTransferBlocking(I2C_Type *base, i2c_master_transfer_t *xfer) { status_t result = kStatus_Success; @@ -407,6 +565,18 @@ status_t I2C_MasterTransferBlocking(I2C_Type *base, i2c_master_transfer_t *xfer) return result; } +/*! + * brief Creates a new handle for the I2C master non-blocking APIs. + * + * The creation of a handle is for use with the non-blocking APIs. Once a handle + * is created, there is not a corresponding destroy handle. If the user wants to + * terminate a transfer, the I2C_MasterTransferAbort() API shall be called. + * + * param base The I2C peripheral base address. + * param[out] handle Pointer to the I2C master driver handle. + * param callback User provided pointer to the asynchronous callback function. + * param userData User provided pointer to the application callback data. + */ void I2C_MasterTransferCreateHandle(I2C_Type *base, i2c_master_handle_t *handle, i2c_master_transfer_callback_t callback, @@ -426,13 +596,23 @@ void I2C_MasterTransferCreateHandle(I2C_Type *base, handle->completionCallback = callback; handle->userData = userData; - FLEXCOMM_SetIRQHandler(base, (flexcomm_irq_handler_t)(uintptr_t)I2C_MasterTransferHandleIRQ, handle); + FLEXCOMM_SetIRQHandler(base, (flexcomm_irq_handler_t)I2C_MasterTransferHandleIRQ, handle); /* Clear internal IRQ enables and enable NVIC IRQ. */ I2C_DisableInterrupts(base, kI2C_MasterIrqFlags); EnableIRQ(s_i2cIRQ[instance]); } +/*! + * brief Performs a non-blocking transaction on the I2C bus. + * + * param base The I2C peripheral base address. + * param handle Pointer to the I2C master driver handle. + * param xfer The pointer to the transfer descriptor. + * retval kStatus_Success The transaction was started successfully. + * retval #kStatus_I2C_Busy Either another master is currently utilizing the bus, or a non-blocking + * transaction is already in progress. + */ status_t I2C_MasterTransferNonBlocking(I2C_Type *base, i2c_master_handle_t *handle, i2c_master_transfer_t *xfer) { status_t result; @@ -462,6 +642,14 @@ status_t I2C_MasterTransferNonBlocking(I2C_Type *base, i2c_master_handle_t *hand return result; } +/*! + * brief Returns number of bytes transferred so far. + * param base The I2C peripheral base address. + * param handle Pointer to the I2C master driver handle. + * param[out] count Number of bytes transferred so far by the non-blocking transaction. + * retval kStatus_Success + * retval #kStatus_I2C_Busy + */ status_t I2C_MasterTransferGetCount(I2C_Type *base, i2c_master_handle_t *handle, size_t *count) { assert(handle); @@ -483,7 +671,18 @@ status_t I2C_MasterTransferGetCount(I2C_Type *base, i2c_master_handle_t *handle, return kStatus_Success; } -void I2C_MasterTransferAbort(I2C_Type *base, i2c_master_handle_t *handle) +/*! + * brief Terminates a non-blocking I2C master transmission early. + * + * note It is not safe to call this function from an IRQ handler that has a higher priority than the + * I2C peripheral's IRQ priority. + * + * param base The I2C peripheral base address. + * param handle Pointer to the I2C master driver handle. + * retval kStatus_Success A transaction was successfully aborted. + * retval #kStatus_I2C_Timeout Timeout during polling for flags. + */ +status_t I2C_MasterTransferAbort(I2C_Type *base, i2c_master_handle_t *handle) { uint32_t status; uint32_t master_state; @@ -496,6 +695,15 @@ void I2C_MasterTransferAbort(I2C_Type *base, i2c_master_handle_t *handle) /* Wait until module is ready */ status = I2C_PendingStatusWait(base); +#if I2C_WAIT_TIMEOUT + if (status == kStatus_I2C_Timeout) + { + /* Reset handle to idle state. */ + handle->state = kIdleState; + return kStatus_I2C_Timeout; + } +#endif + /* Get the state of the I2C module */ master_state = (status & I2C_STAT_MSTSTATE_MASK) >> I2C_STAT_MSTSTATE_SHIFT; @@ -505,12 +713,17 @@ void I2C_MasterTransferAbort(I2C_Type *base, i2c_master_handle_t *handle) base->MSTCTL = I2C_MSTCTL_MSTSTOP_MASK; /* Wait until the STOP is completed */ - I2C_PendingStatusWait(base); + status = I2C_PendingStatusWait(base); + if (status == kStatus_I2C_Timeout) + { + return kStatus_I2C_Timeout; + } } /* Reset handle. */ handle->state = kIdleState; } + return kStatus_Success; } /*! @@ -592,6 +805,8 @@ static status_t I2C_RunTransferStateMachine(I2C_Type *base, i2c_master_handle_t status_t err; transfer = &(handle->transfer); + bool ignoreNak = ((handle->state == kStopState) && (handle->remainingBytes == 0U)) || + ((handle->state == kWaitForCompletionState) && (handle->remainingBytes == 0U)); *isDone = false; @@ -617,7 +832,7 @@ static status_t I2C_RunTransferStateMachine(I2C_Type *base, i2c_master_handle_t /* Get the state of the I2C module */ master_state = (status & I2C_STAT_MSTSTATE_MASK) >> I2C_STAT_MSTSTATE_SHIFT; - if ((master_state == I2C_STAT_MSTCODE_NACKADR) || (master_state == I2C_STAT_MSTCODE_NACKDAT)) + if (((master_state == I2C_STAT_MSTCODE_NACKADR) || (master_state == I2C_STAT_MSTCODE_NACKDAT)) && (ignoreNak != true)) { /* Slave NACKed last byte, issue stop and return error */ base->MSTCTL = I2C_MSTCTL_MSTSTOP_MASK; @@ -738,6 +953,13 @@ static status_t I2C_RunTransferStateMachine(I2C_Type *base, i2c_master_handle_t return err; } +/*! + * brief Reusable routine to handle master interrupts. + * note This function does not need to be called unless you are reimplementing the + * nonblocking API's interrupt handler routines to add special functionality. + * param base The I2C peripheral base address. + * param handle Pointer to the I2C master driver handle. + */ void I2C_MasterTransferHandleIRQ(I2C_Type *base, i2c_master_handle_t *handle) { bool isDone; @@ -753,6 +975,9 @@ void I2C_MasterTransferHandleIRQ(I2C_Type *base, i2c_master_handle_t *handle) if (isDone || (result != kStatus_Success)) { + /* Restore handle to idle state. */ + handle->state = kIdleState; + /* Disable internal IRQ enables. */ I2C_DisableInterrupts(base, kI2C_MasterIrqFlags); @@ -842,10 +1067,22 @@ static uint32_t I2C_SlavePollPending(I2C_Type *base) { uint32_t stat; +#if I2C_WAIT_TIMEOUT + uint32_t waitTimes = I2C_WAIT_TIMEOUT; +#endif do { stat = base->STAT; +#if I2C_WAIT_TIMEOUT + } while ((0u == (stat & I2C_STAT_SLVPENDING_MASK)) && (--waitTimes)); + + if (waitTimes == 0u) + { + return kStatus_I2C_Timeout; + } +#else } while (0u == (stat & I2C_STAT_SLVPENDING_MASK)); +#endif return stat; } @@ -1011,18 +1248,77 @@ static status_t I2C_SlaveTransferNonBlockingInternal(I2C_Type *base, return status; } +/*! + * brief Starts accepting master read from slave requests. + * + * The function can be called in response to #kI2C_SlaveTransmitEvent callback to start a new slave Tx transfer + * from within the transfer callback. + * + * The set of events received by the callback is customizable. To do so, set the a eventMask parameter to + * the OR'd combination of #i2c_slave_transfer_event_t enumerators for the events you wish to receive. + * The #kI2C_SlaveTransmitEvent and #kI2C_SlaveReceiveEvent events are always enabled and do not need + * to be included in the mask. Alternatively, you can pass 0 to get a default set of only the transmit and + * receive events that are always enabled. In addition, the #kI2C_SlaveAllEvents constant is provided as + * a convenient way to enable all events. + * + * param base The I2C peripheral base address. + * param transfer Pointer to #i2c_slave_transfer_t structure. + * param txData Pointer to data to send to master. + * param txSize Size of txData in bytes. + * param eventMask Bit mask formed by OR'ing together #i2c_slave_transfer_event_t enumerators to specify + * which events to send to the callback. Other accepted values are 0 to get a default set of + * only the transmit and receive events, and #kI2C_SlaveAllEvents to enable all events. + * + * retval kStatus_Success Slave transfers were successfully started. + * retval #kStatus_I2C_Busy Slave transfers have already been started on this handle. + */ status_t I2C_SlaveSetSendBuffer( I2C_Type *base, volatile i2c_slave_transfer_t *transfer, const void *txData, size_t txSize, uint32_t eventMask) { return I2C_SlaveTransferNonBlockingInternal(base, transfer->handle, txData, txSize, NULL, 0u, eventMask); } +/*! + * brief Starts accepting master write to slave requests. + * + * The function can be called in response to #kI2C_SlaveReceiveEvent callback to start a new slave Rx transfer + * from within the transfer callback. + * + * The set of events received by the callback is customizable. To do so, set the a eventMask parameter to + * the OR'd combination of #i2c_slave_transfer_event_t enumerators for the events you wish to receive. + * The #kI2C_SlaveTransmitEvent and #kI2C_SlaveReceiveEvent events are always enabled and do not need + * to be included in the mask. Alternatively, you can pass 0 to get a default set of only the transmit and + * receive events that are always enabled. In addition, the #kI2C_SlaveAllEvents constant is provided as + * a convenient way to enable all events. + * + * param base The I2C peripheral base address. + * param transfer Pointer to #i2c_slave_transfer_t structure. + * param rxData Pointer to data to store data from master. + * param rxSize Size of rxData in bytes. + * param eventMask Bit mask formed by OR'ing together #i2c_slave_transfer_event_t enumerators to specify + * which events to send to the callback. Other accepted values are 0 to get a default set of + * only the transmit and receive events, and #kI2C_SlaveAllEvents to enable all events. + * + * retval kStatus_Success Slave transfers were successfully started. + * retval #kStatus_I2C_Busy Slave transfers have already been started on this handle. + */ status_t I2C_SlaveSetReceiveBuffer( I2C_Type *base, volatile i2c_slave_transfer_t *transfer, void *rxData, size_t rxSize, uint32_t eventMask) { return I2C_SlaveTransferNonBlockingInternal(base, transfer->handle, NULL, 0u, rxData, rxSize, eventMask); } +/*! + * brief Configures Slave Address n register. + * + * This function writes new value to Slave Address register. + * + * param base The I2C peripheral base address. + * param addressRegister The module supports multiple address registers. The parameter determines which one shall be + * changed. + * param address The slave address to be stored to the address register for matching. + * param addressDisable Disable matching of the specified address register. + */ void I2C_SlaveSetAddress(I2C_Type *base, i2c_slave_address_register_t addressRegister, uint8_t address, @@ -1031,6 +1327,27 @@ void I2C_SlaveSetAddress(I2C_Type *base, base->SLVADR[addressRegister] = I2C_SLVADR_SLVADR(address) | I2C_SLVADR_SADISABLE(addressDisable); } +/*! + * brief Provides a default configuration for the I2C slave peripheral. + * + * This function provides the following default configuration for the I2C slave peripheral: + * code + * slaveConfig->enableSlave = true; + * slaveConfig->address0.disable = false; + * slaveConfig->address0.address = 0u; + * slaveConfig->address1.disable = true; + * slaveConfig->address2.disable = true; + * slaveConfig->address3.disable = true; + * slaveConfig->busSpeed = kI2C_SlaveStandardMode; + * endcode + * + * After calling this function, override any settings to customize the configuration, + * prior to initializing the master driver with I2C_SlaveInit(). Be sure to override at least the a + * address0.address member of the configuration structure with the desired slave address. + * + * param[out] slaveConfig User provided configuration structure that is set to default values. Refer to + * #i2c_slave_config_t. + */ void I2C_SlaveGetDefaultConfig(i2c_slave_config_t *slaveConfig) { assert(slaveConfig); @@ -1046,6 +1363,19 @@ void I2C_SlaveGetDefaultConfig(i2c_slave_config_t *slaveConfig) *slaveConfig = mySlaveConfig; } +/*! + * brief Initializes the I2C slave peripheral. + * + * This function enables the peripheral clock and initializes the I2C slave peripheral as described by the user + * provided configuration. + * + * param base The I2C peripheral base address. + * param slaveConfig User provided peripheral configuration. Use I2C_SlaveGetDefaultConfig() to get a set of defaults + * that you can override. + * param srcClock_Hz Frequency in Hertz of the I2C functional clock. Used to calculate CLKDIV value to provide + * enough + * data setup time for master when slave stretches the clock. + */ status_t I2C_SlaveInit(I2C_Type *base, const i2c_slave_config_t *slaveConfig, uint32_t srcClock_Hz) { status_t status; @@ -1082,11 +1412,30 @@ status_t I2C_SlaveInit(I2C_Type *base, const i2c_slave_config_t *slaveConfig, ui return status; } +/*! +* brief Deinitializes the I2C slave peripheral. +* + * This function disables the I2C slave peripheral and gates the clock. It also performs a software + * reset to restore the peripheral to reset conditions. + * + * param base The I2C peripheral base address. + */ void I2C_SlaveDeinit(I2C_Type *base) { I2C_SlaveEnable(base, false); } +/*! + * brief Performs a polling send transfer on the I2C bus. + * + * The function executes blocking address phase and blocking data phase. + * + * param base The I2C peripheral base address. + * param txBuff The pointer to the data to be transferred. + * param txSize The length in bytes of the data to be transferred. + * return kStatus_Success Data has been sent. + * return kStatus_Fail Unexpected slave state (master data write while master read from slave is expected). + */ status_t I2C_SlaveWriteBlocking(I2C_Type *base, const uint8_t *txBuff, size_t txSize) { const uint8_t *buf = txBuff; @@ -1099,6 +1448,10 @@ status_t I2C_SlaveWriteBlocking(I2C_Type *base, const uint8_t *txBuff, size_t tx /* wait for SLVPENDING */ stat = I2C_SlavePollPending(base); + if (stat == kStatus_I2C_Timeout) + { + return kStatus_I2C_Timeout; + } /* Get slave machine state */ slaveAddress = (((stat & I2C_STAT_SLVSTATE_MASK) >> I2C_STAT_SLVSTATE_SHIFT) == I2C_STAT_SLVST_ADDR); @@ -1118,6 +1471,10 @@ status_t I2C_SlaveWriteBlocking(I2C_Type *base, const uint8_t *txBuff, size_t tx /* wait for SLVPENDING */ stat = I2C_SlavePollPending(base); + if (stat == kStatus_I2C_Timeout) + { + return kStatus_I2C_Timeout; + } } /* send bytes up to txSize */ @@ -1145,12 +1502,27 @@ status_t I2C_SlaveWriteBlocking(I2C_Type *base, const uint8_t *txBuff, size_t tx { /* wait for SLVPENDING */ stat = I2C_SlavePollPending(base); + if (stat == kStatus_I2C_Timeout) + { + return kStatus_I2C_Timeout; + } } } return kStatus_Success; } +/*! + * brief Performs a polling receive transfer on the I2C bus. + * + * The function executes blocking address phase and blocking data phase. + * + * param base The I2C peripheral base address. + * param rxBuff The pointer to the data to be transferred. + * param rxSize The length in bytes of the data to be transferred. + * return kStatus_Success Data has been received. + * return kStatus_Fail Unexpected slave state (master data read while master write to slave is expected). + */ status_t I2C_SlaveReadBlocking(I2C_Type *base, uint8_t *rxBuff, size_t rxSize) { uint8_t *buf = rxBuff; @@ -1163,6 +1535,10 @@ status_t I2C_SlaveReadBlocking(I2C_Type *base, uint8_t *rxBuff, size_t rxSize) /* wait for SLVPENDING */ stat = I2C_SlavePollPending(base); + if (stat == kStatus_I2C_Timeout) + { + return kStatus_I2C_Timeout; + } /* Get slave machine state */ slaveAddress = (((stat & I2C_STAT_SLVSTATE_MASK) >> I2C_STAT_SLVSTATE_SHIFT) == I2C_STAT_SLVST_ADDR); @@ -1182,6 +1558,10 @@ status_t I2C_SlaveReadBlocking(I2C_Type *base, uint8_t *rxBuff, size_t rxSize) /* wait for SLVPENDING */ stat = I2C_SlavePollPending(base); + if (stat == kStatus_I2C_Timeout) + { + return kStatus_I2C_Timeout; + } } /* receive bytes up to rxSize */ @@ -1209,12 +1589,28 @@ status_t I2C_SlaveReadBlocking(I2C_Type *base, uint8_t *rxBuff, size_t rxSize) { /* wait for SLVPENDING */ stat = I2C_SlavePollPending(base); + if (stat == kStatus_I2C_Timeout) + { + return kStatus_I2C_Timeout; + } } } return kStatus_Success; } +/*! + * brief Creates a new handle for the I2C slave non-blocking APIs. + * + * The creation of a handle is for use with the non-blocking APIs. Once a handle + * is created, there is not a corresponding destroy handle. If the user wants to + * terminate a transfer, the I2C_SlaveTransferAbort() API shall be called. + * + * param base The I2C peripheral base address. + * param[out] handle Pointer to the I2C slave driver handle. + * param callback User provided pointer to the asynchronous callback function. + * param userData User provided pointer to the application callback data. + */ void I2C_SlaveTransferCreateHandle(I2C_Type *base, i2c_slave_handle_t *handle, i2c_slave_transfer_callback_t callback, @@ -1240,18 +1636,54 @@ void I2C_SlaveTransferCreateHandle(I2C_Type *base, /* store pointer to handle into transfer struct */ handle->transfer.handle = handle; - FLEXCOMM_SetIRQHandler(base, (flexcomm_irq_handler_t)(uintptr_t)I2C_SlaveTransferHandleIRQ, handle); + FLEXCOMM_SetIRQHandler(base, (flexcomm_irq_handler_t)I2C_SlaveTransferHandleIRQ, handle); /* Clear internal IRQ enables and enable NVIC IRQ. */ I2C_DisableInterrupts(base, kI2C_SlaveIrqFlags); EnableIRQ(s_i2cIRQ[instance]); } +/*! + * brief Starts accepting slave transfers. + * + * Call this API after calling I2C_SlaveInit() and I2C_SlaveTransferCreateHandle() to start processing + * transactions driven by an I2C master. The slave monitors the I2C bus and pass events to the + * callback that was passed into the call to I2C_SlaveTransferCreateHandle(). The callback is always invoked + * from the interrupt context. + * + * If no slave Tx transfer is busy, a master read from slave request invokes #kI2C_SlaveTransmitEvent callback. + * If no slave Rx transfer is busy, a master write to slave request invokes #kI2C_SlaveReceiveEvent callback. + * + * The set of events received by the callback is customizable. To do so, set the a eventMask parameter to + * the OR'd combination of #i2c_slave_transfer_event_t enumerators for the events you wish to receive. + * The #kI2C_SlaveTransmitEvent and #kI2C_SlaveReceiveEvent events are always enabled and do not need + * to be included in the mask. Alternatively, you can pass 0 to get a default set of only the transmit and + * receive events that are always enabled. In addition, the #kI2C_SlaveAllEvents constant is provided as + * a convenient way to enable all events. + * + * param base The I2C peripheral base address. + * param handle Pointer to i2c_slave_handle_t structure which stores the transfer state. + * param eventMask Bit mask formed by OR'ing together #i2c_slave_transfer_event_t enumerators to specify + * which events to send to the callback. Other accepted values are 0 to get a default set of + * only the transmit and receive events, and #kI2C_SlaveAllEvents to enable all events. + * + * retval kStatus_Success Slave transfers were successfully started. + * retval #kStatus_I2C_Busy Slave transfers have already been started on this handle. + */ status_t I2C_SlaveTransferNonBlocking(I2C_Type *base, i2c_slave_handle_t *handle, uint32_t eventMask) { return I2C_SlaveTransferNonBlockingInternal(base, handle, NULL, 0u, NULL, 0u, eventMask); } +/*! + * brief Gets the slave transfer remaining bytes during a interrupt non-blocking transfer. + * + * param base I2C base pointer. + * param handle pointer to i2c_slave_handle_t structure. + * param count Number of bytes transferred so far by the non-blocking transaction. + * retval kStatus_InvalidArgument count is Invalid. + * retval kStatus_Success Successfully return the count. + */ status_t I2C_SlaveTransferGetCount(I2C_Type *base, i2c_slave_handle_t *handle, size_t *count) { assert(handle); @@ -1274,6 +1706,14 @@ status_t I2C_SlaveTransferGetCount(I2C_Type *base, i2c_slave_handle_t *handle, s return kStatus_Success; } +/*! + * brief Aborts the slave non-blocking transfers. + * note This API could be called at any time to stop slave for handling the bus events. + * param base The I2C peripheral base address. + * param handle Pointer to i2c_slave_handle_t structure which stores the transfer state. + * retval kStatus_Success + * retval #kStatus_I2C_Idle + */ void I2C_SlaveTransferAbort(I2C_Type *base, i2c_slave_handle_t *handle) { /* Disable I2C IRQ sources while we configure stuff. */ @@ -1287,6 +1727,13 @@ void I2C_SlaveTransferAbort(I2C_Type *base, i2c_slave_handle_t *handle) handle->transfer.rxSize = 0; } +/*! + * brief Reusable routine to handle slave interrupts. + * note This function does not need to be called unless you are reimplementing the + * non blocking API's interrupt handler routines to add special functionality. + * param base The I2C peripheral base address. + * param handle Pointer to i2c_slave_handle_t structure which stores the transfer state. + */ void I2C_SlaveTransferHandleIRQ(I2C_Type *base, i2c_slave_handle_t *handle) { uint32_t i2cStatus = base->STAT; @@ -1327,13 +1774,12 @@ void I2C_SlaveTransferHandleIRQ(I2C_Type *base, i2c_slave_handle_t *handle) /* receive a byte */ if ((handle->transfer.rxData) && (handle->transfer.rxSize)) { + /* continue transaction */ + base->SLVCTL = I2C_SLVCTL_SLVCONTINUE_MASK; *(handle->transfer.rxData) = (uint8_t)base->SLVDAT; (handle->transfer.rxSize)--; (handle->transfer.rxData)++; (handle->transfer.transferredCount)++; - - /* continue transaction */ - base->SLVCTL = I2C_SLVCTL_SLVCONTINUE_MASK; } /* is this last transaction for this transfer? allow next transaction */ @@ -1367,12 +1813,11 @@ void I2C_SlaveTransferHandleIRQ(I2C_Type *base, i2c_slave_handle_t *handle) if ((handle->transfer.txData) && (handle->transfer.txSize)) { base->SLVDAT = *(handle->transfer.txData); + /* continue transaction */ + base->SLVCTL = I2C_SLVCTL_SLVCONTINUE_MASK; (handle->transfer.txSize)--; (handle->transfer.txData)++; (handle->transfer.transferredCount)++; - - /* continue transaction */ - base->SLVCTL = I2C_SLVCTL_SLVCONTINUE_MASK; } /* is this last transaction for this transfer? allow next transaction */ diff --git a/ext/hal/nxp/mcux/drivers/lpc/fsl_i2c.h b/ext/hal/nxp/mcux/drivers/lpc/fsl_i2c.h index bda2d815f5c..5470198aabd 100644 --- a/ext/hal/nxp/mcux/drivers/lpc/fsl_i2c.h +++ b/ext/hal/nxp/mcux/drivers/lpc/fsl_i2c.h @@ -1,31 +1,9 @@ /* * Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause */ #ifndef _FSL_I2C_H_ #define _FSL_I2C_H_ @@ -49,10 +27,15 @@ /*! @name Driver version */ /*@{*/ -/*! @brief I2C driver version 1.0.0. */ -#define NXP_I2C_DRIVER_VERSION (MAKE_VERSION(1, 0, 0)) +/*! @brief I2C driver version 2.0.3. */ +#define FSL_I2C_DRIVER_VERSION (MAKE_VERSION(2, 0, 3)) /*@}*/ +/*! @brief Timeout times for waiting flag. */ +#ifndef I2C_WAIT_TIMEOUT +#define I2C_WAIT_TIMEOUT 0U /* Define to zero means keep waiting until the flag is assert/deassert. */ +#endif + /* definitions for MSTCODE bits in I2C Status register STAT */ #define I2C_STAT_MSTCODE_IDLE (0) /*!< Master Idle State Code */ #define I2C_STAT_MSTCODE_RXREADY (1) /*!< Master Receive Ready State Code */ @@ -77,10 +60,12 @@ enum _i2c_status kStatus_I2C_BitError = MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 4), /*!< Transferred bit was not seen on the bus. */ kStatus_I2C_ArbitrationLost = MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 5), /*!< Arbitration lost error. */ kStatus_I2C_NoTransferInProgress = - MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 7), /*!< Attempt to abort a transfer when one is not in progress. */ + MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 6), /*!< Attempt to abort a transfer when one is not in progress. */ kStatus_I2C_DmaRequestFail = MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 7), /*!< DMA request failed. */ kStatus_I2C_StartStopError = MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 8), kStatus_I2C_UnexpectedState = MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 9), + kStatus_I2C_Timeout = MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 10), /*!< Timeout poling status flags. */ + kStatus_I2C_Addr_Nak = MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 11), /*!< NAK received for Address */ }; /*! @} */ @@ -98,8 +83,10 @@ enum _i2c_status enum _i2c_master_flags { kI2C_MasterPendingFlag = I2C_STAT_MSTPENDING_MASK, /*!< The I2C module is waiting for software interaction. */ - kI2C_MasterArbitrationLostFlag = I2C_STAT_MSTARBLOSS_MASK, /*!< The arbitration of the bus was lost. There was collision on the bus */ - kI2C_MasterStartStopErrorFlag = I2C_STAT_MSTSTSTPERR_MASK /*!< There was an error during start or stop phase of the transaction. */ + kI2C_MasterArbitrationLostFlag = + I2C_STAT_MSTARBLOSS_MASK, /*!< The arbitration of the bus was lost. There was collision on the bus */ + kI2C_MasterStartStopErrorFlag = + I2C_STAT_MSTSTSTPERR_MASK /*!< There was an error during start or stop phase of the transaction. */ }; /*! @brief Direction of master and slave transfers. */ @@ -215,19 +202,21 @@ struct _i2c_master_handle * @{ */ - /*! - * @brief I2C slave peripheral flags. - * - * @note These enums are meant to be OR'd together to form a bit mask. - */ +/*! +* @brief I2C slave peripheral flags. +* +* @note These enums are meant to be OR'd together to form a bit mask. +*/ enum _i2c_slave_flags { kI2C_SlavePendingFlag = I2C_STAT_SLVPENDING_MASK, /*!< The I2C module is waiting for software interaction. */ - kI2C_SlaveNotStretching = I2C_STAT_SLVNOTSTR_MASK, /*!< Indicates whether the slave is currently stretching clock (0 = yes, 1 = no). */ + kI2C_SlaveNotStretching = + I2C_STAT_SLVNOTSTR_MASK, /*!< Indicates whether the slave is currently stretching clock (0 = yes, 1 = no). */ kI2C_SlaveSelected = I2C_STAT_SLVSEL_MASK, /*!< Indicates whether the slave is selected by an address match. */ - kI2C_SaveDeselected = I2C_STAT_SLVDESEL_MASK /*!< Indicates that slave was previously deselected (deselect event took place, w1c). */ + kI2C_SaveDeselected = + I2C_STAT_SLVDESEL_MASK /*!< Indicates that slave was previously deselected (deselect event took place, w1c). */ }; - + /*! @brief I2C slave address register. */ typedef enum _i2c_slave_address_register { @@ -430,6 +419,17 @@ void I2C_MasterInit(I2C_Type *base, const i2c_master_config_t *masterConfig, uin */ void I2C_MasterDeinit(I2C_Type *base); +/*! + * @brief Returns an instance number given a base address. + * + * If an invalid base address is passed, debug builds will assert. Release builds will just return + * instance number 0. + * + * @param base The I2C peripheral base address. + * @return I2C instance number starting from 0. + */ +uint32_t I2C_GetInstance(I2C_Type *base); + /*! * @brief Performs a software reset. * @@ -621,7 +621,8 @@ static inline status_t I2C_MasterRepeatedStart(I2C_Type *base, uint8_t address, * @param base The I2C peripheral base address. * @param txBuff The pointer to the data to be transferred. * @param txSize The length in bytes of the data to be transferred. - * @param flags Transfer control flag to control special behavior like suppressing start or stop, for normal transfers use kI2C_TransferDefaultFlag + * @param flags Transfer control flag to control special behavior like suppressing start or stop, for normal transfers + * use kI2C_TransferDefaultFlag * @retval kStatus_Success Data was sent successfully. * @retval #kStatus_I2C_Busy Another master is currently utilizing the bus. * @retval #kStatus_I2C_Nak The slave device sent a NAK in response to a byte. @@ -635,7 +636,8 @@ status_t I2C_MasterWriteBlocking(I2C_Type *base, const void *txBuff, size_t txSi * @param base The I2C peripheral base address. * @param rxBuff The pointer to the data to be transferred. * @param rxSize The length in bytes of the data to be transferred. - * @param flags Transfer control flag to control special behavior like suppressing start or stop, for normal transfers use kI2C_TransferDefaultFlag + * @param flags Transfer control flag to control special behavior like suppressing start or stop, for normal transfers + * use kI2C_TransferDefaultFlag * @retval kStatus_Success Data was received successfully. * @retval #kStatus_I2C_Busy Another master is currently utilizing the bus. * @retval #kStatus_I2C_Nak The slave device sent a NAK in response to a byte. @@ -712,9 +714,9 @@ status_t I2C_MasterTransferGetCount(I2C_Type *base, i2c_master_handle_t *handle, * @param base The I2C peripheral base address. * @param handle Pointer to the I2C master driver handle. * @retval kStatus_Success A transaction was successfully aborted. - * @retval #kStatus_I2C_Idle There is not a non-blocking transaction currently in progress. + * @retval #kStatus_I2C_Timeout Timeout during polling for flags. */ -void I2C_MasterTransferAbort(I2C_Type *base, i2c_master_handle_t *handle); +status_t I2C_MasterTransferAbort(I2C_Type *base, i2c_master_handle_t *handle); /*@}*/ @@ -786,7 +788,8 @@ status_t I2C_SlaveInit(I2C_Type *base, const i2c_slave_config_t *slaveConfig, ui * This function writes new value to Slave Address register. * * @param base The I2C peripheral base address. - * @param addressRegister The module supports multiple address registers. The parameter determines which one shall be changed. + * @param addressRegister The module supports multiple address registers. The parameter determines which one shall be + * changed. * @param address The slave address to be stored to the address register for matching. * @param addressDisable Disable matching of the specified address register. */ diff --git a/ext/hal/nxp/mcux/drivers/lpc/fsl_i2c_dma.c b/ext/hal/nxp/mcux/drivers/lpc/fsl_i2c_dma.c index 17c0f3f5098..14b6025a925 100644 --- a/ext/hal/nxp/mcux/drivers/lpc/fsl_i2c_dma.c +++ b/ext/hal/nxp/mcux/drivers/lpc/fsl_i2c_dma.c @@ -1,31 +1,9 @@ /* * Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP + * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * SPDX-License-Identifier: BSD-3-Clause */ #include "fsl_i2c_dma.h" @@ -35,6 +13,11 @@ * Definitions ******************************************************************************/ +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.flexcomm_i2c_dma" +#endif + /*subaddrBuf, (void *)&base->MSTDAT, sizeof(uint8_t), handle->remainingSubaddr, kDMA_MemoryToPeripheral, NULL); DMA_SubmitTransfer(handle->dmaHandle, &xferConfig); - + DMA_StartTransfer(handle->dmaHandle); handle->remainingSubaddr = 0; if (transfer->dataSize) { @@ -445,6 +420,15 @@ static void I2C_MasterTransferCallbackDMA(dma_handle_t *handle, void *userData) I2C_RunDMATransfer(dmaPrivateHandle->base, dmaPrivateHandle->handle); } +/*! + * brief Init the I2C handle which is used in transcational functions + * + * param base I2C peripheral base address + * param handle pointer to i2c_master_dma_handle_t structure + * param callback pointer to user callback function + * param userData user param passed to the callback function + * param dmaHandle DMA handle pointer + */ void I2C_MasterTransferCreateHandleDMA(I2C_Type *base, i2c_master_dma_handle_t *handle, i2c_master_dma_transfer_callback_t callback, @@ -466,7 +450,7 @@ void I2C_MasterTransferCreateHandleDMA(I2C_Type *base, handle->completionCallback = callback; handle->userData = userData; - FLEXCOMM_SetIRQHandler(base, (flexcomm_irq_handler_t)(uintptr_t)I2C_MasterTransferDMAHandleIRQ, handle); + FLEXCOMM_SetIRQHandler(base, (flexcomm_irq_handler_t)I2C_MasterTransferDMAHandleIRQ, handle); /* Clear internal IRQ enables and enable NVIC IRQ. */ I2C_DisableInterrupts(base, @@ -479,9 +463,21 @@ void I2C_MasterTransferCreateHandleDMA(I2C_Type *base, s_dmaPrivateHandle[instance].base = base; s_dmaPrivateHandle[instance].handle = handle; - DMA_SetCallback(dmaHandle, (dma_callback)(uintptr_t)I2C_MasterTransferCallbackDMA, &s_dmaPrivateHandle[instance]); + DMA_SetCallback(dmaHandle, (dma_callback)I2C_MasterTransferCallbackDMA, &s_dmaPrivateHandle[instance]); } +/*! + * brief Performs a master dma non-blocking transfer on the I2C bus + * + * param base I2C peripheral base address + * param handle pointer to i2c_master_dma_handle_t structure + * param xfer pointer to transfer structure of i2c_master_transfer_t + * retval kStatus_Success Sucessully complete the data transmission. + * retval kStatus_I2C_Busy Previous transmission still not finished. + * retval kStatus_I2C_Timeout Transfer error, wait signal timeout. + * retval kStatus_I2C_ArbitrationLost Transfer error, arbitration lost. + * retval kStataus_I2C_Nak Transfer error, receive Nak during transfer. + */ status_t I2C_MasterTransferDMA(I2C_Type *base, i2c_master_dma_handle_t *handle, i2c_master_transfer_t *xfer) { status_t result; @@ -509,6 +505,13 @@ status_t I2C_MasterTransferDMA(I2C_Type *base, i2c_master_dma_handle_t *handle, return result; } +/*! + * brief Get master transfer status during a dma non-blocking transfer + * + * param base I2C peripheral base address + * param handle pointer to i2c_master_dma_handle_t structure + * param count Number of bytes transferred so far by the non-blocking transaction. + */ status_t I2C_MasterTransferGetCountDMA(I2C_Type *base, i2c_master_dma_handle_t *handle, size_t *count) { assert(handle); @@ -530,6 +533,12 @@ status_t I2C_MasterTransferGetCountDMA(I2C_Type *base, i2c_master_dma_handle_t * return kStatus_Success; } +/*! + * brief Abort a master dma non-blocking transfer in a early time + * + * param base I2C peripheral base address + * param handle pointer to i2c_master_dma_handle_t structure + */ void I2C_MasterTransferAbortDMA(I2C_Type *base, i2c_master_dma_handle_t *handle) { uint32_t status; diff --git a/ext/hal/nxp/mcux/drivers/lpc/fsl_i2c_dma.h b/ext/hal/nxp/mcux/drivers/lpc/fsl_i2c_dma.h index 794e8ec0ba4..a836b1e3e7b 100644 --- a/ext/hal/nxp/mcux/drivers/lpc/fsl_i2c_dma.h +++ b/ext/hal/nxp/mcux/drivers/lpc/fsl_i2c_dma.h @@ -1,31 +1,9 @@ /* * Copyright (c) 2015, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause */ #ifndef _FSL_I2C_DMA_H_ #define _FSL_I2C_DMA_H_ @@ -42,6 +20,12 @@ * Definitions ******************************************************************************/ +/*! @name Driver version */ +/*@{*/ +/*! @brief I2C DMA driver version 2.0.3. */ +#define FSL_I2C_DMA_DRIVER_VERSION (MAKE_VERSION(2, 0, 3)) +/*@}*/ + /*! @brief Maximum lenght of single DMA transfer (determined by capability of the DMA engine) */ #define I2C_MAX_DMA_TRANSFER_COUNT 1024 diff --git a/ext/hal/nxp/mcux/drivers/lpc/fsl_i2s.c b/ext/hal/nxp/mcux/drivers/lpc/fsl_i2s.c index 878f71e7217..a4611b2c031 100644 --- a/ext/hal/nxp/mcux/drivers/lpc/fsl_i2s.c +++ b/ext/hal/nxp/mcux/drivers/lpc/fsl_i2s.c @@ -1,31 +1,9 @@ /* * Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP + * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * SPDX-License-Identifier: BSD-3-Clause */ #include "fsl_i2s.h" @@ -36,6 +14,11 @@ * Definitions ******************************************************************************/ +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.flexcomm_i2s" +#endif + /* TODO - absent in device header files, should be there */ #define I2S_FIFOCFG_TXI2SE0_MASK (0x4U) #define I2S_FIFOCFG_TXI2SE0_SHIFT (2U) @@ -59,12 +42,60 @@ enum _i2s_state ******************************************************************************/ static void I2S_Config(I2S_Type *base, const i2s_config_t *config); +static void I2S_TxEnable(I2S_Type *base, bool enable); +static void I2S_RxEnable(I2S_Type *base, bool enable); static status_t I2S_ValidateBuffer(i2s_handle_t *handle, i2s_transfer_t *transfer); +/******************************************************************************* + * Variables + ******************************************************************************/ + +/*! @brief Array to map i2c instance number to base address. */ +static const uint32_t s_i2sBaseAddrs[FSL_FEATURE_SOC_I2S_COUNT] = I2S_BASE_ADDRS; + +/*! @brief IRQ name array */ +static const IRQn_Type s_i2sIRQ[] = I2S_IRQS; + /******************************************************************************* * Code ******************************************************************************/ +/*! + * brief Returns an instance number given a base address. + * + * If an invalid base address is passed, debug builds will assert. Release builds will just return + * instance number 0. + * + * param base The I2C peripheral base address. + * return I2C instance number starting from 0. + */ +uint32_t I2S_GetInstance(I2S_Type *base) +{ + int i; + for (i = 0; i < FSL_FEATURE_SOC_I2S_COUNT; i++) + { + if ((uint32_t)base == s_i2sBaseAddrs[i]) + { + return i; + } + } + assert(false); + return 0; +} +/*! + * brief Initializes the FLEXCOMM peripheral for I2S transmit functionality. + * + * Ungates the FLEXCOMM clock and configures the module + * for I2S transmission using a configuration structure. + * The configuration structure can be custom filled or set with default values by + * I2S_TxGetDefaultConfig(). + * + * note This API should be called at the beginning of the application to use + * the I2S driver. + * + * param base I2S base pointer. + * param config pointer to I2S configuration structure. + */ void I2S_TxInit(I2S_Type *base, const i2s_config_t *config) { uint32_t cfg = 0U; @@ -86,6 +117,20 @@ void I2S_TxInit(I2S_Type *base, const i2s_config_t *config) base->FIFOTRIG = trig; } +/*! + * brief Initializes the FLEXCOMM peripheral for I2S receive functionality. + * + * Ungates the FLEXCOMM clock and configures the module + * for I2S receive using a configuration structure. + * The configuration structure can be custom filled or set with default values by + * I2S_RxGetDefaultConfig(). + * + * note This API should be called at the beginning of the application to use + * the I2S driver. + * + * param base I2S base pointer. + * param config pointer to I2S configuration structure. + */ void I2S_RxInit(I2S_Type *base, const i2s_config_t *config) { uint32_t cfg = 0U; @@ -106,13 +151,51 @@ void I2S_RxInit(I2S_Type *base, const i2s_config_t *config) base->FIFOTRIG = trig; } +/*! + * brief Sets the I2S Tx configuration structure to default values. + * + * This API initializes the configuration structure for use in I2S_TxInit(). + * The initialized structure can remain unchanged in I2S_TxInit(), or it can be modified + * before calling I2S_TxInit(). + * Example: + code + i2s_config_t config; + I2S_TxGetDefaultConfig(&config); + endcode + * + * Default values: + * code + * config->masterSlave = kI2S_MasterSlaveNormalMaster; + * config->mode = kI2S_ModeI2sClassic; + * config->rightLow = false; + * config->leftJust = false; + * config->pdmData = false; + * config->sckPol = false; + * config->wsPol = false; + * config->divider = 1; + * config->oneChannel = false; + * config->dataLength = 16; + * config->frameLength = 32; + * config->position = 0; + * config->watermark = 4; + * config->txEmptyZero = true; + * config->pack48 = false; + * endcode + * + * param config pointer to I2S configuration structure. + */ void I2S_TxGetDefaultConfig(i2s_config_t *config) { + /* Initializes the configure structure to zero. */ + memset(config, 0, sizeof(*config)); + config->masterSlave = kI2S_MasterSlaveNormalMaster; config->mode = kI2S_ModeI2sClassic; config->rightLow = false; config->leftJust = false; +#if defined(I2S_CFG1_PDMDATA) config->pdmData = false; +#endif config->sckPol = false; config->wsPol = false; config->divider = 1U; @@ -125,13 +208,51 @@ void I2S_TxGetDefaultConfig(i2s_config_t *config) config->pack48 = false; } +/*! + * brief Sets the I2S Rx configuration structure to default values. + * + * This API initializes the configuration structure for use in I2S_RxInit(). + * The initialized structure can remain unchanged in I2S_RxInit(), or it can be modified + * before calling I2S_RxInit(). + * Example: + code + i2s_config_t config; + I2S_RxGetDefaultConfig(&config); + endcode + * + * Default values: + * code + * config->masterSlave = kI2S_MasterSlaveNormalSlave; + * config->mode = kI2S_ModeI2sClassic; + * config->rightLow = false; + * config->leftJust = false; + * config->pdmData = false; + * config->sckPol = false; + * config->wsPol = false; + * config->divider = 1; + * config->oneChannel = false; + * config->dataLength = 16; + * config->frameLength = 32; + * config->position = 0; + * config->watermark = 4; + * config->txEmptyZero = false; + * config->pack48 = false; + * endcode + * + * param config pointer to I2S configuration structure. + */ void I2S_RxGetDefaultConfig(i2s_config_t *config) { + /* Initializes the configure structure to zero. */ + memset(config, 0, sizeof(*config)); + config->masterSlave = kI2S_MasterSlaveNormalSlave; config->mode = kI2S_ModeI2sClassic; config->rightLow = false; config->leftJust = false; +#if defined(I2S_CFG1_PDMDATA) config->pdmData = false; +#endif config->sckPol = false; config->wsPol = false; config->divider = 1U; @@ -163,8 +284,10 @@ static void I2S_Config(I2S_Type *base, const i2s_config_t *config) /* set data justification */ cfg1 |= I2S_CFG1_LEFTJUST(config->leftJust); +#if defined(I2S_CFG1_PDMDATA) /* set source to PDM dmic */ cfg1 |= I2S_CFG1_PDMDATA(config->pdmData); +#endif /* set SCLK polarity */ cfg1 |= I2S_CFG1_SCK_POL(config->sckPol); @@ -192,12 +315,20 @@ static void I2S_Config(I2S_Type *base, const i2s_config_t *config) base->DIV = I2S_DIV_DIV(config->divider - 1U); } +/*! + * brief De-initializes the I2S peripheral. + * + * This API gates the FLEXCOMM clock. The I2S module can't operate unless I2S_TxInit + * or I2S_RxInit is called to enable the clock. + * + * param base I2S base pointer. + */ void I2S_Deinit(I2S_Type *base) { /* TODO gate FLEXCOMM clock via FLEXCOMM driver */ } -void I2S_TxEnable(I2S_Type *base, bool enable) +static void I2S_TxEnable(I2S_Type *base, bool enable) { if (enable) { @@ -212,7 +343,7 @@ void I2S_TxEnable(I2S_Type *base, bool enable) } } -void I2S_RxEnable(I2S_Type *base, bool enable) +static void I2S_RxEnable(I2S_Type *base, bool enable) { if (enable) { @@ -325,13 +456,26 @@ static status_t I2S_ValidateBuffer(i2s_handle_t *handle, i2s_transfer_t *transfe return kStatus_Success; } +/*! + * brief Initializes handle for transfer of audio data. + * + * param base I2S base pointer. + * param handle pointer to handle structure. + * param callback function to be called back when transfer is done or fails. + * param userData pointer to data passed to callback. + */ void I2S_TxTransferCreateHandle(I2S_Type *base, i2s_handle_t *handle, i2s_transfer_callback_t callback, void *userData) { + uint32_t instance; + assert(handle); /* Clear out the handle */ memset(handle, 0U, sizeof(*handle)); + /* Look up instance number */ + instance = I2S_GetInstance(base); + /* Save callback and user data */ handle->completionCallback = callback; handle->userData = userData; @@ -345,9 +489,22 @@ void I2S_TxTransferCreateHandle(I2S_Type *base, i2s_handle_t *handle, i2s_transf handle->useFifo48H = false; /* Register IRQ handling */ - FLEXCOMM_SetIRQHandler(base, (flexcomm_irq_handler_t)(uintptr_t)I2S_TxHandleIRQ, handle); + FLEXCOMM_SetIRQHandler(base, (flexcomm_irq_handler_t)I2S_TxHandleIRQ, handle); + + /* enable NVIC IRQ. */ + EnableIRQ(s_i2sIRQ[instance]); } +/*! + * brief Begins or queue sending of the given data. + * + * param base I2S base pointer. + * param handle pointer to handle structure. + * param transfer data buffer. + * + * retval kStatus_Success + * retval kStatus_I2S_Busy if all queue slots are occupied with unsent buffers. + */ status_t I2S_TxTransferNonBlocking(I2S_Type *base, i2s_handle_t *handle, i2s_transfer_t transfer) { assert(handle); @@ -381,6 +538,12 @@ status_t I2S_TxTransferNonBlocking(I2S_Type *base, i2s_handle_t *handle, i2s_tra return kStatus_Success; } +/*! + * brief Aborts sending of data. + * + * param base I2S base pointer. + * param handle pointer to handle structure. + */ void I2S_TxTransferAbort(I2S_Type *base, i2s_handle_t *handle) { assert(handle); @@ -397,13 +560,26 @@ void I2S_TxTransferAbort(I2S_Type *base, i2s_handle_t *handle) handle->queueUser = 0U; } +/*! + * brief Initializes handle for reception of audio data. + * + * param base I2S base pointer. + * param handle pointer to handle structure. + * param callback function to be called back when transfer is done or fails. + * param userData pointer to data passed to callback. + */ void I2S_RxTransferCreateHandle(I2S_Type *base, i2s_handle_t *handle, i2s_transfer_callback_t callback, void *userData) { + uint32_t instance; + assert(handle); /* Clear out the handle */ memset(handle, 0U, sizeof(*handle)); + /* Look up instance number */ + instance = I2S_GetInstance(base); + /* Save callback and user data */ handle->completionCallback = callback; handle->userData = userData; @@ -417,9 +593,22 @@ void I2S_RxTransferCreateHandle(I2S_Type *base, i2s_handle_t *handle, i2s_transf handle->useFifo48H = false; /* Register IRQ handling */ - FLEXCOMM_SetIRQHandler(base, (flexcomm_irq_handler_t)(uintptr_t)I2S_RxHandleIRQ, handle); + FLEXCOMM_SetIRQHandler(base, (flexcomm_irq_handler_t)I2S_RxHandleIRQ, handle); + + /* enable NVIC IRQ. */ + EnableIRQ(s_i2sIRQ[instance]); } +/*! + * brief Begins or queue reception of data into given buffer. + * + * param base I2S base pointer. + * param handle pointer to handle structure. + * param transfer data buffer. + * + * retval kStatus_Success + * retval kStatus_I2S_Busy if all queue slots are occupied with buffers which are not full. + */ status_t I2S_RxTransferNonBlocking(I2S_Type *base, i2s_handle_t *handle, i2s_transfer_t transfer) { assert(handle); @@ -453,6 +642,12 @@ status_t I2S_RxTransferNonBlocking(I2S_Type *base, i2s_handle_t *handle, i2s_tra return kStatus_Success; } +/*! + * brief Aborts receiving of data. + * + * param base I2S base pointer. + * param handle pointer to handle structure. + */ void I2S_RxTransferAbort(I2S_Type *base, i2s_handle_t *handle) { assert(handle); @@ -469,6 +664,16 @@ void I2S_RxTransferAbort(I2S_Type *base, i2s_handle_t *handle) handle->queueUser = 0U; } +/*! + * brief Returns number of bytes transferred so far. + * + * param base I2S base pointer. + * param handle pointer to handle structure. + * param[out] count number of bytes transferred so far by the non-blocking transaction. + * + * retval kStatus_Success + * retval kStatus_NoTransferInProgress there is no non-blocking transaction currently in progress. + */ status_t I2S_TransferGetCount(I2S_Type *base, i2s_handle_t *handle, size_t *count) { assert(handle); @@ -493,6 +698,16 @@ status_t I2S_TransferGetCount(I2S_Type *base, i2s_handle_t *handle, size_t *coun return kStatus_Success; } +/*! + * brief Returns number of buffer underruns or overruns. + * + * param base I2S base pointer. + * param handle pointer to handle structure. + * param[out] count number of transmit errors encountered so far by the non-blocking transaction. + * + * retval kStatus_Success + * retval kStatus_NoTransferInProgress there is no non-blocking transaction currently in progress. + */ status_t I2S_TransferGetErrorCount(I2S_Type *base, i2s_handle_t *handle, size_t *count) { assert(handle); @@ -517,6 +732,12 @@ status_t I2S_TransferGetErrorCount(I2S_Type *base, i2s_handle_t *handle, size_t return kStatus_Success; } +/*! + * brief Invoked from interrupt handler when transmit FIFO level decreases. + * + * param base I2S base pointer. + * param handle pointer to handle structure. + */ void I2S_TxHandleIRQ(I2S_Type *base, i2s_handle_t *handle) { uint32_t intstat = base->FIFOINTSTAT; @@ -550,7 +771,7 @@ void I2S_TxHandleIRQ(I2S_Type *base, i2s_handle_t *handle) } else if (handle->dataLength <= 8U) { - data = *((uint16_t *)handle->i2sQueue[handle->queueDriver].data); + data = *((volatile uint16_t *)handle->i2sQueue[handle->queueDriver].data); base->FIFOWR = ((data & 0xFF00U) << 8U) | (data & 0xFFU); handle->i2sQueue[handle->queueDriver].data += sizeof(uint16_t); handle->transferCount += sizeof(uint16_t); @@ -558,7 +779,7 @@ void I2S_TxHandleIRQ(I2S_Type *base, i2s_handle_t *handle) } else if (handle->dataLength <= 16U) { - base->FIFOWR = *((uint32_t *)(handle->i2sQueue[handle->queueDriver].data)); + base->FIFOWR = *((volatile uint32_t *)(handle->i2sQueue[handle->queueDriver].data)); handle->i2sQueue[handle->queueDriver].data += sizeof(uint32_t); handle->transferCount += sizeof(uint32_t); handle->i2sQueue[handle->queueDriver].dataSize -= sizeof(uint32_t); @@ -569,7 +790,7 @@ void I2S_TxHandleIRQ(I2S_Type *base, i2s_handle_t *handle) { if (handle->useFifo48H) { - base->FIFOWR48H = *((uint16_t *)(handle->i2sQueue[handle->queueDriver].data)); + base->FIFOWR48H = *((volatile uint16_t *)(handle->i2sQueue[handle->queueDriver].data)); handle->i2sQueue[handle->queueDriver].data += sizeof(uint16_t); handle->transferCount += sizeof(uint16_t); handle->i2sQueue[handle->queueDriver].dataSize -= sizeof(uint16_t); @@ -577,7 +798,7 @@ void I2S_TxHandleIRQ(I2S_Type *base, i2s_handle_t *handle) } else { - base->FIFOWR = *((uint32_t *)(handle->i2sQueue[handle->queueDriver].data)); + base->FIFOWR = *((volatile uint32_t *)(handle->i2sQueue[handle->queueDriver].data)); handle->i2sQueue[handle->queueDriver].data += sizeof(uint32_t); handle->transferCount += sizeof(uint32_t); handle->i2sQueue[handle->queueDriver].dataSize -= sizeof(uint32_t); @@ -605,7 +826,7 @@ void I2S_TxHandleIRQ(I2S_Type *base, i2s_handle_t *handle) } else /* if (handle->dataLength <= 32U) */ { - base->FIFOWR = *((uint32_t *)(handle->i2sQueue[handle->queueDriver].data)); + base->FIFOWR = *((volatile uint32_t *)(handle->i2sQueue[handle->queueDriver].data)); handle->i2sQueue[handle->queueDriver].data += sizeof(uint32_t); handle->transferCount += sizeof(uint32_t); handle->i2sQueue[handle->queueDriver].dataSize -= sizeof(uint32_t); @@ -686,6 +907,12 @@ void I2S_TxHandleIRQ(I2S_Type *base, i2s_handle_t *handle) } } +/*! + * brief Invoked from interrupt handler when receive FIFO level decreases. + * + * param base I2S base pointer. + * param handle pointer to handle structure. + */ void I2S_RxHandleIRQ(I2S_Type *base, i2s_handle_t *handle) { uint32_t intstat = base->FIFOINTSTAT; @@ -715,7 +942,8 @@ void I2S_RxHandleIRQ(I2S_Type *base, i2s_handle_t *handle) else if (handle->dataLength <= 8U) { data = base->FIFORD; - *((uint16_t *)handle->i2sQueue[handle->queueDriver].data) = ((data >> 8U) & 0xFF00U) | (data & 0xFFU); + *((volatile uint16_t *)handle->i2sQueue[handle->queueDriver].data) = + ((data >> 8U) & 0xFF00U) | (data & 0xFFU); handle->i2sQueue[handle->queueDriver].data += sizeof(uint16_t); handle->transferCount += sizeof(uint16_t); handle->i2sQueue[handle->queueDriver].dataSize -= sizeof(uint16_t); @@ -723,7 +951,7 @@ void I2S_RxHandleIRQ(I2S_Type *base, i2s_handle_t *handle) else if (handle->dataLength <= 16U) { data = base->FIFORD; - *((uint32_t *)handle->i2sQueue[handle->queueDriver].data) = data; + *((volatile uint32_t *)handle->i2sQueue[handle->queueDriver].data) = data; handle->i2sQueue[handle->queueDriver].data += sizeof(uint32_t); handle->transferCount += sizeof(uint32_t); handle->i2sQueue[handle->queueDriver].dataSize -= sizeof(uint32_t); @@ -737,7 +965,7 @@ void I2S_RxHandleIRQ(I2S_Type *base, i2s_handle_t *handle) data = base->FIFORD48H; handle->useFifo48H = false; - *((uint16_t *)handle->i2sQueue[handle->queueDriver].data) = data; + *((volatile uint16_t *)handle->i2sQueue[handle->queueDriver].data) = data; handle->i2sQueue[handle->queueDriver].data += sizeof(uint16_t); handle->transferCount += sizeof(uint16_t); handle->i2sQueue[handle->queueDriver].dataSize -= sizeof(uint16_t); @@ -747,7 +975,7 @@ void I2S_RxHandleIRQ(I2S_Type *base, i2s_handle_t *handle) data = base->FIFORD; handle->useFifo48H = true; - *((uint32_t *)handle->i2sQueue[handle->queueDriver].data) = data; + *((volatile uint32_t *)handle->i2sQueue[handle->queueDriver].data) = data; handle->i2sQueue[handle->queueDriver].data += sizeof(uint32_t); handle->transferCount += sizeof(uint32_t); handle->i2sQueue[handle->queueDriver].dataSize -= sizeof(uint32_t); @@ -776,7 +1004,7 @@ void I2S_RxHandleIRQ(I2S_Type *base, i2s_handle_t *handle) else /* if (handle->dataLength <= 32U) */ { data = base->FIFORD; - *((uint32_t *)handle->i2sQueue[handle->queueDriver].data) = data; + *((volatile uint32_t *)handle->i2sQueue[handle->queueDriver].data) = data; handle->i2sQueue[handle->queueDriver].data += sizeof(uint32_t); handle->transferCount += sizeof(uint32_t); handle->i2sQueue[handle->queueDriver].dataSize -= sizeof(uint32_t); diff --git a/ext/hal/nxp/mcux/drivers/lpc/fsl_i2s.h b/ext/hal/nxp/mcux/drivers/lpc/fsl_i2s.h index d7bc3e1ba57..952f021f2b4 100644 --- a/ext/hal/nxp/mcux/drivers/lpc/fsl_i2s.h +++ b/ext/hal/nxp/mcux/drivers/lpc/fsl_i2s.h @@ -1,31 +1,9 @@ /* * Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP + * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * SPDX-License-Identifier: BSD-3-Clause */ #ifndef _FSL_I2S_H_ #define _FSL_I2S_H_ @@ -47,15 +25,19 @@ /*! @name Driver version */ /*@{*/ -/*! @brief I2S driver version 2.0.0. +/*! @brief I2S driver version 2.0.2. * - * Current version: 2.0.0 + * Current version: 2.0.2 * * Change log: + * - Version 2.0.2 + * - Add ENABLE_IRQ handle after register i2s interrupt handle + * - Version 2.0.1 + * - Unify component full name to FLEXCOMM I2S(DMA) Driver * - Version 2.0.0 * - initial version */ -#define FSL_I2S_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) +#define FSL_I2S_DRIVER_VERSION (MAKE_VERSION(2, 0, 2)) /*@}*/ #ifndef I2S_NUM_BUFFERS @@ -113,16 +95,18 @@ typedef struct _i2s_config i2s_mode_t mode; /*!< I2S mode */ bool rightLow; /*!< Right channel data in low portion of FIFO */ bool leftJust; /*!< Left justify data in FIFO */ - bool pdmData; /*!< Data source is the D-Mic subsystem */ - bool sckPol; /*!< SCK polarity */ - bool wsPol; /*!< WS polarity */ - uint16_t divider; /*!< Flexcomm function clock divider (1 - 4096) */ - bool oneChannel; /*!< true mono, false stereo */ - uint8_t dataLength; /*!< Data length (4 - 32) */ - uint16_t frameLength; /*!< Frame width (4 - 512) */ - uint16_t position; /*!< Data position in the frame */ - uint8_t watermark; /*!< FIFO trigger level */ - bool txEmptyZero; /*!< Transmit zero when buffer becomes empty or last item */ +#if defined(I2S_CFG1_PDMDATA) + bool pdmData; /*!< Data source is the D-Mic subsystem */ +#endif + bool sckPol; /*!< SCK polarity */ + bool wsPol; /*!< WS polarity */ + uint16_t divider; /*!< Flexcomm function clock divider (1 - 4096) */ + bool oneChannel; /*!< true mono, false stereo */ + uint8_t dataLength; /*!< Data length (4 - 32) */ + uint16_t frameLength; /*!< Frame width (4 - 512) */ + uint16_t position; /*!< Data position in the frame */ + uint8_t watermark; /*!< FIFO trigger level */ + bool txEmptyZero; /*!< Transmit zero when buffer becomes empty or last item */ bool pack48; /*!< Packing format for 48-bit data (false - 24 bit values, true - alternating 32-bit and 16-bit values) */ } i2s_config_t; diff --git a/ext/hal/nxp/mcux/drivers/lpc/fsl_i2s_dma.c b/ext/hal/nxp/mcux/drivers/lpc/fsl_i2s_dma.c index 3b69be4772e..3e137db39f5 100644 --- a/ext/hal/nxp/mcux/drivers/lpc/fsl_i2s_dma.c +++ b/ext/hal/nxp/mcux/drivers/lpc/fsl_i2s_dma.c @@ -1,31 +1,9 @@ /* * Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP + * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * SPDX-License-Identifier: BSD-3-Clause */ #include "fsl_dma.h" @@ -37,6 +15,11 @@ * Definitions ******************************************************************************/ +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.flexcomm_i2s_dma" +#endif + #define DMA_MAX_TRANSFER_BYTES (DMA_MAX_TRANSFER_COUNT * sizeof(uint32_t)) #define DMA_DESCRIPTORS (2U) @@ -95,7 +78,7 @@ static void I2S_AddTransferDMA(I2S_Type *base, i2s_dma_handle_t *handle); #if defined(__ICCARM__) #pragma data_alignment = 16 static dma_descriptor_t s_DmaDescriptors[DMA_DESCRIPTORS * FSL_FEATURE_SOC_I2S_COUNT]; -#elif defined(__CC_ARM) +#elif defined(__CC_ARM) || defined(__ARMCC_VERSION) __attribute__((aligned(16))) static dma_descriptor_t s_DmaDescriptors[DMA_DESCRIPTORS * FSL_FEATURE_SOC_I2S_COUNT]; #elif defined(__GNUC__) __attribute__((aligned(16))) static dma_descriptor_t s_DmaDescriptors[DMA_DESCRIPTORS * FSL_FEATURE_SOC_I2S_COUNT]; @@ -105,7 +88,7 @@ __attribute__((aligned(16))) static dma_descriptor_t s_DmaDescriptors[DMA_DESCRI #if defined(__ICCARM__) #pragma data_alignment = 4 static uint32_t s_DummyBufferTx = 0U; -#elif defined(__CC_ARM) +#elif defined(__CC_ARM) || defined(__ARMCC_VERSION) __attribute__((aligned(4))) static uint32_t s_DummyBufferTx = 0U; #elif defined(__GNUC__) __attribute__((aligned(4))) static uint32_t s_DummyBufferTx = 0U; @@ -115,7 +98,7 @@ __attribute__((aligned(4))) static uint32_t s_DummyBufferTx = 0U; #if defined(__ICCARM__) #pragma data_alignment = 4 static uint32_t s_DummyBufferRx = 0U; -#elif defined(__CC_ARM) +#elif defined(__CC_ARM) || defined(__ARMCC_VERSION) __attribute__((aligned(4))) static uint32_t s_DummyBufferRx = 0U; #elif defined(__GNUC__) __attribute__((aligned(4))) static uint32_t s_DummyBufferRx = 0U; @@ -210,6 +193,15 @@ static inline void I2S_EnableDMAInterrupts(i2s_dma_handle_t *handle) } } +/*! + * brief Initializes handle for transfer of audio data. + * + * param base I2S base pointer. + * param handle pointer to handle structure. + * param dmaHandle pointer to dma handle structure. + * param callback function to be called back when transfer is done or fails. + * param userData pointer to data passed to callback. + */ void I2S_TxTransferCreateHandleDMA(I2S_Type *base, i2s_dma_handle_t *handle, dma_handle_t *dmaHandle, @@ -235,6 +227,16 @@ void I2S_TxTransferCreateHandleDMA(I2S_Type *base, DMA_SetCallback(dmaHandle, I2S_DMACallback, privateHandle); } +/*! + * brief Begins or queue sending of the given data. + * + * param base I2S base pointer. + * param handle pointer to handle structure. + * param transfer data buffer. + * + * retval kStatus_Success + * retval kStatus_I2S_Busy if all queue slots are occupied with unsent buffers. + */ status_t I2S_TxTransferSendDMA(I2S_Type *base, i2s_dma_handle_t *handle, i2s_transfer_t transfer) { status_t status; @@ -267,6 +269,12 @@ status_t I2S_TxTransferSendDMA(I2S_Type *base, i2s_dma_handle_t *handle, i2s_tra return kStatus_Success; } +/*! + * brief Aborts transfer of data. + * + * param base I2S base pointer. + * param handle pointer to handle structure. + */ void I2S_TransferAbortDMA(I2S_Type *base, i2s_dma_handle_t *handle) { assert(handle); @@ -323,6 +331,15 @@ void I2S_TransferAbortDMA(I2S_Type *base, i2s_dma_handle_t *handle) privateHandle->intA = false; } +/*! + * brief Initializes handle for reception of audio data. + * + * param base I2S base pointer. + * param handle pointer to handle structure. + * param dmaHandle pointer to dma handle structure. + * param callback function to be called back when transfer is done or fails. + * param userData pointer to data passed to callback. + */ void I2S_RxTransferCreateHandleDMA(I2S_Type *base, i2s_dma_handle_t *handle, dma_handle_t *dmaHandle, @@ -332,6 +349,17 @@ void I2S_RxTransferCreateHandleDMA(I2S_Type *base, I2S_TxTransferCreateHandleDMA(base, handle, dmaHandle, callback, userData); } +/*! + * brief Begins or queue reception of data into given buffer. + * + * param base I2S base pointer. + * param handle pointer to handle structure. + * param transfer data buffer. + * + * retval kStatus_Success + * retval kStatus_I2S_Busy if all queue slots are occupied with buffers + * which are not full. + */ status_t I2S_RxTransferReceiveDMA(I2S_Type *base, i2s_dma_handle_t *handle, i2s_transfer_t transfer) { status_t status; @@ -437,9 +465,11 @@ static status_t I2S_StartTransferDMA(I2S_Type *base, i2s_dma_handle_t *handle) /* Prepare transfer of data via initial DMA transfer descriptor */ DMA_PrepareTransfer( - &xferConfig, (handle->state == kI2S_DmaStateTx) ? (void *)transfer->data : (void *)&(base->FIFORD), - (handle->state == kI2S_DmaStateTx) ? (void *)&(base->FIFOWR) : (void *)transfer->data, sizeof(uint32_t), - transferBytes, (handle->state == kI2S_DmaStateTx) ? kDMA_MemoryToPeripheral : kDMA_PeripheralToMemory, + &xferConfig, + (void *)((handle->state == kI2S_DmaStateTx) ? (uint32_t)transfer->data : (uint32_t)(&(base->FIFORD))), + (void *)((handle->state == kI2S_DmaStateTx) ? (uint32_t)(&(base->FIFOWR)) : (uint32_t)transfer->data), + sizeof(uint32_t), transferBytes, + (handle->state == kI2S_DmaStateTx) ? kDMA_MemoryToPeripheral : kDMA_PeripheralToMemory, (void *)&(s_DmaDescriptors[(instance * DMA_DESCRIPTORS) + 0U])); /* Initial descriptor is stored in another place in memory, but treat it as another descriptor for simplicity */ @@ -475,10 +505,11 @@ static status_t I2S_StartTransferDMA(I2S_Type *base, i2s_dma_handle_t *handle) xfercfg.dstInc = 0U; xfercfg.transferCount = 8U; - DMA_CreateDescriptor(descriptor, &xfercfg, - (handle->state == kI2S_DmaStateTx) ? (void *)&s_DummyBufferTx : (void *)&(base->FIFORD), - (handle->state == kI2S_DmaStateTx) ? (void *)&(base->FIFOWR) : (void *)&s_DummyBufferRx, - (void *)nextDescriptor); + DMA_CreateDescriptor( + descriptor, &xfercfg, + ((handle->state == kI2S_DmaStateTx) ? (void *)&s_DummyBufferTx : (void *)(uint32_t)(&(base->FIFORD))), + ((handle->state == kI2S_DmaStateTx) ? (void *)(uint32_t)(&(base->FIFOWR)) : (void *)&s_DummyBufferRx), + (void *)nextDescriptor); } /* Submit and start initial DMA transfer */ @@ -513,6 +544,7 @@ static void I2S_AddTransferDMA(I2S_Type *base, i2s_dma_handle_t *handle) i2s_dma_private_handle_t *privateHandle; dma_descriptor_t *descriptor; dma_descriptor_t *nextDescriptor; + uint32_t srcAddr = 0, destAddr = 0; instance = I2S_GetInstance(base); privateHandle = &(s_DmaPrivateHandle[instance]); @@ -548,11 +580,10 @@ static void I2S_AddTransferDMA(I2S_Type *base, i2s_dma_handle_t *handle) xfercfg.srcInc = (handle->state == kI2S_DmaStateTx) ? 1U : 0U; xfercfg.dstInc = (handle->state == kI2S_DmaStateTx) ? 0U : 1U; xfercfg.transferCount = transferBytes / sizeof(uint32_t); + srcAddr = ((handle->state == kI2S_DmaStateTx) ? (uint32_t)transfer->data : (uint32_t) & (base->FIFORD)); + destAddr = ((handle->state == kI2S_DmaStateTx) ? (uint32_t) & (base->FIFOWR) : (uint32_t)transfer->data); - DMA_CreateDescriptor(descriptor, &xfercfg, - (handle->state == kI2S_DmaStateTx) ? (void *)transfer->data : (void *)&(base->FIFORD), - (handle->state == kI2S_DmaStateTx) ? (void *)&(base->FIFOWR) : (void *)transfer->data, - (void *)nextDescriptor); + DMA_CreateDescriptor(descriptor, &xfercfg, (void *)srcAddr, (void *)destAddr, (void *)nextDescriptor); /* Advance internal state */ @@ -569,13 +600,21 @@ static void I2S_AddTransferDMA(I2S_Type *base, i2s_dma_handle_t *handle) } } +/*! + * brief Invoked from DMA interrupt handler. + * + * param handle pointer to DMA handle structure. + * param userData argument for user callback. + * param transferDone if transfer was done. + * param tcds + */ void I2S_DMACallback(dma_handle_t *handle, void *userData, bool transferDone, uint32_t tcds) { i2s_dma_private_handle_t *privateHandle = (i2s_dma_private_handle_t *)userData; i2s_dma_handle_t *i2sHandle = privateHandle->handle; I2S_Type *base = privateHandle->base; - if (!transferDone || (i2sHandle->state == kI2S_DmaStateIdle)) + if ((!transferDone) || (i2sHandle->state == kI2S_DmaStateIdle)) { return; } diff --git a/ext/hal/nxp/mcux/drivers/lpc/fsl_i2s_dma.h b/ext/hal/nxp/mcux/drivers/lpc/fsl_i2s_dma.h index 72a39e4da6e..064b7f354f1 100644 --- a/ext/hal/nxp/mcux/drivers/lpc/fsl_i2s_dma.h +++ b/ext/hal/nxp/mcux/drivers/lpc/fsl_i2s_dma.h @@ -1,31 +1,9 @@ /* * Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause */ #ifndef _FSL_I2S_DMA_H_ #define _FSL_I2S_DMA_H_ @@ -46,19 +24,10 @@ * @{ */ -/*! @file */ - /*! @name Driver version */ /*@{*/ -/*! @brief I2S DMA driver version 2.0.0. - * - * Current version: 2.0.0 - * - * Change log: - * - Version 2.0.0 - * - initial version - */ -#define FSL_I2S_DMA_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) +/*! @brief I2S DMA driver version 2.0.1. */ +#define FSL_I2S_DMA_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) /*@}*/ /*! @brief Members not to be accessed / modified outside of the driver. */ diff --git a/ext/hal/nxp/mcux/drivers/lpc/fsl_iap.c b/ext/hal/nxp/mcux/drivers/lpc/fsl_iap.c new file mode 100644 index 00000000000..86462da2175 --- /dev/null +++ b/ext/hal/nxp/mcux/drivers/lpc/fsl_iap.c @@ -0,0 +1,458 @@ +/* + * Copyright 2018 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_iap.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.iap" +#endif + +#define HZ_TO_KHZ_DIV 1000 + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +static status_t translate_iap_status(uint32_t status) +{ + /* Translate IAP return code to sdk status code */ + if (status == kStatus_Success) + { + return status; + } + else + { + return MAKE_STATUS(kStatusGroup_IAP, status); + } +} + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ + +/*! + * brief Read part identification number. + + * This function is used to read the part identification number. + * + * param partID Address to store the part identification number. + * + * retval #kStatus_IAP_Success Api was executed successfully. + */ +status_t IAP_ReadPartID(uint32_t *partID) +{ + uint32_t command[5], result[5]; + + command[0] = kIapCmd_IAP_ReadPartId; + iap_entry(command, result); + *partID = result[1]; + + return translate_iap_status(result[0]); +} + +/*! + * brief Read boot code version number. + + * This function is used to read the boot code version number. + * + * param bootCodeVersion Address to store the boot code version. + * + * retval #kStatus_IAP_Success Api was executed successfully. + + * note Boot code version is two 32-bit words. Word 0 is the major version, word 1 is the minor version. + */ +status_t IAP_ReadBootCodeVersion(uint32_t *bootCodeVersion) +{ + uint32_t command[5], result[5]; + + command[0] = kIapCmd_IAP_Read_BootromVersion; + iap_entry(command, result); + bootCodeVersion[0] = result[1]; + bootCodeVersion[1] = result[2]; + + return translate_iap_status(result[0]); +} + +/*! + * brief Reinvoke ISP + + * This function is used to invoke the boot loader in ISP mode. It maps boot vectors and configures the + * peripherals for ISP. + * + * param ispTyoe ISP type selection. + * param status store the possible status + * + * retval #kStatus_IAP_ReinvokeISPConfig reinvoke configuration error. + + * note The error response is returned if IAP is disabled, or if there is an invalid ISP type selection. When + * there is no error the call does not return, so there can be no status code. + */ +void IAP_ReinvokeISP(uint8_t ispType, uint32_t *status) +{ + uint32_t command[5], result[5]; + uint8_t ispParameterArray[8]; + + command[0] = kIapCmd_IAP_ReinvokeISP; + memset(ispParameterArray, 0, sizeof(uint8_t) * 8); + ispParameterArray[1] = ispType; + ispParameterArray[7] = ispParameterArray[0] ^ ispParameterArray[1] ^ ispParameterArray[2] ^ ispParameterArray[3] ^ + ispParameterArray[4] ^ ispParameterArray[5] ^ ispParameterArray[6]; + command[1] = (uint32_t)ispParameterArray; + iap_entry(command, result); + *status = translate_iap_status(result[0]); +} + +/*! + * brief Read unique identification. + + * This function is used to read the unique id. + * + * param uniqueID store the uniqueID. + * + * retval #kStatus_IAP_Success Api was executed successfully. + */ +status_t IAP_ReadUniqueID(uint32_t *uniqueID) +{ + uint32_t command[5], result[5]; + + command[0] = kIapCmd_IAP_ReadUid; + iap_entry(command, result); + uniqueID[0] = result[1]; + uniqueID[1] = result[2]; + uniqueID[2] = result[3]; + uniqueID[3] = result[4]; + + return translate_iap_status(result[0]); +} + +/*! + * brief Read factory settings. + + * This function reads the factory settings for calibration registers. + * + * param dstRegAddr Address of the targeted calibration register. + * param factoryValue Store the factory value + * + * retval #kStatus_IAP_Success Api was executed successfully. + * retval #kStatus_IAP_ParamError Param0 is not one of the supported calibration registers + */ +status_t IAP_ReadFactorySettings(uint32_t dstRegAddr, uint32_t *factoryValue) +{ + uint32_t command[5], result[5]; + + command[0] = kIapCmd_IAP_ReadFactorySettings; + command[1] = dstRegAddr; + iap_entry(command, result); + *factoryValue = result[1]; + + return translate_iap_status(result[0]); +} + +/*! + * brief Prepare sector for write operation + + * This function prepares sector(s) for write/erase operation. This function must be + * called before calling the IAP_CopyRamToFlash() or IAP_EraseSector() or + * IAP_ErasePage() function. The end sector must be greater than or equal to + * start sector number. + * + * param startSector Start sector number. + * param endSector End sector number. + * + * retval #kStatus_IAP_Success Api was executed successfully. + * retval #kStatus_IAP_NoPower Flash memory block is powered down. + * retval #kStatus_IAP_NoClock Flash memory block or controller is not clocked. + * retval #kStatus_IAP_InvalidSector Sector number is invalid or end sector number + * is greater than start sector number. + * retval #kStatus_IAP_Busy Flash programming hardware interface is busy. + */ +status_t IAP_PrepareSectorForWrite(uint32_t startSector, uint32_t endSector) +{ + uint32_t command[5], result[5]; + + command[0] = kIapCmd_IAP_PrepareSectorforWrite; + command[1] = startSector; + command[2] = endSector; + iap_entry(command, result); + + return translate_iap_status(result[0]); +} + +/*! + * brief Copy RAM to flash. + + * This function programs the flash memory. Corresponding sectors must be prepared + * via IAP_PrepareSectorForWrite before calling calling this function. The addresses + * should be a 256 byte boundary and the number of bytes should be 256 | 512 | 1024 | 4096. + * + * param dstAddr Destination flash address where data bytes are to be written. + * param srcAddr Source ram address from where data bytes are to be read. + * param numOfBytes Number of bytes to be written. + * param systemCoreClock SystemCoreClock in Hz. It is converted to KHz before calling the + * rom IAP function. + * + * retval #kStatus_IAP_Success Api was executed successfully. + * retval #kStatus_IAP_NoPower Flash memory block is powered down. + * retval #kStatus_IAP_NoClock Flash memory block or controller is not clocked. + * retval #kStatus_IAP_SrcAddrError Source address is not on word boundary. + * retval #kStatus_IAP_DstAddrError Destination address is not on a correct boundary. + * retval #kStatus_IAP_SrcAddrNotMapped Source address is not mapped in the memory map. + * retval #kStatus_IAP_DstAddrNotMapped Destination address is not mapped in the memory map. + * retval #kStatus_IAP_CountError Byte count is not multiple of 4 or is not a permitted value. + * retval #kStatus_IAP_NotPrepared Command to prepare sector for write operation was not executed. + * retval #kStatus_IAP_Busy Flash programming hardware interface is busy. + */ +status_t IAP_CopyRamToFlash(uint32_t dstAddr, uint32_t *srcAddr, uint32_t numOfBytes, uint32_t systemCoreClock) +{ + uint32_t command[5], result[5]; + + command[0] = kIapCmd_IAP_CopyRamToFlash; + command[1] = dstAddr; + command[2] = (uint32_t)srcAddr; + command[3] = numOfBytes; + command[4] = systemCoreClock / HZ_TO_KHZ_DIV; + iap_entry(command, result); + + return translate_iap_status(result[0]); +} + +/*! + * brief Erase sector + + * This function erases sector(s). The end sector must be greater than or equal to + * start sector number. IAP_PrepareSectorForWrite must be called before + * calling this function. + * + * param startSector Start sector number. + * param endSector End sector number. + * param systemCoreClock SystemCoreClock in Hz. It is converted to KHz before calling the + * rom IAP function. + * + * retval #kStatus_IAP_Success Api was executed successfully. + * retval #kStatus_IAP_NoPower Flash memory block is powered down. + * retval #kStatus_IAP_NoClock Flash memory block or controller is not clocked. + * retval #kStatus_IAP_InvalidSector Sector number is invalid or end sector number + * is greater than start sector number. + * retval #kStatus_IAP_NotPrepared Command to prepare sector for write operation was not executed. + * retval #kStatus_IAP_Busy Flash programming hardware interface is busy. + */ +status_t IAP_EraseSector(uint32_t startSector, uint32_t endSector, uint32_t systemCoreClock) +{ + uint32_t command[5], result[5]; + + command[0] = kIapCmd_IAP_EraseSector; + command[1] = startSector; + command[2] = endSector; + command[3] = systemCoreClock / HZ_TO_KHZ_DIV; + iap_entry(command, result); + + return translate_iap_status(result[0]); +} + +/*! + * This function erases page(s). The end page must be greater than or equal to + * start page number. Corresponding sectors must be prepared via IAP_PrepareSectorForWrite + * before calling calling this function. + * + * param startPage Start page number + * param endPage End page number + * param systemCoreClock SystemCoreClock in Hz. It is converted to KHz before calling the + * rom IAP function. + * + * retval #kStatus_IAP_Success Api was executed successfully. + * retval #kStatus_IAP_NoPower Flash memory block is powered down. + * retval #kStatus_IAP_NoClock Flash memory block or controller is not clocked. + * retval #kStatus_IAP_InvalidSector Page number is invalid or end page number + * is greater than start page number + * retval #kStatus_IAP_NotPrepared Command to prepare sector for write operation was not executed. + * retval #kStatus_IAP_Busy Flash programming hardware interface is busy. + */ +status_t IAP_ErasePage(uint32_t startPage, uint32_t endPage, uint32_t systemCoreClock) +{ + uint32_t command[5], result[5]; + + command[0] = kIapCmd_IAP_ErasePage; + command[1] = startPage; + command[2] = endPage; + command[3] = systemCoreClock / HZ_TO_KHZ_DIV; + iap_entry(command, result); + + return translate_iap_status(result[0]); +} + +/*! + * brief Blank check sector(s) + * + * Blank check single or multiples sectors of flash memory. The end sector must be greater than or equal to + * start sector number. It can be used to verify the sector eraseure after IAP_EraseSector call. + * + * param startSector : Start sector number. Must be greater than or equal to start sector number + * param endSector : End sector number + * retval #kStatus_IAP_Success One or more sectors are in erased state. + * retval #kStatus_IAP_NoPower Flash memory block is powered down. + * retval #kStatus_IAP_NoClock Flash memory block or controller is not clocked. + * retval #kStatus_IAP_SectorNotblank One or more sectors are not blank. + */ +status_t IAP_BlankCheckSector(uint32_t startSector, uint32_t endSector) +{ + uint32_t command[5], result[5]; + + command[0] = kIapCmd_IAP_BlankCheckSector; + command[1] = startSector; + command[2] = endSector; + iap_entry(command, result); + + return translate_iap_status(result[0]); +} + +/*! + * brief Compare memory contents of flash with ram. + + * This function compares the contents of flash and ram. It can be used to verify the flash + * memory contents after IAP_CopyRamToFlash call. + * + * param dstAddr Destination flash address. + * param srcAddr Source ram address. + * param numOfBytes Number of bytes to be compared. + * + * retval #kStatus_IAP_Success Contents of flash and ram match. + * retval #kStatus_IAP_NoPower Flash memory block is powered down. + * retval #kStatus_IAP_NoClock Flash memory block or controller is not clocked. + * retval #kStatus_IAP_AddrError Address is not on word boundary. + * retval #kStatus_IAP_AddrNotMapped Address is not mapped in the memory map. + * retval #kStatus_IAP_CountError Byte count is not multiple of 4 or is not a permitted value. + * retval #kStatus_IAP_CompareError Destination and source memory contents do not match. + */ +status_t IAP_Compare(uint32_t dstAddr, uint32_t *srcAddr, uint32_t numOfBytes) +{ + uint32_t command[5], result[5]; + + command[0] = kIapCmd_IAP_Compare; + command[1] = dstAddr; + command[2] = (uint32_t)srcAddr; + command[3] = numOfBytes; + iap_entry(command, result); + + return translate_iap_status(result[0]); +} + +/*! + * brief Extended Read signature. + + * This function calculates the signature value for one or more pages of on-chip flash memory. + * + * param startPage Start page number. + * param endPage End page number. + * param numOfStates Number of wait status. + * param signature Address to store the signature value. + * + * retval #kStatus_IAP_Success Api was executed successfully. + */ +status_t IAP_ExtendedFlashSignatureRead(uint32_t startPage, uint32_t endPage, uint32_t numOfState, uint32_t *signature) +{ + uint32_t command[5], result[5]; + + command[0] = kIapCmd_IAP_ExtendedReadSignature; + command[1] = startPage; + command[2] = endPage; + command[3] = numOfState; + command[4] = 0; + iap_entry(command, result); + signature[0] = result[4]; + signature[1] = result[3]; + signature[2] = result[2]; + signature[3] = result[1]; + + return translate_iap_status(result[0]); +} + +/*! + * @brief Read flash signature + * + * This funtion is used to obtain a 32-bit signature value of the entire flash memory. + * + * @param signature Address to store the 32-bit generated signature value. + * + * @retval #kStatus_IAP_Success Api was executed successfully. + */ +status_t IAP_ReadFlashSignature(uint32_t *signature) +{ + uint32_t command[5], result[5]; + + command[0] = kIapCmd_IAP_ReadSignature; + iap_entry(command, result); + *signature = result[1]; + + return translate_iap_status(result[0]); +} + +/*! + * brief Read EEPROM page. + + * This function is used to read given page of EEPROM into the memory provided. + * + * param pageNumber EEPROM page number. + * param dstAddr Memory address to store the value read from EEPROM. + * param systemCoreClock Current core clock frequency in kHz. + * + * retval #kStatus_IAP_Success Api was executed successfully. + * retval #kStatus_IAP_InvalidSector Sector number is invalid. + * retval #kStatus_IAP_SrcAddrNotMapped Source address is not mapped in the memory map. + * + * note Value 0xFFFFFFFF of systemCoreClock will retain the timing and clock settings for + * EEPROM] + */ +status_t IAP_ReadEEPROMPage(uint32_t pageNumber, uint32_t *dstAddr, uint32_t systemCoreClock) +{ + uint32_t command[5], result[5]; + + command[0] = kIapCmd_IAP_ReadEEPROMPage; + command[1] = pageNumber; + command[2] = (uint32_t)dstAddr; + command[3] = systemCoreClock / HZ_TO_KHZ_DIV; + iap_entry(command, result); + + return translate_iap_status(result[0]); +} + +/*! + * brief Write EEPROM page. + + * This function is used to write given data in the provided memory to a page of EEPROM. + * + * param pageNumber EEPROM page number. + * param srcAddr Memory address holding data to be stored on to EEPROM page. + * param systemCoreClock Current core clock frequency in kHz. + * + * retval #kStatus_IAP_Success Api was executed successfully. + * retval #kStatus_IAP_InvalidSector Sector number is invalid. + * retval #kStatus_IAP_SrcAddrNotMapped Source address is not mapped in the memory map. + * + * note Value 0xFFFFFFFF of systemCoreClock will retain the timing and clock settings for + * EEPROM] + */ +status_t IAP_WriteEEPROMPage(uint32_t pageNumber, uint32_t *srcAddr, uint32_t systemCoreClock) +{ + uint32_t command[5], result[5]; + + command[0] = kIapCmd_IAP_WriteEEPROMPage; + command[1] = pageNumber; + command[2] = (uint32_t)srcAddr; + command[3] = systemCoreClock / HZ_TO_KHZ_DIV; + iap_entry(command, result); + + return translate_iap_status(result[0]); +} diff --git a/ext/hal/nxp/mcux/drivers/lpc/fsl_iap.h b/ext/hal/nxp/mcux/drivers/lpc/fsl_iap.h new file mode 100644 index 00000000000..6ba12a706be --- /dev/null +++ b/ext/hal/nxp/mcux/drivers/lpc/fsl_iap.h @@ -0,0 +1,386 @@ +/* + * Copyright 2018 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _FSL_IAP_H_ +#define _FSL_IAP_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup IAP_driver + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +#define FSL_IAP_DRIVER_VERSION (MAKE_VERSION(2, 0, 2)) /*!< Version 2.0.2. */ + /*@}*/ + +/*! + * @brief iap status codes. + */ +enum _iap_status +{ + kStatus_IAP_Success = kStatus_Success, /*!< Api is executed successfully */ + kStatus_IAP_InvalidCommand = MAKE_STATUS(kStatusGroup_IAP, 1U), /*!< Invalid command */ + kStatus_IAP_SrcAddrError = MAKE_STATUS(kStatusGroup_IAP, 2U), /*!< Source address is not on word boundary */ + kStatus_IAP_DstAddrError = + MAKE_STATUS(kStatusGroup_IAP, 3U), /*!< Destination address is not on a correct boundary */ + kStatus_IAP_SrcAddrNotMapped = + MAKE_STATUS(kStatusGroup_IAP, 4U), /*!< Source address is not mapped in the memory map */ + kStatus_IAP_DstAddrNotMapped = + MAKE_STATUS(kStatusGroup_IAP, 5U), /*!< Destination address is not mapped in the memory map */ + kStatus_IAP_CountError = + MAKE_STATUS(kStatusGroup_IAP, 6U), /*!< Byte count is not multiple of 4 or is not a permitted value */ + kStatus_IAP_InvalidSector = MAKE_STATUS( + kStatusGroup_IAP, 7), /*!< Sector number is invalid or end sector number is greater than start sector number */ + kStatus_IAP_SectorNotblank = MAKE_STATUS(kStatusGroup_IAP, 8U), /*!< One or more sectors are not blank */ + kStatus_IAP_NotPrepared = + MAKE_STATUS(kStatusGroup_IAP, 9U), /*!< Command to prepare sector for write operation was not executed */ + kStatus_IAP_CompareError = + MAKE_STATUS(kStatusGroup_IAP, 10U), /*!< Destination and source memory contents do not match */ + kStatus_IAP_Busy = MAKE_STATUS(kStatusGroup_IAP, 11U), /*!< Flash programming hardware interface is busy */ + kStatus_IAP_ParamError = + MAKE_STATUS(kStatusGroup_IAP, 12U), /*!< Insufficient number of parameters or invalid parameter */ + kStatus_IAP_AddrError = MAKE_STATUS(kStatusGroup_IAP, 13U), /*!< Address is not on word boundary */ + kStatus_IAP_AddrNotMapped = MAKE_STATUS(kStatusGroup_IAP, 14U), /*!< Address is not mapped in the memory map */ + kStatus_IAP_NoPower = MAKE_STATUS(kStatusGroup_IAP, 24U), /*!< Flash memory block is powered down */ + kStatus_IAP_NoClock = MAKE_STATUS(kStatusGroup_IAP, 27U), /*!< Flash memory block or controller is not clocked */ + kStatus_IAP_ReinvokeISPConfig = MAKE_STATUS(kStatusGroup_IAP, 0x1CU), /*!< Reinvoke configuration error */ +}; + +/*! + * @brief iap command codes. + */ +enum _iap_commands +{ + kIapCmd_IAP_ReadFactorySettings = 40U, /*!< Read the factory settings */ + kIapCmd_IAP_PrepareSectorforWrite = 50U, /*!< Prepare Sector for write */ + kIapCmd_IAP_CopyRamToFlash = 51U, /*!< Copy RAM to flash */ + kIapCmd_IAP_EraseSector = 52U, /*!< Erase Sector */ + kIapCmd_IAP_BlankCheckSector = 53U, /*!< Blank check sector */ + kIapCmd_IAP_ReadPartId = 54U, /*!< Read part id */ + kIapCmd_IAP_Read_BootromVersion = 55U, /*!< Read bootrom version */ + kIapCmd_IAP_Compare = 56U, /*!< Compare */ + kIapCmd_IAP_ReinvokeISP = 57U, /*!< Reinvoke ISP */ + kIapCmd_IAP_ReadUid = 58U, /*!< Read Uid */ + kIapCmd_IAP_ErasePage = 59U, /*!< Erase Page */ + kIapCmd_IAP_ReadSignature = 70U, /*!< Read Signature */ + kIapCmd_IAP_ExtendedReadSignature = 73U, /*!< Extended Read Signature */ + kIapCmd_IAP_ReadEEPROMPage = 80U, /*!< Read EEPROM page */ + kIapCmd_IAP_WriteEEPROMPage = 81U /*!< Write EEPROM page */ +}; + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/*! @brief IAP_ENTRY API function type */ +typedef void (*IAP_ENTRY_T)(uint32_t cmd[], uint32_t stat[]); + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @brief IAP_ENTRY API function type + * + * Wrapper for rom iap call + * + * @param cmd_param IAP command and relevant parameter array. + * @param status_result IAP status result array. + * + * @retval None. Status/Result is returned via status_result array. + */ +static inline void iap_entry(uint32_t *cmd_param, uint32_t *status_result) +{ + __disable_irq(); + ((IAP_ENTRY_T)FSL_FEATURE_SYSCON_IAP_ENTRY_LOCATION)(cmd_param, status_result); + __enable_irq(); +} + +/*! + * @brief Read part identification number. + + * This function is used to read the part identification number. + * + * @param partID Address to store the part identification number. + * + * @retval #kStatus_IAP_Success Api was executed successfully. + */ +status_t IAP_ReadPartID(uint32_t *partID); + +/*! + * @brief Read boot code version number. + + * This function is used to read the boot code version number. + * + * @param bootCodeVersion Address to store the boot code version. + * + * @retval #kStatus_IAP_Success Api was executed successfully. + + * @note Boot code version is two 32-bit words. Word 0 is the major version, word 1 is the minor version. + */ +status_t IAP_ReadBootCodeVersion(uint32_t *bootCodeVersion); + +/*! + * @brief Reinvoke ISP + + * This function is used to invoke the boot loader in ISP mode. It maps boot vectors and configures the + * peripherals for ISP. + * + * @param ispTyoe ISP type selection. + * @param status store the possible status + * + * @retval #kStatus_IAP_ReinvokeISPConfig reinvoke configuration error. + + * @note The error response is returned if IAP is disabled, or if there is an invalid ISP type selection. When + * there is no error the call does not return, so there can be no status code. + */ +void IAP_ReinvokeISP(uint8_t ispType, uint32_t *status); + +/*! + * @brief Read unique identification. + + * This function is used to read the unique id. + * + * @param uniqueID store the uniqueID. + * + * @retval #kStatus_IAP_Success Api was executed successfully. + */ +status_t IAP_ReadUniqueID(uint32_t *uniqueID); + +#if (defined(FSL_FEATURE_IAP_HAS_READ_FACTORY_SETTINGS_FUNCTION) && \ + (FSL_FEATURE_IAP_HAS_READ_FACTORY_SETTINGS_FUNCTION == 1)) +/*! + * @brief Read factory settings. + + * This function reads the factory settings for calibration registers. + * + * @param dstRegAddr Address of the targeted calibration register. + * @param factoryValue Store the factory value + * + * @retval #kStatus_IAP_Success Api was executed successfully. + * @retval #kStatus_IAP_ParamError Param0 is not one of the supported calibration registers + */ +status_t IAP_ReadFactorySettings(uint32_t dstRegAddr, uint32_t *factoryValue); +#endif + +#if (defined(FSL_FEATURE_IAP_HAS_FLASH_FUNCTION) && (FSL_FEATURE_IAP_HAS_FLASH_FUNCTION == 1)) +/*! + * @brief Prepare sector for write operation + + * This function prepares sector(s) for write/erase operation. This function must be + * called before calling the IAP_CopyRamToFlash() or IAP_EraseSector() or + * IAP_ErasePage() function. The end sector must be greater than or equal to + * start sector number. + * + * @param startSector Start sector number. + * @param endSector End sector number. + * + * @retval #kStatus_IAP_Success Api was executed successfully. + * @retval #kStatus_IAP_NoPower Flash memory block is powered down. + * @retval #kStatus_IAP_NoClock Flash memory block or controller is not clocked. + * @retval #kStatus_IAP_InvalidSector Sector number is invalid or end sector number + * is greater than start sector number. + * @retval #kStatus_IAP_Busy Flash programming hardware interface is busy. + */ +status_t IAP_PrepareSectorForWrite(uint32_t startSector, uint32_t endSector); + +/*! + * @brief Copy RAM to flash. + + * This function programs the flash memory. Corresponding sectors must be prepared + * via IAP_PrepareSectorForWrite before calling calling this function. The addresses + * should be a 256 byte boundary and the number of bytes should be 256 | 512 | 1024 | 4096. + * + * @param dstAddr Destination flash address where data bytes are to be written. + * @param srcAddr Source ram address from where data bytes are to be read. + * @param numOfBytes Number of bytes to be written. + * @param systemCoreClock SystemCoreClock in Hz. It is converted to KHz before calling the + * rom IAP function. + * + * @retval #kStatus_IAP_Success Api was executed successfully. + * @retval #kStatus_IAP_NoPower Flash memory block is powered down. + * @retval #kStatus_IAP_NoClock Flash memory block or controller is not clocked. + * @retval #kStatus_IAP_SrcAddrError Source address is not on word boundary. + * @retval #kStatus_IAP_DstAddrError Destination address is not on a correct boundary. + * @retval #kStatus_IAP_SrcAddrNotMapped Source address is not mapped in the memory map. + * @retval #kStatus_IAP_DstAddrNotMapped Destination address is not mapped in the memory map. + * @retval #kStatus_IAP_CountError Byte count is not multiple of 4 or is not a permitted value. + * @retval #kStatus_IAP_NotPrepared Command to prepare sector for write operation was not executed. + * @retval #kStatus_IAP_Busy Flash programming hardware interface is busy. + */ +status_t IAP_CopyRamToFlash(uint32_t dstAddr, uint32_t *srcAddr, uint32_t numOfBytes, uint32_t systemCoreClock); + +/*! + * @brief Erase sector + + * This function erases sector(s). The end sector must be greater than or equal to + * start sector number. IAP_PrepareSectorForWrite must be called before + * calling this function. + * + * @param startSector Start sector number. + * @param endSector End sector number. + * @param systemCoreClock SystemCoreClock in Hz. It is converted to KHz before calling the + * rom IAP function. + * + * @retval #kStatus_IAP_Success Api was executed successfully. + * @retval #kStatus_IAP_NoPower Flash memory block is powered down. + * @retval #kStatus_IAP_NoClock Flash memory block or controller is not clocked. + * @retval #kStatus_IAP_InvalidSector Sector number is invalid or end sector number + * is greater than start sector number. + * @retval #kStatus_IAP_NotPrepared Command to prepare sector for write operation was not executed. + * @retval #kStatus_IAP_Busy Flash programming hardware interface is busy. + */ +status_t IAP_EraseSector(uint32_t startSector, uint32_t endSector, uint32_t systemCoreClock); + +/*! + + * This function erases page(s). The end page must be greater than or equal to + * start page number. Corresponding sectors must be prepared via IAP_PrepareSectorForWrite + * before calling calling this function. + * + * @param startPage Start page number + * @param endPage End page number + * @param systemCoreClock SystemCoreClock in Hz. It is converted to KHz before calling the + * rom IAP function. + * + * @retval #kStatus_IAP_Success Api was executed successfully. + * @retval #kStatus_IAP_NoPower Flash memory block is powered down. + * @retval #kStatus_IAP_NoClock Flash memory block or controller is not clocked. + * @retval #kStatus_IAP_InvalidSector Page number is invalid or end page number + * is greater than start page number + * @retval #kStatus_IAP_NotPrepared Command to prepare sector for write operation was not executed. + * @retval #kStatus_IAP_Busy Flash programming hardware interface is busy. + */ +status_t IAP_ErasePage(uint32_t startPage, uint32_t endPage, uint32_t systemCoreClock); + +/*! + * @brief Blank check sector(s) + * + * Blank check single or multiples sectors of flash memory. The end sector must be greater than or equal to + * start sector number. It can be used to verify the sector eraseure after IAP_EraseSector call. + * + * @param startSector : Start sector number. Must be greater than or equal to start sector number + * @param endSector : End sector number + * @retval #kStatus_IAP_Success One or more sectors are in erased state. + * @retval #kStatus_IAP_NoPower Flash memory block is powered down. + * @retval #kStatus_IAP_NoClock Flash memory block or controller is not clocked. + * @retval #kStatus_IAP_SectorNotblank One or more sectors are not blank. + */ +status_t IAP_BlankCheckSector(uint32_t startSector, uint32_t endSector); + +/*! + * @brief Compare memory contents of flash with ram. + + * This function compares the contents of flash and ram. It can be used to verify the flash + * memory contents after IAP_CopyRamToFlash call. + * + * @param dstAddr Destination flash address. + * @param srcAddr Source ram address. + * @param numOfBytes Number of bytes to be compared. + * + * @retval #kStatus_IAP_Success Contents of flash and ram match. + * @retval #kStatus_IAP_NoPower Flash memory block is powered down. + * @retval #kStatus_IAP_NoClock Flash memory block or controller is not clocked. + * @retval #kStatus_IAP_AddrError Address is not on word boundary. + * @retval #kStatus_IAP_AddrNotMapped Address is not mapped in the memory map. + * @retval #kStatus_IAP_CountError Byte count is not multiple of 4 or is not a permitted value. + * @retval #kStatus_IAP_CompareError Destination and source memory contents do not match. + */ +status_t IAP_Compare(uint32_t dstAddr, uint32_t *srcAddr, uint32_t numOfBytes); + +#if defined(FSL_FEATURE_IAP_HAS_FLASH_EXTENDED_SIGNATURE_READ) && FSL_FEATURE_IAP_HAS_FLASH_EXTENDED_SIGNATURE_READ +/*! + * @brief Extended Read signature. + + * This function calculates the signature value for one or more pages of on-chip flash memory. + * + * @param startPage Start page number. + * @param endPage End page number. + * @param numOfStates Number of wait status. + * @param signature Address to store the signature value. + * + * @retval #kStatus_IAP_Success Api was executed successfully. + */ +status_t IAP_ExtendedFlashSignatureRead(uint32_t startPage, uint32_t endPage, uint32_t numOfState, uint32_t *signature); +#endif /* FSL_FEATURE_IAP_HAS_FLASH_EXTENDED_SIGNATURE_READ */ + +#if defined(FSL_FEATURE_IAP_HAS_FLASH_SIGNATURE_READ) && FSL_FEATURE_IAP_HAS_FLASH_SIGNATURE_READ +/*! + * @brief Read flash signature + * + * This funtion is used to obtain a 32-bit signature value of the entire flash memory. + * + * @param signature Address to store the 32-bit generated signature value. + * + * @retval #kStatus_IAP_Success Api was executed successfully. + */ +status_t IAP_ReadFlashSignature(uint32_t *signature); +#endif /* FSL_FEATURE_IAP_HAS_FLASH_SIGNATURE_READ */ +#endif /* FSL_FEATURE_IAP_HAS_FLASH_FUNCTION */ + +#if (defined(FSL_FEATURE_IAP_HAS_EEPROM_FUNCTION) && (FSL_FEATURE_IAP_HAS_EEPROM_FUNCTION == 1)) +/*! + * @brief Read EEPROM page. + + * This function is used to read given page of EEPROM into the memory provided. + * + * @param pageNumber EEPROM page number. + * @param dstAddr Memory address to store the value read from EEPROM. + * @param systemCoreClock Current core clock frequency in kHz. + * + * @retval #kStatus_IAP_Success Api was executed successfully. + * @retval #kStatus_IAP_InvalidSector Sector number is invalid. + * @retval #kStatus_IAP_SrcAddrNotMapped Source address is not mapped in the memory map. + * + * @note Value 0xFFFFFFFF of systemCoreClock will retain the timing and clock settings for + * EEPROM] + */ +status_t IAP_ReadEEPROMPage(uint32_t pageNumber, uint32_t *dstAddr, uint32_t systemCoreClock); + +/*! + * @brief Write EEPROM page. + + * This function is used to write given data in the provided memory to a page of EEPROM. + * + * @param pageNumber EEPROM page number. + * @param srcAddr Memory address holding data to be stored on to EEPROM page. + * @param systemCoreClock Current core clock frequency in kHz. + * + * @retval #kStatus_IAP_Success Api was executed successfully. + * @retval #kStatus_IAP_InvalidSector Sector number is invalid. + * @retval #kStatus_IAP_SrcAddrNotMapped Source address is not mapped in the memory map. + * + * @note Value 0xFFFFFFFF of systemCoreClock will retain the timing and clock settings for + * EEPROM] + */ +status_t IAP_WriteEEPROMPage(uint32_t pageNumber, uint32_t *srcAddr, uint32_t systemCoreClock); +#endif /* FSL_FEATURE_IAP_HAS_EEPROM_FUNCTION */ + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* _FSL_IAP_H_ */ diff --git a/ext/hal/nxp/mcux/drivers/lpc/fsl_inputmux.c b/ext/hal/nxp/mcux/drivers/lpc/fsl_inputmux.c index 923585174b0..ff94a6abaed 100644 --- a/ext/hal/nxp/mcux/drivers/lpc/fsl_inputmux.c +++ b/ext/hal/nxp/mcux/drivers/lpc/fsl_inputmux.c @@ -1,31 +1,9 @@ /* * Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP + * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * SPDX-License-Identifier: BSD-3-Clause */ #include "fsl_inputmux.h" @@ -34,17 +12,47 @@ * Definitions ******************************************************************************/ +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.inputmux" +#endif + /******************************************************************************* * Code ******************************************************************************/ +/*! + * brief Initialize INPUTMUX peripheral. + + * This function enables the INPUTMUX clock. + * + * param base Base address of the INPUTMUX peripheral. + * + * retval None. + */ void INPUTMUX_Init(INPUTMUX_Type *base) { #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +#if defined(FSL_FEATURE_INPUTMUX_HAS_NO_INPUTMUX_CLOCK_SOURCE) && FSL_FEATURE_INPUTMUX_HAS_NO_INPUTMUX_CLOCK_SOURCE + CLOCK_EnableClock(kCLOCK_Sct); + CLOCK_EnableClock(kCLOCK_Dma); +#else CLOCK_EnableClock(kCLOCK_InputMux); +#endif /* FSL_FEATURE_INPUTMUX_HAS_NO_INPUTMUX_CLOCK_SOURCE */ #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ } +/*! + * brief Attaches a signal + * + * This function gates the INPUTPMUX clock. + * + * param base Base address of the INPUTMUX peripheral. + * param index Destination peripheral to attach the signal to. + * param connection Selects connection. + * + * retval None. +*/ void INPUTMUX_AttachSignal(INPUTMUX_Type *base, uint32_t index, inputmux_connection_t connection) { uint32_t pmux_id; @@ -58,9 +66,56 @@ void INPUTMUX_AttachSignal(INPUTMUX_Type *base, uint32_t index, inputmux_connect *(volatile uint32_t *)(((uint32_t)base) + pmux_id + (index * 4)) = output_id; } +#if defined(FSL_FEATURE_INPUTMUX_HAS_SIGNAL_ENA) +/*! + * brief Enable/disable a signal + * + * This function gates the INPUTPMUX clock. + * + * param base Base address of the INPUTMUX peripheral. + * param signal Enable signal register id and bit offset. + * param enable Selects enable or disable. + * + * retval None. +*/ +void INPUTMUX_EnableSignal(INPUTMUX_Type *base, inputmux_signal_t signal, bool enable) +{ + uint32_t ena_id; + uint32_t bit_offset; + + /* extract enable register to be used */ + ena_id = ((uint32_t)(signal)) >> ENA_SHIFT; + /* extract enable bit offset */ + bit_offset = ((uint32_t)(signal)) & 0xfU; + /* set signal */ + if (enable) + { + *(volatile uint32_t *)(((uint32_t)base) + ena_id) |= (1U << bit_offset); + } + else + { + *(volatile uint32_t *)(((uint32_t)base) + ena_id) &= ~(1U << bit_offset); + } +} +#endif + +/*! + * brief Deinitialize INPUTMUX peripheral. + + * This function disables the INPUTMUX clock. + * + * param base Base address of the INPUTMUX peripheral. + * + * retval None. + */ void INPUTMUX_Deinit(INPUTMUX_Type *base) { #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +#if defined(FSL_FEATURE_INPUTMUX_HAS_NO_INPUTMUX_CLOCK_SOURCE) && FSL_FEATURE_INPUTMUX_HAS_NO_INPUTMUX_CLOCK_SOURCE + CLOCK_DisableClock(kCLOCK_Sct); + CLOCK_DisableClock(kCLOCK_Dma); +#else CLOCK_DisableClock(kCLOCK_InputMux); +#endif /* FSL_FEATURE_INPUTMUX_HAS_NO_INPUTMUX_CLOCK_SOURCE */ #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ } diff --git a/ext/hal/nxp/mcux/drivers/lpc/fsl_inputmux.h b/ext/hal/nxp/mcux/drivers/lpc/fsl_inputmux.h index 3d298558bcd..4e6412e7ffb 100644 --- a/ext/hal/nxp/mcux/drivers/lpc/fsl_inputmux.h +++ b/ext/hal/nxp/mcux/drivers/lpc/fsl_inputmux.h @@ -1,31 +1,9 @@ /* * Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause */ #ifndef _FSL_INPUTMUX_H_ @@ -84,6 +62,21 @@ void INPUTMUX_Init(INPUTMUX_Type *base); */ void INPUTMUX_AttachSignal(INPUTMUX_Type *base, uint32_t index, inputmux_connection_t connection); +#if defined(FSL_FEATURE_INPUTMUX_HAS_SIGNAL_ENA) +/*! + * @brief Enable/disable a signal + * + * This function gates the INPUTPMUX clock. + * + * @param base Base address of the INPUTMUX peripheral. + * @param signal Enable signal register id and bit offset. + * @param enable Selects enable or disable. + * + * @retval None. +*/ +void INPUTMUX_EnableSignal(INPUTMUX_Type *base, inputmux_signal_t signal, bool enable); +#endif + /*! * @brief Deinitialize INPUTMUX peripheral. diff --git a/ext/hal/nxp/mcux/drivers/lpc/fsl_inputmux_connections.h b/ext/hal/nxp/mcux/drivers/lpc/fsl_inputmux_connections.h index 4c9315093e9..f1de855024d 100644 --- a/ext/hal/nxp/mcux/drivers/lpc/fsl_inputmux_connections.h +++ b/ext/hal/nxp/mcux/drivers/lpc/fsl_inputmux_connections.h @@ -3,30 +3,8 @@ * Copyright (c) 2016, NXP * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * SPDX-License-Identifier: BSD-3-Clause */ #ifndef _FSL_INPUTMUX_CONNECTIONS_ @@ -35,6 +13,10 @@ /******************************************************************************* * Definitions ******************************************************************************/ +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.inputmux_connections" +#endif /*! * @addtogroup inputmux_driver diff --git a/ext/hal/nxp/mcux/drivers/lpc/fsl_iocon.h b/ext/hal/nxp/mcux/drivers/lpc/fsl_iocon.h index f175e959020..1b353547537 100644 --- a/ext/hal/nxp/mcux/drivers/lpc/fsl_iocon.h +++ b/ext/hal/nxp/mcux/drivers/lpc/fsl_iocon.h @@ -1,31 +1,9 @@ /* * Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause */ #ifndef _FSL_IOCON_H_ @@ -44,10 +22,16 @@ * Definitions ******************************************************************************/ +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.lpc_iocon" +#endif + + /*! @name Driver version */ /*@{*/ /*! @brief IOCON driver version 2.0.0. */ -#define LPC_IOCON_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) +#define FSL_IOCON_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*@}*/ /** @@ -57,6 +41,7 @@ typedef struct _iocon_group { uint32_t port : 8; /* Pin port */ uint32_t pin : 8; /* Pin number */ + uint32_t ionumber : 8; /* IO number */ uint32_t modefunc : 16; /* Function and mode */ } iocon_group_t; @@ -64,80 +49,94 @@ typedef struct _iocon_group * @brief IOCON function and mode selection definitions * @note See the User Manual for specific modes and functions supported by the various pins. */ - #if defined(FSL_FEATURE_IOCON_FUNC_FIELD_WIDTH) && (FSL_FEATURE_IOCON_FUNC_FIELD_WIDTH== 4) - #define IOCON_FUNC0 0x0 /*!< Selects pin function 0 */ - #define IOCON_FUNC1 0x1 /*!< Selects pin function 1 */ - #define IOCON_FUNC2 0x2 /*!< Selects pin function 2 */ - #define IOCON_FUNC3 0x3 /*!< Selects pin function 3 */ - #define IOCON_FUNC4 0x4 /*!< Selects pin function 4 */ - #define IOCON_FUNC5 0x5 /*!< Selects pin function 5 */ - #define IOCON_FUNC6 0x6 /*!< Selects pin function 6 */ - #define IOCON_FUNC7 0x7 /*!< Selects pin function 7 */ - #define IOCON_FUNC8 0x8 /*!< Selects pin function 8 */ - #define IOCON_FUNC9 0x9 /*!< Selects pin function 9 */ - #define IOCON_FUNC10 0xA /*!< Selects pin function 10 */ - #define IOCON_FUNC11 0xB /*!< Selects pin function 11 */ - #define IOCON_FUNC12 0xC /*!< Selects pin function 12 */ - #define IOCON_FUNC13 0xD /*!< Selects pin function 13 */ - #define IOCON_FUNC14 0xE /*!< Selects pin function 14 */ - #define IOCON_FUNC15 0xF /*!< Selects pin function 15 */ - #define IOCON_MODE_INACT (0x0 << 4) /*!< No addition pin function */ - #define IOCON_MODE_PULLDOWN (0x1 << 4) /*!< Selects pull-down function */ - #define IOCON_MODE_PULLUP (0x2 << 4) /*!< Selects pull-up function */ - #define IOCON_MODE_REPEATER (0x3 << 4) /*!< Selects pin repeater function */ - #define IOCON_HYS_EN (0x1 << 6) /*!< Enables hysteresis */ - #define IOCON_GPIO_MODE (0x1 << 6) /*!< GPIO Mode */ - #define IOCON_I2C_SLEW (0x1 << 6) /*!< I2C Slew Rate Control */ - #define IOCON_INV_EN (0x1 << 7) /*!< Enables invert function on input */ - #define IOCON_ANALOG_EN (0x0 << 8) /*!< Enables analog function by setting 0 to bit 7 */ - #define IOCON_DIGITAL_EN (0x1 << 8) /*!< Enables digital function by setting 1 to bit 7(default) */ - #define IOCON_STDI2C_EN (0x1 << 9) /*!< I2C standard mode/fast-mode */ - #define IOCON_FASTI2C_EN (0x3 << 9) /*!< I2C Fast-mode Plus and high-speed slave */ - #define IOCON_INPFILT_OFF (0x1 << 9) /*!< Input filter Off for GPIO pins */ - #define IOCON_INPFILT_ON (0x0 << 9) /*!< Input filter On for GPIO pins */ - #define IOCON_OPENDRAIN_EN (0x1 << 11) /*!< Enables open-drain function */ - #define IOCON_S_MODE_0CLK (0x0 << 12) /*!< Bypass input filter */ - #define IOCON_S_MODE_1CLK (0x1 << 12) /*!< Input pulses shorter than 1 filter clock are rejected */ - #define IOCON_S_MODE_2CLK (0x2 << 12) /*!< Input pulses shorter than 2 filter clock2 are rejected */ - #define IOCON_S_MODE_3CLK (0x3 << 12) /*!< Input pulses shorter than 3 filter clock2 are rejected */ - #define IOCON_S_MODE(clks) ((clks) << 12) /*!< Select clocks for digital input filter mode */ - #define IOCON_CLKDIV(div) ((div) << 14) /*!< Select peripheral clock divider for input filter sampling clock, 2^n, n=0-6 */ +#if defined(FSL_FEATURE_IOCON_FUNC_FIELD_WIDTH) && (FSL_FEATURE_IOCON_FUNC_FIELD_WIDTH == 4) +#define IOCON_FUNC0 0x0 /*!< Selects pin function 0 */ +#define IOCON_FUNC1 0x1 /*!< Selects pin function 1 */ +#define IOCON_FUNC2 0x2 /*!< Selects pin function 2 */ +#define IOCON_FUNC3 0x3 /*!< Selects pin function 3 */ +#define IOCON_FUNC4 0x4 /*!< Selects pin function 4 */ +#define IOCON_FUNC5 0x5 /*!< Selects pin function 5 */ +#define IOCON_FUNC6 0x6 /*!< Selects pin function 6 */ +#define IOCON_FUNC7 0x7 /*!< Selects pin function 7 */ +#define IOCON_FUNC8 0x8 /*!< Selects pin function 8 */ +#define IOCON_FUNC9 0x9 /*!< Selects pin function 9 */ +#define IOCON_FUNC10 0xA /*!< Selects pin function 10 */ +#define IOCON_FUNC11 0xB /*!< Selects pin function 11 */ +#define IOCON_FUNC12 0xC /*!< Selects pin function 12 */ +#define IOCON_FUNC13 0xD /*!< Selects pin function 13 */ +#define IOCON_FUNC14 0xE /*!< Selects pin function 14 */ +#define IOCON_FUNC15 0xF /*!< Selects pin function 15 */ +#define IOCON_MODE_INACT (0x0 << 4) /*!< No addition pin function */ +#define IOCON_MODE_PULLDOWN (0x1 << 4) /*!< Selects pull-down function */ +#define IOCON_MODE_PULLUP (0x2 << 4) /*!< Selects pull-up function */ +#define IOCON_MODE_REPEATER (0x3 << 4) /*!< Selects pin repeater function */ +#define IOCON_HYS_EN (0x1 << 6) /*!< Enables hysteresis */ +#define IOCON_GPIO_MODE (0x1 << 6) /*!< GPIO Mode */ +#define IOCON_I2C_SLEW (0x0 << 6) /*!< I2C Slew Rate Control */ +#define IOCON_INV_EN (0x1 << 7) /*!< Enables invert function on input */ +#define IOCON_ANALOG_EN (0x0 << 8) /*!< Enables analog function by setting 0 to bit 7 */ +#define IOCON_DIGITAL_EN (0x1 << 8) /*!< Enables digital function by setting 1 to bit 7(default) */ +#define IOCON_STDI2C_EN (0x1 << 9) /*!< I2C standard mode/fast-mode */ +#define IOCON_FASTI2C_EN (0x3 << 9) /*!< I2C Fast-mode Plus and high-speed slave */ +#define IOCON_INPFILT_OFF (0x1 << 9) /*!< Input filter Off for GPIO pins */ +#define IOCON_INPFILT_ON (0x0 << 9) /*!< Input filter On for GPIO pins */ +#define IOCON_OPENDRAIN_EN (0x1 << 11) /*!< Enables open-drain function */ +#define IOCON_S_MODE_0CLK (0x0 << 12) /*!< Bypass input filter */ +#define IOCON_S_MODE_1CLK (0x1 << 12) /*!< Input pulses shorter than 1 filter clock are rejected */ +#define IOCON_S_MODE_2CLK (0x2 << 12) /*!< Input pulses shorter than 2 filter clock2 are rejected */ +#define IOCON_S_MODE_3CLK (0x3 << 12) /*!< Input pulses shorter than 3 filter clock2 are rejected */ +#define IOCON_S_MODE(clks) ((clks) << 12) /*!< Select clocks for digital input filter mode */ +#define IOCON_CLKDIV(div) \ + ((div) << 14) /*!< Select peripheral clock divider for input filter sampling clock, 2^n, n=0-6 */ #else - #define IOCON_FUNC0 0x0 /*!< Selects pin function 0 */ - #define IOCON_FUNC1 0x1 /*!< Selects pin function 1 */ - #define IOCON_FUNC2 0x2 /*!< Selects pin function 2 */ - #define IOCON_FUNC3 0x3 /*!< Selects pin function 3 */ - #define IOCON_FUNC4 0x4 /*!< Selects pin function 4 */ - #define IOCON_FUNC5 0x5 /*!< Selects pin function 5 */ - #define IOCON_FUNC6 0x6 /*!< Selects pin function 6 */ - #define IOCON_FUNC7 0x7 /*!< Selects pin function 7 */ - #define IOCON_MODE_INACT (0x0 << 3) /*!< No addition pin function */ - #define IOCON_MODE_PULLDOWN (0x1 << 3) /*!< Selects pull-down function */ - #define IOCON_MODE_PULLUP (0x2 << 3) /*!< Selects pull-up function */ - #define IOCON_MODE_REPEATER (0x3 << 3) /*!< Selects pin repeater function */ - #define IOCON_HYS_EN (0x1 << 5) /*!< Enables hysteresis */ - #define IOCON_GPIO_MODE (0x1 << 5) /*!< GPIO Mode */ - #define IOCON_I2C_SLEW (0x1 << 5) /*!< I2C Slew Rate Control */ - #define IOCON_INV_EN (0x1 << 6) /*!< Enables invert function on input */ - #define IOCON_ANALOG_EN (0x0 << 7) /*!< Enables analog function by setting 0 to bit 7 */ - #define IOCON_DIGITAL_EN (0x1 << 7) /*!< Enables digital function by setting 1 to bit 7(default) */ - #define IOCON_STDI2C_EN (0x1 << 8) /*!< I2C standard mode/fast-mode */ - #define IOCON_FASTI2C_EN (0x3 << 8) /*!< I2C Fast-mode Plus and high-speed slave */ - #define IOCON_INPFILT_OFF (0x1 << 8) /*!< Input filter Off for GPIO pins */ - #define IOCON_INPFILT_ON (0x0 << 8) /*!< Input filter On for GPIO pins */ - #define IOCON_OPENDRAIN_EN (0x1 << 10) /*!< Enables open-drain function */ - #define IOCON_S_MODE_0CLK (0x0 << 11) /*!< Bypass input filter */ - #define IOCON_S_MODE_1CLK (0x1 << 11) /*!< Input pulses shorter than 1 filter clock are rejected */ - #define IOCON_S_MODE_2CLK (0x2 << 11) /*!< Input pulses shorter than 2 filter clock2 are rejected */ - #define IOCON_S_MODE_3CLK (0x3 << 11) /*!< Input pulses shorter than 3 filter clock2 are rejected */ - #define IOCON_S_MODE(clks) ((clks) << 11) /*!< Select clocks for digital input filter mode */ - #define IOCON_CLKDIV(div) \ - ((div) << 13) /*!< Select peripheral clock divider for input filter sampling clock, 2^n, n=0-6 */ +#define IOCON_FUNC0 0x0 /*!< Selects pin function 0 */ +#define IOCON_FUNC1 0x1 /*!< Selects pin function 1 */ +#define IOCON_FUNC2 0x2 /*!< Selects pin function 2 */ +#define IOCON_FUNC3 0x3 /*!< Selects pin function 3 */ +#define IOCON_FUNC4 0x4 /*!< Selects pin function 4 */ +#define IOCON_FUNC5 0x5 /*!< Selects pin function 5 */ +#define IOCON_FUNC6 0x6 /*!< Selects pin function 6 */ +#define IOCON_FUNC7 0x7 /*!< Selects pin function 7 */ +#define IOCON_MODE_INACT (0x0 << 3) /*!< No addition pin function */ +#define IOCON_MODE_PULLDOWN (0x1 << 3) /*!< Selects pull-down function */ +#define IOCON_MODE_PULLUP (0x2 << 3) /*!< Selects pull-up function */ +#define IOCON_MODE_REPEATER (0x3 << 3) /*!< Selects pin repeater function */ +#define IOCON_HYS_EN (0x1 << 5) /*!< Enables hysteresis */ +#define IOCON_GPIO_MODE (0x1 << 5) /*!< GPIO Mode */ +#define IOCON_I2C_SLEW (0x0 << 5) /*!< I2C Slew Rate Control */ +#define IOCON_INV_EN (0x1 << 6) /*!< Enables invert function on input */ +#define IOCON_ANALOG_EN (0x0 << 7) /*!< Enables analog function by setting 0 to bit 7 */ +#define IOCON_DIGITAL_EN (0x1 << 7) /*!< Enables digital function by setting 1 to bit 7(default) */ +#define IOCON_STDI2C_EN (0x1 << 8) /*!< I2C standard mode/fast-mode */ +#define IOCON_FASTI2C_EN (0x3 << 8) /*!< I2C Fast-mode Plus and high-speed slave */ +#define IOCON_INPFILT_OFF (0x1 << 8) /*!< Input filter Off for GPIO pins */ +#define IOCON_INPFILT_ON (0x0 << 8) /*!< Input filter On for GPIO pins */ +#define IOCON_OPENDRAIN_EN (0x1 << 10) /*!< Enables open-drain function */ +#define IOCON_S_MODE_0CLK (0x0 << 11) /*!< Bypass input filter */ +#define IOCON_S_MODE_1CLK (0x1 << 11) /*!< Input pulses shorter than 1 filter clock are rejected */ +#define IOCON_S_MODE_2CLK (0x2 << 11) /*!< Input pulses shorter than 2 filter clock2 are rejected */ +#define IOCON_S_MODE_3CLK (0x3 << 11) /*!< Input pulses shorter than 3 filter clock2 are rejected */ +#define IOCON_S_MODE(clks) ((clks) << 11) /*!< Select clocks for digital input filter mode */ +#define IOCON_CLKDIV(div) \ + ((div) << 13) /*!< Select peripheral clock divider for input filter sampling clock, 2^n, n=0-6 */ #endif #if defined(__cplusplus) extern "C" { #endif +#if (defined(FSL_FEATURE_IOCON_ONE_DIMENSION) && (FSL_FEATURE_IOCON_ONE_DIMENSION == 1)) +/** + * @brief Sets I/O Control pin mux + * @param base : The base of IOCON peripheral on the chip + * @param ionumber : GPIO number to mux + * @param modefunc : OR'ed values of type IOCON_* + * @return Nothing + */ +__STATIC_INLINE void IOCON_PinMuxSet(IOCON_Type *base, uint8_t ionumber, uint32_t modefunc) +{ + base->PIO[ionumber] = modefunc; +} +#else /** * @brief Sets I/O Control pin mux * @param base : The base of IOCON peripheral on the chip @@ -150,6 +149,7 @@ __STATIC_INLINE void IOCON_PinMuxSet(IOCON_Type *base, uint8_t port, uint8_t pin { base->PIO[port][pin] = modefunc; } +#endif /** * @brief Set all I/O Control pin muxing @@ -164,7 +164,11 @@ __STATIC_INLINE void IOCON_SetPinMuxing(IOCON_Type *base, const iocon_group_t *p for (i = 0; i < arrayLength; i++) { +#if (defined(FSL_FEATURE_IOCON_ONE_DIMENSION) && (FSL_FEATURE_IOCON_ONE_DIMENSION == 1)) + IOCON_PinMuxSet(base, pinArray[i].ionumber, pinArray[i].modefunc); +#else IOCON_PinMuxSet(base, pinArray[i].port, pinArray[i].pin, pinArray[i].modefunc); +#endif /* FSL_FEATURE_IOCON_ONE_DIMENSION */ } } diff --git a/ext/hal/nxp/mcux/drivers/lpc/fsl_mailbox.h b/ext/hal/nxp/mcux/drivers/lpc/fsl_mailbox.h index 220e79a7127..e2f9ece7d5f 100644 --- a/ext/hal/nxp/mcux/drivers/lpc/fsl_mailbox.h +++ b/ext/hal/nxp/mcux/drivers/lpc/fsl_mailbox.h @@ -1,32 +1,10 @@ /* * Copyright(C) NXP Semiconductors, 2014 * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP + * Copyright 2016-2018 NXP + * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * SPDX-License-Identifier: BSD-3-Clause */ #ifndef _FSL_MAILBOX_H_ @@ -45,21 +23,33 @@ * Definitions *****************************************************************************/ +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.mailbox" +#endif + /*! @name Driver version */ /*@{*/ -/*! @brief MAILBOX driver version 2.0.0. */ -#define FSL_MAILBOX_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) +/*! @brief MAILBOX driver version 2.1.0. */ +#define FSL_MAILBOX_DRIVER_VERSION (MAKE_VERSION(2, 1, 0)) /*@}*/ /*! * @brief CPU ID. */ +#if (defined(LPC55S69_cm33_core0_SERIES) || defined(LPC55S69_cm33_core1_SERIES)) +typedef enum _mailbox_cpu_id +{ + kMAILBOX_CM33_Core1 = 0, + kMAILBOX_CM33_Core0 +} mailbox_cpu_id_t; +#else typedef enum _mailbox_cpu_id { kMAILBOX_CM0Plus = 0, kMAILBOX_CM4 } mailbox_cpu_id_t; - +#endif /******************************************************************************* * API ******************************************************************************/ @@ -85,6 +75,10 @@ static inline void MAILBOX_Init(MAILBOX_Type *base) #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) CLOCK_EnableClock(kCLOCK_Mailbox); #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +#if !(defined(FSL_FEATURE_MAILBOX_HAS_NO_RESET) && FSL_FEATURE_MAILBOX_HAS_NO_RESET) + /* Reset the MAILBOX module */ + RESET_PeripheralReset(kMAILBOX_RST_SHIFT_RSTn); +#endif } /*! @@ -107,14 +101,19 @@ static inline void MAILBOX_Deinit(MAILBOX_Type *base) * @brief Set data value in the mailbox based on the CPU ID. * * @param base MAILBOX peripheral base address. - * @param cpu_id CPU id, kMAILBOX_CM0Plus is M0+ or kMAILBOX_CM4 is M4. + * @param cpu_id CPU id, kMAILBOX_CM0Plus or kMAILBOX_CM4 for LPC5410x and LPC5411x devices, + * kMAILBOX_CM33_Core0 or kMAILBOX_CM33_Core1 for LPC55S69 devices. * @param mboxData Data to send in the mailbox. * * @note Sets a data value to send via the MAILBOX to the other core. */ static inline void MAILBOX_SetValue(MAILBOX_Type *base, mailbox_cpu_id_t cpu_id, uint32_t mboxData) { +#if (defined(LPC55S69_cm33_core0_SERIES) || defined(LPC55S69_cm33_core1_SERIES)) + assert((cpu_id == kMAILBOX_CM33_Core0) || (cpu_id == kMAILBOX_CM33_Core1)); +#else assert((cpu_id == kMAILBOX_CM0Plus) || (cpu_id == kMAILBOX_CM4)); +#endif base->MBOXIRQ[cpu_id].IRQ = mboxData; } @@ -122,13 +121,18 @@ static inline void MAILBOX_SetValue(MAILBOX_Type *base, mailbox_cpu_id_t cpu_id, * @brief Get data in the mailbox based on the CPU ID. * * @param base MAILBOX peripheral base address. - * @param cpu_id CPU id, kMAILBOX_CM0Plus is M0+ or kMAILBOX_CM4 is M4. + * @param cpu_id CPU id, kMAILBOX_CM0Plus or kMAILBOX_CM4 for LPC5410x and LPC5411x devices, + * kMAILBOX_CM33_Core0 or kMAILBOX_CM33_Core1 for LPC55S69 devices. * * @return Current mailbox data. */ static inline uint32_t MAILBOX_GetValue(MAILBOX_Type *base, mailbox_cpu_id_t cpu_id) { +#if (defined(LPC55S69_cm33_core0_SERIES) || defined(LPC55S69_cm33_core1_SERIES)) + assert((cpu_id == kMAILBOX_CM33_Core0) || (cpu_id == kMAILBOX_CM33_Core1)); +#else assert((cpu_id == kMAILBOX_CM0Plus) || (cpu_id == kMAILBOX_CM4)); +#endif return base->MBOXIRQ[cpu_id].IRQ; } @@ -136,7 +140,8 @@ static inline uint32_t MAILBOX_GetValue(MAILBOX_Type *base, mailbox_cpu_id_t cpu * @brief Set data bits in the mailbox based on the CPU ID. * * @param base MAILBOX peripheral base address. - * @param cpu_id CPU id, kMAILBOX_CM0Plus is M0+ or kMAILBOX_CM4 is M4. + * @param cpu_id CPU id, kMAILBOX_CM0Plus or kMAILBOX_CM4 for LPC5410x and LPC5411x devices, + * kMAILBOX_CM33_Core0 or kMAILBOX_CM33_Core1 for LPC55S69 devices. * @param mboxSetBits Data bits to set in the mailbox. * * @note Sets data bits to send via the MAILBOX to the other core. A value of 0 will @@ -144,7 +149,11 @@ static inline uint32_t MAILBOX_GetValue(MAILBOX_Type *base, mailbox_cpu_id_t cpu */ static inline void MAILBOX_SetValueBits(MAILBOX_Type *base, mailbox_cpu_id_t cpu_id, uint32_t mboxSetBits) { +#if (defined(LPC55S69_cm33_core0_SERIES) || defined(LPC55S69_cm33_core1_SERIES)) + assert((cpu_id == kMAILBOX_CM33_Core0) || (cpu_id == kMAILBOX_CM33_Core1)); +#else assert((cpu_id == kMAILBOX_CM0Plus) || (cpu_id == kMAILBOX_CM4)); +#endif base->MBOXIRQ[cpu_id].IRQSET = mboxSetBits; } @@ -152,7 +161,8 @@ static inline void MAILBOX_SetValueBits(MAILBOX_Type *base, mailbox_cpu_id_t cpu * @brief Clear data bits in the mailbox based on the CPU ID. * * @param base MAILBOX peripheral base address. - * @param cpu_id CPU id, kMAILBOX_CM0Plus is M0+ or kMAILBOX_CM4 is M4. + * @param cpu_id CPU id, kMAILBOX_CM0Plus or kMAILBOX_CM4 for LPC5410x and LPC5411x devices, + * kMAILBOX_CM33_Core0 or kMAILBOX_CM33_Core1 for LPC55S69 devices. * @param mboxClrBits Data bits to clear in the mailbox. * * @note Clear data bits to send via the MAILBOX to the other core. A value of 0 will @@ -160,7 +170,11 @@ static inline void MAILBOX_SetValueBits(MAILBOX_Type *base, mailbox_cpu_id_t cpu */ static inline void MAILBOX_ClearValueBits(MAILBOX_Type *base, mailbox_cpu_id_t cpu_id, uint32_t mboxClrBits) { +#if (defined(LPC55S69_cm33_core0_SERIES) || defined(LPC55S69_cm33_core1_SERIES)) + assert((cpu_id == kMAILBOX_CM33_Core0) || (cpu_id == kMAILBOX_CM33_Core1)); +#else assert((cpu_id == kMAILBOX_CM0Plus) || (cpu_id == kMAILBOX_CM4)); +#endif base->MBOXIRQ[cpu_id].IRQCLR = mboxClrBits; } diff --git a/ext/hal/nxp/mcux/drivers/lpc/fsl_mrt.c b/ext/hal/nxp/mcux/drivers/lpc/fsl_mrt.c index cd36ab2b4ac..8306b33e764 100644 --- a/ext/hal/nxp/mcux/drivers/lpc/fsl_mrt.c +++ b/ext/hal/nxp/mcux/drivers/lpc/fsl_mrt.c @@ -1,35 +1,18 @@ /* * Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP + * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * SPDX-License-Identifier: BSD-3-Clause */ #include "fsl_mrt.h" +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.mrt" +#endif + /******************************************************************************* * Prototypes ******************************************************************************/ @@ -53,8 +36,15 @@ static MRT_Type *const s_mrtBases[] = MRT_BASE_PTRS; static const clock_ip_name_t s_mrtClocks[] = MRT_CLOCKS; #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -/*! @brief Pointers to MRT resets for each instance. */ +#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) +#if defined(FSL_FEATURE_MRT_WRITE_ZERO_ASSERT_RESET) && FSL_FEATURE_MRT_WRITE_ZERO_ASSERT_RESET +/*! @brief Pointers to MRT resets for each instance, writing a zero asserts the reset */ +static const reset_ip_name_t s_mrtResets[] = MRT_RSTS_N; +#else +/*! @brief Pointers to MRT resets for each instance, writing a one asserts the reset */ static const reset_ip_name_t s_mrtResets[] = MRT_RSTS; +#endif +#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ /******************************************************************************* * Code @@ -78,6 +68,15 @@ static uint32_t MRT_GetInstance(MRT_Type *base) return instance; } +/*! + * brief Ungates the MRT clock and configures the peripheral for basic operation. + * + * note This API should be called at the beginning of the application using the MRT driver. + * + * param base Multi-Rate timer peripheral base address + * param config Pointer to user's MRT config structure. If MRT has MULTITASK bit field in + * MODCFG reigster, param config is useless. + */ void MRT_Init(MRT_Type *base, const mrt_config_t *config) { assert(config); @@ -87,20 +86,33 @@ void MRT_Init(MRT_Type *base, const mrt_config_t *config) CLOCK_EnableClock(s_mrtClocks[MRT_GetInstance(base)]); #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - /* Reset the module */ +#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) + /* Reset the module. */ RESET_PeripheralReset(s_mrtResets[MRT_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ +#if !(defined(FSL_FEATURE_MRT_HAS_NO_MODCFG_MULTITASK) && FSL_FEATURE_MRT_HAS_NO_MODCFG_MULTITASK) /* Set timer operating mode */ base->MODCFG = MRT_MODCFG_MULTITASK(config->enableMultiTask); +#endif } +/*! + * brief Gate the MRT clock + * + * param base Multi-Rate timer peripheral base address + */ void MRT_Deinit(MRT_Type *base) { /* Stop all the timers */ MRT_StopTimer(base, kMRT_Channel_0); MRT_StopTimer(base, kMRT_Channel_1); +#if (FSL_FEATURE_MRT_NUMBER_OF_CHANNELS > 2U) MRT_StopTimer(base, kMRT_Channel_2); +#endif +#if (FSL_FEATURE_MRT_NUMBER_OF_CHANNELS > 3U) MRT_StopTimer(base, kMRT_Channel_3); +#endif #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) /* Gate the MRT clock*/ @@ -108,8 +120,24 @@ void MRT_Deinit(MRT_Type *base) #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ } +/*! + * brief Used to update the timer period in units of count. + * + * The new value will be immediately loaded or will be loaded at the end of the current time + * interval. For one-shot interrupt mode the new value will be immediately loaded. + * + * note User can call the utility macros provided in fsl_common.h to convert to ticks + * + * param base Multi-Rate timer peripheral base address + * param channel Timer channel number + * param count Timer period in units of ticks + * param immediateLoad true: Load the new value immediately into the TIMER register; + * false: Load the new value at the end of current timer interval + */ void MRT_UpdateTimerPeriod(MRT_Type *base, mrt_chnl_t channel, uint32_t count, bool immediateLoad) { + assert(channel < FSL_FEATURE_MRT_NUMBER_OF_CHANNELS); + uint32_t newValue = count; if (((base->CHANNEL[channel].CTRL & MRT_CHANNEL_CTRL_MODE_MASK) == kMRT_OneShotMode) || (immediateLoad)) { diff --git a/ext/hal/nxp/mcux/drivers/lpc/fsl_mrt.h b/ext/hal/nxp/mcux/drivers/lpc/fsl_mrt.h index 5638bf16755..ea82599ba1c 100644 --- a/ext/hal/nxp/mcux/drivers/lpc/fsl_mrt.h +++ b/ext/hal/nxp/mcux/drivers/lpc/fsl_mrt.h @@ -1,31 +1,9 @@ /* * Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP + * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * SPDX-License-Identifier: BSD-3-Clause */ #ifndef _FSL_MRT_H_ #define _FSL_MRT_H_ @@ -45,7 +23,7 @@ /*! @name Driver version */ /*@{*/ -#define FSL_MRT_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0 */ +#define FSL_MRT_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) /*!< Version 2.0.1 */ /*@}*/ /*! @brief List of MRT channels */ @@ -111,7 +89,8 @@ extern "C" { * @note This API should be called at the beginning of the application using the MRT driver. * * @param base Multi-Rate timer peripheral base address - * @param config Pointer to user's MRT config structure + * @param config Pointer to user's MRT config structure. If MRT has MULTITASK bit field in + * MODCFG reigster, param config is useless. */ void MRT_Init(MRT_Type *base, const mrt_config_t *config); @@ -134,9 +113,10 @@ void MRT_Deinit(MRT_Type *base); static inline void MRT_GetDefaultConfig(mrt_config_t *config) { assert(config); - +#if !(defined(FSL_FEATURE_MRT_HAS_NO_MODCFG_MULTITASK) && FSL_FEATURE_MRT_HAS_NO_MODCFG_MULTITASK) /* Use hardware status operating mode */ config->enableMultiTask = false; +#endif } /*! @@ -148,6 +128,8 @@ static inline void MRT_GetDefaultConfig(mrt_config_t *config) */ static inline void MRT_SetupChannelMode(MRT_Type *base, mrt_chnl_t channel, const mrt_timer_mode_t mode) { + assert(channel < FSL_FEATURE_MRT_NUMBER_OF_CHANNELS); + uint32_t reg = base->CHANNEL[channel].CTRL; /* Clear old value */ @@ -175,6 +157,7 @@ static inline void MRT_SetupChannelMode(MRT_Type *base, mrt_chnl_t channel, cons */ static inline void MRT_EnableInterrupts(MRT_Type *base, mrt_chnl_t channel, uint32_t mask) { + assert(channel < FSL_FEATURE_MRT_NUMBER_OF_CHANNELS); base->CHANNEL[channel].CTRL |= mask; } @@ -188,6 +171,7 @@ static inline void MRT_EnableInterrupts(MRT_Type *base, mrt_chnl_t channel, uint */ static inline void MRT_DisableInterrupts(MRT_Type *base, mrt_chnl_t channel, uint32_t mask) { + assert(channel < FSL_FEATURE_MRT_NUMBER_OF_CHANNELS); base->CHANNEL[channel].CTRL &= ~mask; } @@ -202,6 +186,7 @@ static inline void MRT_DisableInterrupts(MRT_Type *base, mrt_chnl_t channel, uin */ static inline uint32_t MRT_GetEnabledInterrupts(MRT_Type *base, mrt_chnl_t channel) { + assert(channel < FSL_FEATURE_MRT_NUMBER_OF_CHANNELS); return (base->CHANNEL[channel].CTRL & MRT_CHANNEL_CTRL_INTEN_MASK); } @@ -223,6 +208,7 @@ static inline uint32_t MRT_GetEnabledInterrupts(MRT_Type *base, mrt_chnl_t chann */ static inline uint32_t MRT_GetStatusFlags(MRT_Type *base, mrt_chnl_t channel) { + assert(channel < FSL_FEATURE_MRT_NUMBER_OF_CHANNELS); return (base->CHANNEL[channel].STAT & (MRT_CHANNEL_STAT_INTFLAG_MASK | MRT_CHANNEL_STAT_RUN_MASK)); } @@ -236,6 +222,7 @@ static inline uint32_t MRT_GetStatusFlags(MRT_Type *base, mrt_chnl_t channel) */ static inline void MRT_ClearStatusFlags(MRT_Type *base, mrt_chnl_t channel, uint32_t mask) { + assert(channel < FSL_FEATURE_MRT_NUMBER_OF_CHANNELS); base->CHANNEL[channel].STAT = (mask & MRT_CHANNEL_STAT_INTFLAG_MASK); } @@ -277,6 +264,7 @@ void MRT_UpdateTimerPeriod(MRT_Type *base, mrt_chnl_t channel, uint32_t count, b */ static inline uint32_t MRT_GetCurrentTimerCount(MRT_Type *base, mrt_chnl_t channel) { + assert(channel < FSL_FEATURE_MRT_NUMBER_OF_CHANNELS); return base->CHANNEL[channel].TIMER; } @@ -301,6 +289,7 @@ static inline uint32_t MRT_GetCurrentTimerCount(MRT_Type *base, mrt_chnl_t chann */ static inline void MRT_StartTimer(MRT_Type *base, mrt_chnl_t channel, uint32_t count) { + assert(channel < FSL_FEATURE_MRT_NUMBER_OF_CHANNELS); /* Write the timer interval value */ base->CHANNEL[channel].INTVAL = count; } @@ -315,6 +304,7 @@ static inline void MRT_StartTimer(MRT_Type *base, mrt_chnl_t channel, uint32_t c */ static inline void MRT_StopTimer(MRT_Type *base, mrt_chnl_t channel) { + assert(channel < FSL_FEATURE_MRT_NUMBER_OF_CHANNELS); /* Stop the timer immediately */ base->CHANNEL[channel].INTVAL = MRT_CHANNEL_INTVAL_LOAD_MASK; } @@ -338,6 +328,7 @@ static inline uint32_t MRT_GetIdleChannel(MRT_Type *base) return base->IDLE_CH; } +#if !(defined(FSL_FEATURE_MRT_HAS_NO_CHANNEL_STAT_INUSE) && FSL_FEATURE_MRT_HAS_NO_CHANNEL_STAT_INUSE) /*! * @brief Release the channel when the timer is using the multi-task mode. * @@ -351,6 +342,8 @@ static inline uint32_t MRT_GetIdleChannel(MRT_Type *base) */ static inline void MRT_ReleaseChannel(MRT_Type *base, mrt_chnl_t channel) { + assert(channel < FSL_FEATURE_MRT_NUMBER_OF_CHANNELS); + uint32_t reg = base->CHANNEL[channel].STAT; /* Clear flag bits to prevent accidentally clearing anything when writing back */ @@ -359,6 +352,7 @@ static inline void MRT_ReleaseChannel(MRT_Type *base, mrt_chnl_t channel) base->CHANNEL[channel].STAT = reg; } +#endif /*! @}*/ diff --git a/ext/hal/nxp/mcux/drivers/lpc/fsl_pint.c b/ext/hal/nxp/mcux/drivers/lpc/fsl_pint.c index c707a251392..de12bb70ca9 100644 --- a/ext/hal/nxp/mcux/drivers/lpc/fsl_pint.c +++ b/ext/hal/nxp/mcux/drivers/lpc/fsl_pint.c @@ -1,35 +1,18 @@ /* * Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP + * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * SPDX-License-Identifier: BSD-3-Clause */ #include "fsl_pint.h" +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.pint" +#endif + /******************************************************************************* * Variables ******************************************************************************/ @@ -44,6 +27,15 @@ static pint_cb_t s_pintCallback[FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS]; * Code ******************************************************************************/ +/*! + * brief Initialize PINT peripheral. + + * This function initializes the PINT peripheral and enables the clock. + * + * param base Base address of the PINT peripheral. + * + * retval None. + */ void PINT_Init(PINT_Type *base) { uint32_t i; @@ -63,16 +55,56 @@ void PINT_Init(PINT_Type *base) pmcfg = pmcfg | (kPINT_PatternMatchNever << (PININT_BITSLICE_CFG_START + (i * 3U))); } - /* Enable the peripheral clock */ - CLOCK_EnableClock(kCLOCK_Pint); +#if defined(FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE) && (FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE == 1) +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Enable the clock. */ + CLOCK_EnableClock(kCLOCK_GpioInt); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - /* Reset the peripheral */ +#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) + /* Reset the module. */ + RESET_PeripheralReset(kGPIOINT_RST_N_SHIFT_RSTn); +#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ + +#elif defined(FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE) && (FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE == 0) +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Enable the clock. */ + CLOCK_EnableClock(kCLOCK_Gpio0); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) + /* Reset the module. */ + RESET_PeripheralReset(kGPIO0_RST_N_SHIFT_RSTn); +#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ + +#else +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Enable the clock. */ + CLOCK_EnableClock(kCLOCK_Pint); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) + /* Reset the module. */ RESET_PeripheralReset(kPINT_RST_SHIFT_RSTn); +#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ +#endif /* FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE && FSL_FEATURE_CLOCK_HAS_NO_GPIOINT_CLOCK_SOURCE*/ /* Disable all pattern match bit slices */ base->PMCFG = pmcfg; } +/*! + * brief Configure PINT peripheral pin interrupt. + + * This function configures a given pin interrupt. + * + * param base Base address of the PINT peripheral. + * param intr Pin interrupt. + * param enable Selects detection logic. + * param callback Callback. + * + * retval None. + */ void PINT_PinInterruptConfig(PINT_Type *base, pint_pin_int_t intr, pint_pin_enable_t enable, pint_cb_t callback) { assert(base); @@ -107,6 +139,18 @@ void PINT_PinInterruptConfig(PINT_Type *base, pint_pin_int_t intr, pint_pin_enab s_pintCallback[intr] = callback; } +/*! + * brief Get PINT peripheral pin interrupt configuration. + + * This function returns the configuration of a given pin interrupt. + * + * param base Base address of the PINT peripheral. + * param pintr Pin interrupt. + * param enable Pointer to store the detection logic. + * param callback Callback. + * + * retval None. + */ void PINT_PinInterruptGetConfig(PINT_Type *base, pint_pin_int_t pintr, pint_pin_enable_t *enable, pint_cb_t *callback) { uint32_t mask; @@ -164,6 +208,17 @@ void PINT_PinInterruptGetConfig(PINT_Type *base, pint_pin_int_t pintr, pint_pin_ *callback = s_pintCallback[pintr]; } +/*! + * brief Configure PINT pattern match. + + * This function configures a given pattern match bit slice. + * + * param base Base address of the PINT peripheral. + * param bslice Pattern match bit slice number. + * param cfg Pointer to bit slice configuration. + * + * retval None. + */ void PINT_PatternMatchConfig(PINT_Type *base, pint_pmatch_bslice_t bslice, pint_pmatch_cfg_t *cfg) { uint32_t src_shift; @@ -201,6 +256,17 @@ void PINT_PatternMatchConfig(PINT_Type *base, pint_pmatch_bslice_t bslice, pint_ s_pintCallback[bslice] = cfg->callback; } +/*! + * brief Get PINT pattern match configuration. + + * This function returns the configuration of a given pattern match bit slice. + * + * param base Base address of the PINT peripheral. + * param bslice Pattern match bit slice number. + * param cfg Pointer to bit slice configuration. + * + * retval None. + */ void PINT_PatternMatchGetConfig(PINT_Type *base, pint_pmatch_bslice_t bslice, pint_pmatch_cfg_t *cfg) { uint32_t src_shift; @@ -225,6 +291,16 @@ void PINT_PatternMatchGetConfig(PINT_Type *base, pint_pmatch_bslice_t bslice, pi cfg->callback = s_pintCallback[bslice]; } +/*! + * brief Reset pattern match detection logic. + + * This function resets the pattern match detection logic if any of the product term is matching. + * + * param base Base address of the PINT peripheral. + * + * retval pmstatus Each bit position indicates the match status of corresponding bit slice. + * = 0 Match was detected. = 1 Match was not detected. + */ uint32_t PINT_PatternMatchResetDetectLogic(PINT_Type *base) { uint32_t pmctrl; @@ -242,6 +318,16 @@ uint32_t PINT_PatternMatchResetDetectLogic(PINT_Type *base) return (pmstatus); } +/*! + * brief Enable callback. + + * This function enables the interrupt for the selected PINT peripheral. Although the pin(s) are monitored + * as soon as they are enabled, the callback function is not enabled until this function is called. + * + * param base Base address of the PINT peripheral. + * + * retval None. + */ void PINT_EnableCallback(PINT_Type *base) { uint32_t i; @@ -257,6 +343,35 @@ void PINT_EnableCallback(PINT_Type *base) } } +/*! + * brief enable callback by pin index. + + * This function enables callback by pin index instead of enabling all pins. + * + * param base Base address of the peripheral. + * param pinIdx pin index. + * + * retval None. + */ +void PINT_EnableCallbackByIndex(PINT_Type *base, pint_pin_int_t pintIdx) +{ + assert(base); + + NVIC_ClearPendingIRQ(s_pintIRQ[pintIdx]); + PINT_PinInterruptClrStatus(base, (pint_pin_int_t)pintIdx); + EnableIRQ(s_pintIRQ[pintIdx]); +} + +/*! + * brief Disable callback. + + * This function disables the interrupt for the selected PINT peripheral. Although the pins are still + * being monitored but the callback function is not called. + * + * param base Base address of the peripheral. + * + * retval None. + */ void PINT_DisableCallback(PINT_Type *base) { uint32_t i; @@ -271,6 +386,34 @@ void PINT_DisableCallback(PINT_Type *base) } } +/*! + * brief disable callback by pin index. + + * This function disables callback by pin index instead of disabling all pins. + * + * param base Base address of the peripheral. + * param pinIdx pin index. + * + * retval None. + */ +void PINT_DisableCallbackByIndex(PINT_Type *base, pint_pin_int_t pintIdx) +{ + assert(base); + + DisableIRQ(s_pintIRQ[pintIdx]); + PINT_PinInterruptClrStatus(base, (pint_pin_int_t)pintIdx); + NVIC_ClearPendingIRQ(s_pintIRQ[pintIdx]); +} + +/*! + * brief Deinitialize PINT peripheral. + + * This function disables the PINT clock. + * + * param base Base address of the PINT peripheral. + * + * retval None. + */ void PINT_Deinit(PINT_Type *base) { uint32_t i; @@ -284,11 +427,39 @@ void PINT_Deinit(PINT_Type *base) s_pintCallback[i] = NULL; } - /* Reset the peripheral */ - RESET_PeripheralReset(kPINT_RST_SHIFT_RSTn); +#if defined(FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE) && (FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE == 1) +#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) + /* Reset the module. */ + RESET_PeripheralReset(kGPIOINT_RST_N_SHIFT_RSTn); +#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ - /* Disable the peripheral clock */ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Disable the clock. */ + CLOCK_DisableClock(kCLOCK_GpioInt); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#elif defined(FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE) && (FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE == 0) +#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) + /* Reset the module. */ + RESET_PeripheralReset(kGPIO0_RST_N_SHIFT_RSTn); +#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Disable the clock. */ + CLOCK_DisableClock(kCLOCK_Gpio0); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#else +#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) + /* Reset the module. */ + RESET_PeripheralReset(kPINT_RST_SHIFT_RSTn); +#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Disable the clock. */ CLOCK_DisableClock(kCLOCK_Pint); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +#endif /* FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE */ } /* IRQ handler functions overloading weak symbols in the startup */ @@ -298,13 +469,21 @@ void PIN_INT0_DriverIRQHandler(void) /* Reset pattern match detection */ pmstatus = PINT_PatternMatchResetDetectLogic(PINT); - /* Clear Pin interrupt before callback */ - PINT_PinInterruptClrStatus(PINT, kPINT_PinInt0); /* Call user function */ if (s_pintCallback[kPINT_PinInt0] != NULL) { s_pintCallback[kPINT_PinInt0](kPINT_PinInt0, pmstatus); } + if ((PINT->ISEL & 0x1U) == 0x0U) + { + /* Edge sensitive: clear Pin interrupt after callback */ + PINT_PinInterruptClrStatus(PINT, kPINT_PinInt0); + } +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif } #if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 1U) @@ -314,13 +493,21 @@ void PIN_INT1_DriverIRQHandler(void) /* Reset pattern match detection */ pmstatus = PINT_PatternMatchResetDetectLogic(PINT); - /* Clear Pin interrupt before callback */ - PINT_PinInterruptClrStatus(PINT, kPINT_PinInt1); /* Call user function */ if (s_pintCallback[kPINT_PinInt1] != NULL) { s_pintCallback[kPINT_PinInt1](kPINT_PinInt1, pmstatus); } + if ((PINT->ISEL & 0x2U) == 0x0U) + { + /* Edge sensitive: clear Pin interrupt after callback */ + PINT_PinInterruptClrStatus(PINT, kPINT_PinInt1); + } +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif } #endif @@ -331,13 +518,21 @@ void PIN_INT2_DriverIRQHandler(void) /* Reset pattern match detection */ pmstatus = PINT_PatternMatchResetDetectLogic(PINT); - /* Clear Pin interrupt before callback */ - PINT_PinInterruptClrStatus(PINT, kPINT_PinInt2); /* Call user function */ if (s_pintCallback[kPINT_PinInt2] != NULL) { s_pintCallback[kPINT_PinInt2](kPINT_PinInt2, pmstatus); } + if ((PINT->ISEL & 0x4U) == 0x0U) + { + /* Edge sensitive: clear Pin interrupt after callback */ + PINT_PinInterruptClrStatus(PINT, kPINT_PinInt2); + } +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif } #endif @@ -348,13 +543,21 @@ void PIN_INT3_DriverIRQHandler(void) /* Reset pattern match detection */ pmstatus = PINT_PatternMatchResetDetectLogic(PINT); - /* Clear Pin interrupt before callback */ - PINT_PinInterruptClrStatus(PINT, kPINT_PinInt3); /* Call user function */ if (s_pintCallback[kPINT_PinInt3] != NULL) { s_pintCallback[kPINT_PinInt3](kPINT_PinInt3, pmstatus); } + if ((PINT->ISEL & 0x8U) == 0x0U) + { + /* Edge sensitive: clear Pin interrupt after callback */ + PINT_PinInterruptClrStatus(PINT, kPINT_PinInt3); + } +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif } #endif @@ -365,63 +568,107 @@ void PIN_INT4_DriverIRQHandler(void) /* Reset pattern match detection */ pmstatus = PINT_PatternMatchResetDetectLogic(PINT); - /* Clear Pin interrupt before callback */ - PINT_PinInterruptClrStatus(PINT, kPINT_PinInt4); /* Call user function */ if (s_pintCallback[kPINT_PinInt4] != NULL) { s_pintCallback[kPINT_PinInt4](kPINT_PinInt4, pmstatus); } + if ((PINT->ISEL & 0x10U) == 0x0U) + { + /* Edge sensitive: clear Pin interrupt after callback */ + PINT_PinInterruptClrStatus(PINT, kPINT_PinInt4); + } +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif } #endif #if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 5U) +#if defined(FSL_FEATURE_NVIC_HAS_SHARED_INTERTTUPT_NUMBER) && FSL_FEATURE_NVIC_HAS_SHARED_INTERTTUPT_NUMBER +void PIN_INT5_DAC1_IRQHandler(void) +#else void PIN_INT5_DriverIRQHandler(void) +#endif /* FSL_FEATURE_NVIC_HAS_SHARED_INTERTTUPT_NUMBER */ { uint32_t pmstatus; /* Reset pattern match detection */ pmstatus = PINT_PatternMatchResetDetectLogic(PINT); - /* Clear Pin interrupt before callback */ - PINT_PinInterruptClrStatus(PINT, kPINT_PinInt5); /* Call user function */ if (s_pintCallback[kPINT_PinInt5] != NULL) { s_pintCallback[kPINT_PinInt5](kPINT_PinInt5, pmstatus); } + if ((PINT->ISEL & 0x20U) == 0x0U) + { + /* Edge sensitive: clear Pin interrupt after callback */ + PINT_PinInterruptClrStatus(PINT, kPINT_PinInt5); + } +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif } #endif #if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 6U) +#if defined(FSL_FEATURE_NVIC_HAS_SHARED_INTERTTUPT_NUMBER) && FSL_FEATURE_NVIC_HAS_SHARED_INTERTTUPT_NUMBER +void PIN_INT6_USART3_IRQHandler(void) +#else void PIN_INT6_DriverIRQHandler(void) +#endif /* FSL_FEATURE_NVIC_HAS_SHARED_INTERTTUPT_NUMBER */ { uint32_t pmstatus; /* Reset pattern match detection */ pmstatus = PINT_PatternMatchResetDetectLogic(PINT); - /* Clear Pin interrupt before callback */ - PINT_PinInterruptClrStatus(PINT, kPINT_PinInt6); /* Call user function */ if (s_pintCallback[kPINT_PinInt6] != NULL) { s_pintCallback[kPINT_PinInt6](kPINT_PinInt6, pmstatus); } + if ((PINT->ISEL & 0x40U) == 0x0U) + { + /* Edge sensitive: clear Pin interrupt after callback */ + PINT_PinInterruptClrStatus(PINT, kPINT_PinInt6); + } +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif } #endif #if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 7U) +#if defined(FSL_FEATURE_NVIC_HAS_SHARED_INTERTTUPT_NUMBER) && FSL_FEATURE_NVIC_HAS_SHARED_INTERTTUPT_NUMBER +void PIN_INT7_USART4_IRQHandler(void) +#else void PIN_INT7_DriverIRQHandler(void) +#endif /* FSL_FEATURE_NVIC_HAS_SHARED_INTERTTUPT_NUMBER */ { uint32_t pmstatus; /* Reset pattern match detection */ pmstatus = PINT_PatternMatchResetDetectLogic(PINT); - /* Clear Pin interrupt before callback */ - PINT_PinInterruptClrStatus(PINT, kPINT_PinInt7); /* Call user function */ if (s_pintCallback[kPINT_PinInt7] != NULL) { s_pintCallback[kPINT_PinInt7](kPINT_PinInt7, pmstatus); } + if ((PINT->ISEL & 0x80U) == 0x0U) + { + /* Edge sensitive: clear Pin interrupt after callback */ + PINT_PinInterruptClrStatus(PINT, kPINT_PinInt7); + } +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif } #endif diff --git a/ext/hal/nxp/mcux/drivers/lpc/fsl_pint.h b/ext/hal/nxp/mcux/drivers/lpc/fsl_pint.h index ae3ce30428c..cfa1e7dbe4d 100644 --- a/ext/hal/nxp/mcux/drivers/lpc/fsl_pint.h +++ b/ext/hal/nxp/mcux/drivers/lpc/fsl_pint.h @@ -1,31 +1,9 @@ /* * Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP + * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * SPDX-License-Identifier: BSD-3-Clause */ #ifndef _FSL_PINT_H_ @@ -46,7 +24,7 @@ /*! @name Driver version */ /*@{*/ -#define FSL_PINT_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0 */ +#define FSL_PINT_DRIVER_VERSION (MAKE_VERSION(2, 0, 2)) /*!< Version 2.0.2 */ /*@}*/ /* Number of interrupt line supported by PINT */ @@ -559,6 +537,30 @@ void PINT_DisableCallback(PINT_Type *base); */ void PINT_Deinit(PINT_Type *base); +/*! + * @brief enable callback by pin index. + + * This function enables callback by pin index instead of enabling all pins. + * + * @param base Base address of the peripheral. + * @param pinIdx pin index. + * + * @retval None. + */ +void PINT_EnableCallbackByIndex(PINT_Type *base, pint_pin_int_t pintIdx); + +/*! + * @brief disable callback by pin index. + + * This function disables callback by pin index instead of disabling all pins. + * + * @param base Base address of the peripheral. + * @param pinIdx pin index. + * + * @retval None. + */ +void PINT_DisableCallbackByIndex(PINT_Type *base, pint_pin_int_t pintIdx); + #ifdef __cplusplus } #endif diff --git a/ext/hal/nxp/mcux/drivers/lpc/fsl_power.c b/ext/hal/nxp/mcux/drivers/lpc/fsl_power.c index 69b53d1f604..d95008496a7 100644 --- a/ext/hal/nxp/mcux/drivers/lpc/fsl_power.c +++ b/ext/hal/nxp/mcux/drivers/lpc/fsl_power.c @@ -3,33 +3,15 @@ * Copyright (c) 2016, NXP * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * SPDX-License-Identifier: BSD-3-Clause */ #include "fsl_common.h" #include "fsl_power.h" +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.power" +#endif /******************************************************************************* * Code diff --git a/ext/hal/nxp/mcux/drivers/lpc/fsl_power.h b/ext/hal/nxp/mcux/drivers/lpc/fsl_power.h index 30353aaf9f8..ce397f6c431 100644 --- a/ext/hal/nxp/mcux/drivers/lpc/fsl_power.h +++ b/ext/hal/nxp/mcux/drivers/lpc/fsl_power.h @@ -3,30 +3,8 @@ * Copyright (c) 2016, NXP * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * SPDX-License-Identifier: BSD-3-Clause */ #ifndef _FSL_POWER_H_ #define _FSL_POWER_H_ @@ -42,7 +20,13 @@ * Definitions ******************************************************************************/ -#define MAKE_PD_BITS(reg, slot) ((reg << 8) | slot) +/*! @name Driver version */ +/*@{*/ +/*! @brief power driver version 2.0.0. */ +#define FSL_POWER_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) +/*@}*/ + +#define MAKE_PD_BITS(reg, slot) (((reg) << 8) | (slot)) #define PDRCFG0 0x0U #define PDRCFG1 0x1U @@ -71,8 +55,12 @@ typedef enum pd_bits kPDRUNCFG_PD_ALT_FLASH_IBG = MAKE_PD_BITS(PDRCFG1, 28U), kPDRUNCFG_SEL_ALT_FLASH_IBG = MAKE_PD_BITS(PDRCFG1, 29U), - - kPDRUNCFG_ForceUnsigned = 0x80000000U + + /* + This enum member has no practical meaning,it is used to avoid MISRA issue, + user should not trying to use it. + */ + kPDRUNCFG_ForceUnsigned = (int)0x80000000U } pd_bit_t; /* Power mode configuration API parameter */ @@ -148,13 +136,16 @@ static inline void POWER_DisableDeepSleep(void) static inline void POWER_PowerDownFlash(void) { /* note, we retain flash trim to make waking back up faster */ - SYSCON->PDRUNCFGSET[0] = SYSCON_PDRUNCFG_LP_VDDFLASH_MASK | SYSCON_PDRUNCFG_PD_VDDHV_ENA_MASK | SYSCON_PDRUNCFG_PD_FLASH_BG_MASK; + SYSCON->PDRUNCFGSET[0] = + SYSCON_PDRUNCFG_LP_VDDFLASH_MASK | SYSCON_PDRUNCFG_PD_VDDHV_ENA_MASK | SYSCON_PDRUNCFG_PD_FLASH_BG_MASK; +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) /* TURN OFF clock for Flash Controller (only needed for FLASH programming, will be turned on by ROM API) */ CLOCK_DisableClock(kCLOCK_Flash); /* TURN OFF clock for Flash Accelerator */ CLOCK_DisableClock(kCLOCK_Fmc); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ } /*! @@ -166,8 +157,13 @@ static inline void POWER_PowerUpFlash(void) { SYSCON->PDRUNCFGCLR[0] = SYSCON_PDRUNCFG_LP_VDDFLASH_MASK | SYSCON_PDRUNCFG_PD_VDDHV_ENA_MASK; - /* TURN ON clock for flash controller */ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* TURN ON clock for flash Accelerator */ CLOCK_EnableClock(kCLOCK_Fmc); + + /* TURN ON clock for flash Controller */ + CLOCK_EnableClock(kCLOCK_Flash); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ } /*! @@ -185,7 +181,6 @@ void POWER_EnterPowerMode(power_mode_cfg_t mode, uint64_t exclude_from_pd); */ void POWER_EnterSleep(void); - /*! * @brief Power Library API to enter deep sleep mode. * @@ -197,7 +192,7 @@ void POWER_EnterDeepSleep(uint64_t exclude_from_pd); /*! * @brief Power Library API to enter deep power down mode. * - * @param exclude_from_pd Bit mask of the PDRUNCFG bits that needs to be powered on during deep power down mode, + * @param exclude_from_pd Bit mask of the PDRUNCFG bits that needs to be powered on during deep power down mode, * but this is has no effect as the voltages are cut off. * @return none */ @@ -206,7 +201,7 @@ void POWER_EnterDeepPowerDown(uint64_t exclude_from_pd); /*! * @brief Power Library API to choose normal regulation and set the voltage for the desired operating frequency. * - * @param freq - The desired frequency at which the part would like to operate, + * @param freq - The desired frequency at which the part would like to operate, * note that the voltage and flash wait states should be set before changing frequency * @return none */ @@ -215,7 +210,7 @@ void POWER_SetVoltageForFreq(uint32_t freq); /*! * @brief Power Library API to choose low power regulation and set the voltage for the desired operating frequency. * - * @param freq - The desired frequency at which the part would like to operate, + * @param freq - The desired frequency at which the part would like to operate, * note only 12MHz and 48Mhz are supported * @return none */ diff --git a/ext/hal/nxp/mcux/drivers/lpc/fsl_reset.c b/ext/hal/nxp/mcux/drivers/lpc/fsl_reset.c index 07a9ed9e2fc..8b0e02fdd9c 100644 --- a/ext/hal/nxp/mcux/drivers/lpc/fsl_reset.c +++ b/ext/hal/nxp/mcux/drivers/lpc/fsl_reset.c @@ -3,30 +3,8 @@ * Copyright (c) 2016, NXP * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * SPDX-License-Identifier: BSD-3-Clause */ #include "fsl_common.h" @@ -35,6 +13,10 @@ /******************************************************************************* * Definitions ******************************************************************************/ +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.reset" +#endif /******************************************************************************* * Variables @@ -51,6 +33,14 @@ #if ((defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0)) || \ (defined(FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT) && (FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT > 0))) +/*! + * brief Assert reset to peripheral. + * + * Asserts reset signal to specified peripheral module. + * + * param peripheral Assert reset to this peripheral. The enum argument contains encoding of reset register + * and reset bit position in the reset register. + */ void RESET_SetPeripheralReset(reset_ip_name_t peripheral) { const uint32_t regIndex = ((uint32_t)peripheral & 0xFFFF0000u) >> 16; @@ -84,6 +74,14 @@ void RESET_SetPeripheralReset(reset_ip_name_t peripheral) } } +/*! + * brief Clear reset to peripheral. + * + * Clears reset signal to specified peripheral module, allows it to operate. + * + * param peripheral Clear reset to this peripheral. The enum argument contains encoding of reset register + * and reset bit position in the reset register. + */ void RESET_ClearPeripheralReset(reset_ip_name_t peripheral) { const uint32_t regIndex = ((uint32_t)peripheral & 0xFFFF0000u) >> 16; @@ -117,10 +115,71 @@ void RESET_ClearPeripheralReset(reset_ip_name_t peripheral) } } +/*! + * brief Reset peripheral module. + * + * Reset peripheral module. + * + * param peripheral Peripheral to reset. The enum argument contains encoding of reset register + * and reset bit position in the reset register. + */ void RESET_PeripheralReset(reset_ip_name_t peripheral) { RESET_SetPeripheralReset(peripheral); RESET_ClearPeripheralReset(peripheral); } +/*! + * brief Set slave core to reset state and hold. + */ +void RESET_SetSlaveCoreReset(void) +{ + uint32_t cpuctrl = (SYSCON->CPUCTRL & ~0x7F80U) | 0xC0C48000U; + + /* CM4 is the master. */ + if (cpuctrl & SYSCON_CPUCTRL_MASTERCPU_MASK) + { + SYSCON->CPUCTRL = cpuctrl | SYSCON_CPUCTRL_CM0RSTEN_MASK; + } + /* CM0 is the master. */ + else + { + SYSCON->CPUCTRL = cpuctrl | SYSCON_CPUCTRL_CM4RSTEN_MASK; + } +} + +/*! + * brief Release slave core from reset state. + */ +void RESET_ClearSlaveCoreReset(void) +{ + uint32_t cpuctrl = (SYSCON->CPUCTRL & ~0x7F80U) | 0xC0C48000U; + + /* CM4 is the master. */ + if (cpuctrl & SYSCON_CPUCTRL_MASTERCPU_MASK) + { + SYSCON->CPUCTRL = cpuctrl & ~SYSCON_CPUCTRL_CM0RSTEN_MASK; + } + /* CM0 is the master. */ + else + { + SYSCON->CPUCTRL = cpuctrl & ~SYSCON_CPUCTRL_CM4RSTEN_MASK; + } +} + +/*! + * brief Reset slave core with the boot entry. + */ +void RESET_SlaveCoreReset(uint32_t bootAddr, uint32_t bootStackPointer) +{ + volatile uint32_t i = 10U; + + SYSCON->CPSTACK = bootStackPointer; + SYSCON->CPBOOT = bootAddr; + + RESET_SetSlaveCoreReset(); + while(i--){} + RESET_ClearSlaveCoreReset(); +} + #endif /* FSL_FEATURE_SOC_SYSCON_COUNT || FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT */ diff --git a/ext/hal/nxp/mcux/drivers/lpc/fsl_reset.h b/ext/hal/nxp/mcux/drivers/lpc/fsl_reset.h index 7765da5c0c1..9a8fff03735 100644 --- a/ext/hal/nxp/mcux/drivers/lpc/fsl_reset.h +++ b/ext/hal/nxp/mcux/drivers/lpc/fsl_reset.h @@ -3,30 +3,8 @@ * Copyright (c) 2016, NXP * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * SPDX-License-Identifier: BSD-3-Clause */ #ifndef _FSL_RESET_H_ @@ -47,6 +25,12 @@ * Definitions ******************************************************************************/ +/*! @name Driver version */ +/*@{*/ +/*! @brief reset driver version 2.0.1. */ +#define FSL_RESET_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) +/*@}*/ + /*! * @brief Enumeration for peripheral reset control bits * @@ -95,7 +79,7 @@ typedef enum _SYSCON_RSTn { \ kCRC_RST_SHIFT_RSTn \ } /* Reset bits for CRC peripheral */ -#define DMA_RSTS \ +#define DMA_RSTS_N \ { \ kDMA_RST_SHIFT_RSTn \ } /* Reset bits for DMA peripheral */ @@ -112,7 +96,7 @@ typedef enum _SYSCON_RSTn { \ kGINT_RST_SHIFT_RSTn, kGINT_RST_SHIFT_RSTn \ } /* Reset bits for GINT peripheral. GINT0 & GINT1 share same slot */ -#define GPIO_RSTS \ +#define GPIO_RSTS_N \ { \ kGPIO0_RST_SHIFT_RSTn, kGPIO1_RST_SHIFT_RSTn \ } /* Reset bits for GPIO peripheral */ @@ -197,6 +181,21 @@ void RESET_ClearPeripheralReset(reset_ip_name_t peripheral); */ void RESET_PeripheralReset(reset_ip_name_t peripheral); +/*! + * @brief Set slave core to reset state and hold. + */ +void RESET_SetSlaveCoreReset(void); + +/*! + * @brief Release slave core from reset state. + */ +void RESET_ClearSlaveCoreReset(void); + +/*! + * @brief Reset slave core with the boot entry. + */ +void RESET_SlaveCoreReset(uint32_t bootAddr, uint32_t bootStackPointer); + #if defined(__cplusplus) } #endif diff --git a/ext/hal/nxp/mcux/drivers/lpc/fsl_rtc.c b/ext/hal/nxp/mcux/drivers/lpc/fsl_rtc.c index 4165af84e3f..b9eedeec6c7 100644 --- a/ext/hal/nxp/mcux/drivers/lpc/fsl_rtc.c +++ b/ext/hal/nxp/mcux/drivers/lpc/fsl_rtc.c @@ -1,31 +1,9 @@ /* * Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP + * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * SPDX-License-Identifier: BSD-3-Clause */ #include "fsl_rtc.h" @@ -33,6 +11,12 @@ /******************************************************************************* * Definitions ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.lpc_rtc" +#endif + #define SECONDS_IN_A_DAY (86400U) #define SECONDS_IN_A_HOUR (3600U) #define SECONDS_IN_A_MINUTE (60U) @@ -205,6 +189,13 @@ static void RTC_ConvertSecondsToDatetime(uint32_t seconds, rtc_datetime_t *datet datetime->day = days; } +/*! + * brief Ungates the RTC clock and enables the RTC oscillator. + * + * note This API should be called at the beginning of the application using the RTC driver. + * + * param base RTC peripheral base address + */ void RTC_Init(RTC_Type *base) { #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) @@ -212,13 +203,30 @@ void RTC_Init(RTC_Type *base) CLOCK_EnableClock(kCLOCK_Rtc); #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +#if !(defined(FSL_FEATURE_RTC_HAS_NO_RESET) && FSL_FEATURE_RTC_HAS_NO_RESET) + RESET_PeripheralReset(kRTC_RST_SHIFT_RSTn); +#endif /* Make sure the reset bit is cleared */ base->CTRL &= ~RTC_CTRL_SWRESET_MASK; +#if !(defined(FSL_FEATURE_RTC_HAS_NO_OSC_PD) && FSL_FEATURE_RTC_HAS_NO_OSC_PD) /* Make sure the RTC OSC is powered up */ base->CTRL &= ~RTC_CTRL_RTC_OSC_PD_MASK; +#endif } +/*! + * brief Sets the RTC date and time according to the given time structure. + * + * The RTC counter must be stopped prior to calling this function as writes to the RTC + * seconds register will fail if the RTC counter is running. + * + * param base RTC peripheral base address + * param datetime Pointer to structure where the date and time details to set are stored + * + * return kStatus_Success: Success in setting the time and starting the RTC + * kStatus_InvalidArgument: Error because the datetime format is incorrect + */ status_t RTC_SetDatetime(RTC_Type *base, const rtc_datetime_t *datetime) { assert(datetime); @@ -235,6 +243,12 @@ status_t RTC_SetDatetime(RTC_Type *base, const rtc_datetime_t *datetime) return kStatus_Success; } +/*! + * brief Gets the RTC time and stores it in the given time structure. + * + * param base RTC peripheral base address + * param datetime Pointer to structure where the date and time details are stored. + */ void RTC_GetDatetime(RTC_Type *base, rtc_datetime_t *datetime) { assert(datetime); @@ -245,6 +259,19 @@ void RTC_GetDatetime(RTC_Type *base, rtc_datetime_t *datetime) RTC_ConvertSecondsToDatetime(seconds, datetime); } +/*! + * brief Sets the RTC alarm time + * + * The function checks whether the specified alarm time is greater than the present + * time. If not, the function does not set the alarm and returns an error. + * + * param base RTC peripheral base address + * param alarmTime Pointer to structure where the alarm time is stored. + * + * return kStatus_Success: success in setting the RTC alarm + * kStatus_InvalidArgument: Error because the alarm datetime format is incorrect + * kStatus_Fail: Error because the alarm time has already passed + */ status_t RTC_SetAlarm(RTC_Type *base, const rtc_datetime_t *alarmTime) { assert(alarmTime); @@ -275,6 +302,12 @@ status_t RTC_SetAlarm(RTC_Type *base, const rtc_datetime_t *alarmTime) return kStatus_Success; } +/*! + * brief Returns the RTC alarm time. + * + * param base RTC peripheral base address + * param datetime Pointer to structure where the alarm date and time details are stored. + */ void RTC_GetAlarm(RTC_Type *base, rtc_datetime_t *datetime) { assert(datetime); diff --git a/ext/hal/nxp/mcux/drivers/lpc/fsl_rtc.h b/ext/hal/nxp/mcux/drivers/lpc/fsl_rtc.h index 83c5ba85496..fb9f8509283 100644 --- a/ext/hal/nxp/mcux/drivers/lpc/fsl_rtc.h +++ b/ext/hal/nxp/mcux/drivers/lpc/fsl_rtc.h @@ -1,31 +1,9 @@ /* * Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause */ #ifndef _FSL_RTC_H_ #define _FSL_RTC_H_ diff --git a/ext/hal/nxp/mcux/drivers/lpc/fsl_sctimer.c b/ext/hal/nxp/mcux/drivers/lpc/fsl_sctimer.c index 22f9d3df138..373402b590b 100644 --- a/ext/hal/nxp/mcux/drivers/lpc/fsl_sctimer.c +++ b/ext/hal/nxp/mcux/drivers/lpc/fsl_sctimer.c @@ -1,31 +1,9 @@ /* * Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP + * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * SPDX-License-Identifier: BSD-3-Clause */ #include "fsl_sctimer.h" @@ -33,6 +11,12 @@ /******************************************************************************* * Definitions ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.sctimer" +#endif + /*! @brief Typedef for interrupt handler. */ typedef void (*sctimer_isr_t)(SCT_Type *base); @@ -59,8 +43,15 @@ static SCT_Type *const s_sctBases[] = SCT_BASE_PTRS; static const clock_ip_name_t s_sctClocks[] = SCT_CLOCKS; #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -/*! @brief Pointers to SCT resets for each instance. */ +#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) +#if defined(FSL_FEATURE_SCT_WRITE_ZERO_ASSERT_RESET) && FSL_FEATURE_SCT_WRITE_ZERO_ASSERT_RESET +/*! @brief Pointers to SCT resets for each instance, writing a zero asserts the reset */ +static const reset_ip_name_t s_sctResets[] = SCT_RSTS_N; +#else +/*! @brief Pointers to SCT resets for each instance, writing a one asserts the reset */ static const reset_ip_name_t s_sctResets[] = SCT_RSTS; +#endif +#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ /*!< @brief SCTimer event Callback function. */ static sctimer_event_callback_t s_eventCallback[FSL_FEATURE_SCT_NUMBER_OF_EVENTS]; @@ -99,6 +90,16 @@ static uint32_t SCTIMER_GetInstance(SCT_Type *base) return instance; } +/*! + * brief Ungates the SCTimer clock and configures the peripheral for basic operation. + * + * note This API should be called at the beginning of the application using the SCTimer driver. + * + * param base SCTimer peripheral base address + * param config Pointer to the user configuration structure. + * + * return kStatus_Success indicates success; Else indicates failure. + */ status_t SCTIMER_Init(SCT_Type *base, const sctimer_config_t *config) { assert(config); @@ -109,8 +110,10 @@ status_t SCTIMER_Init(SCT_Type *base, const sctimer_config_t *config) CLOCK_EnableClock(s_sctClocks[SCTIMER_GetInstance(base)]); #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - /* Reset the module */ +#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) + /* Reset the module. */ RESET_PeripheralReset(s_sctResets[SCTIMER_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ /* Setup the counter operation */ base->CONFIG = SCT_CONFIG_CKSEL(config->clockSelect) | SCT_CONFIG_CLKMODE(config->clockMode) | @@ -146,6 +149,11 @@ status_t SCTIMER_Init(SCT_Type *base, const sctimer_config_t *config) return kStatus_Success; } +/*! + * brief Gates the SCTimer clock. + * + * param base SCTimer peripheral base address + */ void SCTIMER_Deinit(SCT_Type *base) { /* Halt the counters */ @@ -157,10 +165,29 @@ void SCTIMER_Deinit(SCT_Type *base) #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ } +/*! + * brief Fills in the SCTimer configuration structure with the default settings. + * + * The default values are: + * code + * config->enableCounterUnify = true; + * config->clockMode = kSCTIMER_System_ClockMode; + * config->clockSelect = kSCTIMER_Clock_On_Rise_Input_0; + * config->enableBidirection_l = false; + * config->enableBidirection_h = false; + * config->prescale_l = 0; + * config->prescale_h = 0; + * config->outInitState = 0; + * endcode + * param config Pointer to the user configuration structure. + */ void SCTIMER_GetDefaultConfig(sctimer_config_t *config) { assert(config); + /* Initializes the configure structure to zero. */ + memset(config, 0, sizeof(*config)); + /* SCT operates as a unified 32-bit counter */ config->enableCounterUnify = true; /* System clock clocks the entire SCT module */ @@ -179,6 +206,35 @@ void SCTIMER_GetDefaultConfig(sctimer_config_t *config) config->outInitState = 0; } +/*! + * brief Configures the PWM signal parameters. + * + * Call this function to configure the PWM signal period, mode, duty cycle, and edge. This + * function will create 2 events; one of the events will trigger on match with the pulse value + * and the other will trigger when the counter matches the PWM period. The PWM period event is + * also used as a limit event to reset the counter or change direction. Both events are enabled + * for the same state. The state number can be retrieved by calling the function + * SCTIMER_GetCurrentStateNumber(). + * The counter is set to operate as one 32-bit counter (unify bit is set to 1). + * The counter operates in bi-directional mode when generating a center-aligned PWM. + * + * note When setting PWM output from multiple output pins, they all should use the same PWM mode + * i.e all PWM's should be either edge-aligned or center-aligned. + * When using this API, the PWM signal frequency of all the initialized channels must be the same. + * Otherwise all the initialized channels' PWM signal frequency is equal to the last call to the + * API's pwmFreq_Hz. + * + * param base SCTimer peripheral base address + * param pwmParams PWM parameters to configure the output + * param mode PWM operation mode, options available in enumeration ::sctimer_pwm_mode_t + * param pwmFreq_Hz PWM signal frequency in Hz + * param srcClock_Hz SCTimer counter clock in Hz + * param event Pointer to a variable where the PWM period event number is stored + * + * return kStatus_Success on success + * kStatus_Fail If we have hit the limit in terms of number of events created or if + * an incorrect PWM dutycylce is passed in. + */ status_t SCTIMER_SetupPwm(SCT_Type *base, const sctimer_pwm_signal_param_t *pwmParams, sctimer_pwm_mode_t mode, @@ -189,10 +245,11 @@ status_t SCTIMER_SetupPwm(SCT_Type *base, assert(pwmParams); assert(srcClock_Hz); assert(pwmFreq_Hz); + assert(pwmParams->output < FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS); uint32_t period, pulsePeriod = 0; uint32_t sctClock = srcClock_Hz / (((base->CTRL & SCT_CTRL_PRE_L_MASK) >> SCT_CTRL_PRE_L_SHIFT) + 1); - uint32_t periodEvent, pulseEvent; + uint32_t periodEvent = 0, pulseEvent = 0; uint32_t reg; /* This function will create 2 events, return an error if we do not have enough events available */ @@ -298,10 +355,20 @@ status_t SCTIMER_SetupPwm(SCT_Type *base, return kStatus_Success; } +/*! + * brief Updates the duty cycle of an active PWM signal. + * + * param base SCTimer peripheral base address + * param output The output to configure + * param dutyCyclePercent New PWM pulse width; the value should be between 1 to 100 + * param event Event number associated with this PWM signal. This was returned to the user by the + * function SCTIMER_SetupPwm(). + */ void SCTIMER_UpdatePwmDutycycle(SCT_Type *base, sctimer_out_t output, uint8_t dutyCyclePercent, uint32_t event) { assert(dutyCyclePercent > 0); + assert(output < FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS); uint32_t periodMatchReg, pulseMatchReg; uint32_t pulsePeriod = 0, period; @@ -334,6 +401,29 @@ void SCTIMER_UpdatePwmDutycycle(SCT_Type *base, sctimer_out_t output, uint8_t du SCTIMER_StartTimer(base, kSCTIMER_Counter_L); } +/*! + * brief Create an event that is triggered on a match or IO and schedule in current state. + * + * This function will configure an event using the options provided by the user. If the event type uses + * the counter match, then the function will set the user provided match value into a match register + * and put this match register number into the event control register. + * The event is enabled for the current state and the event number is increased by one at the end. + * The function returns the event number; this event number can be used to configure actions to be + * done when this event is triggered. + * + * param base SCTimer peripheral base address + * param howToMonitor Event type; options are available in the enumeration ::sctimer_interrupt_enable_t + * param matchValue The match value that will be programmed to a match register + * param whichIO The input or output that will be involved in event triggering. This field + * is ignored if the event type is "match only" + * param whichCounter SCTimer counter to use when operating in 16-bit mode. In 32-bit mode, this + * field has no meaning as we have only 1 unified counter; hence ignored. + * param event Pointer to a variable where the new event number is stored + * + * return kStatus_Success on success + * kStatus_Error if we have hit the limit in terms of number of events created or + if we have reached the limit in terms of number of match registers + */ status_t SCTIMER_CreateAndScheduleEvent(SCT_Type *base, sctimer_event_t howToMonitor, uint32_t matchValue, @@ -422,12 +512,35 @@ status_t SCTIMER_CreateAndScheduleEvent(SCT_Type *base, return kStatus_Success; } +/*! + * brief Enable an event in the current state. + * + * This function will allow the event passed in to trigger in the current state. The event must + * be created earlier by either calling the function SCTIMER_SetupPwm() or function + * SCTIMER_CreateAndScheduleEvent() . + * + * param base SCTimer peripheral base address + * param event Event number to enable in the current state + * + */ void SCTIMER_ScheduleEvent(SCT_Type *base, uint32_t event) { /* Enable event in the current state */ base->EVENT[event].STATE |= (1U << s_currentState); } +/*! + * brief Increase the state by 1 + * + * All future events created by calling the function SCTIMER_ScheduleEvent() will be enabled in this new + * state. + * + * param base SCTimer peripheral base address + * + * return kStatus_Success on success + * kStatus_Error if we have hit the limit in terms of states used + + */ status_t SCTIMER_IncreaseState(SCT_Type *base) { /* Return an error if we have hit the limit in terms of states used */ @@ -441,13 +554,33 @@ status_t SCTIMER_IncreaseState(SCT_Type *base) return kStatus_Success; } +/*! + * brief Provides the current state + * + * User can use this to set the next state by calling the function SCTIMER_SetupNextStateAction(). + * + * param base SCTimer peripheral base address + * + * return The current state + */ uint32_t SCTIMER_GetCurrentState(SCT_Type *base) { return s_currentState; } +/*! + * brief Toggle the output level. + * + * This change in the output level is triggered by the event number that is passed in by the user. + * + * param base SCTimer peripheral base address + * param whichIO The output to toggle + * param event Event number that will trigger the output change + */ void SCTIMER_SetupOutputToggleAction(SCT_Type *base, uint32_t whichIO, uint32_t event) { + assert(whichIO < FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS); + uint32_t reg; /* Set the same event to set and clear the output */ @@ -461,6 +594,19 @@ void SCTIMER_SetupOutputToggleAction(SCT_Type *base, uint32_t whichIO, uint32_t base->RES = reg; } +/*! + * brief Setup capture of the counter value on trigger of a selected event + * + * param base SCTimer peripheral base address + * param whichCounter SCTimer counter to use when operating in 16-bit mode. In 32-bit mode, this + * field has no meaning as only the Counter_L bits are used. + * param captureRegister Pointer to a variable where the capture register number will be returned. User + * can read the captured value from this register when the specified event is triggered. + * param event Event number that will trigger the capture + * + * return kStatus_Success on success + * kStatus_Error if we have hit the limit in terms of number of match/capture registers available + */ status_t SCTIMER_SetupCaptureAction(SCT_Type *base, sctimer_counter_t whichCounter, uint32_t *captureRegister, @@ -499,11 +645,27 @@ status_t SCTIMER_SetupCaptureAction(SCT_Type *base, return kStatus_Success; } +/*! + * brief Receive noticification when the event trigger an interrupt. + * + * If the interrupt for the event is enabled by the user, then a callback can be registered + * which will be invoked when the event is triggered + * + * param base SCTimer peripheral base address + * param event Event number that will trigger the interrupt + * param callback Function to invoke when the event is triggered + */ + void SCTIMER_SetCallback(SCT_Type *base, sctimer_event_callback_t callback, uint32_t event) { s_eventCallback[event] = callback; } +/*! + * brief SCTimer interrupt handler. + * + * param base SCTimer peripheral base address. + */ void SCTIMER_EventHandleIRQ(SCT_Type *base) { uint32_t eventFlag = SCT0->EVFLAG; @@ -532,4 +694,9 @@ void SCTIMER_EventHandleIRQ(SCT_Type *base) void SCT0_IRQHandler(void) { s_sctimerIsr(SCT0); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif } diff --git a/ext/hal/nxp/mcux/drivers/lpc/fsl_sctimer.h b/ext/hal/nxp/mcux/drivers/lpc/fsl_sctimer.h index e799e1eceff..c27e8587c48 100644 --- a/ext/hal/nxp/mcux/drivers/lpc/fsl_sctimer.h +++ b/ext/hal/nxp/mcux/drivers/lpc/fsl_sctimer.h @@ -1,31 +1,9 @@ /* * Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP + * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * SPDX-License-Identifier: BSD-3-Clause */ #ifndef _FSL_SCTIMER_H_ #define _FSL_SCTIMER_H_ @@ -45,7 +23,7 @@ /*! @name Driver version */ /*@{*/ -#define FSL_SCTIMER_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0 */ +#define FSL_SCTIMER_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) /*!< Version 2.0.1 */ /*@}*/ /*! @brief SCTimer PWM operation modes */ @@ -85,7 +63,9 @@ typedef enum _sctimer_out kSCTIMER_Out_4, /*!< SCTIMER output 4 */ kSCTIMER_Out_5, /*!< SCTIMER output 5 */ kSCTIMER_Out_6, /*!< SCTIMER output 6 */ - kSCTIMER_Out_7 /*!< SCTIMER output 7 */ + kSCTIMER_Out_7, /*!< SCTIMER output 7 */ + kSCTIMER_Out_8, /*!< SCTIMER output 8 */ + kSCTIMER_Out_9 /*!< SCTIMER output 9 */ } sctimer_out_t; /*! @brief SCTimer PWM output pulse mode: high-true, low-true or no output */ @@ -249,7 +229,7 @@ typedef enum _sctimer_status_flags kSCTIMER_BusErrorLFlag = (1U << SCT_CONFLAG_BUSERRL_SHIFT), /*!< Bus error due to write when L counter was not halted */ kSCTIMER_BusErrorHFlag = - (1U << SCT_CONFLAG_BUSERRH_SHIFT) /*!< Bus error due to write when H counter was not halted */ + (int)(1U << SCT_CONFLAG_BUSERRH_SHIFT) /*!< Bus error due to write when H counter was not halted */ } sctimer_status_flags_t; /*! @@ -352,7 +332,7 @@ void SCTIMER_GetDefaultConfig(sctimer_config_t *config); * @note When setting PWM output from multiple output pins, they all should use the same PWM mode * i.e all PWM's should be either edge-aligned or center-aligned. * When using this API, the PWM signal frequency of all the initialized channels must be the same. - * Otherwise all the initialized channels' PWM signal frequency is equal to the last call to the + * Otherwise all the initialized channels' PWM signal frequency is equal to the last call to the * API's pwmFreq_Hz. * * @param base SCTimer peripheral base address @@ -661,6 +641,8 @@ static inline void SCTIMER_SetupNextStateAction(SCT_Type *base, uint32_t nextSta */ static inline void SCTIMER_SetupOutputSetAction(SCT_Type *base, uint32_t whichIO, uint32_t event) { + assert(whichIO < FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS); + base->OUT[whichIO].SET |= (1U << event); } @@ -675,6 +657,8 @@ static inline void SCTIMER_SetupOutputSetAction(SCT_Type *base, uint32_t whichIO */ static inline void SCTIMER_SetupOutputClearAction(SCT_Type *base, uint32_t whichIO, uint32_t event) { + assert(whichIO < FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS); + base->OUT[whichIO].CLR |= (1U << event); } @@ -783,6 +767,7 @@ static inline void SCTIMER_SetupCounterHaltAction(SCT_Type *base, sctimer_counte } } +#if !(defined(FSL_FEATURE_SCT_HAS_NO_DMA_REQUEST) && FSL_FEATURE_SCT_HAS_NO_DMA_REQUEST) /*! * @brief Generate a DMA request. * @@ -803,6 +788,7 @@ static inline void SCTIMER_SetupDmaTriggerAction(SCT_Type *base, uint32_t dmaNum base->DMA1REQUEST |= (1U << event); } } +#endif /* FSL_FEATURE_SCT_HAS_NO_DMA_REQUEST */ /*! * @brief SCTimer interrupt handler. diff --git a/ext/hal/nxp/mcux/drivers/lpc/fsl_spi.c b/ext/hal/nxp/mcux/drivers/lpc/fsl_spi.c index c205e95a071..4985b50438d 100644 --- a/ext/hal/nxp/mcux/drivers/lpc/fsl_spi.c +++ b/ext/hal/nxp/mcux/drivers/lpc/fsl_spi.c @@ -1,39 +1,23 @@ /* * Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP + * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * SPDX-License-Identifier: BSD-3-Clause */ #include "fsl_spi.h" #include "fsl_flexcomm.h" /******************************************************************************* - * Definitons + * Definitions ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.flexcomm_spi" +#endif + /* Note: FIFOCFG[SIZE] has always value 1 = 8 items depth */ #define SPI_FIFO_DEPTH(base) ((((base)->FIFOCFG & SPI_FIFOCFG_SIZE_MASK) >> SPI_FIFOCFG_SIZE_SHIFT) << 3) @@ -41,6 +25,7 @@ * range <0,15>. Range <8,15> represents 2B transfer */ #define SPI_COUNT_TO_BYTES(dataWidth, count) ((count) << ((dataWidth) >> 3U)) #define SPI_BYTES_TO_COUNT(dataWidth, bytes) ((bytes) >> ((dataWidth) >> 3U)) +#define SPI_SSELPOL_MASK ((SPI_CFG_SPOL0_MASK) | (SPI_CFG_SPOL1_MASK) | (SPI_CFG_SPOL2_MASK) | (SPI_CFG_SPOL3_MASK)) /******************************************************************************* * Variables @@ -54,11 +39,14 @@ static const uint32_t s_spiBaseAddrs[FSL_FEATURE_SOC_SPI_COUNT] = SPI_BASE_ADDRS /*! @brief IRQ name array */ static const IRQn_Type s_spiIRQ[] = SPI_IRQS; +/* @brief Dummy data for each instance. This data is used when user's tx buffer is NULL*/ +volatile uint8_t s_dummyData[FSL_FEATURE_SOC_SPI_COUNT] = {0}; /******************************************************************************* * Code ******************************************************************************/ /* Get the index corresponding to the FLEXCOMM */ +/*! brief Returns instance number for SPI peripheral base address. */ uint32_t SPI_GetInstance(SPI_Type *base) { int i; @@ -75,6 +63,25 @@ uint32_t SPI_GetInstance(SPI_Type *base) return 0; } +/*! + * brief Set up the dummy data. + * + * param base SPI peripheral address. + * param dummyData Data to be transferred when tx buffer is NULL. + */ +void SPI_SetDummyData(SPI_Type *base, uint8_t dummyData) +{ + uint32_t instance = SPI_GetInstance(base); + s_dummyData[instance] = dummyData; +} + +/*! + * brief Returns the configurations. + * + * param base SPI peripheral address. + * return return configurations which contain datawidth and SSEL numbers. + * return data type is a pointer of spi_config_t. + */ void *SPI_GetConfig(SPI_Type *base) { int32_t instance; @@ -86,10 +93,28 @@ void *SPI_GetConfig(SPI_Type *base) return &g_configs[instance]; } +/*! + * brief Sets the SPI master configuration structure to default values. + * + * The purpose of this API is to get the configuration structure initialized for use in SPI_MasterInit(). + * User may use the initialized structure unchanged in SPI_MasterInit(), or modify + * some fields of the structure before calling SPI_MasterInit(). After calling this API, + * the master is ready to transfer. + * Example: + code + spi_master_config_t config; + SPI_MasterGetDefaultConfig(&config); + endcode + * + * param config pointer to master config structure + */ void SPI_MasterGetDefaultConfig(spi_master_config_t *config) { assert(NULL != config); + /* Initializes the configure structure to zero. */ + memset(config, 0, sizeof(*config)); + config->enableLoopback = false; config->enableMaster = true; config->polarity = kSPI_ClockPolarityActiveHigh; @@ -100,8 +125,31 @@ void SPI_MasterGetDefaultConfig(spi_master_config_t *config) config->sselNum = kSPI_Ssel0; config->txWatermark = kSPI_TxFifo0; config->rxWatermark = kSPI_RxFifo1; + config->sselPol = kSPI_SpolActiveAllLow; + config->delayConfig.preDelay = 0U; + config->delayConfig.postDelay = 0U; + config->delayConfig.frameDelay = 0U; + config->delayConfig.transferDelay = 0U; } +/*! + * brief Initializes the SPI with master configuration. + * + * The configuration structure can be filled by user from scratch, or be set with default + * values by SPI_MasterGetDefaultConfig(). After calling this API, the slave is ready to transfer. + * Example + code + spi_master_config_t config = { + .baudRate_Bps = 400000, + ... + }; + SPI_MasterInit(SPI0, &config); + endcode + * + * param base SPI base pointer + * param config pointer to master configuration structure + * param srcClock_Hz Source clock frequency. + */ status_t SPI_MasterInit(SPI_Type *base, const spi_master_config_t *config, uint32_t srcClock_Hz) { int32_t result = 0, instance = 0; @@ -134,7 +182,8 @@ status_t SPI_MasterInit(SPI_Type *base, const spi_master_config_t *config, uint3 /* configure SPI mode */ tmp = base->CFG; - tmp &= ~(SPI_CFG_MASTER_MASK | SPI_CFG_LSBF_MASK | SPI_CFG_CPHA_MASK | SPI_CFG_CPOL_MASK | SPI_CFG_LOOP_MASK | SPI_CFG_ENABLE_MASK); + tmp &= ~(SPI_CFG_MASTER_MASK | SPI_CFG_LSBF_MASK | SPI_CFG_CPHA_MASK | SPI_CFG_CPOL_MASK | SPI_CFG_LOOP_MASK | + SPI_CFG_ENABLE_MASK | SPI_SSELPOL_MASK); /* phase */ tmp |= SPI_CFG_CPHA(config->phase); /* polarity */ @@ -145,6 +194,8 @@ status_t SPI_MasterInit(SPI_Type *base, const spi_master_config_t *config, uint3 tmp |= SPI_CFG_MASTER(1); /* loopback */ tmp |= SPI_CFG_LOOP(config->enableLoopback); + /* configure active level for all CS */ + tmp |= ((uint32_t)config->sselPol & (SPI_SSELPOL_MASK)); base->CFG = tmp; /* store configuration */ @@ -161,14 +212,35 @@ status_t SPI_MasterInit(SPI_Type *base, const spi_master_config_t *config, uint3 /* set FIFOTRIG */ base->FIFOTRIG = tmp; + /* Set the delay configuration. */ + SPI_SetTransferDelay(base, &config->delayConfig); + /* Set the dummy data. */ + SPI_SetDummyData(base, (uint8_t)SPI_DUMMYDATA); + SPI_Enable(base, config->enableMaster); return kStatus_Success; } +/*! + * brief Sets the SPI slave configuration structure to default values. + * + * The purpose of this API is to get the configuration structure initialized for use in SPI_SlaveInit(). + * Modify some fields of the structure before calling SPI_SlaveInit(). + * Example: + code + spi_slave_config_t config; + SPI_SlaveGetDefaultConfig(&config); + endcode + * + * param config pointer to slave configuration structure + */ void SPI_SlaveGetDefaultConfig(spi_slave_config_t *config) { assert(NULL != config); + /* Initializes the configure structure to zero. */ + memset(config, 0, sizeof(*config)); + config->enableSlave = true; config->polarity = kSPI_ClockPolarityActiveHigh; config->phase = kSPI_ClockPhaseFirstEdge; @@ -176,8 +248,29 @@ void SPI_SlaveGetDefaultConfig(spi_slave_config_t *config) config->dataWidth = kSPI_Data8Bits; config->txWatermark = kSPI_TxFifo0; config->rxWatermark = kSPI_RxFifo1; + config->sselPol = kSPI_SpolActiveAllLow; } +/*! + * brief Initializes the SPI with slave configuration. + * + * The configuration structure can be filled by user from scratch or be set with + * default values by SPI_SlaveGetDefaultConfig(). + * After calling this API, the slave is ready to transfer. + * Example + code + spi_slave_config_t config = { + .polarity = flexSPIClockPolarity_ActiveHigh; + .phase = flexSPIClockPhase_FirstEdge; + .direction = flexSPIMsbFirst; + ... + }; + SPI_SlaveInit(SPI0, &config); + endcode + * + * param base SPI base pointer + * param config pointer to slave configuration structure + */ status_t SPI_SlaveInit(SPI_Type *base, const spi_slave_config_t *config) { int32_t result = 0, instance; @@ -201,13 +294,16 @@ status_t SPI_SlaveInit(SPI_Type *base, const spi_slave_config_t *config) /* configure SPI mode */ tmp = base->CFG; - tmp &= ~(SPI_CFG_MASTER_MASK | SPI_CFG_LSBF_MASK | SPI_CFG_CPHA_MASK | SPI_CFG_CPOL_MASK | SPI_CFG_ENABLE_MASK); + tmp &= ~(SPI_CFG_MASTER_MASK | SPI_CFG_LSBF_MASK | SPI_CFG_CPHA_MASK | SPI_CFG_CPOL_MASK | SPI_CFG_ENABLE_MASK | + SPI_SSELPOL_MASK); /* phase */ tmp |= SPI_CFG_CPHA(config->phase); /* polarity */ tmp |= SPI_CFG_CPOL(config->polarity); /* direction */ tmp |= SPI_CFG_LSBF(config->direction); + /* configure active level for all CS */ + tmp |= ((uint32_t)config->sselPol & (SPI_SSELPOL_MASK)); base->CFG = tmp; /* store configuration */ @@ -223,10 +319,20 @@ status_t SPI_SlaveInit(SPI_Type *base, const spi_slave_config_t *config) /* set FIFOTRIG */ base->FIFOTRIG = tmp; + SPI_SetDummyData(base, (uint8_t)SPI_DUMMYDATA); + SPI_Enable(base, config->enableSlave); return kStatus_Success; } +/*! + * brief De-initializes the SPI. + * + * Calling this API resets the SPI module, gates the SPI clock. + * The SPI module can't work unless calling the SPI_MasterInit/SPI_SlaveInit to initialize module. + * + * param base SPI base pointer + */ void SPI_Deinit(SPI_Type *base) { /* Assert arguments */ @@ -238,6 +344,12 @@ void SPI_Deinit(SPI_Type *base) base->CFG &= ~(SPI_CFG_ENABLE_MASK); } +/*! + * brief Enables the DMA request from SPI txFIFO. + * + * param base SPI base pointer + * param enable True means enable DMA, false means disable DMA + */ void SPI_EnableTxDMA(SPI_Type *base, bool enable) { if (enable) @@ -250,6 +362,12 @@ void SPI_EnableTxDMA(SPI_Type *base, bool enable) } } +/*! + * brief Enables the DMA request from SPI rxFIFO. + * + * param base SPI base pointer + * param enable True means enable DMA, false means disable DMA + */ void SPI_EnableRxDMA(SPI_Type *base, bool enable) { if (enable) @@ -262,6 +380,13 @@ void SPI_EnableRxDMA(SPI_Type *base, bool enable) } } +/*! + * brief Sets the baud rate for SPI transfer. This is only used in master. + * + * param base SPI base pointer + * param baudrate_Bps baud rate needed in Hz. + * param srcClock_Hz SPI source clock frequency in Hz. + */ status_t SPI_MasterSetBaud(SPI_Type *base, uint32_t baudrate_Bps, uint32_t srcClock_Hz) { uint32_t tmp; @@ -284,6 +409,13 @@ status_t SPI_MasterSetBaud(SPI_Type *base, uint32_t baudrate_Bps, uint32_t srcCl return kStatus_Success; } +/*! + * brief Writes a data into the SPI data register. + * + * param base SPI base pointer + * param data needs to be write. + * param configFlags transfer configuration options ref spi_xfer_option_t + */ void SPI_WriteData(SPI_Type *base, uint16_t data, uint32_t configFlags) { uint32_t control = 0; @@ -310,6 +442,17 @@ void SPI_WriteData(SPI_Type *base, uint16_t data, uint32_t configFlags) base->FIFOWR = data | control; } +/*! + * brief Initializes the SPI master handle. + * + * This function initializes the SPI master handle which can be used for other SPI master transactional APIs. Usually, + * for a specified SPI instance, call this API once to get the initialized handle. + * + * param base SPI peripheral base address. + * param handle SPI handle pointer. + * param callback Callback function. + * param userData User data. + */ status_t SPI_MasterTransferCreateHandle(SPI_Type *base, spi_master_handle_t *handle, spi_master_callback_t callback, @@ -341,11 +484,11 @@ status_t SPI_MasterTransferCreateHandle(SPI_Type *base, /* Initialize the handle */ if (base->CFG & SPI_CFG_MASTER_MASK) { - FLEXCOMM_SetIRQHandler(base, (flexcomm_irq_handler_t)(uintptr_t)SPI_MasterTransferHandleIRQ, handle); + FLEXCOMM_SetIRQHandler(base, (flexcomm_irq_handler_t)SPI_MasterTransferHandleIRQ, handle); } else { - FLEXCOMM_SetIRQHandler(base, (flexcomm_irq_handler_t)(uintptr_t)SPI_SlaveTransferHandleIRQ, handle); + FLEXCOMM_SetIRQHandler(base, (flexcomm_irq_handler_t)SPI_SlaveTransferHandleIRQ, handle); } handle->dataWidth = g_configs[instance].dataWidth; @@ -362,6 +505,14 @@ status_t SPI_MasterTransferCreateHandle(SPI_Type *base, return kStatus_Success; } +/*! + * brief Transfers a block of data using a polling method. + * + * param base SPI base pointer + * param xfer pointer to spi_xfer_config_t structure + * retval kStatus_Success Successfully start a transfer. + * retval kStatus_InvalidArgument Input argument is invalid. + */ status_t SPI_MasterTransferBlocking(SPI_Type *base, spi_transfer_t *xfer) { int32_t instance; @@ -402,10 +553,10 @@ status_t SPI_MasterTransferBlocking(SPI_Type *base, spi_transfer_t *xfer) tx_ctrl |= (SPI_DEASSERT_ALL & (~SPI_DEASSERTNUM_SSEL(g_configs[instance].sselNum))); /* set width of data - range asserted at entry */ tx_ctrl |= SPI_FIFOWR_LEN(dataWidth); + /* delay for frames */ + tx_ctrl |= (xfer->configFlags & (uint32_t)kSPI_FrameDelay) ? (uint32_t)kSPI_FrameDelay : 0; /* end of transfer */ last_ctrl |= (xfer->configFlags & (uint32_t)kSPI_FrameAssert) ? (uint32_t)kSPI_FrameAssert : 0; - /* delay end of transfer */ - last_ctrl |= (xfer->configFlags & (uint32_t)kSPI_FrameDelay) ? (uint32_t)kSPI_FrameDelay : 0; /* last index of loop */ while (txRemainingBytes || rxRemainingBytes || toReceiveCount) { @@ -450,7 +601,7 @@ status_t SPI_MasterTransferBlocking(SPI_Type *base, spi_transfer_t *xfer) } else { - tmp32 = SPI_DUMMYDATA; + tmp32 = ((uint32_t)s_dummyData[instance] << 8U | (s_dummyData[instance])); /* last transfer */ if (rxRemainingBytes == SPI_COUNT_TO_BYTES(dataWidth, toReceiveCount + 1)) { @@ -470,6 +621,16 @@ status_t SPI_MasterTransferBlocking(SPI_Type *base, spi_transfer_t *xfer) return kStatus_Success; } +/*! + * brief Performs a non-blocking SPI interrupt transfer. + * + * param base SPI peripheral base address. + * param handle pointer to spi_master_handle_t structure which stores the transfer state + * param xfer pointer to spi_xfer_config_t structure + * retval kStatus_Success Successfully start a transfer. + * retval kStatus_InvalidArgument Input argument is invalid. + * retval kStatus_SPI_Busy SPI is not idle, is running another transfer. + */ status_t SPI_MasterTransferNonBlocking(SPI_Type *base, spi_master_handle_t *handle, spi_transfer_t *xfer) { /* check params */ @@ -513,6 +674,152 @@ status_t SPI_MasterTransferNonBlocking(SPI_Type *base, spi_master_handle_t *hand return kStatus_Success; } +/*! + * brief Transfers a block of data using a polling method. + * + * This function will do a half-duplex transfer for SPI master, This is a blocking function, + * which does not retuen until all transfer have been completed. And data transfer mechanism is half-duplex, + * users can set transmit first or receive first. + * + * param base SPI base pointer + * param xfer pointer to spi_half_duplex_transfer_t structure + * return status of status_t. + */ +status_t SPI_MasterHalfDuplexTransferBlocking(SPI_Type *base, spi_half_duplex_transfer_t *xfer) +{ + assert(xfer); + + spi_transfer_t tempXfer = {0}; + status_t status; + + if (xfer->isTransmitFirst) + { + tempXfer.txData = xfer->txData; + tempXfer.rxData = NULL; + tempXfer.dataSize = xfer->txDataSize; + } + else + { + tempXfer.txData = NULL; + tempXfer.rxData = xfer->rxData; + tempXfer.dataSize = xfer->rxDataSize; + } + /* If the pcs pin keep assert between transmit and receive. */ + if (xfer->isPcsAssertInTransfer) + { + tempXfer.configFlags = (xfer->configFlags) & (uint32_t)(~kSPI_FrameAssert); + } + else + { + tempXfer.configFlags = (xfer->configFlags) | kSPI_FrameAssert; + } + + status = SPI_MasterTransferBlocking(base, &tempXfer); + + if (status != kStatus_Success) + { + return status; + } + + if (xfer->isTransmitFirst) + { + tempXfer.txData = NULL; + tempXfer.rxData = xfer->rxData; + tempXfer.dataSize = xfer->rxDataSize; + } + else + { + tempXfer.txData = xfer->txData; + tempXfer.rxData = NULL; + tempXfer.dataSize = xfer->txDataSize; + } + tempXfer.configFlags = xfer->configFlags; + + /* SPI transfer blocking. */ + status = SPI_MasterTransferBlocking(base, &tempXfer); + + return status; +} + +/*! + * brief Performs a non-blocking SPI interrupt transfer. + * + * This function using polling way to do the first half transimission and using interrupts to + * do the second half transimission, the transfer mechanism is half-duplex. + * When do the second half transimission, code will return right away. When all data is transferred, + * the callback function is called. + * + * param base SPI peripheral base address. + * param handle pointer to spi_master_handle_t structure which stores the transfer state + * param xfer pointer to spi_half_duplex_transfer_t structure + * return status of status_t. + */ +status_t SPI_MasterHalfDuplexTransferNonBlocking(SPI_Type *base, + spi_master_handle_t *handle, + spi_half_duplex_transfer_t *xfer) +{ + assert(xfer); + assert(handle); + spi_transfer_t tempXfer = {0}; + status_t status; + + if (xfer->isTransmitFirst) + { + tempXfer.txData = xfer->txData; + tempXfer.rxData = NULL; + tempXfer.dataSize = xfer->txDataSize; + } + else + { + tempXfer.txData = NULL; + tempXfer.rxData = xfer->rxData; + tempXfer.dataSize = xfer->rxDataSize; + } + /* If the PCS pin keep assert between transmit and receive. */ + if (xfer->isPcsAssertInTransfer) + { + tempXfer.configFlags = (xfer->configFlags) & (uint32_t)(~kSPI_FrameAssert); + } + else + { + tempXfer.configFlags = (xfer->configFlags) | kSPI_FrameAssert; + } + + status = SPI_MasterTransferBlocking(base, &tempXfer); + if (status != kStatus_Success) + { + return status; + } + + if (xfer->isTransmitFirst) + { + tempXfer.txData = NULL; + tempXfer.rxData = xfer->rxData; + tempXfer.dataSize = xfer->rxDataSize; + } + else + { + tempXfer.txData = xfer->txData; + tempXfer.rxData = NULL; + tempXfer.dataSize = xfer->txDataSize; + } + tempXfer.configFlags = xfer->configFlags; + + status = SPI_MasterTransferNonBlocking(base, handle, &tempXfer); + + return status; +} + +/*! + * brief Gets the master transfer count. + * + * This function gets the master transfer count. + * + * param base SPI peripheral base address. + * param handle Pointer to the spi_master_handle_t structure which stores the transfer state. + * param count The number of bytes transferred by using the non-blocking transaction. + * return status of status_t. + */ status_t SPI_MasterTransferGetCount(SPI_Type *base, spi_master_handle_t *handle, size_t *count) { assert(NULL != handle); @@ -533,6 +840,14 @@ status_t SPI_MasterTransferGetCount(SPI_Type *base, spi_master_handle_t *handle, return kStatus_Success; } +/*! + * brief SPI master aborts a transfer using an interrupt. + * + * This function aborts a transfer using an interrupt. + * + * param base SPI peripheral base address. + * param handle Pointer to the spi_master_handle_t structure which stores the transfer state. + */ void SPI_MasterTransferAbort(SPI_Type *base, spi_master_handle_t *handle) { assert(NULL != handle); @@ -552,6 +867,8 @@ static void SPI_TransferHandleIRQInternal(SPI_Type *base, spi_master_handle_t *h uint32_t tx_ctrl = 0, last_ctrl = 0, tmp32; bool loopContinue; uint32_t fifoDepth; + /* Get flexcomm instance by 'base' param */ + uint32_t instance = SPI_GetInstance(base); /* check params */ assert((NULL != base) && (NULL != handle) && ((NULL != handle->txData) || (NULL != handle->rxData))); @@ -561,10 +878,10 @@ static void SPI_TransferHandleIRQInternal(SPI_Type *base, spi_master_handle_t *h tx_ctrl |= (SPI_DEASSERT_ALL & SPI_ASSERTNUM_SSEL(handle->sselNum)); /* set width of data */ tx_ctrl |= SPI_FIFOWR_LEN(handle->dataWidth); + /* delay for frames */ + tx_ctrl |= (handle->configFlags & (uint32_t)kSPI_FrameDelay) ? (uint32_t)kSPI_FrameDelay : 0; /* end of transfer */ last_ctrl |= (handle->configFlags & (uint32_t)kSPI_FrameAssert) ? (uint32_t)kSPI_FrameAssert : 0; - /* delay end of transfer */ - last_ctrl |= (handle->configFlags & (uint32_t)kSPI_FrameDelay) ? (uint32_t)kSPI_FrameDelay : 0; do { loopContinue = false; @@ -619,7 +936,7 @@ static void SPI_TransferHandleIRQInternal(SPI_Type *base, spi_master_handle_t *h } else { - tmp32 = SPI_DUMMYDATA; + tmp32 = ((uint32_t)s_dummyData[instance] << 8U | (s_dummyData[instance])); /* last transfer */ if (handle->rxRemainingBytes == SPI_COUNT_TO_BYTES(handle->dataWidth, handle->toReceiveCount + 1)) { @@ -636,6 +953,12 @@ static void SPI_TransferHandleIRQInternal(SPI_Type *base, spi_master_handle_t *h } while (loopContinue); } +/*! + * brief Interrupts the handler for the SPI. + * + * param base SPI peripheral base address. + * param handle pointer to spi_master_handle_t structure which stores the transfer state. + */ void SPI_MasterTransferHandleIRQ(SPI_Type *base, spi_master_handle_t *handle) { assert((NULL != base) && (NULL != handle)); diff --git a/ext/hal/nxp/mcux/drivers/lpc/fsl_spi.h b/ext/hal/nxp/mcux/drivers/lpc/fsl_spi.h index e444774a7ba..de33f50d6c7 100644 --- a/ext/hal/nxp/mcux/drivers/lpc/fsl_spi.h +++ b/ext/hal/nxp/mcux/drivers/lpc/fsl_spi.h @@ -1,31 +1,9 @@ /* * Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP + * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * SPDX-License-Identifier: BSD-3-Clause */ #ifndef _FSL_SPI_H_ #define _FSL_SPI_H_ @@ -46,11 +24,18 @@ /*! @name Driver version */ /*@{*/ -/*! @brief USART driver version 2.0.0. */ -#define FSL_SPI_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) +/*! @brief SPI driver version 2.0.3. */ +#define FSL_SPI_DRIVER_VERSION (MAKE_VERSION(2, 0, 3)) /*@}*/ -#define SPI_DUMMYDATA (0xFFFF) +/*! @brief Global variable for dummy data value setting. */ +extern volatile uint8_t s_dummyData[]; + +#ifndef SPI_DUMMYDATA +/*! @brief SPI dummy transfer data, the data is sent while txBuff is NULL. */ +#define SPI_DUMMYDATA (0xFFU) +#endif + #define SPI_DATA(n) (((uint32_t)(n)) & 0xFFFF) #define SPI_CTRLMASK (0xFFFF0000) @@ -64,25 +49,29 @@ #define SPI_FIFOTRIG_RXLVL_GET(base) (((base)->FIFOTRIG & SPI_FIFOTRIG_RXLVL_MASK) >> SPI_FIFOTRIG_RXLVL_SHIFT) /*! @brief SPI transfer option.*/ -typedef enum _spi_xfer_option { - kSPI_FrameDelay = (SPI_FIFOWR_EOF_MASK), /*!< Delay chip select */ - kSPI_FrameAssert = (SPI_FIFOWR_EOT_MASK), /*!< When transfer ends, assert chip select */ +typedef enum _spi_xfer_option +{ + kSPI_FrameDelay = (SPI_FIFOWR_EOF_MASK), /*!< A delay may be inserted, defined in the DLY register.*/ + kSPI_FrameAssert = (SPI_FIFOWR_EOT_MASK), /*!< SSEL will be deasserted at the end of a transfer */ } spi_xfer_option_t; /*! @brief SPI data shifter direction options.*/ -typedef enum _spi_shift_direction { +typedef enum _spi_shift_direction +{ kSPI_MsbFirst = 0U, /*!< Data transfers start with most significant bit. */ kSPI_LsbFirst = 1U /*!< Data transfers start with least significant bit. */ } spi_shift_direction_t; /*! @brief SPI clock polarity configuration.*/ -typedef enum _spi_clock_polarity { +typedef enum _spi_clock_polarity +{ kSPI_ClockPolarityActiveHigh = 0x0U, /*!< Active-high SPI clock (idles low). */ kSPI_ClockPolarityActiveLow /*!< Active-low SPI clock (idles high). */ } spi_clock_polarity_t; /*! @brief SPI clock phase configuration.*/ -typedef enum _spi_clock_phase { +typedef enum _spi_clock_phase +{ kSPI_ClockPhaseFirstEdge = 0x0U, /*!< First edge on SCK occurs at the middle of the first * cycle of a data transfer. */ kSPI_ClockPhaseSecondEdge /*!< First edge on SCK occurs at the start of the @@ -90,7 +79,8 @@ typedef enum _spi_clock_phase { } spi_clock_phase_t; /*! @brief txFIFO watermark values */ -typedef enum _spi_txfifo_watermark { +typedef enum _spi_txfifo_watermark +{ kSPI_TxFifo0 = 0, /*!< SPI tx watermark is empty */ kSPI_TxFifo1 = 1, /*!< SPI tx watermark at 1 item */ kSPI_TxFifo2 = 2, /*!< SPI tx watermark at 2 items */ @@ -102,7 +92,8 @@ typedef enum _spi_txfifo_watermark { } spi_txfifo_watermark_t; /*! @brief rxFIFO watermark values */ -typedef enum _spi_rxfifo_watermark { +typedef enum _spi_rxfifo_watermark +{ kSPI_RxFifo1 = 0, /*!< SPI rx watermark at 1 item */ kSPI_RxFifo2 = 1, /*!< SPI rx watermark at 2 items */ kSPI_RxFifo3 = 2, /*!< SPI rx watermark at 3 items */ @@ -114,7 +105,8 @@ typedef enum _spi_rxfifo_watermark { } spi_rxfifo_watermark_t; /*! @brief Transfer data width */ -typedef enum _spi_data_width { +typedef enum _spi_data_width +{ kSPI_Data4Bits = 3, /*!< 4 bits data width */ kSPI_Data5Bits = 4, /*!< 5 bits data width */ kSPI_Data6Bits = 5, /*!< 6 bits data width */ @@ -131,13 +123,41 @@ typedef enum _spi_data_width { } spi_data_width_t; /*! @brief Slave select */ -typedef enum _spi_ssel { +typedef enum _spi_ssel +{ kSPI_Ssel0 = 0, /*!< Slave select 0 */ kSPI_Ssel1 = 1, /*!< Slave select 1 */ kSPI_Ssel2 = 2, /*!< Slave select 2 */ kSPI_Ssel3 = 3, /*!< Slave select 3 */ } spi_ssel_t; +/*! @brief ssel polarity */ +typedef enum _spi_spol +{ + kSPI_Spol0ActiveHigh = SPI_CFG_SPOL0(1), + kSPI_Spol1ActiveHigh = SPI_CFG_SPOL1(1), + kSPI_Spol2ActiveHigh = SPI_CFG_SPOL2(1), + kSPI_Spol3ActiveHigh = SPI_CFG_SPOL3(1), + kSPI_SpolActiveAllHigh = + (kSPI_Spol0ActiveHigh | kSPI_Spol1ActiveHigh | kSPI_Spol2ActiveHigh | kSPI_Spol3ActiveHigh), + kSPI_SpolActiveAllLow = 0, +} spi_spol_t; + +/*! + * @brief SPI delay time configure structure. + * Note: + * The DLY register controls several programmable delays related to SPI signalling, + * it stands for how many SPI clock time will be inserted. + * The maxinun value of these delay time is 15. + */ +typedef struct _spi_delay_config +{ + uint8_t preDelay; /*!< Delay between SSEL assertion and the beginning of transfer. */ + uint8_t postDelay; /*!< Delay between the end of transfer and SSEL deassertion. */ + uint8_t frameDelay; /*!< Delay between frame to frame. */ + uint8_t transferDelay; /*!< Delay between transfer to transfer. */ +} spi_delay_config_t; + /*! @brief SPI master user configure structure.*/ typedef struct _spi_master_config { @@ -149,8 +169,10 @@ typedef struct _spi_master_config uint32_t baudRate_Bps; /*!< Baud Rate for SPI in Hz */ spi_data_width_t dataWidth; /*!< Width of the data */ spi_ssel_t sselNum; /*!< Slave select number */ + spi_spol_t sselPol; /*!< Configure active CS polarity */ spi_txfifo_watermark_t txWatermark; /*!< txFIFO watermark */ spi_rxfifo_watermark_t rxWatermark; /*!< rxFIFO watermark */ + spi_delay_config_t delayConfig; /*!< Delay configuration. */ } spi_master_config_t; /*! @brief SPI slave user configure structure.*/ @@ -161,6 +183,7 @@ typedef struct _spi_slave_config spi_clock_phase_t phase; /*!< Clock phase */ spi_shift_direction_t direction; /*!< MSB or LSB */ spi_data_width_t dataWidth; /*!< Width of the data */ + spi_spol_t sselPol; /*!< Configure active CS polarity */ spi_txfifo_watermark_t txWatermark; /*!< txFIFO watermark */ spi_rxfifo_watermark_t rxWatermark; /*!< rxFIFO watermark */ } spi_slave_config_t; @@ -196,10 +219,23 @@ typedef struct _spi_transfer { uint8_t *txData; /*!< Send buffer */ uint8_t *rxData; /*!< Receive buffer */ - uint32_t configFlags; /*!< Additional option to control transfer */ + uint32_t configFlags; /*!< Additional option to control transfer, @ref spi_xfer_option_t. */ size_t dataSize; /*!< Transfer bytes */ } spi_transfer_t; +/*! @brief SPI half-duplex(master only) transfer structure */ +typedef struct _spi_half_duplex_transfer +{ + uint8_t *txData; /*!< Send buffer */ + uint8_t *rxData; /*!< Receive buffer */ + size_t txDataSize; /*!< Transfer bytes for transmit */ + size_t rxDataSize; /*!< Transfer bytes */ + uint32_t configFlags; /*!< Transfer configuration flags, @ref spi_xfer_option_t. */ + bool isPcsAssertInTransfer; /*!< If PCS pin keep assert between transmit and receive. true for assert and false for + deassert. */ + bool isTransmitFirst; /*!< True for transmit first and false for receive first. */ +} spi_half_duplex_transfer_t; + /*! @brief Internal configuration structure used in 'spi' and 'spi_dma' driver */ typedef struct _spi_config { @@ -437,6 +473,14 @@ void SPI_EnableRxDMA(SPI_Type *base, bool enable); * @name Bus Operations * @{ */ +/*! + * @brief Returns the configurations. + * + * @param base SPI peripheral address. + * @return return configurations which contain datawidth and SSEL numbers. + * return data type is a pointer of spi_config_t. + */ +void *SPI_GetConfig(SPI_Type *base); /*! * @brief Sets the baud rate for SPI transfer. This is only used in master. @@ -468,6 +512,28 @@ static inline uint32_t SPI_ReadData(SPI_Type *base) return base->FIFORD; } +/*! + * @brief Set delay time for transfer. + * the delay uint is SPI clock time, maximum value is 0xF. + * @param base SPI base pointer + * @param config configuration for delay option @ref spi_delay_config_t. + */ +static inline void SPI_SetTransferDelay(SPI_Type *base, const spi_delay_config_t *config) +{ + assert(NULL != base); + assert(NULL != config); + base->DLY = (SPI_DLY_PRE_DELAY(config->preDelay) | SPI_DLY_POST_DELAY(config->postDelay) | + SPI_DLY_FRAME_DELAY(config->frameDelay) | SPI_DLY_TRANSFER_DELAY(config->transferDelay)); +} + +/*! + * @brief Set up the dummy data. + * + * @param base SPI peripheral address. + * @param dummyData Data to be transferred when tx buffer is NULL. + */ +void SPI_SetDummyData(SPI_Type *base, uint8_t dummyData); + /*! @} */ /*! @@ -513,6 +579,36 @@ status_t SPI_MasterTransferBlocking(SPI_Type *base, spi_transfer_t *xfer); */ status_t SPI_MasterTransferNonBlocking(SPI_Type *base, spi_master_handle_t *handle, spi_transfer_t *xfer); +/*! + * @brief Transfers a block of data using a polling method. + * + * This function will do a half-duplex transfer for SPI master, This is a blocking function, + * which does not retuen until all transfer have been completed. And data transfer mechanism is half-duplex, + * users can set transmit first or receive first. + * + * @param base SPI base pointer + * @param xfer pointer to spi_half_duplex_transfer_t structure + * @return status of status_t. + */ +status_t SPI_MasterHalfDuplexTransferBlocking(SPI_Type *base, spi_half_duplex_transfer_t *xfer); + +/*! + * @brief Performs a non-blocking SPI interrupt transfer. + * + * This function using polling way to do the first half transimission and using interrupts to + * do the second half transimission, the transfer mechanism is half-duplex. + * When do the second half transimission, code will return right away. When all data is transferred, + * the callback function is called. + * + * @param base SPI peripheral base address. + * @param handle pointer to spi_master_handle_t structure which stores the transfer state + * @param xfer pointer to spi_half_duplex_transfer_t structure + * @return status of status_t. + */ +status_t SPI_MasterHalfDuplexTransferNonBlocking(SPI_Type *base, + spi_master_handle_t *handle, + spi_half_duplex_transfer_t *xfer); + /*! * @brief Gets the master transfer count. * @@ -591,7 +687,7 @@ static inline status_t SPI_SlaveTransferNonBlocking(SPI_Type *base, spi_slave_ha */ static inline status_t SPI_SlaveTransferGetCount(SPI_Type *base, spi_slave_handle_t *handle, size_t *count) { - return SPI_MasterTransferGetCount(base, (spi_master_handle_t*)handle, count); + return SPI_MasterTransferGetCount(base, (spi_master_handle_t *)handle, count); } /*! @@ -604,7 +700,7 @@ static inline status_t SPI_SlaveTransferGetCount(SPI_Type *base, spi_slave_handl */ static inline void SPI_SlaveTransferAbort(SPI_Type *base, spi_slave_handle_t *handle) { - SPI_MasterTransferAbort(base, (spi_master_handle_t*)handle); + SPI_MasterTransferAbort(base, (spi_master_handle_t *)handle); } /*! diff --git a/ext/hal/nxp/mcux/drivers/lpc/fsl_spi_dma.c b/ext/hal/nxp/mcux/drivers/lpc/fsl_spi_dma.c index 4ac9007952a..0f200e134ad 100644 --- a/ext/hal/nxp/mcux/drivers/lpc/fsl_spi_dma.c +++ b/ext/hal/nxp/mcux/drivers/lpc/fsl_spi_dma.c @@ -1,38 +1,22 @@ /* * Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP + * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * SPDX-License-Identifier: BSD-3-Clause */ #include "fsl_spi_dma.h" /******************************************************************************* - * Definitons + * Definitions ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.flexcomm_spi_dma" +#endif + /*dataWidth); } -static void PrepareTxFIFO(uint32_t *fifo, uint32_t count, uint32_t ctrl) +static void PrepareTxLastWord(spi_transfer_t *xfer, uint32_t *txLastWord, spi_config_t *config) { - assert(!(fifo == NULL)); - if (fifo == NULL) + if (config->dataWidth > kSPI_Data8Bits) { - return; + *txLastWord = (((uint32_t)xfer->txData[xfer->dataSize - 1] << 8U) | (xfer->txData[xfer->dataSize - 2])); } - /* CS deassert and CS delay are relevant only for last word */ - uint32_t tx_ctrl = ctrl & (~(SPI_FIFOWR_EOT_MASK | SPI_FIFOWR_EOF_MASK)); - uint32_t i = 0; - for (; i + 1 < count; i++) + else { - fifo[i] = (fifo[i] & 0xFFFFU) | (tx_ctrl & 0xFFFF0000U); - } - if (i < count) - { - fifo[i] = (fifo[i] & 0xFFFFU) | (ctrl & 0xFFFF0000U); + *txLastWord = xfer->txData[xfer->dataSize - 1]; } + XferToFifoWR(xfer, txLastWord); + SpiConfigToFifoWR(config, txLastWord); } -static void SPI_SetupDummy(uint32_t *dummy, spi_transfer_t *xfer, spi_config_t *spi_config_p) +static void SPI_SetupDummy(SPI_Type *base, spi_dma_txdummy_t *dummy, spi_transfer_t *xfer, spi_config_t *spi_config_p) { - *dummy = SPI_DUMMYDATA; - XferToFifoWR(xfer, dummy); - SpiConfigToFifoWR(spi_config_p, dummy); + uint32_t instance = SPI_GetInstance(base); + dummy->word = ((uint32_t)s_dummyData[instance] << 8U | s_dummyData[instance]); + dummy->lastWord = ((uint32_t)s_dummyData[instance] << 8U | s_dummyData[instance]); + XferToFifoWR(xfer, &dummy->word); + XferToFifoWR(xfer, &dummy->lastWord); + SpiConfigToFifoWR(spi_config_p, &dummy->word); + SpiConfigToFifoWR(spi_config_p, &dummy->lastWord); + /* Clear the end of transfer bit for continue word transfer. */ + dummy->word &= (uint32_t)(~kSPI_FrameAssert); } +/*! + * brief Initialize the SPI master DMA handle. + * + * This function initializes the SPI master DMA handle which can be used for other SPI master transactional APIs. + * Usually, for a specified SPI instance, user need only call this API once to get the initialized handle. + * + * param base SPI peripheral base address. + * param handle SPI handle pointer. + * param callback User callback function called at the end of a transfer. + * param userData User data for callback. + * param txHandle DMA handle pointer for SPI Tx, the handle shall be static allocated by users. + * param rxHandle DMA handle pointer for SPI Rx, the handle shall be static allocated by users. + */ status_t SPI_MasterTransferCreateHandleDMA(SPI_Type *base, spi_dma_handle_t *handle, spi_dma_callback_t callback, @@ -201,6 +194,19 @@ status_t SPI_MasterTransferCreateHandleDMA(SPI_Type *base, return kStatus_Success; } +/*! + * brief Perform a non-blocking SPI transfer using DMA. + * + * note This interface returned immediately after transfer initiates, users should call + * SPI_GetTransferStatus to poll the transfer status to check whether SPI transfer finished. + * + * param base SPI peripheral base address. + * param handle SPI DMA handle pointer. + * param xfer Pointer to dma transfer structure. + * retval kStatus_Success Successfully start a transfer. + * retval kStatus_InvalidArgument Input argument is invalid. + * retval kStatus_SPI_Busy SPI is not idle, is running another transfer. + */ status_t SPI_MasterTransferDMA(SPI_Type *base, spi_dma_handle_t *handle, spi_transfer_t *xfer) { int32_t instance; @@ -212,21 +218,10 @@ status_t SPI_MasterTransferDMA(SPI_Type *base, spi_dma_handle_t *handle, spi_tra { return kStatus_InvalidArgument; } - /* txData set and not aligned to sizeof(uint32_t) */ - assert(!((NULL != xfer->txData) && ((uint32_t)xfer->txData % sizeof(uint32_t)))); - if ((NULL != xfer->txData) && ((uint32_t)xfer->txData % sizeof(uint32_t))) - { - return kStatus_InvalidArgument; - } - /* rxData set and not aligned to sizeof(uint32_t) */ - assert(!((NULL != xfer->rxData) && ((uint32_t)xfer->rxData % sizeof(uint32_t)))); - if ((NULL != xfer->rxData) && ((uint32_t)xfer->rxData % sizeof(uint32_t))) - { - return kStatus_InvalidArgument; - } - /* byte size is zero or not aligned to sizeof(uint32_t) */ - assert(!((xfer->dataSize == 0) || (xfer->dataSize % sizeof(uint32_t)))); - if ((xfer->dataSize == 0) || (xfer->dataSize % sizeof(uint32_t))) + + /* Byte size is zero. */ + assert(!(xfer->dataSize == 0)); + if (xfer->dataSize == 0) { return kStatus_InvalidArgument; } @@ -256,13 +251,15 @@ status_t SPI_MasterTransferDMA(SPI_Type *base, spi_dma_handle_t *handle, spi_tra SPI_EnableRxDMA(base, true); if (xfer->rxData) { - DMA_PrepareTransfer(&xferConfig, (void *)&base->FIFORD, xfer->rxData, sizeof(uint32_t), xfer->dataSize, - kDMA_PeripheralToMemory, NULL); + DMA_PrepareTransfer(&xferConfig, ((void *)((uint32_t)&base->FIFORD)), xfer->rxData, + ((spi_config_p->dataWidth > kSPI_Data8Bits) ? (sizeof(uint16_t)) : (sizeof(uint8_t))), + xfer->dataSize, kDMA_PeripheralToMemory, NULL); } else { - DMA_PrepareTransfer(&xferConfig, (void *)&base->FIFORD, &s_rxDummy, sizeof(uint32_t), xfer->dataSize, - kDMA_StaticToStatic, NULL); + DMA_PrepareTransfer(&xferConfig, ((void *)((uint32_t)&base->FIFORD)), &s_rxDummy, + ((spi_config_p->dataWidth > kSPI_Data8Bits) ? (sizeof(uint16_t)) : (sizeof(uint8_t))), + xfer->dataSize, kDMA_StaticToStatic, NULL); } DMA_SubmitTransfer(handle->rxHandle, &xferConfig); handle->rxInProgress = true; @@ -270,21 +267,21 @@ status_t SPI_MasterTransferDMA(SPI_Type *base, spi_dma_handle_t *handle, spi_tra /* transmit */ SPI_EnableTxDMA(base, true); + + if (xfer->configFlags & kSPI_FrameAssert) + { + PrepareTxLastWord(xfer, &s_txLastWord[instance], spi_config_p); + } + if (xfer->txData) { - tmp = 0; - XferToFifoWR(xfer, &tmp); - SpiConfigToFifoWR(spi_config_p, &tmp); - PrepareTxFIFO((uint32_t *)xfer->txData, xfer->dataSize / sizeof(uint32_t), tmp); - DMA_PrepareTransfer(&xferConfig, xfer->txData, (void *)&base->FIFOWR, sizeof(uint32_t), xfer->dataSize, - kDMA_MemoryToPeripheral, NULL); - DMA_SubmitTransfer(handle->txHandle, &xferConfig); - } - else - { - if ((xfer->configFlags & kSPI_FrameAssert) && (xfer->dataSize > sizeof(uint32_t))) + /* If end of tranfer function is enabled and data transfer frame is bigger then 1, use dma + * descriptor to send the last data. + */ + if ((xfer->configFlags & kSPI_FrameAssert) && + ((spi_config_p->dataWidth > kSPI_Data8Bits) ? (xfer->dataSize > 2) : (xfer->dataSize > 1))) { - dma_xfercfg_t tmp_xfercfg = { 0 }; + dma_xfercfg_t tmp_xfercfg = {0}; tmp_xfercfg.valid = true; tmp_xfercfg.swtrig = true; tmp_xfercfg.intA = true; @@ -292,17 +289,16 @@ status_t SPI_MasterTransferDMA(SPI_Type *base, spi_dma_handle_t *handle, spi_tra tmp_xfercfg.srcInc = 0; tmp_xfercfg.dstInc = 0; tmp_xfercfg.transferCount = 1; - /* create chained descriptor to transmit last word */ - SPI_SetupDummy(&s_txDummy[instance].lastWord, xfer, spi_config_p); - DMA_CreateDescriptor(&s_spi_descriptor_table[instance], &tmp_xfercfg, &s_txDummy[instance].lastWord, - (uint32_t *)&base->FIFOWR, NULL); - /* use common API to setup first descriptor */ - SPI_SetupDummy(&s_txDummy[instance].word, NULL, spi_config_p); - DMA_PrepareTransfer(&xferConfig, &s_txDummy[instance].word, (void *)&base->FIFOWR, sizeof(uint32_t), - xfer->dataSize - sizeof(uint32_t), kDMA_StaticToStatic, - &s_spi_descriptor_table[instance]); - /* disable interrupts for first descriptor - * to avoid calling callback twice */ + /* Create chained descriptor to transmit last word */ + DMA_CreateDescriptor(&s_spi_descriptor_table[instance], &tmp_xfercfg, &s_txLastWord[instance], + ((void *)((uint32_t)&base->FIFOWR)), NULL); + + DMA_PrepareTransfer( + &xferConfig, xfer->txData, ((void *)((uint32_t)&base->FIFOWR)), + ((spi_config_p->dataWidth > kSPI_Data8Bits) ? (sizeof(uint16_t)) : (sizeof(uint8_t))), + ((spi_config_p->dataWidth > kSPI_Data8Bits) ? (xfer->dataSize - 2) : (xfer->dataSize - 1)), + kDMA_MemoryToPeripheral, &s_spi_descriptor_table[instance]); + /* Disable interrupts for first descriptor to avoid calling callback twice. */ xferConfig.xfercfg.intA = false; xferConfig.xfercfg.intB = false; result = DMA_SubmitTransfer(handle->txHandle, &xferConfig); @@ -313,9 +309,52 @@ status_t SPI_MasterTransferDMA(SPI_Type *base, spi_dma_handle_t *handle, spi_tra } else { - SPI_SetupDummy(&s_txDummy[instance].word, xfer, spi_config_p); - DMA_PrepareTransfer(&xferConfig, &s_txDummy[instance].word, (void *)&base->FIFOWR, sizeof(uint32_t), - xfer->dataSize, kDMA_StaticToStatic, NULL); + DMA_PrepareTransfer( + &xferConfig, xfer->txData, ((void *)((uint32_t)&base->FIFOWR)), + ((spi_config_p->dataWidth > kSPI_Data8Bits) ? (sizeof(uint16_t)) : (sizeof(uint8_t))), + xfer->dataSize, kDMA_MemoryToPeripheral, NULL); + DMA_SubmitTransfer(handle->txHandle, &xferConfig); + } + } + else + { + /* Setup tx dummy data. */ + SPI_SetupDummy(base, &s_txDummy[instance], xfer, spi_config_p); + if ((xfer->configFlags & kSPI_FrameAssert) && + ((spi_config_p->dataWidth > kSPI_Data8Bits) ? (xfer->dataSize > 2) : (xfer->dataSize > 1))) + { + dma_xfercfg_t tmp_xfercfg = {0}; + tmp_xfercfg.valid = true; + tmp_xfercfg.swtrig = true; + tmp_xfercfg.intA = true; + tmp_xfercfg.byteWidth = sizeof(uint32_t); + tmp_xfercfg.srcInc = 0; + tmp_xfercfg.dstInc = 0; + tmp_xfercfg.transferCount = 1; + /* Create chained descriptor to transmit last word */ + DMA_CreateDescriptor(&s_spi_descriptor_table[instance], &tmp_xfercfg, &s_txDummy[instance].lastWord, + (void *)((uint32_t)&base->FIFOWR), NULL); + /* Use common API to setup first descriptor */ + DMA_PrepareTransfer( + &xferConfig, &s_txDummy[instance].word, ((void *)((uint32_t)&base->FIFOWR)), + ((spi_config_p->dataWidth > kSPI_Data8Bits) ? (sizeof(uint16_t)) : (sizeof(uint8_t))), + ((spi_config_p->dataWidth > kSPI_Data8Bits) ? (xfer->dataSize - 2) : (xfer->dataSize - 1)), + kDMA_StaticToStatic, &s_spi_descriptor_table[instance]); + /* Disable interrupts for first descriptor to avoid calling callback twice */ + xferConfig.xfercfg.intA = false; + xferConfig.xfercfg.intB = false; + result = DMA_SubmitTransfer(handle->txHandle, &xferConfig); + if (result != kStatus_Success) + { + return result; + } + } + else + { + DMA_PrepareTransfer( + &xferConfig, &s_txDummy[instance].word, ((void *)((uint32_t)&base->FIFOWR)), + ((spi_config_p->dataWidth > kSPI_Data8Bits) ? (sizeof(uint16_t)) : (sizeof(uint8_t))), + xfer->dataSize, kDMA_StaticToStatic, NULL); result = DMA_SubmitTransfer(handle->txHandle, &xferConfig); if (result != kStatus_Success) { @@ -323,13 +362,102 @@ status_t SPI_MasterTransferDMA(SPI_Type *base, spi_dma_handle_t *handle, spi_tra } } } + handle->txInProgress = true; + tmp = 0; + XferToFifoWR(xfer, &tmp); + SpiConfigToFifoWR(spi_config_p, &tmp); + + /* Setup the control info. + * Halfword writes to just the control bits (offset 0xE22) doesn't push anything into the FIFO. + * And the data access type of control bits must be uint16_t, byte writes or halfword writes to FIFOWR + * will push the data and the current control bits into the FIFO. + */ + if ((xfer->configFlags & kSPI_FrameAssert) && + ((spi_config_p->dataWidth > kSPI_Data8Bits) ? (xfer->dataSize == 2U) : (xfer->dataSize == 1U))) + { + *(((uint16_t *)((uint32_t) & (base->FIFOWR))) + 1) = (uint16_t)(tmp >> 16U); + } + else + { + /* Clear the SPI_FIFOWR_EOT_MASK bit when data is not the last. */ + tmp &= (uint32_t)(~kSPI_FrameAssert); + *(((uint16_t *)((uint32_t) & (base->FIFOWR))) + 1) = (uint16_t)(tmp >> 16U); + } + DMA_StartTransfer(handle->txHandle); } return result; } +/*! + * brief Transfers a block of data using a DMA method. + * + * This function using polling way to do the first half transimission and using DMA way to + * do the srcond half transimission, the transfer mechanism is half-duplex. + * When do the second half transimission, code will return right away. When all data is transferred, + * the callback function is called. + * + * param base SPI base pointer + * param handle A pointer to the spi_master_dma_handle_t structure which stores the transfer state. + * param transfer A pointer to the spi_half_duplex_transfer_t structure. + * return status of status_t. + */ +status_t SPI_MasterHalfDuplexTransferDMA(SPI_Type *base, spi_dma_handle_t *handle, spi_half_duplex_transfer_t *xfer) +{ + assert(xfer); + assert(handle); + spi_transfer_t tempXfer = {0}; + status_t status; + + if (xfer->isTransmitFirst) + { + tempXfer.txData = xfer->txData; + tempXfer.rxData = NULL; + tempXfer.dataSize = xfer->txDataSize; + } + else + { + tempXfer.txData = NULL; + tempXfer.rxData = xfer->rxData; + tempXfer.dataSize = xfer->rxDataSize; + } + /* If the pcs pin keep assert between transmit and receive. */ + if (xfer->isPcsAssertInTransfer) + { + tempXfer.configFlags = (xfer->configFlags) & (uint32_t)(~kSPI_FrameAssert); + } + else + { + tempXfer.configFlags = (xfer->configFlags) | kSPI_FrameAssert; + } + + status = SPI_MasterTransferBlocking(base, &tempXfer); + if (status != kStatus_Success) + { + return status; + } + + if (xfer->isTransmitFirst) + { + tempXfer.txData = NULL; + tempXfer.rxData = xfer->rxData; + tempXfer.dataSize = xfer->rxDataSize; + } + else + { + tempXfer.txData = xfer->txData; + tempXfer.rxData = NULL; + tempXfer.dataSize = xfer->txDataSize; + } + tempXfer.configFlags = xfer->configFlags; + + status = SPI_MasterTransferDMA(base, handle, &tempXfer); + + return status; +} + static void SPI_RxDMACallback(dma_handle_t *handle, void *userData, bool transferDone, uint32_t intmode) { spi_dma_private_handle_t *privHandle = (spi_dma_private_handle_t *)userData; @@ -370,6 +498,12 @@ static void SPI_TxDMACallback(dma_handle_t *handle, void *userData, bool transfe } } +/*! + * brief Abort a SPI transfer using DMA. + * + * param base SPI peripheral base address. + * param handle SPI DMA handle pointer. + */ void SPI_MasterTransferAbortDMA(SPI_Type *base, spi_dma_handle_t *handle) { assert(NULL != handle); @@ -385,6 +519,16 @@ void SPI_MasterTransferAbortDMA(SPI_Type *base, spi_dma_handle_t *handle) handle->state = kSPI_Idle; } +/*! + * brief Gets the master DMA transfer remaining bytes. + * + * This function gets the master DMA transfer remaining bytes. + * + * param base SPI peripheral base address. + * param handle A pointer to the spi_dma_handle_t structure which stores the transfer state. + * param count A number of bytes transferred by the non-blocking transaction. + * return status of status_t. + */ status_t SPI_MasterTransferGetCountDMA(SPI_Type *base, spi_dma_handle_t *handle, size_t *count) { assert(handle); diff --git a/ext/hal/nxp/mcux/drivers/lpc/fsl_spi_dma.h b/ext/hal/nxp/mcux/drivers/lpc/fsl_spi_dma.h index d4bdf8b16c7..cc7ffe28f28 100644 --- a/ext/hal/nxp/mcux/drivers/lpc/fsl_spi_dma.h +++ b/ext/hal/nxp/mcux/drivers/lpc/fsl_spi_dma.h @@ -1,31 +1,9 @@ /* * Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP + * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * SPDX-License-Identifier: BSD-3-Clause */ #ifndef _FSL_SPI_DMA_H_ #define _FSL_SPI_DMA_H_ @@ -44,6 +22,12 @@ * Definitions ******************************************************************************/ +/*! @name Driver version */ +/*@{*/ +/*! @brief SPI DMA driver version 2.0.3. */ +#define FSL_SPI_DMA_DRIVER_VERSION (MAKE_VERSION(2, 0, 3)) +/*@}*/ + typedef struct _spi_dma_handle spi_dma_handle_t; /*! @brief SPI DMA callback called at the end of transfer. */ @@ -111,6 +95,21 @@ status_t SPI_MasterTransferCreateHandleDMA(SPI_Type *base, */ status_t SPI_MasterTransferDMA(SPI_Type *base, spi_dma_handle_t *handle, spi_transfer_t *xfer); +/*! + * @brief Transfers a block of data using a DMA method. + * + * This function using polling way to do the first half transimission and using DMA way to + * do the srcond half transimission, the transfer mechanism is half-duplex. + * When do the second half transimission, code will return right away. When all data is transferred, + * the callback function is called. + * + * @param base SPI base pointer + * @param handle A pointer to the spi_master_dma_handle_t structure which stores the transfer state. + * @param transfer A pointer to the spi_half_duplex_transfer_t structure. + * @return status of status_t. + */ +status_t SPI_MasterHalfDuplexTransferDMA(SPI_Type *base, spi_dma_handle_t *handle, spi_half_duplex_transfer_t *xfer); + /*! * @brief Initialize the SPI slave DMA handle. * diff --git a/ext/hal/nxp/mcux/drivers/lpc/fsl_usart.c b/ext/hal/nxp/mcux/drivers/lpc/fsl_usart.c index 7e276d3091b..873876604ad 100644 --- a/ext/hal/nxp/mcux/drivers/lpc/fsl_usart.c +++ b/ext/hal/nxp/mcux/drivers/lpc/fsl_usart.c @@ -1,37 +1,20 @@ /* * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP + * Copyright 2016-2018 NXP + * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * SPDX-License-Identifier: BSD-3-Clause */ #include "fsl_usart.h" #include "fsl_device_registers.h" #include "fsl_flexcomm.h" +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.flexcomm_usart" +#endif + enum _usart_transfer_states { kUSART_TxIdle, /* TX idle. */ @@ -55,6 +38,7 @@ static const uint32_t s_usartBaseAddrs[FSL_FEATURE_SOC_USART_COUNT] = USART_BASE ******************************************************************************/ /* Get the index corresponding to the USART */ +/*! brief Returns instance number for USART peripheral base address. */ uint32_t USART_GetInstance(USART_Type *base) { int i; @@ -71,7 +55,13 @@ uint32_t USART_GetInstance(USART_Type *base) return 0; } -static size_t USART_TransferGetRxRingBufferLength(usart_handle_t *handle) +/*! + * brief Get the length of received data in RX ring buffer. + * + * param handle USART handle pointer. + * return Length of received data in RX ring buffer. + */ +size_t USART_TransferGetRxRingBufferLength(usart_handle_t *handle) { size_t size; @@ -107,6 +97,23 @@ static bool USART_TransferIsRxRingBufferFull(usart_handle_t *handle) return full; } +/*! + * brief Sets up the RX ring buffer. + * + * This function sets up the RX ring buffer to a specific USART handle. + * + * When the RX ring buffer is used, data received are stored into the ring buffer even when the + * user doesn't call the USART_TransferReceiveNonBlocking() API. If there is already data received + * in the ring buffer, the user can get the received data from the ring buffer directly. + * + * note When using the RX ring buffer, one byte is reserved for internal use. In other + * words, if p ringBufferSize is 32, then only 31 bytes are used for saving data. + * + * param base USART peripheral base address. + * param handle USART handle pointer. + * param ringBuffer Start address of the ring buffer for background receiving. Pass NULL to disable the ring buffer. + * param ringBufferSize size of the ring buffer. + */ void USART_TransferStartRingBuffer(USART_Type *base, usart_handle_t *handle, uint8_t *ringBuffer, size_t ringBufferSize) { /* Check arguments */ @@ -123,6 +130,14 @@ void USART_TransferStartRingBuffer(USART_Type *base, usart_handle_t *handle, uin base->FIFOINTENSET |= USART_FIFOINTENSET_RXLVL_MASK | USART_FIFOINTENSET_RXERR_MASK; } +/*! + * brief Aborts the background transfer and uninstalls the ring buffer. + * + * This function aborts the background transfer and uninstalls the ring buffer. + * + * param base USART peripheral base address. + * param handle USART handle pointer. + */ void USART_TransferStopRingBuffer(USART_Type *base, usart_handle_t *handle) { /* Check arguments */ @@ -139,6 +154,27 @@ void USART_TransferStopRingBuffer(USART_Type *base, usart_handle_t *handle) handle->rxRingBufferTail = 0U; } +/*! + * brief Initializes a USART instance with user configuration structure and peripheral clock. + * + * This function configures the USART module with the user-defined settings. The user can configure the configuration + * structure and also get the default configuration by using the USART_GetDefaultConfig() function. + * Example below shows how to use this API to configure USART. + * code + * usart_config_t usartConfig; + * usartConfig.baudRate_Bps = 115200U; + * usartConfig.parityMode = kUSART_ParityDisabled; + * usartConfig.stopBitCount = kUSART_OneStopBit; + * USART_Init(USART1, &usartConfig, 20000000U); + * endcode + * + * param base USART peripheral base address. + * param config Pointer to user-defined configuration structure. + * param srcClock_Hz USART clock source frequency in HZ. + * retval kStatus_USART_BaudrateNotSupport Baudrate is not support in current clock source. + * retval kStatus_InvalidArgument USART base address is not valid + * retval kStatus_Success Status USART initialize succeed + */ status_t USART_Init(USART_Type *base, const usart_config_t *config, uint32_t srcClock_Hz) { int result; @@ -191,6 +227,13 @@ status_t USART_Init(USART_Type *base, const usart_config_t *config, uint32_t src return kStatus_Success; } +/*! + * brief Deinitializes a USART instance. + * + * This function waits for TX complete, disables TX and RX, and disables the USART clock. + * + * param base USART peripheral base address. + */ void USART_Deinit(USART_Type *base) { /* Check arguments */ @@ -205,11 +248,29 @@ void USART_Deinit(USART_Type *base) base->CFG &= ~(USART_CFG_ENABLE_MASK); } +/*! + * brief Gets the default configuration structure. + * + * This function initializes the USART configuration structure to a default value. The default + * values are: + * usartConfig->baudRate_Bps = 115200U; + * usartConfig->parityMode = kUSART_ParityDisabled; + * usartConfig->stopBitCount = kUSART_OneStopBit; + * usartConfig->bitCountPerChar = kUSART_8BitsPerChar; + * usartConfig->loopback = false; + * usartConfig->enableTx = false; + * usartConfig->enableRx = false; + * + * param config Pointer to configuration structure. + */ void USART_GetDefaultConfig(usart_config_t *config) { /* Check arguments */ assert(NULL != config); + /* Initializes the configure structure to zero. */ + memset(config, 0, sizeof(*config)); + /* Set always all members ! */ config->baudRate_Bps = 115200U; config->parityMode = kUSART_ParityDisabled; @@ -222,6 +283,22 @@ void USART_GetDefaultConfig(usart_config_t *config) config->rxWatermark = kUSART_RxFifo1; } +/*! + * brief Sets the USART instance baud rate. + * + * This function configures the USART module baud rate. This function is used to update + * the USART module baud rate after the USART module is initialized by the USART_Init. + * code + * USART_SetBaudRate(USART1, 115200U, 20000000U); + * endcode + * + * param base USART peripheral base address. + * param baudrate_Bps USART baudrate to be set. + * param srcClock_Hz USART clock source freqency in HZ. + * retval kStatus_USART_BaudrateNotSupport Baudrate is not support in current clock source. + * retval kStatus_Success Set baudrate succeed. + * retval kStatus_InvalidArgument One or more arguments are invalid. + */ status_t USART_SetBaudRate(USART_Type *base, uint32_t baudrate_Bps, uint32_t srcClock_Hz) { uint32_t best_diff = (uint32_t)-1, best_osrval = 0xf, best_brgval = (uint32_t)-1; @@ -266,6 +343,16 @@ status_t USART_SetBaudRate(USART_Type *base, uint32_t baudrate_Bps, uint32_t src return kStatus_Success; } +/*! + * brief Writes to the TX register using a blocking method. + * + * This function polls the TX register, waits for the TX register to be empty or for the TX FIFO + * to have room and writes data to the TX buffer. + * + * param base USART peripheral base address. + * param data Start address of the data to write. + * param length Size of the data to write. + */ void USART_WriteBlocking(USART_Type *base, const uint8_t *data, size_t length) { /* Check arguments */ @@ -294,6 +381,21 @@ void USART_WriteBlocking(USART_Type *base, const uint8_t *data, size_t length) } } +/*! + * brief Read RX data register using a blocking method. + * + * This function polls the RX register, waits for the RX register to be full or for RX FIFO to + * have data and read data from the TX register. + * + * param base USART peripheral base address. + * param data Start address of the buffer to store the received data. + * param length Size of the buffer. + * retval kStatus_USART_FramingError Receiver overrun happened while receiving data. + * retval kStatus_USART_ParityError Noise error happened while receiving data. + * retval kStatus_USART_NoiseError Framing error happened while receiving data. + * retval kStatus_USART_RxError Overflow or underflow rxFIFO happened. + * retval kStatus_Success Successfully received all data. + */ status_t USART_ReadBlocking(USART_Type *base, uint8_t *data, size_t length) { uint32_t status; @@ -347,6 +449,18 @@ status_t USART_ReadBlocking(USART_Type *base, uint8_t *data, size_t length) return kStatus_Success; } +/*! + * brief Initializes the USART handle. + * + * This function initializes the USART handle which can be used for other USART + * transactional APIs. Usually, for a specified USART instance, + * call this API once to get the initialized handle. + * + * param base USART peripheral base address. + * param handle USART handle pointer. + * param callback The callback function. + * param userData The parameter of the callback function. + */ status_t USART_TransferCreateHandle(USART_Type *base, usart_handle_t *handle, usart_transfer_callback_t callback, @@ -373,7 +487,7 @@ status_t USART_TransferCreateHandle(USART_Type *base, handle->rxWatermark = (usart_rxfifo_watermark_t)USART_FIFOTRIG_RXLVL_GET(base); handle->txWatermark = (usart_txfifo_watermark_t)USART_FIFOTRIG_TXLVL_GET(base); - FLEXCOMM_SetIRQHandler(base, (flexcomm_irq_handler_t)(uintptr_t)USART_TransferHandleIRQ, handle); + FLEXCOMM_SetIRQHandler(base, (flexcomm_irq_handler_t)USART_TransferHandleIRQ, handle); /* Enable interrupt in NVIC. */ EnableIRQ(s_usartIRQ[instance]); @@ -381,6 +495,25 @@ status_t USART_TransferCreateHandle(USART_Type *base, return kStatus_Success; } +/*! + * brief Transmits a buffer of data using the interrupt method. + * + * This function sends data using an interrupt method. This is a non-blocking function, which + * returns directly without waiting for all data to be written to the TX register. When + * all data is written to the TX register in the IRQ handler, the USART driver calls the callback + * function and passes the ref kStatus_USART_TxIdle as status parameter. + * + * note The kStatus_USART_TxIdle is passed to the upper layer when all data is written + * to the TX register. However it does not ensure that all data are sent out. Before disabling the TX, + * check the kUSART_TransmissionCompleteFlag to ensure that the TX is finished. + * + * param base USART peripheral base address. + * param handle USART handle pointer. + * param xfer USART transfer structure. See #usart_transfer_t. + * retval kStatus_Success Successfully start the data transmission. + * retval kStatus_USART_TxBusy Previous transmission still not finished, data not all written to TX register yet. + * retval kStatus_InvalidArgument Invalid argument. + */ status_t USART_TransferSendNonBlocking(USART_Type *base, usart_handle_t *handle, usart_transfer_t *xfer) { /* Check arguments */ @@ -413,12 +546,21 @@ status_t USART_TransferSendNonBlocking(USART_Type *base, usart_handle_t *handle, return kStatus_Success; } +/*! + * brief Aborts the interrupt-driven data transmit. + * + * This function aborts the interrupt driven data sending. The user can get the remainBtyes to find out + * how many bytes are still not sent out. + * + * param base USART peripheral base address. + * param handle USART handle pointer. + */ void USART_TransferAbortSend(USART_Type *base, usart_handle_t *handle) { assert(NULL != handle); /* Disable interrupts */ - base->FIFOINTENSET &= ~USART_FIFOINTENSET_TXLVL_MASK; + USART_DisableInterrupts(base, kUSART_TxLevelInterruptEnable); /* Empty txFIFO */ base->FIFOCFG |= USART_FIFOCFG_EMPTYTX_MASK; @@ -426,6 +568,19 @@ void USART_TransferAbortSend(USART_Type *base, usart_handle_t *handle) handle->txState = kUSART_TxIdle; } +/*! + * brief Get the number of bytes that have been written to USART TX register. + * + * This function gets the number of bytes that have been written to USART TX + * register by interrupt method. + * + * param base USART peripheral base address. + * param handle USART handle pointer. + * param count Send bytes count. + * retval kStatus_NoTransferInProgress No send in progress. + * retval kStatus_InvalidArgument Parameter is invalid. + * retval kStatus_Success Get successfully through the parameter \p count; + */ status_t USART_TransferGetSendCount(USART_Type *base, usart_handle_t *handle, uint32_t *count) { assert(NULL != handle); @@ -441,6 +596,32 @@ status_t USART_TransferGetSendCount(USART_Type *base, usart_handle_t *handle, ui return kStatus_Success; } +/*! + * brief Receives a buffer of data using an interrupt method. + * + * This function receives data using an interrupt method. This is a non-blocking function, which + * returns without waiting for all data to be received. + * If the RX ring buffer is used and not empty, the data in the ring buffer is copied and + * the parameter p receivedBytes shows how many bytes are copied from the ring buffer. + * After copying, if the data in the ring buffer is not enough to read, the receive + * request is saved by the USART driver. When the new data arrives, the receive request + * is serviced first. When all data is received, the USART driver notifies the upper layer + * through a callback function and passes the status parameter ref kStatus_USART_RxIdle. + * For example, the upper layer needs 10 bytes but there are only 5 bytes in the ring buffer. + * The 5 bytes are copied to the xfer->data and this function returns with the + * parameter p receivedBytes set to 5. For the left 5 bytes, newly arrived data is + * saved from the xfer->data[5]. When 5 bytes are received, the USART driver notifies the upper layer. + * If the RX ring buffer is not enabled, this function enables the RX and RX interrupt + * to receive data to the xfer->data. When all data is received, the upper layer is notified. + * + * param base USART peripheral base address. + * param handle USART handle pointer. + * param xfer USART transfer structure, see #usart_transfer_t. + * param receivedBytes Bytes received from the ring buffer directly. + * retval kStatus_Success Successfully queue the transfer into transmit queue. + * retval kStatus_USART_RxBusy Previous receive request is not finished. + * retval kStatus_InvalidArgument Invalid argument. + */ status_t USART_TransferReceiveNonBlocking(USART_Type *base, usart_handle_t *handle, usart_transfer_t *xfer, @@ -551,6 +732,15 @@ status_t USART_TransferReceiveNonBlocking(USART_Type *base, return kStatus_Success; } +/*! + * brief Aborts the interrupt-driven data receiving. + * + * This function aborts the interrupt-driven data receiving. The user can get the remainBytes to find out + * how many bytes not received yet. + * + * param base USART peripheral base address. + * param handle USART handle pointer. + */ void USART_TransferAbortReceive(USART_Type *base, usart_handle_t *handle) { assert(NULL != handle); @@ -559,7 +749,7 @@ void USART_TransferAbortReceive(USART_Type *base, usart_handle_t *handle) if (!handle->rxRingBuffer) { /* Disable interrupts */ - base->FIFOINTENSET &= ~USART_FIFOINTENSET_RXLVL_MASK; + USART_DisableInterrupts(base, kUSART_RxLevelInterruptEnable); /* Empty rxFIFO */ base->FIFOCFG |= USART_FIFOCFG_EMPTYRX_MASK; } @@ -568,6 +758,18 @@ void USART_TransferAbortReceive(USART_Type *base, usart_handle_t *handle) handle->rxState = kUSART_RxIdle; } +/*! + * brief Get the number of bytes that have been received. + * + * This function gets the number of bytes that have been received. + * + * param base USART peripheral base address. + * param handle USART handle pointer. + * param count Receive bytes count. + * retval kStatus_NoTransferInProgress No receive in progress. + * retval kStatus_InvalidArgument Parameter is invalid. + * retval kStatus_Success Get successfully through the parameter \p count; + */ status_t USART_TransferGetReceiveCount(USART_Type *base, usart_handle_t *handle, uint32_t *count) { assert(NULL != handle); @@ -583,6 +785,14 @@ status_t USART_TransferGetReceiveCount(USART_Type *base, usart_handle_t *handle, return kStatus_Success; } +/*! + * brief USART IRQ handle function. + * + * This function handles the USART transmit and receive IRQ request. + * + * param base USART peripheral base address. + * param handle USART handle pointer. + */ void USART_TransferHandleIRQ(USART_Type *base, usart_handle_t *handle) { /* Check arguments */ diff --git a/ext/hal/nxp/mcux/drivers/lpc/fsl_usart.h b/ext/hal/nxp/mcux/drivers/lpc/fsl_usart.h index 3fea97e6ec2..802b61831e2 100644 --- a/ext/hal/nxp/mcux/drivers/lpc/fsl_usart.h +++ b/ext/hal/nxp/mcux/drivers/lpc/fsl_usart.h @@ -1,31 +1,9 @@ /* * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP + * Copyright 2016-2018 NXP + * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * SPDX-License-Identifier: BSD-3-Clause */ #ifndef _FSL_USART_H_ #define _FSL_USART_H_ @@ -43,8 +21,8 @@ /*! @name Driver version */ /*@{*/ -/*! @brief USART driver version 2.0.0. */ -#define FSL_USART_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) +/*! @brief USART driver version 2.0.3. */ +#define FSL_USART_DRIVER_VERSION (MAKE_VERSION(2, 0, 3)) /*@}*/ #define USART_FIFOTRIG_TXLVL_GET(base) (((base)->FIFOTRIG & USART_FIFOTRIG_TXLVL_MASK) >> USART_FIFOTRIG_TXLVL_SHIFT) @@ -366,7 +344,19 @@ static inline void USART_EnableInterrupts(USART_Type *base, uint32_t mask) */ static inline void USART_DisableInterrupts(USART_Type *base, uint32_t mask) { - base->FIFOINTENSET = ~(mask & 0xF); + base->FIFOINTENCLR = mask & 0xF; +} + +/*! + * @brief Returns enabled USART interrupts. + * + * This function returns the enabled USART interrupts. + * + * @param base USART peripheral base address. + */ +static inline uint32_t USART_GetEnabledInterrupts(USART_Type *base) +{ + return base->FIFOINTENSET; } /*! @@ -399,6 +389,25 @@ static inline void USART_EnableRxDMA(USART_Type *base, bool enable) } } +/*! + * @brief Enable CTS. + * This function will determine whether CTS is used for flow control. + * + * @param base USART peripheral base address. + * @param enable Enable CTS or not, true for enable and false for disable. + */ +static inline void USART_EnableCTS(USART_Type *base, bool enable) +{ + if (enable) + { + base->CFG |= USART_CFG_CTSEN_MASK; + } + else + { + base->CFG &= ~USART_CFG_CTSEN_MASK; + } +} + /* @} */ /*! @@ -540,6 +549,14 @@ void USART_TransferStartRingBuffer(USART_Type *base, */ void USART_TransferStopRingBuffer(USART_Type *base, usart_handle_t *handle); +/*! + * @brief Get the length of received data in RX ring buffer. + * + * @param handle USART handle pointer. + * @return Length of received data in RX ring buffer. + */ +size_t USART_TransferGetRxRingBufferLength(usart_handle_t *handle); + /*! * @brief Aborts the interrupt-driven data transmit. * diff --git a/ext/hal/nxp/mcux/drivers/lpc/fsl_usart_dma.c b/ext/hal/nxp/mcux/drivers/lpc/fsl_usart_dma.c index 129419eace6..0e39a7a0694 100644 --- a/ext/hal/nxp/mcux/drivers/lpc/fsl_usart_dma.c +++ b/ext/hal/nxp/mcux/drivers/lpc/fsl_usart_dma.c @@ -1,31 +1,9 @@ /* * Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP + * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * SPDX-License-Identifier: BSD-3-Clause */ #include "fsl_usart.h" @@ -34,6 +12,11 @@ #include "fsl_flexcomm.h" #include "fsl_usart_dma.h" +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.flexcomm_usart_dma" +#endif + /*data, (void *)&base->FIFOWR, sizeof(uint8_t), xfer->dataSize, - kDMA_MemoryToPeripheral, NULL); + DMA_PrepareTransfer(&xferConfig, xfer->data, ((void *)((uint32_t)&base->FIFOWR)), sizeof(uint8_t), + xfer->dataSize, kDMA_MemoryToPeripheral, NULL); /* Submit transfer. */ DMA_SubmitTransfer(handle->txDmaHandle, &xferConfig); @@ -186,6 +191,19 @@ status_t USART_TransferSendDMA(USART_Type *base, usart_dma_handle_t *handle, usa return status; } +/*! + * brief Receives data using DMA. + * + * This function receives data using DMA. This is a non-blocking function, which returns + * right away. When all data is received, the receive callback function is called. + * + * param base USART peripheral base address. + * param handle Pointer to usart_dma_handle_t structure. + * param xfer USART DMA transfer structure. See #usart_transfer_t. + * retval kStatus_Success if succeed, others failed. + * retval kStatus_USART_RxBusy Previous transfer on going. + * retval kStatus_InvalidArgument Invalid argument. + */ status_t USART_TransferReceiveDMA(USART_Type *base, usart_dma_handle_t *handle, usart_transfer_t *xfer) { assert(handle); @@ -211,8 +229,8 @@ status_t USART_TransferReceiveDMA(USART_Type *base, usart_dma_handle_t *handle, USART_EnableRxDMA(base, true); /* Prepare transfer. */ - DMA_PrepareTransfer(&xferConfig, (void *)&base->FIFORD, xfer->data, sizeof(uint8_t), xfer->dataSize, - kDMA_PeripheralToMemory, NULL); + DMA_PrepareTransfer(&xferConfig, ((void *)((uint32_t)&base->FIFORD)), xfer->data, sizeof(uint8_t), + xfer->dataSize, kDMA_PeripheralToMemory, NULL); /* Submit transfer. */ DMA_SubmitTransfer(handle->rxDmaHandle, &xferConfig); @@ -224,6 +242,14 @@ status_t USART_TransferReceiveDMA(USART_Type *base, usart_dma_handle_t *handle, return status; } +/*! + * brief Aborts the sent data using DMA. + * + * This function aborts send data using DMA. + * + * param base USART peripheral base address + * param handle Pointer to usart_dma_handle_t structure + */ void USART_TransferAbortSendDMA(USART_Type *base, usart_dma_handle_t *handle) { assert(NULL != handle); @@ -234,6 +260,14 @@ void USART_TransferAbortSendDMA(USART_Type *base, usart_dma_handle_t *handle) handle->txState = kUSART_TxIdle; } +/*! + * brief Aborts the received data using DMA. + * + * This function aborts the received data using DMA. + * + * param base USART peripheral base address + * param handle Pointer to usart_dma_handle_t structure + */ void USART_TransferAbortReceiveDMA(USART_Type *base, usart_dma_handle_t *handle) { assert(NULL != handle); @@ -244,6 +278,18 @@ void USART_TransferAbortReceiveDMA(USART_Type *base, usart_dma_handle_t *handle) handle->rxState = kUSART_RxIdle; } +/*! + * brief Get the number of bytes that have been received. + * + * This function gets the number of bytes that have been received. + * + * param base USART peripheral base address. + * param handle USART handle pointer. + * param count Receive bytes count. + * retval kStatus_NoTransferInProgress No receive in progress. + * retval kStatus_InvalidArgument Parameter is invalid. + * retval kStatus_Success Get successfully through the parameter \p count; + */ status_t USART_TransferGetReceiveCountDMA(USART_Type *base, usart_dma_handle_t *handle, uint32_t *count) { assert(handle); diff --git a/ext/hal/nxp/mcux/drivers/lpc/fsl_usart_dma.h b/ext/hal/nxp/mcux/drivers/lpc/fsl_usart_dma.h index e28692cf3f5..a0c13927026 100644 --- a/ext/hal/nxp/mcux/drivers/lpc/fsl_usart_dma.h +++ b/ext/hal/nxp/mcux/drivers/lpc/fsl_usart_dma.h @@ -1,31 +1,9 @@ /* * Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause */ #ifndef _FSL_USART_DMA_H_ #define _FSL_USART_DMA_H_ @@ -45,6 +23,12 @@ * Definitions ******************************************************************************/ +/*! @name Driver version */ +/*@{*/ +/*! @brief USART dma driver version 2.0.1. */ +#define FSL_USART_DMA_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) +/*@}*/ + /* Forward declaration of the handle typedef. */ typedef struct _usart_dma_handle usart_dma_handle_t; diff --git a/ext/hal/nxp/mcux/drivers/lpc/fsl_utick.c b/ext/hal/nxp/mcux/drivers/lpc/fsl_utick.c index b1b208e8561..b7c32c8922a 100644 --- a/ext/hal/nxp/mcux/drivers/lpc/fsl_utick.c +++ b/ext/hal/nxp/mcux/drivers/lpc/fsl_utick.c @@ -1,31 +1,9 @@ /* * Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP + * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * SPDX-License-Identifier: BSD-3-Clause */ #include "fsl_utick.h" @@ -34,6 +12,11 @@ * Definitions ******************************************************************************/ +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.utick" +#endif + /* Typedef for interrupt handler. */ typedef void (*utick_isr_t)(UTICK_Type *base, utick_callback_t cb); @@ -62,6 +45,12 @@ static const IRQn_Type s_utickIRQ[] = UTICK_IRQS; /* Array of UTICK clock name. */ static const clock_ip_name_t s_utickClock[] = UTICK_CLOCKS; #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#if !(defined(FSL_FEATURE_UTICK_HAS_NO_RESET) && FSL_FEATURE_UTICK_HAS_NO_RESET) +/*! @brief Pointers to UTICK resets for each instance. */ +static const reset_ip_name_t s_utickResets[] = UTICK_RSTS; +#endif + /* UTICK ISR for transactional APIs. */ static utick_isr_t s_utickIsr; @@ -86,6 +75,17 @@ static uint32_t UTICK_GetInstance(UTICK_Type *base) return instance; } +/*! + * brief Starts UTICK. + * + * This function starts a repeat/onetime countdown with an optional callback + * + * param base UTICK peripheral base address. + * param mode UTICK timer mode (ie kUTICK_onetime or kUTICK_repeat) + * param count UTICK timer mode (ie kUTICK_onetime or kUTICK_repeat) + * param cb UTICK callback (can be left as NULL if none, otherwise should be a void func(void)) + * return none + */ void UTICK_SetTick(UTICK_Type *base, utick_mode_t mode, uint32_t count, utick_callback_t cb) { uint32_t instance; @@ -99,33 +99,80 @@ void UTICK_SetTick(UTICK_Type *base, utick_mode_t mode, uint32_t count, utick_ca base->CTRL = count | UTICK_CTRL_REPEAT(mode); } +/*! +* brief Initializes an UTICK by turning its bus clock on +* +*/ void UTICK_Init(UTICK_Type *base) { +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) /* Enable utick clock */ CLOCK_EnableClock(s_utickClock[UTICK_GetInstance(base)]); +#endif + +#if !(defined(FSL_FEATURE_UTICK_HAS_NO_RESET) && FSL_FEATURE_UTICK_HAS_NO_RESET) + RESET_PeripheralReset(s_utickResets[UTICK_GetInstance(base)]); +#endif + /* Power up Watchdog oscillator*/ POWER_DisablePD(kPDRUNCFG_PD_WDT_OSC); s_utickIsr = UTICK_HandleIRQ; } +/*! + * brief Deinitializes a UTICK instance. + * + * This function shuts down Utick bus clock + * + * param base UTICK peripheral base address. + */ void UTICK_Deinit(UTICK_Type *base) { /* Turn off utick */ base->CTRL = 0; +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) /* Disable utick clock */ CLOCK_DisableClock(s_utickClock[UTICK_GetInstance(base)]); +#endif } +/*! + * brief Get Status Flags. + * + * This returns the status flag + * + * param base UTICK peripheral base address. + * return status register value + */ uint32_t UTICK_GetStatusFlags(UTICK_Type *base) { return (base->STAT); } +/*! + * brief Clear Status Interrupt Flags. + * + * This clears intr status flag + * + * param base UTICK peripheral base address. + * return none + */ void UTICK_ClearStatusFlags(UTICK_Type *base) { base->STAT = UTICK_STAT_INTR_MASK; } +/*! + * brief UTICK Interrupt Service Handler. + * + * This function handles the interrupt and refers to the callback array in the driver to callback user (as per request + * in UTICK_SetTick()). + * if no user callback is scheduled, the interrupt will simply be cleared. + * + * param base UTICK peripheral base address. + * param cb callback scheduled for this instance of UTICK + * return none + */ void UTICK_HandleIRQ(UTICK_Type *base, utick_callback_t cb) { UTICK_ClearStatusFlags(base); @@ -139,17 +186,32 @@ void UTICK_HandleIRQ(UTICK_Type *base, utick_callback_t cb) void UTICK0_DriverIRQHandler(void) { s_utickIsr(UTICK0, s_utickHandle[0]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif } #endif #if defined(UTICK1) void UTICK1_DriverIRQHandler(void) { s_utickIsr(UTICK1, s_utickHandle[1]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif } #endif #if defined(UTICK2) void UTICK2_DriverIRQHandler(void) { s_utickIsr(UTICK2, s_utickHandle[2]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif } #endif diff --git a/ext/hal/nxp/mcux/drivers/lpc/fsl_utick.h b/ext/hal/nxp/mcux/drivers/lpc/fsl_utick.h index 6aa617d9335..40edb49d9ad 100644 --- a/ext/hal/nxp/mcux/drivers/lpc/fsl_utick.h +++ b/ext/hal/nxp/mcux/drivers/lpc/fsl_utick.h @@ -1,31 +1,9 @@ /* * Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP + * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * SPDX-License-Identifier: BSD-3-Clause */ #ifndef _FSL_UTICK_H_ #define _FSL_UTICK_H_ @@ -44,8 +22,8 @@ /*! @name Driver version */ /*@{*/ -/*! @brief UTICK driver version 2.0.0. */ -#define FSL_UTICK_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) +/*! @brief UTICK driver version 2.0.1. */ +#define FSL_UTICK_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) /*@}*/ /*! @brief UTICK timer operational mode. */ diff --git a/ext/hal/nxp/mcux/drivers/lpc/fsl_wwdt.c b/ext/hal/nxp/mcux/drivers/lpc/fsl_wwdt.c index 43c44de667b..ccae21b9686 100644 --- a/ext/hal/nxp/mcux/drivers/lpc/fsl_wwdt.c +++ b/ext/hal/nxp/mcux/drivers/lpc/fsl_wwdt.c @@ -1,35 +1,18 @@ /* * Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP + * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * SPDX-License-Identifier: BSD-3-Clause */ #include "fsl_wwdt.h" +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.wwdt" +#endif + /******************************************************************************* * Prototypes ******************************************************************************/ @@ -54,8 +37,12 @@ static WWDT_Type *const s_wwdtBases[] = WWDT_BASE_PTRS; static const clock_ip_name_t s_wwdtClocks[] = WWDT_CLOCKS; #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) +#if !(defined(FSL_FEATURE_WWDT_HAS_NO_RESET) && FSL_FEATURE_WWDT_HAS_NO_RESET) /*! @brief Pointers to WWDT resets for each instance. */ static const reset_ip_name_t s_wwdtResets[] = WWDT_RSTS; +#endif +#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ /******************************************************************************* * Code @@ -83,10 +70,31 @@ static uint32_t WWDT_GetInstance(WWDT_Type *base) * Code ******************************************************************************/ +/*! + * brief Initializes WWDT configure sturcture. + * + * This function initializes the WWDT configure structure to default value. The default + * value are: + * code + * config->enableWwdt = true; + * config->enableWatchdogReset = false; + * config->enableWatchdogProtect = false; + * config->enableLockOscillator = false; + * config->windowValue = 0xFFFFFFU; + * config->timeoutValue = 0xFFFFFFU; + * config->warningValue = 0; + * endcode + * + * param config Pointer to WWDT config structure. + * see wwdt_config_t + */ void WWDT_GetDefaultConfig(wwdt_config_t *config) { assert(config); + /* Initializes the configure structure to zero. */ + memset(config, 0, sizeof(*config)); + /* Enable the watch dog */ config->enableWwdt = true; /* Disable the watchdog timeout reset */ @@ -101,31 +109,76 @@ void WWDT_GetDefaultConfig(wwdt_config_t *config) config->timeoutValue = 0xFFFFFFU; /* No warning is provided */ config->warningValue = 0; + /* Set clock frequency. */ + config->clockFreq_Hz = 0U; } +/*! + * brief Initializes the WWDT. + * + * This function initializes the WWDT. When called, the WWDT runs according to the configuration. + * + * Example: + * code + * wwdt_config_t config; + * WWDT_GetDefaultConfig(&config); + * config.timeoutValue = 0x7ffU; + * WWDT_Init(wwdt_base,&config); + * endcode + * + * param base WWDT peripheral base address + * param config The configuration of WWDT + */ void WWDT_Init(WWDT_Type *base, const wwdt_config_t *config) { assert(config); + /* The config->clockFreq_Hz must be set in order to config the delay time. */ + assert(config->clockFreq_Hz); uint32_t value = 0U; + uint32_t timeDelay = 0U; + + timeDelay = (SystemCoreClock / config->clockFreq_Hz + 1) * 3; #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) /* Enable the WWDT clock */ CLOCK_EnableClock(s_wwdtClocks[WWDT_GetInstance(base)]); #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - /* Reset the WWDT module */ +#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) +#if !(defined(FSL_FEATURE_WWDT_HAS_NO_RESET) && FSL_FEATURE_WWDT_HAS_NO_RESET) + /* Reset the module. */ RESET_PeripheralReset(s_wwdtResets[WWDT_GetInstance(base)]); +#endif +#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ value = WWDT_MOD_WDEN(config->enableWwdt) | WWDT_MOD_WDRESET(config->enableWatchdogReset) | - WWDT_MOD_WDPROTECT(config->enableWatchdogProtect) | WWDT_MOD_LOCK(config->enableLockOscillator); + WWDT_MOD_LOCK(config->enableLockOscillator); /* Set configruation */ - base->WINDOW = WWDT_WINDOW_WINDOW(config->windowValue); base->TC = WWDT_TC_COUNT(config->timeoutValue); + base->MOD |= value; + base->WINDOW = WWDT_WINDOW_WINDOW(config->windowValue); base->WARNINT = WWDT_WARNINT_WARNINT(config->warningValue); - base->MOD = value; + WWDT_Refresh(base); + /* This WDPROTECT bit can be set once by software and is only cleared by a reset */ + if ((base->MOD & WWDT_MOD_WDPROTECT_MASK) == 0U) + { + /* Set the WDPROTECT bit after the Feed Sequence (0xAA, 0x55) with 3 WDCLK delay */ + while (timeDelay--) + { + __NOP(); + } + base->MOD |= WWDT_MOD_WDPROTECT(config->enableWatchdogProtect); + } } +/*! + * brief Shuts down the WWDT. + * + * This function shuts down the WWDT. + * + * param base WWDT peripheral base address + */ void WWDT_Deinit(WWDT_Type *base) { WWDT_Disable(base); @@ -136,6 +189,14 @@ void WWDT_Deinit(WWDT_Type *base) #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ } +/*! + * brief Refreshes the WWDT timer. + * + * This function feeds the WWDT. + * This function should be called before WWDT timer is in timeout. Otherwise, a reset is asserted. + * + * param base WWDT peripheral base address + */ void WWDT_Refresh(WWDT_Type *base) { uint32_t primaskValue = 0U; @@ -147,6 +208,19 @@ void WWDT_Refresh(WWDT_Type *base) EnableGlobalIRQ(primaskValue); } +/*! + * brief Clear WWDT flag. + * + * This function clears WWDT status flag. + * + * Example for clearing warning flag: + * code + * WWDT_ClearStatusFlags(wwdt_base, kWWDT_WarningFlag); + * endcode + * param base WWDT peripheral base address + * param mask The status flags to clear. This is a logical OR of members of the + * enumeration ::_wwdt_status_flags_t + */ void WWDT_ClearStatusFlags(WWDT_Type *base, uint32_t mask) { /* Clear the WDINT bit so that we don't accidentally clear it */ diff --git a/ext/hal/nxp/mcux/drivers/lpc/fsl_wwdt.h b/ext/hal/nxp/mcux/drivers/lpc/fsl_wwdt.h index 02916aa2f24..ea0abe78ebb 100644 --- a/ext/hal/nxp/mcux/drivers/lpc/fsl_wwdt.h +++ b/ext/hal/nxp/mcux/drivers/lpc/fsl_wwdt.h @@ -1,31 +1,9 @@ /* * Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP + * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * SPDX-License-Identifier: BSD-3-Clause */ #ifndef _FSL_WWDT_H_ #define _FSL_WWDT_H_ @@ -45,8 +23,8 @@ /*! @name Driver version */ /*@{*/ -/*! @brief Defines WWDT driver version 2.0.0. */ -#define FSL_WWDT_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) +/*! @brief Defines WWDT driver version 2.1.0. */ +#define FSL_WWDT_DRIVER_VERSION (MAKE_VERSION(2, 1, 0)) /*@}*/ /*! @name Refresh sequence */ @@ -72,7 +50,7 @@ typedef struct _wwdt_config uint32_t timeoutValue; /*!< Timeout value */ uint32_t warningValue; /*!< Watchdog time counter value that will generate a warning interrupt. Set this to 0 for no warning */ - + uint32_t clockFreq_Hz; /*!< Watchdog clock source frequency. */ } wwdt_config_t; /*! diff --git a/soc/arm/nxp_lpc/lpc54xxx/soc.c b/soc/arm/nxp_lpc/lpc54xxx/soc.c index b5c02a3d5ff..9fe3462adc1 100644 --- a/soc/arm/nxp_lpc/lpc54xxx/soc.c +++ b/soc/arm/nxp_lpc/lpc54xxx/soc.c @@ -150,12 +150,12 @@ int _slave_init(struct device *arg) *(uint32_t *)CORE_M0_BOOT_ADDRESS); /* Reset the secondary core and start its clocks */ - temp = SYSCON->CPCTRL; + temp = SYSCON->CPUCTRL; temp |= 0xc0c48000; - SYSCON->CPCTRL = (temp | SYSCON_CPCTRL_CM0CLKEN_MASK - | SYSCON_CPCTRL_CM0RSTEN_MASK); - SYSCON->CPCTRL = (temp | SYSCON_CPCTRL_CM0CLKEN_MASK) - & (~SYSCON_CPCTRL_CM0RSTEN_MASK); + SYSCON->CPUCTRL = (temp | SYSCON_CPUCTRL_CM0CLKEN_MASK + | SYSCON_CPUCTRL_CM0RSTEN_MASK); + SYSCON->CPUCTRL = (temp | SYSCON_CPUCTRL_CM0CLKEN_MASK) + & (~SYSCON_CPUCTRL_CM0RSTEN_MASK); return 0; }