diff --git a/drivers/spi/CMakeLists.txt b/drivers/spi/CMakeLists.txt
index 11af01462b3..cb9343eaea2 100644
--- a/drivers/spi/CMakeLists.txt
+++ b/drivers/spi/CMakeLists.txt
@@ -7,6 +7,7 @@ else()
   zephyr_sources_ifdef(CONFIG_SPI_STM32		spi_ll_stm32.c)
   zephyr_sources_ifdef(CONFIG_SPI_MCUX_DSPI	spi_mcux_dspi.c)
   zephyr_sources_ifdef(CONFIG_SPI_SAM0		spi_sam0.c)
+  zephyr_sources_ifdef(CONFIG_NRFX_SPI		spi_nrfx_spi.c)
 endif()
 
 zephyr_sources_ifdef(CONFIG_USERSPACE		spi_handlers.c)
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index e80bdfc8520..d2fb2a4f474 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -313,6 +313,8 @@ source "drivers/spi/Kconfig.mcux_dspi"
 
 source "drivers/spi/Kconfig.sam0"
 
+source "drivers/spi/Kconfig.nrfx"
+
 endif # !SPI_LEGACY_API
 
 endif # SPI
diff --git a/drivers/spi/Kconfig.nrfx b/drivers/spi/Kconfig.nrfx
new file mode 100644
index 00000000000..cd24b2b5f7c
--- /dev/null
+++ b/drivers/spi/Kconfig.nrfx
@@ -0,0 +1,210 @@
+# Copyright (c) 2017 - 2018, Nordic Semiconductor ASA
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+menuconfig SPI_NRFX
+	bool "nRF SPI nrfx drivers"
+	depends on SOC_FAMILY_NRF
+	help
+	  Enable support for nrfx SPI drivers for nRF MCU series.
+	  Peripherals with the same instance ID cannot be used together,
+	  e.g. SPI_0 and I2C_0. You may need to disable I2C_0 or I2C_1.
+
+if SPI_NRFX
+
+# Nordic TWIx0 and SPIx0 instances can not be used at the same time
+if SPI_0 && !I2C_0
+
+choice
+	prompt "SPI Port 0 Driver type"
+	optional
+
+config SPI_0_NRF_SPI
+	bool "nRF SPI 0"
+	depends on SOC_SERIES_NRF52X || SOC_SERIES_NRF51X
+	select NRFX_SPI
+	help
+	  Enable nRF SPI Master without EasyDMA on port 0
+
+config SPI_0_NRF_SPIM
+	bool "nRF SPIM 0"
+	depends on SOC_SERIES_NRF52X
+	select NRFX_SPIM
+	help
+	  Enable nRF SPI Master with EasyDMA on port 0
+
+config SPI_0_NRF_SPIS
+	bool "nRF SPIS 0"
+	depends on SOC_SERIES_NRF52X
+	select NRFX_SPIS
+	help
+	  Enable nRF SPI Slave with EasyDMA on port 0
+
+endchoice
+
+if SPI_0_NRF_SPI || SPI_0_NRF_SPIM || SPI_0_NRF_SPIS
+
+config SPI_0_NRF_SCK_PIN
+	int "SCK pin number"
+	range 0 47 if SOC_NRF52840_QIAA
+	range 0 31
+	help
+	  GPIO pin number to use for SCK
+
+config SPI_0_NRF_MOSI_PIN
+	int "MOSI pin number"
+	range 0 47 if SOC_NRF52840_QIAA
+	range 0 31
+	help
+	  GPIO pin number to use for MOSI
+
+config SPI_0_NRF_MISO_PIN
+	int "MISO pin number"
+	range 0 47 if SOC_NRF52840_QIAA
+	range 0 31
+	help
+	  GPIO pin number to use for MISO
+
+config SPI_0_NRF_ORC
+	hex "Over-read Character"
+	range 0x00 0xff
+	default 0xff
+	help
+	  Over-read character. Character clocked out after an over-read
+	  of the transmit buffer.
+
+endif # SPI_0_NRF_SPI || SPI_0_NRF_SPIM || SPI_0_NRF_SPIS
+
+endif # SPI_0 && !I2C_0
+
+# Nordic TWIx1 and SPIx1 instances can not be used at the same time
+if SPI_1 && !I2C_1
+
+choice
+	prompt "SPI Port 1 Driver type"
+	optional
+
+config SPI_1_NRF_SPI
+	bool "nRF SPI 1"
+	depends on SOC_SERIES_NRF52X || SOC_SERIES_NRF51X
+	select NRFX_SPI
+	help
+	  Enable nRF SPI Master without EasyDMA on port 1
+
+config SPI_1_NRF_SPIM
+	bool "nRF SPIM 1"
+	depends on SOC_SERIES_NRF52X
+	select NRFX_SPIM
+	help
+	  Enable nRF SPI Master with EasyDMA on port 1
+
+config SPI_1_NRF_SPIS
+	bool "nRF SPIS 1"
+	depends on SOC_SERIES_NRF52X || SOC_SERIES_NRF51X
+	select NRFX_SPIS
+	help
+	  Enable nRF SPI Slave with EasyDMA on port 1
+
+endchoice
+
+if SPI_1_NRF_SPI || SPI_1_NRF_SPIM || SPI_1_NRF_SPIS
+
+config SPI_1_NRF_SCK_PIN
+	int "SCK pin number"
+	range 0 47 if SOC_NRF52840_QIAA
+	range 0 31
+	help
+	  GPIO pin number to use for SCK
+
+config SPI_1_NRF_MOSI_PIN
+	int "MOSI pin number"
+	range 0 47 if SOC_NRF52840_QIAA
+	range 0 31
+	help
+	  GPIO pin number to use for MOSI
+
+config SPI_1_NRF_MISO_PIN
+	int "MISO pin number"
+	range 0 47 if SOC_NRF52840_QIAA
+	range 0 31
+	help
+	  GPIO pin number to use for MISO
+
+config SPI_1_NRF_ORC
+	hex "Over-read Character"
+	range 0x00 0xff
+	default 0xff
+	help
+	  Over-read character. Character clocked out after an over-read
+	  of the transmit buffer.
+
+endif # SPI_1_NRF_SPI || SPI_1_NRF_SPIM || SPI_1_NRF_SPIS
+
+endif # SPI_1 && !I2C_1
+
+if SPI_2
+
+choice
+	prompt "SPI Port 2 Driver type"
+	optional
+
+config SPI_2_NRF_SPI
+	bool "nRF SPI 2"
+	depends on SOC_SERIES_NRF52X
+	select NRFX_SPI
+	help
+	  Enable nRF SPI Master without EasyDMA on port 2
+
+config SPI_2_NRF_SPIM
+	bool "nRF SPIM 2"
+	depends on SOC_SERIES_NRF52X
+	select NRFX_SPIM
+	help
+	  Enable nRF SPI Master with EasyDMA on port 2
+
+config SPI_2_NRF_SPIS
+	bool "nRF SPIS 2"
+	depends on SOC_SERIES_NRF52X
+	select NRFX_SPIS
+	help
+	  Enable nRF SPI Slave with EasyDMA on port 2
+
+endchoice
+
+if SPI_2_NRF_SPI || SPI_2_NRF_SPIM || SPI_2_NRF_SPIS
+
+config SPI_2_NRF_SCK_PIN
+	int "SCK pin number"
+	range 0 47 if SOC_NRF52840_QIAA
+	range 0 31
+	help
+	  GPIO pin number to use for SCK
+
+config SPI_2_NRF_MOSI_PIN
+	int "MOSI pin number"
+	range 0 47 if SOC_NRF52840_QIAA
+	range 0 31
+	help
+	  GPIO pin number to use for MOSI
+
+config SPI_2_NRF_MISO_PIN
+	int "MISO pin number"
+	range 0 47 if SOC_NRF52840_QIAA
+	range 0 31
+	help
+	  GPIO pin number to use for MISO
+
+config SPI_2_NRF_ORC
+	hex "Over-read Character"
+	range 0x00 0xff
+	default 0xff
+	help
+	  Over-read character. Character clocked out after an over-read
+	  of the transmit buffer.
+
+endif # SPI_2_NRF_SPI || SPI_2_NRF_SPIM || SPI_2_NRF_SPIS
+
+endif # SPI_2
+
+endif # SPI_NRFX
diff --git a/drivers/spi/spi_nrfx_spi.c b/drivers/spi/spi_nrfx_spi.c
new file mode 100644
index 00000000000..86ad7dbf3f8
--- /dev/null
+++ b/drivers/spi/spi_nrfx_spi.c
@@ -0,0 +1,328 @@
+/*
+ * Copyright (c) 2017 - 2018, Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <spi.h>
+#include <nrfx_spi.h>
+
+#define SYS_LOG_DOMAIN "spi_nrfx_spi"
+#define SYS_LOG_LEVEL CONFIG_SYS_LOG_SPI_LEVEL
+#include <logging/sys_log.h>
+
+#include "spi_context.h"
+
+struct spi_nrfx_data {
+	struct spi_context ctx;
+	size_t chunk_len;
+	bool   busy;
+};
+
+struct spi_nrfx_config {
+	nrfx_spi_t spi;
+};
+
+static inline struct spi_nrfx_data *get_dev_data(struct device *dev)
+{
+	return dev->driver_data;
+}
+
+static inline const struct spi_nrfx_config *get_dev_config(struct device *dev)
+{
+	return dev->config->config_info;
+}
+
+static inline nrf_spi_frequency_t get_nrf_spi_frequency(u32_t frequency)
+{
+	/* Get the highest supported frequency not exceeding the requested one.
+	 */
+	if (frequency < 250000) {
+		return NRF_SPI_FREQ_125K;
+	} else if (frequency < 500000) {
+		return NRF_SPI_FREQ_250K;
+	} else if (frequency < 1000000) {
+		return NRF_SPI_FREQ_500K;
+	} else if (frequency < 2000000) {
+		return NRF_SPI_FREQ_1M;
+	} else if (frequency < 4000000) {
+		return NRF_SPI_FREQ_2M;
+	} else if (frequency < 8000000) {
+		return NRF_SPI_FREQ_4M;
+	} else {
+		return NRF_SPI_FREQ_8M;
+	}
+}
+
+static inline nrf_spi_mode_t get_nrf_spi_mode(u16_t operation)
+{
+	if (SPI_MODE_GET(operation) & SPI_MODE_CPOL) {
+		if (SPI_MODE_GET(operation) & SPI_MODE_CPHA) {
+			return NRF_SPI_MODE_3;
+		} else {
+			return NRF_SPI_MODE_2;
+		}
+	} else {
+		if (SPI_MODE_GET(operation) & SPI_MODE_CPHA) {
+			return NRF_SPI_MODE_1;
+		} else {
+			return NRF_SPI_MODE_0;
+		}
+	}
+}
+
+static inline nrf_spi_bit_order_t get_nrf_spi_bit_order(u16_t operation)
+{
+	if (operation & SPI_TRANSFER_LSB) {
+		return NRF_SPI_BIT_ORDER_LSB_FIRST;
+	} else {
+		return NRF_SPI_BIT_ORDER_MSB_FIRST;
+	}
+}
+
+static int configure(struct device *dev,
+		     const struct spi_config *spi_cfg)
+{
+	struct spi_context *ctx = &get_dev_data(dev)->ctx;
+	const nrfx_spi_t *spi = &get_dev_config(dev)->spi;
+
+	if (spi_context_configured(ctx, spi_cfg)) {
+		/* Already configured. No need to do it again. */
+		return 0;
+	}
+
+	if (spi_cfg->operation & SPI_OP_MODE_SLAVE) {
+		SYS_LOG_ERR("Slave mode is not supported for %s",
+			    dev->config->name);
+		return -EINVAL;
+	}
+
+	if (spi_cfg->operation & SPI_MODE_LOOP) {
+		SYS_LOG_ERR("Loopback mode is not supported");
+		return -EINVAL;
+	}
+
+	if ((spi_cfg->operation & SPI_LINES_MASK) != SPI_LINES_SINGLE) {
+		SYS_LOG_ERR("Only single line mode is supported");
+		return -EINVAL;
+	}
+
+	if (SPI_WORD_SIZE_GET(spi_cfg->operation) != 8) {
+		SYS_LOG_ERR("Word sizes other than 8 bits"
+			    " are not supported");
+		return -EINVAL;
+	}
+
+	if (spi_cfg->frequency < 125000) {
+		SYS_LOG_ERR("Frequencies lower than 125 kHz are not supported");
+		return -EINVAL;
+	}
+
+	ctx->config = spi_cfg;
+	spi_context_cs_configure(ctx);
+
+	nrf_spi_configure(spi->p_reg,
+			  get_nrf_spi_mode(spi_cfg->operation),
+			  get_nrf_spi_bit_order(spi_cfg->operation));
+	nrf_spi_frequency_set(spi->p_reg,
+			      get_nrf_spi_frequency(spi_cfg->frequency));
+
+	return 0;
+}
+
+static void transfer_next_chunk(struct device *dev)
+{
+	struct spi_nrfx_data *dev_data = get_dev_data(dev);
+	struct spi_context *ctx = &dev_data->ctx;
+	int error = 0;
+
+	size_t chunk_len = spi_context_longest_current_buf(ctx);
+
+	if (chunk_len > 0) {
+		const nrfx_spi_xfer_desc_t xfer_desc = {
+			.p_tx_buffer = ctx->tx_buf,
+			.tx_length = spi_context_tx_buf_on(ctx) ? chunk_len : 0,
+			.p_rx_buffer = ctx->rx_buf,
+			.rx_length = spi_context_rx_buf_on(ctx) ? chunk_len : 0,
+		};
+		dev_data->chunk_len = chunk_len;
+		nrfx_err_t result = nrfx_spi_xfer(&get_dev_config(dev)->spi,
+						  &xfer_desc, 0);
+
+		if (result == NRFX_SUCCESS) {
+			return;
+		}
+
+		error = -EIO;
+	}
+
+	spi_context_cs_control(ctx, false);
+
+	SYS_LOG_DBG("Transaction finished with status %d", error);
+
+	spi_context_complete(ctx, error);
+	dev_data->busy = false;
+}
+
+static int transceive(struct device *dev,
+		      const struct spi_config *spi_cfg,
+		      const struct spi_buf_set *tx_bufs,
+		      const struct spi_buf_set *rx_bufs)
+{
+	struct spi_nrfx_data *dev_data = get_dev_data(dev);
+	int error;
+
+	error = configure(dev, spi_cfg);
+	if (error == 0) {
+		dev_data->busy = true;
+
+		spi_context_buffers_setup(&dev_data->ctx, tx_bufs, rx_bufs, 1);
+		spi_context_cs_control(&dev_data->ctx, true);
+
+		transfer_next_chunk(dev);
+
+		error = spi_context_wait_for_completion(&dev_data->ctx);
+	}
+
+	spi_context_release(&dev_data->ctx, error);
+
+	return error;
+}
+
+static int spi_nrfx_transceive(struct device *dev,
+			       const struct spi_config *spi_cfg,
+			       const struct spi_buf_set *tx_bufs,
+			       const struct spi_buf_set *rx_bufs)
+{
+	spi_context_lock(&get_dev_data(dev)->ctx, false, NULL);
+	return transceive(dev, spi_cfg, tx_bufs, rx_bufs);
+}
+
+#ifdef CONFIG_SPI_ASYNC
+static int spi_nrfx_transceive_async(struct device *dev,
+				     const struct spi_config *spi_cfg,
+				     const struct spi_buf_set *tx_bufs,
+				     const struct spi_buf_set *rx_bufs,
+				     struct k_poll_signal *async)
+{
+	spi_context_lock(&get_dev_data(dev)->ctx, true, async);
+	return transceive(dev, spi_cfg, tx_bufs, rx_bufs);
+}
+#endif /* CONFIG_SPI_ASYNC */
+
+static int spi_nrfx_release(struct device *dev,
+			    const struct spi_config *spi_cfg)
+{
+	struct spi_nrfx_data *dev_data = get_dev_data(dev);
+
+	if (!spi_context_configured(&dev_data->ctx, spi_cfg)) {
+		return -EINVAL;
+	}
+
+	if (dev_data->busy) {
+		return -EBUSY;
+	}
+
+	spi_context_unlock_unconditionally(&dev_data->ctx);
+
+	return 0;
+}
+
+static const struct spi_driver_api spi_nrfx_driver_api = {
+	.transceive = spi_nrfx_transceive,
+#ifdef CONFIG_SPI_ASYNC
+	.transceive_async = spi_nrfx_transceive_async,
+#endif
+	.release = spi_nrfx_release,
+};
+
+
+static void event_handler(const nrfx_spi_evt_t *p_event, void *p_context)
+{
+	struct device *dev = p_context;
+	struct spi_nrfx_data *dev_data = get_dev_data(dev);
+
+	if (p_event->type == NRFX_SPI_EVENT_DONE) {
+		spi_context_update_tx(&dev_data->ctx, 1, dev_data->chunk_len);
+		spi_context_update_rx(&dev_data->ctx, 1, dev_data->chunk_len);
+
+		transfer_next_chunk(dev);
+	}
+}
+
+static int init_spi(struct device *dev, const nrfx_spi_config_t *config)
+{
+	/* This sets only default values of frequency, mode and bit order.
+	 * The proper ones are set in configure() when a transfer is started.
+	 */
+	nrfx_err_t result = nrfx_spi_init(&get_dev_config(dev)->spi,
+					  config,
+					  event_handler,
+					  dev);
+	if (result != NRFX_SUCCESS) {
+		SYS_LOG_ERR("Failed to initialize device: %s",
+			    dev->config->name);
+		return -EBUSY;
+	}
+
+	spi_context_unlock_unconditionally(&get_dev_data(dev)->ctx);
+
+	return 0;
+}
+
+static void spi_isr(void *irq_handler)
+{
+	((nrfx_irq_handler_t)irq_handler)();
+}
+
+/* In Nordic SoCs the IRQ number assigned to a peripheral is equal to the ID
+ * of the block of 0x1000 bytes in the peripheral address space assigned to
+ * this peripheral. See the chapter "Peripheral interface" (sections "Peripheral
+ * ID" and "Interrupts") in the product specification of a given SoC.
+ */
+#define NRF_SPI_IRQ_NUMBER(idx)  (uint8_t)((uint32_t)NRF_SPI##idx >> 12u)
+
+#define SPI_NRFX_SPI_DEVICE(idx)					\
+	static int spi_##idx##_init(struct device *dev)			\
+	{								\
+		IRQ_CONNECT(NRF_SPI_IRQ_NUMBER(idx),			\
+			    CONFIG_SPI_##idx##_IRQ_PRI,			\
+			    spi_isr, nrfx_spi_##idx##_irq_handler, 0);	\
+		const nrfx_spi_config_t config = {			\
+			.sck_pin   = CONFIG_SPI_##idx##_NRF_SCK_PIN,	\
+			.mosi_pin  = CONFIG_SPI_##idx##_NRF_MOSI_PIN,	\
+			.miso_pin  = CONFIG_SPI_##idx##_NRF_MISO_PIN,	\
+			.ss_pin    = NRFX_SPI_PIN_NOT_USED,		\
+			.orc       = CONFIG_SPI_##idx##_NRF_ORC,	\
+			.frequency = NRF_SPI_FREQ_4M,			\
+			.mode      = NRF_SPI_MODE_0,			\
+			.bit_order = NRF_SPI_BIT_ORDER_MSB_FIRST,	\
+		};							\
+		return init_spi(dev, &config);				\
+	}								\
+	static struct spi_nrfx_data spi_##idx##_data = {		\
+		SPI_CONTEXT_INIT_LOCK(spi_##idx##_data, ctx),		\
+		SPI_CONTEXT_INIT_SYNC(spi_##idx##_data, ctx),		\
+		.busy = false,						\
+	};								\
+	static const struct spi_nrfx_config spi_##idx##_config = {	\
+		.spi = NRFX_SPI_INSTANCE(idx),				\
+	};								\
+	DEVICE_AND_API_INIT(spi_##idx, CONFIG_SPI_##idx##_NAME,		\
+			    spi_##idx##_init,				\
+			    &spi_##idx##_data,				\
+			    &spi_##idx##_config,			\
+			    POST_KERNEL, CONFIG_SPI_INIT_PRIORITY,	\
+			    &spi_nrfx_driver_api)
+
+#ifdef CONFIG_SPI_0_NRF_SPI
+SPI_NRFX_SPI_DEVICE(0);
+#endif
+
+#ifdef CONFIG_SPI_1_NRF_SPI
+SPI_NRFX_SPI_DEVICE(1);
+#endif
+
+#ifdef CONFIG_SPI_2_NRF_SPI
+SPI_NRFX_SPI_DEVICE(2);
+#endif
diff --git a/ext/hal/nordic/CMakeLists.txt b/ext/hal/nordic/CMakeLists.txt
index 4871121787b..087c2381df3 100644
--- a/ext/hal/nordic/CMakeLists.txt
+++ b/ext/hal/nordic/CMakeLists.txt
@@ -19,6 +19,7 @@ if(CONFIG_HAS_NRFX)
   zephyr_sources_ifdef(CONFIG_NRFX_SAADC nrfx/drivers/src/nrfx_saadc.c)
   zephyr_sources_ifdef(CONFIG_NRFX_SPI   nrfx/drivers/src/nrfx_spi.c)
   zephyr_sources_ifdef(CONFIG_NRFX_SPIM  nrfx/drivers/src/nrfx_spim.c)
+  zephyr_sources_ifdef(CONFIG_NRFX_SPIS  nrfx/drivers/src/nrfx_spis.c)
   zephyr_sources_ifdef(CONFIG_NRFX_TWI   nrfx/drivers/src/nrfx_twi.c)
   zephyr_sources_ifdef(CONFIG_NRFX_TWIM  nrfx/drivers/src/nrfx_twim.c)
   zephyr_sources_ifdef(CONFIG_NRFX_UART  nrfx/drivers/src/nrfx_uart.c)
diff --git a/ext/hal/nordic/Kconfig b/ext/hal/nordic/Kconfig
index db3977c2d56..56fab3f7b00 100644
--- a/ext/hal/nordic/Kconfig
+++ b/ext/hal/nordic/Kconfig
@@ -9,3 +9,12 @@ config HAS_NORDIC_DRIVERS
 
 config HAS_NRFX
 	bool
+
+config NRFX_SPI
+	bool
+
+config NRFX_SPIM
+	bool
+
+config NRFX_SPIS
+	bool
diff --git a/ext/hal/nordic/nrfx_config_nrf51.h b/ext/hal/nordic/nrfx_config_nrf51.h
index 1dc4ef92ae1..cb65f6d894c 100644
--- a/ext/hal/nordic/nrfx_config_nrf51.h
+++ b/ext/hal/nordic/nrfx_config_nrf51.h
@@ -877,14 +877,14 @@
 
 // <e> NRFX_SPIS_ENABLED - nrfx_spis - SPIS peripheral driver
 //==========================================================
-#ifndef NRFX_SPIS_ENABLED
-#define NRFX_SPIS_ENABLED 0
+#ifdef CONFIG_NRFX_SPIS
+#define NRFX_SPIS_ENABLED 1
 #endif
 // <q> NRFX_SPIS1_ENABLED  - Enable SPIS1 instance
 
 
-#ifndef NRFX_SPIS1_ENABLED
-#define NRFX_SPIS1_ENABLED 0
+#ifdef CONFIG_SPI_1_NRF_SPIS
+#define NRFX_SPIS1_ENABLED 1
 #endif
 
 // <o> NRFX_SPIS_DEFAULT_CONFIG_IRQ_PRIORITY  - Interrupt priority
@@ -967,21 +967,21 @@
 
 // <e> NRFX_SPI_ENABLED - nrfx_spi - SPI peripheral driver
 //==========================================================
-#ifndef NRFX_SPI_ENABLED
-#define NRFX_SPI_ENABLED 0
+#ifdef CONFIG_NRFX_SPI
+#define NRFX_SPI_ENABLED 1
 #endif
 // <q> NRFX_SPI0_ENABLED  - Enable SPI0 instance
 
 
-#ifndef NRFX_SPI0_ENABLED
-#define NRFX_SPI0_ENABLED 0
+#ifdef CONFIG_SPI_0_NRF_SPI
+#define NRFX_SPI0_ENABLED 1
 #endif
 
 // <q> NRFX_SPI1_ENABLED  - Enable SPI1 instance
 
 
-#ifndef NRFX_SPI1_ENABLED
-#define NRFX_SPI1_ENABLED 0
+#ifdef CONFIG_SPI_1_NRF_SPI
+#define NRFX_SPI1_ENABLED 1
 #endif
 
 // <o> NRFX_SPI_MISO_PULL_CFG  - MISO pin pull configuration.
diff --git a/ext/hal/nordic/nrfx_config_nrf52832.h b/ext/hal/nordic/nrfx_config_nrf52832.h
index fe439c4fb68..2a09fee48df 100644
--- a/ext/hal/nordic/nrfx_config_nrf52832.h
+++ b/ext/hal/nordic/nrfx_config_nrf52832.h
@@ -1605,28 +1605,28 @@
 
 // <e> NRFX_SPIM_ENABLED - nrfx_spim - SPIM peripheral driver
 //==========================================================
-#ifndef NRFX_SPIM_ENABLED
-#define NRFX_SPIM_ENABLED 0
+#ifdef CONFIG_NRFX_SPIM
+#define NRFX_SPIM_ENABLED 1
 #endif
 // <q> NRFX_SPIM0_ENABLED  - Enable SPIM0 instance
 
 
-#ifndef NRFX_SPIM0_ENABLED
-#define NRFX_SPIM0_ENABLED 0
+#ifdef CONFIG_SPI_0_NRF_SPIM
+#define NRFX_SPIM0_ENABLED 1
 #endif
 
 // <q> NRFX_SPIM1_ENABLED  - Enable SPIM1 instance
 
 
-#ifndef NRFX_SPIM1_ENABLED
-#define NRFX_SPIM1_ENABLED 0
+#ifdef CONFIG_SPI_1_NRF_SPIM
+#define NRFX_SPIM1_ENABLED 1
 #endif
 
 // <q> NRFX_SPIM2_ENABLED  - Enable SPIM2 instance
 
 
-#ifndef NRFX_SPIM2_ENABLED
-#define NRFX_SPIM2_ENABLED 0
+#ifdef CONFIG_SPI_2_NRF_SPIM
+#define NRFX_SPIM2_ENABLED 1
 #endif
 
 // <o> NRFX_SPIM_MISO_PULL_CFG  - MISO pin pull configuration.
@@ -1723,28 +1723,28 @@
 
 // <e> NRFX_SPIS_ENABLED - nrfx_spis - SPIS peripheral driver
 //==========================================================
-#ifndef NRFX_SPIS_ENABLED
-#define NRFX_SPIS_ENABLED 0
+#ifdef CONFIG_NRFX_SPIS
+#define NRFX_SPIS_ENABLED 1
 #endif
 // <q> NRFX_SPIS0_ENABLED  - Enable SPIS0 instance
 
 
-#ifndef NRFX_SPIS0_ENABLED
-#define NRFX_SPIS0_ENABLED 0
+#ifdef CONFIG_SPI_0_NRF_SPIS
+#define NRFX_SPIS0_ENABLED 1
 #endif
 
 // <q> NRFX_SPIS1_ENABLED  - Enable SPIS1 instance
 
 
-#ifndef NRFX_SPIS1_ENABLED
-#define NRFX_SPIS1_ENABLED 0
+#ifdef CONFIG_SPI_1_NRF_SPIS
+#define NRFX_SPIS1_ENABLED 1
 #endif
 
 // <q> NRFX_SPIS2_ENABLED  - Enable SPIS2 instance
 
 
-#ifndef NRFX_SPIS2_ENABLED
-#define NRFX_SPIS2_ENABLED 0
+#ifdef CONFIG_SPI_2_NRF_SPIS
+#define NRFX_SPIS2_ENABLED 1
 #endif
 
 // <o> NRFX_SPIS_DEFAULT_CONFIG_IRQ_PRIORITY  - Interrupt priority
@@ -1845,28 +1845,28 @@
 
 // <e> NRFX_SPI_ENABLED - nrfx_spi - SPI peripheral driver
 //==========================================================
-#ifndef NRFX_SPI_ENABLED
-#define NRFX_SPI_ENABLED 0
+#ifdef CONFIG_NRFX_SPI
+#define NRFX_SPI_ENABLED 1
 #endif
 // <q> NRFX_SPI0_ENABLED  - Enable SPI0 instance
 
 
-#ifndef NRFX_SPI0_ENABLED
-#define NRFX_SPI0_ENABLED 0
+#ifdef CONFIG_SPI_0_NRF_SPI
+#define NRFX_SPI0_ENABLED 1
 #endif
 
 // <q> NRFX_SPI1_ENABLED  - Enable SPI1 instance
 
 
-#ifndef NRFX_SPI1_ENABLED
-#define NRFX_SPI1_ENABLED 0
+#ifdef CONFIG_SPI_1_NRF_SPI
+#define NRFX_SPI1_ENABLED 1
 #endif
 
 // <q> NRFX_SPI2_ENABLED  - Enable SPI2 instance
 
 
-#ifndef NRFX_SPI2_ENABLED
-#define NRFX_SPI2_ENABLED 0
+#ifdef CONFIG_SPI_2_NRF_SPI
+#define NRFX_SPI2_ENABLED 1
 #endif
 
 // <o> NRFX_SPI_MISO_PULL_CFG  - MISO pin pull configuration.
diff --git a/ext/hal/nordic/nrfx_config_nrf52840.h b/ext/hal/nordic/nrfx_config_nrf52840.h
index cdece46f71c..9fcec04d995 100644
--- a/ext/hal/nordic/nrfx_config_nrf52840.h
+++ b/ext/hal/nordic/nrfx_config_nrf52840.h
@@ -1712,35 +1712,35 @@
 
 // <e> NRFX_SPIM_ENABLED - nrfx_spim - SPIM peripheral driver
 //==========================================================
-#ifndef NRFX_SPIM_ENABLED
-#define NRFX_SPIM_ENABLED 0
+#ifdef CONFIG_NRFX_SPIM
+#define NRFX_SPIM_ENABLED 1
 #endif
 // <q> NRFX_SPIM0_ENABLED  - Enable SPIM0 instance
 
 
-#ifndef NRFX_SPIM0_ENABLED
-#define NRFX_SPIM0_ENABLED 0
+#ifdef CONFIG_SPI_0_NRF_SPIM
+#define NRFX_SPIM0_ENABLED 1
 #endif
 
 // <q> NRFX_SPIM1_ENABLED  - Enable SPIM1 instance
 
 
-#ifndef NRFX_SPIM1_ENABLED
-#define NRFX_SPIM1_ENABLED 0
+#ifdef CONFIG_SPI_1_NRF_SPIM
+#define NRFX_SPIM1_ENABLED 1
 #endif
 
 // <q> NRFX_SPIM2_ENABLED  - Enable SPIM2 instance
 
 
-#ifndef NRFX_SPIM2_ENABLED
-#define NRFX_SPIM2_ENABLED 0
+#ifdef CONFIG_SPI_2_NRF_SPIM
+#define NRFX_SPIM2_ENABLED 1
 #endif
 
 // <q> NRFX_SPIM3_ENABLED  - Enable SPIM3 instance
 
 
-#ifndef NRFX_SPIM3_ENABLED
-#define NRFX_SPIM3_ENABLED 0
+#ifdef CONFIG_SPI_3_NRF_SPIM
+#define NRFX_SPIM3_ENABLED 1
 #endif
 
 // <q> NRFX_SPIM_EXTENDED_ENABLED  - Enable extended SPIM features
@@ -1840,28 +1840,28 @@
 
 // <e> NRFX_SPIS_ENABLED - nrfx_spis - SPIS peripheral driver
 //==========================================================
-#ifndef NRFX_SPIS_ENABLED
-#define NRFX_SPIS_ENABLED 0
+#ifdef CONFIG_NRFX_SPIS
+#define NRFX_SPIS_ENABLED 1
 #endif
 // <q> NRFX_SPIS0_ENABLED  - Enable SPIS0 instance
 
 
-#ifndef NRFX_SPIS0_ENABLED
-#define NRFX_SPIS0_ENABLED 0
+#ifdef CONFIG_SPI_0_NRF_SPIS
+#define NRFX_SPIS0_ENABLED 1
 #endif
 
 // <q> NRFX_SPIS1_ENABLED  - Enable SPIS1 instance
 
 
-#ifndef NRFX_SPIS1_ENABLED
-#define NRFX_SPIS1_ENABLED 0
+#ifdef CONFIG_SPI_1_NRF_SPIS
+#define NRFX_SPIS1_ENABLED 1
 #endif
 
 // <q> NRFX_SPIS2_ENABLED  - Enable SPIS2 instance
 
 
-#ifndef NRFX_SPIS2_ENABLED
-#define NRFX_SPIS2_ENABLED 0
+#ifdef CONFIG_SPI_2_NRF_SPIS
+#define NRFX_SPIS2_ENABLED 1
 #endif
 
 // <o> NRFX_SPIS_DEFAULT_CONFIG_IRQ_PRIORITY  - Interrupt priority
@@ -1948,28 +1948,28 @@
 
 // <e> NRFX_SPI_ENABLED - nrfx_spi - SPI peripheral driver
 //==========================================================
-#ifndef NRFX_SPI_ENABLED
-#define NRFX_SPI_ENABLED 0
+#ifdef CONFIG_NRFX_SPI
+#define NRFX_SPI_ENABLED 1
 #endif
 // <q> NRFX_SPI0_ENABLED  - Enable SPI0 instance
 
 
-#ifndef NRFX_SPI0_ENABLED
-#define NRFX_SPI0_ENABLED 0
+#ifdef CONFIG_SPI_0_NRF_SPI
+#define NRFX_SPI0_ENABLED 1
 #endif
 
 // <q> NRFX_SPI1_ENABLED  - Enable SPI1 instance
 
 
-#ifndef NRFX_SPI1_ENABLED
-#define NRFX_SPI1_ENABLED 0
+#ifdef CONFIG_SPI_1_NRF_SPI
+#define NRFX_SPI1_ENABLED 1
 #endif
 
 // <q> NRFX_SPI2_ENABLED  - Enable SPI2 instance
 
 
-#ifndef NRFX_SPI2_ENABLED
-#define NRFX_SPI2_ENABLED 0
+#ifdef CONFIG_SPI_2_NRF_SPI
+#define NRFX_SPI2_ENABLED 1
 #endif
 
 // <o> NRFX_SPI_MISO_PULL_CFG  - MISO pin pull configuration.