2024-03-28 14:45:58 +01:00
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/*
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* Copyright (c) 2024 Nordic Semiconductor ASA
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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2024-11-04 17:48:40 +01:00
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#include "nrf54l_05_10_15.dtsi"
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2024-03-28 14:45:58 +01:00
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2024-11-04 17:48:40 +01:00
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&cpuapp_sram {
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reg = <0x20000000 DT_SIZE_K(188)>;
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ranges = <0x0 0x20000000 DT_SIZE_K(188)>;
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};
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2024-03-28 14:45:58 +01:00
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2024-11-04 17:48:40 +01:00
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/* 188 + 68 = 256KB */
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2024-03-28 14:45:58 +01:00
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/ {
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soc {
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cpuflpr_sram: memory@2002f000 {
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compatible = "mmio-sram";
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reg = <0x2002f000 DT_SIZE_K(68)>;
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#address-cells = <1>;
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#size-cells = <1>;
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2024-11-04 17:48:40 +01:00
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ranges = <0x0 0x2002f000 DT_SIZE_K(68)>;
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2024-03-28 14:45:58 +01:00
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};
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2024-11-04 17:48:40 +01:00
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};
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};
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2024-03-28 14:45:58 +01:00
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2024-11-04 17:48:40 +01:00
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&cpuapp_rram {
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reg = <0x0 DT_SIZE_K(1428)>;
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};
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2024-03-28 14:45:58 +01:00
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2024-11-04 17:48:40 +01:00
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/* 1428 + 96 = 1524KB */
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&rram_controller {
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cpuflpr_rram: rram@165000 {
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compatible = "soc-nv-flash";
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reg = <0x165000 DT_SIZE_K(96)>;
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erase-block-size = <4096>;
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write-block-size = <16>;
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2024-03-28 14:45:58 +01:00
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};
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};
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