2020-03-13 16:24:01 +05:30
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/*
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* Copyright (c) 2017-2020 Nordic Semiconductor ASA
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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2020-08-19 10:09:58 +05:30
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#include <zephyr.h>
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#include <soc.h>
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2020-03-13 16:24:01 +05:30
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#include <bluetooth/hci.h>
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2020-08-19 10:09:58 +05:30
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#include <sys/byteorder.h>
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2020-03-13 16:24:01 +05:30
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2020-08-19 10:09:58 +05:30
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#include "hal/cpu.h"
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2020-03-13 16:24:01 +05:30
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#include "hal/ticker.h"
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#include "util/util.h"
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#include "util/mem.h"
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#include "util/memq.h"
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#include "util/mayfly.h"
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#include "ticker/ticker.h"
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#include "pdu.h"
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2021-02-24 16:42:02 +05:30
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2020-03-13 16:24:01 +05:30
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#include "lll.h"
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2021-02-24 16:42:02 +05:30
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#include "lll/lll_vendor.h"
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#include "lll/lll_adv_types.h"
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2020-03-13 16:24:01 +05:30
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#include "lll_adv.h"
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2021-02-24 16:42:02 +05:30
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#include "lll/lll_adv_pdu.h"
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2020-02-06 16:43:46 +05:30
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#include "lll_adv_sync.h"
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2021-02-24 16:42:02 +05:30
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#include "lll/lll_df_types.h"
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2021-03-08 12:25:46 +05:30
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#include "lll_chan.h"
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2020-03-13 16:24:01 +05:30
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#include "ull_adv_types.h"
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#include "ull_internal.h"
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2020-02-07 18:12:16 +05:30
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#include "ull_chan_internal.h"
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2020-03-13 16:24:01 +05:30
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#include "ull_adv_internal.h"
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2021-02-24 16:42:02 +05:30
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#include "ll.h"
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2020-03-13 16:24:01 +05:30
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#define BT_DBG_ENABLED IS_ENABLED(CONFIG_BT_DEBUG_HCI_DRIVER)
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#define LOG_MODULE_NAME bt_ctlr_ull_adv_sync
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#include "common/log.h"
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#include "hal/debug.h"
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static int init_reset(void);
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static inline struct ll_adv_sync_set *sync_acquire(void);
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static inline void sync_release(struct ll_adv_sync_set *sync);
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static inline uint16_t sync_handle_get(struct ll_adv_sync_set *sync);
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2020-10-20 17:12:28 +05:30
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static inline uint8_t sync_remove(struct ll_adv_sync_set *sync,
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struct ll_adv_set *adv, uint8_t enable);
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2021-01-22 05:38:47 -08:00
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2021-02-24 13:57:41 +05:30
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#if defined(CONFIG_BT_CTLR_DF_ADV_CTE_TX)
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2021-01-22 05:38:47 -08:00
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static inline void adv_sync_extra_data_set_clear(void *extra_data_prev,
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void *extra_data_new,
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uint16_t hdr_add_fields,
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uint16_t hdr_rem_fields,
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void *data);
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#endif /* CONFIG_BT_CTLR_DF_ADV_CTE_TX */
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static uint8_t adv_sync_hdr_set_clear(struct lll_adv_sync *lll_sync,
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struct pdu_adv *ter_pdu_prev,
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struct pdu_adv *ter_pdu,
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uint16_t hdr_add_fields,
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uint16_t hdr_rem_fields,
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void *data);
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2020-02-12 08:55:57 +05:30
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static void mfy_sync_offset_get(void *param);
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2020-07-17 15:27:42 +05:30
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static inline struct pdu_adv_sync_info *sync_info_get(struct pdu_adv *pdu);
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static inline void sync_info_offset_fill(struct pdu_adv_sync_info *si,
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uint32_t ticks_offset,
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uint32_t start_us);
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2020-03-13 16:24:01 +05:30
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static void ticker_cb(uint32_t ticks_at_expire, uint32_t remainder,
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2021-03-03 15:41:55 +01:00
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uint16_t lazy, uint8_t force, void *param);
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2020-02-12 08:55:57 +05:30
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static void ticker_op_cb(uint32_t status, void *param);
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2020-03-13 16:24:01 +05:30
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static struct ll_adv_sync_set ll_adv_sync_pool[CONFIG_BT_CTLR_ADV_SYNC_SET];
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static void *adv_sync_free;
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uint8_t ll_adv_sync_param_set(uint8_t handle, uint16_t interval, uint16_t flags)
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{
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2020-02-12 08:55:57 +05:30
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struct lll_adv_sync *lll_sync;
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2020-03-13 16:24:01 +05:30
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struct ll_adv_sync_set *sync;
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struct ll_adv_set *adv;
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2021-01-22 05:38:47 -08:00
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uint8_t err, ter_idx;
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2020-03-13 16:24:01 +05:30
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2020-03-13 16:24:01 +05:30
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adv = ull_adv_is_created_get(handle);
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2020-03-13 16:24:01 +05:30
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if (!adv) {
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2020-07-22 01:49:22 +02:00
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return BT_HCI_ERR_UNKNOWN_ADV_IDENTIFIER;
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2020-03-13 16:24:01 +05:30
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}
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2020-02-12 08:55:57 +05:30
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lll_sync = adv->lll.sync;
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if (!lll_sync) {
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2021-02-16 15:41:34 +05:30
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struct pdu_adv_com_ext_adv *ter_com_hdr;
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struct pdu_adv_ext_hdr *ter_hdr;
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struct pdu_adv *ter_pdu;
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2020-02-12 08:55:57 +05:30
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struct lll_adv *lll;
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2021-02-16 15:41:34 +05:30
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uint8_t *ter_dptr;
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2021-02-16 15:43:01 +05:30
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uint8_t ter_len;
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2020-05-11 15:36:12 +05:30
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int err;
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2020-02-10 18:48:04 +05:30
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2020-03-13 16:24:01 +05:30
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sync = sync_acquire();
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if (!sync) {
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return BT_HCI_ERR_MEM_CAPACITY_EXCEEDED;
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}
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2020-02-12 08:55:57 +05:30
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lll = &adv->lll;
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lll_sync = &sync->lll;
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lll->sync = lll_sync;
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lll_sync->adv = lll;
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2020-03-13 16:24:01 +05:30
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2020-10-22 18:40:38 +05:30
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lll_adv_data_reset(&lll_sync->data);
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err = lll_adv_data_init(&lll_sync->data);
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if (err) {
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return BT_HCI_ERR_MEM_CAPACITY_EXCEEDED;
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}
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2020-04-27 17:00:09 +05:30
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/* NOTE: ull_hdr_init(&sync->ull); is done on start */
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2020-02-12 08:55:57 +05:30
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lll_hdr_init(lll_sync, sync);
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2020-02-07 18:12:16 +05:30
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2020-05-11 15:36:12 +05:30
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err = util_aa_le32(lll_sync->access_addr);
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LL_ASSERT(!err);
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2021-03-08 12:25:46 +05:30
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lll_sync->data_chan_id = lll_chan_id(lll_sync->access_addr);
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lll_sync->data_chan_count =
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ull_chan_map_get(lll_sync->data_chan_map);
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2020-05-21 14:51:16 +02:00
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lll_csrand_get(lll_sync->crc_init, sizeof(lll_sync->crc_init));
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2020-02-07 18:12:16 +05:30
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2020-02-12 08:55:57 +05:30
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lll_sync->latency_prepare = 0;
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lll_sync->latency_event = 0;
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lll_sync->event_counter = 0;
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2020-02-07 18:12:16 +05:30
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2020-05-21 10:29:49 +05:30
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sync->is_enabled = 0U;
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sync->is_started = 0U;
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2020-03-13 16:24:01 +05:30
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2021-01-22 05:38:47 -08:00
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ter_pdu = lll_adv_sync_data_peek(lll_sync, NULL);
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ter_pdu->type = PDU_ADV_TYPE_AUX_SYNC_IND;
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ter_pdu->rfu = 0U;
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ter_pdu->chan_sel = 0U;
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2020-03-13 16:24:01 +05:30
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2021-01-22 05:38:47 -08:00
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ter_pdu->tx_addr = 0U;
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ter_pdu->rx_addr = 0U;
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2020-02-10 18:48:04 +05:30
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2021-01-22 05:38:47 -08:00
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ter_com_hdr = (void *)&ter_pdu->adv_ext_ind;
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ter_hdr = (void *)ter_com_hdr->ext_hdr_adv_data;
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ter_dptr = ter_hdr->data;
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*(uint8_t *)ter_hdr = 0U;
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2020-03-13 16:24:01 +05:30
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2021-01-22 05:38:47 -08:00
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/* Non-connectable and Non-scannable adv mode */
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ter_com_hdr->adv_mode = 0U;
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2021-02-16 15:43:01 +05:30
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/* Calc tertiary PDU len */
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ter_len = ull_adv_aux_hdr_len_calc(ter_com_hdr, &ter_dptr);
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ull_adv_aux_hdr_len_fill(ter_com_hdr, ter_len);
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ter_pdu->len = ter_len;
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2021-01-22 05:38:47 -08:00
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} else {
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2021-04-05 12:56:51 +05:30
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sync = HDR_LLL2ULL(lll_sync);
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2020-03-13 16:24:01 +05:30
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}
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2021-01-22 05:38:47 -08:00
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sync->interval = interval;
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2020-02-10 18:48:04 +05:30
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2021-01-22 05:38:47 -08:00
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err = ull_adv_sync_pdu_set_clear(adv, 0, 0, NULL, &ter_idx);
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if (err) {
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return err;
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}
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2020-08-17 12:49:40 +05:30
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2021-01-22 05:38:47 -08:00
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lll_adv_sync_data_enqueue(lll_sync, ter_idx);
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2020-02-10 18:48:04 +05:30
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2020-03-13 16:24:01 +05:30
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return 0;
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}
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2020-05-20 10:18:39 +05:30
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uint8_t ll_adv_sync_ad_data_set(uint8_t handle, uint8_t op, uint8_t len,
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uint8_t const *const data)
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2020-03-13 16:24:01 +05:30
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{
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2021-01-22 05:38:47 -08:00
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struct adv_pdu_field_data pdu_data;
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2020-11-04 13:29:27 +05:30
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struct lll_adv_sync *lll_sync;
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struct ll_adv_set *adv;
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2021-01-22 05:38:47 -08:00
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uint8_t value[5];
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2020-11-04 13:29:27 +05:30
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uint8_t ter_idx;
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2021-01-22 05:38:47 -08:00
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uint8_t err;
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/* TODO: handle other op values */
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if (op != BT_HCI_LE_EXT_ADV_OP_COMPLETE_DATA &&
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op != BT_HCI_LE_EXT_ADV_OP_UNCHANGED_DATA) {
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/* FIXME: error code */
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return BT_HCI_ERR_CMD_DISALLOWED;
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}
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2020-11-04 13:29:27 +05:30
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adv = ull_adv_is_created_get(handle);
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if (!adv) {
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return BT_HCI_ERR_UNKNOWN_ADV_IDENTIFIER;
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}
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lll_sync = adv->lll.sync;
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if (!lll_sync) {
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return BT_HCI_ERR_UNKNOWN_ADV_IDENTIFIER;
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}
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2021-01-22 05:38:47 -08:00
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pdu_data.field_data = value;
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*pdu_data.field_data = len;
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sys_put_le32((uint32_t)data, pdu_data.field_data + 1);
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2020-11-04 13:29:27 +05:30
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2021-01-22 05:38:47 -08:00
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err = ull_adv_sync_pdu_set_clear(adv, ULL_ADV_PDU_HDR_FIELD_AD_DATA,
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0, &pdu_data, &ter_idx);
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if (err) {
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return err;
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2020-11-04 13:29:27 +05:30
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}
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lll_adv_sync_data_enqueue(lll_sync, ter_idx);
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return 0;
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2020-03-13 16:24:01 +05:30
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}
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uint8_t ll_adv_sync_enable(uint8_t handle, uint8_t enable)
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{
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2020-02-12 08:55:57 +05:30
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struct lll_adv_sync *lll_sync;
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2020-03-13 16:24:01 +05:30
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struct ll_adv_sync_set *sync;
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2020-10-09 16:44:23 +05:30
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uint8_t sync_got_enabled;
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2020-03-13 16:24:01 +05:30
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struct ll_adv_set *adv;
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2020-10-09 16:44:23 +05:30
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uint8_t pri_idx;
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uint8_t err;
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2020-03-13 16:24:01 +05:30
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2020-03-13 16:24:01 +05:30
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adv = ull_adv_is_created_get(handle);
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2020-03-13 16:24:01 +05:30
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if (!adv) {
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2020-07-22 01:49:22 +02:00
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return BT_HCI_ERR_UNKNOWN_ADV_IDENTIFIER;
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2020-03-13 16:24:01 +05:30
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}
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2020-02-12 08:55:57 +05:30
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lll_sync = adv->lll.sync;
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if (!lll_sync) {
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2020-03-13 16:24:01 +05:30
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return BT_HCI_ERR_UNKNOWN_ADV_IDENTIFIER;
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}
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2021-04-05 12:56:51 +05:30
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sync = HDR_LLL2ULL(lll_sync);
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2020-03-13 16:24:01 +05:30
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if (!enable) {
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2020-05-21 10:29:49 +05:30
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if (!sync->is_enabled) {
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return BT_HCI_ERR_CMD_DISALLOWED;
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}
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if (!sync->is_started) {
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sync->is_enabled = 0U;
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return 0;
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}
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2020-10-20 17:12:28 +05:30
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err = sync_remove(sync, adv, 0U);
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return err;
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2020-03-13 16:24:01 +05:30
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}
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/* TODO: Check for periodic data being complete */
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/* TODO: Check packet too long */
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2020-10-09 16:44:23 +05:30
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sync_got_enabled = 0U;
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2020-03-13 16:24:01 +05:30
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if (sync->is_enabled) {
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/* TODO: Enabling an already enabled advertising changes its
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* random address.
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*/
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} else {
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2020-10-09 16:44:23 +05:30
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sync_got_enabled = 1U;
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2020-03-13 16:24:01 +05:30
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}
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2020-05-21 10:29:49 +05:30
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if (adv->is_enabled && !sync->is_started) {
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2020-10-09 16:44:23 +05:30
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uint32_t ticks_slot_overhead_aux;
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struct lll_adv_aux *lll_aux;
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struct ll_adv_aux_set *aux;
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uint32_t ticks_anchor_sync;
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uint32_t ticks_anchor_aux;
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uint32_t ret;
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2020-07-06 15:40:58 +05:30
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2020-10-09 16:44:23 +05:30
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lll_aux = adv->lll.aux;
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2020-07-06 15:40:58 +05:30
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/* Add sync_info into auxiliary PDU */
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err = ull_adv_aux_hdr_set_clear(adv,
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|
ULL_ADV_PDU_HDR_FIELD_SYNC_INFO,
|
2020-10-01 19:26:34 +05:30
|
|
|
0, NULL, NULL, &pri_idx);
|
2020-07-06 15:40:58 +05:30
|
|
|
if (err) {
|
|
|
|
return err;
|
|
|
|
}
|
|
|
|
|
2020-10-09 16:44:23 +05:30
|
|
|
if (lll_aux) {
|
|
|
|
/* FIXME: Find absolute ticks until after auxiliary PDU
|
|
|
|
* on air to place the periodic advertising PDU.
|
|
|
|
*/
|
|
|
|
ticks_anchor_aux = 0U; /* unused in this path */
|
|
|
|
ticks_slot_overhead_aux = 0U; /* unused in this path */
|
|
|
|
ticks_anchor_sync = ticker_ticks_now_get();
|
|
|
|
aux = NULL;
|
|
|
|
} else {
|
|
|
|
lll_aux = adv->lll.aux;
|
2021-04-05 12:56:51 +05:30
|
|
|
aux = HDR_LLL2ULL(lll_aux);
|
2020-10-09 16:44:23 +05:30
|
|
|
ticks_anchor_aux = ticker_ticks_now_get();
|
|
|
|
ticks_slot_overhead_aux = ull_adv_aux_evt_init(aux);
|
|
|
|
ticks_anchor_sync =
|
|
|
|
ticks_anchor_aux + ticks_slot_overhead_aux +
|
2021-04-05 12:56:51 +05:30
|
|
|
aux->ull.ticks_slot +
|
2020-10-09 16:44:23 +05:30
|
|
|
HAL_TICKER_US_TO_TICKS(EVENT_MAFS_US);
|
|
|
|
}
|
2020-07-06 15:40:58 +05:30
|
|
|
|
2021-01-22 05:38:47 -08:00
|
|
|
ret = ull_adv_sync_start(adv, sync, ticks_anchor_sync);
|
2020-10-09 16:44:23 +05:30
|
|
|
if (ret) {
|
2020-10-20 17:12:28 +05:30
|
|
|
sync_remove(sync, adv, 1U);
|
|
|
|
|
|
|
|
return BT_HCI_ERR_INSUFFICIENT_RESOURCES;
|
2020-07-06 15:40:58 +05:30
|
|
|
}
|
|
|
|
|
|
|
|
sync->is_started = 1U;
|
2020-10-01 19:26:34 +05:30
|
|
|
|
|
|
|
lll_adv_data_enqueue(&adv->lll, pri_idx);
|
2020-10-09 16:44:23 +05:30
|
|
|
|
|
|
|
if (aux) {
|
|
|
|
/* Keep aux interval equal or higher than primary PDU
|
|
|
|
* interval.
|
|
|
|
*/
|
|
|
|
aux->interval = adv->interval +
|
|
|
|
(HAL_TICKER_TICKS_TO_US(
|
2021-01-16 13:38:07 +01:00
|
|
|
ULL_ADV_RANDOM_DELAY) /
|
|
|
|
ADV_INT_UNIT_US);
|
2020-10-09 16:44:23 +05:30
|
|
|
|
|
|
|
ret = ull_adv_aux_start(aux, ticks_anchor_aux,
|
|
|
|
ticks_slot_overhead_aux);
|
|
|
|
if (ret) {
|
2020-10-20 17:12:28 +05:30
|
|
|
sync_remove(sync, adv, 1U);
|
|
|
|
|
|
|
|
return BT_HCI_ERR_INSUFFICIENT_RESOURCES;
|
2020-10-09 16:44:23 +05:30
|
|
|
}
|
|
|
|
|
|
|
|
aux->is_started = 1U;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
if (sync_got_enabled) {
|
|
|
|
sync->is_enabled = sync_got_enabled;
|
2020-03-13 16:24:01 +05:30
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
int ull_adv_sync_init(void)
|
|
|
|
{
|
|
|
|
int err;
|
|
|
|
|
|
|
|
err = init_reset();
|
|
|
|
if (err) {
|
|
|
|
return err;
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
int ull_adv_sync_reset(void)
|
|
|
|
{
|
|
|
|
int err;
|
|
|
|
|
|
|
|
err = init_reset();
|
|
|
|
if (err) {
|
|
|
|
return err;
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2020-02-06 16:43:46 +05:30
|
|
|
uint16_t ull_adv_sync_lll_handle_get(struct lll_adv_sync *lll)
|
|
|
|
{
|
|
|
|
return sync_handle_get((void *)lll->hdr.parent);
|
|
|
|
}
|
|
|
|
|
2021-01-22 05:38:47 -08:00
|
|
|
uint32_t ull_adv_sync_start(struct ll_adv_set *adv,
|
|
|
|
struct ll_adv_sync_set *sync,
|
2020-10-09 16:26:22 +05:30
|
|
|
uint32_t ticks_anchor)
|
2020-03-13 16:24:01 +05:30
|
|
|
{
|
2021-02-24 13:57:41 +05:30
|
|
|
#if defined(CONFIG_BT_CTLR_DF_ADV_CTE_TX)
|
2021-01-22 05:38:47 -08:00
|
|
|
struct lll_df_adv_cfg *df_cfg;
|
|
|
|
#endif /* CONFIG_BT_CTLR_DF_ADV_CTE_TX */
|
2020-02-07 18:12:16 +05:30
|
|
|
uint32_t ticks_slot_overhead;
|
2020-10-09 16:26:22 +05:30
|
|
|
uint32_t volatile ret_cb;
|
2020-02-12 08:55:57 +05:30
|
|
|
uint32_t interval_us;
|
2020-03-13 16:24:01 +05:30
|
|
|
uint8_t sync_handle;
|
2020-10-09 16:26:22 +05:30
|
|
|
uint32_t slot_us;
|
2020-03-13 16:24:01 +05:30
|
|
|
uint32_t ret;
|
|
|
|
|
2020-10-09 16:13:33 +05:30
|
|
|
ull_hdr_init(&sync->ull);
|
|
|
|
|
2020-03-13 16:24:01 +05:30
|
|
|
/* TODO: Calc AUX_SYNC_IND slot_us */
|
2020-10-09 16:26:22 +05:30
|
|
|
slot_us = EVENT_OVERHEAD_START_US + EVENT_OVERHEAD_END_US;
|
2020-02-12 08:55:57 +05:30
|
|
|
slot_us += 1000;
|
2020-03-13 16:24:01 +05:30
|
|
|
|
2021-02-24 13:57:41 +05:30
|
|
|
#if defined(CONFIG_BT_CTLR_DF_ADV_CTE_TX)
|
2021-01-22 05:38:47 -08:00
|
|
|
df_cfg = adv->df_cfg;
|
|
|
|
if (df_cfg && df_cfg->is_enabled) {
|
|
|
|
slot_us += CTE_LEN_US(df_cfg->cte_length);
|
|
|
|
}
|
|
|
|
#endif /* CONFIG_BT_CTLR_DF_ADV_CTE_TX */
|
|
|
|
|
2020-03-13 16:24:01 +05:30
|
|
|
/* TODO: active_to_start feature port */
|
2021-04-05 12:56:51 +05:30
|
|
|
sync->ull.ticks_active_to_start = 0;
|
|
|
|
sync->ull.ticks_prepare_to_start =
|
2020-02-07 18:12:16 +05:30
|
|
|
HAL_TICKER_US_TO_TICKS(EVENT_OVERHEAD_XTAL_US);
|
2021-04-05 12:56:51 +05:30
|
|
|
sync->ull.ticks_preempt_to_start =
|
2020-02-07 18:12:16 +05:30
|
|
|
HAL_TICKER_US_TO_TICKS(EVENT_OVERHEAD_PREEMPT_MIN_US);
|
2021-04-05 12:56:51 +05:30
|
|
|
sync->ull.ticks_slot = HAL_TICKER_US_TO_TICKS(slot_us);
|
2020-03-13 16:24:01 +05:30
|
|
|
|
|
|
|
if (IS_ENABLED(CONFIG_BT_CTLR_LOW_LAT)) {
|
2021-04-05 12:56:51 +05:30
|
|
|
ticks_slot_overhead = MAX(sync->ull.ticks_active_to_start,
|
|
|
|
sync->ull.ticks_prepare_to_start);
|
2020-03-13 16:24:01 +05:30
|
|
|
} else {
|
|
|
|
ticks_slot_overhead = 0;
|
|
|
|
}
|
|
|
|
|
2021-01-16 13:38:07 +01:00
|
|
|
interval_us = (uint32_t)sync->interval * CONN_INT_UNIT_US;
|
2020-02-12 08:55:57 +05:30
|
|
|
|
2020-03-13 16:24:01 +05:30
|
|
|
sync_handle = sync_handle_get(sync);
|
|
|
|
|
2020-10-09 16:26:22 +05:30
|
|
|
ret_cb = TICKER_STATUS_BUSY;
|
2020-03-13 16:24:01 +05:30
|
|
|
ret = ticker_start(TICKER_INSTANCE_ID_CTLR, TICKER_USER_ID_THREAD,
|
|
|
|
(TICKER_ID_ADV_SYNC_BASE + sync_handle),
|
|
|
|
ticks_anchor, 0,
|
2020-02-12 08:55:57 +05:30
|
|
|
HAL_TICKER_US_TO_TICKS(interval_us),
|
|
|
|
HAL_TICKER_REMAINDER(interval_us), TICKER_NULL_LAZY,
|
2021-04-05 12:56:51 +05:30
|
|
|
(sync->ull.ticks_slot + ticks_slot_overhead),
|
2020-03-13 16:24:01 +05:30
|
|
|
ticker_cb, sync,
|
2020-10-09 16:26:22 +05:30
|
|
|
ull_ticker_status_give, (void *)&ret_cb);
|
|
|
|
ret = ull_ticker_status_take(ret, &ret_cb);
|
2020-03-13 16:24:01 +05:30
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2021-02-03 03:02:28 -08:00
|
|
|
void ull_adv_sync_release(struct ll_adv_sync_set *sync)
|
|
|
|
{
|
|
|
|
lll_adv_sync_data_release(&sync->lll);
|
|
|
|
sync_release(sync);
|
|
|
|
}
|
|
|
|
|
2020-02-12 08:55:57 +05:30
|
|
|
void ull_adv_sync_offset_get(struct ll_adv_set *adv)
|
|
|
|
{
|
|
|
|
static memq_link_t link;
|
|
|
|
static struct mayfly mfy = {0, 0, &link, NULL, mfy_sync_offset_get};
|
|
|
|
uint32_t ret;
|
|
|
|
|
|
|
|
mfy.param = adv;
|
|
|
|
ret = mayfly_enqueue(TICKER_USER_ID_ULL_HIGH, TICKER_USER_ID_ULL_LOW, 1,
|
|
|
|
&mfy);
|
|
|
|
LL_ASSERT(!ret);
|
|
|
|
}
|
|
|
|
|
2021-02-24 13:57:41 +05:30
|
|
|
#if defined(CONFIG_BT_CTLR_DF_ADV_CTE_TX)
|
2021-01-22 05:38:47 -08:00
|
|
|
void ull_adv_sync_update(struct ll_adv_sync_set *sync, uint32_t slot_plus_us,
|
|
|
|
uint32_t slot_minus_us)
|
|
|
|
{
|
|
|
|
uint32_t ret;
|
|
|
|
|
|
|
|
ret = ticker_update(TICKER_INSTANCE_ID_CTLR,
|
|
|
|
TICKER_USER_ID_THREAD,
|
|
|
|
(TICKER_ID_ADV_BASE + sync_handle_get(sync)),
|
|
|
|
0, 0,
|
|
|
|
slot_plus_us,
|
|
|
|
slot_minus_us,
|
|
|
|
0, 0,
|
|
|
|
NULL, NULL);
|
|
|
|
LL_ASSERT((ret == TICKER_STATUS_SUCCESS) ||
|
|
|
|
(ret == TICKER_STATUS_BUSY));
|
|
|
|
}
|
|
|
|
#endif /* CONFIG_BT_CTLR_DF_ADV_CTE_TX */
|
|
|
|
|
2021-02-16 15:39:13 +05:30
|
|
|
/* @brief Set or clear fields in extended advertising header and store
|
|
|
|
* extra_data if requested.
|
|
|
|
*
|
|
|
|
* @param[in] adv Advertising set.
|
|
|
|
* @param[in] hdr_add_fields Flag with information which fields add.
|
|
|
|
* @param[in] hdr_rem_fields Flag with information which fields remove.
|
|
|
|
* @param[in] data Pointer to data to be added to header and
|
|
|
|
* extra_data. Content depends on the value of
|
|
|
|
* @p hdr_add_fields.
|
|
|
|
* @param[out] ter_idx Index of new PDU.
|
|
|
|
*
|
|
|
|
* @Note
|
|
|
|
* @p data content depends on the flag provided by @p hdr_add_fields:
|
|
|
|
* - ULL_ADV_PDU_HDR_FIELD_CTE_INFO:
|
|
|
|
* # @p data->field_data points to single byte with CTEInfo field
|
|
|
|
* # @p data->extra_data points to memory where is struct lll_df_adv_cfg
|
|
|
|
* for LLL.
|
|
|
|
* - ULL_ADV_PDU_HDR_FIELD_AD_DATA:
|
|
|
|
* # @p data->field_data points to memory where first byte
|
|
|
|
* is size of advertising data, following byte is a pointer to actual
|
|
|
|
* advertising data.
|
|
|
|
* # @p data->extra_data is NULL
|
|
|
|
* - ULL_ADV_PDU_HDR_FIELD_AUX_PTR: # @p data parameter is not used
|
|
|
|
*
|
|
|
|
* @return Zero in case of success, other value in case of failure.
|
|
|
|
*/
|
|
|
|
uint8_t ull_adv_sync_pdu_set_clear(struct ll_adv_set *adv,
|
|
|
|
uint16_t hdr_add_fields,
|
|
|
|
uint16_t hdr_rem_fields,
|
|
|
|
struct adv_pdu_field_data *data,
|
|
|
|
uint8_t *ter_idx)
|
|
|
|
{
|
|
|
|
struct pdu_adv *pdu_prev, *pdu_new;
|
|
|
|
struct lll_adv_sync *lll_sync;
|
|
|
|
void *extra_data_prev;
|
2021-02-24 13:57:41 +05:30
|
|
|
#if defined(CONFIG_BT_CTLR_DF_ADV_CTE_TX)
|
2021-02-16 15:39:13 +05:30
|
|
|
void *extra_data;
|
|
|
|
#endif /* CONFIG_BT_CTLR_DF_ADV_CTE_TX */
|
|
|
|
int err;
|
|
|
|
|
|
|
|
lll_sync = adv->lll.sync;
|
|
|
|
if (!lll_sync) {
|
|
|
|
return BT_HCI_ERR_UNKNOWN_ADV_IDENTIFIER;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Get reference to previous periodic advertising PDU data */
|
|
|
|
pdu_prev = lll_adv_sync_data_peek(lll_sync, &extra_data_prev);
|
|
|
|
|
2021-02-24 13:57:41 +05:30
|
|
|
#if defined(CONFIG_BT_CTLR_DF_ADV_CTE_TX)
|
2021-02-16 15:39:13 +05:30
|
|
|
/* Get reference to new periodic advertising PDU data buffer */
|
|
|
|
if ((hdr_add_fields & ULL_ADV_PDU_HDR_FIELD_CTE_INFO) ||
|
|
|
|
(!(hdr_rem_fields & ULL_ADV_PDU_HDR_FIELD_CTE_INFO) &&
|
|
|
|
extra_data_prev)) {
|
|
|
|
/* If there was an extra data in past PDU data or it is required
|
|
|
|
* by the hdr_add_fields then allocate memmory for it.
|
|
|
|
*/
|
|
|
|
pdu_new = lll_adv_sync_data_alloc(lll_sync, &extra_data,
|
|
|
|
ter_idx);
|
|
|
|
if (!pdu_new) {
|
|
|
|
return BT_HCI_ERR_MEM_CAPACITY_EXCEEDED;
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
extra_data = NULL;
|
|
|
|
#else
|
|
|
|
{
|
|
|
|
#endif /* CONFIG_BT_CTLR_DF_ADV_CTE_TX */
|
|
|
|
pdu_new = lll_adv_sync_data_alloc(lll_sync, NULL, ter_idx);
|
|
|
|
if (!pdu_new) {
|
|
|
|
return BT_HCI_ERR_MEM_CAPACITY_EXCEEDED;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
err = adv_sync_hdr_set_clear(lll_sync, pdu_prev, pdu_new,
|
|
|
|
hdr_add_fields, hdr_rem_fields,
|
|
|
|
(data ? data->field_data : NULL));
|
|
|
|
if (err) {
|
|
|
|
return err;
|
|
|
|
}
|
|
|
|
|
2021-02-24 13:57:41 +05:30
|
|
|
#if defined(CONFIG_BT_CTLR_DF_ADV_CTE_TX)
|
2021-02-16 15:39:13 +05:30
|
|
|
if (extra_data) {
|
|
|
|
adv_sync_extra_data_set_clear(extra_data_prev, extra_data,
|
|
|
|
hdr_add_fields, hdr_rem_fields,
|
|
|
|
(data ? data->extra_data : NULL));
|
|
|
|
}
|
|
|
|
#endif /* CONFIG_BT_CTLR_DF_ADV_CTE_TX */
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2020-03-13 16:24:01 +05:30
|
|
|
static int init_reset(void)
|
|
|
|
{
|
|
|
|
/* Initialize adv sync pool. */
|
|
|
|
mem_init(ll_adv_sync_pool, sizeof(struct ll_adv_sync_set),
|
|
|
|
sizeof(ll_adv_sync_pool) / sizeof(struct ll_adv_sync_set),
|
|
|
|
&adv_sync_free);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline struct ll_adv_sync_set *sync_acquire(void)
|
|
|
|
{
|
|
|
|
return mem_acquire(&adv_sync_free);
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline void sync_release(struct ll_adv_sync_set *sync)
|
|
|
|
{
|
|
|
|
mem_release(sync, &adv_sync_free);
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline uint16_t sync_handle_get(struct ll_adv_sync_set *sync)
|
|
|
|
{
|
|
|
|
return mem_index_get(sync, ll_adv_sync_pool,
|
|
|
|
sizeof(struct ll_adv_sync_set));
|
|
|
|
}
|
|
|
|
|
2020-10-20 17:12:28 +05:30
|
|
|
static uint8_t sync_stop(struct ll_adv_sync_set *sync)
|
2020-02-12 08:55:57 +05:30
|
|
|
{
|
|
|
|
uint8_t sync_handle;
|
2020-11-12 15:11:43 +01:00
|
|
|
int err;
|
2020-02-12 08:55:57 +05:30
|
|
|
|
|
|
|
sync_handle = sync_handle_get(sync);
|
|
|
|
|
2020-11-12 15:11:43 +01:00
|
|
|
err = ull_ticker_stop_with_mark(TICKER_ID_ADV_SYNC_BASE + sync_handle,
|
|
|
|
sync, &sync->lll);
|
|
|
|
LL_ASSERT(err == 0 || err == -EALREADY);
|
|
|
|
if (err) {
|
2020-02-12 08:55:57 +05:30
|
|
|
return BT_HCI_ERR_CMD_DISALLOWED;
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2020-10-20 17:12:28 +05:30
|
|
|
static inline uint8_t sync_remove(struct ll_adv_sync_set *sync,
|
|
|
|
struct ll_adv_set *adv, uint8_t enable)
|
|
|
|
{
|
|
|
|
uint8_t pri_idx;
|
|
|
|
uint8_t err;
|
|
|
|
|
|
|
|
/* Remove sync_info from auxiliary PDU */
|
|
|
|
err = ull_adv_aux_hdr_set_clear(adv, 0,
|
|
|
|
ULL_ADV_PDU_HDR_FIELD_SYNC_INFO,
|
|
|
|
NULL, NULL, &pri_idx);
|
|
|
|
if (err) {
|
|
|
|
return err;
|
|
|
|
}
|
|
|
|
|
|
|
|
lll_adv_data_enqueue(&adv->lll, pri_idx);
|
|
|
|
|
|
|
|
if (sync->is_started) {
|
|
|
|
/* TODO: we removed sync info, but if sync_stop() fails, what do
|
|
|
|
* we do?
|
|
|
|
*/
|
|
|
|
err = sync_stop(sync);
|
|
|
|
if (err) {
|
|
|
|
return err;
|
|
|
|
}
|
|
|
|
|
|
|
|
sync->is_started = 0U;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (!enable) {
|
|
|
|
sync->is_enabled = 0U;
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0U;
|
|
|
|
}
|
|
|
|
|
2021-01-22 05:38:47 -08:00
|
|
|
/* @brief Set or clear fields in extended advertising header.
|
|
|
|
*
|
|
|
|
* @param[in] adv Advertising set.
|
|
|
|
* @param[in] hdr_add_fields Flag with information which fields add.
|
|
|
|
* @param[in] hdr_rem_fields Flag with information which fields remove.
|
|
|
|
* @param[in] value Pointer to data to be added to header.
|
|
|
|
* Content depends on the value of
|
|
|
|
* @p hdr_add_fields.
|
|
|
|
* @param[out] ter_idx Index of new PDU.
|
|
|
|
*
|
|
|
|
* @Note
|
|
|
|
* @p value depends on the flag provided by @p hdr_add_fields.
|
|
|
|
* Information about content of value may be found in description of
|
|
|
|
* @ref ull_adv_sync_pdu_set_clear.
|
|
|
|
*
|
|
|
|
* @return Zero in case of success, other value in case of failure.
|
|
|
|
*/
|
|
|
|
static uint8_t adv_sync_hdr_set_clear(struct lll_adv_sync *lll_sync,
|
|
|
|
struct pdu_adv *ter_pdu_prev,
|
|
|
|
struct pdu_adv *ter_pdu,
|
|
|
|
uint16_t hdr_add_fields,
|
|
|
|
uint16_t hdr_rem_fields,
|
|
|
|
void *value)
|
|
|
|
{
|
|
|
|
struct pdu_adv_com_ext_adv *ter_com_hdr, *ter_com_hdr_prev;
|
|
|
|
struct pdu_adv_ext_hdr *ter_hdr, ter_hdr_prev;
|
|
|
|
uint8_t *ter_dptr, *ter_dptr_prev;
|
2021-01-04 13:05:09 +05:30
|
|
|
uint8_t acad_len_prev;
|
2021-02-23 19:18:23 +05:30
|
|
|
uint8_t ter_len_prev;
|
|
|
|
uint8_t hdr_buf_len;
|
|
|
|
uint16_t ter_len;
|
2021-01-22 05:38:47 -08:00
|
|
|
uint8_t *ad_data;
|
2021-02-24 13:57:41 +05:30
|
|
|
#if defined(CONFIG_BT_CTLR_DF_ADV_CTE_TX)
|
2021-01-22 05:38:47 -08:00
|
|
|
uint8_t cte_info;
|
|
|
|
#endif /* CONFIG_BT_CTLR_DF_ADV_CTE_TX */
|
|
|
|
uint8_t ad_len;
|
|
|
|
|
|
|
|
/* Get common pointers from reference to previous tertiary PDU data */
|
|
|
|
ter_com_hdr_prev = (void *)&ter_pdu_prev->adv_ext_ind;
|
|
|
|
ter_hdr = (void *)ter_com_hdr_prev->ext_hdr_adv_data;
|
2021-05-31 17:08:51 +05:30
|
|
|
if (ter_com_hdr_prev->ext_hdr_len) {
|
|
|
|
ter_hdr_prev = *ter_hdr;
|
|
|
|
} else {
|
|
|
|
*(uint8_t *)&ter_hdr_prev = 0U;
|
|
|
|
}
|
2021-01-22 05:38:47 -08:00
|
|
|
ter_dptr_prev = ter_hdr->data;
|
|
|
|
|
|
|
|
/* Set common fields in reference to new tertiary PDU data buffer */
|
|
|
|
ter_pdu->type = ter_pdu_prev->type;
|
|
|
|
ter_pdu->rfu = 0U;
|
|
|
|
ter_pdu->chan_sel = 0U;
|
|
|
|
|
|
|
|
ter_pdu->tx_addr = ter_pdu_prev->tx_addr;
|
|
|
|
ter_pdu->rx_addr = ter_pdu_prev->rx_addr;
|
|
|
|
|
|
|
|
ter_com_hdr = (void *)&ter_pdu->adv_ext_ind;
|
|
|
|
ter_com_hdr->adv_mode = ter_com_hdr_prev->adv_mode;
|
|
|
|
ter_hdr = (void *)ter_com_hdr->ext_hdr_adv_data;
|
|
|
|
ter_dptr = ter_hdr->data;
|
|
|
|
*(uint8_t *)ter_hdr = 0U;
|
|
|
|
|
|
|
|
/* No AdvA in AUX_SYNC_IND */
|
|
|
|
/* No TargetA in AUX_SYNC_IND */
|
|
|
|
|
2021-02-24 13:57:41 +05:30
|
|
|
#if defined(CONFIG_BT_CTLR_DF_ADV_CTE_TX)
|
2021-01-22 05:38:47 -08:00
|
|
|
/* If requested add or update CTEInfo */
|
|
|
|
if (hdr_add_fields & ULL_ADV_PDU_HDR_FIELD_CTE_INFO) {
|
|
|
|
ter_hdr->cte_info = 1;
|
|
|
|
cte_info = *(uint8_t *)value;
|
|
|
|
value = (uint8_t *)value + 1;
|
|
|
|
ter_dptr += sizeof(struct pdu_cte_info);
|
|
|
|
/* If CTEInfo exists in prev and is not requested to be removed */
|
|
|
|
} else if (!(hdr_rem_fields & ULL_ADV_PDU_HDR_FIELD_CTE_INFO) &&
|
|
|
|
ter_hdr_prev.cte_info) {
|
|
|
|
ter_hdr->cte_info = 1;
|
|
|
|
ter_dptr += sizeof(struct pdu_cte_info);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* If CTEInfo exists in prev PDU */
|
|
|
|
if (ter_hdr_prev.cte_info) {
|
|
|
|
ter_dptr_prev += sizeof(struct pdu_cte_info);
|
|
|
|
}
|
|
|
|
#endif /* CONFIG_BT_CTLR_DF_ADV_CTE_TX */
|
|
|
|
|
|
|
|
/* No ADI in AUX_SYNC_IND */
|
|
|
|
|
|
|
|
/* AuxPtr - will be added if AUX_CHAIN_IND is required */
|
|
|
|
if ((hdr_add_fields & ULL_ADV_PDU_HDR_FIELD_AUX_PTR) ||
|
|
|
|
(!(hdr_rem_fields & ULL_ADV_PDU_HDR_FIELD_AUX_PTR) &&
|
|
|
|
ter_hdr_prev.aux_ptr)) {
|
|
|
|
ter_hdr->aux_ptr = 1;
|
|
|
|
}
|
|
|
|
if (ter_hdr->aux_ptr) {
|
|
|
|
ter_dptr += sizeof(struct pdu_adv_aux_ptr);
|
|
|
|
}
|
|
|
|
if (ter_hdr_prev.aux_ptr) {
|
|
|
|
ter_dptr_prev += sizeof(struct pdu_adv_aux_ptr);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* No SyncInfo in AUX_SYNC_IND */
|
|
|
|
|
|
|
|
/* Tx Power flag */
|
|
|
|
if (ter_hdr_prev.tx_pwr) {
|
|
|
|
ter_dptr_prev++;
|
|
|
|
|
|
|
|
ter_hdr->tx_pwr = 1;
|
|
|
|
ter_dptr++;
|
|
|
|
}
|
|
|
|
|
2021-01-04 13:05:09 +05:30
|
|
|
/* Calc previous ACAD len and update PDU len */
|
|
|
|
ter_len_prev = ter_dptr_prev - (uint8_t *)ter_com_hdr_prev;
|
2021-02-23 19:18:23 +05:30
|
|
|
hdr_buf_len = ter_com_hdr_prev->ext_hdr_len +
|
|
|
|
PDU_AC_EXT_HEADER_SIZE_MIN;
|
|
|
|
if (ter_len_prev <= hdr_buf_len) {
|
|
|
|
acad_len_prev = hdr_buf_len - ter_len_prev;
|
2021-01-04 13:05:09 +05:30
|
|
|
ter_len_prev += acad_len_prev;
|
|
|
|
ter_dptr_prev += acad_len_prev;
|
|
|
|
ter_dptr += acad_len_prev;
|
|
|
|
} else {
|
|
|
|
acad_len_prev = 0;
|
|
|
|
/* NOTE: If no flags are set then extended header length will be
|
|
|
|
* zero. Under this condition the current ter_len_prev
|
|
|
|
* value will be greater than extended header length,
|
|
|
|
* hence set ter_len_prev to size of the length/mode
|
|
|
|
* field.
|
|
|
|
*/
|
2021-02-23 19:18:23 +05:30
|
|
|
ter_len_prev = PDU_AC_EXT_HEADER_SIZE_MIN;
|
2021-01-04 13:05:09 +05:30
|
|
|
ter_dptr_prev = (uint8_t *)ter_com_hdr_prev + ter_len_prev;
|
|
|
|
}
|
2021-01-22 05:38:47 -08:00
|
|
|
|
|
|
|
/* Did we parse beyond PDU length? */
|
|
|
|
if (ter_len_prev > ter_pdu_prev->len) {
|
|
|
|
/* we should not encounter invalid length */
|
|
|
|
return BT_HCI_ERR_UNSPECIFIED;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Calc current tertiary PDU len */
|
|
|
|
ter_len = ull_adv_aux_hdr_len_calc(ter_com_hdr, &ter_dptr);
|
|
|
|
ull_adv_aux_hdr_len_fill(ter_com_hdr, ter_len);
|
|
|
|
|
|
|
|
/* Get Adv data from function parameters */
|
|
|
|
if (hdr_add_fields & ULL_ADV_PDU_HDR_FIELD_AD_DATA) {
|
|
|
|
ad_data = value;
|
|
|
|
ad_len = *ad_data;
|
|
|
|
++ad_data;
|
|
|
|
|
|
|
|
ad_data = (void *)sys_get_le32(ad_data);
|
|
|
|
} else if (!(hdr_rem_fields & ULL_ADV_PDU_HDR_FIELD_AD_DATA)) {
|
|
|
|
ad_len = ter_pdu_prev->len - ter_len_prev;
|
|
|
|
ad_data = ter_dptr_prev;
|
|
|
|
} else {
|
|
|
|
ad_len = 0;
|
|
|
|
ad_data = NULL;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Add AD len to tertiary PDU length */
|
|
|
|
ter_len += ad_len;
|
|
|
|
|
|
|
|
/* Check AdvData overflow */
|
|
|
|
if (ter_len > PDU_AC_PAYLOAD_SIZE_MAX) {
|
|
|
|
return BT_HCI_ERR_PACKET_TOO_LONG;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* set the secondary PDU len */
|
|
|
|
ter_pdu->len = ter_len;
|
|
|
|
|
|
|
|
/* Start filling tertiary PDU payload based on flags from here
|
|
|
|
* ==============================================================
|
|
|
|
*/
|
|
|
|
|
|
|
|
/* Fill AdvData in tertiary PDU */
|
|
|
|
memmove(ter_dptr, ad_data, ad_len);
|
|
|
|
|
2021-05-31 17:08:17 +05:30
|
|
|
/* Early exit if no flags set */
|
|
|
|
if (!ter_com_hdr->ext_hdr_len) {
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2021-01-04 13:05:09 +05:30
|
|
|
/* Fill ACAD in tertiary PDU */
|
|
|
|
ter_dptr_prev -= acad_len_prev;
|
|
|
|
ter_dptr -= acad_len_prev;
|
|
|
|
memmove(ter_dptr, ter_dptr_prev, acad_len_prev);
|
2021-01-22 05:38:47 -08:00
|
|
|
|
|
|
|
/* Tx Power */
|
|
|
|
if (ter_hdr->tx_pwr) {
|
|
|
|
*--ter_dptr = *--ter_dptr_prev;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* No SyncInfo in AUX_SYNC_IND */
|
|
|
|
|
|
|
|
/* AuxPtr */
|
|
|
|
if (ter_hdr->aux_ptr) {
|
|
|
|
/* ToDo Update setup of aux_ptr - check documentation */
|
|
|
|
if (ter_hdr_prev.aux_ptr) {
|
|
|
|
ter_dptr_prev -= sizeof(struct pdu_adv_aux_ptr);
|
|
|
|
ter_dptr -= sizeof(struct pdu_adv_aux_ptr);
|
|
|
|
memmove(ter_dptr, ter_dptr_prev,
|
|
|
|
sizeof(struct pdu_adv_aux_ptr));
|
|
|
|
} else {
|
|
|
|
ull_adv_aux_ptr_fill(&ter_dptr, lll_sync->adv->phy_s);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/* No ADI in AUX_SYNC_IND*/
|
|
|
|
|
2021-02-24 13:57:41 +05:30
|
|
|
#if defined(CONFIG_BT_CTLR_DF_ADV_CTE_TX)
|
2021-01-22 05:38:47 -08:00
|
|
|
if (ter_hdr->cte_info) {
|
|
|
|
if (hdr_add_fields & ULL_ADV_PDU_HDR_FIELD_CTE_INFO) {
|
|
|
|
*--ter_dptr = cte_info;
|
|
|
|
} else {
|
|
|
|
*--ter_dptr = *--ter_dptr_prev;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
#endif /* CONFIG_BT_CTLR_DF_ADV_CTE_TX */
|
|
|
|
|
|
|
|
/* No TargetA in AUX_SYNC_IND */
|
|
|
|
/* No AdvA in AUX_SYNC_IND */
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2021-02-24 13:57:41 +05:30
|
|
|
#if defined(CONFIG_BT_CTLR_DF_ADV_CTE_TX)
|
2021-01-22 05:38:47 -08:00
|
|
|
/* @brief Set or clear fields in extended advertising header and store
|
|
|
|
* extra_data if requested.
|
|
|
|
*
|
|
|
|
* @param[in] extra_data_prev Pointer to previous content of extra_data.
|
|
|
|
* @param[in] hdr_add_fields Flag with information which fields add.
|
|
|
|
* @param[in] hdr_rem_fields Flag with information which fields remove.
|
|
|
|
* @param[in] data Pointer to data to be stored in extra_data.
|
|
|
|
* Content depends on the data depends on
|
|
|
|
* @p hdr_add_fields.
|
|
|
|
*
|
|
|
|
* @Note
|
|
|
|
* @p data depends on the flag provided by @p hdr_add_fields.
|
|
|
|
* Information about content of value may be found in description of
|
|
|
|
* @ref ull_adv_sync_pdu_set_clear.
|
|
|
|
*
|
|
|
|
* @return Zero in case of success, other value in case of failure.
|
|
|
|
*/
|
|
|
|
static inline void adv_sync_extra_data_set_clear(void *extra_data_prev,
|
|
|
|
void *extra_data_new,
|
|
|
|
uint16_t hdr_add_fields,
|
|
|
|
uint16_t hdr_rem_fields,
|
|
|
|
void *data)
|
|
|
|
{
|
|
|
|
/* Currently only CTE enable requires extra_data. Due to that fact
|
|
|
|
* CTE additional data are just copied to extra_data memory.
|
|
|
|
*/
|
|
|
|
if (hdr_add_fields & ULL_ADV_PDU_HDR_FIELD_CTE_INFO) {
|
|
|
|
memcpy(extra_data_new, data, sizeof(struct lll_df_adv_cfg));
|
|
|
|
} else if ((hdr_rem_fields & ULL_ADV_PDU_HDR_FIELD_CTE_INFO) ||
|
|
|
|
extra_data_prev) {
|
|
|
|
memmove(extra_data_new, extra_data_prev,
|
|
|
|
sizeof(struct lll_df_adv_cfg));
|
|
|
|
}
|
|
|
|
}
|
|
|
|
#endif /* CONFIG_BT_CTLR_DF_ADV_CTE_TX */
|
|
|
|
|
2020-02-12 08:55:57 +05:30
|
|
|
static void mfy_sync_offset_get(void *param)
|
|
|
|
{
|
|
|
|
struct ll_adv_set *adv = param;
|
2020-07-17 15:27:42 +05:30
|
|
|
struct lll_adv_sync *lll_sync;
|
2020-02-12 08:55:57 +05:30
|
|
|
struct ll_adv_sync_set *sync;
|
2020-07-17 15:27:42 +05:30
|
|
|
struct pdu_adv_sync_info *si;
|
2020-02-12 08:55:57 +05:30
|
|
|
uint32_t ticks_to_expire;
|
|
|
|
uint32_t ticks_current;
|
|
|
|
struct pdu_adv *pdu;
|
|
|
|
uint8_t ticker_id;
|
2021-03-15 16:13:22 +05:30
|
|
|
uint16_t lazy;
|
2020-02-12 08:55:57 +05:30
|
|
|
uint8_t retry;
|
|
|
|
uint8_t id;
|
|
|
|
|
2020-07-17 15:27:42 +05:30
|
|
|
lll_sync = adv->lll.sync;
|
2021-04-05 12:56:51 +05:30
|
|
|
sync = HDR_LLL2ULL(lll_sync);
|
2020-02-12 08:55:57 +05:30
|
|
|
ticker_id = TICKER_ID_ADV_SYNC_BASE + sync_handle_get(sync);
|
|
|
|
|
|
|
|
id = TICKER_NULL;
|
|
|
|
ticks_to_expire = 0U;
|
|
|
|
ticks_current = 0U;
|
|
|
|
retry = 4U;
|
|
|
|
do {
|
2020-07-16 12:34:23 +05:30
|
|
|
uint32_t volatile ret_cb;
|
2020-02-12 08:55:57 +05:30
|
|
|
uint32_t ticks_previous;
|
|
|
|
uint32_t ret;
|
2021-05-19 07:03:27 +05:30
|
|
|
bool success;
|
2020-02-12 08:55:57 +05:30
|
|
|
|
|
|
|
ticks_previous = ticks_current;
|
|
|
|
|
2020-07-16 12:34:23 +05:30
|
|
|
ret_cb = TICKER_STATUS_BUSY;
|
2021-03-15 16:13:22 +05:30
|
|
|
ret = ticker_next_slot_get_ext(TICKER_INSTANCE_ID_CTLR,
|
|
|
|
TICKER_USER_ID_ULL_LOW,
|
|
|
|
&id, &ticks_current,
|
|
|
|
&ticks_to_expire, &lazy,
|
|
|
|
ticker_op_cb, (void *)&ret_cb);
|
2020-02-12 08:55:57 +05:30
|
|
|
if (ret == TICKER_STATUS_BUSY) {
|
|
|
|
while (ret_cb == TICKER_STATUS_BUSY) {
|
|
|
|
ticker_job_sched(TICKER_INSTANCE_ID_CTLR,
|
|
|
|
TICKER_USER_ID_ULL_LOW);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2021-05-19 07:03:27 +05:30
|
|
|
success = (ret_cb == TICKER_STATUS_SUCCESS);
|
|
|
|
LL_ASSERT(success);
|
2020-02-12 08:55:57 +05:30
|
|
|
|
|
|
|
LL_ASSERT((ticks_current == ticks_previous) || retry--);
|
|
|
|
|
|
|
|
LL_ASSERT(id != TICKER_NULL);
|
|
|
|
} while (id != ticker_id);
|
|
|
|
|
|
|
|
/* NOTE: as remainder not used in scheduling primary PDU
|
|
|
|
* packet timer starts transmission after 1 tick hence the +1.
|
|
|
|
*/
|
2020-07-17 15:27:42 +05:30
|
|
|
lll_sync->ticks_offset = ticks_to_expire + 1;
|
2020-02-12 08:55:57 +05:30
|
|
|
|
|
|
|
pdu = lll_adv_aux_data_curr_get(adv->lll.aux);
|
2020-07-17 15:27:42 +05:30
|
|
|
si = sync_info_get(pdu);
|
|
|
|
sync_info_offset_fill(si, ticks_to_expire, 0);
|
2021-03-15 16:13:22 +05:30
|
|
|
si->evt_cntr = lll_sync->event_counter + lll_sync->latency_prepare +
|
|
|
|
lazy;
|
2020-07-17 15:27:42 +05:30
|
|
|
}
|
|
|
|
|
|
|
|
static inline struct pdu_adv_sync_info *sync_info_get(struct pdu_adv *pdu)
|
|
|
|
{
|
|
|
|
struct pdu_adv_com_ext_adv *p;
|
2020-11-09 15:02:38 +01:00
|
|
|
struct pdu_adv_ext_hdr *h;
|
2020-07-17 15:27:42 +05:30
|
|
|
uint8_t *ptr;
|
|
|
|
|
|
|
|
p = (void *)&pdu->adv_ext_ind;
|
2020-11-09 14:53:54 +01:00
|
|
|
h = (void *)p->ext_hdr_adv_data;
|
2020-11-09 15:22:49 +01:00
|
|
|
ptr = h->data;
|
2020-07-17 15:27:42 +05:30
|
|
|
|
|
|
|
if (h->adv_addr) {
|
|
|
|
ptr += BDADDR_SIZE;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (h->adi) {
|
|
|
|
ptr += sizeof(struct pdu_adv_adi);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (h->aux_ptr) {
|
|
|
|
ptr += sizeof(struct pdu_adv_aux_ptr);
|
|
|
|
}
|
|
|
|
|
|
|
|
return (void *)ptr;
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline void sync_info_offset_fill(struct pdu_adv_sync_info *si,
|
|
|
|
uint32_t ticks_offset,
|
|
|
|
uint32_t start_us)
|
|
|
|
{
|
|
|
|
uint32_t offs;
|
|
|
|
|
|
|
|
offs = HAL_TICKER_TICKS_TO_US(ticks_offset) - start_us;
|
2020-09-30 13:40:13 +05:30
|
|
|
offs = offs / OFFS_UNIT_30_US;
|
|
|
|
if (!!(offs >> 13)) {
|
|
|
|
si->offs = offs / (OFFS_UNIT_300_US / OFFS_UNIT_30_US);
|
|
|
|
si->offs_units = 1U;
|
2020-07-17 15:27:42 +05:30
|
|
|
} else {
|
2020-09-30 13:40:13 +05:30
|
|
|
si->offs = offs;
|
|
|
|
si->offs_units = 0U;
|
2020-07-17 15:27:42 +05:30
|
|
|
}
|
2020-02-12 08:55:57 +05:30
|
|
|
}
|
|
|
|
|
2020-03-13 16:24:01 +05:30
|
|
|
static void ticker_cb(uint32_t ticks_at_expire, uint32_t remainder,
|
2021-03-03 15:41:55 +01:00
|
|
|
uint16_t lazy, uint8_t force, void *param)
|
2020-03-13 16:24:01 +05:30
|
|
|
{
|
|
|
|
static memq_link_t link;
|
2020-03-13 16:24:01 +05:30
|
|
|
static struct mayfly mfy = {0, 0, &link, NULL, lll_adv_sync_prepare};
|
2020-03-13 16:24:01 +05:30
|
|
|
static struct lll_prepare_param p;
|
|
|
|
struct ll_adv_sync_set *sync = param;
|
|
|
|
struct lll_adv_sync *lll;
|
|
|
|
uint32_t ret;
|
|
|
|
uint8_t ref;
|
|
|
|
|
|
|
|
DEBUG_RADIO_PREPARE_A(1);
|
|
|
|
|
|
|
|
lll = &sync->lll;
|
|
|
|
|
|
|
|
/* Increment prepare reference count */
|
|
|
|
ref = ull_ref_inc(&sync->ull);
|
|
|
|
LL_ASSERT(ref);
|
|
|
|
|
|
|
|
/* Append timing parameters */
|
|
|
|
p.ticks_at_expire = ticks_at_expire;
|
|
|
|
p.remainder = remainder;
|
|
|
|
p.lazy = lazy;
|
2021-03-03 15:41:55 +01:00
|
|
|
p.force = force;
|
2020-03-13 16:24:01 +05:30
|
|
|
p.param = lll;
|
|
|
|
mfy.param = &p;
|
|
|
|
|
|
|
|
/* Kick LLL prepare */
|
|
|
|
ret = mayfly_enqueue(TICKER_USER_ID_ULL_HIGH,
|
|
|
|
TICKER_USER_ID_LLL, 0, &mfy);
|
|
|
|
LL_ASSERT(!ret);
|
|
|
|
|
|
|
|
DEBUG_RADIO_PREPARE_A(1);
|
|
|
|
}
|
2020-02-12 08:55:57 +05:30
|
|
|
|
|
|
|
static void ticker_op_cb(uint32_t status, void *param)
|
|
|
|
{
|
|
|
|
*((uint32_t volatile *)param) = status;
|
|
|
|
}
|