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zephyr/soc/ite/ec/common/soc_common.h

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soc/riscv: it8xxx2 soc system A new platform soc for it8xxx2. Revising the test/kernel/context/src/main.c for it8xxx2 test case. Signed-off-by: Cheryl Su <cheryl.su@ite.com.tw>
2020-09-09 16:45:45 +08:00
/*
* Copyright (c) 2017 Jean-Paul Etienne <fractalclone@gmail.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file configuration macros for riscv SOCs supporting the riscv
* privileged architecture specification
*/
#ifndef __SOC_COMMON_H_
#define __SOC_COMMON_H_
#include "chip_chipregs.h"
#ifndef _ASMLANGUAGE
ITE drivers/interrupt_controller: add intc_ite_it8xxx2_v2 driver This driver is made for it82xx2 series. Signed-off-by: Ruibin Chang <Ruibin.Chang@ite.com.tw>
2022-10-05 14:05:43 +08:00
#ifdef CONFIG_HAS_ITE_INTC
soc: it8xxx2: introduce SOC_IT8XXX2_PLL_FLASH_48M option Enable SOC_IT8XXX2_PLL_FLASH_48M at default to reduce latency of fetching code from flash. Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
2021-07-05 14:08:50 +08:00
/*
* Save current interrupt state of soc-level into ier_setting[] with
* disabling interrupt.
*/
void ite_intc_save_and_disable_interrupts(void);
/* Restore interrupt state of soc-level from ier_setting[], use with care. */
void ite_intc_restore_interrupts(void);
soc/riscv: it8xxx2 soc system A new platform soc for it8xxx2. Revising the test/kernel/context/src/main.c for it8xxx2 test case. Signed-off-by: Cheryl Su <cheryl.su@ite.com.tw>
2020-09-09 16:45:45 +08:00
extern void ite_intc_irq_enable(unsigned int irq);
extern void ite_intc_irq_disable(unsigned int irq);
drivers: gpio: ite_it8xxx2: enable more gpio groups This change enables A, C, D, E, G, H, I, J, K, and L groups, and fix gpio interrupt function. This change also pull (and rename) dt-bindings/irq.h to dt-bindings/interrupt-controller/ite-intc.h, because it is chip-specific. Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Change-Id: Ifee039981c2cc4cf5980e663702a9921e629fc1e
2021-04-21 16:35:17 +08:00
extern uint8_t ite_intc_get_irq_num(void);
soc/riscv: it8xxx2 soc system A new platform soc for it8xxx2. Revising the test/kernel/context/src/main.c for it8xxx2 test case. Signed-off-by: Cheryl Su <cheryl.su@ite.com.tw>
2020-09-09 16:45:45 +08:00
extern int ite_intc_irq_is_enable(unsigned int irq);
ITE: cleanup: it8xxx2: drivers/intc rename the function The function should be renamed ite_intc_irq_polarity_set. Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
2021-10-26 18:18:17 +08:00
extern void ite_intc_irq_polarity_set(unsigned int irq, unsigned int flags);
drivers/interrupt_controller/intc_ite_it8xxx2: global ite_intc_isr_clear() We need to clear interrupt status, before we enable the interrupt. So I let ite_intc_isr_clear() to be global function. Signed-off-by: Ruibin Chang <ruibin.chang@ite.com.tw>
2021-04-09 17:51:09 +08:00
extern void ite_intc_isr_clear(unsigned int irq);
it8xxx2: changing PLL sequence is high priority This makes the sequence completed before hardware devices initialization. Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
2022-01-28 11:37:10 +08:00
void ite_intc_init(void);
it8xxx2: re-factor idle routine Don't leave idle state if soc isn't waked-up by an interrupt. (We change to check interrupt controller register) Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
2022-03-24 13:36:41 +08:00
bool ite_intc_no_irq(void);
ITE drivers/interrupt_controller: add intc_ite_it8xxx2_v2 driver This driver is made for it82xx2 series. Signed-off-by: Ruibin Chang <Ruibin.Chang@ite.com.tw>
2022-10-05 14:05:43 +08:00
#endif /* CONFIG_HAS_ITE_INTC */
soc/riscv: it8xxx2 soc system A new platform soc for it8xxx2. Revising the test/kernel/context/src/main.c for it8xxx2 test case. Signed-off-by: Cheryl Su <cheryl.su@ite.com.tw>
2020-09-09 16:45:45 +08:00
soc: it8xxx2: introduce SOC_IT8XXX2_PLL_FLASH_48M option Enable SOC_IT8XXX2_PLL_FLASH_48M at default to reduce latency of fetching code from flash. Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
2021-07-05 14:08:50 +08:00
#ifdef CONFIG_SOC_IT8XXX2_PLL_FLASH_48M
void timer_5ms_one_shot(void);
#endif
ITE: drivers/i2c: I2C driver divided into two compatibles As mentioned in #42882, the I2C of IT8XXX2 is designed for two different IP blocks, so this PR divides this I2C driver into two compatibles. Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
2022-02-24 18:24:25 +08:00
uint32_t chip_get_pll_freq(void);
ITE: soc: it8xxx2: export PLL control routine to the head file Export the PLL control routine to the head file for hibernate mode accessing. Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
2021-09-02 18:21:51 +08:00
void chip_pll_ctrl(enum chip_pll_mode mode);
ITE: soc/power: add power management Add the power state of deep doze. When system enters deep doze, the clock of CPU and EC can be stopped to reduce power consumption. And enable the UART Rx WUI before entering deep doze to wake up EC and CPU. Tested on it8xxx2_evb board. It will reduce 5.25mA when system enters deep doze mode. Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
2021-10-15 13:20:47 +08:00
void riscv_idle(enum chip_pll_mode mode, unsigned int key);
ITE: soc: it8xxx2: export PLL control routine to the head file Export the PLL control routine to the head file for hibernate mode accessing. Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
2021-09-02 18:21:51 +08:00
soc: ITE: Add ITE it51xxx SoC Add support for ITE it51xxx SoC. NOTE: it51526aw is not support RISCV_ISA_EXT_C. Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
2024-11-08 19:07:06 +08:00
/* Functions for managing the CPU idle state */
ITE: drivers/i2c: Add command queue mode Adding command queue mode can reduce the time between each byte to improve the I2C bus clock stretching during I2C transaction. I2C command queue mode of it8xxx2 can support I2C APIs including: i2c_write(), i2c_read(), i2c_burst_read. Test: 1. tests\drivers\i2c\i2c_api --> pass 2. Reading 16 bytes of data through i2c_burst_read() can reduce 0.72ms(2.54ms->1.82ms) compared to the original pio mode when the frequency is 100KHz. 3. krabby platform can boot normally. Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
2022-05-18 18:40:19 +08:00
void chip_permit_idle(void);
void chip_block_idle(void);
bool cpu_idle_not_allowed(void);
soc/riscv: it8xxx2 soc system A new platform soc for it8xxx2. Revising the test/kernel/context/src/main.c for it8xxx2 test case. Signed-off-by: Cheryl Su <cheryl.su@ite.com.tw>
2020-09-09 16:45:45 +08:00
#endif /* !_ASMLANGUAGE */
#endif /* __SOC_COMMON_H_ */
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