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zephyr/modules/Kconfig.infineon

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soc: arm: add infineon_xmc series support Add infineon xmc series with XMC4500 support. XMC series comes with, - CPU operates upto 120MHz - 3 RAM (PSRAM1 - code, DSRAM1 - data and DSRAM2 - communiation) - upto 1MB flash init: clock control & gpio is not done, so SoC initialization directly relies on HAL. Core operating clock is stored in no_init section, which is kept under DSRAM1. Only DSRAM1 is used until clock support. Using PSRAM1 and DSRAM1 needs adaptation in linker script - planned for next revision. Note: SystemInit cannot be consumed directly due to vector table + HAL linker dependency. Signed-off-by: Parthiban Nallathambi <parthiban@linumiz.com>
2020-04-21 11:37:42 +02:00
# SPDX-License-Identifier: Apache-2.0
#
# Copyright (c) 2020 Linumiz
# Author: Parthiban Nallathambi <parthiban@linumiz.com>
config HAS_XMCLIB
bool
select HAS_CMSIS_CORE
depends on SOC_FAMILY_XMC
if HAS_XMCLIB
config HAS_XMCLIB_UART
bool
help
Enable XMCLIB Universal asynchronous receiver transmitter (UART)
drivers: flash: Add xmc4xxx flash drivers Add xmc4xxx flash drivers. Signed-off-by: Andriy Gelman <andriy.gelman@gmail.com>
2022-09-01 14:26:11 -04:00
config HAS_XMCLIB_FLASH
bool
help
Enable XMCLIB Flash
drivers: interrupt_controller: Add XMC4XXX ERU driver In Infineon XMC4XXX SoCs, gpio interrupts are triggered via an Event Request Unit (ERU) module. A subset of the gpios are connected to the ERU. The ERU monitors edge triggers and creates a SR. This driver configures the ERU for a target port/pin combination for rising/falling edge events. Note that the ERU module does not generate SR based on the gpio level. Internally the ERU tracks the *status* of an event. The status is set on a positive edge and unset on a negative edge (or vice-versa depending on the configuration). The value of the status is used to implement a level triggered interrupt; The ISR checks the status flag and calls the callback function if the status is set. The ERU configurations for supported port/pin combinations are stored in a devicetree file dts/arm/infineon/xmc4xxx_x_x-intc.dtsi. The configurations are stored in the opaque array uint16 port_line_mapping[]. Signed-off-by: Andriy Gelman <andriy.gelman@gmail.com>
2022-07-21 14:33:28 -04:00
config HAS_XMCLIB_ERU
bool
help
Enable XMCLIB Event Request Unit (ERU) for GPIO interrupt support
drivers: adc: Add ADC xmc4xxx drivers The ADC module has four conversion groups, each one is set up as a zephyr device. The start-up calibration is initiated globally for all groups and it is run in each device init function. The ADC module supports post calibration per group. Post calibration is run automatically after each group acquires the samples. Signed-off-by: Andriy Gelman <andriy.gelman@gmail.com>
2022-08-12 10:26:14 -04:00
config HAS_XMCLIB_VADC
bool
help
Enable XMCLIB VADC
drivers: dma: Add infineon xmc4xxx dma support Adds dma drivers for xmc4xxx SoCs. Signed-off-by: Andriy Gelman <andriy.gelman@gmail.com>
2022-12-14 19:30:58 -05:00
config HAS_XMCLIB_DMA
bool
help
Enable XMCLIB DMA
drivers: spi: Add xmc4xxx driver Adds spi driver for xmc4xxx SoCs. Signed-off-by: Andriy Gelman <andriy.gelman@gmail.com>
2022-10-26 12:00:06 -04:00
config HAS_XMCLIB_SPI
bool
help
Enable XMCLIB SPI
driver: i2c: infineon: Adding XMC4 I2C driver - This includes the driver, test app, and sample app - Only the boards\arm\xmc47_relax_kit board is supported for now Signed-off-by: Bill Waters <bill.waters@infineon.com>
2023-07-10 10:25:26 -07:00
config HAS_XMCLIB_I2C
bool
help
Enable XMCLIB I2C
drivers: pwm: Add driver for xmc4xxx using ccu4 module Adds driver for pwm on xmc4xxx using Capture Compare Unit 4 (CCU4) module. There are four CCU4 with each one having four channels Thus it's possible to have up to 16 pwm output signals. The output of each channel can only be connected to a specific port/pin. The possible connection and gpio configurations are defined using pinctrl. The CCU4 module also has a capture mode. Capture support will be added in the future. Signed-off-by: Andriy Gelman <andriy.gelman@gmail.com>
2023-06-04 21:36:17 -04:00
config HAS_XMCLIB_CCU
bool
help
Enable XMCLIB CCU4/CCU8
drivers: watchdog: Add xmc4xxx support Adds watchdog support for Infineon xmc4xxx MCUs. Signed-off-by: Andriy Gelman <andriy.gelman@gmail.com>
2023-09-21 15:47:13 -04:00
config HAS_XMCLIB_WDT
bool
help
Enable XMCLIB WDT
drivers: mdio: Add xmc4xxx mdio drivers Add mdio drivers for xmc4xxx SoCs. Signed-off-by: Andriy Gelman <andriy.gelman@gmail.com>
2023-12-19 09:50:22 -05:00
config HAS_XMCLIB_ETH
bool
help
Enable XMCLIB Ethernet MAC
drivers: can: Add xmc4xxx CAN support Adds CAN drivers for XMC4xxx SoCs. XMC4xxx has multiple CAN nodes. The nodes share a common clock and a message object pool. The CAN nodes do not have a loopback mode. Instead there is an internal bus which can be used to exchange messages between nodes on the SoC. For this reason tests/samples which rely on the loopback feature have been disabled. Signed-off-by: Andriy Gelman <andriy.gelman@gmail.com>
2023-12-26 12:05:00 -05:00
config HAS_XMCLIB_CAN
bool
help
Enable XMCLIB CAN
soc: arm: add infineon_xmc series support Add infineon xmc series with XMC4500 support. XMC series comes with, - CPU operates upto 120MHz - 3 RAM (PSRAM1 - code, DSRAM1 - data and DSRAM2 - communiation) - upto 1MB flash init: clock control & gpio is not done, so SoC initialization directly relies on HAL. Core operating clock is stored in no_init section, which is kept under DSRAM1. Only DSRAM1 is used until clock support. Using PSRAM1 and DSRAM1 needs adaptation in linker script - planned for next revision. Note: SystemInit cannot be consumed directly due to vector table + HAL linker dependency. Signed-off-by: Parthiban Nallathambi <parthiban@linumiz.com>
2020-04-21 11:37:42 +02:00
endif # HAS_XMCLIB
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