24 lines
593 B
C
24 lines
593 B
C
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/*
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* Copyright (c) 2023 Rivos Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/arch/cpu.h>
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#include <zephyr/devicetree.h>
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#include <zephyr/init.h>
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#define RV_TIMER_BASE (DT_REG_ADDR(DT_NODELABEL(mtimer)))
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static int soc_opentitan_init(const struct device *arg)
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{
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ARG_UNUSED(arg);
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/* Initialize the Machine Timer, so it behaves as a regular one. */
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sys_write32(1u, RV_TIMER_BASE + RV_TIMER_CTRL_REG_OFFSET);
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/* Enable timer interrupts. */
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sys_write32(1u, RV_TIMER_BASE + RV_TIMER_INTR_ENABLE_REG_OFFSET);
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return 0;
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}
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SYS_INIT(soc_opentitan_init, PRE_KERNEL_1, 0);
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