arch: added support for the riscv32 architecture
RISC-V is an open-source instruction set architecture.
Added support for the 32bit version of RISC-V to Zephyr.
1) exceptions/interrupts/faults are handled at the architecture
level via the __irq_wrapper handler. Context saving/restoring
of registers can be handled at both architecture and SOC levels.
If SOC-specific registers need to be saved, SOC level needs to
provide __soc_save_context and __soc_restore_context functions
that shall be accounted by the architecture level, when
corresponding config variable RISCV_SOC_CONTEXT_SAVE is set.
2) As RISC-V architecture does not provide a clear ISA specification
about interrupt handling, each RISC-V SOC handles it in its own
way. Hence, at the architecture level, the __irq_wrapper handler
expects the following functions to be provided by the SOC level:
__soc_is_irq: to check if the exception is the result of an
interrupt or not.
__soc_handle_irq: handle pending IRQ at SOC level (ex: clear
pending IRQ in SOC-specific IRQ register)
3) Thread/task scheduling, as well as IRQ offloading are handled via
the RISC-V system call ("ecall"), which is also handled via the
__irq_wrapper handler. The _Swap asm function just calls "ecall"
to generate an exception.
4) As there is no conventional way of handling CPU power save in
RISC-V, the default nano_cpu_idle and nano_cpu_atomic_idle
functions just unlock interrupts and return to the caller, without
issuing any CPU power saving instruction. Nonetheless, to allow
SOC-level to implement proper CPU power save, nano_cpu_idle and
nano_cpu_atomic_idle functions are defined as __weak
at the architecture level.
Change-Id: I980a161d0009f3f404ad22b226a6229fbb492389
Signed-off-by: Jean-Paul Etienne <fractalclone@gmail.com>
2017-01-11 00:24:30 +01:00
|
|
|
/*
|
|
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|
|
* Copyright (c) 2016 Jean-Paul Etienne <fractalclone@gmail.com>
|
2020-07-21 16:00:39 +02:00
|
|
|
* Copyright (c) 2020 BayLibre, SAS
|
arch: added support for the riscv32 architecture
RISC-V is an open-source instruction set architecture.
Added support for the 32bit version of RISC-V to Zephyr.
1) exceptions/interrupts/faults are handled at the architecture
level via the __irq_wrapper handler. Context saving/restoring
of registers can be handled at both architecture and SOC levels.
If SOC-specific registers need to be saved, SOC level needs to
provide __soc_save_context and __soc_restore_context functions
that shall be accounted by the architecture level, when
corresponding config variable RISCV_SOC_CONTEXT_SAVE is set.
2) As RISC-V architecture does not provide a clear ISA specification
about interrupt handling, each RISC-V SOC handles it in its own
way. Hence, at the architecture level, the __irq_wrapper handler
expects the following functions to be provided by the SOC level:
__soc_is_irq: to check if the exception is the result of an
interrupt or not.
__soc_handle_irq: handle pending IRQ at SOC level (ex: clear
pending IRQ in SOC-specific IRQ register)
3) Thread/task scheduling, as well as IRQ offloading are handled via
the RISC-V system call ("ecall"), which is also handled via the
__irq_wrapper handler. The _Swap asm function just calls "ecall"
to generate an exception.
4) As there is no conventional way of handling CPU power save in
RISC-V, the default nano_cpu_idle and nano_cpu_atomic_idle
functions just unlock interrupts and return to the caller, without
issuing any CPU power saving instruction. Nonetheless, to allow
SOC-level to implement proper CPU power save, nano_cpu_idle and
nano_cpu_atomic_idle functions are defined as __weak
at the architecture level.
Change-Id: I980a161d0009f3f404ad22b226a6229fbb492389
Signed-off-by: Jean-Paul Etienne <fractalclone@gmail.com>
2017-01-11 00:24:30 +01:00
|
|
|
*
|
2017-01-18 17:01:01 -08:00
|
|
|
* SPDX-License-Identifier: Apache-2.0
|
arch: added support for the riscv32 architecture
RISC-V is an open-source instruction set architecture.
Added support for the 32bit version of RISC-V to Zephyr.
1) exceptions/interrupts/faults are handled at the architecture
level via the __irq_wrapper handler. Context saving/restoring
of registers can be handled at both architecture and SOC levels.
If SOC-specific registers need to be saved, SOC level needs to
provide __soc_save_context and __soc_restore_context functions
that shall be accounted by the architecture level, when
corresponding config variable RISCV_SOC_CONTEXT_SAVE is set.
2) As RISC-V architecture does not provide a clear ISA specification
about interrupt handling, each RISC-V SOC handles it in its own
way. Hence, at the architecture level, the __irq_wrapper handler
expects the following functions to be provided by the SOC level:
__soc_is_irq: to check if the exception is the result of an
interrupt or not.
__soc_handle_irq: handle pending IRQ at SOC level (ex: clear
pending IRQ in SOC-specific IRQ register)
3) Thread/task scheduling, as well as IRQ offloading are handled via
the RISC-V system call ("ecall"), which is also handled via the
__irq_wrapper handler. The _Swap asm function just calls "ecall"
to generate an exception.
4) As there is no conventional way of handling CPU power save in
RISC-V, the default nano_cpu_idle and nano_cpu_atomic_idle
functions just unlock interrupts and return to the caller, without
issuing any CPU power saving instruction. Nonetheless, to allow
SOC-level to implement proper CPU power save, nano_cpu_idle and
nano_cpu_atomic_idle functions are defined as __weak
at the architecture level.
Change-Id: I980a161d0009f3f404ad22b226a6229fbb492389
Signed-off-by: Jean-Paul Etienne <fractalclone@gmail.com>
2017-01-11 00:24:30 +01:00
|
|
|
*/
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#include <kernel.h>
|
2019-10-25 00:08:21 +09:00
|
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#include <ksched.h>
|
2020-07-21 16:00:39 +02:00
|
|
|
#include <arch/riscv/csr.h>
|
|
|
|
|
#include <stdio.h>
|
|
|
|
|
#include <core_pmp.h>
|
|
|
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|
#ifdef CONFIG_USERSPACE
|
|
|
|
|
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|
/*
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|
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|
|
* Glogal variable used to know the current mode running.
|
|
|
|
|
* Is not boolean because it must match the PMP granularity of the arch.
|
|
|
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|
*/
|
|
|
|
|
ulong_t is_user_mode;
|
|
|
|
|
bool irq_flag;
|
|
|
|
|
#endif
|
arch: added support for the riscv32 architecture
RISC-V is an open-source instruction set architecture.
Added support for the 32bit version of RISC-V to Zephyr.
1) exceptions/interrupts/faults are handled at the architecture
level via the __irq_wrapper handler. Context saving/restoring
of registers can be handled at both architecture and SOC levels.
If SOC-specific registers need to be saved, SOC level needs to
provide __soc_save_context and __soc_restore_context functions
that shall be accounted by the architecture level, when
corresponding config variable RISCV_SOC_CONTEXT_SAVE is set.
2) As RISC-V architecture does not provide a clear ISA specification
about interrupt handling, each RISC-V SOC handles it in its own
way. Hence, at the architecture level, the __irq_wrapper handler
expects the following functions to be provided by the SOC level:
__soc_is_irq: to check if the exception is the result of an
interrupt or not.
__soc_handle_irq: handle pending IRQ at SOC level (ex: clear
pending IRQ in SOC-specific IRQ register)
3) Thread/task scheduling, as well as IRQ offloading are handled via
the RISC-V system call ("ecall"), which is also handled via the
__irq_wrapper handler. The _Swap asm function just calls "ecall"
to generate an exception.
4) As there is no conventional way of handling CPU power save in
RISC-V, the default nano_cpu_idle and nano_cpu_atomic_idle
functions just unlock interrupts and return to the caller, without
issuing any CPU power saving instruction. Nonetheless, to allow
SOC-level to implement proper CPU power save, nano_cpu_idle and
nano_cpu_atomic_idle functions are defined as __weak
at the architecture level.
Change-Id: I980a161d0009f3f404ad22b226a6229fbb492389
Signed-off-by: Jean-Paul Etienne <fractalclone@gmail.com>
2017-01-11 00:24:30 +01:00
|
|
|
|
2019-03-14 09:20:46 -06:00
|
|
|
void z_thread_entry_wrapper(k_thread_entry_t thread,
|
2020-03-11 18:15:29 -07:00
|
|
|
void *arg1,
|
|
|
|
|
void *arg2,
|
|
|
|
|
void *arg3);
|
arch: added support for the riscv32 architecture
RISC-V is an open-source instruction set architecture.
Added support for the 32bit version of RISC-V to Zephyr.
1) exceptions/interrupts/faults are handled at the architecture
level via the __irq_wrapper handler. Context saving/restoring
of registers can be handled at both architecture and SOC levels.
If SOC-specific registers need to be saved, SOC level needs to
provide __soc_save_context and __soc_restore_context functions
that shall be accounted by the architecture level, when
corresponding config variable RISCV_SOC_CONTEXT_SAVE is set.
2) As RISC-V architecture does not provide a clear ISA specification
about interrupt handling, each RISC-V SOC handles it in its own
way. Hence, at the architecture level, the __irq_wrapper handler
expects the following functions to be provided by the SOC level:
__soc_is_irq: to check if the exception is the result of an
interrupt or not.
__soc_handle_irq: handle pending IRQ at SOC level (ex: clear
pending IRQ in SOC-specific IRQ register)
3) Thread/task scheduling, as well as IRQ offloading are handled via
the RISC-V system call ("ecall"), which is also handled via the
__irq_wrapper handler. The _Swap asm function just calls "ecall"
to generate an exception.
4) As there is no conventional way of handling CPU power save in
RISC-V, the default nano_cpu_idle and nano_cpu_atomic_idle
functions just unlock interrupts and return to the caller, without
issuing any CPU power saving instruction. Nonetheless, to allow
SOC-level to implement proper CPU power save, nano_cpu_idle and
nano_cpu_atomic_idle functions are defined as __weak
at the architecture level.
Change-Id: I980a161d0009f3f404ad22b226a6229fbb492389
Signed-off-by: Jean-Paul Etienne <fractalclone@gmail.com>
2017-01-11 00:24:30 +01:00
|
|
|
|
2019-11-07 12:43:29 -08:00
|
|
|
void arch_new_thread(struct k_thread *thread, k_thread_stack_t *stack,
|
2020-04-23 13:55:56 -07:00
|
|
|
char *stack_ptr, k_thread_entry_t entry,
|
2020-04-23 11:32:08 -07:00
|
|
|
void *p1, void *p2, void *p3)
|
arch: added support for the riscv32 architecture
RISC-V is an open-source instruction set architecture.
Added support for the 32bit version of RISC-V to Zephyr.
1) exceptions/interrupts/faults are handled at the architecture
level via the __irq_wrapper handler. Context saving/restoring
of registers can be handled at both architecture and SOC levels.
If SOC-specific registers need to be saved, SOC level needs to
provide __soc_save_context and __soc_restore_context functions
that shall be accounted by the architecture level, when
corresponding config variable RISCV_SOC_CONTEXT_SAVE is set.
2) As RISC-V architecture does not provide a clear ISA specification
about interrupt handling, each RISC-V SOC handles it in its own
way. Hence, at the architecture level, the __irq_wrapper handler
expects the following functions to be provided by the SOC level:
__soc_is_irq: to check if the exception is the result of an
interrupt or not.
__soc_handle_irq: handle pending IRQ at SOC level (ex: clear
pending IRQ in SOC-specific IRQ register)
3) Thread/task scheduling, as well as IRQ offloading are handled via
the RISC-V system call ("ecall"), which is also handled via the
__irq_wrapper handler. The _Swap asm function just calls "ecall"
to generate an exception.
4) As there is no conventional way of handling CPU power save in
RISC-V, the default nano_cpu_idle and nano_cpu_atomic_idle
functions just unlock interrupts and return to the caller, without
issuing any CPU power saving instruction. Nonetheless, to allow
SOC-level to implement proper CPU power save, nano_cpu_idle and
nano_cpu_atomic_idle functions are defined as __weak
at the architecture level.
Change-Id: I980a161d0009f3f404ad22b226a6229fbb492389
Signed-off-by: Jean-Paul Etienne <fractalclone@gmail.com>
2017-01-11 00:24:30 +01:00
|
|
|
{
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|
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|
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struct __esf *stack_init;
|
|
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|
2020-06-07 16:10:52 +02:00
|
|
|
#ifdef CONFIG_RISCV_SOC_CONTEXT_SAVE
|
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const struct soc_esf soc_esf_init = {SOC_ESF_INIT};
|
|
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|
|
#endif
|
|
|
|
|
|
arch: added support for the riscv32 architecture
RISC-V is an open-source instruction set architecture.
Added support for the 32bit version of RISC-V to Zephyr.
1) exceptions/interrupts/faults are handled at the architecture
level via the __irq_wrapper handler. Context saving/restoring
of registers can be handled at both architecture and SOC levels.
If SOC-specific registers need to be saved, SOC level needs to
provide __soc_save_context and __soc_restore_context functions
that shall be accounted by the architecture level, when
corresponding config variable RISCV_SOC_CONTEXT_SAVE is set.
2) As RISC-V architecture does not provide a clear ISA specification
about interrupt handling, each RISC-V SOC handles it in its own
way. Hence, at the architecture level, the __irq_wrapper handler
expects the following functions to be provided by the SOC level:
__soc_is_irq: to check if the exception is the result of an
interrupt or not.
__soc_handle_irq: handle pending IRQ at SOC level (ex: clear
pending IRQ in SOC-specific IRQ register)
3) Thread/task scheduling, as well as IRQ offloading are handled via
the RISC-V system call ("ecall"), which is also handled via the
__irq_wrapper handler. The _Swap asm function just calls "ecall"
to generate an exception.
4) As there is no conventional way of handling CPU power save in
RISC-V, the default nano_cpu_idle and nano_cpu_atomic_idle
functions just unlock interrupts and return to the caller, without
issuing any CPU power saving instruction. Nonetheless, to allow
SOC-level to implement proper CPU power save, nano_cpu_idle and
nano_cpu_atomic_idle functions are defined as __weak
at the architecture level.
Change-Id: I980a161d0009f3f404ad22b226a6229fbb492389
Signed-off-by: Jean-Paul Etienne <fractalclone@gmail.com>
2017-01-11 00:24:30 +01:00
|
|
|
/* Initial stack frame for thread */
|
2020-04-23 13:55:56 -07:00
|
|
|
stack_init = Z_STACK_PTR_TO_FRAME(struct __esf, stack_ptr);
|
arch: added support for the riscv32 architecture
RISC-V is an open-source instruction set architecture.
Added support for the 32bit version of RISC-V to Zephyr.
1) exceptions/interrupts/faults are handled at the architecture
level via the __irq_wrapper handler. Context saving/restoring
of registers can be handled at both architecture and SOC levels.
If SOC-specific registers need to be saved, SOC level needs to
provide __soc_save_context and __soc_restore_context functions
that shall be accounted by the architecture level, when
corresponding config variable RISCV_SOC_CONTEXT_SAVE is set.
2) As RISC-V architecture does not provide a clear ISA specification
about interrupt handling, each RISC-V SOC handles it in its own
way. Hence, at the architecture level, the __irq_wrapper handler
expects the following functions to be provided by the SOC level:
__soc_is_irq: to check if the exception is the result of an
interrupt or not.
__soc_handle_irq: handle pending IRQ at SOC level (ex: clear
pending IRQ in SOC-specific IRQ register)
3) Thread/task scheduling, as well as IRQ offloading are handled via
the RISC-V system call ("ecall"), which is also handled via the
__irq_wrapper handler. The _Swap asm function just calls "ecall"
to generate an exception.
4) As there is no conventional way of handling CPU power save in
RISC-V, the default nano_cpu_idle and nano_cpu_atomic_idle
functions just unlock interrupts and return to the caller, without
issuing any CPU power saving instruction. Nonetheless, to allow
SOC-level to implement proper CPU power save, nano_cpu_idle and
nano_cpu_atomic_idle functions are defined as __weak
at the architecture level.
Change-Id: I980a161d0009f3f404ad22b226a6229fbb492389
Signed-off-by: Jean-Paul Etienne <fractalclone@gmail.com>
2017-01-11 00:24:30 +01:00
|
|
|
|
|
|
|
|
/* Setup the initial stack frame */
|
2020-04-23 11:32:08 -07:00
|
|
|
stack_init->a0 = (ulong_t)entry;
|
|
|
|
|
stack_init->a1 = (ulong_t)p1;
|
|
|
|
|
stack_init->a2 = (ulong_t)p2;
|
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|
|
|
stack_init->a3 = (ulong_t)p3;
|
2020-10-02 13:09:32 -07:00
|
|
|
|
|
|
|
|
#ifdef CONFIG_THREAD_LOCAL_STORAGE
|
|
|
|
|
stack_init->tp = (ulong_t)thread->tls;
|
|
|
|
|
#endif
|
|
|
|
|
|
arch: added support for the riscv32 architecture
RISC-V is an open-source instruction set architecture.
Added support for the 32bit version of RISC-V to Zephyr.
1) exceptions/interrupts/faults are handled at the architecture
level via the __irq_wrapper handler. Context saving/restoring
of registers can be handled at both architecture and SOC levels.
If SOC-specific registers need to be saved, SOC level needs to
provide __soc_save_context and __soc_restore_context functions
that shall be accounted by the architecture level, when
corresponding config variable RISCV_SOC_CONTEXT_SAVE is set.
2) As RISC-V architecture does not provide a clear ISA specification
about interrupt handling, each RISC-V SOC handles it in its own
way. Hence, at the architecture level, the __irq_wrapper handler
expects the following functions to be provided by the SOC level:
__soc_is_irq: to check if the exception is the result of an
interrupt or not.
__soc_handle_irq: handle pending IRQ at SOC level (ex: clear
pending IRQ in SOC-specific IRQ register)
3) Thread/task scheduling, as well as IRQ offloading are handled via
the RISC-V system call ("ecall"), which is also handled via the
__irq_wrapper handler. The _Swap asm function just calls "ecall"
to generate an exception.
4) As there is no conventional way of handling CPU power save in
RISC-V, the default nano_cpu_idle and nano_cpu_atomic_idle
functions just unlock interrupts and return to the caller, without
issuing any CPU power saving instruction. Nonetheless, to allow
SOC-level to implement proper CPU power save, nano_cpu_idle and
nano_cpu_atomic_idle functions are defined as __weak
at the architecture level.
Change-Id: I980a161d0009f3f404ad22b226a6229fbb492389
Signed-off-by: Jean-Paul Etienne <fractalclone@gmail.com>
2017-01-11 00:24:30 +01:00
|
|
|
/*
|
|
|
|
|
* Following the RISC-V architecture,
|
|
|
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|
* the MSTATUS register (used to globally enable/disable interrupt),
|
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|
* as well as the MEPC register (used to by the core to save the
|
|
|
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|
* value of the program counter at which an interrupt/exception occcurs)
|
|
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|
* need to be saved on the stack, upon an interrupt/exception
|
|
|
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|
* and restored prior to returning from the interrupt/exception.
|
|
|
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* This shall allow to handle nested interrupts.
|
|
|
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*
|
|
|
|
|
* Given that context switching is performed via a system call exception
|
2019-07-24 16:21:58 -04:00
|
|
|
* within the RISCV architecture implementation, initially set:
|
2020-01-03 18:18:24 -08:00
|
|
|
* 1) MSTATUS to MSTATUS_DEF_RESTORE in the thread stack to enable
|
arch: added support for the riscv32 architecture
RISC-V is an open-source instruction set architecture.
Added support for the 32bit version of RISC-V to Zephyr.
1) exceptions/interrupts/faults are handled at the architecture
level via the __irq_wrapper handler. Context saving/restoring
of registers can be handled at both architecture and SOC levels.
If SOC-specific registers need to be saved, SOC level needs to
provide __soc_save_context and __soc_restore_context functions
that shall be accounted by the architecture level, when
corresponding config variable RISCV_SOC_CONTEXT_SAVE is set.
2) As RISC-V architecture does not provide a clear ISA specification
about interrupt handling, each RISC-V SOC handles it in its own
way. Hence, at the architecture level, the __irq_wrapper handler
expects the following functions to be provided by the SOC level:
__soc_is_irq: to check if the exception is the result of an
interrupt or not.
__soc_handle_irq: handle pending IRQ at SOC level (ex: clear
pending IRQ in SOC-specific IRQ register)
3) Thread/task scheduling, as well as IRQ offloading are handled via
the RISC-V system call ("ecall"), which is also handled via the
__irq_wrapper handler. The _Swap asm function just calls "ecall"
to generate an exception.
4) As there is no conventional way of handling CPU power save in
RISC-V, the default nano_cpu_idle and nano_cpu_atomic_idle
functions just unlock interrupts and return to the caller, without
issuing any CPU power saving instruction. Nonetheless, to allow
SOC-level to implement proper CPU power save, nano_cpu_idle and
nano_cpu_atomic_idle functions are defined as __weak
at the architecture level.
Change-Id: I980a161d0009f3f404ad22b226a6229fbb492389
Signed-off-by: Jean-Paul Etienne <fractalclone@gmail.com>
2017-01-11 00:24:30 +01:00
|
|
|
* interrupts when the newly created thread will be scheduled;
|
2019-03-14 09:20:46 -06:00
|
|
|
* 2) MEPC to the address of the z_thread_entry_wrapper in the thread
|
arch: added support for the riscv32 architecture
RISC-V is an open-source instruction set architecture.
Added support for the 32bit version of RISC-V to Zephyr.
1) exceptions/interrupts/faults are handled at the architecture
level via the __irq_wrapper handler. Context saving/restoring
of registers can be handled at both architecture and SOC levels.
If SOC-specific registers need to be saved, SOC level needs to
provide __soc_save_context and __soc_restore_context functions
that shall be accounted by the architecture level, when
corresponding config variable RISCV_SOC_CONTEXT_SAVE is set.
2) As RISC-V architecture does not provide a clear ISA specification
about interrupt handling, each RISC-V SOC handles it in its own
way. Hence, at the architecture level, the __irq_wrapper handler
expects the following functions to be provided by the SOC level:
__soc_is_irq: to check if the exception is the result of an
interrupt or not.
__soc_handle_irq: handle pending IRQ at SOC level (ex: clear
pending IRQ in SOC-specific IRQ register)
3) Thread/task scheduling, as well as IRQ offloading are handled via
the RISC-V system call ("ecall"), which is also handled via the
__irq_wrapper handler. The _Swap asm function just calls "ecall"
to generate an exception.
4) As there is no conventional way of handling CPU power save in
RISC-V, the default nano_cpu_idle and nano_cpu_atomic_idle
functions just unlock interrupts and return to the caller, without
issuing any CPU power saving instruction. Nonetheless, to allow
SOC-level to implement proper CPU power save, nano_cpu_idle and
nano_cpu_atomic_idle functions are defined as __weak
at the architecture level.
Change-Id: I980a161d0009f3f404ad22b226a6229fbb492389
Signed-off-by: Jean-Paul Etienne <fractalclone@gmail.com>
2017-01-11 00:24:30 +01:00
|
|
|
* stack.
|
|
|
|
|
* Hence, when going out of an interrupt/exception/context-switch,
|
|
|
|
|
* after scheduling the newly created thread:
|
|
|
|
|
* 1) interrupts will be enabled, as the MSTATUS register will be
|
|
|
|
|
* restored following the MSTATUS value set within the thread stack;
|
2019-03-14 09:20:46 -06:00
|
|
|
* 2) the core will jump to z_thread_entry_wrapper, as the program
|
arch: added support for the riscv32 architecture
RISC-V is an open-source instruction set architecture.
Added support for the 32bit version of RISC-V to Zephyr.
1) exceptions/interrupts/faults are handled at the architecture
level via the __irq_wrapper handler. Context saving/restoring
of registers can be handled at both architecture and SOC levels.
If SOC-specific registers need to be saved, SOC level needs to
provide __soc_save_context and __soc_restore_context functions
that shall be accounted by the architecture level, when
corresponding config variable RISCV_SOC_CONTEXT_SAVE is set.
2) As RISC-V architecture does not provide a clear ISA specification
about interrupt handling, each RISC-V SOC handles it in its own
way. Hence, at the architecture level, the __irq_wrapper handler
expects the following functions to be provided by the SOC level:
__soc_is_irq: to check if the exception is the result of an
interrupt or not.
__soc_handle_irq: handle pending IRQ at SOC level (ex: clear
pending IRQ in SOC-specific IRQ register)
3) Thread/task scheduling, as well as IRQ offloading are handled via
the RISC-V system call ("ecall"), which is also handled via the
__irq_wrapper handler. The _Swap asm function just calls "ecall"
to generate an exception.
4) As there is no conventional way of handling CPU power save in
RISC-V, the default nano_cpu_idle and nano_cpu_atomic_idle
functions just unlock interrupts and return to the caller, without
issuing any CPU power saving instruction. Nonetheless, to allow
SOC-level to implement proper CPU power save, nano_cpu_idle and
nano_cpu_atomic_idle functions are defined as __weak
at the architecture level.
Change-Id: I980a161d0009f3f404ad22b226a6229fbb492389
Signed-off-by: Jean-Paul Etienne <fractalclone@gmail.com>
2017-01-11 00:24:30 +01:00
|
|
|
* counter will be restored following the MEPC value set within the
|
|
|
|
|
* thread stack.
|
|
|
|
|
*/
|
2020-01-03 18:18:24 -08:00
|
|
|
stack_init->mstatus = MSTATUS_DEF_RESTORE;
|
2020-07-21 16:00:39 +02:00
|
|
|
|
|
|
|
|
#if defined(CONFIG_PMP_STACK_GUARD) || defined(CONFIG_USERSPACE)
|
|
|
|
|
z_riscv_pmp_init_thread(thread);
|
|
|
|
|
#endif /* CONFIG_PMP_STACK_GUARD || CONFIG_USERSPACE */
|
|
|
|
|
|
|
|
|
|
#if defined(CONFIG_PMP_STACK_GUARD)
|
|
|
|
|
if ((thread->base.user_options & K_USER) == 0) {
|
|
|
|
|
/* Enable pmp for machine mode if thread isn't a user*/
|
|
|
|
|
stack_init->mstatus |= MSTATUS_MPRV;
|
|
|
|
|
}
|
|
|
|
|
#endif /* CONFIG_PMP_STACK_GUARD */
|
|
|
|
|
|
2020-05-03 18:03:19 +09:00
|
|
|
#if defined(CONFIG_FPU) && defined(CONFIG_FPU_SHARING)
|
2021-05-19 02:43:13 +08:00
|
|
|
/* Shared FP mode: enable FPU of threads with K_FP_REGS. */
|
2020-03-11 18:15:29 -07:00
|
|
|
if ((thread->base.user_options & K_FP_REGS) != 0) {
|
|
|
|
|
stack_init->mstatus |= MSTATUS_FS_INIT;
|
|
|
|
|
}
|
|
|
|
|
stack_init->fp_state = 0;
|
2021-05-19 02:43:13 +08:00
|
|
|
#elif defined(CONFIG_FPU)
|
|
|
|
|
/* Unshared FP mode: enable FPU of each thread. */
|
|
|
|
|
stack_init->mstatus |= MSTATUS_FS_INIT;
|
2020-03-11 18:15:29 -07:00
|
|
|
#endif
|
2020-07-21 16:00:39 +02:00
|
|
|
|
2019-07-24 16:21:58 -04:00
|
|
|
stack_init->mepc = (ulong_t)z_thread_entry_wrapper;
|
arch: added support for the riscv32 architecture
RISC-V is an open-source instruction set architecture.
Added support for the 32bit version of RISC-V to Zephyr.
1) exceptions/interrupts/faults are handled at the architecture
level via the __irq_wrapper handler. Context saving/restoring
of registers can be handled at both architecture and SOC levels.
If SOC-specific registers need to be saved, SOC level needs to
provide __soc_save_context and __soc_restore_context functions
that shall be accounted by the architecture level, when
corresponding config variable RISCV_SOC_CONTEXT_SAVE is set.
2) As RISC-V architecture does not provide a clear ISA specification
about interrupt handling, each RISC-V SOC handles it in its own
way. Hence, at the architecture level, the __irq_wrapper handler
expects the following functions to be provided by the SOC level:
__soc_is_irq: to check if the exception is the result of an
interrupt or not.
__soc_handle_irq: handle pending IRQ at SOC level (ex: clear
pending IRQ in SOC-specific IRQ register)
3) Thread/task scheduling, as well as IRQ offloading are handled via
the RISC-V system call ("ecall"), which is also handled via the
__irq_wrapper handler. The _Swap asm function just calls "ecall"
to generate an exception.
4) As there is no conventional way of handling CPU power save in
RISC-V, the default nano_cpu_idle and nano_cpu_atomic_idle
functions just unlock interrupts and return to the caller, without
issuing any CPU power saving instruction. Nonetheless, to allow
SOC-level to implement proper CPU power save, nano_cpu_idle and
nano_cpu_atomic_idle functions are defined as __weak
at the architecture level.
Change-Id: I980a161d0009f3f404ad22b226a6229fbb492389
Signed-off-by: Jean-Paul Etienne <fractalclone@gmail.com>
2017-01-11 00:24:30 +01:00
|
|
|
|
2020-07-21 16:00:39 +02:00
|
|
|
#if defined(CONFIG_USERSPACE)
|
|
|
|
|
thread->arch.priv_stack_start = 0;
|
|
|
|
|
thread->arch.user_sp = 0;
|
|
|
|
|
if ((thread->base.user_options & K_USER) != 0) {
|
|
|
|
|
stack_init->mepc = (ulong_t)k_thread_user_mode_enter;
|
|
|
|
|
} else {
|
|
|
|
|
stack_init->mepc = (ulong_t)z_thread_entry_wrapper;
|
|
|
|
|
#if defined(CONFIG_PMP_STACK_GUARD)
|
|
|
|
|
z_riscv_init_stack_guard(thread);
|
|
|
|
|
#endif /* CONFIG_PMP_STACK_GUARD */
|
|
|
|
|
}
|
|
|
|
|
#else
|
|
|
|
|
stack_init->mepc = (ulong_t)z_thread_entry_wrapper;
|
|
|
|
|
#if defined(CONFIG_PMP_STACK_GUARD)
|
|
|
|
|
z_riscv_init_stack_guard(thread);
|
|
|
|
|
#endif /* CONFIG_PMP_STACK_GUARD */
|
|
|
|
|
#endif /* CONFIG_USERSPACE */
|
|
|
|
|
|
2020-06-07 16:10:52 +02:00
|
|
|
#ifdef CONFIG_RISCV_SOC_CONTEXT_SAVE
|
|
|
|
|
stack_init->soc_context = soc_esf_init;
|
|
|
|
|
#endif
|
|
|
|
|
|
2019-07-24 16:21:58 -04:00
|
|
|
thread->callee_saved.sp = (ulong_t)stack_init;
|
arch: added support for the riscv32 architecture
RISC-V is an open-source instruction set architecture.
Added support for the 32bit version of RISC-V to Zephyr.
1) exceptions/interrupts/faults are handled at the architecture
level via the __irq_wrapper handler. Context saving/restoring
of registers can be handled at both architecture and SOC levels.
If SOC-specific registers need to be saved, SOC level needs to
provide __soc_save_context and __soc_restore_context functions
that shall be accounted by the architecture level, when
corresponding config variable RISCV_SOC_CONTEXT_SAVE is set.
2) As RISC-V architecture does not provide a clear ISA specification
about interrupt handling, each RISC-V SOC handles it in its own
way. Hence, at the architecture level, the __irq_wrapper handler
expects the following functions to be provided by the SOC level:
__soc_is_irq: to check if the exception is the result of an
interrupt or not.
__soc_handle_irq: handle pending IRQ at SOC level (ex: clear
pending IRQ in SOC-specific IRQ register)
3) Thread/task scheduling, as well as IRQ offloading are handled via
the RISC-V system call ("ecall"), which is also handled via the
__irq_wrapper handler. The _Swap asm function just calls "ecall"
to generate an exception.
4) As there is no conventional way of handling CPU power save in
RISC-V, the default nano_cpu_idle and nano_cpu_atomic_idle
functions just unlock interrupts and return to the caller, without
issuing any CPU power saving instruction. Nonetheless, to allow
SOC-level to implement proper CPU power save, nano_cpu_idle and
nano_cpu_atomic_idle functions are defined as __weak
at the architecture level.
Change-Id: I980a161d0009f3f404ad22b226a6229fbb492389
Signed-off-by: Jean-Paul Etienne <fractalclone@gmail.com>
2017-01-11 00:24:30 +01:00
|
|
|
}
|
2020-03-11 18:15:29 -07:00
|
|
|
|
2020-05-03 18:03:19 +09:00
|
|
|
#if defined(CONFIG_FPU) && defined(CONFIG_FPU_SHARING)
|
2020-03-11 18:15:29 -07:00
|
|
|
int arch_float_disable(struct k_thread *thread)
|
|
|
|
|
{
|
|
|
|
|
unsigned int key;
|
|
|
|
|
|
|
|
|
|
if (thread != _current) {
|
|
|
|
|
return -EINVAL;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (arch_is_in_isr()) {
|
|
|
|
|
return -EINVAL;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Ensure a preemptive context switch does not occur */
|
|
|
|
|
key = irq_lock();
|
|
|
|
|
|
|
|
|
|
/* Disable all floating point capabilities for the thread */
|
|
|
|
|
thread->base.user_options &= ~K_FP_REGS;
|
|
|
|
|
|
|
|
|
|
/* Clear the FS bits to disable the FPU. */
|
|
|
|
|
__asm__ volatile (
|
|
|
|
|
"mv t0, %0\n"
|
|
|
|
|
"csrrc x0, mstatus, t0\n"
|
|
|
|
|
:
|
|
|
|
|
: "r" (MSTATUS_FS_MASK)
|
|
|
|
|
);
|
|
|
|
|
|
|
|
|
|
irq_unlock(key);
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
2021-02-01 15:16:53 +09:00
|
|
|
int arch_float_enable(struct k_thread *thread, unsigned int options)
|
2020-03-11 18:15:29 -07:00
|
|
|
{
|
|
|
|
|
unsigned int key;
|
|
|
|
|
|
|
|
|
|
if (thread != _current) {
|
|
|
|
|
return -EINVAL;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (arch_is_in_isr()) {
|
|
|
|
|
return -EINVAL;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Ensure a preemptive context switch does not occur */
|
|
|
|
|
key = irq_lock();
|
|
|
|
|
|
|
|
|
|
/* Enable all floating point capabilities for the thread. */
|
|
|
|
|
thread->base.user_options |= K_FP_REGS;
|
|
|
|
|
|
|
|
|
|
/* Set the FS bits to Initial to enable the FPU. */
|
|
|
|
|
__asm__ volatile (
|
|
|
|
|
"mv t0, %0\n"
|
|
|
|
|
"csrrs x0, mstatus, t0\n"
|
|
|
|
|
:
|
|
|
|
|
: "r" (MSTATUS_FS_INIT)
|
|
|
|
|
);
|
|
|
|
|
|
|
|
|
|
irq_unlock(key);
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
2020-05-03 18:03:19 +09:00
|
|
|
#endif /* CONFIG_FPU && CONFIG_FPU_SHARING */
|
2020-07-21 16:00:39 +02:00
|
|
|
|
|
|
|
|
#ifdef CONFIG_USERSPACE
|
|
|
|
|
|
|
|
|
|
/* Function used by Zephyr to switch a supervisor thread to a user thread */
|
|
|
|
|
FUNC_NORETURN void arch_user_mode_enter(k_thread_entry_t user_entry,
|
|
|
|
|
void *p1, void *p2, void *p3)
|
|
|
|
|
{
|
|
|
|
|
arch_syscall_invoke5((uintptr_t) arch_user_mode_enter,
|
|
|
|
|
(uintptr_t) user_entry,
|
|
|
|
|
(uintptr_t) p1,
|
|
|
|
|
(uintptr_t) p2,
|
|
|
|
|
(uintptr_t) p3,
|
|
|
|
|
FORCE_SYSCALL_ID);
|
|
|
|
|
|
|
|
|
|
CODE_UNREACHABLE;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* User space entry function
|
|
|
|
|
*
|
|
|
|
|
* This function is the entry point to user mode from privileged execution.
|
|
|
|
|
* The conversion is one way, and threads which transition to user mode do
|
|
|
|
|
* not transition back later, unless they are doing system calls.
|
|
|
|
|
*/
|
|
|
|
|
FUNC_NORETURN void z_riscv_user_mode_enter_syscall(k_thread_entry_t user_entry,
|
|
|
|
|
void *p1, void *p2, void *p3)
|
|
|
|
|
{
|
|
|
|
|
ulong_t top_of_user_stack = 0U;
|
|
|
|
|
uintptr_t status;
|
|
|
|
|
|
|
|
|
|
/* Set up privileged stack */
|
|
|
|
|
#ifdef CONFIG_GEN_PRIV_STACKS
|
|
|
|
|
_current->arch.priv_stack_start =
|
|
|
|
|
(uint32_t)z_priv_stack_find(_current->stack_obj);
|
|
|
|
|
#else
|
|
|
|
|
_current->arch.priv_stack_start =
|
|
|
|
|
(uint32_t)(_current->stack_obj) +
|
|
|
|
|
Z_RISCV_STACK_GUARD_SIZE;
|
|
|
|
|
#endif /* CONFIG_GEN_PRIV_STACKS */
|
|
|
|
|
|
|
|
|
|
top_of_user_stack = Z_STACK_PTR_ALIGN(
|
|
|
|
|
_current->stack_info.start +
|
|
|
|
|
_current->stack_info.size -
|
|
|
|
|
_current->stack_info.delta);
|
|
|
|
|
|
|
|
|
|
/* Set next CPU status to user mode */
|
|
|
|
|
status = csr_read(mstatus);
|
|
|
|
|
status = INSERT_FIELD(status, MSTATUS_MPP, PRV_U);
|
|
|
|
|
status = INSERT_FIELD(status, MSTATUS_MPRV, 0);
|
|
|
|
|
|
|
|
|
|
csr_write(mstatus, status);
|
|
|
|
|
csr_write(mepc, z_thread_entry_wrapper);
|
|
|
|
|
|
|
|
|
|
/* Set up Physical Memory Protection */
|
|
|
|
|
#if defined(CONFIG_PMP_STACK_GUARD)
|
|
|
|
|
z_riscv_init_stack_guard(_current);
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
z_riscv_init_user_accesses(_current);
|
|
|
|
|
z_riscv_configure_user_allowed_stack(_current);
|
|
|
|
|
|
|
|
|
|
is_user_mode = true;
|
|
|
|
|
|
|
|
|
|
__asm__ volatile ("mv a0, %1"
|
|
|
|
|
: "=r" (user_entry)
|
|
|
|
|
: "r" (user_entry)
|
|
|
|
|
: "memory");
|
|
|
|
|
|
|
|
|
|
__asm__ volatile ("mv a1, %1"
|
|
|
|
|
: "=r" (p1)
|
|
|
|
|
: "r" (p1)
|
|
|
|
|
: "memory");
|
|
|
|
|
|
|
|
|
|
__asm__ volatile ("mv a2, %1"
|
|
|
|
|
: "=r" (p2)
|
|
|
|
|
: "r" (p2)
|
|
|
|
|
: "memory");
|
|
|
|
|
|
|
|
|
|
__asm__ volatile ("mv a3, %1"
|
|
|
|
|
: "=r" (p3)
|
|
|
|
|
: "r" (p3)
|
|
|
|
|
: "memory");
|
|
|
|
|
|
|
|
|
|
__asm__ volatile ("mv sp, %1"
|
|
|
|
|
: "=r" (top_of_user_stack)
|
|
|
|
|
: "r" (top_of_user_stack)
|
|
|
|
|
: "memory");
|
|
|
|
|
|
|
|
|
|
__asm__ volatile ("mret");
|
|
|
|
|
|
|
|
|
|
CODE_UNREACHABLE;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
#endif /* CONFIG_USERSPACE */
|
