2018-05-21 17:47:47 -07:00
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/*
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* Copyright (c) 2018 Intel Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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2022-05-06 10:49:15 +02:00
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#include <zephyr/init.h>
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2022-10-05 16:09:51 +02:00
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#include <zephyr/kernel.h>
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2018-05-21 17:47:47 -07:00
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#include <kernel_arch_data.h>
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#include <kernel_arch_func.h>
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2022-05-06 10:49:15 +02:00
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#include <zephyr/arch/x86/msr.h>
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#include <zephyr/arch/x86/cpuid.h>
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2018-05-21 17:47:47 -07:00
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2019-02-28 15:51:56 -08:00
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/*
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* See:
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* https://software.intel.com/security-software-guidance/api-app/sites/default/files/336996-Speculative-Execution-Side-Channel-Mitigations.pdf
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*/
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2024-03-01 10:43:41 -08:00
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#if defined(CONFIG_X86_DISABLE_SSBD) || defined(CONFIG_X86_ENABLE_EXTENDED_IBRS)
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2024-07-08 17:11:10 -04:00
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int spec_ctrl_init(void)
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2018-05-21 17:47:47 -07:00
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{
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2019-02-28 15:51:56 -08:00
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2020-05-27 11:26:57 -05:00
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uint32_t enable_bits = 0U;
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2022-02-04 09:55:47 +01:00
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uint32_t cpuid7 = z_x86_cpuid_extended_features();
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2019-02-28 15:51:56 -08:00
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2024-03-01 10:43:41 -08:00
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#ifdef CONFIG_X86_DISABLE_SSBD
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2019-03-26 19:57:45 -06:00
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if ((cpuid7 & CPUID_SPEC_CTRL_SSBD) != 0U) {
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2019-06-27 10:41:58 -07:00
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enable_bits |= X86_SPEC_CTRL_MSR_SSBD;
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2019-02-28 15:51:56 -08:00
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}
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#endif
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2024-03-01 10:43:41 -08:00
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#ifdef CONFIG_X86_ENABLE_EXTENDED_IBRS
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2019-03-26 19:57:45 -06:00
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if ((cpuid7 & CPUID_SPEC_CTRL_IBRS) != 0U) {
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2019-06-27 10:41:58 -07:00
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enable_bits |= X86_SPEC_CTRL_MSR_IBRS;
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2019-02-28 15:51:56 -08:00
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}
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#endif
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2019-03-26 19:57:45 -06:00
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if (enable_bits != 0U) {
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2020-05-27 11:26:57 -05:00
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uint64_t cur = z_x86_msr_read(X86_SPEC_CTRL_MSR);
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2018-05-21 17:47:47 -07:00
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2019-06-04 12:42:01 -07:00
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z_x86_msr_write(X86_SPEC_CTRL_MSR,
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2019-02-28 15:51:56 -08:00
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cur | enable_bits);
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2018-05-21 17:47:47 -07:00
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}
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return 0;
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}
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2024-03-01 10:43:41 -08:00
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#endif /* CONFIG_X86_DISABLE_SSBD || CONFIG_X86_ENABLE_EXTENDED_IBRS */
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