2017-05-04 19:27:27 +02:00
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/*
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* Copyright (c) 2017 Justin Watson
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2019-10-25 01:04:25 +02:00
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* Copyright (c) 2019 Gerson Fernando Budke
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2017-05-04 19:27:27 +02:00
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <arm/armv7-m.dtsi>
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2017-05-21 02:47:32 +02:00
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#include <dt-bindings/i2c/i2c.h>
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2018-09-28 21:56:13 +02:00
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#include <dt-bindings/gpio/gpio.h>
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2017-05-04 19:27:27 +02:00
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2020-04-07 15:19:32 +02:00
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#include "sam4s-pinctrl.dtsi"
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2017-05-04 19:27:27 +02:00
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/ {
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2019-11-04 19:17:05 +01:00
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aliases {
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2020-04-04 17:15:59 +02:00
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watchdog0 = &wdt;
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2019-11-04 19:17:05 +01:00
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};
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2020-04-22 20:46:15 +02:00
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chosen {
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zephyr,flash-controller = &eefc;
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};
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2017-05-04 19:27:27 +02:00
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cpus {
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2017-07-15 20:57:32 +02:00
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#address-cells = <1>;
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#size-cells = <0>;
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2019-06-21 14:47:08 +02:00
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cpu0: cpu@0 {
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2017-07-15 20:57:32 +02:00
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device_type = "cpu";
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2017-05-04 19:27:27 +02:00
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compatible = "arm,cortex-m4";
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2017-07-15 20:57:32 +02:00
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reg = <0>;
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2020-04-04 19:57:10 +02:00
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#address-cells = <1>;
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#size-cells = <1>;
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mpu: mpu@e000ed90 {
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compatible = "arm,armv7m-mpu";
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reg = <0xe000ed90 0x40>;
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arm,num-mpu-regions = <8>;
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};
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2017-05-04 19:27:27 +02:00
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};
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};
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2017-06-30 01:44:38 +02:00
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soc {
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2020-04-09 15:18:27 +02:00
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sram0: memory@20100000 {
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compatible = "mmio-sram";
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};
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2020-02-20 13:36:52 +01:00
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/* Only used for HWINFO device ID */
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2020-04-04 17:15:59 +02:00
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eefc: flash-controller@400e0a00 {
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2020-02-20 13:36:52 +01:00
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compatible = "atmel,sam-flash-controller";
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label = "FLASH_CTRL";
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reg = <0x400e0a00 0x200>;
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peripheral-id = <6>;
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#address-cells = <1>;
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#size-cells = <1>;
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2020-04-09 15:18:27 +02:00
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flash0: flash@400000 {
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compatible = "soc-nv-flash";
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label = "FLASH_0";
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};
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2020-02-20 13:36:52 +01:00
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};
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2020-04-04 17:15:59 +02:00
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wdt: watchdog@400e1450 {
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2018-10-25 07:16:25 +02:00
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compatible = "atmel,sam-watchdog";
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2018-11-09 12:53:08 +01:00
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reg = <0x400e1450 0xc>;
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2018-10-25 07:16:25 +02:00
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interrupts = <4 0>;
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peripheral-id = <4>;
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label = "WATCHDOG_0";
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status = "disabled";
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};
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2020-04-04 17:15:59 +02:00
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twi0: i2c@40018000 {
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2017-05-21 02:47:32 +02:00
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compatible = "atmel,sam-i2c-twi";
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clock-frequency = <I2C_BITRATE_STANDARD>;
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reg = <0x40018000 0x128>;
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interrupts = <19 0>;
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peripheral-id = <19>;
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label = "I2C_0";
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status = "disabled";
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2019-06-19 07:20:17 +02:00
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#address-cells = <1>;
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#size-cells = <0>;
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2020-04-20 11:56:00 +02:00
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pinctrl-0 = <&pa4a_twi0_twck0 &pa3a_twi0_twd0>;
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2017-05-21 02:47:32 +02:00
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};
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2020-04-04 17:15:59 +02:00
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twi1: i2c@4001c000 {
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2017-05-21 02:47:32 +02:00
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compatible = "atmel,sam-i2c-twi";
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clock-frequency = <I2C_BITRATE_STANDARD>;
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2018-11-09 12:53:08 +01:00
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reg = <0x4001c000 0x128>;
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2017-05-21 02:47:32 +02:00
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interrupts = <20 0>;
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peripheral-id = <20>;
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label = "I2C_1";
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status = "disabled";
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2019-06-19 07:20:17 +02:00
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#address-cells = <1>;
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#size-cells = <0>;
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2020-04-20 11:56:00 +02:00
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pinctrl-0 = <&pb5a_twi1_twck1 &pb4a_twi1_twd1>;
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2017-05-21 02:47:32 +02:00
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};
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2019-10-25 01:04:25 +02:00
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spi0: spi@40008000 {
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compatible = "atmel,sam-spi";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x40008000 0x4000>;
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interrupts = <21 0>;
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peripheral-id = <21>;
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label = "SPI_0";
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status = "disabled";
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2020-04-23 13:35:10 +02:00
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pinctrl-0 = <&pa12a_spi_miso &pa13a_spi_mosi &pa14a_spi_spck>;
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2019-10-25 01:04:25 +02:00
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};
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2018-11-09 12:53:08 +01:00
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uart0: uart@400e0600 {
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2017-06-30 01:44:38 +02:00
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compatible = "atmel,sam-uart";
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2018-11-09 12:53:08 +01:00
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reg = <0x400e0600 0x200>;
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2018-02-20 06:58:07 +01:00
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interrupts = <8 1>;
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2017-10-15 15:27:47 +02:00
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peripheral-id = <8>;
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2017-06-30 01:44:38 +02:00
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status = "disabled";
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label = "UART_0";
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2020-04-07 15:19:32 +02:00
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pinctrl-0 = <&pa9a_uart0_urxd0 &pa10a_uart0_utxd0>;
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2017-06-30 01:44:38 +02:00
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};
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2018-11-09 12:53:08 +01:00
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uart1: uart@400e0800 {
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2017-06-30 01:44:38 +02:00
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compatible = "atmel,sam-uart";
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2018-11-09 12:53:08 +01:00
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reg = <0x400e0800 0x200>;
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2018-02-20 06:58:07 +01:00
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interrupts = <9 1>;
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2017-10-15 15:27:47 +02:00
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peripheral-id = <9>;
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2017-06-30 01:44:38 +02:00
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status = "disabled";
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label = "UART_1";
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2020-04-07 15:19:32 +02:00
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pinctrl-0 = <&pb2a_uart1_urxd1 &pb3a_uart1_utxd1>;
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2017-06-30 01:44:38 +02:00
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};
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usart0: usart@40024000 {
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compatible = "atmel,sam-usart";
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reg = <0x40024000 0x130>;
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2018-02-20 06:58:07 +01:00
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interrupts = <14 1>;
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2017-10-15 15:27:47 +02:00
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peripheral-id = <14>;
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2017-06-30 01:44:38 +02:00
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status = "disabled";
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label = "USART_0";
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};
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usart1: usart@40028000 {
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compatible = "atmel,sam-usart";
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reg = <0x40028000 0x130>;
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2018-02-20 06:58:07 +01:00
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interrupts = <15 1>;
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2017-10-15 15:27:47 +02:00
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peripheral-id = <15>;
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2017-06-30 01:44:38 +02:00
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status = "disabled";
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label = "USART_1";
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};
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2018-03-03 01:14:16 +01:00
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2020-04-07 18:03:09 +02:00
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pinctrl@400e0e00 {
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compatible = "atmel,sam-pinctrl";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x400e0e00 0x400e0e00 0x600>;
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pioa: gpio@400e0e00 {
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compatible = "atmel,sam-gpio";
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reg = <0x400e0e00 0x190>;
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interrupts = <11 1>;
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peripheral-id = <11>;
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label = "PORTA";
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gpio-controller;
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#gpio-cells = <2>;
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2020-04-07 21:38:04 +02:00
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#atmel,pin-cells = <2>;
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2020-04-07 18:03:09 +02:00
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};
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piob: gpio@400e1000 {
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compatible = "atmel,sam-gpio";
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reg = <0x400e1000 0x190>;
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interrupts = <12 1>;
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peripheral-id = <12>;
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label = "PORTB";
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gpio-controller;
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#gpio-cells = <2>;
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2020-04-07 21:38:04 +02:00
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#atmel,pin-cells = <2>;
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2020-04-07 18:03:09 +02:00
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};
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pioc: gpio@400e1200 {
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compatible = "atmel,sam-gpio";
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reg = <0x400e1200 0x190>;
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interrupts = <13 1>;
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peripheral-id = <13>;
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label = "PORTC";
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gpio-controller;
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#gpio-cells = <2>;
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2020-04-07 21:38:04 +02:00
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#atmel,pin-cells = <2>;
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2020-04-07 18:03:09 +02:00
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};
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2018-03-03 01:14:16 +01:00
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};
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2017-06-30 01:44:38 +02:00
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};
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2017-05-04 19:27:27 +02:00
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};
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&nvic {
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2017-06-17 13:17:34 +02:00
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arm,num-irq-priority-bits = <4>;
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2017-05-04 19:27:27 +02:00
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};
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