2017-03-08 00:56:52 +01:00
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/*
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* Copyright (c) 2017 Piotr Mienkowski
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2017-09-09 16:36:09 +02:00
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*
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2017-03-08 00:56:52 +01:00
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* SPDX-License-Identifier: Apache-2.0
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*/
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2020-04-20 12:17:09 +02:00
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#define DT_DRV_COMPAT atmel_sam_i2c_twihs
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2017-03-08 00:56:52 +01:00
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/** @file
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* @brief I2C bus (TWIHS) driver for Atmel SAM MCU family.
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*
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* Only I2C Master Mode with 7 bit addressing is currently supported.
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*/
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2017-10-24 16:42:07 +02:00
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2017-03-08 00:56:52 +01:00
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#include <errno.h>
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2019-06-26 16:33:39 +02:00
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#include <sys/__assert.h>
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2017-03-08 00:56:52 +01:00
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#include <kernel.h>
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#include <device.h>
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#include <init.h>
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#include <soc.h>
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2019-06-25 21:53:54 +02:00
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#include <drivers/i2c.h>
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2018-09-17 20:24:08 +02:00
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#define LOG_LEVEL CONFIG_I2C_LOG_LEVEL
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#include <logging/log.h>
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2018-11-02 15:17:09 +01:00
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LOG_MODULE_REGISTER(i2c_sam_twihs);
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2018-09-17 20:24:08 +02:00
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2017-10-24 16:42:07 +02:00
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#include "i2c-priv.h"
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2017-03-08 00:56:52 +01:00
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/** I2C bus speed [Hz] in Standard Mode */
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#define BUS_SPEED_STANDARD_HZ 100000U
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/** I2C bus speed [Hz] in Fast Mode */
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#define BUS_SPEED_FAST_HZ 400000U
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/** I2C bus speed [Hz] in High Speed Mode */
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#define BUS_SPEED_HIGH_HZ 3400000U
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2017-09-09 16:36:09 +02:00
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/* Maximum value of Clock Divider (CKDIV) */
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#define CKDIV_MAX 7
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2017-03-08 00:56:52 +01:00
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/* Device constant configuration parameters */
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2017-10-24 14:23:57 +02:00
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struct i2c_sam_twihs_dev_cfg {
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2017-03-08 00:56:52 +01:00
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Twihs *regs;
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void (*irq_config)(void);
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2020-05-27 18:26:57 +02:00
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uint32_t bitrate;
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2017-03-08 00:56:52 +01:00
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const struct soc_gpio_pin *pin_list;
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2020-05-27 18:26:57 +02:00
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uint8_t pin_list_size;
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uint8_t periph_id;
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uint8_t irq_id;
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2017-03-08 00:56:52 +01:00
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};
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struct twihs_msg {
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/* Buffer containing data to read or write */
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2020-05-27 18:26:57 +02:00
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uint8_t *buf;
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2017-03-08 00:56:52 +01:00
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/* Length of the buffer */
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2020-05-27 18:26:57 +02:00
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uint32_t len;
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2017-03-08 00:56:52 +01:00
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/* Index of the next byte to be read/written from/to the buffer */
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2020-05-27 18:26:57 +02:00
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uint32_t idx;
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2017-03-08 00:56:52 +01:00
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/* Value of TWIHS_SR at the end of the message */
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2020-05-27 18:26:57 +02:00
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uint32_t twihs_sr;
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2017-03-08 00:56:52 +01:00
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/* Transfer flags as defined in the i2c.h file */
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2020-05-27 18:26:57 +02:00
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uint8_t flags;
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2017-03-08 00:56:52 +01:00
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};
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/* Device run time data */
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2017-10-24 14:23:57 +02:00
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struct i2c_sam_twihs_dev_data {
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2017-03-08 00:56:52 +01:00
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struct k_sem sem;
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struct twihs_msg msg;
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};
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2020-03-09 12:49:07 +01:00
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#define DEV_NAME(dev) ((dev)->name)
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2017-03-08 00:56:52 +01:00
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#define DEV_CFG(dev) \
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2020-03-09 12:49:07 +01:00
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((const struct i2c_sam_twihs_dev_cfg *const)(dev)->config_info)
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2017-03-08 00:56:52 +01:00
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#define DEV_DATA(dev) \
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2017-10-24 14:23:57 +02:00
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((struct i2c_sam_twihs_dev_data *const)(dev)->driver_data)
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2017-03-08 00:56:52 +01:00
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2020-05-27 18:26:57 +02:00
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static int i2c_clk_set(Twihs *const twihs, uint32_t speed)
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2017-03-08 00:56:52 +01:00
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{
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2020-05-27 18:26:57 +02:00
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uint32_t ck_div = 0U;
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uint32_t cl_div;
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2017-09-09 16:36:09 +02:00
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bool div_completed = false;
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2017-03-08 00:56:52 +01:00
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2017-09-09 16:36:09 +02:00
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/* From the datasheet "TWIHS Clock Waveform Generator Register"
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* T_low = ( ( CLDIV × 2^CKDIV ) + 3 ) × T_MCK
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*/
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2017-03-08 00:56:52 +01:00
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while (!div_completed) {
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2019-03-28 21:57:54 +01:00
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cl_div = ((SOC_ATMEL_SAM_MCK_FREQ_HZ / (speed * 2U)) - 3)
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2017-03-08 00:56:52 +01:00
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/ (1 << ck_div);
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2019-03-27 02:57:45 +01:00
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if (cl_div <= 255U) {
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2017-09-09 16:36:09 +02:00
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div_completed = true;
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2017-03-08 00:56:52 +01:00
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} else {
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ck_div++;
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}
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}
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2017-09-09 16:36:09 +02:00
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if (ck_div > CKDIV_MAX) {
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2018-09-17 20:24:08 +02:00
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LOG_ERR("Failed to configure I2C clock");
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2017-09-09 16:36:09 +02:00
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return -EIO;
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}
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2017-10-24 14:23:57 +02:00
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/* Set I2C bus clock duty cycle to 50% */
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2017-09-09 16:36:09 +02:00
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twihs->TWIHS_CWGR = TWIHS_CWGR_CLDIV(cl_div) | TWIHS_CWGR_CHDIV(cl_div)
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| TWIHS_CWGR_CKDIV(ck_div);
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return 0;
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2017-03-08 00:56:52 +01:00
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}
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2020-05-27 18:26:57 +02:00
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static int i2c_sam_twihs_configure(struct device *dev, uint32_t config)
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2017-03-08 00:56:52 +01:00
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{
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2017-10-24 14:23:57 +02:00
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const struct i2c_sam_twihs_dev_cfg *const dev_cfg = DEV_CFG(dev);
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2017-03-08 00:56:52 +01:00
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Twihs *const twihs = dev_cfg->regs;
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2020-05-27 18:26:57 +02:00
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uint32_t bitrate;
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2017-09-09 16:36:09 +02:00
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int ret;
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2017-03-08 00:56:52 +01:00
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2017-07-06 18:19:23 +02:00
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if (!(config & I2C_MODE_MASTER)) {
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2018-09-17 20:24:08 +02:00
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LOG_ERR("Master Mode is not enabled");
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2017-03-08 00:56:52 +01:00
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return -EIO;
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}
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if (config & I2C_ADDR_10_BITS) {
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2018-09-17 20:24:08 +02:00
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LOG_ERR("I2C 10-bit addressing is currently not supported");
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LOG_ERR("Please submit a patch");
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2017-03-08 00:56:52 +01:00
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return -EIO;
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}
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/* Configure clock */
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2017-09-09 16:36:09 +02:00
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switch (I2C_SPEED_GET(config)) {
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2017-03-08 00:56:52 +01:00
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case I2C_SPEED_STANDARD:
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2017-09-09 16:36:09 +02:00
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bitrate = BUS_SPEED_STANDARD_HZ;
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2017-03-08 00:56:52 +01:00
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break;
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case I2C_SPEED_FAST:
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2017-09-09 16:36:09 +02:00
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bitrate = BUS_SPEED_FAST_HZ;
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2017-03-08 00:56:52 +01:00
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break;
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default:
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2018-09-17 20:24:08 +02:00
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LOG_ERR("Unsupported I2C speed value");
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2017-03-08 00:56:52 +01:00
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return -EIO;
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}
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2017-09-09 16:36:09 +02:00
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/* Setup clock waveform */
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ret = i2c_clk_set(twihs, bitrate);
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if (ret < 0) {
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return ret;
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}
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2017-03-08 00:56:52 +01:00
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/* Disable Slave Mode */
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twihs->TWIHS_CR = TWIHS_CR_SVDIS;
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/* Enable Master Mode */
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twihs->TWIHS_CR = TWIHS_CR_MSEN;
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return 0;
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}
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static void write_msg_start(Twihs *const twihs, struct twihs_msg *msg,
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2020-05-27 18:26:57 +02:00
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uint8_t daddr)
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2017-03-08 00:56:52 +01:00
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{
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2017-10-24 16:42:07 +02:00
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/* Set slave address. */
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2017-03-08 00:56:52 +01:00
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twihs->TWIHS_MMR = TWIHS_MMR_DADR(daddr);
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/* Write first data byte on I2C bus */
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twihs->TWIHS_THR = msg->buf[msg->idx++];
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2017-09-09 16:36:09 +02:00
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2017-03-08 00:56:52 +01:00
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/* Enable Transmit Ready and Transmission Completed interrupts */
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twihs->TWIHS_IER = TWIHS_IER_TXRDY | TWIHS_IER_TXCOMP | TWIHS_IER_NACK;
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}
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static void read_msg_start(Twihs *const twihs, struct twihs_msg *msg,
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2020-05-27 18:26:57 +02:00
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uint8_t daddr)
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2017-03-08 00:56:52 +01:00
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{
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2020-05-27 18:26:57 +02:00
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uint32_t twihs_cr_stop;
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2017-03-08 00:56:52 +01:00
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/* Set slave address and number of internal address bytes */
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twihs->TWIHS_MMR = TWIHS_MMR_MREAD | TWIHS_MMR_DADR(daddr);
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/* Enable Receive Ready and Transmission Completed interrupts */
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twihs->TWIHS_IER = TWIHS_IER_RXRDY | TWIHS_IER_TXCOMP | TWIHS_IER_NACK;
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/* In single data byte read the START and STOP must both be set */
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2019-03-27 02:57:45 +01:00
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twihs_cr_stop = (msg->len == 1U) ? TWIHS_CR_STOP : 0;
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2017-03-08 00:56:52 +01:00
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/* Start the transfer by sending START condition */
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twihs->TWIHS_CR = TWIHS_CR_START | twihs_cr_stop;
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}
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2017-10-24 14:23:57 +02:00
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static int i2c_sam_twihs_transfer(struct device *dev, struct i2c_msg *msgs,
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2020-05-27 18:26:57 +02:00
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uint8_t num_msgs, uint16_t addr)
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2017-03-08 00:56:52 +01:00
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{
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2017-10-24 14:23:57 +02:00
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const struct i2c_sam_twihs_dev_cfg *const dev_cfg = DEV_CFG(dev);
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struct i2c_sam_twihs_dev_data *const dev_data = DEV_DATA(dev);
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2017-03-08 00:56:52 +01:00
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Twihs *const twihs = dev_cfg->regs;
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__ASSERT_NO_MSG(msgs);
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if (!num_msgs) {
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return 0;
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}
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2017-09-09 16:36:09 +02:00
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/* Clear pending interrupts, such as NACK. */
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(void)twihs->TWIHS_SR;
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/* Set number of internal address bytes to 0, not used. */
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twihs->TWIHS_IADR = 0;
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2017-03-08 00:56:52 +01:00
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for (int i = 0; i < num_msgs; i++) {
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dev_data->msg.buf = msgs[i].buf;
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dev_data->msg.len = msgs[i].len;
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2018-11-29 20:12:22 +01:00
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dev_data->msg.idx = 0U;
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dev_data->msg.twihs_sr = 0U;
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2017-03-08 00:56:52 +01:00
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dev_data->msg.flags = msgs[i].flags;
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if ((msgs[i].flags & I2C_MSG_RW_MASK) == I2C_MSG_READ) {
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read_msg_start(twihs, &dev_data->msg, addr);
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} else {
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write_msg_start(twihs, &dev_data->msg, addr);
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}
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/* Wait for the transfer to complete */
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k_sem_take(&dev_data->sem, K_FOREVER);
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if (dev_data->msg.twihs_sr > 0) {
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2017-09-09 16:36:09 +02:00
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/* Something went wrong */
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2017-03-08 00:56:52 +01:00
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return -EIO;
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}
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}
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return 0;
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}
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2017-10-24 14:23:57 +02:00
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static void i2c_sam_twihs_isr(void *arg)
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2017-03-08 00:56:52 +01:00
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{
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struct device *dev = (struct device *)arg;
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2017-10-24 14:23:57 +02:00
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const struct i2c_sam_twihs_dev_cfg *const dev_cfg = DEV_CFG(dev);
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struct i2c_sam_twihs_dev_data *const dev_data = DEV_DATA(dev);
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2017-03-08 00:56:52 +01:00
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Twihs *const twihs = dev_cfg->regs;
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struct twihs_msg *msg = &dev_data->msg;
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2020-05-27 18:26:57 +02:00
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uint32_t isr_status;
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2017-03-08 00:56:52 +01:00
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/* Retrieve interrupt status */
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isr_status = twihs->TWIHS_SR & twihs->TWIHS_IMR;
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/* Not Acknowledged */
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if (isr_status & TWIHS_SR_NACK) {
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msg->twihs_sr = isr_status;
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2017-09-09 16:36:09 +02:00
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goto tx_comp;
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2017-03-08 00:56:52 +01:00
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}
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/* Byte received */
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if (isr_status & TWIHS_SR_RXRDY) {
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msg->buf[msg->idx++] = twihs->TWIHS_RHR;
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2019-03-27 02:57:45 +01:00
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if (msg->idx == msg->len - 1U) {
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2017-10-24 14:23:57 +02:00
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/* Send STOP condition */
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2017-03-08 00:56:52 +01:00
|
|
|
|
twihs->TWIHS_CR = TWIHS_CR_STOP;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Byte sent */
|
|
|
|
|
if (isr_status & TWIHS_SR_TXRDY) {
|
|
|
|
|
if (msg->idx == msg->len) {
|
|
|
|
|
if (msg->flags & I2C_MSG_STOP) {
|
2017-10-24 14:23:57 +02:00
|
|
|
|
/* Send STOP condition */
|
2017-03-08 00:56:52 +01:00
|
|
|
|
twihs->TWIHS_CR = TWIHS_CR_STOP;
|
|
|
|
|
/* Disable Transmit Ready interrupt */
|
|
|
|
|
twihs->TWIHS_IDR = TWIHS_IDR_TXRDY;
|
|
|
|
|
} else {
|
2017-09-09 16:36:09 +02:00
|
|
|
|
/* Transmission completed */
|
|
|
|
|
goto tx_comp;
|
2017-03-08 00:56:52 +01:00
|
|
|
|
}
|
|
|
|
|
} else {
|
|
|
|
|
twihs->TWIHS_THR = msg->buf[msg->idx++];
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
2017-09-09 16:36:09 +02:00
|
|
|
|
/* Transmission completed */
|
2017-03-08 00:56:52 +01:00
|
|
|
|
if (isr_status & TWIHS_SR_TXCOMP) {
|
2017-09-09 16:36:09 +02:00
|
|
|
|
goto tx_comp;
|
2017-03-08 00:56:52 +01:00
|
|
|
|
}
|
2017-09-09 16:36:09 +02:00
|
|
|
|
|
|
|
|
|
return;
|
|
|
|
|
|
|
|
|
|
tx_comp:
|
|
|
|
|
/* Disable all enabled interrupts */
|
|
|
|
|
twihs->TWIHS_IDR = twihs->TWIHS_IMR;
|
|
|
|
|
/* We are done */
|
|
|
|
|
k_sem_give(&dev_data->sem);
|
2017-03-08 00:56:52 +01:00
|
|
|
|
}
|
|
|
|
|
|
2017-10-24 14:23:57 +02:00
|
|
|
|
static int i2c_sam_twihs_initialize(struct device *dev)
|
2017-03-08 00:56:52 +01:00
|
|
|
|
{
|
2017-10-24 14:23:57 +02:00
|
|
|
|
const struct i2c_sam_twihs_dev_cfg *const dev_cfg = DEV_CFG(dev);
|
|
|
|
|
struct i2c_sam_twihs_dev_data *const dev_data = DEV_DATA(dev);
|
2017-03-08 00:56:52 +01:00
|
|
|
|
Twihs *const twihs = dev_cfg->regs;
|
2020-05-27 18:26:57 +02:00
|
|
|
|
uint32_t bitrate_cfg;
|
2017-09-09 16:36:09 +02:00
|
|
|
|
int ret;
|
2017-03-08 00:56:52 +01:00
|
|
|
|
|
|
|
|
|
/* Configure interrupts */
|
|
|
|
|
dev_cfg->irq_config();
|
|
|
|
|
|
|
|
|
|
/* Initialize semaphore */
|
|
|
|
|
k_sem_init(&dev_data->sem, 0, 1);
|
|
|
|
|
|
|
|
|
|
/* Connect pins to the peripheral */
|
|
|
|
|
soc_gpio_list_configure(dev_cfg->pin_list, dev_cfg->pin_list_size);
|
|
|
|
|
|
|
|
|
|
/* Enable module's clock */
|
|
|
|
|
soc_pmc_peripheral_enable(dev_cfg->periph_id);
|
|
|
|
|
|
2017-10-24 14:23:57 +02:00
|
|
|
|
/* Reset the module */
|
2017-03-08 00:56:52 +01:00
|
|
|
|
twihs->TWIHS_CR = TWIHS_CR_SWRST;
|
|
|
|
|
|
2019-03-12 22:15:42 +01:00
|
|
|
|
bitrate_cfg = i2c_map_dt_bitrate(dev_cfg->bitrate);
|
2017-10-24 16:42:07 +02:00
|
|
|
|
|
|
|
|
|
ret = i2c_sam_twihs_configure(dev, I2C_MODE_MASTER | bitrate_cfg);
|
2017-09-09 16:36:09 +02:00
|
|
|
|
if (ret < 0) {
|
2018-09-17 20:24:08 +02:00
|
|
|
|
LOG_ERR("Failed to initialize %s device", DEV_NAME(dev));
|
2017-09-09 16:36:09 +02:00
|
|
|
|
return ret;
|
2017-03-08 00:56:52 +01:00
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Enable module's IRQ */
|
|
|
|
|
irq_enable(dev_cfg->irq_id);
|
|
|
|
|
|
2018-09-17 20:24:08 +02:00
|
|
|
|
LOG_INF("Device %s initialized", DEV_NAME(dev));
|
2017-09-09 16:36:09 +02:00
|
|
|
|
|
2017-03-08 00:56:52 +01:00
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
2017-10-24 14:23:57 +02:00
|
|
|
|
static const struct i2c_driver_api i2c_sam_twihs_driver_api = {
|
|
|
|
|
.configure = i2c_sam_twihs_configure,
|
|
|
|
|
.transfer = i2c_sam_twihs_transfer,
|
2017-03-08 00:56:52 +01:00
|
|
|
|
};
|
|
|
|
|
|
2020-04-20 12:17:09 +02:00
|
|
|
|
#define I2C_TWIHS_SAM_INIT(n) \
|
2020-05-14 15:33:34 +02:00
|
|
|
|
DEVICE_DECLARE(i2c##n##_sam); \
|
2020-04-20 12:17:09 +02:00
|
|
|
|
\
|
|
|
|
|
static void i2c##n##_sam_irq_config(void) \
|
|
|
|
|
{ \
|
|
|
|
|
IRQ_CONNECT(DT_INST_IRQN(n), DT_INST_IRQ(n, priority), \
|
|
|
|
|
i2c_sam_twihs_isr, \
|
|
|
|
|
DEVICE_GET(i2c##n##_sam), 0); \
|
|
|
|
|
} \
|
|
|
|
|
\
|
|
|
|
|
static const struct soc_gpio_pin pins_twihs##n[] = \
|
|
|
|
|
{ATMEL_SAM_DT_PIN(n, 0), ATMEL_SAM_DT_PIN(n, 1)}; \
|
|
|
|
|
\
|
|
|
|
|
static const struct i2c_sam_twihs_dev_cfg i2c##n##_sam_config = {\
|
|
|
|
|
.regs = (Twihs *)DT_INST_REG_ADDR(n), \
|
|
|
|
|
.irq_config = i2c##n##_sam_irq_config, \
|
|
|
|
|
.periph_id = DT_INST_PROP(n, peripheral_id), \
|
|
|
|
|
.irq_id = DT_INST_IRQN(n), \
|
|
|
|
|
.pin_list = pins_twihs##n, \
|
|
|
|
|
.pin_list_size = ARRAY_SIZE(pins_twihs##n), \
|
|
|
|
|
.bitrate = DT_INST_PROP(n, clock_frequency), \
|
|
|
|
|
}; \
|
|
|
|
|
\
|
|
|
|
|
static struct i2c_sam_twihs_dev_data i2c##n##_sam_data; \
|
|
|
|
|
\
|
|
|
|
|
DEVICE_AND_API_INIT(i2c##n##_sam, DT_INST_LABEL(n), \
|
|
|
|
|
&i2c_sam_twihs_initialize, \
|
|
|
|
|
&i2c##n##_sam_data, &i2c##n##_sam_config, \
|
|
|
|
|
POST_KERNEL, CONFIG_I2C_INIT_PRIORITY, \
|
2020-05-07 21:09:05 +02:00
|
|
|
|
&i2c_sam_twihs_driver_api);
|
2020-04-20 12:17:09 +02:00
|
|
|
|
|
2020-05-06 20:23:07 +02:00
|
|
|
|
DT_INST_FOREACH_STATUS_OKAY(I2C_TWIHS_SAM_INIT)
|