2016-08-16 12:35:23 +02:00
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/*
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* Copyright (c) 2016 Linaro Limited.
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*
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2017-01-19 02:01:01 +01:00
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* SPDX-License-Identifier: Apache-2.0
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2016-08-16 12:35:23 +02:00
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*/
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/**
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* @file SoC configuration macros for the ARM LTD Beetle SoC.
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*
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*/
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#ifndef _ARM_BEETLE_SOC_REGS_H_
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#define _ARM_BEETLE_SOC_REGS_H_
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/* System Control Register (SYSCON) */
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struct syscon {
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/* Offset: 0x000 (r/w) remap control register */
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2020-05-27 18:26:57 +02:00
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volatile uint32_t remap;
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2016-08-16 12:35:23 +02:00
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/* Offset: 0x004 (r/w) pmu control register */
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2020-05-27 18:26:57 +02:00
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volatile uint32_t pmuctrl;
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2016-08-16 12:35:23 +02:00
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/* Offset: 0x008 (r/w) reset option register */
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2020-05-27 18:26:57 +02:00
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volatile uint32_t resetop;
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2016-08-16 12:35:23 +02:00
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/* Offset: 0x00c (r/w) emi control register */
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2020-05-27 18:26:57 +02:00
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volatile uint32_t emictrl;
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2016-08-16 12:35:23 +02:00
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/* Offset: 0x010 (r/w) reset information register */
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2020-05-27 18:26:57 +02:00
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volatile uint32_t rstinfo;
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volatile uint32_t reserved0[3];
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2016-08-16 12:35:23 +02:00
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/* Offset: 0x020 (r/w)AHB peripheral access control set */
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2020-05-27 18:26:57 +02:00
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volatile uint32_t ahbper0set;
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2016-08-16 12:35:23 +02:00
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/* Offset: 0x024 (r/w)AHB peripheral access control clear */
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2020-05-27 18:26:57 +02:00
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volatile uint32_t ahbper0clr;
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volatile uint32_t reserved1[2];
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2016-08-16 12:35:23 +02:00
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/* Offset: 0x030 (r/w)APB peripheral access control set */
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2020-05-27 18:26:57 +02:00
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volatile uint32_t apbper0set;
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2016-08-16 12:35:23 +02:00
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/* Offset: 0x034 (r/w)APB peripheral access control clear */
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2020-05-27 18:26:57 +02:00
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volatile uint32_t apbper0clr;
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volatile uint32_t reserved2[2];
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2016-08-16 12:35:23 +02:00
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/* Offset: 0x040 (r/w) main clock control register */
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2020-05-27 18:26:57 +02:00
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volatile uint32_t mainclk;
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2016-08-16 12:35:23 +02:00
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/* Offset: 0x044 (r/w) auxiliary / rtc control register */
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2020-05-27 18:26:57 +02:00
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volatile uint32_t auxclk;
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2016-08-16 12:35:23 +02:00
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/* Offset: 0x048 (r/w) pll control register */
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2020-05-27 18:26:57 +02:00
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volatile uint32_t pllctrl;
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2016-08-16 12:35:23 +02:00
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/* Offset: 0x04c (r/w) pll status register */
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2020-05-27 18:26:57 +02:00
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volatile uint32_t pllstatus;
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2016-08-16 12:35:23 +02:00
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/* Offset: 0x050 (r/w) sleep control register */
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2020-05-27 18:26:57 +02:00
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volatile uint32_t sleepcfg;
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2016-08-16 12:35:23 +02:00
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/* Offset: 0x054 (r/w) flash auxiliary settings control register */
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2020-05-27 18:26:57 +02:00
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volatile uint32_t flashauxcfg;
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volatile uint32_t reserved3[10];
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2016-08-16 12:35:23 +02:00
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/* Offset: 0x080 (r/w) AHB peripheral clock set in active state */
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2020-05-27 18:26:57 +02:00
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volatile uint32_t ahbclkcfg0set;
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2016-08-16 12:35:23 +02:00
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/* Offset: 0x084 (r/w) AHB peripheral clock clear in active state */
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2020-05-27 18:26:57 +02:00
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volatile uint32_t ahbclkcfg0clr;
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2016-08-16 12:35:23 +02:00
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/* Offset: 0x088 (r/w) AHB peripheral clock set in sleep state */
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2020-05-27 18:26:57 +02:00
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volatile uint32_t ahbclkcfg1set;
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2016-08-16 12:35:23 +02:00
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/* Offset: 0x08c (r/w) AHB peripheral clock clear in sleep state */
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2020-05-27 18:26:57 +02:00
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volatile uint32_t ahbclkcfg1clr;
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2016-08-16 12:35:23 +02:00
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/* Offset: 0x090 (r/w) AHB peripheral clock set in deep sleep state */
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2020-05-27 18:26:57 +02:00
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volatile uint32_t ahbclkcfg2set;
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2016-08-16 12:35:23 +02:00
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/* Offset: 0x094 (r/w) AHB peripheral clock clear in deep sleep state */
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2020-05-27 18:26:57 +02:00
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volatile uint32_t ahbclkcfg2clr;
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volatile uint32_t reserved4[2];
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2016-08-16 12:35:23 +02:00
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/* Offset: 0x0a0 (r/w) APB peripheral clock set in active state */
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2020-05-27 18:26:57 +02:00
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volatile uint32_t apbclkcfg0set;
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2016-08-16 12:35:23 +02:00
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/* Offset: 0x0a4 (r/w) APB peripheral clock clear in active state */
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2020-05-27 18:26:57 +02:00
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volatile uint32_t apbclkcfg0clr;
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2016-08-16 12:35:23 +02:00
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/* Offset: 0x0a8 (r/w) APB peripheral clock set in sleep state */
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2020-05-27 18:26:57 +02:00
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volatile uint32_t apbclkcfg1set;
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2016-08-16 12:35:23 +02:00
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/* Offset: 0x0ac (r/w) APB peripheral clock clear in sleep state */
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2020-05-27 18:26:57 +02:00
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volatile uint32_t apbclkcfg1clr;
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2016-08-16 12:35:23 +02:00
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/* Offset: 0x0b0 (r/w) APB peripheral clock set in deep sleep state */
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2020-05-27 18:26:57 +02:00
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volatile uint32_t apbclkcfg2set;
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2016-08-16 12:35:23 +02:00
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/* Offset: 0x0b4 (r/w) APB peripheral clock clear in deep sleep state */
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2020-05-27 18:26:57 +02:00
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volatile uint32_t apbclkcfg2clr;
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volatile uint32_t reserved5[2];
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2016-08-16 12:35:23 +02:00
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/* Offset: 0x0c0 (r/w) AHB peripheral reset select set */
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2020-05-27 18:26:57 +02:00
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volatile uint32_t ahbprst0set;
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2016-08-16 12:35:23 +02:00
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/* Offset: 0x0c4 (r/w) AHB peripheral reset select clear */
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2020-05-27 18:26:57 +02:00
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volatile uint32_t ahbprst0clr;
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2016-08-16 12:35:23 +02:00
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/* Offset: 0x0c8 (r/w) APB peripheral reset select set */
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2020-05-27 18:26:57 +02:00
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volatile uint32_t apbprst0set;
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2016-08-16 12:35:23 +02:00
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/* Offset: 0x0cc (r/w) APB peripheral reset select clear */
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2020-05-27 18:26:57 +02:00
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volatile uint32_t apbprst0clr;
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2016-08-16 12:35:23 +02:00
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/* Offset: 0x0d0 (r/w) AHB power down sleep wakeup source set */
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2020-05-27 18:26:57 +02:00
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volatile uint32_t pwrdncfg0set;
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2016-08-16 12:35:23 +02:00
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/* Offset: 0x0d4 (r/w) AHB power down sleep wakeup source clear */
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2020-05-27 18:26:57 +02:00
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volatile uint32_t pwrdncfg0clr;
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2016-08-16 12:35:23 +02:00
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/* Offset: 0x0d8 (r/w) APB power down sleep wakeup source set */
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2020-05-27 18:26:57 +02:00
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volatile uint32_t pwrdncfg1set;
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2016-08-16 12:35:23 +02:00
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/* Offset: 0x0dc (r/w) APB power down sleep wakeup source clear */
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2020-05-27 18:26:57 +02:00
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volatile uint32_t pwrdncfg1clr;
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2016-08-16 12:35:23 +02:00
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/* Offset: 0x0e0 ( /w) rtc reset */
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2020-05-27 18:26:57 +02:00
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volatile uint32_t rtcreset;
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2016-08-16 12:35:23 +02:00
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/* Offset: 0x0e4 (r/w) event interface control register */
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2020-05-27 18:26:57 +02:00
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volatile uint32_t eventcfg;
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volatile uint32_t reserved6[2];
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2022-03-16 22:07:43 +01:00
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/* Offset: 0x0f0 (r/w) sram power control override */
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2020-05-27 18:26:57 +02:00
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volatile uint32_t pwrovride0;
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2022-03-16 22:07:43 +01:00
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/* Offset: 0x0f4 (r/w) embedded flash power control override */
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2020-05-27 18:26:57 +02:00
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volatile uint32_t pwrovride1;
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2016-08-16 12:35:23 +02:00
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/* Offset: 0x0f8 (r/ ) memory status register */
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2020-05-27 18:26:57 +02:00
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volatile uint32_t memorystatus;
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volatile uint32_t reserved7[1];
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2016-08-16 12:35:23 +02:00
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/* Offset: 0x100 (r/w) io pad settings */
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2020-05-27 18:26:57 +02:00
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volatile uint32_t gpiopadcfg0;
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2016-08-16 12:35:23 +02:00
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/* Offset: 0x104 (r/w) io pad settings */
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2020-05-27 18:26:57 +02:00
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volatile uint32_t gpiopadcfg1;
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2016-08-16 12:35:23 +02:00
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/* Offset: 0x108 (r/w) testmode boot bypass */
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2020-05-27 18:26:57 +02:00
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volatile uint32_t testmodecfg;
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2016-08-16 12:35:23 +02:00
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};
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#endif /* _ARM_BEETLE_SOC_REGS_H_ */
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