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zephyr/dts/riscv/gd/gd32vf103X8.dtsi

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soc: riscv: Add initial support for GigaDevice GD32V SoC Add GigaDevice GD32V SoC. GD32V has non-standard CSR. It doesn't use common startup code. Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
2020-03-03 13:27:10 +01:00
/*
* Copyright (c) 2021 Tokita, Hiroshi <tokita.hiroshi@gmail.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <mem.h>
dts: arm/riscv: gigadevice: s/gigadevice/gd To stay consistent with other vendors, use vendor prefix (gd). Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2024-01-09 09:50:44 +01:00
#include <gd/gd32vf103.dtsi>
soc: riscv: Add initial support for GigaDevice GD32V SoC Add GigaDevice GD32V SoC. GD32V has non-standard CSR. It doesn't use common startup code. Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
2020-03-03 13:27:10 +01:00
dts: gigadevice: simplify flash/sram size assignments Make use of nodelabels to extend flash/sram nodes instead of re-defining the whole tree. This pattern is already used in some other files. Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2022-08-23 23:40:43 +02:00
&sram0 {
reg = <0x20000000 DT_SIZE_K(20)>;
};
soc: riscv: Add initial support for GigaDevice GD32V SoC Add GigaDevice GD32V SoC. GD32V has non-standard CSR. It doesn't use common startup code. Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
2020-03-03 13:27:10 +01:00
dts: gigadevice: simplify flash/sram size assignments Make use of nodelabels to extend flash/sram nodes instead of re-defining the whole tree. This pattern is already used in some other files. Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2022-08-23 23:40:43 +02:00
&flash0 {
reg = <0x08000000 DT_SIZE_K(64)>;
soc: riscv: Add initial support for GigaDevice GD32V SoC Add GigaDevice GD32V SoC. GD32V has non-standard CSR. It doesn't use common startup code. Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
2020-03-03 13:27:10 +01:00
};
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