2017-01-22 17:21:34 +01:00
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/*
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2022-02-14 22:13:07 +01:00
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* Copyright (c) 2022 Intel Corporation
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2017-01-22 17:21:34 +01:00
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* SPDX-License-Identifier: Apache-2.0
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*/
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2022-05-06 10:49:15 +02:00
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#include <zephyr/kernel.h>
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#include <zephyr/irq_offload.h>
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2024-01-24 10:35:04 +01:00
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#include <zephyr/zsr.h>
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2022-10-17 10:24:11 +02:00
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#include <zephyr/irq.h>
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2017-01-22 17:21:34 +01:00
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2022-02-14 22:13:07 +01:00
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static struct {
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irq_offload_routine_t fn;
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const void *arg;
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2022-10-12 17:55:36 +02:00
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} offload_params[CONFIG_MP_MAX_NUM_CPUS];
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2017-01-22 17:21:34 +01:00
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2022-02-14 22:13:07 +01:00
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static void irq_offload_isr(const void *param)
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2017-01-22 17:21:34 +01:00
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{
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2022-02-14 22:13:07 +01:00
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ARG_UNUSED(param);
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2023-08-18 07:06:52 +02:00
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uint8_t cpu_id = _current_cpu->id;
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offload_params[cpu_id].fn(offload_params[cpu_id].arg);
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2017-01-22 17:21:34 +01:00
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}
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2020-07-10 10:57:23 +02:00
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void arch_irq_offload(irq_offload_routine_t routine, const void *parameter)
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2017-01-22 17:21:34 +01:00
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{
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2022-02-14 22:13:07 +01:00
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IRQ_CONNECT(ZSR_IRQ_OFFLOAD_INT, 0, irq_offload_isr, NULL, 0);
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unsigned int intenable, key = arch_irq_lock();
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2023-08-18 07:06:52 +02:00
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uint8_t cpu_id = _current_cpu->id;
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2022-02-14 22:13:07 +01:00
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2023-08-18 07:06:52 +02:00
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offload_params[cpu_id].fn = routine;
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offload_params[cpu_id].arg = parameter;
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2022-02-14 22:13:07 +01:00
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__asm__ volatile("rsr %0, INTENABLE" : "=r"(intenable));
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intenable |= BIT(ZSR_IRQ_OFFLOAD_INT);
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__asm__ volatile("wsr %0, INTENABLE; wsr %0, INTSET; rsync"
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:: "r"(intenable), "r"(BIT(ZSR_IRQ_OFFLOAD_INT)));
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arch_irq_unlock(key);
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2017-01-22 17:21:34 +01:00
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}
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