fe118c4e95
Some files made it through review process with full license header. Change-Id: I2722b127c40b4b19500042c12e4fde85a165bae9 Signed-off-by: Anas Nashif <anas.nashif@intel.com>
148 lines
2.7 KiB
Text
148 lines
2.7 KiB
Text
/*
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* Copyright (c) 2016 Linaro Limited.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include "armv7-m.dtsi"
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/ {
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sram0: memory {
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reg = <0x20000000 0x18000>;
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};
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flash0: flash {
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reg = <0x08000000 0x100000>;
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};
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clocks {
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clk_hse: clk-hse {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <0>;
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};
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};
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soc {
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usart1: uart@40013800 {
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compatible = "st,stm32-usart", "st,stm32-uart";
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reg = <0x40013800 0x400>;
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interrupts = <37>;
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zephyr,irq-prio = <0>;
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baud-rate = <115200>;
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status = "disabled";
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};
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usart2: uart@40004400 {
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compatible = "st,stm32-usart", "st,stm32-uart";
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reg = <0x40004400 0x400>;
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interrupts = <38>;
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zephyr,irq-prio = <0>;
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baud-rate = <115200>;
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status = "disabled";
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};
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usart3: uart@40004800 {
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compatible = "st,stm32-usart", "st,stm32-uart";
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reg = <0x40004800 0x400>;
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interrupts = <39>;
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zephyr,irq-prio = <0>;
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baud-rate = <115200>;
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status = "disabled";
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};
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uart4: uart@40004c00 {
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compatible = "st,stm32-uart";
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reg = <0x40004c00 0x400>;
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interrupts = <52>;
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zephyr,irq-prio = <0>;
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baud-rate = <115200>;
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status = "disabled";
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};
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uart5: uart@40005000 {
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compatible = "st,stm32-uart";
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reg = <0x40005000 0x400>;
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interrupts = <53>;
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zephyr,irq-prio = <0>;
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baud-rate = <115200>;
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status = "disabled";
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};
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syscfg: system-config@40010000 {
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compatible = "syscon";
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reg = <0x40013800 0x400>;
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};
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pin-controller {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "st,stm32l4xx-pinctrl";
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ranges = <0 0x48000000 0x2000>;
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pins-are-numbered;
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gpioa: gpio@48000000 {
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x0 0x400>;
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st,bank-name = "GPIOA";
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};
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gpiob: gpio@48000400 {
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x400 0x400>;
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st,bank-name = "GPIOB";
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};
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gpioc: gpio@48000800 {
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x800 0x400>;
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st,bank-name = "GPIOC";
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};
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gpiod: gpio@48000c00 {
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0xc00 0x400>;
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st,bank-name = "GPIOD";
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};
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gpioe: gpio@48001000 {
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x1000 0x400>;
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st,bank-name = "GPIOE";
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};
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gpiof: gpio@48001400 {
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x1400 0x400>;
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st,bank-name = "GPIOF";
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};
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gpiog: gpio@48001800 {
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x1800 0x400>;
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st,bank-name = "GPIOG";
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};
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gpioh: gpio@48001c00 {
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x1c00 0x400>;
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st,bank-name = "GPIOH";
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};
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};
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};
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};
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&nvic {
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num-irq-prio-bits = <4>;
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num-irqs = <82>;
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};
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