6ef29c0250
A single menu within an if like
if FOO
menu "blah"
...
endmenu
endif
can be replaced with
menu "blah"
depends on FOO
...
endmenu
Fix up all existing instances.
Also remove redundant extra menus underneath 'menuconfig' symbols.
'menuconfig' already creates a menu.
Also remove the menu in arch/arm/core/aarch32/Kconfig around the
"Floating point ABI" choice. The choice depends on FLOAT, which depends
on CPU_HAS_CPU, so remove the 'depends on CPU_HAS_FPU' too.
Piggyback removing a redundant 'default n' for BME280.
Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
274 lines
9.4 KiB
Text
274 lines
9.4 KiB
Text
# ARM core configuration options
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# Copyright (c) 2015 Wind River Systems, Inc.
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# SPDX-License-Identifier: Apache-2.0
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config CPU_CORTEX
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bool
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help
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This option signifies the use of a CPU of the Cortex family.
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config CPU_CORTEX_M
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bool
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select CPU_CORTEX
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select ARCH_HAS_CUSTOM_SWAP_TO_MAIN
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select HAS_CMSIS_CORE
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select HAS_FLASH_LOAD_OFFSET
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select ARCH_HAS_THREAD_ABORT
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select ARCH_HAS_TRUSTED_EXECUTION if ARM_TRUSTZONE_M
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select ARCH_HAS_STACK_PROTECTION if (ARM_MPU && !ARMV6_M_ARMV8_M_BASELINE) || CPU_CORTEX_M_HAS_SPLIM
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select ARCH_HAS_USERSPACE if ARM_MPU
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select ARCH_HAS_NOCACHE_MEMORY_SUPPORT if ARM_MPU && CPU_HAS_ARM_MPU && CPU_CORTEX_M7
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select ARCH_HAS_RAMFUNC_SUPPORT
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select ARCH_HAS_NESTED_EXCEPTION_DETECTION
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select SWAP_NONATOMIC
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help
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This option signifies the use of a CPU of the Cortex-M family.
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config CPU_CORTEX_R
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bool
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select CPU_CORTEX
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select HAS_FLASH_LOAD_OFFSET
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help
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This option signifies the use of a CPU of the Cortex-R family.
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config ISA_THUMB2
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bool
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help
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From: http://www.arm.com/products/processors/technologies/instruction-set-architectures.php
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Thumb-2 technology is the instruction set underlying the ARM Cortex
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architecture which provides enhanced levels of performance, energy
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efficiency, and code density for a wide range of embedded
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applications.
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Thumb-2 technology builds on the success of Thumb, the innovative
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high code density instruction set for ARM microprocessor cores, to
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increase the power of the ARM microprocessor core available to
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developers of low cost, high performance systems.
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The technology is backwards compatible with existing ARM and Thumb
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solutions, while significantly extending the features available to
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the Thumb instructions set. This allows more of the application to
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benefit from the best in class code density of Thumb.
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For performance optimized code Thumb-2 technology uses 31 percent
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less memory to reduce system cost, while providing up to 38 percent
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higher performance than existing high density code, which can be used
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to prolong battery-life or to enrich the product feature set. Thumb-2
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technology is featured in the processor, and in all ARMv7
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architecture-based processors.
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config ISA_ARM
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bool
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help
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From: https://developer.arm.com/products/architecture/instruction-sets/a32-and-t32-instruction-sets
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A32 instructions, known as Arm instructions in pre-Armv8 architectures,
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are 32 bits wide, and are aligned on 4-byte boundaries. A32 instructions
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are supported by both A-profile and R-profile architectures.
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A32 was traditionally used in applications requiring the highest
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performance, or for handling hardware exceptions such as interrupts and
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processor start-up. Much of its functionality was subsumed into T32 with
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the introduction of Thumb-2 technology.
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config NUM_IRQS
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int
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config STACK_ALIGN_DOUBLE_WORD
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bool "Align stacks on double-words (8 octets)"
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default y
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help
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This is needed to conform to AAPCS, the procedure call standard for
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the ARM. It wastes stack space. The option also enforces alignment
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of stack upon exception entry on Cortex-M3 and Cortex-M4 (ARMv7-M).
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Note that for ARMv6-M, ARMv8-M, and Cortex-M7 MCUs stack alignment
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on exception entry is enabled by default and it is not configurable.
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config RUNTIME_NMI
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bool "Attach an NMI handler at runtime"
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select REBOOT
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help
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The kernel provides a simple NMI handler that simply hangs in a tight
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loop if triggered. This fills the requirement that there must be an
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NMI handler installed when the CPU boots. If a custom handler is
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needed, enable this option and attach it via _NmiHandlerSet().
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config PLATFORM_SPECIFIC_INIT
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bool "Enable platform (SOC) specific startup hook"
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help
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The platform specific initialization code (z_platform_init) is executed
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at the beginning of the startup code (__start).
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config FAULT_DUMP
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int "Fault dump level"
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default 2
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range 0 2
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help
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Different levels for display information when a fault occurs.
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2: The default. Display specific and verbose information. Consumes
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the most memory (long strings).
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1: Display general and short information. Consumes less memory
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(short strings).
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0: Off.
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config BUILTIN_STACK_GUARD
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bool "Thread Stack Guards based on built-in ARM stack limit checking"
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depends on CPU_CORTEX_M_HAS_SPLIM
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select THREAD_STACK_INFO
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help
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Enable Thread/Interrupt Stack Guards via built-in Stack Pointer
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limit checking. The functionality must be supported by HW.
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config ARM_STACK_PROTECTION
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bool
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default y if HW_STACK_PROTECTION
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imply BUILTIN_STACK_GUARD if CPU_CORTEX_M_HAS_SPLIM
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select MPU_STACK_GUARD if (!BUILTIN_STACK_GUARD && ARM_MPU)
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help
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This option enables either:
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- The built-in Stack Pointer limit checking, or
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- the MPU-based stack guard
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to cause a system fatal error
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if the bounds of the current process stack are overflowed.
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The two stack guard options are mutually exclusive. The
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selection of the built-in Stack Pointer limit checking is
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prioritized over the MPU-based stack guard. The developer
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still has the option to manually select the MPU-based
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stack guard, if this is desired.
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config ARM_SECURE_FIRMWARE
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bool
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depends on ARMV8_M_SE
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default y if TRUSTED_EXECUTION_SECURE
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help
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This option indicates that we are building a Zephyr image that
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is intended to execute in Secure state. The option is only
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applicable to ARMv8-M MCUs that implement the Security Extension.
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This option enables Zephyr to include code that executes in
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Secure state, as well as to exclude code that is designed to
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execute only in Non-secure state.
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Code executing in Secure state has access to both the Secure
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and Non-Secure resources of the Cortex-M MCU.
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Code executing in Non-Secure state may trigger Secure Faults,
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if Secure MCU resources are accessed from the Non-Secure state.
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Secure Faults may only be handled by code executing in Secure
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state.
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config ARM_NONSECURE_FIRMWARE
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bool
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depends on !ARM_SECURE_FIRMWARE
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depends on ARMV8_M_SE
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default y if TRUSTED_EXECUTION_NONSECURE
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help
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This option indicates that we are building a Zephyr image that
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is intended to execute in Non-Secure state. Execution of this
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image is triggered by Secure firmware that executes in Secure
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state. The option is only applicable to ARMv8-M MCUs that
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implement the Security Extension.
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This option enables Zephyr to include code that executes in
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Non-Secure state only, as well as to exclude code that is
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designed to execute only in Secure state.
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Code executing in Non-Secure state has no access to Secure
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resources of the Cortex-M MCU, and, therefore, it shall avoid
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accessing them.
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menu "ARM TrustZone Options"
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depends on ARM_SECURE_FIRMWARE || ARM_NONSECURE_FIRMWARE
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comment "Secure firmware"
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depends on ARM_SECURE_FIRMWARE
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comment "Non-secure firmware"
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depends on !ARM_SECURE_FIRMWARE
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config ARM_SECURE_BUSFAULT_HARDFAULT_NMI
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bool "BusFault, HardFault, and NMI target Secure state"
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depends on ARM_SECURE_FIRMWARE
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help
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Force NMI, HardFault, and BusFault (in Mainline ARMv8-M)
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exceptions as Secure exceptions.
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config ARM_FIRMWARE_HAS_SECURE_ENTRY_FUNCS
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bool "Secure Firmware has Secure Entry functions"
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depends on ARM_SECURE_FIRMWARE
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help
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Option indicates that ARM Secure Firmware contains
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Secure Entry functions that may be called from
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Non-Secure state. Secure Entry functions must be
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located in Non-Secure Callable memory regions.
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config ARM_NSC_REGION_BASE_ADDRESS
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hex "ARM Non-Secure Callable Region base address"
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depends on ARM_FIRMWARE_HAS_SECURE_ENTRY_FUNCS
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default 0
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help
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Start address of Non-Secure Callable section.
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Notes:
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- The default value (i.e. when the user does not configure
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the option explicitly) instructs the linker script to
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place the Non-Secure Callable section, automatically,
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inside the .text area.
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- Certain requirements/restrictions may apply regarding
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the size and the alignment of the starting address for
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a Non-Secure Callable section, depending on the available
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security attribution unit (SAU or IDAU) for a given SOC.
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config ARM_FIRMWARE_USES_SECURE_ENTRY_FUNCS
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bool "Non-Secure Firmware uses Secure Entry functions"
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depends on ARM_NONSECURE_FIRMWARE
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help
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Option indicates that ARM Non-Secure Firmware uses Secure
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Entry functions provided by the Secure Firmware. The Secure
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Firmware must be configured to provide these functions.
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config ARM_ENTRY_VENEERS_LIB_NAME
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string "Entry Veneers symbol file"
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depends on ARM_FIRMWARE_HAS_SECURE_ENTRY_FUNCS \
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|| ARM_FIRMWARE_USES_SECURE_ENTRY_FUNCS
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default "libentryveneers.a"
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help
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Library file to find the symbol table for the entry veneers.
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The library will typically come from building the Secure
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Firmware that contains secure entry functions, and allows
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the Non-Secure Firmware to call into the Secure Firmware.
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endmenu
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choice
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prompt "Floating point ABI"
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default FP_HARDABI
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depends on FLOAT
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config FP_HARDABI
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bool "Floating point Hard ABI"
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help
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This option selects the Floating point ABI in which hardware floating
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point instructions are generated and uses FPU-specific calling
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conventions
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config FP_SOFTABI
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bool "Floating point Soft ABI"
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help
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This option selects the Floating point ABI in which hardware floating
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point instructions are generated but soft-float calling conventions.
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endchoice
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source "arch/arm/core/aarch32/cortex_m/Kconfig"
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source "arch/arm/core/aarch32/cortex_r/Kconfig"
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source "arch/arm/core/aarch32/cortex_m/mpu/Kconfig"
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source "arch/arm/core/aarch32/cortex_m/tz/Kconfig"
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