fcaa259e22
NMI_INIT() is now a no-op, so remove it from all SoC code. Also remove the irq lock/unlock pattern as it was likely a cause of copy&paste when NMI_INIT() was called. Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
123 lines
3.4 KiB
C
123 lines
3.4 KiB
C
/*
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* Copyright (c) 2022 Renesas Electronics Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/init.h>
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#include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
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#include <zephyr/linker/linker-defs.h>
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#include <string.h>
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#define REMAP_ADR0_QSPI 0x2
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#define FLASH_REGION_SIZE_32M 0
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#define FLASH_REGION_SIZE_16M 1
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#define FLASH_REGION_SIZE_8M 2
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#define FLASH_REGION_SIZE_4M 3
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#define FLASH_REGION_SIZE_2M 4
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#define FLASH_REGION_SIZE_1M 5
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#define FLASH_REGION_SIZE_05M 6
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#define FLASH_REGION_SIZE_025M 7
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#if defined(CONFIG_BOOTLOADER_MCUBOOT)
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#define MAGIC 0xaabbccdd
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static uint32_t z_renesas_cache_configured;
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#endif
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void sys_arch_reboot(int type)
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{
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ARG_UNUSED(type);
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NVIC_SystemReset();
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}
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#if defined(CONFIG_BOOTLOADER_MCUBOOT)
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static void z_renesas_configure_cache(void)
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{
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uint32_t cache_start;
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uint32_t region_size;
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uint32_t reg_region_size;
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uint32_t reg_cache_len;
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if (z_renesas_cache_configured == MAGIC) {
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return;
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}
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cache_start = (uint32_t)&_vector_start;
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region_size = (uint32_t)&__rom_region_end - cache_start;
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/* Disable cache before configuring it */
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CACHE->CACHE_CTRL2_REG = 0;
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CRG_TOP->SYS_CTRL_REG &= ~CRG_TOP_SYS_CTRL_REG_CACHERAM_MUX_Msk;
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/* Disable MRM unit */
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CACHE->CACHE_MRM_CTRL_REG = 0;
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CACHE->CACHE_MRM_TINT_REG = 0;
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CACHE->CACHE_MRM_MISSES_THRES_REG = 0;
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if (region_size > MB(16)) {
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reg_region_size = FLASH_REGION_SIZE_32M;
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} else if (region_size > MB(8)) {
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reg_region_size = FLASH_REGION_SIZE_16M;
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} else if (region_size > MB(4)) {
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reg_region_size = FLASH_REGION_SIZE_8M;
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} else if (region_size > MB(2)) {
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reg_region_size = FLASH_REGION_SIZE_4M;
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} else if (region_size > MB(1)) {
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reg_region_size = FLASH_REGION_SIZE_2M;
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} else if (region_size > KB(512)) {
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reg_region_size = FLASH_REGION_SIZE_1M;
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} else if (region_size > KB(256)) {
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reg_region_size = FLASH_REGION_SIZE_05M;
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} else {
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reg_region_size = FLASH_REGION_SIZE_025M;
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}
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CACHE->CACHE_FLASH_REG =
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(cache_start >> 16) << CACHE_CACHE_FLASH_REG_FLASH_REGION_BASE_Pos |
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((cache_start & 0xffff) >> 2) << CACHE_CACHE_FLASH_REG_FLASH_REGION_OFFSET_Pos |
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reg_region_size << CACHE_CACHE_FLASH_REG_FLASH_REGION_SIZE_Pos;
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reg_cache_len = CLAMP(reg_region_size / KB(64), 0, 0x1ff);
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CACHE->CACHE_CTRL2_REG = (CACHE->CACHE_FLASH_REG & ~CACHE_CACHE_CTRL2_REG_CACHE_LEN_Msk) |
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reg_cache_len;
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/* Copy IVT from flash to start of RAM.
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* It will be remapped at 0x0 so it can be used after SW Reset
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*/
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memcpy(&_image_ram_start, &_vector_start, 0x200);
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/* Configure remapping */
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CRG_TOP->SYS_CTRL_REG = (CRG_TOP->SYS_CTRL_REG & ~CRG_TOP_SYS_CTRL_REG_REMAP_ADR0_Msk) |
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CRG_TOP_SYS_CTRL_REG_CACHERAM_MUX_Msk |
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CRG_TOP_SYS_CTRL_REG_REMAP_INTVECT_Msk |
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REMAP_ADR0_QSPI;
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z_renesas_cache_configured = MAGIC;
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/* Trigger SW Reset to apply cache configuration */
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CRG_TOP->SYS_CTRL_REG |= CRG_TOP_SYS_CTRL_REG_SW_RESET_Msk;
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}
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#endif /* CONFIG_HAS_FLASH_LOAD_OFFSET */
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void z_arm_platform_init(void)
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{
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#if defined(CONFIG_BOOTLOADER_MCUBOOT)
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z_renesas_configure_cache();
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#endif
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}
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static int renesas_da14699_init(void)
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{
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/* Freeze watchdog until configured */
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GPREG->SET_FREEZE_REG = GPREG_SET_FREEZE_REG_FRZ_SYS_WDOG_Msk;
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/* Reset clock dividers to 0 */
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CRG_TOP->CLK_AMBA_REG &= ~(CRG_TOP_CLK_AMBA_REG_HCLK_DIV_Msk |
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CRG_TOP_CLK_AMBA_REG_PCLK_DIV_Msk);
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/* Enable all power domains except for radio */
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CRG_TOP->PMU_CTRL_REG = 0x02;
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return 0;
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}
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SYS_INIT(renesas_da14699_init, PRE_KERNEL_1, 0);
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