fb9b3bcd93
In order to bring consistency in-tree, migrate all includes within include directory to the new prefix <zephyr/...>. Note that the conversion has been scripted, refer to zephyrproject-rtos#45388 for more details. Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
131 lines
3 KiB
C
131 lines
3 KiB
C
/*
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* Copyright (c) 2016 Cadence Design Systems, Inc.
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_INCLUDE_ARCH_XTENSA_XTENSA_IRQ_H_
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#define ZEPHYR_INCLUDE_ARCH_XTENSA_XTENSA_IRQ_H_
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#include <zephyr/toolchain.h>
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#include <xtensa/config/core-isa.h>
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#define CONFIG_GEN_IRQ_START_VECTOR 0
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/*
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* Call this function to enable the specified interrupts.
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*
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* mask - Bit mask of interrupts to be enabled.
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*/
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static inline void z_xt_ints_on(unsigned int mask)
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{
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int val;
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__asm__ volatile("rsr.intenable %0" : "=r"(val));
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val |= mask;
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__asm__ volatile("wsr.intenable %0; rsync" : : "r"(val));
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}
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/*
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* Call this function to disable the specified interrupts.
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*
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* mask - Bit mask of interrupts to be disabled.
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*/
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static inline void z_xt_ints_off(unsigned int mask)
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{
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int val;
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__asm__ volatile("rsr.intenable %0" : "=r"(val));
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val &= ~mask;
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__asm__ volatile("wsr.intenable %0; rsync" : : "r"(val));
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}
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/*
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* Call this function to set the specified (s/w) interrupt.
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*/
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static inline void z_xt_set_intset(unsigned int arg)
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{
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#if XCHAL_HAVE_INTERRUPTS
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__asm__ volatile("wsr.intset %0; rsync" : : "r"(arg));
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#else
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ARG_UNUSED(arg);
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#endif
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}
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#ifdef CONFIG_MULTI_LEVEL_INTERRUPTS
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/* for _soc_irq_*() */
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#include <soc.h>
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#ifdef CONFIG_2ND_LEVEL_INTERRUPTS
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#ifdef CONFIG_3RD_LEVEL_INTERRUPTS
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#define CONFIG_NUM_IRQS (XCHAL_NUM_INTERRUPTS +\
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(CONFIG_NUM_2ND_LEVEL_AGGREGATORS +\
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CONFIG_NUM_3RD_LEVEL_AGGREGATORS) *\
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CONFIG_MAX_IRQ_PER_AGGREGATOR)
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#else
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#define CONFIG_NUM_IRQS (XCHAL_NUM_INTERRUPTS +\
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CONFIG_NUM_2ND_LEVEL_AGGREGATORS *\
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CONFIG_MAX_IRQ_PER_AGGREGATOR)
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#endif
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#else
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#define CONFIG_NUM_IRQS XCHAL_NUM_INTERRUPTS
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#endif
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#define arch_irq_enable(irq) z_soc_irq_enable(irq)
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#define arch_irq_disable(irq) z_soc_irq_disable(irq)
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#define arch_irq_is_enabled(irq) z_soc_irq_is_enabled(irq)
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#ifdef CONFIG_DYNAMIC_INTERRUPTS
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extern int z_soc_irq_connect_dynamic(unsigned int irq, unsigned int priority,
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void (*routine)(const void *parameter),
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const void *parameter, uint32_t flags);
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#endif
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#else
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#define CONFIG_NUM_IRQS XCHAL_NUM_INTERRUPTS
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#define arch_irq_enable(irq) z_xtensa_irq_enable(irq)
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#define arch_irq_disable(irq) z_xtensa_irq_disable(irq)
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#define arch_irq_is_enabled(irq) z_xtensa_irq_is_enabled(irq)
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#endif
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static ALWAYS_INLINE void z_xtensa_irq_enable(uint32_t irq)
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{
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z_xt_ints_on(1 << irq);
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}
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static ALWAYS_INLINE void z_xtensa_irq_disable(uint32_t irq)
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{
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z_xt_ints_off(1 << irq);
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}
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static ALWAYS_INLINE unsigned int arch_irq_lock(void)
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{
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unsigned int key;
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__asm__ volatile("rsil %0, %1"
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: "=r"(key) : "i"(XCHAL_EXCM_LEVEL) : "memory");
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return key;
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}
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static ALWAYS_INLINE void arch_irq_unlock(unsigned int key)
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{
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__asm__ volatile("wsr.ps %0; rsync"
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:: "r"(key) : "memory");
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}
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static ALWAYS_INLINE bool arch_irq_unlocked(unsigned int key)
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{
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return (key & 0xf) == 0; /* INTLEVEL field */
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}
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extern int z_xtensa_irq_is_enabled(unsigned int irq);
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#include <zephyr/irq.h>
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#endif /* ZEPHYR_INCLUDE_ARCH_XTENSA_XTENSA_IRQ_H_ */
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