Do not clock the LPC55xxx cores from PLL1 when CONFIG_FLASH is set. This
is required due to the following limitation of the flash controller
(documented in the reference manual):
Flash operations (erase, blank check, program) and reading a single word
can only be performed for CPU frequencies of up to 100 MHz. These
operations cannot be performed for frequencies above 100 MHz.
The PLL1 clock source will result in a core clock of 150MHz, which
violates this requirement.
Fixes#62963
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
faf5593272