Peter A. Bigot 7c15bae470 dts: riscv32-fe310: cleanup and correct plic register space ... Use zero-padded 32-bit hex constants for the start address and length so the fields are easier to compare. Correct the span of the priority/claim region. Signed-off-by: Peter A. Bigot <pab@pabigot.com>		2020-03-26 11:11:02 -05:00
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arc	boards: em_starterkit: cleanup dts warnings	2020-02-05 17:10:54 -05:00
arm	drivers: serial: uart_pl011: remove shared irq support	2020-03-25 08:34:40 -05:00
bindings	dts: ipm: add binding for intel,cavs-idc	2020-03-25 19:07:28 -04:00
common	dts: introduce macro's to help with changing unit-addr	2020-02-05 17:10:54 -05:00
nios2	driver: uart: ns16550: convert to DT_INST_*	2020-03-14 02:22:05 +02:00
posix	dts: posix: Add DTS support for POSIX architecture	2019-05-28 21:14:19 -04:00
riscv	dts: riscv32-fe310: cleanup and correct plic register space	2020-03-26 11:11:02 -05:00
x86	x86: apollo_lake: correct NW GPIO controller offset and span	2020-02-05 12:00:36 +01:00
xtensa	soc: intel_apl_adsp: add multi-processing support	2020-03-25 19:07:28 -04:00
binding-template.yaml	dts: fix up type comments in binding-template.yaml	2020-02-13 02:14:34 -06:00
Kconfig	dts/Kconfig: Remove symbol HAS_DTC_USB	2019-09-12 08:16:42 -05:00