f91b4dbe94
Convert driver to use DT_INST_ defines. The preferred defines for drivers are DT_INST_. Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
90 lines
3.5 KiB
C
90 lines
3.5 KiB
C
/* SPDX-License-Identifier: Apache-2.0 */
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/* SoC level DTS fixup file */
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#define DT_CPU_CLOCK_FREQUENCY DT_CADENCE_TENSILICA_XTENSA_LX6_0_CLOCK_FREQUENCY
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#define DT_UART_NS16550_PORT_0_BASE_ADDR DT_NS16550_80800_BASE_ADDRESS
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#define DT_UART_NS16550_PORT_0_BAUD_RATE DT_NS16550_80800_CURRENT_SPEED
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#define DT_UART_NS16550_PORT_0_NAME DT_NS16550_80800_LABEL
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#define DT_UART_NS16550_PORT_0_IRQ DT_NS16550_80800_IRQ_0
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#define DT_UART_NS16550_PORT_0_IRQ_PRI DT_NS16550_80800_IRQ_0_PRIORITY
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#define DT_UART_NS16550_PORT_0_IRQ_FLAGS DT_NS16550_80800_IRQ_0_SENSE
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#define DT_UART_NS16550_PORT_0_CLK_FREQ DT_NS16550_80800_CLOCK_FREQUENCY
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#define DT_L2_SRAM_BASE CONFIG_SRAM_BASE_ADDRESS
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#define DT_L2_SRAM_SIZE CONFIG_SRAM_SIZE * 1024
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#define DT_LP_SRAM_BASE DT_INST_1_MMIO_SRAM_BASE_ADDRESS
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#define DT_LP_SRAM_SIZE DT_INST_1_MMIO_SRAM_SIZE
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#define DT_CAVS_ICTL_BASE_ADDR DT_INTEL_CAVS_INTC_78800_BASE_ADDRESS
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#define DT_CAVS_ICTL_0_IRQ DT_INTEL_CAVS_INTC_78800_IRQ_0
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#define DT_CAVS_ICTL_0_IRQ_PRI DT_INTEL_CAVS_INTC_78800_IRQ_0_PRIORITY
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#define DT_CAVS_ICTL_0_IRQ_FLAGS DT_INTEL_CAVS_INTC_78800_IRQ_0_SENSE
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#define DT_CAVS_ICTL_1_IRQ DT_INTEL_CAVS_INTC_78810_IRQ_0
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#define DT_CAVS_ICTL_1_IRQ_PRI DT_INTEL_CAVS_INTC_78810_IRQ_0_PRIORITY
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#define DT_CAVS_ICTL_1_IRQ_FLAGS DT_INTEL_CAVS_INTC_78810_IRQ_0_SENSE
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#define DT_CAVS_ICTL_2_IRQ DT_INTEL_CAVS_INTC_78820_IRQ_0
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#define DT_CAVS_ICTL_2_IRQ_PRI DT_INTEL_CAVS_INTC_78820_IRQ_0_PRIORITY
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#define DT_CAVS_ICTL_2_IRQ_FLAGS DT_INTEL_CAVS_INTC_78820_IRQ_0_SENSE
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#define DT_CAVS_ICTL_3_IRQ DT_INTEL_CAVS_INTC_78830_IRQ_0
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#define DT_CAVS_ICTL_3_IRQ_PRI DT_INTEL_CAVS_INTC_78830_IRQ_0_PRIORITY
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#define DT_CAVS_ICTL_3_IRQ_FLAGS DT_INTEL_CAVS_INTC_78830_IRQ_0_SENSE
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#define DT_INTC_DW_0_BASE_ADDR \
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DT_SNPS_DESIGNWARE_INTC_81800_BASE_ADDRESS
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#define DT_INTC_DW_0_NAME DT_SNPS_DESIGNWARE_INTC_81800_LABEL
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#define DT_INTC_DW_0_IRQ DT_SNPS_DESIGNWARE_INTC_81800_IRQ_0
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#define DT_INTC_DW_0_IRQ_PRI \
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DT_SNPS_DESIGNWARE_INTC_81800_IRQ_0_PRIORITY
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#define DT_INTC_DW_0_IRQ_FLAGS \
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DT_SNPS_DESIGNWARE_INTC_81800_IRQ_0_SENSE
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#define DT_INTC_DW_0_NUM_IRQS DT_SNPS_DESIGNWARE_INTC_81800_NUM_IRQS
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#define DT_SPI_DW_0_BASE_ADDRESS \
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DT_SNPS_DESIGNWARE_SPI_E000_BASE_ADDRESS
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#define DT_SPI_DW_0_CLOCK_FREQUENCY \
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DT_SNPS_DESIGNWARE_SPI_E000_CLOCKS_CLOCK_FREQUENCY
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#define DT_SPI_DW_0_NAME \
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DT_SNPS_DESIGNWARE_SPI_E000_LABEL
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#define DT_SPI_DW_0_IRQ \
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DT_SNPS_DESIGNWARE_SPI_E000_IRQ_0
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#define DT_SPI_DW_0_IRQ_FLAGS \
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DT_SNPS_DESIGNWARE_SPI_E000_IRQ_0_SENSE
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#define DT_SPI_DW_0_IRQ_PRI \
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DT_SNPS_DESIGNWARE_SPI_E000_IRQ_0_PRIORITY
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#define DT_GPIO_DW_0_BASE_ADDR \
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DT_SNPS_DESIGNWARE_GPIO_80C00_BASE_ADDRESS
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#define DT_GPIO_DW_0_BITS \
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DT_SNPS_DESIGNWARE_GPIO_80C00_BITS
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#define DT_GPIO_DW_0_IRQ \
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DT_SNPS_DESIGNWARE_GPIO_80C00_IRQ_0
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#define CONFIG_GPIO_DW_0_IRQ_PRI \
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DT_SNPS_DESIGNWARE_GPIO_80C00_IRQ_0_PRIORITY
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#define DT_GPIO_DW_0_IRQ_FLAGS 0
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#define CONFIG_GPIO_DW_0_NAME \
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DT_SNPS_DESIGNWARE_GPIO_80C00_LABEL
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#define DT_PINMUX_BASE_ADDR \
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DT_INTEL_S1000_PINMUX_81C30_BASE_ADDRESS
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#define DT_PINMUX_CTRL_REG_COUNT \
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(DT_INTEL_S1000_PINMUX_81C30_SIZE / 4)
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/*
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* USB configuration
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*/
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#define DT_USB_DW_0_BASE_ADDRESS \
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DT_SNPS_DESIGNWARE_USB_A0000_BASE_ADDRESS
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#define DT_USB_DW_0_NAME DT_SNPS_DESIGNWARE_USB_A0000_LABEL
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#define DT_USB_DW_0_IRQ DT_SNPS_DESIGNWARE_USB_A0000_IRQ_0
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#define DT_USB_DW_0_IRQ_PRI \
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DT_SNPS_DESIGNWARE_USB_A0000_IRQ_0_PRIORITY
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#define DT_USB_DW_0_IRQ_FLAGS \
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DT_SNPS_DESIGNWARE_USB_A0000_IRQ_0_SENSE
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/* End of SoC Level DTS fixup file */
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