51eaf02626
The original commit uses the incorrect value 42 for CONFIG_MAX_IRQ_PER_AGGREGATOR for the cva6 family of SoCs, which is the total number of IRQs in the system. This commit corrects this to 30, the number of IRQs for the PLIC. Signed-off-by: Eric Ackermann <eric.ackermann@cispa.de>
45 lines
859 B
Text
45 lines
859 B
Text
# Copyright (c) 2024 CISPA Helmholtz Center for Information Security gGmbH
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# SPDX-License-Identifier: Apache-2.0
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if SOC_FAMILY_OPENHWGROUP_CVA6
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config SYS_CLOCK_HW_CYCLES_PER_SEC
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int
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default $(dt_node_int_prop_int,/cpus/cpu@0,timebase-frequency)
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config RISCV_SOC_INTERRUPT_INIT
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default y
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# highest implemented first-level interrupt is machine external, 11
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config 2ND_LVL_ISR_TBL_OFFSET
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default 12
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config 2ND_LVL_INTR_00_OFFSET
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default 11
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# 12 first level, 30 second level
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config MAX_IRQ_PER_AGGREGATOR
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default 30
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# one 2nd level aggregator (PLIC) with 30 interrupts
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# offset of 12
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config NUM_IRQS
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default 42
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config MULTI_LEVEL_INTERRUPTS
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default y
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config 2ND_LEVEL_INTERRUPTS
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default y
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# 1 PLIC
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config NUM_2ND_LEVEL_AGGREGATORS
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default 1
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config PLIC
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default y
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config 3RD_LEVEL_INTERRUPTS
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default n
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endif # SOC_FAMILY_OPENHWGROUP_CVA6
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