zephyr/arch/xtensa
Daniel Leung d31ee53b60 xtensa: allow flushing auto-refill DTLBs on page table swap
This adds a new kconfig and corresponding code to allow flushing
auto-refill data TLBs when page tables are swapped (e.g. during
context switching). This is mainly used to avoid multi-hit TLB
exception raised by certain memory access pattern. If memory is
only marked for user mode access but not inside a memory domain,
accessing that page in kernel mode would result in a TLB being
filled with kernel ASID. When going back into user mode, access
to the memory would result in another TLB being filled with
the user mode ASID. Now there are two entries on the same memory
page, and the multi-hit TLB exception will be raised if that
memory page is accessed. This type of access is better served
using memory partition and memory domain to share data. However,
this type of access is not prohibited but highly discouraged.
Wrapping the code in kconfig is simply because of the execution
penalty as there will be unnecessary TLB refilling being done.
So only enable this if necessary.

Fixes #88772

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2025-05-28 20:01:58 +02:00
..
core xtensa: allow flushing auto-refill DTLBs on page table swap 2025-05-28 20:01:58 +02:00
include xtensa: allow flushing auto-refill DTLBs on page table swap 2025-05-28 20:01:58 +02:00
CMakeLists.txt xtensa: fix typo userpsace to userspace 2024-10-08 18:10:03 -04:00
Kconfig xtensa: allow flushing auto-refill DTLBs on page table swap 2025-05-28 20:01:58 +02:00